LLVM/project fbed673mlir/include/mlir/Dialect/AMDGPU/IR AMDGPUOps.td, mlir/test/Conversion/AMDGPUToROCDL gfx1250.mlir

[mlir][amdgpu] Update TDM ops to use the new barrier type, improve docs (#180572)

Now that we have an AMDGPU dialect type for the in-LDS barriers that the
tensor data mover can automatically visit, update the definition of the
tensor descriptor operations to use said types and document the behavior
of the barrier.
DeltaFile
+4-4mlir/test/Dialect/AMDGPU/ops.mlir
+3-2mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
+2-2mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
+2-2mlir/test/Dialect/AMDGPU/invalid.mlir
+11-104 files

LLVM/project cba0e6amlir/include/mlir/Dialect/AMDGPU/IR AMDGPUTypes.td, mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp

[mlir][AMDGPU] Change width of LDS barrier count (#180554)

Whoops, turns out I was off by 1 on how many bits are in the counts and
phases ind these new LDS barriers. This commit fixes this.

Co-authored-by: Claude Opus 4.5 <noreply at anthropic.com>
DeltaFile
+6-6mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
+3-3mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+2-2mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUTypes.td
+11-113 files

FreeBSD/doc f27d5acdocumentation/content/en/books/porters-handbook/makefiles _index.adoc

porters-handbook: add the Budgie virtual category

PR:             293065
Submitted by:   wosch
DeltaFile
+4-0documentation/content/en/books/porters-handbook/makefiles/_index.adoc
+4-01 files

LLVM/project 470c5camlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

[MLIR][XeGPU] Fix insert_strided_slice op in subgroup distribution (#180604)

The PR modifies the subgroup distribution pass to only sink
insert_strided_slice operation if it becomes the last op before yield.
It avoids sinking insert_strided_slice multiple times and cause
potential issue in worst case.
DeltaFile
+5-2mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+5-21 files

FreeNAS/freenas 5a3379esrc/middlewared/middlewared/common/attachment __init__.py, src/middlewared/middlewared/plugins filesystem.py

start
DeltaFile
+112-68src/middlewared/middlewared/service/base.py
+63-51src/middlewared/middlewared/common/attachment/__init__.py
+84-21src/middlewared/middlewared/plugins/pool_/dataset_attachments.py
+26-12src/middlewared/middlewared/service/sharing_service.py
+8-1src/middlewared/middlewared/plugins/filesystem.py
+4-3src/middlewared/middlewared/plugins/pool_/info.py
+297-1564 files not shown
+304-16010 files

FreeNAS/freenas 0c216c5src/middlewared pyproject.toml, src/middlewared/middlewared/utils/nss pwd.py grp.py

account utils type hints
DeltaFile
+59-32src/middlewared/middlewared/utils/nss/pwd.py
+51-28src/middlewared/middlewared/utils/nss/grp.py
+1-1src/middlewared/pyproject.toml
+111-613 files

LLVM/project 4136d3fllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 inline-asm-nop-reg.ll

[AArch64] Inline asm v0-v31 are scalar when having less than 64-bit capacity (#169930)

If 32-bit (or less) "v0" registers coming from inline asm are treated as
vector ones, codegen might produce incorrect vector<->scalar
conversions. This causes types mismatch assertion failures later during
compile-time. The fix treats 32-bit or less v0-v31 AArch64 registers as
scalar, along with 64-bit ones.

Fixes #153442
DeltaFile
+166-0llvm/test/CodeGen/AArch64/inline-asm-nop-reg.ll
+22-4llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+188-42 files

LLVM/project 8418c41clang/lib/CodeGen CGDecl.cpp, clang/test/CodeGenCXX exceptions-seh.cpp

[WinEH] Check object unwinding in seh block only when -eha is used (#180108)

After this [PR](https://github.com/llvm/llvm-project/pull/172287), build
errors may occur even when `/EHa` is not enabled(like use `/EHsc`).

While MSVC performs similar checks whenever exceptions are enabled, LLVM
is more prone to generating invalid code where SEH fails to function
correctly when asyn exceptions(`/EHa`) are not used. Valid SEH code
generation is typically only ensured when `/EHa` are enabled. Therefore,
this patch is designed to perform the check only when `/EHa` is used.

Of course, on Windows, if LLVM doesn't use `/EHa` but uses `/EHsc` or
`/EHs` instead the code within the `__except` block may behave
unexpectedly, it unlike msvc. This is consistent with previous LLVM
versions.
DeltaFile
+9-0clang/test/CodeGenCXX/exceptions-seh.cpp
+2-2clang/lib/CodeGen/CGDecl.cpp
+11-22 files

FreeNAS/freenas 8e61d18src/middlewared pyproject.toml, src/middlewared/middlewared/plugins auth.py

account utils type hints
DeltaFile
+62-34src/middlewared/middlewared/utils/account/authenticator.py
+59-32src/middlewared/middlewared/utils/nss/pwd.py
+51-28src/middlewared/middlewared/utils/nss/grp.py
+34-24src/middlewared/middlewared/utils/account/utmp.py
+2-2src/middlewared/middlewared/plugins/auth.py
+1-1src/middlewared/pyproject.toml
+209-1212 files not shown
+211-1238 files

LLVM/project 61f9f1aclang/include/clang/Analysis/Analyses/LifetimeSafety Loans.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp Checker.cpp

Field and interior paths
DeltaFile
+174-101clang/unittests/Analysis/LifetimeSafetyTest.cpp
+147-98clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h
+110-46clang/test/Sema/warn-lifetime-safety-invalidations.cpp
+42-46clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+42-42clang/test/Sema/warn-lifetime-safety-dataflow.cpp
+28-48clang/lib/Analysis/LifetimeSafety/Checker.cpp
+543-3818 files not shown
+723-45614 files

LLVM/project 31da3b1clang/include/clang/Analysis/Analyses/LifetimeSafety Loans.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp Checker.cpp

Field and interior paths
DeltaFile
+174-101clang/unittests/Analysis/LifetimeSafetyTest.cpp
+147-98clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h
+110-46clang/test/Sema/warn-lifetime-safety-invalidations.cpp
+42-46clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+42-42clang/test/Sema/warn-lifetime-safety-dataflow.cpp
+28-48clang/lib/Analysis/LifetimeSafety/Checker.cpp
+543-3818 files not shown
+723-44814 files

LLVM/project cd44918clang/test/CodeGenHLSL ArrayAssignable.hlsl BoolVector.hlsl, clang/test/CodeGenHLSL/resources cbuffer_geps.hlsl

[DirectX] Specify element-aligned vectors

Use the new "ve" Data Layout specifier to indicate that vectors are
element-aligned for the target.
DeltaFile
+20-20llvm/test/CodeGen/DirectX/MemIntrinsics/memcpy-pointee.ll
+8-8llvm/test/CodeGen/DirectX/MemIntrinsics/memcpy-struct.ll
+5-5clang/test/CodeGenHLSL/resources/cbuffer_geps.hlsl
+4-4clang/test/CodeGenHLSL/ArrayAssignable.hlsl
+2-2clang/test/CodeGenHLSL/BoolVector.hlsl
+2-2clang/test/CodeGenHLSL/semantics/semantic.array.hlsl
+41-419 files not shown
+53-5415 files

LLVM/project 1266770llvm/docs LangRef.rst, llvm/include/llvm/IR DataLayout.h

[DataLayout] Add a specifier for element-aligned vectors

This adds the "ve" specifier to Data Layout, which says that vectors are
element-aligned by default for a target.

Note that we also remove the default vector specs for 64 and 128 bit
vectors - these match the natural alignment of those vectors, so they
didn't actually have any functional effect.
DeltaFile
+49-8llvm/unittests/IR/DataLayoutTest.cpp
+11-6llvm/lib/IR/DataLayout.cpp
+4-0llvm/include/llvm/IR/DataLayout.h
+3-0llvm/docs/LangRef.rst
+67-144 files

LLVM/project 8ee6c63flang-rt/lib/runtime CMakeLists.txt

[offload][flang-rt] Fix NVPTX runtime build (#180530)

During the check for availability of `strerror_r`, the host include file is used. This doesn't matter for AMDGPU since it actually performs the link step during `check_cxx_symbol_exists`. But for NVPTX, due to `-c`, it doesn't link and then incorrectly assumes that the symbol exists.
For now, removing `io-error.cpp` from the list of GPU sources is the most sensible option since it's unused.
DeltaFile
+0-1flang-rt/lib/runtime/CMakeLists.txt
+0-11 files

FreeNAS/freenas d4d00bfsrc/middlewared/middlewared/plugins/directoryservices_ util_cache.py

Skip cache insertion if we don't have a name

Seen in QE AD domain that is not fully stable or predicable, but
not in other domains in our org or customer sites, it's possible
that AD response for query to resolve SID to name may return
empty string. Because of intervening caching layers in NSS plugin
and winbindd, we don't have an effective way to force AD to keep
trying till it gives us something sane. In this case, we'll just
ignore the entry for cache insertion purposes. The user or
group won't appear in dropdowns, but functional impact will be
limited since admins can still type in the name (hopefully) and
recover at a future point.
DeltaFile
+14-0src/middlewared/middlewared/plugins/directoryservices_/util_cache.py
+14-01 files

Illumos/gate 522e050usr/src/boot Makefile.version, usr/src/boot/efi/loader/arch/amd64 trap.c

14733 loader.efi: faults could try to print out call trace
Reviewed by: Garrett D'Amore <garrett at damore.org>
Reviewed by: Robert Mustacchi <rm+illumos at fingolfin.org>
Approved by: Dan McDonald <danmcd at edgecast.io>
DeltaFile
+36-0usr/src/boot/efi/loader/arch/amd64/trap.c
+1-1usr/src/boot/Makefile.version
+37-12 files

FreeBSD/doc 41695c6website/content/ru/releases/15.0R errata.adoc

website/ru: Update releases/15.0R/errata.adoc

Sync to EN cc6854009d75e97baa24f212d46765a3679d0713
DeltaFile
+11-11website/content/ru/releases/15.0R/errata.adoc
+11-111 files

LLVM/project 2e34fecllvm/lib/Transforms/IPO IPO.cpp BarrierNoopPass.cpp

[NFC][LLVM][IPO] Remove pass initialization from pass constructors (#180584)

DeltaFile
+3-2llvm/lib/Transforms/IPO/IPO.cpp
+1-3llvm/lib/Transforms/IPO/BarrierNoopPass.cpp
+1-3llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp
+1-3llvm/lib/Transforms/IPO/GlobalDCE.cpp
+1-3llvm/lib/Transforms/IPO/LoopExtractor.cpp
+1-3llvm/lib/Transforms/IPO/AlwaysInliner.cpp
+8-172 files not shown
+10-178 files

LLVM/project 62d018blld/ELF/Arch Hexagon.cpp, lld/test/ELF hexagon-tls-ie.s

[lld][Hexagon] Fix R_HEX_TPREL_11_X relocation on duplex instructions (#179860)

findMaskR11() was missing handling for duplex instructions. This caused
incorrect encoding when R_HEX_TPREL_11_X relocations were applied to
duplex instructions with large TLS offsets.

For duplex instructions, the immediate bits are located at positions
20-25 (mask 0x03f00000), not in the standard positions used for
non-duplex instructions.

This fix adds the isDuplex() check to findMaskR11() to return the
correct mask for duplex instruction encodings.
DeltaFile
+35-1lld/test/ELF/hexagon-tls-ie.s
+2-0lld/ELF/Arch/Hexagon.cpp
+37-12 files

LLVM/project 55d75d2lldb/source/Commands Options.td

[lldb][NFC] Fix typo in memory read help text (#180301)

rdar://168081328
DeltaFile
+1-1lldb/source/Commands/Options.td
+1-11 files

OpenBSD/ports 6ZIFsxTx11/brewtarget distinfo Makefile

   Update to brewtarget 5.0.3.
VersionDeltaFile
1.8+2-2x11/brewtarget/distinfo
1.9+1-1x11/brewtarget/Makefile
+3-32 files

NetBSD/pkgsrc-wip bf8c2f8powerdns-recursor distinfo cargo-depends.mk, powerdns-recursor/files pdns_recursor.sh

net/powerdns-recursor: Update to version 5.3.5
DeltaFile
+287-0powerdns-recursor/distinfo
+96-0powerdns-recursor/cargo-depends.mk
+52-0powerdns-recursor/Makefile
+30-0powerdns-recursor/files/smf/manifest.xml
+24-0powerdns-recursor/files/smf/pdns_recursor.sh
+19-0powerdns-recursor/files/pdns_recursor.sh
+508-03 files not shown
+526-09 files

FreeBSD/ports c35267ddevel/py-Js2Py Makefile distinfo

devel/py-Js2Py: Apply upstream patch for Python 3.12 support

Co-authored-by: Michael Osipov <michaelo at FreeBSD.org>
PR:             289085
MFH:            2026Q1
(cherry picked from commit 37e1f72f44e412445a2e97bc85e159b218390243)
DeltaFile
+5-2devel/py-Js2Py/Makefile
+3-1devel/py-Js2Py/distinfo
+8-32 files

NetBSD/pkgsrc V66gDHVdoc CHANGES-2026

   Updated net/xfr to 0.6.0
VersionDeltaFile
1.1018+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc AtR09vunet/xfr distinfo cargo-depends.mk

   Updated net/xfr to 0.6.0

   v0.6.0

   What's New
   Congestion Control Selection (--congestion)

   Choose your TCP congestion control algorithm per-test:

   xfr <host> --congestion bbr -   # Compare BBR vs default CUBIC
   xfr <host> --congestion reno -  # Classic Reno

   Works on both client and server sockets. Invalid algorithms are caught early with a helpful error listing what's available on your kernel.
   Live TCP_INFO Polling

   RTT and cwnd are now reported every interval during tests, not just in the final result. This enables:

    - Real-time TCP metrics in the TUI
    - Per-interval rtt_us and cwnd in --json-stream and --csv output

    [61 lines not shown]
VersionDeltaFile
1.2+187-67net/xfr/distinfo
1.2+61-21net/xfr/cargo-depends.mk
1.2+3-3net/xfr/Makefile
+251-913 files

FreeBSD/ports 37e1f72devel/py-Js2Py Makefile distinfo

devel/py-Js2Py: Apply upstream patch for Python 3.12 support

Co-authored-by: Michael Osipov <michaelo at FreeBSD.org>
PR:             289085
MFH:            2026Q1
DeltaFile
+5-2devel/py-Js2Py/Makefile
+3-1devel/py-Js2Py/distinfo
+8-32 files

OPNSense/plugins 96ed534net/haproxy pkg-descr, net/haproxy/src/opnsense/mvc/app/models/OPNsense/HAProxy HAProxy.xml

Merge pull request #5206 from fraenki/haproxy_500a

net/haproxy: another addition for release 5.0
DeltaFile
+1-1net/haproxy/pkg-descr
+1-0net/haproxy/src/opnsense/mvc/app/models/OPNsense/HAProxy/HAProxy.xml
+2-12 files

NetBSD/pkgsrc VjckYssdoc CHANGES-2026

   doc: Updated games/warzone2100 to 4.6.3
VersionDeltaFile
1.1017+2-1doc/CHANGES-2026
+2-11 files

FreeBSD/src a2eb089. UPDATING, sys/netinet6 nd6_rtr.c

sys/netinet6: switch net.inet6.ip6.use_stableaddr to on by default

This change switches to using RFC 7217 algorithm as the default to
generate SLAAC addresses for IPv6 interfaces configured with
accept_rtadv.

Reviewed by:            pouria, glebius, zlei
Approved by:            zlei
Relnotes:               yes
Differential Revision:  https://reviews.freebsd.org/D55138
DeltaFile
+9-0UPDATING
+1-1sys/netinet6/nd6_rtr.c
+10-12 files

FreeNAS/freenas 6cd0b8atests/sharing_protocols/fibre_channel test_fibre_channel.py, tests/sharing_protocols/iscsi test_261_iscsi_cmd.py test_263_pyscstadmin.py

Temporarily remove sharing tests
DeltaFile
+0-3,459tests/sharing_protocols/iscsi/test_261_iscsi_cmd.py
+0-1,081tests/sharing_protocols/fibre_channel/test_fibre_channel.py
+0-818tests/sharing_protocols/smb/test_smb_protocol_base.py
+0-670tests/sharing_protocols/iscsi/test_263_pyscstadmin.py
+0-574tests/sharing_protocols/iscsi/test_262_iscsi_alua.py
+0-383tests/sharing_protocols/iscsi/test_260_iscsi.py
+0-6,9856 files not shown
+0-7,82912 files