LLVM/project 0ac83dcclang/lib/Driver/ToolChains/Arch AArch64.cpp

[clang][AArch64] Use structured bindings in feature parsing code (#197689)

Clearer than having to know that first is a CPU and second is the
feature list.
DeltaFile
+10-11clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+10-111 files

LLVM/project fb4d033llvm/lib/Target/PowerPC PPCInstrInfo.td PPCISelLowering.cpp

[PowerPC] Match intrinsics ppc_amo_st[dw]at with a pattern

The intrinsics are 1:1 to the instructions except for the order of
the operands, thus it is easy to match them with a pattern.

However, the intrinsics are defined as reading and writing to
memory, but the instructions explicitly set mayLoad to false.
Looking at the ISA description it seems to me that the latter
is not true. In any case, the side effect flags must be the
same, otherwise the pattern is rejected.
DeltaFile
+2-9llvm/lib/Target/PowerPC/PPCInstrInfo.td
+0-10llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+2-2llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+4-213 files

LLVM/project dc4f489libc/test/UnitTest ConstraintHandlerCheckingTest.h CMakeLists.txt

[libc] Annex K: Add constraint handler unit test class

This unit test class will be useful for the tests related to Annex K.
The functions in Annex K may call a constraint handler, so this new unit
test class will facilitate the checks that the constraint handling
mechanism is working as expected.
DeltaFile
+44-0libc/test/UnitTest/ConstraintHandlerCheckingTest.h
+11-0libc/test/UnitTest/CMakeLists.txt
+55-02 files

LLVM/project 692b8fdlibcxx/include/__format format_functions.h

[libc++] Replace ranges::find_first_of with std::find_first_of in __try_constant_folding (#197641)

This reduces the time it takes to instantiate `std::format` from ~160ms
to ~120ms in my testing.
DeltaFile
+7-3libcxx/include/__format/format_functions.h
+7-31 files

LLVM/project 54fb441llvm/include/llvm/Target Target.td, llvm/test/TableGen aarch64-apple-tuning-features.td

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+11-11llvm/test/TableGen/aarch64-apple-tuning-features.td
+1-1llvm/include/llvm/Target/Target.td
+12-122 files

LLVM/project 0f79ba2llvm/lib/Target/SPIRV SPIRVModuleAnalysis.cpp SPIRVSymbolicOperands.td, llvm/test/CodeGen/SPIRV/linkage weak-linkage.ll

Adjust SPV_AMD_weak_linkage (#197484)

Linkage was renamed + a capability added following review in
https://github.com/KhronosGroup/SPIRV-Registry/pull/401
DeltaFile
+6-5llvm/test/CodeGen/SPIRV/linkage/weak-linkage.ll
+3-1llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+2-1llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+1-1llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+12-84 files

LLVM/project db9b7f2llvm/lib/Target/AMDGPU AMDGPU.td AMDGPURegisterBankInfo.cpp

[AMDGPU][NFC] Add VMulU64Inst SubtargetFeature for v_mul_u64 support.
DeltaFile
+5-0llvm/lib/Target/AMDGPU/AMDGPU.td
+2-2llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+0-3llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+10-81 files not shown
+11-97 files

LLVM/project f2a9f41llvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp GCNSubtarget.h

[AMDGPU][NFC] Remove redundant hasMadU64U32NoCarry helper (#197682)

Use hasMadNC64_32Insts() (backed by SubtargetFeature) for MAD 64_32
no-carry and drop the old helper.
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+0-4llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+3-73 files

LLVM/project e30151eclang/test/Driver openmp-offload-gpu.c

one more fix
DeltaFile
+1-2clang/test/Driver/openmp-offload-gpu.c
+1-21 files

FreeBSD/src 988c039sys/compat/linuxkpi/common/include/linux io.h

linux/io: handle memtype_wc mapping for !DMAP range

The amdgpu driver in drm-kmod will attempt to update/reserve certain GPU
VRAM ranges as write-combining. Depending on the system, this address
range may fall outside of FreeBSD's constructed DMAP. We cannot use
pmap_change_attr() in this case.

When INVARIANTS is enabled, this results in the following:

  panic: physical address 0x880000000 not covered by the DMAP

Add a guard against triggering the KASSERT in PHYS_TO_DMAP().

This limitation in our implementation of arch_io_reserve_memtype_wc() is
already known in drm-kmod's amdgpu_bo_init(), and errors are ignored
there (see "BSDFIXME"). This change is only to eliminate the preventable
assertion failure within this scheme.

Tested by:      kevans

    [4 lines not shown]
DeltaFile
+6-1sys/compat/linuxkpi/common/include/linux/io.h
+6-11 files

FreeBSD/ports 901ca63www/nginx distinfo version.mk

www/nginx: Update to 1.30.1

PR:             295270
Approved by:    security/blanket
Security:       3414ac89-4f9f-11f1-a1c0-0050569f0b83
DeltaFile
+3-3www/nginx/distinfo
+1-1www/nginx/version.mk
+4-42 files

FreeBSD/ports 78c6cd4security/vuxml/vuln 2026.xml

security/vuxml: Document www/nginx DoS/RCE

PR:             295270
Security:       3414ac89-4f9f-11f1-a1c0-0050569f0b83
DeltaFile
+52-0security/vuxml/vuln/2026.xml
+52-01 files

LLVM/project 7206901libc/src/__support/CPP/type_traits is_constructible.h is_assignable.h

[libc] Include correct headers in type_traits (#197691)

Otherwise we end up with errors like the following when building with
bazel:
```c++
In file included from external/+_repo_rules+llvm-project/libc/src/__support/CPP/type_traits/is_move_constructible.h:12:
external/+_repo_rules+llvm-project/libc/src/__support/CPP/type_traits/is_constructible.h:32:14: error: no template named 'bool_constant'
   32 |     : public bool_constant<__is_constructible(T, Args...)> {};
```
DeltaFile
+1-1libc/src/__support/CPP/type_traits/is_constructible.h
+1-1libc/src/__support/CPP/type_traits/is_assignable.h
+2-22 files

LLVM/project d1a6d7bllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/AArch64 aarch64-mulv.ll

[DAG] SimplifyMultipleUseDemandedBits - fold (mul X, 1) -> X (#197677)

Use DemandedElts + KnownBits to match hidden identity patterns - helps
especially with reduction patterns padded by legalisation

Once #197455 has landed, I'm intending to convert this (plus
SMIN/SMAX/UMIN/UMAX and the existing ISD::ADD case) to use
isIdentityElement directly.
DeltaFile
+14-23llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+13-13llvm/test/CodeGen/X86/srem-vector-lkk.ll
+10-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+3-6llvm/test/CodeGen/AArch64/aarch64-mulv.ll
+2-2llvm/test/CodeGen/X86/dpbusd_const.ll
+42-445 files

LLVM/project 2a110felldb/source/Plugins/Process/Utility RegisterContextWindows_x86_64.cpp

[lldb][windows] fix x86_64 arg register mapping for lldb-server (#197663)
DeltaFile
+6-6lldb/source/Plugins/Process/Utility/RegisterContextWindows_x86_64.cpp
+6-61 files

FreeNAS/freenas 9e1e80asrc/freenas/usr/local/sbin hactl

fix hactl crash
DeltaFile
+2-2src/freenas/usr/local/sbin/hactl
+2-21 files

LLVM/project 290d0f6llvm/test/Transforms/LoopVectorize/AArch64 sve-interleaved-accesses.ll sve-interleaved-masked-accesses.ll

[LV][NFC] Remove instcombine from RUN lines in AArch64 tests (#197448)

This PR continues other work I've been doing trying to remove
unnecessary extra passes from the RUN lines in order to make it easier
to map the expected vectoriser output to the CHECK lines. As a result it
has exposed some potential optimisations that we may be able to perform
in VPlan.

Here is a summary of the changes I've noticed:

1. instcombine likes to canonicalise GEPs into certain forms. I'm not
sure if there is value in VPlan trying to guess what the canonical form
should be.
2. In tests like sve-cond-inv-loads.ll, etc. the pattern sub(urem) is
often replaced with and(sub). This is potentially something the
vectoriser could improve although I don't know if it would change the
cost model.
3. There is poor codegen in gather_nxv4i32_ind64_stride2 in the file
sve-gather-scatter.ll, which is due to

    [19 lines not shown]
DeltaFile
+176-182llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
+141-143llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
+85-82llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+70-53llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
+68-47llvm/test/Transforms/LoopVectorize/AArch64/reduction-small-size.ll
+47-37llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
+587-54411 files not shown
+756-68817 files

LLVM/project d2de1d2clang/include/clang/Basic BuiltinsPPC.def, clang/test/CodeGen/PowerPC builtins-ppc-dmf.c ppc-dmf-mma-builtin-err.c

[PowerPC] Update base crypto builtins and intrinsics (#197017)

Update the base crypto builtins and LLVM intrinsics to drop the mma_
prefix. Also fix the builtin definitions for dmsha2hash, dmsha3hash,
and dmxxshapad to use the correct immediate constraints.
DeltaFile
+33-33clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c
+17-17llvm/test/CodeGen/PowerPC/mmaplus-crypto.ll
+15-15clang/include/clang/Basic/BuiltinsPPC.def
+15-0clang/test/Sema/builtins-ppc-crypto.c
+6-6clang/test/CodeGen/PowerPC/ppc-dmf-mma-builtin-err.c
+3-3clang/test/Sema/PowerPC/ppc-dmf-mma-builtin-err.c
+89-744 files not shown
+99-8410 files

FreeBSD/ports 09e01bbdevel/nextpnr-devel distinfo Makefile

devel/nextpnr-devel: Update to 2026-05-12
DeltaFile
+3-3devel/nextpnr-devel/distinfo
+2-2devel/nextpnr-devel/Makefile
+5-52 files

LLVM/project 16b2ef3llvm/include/llvm/CodeGen MachineOutliner.h, llvm/lib/CodeGen RegisterScavenging.cpp LiveRegUnits.cpp

[CodeGen] Debug insns must not affect liveness analysis (#193104)

Register references in debug instructions can affect LiveRegUnits
analysis. Skip over debug instructions.

Tests in this PR would fail due to calls to LiveRegUnits::stepBackward
in RegisterScavenging, DeadMachineInstructionElim, and
AArch64InstrInfo.cpp getOutlinableRanges().

Other call-sites to stepBackward may also pass debug instructions to
LiveRegUnits::stepBackward, but LIT testing did not fail when
-debugify-and-strip-all-safe was enabled by default.

---------

Signed-off-by: John Lu <John.Lu at amd.com>
DeltaFile
+25-0llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
+4-2llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+2-2llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
+2-1llvm/lib/CodeGen/RegisterScavenging.cpp
+3-0llvm/lib/CodeGen/LiveRegUnits.cpp
+2-1llvm/include/llvm/CodeGen/MachineOutliner.h
+38-68 files not shown
+49-814 files

FreeBSD/ports e38a015lang/racket-minimal Makefile

lang/racket-minimal: Preserve .rackboot section when stripping gracket

PR:             291732
Submitted by:   Wes Frazier
DeltaFile
+6-0lang/racket-minimal/Makefile
+6-01 files

LLVM/project 439e422flang/lib/Frontend CompilerInvocation.cpp

lowerCamelize variable names
DeltaFile
+12-12flang/lib/Frontend/CompilerInvocation.cpp
+12-121 files

FreeNAS/freenas 078bb34tests/api2 test_300_nfs.py test_200_ftp.py

Remove tests
DeltaFile
+0-2,102tests/api2/test_300_nfs.py
+0-1,411tests/api2/test_200_ftp.py
+0-701tests/api2/test_011_user.py
+0-589tests/api2/test_service_announcement.py
+0-565tests/api2/test_audit_websocket.py
+0-506tests/api2/test_190_filesystem.py
+0-5,874256 files not shown
+0-32,288262 files

LLVM/project 5fc2cd4flang/docs ReleaseNotes.md

Update release notes
DeltaFile
+1-1flang/docs/ReleaseNotes.md
+1-11 files

LLVM/project e42de9dllvm/docs GettingInvolved.rst

[docs] Add the Clang Static Analysis WG to sync-ups (#197679)

See
https://discourse.llvm.org/t/rfc-forming-a-static-analysis-working-group-in-the-clang-ecosystem/90719/17
DeltaFile
+5-0llvm/docs/GettingInvolved.rst
+5-01 files

OpenBSD/xenocara 1aOWodvproto/xorgproto renderproto.txt presentproto.txt, proto/xorgproto/include/X11 XF86keysym.h

   Update to xorgproto 2025.1
VersionDeltaFile
1.6+190-22proto/xorgproto/include/X11/XF86keysym.h
1.2+35-35proto/xorgproto/renderproto.txt
1.3+44-26proto/xorgproto/scripts/keysym-generator.py
1.5+22-20proto/xorgproto/presentproto.txt
1.4+29-13proto/xorgproto/compile
1.2+13-13proto/xorgproto/COPYING-xextproto
+333-12951 files not shown
+489-26057 files

NetBSD/pkgsrc hVL0Dfsmath/py-scipy Makefile

   math/py-scipy: Work around meson finding cython-${NOT_PYVERSION}

   When e.g. building py313-scipy, with py314-cython installed, meson
   will find py314-cython.  It appears to lack a way to specify the path
   instead of searching, based on the two previous workarounds.
VersionDeltaFile
1.106+8-1math/py-scipy/Makefile
+8-11 files

FreeNAS/freenas 4616ad7src/middlewared/middlewared/plugins account.py, src/middlewared/middlewared/plugins/container lifecycle.py

Address review

* Rename a terribly named function. Provide description.
* Expand idmap validation
* Add more tests
DeltaFile
+81-0tests/unit/test_account_userns.py
+52-1src/middlewared/middlewared/plugins/account.py
+29-4src/middlewared/middlewared/plugins/container/lifecycle.py
+162-53 files

NetBSD/pkgsrc bT1R2kbdoc CHANGES-2026

   doc: Updated math/R to 4.6.0
VersionDeltaFile
1.3015+2-1doc/CHANGES-2026
+2-11 files

FreeBSD/src 4cdcacbsys/dev/usb usbdevs

usbdevs: Add TP-Link UB500 (RTL8761BUV) USB ID

This device is not yet supported.

Unfortunately some recently purchased UB400 dongles also contain this
Realtek IC.

Sponsored by:   The FreeBSD Foundation
DeltaFile
+1-0sys/dev/usb/usbdevs
+1-01 files