LLVM/project 4456f31llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll

[AMDGPU][True16] Use COPY instead of V_MOV for non-imm operand in movePackToVALU lowering (#185754)

We should use COPY here for no-imm operands to reduce the number of
generated mov in the isa. However, there is an issue in
https://github.com/llvm/llvm-project/pull/162389#discussion_r2430459341
here that blocked me from doing it.

With https://github.com/llvm/llvm-project/pull/185751 this should work
now
DeltaFile
+228-252llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+144-238llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+136-218llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+118-198llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+100-164llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
+120-129llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+846-1,19913 files not shown
+1,175-1,76519 files

LLVM/project 1fa7051lldb/test/API/lang/objc/objc-optimized TestObjcOptimized.py

[lldb] Update TestObjcOptimized.py for MTE (#186042)

Use process.FixAddress to strip the top byte when running under MTE.
DeltaFile
+11-2lldb/test/API/lang/objc/objc-optimized/TestObjcOptimized.py
+11-21 files

LLVM/project 9344236llvm/lib/Target/AArch64 AArch64CompressJumpTables.cpp AArch64.h, llvm/test/CodeGen/AArch64 jump-table-compress.mir

[NewPM] Port for AArch64CompressJumpTables (#186020)
DeltaFile
+33-12llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
+8-1llvm/lib/Target/AArch64/AArch64.h
+1-1llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+1-0llvm/lib/Target/AArch64/AArch64PassRegistry.def
+1-0llvm/test/CodeGen/AArch64/jump-table-compress.mir
+44-145 files

LLVM/project 7d4dd42mlir/include/mlir/Dialect/Tosa/IR TosaShapeOps.td, mlir/lib/Dialect/Tosa/IR TosaCanonicalizations.cpp

[mlir][tosa] Add concat_shape Op folder (#183293)

Apply compile time folding for TOSA.CONCAT_SHAPE

---------

Signed-off-by: Udaya Ranga <udaya.ranga at arm.com>
DeltaFile
+99-0mlir/test/Dialect/Tosa/constant_folding.mlir
+34-0mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
+2-0mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
+135-03 files

OPNSense/plugins 0e62a49net/wol Makefile, net/wol/src/opnsense/mvc/app/models/OPNsense/Wol/ACL ACL.xml

net/wol: add access to get_arp so dashboard widget works

For core the dashboard ACL holds all the dashboard related API
patterns but we don't want to taint it with plugin requirements.

So instead of adding a WoL-Dashboard privilege add the required
API endpoint to the standard ACL to unbreak.  This is only relevant
for the plugin when installed and explicitly using the privilege.
DeltaFile
+1-1net/wol/Makefile
+1-0net/wol/src/opnsense/mvc/app/models/OPNsense/Wol/ACL/ACL.xml
+2-12 files

OPNSense/core 9c950fcsrc/opnsense/mvc/app/controllers/OPNsense/IPsec/Api SpdController.php, src/opnsense/scripts/ipsec spddelete.py

VPN: IPsec: Security Policy Database - delete selected not backed by actual logic, closes https://github.com/opnsense/core/issues/9937
DeltaFile
+12-6src/opnsense/scripts/ipsec/spddelete.py
+1-1src/opnsense/mvc/app/controllers/OPNsense/IPsec/Api/SpdController.php
+13-72 files

LLVM/project 47a8a6dflang/lib/Semantics canonicalize-acc.cpp, flang/test/Semantics/OpenACC acc-canonicalization-validity.f90

[flang][acc] Ignore compiler directives when checking tight-nesting (#186222)
DeltaFile
+13-0flang/test/Semantics/OpenACC/acc-canonicalization-validity.f90
+6-1flang/lib/Semantics/canonicalize-acc.cpp
+19-12 files

LLVM/project 983269bclang/include/clang/Lex HeaderSearch.h, clang/lib/Frontend ASTUnit.cpp CompilerInstance.cpp

[clang] Expose normalized module cache path in `HeaderSearch` (#185746)

Previously, the normalized module cache path was only accessible via
`HeaderSearch::getSpecificModuleCachePath()` which may or may not also
contain the context hash. Clients would need to parse the result to
learn the normalized module cache path. What `ASTWriter` does instead is
normalize the as-written module cache path redundantly.

Instead, this PR exposes the normalized module cache path in the
`HeaderSearch` interface and moves the computation of specific module
cache path into the clangLex library.

This is motivated by another patch that would've needed to redundantly
perform the module cache path canonicalization or parse the specific
module cache path.
DeltaFile
+33-29clang/lib/Serialization/ASTReader.cpp
+28-0clang/lib/Lex/HeaderSearch.cpp
+20-8clang/include/clang/Lex/HeaderSearch.h
+11-12clang/lib/Frontend/ASTUnit.cpp
+5-17clang/lib/Frontend/CompilerInstance.cpp
+9-3clang/lib/Frontend/FrontendActions.cpp
+106-696 files not shown
+118-9112 files

LLVM/project 4334fedclang/include/clang/Analysis/Scalable/SummaryData SummaryDataStore.h SummaryDataBuilder.h, clang/lib/Analysis/Scalable/SummaryData LUSummaryConsumer.cpp

[clang][ssaf] Add LUSummary consumer APIs

This patch adds the consumer-side infrastructure for the Scalable Static
Analysis Framework (SSAF). After the EntityLinker produces a LUSummary,
these new components build typed analysis data from it.
- `SummaryData` — A base class for analysis views to expose
analysis-specific query API.
- `SummaryDataBuilder` — An abstract base class that populates a
concrete `SummaryData`.
- `SummaryDataBuilderRegistry` — A registry wrapper for
`SummaryDataBuilder` class.
- `SummaryDataStore` - A wrapper containing a map from `SummaryName` to
`SummaryData`, returned as a result of running the `LUSummaryConsumer`.
- `LUSummaryConsumer` — Drives the process of populating `SummaryData`
instances from `LUSummary` via corresponding `SummaryDataBuilder`
instances.
DeltaFile
+397-0clang/unittests/Analysis/Scalable/SummaryData/SummaryDataTest.cpp
+115-0clang/include/clang/Analysis/Scalable/SummaryData/SummaryDataStore.h
+95-0clang/include/clang/Analysis/Scalable/SummaryData/SummaryDataBuilder.h
+93-0clang/include/clang/Analysis/Scalable/SummaryData/LUSummaryConsumer.h
+78-0clang/lib/Analysis/Scalable/SummaryData/LUSummaryConsumer.cpp
+72-0clang/include/clang/Analysis/Scalable/SummaryData/SummaryDataBuilderRegistry.h
+850-06 files not shown
+956-012 files

FreeBSD/ports 4e8a8a9math/R-cran-terra Makefile, math/R-cran-terra/files patch-fix-tests

math/R-cran-terra: Fix tests

Apply upstream patch to fix tests.
DeltaFile
+80-0math/R-cran-terra/files/patch-fix-tests
+2-2math/R-cran-terra/Makefile
+82-22 files

LLVM/project 816b52fllvm/lib/CodeGen MachineCopyPropagation.cpp, llvm/test/CodeGen/X86 machine-copy-prop.mir

[MCP] Never eliminate frame-setup/destroy instructions

Presumably targets only insert frame instructions which are significant,
and there may be effects MCP doesn't model. Similar to reserved registers this
is probably overly conservative, but as this causes no codegen change in
any lit test I think it is benign.

The motivation is just to clean up #183149 for AMDGPU, as we can spill
to physical registers, and currently have to spill the EXEC mask purely
to enable debug-info.

Change-Id: I9ea4a09b34464c43322edd2900361bf635efd9f7
DeltaFile
+22-0llvm/test/CodeGen/X86/machine-copy-prop.mir
+4-1llvm/lib/CodeGen/MachineCopyPropagation.cpp
+26-12 files

LLVM/project 5700b96llvm/lib/CodeGen MachineCopyPropagation.cpp

[MCP][NFC] Opinionated refactoring using new type

There are a few minor inconsistencies across the pass which I found mildly
distracting:

* The use of `Def`/`Dest`/`Dst` to refer to the same thing
* Inconsistent declaration order of `Def`/`Src` vs `Src`/`Def`
* Lots of `->getReg()->asMCReg()`, and uses of `Register` when the pass
  is always running after RA anyway.
* Some places explicitly `assert(isCopyInstr)` while others just deref
  the `optional`.

The refactor uses structured bindings for a couple reasons:

* Naturally enforces consistent order of `Def`-then-`Src`
* Requires the use of `auto`, which ensures the declaration is not
  implicitly converting from `MCRegister` back to `Register`.

In both cases the explicitness of the name `getDefSrcMCRegs` hopefully

    [9 lines not shown]
DeltaFile
+155-166llvm/lib/CodeGen/MachineCopyPropagation.cpp
+155-1661 files

LLVM/project 0f75953clang/lib/CIR/Dialect/Transforms TargetLowering.cpp, clang/lib/CIR/Dialect/Transforms/TargetLowering TargetLoweringInfo.h

Enforce Lang AS -> Target AS conversions via TargetLowering pass
DeltaFile
+252-1clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
+1-4clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+0-1clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.h
+253-63 files

LLVM/project 2b051edmlir/test/Dialect/Builtin/Bytecode builtin_fixed.mlir builtin_fixed_0.mlirbc

[MLIR][Bytecode][builtin] Add non-regression tests (#186078)

Add test to avoid accidental serialization changes.
DeltaFile
+422-0mlir/test/Dialect/Builtin/Bytecode/builtin_fixed.mlir
+0-0mlir/test/Dialect/Builtin/Bytecode/builtin_fixed_0.mlirbc
+422-02 files

FreeBSD/ports 78acbd2misc/py-NATTEN Makefile, misc/py-NATTEN/files patch-pyproject.toml

misc/py-NATTEN: Fix build by fixing dependencies

Reported by:    fallout
DeltaFile
+4-1misc/py-NATTEN/Makefile
+2-2misc/py-NATTEN/files/patch-pyproject.toml
+6-32 files

LLVM/project ca011e4lldb/unittests/SymbolFile/PDB SymbolFilePDBTests.cpp

[lldb] Fix typo in SymbolFilePDBTests (#186236)

This should fix the assertion on Windows caused by #185537.
DeltaFile
+1-1lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp
+1-11 files

LLVM/project ee72082clang/lib/CIR/CodeGen TargetInfo.cpp, clang/lib/CIR/Dialect/Transforms/TargetLowering LowerModule.cpp TargetLoweringInfo.h

[CIR][AMDGPU] Lower Language specific address spaces and implement AMDGPU target
DeltaFile
+48-9clang/test/CIR/Lowering/global-address-space.cir
+51-0clang/test/CIR/CodeGen/amdgpu-address-spaces.cpp
+47-0clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
+46-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+9-2clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
+11-0clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.h
+212-113 files not shown
+219-119 files

NetBSD/pkgsrc DI3IImudatabases/sqlite3-diff distinfo

   sqlite3-diff: regen for sqlite3 update
VersionDeltaFile
1.8+4-4databases/sqlite3-diff/distinfo
+4-41 files

NetBSD/pkgsrc arosgzTaudio/cmus-legacy PLIST

   cmus-legacy: update PLIST for ffmpeg option removal
VersionDeltaFile
1.2+1-2audio/cmus-legacy/PLIST
+1-21 files

LLVM/project 415ab92llvm/lib/CodeGen MachineCopyPropagation.cpp, llvm/test/CodeGen/X86 machine-copy-prop.mir

[MCP] Never eliminate frame-setup/destroy instructions

Presumably targets only insert frame instructions which are significant,
and there may be effects MCP doesn't model. Similar to reserved registers this
is probably overly conservative, but as this causes no codegen change in
any lit test I think it is benign.

The motivation is just to clean up #183149 for AMDGPU, as we can spill
to physical registers, and currently have to spill the EXEC mask purely
to enable debug-info.

Change-Id: I9ea4a09b34464c43322edd2900361bf635efd9f7
DeltaFile
+22-0llvm/test/CodeGen/X86/machine-copy-prop.mir
+4-1llvm/lib/CodeGen/MachineCopyPropagation.cpp
+26-12 files

LLVM/project 811998ellvm/lib/CodeGen MachineCopyPropagation.cpp

[MPC][NFC] Opinionated refactoring using new type

There are a few minor inconsistencies across the pass which I found mildly
distracting:

* The use of `Def`/`Dest`/`Dst` to refer to the same thing
* Inconsistent declaration order of `Def`/`Src` vs `Src`/`Def`
* Lots of `->getReg()->asMCReg()`, and uses of `Register` when the pass
  is always running after RA anyway.
* Some places explicitly `assert(isCopyInstr)` while others just deref
  the `optional`.

The refactor uses structured bindings for a couple reasons:

* Naturally enforces consistent order of `Def`-then-`Src`
* Requires the use of `auto`, which ensures the declaration is not
  implicitly converting from `MCRegister` back to `Register`.

In both cases the explicitness of the name `getDefSrcMCRegs` hopefully

    [9 lines not shown]
DeltaFile
+155-166llvm/lib/CodeGen/MachineCopyPropagation.cpp
+155-1661 files

LLVM/project e6672a9llvm/lib/CodeGen MachineCopyPropagation.cpp

[MCP][NFC] Cleanup and prepare to preserve frame-setup/destroy

This mixes renames, removing redundant code, avoiding
`else`-after-`return`, etc. with factoring out the `isNeverRedundant`
concept. I can drop any bits people would rather I not touch.

Change-Id: I43a62a9415019cdd63c68fd3b915ebb7505d317a
DeltaFile
+73-61llvm/lib/CodeGen/MachineCopyPropagation.cpp
+73-611 files

LLVM/project 959ee11llvm/include/llvm/CodeGen Register.h, llvm/include/llvm/MC MCRegister.h

[CodeGen][MC][NFC] Clarify MCRegister ctor behavior

This is something I have learned, forgotten, and relearned
at least once now, so I figured it is worth noting in a comment:
the `MCRegister` constructor does not `assert` on non-Physical,
non-Invalid values.

Also do some related cleanup:

Make `MCRegister::from` be `constexpr` and use it in `Register::asMCReg`
instead of duplicating the `assert`.

Reword the doc-comment on `MCRegister::from` to avoid using the
overloaded term "valid" (an "invalid" `MCRegister` is perfectly valid here).

Change-Id: I0985a825ae83d0601899fa4ab046ff262359e93f
DeltaFile
+16-3llvm/include/llvm/MC/MCRegister.h
+1-4llvm/include/llvm/CodeGen/Register.h
+17-72 files

LLVM/project ecc4d3elibclc/clc/include/clc/math clc_ep.inc

libclc: Fix mismatch in declared and defined function name (#186227)
DeltaFile
+6-6libclc/clc/include/clc/math/clc_ep.inc
+6-61 files

LLVM/project 2b88a6aclang/lib/CIR/CodeGen CIRGenModule.cpp

Address another round of comments
DeltaFile
+4-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+4-31 files

FreeBSD/ports 5a3685dmisc/rash distinfo Makefile

misc/rash: update 2.17.8 → 2.18.0
DeltaFile
+475-353misc/rash/distinfo
+238-178misc/rash/Makefile
+713-5312 files

FreeBSD/ports 896337cwww/py-qh3 distinfo Makefile, www/py-qh3/files patch-cargo-crates_aws-lc-sys-0.20.1_aws-lc_include_openssl_target.h patch-powerpc64le

www/py-qh3: update 1.0.9 → 1.6.0
DeltaFile
+235-223www/py-qh3/distinfo
+118-113www/py-qh3/Makefile
+0-20www/py-qh3/files/patch-cargo-crates_aws-lc-sys-0.20.1_aws-lc_include_openssl_target.h
+0-20www/py-qh3/files/patch-powerpc64le
+353-3764 files

FreeBSD/ports 1410a0dtextproc/comrak distinfo Makefile

textproc/comrak: update 0.48.0 → 0.51.0
DeltaFile
+313-259textproc/comrak/distinfo
+157-131textproc/comrak/Makefile
+470-3902 files

FreeBSD/ports c1053damisc/timr-tui distinfo Makefile

misc/timr-tui: update 1.7.0 → 1.7.1
DeltaFile
+3-3misc/timr-tui/distinfo
+1-1misc/timr-tui/Makefile
+4-42 files

FreeBSD/ports 9b71ec0security/rpm-sequoia distinfo Makefile

security/rpm-sequoia: update 1.9.0 → 1.10.1
DeltaFile
+263-263security/rpm-sequoia/distinfo
+131-132security/rpm-sequoia/Makefile
+394-3952 files