FreeNAS/freenas 09b989b — src/middlewared/middlewared/plugins/pool_ dataset.py, src/middlewared/middlewared/plugins/zfs resource_create.py name_utils.py

NAS-144148 / 28.0.0-BETA.1 / Reject leading and trailing spaces in new dataset name components (#19906)

ZFS accepts a dataset name component that begins or ends with a space,
and the API only rejected a space at the very end of the full path. So
`pool.dataset.create` with `create_ancestors` could still create a
parent such as `tank/mid ` from `tank/mid /child`, and a leading space
(`tank/ data`) was accepted by create and rename alike. The web UI
already blocks spaces in dataset names; this closes the API side.

- `pool.dataset.create`, `pool.dataset.rename` and `zfs.resource.create`
reject a new name whose last component begins or ends with a space. A
leading space was accepted before and now gets an error saying so on
every API version. A trailing space was already rejected:
`zfs.resource.create` now reports it with the same specific error, while
`pool.dataset.create` and `pool.dataset.rename` keep the generic
invalid-name message because the API's own name validation catches it
first.
- With `create_ancestors`, every parent the request would create is
checked too, and the error names the closest offending parent.

    [5 lines not shown]
DeltaFile
+20-5src/middlewared/middlewared/plugins/zfs/create_rules.py
+20-1tests/api2/test_zfs_resource_create.py
+18-2tests/api2/test_pool_dataset_create.py
+10-5src/middlewared/middlewared/plugins/pool_/dataset.py
+7-0src/middlewared/middlewared/plugins/zfs/name_utils.py
+2-0src/middlewared/middlewared/plugins/zfs/resource_create.py
+77-136 files

LLVM/project ddbd374 — llvm/lib/Target/AMDGPU AMDGPUEventTracking.h AMDGPUEventTracking.cpp, llvm/unittests/Target/AMDGPU AMDGPUEventTrackingTest.cpp

Simplifications, part 2
DeltaFile
+26-112llvm/lib/Target/AMDGPU/AMDGPUEventTracking.cpp
+3-81llvm/unittests/Target/AMDGPU/AMDGPUEventTrackingTest.cpp
+3-48llvm/lib/Target/AMDGPU/AMDGPUEventTracking.h
+32-2413 files

FreeBSD/ports 526dbb8 — devel/etcd36 Makefile distinfo

devel/etcd36: Update to 3.6.15

Sponsored by:   fme AG
DeltaFile
+21-21devel/etcd36/distinfo
+1-1devel/etcd36/Makefile
+22-222 files

LLVM/project 1899f5a — llvm/lib/Target/AMDGPU AMDGPUEventTracking.h AMDGPUEventTracking.cpp, llvm/unittests/Target/AMDGPU AMDGPUEventTrackingTest.cpp

Simplify implementation; part 1
DeltaFile
+122-127llvm/lib/Target/AMDGPU/AMDGPUEventTracking.cpp
+100-105llvm/unittests/Target/AMDGPU/AMDGPUEventTrackingTest.cpp
+52-100llvm/lib/Target/AMDGPU/AMDGPUEventTracking.h
+274-3323 files

FreeBSD/ports 479c4ab — net/samba423 Makefile distinfo

net/samba423: update to 4.23.13

Changes since 4.23.12
---------------------

   * BUG 16097: POSIX ACL backend silently discards errors when processing NT
     ACLs with non-canonical ordering
   * BUG 15962: SMB3 SESSION SETUP responses must always be signed
   * BUG 16081: winbindd_child_msg_filter: talloc_get_type_abort crashes when
     winbind max domain connections > 1
   * BUG 16239: Fix parsing of uppercase "0X" hex values in the "kdc default
     domain      supported enctypes" smb.conf parameter.
   * BUG 16240: smbd temporary mkdir name can exceed NAME_MAX for otherwise
     valid client names
   * BUG 16258: Python smbconf transaction_start() lacks a talloc stack frame
     with CTDB
   * BUG 16254: CTDB database operations can be run against incorrect nodes

Reported by:    portscout
Sponsored by:   Klara, Inc.
DeltaFile
+3-3net/samba423/distinfo
+2-2net/samba423/Makefile
+5-52 files

FreeBSD/ports 1aa38eb — Mk/Uses kde.mk

Uses/kde.mk: Deorbit last bits of Plasma 5
DeltaFile
+1-7Mk/Uses/kde.mk
+1-71 files

LLVM/project 4dfc4f5 — clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/test/CIR/CodeGenOpenCL global-vars.cl

[CIR] Emit OpenCL file scope global variables (#228125)
DeltaFile
+25-0clang/test/CIR/CodeGenOpenCL/global-vars.cl
+7-2clang/lib/CIR/CodeGen/CIRGenModule.cpp
+32-22 files

LLVM/project d917e35 — clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-logb-scalbn.hip

[CIR][AMDGPU] Use nsw add and ordered compare in logb lowering (#228004)

Align with classic codegen, which emits add nsw and fcmp one

Classic codegen code we are aligning with:
https://github.com/llvm/llvm-project/blob/8995a358fa77a669679594aa9857ba0e0b224ab1/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp#L2233-L2239
DeltaFile
+2-2clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+4-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-logb-scalbn.hip
+6-22 files

LLVM/project a3b8700 — clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen CIRGenBuiltin.cpp

[CIR][SPIR-V] Dispatch AMDGPU builtins on AMDGCN-flavored SPIR-V (#222018)

Mappings to classic codegen:
- spirv32/spirv64 arch switch:
https://github.com/llvm/llvm-project/blob/52d922aa153b1232813470e014635419ce006023/clang/lib/CodeGen/CGBuiltin.cpp#L129-L135
- spv -> amdgcn prefix handling:
https://github.com/llvm/llvm-project/blob/52d922aa153b1232813470e014635419ce006023/clang/lib/CodeGen/CGBuiltin.cpp#L6879-L6881
- `supportsLibCall()`:
https://github.com/llvm/llvm-project/blob/52d922aa153b1232813470e014635419ce006023/clang/lib/CodeGen/Targets/SPIR.cpp#L139-L142
DeltaFile
+92-0clang/test/CIR/CodeGenHIP/amdgcnspirv-builtins.hip
+8-0clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+5-0clang/lib/CIR/CodeGen/Targets/SPIRV.cpp
+4-0clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/SPIRV.cpp
+1-0clang/include/clang/CIR/MissingFeatures.h
+110-05 files

LLVM/project ec59078 — clang-tools-extra/clang-tidy/misc ConstCorrectnessCheck.cpp, clang-tools-extra/docs ReleaseNotes.md

[clang-tidy] Ignore parameters of `main` in `misc-const-correctness` (#228120)

The standard fixes the signature of `main`, so suggesting `const` for
its parameters is a false positive. The check warned on `char **argv`
but not on `char *argv[]`. The array form did not warn because the check
does not analyze array-style parameters.

The check now skips all parameters of `main`. Local variables inside
`main` are still checked.

Fixes https://github.com/llvm/llvm-project/issues/227988
DeltaFile
+23-0clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-parameters-main.cpp
+2-2clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
+2-2clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
+3-0clang-tools-extra/docs/ReleaseNotes.md
+30-44 files

LLVM/project e6ef6b9 — llvm/lib/CodeGen RegisterCoalescer.cpp, llvm/test/CodeGen/AMDGPU coalescer-subreg-undef-in-bundle.mir

[RegisterCoalescer] Update undef flags inside bundles (#227615)

When joining makes an earlier subregister def a partial redefinition,
JoinVals::pruneValues removes its undef flag. It only looked at the
instruction returned by getInstructionFromIndex, which for a bundle is
the BUNDLE header, so the def inside the bundle kept a stale undef flag
that disagreed with the header. Update all operands in the bundle.

Co-authored-by: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
DeltaFile
+31-0llvm/test/CodeGen/AMDGPU/coalescer-subreg-undef-in-bundle.mir
+2-2llvm/lib/CodeGen/RegisterCoalescer.cpp
+33-22 files

LLVM/project 3f48e22 — llvm/include/llvm/ADT ilist_iterator.h, llvm/unittests/ADT IListIteratorTest.cpp

[IList] Fix getNodeParent() interaction with const qualifiers (#228362)

In the old implementation getNodeParent() did not work at all on
`const_iterator` (because the body would fail to compile) and `const
iterator` (because the method was not marked const).

Fix this and add more unit tests for various combinations of constness.

It should be noted that `const iterator` behaves just like plain
`iterator` in that it returns a non-const parent pointer. Only
`const_iterator` returns a const parent pointer.
DeltaFile
+21-0llvm/unittests/ADT/IListIteratorTest.cpp
+3-3llvm/include/llvm/ADT/ilist_iterator.h
+24-32 files

LLVM/project 557c3bf — mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc TosaOps.td, mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Add support for ARGMIN (#227997)

- Add ARGMIN table gen
- Add validators and folders
- Add positive and negative tests
- Add compliance info

Signed-off-by: Iliyan Georgiev <iliyan.georgiev at arm.com>
DeltaFile
+73-47mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+51-0mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32.mlir
+35-14mlir/test/Dialect/Tosa/ops.mlir
+36-0mlir/test/Dialect/Tosa/constant_folding.mlir
+36-0mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
+30-0mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+261-6114 files not shown
+428-8720 files

OpenBSD/src gsNf0rK — sys/net pf_table.c pf.c

   pf(4): pfr_insert_kentry() always needs PF_LOCK()

   pfr_insert_kentry() inserts an IP address into a table. The table's
   consistency is protected by PF_LOCK(). Unfortunately, PF_LOCK()
   protection is missing for the code path executed on behalf
   of the overload action in a pf rule. The overload action instructs
   the firewall to insert the packet's source address into the table specified
   as the overload action parameter. That particular code path in
   pf_test() function runs without any lock protection.

   The bug was introduced in revision 1.1074 and remained unnoticed
   until now, when it was kindly reported by alf (a.schlichting () lemarit ! com>)

   OK henning@, OK dlg@, OK jmatthew@
VersionDeltaFile
1.1242+14-4sys/net/pf.c
1.151+3-1sys/net/pf_table.c
+17-52 files

LLVM/project c18f828 — llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/AArch64 memory-widening-debug.ll

[LV][NFC] Add more debug when setting the widening decision (#227617)

Whilst debugging some vectorisation issues recently, I discovered the
vectoriser is very opaque about it's decision making process which makes
it very hard to figure out what is happening. I've added debug messages
to help the developer understand the process better.

Tests assisted by Codex (GPT-5.5)
DeltaFile
+227-0llvm/test/Transforms/LoopVectorize/AArch64/memory-widening-debug.ll
+41-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+268-22 files

LLVM/project 7788875 — clang/include/clang/Basic DiagnosticFrontendKinds.td, clang/lib/CodeGen CodeGenAction.cpp

clang: Set the exception model module flag for IR inputs

Previously the -exception-model cc1 flag did nothing for IR inputs. Record the
module flag in the IR input path too, next to the existing triple override. A
 model contradicting one the input module already records is rejected matching
err_data_layout_mismatch and the conflict llc reports for the same pair of
inputs.

This is to keep the wasm-eh.ll test passing when the TargetOptions field for
ExecptionModel is removed. I'm not sure if this behavior really needs to be
preserved given the bitcode producers should now materialize the flag in the
IR.

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+20-0clang/test/CodeGen/WebAssembly/wasm-exception-model-flag-ir-input-mismatch.ll
+18-0clang/lib/CodeGen/CodeGenAction.cpp
+6-2clang/test/CodeGen/WebAssembly/wasm-exception-model-flag-parse-ir-input.ll
+3-0clang/include/clang/Basic/DiagnosticFrontendKinds.td
+47-24 files

FreeBSD/ports 6874120 — textproc/py-textual-textarea distinfo Makefile

textproc/py-textual-textarea: Update to 0.18.5

- Update list of run-dependencies: the module requires textual[sintax],
  but the relative option in textproc/py-textual is OFF by default, so
  add manually the relative modules.

ChangeLog:

1. https://github.com/tconbeer/textual-textarea/releases/tag/v0.18.5

Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+3-3textproc/py-textual-textarea/distinfo
+4-2textproc/py-textual-textarea/Makefile
+7-52 files

LLVM/project 293fc58 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp

format
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+1-11 files

LLVM/project e524948 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU narrow-int-to-bfloat.ll narrow-int-to-fp.ll

[AMDGPU] Price scalar integer to fp casts by source width and sign

Scalar sources between a byte and 31 bits fell to the default cost of one
while the matching vector lanes were already priced, which skewed the
difference SLP weighs a bundle against. Such a source is extended before
the conversion, and what the extension takes depends on the width, on the
sign and on whether the subtarget has SDWA and 16 bit instructions.
Sources narrower than a byte are left alone, because their vector form is
not priced either.
DeltaFile
+388-388llvm/test/Analysis/CostModel/AMDGPU/narrow-int-to-fp.ll
+72-72llvm/test/Analysis/CostModel/AMDGPU/narrow-int-to-bfloat.ll
+29-9llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+489-4693 files

LLVM/project d05a0a5 — llvm/test/CodeGen/AMDGPU slp-int-to-fp.ll

update slp-int-to-fp.ll
DeltaFile
+324-391llvm/test/CodeGen/AMDGPU/slp-int-to-fp.ll
+324-3911 files

LLVM/project f161776 — llvm/test/CodeGen/AMDGPU slp-int-to-fp.ll

update slp-int-to-fp.ll
DeltaFile
+128-170llvm/test/CodeGen/AMDGPU/slp-int-to-fp.ll
+128-1701 files

LLVM/project 6cbd60e — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU narrow-int-to-bfloat.ll narrow-int-to-fp.ll

few fixes
DeltaFile
+90-90llvm/test/Analysis/CostModel/AMDGPU/narrow-int-to-fp.ll
+24-24llvm/test/Analysis/CostModel/AMDGPU/narrow-int-to-bfloat.ll
+10-1llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+124-1153 files

LLVM/project ca7e603 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU narrow-int-to-bfloat.ll narrow-int-to-fp.ll

[AMDGPU] Do not price the extension of a loaded i40, i48 or i56 in int to fp casts

A widened constant or invariant load still pays it.
DeltaFile
+100-100llvm/test/Analysis/CostModel/AMDGPU/narrow-int-to-fp.ll
+24-24llvm/test/Analysis/CostModel/AMDGPU/narrow-int-to-bfloat.ll
+18-6llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+142-1303 files

LLVM/project f3778fb — llvm/test/Analysis/CostModel/AMDGPU narrow-int-to-bfloat.ll narrow-int-to-fp.ll, llvm/test/CodeGen/AMDGPU itofp-odd-width-load.ll slp-int-to-fp.ll

[NFC][AMDGPU] Add tests for int to fp casts of loaded odd width integers (#227904)

Assisted-by: Claude Code Opus 5
DeltaFile
+855-0llvm/test/CodeGen/AMDGPU/slp-int-to-fp.ll
+466-0llvm/test/CodeGen/AMDGPU/itofp-odd-width-load.ll
+432-0llvm/test/Analysis/CostModel/AMDGPU/narrow-int-to-fp.ll
+130-0llvm/test/Analysis/CostModel/AMDGPU/narrow-int-to-bfloat.ll
+1,883-04 files

FreeBSD/doc 368d0e4 — website/themes/beastie/assets/styles main.css

website: fix sub-menu in the header for mobile devices

If the browser width is less than 1300 pixels: click top left
on "About" and the sub-menu will not open anymore due the missing IDs.

PR: 297509
Approved by: carlavilla, ziaee
Fixes: 10633eb86b6396ec3fe8b666f8e250d67398fbec
Differential Revision: https://reviews.freebsd.org/D60236
DeltaFile
+1-6website/themes/beastie/assets/styles/main.css
+1-61 files

LLVM/project e7f7422 — clang/docs SanitizerCoverage.md, compiler-rt/lib/sanitizer_common sanitizer_flags.inc sanitizer_coverage_libcdep_new.cpp

[compiler-rt] Add print_coverage_summary to silence SanitizerCoverage dump logs (#228039)

When running a test suite of SanitizerCoverage-instrumented binaries,
the `SanitizerCoverage: … PCs written` summary on stderr can poison
FileCheck and cause unexpected failures.

There is no way to turn that print off today. At most you can use
`log_path`, but that still creates a text file per process. We could
have guard it on the verbosity option, but that would change the default
and may regress consumers that rely on this output.

This PR adds `print_coverage_summary` (default true). Set
`print_coverage_summary=0` to keep the dump log disable; .sancov files
are still written. The same guard is used on the Fuchsia path.

The new lit test is a copy of sanitizer_coverage_trace_pc_guard.cpp,
adapted to check the default print and print_coverage_summary=0.
DeltaFile
+32-0compiler-rt/test/sanitizer_common/TestCases/sanitizer_coverage_summary.cpp
+3-2compiler-rt/lib/sanitizer_common/sanitizer_coverage_fuchsia.cpp
+4-0clang/docs/SanitizerCoverage.md
+2-1compiler-rt/lib/sanitizer_common/sanitizer_coverage_libcdep_new.cpp
+2-0compiler-rt/lib/sanitizer_common/sanitizer_flags.inc
+43-35 files

LLVM/project 55be32f —

[IRBuilder] Propagate fast-math flags to folding in CreateBinOpFMF (#227543)

Fast-math flags are used by InstSimplifyFolder, so we need to pass them
to the folding function in CreateBinOpFMF.
DeltaFile
+0-00 files

FreeBSD/doc 2661473 — website/content/en/cgi man.cgi

man.cgi: clarify help text
DeltaFile
+2-2website/content/en/cgi/man.cgi
+2-21 files

LLVM/project 1a92355 — llvm/lib/IR Constants.cpp

[IR] Suppress getGetElementPtr() deprecation in more places (#228364)

These methods are themselves deprecated. Clang does not warn for
them, but MSVC does.
DeltaFile
+4-0llvm/lib/IR/Constants.cpp
+4-01 files

LLVM/project 63dd4ca — llvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU fold-and-exec.mir memintrinsic-unroll.ll

[AMDGPU] Fold away S_AND of a lane mask with EXEC (#227729)

Instruction selection inserts an S_AND with EXEC on branch conditions
unconditionally, because it has not analysed what produced the lane
mask: see the AndExec handling in AMDGPUDAGToDAGISel::SelectBRCOND and
the S_CBRANCH_SCC* case of SIInstrInfo::moveToVALU. The result of a
V_CMP already has 0 in the bits of all inactive lanes, so the AND is
redundant.

SIPreEmitPeephole::optimizeVccBranch already removes some of these, but
it runs after register allocation and only matches a V_CMP in the VOPC
(_e32) encoding writing physical VCC. That requires SIShrinkInstructions
to have set a VCC register allocation hint, which it only does when
canShrink() succeeds, so any V_CMP that is VOP3-only (source modifiers,
or two SGPR sources) keeps its AND.

Fold the AND away in SIFoldOperands instead, which runs before the
register coalescer, so the V_CMP result can be coalesced into VCC.

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+1,019-1,065llvm/test/CodeGen/AMDGPU/frem.ll
+168-196llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+281-0llvm/test/CodeGen/AMDGPU/fold-and-exec.mir
+37-46llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
+30-39llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
+59-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+1,594-1,34653 files not shown
+1,843-1,69659 files