[SystemZ][z/OS] Implement emitCommonSymbol in MCGOFFStreamer (#210179)
Common globals were not emitted in GOFF object files due to a missing
emitCommonSymbol implementation. This adds the implementation to emit
the required SD/ED/PR ESD records in the GOFF object file.
(cherry picked from commit 705d0ec6115cef3232eafe6221f42f78e7b884e8)
[DTLTO] Overlap temporary file removal (#209423)
Deleting the temporary files produced by the DTLTO pipeline can be
expensive on Windows hosts. For a Clang link (Debug build with
sanitizers and instrumentation) using an optimized toolchain (PGO
non-LTO, llvmorg-22.1.0) on a Windows 11 Pro (Build 26200), AMD Family
25 @ ~4.5 GHz, 16 cores/32 threads, 64 GB RAM machine, the mean duration
of the "Remove DTLTO temporary files" time trace scope was 1267.789 ms
(measured over 10 runs).
This patch performs the deletions on a background thread, allowing them
to overlap with the tail of the link to hide this cost.
This is a re-implementation of the asynchronous cleanup idea from
https://github.com/llvm/llvm-project/pull/186988, which had to be
reverted in https://github.com/llvm/llvm-project/pull/189043 because
cleanup was not guaranteed to complete before LLD invoked
timeTraceProfilerCleanup(). In certain cases timeTraceProfilerCleanup()
was called before temporary file deletion had completed in LLD, which
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Mk/Uses/npm.mk: Quote TMPDIR and WRKDIR in shell comparisons
When TMPDIR is unset, the generated shell command becomes:
if [ != ${WRKDIR} ]; then
and /bin/sh reports:
[: !=: unexpected operator
Quoting both variables fixes the issue.
PR: 297181
Reported by: Shin-ichi Nagamura <core at zsc.jp>
GlobalISel: Don't use GISelMatchGenericTypes for floating point opcodes (#212814)
With GISelMatchGenericTypes, AMDGPU had the same input pattern for
G_ATOMICRMW_FADD that checks for v2s16, so the one that is first
in the tablegen table always fires (it was v2f16 in this case).
Should explicitly check for v2f16/v2bf16.
[LoopIdiom] Update MemorySSA when optimizing CRC with lookup table (#213054)
Although the lookup table optimization of CRC loops inserts a `load`
instruction, MemorySSA is not properly updated, and is oblivious to the
new memory access. Insert a memory use immediately after creating the
`load` instruction, and verify MemorySSA at the end of the optimization
if applicable.
[InlineSpiller][AMDGPU] Implement subreg reload during RA spill
Currently, when a virtual register is partially used, the
entire tuple is restored from the spilled location, even if
only a subset of its sub-registers is needed. This patch
introduces support for partial reloads by analyzing actual
register usage and restoring only the required sub-registers.
This improvement enhances register allocation efficiency,
particularly for cases involving tuple virtual registers.
For AMDGPU, this change brings considerable improvements
in workloads that involve matrix operations, large vectors,
and complex control flows.
[AMDGPU] Test precommit for subreg reload
This test currently fails due to insufficient
registers during allocation. Once the subreg
reload is implemented, it will begin to pass
as the partial reload help mitigate register
pressure.
[CodeGen] Enhance createFrom for sub-reg aware cloning
Instead of just cloning the virtual register, this
function now creates a new virtual register derived
from a subregister class of the original value.
[ubsan] Report specific CFI checks in UBSan summaries (#213224)
Instead of reporting generic `cfi-bad-type` in UBSan summaries for CFI
failures, report the specific CFI check kind (e.g., `cfi-vcall`,
`cfi-nvcall`, `cfi-icall`, `cfi-mfcall`, `cfi-derived-cast`,
`cfi-unrelated-cast`).
This is done by splitting CFIBadType into specific error types in
ubsan_checks.inc, and updating the handlers to report the appropriate
ErrorType based on the check kind. The suppression flag name for all of
them remains `cfi` to maintain backward compatibility.
Also replaces cfi-bad-type expectations in the existing tests.
Assisted-by: Automated tooling, human reviewed.
e1000: restrict conventional PCI DMA to 32 bits
Some conventional PCI e1000 configurations hang when given DMA
addresses above 4 GB, particularly on systems using AMD
HyperTransport-to-PCI bridges. Linux has restricted e1000 to DMA32 in
PCI mode since 2011 for the same failure class in commit
e508be174ad36b0cf9b324cd04978c2b13c21502.
Set iflib's DMA width after determining the negotiated bus type. This
covers descriptor and packet-buffer mappings while preserving 64-bit
DMA for PCI-X and PCIe devices and providing a conditional tunable.
PR: 297064
Reported by: Alexander Leidinger <netchild at FreeBSD.org>
Tested by: Alexander Leidinger <netchild at FreeBSD.org>
MFC after: 1 week
[RISCV] Deduplicate frame base address materializations for large stack frames (#211748)
For large stack frames, `eliminateFrameIndex` materializes the frame
base with a `LUI+ADD` sequence for every frame index access. When
multiple accesses share the same 4096-aligned base, this generates
redundant `LUI+ADD` sequences that `MachineLateInstrsCleanup` cannot
eliminate because it operates on individual instructions.
Introduce `PseudoAddUpperImm` to represent the `LUI+ADD` sequence as a
single pseudo instruction during frame index elimination. This enables
`MachineLateInstrsCleanup` to CSE identical frame base computations
within a basic block. The pseudo is expanded back to `LUI+ADD` in
`RISCVPostRAExpandPseudo`.
This patch improves SPEC CPU2026 `cactus` performance by 18% on the
SpaceMit K3 processor.
### Example
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[mlir][NVVM] Add memory clobber support to inline_ptx and BasicPtxBui… (#212937)
PTX with memory side effects (stores, atomics, mbarrier operations with
acquire/release semantics) emitted through `nvvm.inline_ptx` lowers to
`llvm.inline_asm` with register constraints only. Without a `~{memory}`
clobber, LLVM may reorder memory accesses across the inline assembly.
There was no way to express the clobber through this op or the
`BasicPtxBuilderInterface` machinery.
This patch adds, as discussed with @grypp:
- A `hasMemoryClobber` interface method (default `false`) on
`BasicPtxBuilderOpInterface`; when it returns `true`, `PtxBuilder`
appends `~{memory}` to the constraints of the generated inline assembly,
after all register constraints and tied indices.
- An opt-in `memory_clobber` boolean attribute (default `false`) on
`nvvm.inline_ptx` exposing this. Existing behavior is unchanged unless
the attribute is set to `true`.
For example:
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[mlir][tosa] Switch matmul_t output to bf16 from fp16 (#212970)
Note that this implements the TOSA specification change:
https://github.com/arm/tosa-specification/pull/67
---------
Signed-off-by: Jeremy Johnson <jeremy.johnson at arm.com>
[llvm-profgen] Preserve zero-valued first PT_LOAD address (#212258)
FirstLoadableAddress was initialized with if (!FirstLoadableAddress), so
a valid first PT_LOAD at vaddr 0 was treated as unset and overwritten by
a later segment. Track whether the first loadable segment has been seen
instead.
Assisted by GPT-5
AMDGPU: Add missing mqsad-pk-insts to gfx13 frontend feature map (#213124)
fillAMDGCNFeatureMap omitted mqsad-pk-insts for gfx1310/gfx13-generic,
so clang wrongly rejected __builtin_amdgcn_mqsad_pk_u16_u8 on those
targets even though the backend enables the feature. Add it to the gfx13 case.
Co-authored-by: Claude (Claude-Opus-4.8)
