LLVM/project 4fc585fllvm/test/CodeGen/AMDGPU global-atomicrmw-fadd.ll amdgcn.bitcast.128bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-llvm.amdgcn.image.sample.a16.ll

calling conv update
DeltaFile
+4,190-4,346llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,769-2,019llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+1,592-1,625llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+748-1,428llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+1,308-842llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,248-856llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+11,855-11,116174 files not shown
+32,519-25,134180 files

FreeNAS/freenas a014cabsrc/middlewared/middlewared/test/integration/assets privilege.py, tests/api2 test_account_privilege.py

Remove bogus test
DeltaFile
+1-31tests/api2/test_account_privilege.py
+1-30tests/directory_services/test_activedirectory_privilege.py
+20-0src/middlewared/middlewared/test/integration/assets/privilege.py
+22-613 files

LLVM/project fe6a3afclang/test/CodeGenOpenCL builtins-amdgcn-make-buffer-rsrc.cl, llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp

[AMDGPU] Canonicalize num_records to its actual width in InstCombine

llvm.amdgcn.make.buffer.rsrc is overloaded on the type of its
num_records argument, but the hardware field it ends up in has a fixed
width (32 bits, or 45 bits on gfx1250 and up). Rewrite the intrinsic to
use that width, zero-extending or truncating num_records as needed, so
that IR-level optimizations can see that the extra bits of, for example,
the i64 that Clang emits are not demanded.

Targets that aren't concrete enough for the buffer resource layout to be
known are left alone.

AI disclosure: This was my idea but Claude wrote the code (and I've
tried to tighten up the comments)
DeltaFile
+36-44clang/test/CodeGenOpenCL/builtins-amdgcn-make-buffer-rsrc.cl
+27-27llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+22-12llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+21-1llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+106-844 files

LLVM/project 315c575llvm/test/Transforms/InstCombine/AMDGPU make-buffer-rsrc-num-records.ll

[AMDGPU] Pre-commit tests for num_records canonicalization

Add tests for having InstCombine canonicalize the num_records argument
of llvm.amdgcn.make.buffer.rsrc to the width it will ultimately have,
which lets later passes see that, for example, the high bits of the i64
that Clang emits aren't used.

AI disclosure: Claude generated these and I've looked at them
DeltaFile
+153-0llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+153-01 files

LLVM/project c03943dllvm/test/Transforms/InstCombine/AMDGPU make-buffer-rsrc-num-records.ll

Clean up triples
DeltaFile
+3-3llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+3-31 files

LLVM/project 6e2f9b1mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp, mlir/test/Conversion/AMDGPUToROCDL amdgpu-to-rocdl.mlir

[mlir][AMDGPU] Emit num_records at the buffer resource's actual width

makeBufferRsrc() zero-extended num_records to i64 on targets whose
buffer resource has a 45-bit num_records field, leaving 19 bits that the
hardware will never look at. Emit an i45 instead, which is what
rocdl.make.buffer.rsrc will end up putting in the descriptor anyway, so
that downstream consumers can see that those bits aren't demanded.

While here, factor the i32 and i64 conversion helpers into a shared
convertUnsignedToInt() that takes the target width.

AI disclosure: Claude made this, I looked at and poked the design into
shape.
DeltaFile
+50-25mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
+18-19mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+68-442 files

LLVM/project d996ce7llvm/lib/Target/AMDGPU AMDGPULowerBufferFatPointers.cpp, llvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

[AMDGPU] Use real num_records width in LowerBufferFatPointers

Fix the following edge cases in reasoning about whether a value can be
The out-of-bounds analysis in LowerBufferFatPointers took the
num_records operand of llvm.amdgcn.make.buffer.rsrc at face value, which
went wrong in three ways.

1. The pass would crash if num_records was narrower than the
underlying hardware width.
2. A 45-bit num_records with its high bit set made all offsets look
negative, which, among other things, broke the `(1 << 45) - 1` "no
bounds checking" value.
3. The test for all-1 num_records wasn't accounting for hardware
width, leading to false positives if the num_records field was
narrower tan the underlying field.
4. Don't try to do reasoning about num_records when its width isn't
known.

AI disclosure: Claude found and took a try at fixing these, I've
reviewed
DeltaFile
+199-59llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+19-13llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+218-722 files

LLVM/project f7258eallvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

Update generic target to something better
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+1-11 files

LLVM/project 9dd5690llvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

Update test explanations
DeltaFile
+5-7llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+5-71 files

LLVM/project 8c98f8dllvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

[AMDGPU] Pre-commit num_records of arbitrary width tests for LowerBufferFatPointers

Add tests to ensure that the reasoning for whether an access can be
partially out of bounds and needs to be scalarized work correctly when
num_records has a width different from the hardware width.

AI disclosure: Claude generated these and I've looked at them
DeltaFile
+236-0llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+236-01 files

LLVM/project 0f45834llvm/lib/Target/AMDGPU GCNSubtarget.h

Fix typo

Co-authored-by: Lukas Sommer <lukas.sommer at amd.com>
DeltaFile
+1-1llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-11 files

LLVM/project 048ff2bllvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULowerBufferFatPointers.cpp

[AMDGPU] Track buffer resource num_records width in a subtarget field

Replace the boolean 45-bit-num-records-buffer-resource subtarget
feature's `Has45BitNumRecordsBufferResource` flag with a numeric
`BufferResourceNumRecordsWidth` field.

AI disclosure: Code by Claude, comments and wordings by me
DeltaFile
+24-12llvm/lib/Target/AMDGPU/AMDGPU.td
+13-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+40-155 files

LLVM/project ab896c6clang/lib/Sema SemaTemplateDeduction.cpp SemaConcept.cpp, clang/test/CXX/temp/temp.constr/temp.constr.atomic constrant-satisfaction-conversions.cpp

[Clang] Improve concept diagnostics (#218618)

We used to drop SFINAE errors that occurred during parameter mapping
instantiation
on the floor, making our diagnostics worse for some cases.

This patch corrects that behavior. Moreover it fixes some clients where
the errors were not properly handled for invalid expressions.

Fixes https://github.com/llvm/llvm-project/issues/144053
DeltaFile
+49-62clang/lib/Sema/SemaConcept.cpp
+48-15clang/test/SemaCXX/cxx2c-fold-exprs.cpp
+26-0clang/test/SemaTemplate/concepts.cpp
+4-7clang/lib/Sema/SemaTemplateDeduction.cpp
+4-1clang/test/SemaTemplate/cxx2a-constraint-exprs.cpp
+4-0clang/test/CXX/temp/temp.constr/temp.constr.atomic/constrant-satisfaction-conversions.cpp
+135-859 files not shown
+151-8915 files

FreeBSD/ports 45c06eamath/scilab Makefile, math/scilab/files patch-modules_matio_src_cpp_GetSparseVariable.cpp

math/scilab: chase the upgrade of math/matio to 1.6.0

The recent upgrade of matio broke Scilab, because Scilab only test
the minor version MATIO_RELEASE_LEVEL and not the full string.

Reported by:    pkg-fallout
DeltaFile
+20-0math/scilab/files/patch-modules_matio_src_cpp_GetSparseVariable.cpp
+1-0math/scilab/Makefile
+21-02 files

FreeBSD/src 5db5c82sys/arm/arm machdep.c

arm: Quote diagnostic message

The C standard does not require diagnostic messages to be quoted, but
some tools get confused by unbalanced quotes such as the apostrophe in
“don't”.  Wrap this message in double quotes to resolve the confusion.

Sponsored by:   Klara, Inc.
Sponsored by:   NetApp, Inc.
DeltaFile
+1-1sys/arm/arm/machdep.c
+1-11 files

LLVM/project f67f89bclang/test/CodeGenOpenCL builtins-amdgcn-make-buffer-rsrc.cl, llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp

[AMDGPU] Canonicalize num_records to its actual width in InstCombine

llvm.amdgcn.make.buffer.rsrc is overloaded on the type of its
num_records argument, but the hardware field it ends up in has a fixed
width (32 bits, or 45 bits on gfx1250 and up). Rewrite the intrinsic to
use that width, zero-extending or truncating num_records as needed, so
that IR-level optimizations can see that the extra bits of, for example,
the i64 that Clang emits are not demanded.

Targets that aren't concrete enough for the buffer resource layout to be
known are left alone.

AI disclosure: This was my idea but Claude wrote the code (and I've
tried to tighten up the comments)
DeltaFile
+36-44clang/test/CodeGenOpenCL/builtins-amdgcn-make-buffer-rsrc.cl
+27-27llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+22-12llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+21-1llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+106-844 files

LLVM/project 3753c71llvm/test/Transforms/InstCombine/AMDGPU make-buffer-rsrc-num-records.ll

Clean up triples
DeltaFile
+3-3llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+3-31 files

LLVM/project 2d63213llvm/test/Transforms/InstCombine/AMDGPU make-buffer-rsrc-num-records.ll

[AMDGPU] Pre-commit tests for num_records canonicalization

Add tests for having InstCombine canonicalize the num_records argument
of llvm.amdgcn.make.buffer.rsrc to the width it will ultimately have,
which lets later passes see that, for example, the high bits of the i64
that Clang emits aren't used.

AI disclosure: Claude generated these and I've looked at them
DeltaFile
+153-0llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+153-01 files

LLVM/project 861a0f7llvm/lib/Target/AMDGPU AMDGPULowerBufferFatPointers.cpp, llvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

[AMDGPU] Use real num_records width in LowerBufferFatPointers

Fix the following edge cases in reasoning about whether a value can be
The out-of-bounds analysis in LowerBufferFatPointers took the
num_records operand of llvm.amdgcn.make.buffer.rsrc at face value, which
went wrong in three ways.

1. The pass would crash if num_records was narrower than the
underlying hardware width.
2. A 45-bit num_records with its high bit set made all offsets look
negative, which, among other things, broke the `(1 << 45) - 1` "no
bounds checking" value.
3. The test for all-1 num_records wasn't accounting for hardware
width, leading to false positives if the num_records field was
narrower tan the underlying field.
4. Don't try to do reasoning about num_records when its width isn't
known.

AI disclosure: Claude found and took a try at fixing these, I've
reviewed
DeltaFile
+199-59llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+19-13llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+218-722 files

LLVM/project 30b9fedmlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp, mlir/test/Conversion/AMDGPUToROCDL amdgpu-to-rocdl.mlir

[mlir][AMDGPU] Emit num_records at the buffer resource's actual width

makeBufferRsrc() zero-extended num_records to i64 on targets whose
buffer resource has a 45-bit num_records field, leaving 19 bits that the
hardware will never look at. Emit an i45 instead, which is what
rocdl.make.buffer.rsrc will end up putting in the descriptor anyway, so
that downstream consumers can see that those bits aren't demanded.

While here, factor the i32 and i64 conversion helpers into a shared
convertUnsignedToInt() that takes the target width.

AI disclosure: Claude made this, I looked at and poked the design into
shape.
DeltaFile
+50-25mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
+18-19mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+68-442 files

LLVM/project 36fe541llvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

Update generic target to something better
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+1-11 files

LLVM/project 601b097llvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

[AMDGPU] Pre-commit num_records of arbitrary width tests for LowerBufferFatPointers

Add tests to ensure that the reasoning for whether an access can be
partially out of bounds and needs to be scalarized work correctly when
num_records has a width different from the hardware width.

AI disclosure: Claude generated these and I've looked at them
DeltaFile
+236-0llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+236-01 files

LLVM/project 1d7aa39llvm/lib/Target/AMDGPU GCNSubtarget.h

Fix typo

Co-authored-by: Lukas Sommer <lukas.sommer at amd.com>
DeltaFile
+1-1llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-11 files

LLVM/project b3d3e97llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULowerBufferFatPointers.cpp

[AMDGPU] Track buffer resource num_records width in a subtarget field

Replace the boolean 45-bit-num-records-buffer-resource subtarget
feature's `Has45BitNumRecordsBufferResource` flag with a numeric
`BufferResourceNumRecordsWidth` field.

AI disclosure: Code by Claude, comments and wordings by me
DeltaFile
+24-12llvm/lib/Target/AMDGPU/AMDGPU.td
+13-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+40-155 files

LLVM/project fd3471cllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/X86 intrinsic-cttz-elts.ll

[SelectionDAG] Preserve CTTZ_ELTS lane count during expansion (#217982)

Fixes #216649

`expandCttzElts` derives `VL` from its legalized auxiliary step vector.
When that helper vector is widened for target legality, its lane count
may differ from the logical lane count of the `CTTZ_ELTS` operand.

On X86 with AVX512F, the step vector for a semantic `<4 x i1>` mask is
widened from `v4i8` to `v16i8`. As a result, an all-zero
`llvm.experimental.cttz.elts` input returns 16 instead of the required
result of 4.

Preserve the `ElementCount` from the `CTTZ_ELTS` operand and use it when
materializing `VL`. Auxiliary step-vector legalization can still widen
its representation without changing the logical lane domain of the
operation.

Add AVX512F regression coverage for the affected `v4i1` and `v8i1`
cases.
DeltaFile
+95-0llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll
+5-5llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+100-52 files

LLVM/project 13967c2clang/test/CodeGen/X86 x86_64-union-empty-member-abi.cpp, llvm/lib/ABI/Targets X86.cpp

[LLVMABI] Skip data-free members when reducing a union (#218532)

While implementing union support for ClangIR, I found that
`reduceUnionForX8664` can choose a member holding no data as the type
representing the union. It chooses by alignment and then by size, and an
over-aligned empty class or an array of empty records wins either
comparison, so the coercion comes out wider than Clang's.

Clang does not need this skip because it compares lowered types, where
an empty class is a byte array it can narrow the coercion through. A
record reaching this library has no fields, so there is nothing to
narrow through.

This change skips members holding no data, using `bitsContainNoUserData`
to identify them.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+235-0llvm/unittests/ABI/X86TargetInfoTest.cpp
+41-0clang/test/CodeGen/X86/x86_64-union-empty-member-abi.cpp
+13-0llvm/lib/ABI/Targets/X86.cpp
+1-0llvm/unittests/ABI/CMakeLists.txt
+290-04 files

LLVM/project ab12b86clang/test/CIR/CodeGen attr-noundef.cpp call-conv-lowering-x86_64-byref.cpp

[CIR] Update CHECK lines for the nofreeobj rename

#218404 renamed classic's indirect-argument attribute from nofree to
nofreeobj.  Five OGCG lines across two tests still pinned the
old spelling.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+3-3clang/test/CIR/CodeGen/call-conv-lowering-x86_64-byref.cpp
+2-2clang/test/CIR/CodeGen/attr-noundef.cpp
+5-52 files

LLVM/project 0238b95llvm/include/llvm/MC MCRegisterInfo.h, llvm/unittests/CodeGen MachineInstrTest.cpp

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+20-10llvm/utils/TableGen/RegisterInfoEmitter.cpp
+6-4llvm/include/llvm/MC/MCRegisterInfo.h
+1-1llvm/unittests/CodeGen/MachineInstrTest.cpp
+27-153 files

OPNSense/core b3047e4src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms dialogOneToOneRule.xml dialogNptRule.xml, src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes JsonAuditField.php

Merge remote-tracking branch 'origin/master' into firewall-received-on
DeltaFile
+161-22src/opnsense/mvc/app/models/OPNsense/Firewall/FieldTypes/AliasNameField.php
+147-0src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes/JsonAuditField.php
+75-1src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogSNatRule.xml
+74-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogOneToOneRule.xml
+74-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogNptRule.xml
+74-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogFilterRule.xml
+605-2326 files not shown
+845-10432 files

LLVM/project c7beee7mlir/lib/Dialect/Tensor/Transforms ReshapePatterns.cpp, mlir/test/Dialect/Tensor fold-reassociative-reshapes.mlir

[mlir][tensor] Add FoldExtractSliceOfExpandShape folding pattern (#212974)

Extends Tensor `ReassociativeReshapeFoldingPatterns` by adding a
`FoldExtractSliceOfExpandShape` pattern.

FoldExtractSliceOfExpandShape pattern folds full-slice rank-reducing
extract of expand_shape.

Assisted-by: GPT-5.3-Codex
DeltaFile
+45-7mlir/lib/Dialect/Tensor/Transforms/ReshapePatterns.cpp
+31-0mlir/test/Dialect/Tensor/fold-reassociative-reshapes.mlir
+76-72 files