LLVM/project 8398672llvm/test/CodeGen/LoongArch/lasx/ir-instruction fptrunc.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction fptrunc.ll

[LoongArch][NFC] Pre-commit tests for vector fptrunc from vxf64 to vxf32 (#164058)
DeltaFile
+117-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
+112-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
+229-02 files

LLVM/project 2487d43llvm/lib/Target/LoongArch LoongArchISelLowering.cpp

stricter restrictions on original types
DeltaFile
+5-4llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+5-41 files

LLVM/project e1878d7llvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchLSXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction fptrunc.ll

[LoongArch] Add support for vector FP_ROUND from vxf64 to vxf32

In LoongArch, [x]vfcvt.s.d intstructions require two vector registers
for v4f64->v4f32, v8f64->v8f32 conversions.

This patch handles these cases:
- For FP_ROUND v2f64->v2f32(illegal), add a customized v2f32 widening
  to convert it into a target-specific LoongArchISD::VFCVT.
- For FP_ROUND v4f64->v4f32, on LSX platforms, v4f64 is illegal and will
  be split into two v2f64->v2f32, resulting in two LoongArchISD::VFCVT.
  Finally, they are combined into a single node during combining
  LoongArchISD::VPACKEV. On LASX platforms, v4f64->v4f32 can directly
  lower to vfcvt.s.d in lowerFP_ROUND.
- For FP_ROUND v8f64->v8f32, on LASX platforms, v8f64 is illegal and
  will be split into two v4f64->v4f32 and then combine using
  ISD::CONCAT_VECTORS, so xvfcvt.s.d is generated during its
  combination.
DeltaFile
+131-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+10-38llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
+5-22llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
+7-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+2-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+1-1llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+156-616 files

LLVM/project 2acb741llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx/ir-instruction fptrunc.ll

fixes according reviews
DeltaFile
+4-27llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll
+2-12llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
+9-2llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+15-413 files

LLVM/project 7cb8a80llvm/lib/Target/LoongArch LoongArchLASXInstrInfo.td LoongArchLSXInstrInfo.td, llvm/lib/Target/LoongArch/AsmParser LoongArchAsmParser.cpp

Address wanglei's comments
DeltaFile
+12-24llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+12-24llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+1-4llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+0-1llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+25-534 files

LLVM/project 85f485ellvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lsx/ir-instruction and.ll xor.ll

[LoongArch] Select `V{AND,OR,XOR,NOR}I.B` for bitwise with byte splat immediates

The `V{AND,OR,XOR,NOR}I.B` instructions operate on byte elements and accept
an 8-bit immediate. However, when the same byte splat constant is used with
wider vector element types (e.g. v8i16, v4i32, v2i64), instruction selection
currently falls back to materializing the constant in a temporary register.

```
vrepli.b  -1
vxor.v
```

even though the immediate form is available:

```
vxori.b 255
```

This happens because selectVSplatImm requires the splat bit width to match

    [11 lines not shown]
DeltaFile
+29-2llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+24-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+3-6llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
+3-6llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
+3-6llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
+3-6llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll
+65-2614 files not shown
+102-8520 files

LLVM/project 35b981bllvm/lib/Target/LoongArch LoongArchISelDAGToDAG.cpp

Address wanglei's comments
DeltaFile
+3-4llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+3-41 files

LLVM/project 0c4cb19llvm/lib/Target/LoongArch LoongArchISelDAGToDAG.cpp

Fix a typo
DeltaFile
+1-1llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+1-11 files

LLVM/project a758238llvm/lib/Target/LoongArch LoongArchISelDAGToDAG.cpp LoongArchLSXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction add.ll sub.ll

[LoongArch] Select V{ADD,SUB}I for operations with negative splat immediates

Currently, vector add/sub with a negative splat immediate is lowered as a
vector splat followed by a register-register add, e.g.:

```
vrepli.b $vr1, -1
vadd.b   $vr0, $vr0, $vr1
```

This misses the opportunity to use the more efficient V{ADD,SUB}I instruction
with a positive immediate.

This patch introduces `selectVSplatImmNeg` to detect negative splat
immediates whose negated value fits in a 5-bit unsigned immediate. New
patterns `(Pat{Vr,Vr}Nimm5)` are added to match:

```
add v, splat(-imm)  -->  vsubi v, v, imm

    [7 lines not shown]
DeltaFile
+22-0llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+17-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+5-10llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+5-10llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+5-10llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+5-10llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+59-402 files not shown
+74-408 files

LLVM/project 2bac8d6llvm/test/CodeGen/LoongArch/lasx/ir-instruction nor.ll and.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction nor.ll and.ll

[LoongArch][NFC] Add tests for bitwise with byte splat immediates (#192216)
DeltaFile
+36-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/nor.ll
+36-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/nor.ll
+33-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
+33-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
+33-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
+33-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
+204-02 files not shown
+270-08 files

LLVM/project 7cabc53llvm/test/CodeGen/LoongArch/lasx/ir-instruction add.ll sub.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction add.ll sub.ll

[LoongArch][NFC] Add tests for add/sub with negative splat immediates (#191965)
DeltaFile
+66-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+66-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+66-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+66-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+264-04 files

LLVM/project 6527bf9llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge branch 'main' into users/ylzsx/precommit-fptrunc
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-01,735 files not shown
+976,030-41,5901,741 files

LLVM/project 685ee06utils/bazel/llvm-project-overlay/libc BUILD.bazel

[Bazel] Fixes 7094eb5 (#192584)

This fixes 7094eb52d8cbaa9faeb635bfb6f6c06e6cd52b64.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+12-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+12-01 files

LLVM/project 7094eb5libc/src/__support/threads futex_utils.h raw_rwlock.h, libc/src/__support/threads/darwin futex_utils.h

[libc][threads] adjust futex library and expose requeue API (#192478)

Make futex a common abstraction layer across platforms.
(linux/wasm/macOS/windows/fuchsia all have the support, which we can
align their support later on).

This patch also expose a requeue API that returns ENOSYS on unsupported
platforms. The requeue operation will be needed to reimplement a strict
FIFO style condvar similar to musl.

Additional cleanup is done to change raw syscall return value to
`ErrorOr<int>`.

Assisted-by: Codex with gpt-5.4 medium fast
DeltaFile
+64-29libc/src/__support/threads/linux/futex_utils.h
+54-26libc/src/__support/threads/darwin/futex_utils.h
+80-0libc/test/integration/src/__support/threads/futex_requeue_test.cpp
+37-0libc/test/src/__support/threads/futex_utils_test.cpp
+20-0libc/src/__support/threads/futex_utils.h
+8-7libc/src/__support/threads/raw_rwlock.h
+263-627 files not shown
+305-7313 files

FreeBSD/src 4390c37share/man/man4 rge.4, sys/dev/rge if_rge.c if_rge_sysctl.c

rge: add disable_aspm tunable for PCIe power management

Add a per-interface loader tunable dev.rge.%d.disable_aspm to
disable PCIe ASPM (L0s/L1) and ECPM on the RTL8125/8126/8127.

Disabling ASPM reduces latency at the cost of higher power
consumption. Default is off (ASPM left as configured by BIOS).

Signed-off-by: Christos Longros <chris.longros at gmail.com>

Reviewed by:    adrian
Differential Revision:  https://reviews.freebsd.org/D56103
DeltaFile
+12-16sys/dev/rge/if_rge.c
+9-0share/man/man4/rge.4
+5-0sys/dev/rge/if_rge_sysctl.c
+1-0sys/dev/rge/if_rgevar.h
+27-164 files

FreeBSD/src aae9068sys/dev/asmc asmc.c asmcvar.h

asmc: add automatic voltage/current/power/ambient sensor detection

Apple SMCs contain numerous undocumented voltage, current, power,
and ambient light sensors. This change adds automatic detection
and registration of these sensors as sysctls.

New sysctl trees:
  dev.asmc.0.voltage.*  - Voltage sensors (millivolts)
  dev.asmc.0.current.*  - Current sensors (milliamps)
  dev.asmc.0.power.*    - Power sensors (milliwatts)
  dev.asmc.0.ambient.*  - Ambient light sensors

Implementation:
- Scans all SMC keys at attach time via asmc_key_dump_by_index()
- Identifies sensors by key prefix patterns:
  - Voltage: VC*, VD*, VG*, VP*, VI*
  - Current: I{C,D,G,M,N,O,H,P,B,A,L}*
  - Power:   P{C,D,N,S,T,H,F,Z,z}*
  - Light:   ALV*, ALS*

    [24 lines not shown]
DeltaFile
+435-2sys/dev/asmc/asmc.c
+10-0sys/dev/asmc/asmcvar.h
+445-22 files

LLVM/project 91fcdabmlir/lib/Dialect/MemRef/Transforms FoldMemRefAliasOps.cpp, mlir/test/Dialect/MemRef fold-memref-alias-ops.mlir

[mlir][memref] Remove unit-stride restriction in SubViewOp folding  (#192437)

This PR replaces manual offset/size resolution with `affine::mergeOffsetsSizesAndStrides`, simplifying the code and extending subview-of-subview folding to support non-unit strides.
DeltaFile
+8-26mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
+22-0mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
+30-262 files

LLVM/project 7f6c395llvm/include/llvm/Transforms/IPO LowerTypeTests.h, llvm/lib/Passes PassBuilder.cpp PassRegistry.def

enum

Created using spr 1.3.7
DeltaFile
+20-0llvm/lib/Passes/PassBuilder.cpp
+13-6llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+12-3llvm/include/llvm/Transforms/IPO/LowerTypeTests.h
+3-6llvm/lib/Passes/PassRegistry.def
+1-1llvm/lib/Passes/PassBuilderPipelines.cpp
+49-165 files

OpenBSD/ports fxxUznXnet/ngtcp2 Makefile distinfo

   Update to ngtcp2 1.22.1

   Only code change in the lib cranks buf[1024] to buf[2048] to avoid a
   stack overwrite when qlog is enabled.
   https://github.com/ngtcp2/ngtcp2/releases/tag/v1.22.1
VersionDeltaFile
1.39+2-2net/ngtcp2/Makefile
1.37+2-2net/ngtcp2/distinfo
+4-42 files

OpenBSD/ports lUtam0ndevel/arm-compute-library Makefile distinfo, devel/arm-compute-library/patches patch-SConstruct

   Update arm-compute-library to 53.0.0
VersionDeltaFile
1.26+2-2devel/arm-compute-library/Makefile
1.20+2-2devel/arm-compute-library/distinfo
1.17+1-1devel/arm-compute-library/patches/patch-SConstruct
1.20+1-0devel/arm-compute-library/pkg/PLIST
+6-54 files

OpenBSD/src XXNmJh4usr.bin/ipcs ipcs.c

   In ipcs(1) use shm_cpid to determine whether a shared memory segment is in use.
   As since kern_sysctl.c r1.490 shm_internal is always NULL.

   ok deraadt
VersionDeltaFile
1.29+2-2usr.bin/ipcs/ipcs.c
+2-21 files

LLVM/project fb0861bllvm/lib/Passes PassBuilderPipelines.cpp

comment

Created using spr 1.3.7
DeltaFile
+1-1llvm/lib/Passes/PassBuilderPipelines.cpp
+1-11 files

LLVM/project 62032d3clang/lib/CodeGen BackendUtil.cpp, llvm/include/llvm/Transforms/IPO LowerTypeTests.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+43-47llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+13-14llvm/include/llvm/Transforms/IPO/LowerTypeTests.h
+7-14llvm/lib/Passes/PassBuilderPipelines.cpp
+8-0llvm/lib/Passes/PassRegistry.def
+1-4clang/lib/CodeGen/BackendUtil.cpp
+2-2llvm/test/Other/new-pm-O0-defaults.ll
+74-819 files not shown
+84-9115 files

LLVM/project 27769d7llvm/lib/Target/RISCV RISCVInstrInfo.cpp RISCVInstrInfo.h, llvm/test/CodeGen/RISCV machine-outliner-x5-regsave-rv32e.mir machine-outliner-reserved-regs.mir

[RISCV] Support MachineOutlinerRegSave for RISCV (#191351)

This patch adds support for the RegSave strategy in the RISC-V
MachineOutliner pass. It uses t1–t6 to preserve the t0 value across the
outlined function call when t0 is unavailable. This enables more
potential outlining candidates.

---------

Co-authored-by: Craig Topper <craig.topper at sifive.com>
DeltaFile
+250-0llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave-rv32e.mir
+166-0llvm/test/CodeGen/RISCV/machine-outliner-reserved-regs.mir
+116-0llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave.mir
+90-7llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+6-6llvm/test/CodeGen/RISCV/machine-outliner-call-x5-liveout.mir
+1-0llvm/lib/Target/RISCV/RISCVInstrInfo.h
+629-136 files

FreeNAS/freenas 0afb8e0src/middlewared/middlewared/api/v27_0_0 failover.py failover_disabled_reasons.py, src/middlewared/middlewared/plugins failover.py

Improve some failover API docs and add auditing
DeltaFile
+31-8src/middlewared/middlewared/plugins/failover.py
+28-9src/middlewared/middlewared/api/v27_0_0/failover.py
+31-2src/middlewared/middlewared/api/v27_0_0/failover_disabled_reasons.py
+19-1src/middlewared/middlewared/plugins/failover_/reboot.py
+1-0src/middlewared/middlewared/api/v27_0_0/failover_reboot.py
+110-205 files

LLVM/project 114f662llvm/tools/llvm-readobj ELFDumper.cpp

[llvm-readobj][ELF] Remove redundant error in reportWarning (#192458)
DeltaFile
+1-2llvm/tools/llvm-readobj/ELFDumper.cpp
+1-21 files

OpenZFS/src b3623d1.github/workflows/scripts qemu-1-setup.sh

CI: Do not set scheduler in qemu-1-setup.sh

We've seen some qemu-1-setup failures while trying to change the
runner's block device scheduler value to 'none':

  We have a single 150GB block device
  Setting up swapspace version 1, size = 16 GiB (17179865088 bytes)
  no label, UUID=7a790bfe-79e5-4e38-b208-9c63fe523294
  tee: '/sys/block/s*/queue/scheduler': No such file or directory

Luckily, we don't need to set the scheduler anymore on modern kernels:
https://github.com/openzfs/zfs/issues/9778#issuecomment-569347505

This commit just removes the code that sets the scheduler.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Tony Hutter <hutter2 at llnl.gov>
Closes #18437
DeltaFile
+0-5.github/workflows/scripts/qemu-1-setup.sh
+0-51 files

FreeBSD/src 65ccf92sys/kern vfs_syscalls.c, sys/sys fcntl.h

openat(2): check that userspace pass known and allowed flags

(cherry picked from commit 8a5601cff1ea32ab63df1377f61620e4f91999b3)
DeltaFile
+6-0sys/sys/fcntl.h
+4-1sys/kern/vfs_syscalls.c
+10-12 files

FreeBSD/src ee3ef70lib/libsys fork.2

fork.2: note that all methods to pre-resolve symbols have consequences

(cherry picked from commit 660498986a8e56025d9d2f9c6a0813c09a27ba8e)
DeltaFile
+2-0lib/libsys/fork.2
+2-01 files

FreeBSD/src 803a892include unistd.h

unistd.h: _Fork(2) is required by POSIX 2024

(cherry picked from commit f286933c950f6308117c8400f36f3160f6227491)
DeltaFile
+4-1include/unistd.h
+4-11 files