LLVM/project c2112e9lldb/packages/Python/lldbsuite/test/make Makefile.rules

[lldb][Windows] Fix ECHO_TO_FILE/ECHO_APPEND_FILE (#202612)

The Windows recipes for these macros were `printf "%s\n" $(1)`. The
callers wrap content in single quotes (for the POSIX printf), but the
test recipes run under `cmd.exe` on Windows, which keeps the single
quotes literal and word-splits on spaces, and the bundled `printf`
additionally mangles backslashes and spaces. The result is garbage
generated files (e.g. a modulemap whose first line is `'module`, or a
truncated SDK path from a "Program Files" directory).

Write the file with cmd's `echo` after stripping the callers' single
quotes. `echo` runs in the recipe shell, so unlike GNU make's `$(file
...)` it still works after a preceding `MKDIR_P` in the same recipe.

rdar://179218545
DeltaFile
+2-2lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+2-21 files

OPNSense/core 4223124src/etc/inc interfaces.lib.inc

interfaces: parse ifconfig output despite exit error in legacy_interfaces_details()

Move stderr to /dev/null and always read stdout.  It improves intermittent
issues with ifconfig that will return data but "fail" with a non-zero return
code.

PR: https://github.com/opnsense/src/issues/284
Suggested by: @e-alfred
DeltaFile
+4-12src/etc/inc/interfaces.lib.inc
+4-121 files

LLVM/project 690b0b0llvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlan.h, llvm/test/Transforms/LoopVectorize cast-costs.ll

[LV] Add initial costs for VPInstructionWithType::computeCost (#198291)

I noticed this was previously always returning a cost of 0
due to fear of triggering the (now deleted) legacy/vplan
cost model assert. Since the assert has now been removed
this should be safe to implement properly. I haven't
filled in the costs for all types yet, since there is
currently no way to expose those code paths. I suspect
for things like VPInstruction::StepVector the recipe is
always in the vector preheader and we never ask for its
cost.
DeltaFile
+24-49llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
+25-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+6-6llvm/test/Transforms/LoopVectorize/cast-costs.ll
+7-5llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
+1-4llvm/lib/Transforms/Vectorize/VPlan.h
+2-2llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
+65-661 files not shown
+67-687 files

LLVM/project c6be475llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmin.ll llvm.amdgcn.reduce.fmax.ll

[AMDGPU] Support Wave Reduction intrinsics for half types

Supported Ops: `fmin`, `fmax`, `fadd`, `fsub`.
DeltaFile
+1,587-578llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+1,587-578llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+1,446-378llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+1,429-372llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+18-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+15-3llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+6,082-1,9146 files

LLVM/project ce811aallvm/test/CodeGen/X86 pr53842.ll

[X86] pr53842.ll - add test coverage for ICMP_SGT/SLT cases (#202906)
DeltaFile
+65-2llvm/test/CodeGen/X86/pr53842.ll
+65-21 files

LLVM/project f7bfc6cllvm/lib/Transforms/InstCombine InstCombineCalls.cpp

[InstCombine][NFC] Drop ignore bundles when iterating the bundles (#202903)
DeltaFile
+4-2llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+4-21 files

LLVM/project b7c9fd9llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

[AMDGPU] Support Wave Reduction for i16 types - 3 (#194812)

Supported Ops: `and`, `or`, `xor`.
DeltaFile
+673-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+563-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+563-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+4-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+4-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1,807-4345 files

LLVM/project 1792fcdclang/include/clang/Basic BuiltinsAMDGPU.td, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics

Assisted by - Claude-sonnet:4.6
DeltaFile
+189-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+18-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+9-0clang/include/clang/Basic/BuiltinsAMDGPU.td
+216-03 files

LLVM/project 2157ee5clang/test/Sema wave-reduce-builtins-validate-amdgpu.cl

Missing SEMA tests
DeltaFile
+26-0clang/test/Sema/wave-reduce-builtins-validate-amdgpu.cl
+26-01 files

LLVM/project df98d04llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.or.ll

[AMDGPU] Support Wave Reduction for i16 types - 3

Supported Ops: `and`, `or`, `xor`.
DeltaFile
+673-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+563-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+563-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+4-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+1,807-4345 files

LLVM/project 322f5d0llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] Support Wave Reduction for i16 types - 2 (#194810)

Supported Ops: `add`, `sub`.
DeltaFile
+692-187llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+668-184llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+6-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-2llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+1,372-3754 files

LLVM/project 651afa8lld/ELF Relocations.cpp, lld/test/ELF arm-thunk-overlay-reuse.s aarch64-thunk-bti-overlay-reuse.s

[LLD][ELF] Do not reuse thunks in OVERLAYs (#200415)

We cannot guarantee that a thunk in an OVERLAY will be in memory at the
same time as the caller if the caller is not in the same output section.
It is safe for a caller in an OVERLAY to reuse a thunk in a non-OVERLAY
section as we know that will be in memory. Thunks that are placed
before their target, are alternative entry points and can also be reused.

Resurrect the isThunkSectionCompatible function that was recently
removed as it served a similar purpose for thunks in different
partitions.

Potentially fixes #199966 which mentions a similar problem for sections
assigned to TCM (Tightly Coupled Memory). It should be possible to model
a TCM as an OVERLAY. If not then there may need to be a command-line
option to inhibit thunk sharing across output sections.
DeltaFile
+89-0lld/test/ELF/arm-thunk-overlay-reuse.s
+70-0lld/test/ELF/aarch64-thunk-bti-overlay-reuse.s
+18-1lld/ELF/Relocations.cpp
+177-13 files

LLVM/project e6a70acmlir/include/mlir/Conversion Passes.td, mlir/lib/Conversion/ConvertToEmitC ConvertToEmitCPass.cpp

Revert "[mlir][emitc] Lower multiple results as a struct (#200659)" (#202911)

This reverts commit 1e0a4c7a9154e46ef52a7c5b0ddbca69fbdcfacd.

Failed buildbot:
https://lab.llvm.org/buildbot/#/builders/116/builds/29302
DeltaFile
+25-236mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
+2-96mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
+1-87mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
+0-63mlir/test/Target/Cpp/func.mlir
+5-13mlir/lib/Conversion/ConvertToEmitC/ConvertToEmitCPass.cpp
+0-6mlir/include/mlir/Conversion/Passes.td
+33-5017 files not shown
+39-51213 files

LLVM/project ac0f040orc-rt/include/orc-rt NativeDylibManager.h, orc-rt/lib/executor NativeDylibManager.cpp

[orc-rt] Treat empty path as "process symbols" in NativeDylibManager. (#202905)

NativeDylibManager::load now handles an empty path by returning the
process's global lookup handle (RTLD_DEFAULT on POSIX) directly,
bypassing dlopen and the shutdown-time dlclose registration. This
matches the behavior of OrcTargetProcess's SimpleExecutorDylibManager.
DeltaFile
+20-0orc-rt/unittests/NativeDylibManagerTest.cpp
+17-0orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
+4-6orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
+5-0orc-rt/lib/executor/NativeDylibManager.cpp
+3-0orc-rt/include/orc-rt/NativeDylibManager.h
+49-65 files

LLVM/project 0345e7dllvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.umax.ll llvm.amdgcn.reduce.umin.ll

[AMDGPU] Support Wave Reduction for i16 types - 1 (#194808)

Supported Ops: `min`, `umin`, `max`, `umax`.
16-bit wave reduce ops are promoted to 32-bit
operations before ISEL. From there they use the
existing implementations for 32-bit reductions.

Assisted by - Claude-sonnet:4.6
DeltaFile
+589-137llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+562-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+528-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+528-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+52-21llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+21-0llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+2,280-5666 files

LLVM/project ded7a39llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.or.ll

[AMDGPU] Support Wave Reduction for i16 types - 3 (#194812)

Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+673-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+563-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+563-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+4-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+4-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1,807-4345 files

LLVM/project 15fdf79llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] Support Wave Reduction for i16 types - 2 (#194810)

Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+692-187llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+668-184llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+6-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-2llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+1,372-3754 files

LLVM/project 37931f6llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.umax.ll llvm.amdgcn.reduce.umin.ll

[AMDGPU] Support Wave Reduction for i16 types - 1 (#194808)

Supported Ops: `min`, `umin`, `max`, `umax`.
16-bit wave reduce ops are promoted to 32-bit
operations before ISEL. From there they use the
existing implementations for 32-bit reductions.

Assisted by - Claude-sonnet:4.6
DeltaFile
+589-137llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+562-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+528-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+528-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+52-21llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+21-0llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+2,280-5666 files

NetBSD/pkgsrc-wip 1304b8dbrush-shell DESCR Makefile

brush-shellL cosmetic fix
DeltaFile
+5-2brush-shell/DESCR
+2-2brush-shell/Makefile
+7-42 files

LLVM/project 67fb966flang/include/flang/Semantics symbol.h, flang/lib/Lower/OpenMP OpenMP.cpp

[flang][OpenMP] Unify groupprivate device_type handling with declare_target
DeltaFile
+25-24flang/lib/Semantics/resolve-directives.cpp
+11-15flang/lib/Lower/OpenMP/OpenMP.cpp
+9-12flang/lib/Semantics/mod-file.cpp
+12-8flang/lib/Semantics/symbol.cpp
+9-9flang/include/flang/Semantics/symbol.h
+66-685 files

FreeBSD/ports 72920c7security/openssl pkg-message distinfo

security/openssl30: Security update to 3.0.21

Security:       259b562f-64ab-11f1-8607-8447094a420f
MFH:            2026Q2
DeltaFile
+22-0security/openssl/pkg-message
+3-3security/openssl/distinfo
+1-1security/openssl/Makefile
+26-43 files

FreeBSD/ports 29d6a22security/openssl35 pkg-message distinfo

security/openssl35: Security update to 3.5.7

Security:       259b562f-64ab-11f1-8607-8447094a420f
MFH:            2026Q2
DeltaFile
+20-0security/openssl35/pkg-message
+3-3security/openssl35/distinfo
+1-1security/openssl35/Makefile
+24-43 files

LLVM/project 95fd258llvm/lib/Target/AMDGPU/Utils AMDGPUHWEvents.cpp

Comment
DeltaFile
+11-14llvm/lib/Target/AMDGPU/Utils/AMDGPUHWEvents.cpp
+11-141 files

LLVM/project 05df7bbllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUHWEvents.cpp AMDGPUHWEvents.h

[AMDGPU][InsertWaitCnts] Move HWEvent analysis code

Building up on the previous RFC, if it is accepted:
Move the code that maps a MachineInstr to HWEventSet to a separate file.

This should be NFC.
DeltaFile
+164-0llvm/lib/Target/AMDGPU/Utils/AMDGPUHWEvents.cpp
+3-116llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+6-0llvm/lib/Target/AMDGPU/Utils/AMDGPUHWEvents.h
+173-1163 files

LLVM/project de477b6llvm/lib/Target/AMDGPU/Utils AMDGPUHWEvents.h

fmt
DeltaFile
+2-1llvm/lib/Target/AMDGPU/Utils/AMDGPUHWEvents.h
+2-11 files

LLVM/project 51fb7eellvm/lib/Target/SPIRV SPIRVCommandLine.cpp

[SPIR-V] Remove duplicate SPV_INTEL_int4 extension map entry (#202871)
DeltaFile
+0-1llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+0-11 files

LLVM/project 658bcd6llvm/lib/Target/AMDGPU/Utils AMDGPUHWEvents.cpp

Comment
DeltaFile
+11-14llvm/lib/Target/AMDGPU/Utils/AMDGPUHWEvents.cpp
+11-141 files

LLVM/project 441bcd5llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUHWEvents.cpp AMDGPUHWEvents.h

[AMDGPU][InsertWaitCnts] Move HWEvent analysis code

Building up on the previous RFC, if it is accepted:
Move the code that maps a MachineInstr to HWEventSet to a separate file.

This should be NFC.
DeltaFile
+164-0llvm/lib/Target/AMDGPU/Utils/AMDGPUHWEvents.cpp
+3-116llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+6-0llvm/lib/Target/AMDGPU/Utils/AMDGPUHWEvents.h
+173-1163 files

LLVM/project c13aa46llvm/lib/Target/AMDGPU/Utils AMDGPUHWEvents.cpp AMDGPUHWEvents.h

Comment
DeltaFile
+0-5llvm/lib/Target/AMDGPU/Utils/AMDGPUHWEvents.cpp
+3-1llvm/lib/Target/AMDGPU/Utils/AMDGPUHWEvents.h
+3-62 files

OPNSense/tools f58e1f3config/26.1 base.plist.amd64

config: rebase for upcoming 26.1.10
DeltaFile
+2-0config/26.1/base.plist.amd64
+2-01 files