LLVM/project 1cc9a8dllvm/test/tools/dsymutil odr-two-units-in-single-file.test, llvm/test/tools/dsymutil/AArch64 typedefs-with-same-name.test

[dsymutil] Relax tests to accept both linker outputs (#195354)

Remove the FIXMEs from tests whose divergence between the classic and
parallel linkers was cosmetic. Typical relaxations consist of using
CHECK-DAG for reordered attributes and allowing DIE and string offsets
to differ.
DeltaFile
+18-15llvm/test/tools/dsymutil/X86/odr-two-units-in-single-file.test
+19-10llvm/test/tools/dsymutil/AArch64/typedefs-with-same-name.test
+16-12llvm/test/tools/dsymutil/X86/union-fwd-decl.test
+13-9llvm/test/tools/dsymutil/odr-two-units-in-single-file.test
+9-6llvm/test/tools/dsymutil/X86/keep-func.test
+9-5llvm/test/tools/dsymutil/X86/objc.test
+84-573 files not shown
+98-679 files

GhostBSD/gib 9bad5b3. setup.py, src use_zfs.py

Merge pull request #88 from ghostbsd/68-feature-full-system-encryption-using-geli

Rework ZFS configuration page and fix GELI encryption with swap
DeltaFile
+183-339src/use_zfs.py
+1-1setup.py
+184-3402 files

LLVM/project df7408fllvm/lib/Target/SystemZ SystemZOperands.td

Also change to FPImmLeaf.
DeltaFile
+2-2llvm/lib/Target/SystemZ/SystemZOperands.td
+2-21 files

LLVM/project 82bf5e8compiler-rt/lib/ubsan ubsan_handlers.cpp, compiler-rt/test/cfi mfcall.cpp

[LowerTypeTests] Add debug info to jump table entries (#194493)

[LowerTypeTests] Add debug info to jump table entries (#192736)
    
When Control Flow Integrity (CFI) is enabled, jump tables are used to
redirect indirect calls. Previously, these jump table entries lacked
debug information, making it difficult for profilers and debuggers to
attribute execution time correctly.

Now stack trace, when stopped on jump table entry will looks like this:
```
#0: c::c() (.cfi_jt) at sanitizer/ubsan_interface.h:0:0
#1: __ubsan_check_cfi_icall_jt at sanitizer/ubsan_interface.h:0
```

Following up on previous attempts #192736 and #193670, this PR is
essentially #192736 but with the `(.cfi_jt)` and
`__ubsan_check_cfi_icall_jt`
frames swapped. While the specific order of `__ubsan_check_cfi_icall_jt`

    [5 lines not shown]
DeltaFile
+69-4llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+27-9llvm/test/Transforms/LowerTypeTests/x86-jumptable-dbg.ll
+29-1compiler-rt/lib/ubsan/ubsan_handlers.cpp
+14-5llvm/test/Transforms/LowerTypeTests/aarch64-jumptable-dbg.ll
+2-2compiler-rt/test/cfi/mfcall.cpp
+1-1compiler-rt/test/cfi/cross-dso/icall/diag.cpp
+142-222 files not shown
+144-248 files

LLVM/project 29e48d9clang/test/AST ast-dump-templates.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+648-9,301clang/test/AST/ast-dump-templates.cpp
+4,811-4,818llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+4,652-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+42,104-22,9078,095 files not shown
+397,644-203,3128,101 files

LLVM/project 58f6727clang/test/AST ast-dump-templates.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+648-9,301clang/test/AST/ast-dump-templates.cpp
+4,811-4,818llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+4,652-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+42,104-22,9078,095 files not shown
+397,644-203,3118,101 files

LLVM/project 073f765clang/test/AST ast-dump-templates.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+648-9,301clang/test/AST/ast-dump-templates.cpp
+4,811-4,818llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+4,652-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+42,104-22,9078,098 files not shown
+397,757-203,3348,104 files

LLVM/project 73f78fbclang/test/AST ast-dump-templates.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+648-9,301clang/test/AST/ast-dump-templates.cpp
+4,811-4,818llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+4,652-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+42,104-22,9078,097 files not shown
+397,721-203,3018,103 files

LLVM/project a671e79clang-tools-extra/clang-tidy/readability RedundantTypenameCheck.cpp, clang/docs ReleaseNotes.rst

[clang] Implement CWG2413 (implicit `typename` in conversion operators) (#195207)

Link: [CWG2413](https://wg21.link/cwg2413). This DR was resolved by
[P1787R6](https://wg21.link/P1787R6) by adding the following wording to
[[temp.res.general]/4](https://eel.is/c++draft/temp.res.general#4):

> A [type-only
context](https://eel.is/c++draft/temp.res.general#def:context,type-only)
is defined as follows: A qualified or unqualified name is said to be in
a type-only context if it is the terminal name of
> - ...
> - a [type-specifier](https://eel.is/c++draft/dcl.type.general#nt:type-specifier) of a
>   - ...
> - [conversion-type-id](https://eel.is/c++draft/class.conv.fct#nt:conversion-type-id),

Towards #54150.
DeltaFile
+14-4clang/test/CXX/drs/cwg24xx.cpp
+1-4clang/lib/Parse/ParseDecl.cpp
+2-2clang/test/CXX/temp/temp.res/p4.cpp
+3-0clang/docs/ReleaseNotes.rst
+2-1clang-tools-extra/clang-tidy/readability/RedundantTypenameCheck.cpp
+1-1clang/www/cxx_dr_status.html
+23-121 files not shown
+24-137 files

LLVM/project 7c881ddclang/lib/CIR/CodeGen CIRGenBuiltinRISCV.cpp, clang/test/CIR/CodeGenBuiltins/RISCV riscv-zbkx.c

[CIR][RISCV] Support zbkx builitin codegen (#195211)

Include 4 builtins: __builtin_riscv_xperm4_32,
__builtin_riscv_xperm4_64, __builtin_riscv_xperm8_32,
__builtin_riscv_xperm8_64.
DeltaFile
+64-0clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zbkx.c
+8-2clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+72-22 files

LLVM/project 14ea3a1mlir/include/mlir/Dialect/LLVMIR ROCDLOps.td, mlir/test/Dialect/LLVMIR rocdl.mlir

[mlir][ROCDL] Add rocdl.wave.barrier (#195357)

Co-authored-by: Claude Opus 4.7 (1M context) <noreply at anthropic.com>
DeltaFile
+13-0mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+7-0mlir/test/Target/LLVMIR/rocdl.mlir
+6-0mlir/test/Dialect/LLVMIR/rocdl.mlir
+26-03 files

LLVM/project a235362clang/include/clang/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis SourcePassAnalysis.h

improve doc/comments
DeltaFile
+11-7clang/include/clang/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis/SourcePassAnalysis.h
+11-71 files

FreeBSD/ports a47da9fwww/gitlab-workhorse/files patch-internal_gitaly_blob.go

www/gitlab-workhorse: fix build on armv7

This cast is a no-op on 64 bit platforms and prevents a type error
on 32-bit platforms.

Approved by:    portmgr (build fix blanket)
PR:             2026Q2

(cherry picked from commit 4731beeec6f8dad167fa3b3ff8d4848aea26c2fc)
DeltaFile
+11-0www/gitlab-workhorse/files/patch-internal_gitaly_blob.go
+11-01 files

FreeBSD/ports e244144devel/gitaly/files patch-internal_command_command.go

devel/gitaly: fix build on armv7

Apparently these are not int64 on 32-bit platforms.

Approved by:    portmgr (build fix blanket)
MFH:            2026Q2

(cherry picked from commit e665c2bc9970aebba5a2a021092b0ca753204f84)
DeltaFile
+17-0devel/gitaly/files/patch-internal_command_command.go
+17-01 files

LLVM/project 8f46a9dllvm/test/tools/llvm-profgen filter-build-id.test, llvm/test/tools/llvm-profgen/Inputs buildid-cs-noprobe.aggperfscript buildid-cs-noprobe.perfscript

[llvm-profgen] Support [buildid:]0xaddr format in perfscript input (#190863)

Add support for optional build ID prefix in perfscript addresses,
following the format buildid:0xhexaddr. This enables multi-DSO profiling
with a single input file: each address optionally carries a build ID,
and profgen filters addresses by matching the binary's build ID.

--filter-build-id=<hex> CLI option overrides auto-detected build ID.
DeltaFile
+58-13llvm/tools/llvm-profgen/PerfReader.cpp
+57-0llvm/test/tools/llvm-profgen/filter-build-id.test
+11-0llvm/test/tools/llvm-profgen/Inputs/buildid-cs-noprobe.aggperfscript
+9-0llvm/test/tools/llvm-profgen/Inputs/buildid-cs-noprobe.perfscript
+135-134 files

LLVM/project 627813cclang/test/CIR/CodeGenCUDA address-spaces.cu

Fix cc mismatch
DeltaFile
+1-1clang/test/CIR/CodeGenCUDA/address-spaces.cu
+1-11 files

LLVM/project ff91bf8lldb/include/lldb/Symbol VariableList.h, lldb/source/Symbol VariableList.cpp

[lldb] Make VariableList::FindVariable const (NFC) (#195355)

I was surprised to find `FindVariable` was not `const`. While making it
`const`, I also replaced the iterator based loop with a ranged based
loop.
DeltaFile
+12-24lldb/source/Symbol/VariableList.cpp
+3-4lldb/include/lldb/Symbol/VariableList.h
+15-282 files

LLVM/project dfb7a66clang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp

fix fmt
DeltaFile
+4-5clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+4-51 files

LLVM/project 25af42dclang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp, clang/test/CIR/CodeGenCUDA device-stub.cu

[CIR][HIP] Handle HIP module constructor and destructor emission
DeltaFile
+147-5clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+121-0clang/test/CIR/CodeGenCUDA/device-stub.cu
+268-52 files

FreeBSD/ports e665c2bdevel/gitaly/files patch-internal_command_command.go

devel/gitaly: fix build on armv7

Apparently these are not int64 on 32-bit platforms.

Approved by:    portmgr (build fix blanket)
MFH:            2026Q2
DeltaFile
+17-0devel/gitaly/files/patch-internal_command_command.go
+17-01 files

FreeBSD/ports 4731beewww/gitlab-workhorse/files patch-internal_gitaly_blob.go

www/gitlab-workhorse: fix build on armv7

This cast is a no-op on 64 bit platforms and prevents a type error
on 32-bit platforms.

Approved by:    portmgr (build fix blanket)
PR:             2026Q2
DeltaFile
+11-0www/gitlab-workhorse/files/patch-internal_gitaly_blob.go
+11-01 files

LLVM/project 1baf1a0utils/bazel/llvm-project-overlay/llvm/unittests BUILD.bazel

[Bazel] Fixes 30463fb (#195375)

This fixes 30463fbc4cd49bc1caa02bf799da5226dd5d7927.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
+1-01 files

LLVM/project d073a10llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

rebase

Created using spr 1.3.4
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-010,333 files not shown
+1,452,699-291,86310,339 files

LLVM/project b6af213llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-010,333 files not shown
+1,452,699-291,86310,339 files

LLVM/project 45b1195llvm/tools/llvm-profgen PerfReader.cpp PerfReader.h

[llvm-profgen][NFC] Reuse isLBRSample (#191595)

Replace `StringRef::starts_with(" 0x")` calls with explicit
`isLBRSample` checks.
This is needed to support buildid-prefixed addresses in a follow-up
#190863.
DeltaFile
+9-7llvm/tools/llvm-profgen/PerfReader.cpp
+1-1llvm/tools/llvm-profgen/PerfReader.h
+10-82 files

LLVM/project 8fec6f4lld/MachO ConcatOutputSection.cpp

Avoid calling markBranchAsResolved() when we discover a thunk in range

The only way for a thunk to be in range is if we created one. In that
case, we already call thunkInfo.pendingBranches.clear() so there is no
need to remove this branch.
DeltaFile
+4-5lld/MachO/ConcatOutputSection.cpp
+4-51 files

Linux/linux f1a5e78drivers/gpu/drm/amd/amdgpu gfx_v6_0.c amdgpu_kms.c, drivers/gpu/drm/amd/display/dc/bios bios_parser.c

Merge tag 'drm-fixes-2026-05-02' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "Fixes for rc2, the usual amdgpu/xe double header, I think xe had a
  couple of weeks combined due to some maintainer access issues,
  otherwise there's just a few misc fixes and documentation fixups.

  core and helpers:
   - calculate framebuffer geometry with format helpers
   - fix docs

  amdgpu:
   - GFX12 fix for CONFIG_DRM_DEBUG_MM configs
   - Fix DC analog support
   - Userq fixes
   - GART placement fix
   - Aldebaran SMU fixes
   - AMDGPU_INFO_READ_MMR_REG fix
   - UVD 3.1 fix

    [64 lines not shown]
DeltaFile
+403-0drivers/gpu/drm/xe/xe_mem_pool.c
+59-35drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+72-1drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+66-0drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+24-33drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+31-25drivers/gpu/drm/xe/xe_migrate.c
+655-9482 files not shown
+1,085-26988 files

LLVM/project 80c4302llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

rebase

Created using spr 1.3.4
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-010,333 files not shown
+1,452,705-291,87710,339 files

LLVM/project 2203242llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-010,333 files not shown
+1,452,705-291,87710,339 files

LLVM/project f089c0fllvm/tools/llvm-profgen PerfReader.cpp

[llvm-profgen][NFC] Factor out parseAddress (#191594)

Replace `StringRef::getAsInteger(16)` calls with explicit `parseAddress`
to make it easier to support buildid-prefixed addresses in a follow-up
(#190863).
DeltaFile
+12-5llvm/tools/llvm-profgen/PerfReader.cpp
+12-51 files