FreeBSD/ports 1cb3221www/forgejo-lts distinfo Makefile

www/forgejo-lts: Update to 11.0.13

Changelog:
* https://codeberg.org/forgejo/forgejo/src/branch/forgejo/release-notes-published/11.0.13.md

MFH:            2026Q2
(cherry picked from commit 5c4949187b0cee97d37285aeec4d29dbe91d036f)
DeltaFile
+3-3www/forgejo-lts/distinfo
+1-2www/forgejo-lts/Makefile
+4-52 files

FreeBSD/ports 5e28a91www/forgejo distinfo Makefile

www/foregjo: Update to 14.0.5

Changelog:
* https://codeberg.org/forgejo/forgejo/src/branch/forgejo/release-notes-published/14.0.5.md

MFH:            2026Q2
(cherry picked from commit ebe4b4ee79ce847f736b39ede67058848ca4d69d)
DeltaFile
+3-3www/forgejo/distinfo
+1-2www/forgejo/Makefile
+4-52 files

FreeBSD/ports 5c49491www/forgejo-lts distinfo Makefile

www/forgejo-lts: Update to 11.0.13

Changelog:
* https://codeberg.org/forgejo/forgejo/src/branch/forgejo/release-notes-published/11.0.13.md

MFH:            2026Q2
DeltaFile
+3-3www/forgejo-lts/distinfo
+1-2www/forgejo-lts/Makefile
+4-52 files

FreeBSD/ports ebe4b4ewww/forgejo distinfo Makefile

www/foregjo: Update to 14.0.5

Changelog:
* https://codeberg.org/forgejo/forgejo/src/branch/forgejo/release-notes-published/14.0.5.md

MFH:            2026Q2
DeltaFile
+3-3www/forgejo/distinfo
+1-2www/forgejo/Makefile
+4-52 files

FreeNAS/freenas 5e8b440src/middlewared/middlewared/plugins/failover_ event.py, src/middlewared/middlewared/plugins/iscsi_ lio.py alua.py

Add middleware support for LIO ALUA HA

Wire up the middleware side of LIO ALUA high-availability: load
lio_ha.ko with per-node addresses on service start, manage the
4-row ALUA state table (MASTER/BACKUP × synced/not-synced) across
failover events, clean up STANDBY configfs on pool export, and
add pre-flight validation that targets have static initiator ACLs
before ALUA can be enabled.
DeltaFile
+258-53src/middlewared/middlewared/utils/lio/config.py
+179-1src/middlewared/middlewared/plugins/iscsi_/lio.py
+62-9src/middlewared/middlewared/plugins/iscsi_/alua.py
+33-21src/middlewared/middlewared/plugins/failover_/event.py
+34-19src/middlewared/middlewared/plugins/iscsi_/iscsi_global.py
+28-0src/middlewared/middlewared/plugins/iscsi_/global_linux.py
+594-1033 files not shown
+628-1039 files

LLVM/project a8f9baellvm/lib/Target/AMDGPU SIProgramInfo.cpp

[NFC] typo fixes (#194908)
DeltaFile
+3-3llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
+3-31 files

FreeNAS/freenas f932bf0src/middlewared/middlewared/alert/source smart.py

use latest test instead of oldest when checking ATA SMART alerts
DeltaFile
+3-1src/middlewared/middlewared/alert/source/smart.py
+3-11 files

LLVM/project 202adc3llvm/include/llvm/Support DebugCounter.h, llvm/unittests/Support DebugCounterTest.cpp

[Support] Introduce a function to reset all debug counters (#194864)

This PR adds a function to reset all debug counters, and extends the
unit test to verify that the debug counters are reset as expected. This
is required for running tools repeatedly in the same process.
DeltaFile
+13-0llvm/include/llvm/Support/DebugCounter.h
+13-0llvm/unittests/Support/DebugCounterTest.cpp
+26-02 files

LLVM/project 4acbff3clang/lib/CodeGen CGCleanup.cpp CGExprCXX.cpp, clang/test/CodeGen windows-seh-EHa-TryInFinally.cpp

[WinEH] Fix crash when deleting C++ objects inside SEH __try (#180144)

Introduce a dedicated cleanup flag for SEH __finally blocks and use it
to separate SEH try cleanup emission from C++ object cleanup emission

This prevents __finally cleanups from emitting seh.scope.begin/end and
keeps destructor/delete cleanups paired with seh.scope markers

Fix #109576
DeltaFile
+117-6clang/test/CodeGen/windows-seh-EHa-TryInFinally.cpp
+15-10clang/lib/CodeGen/CGCleanup.cpp
+25-0clang/test/CodeGenCXX/exceptions-seh.cpp
+12-0clang/lib/CodeGen/CGExprCXX.cpp
+7-0clang/lib/CodeGen/CGCleanup.h
+4-2clang/lib/CodeGen/CGException.cpp
+180-181 files not shown
+183-187 files

LLVM/project 4d7c1c6llvm/cmake config-ix.cmake, llvm/cmake/modules FindLibXml2.cmake

[cmake] Fix find libxml2 for Windows static libraries (#194894)

* Add the usual Windows static library name "libxml2s"
* Windows build with static libxml2 requires compiler define
DeltaFile
+3-0llvm/cmake/modules/FindLibXml2.cmake
+1-0llvm/cmake/config-ix.cmake
+4-02 files

LLVM/project 5193332clang/lib/CIR/CodeGen CIRGenExprScalar.cpp, clang/test/CIR/CodeGen vector-ext.cpp vector.cpp

[CIR] Ternary expression for VectorType with vector cond (#194128)

Support Ternary expression for VectorType with vector condition

Issue #192311
DeltaFile
+42-0clang/test/CIR/CodeGen/vector-ext.cpp
+42-0clang/test/CIR/CodeGen/vector.cpp
+3-3clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+87-33 files

LLVM/project 1242f93llvm/docs LangRef.rst TransformMetadata.rst, llvm/lib/Transforms/Scalar WarnMissedTransforms.cpp

Revert "[LoopVectorize] Add metadata to distinguish vectorized loop body from scalar remainder (#190258)" (#194901)

Reverts llvm/llvm-project#190258

This commit is causing crashes on the `intel-sycl-gpu` buildbot:
https://lab.llvm.org/buildbot/#/builders/225/builds/7157

The crash is a SEGFAULT in
`LoopVectorizationPlanner::updateLoopMetadataAndProfileInfo` when
optimization remarks are enabled
(`-pass-remarks-analysis=loop-vectorize`). Reverting while investigating
the root cause.
DeltaFile
+0-120llvm/test/Transforms/LoopTransformWarning/vectorizer-loop-kind-unroll-warning.ll
+0-110llvm/test/Transforms/LoopUnroll/vectorizer-loop-kind-remarks.ll
+0-42llvm/docs/LangRef.rst
+0-21llvm/docs/TransformMetadata.rst
+3-10llvm/lib/Transforms/Scalar/WarnMissedTransforms.cpp
+0-12llvm/lib/Transforms/Utils/LoopUtils.cpp
+3-3155 files not shown
+9-34611 files

LLVM/project 27b8441llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP][NFC]Fix building on windows, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194903
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4-41 files

LLVM/project ff8abfallvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-trunc-vp.ll vtrunc-vp.ll

[RISCV] Remove codegen for vp_trunc (#194886)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off vp_truncate from #179622.
DeltaFile
+148-687llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
+59-156llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
+8-128llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+23-26llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
+12-13llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
+12-12llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
+262-1,0227 files not shown
+283-1,06313 files

NetBSD/src UA7Kbuksys/arch/x86/x86 via_padlock.c

   Update to match recent cryptodev update

   <opencrypto/cryptodev.h> recently changed a bunch of fields from
   signed to unsigned.   To avoid gcc stupidly complaining about
   comparisons of different signedness ints (I mean, how can

        for (i = 0; i < unsigned_thing; i++)

   ever see i become negative?) change i from int to unsigned int.

   Should fix the i386 build.
VersionDeltaFile
1.38+4-3sys/arch/x86/x86/via_padlock.c
+4-31 files

LLVM/project 6a82589clang/unittests/Lex ModuleMapTest.cpp

Remove an unused include which causes Bazel dep-check failure (#194902)
DeltaFile
+0-1clang/unittests/Lex/ModuleMapTest.cpp
+0-11 files

LLVM/project e6d46f1llvm/test/Transforms/LoopVectorize uniform_across_vf_induction2.ll uniform_across_vf_induction1_lshr.ll, llvm/test/Transforms/LoopVectorize/AArch64 scalable-strict-fadd.ll

[VPlan] Expand DerivedIV into executable recipes (#187589)

This allows us to strip DerivedIVRecipe::execute, and remove the
dependency on emitTransformedIndex. It allows us to benefit from
existing simplifications in VPlan.
DeltaFile
+636-636llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
+288-288llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
+228-228llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
+115-115llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
+66-68llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-hoist-load-across-store.ll
+58-58llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
+1,391-1,39399 files not shown
+1,978-2,126105 files

NetBSD/pkgsrc TyYTSf1doc TODO

   TODO: remove qgis 4.0 because it is not yet stable
VersionDeltaFile
1.27175+1-2doc/TODO
+1-21 files

NetBSD/pkgsrc b30L3Mrdoc CHANGES-2026

   doc: Updated geography/qgis to 3.44.9
VersionDeltaFile
1.2681+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc kr1KWYLgeography/qgis distinfo Makefile

   geography/qgis: Update to 3.44.9

   Upstream NEWS: micro release
VersionDeltaFile
1.89+4-4geography/qgis/distinfo
1.269+2-2geography/qgis/Makefile
1.37+2-1geography/qgis/PLIST
+8-73 files

FreeBSD/src 6883b12sys/netinet in_pcb.c in_pcb.h

inpcb: allow to specify different sizes for port and load balance hashes

Understand zero size as instruction to not allocate the hash.  Do not
allocate both hashes for rawip(4).  There are no functional changes to TCP
or UDP.

Reviewed by:            markj
Differential Revision:  https://reviews.freebsd.org/D56705
DeltaFile
+25-12sys/netinet/in_pcb.c
+3-2sys/netinet/in_pcb.h
+3-2sys/netinet/udp_usrreq.c
+1-1sys/netinet/tcp_subr.c
+1-1sys/netinet/raw_ip.c
+33-185 files

LLVM/project e784c7dllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

[RISCV] Fix crashes and add RV32 RUN line to rvp-simd-64.ll (#194782)

Prevent combinePExtTruncate from forming RISCVISD nodes with illegal
type. Remove unnecessary call to getSimpleVT().

Legalize shift amount when custom legalizing i64 shifts.
SelectionDAGBuilder usually pre-legalizes shift amounts. If we scalarize
a vXi64 vector shift the shift amount will be i64.
DeltaFile
+3,250-1,325llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+12-4llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+3,262-1,3292 files

FreeBSD/src 9b8eb70sys/netinet in_pcb.c, sys/netinet6 in6_pcb.c in6_pcb.h

inpcb: improve some internal function names

The 'hash' subword doesn't bring any additional information.  All inpcb
lookup functions operate on hashes.

For lookup functions that work on either exact hash or wild hash just
perform s/hash_//.  Rename in_pcblookup_hash() into
in_pcblookup_with_lock(), emphasizing its difference to
in_pcblookup_smr().  Rename in_pcblookup_hash_locked() to
in_pcblookup_internal(), as it doesn't return a locked inpcb and is used
only for internal purposes.  Note that the IPv6 sibling of this function
already lives by name in6_pcblookup_internal().  Some future changes will
make such naming more justified.

No functional change.

Reviewed by:            pouria, markj
Differential Revision:  https://reviews.freebsd.org/D56482
DeltaFile
+28-25sys/netinet/in_pcb.c
+22-24sys/netinet6/in6_pcb.c
+1-1sys/netinet6/in6_pcb.h
+51-503 files

LLVM/project 1230cfdllvm/test/CodeGen/AMDGPU ptr-arg-dbg-value.ll, llvm/test/CodeGen/BPF/CORE offset-reloc-basic.ll

[AMDGPU] Propagate debug info to constant materialization instr (#192669)

Set the debug location on non-target constant nodes so that the
resulting machine instructions inherit the correct source location.
DeltaFile
+5-4llvm/test/DebugInfo/COFF/jump-table-with-indirect-ptr-null.ll
+4-4llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
+3-3llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
+2-2llvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll
+1-1llvm/test/DebugInfo/AMDGPU/debug-loc-copy.ll
+1-1llvm/test/DebugInfo/ARM/single-constant-use-preserves-dbgloc.ll
+16-151 files not shown
+18-157 files

NetBSD/pkgsrc 9xu5zS8doc CHANGES-2026

   doc: Updated sysutils/htop to 3.5.1
VersionDeltaFile
1.2680+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc sViak3asysutils/htop distinfo Makefile

   sysutils/htop: Update to 3.5.1

   Changes since 3.4.1:

   What's new in version 3.5.1

     * Consolidate ClockMeter code into DateTimeMeter code
     * Darwin: Fix unsigned underflow in memory meter on ARM64 (Apple
       Silicon 16K pages showing ~64TB used)
     * Linux/PCP: Replace M_SHARE (SHR) with M_PRIV (PRIV) in default
       Main screen columns
     * PCP: Fix dynamic screen column (instance) sorting (incorrect
       cast and field offsets)
     * PCP: Fix units used when printing M_PRIV memory column values
     * PCP: Add Darwin swap metric values and a fallback on Linux for
       SwapMeter
     * Fix null pointer dereference in actionBacktrace() (GCC LTO -O2
       -flto, Ubuntu 24.04)
     * Make search function activate following on find consistently

    [123 lines not shown]
VersionDeltaFile
1.29+4-4sysutils/htop/distinfo
1.38+2-2sysutils/htop/Makefile
+6-62 files

FreeBSD/ports d80fc2csysutils/vobcopy distinfo Makefile, sysutils/vobcopy/files patch-vobcopy.c patch-Makefile.am

sysutils/vobcopy: Update to 1.2.2
DeltaFile
+1-55sysutils/vobcopy/files/patch-vobcopy.c
+3-3sysutils/vobcopy/distinfo
+2-2sysutils/vobcopy/files/patch-Makefile.am
+1-1sysutils/vobcopy/Makefile
+7-614 files

LLVM/project 70a26a2llvm/docs LangRef.rst TransformMetadata.rst, llvm/lib/Transforms/Scalar WarnMissedTransforms.cpp

[LoopVectorize] Add metadata to distinguish vectorized loop body from scalar remainder (#190258)

Add two new loop metadata attributes — `llvm.loop.vectorize.body` and
`llvm.loop.vectorize.epilogue` — that the loop vectorizer sets on the
generated vector loop and epilogue loop respectively. The metadata is
only emitted when optimization remarks are enabled (`ORE->enabled()`),
so it has zero cost in normal compilation.

These enable downstream passes (LoopUnroll, WarnMissedTransforms) to
produce more precise optimization remarks. Instead of the generic "loop
not unrolled" warning on a source line that was vectorized, the unroller
can now report:
- **"vectorized loop"** for the main vector body
- **"epilogue loop"** for the scalar epilogue/remainder
- **"epilogue vectorized loop"** for an epilogue that was itself
vectorized during epilogue vectorization (carries both attributes)

A shared `getLoopVectorizeKindPrefix()` helper in
`LoopUtils.h`/`LoopUtils.cpp` reads the metadata and returns the

    [17 lines not shown]
DeltaFile
+120-0llvm/test/Transforms/LoopTransformWarning/vectorizer-loop-kind-unroll-warning.ll
+110-0llvm/test/Transforms/LoopUnroll/vectorizer-loop-kind-remarks.ll
+42-0llvm/docs/LangRef.rst
+21-0llvm/docs/TransformMetadata.rst
+10-3llvm/lib/Transforms/Scalar/WarnMissedTransforms.cpp
+12-0llvm/lib/Transforms/Utils/LoopUtils.cpp
+315-35 files not shown
+346-911 files

LLVM/project 63c0520llvm/lib/Target/RISCV RISCVSchedSiFive7.td, llvm/test/CodeGen/RISCV short-forward-branch-opt.ll sifive7-enable-intervals.mir

[RISCV] Use BufferSize = 0 for ProcResGroup in SiFive7 scheduling models (#194754)

As it turns out, even if a `ProcResGroup` consists of in-order pipes, as
long as its (the group's) BufferSize is not zero, Machine Scheduler will
not use in-order scheduling on instructions that consume it. Since
BufferSize also defaults to -1 for `ProcResGroup`, we have been
scheduling the resource consumption of SiFive7's `PipeAB` (scalar pipes)
and `VA1OrVA2` (vector pipes) in an out-of-order fashion!

Co-authored-by: Min Hsu <min.hsu at sifive.com>
DeltaFile
+18-18llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
+7-7llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+3-3llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
+28-283 files

FreeBSD/doc 3737bb9website/content/en/releases/15.0R/ec2-ami-ids latest.adoc

15.0: Update "latest" AMIs

We now have 15.0-RELEASE-p7 AMIs.

Approved by:    re (implicit)
Sponsored by:   Amazon
DeltaFile
+512-512website/content/en/releases/15.0R/ec2-ami-ids/latest.adoc
+512-5121 files