service: add reusable daemon(8) supervisor
Critical services can occasionally disappear after an OOM kill, crash or
unexpected signal. This is especially disruptive when Suricata runs in
divert-to mode: if it no longer consumes and reinjects packets, most traffic
can stop until the service is restarted manually. Other vital system
services have similar, albeit rare, failure modes.
Use daemon(8) as a small, reusable safety harness for supported services. A
shared rc.subr helper starts a foreground service below daemon(8), tracks the
supervisor and child independently, forwards stop and reload operations, and
removes stale service PID files before restart attempts. Configurable retry
limits and delays prevent a permanently failing service from looping without
bounds.
Add an opt-in System: Settings: Services page and a capability directory so
only explicitly adapted services can be selected. Existing service behavior
therefore remains unchanged until supervision is enabled and the service is
restarted.
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fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms
Select merging AND-NOT operations with TableGen patterns instead of the C++ combine. Preserve the first operand in inactive lanes and use an unpredicated BIC when both predicates are all-active.
[AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms
Replace NOT followed by merging AND with BIC for expressions such as:
return svand_u32_m(pg, a, svnot_u32_x(pg, b));
Combine when NOT is the second operand and its predicate matches the AND
predicate or is all-active.
Use predicated BIC to preserve the AND's first operand in inactive
lanes. Use unpredicated BIC when the AND predicate is all-active.
Do not commute merging AND operands, since this would change inactive
results. Leave pairs with incompatible predicates unchanged.
This applies to all integer element widths. Update the pre-commit LLVM
expectations, including cases where combining would change the
result.
fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms
Lower AND_U to an AArch64 target DAG node and match that node in TableGen. Keep the predicate for matching AND-NOT pairs, and combine other cases to ordinary AND so generic simplifications remain available. Name the data operands and iterate over them directly.
fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms
Check BIC selection for AND_U with poison NOT passthrough and different predicates. Cover the pattern independently of the matching-predicate case.
fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms
Keep AND_U as an AArch64 target node until instruction selection. Remove the C++ combine and restore the TableGen patterns for BIC, register AND and immediate AND selection.
fixup! Replace performSVEAndNotIntrinsicCombine() with tablegen
Move AND_U and NOT matching to TableGen, using a shared pattern fragment
for both operand orders. Retain register and immediate AND selection
for other AND_U operations.
fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms
Remove the AND_U pattern for NOT with undefined inactive lanes and an arbitrary predicate. Keep the original fix focused; ordinary cases still lower to AND and use the existing AND-NOT patterns.
[AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms
Replace NOT followed by AND with BIC for expressions such as:
return svand_u32_x(svptrue_b32(), a, svnot_u32_x(svptrue_b32(), b));
Combine ordinary AND with NOT when the NOT predicate is all-active or
its inactive values are undefined.
Also combine matching-predicate SVE AND_x-NOT pairs before lowering
discards the AND predicate. AND_x ignores inactive results, so the NOT's
inactive values do not need preserving.
This applies to all integer element widths. Update the pre-commit LLVM
expectations, including cases where combining would change the
result.
fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms
Remove the extra AND_U patterns for all-active NOT, ordinary LLVM NOT
and register AND fallback. The C++ helper lowers ordinary cases to
AND and retains matching-predicate AND-NOT pairs for the remaining BIC
pattern.
fixup! [AArch64][llvm] Add pre-commit tests for SVE AND-NOT combining
Add an AND_U case with poison NOT passthrough and different predicates. Record the existing NOT followed by AND before the BIC selection change.
[AArch64][llvm] Add pre-commit tests for SVE AND-NOT combining
Add LLVM tests for expressions where NOT followed by AND could
use BIC. Record the existing assembly so the following changes show the
missed optimisations being fixed.
Cover _x and _m AND forms using all-active and runtime predicates. Test
_m forms across all integer element widths. Include NOT with defined
inactive values and reversed AND operands.
Also test cases that must remain as NOT followed by AND because
combining would change the values in inactive lanes.
fixup! [AArch64][llvm] Add pre-commit tests for SVE AND-NOT combining
Add the ordinary LLVM NOT cases to the pre-commit tests, covering both AND_U operand orders. These already select BIC and guard against regressions when retaining AND_U for TableGen selection.
fixup! [AArch64][llvm] Add pre-commit tests for SVE AND-NOT combining
Move the extra 8-, 16- and 64-bit AND-NOT cases into the pre-commit tests. Record the existing NOT followed by AND so the implementation change shows BIC selection for every integer element width.
