LLVM/project 51e0c89llvm/lib/Target/Sparc SparcISelLowering.cpp

[Sparc] Create MMO for STORE_BIG/LITTLE with MOStore (#206929)

This only stores, so we can use a store MMO instead of a load+store one.
DeltaFile
+2-1llvm/lib/Target/Sparc/SparcISelLowering.cpp
+2-11 files

LLVM/project 805e89allvm/lib/Target/Sparc SparcInstrInfo.td

[Sparc] Mark LOAD_BIG/LOAD_LITTLE as MayLoad (#206924)

These were marked as MayStore, but should be MayLoad.
DeltaFile
+2-2llvm/lib/Target/Sparc/SparcInstrInfo.td
+2-21 files

LLVM/project 5969d64llvm/docs LangRef.rst, llvm/test/CodeGen/AMDGPU madak.ll asyncmark-gfx12plus.ll

[IR] Enable dereferenceable-at-point semantics (#204795)

The precise semantics of `dereferenceable` are currently undocumented,
but de facto they are:

* Argument position `dereferenceable` implies that the memory remains
dereferenceable while the function executes.
* Return position `dereferenceable` implies that the memory remains
dereferenceable forever.

This is not coherent with how these attributes are used, in at least two
ways:

* C++ reference arguments are annotated as `dereferenceable` by Clang.
However, C++ does not actually make any guarantees that the underlying
memory does not get freed during the execution of the function. (Unlike
Rust, which does guarantee this via protectors in SB/TB.)
* We infer `dereferenceable` on allocator return values (from
`allocsize`). Allocator return values quite obviously do not stay

    [25 lines not shown]
DeltaFile
+11-13llvm/test/CodeGen/AMDGPU/madak.ll
+9-9llvm/test/Transforms/LoopVectorize/early_exit_with_outer_loop.ll
+11-6llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll
+13-3llvm/docs/LangRef.rst
+8-7llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
+8-6llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
+60-4414 files not shown
+87-6920 files

NetBSD/pkgsrc s0MYo0Udoc CHANGES-2026

   Updated multimedia/libva, security/sqlmap
VersionDeltaFile
1.4200+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc JhtDTsosecurity/sqlmap PLIST distinfo

   sqlmap: updated to 1.10.7

   1.10.7
   Unknown changes
VersionDeltaFile
1.22+290-10security/sqlmap/PLIST
1.32+4-4security/sqlmap/distinfo
1.47+2-2security/sqlmap/Makefile
+296-163 files

DragonFlyBSD/src c3192b1lib/libthread_xu Makefile

libthread_xu: Link with '-z nodelete'; unloading it is unsafe

Loading libthread_xu has irreversible process-wide effects:

* rtld lazily rebinds libc weak pthread stubs (e.g. _spinlock) to
  the strong definitions in this library.  There is no mechanism to
  undo GOT bindings on dlclose(), so after an unload libc keeps
  calling into the unmapped region.

* __isthreaded stays set -- the library cannot prove that no other
  threads exist, so it cannot safely clear it -- which keeps the
  libc malloc on the locked path through the dangling _spinlock
  pointer.

* _thr_signal_init() installs signal handlers pointing into the
  library, and _thr_signal_deinit() is empty, so signal delivery
  after an unload also jumps into unmapped memory.

Consequently a program that dlopen()s a dependency chain pulling in

    [42 lines not shown]
DeltaFile
+4-0lib/libthread_xu/Makefile
+4-01 files

NetBSD/pkgsrc LQrXtx8multimedia/libva Makefile distinfo, multimedia/libva/patches patch-va_va__internal.h

   libva: updated to 2.24.0

   2.24.0 - 02.Jul.2026
   * va: Add VA_PICTURE_H264_NON_EXISTING flag
   * va: use secure_getenv instead of getenv in va_x11.c
   * doc: fix libva av1 link for doxygen
   * trace: dump input/output data in va_TraceProtectedSessionExecute
   * trace: Add ProtectedSession Related Log in Trace
VersionDeltaFile
1.40+6-8multimedia/libva/Makefile
1.1+14-0multimedia/libva/patches/patch-va_va__internal.h
1.29+5-4multimedia/libva/distinfo
+25-123 files

LLVM/project aa7773bclang-tools-extra/test/clang-tidy/checkers/readability redundant-typename.cpp

[clang-tidy] Add regression tests for readability-redundant-typename. NFC. (#207318)

Part of https://github.com/llvm/llvm-project/issues/206995
DeltaFile
+19-0clang-tools-extra/test/clang-tidy/checkers/readability/redundant-typename.cpp
+19-01 files

LLVM/project 9b0295cclang/test/CodeGen/LoongArch/lasx builtin.c builtin-alias.c, llvm/test/CodeGen/RISCV determine-callee-saves-gpr.mir

rebase

Created using spr 1.3.8-wip
DeltaFile
+733-733clang/test/CodeGen/LoongArch/lasx/builtin.c
+733-733clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+42-1,387llvm/test/CodeGen/X86/haddsub-2.ll
+1,283-0llvm/test/CodeGen/RISCV/determine-callee-saves-gpr.mir
+1,030-14llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
+959-12llvm/test/Transforms/PhaseOrdering/X86/hadd.ll
+4,780-2,879532 files not shown
+24,456-12,093538 files

LLVM/project cc62255clang/test/CodeGen/LoongArch/lasx builtin-alias.c builtin.c, llvm/test/CodeGen/RISCV determine-callee-saves-gpr.mir

[spr] changes introduced through rebase

Created using spr 1.3.8-wip

[skip ci]
DeltaFile
+733-733clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+733-733clang/test/CodeGen/LoongArch/lasx/builtin.c
+42-1,387llvm/test/CodeGen/X86/haddsub-2.ll
+1,283-0llvm/test/CodeGen/RISCV/determine-callee-saves-gpr.mir
+1,030-14llvm/test/Transforms/PhaseOrdering/X86/hsub.ll
+959-12llvm/test/Transforms/PhaseOrdering/X86/hadd.ll
+4,780-2,879532 files not shown
+24,456-12,093538 files

LLVM/project ac05f72llvm/include/llvm/CodeGen TargetRegisterInfo.h, llvm/include/llvm/MC MCRegisterInfo.h

[CodeGen] Merge TargetRegClass into MCRegClass (#207168)

Both data types store primitive information only and TargetRegisterClass
doesn't reference target-specific data structures. TargetRegisterClass,
however, freqeuently refers to MCRegisterClass through a pointer, which
prevents moving the large TargetRegisterClass instances to .rodata.

Therefore, merge the fields of TargetRegisterClass into MCRegisterClass
and adjust the remaining fields to use the existing storage mechanism
for pointer-free storage. To avoid invasive code changes, keep
TargetRegisterClass as alias for MCRegisterClass.

This reduces the size of .data.rel.ro by ~122 kiB in an all-target
build while growing .rodata by just 92 kiB. Further size improvements
are possible in future by reordering struct fields and deduplicating
masks/register lists/register class lists.

Pull Request: https://github.com/llvm/llvm-project/pull/207168
DeltaFile
+146-126llvm/utils/TableGen/RegisterInfoEmitter.cpp
+4-157llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+109-1llvm/include/llvm/MC/MCRegisterInfo.h
+5-14llvm/test/TableGen/RegisterInfoEmitter-inherit-properties.td
+4-8llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+5-4llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+273-31042 files not shown
+359-36748 files

FreeBSD/ports fb5705fnet/redpanda-connect distinfo Makefile

net/redpanda-connect: Update to 4.99.0
DeltaFile
+5-5net/redpanda-connect/distinfo
+3-3net/redpanda-connect/Makefile
+8-82 files

LLVM/project d3b6ad1mlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

[mlir-c] Reapply Add ConversionTarget dynamic legality C API (#207104) (#207253)

Fixes LeakSanitizer failure from #206161 (reverted in #207104);
`mlirFreezeRewritePattern` moves contents out of the `RewritePatternSet`
but does not free the container (passed by value in the C API), so the
allocation from `mlirRewritePatternSetCreate` was never freed (add
`mlirRewritePatternSetDestroy(patterns)` after freezing).
DeltaFile
+181-0mlir/test/CAPI/rewrite.c
+60-0mlir/lib/CAPI/Transforms/Rewrite.cpp
+44-0mlir/include/mlir-c/Rewrite.h
+285-03 files

NetBSD/pkgsrc-wip de53443rust-beta options.mk

rust-beta: follow main changes

Note this packages needs to be updated to the current beta iteration.
I'll do this soon but, I'm currently AFK.
DeltaFile
+83-6rust-beta/options.mk
+83-61 files

LLVM/project e49c8a0libcxx/include string, libcxx/include/__cxx03 string

[libc++] Base string's alignment on __STDCPP_DEFAULT_NEW_ALIGNMENT__ (#171785)

This allows users to influence how much we overalign `string`s
allocations and tune it to the new/delete implementation via
`-fnew-alignment`. If we don't have `__STDCPP_DEFAULT_NEW_ALGINMENT__`
or we're not using `std::allocator`, we default to an alignment of
`sizeof(void*)`.
DeltaFile
+30-0libcxx/test/libcxx/strings/basic.string/new_alignment.sh.cpp
+15-9libcxx/test/libcxx/strings/basic.string/string.capacity/allocation_size.pass.cpp
+12-1libcxx/include/__cxx03/string
+11-1libcxx/include/string
+2-7libcxx/test/std/strings/basic.string/string.capacity/over_max_size.pass.cpp
+5-2libcxx/test/libcxx-03/strings/basic.string/string.capacity/allocation_size.pass.cpp
+75-203 files not shown
+88-239 files

LLVM/project 1030639lld/ELF LinkerScript.cpp

[ELF] Precompute orphan output section names in parallel. NFC (#207321)

addOrphanSections computes getOutputSectionName serially for every live
orphan section. Without --emit-relocs/-r, the name is a pure function of
the section: precompute the names with a parallelFor.
DeltaFile
+16-4lld/ELF/LinkerScript.cpp
+16-41 files

LLVM/project 3d54bedllvm/include/llvm/IR IRBuilder.h, llvm/lib/CodeGen AtomicExpandPass.cpp

Update for comments
DeltaFile
+9-13llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+14-0llvm/include/llvm/IR/IRBuilder.h
+4-6llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+2-4llvm/lib/CodeGen/AtomicExpandPass.cpp
+29-234 files

OpenBSD/ports KEbJwwLx11/kde-plasma/plasma-workspace Makefile, x11/kde-plasma/plasma-workspace/pkg PLIST

   Fix conflict plasma-desktop version

   New file was added in 6.7 not 6.4 (copy waste issue).
VersionDeltaFile
1.27+1-1x11/kde-plasma/plasma-workspace/pkg/PLIST
1.43+1-1x11/kde-plasma/plasma-workspace/Makefile
+2-22 files

FreeBSD/doc 1236f48shared contrib-additional.adoc

contrib-additional.adoc: add Vyacheslav Olkhovchenkov <slw at zxy.spb.ru>

Add Vyacheslav Olkhovchenkov <slw at zxy.spb.ru> for the port misc/auto-tempo.
DeltaFile
+1-0shared/contrib-additional.adoc
+1-01 files

FreeBSD/ports 674c4d4misc Makefile, misc/auto-tempo Makefile pkg-descr

misc/auto-tempo: Manage Jira Tempo Timesheets worklogs from a text file

AutoTempo manages Jira worklogs through the Tempo Timesheets REST API
using a simple, version-controllable text file.
It can generate a monthly worklog template pre-populated
with working days, expand keyword shortcuts and recurring entries
defined in config.toml, validate daily totals, and apply worklogs
idempotently to Jira. A helper can draft worklogs from local
git commit history.

Targets Tempo Timesheets on Jira Server/Data Center;
authentication uses a Jira personal access token.
The tool is run from a directory containing a config.toml file.

PR:             296427
DeltaFile
+128-0misc/auto-tempo/files/patch-autotempo.py
+35-0misc/auto-tempo/Makefile
+10-0misc/auto-tempo/pkg-descr
+3-0misc/auto-tempo/distinfo
+1-0misc/Makefile
+177-05 files

LLVM/project 7c0b1d3clang/include/clang/AST OpenMPClause.h, clang/lib/Parse ParseOpenMP.cpp

[Clang][OpenMP] Add parsing for dims modifier in num_teams and thread_limit
DeltaFile
+132-24clang/lib/Sema/SemaOpenMP.cpp
+129-0clang/test/OpenMP/dims_modifier_messages.cpp
+63-21clang/lib/Parse/ParseOpenMP.cpp
+72-10clang/include/clang/AST/OpenMPClause.h
+40-0clang/test/OpenMP/dims_modifier_ast_print.cpp
+23-11clang/lib/Sema/TreeTransform.h
+459-6614 files not shown
+577-10720 files

LLVM/project 16a6b51clang/lib/Sema SemaOpenMP.cpp

[NFC][Clang][OpenMP] Simplify checks for num_teams and thread_limit expressions (#207305)

Prepare changes for #206412
DeltaFile
+61-57clang/lib/Sema/SemaOpenMP.cpp
+61-571 files

OpenBSD/src lrs9pIpsys/dev/pci if_bnxt.c

   Attach to BCM5745x devices, which should work as far as I can tell from the
   vendor driver.
VersionDeltaFile
1.70+3-1sys/dev/pci/if_bnxt.c
+3-11 files

OpenBSD/src A1L3iz1sys/dev/pci pcidevs_data.h pcidevs.h

   regen
VersionDeltaFile
1.2129+9-1sys/dev/pci/pcidevs_data.h
1.2134+3-1sys/dev/pci/pcidevs.h
+12-22 files

OpenBSD/src hpCLFfhsys/dev/pci pcidevs

   Add missing BCM5745x devices, pointed out by Brad
VersionDeltaFile
1.2141+3-1sys/dev/pci/pcidevs
+3-11 files

NetBSD/src gq5Yi43usr.bin/make/filemon filemon_dev.c

   filemon_close:  FILEMON_FLUSH_IOCTL if defined
VersionDeltaFile
1.10+14-1usr.bin/make/filemon/filemon_dev.c
+14-11 files

LLVM/project 602897fllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 vecreduce-add.ll vecreduce-fadd.ll

[DAGCombiner] Reassociate chains of vector reductions (#206471)

`DAGCombiner::reassociateReduction` already folds a single
`add(vecreduce(x), vecreduce(y)) -> vecreduce(add(x, y))`, and the
balanced-tree form `add(add(vecreduce(a), b), add(vecreduce(c), d))`.
It does not, however, handle a linear chain of reductions like the one
SLP emits for x264's SAD:

```
add(reduce(X0), add(reduce(X1), add(reduce(X2), acc)))
```

Only the innermost pair can ever be merged; the cascade breaks and every
reduction survives to lowering, giving one `vredsum` (or one `uadalp` step,
etc.) per term.

This PR adds a third form to `reassociateReduction`:

```

    [17 lines not shown]
DeltaFile
+74-82llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+136-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
+97-0llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
+36-35llvm/test/CodeGen/AArch64/vecreduce-add.ll
+36-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+17-9llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
+396-1261 files not shown
+399-1327 files

OpenBSD/src 2mPz1sVsys/dev/pci if_mcx.c

   use the same rwlock for queue kstats as other kstat instances

   ok dlg@
VersionDeltaFile
1.123+2-1sys/dev/pci/if_mcx.c
+2-11 files

LLVM/project 70f945fllvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchLSXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx vexth.ll

[LoongArch] Add DAG combines for vector widening extends

Lower:

```
  SEXT/ZEXT(High-Half-128-Bit-Lanes(vec))
```

to:

```
  LSX:  VEXTH.H.B, VEXTH.W.H, VEXTH.D.W
        VEXTH.HU.BU, VEXTH.WU.HU, VEXTH.DU.WU

  LASX: XVEXTH.H.B, XVEXTH.W.H, XVEXTH.D.W
        XVEXTH.HU.BU, XVEXTH.WU.HU, XVEXTH.DU.WU
```
DeltaFile
+4-54llvm/test/CodeGen/LoongArch/lasx/vexth.ll
+23-12llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+29-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+24-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+6-15llvm/test/CodeGen/LoongArch/lsx/vexth.ll
+86-815 files

LLVM/project d0733c1llvm/test/CodeGen/LoongArch/lasx vexth.ll, llvm/test/CodeGen/LoongArch/lsx vexth.ll

[LoongArch][NFC] Add vector widening extends tests
DeltaFile
+217-0llvm/test/CodeGen/LoongArch/lasx/vexth.ll
+104-0llvm/test/CodeGen/LoongArch/lsx/vexth.ll
+321-02 files