LLVM/project 088e3c7clang/lib/Driver/ToolChains Hexagon.cpp, clang/test/Driver hexagon-toolchain-linux.c

[Hexagon] Skip CRT start files for relocatable (-r) links on musl (#201262)

Guard the dynamic-linker, crt1.o, and crti.o additions with OPT_r,
consistent with Gnu.cpp and the existing -pie suppression in this file.
CRT start files must not appear in partial links (-r) as they define
_start, causing duplicate-symbol errors when the output is later linked
into an executable.
DeltaFile
+19-0clang/test/Driver/hexagon-toolchain-linux.c
+4-3clang/lib/Driver/ToolChains/Hexagon.cpp
+23-32 files

LLVM/project de6f07flibcxx/test/std/atomics/atomics.ref fetch_min.pass.cpp fetch_max.pass.cpp, libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req atomic_fetch_min_explicit.pass.cpp atomic_fetch_min.pass.cpp

Port test coverage from #186694

Assisted by Claude, reviewed manually.
DeltaFile
+147-0libcxx/test/support/atomic_fetch_max_helper.h
+147-0libcxx/test/support/atomic_fetch_min_helper.h
+38-27libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_fetch_min_explicit.pass.cpp
+38-26libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_fetch_min.pass.cpp
+18-42libcxx/test/std/atomics/atomics.ref/fetch_min.pass.cpp
+18-42libcxx/test/std/atomics/atomics.ref/fetch_max.pass.cpp
+406-1372 files not shown
+474-1688 files

LLVM/project e52cad0mlir/lib/Dialect/OpenACC/Transforms ACCRecipeMaterialization.cpp, mlir/test/Dialect/OpenACC acc-recipe-materialization-firstprivate.mlir acc-recipe-materialization-private.mlir

[ACCRecipeMaterialization] add tests for private/firstprivate destroy (#203990)

While working on #203935, I noticed that private and firstprivate
recipes with destroy regions were not tested. Add these tests and fix a
bug from the previous commit that would have been caught had these tests
been fixed by generating the destroy region at the correct insertion
point
DeltaFile
+5-0mlir/test/Dialect/OpenACC/acc-recipe-materialization-firstprivate.mlir
+5-0mlir/test/Dialect/OpenACC/acc-recipe-materialization-private.mlir
+2-2mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
+12-23 files

LLVM/project 0c8725fllvm/test/Analysis/CostModel/AArch64 sve-arith.ll

[AArch64] Add scalable i128 costmodel test coverage. NFC (#203996)

This also adds some basic sub costs, similar to the others, and sorts
the
operations into a more standard order.
DeltaFile
+71-42llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
+71-421 files

LLVM/project 68fb2e7llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/PowerPC insertvalue-with-copyable-args.ll

[SLP] Fix insert point for insertvalue buildvector with copyable operands

Use the last insertvalue as the insert point (like insertelement) so the
vec2struct store/load are not emitted before the vectorized operand.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/203994
DeltaFile
+37-0llvm/test/Transforms/SLPVectorizer/PowerPC/insertvalue-with-copyable-args.ll
+2-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+39-12 files

LLVM/project 4f6af6ellvm/docs/CommandGuide index.rst, llvm/docs/GlobalISel index.rst Pipeline.rst

[docs] Enforce unambiguous toctree in llvm/docs

It seems like using a non-`hidden` `toctree` for page navigation is a
bit of a trap, in that every doc must have a single unique path through
the global toctree to the root doc, and it is very easy to end up with
multiple.

This patch tries to address the warnings (actually infos, hence why it
does not fail the build) in llvm/docs/, namely:

  $ sphinx-build -b html -jauto llvm/docs/ /tmp/sphinx-out
  checking consistency...
  llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md: document is referenced in multiple toctrees: ['UserGuides', 'AMDGPUUsage'], selecting: UserGuides <- AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack
  llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst: document is referenced in multiple toctrees: ['UserGuides', 'AMDGPUUsage'], selecting: UserGuides <- AMDGPUDwarfExtensionsForHeterogeneousDebugging
  llvm/docs/CommandGuide/llvm-reduce.rst: document is referenced in multiple toctrees: ['CommandGuide/index', 'CommandGuide/index', 'Reference'], selecting: Reference <- CommandGuide/llvm-reduce
  llvm/docs/GitHub.rst: document is referenced in multiple toctrees: ['GettingInvolved', 'UserGuides'], selecting: UserGuides <- GitHub
  llvm/docs/GlobalISel/IRTranslator.rst: document is referenced in multiple toctrees: ['GlobalISel/index', 'GlobalISel/Pipeline'], selecting: GlobalISel/index <- GlobalISel/IRTranslator
  llvm/docs/GlobalISel/InstructionSelect.rst: document is referenced in multiple toctrees: ['GlobalISel/index', 'GlobalISel/Pipeline'], selecting: GlobalISel/index <- GlobalISel/InstructionSelect
  llvm/docs/GlobalISel/Legalizer.rst: document is referenced in multiple toctrees: ['GlobalISel/index', 'GlobalISel/Pipeline'], selecting: GlobalISel/index <- GlobalISel/Legalizer

    [35 lines not shown]
DeltaFile
+88-39llvm/docs/CommandGuide/index.rst
+30-21llvm/docs/GlobalISel/index.rst
+50-0utils/docs/llvm_sphinx/ext/checks.py
+21-21llvm/tools/llvm-debuginfo-analyzer/README.md
+0-14llvm/docs/tutorial/MyFirstLanguageFrontend/index.rst
+0-8llvm/docs/GlobalISel/Pipeline.rst
+189-1035 files not shown
+191-11211 files

LLVM/project 47f1dc2clang/docs ghlinks.py conf.py, lldb/docs conf.py

[docs] Create utils/docs

llvm-project is home to many sphinx documentation sites, each with
configuration quirks and bespoke extentions.

The sphinx config model makes sharing code somewhat difficult. There
are options like sphinx-multiproject, but some of our docs builds are
out of the source tree while some are done out of the binary tree, so
the multiproject configuration itself would need to be generated. It
also would impose more uniformity around extensions than required.

This change instead creates a python package at utils/docs/llvm_sphinx
and makes it available to all sphinx-build processes via PYTHONPATH.
Each conf.py does not modify its own sys.path because not all builds are
out of the source tree, so there isn't a stable relative path to use to
refer to the utils/docs/ directory.

Type checking via pyright in new package is pinned to being python 3.8
compatible.

    [29 lines not shown]
DeltaFile
+0-273clang/docs/ghlinks.py
+151-0utils/docs/llvm_sphinx/ext/ghlinks/__init__.py
+72-0utils/docs/llvm_sphinx/__init__.py
+7-39lldb/docs/conf.py
+5-38llvm/docs/conf.py
+10-30clang/docs/conf.py
+245-38023 files not shown
+419-64329 files

LLVM/project 4f55655flang/lib/Semantics check-omp-structure.h

[flang][OpenMP] Remove unused variable 'noWaitClauseNotAllowedSet', NFC (#203973)
DeltaFile
+0-11flang/lib/Semantics/check-omp-structure.h
+0-111 files

LLVM/project 1b49912clang/lib/CIR/CodeGen CIRGenExprScalar.cpp, clang/test/CIR/CodeGen bitfield-postinc.cpp

[CIR] Fix bitfield post-increment return value (#201723)

In \`emitScalarPrePostIncDec\`, the bitfield branch called
\`emitStoreThroughBitfieldLValue\` and returned its result directly,
bypassing the \`return e->isPrefix() ? value : input\` logic that
selects old vs new for post vs pre-increment. For post-increment on a
bitfield, this returned the new (incremented) value instead of the old
one, so \`if (s->nRefs++)\` always evaluated true even when \`nRefs\`
was zero on entry.

Fix by assigning the store result to \`value\` and falling through to
the existing prefix/postfix selector, mirroring the non-bitfield path.

Found via the SPEC CPU 2026 abc_r benchmark: \`Cnf_ManScanMapping_rec\`
uses \`if (pObj->nRefs++)\` on a 26-bit bitfield to detect
already-visited AIG nodes. With the bug, every call returned true
(already visited) immediately, producing an empty CNF mapping and a
spuriously satisfiable SAT problem (133 variables instead of 3018).
DeltaFile
+63-0clang/test/CIR/CodeGen/bitfield-postinc.cpp
+1-1clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+64-12 files

FreeBSD/doc 6687acawebsite/content/ru/releases/15.1R errata.adoc

website/ru: Add releases/15.1R/errata.adoc

Synced to EN 9e5117bd9b2e04bbfbee53aac92e1a2ad59ad891
DeltaFile
+79-0website/content/ru/releases/15.1R/errata.adoc
+79-01 files

LLVM/project 010ff4fclang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp

[CIR] NFC: Clarify Expand insertion-point guard

Gate the field-store insertion point on the same destAlloca condition
that gates emitting the stores.  This makes it explicit that when the
CIRGen spill is absent (DCE removed it) the Expand path only reshapes
the signature and emits no stores, so no insertion point is consulted.
When the spill survives, the insertion point is its old slot, which sits
after the CIRGen allocas.  No functional change.
DeltaFile
+7-4clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+7-41 files

GhostBSD/ghostbsd 2864dbdsys/dev/atkbdc psm.c

Merge pull request #388 from b-aaz/psm_workaround

psm(4): Disabled IMEX side-buttons by default.
DeltaFile
+8-0sys/dev/atkbdc/psm.c
+8-01 files

FreeNAS/freenas 3f9cb3esrc/middlewared/middlewared/plugins/audit utils.py

audit: serialize truenas_verify baseline against /usr race

setup_truenas_verify generates the as-installed truenas_verify baseline by
reading the entire rootfs. It runs as a first-boot system.ready handler,
concurrently with boot.update_initramfs (another system.ready agent), which
overlays a read-only functioning-dpkg sysext on /usr for the duration of its
truenas-initrd.py rebuild.

When the baseline read hits /usr while that overlay is mounted, it captures
the overlay's dpkg files instead of the installed ones, producing spurious
discrepancies (e.g. '/usr/bin/dpkg: got mode 0o755, expected: 644',
'/usr/local/bin/dpkg: incorrect file type.') and a non-clean install log.

Wrap the do_verify call in rootfs_protection_lock() so it can't overlap the
sysext rebuild. Only caller is audit's run_in_thread(setup_truenas_verify),
so the blocking flock stays off the event loop, and do_verify never calls
back into middleware, so there is no deadlock.
DeltaFile
+9-1src/middlewared/middlewared/plugins/audit/utils.py
+9-11 files

LLVM/project 9ffa02dclang/include/clang/CIR/Dialect/IR CIROps.td CIRTypeConstraints.td, clang/lib/CIR/CodeGen CIRGenBuiltin.cpp

[CIR] Lower __builtin_bswapg (#203618)

C++23 `std::byteswap` lowers every value wider than a single byte
through the type-generic `__builtin_bswapg` builtin, which CIRGen had no
case for, so `std/numerics/bit/byteswap.pass.cpp` hit `errorBuiltinNYI`.

This handles `__builtin_bswapg` the way classic CodeGen does
(`CGBuiltin.cpp`): a bool or single-byte integer is returned unchanged,
and wider values go through `cir.byte_swap`. Unlike the unsigned-only
`__builtin_bswap16/32/64`, the generic builtin also accepts signed
operands, so a signed argument is reinterpreted as unsigned of the same
width before the swap and cast back afterward.

`cir.byte_swap` previously accepted only 16/32/64-bit operands, but
`std::byteswap` instantiates it for `__int128` and wide `_BitInt` too
(the libc++ test reaches `_BitInt(256)`). The operand constraint is
widened to any unsigned integer whose width is a multiple of 16 bits --
which is what `llvm.bswap` requires -- and the existing CIR-to-LLVM
lowering already handles any such width. With the fix,
`byteswap.pass.cpp` passes under `-fclangir`.
DeltaFile
+139-0clang/test/CIR/CodeGenBuiltins/builtin-bit.cpp
+21-0clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+12-0clang/test/CIR/IR/invalid-bit.cir
+3-3clang/include/clang/CIR/Dialect/IR/CIROps.td
+4-0clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
+179-35 files

LLVM/project 14eff09llvm/test/CodeGen/AMDGPU ldsdmacnt_sched.mir

Update lit

Change-Id: Idd5437cccc1d1db229acff7b2a519d1188f98833
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
+2-21 files

LLVM/project 37d4ee5llvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp AMDGPUInstructionSelector.cpp

[AMDGPU] Guard against opsel selection in V_PK_*64

These instructions do not have OPSEL or ABS so bail on selection.
This does not affect any tests now because v2f64/v2i64 are not legal
for BUILD_VECTOR and alike, but if it is legal it will silently
produce incorrect code. GlobalISel already has this guard.
DeltaFile
+8-0llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+9-12 files

FreeNAS/freenas 9069788.github/workflows mypy.yml, src/middlewared_docs generate_docs.py

fix mypy
DeltaFile
+2-2src/middlewared_docs/generate_docs.py
+1-0.github/workflows/mypy.yml
+3-22 files

LLVM/project 018b29aflang/include/flang/Semantics expression.h, flang/lib/Semantics expression.cpp

[flang] Extract misparsed function reference check into function (#203899)

Function calls and array element acceses have the same syntax, and some
array element accesses may be misparsed as calls. The ExprChecker will
identify and correct such cases in expressions, but they may also occur
outside of expressions (e.g. OpenMP directives and clauses).

To avoid code duplication extract the check into a new function
`IsMisparsedFunctionReference`.
DeltaFile
+37-32flang/lib/Semantics/expression.cpp
+3-0flang/include/flang/Semantics/expression.h
+40-322 files

Illumos/gate f2b3489usr/src/cmd/make/include/mksh dosys.h, usr/src/cmd/make/include/vroot args.h vroot.h

18161 dmake(1) could use posix_spawn() to run commands
Reviewed by: Dan Cross <cross at oxidecomputer.com>
Reviewed by: Gordon Ross <Gordon.W.Ross at gmail.com>
Reviewed by: Toomas Soome <tsoome at me.com>
Approved by: Dan McDonald <danmcd at edgecast.io>
DeltaFile
+163-119usr/src/cmd/make/lib/mksh/dosys.cc
+29-11usr/src/cmd/make/lib/vroot/execve.cc
+8-3usr/src/cmd/make/include/vroot/args.h
+6-2usr/src/cmd/make/include/mksh/dosys.h
+7-1usr/src/cmd/make/include/vroot/vroot.h
+213-1365 files

LLVM/project 9c2ceddllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-sched-barrier-latency.mir

[AMDGPU] Add some DAG mutations to CoexecSched

Change-Id: Id86bbdb427b23f68d39ceee196e4232e91974186
DeltaFile
+171-0llvm/test/CodeGen/AMDGPU/coexec-sched-barrier-latency.mir
+2-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+173-02 files

LLVM/project 556a558llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

Adrress comments from https://github.com/llvm/llvm-project/pull/188658

Change-Id: Ia94c567a753168c1ffa16dc5d91195e7dd0ba044
DeltaFile
+114-114llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+3-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+117-1172 files

LLVM/project bde64e4llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f
DeltaFile
+6-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+6-01 files

LLVM/project 8906073llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h

Make fence heuristic work bottom-up

Change-Id: I629cbc8905b87a962e8b123287e5f60a3154df6b
DeltaFile
+22-19llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+7-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+29-252 files

LLVM/project badb161llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484
DeltaFile
+7-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+7-01 files

LLVM/project 9020a86llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir coexec-block-carried-latency.mir

Update tests

Change-Id: Ided5a4e6968d4670d1fd09bcb327a75a25273d4e
DeltaFile
+24-24llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+2-2llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
+26-262 files

LLVM/project afd177bllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add comment

Change-Id: I2180bba631fe4a01ed3c3fbcfa8c19cbefa84133
DeltaFile
+1-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-01 files

LLVM/project bf8e995llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

[AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5
DeltaFile
+323-0llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+77-22llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+18-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+418-223 files

LLVM/project c304ba9llvm/test/CodeGen/AMDGPU ldsdmacnt_sched.mir llvm.amdgcn.sched.group.barrier.gfx12.ll

Update lit

Change-Id: Ib55e5e1d9ed960c6c5442c62633850de51d8b3d9
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
+3-32 files

LLVM/project f4c4f87llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Update test

Change-Id: I65d4e77a81c65f2f895cb295b74185a70b403de3
DeltaFile
+65-69llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+65-691 files

LLVM/project 9619bbbllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Use static_cast

Change-Id: Ibec2cf245d5ac213ef0cc4292ba80cb983a58692
DeltaFile
+12-7llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+12-71 files