Simplify license delegate active check and usage alert
This commit makes some changes where license delegates decided whether the node is the active controller by reading failover.status.get_local and the VIP rows themselves; they now use the existing failover.is_single_master_node check, same as the TNC heartbeat.
It also turns the unlicensed features in use alert from a 10 minute polling source into a one-shot alert that is evaluated at the end of truenas.license.apply, once at system.ready on the active node and when a node becomes master, since gates already block new use of unlicensed features so the list can only shrink between license changes. A license daemon error still leaves the existing alert untouched.
VM and container updates are gated by the license again without carving out autostart-only edits, since an autostart instance coming back on a re-grant is what autostart means and the admin can change it once licensed.
Stopping active VMs and containers is simplified as well. The libvirt reachability probe, the resume-before-stop of suspended instances and the extra private endpoints are gone; a suspended VM is powered off and a suspended container killed, shutdown and failover call stop_active directly, and the pool import license guard for containers is dropped since container.start already refuses when unlicensed.
AMDGPU: Check implicit argument accesses with a single walk
Each update of AAAMDAttributes visited all call-like instructions of
the function up to seven times, for each implicit kernel argument plus
lds_kernel_id. Check all the relevant accesses in one pass.
Instructions spent in amdgpu-attributor:
rocPRIM test_device_scan, gfx942: 1429M -> 1385M (-3.0%)
Blender Cycles HIP kernel, gfx1100: 507M -> 504M (-0.6%)
rocPRIM 16 tests, full LTO, closed world: 5283M -> 5091M (-3.6%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[GVN] Add support for MSSA-path in masked store-to-load forwarding (#229757)
Following up on #157689, extend `processMaskedLoad` to employ MemorySSA
to locate the masked store that accesses the memory location of the
subsequent masked load. In order for the forwarding to be legal, the
store and load need to access the same memory location, which is
inherently provided by MemoryDependenceAnalysis, and needs instead be
explicitly checked with MSSA.
chinese/gcin: fix build on powerpc64*
Build with -fsigned-char: the phrase tables flag mixed-case English
words with a negative length stored in plain char. Also fix the hash
index of 1-byte keys in tsa2d32 on big-endian.
security/kuku: fix build on powerpc64
Upstream rejects big-endian targets because item words and the BLAKE2xb-seeded
tabulation table were read in native byte order, so a big-endian build would
compute a different table layout than little-endian peers. Define both in
little-endian byte order instead (a no-op on little-endian targets) and drop
the guards.
ftp/py-curl-cffi: fix build on powerpc64le
platform.uname().machine is "powerpc" on every FreeBSD PowerPC flavour, so the
"powerpc64" entry introduced by the 0.16.3 update never matched and the build
died with "Unsupported arch".
net/tcplog_dumper: fix build on powerpc64
struct tcp_log_bbr lost its ininput member in FreeBSD 14.0 (a370832bec5f);
it was only referenced by the big-endian conversion code.
misc/outside: fix build on powerpc64
The savefile crate refuses to build on big-endian targets with its
bit-vec feature, and its raw-memory fast paths write native byte order
there while the data is read back as little-endian, corrupting the
cache on round-trip. Serialize the BitVec storage words as little-endian
and disable the fast paths on big-endian.
www/qt6-webengine: add powerpc64le support
The architecture layer is derived from Chimera Linux's qt6-qtwebengine
ppc64le patchset, reduced to the files FreeBSD actually compiles and
adapted to FreeBSD:
- gn: map uname -m "powerpc" to ppc64 in host arch detection
- cmake/QtToolchainHelpers: map power64 to the ppc64 GN arch
- build/config/compiler: don't force a Linux target triple on BSD
- PartitionAlloc: ppc64 GN wiring, dynamic-page-size ASLR variant on BSD
(as for arm64), pin kAlignment to 16 (alignof(max_align_t) is 8 while
long double is 64-bit)
- v8: POWER8 baseline with AltiVec/VSX; make
Assembler::kMaximalBufferSize public, as the 6.11.2 baseline compiler
needs it
- base: define kThreadPriorityToNiceValueMapForTest on BSD; on ppc64 the
TOC reference survives --gc-sections
- blink/webaudio: fix the stale scalar ProcessARateVector fallback
signature in delay.cc
- devtools: don't create a zero-sized @rollup/plugin-terser worker pool
[8 lines not shown]
devel/jetbrains-rustrover: fix pty4j and sqlite paths on powerpc64le
The IDE looks up libsqliteij.so under linux-x86_64 on anything that is
not arm64, and pty4j uses JNA arch name ppc64le.
devel/jetbrains-clion: enable on powerpc64le
JetBrains provides no build of its clangd fork for powerpc64le, and the
IDE refuses a stock clangd, so the bundled clang tools are not installed
there.
biology/hmmer: add powerpc64le support
Swap vec_sld operands on little-endian so the Altivec code keeps its
big-endian element order, and drop the configure check that rejects
VMX on little-endian.
ipsec: move ping_hosts.sh to legacy plugin and harden
The script doesn't need to be in core and does not need to be
run by default. Tampering with /tmp/tmpHOSTS without legacy
IPsec running would allow creating the file with a non-root
user which the script would pick up and potentially evaluate.
The fix for ping_hosts.sh will be in the matching plugins commit.
Reported by: Adam Korczynski of Ada Logics using Anrophic
(cherry picked from commit d111374705013c217910a0d12399ca436c6c9b9c)
[AMDGPU] Remove unneeded check after SSA update in SILowerI1Copies. NFC. (#232219)
Since the switch to MachineIDFSSAUpdater in c59c19bf5921 this condition
is always true, since MachineIDFSSAUpdater never reuses existing phis.
