[mlir-python] Fix duplicate EnumAttr builder registration across dialects.
When multiple dialects share .td includes (e.g. affine includes arith),
each dialect's _*_enum_gen.py file registered attribute builders under
the same keys, causing "already registered" errors on the second import.
Two-pronged fix:
1. Add `allow_existing=True` to `register_attribute_builder` (and the
underlying C++ `registerAttributeBuilder`). When set, silently skips
registration if the key already exists (first-wins semantics). This
handles EnumInfo-based builders (e.g. `AtomicRMWKindAttr`,
`Arith_CmpFPredicateAttr`) that are emitted by every dialect whose
.td file includes the defining file.
2. Filter EnumAttr-loop builders by `-bind-dialect` in
`EnumPythonBindingGen.cpp` and register them under dialect-qualified
keys (`"dialect.AttrName"`). Update `OpPythonBindingGen.cpp` to look
up the same qualified keys for EnumAttr-typed op attributes (detected
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[clang][Driver][Darwin] Use `xcselect` for `*-apple-darwin*` targets too (#186683)
This is a follow-up to #119670. There, we introduced a CMake option
`CLANG_USE_XCSELECT`, which, when enabled, uses `libxcselect` to find
the right SDK to inject as an `-isysroot` flag when targeting
`*-apple-macos*`.
We intentionally left out `*-apple-darwin*` targets because it broke
many tests. This is unfortunate because `*-apple-darwin*` is the default
triple when building LLVM on macOS, so one isn't able to take advantage
of `xcselect` without an explicit `-target` flag or a change to the
toolchain's default target.
We fix this in two ways.
First, we move the injection of the `-isysroot` flag using `xcselect`
later, until after we are sure that we are targeting macOS. This avoids
confusing the earlier deployment target detection code when we inject
the macOS SDK but actually intended to target non-macOS.
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[orc-rt] Add BootstrapInfo: info for controller session bootstrap. (#187184)
BootstrapInfo holds information needed to bootstrap the ExecutionSession
in the controller. Future patches will update ControllerAccess to send
the bootstrap information at controller-connection time.
BootstrapInfo includes information about the executor process (via
Session::processInfo), an initial set of symbols (replacing
Session::controllerInterface()), and a simple key/value store.
[clang][RISCV] Add RequiredFeatures for zvknha and zvknhb (#186993)
zvknhb now implies zvknha so we dont need to check extensions manually
in SemaRISCV, we can just use RequiredFeatures instead.
[X86] Support reserving EDI on x86-32 (#186123)
Which is under discussion in
https://github.com/llvm/llvm-project/issues/179036.
x86-64 support is added in
https://github.com/llvm/llvm-project/pull/180242.
Now add x86-32 support for reserving EDI via `-ffixed-edi` Update the
X86 backend to respect those reservations in register handling,
callee-save logic, and memcpy/memset lowering, and add driver/codegen
tests.
Add clang driver support for -ffixed-edi and map it to the reserve-edi
target feature on i386.
Teach the X86 backend to treat EDI as a user-reserved register in
register lookup, reserved-register tracking, and callee-save handling,
and avoid selecting REP MOVS/REP STOS when EDI is reserved.
Add driver, Sema, and codegen tests covering option handling, named
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[FMV][AIX] Implement target_clones (cpu-only) (#177428)
This PR implements Function Multi-versioning on AIX using `__attribute__
((target_clones(<feature-list>)))`.
Initially, we will only support specifying a cpu in the version list.
Feature strings (such as "altivec" or "isel") on target_clones will be
implemented in a future PR.
Accepted syntax:
```
__attribute__((target_clones(<OPTIONS>)))
```
where `<OPTIONS>` is a comma separated list of strings, each string is
either:
1) the default string `"default"`
2) a cpu string `"cpu=<CPU>"`, where `<CPU>`is a value accepted by the
`-mcpu` flag.
For example, specifying the following on a function
```
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sysutils/lsblk: update to 4.1
Changelog between 4.0 and 4.1 is as follows:
- Fix column align for 1000-1023k size.
- Fix single disk argument.
- Properly calculate provider size.
- Add lsblk(8) man page.
- Fix disks listing.
- Extend column size for better formatting.
- Add -V to sort(1) for proper order of devices.
- Ignore card readers that have '0B' size.
- Fix listing devices with 0B size.
- Fix SUMMARY printing.
- Other minor fixes.
PR: 293887
[Clang][Modules] Add regression test for #179178 (#187173)
This patch adds a regression test for a clang header modules failure we
saw after #179178 landed.
I'm too familiar with the norms for clang modules tests, so feel free to
nit-pick.
I've verified that this test passes at HEAD and fails with #179168
applied (i.e., the revert reverted).
[libclc][NFC] Change include style from <...> to "..." (#186537)
project-specific headers should use "". Keep #include <amdhsa_abi.h>
llvm-diff shows no change to libclc.bc for spir--, spir64--, nvptx64--,
nvptx64--nvidiacl, nvptx64-nvidia-cuda and amdgcn-amd-amdhsa-llvm when
LIBCLC_TARGETS_TO_BUILD is "all".
Verified that reversing spir64--/libclc.spv and spir--/libclc.spv to
LLVM bitcode shows no diff.
Also fix `__CLC_INTEGER_CLC_BITFIELD_EXTRACT_SIGNED_H__` guard per
copilot review.
---------
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot at users.noreply.github.com>
[clang] Add `-verify-directives` cc1 flag (#179835)
Matheus once told me that the various rules I enforce in C++ DR tests
should be checked automatically. This is the patch to check some of
them.
`-verify-directives` is a cc1 flag that checks how `expected` directives
themselves are written. It enforces the following rules on top of
`-verify` mode:
1. Directives have to fully match diagnostic text (but regular
expressions are still allowed).
2. Lexical order of directives must match the order in which diagnostics
are emitted.
3. Each directive must match exactly one diagnostic.
4. Directives has to specify exact source location of the diagnostic,
i.e. wildcards (`*`) are not allowed.
The second rule (about order) is the most significant: it doesn't allow
to e.g. have `expected-note {{declared here}}` somewhere far away from
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[orc-rt] Rename SimpleSymbolTable::addSymbolsUnique, relax error cond… (#187171)
…ition.
Renames the SimpleSymbolTable addSymbolsUnique method to addUnique. The
new class name (from c727cd9a4b2) already implies that we're adding
symbols.
This commit also relaxes the error condition for addUnique: Rather than
rejecting any duplicate symbols, it only rejects symbols that were
previously added with a different address. This makes it safe to add the
same symbol(s) multiple time, as long as all definitions point to the
same address. The intent of this is to allow ORC runtime components to
unconditionally add their interfaces to symbols, even if that interface
might have been added previously.
[WebAssembly] Fold sign-extending shifts into signed loads in FastISel (#185906)
WebAssembly FastISel currently fails to fold sign-extension patterns
composed of zero-extending loads followed by shift operations. This
results in redundant shift and constant instructions in the output.
Before:
i32.load8_u $push3=, 0($0)
i32.const $push0=, 24
i32.shl $push1=, $pop3, $pop0
i32.const $push4=, 24
i32.shr_s $push2=, $pop1, $pop4
The matched shift instruction sequence is removed and safely folded into
a single sign-extending load, erasing the dead code via the
MachineBasicBlock iterator.
After:
i32.load8_s $push0=, 0($0)
Fixed: #184302
[NVPTX][AutoUpgrade] atom.load intrinsics should be autoupgraded to monotonic atomicrmw for NVPTX (#187140)
Prior to https://github.com/llvm/llvm-project/pull/179553, the seq_cst
qualifier was being ignored. The expected codegen for these intrinsics
is `atom.relaxed`- which corresponds to `Monotonic`. The fix does to
AutoUpgrade what https://github.com/llvm/llvm-project/pull/185822 does
to clang.
Revert "[LV] Replace remaining LogicalAnd to vp.merge in EVL optimization." (#187170)
Reverts llvm/llvm-project#184068
This hit the cost model assertion in rva23 stage2 build bot.
https://lab.llvm.org/buildbot/#/builders/213/builds/2497
[LV] Replace remaining LogicalAnd to vp.merge in EVL optimization. (#184068)
This patch replace the remaining LogicalAnd to vp.merge in the second
pass to not break the `m_RemoveMask` pattern in the optimizeMaskToEVL.
This can help to remove header mask for FindLast reduction (CSA) loops.
PR: https://github.com/llvm/llvm-project/pull/184068
