LLVM/project f376511 — llvm/lib/Target/ARM ARMRegisterInfo.td, llvm/test/CodeGen/Thumb inline-asm-tied-r12.ll

ARM: Define the R12 register class explicitly (#241005)

TableGen inferred the R12-only class from hGPR and tcGPR, and it
inherited the Thumb1 allocation order of tcGPR, which only has low
registers. On Thumb1 the class had no allocatable registers, so an
inline asm input tied to r12 failed to allocate. In the future
TableGen should error on allocatable classes without any members.

Define the class explicitly so R12 is in its allocation order. This
fixes a regression from #238705, which started creating tied inline
asm inputs in this class.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+28-0llvm/test/CodeGen/Thumb/inline-asm-tied-r12.ll
+4-0llvm/lib/Target/ARM/ARMRegisterInfo.td
+32-02 files

LLVM/project 47d41c1 — clang/lib/CIR/CodeGen CIRGenItaniumCXXABI.cpp, clang/test/CIR/CodeGen attribute-visibility.c rtti-visibility.cpp

Merge branch 'main' into users/arsenm/runtime-libcalls/sqrt-attrs-tablegen
DeltaFile
+78-0llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
+53-0clang/test/CIR/CodeGen/rtti-visibility.cpp
+28-21clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
+14-14clang/test/CIR/CodeGenCXX/vtable-linkage.cpp
+20-0llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+5-10clang/test/CIR/CodeGen/attribute-visibility.c
+198-4517 files not shown
+249-7123 files

LLVM/project f05ad4f — lld/docs ReleaseNotes.md

add release notes
DeltaFile
+4-0lld/docs/ReleaseNotes.md
+4-01 files

LLVM/project 41312b7 — llvm/include/llvm/IR RuntimeLibcalls.td RuntimeLibcallsImpl.td, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Move malloc, calloc and free attributes to TableGen (#240713)

This requires new attribute plumbing for attributes that have an
argument value.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+2-70llvm/lib/IR/RuntimeLibcalls.cpp
+59-11llvm/test/TableGen/RuntimeLibcallEmitter-attributes.td
+38-18llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
+28-5llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+24-3llvm/include/llvm/IR/RuntimeLibcalls.td
+20-0llvm/test/TableGen/RuntimeLibcallEmitter-attributes-errors.td
+171-1072 files not shown
+179-1128 files

LLVM/project a924ec9 — lld/MachO Options.td Driver.cpp, lld/test/MachO icf-safe-thunks.ll icf-safe-thunks-callers.s

add --icf=relaxed_thunks
DeltaFile
+0-253lld/test/MachO/icf-safe-thunks-callers.s
+253-0lld/test/MachO/icf-relaxed-thunks.s
+21-21lld/MachO/ICF.cpp
+8-4lld/test/MachO/icf-safe-thunks.ll
+6-5lld/MachO/Options.td
+8-3lld/MachO/Driver.cpp
+296-2864 files not shown
+307-28710 files

LLVM/project 99e2ec4 — llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-amdgcn.ptr.s.buffer.load.ll

Update nuw copies of tests
DeltaFile
+8-10llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
+8-101 files

LLVM/project 5734a45 — llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-amdgcn.s.buffer.load.ll regbankselect-amdgcn.ptr.s.buffer.load.ll

[AMDGPU][GlobalISel] Fix immediate offset overflow when splitting s.buffer.load

When we're splitting a very large (>128 bit) s.buffer.load into
128-bit buffer loads, we add offsets to each split load. Currently,
when dealing with ptr.s.buffer.load, the code wouldn't subtract enough
from the immediate offset, so that when we added that +128 or +256,
we'd overflow the 12-bit immediate, causing silent overflow.

This commit fixes the issue by correctly calling the offset
splitter with a "alignment" that ensures that all those intermediate
loads don't overflow.

This matches the behavior in SDag and RegisterBankInfo.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+30-34llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
+24-24llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll
+16-20llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
+4-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+82-875 files

LLVM/project 7be8505 — llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-amdgcn.ptr.s.buffer.load.ll

[AMDGPU][GlobalISel] Pre-commit tests for split s.buffer.load offset overflow

Add divergent-offset ptr.s.buffer.load tests where the 256- and 512-bit
loads are split into 128-bit pieces at an offset of 4092, causing
overflow on the immediate field.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+217-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
+217-01 files

LLVM/project a5e728e — llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-amdgcn.ptr.s.buffer.load.ll

Add nuw tests
DeltaFile
+146-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
+146-01 files

LLVM/project 1099113 — clang/test/OffloadTools/clang-nvlink-wrapper opt-remarks.c, clang/tools/clang-nvlink-wrapper ClangNVLinkWrapper.cpp NVLinkOpts.td

[NvlinkWrapper] opt-remarks-filter -> opt-remarks-passes

`renderRemarksOptions` in Clang's `CommonArgs.cpp` translates
`-foptimization-record-passes` to `--plugin-opt=opt-remarks-passes`.
`lld` expects that, but `clang-nvlink-wrapper` currently expects
`--plugin-opt=opt-remarks-filter` instead, producing errors like:

```
clang-nvlink-wrapper: Unknown command line argument opt-remarks-passes=inline
```

In `NVLinkOpts.td` for `clang-nvlink-wrapper`, this patch adds
`--plugin-opt=opt-remarks-passes` and makes
`--plugin-opt=opt-remarks-filter` an alias.  If there are no users of
the latter, we can consider removing it.

Assisted-by: LLM
DeltaFile
+22-0clang/test/OffloadTools/clang-nvlink-wrapper/opt-remarks.c
+3-1clang/tools/clang-nvlink-wrapper/NVLinkOpts.td
+1-1clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
+26-23 files

LLVM/project 2940c71 — clang/test/CIR/CodeGen attr-alias.c attr-alias-no-proto.c

[mlir][LLVMIR] Drop ClangIR test updates now that #234753 has landed

Assisted-by: Cursor / claude-opus-5.5
DeltaFile
+3-3clang/test/CIR/CodeGen/attr-alias.c
+3-3clang/test/CIR/CodeGen/attr-alias-no-proto.c
+6-62 files

LLVM/project 77cf68f — llvm/test/CodeGen/RISCV rvp-simd-32.ll rvp-simd-64.ll

[RISCV][P-ext] Add tests for extractelement with a variable index. NFC

Assisted-by: Claude
DeltaFile
+109-61llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+36-4llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+145-652 files

LLVM/project bbcc52d — llvm/test/CodeGen/AArch64 bitinsert-bitextract-vector.ll

[AArch64] Use `-global-isel=0` in vector `bitinsert`/`bitextract` test
DeltaFile
+1-1llvm/test/CodeGen/AArch64/bitinsert-bitextract-vector.ll
+1-11 files

LLVM/project 07a5b49 — clang/lib/CIR/CodeGen CIRGenItaniumCXXABI.cpp, clang/test/CIR/CodeGen multi-vtable.cpp thunks.cpp

[CIR] Implement 'dsoLocal and 'protected visibility' (#240985)

This patch implements the setDSOLocal and protectedVisibility missing
features. These are both required to get the 'dso_local' to show up
correctly on RTTI members and to get their visibility correct.
Previously, we approximated it based on the MLIR public/private-ness,
but this doesn't take into account the visibility attribute, nor RTTI
correctly.

This patch adds that, and adds testing for all of the places this
changes. However, note that LLVM-IR will not print dso_local if it is
'implied' so it wasn't as obvious that it was not correctly marked in
CIR (but LLVM-IR effectively 'got it right').

Additionally, mlir default-sets declarations as 'private', so we were
missing a few cases where the linkage wasn't being set properly. This
patch ALSO updates those. This again is something that doesn't really
end up in the LLVM-IR, just in the MLIR types however, so it isn't
really visible, just another 'correctness' fix.
DeltaFile
+53-0clang/test/CIR/CodeGen/rtti-visibility.cpp
+28-21clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
+14-14clang/test/CIR/CodeGenCXX/vtable-linkage.cpp
+5-10clang/test/CIR/CodeGen/attribute-visibility.c
+5-5clang/test/CIR/CodeGen/thunks.cpp
+3-3clang/test/CIR/CodeGen/multi-vtable.cpp
+108-5311 files not shown
+129-6817 files

FreeNAS/freenas 7079a2e — src/middlewared/middlewared/plugins/iscsi_ lio.py

Update how we tell LIO that an extent has resized.
DeltaFile
+2-2src/middlewared/middlewared/plugins/iscsi_/lio.py
+2-21 files

FreeNAS/freenas 6a9e72a — tests/sharing_protocols/iscsi test_269_iscsi_pr_failover.py

Add test_write_and_read_through_the_standby_port
DeltaFile
+60-2tests/sharing_protocols/iscsi/test_269_iscsi_pr_failover.py
+60-21 files

FreeNAS/freenas 0d4d753 — tests/sharing_protocols/iscsi conftest.py test_268_iscsi_pr_identity.py

Add LIO per-I_T-nexus UA/PR and HA failover tests

test_266: LIO ALUA, single node and HA, including hard failover.
test_267: unit attentions are queued and reported per I_T nexus.
test_268: PR identity: ISID, ports, unregistered nexuses.
test_269: PR state across failover and failback (S7 to S22).

conftest.py and iscsi_ua_pr_utils.py hold the shared fixtures and
helpers; the fixtures are opt-in and the existing tests are unaffected.
DeltaFile
+1,384-0tests/sharing_protocols/iscsi/test_266_iscsi_lio_alua.py
+1,061-0tests/sharing_protocols/iscsi/test_269_iscsi_pr_failover.py
+897-0tests/sharing_protocols/iscsi/iscsi_ua_pr_utils.py
+579-0tests/sharing_protocols/iscsi/test_267_iscsi_ua_pr_per_nexus.py
+408-0tests/sharing_protocols/iscsi/test_268_iscsi_pr_identity.py
+109-0tests/sharing_protocols/iscsi/conftest.py
+4,438-06 files

FreeNAS/freenas d6b3f36 — src/middlewared/middlewared/utils/lio config.py

Make LIO directory teardown failure log an error
DeltaFile
+27-48src/middlewared/middlewared/utils/lio/config.py
+27-481 files

FreeNAS/freenas 96b8f54 — tests/protocols __init__.py iscsi_proto.py

Add context_params to iscsi_scsi_connect()

Pass an optional context_params dict through to python-scsi's
init_device(), so a test can set pre-login iscsi.Context options such
as an explicit ISID.  context_params_supported() lets callers skip when
the installed python-scsi predates it.

Also ruff.
DeltaFile
+41-6tests/protocols/iscsi_proto.py
+8-1tests/protocols/__init__.py
+49-72 files

FreeNAS/freenas f8adcad — tests/sharing_protocols/iscsi test_269_iscsi_pr_failover.py

Check S22's holder by access, not by READ FULL STATUS port

check_s22 looked for the holding registration by its RELATIVE TARGET
PORT IDENTIFIER in READ FULL STATUS. For an ALL_TG_PT registration that
field is not defined (SPC-5 6.16.4) and LIO reports 0, so the check
failed in every phase although the state was correct.

Assert instead that every registration belongs to the ALL_TG_PT
initiator port and that exactly one holds the reservation, and identify
the holding port by access: through the STANDBY port the nexus has a
holder's access, through the ACTIVE port a registered non-holder's.
DeltaFile
+13-9tests/sharing_protocols/iscsi/test_269_iscsi_pr_failover.py
+13-91 files

FreeNAS/freenas fe79aaf — src/middlewared/middlewared/plugins/failover_ event.py, src/middlewared/middlewared/plugins/iscsi_ alua.py lio.py

Harden LIO ALUA state updates on failover

Log and skip a failed write to one storage object's ALUA group instead
of aborting, and do not let an ALUA error abort vrrp_master.

On takeover, set both controller groups to TRANSITIONING before pool
import; the peer's group still held ACTIVE_OPTIMIZED from when this node
was STANDBY.

When the STANDBY syncs, retry the ACTIVE's refresh_alua_states until it
gives the STANDBY's group NONOPTIMIZED. The ACTIVE's own ha_state can lag,
and one missed refresh left the group UNAVAILABLE until the next reload.
DeltaFile
+48-21src/middlewared/middlewared/plugins/iscsi_/lio.py
+36-10src/middlewared/middlewared/plugins/iscsi_/alua.py
+8-2src/middlewared/middlewared/plugins/failover_/event.py
+92-333 files

FreeNAS/freenas e3e452a — src/middlewared/middlewared/api/v28_0_0 iscsi_global.py

Allow iSCSI mode=2
DeltaFile
+1-1src/middlewared/middlewared/api/v28_0_0/iscsi_global.py
+1-11 files

FreeNAS/freenas 699da80 — tests/sharing_protocols/iscsi test_269_iscsi_pr_failover.py

Add test_s24_grown_file_extent_is_seen_by_open_sessions
DeltaFile
+75-1tests/sharing_protocols/iscsi/test_269_iscsi_pr_failover.py
+75-11 files

FreeNAS/freenas 1c2b99a — tests/sharing_protocols/iscsi test_269_iscsi_pr_failover.py

Add test_s23_registration_dropped_with_its_acl
DeltaFile
+35-3tests/sharing_protocols/iscsi/test_269_iscsi_pr_failover.py
+35-31 files

FreeNAS/freenas 27e27bf — src/middlewared/middlewared/plugins/failover_ event.py, src/middlewared/middlewared/plugins/iscsi_ lio.py

Reload lio_ha as STANDBY when demoted without a reboot

vrrp_backup started iscsitarget in LIO mode, which does not reload a
loaded lio_ha.  A node demoted without a reboot kept the lio_ha it had
as ACTIVE, with forwarding cleared: as BACKUP it did not forward, and
lio_ha now refuses to set forwarding again.  Restart iscsitarget in
that case, which reloads lio_ha with default_forward_active=1.
DeltaFile
+14-0src/middlewared/middlewared/plugins/iscsi_/lio.py
+8-1src/middlewared/middlewared/plugins/failover_/event.py
+22-12 files

FreeNAS/freenas 4703160 — src/middlewared/middlewared/plugins/iscsi_ alua.py extents.py, src/middlewared/middlewared/utils/lio config.py

Add middleware support for LIO ALUA HA

Wire up the middleware side of LIO ALUA high-availability: load
lio_ha.ko with per-node addresses on service start, manage ALUA
state across failover events, clean up STANDBY configfs on pool
export, and add pre-flight validation that targets have static
initiator ACLs before ALUA can be enabled.

For each target, create a portal-less phantom TPG carrying the peer
node's controller group so that a single RTPG response from any
connected port lists both ALUA groups.  Write tpgt_N/rtpi explicitly
before enable so that relative target port IDs in RTPG match the
tag formula (portal.tag on Node A, portal.tag + 32000 on Node B)
rather than being auto-assigned sequentially by the kernel.

ALUA group states are driven by role and ha_state:

  MASTER  + synced        local=OPTIMIZED     remote=NONOPTIMIZED
  MASTER  + connected     local=OPTIMIZED     remote=TRANSITIONING

    [4 lines not shown]
DeltaFile
+541-135src/middlewared/middlewared/utils/lio/config.py
+214-2src/middlewared/middlewared/plugins/iscsi_/lio.py
+87-71src/middlewared/middlewared/plugins/iscsi_/fs_attachment_delegate.py
+89-58src/middlewared/middlewared/plugins/iscsi_/target_to_extent.py
+59-47src/middlewared/middlewared/plugins/iscsi_/extents.py
+62-9src/middlewared/middlewared/plugins/iscsi_/alua.py
+1,052-3228 files not shown
+1,236-37114 files

FreeNAS/freenas 7933b2e — src/middlewared/middlewared/plugins/iscsi_ lio.py

Set the peer's ALUA group when LIO becomes ACTIVE

On takeover, set_alua_active() wrote only the local controller group.
The peer's group kept the value this node had given it while STANDBY,
ACTIVE/OPTIMIZED. Nothing else rewrote it until the peer came back,
reached lio_ha 'synced' and called refresh_alua_states() on this node.
Until then, REPORT TARGET PORT GROUPS advertised the down peer as the
optimized path. If that remote call failed, the wrong state stayed,
because the failure is only logged.

set_alua_active() now writes both groups. The local group becomes
OPTIMIZED, and the peer's group gets the state the ACTIVE node gives
for the current ha_state: NONOPTIMIZED when synced, UNAVAILABLE when
disconnected, otherwise TRANSITIONING.

refresh_alua_states() uses the same table, so the disconnected case now
writes UNAVAILABLE rather than TRANSITIONING. That matches the table in
utils/lio/config.py, so the reconciler and the event handlers no longer
disagree about the peer's state.
DeltaFile
+39-24src/middlewared/middlewared/plugins/iscsi_/lio.py
+39-241 files

NetBSD/pkgsrc G0xjMFq — doc CHANGES-2026

   Updated www/freenginx to 1.30.2
   Updated www/freenginx-devel to 1.31.5
VersionDeltaFile
1.7911+3-1doc/CHANGES-2026
+3-11 files

LLVM/project 54b2a57 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

[RISCV][P-ext] Fix crash on v2i32 extract_vector_elt with a variable index on RV32.

Assisted-by: Claude
DeltaFile
+63-39llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+6-3llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+69-422 files

NetBSD/pkgsrc IdZjCYX — www/freenginx options.mk Makefile

   www/freenginx: update: 1.30.1 -> 1.30.2

   While I'm here fix fetch echo third-party module.

   Sponsored by:        tipi.work

   <ChangeLog>

   *) Security: one of the keys was left uninitialized when using automatic
      rotation of TLS session ticket keys, making it possible to forge a
      session and bypass client certificate verification (CVE-2026-97629);

   </ChangeLog>
VersionDeltaFile
1.13+4-4www/freenginx/distinfo
1.18+2-3www/freenginx/Makefile
1.11+2-2www/freenginx/options.mk
+8-93 files