PR/60597: RVP: Instead of assuming that writing to a UDP port is an immediate
success, wait for a bit for the ICMP port unreachable message to reach us.
e1000: Report 82576 memory ECC errors
82576 exposes clear-on-read corrected error counters for RX, TX,
switch, IPsec, descriptor-handler, PCIe retry, PCIe write, and
MSI-X memories. The packet and descriptor memories also count
uncorrectable errors.
Sample each status register exactly once from the regular hardware
statistics update and immediately before handling a memory-error
interrupt. Group the counters by packet buffer, descriptor handler,
and PCIe region. Skip the absent IPsec block on 82576NS.
PRBESTS and PMSIXESTS are shared by both LAN ports. Attribute an
indication to whichever attached port samples the clear-on-read
register first so it is not counted twice.
Hardware validation used an 82576EB revision 1. All nine implemented
status registers reported their ECC-enable bit set. The sysctl
counters remained clear across interface lifecycle, two-stream
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e1000: Recover from 82576 memory errors
82576 reports fatal and non-fatal internal memory errors through
ICR.FER and ICR.NFER and identifies the affected memory in its
native PEIND layout. Fatal errors can stop transmit, receive, or
both until software resets and reinitializes the port.
Enable the controller-wide parity detector and implemented PEINDM
reaction bits after hardware initialization, while preserving unrelated
register state and omitting the absent IPsec memories on 82576NS.
Enable both interrupt causes and capture the read-clear PEIND register
in the interrupt filter.
Keep the causes masked while the iflib admin task owns the event.
Acknowledge non-fatal packet data errors without disrupting the port.
Request normal port reinitialization for FER, a fatal PEIND source, or
the memory hang indication. Do not apply the later I210/I350 register
layout or their special PCIe parity reset order.
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e1000: Report corrected I350 ECC errors
I350 does not interrupt for corrected internal ECC errors. Instead,
the PCIe, DMA, packet buffer, loopback, and management memories expose
sticky status bits in their region-specific status registers.
Sample those bits with the regular hardware statistics update, preserve
the RX and TX packet buffer ECC enable state while clearing RW1C
indications, and expose counters grouped by memory region. Each counter
records observed indication bits rather than exact error counts because
repeated corrections between samples collapse into one sticky bit.
On an I350 (8086:1521 revision 1), the ECC enables remained set. All
corrected-error status registers remained clear across boot, interface
down/up, three FER recovery resets, and bidirectional line-rate traffic.
The device has no documented corrected error injector. Therefore, the
per-region paths were validated against the register definitions rather
than an injected SRAM error.
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e1000: Recover from I350 memory errors
I350 reports uncorrectable internal memory errors through ICR.FER and
identifies the affected region in PEIND. Depending on the region and
memory, hardware stops transmit, receive, or all PCIe and DMA traffic
until the port is reset and reinitialized.
Enable FER and all regional indication masks. Capture the read-clear
status in the interrupt filter.
Record the fatal PCIe, DMA, and LAN status registers, keep FER masked
while recovery is pending, and expose per-region indication counters.
Use the datasheet required port reset before master disable order for
PCIe parity errors. Reset for PCIe, DMA, and traffic-affecting LAN
errors. Statistics and VF-mailbox parity errors only require their
status to be discarded and cleared; management-memory recovery remains
under firmware control.
Validated on an I350 (8086:1521 revision 1). Three software-set FER
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Revert "[Clang] Support friend declarations with a dependent nested-name-specifier" (#216549)
Reverts llvm/llvm-project#208345
---
Revert dependent friend support due to GCC build failure
e1000: Report corrected I210 and I211 ECC errors
I210 and I211 do not interrupt for corrected internal ECC errors.
Instead, the DMA packet-buffer and PCIe memories expose sticky status
bits in PBECCSTS and PCIEECCSTS.
Sample these bits with the regular hardware statistics update, preserve
the I210/I211 PBECCSTS enable state while clearing its RW1C indication,
and expose separate counters for the DMA packet buffer, PCIe transmit
data, and PCIe retry buffer.
The counters represent observed indications rather than exact error
counts because multiple corrections between samples collapse into one
sticky status bit.
Hardware validation used an I210 revision 3. Unlike I225 and I226, the
published I210/I211 register definitions do not expose self-clearing
injectors for these corrected ECC memories. The three counter sysctls
were present and remained zero under line-rate traffic and three fatal
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e1000: Recover from I210 and I211 memory errors
I210 and I211 report uncorrectable internal memory errors through
ICR.FER and identify the affected region in PEIND. Depending on the
region, hardware stops transmit or all PCIe and DMA traffic until the
port is reset and reinitialized.
Enable FER and all regional indication masks. Discard indication state
left by firmware before enabling reactions, capture the read-clear
status in the interrupt filter, and keep the cause masked while recovery
is pending. Report the affected regions and expose per-region
indication counters. Management-only errors remain under firmware
control.
PCIe region parity errors require a different recovery order from the
normal reset path. Assert the port-local CTRL.RST bit, wait at least
3 ms, verify reset completion, disable master requests, clear
PCIEERRSTS, and then enter normal port reinitialization. Do not use the
device-wide CTRL.DEV_RST sequence used by I225 and I226.
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[VectorCombine] Drop invariant.group from scalarized stores (#212473)
!invariant.group is tied to a pointer SSA value, so it cannot be copied
from a vector store to a scalar store that uses a newly created GEP.
Drop the metadata after copying the remaining store metadata and update
the regression expectations.
Fixes https://github.com/llvm/llvm-project/issues/212472
Assisted-by: Codex
ure: add USB device IDs for additional RTL8152/RTL8153 adapters
Add device IDs for several USB Ethernet adapters that use
RTL8152 and RTL8153 chips but are not yet recognized by ure(4).
This includes adapters from Cisco/Linksys, D-Link, Lenovo,
Microsoft Surface, Realtek, Samsung, and TP-Link.
All added devices use chip revisions already handled by
ure_read_chipver().
Signed-off-by: Christos Longros <chris.longros at gmail.com>
Reviewed by: adrian
Differential Revision: https://reviews.freebsd.org/D55748
ure(4): Fix spurious link flaps from MII
A race condition in the MII layer causes spurious link down events.
In `statchg`, on link down, check if the PHY reports the link as
actually down using the BMSR register, if not, force the status of the
link to back up and restart TX. Do the same in a MII `linkchg` handler.
On actual link up, restart TX in case it went idle and down.
PR: 252165
Signed-off-by: Rafael Kitover <rkitover at gmail.com>
Reviewed by: pouria
Differential Revision: https://reviews.freebsd.org/D55682
[clang][bytecode] Fix assertion failure in in valid continue stmt (#216547)
We need to handle the missing TargetLabel here, similarly to what we do
in break statements.
e1000: Report PCH packet buffer ECC statistics
PCH packet buffer ECC status contains read-clear byte counters for
corrected and uncorrected errors. Sample them with the regular
hardware statistics update and account for the snapshot captured by
the fatal error interrupt path.
Expose the counters and the number of reset worthy interrupt
indications under dev.em.N.memory_errors. Keeping the reset counter
separate also preserves evidence when another status reader wins the
read-clear race.
Hardware validation used an I219-LM. Three documented ICS.ECCER
injections advanced fatal_resets from zero to three, exactly once per
reset. corrected_packet_buffer and uncorrected_packet_buffer remained
zero, as expected because ICS does not inject a memory error or alter
PBECCSTS.
MFC after: 2 weeks
Sponsored by: BBOX.io
e1000: Recover from PCH packet buffer ECC errors
PCH LAN controllers beginning with I217 report uncorrectable
packet buffer ECC errors through ICR.ECCER. Descriptor memory errors
stop the MAC and require a reset before traffic can resume.
Enable the interrupt on the PCH generations whose shared code setup
enables packet buffer ECC. Capture the read-clear PBECCSTS value in
the interrupt filter, mask ECCER while recovery is pending, and request
an iflib reset from the admin task. Reenable the cause only after
hardware initialization succeeds.
Hardware validation used an I219-LM and the documented ICS.ECCER bit to
generate the fatal interrupt. This synthesizes the interrupt cause but
does not corrupt packet buffer memory or alter its ECC byte counters.
Three injections in one boot each requested one reset and recovered
traffic without a panic or watchdog. IMS.ECCER and PBECCSTS.ECC_ENABLE
remained set after every reset.
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[MLIR][LLVM] Preserve pointer-valued metadata operands on import (#215743)
convertMetadataToAttrImpl only modelled ConstantInt operands wrapped in
a ConstantAsMetadata, so any metadata node containing a pointer constant
could not be represented and the whole node was rejected.
Add #llvm.md_null and #llvm.md_addrspacecast to model
ConstantPointerNull and addrspacecast constant expressions, keeping the
address space so that `ptr null` and `ptr addrspace(1) null` stay
distinct. MDAddrSpaceCastAttr verifies that its operand is itself
pointer-valued metadata.
Global values are constants, so ValueAsMetadata::get wraps them in a
ConstantAsMetadata and they never reached the ValueAsMetadata case.
Match them in the ConstantAsMetadata case instead, which also
generalizes the existing function-only handling to any named global
value and makes the addrspacecast operand representable.
Mirror both attributes in ModuleTranslation::convertMetadataAttr so the
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misc/xdelta3: Update to 3.2.0 and take maintainership
Port changes:
- Switch the upstream build from Autotools to CMake
(see https://github.com/jmacd/xdelta)
- Update the declared license from GPLv2+ to Apache 2.0
(as per https://github.com/jmacd/xdelta)
- Enable armor support and the static-library build
- Install the public header, static library, pkg-config file, and CMake
package metadata
- Remove the obsolete regtest patch (not required anymore due to
changes to the build infrastructure)
- Update WWW, COMMENT, and pkg-descr to reflect these chagnes
- Add a complete pkg-plist
Changelog: https://github.com/jmacd/xdelta/releases/tag/v3.2.0
PR: 297302
Reported by: Thomas Barabosch <oss at tbarabosch.com> (new maintainer)
Reviewed by: diizzy
[InstCombine] Fold shl of constant by cttz into multiply of lowest set bit (#214517)
Currently, `C << cttz(X, true)` generates a DeBruijn lookup table on
RV64I (13 instructions).
And this patch adds a fold in InstCombine:
`C << cttz(X, true) --> (-X & X) * C`
This reduces the instruction count from 13 to 3 on RV64I.
The fold requires that cttz has a single use (to avoid increasing
instruction count)
Alive2 proof: https://alive2.llvm.org/ce/z/TmWxrT
clang/AMDGPU: Stop passing redundant -target-cpu to cc1
Now that the exact target is encoded in the triple's subarch field,
-target-cpu is redundant. This avoids polluting the resultant IR with
unwanted "target-cpu" attributes. The net result is the desired codegen
when compiling libraries for a major subarch and linking it into a
program compiled for a specific arch. e.g., compiling for "gfx9-generic"
would pollute the IR with "target-cpu"="gfx9-generic", so codegen
would ultimately be performed for the generic target even after
linking into the concrete gfx9 cpu. The specialization will now be
achieved by merging the triples without the linker or optimization
passes needing to fixup function attributes.
AMDGPU: Start using subarch in attributor instead of subtarget
Avoid querying the subtarget for functions when the relevant
properties are known from the triple. The various subtarget
group size functions should also be decoupled from the subtarget,
but those are trickier to untangle.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
clang: Start using new amdgpu subarch triples
Fixup invocations using --target=amdgcn + -mcpu to introduce
the subarch in the triple.
For offload toolchains, a single toolchain is constructed for the
top level amdgpu architecture, and the effective triple is used for
target specific tool invocations.
The specifics of the resource directory layout are tbd. This does
try to find resources in the subarch named directory. The paths
are searched at toolchain creation time, so that does not work
when there are multiple subarches.
Fixes #154925
