RegAllocFast: Only clear dead flag for live defs of the same or super reg (#232264)
This is a refinement of #229049, which was too strict.
A dead def is only contradicted by a live def of the same register or
a super-register. A dead super-register def with a live sub-register
def is consistent, and is what LiveVariables produces when only part
of a register is used. Checking register unit coverage also cleared
the dead flag in that case when the registers have the same units,
such as $rax and $eax on x86_64.
Track the live physical register defs of the instruction and check for
a super-register instead of stamping register units.
I'm questioning whether regallocfast should be trying to set dead
flags at all. Functionally, it only introduces these flags on
pre-existing physreg references which ideally would never happen. The
edge case where it does add the flag on assigned registers is the
error case where the first register in the allocation order is forced
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[CIR][CUDA][HIP] Skip global init for device variables (#231971)
Sema allows only empty or constant initializers and empty dtors on
__device__, __constant__ and __shared__ variables, so they need no
dynamic init
CIR emitted a dtor registration that failed to verify
[AMDGPU] Custom lower dynamic insertelt on wide vectors of 16-bit elements
Currently, in case of dynamic-index `insertelement` into v8, v16 and v32 of i16, f16 and bf16 was
set to Expand. At -O1 and above, single inserts were expanded into a select per
element and chains of inserts were folded into a stack temporary. At -O0,
every insert went through the stack unconditionally.
This patch extends the existing `v_bfi_b32` lowering, previously limited to
64-bit vectors, to the 16-bit wide vectors as well, making `INSERT_VECTOR_ELT` as
now Custom for them, so legalization uses the custom lowering at all
optimization levels, and the generic DAGCombiner chain fold, which only applies
to Expand types, no longer fires.
In 'lowerINSERT_VECTOR_ELT' each 64-bit sized
piece updates with `(Mask & splat(Val)) | (~Mask & Piece)`, where only the piece holding
the index gets a nonzero mask, alongwith skipping `performInsertVectorEltCombine` that use
select-per-element expansion for such types, since the custom lowering is
cheaper. wider i8 vectors still use the stack.
[clang] Add regression test for GH53049 (#232266)
Add a reduced, library-independent test for a recursive exception
specification triggered by std::sort with a reference-wrapped
std::function.
Clang 21 incorrectly rejected this code, while current Clang accepts it.
Fixes #53049
[LoongArch] Add arithmetic instruction costs (#232230)
Provide latency and reciprocal-throughput costs for arithmetic, logical,
shift and FP operations on LA32/LA64 and LSX/LASX, measured on 3A6000
(LA664). Unhandled cases fall back to the base implementation.
[llvm-readobj][ELF] Print Names for call graph relocations
In a relocatable object file, an entry identified by a relocation had no
Names. Compute the address that the relocation resolves to with
RelocationResolver, look up the functions at that address in the section
of the relocation's symbol, and print them as Names before the
Relocation object.
As with Names for an Address, the names follow --demangle. Nothing is
printed for an undefined symbol, or when no function is at the address.
A relocation type that RelocationResolver doesn't support, or a symbol
whose section can't be found, gets a warning.
Assisted-by: Gemini
[llvm-readobj][ELF] Fall back to Address when no single relocation applies
In a relocatable object file, --call-graph-info identifies a function by
the relocation that applies to its address field. If a field had no
relocation, nothing in the output identified the function. If the
relocation section had an invalid sh_link, the dump stopped. If a field
had more than one relocation, the first one was used silently.
In all of these cases, print the value stored in the field as Address,
as for linked files. Warn once if a call graph section has no relocation
section, and warn about each field with no relocation or more than one.
If the relocations can't be read, only that is reported.
Assisted-by: Gemini
[llvm-readobj][ELF] Print implicit addends of call graph relocations
A SHT_REL relocation, or a SHT_CREL relocation without explicit addends,
keeps its addend in the field that it applies to. Print the
sign-extended field value as the Addend of such a relocation instead of
dropping it. The ARM test now uses SHT_REL and covers the same cases as
the SHT_RELA tests: named symbols, a negative addend, and a section
symbol with an addend.
Assisted-by: Gemini
[llvm-readobj][ELF] Print a Relocation object instead of Name in --call-graph-info
In a relocatable file, the address fields of a call graph section hold
placeholders, and the relocation that applies to each field identifies
the function. Name showed only the relocation's symbol name, made up
from the section name for an unnamed section symbol, and dropped the
addend. So entries that refer to a function through a section symbol
couldn't be told apart.
Print a Relocation object instead, with the symbol index, the symbol
name exactly as recorded in st_name, and the addend if it is non-zero.
With --demangle, the demangled symbol name is printed as DemangledName.
If the symbol can't be read, the existing warning is reported and only
the symbol index is printed.
Assisted-by: Gemini
[llvm-readobj][NFC] Match call graph relocations to address fields in one pass (#230650)
Read the relocations for a call graph section once, sort them by offset,
and attach each one to the address field it applies to while walking the
fields in order. Each field now stores the existing `Relocation<ELFT>`,
so the printing code no longer searches the relocation list for every
field. The call graph structs become templates so that they can hold it.
Assisted-by: Gemini
[llvm-readobj][ELF] Print call graph callees in section order (#230649)
Keep both the offset and the value of each address field in the call
graph section, and let the printing code pick the one it needs. Later
patches use the offset to look up relocations.
Callees were stored in a SmallSet, which sorts its elements once it
holds more than four, so the output order depended on the number of
callees. They are now kept in section order, and repeated addresses in
linked files are skipped when printing.
Assisted-by: Gemini
AMDGPU: Don't look up ConstantData in the constant access cache
AAAMDAttributes checks the constant operands of all instructions for
address space casts and LDS globals that need the queue pointer or
flat scratch initialization, looking each of them up in a cache. Skip
the lookup for trivial constants which have no operands.
Instructions spent in amdgpu-attributor:
rocPRIM test_device_scan, gfx942: 1429M -> 1419M (-0.7%)
Blender Cycles HIP kernel, gfx1100: 507M -> 506M (-0.2%)
rocPRIM 16 tests, full LTO, closed world: 5283M -> 5263M (-0.4%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[MLIR][Remark] Report why the LLVM remark streamer could not be created (#230130)
`LLVMRemarkStreamer::createToFile` dropped the reason it failed. A file
that could not be opened and a serializer that could not be created both
became a bare failure, so `enableOptimizationRemarksWithLLVMStreamer`
failed without a diagnostic.
- `createToFile` now also returns a reason of a failure as unexpected
result.
- `enableOptimizationRemarksWithLLVMStreamer` now emits the error to the
context.
Assisted-by: Claude Code (Claude Opus 5.5)
NAS-144426 / 27.0.0 / Allow selecting the VM video model (by Qubad786) (#20019)
## Problem
VMs always got a QXL video adapter. QXL can deadlock a Linux guest
during shutdown when the host stops releasing its memory, and it doesn't
exist on aarch64, so aarch64 VMs with a display device couldn't start.
## Solution
Added `video_model` (`QXL`, `VGA`, `VIRTIO`) to VMs. New VMs default to
`VGA`, or `VIRTIO` for aarch64 guests, which only accept `VIRTIO`. The
migration keeps existing x86 VMs with a display on `QXL`, moves headless
VMs from libvirt's implicit cirrus adapter to `VGA`, and sets aarch64
VMs to `VIRTIO`.
This depends on https://github.com/truenas/truenas_pylibvirt/pull/95 and
has to be merged together with it.
Original PR: https://github.com/truenas/middleware/pull/20012
Co-authored-by: M. Rehan <mrehanlm93 at gmail.com>
NAS-144426 / 28.0.0-BETA.1 / Move VM video model migration to 27.0 (#20020)
## Problem
The VM video model change is being backported to 27.0 with its own 27.0
migration. Master's 28.0 migration added the same column, so a 27.0
database stamped with the backported revision would have no path into
master's chain, and master's v27_0_0 API models would not match what
27.0 ships.
## Solution
Added the 27.0 migration as it ships on 27.0, made the 28.0 migration a
no-op that keeps its revision so installs that already recorded it keep
a valid chain, and added a merge migration joining the two. The 27.0
migration skips itself when the column already exists, so nightlies that
ran the original 28.0 migration keep their values. Also added
`video_model` to master's v27_0_0 VM models to match 27.0.
[AArch64] add patterns for SQABS (#229812)
Recognise umin(abs(X), signed_max) as a saturating absolute value and
select SQABS for legal Neon and SVE2/SME vectors.
