LLVM/project cc4f4b1libcxx/include __split_buffer, libcxx/include/__vector vector.h

Revert "[libcxx] Add `__split_buffer::__swap_layouts` (#180102)"

This reverts commit 65f39a16abf651008185839459fb330258800a62.
DeltaFile
+16-3libcxx/include/__vector/vector.h
+0-17libcxx/include/__split_buffer
+16-202 files

LLVM/project 1cdcee2clang/lib/CodeGen CGExprScalar.cpp, clang/test/CodeGenHLSL/BasicFeatures MatrixExplicitTruncation.hlsl MatrixImplicitTruncation.hlsl

[HLSL][Matrix] Make matrix truncation respect default matrix memory layout (#184280)

Fixes #183127 and #184371

This PR makes the matrix truncation cast implementation use the new
matrix flattened index helper functions introduced by #182904 so that it
reads elements from the source matrix using the default matrix memory
layout instead of always assuming column-major order.

This PR also fixes a bug where matrix truncation truncated the wrong
elements.

Assisted-by: claude-opus-4.6
DeltaFile
+24-12clang/test/CodeGenHLSL/BasicFeatures/MatrixExplicitTruncation.hlsl
+22-11clang/test/CodeGenHLSL/BasicFeatures/MatrixImplicitTruncation.hlsl
+11-10clang/lib/CodeGen/CGExprScalar.cpp
+57-333 files

LLVM/project 6dea289clang/lib/CIR/CodeGen CIRGenItaniumCXXABI.cpp, clang/test/CIR/CodeGen try-catch-tmp.cpp

[CIR] Implement reference type in init catch param (#184442)

Implement init support for reference type in the init catch param
DeltaFile
+115-0clang/test/CIR/CodeGen/try-catch-tmp.cpp
+17-1clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
+132-12 files

FreeNAS/freenas c92faa5src/middlewared/middlewared event.py

NAS-140179 / 27.0.0-BETA.1 / Introduce typed event source (#18396)

## Context

Introduce `TypedEventSource` which to the `run` body gives access to the
pydantic model itself which should be used so we can statically type
check properly arguments.
DeltaFile
+21-0src/middlewared/middlewared/event.py
+21-01 files

Illumos/gate 196cb0eusr/src/cmd/svc/configd configd.c

17900 svc/configd: format issue while printing pid_t
Reviewed by: Gordon Ross <Gordon.W.Ross at gmail.com>
Approved by: Dan McDonald <danmcd at edgecast.io>
DeltaFile
+1-1usr/src/cmd/svc/configd/configd.c
+1-11 files

LLVM/project d259193clang/lib/CIR/CodeGen CIRGenExprScalar.cpp CIRGenExprComplex.cpp

[CIR] Fix operator-precedence bugs in assert conditions

Due to && binding tighter than ||, asserts of the form
assert(A || B && "msg") always pass when A is true. Add
parentheses so the string message is properly attached:
assert((A || B) && "msg").
DeltaFile
+8-7clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+4-5clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
+12-122 files

FreeNAS/freenas 9c501d3tests/api2 test_300_nfs.py

Add many small-ish tweaks to add resilience to idiosyncrasies in running the CI tests.
A good part of this is handling the 'websocket' disconnect.
DeltaFile
+166-35tests/api2/test_300_nfs.py
+166-351 files

LLVM/project d34f179llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.exp.ll llvm.amdgcn.exp.row.ll

AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_exp/exp_row (#181956)
DeltaFile
+57-10llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
+9-5llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
+11-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+10-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
+93-176 files

FreeBSD/ports 27001d6mail/thunderbird distinfo Makefile

mail/thunderbird: update to 148.0.1 (rc1)

Release Notes:
  https://www.thunderbird.net/en-US/thunderbird/148.0.1/releasenotes/

(cherry picked from commit d454980ee94c47d12a2195f2dab12ced70e11526)
DeltaFile
+3-3mail/thunderbird/distinfo
+1-1mail/thunderbird/Makefile
+4-42 files

FreeBSD/ports d454980mail/thunderbird distinfo Makefile

mail/thunderbird: update to 148.0.1 (rc1)

Release Notes:
  https://www.thunderbird.net/en-US/thunderbird/148.0.1/releasenotes/
DeltaFile
+3-3mail/thunderbird/distinfo
+1-1mail/thunderbird/Makefile
+4-42 files

LLVM/project dc8de10llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

[AMDGPU][SIInsertWaitcnts][NFC] Simplify logic in GFX12Plus::applyPreexistingWaitcnts (#184925)

The loop is collecting the first instruction of each waitcnt kind and is
erasing the rest, with the exception of DEPCTR which needs more checks.
The existing code was factoring out the instruction deletion and the
setting of the collected instruction variables. But the special handling
for DEPCTR and the in-loop deletion of `S_WAITCNT_lds_direct` was just
complicating the logic.
DeltaFile
+40-29llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+40-291 files

LLVM/project 89d6936llvm/test/CodeGen/AArch64 fp-maximumnum-minimumnum.ll arm64-build-vector.ll

[AArch64][GlobalISel] Add more gisel test coverage. NFC
DeltaFile
+2,071-1,930llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
+125-56llvm/test/CodeGen/AArch64/arm64-build-vector.ll
+122-57llvm/test/CodeGen/AArch64/fdiv-const.ll
+76-39llvm/test/CodeGen/AArch64/isinf.ll
+78-18llvm/test/CodeGen/AArch64/f16-imm.ll
+59-27llvm/test/CodeGen/AArch64/half-precision-signof-no-assert.ll
+2,531-2,1273 files not shown
+2,616-2,1609 files

LLVM/project 65f39a1libcxx/include __split_buffer, libcxx/include/__vector vector.h

[libcxx] Add `__split_buffer::__swap_layouts` (#180102)

This commit simplifies the cumbersome process of swapping the respective
layout members for `__split_buffer` and `vector`.
DeltaFile
+3-16libcxx/include/__vector/vector.h
+17-0libcxx/include/__split_buffer
+20-162 files

LLVM/project ab5844dllvm/lib/Target/AMDGPU SILoadStoreOptimizer.cpp, llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll promote-constOffset-to-imm-gfx12.mir

[AMDGPU] Disable negative imm offset for async load/store instructions (#185078)

They are not allowed by the HW.
DeltaFile
+99-171llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+64-21llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
+75-10llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+34-40llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
+6-6llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
+278-2485 files

LLVM/project 6bd99efflang/include/flang/Optimizer/Dialect/CUF CUFOps.td, flang/lib/Lower Bridge.cpp

[flang][cuda] Add hasManagedOrUnifedSymbols attribute to cuf.data_transfer op (#185106)

Add an attribute to signal the presence of managed or unified symbols in
the data transfer. In some case, the presence of such symbols require to
insert synchronization. Adding the attribute in the op during lowering
facilitate the recognition of such data transfer.
DeltaFile
+16-6flang/lib/Lower/Bridge.cpp
+11-1flang/test/Lower/CUDA/cuda-data-transfer.cuf
+4-3flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
+31-103 files

LLVM/project e820236clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.h

[CIR] Fix convertSideEffectForCall header/definition signature mismatch

Add missing bool &noReturn parameter to the declaration in
LowerToLLVM.h to match the definition in LowerToLLVM.cpp.
DeltaFile
+1-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
+1-11 files

FreeNAS/freenas 763ecc0src/middlewared/middlewared/service crud_service_part.py

NAS-140178 / 27.0.0-BETA.1 / Fix CRUD service part query overload (#18395)

## Context

We need to fix CRUD Service part query overloads similar to
https://github.com/truenas/middleware/pull/18394.
DeltaFile
+3-3src/middlewared/middlewared/service/crud_service_part.py
+3-31 files

FreeBSD/ports a0a0115sysutils/storcli Makefile distinfo

sysutils/storcli: Update 7.3503 => 7.3603

PR:     293539
DeltaFile
+5-5sysutils/storcli/Makefile
+3-3sysutils/storcli/distinfo
+8-82 files

LLVM/project 8793c32clang/test/CIR/CodeGenOpenACC private-clause-pointer-array-recipes-CtorDtor.cpp combined-reduction-clause-default-ops.cpp, clang/test/CIR/IR cmp.cir

[CIR] Change CmpOp assembly format to use bare keyword style

Update the assembly format of cir.cmp from the parenthesized style
  cir.cmp(gt, %a, %b) : !s32i, !cir.bool
to the bare keyword style used by other CIR ops like cir.cast:
  cir.cmp gt %a, %b : !s32i

The result type (!cir.bool) is now automatically inferred as it is
always cir::BoolType.
DeltaFile
+64-64clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-CtorDtor.cpp
+60-60clang/test/CIR/IR/cmp.cir
+57-57clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
+352-35281 files not shown
+1,316-1,29387 files

LLVM/project adde5faclang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Fix GlobalOp::getSuccessorRegions using wrong region for dtor
DeltaFile
+1-1clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+1-11 files

FreeNAS/freenas 9be9ec4src/middlewared/middlewared/service crud_service.py

NAS-140176 / 27.0.0-BETA.1 / Fix GenericCRUDService query overload (#18394)

## Context

Fix query overload of GenericCRUDService as if count/get are not set, we
return a list of entries.
DeltaFile
+3-3src/middlewared/middlewared/service/crud_service.py
+3-31 files

Linux/linux 325a118. MAINTAINERS, arch/powerpc/kernel pci_of_scan.c

Merge tag 'pci-v7.0-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull pci fixes from Bjorn Helgaas:

 - Initialize msi_addr_mask for OF-created PCI devices to fix sparc and
   powerpc probe regressions (Nilay Shroff)

 - Orphan the Altera PCIe controller driver (Dave Hansen)

* tag 'pci-v7.0-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
  MAINTAINERS: Orphan Altera PCIe controller driver
  sparc/PCI: Initialize msi_addr_mask for OF-created PCI devices
  powerpc/pci: Initialize msi_addr_mask for OF-created PCI devices
DeltaFile
+7-0arch/powerpc/kernel/pci_of_scan.c
+7-0arch/sparc/kernel/pci.c
+2-4MAINTAINERS
+16-43 files

LLVM/project 2170368clang/test/CIR/CodeGenOpenACC private-clause-pointer-array-recipes-CtorDtor.cpp combined-reduction-clause-default-ops.cpp, clang/test/CIR/IR cmp.cir

[CIR] Change CmpOp assembly format to use bare keyword style

Update the assembly format of cir.cmp from the parenthesized style
  cir.cmp(gt, %a, %b) : !s32i, !cir.bool
to the bare keyword style used by other CIR ops like cir.cast:
  cir.cmp gt %a, %b : !s32i

The result type (!cir.bool) is now automatically inferred as it is
always cir::BoolType.
DeltaFile
+64-64clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-CtorDtor.cpp
+60-60clang/test/CIR/IR/cmp.cir
+57-57clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
+57-57clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
+352-35281 files not shown
+1,317-1,29387 files

FreeBSD/src 1e4086dshare/man/man9 bus_alloc_resource.9, sys/arm/nvidia tegra_pcie.c

sys: Don't pass RF_ALLOCATED to bus_alloc_resource*

This is a nop as eventually these flags are passed to rman_reserve_resource
which unconditionally sets RF_ALLOCATED in the new flags for a region.
However, it's really a layering violation to use RF_ALLOCATED in relation
to struct resource objects outside of subr_rman.c as subr_rman.c uses
this flag to manage it's internal tracking of allocated vs free regions.

In addition, don't document this as a valid flag in the manual.  I
think the intention here was that if a caller didn't want to pass
RF_ACTIVE or RF_SHAREABLE, they could pass RF_ALLOCATED instead of 0,
but given the layering violation, I think it's best to just pass 0
instead in that case.

NB: The bhnd bus uses RF_ALLOCATED (along with RF_ACTIVE) in a
separate API to manage resource regions that are not struct resource
objects (but a separate wrapper object).  It would perhaps be cleaner
if the chipc_retain_region and chipc_release_region functions used
their own flag constants instead of reusing the rman(9) flags.

    [3 lines not shown]
DeltaFile
+3-7share/man/man9/bus_alloc_resource.9
+2-3sys/arm/nvidia/tegra_pcie.c
+1-1sys/x86/iommu/amd_drv.c
+6-113 files

LLVM/project 06f7cd4clang/lib/Headers/hlsl hlsl_intrinsics.h hlsl_alias_intrinsics.h, clang/lib/Sema SemaHLSL.cpp

[HLSL][DirectX] Implement HLSL `mul` function and DXIL lowering of `llvm.matrix.multiply` (#184882)

Fixes #99138

- Defines a `__builtin_hlsl_mul` clang builtin in `Builtins.td`.
- Links the `__builtin_hlsl_mul` clang builtin with
`hlsl_alias_intrinsics.h` under the name `mul` for matrix cases
- Implement scalar and vector elementwise multiplication cases of the
`mul` function in `hlsl_intrinsics.h` and `hlsl_intrinsic_helpers.h`
- Adds sema for `__builtin_hlsl_mul` to `CheckBuiltinFunctionCall` in
`SemaHLSL.cpp`
- Adds codegen for `__builtin_hlsl_mul` to `EmitHLSLBuiltinExpr` in
`CGHLSLBuiltins.cpp`
- Vector-vector cases lower to `dot` (except double vectors, which
expands to scalar multiply-adds).
- Matrix-matrix, matrix-vector, and vector-matrix multiplication lower
to the `llvm.matrix.multiply` intrinsic
- Adds codegen tests to `clang/test/CodeGenHLSL/builtins/mul.hlsl`
- Adds sema tests to `clang/test/SemaHLSL/BuiltIns/mul-errors.hlsl`

    [13 lines not shown]
DeltaFile
+336-0llvm/test/CodeGen/DirectX/matrix-multiply.ll
+109-0clang/test/CodeGenHLSL/builtins/mul.hlsl
+95-0llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
+68-0clang/lib/Headers/hlsl/hlsl_intrinsics.h
+49-0clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+43-0clang/lib/Sema/SemaHLSL.cpp
+700-04 files not shown
+795-010 files

LLVM/project fef16a7mlir/test/Dialect/GPU shuffle-rewrite.mlir, mlir/test/Dialect/Vector vector-warp-distribute.mlir

[mlir][ODS] Fix notorious double-space bug in op printers (#184253)

When an op's assembly format prints an attribute via
`printStrippedAttrOrType`, two independent space-emission mechanisms
would fire: the op format generator emits a space before each argument,
and the attribute's generated `print` method also emits a leading space
(`shouldEmitSpace` initialized to true). This caused double spaces like
`gpu.shuffle xor`.

The usual workaround for this was to add double backticks to consume the
leading space.

Fixed by removing the leading space from generated attr/type `print()`
methods and compensating in the print dispatcher by conditionally adding
a space between the mnemonic and `print` call when the format starts
with a name or keyword rather than punctuation.

Also remove some workarounds for the double-spacing in op formats and
fix tests that now don't have leading spaces.

Assisted-by: claude
DeltaFile
+52-4mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
+20-20mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+17-17mlir/test/Dialect/Vector/vector-warp-distribute.mlir
+4-5mlir/test/mlir-tblgen/attr-or-type-format.td
+5-3mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
+4-4mlir/test/Dialect/GPU/shuffle-rewrite.mlir
+102-538 files not shown
+115-6614 files

Linux/linux dfb3142drivers/accel/amdxdna amdxdna_mailbox.c aie2_pci.c, drivers/gpu/drm/amd/amdgpu amdgpu_userq.c amdgpu_userq_fence.c

Merge tag 'drm-fixes-2026-03-07' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "Weekly fixes pull.

  There is one mm fix in here for a HMM livelock triggered by the xe
  driver tests. Otherwise it's a pretty wide range of fixes across the
  board, ttm UAF regression fix, amdgpu fixes, nouveau doesn't crash my
  laptop anymore fix, and a fair bit of misc.

  Seems about right for rc3.

  mm:
   - mm: Fix a hmm_range_fault() livelock / starvation problem

  pagemap:
   - Revert "drm/pagemap: Disable device-to-device migration"

  ttm:

    [72 lines not shown]
DeltaFile
+81-35drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+49-50drivers/accel/amdxdna/amdxdna_mailbox.c
+37-29drivers/accel/amdxdna/aie2_pci.c
+35-8drivers/gpu/drm/xe/xe_gsc_proxy.c
+15-27drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
+28-8drivers/accel/amdxdna/aie2_message.c
+245-15745 files not shown
+516-29151 files

FreeBSD/ports a9052c7sysutils/py-hcloud distinfo Makefile

sysutils/py-hcloud: update to 2.17.0

Changes:        https://github.com/hetznercloud/hcloud-python/blob/v2.17.0/CHANGELOG.md
Reported by:    portscout, repology
DeltaFile
+3-3sysutils/py-hcloud/distinfo
+1-1sysutils/py-hcloud/Makefile
+4-42 files

LLVM/project bc55e5ellvm/utils/gn/secondary/clang/include/clang/Basic BUILD.gn, llvm/utils/gn/secondary/clang/lib/Basic BUILD.gn

[gn] port 3da28bfbce4d7a (DiagnosticStableIDs)
DeltaFile
+10-5llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
+1-0llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
+11-52 files

LLVM/project 949db45llvm/lib/Target/AMDGPU SILoadStoreOptimizer.cpp

cap the promotion to u16
DeltaFile
+9-2llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+9-21 files