[RISCV] Add the missing SEW search table field to vector FMA instructions (#175646)
We split vector floating point FMA (pseudo) instructions' opcodes by SEW
since c6b7944be4dfbb1fb35301c670812726845acaa7 , but forgot to populate
their `SEW` field, which is used by various search tables. This results
in incorrect pseudo instruction opcodes lookup -- and to a larger
extent, incorrect scheduling class lookups -- in llvm-mca. This patch
fixes such issue.
[cmake] Make CMAKE_BUILD_TYPE=Release the default (#174520)
Currently, we report a fatal error if the user leaves CMAKE_BUILD_TYPE
blank. This was implemented in https://reviews.llvm.org/D124153 /
350bdf9227ceb , based on this RFC:
https://discourse.llvm.org/t/rfc-select-a-better-linker-by-default-or-warn-about-using-bfd/61899/1
Tom Stellard mentioned that he'd like to revisit this on Discord, and
Aiden, myself, and apparently most people on the original RFC agree, so
I'm proposing we do it. However, on the review, several folks objected
and insisted that Debug was a better default. I want to reopen the
question.
I think we've made the wrong tradeoff. I wish Debug builds worked out of
the box on most systems, but they don't, and LLVM has only gotten bigger
over the last four years, making the build scalability problems of Debug
builds worse. I think we should optimize our build configuration for new
developers, not experienced longtime contributors who are invested
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[profcheck] Fix encoding of 0 loopEstimatedTrip count (#174896)
We currently encode an estimated trip count of 0 as the latch having branch probabilities 0-0. That's an invalid pair of weights. The probability of a branch is computed as a fraction of its corresponding weight and the sum of the weights. In fact, `BranchProbabilityInfo::calcMetadataWeights` will convert this to a 1-1, meaning 50% - 50%, which isn't quite what we want. To indicate the loop is never taken, we just need to initialize the exit probability to non-zero (hence, 1)
Related: https://reviews.llvm.org/D67905
Issue #147390
[RISCV] Adjust base cost for Xqcilo loads/stores in RISCVMakeCompressible (#175572)
We only need two uses in Xqcilo load/store instructions for the base
adjustment to be profitable as compared to three uses in the base
load/store instructions.
[CIR][X86] Add support for `intersect` builtins (#172554)
adds support for the
`__builtin_ia32_vp2intersect_d`/`__builtin_ia32_vp2intersect_q` x86
builtins.
Part of #167765
---------
Signed-off-by: vishruth-thimmaiah <vishruththimmaiah at gmail.com>
[flang] Turn -Werror back off for Flang build (#175689)
Different build environments are picking up warnings that my testing
didn't expose; turn -Werror back off.
(And also delete an unused data member that was triggering some MSVC
warnings.)
[RISCV] Use LD_RV32/SD_RV32 for spills and reloads when Zilsd is enabled (#153595)
We are currently only using `PseudoRV32ZdinxSD/LD` for spills and
reloads when the register class is `GPRPairRegClass` . However, we can
use `LD_RV32/SD_RV32` when the `Zilsd` extension is enabled and certain
alignment requirements are met.
[Darwin] [compiler-rt] Normalize DYLD_LIBRARY_PATH to workaround LD bug (#175685)
There is an issue in certain versions of LD which causes the wrong
libLTO to be used if the DYLD_LIBRARY_PATH is not normalized.
Will fix these failures:
```
AddressSanitizer-x86_64-darwin.TestCases/Darwin.odr-lto.cpp
AddressSanitizer-x86_64h-darwin.TestCases/Darwin.odr-lto.cpp
```
https://green.lab.llvm.org/job/llvm.org/job/clang-stage1-cmake-RA-incremental/13428/
rdar://168024431
[flang] Temporarily disabled a check in a test that was breaking buildbots (#175684)
PR https://github.com/llvm/llvm-project/pull/175383 had breaking test
Semantics/OpenMP/linear-clause01.f90
I disabled problematic part of the test for now to let the builds pass.
I will file the issue for PR author to fix the test.
[clang][Tooling] Fix assertion failure when processing CUDA files (#173762)
Running clang-tidy on CUDA files without specifying `--cuda-host-only`
or `--cuda-device-only` would trigger an assertion failure in
`Actions.size() > 1`, a related discussion:
https://github.com/llvm/llvm-project/pull/173699#discussion_r2649279975.
This occurred because the Clang Driver generates a single top-level
`OffloadAction` in `-fsyntax-only`, `-E`, `-M`. This commit removes the
overly strict assertions.
Closes #173777
If joined to an AD or IPA domain the 'domain' field in the network configuration cannot be changed.
Renamed the test_ssh.py CI module to Test_directory_services_basic.py and added a CI test for domain name changing.
[llvm-jitlink] Remove flaky testcase. (#175680)
On some systems, backtraces contain addresses with their high bits set*.
These high bits prevent symbolication using the JIT symbol table. Since
this test is for a best-effort debugging / diagnosis tool it seems best
to remove the test until/unless we can get it passing on all systems, or
find some way to identify systems that will fail.
See discussion in https://github.com/llvm/llvm-project/pull/175537.
* Note that the test does not use PAC or pointer tagging -- the high
bits are coming from somewhere else. Possibly libunwind, but that is
just speculation.
devel/gamin: Unbreak and improve port
* Update MASTER_SITES and WWW
* Rework port Makefile to follow porters handbook more closely
Initial patch submitted by mew14930xvi
PR: 292327
Reported by: Evgenii Khramtsov <2khramtsov at gmail.com>