LLVM/project f190477clang/include/clang/Basic BuiltinsAMDGPU.td, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics (#170813)

DeltaFile
+86-0clang/test/Sema/wave-reduce-builtins-validate-amdgpu.cl
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+26-22clang/include/clang/Basic/BuiltinsAMDGPU.td
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+204-224 files

LLVM/project 4ded7e0llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fadd.ll llvm.amdgcn.reduce.fsub.ll

[AMDGPU] Add wave reduce intrinsics for double types - 2 (#170812)

Supported Ops: `add`, `sub`
DeltaFile
+1,115-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+1,102-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+91-19llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2,310-194 files

LLVM/project d1817c4llvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+76-4llvm/docs/AMDGPUUsage.rst
+76-41 files

LLVM/project 9e7919allvm/lib/Target/AMDGPU SIISelLowering.cpp

Use getRegClass() API
DeltaFile
+1-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-21 files

LLVM/project 88ec5a0clang/include/clang/Basic BuiltinsAMDGPU.td, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+86-0clang/test/Sema/wave-reduce-builtins-validate-amdgpu.cl
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+26-22clang/include/clang/Basic/BuiltinsAMDGPU.td
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+204-224 files

LLVM/project 61d5361llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fsub.ll llvm.amdgcn.reduce.fadd.ll

Use _pseudo instead of _gfx12 encoding, plus minor code cleanup
DeltaFile
+19-14llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+27-223 files

LLVM/project daefbefllvm/lib/Target/AMDGPU SIISelLowering.cpp

Refactor code and add some comments
DeltaFile
+8-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+8-51 files

LLVM/project 66042a3llvm/lib/Target/AMDGPU SIISelLowering.cpp

    Avoid generation check in callee function
DeltaFile
+17-7llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+17-71 files

LLVM/project 0ee4dd0llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fadd.ll

use `v_mul_f64_pseudo_e64`
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-42 files

LLVM/project 7794646llvm/lib/Target/AMDGPU SIISelLowering.cpp

Use `WAVE_REDUCE_FSUB_PSEUDO_F64` in switch statements
DeltaFile
+17-13llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+17-131 files

LLVM/project eab54ballvm/lib/Target/AMDGPU SIISelLowering.cpp

Use pseudo opcode for switch statements
DeltaFile
+9-9llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+9-91 files

LLVM/project 6cf1198llvm/lib/Target/AMDGPU SIISelLowering.cpp

Don't use the pseudo as a case label.
DeltaFile
+17-23llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+17-231 files

LLVM/project cedbeaellvm/lib/Target/AMDGPU SIISelLowering.cpp

Use enum values for source modifiers
DeltaFile
+3-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-31 files

LLVM/project 49be7ballvm/lib/Target/AMDGPU SIISelLowering.cpp

Use `e32` encoding as placeholder
DeltaFile
+9-9llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+9-91 files

LLVM/project 70226dbllvm/lib/Target/AMDGPU SIISelLowering.cpp

Use enum values for src modifiers.
DeltaFile
+8-8llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+8-81 files

LLVM/project 929f55dllvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fadd.ll llvm.amdgcn.reduce.fsub.ll

[AMDGPU] Add wave reduce intrinsics for double types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,115-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+1,102-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+76-19llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2,295-194 files

LLVM/project cd91d31llvm/lib/Transforms/Utils EntryExitInstrumenter.cpp

[EntryExitInstrumenter] Mark CFG as preserved (#178875)

This pass does not change the CFG, so mark all CFG analyses as
preserved, instead of DT in particular. This matches what the NewPM
implementation does.

(This currently has no direct benefit as nearby passes end up
invalidating things anyway.)
DeltaFile
+1-1llvm/lib/Transforms/Utils/EntryExitInstrumenter.cpp
+1-11 files

GhostBSD/ports 5ba2149ports-mgmt/pkg pkg-plist distinfo, ports-mgmt/pkg/files patch-libpkg_pkg__config.c

ports-mgmt/pkg: Sync with FreeBSD
DeltaFile
+0-11ports-mgmt/pkg/files/patch-libpkg_pkg__config.c
+4-3ports-mgmt/pkg/pkg-plist
+3-3ports-mgmt/pkg/distinfo
+2-1ports-mgmt/pkg/Makefile
+9-184 files

LLVM/project 41f453ellvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-int-mulh.ll sve-streaming-mode-fixed-length-fp-rounding.ll

Revert "[DAG] Enable bitcast STLF for Constant/Undef" (#178872)

Reverts llvm/llvm-project#172523

As explained in
https://github.com/llvm/llvm-project/pull/172523#issuecomment-3823234270
(along with reproducer), this causes compiler crashes building
llvm-test-suite for RVV targets.
DeltaFile
+0-71llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
+22-8llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
+3-26llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+14-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
+8-4llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
+0-12llvm/test/CodeGen/RISCV/rvv/stlf.ll
+47-12136 files not shown
+172-18742 files

LLVM/project c88dd45llvm/test/DebugInfo/Generic debug-label-mi.ll, llvm/test/Feature optnone-llc.ll

[AArch64][GlobalISel] Exclude arm64 from failing tests (#178849)

As pointed out by the buildbots &
https://github.com/llvm/llvm-project/pull/174746#issuecomment-3821237987,
some of the tests modified by
https://github.com/llvm/llvm-project/pull/174746 are missing exclusions
for arm64 target triples causing the builds to fail.

I have added these exclusions here.
DeltaFile
+1-1llvm/test/DebugInfo/Generic/debug-label-mi.ll
+1-1llvm/test/Feature/optnone-llc.ll
+2-22 files

OpenBSD/ports HGpl9PZwww/vaultwarden-web Makefile distinfo, www/vaultwarden-web/pkg PLIST

   Update to vaultwarden-web-2025.12.1.3

   Changes:
   https://github.com/dani-garcia/bw_web_builds/compare/v2025.7.0...v2025.12.1+build.3
VersionDeltaFile
1.20.2.1+74-67www/vaultwarden-web/pkg/PLIST
1.22.2.1+4-3www/vaultwarden-web/Makefile
1.20.2.1+2-2www/vaultwarden-web/distinfo
+80-723 files

LLVM/project fbffdaamlir/include/mlir/Dialect/GPU/IR CompilationInterfaces.h, mlir/lib/Target/LLVM/NVVM Target.cpp

[MLIR][GPU] Update serializeToObject to use SerializedObject wrapper and include ISA compiler logs (#176697)

This PR makes the compilation log from ISA compiler available to users
by returning it as part of the `gpu::ObjectAttr` properties, following
the existing pattern like `LLVMIRToISATimeInMs`.

Currently, the compiler log (which contains useful information such as
spill statistics when --verbose is passed) is only accessible in debug
builds via `LLVM_DEBUG`. However, there are good reasons to make this
information available in release builds as well:

1. Both `ptxas` and `libnvptxcompiler` are publicly available
tools/libraries distributed with the CUDA Toolkit. The `--verbose` flag
and its output are documented public features, not internal debug
information.
2. The verbose output provides valuable insights for users.

A new `SerializedObject` class is used to carry the metadata alongside
the binary when returning from `serializeObject`.
DeltaFile
+57-28mlir/lib/Target/LLVM/NVVM/Target.cpp
+22-18mlir/unittests/Target/LLVM/SerializeROCDLTarget.cpp
+21-18mlir/unittests/Target/LLVM/SerializeToLLVMBitcode.cpp
+18-14mlir/unittests/Target/LLVM/SerializeNVVMTarget.cpp
+12-8mlir/lib/Target/LLVM/ROCDL/Target.cpp
+19-0mlir/include/mlir/Dialect/GPU/IR/CompilationInterfaces.h
+149-868 files not shown
+191-10114 files

LLVM/project e8f70c9llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-int-mulh.ll sve-streaming-mode-fixed-length-fp-rounding.ll

Revert "[DAG] Enable bitcast STLF for Constant/Undef (#172523)"

This reverts commit d3c64633c3a17edd370280eb09668c8c3927383e.
DeltaFile
+0-71llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
+22-8llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
+3-26llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+14-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
+8-4llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
+0-12llvm/test/CodeGen/AArch64/sve-stlf.ll
+47-12136 files not shown
+172-18742 files

OpenBSD/ports 1kxeIfjaudio/ocp distinfo Makefile

   Update ocp to 3.1.2.
VersionDeltaFile
1.21+2-2audio/ocp/distinfo
1.44+1-1audio/ocp/Makefile
+3-32 files

OPNSense/core c264c90src/opnsense/mvc/app/library/OPNsense/Core ConfigMaintenance.php, src/www interfaces.php

interfaces: check dhcpdv6.enabled for -1 and add legacy config sections

PR: https://forum.opnsense.org/index.php?topic=50580.0
DeltaFile
+2-2src/www/interfaces.php
+2-0src/opnsense/mvc/app/library/OPNsense/Core/ConfigMaintenance.php
+4-22 files

LLVM/project 1ce7a81compiler-rt/include/fuzzer FuzzedDataProvider.h

fuzzer: modernize FuzzedDataProvider conversions (#177794)

This change modernizes FuzzedDataProvider.h now that C++17+ is standard
in LLVM.
Replace the runtime if with if constexpr in ConvertUnsignedToSigned
Make the unsigned/signed comparison explicit by casting TS::max() to TU
DeltaFile
+3-3compiler-rt/include/fuzzer/FuzzedDataProvider.h
+3-31 files

NetBSD/pkgsrc QQBTB1ldoc CHANGES-2026

   Updated sysutils/gam to 7.32.06
VersionDeltaFile
1.753+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc DVUEmBdsysutils/gam distinfo Makefile

   gam: update to 7.32.06

   Changes since 7.29.01:

   7.32.06

   Added options to gam <UserTypeEntity> copy drivefile ... copysubfiles to limit copying to files whose modifiedTime meets specified requirements.

       start|starttime <Date>|<Time> - If specified, modifiedTime must be >= the value
       end|endtime <Date>|<Time> - If specified, modifiedTime must be <= the value
       range <Date>|<Time> <Date>|<Time> - first value <= modifiedTime <= second value

   7.32.05

   Fixed bug in gam <UserTypeEntity> print messages|threads ... headers <SMTPHeaderList> where headers other than those specified in <SMTPHeaderList> were displayed.

   Updated gam info users <UserTypeEntity> to display the following data when the Licensing API does not return data due to quota limits. Previously, no License data was displayed and there was no way to know if it was omitted due to API quota limits vs the user has no license?

     Licenses: (1)

    [210 lines not shown]
VersionDeltaFile
1.12+4-4sysutils/gam/distinfo
1.20+2-2sysutils/gam/Makefile
+6-62 files

LLVM/project 10afcd4flang/test/Lower derived-pointer-components.f90 do_loop.f90

[flang][NFC] Converted five tests from old lowering to new lowering (part 12) (#178831)

Tests converted from test/Lower: derived-pointer-components.f90,
derived-type-finalization.f90, derived-types.f90, do_loop.f90,
do_loop_unstructured.f90
DeltaFile
+376-378flang/test/Lower/derived-pointer-components.f90
+83-67flang/test/Lower/do_loop.f90
+65-53flang/test/Lower/derived-types.f90
+44-63flang/test/Lower/derived-type-finalization.f90
+29-23flang/test/Lower/do_loop_unstructured.f90
+597-5845 files

OpenBSD/src BS3tpPsusr.bin/file/magdir fonts

   file(1): add support for Web Open Font Format (WOFF) detection.

   From NetBSD.

   OK sthen@
VersionDeltaFile
1.6+28-1usr.bin/file/magdir/fonts
+28-11 files