LLVM/project c630b09clang/lib/CIR/CodeGen CIRGenExprScalar.cpp

[CIR][NFC] Remove NYI checks in ternary with cleanup (#186870)

We added those checks when CleanupScopeOp is used to emit an error
message in this edge case until we fix it. Now it's already fixed, and
we don't need to keep the NYI
DeltaFile
+0-8clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+0-81 files

FreeNAS/freenas 4b3f8e0src/middlewared/middlewared/plugins/fc fc.py, src/middlewared/middlewared/plugins/rdma rdma.py

cli_private = True
DeltaFile
+3-0src/middlewared/middlewared/plugins/rdma/rdma.py
+1-0src/middlewared/middlewared/plugins/fc/fc.py
+4-02 files

LLVM/project 03f488allvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp, llvm/test/MC/AArch64 global-tagging.ll

[AsmPrinter][MTE] Support memtag-globals for all AArch64 targets (#187065)

This change ensures that all AArch64 targets can use memtag globals, not
only Android.
DeltaFile
+7-3llvm/test/MC/AArch64/global-tagging.ll
+2-2llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+9-52 files

FreeNAS/freenas 0eb3f6dsrc/middlewared/middlewared/plugins/zpool get_zpool_disks_impl.py

NAS-140344 / 26.0.0-BETA.1 / fix pool.get_disks for nested vdev types (by yocalebo) (#18500)

Original PR: https://github.com/truenas/middleware/pull/18499

Co-authored-by: caleb <yocalebo at gmail.com>
DeltaFile
+18-8src/middlewared/middlewared/plugins/zpool/get_zpool_disks_impl.py
+18-81 files

FreeNAS/freenas 53c7020src/middlewared/middlewared/plugins/zpool get_zpool_disks_impl.py

NAS-140344 / 26.0.0-BETA.2 / fix pool.get_disks for nested vdev types (by yocalebo) (#18501)

Original PR: https://github.com/truenas/middleware/pull/18499

Co-authored-by: caleb <yocalebo at gmail.com>
DeltaFile
+18-8src/middlewared/middlewared/plugins/zpool/get_zpool_disks_impl.py
+18-81 files

FreeNAS/freenas 4af2b81src/middlewared/middlewared/plugins/zpool get_zpool_disks_impl.py

NAS-140344 / 27.0.0-BETA.1 / fix pool.get_disks for nested vdev types (#18499)
DeltaFile
+18-8src/middlewared/middlewared/plugins/zpool/get_zpool_disks_impl.py
+18-81 files

FreeNAS/freenas bdf80adsrc/middlewared/middlewared/plugins/enclosure_ enclosure2.py, src/middlewared/middlewared/plugins/fc fc.py

expose several other public methods in the API docs
DeltaFile
+6-2src/middlewared/middlewared/plugins/enclosure_/enclosure2.py
+5-2src/middlewared/middlewared/plugins/webui/enclosure.py
+5-2src/middlewared/middlewared/plugins/fc/fc.py
+2-2src/middlewared/middlewared/plugins/webui/main_dashboard.py
+0-3src/middlewared/middlewared/plugins/rdma/rdma.py
+0-1src/middlewared/middlewared/plugins/webui/crypto.py
+18-126 files

LLVM/project da47edellvm/include/llvm/CodeGen RegisterScavenging.h, llvm/lib/Target/AArch64 AArch64FrameLowering.cpp

[AArch64] Fix register scavenger crash when merging MTE stack tags (#186934)

When `-sanitize=memtag-stack` is enabled, `TagStoreEdit::emitLoop`
optimizes contiguous ST2Gi instructions into an STGloop. Because this
runs during PEI (post-register allocation), it spawns two new virtual
registers: BaseReg and SizeReg.

Under high register pressure (e.g., Swift async continuation thunks
where almost all registers are kept live), the Register Scavenger must
rely on emergency spill slots to assign physical registers to BaseReg
and SizeReg.

Previously, the compiler assumed at most one emergency spill slot was
needed. If PEI found an unused Callee-Saved Register (`ExtraCSSpill`),
it bypassed allocating an emergency slot entirely. If no CSRs were free,
it allocated exactly one slot. Because STGloop requires TWO scratch
locations, the scavenger would crash trying to fulfill the second
allocation.


    [11 lines not shown]
DeltaFile
+551-0llvm/test/CodeGen/AArch64/memtag-stg-loop-reg-pressure.mir
+28-0llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+2-0llvm/include/llvm/CodeGen/RegisterScavenging.h
+581-03 files

LLVM/project 7f1be73llvm/include/llvm/Remarks RemarkStreamer.h, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+5-6llvm/lib/Remarks/RemarkStreamer.cpp
+5-5llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+3-3llvm/test/CodeGen/X86/remarks-section.ll
+3-1llvm/include/llvm/Remarks/RemarkStreamer.h
+16-154 files

FreeBSD/src 1acf507release/tools ec2.conf

EC2: Don't use unicode in boot loader

The boot loader menu is disabled by default in EC2, but if it is ever
turned on, the default (unicode) output breaks EC2's web interface to
the serial console.

Set loader_menu_frame="ascii" instead.

MFC after:      3 days
Sponsored by:   Amazon

(cherry picked from commit 277830b4d3ae9999c80bf915b5491850e91c6516)
(cherry picked from commit 251907ca480eff7f6177f52959b71a6cfce45579)
DeltaFile
+4-1release/tools/ec2.conf
+4-11 files

FreeBSD/src c25839csys/kern subr_intr.c

intrng: Shuffle unhandled interrupts too

When interrupt vectors are first allocated, they get assigned to
CPU #0; at SI_SUB_SMP / SI_ORDER_SECOND (aka once we have multiple
CPUs), the intr_irq_shuffle SYSINIT clears their CPU sets with the
effect of forcing them to be assigned to new CPUs later.

In case where interrupt vectors were allocated *but not yet bound*
this code did not run, with the effect that those interrupts would
remain pinned to CPU #0 forever.  This affected the ena(4) driver,
which allocates interrupts for I/O when the device is attached but
doesn't set them up until the interface is brought up much later in
the boot process (and, crucially, long after intr_irq_shuffle runs).

Adjust intr_irq_shuffle to clear the CPU set for an interrupt source
even if it currently has no handlers, so that it will be properly
assigned to a CPU when it is used later.

Reviewed by:    andrew, mhorne

    [5 lines not shown]
DeltaFile
+13-1sys/kern/subr_intr.c
+13-11 files

FreeNAS/freenas 1befda3src/middlewared/middlewared/api/v26_0_0 interface.py, src/middlewared/middlewared/plugins network.py

touch up

(cherry picked from commit 487333c56bf1e83a61bc804e41ddd100a67e1070)
DeltaFile
+13-9src/middlewared/middlewared/plugins/network.py
+2-1src/middlewared/middlewared/api/v26_0_0/interface.py
+15-102 files

FreeNAS/freenas 8cf1bc2src/middlewared/middlewared/api/v26_0_0 interface.py, src/middlewared/middlewared/plugins network.py

draft

(cherry picked from commit d16888374ed500ee562e9b625ac3ff3cd00f7206)
DeltaFile
+22-2src/middlewared/middlewared/plugins/network.py
+12-1src/middlewared/middlewared/api/v26_0_0/interface.py
+34-32 files

FreeNAS/freenas 6a2f17asrc/middlewared/middlewared/plugins network.py

remove unnecessary get_instance call

(cherry picked from commit cb2cfcbea07987d48f55a0c59a5e869b90e5c6d1)
DeltaFile
+3-6src/middlewared/middlewared/plugins/network.py
+3-61 files

FreeNAS/freenas cf35691src/middlewared/middlewared/alembic/versions/26.0 2026-02-17_16-20_add_interface_fec_mode.py, src/middlewared/middlewared/api/v26_0_0 interface.py

begin

(cherry picked from commit 67ffecc7099df7cdf4068f9bd1e14ff93663855b)
DeltaFile
+26-0src/middlewared/middlewared/alembic/versions/26.0/2026-02-17_16-20_add_interface_fec_mode.py
+14-0src/middlewared/middlewared/api/v26_0_0/interface.py
+10-0src/middlewared/middlewared/plugins/interface/addresses.py
+7-0src/middlewared/middlewared/plugins/network.py
+57-04 files

FreeNAS/freenas feae449src/middlewared/middlewared/alembic/versions/26.0 2026-03-11_18-44_add_interface_fec_mode.py, src/middlewared/middlewared/alembic/versions/27.0 2026-03-17_14-37_merge.py

NAS-139477 / 27.0.0-BETA.1 / Add FEC mode configuration to network interfaces (#18447)

### Summary
                
Exposes Forward Error Correction (FEC) mode as a configurable property
on physical network interfaces. Operators can query which FEC modes a
NIC supports, set a preferred mode, and observe the active mode the
hardware is using.

Feature requested by support for the purpose of fixing interface
connectivity when FEC negotiation with the switch fails. This provides
the customer with a cleaner way to correct the issue than setting up a
custom boot-time script.

### API usage

Check what modes the NIC supports
```
midclt call interface.available_fec_modes eno8np2

    [19 lines not shown]
DeltaFile
+59-2src/middlewared/middlewared/api/v27_0_0/interface.py
+55-1src/middlewared/middlewared/api/v26_0_0/interface.py
+40-1src/middlewared/middlewared/plugins/network.py
+26-0src/middlewared/middlewared/alembic/versions/26.0/2026-03-11_18-44_add_interface_fec_mode.py
+24-0src/middlewared/middlewared/alembic/versions/27.0/2026-03-17_14-37_merge.py
+10-0src/middlewared/middlewared/plugins/interface/addresses.py
+214-46 files

FreeBSD/src 660a79erelease/tools ec2.conf

EC2: Don't use unicode in boot loader

The boot loader menu is disabled by default in EC2, but if it is ever
turned on, the default (unicode) output breaks EC2's web interface to
the serial console.

Set loader_menu_frame="ascii" instead.

MFC after:      3 days
Sponsored by:   Amazon

(cherry picked from commit 277830b4d3ae9999c80bf915b5491850e91c6516)
(cherry picked from commit 251907ca480eff7f6177f52959b71a6cfce45579)
DeltaFile
+4-1release/tools/ec2.conf
+4-11 files

FreeBSD/src b109809sys/kern subr_intr.c

intrng: Shuffle unhandled interrupts too

When interrupt vectors are first allocated, they get assigned to
CPU #0; at SI_SUB_SMP / SI_ORDER_SECOND (aka once we have multiple
CPUs), the intr_irq_shuffle SYSINIT clears their CPU sets with the
effect of forcing them to be assigned to new CPUs later.

In case where interrupt vectors were allocated *but not yet bound*
this code did not run, with the effect that those interrupts would
remain pinned to CPU #0 forever.  This affected the ena(4) driver,
which allocates interrupts for I/O when the device is attached but
doesn't set them up until the interface is brought up much later in
the boot process (and, crucially, long after intr_irq_shuffle runs).

Adjust intr_irq_shuffle to clear the CPU set for an interrupt source
even if it currently has no handlers, so that it will be properly
assigned to a CPU when it is used later.

Reviewed by:    andrew, mhorne

    [5 lines not shown]
DeltaFile
+13-1sys/kern/subr_intr.c
+13-11 files

LLVM/project 2408c2blibclc/clc/lib/generic/math clc_nextdown.inc clc_nextup.inc

libclc: Fix nextafter with -cl-denorms-are-zero

Follow the suggested behavior of returning +/-FLT_MIN for logical
zeros.
DeltaFile
+5-2libclc/clc/lib/generic/math/clc_nextdown.inc
+4-0libclc/clc/lib/generic/math/clc_nextup.inc
+2-0libclc/clc/lib/generic/math/clc_nextafter.cl
+1-1libclc/clc/lib/generic/math/clc_nextafter.inc
+1-0libclc/clc/lib/generic/math/clc_nextdown.cl
+1-0libclc/clc/lib/generic/math/clc_nextup.cl
+14-36 files

OpenZFS/src 3ee08abmodule/os/linux/zfs zpl_super.c

linux/super: flatten zpl_fill_super into zpl_get_tree

Target of opportunity; with no other callers, there's no need for it to
be a static function.

Sponsored-by: TrueNAS
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Rob Norris <rob.norris at truenas.com>
Closes #18339
DeltaFile
+6-17module/os/linux/zfs/zpl_super.c
+6-171 files

OpenZFS/src 96a0b20module/os/linux/zfs zpl_super.c

linux/super: flatten zpl_mount_impl into zpl_get_tree

Target of opportunity; with no other callers, there's no need for it to
be a static function.

Sponsored-by: TrueNAS
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Rob Norris <rob.norris at truenas.com>
Closes #18339
DeltaFile
+69-75module/os/linux/zfs/zpl_super.c
+69-751 files

OpenZFS/src 5ebb9ffmodule/os/linux/zfs zpl_super.c

linux/super: flatten mount/remount into get_tree/reconfigure

With the old API gone, there's no need to massage new-style calls into
its shape and call another function; we can just make those handlers
work directly.

Sponsored-by: TrueNAS
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Rob Norris <rob.norris at truenas.com>
Closes #18339
DeltaFile
+17-40module/os/linux/zfs/zpl_super.c
+17-401 files

OpenZFS/src f828aebmodule/os/linux/zfs zpl_super.c

linux/super: remove support for old mount API

Removing the HAVE_FS_CONTEXT gates and anything that would be used if it
wasn't set.

Sponsored-by: TrueNAS
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Rob Norris <rob.norris at truenas.com>
Closes #18339
DeltaFile
+0-11module/os/linux/zfs/zpl_super.c
+0-111 files

OpenZFS/src 188888aconfig kernel-fs-context.m4

config: refuse to build without fs_context

Sponsored-by: TrueNAS
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Rob Norris <rob.norris at truenas.com>
Closes #18339
DeltaFile
+3-0config/kernel-fs-context.m4
+3-01 files

LLVM/project ea2ac04libclc/clc/include/clc/math clc_flush_if_daz.h clc_canonicalize.h, libclc/clc/lib/generic/math clc_flush_if_daz.inc clc_flush_if_daz.cl

libclc: Add canonicalize utility functions

This is mostly to work around spirv's canonicalize still
being broken.
DeltaFile
+43-0libclc/clc/lib/generic/math/clc_flush_if_daz.inc
+19-0libclc/clc/include/clc/math/clc_flush_if_daz.h
+19-0libclc/clc/include/clc/math/clc_canonicalize.h
+16-0libclc/clc/lib/generic/math/clc_flush_if_daz.cl
+15-0libclc/clc/lib/generic/math/clc_canonicalize.cl
+0-10libclc/clc/include/clc/math/math.h
+112-104 files not shown
+121-1510 files

LLVM/project 08848cdlibclc/clc/include/clc/math gentype.inc clc_subnormal_config.h, libclc/clc/lib/generic subnormal_config.cl

libclc: Really implement denormal config checks

These should be implementable by checking the behavior of
the canonicalize intrinsic. Hack around spirv still failing
on canonicalize by overriding and assuming DAZ for float.
DeltaFile
+24-3libclc/clc/lib/generic/subnormal_config.cl
+19-0libclc/clc/lib/spirv/subnormal_config.cl
+7-1libclc/clc/include/clc/math/gentype.inc
+3-0libclc/clc/include/clc/math/clc_subnormal_config.h
+1-0libclc/clc/lib/spirv/CMakeLists.txt
+54-45 files

FreeBSD/src cc66722tests/sys/netinet raw.c

tests/netinet/raw: fix ssize_t printf(3) format

Fixes:  c1481c9f4a425db7295332be87f837bfb7d127df
DeltaFile
+1-1tests/sys/netinet/raw.c
+1-11 files

LLVM/project eabcfceclang/lib/Headers/hlsl hlsl_alias_intrinsics.h, clang/test/CodeGenHLSL/builtins QuadReadAcrossX.hlsl

[HLSL][DXIL][SPIRV] QuadReadAcrossX intrinsic support (#184360)

This PR adds QuadReadAcrossX intrinsic support in HLSL with codegen for
both DirectX and SPIRV backends. Resolves
https://github.com/llvm/llvm-project/issues/99175.

- [x] Implement QuadReadAcrossX clang builtin
- [x]  Link QuadReadAcrossX clang builtin with hlsl_intrinsics.h
- [x] Add sema checks for QuadReadAcrossX to
CheckHLSLBuiltinFunctionCall in SemaChecking.cpp
- [x] Add codegen for QuadReadAcrossX to EmitHLSLBuiltinExpr in
CGBuiltin.cpp
- [x] Add codegen tests to
clang/test/CodeGenHLSL/builtins/QuadReadAcrossX.hlsl
- [x] Add sema tests to
clang/test/SemaHLSL/BuiltIns/QuadReadAcrossX-errors.hlsl
- [x] Create the int_dx_QuadReadAcrossX intrinsic in
IntrinsicsDirectX.td
- [x] Create the DXILOpMapping of int_dx_QuadReadAcrossX to 123 in

    [8 lines not shown]
DeltaFile
+99-0clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+87-0llvm/test/CodeGen/DirectX/QuadReadAcrossX.ll
+46-0clang/test/CodeGenHLSL/builtins/QuadReadAcrossX.hlsl
+44-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/QuadReadAcrossX.ll
+30-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+28-0clang/test/SemaHLSL/BuiltIns/QuadReadAcrossX-errors.hlsl
+334-012 files not shown
+401-218 files

LLVM/project 17158b2llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

[InstCombine] Fix comment in SimplifyDemandedUseBits (NFC) (#187126)

Fix the values in the truth table comment for the combine

  add iN (sext i1 X), (sext i1 Y) --> sext (X | Y) to iN
DeltaFile
+2-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+2-21 files

LLVM/project e9799e5lldb/test/API/tools/lldb-dap/variables TestDAP_variables.py main.cpp, lldb/tools/lldb-dap Variables.cpp ProtocolUtils.cpp

[lldb-dap] Improve support for variables with anonymous fields and types (#186482)

While looking at the '[raw]' value of a std::vector I noticed we didn't
handle the anonymous inner struct very well. The 'evaluateName' was
incorrect (e.g. the evaluateName would return `<var>.` for the anonymous
struct).

This improves support for variables with anonymous fields and anonymous
types.

* Changed the name of anonymous fields from `<null>` to `(anonymous)`,
which matches other tooling like clangd's representation and how types
are presented if the field is not defined.
* Adjusts variables to not return an 'evaluateName' for anonymous
fields.
* Adjusted '[raw]' values to be marked as 'internal' which deemphasizes
them in the UI.

While working in this area, I also consolidated some helpers that are

    [10 lines not shown]
DeltaFile
+194-109lldb/tools/lldb-dap/Variables.cpp
+153-24lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
+0-73lldb/tools/lldb-dap/ProtocolUtils.cpp
+18-25lldb/tools/lldb-dap/Variables.h
+42-1lldb/test/API/tools/lldb-dap/variables/main.cpp
+0-42lldb/tools/lldb-dap/ProtocolUtils.h
+407-2746 files not shown
+440-29812 files