LLVM/project 3ad91ceclang/lib/CIR/CodeGen CIRGenModule.cpp

crash on sycl tempAlloca
DeltaFile
+1-1clang/lib/CIR/CodeGen/CIRGenModule.cpp
+1-11 files

LLVM/project a88714blld/ELF/Arch LoongArch.cpp RISCV.cpp, lld/test/ELF loongarch-relocatable-align.s riscv-relocatable-align.s

[ELF] -r: Don't let a weaker offset-0 R_RISCV_ALIGN suppress ALIGN synthesis (#198147)

PR #151639 skipped synthesizing the section-start R_RISCV_ALIGN whenever
any R_RISCV_ALIGN existed at offset 0, regardless of its alignment. This
works with newer LLVM integrated assembler (#150816).

However, older MC and GNU Assembler as of today
(https://sourceware.org/bugzilla/show_bug.cgi?id=33236) can carry a weak
offset-0 R_RISCV_ALIGN (addend 2 => align 4) while its real alignment
requirement comes from a `.option norelax` .balign, which emits no
relocation.

Fix the condition to not suppress synthesis.

Link: https://sourceware.org/bugzilla/show_bug.cgi?id=33236#c4
DeltaFile
+25-0lld/test/ELF/loongarch-relocatable-align.s
+24-0lld/test/ELF/riscv-relocatable-align.s
+12-5lld/ELF/Arch/LoongArch.cpp
+12-5lld/ELF/Arch/RISCV.cpp
+73-104 files

LLVM/project 87fb6b5lldb/source/Plugins/Platform/WebAssembly PlatformWebInspectorWasm.cpp

[lldb] Recheck connection state in webinspector-wasm EnsureConnected (#198701)

m_remote_platform_sp can be non-null while the remote is disconnected
(PlatformWasm::ConnectRemote installs the pointer before the connect
call). Also check IsConnected() so a prior failed connect doesn't make
EnsureConnected falsely report success.
DeltaFile
+1-1lldb/source/Plugins/Platform/WebAssembly/PlatformWebInspectorWasm.cpp
+1-11 files

FreeBSD/ports eed3a46databases/timescaledb distinfo Makefile

databases/timescaledb: Update to 2.27.1
DeltaFile
+3-3databases/timescaledb/distinfo
+1-1databases/timescaledb/Makefile
+2-0databases/timescaledb/pkg-plist
+6-43 files

LLVM/project 6113e16clang-tools-extra/clangd/test non-existent.test, clang/lib/Parse Parser.cpp

[clang] Don't cutoff parsing when load C++ named module failed (#187858)

Since https://github.com/llvm/llvm-project/pull/173130, clang convert
module name pp-token sequence into a annot_module_name token for C++20
module/import directive. This PR follows the changes and correct the
module name handling in clangd.

This PR avoid parsing cutoff when hit an C++ named module loading.

Fixes https://github.com/llvm/llvm-project/issues/181358.

Signed-off-by: yronglin <yronglin777 at gmail.com>
DeltaFile
+82-0clang-tools-extra/clangd/test/non-existent.test
+12-0clang/test/Modules/cxx20-fatal-module-loader-error.cpp
+7-1clang/lib/Parse/Parser.cpp
+101-13 files

LLVM/project d691b3dclang/lib/Tooling/Syntax Tokens.cpp, clang/unittests/Tooling/Syntax TokensTest.cpp

[clang][tooling] Handle C++20 annot_module_name in syntax tokens (#198544)

The token collector will ignore all the annotation tokens, but IIUC, the
annot_module_name shoulde not be ignored.

Signed-off-by: yronglin <yronglin777 at gmail.com>
DeltaFile
+31-3clang/unittests/Tooling/Syntax/TokensTest.cpp
+11-2clang/lib/Tooling/Syntax/Tokens.cpp
+42-52 files

LLVM/project f7fd42bllvm/test/tools/dsymutil/X86 modules.m

[dsymutil] Update modules test for divergence between the two linkers (#198661)

The parallel linker keeps DW_AT_GNU_dwo_id on linked CUs while the
classic linker drops it. Gate the four `CHECK-NOT: DW_AT_GNU_dwo_id`
assertions to a CLASSIC-only prefix so the test reflects the actual,
intended behavior of each linker.
DeltaFile
+9-10llvm/test/tools/dsymutil/X86/modules.m
+9-101 files

NetBSD/pkgsrc hLfbWAwdoc CHANGES-2026

   doc: Updated devel/R-lazyeval to 0.2.3
VersionDeltaFile
1.3136+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc P6Y9dJCdevel/R-lazyeval Makefile distinfo

   (devel/R-lazyeval) Updated 0.2.2 to 0.2.3

   # lazyeval 0.2.3 (Time stamp of NEWS.md is 2026/04/03)

   * Fixes for CRAN checks. The new implementation is now compliant with
     the public C API of R and might differ from the historical one in
     subtle ways.
VersionDeltaFile
1.6+9-2devel/R-lazyeval/Makefile
1.5+4-4devel/R-lazyeval/distinfo
+13-62 files

NetBSD/pkgsrc To2Vmzbdoc CHANGES-2026

   doc: Updated devel/ast-grep to 0.42.3
VersionDeltaFile
1.3135+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc lcKlVPOdevel/ast-grep distinfo cargo-depends.mk

   devel/ast-grep: update to 0.42.3

    - feat: support nth-last-child esquery #2631
    - chore(deps): update rust crate dashmap to v6.2.1 #2645
    - chore(deps): update dependency oxlint to v1.65.0 #2635
    - chore(deps): update rust crate napi-derive to v3.5.6 #2642
    - chore(deps): update rust crate napi-build to v2.3.2 #2641
    - chore(deps): update rust crate napi to v3.9.0 #2643
    - chore(deps): update dependency @ast-grep/napi to v0.42.2 #2630
    - fix: fix windows installation 4021ae0
VersionDeltaFile
1.82+22-22devel/ast-grep/distinfo
1.77+6-6devel/ast-grep/cargo-depends.mk
1.82+2-2devel/ast-grep/Makefile
+30-303 files

LLVM/project 97d8931llvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c
DeltaFile
+67-67llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+33-0llvm/lib/MC/MCDwarf.cpp
+15-15llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+10-0llvm/lib/CodeGen/MachineFunction.cpp
+4-4llvm/test/CodeGen/AMDGPU/debug-frame.ll
+4-0llvm/include/llvm/CodeGen/MachineFunction.h
+133-865 files not shown
+143-9011 files

LLVM/project 20dec1ellvm/lib/Target/AMDGPU SIFrameLowering.cpp SIMachineFunctionInfo.h, llvm/test/CodeGen/AMDGPU amdgpu-spill-cfi-saved-regs.ll

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
DeltaFile
+2,926-0llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
+12-0llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+10-0llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+9-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+2,959-05 files

LLVM/project fff1235llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll gfx-callable-argument-types.ll

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+3,568-2,598llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,912-1,913llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+2,700-12llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+631-631llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+505-510llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+394-399llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+9,710-6,063108 files not shown
+14,825-9,526114 files

LLVM/project 93f5fe8llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll

[AMDGPU] Use register pair for PC spill

Change-Id: Ibedeef926f7ff235a06de65a83087c151f66a416
DeltaFile
+4,331-4,331llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,742-1,740llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+1,562-1,560llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,462-1,460llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+1,238-1,236llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+1,030-1,028llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+11,365-11,35589 files not shown
+18,153-18,04495 files

LLVM/project 0d844f1

[Clang] Default to async unwind tables for amdgcn

To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.

There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.

Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
DeltaFile
+0-00 files

LLVM/project 5ae601fllvm/lib/Target/AMDGPU SIFrameLowering.cpp, llvm/test/CodeGen/AMDGPU debug-frame.ll eliminate-frame-index-v-add-u32.mir

[AMDGPU] Emit entry function Dwarf CFI

Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.

Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+1,405-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+204-12llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
+134-6llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
+114-10llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
+42-5llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+34-0llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
+1,933-3322 files not shown
+2,044-5028 files

LLVM/project b01748fllvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir

[AMDGPU] Implement CFI for non-kernel functions

This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.

Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+2,136-0llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
+1,671-1llvm/test/CodeGen/AMDGPU/debug-frame.ll
+16,779-16993 files not shown
+22,925-1,04999 files

LLVM/project 77a4ba0

[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU

While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).

Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
DeltaFile
+0-00 files

LLVM/project 2dd3cef

[MIR] Error on signed integer in getUnsigned

Previously we effectively took the absolute value of the APSInt, instead
diagnose the unexpected negative value.

Change-Id: I4efe961e7b29fdf1d5f97df12f8139aac12c9219
DeltaFile
+0-00 files

FreeBSD/src 84f7ee3contrib/expat Changes, contrib/expat/lib xmlparse.c

contrib/expat: import expat 2.8.1

Changes: https://github.com/libexpat/libexpat/blob/R_2_8_1/expat/Changes

Security:       CVE-2026-45186

(cherry picked from commit 9cc9b8b372842b9a941d235c5e9949a214e5284f)
DeltaFile
+295-15contrib/expat/tests/basic_tests.c
+41-42contrib/expat/xmlwf/xmlwf.c
+30-6contrib/expat/lib/xmlparse.c
+19-15contrib/expat/tests/handlers.c
+26-0contrib/expat/Changes
+5-5contrib/expat/tests/minicheck.c
+416-8316 files not shown
+450-11122 files

LLVM/project 45f519bmlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

Remove unrelated empty line
DeltaFile
+0-1mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+0-11 files

FreeBSD/src 659a27econtrib/expat Changes, contrib/expat/lib xmlparse.c

contrib/expat: import expat 2.8.1

Changes: https://github.com/libexpat/libexpat/blob/R_2_8_1/expat/Changes

Security:       CVE-2026-45186

(cherry picked from commit 9cc9b8b372842b9a941d235c5e9949a214e5284f)
DeltaFile
+295-15contrib/expat/tests/basic_tests.c
+41-42contrib/expat/xmlwf/xmlwf.c
+30-6contrib/expat/lib/xmlparse.c
+19-15contrib/expat/tests/handlers.c
+26-0contrib/expat/Changes
+5-5contrib/expat/tests/minicheck.c
+416-8316 files not shown
+450-11122 files

LLVM/project 52998b1clang/lib/Parse ParseStmt.cpp

format
DeltaFile
+2-2clang/lib/Parse/ParseStmt.cpp
+2-21 files

LLVM/project 403880eclang/docs LanguageExtensions.rst, clang/include/clang/Basic DiagnosticParseKinds.td

rethink parsing
DeltaFile
+10-27clang/lib/Parse/ParseExprCXX.cpp
+22-12clang/lib/Parse/ParseStmt.cpp
+6-6clang/include/clang/Parse/Parser.h
+3-4clang/test/C/C2y/n3267.c
+6-0clang/include/clang/Basic/DiagnosticParseKinds.td
+1-0clang/docs/LanguageExtensions.rst
+48-496 files

LLVM/project 69e298dllvm/lib/Target/DirectX DXILPrettyPrinter.cpp

Reduce use of auto.
DeltaFile
+9-7llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
+9-71 files

FreeBSD/src 3185542sys/dev/dpaa if_memac_fdt.c

dpaa: Restore Semihalf license header

This is a "new" file, but is mostly copied from if_dtsec_fdt.c, so need to
retain the original license header in addition to the new one.

Reviewed by:    ziaee
Differential Revision:  https://reviews.freebsd.org/D57123
DeltaFile
+25-0sys/dev/dpaa/if_memac_fdt.c
+25-01 files

FreeNAS/freenas f5d34fdtests/api2/zfs_tier test_smoke.py conftest.py

Fix test framework
DeltaFile
+86-67tests/api2/zfs_tier/test_smoke.py
+99-8tests/api2/zfs_tier/conftest.py
+60-41tests/api2/zfs_tier/test_jobs_extended.py
+43-49tests/api2/zfs_tier/test_set_tier_errors.py
+9-33tests/api2/zfs_tier/test_shares.py
+20-15tests/api2/zfs_tier/test_config.py
+317-2133 files not shown
+348-2449 files

FreeBSD/doc 4c396c5website/content/en/releases/14.3R hardware.adoc, website/content/en/releases/14.4R hardware.adoc

hardware: Update pSeries entries

14.4 and 15.1 support little-endian pSeries. 15.0 has boot panic due to
bug in SLOF, but it should be reclassified as QEMU pSeries instead of
IBM.

Reviewed by:            kbowling, ziaee
Signed-off-by:          Minsoo Choo <minsoo at minsoo.io>
Differential Revision:  https://reviews.freebsd.org/D57102
DeltaFile
+3-6website/content/en/releases/14.4R/hardware.adoc
+3-6website/content/en/releases/14.5R/hardware.adoc
+3-6website/content/en/releases/15.1R/hardware.adoc
+4-4website/content/en/releases/15.0R/hardware.adoc
+1-2website/content/en/releases/14.3R/hardware.adoc
+14-245 files

FreeBSD/src cd3cc6esys/conf files, sys/dev/iicbus/sensor w83793g.c

i2c/sensors: Add driver for W83793 hardware monitor

The Winbond/Nuvoton W83793G system monitor chip includes many features
not currently supported by this driver.  The following are currently
supported:

* Up to 6 temperature sensors, 4 of which have 10-bit resolution
  (8.2),two with 8-bit resolution (no decimal component)
* Up to 12 fans
  - Fans 0-4 (1-5 on the datasheet) are always enabled.  The remaining 7
    fans are individually enabled.
* Multiple voltage sensors, reading up to 10 voltage sources.  Sysctls
  are labeled to match the datasheet.
* Chassis open detection.

The W83793AG is a feature-reduced version, which lacks 3 thermal diodes
and 2 voltage monitors.  Since there is no way to tell the difference
between the W83793AG and W83793G programmatically, sensors reported on
the W83793AG will report strange values.

    [18 lines not shown]
DeltaFile
+366-0sys/dev/iicbus/sensor/w83793g.c
+14-0sys/modules/i2c/w83793g/Makefile
+2-1sys/modules/i2c/Makefile
+1-0sys/conf/files
+383-14 files