LLVM/project ee27f89 — mlir/lib/Dialect/SPIRV/Transforms UnifyAliasedResourcePass.cpp, mlir/test/Dialect/SPIRV/Transforms unify-aliased-resource.mlir

[mlir][SPIRV] Handle vector stores when unifying aliased resources (#232185)

I hit this while compiling JAX training code to WebGPU through IREE.

The alias-unification pass can select a smaller vector resource, but its
store conversion currently only handles scalars. Handle vector stores by
splitting them into stores of the canonical vector type, preserving
memory-access flags and alignment.

---------

Signed-off-by: anutosh491 <andersonbhat491 at gmail.com>
DeltaFile
+169-0mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir
+67-6mlir/lib/Dialect/SPIRV/Transforms/UnifyAliasedResourcePass.cpp
+236-62 files

LLVM/project 5420fce — mlir/lib/Conversion/SPIRVToLLVM SPIRVToLLVM.cpp, mlir/test/Conversion/SPIRVToLLVM cl-ops-to-llvm.mlir gl-ops-to-llvm.mlir

[mlir][SPIR-V] Add SPIRVToLLVM conversion for CL.ldexp and GL.Ldexp (#237745)

Vector exponents are not covered since llvm.intr.ldexp accepts only a
scalar integer exponent
DeltaFile
+11-0mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
+7-0mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
+2-0mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+20-03 files

LLVM/project eb85651 — llvm/lib/Target/RISCV RISCVInstrInfoV.td, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.ll

[RISCV] Set DestEEW = EEW1 for VLM_V (#239498)

Assisted-by: Claude
DeltaFile
+14-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+15-12 files

LLVM/project ebc8a1b — llvm/lib/ObjCopy/MachO MachOReader.cpp, llvm/test/tools/llvm-objcopy/MachO arm64-relocs.s

[llvm-objcopy][MachO] Handle ARM64_RELOC_ADDEND for CPU_TYPE_ARM64_32 (#238296)

`ARM64_RELOC_ADDEND` was only handled for arm64, not arm64_32. On
arm64_32 the addend was read as a section index, so `llvm-objcopy` could
crash or write a wrong addend. Handle it for arm64_32 too, and add an
arm64_32 case to `arm64-relocs.s`.

Fixes #238273
I wrote the code and verified everything myself. Claude Code helped me
identify the issue.

Assisted-by: Claude Code
DeltaFile
+4-2llvm/lib/ObjCopy/MachO/MachOReader.cpp
+5-0llvm/test/tools/llvm-objcopy/MachO/arm64-relocs.s
+9-22 files

FreeBSD/ports 20a2a74 — misc/ncnn Makefile pkg-plist

misc/ncnn: fix plist

Reported by:    fallout
DeltaFile
+1-1misc/ncnn/pkg-plist
+1-0misc/ncnn/Makefile
+2-12 files

LLVM/project db52992 — llvm/include/llvm/IR IRBuilder.h

Reapply [IRBuilder] Assert correct offset width for CreatePtrAdd (#239262)

Reapply #238806 without changes after fixing more CreatePtrAdd uses.

-----

Assert that the offset width matches the pointer index width. This is
supposed to become an IR well-formedness requirement when we switch to
ptradd, so we should start asserting it in the builder now.

Helpers like CreatePtrAddWith(Unsigned|Signed)Offset and
CreatePtrAddWith[SZ]ExtOrTrunc can be used to more conveniently create
ptradds with appropriately sized offsets.

Problematic uses of CreatePtrAdd were already adjusted in #238347.
DeltaFile
+4-2llvm/include/llvm/IR/IRBuilder.h
+4-21 files

LLVM/project f6f7322 — llvm/lib/Transforms/Instrumentation MemorySanitizer.cpp

[MemorySanitizer] Consistently use unsigned offsets (NFC) (#239193)

Helper functions for getting origin/shadow etc accepted a mix of int and
unsigned. I believe all of these offsets are non-negative, so use
unsigned everywhere to avoid confusion.
DeltaFile
+13-12llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+13-121 files

LLVM/project e0d0b97 — llvm/test/CodeGen/RISCV rvp-simd-32.ll rvp-simd-64.ll

[RISCV][P-ext] Remove line breaks from argument list of function definition in tests. NFC (#238881)

These line breaks cause the update_llc_test_checks.py script to put the
checks in the middle of the argument list.
DeltaFile
+23-44llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+8-16llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+31-602 files

FreeBSD/ports c9db94f — misc/py-onnxruntime Makefile, misc/py-onnxruntime/files patch-onnxruntime_core_platform_posix_env.cc

misc/py-onnxruntime: Fix loading models with external data

fcntl(F_KINFO) needs kf_structsize set to the size of the structure,
otherwise the kernel refuses the request.  Without it the FreeBSD branch
never resolved the path of an opened file, so no model with weights in an
external data file could be loaded.

Pending upstream as microsoft/onnxruntime#33433.

PR:                     300445
Approved by:            portmgr (blanket)
Sponsored by:           Netzkommune GmbH
DeltaFile
+15-2misc/py-onnxruntime/files/patch-onnxruntime_core_platform_posix_env.cc
+1-0misc/py-onnxruntime/Makefile
+16-22 files

LLVM/project 4c22a9f — mlir/include/mlir/Dialect/AMDGPU/IR AMDGPUDialectDecl.h, mlir/include/mlir/Dialect/Affine/IR AffineDialect.h

[mlir][ODS] Include headers required by generated dialect declarations and definitions (#239215)

Generated dialect declarations and definitions use C++ constructs that
are not declared by any header they include. They therefore relied on
the surrounding source file to include these headers first.

The dialect declarations now include the header declaring the dialect
base class, and the headers declaring `StringAttr` and `Operation` if
the dialect has discardable attributes. The dialect definitions include
`MLIRContext.h` if they load dependent dialects.

Similar to #236155 and #238735 but for the dialect generator.

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+40-0mlir/test/mlir-tblgen/cpp-includes-dialect.td
+20-0mlir/tools/mlir-tblgen/DialectGen.cpp
+0-3mlir/include/mlir/Dialect/LLVMIR/ROCDLDialectDecl.h
+0-2mlir/include/mlir/Dialect/Arith/IR/ArithDialect.h
+0-2mlir/include/mlir/Dialect/Affine/IR/AffineDialect.h
+0-2mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUDialectDecl.h
+60-952 files not shown
+61-7658 files

LLVM/project f133b97 — utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[Bazel] Fixes d1ec07e (#239493)

This fixes d1ec07e0431412a667fecd5c2708f3606b6799a4 (#238966).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=d1ec07e0431412a667fecd5c2708f3606b6799a4

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+2-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+2-01 files

LLVM/project 5c9aa46 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll amdgcn.bitcast.832bit.ll

[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+89,147-91,827llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,378-26,402llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,311-9,381llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,998-9,209llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+8,016-8,194llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+7,335-7,432llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+148,185-152,44513,886 files not shown
+699,970-465,39813,892 files

FreeBSD/ports bec4e18 — www/py-flask-oauthlib Makefile

www/py-flask-oauthlib: mark broken and set to expire

the port is broken at runtime with current version of werkzeug in the tree.
Last release of it was 3 years ago and upstream author recommends to switch
to switch to Authlib (security/py-authlib).

PR:             299797
Reported by:    Patrick Crandol <patrick at crandol.com>
DeltaFile
+5-1www/py-flask-oauthlib/Makefile
+5-11 files

LLVM/project 47d998a — llvm/lib/Target/LoongArch LoongArchRegisterInfo.cpp, llvm/test/CodeGen/LoongArch/lasx xvldrepl-frame-index.ll

[LoongArch] Fix misaligned frame-index offset for vldrepl.{h,w,d}

eliminateFrameIndex did not check that the final offset is a multiple of
the access size for [X]VLDREPL_{H,W,D}, so a byte-aligned stack object
could produce an unencodable immediate. Materialize the address in a
scratch register in that case, as is already done for [X]VSTELM_*.

Assisted-by: LLM
DeltaFile
+12-0llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
+6-3llvm/test/CodeGen/LoongArch/lsx/vldrepl-frame-index.ll
+6-3llvm/test/CodeGen/LoongArch/lasx/xvldrepl-frame-index.ll
+24-63 files

LLVM/project e641369 — llvm/test/CodeGen/LoongArch/lasx xvldrepl-frame-index.ll, llvm/test/CodeGen/LoongArch/lsx vldrepl-frame-index.ll

[LoongArch] Pre-commit tests for misaligned frame-index offset on vldrepl

Assisted-by: LLM
DeltaFile
+76-0llvm/test/CodeGen/LoongArch/lasx/xvldrepl-frame-index.ll
+76-0llvm/test/CodeGen/LoongArch/lsx/vldrepl-frame-index.ll
+152-02 files

FreeBSD/ports 5d7f083 — www/py-sockjs-tornado distinfo Makefile, www/py-sockjs-tornado/files patch-sockjs_tornado_transports_htmlfile.py

www/py-sockjs-tornado: update to 1.0.7

This release fixes runtime with tornado 6.5. Also add unreleased upstream
patch that's fix XSS issue. Port has been switched to pep517 with
porlint warnings fixed.

Pass maintainership to python@

PR:             299792
Reported by:    Patrick Crandol <patrick at crandol.com>
DeltaFile
+37-0www/py-sockjs-tornado/files/patch-sockjs_tornado_transports_htmlfile.py
+6-5www/py-sockjs-tornado/Makefile
+3-3www/py-sockjs-tornado/distinfo
+46-83 files

LLVM/project fa98dee — llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/X86 tl-libcalls-module-flags.ll

[TargetLowering] Use DAG.getLibcalls() in expandMultipleResultFPLibCall (#239150)

`getLibcallLoweringInfo` and the helper `getLibcallImplCallingConv`
access the `Libcalls` from TargetLoweringBase, which is constructed
without the LLVM Module being available. This affects the libcalls
available through module flags like `long-double-type`. SelectionDAG
already consults the module flags, so missing it here can lead
inconsistencies in which libcalls are available.

Fixes: #239145
DeltaFile
+34-0llvm/test/CodeGen/X86/tl-libcalls-module-flags.ll
+3-2llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+37-22 files

LLVM/project 8a8ab64 — offload/include device.h, offload/libompaccsupport device.cpp

[Offload][Omp] Decouple RecordReplay from PluginInterface (#236814)

After we broke the `GenericKernelyTy` dependence in the RecordReplay
(RR), most of it became independent from the `PluginInterface`.

This PR moves the RR logic from the `PluginInterface` to libomptarget
and changes RR to use OpenMP errors and liboffload for data transfers.
Still, the _VirtualAddress_ interfaces are not available through the
liboffload API so we use them through temporary helpers.

I purposely didn't move the RR source files from the plugin directory so
the changes in this PR would easier to review. The code will be
reorganized in a follow-up NFC PR.

It was verified by @kevinsala on NVIDIA and AMD gpus.

Assisted by Claude

---------

Co-authored-by: Kevin Sala <salapenades1 at llnl.gov>
DeltaFile
+92-18offload/libompaccsupport/device.cpp
+67-42offload/plugins-nextgen/common/src/RecordReplay.cpp
+0-37offload/plugins-nextgen/common/src/PluginInterface.cpp
+0-34offload/plugins-nextgen/common/include/PluginInterface.h
+11-11offload/plugins-nextgen/common/include/RecordReplay.h
+22-0offload/include/device.h
+192-1424 files not shown
+217-14910 files

LLVM/project 5c81f69 — llvm/include/llvm/Transforms/IPO Attributor.h, llvm/lib/Transforms/IPO Attributor.cpp

Attributor: Only check once if time trace scopes are recorded

Every initialization and update of an abstract attribute opened a
TimeTraceScope, which checks if the time profiler is enabled out of line.
Check it once per Attributor instead. NFC.

CTMark instructions:u with -attributor-enable=light changes by O3 -0.02%,
ThinLTO -0.03%. The attributor-light pass itself is 0.3-0.8% faster
(callgrind), and 0.3-1.9% faster with the other pending Attributor
compile-time changes applied.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+12-4llvm/include/llvm/Transforms/IPO/Attributor.h
+8-4llvm/lib/Transforms/IPO/Attributor.cpp
+20-82 files

LLVM/project c408850 — llvm/test/CodeGen/AArch64 arm64-dagcombiner-load-slicing.ll scalarized-store.ll

[AArch64] Regnerate arm64-dagcombiner-load-slicing.ll and add expended store tests. NFC (#239509)
DeltaFile
+900-0llvm/test/CodeGen/AArch64/scalarized-store.ll
+33-21llvm/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll
+933-212 files

OpenBSD/src HsLalsc — sys/dev/isa isadma.c

   Remove unused isa_dmamap_destroy().
VersionDeltaFile
1.40+1-26sys/dev/isa/isadma.c
+1-261 files

FreeBSD/src 1dd8d2d — sys/dev/bnxt/bnxt_en bnxt_ktls.h if_bnxt.c

if_bnxt: skip HW kTLS on old firmware and add a tunable to disable it

Older Thor2 firmware serves key context allocation requests very
slowly, about a second each. The driver allocates key contexts in
batches of 128, so setting up 500k sessions takes roughly 3900
requests and driver load appears to hang.

Enable hardware kTLS only when the firmware's HWRM interface version
is 1.10.3.99 or newer. Keep the full four-part version in
hwrm_spec_code_ext for the comparison.

Also add a disable_hw_ktls loader tunable that turns hardware kTLS off
for a device without unloading kTLS support, which helps isolate kTLS
problems in the field.

Reviewed by:    gallatin
Sponsored by:   Broadcom Inc
MFC after:      3 days
Differential Revision: https://reviews.freebsd.org/D60977

    [2 lines not shown]
DeltaFile
+14-0sys/dev/bnxt/bnxt_en/bnxt_ktls.c
+6-0sys/dev/bnxt/bnxt_en/bnxt_sysctl.c
+6-0sys/dev/bnxt/bnxt_en/bnxt.h
+2-1sys/dev/bnxt/bnxt_en/if_bnxt.c
+3-0sys/dev/bnxt/bnxt_en/bnxt_hwrm.c
+2-0sys/dev/bnxt/bnxt_en/bnxt_ktls.h
+33-16 files

FreeBSD/src 74356e5 — sys/dev/bnxt/bnxt_en bnxt.h bnxt_hwrm.c

if_bnxt: size MRAV from the AV split entry for backing store V2

On RoCE-capable Thor2, attach fails with
HWRM_FUNC_BACKING_STORE_CFG_V2 returning INVALID_PARAMS, as MRAV is
sized the pre-V2 way and the firmware's AV split value is sent as is.

Size MRAV from the AV split entry, and move the legacy entry-count
packing into bnxt_hwrm_func_backing_store_cfg().

Fixes: d5ce906da7c5 ("bnxt_en: Add backing store V2 support")
Reviewed by:    gallatin
Sponsored by:   Broadcom Inc
MFC after:      3 days
Differential Revision: https://reviews.freebsd.org/D60976

(cherry picked from commit aca2e5fae3d9c3350b47ee3e7d00937a73dba9a9)
DeltaFile
+12-12sys/dev/bnxt/bnxt_en/if_bnxt.c
+11-1sys/dev/bnxt/bnxt_en/bnxt_hwrm.c
+2-0sys/dev/bnxt/bnxt_en/bnxt.h
+25-133 files

LLVM/project eaaa209 — llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-stackrestore.mir

[AMDGPU][GISel] Add RegBankLegalize rule for G_STACKRESTORE
DeltaFile
+21-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-stackrestore.mir
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+23-42 files

LLVM/project 456b470 — llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-stackrestore.mir

pre-commit failing test cases
DeltaFile
+41-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-stackrestore.mir
+41-01 files

LLVM/project 2c87de2 — clang/lib/CIR/Dialect/Transforms CIRABIClassifier.cpp, clang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.h CIRABIRewriteContext.cpp

[CIR][AMDGPU] Lower Indirect arguments and sret returns in addrspace(5)
DeltaFile
+62-34clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+93-0clang/test/CIR/Transforms/abi-lowering/amdgpu-indirect.cir
+0-22clang/test/CIR/Transforms/abi-lowering/amdgpu-indirect-nyi.cir
+6-5clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
+0-3clang/lib/CIR/Dialect/Transforms/CIRABIClassifier.cpp
+161-645 files

LLVM/project 7e4250c — clang/test/OpenMP interchange_codegen.cpp, libcxx/test/std/language.support/support.limits/support.limits.general version.version.compile.pass.cpp

Merge branch 'main' into users/zero9178/ods-dialect-includes
DeltaFile
+8,752-1,285llvm/test/CodeGen/WebAssembly/memory-interleave.ll
+3,550-3,691llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+984-980llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+818-816llvm/test/CodeGen/ARM/vector-lrint.ll
+1,576-10libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
+764-684clang/test/OpenMP/interchange_codegen.cpp
+16,444-7,4661,517 files not shown
+66,422-32,9671,523 files

LLVM/project 58ddb5c — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 concat_vector-truncate-combine.ll concat_vector-truncate-combine2.ll

[DAG][AArch64] Use NVCAST instead of BITCAST in (concat_vectors (trunc), (trunc)) (#238633)

Fix issue: https://github.com/llvm/llvm-project/issues/238632
DeltaFile
+53-0llvm/test/CodeGen/AArch64/concat_vector-truncate-combine2.ll
+0-26llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
+5-5llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+58-313 files

OpenBSD/ports fgonldQ — devel/lua-cjson Makefile

   update HOMEPAGE and SITES

   ok tb@
VersionDeltaFile
1.12+3-3devel/lua-cjson/Makefile
+3-31 files

LLVM/project 713c979 — mlir/lib/Dialect/NVGPU/Transforms OptimizeSharedMemory.cpp, mlir/test/Dialect/NVGPU optimize-shared-memory.mlir

[mlir][nvgpu] Don't swizzle shared memory rows that aren't a power of 2 (#237179)

`nvgpu-optimize-shared-memory` miscompiles memrefs whose rows aren't a
power
of 2 long. The swizzle XORs the index of each 16-byte vector in a row
with low
bits of the row index. When a row holds a power of 2 number of vectors,
the
result is always an index in the same row, so the swizzle only reorders
each
row. Otherwise, the result can be past the end of the row: the access
then
lands in the next row and overwrites one of its vectors, or past the end
of
the buffer for the last rows.

Skip such memrefs and leave their accesses unswizzled.

Assisted-by: Claude
DeltaFile
+30-0mlir/test/Dialect/NVGPU/optimize-shared-memory.mlir
+6-0mlir/lib/Dialect/NVGPU/Transforms/OptimizeSharedMemory.cpp
+36-02 files