ansible: updated to 14.1.0
14.1.0
Major Changes
community.clickhouse
- clickhouse_named_collection - new module to add/modify/delete named collections in database.
vmware.vmware_rest
- Update minimum required ansible-core version to 2.16 in meta/runtime.yml
resterm: Update to 0.45.1
Vim-Style Command Line
Added a Vim-like command line to the TUI. Press : from normal-mode panes to run common actions such as :w, :q, :q!, :wq, :x, :e, :help, and :noh.
Search UX
Search behavior now more closely follows Vim: opening / starts with an empty prompt while keeping the previous search available for match navigation, and clearing the live search input clears current highlights.
The search prompt UI was also simplified by removing the extra search icon. This release also includes theming support.
clang/AMDGPU: Fix double linking opencl libs with --libclc-lib
Noticed by inspection. If using an explicit --libclc-lib flag,
do not attempt to also link the rocm device libs which will contain
different implementations of the same opencl symbols.
Co-Authored-By: Claude <noreply at anthropic.com>
clang/AMDGPU: Remove driver restriction on --gpu-max-threads-per-block
Previously this flag was only handled for HIP, and would produce an unused
argument warning. There is a custom warning produced by cc1 that the
argument isn't supported, but practically speaking that was unreachable
due to not forwarding the argument. Also add a test for the untested warning.
Also use a simpler method for forwarding the flag to cc1.
dropbear: updated to 2026.92
2026.92 - 6 July 2026
Note >> for compatibility/configuration changes
- >> server auth plugins have been deprecated, the configure option
has been renamed to --enable-plugin-deprecated.
Planned to be removed in future.
- >> Two factor auth "-t" has been deprecated, it now requires
a configuration option DEPRECATED_TWO_FACTOR.
Planned to be removed in future.
- Security: server: Don't allow -B (accept blank password) with
-t (two factor auth). If run with -t and -B a user configured with a
blank password would be allowed to log in without pubkey auth.
https://github.com/mkj/dropbear/commit/23ec78285639edf068d86bb96f91cba755039740
Reported by nvidia
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[LV][RISCV] Enable FSub reduction for scalable VFs (#207698)
#197134 introduced a change to FAdd reduction recognition, causing fsub
instructions to be classified as FSub reductions instead of FAdd
reductions. This patch fixes the regression by enabling FSub reduction
support for scalable VFs in TTI.
[Hexagon] Optimize sext + mul pattern for splatted scalar sext i16 (#206893)
Extend the existing vmpyh pattern to handle the case where one operand
of a v2i32 nsw mul is a splatted scalar sext i16 value. When the splat
is hoisted out of a loop, it arrives as assertsext v2i32, i16 in the DAG
rather than sext v2i16. The existing pattern did not match this form,
causing the multiply to expand to two scalar mpyi instructions.
Add a PatFrag assertsext_v2i32_i16 to match assertsext nodes of type
v2i32 extended from i16, and two new patterns (both operand orderings)
that recover the v2i16 using A2_combine_ll before feeding into
M2_vmpy2s_s0.
[AArch64] C1-Nano scheduler cleanup in preparation for SME [NFC] (#207738)
Change are in preparation for a forthcoming addition of SME to the
C1-Nano scheduling model. This is restructuring of the code which does
not involve the actual SME changes. By separating out these NFC changes
it will make review of the SME specific changes easier.
- Defined resource names to match the form now used in the C1-Ultra
scheduling model which has the throughput information on the end of the
name rather than in the middle:
C1NanoWrite_1c_1r_2ALU => C1NanoWrite_1c_2ALU_1rc
- Moved definitions so that they more closely match the order they are
defined in the C1-Nano SWOG. This make it easier to match entries in the
code to the tables in the SWOG.
These changes also make the C1-Nano scheduling model more closely match
the forms and layout used in the C1-Ultra scheduling model.
[clang][AST] Qualify DeclRefExpr printing (#206041)
I updated DeclRefExpr printing so fully-qualified printing consistently
uses declaration ownership rather than only the written qualifier. This
also preserves existing behavior for local names and cleaned parameter
names.
The added tests cover both the direct expression printer behavior and
the original type-printing scenario that exposed the missing
qualification.
Fixes #205925
octgpio: OCTEON GPIO controller driver
Port of OpenBSD octgpio(4) (Visa Hankala) onto the NetBSD fdtbus
gpio controller API.
Deviations from the OpenBSD original, per the SDK CSR definitions:
CN63XX/CN68XX and CN38/52/56/58XX have 16 pins and no XBIT_CFG
registers. The OUTPUT_SEL output mux is cleared only on CN70XX and
newer, where it exists.
Attach at pass 3 so consumers (octmmc cd-gpios) find the controller
registered. Primary motivation is SD card-detect on boards with a
real MMC slot but could drive LEDs and other features later.
Reviewed by skrll@
: ----------------------------------------------------------------------
clang/AMDGPU: Merge toolchain subclasses
Simplify the toolchain implementations by collapsing
them into one. Previously we had a confusing split. The
AMDGPUToolChain base class implemented much of the base
support. It was subclassed by ROCMToolChain, which would
have been more accurately described as the offloading subclass.
That was further subclassed into HIP and OpenMP specific subclasses.
Deleting those two is the important part of this change. There was
code duplication, and features arbitrarily handled in one but not
the other. The offload kind is passed in almost everywhere if you
really need to know the original language. However, I consider
this an antifeature, and it is really poor QoI to have the HIP
and OpenMP toolchains behave differently in any way. The platform
should be consistent and the driver behaviors should not depend
on the language.
There is additional mess in the handling of spirv, which this
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[RISCV][LLDB] Add RISC-V Architecture plugin for trap validation (#207675)
Add a minimal `RISC-V Architecture` plugin and implement
`IsValidTrapInstruction` for trap opcodes. The plugin recognizes riscv32
and riscv64 targets and validates 32-bit `EBREAK` and 16-bit `C.EBREAK`.
On RISC-V, `EBREAK` traps with the PC still pointing at the `EBREAK`
instruction. A plain continue resumes from that same PC and traps again.
This issue was found while trying to run the `TestBuiltinDebugTrap` test
case locally on a `RISC-V QEMU`.
Added a cpp unit test to verify the behaviour of
`IsValidTrapInstruction`. I've chosen to verify `EBREAK` on `riscv32`
and `C.EBREAK` on `riscv64` so that there is some coverage for both
targets.
Assisted by gpt-5.5
Pull up the following revisions(s) (requested by msaitoh in ticket #2036):
usr.sbin/syslogd/extern.h: revision 1.5
usr.sbin/syslogd/sign.c: revision 1.10
usr.sbin/syslogd/sign.h: revision 1.4
usr.sbin/syslogd/syslogd.c: revision 1.132,1.137,1.139,1.141,1.145,1.148,1.151-1.155 via patch
usr.sbin/syslogd/syslogd.h: revision 1.10-1.11 via patch
usr.sbin/syslogd/tls.c: revision 1.18,1.20,1.26-1.27
usr.sbin/syslogd/tls.h: revision 1.4
Some improvements for syslogd(8):
- Retry sendto() if it raises EBUSY, too.
- Add missing SLIST_INIT() in main(). This is not a real bug because
the tls_opt is in BSS and SLIST_INIT() assign NULL.
- Cleanups (KNF, fix typos and G.C.).
AMDGPU: Respect target assembler directives over command line
Mutate the global subtarget, using essentially the same code that ARM uses.
The main difference is we need to mutate the actual CPU name in addition
to just flipping the feature bits, so this needs a new setter in
MCSubtargetInfo. Liberalize the triple check so that after #206480,
old assembly files to not break on new assembler invocations.
For some reason we have 2 different assembler directives that indicate the
target, .amdgcn_target for amdhsa and .amd_amdgpu_isa for amdpal. Previously,
we would take the target from the command line and then error if the directive
did not exactly match. In order to move away from depending on the xnack and
sramecc subtarget features, start treating the directives as a change of target,
similar to ARM's .cpu and .arch directives.
Both .amdgcn_target and .amd_amdgpu_isa encode full triples, but unlike
.amdgcn_target, the PAL directive does not include xnack or sramecc. Ideally
we would introduce new independent directives for these.
Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
[X86][Windows] use `LowerWin64_INT128_TO_FP` for `u128` to `f128` conversion (#207285)
This change fixes an ABI issue where the signed conversion passes a
`i128` different from a `u128`, and crucially different from GCC.
https://godbolt.org/z/x3daY3rej
```diff
--- <unnamed>
+++ <unnamed>
@@ -1,15 +1,15 @@
-conv_from_i128:
+conv_from_u128:
push rsi
- sub rsp, 64
+ sub rsp, 48
mov rsi, rcx
- movaps xmm0, xmmword ptr [rdx]
- movaps xmmword ptr [rsp + 48], xmm0
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[AArch64][msvc] allow higher align than slot size in va_arg (#207591)
Fixes https://github.com/llvm/llvm-project/issues/207584
On aarch64 windows, an `__int128` argument is passed with alignment 16,
but was read with an alignment of 8. Based on the MSVC assembly and how
e.g. aarch64 darwin handles this, I think it's correct to set
`AllowHigherAlign = true`.
