[Clang][OpenMP] Preserve dbg loc for GPU reduction combiner calls (#236574)
GPU reduction codegen currently suppresses debug information while
emitting combiners because they may be emitted in generated helpers
without a DISubprogram. However, the same combiner can also be emitted
directly in outlined functions that have a DISubprogram.
Suppress debug information only for the helper case, preserving valid
debug locations for direct combiner calls in outlined functions.
Assisted by gpt-5.6.
[VPlan] Remove header masks whose tail lanes aren't used
Replace a use of header-mask && x with x if the user, transitively
through freeze, logical-and, not and mask.beforefirst(freeze ...), only
reaches masks that are and'ed with the header mask again. The header
mask is a prefix and lane i of mask.beforefirst only depends on lanes
0..i, so the lanes outside of the header mask are never used.
This avoids the i1 vp.merge that EVL tail folding needs for the inner
header mask, e.g. in the early exit mask.beforefirst(freeze(header-mask
&& c)) and in switch default edges.
[InstCombine] Canonicalise Vector Shuffle that clears upper bits
Currently, shuffle vectors that are equivalent to preserving lane 0 and clearing the uppers lanes of a vector result in different shuffle vectors and masks
Recognise and canonicalise the shuffleVectors to the same form allowing for easier recognition in the backend
[VPlan] Allow tail folding early exits with side effects
Continues the work in #179595.
This allows us to tail fold e.g. the following loop:
```c
extern char a[1024], b[1024], c[1024], y[1024];
void two_guards(void) {
for (int i = 0; i < 1000; i++) {
if (a[i] == 0)
break;
if (b[i] > 3) {
if (c[i] < 9)
y[i] = 1;
}
}
}
```
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editors/openoffice-4: Switch to bundled lucene.
Use bundled lucene instead of the lucene port and amend DEPRECATED.
MFH: 2026Q4
(cherry picked from commit 77dc9dabebd898241d5f641dfb3e58029a7f1298)
editors/openoffice-devel: upgrade to new snapshot
Upgrade to a newer snapshot of the upstream trunk branch.
Wiki Publisher no longer uses apache-commons-codec or the insecure
apache-commons-httpclient so unbreak and re-enable the WIKI_PUBLISHER_
option.
These patches have been upstreamed:
patch-bridges_source_cpp__uno_gcc3__freebsd__powerpc64_call.s
patch-bridges_source_cpp__uno_gcc3__freebsd__powerpc64_cpp2uno.cxx
patch-bridges_source_cpp__uno_gcc3__freebsd__powerpc64_share.hxx
patch-bridges_source_cpp__uno_gcc3__freebsd__powerpc64_uno2cpp.cxx
patch-jvmfwk_plugins_sunmajor_pluginlib_vendorbase.hxx
patch-set_soenv.in
patch-source__soenv.sh
Use bundled lucene instead of the lucene port and remove DEPRECATED.
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editors/openoffice-*: enable on powerpc64le
OpenJDK keeps its libraries in jre/lib/ppc64le on little-endian, and
source_soenv.sh in -devel only knew the big-endian triple.
(cherry picked from commit cfb4eff2c826bcd0a780fe925be1894d4bc1369b)
editors/openoffice-*: don't require libjawt.so
openjdk8 keeps libjawt.so under jre/lib, where pkg doesn't register it
as provided, so pkg add of the package fails with "Missing shlib
libjawt.so". openjdk8 is already a run dependency.
(cherry picked from commit e1c869f4c1d4a0c358c5115b92440c7613c230e3)
[lldb] Number the Wasm virtual registers (#237243)
WasmVirtualRegisterInfo current leaves every register number at 0, the
default
constructed value.
This PR gives each virtual register its own number,
GetWasmRegister(kind, index), as its LLDB number.
Other kinds are left as invalid: DWARF names these values with
DW_OP_WASM_location, not with register numbers, and they have no EH
frame or generic number.
code assisted by claude
[Driver] Remove -mcmodel=small restriction for -fsanitize=function (#238028)
Since https://reviews.llvm.org/D148785, -fsanitize=function no longer
uses RTTI pointers or relocations in the function prefix, so it can now
be used with medium and large code models.
[Bazel][libc] Add kill syscall wrapper target (#238035)
Fixes Bazel build after c7d0351b066cf2770ce2110c616c4e60b847ca79
(#237798), which refactored the Linux `kill` syscall into
`src/__support/OSUtil/linux/syscall_wrappers/kill.h`.
[InstCombine] Canonicalise Vector Shuffle that clears upper bits
Currently, shuffle vectors that are equivalent to preserving lane 0 and clearing the uppers lanes of a vector result in different shuffle vectors and masks
Recognise and canonicalise the shuffleVectors to the same form allowing for easier recognition in the backend
igc: Count packets dropped for want of a receive descriptor
When a receive ring is full the hardware drops the packet and counts it
in RQDPC, a per-queue register the driver never read. Such drops were
invisible: MPC counts packet buffer overflows, not descriptor
exhaustion, so an overloaded queue lost packets with nothing to show for
it. With several receive queues this is the common overload signature,
since RSS loads the queues unevenly and one saturated queue drops while
the others idle.
Read RQDPC for each queue with the other statistics and account the
drops per queue as dev.igc.N.queue_rx_M.rx_drops and in total as the
interface's input queue drop counter (netstat -d, Idrop), as ixgbe does
with QPRDC. Write the register back to zero after reading; the I210
documents it as read/write rather than read-to-clear.
Reviewed by: kbowling
MFC after: 2 weeks
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D61004
[SPIR-V][NewPM] Force AsmPrinter begin/end passes (#238020)
Without Force, -start-after drops them and SPIRVAsmPrinterPass crashes
on a missing AsmPrinter
This matches other targets
[SelectionDAG] Provide context for vector count / type mismatch (#175433)
This now gives better details about what the mismatch is in the error
message:
subprocess.CalledProcessError: Command '/usr/local/bin/llc
-mtriple=amdgcn -mcpu=tahiti' returned non-zero exit status 134.
LLVM ERROR: Part count doesn't match vector breakdown! 6 registers, 6
parts, i32 RegisterVT, f32 PartVT
PLEASE submit a bug report to
https://github.com/llvm/llvm-project/issues/ and include the crash
backtrace and instructions to reproduce the bug.
[AArch64][llvm] Ensure svnot_u32_x() intrinsic is optimised to subr (#237251)
All-active SVE NOT intrinsics, such as `svnot_u32_x(svptrue_b32(), x)`
currently generate `ptrue` followed by predicated `not`. Optimise this
to subr `z0.b, z0.b, #255`, which subtracts each byte from 255 and
therefore flips every bit. This implements bitwise `not` for vectors
of 8, 16, 32, or 64-bit elements. Test all these four widths.
[AArch64][llvm] Add pre-commit tests for all-active SVE not intrinsics (#237250)
Cover all four integer widths with undefined and merging passthroughs,
plus a partially active predicate that must preserve inactive lanes.
