WebAssembly: Take the exception model from the module flag
The WebAssembly EH passes chose whether and how to run from
MCAsmInfo::getExceptionHandlingType() and TargetOptions::ExceptionModel,
A module that asked for Wasm EH through the module flag alone would have
its invokes rewritten by LowerInvoke before WasmEHPrepare ran.
Schedule the passes unconditionally and read the module flag inside the
passes instead. Passes for other models can noop on the models they are
not intended for.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
zinject: keep inject_lock off the zio hot path
zio_vdev_io_start() and the leaf vdev io_start() handlers call into
zinject for every leaf zio without first checking whether any handler
is registered. inject_lock is a single global rwlock, so acquiring it
even as a reader bounces its cache line across all CPUs: it accounted
for ~18% of write issue thread time in a 32KB random write profile on
a 64-core system.
Short circuit each injection hook on zio_injection_enabled before
the lock, and make inject_delay_count atomic so zio_handle_io_delay()
can test it unlocked. With the gate now in the callee, drop the
redundant caller-side checks on the cold panic injection paths.
Reviewed-by: Matthew Ahrens <matt at mahrens.org>
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Alexander Motin <alexander.motin at TrueNAS.com>
Closes #19357
[clang][ssaf] Add clang-ssaf-orchestrator-make (#231583)
Add a tool that runs an SSAF workflow over a project built with make. It
extracts a summary for every translation unit, links the summaries the
way the build links the objects, and can run whole-program analysis on
the result.
The tool works alongside the build rather than replacing it. It puts a
directory of links named cc, clang, c++, clang++ and ld at the front of
PATH, all pointing to one shim program. Each shim runs the build's own
tool unchanged and then the matching SSAF step. A compiler that PATH
does not reach, such as one named by an absolute path or run through a
launcher, is not analyzed.
The clang shim asks the driver with -### how a command decomposes into
jobs, and runs each frontend job again with the SSAF clang and the
--ssaf-* options. The ld shim records which artifacts each link consumed
and links their summaries with clang-ssaf-linker. The output that
nothing else consumes is the link unit; with --analysis,
[3 lines not shown]
[AArch64] Support FP atomic stores with memory hints
This patch extends the atomic-store-hint pseudos to accept preserved
floating-point atomic stores. It adds an FPR16 pseudo family and direct
half, bfloat, float, and double patterns for the supported addressing
modes.
The pseudos expand relaxed stores to STR and RCPC3 release stores to
STLUR, retaining memory hints without cross-register-bank copies.
[AArch64] Support direct RCPC3 FP atomic loads and stores
This patch preserves half, bfloat, float, and double atomic loads and
stores through AtomicExpand for acquire and release orderings when RCPC3
and NEON are available.
It adds SelectionDAG patterns for the RCPC3 LDAPUR and STLUR operations,
including unscaled offsets, and updates the existing FP lane patterns to
match the preserved floating-point atomic nodes. Targets without the
required features continue to use integer lowering.
CI: start only one dhcpcd on the Alpine runner
The Alpine VMs started dhcpcd twice: once as the dhcpcd service, and
once from the networking service, which brings up eth0 through
ifupdown-ng and runs dhcpcd itself. The two race at boot. When the
second one contacts the first while it is still starting up, neither
configures eth0, and the test VMs cannot be reached.
The race is rare on a normal boot but much more common with kmemleak
enabled.
Leave eth0 to the networking service.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Alexander Moch <mail at alexmoch.com>
Closes #19363
Attributor: Don't privatize pointers to types with tail padding (#231558)
isDenselyPacked checked for padding before and between struct elements,
but not after the last one, so { ptr, i32 } was considered densely packed.
The padding bytes are not passed when the argument is privatized, which
broke sqlite3 when the pointer was to a union containing such a struct.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Skip the nopwrite checksum ASSERT for data-less overrides
dbuf_write() issues the override write of a Direct I/O write with no
data and the WP_NOFILL policy, so its zp_checksum is off. When the
Direct I/O write was a nopwrite, zio_write_bp_init() then compares the
checksum of the old block pointer with it and fails
ASSERT3U(BP_GET_CHECKSUM(bp), ==, zp->zp_checksum) on debug builds.
Only check the checksum when the override write has data.
This makes dio_nopwrite pass on debug builds.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Will Rouesnel <wrouesnel at wrouesnel.com>
Closes #19335
ZTS: Direct I/O write of the same data as a nopwrite
No test covers a Direct I/O write that nopwrites. On a debug build,
syncing one fails ASSERT3U(BP_GET_CHECKSUM(bp), ==, zp->zp_checksum)
in zio_write_bp_init(): dbuf_write() issues the data-less override of
a Direct I/O write with the WP_NOFILL policy, whose checksum is off.
Add a test that rewrites a file with the same data with Direct I/O on
a dataset with nopwrite enabled, and checks that the block pointers
did not change.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Will Rouesnel <wrouesnel at wrouesnel.com>
Closes #19335
[SLP]Fix crash for reused non-schedulable copyables
Bail out of scheduling a bundle if its scalar is a non-schedulable
copyable element of another same-block node, which reuses it without
a schedule dependency.
Fixes #231525
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/231598
[dyndbg][LLD][ELF] Add dynamic debugging support for `--wrap=<symbol>` (#222990)
* Forward the `--wrap=<symbol>` arguments to the "inner" relocatable
link.
* In the "outer" main link, set the `isDynDbgRef` flag appropriately for
the symbols involved.
mgb: support for PCI11414.
Add support for Microchip PCI11414 Gigabit Ethernet Controller.
The PCI11414 is used on the CHERI VITA 57.1 PCIe Extension Board.
- Add PCI11414 device ID
- Add support for SGMII mode. Read the programmed strap configuration
and enable SGMII operation when configured. Bypass the MII interface
in SGMII mode.
- Increase the DMA descriptor ring size.
Reviewed by: emaste
Sponsored by: EPSRC ("UKRI3001: CHERI Research Centre")
Differential Revision: https://reviews.freebsd.org/D60539
[AMDGPU] Recognize workitem.id.x as the lane ID in isThreadID
The matchers for wave shuffles use `isThreadID`, which only recognized
the mbcnt()-based form. However,
1) This gets canonicalized to workitem-id-based checks in some cases
and
2) Masking the workitem ID (when we know it changes between waves at a
power of 2) is a valid and typical way to express the lane ID.
Therefore, amend isThreadID to catch these forms of lane ID.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
[AMDGPU][NFC] Add lane-index-from-workitem.id.x tests for wave shuffles (#231234)
mbcnt()-based lane IDs are sometimes rewritten to workitem ID-based
ones, precommit tests for this.
AI disclosure: Claude wrote these tests, I wrote the commit message
and renamed the tests / trimmed down comments
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
[AArch64] Support FP atomic stores with memory hints
This patch extends the atomic-store-hint pseudos to accept preserved
floating-point atomic stores. It adds an FPR16 pseudo family and direct
half, bfloat, float, and double patterns for the supported addressing
modes.
The pseudos expand relaxed stores to STR and RCPC3 release stores to
STLUR, retaining memory hints without cross-register-bank copies.
[AArch64] Support direct RCPC3 FP atomic loads and stores
This patch preserves half, bfloat, float, and double atomic loads and
stores through AtomicExpand for acquire and release orderings when RCPC3
and NEON are available.
It adds SelectionDAG patterns for the RCPC3 LDAPUR and STLUR operations,
including unscaled offsets, and updates the existing FP lane patterns to
match the preserved floating-point atomic nodes. Targets without the
required features continue to use integer lowering.
[AArch64] Support direct relaxed FP atomic loads and stores
This patch preserves half, bfloat, float, and double atomic loads and
stores through AtomicExpand when they use unordered or monotonic
ordering and the target supports floating point.
It adds SelectionDAG patterns that select the accesses directly in the
floating-point register bank. Unsupported targets, stronger orderings,
and stores carrying memory hints continue to use integer lowering.
