[SPARC] Model FSR use and FP exceptions on FP instructions (#237497)
FP instructions depend on the rounding mode held in %fsr and may raise
FP exceptions, but nothing told the code generator about either.
Mark the FPop instructions (arithmetic, square root, conversions, the
UA2007 FMAs and the VIS3 fused negate/halve instructions) as implicitly
using %fsr and as mayRaiseFPException, and mark the FP compares as
mayRaiseFPException. Reserve FSR so that the implicit use is always
valid.
Instruction selection marks instructions selected from ordinary
(non-strict) FP operations as nofpexcept, so code generation does not
change. This prepares for supporting constrained FP operations.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[llvm][unittests] Unregister the local cl::opt in MLGOUtilsTest (#239022)
Since commit 00f2b0ed670a, this test has been failing w/ asan because of
a pointer to a stack-local object is put in the global options map
without cleanup.
LLM-aided
security/openpgp-card-tools-git: [NEW PORT] Git signing and verification with a focus on OpenPGP cards
The openpgp-card-tools-git package provides 'oct-git', a tool for Git
commit and tag signing and verification with a focus on OpenPGP cards.
It can be configured as Git's gpg.program, keeping signing keys on
hardware tokens instead of on disk.
WWW: https://codeberg.org/openpgp-card/oct-git
PR: 293961
CodeGen: Compute the machine dominance frontier lazily
The legacy pass eagerly computed the frontier whenever a pass required
it. X86 LVI load hardening always required it but returned immediately
unless the lvi-load-hardening feature is enabled, so this was computed
and thrown away in the default case. Record the dominator tree when
the wrapper runs and compute the frontier the first time it is
requested.
Instructions retired for llc -O3 -filetype=null over the 10 CTMark
programs as x86_64 full-LTO modules:
total -0.26%
ClamAV -0.47%
7zip -0.41%
consumer-typeset -0.32%
SPASS -0.31%
sqlite3 -0.29%
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[CIR] Calling convention add tagging marker (#237433)
[CIR] Make CallConvLowering safe to rerun on its own output
A signature lowered by CallConvLowering uses ordinary CIR types, so the
pass cannot tell it apart from one that still needs lowering. Running
it again on its own output, e.g. on an emitted .cir file, lowers it a
second time: on x86_64 a struct of two floats lowers to
vector<2 x float>, which a second run turns into double, the lowering
of a source-level float vector_size(8). Nothing errors and the code is
wrong.
Record what the pass has lowered with a 'call_conv_lowered' marker and
skip it on later runs:
- cir.func gets a unit attribute, printed as a keyword at the end of
the function header, when the pass rewrites its signature.
- An indirect call gets the marker when its rewrite changes anything.
- A call that passes arguments through an ellipsis is classified on its
own, so it can need a rewrite its callee does not; it gets its own
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DwarfEHPrepare: Use RuntimeLibcallsInfo signature for the rewind libcall (#238998)
Report an error if no rewind libcall is available, rather than
emitting a call to a function with an empty name.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Print encoding suffix for instructions without operands (#234466)
The _e64 and _sdwa suffixes are printed by printVOPDst along with the
destination operand. v_nop, v_clrexcp and v_pipeflush have no operands,
so their VOP3 and SDWA forms were printed without the suffix, and
textual output reassembled to the 4-byte VOP1 encoding. With the
integrated assembler, -S and -save-temps output is assembled again by
MC, so this silently changed code size and branch offsets compared with
direct object emission.
This fixes the FIXMEs in vop3.s and vop3-vop1-nosrc.s, which is removed.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[DebugInfo][SelectionDAG] Stop unsalvageable debug values from sinking (#233667)
SelectionDAG resolves dangling debug values at the end of a block. When
a
value cannot be salvaged, the poison `DBG_VALUE` currently uses the
current
`SDNodeOrder`, so it can sink past later calls and stores instead of
ending the
earlier variable location at the original debug record.
Use the saved order of the debug record, as the successful salvage paths
already do. Extend `sdag-order.ll` with an unsalvageable call result
followed
by another call and a volatile store; without the fix the location
termination
appears after both instructions.
This completes the ordering correction from #94458 for the final
unsalvageable fallback.
AI assisted with the analysis and development of the fix.
libthr: Cache recent pshared_key
For a pshare key, we can actually cache the last one as a fast path
instead of trapping into kernel directly. It makes sense as a lock and
unlock should be a pair on the same key and at the same time. For
example, lock(A) -> unlock(A) -> lock(B) -> unlock(B). Each unlock is
a hit and refresh later (50% hit).
For a single pshare lock, it is evne a 100% hit as the key never
changed.
For nested lock lock(A) -> lock(B) -> lock(C) -> unlock(C) ->
unlock(B) -> unlock(A). It only cache the last one. However, we should
really think about rewritting this logic as it is a pshare lock shared
by many processes and nested should be uncommon.
Reviewed by: kib
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D60957
security/keychain: Small updates
Point at new GH location (old redirects to new), modernize pkg-descr,
and adopt my personal preferences (the port has been around for 21
years, we can probably stop guarding against its name changing.)
Note that keychain 3.x, which has been out for a couple months, is a
Python rewrite. It needs no third-party modules, but it's definitely
a change from the "one portable shell script" ethos I recall from
decades ago. I'm working on that update, and from what I can tell it
should require basically no adjustment on the end-user side of things,
so I'm unlikely to create a keychain298 port (happy to take input on
that!).
WasmEHPrepare: Use RuntimeLibcallsInfo
Take the function type, attributes and calling convention from
RuntimeLibcallsInfo instead of constructing them by hand. Also
validate the required functions are available.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
RuntimeLibcalls: Mark vector libcall out pointers dereferenceable
The whole vector width will be written, so mark the vector width. To
maintain the element width alignment for some functions, we need to
start explicitly tracking if the element alignment is used or not.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Tools/scripts/update-plist.py: Bugfix
Remove stale pkg-plist lines preceded by an OPTIONS_SUB. E.g.: remove
%%FOO%%include/bar.h if it is no longer packaged.
MFH: 2026Q4
(cherry picked from commit 97856031311db3350b2e1428d7a9b00f9c2e5b85)
RuntimeLibcalls: Declare vector libcall attributes in TableGen
Replace the type-based heuristics for vector math libcall attributes
with attributes declared on the libcall definitions, emitted with the
same attribute table helpers as intrinsics.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Tools/scripts/update-plist.py: Bugfix
Remove stale pkg-plist lines preceded by an OPTIONS_SUB. E.g.: remove
%%FOO%%include/bar.h if it is no longer packaged.
MFH: 2026Q4
AtomicExpand: Use RuntimeLibcallsInfo signatures for atomic libcalls (#238972)
Take the function type and attributes of the emitted __atomic_* calls
from RuntimeLibcallsInfo instead of building them by hand.
This fixes missing extension attributes on the value operand and
result of the sized variants, which are unsigned integers of the
access size. On targets whose C ABI extends narrow integer arguments,
such as RISC-V and ARM, the callee could see unextended high bits. i8
and i16 values now get zeroext, and i32 values get signext on
RV64. Callers can also rely on the extended return value, which
removes redundant extensions after some calls.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
gve: Page-align DQO descriptor and completion rings
Currently, gve_rx_alloc_ring_dqo() and gve_tx_alloc_ring_dqo() request
CACHE_LINE_SIZE alignment when allocating DMA memory for the DQO TX/RX
descriptor and completion rings. The device requires stronger alignment
than cache line alignment, which was incidentally being met due to how
the kernel allocates memory. Explicitly meet this requirement by
requesting page aligned memory.
Signed-off-by: Tim Hostetler <thostet at google.com>
Reviewed by: markj, Jasper Tran O'Leary <jtranoleary at google.com>
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D61211
gve: Fix AdminQ buffer DMA sync directions
In gve_verify_driver_compatibility(), the driver populates the
gve_driver_info buffer for the device to read. Sync this buffer with
BUS_DMASYNC_PREWRITE instead of BUS_DMASYNC_PREREAD before issuing
the command.
In gve_adminq_describe_device(), the device populates the
gve_device_descriptor buffer for the driver to read. Sync this buffer
with BUS_DMASYNC_PREREAD instead of BUS_DMASYNC_PREWRITE before
issuing the command.
In gve_adminq_get_ptype_map_dqo(), the device populates the
gve_ptype_map buffer for the driver to read. Add the missing
BUS_DMASYNC_PREREAD and BUS_DMASYNC_POSTREAD syncs around the
command.
In normal GCP environments this did not cause a functional failure
because the underlying platforms are DMA cache-coherent and
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sparc: Stop exposing default KERNBASE to modules
Otherwise, on kernels with non-standard KERNBASE, modules reference
illegal addresses when using curcpu(), curlwp, and so on.
Unfortunately, this cannot be pulled-up to release branches, as
this changes module ABI.
Ride on 11.99.10 version bump.
ARM: Remove dead kill flag maintenance in MVETPAndVPTOptimisations
This pass runs before register allocation, and the verifier now
rejects kill flags on virtual registers.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
