[Clang][OpenCL] Add OpenCL 3.1 language version (#204043)
OpenCL 3.1 was recently added to spec in
https://github.com/KhronosGroup/OpenCL-Docs/commit/9fff1a87a975
This PR adds version 3.1 to clang support, including frontend flag
`-std=cl3.1` (and its alias `-std=CL3.1`).
Updated release note.
A few extensions are promoted to 3.1 core. They'll be handled in
follow-up PRs.
Assisted-by: Claude Sonnet 4.6
[RFC][IR] Extract AMDGPU-specific verification logic into `VerifierAMDGPU.cpp`
`Verifier.cpp` is large and already mixes generic IR verification with
target-specific checks. We also have a growing amount of AMDGPU verifier logic
downstream, which would all end up in the same file if we don't address this,
and that is not ideal.
This patch extracts AMDGPU-specific verification logic into a separate
`VerifierAMDGPU.cpp` file, with shared infrastructure (`VerifierSupport`) moved
into `VerifierInternal.h`.
This is purely a code organization change, not a target-dependent IR verifier.
All checks remain compiled and linked into `LLVMCore` regardless of the target
triple. The extracted functions are called unconditionally at well-defined
extension points in `Verifier.cpp`, and each function internally gates on
target-specific conditions (for example, triple checks or intrinsic IDs) as
needed. The file is strictly limited to AMDGPU-specific IR constructs (amdgcn
intrinsics, AMDGPU module flags, etc.), and does not contain generic IR rules
that vary by target.
[10 lines not shown]
[LoongArch] Add DAG combine for widening shift-left (#202602)
Add DAG combines to recognize vector widening left-shift idioms and
lower them to VSLLWIL instructions.
The following pattern is matched for both signed and unsigned variants:
```
SEXT/ZEXT(Low-Half-Lanes(vec)) << Imm
```
This covers the following instructions:
```
LSX: VSLLWIL.H.B, VSLLWIL.W.H, VSLLWIL.D.W
VSLLWIL.HU.BU, VSLLWIL.WU.HU, VSLLWIL.DU.WU
LASX: XVSLLWIL.H.B, XVSLLWIL.W.H, XVSLLWIL.D.W
XVSLLWIL.HU.BU, XVSLLWIL.WU.HU, XVSLLWIL.DU.WU
```
[RDF] Replace unordered_map with DenseMap. NFC (#204280)
std::unordered_map is slow. Switch DefStackMap and RefMap to DenseMap.
erase-while-iterating loops become DenseMap::remove_if.
[llvm] Replace unordered_{map,set} with Dense{Map,Set} in local maps (#204277)
std::unordered_map is slow. Replace maps and sets without a
pointer-stability requirement to DenseMap/DenseSet.
Extracted from #202222
[bazel] Use --incompatible_default_to_explicit_init_py (#204275)
After #203998, the `per-test-coverage-by-lit-cfg.py` test is failing in
Bazel. It seems to be due to automatic `__init__.py` generation.
With some extra logs:
```
# .---command stdout------------
# | -- Testing: 5 tests, 1 workers --
# | FAIL: per-test-coverage-by-lit-cfg :: name-collision/__init__.py (1 of 5)
# | ******************** TEST 'per-test-coverage-by-lit-cfg :: name-collision/__init__.py' FAILED ********************
...
# | # .---command stderr------------
# | # | error: no check strings found with prefix 'CHECK:'
# | # `-----------------------------
```
I am not sure exactly the best way to deal with this, but
`--incompatible_default_to_explicit_init_py` disables this behavior and
[2 lines not shown]
[LoongArch] Add DAG combine for widening shift-left
Add DAG combines to recognize vector widening left-shift idioms and
lower them to VSLLWIL instructions.
The following pattern is matched for both signed and unsigned variants:
```
SEXT/ZEXT(Low-Half-Lanes(vec)) << Imm
```
This covers the following instructions:
```
LSX: VSLLWIL.H.B, VSLLWIL.W.H, VSLLWIL.D.W
VSLLWIL.HU.BU, VSLLWIL.WU.HU, VSLLWIL.DU.WU
LASX: XVSLLWIL.H.B, XVSLLWIL.W.H, XVSLLWIL.D.W
XVSLLWIL.HU.BU, XVSLLWIL.WU.HU, XVSLLWIL.DU.WU
```
