LLVM/project 496da8d — llvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine icmp-zext-trunc-and.ll

[InstCombine] Fold icmp (zext X), (and (trunc Y), Mask) -> icmp X, trunc Y (#221189)

Fixes #115466

Alive2 proofs:
 (zext, and-mask):
1.ugt: https://alive2.llvm.org/ce/z/akAyDD
2. ult: https://alive2.llvm.org/ce/z/FBkBc1
3.uge: https://alive2.llvm.org/ce/z/-P4B3F
4.ule: https://alive2.llvm.org/ce/z/arHptc

 (and-mask, zext)
1.ugt: https://alive2.llvm.org/ce/z/M2n__t
2.ult: https://alive2.llvm.org/ce/z/6M8Maq
3.uge: https://alive2.llvm.org/ce/z/j99P_Q
4.ule: https://alive2.llvm.org/ce/z/5aaRny


Assisted by: Claude (Anthropic) used for debugging test
failures, and code review during development.
DeltaFile
+86-0llvm/test/Transforms/InstCombine/icmp-zext-trunc-and.ll
+19-0llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+105-02 files

LLVM/project d32a547 — llvm/include/llvm/CodeGen Passes.h, llvm/lib/CodeGen IndirectBrExpandPass.cpp

Reapply "[IndirectBrExpand] Preserve profile weights" (#229691) (#230224)

This reverts commit e699478b640736e11855041fda4e2902c0d0bb22. Includes
changes to only enable profile preservation at optimization levels
greater than -O0 which fixes the compile time regression reported in the
revert.
DeltaFile
+148-0llvm/test/Transforms/IndirectBrExpand/pgo.ll
+129-16llvm/lib/CodeGen/IndirectBrExpandPass.cpp
+4-1llvm/test/CodeGen/X86/opt-pipeline.ll
+1-1llvm/lib/Target/X86/X86TargetMachine.cpp
+1-1llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+1-1llvm/include/llvm/CodeGen/Passes.h
+284-201 files not shown
+284-217 files

FreeBSD/src 5bf7849 — sys/kern uipc_socket.c

socket: Remove the divert(4) socket compat shim again

Python in the ports tree now handles PF_DIVERT sockets properly; see
ports commit 4d84480d7a68.  I no longer have any specific reason to keep
the shim and Gleb wants to remove it, so, let's remove it.

This reverts commit cb7009867ae6b33aa39cb6cb1453b69073144b44.

Requested by:   glebius
Reviewed by:    glebius
Differential Revision:  https://reviews.freebsd.org/D60390
DeltaFile
+0-7sys/kern/uipc_socket.c
+0-71 files

LLVM/project 1553f22 — lldb/source/Plugins/TypeSystem/Clike CMakeLists.txt Identifier.cpp, lldb/unittests CMakeLists.txt

[lldb][Clike] Add IdentifierMap (#222663)

TypeSystemClike needs to store the name of structs, enums, member
variables and similar entities. In the old TypeSystemClang this
information was stored in Clang's IdentifierTable.

This patch introduces an equivalent for TypeSystemClike called
`IdentifierMap`. It turns strings into unique Identifier objects, which
for now directly store the StringRef to the value. The actual storage
of the string contents is either (A) in the IdentifierMap itself
or (B) backed by ConstString/constant memory for strings. Option B
exists mainly because we often already have a ConstString around that
already contains the respective string, and it avoids us having to
save a copy like with TypeSystemClang.

Some design questions where I just picked one option:

(a) Do we really need to deduplicate strings?


    [16 lines not shown]
DeltaFile
+65-0lldb/source/Plugins/TypeSystem/Clike/Identifier.h
+64-0lldb/unittests/TypeSystem/Clike/IdentifierTest.cpp
+49-0lldb/source/Plugins/TypeSystem/Clike/Identifier.cpp
+6-0lldb/unittests/TypeSystem/Clike/CMakeLists.txt
+1-0lldb/unittests/CMakeLists.txt
+1-0lldb/source/Plugins/TypeSystem/Clike/CMakeLists.txt
+186-01 files not shown
+187-07 files

FreeBSD/src 6b1d5fe — sys/netipsec key.c

netipsec: Fix V_spd_size updates

key_unregister_ifnet() was erroneously decrementing the size of the
global security policy database, V_sptree, but it doesn't modify that
database.  V_sptree_ifnet is for policies attached to if_ipsec
interfaces.  Note also that key_register_ifnet() was not incrementing
the counter.

Move the definition of V_spd_size up to the rest of the SPD definitions.
Its inclusion among the SPD cache definitions was confusing to me.

Reviewed by:    ae
Reported by:    Stephan de Wit and Cedrik Pischem from OPNsense
Sponsored by:   OPNsense
Sponsored by:   Klara, Inc.
MFC after:      2 weeks
Differential Revision:  https://reviews.freebsd.org/D60418
DeltaFile
+4-3sys/netipsec/key.c
+4-31 files

LLVM/project 493a990 — llvm/docs AMDGPUDMAOperations.md, llvm/include/llvm/IR IntrinsicsAMDGPU.td

[AMDGPU] Fix memory effects of tensor load/store intrinsics (#229728)

Tensor load/store intrinsics access global and LDS memory through
addresses encoded in integer vectors. Their memory effects are limited
to pointer arguments and inaccessible memory, which can let LLVM delete
needed stores or reuse stale loaded values.

Remove this restriction so LLVM accounts for their reads and writes to
ordinary memory.
DeltaFile
+47-0llvm/test/Transforms/GVN/AMDGPU/tensor-descriptor.ll
+44-0llvm/test/Transforms/DeadStoreElimination/AMDGPU/tensor-descriptor.ll
+4-0llvm/docs/AMDGPUDMAOperations.md
+1-1llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+2-0llvm/test/Transforms/DeadStoreElimination/AMDGPU/lit.local.cfg
+2-0llvm/test/Transforms/GVN/AMDGPU/lit.local.cfg
+100-16 files

LLVM/project 59afc84 — llvm/include/llvm/CodeGen LiveVariables.h, llvm/lib/CodeGen LiveVariables.cpp

LiveVariables: Only visit tracked physical registers

Keep a bitvector of physical registers with a recorded def or use in
the current block. Register mask handling, the end of block scan, and
the per-block reset now only visit those registers instead of every
register. This is significant for targets with many registers, such as
AMDGPU.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+19-8llvm/lib/CodeGen/LiveVariables.cpp
+3-0llvm/include/llvm/CodeGen/LiveVariables.h
+22-82 files

LLVM/project fe73243 — llvm/lib/CodeGen LiveIntervalUnion.cpp, llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp SelectionDAGISel.cpp

Remove SparseBitVector include
DeltaFile
+1-0llvm/lib/Target/X86/X86ISelLowering.cpp
+1-0llvm/lib/Target/VE/VETargetMachine.h
+1-0llvm/lib/Target/AMDGPU/SIFrameLowering.h
+1-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+1-0llvm/lib/CodeGen/LiveIntervalUnion.cpp
+6-03 files not shown
+8-19 files

LLVM/project 4e2af41 — llvm/include/llvm/CodeGen LiveVariables.h, llvm/lib/CodeGen LiveVariables.cpp

LiveVariables: Remove dead live-in handling and Defs plumbing

No physical register is tracked at the start of a block, so handling
the block live-ins was a no-op. The Defs list was only appended for
instruction defs, which runOnInstr already collects.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+9-24llvm/lib/CodeGen/LiveVariables.cpp
+3-5llvm/include/llvm/CodeGen/LiveVariables.h
+12-292 files

LLVM/project 6d2f78c — llvm/include/llvm/CodeGen LiveVariables.h, llvm/lib/CodeGen LiveVariables.cpp

CodeGen: Strip LiveVariables down to dead flag computation

This analysis is dead and there are no more explicit uses. There are still
passes implicitly relying on adjustments of dead flags. Missing dead
flags are added, and implicit-def operands are added for partially dead
physical registers.

The whole pass should be deleted, but it's taking a while to get all the dead
flag changes through the rest of the compiler. As a stop-gap to try to recover
some compile time regression, and avoiding new users appearing, strip the pass
down to only commputing the dead flags.

The main side effect of this is kill flags are no longer made accurate, which
is the source of the test churn.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+53-519llvm/lib/CodeGen/LiveVariables.cpp
+7-231llvm/include/llvm/CodeGen/LiveVariables.h
+34-34llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+0-64llvm/unittests/MI/LiveIntervalTest.cpp
+26-26llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
+16-16llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+136-89031 files not shown
+213-99737 files

FreeBSD/src 9543276 — sys/dev/usb usbdevs

usbdevs: Add ublox LARA-L6

The device has multiple PIDs as it supports different USB profiles.

Approved by:            adrian
MFC after:              3 days
Differential Revision:  https://reviews.freebsd.org/D60482
DeltaFile
+6-0sys/dev/usb/usbdevs
+6-01 files

OPNSense/plugins c836a89 — benchmarks/iperf/src/opnsense/mvc/app/views/OPNsense/iperf instance.volt client.volt, benchmarks/iperf/src/opnsense/scripts/iperf server.py client.py

Report bytes per second in the API and format with byteFormatter in the front end
DeltaFile
+6-2benchmarks/iperf/src/opnsense/mvc/app/views/OPNsense/iperf/instance.volt
+6-2benchmarks/iperf/src/opnsense/mvc/app/views/OPNsense/iperf/client.volt
+2-2benchmarks/iperf/src/opnsense/scripts/iperf/client.py
+1-1benchmarks/iperf/src/opnsense/scripts/iperf/server.py
+15-74 files

LLVM/project 254f05a — clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenBuiltin.cpp

[CIR] Added Vector Reduce Op (#226546)

Added cir.vec.reduce for vector reduction builtins supporting integer,
floating-point, bitwise and min/max reductions.

Used the operation for generic and x86 reduction builtins and preserved
expression FP options and merged builtin-required reassoc and nnan
flags.

Added CIR, verifier, lowering, fixed and scalable vector, boolean, FP16
and fast-math regression tests.
DeltaFile
+108-0clang/include/clang/CIR/Dialect/IR/CIROps.td
+56-51clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+99-0clang/test/CIR/CodeGenBuiltins/builtin-reduce-fast-math.c
+40-18clang/test/CIR/CodeGenBuiltins/builtin-reduce-arithmetic.c
+53-0clang/test/CIR/IR/invalid-vector-reduce.cir
+50-0clang/test/CIR/Lowering/vector-reduce.cir
+406-6911 files not shown
+649-14617 files

LLVM/project eb12512 — llvm/cmake/modules MLGOLower.cmake, llvm/include/llvm/Analysis/Utils MLGOUtils.h

[mlgo] Allow passing pre-emitc-ed models
DeltaFile
+79-58llvm/cmake/modules/MLGOLower.cmake
+98-0llvm/lib/Analysis/models/inline-oz-test-model.inc
+49-0llvm/lib/Analysis/models/regalloc-eviction-test-model.inc
+13-12llvm/lib/CodeGen/CMakeLists.txt
+13-12llvm/lib/Analysis/CMakeLists.txt
+9-13llvm/include/llvm/Analysis/Utils/MLGOUtils.h
+261-9520 files not shown
+323-20026 files

LLVM/project 3de9384 — llvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU ds-latency-mode-attr.mir perfhint-matrix-intrinsics.ll

Change handling and control

Change-Id: I7032fc47390396257ccc399c30c2cb52aa68f50d
DeltaFile
+116-0llvm/test/CodeGen/AMDGPU/perfhint-lds-contention.ll
+110-0llvm/test/CodeGen/AMDGPU/perfhint-matrix-intrinsics.ll
+90-3llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp
+38-37llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+16-26llvm/lib/Target/AMDGPU/SIInstrInfo.h
+4-21llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
+374-8720 files not shown
+463-9926 files

LLVM/project f853649 — llvm/test/CodeGen/AMDGPU coexec-sched-flavor-classification.mir coexec-sched-ds-fifo.mir

Rebase

Change-Id: I2629315a64ca3b49d07c5c38444a95027f875282
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+1-1llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+1-1llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
+5-53 files

LLVM/project df15fc7 — llvm/test/CodeGen/AMDGPU coexec-scheduler.ll coexec-sched-agpr-excess.mir

Fix lit

Change-Id: Id8c3f63acdce212f1030e5dfc7d9273c56945958
DeltaFile
+11-3llvm/test/CodeGen/AMDGPU/ds-latency-mode-flag.mir
+3-3llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
+0-4llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+2-2llvm/test/CodeGen/AMDGPU/coexec-sched-agpr-excess.mir
+16-124 files

LLVM/project 258416e — llvm/lib/Target/AMDGPU SIInstrInfo.cpp GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU ds-latency-mode-flag.mir ds-latency-mode-branch-cost.mir

[AMDGPU] Add DSLatencyMode flag + attr to control LDS latency

Change-Id: Ia5fee7983adffdb837ba2e876a64d805263b60c3
DeltaFile
+119-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-default-scheduler.mir
+74-10llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+59-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+61-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
+53-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-branch-cost.mir
+29-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-flag.mir
+395-128 files not shown
+436-2014 files

LLVM/project 6bfbbe0 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIInstrInfo.h

More documentation

Change-Id: I65ff1a1b605796d21a52766dcf04c64bc64aaa4e
DeltaFile
+21-6llvm/lib/Target/AMDGPU/SIInstrInfo.h
+1-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+22-72 files

OpenZFS/src 7391add — module/zfs ddt.c, tests/runfiles common.run

ddt: don't prune every unique entry for a target below one entry

A percentage prune rounds its target down to whole entries. When the
target is zero, for example 1% of a table with fewer than 100 unique
entries, the search for the oldest age bin to keep never runs, the
cutoff stays at the current time, and the walk prunes every unique
entry instead of none.

Return without pruning when the target is zero. dedup_prune_percentage
prunes 1% of three unique entries, which must keep all of them, and
then 100%, which must remove them.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Reviewed-by: Alexander Motin <alexander.motin at TrueNAS.com>
Signed-off-by: Kamil Monicz <kamil at monicz.dev>
Closes #19264
DeltaFile
+79-0tests/zfs-tests/tests/functional/dedup/dedup_prune_percentage.ksh
+2-1tests/runfiles/common.run
+3-0module/zfs/ddt.c
+1-0tests/zfs-tests/tests/Makefile.am
+85-14 files

LLVM/project 610abc7 — libc/src/dlfcn dladdr.h dladdr.cpp

[libc] Fix dladdr stub (#230227)

Previously the dladdr stub returned -1 on error, but dladdr should
return 0 on error, see:
https://pubs.opengroup.org/onlinepubs/9799919799/functions/dladdr.html
DeltaFile
+7-2libc/src/dlfcn/dladdr.cpp
+6-1libc/src/dlfcn/dladdr.h
+13-32 files

OPNSense/plugins 6102c50 — benchmarks/iperf +POST_INSTALL.pre, benchmarks/iperf/src/opnsense/mvc/app/controllers/OPNsense/iperf/Api ClientController.php

Lets keep client and server config and log inside /var/db/iperf
DeltaFile
+8-9benchmarks/iperf/src/opnsense/scripts/iperf/server.py
+3-2benchmarks/iperf/src/opnsense/mvc/app/controllers/OPNsense/iperf/Api/ClientController.php
+5-0benchmarks/iperf/+POST_INSTALL.pre
+2-2benchmarks/iperf/src/opnsense/scripts/iperf/client.py
+18-134 files

NetBSD/pkgsrc U6kKvG6 — doc CHANGES-2026

   doc: Updated shells/oksh to 7.9
VersionDeltaFile
1.6810+2-1doc/CHANGES-2026
+2-11 files

LLVM/project fd842aa — llvm/test/CodeGen/AMDGPU coexec-sched-flavor-classification.mir

Precommit test change

Change-Id: Id3546e1492a335f48cf70d9b0e93afe22b31ff7a
DeltaFile
+6-10llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+6-101 files

LLVM/project 7e6f964 — llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-sched-flavor-classification.mir llvm.amdgcn.sched.group.barrier.gfx12.ll

[AMDGPU] Use instrLatency for memory HWUI cycle accounting

Change-Id: I7a9e2deb5db7638d6f735570e65d6ca988a7477f
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
+3-3llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+2-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+9-83 files

LLVM/project 33802a6 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.sched.group.barrier.gfx12.ll coexec-sched-flavor-classification.mir

Rebase

Change-Id: I57aa4243360b919077eabc49d66108da4279b660
DeltaFile
+10-2llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
+14-62 files

LLVM/project 9f926a2 — llvm/test/CodeGen/AMDGPU coexec-sched-flavor-classification.mir

Fix lit

Change-Id: Ia53e8f2317d4db93dcd87a616ae774137b8c0572
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+1-11 files

NetBSD/pkgsrc ng7Tyym — shells/oksh Makefile distinfo

   oksh: update to 7.9

   synced with OpenBSD's release
VersionDeltaFile
1.14+4-4shells/oksh/distinfo
1.15+2-2shells/oksh/Makefile
+6-62 files

LLVM/project 8b46d77 — llvm/lib/Passes PassesOptions.cpp PassesOptions.h, utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[Passes] Declare command line options in TableGen (#230020)

Move the LLVMPasses cl::opts into a private PassesOptions struct
(lib/Passes/PassesOptions.td). PassBuilder holds
`const PassesOptions &Opts`, forward-declared in PassBuilder.h.

-force-new-pm-codegen and -verify-analysis-invalidation become
BoolOrDefault members; the latter defaults to on with EXPENSIVE_CHECKS.
DotCfgChangeReporter keeps the expanded -dot-cfg-dir in a new OutputDir
member instead of writing it back to the option.

-print-{before,after}-pass-number (cl::list) and -print-pipeline-passes
(custom parser) stay cl::opt.

Aided by Opus 5.5
DeltaFile
+69-231llvm/lib/Passes/PassBuilderPipelines.cpp
+71-139llvm/lib/Passes/StandardInstrumentations.cpp
+150-0llvm/lib/Passes/PassesOptions.td
+18-0llvm/lib/Passes/PassesOptions.h
+15-0llvm/lib/Passes/PassesOptions.cpp
+12-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+335-3706 files not shown
+365-38212 files

LLVM/project bc74df3 — llvm/include/llvm/IR RuntimeLibcalls.td, llvm/test/CodeGen/AArch64 sincos-f128.ll

RuntimeLibcalls: Only provide fp128 sincosl when long double is fp128

LibmHasSinCosF128 provided sincosl for any target with sincos, so
llvm.sincos.f128 called sincosl on aarch64 MinGW and hexagon-*-gnu,
where long double is double. Require fp128 long double, and rename it
to LibmHasSincoslF128 to distinguish it from sincosf128.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+438-0llvm/test/Transforms/Util/DeclareRuntimeLibcalls/hexagon.ll
+31-0llvm/test/CodeGen/AArch64/sincos-f128.ll
+7-6llvm/include/llvm/IR/RuntimeLibcalls.td
+9-0llvm/test/CodeGen/Hexagon/llvm.sincos.f128.ll
+0-1llvm/test/Transforms/Util/DeclareRuntimeLibcalls/aarch64.ll
+485-75 files