LLVM/project e2a9335 — mlir/include/mlir/Dialect/GPU/IR GPUDialect.h, mlir/include/mlir/Dialect/MemRef/IR MemRef.h

[mlir][NFC] Remove includes of headers declaring used traits and interfaces (#240404)

The generated declarations of ops, attributes, types and interfaces now
include the headers declaring the core traits and interfaces they use.
Includes that headers only had for these generated declarations are
therefore redundant. This removes them in MLIR, Flang and ClangIR.

Includes of headers that the hand-written code uses directly are kept,
even when the generated code includes them as well.

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+0-11mlir/include/mlir/Dialect/MemRef/IR/MemRef.h
+0-10mlir/test/lib/Dialect/Test/TestOps.h
+0-9mlir/include/mlir/Dialect/Vector/IR/VectorOps.h
+1-8mlir/include/mlir/Dialect/SCF/IR/SCF.h
+0-8mlir/include/mlir/Dialect/Tensor/IR/Tensor.h
+0-8mlir/include/mlir/Dialect/GPU/IR/GPUDialect.h
+1-5465 files not shown
+1-26671 files

LLVM/project fd626bb — lldb/test/API/commands/dwim-print TestDWIMPrint.py

fixup! [lldb][test] Build PDB test inferiors with column info
DeltaFile
+0-1lldb/test/API/commands/dwim-print/TestDWIMPrint.py
+0-11 files

LLVM/project dff6968 — clang/lib/CIR/CodeGen CIRGenExprScalar.cpp, clang/test/CIR/CodeGen vector-ext.cpp vector.cpp

[CIR] Use `cir.vec.fcmp` op for logical comparisons (#239706)
DeltaFile
+26-6clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+6-6clang/test/CIR/CodeGen/vector-logical-long-double.cpp
+5-5clang/test/CIR/CodeGen/vector.cpp
+5-5clang/test/CIR/CodeGen/vector-strict-fp.cpp
+4-4clang/test/CIR/CodeGen/vector-ext.cpp
+46-265 files

LLVM/project f3c1281 — clang/lib/CodeGen CodeGenFunction.h CGAtomic.cpp, clang/test/OpenMP amdgpu-unsafe-fp-atomics.cpp target_atomic_device_scope.cpp

[OpenMP] Use device scope for atomic constructs on the device

OpenMP 6.0, 17.8.5 specifies that "The memscope clause determines the
binding thread set for an atomic region. If the memscope clause is not
present, the behavior is as if the memscope clause appeared on the
construct with the device scope-specifier."

Thread the sync scopes through codegen amd also add a release note
because this is changing existing behavior.
Existing behavior was overly cautios for OpenMP 5.2, too, though. The
atomic construct never specified the option of having system-level
scope. This only came with the memscope clause and it's "all"
scope-specifier.

Claude assisted with this patch.
DeltaFile
+130-0clang/test/OpenMP/target_atomic_device_scope.cpp
+24-9clang/lib/CodeGen/CGStmtOpenMP.cpp
+16-11clang/lib/CodeGen/CGAtomic.cpp
+11-10llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+8-8clang/test/OpenMP/amdgpu-unsafe-fp-atomics.cpp
+6-3clang/lib/CodeGen/CodeGenFunction.h
+195-413 files not shown
+205-459 files

LLVM/project 1ae7bb5 — mlir/include/mlir/Dialect/XeGPU/uArch uArchBase.h, mlir/test/Dialect/XeGPU propagate-layout-inst-data.mlir peephole-optimize.mlir

[MLIR][XeGPU] Limit transposed 2D block load height to 16 (#239469)

The hardware supports transposed 2D block loads with height 16 or 32,
but a 32-row tile does not align with the DPAS layout. Limit the
8/16/32-bit transposed block load entries in the uArch table to height
16.

Layout propagation now falls back to inst_data [16, 8] for a transposed
i32 load whose consumer asks for 32 rows, and the peephole optimizer
splits 32-row transposed loads into two 16-row loads.

Add a propagate-layout-inst-data test covering the fallback, and update
the peephole-optimize CHECK lines for the split loads.

assisted-by-claude

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+51-22mlir/test/Dialect/XeGPU/peephole-optimize.mlir
+22-0mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
+5-3mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h
+78-253 files

NetBSD/pkgsrc-wip faa0c01 — burp Makefile

Forgot a PKG_SYSCONFDIR used within manpages.
DeltaFile
+3-1burp/Makefile
+3-11 files

LLVM/project f8ff80a — clang/lib/CodeGen CGStmtOpenMP.cpp, clang/test/OpenMP amdgpu-unsafe-fp-atomics.cpp

[OpenMP][clang] Apply atomic options to atomic compare

Thread denormal mode, fine-grained memory and remote memory options
through for atomic compare directivs.

Claude assisted with this patch.
DeltaFile
+26-14llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+40-0clang/test/OpenMP/amdgpu-unsafe-fp-atomics.cpp
+10-2llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+10-2clang/lib/CodeGen/CGStmtOpenMP.cpp
+86-184 files

LLVM/project 6ae787b — clang/include/clang/Lex ModuleMap.h, clang/lib/Lex ModuleMap.cpp

[clang][Lex][NFC] Remove unused ShadowModules (#239938)

`ModulesAlloc` manages module lifetimes, making `ShadowModules`
redundant.
DeltaFile
+0-3clang/include/clang/Lex/ModuleMap.h
+0-1clang/lib/Lex/ModuleMap.cpp
+0-42 files

LLVM/project a182f80 — llvm/lib/Target/AMDGPU SIFoldOperands.cpp

[AMDGPU] Remove V_CNDMASK_B64_PSEUDO handling from SIFoldOperands. NFC. (#240324)

This is dead because the pseudo always gets expanded earlier, and broken
because it would have used V_MOV_B32 to move a 64-bit value.
DeltaFile
+1-2llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+1-21 files

NetBSD/pkgsrc-wip 1863e58 — trafficserver distinfo, trafficserver/patches patch-tsmemcache.cc patch-swoc_file.h

trafficserver: Add logic to check if NetBSD's accept filter is loaded

Also cleanup other patch files per pkgsrc guide.
DeltaFile
+26-24trafficserver/patches/patch-Server.cc
+0-18trafficserver/patches/patch-ink_inet.cc
+5-6trafficserver/distinfo
+4-5trafficserver/patches/patch-DbgCtl.h
+3-3trafficserver/patches/patch-swoc_file.h
+2-2trafficserver/patches/patch-tsmemcache.cc
+40-581 files not shown
+41-597 files

FreeBSD/src 488bf44 — sys/netipsec key.c

netipsec: Do not leak the SAH when an SA is cloned

key_updateaddresses() gives the clone of an SA a new SAH reference when
the SA index comes from key_newsah() or key_getsah(), but nothing
releases the reference of the old SA: key_delsav() leaves the SAH alone,
because key_unlinksav() normally releases it, and an SA that is replaced
never goes through that.  The SAH then stays allocated for good, after
its SAs are flushed and after the vnet is destroyed, as an SADB_UPDATE
with a new address does each time an IKE daemon moves an SA.

The old SA cannot release the reference when it is replaced, since a
sender that still holds it reads its SAH.  Release it in key_delsav()
instead.  When only the NAT-T config changes, the clone used to take over
the reference of the old SA; take a new one in that case as well, so that
every SA holds its own.

Reviewed by:            kib, markj
MFC after:              1 week
Sponsored by:           Rubicon Communications, LLC ("Netgate")
Differential Revision:  https://reviews.freebsd.org/D61101
DeltaFile
+7-3sys/netipsec/key.c
+7-31 files

LLVM/project 5f4db49 — libc/src/__support/threads thread.h, libc/src/__support/threads/linux futex_utils.h thread.cpp

[libc] Apply scheduler attributes on thread creation (#225674)

POSIX specifies that pthread_create should apply the scheduling policy
and parameters given in the attributes object (if PTHREAD_EXPLICIT_SCHED
is set). Linux's clone syscall doesn't support setting scheduling
parameters directly, so we have to apply them from userspace via
sched_setscheduler after the thread is created.

To make sure the thread doesn't start running user code with the wrong
scheduling parameters (and to allow returning an error if
sched_setscheduler fails without leaving a half-running thread), I've
added a startup handshake using the clear_tid futex on the child stack:
- the child waits on the futex if explicit scheduling was requested
- the parent calls setschedparam, and then signals the child to either
continue (running) or abort (exit)
- if the call fails, the child exits immediately, the parent reaps it
via Thread::wait(), and returns the error code to the caller

Assisted-by: Gemini
DeltaFile
+234-0libc/test/integration/src/pthread/pthread_create_test.cpp
+53-9libc/src/__support/threads/linux/thread.cpp
+22-0libc/src/__support/threads/linux/futex_utils.h
+16-2libc/src/pthread/pthread_create.cpp
+6-4libc/src/__support/threads/thread.h
+7-0libc/test/integration/src/pthread/CMakeLists.txt
+338-152 files not shown
+340-158 files

LLVM/project 41e035a — clang/docs ReleaseNotes.md, clang/lib/CodeGen CGStmtOpenMP.cpp

[OpenMP][clang] Add ompx_fast_fp_atomics and ompx_safe_fp_atomics hints

Add omp_sync_hint_t extensions that override
-f[no-]atomic-ignore-denormal-mode (-m[no-]unsafe-fp-atomics) for a single
atomic construct. The safe hint takes precedence if both are given.

This is an upstreaming/copy-paste of downstream code and release notes.

Claude assisted with this patch.
DeltaFile
+71-0clang/test/OpenMP/amdgpu-unsafe-fp-atomics.cpp
+20-0clang/lib/CodeGen/CGStmtOpenMP.cpp
+4-1openmp/runtime/src/include/omp.h.var
+4-0clang/docs/ReleaseNotes.md
+99-14 files

LLVM/project 98d77d7 — libc/src/__support checked_ptr.h, libc/src/__support/regex regex_parser.cpp regex_expr_pool.h

[libc] Use CheckedPtr/make_unique in the regex code (#238366)

The regex code was written before we had unique_ptr, and so it did all
of its memory management by hand (AllocChecker + new/delete, with
scope_exit guards for the error paths). This replaces that with
make_unique, and stores the results in cpp::unique_ptr members.

Specific changes:
- ExprPool now holds its blocks, byte sets and hash table in
unique_ptr<T[]> members, which means the destructor can be defaulted.
Since unique_ptr does not know the size of the array, the capacity of
each array is now tracked in a separate field (previously it was implied
by the span size).
- make_unique<T[]> value-initializes the array, so the explicit
inline_memset of the hash table is gone.
- ParsedAtomStack and regcomp no longer need scope guards to clean up on
the error paths.

regfree still does a plain delete, as regex_t::__internal is a void

    [18 lines not shown]
DeltaFile
+36-66libc/src/__support/regex/regex_expr_pool.cpp
+101-1libc/test/src/__support/checked_ptr_test.cpp
+50-1libc/src/__support/checked_ptr.h
+22-19libc/src/__support/regex/regex_expr_pool.h
+17-18libc/src/__support/regex/regex_parser.cpp
+4-12libc/src/regex/regcomp.cpp
+230-1173 files not shown
+235-1299 files

LLVM/project acd549a — llvm/lib/Analysis InstructionSimplify.cpp, llvm/lib/Transforms/InstCombine InstCombineCalls.cpp

[InstCombine] Simplify `llvm.vector.shuffle` with constant or length 1 mask (#240231)

When a dynamic shuffle has a mask that can is const, it can lower to a
`shufflevector` instruction which is faster on some architectures (and
has real codegen lowering until
https://github.com/llvm/llvm-project/pull/240222 and friends all merge).
DeltaFile
+152-0llvm/test/Transforms/InstCombine/vector-shuffle.ll
+63-0llvm/test/Transforms/InstSimplify/vector-shuffle.ll
+32-0llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+9-0llvm/lib/Analysis/InstructionSimplify.cpp
+256-04 files

LLVM/project 463f518 — flang/test/Integration/OpenMP dispatch.f90

[flang][OpenMP] Add explicit triple to test (NFC) (#240298)

To avoid ABI differences across targets. This is irrelevant to the
purpose of the test.

Fixup for https://github.com/llvm/llvm-project/pull/227954 to fix a test
failure on s390x.
DeltaFile
+1-1flang/test/Integration/OpenMP/dispatch.f90
+1-11 files

LLVM/project bb14f83 — lldb/packages/Python/lldbsuite/test/make Makefile.rules, lldb/test/API/lang/cpp/break-on-initializers TestBreakOnCPP11Initializers.py

[lldb][test] Build PDB test inferiors with column info
DeltaFile
+1-1lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+0-1lldb/test/API/lang/cpp/structured-binding/TestStructuredBinding.py
+0-1lldb/test/API/lang/cpp/step-through-trampoline/TestStepThroughTrampoline.py
+0-1lldb/test/API/lang/cpp/break-on-initializers/TestBreakOnCPP11Initializers.py
+1-44 files

LLVM/project a89b48d — lldb/source/Plugins/SymbolFile/NativePDB SymbolFileNativePDB.cpp, lldb/test/API/functionalities/breakpoint/breakpoint_by_line_and_column TestBreakpointByLineAndColumn.py

[lldb][NativePDB] Read the columns of line tables (#238603)

A CodeView line table has a column entry for every line entry when it
was emitted with columns (`DebugLinesHasColumns`, clang's
`-gcolumn-info`). `ParseLineTable` ignores them and gives every entry
column 0, so breakpoints by line and column can't resolve and stop
locations never show a column.

This patch takes the start column of each line entry from the column
entries when there are as many of them as line entries.

Fixes `TestBreakpointByLineAndColumn` (whose Makefile already passes
`-gcolumn-info`) with PDB debug info.

rdar://191741255
DeltaFile
+21-0lldb/test/Shell/SymbolFile/NativePDB/line-table-columns.cpp
+6-3lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
+0-3lldb/test/API/functionalities/breakpoint/breakpoint_by_line_and_column/TestBreakpointByLineAndColumn.py
+27-63 files

NetBSD/pkgsrc-wip 93a1ad3 — burp Makefile, burp/patches patch-configs_server_summary__script.in patch-configs_certs_CA_CA.cnf.in

Get rid of a few patches, using the subst framework instead.
DeltaFile
+0-93burp/patches/patch-configs_server_burp.conf.in
+0-34burp/patches/patch-configs_client_burp.conf.in
+0-13burp/patches/patch-configs_certs_CA_burp__ca.in
+0-12burp/patches/patch-configs_certs_CA_CA.cnf.in
+0-11burp/patches/patch-configs_server_summary__script.in
+4-5burp/Makefile
+4-1681 files not shown
+4-1737 files

LLVM/project 750ec02 — llvm/lib/Target/Hexagon HexagonOptAddrMode.cpp

Hexagon: Fix HexagonOptAddrMode::processAddBases losing Changed (#240397)

processAddBases could rewrite one addi via updateAddBases and then
return false when a later addi in the list failed the usedInLoadStore
check. If nothing else changed, runOnMachineFunction then skipped
Liveness::resetKills, leaving stale kill flags. This was previously
hidden by the clearKillFlags call in updateAddBases removed in #239894,
and caused CodeGen/Hexagon/autohvx/addi-offset-opt-addr-mode.ll to fail
machine verification in EXPENSIVE_CHECKS builds.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+3-4llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+3-41 files

LLVM/project bf4167b — llvm/docs AMDGPUUsage.md, llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp

[AMDGPU] Warn about missing async barrier replay workarounds

Warn by default when assembly lacks the recognized EXEC-zero B8 replay
after an async barrier arrival. Keep recognition within a straight-line
assembly block and support targeted and general warning controls.

DeltaFile
+187-0llvm/test/MC/AMDGPU/async-barrier-replay-warning.s
+81-0llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+38-0llvm/test/MC/AMDGPU/async-barrier-replay-warning-vgpr-msb.s
+28-0llvm/docs/AMDGPUUsage.md
+27-0llvm/test/MC/AMDGPU/async-barrier-replay-warning-xnack.s
+24-0llvm/test/CodeGen/AMDGPU/async-barrier-replay-inline-asm.ll
+385-02 files not shown
+393-38 files

LLVM/project 17aba91 — clang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp, clang/test/CIR/Transforms/abi-lowering amdgpu-byref.cir indirect-byval.cir

[CIR][AMDGPU] Look through address_space views when forwarding indirect args (#239158)

Summary:

- `CIRGen` loads AMDGPU locals through an `address_space` cast of their
addrspace(5) `alloca`.
- `forwardableIndirectLoad` required the load address to have the
parameter's type, so a `byref` argument was copied into a fresh slot
instead of passing the `alloca`.
- Now pass the `alloca` instead of copying into a new `byref` slot.
- `forwardableIndirectLoad` becomes `forwardableIndirectAddr` and
returns the cast's source when it has the parameter's type.

Relates to: https://github.com/llvm/llvm-project/issues/220471

Assisted by: claude opus 5.5
DeltaFile
+29-20clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+47-0clang/test/CIR/Transforms/abi-lowering/indirect-non-byval-forward-param.cir
+0-45clang/test/CIR/Transforms/abi-lowering/indirect-non-byval-nyi.cir
+9-11clang/test/CIR/Transforms/abi-lowering/indirect-byval.cir
+16-0clang/test/CIR/Transforms/abi-lowering/amdgpu-byref.cir
+101-765 files

LLVM/project d661328 — llvm/lib/Transforms/Utils SimplifyCFG.cpp

[SimplifyCFG] Fix and improve a bunch of comments around `simplifyEqualityComparisonWithOnlyPredecessor` (NFC) (#240286)
DeltaFile
+29-24llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+29-241 files

LLVM/project b121d10 — lldb/source/Plugins/SymbolFile/NativePDB SymbolFileNativePDB.cpp

switch to std::enumerate
DeltaFile
+2-5lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
+2-51 files

OPNSense/core 92ee1fd — src/opnsense/mvc/app/controllers/OPNsense/Base ApiControllerBase.php

mvc:ApiControllerBase - increase server sent events limit to 15, browser seems to lock at 7, but in general we don't want to deplete our resource pool with streams (current max processes is 40).
DeltaFile
+1-1src/opnsense/mvc/app/controllers/OPNsense/Base/ApiControllerBase.php
+1-11 files

NetBSD/pkgsrc KXEH6HD — doc CHANGES-2026

   Updated multimedia/gstreamer1
VersionDeltaFile
1.7871+2-1doc/CHANGES-2026
+2-11 files

LLVM/project 3e3ca05 — llvm/lib/CodeGen/SelectionDAG CMakeLists.txt LegalizeTypes.cpp

[SelectionDAG] Declare command line options in TableGen (Part 1) (#240033)

First patch for SelectionDAG lib - DAGCombiner and LegalizeType
DeltaFile
+54-92llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+47-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGOptions.td
+15-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGOptions.h
+15-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGOptions.cpp
+6-5llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+7-0llvm/lib/CodeGen/SelectionDAG/CMakeLists.txt
+144-971 files not shown
+147-977 files

LLVM/project 50b520f — mlir/lib/Dialect/SPIRV/Transforms SPIRVConversion.cpp

[mlir][spirv] Fix invalid placeholder in FuncOpVectorUnroll (#240370)

FuncOpVectorUnroll uses an arith.constant from getZeroAttr as a
placeholder for each argument it does not unroll. Since #238629,
getZeroAttr returns null for types such as tensor<8x8xvector<4xi8>>,
so the pattern builds an arith.constant with no value. The greedy driver
erases the dead placeholder later, but expensive checks verify the IR
right after the pattern and fail:

  error: 'arith.constant' op requires attribute 'value'

The placeholder's value is never read. Use a zero-operand
unrealized_conversion_cast instead, which works for any type.
func-signature-vector-unroll.mlir already covers this case.

Fixes https://lab.llvm.org/buildbot/#/builders/241/builds/1796
DeltaFile
+6-4mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
+6-41 files

LLVM/project 29cd49b — llvm/test/CodeGen/AArch64 build-vector-extract.ll aarch64-neon-vector-insert-uaddlv.ll

Update Test Checks
DeltaFile
+644-665llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+169-90llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
+13-17llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
+1-3llvm/test/CodeGen/AArch64/build-vector-extract.ll
+827-7754 files

LLVM/project 893d7d8 — llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 shuffle-insert-zero.ll

[AArch64][DAG] Improve codegen for clearing upper vector lanes

Add patterns that use scalar fmov instruction to clear the upper lanes of a vector
DeltaFile
+305-16llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
+69-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+374-162 files