NextBSD/src 2b251af — . README.md, .github/workflows build.yml

T9+T11+T7: rename job, stop the ISO dispatch/schedule, redux sweep, harness v0.3.5

- T9 (nextbsd-ci#11): `name: ci` -> `Build NextBSD ISO/IMG` (the only generic
  name left in the org).
- T11 (nextbsd-ci#13): remove the `repository_dispatch` (ISO) trigger and the
  nightly `schedule`, and the `repository_dispatch` branch in the release
  `if`. ISO is the expensive one (qemu, live boot, ISO boot test); the cheap
  components it re-validated are all gated upstream (kernel continuous on
  push, userland on push per T10, pkg manual-only), so the cascade had no
  unique value. `workflow_dispatch` (manual ISO + release) and `pull_request`
  (PR img lane) remain; img-test and release now fire on `pull_request` or
  manual.
- T7 (nextbsd-ci#7): README `nextbsd-redux` -> `nextbsd`.
- Lockstep: harness pin v0.3.4 -> v0.3.5 (the T8 flake fixes: nextbsd#428
  end-state hold, nextbsd#503 teardown, nextbsd#405 marker protocol).
DeltaFile
+26-35.github/workflows/build.yml
+4-4README.md
+1-1tests/iso-boot-test.sh
+1-1tests/img-boot-test.sh
+32-414 files

FreeNAS/freenas 72dade2 — src/middlewared/middlewared/plugins/cloud crud.py, tests/cloud test_cloud_backup.py

Do not crash updating cloud backup task whose source path is a zvol and whose "Take Snapshot" option is enabled
DeltaFile
+18-0tests/cloud/test_cloud_backup.py
+1-1src/middlewared/middlewared/plugins/cloud/crud.py
+19-12 files

LLVM/project 6169f98 — lldb/include/lldb/Host/common NativeThreadProtocol.h, lldb/source/Plugins/Process/Windows/Common NativeThreadWindows.cpp

[lldb-server] Handle jThreadExtendedInfo
DeltaFile
+51-0lldb/test/API/tools/lldb-server/TestGdbRemote_jThreadExtendedInfo.py
+49-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+42-0lldb/test/API/windows/thread-extended-info/TestThreadExtendedInfo.py
+4-0lldb/source/Plugins/Process/Windows/Common/NativeThreadWindows.cpp
+3-0lldb/include/lldb/Host/common/NativeThreadProtocol.h
+3-0lldb/test/API/windows/thread-extended-info/Makefile
+152-05 files not shown
+162-011 files

LLVM/project ff2013a — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.768bit.ll amdgcn.bitcast.832bit.ll

Merge branch 'main' into users/aokblast/gvn/give_access_a_chance
DeltaFile
+84,649-104,050llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+23,473-29,275llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+16,802-20,458llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+15,510-18,987llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+14,281-17,622llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+12,111-15,454llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+166,826-205,8467,408 files not shown
+515,763-483,7937,414 files

LLVM/project 8d89b66 — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.768bit.ll amdgcn.bitcast.832bit.ll

Merge branch 'main' into users/aokblast/lldb/add_dap_timeout
DeltaFile
+84,649-104,050llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+23,473-29,275llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+16,802-20,458llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+15,510-18,987llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+14,281-17,622llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+12,111-15,454llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+166,826-205,8467,408 files not shown
+515,763-483,7937,414 files

LLVM/project 2771c75 — llvm/lib/Target/X86 X86CmovConversion.cpp X86InstrInfo.cpp, llvm/lib/Target/X86/MCTargetDesc X86AsmBackend.cpp

[X86] Declare command line options in TableGen (#228327)

Move the cl::opts of X86CodeGen into X86Options.td, following Sparc
(#227977): X86Subtarget.h declares the struct, LLVMInitializeX86Target
registers it, and code reads Subtarget.getCLOpts().

Move those of X86Desc and X86AsmParser into
MCTargetDesc/X86MCOptions.td, registered by LLVMInitializeX86TargetMC().
X86AsmBackend and X86AsmParser hold `const X86MCOptions &CLOpts`.
-x86-align-branch becomes a string that X86AsmBackend parses.

Options that read cl::opt::getNumOccurrences() become std::optional
members.

Aided by Opus 5.5
DeltaFile
+188-0llvm/lib/Target/X86/X86Options.td
+21-64llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+11-69llvm/lib/Target/X86/X86ISelLowering.cpp
+17-60llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+15-43llvm/lib/Target/X86/X86InstrInfo.cpp
+19-35llvm/lib/Target/X86/X86CmovConversion.cpp
+271-27135 files not shown
+495-55641 files

LLVM/project 129a566 — llvm/test/Transforms/InstCombine bitinsert-bitextract.ll

[InstCombine] Pre-commit tests for full-width `bitinsert`/`bitextract`
DeltaFile
+152-0llvm/test/Transforms/InstCombine/bitinsert-bitextract.ll
+152-01 files

LLVM/project 28901d1 — llvm/lib/Transforms/InstCombine InstCombineInternal.h InstructionCombining.cpp, llvm/test/Transforms/InstCombine bitinsert-bitextract.ll

[InstCombine] Fold full-width `bitinsert` and `bitextract` to `bitcast`
DeltaFile
+31-0llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+8-10llvm/test/Transforms/InstCombine/bitinsert-bitextract.ll
+2-0llvm/lib/Transforms/InstCombine/InstCombineInternal.h
+41-103 files

LLVM/project fc5e600 — llvm/include/llvm/Analysis InstSimplifyFolder.h InstructionSimplify.h, llvm/include/llvm/IR PatternMatch.h

[InstSimplify] Simplify `bitinsert` and `bitextract`
DeltaFile
+89-0llvm/lib/Analysis/InstructionSimplify.cpp
+18-43llvm/test/Transforms/InstSimplify/bitinsert-bitextract.ll
+29-0llvm/unittests/IR/PatternMatch.cpp
+15-0llvm/include/llvm/IR/PatternMatch.h
+8-0llvm/include/llvm/Analysis/InstructionSimplify.h
+2-4llvm/include/llvm/Analysis/InstSimplifyFolder.h
+161-476 files

LLVM/project 79d3629 — llvm/test/Transforms/InstSimplify bitinsert-bitextract.ll

[InstSimplify] Pre-commit tests for `bitinsert` and `bitextract`




DeltaFile
+331-0llvm/test/Transforms/InstSimplify/bitinsert-bitextract.ll
+331-01 files

LLVM/project 59c1294 — llvm/test/Transforms/GVN byte-conversion.ll

[GVN] Pre-commit tests for byte conversions

DeltaFile
+278-0llvm/test/Transforms/GVN/byte-conversion.ll
+278-01 files

LLVM/project 8875b3e — llvm/lib/Transforms/Utils VNCoercion.cpp, llvm/test/Transforms/GVN byte-conversion.ll

[GVN] Don't coerce forwarded byte values through integers

DeltaFile
+46-90llvm/test/Transforms/GVN/byte-conversion.ll
+25-6llvm/lib/Transforms/Utils/VNCoercion.cpp
+71-962 files

LLVM/project e82bf1f — llvm/include/llvm/Analysis TargetFolder.h, llvm/include/llvm/IR ConstantFolder.h ConstantFold.h

[ConstantFolding] Fold `bitinsert` and `bitextract`



DeltaFile
+31-62llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+83-0llvm/lib/IR/ConstantFold.cpp
+14-0llvm/include/llvm/IR/ConstantFold.h
+9-2llvm/include/llvm/IR/ConstantFolder.h
+9-0llvm/include/llvm/Analysis/TargetFolder.h
+5-0llvm/lib/Analysis/ConstantFolding.cpp
+151-646 files

LLVM/project d19f52d — llvm/include/llvm/Analysis ConstantFolding.h, llvm/include/llvm/IR ConstantFolder.h ConstantFold.h

[ConstantFolding] Make `bitinsert`/`bitextract` folding DL-aware
DeltaFile
+83-3llvm/lib/Analysis/ConstantFolding.cpp
+0-83llvm/lib/IR/ConstantFold.cpp
+0-14llvm/include/llvm/IR/ConstantFold.h
+14-0llvm/include/llvm/Analysis/ConstantFolding.h
+10-2llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+2-9llvm/include/llvm/IR/ConstantFolder.h
+109-1111 files not shown
+111-1137 files

LLVM/project 17b95e5 — llvm/test/Transforms/InstSimplify/ConstProp bitinsert-bitextract.ll

[ConstantFolding] Pre-commit tests for `bitinsert`/`bitextract` folding



DeltaFile
+403-0llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+403-01 files

LLVM/project d74a488 — llvm/lib/Target/AMDGPU AMDGPURegBankLegalize.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-anyext.mir regbankselect-mui.mir

[AMDGPU][GlobalISel] Keep typed LLTs in RegBankLegalize combines (#227476)

The S1 cleanup combines in AMDGPURegBankLegalize built new registers
with an untyped s32, but missed when lowering switched to extended LLTs.
The regbank combiner later unified these with typed registers, so
constrainRegAttrs retyped e.g. an i32 G_CTPOP result to s32, which
failed instruction selection.

Take the type from the source or destination register instead.

Assisted by: Claude Code
DeltaFile
+86-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-combine-s1.mir
+7-6llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+7-6llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
+5-4llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
+107-185 files

FreeNAS/freenas a00037b — src/middlewared/middlewared/plugins/webshare sharing.py, src/middlewared/middlewared/test/integration/assets webshare.py

NAS-144150 / 27.0.0 / Ensure that WebShare shares paths do not overlap (by themylogin) (#19944)

Original PR: https://github.com/truenas/middleware/pull/19938

---------

Co-authored-by: themylogin <themylogin at gmail.com>
DeltaFile
+157-0tests/api2/test_webshare_sharing.py
+53-82tests/api2/test_webshare_homedir.py
+35-1src/middlewared/middlewared/plugins/webshare/sharing.py
+17-0src/middlewared/middlewared/test/integration/assets/webshare.py
+262-834 files

LLVM/project e9c7db2 — lldb/docs/resources formatterbytecode.md, lldb/examples/python formatter_bytecode.py

[lldb] Add three more formatter bytecode selectors (#224773)
DeltaFile
+34-31lldb/docs/resources/formatterbytecode.md
+32-0lldb/source/DataFormatters/FormatterBytecode.cpp
+18-0lldb/examples/python/formatter_bytecode.py
+3-0lldb/include/lldb/DataFormatters/FormatterBytecode.def
+87-314 files

LLVM/project 9c3d8dd — libc/src/__support/math powf_double_eval.h

[libc][math] Fix unused variables and functions for powf_double_eval with GPU builds. (#229159)

Fixes https://lab.llvm.org/buildbot/#/builders/10/builds/36988
DeltaFile
+15-3libc/src/__support/math/powf_double_eval.h
+15-31 files

FreeNAS/freenas 6ff1e02 — src/middlewared/middlewared/plugins/webshare sharing.py, src/middlewared/middlewared/test/integration/assets webshare.py

ruff

(cherry picked from commit 6869f21880b809b44ba652c8828f6fc1219c312a)
DeltaFile
+63-55tests/api2/test_webshare_sharing.py
+48-33tests/api2/test_webshare_homedir.py
+7-3src/middlewared/middlewared/plugins/webshare/sharing.py
+1-5src/middlewared/middlewared/test/integration/assets/webshare.py
+119-964 files

FreeNAS/freenas 67fd777 — src/middlewared/middlewared/alembic/versions/27.0 2026-10-05_12-00_rsync_extra_json_list.py, src/middlewared/middlewared/plugins rsync.py

Store rsync extra args as list
DeltaFile
+66-0src/middlewared/middlewared/alembic/versions/27.0/2026-10-05_12-00_rsync_extra_json_list.py
+58-0src/middlewared/middlewared/pytest/unit/plugins/test_rsync_extra_args.py
+56-0tests/api2/test_rsync_task_extra.py
+6-13src/middlewared/middlewared/plugins/rsync.py
+12-0src/middlewared/middlewared/pytest/unit/helpers.py
+198-135 files

LLVM/project 535ee99 — llvm/lib/Target/RISCV RISCVISelLowering.cpp

fixup! Update comments
DeltaFile
+1-2llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1-21 files

LLVM/project 97f3b33 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vector-deinterleave.ll fixed-vectors-shuffle-zvzip-zve32f.ll

[RISCV] Use Zvzip vunzip in more cases of vector_shuffle
DeltaFile
+222-106llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+159-73llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+41-41llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+12-12llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zvzip-zve32f.ll
+4-6llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+438-2385 files

FreeNAS/freenas c8b5715 — src/middlewared/middlewared/plugins/webshare sharing.py, src/middlewared/middlewared/test/integration/assets webshare.py

Ensure that WebShare shares paths do not overlap

(cherry picked from commit 6bb09897f08271b506b8c936bcdb09ad9cb9f700)
DeltaFile
+149-0tests/api2/test_webshare_sharing.py
+24-68tests/api2/test_webshare_homedir.py
+30-0src/middlewared/middlewared/plugins/webshare/sharing.py
+21-0src/middlewared/middlewared/test/integration/assets/webshare.py
+224-684 files

FreeNAS/freenas 23386de — src/middlewared/middlewared/plugins/webshare sharing.py, src/middlewared/middlewared/test/integration/assets webshare.py

NAS-144150 / 28.0.0-BETA.1 / Ensure that WebShare shares paths do not overlap (#19938)
DeltaFile
+157-0tests/api2/test_webshare_sharing.py
+53-82tests/api2/test_webshare_homedir.py
+35-1src/middlewared/middlewared/plugins/webshare/sharing.py
+17-0src/middlewared/middlewared/test/integration/assets/webshare.py
+262-834 files

FreeNAS/freenas 8153da7 — tests/api2 test_zfs_resource_destroy.py

NAS-144209 / 28.0.0-BETA.1 / Test deleting a dataset after incomplete receive (#19939)
DeltaFile
+29-0tests/api2/test_zfs_resource_destroy.py
+29-01 files

FreeNAS/freenas 832934c — src/middlewared/debian middlewared.zettarepl.service, src/middlewared/middlewared/plugins zettarepl.py

Standalone zettarepl daemon
DeltaFile
+297-505src/middlewared/middlewared/plugins/zettarepl.py
+305-0tests/api2/test_zettarepl_daemon.py
+13-18tests/api2/test_zettarepl_errors.py
+5-5tests/api2/test_zettarepl_definition.py
+7-3tests/api2/test_zettarepl_state.py
+10-0src/middlewared/debian/middlewared.zettarepl.service
+637-5313 files not shown
+650-5319 files

LLVM/project 6f41c6b — libc/src/__support/math powf.h, llvm/test/CodeGen/AMDGPU/GlobalISel srem.i64.ll sdiv.i64.ll

Merge branch 'main' into users/arsenm/remove-kill-flags/riscv/cascaded-select-one-use
DeltaFile
+986-1,144llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+914-1,072llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+728-824llvm/test/CodeGen/X86/mul-constant-i32.ll
+585-680llvm/test/CodeGen/X86/mul-constant-i64.ll
+581-521llvm/test/CodeGen/X86/vector-compress.ll
+15-1,034libc/src/__support/math/powf.h
+3,809-5,275564 files not shown
+24,149-16,592570 files

FreeNAS/freenas 671593f — src/middlewared/middlewared/service crud_service.py config_service.py, tests/api2 test_legacy_api.py

Properly handle filterable methods versioned API
DeltaFile
+21-0tests/api2/test_legacy_api.py
+1-1src/middlewared/middlewared/service/crud_service.py
+1-1src/middlewared/middlewared/service/config_service.py
+23-23 files

LLVM/project f52f991 — llvm/lib/Target/SystemZ SystemZInstrInfo.cpp, llvm/test/CodeGen/SystemZ twoaddr-risbg-cc-liveintervals.mir

SystemZ: Don't convert AND to RISBG if CC is live

The RISBG-type replacements either don't define CC or set it with
different semantics, so the conversion dropped or clobbered a CC value
that was still used.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+59-0llvm/test/CodeGen/SystemZ/twoaddr-risbg-cc-liveintervals.mir
+2-0llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+61-02 files