[clang][Sema] Fix false-positive -Wshadow for friend functions (#221249)
A friend function defined inline in a class body has no implicit `this`,
so a parameter with the same name as a field cannot actually shadow it.
`CheckShadow` only exempted static members and members with an explicit
object parameter, it never handled the case where the enclosing function
isn't a member function at all, which fell through to the generic
diagnostic. In this PR I extend the exemption to cover that case and
added the regression test.
In this PR, I used Claude to help navigate the codebase and explain key
functions.
Fixes #221190
[Profcheck] Exclude two new tests (#223690)
Exclude these tests for now. We haven't gotten to AtomicExpand/ARM yet,
and the AggressiveInstCombine change is overlapping.
PowerPC: Remove LiveVariables dependency from PPCMIPeephole
PPCMIPeephole only used LiveVariables to keep kill/dead flags valid after its
transforms, and made no real use of the analysis.
A later LiveVariables run recomputes those flags from scratch anyway, so
just clear possbly stale kill/dead flags on changed registers.
PPCMIPeephole was the only user of LiveVariables at this point in the
pipeline, so also drop the explicit LiveVariables run before
PPCTLSDynamicCallPass, whose comment references a > 10 year old build
bot failure.
Co-authored-by: Claude (Claude-Opus-4.8)
RegisterPressure: Remove dead defs correctly
When an instruction has overlapping register defs where only some carry the
dead flag (for example a dead super-register def alongside a live sub-register
def), the collector left the shared register units in both the live and dead def
sets. That produced a PressureDiff decrement with no matching increment and tripped
the "PSet overflow/underflow" assertion in getUpwardPressureDelta.
A register unit is dead if any def covering it is dead, regardless of operand
order. Reconcile by subtracting the dead defs from the live defs instead of the
reverse: removeRegLanes only clears the overlapping units, so a def keeps any
units a dead def does not cover.
Fixes #155807.
Fixes #149144.
Fixes #76416.
Fixes #205272.
Co-authored-by: XChy <xxs_chy at outlook.com>
Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
tinygo: update to 0.42.0
- Support for Go 1.27 and LLVM 22
- Runtime panics (divide-by-zero, nil dereference, map and channel
failures) are now recoverable, so recover() works as expected
- Compiler generates type-specific hash and equal functions
- Many GC, scheduler, and timer fixes for more solid concurrent code
- Dynamic USB endpoint registration on RP2, SAMD21/51, and nRF52840
- Big ESP32 step forward: interrupts, ADC, flash XIP, and the new
ESP32-C6
- New targets: STM32H7, the Puya PY32F family, and UEFI
- New boards: ESP32-S3-BOX-3, M5Stack Stamp-S3A, and Pimoroni
Badger 2350
[SCEV] Return a SCEVUse from getAddRecExpr and propagate use flags. (#221606)
Same as https://github.com/llvm/llvm-project/pull/220007 but for
getAddRecExpr:
Pass both expression and use specific flags to getAddRecExpr and
propagate the use flags, if valid conservatively. That is, the final expression
forms an AddRec with the same operands. For example, it is not valid to
propagate the use flags if other (sub-)expressions have been inlined.
It also includes a few mechanical changes, to update users that still
expected const SCEV *.
PR: https://github.com/llvm/llvm-project/pull/221606
AMDGPU: Maintain LiveIntervals when removing blocks in SILowerControlFlow
removeMBBifRedundant removed a redundant block's instructions from the
LiveIntervals maps but not the block itself, leaving a stale idx2MBBMap entry
that crashed getMBBFromIndex in the verifier.
Add SlotIndexes::removeMBBFromMaps to drop the erased block's slot range, and
recompute the intervals that spanned it.
Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
[AMDGPU] Model the cost of the expanded integer to/from floating point casts
No instruction converts to or from a 64 bit integer, and narrow vector
lanes are converted one at a time. Price these expansions by the FP64
rate, sdwa and 16 bit instruction support, and price i33 to i63 like
i64 and bf16 like f32 plus rounding.
Assisted-by: Claude Code Opus 5
[NFC][AMDGPU] Add cost tests for integer to/from floating point casts (#223571)
Cover i48, i64, i128, bf16, fp128 and narrow vector lanes across FP64
rates, 16 bit instructions, sdwa and both cost kinds.
Assisted-by: Claude Code Opus 5
[NFC][AMDGPU] Fix two code quality issues in AMDGPUSwLowerLDS
- NumStaticLDS is always a positive number, so it was always true
- Potential `Changed = true` was dropped in the loop
