LICENSE: sync
While this is nice to give visibility the classes with their
copyright in acme-client are a bit over the top for the process
of exporting a couple of environment variables.
[mlir][llvm] Add MemProf metadata attributes and translation (#238988)
The LLVM dialect understands neither `!memprof` nor `!callsite`: both
are dropped on import and unrepresentable on export. Add
`#llvm.memprof_mib` (one MemInfoBlock: call stack, allocation-type tag,
optional context sizes) plus `#llvm.memprof_context_size`, with
`llvm.memprof`/`llvm.callsite` discardable attributes and import/export
translation.
Known limitation: the MLIR inliner carries both attributes over
unchanged, so contexts go stale across an MLIR-side inline (a
hint-quality issue, not a miscompile). The LLVM's own inliner rewrites
them.
[AMDGPU] Price misaligned flat and LDS accesses with the LDS misaligned bug
In WGP mode on subtargets with the LDS misaligned bug, a flat access is
split into pieces no wider than its alignment and no narrower than 4
bytes, and an LDS access aligned below 4 bytes uses 8-byte pieces as one
aligned to 4 does.
[AMDGPU] Price buffer fat pointer memory operations
Price buffer fat pointer accesses as global accesses, except that an
aligned load is not widened and a vector of odd width elements is not
split element by element. Without relaxed buffer bounds checking, a
vector of elements that are a multiple of 32 bits wide is accessed in
pieces no wider than its alignment and no narrower than 4 bytes, and a
vector of other byte-sized or power of 2 wide elements in pieces of the
largest power of 2 bytes that divides the element size. The width comes
from buffer fat pointer lowering, which now exposes it. When the pointer
is a buffer resource plus a constant offset, the offset and a constant
number of records give the same bounds facts lowering uses to access it
in wider pieces.
[AMDGPU] Price constant address space memory operations
Price constant address space accesses as global accesses, except for
loads selected to scalar loads of up to 64 bytes. These are loads from
the 32-bit constant address space, and loads from the constant address
space whose pointer is an argument passed in SGPRs or a constant, plus
constant offsets, both aligned to 4 bytes or to their size. A scalar
load is widened as its lowering does. An integer whose size is not a
multiple of 4 bytes is loaded as whole dwords, plus a byte load when its
size is 7 modulo 8, since the last byte of such a remainder is left out
of the scalar load. A type with no legal dword vector equivalent is
split into the largest power of 2 pieces that fit, and once the
remainder fits in the alignment it is widened to a power of 2 piece of
up to the alignment, at most 8 bytes for byte vectors. A 3-dword
remainder of a legal dword vector takes a fourth dword when aligned to 8
on a subtarget without scalar dwordx3 loads.
[CIR] Pass _Complex inline asm register operands by value
CIR still returned a _Complex register output through memory ("=*r"),
and passed a 128-bit input that has to be in registers by its address
("*r"), which the backend rejects. Classic codegen now passes both by
value.
Do the same: return a _Complex output with a register-only constraint as
an integer of its size, load a 128-bit input when it has to be in
registers or is tied to an output, and extend a narrower tied input to
the integer type of a _Complex or struct output.
Assisted-by: Claude Opus 5.5
[Clang][CodeGen] Report an unstorable asm register output once
A register output that no integer type is as wide as, such as a 32-byte
struct with "=r", was reported when its store was emitted. An asm goto
emits its stores once for each of its targets, so the error repeated for
each one. It also pointed at the wrong operand when a memory output came
first, since the store's index counts only register outputs.
Report it once, when the output's register type is chosen, at the
output's own expression. This also drops a second error that followed
"output size should not be zero".
Assisted-by: Claude Opus 5.5
