[msan] Handle NEON dot product intrinsics (#176084)
Propagate shadow by reusing existing `handleVectorPmaddIntrinsic()`
(used for analogous x86 instructions; renamed to
`handleVectorDotProductIntrinsic()`), instead of strictly handling.
[TableGen] Gracefully error out in ParseTreePattern when DAG has zero operands so that llvm-tblgen doesn't crash (#161417)
Also handle the case when Pat->Child(i) is null in
CodeGenDAGPatterns::FindPatternInputsAndOutputs().
Fixes issue #157619 : TableGen asserts on invalid cast
[OpenMP][NFC] Use `uinc` atomic builtins for this operation (#177207)
Summary:
We support this now, this is 1-to-1 equivalent and simply prevents us
from needing to do it ourselves.
[lldb] Skip TestDAP_launch_io.py tests on asan builds (#177198)
Two out of three TestDAP_launch_io.py's test's classes have been failing
on ASAN builds ever since it was added into the repo. The ASAN failure
is not easy to debug, so skip these tests until we fix it.
Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)"
This re-applies commit f21e3593371c049380f056a539a1601a843df558 along
with the compile fix failure introduced in
8ab79377740789f6a34fc6f04ee321a39ab73724 before the initial patch was
reverted and fixes for the previously observed assert failure.
We were hitting the assert in the HIP Blender due to a combination of
two issues that could happen when rematerializations are being rolled
back.
1. Small changes in slots indices (while preserving instruction order)
compared to the pre-re-scheduling state meand that we have to
re-compute live ranges for all register operands of rolled back
rematerializations. This was not being done before.
2. Re-scheduling can move registers that were rematerialized at
arbitrary positions in their respective regions while their opcode
is set to DBG_VALUE, even before their read operands are defined.
This makes re-scheduling reverts mandatory before rolling back
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socket.2: Cross-reference protocol families
While here, make wider use of Dv for socket types and protocol families
and reference fcntl(2) flags for the `type` argument values.
MFC after: 3 days
Reviewed by: glebius, ziaee
Differential Revision: https://reviews.freebsd.org/D54434
Improve pwenc handling
Add a common pwenc_rename function that resets caches on
config upload parsing and other places where we replace the
pwenc file. This also ensures that we never have a partially-
written pwenc file (for example sent by remote HA node).
When we rename / replace the pwenc file we'll keep a backup
of the old on so that we have potential to rebuild old
config if needed.
Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)"
This re-applies commit f21e3593371c049380f056a539a1601a843df558 along
with the compile fix failure introduced in
8ab79377740789f6a34fc6f04ee321a39ab73724 before the initial patch was
reverted and fixes for the previously observed assert failure.
We were hitting the assert in the HIP Blender due to a combination of
two issues that could happen when rematerializations are being rolled
back.
1. Small changes in slots indices (while preserving instruction order)
compared to the pre-re-scheduling state meand that we have to
re-compute live ranges for all register operands of rolled back
rematerializations. This was not being done before.
2. Re-scheduling can move registers that were rematerialized at
arbitrary positions in their respective regions while their opcode
is set to DBG_VALUE, even before their read operands are defined.
This makes re-scheduling reverts mandatory before rolling back
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[CodeGen][NPM] dump slot index info with -debug while running LiveIntervals (#173488)
matches legacy. tests such as "CodeGen/AMDGPU/liveness.mir" and
"CodeGen/AMDGPU/phys-partial-liveness.mir" use this.
[Darwin] CMake warning when building sanitized libLTO on Darwin with system sanitizer library (#176976)
Due to a system security policy, libLTO built with `LLVM_USE_SANITIZER`
and a toolchain (i.e. Xcode) sanitizer library cannot be loaded into the
toolchain `ld`. This only affects Darwin.
This adds a warning when users try to do this, and suggests a workaround
(use just-built sanitizer libraries).
This affected the lldb-cmake-sanitized job:
https://github.com/llvm/llvm-zorg/commits/main/zorg/jenkins/jobs/jobs/lldb-cmake-sanitized
rdar://168502870
[AMDGPU][GlobalISel] Add RegBankLegalize rules for SMED3 and CVT_PK_I16_I32 (#176596)
These opcodes are created together for the i64->i16 signed clamp
pattern.
[Clang][WebAssembly] Fix crash when using __funcref in C++ code (#176237)
Enable address space map mangling for the WebAssembly target. This fixes
a crash in the Itanium name mangler when trying to mangle types with the
wasm_funcref address space qualifier in C++ mode.
Fixes #176154
[AMDGPU][Scheduler] Revert all regions when remat fails to increase occ.
When the rematerialization stage fails to increase occupancy in all
regions, the current implementation only reverts the effect of
re-scheduling in regions in which the increased occupancy target could
not be achieved. However, given that re-scheduling with a higher
occupancy target puts more pressure on the scheduler to achieve lower
maximum RP at the cost of potentially lower ILP as well, region
schedules made with higher occupancy targets are generally less
desirable if the whole function is not able to meet that target.
Therefore, if at least one region cannot reach its target, it makes
sense to revert re-scheduling in all affected regions to go back to
a schedule that was made with a lower occupancy target.
This implements such logic for the rematerialization stage, and adds a
test to showcase that re-scheduling is indeed interrupted/reverted as
soon as a re-scheduled region that does not meet the increased target
occupancy is encountered.
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[AMDGPU][Scheduler] Simplify scheduling revert logic
When scheduling must be reverted for a region, the current
implementation re-orders non-debug instructions and debug instructions
separately; the former in a first pass and the latter in a second pass
handled by a generic machine scheduler helper whose state is tied to the
current region being scheduled, in turns limiting the revert logic to
only work on the active scheduling region.
This makes the revert logic work in a single pass for all MIs, and
removes the restriction that it works exclusively on the active
scheduling region. The latter enables future use cases such as
reverting scheduling of multiple regions at once.
While the instruction order produced should be identical to what it was
before, small changes in slot indices of re-scheduled MIs yield
different RA decisions and significant test churn.
