LLVM/project b05b77allvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fsub.ll llvm.amdgcn.reduce.fadd.ll

[AMDGPU] DPP wave reduction for double types - 2 (#189391)

Supported Ops: `fadd` and `fsub`
DeltaFile
+1,030-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+1,008-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+20-15llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,058-2753 files

LLVM/project bc54a63llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmax.ll llvm.amdgcn.reduce.fmin.ll

[AMDGPU] DPP wave reduction for double types - 1 (#189390)

Supported Ops: `fmin` and `fmax`
DeltaFile
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+27-13llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,251-4813 files

LLVM/project ed1199allvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

[AMDGPU] DPP wave reduction for long types - 3 (#189226)

Supported Ops: `and`, `or`, `xor`
DeltaFile
+984-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+12-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,916-3494 files

FreeBSD/src a6bd704usr.bin/sockstat sockstat.1

sockstat: Unbreak SEE ALSO section

MFC after:      1 week
Fixes:          7b35b4d19630 ("sockstat: add libxo support")
DeltaFile
+3-3usr.bin/sockstat/sockstat.1
+3-31 files

LLVM/project 66b946dllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] DPP wave reduction for long types - 2 (#189225)

Supported Ops: `add`, `sub`
DeltaFile
+1,113-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,079-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+73-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,265-3083 files

LLVM/project 42ce9dbllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] DPP wave reduction for long types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,113-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,079-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+73-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,265-3083 files

LLVM/project e27bc38llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fsub.ll llvm.amdgcn.reduce.fadd.ll

[AMDGPU] DPP wave reduction for double types - 2

Supported Ops: `fadd` and `fsub`
DeltaFile
+1,030-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+1,008-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+20-15llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,058-2753 files

LLVM/project 1bdb9c9llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmax.ll llvm.amdgcn.reduce.fmin.ll

[AMDGPU] DPP wave reduction for double types - 1

Supported Ops: `fmin` and `fmax`
DeltaFile
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+27-13llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,251-4813 files

LLVM/project d98d274llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

[AMDGPU] DPP wave reduction for long types - 3

Supported Ops: `and`, `or`, `xor`
DeltaFile
+984-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+12-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,916-3494 files

LLVM/project 15ce7e1llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.max.ll llvm.amdgcn.reduce.min.ll

[AMDGPU] DPP wave reduction for long types - 1 (#189224)

Supported Ops: `min`, `max`, `umin`, `umax`
DeltaFile
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+187-42llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4,443-4745 files

LLVM/project ef36f92llvm/test/Transforms/LoopVectorize pr31190.ll optsize.ll, llvm/test/Transforms/LoopVectorize/AArch64 sve2-histcnt-epilogue.ll

[LV][NFC] Remove "REQUIRES: asserts" line from some tests (#191795)

Several tests seemed to require asserts despite not testing any debug
output so I have removed the line.
DeltaFile
+31-4llvm/test/Transforms/LoopVectorize/pr31190.ll
+2-2llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
+0-1llvm/test/Transforms/LoopVectorize/X86/slm-no-vectorize.ll
+0-1llvm/test/Transforms/LoopVectorize/optsize.ll
+0-1llvm/test/Transforms/LoopVectorize/LoongArch/loongarch-interleaved.ll
+0-1llvm/test/Transforms/LoopVectorize/tripcount.ll
+33-106 files

LLVM/project cee66b7llvm/lib/Target/AMDGPU SIISelLowering.cpp

[AMDGPU]Refactor `lowerWaveReduce` for maintainability (#189223)

The function to lower wave reduce pseudos is already quite
large ,and there are yet a few more operations to support.
Refactoring some of the code to make it more manageable.
Summary of changes:
1. Moved the expansion for `V_CNDMASK_B64_PSEUDO` to a
separate function. It's needed for 64 bit dpp operations.

2. Collapsed `getIdentityValueFor32BitWaveReduction` and
`getIdentityValueFor64BitWaveReduction` into a single
function which returns a 64 bit unsigned value.

3. Modified `getDPPOpcForWaveReduction` to also return
the `Clamp` opcode.

4. Added a lambda: `BuildRegSequence` and a static function
`ExtractSubRegs` as those code blocks are repeated with
little variation.

    [2 lines not shown]
DeltaFile
+196-216llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+196-2161 files

FreeBSD/src ab57518sys/sys abi_types.h

sys/abi_types.h: Stick with 32-bit time32_t

This unbreaks zfs on non-x86 64-bit architectures.
DeltaFile
+2-0sys/sys/abi_types.h
+2-01 files

FreeBSD/ports cdecda5misc/py-uuid-utils distinfo Makefile

misc/py-uuid-utils: update 0.12.0 → 0.14.1
DeltaFile
+5-5misc/py-uuid-utils/distinfo
+4-4misc/py-uuid-utils/Makefile
+9-92 files

FreeBSD/ports 9c29b40audio/cardinal pkg-plist distinfo

audio/cardinal: update 25.06 → 26.02
DeltaFile
+466-7audio/cardinal/pkg-plist
+3-3audio/cardinal/distinfo
+2-1audio/cardinal/Makefile
+471-113 files

FreeBSD/ports 63b396clang/pomsky distinfo Makefile

lang/pomsky: update 0.10 → 0.12.0
DeltaFile
+639-309lang/pomsky/distinfo
+319-155lang/pomsky/Makefile
+958-4642 files

FreeBSD/ports e64ea09graphics/ocrs distinfo Makefile

graphics/ocrs: update 0.10.4 → 0.12.2
DeltaFile
+157-77graphics/ocrs/distinfo
+78-39graphics/ocrs/Makefile
+235-1162 files

LLVM/project 120cbbdllvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine fold-fcmp-trunc.ll known-never-nan.ll

[InstCombine] Fold `fptrunc(x) ord/uno [ C | fptrunc(y) ]` to `x ord/uno [ C | y ]` (#185844)

Recognize TWO new patterns and fold them as follows:
```
fptrunc(x) ord/uno C           -->  x ord/uno 0
fptrunc(x) ord/uno fptrunc(y)  -->  x ord/uno y
```

Fixes #185698
Alive2: https://alive2.llvm.org/ce/z/YvXnBJ
IR diff: https://github.com/dtcxzyw/llvm-opt-benchmark/pull/3551
CompTime impact: https://github.com/dtcxzyw/llvm-opt-benchmark/pull/3552
DeltaFile
+48-3llvm/test/Transforms/InstCombine/fold-fcmp-trunc.ll
+28-9llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+1-2llvm/test/Transforms/InstCombine/known-never-nan.ll
+77-143 files

FreeBSD/src 47a9af4. UPDATING, libexec/rc/rc.d NETWORKING

rc.d/NETWORKING: remove the NETWORK alias

NETWORKING is the documented placeholder, while
/etc/rc.d/NETWORKING still provides the legacy alias
NETWORK.

The NETWORKING script was originally introduced to avoid
conflicts with NetBSD's lowercase network script on
case-insensitive file systems.  The NETWORK alias was
retained for compatibility with older scripts.

Following the discussion in PR 293652, remove the legacy
NETWORK alias from 16-CURRENT.  Keeping both names adds
more confusion than value now that NETWORKING is the
documented placeholder and current base system and ports
tree uses are already clean.

Add an UPDATING entry to note that local RC scripts using
REQUIRE: NETWORK should be migrated to REQUIRE: NETWORKING.

    [5 lines not shown]
DeltaFile
+6-0UPDATING
+1-1libexec/rc/rc.d/NETWORKING
+7-12 files

NetBSD/pkgsrc-wip 29598b6neatvnc buildlink3.mk Makefile, wayvnc Makefile

neatvnc, wayvnc: update aml path after import
DeltaFile
+1-1neatvnc/buildlink3.mk
+1-1wayvnc/Makefile
+1-1neatvnc/Makefile
+3-33 files

NetBSD/pkgsrc-wip 4eccccd. Makefile, wlsunset Makefile distinfo

wlsunset: remove, imported to pkgsrc
DeltaFile
+0-18wlsunset/Makefile
+0-5wlsunset/distinfo
+0-3wlsunset/PLIST
+0-2wlsunset/DESCR
+0-1Makefile
+0-295 files

NetBSD/pkgsrc-wip 30b3b60. Makefile, wtype Makefile distinfo

wtype: remove, imported to pkgsrc
DeltaFile
+0-19wtype/Makefile
+0-5wtype/distinfo
+0-3wtype/PLIST
+0-2wtype/DESCR
+0-1Makefile
+0-305 files

NetBSD/pkgsrc-wip 8b5c77f. Makefile, labwc-tweaks PLIST Makefile

labwc-tweaks: remove, imported to pkgsrc
DeltaFile
+0-44labwc-tweaks/PLIST
+0-24labwc-tweaks/Makefile
+0-5labwc-tweaks/distinfo
+0-2labwc-tweaks/DESCR
+0-1Makefile
+0-765 files

NetBSD/pkgsrc-wip 7a637db. Makefile, wf-recorder Makefile distinfo

wf-recorder: remove, imported to pkgsrc
DeltaFile
+0-27wf-recorder/Makefile
+0-5wf-recorder/distinfo
+0-5wf-recorder/DESCR
+0-4wf-recorder/PLIST
+0-1Makefile
+0-425 files

NetBSD/pkgsrc-wip 980a24e. Makefile, wvkbd Makefile DESCR

wvkbd: remove, imported to pkgsrc
DeltaFile
+0-39wvkbd/Makefile
+0-5wvkbd/DESCR
+0-5wvkbd/distinfo
+0-3wvkbd/PLIST
+0-1Makefile
+0-535 files

NetBSD/pkgsrc-wip 13309d6. Makefile, wev Makefile distinfo

wev: remove, imported to pkgsrc
DeltaFile
+0-27wev/Makefile
+0-5wev/distinfo
+0-4wev/DESCR
+0-3wev/PLIST
+0-1Makefile
+0-405 files

NetBSD/pkgsrc-wip 76b7bb8lswt Makefile distinfo, lswt/patches patch-lswt.c patch-Makefile

lswt: remove, imported to pkgsrc
DeltaFile
+0-26lswt/Makefile
+0-24lswt/patches/patch-lswt.c
+0-17lswt/patches/patch-Makefile
+0-7lswt/distinfo
+0-4lswt/DESCR
+0-4lswt/PLIST
+0-821 files not shown
+0-837 files

FreeBSD/ports ac7c78adeskutils/joplin-desktop Makefile, editors/vscode Makefile

*/*: Bump port revision after electron39 update (29f337f0e7de)
DeltaFile
+1-1textproc/obsidian/Makefile
+1-1net-im/teams/Makefile
+1-1deskutils/joplin-desktop/Makefile
+1-1net-im/deltachat-desktop/Makefile
+1-0net-im/vesktop/Makefile
+1-0editors/vscode/Makefile
+6-41 files not shown
+7-47 files

LLVM/project 49d7237llvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx ctpop-ctlz.ll

[LoongArch] Select `V{AND,OR,XOR,NOR}I.B` for bitwise with byte splat immediates

The `V{AND,OR,XOR,NOR}I.B` instructions operate on byte elements and accept
an 8-bit immediate. However, when the same byte splat constant is used with
wider vector element types (e.g. v8i16, v4i32, v2i64), instruction selection
currently falls back to materializing the constant in a temporary register.

```
vrepli.b  -1
vxor.v
```

even though the immediate form is available:

```
vxori.b 255
```

This happens because selectVSplatImm requires the splat bit width to match

    [11 lines not shown]
DeltaFile
+29-2llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+24-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+3-6llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
+3-6llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll
+3-6llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
+3-6llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll
+65-2614 files not shown
+102-8520 files

FreeBSD/ports 29f337fdevel/electron39 distinfo, devel/electron39/files patch-electron_shell_browser_api_electron__api__web__contents.cc patch-electron_shell_browser_ui_inspectable__web__contents.cc

devel/electron39: Update to 39.8.7

Changelog:
- https://github.com/electron/electron/releases/tag/v39.8.6
- https://github.com/electron/electron/releases/tag/v39.8.7

Reported by:    GitHub (watch releases)
DeltaFile
+158-15devel/electron39/files/packagejsons/yarn.lock
+5-5devel/electron39/distinfo
+4-4devel/electron39/files/patch-electron_shell_browser_api_electron__api__web__contents.cc
+4-4devel/electron39/files/patch-electron_shell_browser_ui_inspectable__web__contents.cc
+3-3devel/electron39/files/patch-services_device_public_cpp_device__features.cc
+4-0devel/electron39/files/packagejsons/package.json
+178-312 files not shown
+181-348 files