x11/openrgb: Update to 1.0
Also:
- Remove LIB_DEPENDS from BUILD_DEPENDS
- Switch to QT6
- Use a cleaner/predictable GL_TAGNAME
- Remove do-install target to leave the build system install files
- Use a pkg-plist file
- Add more details to pkg-descr
PR: 299149
Approved by: Vidar Karlsen <vidar at karlsen.tech> (maintainer)
isakmpd: Bound the HASH coverage in cfg_verify_hash()
The verifier assumed the HASH payload is the first payload and
derived the covered length from the message length, reading past
the end of the message when another payload precedes HASH. Compute
the covered range from the HASH payload's actual position and reject
it if it extends past the message end.
from markus@, ok me deraadt@
[CMake] Make find_package(Clang) load MLIR when ClangIR uses a full MLIR (#228366)
With CLANG_ENABLE_CIR=ON, Clang's exported libraries link MLIR. When
MLIR is listed in LLVM_ENABLE_PROJECTS it installs its own package and
owns every target exported from mlir/. ClangTargets.cmake references
those targets without defining them, and ClangConfig.cmake never loaded
the MLIR package, so an external find_package(Clang) failed with:
```
The following imported targets are referenced, but are missing:
MLIRIR MLIRPass MLIRAnalysis ... MLIRSupport MLIRTransforms ...
```
unless the consumer happened to call find_package(MLIR) first.
When MLIR is enabled only implicitly as a ClangIR dependency
(LLVM_DEPENDENCY_ONLY_PROJECTS), no MLIR package exists and Clang
already promotes the reachable MLIR closure into its own exports, so
that mode worked. The two modes therefore need different plumbing but
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RISCV: Stop setting kill flags on virtual registers before FinalizeISel
Kill flags have no remaining use before register allocation and are
stripped by LiveIntervals.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Fold fmul with zero checks to fmul.legacy
Recognize f32 multiplication with zero checks in AMDGPUCodeGenPrepare,
including fabs/fneg wrappers.
Example:
```
(x == 0 || y == 0) ? +0.0 : x * y
==>
llvm.amdgcn.fmul.legacy(x, y)
```
[AMDGPU] Add fmul.legacy select fold tests. NFC
Add AMDGPUCodeGenPrepare tests for folding a select guarded by zero
checks into llvm.amdgcn.fmul.legacy, including negative tests and min
cases for future work.
[AArch64][SPIRV][GlobalISel] Migrate target-specific wip_match_opcode combines to MIR-pattern (#222903)
It replaces the `wip_match_opcode` with declarative MIR-pattern match
roots across the AArch64 and SPIRV target-specific GICombines.
Some important points to consider :
- **shuffle_vector_lowering:** these `G_SHUFFLE_VECTOR` rules are order-
sensitive. `fullrev` previously gained priority through a nested
`G_IMPLICIT_DEF` match; that predicate is relocated to C++ so all rules
are equal-priority and `fullrev` is ordered last, preserving the
original dispatch sequence and codegen.
- **SPIRV intrinsic roots:** the matrix/length/distance rules match and
apply on target intrinsics (`int_spv_*`, `int_matrix_*`), requiring the
`IntrinsicsSPIRV` enum in the combiner translation unit.
- **Deferred:** `vector_unmerge_lowering` and `unmerge_ext_to_unmerge`
remain on `wip_match_opcode`; their `G_UNMERGE_VALUES` variadic-def
roots are not yet expressible as MIR patterns.
[AArch64][LSR] Prefer pointer IVs for SVE accesses that need splitting (#228510)
Currently, LSR always prefers scaled accesses but that ends up doing
more work as only the first access can used the scaled register. Later
split accesses need to compute the base then another `mul vl` offset.
Assisted-by: Codex
Merge tag 'printk-for-7.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/printk/linux
Pull printk fix from Petr Mladek:
- Allow using Braille console with a serial console driver converted
to NBCON API
* tag 'printk-for-7.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/printk/linux:
braille: nbcon: Allow to use a serial console with NBCON API as Braille console
editors/xemacs-current{,-nox11} -- Update to v21.5.37 "lettuce"
Major Features, Bugfixes, and Backward Incompatible Changes
-- Fix: Avoid OpenSSL header conflicts on windows, get Cygwin building
-- Henry S. Thompson
-- Fix: Get XEmacs building as C++ under Visual Studio
-- Aidan Kehoe
-- Fix: Handle -display correctly once more on X11
-- Aidan Kehoe
-- Fix: Turn on -fno-strict-aliasing unconditionally with clang, avoid crashes
-- Aidan Kehoe, Mike Sperber
-- Fix: Don't crash when Fselected_window() returns nil. -- Aidan Kehoe
-- Fix: Produce zero-length bit vectors without crashing, error-checking builds
-- Aidan Kehoe
-- Fix: Printing char tables respecting print-table-noreadably-length
-- Aidan Kehoe
-- Fix: Appropriate type checking with #'ephemeron-ref, avoid crashes
-- Aidan Kehoe
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[LAA] Avoid duplicate runtime-check group members (#226829)
Found while working on #226816 and extracted into a separate PR for
easier review.
A read-modify-write pointer has separate read and write entries in the
dependence candidates. Both entries can map back to the same
runtime-check pointer, causing its index to be added to a checking group
twice.
Key the runtime-pointer map by MemAccessInfo, including the read/write
distinction, so each runtime pointer appears only once in a checking
group.
Duplicate members also consume the memory-check merge budget. With a low
merge threshold, the fix reduces two runtime checks to one. It also
restores the singleton-group invariant used by #226816.
Developed with assistance from OpenAI Codex.
[MLIR][ODS] Require the value after oilist keyword (#229334)
The generated parser treated optional attribute inside an oilist clause
as optional even after its keyword was parsed
As a result, a keyword without a value was accepted, but the attribute
was simply dropped
Prerequisite for https://github.com/llvm/llvm-project/pull/228977
lang/swift6: Fix compilation of math functions when using c++ interoperability mode
The following code failed to build if it was compiled with c++
interoperability mode:
```
import Foundation
print(log2(2.0))
```
with the following error:
error: reference to declaration 'log2' broken by a context change; the declaration kind of 'log2' changed since building 'Foundation', it was in 'SwiftGlibc' and now a candidate is found only in 'Foundation'
This commit fixes it.
[lldb][NativePDB] Use host arch for thread locals test (#229340)
The test used to use `--arch=64`, but technically, it doesn't care about
the architecture, so it was removed. This intends to fix the
lldb-remote-linux-win buildbot:
<lab.llvm.org/buildbot/#/builders/197/builds/19717>.
AMDGPU: Improve optimization remarks for atomic lowering
Improve the phrasing when the atomicrmw legalization emits the hardware
instruction. Replace the unhelpful "due to an unsafe request" wording in the
optimization remark with the actual reason the native instruction was legal
to use.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[SPIRV] Fix invalid SPIR-V for loops with switch headers (#229289)
For non-shader targets without SPV_INTEL_unstructured_loop_controls, the
backend uses OpLoopMerge to carry loop unroll hints. When the loop
header ends with a switch, it emits OpLoopMerge after OpSwitch,
producing invalid SPIR-V.
OpLoopMerge must immediately precede OpBranch or OpBranchConditional
[1]. Emit it only when the loop header ends with one of these branches.
Non-shader loops do not require OpLoopMerge, so skipping it drops only
the unroll hint and preserves the loop's behavior.
[1]
https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpLoopMerge
---------
Co-authored-by: Arseniy Obolenskiy <gooddoog at student.su>
