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science/wannier90: update 4.0.2 → 4.0.3

misc/py-openinference-instrumentation: update 0.1.66 → 0.1.71

misc/py-comfy-aimdo: update 0.5.5 → 0.5.6

misc/py-openinference-instrumentation-smolagents: update 0.1.40 → 0.1.43

misc/py-openinference-semantic-conventions: update 0.1.39 → 0.1.41

graphics/py-albucore: update 0.2.18 → 0.2.21

devel/py-cytoolz: update 1.1.0 → 1.2.0

misc/py-modelscope-hub: update 0.4.2 → 0.4.6

devel/py-camel-converter: update 5.1.1 → 6.0.0

finance/py-financetoolkit: update 2.2.0 → 2.2.2

devel/py-uncalled-for: update 0.4.0 → 0.4.1

databases/py-sqlcipher3: update 0.6.2 → 0.6.3

finance/py-pandas-market-calendars: update 5.4.0 → 5.5.0

security/py-iamdata: update 0.1.202609091 → 0.1.202610111

textproc/py-json-repair: update 0.63.4 → 0.64.0

math/py-numba-stats: update 1.13.0 → 1.14.0

security/py-liboqs-python: update 0.16.0 → 0.16.0.1

devel/py-numkong: update 7.8.2 → 7.8.5

devel/py-cyclopts: update 4.25.2 → 5.2.0

cad/nvc: update 1.22.1 → 1.23.0

misc/py-ag2: update 1.0.4 → 1.1.2

misc/py-openai: update 3.8.0 → 3.28.0

Drop the zero shift check in the and fold

Regenerate load-global-i8.ll and sign_extend.ll after rebase

[AMDGPU] Extract byte lanes of a split vector from the 32-bit source

After a <4 x i8> is split into i16 halves, a byte lane is extended
from an i16 shift of a truncate. Rewrite it on the 32-bit source as an
and of srl or a sign_extend_inreg of srl, which select to a single bit
field extract.

Uniform zero and any extends are left alone, their i16 shift is already
promoted to i32.

[NFC][AMDGPU] Precommit test for byte lane extension after vector split (#228423)

Assisted-by: Claude Code Opus 5

   doc/CHANGES: fix typo

net-im/parla: Update to 0.9.9

[InstCombine] Remove redundant CRC32 intrinsic declarations from tests (#230926)

Based on review suggestion comment in
https://github.com/llvm/llvm-project/pull/230751#discussion_r4240611585

   doc: Updated lang/quickjs-ng to 0.17.0