NAS-139807 / 26.0.0-BETA.1 / Handle EROFS when setting immutable flag on lock of readonly dataset (#18292)
## Problem
Locking an encrypted dataset on a replication target (where the parent
has readonly=on) fails with EROFS. After lock unmounts the child
dataset, the mountpoint directory lives on the parent's read-only
filesystem, so setting the immutable flag via chattr +i fails.
## Solution
Catch OSError with errno.EROFS in the lock path, matching the existing
pattern in the unlock code (ffafdaf2c0). The immutable flag is
unnecessary here anyway since the parent's read-only mount already
prevents writes to the mountpoint directory.
[LLVM][TTI] Remove the isVScaleKnownToBeAPowerOfTwo hook. (#183292)
After https://github.com/llvm/llvm-project/pull/183080 this is no longer
a configurable property.
NOTE: No test changes expected beyond
llvm/test/Transforms/LoopVectorize/scalable-predication.ll which has
been removed because it only existed to verfiy the now unsupported
functionality.
[clang-tidy] Fix erroneous warning to make deleted function public (#182577)
This PR fixes #54276 and fixes #135249 by only matching private deleted
functions with a public overload or special member functions.
[CIR][AArch64] Add lowering + tests for predicated SVE svdup_lane builtins
This PR adds CIR lowering + tests for SVE `svdup_lane` builtins on
AArch64. The corresponding ACLE intrinsics are documented at:
https://developer.arm.com/architectures/instruction-sets/intrinsics
[SPIRV] Implement Gather and GatherCmp intrinsics (#182578)
This commit implements the intrinsics needed to represent the texture
Gather* instructions in HLSL.
Assisted-by: Gemini
[CIR] Implement compare exchange with dynamic failure ordering (#183110)
In #156253, we implemented the rest of this feature, with compile time
constant failure ordering. This patch follows the incubators direction
(with a little cleanup based on other cleanup that we do) to replace
this situation with a 'switch'.
fixup! Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
and use tablegen pattern for intrinsic, plus other small review changes.
[MLIR][Python] Fix typeid support for DynamicType and DynamicAttr (#183076)
Previously, we were using the static `typeid` of `DynamicType` for
checks, which is incorrect. We should instead check against the `typeid`
of `DynamicTypeDefinition` (which is a subclass of `SelfOwningTypeID`),
and register it via `register_type_caster` so that Python-defined types
can use `maybe_downcast`. (The attribute part is same.)
NAS-139980 / 26.0.0-BETA.1 / Fix test__check_root_level_dataset_properties xattr/checksum assertions (#18295)
Commit 144edb2a88 correctly changed xattr from 'ON' to 'SA' to match
upstream ZFS commit
[073b34b3](https://github.com/openzfs/zfs/commit/073b34b3) (which
reordered xattr_table so 'sa' displays instead of 'on' for
ZFS_XATTR_SA), but also incorrectly changed checksum from 'ON' to 'SA'.
Follow-up ef786c525b reverted xattr back to 'ON' instead of reverting
checksum, leaving both values swapped.
Restore the correct assertions:
- xattr: 'SA'
- checksum: 'ON'
[InstCombine] Replace alloca with poison size using poison instead of null
When an alloca instruction has an undef (poison) array size, InstCombine
was previously replacing all uses of the alloca with a null pointer. This
caused invalid IR when the alloca was used by @llvm.lifetime intrinsics.
According to the @llvm.lifetime intrinsic specification, the pointer
argument must be either:
- A pointer to an alloca instruction, or
- A poison value
Since null is neither an alloca pointer nor poison, the previous
transformation violated the intrinsic's requirements and produced
invalid IR.
Fix by replacing the alloca with a poison value instead of null, which
satisfies the @llvm.lifetime requirements and produces valid IR.
[LLVM] Refine MemoryEffect handling for target-specific intrinsics (#155590)
This patch improves memory alias analysis between calls if they change
inaccessible or target memory locations. The results is
computed by comparing each location ModRefInfo between the calls.
[LAA] NFC: Rename mulSCEVOverflow to mulSCEVNoOverflow (#183096)
The function returns nullptr when the multiplication WOULD overflow,
matching the semantics of its sibling addSCEVNoOverflow. The old name
reads as if the function multiplies with overflow, which is the opposite
of what it does.
[InstCombine] Replace alloca with poison size using poison instead of null
When an alloca instruction has an undef (poison) array size, InstCombine
was previously replacing all uses of the alloca with a null pointer. This
caused invalid IR when the alloca was used by @llvm.lifetime intrinsics.
According to the @llvm.lifetime intrinsic specification, the pointer
argument must be either:
- A pointer to an alloca instruction, or
- A poison value
Since null is neither an alloca pointer nor poison, the previous
transformation violated the intrinsic's requirements and produced
invalid IR.
Fix by replacing the alloca with a poison value instead of null, which
satisfies the @llvm.lifetime requirements and produces valid IR.
[MLIR][NVVM] Fix kFactor for fp8/fp6/fp4 types in MmaSpOp verifier. Improve mma tests. (#183133)
Fix an incorrect kFactor value for e4m3/e5m2, e3m2/e2m3, e2m1 types in
MmaSpOp::verify(). The kFactor for these types was set to 32 but should
be 16.
kFactor is used to compute the expected number of operand A/B register
fragments. With kFactor=32 (wrong) and the only allowed shape m16n8k64,
the fragment count was incorrect. With kFactor=16 (correct), it matches
the PTX ISA definition for mma.sp with fp8/fp6/fp4 A/B operands.
PTX ISA reference:
[https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-sparse-mma](https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-sparse-mma)
Also improve existing MLIR dialect tests for nvvm.mma.sp.sync and add
new mlir-translate tests covering mma, mma.sp, and blockscale variants.
[InstSimplify] Add support for llvm.structured.gep (#182874)
Similar to GEP, the SGEP instruction with no indices can be simplified
by directly using the base pointer.
tcp: improve handling of segments in TIME WAIT
The check for excluding duplicate ACKs needs to consider only TH_SYN
and TH_FIN. We know that TH_ACK is set and TH_RST is cleared. All
other flags, in particular TH_ECE, TH_CWR, and TH_AE needs to be
ignored for the check.
PR: 292293
Reviewed by: rrs
MFC after: 3 days
Sponsored by: Netflix, Inc.
Differential Revision: https://reviews.freebsd.org/D55489
[WebAssembly] optimize ext + shuffle + add into addext (#182849)
cc https://github.com/llvm/llvm-project/issues/179143
This adds a second pattern: we already recognize "shuffle + extend +
add" as `addext`, this adds another pattern for "extend + shuffle +
add", which can come up when programs are optimized.
tcp: BBLog incoming packets in TCPS_TIME_WAIT
PR: 292293
Reviewed by: rrs, rscheff, pouria, Nick Banks, Peter Lei
MFC after: 3 days
Sponsored by: Netflix, Inc.
Differential Revision: https://reviews.freebsd.org/D5546
