radvd: allow to start without primary IPv6 for #10048
Reshuffle the code a little to make it (a bit) more obvious this is
safe to assume and working confirmed by automatic mode already.
Since we have full control via MVC enable/disable this is fine now.
[AArch64][GISel] Add widenScalarOrEltToNextPow2OrMinSize for small element vector CTPOP (#189397)
This widens small ctpop to at least i8, preventing types like v8i4 from
falling back.
[AMDGPU] computeKnownBitsForTargetNode - convert AMDGPUISD::MUL_U24/MUL_I24 handling to use KnownBits::mul (#190600)
Remove custom implementation and rely on KnownBits::mul directly
[AArch64] Optimize vector multiplications by certain constants for v2i64 (#183827)
## Summary
This patch optimizes v2i64 multiplications by constants that can be
decomposed into a single shift and an addition/subtraction (i.e.,
constants of the form $2^n \pm 1$).
Unlike 32-bit or 16-bit vectors, AArch64 Advanced SIMD (NEON) lacks a
native v2i64 multiply instruction.
Currently, the compiler scalarizes these operations, By lowering these
specific cases to shl + add/sub, we keep the entire operation within the
SIMD unit, significantly reducing instruction count and execution
latency.
## Technical Details
- Target: AArch64 (With Neon Enabled)
- Transformation: Replaces (mul x, splat(2^n + 1)) with (add (shl x, n),
x) and (mul x, splat(2^n - 1)) with (sub (shl x, n), x).
- Placement: Integrated into performMulCombine in
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[CIR][AArch64] Lower NEON vbsl builtins (#188449)
Part of : https://github.com/llvm/llvm-project/issues/185382
Add CIR lowering for the AArch64 NEON bitwise-select builtins.
Lower the NEON bitwise-select builtins to CIR bitwise operations
implementing the ACLE bitwise-select semantics, including the
floating-point forms.Also add CIR support for `mfloat8` NEON vector
types so `vbsl_mf8` and `vbslq_mf8` lower successfully instead of
hitting the existing NYI in type conversion.
Move and extend the corresponding FileCheck coverage in
`clang/test/CodeGen/AArch64/neon/intrinsics.c`.
[compiler-rt] Enable minimal ubsan for GPU targets (#188289)
Summary:
This PR enabled the ubsan-minimal target for the GPU. This should enable
the trivial checks on the GPU-side. I had to make some changes to the
common sanitizer requirements, but I think this is reasonable
considering the common_sanitizer requires a fully hosted environment and
all we needed were the headers.
[libc] Make rpc_server.h independent from libc internals (#190423)
Summary:
It was very convenient to have the RPC server use the internal libc
printing utilities, but it caused a lot of problems. The LLVM libc
internals were never meant to be included arbitrarily and we completely
bypassed this restriction. Furthermore it prevented us from installing
and using these libraries in other contexts. There was a whole host of
hacks around this, leading to endless PPC problems, compiler errors,
etc.
This PR re-uses the old minified format parser I used to use for the GPU
case. We simply parse the formats to get the size, then copy the
strings. The actual printing instead is done by locking the output file
and repeatedly building up the string using the host's `printf`. Slight
test modifications because we no longer can depend on the specific user
printf specification, it may not handle null or binary values for
example.
[libc] Fix ordering to make sure event_id is written before interrupt (#190705)
Summary:
Right now this meant we could avoid flushing the event_id write before
firing the interrupt, so it could be unset.
[NFC][analyzer] Spread use of 'Expr*' instead of 'Stmt*' (#188319)
When I was browsing the codebase, I was surprised to see that the first
parameter of `ProgramStateRef::BindExpr` was `const Stmt*` instead of
`const Expr*`. As I surveyed calls to `BindExpr`, I realized that
fortunately no code passes non-expression statements to `BindExpr`
(anymore... it seems that earlier we had such hacks) so in this commit
I'm able to change the type of the first parameter to `const Expr*`.
There was a call to `BindExpr` where the first argument was the value of
the data member `StackFrameContext::CallSite`, so I also changed the
type of that member from `const Stmt*` to `const Expr*` because it was
another statement pointer that always pointed to expressions (or null).
This commit prepares the ground for using `Expr*` instead of `Stmt*` in
`EnvironmentEntry`, which is currently a `pair<const Stmt *, const
StackFrameContext *>` and will be updated in follow-up commits.
This commit also includes minor unrelated simplifications and
corrections.
Add tiering API
This commit modifies the truenas API to wrap around tiering design
in the following ways:
A new namespace zfs.tier. will be added. This contains global
configuration for systemwide tiering settings. Parameters include
- enabled: whether to enable tiering. This feature requries changes
to global ZFS behavior and we will have various internal checks
that check this value in datastore extend context methods.
- max_concurrent_jobs: the maximum number of concurrent rewrite
jobs (tier migrations for existing data).
- min_available_space: point in available space for a dataset where
tier migrations will error out.
The namespace will also support APIs for managing and querying
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[AMDGPU] Fix duplicate s_wait_asynccnt on gfx12-plus
S_WAIT_ASYNCCNT was missing from counterTypeForInstr(), so
isWaitInstr() did not recognize it as a wait instruction. On the
fixpoint algorithm's second pass over a loop body, the already-inserted
S_WAIT_ASYNCCNT was treated as a normal instruction, causing
WAIT_ASYNCMARK to be re-processed and a duplicate S_WAIT_ASYNCCNT to
be emitted.
Assisted-By: Claude Opus 4.6
NAS-140580 / 26.0.0-BETA.2 / Use mypy from pip (by themylogin) (#18663)
We already have it in the developer image
Original PR: https://github.com/truenas/middleware/pull/18661
Co-authored-by: themylogin <themylogin at gmail.com>
[Clang] prevent incorrect rejection of auto with reordered declaration specifiers in C23 (#177865)
Fixes #164121
---
This patch addresses the issue where `auto` was incorrectly rejected
with reordered declaration specifiers in C23.
[AMDGPU] Fix async operations in GlobalISel on gfx12-plus
For GFX1250 async LDS intrinsics, map the LDS pointer operand to VGPR
instead of SGPR. These instructions use $vdst/$vdata (VGPROp_32)
for the LDS address, unlike the pre-GFX12 variants which use M0 (SGPR).
Assisted-By: Claude Opus 4.6
libc: Add missing MLINK for stravis(3)
MFC after: 1 week
Fixes: 8dfeba04eb36 ("Update to a June 8th snapshot of (un)vis form NetBSD.")
Reviewed by: ziaee
Differential Revision: https://reviews.freebsd.org/D56260
