FreeBSD/ports dbc91f2 — net/telemt distinfo, net/telemt/files patch-src_daemon_pid__file.rs patch-src_proxy_tests_direct__relay__security__tests_anchored.rs

net/telemt: Update 3.5.7 => 3.5.9

Changelogs:
- https://github.com/telemt/telemt/releases/tag/3.5.8
- https://github.com/telemt/telemt/releases/tag/3.5.9

Commit log:
- https://github.com/telemt/telemt/compare/3.5.7...3.5.9

PR:             298965
Approved by:    osa, vvd (Mentors, implicit)
DeltaFile
+53-0net/telemt/files/patch-src_maestro_listeners_bind.rs
+46-0net/telemt/files/patch-src_util_secure__fs_write.rs
+17-3net/telemt/files/patch-src_proxy_tests_direct__relay__security__tests_anchored.rs
+20-0net/telemt/files/patch-src_util_secure__fs_path.rs
+11-0net/telemt/files/patch-src_daemon_pid__file.rs
+3-3net/telemt/distinfo
+150-61 files not shown
+151-77 files

LLVM/project 915afaa — llvm/lib/Target/AMDGPU AMDGPURegBankLegalize.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-anyext.mir regbankselect-mui.mir

[AMDGPU][GlobalISel] Keep typed LLTs in RegBankLegalize combines

The S1 cleanup combines in AMDGPURegBankLegalize built new registers
with an untyped s32, missed when lowering switched to extended LLTs.
The regbank combiner later unified these with typed registers, so
constrainRegAttrs retyped e.g. an i32 G_CTPOP result to s32, which
failed instruction selection.

Take the type from the source or destination register instead.

Change-Id: I06cfb7278af045dbaa3ca0cc6c77a3938f4cef01
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
DeltaFile
+86-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-combine-s1.mir
+7-6llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+7-6llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
+5-4llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
+107-185 files

LLVM/project 917a745 — llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU VOP3Instructions.td AMDGPULowerIntrinsics.cpp

[AMDGPU] Validate scale_sel in v_cvt_scale_*

These instructions can be block16 or block32 depending on the target
and scale_sel bits. Block16 is not supported in strict mode.

Re-enable the rest of the instructions in the strict mode but validate
the scale selector.
DeltaFile
+265-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk-scale-range.ll
+132-16llvm/test/MC/AMDGPU/gfx1250-strict_err.s
+62-0llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+47-0llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+7-9llvm/lib/Target/AMDGPU/VOP3Instructions.td
+6-8llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+519-333 files not shown
+528-489 files

FreeBSD/src 767cd9b — sys/amd64/conf GENERIC, sys/vm vm_swapout.c

vm_swapout: Fix the build without options RACCT

Reported by:    Jenkins
Fixes:          da0764f23554 ("vm_swapout: Restore handling of RLIMIT_RSS")
DeltaFile
+6-1sys/vm/vm_swapout.c
+3-3sys/amd64/conf/GENERIC
+9-42 files

LLVM/project 0c7c264 — llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp

Use isFixedVector instead of LLT equality
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+1-11 files

LLVM/project 4d70131 — llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU mad-mix.ll

[AMDGPU][GlobalISel] Fold neg/abs modifiers when mad-mix selects the low half

selectVOP3PMadMixModsImpl re-runs the fneg/fabs match after rewriting Src
to the 32-bit register the 16-bit value is a half of, but only did so on
the isExtractHiElt path, not for isExtractLoElt.

The two halves are not symmetric. An fneg/fabs of a 32-bit float only
touches bit 31, which is the sign bit of the high half, so folding it
into a modifier on the selected high half is correct. The low half's sign
bit is bit 15, which such an fneg/fabs leaves alone, so only a modifier
that acts on each 16-bit element can be folded there. So the source must be
a 2 x 16-bit vector to fold it.
DeltaFile
+972-0llvm/test/CodeGen/AMDGPU/mad-mix.ll
+252-257llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+20-22llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+10-16llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
+9-6llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+1,263-3015 files

LLVM/project 72c6b3b — llvm/lib/Transforms/InstCombine InstCombineSelect.cpp, llvm/test/Transforms/InstCombine truncating-saturate.ll

[InstCombine] Handle select-like i1 sext/zexts in canonicalizeClampLike (#227067)

canonicalizeClampLike matches a select of a select. But if the inner
select has an i1 result type it will be canonicalized to a sext or zext
of the condition. In FFmpeg there is a clamping pattern that shifts the
inverted bits instead of the negated, and the inner select ends up being
canonicalized this way: https://godbolt.org/z/5q8bx69x3

This teaches canonicalizeClampLike to use m_SelectLike to catch these
cases too.
DeltaFile
+47-22llvm/test/Transforms/InstCombine/truncating-saturate.ll
+3-3llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+50-252 files

LLVM/project bad4daa — llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/lib/MC GOFFObjectWriter.cpp MCSymbolGOFF.cpp

Fix formatting
DeltaFile
+4-2llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+2-2llvm/lib/MC/MCSymbolGOFF.cpp
+2-2llvm/lib/MC/MCObjectFileInfo.cpp
+2-1llvm/lib/MC/GOFFObjectWriter.cpp
+10-74 files

FreeBSD/ports ddf4b46 — cad/openvsp Makefile distinfo

cad/openvsp: Update to 3.53.1

ChangeLog: https://github.com/OpenVSP/OpenVSP/releases/tag/OpenVSP_3.53.1

Bug Fixes:
 * Conformal Geoms of Wings had wrong spanwise extent
 * WireGeom feature lines not drawing correctly
DeltaFile
+3-3cad/openvsp/distinfo
+1-1cad/openvsp/Makefile
+4-42 files

LLVM/project 7aeadb3 — lldb/include/lldb/Host/common NativeThreadProtocol.h, lldb/source/Plugins/Process/Windows/Common NativeThreadWindows.h NativeThreadWindows.cpp

[lldb-server] Handle jThreadExtendedInfo
DeltaFile
+49-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+4-0lldb/source/Plugins/Process/Windows/Common/NativeThreadWindows.cpp
+3-0lldb/include/lldb/Host/common/NativeThreadProtocol.h
+2-0lldb/source/Utility/StringExtractorGDBRemote.cpp
+2-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
+2-0lldb/source/Plugins/Process/Windows/Common/NativeThreadWindows.h
+62-01 files not shown
+63-07 files

LLVM/project 99b0ac4 — llvm/test/Transforms/IndirectBrExpand basic.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+42-21llvm/test/Transforms/IndirectBrExpand/basic.ll
+42-211 files

LLVM/project bb7c11d — llvm/include/llvm/Frontend/OpenMP OMPDescriptors.h, llvm/lib/Frontend/OpenMP OMPDescriptors.cpp

[OpenMP] Remove redundant namespace qualifications, NFC
DeltaFile
+4-4llvm/include/llvm/Frontend/OpenMP/OMPDescriptors.h
+3-3llvm/lib/Frontend/OpenMP/OMPDescriptors.cpp
+7-72 files

LLVM/project a983e21 — lldb/source/Host/windows HostThreadWindows.cpp

[lldb][Windows] Fix import of NtQueryInformationThread
DeltaFile
+1-1lldb/source/Host/windows/HostThreadWindows.cpp
+1-11 files

LLVM/project 7d4bf8b — lldb/include/lldb/Host HostNativeThreadBase.h, lldb/include/lldb/Host/windows HostThreadWindows.h

[lldb][Windows] Move extended info to host thread
DeltaFile
+41-0lldb/source/Host/windows/HostThreadWindows.cpp
+1-37lldb/source/Plugins/Process/Windows/Common/TargetThreadWindows.cpp
+4-0lldb/source/Host/common/HostNativeThreadBase.cpp
+2-0lldb/include/lldb/Host/windows/HostThreadWindows.h
+2-0lldb/include/lldb/Host/HostNativeThreadBase.h
+50-375 files

FreeBSD/src f3d6bce — usr.sbin/zonectl/tests zonectl_test.sh

tests/zonectl: skip when geom_zoned module is missing

Approved by:    asomers
Sponsored by:   Netflix
Differential Revision:  https://reviews.freebsd.org/D60144
DeltaFile
+8-0usr.sbin/zonectl/tests/zonectl_test.sh
+8-01 files

LLVM/project 4a0e98b — clang/test/CodeGenHLSL/builtins RWBuffer-Interlocked.hlsl RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl, clang/test/SemaHLSL/BuiltIns ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl InterlockedCompareExchangeFloatBitwise-errors.hlsl

[HLSL] Add `InterlockedCompareExchangeFloatBitwise` function and resource methods (#222167)

This PR adds the `InterlockedCompareExchangeFloatBitwise` standalone
function
and resource methods. It completes the interlocked stack.

The operation matches `InterlockedCompareStoreFloatBitwise`, except that
it
reports the previous value. Clang bitcasts both float arguments to `i32`
before the `cmpxchg`, then bitcasts the extracted result back to `float`
before it stores it through the `original_value` reference parameter.

As with the compare-store form, DXC declares this function for 32-bit
float
alone, so the overload set is float only, and the operation reuses the
32-bit
integer DXIL operation, so it works from shader model 6.0 without
capability
bits.

    [2 lines not shown]
DeltaFile
+119-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchangeFloatBitwise-errors.hlsl
+43-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchangeFloatBitwise.hlsl
+42-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl
+32-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+25-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+10-0clang/test/CodeGenHLSL/builtins/RWBuffer-Interlocked.hlsl
+271-06 files not shown
+302-312 files

LLVM/project 1fbf812 — clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl InterlockedCompareStoreFloatBitwise.hlsl

[HLSL] Add `InterlockedCompareStoreFloatBitwise` function and resource methods (#222166)

This PR adds the `InterlockedCompareStoreFloatBitwise` standalone
function and
resource methods.

`cmpxchg` rejects a float operand, clang therefore
bitcasts both float arguments to `i32` before it emits the `cmpxchg`,
and the
backend only ever sees an integer compare exchange. No DXIL legalization
is
needed for this operation.

DXC declares this function for 32-bit float alone, with no integer
overload,
so the overload set here is float only. `half` and `double` are
rejected.

The operation reuses the 32-bit integer DXIL operation, so it needs no

    [6 lines not shown]
DeltaFile
+100-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
+39-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
+34-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
+30-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
+27-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
+16-6clang/lib/Sema/SemaHLSL.cpp
+246-67 files not shown
+319-713 files

LLVM/project 7f3fa13 — clang/lib/Sema HLSLExternalSemaSource.cpp SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl RWByteAddressBuffer-InterlockedCompareExchange.hlsl

[HLSL] Add `InterlockedCompareExchange` function and resource methods (#222165)

This PR adds the `InterlockedCompareExchange` standalone function and
resource
methods. The operation lowers to the same `cmpxchg monotonic` as
`InterlockedCompareStore`.

`InterlockedCompareExchange` reports the previous value, so an
`extractvalue`
reads it from the `cmpxchg` result and stores it through the
`original_value`
reference parameter.

The PR also adds the 64-bit `InterlockedCompareExchange64` methods,
which DXIL
gates on shader model 6.6.

Fixes: https://github.com/llvm/llvm-project/issues/99130
Assisted by: Github Copilot
DeltaFile
+93-81clang/lib/Sema/SemaHLSL.cpp
+113-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchange-errors.hlsl
+66-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchange.hlsl
+41-24clang/lib/Sema/HLSLExternalSemaSource.cpp
+44-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchange.hlsl
+40-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl
+397-1057 files not shown
+485-12213 files

LLVM/project 824500a — llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp

Re-check setting of AMODE.
DeltaFile
+2-2llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+2-21 files

Linux/linux a243ede — drivers/mtd mtdcore.c, drivers/mtd/chips cfi_cmdset_0001.c

Merge tag 'mtd/fixes-for-7.3-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD fixes from Miquel Raynal:
 "The most important set of fixes are around the handling of the QE bit
  in SPI NAND.

  There are also a couple of behavioral fixes (mutex issue in SPI-NOR,
  spurious bitflips on vf610_nfc, OOB bytes count in SPI NAND and
  cfi_cmdset stack usage).

  The rest is mostly AI fuzzing results"

* tag 'mtd/fixes-for-7.3-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
  mtd: spinand: Do not update the QE bit on devices without one
  mtd: spi-nor: core: Fix mutex leak in spi_nor_rww_start_exclusive()
  mtd: rawnand: cadence: Initialize IRQ state before requesting IRQ
  mtd: rawnand: vf610_nfc: fix false bitflips on reads of erased pages
  mtd: rawnand: vf610_nfc: fix reads on chips with more than 64 bytes of OOB
  mtd: spinand: fix zero oobavail when no ECC engine is used

    [7 lines not shown]
DeltaFile
+70-15drivers/mtd/nand/raw/vf610_nfc.c
+37-16drivers/mtd/nand/spi/core.c
+26-16drivers/mtd/chips/cfi_cmdset_0001.c
+7-0drivers/mtd/nand/ecc.c
+3-3drivers/mtd/nand/raw/cadence-nand-controller.c
+2-1drivers/mtd/mtdcore.c
+145-514 files not shown
+151-5410 files

LLVM/project 36ce993 — libcxx/docs/DesignDocs UniquePtrTrivialAbi.md

[libc++][docs] Address batch 2 review feedback
DeltaFile
+1-1libcxx/docs/DesignDocs/UniquePtrTrivialAbi.md
+1-11 files

LLVM/project d21e461 — clang/test/CodeGen/RISCV rvp-intrinsics.c, llvm/test/CodeGen/AMDGPU load-constant-i1.ll amdgcn.bitcast.512bit.ll

Merge cascade
DeltaFile
+42,441-42,426llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+7,527-7,623llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+4,095-8,355clang/test/CodeGen/RISCV/rvp-intrinsics.c
+4,036-4,380llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+2,544-2,872llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+2,603-2,582llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+63,246-68,2382,305 files not shown
+170,884-146,5602,311 files

LLVM/project 9bd49c7 —

[libc++][docs] Continue batch 2 rename after dependency update
DeltaFile
+0-00 files

LLVM/project 9d3159c — clang/test/CodeGen/RISCV rvp-intrinsics.c, llvm/test/CodeGen/AMDGPU load-constant-i1.ll amdgcn.bitcast.512bit.ll

Merge cascade
DeltaFile
+42,441-42,426llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+7,527-7,623llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+4,095-8,355clang/test/CodeGen/RISCV/rvp-intrinsics.c
+4,036-4,380llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+2,544-2,872llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+2,603-2,582llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+63,246-68,2382,305 files not shown
+170,884-146,5602,311 files

FreeBSD/ports d04628d — games/sgt-puzzles Makefile distinfo

games/sgt-puzzles: update 20260906 → 20260923
DeltaFile
+3-3games/sgt-puzzles/distinfo
+2-2games/sgt-puzzles/Makefile
+5-52 files

LLVM/project 9e17a9e — flang/lib/Evaluate fold-implementation.h, flang/test/Evaluate fold-conditional-arg.f90

[flang][Evaluate] Fold type-only inquiries of conditional arguments

Fold a reference to an intrinsic inquiry function whose result depends
only on the declared type, kind type parameters, or rank of an argument
when that argument is a conditional argument with a non-constant
condition:

  integer, parameter :: k = kind((flag ? a : b))

Every consequent-arg of a conditional argument has the same declared
type and kind type parameters (F2023 C1538) and the same rank unless
all of them are assumed-rank (C1539), so such an inquiry has the same
value whichever consequent-arg is chosen at run time.
FoldOperation(FunctionRef) folds the reference by substituting the
first consequent-arg for the conditional argument in a copy of the
reference and keeps the result when it is a constant.

The qualifying arguments are the dummy arguments that the intrinsic
table marks with ArgFlag::onlyConstantInquiry, which

    [34 lines not shown]
DeltaFile
+60-28flang/lib/Evaluate/fold-implementation.h
+71-0flang/test/Evaluate/fold-conditional-arg.f90
+68-0flang/test/Semantics/conditional-arg-inquiry.f90
+199-283 files

LLVM/project 838b328 — llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/lib/MC MCSymbolGOFF.cpp GOFFObjectWriter.cpp

[SystemZ][z/OS] Add AMODE to PR symbols

Contrary to the documentation, setting the AMODE at PR symbols is
required. The symptom is that references to variables `optind` and
`optarg` (from include `<getopt.h>`, the LE-provided C runtime)
results in "missing symbol" errors.
Fix is to add AMODE to PrAttr, analog to LdAttr.
DeltaFile
+4-3llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+4-2llvm/lib/MC/MCObjectFileInfo.cpp
+2-2llvm/test/CodeGen/SystemZ/zos-section-2.ll
+2-1llvm/lib/MC/MCSymbolGOFF.cpp
+2-1llvm/lib/MC/GOFFObjectWriter.cpp
+1-1llvm/test/tools/llvm-ar/zos-symattrs.test
+15-103 files not shown
+18-129 files

LLVM/project c889f53 — llvm/lib/CodeGen TwoAddressInstructionPass.cpp, llvm/test/CodeGen/AMDGPU twoaddr-insert-subreg-subrange.mir

TwoAddressInstructions: Fix subranges straddling the INSERT_SUBREG subreg index

Rewriting INSERT_SUBREG into a subregister COPY narrows the def from the
whole register down to one subreg index. The live interval fixup for that
only handled subranges entirely disjoint from the inserted lane mask, so a
partially overlapping subrange keeps a value whose def no longer writes all
of its lanes.

The stale value makes the lanes outside the inserted subregister look
defined by the COPY, so the copy that actually provides them ends up dead
and its value is lost. Refine the subranges against the subreg index before
narrowing the def, leaving each one either fully redefined by the COPY or
untouched by it.

Fixes a miscompile reported on RISC-V and restores the pre-6286f77214be
output of Thumb2/mve-vst2.ll, Thumb2/mve-vst3.ll and PowerPC/dmr-enable.ll.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+18-17llvm/test/CodeGen/Thumb2/mve-vst3.ll
+29-0llvm/test/CodeGen/AMDGPU/twoaddr-insert-subreg-subrange.mir
+29-0llvm/test/CodeGen/RISCV/twoaddr-insert-subreg-subrange.mir
+17-8llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+8-8llvm/test/CodeGen/PowerPC/dmr-enable.ll
+4-4llvm/test/CodeGen/Thumb2/mve-vst2.ll
+105-376 files

NetBSD/pkgsrc-wip 4b70fb7 — miranda Makefile PLIST, miranda/patches patch-just.c patch-steer.c

Add (so far not quite working) miranda, the inspiration for Haskell.
DeltaFile
+179-0miranda/patches/patch-lex.c
+146-0miranda/PLIST
+60-0miranda/patches/patch-Makefile
+35-0miranda/Makefile
+30-0miranda/patches/patch-steer.c
+27-0miranda/patches/patch-just.c
+477-04 files not shown
+516-010 files

LLVM/project a367d92 — libc/test/UnitTest SIMDMatcher.h

[libc][mathvec] Remove unneeded inf check in within_ulp_tolerance (#227459)
DeltaFile
+0-4libc/test/UnitTest/SIMDMatcher.h
+0-41 files