LLVM/project 07f7b03llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge remote-tracking branch 'origin/users/ziqingluo/PR-172429193-2-split-1' into users/ziqingluo/PR-172429193-2-split-2

 Conflicts:
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevelFormat.h
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-03,038 files not shown
+986,216-65,9093,044 files

NetBSD/src UxE4gKpsys/modules Makefile.assym

   Handle the new common m68k genassym.cf
VersionDeltaFile
1.7+5-1sys/modules/Makefile.assym
+5-11 files

NetBSD/pkgsrc 48W4KTldoc CHANGES-2026

   Updated databases/redis, databases/py-redis
VersionDeltaFile
1.2508+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc 5eibdOFdatabases/py-redis PLIST distinfo

   py-redis: updated to 7.4.0

   7.4.0

   Bug Fixes

   Fix AttributeError in cluster metrics recording when connection is None or ClusterNode object instance is used to extract the connection info
   Fixing security concern in repr methods for ConnectionPools - passwords might leak in plain text logs
   Refactored connection count and SCH metric collection

   Experimental Features

   -Refactored health check logic for MultiDBClient
VersionDeltaFile
1.17+31-4databases/py-redis/PLIST
1.53+4-4databases/py-redis/distinfo
1.58+2-2databases/py-redis/Makefile
+37-103 files

LLVM/project 4976de9llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/RISCV/rvv vector-interleave.ll

remove opt

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+731-1,359llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+1,957-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
+1,950-0llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+36,926-2,9262,036 files not shown
+103,072-36,4012,042 files

LLVM/project 3fb1444llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/RISCV/rvv vector-interleave.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+731-1,359llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+1,957-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
+1,950-0llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+36,926-2,9262,036 files not shown
+103,050-36,3802,042 files

LLVM/project 0fb1f2dllvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/RISCV/rvv vector-interleave.ll

remove opt

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+731-1,359llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+1,957-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
+1,950-0llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+36,926-2,9262,036 files not shown
+103,050-36,3802,042 files

LLVM/project a85d39dllvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/RISCV/rvv vector-interleave.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+731-1,359llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+1,957-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
+1,950-0llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+36,926-2,9262,031 files not shown
+102,874-36,2652,037 files

NetBSD/pkgsrc sjx3BQ2databases/redis distinfo Makefile, databases/redis/patches patch-src_config.h

   redis: updated to 8.6.2

   Redis 8.6.1    Released Mon 23 Feb 2026 10:00:00 IST

   Upgrade urgency SECURITY: There is a security fix in the release

   Security fixes

   - A user can manipulate data read by a connection by injecting \r\n sequences into a Redis error reply

   Bug fixes

   - `HOTKEYS`: The `INFO` command may display module information, and the missing `HOTKEYS HELP` subcommand has been added
   - Bug in RDB loading prevented hash table expansion, increasing load time


   Redis 8.6 GA (8.6.0)    Released Tue 10 Feb 2026 16:00:00 IST

   This is the General Availability release of Redis 8.6 in Redis Open Source.

    [10 lines not shown]
VersionDeltaFile
1.92+4-5databases/redis/distinfo
1.102+2-2databases/redis/Makefile
1.4+1-1databases/redis/patches/patch-src_config.h
+7-83 files

NetBSD/pkgsrc dvCbPokdoc CHANGES-2026

   Updated devel/meson, devel/py-cachetools, databases/py-psycopg2
VersionDeltaFile
1.2507+4-1doc/CHANGES-2026
+4-11 files

NetBSD/pkgsrc bgkGS8adatabases/py-psycopg2 distinfo Makefile

   py-psycopg2: updated to 2.9.12

   2.9.12

   - Fix infinite loop with malformed interval
VersionDeltaFile
1.51+4-4databases/py-psycopg2/distinfo
1.65+2-2databases/py-psycopg2/Makefile
+6-62 files

NetBSD/pkgsrc xeVQFYedevel/py-cachetools distinfo Makefile

   py-cachetools: updated to 7.0.6

   v7.0.6 (2026-04-20)

   - Minor code improvements.
   - Update project URLs.
   - Update CI environment.
VersionDeltaFile
1.33+4-4devel/py-cachetools/distinfo
1.34+2-2devel/py-cachetools/Makefile
+6-62 files

NetBSD/pkgsrc hMFdkccdevel/meson distinfo Makefile

   meson: updated to 1.11.1

   1.11.1
   Bug fixes
VersionDeltaFile
1.80+4-4devel/meson/distinfo
1.93+2-2devel/meson/Makefile
+6-62 files

NetBSD/pkgsrc 8OwTrR0doc CHANGES-2026

   Updated devel/git, sysutils/py-borgbackup
VersionDeltaFile
1.2506+3-1doc/CHANGES-2026
+3-11 files

LLVM/project a69a290clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel EntityPointerLevel.cpp

a class should own a std::function instead of a llvm::function_ref
DeltaFile
+3-3clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
+3-31 files

LLVM/project 2851ad5llvm/lib/Target/AMDGPU SIRegisterInfo.cpp

Fix comments
DeltaFile
+4-6llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+4-61 files

LLVM/project cd5634aclang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.cpp SSAFAnalysesCommon.h

Move templates into clang::ssaf
DeltaFile
+17-0clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
+4-5clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
+1-0clang/lib/ScalableStaticAnalysisFramework/Analyses/CMakeLists.txt
+22-53 files

LLVM/project 83f8eeelld/ELF Driver.cpp Config.h

[ELF] Parallelize input file loading (#191690)

During `createFiles`, `addFile()` records a `LoadJob` for each
non-script input (archive, relocatable, DSO, bitcode, binary) with a
state-machine snapshot (`inWholeArchive`, `inLib`, `asNeeded`,
`withLOption`, `groupId`) and expands them on worker threads in
`loadFiles()`. Linker scripts are still processed inline since their
`INPUT()` and `GROUP()` commands recursively call `addFile()`.

Outside `createFiles()`, `loadFiles()` is called with a single job and
drained immediately (`deferLoad` is false). Two cases:
- `addDependentLibrary()`: `.deplibs` sections trigger `addFile()`
  during the serial `doParseFiles()` loop.
- `--just-symbols`: pushes files directly, bypassing
`addFile`/`LoadJob`.

Thread-safety:
- A mutex serializes `BitcodeFile` / fatLTO constructors that call
  `ctx.saver` / `ctx.uniqueSaver`. Zero contention on pure ELF links.

    [23 lines not shown]
DeltaFile
+155-103lld/ELF/Driver.cpp
+20-2lld/ELF/Config.h
+1-1lld/ELF/InputFiles.h
+1-1lld/ELF/InputFiles.cpp
+177-1074 files

LLVM/project b2d7d89llvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp, llvm/test/CodeGen/AMDGPU rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll

Revert "[AMDGPU] Fixed verifier crash because of multiple live range components." (#193135)

Reverts llvm/llvm-project#190719

The Buildbot has detected a new failure on builder
sanitizer-aarch64-linux-bootstrap-hwasan while building llvm.
DeltaFile
+0-459llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir
+0-148llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
+0-19llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+0-6263 files

LLVM/project 4712ca8mlir/lib/Dialect/XeGPU/Transforms XeGPULayoutImpl.cpp, mlir/lib/Dialect/XeGPU/Utils XeGPUUtils.cpp

[MLIR][XeGPU] Recover temporary layout from Anchor Layout (#191947)

This PR refactor the recoverTemporaryLayout() method so that the
temporary layout is recovered from anchor layout, not from any user
specified temporary layout.
DeltaFile
+257-49mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+182-1mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+150-0mlir/test/Dialect/XeGPU/xegpu-recover-layout.mlir
+33-0mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
+11-19mlir/test/Dialect/XeGPU/sg-to-wi-experimental.mlir
+19-5mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
+652-748 files not shown
+683-12114 files

LLVM/project ba3ceb8clang-tools-extra/clangd ProjectModules.cpp ProjectModules.h, clang-tools-extra/clangd/unittests PrerequisiteModulesTest.cpp

[NFC] [clangd] [C++20] [Modules] Introduce ProjectModules::getModuleNameState interface (#193133)

A hole in the current design is that, we assumed there is no duplicated
module name in different module interface in the same project.

This is not true techniquelly. ISO disallows duplicated module names in
a linked program. But we can have multiple program in a project. It will
be fine if they are not linked together. And in practice, it will be
fine if the symbols are masked and if these module interface units are
not showing in the same context of a single translation unit.

I am trying to improve this. This patch tries to add some NFC things to
reduce further patch size.

AI assisted.
DeltaFile
+32-14clang-tools-extra/clangd/ProjectModules.cpp
+9-0clang-tools-extra/clangd/ProjectModules.h
+4-0clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
+45-143 files

OpenBSD/ports aviuzeNsysutils/rclone distinfo Makefile

   Update to rclone-1.73.5

   CVE-2026-41176
   rc: add AuthRequired to options/set to prevent auth bypass
   rc: snapshot NoAuth at startup to prevent runtime auth bypass

   CVE-2026-41179
   operations: add AuthRequired to operations/fsinfo to prevent backend
   creation

   Changelog: https://rclone.org/changelog/#v1-73-5-2026-04-19

   OK sthen@
VersionDeltaFile
1.64+4-4sysutils/rclone/distinfo
1.74+1-1sysutils/rclone/Makefile
+5-52 files

LLVM/project ae8979dllvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp, llvm/test/CodeGen/AMDGPU rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll

Revert "[AMDGPU] Fixed verifier crash because of multiple live range componen…"

This reverts commit b39dfca39fa794d66580238fb382477e34fbd093.
DeltaFile
+0-459llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-mir.mir
+0-148llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
+0-19llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+0-6263 files

LLVM/project b0b3e50llvm/lib/Target/NVPTX NVPTXInstrInfo.cpp NVPTXInstrInfo.td, llvm/test/CodeGen/NVPTX machine-cse-predicate-inversion-rollback.mir machine-cse-predicate-inversion-multiple-users.ll

update rollback logic and add test exercising it
DeltaFile
+66-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-rollback.mir
+17-19llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+9-7llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
+1-1llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+93-274 files

LLVM/project b77ccdfllvm/test/CodeGen/NVPTX machine-cse-predicate-inversion-float16.ll machine-cse-predicate-inversion-bfloat16.ll

[NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates

Inverted predicates can be used freely in PTX. If we can invert a
predicate and CSE the generating instruction we can save calculating
the inverse.

Teach the NVPTX commuteInstructionImpl that SETP instructions can be
inverted to allow CSEing with previous SETP that match the inverted
form. This also inverts the branch users of the predicate to maintain
correctness.

Currently only allow the SETP inversion if all users are branches.
Future work can extend this to sel and not instructions.

Made-with: Cursor
DeltaFile
+695-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
+695-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
+679-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
+663-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
+437-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
+437-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
+3,606-013 files not shown
+5,908-419 files

LLVM/project e4456ballvm/lib/Target/NVPTX NVPTXInstrInfo.cpp

clang-format
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+1-4llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+1-41 files

LLVM/project 1bfcddcclang-tools-extra/clang-tidy add_new_check.py, clang-tools-extra/docs/clang-tidy/checks list.rst

[clang-tidy][NFC] Fix list.rst and improve alias detection of `add_new_check.py` (#192228)

Follow up of https://github.com/llvm/llvm-project/pull/192224.

This commit does two things:

- Replace the original alias detection based on `:http-equiv` (we may
remove these completely in the future) with a method of directly
matching the documentation section.
- Update the list.rst

---------

Co-authored-by: Victor Chernyakin <chernyakin.victor.j at outlook.com>
DeltaFile
+120-109clang-tools-extra/clang-tidy/add_new_check.py
+2-2clang-tools-extra/docs/clang-tidy/checks/list.rst
+122-1112 files

LLVM/project 23f2a0allvm/lib/Target/NVPTX NVPTXInstrInfo.cpp NVPTXInstrInfo.td, llvm/lib/Target/NVPTX/MCTargetDesc NVPTXInstPrinter.cpp

Move predicate inversion to a flag
DeltaFile
+16-18llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+8-4llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+4-4llvm/test/CodeGen/NVPTX/branch-fold.mir
+4-4llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
+7-0llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
+2-2llvm/test/CodeGen/NVPTX/switch-loop-header.mir
+41-322 files not shown
+44-338 files

LLVM/project 4acbf99clang-tools-extra/clangd ProjectModules.cpp ScanningProjectModules.cpp, clang-tools-extra/clangd/unittests PrerequisiteModulesTest.cpp

[NFC] [clangd] [C++20] [Modules] Rename and move scanningProjectModules (#193128)

I am going to add more stuff to ProjectModules and the current structure
and the file name scanningProjectModules may be confusing.

This NFC patch changes that.
DeltaFile
+241-0clang-tools-extra/clangd/ProjectModules.cpp
+0-240clang-tools-extra/clangd/ScanningProjectModules.cpp
+0-26clang-tools-extra/clangd/ScanningProjectModules.h
+5-0clang-tools-extra/clangd/ProjectModules.h
+3-2clang-tools-extra/clangd/unittests/PrerequisiteModulesTest.cpp
+1-2clang-tools-extra/clangd/GlobalCompilationDatabase.cpp
+250-2701 files not shown
+251-2717 files

LLVM/project 423d105llvm/test/CodeGen/RISCV/rvv vitofp-sdnode.ll vfptoi-sdnode.ll, llvm/test/Transforms/LoopVectorize/ARM mve-interleaved-cost.ll

Merge branch 'main' into users/efric/rocdl-dot
DeltaFile
+878-428llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862-426llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+428-526llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
+668-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
+619-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+4,033-1,392372 files not shown
+13,739-5,831378 files