[flang][cuda] Fix matching distance for use_device and none (#223849)
https://docs.nvidia.com/hpc-sdk/compilers/cuda-fortran-prog-guide/#unified-data
the table set the matching distance for actual `use_device` and dummy
argument `none` to 1 but the implementation set it to 3.
@wangzpgi Was there a specific reason to set 3 instead of 1?
[RISCV] Call DecodeGPRPairRegisterClass from DecodeGPRPairCRegisterClass. NFC (#223882)
GPRPairC is a subset of GPRPair. We just need to do the range check and
let DecodeGPRPairRegisterClass do the rest of the work.
[RISCV] Remove Zicfiss DecoderNamespace. NFC (#223891)
This used to be needed to prioritize c.sspopchk and c.sspush over
c.mop.1 and c.mop.5, but those are treated as InstAliases now.
Make writes of the hibernate signature go through the I/O page of the
piglet. This fixes a potential issue on arm64 where the kernel might
have been loaded into memory that isn't DMA reachable. It will also
help with implementing some future changes to make the side-effect free
I/O functions support hardware without cache-coherent DMA or IOMMUs.
ok deraadt@, mlarkin@
Add a few more fields directly to exec_package so that the front-end
and back-end of the ELF code doesn't need to communicate them via an
malloc'd structure. Much simpler.
ok kettenis
[clang] Fix handling of constexpr static data member template. (#220469)
[temp.expl.spec] says "An explicit specialization of a static data
member of a template or an explicit specialization of a static data
member template is a definition if the declaration includes an
initializer." The code did not match this rule for constexpr variables.
The check in question was only supposed to match the cases from
[depr.static.constexpr].
Fixes #219796
[AMDGPU] Add block carried latency to CoExecSched (#192324)
This adds some rudimentary logic to check for load dependencies across
blocks. Since the scheduling algorithm is local scheduling per region,
we do not have about latencies carried from other blocks. Rather than
constructing a global DAG to accurately measure these latencies, this PR
uses a heuristic to estimate the incoming latency.
We limit our incoming dependencies to load instructions, as these are
expected to be the ones that cause problems. This uses the full latency
of the instruction as the incoming latency to cover. We check for any
use that occurred later in the def block - if we find such a use then we
do not have incoming latency as we have already waited for the load.
Using the incoming latency assumes that the load is the last instruction
in the block, and that the branch takes 0 cycles. Aside from not fully
understanding the dependencies of other blocks, a challenge in defining
a more accurate incoming latency is that it is possible that the block
with the load may be rescheduled.
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[CIR] Address review on the x86-64 va_arg expansion
rewriteVAArg had grown to 254 lines, with the register arm alone taking
105 of them inside a nested builder callback. The round-up, the overflow
arm, the register gate, the pair reassembly, the temp copy and the cursor
write-back are now named functions taking a small context struct, and the
48 and 176 register-file bounds sit in one place.
Four fixes come with it.
A va_arg of an empty record yielded a dummy value, which is an alloca and
a load of uninitialized memory. It now yields the poison the file already
hands to an ignored block argument.
The register slot size came from the integer register count while the
address it described came from whichever area the vector count selected,
so the two disagreed for a fetch needing one register of each class. Only
one class is ever in play, since a fetch needing both is a coerced pair
that takes the reassembly path, and an assert now says so. Reachable
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[CMake] Clean up factored lit dependency names
Replace the opaque SHA1-based stamp and anchor names with readable names
based on the lit project. Document why the symbolic outputs and internal
anchor target are needed.
Warn once when the active project minimum reaches CMake 3.27, making the
compatibility fallback obsolete.
