LLVM/project 15d7196lld/ELF/Arch X86_64.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+1-1lld/ELF/Arch/X86_64.cpp
+1-11 files

LLVM/project 1e4f189lld/ELF/Arch X86_64.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+1-1lld/ELF/Arch/X86_64.cpp
+1-11 files

LLVM/project 2c820e8lld/ELF/Arch X86_64.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+1-1lld/ELF/Arch/X86_64.cpp
+1-11 files

LLVM/project 39524e9lld/ELF/Arch X86_64.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+1-1lld/ELF/Arch/X86_64.cpp
+1-11 files

LLVM/project 6232541lld/ELF/Arch X86_64.cpp

DenseMap

Created using spr 1.3.6-beta.1
DeltaFile
+1-1lld/ELF/Arch/X86_64.cpp
+1-11 files

LLVM/project 8e41b9cclang/lib/Parse ParseDecl.cpp ParseDeclCXX.cpp

minor comment corrections
DeltaFile
+1-1clang/lib/Parse/ParseDecl.cpp
+1-1clang/lib/Parse/ParseDeclCXX.cpp
+2-22 files

LLVM/project 866bdfallvm/lib/Analysis ConstantFolding.cpp, llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU wave.reduce.ll

[AMDGPU] Unmark wave reduce intrinsics for constant folding

The `add`, `sub`, and `xor` wave reduction intrinsics cannot
be constant folded, as `add` and `sub` need to be multipled
by the number of active lanes, and `xor` depends on the parity
of the number of active lanes.
DeltaFile
+24-12llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/wave.reduce.ll
+0-6llvm/lib/Analysis/ConstantFolding.cpp
+24-182 files

LLVM/project 31bacc1clang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.cpp

Merge branch 'users/ziqingluo/PR-172429193-2-split-3' into users/ziqingluo/PR-172429193-2-split-4

 Conflicts:
        clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
DeltaFile
+1-0clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
+1-01 files

LLVM/project bc19b3dclang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.cpp

fix build issue
DeltaFile
+1-0clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
+1-01 files

LLVM/project 699d592clang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.cpp

fix build issue
DeltaFile
+1-0clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
+1-01 files

LLVM/project 773a14blld/ELF ScriptParser.cpp

[ELF] Fix heap-use-after-free with INPUT(relative-path) (#193146)

`ScriptParser::addFile` Case 4 (relative path resolved against the
script's parent directory) passes a `SmallString<0>` stack local by
StringRef, causing asan error after #191690.

Fix with ctx.saver similar to other cases.
DeltaFile
+1-1lld/ELF/ScriptParser.cpp
+1-11 files

LLVM/project 66f2945llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge remote-tracking branch 'origin/users/ziqingluo/PR-172429193-2-split-3' into users/ziqingluo/PR-172429193-2-split-4

 Conflicts:
        clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-03,040 files not shown
+986,232-65,9253,046 files

LLVM/project 7f6896allvm/lib/Target/X86/MCTargetDesc X86MCTargetDesc.cpp X86MCAsmInfo.cpp, llvm/test/MC/X86 intel-syntax-quote-reserved.s

[X86] Quote symbol names that collide with registers/keywords in Intel syntax (#186570)

When outputting Intel syntax assembly, symbol names that match register
names (e.g., `rsi`, `rax`) or keywords (`byte`, `ptr`, etc.) must be
quoted, otherwise the assembler parses them as registers/keywords
instead of symbol references.

Fix this by populating MCAsmInfo::ReservedIdentifiers with all X86
register names and Intel syntax keywords. isValidUnquotedName() checks
this set and forces quoting when a symbol name matches.

```
% cat rsi.c
void rsi(void); void foo(void) { rsi(); }

// old clang
% clang -c rsi.c -save-temps -masm=intel -fno-pic -o - | llvm-objdump -dr -
...
       4: ff d6                         callq   *%rsi

    [14 lines not shown]
DeltaFile
+122-0llvm/test/MC/X86/intel-syntax-quote-reserved.s
+47-11llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+28-0llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
+9-0llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h
+206-114 files

LLVM/project 5e19d35clang/lib/Parse ParseDecl.cpp ParseDeclCXX.cpp, clang/test/SemaCXX gh187664.cpp

[clang][NFC] Prevent scope pollution from repeat type specifiers

Fixes #187664

When parsing `type-specifier {class,union,struct,enum,etc} nested-name`
ParseClassSpecifier and ParseEnumSpecifier both operated on the current
declaration scope on the assumption that they were the only type
specifier. Of course in incorrect code that assumption is false, and
as a result when parsing the name specifier they would pollute the
the real scope.

This is not relevant to the semantic correctness: the error is detected
and reported. The problem is that the subsequent state is not correct,
though not in a way that impacts functional behavior of release builds.

In assertion builds however this is detected (via a somewhat obtuse path)
when we attempt to plant namespace location information from the invalid
declaration on the initial declaration.


    [3 lines not shown]
DeltaFile
+76-0clang/test/SemaCXX/gh187664.cpp
+5-1clang/lib/Parse/ParseDecl.cpp
+5-1clang/lib/Parse/ParseDeclCXX.cpp
+86-23 files

LLVM/project 43f8208llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge branch 'users/ziqingluo/PR-172429193-2-split-2' into users/ziqingluo/PR-172429193-2-split-3

 Conflicts:
        clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
        clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-03,040 files not shown
+986,235-65,9253,046 files

LLVM/project 4b9cac9llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] Unmark wave reduce intrinsics for constant folding

The `add`, `sub`, and `xor` wave reduction intrinsics cannot
be constant folded, as `add` and `sub` need to be multipled
by the number of active lanes, and `xor` depends on the parity
of the number of active lanes.
DeltaFile
+352-172llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+337-168llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+327-156llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+229-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+228-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+228-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+1,701-8924 files not shown
+2,383-1,29410 files

LLVM/project e983c47llvm/lib/Analysis ConstantFolding.cpp

[AMDGPU] Unmark wave reduce intrinsics for constant folding

The `add`, `sub`, and `xor` wave reduction intrinsics cannot
be constant folded, as `add` and `sub` need to be multipled
by the number of active lanes, and `xor` depends on the parity
of the number of active lanes.
DeltaFile
+0-6llvm/lib/Analysis/ConstantFolding.cpp
+0-61 files

OpenBSD/src eycBTRfregress/lib/libcrypto/pkcs7 pkcs7test.c

   pkcs7test: factor main into a helper so we can add some unit tests easily
VersionDeltaFile
1.6+13-3regress/lib/libcrypto/pkcs7/pkcs7test.c
+13-31 files

LLVM/project e9d24b0clang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.cpp

fix build issue
DeltaFile
+2-0clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.cpp
+2-01 files

NetBSD/pkgsrc 2R4Eo1xdoc CHANGES-2026

   doc: Updated games/vms-empire to 1.21
VersionDeltaFile
1.2509+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc KIiZyjBgames/vms-empire Makefile distinfo, games/vms-empire/patches patch-aa patch-usermove.c

   vms-empire: update to 1.21.

   Yet more code hardening.
   Documentation fully cobveted to asciidoc.
VersionDeltaFile
1.9+43-6games/vms-empire/patches/patch-aa
1.21+9-6games/vms-empire/Makefile
1.16+5-10games/vms-empire/distinfo
1.3+1-2games/vms-empire/PLIST
1.5+1-1games/vms-empire/patches/patch-usermove.c
1.5+1-1games/vms-empire/patches/patch-edit.c
+60-263 files not shown
+63-299 files

LLVM/project 07f7b03llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge remote-tracking branch 'origin/users/ziqingluo/PR-172429193-2-split-1' into users/ziqingluo/PR-172429193-2-split-2

 Conflicts:
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevelFormat.h
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-03,038 files not shown
+986,216-65,9093,044 files

NetBSD/src UxE4gKpsys/modules Makefile.assym

   Handle the new common m68k genassym.cf
VersionDeltaFile
1.7+5-1sys/modules/Makefile.assym
+5-11 files

NetBSD/pkgsrc 48W4KTldoc CHANGES-2026

   Updated databases/redis, databases/py-redis
VersionDeltaFile
1.2508+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc 5eibdOFdatabases/py-redis PLIST distinfo

   py-redis: updated to 7.4.0

   7.4.0

   Bug Fixes

   Fix AttributeError in cluster metrics recording when connection is None or ClusterNode object instance is used to extract the connection info
   Fixing security concern in repr methods for ConnectionPools - passwords might leak in plain text logs
   Refactored connection count and SCH metric collection

   Experimental Features

   -Refactored health check logic for MultiDBClient
VersionDeltaFile
1.17+31-4databases/py-redis/PLIST
1.53+4-4databases/py-redis/distinfo
1.58+2-2databases/py-redis/Makefile
+37-103 files

LLVM/project 4976de9llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/RISCV/rvv vector-interleave.ll

remove opt

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+731-1,359llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+1,957-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
+1,950-0llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+36,926-2,9262,036 files not shown
+103,072-36,4012,042 files

LLVM/project 3fb1444llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/RISCV/rvv vector-interleave.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+731-1,359llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+1,957-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
+1,950-0llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+36,926-2,9262,036 files not shown
+103,050-36,3802,042 files

LLVM/project 0fb1f2dllvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/RISCV/rvv vector-interleave.ll

remove opt

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+731-1,359llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+1,957-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
+1,950-0llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+36,926-2,9262,036 files not shown
+103,050-36,3802,042 files

LLVM/project a85d39dllvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/RISCV/rvv vector-interleave.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+731-1,359llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+1,957-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-rem.ll
+1,950-0llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+36,926-2,9262,031 files not shown
+102,874-36,2652,037 files

NetBSD/pkgsrc sjx3BQ2databases/redis distinfo Makefile, databases/redis/patches patch-src_config.h

   redis: updated to 8.6.2

   Redis 8.6.1    Released Mon 23 Feb 2026 10:00:00 IST

   Upgrade urgency SECURITY: There is a security fix in the release

   Security fixes

   - A user can manipulate data read by a connection by injecting \r\n sequences into a Redis error reply

   Bug fixes

   - `HOTKEYS`: The `INFO` command may display module information, and the missing `HOTKEYS HELP` subcommand has been added
   - Bug in RDB loading prevented hash table expansion, increasing load time


   Redis 8.6 GA (8.6.0)    Released Tue 10 Feb 2026 16:00:00 IST

   This is the General Availability release of Redis 8.6 in Redis Open Source.

    [10 lines not shown]
VersionDeltaFile
1.92+4-5databases/redis/distinfo
1.102+2-2databases/redis/Makefile
1.4+1-1databases/redis/patches/patch-src_config.h
+7-83 files