[libc++][docs] Remove stale release notes from toctree
#234169 deleted the release notes for LLVM 20, 21 and 22 but left them
listed in the hidden toctree in ReleaseNotes.rst. Sphinx reports each
as a nonexisting document, which fails the documentation build because
warnings are errors.
LLM-aided
[libc++] Request refinement commits from the benchmark cron job (#234739)
This closes the loop for automatic refinement of benchmark data. It adds
a CI job that determines which commits to bisect based on the
changepoints we find in the existing data, and incorporates them into
the set of commits to measure.
The result is that we automatically bisect commits between which a
significant changepoint is detected.
Assisted by Claude
[docs] Enable absolute LLVM documentation link checks (#222508)
Enable the absolute documentation URL warning for the LLVM Sphinx docs
build.
Part of #214861
[docs] Finish MyST migration for leftover docs
Clean up the rst2myst output for the lldb man pages, the VariableNames
proposal, and the lit, gn, cmake and OpenMP Modules READMEs. The man
pages keep generating byte-identical roff, and the READMEs use plain
GitHub-flavored Markdown because they are viewed on GitHub and are not
part of a Sphinx build. Declare Markdown as lit's long_description
content type now that its README is Markdown.
LLM-aided
[SCEV] Derive x >=s 0 from x <u y and y <=u 2^(n-1)
Let n be the bit width of x and y. If x <u y and y <=u 2^(n-1), then
x <u 2^(n-1), so x >=s 0. Here y <=u 2^(n-1) means y >=s 0 or
y == INT_MIN. In the same way, if x <=u y and y <u 2^(n-1), then
x >=s 0.
This lets a guard like x <u len prove x >=s 0 when len is non-negative.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][IndVars][NFC] Add tests for x >=s 0 from x <u y with swapped operands
Let n be the bit width of x and y. If x <u y and y <=u 2^(n-1), then
x >=s 0. SCEV can't prove this yet when the operands of the compare to
prove are in the opposite order to the guard, e.g. 0 <=s x with
x <u y known.
Add tests for it.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][IndVars][NFC] Add tests for x >=s 0 from x <u y and y <=u 2^(n-1)
Let n be the bit width of x and y. If x <u y and y <=u 2^(n-1), then
x >=s 0. SCEV can't prove this yet.
Add tests for it.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV] Prove signed/unsigned implications in either operand order
SCEV could prove these implications only with the operands in the same
order:
- If a <u b and a, b have the same sign, then a <s b.
- If a <s b and a, b have the same sign, then a <u b.
- If a <u b and b >=s 0, then a <s b.
- If a <s b and b <s 0, then a <u b.
For example, it proved a <s b from a <u b and b >=s 0, but not b >s a.
Now it proves them in either order.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][NFC] Factor isImpliedCondViaSignFlippedPred out of isImpliedCondBalancedTypes
Move the code that proves a condition from a found condition with the
other signedness into a new private function.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][IndVars][NFC] Add tests for implied conditions with different signedness
SCEV can prove some signed conditions from unsigned ones and the other
way around. For example, it proves a <s b from a <u b and b >=s 0. But
it fails when the operands are in the opposite order, like b >s a.
Add tests for this.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[ARM] Implement INIT_TRAMPOLINE and ADJUST_TRAMPOLINE
ARM never handled ISD::INIT_TRAMPOLINE or ISD::ADJUST_TRAMPOLINE. The
legalizer treats a "legal" trampoline node as Custom, so any use of
llvm.init.trampoline reached ARMTargetLowering::LowerOperation's default
case and crashed with "Don't know how to custom lower this!". Front ends
that use trampolines (Flang's internal procedures, GNAT-LLVM's nested
subprograms, and Julia's closures) couldn't target 32-bit ARM.
Lower them with the same 16-byte sequences GCC uses. Both load the static
chain into r12, which ARMCallingConv.td already assigns to 'nest'
parameters, and then load the nested function's address into pc:
ARM: ldr r12, [pc] ldr pc, [pc] .word nest, fptr
Thumb-2: ldr.w r12, [pc, #4] ldr.w pc, [pc, #4] .word nest, fptr
Loading pc interworks from ARMv5T on, so either sequence can reach an ARM
or a Thumb function. Thumb-2 code uses the Thumb-2 sequence, and
ADJUST_TRAMPOLINE sets the low bit of its address so it's entered in Thumb
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TableGen: Skip disjoint register classes before intersecting them
inferCommonSubClass intersects the member lists of a register class
with every other class, and most pairs are disjoint. Check that with
the member bit vectors first, which avoids loading the members and
allocating the intersection.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 576 346 111
After 573 (-0.6%) 343 (-0.7%) 110 (-0.6%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Compute register sizes once for the sub-register size check
checkSubRegIndexSizes found the size of each register by scanning every
register class for one containing it, about 18 million class membership
tests for AMDGPU. Compute the size of all registers in one pass over
the members of each register class instead, and pass it in.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 578 355 113
After 576 (-0.2%) 345 (-2.8%) 110 (-2.4%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Test register sub-classes with the member bit vectors
computeSubClasses tests most pairs of register classes for inclusion,
and compared the sorted member lists, which loads every register on
the way. Each class already has a bit vector of its members, so use
that instead, after checking the sizes.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 596 365 117
After 577 (-3.1%) 353 (-3.4%) 112 (-3.7%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Skip redundant addComposite calls for secondary sub-registers
computeSecondarySubRegs adds the compositions of each new secondary
sub-register's index with every index of the sub-register. These were
almost always already added for another register with the same
structure: of 29.8 million calls for AMDGPU, 15000 added anything. If
the composition is known and its result has an offset in every mode,
addComposite has no effect, so skip the call.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 603 367 116
After 595 (-1.3%) 362 (-1.2%) 115 (-1.0%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Index registers by sub-register index enum value when inferring sub-classes
inferSubClassWithSubReg groups the members of a register class by each
of their sub-register indices, and looked up every index of every member
in a std::map. Sub-register indices are numbered densely, so use a
vector indexed by enum value instead. Also count the members once
instead of once per index.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 622 380 120
After 604 (-3.0%) 367 (-3.4%) 115 (-3.7%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Store super-register class sets as bit vectors
extendSuperRegClasses merges the super-register class sets of each
register class into those of its sub-classes, and the sets were
DenseSets, so most of its time went to hashing classes that were
already present. Number register classes in creation order, and store
the sets as bit vectors indexed by that number, so merging is a bitwise
or. For AMDGPU's 913 classes the sets also take about 2 MB instead of
about 15 MB.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 700 435 135
After 622 (-11.1%) 381 (-12.5%) 120 (-11.2%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Avoid binary searches for sub-registers of similar registers
inferMatchingSuperRegClass looks up the sub-register at one index for
every member of a register class. Members of a class almost always have
the same sub-register indices, so the index is usually at the same
position in each member's sorted array. Pass the position found in the
previous member as a hint, and only binary search if it doesn't match.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 720 442 138
After 701 (-2.7%) 437 (-1.2%) 137 (-1.2%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Return conflicting compositions from addComposite immediately
Check for an existing composition up front: return a conflicting one
right away, instead of after updating B's ranges from a composition that
isn't recorded. This no longer needs the try_emplace result. The
generated code for all in-tree targets is unchanged, and the instruction
count is the same.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Look up sub-register index compositions in an array
compose() looked up each composition in a std::map. It is called for
every super-register class set in extendSuperRegClasses, and by
addComposite. Sub-register indices are numbered densely, so also keep
each index's compositions in an array indexed by enum value. For
AMDGPU's 400 indices this is about 1 MB.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 746 474 148
After 721 (-3.4%) 446 (-6.1%) 139 (-5.8%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Skip classes without matching super-register classes in RegisterBankEmitter
visitRegisterBankClasses checks every sub-register index for every pair
of register classes. Skip the per-index loop if RC is not in any of the
class's super-register class sets.
AMDGPU tablegen run for AMDGPUGenRegisterBank.inc:
Gigacycles CPU seconds
Before 51.7 16.0
After 48.4 (-6.4%) 14.9 (-6.9%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Insert super-register class sets in one step
extendSuperRegClasses added each super-register class to the composed
index's set with a separate addSuperRegClass call, which looks up the
set in the DenseMap every time. Look up the set once and insert the
whole range.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 797 489 153
After 755 (-5.2%) 477 (-2.4%) 149 (-2.5%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Return early from addComposite for known compositions
computeComposites calls addComposite for each pair of sub-registers of
every register with a distinct sub-register structure, so most calls
repeat a composition that is already known. Each call still did three
std::map lookups per hardware mode to update the sub-register ranges.
If the composition already exists and its result has an offset in every
mode, the rest of the function has no effect, so return early. Cache
whether the result has an offset in every mode, since offsets are never
cleared once set.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 916 540 169
After 797 (-13.0%) 489 (-9.5%) 153 (-9.4%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
update to wine 11.20. Tested by Andrii and me.
dlls/ntdll/unix/file.c has undergone a refactor upstream; we may need
to fix a few things upon further review, but things run well enough to
not delay this update.
Reminder for users to look at README. Expect to be called out for not
having read it when reporting about 32-bit software not running.
This is still early days for the port, so not all 64-bit software runs.
[SandboxVec][NFC] Move test and add RUN line (#234432)
Moves the unsupported_alignment.ll test from the BundleVec directory to
the Common directory and add a RUN line to exercise LoadStoreVec.
This is for a follow-up patch that implements the unsupported alignment
check in LoadStoreVec.
