[AMDGPU] Refactor GFX11 VALU Mask Hazard Waitcnt Merging (#169213)
Move GFX11 SGPR VALU mask hazard waitcnt merging to the a forward scan
within the AMDGPUWaitSGPRHazard pass.
This simplifies the hazard recognizer code and allows merging of waitcnt
instructions in cases where SGPRs unaffected by pending writes are used.
In turn this greatly decreasing numbers of waits inserted in sequences
of V_CMP instructions writing SGPRs improving VALU pipeline performance.
devel/cargo-edit: update to 0.13.13
v0.13.13 - 2026-07-15
Fixes
- (upgrade) Point single---verbose users to --verbose --verbose when more dependencies are hidden
v0.13.12 - 2026-07-14
Fixes
- (set-version) Error on -p invalid package names
[orc-rt] Add TaskGroup::TokenSource; drop raw group accessor (#210240)
Session::managedCodeTaskGroup() returned the raw
std::shared_ptr<TaskGroup> for the managed-code group, exposing the
group's full interface -- including close() and addOnComplete() -- to
callers, even though those operations are reserved for the Session.
Add TaskGroup::TokenSource, a strong handle whose sole role is to serve
as an argument to the TaskGroup::Token constructor. Session now exposes
managedCodeTokenSource() in its place, so clients can acquire tokens (to
keep managed code alive across shutdown) without gaining the ability to
close the group or register completion callbacks.
[SLP][modularisation][NFC] Extract mask, shuffle and AA helpers into SLUtils 3/3 (#209973)
Move the mask/shuffle construction and alias-analysis free helpers out
of SLPVectorizer.cpp into SLPVectorizer/SLPUtils.{h,cpp} (namespace
llvm::slpvectorizer).
Moved:
transformScalarShuffleIndiciesToVector
getShufflevectorNumGroups
calculateShufflevectorMask
UseMask (enum)
buildUseMask
isUndefVector
doesInTreeUserNeedToExtract
getLocation
isSimple
addMask
fixupOrderingIndices
getAltInstrMask
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firewire: remove SPL calls
SPL is a no-op on amd64. Real locking is already handled by fc_mtx and
per-driver mutexes.
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D58210
fwdv: match unit directories instead of IDENTIFY
Migrated fwdv to use per-unit-directory child device
Reviewed by: adrian
Differential Revision: https://reviews.freebsd.org/D58204
fwisound: match unit directories instead of IDENTIFY
Migrated fwisound to use per-unit-directory child device
Differential Revision: https://reviews.freebsd.org/D58203
Reviewed by: adrian
fwcam: match unit directories, defer probe to first open
Migrated fwcam to use per-unit-directory child device
Differential Revision: https://reviews.freebsd.org/D58202
Reviewed by: adrian
firewire: per-unit-directory child device support
Added structure to allow multiple device to attach to the same driver.
Also removed the deprecation warning from the man page.
Differential Revision: https://reviews.freebsd.org/D58201
Reviewed by: adrian
workflows: Fixes for release-binaries and upload-release-artifact (#209246)
There were some bugs in upload-release-artifact workflow and
release-binaries was not including this action in its checkout.
[flang][cuda] Managed backing for -gpu=unified allocatables/pointers (#210149)
Under `-gpu=unified`, allocatables and pointers with no explicit CUDA data
attribute must be reachable from the device. Back them with CUDA managed
memory by selecting the unified allocator index at the ALLOCATE site (in
lowering), instead of stamping an implicit `Unified`/`Managed` CUDA data attribute
on the symbol in the frontend — the approach introduced in PR #209292.
This is necessary because attributing the symbol in the frontend routed every
plain allocatable/pointer through the CUDA Fortran managed descriptor
pipeline (constructor registration, `cuf.allocate`/`cuf.free`), which added
per-`ALLOCATE` overhead, forced special-casing for objects that may not legally carry a
CUDA attribute (COMMON members, derived-type components, module globals), and
changed symbol semantics used well beyond allocation. Choosing the allocator
index at the `ALLOCATE` site keeps the object a plain host allocatable/pointer while
the storage still comes from the managed allocator.
[flang][OpenMP] Check DEFAULT(NONE) on metadirective loop variants
Standalone metadirectives and their associated loops are separate parse-tree
nodes. For example:
```fortran
!$omp metadirective &
!$omp& when(implementation={vendor(llvm)}: &
!$omp& parallel do default(none) shared(n, a)) default(nothing)
do i = 1, n
a(i) = x
end do
```
Unlike an ordinary PARALLEL DO, the loop is not nested under the directive:
```text
METADIRECTIVE
`-- WHEN
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[ObjectYAML][NFC] Hoist BBAddrMap yaml2obj encoder into a shared helper (#205991)
Preparatory NFC refactor to let the upcoming COFF emitter reuse the
BBAddrMap YAML encoder.
devel/py-expression: Add port: Practical functional programming for Python 3.10+
Expression aims to be a solid, type-safe, pragmatic, and high
performance library for frictionless and practical functional
programming in Python 3.10+.
WWW: https://github.com/dbrattli/Expression
[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic
The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.
Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:
- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
Operations use APInt arithmetic at WideBits, chosen to guarantee no
intermediate overflow:
$$
WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
$$
This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
extra bits.
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Remove fips-module related diff
This particular change didn't come from upstream. It was added locally
in 7a991ecd1 when attempting to enable the fips provider with 3.0.
Given the fact that we no longer build the fips provider and the fips
provider build process (including sources) is very prescribed to
specific build steps and source versions, there's no reason why we need
to continue carrying around this diff anymore.
MFC after: 1 week
Signed-off-by: Enji Cooper <ngie at FreeBSD.org>
(cherry picked from commit d6e3662bc1f5054d81b1ceab641396047c2cad94)
Remove `$FreeBSD$` from upstream-provided config file
This diff reduces with the content provided by upstream (OpenSSL).
MFC after: 1 week
(cherry picked from commit 2de6d07e16aa4d902b7b322a869f89a07348e851)
Remove `$FreeBSD$` from upstream-provided config file
This diff reduces with the content provided by upstream (OpenSSL).
MFC after: 1 week
(cherry picked from commit 2de6d07e16aa4d902b7b322a869f89a07348e851)
exterr_set: sync the definition with the header declaration
This unbreaks buildkernel with TARGET=armv7 (32-bit arm). More work may be required
in order to unbreak `exterr_set` with 32-bit kernels.
Fixes: 844009378da9 ("exterr: allow exterr to fit pointers on CHERI targets")
[LoongArch] Fix invalid VEXTH combines for unsupported type extensions (#209725)
`performEXTENDCombine` could form `VEXTH`/`VEXTH_U` nodes for
unsupported type combinations, such as extending `v8i8` to `v8i32` or
`v2i64` to `v2i128`. These illegal nodes would later reach instruction
selection and trigger backend failures:
* `Cannot select: LoongArchISD::VEXTH`
* `Don't know how to legalize this operation`
Prevent these combines from firing by verifying that the destination
type is legal and has exactly twice the total bit width of the source
before forming a `VEXTH`/`VEXTH_U` node.
Apply the same checks to `performSHLCombine` for consistency.
Fixes
https://github.com/llvm/llvm-project/pull/207316#issuecomment-4978234865
Fixes
https://github.com/llvm/llvm-project/pull/207316#issuecomment-4979233899
