LLVM/project 81a537elldb/include/lldb/Core PluginManager.h, lldb/source/Core PluginManager.cpp

[lldb] Use range-based for loops over plugins (#184837)

This PR replaces the Get*CallbackAtIndex pattern in the PluginManager
with returning a snapshot of callbacks that the caller can iterate over
using a range-based for loop. This is a continuation of #184452 which
added thread safety by using snapshots. However, that introduced a bunch
of unnecessary copies which are largely eliminated again by getting the
snapshot once when gather all the callbacks, rather than doing that on
each iteration when querying a plugin for a given index. It also
eliminates the possibility of the snapshot changing underneath you when
iterating over the plugins.

This change was largely mechanical and I used Claude to do the menial
work of updating the signatures and call sites.
DeltaFile
+125-163lldb/source/Core/PluginManager.cpp
+87-87lldb/unittests/Core/PluginManagerTest.cpp
+79-78lldb/include/lldb/Core/PluginManager.h
+16-38lldb/source/Symbol/ObjectFile.cpp
+8-27lldb/source/Target/LanguageRuntime.cpp
+6-22lldb/source/Target/Platform.cpp
+321-41520 files not shown
+368-55126 files

LLVM/project 9d11b09llvm/test/CodeGen/AArch64 clmul-fixed.ll, llvm/test/CodeGen/PowerPC clmul-vector.ll

reb

Created using spr 1.3.7
DeltaFile
+53,024-7,001llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+15,172-1,553llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+6,812-3,080llvm/test/CodeGen/AArch64/clmul-fixed.ll
+5,488-0llvm/test/CodeGen/X86/bit-manip-i512.ll
+2,338-2,209llvm/test/CodeGen/PowerPC/clmul-vector.ll
+1,561-2,812llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+84,395-16,6552,299 files not shown
+171,433-46,3802,305 files

LLVM/project d43b9bcllvm/test/CodeGen/AArch64 clmul-fixed.ll, llvm/test/CodeGen/PowerPC clmul-vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+53,024-7,001llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+15,172-1,553llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+6,812-3,080llvm/test/CodeGen/AArch64/clmul-fixed.ll
+5,488-0llvm/test/CodeGen/X86/bit-manip-i512.ll
+2,338-2,209llvm/test/CodeGen/PowerPC/clmul-vector.ll
+1,561-2,812llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+84,395-16,6552,299 files not shown
+171,433-46,3802,305 files

LLVM/project 610ed83llvm/lib/Transforms/Instrumentation HWAddressSanitizer.cpp, llvm/test/Instrumentation/HWAddressSanitizer use-after-scope.ll

[HWASan] add optimization remark for supported lifetimes

This lets us find functions where we pessimize codegen by removing
lifetimes.

Reviewers: vitalybuka

Reviewed By: vitalybuka

Pull Request: https://github.com/llvm/llvm-project/pull/183858
DeltaFile
+26-1llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
+18-5llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+44-62 files

LLVM/project 4e438f7llvm/lib/Support JSON.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+0-3llvm/lib/Support/JSON.cpp
+0-31 files

LLVM/project 01a9705libcxx/include __split_buffer, libcxx/include/__vector vector.h

Revert "[libcxx] adds `__split_buffer::__swap_layouts`" (#185120)

Reverts llvm/llvm-project#180102
DeltaFile
+16-3libcxx/include/__vector/vector.h
+0-17libcxx/include/__split_buffer
+16-202 files

LLVM/project cf21ea9llvm/lib/Target/ARM ARMBaseInstrInfo.cpp ARMISelLowering.cpp, llvm/lib/Target/ARM/AsmParser ARMAsmParser.cpp

[ARM] Fix more typos (NFC)

Fix more typos in the AArch64 codebase using the
https://github.com/crate-ci/typos Rust package.

commit-id:33a1bb8d

Reviewers: davemgreen

Reviewed By: davemgreen

Pull Request: https://github.com/llvm/llvm-project/pull/183087
DeltaFile
+9-9llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+9-9llvm/lib/Target/ARM/ARMISelLowering.cpp
+6-6llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+5-5llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+5-5llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+4-4llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+38-3823 files not shown
+68-6829 files

LLVM/project 43f7838llvm/lib/Target/AArch64 MachineSMEABIPass.cpp AArch64StackTagging.cpp, llvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp

[AArch64] Fix more typos (NFC)

Fix more typos in the AArch64 codebase using the
https://github.com/crate-ci/typos Rust package.

commit-id:9f4d826d

Reviewers: davemgreen

Pull Request: https://github.com/llvm/llvm-project/pull/183086
DeltaFile
+2-2llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+1-1llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+1-1llvm/lib/Target/AArch64/AArch64StackTagging.cpp
+1-1llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+7-75 files not shown
+12-1211 files

NetBSD/pkgsrc-wip 822325dpy-datasci packages.mk, py-mbake Makefile

*: fix py-typer paths after import
DeltaFile
+1-1py-datasci/packages.mk
+1-1py-mbake/Makefile
+2-22 files

NetBSD/pkgsrc aNWsspwdoc TODO

   doc/TODO: + rust-1.94.0.
VersionDeltaFile
1.26897+2-1doc/TODO
+2-11 files

LLVM/project cc4f4b1libcxx/include __split_buffer, libcxx/include/__vector vector.h

Revert "[libcxx] Add `__split_buffer::__swap_layouts` (#180102)"

This reverts commit 65f39a16abf651008185839459fb330258800a62.
DeltaFile
+16-3libcxx/include/__vector/vector.h
+0-17libcxx/include/__split_buffer
+16-202 files

LLVM/project 1cdcee2clang/lib/CodeGen CGExprScalar.cpp, clang/test/CodeGenHLSL/BasicFeatures MatrixExplicitTruncation.hlsl MatrixImplicitTruncation.hlsl

[HLSL][Matrix] Make matrix truncation respect default matrix memory layout (#184280)

Fixes #183127 and #184371

This PR makes the matrix truncation cast implementation use the new
matrix flattened index helper functions introduced by #182904 so that it
reads elements from the source matrix using the default matrix memory
layout instead of always assuming column-major order.

This PR also fixes a bug where matrix truncation truncated the wrong
elements.

Assisted-by: claude-opus-4.6
DeltaFile
+24-12clang/test/CodeGenHLSL/BasicFeatures/MatrixExplicitTruncation.hlsl
+22-11clang/test/CodeGenHLSL/BasicFeatures/MatrixImplicitTruncation.hlsl
+11-10clang/lib/CodeGen/CGExprScalar.cpp
+57-333 files

LLVM/project 6dea289clang/lib/CIR/CodeGen CIRGenItaniumCXXABI.cpp, clang/test/CIR/CodeGen try-catch-tmp.cpp

[CIR] Implement reference type in init catch param (#184442)

Implement init support for reference type in the init catch param
DeltaFile
+115-0clang/test/CIR/CodeGen/try-catch-tmp.cpp
+17-1clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
+132-12 files

FreeNAS/freenas c92faa5src/middlewared/middlewared event.py

NAS-140179 / 27.0.0-BETA.1 / Introduce typed event source (#18396)

## Context

Introduce `TypedEventSource` which to the `run` body gives access to the
pydantic model itself which should be used so we can statically type
check properly arguments.
DeltaFile
+21-0src/middlewared/middlewared/event.py
+21-01 files

Illumos/gate 196cb0eusr/src/cmd/svc/configd configd.c

17900 svc/configd: format issue while printing pid_t
Reviewed by: Gordon Ross <Gordon.W.Ross at gmail.com>
Approved by: Dan McDonald <danmcd at edgecast.io>
DeltaFile
+1-1usr/src/cmd/svc/configd/configd.c
+1-11 files

LLVM/project d259193clang/lib/CIR/CodeGen CIRGenExprScalar.cpp CIRGenExprComplex.cpp

[CIR] Fix operator-precedence bugs in assert conditions

Due to && binding tighter than ||, asserts of the form
assert(A || B && "msg") always pass when A is true. Add
parentheses so the string message is properly attached:
assert((A || B) && "msg").
DeltaFile
+8-7clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+4-5clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
+12-122 files

FreeNAS/freenas 9c501d3tests/api2 test_300_nfs.py

Add many small-ish tweaks to add resilience to idiosyncrasies in running the CI tests.
A good part of this is handling the 'websocket' disconnect.
DeltaFile
+166-35tests/api2/test_300_nfs.py
+166-351 files

LLVM/project d34f179llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.exp.ll llvm.amdgcn.exp.row.ll

AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_exp/exp_row (#181956)
DeltaFile
+57-10llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
+9-5llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
+11-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+10-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
+93-176 files

FreeBSD/ports 27001d6mail/thunderbird distinfo Makefile

mail/thunderbird: update to 148.0.1 (rc1)

Release Notes:
  https://www.thunderbird.net/en-US/thunderbird/148.0.1/releasenotes/

(cherry picked from commit d454980ee94c47d12a2195f2dab12ced70e11526)
DeltaFile
+3-3mail/thunderbird/distinfo
+1-1mail/thunderbird/Makefile
+4-42 files

FreeBSD/ports d454980mail/thunderbird distinfo Makefile

mail/thunderbird: update to 148.0.1 (rc1)

Release Notes:
  https://www.thunderbird.net/en-US/thunderbird/148.0.1/releasenotes/
DeltaFile
+3-3mail/thunderbird/distinfo
+1-1mail/thunderbird/Makefile
+4-42 files

LLVM/project dc8de10llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

[AMDGPU][SIInsertWaitcnts][NFC] Simplify logic in GFX12Plus::applyPreexistingWaitcnts (#184925)

The loop is collecting the first instruction of each waitcnt kind and is
erasing the rest, with the exception of DEPCTR which needs more checks.
The existing code was factoring out the instruction deletion and the
setting of the collected instruction variables. But the special handling
for DEPCTR and the in-loop deletion of `S_WAITCNT_lds_direct` was just
complicating the logic.
DeltaFile
+40-29llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+40-291 files

LLVM/project 89d6936llvm/test/CodeGen/AArch64 fp-maximumnum-minimumnum.ll arm64-build-vector.ll

[AArch64][GlobalISel] Add more gisel test coverage. NFC
DeltaFile
+2,071-1,930llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
+125-56llvm/test/CodeGen/AArch64/arm64-build-vector.ll
+122-57llvm/test/CodeGen/AArch64/fdiv-const.ll
+76-39llvm/test/CodeGen/AArch64/isinf.ll
+78-18llvm/test/CodeGen/AArch64/f16-imm.ll
+59-27llvm/test/CodeGen/AArch64/half-precision-signof-no-assert.ll
+2,531-2,1273 files not shown
+2,616-2,1609 files

LLVM/project 65f39a1libcxx/include __split_buffer, libcxx/include/__vector vector.h

[libcxx] Add `__split_buffer::__swap_layouts` (#180102)

This commit simplifies the cumbersome process of swapping the respective
layout members for `__split_buffer` and `vector`.
DeltaFile
+3-16libcxx/include/__vector/vector.h
+17-0libcxx/include/__split_buffer
+20-162 files

LLVM/project ab5844dllvm/lib/Target/AMDGPU SILoadStoreOptimizer.cpp, llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll promote-constOffset-to-imm-gfx12.mir

[AMDGPU] Disable negative imm offset for async load/store instructions (#185078)

They are not allowed by the HW.
DeltaFile
+99-171llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+64-21llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
+75-10llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+34-40llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
+6-6llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
+278-2485 files

LLVM/project 6bd99efflang/include/flang/Optimizer/Dialect/CUF CUFOps.td, flang/lib/Lower Bridge.cpp

[flang][cuda] Add hasManagedOrUnifedSymbols attribute to cuf.data_transfer op (#185106)

Add an attribute to signal the presence of managed or unified symbols in
the data transfer. In some case, the presence of such symbols require to
insert synchronization. Adding the attribute in the op during lowering
facilitate the recognition of such data transfer.
DeltaFile
+16-6flang/lib/Lower/Bridge.cpp
+11-1flang/test/Lower/CUDA/cuda-data-transfer.cuf
+4-3flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
+31-103 files

LLVM/project e820236clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.h

[CIR] Fix convertSideEffectForCall header/definition signature mismatch

Add missing bool &noReturn parameter to the declaration in
LowerToLLVM.h to match the definition in LowerToLLVM.cpp.
DeltaFile
+1-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
+1-11 files

FreeNAS/freenas 763ecc0src/middlewared/middlewared/service crud_service_part.py

NAS-140178 / 27.0.0-BETA.1 / Fix CRUD service part query overload (#18395)

## Context

We need to fix CRUD Service part query overloads similar to
https://github.com/truenas/middleware/pull/18394.
DeltaFile
+3-3src/middlewared/middlewared/service/crud_service_part.py
+3-31 files

FreeBSD/ports a0a0115sysutils/storcli Makefile distinfo

sysutils/storcli: Update 7.3503 => 7.3603

PR:     293539
DeltaFile
+5-5sysutils/storcli/Makefile
+3-3sysutils/storcli/distinfo
+8-82 files

LLVM/project 8793c32clang/test/CIR/CodeGenOpenACC private-clause-pointer-array-recipes-CtorDtor.cpp combined-reduction-clause-default-ops.cpp, clang/test/CIR/IR cmp.cir

[CIR] Change CmpOp assembly format to use bare keyword style

Update the assembly format of cir.cmp from the parenthesized style
  cir.cmp(gt, %a, %b) : !s32i, !cir.bool
to the bare keyword style used by other CIR ops like cir.cast:
  cir.cmp gt %a, %b : !s32i

The result type (!cir.bool) is now automatically inferred as it is
always cir::BoolType.
DeltaFile
+64-64clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-CtorDtor.cpp
+60-60clang/test/CIR/IR/cmp.cir
+57-57clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
+352-35281 files not shown
+1,316-1,29387 files

LLVM/project adde5faclang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Fix GlobalOp::getSuccessorRegions using wrong region for dtor
DeltaFile
+1-1clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+1-11 files