FreeNAS/freenas e12a45fsrc/middlewared/middlewared/plugins/webshare config.py

Address review
DeltaFile
+5-0src/middlewared/middlewared/plugins/webshare/config.py
+5-01 files

LLVM/project 329cd89llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/test/CodeGen/X86 selectiondag-dbgvalue-null-crash.ll

[SelectionDAG] Fix null pointer dereference in resolveDanglingDebugInfo (#180425)

Fix crash when Val.getNode() is null by moving ValSDNodeOrder
declaration inside the null check.

The crash occurred when compiling code with debug info containing
aggregate types with nested empty structs.
DeltaFile
+37-0llvm/test/CodeGen/X86/selectiondag-dbgvalue-null-crash.ll
+1-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+38-12 files

LLVM/project 1a802d5llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 ptrauth-isel.ll ptrauth-intrinsic-auth-resign-with-blend.ll

[AArch64][PAC] Mark $Scratch operand of AUTxMxN as earlyclobber (#173999)

This fixes an assertions when emitting code at `-O0`.

(cherry picked from commit a47f3802bfd7f8f4c56cb11bad89d844398e6662)
DeltaFile
+57-4llvm/test/CodeGen/AArch64/ptrauth-isel.ll
+27-0llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-with-blend.ll
+12-1llvm/lib/Target/AArch64/AArch64InstrInfo.td
+96-53 files

LLVM/project 9340294llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

review
DeltaFile
+4-3llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+4-31 files

LLVM/project 359bb10clang/include/clang/Driver RocmInstallationDetector.h, clang/lib/Driver/ToolChains AMDGPU.cpp

clang/AMDGPU: Stop checking for finite only and unsafe math control libraries

These will be imminently deleted. Just ignore them if they are not present.
DeltaFile
+3-4clang/include/clang/Driver/RocmInstallationDetector.h
+4-2clang/lib/Driver/ToolChains/AMDGPU.cpp
+6-0clang/test/Driver/rocm-device-libs.cl
+0-0clang/test/Driver/Inputs/rocm-no-math-opt-libs/amdgcn/bitcode/oclc_wavefrontsize64_on.bc
+0-0clang/test/Driver/Inputs/rocm-no-math-opt-libs/amdgcn/bitcode/ocml.bc
+0-0clang/test/Driver/Inputs/rocm-no-math-opt-libs/amdgcn/bitcode/opencl.bc
+13-66 files not shown
+13-612 files

LLVM/project dc4fe14llvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/Transforms/InstCombine freeze.ll select.ll

Revert "[InstCombine] Allow freezing multiple operands (#154336)" (#182769)

This reverts commit f8f6965ceece9e330ddb66db5f402ecfb5e3ad34.

This is causing infinite loops interacting with other transforms. See
discussion on #182647 .

(cherry picked from commit bd3b163dce306040e2fa8d3bf5eef2385fc0bb37)
DeltaFile
+46-51llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+27-27llvm/test/Transforms/PGOProfile/chr.ll
+16-18llvm/test/Transforms/InstCombine/freeze.ll
+14-10llvm/test/Transforms/InstCombine/select.ll
+7-8llvm/test/Transforms/LoopVectorize/forked-pointers.ll
+6-6llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
+116-1207 files not shown
+139-15013 files

FreeBSD/doc e34c7c9documentation/content/en/articles/pgpkeys _index.adoc, documentation/static/pgpkeys nxjoseph.key

Add records about new ports committer (nxjoseph)

New author entry for Yusuf Yaman together with the news item and PGP
key added. List of Developers and Contributors updated as well to follow
steps 1-4 of the Committers Guide.

Reviewed by:    osa, vvd (mentors)
Approved by:    osa, vvd (mentors)
Differential Revision: https://reviews.freebsd.org/D55435
DeltaFile
+54-0documentation/static/pgpkeys/nxjoseph.key
+4-0website/data/en/news/news.toml
+4-0shared/authors.adoc
+3-0documentation/content/en/articles/pgpkeys/_index.adoc
+1-0shared/contrib-committers.adoc
+66-05 files

FreeNAS/freenas 348b75asrc/middlewared/middlewared/api/v26_0_0 webshare.py, src/middlewared/middlewared/etc_files/webshare-auth config.json.py

Webshare Groups configuration
DeltaFile
+14-0src/middlewared/middlewared/plugins/webshare/config.py
+1-1src/middlewared/middlewared/etc_files/webshare-auth/config.json.py
+2-0src/middlewared/middlewared/api/v26_0_0/webshare.py
+17-13 files

LLVM/project b615b80llvm/test/CodeGen/AMDGPU cc-inreg-sgpr0-3-mismatch.ll

[NFC][AMDGPU] Add test showing caller/callee SGPR mismatch for inreg args

Add a test demonstrating a bug where the caller and callee disagree on which
SGPRs hold user inreg arguments when there are enough to reach the SGPR0-3
range.

On the callee side, `LowerFormalArguments` marks SGPR0-3 as allocated in
`CCState` before the CC analysis runs. On the caller side, `LowerCall` adds the
scratch resource to `RegsToPass` without marking SGPR0-3 in `CCState`. This
causes `CC_AMDGPU_Func` to assign user inreg args to SGPR0-3 on the caller side
(they appear free) while the callee skips them.

In the test, the caller writes arg 0 (value 42) to s0, but the callee reads arg
0 from s16.
DeltaFile
+105-0llvm/test/CodeGen/AMDGPU/cc-inreg-sgpr0-3-mismatch.ll
+105-01 files

LLVM/project 426573fclang/include/clang/Driver RocmInstallationDetector.h, clang/lib/Driver/ToolChains AMDGPU.cpp

clang/AMDGPU: Stop looking for oclc_correctly_rounded_sqrt control libraries (#182858)

These have not done anything in almost a year.
DeltaFile
+0-11clang/lib/Driver/ToolChains/AMDGPU.cpp
+1-7clang/include/clang/Driver/RocmInstallationDetector.h
+0-5clang/test/Driver/hip-device-libs.hip
+0-5clang/test/Driver/rocm-device-libs.cl
+2-2clang/test/Driver/amdgpu-openmp-toolchain.c
+0-0clang/test/Driver/Inputs/rocm-invalid/amdgcn/bitcode/oclc_correctly_rounded_sqrt_off.bc
+3-3010 files not shown
+3-3016 files

LLVM/project 16460f5llvm/lib/Target/X86 X86AsmPrinter.h X86AsmPrinter.cpp, llvm/test/CodeGen/X86 basic-block-sections-mir-parse.mir

fix

Created using spr 1.3.7
DeltaFile
+0-7llvm/lib/Target/X86/X86AsmPrinter.h
+0-3llvm/lib/Target/X86/X86AsmPrinter.cpp
+1-0llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir
+1-103 files

LLVM/project a51098ellvm/test/CodeGen/AMDGPU cc-inreg-sgpr0-3-mismatch.ll

[NFC][AMDGPU] Add test showing caller/callee SGPR mismatch for inreg args

Add a test demonstrating a bug where the caller and callee disagree on which
SGPRs hold user inreg arguments when there are enough to reach the SGPR0-3
range.

On the callee side, `LowerFormalArguments` marks SGPR0-3 as allocated in
`CCState` before the CC analysis runs. On the caller side, `LowerCall` adds the
scratch resource to `RegsToPass` without marking SGPR0-3 in `CCState`. This
causes `CC_AMDGPU_Func` to assign user inreg args to SGPR0-3 on the caller side
(they appear free) while the callee skips them.

In the test, the caller writes arg 0 (value 42) to s0, but the callee reads arg
0 from s16.
DeltaFile
+105-0llvm/test/CodeGen/AMDGPU/cc-inreg-sgpr0-3-mismatch.ll
+105-01 files

FreeNAS/freenas 110ce1bdebian/debian control

NAS-139944 / 26.0.0-BETA.1 / Add truenas-file-manager dependency (#18276)

Add truenas-file-manager dep to match how we did with truesearch
DeltaFile
+1-0debian/debian/control
+1-01 files

LLVM/project f7ae5e6clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen/AArch64 pcdphint-atomic-store.c

fixup! Ensure stshh always immediately precedes a store instruction
DeltaFile
+82-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+50-13clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+62-0llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+20-26clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+15-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+8-3llvm/lib/Target/AArch64/AArch64InstrFormats.td
+237-423 files not shown
+248-499 files

LLVM/project 4f30127llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-select.ll eliminate-frame-index-select.mir

[AMDGPU] fix eliminateFrameIndex to use SGPR frame index (#178991)

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
DeltaFile
+138-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
+110-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
+0-2llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+248-23 files

LLVM/project 2778537clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup! Fix Kerry's CR comments and add negative test for "must be an integer type"
DeltaFile
+16-6llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+3-7clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+3-3clang/lib/Sema/SemaARM.cpp
+5-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+3-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-1clang/lib/Headers/arm_acle.h
+31-176 files

LLVM/project ec47932clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup! Improve error diagnostics, and other cleanups
DeltaFile
+12-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4-2clang/lib/Sema/SemaARM.cpp
+2-1clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1-1clang/test/Sema/AArch64/pcdphint-atomic-store.c
+1-1clang/include/clang/Basic/DiagnosticSemaKinds.td
+2-0clang/lib/Headers/arm_acle.h
+22-56 files

LLVM/project 7f0f426clang/include/clang/Basic BuiltinsAArch64.def, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup!

More small issues tidied, and remove gating.
DeltaFile
+6-2clang/test/Sema/AArch64/pcdphint-atomic-store.c
+2-2clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1-1clang/lib/Sema/SemaARM.cpp
+1-1clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+1-1clang/include/clang/Basic/BuiltinsAArch64.def
+0-2clang/lib/Headers/arm_acle.h
+11-96 files

LLVM/project 46ddaaaclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/Sema/AArch64 pcdphint-atomic-store.c

fixup!

A few small tidyups
DeltaFile
+7-6clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4-4llvm/lib/Target/AArch64/AArch64InstrFormats.td
+4-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+15-103 files

LLVM/project b026046clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin

Add `__arm_atomic_store_with_stshh` implementation as defined
in the ACLE. Validate that the arguments passed are correct, and
lower it to the stshh intrinsic plus an atomic store with the
allowed orderings.

Gate this on FEAT_PCDPHINT so that availability matches
hardware support for the `STSHH` instruction. Use an i64
immediate and side-effect modeling to satisfy tablegen and decoding.
DeltaFile
+140-0clang/lib/Sema/SemaARM.cpp
+48-0clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+31-0clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+29-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+13-0llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+10-2llvm/lib/Target/AArch64/AArch64InstrFormats.td
+271-25 files not shown
+298-211 files

LLVM/project d3b599ellvm/include/llvm/CodeGen AsmPrinter.h, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

fix

Created using spr 1.3.7
DeltaFile
+70-4llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+3-61llvm/include/llvm/CodeGen/AsmPrinter.h
+49-0llvm/lib/Target/X86/X86AsmPrinter.cpp
+3-40llvm/lib/Target/X86/X86AsmPrinter.h
+12-12llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+16-6llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+153-1234 files not shown
+168-13010 files

LLVM/project 808eadallvm/include/llvm/CodeGen AsmPrinter.h, llvm/include/llvm/Passes CodeGenPassBuilder.h

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+5-4llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+4-4llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+3-3llvm/include/llvm/Passes/CodeGenPassBuilder.h
+3-3llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
+1-0llvm/include/llvm/CodeGen/AsmPrinter.h
+16-145 files

LLVM/project 0e9880cllvm/lib/Transforms/Vectorize VPlanVerifier.cpp VPlanVerifier.h

[VPlan] Remove verifyLate from VPlanVerifier. NFC (#182799)

We can instead just check if the VPlan has been unrolled.
DeltaFile
+5-7llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
+2-5llvm/lib/Transforms/Vectorize/VPlanVerifier.h
+1-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+8-143 files

LLVM/project 4418e20clang/include/clang/Driver RocmInstallationDetector.h, clang/lib/Driver/ToolChains AMDGPU.cpp

clang/AMDGPU: Stop checking for finite only and unsafe math control libraries

These will be imminently deleted. Just ignore them if they are not present.
DeltaFile
+3-4clang/include/clang/Driver/RocmInstallationDetector.h
+6-0clang/test/Driver/rocm-device-libs.cl
+4-2clang/lib/Driver/ToolChains/AMDGPU.cpp
+0-0clang/test/Driver/Inputs/rocm-no-math-opt-libs/amdgcn/bitcode/hip.bc
+0-0clang/test/Driver/Inputs/rocm-no-math-opt-libs/amdgcn/bitcode/asanrtl.bc
+0-0clang/test/Driver/Inputs/rocm-no-math-opt-libs/amdgcn/bitcode/ockl.bc
+13-66 files not shown
+13-612 files

FreeNAS/freenas 92b5827src/middlewared/middlewared/plugins/update_ trains.py

NAS-139938 / 25.10.2.1 / Fix ClientConnectorCertificateError object has no attribute _os_error (by themylogin) (#18275)

Automatic cherry-pick failed. Please resolve conflicts by running:

    git reset --hard HEAD~1
    git cherry-pick -x d9a40f93a083c538cdc1dac8f26437fec6a654ac

If the original PR was merged via a squash, you can just cherry-pick the
squashed commit:

    git reset --hard HEAD~1
    git cherry-pick -x 5966611429782bc7b9b295664a15441406c1147c



Original PR: https://github.com/truenas/middleware/pull/18274

Co-authored-by: themylogin <themylogin at gmail.com>
DeltaFile
+7-1src/middlewared/middlewared/plugins/update_/trains.py
+7-11 files

NetBSD/pkgsrc iFgAIEedoc CHANGES-2026

   Updated net/py-aiormq, devel/py-greenlet
VersionDeltaFile
1.1345+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc X2jmxRHdevel/py-greenlet distinfo PLIST

   py-greenlet: updated to 3.3.2

   3.3.2 (2026-02-20)

   - Fix a crash on Python 3.10 if there are active greenlets during
     interpreter shutdown.
VersionDeltaFile
1.36+4-4devel/py-greenlet/distinfo
1.10+4-1devel/py-greenlet/PLIST
1.38+2-2devel/py-greenlet/Makefile
+10-73 files

NetBSD/pkgsrc pfowN7wnet/py-aiormq distinfo Makefile

   py-aiormq: updated to 6.9.3

   6.9.3

   fix: case where not all futures were rejected
   Use UV and Ruff
VersionDeltaFile
1.12+4-4net/py-aiormq/distinfo
1.13+3-3net/py-aiormq/Makefile
1.5+1-2net/py-aiormq/PLIST
+8-93 files

LLVM/project 222e661clang/docs ReleaseNotes.rst, clang/lib/AST RecordLayoutBuilder.cpp

[clang][layout] Fix unsigned char overflow in ms_struct bitfield layout (#181433)

Fixes #161511

When using MS-struct layout rules (`#pragma ms_struct`), Clang produces
incorrect memory layouts when encountering large `_BitInt` bit-fields.
The reason was that `LastBitfieldStorageUnitSize` variable was declared
as `unsigned char`, which caused it to overflow when the values used
with `_BitInt` exceeded `255`, so I changed it from `unsigned char` to
`uint64_t`.

In the added test, we can clearly see that `f2` and `f3` are both packed
in the same 256-bit unit.
DeltaFile
+31-0clang/test/Layout/ms-x86-bitfields-overflow.c
+5-0clang/docs/ReleaseNotes.rst
+2-2clang/lib/AST/RecordLayoutBuilder.cpp
+38-23 files

LLVM/project 0593d0dllvm/test/CodeGen/AMDGPU cc-inreg-sgpr0-3-mismatch.ll

[NFC][AMDGPU] Add test showing caller/callee SGPR mismatch for inreg args

Add a test demonstrating a bug where the caller and callee disagree on which
SGPRs hold user inreg arguments when there are enough to reach the SGPR0-3
range.

On the callee side, `LowerFormalArguments` marks SGPR0-3 as allocated in
`CCState` before the CC analysis runs. On the caller side, `LowerCall` adds the
scratch resource to `RegsToPass` without marking SGPR0-3 in `CCState`. This
causes `CC_AMDGPU_Func` to assign user inreg args to SGPR0-3 on the caller side
(they appear free) while the callee skips them.

In the test, the caller writes arg 0 (value 42) to s0, but the callee reads arg
0 from s16.
DeltaFile
+105-0llvm/test/CodeGen/AMDGPU/cc-inreg-sgpr0-3-mismatch.ll
+105-01 files