LLVM/project 53b4c84llvm/test/CodeGen/X86 ucmp.ll pr45563-2.ll

[X86] Attempt to fold extract_vector_elt(logicop(x,y),i) -> extract_vector_elt(x,i) (#194581)

When extracting from logicops, we often don't need to extract the result
if one of the element sources is identity (and(x,-1) -> x, or/xor(x,0)
-> x etc.), so this patch uses SimplifyMultipleUseDemandedVectorElts to
peek through to an underlying build_vector.

I had hoped to make this generic, but there's still a lot of yak shaving
to deal with first, as usual - I've included the minimal x86-specific
fixes:
 * missing constant folding of (vXi1 logicop(bitcast(c1),bitcast(c2)))
 * fold kshiftr(concat_vectors(x,y,z,w),c) -> concat_vectors(z,w,0,0)

Fixes #193700
DeltaFile
+861-864llvm/test/CodeGen/X86/ucmp.ll
+107-109llvm/test/CodeGen/X86/pr45563-2.ll
+68-138llvm/test/CodeGen/X86/masked_store.ll
+97-101llvm/test/CodeGen/X86/pr45833.ll
+22-92llvm/test/CodeGen/X86/pr193700.ll
+21-22llvm/test/CodeGen/X86/pr173924.ll
+1,176-1,3263 files not shown
+1,211-1,3319 files

FreeNAS/freenas 79fb854

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 50d5333src/middlewared/middlewared/plugins/vm utils.py clone.py

NAS-140814 / 27.0.0-BETA.1 / Copy VM NVRAM and TPM state on clone (#18828)

## Context

In continuation of the changes made in
https://github.com/truenas/middleware/pull/18764, the same fixes have
been applied to the VM cloning process ensuring that when a VM is cloned
- relevant files are copied over of the VM as well so tpm/secure boot
function as intended.
DeltaFile
+104-0src/middlewared/middlewared/plugins/vm/utils.py
+39-0src/middlewared/middlewared/plugins/vm/clone.py
+143-02 files

LLVM/project 402d309flang/include/flang/Parser tools.h, flang/lib/Lower PFTBuilder.cpp OpenACC.cpp

[flang][pft] visit original symbol in acc use_device  (#194588)

Fix regression after https://github.com/llvm/llvm-project/pull/193689
when a use_device is referring to variables from a host module.

The original symbol needs to be visited in the PFT so that it will be
instantiated, but it is not visible anymore from the parse tree, and not
directly connected to the new symbol (this is because variables in
use_device are treated in a special way in order to give them the DEVICE
attribute, other data clause do not need such handling).

Look into the parent scope for a symbol with the same name and visit it.
DeltaFile
+75-0flang/test/Lower/host_module_variable_instantiation_use_device.f90
+19-0flang/lib/Lower/PFTBuilder.cpp
+2-13flang/lib/Lower/OpenACC.cpp
+5-0flang/lib/Parser/tools.cpp
+1-0flang/include/flang/Parser/tools.h
+102-135 files

LLVM/project df0bec5clang/include/clang/Basic BuiltinsAMDGPU.td, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics

Assisted by - Claude-sonnet:4.6
DeltaFile
+189-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+18-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+9-0clang/include/clang/Basic/BuiltinsAMDGPU.td
+216-03 files

LLVM/project 9465d29llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.or.ll

[AMDGPU] Support Wave Reduction for true-16 types - 3

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+292-145llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+251-124llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+251-124llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+20-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-1llvm/lib/Target/AMDGPU/SIInstructions.td
+818-3975 files

LLVM/project 4be91fdllvm/test/CodeGen/LoongArch expandmemcmp.ll expandmemcmp-optsize.ll

update tests
DeltaFile
+670-297llvm/test/CodeGen/LoongArch/expandmemcmp.ll
+612-155llvm/test/CodeGen/LoongArch/expandmemcmp-optsize.ll
+1,282-4522 files

LLVM/project 2c0b673llvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchTargetTransformInfo.cpp

[LoongArch] Support memcmp expansion for vectors and combine for i128/i256 setcc

This commit enables memcmp expansion for lsx/lasx. After doing
this, i128 and i256 loads which are illegal types on LoongArch
will be generated. Without process, they will be splited to
legal scalar type.

So this commit also enable combination for `setcc` to bitcast
i128/i256 types to vector types before type legalization and
generate vector instructions.

Inspired by x86 and riscv.
DeltaFile
+114-8llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+8-3llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
+122-112 files

LLVM/project a70898bllvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis Banerjee.ll gcd-miv-overflow.ll

[DA] Disable the BanerjeeMIV dependence test (#174733)

The various `findBounds` helpers (e.g. `findBoundsLT`) are suspected to
be incorrect because they do not account for potential integer overflow,
which can lead the dependence analysis to produce incorrect results.
Since these helpers are used by the BanerjeeMIV dependence test, this
patch disables BanerjeeMIV by default to avoid unsafe results and
progress the default enablement of DA. The Banerjee test is required for
our motivating example, and we will working on correctness issues and
reenabling it after default enablement.

This is working around issue: #169813
DeltaFile
+11-2llvm/lib/Analysis/DependenceAnalysis.cpp
+3-3llvm/test/Analysis/DependenceAnalysis/Banerjee.ll
+1-1llvm/test/Transforms/LoopInterchange/legality-check.ll
+1-1llvm/test/Transforms/LoopInterchange/interchange-insts-between-indvar.ll
+1-1llvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
+1-1llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
+18-94 files not shown
+22-1310 files

LLVM/project 317a942llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

[AMDGPU] Support Wave Reduction for i16 types - 3

Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+587-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+487-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+487-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+24-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-0llvm/lib/Target/AMDGPU/SIInstructions.td
+1,588-4345 files

LLVM/project bcb38c1llvm/test/CodeGen/LoongArch expandmemcmp.ll expandmemcmp-optsize.ll

[LoongArch][NFC] Add lsx/lasx checks for memcmp expansion tests

Add checks for lsx/lasx and check-prefixes to reduce the duplication.
DeltaFile
+1,801-193llvm/test/CodeGen/LoongArch/expandmemcmp.ll
+1,023-197llvm/test/CodeGen/LoongArch/expandmemcmp-optsize.ll
+2,824-3902 files

FreeBSD/ports d2c3a65cad/freecad-devel Makefile.git_rev distinfo

cad/freecad-devel: Update to 2026.04.29
DeltaFile
+3-3cad/freecad-devel/Makefile.git_rev
+3-3cad/freecad-devel/distinfo
+3-0cad/freecad-devel/pkg-plist
+9-63 files

LLVM/project 5d172f7llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] Support Wave Reduction for true-16 types - 2

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+373-185llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+357-176llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+15-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-1llvm/lib/Target/AMDGPU/SIInstructions.td
+748-3644 files

LLVM/project dff6f0cllvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.min.ll llvm.amdgcn.reduce.max.ll

[AMDGPU] Support Wave Reduction for true-16 types - 1

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `min`, `umin`, `max`, `umax`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+255-124llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+255-123llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+255-123llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+272-101llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+44-6llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+17-8llvm/lib/Target/AMDGPU/SIInstructions.td
+1,098-4856 files

LLVM/project dddef41llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] Support Wave Reduction for i16 types - 2

Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+658-177llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+637-173llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+31-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+1,328-3554 files

LLVM/project 8508e57llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.max.ll llvm.amdgcn.reduce.min.ll

[AMDGPU] Support Wave Reduction for i16 types - 1

Supported Ops: `min`, `umin`, `max`, `umax`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.

Assisted by - Claude-sonnet:4.6
DeltaFile
+494-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+494-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+493-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+480-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+96-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2,062-5493 files not shown
+2,069-5499 files

OpenBSD/src quIaNYrsbin/pfctl parse.y

   The dual-pool form of the af-to action, af-to af FROM redirpool pool_opts
   TO redirpool pool_opts was writing the TO side options in the FROM side.

   OK sashan@
VersionDeltaFile
1.725+3-3sbin/pfctl/parse.y
+3-31 files

LLVM/project 852a449clang/include/clang/Basic BuiltinsAMDGPU.td, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics

Assisted by - Claude-sonnet:4.6
DeltaFile
+189-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+18-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+9-0clang/include/clang/Basic/BuiltinsAMDGPU.td
+216-03 files

LLVM/project 23d9582llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

[AMDGPU] Support Wave Reduction for true-16 types - 3

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+20-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+8-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+8-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+8-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+4-1llvm/lib/Target/AMDGPU/SIInstructions.td
+48-45 files

FreeBSD/ports ade8b6cmisc Makefile

misc/py-aider-chat: Remove Makefile entry

Fixes:     2cc531514db9
Reported by: antoine
DeltaFile
+0-1misc/Makefile
+0-11 files

LLVM/project 43f3352llvm/lib/CodeGen SpillPlacement.cpp

Revert "[CodeGen] Use SmallMapVector for SpillPlacement::Node::Links" (#194801)

Reverts llvm/llvm-project#194653

This caused a compile-time regression, rather than the expected
improvement.
DeltaFile
+20-14llvm/lib/CodeGen/SpillPlacement.cpp
+20-141 files

LLVM/project 7ab6bc0llvm/lib/Bitcode/Writer BitcodeWriter.cpp, llvm/test/Bitcode thinlto-unicode-module-paths.test

[ThinLTO] Preserve Unicode characters in module paths when writing the combined-index (#194320)

`IndexBitcodeWriter::writeModStrings()` serializes module path strings
into a `SmallVector<unsigned>` before emitting `MST_CODE_ENTRY` records.
When a path contains UTF-8 bytes with the high bit set, appending from
`StringRef::begin()/end()` can be incorrect. Instead, append the module
path through `bytes_begin()/bytes_end()`, so the bitcode writer always
serializes unsigned bytes.

Fixes: https://github.com/llvm/llvm-project/issues/194318 (#194318)

Based on work by @kbelochapka and @romanova-ekaterina.
DeltaFile
+18-0llvm/test/Bitcode/thinlto-unicode-module-paths.test
+2-1llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+20-12 files

FreeBSD/ports 8b9c184graphics/drm-61-kmod distinfo Makefile.version, graphics/nvidia-drm-61-kmod distinfo

graphics/drm-61-kmod: Update to latest version

This fixes compilation with clang21 (defualt on FreeBSD 16)

Sponsored by:   Beckhoff Automation GmbH & Co. KG
DeltaFile
+3-3graphics/nvidia-drm-61-kmod/distinfo
+3-3graphics/drm-61-kmod/distinfo
+3-3graphics/nvidia-drm-61-kmod-580/distinfo
+3-3graphics/nvidia-drm-61-kmod-devel/distinfo
+1-1graphics/nvidia-drm-61-kmod-580/Makefile
+1-1graphics/drm-61-kmod/Makefile.version
+14-143 files not shown
+17-179 files

FreeBSD/ports d94082fgraphics/drm-66-kmod distinfo Makefile, graphics/nvidia-drm-66-kmod distinfo

graphics/drm-66-kmod: Update to latest version

This fixes compilation with clang21 (defualt on FreeBSD 16)

Sponsored by:   Beckhoff Automation GmbH & Co. KG
DeltaFile
+3-3graphics/drm-66-kmod/distinfo
+3-3graphics/nvidia-drm-66-kmod/distinfo
+3-3graphics/nvidia-drm-66-kmod-580/distinfo
+3-3graphics/nvidia-drm-66-kmod-devel/distinfo
+1-1graphics/drm-66-kmod/Makefile
+1-1graphics/nvidia-drm-66-kmod-devel/Makefile
+14-143 files not shown
+17-179 files

LLVM/project ae66bfcllvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.or.ll

[AMDGPU] Support Wave Reduction for i16 types - 3

Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+571-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+471-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+471-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+24-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-0llvm/lib/Target/AMDGPU/SIInstructions.td
+1,540-4345 files

LLVM/project a5ff9eallvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] Support Wave Reduction for true-16 types - 2

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+373-185llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+357-176llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+15-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-1llvm/lib/Target/AMDGPU/SIInstructions.td
+748-3644 files

LLVM/project 20b5555llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] Support Wave Reduction for i16 types - 2

Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+658-177llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+637-173llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+31-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+1,328-3554 files

LLVM/project 294cee0llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.min.ll llvm.amdgcn.reduce.umin.ll

[AMDGPU] Support Wave Reduction for true-16 types - 1

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `min`, `umin`, `max`, `umax`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+255-124llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+255-123llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+255-123llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+272-101llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+44-6llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+17-8llvm/lib/Target/AMDGPU/SIInstructions.td
+1,098-4856 files

LLVM/project 561a0c5flang/lib/Lower Bridge.cpp, flang/lib/Parser unparse.cpp

[flang] Follow up #192674 Add INLINEALWAYS Directive (#194313)

Following some post merge review comments, this updates the work done in
#192674 based on feedback. It fixes some formatting that was not
conforming, fixes Typo's and updates the new warning's for Semantics
checks.
DeltaFile
+4-4flang/lib/Semantics/resolve-names.cpp
+3-3flang/test/Semantics/inlinealways-directive01.f90
+3-3flang/lib/Parser/unparse.cpp
+2-2flang/test/Lower/inlinealways-directive.f90
+1-1flang/lib/Lower/Bridge.cpp
+13-135 files

FreeBSD/ports 0eb5320www/onlyoffice-documentserver Makefile distinfo, www/onlyoffice-documentserver/files patch-server_Metrics_patches_statsd patch-server_Metrics_package.json

www/onlyoffice-documentserver: Bugfix Node OOM error on aarch64

Also update cache fetch method, and yao-pkg/node versions

PR:             294620
DeltaFile
+64-0www/onlyoffice-documentserver/files/patch-server_Metrics_patches_statsd
+22-18www/onlyoffice-documentserver/Makefile
+10-0www/onlyoffice-documentserver/files/patch-server_Metrics_package.json
+5-5www/onlyoffice-documentserver/files/patch-build__tools_scripts_build__server.py
+5-5www/onlyoffice-documentserver/distinfo
+1-1www/onlyoffice-documentserver/files/npm
+107-296 files