LLVM/project 9f3d143llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

AMDGPU: Remove dead code configuring f16 is_fpclass (#177626)

isTypeLegal can never be true here. The register classes
are registered at the end of the target lowering constructor,
and in the subclasses.
DeltaFile
+0-5llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+0-51 files

LLVM/project 1986628llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU flat-scratch.ll target-cpu.ll

[AMDGPU] Remove `FeaturePromoteAlloca`
DeltaFile
+14-14llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+1-16llvm/test/CodeGen/AMDGPU/target-cpu.ll
+7-7llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
+6-6llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
+7-4llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+45-5723 files not shown
+95-12129 files

LLVM/project 09685b7llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fmax_legacy.ll fmin_legacy.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for fmin/fmax_legacy (#177520)

DeltaFile
+26-3llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
+26-3llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+56-63 files

LLVM/project 9109c60mlir/include/mlir/Dialect/XeGPU/uArch IntelGpuXe2.h uArchBase.h, mlir/lib/Dialect/XeGPU/Transforms XeGPUPropagateLayout.cpp

[MLIR][XeGPU] Add uArch limitation to scatter load store (#172845)

DeltaFile
+98-35mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+71-2mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
+32-4mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
+7-1mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h
+208-424 files

LLVM/project fef6a14llvm/lib/Target/AMDGPU AMDGPU.td

[NFCI][AMDGPU] Fix the predicate `HasDsSrc2Insts` (#177621)

I'm not sure why the predicate has a `!`, and more surprisingly,
removing it doesn't change anything.
DeltaFile
+1-5llvm/lib/Target/AMDGPU/AMDGPU.td
+1-51 files

FreeBSD/src 4990cf8. MAINTAINERS

MAINTAINERS: Remove some stale entries

Remove some stale entries, preen some others. Longer term, we need a
better format. Also, if there's mistakes, let us know: we want it to be
useful to people seeking review, not be perscriptive about who can do
what.

Reviewed by: srcmgr@
DeltaFile
+14-22MAINTAINERS
+14-221 files

LLVM/project 6cf189aclang/test/CodeGen builtin-rotate.c

[clang][test] Fix builtin-rotate.c failure on ARM32 (#177290)

Replace unsigned __int128 with unsigned _BitInt(128) since __int128 is
not supported on ARM 32-bit targets.

Fixes https://lab.llvm.org/buildbot/#/builders/79/builds/2754
DeltaFile
+14-4clang/test/CodeGen/builtin-rotate.c
+14-41 files

LLVM/project 4237e74llvm/include/llvm/Analysis TargetTransformInfo.h, llvm/lib/Analysis TargetTransformInfo.cpp

[VectorCombine] foldShuffleOfBinops - failure to track OperandValueInfo (#171934)

Resolves #170500.

Implemented mergeInfo static helper to return common
TTI::OperandValueInfo data .

Added common OperandValueInfo `Op0Info` && `Op1Info` to NewCost
calculation.
DeltaFile
+193-0llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
+15-0llvm/include/llvm/Analysis/TargetTransformInfo.h
+10-4llvm/lib/Analysis/TargetTransformInfo.cpp
+7-4llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+225-84 files

LLVM/project 4f09b7allvm/test/CodeGen/AMDGPU frem.ll fract-match.ll, llvm/test/CodeGen/AMDGPU/GlobalISel frem.ll

AMDGPU: Ignore type legality in isFAbsFree

This treats it as free on targets without legal f16. This
matches the existing logic in fneg, and they should be the same.
The test changes are mostly neutral with a few improvements.
DeltaFile
+130-148llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+93-93llvm/test/CodeGen/AMDGPU/frem.ll
+22-24llvm/test/CodeGen/AMDGPU/fract-match.ll
+11-21llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
+12-15llvm/test/CodeGen/AMDGPU/fp-classify.ll
+8-8llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
+276-3093 files not shown
+285-3189 files

FreeBSD/ports f30daffsysutils/siegfried distinfo Makefile

sysutils/siegfried: Update to 1.11.4

ChangeLog:      https://github.com/richardlehane/siegfried/blob/main/CHANGELOG.md
MFH:            2026Q1
DeltaFile
+5-5sysutils/siegfried/distinfo
+1-2sysutils/siegfried/Makefile
+6-72 files

LLVM/project c1de2a9llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp SIISelLowering.cpp

AMDGPU: Move f16 legality configuration to SITargetLowering

f16 is never legal for R600 so this should not be in the common
base class.
DeltaFile
+2-11llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+3-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5-112 files

OpenBSD/ports YYoWixznet/netatalk3 Makefile, net/netatalk3/pkg PLIST

   Don't build docs, it requires doxygen.
VersionDeltaFile
1.24+0-2,010net/netatalk3/pkg/PLIST
1.72+1-0net/netatalk3/Makefile
+1-2,0102 files

LLVM/project 5b4a5cfllvm/docs ReleaseNotes.md, llvm/docs/CommandGuide llvm-objdump.rst

[RISCV][llvm-objdump] Support --symbolize-operands (#166656)

This adds support for `--symbolize-operands`, so that local references
are turned back into labels by objdump, which makes it easier to tell
what is going on with a linked object.

When using `--symbolize-operands`, branch target addresses are not
printed, only the referenced symbol is printed, and the address is
elided:

```
# Without --symbolize-operands
       0: 04a05263      blez    a0, 0x44 <.text+0x44>
...
      40: fd1ff06f      j       0x10 <.text+0x10>
      44: 00000613      li      a2, 0x0

# With --symbolize-operands
       0: 04a05263      blez    a0,  <L3>

    [4 lines not shown]
DeltaFile
+55-0llvm/test/MC/RISCV/symbolize-operands.s
+5-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+2-1llvm/tools/llvm-objdump/llvm-objdump.cpp
+1-1llvm/docs/CommandGuide/llvm-objdump.rst
+2-0llvm/docs/ReleaseNotes.md
+65-25 files

NetBSD/pkgsrc-wip 2616e6crofi COMMIT_MSG options.mk

rofi: update to 2.0.0
DeltaFile
+31-0rofi/COMMIT_MSG
+17-0rofi/options.mk
+4-5rofi/Makefile
+3-3rofi/distinfo
+55-84 files

LLVM/project 12cea04lldb/packages/Python/lldbsuite/test lldbtest.py

[lldb] Improve filecheck() by replacing assertTrue with assertEqual (#177212)

DeltaFile
+2-2lldb/packages/Python/lldbsuite/test/lldbtest.py
+2-21 files

Illumos/gate 4db51dbusr/src/data/ucode/amd THIRDPARTYLICENSE B680-00, usr/src/pkg/manifests system-microcode-amd.p5m

17835 Update AMD microcode to 20251202
Reviewed by: Robert Mustacchi <rm+illumos at fingolfin.org>
Reviewed by: Toomas Soome <tsoome at me.com>
Approved by: Gordon Ross <gordon.w.ross at gmail.com>
DeltaFile
+16-2usr/src/pkg/manifests/system-microcode-amd.p5m
+1-1usr/src/data/ucode/amd/THIRDPARTYLICENSE
+0-0usr/src/data/ucode/amd/B680-00
+0-0usr/src/data/ucode/amd/B700-00
+0-0usr/src/data/ucode/amd/B021-00
+0-0usr/src/data/ucode/amd/equivalence-table
+17-36 files not shown
+17-312 files

LLVM/project 6c941d7llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

AMDGPU: Remove dead code configuring f16 is_fpclass

isTypeLegal can never be true here. The register classes
are registered at the end of the target lowering constructor,
and in the subclasses.
DeltaFile
+0-5llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+0-51 files

FreeBSD/src 3cdb6c9contrib/llvm-project/libcxx/include inttypes.h

libc++ inttypes.h: define __STDC_CONSTANT_MACROS and __STDC_LIMIT_MACROS

Before transitively including the base version of inttypes.h, define
__STDC_CONSTANT_MACROS and __STDC_LIMIT_MACROS, because the base
inttypes.h directly includes sys/stdint.h, instead of going through the
'regular' stdint.h.

The libc++ version of the latter does define those macros, to ensure
things like UINT64_C() and SIZE_MAX are defined even in C++98 or C++03.

MFC after:      3 days
DeltaFile
+9-2contrib/llvm-project/libcxx/include/inttypes.h
+9-21 files

FreeNAS/freenas 0e7f611src/middlewared/middlewared/common/attachment __init__.py, src/middlewared/middlewared/plugins filesystem.py

progress
DeltaFile
+63-51src/middlewared/middlewared/common/attachment/__init__.py
+84-21src/middlewared/middlewared/plugins/pool_/dataset_attachments.py
+28-14src/middlewared/middlewared/service/sharing_service.py
+8-1src/middlewared/middlewared/plugins/filesystem.py
+4-3src/middlewared/middlewared/plugins/pool_/info.py
+3-3src/middlewared/middlewared/plugins/pool_/dataset.py
+190-934 files not shown
+196-9510 files

LLVM/project 56e04bellvm/lib/Target/AMDGPU AMDGPU.td

[NFCI][AMDGPU] Fix the predicate `HasDsSrc2Insts`

I'm not sure why the predicate has a `!`, and more surprisingly, removing it doesn't change anything.
DeltaFile
+1-5llvm/lib/Target/AMDGPU/AMDGPU.td
+1-51 files

LLVM/project 67baa87offload/test/mapping declare_mapper_target_checks.cpp

Revert "[NFC][OpenMP] Mark new mapper test as XFAIL on intelgpu. (#177491)"

This reverts commit 7d5622f7917815d224b780309432ffe4729e4852.
DeltaFile
+0-2offload/test/mapping/declare_mapper_target_checks.cpp
+0-21 files

LLVM/project 5997b42llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU wait-xcnt-atomic-rmw-optimization.ll

[AMDGPU][GFX1250] Optimize s_wait_xcnt for back-to-back atomic RMWs

This patch optimizes the insertion of s_wait_xcnt instruction for
sequences of atomic read-modify-write (RMW) operations in the
SIInsertWaitcnts pass. The Memory Legalizer conservatively inserts a
soft xcnt instruction before each atomic RMW operation as part of PR
168852, which is correct given the nature of atomic operations.
However, for back-to-back atomic RMWs, only the first s_wait_xcnt is
necessary for better runtime performance. This patch tracks atomic
RMW blocks within each basic block and removes redundant soft xcnt
instructions, keeping only the first wait in each sequence. An atomic
RMW block continues through subsequent atomic RMWs and non-memory
instructions (e.g., ALU operations) but is broken by CU-scoped memory
operations, atomic stores, or basic block boundaries.
DeltaFile
+71-2llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+0-31llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
+71-332 files

LLVM/project 63e7070utils/bazel/llvm-project-overlay/clang BUILD.bazel

[bazel] Add filegroup for builtin_headers (#67757)

I'd like to package these files into a distribution tar as part of
https://github.com/dzbarsky/static-clang. I'm currently applying patches
to the llvm repo but figured this bit could be upstreamed.

(Also open to ideas what to do about the `config.bzl` change in
https://github.com/dzbarsky/static-clang/blob/master/llvm.patch - it's
needed to link with musl libc)
DeltaFile
+5-0utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+5-01 files

LLVM/project 296f5a7llvm/include/llvm/IR IntrinsicsSPIRV.td IntrinsicsDirectX.td, llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp SPIRVModuleAnalysis.cpp

[SPIR-V] Implement sample and sample_clamp intrinsics for HLSL resources (#177234)

This patch implements the `sample` and `sample_clamp` intrinsics for
HLSL
resources in the SPIR-V backend. It adds the necessary intrinsic
definitions
in `IntrinsicsDirectX.td` and `IntrinsicsSPIRV.td`, and implements the
instruction selection logic in `SPIRVInstructionSelector.cpp`.

Key changes:
- Added `int_dx_resource_sample` and `int_dx_resource_sample_clamp`
intrinsics.
- Added `int_spv_resource_sample` and `int_spv_resource_sample_clamp`
intrinsics.
- Implemented `selectSampleIntrinsic` to handle
`OpImageSampleImplicitLod` generation.
- Added `ResourceDimension` enum in `DXILABI.h` and `HLSLResource.h`.
- Added a new test case
`llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll` to verify the
implementation.
DeltaFile
+127-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+69-0llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll
+11-0llvm/include/llvm/IR/IntrinsicsSPIRV.td
+11-0llvm/include/llvm/IR/IntrinsicsDirectX.td
+3-0llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+221-05 files

LLVM/project 69eac70clang/lib/Driver/ToolChains Flang.cpp, flang/lib/Frontend CompilerInvocation.cpp

[flang] Support -f(no-)protect-parens (#170505)

Driver/compiler option plumbing to get -f(no-)protect-parens supported
on flang. (This option was already supported in clang, so extended the
option config to enable it in flang.)

In the compiler, support it in code gen options and in lowering options.
Hooked up lowering options with the code by @alexey-bataev that turns
off reassociation transformations.

Co-authored-by: Alexey Bataev <a.bataev at outlook.com>
DeltaFile
+45-0flang/test/Lower/HLFIR/protect-parens-arrays.f90
+38-4flang/lib/Lower/ConvertExprToHLFIR.cpp
+32-0flang/test/Lower/HLFIR/protect-parens.f90
+13-0flang/test/Driver/protect-parens.f90
+6-0clang/lib/Driver/ToolChains/Flang.cpp
+5-0flang/lib/Frontend/CompilerInvocation.cpp
+139-45 files not shown
+149-911 files

LLVM/project a521774llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeVectorOps.cpp, llvm/test/CodeGen/AMDGPU vector-reduce-umax.ll vector-reduce-or.ll

DAG: Use poison for unused shuffle operands in legalizer (#177578)

DeltaFile
+71-74llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+28-28llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
+16-16llvm/test/CodeGen/X86/x86-interleaved-access.ll
+4-4llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+4-3llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+2-2llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+125-1276 files

LLVM/project e044ad9lldb/source/Host/macosx/objcxx PosixSpawnResponsible.h

[lldb] Unconditionally setup posix spawn responsible flag (#177451)

# Problem

The TCC support in LLDB was added by
https://github.com/llvm/llvm-project/commit/041c7b84a4b925476d1e21ed302786033bb6035f.

However, on newer macOS machines, when launching and debugging an
Catalyst app on macOS (see
[Host.mm](https://github.com/llvm/llvm-project/blob/1286de408cc4a3ba1bd6cb6fed7d9517c0429462/lldb/source/Host/macosx/objcxx/Host.mm#L1208-L1219)),
the TCC doesn't work as expected. This is because, even though the
launch info doesn't specify `eLaunchFlagInheritTCCFromParent`, the app
is still launched to inherit TCC from its parent (the LLDB). This
prevents the user from granting privacy access to the Catalyst app,
which is usually reflected in macOS' "Privacy & Security" settings.

For example, in the following screenshot (see PR), even when the microphone
access has already been granted to WhatsApp, trying to use it will still
cause a prompt (as if it's not granted already).

    [13 lines not shown]
DeltaFile
+10-20lldb/source/Host/macosx/objcxx/PosixSpawnResponsible.h
+10-201 files

LLVM/project 82164b6llvm/test/CodeGen/AMDGPU wait-xcnt-atomic-rmw-optimization.ll

[AMDGPU] Precommit lit test for optimized xcnt insertion.
DeltaFile
+1,302-0llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
+1,302-01 files

LLVM/project 77ebdadclang-tools-extra/clang-tidy/modernize UseStringViewCheck.cpp UseStringViewCheck.h, clang-tools-extra/docs/clang-tidy/checks/modernize use-string-view.rst

[clang-tidy] Add a new check 'modernize-use-string-view' (#172170)

Looks for functions returning `std::[w|u8|u16|u32]string` and suggests
to change it to `std::[...]string_view` if possible and profitable.

 Example:
```cpp
 std::string foo(int i) { // <---- can be replaced to `std::string_view foo(...) {`
   switch(i) {
     case 1:
       return "case1";
     case 2:
       return "case2";
     default:
       return {};
   }
 }

```
DeltaFile
+485-0clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view.cpp
+151-0clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
+136-0clang-tools-extra/docs/clang-tidy/checks/modernize/use-string-view.rst
+49-0clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.h
+41-0clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view-cxx20.cpp
+40-0clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view-ignored.cpp
+902-05 files not shown
+935-011 files

FreeBSD/src 6abefcdsys/dev/ahci ahci.c, sys/dev/mvs mvs.c

Fix SATA NCQ error recovery after 25375b1415

Since that commit ahci(4), siis(4) and mvs(4) drivers ended up
using wrong command to fetch error information for NCQ commands.
Since ATA errors are not very informative to begin with, the only
noticeable effect is a lack of retries on those errors by CAM.

MFC after:      1 week
PR:             279978

(cherry picked from commit 87085c12ba8fa51f777bc636df67008b45e20d1c)
DeltaFile
+1-1sys/dev/siis/siis.c
+1-1sys/dev/mvs/mvs.c
+1-1sys/dev/ahci/ahci.c
+3-33 files