LLVM/project a42f703llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-ctlz-zero-poison-extract-vector-elt.ll combine-ctlz-zero-poison-build-vector.ll

[GlobalISel][AMDGPU] Expand `isKnownNeverZero` for vector instructions (#211149)

A followup PR about adding some vector instruction patterns to
`isKnownNeverZero`, which firstly added in
https://github.com/llvm/llvm-project/pull/198438

The following instructions are added:
* `G_BUILD_VECTOR`
* `G_EXTRACT_VECTOR_ELT`
* `G_SHUFFLE_VECTOR`
DeltaFile
+97-0llvm/test/CodeGen/AMDGPU/GlobalISel/known-never-zero-vector.mir
+48-1llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+33-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-shuffle-vector.ll
+31-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-build-vector.ll
+24-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-extract-vector-elt.ll
+6-6llvm/test/tools/UpdateTestChecks/update_givaluetracking_test_checks/Inputs/const.mir.expected
+239-71 files not shown
+243-97 files

FreeBSD/ports 903be4bmisc/shimmy Makefile Makefile.crates, misc/shimmy/files patch-Cargo.lock

misc/shimmy: Update to 2.5.0

Changelog: https://github.com/Michael-A-Kuykendall/shimmy/blob/v2.5.0/CHANGELOG.md

Reported by:    GitHub (watch releases)
DeltaFile
+0-77misc/shimmy/files/patch-Cargo.lock
+21-21misc/shimmy/distinfo
+9-9misc/shimmy/Makefile.crates
+1-1misc/shimmy/Makefile
+31-1084 files

LLVM/project b6eb594llvm/test/CodeGen/AMDGPU splitkit-getsubrangeformask-phi-extend.ll memintrinsic-unroll.ll

[AMDGPU] Reschedule loads in clauses to improve throughput (#102595)

After clauses are formed their internal loads can be reordered to
facilitate some additional opportunities for overlapping computation.
This late stage rescheduling causes no change in register pressure.
DeltaFile
+2,087-1,967llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+445-403llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+449-293llvm/test/CodeGen/AMDGPU/div_i128.ll
+261-241llvm/test/CodeGen/AMDGPU/bf16.ll
+232-198llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+210-210llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
+3,684-3,31268 files not shown
+6,129-4,99474 files

LLVM/project 0fd1b98.github/workflows release-documentation.yml

Fixes plus debug
DeltaFile
+2-1.github/workflows/release-documentation.yml
+2-11 files

FreeBSD/src 5aab616share/man/man4 pci.4, sys/dev/pci pci.c

pci: Ignore SR-IOV VFs when tuning MPS

The VF Device Control MPS and MRRS fields are reserved and preserved.
VF transactions use the PF MPS, so a hardwired VF value must not be
used to retune the shared PCIe hierarchy.

Document the previously undocumented tuning knob and clarify why a VF
may continue to display its reserved hardwired value.

This fixes an instant crash/reboot on my Zen3 system with 82599 VFs.

MFC after:      1 week
DeltaFile
+12-1share/man/man4/pci.4
+7-0sys/dev/pci/pci.c
+19-12 files

LLVM/project f2bfcf5llvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction extractelement.ll

[LoongArch] Use unsigned vector extract for zero extension (#214120)

Add patterns to select VPICKVE2GR_BU/HU and [X]VPICKVE2GR_WU for vector
extraction followed by zero extension, eliminating redundant masking
instructions.
DeltaFile
+16-38llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
+28-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+8-19llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
+13-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+65-574 files

FreeBSD/src 9d871fasys/dev/ixgbe ixgbe.h if_ixv.c

ixv: reconcile VLAN filters through the mailbox

VLAN registration callbacks only update the software shadow, leaving
the PF unaware until a later full initialization.  Initialization then
retries each failed request in a tight loop, while skipping replay
entirely when local hardware filtering is disabled.

Send additions and removals as soon as the desired state changes,
independent of the VF local-filter capability.  Replay the desired
memberships after reset and retry a bounded batch per timer tick.  Stop
after the first failure so a silent PF can consume only one mailbox
timeout per pass, while a responsive PF can drain several requests.
Treat the retry window as a no-progress deadline: advance it when
pending work succeeds so a large backlog can drain, but leave entries
dormant after a sustained failure.

A successful mailbox request wakes a dormant backlog.  Dispatch
timer-driven retries only while iflib marks the VF running, so a stale
timer tick cannot restore PF VLAN state after the stop path resets the

    [14 lines not shown]
DeltaFile
+210-54sys/dev/ixgbe/if_ixv.c
+4-0sys/dev/ixgbe/ixgbe.h
+214-542 files

Linux/linux f9a2394arch/arm64/mm mmu.c, mm page_table_check.c pagewalk.c

Merge tag 'mm-hotfixes-stable-2026-08-06-18-44' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm

Pull MM fixes from Andrew Morton:
 "17 hotfixes.  15 are cc:stable.  16 are for MM.

  There's a patch series from Lorenzo "mm: fix UAF caused by race
  between ptdump and vmap pgtable freeing" which addresses a quite old
  bug in the ptdump code.

  And another series also from Lorenzo which fixes a four year old bug
  in the huge_zero_folio handling.

  A series from SJ fixes a few possible divide-by-zero issues which
  Sashiko sniffed out. And a series which fixes handling of the
  commit_inputs parameters.

  The remainder are singletons, please see their changelogs for details"

* tag 'mm-hotfixes-stable-2026-08-06-18-44' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm:

    [17 lines not shown]
DeltaFile
+122-77mm/huge_memory.c
+4-39arch/arm64/mm/mmu.c
+31-9mm/vmalloc.c
+21-15mm/pagewalk.c
+16-4mm/page_table_check.c
+8-5mm/damon/lru_sort.c
+202-14913 files not shown
+249-16819 files

FreeBSD/ports c20913edevel/py-ty Makefile Makefile.crates

devel/py-ty: Update to 0.0.69

Changelog: https://github.com/astral-sh/ty/blob/0.0.69/CHANGELOG.md

Reported by:    portscout
DeltaFile
+27-27devel/py-ty/distinfo
+12-12devel/py-ty/Makefile.crates
+1-1devel/py-ty/Makefile
+40-403 files

Linux/linux 364465afs/smb/common/compress compress.h compress.c, fs/smb/server connection.c connection.h

Merge tag 'v7.2-rc6-smb3-server-fixes' of git://git.samba.org/ksmbd

Pull smb server fixes from Steve French:

 - Reject Pattern_V1 payloads when Pattern_V1 support was not
   negotiated

 - Validate compression transform flags and chained mode before
   allocating the decompression buffer

 - Enforce the pre-authentication PDU size limit before allocating
   the decompression buffer, preventing compressed requests from
   bypassing the limit

* tag 'v7.2-rc6-smb3-server-fixes' of git://git.samba.org/ksmbd:
  ksmbd: apply the pre-authentication PDU limit when decompressing
  ksmbd: validate compression Flags before kvmalloc
  smb: compress: reject Pattern_V1 when not negotiated
DeltaFile
+12-2fs/smb/server/compress.c
+8-3fs/smb/common/compress/compress.c
+9-0fs/smb/server/connection.h
+1-5fs/smb/server/connection.c
+2-1fs/smb/common/compress/compress.h
+32-115 files

LLVM/project 8d19df3llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/RISCV select-fp-zve32x.ll

[RISCV][CostModel] Fix invalid cost for vector select on targets without FP vector support (#183158)

Fixes #182047

**Issue:** Compiling floating-point vector selects (e.g., `<2 x float>`)
on RISC-V targets that only support integer vectors (like `zve32x`)
causes a compiler crash in the Loop Vectorizer (`emitInvalidCostRemarks`
unhandled `TypeSwitch`).

**Root Cause:** The Type Legalizer correctly scalarizes the unsupported
FP vector into `f32` operations. However,
`RISCVTTIImpl::getCmpSelInstrCost` attempted to cost
`Instruction::Select` natively without verifying floating-point vector
hardware support. It passed the scalarized type to
`getRISCVInstructionCost` to price a native vector merge instruction,
which returned `InstructionCost::getInvalid()`.

**Fix:** Added hardware support checks (`hasVInstructionsF16/32/64()`)
for floating-point types in the `Instruction::Select` block. If the

    [9 lines not shown]
DeltaFile
+57-0llvm/test/Analysis/CostModel/RISCV/select-fp-zve32x.ll
+1-1llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+58-12 files

OpenBSD/ports ctlYgZAgames Makefile

   Hook prismlauncher up to the build
VersionDeltaFile
1.516+1-0games/Makefile
+1-01 files

LLVM/project f0c8cb2clang/docs HardwareAssistedAddressSanitizerDesign.md Block-ABI-Apple.md, clang/docs/CIR CleanupAndEHDesign.md

[docs] Finish MyST migration for selected docs
DeltaFile
+112-249clang/docs/CommandGuide/clang.md
+104-121clang/docs/ControlFlowIntegrityDesign.md
+94-98clang/docs/AutomaticReferenceCounting.md
+38-39clang/docs/CIR/CleanupAndEHDesign.md
+23-24clang/docs/HardwareAssistedAddressSanitizerDesign.md
+23-24clang/docs/Block-ABI-Apple.md
+394-5559 files not shown
+436-60615 files

OpenBSD/ports 39NUZUigames/prismlauncher Makefile, games/prismlauncher/patches patch-launcher_minecraft_Library_h patch-launcher_CMakeLists_txt

   Initial revision
VersionDeltaFile
1.1+123-0games/prismlauncher/patches/patch-launcher_launch_steps_PatchLWJGL_cpp
1.1+68-0games/prismlauncher/patches/patch-launcher_HardwareInfo_cpp
1.1+52-0games/prismlauncher/patches/patch-launcher_ui_dialogs_ProgressDialog_cpp
1.1+49-0games/prismlauncher/patches/patch-launcher_CMakeLists_txt
1.1+47-0games/prismlauncher/Makefile
1.1+45-0games/prismlauncher/patches/patch-launcher_minecraft_Library_h
+384-028 files not shown
+600-034 files

LLVM/project b4c0131llvm/docs DirectXUsage.md RISCVUsage.md, llvm/docs/PDB index.md

[docs] Finish MyST migration for selected docs
DeltaFile
+391-337llvm/docs/LFI.md
+203-207llvm/docs/SymbolizerMarkupFormat.md
+192-202llvm/docs/RISCVUsage.md
+80-44llvm/docs/PDB/index.md
+20-25llvm/docs/DirectXUsage.md
+14-15llvm/docs/RISCV/RISCVVectorExtension.md
+900-8306 files not shown
+913-85912 files

FreeBSD/src a668903sys/powerpc/include vmparam.h

powerpc64: Bump KVA to 2TB

This reflects what amd64 has, and is needed for using GPUs with large
VRAM.
DeltaFile
+1-1sys/powerpc/include/vmparam.h
+1-11 files

FreeBSD/src 7bc0655tools/tools/crypto cryptocheck.c

tools/cryptocheck: Fix allow_soft sysctl name
DeltaFile
+2-2tools/tools/crypto/cryptocheck.c
+2-21 files

FreeBSD/src b83204esys/powerpc/booke pmap.c pmap_64.c

powerpc/pmap: Support booke64 kernel pmap growing

In preparation of increasing the KVA on powerpc64 to 2TB to mirror
amd64's, rework the 64-bit Book-E pmap to not allocate all page table
pages at boot time, since that would be a waste of a lot of memory.
Instead, allocate all page table pages for the higher levels, leaving
the leaves (page directories) for dynamic allocation.  This cuts the
boot-time page table size down from ~64MB to ~8MB with the current 32GB
KVA size, and bumping to 2TB KVA the boot-time page table is still ~8MB
instead of ballooning to ~4GB of mostly wasted space.
DeltaFile
+86-9sys/powerpc/booke/pmap_64.c
+15-3sys/powerpc/booke/pmap.c
+101-122 files

LLVM/project ceaff22clang/lib/CodeGen CGExprScalar.cpp, clang/test/CodeGen constrained-math-builtins.c fp-reassoc-pragma.cpp

[Clang][CodeGen] Respect FP pragma options for fneg and calls (#212141)

Apply expression-specific floating-point options when emitting fneg and
call instructions.

This prevents these instructions from retaining fast-math flags disabled
by local FP pragmas, such as #pragma clang fp reassociate(off).

Fixes #51905
DeltaFile
+22-22clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
+22-8clang/test/CodeGen/fp-reassoc-pragma.cpp
+8-8clang/test/CodeGen/constrained-math-builtins.c
+5-1clang/lib/CodeGen/CGExprScalar.cpp
+57-394 files

FreeBSD/ports 7717b87shells/iris Makefile distinfo

shells/iris: Update to 0.5.2

Changelog:
- https://github.com/versenilvis/IRIS/releases/tag/v0.5.0
- https://github.com/versenilvis/IRIS/releases/tag/v0.5.1
- https://github.com/versenilvis/IRIS/releases/tag/v0.5.2

Reported by:    GitHub (watch releases)
DeltaFile
+5-5shells/iris/distinfo
+1-1shells/iris/Makefile
+6-62 files

LLVM/project 5ab9b3ellvm/docs AMDGPUMemoryModel.md

[Docs][AMDGPU] fully specify volatile accesses in the memory model (#214168)

A non-atomic volatile access on AMDGPU includes store-available or
load-visible
semantics at the widest scope supported by its address space:

- system scope for global/generic,
- workgroup scope for local (LDS)

An atomic volatile access has the same availability and visibility as
its atomic
non-volatile variant.

Previous Reference: 2f499b9

This fully specifies the behavior that the LLVM memory model leaves
target-dependent, matching the implementation in SIMemoryLegalizer. 

Assisted-By: Claude Opus 4.8
DeltaFile
+25-0llvm/docs/AMDGPUMemoryModel.md
+25-01 files

NetBSD/src yIItmRwsys/dev/ic wdc.c

   Deal with the absolutely pathological handling of the IDENTIFY command
   on big-endian systems.

   In wdc_datain_pio(), in the ATA_DRIVE_NOSTREAM case, if the bus.h
   implementation does does not have __BUS_SPACE_HAS_STREAM_METHODS
   and the system is _BIG_ENDIAN, individually swap each 16-bit value
   rather than assuming the bus_space_read_*2() implementation will do
   it.

   This is necessary because IDENTIFY is treated differently than every
   other command; all callers assume it will be returned in host-order,
   when in reality it's an array of 256 16-bit little-endian integers (even
   the string fields).

   Ultimately, the correct fix is to stop special-casing IDENTIFY, but
   that is a much larger change due to the confusing array of flags that
   control I/O size and disposition, and requires much wider testing.
VersionDeltaFile
1.316+36-2sys/dev/ic/wdc.c
+36-21 files

LLVM/project 35b6c91llvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction extractelement.ll

[LoongArch] Use unsigned vector extract for zero extension

Add patterns to select VPICKVE2GR_BU/HU and [X]VPICKVE2GR_WU for vector
extraction followed by zero extension, eliminating redundant masking
instructions.
DeltaFile
+16-38llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
+28-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+8-19llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
+13-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+65-574 files

LLVM/project 22219cdllvm/docs Telemetry.md CMakePrimer.md, llvm/docs/RISCV RISCVVectorExtension.md

[docs] Convert selected rst docs with rst2myst
DeltaFile
+563-482llvm/docs/RISCVUsage.md
+282-270llvm/docs/SymbolizerMarkupFormat.md
+257-256llvm/docs/yaml2obj.md
+215-235llvm/docs/CMakePrimer.md
+200-229llvm/docs/RISCV/RISCVVectorExtension.md
+175-182llvm/docs/Telemetry.md
+1,692-1,65414 files not shown
+2,771-2,84420 files

LLVM/project 1a12786clang/docs ControlFlowIntegrityDesign.md Block-ABI-Apple.md, clang/docs/CIR ABILowering.md CleanupAndEHDesign.md

[docs] Convert selected rst docs with rst2myst
DeltaFile
+1,504-1,583clang/docs/AutomaticReferenceCounting.md
+1,110-1,139clang/docs/CIR/CleanupAndEHDesign.md
+640-663clang/docs/Block-ABI-Apple.md
+637-629clang/docs/CommandGuide/clang.md
+339-370clang/docs/CIR/ABILowering.md
+336-338clang/docs/ControlFlowIntegrityDesign.md
+4,566-4,72214 files not shown
+5,730-6,04020 files

LLVM/project 9a50892llvm/docs SymbolizerMarkupFormat.rst SymbolizerMarkupFormat.md

[docs] Rename selected LLVM docs to Markdown
DeltaFile
+0-721llvm/docs/RISCVUsage.rst
+721-0llvm/docs/RISCVUsage.md
+0-672llvm/docs/LFI.rst
+672-0llvm/docs/LFI.md
+0-439llvm/docs/SymbolizerMarkupFormat.rst
+439-0llvm/docs/SymbolizerMarkupFormat.md
+1,832-1,83234 files not shown
+5,153-5,15340 files

LLVM/project 07ae984clang/docs Block-ABI-Apple.rst Block-ABI-Apple.md, clang/docs/CIR CleanupAndEHDesign.rst CleanupAndEHDesign.md

[docs] Rename selected Clang docs to Markdown
DeltaFile
+0-2,674clang/docs/AutomaticReferenceCounting.rst
+2,674-0clang/docs/AutomaticReferenceCounting.md
+0-1,631clang/docs/CIR/CleanupAndEHDesign.rst
+1,631-0clang/docs/CIR/CleanupAndEHDesign.md
+0-944clang/docs/Block-ABI-Apple.rst
+944-0clang/docs/Block-ABI-Apple.md
+5,249-5,24935 files not shown
+10,297-10,29841 files

LLVM/project 1bfd939llvm/test/CodeGen/LoongArch/lasx/ir-instruction extractelement.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction extractelement.ll

[LoongArch][NFC] Add tests for vector extraction with zero extension (#214119)
DeltaFile
+107-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
+64-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
+171-02 files

LLVM/project 8307b46bolt/lib/RuntimeLibs RuntimeLibrary.cpp, bolt/test CMakeLists.txt lit.cfg.py

[BOLT] Support runtime libraries built as thin archives (#214292)

In some configurations, BOLT runtime libraries may be built as thin
archive. Use the more generic `Archive::create` to handle these.
DeltaFile
+22-0bolt/test/runtime/thin-archive.c
+4-3bolt/lib/RuntimeLibs/RuntimeLibrary.cpp
+3-0bolt/test/lit.cfg.py
+1-0bolt/test/CMakeLists.txt
+30-34 files

NetBSD/src CABQutysbin/disklabel main.c

   Add hb68k to the "native layout" table.
VersionDeltaFile
1.60+3-2sbin/disklabel/main.c
+3-21 files