LLVM/project 2489e03llvm/lib/CodeGen/SelectionDAG LegalizeIntegerTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/AArch64 pr161013.ll

[LegalizeIntegerTypes] Add `PromoteIntOp_ANY_EXTEND_VECTOR_INREG` (#178144)

Fixes #161013
DeltaFile
+1,124-0llvm/test/CodeGen/X86/pr161013.ll
+49-0llvm/test/CodeGen/AArch64/pr161013.ll
+13-0llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+1,187-04 files

LLVM/project 43ac23cclang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

[LifetimeSafety] Handle temporaries of non-trivial view types
DeltaFile
+22-0clang/test/Sema/warn-lifetime-safety.cpp
+10-7clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+1-0clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+33-73 files

LLVM/project e5902caclang/include/clang/Basic AttrDocs.td, clang/lib/Analysis/LifetimeSafety LifetimeAnnotations.cpp

Transparent functions for all gsl::Pointers
DeltaFile
+75-0clang/test/Sema/warn-lifetime-safety.cpp
+32-19clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
+40-0clang/include/clang/Basic/AttrDocs.td
+147-193 files

NetBSD/pkgsrc-wip 912df47open-src-cvc Makefile COMMIT_MSG, open-src-cvc/patches patch-v__asmlnk.c patch-config.h

open-src-cvs: Verilog simulator with SDF support, initial commit
DeltaFile
+31-0open-src-cvc/Makefile
+30-0open-src-cvc/COMMIT_MSG
+18-0open-src-cvc/patches/patch-v__asmlnk.c
+18-0open-src-cvc/patches/patch-config.h
+8-0open-src-cvc/DESCR
+7-0open-src-cvc/distinfo
+112-01 files not shown
+114-07 files

LLVM/project f9222cdclang/include/clang/AST TypeLoc.h, clang/lib/Sema HLSLBuiltinTypeDeclBuilder.cpp TreeTransform.h

Reapply "[HLSL] Improve HLSL resource method generation" (https://github.com/llvm/llvm-project/pull/178266) (#178427)

This reverts commit
https://github.com/llvm/llvm-project/commit/c960499255a04e402d118d86a00ebcf1a8942ac9,
and fixes the msan error.
DeltaFile
+72-74clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
+33-34clang/test/AST/HLSL/TypedBuffers-AST.hlsl
+37-17clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+23-13clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
+6-2clang/lib/Sema/TreeTransform.h
+2-1clang/include/clang/AST/TypeLoc.h
+173-1416 files

LLVM/project 3a60a1emlir/lib/Dialect/Arith/IR ArithOps.cpp, mlir/test/Dialect/Arith canonicalize.mlir

[mlir][Arith] Fix crash when folding operations with dynamic-shaped tensors (#178428)

- Add static shape check in `getBoolAttribute` to prevent crash when
folding comparison operations with dynamic-shaped tensor types
- Add static shape check in `SelectOp::fold` before creating
`DenseElementsAttr` for the result
- Add test case to verify the fix

Fixes #178415.

Co-authored-by: Claude Opus 4.5 <noreply at anthropic.com>
DeltaFile
+11-0mlir/test/Dialect/Arith/canonicalize.mlir
+6-0mlir/lib/Dialect/Arith/IR/ArithOps.cpp
+17-02 files

LLVM/project 254eb56clang/include/clang/Basic AttrDocs.td, clang/lib/Analysis/LifetimeSafety LifetimeAnnotations.cpp

Transparent functions for all gsl::Pointers
DeltaFile
+75-0clang/test/Sema/warn-lifetime-safety.cpp
+32-19clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
+39-0clang/include/clang/Basic/AttrDocs.td
+146-193 files

LLVM/project 994bbf8clang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

[LifetimeSafety] Handle temporaries of non-trivial view types
DeltaFile
+22-0clang/test/Sema/warn-lifetime-safety.cpp
+10-7clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+1-0clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+33-73 files

LLVM/project 0e02669llvm/lib/Target/AArch64 AArch64InstrInfo.cpp AArch64PrologueEpilogue.cpp, llvm/test/CodeGen/AArch64 sign-return-address-pauthlr-slh.ll

[AArch64] Mark X16 as clobbered in PAUTH_EPILOGUE for hint-based PAuthLR

When users request branch protection with PAuthLR on targets that do not
support the PAuthLR instructions, the PAUTH_EPILOGUE falls back to using
hint-space instructions. This fallback sequence uses X16 as a temporary
register, but X16 was not listed in the clobber set.

Because Speculative Load Hardening uses X16, this omission made SLH
incompatible with this PAUTH_EPILOGUE path.

Mark X16 as clobbered so the compiler does not assume X16 is preserved across
the epilogue, restoring compatibility with Speculative Load Hardening and
avoiding incorrect register liveness assumptions. The clobber is added in C++
rather than TableGen, as X16 is only clobbered when PAuthLR is requested as a
branch protection variation and should not be treated as clobbered
unconditionally.
DeltaFile
+103-0llvm/test/CodeGen/AArch64/sign-return-address-pauthlr-slh.ll
+13-3llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+2-5llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
+6-0llvm/lib/Target/AArch64/AArch64InstrInfo.h
+1-2llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+3-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+128-106 files

LLVM/project 68450ballvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 vec_list_bias-inseltpoison.ll

[SLP]Support for tree throttling in SLP graphs with gathered loads

Gathered loads forming DAG instead of trees in SLP vectorizer. When
doing the throttling analysis for such graphs, need to consider partially
matched gathered loads DAG nodes and consider extract and/or gather
operations and their costs.
The patch adds this analysis and allows cutting off the expensive
sub-graphs with gathered loads.

Reviewers: hiraditya, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/177855

Recommit after revert in d733771113339608aff6002d1fa89aaf4a51c502, which
was related to a crash in SelectionDAG
DeltaFile
+99-14llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+12-13llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
+111-272 files

LLVM/project 4ec35a0llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/AMDGPU combine-scalar-selects.ll

[VectorCombine] Fix crash when folding select of bitcast (#177183)

Fixes #177144. Nits appreciated.

The fold in question does the following transformation:
Before
```
%bc = bitcast <4 x i32> %src to <16 x i8>
%e0 = extractelement <16 x i8> %bc, i32 0
%s0 = select i1 %cond, i8 %e0, i8 0
%e1 = extractelement <16 x i8> %bc, i32 1
%s1 = select i1 %cond, i8 %e1, i8 0
...
```

After
```
%sel = select i1 %cond, <4 x i32> %src, <4 x i32> zeroinitializer
%bc = bitcast <4 x i32> %sel to <16 x i8>

    [12 lines not shown]
DeltaFile
+351-0llvm/test/Transforms/VectorCombine/AMDGPU/combine-scalar-selects.ll
+7-1llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+358-12 files

LLVM/project 1e3c351openmp/runtime/src kmp_adt.h, openmp/runtime/unittests/ADT TestStringRef.cpp

use string_view
DeltaFile
+19-26openmp/runtime/src/kmp_adt.h
+2-2openmp/runtime/unittests/ADT/TestStringRef.cpp
+21-282 files

LLVM/project 8e362e1llvm/lib/Target/AArch64 AArch64PointerAuth.cpp, llvm/test/CodeGen/AArch64 sign-return-address-pauth-lr.ll

[AArch64] Remove dead code emission in Pointer Authentication (#175989)

The AArch64 Pointer Authentication pass was emitting address
materialization instructions that were never used. These instructions
formed dead code and served no purpose in the final control flow.

Remove the unnecessary ADRP/ADD sequence from the Pointer Auth codegen
and update the corresponding test to reflect the simplified output.

This avoids generating dead instructions and keeps the PAUTH LR sequence
minimal and correct.
DeltaFile
+0-26llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
+0-2llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+0-282 files

LLVM/project 8c944d0llvm/lib/Target/AArch64 AArch64PointerAuth.cpp

[AArch64] Refactor PACM emission in Pointer Authentication (NFC) (#175937)

Refactor the emission of PACM instructions in the AArch64 Pointer
Authentication code to simplify the control flow and reduce duplication.

This change consolidates the PACM generation logic, making the code
easier to follow and less error-prone, while preserving the existing
behavior and generated output.

No functional change is intended beyond the internal refactoring.
DeltaFile
+14-27llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+14-271 files

LLVM/project aa8e292flang/test/Lower character-local-variables.f90 complex-operations.f90

[flang] Converted five tests from old lowering to new lowering (part 9) (#176310)

Tests converted from test/Lower: c-interoperability-c-pointer.f90,
c-interoperability.f90, character-elemental.f90,
character-local-variables.f90, complex-operations.f90
DeltaFile
+122-61flang/test/Lower/character-local-variables.f90
+98-56flang/test/Lower/complex-operations.f90
+27-25flang/test/Lower/c-interoperability-c-pointer.f90
+18-21flang/test/Lower/character-elemental.f90
+20-12flang/test/Lower/c-interoperability.f90
+285-1755 files

FreeNAS/freenas 8d79f4csrc/middlewared/middlewared/plugins/boot_ boot_loader.py, src/middlewared/middlewared/plugins/update_ upload_location_linux.py utils_linux.py

Add umount utility

This commit exposes truenas_os.umount2 as an available utility
in mount.py, and replaces existing subprocess calls to the
umount command with the syscall-based utility.
DeltaFile
+63-1src/middlewared/middlewared/utils/mount.py
+2-1src/middlewared/middlewared/plugins/update_/upload_location_linux.py
+2-1src/middlewared/middlewared/plugins/update_/utils_linux.py
+2-1src/middlewared/middlewared/plugins/boot_/boot_loader.py
+69-44 files

LLVM/project 762ba88llvm/include/llvm/Analysis TargetTransformInfo.h, llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp

[LV] Add support for llvm.vector.partial.reduce.fadd (#163975)

Allows the Loop Vectorizer to generate `llvm.vector.partial.reduce.fadd`
intrinsics when sequences which match its requirements are found.
DeltaFile
+757-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+38-5llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+28-3llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+19-9llvm/include/llvm/Analysis/TargetTransformInfo.h
+14-10llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+16-3llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+872-308 files not shown
+899-3814 files

FreeNAS/freenas b98e853src/middlewared/middlewared/plugins nfs.py, src/middlewared/middlewared/plugins/service_/services nfs.py

NAS-138841 / 26.0.0-BETA.1 / Remove configuration of legacy NFS client tracking. (#18112)

Debian Trixie has removed support for the legacy NFS client tracking.
This PR makes the changes to follow that.

Update CI test to match.
CI tests run with no change in behavior.

Also confirmed, on single and HA systems, that multiple clients doing
active writing are correctly paused and restart write operations with no
loss of data or corruption across a reboot and sudden power loss.

This PR is part of a pair. The companion PR is
https://github.com/truenas/linux/pull/237
DeltaFile
+0-25src/middlewared/middlewared/plugins/nfs.py
+0-8src/middlewared/middlewared/plugins/service_/services/nfs.py
+0-6tests/api2/test_300_nfs.py
+0-393 files

LLVM/project 1e0e7f7llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] Avoid repeating the type
DeltaFile
+2-1llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+2-11 files

LLVM/project cde40f4llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] add const and rename
DeltaFile
+9-8llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+9-81 files

LLVM/project d267dbellvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] reuse vector
DeltaFile
+2-2llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+2-21 files

FreeNAS/freenas 0a1a19bsrc/middlewared/middlewared/api/v26_04_0 tn_connect.py, src/middlewared/middlewared/plugins/truenas_connect update.py

NAS-137278 / 26.0.0-BETA.1 / Add TrueNAS Connect account tier status to tn_connect.config (#18116)

DeltaFile
+13-1src/middlewared/middlewared/plugins/truenas_connect/update.py
+4-0src/middlewared/middlewared/api/v26_04_0/tn_connect.py
+17-12 files

LLVM/project afcd690llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] Add const
DeltaFile
+20-18llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+20-181 files

LLVM/project 714e829llvm/lib/Target/AArch64 AArch64SystemOperands.td AArch64Features.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Allow some `tlbip` insns to be used with only +tlbid

Allow `tlbip` instructions containing *E1IS*, *E1OS*, *E2IS* or *E2OS*
to be used with `+tlbid` or `+d128`. This is because the 2025 Armv9.7-A
MemSys specification says:

```
All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions
that are currently dependent on FEAT_D128 are updated to be dependent
on FEAT_D128 or FEAT_TLBID
```
DeltaFile
+110-110llvm/test/MC/AArch64/armv9a-sysp.s
+23-12llvm/lib/Target/AArch64/AArch64SystemOperands.td
+27-2llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+13-5llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+7-4llvm/lib/Target/AArch64/AArch64Features.td
+10-0llvm/unittests/TargetParser/TargetParserTest.cpp
+190-1333 files not shown
+201-1399 files

LLVM/project a512065libc/config/gpu config.json

[libc] Do not use stack protectors or frame pointers on GPU

Summary:
This doesn't work because they're unused in some contexts. Added in
https://github.com/llvm/llvm-project/pull/178136
DeltaFile
+8-0libc/config/gpu/config.json
+8-01 files

FreeNAS/freenas 90232c6src/middlewared/middlewared/api/base/server/ws_handler rpc.py

Address review
DeltaFile
+3-2src/middlewared/middlewared/api/base/server/ws_handler/rpc.py
+3-21 files

LLVM/project 6074f9bllvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp, llvm/test/CodeGen/AArch64 arm64-int-neon.ll arm64-vshift.ll

[AArch64][GlobalISel] Add support for scalar variants of neon right shifts (#178207)

Neon intrinsics are able to operate on single-element vectors (e.g <1 x
i64>). However, LLVM doesn't allow single-element vectors, and instead
converts them to scalar values (e.g i64) in the frontend.
To get around this, the backend must place these scalar values onto an
fpr register bank, in order for the intrinsic to operate on the value as
a vector.

Previously, scalar right shift intrinsics were not legalising due to
misconfigured logic in AArch64LegalizerInfo, which treated non-vector
variants of these intrinsics as invalid.
This has been fixed so that the following can lower:
sqshrn
sqshrun
sqrshrn
sqrshrun
uqshrn
uqrshrn
DeltaFile
+6-11llvm/test/CodeGen/AArch64/arm64-int-neon.ll
+6-6llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+0-7llvm/test/CodeGen/AArch64/arm64-vshift.ll
+12-243 files

LLVM/project 919113dllvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] miscleaneaous renaming
DeltaFile
+34-37llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+34-371 files

FreeNAS/freenas 80cb9a3src/middlewared/middlewared/api/v26_04_0 tn_connect.py, src/middlewared/middlewared/plugins/truenas_connect update.py

Add TrueNAS Connect account tier status to tn_connect.config
DeltaFile
+13-1src/middlewared/middlewared/plugins/truenas_connect/update.py
+4-0src/middlewared/middlewared/api/v26_04_0/tn_connect.py
+17-12 files

LLVM/project a5ab8e8llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] found -> reached
DeltaFile
+1-1llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+1-11 files