[Clang][C2y] Make the 'if' declaration extension warning on by default
Declarations in the condition of 'if' and 'switch' statements (N3356)
were previously only diagnosed in pre-C2y modes under -pedantic, since
the C compatibility warnings default to Extension. Promote the
diagnostic to an ExtWarn so users on older language modes are told
they are relying on a C2y extension; -Wno-c2y-extensions silences it.
Co-Authored-By: Claude Fable 5.1 <noreply at anthropic.com>
[Clang][C2y] Simplify condition-declaration diagnostics in C
Key the diagnostics on whether a declaration is permitted as the
condition (only as the sole clause of an 'if' or 'switch'), so the two
"expected expression" emissions collapse into one and the first-clause
check is no longer nested inside the branching. No functional change.
Co-Authored-By: Claude Fable 5.1 <noreply at anthropic.com>
[DAGCombiner] Merge narrow stores after a store of another type (#233120)
Stop collection at a store of a different memory type instead of
rejecting the narrow stores already collected. Keep that store as
the incoming chain of the merged store.
Fixes: https://github.com/llvm/llvm-project/issues/198242
Assisted-by: Codex
[lldb][bazel] Support parse_headers (#232936)
Reorganize the lldb Bazel files so that Bazel header parsing works:
- Combine all headers into a single Headers target.
- Fix a few `select`s to ensure that host-specific files aren't being
included on the wrong host platforms.
- Fix a few circular dependencies between header files.
Testing:
- I ran `bazel build --config=generic_clang @llvm-project//lldb/...` and
confirmed there were no errors.
- I build lldb-server and confirmed that the file size was the same (to
the nearest megabyte) before and after.
- I ran `bazel query 'deps(@llvm-project//lldb:lldb-server)'` before and
after this change, and confirmed that no new code was being linked into
lldb-server.
[Offload][Omp] Move getHostDeviceUid to libomptarget (#234193)
This is just a static function used from within the OpenMP APIs
implementation so moving it out of the Plugin Interface.
[SPIR-V] Fix pointee types of pointers extracted from or inserted into aggregates (#227599)
The pointee type of a pointer extracted from an aggregate was deduced
from its uses, so it could disagree with the member's type: e.g. `load
i32` through the `ptr` member of `{ ptr, i8 }`, which is lowered as a
pointer to `i8`. `OpCompositeExtract` and `OpCompositeInsert` require
the types to match, so this produced invalid SPIR-V.
Derive an extracted pointer's pointee type from the aggregate member,
and cast inserted pointers to the member type. Mismatches are then
handled by the existing `spv_ptrcast` machinery, which keeps
pointer-cast legalization for logical SPIR-V and emits no casts with
`SPV_KHR_untyped_pointers`.
[LV] Verify DominatorTree once per function (#231820)
`processLoop()` verified the whole function's dominator tree after every
successfully vectorized or interleaved loop.
Move the check next to the existing once-per-function `verifyFunction()`
assertion, which was moved out of `processLoop()` for the same reason in
#216448. On a generated function with 12814 basic blocks and 99706
instructions where LoopVectorize vectorizes 2304 of the 3092 loops it
analyzes, `DT->verify()` goes from 2304 calls to one: `loop-vectorize`
wall time drops 72% and instructions retired 69%.
For verify this perf and proofread, I got help from AI assistant.
The per-loop DT check under `EXPENSIVE_CHECKS` in `executePlan()` is
left unchanged.
Fixes #218487
[clang-repl] Link builtin bitcode into every PTU (#229788)
BackendConsumer::LinkInModules links the -mlink-builtin-bitcode modules
into the first module it finalizes and clears the list. The interpreter
runs the consumer once per PTU, so only the initial PTU links libdevice.
A kernel using device math in a later PTU references undefined `__nv_*`
symbols and the PTX JIT rejects it with cudaErrorInvalidPtx.
Reload the builtin bitcode for every PTU in incremental mode. The
modules get internalized into whatever links them, so each PTU needs its
own copy. loadLinkModules now takes a flag to open only those entries,
so plain -mlink-bitcode-file inputs are linked once and never reopened.
Add a lit test that calls sinf and expf from a kernel (needs a GPU) and
a unittest that links one bitcode library as builtin and an empty one as
a plain bitcode file, deletes the plain one once the interpreter is up,
and checks that two device PTUs define the builtin function rather than
declare it.
[flang][OpenMP] Ignore DECLARE_SIMD and warn about missing implementa… (#232712)
…tion
Currently DECLARE_SIMD emits a "not yet implemented" error in the MLIR
to LLVM IR translation.
DECLARE_SIMD is a hint to the compiler and ignoring it is technically
speaking a conforming implementation (although obviously not desirable).
Do not abort compilation when DECLARE_SIMD is encountered, but emit a
warning that it's currently ignored.
(cherry picked from commit 5ca62fdee645ec253263e41a45fe626c6b66be22)
Fixes: https://github.com/llvm/llvm-project/issues/234108
[flang][OpenMP] Fix the creation of implicit symbols for locals (#233600)
When creating implicit symbols for variables that are declared in a
nested scope (e.g. in a BLOCK), the constructs that enclose the symbol
declaration must be skipped, since the symbol doesn't exist in them.
Fixes #230273
Assisted-By: Claude Opus 5.5
AArch64: Skip physical registers in MIPeepholeOpt visitORR
Doubt this appears in any real case, but ran into this when auditing
cases which could possibly need to clear kill flags on physical
registers. Also stop using getUniqueVRegDef in an SSA pass.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[Loads] Add MUL/SHL handling in decomposeLinearExpression (#222574)
Implements a FIXME in decomposeLinearExpression, allowing it to look
through multiplications and left-shifts.
We peel the variable index and keep track of the accumulated scale from
the multiplications and shifts and apply this scale when we return the
final expression.
This allows decomposeLinearExpression to extract more statically known
information into the `Scale` of the linear expression.
assisted-by: codex
[flang] Resolve symbols through a SymbolTableCollection in FIR to LLVM codegen (#232555)
The FIR to LLVM conversion patterns resolve `fir.address_of`, derived
type descriptor globals, comdat selectors, the CUDA device module and
the malloc/free declarations with `ModuleOp::lookupSymbol`, a linear
walk of the module body. A compilation unit that uses a derived type
reaching N other types carries `linkonce_odr` runtime type info for all
of them (about 25 globals per type), so the conversion performs O(N)
lookups of O(N) cost each and compile time is quadratic in the number of
module symbols: a 12-line subroutine that only passes a `TYPE(TOP)`
dummy, where the module defines 1000 types, takes 137 s to compile,
60-67% of it inside `SymbolTable::lookupSymbolIn`.
This gives the patterns an optional `mlir::SymbolTableCollection`, the
way `populateFuncToLLVMConversionPatterns` already takes one:
`fir::FIROpConversion` and `populateFIRToLLVMConversionPatterns` accept
a `SymbolTableCollection *` (default `nullptr`, which keeps the linear
lookups for other users), the lookup sites go through
`fir::lookupSymbolIn`, and the sites that create symbols register them.
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AMDGPU: Stop adding kill flags on virtual registers
Fix misc. AMDGPU passes and hooks running before register allocation
introducing kill flags. There's no point in doing this anymore.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AMDGPU: Stop adding kill flags in SILoadStoreOptimizer
No pre-RA pass should try to create kill flags on virtual registers.
They're unused in any pre/mid-RA pass, and stripped by LiveIntervals.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AArch64] [DAG] combine vector_interleave to zip1/zip2 (#231066)
Interleaving the low (or high) halves of two vectors is exactly what a
single ZIP1 (or ZIP2) of the full vectors computes:
(vector_interleave (extract_subvector A, I), (extract_subvector B, I))
-> Z = (zip1 A, B) if I == 0, or (zip2 A, B) if I == NumElts/2
results: (extract_subvector Z, 0), (extract_subvector Z, NumElts/2)
Without this combine, type legalization splits or promotes the
half-width operands first, which destroys the pattern and leads to
unpack + zip/trn/uzp sequences, or even a stack round trip for types
such as <vscale x 1 x double>.
The combine runs before operation legalization so the half-width types
are still intact. It is restricted to legal full-width types and skips
fixed-length vectors lowered via SVE, where ZIP1/ZIP2 on the fixed type
cannot be selected.
Assisted By: Claude Opus
[libc] Use a syscall wrapper for `getcpu` (#234157)
This PR move `getcpu` behind the centralized syscall wrappers, following
`libc/docs/dev/syscall_wrapper_refactor.md`.
