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databases/ladybug: Update 0.16.0 => 0.16.1

Changelog:
https://github.com/LadybugDB/ladybug/releases/tag/v0.16.1

PR:             295039
Sponsored by:   UNIS Labs

[NFC][AMDGPU][Doc] Add developer guideline

This guideline covers topics on top of existing LLVM guideline.

misc/crush: Update to 0.65.3

Changelog:
- https://github.com/charmbracelet/crush/releases/tag/v0.65.2
- https://github.com/charmbracelet/crush/releases/tag/v0.65.3

Reported by:    GitHub (watch releases)

cloudflare-speed-cli: update to 0.6.7

lang/hs-futhark: update 0.25.36 → 0.26.1

lang/hs-koka: update 3.2.2 → 3.2.3

devel/py-uv-build: update 0.11.8 → 0.11.10

net/wstunnel: update 10.5.4 → 10.5.5

www/cpp-httplib: update 0.43.2 → 0.43.3

editors/cpeditor: update 7.0.1 → 7.1.1

devel/{,py-}uv: update 0.11.8 → 0.11.10

sysutils/mise: update 2026.5.0 → 2026.5.1

[CIR][RISCV] Support zbkb builtin codegen (#195401)

Include 4 builtins: __builtin_riscv_brev8_32, __builtin_riscv_brev8_64,
__builtin_riscv_zip_32, __builtin_riscv_unzip_32.

[RISCV] Rename and invert UseGPRForF16_F32/UseGPRForF16_F32. (#195971)

Rename to AllowFPR. We used to set these flags when we ran out of FPRs,
but we haven't for a while. I think rephrasing as allow FPR is a bit
clearer.

[RISCV][P-ext] Remove VXSAT from SHL/SHLR/SHA/SHAR. Add to PSAS and PSSA. (#195488)

[𝘀𝗽𝗿] initial version

Created using spr 1.3.4

py-ksef2: update to 0.13.1

[RFC][Docs] Clarify brace omission for single-line bodies

Update the Coding Standards brace guidance to emphasize that braces should be
omitted only for simple bodies that do not wrap across multiple physical lines.

[SPIRV] Dummy implementation of the `returnaddress` and `frameaddress` intrinsics (#195976)

The SPIR-V specification doesn't define any operations for the
return and frame address. The valid implementation in this case is to
produce a null pointer.

Assisted-by: Claude Opus 4.6 <noreply at anthropic.com>

[SPIRV] Add support for SPV_KHR_abort extension (#193037)

This commit adds support for the SPV_KHR_abort extension in the SPIRV
backend. The extension allows shaders to abort execution with a custom
message.

Assisted-by: Claude Opus 4.7 <noreply at anthropic.com>

---------

Co-authored-by: Marcos Maronas <mmaronas at amd.com>

[RISCV][MC] Add experimental `Zvvmm` MC support (#193956)

Add initial MC-layer support for `Zvvmm` from the experimental [RISC-V
Integrated Matrix
Extension](https://github.com/riscv/integrated-matrix-extension/blob/d2e64b4922f5c2c416761f3c7c997d4f0cf814d9/src/integrated-matrix.adoc)
(version
[2026-04-23](https://github.com/riscv/integrated-matrix-extension/releases/tag/riscv-isa-release-d2e64b4-2026-04-23))

This patch:
- Adds the experimental `zvvmm` 0.1 extension feature, depending on
`zve32x`.
- Adds assembler/disassembler definitions for the integer matrix
multiply-accumulate instructions:
  - `vmmacc.vv`
  - `vwmmacc.vv`
  - `vqmmacc.vv`
  - `v8wmmacc.vv`
- Adds IME vtype helper modeling in `RISCVVType`, covering lambda
encoding/decoding, IME vtype field masks,

    [3 lines not shown]

devel/py-pytz: Update to 2026.2

fold memref global async to lds

Signed-off-by: Eric Feng <Eric.Feng at amd.com>

nits

Signed-off-by: Eric Feng <Eric.Feng at amd.com>

format

Signed-off-by: Eric Feng <Eric.Feng at amd.com>

nit

Signed-off-by: Eric Feng <Eric.Feng at amd.com>

[clang][ssaf] Add `clang-ssaf-analyzer` (#188881)

This patch introduces `clang-ssaf-analyzer`, a new SSAF tool that runs whole-program analyses over an `LUSummary` and writes the resulting `WPASuite` to an output file.

support gfx942 bf16 sparse mfma in gfx950

Signed-off-by: Eric Feng <Eric.Feng at amd.com>

[SSAF] Fix -Wunused-variable (#195975)

Add [[maybe_unused]] given the operation is side effecting/returns
multiple values.

[libc][sched] Fix generated scheduler prototypes (#195332)

Fixes generated <sched.h> prototypes for
sched_getscheduler/sched_setscheduler and adds compile-time
public-header coverage

ichsmb: add Ice Lake-LP (0x34a3) and Ice Lake-N (0x38a3) SMBus device IDs

Add PCI device IDs for two Ice Lake PCH SMBus controller variants:
- 0x34a3 (Ice Lake-LP), previously listed as the generic "Ice Lake" entry (ID_ICELAKE), renamed to ID_ICELAKELP for clarity.
- 0x38a3 (Ice Lake-N), a separate PCH variant not previously supported.

Reviewed by:    adrian
Differential Revision:  https://reviews.freebsd.org/D56732