[flang][cuda] Propagate CUDA attrs from parent variable to component deallocs (#220059)
This is a follow up to
[#206614](https://github.com/llvm/llvm-project/pull/206614), which made
`allocate(foo(i)%arr(...))` inherit `foo`'s CUDA memory attribute, but
did not add the equivalent inheritance for `deallocate(foo(i)%arr)`. The
deallocation still lowered to an inlined `fir.freemem`, so memory
obtained from a CUDA allocator was released with libc `free()`.
The allocate side already walked the `DataRef` chain for a
CUDA-attributed parent, but the helpers were private to
`AllocateStmtHelper` and unreachable from the deallocate path. This
patch hoists `findCUDAAttrInDataRef` to file scope, adds
`getCUDAAttrParentSymbol(AllocateObject)` beside it, and reduces the
existing member to a thin wrapper. The allocate behavior is unchanged.
`genDeallocate` gains an optional `cudaSymbol` used only for the CUDA
decisions (`isCudaSymbol` and the `genCudaDeallocate` call).
`genDeallocateStmt` supplies the parent symbol, which is non-null only
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[WebAssembly] Mark SIMD min and max as commutable (#219812)
Vector add/mul and scalar floating-point min/max are already marked as
commutable. This extends the same property to floating-point vector
min/max, allowing better WebAssembly register stackification.
Should avoid any locals as per what's happening now
```
.local v128
call red
local.set 0
call green
local.get 0
f32x4.min
```
dd(1): Sync with FreeBSD
New features:
- Added conv=fsync flag
- Added conv=fdatasync flag
- Added oflag=fsync and oflag=sync flags
- Added iflag=fullblock flag
- Added iflag=direct and oflag=direct flags that set O_DIRECT
Fixes:
- Fixed SIGINT handling.
[SelectionDAG] Fix CSE keys that disagree with SDNode::Profile (#219911)
A getNode helper builds its lookup ID by hand; matching it later
rebuilds one from the node with AddNodeIDCustom. Where the two disagree
the compare always fails and the node never CSEs. Fix whichever side is
wrong: the labels, DEACTIVATION_SYMBOL, GET/SET_FPENV_MEM and
EXPERIMENTAL_VECTOR_HISTOGRAM have no case; getLifetimeNode keys on a
frame index operand 1 already carries, getStridedLoadVP on the result
type instead of the memory type, and getPseudoProbeNode drops the
attributes its case profiles.
Ask AtomicSDNode instead of an opcode list stale since ATOMIC_LOAD_FADD,
and add the two opcodes its own classof was missing.
AddNodeIDCustom now takes the opcode to profile under, so MorphNodeTo's
pre-morph lookup keys on what the morph produces. Machine opcodes
profile nothing: the morph overlays MachineSDNode's memory references on
the fields the MemSDNode checks read.
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[NFC][HLSL] Refactor texture type declaration (#219561)
Fixes https://github.com/llvm/llvm-project/issues/219542
Refactors texture type declaration in `HLSLExternalSemaSource.cpp` so
that new
texture types can more easily be added without adding a bunch of new
helper
functions.
This is accomplished with the introduction of a new `TextureTypeInfo`
struct
to record the properties of each texture type, as well as its
capabilities
indicated by the `TexCap` bitmask enum.
Adding a new texture type to be declared should, in most cases, only
require
appending a new entry to the static `TextureTypes` array of
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[CSSPGO] Don't let pseudo probes block early-exit vectorization (#219872)
llvm.pseudoprobe is modeled as accessing inaccessible memory, so
mayReadFromMemory()/mayWriteToMemory() return true even though the
intrinsic
carries no real memory dependence. An otherwise vectorizable early-exit
loop
is therefore rejected as soon as it contains a pseudo probe.
This patch skips pseudo probes in isVectorizableEarlyExitLoop(),
isReadOnlyLoop() and
areAllLoadsDereferenceable() so the three checks agree and such loops
vectorize as they would without pseudo probe instrumentation.
Discussion:
https://discourse.llvm.org/t/csspgo-unblocking-pseudo-probe-safe-optimizations/90946
[ORC] Add SymbolStringPtr overloads for recordAddr/recordProxy (#220125)
Allow clients to pass symbol names as SymbolStringPtrs (in addition to
StringRefs).
[AMDGPU] Allow combining uniform OR/AND to V_PERM (#220048)
Allow the OR/AND -> V_PERM DAG combine for values, even if they are
uniform.
Co-authored by Brendon Cahoon and Cursor
[Clang] Honor -Xarch_gfx* when linking the UBSan offload runtime
Empty bound architecture misses per-GPU sanitizer flags, so inspect each
offload arch when deciding whether the host interceptor is required.
[Clang] Enable UBSan for AMDGPU device offload
Summary:
This enables the device UBSan runtime for AMDGPU decides. Primarily this
required modifications to the `addSanitizerRuntime` interface so we can
query the compilation's offload status. Also need to forward it through
the linker wrapper interface. Works on all AMDGPU offload, slight hacks
around the other targets as they do not advertise sanitizer
runtimes properly.
This is linked in via a new `-u __ubsan_device_initialize` hook to pull
in the side library. This is standard behavior and keeps the core logic
mostly unchanged and re-used.
[LoongArch] Add omitted LASX patterns for vector extend (#219351)
Adds omitted 128-bit to 256-bit patterns for `sign_extend_vector_inreg`,
including `v16i8 -> v4i64` and `v8i16 -> v4i64`, which will generate by
the combination of `icmp + or/and/xor + zext/sext`, all related tests
are added.
Fix: https://github.com/llvm/llvm-project/issues/219224
Trim stale and redundant comments in the alert applicability work
This commit adds changes to correct or remove the comments this branch introduced. Four were plainly wrong -- the classify ordering was backwards, an unlicensed system does have a licence daemon answering it, a docstring called a HARDWARE class an HA one, and a guard test reads a whole class body rather than check() -- and the rest either restated the code or pinned counts, gate lists and file paths that drift. No behaviour changes: every touched file parses to an identical AST once docstrings are stripped, and the frozen inventory is byte-identical.
[ConstantTime] Address reviewer feedback on llvm.ct.select core
- Fix vector-split build error: call the existing SplitRes_Select for
CT_SELECT instead of the nonexistent SplitRes_CT_SELECT.
- Fix a VP_MERGE result-split regression: the CT_SELECT switch reformat had
moved ISD::VP_MERGE onto the SplitRes_SELECT_CC line, which reads operand 4
(out of bounds for VP_MERGE's 4 operands) and builds a SELECT_CC without
splitting the EVL, crashing or miscompiling any vp.merge whose result
vector must be split. Restore it to the SplitRes_Select group.
- Accept byte types (bN and vectors of them) in the Verifier and document
them in LangRef; add byte-typed X86 codegen and Verifier test coverage.
- Drop the redundant `VT0 == MVT::i1` guard in visitCT_SELECT; the inner
condition-type checks already cover correctness after promotion.
- LangRef: reword the constant-fold rule to the enforceable "constant
operand" form, restate fast-math flags via the general FP-call rule (only
nnan/ninf are poison-generating), and switch undef/poison to match select,
dropping the noundef return attribute so poison propagates (both arms always
evaluate, so poison in either yields poison).
- Revert an unrelated whitespace change in LegalizeTypes.h.
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[AArch64] Constraint SUBS register classes after if-converting CMPBR (#219884)
When generating SUBS to un-fuse the Armv9.6 Compare-and-Branch immediate
variants CBWPri and CBXPri during if-conversion, we missed to constraint
the register classes, leading to a verifier crash.
[SLP][NFC] Pre-commit regression tests for InsertValueInst element size. (#219221)
Add regression tests for SLP vectorization of insertvalue chains over
homogeneous structs ({ i64, i64 } and { i32, i32, i32, i32 }).
The tests capture the current behavior prior to the fix, where
getVectorElementSize() uses the aggregate's total size, potentially
limiting the maximum vectorization factor on targets with a bounded
TTI::getMaximumVF().
A follow-up patch will fix getVectorElementSize() to recurse through
InsertValueInst and update these CHECK lines to reflect the correct
vectorized output.
Tests added:
- llvm/test/Transforms/SLPVectorizer/RISCV/insertvalue-elt-size.ll
Co-authored-by: Aditya-Chaudhary1 <aditya.chaudhary1 at ibm.com>
Save CET state on Intel vmm(4) hosts before vm entry.
On Intel hosts with CET support, vmm must set the host CET related
state in the VMCS so VMX will restore it on vm exit. vmm was not
setting this before vm entry resulting in VMX disabling CET on host
cpus when returning to the kernel.
Additionally, vmm should explicitly zero the initial guest state
related to CET and supervisor shadow stacks instead of relying on
the memory backing the VMCS to have been zeroed.
ok mlarkin@
[ConstantTime] Address reviewer feedback on llvm.ct.select core
- Fix vector-split build error: call the existing SplitRes_Select for
CT_SELECT instead of the nonexistent SplitRes_CT_SELECT.
- Fix a VP_MERGE result-split regression: the CT_SELECT switch reformat had
moved ISD::VP_MERGE onto the SplitRes_SELECT_CC line, which reads operand 4
(out of bounds for VP_MERGE's 4 operands) and builds a SELECT_CC without
splitting the EVL, crashing or miscompiling any vp.merge whose result
vector must be split. Restore it to the SplitRes_Select group.
- Accept byte types (bN and vectors of them) in the Verifier and document
them in LangRef; add byte-typed X86 codegen and Verifier test coverage.
- Drop the redundant `VT0 == MVT::i1` guard in visitCT_SELECT; the inner
condition-type checks already cover correctness after promotion.
- LangRef: reword the constant-fold rule to the enforceable "constant
operand" form, restate fast-math flags via the general FP-call rule (only
nnan/ninf are poison-generating), and drop the redundant undef/poison
propagation paragraph that the noundef return already covers.
- Revert an unrelated whitespace change in LegalizeTypes.h.
- Drop redundant intrinsic declarations from the InstSimplify test and soften
the SelectionDAGBuilder fast-math comment.
[BOLT] Parse .eh_frame CFI programs on demand to reduce memory (#214896)
BOLT read the entire .eh_frame up front via DwCtx->getEHFrame(), which
parses and caches the CFI instruction program of every CIE/FDE in the
binary for the whole run. On a large binary, this dominated file-object
discovery: CFIProgram::parse accounted for ~6.5 GB and the cached
DWARFDebugFrame ~6.9 GB of live memory. Yet the CFI programs are only
consumed in CFIReaderWriter::fillCFIInfoFor, and only for the functions
BOLT actually disassembles. discoverFileObjects itself needs nothing but
each FDE's address and range for function-boundary checks.
Here we parse .eh_frame for its index only, and decode each function's
CFI program on demand, lazily, only for the functions that really need
it. In a large binary, DWARFDebugFrame::parse drops from 6922.2 MB to
587.6 MB, the residual being the lightweight FDE/CIE index (entries
without instruction programs), and readSpecialSections falls from 7078.7
MB to 738.6 MB on the tested binary for which BOLT's RSS is about
80-120GB.
[HLSL] Add UAV-specific texture load method (#218728)
Fixes https://github.com/llvm/llvm-project/issues/218535
UAV texture resources were using the SRV version of the .Load() method
and resulted in no matching member function calls when attempted to be
used.
This PR fixes that issue by adding addRWTextureLoadMethods() to
HLSLBuiltinTypeDeclBuilder.cpp and fixing the codegen for
BI__builtin_hlsl_resource_load_level to handle UAVs.
Assisted by: Claude Opus 5
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