LLVM/project 903cfcfllvm/include/llvm/IR IntrinsicsNVVM.td, llvm/test/CodeGen/NVPTX dead-shfl.ll

[NVVM] Update properties for non-sync variants of the SHFL intrinsics (#189615)

Non-sync SHFL variants (shfl without .sync) are pure functions of their SSA operands and the active thread mask. Assign IntrReadMem, IntrInaccessibleMemOnly and IntrWillReturn so that: - Reading the implicit mask state is modeled for correct ordering with other convergent operations - Truly dead non-sync shfl code can still be DCE'd

Sync SHFL variants keep IntrInaccessibleMemOnly (no IntrReadMem, no IntrWillReturn) to model synchronization side effects and prevent unsafe DCE/reordering.
DeltaFile
+19-0llvm/test/CodeGen/NVPTX/dead-shfl.ll
+13-4llvm/include/llvm/IR/IntrinsicsNVVM.td
+32-42 files

LLVM/project daf7a8fllvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU inline-asm-vgpr-range-unsupported-width.ll

AMDGPU coverity fixes (#182013)

Coverity fixes
DeltaFile
+12-0llvm/test/CodeGen/AMDGPU/inline-asm-vgpr-range-unsupported-width.ll
+2-1llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-0llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+16-24 files

LLVM/project 5616ad7llvm/lib/Analysis ConstantFolding.cpp, llvm/lib/Target/NVPTX NVPTXTargetTransformInfo.cpp

[NVPTX] Lower nvvm.fmax to maximumnum not maxnum (#189976)

Converting nvvm.{fmin/fmax} into llvm.{min/max}num is slightly
incorrect, as {min/max}(a, sNaN) should produce "a" according to the PTX
spec, but LLVM's {min/max}num intrinsics may return either NaN or "a".

Use the {min/max}imumnum intrinsics instead for correct sNaN behaviour.

Also tidy up NVVM FMin/FMax constant-folding using these tighter
definitions of how the NVVM intrinsics map to {min/max}imum and
{min/max}imumnum.
DeltaFile
+14-14llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
+12-12llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll
+5-13llvm/lib/Analysis/ConstantFolding.cpp
+6-6llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll
+37-454 files

LLVM/project ada5383lldb/test/API/linux/aarch64/sme_only_registers TestSMEOnlyRegisters.py main.c

[lldb][AArch64][Linux] Add tests for SME only core files (#189985)

Part of #138717.

This did not require any changes to core file handling. Since a static
snapshot of an SME only system looks pretty much the same as one from
the same state on a system with SVE and SME.

For this reason, we're only testing 2 combinations. In total these
include streaming and non-streaming, ZA on and off, and 2 different
vector lengths. I think this is enough to prove that the existing code
is working.
DeltaFile
+25-0lldb/test/API/linux/aarch64/sme_only_registers/TestSMEOnlyRegisters.py
+8-3lldb/test/API/linux/aarch64/sme_only_registers/main.c
+0-0lldb/test/API/linux/aarch64/sme_only_registers/core_simd_on_32
+0-0lldb/test/API/linux/aarch64/sme_only_registers/core_streaming_off_64
+33-34 files

LLVM/project 8798c1dllvm/lib/Target/AMDGPU SIISelLowering.cpp

Review comments:
use input wave instruction for checks
DeltaFile
+7-7llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+7-71 files

LLVM/project e4a7113llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fsub.ll llvm.amdgcn.reduce.fadd.ll

[AMDGPU] DPP wave reduction for double types - 2

Supported Ops: `fadd` and `fsub`
DeltaFile
+1,030-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+1,008-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+12-10llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,050-2703 files

LLVM/project ebdd7e9llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] DPP wave reduction for long types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,113-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,079-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+72-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,264-3083 files

LLVM/project c5a7fc9llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.min.ll llvm.amdgcn.reduce.max.ll

[AMDGPU] DPP wave reduction for long types - 1

Supported Ops: `min`, `max`, `umin`, `umax`
DeltaFile
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+185-42llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4,441-4745 files

LLVM/project 368e697llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmax.ll llvm.amdgcn.reduce.fmin.ll

[AMDGPU] DPP wave reduction for double types - 1

Supported Ops: `fmin` and `fmax`
DeltaFile
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+27-13llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,251-4813 files

LLVM/project 219874dllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

[AMDGPU] DPP wave reduction for long types - 3

Supported Ops: `and`, `or`, `xor`
DeltaFile
+984-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+12-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,916-3494 files

LLVM/project b9e1e0ellvm/lib/Target/AMDGPU SIISelLowering.cpp

Refactor lambda to a helper function
DeltaFile
+26-22llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+26-221 files

FreeBSD/ports a0718fdsecurity/ossec-hids-local-config Makefile

security/ossec-hids-local-config: Unbreak

PR:             294020
MFH:            2026Q2
Differential Revision:  https://reviews.freebsd.org/D56303

(cherry picked from commit 082e36892d5c1f00fb726a360d7484090e57b343)
DeltaFile
+2-2security/ossec-hids-local-config/Makefile
+2-21 files

FreeBSD/ports 082e368security/ossec-hids-local-config Makefile

security/ossec-hids-local-config: Unbreak

PR:             294020
MFH:            2026Q2
Differential Revision:  https://reviews.freebsd.org/D56303
DeltaFile
+2-2security/ossec-hids-local-config/Makefile
+2-21 files

LLVM/project 2cdf60aclang/lib/Basic/Targets AArch64.cpp AArch64.h, clang/lib/Sema SemaARM.cpp

[AArch64][clang] Use tablegen rather than hard-coded feature dependencies

Refactor AArch64 frontend feature handling so extension relationships come
from the TargetParser extension graph instead of hand-written dependency
code in C++. This makes `llvm::AArch64::ExtensionSet` the source of
truth for dependency expansion while still keeping the short `Has...` names
used in the frontend code.

This removes a large amount of duplicated implication logic from
`handleTargetFeatures` and related feature queries. The frontend now
rebuilds its extension state from TableGen-derived data and then derives
its cached feature state from that, rather than maintaining parallel
dependency rules in C++.

I also preserved several pieces of historical frontend behaviour that are
not represented directly in the extension graph. Explicit disables such as
`no-sme` still win after implied-feature expansion, direct `+fullfp16` and
`+jscvt` still restore the expected NEON-facing state, and SME-family
features no longer incorrectly appear to enable AdvSIMD/NEON.

    [4 lines not shown]
DeltaFile
+234-279clang/lib/Basic/Targets/AArch64.cpp
+9-71clang/lib/Basic/Targets/AArch64.h
+69-0clang/lib/Basic/Targets/AArch64TargetInfoFeatures.inc
+22-0clang/test/Preprocessor/aarch64-target-features.c
+3-3clang/lib/Sema/SemaARM.cpp
+5-0clang/test/Sema/aarch64-sme-func-attrs-without-target-feature.cpp
+342-3531 files not shown
+343-3547 files

LLVM/project db61d1corc-rt/include/orc-rt QueueingTaskDispatcher.h, orc-rt/lib/executor QueueingTaskDispatcher.cpp

[orc-rt] Refactor QueueingTaskDispatcher to use an external TaskQueue. (#190920)

QueueingTaskDispatcher now takes a TaskQueue by reference rather than
maintaining an internal queue. This lets API clients retain direct
access to the queue after transferring dispatcher ownership to the
Session.

TaskQueue operations (takeFirstIn, takeLastIn) are blocking: callers
wait until a task arrives or the queue is shut down. This enables a
simple client idiom:

```
  QueueingTaskDispatcher::TaskQueue TQ;
  Session S(std::make_unique<QueueingTaskDispatcher>(TQ), ...);
  S.attach(<controller access>);

  while (auto T = TQ.takeFirstIn())
    T->run();
```
DeltaFile
+148-205orc-rt/unittests/QueueingTaskDispatcherTest.cpp
+33-17orc-rt/include/orc-rt/QueueingTaskDispatcher.h
+25-16orc-rt/lib/executor/QueueingTaskDispatcher.cpp
+206-2383 files

FreeBSD/src 1c793e7usr.bin/stat/tests readlink_test.sh

stat: Nits in readlink tests

* The f_flag test may fail if a component of the full path to the
  temporary directory is a symbolic link.

* The n_flag test had an empty head; give it a description.

* Use consistent quoting.

MFC after:      1 week
Sponsored by:   Klara, Inc.
Reviewed by:    kevans
Differential Revision:  https://reviews.freebsd.org/D56293
DeltaFile
+6-3usr.bin/stat/tests/readlink_test.sh
+6-31 files

LLVM/project 66eae42lldb/source/Expression DWARFExpression.cpp, lldb/source/Plugins/SymbolFile/DWARF SymbolFileWasm.cpp DWARFUnit.cpp

[lldb] Use llvm::DWARFExpression::iterator in DWARFExpression::Evaluate (#190556)

Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
DeltaFile
+115-88lldb/source/Expression/DWARFExpression.cpp
+6-6lldb/source/Plugins/SymbolFile/DWARF/SymbolFileWasm.cpp
+4-5lldb/unittests/Expression/DWARFExpressionTest.cpp
+2-1lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
+2-1lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
+2-1lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
+131-1026 files not shown
+139-10612 files

LLVM/project 197051bllvm/lib/Target/AMDGPU SIISelLowering.cpp

Review comments:
use input wave instruction for checks
DeltaFile
+7-7llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+7-71 files

LLVM/project ecc0ac4llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

[AMDGPU] DPP wave reduction for long types - 3

Supported Ops: `and`, `or`, `xor`
DeltaFile
+984-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+12-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,916-3494 files

LLVM/project 8d8cf45llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] DPP wave reduction for long types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,113-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,079-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+72-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,264-3083 files

LLVM/project 0be0a5allvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmin.ll llvm.amdgcn.reduce.fmax.ll

[AMDGPU] DPP wave reduction for double types - 1

Supported Ops: `fmin` and `fmax`
DeltaFile
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+27-13llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,251-4813 files

LLVM/project b9153b0llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fsub.ll llvm.amdgcn.reduce.fadd.ll

[AMDGPU] DPP wave reduction for double types - 2

Supported Ops: `fadd` and `fsub`
DeltaFile
+1,030-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+1,008-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+12-10llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,050-2703 files

LLVM/project 4d869e2llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.max.ll llvm.amdgcn.reduce.min.ll

[AMDGPU] DPP wave reduction for long types - 1

Supported Ops: `min`, `max`, `umin`, `umax`
DeltaFile
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+185-42llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4,441-4745 files

LLVM/project e921c26llvm/lib/Target/AMDGPU SIISelLowering.cpp

Remove `MachineIRBuilder` uses
DeltaFile
+5-9llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5-91 files

FreeBSD/ports ec26aa9sysutils/podman Makefile distinfo

sysutils/podman: Fix panic when using network=host

If using host-based networking, instead of default VNET, some podman commands
including inspect could fail:

podman run -d --network=host ghcr.io/freebsd/freebsd-notoolchain:15.0 /bin/sh
podman inspect --latest

See https://github.com/containers/podman/issues/28289 for details.

While here, appease portclippy & portfmt

Reviewed by:    dfr
Obtained from:  dfr
Sponsored by:   SkunkWerks, GmbH
DeltaFile
+6-5sysutils/podman/Makefile
+3-1sysutils/podman/distinfo
+9-62 files

LLVM/project b384622lld/COFF SymbolTable.cpp, lld/test/COFF export-all-conflict.test

[LLD] [COFF] Explicitly prefer def files and export directives over /export-all-symbols (#190749)

If a def file is specified (or explicit export directives), they should
be preferred over exports from /export-all-symbols. There is no need to
warn about conflicts in these cases, just make a clear preference and
ignore the export with lower preference.
DeltaFile
+35-1lld/COFF/SymbolTable.cpp
+9-3lld/test/COFF/export-all-conflict.test
+44-42 files

LLVM/project bc057a3llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-int-rem.ll sve-fixed-length-int-div.ll

[LLVM][CodeGen][AArch64] Improve generated code for SVE VLS truncates. (#190778)

When SVE VLS is enabled we request custom lowering for all ISD::TRUNCATE
operations involving legal types. However, we only custom lower all of
them when NEON is not available and so there are variants that do not
require SVE and can be done via NEON but we are instead falling back to
default expansion, which is this case means scalarisation. This patch
updates custom lowering to mark the variants that have isel patterns
available.
DeltaFile
+26-158llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
+24-156llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
+4-18llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
+4-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+58-3324 files

LLVM/project 7ca5698lld/COFF InputFiles.cpp, lld/test/COFF weak-preference.test gnu-weak.test

[LLD] [COFF] Make weak aliases to implementations take priority over null pointers (#190491)

Normally, one uses weak aliases in one out of two ways.

Either one uses weak definitions to let a weak definition work as
fallback if a strong definition isn't available (which works with
link.exe as well), or as a sort of selectany COMDAT, to let multiple
weak definitions coexist, letting the linker pick any of them. (This
isn't supported by MS link.exe, but requires the LLD extension option
-lld-allow-duplicate-weak, normally implied by the mingw mode.)

Or, one uses weak references, to let a referencing translation unit
check at runtime, whether a symbol was found (at link time) or not,
optionally using the symbol.

In the latter case, the referencing object file provides a fallback
value for the weak symbol, as an absolute null symbol.

Previously, if we had multiple weak externals for the same symbol, we'd

    [16 lines not shown]
DeltaFile
+46-0lld/test/COFF/weak-preference.test
+11-3lld/COFF/InputFiles.cpp
+3-0lld/test/COFF/gnu-weak.test
+60-33 files

LLVM/project ac9c8d1lldb/source/Expression DWARFExpression.cpp

[lldb] Replace C-style casts with static_cast in DWARFExpression.cpp (NFC) (#190949)

Suggested in #190556.
DeltaFile
+17-14lldb/source/Expression/DWARFExpression.cpp
+17-141 files

LLVM/project ddb9edellvm/lib/Transforms/Instrumentation NumericalStabilitySanitizer.cpp, llvm/test/Instrumentation/NumericalStabilitySanitizer non_float_store.ll

[LLVM][NumericalStabilitySanitizer] Extend shadow value tracking to support vector ConstantInts. (#190794)
DeltaFile
+5-21llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp
+14-0llvm/test/Instrumentation/NumericalStabilitySanitizer/non_float_store.ll
+19-212 files