Reland "[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors" (#221058)
This relands #217055
The original commit revealed a latent issue in eliminateFrameIndex in
SIRegisterInfo where SCC can be clobbered before reading it on
gfx900/gfx90a. This change itself has no known issues.
[AMDGPU] Use the scavenger to test whether SCC is live after MI
The register scavenger is stepped backwards to the liveness state
immediately after MI, so RS->isRegUsed(SCC) already answers "is SCC live
after MI" directly. Replace the hand-rolled test with that query.
[AMDGPU] Update based on review feedback
Replace the lambda with the check inlined at both sites, and report a fatal
error when neither a free SGPR nor FrameReg is available, rather than
silently falling back to the spilling scavenge.
[AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering
When SCC is live into a scalar frame index user, the scaling path avoids
SALU ops that write SCC by computing the address in a VGPR and reading it
back with V_READFIRSTLANE_B32. If the destination of that readfirstlane is
scavenged with spilling allowed, an AMDGPU SGPR spill writes inactive
lanes, so it flips EXEC with S_NOT_B64 and clobbers SCC. Instead, scavenge
that register with AllowSpill=false.
[NFC][AMDGPU] Add tests for SCC live into a frame index user
Pre-commit tests for the case where SCC is live into a frame index user and
no SGPR is free to hold the V_READFIRSTLANE_B32 result. Scavenging one
emergency-spills an SGPR, and an SGPR spill flips EXEC with S_NOT_B64, so the
EXEC flips land between the S_CMP_EQ_U32 that defines SCC and the read of SCC
that follows, clobbering it in between.
[AMDGPU] Unify liveness guard to prevent SCC clobber in frame index lowering in scaling path (#223789)
eliminateFrameIndex has two lowering strategies, but only one has the
proper handling for checking SCC-liveness to prevent clobbering. Unify
them with a helper function to ensure both paths handle the same
Add kernel calling convention and IR syntax
Define PISA_KERNEL as calling convention 128 and classify kernels as
non-callable. Add parsing and printing support for pisa_kernel.
Test assembler round trips, the bitcode mapping from cc128, and rejection
of calls using the kernel calling convention.
[llvm][test] Small fixes around CGTestPlugin (NFC) (#225362)
We use `LLVM_ENABLE_PLUGINS` as condition to run the unit-tests in
CGPluginTest, but we used to built the required plugin under `NOT WIN32
AND NOT CYGWIN`. These only happened to be equivalent. This patch guards
the entire folder under `LLVM_ENABLE_PLUGINS`. It also moves the related
LIT test to Feature/codegen-plugin-legacy.ll and adds REQUIRES plugin.
[VectorCombine] foldShuffleOfIntrinsics - don't use I variable name for Index iteration. NFC. (#225394)
Shadows the Instruction &I argument.
Noticed in #182768
Fix recursive DI variant part (#225373)
`mlir::translateModuleToLLVMIR` could leave recursive `DICompositeType`
metadata unresolved when the composite used `DW_TAG_variant_part`.
`DW_TAG_variant_part` was not emitted as a distinct `DICompositeType`,
unlike other recursive composite type tags. This change adds it to the
distinct path and adds a regression test covering the recursive
variant-part case.
Testing:
* `mlir/test/Target/LLVMIR/llvmir-debug.mlir`
* `ninja -C build check-mlir`
Fixes: #225151
Co-authored-by: Purnima Shrivastava <purnimashrivastava05@.com>
hwpmc: fix leak of IBS per-CPU array on unload
pmc_ibs_initialize() allocates the ibs_pcpu[] pointer array, and
pmc_ibs_finalize() exists to free it, but pmc_ibs_finalize() is
never called. Every hwpmc unload on a CPU with IBS therefore leaks
one pmc_cpu_max()-sized pointer array.
Call pmc_ibs_finalize() from pmc_amd_finalize(), alongside the RAPL,
TSC and perf classes. IBS is only initialized on CPUs that support
it, so make pmc_ibs_finalize() return early when ibs_pcpu is NULL,
making it safe to call when the class was skipped at initialize
time, as pmc_rapl_finalize() already is.
Tested on an AMD Ryzen 5 5600X (Zen 3, 12 threads) with INVARIANTS.
Before the change, each kldload/kldunload cycle leaked one 96-byte
M_PMC allocation, and DTrace showed the ibs_pcpu[] allocation from
pmc_ibs_initialize() as the only one never freed. After the change,
50 load/unload cycles leave M_PMC InUse and MemUse unchanged, and
every allocation made at load is freed at unload.
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tarfs_test: split large file test into independent cases
This avoids globally set timeouts for the group of
tarfs_large tests on slower emulated architectures.
While here, lower each testcase's timeout to reflect
the reduction of work. On QEMU aarch64, the largest case
runs in ~500s on a modern desktop, so double that for a
conservative estimate.
Discussed with: des
MFC after: 3 days
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D59033
[offload] add context to olMemAlloc* (#224930)
This is the last part of the context refactor. This patch:
- Adds context param to all memory allocation functions.
- Routes ptr info through the plugins instead of a global map.
- Removes allocation tracking from liboffload.
- olGetMemInfo(OL_MEM_INFO_DEVICE) now returns INVALID_ARGUMENT for host
allocations, which have no per-device affinity.
Re-land of #222677 + #224622, which were reverted together in #224703.
Assisted-by: Claude Opus 4.7
[clang-tidy] Fix infinite loop in misc-multiple-inheritance (#220223)
This PR contains the fix for the infinite loop in
`misc-multiple-inheritance`. The checker was getting stuck in an
infinite cycle when it encountered circular inheritance. I fixed this by
adding a visited map (`InterfaceMap.try_emplace(Node, false)`) to break
the cycle during the DFS traversal.
Part of #213948.
jh7110_temp: CPU temperature sensor for JH7110
This patch adds a driver for the CPU temperature sensor on the jh7110
SoC.
The calibration numbers come from the OpenBSD driver but are reworked to
produce a result in K rather than C.
The temperature is exposed as a sysctl, dev.jh7110_temp.0.temperature
but I have also exposed it as dev.cpu.0.temperature because that's where
you find it on a RaspberryPi and amdtemp(4), so it's a lot more obvious.
(mhorne: Added 'starfive,jh7100-temp' compatible.)
Reviewed by: mhorne, bnovkov
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D59478
Add tier field to sharing.s3 entries
Information about the current S3 share's tier was accidentally
omitted during intial round of S3 development. This commit adds
the standard tier info.
[lldb-dap][NFC] Simplify using var_ref_t directly. (#225187)
Make var_ref_t printable, update functions that requires var_ref_t to
use var_ref_t instead of integers.
