FreeNAS/freenas 0d89be4src/middlewared/middlewared/utils plugins.py limits.py

More mypy fixes in utils
DeltaFile
+17-15src/middlewared/middlewared/utils/plugins.py
+6-4src/middlewared/middlewared/utils/limits.py
+5-5src/middlewared/middlewared/utils/kbdmap_choices.py
+4-4src/middlewared/middlewared/utils/user_api_key.py
+5-2src/middlewared/middlewared/utils/mount.py
+3-3src/middlewared/middlewared/utils/profile.py
+40-334 files not shown
+49-4010 files

LLVM/project 99a74aallvm/lib/CodeGen/MIRParser MIRParser.cpp

CodeGen: Change error messages to follow phrasing guidance

Avoid contractions and starting with a capital. These seem to be
missing tests.
DeltaFile
+2-2llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+2-21 files

LLVM/project 6d7ec4bllvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp DAGCombiner.cpp, llvm/test/CodeGen/X86 known-pow2.ll

[DAG] Improved ISD::SHL handling in isKnownToBeAPowerOfTwo (#181882)

Fixes  #181650
DeltaFile
+51-0llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+3-7llvm/test/CodeGen/X86/known-pow2.ll
+4-4llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+2-3llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+60-144 files

LLVM/project 0f415a3llvm/lib/Target/AMDGPU SIRegisterInfo.cpp

Use `findCommonRegClass` API.
DeltaFile
+3-7llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+3-71 files

LLVM/project 850b045lldb/source/Plugins/Process/FreeBSD-Kernel-Core ProcessFreeBSDKernelCore.cpp CMakeLists.txt, llvm/docs ReleaseNotes.md

Revert "[lldb][Process/FreeBSDKernelCore] Implement DoWriteMemory()" (#183485)

Reverts llvm/llvm-project#183237

This was landed without addressing review comments.
DeltaFile
+2-69lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
+0-12lldb/source/Plugins/Process/FreeBSD-Kernel-Core/CMakeLists.txt
+0-8lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCoreProperties.td
+0-6lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.h
+0-2llvm/docs/ReleaseNotes.md
+2-975 files

LLVM/project 7a2bb5fllvm/lib/CodeGen ComplexDeinterleavingPass.cpp, llvm/test/CodeGen/AArch64 complex-deinterleaving-opt-crash-178671.ll

[AArch64] ComplexDeinterleavingPass: instruction does not dominate all uses! (#182494)

https://github.com/llvm/llvm-project/issues/178671 highlights IR in
which ComplexDeinterleavingPass places a deinterleave2 after it's use
due to the real and imaginary parts ending up in different basic blocks.
This change modifies ComplexDeinterleavingPass to to insert the 
deinterleave into the exit block.
DeltaFile
+86-0llvm/test/CodeGen/AArch64/complex-deinterleaving-opt-crash-178671.ll
+4-2llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
+90-22 files

NetBSD/pkgsrc-wip c59c9fbopentofu110 Makefile

opentofu*: Avoid copypasting PKGNAME

Just add the suffix based on DISTNAME via :S// so we spell the full
version number only once.
DeltaFile
+1-1opentofu110/Makefile
+1-11 files

NetBSD/pkgsrc-wip 7d759e6terraform013 Makefile, terraform014 Makefile

terraform*: Avoid copypasting PKGNAME

Just add the suffix based on DISTNAME via :S// so we spell the full
version number only once.
DeltaFile
+1-1terraform013/Makefile
+1-1terraform014/Makefile
+1-1terraform015/Makefile
+1-1terraform11/Makefile
+1-1terraform13/Makefile
+1-1terraform15/Makefile
+6-61 files not shown
+7-77 files

NetBSD/pkgsrc-wip f2d34aeterraform012 Makefile

terraform012: Remove version.mk inclusion

It is no longer available and needed.
DeltaFile
+0-2terraform012/Makefile
+0-21 files

LLVM/project bc653c4libclc/opencl/lib/clspv SOURCES

[libclc] add subnormals back to clspv (#183469)

DeltaFile
+1-0libclc/opencl/lib/clspv/SOURCES
+1-01 files

NetBSD/pkgsrc-wip 5fb9390opentofu110 Makefile, terraform version.mk

terraform: Remove version.mk

It was used only in the various terraform/opentofu (non-provider)
packages and only adds an useless layer of indirection.

NFCI.
DeltaFile
+0-13terraform/version.mk
+2-4terraform13/Makefile
+2-4opentofu110/Makefile
+2-4terraform15/Makefile
+2-4terraform013/Makefile
+2-4terraform014/Makefile
+10-334 files not shown
+16-4510 files

LLVM/project 0d8b336lldb/include/lldb/Utility AnsiTerminal.h, lldb/unittests/Utility AnsiTerminalTest.cpp

[lldb] Fix partial Unicode handling in TrimAndPad (#183299)

This fixes an issue I found while writing a variant of TrimAndPad for
word wrapping purposes.

TrimAndPad relies on llvm::sys::locale::ColumnWidth returning an error
value, when there is a partial uft8 character. This error code is
ErrorInvalidUTF8, which is -2.

The idea was that when you cast that into a size_t, it was always going
to be larger than our target visible width.

The check for this was:
result_visibile_length + column_width <= visible_length

Where result_visible_length and column_width are size_ts.

And the idea is correct, as long as result_visible_width is not large
enough to cause the result to wrap to be lower than visible_length.

    [6 lines not shown]
DeltaFile
+10-6lldb/include/lldb/Utility/AnsiTerminal.h
+12-0lldb/unittests/Utility/AnsiTerminalTest.cpp
+22-62 files

LLVM/project ede6ef4clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CIR/CodeGenBuiltins/AArch64 acle_sve_dup.c

[CIR][AArch64] Add lowering + tests for predicated SVE svdup_lane builtins (#183276)

This PR adds CIR lowering + tests for SVE `svdup_lane` builtins on
AArch64. The corresponding ACLE intrinsics are documented at:
https://developer.arm.com/architectures/instruction-sets/intrinsics
DeltaFile
+157-0clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c
+20-3clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+177-32 files

LLVM/project 72215a4llvm/lib/CodeGen/AsmPrinter DwarfUnit.h

[DwarfUnit] Fix comment mistake in shouldPlaceInUnitDIE() (#183481)

Subprogram definition DIEs (for which `SP->getDeclaration() != nullptr`)
are placed at the CU scope, while subprogram declaration DIEs are placed
in their corresponding (local) scopes.
DeltaFile
+1-1llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
+1-11 files

LLVM/project 7aa74c9mlir/lib/Dialect/Vector/Transforms LowerVectorMultiReduction.cpp

[mlir][vector] Refactor multi-reduction patterns (NFC) (#183048)

Refactor the following patterns to inherit from
`MaskableOpRewritePattern`:
  * `TwoDimMultiReductionToReduction`
  * `TwoDimMultiReductionToElementWise`

This improves code reuse, enables small simplifications, and unifies the
structure of the patterns. Add high-level comments to clarify the
overall lowering strategy.

Prepares for future refactoring (e.g. #182301) and helps maintain a
uniform implementation.
DeltaFile
+85-67mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp
+85-671 files

FreeBSD/ports 85333a2net-im/py-matrix-synapse pkg-descr Makefile

net-im/py-matrix-synapse: Update WWW and description

PR:             274257
Approved by:    Sascha Biberhofer <ports at skyforge.at> (maintainer,
timeout > 2 weeks)
Approved by:    db@, yuri@ (Mentors, implicit)
DeltaFile
+2-2net-im/py-matrix-synapse/pkg-descr
+1-1net-im/py-matrix-synapse/Makefile
+3-32 files

LLVM/project 2d1ab7cllvm/include/llvm/Object ELF.h

fixup! [Object][ELF] Fix section header zero check
DeltaFile
+2-1llvm/include/llvm/Object/ELF.h
+2-11 files

LLVM/project 5c065eallvm/include/llvm/ADT GenericUniformityImpl.h, llvm/lib/Analysis UniformityAnalysis.cpp

use CallbackVH for deletion/RAUW
DeltaFile
+149-0llvm/unittests/Target/AMDGPU/UniformityAnalysisCallbackVHTest.cpp
+45-0llvm/lib/Analysis/UniformityAnalysis.cpp
+12-1llvm/include/llvm/ADT/GenericUniformityImpl.h
+1-0llvm/unittests/Target/AMDGPU/CMakeLists.txt
+207-14 files

LLVM/project 523cb52llvm/lib/Target/AMDGPU AMDGPU.td, llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUInstPrinter.cpp

AMDGPU: Add FlatSignedOffset feature and use it for flat offset printing
DeltaFile
+6-1llvm/lib/Target/AMDGPU/AMDGPU.td
+1-1llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+7-22 files

FreeBSD/ports 2ea0d37editors/zed distinfo Makefile.crates, editors/zed/files patch-Cargo.lock patch-crates_gpui_src_platform_blade_blade__renderer.rs

editors/zed: Update to 0.225.9

Changelog: https://github.com/zed-industries/zed/releases/tag/v0.225.9

Reported by:    GitHub (watch releases)
DeltaFile
+77-59editors/zed/distinfo
+37-28editors/zed/Makefile.crates
+8-8editors/zed/files/patch-Cargo.lock
+0-11editors/zed/files/patch-crates_gpui_src_platform_blade_blade__renderer.rs
+11-0editors/zed/files/patch-crates_audio_src_audio.rs
+4-4editors/zed/files/patch-crates_project_src_agent__server__store.rs
+137-1106 files not shown
+150-12312 files

OpenBSD/ports YFhLnOdx11/freerdp Makefile distinfo

   update to freerdp-2.11.8

   remove PORTROACH marker, this is the last 2.x release (updating is
   blocked, 3.x needs a more complete posix timers implementation)
VersionDeltaFile
1.78+36-36x11/freerdp/Makefile
1.31+2-2x11/freerdp/distinfo
+38-382 files

OPNSense/tools db8a760config/26.1 make.conf

www/caddy-custom: Remove ntml-transport plugin (#502)

DeltaFile
+1-2config/26.1/make.conf
+1-21 files

FreeBSD/ports ed534f0math/R-cran-pls distinfo Makefile

math/R-cran-pls: Update to 2.9-0

Reported by:    portscout
DeltaFile
+3-3math/R-cran-pls/distinfo
+1-1math/R-cran-pls/Makefile
+4-42 files

OPNSense/tools b2d6c98config/26.1 make.conf

www/caddy-custom: Remove ntml-transport plugin
DeltaFile
+1-2config/26.1/make.conf
+1-21 files

NetBSD/pkgsrc-wip 89007f5postgresql-pgvector TODO

postgresql-pgvector: Add reference to CVE-2026-3172
DeltaFile
+2-0postgresql-pgvector/TODO
+2-01 files

NetBSD/pkgsrc-wip 1579586opensips TODO

opensips: Add reference to CVE-2026-25554
DeltaFile
+1-1opensips/TODO
+1-11 files

LLVM/project 3c566a6llvm/lib/Transforms/Vectorize VPlanConstruction.cpp VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize iv-select-cmp-fold-tail.ll

[LV] Fix miscompile with conditional scalar assignment + tail folding (#182492)

Previously, we could miscompile when vectorizing conditional scalar
assignments with forced tail folding, as the backedge select could be
based on the header mask, not the assignment conditional.

This resulted in a number of failures in the LLVM test suite when
building with `-O3 -march=armv8-a+sve -mllvm
-prefer-predicate-over-epilogue=predicate-dont-vectorize`.

The patch reworks `handleFindLastReductions()` to correctly handle tail
folding.
DeltaFile
+176-2llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
+142-0llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
+71-13llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
+26-8llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+15-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-3llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+441-336 files

OPNSense/plugins d46585fwww/caddy/src/opnsense/mvc/app/controllers/OPNsense/Caddy/Api ServiceController.php, www/caddy/src/opnsense/mvc/app/models/OPNsense/Caddy Caddy.xml

www/caddy: Remove NTML support and cleanup service control (#5258)

* www/caddy: Remove NTML plugin as it causes issues with service control that can not worked around with anymore.

The NTML plugin and caddy core diverged too much and its considered unmaintained. While there clean up all service control workarounds that were implemented.
Since removing the service control (caddy_control.py) script would make it hard to somehow funnel caddyfile validation in, this has been removed too.
Our input is heavily validated so the Caddyfile will be valid in almost all cases, and in cases its not the log will show the error.
DeltaFile
+0-135www/caddy/src/opnsense/scripts/OPNsense/Caddy/caddy_control.py
+3-44www/caddy/src/opnsense/mvc/app/views/OPNsense/Caddy/reverse_proxy.volt
+3-44www/caddy/src/opnsense/mvc/app/views/OPNsense/Caddy/general.volt
+1-36www/caddy/src/opnsense/mvc/app/views/OPNsense/Caddy/diagnostics.volt
+1-24www/caddy/src/opnsense/mvc/app/controllers/OPNsense/Caddy/Api/ServiceController.php
+1-17www/caddy/src/opnsense/mvc/app/models/OPNsense/Caddy/Caddy.xml
+9-3003 files not shown
+15-3289 files

OPNSense/core 52e8010src/opnsense/mvc/app/controllers/OPNsense/Core/forms wizard_deployment_type.xml, src/opnsense/mvc/app/controllers/OPNsense/Dnsmasq/forms general.xml

dnsmask: use "Dnsmasq" consequently

(cherry picked from commit eb02f720dfb47f7a137de705422fab0aa8a90098)
DeltaFile
+2-2src/opnsense/mvc/app/controllers/OPNsense/Core/forms/wizard_deployment_type.xml
+1-1src/opnsense/mvc/app/controllers/OPNsense/Dnsmasq/forms/general.xml
+3-32 files

OPNSense/core eb02f72src/opnsense/mvc/app/controllers/OPNsense/Core/forms wizard_deployment_type.xml, src/opnsense/mvc/app/controllers/OPNsense/Dnsmasq/forms general.xml

dnsmask: use "Dnsmasq" consequently
DeltaFile
+2-2src/opnsense/mvc/app/controllers/OPNsense/Core/forms/wizard_deployment_type.xml
+1-1src/opnsense/mvc/app/controllers/OPNsense/Dnsmasq/forms/general.xml
+3-32 files