Thread Safety Analysis: Fix crash with wide string literals (#180349)
The SExprBuilder was previously using StringLiteral::getString() to
extract the value of string literals. This method asserts that the
string is a narrow string (char width == 1):
```
clang/include/clang/AST/Expr.h:1872: StringRef clang::StringLiteral::getString() const: Assertion `(isUnevaluated() || getCharByteWidth() == 1) && "This function is used in places that assume strings use char"' failed.
[...]
#9 0x0000556247fcfe3e clang::threadSafety::SExprBuilder::translate(clang::Stmt const*, clang::threadSafety::SExprBuilder::CallingContext*)
[...]
```
This fails when using wide string literals as in the new test case
added.
Switch to using StringLiteral::getBytes(), which provides the raw byte
representation of the string. This is sufficient to compare expressions
for identity.
Fixes: https://github.com/llvm/llvm-project/pull/148551
[hwasan][Fuchsia] Use GetCurrentThread (#180602)
The hook passed to __sanitizer_thread_exit_hook will be null if we ever
call thrd/pthread_exit from the initial thread since
__sanitizer_before_thread_create_hook is never called on the initial
thread. Rather than using the hook, we can use the normal hwasan
machinery for getting the current pointer rather than the hook.
Merge tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq chip driver updates from Thomas Gleixner:
- Add support for the Renesas RZ/V2N SoC
- Add a new driver for the Renesas RZ/[TN]2H SoCs
- Preserve the register state of the RISCV APLIC interrupt controller
accross suspend/resume
- Reinitialize the RISCV IMSIC registers after suspend/resume
- Make the various Loongson interrupt chip drivers 32/64-bit aware
- Handle the number of hardware interrupts in the SIFIVE PLIC driver
correctly
The hardware interrupt 0 is reserved which resulted in inconsistent
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[AMDGPU] Fix LDS address correction in promoteConstantOffsetToImm for async stores (#180220)
`updateAsyncLDSAddress`, introduces by
https://github.com/llvm/llvm-project/pull/176816, previously only
handled async loads , where the LDS address is in the `vdst` operand.
Therefore Async stores produced a nullptr dereference since the LDS
address is in `vdata` for those instructions.
---------
Co-authored-by: Jay Foad <jay.foad at gmail.com>
[DAGCombiner] Fix crash in reassociationCanBreakAddressingModePattern for multi-memop nodes (#180268)
Two code paths in `reassociationCanBreakAddressingModePattern` were
missing a `hasUniqueMemOperand()` guard before calling
`getAddressSpace()`. Note that on `L1214` we already have the same guard
in place.
`getAddressSpace()` chains through `getPointerInfo()` to
`getMemOperand()`, which asserts that the node has exactly one memory
operand.
brcmfmac: deal with bus attachments to the module Makefile
As with LinuxKPI-based wireless drivers, e.g., rtw88, PCI depends
on PCI being compiled into the kernel, SDIO will depend on
MMCCAM in the kernel once supported, and USB can always be
loaded.
Sponsored by: The FreeBSD Foundation
MFC after: 3 days
Merge tag 'irq-core-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq core updates from Thomas Gleixner:
"Updates for the interrupt core subsystem:
- Remove the interrupt timing infrastructure
This was added seven years ago to be used for power management
purposes, but that integration never happened.
- Clean up the remaining setup_percpu_irq() users
The memory allocator is available when interrupts can be requested
so there is not need for static irq_action. Move the remaining
users to request_percpu_irq() and delete the historical cruft.
- Warn when interrupt flag inconsistencies are detected in
request*_irq().
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[RISCV] Add basic scalar support for MERGE, MVM, and MVMN from P extension (#180677)
These are 3 variations of the same operation with a different operand
tied to the destination register. We need to pick the one that
minimizes the number of mvs.
To do this we take the approach used by AArch64 to select between
BIT, BIF, and BSL which the same operations. We define a pseudo
with no tied constraint and expand it after register allocation based
on where the destination register ended up. If the destination
register is none of the operands, we'll insert a mv.
I've replaced RISCVISD::MVM with RISCVISD::MERGE and updated the operand
order accordingly. I find the MERGE name easier to read so I've made it
the canonical name.
Ideally we could use commuteInstructionImpl and the
TwoAddressInstructionPass
to select the opcode before register allocation. That only works if
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brcmfmac: make USB parts compile (and not panic right away)
Fix casts and consts and add one extra error check for a NULL pointer.
This will require [a future] linuxkpi_usb.
There are very few dongles I know off:
- the original Raspberry PI USB dongle [1]
- Cisco Linksys AE1200
The reason for making USB compile despite the limited 11n 150/300 Mbit/s
adapters is that it is the simplest way to work on cfg80211 while on the
road, not requiring a full PCIe slot or another SoC for SDIO.
Sponsored by: The FreeBSD Foundation
Hardware donated by: Martin Husemann (martin NetBSD.org) [1]
MFC after: 3 days
brcm80211: add LinuxKPI files and module Makefiles
sys/compat/linuxkpi/common/include/linux/platform_data/brcmfmac.h
is based on
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
e5f0a698b34ed76002dc5cff3804a61c80233a7a ( tag: v6.17 ).
Currently only PCIe is made to compile.
It does load firmware (if needed, e.g., on arm64 with an alignment
issue fixed), and starts to come up.
To make it work there is a cfg80211 layer and netdevice integration
to do, so do not hold your breath just yet.
[RISCV] Remove non-alias tests from rv32zbb-aliases-valid.s and rv64zbb-aliases-valid.s. NFC (#180317)
These are real instructions and are tested in rv32zbb-only-valid.s,
rv64-zbb-valid.s, or rvzbb-valid.s
I think this is some artifact of the refactoring that happened when some
of the Bitmanip extensions/instructions were removed years ago.
