LLVM/project b996b4elibc/src/__support/OSUtil/linux/syscall_wrappers rt_sigprocmask.h, libc/src/signal pthread_sigmask.h

[libc] Implement pthread_sigmask (#198682)

* Extract `rt_sigprocmask` syscall wrapper into the
libc/src/__support/OSUtil/linux/syscall_wrappers/ directory
* Convert all existing users of this syscall, and simplify the logic
where applicable.
* Implement `pthread_sigmask`, which is effectively another POSIX
wrapper around `rt_sigprocmask` syscall similar to `sigprocmask`
DeltaFile
+64-0libc/test/src/signal/pthread_sigmask_test.cpp
+36-0libc/src/__support/OSUtil/linux/syscall_wrappers/rt_sigprocmask.h
+33-0libc/src/signal/linux/pthread_sigmask.cpp
+27-0libc/src/signal/pthread_sigmask.h
+10-12libc/src/signal/linux/signal_utils.h
+15-2libc/src/signal/linux/CMakeLists.txt
+185-1411 files not shown
+248-3617 files

LLVM/project 57d2c4clibc/include/sys prctl.yaml, libc/src/sys/prctl prctl.h

[libc] Update prctl() declaration to use variadic arguments. (#198654)

prctl declaration should typically use variadic arguments (e.g. see
https://man7.org/linux/man-pages/man2/prctl.2.html), as the types /
quantity of subsequent arguments depends on the `option`. We can't
depend on all `<prctl.h>` users to explicitly cast arguments to
`unsigned long` and passing all 5 of them every time.

* Don't add any option-specific logic, and just consume `arg2`-`arg5`
from variadic arguments and pass them to syscall implementation as-is,
assuming that they won't be used by the kernel if they are not needed,
and consuming these arguments won't lead to crashes.
* Updated the test to use `prctl` variants with less than 5 explicit
arguments (for PR_SET_NAME and PR_GET_NAME).
DeltaFile
+6-12libc/test/src/sys/prctl/linux/prctl_test.cpp
+11-3libc/src/sys/prctl/linux/prctl.cpp
+1-4libc/include/sys/prctl.yaml
+1-2libc/src/sys/prctl/prctl.h
+19-214 files

NetBSD/src raK90zJshare/man/man4 axen.4

   axen.4: note examples of presently unsupported features

   (These could go under a bugs section, but it perhaps makes more sense
   to keep all this information together.)
VersionDeltaFile
1.12+3-1share/man/man4/axen.4
+3-11 files

FreeBSD/ports 94fbcd0net-mgmt/librenms distinfo Makefile, net-mgmt/librenms/files pkg-message.in

net-mgmt/librenms: Update to 26.5.1

re: https://github.com/librenms/librenms/releases/tag/26.5.1

While here, add an additional approach to running 'lnms migrate'
to pkg-message
DeltaFile
+5-5net-mgmt/librenms/distinfo
+6-0net-mgmt/librenms/files/pkg-message.in
+2-3net-mgmt/librenms/Makefile
+13-83 files

LLVM/project 1a41236llvm/include/llvm/IR Use.h

format

Created using spr 1.3.6-beta.1
DeltaFile
+4-4llvm/include/llvm/IR/Use.h
+4-41 files

LLVM/project 62e427fclang/lib/CIR/CodeGen CIRGenExpr.cpp CIRGenFunction.cpp, clang/test/CIR/CodeGen amdgpu-stack-alloca-array-decay.cpp

[CIR][CIRGen] Cast stack allocas to the language-visible address space (#196868)

This patch aims to improve parity with OG codegen on targets with
non-flat alloca address space. I observed this after getting some
crashes while compiling PolybenchGpu for HIP (amdgpu). This work had
previously been merged in the incubator, most notably:
https://github.com/llvm/clangir/pull/2090,
https://github.com/llvm/clangir/pull/2088.

CIR currently returns the raw `cir.alloca` address from temporary/local
alloca creation. On AMDGPU, stack allocas live in private addrspace(5),
but ordinary C/C++/HIP auto variables are still used through the
language-visible generic/flat address space.

OG CodeGen handles this by creating the alloca in the target stack
address space and immediately casting it to the language-visible address
space when those differ. For example:

```llvm

    [11 lines not shown]
DeltaFile
+45-20clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+42-0clang/test/CIR/CodeGen/amdgpu-stack-alloca-array-decay.cpp
+9-9clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
+7-6clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+11-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+8-1clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
+122-366 files not shown
+139-4712 files

LLVM/project 5610e5cllvm/include/llvm/IR Use.h User.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+15-0llvm/include/llvm/IR/Use.h
+0-15llvm/include/llvm/IR/User.h
+15-152 files

LLVM/project cf7e148llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 non-schedulable-user-different-bb.ll non-schedulable-node-with-non-schedulable-parent.ll

[SLP]Bail out when copyable has cross-block reused non-schedulable user

When a copyable scalar in the bundle being scheduled has a same-block,
non-PHI, non-schedulable user with multiple uses, and at least one of
those uses is a non-PHI use in another block, the user's dependency
tracking across multiple bundles can be inconsistent.
Cancel scheduling of such copyable bundles instead.

Fixes #198364.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/198915
DeltaFile
+73-0llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-user-different-bb.ll
+10-13llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-node-with-non-schedulable-parent.ll
+18-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+101-133 files

FreeBSD/ports 530483dx11/xwayland-satellite Makefile

x11/xwayland-satellite: install man page after 06d0f75724e2

Obtained from:  OpenBSD Ports

(cherry picked from commit c053663b583bd4ed5d1e92da7327ae3176b47742)
DeltaFile
+7-2x11/xwayland-satellite/Makefile
+7-21 files

FreeBSD/ports 33d1877games/veloren-weekly distinfo Makefile

games/veloren-weekly: update to s20260520

Changes:        https://gitlab.com/veloren/veloren/-/compare/50376dc2e4...c6791e6e3c
(cherry picked from commit a5d5f4eb64b7cd0b05561e29eb2c8d9e3140aa4c)
DeltaFile
+3-3games/veloren-weekly/distinfo
+2-2games/veloren-weekly/Makefile
+5-52 files

LLVM/project 28112c8llvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/CodeGen/ARM atomic-load-store.ll

[AtomicExpand] Add bitcasts when expanding store atomic vector

AtomicExpand fails for aligned \`store atomic <n x T>\` because it
does not find a compatible library call. This change adds appropriate
ptrtoint + bitcast so that the call can be lowered, mirroring the
load-side handling from #148900.
DeltaFile
+99-6llvm/test/CodeGen/X86/atomic-load-store.ll
+98-0llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+49-0llvm/test/CodeGen/ARM/atomic-load-store.ll
+4-2llvm/lib/CodeGen/AtomicExpandPass.cpp
+250-84 files

LLVM/project 0d958f9llvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/Target/X86 X86InstrFragmentsSIMD.td X86InstrAVX512.td

[X86] Cast atomic vectors in IR to support floats

Extend the X86 \`alignedstore\` PatFrag to also match \`atomic_store\`
with vector-size alignment, so existing MOVAPS/MOVAPD/MOVDQA-family
aligned-store patterns cover 128-bit aligned vector atomic stores on
SSE/AVX/AVX-512 without per-type duplicates. \`<4 x float>\`,
\`<2 x double>\`, \`<2 x i64>\`, \`<4 x i32>\`, \`<8 x half>\`, \`<8 x bfloat>\`
all codegen to a single \`movaps\`/\`movapd\` on AVX+ via this.

Adds v8f16/v8bf16 bitconvert variants to the widen-path
\`atomic_store_32\` / \`atomic_store_64\` patterns so \`<2 x half>\`,
\`<2 x bfloat>\`, \`<4 x half>\`, \`<4 x bfloat>\` atomic stores reaching
the PR4 widen path also collapse to a single instruction on AVX+
targets.

Vectors whose \`getTypeAction\` is split rather than widen still rely
on PR6's \`SplitVecOp_ATOMIC_STORE\` — that path bitcasts the vector
to a scalar integer and issues an integer \`atomic_store_N\`, picked
up by the pre-existing scalar atomic-store patterns. The two

    [4 lines not shown]
DeltaFile
+86-0llvm/test/CodeGen/X86/atomic-load-store.ll
+5-4llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+3-2llvm/lib/Target/X86/X86InstrAVX512.td
+1-1llvm/include/llvm/Target/TargetSelectionDAG.td
+95-74 files

LLVM/project 98275c5llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Split vector types for atomic store

Vector types that aren't widened are split so that a single ATOMIC_STORE
is issued for the entire vector at once. This enables SelectionDAG to
translate vectors with type bfloat,half.
DeltaFile
+440-0llvm/test/CodeGen/X86/atomic-load-store.ll
+20-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+461-03 files

LLVM/project 7fb4fcfllvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/Target/X86 X86InstrSSE.td X86InstrAVX512.td

[X86] Remove extra MOV after widening atomic store

This change adds patterns to optimize out an extra MOV present after
widening the atomic store. Covers <2 x i8> (SSE4.1+), <2 x i16>,
<4 x i8>, <2 x i32>, <2 x float>, <4 x i16>, <2 x ptr addrspace(270)>.
DeltaFile
+47-64llvm/test/CodeGen/X86/atomic-load-store.ll
+30-24llvm/test/CodeGen/X86/atomic-unordered.ll
+35-0llvm/include/llvm/Target/TargetSelectionDAG.td
+10-10llvm/lib/Target/X86/X86InstrSSE.td
+6-6llvm/lib/Target/X86/X86InstrAVX512.td
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+129-1056 files

LLVM/project 63ef83cllvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Widen <2 x T> vector types for atomic store

Vector types of 2 elements must be widened. This change does this
for vector types of atomic store in SelectionDAG so that it can
translate aligned vectors of >1 size.
DeltaFile
+198-0llvm/test/CodeGen/X86/atomic-load-store.ll
+56-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+255-03 files

LLVM/project bc7894aclang/docs ReleaseNotes.rst

[Clang] [Docs] Remove stray release note (#198913)

The patch that added this release note was reverted (#198341), but then
(#198167) accidentally added it back.
DeltaFile
+0-3clang/docs/ReleaseNotes.rst
+0-31 files

pkgng/pkgng 6f9636flibpkg pkg_jobs_conflicts.c pkg_jobs.c, libpkg/private pkg_jobs.h

fix: another memory leak
DeltaFile
+20-0libpkg/pkg_jobs_conflicts.c
+1-0libpkg/pkg_jobs.c
+1-0libpkg/private/pkg_jobs.h
+22-03 files

FreeBSD/ports 4c160bcemulators/rpcs3 distinfo Makefile

emulators/rpcs3: update to 0.0.40.19389

Changes:        https://github.com/RPCS3/rpcs3/compare/320e8d634a...67464f97df
DeltaFile
+3-3emulators/rpcs3/distinfo
+2-2emulators/rpcs3/Makefile
+5-52 files

FreeBSD/ports a5d5f4egames/veloren-weekly distinfo Makefile

games/veloren-weekly: update to s20260520

Changes:        https://gitlab.com/veloren/veloren/-/compare/50376dc2e4...c6791e6e3c
DeltaFile
+3-3games/veloren-weekly/distinfo
+2-2games/veloren-weekly/Makefile
+5-52 files

FreeBSD/ports 57a95f9graphics/mesa-devel distinfo Makefile

graphics/mesa-devel: update to 26.1.b.1594

Changes:        https://gitlab.freedesktop.org/mesa/mesa/-/compare/f6debb842d7...7eba054c5ba
DeltaFile
+3-3graphics/mesa-devel/distinfo
+2-3graphics/mesa-devel/Makefile
+5-62 files

FreeBSD/ports c1de93bdevel/sdbus-cpp distinfo Makefile

devel/sdbus-cpp: update to 2.3.1

Changes:        https://github.com/Kistler-Group/sdbus-cpp/releases/tag/v2.3.0
Changes:        https://github.com/Kistler-Group/sdbus-cpp/releases/tag/v2.3.1
Reported by:    GitHub (watch releases)
DeltaFile
+3-3devel/sdbus-cpp/distinfo
+1-1devel/sdbus-cpp/Makefile
+1-0devel/sdbus-cpp/pkg-plist
+5-43 files

FreeBSD/ports c053663x11/xwayland-satellite Makefile

x11/xwayland-satellite: install man page after 06d0f75724e2

Obtained from:  OpenBSD Ports
DeltaFile
+7-2x11/xwayland-satellite/Makefile
+7-21 files

FreeBSD/ports 9764285x11-toolkits/wlroots020 distinfo Makefile

x11-toolkits/wlroots020: update to 0.20.1

Changes:        https://gitlab.freedesktop.org/wlroots/wlroots/-/releases/0.20.1
Reported by:    GitLab (notify releases)
DeltaFile
+3-3x11-toolkits/wlroots020/distinfo
+1-2x11-toolkits/wlroots020/Makefile
+4-52 files

FreeBSD/ports 88972ddbenchmarks/clpeak distinfo Makefile, benchmarks/clpeak/files patch-src_vulkan_kernel__latency.cpp patch-src_vk__peak.cpp

benchmarks/clpeak: update to 2.0.8

Changes:        https://github.com/krrishnarraj/clpeak/releases/tag/2.0.7
Changes:        https://github.com/krrishnarraj/clpeak/releases/tag/2.0.8
Reported by:    GitHub (watch releases)
DeltaFile
+15-0benchmarks/clpeak/files/patch-src_vulkan_kernel__latency.cpp
+0-11benchmarks/clpeak/files/patch-src_vk__peak.cpp
+3-3benchmarks/clpeak/distinfo
+1-1benchmarks/clpeak/Makefile
+19-154 files

FreeBSD/ports b9c9717ports-mgmt/pkg-devel distinfo Makefile

ports-mgmt/pkg-devel: update to 2.7.99.2

Changes:
- periodic: daily checksum is now off by default
- extract: prefer mtime from manifest over archive
- db: fix some concurrency issues
- which: always show the matched path
- checksum: new pkg-checksum(8) command to generate and validate checksums
- checksum: use blake2b everywhere we can
- repo: use blake2 instead of sha256
- rwhich: implement file tracking and search for remote repositories
- backup_lib: prevent accumulating old libs and badly match them
- backup_lib: fix backup_library with rootdir
- pkg-which: fix spurious warning message with -p
- progress: don't add new line for file_meta and dir_meta event
- fix: replace system() with execlp() for man page display
- fix: query_select discards valid input on EOF without newline
- fix: harden input validation found by fuzzing
- fix: handle trailing %% in printf format strings

    [10 lines not shown]
DeltaFile
+3-3ports-mgmt/pkg-devel/distinfo
+2-2ports-mgmt/pkg-devel/Makefile
+1-0ports-mgmt/pkg-devel/pkg-plist
+6-53 files

LLVM/project 8a3f021clang/docs ReleaseNotes.rst, clang/include/clang/Sema Scope.h

[Clang] Disallow `break`/`continue` in loop conditions (#198436)

tl;dr: This makes e.g. `while (({ break; 1; })) {}` ill-formed.

GCC used to allow this a long time ago (< GCC 9 I believe), but
eventually removed support for it; we originally allowed this both for
GCC compatibility and because there was actual code in the wild using it
(see Richard’s comment here for more background:
https://github.com/llvm/llvm-project/pull/152606#issuecomment-3166130973).

Note that this _is_ still allowed inside another loop, e.g. this
```c++
for (;;) {
    while (({ break; true; })) {}
}
```
is well-formed; the `break` here will break out of the `for` loop.

Removing support for this gets rid of quite a bit of code and has a few

    [32 lines not shown]
DeltaFile
+114-0clang/test/Sema/break-continue-cond.c
+25-25clang/test/Sema/loop-control.c
+14-32clang/lib/Parse/ParseStmt.cpp
+12-24clang/include/clang/Sema/Scope.h
+0-35clang/lib/Sema/SemaStmt.cpp
+31-0clang/docs/ReleaseNotes.rst
+196-11610 files not shown
+228-21716 files

pkgng/pkgng 7fa6a77.builds freebsd.yml

fix: kyua is now part of base
DeltaFile
+0-1.builds/freebsd.yml
+0-11 files

pkgng/pkgng c9d7564libpkg pkg_repo_meta.c pkg_manifest.c, libpkg/repo/binary update.c

fix: memory leaks
DeltaFile
+3-1libpkg/pkg_repo_meta.c
+1-0libpkg/pkg_manifest.c
+1-0libpkg/repo/binary/update.c
+5-13 files

LLVM/project 671bb1fllvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/CodeGen/ARM atomic-load-store.ll

[AtomicExpand] Add bitcasts when expanding store atomic vector

AtomicExpand fails for aligned \`store atomic <n x T>\` because it
does not find a compatible library call. This change adds appropriate
ptrtoint + bitcast so that the call can be lowered, mirroring the
load-side handling from #148900.
DeltaFile
+99-6llvm/test/CodeGen/X86/atomic-load-store.ll
+98-0llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+49-0llvm/test/CodeGen/ARM/atomic-load-store.ll
+4-2llvm/lib/CodeGen/AtomicExpandPass.cpp
+250-84 files

LLVM/project 1d7267allvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/Target/X86 X86InstrFragmentsSIMD.td X86InstrAVX512.td

[X86] Cast atomic vectors in IR to support floats

Extend the X86 \`alignedstore\` PatFrag to also match \`atomic_store\`
with vector-size alignment, so existing MOVAPS/MOVAPD/MOVDQA-family
aligned-store patterns cover 128-bit aligned vector atomic stores on
SSE/AVX/AVX-512 without per-type duplicates. \`<4 x float>\`,
\`<2 x double>\`, \`<2 x i64>\`, \`<4 x i32>\`, \`<8 x half>\`, \`<8 x bfloat>\`
all codegen to a single \`movaps\`/\`movapd\` on AVX+ via this.

Adds v8f16/v8bf16 bitconvert variants to the widen-path
\`atomic_store_32\` / \`atomic_store_64\` patterns so \`<2 x half>\`,
\`<2 x bfloat>\`, \`<4 x half>\`, \`<4 x bfloat>\` atomic stores reaching
the PR4 widen path also collapse to a single instruction on AVX+
targets.

Vectors whose \`getTypeAction\` is split rather than widen still rely
on PR6's \`SplitVecOp_ATOMIC_STORE\` — that path bitcasts the vector
to a scalar integer and issues an integer \`atomic_store_N\`, picked
up by the pre-existing scalar atomic-store patterns. The two

    [4 lines not shown]
DeltaFile
+86-0llvm/test/CodeGen/X86/atomic-load-store.ll
+5-4llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+3-2llvm/lib/Target/X86/X86InstrAVX512.td
+1-1llvm/include/llvm/Target/TargetSelectionDAG.td
+95-74 files