LLVM/project 82da5a9llvm/lib/Target/AMDGPU VOP3PInstructions.td AMDGPUTargetTransformInfo.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[AMDGPU] Duplicate packed fp32 instructions

These have different semantics on gfx9 and gfx12 with respect to
scalar operands.
DeltaFile
+21-9llvm/lib/Target/AMDGPU/SIInstructions.td
+9-9llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+7-7llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+9-4llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+6-6llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
+5-5llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+57-409 files not shown
+89-5415 files

LLVM/project a50d01cllvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp Triple.cpp

AMDGPU: TableGen the subarch triple name table

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+87-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+2-45llvm/lib/TargetParser/Triple.cpp
+23-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+17-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+4-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+133-655 files

LLVM/project 015dcd4clang/test/Misc/target-invalid-cpu-note r600.c amdgcn.c, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

AMDGPU: Eliminate old macro driven processor name parsing

Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+162-114llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+72-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+18-18clang/test/Misc/target-invalid-cpu-note/amdgcn.c
+10-10clang/test/Misc/target-invalid-cpu-note/r600.c
+2-2llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+264-1875 files

LLVM/project ace49dcllvm/lib/TargetParser AMDGPUTargetParser.cpp, llvm/utils/TableGen/Basic AMDGPUTargetDefEmitter.cpp

AMDGPU: TableGen the subarch to processor name mapping table

Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical GPU
name) with a generated table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+23-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+61-5llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+84-482 files

LLVM/project 76116e1llvm/lib/Target/ARM ARMSubtarget.cpp

Fix regression after removal of suffixed cmpeq calls
DeltaFile
+9-0llvm/lib/Target/ARM/ARMSubtarget.cpp
+9-01 files

LLVM/project 26d08c2llvm/lib/Target/RISCV RISCVRegisterInfo.td, llvm/test/MC/RISCV rv64zfh-invalid.s rv32d-invalid.s

[RISCV][MC] Improve FPR Error Messages (#212492)

This patch improves the error messages for the following register classes:
    
   1. FPR RegClasses (FPR16, FPR32, FPR64, FPR128, FPR256)
   2. Compressed FPR RegClasses (FPR16C, FPR32C, FPR64C)
   3. GPR-as-FPR classes used by Zfinx/Zdinx extensions (GPRAsFPR16, GPRAsFPR32, GPRF64AsFPR, GPRPairAsFPR).

---------

Co-authored-by: Saloni Shinde <saloshin at qti.qualcomm.com>
DeltaFile
+33-8llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+7-5llvm/test/MC/RISCV/rv32zfh-invalid.s
+9-3llvm/test/MC/RISCV/rv64d-invalid.s
+6-3llvm/test/MC/RISCV/rv32d-invalid.s
+7-2llvm/test/MC/RISCV/rv64f-invalid.s
+6-2llvm/test/MC/RISCV/rv64zfh-invalid.s
+68-2319 files not shown
+108-5925 files

LLVM/project 683799aclang-tools-extra/docs ReleaseNotes.rst

[clangd] Clarify release note about skipping preamble builds when using modules
DeltaFile
+3-1clang-tools-extra/docs/ReleaseNotes.rst
+3-11 files

FreeBSD/ports 20c1003security/vuxml/vuln 2026.xml

security/vuxml: document gitlab vulnerabilities
DeltaFile
+53-0security/vuxml/vuln/2026.xml
+53-01 files

LLVM/project 528ee37llvm/lib/Transforms/Vectorize/SandboxVectorizer DependencyGraph.cpp, llvm/unittests/Transforms/Vectorize/SandboxVectorizer DependencyGraphTest.cpp

[SandboxIR] Fix notifyEraseInstr to skip scheduled neighbors

Guard both loops with !PredN->scheduled() / !SuccN->scheduled() so
scheduled neighbors are left untouched, and add a unit test that erases
a node with one scheduled and one unscheduled predecessor to cover the
fix.
DeltaFile
+43-0llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
+2-1llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
+45-12 files

LLVM/project 6d32808llvm/lib/Transforms/Vectorize/SandboxVectorizer DependencyGraph.cpp, llvm/unittests/Transforms/Vectorize/SandboxVectorizer DependencyGraphTest.cpp

[SandboxIR] Fix notifyEraseInstr to skip scheduled neighbors

Guard both loops with !PredN->scheduled() / !SuccN->scheduled() so
scheduled neighbors are left untouched, and add a unit test that erases
a node with one scheduled and one unscheduled predecessor to cover the
fix.
DeltaFile
+43-0llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
+2-1llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
+45-12 files

LLVM/project 7330a8dllvm/lib/Target/AMDGPU GCNProcessors.td AMDGPUTargetParser.td, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: TableGen subarch to major subarch table (#212605)

Replace the hand-written AMDGPUMajorFamilies array with a
generated lookup table. Adds a special case for the major
arches missing a concrete generic target definition (we probably
should just define those to avoid this).

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+86-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+19-55llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+8-0llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
+6-0llvm/lib/Target/AMDGPU/GCNProcessors.td
+119-754 files

LLVM/project 095a652llvm/include/llvm/IR RuntimeLibcalls.td, llvm/lib/Target/ARM ARMSubtarget.cpp

ARM: Mark more generic libgcc functions as available

Generic libgcc/compiler-rt functions coexist with aeabi variants
(e.g., __divsi3  and __aeabi_idiv) according to my reading of the
build. At least in compiler-rt, they are aliases (such that I'm not sure
what the point of ever emitting the __aeabi name is).

They were previously removed from the available set on AEABI+AAPCS targets
to force selection of the preferred __aeabi_* variants, back when
only one implementation per libcall could be recorded.

Now that multiple implementations can be available per libcall, stop hiding
the generics and select the __aeabi_* variant explicitly as the preferred
implemntation. This reduces the number of special cases to consider for
future libcalls info improvements.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+62-0llvm/lib/Target/ARM/ARMSubtarget.cpp
+1-7llvm/include/llvm/IR/RuntimeLibcalls.td
+63-72 files

LLVM/project 83bd642llvm/lib/Target/ARM ARMAsmPrinter.cpp ARMISelLowering.cpp

ARM: Thread float ABI through ARMSubtarget (NFC)

Preparation to use the "float-abi" module flag. Store the resolved
float ABI in ARMSubtarget and fold it into the subtarget key. The
value is still sourced from TargetOptions::FloatABIType.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+9-3llvm/lib/Target/ARM/ARMTargetMachine.cpp
+11-1llvm/lib/Target/ARM/ARMSubtarget.h
+4-3llvm/lib/Target/ARM/ARMSubtarget.cpp
+0-6llvm/lib/Target/ARM/ARMTargetMachine.h
+2-3llvm/lib/Target/ARM/ARMISelLowering.cpp
+2-2llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+28-181 files not shown
+29-207 files

FreeBSD/ports 155f3addevel/RStudio Makefile

devel/RStudio: Extend expiration because electron41 fails to build

devel/electron41 is blacklisted on package builders so it is not
regularly tested.
DeltaFile
+1-1devel/RStudio/Makefile
+1-11 files

LLVM/project e1f93b0llvm/include/llvm/IR RuntimeLibcalls.td, llvm/lib/Target/MSP430 MSP430Subtarget.cpp

MSP430: Mark more generic libgcc functions as available (#212927)

The generic soft-float, conversion, comparison and integer helper
routines (__addsf3, __divli's __divsi3, __ashlsi3, ...) exist in the
MSP430 libgcc port alongside the preferred __mspabi_* variants. They 
were previously removed to force selection of the __mspabi_* names, back 
when only one implementation per libcall could be recorded.

Stop hiding them: only __lshrsi3 stays excluded, since the MSP430 libgcc
port provides the 32-bit logical right shift solely under __mspabi_srll
and never defines a generic __lshrsi3.

Repost of #210962

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+67-0llvm/lib/Target/MSP430/MSP430Subtarget.cpp
+4-11llvm/include/llvm/IR/RuntimeLibcalls.td
+71-112 files

FreeBSD/src 5f02c84share/man/man4 Makefile em.4

igb(4)/igbv(4): Document SR-IOV PF and VF functionality

Document supported controllers, PF and VF naming, PCI_IOV and IOMMU
requirements, queue and lifecycle constraints, iovctl schema, filtering
and anti-spoof policy, mailbox and MDD recovery, shared hardware
limits, rate control, and statistics cadence.

Relnotes:       yes
Sponsored by:   BBOX.io
DeltaFile
+169-4share/man/man4/em.4
+2-0share/man/man4/Makefile
+171-42 files

FreeBSD/src fdce383sys/dev/e1000 if_em.h if_em.c

igbv: Retry transient VLAN admission failures

A PF mailbox NACK does not distinguish the SR-IOV VLAN request rate
limit from permanent VLVF exhaustion. Preserve desired VLAN membership
and retry four additions per 500 ms timer tick, matching the PF
sustained allowance.

Bound the whole recovery batch to eight seconds from its first failure
and consolidate restore diagnostics, so a full table cannot create a
permanent mailbox poller or repeated per-VID log bursts.

Sponsored by:   BBOX.io
DeltaFile
+92-3sys/dev/e1000/if_igbv.c
+16-5sys/dev/e1000/if_em.c
+5-0sys/dev/e1000/if_em.h
+113-83 files

FreeBSD/src d2cd0b5sys/dev/e1000 if_em.h if_igbv.c

e1000: Sample statistics at timer cadence

Mailbox and link interrupts share iflib admin service with the periodic
timer. Mark timer-driven passes explicitly and run the hardware
statistics sweep only for those samples instead of repeating 66 PF MMIO
reads for every VF mailbox message.

DTrace on the I350 DUT measured the PF sweep at about 79 us on average.
The normal hz/2 timer continues to extend clear-on-read counters
safely; exported counters may trail hardware by up to 500 ms.

Sponsored by:   BBOX.io
DeltaFile
+14-1sys/dev/e1000/if_em.c
+2-1sys/dev/e1000/if_igbv.c
+1-0sys/dev/e1000/if_em.h
+17-23 files

FreeBSD/src e8f3b96sys/dev/e1000 if_igb_iov.c

igb: Rate-limit VF VLAN rebuild requests

Give each VF a burst of 64 VLAN additions and refill it at eight
additions per second. Removals remain unrestricted, idempotent requests
consume nothing, and trusted PF-wide initialization replenishes the
burst while guest resets do not.  Checks VLVF capacity before charging
a token.

Do not apply this policy to multicast requests because Linux igbvf and
DPDK ignore their reply status; aggregate MTA write elision bounds
those updates instead.

Sponsored by:   BBOX.io
DeltaFile
+57-5sys/dev/e1000/if_igb_iov.c
+57-51 files

FreeBSD/src 5ce6c94sys/dev/e1000 if_igb_iov.c

igb: Update only changed IOV VLAN filters

Keep the full VFTA/VLVF software recomputation and clear-map-set
ordering, but compare each phase against the authoritative old value.
Write only VFTA words and VLVF slots whose effective contents change.

I350 uses its software VFTA shadow because erratum 20 makes live reads
unreliable; an invalid shadow forces a complete clear before sparse
restoration. 82576 continues to diff against live VFTA reads.

Add SDT probes for every logical write phase and the final software
images so hardware tests can verify exact elision counts. On my I350
DUT, the old full table path averaged 819 us across 31 VLAN removals
versus about 79 us for the PF statistics sweep.

Sponsored by:   BBOX.io
DeltaFile
+83-15sys/dev/e1000/if_igb_iov.c
+83-151 files

FreeBSD/src 350211asys/dev/e1000 if_em.h if_em.c

igb: Update only changed IOV multicast hashes

Build the aggregate PF/VF multicast bitmap in software and compare it
with the e1000 MTA shadow. Write only registers whose desired value
changed, while forcing a complete write after PF reset invalidates the
hardware table.

This bounds alternating VF multicast updates without NACKing them.
Linux igbvf and DPDK ignore multicast reply status, so a command-rate
limiter could otherwise acknowledge configuration while leaving
hardware state stale.

Sponsored by:   BBOX.io
DeltaFile
+29-8sys/dev/e1000/if_igb_iov.c
+2-1sys/dev/e1000/if_em.c
+1-0sys/dev/e1000/if_em.h
+32-93 files

FreeBSD/src c637d47sys/dev/e1000 if_em.c

igb: Stop writing the legacy TADV register

TADV is an em-class interrupt delay register and is absent from the
82575 and later register model. The igb attach path does not expose or
initialize that control, but transmit initialization still wrote its
zero valued storage into a reserved queue-window offset.

Apply the same igb_mac_min boundary already used for TIDV and the
absolute-delay sysctls.

MFC after:      1 week
Sponsored by:   BBOX.io
DeltaFile
+1-1sys/dev/e1000/if_em.c
+1-11 files

FreeBSD/src 9332fd5sys/dev/e1000 if_em.c e1000_vf.h

igbv: Support secondary unicast filters

Support the Linux igbvf secondary-MAC mailbox subprotocol, used by
Linux guests running MacVTap.

Replay up to three non-primary unicast addresses after reset and
whenever the address list changes, subject to PF allow-set-mac policy.

Sponsored by:   BBOX.io
DeltaFile
+66-0sys/dev/e1000/if_igbv.c
+35-0sys/dev/e1000/e1000_vf.c
+3-0sys/dev/e1000/if_em.h
+1-0sys/dev/e1000/if_em.c
+1-0sys/dev/e1000/e1000_vf.h
+1-0sys/dev/e1000/e1000_82575.h
+107-06 files

LLVM/project f5932b7llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp Triple.cpp

AMDGPU: TableGen the subarch triple name table

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+87-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+2-45llvm/lib/TargetParser/Triple.cpp
+23-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+17-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+4-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+133-655 files

LLVM/project eb68413clang/test/Misc/target-invalid-cpu-note r600.c amdgcn.c, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

AMDGPU: Eliminate old macro driven processor name parsing

Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+162-114llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+72-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+18-18clang/test/Misc/target-invalid-cpu-note/amdgcn.c
+10-10clang/test/Misc/target-invalid-cpu-note/r600.c
+2-2llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+264-1875 files

LLVM/project 2bd2710llvm/lib/TargetParser AMDGPUTargetParser.cpp, llvm/utils/TableGen/Basic AMDGPUTargetDefEmitter.cpp

AMDGPU: TableGen the subarch to processor name mapping table

Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical GPU
name) with a generated table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+23-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+61-5llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+84-482 files

LLVM/project 8ec997dllvm/lib/Target/AMDGPU GCNProcessors.td AMDGPUTargetParser.td, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: TableGen subarch to major subarch table

Replace the hand-written AMDGPUMajorFamilies array with a
generated lookup table. Adds a special case for the major
arches missing a concrete generic target definition (we probably
should just define those to avoid this).

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+86-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+19-55llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+8-0llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
+6-0llvm/lib/Target/AMDGPU/GCNProcessors.td
+119-754 files

LLVM/project 8069359clang/test/Misc/target-invalid-cpu-note amdgcn.c, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

AMDGPU: Handle more TargetParser queries in tablegen (#212357)

Previously we had various enum switches. Start generated tables
indexed by enums. Avoid some special cases by defining the dummy
"generic" and "generic-hsa" targets as real processors.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+79-83llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+109-39llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+21-0llvm/unittests/TargetParser/TargetParserTest.cpp
+12-4llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+14-0clang/test/Misc/target-invalid-cpu-note/amdgcn.c
+7-4llvm/lib/Target/AMDGPU/GCNProcessors.td
+242-1307 files not shown
+271-14013 files

FreeBSD/src a6bb385sys/dev/e1000 if_em.h igb_txrx.c

igbv: Improve VF mailbox and status behavior

Treat VF media as fixed 1000baseT full duplex and report PF not ready
and generated MAC fallback states during attach.

After a successful reset handshake, reconcile a PF rejected MAC back
into the ifnet. If the PF is unavailable, defer MAC, multicast, VLAN,
LPE, and promiscuity replay until CTS is restored. Track a rejected
VLAN removal separately so leaked traffic remains tagged until reset
proves that the stale hardware filter is gone.

Baseline VF counters at attach, collect the four loopback packet and
octet counters with rollover-safe deltas, and account software RX
checksum offload results. Preserve accumulated statistics across PF
resets by rebasing the raw hardware counters, and sample them while
physical link is down because VF loopback can remain active.

Retain the 82576 VFMPRC hardware statistic, but do not read it on I350
VFs because specification update errata 31 says it is unavailable.

    [5 lines not shown]
DeltaFile
+168-44sys/dev/e1000/if_em.c
+115-0sys/dev/e1000/if_igbv.c
+26-8sys/dev/e1000/igb_txrx.c
+10-4sys/dev/e1000/if_em.h
+319-564 files

FreeBSD/src 316f6f2sys/dev/e1000 em_txrx.c if_em.h, sys/modules/em Makefile

igbv: Isolate VF policy and validate its registers

Give igb virtual functions a separate ifdi method table and move
VF-specific attach, reset, queue, interrupt, and diagnostic policy to
if_igbv.c. Keep shared descriptor-ring mechanisms in if_em.c.

Derive VF identity from IFLIB_IS_VF and assert that hardware
identification agrees. Under INVARIANTS, validate normal VF CSR
accesses against the sparse 82576 and I350 VF register maps.

Stop shared setup from accessing PF-only controls. Require MSI-X and
defer VF sysctls until attach succeeds so failed attachment cannot
leave handlers pointing at freed driver state.

Advertise only VF capabilities, run adaptive moderation without the
PF receive-buffer guard, enable SRRCTL.DROP_EN, and provide a VF-safe
diagnostic register view.

The moved implementation is the existing FreeBSD code. Register model

    [3 lines not shown]
DeltaFile
+361-252sys/dev/e1000/if_em.c
+205-0sys/dev/e1000/if_igbv.c
+83-1sys/dev/e1000/e1000_osdep.h
+19-0sys/dev/e1000/if_em.h
+5-0sys/dev/e1000/em_txrx.c
+1-1sys/modules/em/Makefile
+674-2541 files not shown
+676-2547 files