LLVM/project a966e74clang/include/clang/CIR/Dialect/IR CIRTypes.h, clang/lib/CIR/CodeGen CIRGenRecordLayoutBuilder.cpp

[CIR][NFC] Say "access unit" where the code says "unit"

`makeMemberKind` took a bool called `isUnit`, which does not say what the
member is a unit of, and the `isBitFieldUnit` predicate feeding it had the same
gap. Both become `isBitFieldAccessUnit`, matching the term classic uses, and
the helper picks up a short comment adapted from `CGRecordLayoutBuilder.cpp` so
a reader meets the definition where the parameter is read.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+11-4clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
+5-5clang/include/clang/CIR/Dialect/IR/CIRTypes.h
+16-92 files

LLVM/project 7b09cd4clang/docs/analyzer checkers.md checkers.rst, clang/docs/analyzer/developer-docs IPA.rst

rebase

Created using spr 1.3.7
DeltaFile
+0-4,248clang/docs/analyzer/checkers.rst
+4,182-0clang/docs/analyzer/checkers.md
+0-735clang/docs/analyzer/user-docs/Annotations.rst
+720-0clang/docs/analyzer/user-docs/Annotations.md
+362-151llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
+0-396clang/docs/analyzer/developer-docs/IPA.rst
+5,264-5,530398 files not shown
+17,233-10,171404 files

LLVM/project 55c17f2clang/docs/analyzer checkers.md checkers.rst, clang/docs/analyzer/developer-docs IPA.rst

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-4,248clang/docs/analyzer/checkers.rst
+4,182-0clang/docs/analyzer/checkers.md
+0-735clang/docs/analyzer/user-docs/Annotations.rst
+720-0clang/docs/analyzer/user-docs/Annotations.md
+362-151llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
+0-396clang/docs/analyzer/developer-docs/IPA.rst
+5,264-5,530398 files not shown
+17,233-10,171404 files

LLVM/project d43053aclang/docs/analyzer checkers.md checkers.rst, clang/docs/analyzer/developer-docs IPA.rst

rebase

Created using spr 1.3.7
DeltaFile
+0-4,248clang/docs/analyzer/checkers.rst
+4,182-0clang/docs/analyzer/checkers.md
+0-735clang/docs/analyzer/user-docs/Annotations.rst
+720-0clang/docs/analyzer/user-docs/Annotations.md
+362-151llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
+0-396clang/docs/analyzer/developer-docs/IPA.rst
+5,264-5,530398 files not shown
+17,233-10,171404 files

LLVM/project 774d70allvm/include/llvm/CodeGen/GlobalISel LoadStoreOpt.h, llvm/lib/CodeGen/GlobalISel LoadStoreOpt.cpp

[GISel] Remove unused DoNotRunPass Hook

This was not used anywhere by callers of LoadStoreOpt and not even wired
up in the implementation, so remove it.

Reviewers: arsenm, aemerson

Pull Request: https://github.com/llvm/llvm-project/pull/217050
DeltaFile
+1-5llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
+0-5llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h
+1-102 files

LLVM/project 081c5a7clang/docs/analyzer conf.py, libc/docs/_static copybutton.js

[clang][docs] Prototype Furo theme setup
DeltaFile
+140-0utils/docs/llvm_sphinx/_static/furo-common.css
+0-71llvm/docs/_static/custom.css
+0-56llvm/docs/_static/copybutton.js
+0-56libc/docs/_static/copybutton.js
+56-0utils/docs/llvm_sphinx/_static/copybutton.js
+10-34clang/docs/analyzer/conf.py
+206-2179 files not shown
+335-39215 files

LLVM/project e44ebfeclang/docs UsersManual.md

Fix text color in dark mode
DeltaFile
+1-1clang/docs/UsersManual.md
+1-11 files

LLVM/project d86340eclang/docs Toolchain.md ReleaseNotes.md, clang/include/clang/Basic BuiltinsAMDGPUDocs.td

[clang][docs] Remove page-local contents directives
DeltaFile
+0-10clang/docs/DriverInternals.md
+0-4clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+0-4clang/docs/Toolchain.md
+0-4clang/docs/ReleaseNotes.md
+0-4clang/docs/LanguageExtensions.md
+0-4clang/docs/FunctionEffectAnalysis.md
+0-3074 files not shown
+0-24980 files

LLVM/project 3646ebaclang/docs conf.py, clang/docs/_static custom.css

[docs] Restore project-specific Furo CSS
DeltaFile
+0-140utils/docs/llvm_sphinx/_static/furo-common.css
+71-0llvm/docs/_static/custom.css
+60-0clang/docs/_static/custom.css
+8-0utils/docs/llvm_sphinx/__init__.py
+2-1llvm/docs/conf.py
+3-0clang/docs/conf.py
+144-1414 files not shown
+147-14210 files

LLVM/project 7a7a207flang/lib/Optimizer/OpenMP MapInfoFinalization.cpp, flang/test/Lower/OpenMP usm-descriptor-close-map.f90

[Flang][OpenMP] Remove forced close mapping for descriptor in USM (#215350)

This was added originally to solve an issue with pointer checking on USM
devices (usm_map_close.f90 in the fortran offload tests) but no longer
appears to be required.

None the less, this isn't a fix we can keep around, we cannot force
close mapping on things, we should only carry it over if a user
specifies it (done so above). As if we force it onto the descriptor,
then on USM architectures in USM mode we're actually inflicting the user
with unwanted and unrequested host to device transfers. As we're saying
we want the descriptor to be placed in memory as close to the device as
possible (so device memory). We shouldn't make the assumption this is
what a user wishes, especially when they can now refine there mappings
to specify what they want done with the descriptor.

So, removing this as a performance and correctness optimization now that
it no longer appears to be required for the usm_map_close.f90 test on at
least a fully USM enabled system like gfx942.

    [2 lines not shown]
DeltaFile
+35-0flang/test/Lower/OpenMP/usm-descriptor-close-map.f90
+0-5flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
+35-52 files

LLVM/project 6c9ef39llvm/test/Transforms/InstCombine/AMDGPU make-buffer-rsrc-num-records.ll

Clean up triples
DeltaFile
+3-3llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+3-31 files

LLVM/project b09a1d8llvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

Update generic target to something better
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+1-11 files

LLVM/project b88c1daclang/lib/CodeGen CodeGenModule.h CodeGenModule.cpp, clang/test/CodeGenSYCL offload-include-binary.cpp

[clang][SYCL] Embed finalized device binary for -foffload-include-binary (#216419)

During SYCL host compilation, honor -foffload-include-binary by reading
the finalized SYCL device binary it names and embedding it into the host
module, along with the registration constructors and destructors the
SYCL runtime expects. This reuses the shared offloading wrapper
(llvm::offloading::wrapSYCLBinaries).

wrapSYCLBinaries gains an IsFinalizedImage parameter.
clang-linker-wrapper scans sections whose name starts with
".llvm.offloading" for device code that still needs a device link, so an
already finalized image is placed in ".sycl_fatbin" instead.

wrapSYCLBinaries() now hands the register/unregister functions back to
the caller, and CodeGenModule::Release() adds them with
AddGlobalCtor/AddGlobalDtor.
The embedding (and adding of Ctor/Dctor to the constructors/destructors
lists) runs before registerGlobalDtorsWithAtExit in
CodeGenModule::Release(): with -fregister-global-dtors-with-atexit

    [4 lines not shown]
DeltaFile
+57-0clang/test/CodeGenSYCL/offload-include-binary.cpp
+26-12llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
+26-0clang/lib/CodeGen/CodeGenSYCL.cpp
+10-3llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
+9-0clang/lib/CodeGen/CodeGenModule.cpp
+6-0clang/lib/CodeGen/CodeGenModule.h
+134-156 files

LLVM/project 2b417a2llvm/lib/Target/M68k M68kTargetMachine.cpp

[M68k] Fix build after IRTranslator rename to IRTranslatorLegacy (#217129)

Regression introduced by f442901707f9 ("[NewPM] Port ir-translator"),
which renamed the legacy pass but missed the M68k target.
DeltaFile
+1-1llvm/lib/Target/M68k/M68kTargetMachine.cpp
+1-11 files

FreeBSD/ports f56b754biology/exonerate pkg-plist Makefile

biology/exonerate: Improve port, take maintainership

* Use https:// scheme for MASTER_SITES
* Improve COMMENT
* Pet portclippy(1) and portfmt(1)
* Sort pkg-plist

Approved by:            db@, yuri@ (Mentors, implicit)
DeltaFile
+8-8biology/exonerate/Makefile
+6-6biology/exonerate/pkg-plist
+14-142 files

LLVM/project d2d47f6bolt/lib/Core Relocation.cpp, bolt/test/AArch64 tls.c

Revert "[AArch64][BOLT] Fold local-exec TLS relocations into loads and stores" (#217095)

Reverts llvm/llvm-project#215531 due to regressions on systems with
older binutils.
DeltaFile
+6-47llvm/test/CodeGen/AArch64/arm64-tls-local-exec.ll
+1-18llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+0-12bolt/test/AArch64/tls.c
+7-5llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+0-10llvm/test/CodeGen/AArch64/win-tls.ll
+0-8bolt/lib/Core/Relocation.cpp
+14-1006 files

LLVM/project 17df998llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv masked-load-vl-predicatable.ll

[RISCV] Canonicalize mask-producing SETCC for easier conversion on the consuming instruction to be VL-predicate (#214877)

Split out from #214350 .

This patch canonicalizes
```
%b = splat %base
%s = <%offset, %offset + 1, %offset + 2, %offset + 3, ...>
%a = add nuw %b, %s
%N = splat %n
%p = setcc ult %a, %N
```
into
```
%s = <0, 1, 2, 3, ...>
%m = sub %n, min(%n, %base + %offset)
%M = splat %m
%p = setcc ult %s, %M
```

    [2 lines not shown]
DeltaFile
+243-0llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
+85-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+328-02 files

LLVM/project 8c28e29libc/src/__support/OSUtil/linux/syscall_wrappers clone3.h rt_sigaction.h, libc/src/stdlib/linux system.cpp

[libc] Implement system function (#211672)

This Pr implements the system function, as well as adding syscall
wrappers for several syscalls that system needs.
DeltaFile
+118-0libc/src/stdlib/linux/system.cpp
+53-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+49-0libc/src/__support/OSUtil/linux/syscall_wrappers/execle.h
+48-0libc/test/src/stdlib/system_test.cpp
+36-0libc/src/__support/OSUtil/linux/syscall_wrappers/clone3.h
+36-0libc/src/__support/OSUtil/linux/syscall_wrappers/rt_sigaction.h
+340-07 files not shown
+419-013 files

LLVM/project 1aed87dlldb/source/Target StackFrameList.cpp, lldb/test/API/functionalities/scripted_frame_provider/frame_index_after_depth_change Makefile main.c

[lldb] Don't merge a frame provider's frames into the unwinder frame list (#216847)

`Thread::ClearStackFrames` keeps the previous public frame list as the
predecessor of the next unwinder list. When a scripted frame provider is
registered, that public list is a `SyntheticStackFrameList` holding
`BorrowedStackFrames`, and the unwinder list's merge step reuses a
predecessor frame whenever the stack IDs match, so it adopted frames
belonging to the provider's list.

`UpdatePreviousFrameFromCurrentFrame` refreshes
`StackFrame::m_frame_index`, but `BorrowedStackFrame::GetFrameIndex()`
returns its own `m_new_frame_index`, which supersedes it. The adopted
frame keeps reporting its index from the previous stop, so once the
stack grows the backtrace stops counting up:

```
  frame #1: middle
  frame #1: main
  frame #2: start

    [12 lines not shown]
DeltaFile
+49-0lldb/test/API/functionalities/scripted_frame_provider/frame_index_after_depth_change/TestFrameProviderFrameIndexAfterDepthChange.py
+21-0lldb/test/API/functionalities/scripted_frame_provider/frame_index_after_depth_change/frame_provider.py
+20-0lldb/test/API/functionalities/scripted_frame_provider/frame_index_after_depth_change/main.c
+9-0lldb/source/Target/StackFrameList.cpp
+4-0lldb/test/API/functionalities/scripted_frame_provider/frame_index_after_depth_change/Makefile
+103-05 files

LLVM/project b0e9c53lldb/source/Plugins/OperatingSystem/Python OperatingSystemPython.cpp, lldb/source/Plugins/Process/Utility RegisterContextMemory.cpp

[lldb] Fix use-after-free of a scripted frame's register info (#216840)

`ScriptedFrame::CreateRegisterContext` built the frame's
`DynamicRegisterInfo` in a local `shared_ptr` and passed it to
`RegisterContextMemory`, which kept a `DynamicRegisterInfo` reference
and did not own it. That function was the sole owner, so the register
info died as soon as it returned, leaving the register context it had
just produced with a dangling reference.

The frame survives creation because `SetAllRegisterData` runs while the
register info is still alive. It crashes later, on the first register
lookup driven by a DWARF location expression, for instance when a
backtrace formats the frame's arguments.

This patch makes `RegisterContextMemory` own its register info: it takes
a `shared_ptr` and keeps it for its own lifetime, so a register context
is self-contained and nothing else has to stay alive on its behalf.
`ScriptedThread` and `OperatingSystemPython` both kept the register info
in a member to back the reference they handed out, so both members are

    [12 lines not shown]
DeltaFile
+54-84lldb/source/Plugins/Process/scripted/ScriptedFrame.cpp
+83-0lldb/test/API/functionalities/scripted_frame_provider/wrapped_frame_register_context/frame_provider.py
+23-23lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.cpp
+35-0lldb/test/API/functionalities/scripted_frame_provider/wrapped_frame_register_context/TestFrameProviderWrappedFrameRegisterContext.py
+17-15lldb/source/Plugins/Process/scripted/ScriptedThread.cpp
+12-11lldb/source/Plugins/Process/Utility/RegisterContextMemory.cpp
+224-1336 files not shown
+241-14412 files

LLVM/project 76d426aclang/docs/ScalableStaticAnalysis/developer-docs HowToExtend.md, clang/docs/analyzer checkers.md

[docs][clang] Finish MyST migration for analyzer docs (#216245)

Tracking issue: #201242
See the [migration guide] for more information. 

[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is a stacked PR based on #216244 , which will be a standalone
commit that
renames *.rst -> *.md before this PR lands for history preservation
purposes.

This PR has two commits:
- One that is the raw output of rst2myst
- A cleanup commit using LLMs and prompting

I validated the output by rendering the web page and looking at pixel
diffs, and all the diffs appear to be bug fixes. I don't yet have a way
to publish that artifact, but I'm working on it.
DeltaFile
+2,611-2,677clang/docs/analyzer/checkers.md
+340-355clang/docs/analyzer/user-docs/Annotations.md
+235-239clang/docs/analyzer/user-docs/CrossTranslationUnit.md
+155-144clang/docs/analyzer/developer-docs/DebugChecks.md
+149-136clang/docs/analyzer/user-docs/CommandLineUsage.md
+127-142clang/docs/ScalableStaticAnalysis/developer-docs/HowToExtend.md
+3,617-3,69318 files not shown
+4,428-4,58524 files

LLVM/project d9a8f74clang/docs/analyzer checkers.rst checkers.md, clang/docs/analyzer/developer-docs IPA.rst IPA.md

[docs][clang] Rename analyzer docs to Markdown (#216244)

Tracking issue: #201242
See the [migration guide] for more information. 

[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines

This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
DeltaFile
+0-4,248clang/docs/analyzer/checkers.rst
+4,248-0clang/docs/analyzer/checkers.md
+0-735clang/docs/analyzer/user-docs/Annotations.rst
+735-0clang/docs/analyzer/user-docs/Annotations.md
+0-396clang/docs/analyzer/developer-docs/IPA.rst
+396-0clang/docs/analyzer/developer-docs/IPA.md
+5,379-5,37942 files not shown
+8,210-8,21048 files

NetBSD/src 4f1fSrGsys/arch/sgimips/gio newport.c

   newport: ensure a valid ri_stride is provided to rasops_init()

   The x resolution is calculated by timings programmed into VC2, rather
   than some kind of hard coded width/height from the framebuffer.
   Newport always supports up to 1280x1024 regardless of what your monitor
   resolution is.

   However for some monitor detection timings, the resulting geometry
   is not ENTIRELY correct for rasops to work with.  So just round it up
   to a multiple of four so a newport console will always show up regardless
   of said monitor timing.

   Submitted by Imre Kaloz  <kaloz at dune.hu> .

   Fixes PR port-sgimips/60585 .
VersionDeltaFile
1.26+11-4sys/arch/sgimips/gio/newport.c
+11-41 files

LLVM/project c731596libc/test/src/stdio freopen_test.cpp, llvm/lib/CodeGen/GlobalISel IRTranslator.cpp

Merge branch 'main' into users/isanbard/implicit-null-check-newpm
DeltaFile
+294-294llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
+567-0llvm/test/CodeGen/AArch64/aarch64-condopt-cross-block-select.mir
+362-151llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
+265-207llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+318-0libc/test/src/stdio/freopen_test.cpp
+141-141llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
+1,947-793445 files not shown
+12,962-3,439451 files

LLVM/project 7d89e08llvm/include/llvm/CodeGen ImplicitNullChecks.h

Use OptionalPasInfoMixin
DeltaFile
+2-1llvm/include/llvm/CodeGen/ImplicitNullChecks.h
+2-11 files

LLVM/project f9b0d5cclang/test/CodeGenOpenCL builtins-amdgcn-make-buffer-rsrc.cl, llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp

[AMDGPU] Canonicalize num_records to its actual width in InstCombine

llvm.amdgcn.make.buffer.rsrc is overloaded on the type of its
num_records argument, but the hardware field it ends up in has a fixed
width (32 bits, or 45 bits on gfx1250 and up). Rewrite the intrinsic to
use that width, zero-extending or truncating num_records as needed, so
that IR-level optimizations can see that the extra bits of, for example,
the i64 that Clang emits are not demanded.

Targets that aren't concrete enough for the buffer resource layout to be
known are left alone.

AI disclosure: This was my idea but Claude wrote the code (and I've
tried to tighten up the comments)
DeltaFile
+36-44clang/test/CodeGenOpenCL/builtins-amdgcn-make-buffer-rsrc.cl
+27-27llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+22-12llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+21-1llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+106-844 files

LLVM/project 58b7363mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp, mlir/test/Conversion/AMDGPUToROCDL amdgpu-to-rocdl.mlir

[mlir][AMDGPU] Emit num_records at the buffer resource's actual width

makeBufferRsrc() zero-extended num_records to i64 on targets whose
buffer resource has a 45-bit num_records field, leaving 19 bits that the
hardware will never look at. Emit an i45 instead, which is what
rocdl.make.buffer.rsrc will end up putting in the descriptor anyway, so
that downstream consumers can see that those bits aren't demanded.

While here, factor the i32 and i64 conversion helpers into a shared
convertUnsignedToInt() that takes the target width.

AI disclosure: Claude made this, I looked at and poked the design into
shape.
DeltaFile
+50-25mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
+18-19mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+68-442 files

LLVM/project 1439a63llvm/test/Transforms/InstCombine/AMDGPU make-buffer-rsrc-num-records.ll

[AMDGPU] Pre-commit tests for num_records canonicalization

Add tests for having InstCombine canonicalize the num_records argument
of llvm.amdgcn.make.buffer.rsrc to the width it will ultimately have,
which lets later passes see that, for example, the high bits of the i64
that Clang emits aren't used.

AI disclosure: Claude generated these and I've looked at them
DeltaFile
+153-0llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+153-01 files

LLVM/project baecc9ellvm/lib/Target/AMDGPU AMDGPULowerBufferFatPointers.cpp, llvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

[AMDGPU] Use real num_records width in LowerBufferFatPointers

Fix the following edge cases in reasoning about whether a value can be
The out-of-bounds analysis in LowerBufferFatPointers took the
num_records operand of llvm.amdgcn.make.buffer.rsrc at face value, which
went wrong in three ways.

1. The pass would crash if num_records was narrower than the
underlying hardware width.
2. A 45-bit num_records with its high bit set made all offsets look
negative, which, among other things, broke the `(1 << 45) - 1` "no
bounds checking" value.
3. The test for all-1 num_records wasn't accounting for hardware
width, leading to false positives if the num_records field was
narrower tan the underlying field.
4. Don't try to do reasoning about num_records when its width isn't
known.

AI disclosure: Claude found and took a try at fixing these, I've
reviewed
DeltaFile
+199-59llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+19-13llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+218-722 files

LLVM/project ef6955dllvm/test/CodeGen/AMDGPU lower-buffer-fat-pointers-num-records-width.ll

[AMDGPU] Pre-commit num_records of arbitrary width tests for LowerBufferFatPointers

Add tests to ensure that the reasoning for whether an access can be
partially out of bounds and needs to be scalarized work correctly when
num_records has a width different from the hardware width.

AI disclosure: Claude generated these and I've looked at them
DeltaFile
+236-0llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-num-records-width.ll
+236-01 files