[StructurizeCFG] Remove hidden option -structurizecfg-relaxed-uniform-regions (#232645)
This option has been enabled by default since 5a0794327a67 over 7 years
ago and I am not aware of any users that disable it. It only matters
when -structurizecfg-skip-uniform-regions is also enabled, which is
currently only done by the AMDGPU backend.
system: multiple users with the same UID share the same groups
This would actually prevent root from logging into the web GUI
as the page lookup failed because looking for the installer user
did not yield any associated pages.
[AMDGPU] Update sleep max (#232561)
The `s_monitor_sleep` has a maximum of around 8000 clock, but was
calculated by the low 6 bit multiply by 64.
So the maximum value in operand is 127.
Co-authored-by: shore <shorshen at amd.com>
[X86] vector-reduce-add-mask.ll - fix v4i16_v4i8 test so the v4i16 is representable as v4i8 (#232642)
Cut + paste typo that we didn't notice as we don't do much to reduce sub-128-bit vectors yet
[CodeGen] Report an error for a direct inline asm output in memory
An inline asm output returned by value has no memory to write to, yet a
constraint such as "=rm" picks memory, the most general constraint, as
does "=m". SelectionDAG asserted on that ("Can only indirectify direct
input operands!"), and GlobalISel dereferenced a null pointer. Clang
never emits such an output, since it passes the address of a memory
output, but other IR can. Report "cannot handle direct memory outputs
yet for constraint 'm'" instead, like the other inline asm errors there.
Assisted-by: Claude Opus 5.5
[CodeGen] Address review: error for "=m|r" direct outputs too
A direct output whose chosen alternative is memory, e.g. "=m|r", still
crashed SelectionDAG, which exempted multiple-alternative operands from the
check and then asked for the address of an output with no value. Drop the
exemption and test "=m|r" with both instruction selectors. Name the
selector explicitly in the RUN lines rather than relying on -O levels,
since X86 GlobalISel can't lower inline asm and both X86 lines ran
SelectionDAG anyway. Drop "yet" from the error: Clang never emits a
direct memory output, so there are no plans to support one.
Assisted-by: Claude Opus 5.5
[TargetInstrInfo] Address review: autogenerate greedy-inline-asm-fold.mir checks
Generate the checks with update_mir_test_checks.py so that the spills and
reloads around each folded inline asm are verified, not just the INLINEASM
itself. Fix the "=r" comment to describe the C "+r" operand, note that which
"+rm" pair greedy folds is its own choice, and add a "+&rm" case on an
uninitialized value showing that folding a pair whose tied use is undef
stores to the slot without loading from it.
Assisted-by: Claude Opus 5.5
[TargetInstrInfo] Fix folding inline asm operands next to tied operands
foldInlineAsmMemOperand() swapped a register operand for the target's
memory operands with MachineInstr::removeOperand(), which asserts when a
later operand is tied, because moving it would break the tie. Inline asm
lists every input after every output, so folding any operand that comes
before another tied pair asserted, e.g. an "rm" input followed by the
input of a "+r" operand, or one of two "+rm" operands. Without
assertions, the moved operands kept stale tie indices. Untie the
operands, rebuild the operand list, and re-tie the remaining pairs at
their new positions.
It also gave up when the register appears in more than one operand, e.g.
one value passed to two "rm" operands, which left the greedy allocator
unable to spill that value at all. Fold every such operand into the
stack slot.
Finally, take MayLoad from the folded operands rather than from every
read of the register: a folded def whose tied use is another virtual
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[TableGen] Remove deprecated ListInit::getValues() (#232451)
`ListInit::getValues()` was deprecated in favor of getElements(). Remove
it now that there are no remaining in-tree users.
Co-authored-by: Claude <noreply at anthropic.com>
[RISCV][P-ext] Add scalar multiply high accumulate intrinsics (#232340)
Add the scalar Multiply High Accumulate intrinsics
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#multiply-high-accumulate
- `__riscv_mhacc_i32`
- `__riscv_mhracc_i32`
- `__riscv_mhaccu_u32`
- `__riscv_mhraccu_u32`
- `__riscv_mhaccsu_i32`
- `__riscv_mhraccsu_i32`
RV32 selects the scalar `mhacc` family directly. RV64 has no scalar
forms,so the intrinsics use the `pmhacc.w` family on the low words,
the same way as the scalar `aadd`/`asub` intrinsics (#230710).
[SLP] Skip getelementptr pairs that are related affine loop recurrences (#226220)
When the loop vectorizer scalarizes strided accesses, each lane computes
its address as `base + ((off + stride * (iv + k)) << 2)`, with a
loop-invariant stride and offset, which loop strength reduction turns
into pointer increments. Since #150450 made the cost model loop-aware,
`vectorizeGEPIndices` compares against that scalar arithmetic and finds
`<4 x i64>` mul/add/shl, with every lane extracted for the scalar
accesses, profitable.
`vectorizeGEPIndices` already drops pairs of getelementptrs with a
constant difference. This patch also drops pairs that are affine
recurrences of the enclosing loop with a loop-invariant difference,
since LSR computes both from a common induction variable. Since #228918,
the once-used seeds no longer pick up this index arithmetic, so no extra
seed filtering is needed.
For `strided_gather_offset` in `X86/strength-reducible-address.ll`
(#226907), the loop goes from 30 to 13 instructions with Haswell code,
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