LLVM/project fc4cac3llvm/test/Transforms/IndVarSimplify unreachable-exit.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+4-4llvm/test/Transforms/IndVarSimplify/unreachable-exit.ll
+4-41 files

LLVM/project 0e785f0llvm/test/Transforms/IndVarSimplify unreachable-exit.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+89-4llvm/test/Transforms/IndVarSimplify/unreachable-exit.ll
+89-41 files

LLVM/project 22a3f7butils/bazel/llvm-project-overlay/lldb/source/Plugins BUILD.bazel

[bazel] Fix after #181026 (#181260)

DeltaFile
+3-3utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
+3-31 files

LLVM/project ef85b0cllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize first-order-recurrence-tail-folding.ll first-order-recurrence.ll

[VPlan] Check scalar VF in removeRedundantCanonicalIVs.

When the plan has only a scalar VF, we never generate vectors for IVs,
so we can always perform the replacement.
DeltaFile
+12-15llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
+6-7llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
+4-5llvm/test/Transforms/LoopVectorize/strict-fadd-interleave-only.ll
+2-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+24-284 files

LLVM/project 449dfd4llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

Removed shouldExpandPowerOf2DivRem, rebased, fixed conflicts
DeltaFile
+1,099-947llvm/test/CodeGen/AMDGPU/rem_i128.ll
+726-612llvm/test/CodeGen/AMDGPU/div_i128.ll
+138-51llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
+9-27llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
+0-7llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+0-5llvm/include/llvm/CodeGen/TargetLowering.h
+1,972-1,6491 files not shown
+1,972-1,6517 files

LLVM/project 686fd7fclang/test/CodeGenCUDA fp-contract.cu

Fixed test, addressed comment.
DeltaFile
+5-5clang/test/CodeGenCUDA/fp-contract.cu
+5-51 files

LLVM/project a527a88llvm/test/CodeGen/AMDGPU memory-legalizer-private-wavefront.ll memory-legalizer-private-workgroup.ll

[AMDGPU] Disable generic DAG combines at -O0 to preserve debuggability.

Disable generic DAG combines for AMDGPU at -O0 via disableGenericCombines()
to preserve instructions that users may want to set breakpoints
on during debugging.

Since power-of-2 division/remainder for types > i64 was dependent on
DAG combine optimizations, added shouldExpandPowerOf2DivRem()
to request IR-level expansion for these cases at -O0.
DeltaFile
+8,544-1,366llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+8,544-1,366llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
+8,544-1,366llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
+8,449-1,355llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
+8,449-1,355llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
+8,069-1,315llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
+50,599-8,12370 files not shown
+189,659-24,55276 files

LLVM/project d0ff94f.github/workflows release-tasks.yml release-documentation.yml

workflows/release-documentation: Add release environment (#181063)

This way we can limit access to the secrets to the main and release
branches.

This is a partial re-commit of b6ee085068972a41f3b2735a9f7e3ca48eab0f00
DeltaFile
+0-4.github/workflows/release-tasks.yml
+1-0.github/workflows/release-documentation.yml
+1-42 files

LLVM/project d4cac78clang/include module.modulemap

[clang] Mark `PrivateFieldNames.def` as textual header in module map (#181250)

When building with modules enabled (`LLVM_ENABLE_MODULES=ON`), the
module system attempts to transform the inclusion of
`PrivateFieldNames.def` into a module import. Since this `#include`
appears inside the `SerializationFormat` class definition (to generate
accessor methods via macros), the resulting module import violates C++
modules rules that imports must appear at file scope. The fix is to mark
`PrivateFieldNames.def` as a textual header in the `Clang_Analysis`
module to ensure the file is processed as a traditional textual include.

rdar://170257449
DeltaFile
+1-0clang/include/module.modulemap
+1-01 files

LLVM/project f952dbcllvm/test/Transforms/IndVarSimplify unreachable-exit.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+4-4llvm/test/Transforms/IndVarSimplify/unreachable-exit.ll
+4-41 files

LLVM/project 373b3e1clang/lib/CIR/Dialect/Transforms FlattenCFG.cpp, clang/test/CIR/Transforms flatten-cleanup-scope-multi-exit.cir

Merge branch 'main' into users/dfukalov/add_ir_pow2expansion
DeltaFile
+1,362-0llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+828-120clang/test/CIR/Transforms/flatten-cleanup-scope-multi-exit.cir
+415-234clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
+15-334libcxx/src/hash.cpp
+324-0lldb/unittests/Highlighter/HighlighterTest.cpp
+0-319lldb/unittests/Language/Highlighting/HighlighterTest.cpp
+2,944-1,007222 files not shown
+8,829-2,522228 files

LLVM/project 33d0365clang/include/clang/Basic BuiltinsAMDGPU.td, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-wmma-w32.cl .gdb_history

[AMDGPU] Change 9 SWMMAC builtins to use 64-bit index

There 9 gfx1250 instructions have 64-bit packed index:

- v_swmmac_f16_16x16x128_bf8_bf8
- v_swmmac_f16_16x16x128_bf8_fp8
- v_swmmac_f16_16x16x128_fp8_bf8
- v_swmmac_f16_16x16x128_fp8_fp8
- v_swmmac_f32_16x16x128_bf8_bf8
- v_swmmac_f32_16x16x128_bf8_fp8
- v_swmmac_f32_16x16x128_fp8_bf8
- v_swmmac_f32_16x16x128_fp8_fp8
- v_swmmac_i32_16x16x128_iu8

Intrinsics accept anyint, but builtins are defined with i32 argument.

Fixes: SWDEV-579843
DeltaFile
+245-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.index.gfx1250.w32.ll
+21-20clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-wmma-w32.cl
+9-9clang/include/clang/Basic/BuiltinsAMDGPU.td
+12-4llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+11-0clang/test/CodeGenOpenCL/.gdb_history
+8-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+306-356 files

LLVM/project 9f4ed86llvm/test/CodeGen/AMDGPU div_i128.ll, llvm/test/Transforms/ExpandIRInsts/X86 divrem-pow2.ll sdiv129.ll

Addressed review comments:

- Added proofs for power-of-2 div/rem expansion in ExpandIRInsts at
  https://alive2.llvm.org/ce/z/Y-iWm-
- Tests updated as requested.

Also added CreateFreeze() where needed.
DeltaFile
+255-0llvm/test/Transforms/ExpandIRInsts/X86/divrem-pow2.ll
+0-148llvm/test/Transforms/ExpandIRInsts/X86/sdiv129.ll
+0-115llvm/test/Transforms/ExpandIRInsts/X86/srem129.ll
+0-51llvm/test/Transforms/ExpandIRInsts/X86/udiv129.ll
+24-11llvm/test/CodeGen/AMDGPU/div_i128.ll
+0-25llvm/test/Transforms/ExpandIRInsts/X86/urem129.ll
+279-3503 files not shown
+291-3539 files

Linux/linux 582a1eftools/tracing/rtla/sample timerlat_load.py, tools/tracing/rtla/src common.c utils.c

Merge tag 'trace-rtla-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace

Pull RTLA updates from Steven Rostedt:

 - Remove unused function declarations

   Some functions were removed in recent code consolidation 6.18, but
   their prototypes were not removed from headers. Remove them.

 - Set stop threshold after enabling instances

   Prefer recording samples without stopping on them on the start of
   tracing to stopping on samples that are never recorded. This fixes
   flakiness of some RTLA tests and unifies behavior of sample
   collection between tracefs mode and BPF mode.

 - Consolidate usage help message implementation

   RTLA tools (osnoise-top, osnoise-hist, timerlat-top, timerlat-hist)

    [50 lines not shown]
DeltaFile
+139-1tools/tracing/rtla/src/common.c
+65-35tools/tracing/rtla/src/utils.c
+19-71tools/tracing/rtla/src/osnoise_top.c
+17-63tools/tracing/rtla/src/timerlat_top.c
+17-63tools/tracing/rtla/src/timerlat_hist.c
+0-78tools/tracing/rtla/sample/timerlat_load.py
+257-31121 files not shown
+585-43427 files

LLVM/project 7f6368cllvm/lib/Transforms/Scalar LowerMatrixIntrinsics.cpp

formatting

Created using spr 1.3.7
DeltaFile
+2-3llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
+2-31 files

LLVM/project a7224b6llvm/test/Transforms/LowerMatrixIntrinsics select.ll

fix

Created using spr 1.3.7
DeltaFile
+2-2llvm/test/Transforms/LowerMatrixIntrinsics/select.ll
+2-21 files

FreeBSD/ports edf44a2filesystems/moosefs-cgi Makefile, filesystems/moosefs-client pkg-plist

filesystems/moosefs-*: Add new ports MooseFS 4.58.3

MooseFS Distributed Storage – Open Source, Petabyte, Fault-Tolerant,
Highly Performing, Scalable Network Distributed File System /
Software-Defined Storage.

Official site: https://moosefs.com/
Source repository: https://github.com/moosefs/moosefs/
Documentation: https://docs.moosefs.com/

PR:             289966
Co-authored-by: Vladimir Druzenko <vvd at FreeBSD.org>
DeltaFile
+105-71filesystems/moosefs-client/pkg-plist
+56-4filesystems/moosefs-gui/pkg-plist
+20-27filesystems/moosefs-master/Makefile
+30-0filesystems/moosefs-master/files/mfsgui.in
+0-29filesystems/moosefs-master/files/mfscgiserv.in
+15-5filesystems/moosefs-cgi/Makefile
+226-13616 files not shown
+284-18822 files

FreeBSD/ports a5ac15bfilesystems/moosefs-client pkg-plist, filesystems/moosefs-master Makefile

filesystems/moosefs-*: Repocopy from filesystems/moosefs3-*

PR:     289966
DeltaFile
+114-0filesystems/moosefs-master/Makefile
+88-0filesystems/moosefs-client/pkg-plist
+31-0filesystems/moosefs-master/files/mfsmaster.in
+30-0filesystems/moosefs-master/files/mfschunkserver.in
+30-0filesystems/moosefs-master/files/mfsmetalogger.in
+29-0filesystems/moosefs-master/files/mfscgiserv.in
+322-027 files not shown
+564-033 files

LLVM/project e3af9aallvm/lib/Target/RISCV RISCVISelDAGToDAG.cpp

[RISCV] Add isel helper functions for building a GPRPair or extract from a GPRPair. NFC (#181245)

DeltaFile
+32-55llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+32-551 files

LLVM/project 8f1ff22llvm/lib/Transforms/Scalar LowerMatrixIntrinsics.cpp, llvm/test/Transforms/LowerMatrixIntrinsics select.ll

feedback

Created using spr 1.3.7
DeltaFile
+5-4llvm/test/Transforms/LowerMatrixIntrinsics/select.ll
+3-1llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
+8-52 files

LLVM/project 2b2582cllvm/lib/Transforms/Vectorize VPlanUtils.cpp, llvm/test/Transforms/LoopVectorize first-order-recurrence.ll iv_outside_user.ll

[VPlan] Update isUniformAcrossVFsAndUFs to account for sinking.

Recipes can be sunk now. In those cases, the sunk recipes are outside
the loop region, but may not be uniform across VF and UF.

Update the code to only exit early if the recipe is defined before the
region. Without DT available, the easiest way to check is just if it is
in the entry/preheader block.

Fixes https://github.com/llvm/llvm-project/issues/181002.
Fixes https://github.com/llvm/llvm-project/issues/180781.
DeltaFile
+10-6llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+4-3llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
+2-1llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+16-103 files

Linux/linux f75c03aDocumentation/trace/rv monitor_synthesis.rst, include/rv da_monitor.h automata.h

Merge tag 'trace-rv-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace

Pull runtime verifier updates from Steven Rostedt:

 - Refactor da_monitor to minimize macros

   Complete refactor of da_monitor.h to reduce reliance on macros
   generating functions. Use generic static functions and uses the
   preprocessor only when strictly necessary (e.g. for tracepoint
   handlers).

   The change essentially relies on functions with generic names (e.g.
   da_handle) instead of monitor-specific as well adding the need to
   define constant (e.g. MONITOR_NAME, MONITOR_TYPE) before including
   the header rather than calling macros that would define functions.
   Also adapt monitors and documentation accordingly.

 - Cleanup DA code generation scripts


    [34 lines not shown]
DeltaFile
+429-464include/rv/da_monitor.h
+70-64include/rv/automata.h
+38-73tools/verification/rvgen/rvgen/dot2c.py
+21-23Documentation/trace/rv/monitor_synthesis.rst
+19-21kernel/trace/rv/monitors/opid/opid.c
+18-20kernel/trace/rv/monitors/sssw/sssw.c
+595-66525 files not shown
+839-91231 files

LLVM/project b7e1922lld/ELF OutputSections.cpp InputSection.h, lld/test/ELF linkorder-group.test

[lld] Fix undefined behavior with misaligned SHT_GROUP section. (#180848)

read32() allows misaligned values, but a `uint32_t &` must be properly
aligned even if it isn't directly read. ubsan detects this. To fix the
issue, replace the `uint32_t &` with a value that doesn't require
alignment.

Also added an assertion to catch similar misuse of getDataAs().

(Alternatively, we could make the input validation more strict, and
reject files with a misaligned SHT_GROUP, but I don't see any obvious
reason to require that.)
DeltaFile
+2-1lld/test/ELF/linkorder-group.test
+1-1lld/ELF/OutputSections.cpp
+1-0lld/ELF/InputSection.h
+4-23 files

FreeBSD/ports 3f297f8net/ooni-probe-cli distinfo Makefile

net/ooni-probe-cli: update to 3.29.0
DeltaFile
+5-5net/ooni-probe-cli/distinfo
+1-2net/ooni-probe-cli/Makefile
+6-72 files

LLVM/project a002786llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.buffer.load.lds.err.ll llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll

AMDGPU/GlobalISel: Regbanklegalize rules for buffer load lds intrinsics (#180998)

DeltaFile
+13-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.lds.err.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.lds.ll
+23-102 files not shown
+25-128 files

Linux/linux a67594carch/openrisc/boot/dts simple_smp.dts simple-smp.dtsi, arch/openrisc/configs de0_nano_multicore_defconfig de0_nano_defconfig

Merge tag 'for-linus' of https://github.com/openrisc/linux

Pull OpenRISC updates from Stafford Horne:
 "The main focus for this series has been to improve OpenRISC kernel
  out-of-the-box support for FPGA dev boards.

   - Add device tree configurations for De0 Nano single and multicore
     configurations

   - Fix bug in OpenRISC SMP preventing the kernel from running on FPGA
     boards, due to IPIs not being unmasked on secondary CPUs in some
     configurations

   - Pick up a fix from Brian Masney defining the nop() macro to fix
     build failures on OpenRISC for drivers using it"

* tag 'for-linus' of https://github.com/openrisc/linux:
  openrisc: define arch-specific version of nop()
  openrisc: dts: Add de0 nano multicore config and devicetree

    [3 lines not shown]
DeltaFile
+92-0arch/openrisc/configs/de0_nano_multicore_defconfig
+79-0arch/openrisc/configs/de0_nano_defconfig
+0-69arch/openrisc/boot/dts/simple_smp.dts
+68-0arch/openrisc/boot/dts/simple-smp.dtsi
+54-0arch/openrisc/boot/dts/de0-nano.dts
+42-0arch/openrisc/boot/dts/de0-nano-common.dtsi
+335-698 files not shown
+449-7814 files

Linux/linux 8c0901bdrivers/block/rnull configfs.rs, rust/kernel configfs.rs

Merge tag 'configfs-for-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/a.hindborg/linux

Pull configfs updates from Andreas Hindborg:

 - Switch the configfs rust bindings to use c string literals provided
   by the compiler, rather than a macro

 - A follow up on constifying `configfs_item_operations`, applying the
   change to the configfs sample

* tag 'configfs-for-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/a.hindborg/linux:
  samples: configfs: Constify struct configfs_item_operations and configfs_group_operations
  rust: configfs: replace `kernel::c_str!` with C-Strings
DeltaFile
+5-4rust/kernel/configfs.rs
+4-4samples/configfs/configfs_sample.c
+2-3samples/rust/rust_configfs.rs
+0-1drivers/block/rnull/configfs.rs
+11-124 files

FreeBSD/src c779717. RELNOTES

RELNOTES:  Add entry for 8accd4d99f81
DeltaFile
+7-0RELNOTES
+7-01 files

FreeNAS/freenas 9f14aa7src/middlewared/middlewared/alert/source ipmi_sel.py, src/middlewared/middlewared/api/v26_0_0 truenas.py

Name update: is_ix_hardware to is_supported_hardware.
Also updated associated API class names.
DeltaFile
+4-4src/middlewared/middlewared/api/v26_0_0/truenas.py
+2-2src/middlewared/middlewared/plugins/enclosure_/enclosure2.py
+2-2src/middlewared/middlewared/plugins/truenas.py
+1-1src/middlewared/middlewared/pytest/unit/plugins/enclosure/test_enclosure2_query.py
+1-1src/middlewared/middlewared/alert/source/ipmi_sel.py
+1-1src/middlewared/middlewared/plugins/network.py
+11-111 files not shown
+12-127 files

LLVM/project 0338ffcclang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Dialect/Transforms FlattenCFG.cpp

[CIR] Implement flattening for cleanup scopes with multiple exits (#180627)

This implements CFG flattening for cir.cleanup.scope operations where
the scope body has multiple exits that must all branch through the
cleanup region.

This uses the same strategy that Clang uses when generating LLVM IR for
equivalent cases -- a cleanup destination slot is allocated on the
stack, and a value is stored to this slot before each branch to the
cleanup, indicating where control must go after the cleanup is executed.

Substantial amounts of this PR were created using agentic AI tools, but
I have carefully reviewed the code, comments, and tests and made changes
as needed.
DeltaFile
+828-120clang/test/CIR/Transforms/flatten-cleanup-scope-multi-exit.cir
+415-234clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
+33-0clang/test/CIR/Transforms/flatten-cleanup-scope-nyi.cir
+5-0clang/include/clang/CIR/Dialect/IR/CIROps.td
+1-1clang/test/CIR/Transforms/flatten-cleanup-scope-simple.cir
+1,282-3555 files