kern: fix oversight in security.bsd.unprivileged_kenv_read
It was intended that one could close the hole back in loader, but the
sysctl was actually not marked TUNABLE. The hardening menu option thus
did nothing, because we wouldn't read the value from kenv.
Reported by: markj
Fixes: 6e81fbf5833d ("bsdinstall: add a hardening knob [...]")
Fixes: 4fd518fcb2bb ("kern: add a security knob to disable [...]")
[mlir][wasm] Support for saturating FP truncations (#212709)
Add support for saturate truncation of float to int operations.
This also requires the support of parser with sub-opcodes.
This is handled by supporting parser with extra argument for sub-opcode.
---------
Co-authored-by: Ferdinand Lemaire <ferdinand.lemaire at woven-planet.global>
Fix the build under Darwin by not defining -D_POSIX_C_SOURCE
Whatever this Darwin-specific tweak was trying to fix in 2016, the
reverse now seems to be the case - this package will not build on
Darwin with this #define defined, because it confuses malloc.h.
Today, a decade later, it builds fine without this tweak.
[libclc] Add math smoke test for cos special values (#214786)
Summary:
Basic math version of unit tests used to give reference for how these
can test the known special values. SImilar to LLVM libc's smoke math
tests on the GPU. More can be added later,
[libc++] Include range access headers in `<optional>` only since C++26 (#214688)
Inclusions of internal range access headers address LWG4131 which
patches P3168R2 "Give `std::optional` Range Support". As P3168R2 is
certainly a new feature in C++26, these includes are unnecessary in old
modes.
It was reported that these increased the size of `<optional>` by ~8%, so
probably it is better to avoid such cost in old modes.
[NVPTX] Drop cache hints on volatile loads/stores (#214830)
https://github.com/llvm/llvm-project/pull/204067 added cache hint
metadata support for NVPTX. I forgot to handle volatile loads/stores
correctly. Volatile loads only support .level::prefetch_size and
volatile stores don't support any cache hints. This PR drops unsupported
metadata for volatile loads/stores.
[libclc][test] Update cos.cl checks after fneg FP-options fix (#214906)
ceaff22ed2c3 ([Clang][CodeGen] Respect FP pragma options for fneg and
calls) scopes fneg's fast-math flags to the expression's own FPOptions
instead of the ambient IRBuilder state, so one fneg in cos.cl's
generated IR no longer carries contract. Regenerate check.
Co-authored-by: Claude Sonnet 5 <noreply at anthropic.com>
[Driver][KCFI] Forward -fsanitize-kcfi-hash= to cc1 (#214827)
-fsanitize-kcfi-hash= is a CC1Option that selects the hash algorithm
used to derive KCFI type IDs (xxHash64 or FNV-1a), but the driver never
claimed or forwarded it. As a result, invocations like
clang -fsanitize=kcfi -fsanitize-kcfi-hash=FNV-1a foo.c
silently dropped the flag with an "argument unused during compilation"
warning; users had to route it through -Xclang to reach cc1. This is
particularly awkward for build systems (e.g. the Linux kernel) that want
to select FNV-1a for -fsanitize=kcfi builds.
Handle the option in SanitizerArgs alongside -fsanitize-kcfi-arity:
capture the last-specified value when KCFI is enabled and forward it to
cc1 as -fsanitize-kcfi-hash=<value>. Values are still validated by cc1's
tablegen-driven Values<"xxHash64,FNV-1a"> checker, so bad values produce
the usual "invalid value" diagnostic. When -fsanitize=kcfi is not
specified, the flag remains unclaimed and triggers
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[MC] Make pseudo-probe divisions ordering stable (#214803)
**Problem**
`MCPseudoProbeSections::emit` sorts probe divisions only by section
ordinal.
Functions sharing a section will have a nondeterministic `unordered_map`
iteration order, producing *different .pseudo_probe bytes for identical
inputs.*
**Solution**
Use the function symbol name as a stable tie-breaker when section
ordinals match.
Add an MC regression test that reverses pseudo-probe insertion order and
requires byte-identical object files.
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[RISC-V] Use an optional offset operand instead of zero-offset InstAliases
Introduce OptionalMemOffsetAsmOperand, which wraps a memory-offset
operand class into a variant with `IsOptional` set so that a memory
operand written without an offset, e.g. "lb a0, (a1)", parses with a
default offset of 0, and use it for a simm12_lo_optional operand. This
replaces the hand-written "(${rs1})" zero-offset InstAlias that every
load/store-style instruction needed (scalar and FP loads/stores, Zilsd,
jr/jalr and the .insn_i/.insn_s memory forms).
OptionalMemOffsetAsmOperand is somewhat complicated, but this makes it
easier to replace all the other optional zero memory operands which I
will do in follow-up commits, removing all the InstAlias duplication.
This change was assisted by AI.
Pull Request: https://github.com/llvm/llvm-project/pull/210901
[BOLT] Page out .dwo files
Split-DWARF inputs at big binaries scale ship 100+ GiB of .dwo
files. BOLT opened a fair number of them during readDebugInfo, putting
a lot of pressure on the OS memory management: mmap'd reads always
populate the page cache; with every .dwo mapped at once those pages
accumulated, refaulted, and registered as memory pressure that got the
process oomd-killed.
Now, .dwo page-cache pages are reclaimed as soon as BOLT is done with
each file: madvise(MADV_PAGEOUT) on the live mapping, then
posix_fadvise(POSIX_FADV_DONTNEED) once it is unmapped. Controlled by
-drop-dwo-page-cache, OFF by default, as it is unlikely upstream
will be processing gigantic sets of dwo files.
ptrace/procfs: Take lwp lock around process_read/write_(fp)regs(32).
And verify that the lwp is in LSSTOP state before trying to read.
Otherwise, we might catch an lwp while it's still running on the CPU,
with all FPU state active, making the result unstable and tripping
assertions on some architectures.
PR port-amd64/60556: panic in process_read_fpregs_xmm
igc: Disable PCIe L1.2 on I225
I225 devices can incorrectly enter L1 substates while CLKREQ# is
asserted, both while idle and in D3. Disable ASPM and PCI-PM L1.2 on
I225 to prevent the resulting packet loss.
Keep the I226 workaround ASPM-only because it addresses a separate
traffic exit latency observation.
PR: 265714
(cherry picked from commit 4a28d390f5fbae2483e88805559881b04ccf9a80)
ixgbe: clear VF head write-back state on reset
VF reset and FLR do not clear the transmit head write-back address
registers. A previous VF driver can therefore leave DMA write-back
enabled with a stale address for the next driver instance.
After consuming the reset request and disabling the VF queues, clear the
address registers for each queue belonging to that VF. Derive the queue
count from the active IOV mode so peer queue state is not touched.
Linux commit dbf231af81a7 documents the hardware behavior. The FreeBSD
implementation follows the local queue mapping and register interfaces.
(cherry picked from commit 6f940ca879cbf691ddf5605d852770cef27847b2)
ixgbe: dispatch PBA string reads through EEPROM ops
E610 installs a device-specific PBA string reader, but the public API
always calls the generic implementation. Dispatch through the EEPROM
operation table so device overrides are honored.
Initialize the generic operation for devices that use the ordinary
EEPROM representation.
Obtained from: Intel ix 3.4.39
(cherry picked from commit 9cf1aa6e68e4b9dd4a77c67b7b902b9221198e7a)
