LLVM/project cc4b98ellvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 bitcast-vector-bool.ll

[X86] combineSetCC - attempt to match more complex icmp_eq/ne patterns before falling back to PTEST/PMOVMSKB patterns (#180034)

combineVectorSizedSetCCEquality attempts to convert equality comparisons
of larger-than-legal scalar integers to PTEST/PMOVMSKB vector
comparisons.

However, combineSetCC has a number of other folds with more complex
icmp_eq/ne patterns that work with big integers (including bit test and
reduction patterns) that don't get a change to match as
combineVectorSizedSetCCEquality is run first, and the other folds are
then more difficult to match from PTEST/PMOVMSKB nodes.

This patch moves the combineVectorSizedSetCCEquality fold later to give
other icmp_eq/ne folds a chance to run first.
DeltaFile
+30-132llvm/test/CodeGen/X86/bitcast-vector-bool.ll
+4-6llvm/lib/Target/X86/X86ISelLowering.cpp
+34-1382 files

FreeBSD/ports 19b85d9textproc/logseq Makefile

textproc/logseq: Bump port revision after electron38 update (e20b87351d03)
DeltaFile
+1-1textproc/logseq/Makefile
+1-11 files

HardenedBSD/src 97cd80bsys/net if_lagg.c

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+38-21sys/net/if_lagg.c
+38-211 files

HardenedBSD/src 5dbcb0dsys/kern kern_synch.c kern_ktrace.c, sys/sys ktrace.h

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main
DeltaFile
+11-15sys/kern/kern_synch.c
+16-2sys/kern/kern_ktrace.c
+1-0sys/sys/ktrace.h
+28-173 files

HardenedBSD/ports 4f0477adevel Makefile, devel/R-cran-pkgload distinfo

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+16-3x11/slim/Makefile
+3-3devel/R-cran-pkgload/distinfo
+3-3math/octave-forge-llms/distinfo
+3-3math/octave-forge-io/distinfo
+1-1multimedia/navidrome/Makefile
+1-1devel/Makefile
+27-143 files not shown
+30-179 files

FreeBSD/ports e20b873devel/electron38 distinfo, devel/electron38/files patch-electron_spec_api-browser-window-spec.ts

devel/electron38: Update to 38.8.0

Changelog: https://github.com/electron/electron/releases/tag/v38.8.0

Reported by:    GitHub (watch releases)
DeltaFile
+0-942devel/electron38/files/packagejsons/.yarn/releases/yarn-4.11.0.cjs
+942-0devel/electron38/files/packagejsons/.yarn/releases/yarn-4.12.0.cjs
+406-414devel/electron38/files/packagejsons/yarn.lock
+13-13devel/electron38/files/patch-electron_spec_api-browser-window-spec.ts
+9-9devel/electron38/distinfo
+9-5devel/electron38/files/packagejsons/package.json
+1,379-1,3839 files not shown
+1,413-1,39515 files

HardenedBSD/ports 99b7707devel Makefile

devel/Makefile: Fix spago entry after renaming

PR:             292941 292975
Fixes:  d766b804ac192340a2809f069ff309acfe0b064b
DeltaFile
+1-1devel/Makefile
+1-11 files

FreeBSD/ports 99b7707devel Makefile

devel/Makefile: Fix spago entry after renaming

PR:             292941 292975
Fixes:  d766b804ac192340a2809f069ff309acfe0b064b
DeltaFile
+1-1devel/Makefile
+1-11 files

LLVM/project 5ae2ee9llvm/test/CodeGen/AMDGPU load-saddr-offset-imm.ll

[AMDGPU] regenerate test checks
DeltaFile
+3-5llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
+3-51 files

LLVM/project 5f8b905clang/lib/CIR/CodeGen CIRGenCUDANV.cpp

fix nit
DeltaFile
+0-3clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
+0-31 files

LLVM/project d99f1cdllvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rvp-ext-rv32.ll rvp-ext-rv64.ll

[RISCV][llvm] Support INSERT_VECTOR_ELT codegen for P extension (#179471)

Add custom lowering for INSERT_VECTOR_ELT on P extension vector types
using the MVM instruction.

TODO: Handle <4 x i8> on RV64 which is constructed to extract_vector_elt
+ build_vector instead of insert_vector_elt.
DeltaFile
+74-4llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+70-6llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+48-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+10-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+202-114 files

LLVM/project b1274dfllvm/test/CodeGen/AMDGPU load-saddr-offset-imm.ll

Merge branch 'add-test' into opt-global-addr
DeltaFile
+69-38llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
+69-381 files

LLVM/project 22fb226llvm/test/CodeGen/AMDGPU load-saddr-offset-imm.ll

[AMDGPU] Add more tests
DeltaFile
+69-42llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
+69-421 files

LLVM/project 43358cbclang/lib/AST/ByteCode Interp.cpp, clang/test/AST/ByteCode records.cpp

[clang][bytecode] Check pointer lifetime in CheckDestructor (#179957)

So we diagnose double-destroy scenarios.
DeltaFile
+9-0clang/test/AST/ByteCode/records.cpp
+2-0clang/lib/AST/ByteCode/Interp.cpp
+11-02 files

LLVM/project 295b0efclang/lib/Serialization ASTWriter.cpp, clang/test/PCH reloc.c

[C++20][Modules] Fix relocatable PCH feature. (#180023)

DeltaFile
+5-3clang/lib/Serialization/ASTWriter.cpp
+5-0clang/test/PCH/reloc.c
+10-32 files

LLVM/project 4c388b7clang/lib/CIR/CodeGen CIRGenCUDANV.cpp, clang/test/CIR/CodeGenCUDA kernel-call.cu

lit bro
DeltaFile
+2-2clang/test/CIR/CodeGenCUDA/kernel-call.cu
+3-0clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
+5-22 files

LLVM/project d289020llvm/docs LangRef.rst

[LangRef] Correct `uitofp` example (#180123)

The to type is incorrect, use `float` instead.
DeltaFile
+2-2llvm/docs/LangRef.rst
+2-21 files

OPNSense/plugins fe9abadnet/tayga pkg-descr

net/tayga: update website in pkg-descr (new maintainer @apalrd) (#5193)

DeltaFile
+0-2net/tayga/pkg-descr
+0-21 files

LLVM/project f0b371dclang/lib/CIR/CodeGen CIRGenCUDANV.cpp

hip global storage fix and bitcast to match hipLaunchkernel definition
DeltaFile
+3-2clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
+3-21 files

LLVM/project 22c5c25llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoP.td

[RISCV] Reorder the operands for RISCVISD::PPAIRE_DB. NFC (#180111)

Order the operands so the the low and high part of the rs1 regpair are
first, followed by the low and high part of the rs2 regpair.

Also change the type to use v4i8 for the result so that it's only
shuffling elements not combining elements into a larger elment.

I'm planning to add ADDD and SUBD opcodes that will be defined with the
same operand order allowing RISCVISelDAGToDAG.cpp code to be shared.
DeltaFile
+6-6llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+7-5llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+2-2llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+15-133 files

LLVM/project 3fd0464llvm/lib/Transforms/Instrumentation MemorySanitizer.cpp, llvm/test/Instrumentation/MemorySanitizer/AArch64 aarch64-bf16-dotprod-intrinsics.ll aarch64-matmul.ll

[msan] Handle NEON bfmmla (#176264)

This patch adapts handleNEONMatrixMultiply() (used for integer matrix
multiply: smmla/ummla/usmmla) to floating-point (bfmmla).
DeltaFile
+94-44llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+14-19llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll
+2-2llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-matmul.ll
+110-653 files

Linux/linux b7ff715drivers/hwmon acpi_power_meter.c dell-smm-hwmon.c, drivers/hwmon/occ common.c

Merge tag 'hwmon-for-v6.19-final' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging

Pull hwmon fixes from Guenter Roeck:

 - occ: Mark occ_init_attribute() as __printf to avoid build failure due
   to '-Werror=suggest-attribute=format'

 - gpio-fan: Allow to stop fans when CONFIG_PM is disabled, and fix
   set_rpm() return value

 - acpi_power_meter: Fix deadlocks related to acpi_power_meter_notify()

 - dell-smm: Add Dell G15 5510 to fan control whitelist

* tag 'hwmon-for-v6.19-final' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging:
  hwmon: (occ) Mark occ_init_attribute() as __printf
  hwmon: (gpio-fan) Allow to stop FANs when CONFIG_PM is disabled
  hwmon: (gpio-fan) Fix set_rpm() return value
  hwmon: (acpi_power_meter) Fix deadlocks related to acpi_power_meter_notify()
  hwmon: (dell-smm) Add Dell G15 5510 to fan control whitelist
DeltaFile
+14-3drivers/hwmon/acpi_power_meter.c
+8-0drivers/hwmon/dell-smm-hwmon.c
+3-3drivers/hwmon/gpio-fan.c
+1-0drivers/hwmon/occ/common.c
+26-64 files

LLVM/project 3392ec8llvm/lib/Target/NVPTX NVPTXInstrInfo.td, llvm/test/CodeGen/NVPTX fma-relu-contract.ll

[NVPTX] Remove `NoSignedZerosFPMath` uses (#180086)

Users should use `nsz` flag instead.
DeltaFile
+15-15llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
+1-1llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+16-162 files

LLVM/project 2d8ce3alld/test/ELF eh-frame-invalid-fde-encoding.s eh-frame-invalid-cie.s

[ELF][test] Consolidate invalid-eh-frame tests

Merge 9 individual invalid-eh-frame test files into 2 categorized files
using split-file:

- eh-frame-invalid-cie.s: CIE structure errors (too small, unexpected
  end, failed string/LEB128 reads)
- eh-frame-invalid-fde-encoding.s: EhReader::getFdeEncoding errors
  (unknown augmentation string, unknown FDE encoding, unsupported
  aligned encoding, corrupted CIE)
DeltaFile
+122-0lld/test/ELF/eh-frame-invalid-fde-encoding.s
+77-0lld/test/ELF/eh-frame-invalid-cie.s
+0-32lld/test/ELF/invalid-eh-frame6.s
+0-30lld/test/ELF/invalid-eh-frame8.s
+0-30lld/test/ELF/invalid-eh-frame7.s
+0-30lld/test/ELF/invalid-eh-frame4.s
+199-1225 files not shown
+199-22611 files

FreeNAS/freenas 0069986src/middlewared/middlewared/plugins nfs.py smb.py, src/middlewared/middlewared/plugins/cloud_backup crud.py

correct filters
DeltaFile
+1-1src/middlewared/middlewared/plugins/nfs.py
+1-1src/middlewared/middlewared/plugins/nvmet/namespace.py
+1-1src/middlewared/middlewared/plugins/smb.py
+1-0src/middlewared/middlewared/plugins/cloud_backup/crud.py
+4-34 files

HardenedBSD/ports 8e9cbb7multimedia/navidrome Makefile

multimedia/navidrome: Return to pool

This is a useful piece of software but between Go and Node being
grotesque in their own ways I don't enjoy working on this any longer.
DeltaFile
+1-1multimedia/navidrome/Makefile
+1-11 files

FreeBSD/ports 8e9cbb7multimedia/navidrome Makefile

multimedia/navidrome: Return to pool

This is a useful piece of software but between Go and Node being
grotesque in their own ways I don't enjoy working on this any longer.
DeltaFile
+1-1multimedia/navidrome/Makefile
+1-11 files

LLVM/project 7449d32llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine add-shl-mul-umax.ll

[InstCombine][profcheck] Fix profile metadata propagation for umax in InstCombine (#179332)

Select instructions created from the expansion of an umax intrinsic do
not have profile data even though the function may have profile data.
This is because PGO instrumentation does not support intrinsics.

Assisted-by: gemini
DeltaFile
+9-3llvm/test/Transforms/InstCombine/add-shl-mul-umax.ll
+4-2llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+0-1llvm/utils/profcheck-xfail.txt
+13-63 files

LLVM/project c41f956llvm/lib/Transforms/Instrumentation MemorySanitizer.cpp

[msan][NFCI] Generalize handleAVX512VectorGenericMaskedFP (#179850)

handleAVX512VectorGenericMaskedFP() assumes there is one vector of data
(excluding the mask). This patch generalizes it to allow multiple
vectors of data, which we assume will be munged together.

Future work can apply this to intrinsics such as:
```
<16 x float> @llvm.x86.avx512.mask.scalef.ps.512
                    (<16 x float>, <16 x float>, <16 x float>, i16, i32)
                     WriteThru     A             B             Mask Rounding
```
DeltaFile
+59-29llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+59-291 files

LLVM/project e7d1499clang/lib/Basic/Targets PPC.cpp

normalize the CPU name on the target* attribute
DeltaFile
+2-0clang/lib/Basic/Targets/PPC.cpp
+2-01 files