LLVM/project f91a3b1 — bolt/test/X86 dwarf5-debug-names-skip-forward-decl.s

[BOLT,test] Add missing pipe in dwarf5-debug-names-skip-forward-decl.s (#226338)

With cl::Grouping, --check-prefix=POSTCHECK parses as -c -h..., so
llvm-dwarfdump prints --help and exits 0, and the checks never run.
DeltaFile
+1-1bolt/test/X86/dwarf5-debug-names-skip-forward-decl.s
+1-11 files

LLVM/project f119c93 — lldb/source/Interpreter CommandInterpreter.cpp, lldb/test/Shell/ScriptInterpreter/Python nested_command_selected_target.test

[lldb] Use the selected target when the override context is the dummy (#226332)
DeltaFile
+29-0lldb/test/Shell/ScriptInterpreter/Python/nested_command_selected_target.test
+4-1lldb/source/Interpreter/CommandInterpreter.cpp
+33-12 files

LLVM/project 8c237a2 — .github/workflows libcxx-benchmark-commit.yml libcxx-pr-benchmark.yml, .github/workflows/libcxx/build-at-commit action.yml

[libc++] Run the PR benchmarking tooling from main (#226278)

Previously, we'd use the workflow file and machines.json from the main
branch, but the rest of the tools (e.g. build-at-commit) would be taken
from the PR head. This patch switches to using the tools from main and
only using the PR head's content for the actual code and benchmarks.

This should make it easier to evolve the tools and the workflow files
without breaking PR benchmarking for people who submit PRs from slightly
outdated bases.
DeltaFile
+26-9.github/workflows/libcxx-pr-benchmark.yml
+14-4.github/workflows/libcxx/build-at-commit/action.yml
+1-0.github/workflows/libcxx-benchmark-commit.yml
+41-133 files

LLVM/project 4880e16 — llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVFrameLowering.cpp, llvm/test/CodeGen/RISCV sifive-interrupt-attr-err.ll sifive-interrupt-frame-flags.ll

[RISCV] Support frame pointers in SiFive CLIC preemptible handlers (#221318)

This commit adds frame-pointer support for SiFive CLIC preemptible
handlers by using t0 to save mcause and mepc to dedicated stack slots in
both cases.
DeltaFile
+951-0llvm/test/CodeGen/RISCV/sifive-interrupt-frame-pointer.ll
+386-167llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
+93-54llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+17-12llvm/test/CodeGen/RISCV/sifive-interrupt-frame-flags.ll
+0-12llvm/test/CodeGen/RISCV/sifive-interrupt-attr-err.ll
+0-6llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1,447-2511 files not shown
+1,448-2537 files

NextBSD/src df98d94 — tests img-boot-test.sh boot-test.sh

tests: wait for a shell in one block, not two

The previous commit fixed the wrong half. Both tests had a stage that
waited for "login:" and then a stage that handled either a prompt or an
automatic login. I replaced the second -- the one that printed the error I
had seen -- and left the first demanding a prompt.

On an image where automatic login works there is no prompt, so the first
block waited out its full eight minutes and the second never ran. That is
why all four lanes failed on the run against fresh packages, with

    FAIL: 'login:' prompt not seen within 8 minutes

rather than the login rejection from before. The packages were the fix for
the earlier failure -- they carry autologin-user, so admin is now logged in
automatically -- and the test could not cope with its own success.

Splitting the wait from the decision was the mistake: an earlier block
could contradict a later one about what boot looks like. One block now does
both, and the panic check folds into it.
DeltaFile
+13-13tests/boot-test.sh
+10-10tests/img-boot-test.sh
+23-232 files

LLVM/project 138694b — clang/test/CIR/Lowering fastmath-contract.cir

[CIR] Update the fastmath contract lowering test

cir-to-llvm now requires a module triple, and the LLVM dialect prints
fastmath flags as fastmath<contract> rather than an attribute dictionary.

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+5-5clang/test/CIR/Lowering/fastmath-contract.cir
+5-51 files

LLVM/project 11612ad — llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.dot.ll

[AMDGPU][InstCombine] Fold zero dot operands to accumulator

Fold AMDGPU dot intrinsics when either operand is zero.

`dot(a, 0) = 0` and `dot(0, b) = 0`, so replace the intrinsic with its accumulator.
This avoids unrelated clamp and add/sub reassociation cases.
DeltaFile
+15-30llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
+3-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+18-302 files

LLVM/project 3243453 — .github/workflows libcxx-pr-benchmark.yml, libcxx/utils test-at-commit

[libc++] Take the benchmark testing configuration from the test suite (#226267)

Previously, we'd use the testing configuration (the .cfg.in file) from
the checked out test suite for the PR benchmarking, but we'd use the one
from `main` for the historical benchmarking. Since the config file is
logically part of the test suite (just like the rest of the Lit setup),
it makes more sense to take it from the checked-out test suite version.
DeltaFile
+6-6libcxx/utils/ci/lnt/machines.json
+2-2.github/workflows/libcxx-pr-benchmark.yml
+1-2libcxx/utils/test-at-commit
+1-1libcxx/utils/ci/lnt/run-benchmarks
+10-114 files

LLVM/project 5ad5c0a — llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

[SelectionDAG][AMDGPU] Fold mul24 with an AND operand whose low bits are zero

Use SimplifyMultipleUseDemandedBits to simplify AND operands based on the
low 24 bits consumed by mul24.

Fold the multiply to zero when the simplified operand is zero.

This folds cases such as:

  mul24(x & 0xff000000, y) -> 0
DeltaFile
+8-8llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+6-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+5-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+19-113 files

LLVM/project 72dc9bc — llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mul.i24.ll

[AMDGPU] Fold 24 bit multiply with zero low bits

Fold `MUL_I24` and `MUL_U24` to zero when either operand has known zero
low 24 bits.

For example:
```
  llvm.amdgcn.mul.i24(x, 0x01000000) -> 0
```
DeltaFile
+21-33llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+5-0llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+26-332 files

LLVM/project 94d55b3 — llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mul.i24.ll rotl.ll

[SelectionDAG] Handle constants in SimplifyMultipleUseDemandedBits

Replace a non-zero constant with zero when none of its set bits are
demanded.

This allows users of `SimplifyMultipleUseDemandedBits` to eliminate
irrelevant constant bits while preserving the convention that a null
SDValue indicates no simplification.
DeltaFile
+38-45llvm/test/CodeGen/AMDGPU/rotl.ll
+3-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+3-4llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll
+2-4llvm/test/CodeGen/SystemZ/shift-08.ll
+2-4llvm/test/CodeGen/SystemZ/shift-04.ll
+6-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+54-634 files not shown
+58-7110 files

LLVM/project 35f073e — llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.sudot.ll

[AMDGPU] Fold a constant add/sub into the sudot4/sudot8 accumulator (#225322)

Fold a constant add into the accumulator operand of sudot4 and sudot8
when
clamping is disabled:
```
  sudot(a, b, C1, false) + C2 -> sudot(a, b, C1 + C2, false)
```
Subtraction by a constant is canonicalized to addition of its negation.
DeltaFile
+39-19llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+10-20llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
+49-392 files

LLVM/project 9fa7fc2 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIInstrInfo.h, llvm/test/CodeGen/AMDGPU vperm-pk16-exec-hazard.mir llvm.amdgcn.perm.pk.ll

[AMDGPU] Ensure v_perm_pk16 hazard is applied to both gfx1250 and gfx1251.
DeltaFile
+12-14llvm/lib/Target/AMDGPU/SIInstrInfo.h
+4-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-2llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-vperm-pk16.mir
+2-1llvm/test/CodeGen/AMDGPU/vperm-pk16-exec-hazard.ll
+2-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
+1-0llvm/test/CodeGen/AMDGPU/vperm-pk16-exec-hazard.mir
+24-196 files

LLVM/project 7ee53cc — clang/docs/HLSL DynamicResources.md, clang/lib/Sema HLSLExternalSemaSource.cpp HLSLBuiltinTypeDeclBuilder.cpp

[HLSL] Add support for dynamic resources (#221103)

Adds support for dynamic resources, also known as bindless or directly
indexed resources. The design is described in
https://github.com/llvm/wg-hlsl/issues/204.

The change adds:
- The `ResourceDescriptorHeap` and `SamplerDescriptorHeap` global
symbols, which expose the Shader Model 6.6 descriptor heaps.
- Internal `hlsl::__detail::heap_resource_info` and
`hlsl::__detail::heap_sampler_info` types, which are produced by
indexing the corresponding descriptor heap. HLSL resource and sampler
types can be implicitly constructed from these values.
- Constructors that accept the corresponding internal heap info type for
all currently implemented resource classes.
- Clang builtins `__builtin_hlsl_resource_handlefromheap` and
`__builtin_hlsl_resource_counterhandlefromheap` for creating resource
and counter handles from descriptor heap indices.
- Sema validation and return-type handling for the new builtins.

    [8 lines not shown]
DeltaFile
+132-0clang/test/AST/HLSL/DynamicResources-AST.hlsl
+109-0clang/test/CodeGenHLSL/resources/dynamic-resources.hlsl
+81-0clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+52-13clang/lib/Sema/HLSLExternalSemaSource.cpp
+50-0clang/test/SemaHLSL/Resources/dynamic-resources.hlsl
+43-0clang/docs/HLSL/DynamicResources.md
+467-1319 files not shown
+651-1725 files

LLVM/project 6e687f8 — llvm/include/llvm/CodeGen MIRYamlMapping.h, llvm/include/llvm/CodeGen/MIRParser MIParser.h

[MIR][AMDGPU] Serialize register allocation anti-hints (#218073)

This PR adds MIR print and parse support for the register allocation
anti-hints through
a per vreg anti-hints: [ .. ] field in the registers: section. The
printer only emits
the anti-hint registers only when the it is non-empty to keep existing
tests unchanged.
## Stack
PR **2/4**. Depends on #218071. Next: Apply Occupancy-Aware allocation
anti-hints #218074.
DeltaFile
+121-0llvm/test/CodeGen/MIR/AMDGPU/register-allocation-antihints-mir-print-parse.mir
+19-0llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+12-0llvm/lib/CodeGen/MIRPrinter.cpp
+5-0llvm/include/llvm/CodeGen/MIRYamlMapping.h
+1-0llvm/include/llvm/CodeGen/MIRParser/MIParser.h
+158-05 files

LLVM/project bacc5bd — llvm/lib/Target/AMDGPU GCNRegPressure.cpp GCNRegPressure.h

[AMDGPU] Track allocator-reserved register pressure separately

GCNRegPressure counts a tuple at its live lane count, but the excess and
critical limits the scheduler compares against are expressed in
allocatable registers. A tuple is reserved at its full class width for
its whole live range, so lanes that are dead at a given point are still
unavailable to any other value, and the live lane count underestimates
what the allocator has to set aside.

Track a third set of per-kind values recording the reserved width, and
use it for the pressure the GCN trackers hand to the scheduling
heuristics.

Also add -amdgpu-trackers-compare-rp to print the GCN tracker and the
generic tracker pressure side by side for every candidate, which is what
the discrepancy was found with.

WIP

AI-Assisted
DeltaFile
+38-7llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+25-4llvm/lib/Target/AMDGPU/GCNRegPressure.h
+10-1llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+73-123 files

NetBSD/pkgsrc vOq5nVC — graphics/shader-slang Makefile, graphics/shader-slang/patches patch-include_slang.h

   shader-slang: fixed github project name; added missed pathc
VersionDeltaFile
1.1+25-0graphics/shader-slang/patches/patch-include_slang.h
1.2+2-1graphics/shader-slang/Makefile
+27-12 files

LLVM/project feaab8e — llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp GCNSchedStrategy.h

[AMDGPU] Handle AVGPR pressure in a bank-aware manner.

WIP

AI-Assisted
DeltaFile
+33-5llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+23-0llvm/lib/Target/AMDGPU/GCNRegPressure.h
+15-0llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+73-74 files

NetBSD/src GlaHZSd — sys/kern uipc_syscalls.c, sys/sys socketvar.h

   kern: Nix SS_ISABORTING.

   This was a vestige of an earlier revision of the .fo_restart
   mechanism; it is never set by anything in the kernel, it has been
   supplanted by SS_RESTARTSYS, and it serves no further purpose.
VersionDeltaFile
1.217+2-7sys/kern/uipc_syscalls.c
1.172+2-2sys/sys/socketvar.h
+4-92 files

LLVM/project 88710e8 — clang/lib/CIR/CodeGen CIRGenFunction.cpp, clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

[CIR] clang-format the fp-contract changes

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+17-20clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+2-1clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+19-212 files

NetBSD/src 20lNrtR — sys/kern uipc_syscalls.c, tests/kernel t_fdrestart.c

   connect(2): Fix wakeup if the fd is concurrently closed.

   PR kern/57659: closing pipe writefd fails to wake concurrent write on
   same writefd
VersionDeltaFile
1.216+14-4sys/kern/uipc_syscalls.c
1.9+2-5tests/kernel/t_fdrestart.c
+16-92 files

NetBSD/src NAOiXKa — tests/kernel t_fdrestart.c

   t_fdrestart: Test socket connect and accept too.

   The logic for connect, it turns out, is missing .fo_restart tests.

   PR kern/57659: closing pipe writefd fails to wake concurrent write on
   same writefd
VersionDeltaFile
1.8+115-2tests/kernel/t_fdrestart.c
+115-21 files

NetBSD/src OAhWF2m — tests/lib/libc/sys t_sigio.c

   t_sigio: Set SA_SIGINFO|SA_RESTART as originally intended.

   Lost this in a round of refactoring, and it just kinda worked by
   accident, oops!

   PR kern/59056: poll POLLHUP bugs
   PR kern/60782: SIGIO says socket ready for send before send does
   PR kern/60783: tty: missing siginfo_t in SIGIO
   PR kern/60784: pty doesn't deliver SIGIO when writable
   PR kern/60785: fifo delivers SIGIO with wrong si_fd
VersionDeltaFile
1.2+3-2tests/lib/libc/sys/t_sigio.c
+3-21 files

LLVM/project 051daff — clang/docs/analyzer checkers.md, clang/include/clang/StaticAnalyzer/Checkers Checkers.td

[WebKit Checkers] Add alpha.webkit.UnborrowedLambdaCapturesChecker (#226288)

Like alpha.webkit.UnborrowedLocalVarsChecker, but for lambda captures.

This checker is pretty restrictive because, unlike a refcounted object,
a lifetime-dependent pointer/reference/view cannot be captured in an
escaping closure at all. Still, we permit capturing in a NOESCAPE
closure.
DeltaFile
+197-0clang/test/Analysis/Checkers/WebKit/unborrowed-lambda-captures.cpp
+80-8clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
+34-0clang/docs/analyzer/checkers.md
+32-0clang/test/Analysis/Checkers/WebKit/mock-canborrow.h
+8-2clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefSafetyModel.cpp
+4-0clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
+355-106 files

LLVM/project 97d1d14 — clang/include/clang/CIR/Dialect/Builder CIRBaseBuilder.h, clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR] Record -ffp-contract=fast as a per-op contract flag

Classic CodeGen stamps contract on floating-point instructions so a later
Standard-fusion backend can still form an FMA. CIR only fused within a
statement via cir.fmuladd, which dropped FFMA on the CUDA device default.

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+138-0clang/test/CIR/CodeGen/fp-contract-fast.c
+86-18clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+54-17clang/include/clang/CIR/Dialect/IR/CIROps.td
+57-0clang/test/CIR/CodeGenCUDA/fp-contract.cu
+47-0clang/test/CIR/Lowering/fastmath-contract.cir
+30-8clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
+412-439 files not shown
+527-6615 files

LLVM/project dd3534f — clang/lib/DependencyScanning DependencyScanningWorker.cpp, clang/test/ClangScanDeps modules-relocated-mm-macro.c build-session-validation-relocated-modules.c

[clang][DepScan] Disable relocation checks (#225563)

This internally broke an incremental build. Disable while it gets
investigated.

This is partial revert of cf8597bd3b87 
resolves: rdar://188026923
DeltaFile
+0-71clang/test/ClangScanDeps/build-session-validation-relocated-modules.c
+9-6clang/test/ClangScanDeps/modules-relocated-mm-macro.c
+3-0clang/lib/DependencyScanning/DependencyScanningWorker.cpp
+12-773 files

LLVM/project 6df97aa — clang/include/clang/CIR/Dialect/Builder CIRBaseBuilder.h, clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR] Record -ffp-contract=fast as a per-op contract flag

Classic CodeGen stamps contract on floating-point instructions so a later
Standard-fusion backend can still form an FMA. CIR only fused within a
statement via cir.fmuladd, which dropped FFMA on the CUDA device default.

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+138-0clang/test/CIR/CodeGen/fp-contract-fast.c
+86-17clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+54-17clang/include/clang/CIR/Dialect/IR/CIROps.td
+57-0clang/test/CIR/CodeGenCUDA/fp-contract.cu
+47-0clang/test/CIR/Lowering/fastmath-contract.cir
+30-8clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
+412-429 files not shown
+527-6615 files

FreeBSD/ports 42fc9f6 — devel/ghgrab Makefile Makefile.crates

devel/ghgrab: Update to 2.1.0
DeltaFile
+63-5devel/ghgrab/distinfo
+30-1devel/ghgrab/Makefile.crates
+1-2devel/ghgrab/Makefile
+94-83 files

FreeBSD/ports d3c362c — sysutils/usermin Makefile distinfo

sysutils/usermin: Update to 2.570
DeltaFile
+22-25sysutils/usermin/pkg-plist
+3-3sysutils/usermin/distinfo
+1-1sysutils/usermin/Makefile
+26-293 files

FreeBSD/ports 5703a61 — sysutils/webmin Makefile distinfo

sysutils/webmin: Update to 2.670
DeltaFile
+108-154sysutils/webmin/pkg-plist
+3-3sysutils/webmin/distinfo
+1-1sysutils/webmin/Makefile
+112-1583 files