LLVM/project 841d4adclang/test/OpenMP distribute_parallel_for_simd_num_threads_codegen.cpp teams_distribute_parallel_for_simd_if_codegen.cpp

[Clang][OpenMP] Don't mark outlined parallel region functions norecurse (#218862)

Clang marks every outlined OpenMP region function `norecurse`, in both
`emitOutlinedFunctionPrologue` and
`emitOutlinedFunctionPrologueAggregate`, and
does the same for the GPU parallel wrapper. For a `parallel` region that
is not
true: the body is reached through the function pointer the runtime is
handed, and
if the body opens another parallel region the runtime's parallel entry
is
re-entered while the first call is still live, so the entry and the body
sit in a
call graph cycle. `rpo-function-attrs` propagates the annotation off the
body and
onto the device runtime's parallel entry once internalization makes it
internal,
and a nested parallel region can then be folded away.


    [18 lines not shown]
DeltaFile
+588-588clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+568-568clang/test/OpenMP/teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+455-455clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
+449-449clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
+445-445clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
+357-357clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp
+2,862-2,862111 files not shown
+5,039-5,134117 files

LLVM/project 1b59b61llvm/lib/CodeGen RegisterCoalescer.cpp, llvm/test/CodeGen/AArch64 coalescer-empty-subrange-early-lis.ll

RegisterCoalescer: Remove empty subranges after merging subranges

Merging subranges in joinVirtRegs didn't try to clear empty ranges after
refineSubRanges, manifesting in an assert in overlaps checks later.

Exposed with subregister liveness once LiveIntervals runs before TwoAddress.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+30-0llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
+3-0llvm/lib/CodeGen/RegisterCoalescer.cpp
+33-02 files

LLVM/project 5d53653clang/include/clang/Options FlangOptions.td, flang/docs ReleaseNotes.md

[flang] Enable FP sum reassociation by default (#218746)

Enable Fortran-standard-compliant reassociation within individual REAL
and COMPLEX sum expressions by default at all optimisation levels.
Preserve the explicit positive and negative Flang override flags.

Also enable by default on bbc to match flang.

RFC:
https://discourse.llvm.org/t/rfc-flang-reasssociate-within-real-and-complex-expressions-by-default/91626

Assisted-by: Codex
DeltaFile
+6-6flang/test/Lower/math-lowering/exponentiation.f90
+6-3flang/test/Lower/split-sum-expression-tree-lowering.f90
+7-0flang/tools/bbc/bbc.cpp
+3-2clang/include/clang/Options/FlangOptions.td
+5-0flang/docs/ReleaseNotes.md
+2-0flang/test/Driver/driver-help.f90
+29-111 files not shown
+30-127 files

LLVM/project 6e1cb51llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp

[GlobalISel] Drop redundant scalable-dest check in G_EXTRACT_SUBVECTOR lowering (NFC) (#221934)

The scalarizing lowering of G_EXTRACT_SUBVECTOR bails out for both a
scalable source and a scalable destination.
According to llvm/docs/GlobalISel/GenericOpcode.md, G_EXTRACT_SUBVECTOR
only supports extracting a fixed vector from a scalable vector, never a
scalable vector from a fixed one.
This means that a fixed source implies a fixed destination, making the
DstTy.isScalable() check redundant.

Remove it. NFC.
DeltaFile
+1-1llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+1-11 files

LLVM/project 16bcb27mlir/include/mlir/ExecutionEngine/SparseTensor File.h, mlir/test/Integration/Dialect/SparseTensor/CPU sparse_file_coordinates.mlir

[mlir][sparse] Reject invalid tensor coordinates (#220708)
DeltaFile
+79-0mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_file_coordinates.mlir
+32-1mlir/include/mlir/ExecutionEngine/SparseTensor/File.h
+4-0mlir/test/Integration/data/coordinate_zero.tns
+4-0mlir/test/Integration/data/coordinate_narrow.tns
+4-0mlir/test/Integration/data/coordinate_negative.tns
+4-0mlir/test/Integration/data/coordinate_overflow.tns
+127-11 files not shown
+131-17 files

LLVM/project 098c15fclang/lib/Headers riscv_packed_simd.h, clang/test/CodeGen/RISCV rvp-intrinsics.c

[RISCV][P-ext] Support Packed Element Extract (#221565)

See also
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-element-extract.
DeltaFile
+182-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+76-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+29-0clang/test/Sema/riscv-pget-index-out-of-range.c
+24-0clang/lib/Headers/riscv_packed_simd.h
+311-04 files

LLVM/project 793137bmlir/include/mlir/ExecutionEngine/SparseTensor File.h, mlir/lib/ExecutionEngine/SparseTensor File.cpp

[mlir][sparse] Reject tensor files with unsupported ranks (#220709)
DeltaFile
+44-0mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_file_rank.mlir
+7-0mlir/lib/ExecutionEngine/SparseTensor/File.cpp
+2-1mlir/include/mlir/ExecutionEngine/SparseTensor/File.h
+3-0mlir/test/Integration/data/rank_511.tns
+56-14 files

OPNSense/core 640ada5src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes JsonAuditField.php

mvc: can't help it

(cherry picked from commit 7aa4c5f0207fe7aeb6833f58f91544a06bf4ea17)
DeltaFile
+1-1src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes/JsonAuditField.php
+1-11 files

OPNSense/core 7aa4c5fsrc/opnsense/mvc/app/models/OPNsense/Base/FieldTypes JsonAuditField.php

mvc: can't help it
DeltaFile
+1-1src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes/JsonAuditField.php
+1-11 files

LLVM/project 67b8998llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-proper-value-replacement.ll

[AMDGPU] Avoid dangling SSAUpdater reference in PromoteAlloca full-vector store (#215686)

promoteAllocaToVector walks alloca users in use-list order across
blocks. A full-vector store forwards its value operand to the
SSAUpdater, and that operand can be a load from the same alloca in a
dominating block. If the store is visited first, the SSAUpdater holds a
raw pointer to the load; the load is later RAUW'd and deleted, leaving a
dangling reference that causes a crash.

Fix by sorting blocks in reverse post-order before visiting them, so a
forwarded load is always replaced before any store hands it to the
SSAUpdater.

Assisted-By: Cursor (Claude)

---------

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+34-0llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll
+14-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+48-32 files

LLVM/project 6dd2291llvm/lib/Target/AMDGPU GCNDPPCombine.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU dpp_combine.mir dpp_combine_gfx11.mir

[AMDGPU] Restrict DPP combine from performing bad transformations when handling certain REV insts that use Src1 as the DPP operand (#216835)

This issue was originally discovered due to a benchmark failure in the
downstream. The REV subtractions have always worked this way, and the
REV shift operands worked this way before GFX11
DeltaFile
+1,503-0llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll
+183-0llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.mir
+37-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+19-11llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
+10-7llvm/test/CodeGen/AMDGPU/dpp_combine.mir
+12-0llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+1,764-181 files not shown
+1,775-187 files

LLVM/project 4f22c50clang/test/Sema assign.c

Add a regression test; NFC (#221981)

There was a request for a regression test in #50193; this was fixed
initially by 9eef4d1c5fa6b1bcbbe675c14ca8301d5d346f7b
DeltaFile
+7-0clang/test/Sema/assign.c
+7-01 files

LLVM/project 5561afbllvm/lib/ExecutionEngine/Orc/Shared CMakeLists.txt

[LLVM] Add missing link library `TargetParser` to `LLVMOrcShared`

When building with shared libraries, I've got:

```
/usr/bin/ld:
lib/ExecutionEngine/Orc/Shared/CMakeFiles/LLVMOrcShared.dir/Mangler.cpp.o:
in function `llvm::orc::Mangler::fromTriple(llvm::Triple const&,
llvm::StringRef)':
/llvm/lib/ExecutionEngine/Orc/Shared/Mangler.cpp:50:
undefined reference to
`llvm::Triple::computeDataLayout[abi:cxx11](llvm::StringRef) const'
```
DeltaFile
+1-0llvm/lib/ExecutionEngine/Orc/Shared/CMakeLists.txt
+1-01 files

LLVM/project 86a649amlir/lib/Dialect/Linalg/Transforms TilingInterfaceImpl.cpp

[MLIR][linalg] Share external interface implementations to reduce build time (NFC) (#221814)

The Linalg tiling and partial-reduction external models instantiate
their operation-independent implementations for every registered
structured op. Keep thin operation-specific external models, but inherit
the implementations from non-template bases so the compiler emits and
optimizes them only once.

Assisted-by: Codex
DeltaFile
+87-34mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
+87-341 files

LLVM/project f0bcda3mlir/lib/Dialect/Linalg/IR LinalgOps.cpp, mlir/test/Dialect/Linalg/elementwise roundtrip.mlir

[MLIR][linalg] Handle invalid elementwise kind safely (#221835)

The generic elementwise builder accepts an attribute list. Avoid passing
an uninitialized kind to region construction if a caller omits the
required kind, and reject attributes of the wrong type rather than
relying on an assertion.

Found by Coverity.

Assisted-by: Codex
DeltaFile
+18-0mlir/test/lib/Dialect/Linalg/TestLinalgElementwiseFusion.cpp
+13-3mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+3-0mlir/test/Dialect/Linalg/elementwise/roundtrip.mlir
+34-33 files

LLVM/project 91ee3ddllvm/include/llvm/Transforms/Vectorize/SandboxVectorizer Scheduler.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer Scheduler.cpp

[SandboxVec][Scheduler][NFC] Rename ScheduleTopItOpt to ScheduleFrontier (#220409)

We now have an actual class `SchedulingPoint` for pointing to the top of
schedule, so it is no longer an iteraterator as `ScheduleTopItOpt` would
imply. We also support both bottom-up and top-down directions so "Top"
is no longer a good name.

This patch renames the iterator to ScheduleFrontier.
DeltaFile
+22-21llvm/lib/Transforms/Vectorize/SandboxVectorizer/Scheduler.cpp
+3-3llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Scheduler.h
+25-242 files

LLVM/project 8b824bbllvm/lib/CodeGen/GlobalISel IRTranslator.cpp, llvm/lib/IR IRBuilder.cpp

[IRBuilder][GlobalISel] Add byte ptr cast support in IRBuilder

Fix handling of byte-ptr casts in CreateBitPreservingCastChain.
Add G_BITCAST lowering in IRTranslator, emit G_INTTOPTR / G_PTRTOINT
if the type shape does not match.
DeltaFile
+122-0llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-byte-ptr-bitcast.ll
+86-1llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
+44-10llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+16-6llvm/lib/IR/IRBuilder.cpp
+8-11llvm/test/CodeGen/AMDGPU/promote-alloca-byte-ptr-cast.ll
+6-3llvm/unittests/IR/IRBuilderTest.cpp
+282-316 files

LLVM/project d34b9a8llvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/CodeGen MachineVerifier.cpp MachineBasicBlock.cpp

[CodeGen] Add const MBB overload to analyzeBranch (#221847)
DeltaFile
+8-8llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+13-0llvm/include/llvm/CodeGen/TargetInstrInfo.h
+3-4llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+2-3llvm/lib/CodeGen/MachineVerifier.cpp
+2-3llvm/lib/CodeGen/MachineBasicBlock.cpp
+2-0llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+30-186 files

FreeBSD/ports 44dc35bdevel/libvirt Makefile, devel/libvirt/files libvirtd.in

devel/libvirt: run virt-host-validate in rc script

Update the libvirtd rc script to run virt-host-validate(1)
before running libvirtd(8). This command provides information
about possibly missing kernel modules required for certain
features of libvirtd. Errors and warnings from this tool do not
prevent libvirtd(8) from starting as most of the features
are optional.

Suggested by:   arrowd
Reviewed by:    arrowd
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D59490
DeltaFile
+19-0devel/libvirt/files/libvirtd.in
+1-0devel/libvirt/Makefile
+20-02 files

FreeNAS/freenas 97fe85esrc/middlewared/middlewared/alert/source ipmi_sel.py, src/middlewared/middlewared/pytest/unit/alert/source test_ipmi_sel.py

Remove correctable ECC memory errors from `IPMISELAlert`, and raise a separate error if there were more than 10 in the last 24 hours
DeltaFile
+62-0src/middlewared/middlewared/pytest/unit/alert/source/test_ipmi_sel.py
+49-2src/middlewared/middlewared/alert/source/ipmi_sel.py
+111-22 files

LLVM/project b674d2cclang/include/clang/Options Options.td, clang/lib/Driver/ToolChains ZOS.cpp

[Driver][Clang] Add -nodefaultrtlibs (#219496)

On z/OS testing compiler-rt does not work with the -nodefaultlibs since
that option remove both the standard libraries like libc and the
compiler-rt library. On other platforms adding an argument like `-lc`
back to the command line in the test scripts works because the path for
libc (eg. `-L<path>`) hadn't been removed. On z/OS, the standard
libraries are located in data sets and you need to specify them by
complete name (eg. `<HLQ>.SCEELIB(CELQS003)`).

This is adding the option `-nodefaultrtlibs` so the compiler-rt tests
can remove just the compiler-rt libs from the link step.
DeltaFile
+6-0clang/test/Driver/nodefaultrtlibs.c
+2-1clang/lib/Driver/ToolChains/ZOS.cpp
+2-0clang/include/clang/Options/Options.td
+10-13 files

FreeNAS/freenas dd5b983src/middlewared/middlewared/plugins rsync.py, src/middlewared/middlewared/plugins/rsync_ utils.py

Fix rsync extra arguments quoting
DeltaFile
+56-0src/middlewared/middlewared/pytest/unit/plugins/test_rsync_extra_args.py
+21-0tests/api2/test_rsync_ssh_authentication.py
+12-0src/middlewared/middlewared/plugins/rsync_/utils.py
+2-2src/middlewared/middlewared/plugins/rsync.py
+91-24 files

LLVM/project 443d419lldb/source/Plugins/ObjectFile/COFF ObjectFileCOFF.cpp

[lldb] Fix switch case for i386 in COFF GetModuleSpecifications (#222030)

08c94c0ac3b503dd4971da8935001aba01918688 / #188276 accidentally removed
the "case:" for i386.
DeltaFile
+1-0lldb/source/Plugins/ObjectFile/COFF/ObjectFileCOFF.cpp
+1-01 files

LLVM/project 00a81e0flang/include/flang/Optimizer/HLFIR Passes.td, flang/include/flang/Tools CrossToolHelpers.h

[flang][cuda] Inline scalar-to-array assignments in CUDA Fortran device code at -O0 (#221333)

At -O0, `arr = 11` lowers to a `_FortranAAssign` call. In device code
the runtime function's callees join the kernel's call graph, so the
device linker reserves a worst-case stack frame for every kernel
reaching it: `65,720` bytes per thread for a kernel with one such
assignment, versus `0` at -O1.

`InlineHLFIRAssign` already runs at -O0 with `onlyScalarRHS` for OpenMP
target device compilations. This extends that carve-out to CUDA Fortran.
Since a CUDA Fortran module holds both host and device code, the
decision is per-operation via `cuf::isCUDADeviceContext`, and host code
keeps the runtime call.

Only scalar-to-array broadcast is covered.
DeltaFile
+42-3flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
+44-0flang/test/Lower/CUDA/scalar-to-array-assign-device-O0.cuf
+11-5flang/include/flang/Optimizer/HLFIR/Passes.td
+8-0flang/lib/Optimizer/Passes/Pipelines.cpp
+5-0flang/lib/Frontend/FrontendActions.cpp
+1-0flang/include/flang/Tools/CrossToolHelpers.h
+111-86 files

LLVM/project 3c41e75llvm/lib/TargetParser AMDGPUTargetParser.cpp

brbr
DeltaFile
+2-1llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+2-11 files

LLVM/project b12d510clang/docs ReleaseNotes.md, clang/lib/Sema SemaChecking.cpp

[Clang] Fix assertion when a Unicode character is splatted to a vector of its own type (#219987)

Fixes #202317

Comparing an `ext_vector_type` of `char32_t` against one of its own
elements (`V.xyzw < V.x`) splats the scalar to the vector type, and
`-Wconversion` checking then trips `Source != Target` in
`DiagnoseMixedUnicodeImplicitConversion`. `CheckImplicitConversion` does
reject `Source == Target` at the top, but only on the outer types; when
it later strips the vector wrapper off the target it ends up with
`char32_t` on both sides and nothing re-checks that. Every other element
check just happened to tolerate identical types silently, the Unicode
one is the first to assert, which is why this only showed up as a Clang
21 regression.

The fix is at the call site rather than in the diagnostic: once the
vector, matrix and SVE wrappers have been stripped, return early if the
element types are the same. That covers matrix splats and HLSL
truncation to the same element type too, not just this one warning, and

    [5 lines not shown]
DeltaFile
+19-0clang/test/SemaCXX/warn-implicit-unicode-conversions.cpp
+5-0clang/lib/Sema/SemaChecking.cpp
+1-0clang/docs/ReleaseNotes.md
+25-03 files

LLVM/project cedc3abllvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp, llvm/test/tools/llvm-objdump/ELF/AMDGPU kd-cov5.s kd-vgpr.s

Address review comments
DeltaFile
+8-8llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
+6-6llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s
+6-6llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s
+6-6llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx90a.s
+1-5llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+3-3llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
+30-345 files not shown
+38-4211 files

LLVM/project 33b76b8llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp AMDGPUBaseInfo.h

Remove unused two-arg getNumExtraSGPRs overload
DeltaFile
+0-6llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+0-5llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+0-112 files

LLVM/project c706702clang/test/Driver amdgpu-assembler-xnack-sramecc.s, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

maintain cc1 behavior
DeltaFile
+24-29clang/test/Driver/amdgpu-assembler-xnack-sramecc.s
+44-8llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+5-19llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+8-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+81-564 files

LLVM/project e6a386dclang/test/Driver amdgpu-assembler-xnack-sramecc.s, lld/test/ELF amdgpu-tid.s

AMDGPU: Remove xnack and sramecc subtarget features

Now that these are controlled by module flags, the subtarget
features were just used for assembler and disassembler controls.
Now that the assembler and disassembler can infer these from
the e_flags and target directives, they are no longer necessary.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+26-70llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+38-24llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
+44-14llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
+29-24clang/test/Driver/amdgpu-assembler-xnack-sramecc.s
+30-14lld/test/ELF/amdgpu-tid.s
+30-8llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+197-15423 files not shown
+317-26229 files