LLVM/project 2196957mlir/lib/Dialect/Arith/Transforms ExpandOps.cpp, mlir/test/Dialect/Arith expand-flush-denormals.mlir

address comments
DeltaFile
+16-31mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
+15-27mlir/test/Dialect/Arith/expand-flush-denormals.mlir
+31-582 files

LLVM/project 649143cmlir/include/mlir/Dialect/Arith/Transforms Passes.td Passes.h, mlir/lib/Dialect/Arith/Transforms ExpandOps.cpp

[mlir][arith] Add support for `arith.flush_denormals` emulation
DeltaFile
+121-0mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
+108-0mlir/test/Dialect/Arith/expand-flush-denormals.mlir
+15-0mlir/include/mlir/Dialect/Arith/Transforms/Passes.td
+5-0mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
+249-04 files

LLVM/project 744279bmlir/include/mlir/Dialect/Arith/IR ArithOps.td, mlir/lib/Conversion/ArithAndMathToAPFloat ArithToAPFloat.cpp

[mlir][arith] Add `arith.flush_denormals` operation (#192641)

Add a new `arith.flush_denormals` operation. The operation takes a
floating-point value as input and returns zero if the value is denormal.
If the input is not denormal, the operation passes through the input.
This commit also adds support to the `ArithToAPFloat` infrastructure.

Running example:
```mlir
%flush_a = arith.flush_denormals %a : f32
%flush_b = arith.flush_denormals %b : f32
%res = arith.addf %flush_a, %flush_b : f32
%flush_res = arith.flush_denormals %res : f32
```

The exact lowering path depends on the backend and is not implemented as
part of this PR:
- Per-instruction mode. E.g., on NVIDIA architectures, the above example
can lower to `add.ftz.f32 dest, a, b`.

    [11 lines not shown]
DeltaFile
+39-0mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+23-13mlir/lib/Conversion/ArithAndMathToAPFloat/ArithToAPFloat.cpp
+32-0mlir/test/Dialect/Arith/ops.mlir
+26-0mlir/test/Conversion/ArithAndMathToAPFloat/arith-to-apfloat.mlir
+23-0mlir/test/Dialect/Arith/canonicalize.mlir
+22-0mlir/lib/Dialect/Arith/IR/ArithOps.cpp
+165-132 files not shown
+195-138 files

FreeBSD/ports 4ad93ednet-im/ejabberd distinfo Makefile

net-im/ejabberd: Update ejabberd to 26.04

MFH:            2026Q2
Security:       82064ab5-3d76-11f1-89ab-901b0e9408dc
(cherry picked from commit d35a21ccf786b7174bb82f48a4be381560751fcc)
DeltaFile
+7-7net-im/ejabberd/distinfo
+4-7net-im/ejabberd/Makefile
+1-1net-im/ejabberd/pkg-plist
+12-153 files

FreeBSD/ports 8ff2117net-im/ejabberd Makefile

net-im/ejabberd: Unbreak on FreeBSD 13.x

Reported by:    pkg-fallout

(cherry picked from commit 541994f5a2faf827c21cad3335780c508cbf26e7)
DeltaFile
+1-0net-im/ejabberd/Makefile
+1-01 files

FreeBSD/ports b307a6dnet-im/ejabberd distinfo Makefile, net-im/ejabberd/files patch-Makefile.in patch-ejabberdctl.template

net-im/ejabberd: Update to 23.06

- Add dependency on unzip
- Remove unneeded dependencies
- Handle FULLXML option which was missed
- Disable MAKE_JOBS

(cherry picked from commit 53c923abe0474df8895e68638777398ffea2dc3c)
DeltaFile
+41-41net-im/ejabberd/distinfo
+37-25net-im/ejabberd/Makefile
+15-15net-im/ejabberd/files/patch-Makefile.in
+8-8net-im/ejabberd/files/patch-ejabberdctl.template
+7-7net-im/ejabberd/files/patch-deps_jiffy_c__src_double-conversion_strtod.cc
+6-7net-im/ejabberd/pkg-plist
+114-1036 files

LLVM/project 95c5836llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU minimumnum.ll maximumnum.ll

[AMDGPU] Add legalizer rule support for AMDGPU's regbank fminimumnum and fmaximumnum (#192719)

Part of #192497
DeltaFile
+51-24llvm/test/CodeGen/AMDGPU/minimumnum.ll
+51-24llvm/test/CodeGen/AMDGPU/maximumnum.ll
+2-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+104-493 files

FreeBSD/ports d35a21cnet-im/ejabberd distinfo Makefile

net-im/ejabberd: Update ejabberd to 26.04

MFH:            2026Q2
Security:       82064ab5-3d76-11f1-89ab-901b0e9408dc
DeltaFile
+7-7net-im/ejabberd/distinfo
+4-7net-im/ejabberd/Makefile
+1-1net-im/ejabberd/pkg-plist
+12-153 files

FreeBSD/ports 1ff7aecsecurity/vuxml/vuln 2026.xml

security/vuxml: Document ejabberd vulnerability
DeltaFile
+30-0security/vuxml/vuln/2026.xml
+30-01 files

LLVM/project 60af5a9libsycl/include/sycl/__impl queue.hpp, libsycl/include/sycl/__impl/detail arg_wrapper.hpp

fix merge errors

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+0-135libsycl/include/sycl/__impl/detail/arg_wrapper.hpp
+0-43libsycl/include/sycl/__impl/queue.hpp
+0-1782 files

LLVM/project c5f5458clang-tools-extra/clang-tidy/readability IdentifierLengthCheck.cpp

Revert "[clang-tidy][NFC] add numeric include for transform_reduce (#193165)"

This reverts commit 3db991b5c287617cedfdb5b2aa5b4cfdd1173a1c.
DeltaFile
+0-1clang-tools-extra/clang-tidy/readability/IdentifierLengthCheck.cpp
+0-11 files

LLVM/project 36836e6clang-tools-extra/clang-tidy/readability IdentifierLengthCheck.cpp IdentifierLengthCheck.h, clang-tools-extra/docs ReleaseNotes.rst

Revert "Revert "[clang-tidy][readability-identifier-length] Add a line count …"

This reverts commit b3647eb0830f62c1ba0fe94dc9f325b7a205d7fd.
DeltaFile
+85-0clang-tools-extra/test/clang-tidy/checkers/readability/identifier-length-line-count-threshold.cpp
+55-1clang-tools-extra/clang-tidy/readability/IdentifierLengthCheck.cpp
+18-0clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.rst
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+2-0clang-tools-extra/clang-tidy/readability/IdentifierLengthCheck.h
+165-15 files

LLVM/project a1dfc8dmlir/include/mlir/Transforms GreedyPatternRewriteDriver.h CSE.h, mlir/lib/Dialect/Transform/IR TransformOps.cpp

[mlir] Add option to run CSE between greedy rewriter iterations (#193081)

The greedy pattern rewrite driver previously only deduplicated constant
ops between iterations (via the operation folder). Structurally
identical non-constant subexpressions remained distinct SSA values,
blocking fold patterns that only fire when operands match. Reaching the
true fixpoint required chaining an external `cse,canonicalize,...`
pipeline.

Add an opt-in `cseBetweenIterations` flag on `GreedyRewriteConfig` that
runs full CSE on the scoped region after each pattern-application
iteration, and surface it as a `cse-between-iterations` option on the
canonicalizer pass. Off by default to preserve existing performance
characteristics.

Assisted-by: Claude Code
DeltaFile
+435-0mlir/lib/Transforms/Utils/CSE.cpp
+12-401mlir/lib/Transforms/CSE.cpp
+81-0mlir/test/Transforms/canonicalize-cse-between-iterations.mlir
+22-26mlir/lib/Dialect/Transform/IR/TransformOps.cpp
+24-0mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
+17-1mlir/include/mlir/Transforms/CSE.h
+591-4286 files not shown
+615-43112 files

FreeBSD/ports d8eaba1math/py-lrcalc distinfo Makefile

math/py-lrcalc: avoid distfile conflict with math/lrcalc

PR:             294681
Reported by:    Hiroo Ono
DeltaFile
+3-3math/py-lrcalc/distinfo
+1-0math/py-lrcalc/Makefile
+4-32 files

FreeBSD/ports f61e01emath/py-lrcalc pkg-plist Makefile

math/py-lrcalc: switch to pep517
DeltaFile
+7-0math/py-lrcalc/pkg-plist
+3-3math/py-lrcalc/Makefile
+10-32 files

LLVM/project ed34ee3mlir/include/mlir/Transforms GreedyPatternRewriteDriver.h, mlir/lib/Transforms/Utils GreedyPatternRewriteDriver.cpp

[mlir] Assert region is within config scope in RegionPatternRewriteDriver (#193177)

Assisted-by: Claude Code
DeltaFile
+11-1mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
+7-2mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
+18-32 files

LLVM/project 797fc5dllvm/test/CodeGen/AMDGPU idot4u.ll idot2.ll

[AMDGPU] Prefer mul24 over mad24 on SDWA targets (#193033)

If either of a mul24's operands can potentially fold into a SDWA
pattern, then don't fold into a mad24 node (which doesn't have SDWA
variants).

Fixes regressions I first noticed in #162242 - but turns out its an
older problem
DeltaFile
+256-360llvm/test/CodeGen/AMDGPU/idot4u.ll
+134-230llvm/test/CodeGen/AMDGPU/idot2.ll
+136-199llvm/test/CodeGen/AMDGPU/idot4s.ll
+94-115llvm/test/CodeGen/AMDGPU/idot8u.ll
+73-93llvm/test/CodeGen/AMDGPU/idot8s.ll
+32-56llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
+725-1,0533 files not shown
+764-1,0559 files

LLVM/project 78cb9fbllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[DAG] Add Srl combine for extracting last element of BUILD_VECTOR (#181412)

While working on another combine, I noticed some redundant zext shift
pairs `v_lshrrev_b32 + v_lshlrev_b32` coming from a `build_vector(undef,
x)` created by `TargetLowering::SimplifyDemandedBits` and a `srl`
created by `lowerEXTRACT_VECTOR_ELT`.
DeltaFile
+4,805-4,811llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,871-1,882llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+837-855llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+415-431llvm/test/CodeGen/AMDGPU/load-global-i8.ll
+202-482llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
+303-329llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+8,433-8,79013 files not shown
+9,460-9,83219 files

LLVM/project 5d24bebllvm/include/llvm/IR ValueDeletionListener.h LLVMContext.h, llvm/lib/IR LLVMContext.cpp LLVMContextImpl.h

[IR] Add ValueDeletionListener for context-level Value deletion notifications
DeltaFile
+132-0llvm/unittests/IR/ValueDeletionListenerTest.cpp
+58-0llvm/include/llvm/IR/ValueDeletionListener.h
+18-0llvm/lib/IR/LLVMContext.cpp
+10-0llvm/include/llvm/IR/LLVMContext.h
+6-0llvm/lib/IR/LLVMContextImpl.h
+6-0llvm/lib/IR/Value.cpp
+230-01 files not shown
+231-07 files

LLVM/project e17fe37llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge branch 'users/KseniyaTikhomirova/kernel_submit_single_3' into users/KseniyaTikhomirova/kernel_submit_parallel_4
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-012,193 files not shown
+1,862,921-399,89412,199 files

LLVM/project 3de6b5cmlir/lib/Dialect/SPIRV/IR SPIRVTypes.cpp, mlir/test/Conversion/FuncToSPIRV types-to-spirv.mlir

[mlir][spirv] Fix Float8EXT type conversion legality (#192466)

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+50-27mlir/test/Conversion/FuncToSPIRV/types-to-spirv.mlir
+2-0mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
+52-272 files

FreeNAS/freenas 4f3dde5src/middlewared/middlewared/plugins/vm utils.py crud.py, src/middlewared/middlewared/pytest/unit/plugins/vm test_state_utils.py

Move VM NVRAM and TPM atomically with VM rename
DeltaFile
+175-0src/middlewared/middlewared/pytest/unit/plugins/vm/test_state_utils.py
+119-0src/middlewared/middlewared/plugins/vm/utils.py
+44-19src/middlewared/middlewared/plugins/vm/crud.py
+338-193 files

FreeBSD/ports b9afbefeditors/vscode pkg-plist Makefile

editors/vscode: Fix pkg-plist

The string "311" has been inadvertently substituted with
%%PYTHON_SUFFIX%% by `make makeplist`.

That has caused an error in the package phase for users using
non-default python versions (e.g. 3.12).

PR:             294660
Reported by:    Dean E. Weimer <dweimer at dweimer.net>
Tested by:      Dean E. Weimer <dweimer at dweimer.net>
DeltaFile
+2-2editors/vscode/pkg-plist
+1-1editors/vscode/Makefile
+3-32 files

FreeNAS/freenas d65d661src/middlewared/middlewared/plugins/vm utils.py crud.py, src/middlewared/middlewared/pytest/unit/plugins/vm test_state_utils.py

Move VM NVRAM and TPM atomically with VM rename
DeltaFile
+175-0src/middlewared/middlewared/pytest/unit/plugins/vm/test_state_utils.py
+111-0src/middlewared/middlewared/plugins/vm/utils.py
+44-19src/middlewared/middlewared/plugins/vm/crud.py
+330-193 files

LLVM/project 044e21fclang/lib/Headers vecintrin.h, clang/test/CodeGen/SystemZ builtins-systemz-zvector2.c

[SystemZ] Fix wrong mask for float vec_insert (#192967)

This commit fixes an error in vec_insert, where the index masking
effectively made the last two float elements of a vector non-insertable.

co-authored-by: @Andreas-Krebbel
DeltaFile
+4-1clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
+1-1clang/lib/Headers/vecintrin.h
+5-22 files

LLVM/project cf1f7c5llvm/test/Transforms/Attributor dereferenceable-2-inseltpoison.ll dereferenceable-2.ll, llvm/test/Transforms/Attributor/ArgumentPromotion musttail.ll

[Attributor] Regenerate test checks (NFC) (#193192)

To avoid spurious invariant.load changes in future changes.
DeltaFile
+44-22llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll
+12-8llvm/test/Transforms/Attributor/ArgumentPromotion/musttail.ll
+9-7llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll
+9-7llvm/test/Transforms/Attributor/dereferenceable-2.ll
+10-6llvm/test/Transforms/Attributor/align.ll
+8-6llvm/test/Transforms/Attributor/call-simplify-pointer-info.ll
+92-565 files not shown
+117-6711 files

LLVM/project 8e132f7cmake/Modules GetToolchainDirs.cmake, flang-rt/cmake/modules AddFlangRT.cmake

[runtimes][CMake] Move Fortran support code from flang-rt (#171610)

Common CMake code to be used by flang-rt and openmp to emit Flang module
files. Most of the code is not yet used within this PR.

Extracted out of #171515 for review by @petrhosek.
DeltaFile
+250-0runtimes/cmake/config-Fortran.cmake
+15-0runtimes/CMakeLists.txt
+14-0flang-rt/cmake/modules/AddFlangRT.cmake
+11-0cmake/Modules/GetToolchainDirs.cmake
+290-04 files

LLVM/project 7f72a8dllvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Remove support for FEAT_MPAMv2_VID

`FEAT_MPAMv2_VID` instructions and system registers, as introduced
in change d30f18d2c, are being removed at this time, as they've been
removed from the latest Arm ARM, which doesn't preclude them returning
in some form in future.

Other system registers introduced with `FEAT_MPAMv2` are unaffected,
and these continue to be ungated, but since `+mpamv2` gating is now empty,
I'm removing this superfluous gating code.
DeltaFile
+5-86llvm/test/MC/AArch64/armv9.7a-mpamv2.s
+0-36llvm/lib/Target/AArch64/AArch64SystemOperands.td
+5-17llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+0-18llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s
+2-12llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+0-10llvm/test/CodeGen/AArch64/aarch64-sys-intrinsic.ll
+12-1797 files not shown
+13-20513 files

LLVM/project af5fb38llvm/lib/Transforms/IPO AttributorAttributes.cpp, llvm/test/Transforms/Attributor undefined_behavior.ll

[Attributor] Clarify volatile null pointer behavior (NFCI) (#193190)

The comment was referring to volatile stores in particular, which
are specified as non-willreturn. However, allowing volatile accesses
on null (independently of null_pointer_is_valid) is a general
provision that is independent of the access kind.

The actual behavior was still correct, because volatile loads are
considered as writing inaccessible memory, so the mayWriteToMemory()
check was ultimately redundant.

Add a test to make sure volatile load is handled correctly.
DeltaFile
+62-85llvm/test/Transforms/Attributor/undefined_behavior.ll
+2-2llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+64-872 files

NetBSD/pkgsrc-wip a1ea486chromium distinfo COMMIT_MSG, chromium/patches patch-third__party_libvpx_source_config_linux_arm64_vpx__dsp__rtcd.h patch-chrome_browser_about__flags.cc

chromium: update to 147.0.7727.101
DeltaFile
+1,573-1,574chromium/distinfo
+65-125chromium/COMMIT_MSG
+104-0chromium/patches/patch-third__party_libvpx_source_config_linux_arm64_vpx__dsp__rtcd.h
+51-51chromium/patches/patch-chrome_browser_about__flags.cc
+0-37chromium/patches/patch-media_gpu_vaapi_vaapi__jpeg__encoder.cc
+0-35chromium/patches/patch-ui_gfx_paint__vector__icon.cc
+1,793-1,8221,568 files not shown
+3,440-3,5331,574 files