[Bitcode] Decode small byte constants as signed values (#203408)
Decode small byte constants the same way we encode them. The bitcode
writer stores ConstantByte values as signed integers, so the reader must
rebuild them using the signed ConstantByte::get path. This has high-bit
values like b8 255 round-trip as their canonical signed form, b8 -1,
instead of tripping the APInt width assertion. This matches current i8
behavior.
Before the fix, the new test crashes in llvm-dis with: "APInt.h:
Assertion `llvm::isUIntN(BitWidth, val) && "Value is not an N-bit
unsigned value"' failed."
Bug found while investigating this PR
(https://github.com/llvm/llvm-project/pull/177908), which transitions
the LSV to emitting the byte type. Fix assisted by AI.
[MIR] Serialize/Deserialize MachineInstr::LRSplit attribute
The LRSplit MachineInstr flag is set by SplitKit on copies inserted for
live-range splitting.
Until now the flag had no MIR-text representation.
This patch fixes that so that it gets easier to reproduce/capture issues
that involves SplitKit.
Round-trip coverage in
llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir.
[ValueTracking] Infer non-zero from shr (add nuw A, B), C (#203039)
...if either A or B has a known-one bit at position >= C.
https://alive2.llvm.org/ce/z/ELYTjh
This eliminates null checks in some internal workloads.
Assisted-by: claude
NAS-141273 / 25.10.5 / Remove shared pydantic `Field()` from API type aliases (#19078)
## Problem
Several API fields that are declared *required* are silently treated as
**optional with a bogus default** at runtime. For example, on the
current API
(v25_10_4):
VMRAWDevice.path = '127.0.0.1' # required path field, no default
declared
`VMRAWDevice.path` is `path: NonEmptyString = Field(pattern=...)` — it
should be
required, but it inherits `'127.0.0.1'` (leaked from
`VMDisplayDevice.bind`).
So `vm.device.create` for a RAW device with no `path` passes validation
and
silently uses `'127.0.0.1'` as the file path instead of being rejected.
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[mlir][SPIR-V] Guard UMod canonicalization against zero divisor (#203513)
Chained `spirv.UMod` with a zero outer divisor reached `APInt::urem`
which causes UB
[AMDGPU] Fix illegal AGPR reclassification in RewriteMFMAFormStage (#200972)
If src2 escapes rewrite group then bridge copy AGPR -> VGPR must be
inserted.
Fixes a regression after
https://github.com/llvm/llvm-project/pull/198555
[LifetimeSafety] Warn on inapplicable [[clang::lifetimebound]] parameters (#201101)
Adds `-Wlifetime-safety-inapplicable-lifetimebound` to diagnose
`[[clang::lifetimebound]]` annotations that have no effect because the
parameter type cannot carry a lifetime.
This currently diagnoses scalar parameters and `gsl::Owner` parameters
and unannotated record values (because they currently do not have
origins), while still allowing references, pointers and `gsl::Pointer`
values.
Closes #177184
clang-format/test: Anchor the empty .clang-format-ignore to test_exec_root (#203444)
The test suite's lit.local.cfg creates an empty .clang-format-ignore at
config discovery time to protect the multiple-inputs[-inplace].cpp tests
that work on files in temporary locations.
This file should be written to where the tests execute instead of the
CWD during config discovery. The CWD might not even be an ancestor of
where the tests execute, and it might be the repository root which does
have a .clang-format-ignore that is incorrectly clobbered without this
change.
An alternative would be to just fix the tests that need to be protected,
but having a blanket guard like this does seem like a reasonable thing
to do.
Fixes: 915de1a5889c ("Generate empty .clang-format-ignore before running
tests (#136154)")
[X86] combineConcatVectorOps - concat(roti(x,i),roti(y,i)) -> roti(concat(x,y),i) on non-vlx targets (#203528)
128/256-bit rotates are widened in tablegen, we don't need to limit
these to VLX targets - any AVX512 target can perform these
We already have test coverage to ensure 128-bit XOP rotates don't get
concatenated to 256-bit
[MIR] Save internal VirtRegMap state
Adds two optional fields to the per-vreg YAML record so MIR tests can
express VirtRegMap state that previously had no representation:
registers:
- { id: 1, class: vgpr_32, split-from: '%0', assigned-phys: '$vgpr5' }
Testing passes that consume sibling-register information (e.g.
InlineSpiller) requires constructing a VirtRegMap with split
relationships from a MIR test, which implies triggering live-range
splitting at minimum and make reproducers unnecessarily complicated.
So this change introduces a mechanism to serialize/deserialize the state
of the VirtRegMap pass.
Mechanism:
- For serialization:
- MIRPrinter emits the new fields only when the VirtRegMap is available.
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