LLVM/project b6efd3allvm/lib/Target/AMDGPU SIInsertHardClauses.cpp, llvm/test/CodeGen/AMDGPU hard-clauses-gfx1250.mir

[AMDGPU] Prevent clauses with incompatible scopes on gfx1250-strict
DeltaFile
+168-8llvm/test/CodeGen/AMDGPU/hard-clauses-gfx1250.mir
+20-1llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
+188-92 files

FreeBSD/ports acb9626net-mgmt/netbox pkg-plist distinfo

net-mgmt/netbox: Update to 4.6.9

Changelog:

Enhancements:
* Add InfiniBand 4X interface types
* Add an interface type for HPE Synergy interconnect links
* Restrict images in rendered Markdown to HTTP(S) and relative URLs
* Add a 100GBase-X-SFP112 interface type

Performance Improvements:
* Prefetch cable terminations to avoid N+1 queries when fetching cables
  via the GraphQL API

Bug Fixes:
* Prevent a server error when bulk import validation raises an error
  referencing a field omitted from the import data
* Avoid loading all associated jobs into memory when deleting a custom
  script or other job-bearing object

    [34 lines not shown]
DeltaFile
+7-7net-mgmt/netbox/Makefile
+3-3net-mgmt/netbox/distinfo
+4-0net-mgmt/netbox/pkg-plist
+14-103 files

FreeBSD/ports 09a06e5www/py-nh3 Makefile Makefile.crates

www/py-nh3: Update to 0.3.7

Changelog:

https://github.com/messense/nh3/compare/v0.3.6...v0.3.7

MFH:            2026Q3
(cherry picked from commit 628452e0813bc81ca51b30f482acf1db4aa067d2)
DeltaFile
+91-103www/py-nh3/distinfo
+44-50www/py-nh3/Makefile.crates
+1-1www/py-nh3/Makefile
+136-1543 files

FreeBSD/ports d52f0d6www/py-dj60-django-debug-toolbar Makefile distinfo

www/py-dj60-django-debug-toolbar: Update to 7.1.1

Changelog:

https://github.com/django-commons/django-debug-toolbar/releases/tag/7.1.1

MFH:            2026Q3
(cherry picked from commit e09dfb4a52b58e1e055ff050e1c4b7454862556c)
DeltaFile
+3-3www/py-dj60-django-debug-toolbar/distinfo
+1-1www/py-dj60-django-debug-toolbar/Makefile
+4-42 files

FreeBSD/ports e2daedatextproc/py-zensical Makefile distinfo

textproc/py-zensical: Update to 0.0.57

Changelog:

https://github.com/zensical/zensical/releases/tag/v0.0.57
(cherry picked from commit 84a8cecbaf187d8a15cc727551be4d3b02dad344)
DeltaFile
+3-3textproc/py-zensical/distinfo
+1-1textproc/py-zensical/Makefile
+4-42 files

FreeBSD/ports fee724egraphics/py-dj60-sorl-thumbnail Makefile distinfo

graphics/py-dj60-sorl-thumbnail: Update to 13.1.0

Changelog:

https://github.com/jazzband/sorl-thumbnail/releases/tag/13.1.0

MFH:            2026Q3
(cherry picked from commit 8c43902696d042cad2e42db73769b88ae8ee8ae2)
DeltaFile
+3-3graphics/py-dj60-sorl-thumbnail/distinfo
+2-2graphics/py-dj60-sorl-thumbnail/Makefile
+5-52 files

FreeBSD/ports 6b4032edevel/py-rq Makefile distinfo

devel/py-rq: Update 2.10.0 => 2.11.0

Changelog: https://github.com/rq/rq/releases/tag/v2.11
(cherry picked from commit 4e8d8f5f3014ef2a8cb257a9345492b3d0103f4b)
DeltaFile
+3-3devel/py-rq/distinfo
+1-1devel/py-rq/Makefile
+4-42 files

FreeBSD/ports a8dc430textproc/py-zensical Makefile Makefile.crates

textproc/py-zensical: Update to 0.0.56

Changelogs since 0.0.53:

https://github.com/zensical/zensical/releases/tag/v0.0.56
https://github.com/zensical/zensical/releases/tag/v0.0.55
https://github.com/zensical/zensical/releases/tag/v0.0.54
(cherry picked from commit 29050cc33cbf38a52b47283587feb3beccc6f5d0)
DeltaFile
+11-9textproc/py-zensical/distinfo
+4-3textproc/py-zensical/Makefile.crates
+1-1textproc/py-zensical/Makefile
+16-133 files

FreeBSD/ports 6e79bedwww/py-dj60-django-js-asset Makefile distinfo

www/py-dj60-django-js-asset: Update to 4.0.2

Changelog:

https://github.com/feincms/django-js-asset/blob/4.0.2/CHANGELOG.rst
(cherry picked from commit ab922d68a487e55bbf159b14e733a5e0c3fc17ad)
DeltaFile
+3-3www/py-dj60-django-js-asset/distinfo
+1-1www/py-dj60-django-js-asset/Makefile
+4-42 files

FreeBSD/ports 11fe3bctextproc/py-mkdocstrings-python Makefile distinfo

textproc/py-mkdocstrings-python: Update to 2.0.7

Changelog since 2.0.5:

https://github.com/mkdocstrings/python/blob/2.0.7/CHANGELOG.md
(cherry picked from commit 43ef0934a3701bc0d302a3da2868be49b66add16)
DeltaFile
+3-3textproc/py-mkdocstrings-python/distinfo
+1-1textproc/py-mkdocstrings-python/Makefile
+4-42 files

FreeBSD/ports 847ae41devel/bear Makefile Makefile.crates

devel/bear: Update to 4.2.1
DeltaFile
+91-105devel/bear/distinfo
+44-51devel/bear/Makefile.crates
+1-2devel/bear/Makefile
+136-1583 files

FreeBSD/ports 5ede2cddatabases/cassandra-cpp-driver distinfo Makefile, databases/cassandra-cpp-driver/files patch-e5a486ac52b99ae74d40e285b4438252fcf3b07a

databases/cassandra-cpp-driver: unbreak with CMake 4

While at it, adjust the GH repo to com/apache/cassandra-cpp-driver and
bump portrevision (the tarball SHA has changed).

PR:             297916
Reported by:    arrowd
DeltaFile
+505-0databases/cassandra-cpp-driver/files/patch-e5a486ac52b99ae74d40e285b4438252fcf3b07a
+4-3databases/cassandra-cpp-driver/Makefile
+3-3databases/cassandra-cpp-driver/distinfo
+512-63 files

FreeBSD/ports e4eebeawww/redmine60 pkg-plist Makefile, www/redmine60/files patch-Gemfile

www/redmine60: update to 6.0.11
DeltaFile
+3-3www/redmine60/distinfo
+2-2www/redmine60/files/patch-Gemfile
+1-2www/redmine60/Makefile
+1-0www/redmine60/pkg-plist
+7-74 files

LLVM/project a2ac4f6clang/include/clang/AST Expr.h, clang/lib/AST Expr.cpp ExprConstant.cpp

[clang][AST] Add `StringLiteral::findZeroCodeUnit()` (#218601)

Which can be used to implement strlen-like functionality.
DeltaFile
+78-0clang/unittests/AST/StringLiteral.cpp
+10-16clang/lib/AST/ExprConstant.cpp
+22-0clang/lib/AST/Expr.cpp
+4-8clang/lib/AST/ByteCode/InterpBuiltin.cpp
+4-7clang/lib/AST/ByteCode/Context.cpp
+9-0clang/include/clang/AST/Expr.h
+127-311 files not shown
+128-317 files

FreeBSD/ports 966d428. UPDATING, net-mgmt/semaphore pkg-install pkg-plist

net-mgmt/semaphore: update to 2.19.7, restore web UI

The port was frozen at 2.9.2 and installed only the REST API server; the
bundled web UI was never built, so every UI route returned 404.  Update
to
2.19.7 and restore the embedded Vue UI.

Upstream dropped BoltDB support in 2.19; the supported dialects are now
mysql, postgres and sqlite.  BoltDB installations must import their data
with a Semaphore 2.18 binary before the upgrade, because 2.19 no longer
ships the import tool.  Changing the dialect without importing silently
creates an empty database and all projects, templates, access keys and
the
task history are lost.  Add a pkg-install check that warns during
PRE-INSTALL when the configuration still selects the bolt dialect or a
database.boltdb is present, a pkg-message for upgrades from before 2.19,
and an UPDATING entry documenting the procedure.

Further changes:

    [19 lines not shown]
DeltaFile
+127-93net-mgmt/semaphore/distinfo
+89-69net-mgmt/semaphore/Makefile
+42-0UPDATING
+0-41net-mgmt/semaphore/pkg-plist
+39-0net-mgmt/semaphore/pkg-install
+38-0net-mgmt/semaphore/files/pkg-message.in
+335-2035 files not shown
+348-24111 files

LLVM/project 3638e00llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll coexec-hazardrec-preRA.mir

[AMDGPU] Add stalls for DS FIFO buffer (#192323)

This PR adds modeling for the LDS FIFO, and adds support for modelling
other types of buffers with similar characteristics.

The LDS unit has a FIFO which allows us to issue multiple LDS
instructions while the first is still executing. However, the FIFO is
sized, and, if we exceed the capacity, we will need to wait for a spot
in the FIFO before we can issue the instruction. This adds modeling for
this feature, which has impacts on: 1. the stall cycle calculations, and
2. the total usage of the HardwareUnit. The reason why this impacts 2.
is because previously we just summed the cycle count for each LDS
instruction for the total cycle. But, we can actually run N LDS
instructions in N + SingleInstructionCycle * N / BufferSize cycles. So,
if we scheduled 2 DS_LOAD instructions back to back, with
SingleInstructionCycle of 20 and BufferSize of 16, it would take 21
cycles to execute them instead of 40.

The SchedModel doesn't really have any good way to express this. It has

    [10 lines not shown]
DeltaFile
+67-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+57-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+48-0llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
+5-5llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir
+4-4llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+181-215 files

FreeBSD/ports 20ed1ffwww/redmine61 pkg-plist distinfo, www/redmine61/files patch-Gemfile patch-config_database.yml.sample

www/redmine61: update to 6.1.3

Security and bug fix release. Rails updated to 7.2.3.1.

While here, fix portclippy ordering for TRILOGY_DESC and
TRILOGY_RUN_DEPENDS.
DeltaFile
+5-6www/redmine61/Makefile
+4-4www/redmine61/files/patch-config_database.yml.sample
+3-3www/redmine61/files/patch-Gemfile
+3-3www/redmine61/distinfo
+1-0www/redmine61/pkg-plist
+16-165 files

OPNSense/core 1bf30c9src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms dialogFilterRule.xml, src/opnsense/mvc/app/models/OPNsense/Firewall Filter.xml

Move received-on to interface settings
DeltaFile
+24-22src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogFilterRule.xml
+9-9src/opnsense/mvc/app/models/OPNsense/Firewall/Filter.xml
+33-312 files

LLVM/project 23fa5a8llvm/lib/Transforms/InstCombine InstCombineAndOrXor.cpp, llvm/test/Transforms/InstCombine simple-round-up-pow2-alignment.ll

[InstCombine] Simplify conditional round-up to power-of-2 alignment (#184989)

The pattern `(X + (X % P == 0 ? 0 : P)) & -P`, that may arise when
computing `div_ceil(V, P) * P`, can be canonicalized to `(X + P-1) &
-P`, with P being a power of 2.

Proof: https://alive2.llvm.org/ce/z/ehyiNf.

Fixes: https://github.com/llvm/llvm-project/issues/184762.
DeltaFile
+229-0llvm/test/Transforms/InstCombine/simple-round-up-pow2-alignment.ll
+36-0llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+265-02 files

LLVM/project f2c18d8llvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU waitcnt-vavdst-ordered-xdl.mir

[AMDGPU] Model ordered XDL writes in expert scheduling

Treat qualifying XDL WMMA as VA_VDST fences so expert scheduling can use
nonzero waits after out-of-order event mixes.

An XDL instruction with a destination register of 8 or more VGPRs decrements
VA_VDST after all instructions that were issued earlier.

This offers a significant benefit in compute bound kernels since we are not
required to pessimistically wait for WMMAs to write their results when
interleaving LDS.

```
VALU def r0
TRANS
VALU
TRANS
WMMA
va_vdst(1) # previously this would require va_vdst(0)

    [2 lines not shown]
DeltaFile
+445-0llvm/test/CodeGen/AMDGPU/waitcnt-vavdst-ordered-xdl.mir
+112-27llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+14-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+4-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+575-274 files

FreeBSD/ports 153dd2dmisc/qwen-code Makefile distinfo, misc/qwen-code/files package-lock.json

misc/qwen-code: update to 0.22.1
DeltaFile
+180-140misc/qwen-code/files/package-lock.json
+3-3misc/qwen-code/distinfo
+4-1misc/qwen-code/Makefile
+187-1443 files

LLVM/project fc7697cclang/unittests/AST/ByteCode Pointer.cpp

[clang][bytecode][test] Test elem size against target wchar (#218837)

I *think* this is the problem here. I thought since I'm not specifying a
target triple, the host triple would always be used.

I've locally checked that elemSize() returns the correct value when
changing the target triple and that works.

The previous approach caused problems on some builders, see
https://github.com/llvm/llvm-project/pull/218707#issuecomment-5417327986
https://github.com/llvm/llvm-project/pull/216736#issuecomment-5419450306
DeltaFile
+7-4clang/unittests/AST/ByteCode/Pointer.cpp
+7-41 files

FreeBSD/ports 7d48fe9devel/py-virtualenv Makefile distinfo

devel/py-virtualenv: Update to 21.7.5

- Update list of test and doc dependencies

ChangeLog:

https://github.com/pypa/virtualenv/releases/tag/21.7.5

Reported by: "github-actions[bot]" <notifications at github.com>
DeltaFile
+3-3devel/py-virtualenv/distinfo
+3-1devel/py-virtualenv/Makefile
+6-42 files

FreeBSD/ports 18154d2www/oauth2-proxy Makefile distinfo

www/oauth2-proxy: Update to 7.15.4

ChangeLog: https://github.com/oauth2-proxy/oauth2-proxy/releases/tag/v7.15.4
DeltaFile
+5-5www/oauth2-proxy/distinfo
+1-2www/oauth2-proxy/Makefile
+6-72 files

NetBSD/pkgsrc 61LJnsJdoc CHANGES-2026

   Updated devel/cmake[-gui]
VersionDeltaFile
1.5535+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc p21a6c8devel/cmake version.mk distinfo

   cmake cmake-gui: updated to 4.4.3

   4.4.3
   Swift policy CMP0215's NEW behavior has been updated to require policies CMP0157 and CMP0195 to also be set to NEW.
VersionDeltaFile
1.270+4-4devel/cmake/distinfo
1.91+2-2devel/cmake/version.mk
+6-62 files

FreeBSD/ports a648a60sysutils/py-dbuild Makefile distinfo

sysutils/py-dbuild: Update to 1.9.13

ChangeLog: https://github.com/daemonless/dbuild/releases/tag/v1.9.13
DeltaFile
+3-3sysutils/py-dbuild/distinfo
+1-1sysutils/py-dbuild/Makefile
+4-42 files

FreeBSD/ports caac6e4security/py-unicode-show Makefile distinfo

security/py-unicode-show: Update to 54.3-1
DeltaFile
+3-3security/py-unicode-show/distinfo
+1-1security/py-unicode-show/Makefile
+4-42 files

FreeBSD/ports c2d05f8www/lycheeorg Makefile pkg-plist

www/lycheeorg: Upgrade to 7.7.5
DeltaFile
+30-32www/lycheeorg/pkg-plist
+13-15www/lycheeorg/Makefile
+43-472 files

LLVM/project 78d53f1llvm/lib/Target/AMDGPU SIInsertHardClauses.cpp, llvm/test/CodeGen/AMDGPU hard-clauses-gfx1250.mir

[AMDGPU] Prevent clauses with incompatible scopes on gfx1250-strict
DeltaFile
+168-8llvm/test/CodeGen/AMDGPU/hard-clauses-gfx1250.mir
+20-1llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
+188-92 files