[Hexagon] Disable new value jumps when packetizer is disabled (#180615)
New value jumps require the feeder instruction to be in the same packet
as the consumer (.new) instruction. When --disable-packetizer is used,
each instruction is placed in its own packet, making it impossible to
satisfy this requirement.
Previously, using --disable-packetizer would cause an assertion failure
in the MCCodeEmitter: "Couldn't find producer". This change fixes the
crash by checking the DisablePacketizer flag in the NewValueJump pass
and skipping NVJ generation when packetization is disabled.
(cherry picked from commit e1be4dfe1ef889c51d7e1704782a31dc65bb745c)
Reland "[llvm-ir2vec] Adding Inst Embeddings Map API to ir2vec python bindings (#180140)" (#184196)
Relanding change from https://github.com/llvm/llvm-project/pull/180140
- Returns a Inst Embedding Map based on the input function name
`getInstEmbMap(funcName) -> Map<Inst string, Embedding>`
- Refactors IR2VecTool methods to have a separate call to create the
embedder object
[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin (#181386)
Add `__arm_atomic_store_with_stshh` implementation as defined in the
ACLE. Validate arguments passed are correct, and lower to the `stshh`
intrinsic plus an atomic store using a pseudo-instruction with the
allowed orderings:
* memory orderings: relaxed, release, seq_cst
* retention policies: keep, strm
The `STSHH` instruction (Store with Store Hint for Hardware) is part
of the `FEAT_PCDPHINT` extension.
Fix broken WRITE_ATTRIBUTES test
This commit fixes a test that claude munged when converting
functional tests from tests/api2 to tests/unit (with local utils).
fixup! Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
and use tablegen pattern for intrinsic, plus other small review changes.
[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin
Add `__arm_atomic_store_with_stshh` implementation as defined
in the ACLE. Validate that the arguments passed are correct, and
lower it to the stshh intrinsic plus an atomic store with the
allowed orderings.
Gate this on FEAT_PCDPHINT so that availability matches
hardware support for the `STSHH` instruction. Use an i64
immediate and side-effect modeling to satisfy tablegen and decoding.