FreshBSD

LLVM/project 1d1c83a — offload/include/OpenMP Mapping.h, offload/libomptarget omptarget.cpp

2026-03-02 23:32:30 UTC by Abhinav Gaba via GitHub on ⎇

main

Reland "[OpenMP][Offload] Handle `present/to/from` when a different entry did `alloc/delete`." (#184260)

Some tests that were checking for prints inside/outside `target` regions
needed to be updated to work on systems where the ordering wasn't
deterministic.

Reverts llvm/llvm-project#184240
    
Original description from #165494:

-----

OpenMP allows cases like the following:

```c
  int *p1, *p2, x;
  p1 = p2 = &x;
  ...
  #pragma omp target_exit_data map(delete: p1[:]) from(p2[0])

    [35 lines not shown]

Delta		File
+223	-50	offload/libomptarget/omptarget.cpp
+103	-15	offload/include/OpenMP/Mapping.h
+50	-0	offload/test/mapping/map_ordering_tgt_exit_data_from_mapper_overlap.c
+49	-0	offload/test/mapping/map_ordering_ptee_tgt_data_alloc_tgt_mapper_present_delete_from_to.c
+48	-0	offload/test/mapping/map_ordering_ptee_tgt_alloc_mapper_alloc_from_to.c
+43	-0	offload/test/mapping/map_ordering_tgt_exit_data_delete_from_assumedsize.c
+516	-65	11 files not shown
+765	-76	17 files

LLVM/project d4d1824 — lldb/include/lldb/Utility LLDBLog.h, lldb/source/Initialization SystemInitializerCommon.cpp

2026-03-02 23:30:05 UTC by Jonas Devlieghere via GitHub on ⎇

main

[lldb] Terminate the LLDB Log in SystemInitializerCommon::Terminate (#184261)

Currently, when calling SBDebugger::Initialize after
SBDebugger::Terminate, you hit an assert in LLDBLog when trying to
register the LLDB log a second time. Also fix the awkward
capitalization.

Delta		File
+3	-1	lldb/source/Initialization/SystemInitializerCommon.cpp
+3	-1	lldb/source/Utility/LLDBLog.cpp
+2	-1	lldb/include/lldb/Utility/LLDBLog.h
+8	-3	3 files

LLVM/project 582b009 — llvm/test/Transforms/LoopVectorize vplan-based-stride-mv.ll, llvm/test/Transforms/LoopVectorize/VPlan vplan-based-stride-mv.ll

2026-03-02 23:27:30 UTC by Andrei Elovikov on ⎇

users/eas/vplan-based-stride-mv-tests

[NFC][VPlan] Add initial tests for future VPlan-based stride MV

I tried to include both the features that current
LoopAccessAnalysis-based transformation supports (e.g., trunc/sext of
stride) but also cases where the current implementation behaves poorly,
e.g., https://godbolt.org/z/h31c3zKxK; as well as some other potentially
interesting scenarios I could imagine.

The are two test files with the same content. One is for VPlan dump change of
the future transformation alone (I'll update `-vplan-print-after` in the next
PR), another is for the full vectorizer pipeline. The latter have two `RUN:`
lines:
 * No multiversioning, so the next PR diff can show the transformation itself
 * Stride multiversionin performed in LAA, so that we can compare future
   VPlan-based transformation vs old behavior.

Delta		File
+4,627	-0	llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+3,306	-0	llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+7,933	-0	2 files

LLVM/project f77a830 — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h, llvm/test/Transforms/LoopVectorize/VPlan vplan-print-after-all.ll

2026-03-02 23:23:36 UTC by Andrei Elovikov on ⎇

users/eas/mem-widen-subpasses

[NFC][VPlan] Split `makeMemOpWideningDecisions` into subpasses

The idea is to have handling of strided memory operations (either from
https://github.com/llvm/llvm-project/pull/147297 or for VPlan-based
multiversioning for unit-strided accesses) done after some mandatory
processing has been performed (e.g., some types **must** be scalarized)
but before legacy CM's decision to widen (gather/scatter) or scalarize
has been committed.

And in longer term, we can uplift all other memory widening decision to
be done here directly at VPlan level. I expect this structure would also
be beneficial for that.

Delta		File
+82	-38	llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+10	-0	llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+0	-10	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3	-0	llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
+95	-48	4 files

LLVM/project d1080c4 — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

2026-03-02 23:22:33 UTC by Andrei Elovikov on ⎇

users/eas/split-mem-widen-transform

Braces for outer `if`

Delta		File
+2	-1	llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2	-1	1 files

LLVM/project 7f998a9 — llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanTransforms.cpp

2026-03-02 23:22:32 UTC by Andrei Elovikov on ⎇

users/eas/split-mem-widen-transform

Move to VPlanTransforms, have to pass Legal explicitly

Delta		File
+1	-78	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+76	-0	llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+3	-1	llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+80	-79	3 files

LLVM/project 10319e7 — llvm/lib/Transforms/Vectorize LoopVectorize.cpp

2026-03-02 23:22:32 UTC by Andrei Elovikov on ⎇

users/eas/split-mem-widen-transform

Don't make unnecessary captures

Delta		File
+1	-1	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1	-1	1 files

LLVM/project c535af1 — llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPRecipeBuilder.h, llvm/test/Transforms/LoopVectorize/AArch64 predication_costs.ll

2026-03-02 23:22:32 UTC by Andrei Elovikov on ⎇

users/eas/split-mem-widen-transform

[NFCI][VPlan] Split initial mem-widening into a separate transformation

Preparation change before implementing stride-multiversioning as a
VPlan-based transformation. Might help
https://github.com/llvm/llvm-project/pull/147297/ as well.

Delta		File
+92	-31	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+14	-12	llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+3	-2	llvm/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
+4	-0	llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+1	-0	llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
+114	-45	5 files

LLVM/project 03e2af7 — clang/lib/CIR/CodeGen CIRGenExpr.cpp CIRGenExprScalar.cpp, clang/test/CIR/CodeGen bitfield-assignment-loc.c

2026-03-02 23:12:04 UTC by Akimasa Watanuki via GitHub on ⎇

main

[CIR] Fix bitfield store locations for assignment codegen (#184005)

Update bitfield-assignment codegen to emit stores at
assignment-expression source locations.
Keep `cir.set_bitfield` aligned with other store-like operations.
Prevent regressions that reattach bitfield stores to declaration-site
locations.

Add a CIR test on `clang/test/CIR/CodeGen/bitfield-assignment-loc.c`.

Fix https://github.com/llvm/llvm-project/issues/183759

Delta		File
+15	-0	clang/test/CIR/CodeGen/bitfield-assignment-loc.c
+2	-2	clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+2	-0	clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+19	-2	3 files

LLVM/project db95cd9 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

2026-03-02 23:01:45 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Address Carol's comments and fix git clang-format issues

Delta		File
+27	-0	llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+20	-0	llvm/lib/IR/Verifier.cpp
+12	-6	clang/lib/Sema/SemaARM.cpp
+0	-11	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4	-2	clang/lib/Headers/arm_acle.h
+2	-4	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+65	-23	6 files

LLVM/project 8b53b60 — llvm/test/CodeGen/AArch64 pcdphint-atomic-store.ll

2026-03-02 23:01:45 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Sort out testcases

Delta		File
+54	-102	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+54	-102	1 files

LLVM/project be0dd19 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

2026-03-02 23:01:45 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fixes for Caroline

Delta		File
+27	-0	llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+1	-12	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2	-2	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+0	-3	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+30	-17	4 files

LLVM/project e097c3b — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

2026-03-02 23:01:45 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! More small fixes

Delta		File
+15	-37	clang/lib/Sema/SemaARM.cpp
+11	-0	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5	-3	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2	-2	clang/lib/Headers/arm_acle.h
+0	-1	clang/test/CodeGen/arm_acle.c
+33	-43	5 files

LLVM/project 8e2ce3f — clang/test/CodeGen arm_acle.c builtins-arm64.c, clang/test/Sema/AArch64 pcdphint-atomic-store.c

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fix more PR comments

Delta		File
+19	-9	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+8	-6	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+10	-0	clang/test/CodeGen/arm_acle.c
+0	-9	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5	-0	clang/test/CodeGen/builtins-arm64.c
+0	-4	llvm/include/llvm/IR/IntrinsicsAArch64.td
+42	-28	2 files not shown
+44	-32	8 files

LLVM/project 1a94e50 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen/AArch64 pcdphint-atomic-store.c

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Ensure stshh always immediately precedes a store instruction

Delta		File
+82	-0	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+50	-13	clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+62	-0	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+20	-26	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+15	-0	llvm/lib/Target/AArch64/AArch64InstrInfo.td
+8	-3	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+237	-42	3 files not shown
+248	-49	9 files

LLVM/project 7a9d1c2 — clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fix Kerry's CR comments and add negative test for "must be an integer type"

Delta		File
+16	-6	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+3	-7	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+3	-3	clang/lib/Sema/SemaARM.cpp
+5	-0	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+3	-0	clang/include/clang/Basic/DiagnosticSemaKinds.td
+1	-1	clang/lib/Headers/arm_acle.h
+31	-17	6 files

LLVM/project 1b235b6 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/Sema/AArch64 pcdphint-atomic-store.c

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup!

A few small tidyups

Delta		File
+7	-6	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4	-4	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+4	-0	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+15	-10	3 files

LLVM/project 1d37ec3 — clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Small fixes Kerry has suggested

Delta		File
+112	-40	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+7	-11	clang/lib/Sema/SemaARM.cpp
+7	-9	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1	-1	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+127	-61	4 files

LLVM/project 54a9230 — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fix tests

Delta		File
+2	-0	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2	-0	1 files

LLVM/project 4310ee6 — clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fix issues Kerry raised in PR

Delta		File
+10	-23	clang/lib/Sema/SemaARM.cpp
+16	-11	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5	-12	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1	-5	clang/include/clang/Basic/DiagnosticSemaKinds.td
+32	-51	4 files

LLVM/project d6f0d14 — clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Address more helpful review comments from Kerry

Delta		File
+160	-0	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4	-4	llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1	-4	clang/lib/Sema/SemaARM.cpp
+0	-5	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+165	-13	4 files

LLVM/project cc85d58 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`

Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
and use tablegen pattern for intrinsic, plus other small review changes.

Delta		File
+47	-75	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+69	-32	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+42	-47	clang/lib/Sema/SemaARM.cpp
+21	-12	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+17	-5	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+10	-12	llvm/lib/Target/AArch64/AArch64InstrInfo.td
+206	-183	5 files not shown
+220	-192	11 files

LLVM/project 4705fde — llvm/include/llvm/IR IntrinsicsAArch64.td, llvm/lib/Target/AArch64 AArch64InstrFormats.td

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! remove mayLoad/mayStore as suggested by Kerry

Delta		File
+0	-5	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+1	-1	llvm/include/llvm/IR/IntrinsicsAArch64.td
+1	-6	2 files

LLVM/project da5515b — clang/include/clang/Basic BuiltinsAArch64.def, clang/lib/CodeGen/TargetBuiltins ARM.cpp

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup!

More small issues tidied, and remove gating.

Delta		File
+6	-2	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+2	-2	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+0	-2	clang/lib/Headers/arm_acle.h
+1	-1	clang/lib/Sema/SemaARM.cpp
+1	-1	clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+1	-1	clang/include/clang/Basic/BuiltinsAArch64.def
+11	-9	6 files

LLVM/project 636672b — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin

Add `__arm_atomic_store_with_stshh` implementation as defined
in the ACLE. Validate that the arguments passed are correct, and
lower it to the stshh intrinsic plus an atomic store with the
allowed orderings.

Gate this on FEAT_PCDPHINT so that availability matches
hardware support for the `STSHH` instruction. Use an i64
immediate and side-effect modeling to satisfy tablegen and decoding.

Delta		File
+140	-0	clang/lib/Sema/SemaARM.cpp
+48	-0	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+31	-0	clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+29	-0	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+13	-0	llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+10	-2	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+271	-2	5 files not shown
+298	-2	11 files

LLVM/project 675685e — clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

2026-03-02 23:01:44 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Improve error diagnostics, and other cleanups

Delta		File
+12	-0	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4	-2	clang/lib/Sema/SemaARM.cpp
+2	-1	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2	-0	clang/lib/Headers/arm_acle.h
+1	-1	clang/include/clang/Basic/DiagnosticSemaKinds.td
+1	-1	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+22	-5	6 files

NetBSD/pkgsrc UuVAZ6p — misc/window distinfo Makefile

2026-03-02 23:00:24 UTC by buhrow on ⎇

pkgsrc-2025Q3

   Teach window(1) how to deal with ANSI terminal escape sequences.
   Specifically: escape sequences begining with [ and which contain ? or numeric values.
   This allows window(1) to work better with those terminal programs, especially those which use
   readline(3) calls, which insist on emitting these extended escape sequences even if those
   definitions are not in the termcap or terminfo spec for the terminal in use.
   this new support is incomplete in the sense that we don't do anything with the numeric values,
   but we do honor the functions of the actions requested as long as they were actions this
   program already supported.
   Preliminary testing shows a vast improvement with programs like gdb and the interactive python
   shells.

Version	Delta		File
1.6.32.1	+4	-4	misc/window/distinfo
1.6.66.1	+2	-2	misc/window/Makefile
	+6	-6	2 files

FreeBSD/ports 2fb3937 — java/netbeans pkg-plist distinfo

2026-03-02 22:58:36 UTC by Paolo Enriello via Vladimir Druzenko (vvd) on ⎇

2026Q1

java/netbeans: Update 28 => 29

Changelog:
https://github.com/apache/netbeans/releases/tag/29

PR:     293537
MFH:    2026Q1
(cherry picked from commit bb8247385cbd3f1d98e02f5dd5a33af3636fb449)

Delta		File
+60	-110	java/netbeans/pkg-plist
+3	-3	java/netbeans/distinfo
+1	-1	java/netbeans/Makefile
+64	-114	3 files

LLVM/project 0f8aa96 — lldb/source/Plugins/Process/minidump RegisterContextMinidump_ARM64.cpp

2026-03-02 22:56:44 UTC by Jason Molenda on ⎇

main

[lldb][NFC] Whitespace cleanup in RegisterContextMinidump_ARM64
Breaking out the whitespace changes turned up in a separate
contentful PR.

Delta		File
+80	-70	lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.cpp
+80	-70	1 files

FreeNAS/freenas c9ada68 — src/middlewared/middlewared/etc_files/local/nginx nginx.conf.mako, src/middlewared/middlewared/plugins/ports ports.py

2026-03-02 22:55:01 UTC by Waqar Ahmed on ⎇

NAS-139710

Add nginx route for rwd

This commit adds an nginx reverse proxy route at /rwd/ pointing to the rwd service on 127.0.0.1:1700. Since rwd listens on TCP (not a unix socket), nginx handles the missing service gracefully — returning 502 when rwd is down without affecting startup or other routes. Port 1700 is also registered as a reserved system port to prevent conflicts.

Delta		File
+13	-0	src/middlewared/middlewared/etc_files/local/nginx/nginx.conf.mako
+1	-1	src/middlewared/middlewared/plugins/ports/ports.py
+14	-1	2 files