LLVM/project d7904abclang/lib/Sema SemaCoroutine.cpp, clang/test/CodeGenCoroutines coro-await-elidable.cpp

[Clang] Fix coro_await_elidable breaking with parenthesized expressions

The applySafeElideContext function used IgnoreImplicit() to find the
underlying CallExpr, but this didn't strip ParenExpr nodes. When code
like `co_await (fn(leaf()))` was parsed, the operand was wrapped in a
ParenExpr, causing HALO (Heap Allocation eLision Optimization) to fail.

This fix uses IgnoreExprNodes with IgnoreImplicitSingleStep and
IgnoreParensSingleStep to iteratively strip both implicit nodes and
parentheses until reaching a fixed point, handling any ordering of
these nodes in the AST.

Fixes the issue where adding parentheses around co_await's argument
would prevent heap elision for coro_await_elidable coroutines, which
is particularly problematic since parentheses are often required in
real-world code due to co_await's tight binding with operators.
DeltaFile
+50-0clang/test/CodeGenCoroutines/coro-await-elidable.cpp
+6-1clang/lib/Sema/SemaCoroutine.cpp
+56-12 files

LLVM/project 91856eallvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopUnrollPass] Add comment explaining the use of `UP.DefaultUnrollRuntimeCount` in `shouldPartialUnroll` (NFC) (#178817)

DeltaFile
+2-0llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+2-01 files

LLVM/project 43e52b7llvm/lib/CodeGen/SelectionDAG SelectionDAGISel.cpp

[SelectionDAGISel] Use size_t for MatcherIndex. NFC (#178828)

There's some evidence that this improves compile time on stage2-O3.
https://llvm-compile-time-tracker.com/compare.php?from=75f03a62d1f9b0081fff57ceebb29a3ae1560a61&to=d9cdb41d51f7010ba710403e2d1e30c969e4f88b&stat=instructions:u
DeltaFile
+24-24llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+24-241 files

LLVM/project b936771llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP][NFC] Refactor vectorizeStores::RangeSizes (#177241)

Currently `RangeSizes` is used to allow us to skip trying to vectorize
clearly unprofitable trees by caching prior attempts `TreeSizes`. This
PR refactors that logic to simplify and improve readability. This will
make it easier to handle the strided stores.

Switches RangeSizes to use `first` as the location to lookup values from, and `second` as the location to store values to. `first` gets updated by `second` at the appropriate times to match the behavior prior to this change.
DeltaFile
+30-38llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+30-381 files

LLVM/project 3f67996llvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopUnrollPass] Fix spelling mistake in `computeUnrollCount` description (NFC) (#178816)

DeltaFile
+1-1llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+1-11 files

LLVM/project 7710d21llvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopUnrollPass] Remove unhelpful comment in `shouldPragmaUnroll` (NFC) (#178814)

The note the comment is making should be obvious based on the structure
of the pass. Additionally, it is grammatically incorrect and has
spelling errors.
DeltaFile
+0-1llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+0-11 files

LLVM/project b686226llvm/include/llvm/BinaryFormat MachO.h, llvm/lib/Target/RISCV/MCTargetDesc RISCVMachObjectWriter.cpp

[RISC-V][Mach-O] Use RISCV_RELOC_ADDEND for large pc-relative offset. (#178699)

Do not inline the pc-relative offset from the auipc into the addi/lw
immediates if the offset requires than the 12-bit (signed). Instead,
emit a 24-bit (signed) relocation record with RISCV_RELOC_ADDEND.
DeltaFile
+46-0llvm/test/MC/RISCV/macho-offset-relocations.s
+22-8llvm/lib/Target/RISCV/MCTargetDesc/RISCVMachObjectWriter.cpp
+6-5llvm/include/llvm/BinaryFormat/MachO.h
+74-133 files

LLVM/project 7890960llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs riscv_function_name.ll.expected riscv_function_name.ll, llvm/utils/UpdateTestChecks asm.py

[UTC][RISC-V] Enable riscv32 Mach-O triple. (#178738)

Co-authored-by: Adam Nemet <anemet at apple.com>
DeltaFile
+10-0llvm/utils/UpdateTestChecks/asm.py
+6-0llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_function_name.ll.expected
+1-0llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_function_name.ll
+17-03 files

LLVM/project 7994dacllvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp, llvm/test/CodeGen/X86 stack-usage-file.ll

[AsmPrinter] Add a command-line option to emit stack usage files (#178908)

Preparation for #178005.

This will allow stack usage files to be requested during the linking
step in LTO builds, in a more straightforward way than via
TargetOptions.
DeltaFile
+12-0llvm/test/CodeGen/X86/stack-usage-file.ll
+8-1llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+20-12 files

LLVM/project f0288c4clang/lib/CIR/CodeGen CIRGenCUDANV.cpp

newlines yo
DeltaFile
+1-1clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
+1-11 files

LLVM/project 3eddc7cclang/lib/CIR/CodeGen CIRGenCUDANV.cpp

nyi on runtime constructor
DeltaFile
+1-1clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
+1-11 files

LLVM/project 8e3701eclang/include/clang/AST ASTContext.h, clang/lib/AST ASTContext.cpp

address comments and adapt a bunch of lines to proper coding standards
DeltaFile
+50-66clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
+36-4clang/test/CIR/CodeGen/CUDA/kernel-call.cu
+12-0clang/lib/AST/ASTContext.cpp
+9-2clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-0clang/include/clang/AST/ASTContext.h
+2-0clang/lib/CIR/CodeGen/CIRGenModule.h
+111-726 files

LLVM/project fb1c745llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp

Fix typo in code coming from main
DeltaFile
+1-1llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+1-11 files

NetBSD/pkgsrc-wip 7d9f67fxemu distinfo Makefile

Update xemu to 0.0.2026.01.29.

New "stable" (kind of ... # ) release
CHANGE: "none" (other than copyright adjustments for 2026). This is
release of the last next as stable. As it was a long time ago when we
had a stable release what we have now here.
DeltaFile
+3-3xemu/distinfo
+2-2xemu/Makefile
+5-52 files

Dreckly/dreckly 7d5b0dbnet/yt-dlp PLIST Makefile

yt-dlp: Update to 2026.1.29
DeltaFile
+85-11net/yt-dlp/PLIST
+7-5net/yt-dlp/Makefile
+4-4net/yt-dlp/distinfo
+2-2net/yt-dlp/MESSAGE
+98-224 files

Dreckly/dreckly 0d5df69devel/py-hatchling distinfo Makefile

py-hatchling: Update to 1.28.0
DeltaFile
+4-4devel/py-hatchling/distinfo
+2-2devel/py-hatchling/Makefile
+6-62 files

FreeBSD/ports e826eb2devel/py-rich-click Makefile distinfo

devel/py-rich-click: Update to 1.9.6

Many enhancements since 1.6.1
Changes: https://github.com/ewels/rich-click/releases
Run-tested under py-multiqc
Pip pkg for py-litestar uses 1.9.6

PR:             292776
Reported by:    nivit
DeltaFile
+14-4devel/py-rich-click/Makefile
+3-3devel/py-rich-click/distinfo
+17-72 files

LLVM/project e79bb02llvm/test/CodeGen/AMDGPU swdev503538-move-to-valu-stack-srd-physreg.ll

[NFC] Reduce fragility of swdev503538-... test. (#176302)

The original test was created in PR #120815, but it depends on -O0 and
implicitly uses DAGCombiner (that is switched on by default for -O0).
The patch reduces fragility of the test and removes dependency on
DAGCombiner.
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
+2-21 files

LLVM/project 5f3bda9llvm/test/CodeGen/SPIRV/transcoding spirv-event-null-64.ll spirv-event-null.ll

[review] Add missing changes.
DeltaFile
+46-46llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null-64.ll
+45-45llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
+21-21llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided-64.ll
+20-20llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided.ll
+132-1324 files

FreeBSD/src bda8028release/pkg_repos release-dvd.conf, release/scripts pkg-stage.sh

release: Ship firmware from kmods repo on DVD

The packages for X.Y-RELEASE are a snapshot of the quarterly branch
for stable/X, i.e. typically built on X.(Y-1)-RELEASE.  (The case of
Y=0 is an exception for obvious reasons.)  This works for most ports
but not for kernel modules, which may need to be built on the release
in question; this is why we have a separate "kmods" repository.

Make sure that we put the packages from the kmods repository onto the
mini-pkg-repo on the DVD rather than shipping unusable firmware.

Reviewed by:    bz
MFC after:      1 week
Sponsored by:   https://www.patreon.com/cperciva
Differential Revision:  https://reviews.freebsd.org/D52581
DeltaFile
+18-7release/scripts/pkg-stage.sh
+7-0release/pkg_repos/release-dvd.conf
+25-72 files

FreeNAS/freenas ac19fadsrc/middlewared/middlewared/plugins/failover_ event.py

In become_active ensure all user-related config

This commit ensures that when a controller becomes active, we
regenerate the user and API key configuration so that there's
no chance of stale information being preset.
DeltaFile
+5-0src/middlewared/middlewared/plugins/failover_/event.py
+5-01 files

LLVM/project 09b62edclang/bindings/python/tests/cindex test_code_completion.py

[libclang/python] Ignore our own DeprecationWarnings in tests (#178631)

Suppress `DeprecationWarnings` raised in the libclang python tests. Also
ensure that they are returned where expected.
Resolves #178203
DeltaFile
+25-7clang/bindings/python/tests/cindex/test_code_completion.py
+25-71 files

FreeBSD/doc cc68540website/content/en/releases/15.0R errata.adoc

15.0: Update status of devinfo issue

This was fixed in FreeBSD 15.0-RELEASE-p2.

Reviewed by:    ziaee
Differential Revision:  https://reviews.freebsd.org/D54958
DeltaFile
+1-1website/content/en/releases/15.0R/errata.adoc
+1-11 files

LLVM/project 70e3c12llvm/test/CodeGen/SPIRV/transcoding OpGroupAsyncCopy-strided-64.ll OpGroupAsyncCopy-strided.ll

[review] Use default CHECK.
DeltaFile
+1-1llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided-64.ll
+1-1llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided.ll
+1-1llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null-64.ll
+1-1llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
+4-44 files

LLVM/project 29a55f7clang/lib/Driver/ToolChains HIPSPV.cpp, clang/test/Driver hipspv-toolchain-rdc.hip hipspv-toolchain.hip

[Clang][retry] Lift HIPSPV onto the new offload driver (#178664)

Update HIPSPV toolchain to support --offload-new-driver. Additionally,
tailor llvm-spirv invocation for
[chipStar](https://github.com/CHIP-SPV/chipStar) via
`spirv64-*-chipstar` offload triple.

The previous PR (#168043) had CI failures that were not caught early.
This one attempts to address them.
DeltaFile
+98-42clang/test/Driver/hipspv-toolchain-rdc.hip
+78-16clang/test/Driver/hipspv-toolchain.hip
+59-11clang/lib/Driver/ToolChains/HIPSPV.cpp
+66-0clang/test/Driver/hipspv-toolchain-rdc-separate.hip
+38-8clang/test/Driver/hipspv-pass-plugin.hip
+28-10clang/test/Driver/hipspv-link-static-library.hip
+367-879 files not shown
+425-11215 files

LLVM/project 3d4f6b3llvm/include/llvm/CodeGen CalcSpillWeights.h, llvm/lib/CodeGen CalcSpillWeights.cpp

[RegAlloc] Remove redundant parameters for weightCalcHelper (NFC). (#170151)

Since futureWeight was removed by
145cc9db2b442fc0533e275b92943a9894e33337, there is no more calls to
weightCalcHelper(LI, start, end)
DeltaFile
+3-35llvm/lib/CodeGen/CalcSpillWeights.cpp
+1-8llvm/include/llvm/CodeGen/CalcSpillWeights.h
+4-432 files

LLVM/project a994198llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-int-mulh.ll sve-streaming-mode-fixed-length-fp-rounding.ll

[DAG] Reland: Enable bitcast STLF for Constant/Undef (#178890)

This is a reland of #172523.

The original patch caused an assertion failure on RISC-V because it
attempted to create a bitcast from an illegal type (i32 on RV64) during
the post-type-legalization DAGCombine stage.

Added a `TLI.isTypeLegal(Val.getValueType())` check to ensure we only
proceed with the bitcast STLF optimization when the source value's type
is legal for the target.
DeltaFile
+71-0llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
+67-0llvm/test/CodeGen/RISCV/rvv/stlf.ll
+8-22llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
+26-3llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+0-14llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
+4-8llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
+176-4736 files not shown
+242-17242 files

LLVM/project 4ea1791llvm/lib/Target/X86 X86FixupInstTuning.cpp

[X86] Truncate unused bit for blendw mask (#178883)

While tuning ProcessBLENDWToBLENDD 

https://github.com/mahesh-attarde/llvm-project/blob/07ec2fa1443ccd3cbb55612937f1dddebfe51c15/llvm/lib/Target/X86/X86FixupInstTuning.cpp#L262
we creating mask from `getImm()` which returns 64bit int and APInt
accept 64 bit int.
```
    APInt MaskW =
        APInt(8, MI.getOperand(NumOperands - 1).getImm(), /*IsSigned=*/false);
```
It fails with MIR for BLENDW instruction that requires8 bit mask 0xAA
from 64 bit Imm.
```
  renamable $xmm2 = VPBLENDWrri renamable $xmm1, killed renamable $xmm2, -86
```
APInt construction complains since higher bits of are also set for
transformations where mask bits are set (results in negative values).


    [11 lines not shown]
DeltaFile
+2-1llvm/lib/Target/X86/X86FixupInstTuning.cpp
+2-11 files

FreeBSD/ports 6d1520cwww/tomcat-native2 distinfo Makefile, www/tomcat-native2/files patch-src_ssl.c patch-src_sslutils.c

www/tomcat-native2: Upgrade port to 2.0.12

This release finally drops backported OpenSSL 1.1.1 support, thus FreeBSD 13
support because the patches fail to apply due to upstream changes to those files.

MFH:            2026Q1
Changelog:      https://tomcat.apache.org/native-doc/miscellaneous/changelog.html#Changes_in_2.0.12
(cherry picked from commit 99c91e99baae1f10136796a261d183566dc1c8b1)
DeltaFile
+0-63www/tomcat-native2/files/patch-src_ssl.c
+0-14www/tomcat-native2/files/patch-src_sslutils.c
+0-12www/tomcat-native2/files/patch-include_ssl__private.h
+3-3www/tomcat-native2/distinfo
+3-2www/tomcat-native2/Makefile
+6-945 files

FreeBSD/ports 99c91e9www/tomcat-native2 distinfo Makefile, www/tomcat-native2/files patch-src_ssl.c patch-src_sslutils.c

www/tomcat-native2: Upgrade port to 2.0.12

This release finally drops backported OpenSSL 1.1.1 support, thus FreeBSD 13
support because the patches fail to apply due to upstream changes to those files.

MFH:            2026Q1
Changelog:      https://tomcat.apache.org/native-doc/miscellaneous/changelog.html#Changes_in_2.0.12
DeltaFile
+0-63www/tomcat-native2/files/patch-src_ssl.c
+0-14www/tomcat-native2/files/patch-src_sslutils.c
+0-12www/tomcat-native2/files/patch-include_ssl__private.h
+3-3www/tomcat-native2/distinfo
+3-2www/tomcat-native2/Makefile
+6-945 files