LLVM/project bc54aefllvm/test/Analysis/LoopAccessAnalysis invariant-dep-same-ptr.ll

[LAA] Add tests with missed aliasing invariant load/store. (NFC)

Add a set of tests showing incorrect LAA results based on
https://github.com/llvm/llvm-project/issues/186922.
DeltaFile
+343-0llvm/test/Analysis/LoopAccessAnalysis/invariant-dep-same-ptr.ll
+343-01 files

LLVM/project fdbc015lldb/source/Plugins/Platform/MacOSX PlatformDarwin.cpp, lldb/unittests/Platform PlatformDarwinTest.cpp

[lldb][PlatformDarwin][NFC] Move logic to emit warning on invalid/conflicting Python script names into helper function (#185669)

Depends on:
* https://github.com/llvm/llvm-project/pull/185666
* https://github.com/llvm/llvm-project/pull/185627

I'm planning on re-using this logic for a different API. Hence move it
into a common helper.
DeltaFile
+36-26lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
+15-16lldb/unittests/Platform/PlatformDarwinTest.cpp
+51-422 files

LLVM/project bc19061utils/bazel/llvm_configs config.h.cmake

[Bazel] Port 55b271d (#187007)
DeltaFile
+3-0utils/bazel/llvm_configs/config.h.cmake
+3-01 files

LLVM/project a78d1d9mlir/lib/Conversion/VectorToLLVM ConvertVectorToLLVM.cpp, mlir/test/Conversion/VectorToLLVM vector-to-llvm-interface.mlir

[mlir][vector] Add missing tests (nfc) (#186990)

Currently, `ConvertVectorToLLVM` rejects strided memrefs when lowering
`vector.gather` and `vector.scatter`. This PR adds tests to document
that behavior.

Supporting strided memrefs in the lowering is left as future work.
However, it is still unclear whether gather/scatter on strided memrefs
should be supported at all (see the Discourse discussion [1]).

This PR also adds tests for `vector.load` and `vector.store` in
`invalid.mlir` to document that these ops do not support strided
memrefs.

[1] https://discourse.llvm.org/t/rfc-semantics-of-vector-gather-indices-with-strided-memrefs
DeltaFile
+27-0mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
+16-0mlir/test/Dialect/Vector/invalid.mlir
+2-0mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
+45-03 files

LLVM/project f3bed35llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td, llvm/lib/Target/AArch64/MCTargetDesc AArch64InstPrinter.cpp

[AArch64][llvm] Redefine some isns as an alias of `SYS`

Some instructions are not currently defined as an alias of `SYS`
when they should be, so they don't disassemble back into the
native instruction, but instead disassemble into `SYS`.
Fix these cases and add additional testcase.

Note that I've left `GCSPUSHM` due to a `mayStore`, `GCSSS1` and
`GCSSS2` as they're used in AArch64ISelDAGToDAG.cpp, and `GCSPOPM`
has an intrinsic pattern in AArch64InstrInfo.td. They will disassemble
correctly though, as they use `InstAlias`.
DeltaFile
+116-0llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+24-23llvm/lib/Target/AArch64/AArch64InstrInfo.td
+40-0llvm/test/MC/AArch64/armv9.4a-gcs.s
+0-19llvm/lib/Target/AArch64/AArch64InstrFormats.td
+6-2llvm/test/MC/AArch64/brbe.s
+5-0llvm/test/MC/AArch64/armv8.9a-debug-pmu.s
+191-441 files not shown
+196-447 files

HardenedBSD/src 80d813dsys/dev/virtio virtqueue.c, sys/net if_bridge.c

Merge remote-tracking branch 'origin/hardened/current/master' into hardened/current/cross-dso-cfi
DeltaFile
+2-2sys/net/if_bridge.c
+2-1sys/netinet6/nd6.c
+1-1sys/dev/virtio/virtqueue.c
+5-43 files

HardenedBSD/src 572a8aesys/dev/virtio virtqueue.c, sys/net if_bridge.c

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+2-2sys/net/if_bridge.c
+2-1sys/netinet6/nd6.c
+1-1sys/dev/virtio/virtqueue.c
+5-43 files

FreeBSD/src edc9c3eusr.sbin/virtual_oss/virtual_oss main.c

virtual_oss: Combine -d, -l and -L option getopt code

Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Reviewed by:    markj
Differential Revision:  https://reviews.freebsd.org/D55671

(cherry picked from commit a2b601343bf9261c4ada51e4d4c30c5b9320bb2b)
DeltaFile
+3-21usr.sbin/virtual_oss/virtual_oss/main.c
+3-211 files

HardenedBSD/ports 70b2e2emath/leangz distinfo Makefile, misc/py-hf-xet distinfo Makefile.crates

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+253-141net/krill/distinfo
+159-139misc/py-hf-xet/distinfo
+126-70net/krill/Makefile.crates
+121-55math/leangz/distinfo
+78-68misc/py-hf-xet/Makefile.crates
+60-27math/leangz/Makefile
+797-50079 files not shown
+1,457-72385 files

LLVM/project 04cc752mlir/lib/Dialect/Bufferization/Transforms FuncBufferizableOpInterfaceImpl.cpp, mlir/test/Dialect/Bufferization/Transforms one-shot-module-bufferize-call-copy-before-write.mlir

[mlir][bufferization] Fix crash with copy-before-write + bufferize-function-boundaries (#186446)

When `copy-before-write=1` is combined with
`bufferize-function-boundaries=1`, `bufferizeOp` creates a plain
`AnalysisState` (not `OneShotAnalysisState`) and passes it to
`insertTensorCopies`. Walking `CallOp`s during conflict resolution
called `getCalledFunction(callOp, state)`, which unconditionally cast
the `AnalysisState` to `OneShotAnalysisState` via `static_cast`, causing
UB and a stack overflow crash.

Fix by guarding the cast with `isa<OneShotAnalysisState>()` so that when
the state is a plain `AnalysisState`, the function falls through to
building a fresh `SymbolTableCollection` — the same safe fallback
already present.

Fixes https://github.com/llvm/llvm-project/issues/163052

Assisted-by: Claude Code
DeltaFile
+16-0mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-call-copy-before-write.mlir
+8-6mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
+24-62 files

LLVM/project a26077ellvm/lib/Target/NVPTX NVPTXIntrinsics.td, llvm/test/CodeGen/NVPTX tcgen05-mma-scale-d.ll tcgen05-mma.ll

[NFC][NVPTX] Fix tcgen05.mma PTX instruction encoding (#186602)

.ashift should be before .collector::a::* according to PTX ISA.

ptxas accepts both orderings, but the spec-correct order is used now.
DeltaFile
+16-16llvm/test/CodeGen/NVPTX/tcgen05-mma-scale-d.ll
+12-12llvm/test/CodeGen/NVPTX/tcgen05-mma.ll
+4-4llvm/test/CodeGen/NVPTX/tcgen05-mma-i8.ll
+1-1llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+33-334 files

HardenedBSD/ports b7c8ef2devel/adacurses Makefile distinfo

devel/adacurses: update to 20251230 release with ncurses 6.8 support
DeltaFile
+5-4devel/adacurses/Makefile
+3-3devel/adacurses/distinfo
+5-0devel/adacurses/pkg-plist
+13-73 files

FreeBSD/ports b7c8ef2devel/adacurses Makefile distinfo

devel/adacurses: update to 20251230 release with ncurses 6.8 support
DeltaFile
+5-4devel/adacurses/Makefile
+3-3devel/adacurses/distinfo
+5-0devel/adacurses/pkg-plist
+13-73 files

FreeNAS/freenas 2c949f2tests/api2 test_300_nfs.py

test diagnostics
DeltaFile
+44-7tests/api2/test_300_nfs.py
+44-71 files

FreeNAS/freenas 09c2a06src/freenas/etc/systemd/system/fsidd.service.d override.conf, src/freenas/etc/systemd/system/nfsdcld.service.d override.conf

Generate nfs.conf after system global ID creation on first boot
DeltaFile
+7-0src/middlewared/middlewared/migration/0009_system_global_id.py
+4-0src/freenas/etc/systemd/system/nfsdcld.service.d/override.conf
+4-0src/freenas/etc/systemd/system/fsidd.service.d/override.conf
+15-03 files

LLVM/project 055322cmlir/lib/IR Diagnostics.cpp, mlir/test/mlir-opt expected-unknown-loc-unmatched.mlir

[mlir] Fix crash in diagnostic verifier for unmatched @unknown expectations (#186148)

When an expected-* directive uses the @unknown location specifier, the
associated ExpectedDiag record has an invalid (null) SMLoc as its
fileLoc. If the expected diagnostic is never produced, emitError() is
called to report the unmatched expectation, but it unconditionally
constructs an SMRange from fileLoc, triggering a null-pointer
dereference (UBSan) and an assertion failure in SMRange's constructor
which requires both endpoints to have equal validity.

Fix by guarding the SMRange construction with a fileLoc.isValid() check.
When fileLoc is invalid, call PrintMessage without a source range.

Fixes #163343

Assisted-by: Claude Code
DeltaFile
+11-3mlir/lib/IR/Diagnostics.cpp
+9-0mlir/test/mlir-opt/expected-unknown-loc-unmatched.mlir
+20-32 files

LLVM/project 48e6a61llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'arm-fp-flt' into arm-fp-faddsub

The merged changes on main include a fix for the previous denormal
handling bug in the old Thumb1 addsf3. So one of my reasons to replace
it completely is gone. Therefore I'm reinstating it, and putting the
new one alongside it as a different time/space tradeoff.
DeltaFile
+84,299-78,378llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,754-24,794llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,631-20,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,843-18,635llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,086-16,499llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+240,906-188,1409,745 files not shown
+957,718-642,6419,751 files

OPNSense/core 64a43f2src/opnsense/mvc/app/models/OPNsense/Dnsmasq Dnsmasq.php

dnsmasq: remove a too-strict validation

When adding ranges from setaddr.php we do not use the model so
one can input ::1000 etc and then Dnsmasq migration will fail
due to it not setting a constructor.  We still validate :: prefix
for constructor use but now take :: prefix verbatim which
doesn't interfere with Dnsmasq service start.

Discussed-with: @monviech
(cherry picked from commit a5773fe71f5703426761b9965bd49e468366de27)
DeltaFile
+0-12src/opnsense/mvc/app/models/OPNsense/Dnsmasq/Dnsmasq.php
+0-121 files

LLVM/project b861a28llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/WebAssembly simd-bitmask.ll

[WebAssembly] combine `bitmask` with `setcc <X>, 0, setlt` (#179065)

The rust `simd_bitmask` intrinsic is UB when the lanes of its input are
not either `0` or `!0`, presumably so that the implementation can be
more efficient because it could look at any bit. To get the "mask of
MSB" behavior of webassembly's `bitmask`, we would like to simply first
compare with a zero vector.

```llvm
define i32 @example(<2 x i64> noundef %v) {
entry:
  %1 = icmp slt <16 x i8> %v, zeroinitializer
  %2 = bitcast <16 x i1> %1 to i16
  %3 = zext i16 %2 to i32
  ret i32 %3
}
```

On x86_64, this additional comparison optimizes away, but for wasm it

    [22 lines not shown]
DeltaFile
+120-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+23-1llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+143-12 files

LLVM/project 973a5a9llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'arm-fp-fix' into arm-fp-flt
DeltaFile
+84,299-78,378llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,754-24,794llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,631-20,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,843-18,635llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,086-16,499llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+240,906-188,1409,743 files not shown
+956,257-641,4579,749 files

LLVM/project d080cacllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'arm-fp-f2d2f' into arm-fp-fix
DeltaFile
+84,299-78,378llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,754-24,794llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,631-20,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,843-18,635llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,086-16,499llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+240,906-188,1409,743 files not shown
+956,257-641,4579,749 files

LLVM/project a25bf27llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'arm-fp-fcmp' into arm-fp-f2d2f
DeltaFile
+84,299-78,378llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,754-24,794llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,631-20,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,843-18,635llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,086-16,499llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+240,906-188,1409,743 files not shown
+956,257-641,4579,749 files

LLVM/project fe187f6compiler-rt/lib/builtins CMakeLists.txt

Stop trying to crt_supersede one Arm .S file with another

Turns out that doesn't work: both versions of the assembly language
comparison were included in the output library, and the linker would
make an arbitrary choice of which to pull in to the link. Instead,
just put the old files on to the SOURCES list in an else clause.
DeltaFile
+8-4compiler-rt/lib/builtins/CMakeLists.txt
+8-41 files

LLVM/project b50e6b8llvm/test/CodeGen/AArch64 arm64-int-neon.ll

[AArch64][GlobalISel] Update test checks
DeltaFile
+0-4llvm/test/CodeGen/AArch64/arm64-int-neon.ll
+0-41 files

LLVM/project 039c88ellvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.cpp

[AArch64][GlobalISel] Fix uqadd/sub with scalar operands

Previously, neon uqadd/uqsub would not lower when given s32/s64 operands, as GlobalISel would wrongly try to put the operands on general-purpose register banks. Changing this in RegBankSelection allows the intrinsics to lower just like their signed versions.
DeltaFile
+2-0llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+2-01 files

LLVM/project 0cb3d34llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'arm-fp-dcmp' into arm-fp-fcmp
DeltaFile
+84,299-78,378llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,754-24,794llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,631-20,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,843-18,635llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,086-16,499llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+240,906-188,1409,735 files not shown
+956,198-641,4159,741 files

LLVM/project dcaa9c2llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'arm-fp-dmuldiv' into arm-fp-dcmp
DeltaFile
+84,299-78,378llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,754-24,794llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,631-20,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,843-18,635llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,086-16,499llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+240,906-188,1409,735 files not shown
+956,198-641,4159,741 files

LLVM/project 67e47fbmlir/include/mlir/Dialect/GPU/IR GPUOps.td, mlir/lib/Dialect/GPU/IR GPUDialect.cpp

[mlir][gpu] Add SymbolUserOpInterface to launch_func op (#173277)

The gpu.launch_func is an operation that performs symbol references.
Currently, its symbol validation logic is implemented within
GPUDialect::verifyOperationAttribute. To improve the clarity and
structure of the validation logic, this PR makes LaunchFuncOp implement
the SymbolUserOpInterface. In addition, implementing this interface
allows the operation to benefit from various symbol-usage analysis
passes.
DeltaFile
+85-77mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
+18-2mlir/test/Dialect/GPU/invalid.mlir
+1-0mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
+104-793 files

LLVM/project 7cf9ff4llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'arm-fp-daddsub' into arm-fp-dmuldiv
DeltaFile
+84,299-78,378llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,754-24,794llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,631-20,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,843-18,635llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,086-16,499llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+240,906-188,1409,735 files not shown
+956,198-641,4159,741 files

LLVM/project cb20d02llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'arm-fp-double-support' into arm-fp-daddsub
DeltaFile
+84,299-78,378llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,754-24,794llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,631-20,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,843-18,635llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,086-16,499llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+240,906-188,1409,735 files not shown
+956,198-641,4159,741 files