LLVM/project d1f7425mlir/lib/IR OperationSupport.cpp, mlir/test/IR operation-equality.mlir

[mlir] Propagate `checkCommutativeEquivalent` into `isRegionEquivalentTo` (#192670)

The `checkCommutativeEquivalent` callback was not forwarded when
recursing into nested regions via `isRegionEquivalentTo`, causing silent
fallback to strict operand-order comparison for ops inside regions. Fix
by propagating the callback through the call site, and add a lit test
covering this case.
DeltaFile
+15-0mlir/test/IR/operation-equality.mlir
+3-3mlir/lib/IR/OperationSupport.cpp
+18-32 files

LLVM/project 25b0ab2.ci compute_projects_test.py compute_projects.py, cross-project-tests/debuginfo-tests/dexter-tests/memvars const-branch.c

[ci][llvm] Run cross-project-tests on llvm/ changes (#188522)

This patch ensures we run the `cross-project-tests` on `llvm/` PRs. At
the very least those tests depend on debug-info and
`llvm/ADT/`/`llvm/Support` (and the data-formatters that also live in
`llvm/`).

This would've helped catch
https://github.com/llvm/llvm-project/pull/188483 at pre-merge time.
DeltaFile
+8-8.ci/compute_projects_test.py
+1-1.ci/compute_projects.py
+1-1cross-project-tests/debuginfo-tests/dexter-tests/memvars/const-branch.c
+10-103 files

LLVM/project ecb2d81lldb/source/Plugins/Process/Windows/Common NativeProcessWindows.cpp

[lldb][Windows] Read/Write PC after suspending thread (#191371)

Currently, we access the PC before suspending the thread in case of a
software breakpoint exception. However, we can't reliably read or write
the thread context while the thread is running. So, suspend the thread
first and then read or write the PC when handling a software breakpoint
exception.

Co-authored-by: Ayush Sahay <asahay at qti.qualcomm.com>
DeltaFile
+1-1lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
+1-11 files

FreeNAS/freenas 0c7ed8fsrc/middlewared/middlewared/plugins/apps upgrade.py app_scale.py, src/middlewared/middlewared/plugins/docker backup.py

Some more fixes
DeltaFile
+12-5src/middlewared/middlewared/plugins/apps/upgrade.py
+6-2src/middlewared/middlewared/plugins/apps/app_scale.py
+2-2src/middlewared/middlewared/plugins/apps/crud.py
+1-1src/middlewared/middlewared/plugins/docker/backup.py
+1-1src/middlewared/middlewared/plugins/apps/custom_app_ops.py
+1-1src/middlewared/middlewared/plugins/apps/events.py
+23-121 files not shown
+24-137 files

LLVM/project b2ca731llvm/lib/CodeGen MachineBlockPlacement.cpp, llvm/test/CodeGen/X86 block-placement-triangle-profile-likely-prob.mir

[CodeGen] Fix profiled triangular CFG threshold in MachineBlockPlacement (#188752)

Fix an assertion failure in MachineBlockPlacement for profiled
triangular CFGs with large -profile-likely-prob values.

The existing triangular-CFG threshold scaling can produce a
BranchProbability greater than 1. Capping to `BranchProbability(100,
100)` added.
DeltaFile
+60-0llvm/test/CodeGen/X86/block-placement-triangle-profile-likely-prob.mir
+8-4llvm/lib/CodeGen/MachineBlockPlacement.cpp
+68-42 files

LLVM/project 673c71fflang/lib/Semantics check-omp-structure.h check-omp-structure.cpp

[flang][OpenMP] Clean up check-omp-structure.h, NFC

Group declarations to make it clear in which of the check-omp-*.cpp
files a given function is defined.
Delete declarations that don't have corresponding definitions.
Rename private member variable to follow naming convention.
DeltaFile
+115-118flang/lib/Semantics/check-omp-structure.h
+4-4flang/lib/Semantics/check-omp-structure.cpp
+119-1222 files

HardenedBSD/src 42af3dasys/conf newvers.sh

HBSD: Resolve merge conflict

Signed-off-by:  Shawn Webb <shawn.webb at hardenedbsd.org>
DeltaFile
+1-6sys/conf/newvers.sh
+1-61 files

HardenedBSD/src adf160binclude unistd.h, lib/libthr libthr.3

Merge remote-tracking branch 'tor/freebsd/15-stable/main' into hardened/15-stable/main

Conflicts:
        sys/conf/newvers.sh (unresolved)
DeltaFile
+25-0lib/libthr/libthr.3
+2-4sys/kern/vfs_aio.c
+6-0sys/sys/fcntl.h
+5-0sys/conf/newvers.sh
+4-1include/unistd.h
+4-1sys/kern/vfs_syscalls.c
+46-64 files not shown
+50-1110 files

LLVM/project 5de013dllvm/test/CodeGen/X86 pr192034.ll

[X86] Add test coverage for #192034 (#192686)
DeltaFile
+35-0llvm/test/CodeGen/X86/pr192034.ll
+35-01 files

LLVM/project 424140allvm/lib/Target/AArch64 AArch64InstrFormats.td AArch64InstrInfo.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Some instructions should be `HINT` aliases (NFC)

Implement the following instructions as a `HINT` alias instead of a
dedicated instruction in separate classes:
  * `stshh`
  * `stcph`
  * `shuh`
  * `tsb`

Updated all their helper methods too, and updated the `stshh` pseudo
expansion for the intrinsic to emit `HINT #0x30 | policy`.

Code in AArch64AsmPrinter::emitInstruction identified an initial BTI using a
broad bitmask on the HINT immediate, which also matched shuh/stcph (50..52)
This could move the patchable entry label after a non-BTI instruction.
Replaced it with an exact BTI check using the BTI HINT range (32..63) and
AArch64BTIHint::lookupBTIByEncoding(Imm ^ 32).

A following change will remove duplicated code and simplify.

    [2 lines not shown]
DeltaFile
+115-0llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+41-39llvm/lib/Target/AArch64/AArch64InstrFormats.td
+22-3llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+5-14llvm/lib/Target/AArch64/AArch64InstrInfo.td
+5-10llvm/lib/Target/AArch64/AArch64SystemOperands.td
+4-2llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+192-682 files not shown
+199-698 files

LLVM/project 3183e57llvm/test/CodeGen/X86 masked_gather_scatter.ll

[X86] masked_gather_scatter.ll - regenerate with VPADD asm comments (#192685)
DeltaFile
+8-8llvm/test/CodeGen/X86/masked_gather_scatter.ll
+8-81 files

LLVM/project a8a1bc4llvm/lib/Target/AArch64 AArch64InstrFormats.td AArch64InstrInfo.td, llvm/lib/Target/AArch64/Disassembler AArch64Disassembler.cpp

[AArch64][llvm] Tighten SYSP; don't disassemble invalid encodings

Tighten SYSP aliases, so that invalid encodings are disassembled
to `<unknown>`. This is because:

```
  Cn is a 4-bit unsigned immediate, in the range 8 to 9
  Cm is a 4-bit unsigned immediate, in the range 0 to 7
  op1 is a 3-bit unsigned immediate, in the range 0 to 6
  op2 is a 3-bit unsigned immediate, in the range 0 to 7
```

Ensure we check this when disassembling, and also constrain
tablegen for compile-time errors of invalid encodings.

Also adjust the testcases in `armv9-sysp-diagnostics.s` and
`llvm/test/MC/AArch64/armv9a-sysp.s` as they were invalid,
and added a few invalid (outside of range) SYSP-alikes to
test that `<unknown>` is printed
DeltaFile
+111-111llvm/test/MC/AArch64/armv9a-sysp.s
+25-1llvm/lib/Target/AArch64/AArch64InstrFormats.td
+25-0llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+20-0llvm/test/MC/AArch64/armv9-sysp-invalid.s
+7-8llvm/test/MC/AArch64/armv9-sysp-diagnostics.s
+7-3llvm/lib/Target/AArch64/AArch64InstrInfo.td
+195-1233 files not shown
+207-1279 files

LLVM/project f1a872fllvm/lib/Target/AArch64/MCTargetDesc AArch64InstPrinter.cpp

fixup! Address PR comment about shortened `sysp` with xzr/xzr
DeltaFile
+17-16llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+17-161 files

LLVM/project 9b1deefllvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Remove SYSPxt_XZR and update code to reflect this
DeltaFile
+27-34llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+41-14llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+8-26llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+2-30llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-20llvm/test/MC/AArch64/armv9-sysp-invalid.s
+13-3llvm/test/MC/AArch64/armv9-sysp-diagnostics.s
+91-1274 files not shown
+105-13710 files

LLVM/project 0e914fdllvm/lib/Target/AArch64 AArch64RegisterInfo.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Implement Marian's suggestion to implement as XSeqPairsClass + [XZR, XZR]
DeltaFile
+54-82llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+35-73llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+12-9llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+8-1llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+0-7llvm/test/MC/AArch64/armv9a-sysp.s
+1-3llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
+110-1756 files

LLVM/project 8539d3allvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/test/MC/AArch64 armv9-sysp-diagnostics.s

fixup! Improve error parsing
DeltaFile
+46-25llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+12-12llvm/test/MC/AArch64/armv9-sysp-diagnostics.s
+58-372 files

LLVM/project b9cbc9ellvm/lib/Target/AArch64 AArch64InstrFormats.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Address PR comments
DeltaFile
+5-9llvm/lib/Target/AArch64/AArch64InstrFormats.td
+2-3llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+1-2llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+1-1llvm/test/MC/AArch64/armv9-sysp-diagnostics.s
+9-154 files

LLVM/project 58512bbllvm/lib/Target/AArch64 AArch64InstrFormats.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Templatise bounds checking and improve tests
DeltaFile
+15-4llvm/test/MC/AArch64/armv9-sysp-diagnostics.s
+18-0llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+12-5llvm/lib/Target/AArch64/AArch64InstrFormats.td
+0-8llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+45-174 files

LLVM/project 73f6f1fllvm/lib/Target/AArch64 AArch64InstrFormats.td AArch64InstrInfo.td

fixup! Address Marian's PR comments: use imm0_6 predicate
DeltaFile
+9-1llvm/lib/Target/AArch64/AArch64InstrFormats.td
+2-2llvm/lib/Target/AArch64/AArch64InstrInfo.td
+11-32 files

LLVM/project 7bd71b4llvm/lib/Target/AArch64 AArch64InstrFormats.td

fixup! Fixes after rebasing following Marian's change
DeltaFile
+3-3llvm/lib/Target/AArch64/AArch64InstrFormats.td
+3-31 files

LLVM/project d532646llvm/lib/Target/AArch64/MCTargetDesc AArch64InstPrinter.cpp, llvm/test/MC/AArch64 armv9a-sysp.s

fixup! Add no-alias tests
DeltaFile
+4-3llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+7-0llvm/test/MC/AArch64/armv9a-sysp.s
+11-32 files

LLVM/project fce4a1eclang/docs/CIR CleanupAndEHDesign.rst CleanupAndEHDesign.md

[CIR][docs] Migrate existing Markdown documents to reStructuredText format (#192066)

This patch migrates the existing ClangIR documents that are written in
Markdown format to reStructuredText format to align CIR's documents with
clang's documentation policy.

Closes #191850 .
DeltaFile
+1,631-0clang/docs/CIR/CleanupAndEHDesign.rst
+0-1,587clang/docs/CIR/CleanupAndEHDesign.md
+589-0clang/docs/CIR/ABILowering.rst
+0-556clang/docs/CIR/ABILowering.md
+2,220-2,1434 files

LLVM/project 8656768clang/test/Driver hexagon-toolchain-picolibc.c

[Hexagon] Relax toolchain check to accept ld in driver test (#192596)

Fixes failures in
https://lab.llvm.org/buildbot/#/builders/145/builds/13829
https://lab.llvm.org/buildbot/#/builders/124/builds/2152

Signed-off-by: Kushal Pal <kushpal at qti.qualcomm.com>
DeltaFile
+2-2clang/test/Driver/hexagon-toolchain-picolibc.c
+2-21 files

LLVM/project 2c9a1a7clang/lib/Driver SanitizerArgs.cpp, clang/test/Driver fsanitize-realtime.c

[clang][rtsan] Disallow type and realtime sanitizer combo (#192681)

Both of these sanitizer runtimes define similar interceptors, so they
may not be used together
DeltaFile
+5-0clang/test/Driver/fsanitize-realtime.c
+2-1clang/lib/Driver/SanitizerArgs.cpp
+7-12 files

pkgng/pkgng 0092c01libpkg pkg_repo.c

fingerprints, fallback on the host to find them when using -r

Fixes:  #2390
DeltaFile
+8-2libpkg/pkg_repo.c
+8-21 files

LLVM/project 6e94ad0flang/lib/Evaluate fold-implementation.h, flang/test/Evaluate rewrite09.f90 rewrite01.f90

[flang] Fold x + 0, 0 + x and x - 0 for INTEGER and UNSIGNED (#192479)

This fixes https://github.com/llvm/llvm-project/issues/191928.
DeltaFile
+49-0flang/test/Evaluate/rewrite09.f90
+30-0flang/lib/Evaluate/fold-implementation.h
+4-12flang/test/Lower/HLFIR/array-ctor-as-inlined-temp.f90
+1-3flang/test/Lower/HLFIR/array-ctor-as-runtime-temp.f90
+1-3flang/test/Lower/HLFIR/array-ctor-as-elemental.f90
+1-1flang/test/Evaluate/rewrite01.f90
+86-196 files

LLVM/project d9b43e2libc/src/__support wctype_impl.h wctype_utils.h, libc/src/wctype CMakeLists.txt iswctype.cpp

[libc] Reorganize iswctype to avoid GPU/libc++ error (#192659)

After #191178 there were build errors when building the libc++
hand-in-hand pieces due to header layering.

Written with the assistance of Gemini
DeltaFile
+105-0libc/src/__support/wctype_impl.h
+0-82libc/src/__support/wctype_utils.h
+13-0libc/src/__support/CMakeLists.txt
+4-2libc/src/wctype/CMakeLists.txt
+2-3libc/src/wctype/iswctype.cpp
+2-3libc/src/wctype/wctype.cpp
+126-906 files

Linux/linux d730905Documentation/devicetree/bindings/soc/mobileye mobileye,eyeq6lplus-olb.yaml, arch/mips/boot/dts/econet en751221.dtsi

Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - Support for Mobileye EyeQ6Lplus

 - Cleanups and fixes

* tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits)
  MIPS/mtd: Handle READY GPIO in generic NAND platform data
  MIPS/input: Move RB532 button to GPIO descriptors
  MIPS: validate DT bootargs before appending them
  MIPS: Alchemy: Remove unused forward declaration
  MAINTAINERS: Mobileye: Add EyeQ6Lplus files
  MIPS: config: add eyeq6lplus_defconfig
  MIPS: Add Mobileye EyeQ6Lplus evaluation board dts
  MIPS: Add Mobileye EyeQ6Lplus SoC dtsi
  clk: eyeq: Add Mobileye EyeQ6Lplus OLB
  clk: eyeq: Adjust PLL accuracy computation

    [11 lines not shown]
DeltaFile
+308-129drivers/pinctrl/pinctrl-eyeq5.c
+208-0Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq6lplus-olb.yaml
+170-0arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi
+117-0arch/mips/configs/eyeq6lplus_defconfig
+114-0arch/mips/boot/dts/econet/en751221.dtsi
+69-39arch/mips/pci/pci-mt7620.c
+986-16836 files not shown
+1,589-24742 files

pkgng/pkgng 05a37aclibpkg pkgdb.c

search: improve error message

Fixes: #1397
DeltaFile
+10-2libpkg/pkgdb.c
+10-21 files

LLVM/project fd647callvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 f16f32dot-fixed-length-fdot.ll

[AArch64] Fix codegen for FEAT_F16F32DOT with SVE2/SME. (#192668)

When compiling with +sve2/+sme, don't override to use Custom lowering
for PARTIAL_REDUCE_FMLA when it previously determined the operation was
legal due to +f16f32dot/+fp16fml.
DeltaFile
+10-5llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+14-0llvm/test/CodeGen/AArch64/f16f32dot-fixed-length-fdot.ll
+24-52 files