LLVM/project 6dfe9eellvm/lib/Target/AMDGPU SIFoldOperands.cpp

AMDGPU: Fix using getVRegDef on a physical register in SIFoldOperands

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+3-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+3-01 files

LLVM/project 0b99968llvm/lib/Transforms/InstCombine InstCombineAndOrXor.cpp, llvm/test/Transforms/InstCombine free-inversion.ll

[InstCombine] Fix crash on dereferencing null insertion point (#216363)

Fix, add assertions and regressin test.

The issue occurred when trying to invert a phi inside a catchswitch
block, because there is no legal insertion point after the phi.
DeltaFile
+38-0llvm/test/Transforms/InstCombine/free-inversion.ll
+10-3llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+48-32 files

LLVM/project 8798fffclang/lib/CodeGen CodeGenModule.cpp, clang/test/CodeGen amdgpu-builtin-processor-is.c amdgpu-builtin-is-invocable.c

clang/AMDGPU: Don't emit target-features on AMDGCN-flavored SPIR-V

The spirv64-amd-amdhsa target unions every GPU's features in its feature
map so it can report builtins as available. The CodeGen doesn't have
any use of the target-features. Putting it into the IR just results
in an annoying to update test every time a new feature is added. The
ultimate SPIRV codegen doesn't do anything with it, and if it did
survive to AMDGPU codegen, it would be actively harmful.

This isn't an ideal solution. The target-features spam is also
noisy and useless in the AMDGPU case, but solving that is more
intricate because we do currently rely on this for some features,
most notably the wavesize.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+5-0clang/lib/CodeGen/CodeGenModule.cpp
+2-2clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
+1-1clang/test/CodeGen/amdgpu-builtin-processor-is.c
+1-1clang/test/CodeGen/amdgpu-builtin-is-invocable.c
+9-44 files

LLVM/project 9a5bd30clang/lib/Basic/Targets AMDGPU.h AMDGPU.cpp, clang/lib/Driver/ToolChains CommonArgs.cpp AMDGPU.cpp

clang/AMDGPU: Use feature bitset instead of ArchAttr (#216674)

Convert from the legacy getArchAttrAMDGCN manual bitmask checks to using
the new generated bitset. These are the easy cases. sramecc and xnack
require more supporting work so will be done later.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+11-9clang/lib/Driver/ToolChains/AMDGPU.cpp
+11-2llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+6-2clang/lib/Basic/Targets/AMDGPU.cpp
+4-2clang/lib/Basic/Targets/AMDGPU.h
+2-2clang/lib/Driver/ToolChains/CommonArgs.cpp
+2-1llvm/lib/Target/AMDGPU/AMDGPU.td
+36-186 files

LLVM/project 27cb076mlir/include/mlir/Interfaces ControlFlowInterfaces.h, mlir/lib/Dialect/SCF/IR SCF.cpp

[mlir] Fix RemoveDeadRegionBranchOpSuccessorInputs producing invalid scf.for

RemoveDeadRegionBranchOpSuccessorInputs builds its tied-value sets from
RegionBranchOpInterface::getSuccessorOperandInputMapping, which is derived from
getSuccessorRegions. For an scf.for with a statically-known trip count of 1,
getSuccessorRegions drops the region->region back edge (the loop provably never
iterates back). That back edge is what forwards a yield operand to the region
iter_args, so without it an iter_arg and its corresponding op result are no
longer tied through a shared operand. The pattern then removes a dead iter_arg
without its (structurally required) result, producing an scf.for with
mismatched loop-carried counts:

    'scf.for' op mismatch in number of loop-carried values and defined values

The greedy driver repairs this on a later iteration (InlineRegionBranchOp folds
the single-trip loop), so it is only observed with
MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS, which verifies the IR after every
pattern application. It shows up across Linalg tiling / pack-unpack /
convolution lowering and scf loop canonicalization; see issue #163599.

    [15 lines not shown]
DeltaFile
+29-7mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+24-1mlir/lib/Dialect/SCF/IR/SCF.cpp
+17-2mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+70-103 files

FreeNAS/freenas 3704efb

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 41f3939

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 58f8e60src/middlewared/middlewared/plugins/device_ netlink_events.py, src/middlewared/middlewared/pytest/unit/plugins test_netlink_vendor_restart.py

NAS-142227 / 27.0.0-BETA.1 / Drop kernel address refresh re-announcements in netlink monitor (#19510)

The kernel re-emits RTM_NEWADDR every time a router advertisement
refreshes an address lifetime. Each refresh became an ipaddress.change
event that restarted ix-vendor.service, every few seconds behind routers
with aggressive RA timers.

IFA_CACHEINFO carries creation and update timestamps that are equal only
for a brand new address, so refreshes are dropped at parse time with no
state tracking needed. Messages without cacheinfo pass through and
RTM_DELADDR is never filtered.

Restarts now allow a single waiter on the lock instead of silently
skipping, so the latest address state is always applied without piling
up. Verified against a live kernel on real hardware.

This was pointed out in
https://ixsystems.atlassian.net/browse/NAS-141358 and a fix was proposed
in https://github.com/truenas/middleware/pull/19401. This fix supersedes
that one.
DeltaFile
+173-0src/middlewared/middlewared/pytest/unit/plugins/test_netlink_vendor_restart.py
+59-22src/middlewared/middlewared/plugins/device_/netlink_events.py
+232-222 files

LLVM/project 94a5aa6lldb/packages/Python/lldbsuite/test lldbtest.py, lldb/test/API/functionalities/expr-result-var two-bases.cpp TestCPPExprResult.py

Add a ValueCheck construction method that takes an SBValue (#216208)

Making ValueCheck's can be pretty tedious. But in cases where you are
checking an SBValue that comes from some complex operation, e.g. an
expression evaluation, you can arrange to have the result you expect as
another value in your test program. In that case, it would be much
easier to make a SBValue from the reference object, and then compare the
result against that reference ValueCheck.

This PR adds the valobj based ValueCheck and uses it to replace the
hand-crafted one in TestCPPExprResult.py.

---------

Co-authored-by: Med Ismail Bennani <ismail at bennani.ma>
DeltaFile
+7-60lldb/test/API/functionalities/expr-result-var/TestCPPExprResult.py
+33-12lldb/packages/Python/lldbsuite/test/lldbtest.py
+3-0lldb/test/API/functionalities/expr-result-var/two-bases.cpp
+43-723 files

OPNSense/core 09356f3src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api DNatController.php SourceNatController.php, src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes JsonAuditField.php

ignore audit in import and export
DeltaFile
+8-2src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/SourceNatController.php
+8-2src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/OneToOneController.php
+8-2src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/NptController.php
+8-2src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/FilterController.php
+2-1src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/DNatController.php
+1-0src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes/JsonAuditField.php
+35-96 files

LLVM/project 052e6ffmlir/lib/Dialect/Tosa/Transforms TosaDowngrade1p1To1p0.cpp, mlir/test/Dialect/Tosa verifier.mlir ops.mlir

[mlir][tosa] Add input_unsigned attribute to CAST (#215838)

- Add optional attribute input_unsigned
- Add attributeCheckCast
- Update verification for CAST to reflect new attribute rules

Signed-off-by: Madeleine Dunn <madeleine.dunn at arm.com>
DeltaFile
+81-58mlir/test/Dialect/Tosa/canonicalize.mlir
+33-11mlir/test/Dialect/Tosa/constant_folding.mlir
+18-18mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+21-14mlir/test/Dialect/Tosa/ops.mlir
+16-12mlir/lib/Dialect/Tosa/Transforms/TosaDowngrade1p1To1p0.cpp
+21-5mlir/test/Dialect/Tosa/verifier.mlir
+190-11818 files not shown
+309-16524 files

LLVM/project 7c26749llvm/lib/Target/NVPTX NVPTXPeephole.cpp

NVPTX: Fix using getVRegDef on a physical register (#216735)
DeltaFile
+2-2llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
+2-21 files

LLVM/project 0b02ca0mlir/include/mlir/Dialect/Affine/Analysis NestedMatcher.h

[mlir] Remove dead declarations (#216651)

The corresponding function definitions were removed on March 29, 2019
in 4dc7af9da8837a5f9515c4622e093578fb6ab766
DeltaFile
+0-2mlir/include/mlir/Dialect/Affine/Analysis/NestedMatcher.h
+0-21 files

LLVM/project 782f113compiler-rt/lib/msan/tests msan_test.cpp, compiler-rt/test/fuzzer reload.test

[sanitizer] Skip hanging tests on NetBSD (#216712)

Several sanitizer tests hang indefinitely on NetBSD:

```
MemorySanitizer-Unit :: ./Msan-x86_64-Test
MemorySanitizer-Unit :: ./Msan-x86_64-with-call-Test
MemorySanitizer-X86_64 :: zero_alloc.cpp
ThreadSanitizer-x86_64 :: signal_cond.cpp
libFuzzer-x86_64-default-NetBSD :: reload.test
```

All of them loop and don't time out, so they need to be terminated
manually for `ninja check-all` to complete. To avoid this, this patch
skips the affected tests or subtests. Unfortunately, the Msan unit tests
still hang on exit in `__cxa_finalize` even if all subtests are skipped
with `llvm-lit -gtest_filter=-*`.

Tested on `x86_64-pc-netbsd11.0`, `x86_64-pc-freebsd15.1`, and
`x86_64-pc-linux-gnu`.
DeltaFile
+4-0compiler-rt/lib/msan/tests/msan_test.cpp
+2-0compiler-rt/test/tsan/signal_cond.cpp
+2-0compiler-rt/test/msan/zero_alloc.cpp
+1-0compiler-rt/test/fuzzer/reload.test
+9-04 files

FreeNAS/freenas 21886b4src/middlewared/middlewared/pytest/unit/plugins test_netlink_vendor_restart.py

ruff it
DeltaFile
+3-10src/middlewared/middlewared/pytest/unit/plugins/test_netlink_vendor_restart.py
+3-101 files

LLVM/project 5f81b8dclang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp CIRGenBuilder.h, clang/lib/CIR/Dialect/IR CIRTypes.cpp

[CIR] Derive record padding from the member marks (#215176)r

Now that every record member carries a kind, the record-level `padded`
bool is redundant: a record is padded exactly when some member is marked
pad. Drop the parameter and answer `getPadded()` from the marks.

That also fixes `computeStructDataSize`, which had read the bool as "the
last member is tail padding" and so dropped a real member when padding
sat between two data members. It now drops the trailing run, so an
all-pad record sizes to zero.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+140-0clang/test/CIR/Lowering/copy-skip-tail-padding.cir
+43-47clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+46-11clang/unittests/CIR/RecordMemberKindTest.cpp
+13-28clang/lib/CIR/CodeGen/CIRGenBuilder.h
+15-20clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+16-16clang/test/CIR/IR/invalid-array-structor.cir
+273-12256 files not shown
+449-31462 files

FreeNAS/freenas fbbf635src/middlewared/middlewared/plugins/device_ netlink_events.py, src/middlewared/middlewared/pytest/unit/plugins test_netlink_vendor_restart.py

Drop kernel address refresh re-announcements in netlink monitor

The kernel re-emits RTM_NEWADDR every time a router advertisement
refreshes an address lifetime. Each refresh became an ipaddress.change
event that restarted ix-vendor.service, every few seconds behind
routers with aggressive RA timers.

IFA_CACHEINFO carries creation and update timestamps that are equal
only for a brand new address, so refreshes are dropped at parse time
with no state tracking needed. Messages without cacheinfo pass through
and RTM_DELADDR is never filtered.

Restarts now allow a single waiter on the lock instead of silently
skipping, so the latest address state is always applied without piling
up. Verified against a live kernel on real hardware.
DeltaFile
+180-0src/middlewared/middlewared/pytest/unit/plugins/test_netlink_vendor_restart.py
+59-22src/middlewared/middlewared/plugins/device_/netlink_events.py
+239-222 files

LLVM/project 759e214llvm/lib/Target/NVPTX NVPTXIntrinsics.td

[NVPTX] Cleanup overloaded intrinsic addrspace matching (NFC) (#213110)
DeltaFile
+61-118llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+61-1181 files

FreeBSD/ports f79e23amultimedia/handbrake Makefile

multimedia/handbrake: Update the VPL option description

after "Switch dependency from onevpl to libvpl" in eba41bee20b2.

PR:             297590 293561
Sponsored by:   UNIS Labs
DeltaFile
+1-1multimedia/handbrake/Makefile
+1-11 files

NetBSD/src Rvnvz2Hdoc CHANGES-10.2

   Tickets #1323 - #1327
VersionDeltaFile
1.1.2.124+26-1doc/CHANGES-10.2
+26-11 files

NetBSD/src nr0FrO7sys/external/bsd/dwc2/dist dwc2_core.c

   dwc2: Bring dwc2_wait_for_mode from upstream and use in dwc2_force_mode.

   dwc2_wait_for_mode will wait upto 110milliseconds for the controller
   to enter the expected mode.

   This hopefully fixes

   port-evbarm/60613: Recent dwc2 commit breaks usb based ethernet device...
VersionDeltaFile
1.15+37-3sys/external/bsd/dwc2/dist/dwc2_core.c
+37-31 files

NetBSD/src AOfKu15sys/dev/pci pciconf.c

   Pull up following revision(s) (requested by rin in ticket #1327):

        sys/dev/pci/pciconf.c: revision 1.57
        sys/dev/pci/pciconf.c: revision 1.58
        sys/dev/pci/pciconf.c: revision 1.59

   pciconf: Fix alignments of device memory and I/O resources

   Resources must be their-size-aligned. While here:
   - Switch *align variable from int to more suitable integer types.
   - Make some conditions clearer (NFC).


   pciconf: Fix round-up logics for total sizes of bridge resources

   The previous ones are valid only if alignments are 4K or 1M,
   for I/O or memory, respectively.
   pciconf: Sort resource windows in order of decreasing alignment
   instead of size.

    [8 lines not shown]
VersionDeltaFile
1.55.4.1+34-37sys/dev/pci/pciconf.c
+34-371 files

NetBSD/src fYXfL0Vdoc CHANGES-11.1

   Tickets #411 - #416, #418
VersionDeltaFile
1.1.2.3+45-1doc/CHANGES-11.1
+45-11 files

NetBSD/src ImZzgoEsys/dev/pci pciconf.c

   Pull up following revision(s) (requested by rin in ticket #418):

        sys/dev/pci/pciconf.c: revision 1.57
        sys/dev/pci/pciconf.c: revision 1.58
        sys/dev/pci/pciconf.c: revision 1.59

   pciconf: Fix alignments of device memory and I/O resources

   Resources must be their-size-aligned. While here:
   - Switch *align variable from int to more suitable integer types.
   - Make some conditions clearer (NFC).


   pciconf: Fix round-up logics for total sizes of bridge resources

   The previous ones are valid only if alignments are 4K or 1M,
   for I/O or memory, respectively.
   pciconf: Sort resource windows in order of decreasing alignment
   instead of size.

    [8 lines not shown]
VersionDeltaFile
1.55.12.1+34-37sys/dev/pci/pciconf.c
+34-371 files

FreeBSD/src d383c87contrib/mandoc mdoc.7, share/examples/mdoc example.4

mdoc: Standardize SYNOPISIS section for drivers

Standardize driver manuals on the style used for 12 years in vt(4).
This brings SYNOPSIS across all FreeBSD manual sections into harmony
of meaning where where SYNOPSIS lists available options, and does not
contain prose. Adjust mdoc(7) to reflect the established convention.

Reviewed by:    jhb
Discussed with: arch@ (marc.info/?l=freebsd-arch&m=176782215606871)
Differential Revision:  https://reviews.freebsd.org/D54586
DeltaFile
+27-19share/examples/mdoc/example.4
+8-1contrib/mandoc/mdoc.7
+35-202 files

OPNSense/core 7849091src/opnsense/mvc/app/controllers/OPNsense/Interfaces/Api AssignmentController.php, src/opnsense/mvc/app/controllers/OPNsense/Interfaces/forms dialogAssignment.xml

Interfaces: Assignments - add interface configuration settings in new assignments page. for https://github.com/opnsense/core/issues/10568

Refactor NetworkInterface model to reuse existing property names as much as possible, move from/to legacy logic into a custom fieldtype and store all legacy settings in a container named "pending" to ease reconfiguration and updating legacy configurations.
DeltaFile
+131-0src/opnsense/mvc/app/controllers/OPNsense/Interfaces/forms/dialogAssignment.xml
+66-10src/opnsense/mvc/app/models/OPNsense/Interfaces/NetworkInterface.php
+59-1src/opnsense/mvc/app/models/OPNsense/Interfaces/NetworkInterface.xml
+18-1src/opnsense/scripts/interfaces/apply_pending_if_changes.php
+16-1src/opnsense/mvc/app/views/OPNsense/Interface/assignment.volt
+11-2src/opnsense/mvc/app/controllers/OPNsense/Interfaces/Api/AssignmentController.php
+301-151 files not shown
+302-157 files

FreeBSD/src 557ba0cusr.bin/yes yes.c

yes: Avoid static initialization

Our buffer is half a megabyte, but we are only initializing the first
two bytes.  Switching from static to dynamic initialization moves it
from .data to .bss, greatly reducing the size of the binary.

Fixes:          cf74b63d61b4 ("yes: Completely overengineer")
MFC after:      1 week
Sponsored by:   Klara, Inc.
Reviewed by:    kevans
Differential Revision:  https://reviews.freebsd.org/D58890
DeltaFile
+7-3usr.bin/yes/yes.c
+7-31 files

NetBSD/src DHwo3WCsys/external/bsd/dwc2 dwc2.c

   Backout ticket #417, fallout needs more investigation
VersionDeltaFile
1.81.4.2+0-15sys/external/bsd/dwc2/dwc2.c
+0-151 files

NetBSD/src EqMf2ZYsys/external/bsd/dwc2 dwc2.c

   Pull up following revision(s) (requested by skrll in ticket #417):

        sys/external/bsd/dwc2/dwc2.c: revision 1.84

   PR/60021: USB-only boot: uhub0 attaches but uhub1 never appears...

   Update the dwc2 intial reset sequence to more closely match the upstream
   driver - it's changed a bit in the last 10 years.

   This reset sequence gets the device out of the state it's left in by the

   RaspberryPI firmware when booting from USB.
VersionDeltaFile
1.81.4.1+17-2sys/external/bsd/dwc2/dwc2.c
+17-21 files

NetBSD/src S6qpGiusys/dev/ic bcmgenet.c

   PR kern/60592

   properly move bits to ensure unicast bit and locally administered
   bits were rightly set.

   needs pullup to 11 and 10
VersionDeltaFile
1.25+8-6sys/dev/ic/bcmgenet.c
+8-61 files