[X86] Attempt to fold extract_vector_elt(logicop(x,y),i) -> extract_vector_elt(x,i) (#194581)
When extracting from logicops, we often don't need to extract the result
if one of the element sources is identity (and(x,-1) -> x, or/xor(x,0)
-> x etc.), so this patch uses SimplifyMultipleUseDemandedVectorElts to
peek through to an underlying build_vector.
I had hoped to make this generic, but there's still a lot of yak shaving
to deal with first, as usual - I've included the minimal x86-specific
fixes:
* missing constant folding of (vXi1 logicop(bitcast(c1),bitcast(c2)))
* fold kshiftr(concat_vectors(x,y,z,w),c) -> concat_vectors(z,w,0,0)
Fixes #193700
NAS-140814 / 27.0.0-BETA.1 / Copy VM NVRAM and TPM state on clone (#18828)
## Context
In continuation of the changes made in
https://github.com/truenas/middleware/pull/18764, the same fixes have
been applied to the VM cloning process ensuring that when a VM is cloned
- relevant files are copied over of the VM as well so tpm/secure boot
function as intended.
[flang][pft] visit original symbol in acc use_device (#194588)
Fix regression after https://github.com/llvm/llvm-project/pull/193689
when a use_device is referring to variables from a host module.
The original symbol needs to be visited in the PFT so that it will be
instantiated, but it is not visible anymore from the parse tree, and not
directly connected to the new symbol (this is because variables in
use_device are treated in a special way in order to give them the DEVICE
attribute, other data clause do not need such handling).
Look into the parent scope for a symbol with the same name and visit it.
[AMDGPU] Support Wave Reduction for true-16 types - 3
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
[LoongArch] Support memcmp expansion for vectors and combine for i128/i256 setcc
This commit enables memcmp expansion for lsx/lasx. After doing
this, i128 and i256 loads which are illegal types on LoongArch
will be generated. Without process, they will be splited to
legal scalar type.
So this commit also enable combination for `setcc` to bitcast
i128/i256 types to vector types before type legalization and
generate vector instructions.
Inspired by x86 and riscv.
[DA] Disable the BanerjeeMIV dependence test (#174733)
The various `findBounds` helpers (e.g. `findBoundsLT`) are suspected to
be incorrect because they do not account for potential integer overflow,
which can lead the dependence analysis to produce incorrect results.
Since these helpers are used by the BanerjeeMIV dependence test, this
patch disables BanerjeeMIV by default to avoid unsafe results and
progress the default enablement of DA. The Banerjee test is required for
our motivating example, and we will working on correctness issues and
reenabling it after default enablement.
This is working around issue: #169813
[AMDGPU] Support Wave Reduction for i16 types - 3
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
[AMDGPU] Support Wave Reduction for true-16 types - 2
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
[AMDGPU] Support Wave Reduction for true-16 types - 1
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `min`, `umin`, `max`, `umax`.
Supports only the iterative stratergy, DPP is yet
to be supported.
[AMDGPU] Support Wave Reduction for i16 types - 2
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
[AMDGPU] Support Wave Reduction for i16 types - 1
Supported Ops: `min`, `umin`, `max`, `umax`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
Assisted by - Claude-sonnet:4.6
The dual-pool form of the af-to action, af-to af FROM redirpool pool_opts
TO redirpool pool_opts was writing the TO side options in the FROM side.
OK sashan@
[AMDGPU] Support Wave Reduction for true-16 types - 3
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Revert "[CodeGen] Use SmallMapVector for SpillPlacement::Node::Links" (#194801)
Reverts llvm/llvm-project#194653
This caused a compile-time regression, rather than the expected
improvement.
[ThinLTO] Preserve Unicode characters in module paths when writing the combined-index (#194320)
`IndexBitcodeWriter::writeModStrings()` serializes module path strings
into a `SmallVector<unsigned>` before emitting `MST_CODE_ENTRY` records.
When a path contains UTF-8 bytes with the high bit set, appending from
`StringRef::begin()/end()` can be incorrect. Instead, append the module
path through `bytes_begin()/bytes_end()`, so the bitcode writer always
serializes unsigned bytes.
Fixes: https://github.com/llvm/llvm-project/issues/194318 (#194318)
Based on work by @kbelochapka and @romanova-ekaterina.
graphics/drm-61-kmod: Update to latest version
This fixes compilation with clang21 (defualt on FreeBSD 16)
Sponsored by: Beckhoff Automation GmbH & Co. KG
graphics/drm-66-kmod: Update to latest version
This fixes compilation with clang21 (defualt on FreeBSD 16)
Sponsored by: Beckhoff Automation GmbH & Co. KG
[AMDGPU] Support Wave Reduction for i16 types - 3
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
[AMDGPU] Support Wave Reduction for true-16 types - 2
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
[AMDGPU] Support Wave Reduction for i16 types - 2
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
[AMDGPU] Support Wave Reduction for true-16 types - 1
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `min`, `umin`, `max`, `umax`.
Supports only the iterative stratergy, DPP is yet
to be supported.
[flang] Follow up #192674 Add INLINEALWAYS Directive (#194313)
Following some post merge review comments, this updates the work done in
#192674 based on feedback. It fixes some formatting that was not
conforming, fixes Typo's and updates the new warning's for Semantics
checks.
