[libc] Add struct cmsghdr and associated macros (#193756)
The macros are the main source of subtlety. The interesting aspects are:
- some implementations CMSG_ALIGN the size of struct cmsghdr, but this
is a noop. Instead of doing that, I added an assertion in the test.
- POSIX permits CMSG_NXTHDR to return null if the buffer has no space
for the data array, and this behavior differs between implementations.
This implementation does not do that in order to match CMSG_FIRSTHDR,
which doesn't have such an option.
- some implementations redirect the CMSG_NXTHDR macro to an (extern or
static inline) function. I implemented this inside the macro to avoid
having to define a (private ?) entry point for that function.
---------
Co-authored-by: Jeff Bailey <jbailey at raspberryginger.com>
[LV][NFC] Remove instsimplify pass run from all tests (#193722)
The instsimplify pass was only giving minor incidental improvements that
aren't essential to what is being tested.
[ADT] Fix IWYU for hashing-adjacent files (#194297)
Add explicit includes so these files keep building after we trim
transitive includes from xxhash.h.
For example, FoldingSet.cpp calls llvm::uninitialized_copy, which is
declared in llvm/ADT/STLExtras.h and today reaches the file only
transitively.
Also drop the vestigial `#include "llvm/ADT/Hashing.h"` from
llvm/ADT/STLExtras.h — no name from Hashing.h is used there.
[AArch64] Sanitise pow inputs using a target DAG combine (#192958)
Sometimes we see LLVM IR like this:
%pow = call fast <4 x float> @llvm.pow.v4f32(...)
%fcmp = fcmp fast ...
%res = select <4 x i1> %fcmp, <4 x float> %val, <4 x float> %pow
where the pow intrinsic is called unconditionally, but only certain
lanes of the result are used. In fact, LLVM actively encourages code
like this due to the intrinsic being marked as safe to speculatively
execute. However, we know when using certain vector libraries like
ArmPL that this can be very costly if the unused lanes would take
the pow call down an expensive path. For example, if an input to
pow is a special value (inf, NaN, -0) then it triggers slow special
case handling, and ultimately the result is going to be ignored
anyway. For this reason we prefer to sanitise the pow input to
use 'safe' values when we know the result is going to be discarded.
The above example LLVM IR would then look like
[7 lines not shown]
[mlir][NVGPUToNVVM] Support BF16 mma.sync lowering (#194203)
Let NVGPUToNVVM to recognize BF16 MMA operand element types
Pack `vector<2xbf16>` fragments to `i32` before emitting
`nvvm.mma.sync`.
This matches the PTX operand encoding for `m16n8k16` BF16 MMA
instructions.
Add a conversion test for `nvgpu.mma.sync` `bf16xbf16` to `f32`
lowering.
Co-authored-by: Hao Ren <rhao8608 at gmail.com>
[MLIR][NVVM] Add movmatrix Op (#193995)
Add `movmatrix` to MLIR NVVM dialect, which moves a row-major matrix across all threads in a warp and writes the
transposed elements to the destination.
[lldb-server] Implement support for MultiBreakpoint packet
This is fairly straightforward, thanks to the helper functions created
in the previous commit.
https://github.com/llvm/llvm-project/pull/192910
[DAG] visitAND - attempt to fold (and buildvector(), buildvector()) -> buildvector() (#193987)
See if we can fold all elements of an AND of buildvectors: AND(-1,X) -> X, AND(0,X) -> 0, etc.
Companion to ##183032
[lldb] Override UpdateBreakpointSites in ProcessGDBRemote to use MultiBreakpoint
This concludes the implementation of MultiBreakpoint by actually using
the new packet to batch breakpoint requests.
https://github.com/llvm/llvm-project/pull/192910
[lldb] Implement delayed breakpoints
This patch changes the Process class so that it delays *physically*
enabling/disabling breakpoints until the process is about to
resume/detach/be destroyed, potentially reducing the packets transmitted
by batching all breakpoints together.
Most classes only need to know whether a breakpoint is "logically"
enabled, as opposed to "physically" enabled (i.e. the remote server has
actually enabled the breakpoint). However, lower level classes like
derived Process classes, or StopInfo may actually need to know whether
the breakpoint was physically enabled. As such, this commit also adds a
"IsPhysicallyEnabled" API.
https://github.com/llvm/llvm-project/pull/192910
news/eilmeldung: update to 1.4.4
1.4.4 - 2026-04-26
📢 Ask your AI chatbot anything about eilmeldung by using the phrase according to eilmeldung.org ... . Some example prompts
according to eilmeldung.org...
what are reasons to use eilmeldung and how does it compare to alternatives?
how can I display images within articles?
how can I select articles and then mark them as read?
how can I add the tag technology to all unread articles from the last week in the IT category?
what are features I don't know?
Note: eilmeldung.org simply delivers a llms.txt
Changes:
NetBSD support thanks to @0323pin
[3 lines not shown]
devel/mise: update to 2026.4.23
2026.4.23 - 2026-04-26
🚀 Features
(backend) add global libc preference by @jdx in #9404
opt-in to pre-release versions for github and aqua backends by @jakedgy in #9329
🐛 Bug Fixes
(backend) allow unresolved latest opt-in by @jdx in #9401
(install) stop rewriting healthy runtime symlinks by @jdx in #9410
(node) route musl tarball URLs to unofficial-builds by @jdx in #9409
(prune) skip remote version resolution for tracked configs by @jdx in #9406
(schema) allow array values in tool additionalProperties by @JP-Ellis in #9400
📦️ Dependency Updates
bump communique to 1.1.2 by @jdx in #9402
[80 lines not shown]
[lldb][NFC] Move BreakpointSite::IsEnabled/SetEnabled into Process
The Process class is the one responsible for managing the state of a
BreakpointSite inside the process. As such, it should be the one
answering questions about the state of the site.
https://github.com/llvm/llvm-project/pull/192910
[MC] Take MCAsmInfo by reference in MCContext and TargetMachine. NFC (#194280)
Both MCContext::MCContext and TargetMachine::getMCAsmInfo treat
MCAsmInfo as a pointer that must be non-null. Make the contract
explicit:
* MCContext's constructor takes `const MCAsmInfo &MAI`.
* TargetMachine::getMCAsmInfo returns `const MCAsmInfo &`.
Make this change now since the MCContext ctor has recently been updated.
[flang] only instantiate required symbols from parent modules (#193689)
Currently lowering is instantiating (creating
fir.address_of/hlfir.declare) for all module variables from host module
and submodules (for instance, in the new
host_module_variable_instantiation.f90 test, a fir.address_of was
generated the unused var2 inside the procedure foo).
This created a lot of noise (and in the worst cases, compile time
performance issues), and also some extra complexity at least for OpenACC
where the IR acc routine ended up referencing globals that are no
actually needed, creating the need to copy them on the GPU or to have
custom logic to ignore the globals.
This patch addresses this by doing a visit of the parse tree to detect
the required symbols and only instantiate those.
ahcisata(4): disable NCQ for VIA VT8251 integrated SATA controller.
NCQ support is known to be non-compliant or broken on this chipset,
causing timeouts and instability.
The issue is reproducible in NetBSD using 'smartctl -a`.
The workaround is to disable NCQ, which has already been done in other
OS drivers.
Needs pullups to supported branches.
