Rather than constructing a temporary "hull" LiveInterval and calling the
LiveInterval-based checkInterference overload -- which risks a query-cache
identity hazard when that temporary interval is stack-allocated and reused
across the AllocOrder loop (see the FIXME comment in
LiveRegMatrix::checkInterference(SlotIndex, SlotIndex, MCRegister)) -- this
patch switches the unspilling code to call the slot-index-based
checkInterference(SlotIndex, SlotIndex, MCRegister) overload directly with
the hull's [beginIndex, endIndex).
Doing so exposed a real bug in that overload: LiveRegMatrix.h documents
that returning false means "PhysReg is free at [Start, End)", but the
implementation only checked the matrix of already-assigned virtual
registers. It never checked fixed register-unit interference (e.g. PhysReg
is defined directly by some instruction in [Start, End)) or regmask
interference (e.g. PhysReg is clobbered by a call in [Start, End)) -- both
of which the LiveInterval-based overload does check. This patch adds both
checks to the slot-index-based overload, in the same priority order
(regmask -> regunit -> matrix) as the LiveInterval-based one, bringing the
two implementations in line.
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[LoongArch] Add memory barrier optimization pass (#218597)
Add a machine-level pass to remove redundant DBARs and merge them with
atomic memory operations. The pass uses machine dominator and
post-dominator trees to ensure the transformation is safe across basic
blocks.
[Flang][OpenMP] Remove target implicit allocatable member mapping from MapInfoFinalization and extend lowering to support it (#219434)
This PR aims to remove the partially implemented implicit allocatable
member mapping code from MapInfoFinalization, and move it to the
lowering.
The MapInfoFinalization code should no longer be required as the
DeclareMapper infrastructure in the frontend is capable of handling
these cases now and already does so for the majority of them, so we are
better consolidating the implementation to one location and extending it
to support more cases.
This PR removes the old code from MapInfoFinalization, and enables the
default declare mapper generation that handles most other implicit
mapping cases for derived types in the initial lowering to handle the
previously supported cases and more.
The implicit default declare mapper generation has been modified to only
map the necessary bits of a derived type, which are record types (to
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Enforce the SED entitlement on pool and password paths
This commit adds changes to actually enforce the SED rule, which until now was checked almost nowhere — creating a pool with the all_sed flag had no entitlement check at all. Pool create, update, attach and replace now go through a shared validate_sed_license, and setting a global or per-disk SED password is gated too, though clearing one always works so a system that lost the entitlement can still drop a secret it is no longer allowed to use.
Unlock is deliberately left ungated. A license daemon that errors with anything other than "no license" reads as unlicensed, so gating unlock would turn a daemon hiccup into a failed pool import at boot and a failed unlock on an HA master transition. The drives are already provisioned by that point, so unlocking them grants nothing new. What this enforces is no new SED usage, rather than no SED usage at all.
Require a SED feature key on TrueNAS hardware
This commit adds changes to narrow the SED entitlement so it only resolves on TrueNAS hardware carrying a license with the SED feature key, and to inject that key into legacy licenses so the existing installed base keeps working. Both halves have to land together: narrowing the vector on its own would deny every legacy licensee whose bitmask never carried the SED bit, and their pools would stop unlocking on upgrade. The injection is unconditional because the hardware conjunct lives in the vector, not in the license parser, which stays a pure function of the blob it is handed. This supersedes the earlier decision that allowed the keyless grants.
Enforce the SED entitlement on pool and password paths
This commit adds changes to actually enforce the SED rule, which until now was checked almost nowhere — creating a pool with the all_sed flag had no entitlement check at all. Pool create, update, attach and replace now go through a shared validate_sed_license, and setting a global or per-disk SED password is gated too, though clearing one always works so a system that lost the entitlement can still drop a secret it is no longer allowed to use.
Unlock is deliberately left ungated. A license daemon that errors with anything other than "no license" reads as unlicensed, so gating unlock would turn a daemon hiccup into a failed pool import at boot and a failed unlock on an HA master transition. The drives are already provisioned by that point, so unlocking them grants nothing new. What this enforces is no new SED usage, rather than no SED usage at all.
Require a SED feature key on TrueNAS hardware
This commit adds changes to narrow the SED entitlement so it only resolves on TrueNAS hardware carrying a license with the SED feature key, and to inject that key into legacy licenses so the existing installed base keeps working. Both halves have to land together: narrowing the vector on its own would deny every legacy licensee whose bitmask never carried the SED bit, and their pools would stop unlocking on upgrade. The injection is unconditional because the hardware conjunct lives in the vector, not in the license parser, which stays a pure function of the blob it is handed. This supersedes the earlier decision that allowed the keyless grants.
[RISCV][P-ext] Fold an add of a multiply-parts product into the accumulate form (#222748)
An add of a multiply-parts product selects the accumulating instruction, so
that a loop written with `sum += __riscv_mul_h00_i32(a, b)` gets `macc.h00`
rather than a separate multiply and add.
Rewriting the add before type legalization keeps the shapes whose result is
illegal, so the existing accumulate lowering covers all of them.
[AMDGPU] Invalidate uniformity info after intrinsic combine (#222357)
The uniform intrinsic combine pass changed IR while preserving
uniformity information. Its result keeps references to cycle
information. Those references could be invalidated and later accessed
by another pass.
Invalidate uniformity information after a change. Before erasing an
instruction, remove it from the analysis state used by the pass. Also
report each erasure as a change so invalidation always runs.
x11/babl: Fix build
meson.build:1:0: ERROR: Value "false" (of type "string") for option "gi-docgen" is not one of the choices. Possible choices are (as string): "enabled", "disabled", "auto".
Approved by: blanket (fix build)
Fixes: 90274e2e7fe3 (update to 0.1.128 release)
Sponsored by: UNIS Labs
[AArch64] Form CCMP for CBB and CBH
AArch64ConditionalCompares forms CMP/CCMP chains to transform patterns
such as
Head Head
/ | CmpBB
/ | / |
| CmpBB => / |
| / | Tail |
| / | | |
Tail | | |
| | | |
... ... ... ...
where Head is terminated by a conditional branch and CmpBB contains
a cmp + conditional branch.
We usually try to split any fused conditional branches to be able to
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[RISCV][GlobalISel] Add G_CLMULH support (#221686)
Add G_CLMULH to represent the high half of a carry-less multiplication
in generic Machine IR.
Translate llvm.riscv.clmulh to G_CLMULH and mark it legal for native
XLEN scalar types when Zbkc is available. Reuse the existing
SelectionDAG pattern to select the RISC-V CLMULH instruction.
