LLVM/project 2d16e60llvm/lib/Target/RISCV RISCVISelLowering.cpp

fixup! Do not freeze the operands
DeltaFile
+2-3llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-31 files

LLVM/project 72f5694libc CMakeLists.txt, libc/cmake/modules LLVMLibCTestRules.cmake

[libc] Enable full-build code coverage (#221802)

Extended LIBC_ENABLE_COVERAGE to support LLVM_LIBC_FULL_BUILD=ON and
added the LIBC_ENABLE_COVERAGE_MCDC CMake option for MC/DC coverage.

This enables developers and CI pipelines to measure source-level and
MC/DC coverage directly on hermetic tests in full-build configurations
without relying on the host C library.

Updated add_libc_hermetic in LLVMLibCTestRules.cmake to link hermetic
tests with -noprofilelib, -u__llvm_profile_runtime, and compiler-rt's
profiling library. Replaced internal entrypoint objects in
link_object_files with public entrypoint objects for the C functions
referenced by libclang_rt.profile.a.

Added calloc and __errno_location to HermeticTestUtils.cpp to satisfy
remaining freestanding profiling runtime dependencies. Updated
libc/docs/dev/code_coverage.md with full-build instructions.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+140-62libc/docs/dev/code_coverage.md
+77-0libc/cmake/modules/LLVMLibCTestRules.cmake
+32-6libc/CMakeLists.txt
+22-0libc/test/UnitTest/HermeticTestUtils.cpp
+2-0libc/test/UnitTest/CMakeLists.txt
+273-685 files

FreeBSD/ports 1acab53www/angelfish distinfo, www/falkon distinfo

KDE: Update KDE Gear to 26.08.1

Announcement: https://kde.org/announcements/gear/26.08.1/
DeltaFile
+3-3x11-fm/konqueror/distinfo
+3-3x11-fm/dolphin/distinfo
+3-3x11-clocks/ktimer/distinfo
+3-3x11-clocks/kteatime/distinfo
+3-3www/falkon/distinfo
+3-3www/angelfish/distinfo
+18-18229 files not shown
+700-693235 files

FreeBSD/ports e80c17earchivers/kf6-karchive distinfo, deskutils/kf6-kstatusnotifieritem distinfo

KDE: Update KDE Frameworks 6 to 6.30.0

Announcement: https://kde.org/announcements/frameworks/6/6.30.0/
DeltaFile
+0-52misc/kf6-purpose/pkg-plist
+33-3x11-themes/oxygen-icons/pkg-plist
+32-0x11-themes/kf6-breeze-icons/pkg-plist
+18-0net/kf6-kcalendarcore/pkg-plist
+3-3deskutils/kf6-kstatusnotifieritem/distinfo
+3-3archivers/kf6-karchive/distinfo
+89-6177 files not shown
+306-27483 files

LLVM/project 20ddf3ecompiler-rt/lib/fuzzer FuzzerMerge.cpp FuzzerFlags.def, compiler-rt/test/fuzzer fuzzer-oom-with-profile.test fuzzer-dirs.test

[libFuzzer] Use uppercase "B" for byte units in output (#220828)

Fixes issue #56766. libFuzzer printed data sizes as "b", "Kb" and "Mb",
which denote bits. Use "B", "KB" and "MB" instead.
DeltaFile
+14-14llvm/docs/LibFuzzer.md
+7-7compiler-rt/lib/fuzzer/FuzzerLoop.cpp
+1-1compiler-rt/test/fuzzer/fuzzer-oom-with-profile.test
+1-1compiler-rt/test/fuzzer/fuzzer-dirs.test
+1-1compiler-rt/lib/fuzzer/FuzzerMerge.cpp
+1-1compiler-rt/lib/fuzzer/FuzzerFlags.def
+25-251 files not shown
+26-267 files

LLVM/project fd00fafllvm/lib/CodeGen/SelectionDAG LegalizeDAG.cpp, llvm/test/CodeGen/RISCV ctselect-fallback-gisel.ll ctselect-fallback-scalable.ll

[ConstantTime] Use ARITH_FENCE as the combine barrier in CT_SELECT expansion

Replace the CopyToReg/CopyFromReg vreg barrier in ExpandCTSELECT with
ISD::ARITH_FENCE. The legalizer no longer creates vregs or picks register
classes via getRegClassFor, and scalable vectors are now covered too.
Codegen tests regenerated; output stays branchless.
DeltaFile
+945-702llvm/test/CodeGen/X86/ctselect.ll
+232-144llvm/test/CodeGen/RISCV/ctselect-fallback.ll
+5-25llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+8-0llvm/test/CodeGen/RISCV/ctselect-fallback-scalable.ll
+2-0llvm/test/CodeGen/RISCV/ctselect-fallback-gisel.ll
+1,192-8715 files

LLVM/project 36ecd98llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU fix-sgpr-copies-f16-true16.mir v_swap_b16.ll

[AMDGPU][SIInstrInfo] Materialise t16 PHI subreg operands
DeltaFile
+1,527-1,045llvm/test/CodeGen/AMDGPU/frem.ll
+20-26llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
+18-7llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+8-2llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+1,573-1,0804 files

LLVM/project cf879a1llvm/lib/Target/AMDGPU SIInstrInfo.cpp

Refactor `ExpectedRC` determination
DeltaFile
+20-10llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+20-101 files

LLVM/project 903001allvm/test/CodeGen/AMDGPU fix-sgpr-copies-f16-true16.mir

[NFC][AMDGPU] Pre-commit test that exposes subreg copies into PHI nodes
DeltaFile
+68-0llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+68-01 files

LLVM/project 98b04e5clang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/CodeGen/PowerPC aix-vec-extabi-module-flag.c

PPC: Replace EnableAIXExtendedAltivecABI with "target-abi" module flag

Continue purging ABI-influencing TargetOptions fields. Eliminate this case
by migrating to a module flag, reusing the generic target-abi module flag
with a new value.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+22-21llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+10-16llvm/include/llvm/Target/TargetOptions.h
+12-12llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll
+18-0clang/test/CodeGen/PowerPC/aix-vec-extabi-module-flag.c
+13-0flang/test/Integration/PowerPC/aix-vec-extabi.f90
+0-11clang/lib/Driver/ToolChains/CommonArgs.cpp
+75-6076 files not shown
+199-19782 files

LLVM/project 5ade766llvm/lib/Target/PowerPC PPC.h PPCSubtarget.h, llvm/test/CodeGen/PowerPC target-abi-module-flag.ll

PPC: Read the ELF ABI from the "target-abi" module flag

Resolve the ELFv2 ABI from the effective ABI name module flag,
rather than strictly relying on the -target-abi flag.

Also start emitting "target-abi" for PPC from clang.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+37-0llvm/test/CodeGen/PowerPC/target-abi-module-flag.ll
+18-17llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+5-3llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+4-3llvm/lib/Target/PowerPC/PPCTargetMachine.h
+4-1llvm/lib/Target/PowerPC/PPCSubtarget.h
+4-0llvm/lib/Target/PowerPC/PPC.h
+72-245 files not shown
+79-3011 files

OpenBSD/ports y7lwbKRlang/erlang/28 distinfo Makefile

   lang/erlang/28: Update to 28.5.0.6

   Fixes CVE-2026-75538

   ok sthen@
VersionDeltaFile
1.16.2.6+15-15lang/erlang/28/Makefile
1.15.2.4+4-4lang/erlang/28/distinfo
+19-192 files

OpenBSD/ports TqnQn31lang/elixir Makefile distinfo

   lang/elixir: Update to 1.19.6

   Fixes CVE-2026-75758

   ok sthen@
VersionDeltaFile
1.74.2.1+2-2lang/elixir/distinfo
1.87.2.1+1-2lang/elixir/Makefile
+3-42 files

LLVM/project 5b757b8libcxx/include/__configuration compiler.h, libcxx/include/__memory unique_temporary_buffer.h allocator.h

[libc++] Remove __libcpp_allocate (#220981)

We use `__libcpp_allocate` and friends only in very specific
circumstances. Instead of providing a private API we can make
`std::allocator` the default API for the uses of `__libcpp_allocate`.
DeltaFile
+0-252libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+0-78libcxx/include/__new/allocate.h
+23-12libcxx/include/__memory/allocator.h
+15-4libcxx/include/__memory/unique_temporary_buffer.h
+3-3libcxx/include/__utility/small_buffer.h
+6-0libcxx/include/__configuration/compiler.h
+47-34912 files not shown
+63-36418 files

LLVM/project 2f1a132llvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.alignbyte.ll true16-fold.mir

fold sgpr32 via vgpr16
DeltaFile
+116-12llvm/test/CodeGen/AMDGPU/true16-fold.mir
+26-58llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+57-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+4-11llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
+206-861 files not shown
+207-887 files

LLVM/project e4671adllvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU lit.local.cfg

add machine verifier check
DeltaFile
+84-3llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+2-0llvm/test/CodeGen/AMDGPU/lit.local.cfg
+89-33 files

LLVM/project 7f600d5llvm/test/CodeGen/AMDGPU llvm.amdgcn.image.d16.dim.ll float-to-arbitrary-fp-fp8-hw.ll

fix pattern
DeltaFile
+8,380-0llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
+1,481-1,527llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+1,021-1,456llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+172-359llvm/test/CodeGen/AMDGPU/bf16.ll
+210-215llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+359-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
+11,623-3,55735 files not shown
+12,823-4,56841 files

LLVM/project c820be7llvm/test/CodeGen/AMDGPU flat-atomicrmw-fmax.ll flat-atomicrmw-fadd.ll

rebase and update test
DeltaFile
+2,102-1,533llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,576-1,609llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+1,514-1,093llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+1,141-782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+7,417-7,20746 files not shown
+14,545-17,68152 files

LLVM/project 6a98c13llvm/test/CodeGen/AMDGPU fptoui-sat-scalar.ll usubsat.ll, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.raw.tbuffer.store.f16.ll combine-fma-add-fma-mul.ll

update test
DeltaFile
+434-434llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
+146-218llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+106-170llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+134-134llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+42-89llvm/test/CodeGen/AMDGPU/usubsat.ll
+13-41llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+875-1,0869 files not shown
+1,006-1,26315 files

LLVM/project 6a24ff3llvm/test/CodeGen/AMDGPU global-atomicrmw-fmin.ll global-atomicrmw-fadd.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-llvm.amdgcn.image.sample.a16.ll

calling conv update
DeltaFile
+1,777-2,342llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,241-1,664llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+927-1,291llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+748-1,428llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+1,248-856llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+1,251-722llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+7,192-8,303158 files not shown
+22,916-20,214164 files

LLVM/project c41fbc7llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll amdgcn.bitcast.1024bit.ll

rebase and update test
DeltaFile
+16,867-9,815llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,158-3,995llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,025-13,8102 files

LLVM/project 286b832llvm/test/CodeGen/AMDGPU atomicrmw_usub_sat.ll

rebase and update test
DeltaFile
+8-0llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
+8-01 files

LLVM/project 6aa887cllvm/lib/Target/AMDGPU SIFixSGPRCopies.cpp, llvm/test/CodeGen/AMDGPU fix-sgpr-copies-f16-true16.mir

fix change vgpr32 to sreg32 in fix-sgpr-copy pass
DeltaFile
+27-0llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+23-1llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+50-12 files

LLVM/project 90bd765llvm/test/CodeGen/AMDGPU amdgcn.bitcast.320bit.ll amdgcn.bitcast.704bit.ll

Legalize sgpr16 in sdag
DeltaFile
+5,708-2,866llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+5,324-2,688llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+4,942-2,490llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+4,556-2,294llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+4,172-2,110llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
+4,149-2,025llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+28,851-14,473120 files not shown
+62,762-38,918126 files

LLVM/project b4fdbf8llvm/lib/Target/AMDGPU SIInstrInfo.cpp

clang-format change
DeltaFile
+4-10llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+4-101 files

LLVM/project a2f0df2llvm/test/CodeGen/AMDGPU fptoui-sat-vector.ll fptosi-sat-vector.ll

clean up
DeltaFile
+288-153llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+154-154llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
+130-175llvm/test/CodeGen/AMDGPU/half.ll
+0-226llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+142-70llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+114-56llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+828-8345 files not shown
+914-91411 files

LLVM/project 6e1d294llvm/include/llvm/Frontend/Directive DirectiveBase.td, llvm/include/llvm/Frontend/OpenMP OMP.td

[OpenMP] Change association of some directives from "none" to "explicit"

Certain declarative directives are associated with base language
declarations by having the declared entities explicitly listed as
arguments.

Previously these had "none" in OMP.td. Change them to "explicit"
to be consistent with the spec. The existing code does not require
any changes, since the only potentially affected code would be that
which checked the assocation for "none", and the only such cases
were applied to executable directives.
DeltaFile
+4-4llvm/include/llvm/Frontend/OpenMP/OMP.td
+2-1llvm/test/TableGen/directive2.td
+2-1llvm/test/TableGen/directive1.td
+2-0llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
+1-0llvm/include/llvm/Frontend/Directive/DirectiveBase.td
+11-65 files

LLVM/project a56fd54mlir/include/mlir/Tools/mlir-translate MlirTranslateMain.h, mlir/lib/Tools/mlir-translate MlirTranslateMain.cpp

[mlir-translate] Add structured translation entry point (#222623)

Please read: [RFC: Embeddable LLVM tool drivers for long-lived
hosts](https://discourse.llvm.org/t/rfc-embeddable-llvm-tool-drivers-for-long-lived-hosts/91754)
and the [MLIR
section](https://discourse.llvm.org/t/rfc-embeddable-llvm-tool-drivers-for-long-lived-hosts/91754#p-367966-mlir-13).

`mlir-opt` already separates its standalone command-line frontend from
its reusable implementation:

```text
command-line parsing
        ↓
MlirOptMainConfig
        ↓
MlirOptMain(input buffer, output stream, registry, config)
```

`mlir-translate` currently combines those responsibilities inside

    [36 lines not shown]
DeltaFile
+108-71mlir/lib/Tools/mlir-translate/MlirTranslateMain.cpp
+70-0mlir/include/mlir/Tools/mlir-translate/MlirTranslateMain.h
+178-712 files

LLVM/project 9d4a7d0clang/lib/Basic LangOptions.cpp, clang/lib/CodeGen BackendUtil.cpp

CodeGen: Remove AllowFPOpFusion from TargetOptions (#222683)
DeltaFile
+0-26llvm/include/llvm/Target/TargetOptions.h
+0-16clang/lib/CodeGen/BackendUtil.cpp
+0-14llvm/lib/CodeGen/CommandFlags.cpp
+0-12llvm/test/CodeGen/X86/llc-fp-contract-warning.ll
+0-8clang/lib/Basic/LangOptions.cpp
+4-4llvm/lib/Target/SPIRV/SPIRVAPI.cpp
+4-803 files not shown
+5-899 files

LLVM/project e8c833bmlir/lib/Conversion/XeGPUToXeVM XeGPUToXeVM.cpp, mlir/test/Conversion/XeGPUToXeVM extf_truncf.mlir

[MLIR][XeGPU] Lower arith.truncf wider than one xevm.truncf group (#217130)

`xevm.truncf` lowers to device builtins that convert exactly 16 f16/bf16
elements
per call, so `TruncfToXeVMPattern` only matched a 16-element source. A
workgroup-level mxfp GEMM that quantizes A in the kernel produces a
wider one,
which nothing else lowers, so the module failed to build:

  %r = arith.truncf %a : vector<32xbf16> to vector<32xf4E2M1FN>
// cannot be converted to LLVM IR: missing
`LLVMTranslationDialectInterface`
  // registration ... for op: arith.truncf

Convert a whole number of groups at a time instead: slice the source
into
16-element groups, emit one `xevm.truncf` per group, and concatenate the
packed
results before the final bitcast. A source of exactly one group takes

    [7 lines not shown]
DeltaFile
+41-14mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
+38-0mlir/test/Conversion/XeGPUToXeVM/extf_truncf.mlir
+79-142 files