[lld-macho] Collect markLive roots in parallel
With the traversal parallel, most of markLive's remaining time goes to
the serial loops around it: finding the GC roots, which visits every
global symbol, every object file's local symbols and every input
section, and the S_ATTR_LIVE_SUPPORT scan over every input section.
Run those loops on all threads. The type-erased MarkLive interface now
takes a shard index with each root: each thread adds the roots it finds
to its own shard, and moves them to nextLevel after every chunk, so with
one thread the order is unchanged. The live-support scan does the same
with the sections it marks live, reading the live bits of sections that
other threads may be marking at the same time through the thread-safe
isLive(). A live-support section that refers only to another one marked
by the same scan may be found by the next iteration of the loop around
it instead; the final live set is the same.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
allwinner: a33: Fix the pin number of PE17
The PE17 entry of the pad table of the A33 had the pin number 16, the
one of PE16, so the pinctrl of PE17 configured PE16 and a <&pio 4 17>
specifier could not be mapped.
Reported by: llm-postcr
Fixes: cf72965fbf02 ("Allwinner: Add A33 support")
aw_ccu: h6: Allow the IR and W1 clocks to change their parent
The IR clock was defined without AW_CLK_REPARENT, so only the current
parent was used to find a rate. The firmware leaves the mux on osc32k,
from which the best rate is 32768Hz, and aw_cir asks for exactly 3MHz,
which osc24M can give. The request failed and r_ir did not attach. Do
the same as the main CCU for the CIR-TX clock and let the clock use the
best parent, and do the same for the 1-wire clock which is the same.
Reported by: llm-postcr
Fixes: 69919babdac7 ("aw_ccu: h6: Add the IR, W1, RSB and RTC clocks of the R CCU")
Tested on: H6
axp81x: Fix the number of steps of the first range of DCDC5
The voltage of DCDC5 goes from 800mV to 1120mV in 10mV steps with the
codes 0x00 to 0x20, then from 1140mV to 1840mV in 20mV steps with the
codes 0x21 to 0x44. The first range has 32 steps and not 42, so every
code above 32 was decoded and encoded wrongly: the driver read 1160mV
for the 1.2V that the firmware sets for the DRAM, did not see it in the
range of the FDT and wrote a code that is really 1280mV. The same
happens for the other voltages, 1.36V is set to 1.46V and 1.5V to 1.6V.
It also made the voltage reported for the regulator wrong.
Reported by: llm-postcr
Fixes: c175fd0fe8a3 ("axp81x: Add support for AXP803")
Tested on: A64
aw_ccu: h616: Set the lock enable bit of the PLLs
The lock status bit of a PLL is only updated when its lock enable bit,
bit 29, is set, and the firmware only sets it for the PLLs it uses.
Enabling another PLL, or changing the rate of an enabled one, then
waited for a lock that never came and ended after a second with an
error. Set the bit on all the PLLs when attaching, like Linux does.
Reported by: llm-postcr
Fixes: 92b59f3d010d ("aw_clk: Wait for the PLL to lock when enabling it")
axp209: Allow the interrupt handler to sleep
The interrupt handler reads and writes the registers of the PMU with
IIC_INTRWAIT, which can sleep when the bus is busy, and the I2C
controller the AXP209 is on in the A10 and A20 waits for the end of the
transfer. The handler runs in an interrupt thread, which cannot sleep
unless the interrupt is marked as sleepable, so an interrupt of the PMU
would panic a kernel with INVARIANTS. Mark it, the interrupt is not
shared, like it was done for the axp81x driver.
Reported by: llm-postcr
Fixes: 30068a1de9e3 ("Add support for interrupts, sensors and GPIO for AXP209 PMIC")
allwinner: a31s: Fix the pin number of PH28
The PH28 entry of the pad table of the A31s had the pin number 27, the
one of PH27, so the pinctrl of PH28 configured PH27 and a <&pio 7 28>
specifier could not be mapped. This was fixed for the A31 in
222947a74223 but not in the copy for the A31s.
Reported by: llm-postcr
Fixes: ccf8caad1413 ("Add the Allwinner A31 and A31s padconf support. It's currently unused, but")
aw_gpio: Return the error when an interrupt cannot be mapped
aw_gpio_pic_map_intr() returned success without setting the interrupt
source when aw_gpio_pic_map_gpio() failed, which happens for a pin that
has no interrupt function or for an unsupported mode. The caller then
went on with an uninitialized pointer. Return the error.
Reported by: llm-postcr
Fixes: 0fe5379c6a99 ("arm: allwinner: Add GPIO Interrupt support")
allwinner: h616: Put the PI pins in bank 8
The PI0 to PI16 entries of the pad table had port 9 and interrupt bank 9
but the PI bank is the ninth one, bank 8, at offset 0x120. Bank 9 is a
bank that does not exist, so the configuration, data, drive and pull of
these pins, and their interrupt registers, were accessed at the wrong
place and a <&pio 8 N> specifier, like the one of the card detect GPIO
of some boards, did not find its pin.
Use 8 for the port and the interrupt bank, like the other entries do
with the position of their letter.
Reported by: llm-postcr
Fixes: e506af08bb52 ("aw_gpio: Add support for H616")
aw_ccu: d1: Set the lock enable bit of the PLLs
The lock status bit of a PLL is only updated when its lock enable bit,
bit 29, is set, and the firmware only sets it for the PLLs it uses.
Enabling another PLL, or changing the rate of an enabled one, then
waited for a lock that never came and ended after a second with an
error. Set the bit on all the PLLs when attaching, like Linux does.
Reported by: llm-postcr
Fixes: 92b59f3d010d ("aw_clk: Wait for the PLL to lock when enabling it")
[lld][MachO] Skip relinking -object_path_lto files that already match the cache (#237099)
On an incremental ThinLTO link the object file from the previous link is
usually already a hardlink to the same cache entry. Compare the two
before touching anything, and take the modification time from the status
that is already at hand instead of stat'ing the result again. The output
path is also saved once up front and passed around as a StringRef
instead of being copied for each use.
On a 47k-module incremental ThinLTO link, saveOrHardlinkBuffer drops
from 5% of link time to 0.3%.
Also stop a link without -cache_path_lto from overwriting cache entries
through hardlinks left in -object_path_lto.
nd6: keep foreign-CPU neighbors off the timer and purge list
Route requests create neighbor entries on each network CPU, but timers
and purge run on CPU 0. Purging a foreign-CPU entry deletes the matching
local route and can follow its freed neighbor entry. Link only CPU 0
entries into the list and unlink only linked entries; keep other CPUs
route-local neighbor data.
Bug: https://bugs.dragonflybsd.org/issues/3439
pf.conf.5: describe IPv6 fragment filtering without reassembly
IPv6 fragments are filtered as the Fragment header protocol, not blocked
unconditionally. State that port/type rules cannot pass them and that a
broad pass rule does not enforce those restrictions.
Bug: https://bugs.dragonflybsd.org/issues/3438
netinet: fix ARP resolution during the first second of uptime
A cloned route created while time_uptime is zero passes a zero expiry
to its neighbors. Zero denotes a permanent entry, so unresolved dynamic
neighbors never send ARP requests.
Add the arp_expire_unresolved (= time_uptime + 1) to keep dynamic expiry
nonzero and track the last request time separately, using la_asked to
indicate whether that time is valid. This preserves same-second rate
limiting and permanent-entry semantics without changing the routing ABI.
While there, fix the code to add arpt_down to rt_expire only when it's a
cloned route.
Co-authored-by: Aaron LI <aly at aaronly.me>
GitHub-PR: https://github.com/DragonFlyBSD/DragonFlyBSD/pull/58
dsynth - Do not cross mount boundaries when making template's /etc
* When making the template's /etc, do not cross mount boundaries.
* This is a bit of a hack but /etc/namedb sometimes has a "dev"
subdirectory for its chroot area that mounts devfs. This kinda
implodes when we later try to tmpfs it.
