LLVM/project 3c205edlibc/AOR_v20.02/math/test/traces sincosf.txt exp.txt, llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll memory-legalizer-private-wavefront.ll

Merge branch 'main' into users/modiking/nvptx-reverse-branch-condition
DeltaFile
+0-31,999libc/AOR_v20.02/math/test/traces/sincosf.txt
+0-16,000libc/AOR_v20.02/math/test/traces/exp.txt
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,432-6,562llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+4,582-5,914llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+8,836-1,658llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+26,685-68,93114,032 files not shown
+1,134,048-601,76514,038 files

LLVM/project ca318abllvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlanConstruction.cpp, llvm/test/Transforms/LoopVectorize early-exit-calls.ll early-exit-unary-ops.ll

Reapply "[VPlan] Handle calls in VPInstruction:opcodeMayReadOrWriteFromMemory." (#191886)

This reverts commit
https://github.com/llvm/llvm-project/commit/3bf9639ec04544902670ab4199401ac470c1fcca.

The reapply adds trivial support for ExtractValue and InsertValue to fix
the crash causing the revert.

Original message:

Retrieve the called function and check its memory attributes, to
determine if a VPInstruction calling a function reads or writes memory.

Use it to strengthen assert in areAllLoadsDereferenceable.

PR: https://github.com/llvm/llvm-project/pull/190681
DeltaFile
+74-0llvm/test/Transforms/LoopVectorize/early-exit-calls.ll
+70-0llvm/test/Transforms/LoopVectorize/early-exit-unary-ops.ll
+27-8llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+4-2llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+175-104 files

LLVM/project d40b508llvm/lib/Transforms/Instrumentation HWAddressSanitizer.cpp

error handling

Created using spr 1.3.7
DeltaFile
+12-5llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+12-51 files

LLVM/project 39fbbbaclang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsage.h, clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel EntityPointerLevel.cpp

fix format
DeltaFile
+0-6clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.h
+2-1clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
+2-72 files

LLVM/project 1e89261llvm/lib/Transforms/Instrumentation HWAddressSanitizer.cpp, llvm/test/Instrumentation/HWAddressSanitizer alloca.ll

review comment

Created using spr 1.3.7
DeltaFile
+6-4llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+1-1llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
+7-52 files

OPNSense/tools bc4ce3econfig/26.1 make.conf plugins.conf

remove zabbix 7.2 EOL
DeltaFile
+0-2config/26.1/make.conf
+0-2config/26.1/plugins.conf
+0-2config/26.1/ports.conf
+0-63 files

OPNSense/plugins acf0c92net-mgmt/zabbix-proxy Makefile

net-mgmt/zabbix-proxy: remove leftover
DeltaFile
+1-1net-mgmt/zabbix-proxy/Makefile
+1-11 files

OPNSense/plugins 6102a99net-mgmt/zabbix-agent Makefile pkg-descr, net-mgmt/zabbix-proxy Makefile pkg-descr

remove Zabbix 7.2 EOL (#5403)
DeltaFile
+2-5net-mgmt/zabbix-agent/Makefile
+5-0net-mgmt/zabbix-agent/pkg-descr
+1-4net-mgmt/zabbix-proxy/Makefile
+4-0net-mgmt/zabbix-proxy/pkg-descr
+12-94 files

LLVM/project 9962180llvm/lib/Target/AMDGPU AMDGPULowerModuleLDSPass.cpp, llvm/test/CodeGen/AMDGPU lower-module-lds-link-time-classify.ll lower-module-lds-link-time-multi-kernel.ll

[AMDGPU] Add object linking support for LDS and named barrier lowering in the middle end

This is the first patch in a series introducing object linking support for
AMDGPU.

This PR adds the -amdgpu-enable-object-linking flag to enable object linking in
the backend. It also updates the AMDGPULowerModuleLDSPass and
AMDGPULowerExecSync passes to support lowering LDS and named barrier globals
when object linking is enabled.
DeltaFile
+163-0llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+73-0llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-classify.ll
+62-0llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-multi-kernel.ll
+52-0llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-multi-lds-per-func.ll
+50-0llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-internal-multi-user.ll
+50-0llvm/test/CodeGen/AMDGPU/lower-module-lds-link-time-transitive.ll
+450-06 files not shown
+619-012 files

NetBSD/pkgsrc-wip aa19f5flabwc Makefile, lxqt-wayland-session Makefile

*: update some paths after imports
DeltaFile
+3-3sway/Makefile
+2-2labwc/Makefile
+1-1lxqt-wayland-session/Makefile
+1-1plasma6-kwin-x11/Makefile
+1-1slurp/Makefile
+1-1wayvnc/Makefile
+9-95 files not shown
+14-1411 files

LLVM/project b79b68fllvm/test/CodeGen/NVPTX machine-cse-predicate-inversion-float16.ll machine-cse-predicate-inversion-bfloat16.ll

[NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates

Inverted predicates can be used freely in PTX. If we can invert a
predicate and CSE the generating instruction we can save calculating
the inverse.

Teach the NVPTX commuteInstructionImpl that SETP instructions can be
inverted to allow CSEing with previous SETP that match the inverted
form. This also inverts the branch users of the predicate to maintain
correctness.

Currently only allow the SETP inversion if all users are branches.
Future work can extend this to sel and not instructions.

Made-with: Cursor
DeltaFile
+695-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
+695-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
+679-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
+663-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
+437-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
+437-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
+3,606-013 files not shown
+5,920-219 files

LLVM/project d3114dcllvm/lib/Target/NVPTX NVPTXInstrInfo.cpp NVPTXInstrInfo.h, llvm/test/CodeGen/NVPTX jump-table.ll i128.ll

[NVPTX] Add reverseBranchCondition and CBranchOther

Add CBranchOther instruction for inverted predicate branches (@!p bra)
and implement reverseBranchCondition to support branch condition
inversion. Update analyzeBranch, insertBranch, and removeBranch to
handle both CBranch and CBranchOther.

This enables passes like branch folding to properly reverse branch
conditions, and is a prerequisite for SETP predicate inversion CSE.

Made-with: Cursor
DeltaFile
+24-31llvm/test/CodeGen/NVPTX/jump-table.ll
+16-20llvm/test/CodeGen/NVPTX/i128.ll
+25-8llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+2-0llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
+2-0llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+69-595 files

LLVM/project c9f175bmlir/include/mlir/Dialect/SPIRV/IR SPIRVIntelExtOps.td SPIRVBase.td, mlir/lib/Dialect/SPIRV/IR SPIRVTypes.cpp

[mlir][SPIR-V] Add support for SPV_INTEL_masked_gather_scatter extension (#189099)

Add MaskedGather/MaskedScatter ops and VectorOfPointerType for
SPV_INTEL_masked_gather_scatter extension implemented in #185418
DeltaFile
+134-0mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir
+134-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td
+60-0mlir/test/Target/SPIRV/intel-ext-ops.mlir
+14-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+4-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h
+2-1mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
+348-56 files

NetBSD/pkgsrc YxU5iBEdoc TODO

   doc/TODO: + mold-2.41.
VersionDeltaFile
1.27090+2-1doc/TODO
+2-11 files

LLVM/project 10d5a4fcompiler-rt/lib/tysan tysan.cpp tysan_interceptors.cpp

Revert "[TySan][Sanitizer Common] Make TySan compatible with sanitizer common…"

This reverts commit d043b9e38dd9494c3c56018b2cbaf44fe205b110.
DeltaFile
+7-33compiler-rt/lib/tysan/tysan.cpp
+1-33compiler-rt/lib/tysan/tysan_interceptors.cpp
+8-662 files

LLVM/project 7099c02llvm/test/CodeGen/AMDGPU minmax3-tree-reduction.ll

[AMDGPU] Update minmax3-tree-reduction.ll for true16. NFC (#191879)
DeltaFile
+64-26llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
+64-261 files

FreeBSD/ports 2891a38science/openmolcas distinfo Makefile, science/openmolcas/files patch-src_linalg__util_linalg__mod.F90 patch-src_mma__util_cgetshmem.c

science/openmolcas: update 25.10 → 26.02
DeltaFile
+0-21science/openmolcas/files/patch-src_linalg__util_linalg__mod.F90
+7-7science/openmolcas/distinfo
+0-11science/openmolcas/files/patch-src_mma__util_cgetshmem.c
+4-4science/openmolcas/Makefile
+11-434 files

FreeBSD/ports 6bd2552misc/free42 distinfo Makefile

misc/free42: update 3.3.10 → 3.3.11
DeltaFile
+3-3misc/free42/distinfo
+1-1misc/free42/Makefile
+4-42 files

FreeBSD/ports c7b7830misc/py-comfyui-workflow-templates-media-other distinfo Makefile

misc/py-comfyui-workflow-templates-media-other: update 0.3.169 → 0.3.170
DeltaFile
+3-3misc/py-comfyui-workflow-templates-media-other/distinfo
+1-1misc/py-comfyui-workflow-templates-media-other/Makefile
+4-42 files

FreeBSD/ports decaaa8misc/ollama pkg-message

misc/ollama: Update pkg-message
DeltaFile
+5-2misc/ollama/pkg-message
+5-21 files

FreeBSD/ports d677f8dmisc/py-comfyui-workflow-templates-media-video distinfo Makefile

misc/py-comfyui-workflow-templates-media-video: update 0.3.75 → 0.3.76
DeltaFile
+3-3misc/py-comfyui-workflow-templates-media-video/distinfo
+1-1misc/py-comfyui-workflow-templates-media-video/Makefile
+4-42 files

FreeBSD/ports 056ba6emisc/py-comfyui-workflow-templates Makefile distinfo

misc/py-comfyui-workflow-templates: update 0.9.48 → 0.9.49
DeltaFile
+4-4misc/py-comfyui-workflow-templates/Makefile
+3-3misc/py-comfyui-workflow-templates/distinfo
+7-72 files

LLVM/project 7d383ecmlir/include/mlir/Dialect/XeGPU/Transforms XeGPULayoutImpl.h, mlir/lib/Dialect/XeGPU/IR XeGPUDialect.cpp

[MLIR][XeGPU] Adding Layout Utility inferMaskOffsetLayoutForScatterIO (#191573)

This PR add a new layout utility function, named
inferMaskOffsetLayoutForScatterIO(), to support the propagation and
lowering of XeGPU scatter IO operations.
DeltaFile
+17-52mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
+6-32mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+6-7mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+11-0mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+6-0mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h
+1-1mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+47-926 files

FreeBSD/ports c8196a0sysutils/nut-devel/files patch-configure.ac, sysutils/nut/files patch-configure

sysutils/nut*: Fix configure when user uses the uucp user account

Users wanting to use the uucp user account will experience configure
faiures because uucp is baked into the configure script. We make the
configure script default to "nothing" to address this edge case. The
default user (nut) is already set by the port and ports plumbing.

PR:     294350
DeltaFile
+18-12sysutils/nut/files/patch-configure
+15-5sysutils/nut-devel/files/patch-configure.ac
+33-172 files

LLVM/project 0dbb38aclang/lib/CIR/CodeGen CIRGenExprAggregate.cpp CIRGenExpr.cpp, clang/test/CIR/CodeGen cast.c

[[CIR]] Implement 'to-union' cast. (#191485)

This ends up being pretty trivial/can only really happen in 2 ways, the
only useful way is via an extension. This patch implements this.

This doesn't really affect anything as it is a pretty rarely used
feature and thus doesn't appear in the test suite I've seen, but I saw
it while investigating something else.
DeltaFile
+44-0clang/test/CIR/CodeGen/cast.c
+13-0clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
+4-1clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+61-13 files

LLVM/project 7a1f880llvm/lib/Target/RISCV RISCVISelDAGToDAG.cpp, llvm/test/CodeGen/RISCV rvp-ext-rv64.ll rvp-ext-rv32.ll

[RISCV][P-ext] Use li for all ones splat_vector. (#191748)

li -1 can be compressed to c.li.
DeltaFile
+30-6llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+20-4llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+9-0llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+59-103 files

HardenedBSD/ports e929152Mk bsd.port.mk

HBSD: Resolve merge conflict

Signed-off-by:  Shawn Webb <shawn.webb at hardenedbsd.org>
DeltaFile
+0-4Mk/bsd.port.mk
+0-41 files

HardenedBSD/ports fba34bcjava/openjdk26/files patch-src_hotspot_os__cpu_bsd__ppc_os__bsd__ppc.cpp patch-src_hotspot_os__cpu_bsd__ppc_orderAccess__bsd__ppc.hpp, security/vaultwarden distinfo Makefile.crates

Merge remote-tracking branch 'origin/freebsd/main' into hardenedbsd/main

Conflicts:
        Mk/bsd.port.mk (unresolved)
DeltaFile
+243-271security/vaultwarden/distinfo
+120-134security/vaultwarden/Makefile.crates
+120-81sysutils/cbsd/pkg-plist
+96-0sysutils/ansible-sshjail/files/patch-sshjail.py
+89-0java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_os__bsd__ppc.cpp
+80-0java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_orderAccess__bsd__ppc.hpp
+748-48661 files not shown
+975-65967 files

LLVM/project 6adef02clang/docs ReleaseNotes.rst, clang/lib/CodeGen/Targets X86.cpp

[X86][regcall] Rework struct classification for non-Windows x86-64 targets (#187134)

Currently, when `X86_64ABIInfo::classifyRegCallStructTypeImpl`
classifies a struct argument or return value as direct, it leaves the
LLVM IR coerce type unspecified, implicitly relying on
`CodeGenTypes::ConvertType` to eventually construct a default IR type
based on the struct's layout. This conversion is neither stable nor
guaranteed to adhere to the ABI's classification rules.

Instead, rewrite `classifyRegCallStructTypeImpl` to construct an
explicit sequence of coerce types, using the existing field
classification to obtain a coerce type for each member of the struct.
Also, rename the function to `passRegCallStructTypeDirectly` and return
a boolean instead, so that now `classifyRegCallStructType` is the only
place that computes `ABIArgInfo`.

This rewrite also fixes several other issues with the `X86_64ABIInfo`
implementation of `__regcall`:


    [17 lines not shown]
DeltaFile
+85-51clang/lib/CodeGen/Targets/X86.cpp
+64-6clang/test/CodeGen/regcall.c
+64-6clang/test/CodeGen/regcall4.c
+24-0clang/test/CodeGenCXX/regcall4.cpp
+24-0clang/test/CodeGenCXX/regcall.cpp
+6-0clang/docs/ReleaseNotes.rst
+267-636 files

FreeBSD/ports 9ec5a9bmisc/py-comfyui-workflow-templates-core distinfo Makefile

misc/py-comfyui-workflow-templates-core: update 0.3.197 → 0.3.198
DeltaFile
+3-3misc/py-comfyui-workflow-templates-core/distinfo
+1-1misc/py-comfyui-workflow-templates-core/Makefile
+4-42 files