net/rustconn: Update to 0.19.7
- Update list of lib dependencies
- Add a couple of patches (provided upstream) to fix cpal crate, that fails
with error:
error[E0425]: cannot find value `ESTRPIPE` in crate `libc`
--> /usr/local/poudriere/ports/default/net/rustconn/work/RustConn-0.19.5/cargo-crates/cpal-0.18.1/src/host/alsa/mod.rs:1125:42
|
1125 | Err(err) if err.errno() == libc::ESTRPIPE => return try_resume(&stream.handle),
| ^^^^^^^^
|
::: /usr/local/poudriere/ports/default/net/rustconn/work/RustConn-0.19.5/cargo-crates/libc-0.2.189/src/unix/bsd/freebsdlike/mod.rs:630:1
|
630 | pub const ESPIPE: c_int = 29;
| ----------------------- similarly named constant `ESPIPE` defined here
|
help: a constant with a similar name exists
|
[6 lines not shown]
ARM: Mark more generic libgcc functions as available (#210961)
Generic libgcc/compiler-rt functions coexist with aeabi variants
(e.g., __divsi3 and __aeabi_idiv) according to my reading of the
build. At least in compiler-rt, some are aliases.
They were previously removed from the available set on AEABI+AAPCS
targets to force selection of the preferred __aeabi_* variants, back when
only one implementation per libcall could be recorded.
Now that multiple implementations can be available per libcall, stop
hiding the generics and select the __aeabi_* variant explicitly as the
preferred implementation. This reduces the number of special cases to
consider for future libcalls info improvements.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[Docs][AMDGPU] availability/visibility in addrspace(3) and other cleanups
addrspace(3) on AMDGPU corresponds to LDS, which is a fast memory directly
accessed by all threads in a workgroup (there is no intervening cache). Thus,
any accesses to this addrspace have built-in availability and visibility at
"workgroup" scope.
Other cleanups:
- Update the intrinsic names to match the implementation.
- Explain store-available and load-visible.
- Rename to "make-available" and "make-visible" for consistent spelling.
[AArch64] Remove assembler-only register classes (#211527)
ZPRMul2, ZPRMul4 and PPRMul2 register classes are used solely by the asm
parser to validate other register classes (ZPR2Mul2, ZPR4Mul4,
PPR2Mul2). Since they're real register classes TableGen synthesizes
numerous intersection classes and pressure sets from them.
Removing them and validating the constraint directly in the assembly
parser reduces:
- generated register classes: 521 -> 403 (~22%)
- generated pressure sets: 188 -> 60 (68%)
- generated register-info size: 11.9 MB -> 9.1 MB (23%)
Also improves CTMark geomean -0.23% on stage1-aarch64-O3.
https://llvm-compile-time-tracker.com/compare.php?from=a90dbb43cd67856f681feba82d51a0d5fbcae3c2&to=5565d4907cdf960cc142a7507f16e551f51919b0&stat=instructions%3Au
Assisted-by: codex
AMDGPU: Export the TargetParser feature bitset
Previously this bitset was only used to populate the feature
name string map used by clang. Eventually this will replace
the current bitmask integer. AArch64 already has a similar
interface.
Co-authored-by: Claude (Claude-Opus-4.8)
AMDGPU: Tablegenerate TargetParser feature sets
Traditionally we maintained 2 parallel feature mechanisms,
one in clang (later moved to TargetParser), with largely
mirrored subtarget features defined in the backend. Start
directly taking feature information from the backend and putting
it into TargetParser. This is still in a compromise mid-migration
state. We still have both the legacy "ArchAttr" bitfield integer,
plus a new AMDGPUFeatureBitset field stored in the table, which
isn't yet exported.
For the moment, the new bitset is only used to populate the
feature string name map, which is the big maintainability win.
This also lists an explicit subset of exported features to
avoid churn.
Co-authored-by: Claude (Claude-Opus-4.8)
AMDGPU: Eliminate old macro driven processor name parsing (#212608)
Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.
Co-authored-by: Claude (Claude-Opus-4.8)
CSKY: Avoid constructing a temporary CSKYSubtarget in AsmPrinter
This was reconstructing a subtarget equivalent to the global
subtarget instead of just using the available one.
[BFI] Simplify/optimize getMass/getContainingLoop. NFC (#212938)
A block can head both a natural loop and the irreducible loop wrapping
it (`@crossloops` in BlockFrequencyInfo/irreducible.ll).
getContainingLoop and getMass unroll to a fixed depth of two through
isDoubleLoopHeader and isADoublePackage. Depth two holds because
IrreducibleGraph::addEdge drops edges into the enclosing loop's headers,
keeping such a header out of any nested SCC.
(The old comment "If it's a node inside a packaged loop, it returns the
loop's mass." is wrong.)
Walk the Parent chain instead to drop the depth two assumption. Testing
`IsPackaged` before isHeader also skips the Nodes[0] load on the common
path.
[RISCV] Support CodeGen of Zilx extension
Thanks for `XTheadMemIdx` extension that makes life easier.
Reviewers: lukel97, topperc, kito-cheng, tclin914
Reviewed By: topperc
Pull Request: https://github.com/llvm/llvm-project/pull/209420
AMDGPU: Eliminate old macro driven processor name parsing
Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.
Co-authored-by: Claude (Claude-Opus-4.8)
