OPNSense/plugins cd42fc1sysutils/gdrive-backup Makefile, sysutils/gdrive-backup/src/opnsense/mvc/app/library/OPNsense/Backup GDrive.php

sysutils/gdrive-backup: sync with master
DeltaFile
+1-1sysutils/gdrive-backup/src/opnsense/mvc/app/library/OPNsense/Backup/GDrive.php
+1-0sysutils/gdrive-backup/Makefile
+2-12 files

OPNSense/core 8e00d7bScripts class-filename.sh

Scripts: safeguard against missing directory
DeltaFile
+4-0Scripts/class-filename.sh
+4-01 files

OPNSense/core ab4f4c1src/etc/inc interfaces.inc, src/opnsense/scripts/interfaces rtsold_script.sh

interfaces: multi-dhcp6c support and custom PD association #7647

This splits off rtsold and dhcp6c into separate processes
which frees us from the restrictions of faked iterative IDs
for PD associations.  For NA we simply default to 0 now.

I'm not entirely sure why we settled for a single deamon of
dhcp6c back in the day, but there are certianly downsides to
it and I don't see something that wasn't fixed in the meantime
that makes this not work.
DeltaFile
+22-58src/etc/inc/interfaces.inc
+58-4src/www/interfaces.php
+6-6src/opnsense/scripts/interfaces/rtsold_script.sh
+86-683 files

LLVM/project 151fadeclang/test/Preprocessor riscv-target-features.c, llvm/lib/Target/RISCV RISCVInstrInfoZvabd.td RISCVFeatures.td

[RISCV][MC] Support experimental Zvabd instructions

The `Zvabd` is for `RISC-V Integer Vector Absolute Difference` and
it provides 5 instructions:

* `vabs.v`: Vector Signed Integer Absolute.
* `vabd.vv`: Vector Signed Integer Absolute Difference.
* `vabdu.vv`: Vector Unsigned Integer Absolute Difference.
* `vwabda.vv`: Vector Signed Integer Absolute Difference And Accumulate.
* `vwabdau.vv`: Vector Unsigned Integer Absolute Difference And Accumulate.

Doc: https://github.com/riscv/integer-vector-absolute-difference

Reviewers: topperc, lukel97, preames, tclin914, asb, kito-cheng, mshockwave

Pull Request: https://github.com/llvm/llvm-project/pull/180139
DeltaFile
+63-0llvm/test/MC/RISCV/rvv/zvabd.s
+27-0llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+10-0llvm/test/MC/RISCV/rvv/zvabd-invalid.s
+9-0clang/test/Preprocessor/riscv-target-features.c
+6-0llvm/lib/Target/RISCV/RISCVFeatures.td
+4-0llvm/test/CodeGen/RISCV/attributes.ll
+119-06 files not shown
+128-012 files

OPNSense/plugins 59af1b0net/tayga pkg-descr

net/tayga: sync with master
DeltaFile
+0-2net/tayga/pkg-descr
+0-21 files

LLVM/project fad32ffllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 combine-adc.ll

[X86] Optimized ADC + ADD to ADC (#176713)

DeltaFile
+6-2llvm/lib/Target/X86/X86ISelLowering.cpp
+3-5llvm/test/CodeGen/X86/combine-adc.ll
+9-72 files

NetBSD/src TXyJP7Ltools/gcc mknative-gcc

   also pull out nodist_libsubinclude_HEADERS for libquadmath.
VersionDeltaFile
1.126+2-1tools/gcc/mknative-gcc
+2-11 files

OPNSense/core ab3a745src/opnsense/mvc/app/models/OPNsense/Firewall Group.php

Firewall: Rules [new]: Fix group rename in source_net, destination_net and SNAT/DNAT target fields (#9734)

* Firewall: Rules [new]: Fix group rename in source_net, destination_net and SNAT/DNAT target fields

* review comments @fichtner

(cherry picked from commit aa6a813617a5161f0496a4470cfa3b58837debe0)
DeltaFile
+20-3src/opnsense/mvc/app/models/OPNsense/Firewall/Group.php
+20-31 files

OPNSense/core 1e1fdafsrc/opnsense/mvc/app/views/OPNsense/Diagnostics fw_log.volt

firewall: live view: combined filters stored as converted strings, adjust parsing (fixes https://github.com/opnsense/core/issues/9741)

(cherry picked from commit 72cea55c1a8387b201b19d27e0cfafe762ba4447)
DeltaFile
+6-3src/opnsense/mvc/app/views/OPNsense/Diagnostics/fw_log.volt
+6-31 files

OPNSense/core 47993fbsrc/opnsense/scripts/unbound-dnsbl dnsbl_match.py, src/opnsense/scripts/unbound-dnsbl/lib dnsbl.py

Services: Unbound DNS: Blocklists / Tester - safeguard config use, when there's none specified, don't crash out.

(cherry picked from commit b84bd68b292e21cfd0cd6ed18dc7d59baa6957b8)
DeltaFile
+3-0src/opnsense/scripts/unbound-dnsbl/lib/dnsbl.py
+1-1src/opnsense/scripts/unbound-dnsbl/dnsbl_match.py
+4-12 files

OPNSense/core 6cd589esrc/opnsense/mvc/app/controllers/OPNsense/Kea DhcpController.php

Services: Kea DHCP: Kea DHCPv4/6 / Subnets - missing root node, closes https://github.com/opnsense/core/issues/9762

(cherry picked from commit ccffd887d4cb7150adeb1864e46ebbf5d3d281b7)
DeltaFile
+2-2src/opnsense/mvc/app/controllers/OPNsense/Kea/DhcpController.php
+2-21 files

FreeBSD/ports c7ba723Mk/Uses inotify.mk

Mk/Uses/inotify.mk: Add USES=inotify

FreeBSD 15 includes the inotify system in base, but anything prior to 15
needs the libinotify port. This USES script makes it a little easier to
depend on and use the correct thing.

Reviewed by:    mat
Approved by:    mat
Differential Revision:  https://reviews.freebsd.org/D54116
DeltaFile
+34-0Mk/Uses/inotify.mk
+34-01 files

LLVM/project 8e02d24bolt/include/bolt/Profile DataAggregator.h

[Bolt] Replace -1ULL/-2ULL/-3ULL with std::numeric_limits in DataAggregator (#178597)

Replace instances of -1ULL, -2ULL, and -3ULL with std::numeric_limits in
Bolt DataAggregator Trace constants to address C4146 compiler warning.

Changes:
- BR_ONLY: -1ULL → std::numeric_limits<uint64_t>::max()
- FT_ONLY: -1ULL → std::numeric_limits<uint64_t>::max()
- FT_EXTERNAL_ORIGIN: -2ULL → std::numeric_limits<uint64_t>::max() - 1
- FT_EXTERNAL_RETURN: -3ULL → std::numeric_limits<uint64_t>::max() - 2

Fixes part of #147439
DeltaFile
+9-4bolt/include/bolt/Profile/DataAggregator.h
+9-41 files

OpenBSD/ports 0nOmO5ofonts/0xProto Makefile distinfo, fonts/0xProto/pkg PLIST-main PLIST-web

   Update to 0xProto-2.502, switch to the font module, and package web fonts.
VersionDeltaFile
1.2+13-11fonts/0xProto/Makefile
1.1+8-0fonts/0xProto/pkg/PLIST-main
1.1+5-0fonts/0xProto/pkg/PLIST-web
1.2+2-2fonts/0xProto/distinfo
1.1+2-0fonts/0xProto/pkg/DESCR-web
1.1+2-0fonts/0xProto/pkg/DESCR-main
+32-132 files not shown
+32-138 files

LLVM/project 355b676mlir .clang-tidy

[MLIR][NFC] Ignore clang-tidy `modernize-use-using` check in C code (#180326)

In the MLIR C API headers, clang-tidy’s `modernize-use-using` check
reports a large number of type definitions that use `typedef`. In my
IDE, this even causes the `typedef` code to be shown as struck through.
However, in this case it is clearly not possible to replace them with
`using`. This PR suppresses the `modernize-use-using` check for the code
inside `extern "C"` blocks.
DeltaFile
+2-0mlir/.clang-tidy
+2-01 files

LLVM/project 3d2353bllvm/unittests/CodeGen MFCommon.inc MachineInstrTest.cpp

fix unittest

Created using spr 1.3.5-bogner
DeltaFile
+7-1llvm/unittests/CodeGen/MFCommon.inc
+3-0llvm/unittests/CodeGen/MachineInstrTest.cpp
+2-0llvm/unittests/CodeGen/MachineOperandTest.cpp
+12-13 files

LLVM/project 6b97a83llvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

Remove IsRVVWideningReduction

Created using spr 1.3.6-beta.1
DeltaFile
+3-5llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+3-51 files

LLVM/project 985116dllvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+1-11 files

LLVM/project 6bd4d28llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp AMDGPUMCInstLower.cpp, llvm/test/CodeGen/AMDGPU asyncmark-max-pregfx12.ll asyncmark-pregfx12.ll

[AMDGPU] Introduce asyncmark/wait intrinsics

Asynchronous operations are memory transfers (usually between the global memory
and LDS) that are completed independently at an unspecified scope. A thread that
requests one or more asynchronous transfers can use async marks to track their
completion. The thread waits for each mark to be completed, which indicates that
requests initiated in program order before this mark have also completed.

For now, we implement asyncmark/wait operations on pre-GFX12 architectures that
support "LDS DMA" operations. Future work will extend support to GFX12Plus
architectures that support "true" async operations.

Co-authored-by: Ryan Mitchell ryan.mitchell at amd.com

Fixes: SWDEV-521121
DeltaFile
+268-12llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+279-0llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
+194-75llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
+38-16llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
+19-0llvm/test/CodeGen/AMDGPU/asyncmark-err.ll
+15-1llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+813-1047 files not shown
+874-10913 files

LLVM/project 134e9b1llvm/docs AMDGPUAsyncOperations.rst, llvm/lib/Target/AMDGPU SIISelLowering.cpp FLATInstructions.td

[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12

The existing "LDS DMA" builtins/intrinsics copy data from global/buffer pointer
to LDS. These are now augmented with their ".async" version, where the compiler
does not automatically track completion. The completion is now tracked using
explicit mark/wait intrinsics, which must be inserted by the user. This makes it
possible to write programs with efficient waits in software pipeline loops. The
program can now wait for only the oldest outstanding operations to finish, while
launching more operations for later use.

This change only contains the new names of the builtins/intrinsics, which
continue to behave exactly like their non-async counterparts. A later change
will implement the actual mark/wait semantics in SIInsertWaitcnts.

Fixes: SWDEV-521121
DeltaFile
+444-0llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
+238-0llvm/docs/AMDGPUAsyncOperations.rst
+91-0llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
+38-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+37-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
+13-12llvm/lib/Target/AMDGPU/FLATInstructions.td
+861-1723 files not shown
+1,066-7629 files

FreeBSD/ports a1184e5x11/wleave distinfo Makefile

x11/wleave: Update to 0.7.1

Changelog: https://github.com/AMNatty/wleave/releases/tag/0.7.1

Reported by:    GitHub (watch releases)
DeltaFile
+3-3x11/wleave/distinfo
+1-2x11/wleave/Makefile
+4-52 files

LLVM/project 9fd411fbolt/include/bolt/Core BinaryContext.h, bolt/lib/Core BinaryContext.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.5-bogner
DeltaFile
+5-2lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+4-2llvm/unittests/MC/AMDGPU/Disassembler.cpp
+2-1llvm/unittests/MC/SystemZ/SystemZMCDisassemblerTest.cpp
+3-0bolt/include/bolt/Core/BinaryContext.h
+2-1bolt/lib/Core/BinaryContext.cpp
+1-2lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+17-811 files not shown
+35-1617 files

LLVM/project 6e210f4bolt/lib/Core BinaryContext.cpp, lldb/source/Plugins/Disassembler/LLVMC DisassemblerLLVMC.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.5-bogner
DeltaFile
+15-11llvm/lib/MC/MCContext.cpp
+3-5llvm/lib/MC/MCObjectStreamer.cpp
+3-4llvm/lib/MC/ELFObjectWriter.cpp
+5-2lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+5-1bolt/lib/Core/BinaryContext.cpp
+5-1llvm/include/llvm/MC/TargetRegistry.h
+36-2418 files not shown
+70-4224 files

LLVM/project 5925521lldb/source/Plugins/Disassembler/LLVMC DisassemblerLLVMC.cpp, lldb/source/Plugins/Instruction/MIPS EmulateInstructionMIPS.cpp EmulateInstructionMIPS.h

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.5-bogner

[skip ci]
DeltaFile
+5-2lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+4-2llvm/unittests/MC/AMDGPU/Disassembler.cpp
+1-2lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+3-0lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
+1-2lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+2-1llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp
+16-911 files not shown
+35-1617 files

FreeBSD/src 8f23665sys/amd64/include pcb.h, sys/arm/include pcb.h

pcb.h: mark struct pcb to be preserved

There are programs that depend on this structure (e.g. kernel debuggers)
that breaks when the ABI changes.

Signed-off-by:  Minsoo Choo <minsoochoo0122 at proton.me>
Reviewed by:    kib
MFC after:      1 week
Differential Revision:  https://reviews.freebsd.org/D55149
DeltaFile
+11-10sys/amd64/include/pcb.h
+9-8sys/i386/include/pcb.h
+5-0sys/arm64/include/pcb.h
+5-0sys/riscv/include/pcb.h
+5-0sys/powerpc/include/pcb.h
+4-0sys/arm/include/pcb.h
+39-186 files

OpenBSD/ports zXElWKGemulators/libchdr Makefile distinfo, emulators/libchdr/patches patch-CMakeLists_txt

   Update to a newer revision of libchdr (last commit 2026-12-26).

   From "Matthew"; thanks!
VersionDeltaFile
1.6+4-4emulators/libchdr/Makefile
1.3+2-2emulators/libchdr/distinfo
1.2+0-0emulators/libchdr/patches/patch-CMakeLists_txt
+6-63 files

LLVM/project 7240aefllvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+1-11 files

LLVM/project 78f33e5llvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+1-11 files

LLVM/project 569d01fllvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

Use VALUVs2

Created using spr 1.3.6-beta.1
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+1-11 files

LLVM/project bd4784allvm/lib/Target/RISCV RISCVSchedSpacemitX100.td, llvm/test/tools/llvm-mca/RISCV/SpacemitX100 atomic.test floating-point.test

[RISCV] Add SpacemiT X100 base scheduling model (#178189)

SpacemiT X100 is a 4-issue, out-of-order, RVA23 processor. This patch
introduces the base scheduling model for scalar instructions. The
scheduling model for RVV will be added in a future update.
DeltaFile
+370-0llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td
+224-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/atomic.test
+168-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/floating-point.test
+160-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/integer.test
+96-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/zbb.test
+78-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/zfh.test
+1,096-08 files not shown
+1,478-114 files