FreeBSD/src 16bdecc — sys/dev/sound/midi mpu401.c

Revert "sound/midi: Drain the mpu401 callout before device teardown"

This was committed to main by accident, but was also buggy.

This reverts commit 91539591d7f8dd8ca24ced875bd16c3ba3c7d201.
DeltaFile
+1-3sys/dev/sound/midi/mpu401.c
+1-31 files

NetBSD/pkgsrc-wip aeb0bf7 — grafana Makefile go-modules.mk

grafana: update to 13.3.1.

Still doesn't build, reported upstream.
DeltaFile
+12-12grafana/distinfo
+6-6grafana/TODO
+2-2grafana/go-modules.mk
+1-1grafana/Makefile
+21-214 files

FreeBSD/ports f95f354 — x11-themes/plasma6-breeze-gtk Makefile

x11-themes/plasma6-breeze-gtk: Drop unused dependency on GTK2
DeltaFile
+2-2x11-themes/plasma6-breeze-gtk/Makefile
+2-21 files

FreeBSD/ports 484ce95 — x11-themes/plasma6-kde-gtk-config Makefile

x11-themes/plasma6-kde-gtk-config: Drop unused dependencies
DeltaFile
+7-5x11-themes/plasma6-kde-gtk-config/Makefile
+7-51 files

LLVM/project 71d20a0 — llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AArch64 sve-intrinsics.ll

[LLVM][CodeModel][SVE] Fix crash when attempting to cost llvm.vector.splice.left/right of non-legalisable type. (#241994)

Fixes https://github.com/llvm/llvm-project/issues/240454
DeltaFile
+9-0llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+4-1llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+13-12 files

LLVM/project c05630d — llvm/lib/Target/SystemZ SystemZISelLowering.cpp, llvm/test/CodeGen/SystemZ vec-sext-shuffle.ll

[SystemZ] Fix SIGN_EXTEND_VECTOR_INREG of shuffles (#241940)

`lowerSIGN_EXTEND_VECTOR_INREG` folds a `VECTOR_SHUFFLE` feeding the
extension into the start offset of its `UNPACK_HIGH`/`UNPACK_LOW` chain
when the extended lanes are consecutive elements of the shuffle input.
The offset is taken from the shuffle mask, which indexes the
concatenation of both shuffle operands, but the unpack chain was always
built on operand 0. When the offset was at least the lane count of one
operand, the chain extended unrelated lanes of the first operand instead
of lanes of the second one.

Select the operand the offset points into and make the offset relative
to it.

Fixes #238713 by implementing the suggested solution.

Assisted-by: IBM Bob
DeltaFile
+73-0llvm/test/CodeGen/SystemZ/vec-sext-shuffle.ll
+7-2llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+80-22 files

LLVM/project f7c97b2 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp

[AMDGPU] Use DataLayout sizes in the bitcast cost, compute each EVT once

getPrimitiveSizeInBits returns 0 for pointers, so use the DataLayout
sizes for the size check. Compute the EVT of each side once and use it
for both checks. The costs do not change.

Assisted-by: Claude Opus
DeltaFile
+8-6llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+8-61 files

LLVM/project d071ac7 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU bitcast-int-fp.ll

[AMDGPU] Treat a bitcast between scalars legalized to the same size as free
DeltaFile
+15-7llvm/test/Analysis/CostModel/AMDGPU/bitcast-int-fp.ll
+11-8llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+26-152 files

LLVM/project f96daf8 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU bitcast-int-fp.ll

[AMDGPU] Move the bitcast cost comments, document the i1 mask test

Put the comment about the scalarized parts of a vector bitcast above
the size check, and the comment about the shared registers inside it.
Say in the test which case @i1_mask covers.

Assisted-by: Claude Opus
DeltaFile
+4-2llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+3-0llvm/test/Analysis/CostModel/AMDGPU/bitcast-int-fp.ll
+7-22 files

LLVM/project 1e313a8 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU bitcast-int-fp.ll

[AMDGPU] Require equal sizes for a free bitcast, add i1 mask and gfx6 tests
DeltaFile
+79-49llvm/test/Analysis/CostModel/AMDGPU/bitcast-int-fp.ll
+5-3llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+84-522 files

LLVM/project b5a4137 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU bitcast-int-fp.ll

[AMDGPU] Treat a bitcast between legal types as free

The generic cost model treats a bitcast as free only when both types
are integer types or both are not. AMDGPU keeps integer and
floating-point values in the same registers, so a bitcast between two
legal types is a no-op. A scalar bitcast from i32 to float cost 1, but
the vector bitcast from <2 x i32> to <2 x float> cost 0. The SLP
vectorizer counted this difference as a saving.

A bitcast that involves a type the target legalizes, such as a vector
of i8, keeps its cost, because the lanes may need repacking.

Assisted-by: Claude Opus
DeltaFile
+35-35llvm/test/Analysis/CostModel/AMDGPU/bitcast-int-fp.ll
+4-3llvm/test/Transforms/SLPVectorizer/AMDGPU/bitcast-int-fp.ll
+6-0llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+45-383 files

LLVM/project aca8fe7 — llvm/include/llvm/ADT APFloat.h, llvm/lib/Support APFloat.cpp

Revert "[APFloat] Support user defined bit conversions (#240920)" (#242244)

This reverts commit 2be50053ae1b2e4d1a90683e93e451b065f56155.

This is failing in llvm::APFloatBase::SemanticsToEnum on buildbots and
causing considerable warnings on MSVC builds.
DeltaFile
+353-406llvm/lib/Support/APFloat.cpp
+3-343llvm/unittests/ADT/APFloatTest.cpp
+62-91llvm/include/llvm/ADT/APFloat.h
+418-8403 files

LLVM/project 8720948 — llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/lib/Target/AArch64 AArch64SVEInstrInfo.td AArch64ISelLowering.cpp

[LLVM][CodeGen][SVE] Add isel for ISD::FLDEXP. (#241882)

Support for bfloat, fixed-length vectors and strict-fp will follow in a
subsequent PRs.
DeltaFile
+208-0llvm/test/CodeGen/AArch64/sve-fp.ll
+56-36llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+12-12llvm/test/Analysis/CostModel/AArch64/sve-ldexp.ll
+14-0llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+4-3llvm/test/CodeGen/AArch64/ldexp.ll
+4-1llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+298-521 files not shown
+299-527 files

LLVM/project b0605d7 — llvm/lib/Target/X86 X86InstrAVX10.td

[X86] Add missing AVX10_2 guard to VMINMAX with SAE (#242003)

Noticed during work on scheduling model
DeltaFile
+1-1llvm/lib/Target/X86/X86InstrAVX10.td
+1-11 files

FreeBSD/ports 41e9480 — www/immich-deduper Makefile

www/immich-deduper: Allow watchdog 7

Sponsored by:   Netzkommune GmbH
DeltaFile
+2-1www/immich-deduper/Makefile
+2-11 files

FreeBSD/ports 2afb265 — www/immich Makefile, www/immich/files patch-server_src_repositories_storage.repository.ts

www/immich: Fix the storage usage display

node reports no frsize on FreeBSD, so the computed values came out NaN
and the server reported no disk usage at all. Fall back to bsize.

Sponsored by:   Netzkommune GmbH
DeltaFile
+20-0www/immich/files/patch-server_src_repositories_storage.repository.ts
+1-0www/immich/Makefile
+21-02 files

FreeBSD/src 64abec2 — sys/arm/allwinner aw_sid.c

aw_sid: Add support for the H6

Add the SID of the H6.  The efuse starts at 0x200 like on the other
64 bits SoCs and starts with the 16 bytes of the chip ID, which awg(4)
uses to create a MAC address when the firmware did not give it one.

The thermal sensor calibration data is not added, there is no driver
for the thermal sensors of the H6.

Tested on: H6
DeltaFile
+18-0sys/arm/allwinner/aw_sid.c
+18-01 files

FreeBSD/src 8a131d2 — sys/arm/allwinner axp81x.c

axp81x: Honor the enable delay of the regulators

axp8xx_regnode_enable() always reported a delay of 0, so the
regulator-enable-ramp-delay property of the FDT was ignored.  On the
Pine H64 model B the Ethernet PHY is supplied by ALDO2, which has a
delay of 100ms, and awg(4) resets the controller right after enabling
it, before the PHY is ready: the soft reset timed out and the interface
did not attach.  Return the delay when enabling a regulator, like the
fixed regulator driver does.

Fixes:          c175fd0fe8a3 ("axp81x: Add support for AXP803")
Tested on: H6
DeltaFile
+3-2sys/arm/allwinner/axp81x.c
+3-21 files

FreeBSD/src deedeb1 — sys/arm/allwinner if_awg.c

awg: Use the MAC address of the FDT

The firmware gives the MAC address of the controller in the FDT, in the
mac-address or local-mac-address property.  awg(4) only used the address
in the registers, which is set when the firmware used the controller,
and the one created from the SID.  On the Pine H64 the firmware does not
initialise the Ethernet and the SID driver does not support the H6, so a
random address was created and it changed at every boot.

Use fdt_ether_get_addr(), it takes the address of the FDT and keeps the
current one when there is none.

Tested on: H6
DeltaFile
+5-0sys/arm/allwinner/if_awg.c
+5-01 files

LLVM/project f023326 — mlir/lib/Target/SPIRV/Deserialization Deserializer.cpp, mlir/lib/Target/SPIRV/Serialization Serializer.cpp

[mlir][SPIR-V] Round trip OpConstantNull of pointer and composite types (#241923)

Deserializer failed with "unsupported OpConstantNull type" on thes
types, map them to and from #spirv.null

Depends on #241765
DeltaFile
+24-0mlir/test/Target/SPIRV/constant-null.mlir
+4-0mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
+3-0mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
+31-03 files

NetBSD/pkgsrc-wip 028b66f — rust-beta Makefile distinfo

rust-beta: update to 1.101.0beta.1
DeltaFile
+9-9rust-beta/distinfo
+2-2rust-beta/Makefile
+11-112 files

LLVM/project cc6ecb2 — llvm/test/CodeGen/AArch64/Atomics aarch64-atomic-load-v8a.ll aarch64-atomic-load-v8_1a.ll

[AArch64] Update test generator script for atomics (#241331)

Update the test generator script for AArch64 atomics to generate tests
for FP load/stores.

Also, update the test files accordingly.
DeltaFile
+544-0llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-v8a.ll
+544-0llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-v8_1a.ll
+544-0llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc3.ll
+544-0llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc.ll
+544-0llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-outline_atomics.ll
+544-0llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-lse2_lse128.ll
+3,264-024 files not shown
+10,092-630 files

LLVM/project f7aefc9 — llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/test/CodeGen/AMDGPU fcopysign.bf16.ll fcopysign.f16.ll

[LLVM][SelectionDAG] Use WidenVecRes_Binary to widen fcopysign variants with matching operand types. (#238807)

ISD::FCOPYSIGN cannot trap, so doesn't need to call
WidenVecRes_BinaryCanTrap.
DeltaFile
+79-79llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+42-42llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+2-2llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+123-1233 files

LLVM/project 4fa16f2 — llvm/cmake/modules AddLLVM.cmake, llvm/include/llvm/Config abi-breaking.h.cmake

[cmake] Centralize LLVM ABI compile definitions (#239689)

This adds a helper function, `llvm_update_abi_definitions()`, that
updates the ABI-related compile definitions in a centralized manner. The
helper narrows down the compile definitions to where they are actually
needed, which is only in the MSVC/clang-cl dylib build. As a side
effect, this removes PCH-related warnings concerning these defines in
the non-dylib and non-MSVC builds.

This changes the `LLVM_BUILD_LLVM_DYLIB=ON`/`LLVM_LINK_LLVM_DYLIB=OFF`
MSVC build behavior, which is non-functional anyway, and object
libraries now receive the same definitions as their target, which is
more correct.

This also updates the `abi-breaking.h` definitions for MinGW to match
`llvm/Support/Compiler.h` to prevent breakage.

This is a first step toward supporting PCHs in the LLVM dylib build on
Windows, tracked in #226993.

    [31 lines not shown]
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+38-12llvm/cmake/modules/AddLLVM.cmake
+5-6llvm/lib/Support/BLAKE3/CMakeLists.txt
+1-1utils/bazel/llvm_configs/abi-breaking.h.cmake
+1-1llvm/include/llvm/Config/abi-breaking.h.cmake
+45-204 files

LLVM/project 6193219 — openmp/tools/omptest CMakeLists.txt, openmp/tools/omptest/include OmptTester.h OmptestConfig.h.cmake

[OpenMP][omptest] WIP: keep per-target config dir, generated OmptestConfig.h

Assisted-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+19-0openmp/tools/omptest/include/OmptestConfig.h.cmake
+8-8openmp/tools/omptest/CMakeLists.txt
+1-0openmp/tools/omptest/include/OmptTester.h
+28-83 files

LLVM/project 927c9d2 — llvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp, llvm/test/CodeGen/AMDGPU store-to-constant.ll constant-address-space-32bit-vmem.ll

[AMDGPU] Expand 32-bit constant addresses for VMEM loads (#240829)

Uniform addrspace(6) loads that cannot use SMEM can pass a 32-bit
pointer to a VMEM instruction requiring a 64-bit address, causing
invalid copies or assertions during register allocation.

Fixes https://github.com/llvm/llvm-project/issues/239192
DeltaFile
+1,070-0llvm/test/CodeGen/AMDGPU/constant-address-space-32bit-vmem.ll
+6-6llvm/test/CodeGen/AMDGPU/store-to-constant.ll
+5-0llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+1,081-63 files

LLVM/project ae75b63 — llvm/test/Analysis/CostModel/AArch64 masked_expand_load.ll masked_compress_load.ll

[CostModel] NFC: Rename masked_compress_load.ll -> masked_compress_store.ll (#242259)

Also simplified masked_expand_load.ll and masked_compress_store.ll by
moving the target triple from the RUN line to the IR.
DeltaFile
+296-0llvm/test/Analysis/CostModel/AArch64/masked_compress_store.ll
+0-294llvm/test/Analysis/CostModel/AArch64/masked_compress_load.ll
+8-6llvm/test/Analysis/CostModel/AArch64/masked_expand_load.ll
+304-3003 files

FreeBSD/src 9153959 — sys/dev/sound/midi mpu401.c

sound/midi: Drain the mpu401 callout before device teardown

midi_uninit() frees the snd_midi that mpu401_intr() reaches through
midi_in() and midi_out(), but the callout that calls it was drained
afterwards. Drain it first, and clear M_TXPEND so that a firing handler
does not re-arm itself.

Fixes:          f960b33d35da ("sound/midi: Drain the mpu401 callout")
MFC with:       f960b33d35da
Sponsored by:   The FreeBSD Foundation
DeltaFile
+3-1sys/dev/sound/midi/mpu401.c
+3-11 files

LLVM/project a62842e — libc/test/src/math/smoke sinhf16_test.cpp expm1f16_test.cpp

[libc] Fix -Wunused-variable warnings

These variables may end up unused depending on the rounding mode in
place.
DeltaFile
+1-1libc/test/src/math/smoke/sinhf16_test.cpp
+1-1libc/test/src/math/smoke/expm1f16_test.cpp
+1-1libc/test/src/math/smoke/expf16_test.cpp
+1-1libc/test/src/math/smoke/exp2m1f16_test.cpp
+1-1libc/test/src/math/smoke/exp2f16_test.cpp
+1-1libc/test/src/math/smoke/exp10m1f16_test.cpp
+6-62 files not shown
+8-88 files

LLVM/project 982bc6f — libc/cmake/caches baremetal_common.cmake

[libc] Enable -Werror in baremetal_common.cmake cache file

After recent fixes, all the warnings are gone in baremetal builds.

Enable -Werror again so that we can catch warnings as they come.
DeltaFile
+1-2libc/cmake/caches/baremetal_common.cmake
+1-21 files