FreeBSD/ports 3e65db3www/squidclamav distinfo Makefile

www/squidclamav: Update to 7.5

Pull Request:   Rubicon Communications, LLC ("Netgate")
DeltaFile
+3-3www/squidclamav/distinfo
+1-2www/squidclamav/Makefile
+4-52 files

LLVM/project 0521f37clang/lib/CodeGen CGCUDANV.cpp, clang/test/CodeGenCUDA device-stub.cu

[clang][cuda] Use the source filename for module ID
DeltaFile
+13-0clang/test/CodeGenCUDA/device-stub.cu
+10-2clang/lib/CodeGen/CGCUDANV.cpp
+23-22 files

LLVM/project 0a5793bllvm/lib/Transforms/InstCombine InstCombineVectorOps.cpp, llvm/test/Transforms/InstCombine shuffle-cmp-cast-preserve-flags.ll

[InstCombine] Preserve IR flags when reordering icmp/fcmp/cast through a shuffle (#208627)

InstCombine's `evaluateInDifferentElementOrder` pushes a lane-reordering
`shufflevector` *through* the instruction that produced its input,
rebuilding that instruction on the reordered operands via the `buildNew`
helper — a `switch` with one case per opcode. The binary-operator case
carefully re-applies the original's poison-generating flags
(`nuw`/`nsw`, `exact`, FMF), and the `GetElementPtr` case passes through
its `getNoWrapFlags()`.

The `ICmp`, `FCmp`, and cast cases are the odd ones out. Each is a terse
`return Builder.CreateICmp/CreateFCmp/CreateCast(...)` that copies only
the predicate/opcode, returning the rebuilt instruction with default
flags. As a result a reordered `icmp samesign`, `fcmp nnan ninf`, `zext
nneg`, or `trunc nuw`/`nsw` silently loses its flag, even though the
flag held on the original.

Route each rebuilt instruction through `copyIRFlags(I)`, bringing these
cases in line with the binary-op and GEP cases. `copyIRFlags` transfers

    [17 lines not shown]
DeltaFile
+61-0llvm/test/Transforms/InstCombine/shuffle-cmp-cast-preserve-flags.ll
+14-7llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
+75-72 files

LLVM/project 3992543flang/lib/Lower/OpenMP OpenMP.cpp, mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

[flang][OpenMP] Lower target in_reduction

Enable host lowering for target in_reduction in Flang and MLIR OpenMP
translation.

Model target in_reduction through the matching map entry, force
address-preserving implicit mapping for Flang in_reduction list items, and emit
the host-side task-reduction lookup with __kmpc_task_reduction_get_th_data. The
runtime entry point takes and returns a generic, default-address-space pointer,
so normalize a non-default-address-space captured pointer to the generic address
space before the call and cast the returned private pointer back to the map
block argument's address space, mirroring the in_reduction handling on
omp.taskloop. On the target device, in_reduction is handled as a regular
map(tofrom) variable. The byref modifier, two-argument initializers, cleanup
regions, and the remaining Flang COMMON/EQUIVALENCE/privatized-variable cases
continue to be diagnosed.

Add Flang lowering, MLIR verifier/translation, and LLVM IR tests for the
supported host path, including a non-default-address-space case, and the
remaining unsupported cases.
DeltaFile
+128-21mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+124-14mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+107-0mlir/test/Target/LLVMIR/openmp-target-in-reduction.mlir
+88-15flang/lib/Lower/OpenMP/OpenMP.cpp
+88-3mlir/test/Target/LLVMIR/openmp-todo.mlir
+85-0mlir/test/Dialect/OpenMP/invalid.mlir
+620-5314 files not shown
+1,029-7920 files

LLVM/project 66dc68dlldb/source/Plugins/Process/Utility InferiorCallPOSIX.cpp

fixup! Support Re-export Symbol for FunctionCall
DeltaFile
+58-61lldb/source/Plugins/Process/Utility/InferiorCallPOSIX.cpp
+58-611 files

LLVM/project b73de5dllvm/lib/Target/WebAssembly WebAssemblyCodeGenPassBuilder.cpp

add comment

Created using spr 1.3.7
DeltaFile
+8-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+8-01 files

LLVM/project 4a06d1dlibcxx/test/selftest if-else.sh.cpp

Use `target={{.+}}` feature instead for the test
DeltaFile
+1-1libcxx/test/selftest/if-else.sh.cpp
+1-11 files

LLVM/project 685cd0dllvm/utils/lit/tests shtest-run-at-line.py shtest-timeout.py, llvm/utils/lit/tests/Inputs/shtest-readfile lit.cfg

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+5-53llvm/utils/lit/tests/shtest-run-at-line.py
+7-30llvm/utils/lit/tests/shtest-timeout.py
+0-36llvm/utils/lit/tests/shtest-external-shell-kill.py
+0-25llvm/utils/lit/tests/shtest-readfile-external.py
+1-11llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
+1-11llvm/utils/lit/tests/Inputs/shtest-timeout/lit.cfg
+14-16621 files not shown
+44-25427 files

FreeBSD/ports 783a09edevel/buildkite-agent/files buildkite.in

devel/buildkite_agent: Enable logfile for output

Reviewed by:    dch
Sponsored by:   The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D57885
DeltaFile
+1-0devel/buildkite-agent/files/buildkite.in
+1-01 files

LLVM/project 54e44f9llvm/lib/Transforms/IPO AlwaysInliner.cpp, llvm/test/Transforms/Inline always-inline-phase-ordering.ll

Revert "[AlwaysInliner] Do not inline on attribute mismatches"

This reverts commit 37b8e765ce4837a7577e6f762bcdffe4b232759c.
DeltaFile
+0-29llvm/test/Transforms/Inline/X86/always-inline-incompatible-target-features.ll
+0-17llvm/lib/Transforms/IPO/AlwaysInliner.cpp
+1-1llvm/test/Transforms/Inline/always-inline-phase-ordering.ll
+1-473 files

OpenBSD/ports HlUMqTOwww/mozilla-firefox distinfo Makefile

   www/mozilla-firefox: MFC update to 152.0.6.

   see https://www.firefox.com/en-US/firefox/152.0.6/releasenotes/
   fixes https://www.mozilla.org/en-US/security/advisories/mfsa2026-67/
VersionDeltaFile
1.397.2.11+2-2www/mozilla-firefox/distinfo
1.680.2.13+1-1www/mozilla-firefox/Makefile
+3-32 files

OpenBSD/ports sybZfeowww/firefox-i18n distinfo Makefile.inc, www/mozilla-firefox distinfo Makefile

   www/mozilla-firefox: update to 152.0.6.

   see https://www.firefox.com/en-US/firefox/152.0.6/releasenotes/
   fixes https://www.mozilla.org/en-US/security/advisories/mfsa2026-67/
VersionDeltaFile
1.398+164-164www/firefox-i18n/distinfo
1.412+4-4www/mozilla-firefox/distinfo
1.698+2-2www/mozilla-firefox/Makefile
1.353+1-1www/firefox-i18n/Makefile.inc
+171-1714 files

LLVM/project 53da348llvm/test/Transforms/LoopVectorize fmax-without-fast-math-flags.ll

[LV] Add test showing incorrect trip count materialization (NFC) (#209460)

Add test case showing mis-compile for
https://github.com/llvm/llvm-project/issues/209159.
DeltaFile
+105-0llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
+105-01 files

LLVM/project e731908clang/docs ReleaseNotes.md, clang/lib/Sema SemaConcept.cpp

[Clang] Adjust NTTP depths in IsAtLeastAsConstrained (#209445)

The default transform for NTTP, which is no-op, doesn't help if we need
to adjust their depths when comparing constraints.

Fixes https://github.com/llvm/llvm-project/issues/182671
DeltaFile
+25-0clang/lib/Sema/SemaConcept.cpp
+18-1clang/test/SemaCXX/concepts-subsumption.cpp
+2-0clang/docs/ReleaseNotes.md
+45-13 files

LLVM/project 5010dd7llvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Stop using changeTo in legaizer actions

Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
DeltaFile
+855-425llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+783-389llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+759-377llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+253-160llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+232-138llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+58-80llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+2,940-1,56911 files not shown
+3,066-1,65117 files

LLVM/project f6e5179llvm/test/CodeGen/AMDGPU memset-param-combinations.ll shrink-add-sub-constant.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll saddsat.ll

AMDGPU/GlobalISel: Fix G_MERGE_VALUES lowering for extended LLTs

Use integer type for bit twiddling instead of scalar.
DeltaFile
+1,801-1,013llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
+1,584-1,032llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+1,583-1,004llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+1,449-654llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+1,314-625llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+989-704llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+8,720-5,032186 files not shown
+29,006-19,794192 files

LLVM/project 83e96b5llvm/test/CodeGen/AMDGPU freeze.ll vector-reduce-fmin.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f16.ll

AMDGPU/GlobalISel: Fix G_UNMERGE_VALUES lowering for extended LLTs

Use integer type for bit twiddling instead of scalar.
DeltaFile
+1,623-486llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+1,155-361llvm/test/CodeGen/AMDGPU/freeze.ll
+663-347llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+663-347llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+590-290llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+545-261llvm/test/CodeGen/AMDGPU/mad-mix.ll
+5,239-2,092150 files not shown
+15,641-10,429156 files

Illumos/gate 2b7388busr/src/uts/common/rpc clnt.h xdr.h

18214 rpc headers missed in 5066
Reviewed by: Jason King <jason.brian.king+illumos at gmail.com>
Reviewed by: Toomas Soome <tsoome at me.com>
Reviewed by: Robert Mustacchi <rm at fingolfin.org>
DeltaFile
+53-143usr/src/uts/common/rpc/clnt.h
+0-84usr/src/uts/common/rpc/xdr.h
+0-78usr/src/uts/common/rpc/svc.h
+0-50usr/src/uts/common/rpc/auth.h
+10-32usr/src/uts/common/rpc/rpc_msg.h
+2-27usr/src/uts/common/rpc/clnt_soc.h
+65-41411 files not shown
+66-53017 files

LLVM/project fcc4b39llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

AMDGPU/GlobalISel: Switch legalizer intrinsic lowering to extended LLTs

Affects various buffer intrinsics.
DeltaFile
+5,162-5,142llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+4,767-4,791llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+4,321-4,345llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+2,172-2,164llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+2,119-2,107llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+965-965llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+19,506-19,51462 files not shown
+24,540-23,91268 files

FreeBSD/ports 51cda26x11-toolkits/mygui-dummy Makefile, x11-toolkits/mygui-opengl Makefile

x11-toolkits/mygui-*: restore oblivoiusly zeroed PORTREVISIONS
DeltaFile
+1-1x11-toolkits/mygui-dummy/Makefile
+1-1x11-toolkits/mygui-opengl/Makefile
+2-22 files

LLVM/project ada81e0llvm/test/CodeGen/AMDGPU llvm.amdgcn.permlane.ll llvm.is.fpclass.f16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Handle G_BITCAST for 16 bit extendedLLTs

Handle bitcast between i16 and f16/bf16.
For true16 this was already legal, make it legal in regbanklegalize as well.
For non-true16 widen it using G_ANYEXT to i32 and G_TRUNC to dst.
The "i32 G_ANYEXT f16/bf16" and "f16/bf16 G_TRUNC i32" are already legal,
for example these are generated by common CallLowering argument lowering.
DeltaFile
+3,572-3,745llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+3,314-3,041llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+3,245-2,737llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1,670-1,373llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+1,239-552llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+656-996llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+13,696-12,444179 files not shown
+24,976-20,597185 files

LLVM/project db63c56compiler-rt/lib/asan asan_malloc_linux.cpp, compiler-rt/lib/asan/AIX asan.link_with_main_exec.txt

[ASan][AIX] Intercept __linux_vec_malloc/__linux_vec_calloc/__linux_realloc (#209359)

On AIX PASE, when `__VEC__` and `_ALL_SOURCE` are defined, the XL
compiler frontend lowers calls to vec_malloc/vec_calloc/realloc to
internal symbols named `__linux_vec_malloc`, `__linux_vec_calloc`, and
`__linux_realloc` instead of the standard
`vec_malloc`/`vec_calloc`/`realloc` names. These symbols were not
intercepted, so allocations made through them bypassed ASan entirely, no
redzone poisoning, no use-after-free or overflow detection.
This adds interceptors for `__linux_vec_malloc`, `__linux_vec_calloc`,
and `__linux_realloc`, following the same pattern as the existing
`vec_malloc`/`vec_calloc` interceptors (#175584): `__linux_vec_malloc`
and `__linux_vec_calloc` route through
`asan_vec_malloc`/`asan_vec_calloc` (16-byte aligned), and
`__linux_realloc` routes through the existing `asan_realloc`.

---------

Co-authored-by: Midhunesh <midhuensh.p at ibm.com>
DeltaFile
+36-10compiler-rt/test/asan/TestCases/AIX/vec_malloc_calloc.cpp
+29-0compiler-rt/lib/asan/asan_malloc_linux.cpp
+6-0compiler-rt/lib/asan/AIX/asan.link_with_main_exec.txt
+71-103 files

LLVM/project f17aa03clang/www c_status.html

bump up clang version
DeltaFile
+1-1clang/www/c_status.html
+1-11 files

LLVM/project 1b10cd9llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 non-power-of-2-with-adjusted-gathers.ll

[SLP]Do not blacklist ordered-reduction operands on failed root attempt

An ordered reduction pulls its leaf operands into ReductionOps via the
fallback in matchAssociativeReduction. When such a reduction fails to
vectorize, marking every reduction op as analyzed also blocks those leaves,
which may still be valid reduction roots on their own.

Fixes https://github.com/llvm/llvm-project/pull/185320#issuecomment-4925949343

Reviewers: hiraditya, bababuck, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/208511
DeltaFile
+3-19llvm/test/Transforms/SLPVectorizer/X86/reduction-root-multiuse-same-opcode.ll
+10-10llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
+11-3llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4-5llvm/test/Transforms/SLPVectorizer/X86/control-deps-schedule-data-recalculate.ll
+28-374 files

LLVM/project 5eaa6bfllvm/docs LangRef.rst LangRef.md, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

Merge branch 'main' into users/aokblast/lldb/fix_auxilary_handle
DeltaFile
+20,246-21,270llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+0-33,206llvm/docs/LangRef.rst
+30,315-0llvm/docs/LangRef.md
+23,904-12llvm/test/CodeGen/RISCV/clmul.ll
+8,882-7,730llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+6,601-5,921llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+89,948-68,1397,866 files not shown
+511,138-371,3257,872 files

LLVM/project 36936a7llvm/test/CodeGen/AMDGPU occupancy-levels.ll offset-split-flat.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (27)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+26-26llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
+12-12llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
+12-12llvm/test/CodeGen/AMDGPU/offset-split-global.ll
+8-8llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+8-8llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+7-7llvm/test/CodeGen/AMDGPU/packed-fp32.ll
+73-7394 files not shown
+238-238100 files

LLVM/project bf96576llvm/test/CodeGen/AMDGPU readcyclecounter.ll reassoc-mul-add-1-to-mad.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (28)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+13-13llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
+10-10llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
+8-8llvm/test/CodeGen/AMDGPU/print-pipeline-passes.ll
+6-6llvm/test/CodeGen/AMDGPU/preserve-hi16.ll
+5-5llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
+5-5llvm/test/CodeGen/AMDGPU/ptradd-sdag.ll
+47-4785 files not shown
+181-18191 files

LLVM/project f249e96llvm/test/CodeGen/AMDGPU minmax.ll neighboring-mfma-padding.mir

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (26)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+16-16llvm/test/CodeGen/AMDGPU/minmax.ll
+11-11llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
+8-8llvm/test/CodeGen/AMDGPU/mul.ll
+6-6llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
+6-6llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
+6-6llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
+53-5395 files not shown
+266-267101 files

LLVM/project 75355d5llvm/test/CodeGen/AMDGPU maximumnum.ll mad-mix.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (24)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+26-26llvm/test/CodeGen/AMDGPU/maximumnum.ll
+14-14llvm/test/CodeGen/AMDGPU/mad-mix.ll
+12-12llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+10-10llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+9-9llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8-8llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+79-7992 files not shown
+307-30798 files

LLVM/project b9bb2f2llvm/test/CodeGen/AMDGPU minimumnum.ll memory-legalizer-private-workgroup.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (25)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+26-26llvm/test/CodeGen/AMDGPU/minimumnum.ll
+14-14llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
+14-14llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+14-14llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
+14-14llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-global.ll
+14-14llvm/test/CodeGen/AMDGPU/memory-legalizer-fence-mmra-local.ll
+96-9693 files not shown
+647-64999 files