LLVM/project 4711f40llvm/lib/CodeGen Rematerializer.cpp

Remove lambda
DeltaFile
+20-21llvm/lib/CodeGen/Rematerializer.cpp
+20-211 files

LLVM/project 1f48b88llvm/lib/CodeGen Rematerializer.cpp, llvm/unittests/CodeGen RematerializerTest.cpp

[CodeGen] Fix incorrect rematerializtion order in rematerializer

When rematerializing DAGs of registers wherein multiple paths exist
between some regsters of the DAG, it is possible that the
rematerialization determines an incorrect rematerialization order that
does not ensure that a register's dependencies are rematerialized before
itself; an invariant that is otherwise required.

This fixes that using a simpler recursive logic to determine a correct
rematerialization order that honors this invariant. A minimal unit test
is added that fails on the current implementation.
DeltaFile
+20-33llvm/lib/CodeGen/Rematerializer.cpp
+38-0llvm/unittests/CodeGen/RematerializerTest.cpp
+58-332 files

LLVM/project 8e54890clang/include/clang/ScalableStaticAnalysisFramework SSAFBuiltinForceLinker.h, clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageTest.cpp

fix bugs
DeltaFile
+1-1clang/include/clang/ScalableStaticAnalysisFramework/SSAFBuiltinForceLinker.h
+1-1clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+2-22 files

LLVM/project 94875aellvm/include/llvm/CodeGen LiveIntervals.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Fix multiple connected component issue in rematerializer (#186674)

This fixes a rematerializer issue wherein re-creating the interval of a
non-rematerializable super-register defined over multiple MIs, some of
which defining entirely dead sub-registers, could cause a crash when
changing the order of sub-definitions (for example during scheduling)
because the re-created interval could end up with multiple connected
components, which is illegal. The solution is to split separate
components of the interval in such cases. The added unit test crashes
without that added behavior.
DeltaFile
+71-0llvm/unittests/CodeGen/RematerializerTest.cpp
+16-1llvm/lib/CodeGen/Rematerializer.cpp
+6-0llvm/include/llvm/CodeGen/LiveIntervals.h
+93-13 files

FreeBSD/ports 61a4663deskutils/py-vit distinfo Makefile

deskutils/py-vit: Update 2.3.3 => 2.3.4

Changelog:
https://github.com/vit-project/vit/releases/tag/v2.3.4

Port changes:
* Remove unneeded GH_PROJECT.
* Remove extra arguments from USES=python.

PR:             294252
Reported by:    Thierry Dussuet <thierry.dussuet at protonmail.com> (maintainer)
Approved by:    maintainer, vvd (co-mentor)

(cherry picked from commit 96442118053ee250fae90bb16f86f369727fda17)
DeltaFile
+3-3deskutils/py-vit/distinfo
+3-3deskutils/py-vit/Makefile
+6-62 files

LLVM/project 90ec5f2mlir/test/Integration/GPU/CUDA async.mlir

[MLIR][test] Re-disable FileCheck on async.mlir integration test (#190702)

#190563 re-enabled FileCheck on `Integration/GPU/CUDA/async.mlir`, but
the buildbot has shown intermittent wrong-output failures
([example](https://lab.llvm.org/buildbot/#/builders/116/builds/27026)):
the test produces `[42, 42]` instead of the expected `[84, 84]`.

This wrong-output flakiness is distinct from the cleanup-time
`cuModuleUnload` errors that #190563 actually fixes — it's the
underlying issue tracked by #170833. The merged commit message for
#190563 incorrectly says `Fixes #170833`; that issue should be reopened,
since the cleanup-error fix doesn't address the wrong-output behavior.

This PR puts the test back in its previously-disabled state. The runtime
cleanup fix in #190563 is unaffected.
DeltaFile
+5-2mlir/test/Integration/GPU/CUDA/async.mlir
+5-21 files

LLVM/project aedd4e0clang/lib/CIR/CodeGen CIRGenExprConstant.cpp, clang/test/CIR/CodeGen static-local.cpp

[CIR] Handle static local var decl constants (#190699)

This adds the handling for the case where the address of a static local
variable is used to initialize another static local. In this case, the
address of the first variable is emitted as a constant in the
initializer of the second variable.
DeltaFile
+17-3clang/test/CIR/CodeGen/static-local.cpp
+4-3clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+21-62 files

LLVM/project 228b6aeclang/lib/CIR/CodeGen CIRGenBuiltin.cpp, clang/test/CIR/CodeGenBuiltins builtin-signbit.c

[CIR][CodeGen] Implement __builtin_signbit (#188433)

__builtin_signbit function checks if the sign bit of a floating-point
number is set to 0 or 1.
DeltaFile
+158-0clang/test/CIR/CodeGenBuiltins/builtin-signbit.c
+10-1clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+168-12 files

OpenZFS/src 5cb95admodule/zfs spa_errlog.c

fix memleak in spa_errlog.c

Reviewed-by: Alexander Motin <alexander.motin at TrueNAS.com>
Reviewed-by: Alan Somers <asomers at freebsd.org>
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Alek Pinchuk <apinchuk at axcient.com>
Closes #18403
DeltaFile
+1-1module/zfs/spa_errlog.c
+1-11 files

OpenZFS/src 3599964module/os/linux/zfs zpl_file.c

Linux: Refactor zpl_fadvise()

Similar to FreeBSD stop issuing prefetches on POSIX_FADV_SEQUENTIAL.
It should not have this semantics, only hint speculative prefetcher,
if access ever happen later.  Instead after POSIX_FADV_WILLNEED
handling call generic_fadvise(), if available, to do all the generic
stuff, including setting f_mode in struct file, that we could later
use to control prefetcher as part of read/write operations.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Alexander Motin <alexander.motin at TrueNAS.com>
Closes #18395
DeltaFile
+10-27module/os/linux/zfs/zpl_file.c
+10-271 files

NetBSD/pkgsrc-wip de68407med Makefile

med: add missing dependency
DeltaFile
+2-4med/Makefile
+2-41 files

FreeBSD/ports 6ef9481security/strongswan pkg-plist Makefile, security/strongswan/files patch-conf_Makefile.in patch-src_libcharon_plugins_smp_smp.c

security/strongswan: Update 6.0.4 => 6.0.5 (CVE-2026-25075)

Changelog:
https://github.com/strongswan/strongswan/releases/tag/6.0.5

While here:
- Switch from post-install + "if PORT_OPTIONS:MVICI" to
  post-install-VICI-on.
- Add option FIPS_PRF - software implementation plugin.
- Improve plist.
- Refresh patches.

Reported by:    Mike Bressem <mike at bressem.com> (via email)
Approved by:    blanket (fix CVE)
Security:       CVE-2026-25075
Sponsored by:   UNIS Labs
MFH:            2026Q2

(cherry picked from commit 2d6221ae7df33419e639c439a12c78fdea84e748)
DeltaFile
+48-4security/strongswan/pkg-plist
+18-6security/strongswan/files/patch-conf_Makefile.in
+5-5security/strongswan/Makefile
+4-4security/strongswan/files/patch-src_libcharon_plugins_smp_smp.c
+3-3security/strongswan/distinfo
+2-2security/strongswan/files/patch-src_libstrongswan_plugins_openssl_openssl__plugin.c
+80-241 files not shown
+82-267 files

LLVM/project fe07678.github/workflows libcxx-build-and-test.yaml

[libc++] Switch CI runners to use the latest Docker image (#190363)
DeltaFile
+3-3.github/workflows/libcxx-build-and-test.yaml
+3-31 files

LLVM/project 85eb6b3llvm/include/llvm/CodeGen LiveIntervals.h

Format
DeltaFile
+1-1llvm/include/llvm/CodeGen/LiveIntervals.h
+1-11 files

LLVM/project fe9a478llvm/include/llvm/CodeGen LiveIntervals.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Fix multiple connected component issue in rematerializer

This fixes a rematerializer issue wherein re-creating the interval of a
non-rematerializable super-register defined over multiple MIs, some of
which defining entirely dead subregisters, could cause a crash when
changing the order of sub-definitions (for example during scheduling)
because the re-created interval could end up with multiple connected
components, which is illegal. The solution is to split separate
components of the interval in such cases. The added unit test crashes
without that added behavior.
DeltaFile
+71-0llvm/unittests/CodeGen/RematerializerTest.cpp
+16-1llvm/lib/CodeGen/Rematerializer.cpp
+6-0llvm/include/llvm/CodeGen/LiveIntervals.h
+93-13 files

LLVM/project 014d5d5lldb/packages/Python/lldbsuite/test/make Makefile.rules

[lldb] Change most tests to build with system libc++ on Darwin (#190034)

Today, on Darwin platforms, almost every test binary in our test suite
loads two copies of libc++, libc++abi, and libunwind. This is because
each of the test binaries explicitly link against a just-built libc++
(which is explicitly required on Darwin right now) but we don't take the
correct steps to replace the system libc++. Doing so is unnecessary and
potentially error-prone, so most tests should link against the system
libc++ where possible.

Background:
The lldb test suite has a collection of tests that rely on libc++
explicitly. The two biggest categories are data formatter tests (which
make sure that we can correctly display values for std types) and
import-std-module tests (which test that we can import the libc++ std
module). To make sure these tests are run, we require a just-built
libc++ to be used.

All of the test binaries link against the just-built libc++, so it gets

    [12 lines not shown]
DeltaFile
+18-11lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+18-111 files

LLVM/project 8e1ea8allvm/lib/Target/RISCV RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rv32p.ll

[RISCV][P-ext] Add isel patterns for mhacc/mhaccu/mhaccsu. (#190670)
DeltaFile
+130-0llvm/test/CodeGen/RISCV/rv32p.ll
+7-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+137-02 files

FreeBSD/ports 2d6221asecurity/strongswan pkg-plist Makefile, security/strongswan/files patch-conf_Makefile.in patch-src_libcharon_plugins_smp_smp.c

security/strongswan: Update 6.0.4 => 6.0.5 (CVE-2026-25075)

Changelog:
https://github.com/strongswan/strongswan/releases/tag/6.0.5

While here:
- Switch from post-install + "if PORT_OPTIONS:MVICI" to
  post-install-VICI-on.
- Add option FIPS_PRF - software implementation plugin.
- Improve plist.
- Refresh patches.

Reported by:    Mike Bressem <mike at bressem.com> (via email)
Approved by:    blanket (fix CVE)
Security:       CVE-2026-25075
Sponsored by:   UNIS Labs
MFH:            2026Q2
DeltaFile
+48-4security/strongswan/pkg-plist
+18-6security/strongswan/files/patch-conf_Makefile.in
+5-5security/strongswan/Makefile
+4-4security/strongswan/files/patch-src_libcharon_plugins_smp_smp.c
+3-3security/strongswan/distinfo
+2-2security/strongswan/files/patch-src_libstrongswan_plugins_openssl_openssl__plugin.c
+80-241 files not shown
+82-267 files

LLVM/project ce61fe5llvm/tools/llvm-profgen MissingFrameInferrer.cpp ProfileGenerator.cpp

[NFC][llvm-profgen] Fix a few minor issues (#190019)

A few NFC (mostly) fixes:
- Drop unused parameters.
- Check return error.
- Fix return type.
DeltaFile
+8-6llvm/tools/llvm-profgen/MissingFrameInferrer.cpp
+4-5llvm/tools/llvm-profgen/ProfileGenerator.cpp
+1-2llvm/tools/llvm-profgen/ProfileGenerator.h
+2-0llvm/tools/llvm-profgen/llvm-profgen.cpp
+1-1llvm/tools/llvm-profgen/PerfReader.h
+16-145 files

LLVM/project 1ae179bllvm/lib/Transforms/IPO SampleProfileMatcher.cpp, llvm/test/Transforms/SampleProfile pseudo-probe-stale-profile-backward-matching.ll

[SampleProfileMatcher] Fix backward matching of non-anchor locations (#190118)

The backward matching loop in `matchNonCallsiteLocs` was ineffective
because `InsertMatching` used `std::unordered_map::insert()` which does
not overwrite existing entries. Since forward matching already inserted
entries for all non-anchor locations, the backward matching for the
second half was silently ignored.

The backward matching can update forward mappings in
`IRToProfileLocationMap` in 2 ways:
- The IR location maps a new different profile location. Change
`insert()` to `insert_or_assign()` so that entry overwrite can happen.
- The IR location maps the same profile location. Add `erase()` to
remove such mapping.
DeltaFile
+92-0llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-backward-matching.ll
+8-6llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
+6-0llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-stale-profile-backward-matching.prof
+106-63 files

LLVM/project fc1ce37llvm/lib/Target/AMDGPU AMDGPU.td

[AMDGPU] Enable real true16 on gfx1250
DeltaFile
+1-0llvm/lib/Target/AMDGPU/AMDGPU.td
+1-01 files

NetBSD/src azRdFzLshare/man/man4 akbd.4

   akbd(4): s/shoud/should/.
VersionDeltaFile
1.5+2-2share/man/man4/akbd.4
+2-21 files

NetBSD/pkgsrc BIr7aVidoc CHANGES-2026

   Update vim
VersionDeltaFile
1.2131+2-1doc/CHANGES-2026
+2-11 files

LLVM/project dd4e284llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp, llvm/test/CodeGen/AMDGPU vgpr-setreg-mode-swar.mir hazard-setreg-vgpr-msb-gfx1250.mir

[AMDGPU] Fix setreg handling in the VGPR MSB lowering

There are multiple issues with it:

1. It can skip inserting S_SET_VGPR_MSB if we set the mode via
   piggybacking. We are now relying on the HW bug for correct
   behavior. If/when the bug is fixed lowering will be incorrect.
2. We should just unconditionally update MSBs if immediate allows it.
   We shall set correct bits and keep the rest of the immediate
   (that is done). There is no reasonable way for an user to change
   MSBs nor does it do anything good to set it with SETREG and then
   immediately overwrite with S_SET_VGPR_MSB.
3. We can always update immediate if Offset is zero.
4. Redundant mode changes created as seen in the
   hazard-setreg-vgpr-msb-gfx1250.mir.

With unconditional immediate update most of time and not relying on
the SETREG for setting MSBs there is no good reason to complicate
handling by supporting SETREG as a piggybacking target. Moreover,

    [10 lines not shown]
DeltaFile
+209-47llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
+27-40llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+12-18llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir
+248-1053 files

OpenBSD/src R0JBej4share/man/man4/man4.riscv64 smtpmic.4 Makefile

   smtpmic(4)
VersionDeltaFile
1.1+45-0share/man/man4/man4.riscv64/smtpmic.4
1.17+2-2share/man/man4/man4.riscv64/Makefile
+47-22 files

LLVM/project e8566f8lldb/bindings/interface SBModuleSpecListExtensions.i, lldb/test/API/python_api/sbmodule TestSBModule.py

[lldb][python] Add polymorphic `__getitem__` to `SBModuleSpecList` for Pythonic indexing (#189125)

### Summary

`SBModuleSpecList` already supports `len()` and iteration via `__len__`
and `__iter__`, but is not subscriptable — `specs[0]` raises
`TypeError`.

This adds a `__getitem__` method that supports integer indexing (with
negative index support) and string lookup using `endswith()` matching,
which works for both Unix and Windows paths.

### Supported key types

| Key type | Example | Behavior |
|---|---|---|
| `int` | `specs[0]`, `specs[-1]` | Direct index with negative index
support |
| `str` | `specs['a.out']`, `specs['/usr/lib/liba.dylib']` | Lookup by

    [64 lines not shown]
DeltaFile
+60-0lldb/test/API/python_api/sbmodule/TestSBModule.py
+21-9lldb/bindings/interface/SBModuleSpecListExtensions.i
+81-92 files

FreeBSD/ports 75ee539japanese/navi2ch pkg-plist Makefile

japanese/navi2ch: Refactor

Lint with portclippy.
Switch LISPDIR variable to NLISPDIR and add NICONDIR.
Switch from INSTALL_DATA to COPYTREE_SHARE.

PR:             291381
Approved by:    osa (mentor)
DeltaFile
+73-73japanese/navi2ch/pkg-plist
+10-10japanese/navi2ch/Makefile
+83-832 files

FreeBSD/ports f8cebdfjapanese/navi2ch Makefile

japanese/navi2ch: Take maintainership

Remove the mona font from the default option as ASCII art is becoming
obsolete.

PR:             291381
Approved by:    hrs (maintainer timeout)
Approved by:    osa (mentor)
DeltaFile
+2-3japanese/navi2ch/Makefile
+2-31 files

FreeBSD/ports 4225bc1japanese/navi2ch pkg-message Makefile, japanese/navi2ch/files patch-navi2ch-list.el patch-navi2ch-multibbs.el

japanese/navi2ch: Switch RUN_DEPENDS from p5-2chproxy to proxy2ch

Update GH_TAGNAME from faebfd1 to 7811dba.
Add NO_ARCH=yes.
Add a patch to accommodate the url change.
Update pkg-descr.

Changelog:
https://github.com/naota/navi2ch/compare/faebfd1...7811dba

PR:             291381
Approved by:    hrs (maintainer timeout)
Approved by:    osa (mentor)
DeltaFile
+28-0japanese/navi2ch/files/patch-navi2ch-list.el
+20-0japanese/navi2ch/files/patch-navi2ch-multibbs.el
+15-0japanese/navi2ch/files/patch-navi2ch-article.el
+12-3japanese/navi2ch/files/patch-navi2ch-vars.el
+4-4japanese/navi2ch/pkg-message
+4-2japanese/navi2ch/Makefile
+83-92 files not shown
+89-138 files

LLVM/project df461c1clang/lib/CIR/CodeGen CIRGenBuiltin.cpp, clang/test/CIR/CodeGenBuiltins builtin-fpclassify.c

[CIR][CodeGen] Implement __builtin_fpclassify (#187977)

I implemented CIR version of __builtin_fpclassify function.
DeltaFile
+356-0clang/test/CIR/CodeGenBuiltins/builtin-fpclassify.c
+79-1clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+435-12 files