LLVM/project 2c4c9d8llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp SPIRVLegalizeImplicitBinding.cpp, llvm/test/CodeGen/SPIRV/hlsl-resources ImplicitBinding.ll

[SPIRV] Fix inconsistent operand order for counter resource intrinsic (#221646)

The `llvm.spv.resource.handlefrombinding` intrinsic stores its binding
operands in the order (DescriptorSet, BindingNo, ...). The
`llvm.spv.resource.counterhandlefrombinding` intrinsic should use the
same order.

The `llvm.spv.resource.counterhandlefrombinding` intrinsic is currently
emitted only by the `SPIRVLegalizeImplicitBinding` pass. The pass
previously built its operands in the wrong order, and the instruction
selector repeated the same inversion when emitting decorations.

This change makes the operand order consistent with
`llvm.spv.resource.handlefrombinding`.

Test update closes a coverage gap - there were no tests for explicit
`llvm.spv.resource.counterhandlefrombinding` calls.

Assisted by GPT-5.6 Sol.
DeltaFile
+30-3llvm/test/CodeGen/SPIRV/hlsl-resources/ImplicitBinding.ll
+7-5llvm/lib/Target/SPIRV/SPIRVLegalizeImplicitBinding.cpp
+2-2llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+39-103 files

FreeBSD/ports 8fc9772games/veloren-weekly Makefile distinfo

games/veloren-weekly: update to s20260909

Changes:        https://gitlab.com/veloren/veloren/-/compare/f64ec65731...b2bf67917f
(cherry picked from commit b9f4dad8e5557c819e671e32ff4e546d486d6c46)
DeltaFile
+3-3games/veloren-weekly/distinfo
+2-2games/veloren-weekly/Makefile
+5-52 files

FreeBSD/ports 1971a6dwww/gallery-dl Makefile distinfo

www/gallery-dl: update to 1.32.11

Changes:        https://github.com/mikf/gallery-dl/releases/tag/v1.32.11
Reported by:    GitHub (watch releases)

(cherry picked from commit 7c47912b306b6849f0ab28a65466bafcaf1bc57b)
DeltaFile
+3-3www/gallery-dl/distinfo
+1-1www/gallery-dl/Makefile
+4-42 files

NetBSD/pkgsrc 6wfrY1ndoc CHANGES-2026

   doc: Updated lang/akku to 1.1.0
VersionDeltaFile
1.5980+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc FBfWoqqlang Makefile, lang/akku distinfo DESCR

   imported akku 1.1.0
VersionDeltaFile
1.1+287-0lang/akku/PLIST
1.1+42-0lang/akku/patches/patch-spells_define-values.scm
1.1+20-0lang/akku/Makefile
1.1+7-0lang/akku/DESCR
1.1+6-0lang/akku/distinfo
1.797+2-1lang/Makefile
+364-16 files

FreeBSD/ports e26b1e4graphics/mesa-devel Makefile distinfo

graphics/mesa-devel: update to 26.2.b.3053

Changes:        https://gitlab.freedesktop.org/mesa/mesa/-/compare/946b15ec48a...0ba4b08edc6
DeltaFile
+3-3graphics/mesa-devel/distinfo
+2-3graphics/mesa-devel/Makefile
+5-62 files

FreeBSD/ports b9f4dadgames/veloren-weekly Makefile distinfo

games/veloren-weekly: update to s20260909

Changes:        https://gitlab.com/veloren/veloren/-/compare/f64ec65731...b2bf67917f
DeltaFile
+3-3games/veloren-weekly/distinfo
+2-3games/veloren-weekly/Makefile
+5-62 files

FreeBSD/ports c50efd0x11/swayimg distinfo Makefile

x11/swayimg: update to 5.6

Changes:        https://github.com/artemsen/swayimg/releases/tag/v5.6
Reported by:    GitHub (watch releases)
DeltaFile
+15-6x11/swayimg/Makefile
+3-3x11/swayimg/distinfo
+18-92 files

FreeBSD/ports 7c47912www/gallery-dl Makefile distinfo

www/gallery-dl: update to 1.32.11

Changes:        https://github.com/mikf/gallery-dl/releases/tag/v1.32.11
Reported by:    GitHub (watch releases)
DeltaFile
+3-3www/gallery-dl/distinfo
+1-1www/gallery-dl/Makefile
+4-42 files

LLVM/project e6942b4clang/test/CIR/CodeGen call-conv-lowering-x86_64-sret-res-attrs.c

[CIR] Add a C test for the sret res_attrs drop

Assisted-by: Cursor / claude-opus-5
DeltaFile
+41-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-sret-res-attrs.c
+41-01 files

LLVM/project a5ef934clang/docs ReleaseNotes.md, clang/lib/Sema SemaChecking.cpp

[clang] Warn on signed char array constant conversion (#203792)

This resolves #181730: fixes a missing `-Wconstant-conversion`
diagnostic for `signed char` array initialization.

Before this change, Clang warned for `signed char foo = 255;` but did
not
warn for `signed char bar[] = {255};`.

The warning suppression helper did not distinguish between `char`,
`unsigned char`, and `signed char` in brace-initialized arrays. Now it
does.
DeltaFile
+16-5clang/test/Sema/constant-conversion.c
+5-4clang/lib/Sema/SemaChecking.cpp
+3-0clang/docs/ReleaseNotes.md
+24-93 files

LLVM/project 2f704c9clang/docs ReleaseNotes.md, clang/lib/Sema SemaOpenACCClause.cpp

[Clang][OpenACC] Fixed getExtValue Call on Invalid Gang Dim (#221502)

**Problem**
When an invalid 'gang dim' value is used in `CheckGangDimExpr`, the
function prints the value into the diagnostic message by calling
`getExtValue`. This function asserts on values that can't fit into a
signed integer.

**Solution**
`APSInt` has a `<<` operator anyway so just use that.


The fix causes the message to print with the following formatting: 
```
test.cpp:5:40: error: argument to 'gang' clause dimension must be 1, 2, or 3: evaluated to 18'446'744'073'709'551'574
    5 | #pragma acc routine(S::foo) gang(dim : S::foo())
      |                                        ^
1 warning and 1 error generated.
```
Fixes #221418
DeltaFile
+3-3clang/lib/Sema/SemaOpenACCClause.cpp
+3-0clang/test/SemaOpenACC/routine-construct-clauses.cpp
+3-0clang/docs/ReleaseNotes.md
+9-33 files

LLVM/project 3e45797llvm/test/Transforms/LoopVectorize div-exact.ll if-pred-stores.ll, llvm/test/Transforms/LoopVectorize/AArch64 force-target-instruction-cost.ll

[VPlan] Skip branch term in masks for some preserved uniform edges
DeltaFile
+6-425llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll
+90-300llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
+83-117llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
+36-129llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
+9-123llvm/test/Transforms/LoopVectorize/div-exact.ll
+29-89llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
+253-1,18345 files not shown
+666-2,04251 files

HardenedBSD/src 1725e7blib/libjail jail.c, sys/compat/linuxkpi/common/include/linux pci.h util_macros.h

Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/pledge
DeltaFile
+25-6lib/libjail/jail.c
+27-0sys/compat/linuxkpi/common/src/linux_pci.c
+26-0sys/compat/linuxkpi/common/include/linux/cleanup.h
+18-0sys/compat/linuxkpi/common/include/linux/util_macros.h
+4-1usr.sbin/jail/tests/jail_basic_test.sh
+5-0sys/compat/linuxkpi/common/include/linux/pci.h
+105-75 files not shown
+114-911 files

HardenedBSD/src 2885133lib/libjail jail.c, sys/compat/linuxkpi/common/include/linux pci.h util_macros.h

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+25-6lib/libjail/jail.c
+27-0sys/compat/linuxkpi/common/src/linux_pci.c
+26-0sys/compat/linuxkpi/common/include/linux/cleanup.h
+18-0sys/compat/linuxkpi/common/include/linux/util_macros.h
+4-1usr.sbin/jail/tests/jail_basic_test.sh
+5-0sys/compat/linuxkpi/common/include/linux/pci.h
+105-75 files not shown
+114-911 files

HardenedBSD/ports f92c699multimedia/mediamtx/files patch-internal_core_core.go, net/libpcap Makefile

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+215-0x11-fonts/monaspace/pkg-plist
+0-96ports-mgmt/appstream-generator/files/patch-backend
+68-7multimedia/mediamtx/files/patch-internal_core_core.go
+0-65net/libpcap/files/patch-Makefile.in
+36-14sysutils/py-salt/Makefile
+28-15net/libpcap/Makefile
+347-19788 files not shown
+718-50194 files

LLVM/project 18a8d12clang/test/CIR/CodeGen cxx20-module-initializer.cppm, clang/test/CIR/CodeGenCXX typeid-should-throw.cpp typeid-most-derived.cpp

[CIR] Fix CIR tests by adding a triple/Requires. (#222346)

Now that we're trying to build by default, we actually have to be able
to build on other buildbots! But since we still don't have the
ABI/target stuff for non linux, we need to make sure our tests don't hit
that. Tests that execute 'clang' in some way are given a triple, ones
that are on .cir files we just add a 'requires'. Some day we should be
able to remove those, but it'll require us to add the cxxabi/etc for
windows.
DeltaFile
+3-3clang/test/CIR/Transforms/lib-opt.cpp
+2-2clang/test/CIR/CodeGenCXX/typeid-should-throw.cpp
+2-2clang/test/CIR/CodeGenCXX/typeid-most-derived.cpp
+1-1clang/test/CIR/Transforms/idiom-recognizer.cpp
+1-1clang/test/CIR/CodeGen/cxx20-module-initializer.cppm
+1-0clang/test/CIR/Tools/warn-default-triple.cir
+10-96 files not shown
+16-912 files

LLVM/project eadaccellvm/lib/Target/AMDGPU VOPCInstructions.td VOPInstructions.td, llvm/test/CodeGen/AMDGPU coexec-sched-flavor-classification.mir

[AMDGPU] Model GFX1250 VALU blocking cycles

Some gfx1250 VALU instructions block the VALU pipe for N cycles, and
the CoExec scheduler must model that occupancy. The existing SchedModel
cannot represent this given current modelling constraints (see #202775).

Attach GFX1250BlockingCycles to the VOP instruction definitions and
emit a searchable table so SIInstrInfo::getBlockingCycles() can report
the occupancy. CoExec uses that to classify multi-cycle VALU and to
account for blocking when computing HWUI cycles.

Authored by Jeffrey Byrnes <jeffrey.byrnes at amd.com>
DeltaFile
+132-6llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+56-38llvm/lib/Target/AMDGPU/VOP3Instructions.td
+23-16llvm/lib/Target/AMDGPU/VOP1Instructions.td
+19-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+15-0llvm/lib/Target/AMDGPU/VOPInstructions.td
+9-2llvm/lib/Target/AMDGPU/VOPCInstructions.td
+254-623 files not shown
+271-679 files

LLVM/project a53bc4fllvm/cmake/modules AddLLVM.cmake, mlir/cmake/modules AddMLIR.cmake

[mlir] Reuse the MLIRIR PCH through dependencies (NFC)

Track whether an MLIR library's link closure reaches MLIRIR and reuse the
MLIRIR PCH for those libraries. Preserve higher-priority local PCHs and add an
explicit opt-out for targets whose sources are incompatible with reuse.

Relative to the core and LLVM dialect PCH parent, clean Release builds of LLVM
and MLIR with Ninja -j16 pinned to CPUs 16-31 improved as follows:

  wall:   398.79s -> 386.47s (-3.09%)
  user:  5789.14s -> 5624.02s (-2.85%)
  system: 455.05s -> 438.45s (-3.65%)

Assisted-by: Codex
DeltaFile
+60-1mlir/cmake/modules/AddMLIR.cmake
+38-0mlir/test/lib/CMake/CMakeLists.txt
+8-1llvm/cmake/modules/AddLLVM.cmake
+1-0mlir/test/lib/CMakeLists.txt
+1-0mlir/test/lib/CMake/Inputs/PCHOptOut.cpp
+1-0mlir/test/lib/CMake/Inputs/PCHOptOut.c
+109-26 files

LLVM/project 707c032mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/test/Dialect/Tosa ops.mlir invalid_extension.mlir

[mlir][tosa] Add support for MXFP SCATTER (#222288)

Tosa specification changes in
https://github.com/arm/tosa-specification/pull/78
DeltaFile
+60-0mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+16-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+8-0mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
+7-0mlir/test/Dialect/Tosa/ops.mlir
+7-0mlir/test/Dialect/Tosa/invalid_extension.mlir
+98-05 files

LLVM/project 81b343fmlir/include/mlir/Dialect/LLVMIR pch.h, mlir/lib CMakeLists.txt

[mlir][LLVM] Reuse a PCH for MLIRLLVMDialect (NFC)

Build a private precompiled header from the LLVM dialect and LLVM IR headers
and use it for MLIRLLVMDialect. Build dialect libraries before conversions so
the PCH is available early and repeated parsing is avoided.

Relative to the MLIRIR PCH parent, clean Release builds of LLVM and MLIR with
Ninja -j16 pinned to CPUs 16-31 improved as follows:

  wall:   420.41s -> 398.79s (-5.14%)
  user:  6125.97s -> 5789.14s (-5.50%)
  system: 481.88s -> 455.05s (-5.57%)

Assisted-by: Codex
DeltaFile
+14-0mlir/include/mlir/Dialect/LLVMIR/pch.h
+3-0mlir/lib/Dialect/LLVMIR/CMakeLists.txt
+1-1mlir/lib/CMakeLists.txt
+18-13 files

LLVM/project 2d70439llvm/utils/gn/secondary/lldb/test BUILD.gn

[gn] port eb5cd179549d68 (#222476)
DeltaFile
+0-1llvm/utils/gn/secondary/lldb/test/BUILD.gn
+0-11 files

LLVM/project cdf702dmlir/include/mlir/IR pch.h, mlir/lib CMakeLists.txt

[mlir] Reuse a precompiled header for MLIRIR (NFC)

Build a private precompiled header from the common MLIR IR headers and use it
for MLIRIR. Build Support and IR first so the PCH is available early, and
qualify the LLVM LSP Location name that the broader header surface exposes.

On current main, clean Release builds of LLVM and MLIR with Ninja -j16 pinned
to CPUs 16-31 improved as follows:

  wall:   535.99s -> 420.41s (-21.56%)
  user:  7550.29s -> 6125.97s (-18.86%)
  system: 569.85s -> 481.88s (-15.44%)

Assisted-by: Codex
DeltaFile
+20-0mlir/include/mlir/IR/pch.h
+8-8mlir/lib/Tools/mlir-lsp-server/LSPServer.cpp
+2-2mlir/lib/CMakeLists.txt
+3-0mlir/lib/IR/CMakeLists.txt
+33-104 files

OpenZFS/src 75bd31cmodule/zfs arc.c

L2ARC: do not feed a device while its rebuild is pending

l2arc_add_vdev() leaves the device at l2ad_start with l2ad_first set,
marks it l2ad_rebuild, and starts its feed thread.  The rebuild runs
later from the spa async thread and only then restores the geometry the
on-disk header describes.

A feed in that window writes at l2ad_start believing the device is
empty, and its headers go on the head of l2ad_buflist while the rebuild
appends the restored ones at the tail.  l2arc_evict() walks that list
from the tail and stops at the first header outside the range it is
clearing, so once list position stops tracking device offset the walk
exits early, headers the hand is about to overwrite are never destroyed,
and the writes that replace them charge the space twice.  vs_alloc
passes vs_space and zpool(8) reports 16.0E free.

l2arc_dev_invalid() rejected a device with l2ad_rebuild or l2ad_trim_all
set until b525525b4 made the feed threads per-device; neither flag has
had a reader since.  Restore the test, after SCL_L2ARC is taken so it

    [7 lines not shown]
DeltaFile
+5-0module/zfs/arc.c
+5-01 files

LLVM/project 265bb9fclang/lib/Basic/Targets AMDGPU.cpp AMDGPU.h, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

AMDGPU: Migrate R600 onto generated TargetParser bitset (#222461)

Follow the new amdgcn system so we don't have to carry 2 different
forms of this infrastructure.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+80-36llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+12-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+8-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+1-5clang/lib/Basic/Targets/AMDGPU.cpp
+2-4clang/lib/Basic/Targets/AMDGPU.h
+5-0llvm/lib/Target/AMDGPU/R600Processors.td
+108-451 files not shown
+111-457 files

NetBSD/src TG8B0wwdistrib/utils/embedded/conf riscv64mbr.conf riscv64.conf

   s/kernel_GENERIC/kernel_GENERIC64, sync with arm64.
VersionDeltaFile
1.2+3-3distrib/utils/embedded/conf/riscv64mbr.conf
1.2+3-3distrib/utils/embedded/conf/riscv64.conf
+6-62 files

LLVM/project 70e79a0llvm/lib/Target/X86/AsmParser X86AsmParser.cpp, llvm/test/MC/X86 x86_errors.s

[X86] Reject a register where a memory operand displacement belongs (#216068)

Fixes #61438
DeltaFile
+13-0llvm/test/MC/X86/x86_errors.s
+5-1llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+18-12 files

LLVM/project 7c5e5callvm/utils profcheck-xfail.txt

[ProfCheck] Removing passing tests from xfail list (#222473)

These tests appear to be passing/deleted as of 9/9/26.
DeltaFile
+0-4llvm/utils/profcheck-xfail.txt
+0-41 files

LLVM/project f1b62b8clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl

First attempt implementing InterlockedCompareExchangeFloatBitwise
DeltaFile
+119-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchangeFloatBitwise-errors.hlsl
+43-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchangeFloatBitwise.hlsl
+42-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl
+32-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+25-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+10-3clang/lib/Sema/SemaHLSL.cpp
+271-35 files not shown
+302-611 files

LLVM/project f861da9clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl InterlockedCompareStoreFloatBitwise.hlsl

First attempt implementing InterlockedCompareStoreFloatBitwise
DeltaFile
+100-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
+39-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
+35-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
+30-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
+20-8clang/lib/Sema/SemaHLSL.cpp
+27-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
+251-86 files not shown
+316-1312 files