LLVM/project 14ea3a1mlir/include/mlir/Dialect/LLVMIR ROCDLOps.td, mlir/test/Dialect/LLVMIR rocdl.mlir

[mlir][ROCDL] Add rocdl.wave.barrier (#195357)

Co-authored-by: Claude Opus 4.7 (1M context) <noreply at anthropic.com>
DeltaFile
+13-0mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+7-0mlir/test/Target/LLVMIR/rocdl.mlir
+6-0mlir/test/Dialect/LLVMIR/rocdl.mlir
+26-03 files

LLVM/project a235362clang/include/clang/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis SourcePassAnalysis.h

improve doc/comments
DeltaFile
+11-7clang/include/clang/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis/SourcePassAnalysis.h
+11-71 files

FreeBSD/ports a47da9fwww/gitlab-workhorse/files patch-internal_gitaly_blob.go

www/gitlab-workhorse: fix build on armv7

This cast is a no-op on 64 bit platforms and prevents a type error
on 32-bit platforms.

Approved by:    portmgr (build fix blanket)
PR:             2026Q2

(cherry picked from commit 4731beeec6f8dad167fa3b3ff8d4848aea26c2fc)
DeltaFile
+11-0www/gitlab-workhorse/files/patch-internal_gitaly_blob.go
+11-01 files

FreeBSD/ports e244144devel/gitaly/files patch-internal_command_command.go

devel/gitaly: fix build on armv7

Apparently these are not int64 on 32-bit platforms.

Approved by:    portmgr (build fix blanket)
MFH:            2026Q2

(cherry picked from commit e665c2bc9970aebba5a2a021092b0ca753204f84)
DeltaFile
+17-0devel/gitaly/files/patch-internal_command_command.go
+17-01 files

LLVM/project 8f46a9dllvm/test/tools/llvm-profgen filter-build-id.test, llvm/test/tools/llvm-profgen/Inputs buildid-cs-noprobe.aggperfscript buildid-cs-noprobe.perfscript

[llvm-profgen] Support [buildid:]0xaddr format in perfscript input (#190863)

Add support for optional build ID prefix in perfscript addresses,
following the format buildid:0xhexaddr. This enables multi-DSO profiling
with a single input file: each address optionally carries a build ID,
and profgen filters addresses by matching the binary's build ID.

--filter-build-id=<hex> CLI option overrides auto-detected build ID.
DeltaFile
+58-13llvm/tools/llvm-profgen/PerfReader.cpp
+57-0llvm/test/tools/llvm-profgen/filter-build-id.test
+11-0llvm/test/tools/llvm-profgen/Inputs/buildid-cs-noprobe.aggperfscript
+9-0llvm/test/tools/llvm-profgen/Inputs/buildid-cs-noprobe.perfscript
+135-134 files

LLVM/project 627813cclang/test/CIR/CodeGenCUDA address-spaces.cu

Fix cc mismatch
DeltaFile
+1-1clang/test/CIR/CodeGenCUDA/address-spaces.cu
+1-11 files

LLVM/project ff91bf8lldb/include/lldb/Symbol VariableList.h, lldb/source/Symbol VariableList.cpp

[lldb] Make VariableList::FindVariable const (NFC) (#195355)

I was surprised to find `FindVariable` was not `const`. While making it
`const`, I also replaced the iterator based loop with a ranged based
loop.
DeltaFile
+12-24lldb/source/Symbol/VariableList.cpp
+3-4lldb/include/lldb/Symbol/VariableList.h
+15-282 files

LLVM/project dfb7a66clang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp

fix fmt
DeltaFile
+4-5clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+4-51 files

LLVM/project 25af42dclang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp, clang/test/CIR/CodeGenCUDA device-stub.cu

[CIR][HIP] Handle HIP module constructor and destructor emission
DeltaFile
+147-5clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+121-0clang/test/CIR/CodeGenCUDA/device-stub.cu
+268-52 files

FreeBSD/ports e665c2bdevel/gitaly/files patch-internal_command_command.go

devel/gitaly: fix build on armv7

Apparently these are not int64 on 32-bit platforms.

Approved by:    portmgr (build fix blanket)
MFH:            2026Q2
DeltaFile
+17-0devel/gitaly/files/patch-internal_command_command.go
+17-01 files

FreeBSD/ports 4731beewww/gitlab-workhorse/files patch-internal_gitaly_blob.go

www/gitlab-workhorse: fix build on armv7

This cast is a no-op on 64 bit platforms and prevents a type error
on 32-bit platforms.

Approved by:    portmgr (build fix blanket)
PR:             2026Q2
DeltaFile
+11-0www/gitlab-workhorse/files/patch-internal_gitaly_blob.go
+11-01 files

LLVM/project 1baf1a0utils/bazel/llvm-project-overlay/llvm/unittests BUILD.bazel

[Bazel] Fixes 30463fb (#195375)

This fixes 30463fbc4cd49bc1caa02bf799da5226dd5d7927.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
+1-01 files

LLVM/project d073a10llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

rebase

Created using spr 1.3.4
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-010,333 files not shown
+1,452,699-291,86310,339 files

LLVM/project b6af213llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-010,333 files not shown
+1,452,699-291,86310,339 files

LLVM/project 45b1195llvm/tools/llvm-profgen PerfReader.cpp PerfReader.h

[llvm-profgen][NFC] Reuse isLBRSample (#191595)

Replace `StringRef::starts_with(" 0x")` calls with explicit
`isLBRSample` checks.
This is needed to support buildid-prefixed addresses in a follow-up
#190863.
DeltaFile
+9-7llvm/tools/llvm-profgen/PerfReader.cpp
+1-1llvm/tools/llvm-profgen/PerfReader.h
+10-82 files

LLVM/project 8fec6f4lld/MachO ConcatOutputSection.cpp

Avoid calling markBranchAsResolved() when we discover a thunk in range

The only way for a thunk to be in range is if we created one. In that
case, we already call thunkInfo.pendingBranches.clear() so there is no
need to remove this branch.
DeltaFile
+4-5lld/MachO/ConcatOutputSection.cpp
+4-51 files

Linux/linux f1a5e78drivers/gpu/drm/amd/amdgpu gfx_v6_0.c amdgpu_kms.c, drivers/gpu/drm/amd/display/dc/bios bios_parser.c

Merge tag 'drm-fixes-2026-05-02' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "Fixes for rc2, the usual amdgpu/xe double header, I think xe had a
  couple of weeks combined due to some maintainer access issues,
  otherwise there's just a few misc fixes and documentation fixups.

  core and helpers:
   - calculate framebuffer geometry with format helpers
   - fix docs

  amdgpu:
   - GFX12 fix for CONFIG_DRM_DEBUG_MM configs
   - Fix DC analog support
   - Userq fixes
   - GART placement fix
   - Aldebaran SMU fixes
   - AMDGPU_INFO_READ_MMR_REG fix
   - UVD 3.1 fix

    [64 lines not shown]
DeltaFile
+403-0drivers/gpu/drm/xe/xe_mem_pool.c
+59-35drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+72-1drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+66-0drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+24-33drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+31-25drivers/gpu/drm/xe/xe_migrate.c
+655-9482 files not shown
+1,085-26988 files

LLVM/project 80c4302llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

rebase

Created using spr 1.3.4
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-010,333 files not shown
+1,452,705-291,87710,339 files

LLVM/project 2203242llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-010,333 files not shown
+1,452,705-291,87710,339 files

LLVM/project f089c0fllvm/tools/llvm-profgen PerfReader.cpp

[llvm-profgen][NFC] Factor out parseAddress (#191594)

Replace `StringRef::getAsInteger(16)` calls with explicit `parseAddress`
to make it easier to support buildid-prefixed addresses in a follow-up
(#190863).
DeltaFile
+12-5llvm/tools/llvm-profgen/PerfReader.cpp
+12-51 files

FreeBSD/src c4f08d4packages/toolchain Makefile, usr.bin/clang/llvm-ar Makefile

llvm-*: Move all LLVM_BINUTILS symlinks to toolchain package

Some of the LLVM binary utilities were included in the Clang package
(because they did not set an explicit PACKAGE).

Add a new Makefile under clang/toolchain to create the symlinks and man
links for ar, c++filt, nm, and so on (without the llvm-* prefix) when
LLVM_BINUTILS is enabled (as it is by default).

PR:             293610
Reviewed by:    bapt, ivy, brooks
Sponsored by:   The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D55692
DeltaFile
+35-0usr.bin/clang/toolchain/Makefile
+0-7usr.bin/clang/llvm-ar/Makefile
+0-7usr.bin/clang/llvm-objcopy/Makefile
+6-0packages/toolchain/Makefile
+0-6usr.bin/clang/llvm-nm/Makefile
+0-6usr.bin/clang/llvm-size/Makefile
+41-265 files not shown
+45-4211 files

LLVM/project 2dca922llvm/test/Transforms/LowerTypeTests aarch64-jumptable-dbg.ll x86-jumptable-dbg.ll

[NFC][LowerTypeTests] Pre-commit tests with debug info kill switch (#195373)

For https://github.com/llvm/llvm-project/pull/194493
DeltaFile
+39-0llvm/test/Transforms/LowerTypeTests/aarch64-jumptable-dbg.ll
+38-0llvm/test/Transforms/LowerTypeTests/x86-jumptable-dbg.ll
+77-02 files

Linux/linux cd546f7arch/arm64/include/asm irqflags.h kernel-pgtable.h, arch/arm64/kernel signal.c

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:

 - Avoid writing an uninitialised stack variable to POR_EL0 on sigreturn
   if the poe_context record is absent

 - Reserve one more page for the early 4K-page kernel mapping to cover
   the extra [_text, _stext) split introduced by the non-executable
   read-only mapping

 - Force the arch_local_irq_*() wrappers to be __always_inline so that
   noinstr entry and idle paths cannot call out-of-line, instrumentable
   copies

 - Fix potential sign extension in the arm64 SCS unwinder's DWARF
   advance_loc4 decoding

 - Tolerate arm64 ACPI platforms with only WFI and no deeper PSCI idle

    [14 lines not shown]
DeltaFile
+43-11arch/arm64/kernel/signal.c
+7-7arch/arm64/include/asm/irqflags.h
+3-7drivers/acpi/arm64/cpuidle.c
+6-1arch/arm64/include/asm/kernel-pgtable.h
+0-6tools/testing/selftests/arm64/gcs/gcs-util.h
+2-2arch/arm64/kernel/pi/patch-scs.c
+61-341 files not shown
+62-347 files

LLVM/project 8653946clang/lib/CIR/CodeGen TargetInfo.cpp, clang/test/CIR/CodeGenCUDA ptx-kernels.cu

[CIR][CUDA] Set ptx_kernel calling convention on CUDA kernels
DeltaFile
+42-0clang/test/CIR/CodeGenCUDA/ptx-kernels.cu
+18-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+60-02 files

LLVM/project 25c3fa2libcxx/test/selftest/dsl dsl.sh.py

[libcxx][lit] Fix dsl.sh.py test failure on Windows (#195230)

We are seeing linux runtimes test failures on Windows host after PR
#194752 was merged. The runtimes unit test is producing Unix style line
break symbol on Windows, causing dsl.sh.py to fail. This patch mitigate
this issue by converting Windows style line breaks to Unix style ones to
mitigate this issue.
DeltaFile
+12-5libcxx/test/selftest/dsl/dsl.sh.py
+12-51 files

LLVM/project 2a95dc8clang/lib/CIR/CodeGen TargetInfo.cpp, clang/test/CIR/CodeGenCUDA ptx-kernels.cu

[CIR][CUDA] Set ptx_kernel calling convention on CUDA kernels
DeltaFile
+46-0clang/test/CIR/CodeGenCUDA/ptx-kernels.cu
+18-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+64-02 files

LLVM/project 8cba4e8clang/lib/CIR/CodeGen/Targets AMDGPU.cpp, clang/test/CIR/CodeGenHIP amdgpu-attrs.hip

[CIR][AMDGPU] Set amdgpu_kernel calling convention on HIP kernels
DeltaFile
+2-2clang/test/CIR/CodeGenHIP/amdgpu-attrs.hip
+2-1clang/lib/CIR/CodeGen/Targets/AMDGPU.cpp
+4-32 files

LLVM/project 175dfa2clang/test/Instrumentor StackUsageRT.cpp

Apply suggestion from @jdoerfert
DeltaFile
+1-1clang/test/Instrumentor/StackUsageRT.cpp
+1-11 files

LLVM/project af422bfllvm/docs/RISCV RISCVVectorExtension.rst

[RISCV][docs] Document RISCVVLOptimizer and remove trivial VP intrinsics (#195358)
DeltaFile
+25-27llvm/docs/RISCV/RISCVVectorExtension.rst
+25-271 files

LLVM/project 3cb88c8llvm/tools/llvm-profgen PerfReader.cpp PerfReader.h

rebase

Created using spr 1.3.4
DeltaFile
+6-9llvm/tools/llvm-profgen/PerfReader.cpp
+2-7llvm/tools/llvm-profgen/PerfReader.h
+8-162 files