[LoongArch] Select `V{AND,OR,XOR,NOR}I.B` for bitwise with byte splat immediates
The `V{AND,OR,XOR,NOR}I.B` instructions operate on byte elements and accept
an 8-bit immediate. However, when the same byte splat constant is used with
wider vector element types (e.g. v8i16, v4i32, v2i64), instruction selection
currently falls back to materializing the constant in a temporary register.
```
vrepli.b -1
vxor.v
```
even though the immediate form is available:
```
vxori.b 255
```
This happens because selectVSplatImm requires the splat bit width to match
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[LoongArch] Select V{ADD,SUB}I for operations with negative splat immediates
Currently, vector add/sub with a negative splat immediate is lowered as a
vector splat followed by a register-register add, e.g.:
```
vrepli.b $vr1, -1
vadd.b $vr0, $vr0, $vr1
```
This misses the opportunity to use the more efficient V{ADD,SUB}I instruction
with a positive immediate.
This patch introduces `selectVSplatImmNeg` to detect negative splat
immediates whose negated value fits in a 5-bit unsigned immediate. New
patterns `(Pat{Vr,Vr}Nimm5)` are added to match:
```
add v, splat(-imm) --> vsubi v, v, imm
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[libc][threads] adjust futex library and expose requeue API (#192478)
Make futex a common abstraction layer across platforms.
(linux/wasm/macOS/windows/fuchsia all have the support, which we can
align their support later on).
This patch also expose a requeue API that returns ENOSYS on unsupported
platforms. The requeue operation will be needed to reimplement a strict
FIFO style condvar similar to musl.
Additional cleanup is done to change raw syscall return value to
`ErrorOr<int>`.
Assisted-by: Codex with gpt-5.4 medium fast
rge: add disable_aspm tunable for PCIe power management
Add a per-interface loader tunable dev.rge.%d.disable_aspm to
disable PCIe ASPM (L0s/L1) and ECPM on the RTL8125/8126/8127.
Disabling ASPM reduces latency at the cost of higher power
consumption. Default is off (ASPM left as configured by BIOS).
Signed-off-by: Christos Longros <chris.longros at gmail.com>
Reviewed by: adrian
Differential Revision: https://reviews.freebsd.org/D56103
[mlir][memref] Remove unit-stride restriction in SubViewOp folding (#192437)
This PR replaces manual offset/size resolution with `affine::mergeOffsetsSizesAndStrides`, simplifying the code and extending subview-of-subview folding to support non-unit strides.
[RISCV] Support MachineOutlinerRegSave for RISCV (#191351)
This patch adds support for the RegSave strategy in the RISC-V
MachineOutliner pass. It uses t1–t6 to preserve the t0 value across the
outlined function call when t0 is unavailable. This enables more
potential outlining candidates.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
CI: Do not set scheduler in qemu-1-setup.sh
We've seen some qemu-1-setup failures while trying to change the
runner's block device scheduler value to 'none':
We have a single 150GB block device
Setting up swapspace version 1, size = 16 GiB (17179865088 bytes)
no label, UUID=7a790bfe-79e5-4e38-b208-9c63fe523294
tee: '/sys/block/s*/queue/scheduler': No such file or directory
Luckily, we don't need to set the scheduler anymore on modern kernels:
https://github.com/openzfs/zfs/issues/9778#issuecomment-569347505
This commit just removes the code that sets the scheduler.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Tony Hutter <hutter2 at llnl.gov>
Closes #18437
[DAGCombiner] Extend convertBuildVecZextToZext to sign extends (#192372)
Generalize the existing fold that collapses a BUILD_VECTOR of ZERO_EXTEND
(or ANY_EXTEND) of EXTRACT_VECTOR_ELTs into a single vector extend so that
it also handles SIGN_EXTEND. Mixed sign and zero extends remain unsupported
because their high-bit semantics differ, so the combine bails out in that
case.
---------
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
ntp_adjtime.2: Increase visibility
+ s/ntp/ntpd/ for correctness + apropos results in document description
+ silence a linter warning by escaping a period with a zero-width space
MFC after: 3 days
