LLVM/project fdf4eb1libcxx/include/__memory uninitialized_algorithms.h, libcxx/test/libcxx/memory uninitialized_allocator_copy_template_op_assign.pass.cpp

[libc++] Require the exact assignment expression to be trivial in __uninitialized_allocator_copy_impl

__uninitialized_allocator_copy_impl has an optimization that replaces allocator_traits::construct with std::copy for raw pointer ranges when the element type is trivially copy constructible and trivially copy assignable.

The copy-assignment trait only checks whether assignment from const T& is trivial. That is weaker than the expression used by std::copy, which evaluates *out = *in. If overload resolution selects a different non-trivial assignment operator for that expression, std::copy can call that operator on uninitialized storage.

Check is_trivially_assignable<_Out&, _In&> instead. This matches the assignment expression used by std::copy, preserves the optimized path when that assignment is actually trivial, and falls back to placement construction otherwise.

Add a regression test with a type whose defaulted copy assignment is trivial but whose templated assignment operator is selected for non-const lvalue sources.

Tested with:
~/llvm-project/build-libcxx-fresh/bin/llvm-lit ~/llvm-project/libcxx/test/libcxx/memory/uninitialized_allocator_copy_template_op_assign.pass.cpp ~/llvm-project/libcxx/test/libcxx/memory/uninitialized_allocator_copy.pass.cpp -q
DeltaFile
+66-0libcxx/test/libcxx/memory/uninitialized_allocator_copy_template_op_assign.pass.cpp
+1-1libcxx/include/__memory/uninitialized_algorithms.h
+67-12 files

OpenBSD/ports HiYXOBrnet/p5-Net-DHCP Makefile, net/p5-Net-DHCP/patches patch-t_102-discover-offer-request-ack_t patch-t_103-real-nak_t

   update p5-Net-DHCP to 0.700
   disable test that require a huge dependency tree
   take maintainer
VersionDeltaFile
1.9+15-8net/p5-Net-DHCP/Makefile
1.1+20-0net/p5-Net-DHCP/patches/patch-t_102-discover-offer-request-ack_t
1.1+20-0net/p5-Net-DHCP/patches/patch-t_103-real-nak_t
1.1+20-0net/p5-Net-DHCP/patches/patch-t_104-offer-o90-o120_t
1.1+20-0net/p5-Net-DHCP/patches/patch-t_105-discover-offer-o122-o82_t
1.1+20-0net/p5-Net-DHCP/patches/patch-t_106-discover-offer-o60-o43-o82_t
+115-83 files not shown
+146-109 files

LLVM/project b1b3b43.github/workflows libc-overlay-tests.yml libc-fullbuild-tests.yml, libc/cmake/modules LLVMLibCCheckCpuFeatures.cmake

[libc] Disable -march=native in CI to fix sccache poisoning (#196560)

-march=native is incompatible with shared build caches because sccache
treats it as a literal string. Object files compiled on one CPU model
get silently served to runners with a different CPU, causing SIGILL
crashes in the opt_host memory tests.

Made LIBC_COMPILE_OPTIONS_NATIVE a CMake cache variable so CI can
override it. Both overlay and fullbuild workflows now pass
-DLIBC_COMPILE_OPTIONS_NATIVE="" to disable -march=native. Local
developer builds are unaffected and still default to -march=native.

Reverted the per-CPU cache key approach from #196477 in favour of this
fix, which addresses the root cause.

Bumped sccache key versions (v2) in both workflows to invalidate the
poisoned caches.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+2-26.github/workflows/libc-overlay-tests.yml
+16-3libc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
+3-2.github/workflows/libc-fullbuild-tests.yml
+21-313 files

FreeNAS/freenas 90b5a3b

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeBSD/ports 22c6d9anet/amnezia-kmod distinfo Makefile

net/amnezia-kmod: Update 2.0.10 => 2.0.11

Changelog:
- Fix mbuf leak on processing invalid packets.
https://github.com/vgrebenschikov/wireguard-amnezia-kmod/releases/tag/v2.0.11

PR:             295108
Sponsored by:   UNIS Labs
MFH:            2026Q2

(cherry picked from commit f6e3eec6fbb45ccdb3ece1e5db70286948535896)
DeltaFile
+3-3net/amnezia-kmod/distinfo
+1-1net/amnezia-kmod/Makefile
+4-42 files

FreeNAS/freenas f74948asrc/middlewared/middlewared/alert/source update.py, src/middlewared/middlewared/migration 0015_update_profile.py

NAS-140905 / 26.0.0-RC.1 / Stop migration 0015 from forcing MISSION_CRITICAL profile (#18916)

Two small fixes for issues present on Goldeye:

- Migration `0015_update_profile.py` was force-setting `update.profile =
MISSION_CRITICAL` on every enterprise system regardless of the running
version's actual profile. A user upgrading from Fangtooth to a Goldeye
`EARLY_ADOPTER` release (e.g. 25.10-RC.1) was silently locked into
`MISSION_CRITICAL`. Once 25.10.3 (the first `MISSION_CRITICAL` Goldeye
release) shipped, `update.status` started returning a profile mismatch
and the `CurrentlyRunningVersionDoesNotMatchProfile` alert fired.
Migration is now a no-op; `update.config` already auto-populates
`profile` from `current_version_profile()` on first read.
- The mismatch alert was resolving profile names through
`update.profile_choices`, which filters out profiles outside the user's
product type (enterprise hides `DEVELOPER`/`EARLY_ADOPTER`). When the
running profile fell outside that filter, the alert text rendered
`<Unknown>` instead of the friendly name. Switched to resolving via
`UpdateProfiles[...].describe().name`.

    [3 lines not shown]
DeltaFile
+10-13src/middlewared/middlewared/alert/source/update.py
+0-11src/middlewared/middlewared/migration/0015_update_profile.py
+4-0src/middlewared/middlewared/plugins/update_/profile_.py
+14-243 files

FreeBSD/ports f6e3eecnet/amnezia-kmod distinfo Makefile

net/amnezia-kmod: Update 2.0.10 => 2.0.11

Changelog:
- Fix mbuf leak on processing invalid packets.
https://github.com/vgrebenschikov/wireguard-amnezia-kmod/releases/tag/v2.0.11

PR:             295108
Sponsored by:   UNIS Labs
MFH:            2026Q2
DeltaFile
+3-3net/amnezia-kmod/distinfo
+1-1net/amnezia-kmod/Makefile
+4-42 files

LLVM/project 1e28dballvm/include/llvm/IR Intrinsics.h, llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

keep all comments

Created using spr 1.3.4
DeltaFile
+244-245llvm/include/llvm/IR/Intrinsics.h
+278-0llvm/test/Instrumentation/MemorySanitizer/ftrunc.ll
+139-0llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
+115-0llvm/test/CodeGen/RISCV/stack-probing-dynamic-nonentry.ll
+70-19llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+73-0mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm.mlir
+919-26431 files not shown
+1,158-32637 files

FreeNAS/freenas 6ed3216src/middlewared/middlewared/alert/source update.py, src/middlewared/middlewared/plugins/update_ profile_.py

rename `display_name`
DeltaFile
+1-1src/middlewared/middlewared/alert/source/update.py
+1-1src/middlewared/middlewared/plugins/update_/profile_.py
+2-22 files

LLVM/project a47d363llvm/lib/DWARFLinker/Parallel DependencyTracker.cpp, llvm/test/tools/dsymutil/Inputs/odr-static-member-decl a.o b.o

[DWARFLinker] Don't duplicate classes with in-class static decls (#196442)

An in-class static declaration was forced to PlainDwarf placement and
cascaded that up to its enclosing class. If the class was already in the
type table via the out-of-line definition's specification, it ended up
with Both placement and cloneDIE emitted two copies. Keep in-class
static declarations in the type table so they stay with their enclosing
type.
DeltaFile
+104-0llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-static-member-decl.test
+26-0llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp
+0-0llvm/test/tools/dsymutil/Inputs/odr-static-member-decl/a.o
+0-0llvm/test/tools/dsymutil/Inputs/odr-static-member-decl/b.o
+130-04 files

LLVM/project cb749c8mlir/test/lib/Dialect/Vector TestVectorTransforms.cpp

format

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+4-4mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
+4-41 files

LLVM/project 7748bf5libc/cmake/modules LLVMLibCFlagRules.cmake

[libc] Skip targets with unavailable __ONLY flags (#196637)

When SKIP_FLAG_EXPANSION strips a flag that has the __ONLY modifier,
remove_duplicated_flags drops the flag from the list. This leaves
expand_flags_for_target with an empty flag list, causing it to create a
plain (non-flag) target. The __ONLY semantics, "only build this target
with the flag active", are silently violated.

On x86-64 CI runners without FMA, this results in cosf_float_test and
sinf_float_test being built and linked without FMA. The sincosf
algorithm was tuned assuming fused multiply-add precision, so the
unfused x*y+z fallback exceeds the 3.5 ULP tolerance (57 ULP for cosf,
12 ULP for sinf).

Added an early return in add_target_with_flags: if any flag with the
__ONLY modifier would be skipped, the target is not generated.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+16-0libc/cmake/modules/LLVMLibCFlagRules.cmake
+16-01 files

LLVM/project 129021fmlir/include/mlir/Dialect/Vector/Transforms LoweringPatterns.h, mlir/lib/Dialect/Vector/Transforms LowerVectorContract.cpp

format

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+7-12mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp
+4-8mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
+11-202 files

LLVM/project aa7cb8ellvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.fp8.e5m3.ll

AMDGPU/GlobalISel: RegBankLegalize rules for cvt fp8 e5m3 intrinsics (#196369)
DeltaFile
+56-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+61-42 files

LLVM/project 33d30f4mlir/include/mlir/Dialect/Vector/Transforms LoweringPatterns.h

nit

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+0-4mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
+0-41 files

LLVM/project 7b5bb30llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.cluster.load.ll

AMDGPU/GlobalISel: RegBankLegalize rules for cluster_load_b32/b64/b128 (#196186)
DeltaFile
+54-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
+19-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+73-12 files

FreeNAS/freenas 5a6f945src/middlewared/middlewared/alert/source update.py, src/middlewared/middlewared/plugins/update_ profile_.py

don't override builtin name prop
DeltaFile
+1-1src/middlewared/middlewared/alert/source/update.py
+1-1src/middlewared/middlewared/plugins/update_/profile_.py
+2-22 files

LLVM/project 0c0126dllvm/lib/DWARFLinker/Parallel DWARFLinkerImpl.cpp DWARFLinkerImpl.h, llvm/test/tools/dsymutil/X86 frame-2.test frame-1.test

[DWARFLinker] Deduplicate .debug_frame CIEs across LinkContexts (#195393)

Each LinkContext held its own EmittedCIEs map, so linking the same
object twice (or two objects with identical CIEs) produced one CIE per
LinkContext instead of one shared CIE. Hoist the registry to linker
scope and split emission into three phases so contexts can emit their
frames concurrently while still sharing one deduplicated CIE pool:

1. Scan (parallel, during link). scanFrameData() records the unique CIEs
referenced by retained FDEs, in first-reference order, into
FrameScanResult::CIEs. scanAndUnloadInput() chains the scan in front of
the existing input-unload so the DWARFContext can be released before the
post-link emit pass.

2. Merge (serial, after link completes). registerCIEs() walks each
context's scanned CIEs in ObjectContexts order and try_emplaces them
into the linker-wide CIERegistry. The first LinkContext to reference a
CIE becomes its owner and reserves a local offset in its own
.debug_frame section; later contexts only learn the owner's section and

    [14 lines not shown]
DeltaFile
+140-61llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp
+69-2llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h
+0-46llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/frame-2.test
+0-36llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/frame-1.test
+3-2llvm/test/tools/dsymutil/X86/frame-2.test
+1-2llvm/test/tools/dsymutil/X86/frame-1.test
+213-1496 files

LLVM/project 50fe986mlir/include/mlir/Dialect/Vector/Transforms LoweringPatterns.h, mlir/lib/Dialect/Vector/Transforms LowerVectorContract.cpp

experimental expose vector contract lowerings to have multiple options

Signed-off-by: Eric Feng <Eric.Feng at amd.com>

add more tests and parallelarith

Signed-off-by: Eric Feng <Eric.Feng at amd.com>

Keep contract lowering filter patch focused

Reuse filter constraint naming for contract lowering policy

Rename vector contract default filter
DeltaFile
+109-51mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp
+118-0mlir/test/Dialect/Vector/vector-contract-composable-lowering.mlir
+68-0mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
+31-0mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
+326-514 files

FreeNAS/freenas 9f6d07esrc/middlewared/middlewared/alert/source update.py, src/middlewared/middlewared/plugins/update_ profile_.py

`UpdateProfiles.name` property
DeltaFile
+5-1src/middlewared/middlewared/plugins/update_/profile_.py
+1-1src/middlewared/middlewared/alert/source/update.py
+6-22 files

OpenBSD/ports MKCLqdIlang/deno Makefile

   lang/deno: Add LIB_DEPENDS / WANTLIB for textproc/oniguruma

   With 2.7.x the onig crates slipped back into deno.
   pointed out by tb@, thanks
VersionDeltaFile
1.63+6-3lang/deno/Makefile
+6-31 files

LLVM/project 588fa29llvm/lib/Transforms/Vectorize VPlanAnalysis.cpp

[VPlan] Fix cyclic phi type inference in early outer loop plans. (#196634)

For phis check if any of the operands are VPIRValues or we already have
cached types. If so, return them.

This fixes a verification stack overflow in the VPlan outer loop path
after https://github.com/llvm/llvm-project/pull/192868.
DeltaFile
+8-1llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
+8-11 files

LLVM/project 0b60113flang/test/Driver intrinsic-module-path_bbc.f90, flang/tools/bbc bbc.cpp

Outstract bbc changes
DeltaFile
+0-12flang/test/Driver/intrinsic-module-path_bbc.f90
+0-5flang/tools/bbc/bbc.cpp
+0-172 files

LLVM/project 8e350bcflang/test/Driver intrinsic-module-path_bbc.f90 intrinsic-module-path_per_target.f90

Add bbc test
DeltaFile
+12-0flang/test/Driver/intrinsic-module-path_bbc.f90
+3-1flang/test/Driver/intrinsic-module-path_per_target.f90
+15-12 files

LLVM/project f1708dellvm/lib/Target/AMDGPU SIFrameLowering.cpp SIMachineFunctionInfo.h, llvm/test/CodeGen/AMDGPU amdgpu-spill-cfi-saved-regs.ll

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
DeltaFile
+2,998-0llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
+17-0llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+10-0llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+9-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+3,036-05 files

LLVM/project c56f481llvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c
DeltaFile
+67-67llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+30-0llvm/lib/MC/MCDwarf.cpp
+15-15llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+14-0llvm/lib/CodeGen/MachineFunction.cpp
+4-4llvm/test/CodeGen/AMDGPU/debug-frame.ll
+4-0llvm/include/llvm/CodeGen/MachineFunction.h
+134-865 files not shown
+145-9011 files

LLVM/project 4805dfcllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll gfx-callable-argument-types.ll

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+3,568-2,598llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,912-1,913llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+2,700-12llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+631-631llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+505-510llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+394-399llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+9,710-6,063108 files not shown
+14,825-9,527114 files

LLVM/project c53cc7cllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll

[AMDGPU] Use register pair for PC spill

Change-Id: Ibedeef926f7ff235a06de65a83087c151f66a416
DeltaFile
+4,331-4,331llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,742-1,740llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+1,562-1,560llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,462-1,460llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+1,238-1,236llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+1,030-1,028llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+11,365-11,35589 files not shown
+18,153-18,04495 files

LLVM/project fc8bebbllvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir

[AMDGPU] Implement CFI for non-kernel functions

This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.

Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+2,136-0llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
+1,671-1llvm/test/CodeGen/AMDGPU/debug-frame.ll
+16,779-16993 files not shown
+22,889-1,13299 files

LLVM/project 3aac4eallvm/lib/Target/AMDGPU SIFrameLowering.cpp, llvm/test/CodeGen/AMDGPU debug-frame.ll eliminate-frame-index-v-add-u32.mir

[AMDGPU] Emit entry function Dwarf CFI

Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.

Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+1,405-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+204-12llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
+134-6llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
+114-10llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
+42-5llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+34-0llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
+1,933-3322 files not shown
+2,044-5028 files