13,342,987 commits found in 11 milliseconds
LLVM /project 91da2c8 — llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Transforms/InstCombine/AArch64 sve-intrinsic-to-svbool-binops.ll [LLVM][InstCombine] Enable simplification of SVE predicate binops. (#211016)
Enable existing SVE binop simplification code paths for predicate
vectors. I've extended tryCombineFromSVBoolBinOp to maintain an existing
tranformation for the case where AND operations are replaced by their
SELECT equivalent. LLVM /project ca6f270 — llvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp AArch64SVEInstrInfo.td, llvm/test/CodeGen/AArch64 imm-splat-ops.ll bf16-v8-instructions.ll [LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to include min/max operations. (#211228) LLVM /project bad66b4 — bolt/test/X86 mixed-dwarf32-dwarf64-str-offsets.test mixed-dwarf32-dwarf64-rnglists.test, llvm/test/CodeGen/AArch64 aarch64-no-mov-spill-chain.ll Rebase
Created using spr 1.3.6-beta.1
LLVM /project 4ce57c1 — bolt/test/X86 mixed-dwarf32-dwarf64-str-offsets.test mixed-dwarf32-dwarf64-rnglists.test, llvm/test/CodeGen/AArch64 aarch64-no-mov-spill-chain.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
LLVM /project 7b0c475 — llvm/test/CodeGen/AMDGPU flat-atomicrmw-fmin.ll flat-atomicrmw-fmax.ll Reword comment and override getRawRegPressureSetLimit in SIRegisterInfo
Created using spr 1.3.6-beta.1
Delta File +3,784 -3,772 llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll +3,784 -3,772 llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll +3,445 -3,475 llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll +3,445 -3,475 llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll +3,371 -3,313 llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll +2,673 -2,602 llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll +20,502 -20,409 52 files not shown +46,590 -45,526 58 files
OPNSense /core 2e6ffc6 — . plist, src/opnsense/service/conf/actions.d actions_plugins.conf actions_dns.conf system: configure dhcp via backend, move dns over #9352
system: move backup restore to /var/lib/php/tmp #9352
OPNSense /core 56e2655 — src/opnsense/service/conf/actions.d actions_dns.conf, src/www system_advanced_admin.php system_general.php system: add dns reconfigure #9352
OpenBSD /ports hsGY6Bz — mail/mozilla-thunderbird distinfo Makefile, mail/thunderbird-i18n distinfo Makefile.inc mail/mozilla-thunderbird: update to 153.0.1esr
see https://www.thunderbird.net/en-US/thunderbird/153.0.1esr/releasenotes/
system: switch timezone and hostname restarts #9352
yt-dlp: Update to 2026.6.9
system: replace kernel/powerd restart now that it works #9352
rwhich: add a global configuration and a per repo configuration
This helps fine grained control on the usage of the rwhich database
OpenBSD /ports 7Oy5WsN — www/librewolf Makefile distinfo, www/librewolf/patches patch-lw_policies_json patch-toolkit_components_downloads_DownloadIntegration_sys_mjs www/librewolf: update to 153.0-3, from yaydn
yt-dlp: Update to 2026.7.4
LLVM /project 383e266 — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize iv_outside_user.ll [LV] Use SCEV to compute final value of complex induction variables (#195059)
Extend optimizeInductionLiveOutUsers to handle complex induction
variable by using SCEV analysis. When an induction variable forms an
affine AddRec {Start,+,Step}, compute the final value as Start +
(ResumeTripCount - 1) * Step using VPDerivedIVRecipe.
This patch eliminates unnecessary vector widening for induction
variables only used outside the loop.
Pre-commit test #195055 system: change approach due to MVC entanglement
Frist approach did not work. Make it a bit more obvious.
LLVM /project 999c620 — llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp SPIRVNonSemanticDebugHandler.h, llvm/test/CodeGen/SPIRV/debug-info debug-function.ll debug-function-namespace-scope.ll Implement support for NSDI DebugFunction opcode.
telephony/baresip: update to 4.10.0.
see https://github.com/baresip/baresip/releases/tag/v4.10.0
and https://github.com/baresip/re/releases/tag/v4.10.0
libcreg may pick up libbfio at configure stage and break build when
uninstalled at that time. explicitly add to LIB_DEPENDS
pointed out by naddy@
MVC: UI: base_tabs_header fix tab activation
graphics/lerc: update to 4.2.0.
see https://raw.githubusercontent.com/Esri/lerc/refs/tags/v4.2.0/CHANGELOG.md
compression: respect compression_level for the file db and the metadata
[CIR][RISCV] Add new builtins (#211555)
Leave them NYI now. LLVM /project 3ba240e — llvm/test/CodeGen/AMDGPU maximumnum.ll minimumnum.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir Update to latest spec
Created using spr 1.3.6-beta.1
Delta File +9,414 -9,234 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir +7,009 -6,937 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir +13,068 -0 llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll +5,819 -5,824 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir +5,588 -5,406 llvm/test/CodeGen/AMDGPU/maximumnum.ll +5,467 -5,272 llvm/test/CodeGen/AMDGPU/minimumnum.ll +46,365 -32,673 11,977 files not shown +468,628 -322,998 11,983 files
LLVM /project a753004 — llvm/test/CodeGen/AMDGPU maximumnum.ll minimumnum.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +9,414 -9,234 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir +7,009 -6,937 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir +13,068 -0 llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll +5,819 -5,824 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir +5,588 -5,406 llvm/test/CodeGen/AMDGPU/maximumnum.ll +5,467 -5,272 llvm/test/CodeGen/AMDGPU/minimumnum.ll +46,365 -32,673 11,974 files not shown +467,658 -321,816 11,980 files
LLVM /project aea6a24 — llvm/test/CodeGen/AMDGPU maximumnum.ll minimumnum.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir Update to latest spec
Created using spr 1.3.6-beta.1
Delta File +9,414 -9,234 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir +7,009 -6,937 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir +13,068 -0 llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll +5,819 -5,824 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir +5,588 -5,406 llvm/test/CodeGen/AMDGPU/maximumnum.ll +5,467 -5,272 llvm/test/CodeGen/AMDGPU/minimumnum.ll +46,365 -32,673 11,974 files not shown +467,658 -321,816 11,980 files
[AArch64] Mark SP-only register classes as non-allocatable (#211549)
Reserved registers are not allocatable and since these are singleton
classes, they should be marked as such.
Assisted-by: codex FIX some OMPT tests that fail on RISC-V (#156914)
There is a known issue with these tests (see
https://github.com/llvm/llvm-project/issues/35661 ).
It looks that the behaviour is very architecture specific and it was
somehow solved for aarch64 but no mention to riscv64. OPNSense /core 86d6fd2 — src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api DNatController.php, src/opnsense/mvc/app/models/OPNsense/Firewall/FieldTypes SourceNatRuleField.php FilterRuleField.php Firewall: Rules and NAT: Group invalid rules to the end of the ruleset. These rules are skipped by PF processing because they do not have a valid interface. (#10550)
---------
Co-authored-by: Stephan de Wit <stephan.de.wit at deciso.com>