LLVM/project af6b259llvm/include/llvm/MC MCGOFFStreamer.h, llvm/lib/MC MCGOFFStreamer.cpp

[SystemZ][z/OS] Implement emitCommonSymbol in MCGOFFStreamer (#210179)

Common globals were not emitted in GOFF object files due to a missing
emitCommonSymbol implementation. This adds the implementation to emit
the required SD/ED/PR ESD records in the GOFF object file.

(cherry picked from commit 705d0ec6115cef3232eafe6221f42f78e7b884e8)
DeltaFile
+29-0llvm/lib/MC/MCGOFFStreamer.cpp
+28-0llvm/test/CodeGen/SystemZ/zos-common-global.ll
+1-1llvm/include/llvm/MC/MCGOFFStreamer.h
+58-13 files

LLVM/project d62f721llvm/lib/DTLTO CMakeLists.txt

[CMake] Added missing LLVM_PTHREAD_LIB dependency. (#211041)

Required after #209423.

(cherry picked from commit 4f5675a0500f9ccc60dcbabb57e1c4dc88c40a84)
DeltaFile
+3-0llvm/lib/DTLTO/CMakeLists.txt
+3-01 files

LLVM/project 9ecb67blld/COFF SymbolTable.cpp LTO.cpp, lld/ELF Driver.cpp

[DTLTO] Overlap temporary file removal (#209423)

Deleting the temporary files produced by the DTLTO pipeline can be
expensive on Windows hosts. For a Clang link (Debug build with
sanitizers and instrumentation) using an optimized toolchain (PGO
non-LTO, llvmorg-22.1.0) on a Windows 11 Pro (Build 26200), AMD Family
25 @ ~4.5 GHz, 16 cores/32 threads, 64 GB RAM machine, the mean duration
of the "Remove DTLTO temporary files" time trace scope was 1267.789 ms
(measured over 10 runs).

This patch performs the deletions on a background thread, allowing them
to overlap with the tail of the link to hide this cost.

This is a re-implementation of the asynchronous cleanup idea from
https://github.com/llvm/llvm-project/pull/186988, which had to be
reverted in https://github.com/llvm/llvm-project/pull/189043 because
cleanup was not guaranteed to complete before LLD invoked
timeTraceProfilerCleanup(). In certain cases timeTraceProfilerCleanup()
was called before temporary file deletion had completed in LLD, which

    [11 lines not shown]
DeltaFile
+47-15llvm/lib/DTLTO/DTLTO.cpp
+23-1llvm/include/llvm/DTLTO/DTLTO.h
+9-0lld/ELF/Driver.cpp
+8-0llvm/include/llvm/LTO/LTO.h
+5-0lld/COFF/SymbolTable.cpp
+5-0lld/COFF/LTO.cpp
+97-167 files not shown
+111-1613 files

LLVM/project 829c8e9llvm/include/llvm/CodeGen TargetRegisterInfo.h, llvm/lib/CodeGen InlineSpiller.cpp

Fix merge conflicts while rebasing on main.
DeltaFile
+0-5llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+0-5llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+0-4llvm/lib/CodeGen/InlineSpiller.cpp
+0-3llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+0-174 files

FreeBSD/ports cbeb1beMk/Uses npm.mk

Mk/Uses/npm.mk: Quote TMPDIR and WRKDIR in shell comparisons

When TMPDIR is unset, the generated shell command becomes:
    if [ != ${WRKDIR} ]; then
and /bin/sh reports:
    [: !=: unexpected operator

Quoting both variables fixes the issue.

PR:             297181
Reported by:    Shin-ichi Nagamura <core at zsc.jp>
DeltaFile
+2-2Mk/Uses/npm.mk
+2-21 files

LLVM/project 3e58eadllvm/include/llvm/ProfileData SampleProfReader.h, llvm/lib/Transforms/IPO SampleProfileMatcher.cpp SampleProfile.cpp

Revert "[ProfileData] Implement contains in SampleProfileNameTable (NFC) (#21…"

This reverts commit 86fb40ddfa3c7cd5c32d758f4b1709d01028a7db.
DeltaFile
+18-65llvm/include/llvm/ProfileData/SampleProfReader.h
+25-5llvm/lib/Transforms/IPO/SampleProfile.cpp
+0-11llvm/unittests/ProfileData/SampleProfTest.cpp
+2-1llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
+45-824 files

LLVM/project 55418a5llvm/include/llvm/Target GenericOpcodes.td, llvm/test/CodeGen/AMDGPU flat-saddr-atomics.ll

GlobalISel: Don't use GISelMatchGenericTypes for floating point opcodes (#212814)

With GISelMatchGenericTypes, AMDGPU had the same input pattern for
G_ATOMICRMW_FADD that checks for v2s16, so the one that is first
in the tablegen table always fires (it was v2f16 in this case).
Should explicitly check for v2f16/v2bf16.
DeltaFile
+41-35llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
+41-35llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
+20-40llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+14-8llvm/include/llvm/Target/GenericOpcodes.td
+116-1184 files

LLVM/project ed0b5c0llvm/lib/Transforms/Scalar LoopIdiomRecognize.cpp, llvm/test/Transforms/LoopIdiom cyclic-redundancy-check-memoryssa.ll

[LoopIdiom] Update MemorySSA when optimizing CRC with lookup table (#213054)

Although the lookup table optimization of CRC loops inserts a `load`
instruction, MemorySSA is not properly updated, and is oblivious to the
new memory access. Insert a memory use immediately after creating the
`load` instruction, and verify MemorySSA at the end of the optimization
if applicable.
DeltaFile
+30-0llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check-memoryssa.ll
+11-1llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
+41-12 files

LLVM/project 2bd28bdllvm/test/CodeGen/X86 fptosi-sat-scalar-f16.ll fptosi-sat-scalar.ll, llvm/test/Transforms/LoopVectorize interleaved-accesses.ll float-induction.ll

Merge branch 'main' into users/arsenm/amdgpu/cvt-sr-pk-bf16-distinct-feature
DeltaFile
+793-710llvm/test/Transforms/LoopVectorize/induction.ll
+112-1,272llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
+1,298-0llvm/test/CodeGen/X86/fptosi-sat-scalar-f16.ll
+544-511llvm/test/Transforms/LoopVectorize/float-induction.ll
+298-217mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+244-237llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
+3,289-2,947101 files not shown
+5,526-4,727107 files

FreeBSD/ports 40f76efaudio/maolan Makefile Makefile.crates

audio/maolan: Update to 0.2.4

Changelog: https://github.com/maolan/maolan/releases/tag/0.2.2
           https://github.com/maolan/maolan/releases/tag/0.2.3
           https://github.com/maolan/maolan/releases/tag/0.2.4

PR:             296653
Reported by:    Goran Mekić <meka at sys.it.com> (maintainer)
Reviewed by:    fgorter <fgorter at gmail.com>
DeltaFile
+461-433audio/maolan/distinfo
+229-215audio/maolan/Makefile.crates
+7-15audio/maolan/Makefile
+697-6633 files

LLVM/project 1a848f4llvm/test/CodeGen/AMDGPU identical-subrange-spill-infloop.ll skip-partial-reload-for-16bit-regaccess.mir

[InlineSpiller][AMDGPU] Implement subreg reload during RA spill

Currently, when a virtual register is partially used, the
entire tuple is restored from the spilled location, even if
only a subset of its sub-registers is needed. This patch
introduces support for partial reloads by analyzing actual
register usage and restoring only the required sub-registers.
This improvement enhances register allocation efficiency,
particularly for cases involving tuple virtual registers.
For AMDGPU, this change brings considerable improvements
in workloads that involve matrix operations, large vectors,
and complex control flows.
DeltaFile
+5,197-5,955llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+92-98llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
+82-103llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+59-97llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+35-56llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+91-0llvm/test/CodeGen/AMDGPU/skip-partial-reload-for-16bit-regaccess.mir
+5,556-6,30921 files not shown
+5,865-6,54927 files

LLVM/project 841b269llvm/test/CodeGen/AMDGPU regpressure-mitigation-with-subreg-reload.mir

compacted the virt-reg numbers
DeltaFile
+14-14llvm/test/CodeGen/AMDGPU/regpressure-mitigation-with-subreg-reload.mir
+14-141 files

LLVM/project 788b0d3llvm/test/CodeGen/AMDGPU regpressure-mitigation-with-subreg-reload.mir

[AMDGPU] Test precommit for subreg reload

This test currently fails due to insufficient
registers during allocation. Once the subreg
reload is implemented, it will begin to pass
as the partial reload help mitigate register
pressure.
DeltaFile
+37-0llvm/test/CodeGen/AMDGPU/regpressure-mitigation-with-subreg-reload.mir
+37-01 files

FreeBSD/ports 0a56f0ddeskutils/lumina-pdf Makefile, graphics/gowall Makefile

*/*: Bump PORTREVISION

Bump PORTREVISIONs because of mupdf update.
DeltaFile
+1-1print/sioyek/Makefile
+1-1graphics/gowall/Makefile
+1-1deskutils/lumina-pdf/Makefile
+3-33 files

LLVM/project 5808b2dllvm/lib/Target/SPIRV SPIRVISelLowering.cpp, llvm/test/CodeGen/SPIRV atomicrmw-uinc-udec-wrap.ll

[SPIR-V] Expand atomicrmw nand through compare-exchange (#213217)
DeltaFile
+20-0llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
+1-0llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+21-02 files

LLVM/project bb5f7a2llvm/include/llvm/CodeGen LiveRangeEdit.h, llvm/lib/CodeGen LiveRangeEdit.cpp

[CodeGen] Enhance createFrom for sub-reg aware cloning

Instead of just cloning the virtual register, this
function now creates a new virtual register derived
from a subregister class of the original value.
DeltaFile
+9-1llvm/lib/CodeGen/LiveRangeEdit.cpp
+5-2llvm/include/llvm/CodeGen/LiveRangeEdit.h
+14-32 files

LLVM/project 2a5c8c9llvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp

Fix Merge conflict from rebasing.
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+1-11 files

LLVM/project 6f9c189compiler-rt/lib/ubsan ubsan_checks.inc ubsan_handlers.cpp, compiler-rt/test/cfi mfcall.cpp

[ubsan] Report specific CFI checks in UBSan summaries (#213224)

Instead of reporting generic `cfi-bad-type` in UBSan summaries for CFI
failures, report the specific CFI check kind (e.g., `cfi-vcall`,
`cfi-nvcall`, `cfi-icall`, `cfi-mfcall`, `cfi-derived-cast`,
`cfi-unrelated-cast`).

This is done by splitting CFIBadType into specific error types in
ubsan_checks.inc, and updating the handlers to report the appropriate
ErrorType based on the check kind. The suppression flag name for all of
them remains `cfi` to maintain backward compatibility.

Also replaces cfi-bad-type expectations in the existing tests.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+20-1compiler-rt/lib/ubsan/ubsan_handlers_cxx.cpp
+6-6compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
+10-2compiler-rt/lib/ubsan/ubsan_handlers.cpp
+5-5compiler-rt/test/cfi/mfcall.cpp
+6-1compiler-rt/lib/ubsan/ubsan_checks.inc
+3-3compiler-rt/test/cfi/cross-dso/icall/diag.cpp
+50-1814 files not shown
+71-3920 files

FreeBSD/src 4175949sys/dev/e1000 if_em.h if_em.c

e1000: restrict conventional PCI DMA to 32 bits

Some conventional PCI e1000 configurations hang when given DMA
addresses above 4 GB, particularly on systems using AMD
HyperTransport-to-PCI bridges.  Linux has restricted e1000 to DMA32 in
PCI mode since 2011 for the same failure class in commit
e508be174ad36b0cf9b324cd04978c2b13c21502.

Set iflib's DMA width after determining the negotiated bus type.  This
covers descriptor and packet-buffer mappings while preserving 64-bit
DMA for PCI-X and PCIe devices and providing a conditional tunable.

PR:             297064
Reported by:    Alexander Leidinger <netchild at FreeBSD.org>
Tested by:      Alexander Leidinger <netchild at FreeBSD.org>
MFC after:      1 week
DeltaFile
+21-0sys/dev/e1000/if_em.c
+1-0sys/dev/e1000/if_em.h
+22-02 files

NetBSD/pkgsrc OaYrRMedoc CHANGES-2026

   Updated www/typo3-13 to 13.4.33nb1
VersionDeltaFile
1.4868+2-1doc/CHANGES-2026
+2-11 files

FreeBSD/ports 997d22agraphics/mupdf pkg-plist Makefile

graphics/mupdf: Update to 1.28.0

Changelog: https://github.com/ArtifexSoftware/mupdf/blob/master/CHANGES
DeltaFile
+3-3graphics/mupdf/distinfo
+2-1graphics/mupdf/Makefile
+1-0graphics/mupdf/pkg-plist
+6-43 files

LLVM/project 4120b5fllvm/lib/Target/RISCV RISCVInstrInfo.td RISCVRegisterInfo.cpp, llvm/test/CodeGen/RISCV vararg.ll frame-base-addr-reuse.mir

[RISCV] Deduplicate frame base address materializations for large stack frames (#211748)

For large stack frames, `eliminateFrameIndex` materializes the frame
base with a `LUI+ADD` sequence for every frame index access. When
multiple accesses share the same 4096-aligned base, this generates
redundant `LUI+ADD` sequences that `MachineLateInstrsCleanup` cannot
eliminate because it operates on individual instructions.

Introduce `PseudoAddUpperImm` to represent the `LUI+ADD` sequence as a
single pseudo instruction during frame index elimination. This enables
`MachineLateInstrsCleanup` to CSE identical frame base computations
within a basic block. The pseudo is expanded back to `LUI+ADD` in
`RISCVPostRAExpandPseudo`.

This patch improves SPEC CPU2026 `cactus` performance by 18% on the
SpaceMit K3 processor.

  ### Example


    [18 lines not shown]
DeltaFile
+164-0llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
+0-30llvm/test/CodeGen/RISCV/vararg.ll
+28-0llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+0-16llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
+12-0llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+8-0llvm/lib/Target/RISCV/RISCVInstrInfo.td
+212-462 files not shown
+214-548 files

NetBSD/pkgsrc COTvjtRwww/typo3-13 Makefile PLIST

   Fix PLIST
   Thanks to taca@
VersionDeltaFile
1.11+39-1www/typo3-13/PLIST
1.16+2-1www/typo3-13/Makefile
+41-22 files

LLVM/project 65cd538llvm/test/Transforms/LoopVectorize reduction-inloop-uf4.ll reduction-inloop-cond.ll

[LV][NFC] Remove almost all remaining instcombine passes in RUN lines (#213067)
DeltaFile
+793-710llvm/test/Transforms/LoopVectorize/induction.ll
+544-511llvm/test/Transforms/LoopVectorize/float-induction.ll
+244-237llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
+171-148llvm/test/Transforms/LoopVectorize/reduction.ll
+146-133llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
+103-102llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
+2,001-1,84123 files not shown
+2,729-2,45029 files

LLVM/project 9b734e2mlir/include/mlir/Dialect/LLVMIR BasicPtxBuilderInterface.td NVVMOps.td, mlir/lib/Dialect/LLVMIR/IR BasicPtxBuilderInterface.cpp

[mlir][NVVM] Add memory clobber support to inline_ptx and BasicPtxBui… (#212937)

PTX with memory side effects (stores, atomics, mbarrier operations with
acquire/release semantics) emitted through `nvvm.inline_ptx` lowers to
`llvm.inline_asm` with register constraints only. Without a `~{memory}`
clobber, LLVM may reorder memory accesses across the inline assembly.
There was no way to express the clobber through this op or the
`BasicPtxBuilderInterface` machinery.

This patch adds, as discussed with @grypp:
- A `hasMemoryClobber` interface method (default `false`) on
`BasicPtxBuilderOpInterface`; when it returns `true`, `PtxBuilder`
appends `~{memory}` to the constraints of the generated inline assembly,
after all register constraints and tied indices.
- An opt-in `memory_clobber` boolean attribute (default `false`) on
`nvvm.inline_ptx` exposing this. Existing behavior is unchanged unless
the attribute is set to `true`.

For example:

    [9 lines not shown]
DeltaFile
+33-0mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
+20-11mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+14-1mlir/include/mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.td
+7-0mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
+74-124 files

LLVM/project 814c0e6mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/test/Dialect/Tosa tosa-validation-version-1p1-valid.mlir ops.mlir

[mlir][tosa] Switch matmul_t output to bf16 from fp16 (#212970)

Note that this implements the TOSA specification change:
https://github.com/arm/tosa-specification/pull/67

---------

Signed-off-by: Jeremy Johnson <jeremy.johnson at arm.com>
DeltaFile
+298-217mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+4-4mlir/test/Dialect/Tosa/invalid_extension.mlir
+3-3mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+3-3mlir/test/Dialect/Tosa/ops.mlir
+308-2274 files

LLVM/project 4fbad31mlir/lib/Conversion/SPIRVToLLVM SPIRVToLLVM.cpp, mlir/test/Conversion/SPIRVToLLVM arithmetic-ops-to-llvm.mlir

[mlir][SPIR-V] Add SPIRVToLLVM conversions for FMod and SMod (#206933)
DeltaFile
+75-2mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+54-0mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
+129-22 files

LLVM/project 1e7fa4bcompiler-rt/lib/ubsan ubsan_checks.inc ubsan_handlers.cpp, compiler-rt/test/cfi mfcall.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+20-1compiler-rt/lib/ubsan/ubsan_handlers_cxx.cpp
+6-6compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
+10-2compiler-rt/lib/ubsan/ubsan_handlers.cpp
+5-5compiler-rt/test/cfi/mfcall.cpp
+6-1compiler-rt/lib/ubsan/ubsan_checks.inc
+3-3compiler-rt/test/cfi/cross-dso/icall/diag.cpp
+50-1814 files not shown
+71-3920 files

LLVM/project df81098llvm/test/tools/llvm-profgen/X86 first-loadable-address.test, llvm/tools/llvm-profgen ProfiledBinary.cpp

[llvm-profgen] Preserve zero-valued first PT_LOAD address (#212258)

FirstLoadableAddress was initialized with if (!FirstLoadableAddress), so
a valid first PT_LOAD at vaddr 0 was treated as unset and overwritten by
a later segment. Track whether the first loadable segment has been seen
instead.

Assisted by GPT-5
DeltaFile
+59-0llvm/test/tools/llvm-profgen/X86/first-loadable-address.test
+4-1llvm/tools/llvm-profgen/ProfiledBinary.cpp
+63-12 files

LLVM/project 2b4f6c4clang/test/CodeGenOpenCL builtins-amdgcn-gfx13.cl, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: Add missing mqsad-pk-insts to gfx13 frontend feature map (#213124)

fillAMDGCNFeatureMap omitted mqsad-pk-insts for gfx1310/gfx13-generic,
so clang wrongly rejected __builtin_amdgcn_mqsad_pk_u16_u8 on those 
targets even though the backend enables the feature. Add it to the gfx13 case.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+23-0clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
+14-7llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
+1-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+38-73 files