LLVM/project 22d90e4clang/lib/Basic Cuda.cpp, llvm/include/llvm/TargetParser NVPTXTargetParser.h NVPTXTargetParser.def

NVPTX: Add target names in TargetParser

Track the canonical sm name and other target information.
This will eventually be used to reduce the pain of maintaining
OffloadArch in clang; all of the dijoint targets share an
enum which makes target specific covered switches annoying.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+24-156clang/lib/Basic/Cuda.cpp
+73-0llvm/lib/TargetParser/NVPTXTargetParser.cpp
+72-0llvm/unittests/TargetParser/NVPTXTargetParserTest.cpp
+71-0llvm/include/llvm/TargetParser/NVPTXTargetParser.def
+69-0llvm/include/llvm/TargetParser/NVPTXTargetParser.h
+1-0llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
+310-1563 files not shown
+313-1569 files

LLVM/project 9c9e12cllvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIProgramInfo.cpp

[AMDGPU] Fix typos SGRP and VGRP. NFC. (#212732)
DeltaFile
+4-4llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt
+4-4llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
+3-3llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
+2-2llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt
+1-1llvm/docs/AMDGPUUsage.rst
+14-145 files

LLVM/project 3757c5dllvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-trunc.ll clmul-fixed.ll, llvm/test/CodeGen/AArch64/GlobalISel split-wide-shifts-multiway.ll

[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)

FIXED_REGS is not used for register allocation, but since it overlaps
the GPR classes via FP and SP, TableGen merges VG and FFR into the GPR
pressure set, giving it a static limit of 35.

The underlying GPR32all class has 33 registers: W0-W30, WZR, and WSP.
WZR and WSP are always reserved, leaving up to 31 allocatable registers
depending on whether W29 (FP) and W30 (LR) are reserved.

Marking FIXED_REGS non-allocatable removes VG and FFR from the pressure
set, reducing its static limit from 35 to 33 and its dynamic limit from
33 to 31. The corrected limit changes scheduling decisions made by the
register-pressure heuristics, which explains the test churn.

Assisted-by: codex
DeltaFile
+1,148-1,123llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
+1,023-1,030llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+727-755llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+611-614llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
+606-611llvm/test/CodeGen/AArch64/clmul-fixed.ll
+453-453llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
+4,568-4,5867 files not shown
+5,328-5,34613 files

FreeBSD/ports 8980eb2lang/erlang-man Makefile distinfo

lang/erlang-man: Update to 28.5.0.4

(cherry picked from commit 3399ba82610fd34ec2c677cc46de052ea2d7fd15)
DeltaFile
+3-3lang/erlang-man/distinfo
+1-1lang/erlang-man/Makefile
+4-42 files

FreeBSD/ports 9c8d102databases/couchdb3 Makefile pkg-plist

databases/couchdb3: Bump PORTREVISION after erlang-runtime28 update

(cherry picked from commit e385acc7532215d2779564241fa984dc43f95495)
DeltaFile
+367-367databases/couchdb3/pkg-plist
+1-1databases/couchdb3/Makefile
+368-3682 files

FreeBSD/ports eef1e5clang/erlang-java Makefile distinfo

lang/erlang-java: Update to 28.5.0.4

(cherry picked from commit 131f496910926ea5f0aa59243108e3ecb1171a78)
DeltaFile
+3-3lang/erlang-java/distinfo
+1-1lang/erlang-java/Makefile
+4-42 files

FreeBSD/ports 94c8be8lang/erlang-wx Makefile distinfo

lang/erlang-wx: Update to 28.5.0.4

(cherry picked from commit f2a23d43214b60ef69c069f40dfecd0da9538dd7)
DeltaFile
+3-3lang/erlang-wx/distinfo
+1-1lang/erlang-wx/Makefile
+4-42 files

FreeBSD/ports 6e5e592lang/erlang-doc Makefile distinfo

lang/erlang-doc: Update to 28.5.0.4

(cherry picked from commit 8aad612cb771e02cfbc4b519163cf3f31c4e3489)
DeltaFile
+3-3lang/erlang-doc/distinfo
+1-1lang/erlang-doc/Makefile
+4-42 files

FreeBSD/ports 914d712lang/erlang Makefile distinfo

lang/erlang: Update to 28.5.0.4

(cherry picked from commit a2553a6734e0c4640a135e14d7e198c51e216ed8)
DeltaFile
+3-3lang/erlang/distinfo
+1-1lang/erlang/Makefile
+4-42 files

FreeBSD/ports 281dad7lang/erlang-runtime28 Makefile distinfo

lang/erlang-runtime28: Update to 28.5.0.4

(cherry picked from commit 2bd35a76cc53c51b764d7bec12268ec589af2817)
DeltaFile
+3-3lang/erlang-runtime28/distinfo
+1-2lang/erlang-runtime28/Makefile
+4-52 files

FreeBSD/ports 2e1d208lang/erlang-runtime29 Makefile distinfo

lang/erlang-runtime29: Update to 29.0.4

(cherry picked from commit 52d8a78f774d062cf417fd769a061ccfaff01b44)
DeltaFile
+3-3lang/erlang-runtime29/distinfo
+1-1lang/erlang-runtime29/Makefile
+4-42 files

FreeBSD/ports a60e0b6lang/erlang-runtime27 Makefile distinfo

lang/erlang-runtime27: Update to 27.3.4.15

(cherry picked from commit 71bbe289f5f4dd2797e69ab79317f281823a7d27)
DeltaFile
+3-3lang/erlang-runtime27/distinfo
+1-2lang/erlang-runtime27/Makefile
+4-52 files

LLVM/project d036f0aclang/lib/Basic Cuda.cpp, llvm/include/llvm/TargetParser NVPTXTargetParser.h NVPTXTargetParser.def

NVPTX: Add target names in TargetParser

Track the canonical sm name and other target information.
This will eventually be used to reduce the pain of maintaining
OffloadArch in clang; all of the dijoint targets share an
enum which makes target specific covered switches annoying.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+24-156clang/lib/Basic/Cuda.cpp
+73-0llvm/lib/TargetParser/NVPTXTargetParser.cpp
+72-0llvm/unittests/TargetParser/NVPTXTargetParserTest.cpp
+71-0llvm/include/llvm/TargetParser/NVPTXTargetParser.def
+63-0llvm/include/llvm/TargetParser/NVPTXTargetParser.h
+1-0llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
+304-1563 files not shown
+307-1569 files

NetBSD/pkgsrc-wip 7845a95CodeWhale COMMIT_MSG

Correct CodeWhale version push
DeltaFile
+1-1CodeWhale/COMMIT_MSG
+1-11 files

FreeBSD/ports 1f2a806www/chromium Makefile distinfo

www/chromium: bump PORTREVISION after devel/esbuild update

Approved by:    portmgr (fixit blanket)
Fixes:          3445965ab0a71b23c9314953fb59c2aadcd63542
Differential Revision:  https://reviews.freebsd.org/D58363
DeltaFile
+3-3www/chromium/distinfo
+1-1www/chromium/Makefile
+4-42 files

LLVM/project e7db113llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/MachineVerifier/AMDGPU verify-ds-vdata-vdst-both-agpr-or-vgpr.mir

[AMDGPU] Remove redundant AGPR/VGPR register class verification (#212721)
DeltaFile
+1-14llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+0-11llvm/test/MachineVerifier/AMDGPU/verify-ds-vdata-vdst-both-agpr-or-vgpr.mir
+1-252 files

LLVM/project 462602dllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU soft-waitcnt-deletion.mir

[AMDGPU] Fix incorrect VM_VSRC simplification after async instruction (#212481)

Add ASYNC_CNT to the list of VMEM counters. The implication is that only
if all these counters are zero can we know that there are no outstanding
VMEM instructions, so VM_VSRC must be zero.
DeltaFile
+432-0llvm/test/CodeGen/AMDGPU/soft-waitcnt-deletion.mir
+1-1llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+433-12 files

LLVM/project 3120980llvm/lib/Transforms/Vectorize LoopVectorize.cpp

[LV][NFC]: Use CostCtx.CM instead of CM in precomputeCosts (#212287)
DeltaFile
+2-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+2-21 files

NetBSD/pkgsrc sJfqifochat/element-web Makefile

   chat/element-web: Store pointer to upstream bug report

   NFCI
VersionDeltaFile
1.45+5-1chat/element-web/Makefile
+5-11 files

NetBSD/src Zz59kRLdoc CHANGES-10.2

   Ticket 1315
VersionDeltaFile
1.1.2.121+8-1doc/CHANGES-10.2
+8-11 files

NetBSD/src jQahnaYsys/dev/raidframe rf_disks.c

   Pull up the following revisions(s) (requested by joe in ticket #1315):
        sys/dev/raidframe/rf_disks.c:   revision 1.96-1.97

   Use the right assertions to ensure that all IOs are suspended.
   zero indicates that IOs resume.
   PR kern/60477
VersionDeltaFile
1.93.4.3+3-3sys/dev/raidframe/rf_disks.c
+3-31 files

FreeBSD/ports a4214f1sysutils/rdfind Makefile

sysutils/rdfind: add support for xxhash

In the current form - the support for xxhash depends on whether or not
xxhash is installed in the system where the port is built. See
https://github.com/pauldreik/rdfind#development.

This commit makes (lack of) support for xxhash explicit. If the option
is enabled - the xxhash is added to dependencies and built into rdfind,
if disabled - xxhash support is disabled even if the library is present
in the system.

Reviewed by:    dtxdf
Differential Revision:  https://reviews.freebsd.org/D58398
DeltaFile
+8-0sysutils/rdfind/Makefile
+8-01 files

LLVM/project 9df6ca1llvm/lib/Target/AArch64 SVEInstrFormats.td, llvm/test/CodeGen/AArch64 sve-ptrue-coalesce.mir

[LLVM][CodeGen][SVE] Add ElementSize information to fp compare, continuous/replicating load and store instructions (#204821)

This information was originally used to implement MOVPFRX support.
However https://github.com/llvm/llvm-project/pull/204820 uses the same
information to determine which bits of an instruction's predicate
operand are used so that PTRUE instructions can be coalesced.
MOVPRFXable instructions are a subset of all predicated instructions, so
this patch extends some non-MOVPRFXable instructions with ElementSize
information.
DeltaFile
+334-1llvm/test/CodeGen/AArch64/sve-ptrue-coalesce.mir
+33-19llvm/lib/Target/AArch64/SVEInstrFormats.td
+367-202 files

LLVM/project e17d910llvm/test/MC/AMDGPU mcexpr_amd.s data.s

AMDGPU: Manually convert some MC tests to subarch triples

Many are switches from using the dummy amdgcn triple to a concrete
subarch.
DeltaFile
+7-7llvm/test/MC/AMDGPU/hsa-metadata-kernel-attrs-v3.s
+6-6llvm/test/MC/AMDGPU/hsa-metadata-kernel-args-v3.s
+3-3llvm/test/MC/AMDGPU/s_endpgm.s
+3-3llvm/test/MC/AMDGPU/hsa-metadata-kernel-code-props-v3.s
+2-2llvm/test/MC/AMDGPU/mcexpr_amd.s
+2-2llvm/test/MC/AMDGPU/data.s
+23-2328 files not shown
+55-5534 files

LLVM/project 7c20e1dllvm/include/llvm/CodeGen SelectionDAG.h, llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp DAGCombiner.cpp

DAG: Use poison in getLoad/getStore for offsets

The painful part of this is due to a few unfortunate things.

1. poison is legalized to undef
2. Non-indexed load/store encode the offset as an undef (which is
   not like a TargetConstant, and does get legalized)
3. 2 asserts in DAGCombiner expect identical load/store nodes,
   which assumes the offset will be preserved and not converted
   between poison and undef
4. The getLoad/getStore overloads are a mess, and a path was missing
   to recreate the store case with the original offset.
DeltaFile
+36-20llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+11-10llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+7-7llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+12-0llvm/include/llvm/CodeGen/SelectionDAG.h
+4-4llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
+2-2llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+72-432 files not shown
+74-458 files

LLVM/project 0cce7a0llvm/test/CodeGen/AMDGPU mixed-vmem-types.ll, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-sub.mir regbankselect-add.mir

AMDGPU/GlobalISel: Fix Vcc reg bank apply method for sgpr i1 input (#212532)

Need to clean up high bits on sgpr bool use, simlar to Sgpr32AExtBoolInReg.
G_AMDGPU_COPY_VCC_SCC assumes clean (zero) high bits in sgpr i32 input.
This should be combined away in most cases, for example if input is result
of a compare. But should stay for example for truncated input from s_load.
DeltaFile
+106-72llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
+60-20llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
+13-12llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
+14-10llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
+16-8llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
+8-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
+217-12615 files not shown
+292-15121 files

FreeBSD/ports 1baf6c3www/vaultwarden-web_vault Makefile distinfo

www/vaultwarden-web_vault: Update to 2026.6.4

PR:             297045
Reported by:     Bernard Spil
DeltaFile
+3-3www/vaultwarden-web_vault/distinfo
+1-1www/vaultwarden-web_vault/Makefile
+4-42 files

Illumos/gate f427417usr/src/cmd/powertop/common powertop.h display.c

18267 powertop: dereferencing freed memory
Reviewed by: Gordon Ross <Gordon.W.Ross at gmail.com>
Approved by: Dan McDonald <danmcd at edgecast.io>
DeltaFile
+27-19usr/src/cmd/powertop/common/suggestions.c
+19-11usr/src/cmd/powertop/common/display.c
+1-1usr/src/cmd/powertop/common/powertop.h
+47-313 files

FreeBSD/ports 091b5ebsecurity/vaultwarden Makefile Makefile.crates

security/vaultwarden: Update to 1.37.0

PR:             297045
Reported by:    Bernard Spil
DeltaFile
+383-431security/vaultwarden/distinfo
+197-214security/vaultwarden/Makefile.crates
+1-3security/vaultwarden/Makefile
+581-6483 files

LLVM/project e062a29libcxx/docs/Status Cxx20Issues.csv, libcxx/test/std/numerics/numarray/template.valarray/valarray.access const_access.pass.cpp access.pass.cpp

[libc++] Mark LWG3133 as Complete and add valarray operator[] safety tests (#208145)

This verifies that libc++ has implemented the resolution of LWG3133,
which modernizes the requirements on `T` for `std::complex<T>` and
`std::valarray<T>` in [numeric.requirements].
- No code changes were needed for `std::valarray<T>`: its `operator[]`
already indexes through a raw pointer and never relies on a
user-overloadable `operator&`, so it already conforms to the revised
wording.
- Added o`perator_hijacker`-based tests to `valarray`'s
`access.pass.cpp`/`const_access.pass.cpp`, confirming `operator[]`
doesn't rely on a user-overloadable `operator&`.
DeltaFile
+6-0libcxx/test/std/numerics/numarray/template.valarray/valarray.access/const_access.pass.cpp
+6-0libcxx/test/std/numerics/numarray/template.valarray/valarray.access/access.pass.cpp
+1-1libcxx/docs/Status/Cxx20Issues.csv
+13-13 files