AMDGPU: Clear v_cmpx source kill flags locally
clearKillFlags is potentially expensive and should be avoided. When
the v_cmp is folded into a v_cmpx at the saveexec, only kills of
registers overlapping the compare sources between the v_cmp and the
saveexec become invalid. Clear those directly when applying the fold,
instead of collecting candidate kills during matching and then
clearing every kill of the sources in the function.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[SLP]Vectorize sincos with both fields used in one tree
- Reuse the vectorized struct call for the second extractvalue
field instead of a struct gather, which rejected the tree. Do
not trim the call while it is still reused.
- Cost vector sincos as vector sin and cos calls when
ReplaceWithVeclib splits it; move the split check to VectorUtils.
Fixes #239948
Assisted-by: Cursor
Reviewers: bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/240154
Attributor: Fix light-preserved-analyses.ll with GCC-built opt
The printed RequireAnalysisPass type name depends on the host
compiler. GCC omits the defaulted AnalysisManager template argument,
so the check line failed on GCC-built bots. Match it with a regex like
the other pass manager tests.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[scudo] Modify wrapper test to handle different configs. (#240642)
If enabling only a few of the AbortOnDeallocXXX flags, the wrappers test
would fail. Therefore, seperate out the different checks so that it's
possible to only test the values that are enabled.
In addition, remove the setting of the defines for Android. Use the
build system to set any necessary flags.
[lldb] Fix ObjectFileMachO build on embedded (#241011)
The TARGET_OS_IPHONE-only ParseSymtab path bitrotted: #209926 dropped a
brace after the __IMPORT check and #190183 made the AsCString argument
mandatory.
[bazel] Port 528affb94ef8e664f04cab92758c06886e56fea9 (#241007)
This commit also add `layering_check` to package features so future
layering issues show up in CI and can be handled by the auto-fixing
Bazel bot.
[flang][acc] Issue implicit copies before optimized copyins (#240643)
Optimized copyins are appended so the remaining implicit copies are
issued first. This is done because this pass relies on alias analysis,
which takes advantage of Fortran aliasing rules: for example, dummy
arguments do not alias. However, if they did alias, then we are now
depending on the order ACCImplicitData decided to map, because a copyin
followed by a copy is not the same as a copy followed by a copyin (since
only the first data action maps, everything else updates the counter).
By issuing the copies before the copyins, we can ensure we do not break
anything even if we relied on the language rules to do the optimization.
OpenMP: Stop using TTI to pick the partial unroll factor in OMPIRBuilder
When the unrolled loop's CanonicalLoopInfo is needed by an enclosing
loop directive and no factor was given, unrollLoopPartial computed one
by constructing its own TargetMachine with default TargetOptions and a
standalone FunctionAnalysisManager, then running LoopUnrollPass's cost
model on the function while it was still being built.
This is a layering violation. Frontends should not be using codegen
optimization information to construct the original program. This will
not have a properly configured TargetTransformInfo from a pass
manager. The cost model is also not meaningful on incomplete,
unoptimized IR.
Use a factor of 2, matching what Sema's OpenMP loop transformation
uses for a partial clause without a factor. This removes the hidden
-openmp-ir-builder-unroll-threshold-factor option.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[Hexagon] Add HLX load and store memory intrinsics (#240995)
Lower the HLX temporary-load and new-value-store intrinsics to their
corresponding pseudo instructions and describe them as memory intrinsics
so that the selected nodes carry correct MachineMemOperands.
This adds:
- the isel patterns mapping int_hexagon_LX_L16b_tmp and
int_hexagon_LX_S16b_new onto LX_L16b_pseudo and LX_S16b_pseudo;
- getTgtMemIntrinsic support that infers the access type, pointer,
alignment, and memory flags from the intrinsic signature;
- lowering of the paired load/store intrinsics int_hexagon_LX_LL16b_tmp
and int_hexagon_LX_SS16b_new, splitting each pair access into two
single-vector accesses.
Marking INTRINSIC_W_CHAIN as custom to lower the paired HLX intrinsics
also routes HVX chained intrinsics through LowerHvxOperation, so a
pass-through case is added there to keep them selected by the existing
patterns.
Attributor: Only destroy the cached opcodes' instruction vectors
The FunctionInfo destructor checked all of the ~70 opcode slots of
OpcodeInstMap, but only the interesting opcodes are ever filled in.
Loop over those instead.
Instruction counts (callgrind) of attributor-light:
sqlite3 -0.02%, kimwitu++ k -0.30%, SPASS cnf -0.03%, consumer-typeset
z08 -0.01%.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[flang][OpenACC] Bind a module COMMON block named in a data clause (#239811)
A COMMON block declared in a module and named in a data clause of a
module procedure crashes lowering when the procedure does not reference
any of the block's members:
```fortran
module m
integer :: a
common /c/ a
contains
subroutine s()
!$acc enter data create(/c/)
end subroutine
end module
```
```
Assertion `detail::isPresent(Val) && "dyn_cast on a non-existent value"' failed.
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[AMDGPU] Model ordered XDL writes in expert scheduling (#218326)
Treat qualifying XDL WMMA as VA_VDST fences so expert scheduling can use
nonzero waits after out-of-order event mixes.
An XDL instruction with a destination register of 8 or more VGPRs
decrements VA_VDST after all instructions that were issued earlier.
This offers a significant benefit in compute bound kernels since we are
not required to pessimistically wait for WMMAs to write their results
when interleaving LDS.
```
VALU def r0
TRANS
VALU
TRANS
WMMA
va_vdst(1) # previously this would require va_vdst(0)
DS_LOAD use r0
```
[lldb][docs] Add GPU debugging blog post to links page (#240930)
This Meta blog post is a great resource about the GPU/accelerator
debugging support in LLDB and lldb-server.
[clang-nvlink-wrapper] Keep LTO task outputs distinct (#238883)
With `--save-temps` and multiple LTO tasks, the wrapper reuses the same
PTX and cubin names, so later tasks overwrite earlier results and
`nvlink` receives duplicate inputs. Give each task a distinct output
name, serialize creation of shared temporary-file bookkeeping, and skip
inactive task slots.
Fixes #238882
Testing:
- Full LTO two-partition and single-partition `FileCheck` regressions;
Unified ThinLTO regression for the unused task slot.
- CUDA 13.2 `ptxas` and `nvlink`: successfully linked a two-kernel,
two-partition image for `sm_90` and `sm_103a` with `--save-temps`. The
unpatched current baseline fails with duplicate definitions.
- Loaded and ran both kernels on two GH200 GPUs and one B300 GPU;
results were 111 and 222 on each device.
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Remove {ATF,PLAIN}_REQUIRE_KERNEL_MODULE macros
These macros predated the `require.kmod` (ATF) and `required_kmods`
(kyua) test metadata and are no longer needed.
Add a hint to freebsd_test_suite/macros.h about the `*FEATURE*` macros
going away soon. See [this kyua issue][kyua-issue] for more details.
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D61082
[kyua-issue]: https://github.com/freebsd/kyua/issues/346
[flang][codegen] Fix complex part designator with a non-constant index (#240550)
CoordinateOpConversion lowers a complex part access unconditionally as a
struct GEP, whose field index LLVM requires to be constant, and nothing
checks that the index operand is one. Block merging can make it
non-constant: two blocks differing only in the complex part index are
identical, so merging collapses them and passes the index as a block
argument. The conversion then emits invalid IR.
A complex is two elements of the same type laid out contiguously, so a
non-constant part index can index the element type directly, where a dynamic
index is allowed. Only an index into the struct itself has to be constant.
The constant path is unchanged.
Attributor: Don't keep a reference into the function information map (#240717)
getFunctionInfo kept a reference to the map entry while initializing the
information, which can add other functions to the map. If that grows the
map, the reference dangles and the function information is read from
freed memory.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
nvmecontrol: Range-check the format command's field values
The format command accepted any 32-bit value for -m, -p, -l and
--ses and passed it into the Format NVM command. Before
eae727676169 an out-of-range value spilled into the adjacent cdw10
fields, which usually drew an error from the controller; after it,
the value is masked to the field width, so a mistyped value is
silently accepted with a different meaning. Most seriously,
--ses 8 masked to SES=0 and performed a plain format with no erase
at all, exiting 0. A value like --ses 10 masked to a cryptographic
erase while bypassing the FNA cryptographic erase capability check,
which compares the unmasked value.
Reject values outside the ranges nvmecontrol.8 documents, which are
the values the spec defines: 0-1 for -m and -l, 0-3 for -p, and
0-2 for --ses. The checks run at option validation time, before
the device is opened, and the capability check now only ever sees
valid values.
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TableGen: Error on allocatable register classes with an empty allocation order
A register can never be allocated from a class with an empty
allocation order. This can happen when an alternative order excludes
every member, or when an inferred class inherits such an order from
its super class.
Classes with no members are exempt, since AMDGPU's VReg_1 is a verfy
hacky, intentionally empty allocatable class.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Backport security fixes from zlib 1.4
From the 9 security fixes listed in
https://github.com/madler/zlib/releases/tag/v1.4
we already have the fix for CVE-2026-85091 in 8.0.
The remaining 8 of these are cherry-picked here for userland, 6 of which
also affect the kernel. That required a bit of fiddling due to our patches
(#ifdef SMALL, size for ZFREE in the kernel).
There is an oob write of 32k and various other oob accesses, some info
leaks and a cloexec carelessness.
from tb@; looks good to deraadt@
In detail this is:
deflate.c, hunks 1 and 2:
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CI: Add AlmaLinux 10 x86-64-v2 package build
EL10 is built for x86-64-v3 CPUs, so the packages built on AlmaLinux 10
cannot be installed on its x86-64-v2 variant. Add an almalinux10-v2
job to the package workflow that builds on the x86_64_v2 cloud image,
and store its RPMs in a separate x86_64_v2 directory so they do not
collide with the regular EL10 packages.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Reviewed-by: Tony Hutter <hutter2 at llnl.gov>
Signed-off-by: FingerlessGlov3s <me at fingerlessgloves.me>
Closes #19811
