FreeNAS/freenas 15782ba — src/middlewared/middlewared/alert/source license_status.py

Fix `Your support contract expires in 0 days`
DeltaFile
+17-3src/middlewared/middlewared/alert/source/license_status.py
+17-31 files

FreeBSD/ports 8a2e817 — Mk/Uses npm.mk

Mk/Uses/npm.mk: Add support for pnpm >= 12

pnpm 12 has been rewritten in Rust and introduced an
architecture-dependent node module, which is required to be installed
separately from the main node module.

By default, the installation occurs upon the first pnpm execution and
breaks poudriere builds. So prefetch and extract the native executable
to the expected location in advance to avoid breakage.
DeltaFile
+25-0Mk/Uses/npm.mk
+25-01 files

LLVM/project 957dc60 — llvm/test/CodeGen/AMDGPU/GlobalISel global-atomic-fadd.f32-rtn.ll divergence-structurizer.ll

AMDGPU/GlobalISel: Mark SCC clobbers on control flow pseudos dead (#227636)

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+36-22llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
+22-22llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
+13-13llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
+111-976 files not shown
+152-13112 files

LLVM/project 94a6d82 — llvm/include/llvm/CodeGen TargetRegisterInfo.h, llvm/lib/CodeGen TargetRegisterInfo.cpp InlineSpiller.cpp

Refactor subreg spilling logic.

Avoiding Lanebitemask manipulations.
Moved most of generic the calculations to use TargetRegisterInfo APIs.
Added a new API to get the covering subreg index given a lanebitmask.
DeltaFile
+102-0llvm/test/CodeGen/AMDGPU/subreg-reload-tuple.mir
+28-32llvm/lib/CodeGen/InlineSpiller.cpp
+20-0llvm/lib/CodeGen/TargetRegisterInfo.cpp
+12-5llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+2-2llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+1-1llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+165-406 files

LLVM/project fa189b0 — clang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode matrix.c

[clang][bytecode] Reject matrix lvalue-to-rvalue casts in non-HLSL (#227305)

To fix test/CodeGen/AArch64/abi-classify-return-types.c.

The code path in the existing tests in
`test/SemaHLSL/Types/BuiltinMatrix/MatrixConstantExpr.hlsl` don't go
though `CheckLiteralType()`, so aren't rejected.
DeltaFile
+5-0clang/lib/AST/ByteCode/Compiler.cpp
+5-0clang/test/AST/ByteCode/matrix.c
+10-02 files

FreeBSD/ports 2e63b43 — security/vuxml/vuln 2026.xml

security/vuxml: Update latest OpenSSL vulns

after renames for 3.0 and 3.5
DeltaFile
+6-5security/vuxml/vuln/2026.xml
+6-51 files

FreeBSD/ports 2fbe836 — security/openssl Makefile, security/openssl/files extra-patch-ktls

security/openssl: Security upgrade to 3.5.9

OpenSSL 3.0 is end-of-life and has known vulnerabilities.
Upgrade port to OpenSSL 3.5 by renaming security/openssl35

Security:       0d183075-bcb5-11f1-b09d-8447094a420
MFH:            2026Q3
DeltaFile
+0-540security/openssl35/files/extra-patch-ktls
+0-285security/openssl35/pkg-plist
+124-124security/openssl/files/extra-patch-ktls
+0-203security/openssl35/Makefile
+49-25security/openssl/Makefile
+0-35security/openssl35/files/patch-Configurations_10-main.conf
+173-1,21218 files not shown
+213-1,39624 files

LLVM/project a23820b — llvm/test/CodeGen/AMDGPU regpressure-mitigation-with-subreg-reload.mir

compacted the virt-reg numbers
DeltaFile
+14-14llvm/test/CodeGen/AMDGPU/regpressure-mitigation-with-subreg-reload.mir
+14-141 files

LLVM/project e9a77f5 — llvm/test/CodeGen/AMDGPU regpressure-mitigation-with-subreg-reload.mir

[AMDGPU] Test precommit for subreg reload

This test currently fails due to insufficient
registers during allocation. Once the subreg
reload is implemented, it will begin to pass
as the partial reload help mitigate register
pressure.
DeltaFile
+37-0llvm/test/CodeGen/AMDGPU/regpressure-mitigation-with-subreg-reload.mir
+37-01 files

LLVM/project 9fe0644 — llvm/test/CodeGen/AMDGPU ra-inserted-scalar-instructions.mir identical-subrange-spill-infloop.ll

[InlineSpiller][AMDGPU] Implement subreg reload during RA spill

Currently, when a virtual register is partially used, the
entire tuple is restored from the spilled location, even if
only a subset of its sub-registers is needed. This patch
introduces support for partial reloads by analyzing actual
register usage and restoring only the required sub-registers.
This improvement enhances register allocation efficiency,
particularly for cases involving tuple virtual registers.
For AMDGPU, this change brings considerable improvements
in workloads that involve matrix operations, large vectors,
and complex control flows.
DeltaFile
+10,233-11,171llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+83-117llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+92-98llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
+35-56llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+91-0llvm/test/CodeGen/AMDGPU/skip-partial-reload-for-16bit-regaccess.mir
+38-38llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
+10,572-11,48023 files not shown
+10,834-11,67929 files

LLVM/project 8140fc2 — llvm/include/llvm/CodeGen LiveRangeEdit.h, llvm/lib/CodeGen LiveRangeEdit.cpp

pass in subregidx rather than a regclass
DeltaFile
+12-7llvm/lib/CodeGen/LiveRangeEdit.cpp
+5-5llvm/include/llvm/CodeGen/LiveRangeEdit.h
+17-122 files

FreeBSD/ports dad036b — japanese/fcitx5-hazkey Makefile

japanese/fcitx5-hazkey: Bump port revision after swift6 update (14d51afd2197)

While here, adjust swift6 compiler path.
DeltaFile
+4-4japanese/fcitx5-hazkey/Makefile
+4-41 files

FreeBSD/ports 14d51af — lang/swift6 distinfo Makefile, lang/swift6/files patch-swift_unittests_Parse_CMakeLists.txt patch-swift-log_Sources_Logging_Logging.swift

lang/swift6: lang/swift6: Update to 6.4.0

Swift 6.4 has removed the ability for bootstrapping without a
pre-built host swift compiler. So now the port requires a bootstrap
swift toolchain regardless of the build mode.

The installation paths have been changed from
${PREFIX}/swift6/{bin,include,lib,...} to
${PREFIX}/swift6/usr/local/{bin,include,lib,...} to follow the
standard Swift toolchain layout.

Release Announcement: https://www.swift.org/blog/swift-6.4-released/

Reported by:    GitHub (watch releases)
DeltaFile
+2,566-2,513lang/swift6/pkg-plist
+180-91lang/swift6/Makefile
+73-69lang/swift6/distinfo
+40-0lang/swift6/files/patch-swift-log_Sources_Logging_Locks.swift
+25-0lang/swift6/files/patch-swift-log_Sources_Logging_Logging.swift
+8-8lang/swift6/files/patch-swift_unittests_Parse_CMakeLists.txt
+2,892-2,68120 files not shown
+3,023-2,75226 files

LLVM/project 0aa5083 — mlir/lib/Target/LLVMIR/Dialect/LLVMIR CMakeLists.txt LLVMToLLVMIRTranslation.cpp, mlir/test/Target/LLVMIR llvmir.mlir

[MLIR][LLVMIR] Restore constant folding for global initializer GEPs

Before #226904, a GEP in a global initializer went through
IRBuilder::CreateGEP, and MLIR's IRBuilder<TargetFolder> folded the result
with ConstantFoldConstant. That combines nested GEPs, folds null and integer
bases, and infers inbounds and nuw when the offset stays within the global.
Building the constant expression directly skipped the folder, so the output
lost those flags.

Fold the constant again. This also applies to inrange GEPs, which used to
bypass the folder; the only visible difference there is that an inbounds
GEP with a non-negative offset now also gets nuw.

CIR's vtable, VTT and constant pointer tests check for the inferred flags
(for example CIR/CodeGen/vtt.cpp) and have failed since #226904.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+11-1mlir/test/Target/LLVMIR/llvmir.mlir
+4-0mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
+1-0mlir/lib/Target/LLVMIR/Dialect/LLVMIR/CMakeLists.txt
+16-13 files

LLVM/project 327d069 — mlir/docs Remarks.md, mlir/include/mlir/IR Remarks.h

[MLIR][Remark] Make remark reporting thread-safe and order final remarks by source position

Passes nested under the multithreaded pass manager report into the same
RemarkEngine from worker threads, but nothing in the engine or the
policies was synchronized. RemarkEmittingPolicyFinal inserted into its
map from several threads at once, and under RemarkEmittingPolicyAll the
streamer, including the LLVM remark serializer, was called from several
threads at once. ThreadSanitizer reports both races in the new unit tests.

RemarkEngine now holds a lock around every call into the policy. It is a
recursive llvm::sys::SmartMutex, the same type as the DiagnosticEngine's
lock. report() takes it, and so does a new finalizePolicy(), which the
engine destructor and mlir-opt now use instead of calling finalize() on
the policy directly. For the All policy the streamer and the diagnostic
printer also run under the lock, so custom policies and streamers need no
lock of their own.

With the race fixed, the final policy's creation order is still not
deterministic: which thread reports first depends on scheduling.

    [16 lines not shown]
DeltaFile
+197-13mlir/unittests/IR/RemarkTest.cpp
+78-14mlir/lib/IR/Remarks.cpp
+51-0mlir/test/Pass/remark-final-parallel.mlir
+29-4mlir/include/mlir/IR/Remarks.h
+26-2mlir/docs/Remarks.md
+9-8mlir/test/Pass/remark-final.mlir
+390-411 files not shown
+391-427 files

LLVM/project 0f972d1 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-trap-gfx11.mir

AMDGPU: Mark scc clobbers in the simulated trap expansion dead (#227633)

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir
+4-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+8-62 files

LLVM/project d4a422c — llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU move-load-addr-to-valu-flat.mir move-load-addr-to-valu.mir

AMDGPU: Mark SCC clobber dead when moving scalar branches to VALU (#227635)

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+10-10llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
+8-8llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
+2-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+20-193 files

NetBSD/pkgsrc UfcpwaB — doc CHANGES-2026

   doc: Updated www/chromium to 154.0.8037.57nb1
VersionDeltaFile
1.6526+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc ClX5QoV — www/chromium Makefile distinfo, www/chromium/patches patch-third__party_typescript_typescript.py patch-third__party_devtools-frontend_src_third__party_typescript_typescript.py

   chromium: fix build, set correct path for tsc
VersionDeltaFile
1.3+9-9www/chromium/patches/patch-third__party_typescript_typescript.py
1.3+9-9www/chromium/patches/patch-third__party_devtools-frontend_src_third__party_typescript_typescript.py
1.63+3-3www/chromium/distinfo
1.86+2-1www/chromium/Makefile
+23-224 files

NetBSD/pkgsrc-wip 8988b17 — whisper.cpp Makefile

whisper.cpp: switch to ffmpeg9

Does not really need git, remove from tools.
DeltaFile
+2-2whisper.cpp/Makefile
+2-21 files

FreeBSD/src 9006a6a — sys/dev/dwc dwc4_dma.h dwc4_mtl.h

dwc(4): Support a major update of Synopsys IP.

Support new versions 4.x and 5.x of Synopsys DesignWare Gigabit
Ethernet MAC, often referred to as DWC Quality-of-Service IP Core.

In particular:
- version 5_30 (0x53) that is found on stm32mp2 arm64 SoC
- version 5_40 (0x54) that is found on Spacemit K3 RISC-V RVA23 SoC

DWC Ethernet QoS introduced a new scalable multi-channel architecture
with up to eight TX/RX channels, enhanced DCB support, TCP segmentation
offload (TSO).

Thanks to manu@ for start splitting out the DMA code of the older
(dwc version 3.x) driver to separate files in 2023.  This patch is
a continuation of that work to support new core and DMA engine.

Thanks to mmel@ for initial review.  Initial support covers the same
interface capabilities as the version 3 (VLAN_MTU, HWCSUM, HWCSUM_IPV6).

    [5 lines not shown]
DeltaFile
+920-0sys/dev/dwc/dwc4_dma.c
+432-0sys/dev/dwc/dwc4_core.c
+242-0sys/dev/dwc/dwc4_reg.h
+108-24sys/dev/dwc/if_dwc.c
+124-0sys/dev/dwc/dwc4_mtl.h
+111-0sys/dev/dwc/dwc4_dma.h
+1,937-244 files not shown
+1,997-3810 files

LLVM/project 6d125c9 — clang-tools-extra/clangd/refactor/tweaks ExtractFunction.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx13.cl

Merge branch 'main' into users/arsenm/mips/gisel-call-dead-ra-tests
DeltaFile
+1,594-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exclusive.scan.ll
+912-0llvm/lib/ExecutionEngine/JITLink/ELF_mips.cpp
+413-0llvm/include/llvm/ExecutionEngine/JITLink/mips.h
+262-9clang-tools-extra/clangd/refactor/tweaks/ExtractFunction.cpp
+260-0clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
+226-0llvm/lib/ExecutionEngine/JITLink/mips.cpp
+3,667-9129 files not shown
+5,603-333135 files

LLVM/project 09a15dd — clang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode initializer_list.cpp

[clang][bytecode] Fix initializer-list edge cases (#227587)

Namely, initializer lists for primitive types and discarding the result
of an initializer list.
DeltaFile
+20-3clang/lib/AST/ByteCode/Compiler.cpp
+14-0clang/test/AST/ByteCode/initializer_list.cpp
+34-32 files

LLVM/project b62fe22 — mlir/docs Remarks.md, mlir/include/mlir/IR Remarks.h

[MLIR][Remark] Make remark reporting thread-safe and order final remarks by source position

Passes nested under the multithreaded pass manager report into the same
RemarkEngine from worker threads, but nothing in the engine or the
policies was synchronized. RemarkEmittingPolicyFinal inserted into its
map from several threads at once, and under RemarkEmittingPolicyAll the
streamer, including the LLVM remark serializer, was called from several
threads at once. ThreadSanitizer reports both races in the new unit tests.

RemarkEngine now holds a lock around every call into the policy. It is a
recursive llvm::sys::SmartMutex, the same type as the DiagnosticEngine's
lock. report() takes it, and so does a new finalizePolicy(), which the
engine destructor and mlir-opt now use instead of calling finalize() on
the policy directly. For the All policy the streamer and the diagnostic
printer also run under the lock, so custom policies and streamers need no
lock of their own.

With the race fixed, the final policy's creation order is still not
deterministic: which thread reports first depends on scheduling.

    [16 lines not shown]
DeltaFile
+184-5mlir/unittests/IR/RemarkTest.cpp
+84-10mlir/lib/IR/Remarks.cpp
+51-0mlir/test/Pass/remark-final-parallel.mlir
+33-6mlir/include/mlir/IR/Remarks.h
+31-3mlir/docs/Remarks.md
+9-8mlir/test/Pass/remark-final.mlir
+392-321 files not shown
+393-337 files

LLVM/project d58ae91 — mlir/docs Remarks.md, mlir/include/mlir/IR Remarks.h

[MLIR][Remark] Emit final-policy remarks in deterministic order

RemarkEmittingPolicyFinal stores remarks in a DenseSet whose hash covers the
location pointer and the hash seed, so finalize() emitted them in bucket
order, which depends on the build and on where things landed in memory. That
is why mlir/test/Pass/remark-final.mlir used CHECK-DAG.

The engine assigns every remark a RemarkId from a monotonic counter when it is
created, and the set already keeps the newer of two remarks with the same
identity. finalize() now sorts the drained remarks by that ID before emitting,
so remarks come out in creation order and a replaced identity takes the
position of its last report. Linked remarks still follow their parent.

Order only. The identity, DenseMapInfo<Remark> and the header are unchanged.
Only remarks handed to the policy outside the engine have no ID; the unit
tests that do so assert unordered or single results.

Assisted-by: Claude Code (Claude Fable 5.1)
DeltaFile
+20-14mlir/test/Pass/remark-final.mlir
+22-4mlir/unittests/IR/RemarkTest.cpp
+10-4mlir/lib/IR/Remarks.cpp
+2-1mlir/include/mlir/IR/Remarks.h
+2-1mlir/docs/Remarks.md
+56-245 files

FreeBSD/ports 06d4d26 — net/samba422 Makefile, net/samba422/files patch-source3_modules_vfs__freebsd.c

net/samba42[234Ø: fix on ZFS STATUS_INTERNAL_ERROR, Input/output error from vfs_freebsd.c

Replace strlcpy() to memmove() in vfs_freebsd.c.

PR:     292618
Reported by:    Dave Baukus <daveb at spectralogic.com>
Sponsored by:   Klara, Inc
DeltaFile
+12-9net/samba424/files/patch-source3_modules_vfs__freebsd.c
+12-9net/samba423/files/patch-source3_modules_vfs__freebsd.c
+12-9net/samba422/files/patch-source3_modules_vfs__freebsd.c
+1-1net/samba424/Makefile
+1-1net/samba423/Makefile
+1-1net/samba422/Makefile
+39-306 files

FreeBSD/ports ae3d4a7 — security/openssl30 Makefile pkg-plist, security/openssl30/files patch-crypto_async_arch_async__posix.h patch-crypto_ppccap.c

security/openssl30: Resurrect OpenSSL 3.0 port

For FreeBSD 14, expires 2028-11-30
Has known vulnerabilities, users are encouraged to move
to OpenSSL 3.5 from security/openssl
DeltaFile
+540-0security/openssl30/files/extra-patch-ktls
+275-0security/openssl30/pkg-plist
+179-0security/openssl30/Makefile
+35-0security/openssl30/files/patch-Configurations_10-main.conf
+34-0security/openssl30/files/patch-crypto_ppccap.c
+32-0security/openssl30/files/patch-crypto_async_arch_async__posix.h
+1,095-09 files not shown
+1,193-015 files

LLVM/project b63ea1c — lldb/source/Plugins/Process/Windows/Common NativeProcessWindows.cpp

[lldb][Windows] Lock the thread list when lldb-server accesses it (#226974)

`NativeProcessProtocol::Threads()` returns a `LockingAdaptedIterable`
that holds `m_threads_mutex` for the lifetime of the iteration, so
callers may hold references into `m_threads` across the loop body. On
Windows, this is only done when removing threads:

```
  // OnCreateThread
  m_threads.push_back(std::move(thread));
...
  // OnExitThread
  std::lock_guard<std::recursive_mutex> guard(m_threads_mutex);
  llvm::erase_if(m_threads, ...);
```

`m_threads` is a `std::vector<std::unique_ptr<NativeThreadProtocol>>`.
When the debug-event thread appends and the vector reallocates, every
reference held by a concurrent iteration on the main loop dangles. This

    [17 lines not shown]
DeltaFile
+55-38lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
+55-381 files

FreeBSD/ports d6f475d — comms/meshcore-cli Makefile distinfo

comms/meshcore-cli: upgrade to 1.6.4
DeltaFile
+3-3comms/meshcore-cli/distinfo
+1-1comms/meshcore-cli/Makefile
+4-42 files

OpenBSD/src zl9bFfK — sys/dev/ic qwzvar.h qwz.c, sys/dev/pci if_qwz_pci.c

   sys/qwz: unwind cold startup failures

   Based on sys/dev/ic/qwx.c,v 1.134

   Track powerup and completed core initialization so failed cold starts
   reset hardware before reclaiming initialized DMA resources. Release
   partial TX allocations and RX rings; ordinary interface down and up
   continues to retain firmware.

   OK: stsp@
VersionDeltaFile
1.66+100-26sys/dev/ic/qwz.c
1.18+4-2sys/dev/pci/if_qwz_pci.c
1.23+2-1sys/dev/ic/qwzvar.h
+106-293 files