NAS-143133 / 26.0.0 / Change client IP detection method for `test_system_general_ui_allowlist` (by themylogin) (#19689)
This test fails frequently because the IP nginx sees is not the IP
`s.getsockname()[0]` returns (there might be NAT on the way or
something).
Binding to our session IP as seen by the middleware will be more
reliable.
Original PR: https://github.com/truenas/middleware/pull/19619
Co-authored-by: themylogin <themylogin at gmail.com>
NAS-143512 / 26.0.0-RC.1 / Gate S3 auditing on appliance hardware (by sonicaj) (#19686)
This commit adds changes to decide whether the S3 service audits
requests from the hardware class rather than from the license, so it
matches the gate the kernel audit handler already uses -- both halves of
the audit trail land in the same database, so both have to answer to the
same thing. The check is renamed audit_supported since it no longer
reads a license, and the validation messages and API field descriptions
say appliance hardware instead of Enterprise license.
Original PR: https://github.com/truenas/middleware/pull/19668
Co-authored-by: sonicaj <waqarahmedjoyia at live.com>
NAS-143512 / 26.0.0 / Gate S3 auditing on appliance hardware (by sonicaj) (#19685)
This commit adds changes to decide whether the S3 service audits
requests from the hardware class rather than from the license, so it
matches the gate the kernel audit handler already uses -- both halves of
the audit trail land in the same database, so both have to answer to the
same thing. The check is renamed audit_supported since it no longer
reads a license, and the validation messages and API field descriptions
say appliance hardware instead of Enterprise license.
Original PR: https://github.com/truenas/middleware/pull/19668
Co-authored-by: sonicaj <waqarahmedjoyia at live.com>
[clang] Add missing information to AST for calling explicit object member functions (#220463)
For `E1.E2()` and `E1->E2()`,
1. A `MemberExpr` is created to represent `E1.E2` and `E1->E2`.
If overload resolution is performed, it is created using information
from a `UnresolvedMemberExpr`.
2. If `E2` is an explicit object member function, a `DeclRefExpr` is
created to represent `E2` using information from the `MemberExpr`.
This PR adds missed information to the `DeclRefExpr`.
Fixes #218829.
[flang] Enumeration Type: (PR 3/5) Intrinsics + I/O + Modules (#193235)
This PR adds intrinsics: HUGE, INT, NEXT, and PREVIOUS. It adds support
for I/O, specifically formatted I/O with explicit format. Also, it adds
module support.
It is the 3rd of 5 stacked PRs.
Assisted-by: AI
---------
Co-authored-by: Kevin Wyatt <kwyatt at hpe.com>
[InferAlignment] Do not use intrinsic align attributes as base pointer alignment (#221018)
InferAlignment propagates alignment between accesses of the same base
pointer: each load/store records how aligned the base must be, and later
accesses of that base are upgraded. Since #156057 (masked.load/store)
and
#217172 (memcpy/memmove/memset), the align parameter attribute of these
intrinsics is fed into the same table.
That is not sound. A memset with a zero length (or a masked store with
an
all-false mask) does not access memory, and its pointer argument is
allowed
to be poison, so an align attribute on it proves nothing about the
pointer.
For
```llvm
define void @test(ptr %p, i64 %n) {
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[AArch64][GlobalISel] Add support for TLS for ELF (#220236)
Mirror the existing DAGISel lowering for the TLS access sequences.
'AArch64 local-dynamic TLS cleanup pass' moved to
`AArch64PassConfig::addMachineSSAOptimization()` hook to make it running
for both instruction selection pipelines.
The generated by GlobalISel code matches DAGISel for the existing TLS
test cases.
[AMDGPU] Match the AsmParser's operand-side check and share its helper
In the upcoming PR AsmParser performs the same alignment check but differently:
it tests whether a concrete physreg, which carries no regclass, is in the
relaxed operand's regclass.
Change the verifier to work the same way, reusing
AMDGPUBaseInfo::getUnalignedEquivalentRC.
Co-Authored-By: Claude <noreply at anthropic.com>
[AMDGPU] Drop the redundant operand register-class verifier check
The generic MachineVerifier already rejects a register operand whose
class does not fit the instruction's operand class, for both virtual
(hasSuperClassEq / getMatchingSuperRegClass) and physical (contains)
registers, using the HwMode-resolved operand class. On subtargets that
require aligned VGPRs that class is the even-aligned one, so the generic
check catches a misaligned tuple on its own.
Remove SIInstrInfo::verifyInstruction's own alignment and physical
register-class checks and the now-unused getUnalignedEquivalentRC helper.
Misaligned tuples now report the generic "Illegal virtual/physical
register for instruction" instead of "Subtarget requires even aligned
vector registers"; a bad physical class reports the same instead of
"Operand has incorrect register class".
[AMDGPU] Verify VGPR tuple alignment from the operand register class
The machine verifier decided VGPR tuple alignment with isProperlyAlignedRC(),
which inspects only the register's own class. Alignment is not really a property
of the register in isolation: whether a 64-bit tuple must be even-aligned depends
on the operand it feeds, and on mixed-alignment targets the same register class
can be required to be aligned in one operand and exempt in another. Inspecting
only the register also conflates alignment with unrelated problems - a register
that is simply the wrong bank or size for the operand came out as "requires even
aligned vector registers" as well.
Make the operand's register class the source of truth instead: a register is
misaligned only when it does not satisfy the operand's class but its even-aligned
same-bank/width equivalent (SIRegisterInfo::getAlignedEquivalentRC) would. A
register that fits neither is a genuine class or bank mismatch and is left to the
illegal-register and sub-register checks. So an AGPR in a VGPR|SGPR (VS_64)
operand is now reported as an illegal register, and a wrong-size register (e.g. a
64-bit VGPR in a 128-bit MFMA source) or an invalid sub-register index is
reported by those checks alone, no longer doubled up as an "even aligned" error.
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[Offloading] Add support for compressed OffloadBinary types
Summary:
Offload binaries are used to store many heterogenous architectures into
a singel offloading blob. These lists can get very large so this PR adds
the option to compress them with the LLVM provided compression
libraries.
The implementation is quite simple, we simply compress all the buffers
after the header into a single compressed blob, then re-construct the
header. Extracting is the reverse.
The biggest change is that the offload binary now **owns** the memory,
whereas before we simply took a reference to it. This is necessary
because the decompression must create new memory compared to what the
user provided. This adds an extra copy internally, but it also
simplifies the V2 additions.
This does not wire up any clang/HIP support, just providing the
functionality.
