FreeBSD/ports 2c12a36misc/py-huggingface-hub distinfo Makefile

misc/py-huggingface-hub: Update to 1.3.2

Changelog: https://github.com/huggingface/huggingface_hub/releases/tag/v1.3.2

Reported by:    Repology
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+1-1misc/py-huggingface-hub/Makefile
+4-42 files

LLVM/project 4db68e4llvm/include/llvm/Passes MachinePassRegistry.def

[NewPM][CodeGen] Add missing non-ported pass to registry

Not sure why this did not make it in the list originally. But adding it
so that someone looking for passes to port in the registry will see it.
DeltaFile
+1-0llvm/include/llvm/Passes/MachinePassRegistry.def
+1-01 files

HardenedBSD/src 59096c6release Makefile.ec2

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main
DeltaFile
+5-1release/Makefile.ec2
+5-11 files

OpenZFS/src 8605bdfmodule/zfs vdev.c, tests/zfs-tests/cmd mmap_seek.c

FreeBSD: unbreak compilation on i386

tests/zfs-tests/cmd/mmap_seek.c: use correct printf specifier
module/zfs/vdev.c: vdev_clear(): correctly cast argument to
atomic_add_64().

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Martin Matuska <mm at FreeBSD.org>
Closes #18096
DeltaFile
+1-1module/zfs/vdev.c
+1-1tests/zfs-tests/cmd/mmap_seek.c
+2-22 files

FreeBSD/ports 9514ac9games/veloren-weekly distinfo Makefile

games/veloren-weekly: update to s20260114

Changes:        https://gitlab.com/veloren/veloren/-/compare/a5ef556b04...a95ccd4d76
(cherry picked from commit 1b873f3ec9c3f3109fa647e6de816d169ad53152)
DeltaFile
+3-3games/veloren-weekly/distinfo
+2-2games/veloren-weekly/Makefile
+5-52 files

FreeBSD/ports 4e2183egraphics/mesa-devel distinfo Makefile

graphics/mesa-devel: update to 25.3.b.3439

Changes:        https://gitlab.freedesktop.org/mesa/mesa/-/compare/5ac41be6777...6f076cdfda3
DeltaFile
+3-3graphics/mesa-devel/distinfo
+2-2graphics/mesa-devel/Makefile
+5-52 files

FreeBSD/ports 76b30a7emulators/rpcs3 distinfo Makefile

emulators/rpcs3: update to 0.0.39.18702

Changes:        https://github.com/RPCS3/rpcs3/compare/v0.0.39...d7b723cd7c
DeltaFile
+3-3emulators/rpcs3/distinfo
+2-2emulators/rpcs3/Makefile
+5-52 files

FreeBSD/ports 1b873f3games/veloren-weekly distinfo Makefile

games/veloren-weekly: update to s20260114

Changes:        https://gitlab.com/veloren/veloren/-/compare/a5ef556b04...a95ccd4d76
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+3-3games/veloren-weekly/distinfo
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+5-52 files

LLVM/project 036fa67llvm/lib/Target/AMDGPU SIRegisterInfo.td GCNSubtarget.cpp, llvm/test/CodeGen/AMDGPU regalloc-vgpr_lo128-gfx1250-t16.mir regalloc-vgpr_lo128-gfx1250.mir

[AMDGPU] Limit allocation of lo128 registers for occupancy

Parent change allows allocation of lo128 VGPRs from all 4 banks.
That may result in the undesired allocation leaving a hole of
maximum 128 registers in case if for example v0-v127 are allocated,
and v128-v255 are free.

Limit the available allocation order to the occupancy. Both hard
occupancy limits and occupancy achieved during scheduling are
considered. That is better to spill a register than to drop occupancy
in this case.
DeltaFile
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250-t16.mir
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250.mir
+53-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250-t16.mir
+30-4llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+29-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250.mir
+9-0llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+315-61 files not shown
+323-67 files

LLVM/project 9979f63llvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx11_asm_vop3_from_vopc.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge branch 'users/chapuni/mcdc/nest/nest' into users/chapuni/mcdc/nest/trunk
DeltaFile
+5,421-5,421llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+2,919-2,919llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,802-2,802llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
+2,645-2,645llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+22,912-22,912742 files not shown
+126,623-105,479748 files

LLVM/project 1b17f31llvm/test/MC/AMDGPU gfx8_asm_vop3.s gfx7_asm_vop3.s, llvm/test/MC/Disassembler/AMDGPU gfx9_vop3.txt

Merge branch 'users/chapuni/mcdc/nest/covmapdesc' into users/chapuni/mcdc/nest/nest

Conflicts:
        clang/lib/CodeGen/CodeGenPGO.cpp
DeltaFile
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+41,419-41,418llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+36,428-36,427llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+28,175-28,174llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
+22,711-22,884llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+22,276-22,275llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
+193,358-193,5265,661 files not shown
+1,449,922-1,252,6225,667 files

LLVM/project ef2ee43llvm/test/MC/AMDGPU gfx8_asm_vop3.s gfx7_asm_vop3.s, llvm/test/MC/Disassembler/AMDGPU gfx9_vop3.txt

Merge branch 'users/chapuni/mcdc/nest/bitmapaddr' into users/chapuni/mcdc/nest/covmapdesc
DeltaFile
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+41,419-41,418llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+36,428-36,427llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+28,175-28,174llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
+22,711-22,884llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+22,276-22,275llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
+193,358-193,5265,663 files not shown
+1,450,232-1,252,8205,669 files

LLVM/project a837107llvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx10_asm_vop1.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge branch 'users/chapuni/mcdc/nest/covgen' into users/chapuni/mcdc/nest/bitmapaddr
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+4,672-4,671llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+34,743-34,7392,431 files not shown
+225,579-160,7002,437 files

LLVM/project 11efca0llvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx11_asm_vop3_from_vopc.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge branch 'main' into users/chapuni/mcdc/nest/covgen
DeltaFile
+5,421-5,421llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+2,919-2,919llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,802-2,802llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
+2,645-2,645llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+22,912-22,912747 files not shown
+126,682-105,505753 files

LLVM/project a7f489bllvm/lib/Target/AMDGPU SIRegisterInfo.td GCNSubtarget.h, llvm/test/CodeGen/AMDGPU regalloc-vgpr_lo128-gfx1250.mir regalloc-vgpr_lo128-gfx1250-t16.mir

[AMDGPU] Limit allocation of lo128 registers for occupancy

Parent change allows allocation of lo128 VGPRs from all 4 banks.
That may result in the undesired allocation leaving a hole of
maximum 128 registers in case if for example v0-v127 are allocated,
and v128-v255 are free.

Limit the available allocation order to the occupancy. Both hard
occupancy limits and occupancy achieved during scheduling are
considered. That is better to spill a register than to drop occupancy
in this case.
DeltaFile
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250.mir
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250-t16.mir
+53-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250-t16.mir
+30-4llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+29-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250.mir
+8-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+314-61 files not shown
+321-67 files

LLVM/project 663647fcross-project-tests/dtlto multimodule.test, llvm/include/llvm/LTO LTO.h

[DTLTO] Fix handling of multi-module bitcode inputs (#174624)

This change fixes two issues when processing multi-module bitcode files
in DTLTO:

1. The DTLTO archive handling code incorrectly uses
getSingleBitcodeModule(), which asserts when the bitcode file contains
more than one module.
2. The temporary file containing the contents of an input archive member
was not emitted for multi-module bitcode files. This was due to
incorrect logic for recording whether a bitcode input contains any
ThinLTO modules. In a typical multi-module bitcode file, the first
module is a ThinLTO module while a subsequent auxiliary module is
non-ThinLTO. When modules are processed in order, the auxiliary module
causes the entire bitcode file to be classified as non-ThinLTO, and the
archive-member emission logic then incorrectly skips it.

In addition, this patch adds a test that verifies that multi-module
bitcode files can be successfully linked with DTLTO. The test reproduces

    [2 lines not shown]
DeltaFile
+42-0cross-project-tests/dtlto/multimodule.test
+3-1llvm/lib/LTO/LTO.cpp
+2-0llvm/include/llvm/LTO/LTO.h
+1-1llvm/lib/DTLTO/DTLTO.cpp
+48-24 files

LLVM/project d7b6df7clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 avx512vldq-builtins.c avx10_2bf16-builtins.c

[CIR][X86] Add CIR codegen support for fpclass x86 builtins (#172813)

This implements the handling for x86-specific fpclass builtin functions.
DeltaFile
+173-0clang/test/CIR/CodeGenBuiltins/X86/avx512vldq-builtins.c
+72-0clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
+72-0clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c
+60-4clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+37-0clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
+36-0clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
+450-41 files not shown
+451-47 files

FreeNAS/freenas 72cf61dsrc/middlewared/middlewared/plugins network.py

whoops, forgot commit
DeltaFile
+5-3src/middlewared/middlewared/plugins/network.py
+5-31 files

LLVM/project a11feefclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp, clang/test/CIR/IR vector.cir throw.cir

[CIR] Make cir.alloca alignment mandatory (#172663)

Fixed a crash in `CIRToLLVMAllocaOpLowering` where `cir.alloca`
operations without an explicit alignment attribute caused failures.

Modified the ODS definition of `cir.alloca` to use
`ConfinedAttr<I64Attr, [IntMinValue<0>]>`. This ensures the attribute is
always present.

Added a regression test in `clang/test/CIR/Lowering/alloca.cir`.

---------

Co-authored-by: Sirui Mu <msrlancern at gmail.com>
DeltaFile
+17-17clang/test/CIR/IR/vector.cir
+13-0clang/test/CIR/Lowering/alloca.cir
+3-3clang/test/CIR/IR/throw.cir
+3-3clang/test/CIR/IR/invalid-complex.cir
+2-2clang/test/CIR/Transforms/vector-extract-fold.cir
+2-2clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+40-2710 files not shown
+53-4016 files

LLVM/project 779c05aclang/lib/CodeGen CodeGenPGO.cpp CodeGenPGO.h, clang/test/Profile c-mcdc-logicalop-ternary.c

[MC/DC] Create dedicated MCDCCondBitmapAddr for each Decision (#125411)

MCDCCondBitmapAddr is moved from `CodeGenFunction` into `MCDCState` and
created for each Decision.

In `maybeCreateMCDCCondBitmap`, Allocate bitmaps for all valid Decisions
and emit them order by ID, to prevent nondeterminism.
DeltaFile
+44-10clang/lib/CodeGen/CodeGenPGO.cpp
+10-8clang/test/Profile/c-mcdc-logicalop-ternary.c
+3-5clang/lib/CodeGen/CodeGenPGO.h
+0-3clang/lib/CodeGen/CodeGenFunction.h
+2-0clang/lib/CodeGen/MCDCState.h
+59-265 files

LLVM/project 01f7057utils/bazel MODULE.bazel.lock, utils/bazel/llvm-project-overlay/clang BUILD.bazel

Revert "Fix bazel build for d5442b8 (#176034)"

This reverts commit 43f1edf0cfcbcce7c928e0e27221a5de1fb797ba.

Fixed already by 44b691a1e9e1201034120d71de8bc5b9b3c044e6.
DeltaFile
+1-18utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+2-3utils/bazel/MODULE.bazel.lock
+3-212 files

LLVM/project a809862llvm/lib/Analysis ValueTracking.cpp, llvm/lib/IR Instruction.cpp Operator.cpp

[IR] Teach `drop/hasPoisonGeneratingAnnotations()` about `abs`, `ctlz` and `cttz` (#175941)

DeltaFile
+9-9llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll
+13-0llvm/lib/IR/Instruction.cpp
+11-0llvm/lib/IR/Operator.cpp
+2-3llvm/lib/Analysis/ValueTracking.cpp
+0-5llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+35-175 files

LLVM/project 43f1edfutils/bazel MODULE.bazel.lock, utils/bazel/llvm-project-overlay/clang BUILD.bazel

Fix bazel build for d5442b8 (#176034)

Bazel equivalent of cmakelists changes.
DeltaFile
+18-1utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+3-2utils/bazel/MODULE.bazel.lock
+21-32 files

LLVM/project 882560eclang/lib/Sema OpenCLBuiltins.td, clang/test/SemaOpenCL fdeclare-opencl-builtins.cl

[OpenCL] Add missing mipmap read_write image builtins to OpenCLBuiltins.td (#175748)

This issue was discovered while writing tests for #175120.
DeltaFile
+57-0clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl
+2-2clang/lib/Sema/OpenCLBuiltins.td
+59-22 files

FreeBSD/ports ff6db80devel/freebsd-git-devtools distinfo Makefile

devel/freebsd-git-devtools: Update to 2026-01-05 snapshot

Base commits since last update:
1c8dafe61887 - git-arc: Try to improve documentation
684c762485d3 - git-arc: Try to make patching more useful

Sponsored by:   The FreeBSD Foundation
DeltaFile
+7-7devel/freebsd-git-devtools/distinfo
+2-2devel/freebsd-git-devtools/Makefile
+9-92 files

FreeBSD/ports f9c4099dns/dnsmasq Makefile distinfo, dns/dnsmasq/files patch-src_util.c update.py

dns/dnsmasq: update to v2.92 + inotify patch

Changelog:      https://lists.thekelleys.org.uk/pipermail/dnsmasq-discuss/2026q1/018380.html

We keep the local patch to enable inotify on FreeBSD 15,
which was only merged after the release but had been in this port
already.

Make it so the pkg-message is printed on new installs and upgrades.
DeltaFile
+0-73dns/dnsmasq/files/patch-src_util.c
+52-0dns/dnsmasq/files/update.py
+5-5dns/dnsmasq/Makefile
+3-3dns/dnsmasq/distinfo
+1-1dns/dnsmasq/files/pkg-message.in
+0-0dns/dnsmasq/files/simon-kelley-keyring.asc
+61-826 files

LLVM/project eaa7516llvm/lib/Target/X86 X86ISelLowering.cpp X86InstrSSE.td, llvm/test/CodeGen/X86 clmul.ll clmul-x86.ll

[X86] Lower scalar llvm.clmul intrinsics to PCLMULQDQ (#175189) (#175216)

Add support for lowering scalar llvm.clmul intrinsics (i8/i16/i32/i64)
to the PCLMULQDQ hardware instruction on X86 targets with the PCLMUL
feature, instead of using the default software expansion.

The lowering:

- Extends smaller types to the target's native width (i64 on x86-64, i32
on i686)
- Uses SCALAR_TO_VECTOR to create vectors (v2i64 on x86-64, v4i32 with
bitcast to v2i64 on i686)
- Performs X86ISD::PCLMULQDQ with immediate 0x00
- Extracts the result and truncates back to the original type

i8/i16/i32 CLMUL is enabled on both 32-bit and 64-bit targets. i64
CLMUL/CLMULH is only enabled on 64-bit targets.

Also adds ISD::CLMULH i64 support by extracting the upper element from

    [2 lines not shown]
DeltaFile
+215-0llvm/test/CodeGen/X86/clmul.ll
+58-0llvm/lib/Target/X86/X86ISelLowering.cpp
+11-13llvm/lib/Target/X86/X86InstrSSE.td
+18-0llvm/test/CodeGen/X86/clmul-x86.ll
+4-4llvm/lib/Target/X86/X86InstrAVX512.td
+3-0llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+309-172 files not shown
+315-178 files

FreeNAS/freenas 1c5735csrc/middlewared/middlewared/plugins/account_ constants.py privilege.py, src/middlewared/middlewared/utils privilege_constants.py

NAS-139304 / 26.04 / Convert ALLOWED_BUILTIN_GIDS to frozenset (#18023)

Correcting issues with #17894
The LocalAdminGroups included non-admin groups. Split those groups into
a separate enum class.
Renamed the class to more clearly indicate they are 'builtin' groups.
Changed the ALLOWED_BUILTIN_GIDS set to a frozenset and populate it with
the values of the new enum classes.

This passes all CI tests related to 'privilege' and manual targeted
testing.
DeltaFile
+10-10src/middlewared/middlewared/plugins/account_/constants.py
+9-5src/middlewared/middlewared/utils/privilege_constants.py
+3-3src/middlewared/middlewared/plugins/account_/privilege.py
+22-183 files

FreeNAS/freenas b472932src/middlewared/middlewared/plugins dlm.py

In local_reset start any stopped lockspace on a BlockingIOError
DeltaFile
+9-1src/middlewared/middlewared/plugins/dlm.py
+9-11 files

FreeNAS/freenas ad7ac8bsrc/middlewared/middlewared/plugins/iscsi_ alua.py scst.py

Add additional lun health checks to standby_after_start

- Ensure that all expected IQNs and LUNs are present
- Ensure that SCST deems the LUN healthy to add to copy manager
DeltaFile
+43-1src/middlewared/middlewared/plugins/iscsi_/alua.py
+14-0src/middlewared/middlewared/plugins/iscsi_/scst.py
+57-12 files