[ORC] Call Perf/VTune support wrappers through Proxies (#226677)
Hold PerfSupportPlugin's start/end registration wrappers and
VTuneSupportPlugin's unregister wrapper as Proxy members, replacing
their callSPSWrapper calls. Each proxy is built in the constructor from
the address it already takes, so the constructor signatures are
unchanged. The Perf impl and VTune register wrappers are only used as
alloc-action tags and stay ExecutorAddrs.
[clang] Unique NamespaceAndPrefixStorages with a UniquingSet (NFC) (#224221)
This patch migrates NamespaceAndPrefixStorages in ASTContext from
llvm::FoldingSet to llvm::UniquingSet.
NamespaceAndPrefixStorage keys on a pair of const NamespaceBaseDecl *
and NestedNameSpecifier. Switching to UniquingSet allows us to look
up storages with a typed key, eliminating FoldingSetNodeID
serialization at lookup sites and removing
NamespaceAndPrefixStorage::Profile.
Assisted-by: Antigravity
pool_cache(9): Allocate struct pool_cache with declared alignment.
The definition of struct pool_cache has __aligned(CACHE_LINE_SIZE) on
the pc_fullgroups member, so the compiler will assume struct
pool_cache pointers are aligned as such.
As a space optimization on uniprocessor systems, we define the
variable `coherency_unit' (as part of the module ABI) to be
COHERENCY_UNIT (often 64 or 128) in MULTIPROCESSOR builds, but
to ALIGNBYTES+1 (often 4, 8, or 16) for !MULTIPROCESSOR builds where
cache line sharing isn't as much of a problem.
But this isn't safe as an optimization for allocating objects that
have statically declared (as part of their ABI) CACHE_LINE_SIZE
alignment.
PR port-evbmips/60812: UBSan: Undefined Behavior in [sys-src] member
access within misaligned address [..] for type '[..]' which requires
128 byte alignment
proc(9): Allocate struct proc with declared alignment.
The definition of struct proc includes __aligned(COHERENCY_UNIT) on
the p_auxlock member, so the compiler will assume struct proc
pointers are aligned as such.
As a space optimization on uniprocessor systems, we define the
variable `coherency_unit' (as part of the module ABI) to be
COHERENCY_UNIT (often 64 or 128) in MULTIPROCESSOR builds, but
toALIGNBYTES+1 (often 4, 8, or 16) for !MULTIPROCESSOR builds where
cache line sharing isn't as much of a problem.
But this isn't safe as an optimization for allocating objects that
have statically declared (as part of their ABI) COHERENCY_UNIT
alignment.
PR port-evbmips/60812: UBSan: Undefined Behavior in [sys-src] member
access within misaligned address [..] for type '[..]' which requires
128 byte alignment
vnode(9): Allocate vnodes with declared alignment.
The definition of struct vnode_impl includes various
__aligned(COHERENCY_UNIT), so the compiler will assume struct vnode
pointers are aligned as such.
As a space optimization on uniprocessor systems, we define the
variable `coherency_unit' (as part of the module ABI) to be
COHERENCY_UNIT (often 64 or 128) in MULTIPROCESSOR builds, but
toALIGNBYTES+1 (often 4, 8, or 16) for !MULTIPROCESSOR builds where
cache line sharing isn't as much of a problem.
But this isn't safe as an optimization for allocating objects that
have statically declared (as part of their ABI) COHERENCY_UNIT
alignment.
PR port-evbmips/60812: UBSan: Undefined Behavior in [sys-src] member
access within misaligned address [..] for type '[..]' which requires
128 byte alignment
[AMDGPU] Price scalar integer to fp casts by source width and sign
Scalar sources between a byte and 31 bits fell to the default cost of one
while the matching vector lanes were already priced, which skewed the
difference SLP weighs a bundle against. Such a source is extended before
the conversion, and what the extension takes depends on the width, on the
sign and on whether the subtarget has SDWA and 16 bit instructions.
Sources narrower than a byte are left alone, because their vector form is
not priced either.
[AMDGPU] Price narrow integer to bfloat vector casts
A vector lane of 9 to 15 or 17 to 31 bits converted to bfloat got the
generic cost, which leaves out the rounding. Such a lane is converted to
f32 first like any other narrow lane, so price it as the f32 conversion of
the same source plus the rounding. Lanes of 8 and 16 bits keep their cost.
[AMDGPU] Model the cost of the expanded integer to/from floating point casts
No instruction converts to or from a 64 bit integer, and narrow vector
lanes are converted one at a time. Price these expansions by the FP64
rate, sdwa and 16 bit instruction support, and price i33 to i63 like
i64 and bf16 like f32 plus rounding.
Assisted-by: Claude Code Opus 5
[NFC][AMDGPU] Add cost tests for narrow integer to fp casts
Covers integer sources from a byte to 31 bits converted to half, float,
bfloat and double, as vector lanes and as scalars, over the subtarget
combinations that change the expansion. The existing cast tests get the
same subtarget coverage and the cases they were missing. The costs
recorded here are the ones the model reports today.
lang/ocaml: Reduce diffs to wip
- MASTER_SITES https
- Drop MAKE_JOBS_SAFE=no, as ancient and a 24-job build worked for
me.
- Add PRINT_PLIST_AWK for ocaml-opt, with partial coverage.
- c99
[LV] Remove EpilogueLoopVectorizationInfo::EpilogueUF (NFC). (#226792)
The epilogue vector loop is always unrolled by 1: the only construction
site passes 1 and the constructor asserted it. Drop the field and use 1
directly at its users, and drop the now always 1 EpilogueUF parameter of
addMinimumVectorEpilogueIterationCheck.
Clean-up in preparation for removing/simplifying
EpilogueLoopVectorizationInfo.
CodeGen: Merge TargetLoweringObjectFile::getModuleMetadata into Initialize
getModuleMetadata had a single caller, which invoked it immediately after
Initialize. Pass the module to Initialize and fold it in.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
