LLVM/project 34e136bllvm/test/Transforms/PhaseOrdering/X86 horizontal-reduce-smax.ll horizontal-reduce-smin.ll

[PhaseOrdering][X86] Copy backend horizontal min/max reduction tests to phaseordering (#194601)

As discussed on #194473 - add middleend test coverage to ensure we're
creating vXi8/vXi16 llvm.vector.reduce calls to ensure we can lower to
PHMINPOS instructions

Also demonstrates that we're still not matching partial reduction
patterns in vectorcombine
DeltaFile
+419-0llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
+419-0llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
+419-0llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
+419-0llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
+1,676-04 files

LLVM/project c5e941dllvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx bitrev.ll bitset.ll

[LoongArch] Support VBIT{CLR,SET,REV}I patterns for non-native element sizes (#193719)

Extend vsplat_uimm_{pow2,inv_pow2} matching to allow specifying an
explicit element bit width, enabling recognition of splat patterns whose
logical element size differs from the vector's native element type.

Introduce templated selectVSplatUimm{Pow2,InvPow2} helpers with an
optional EltSize parameter, and add corresponding ComplexPattern
definitions for i8/i16/i32 element widths. This allows TableGen patterns
to match cases such as operating on v8i32/v4i64 vectors with masks
derived from smaller element sizes.

With these changes, AND/OR/XOR operations using inverse power-of-two or
power-of-two splat masks are now correctly selected to VBITCLRI,
VBITSETI, and VBITREVI instructions instead of falling back to vector
logical operations with materialized constants.
DeltaFile
+35-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+27-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+8-4llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+3-6llvm/test/CodeGen/LoongArch/lasx/bitrev.ll
+3-6llvm/test/CodeGen/LoongArch/lasx/bitset.ll
+3-6llvm/test/CodeGen/LoongArch/lasx/bitclr.ll
+79-224 files not shown
+90-4110 files

LLVM/project 378b411clang/test/CodeGen/AArch64/sve2p3-intrinsics acle_sve2p3_qshr.c acle_sve2p3_qrshr.c, clang/test/Sema/AArch64 arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c

[clang][AArch64][SVE2p3][SME2p3] Add intrinsics for v9.7a shift operations (#186087)

Add the following new clang intrinsics based on the ACLE specification
https://github.com/ARM-software/acle/pull/428 (Add alpha support for 9.7
data processing intrinsics)

Multi-vector saturating rounding shift right narrow and interleave
instructions
- SQRSHRN
- svint8_t svqrshrn_s8(svint16x2_t, uint64_t) / svint8_t
svqrshrn_n_s8_s16_x2(svint16x2_t, uint64_t)

- UQRSHRN
- svuint8_t svqrshrn_u8(svuint16x2_t, uint64_t) / svuint8_t
svqrshrn_n_u8_u16_x2(svuint16x2_t, uint64_t)

- SQRSHRUN
- svuint8_t svqrshrun_u8(svint16x2_t, uint64_t) / svuint8_t
svqrshrun_n_u8_s16_x2(svint16x2_t, uint64_t)

    [18 lines not shown]
DeltaFile
+255-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_qshr.c
+144-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_qrshr.c
+87-0clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
+66-0clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
+58-0llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-qshr.ll
+51-0clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_qshrn.cpp
+661-05 files not shown
+734-1611 files

OPNSense/core 25b8045. plist, src/opnsense/mvc/app/models/OPNsense/Base BaseModel.php

mvc: fix validation via string cast, mostly for UpdateOnlyTextField

PR: https://github.com/opnsense/plugins/pull/5404
DeltaFile
+64-0src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes/UpdateOnlyTextFieldTest.php
+27-26src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes/Field_Framework_TestCase.php
+2-2src/opnsense/mvc/app/models/OPNsense/Base/BaseModel.php
+1-0plist
+94-284 files

FreeNAS/freenas fab9f18src/middlewared/middlewared service_exception.py, src/middlewared/middlewared/api/base/handler version.py

Fix unpicklable custom exceptions across the codebase
DeltaFile
+65-17src/middlewared/middlewared/plugins/zpool/exceptions.py
+28-7src/middlewared/middlewared/plugins/zfs/exceptions.py
+8-2src/middlewared/middlewared/api/base/handler/version.py
+5-0src/middlewared/middlewared/utils/service/call.py
+5-0src/middlewared/middlewared/service_exception.py
+4-1src/middlewared/middlewared/plugins/service_/services/dbus_router.py
+115-276 files not shown
+121-2712 files

FreeBSD/ports 7e0734dsecurity/netbird distinfo Makefile

security/netbird: update to 0.70.0

Changelo: https://github.com/netbirdio/netbird/releases/tag/v0.70.0

PR:             294843
DeltaFile
+5-5security/netbird/distinfo
+1-1security/netbird/Makefile
+6-62 files

LLVM/project c28d907llvm/test/tools/llubi intr_vector_interleave.ll intr_vector_manip.ll, llvm/tools/llubi/lib Interpreter.cpp

[llubi] Implement vector reduction/manipulation intrinsics (#194345)

This PR implements vector reduction and manipulation intrinsics. 

Note that floating-point vector reduction intrinsics are not covered by
this change; they will be added in a follow-up PR after #188453 is
merged.
DeltaFile
+181-0llvm/tools/llubi/lib/Interpreter.cpp
+61-0llvm/test/tools/llubi/intr_vector_interleave.ll
+56-0llvm/test/tools/llubi/intr_vector_manip.ll
+55-0llvm/test/tools/llubi/intr_vector_reduce.ll
+17-0llvm/test/tools/llubi/intr_vector_stepvector.ll
+370-05 files

FreeBSD/ports 6558b42filesystems/amazon-efs-utils distinfo Makefile.crates

filesystems/amazon-efs-utils: Update to 3.1.0

Reported by:    portscout
Sponsored by:   Netflix
DeltaFile
+89-71filesystems/amazon-efs-utils/distinfo
+43-34filesystems/amazon-efs-utils/Makefile.crates
+1-2filesystems/amazon-efs-utils/Makefile
+133-1073 files

LLVM/project f82a74aflang/test/Lower submodule.f90 statement-function.f90

[flang][NFC] Converted five tests from old lowering to new lowering (part 51) (#194522)

Converted Lower/associate-construct.f90,
Lower/default-initialization.f90, Lower/select-type-2.f90,
Lower/statement-function.f90, and Lower/submodule.f90 from legacy
lowering (-hlfir=false) to new lowering (-emit-hlfir).
DeltaFile
+65-72flang/test/Lower/submodule.f90
+59-59flang/test/Lower/statement-function.f90
+46-33flang/test/Lower/associate-construct.f90
+30-22flang/test/Lower/default-initialization.f90
+6-5flang/test/Lower/select-type-2.f90
+206-1915 files

LLVM/project 31687bbutils/bazel/llvm-project-overlay/libc/test/src/sys/socket BUILD.bazel

[Bazel] Fixes 412d474 (#194598)

This fixes 412d474f5e1dc9a931a71cf972c5415e6a025a6f.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+3-0utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
+3-01 files

LLVM/project 90c90a4clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen CIRGenExprConstant.cpp

[CIR] Initialization of global atomic variables (#194239)

This patch adds support for initializing global atomic variables. It
does not include support for tail paddings, which will be added in later
patches.

Assisted-by: Codex / GPT-5.5
DeltaFile
+12-9clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+11-0clang/test/CIR/CodeGen/atomic.c
+1-0clang/include/clang/CIR/MissingFeatures.h
+24-93 files

FreeBSD/ports 7390911databases/cassandra5 Makefile, databases/cassandra5/files/maven build.xml

databases/cassandra5: new port Cassandra 5.0

Highly scalable distributed database

PR:     282693
DeltaFile
+2,094-0databases/cassandra5/files/maven/build.xml
+1,267-0databases/cassandra5/files/maven/.build/parent-pom-template.xml
+380-0databases/cassandra5/files/maven/.build/cassandra-deps-template.xml
+314-0databases/cassandra5/files/maven/.build/build-resolver.xml
+247-0databases/cassandra5/files/maven/.build/build-sonar.xml
+199-0databases/cassandra5/Makefile
+4,501-042 files not shown
+7,018-048 files

LLVM/project 0342d2fclang/include/clang/StaticAnalyzer/Checkers Taint.h, clang/include/clang/StaticAnalyzer/Core/PathSensitive ProgramState.h Environment.h

[NFC][analyzer] Refactor Environment to map Expr to SVal instead of Stmt to SVal (#193295)

Previously the `Environment` mapped `{Stmt *, LocationContext}` pairs to
symbolic values; but semantically it represents the values produced by
the evaluation of _expressions_, so there was no good reason to use
non-`Expr` statements in this mapping.

This commit replaces `Stmt` with `Expr` (its subclass) in this mapping
to accurately represent the actually relevant type.

This change is also propagated to methods, variables etc. that handle
the `Environment`.

There was a special case in `Environment::getSVal` that allowed looking
up a `ReturnStmt` in the `Environment` (and translated this to a lookup
of the "return value" sub-expression of the `ReturnStmt`). This commit
eliminates this and modifies the callers to explicitly look up the
sub-expression of the `ReturnStmt`.
DeltaFile
+16-46clang/lib/StaticAnalyzer/Core/Environment.cpp
+10-15clang/include/clang/StaticAnalyzer/Core/PathSensitive/ProgramState.h
+14-8clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+9-8clang/lib/StaticAnalyzer/Checkers/Taint.cpp
+5-10clang/include/clang/StaticAnalyzer/Core/PathSensitive/Environment.h
+8-7clang/include/clang/StaticAnalyzer/Checkers/Taint.h
+62-9413 files not shown
+93-12319 files

LLVM/project 14e69bdllvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIISelLowering.cpp

[AMDGPU] Make `ds_atomic_barrier` operations atomic (#194351)

Add the MMO, and document them as such in AMDGPUUsage.
DeltaFile
+29-0llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll
+26-0llvm/docs/AMDGPUUsage.rst
+1-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+56-03 files

NetBSD/pkgsrc m7wbnAweditors/vim Makefile, editors/vim-share Makefile DESCR

   Allow compilation on Cygwin
VersionDeltaFile
1.81+5-1editors/vim/Makefile
1.77+5-1editors/vim-share/Makefile
1.3+1-1editors/vim-share/DESCR
+11-33 files

LLVM/project 9b8486elibsycl/include/sycl/__impl queue.hpp, libsycl/src/detail queue_impl.cpp

fix comments

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+9-9libsycl/include/sycl/__impl/queue.hpp
+2-2libsycl/src/detail/queue_impl.cpp
+11-112 files

FreeNAS/freenas 9dc12e2src/middlewared/middlewared/plugins/truenas license.py

NAS-140813 / 26.0.0-BETA.2 / Fix license upload (by themylogin) (#18827)

Original PR: https://github.com/truenas/middleware/pull/18826

Co-authored-by: themylogin <themylogin at gmail.com>
DeltaFile
+1-1src/middlewared/middlewared/plugins/truenas/license.py
+1-11 files

FreeNAS/freenas cba3251src/middlewared/middlewared/plugins/truenas license.py

NAS-140813 / 27.0.0-BETA.1 / Fix license upload (#18826)
DeltaFile
+1-1src/middlewared/middlewared/plugins/truenas/license.py
+1-11 files

FreeNAS/freenas 78ac41esrc/middlewared/middlewared/plugins service.py

NAS-140324 / 26.0.0-BETA.2 / Emit service.query CHANGED event on service.update (by sonicaj) (#18823)

This commit adds changes so that when a service config update operation
is performed, we emit out an event which UI can listen to in order to
update it's state accordingly.

Original PR: https://github.com/truenas/middleware/pull/18822

Co-authored-by: Waqar Ahmed <waqarahmedjoyia at live.com>
DeltaFile
+1-0src/middlewared/middlewared/plugins/service.py
+1-01 files

FreeNAS/freenas 68dd51ctests/api2 test_legacy_api.py

NAS-140509 / 26.0.0-BETA.2 / fix test_legacy_api test failures (by yocalebo) (#18825)

The commit in ad71fbed02 caused this test to start failing. Fix the test
to account for the changes in that commit.

Original PR: https://github.com/truenas/middleware/pull/18620

Co-authored-by: caleb <yocalebo at gmail.com>
DeltaFile
+3-0tests/api2/test_legacy_api.py
+3-01 files

NetBSD/pkgsrc jbPdNHUdoc CHANGES-2026

   doc: Updated devel/mise to 2026.4.24
VersionDeltaFile
1.2671+2-1doc/CHANGES-2026
+2-11 files

FreeBSD/ports b9c7ff8games/kodi-addon-game.libretro Makefile distinfo, games/kodi-addon-game.libretro.fceumm distinfo

games/kodi-addon-game.libretro*,multimedia/kodi-addon*: update ports to latest kodi version

unbreaks and undeprecates games/kodi-addon-game.libretro

PR:     294761
PR:     294242
DeltaFile
+5-8games/kodi-addon-game.libretro/Makefile
+5-5games/kodi-addon-game.libretro/distinfo
+3-3games/kodi-addon-game.libretro.fceumm/distinfo
+3-3multimedia/kodi-addon-visualization.spectrum/distinfo
+3-3multimedia/kodi-addon-visualization.projectm/Makefile
+3-3multimedia/kodi-addon-visualization.projectm/distinfo
+22-2522 files not shown
+88-8528 files

NetBSD/pkgsrc N80wADLdevel/mise distinfo Makefile

   devel/mise: update to 2026.4.24

   2026.4.24 - 2026-04-27
   🚀 Features

       (ls-remote) add prereleases setting and --prerelease flag by @jdx in #9415

   🐛 Bug Fixes

       (http) retry transient HTTP failures with backoff and warn on rescue by @jdx in #9414
       (release) purge mise.en.dev CDN zone after each S3 publish by @jdx in #9416

   📚 Documentation

       prefix GitHub star count with ★ glyph by @jdx in #9417
       update intro messaging by @jdx in #9418
VersionDeltaFile
1.107+4-7devel/mise/distinfo
1.112+2-2devel/mise/Makefile
1.106+0-1devel/mise/cargo-depends.mk
+6-103 files

OPNSense/core 825836fsrc/etc/inc interfaces.inc

interfaces: small cleanups in previous as a starting point
DeltaFile
+10-19src/etc/inc/interfaces.inc
+10-191 files

OPNSense/core e16fd7fsrc/etc/inc interfaces.inc

Add HA/CARP safety for PPP link startup

Implement HA/CARP safety checks for PPP links to prevent startup if no parent interface is CARP MASTER when 'Disconnect dialup interfaces' is enabled.
DeltaFile
+33-0src/etc/inc/interfaces.inc
+33-01 files

OPNSense/core e5db8bbsrc/etc/inc interfaces.inc

Cleanup HA/CARP safety checks for PPP links patch

Proper indentation and better comment for HA/CARP safety checks for PPP links
DeltaFile
+23-23src/etc/inc/interfaces.inc
+23-231 files

OPNSense/core 9b21321src/opnsense/mvc/app/views/layout_partials base_apply_button.volt, src/opnsense/www/js opnsense_bootgrid.js opnsense_ui.js

ui: use space in apply box for the apply reminder (#10103)

It's a good way to use existing space and move the
message to where it matters most -- the apply button
itself. This also matches the legacy apply box style.
DeltaFile
+13-17src/opnsense/mvc/app/views/layout_partials/base_apply_button.volt
+1-19src/opnsense/www/js/opnsense_bootgrid.js
+2-0src/opnsense/www/js/opnsense_ui.js
+16-363 files

LLVM/project d2fe911llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/RISCV combine-is_fpclass.ll

[DAG] computeKnownFPClass - add ISD::FCOPYSIGN handling (#193672)

This PR implements `ISD::FCOPYSIGN` in
`SelectionDAG::computeKnownFPClass`, propagating class info from the
magnitude operand and sign-bit info from the sign operand.

Additionally, added RISC-V test coverage for `ISD::FCOPYSIGN`.

closes #193501
DeltaFile
+63-0llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
+8-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+71-02 files

NetBSD/pkgsrc-wip 484ba54py-pymdown-extensions PLIST Makefile

py-pymdown-extensions: update to 10.21.2.
DeltaFile
+34-5py-pymdown-extensions/PLIST
+6-6py-pymdown-extensions/Makefile
+3-3py-pymdown-extensions/distinfo
+0-2py-pymdown-extensions/TODO
+43-164 files

LLVM/project c206275llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP][NFC]Cache some results to improve compile time, NFC

Try to avoid some recalculations, if possible to cache some previous
results

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194599
DeltaFile
+62-27llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+62-271 files