LLVM/project ac47b04llvm/lib/Target/WebAssembly WebAssemblyMachineFunctionInfo.cpp

WebAssembly: Avoid using createDataLayout

Find the datalayout from the IR context instead of copying one
from the TargetMachine
DeltaFile
+3-2llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
+3-21 files

LLVM/project 21cdedbllvm/lib/Target/AMDGPU SIInstrInfo.cpp SIInstrInfo.h

More documentation

Change-Id: I65ff1a1b605796d21a52766dcf04c64bc64aaa4e
DeltaFile
+21-6llvm/lib/Target/AMDGPU/SIInstrInfo.h
+1-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+22-72 files

LLVM/project 49ece85llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU ds-latency-mode-flag.mir ds-latency-mode-branch-cost.mir

[AMDGPU] Add DSLatencyMode flag + attr to control LDS latency

Change-Id: Ia5fee7983adffdb837ba2e876a64d805263b60c3
DeltaFile
+119-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-default-scheduler.mir
+59-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+61-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
+53-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-branch-cost.mir
+29-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-flag.mir
+10-13llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+331-158 files not shown
+373-2314 files

LLVM/project 77c9d99llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.sched.group.barrier.gfx12.ll coexec-sched-flavor-classification.mir

[AMDGPU] Use instrLatency for memory HWUI cycle accounting

Change-Id: I7a9e2deb5db7638d6f735570e65d6ca988a7477f
DeltaFile
+5-5llvm/test/CodeGen/AMDGPU/coexec-mfma-interleave-gfx950.ll
+4-3llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+3-3llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+2-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
+2-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+16-155 files

LLVM/project f0b5bfbclang/lib/CIR/Dialect/Transforms FlattenCFG.cpp, clang/test/CIR/Transforms flatten-eh-spec-nyi.cir flatten-eh-spec.cir

[CIR][EH] Implement flattening for dynamic exception specification (#223780)

This change implements the CFG flattening for try operations with filter
and unexpected exception handlers. The flattening dispatches unexpected
exceptions to an operation that will later be lowered to target-specific
IR to call std::unexpected, while exceptions that match the dynamic
exception specification are routed to normal unwind handling.

Target-specific EH ABI lowering will be added in a follow-up change.

Assisted-by: Cursor / various models
DeltaFile
+136-0clang/test/CIR/Transforms/flatten-eh-spec.cir
+55-40clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
+0-37clang/test/CIR/Transforms/flatten-eh-spec-nyi.cir
+191-773 files

LLVM/project 1e522aallvm/test/Transforms/Util/DeclareRuntimeLibcalls basic.ll

Require X86 for DeclareRuntimeLibcalls test (#223832)
DeltaFile
+1-0llvm/test/Transforms/Util/DeclareRuntimeLibcalls/basic.ll
+1-01 files

LLVM/project bd695f7llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 splat-gather-subtree-keep-drop.ll splat-gather-subtree-satd.ll

[SLP]Fix splat gather subtree keep/drop to restore lost vectorization

The splat gather subtrees were kept on cost ties and resurrected by the
trimming revert without a profitability re-check, and dropping them left
the gathered loads built for them orphaned and forcing extracts. This
rejected otherwise profitable VF=2 trees. Keep subtrees only when
strictly profitable, re-evaluate them against the restored tree on a
revert, and delete the gathered loads left dead by a drop.

Fixes the remaining regressions from #220250 reported in #221717.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/223833
DeltaFile
+146-142llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-satd.ll
+87-101llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-keep-drop.ll
+63-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+296-2443 files

FreeBSD/doc dce9bc1website/archetypes/release hardware.adoc

hardware: Add the tpm driver

Discussed with: kbowling (put that in misc)
DeltaFile
+2-0website/archetypes/release/hardware.adoc
+2-01 files

LLVM/project 89ec1e3clang/lib/CodeGen CGExpr.cpp, clang/test/CodeGen attr-counted-by-or-null-for-pointers.c attr-sized-by-for-pointers.c

[CodeGen] Fix -fsanitize=array-bounds for __sized_by / _or_null pointers (#213795)

`EmitCountedByBoundsChecking()` assumed a CountAttributedType is always
a __counted_by pointer. That isn't true; there are four versions of the
attribute:

* `__counted_by`: Already handled correctly.
* `__counted_by_or_null`: Incorrectly handled.
* `__sized_by`: Incorrectly handled.
* `__sized_by_or_null`: Incorrectly handled.

In particular:

* __sized_by / __sized_by_or_null: the loaded bound is a byte count, but
the
  element index was compared against it directly, so an access was only
flagged once the index exceeded the byte count -- missing out-of-bounds
accesses for a pointee larger than one byte. Convert the loaded byte
count

    [54 lines not shown]
DeltaFile
+666-171clang/test/CodeGen/attr-sized-by-or-null-for-pointers.c
+571-86clang/test/CodeGen/attr-sized-by-for-pointers.c
+289-93clang/test/CodeGen/attr-counted-by-or-null-for-pointers.c
+75-3clang/lib/CodeGen/CGExpr.cpp
+1,601-3534 files

FreeBSD/src 32878e6sys/arm/broadcom/bcm2835 bcm2835_pwm.c

bcm2835_pwm: Fix dev.pwm.0.ratio2 register

A typo in the sysctl for RPI0 PWM channel 2 was causing it to
write to the wrong register, leaving it misconfigured if used.

PR:                     298301
MFC after:              3 days (problem reported on 14.4)
Reviewed by:            adrian
Reported by:            Attila Kover <attila.kover at guardian.co.uk>
Differential Revision:  https://reviews.freebsd.org/D59644
DeltaFile
+1-1sys/arm/broadcom/bcm2835/bcm2835_pwm.c
+1-11 files

LLVM/project 320bc62llvm/test/CodeGen/AMDGPU minimumnum.bf16.ll amdgcn.bitcast.128bit.ll

[AMDGPU] Fix for GFX11 VOPD interlock hazard (#220348)

On GFX11, a VOPD consumer whose X/Y sources share a gather class (srcA
or srcB) and the same VGPR parity can lose the destination-buffer interlock
for one of those sources. Thus, use parity as bank mask instead.
DeltaFile
+4,377-4,141llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,597-2,593llvm/test/CodeGen/AMDGPU/bf16.ll
+2,633-2,496llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,272-1,259llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+698-692llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+422-427llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+11,999-11,60888 files not shown
+15,760-15,14794 files

LLVM/project 2f85201llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/hlsl-resources unbounded-struct-arr.ll

[SPIRV] Emit RuntimeDescriptorArrayEXT capability for all unbounded array types (#222819)

Previously, the `RuntimeDescriptorArrayEXT` capability was emitted only
for image descriptor arrays. This change emits the capability for the
shader whenever resource array has `ArraySize == 0`.

This covers all supported runtime descriptor array types, including
images, structured buffers, samplers, and counter descriptor arrays.
Emitting the capability for these arrays is necessary to support dynamic
resources in SPIR-V.

Assisted by GPT-5.6 Sol.
DeltaFile
+28-0llvm/test/CodeGen/SPIRV/hlsl-resources/unbounded-struct-arr.ll
+3-1llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+31-12 files

LLVM/project cf09a76utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[Bazel] Fixes 4f4110d (#223824)

This fixes 4f4110d0be5601eb6c62e18110009cddb0573051 (#222452).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=4f4110d0be5601eb6c62e18110009cddb0573051

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

FreeBSD/ports 0b14c94. MOVED, databases Makefile

databases/py-cassandra-driver: Remove expired port

2026-09-15 databases/py-cassandra-driver: Depends on expired lang/cython0
DeltaFile
+0-45databases/py-cassandra-driver/Makefile
+0-3databases/py-cassandra-driver/pkg-descr
+0-3databases/py-cassandra-driver/distinfo
+0-1databases/Makefile
+1-0MOVED
+1-525 files

LLVM/project 1f82303libcxx/docs conf.py, lld/docs conf.py

[docs] Require MyST for Sphinx documentation builds

Fedora plans to use the man pages we build in our binary releases for
its packaging:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840/37

I'm assuming that other distributions are either going to be able to
install the necessary Python modules that we depend on (myst_parser
etc), or will be able to adopt similar strategies. Therefore, I think we
can remove this enum and associated complexity.

Assisted-by: codex
DeltaFile
+4-25utils/docs/llvm_sphinx/__init__.py
+1-1polly/docs/conf.py
+1-1llvm/docs/conf.py
+1-1lldb/docs/conf.py
+1-1lld/docs/conf.py
+1-1libcxx/docs/conf.py
+9-304 files not shown
+13-3410 files

FreeBSD/ports fa30405. MOVED, devel Makefile

devel/py-game_sdl2: Remove expired port

2026-09-15 devel/py-game_sdl2: Depends on expired lang/cython0
DeltaFile
+0-35devel/py-game_sdl2/Makefile
+0-8devel/py-game_sdl2/files/patch-setup.cfg
+0-5devel/py-game_sdl2/pkg-descr
+0-3devel/py-game_sdl2/distinfo
+0-1devel/Makefile
+1-0MOVED
+1-526 files

FreeBSD/ports 3bbe716. MOVED, databases Makefile

databases/py-pymssql: Remove expired port

2026-09-15 databases/py-pymssql: Depends on expired lang/cython0
DeltaFile
+0-31databases/py-pymssql/Makefile
+0-6databases/py-pymssql/pkg-descr
+0-3databases/py-pymssql/distinfo
+0-1databases/Makefile
+1-0MOVED
+1-415 files

FreeBSD/src 09711ccusr.sbin/bsdconfig/share sysrc.subr, usr.sbin/sysrc sysrc sysrc.subr

Remove source_rc_confs, inlined from defaults/rc.conf

Inlining source_rc_confs broke sysrc_test:A_flag

While here, switch to SPDX, bump version/copyrights, fixup comments.

Prevent common function override when bsdconfig includes new
sysrc.subr that contains inlined commons. Fix non-unique duplicate
header variable incorrectly shared between bsdconfig's sysrc.subr
include and new sysrc.subr include.

Harden RC_DEFAULTS parameter expansion from DoS-via-glob (SC2223).

Move pgm to the correct location to not override bsdconfig's pgm.

Drop _SYSRC_JAILED=1 that is no-longer needed.  Drop i18n from
jail_depend now that messages are inlined to subr.

Reported by:    siva
Fixes:  eaeb5f29bc6f sysrc: make independant from bsdconfig(8)
DeltaFile
+27-79usr.sbin/sysrc/sysrc.subr
+10-50usr.sbin/sysrc/sysrc
+6-7usr.sbin/bsdconfig/share/sysrc.subr
+43-1363 files

FreeBSD/ports 7341b73. MOVED, science Makefile

science/py-molmod: Remove expired port

2026-09-15 science/py-molmod: Depends on expired lang/cython0
DeltaFile
+0-31science/py-molmod/Makefile
+0-3science/py-molmod/distinfo
+0-2science/py-molmod/pkg-descr
+0-1science/Makefile
+1-0MOVED
+1-375 files

LLVM/project 7a75731utils/bazel/tools check_bazel_inputs.py

[bazel] Add script for finding files not in the graph (#220343)

This is useful to make sure that globs cover all files in a given
subdirectory. Right now this doesn't cover many directories because we
don't have tons of tests in bazel but if we eventually add those we can
more easily spot ones we miss with this script.

Assisted by: codex
DeltaFile
+112-0utils/bazel/tools/check_bazel_inputs.py
+112-01 files

LLVM/project 435111ellvm/test/CodeGen/AMDGPU coexec-sched-flavor-classification.mir

Precommit test change

Change-Id: Id3546e1492a335f48cf70d9b0e93afe22b31ff7a
DeltaFile
+5-5llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+5-51 files

LLVM/project 4f4110dmlir/lib/Conversion/XeVMToLLVM XeVMToLLVM.cpp, mlir/test/Conversion/XeVMToLLVM legalize_large_vector.mlir mxfp_scale_binary_hoist.mlir

[MLIR][XeVM] Hoist contiguous-slice shuffles through n-ary elementwise ops (#222452)

XeGPU expresses vector operands in their logical element type, so
per-lane compute chains can end up wider than the SPIR-V backend can
legalize as a single operand. HandleVectorExtractPattern already narrows
such chains by hoisting a contiguous-slice shufflevector upward through
unary element-wise ops (fpext/fptrunc/bitcast), merging shuffle chains,
and folding into smaller loads. But it stops at n-ary ops, so a chain
like

%0 = llvm.fdiv %a, %b : vector<32xf32> // wide, binary
%1 = llvm.shufflevector %0, %0 [0..15] : vector<32xf32> // legal 16-wide
slice

keeps a wide vector<32xf32> compute that the backend rejects.

This extends the pattern to hoist a contiguous slice through n-ary
element-wise ops as well: slice each same-length vector operand with the
same mask and re-create the op at the narrow width. The freshly created

    [5 lines not shown]
DeltaFile
+86-0mlir/test/Conversion/XeVMToLLVM/mxfp_scale_binary_hoist.mlir
+56-0mlir/test/Conversion/XeVMToLLVM/legalize_large_vector.mlir
+41-0mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
+183-03 files

FreeBSD/ports 34637c4. MOVED, science Makefile

science/py-openEMS: Remove expired port

2026-09-15 science/py-openEMS: Depends on expired lang/cython0
DeltaFile
+0-44science/py-openEMS/Makefile
+0-6science/py-openEMS/pkg-descr
+0-3science/py-openEMS/distinfo
+0-1science/Makefile
+1-0MOVED
+1-545 files

FreeBSD/ports bbb54f2. MOVED, net Makefile

net/py-pyenet: Remove expired port

2026-09-15 net/py-pyenet: Depends on expired lang/cython0
DeltaFile
+0-26net/py-pyenet/Makefile
+0-11net/py-pyenet/files/patch-README.rst
+0-3net/py-pyenet/distinfo
+0-2net/py-pyenet/pkg-descr
+0-1net/Makefile
+1-0MOVED
+1-436 files

LLVM/project cc0f679llvm/lib/Target/AArch64 SVEShuffleOpts.cpp

AArch64: Avoid dependin on createDataLayout in a pass

This should read directly from the context IR's module.
DeltaFile
+4-3llvm/lib/Target/AArch64/SVEShuffleOpts.cpp
+4-31 files

FreeBSD/ports 06c4657. MOVED, net Makefile

net/py-DTLSSocket: Remove expired port

2026-09-15 net/py-DTLSSocket: Depends on expired lang/cython0
DeltaFile
+0-23net/py-DTLSSocket/Makefile
+0-7net/py-DTLSSocket/pkg-descr
+0-3net/py-DTLSSocket/distinfo
+0-1net/Makefile
+1-0MOVED
+1-345 files

FreeBSD/ports 1899b2e. MOVED, net Makefile

net/py-pytradfri: Remove expired port

2026-09-15 net/py-pytradfri: Depends on expirign net/py-DTLSSocket
DeltaFile
+0-24net/py-pytradfri/Makefile
+0-16net/py-pytradfri/pkg-descr
+0-3net/py-pytradfri/distinfo
+0-1net/Makefile
+1-0MOVED
+1-445 files

LLVM/project 5dd43d7llvm/include/llvm/CodeGen SlotIndexes.h, llvm/lib/CodeGen LiveIntervals.cpp LiveDebugVariables.cpp

[CodeGen] Drop dead SlotIndexes before allocation

SlotIndexes keeps the index list entry of an erased instruction and only
clears its instruction pointer. Live range sizes are measured in slot
indexes and greedy ranks ranges by size, so the leftovers inflate some
ranges more than others and reorder allocation, spilling heavily on
register-starved functions.

Add SlotIndexes::compactIndexes() to erase them. Erased entries are
unlinked, so LiveIntervals, LiveStacks and LiveDebugVariables first
report the indexes they hold via appendReferencedIndexes(); a missed one
trips an assert instead of dangling.

Off by default behind -greedy-compact-slot-indexes, since it changes
allocation across much of the test suite.
DeltaFile
+263-0llvm/unittests/CodeGen/SlotIndexesTest.cpp
+48-0llvm/lib/CodeGen/SlotIndexes.cpp
+29-6llvm/include/llvm/CodeGen/SlotIndexes.h
+33-0llvm/test/CodeGen/AMDGPU/greedy-compact-slot-indexes.ll
+29-0llvm/lib/CodeGen/LiveIntervals.cpp
+29-0llvm/lib/CodeGen/LiveDebugVariables.cpp
+431-66 files not shown
+480-812 files

LLVM/project 7121969flang/test/Lower/OpenMP mismatched-bound-types.f90

Revert "[flang][test][NFC] Add OpenMP test for mismatched loop bound types" (#223813)

Reverts llvm/llvm-project#221097

This fails buildbots
https://lab.llvm.org/buildbot/#/builders/80/builds/24748 and precommit
CI.

@doru1004 please look at it and remand when fixed.
DeltaFile
+0-35flang/test/Lower/OpenMP/mismatched-bound-types.f90
+0-351 files

FreeBSD/ports 234d2a1cad/abc Makefile distinfo

cad/abc: Update g20260801 => g20260911
DeltaFile
+3-3cad/abc/distinfo
+2-2cad/abc/Makefile
+5-52 files