[DFSan] Remove check for icmp constant expression (NFC) (#235709)
icmp constant expressions are no longer supported, so we should
only check for the instruction form.
[BitcodeWriter] Remove support for fneg constant expression (NFC) (#235710)
fneg constant expressions are no longer supported, so can never
be written to bitcode.
[SCEV] Use willNotOverflow() for IV increment nuw/nsw (NFCI) (#235700)
IsIncrementNSW/IsIncrementNUW check for nsw/nuw in the same way
as willNotOverflow(), so reuse the helper.
[CIR] Admit only CIR types as nested CIR types
FuncType::verify required every type reachable from a signature to be a
CIR type, and proved it with a deep walk on every !cir.func construction.
#232863 memoized the walk in the dialect behind a mutex, but a record
that is still incomplete cannot be cached, and during CIRGen most of them
are.
The walk was needed because !cir.ptr, !cir.array, !cir.data_member,
!cir.bitfield and the record types took unconstrained mlir::Type
parameters. Constrain them to CIR types instead. Each type then checks
only its own parameters, a CIR type holds only CIR types at any depth,
and FuncType::verify checks only its inputs and result. The walk, the
cache and the mutex go away.
- Pointee and data member types use a new CIR_DialectType constraint,
and the array element constraint now requires it too.
- Bit-field storage and record members are checked in their verifiers.
Union padding is already limited to !u8i.
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[CIR][AArch64] Use CIR float types in getSVEType (#233896)
getSVEType built the bf16 and f32 vectors from mlir::Builder's
getBF16Type() and getF32Type(), which return builtin MLIR types.
!cir.vector only accepts CIR element types, so an assertions build
aborts in VectorType::get and a release build creates an invalid type.
Use getBfloat16Ty() and getSingleTy(), as the f16 and f64 cases do.
No SVE builtin reaches these cases yet, so a lit test can't cover them.
Instead, CIRBaseBuilderTy now deletes mlir::Builder's builtin float
getters, so this mistake fails to compile.
Assisted-by: Claude Code (Claude Opus 5.5)
devel/got: update to 0.130.1
User-visible changes:
- default to using SHA256 object IDs in newly created repositories
The got-portable-0.130 release accidentally skipped some commits
from got 0.130.
devel/got: update to 0.130.1
User-visible changes:
- default to using SHA256 object IDs in newly created repositories
The got-portable-0.130 release accidentally skipped some commits
from got 0.130.
[IR] Remove redundant function return alignment check (NFC) (#235690)
getRetAlign() on CallBase already falls back to the alignment of
the callee function, no need to do it again here.
[mlir][tosa] Add tosa.argmin lowering to Linalg (#233754)
Add ArgMinConverter following the existing ArgMaxConverter, including
reduction initialization and pattern registration.
Add conversion tests covering static and dynamic shapes, NaN modes, f16
inputs, and i64 indices.
Assisted-by: Codex
[IR][BasicAA] Move guard/deoptimize memory effects to declaration (#235687)
Nowadays we can express these memory effects using `IntrWrite<>`, so
move them to the intrinsic declaration in TableGen instead of
special-casing them in BasicAA.
[RISCV][GlobalISel] Support G_FPTOSI_SAT/G_FPTOUI_SAT (#234885)
RISC-V `fcvt` already saturates, so unlike G_FPTOSI/G_FPTOUI no libcalls
are needed, but it yields all-ones for NaN instead of 0. The native
cases get a custom legalization that adds a compare and a select,
mirroring lowerFP_TO_INT_SAT, using the new G_FCVT_X/G_FCVT_XU pseudos
selected through the existing `riscv_fcvt_x[u]` patterns. f16 sources
without Zfh are widened to f32 first; the remaining scalar cases use the
generic clamping lowering.
Adds the `_sat` cases to the existing GlobalISel `*-convert.ll` tests
and updates `legalizer-info-validation.mir`.
[lld][ELF]: Fix crash when a basic-block sections profile doesn't exist (#226522)
I ran into this crash while linking ONNX Runtime with ThinLTO after
passing a nonexistent path to `--lto-basic-block-sections`. lld reported
that it could not open the profile, but then crashed instead of exiting
with an error.
The failed read leaves `BBSectionsFuncListBuf` null, but `createConfig`
still sets `BBSections` to `List`. The LTO backend then constructs a
basic-block sections profile reader with that null buffer.
This change enables `List` mode only after the profile has been read
successfully, leaving the existing error reporting in place.
The regression test uses a minimal `_start` definition and a nonexistent
profile path to cover both full LTO and ThinLTO.
AI assistance: LLM-aided investigation and testing
[flang] Trust the lowering symbol table in the FirOpBuilder lookups (#232678)
Lowering's `FirOpBuilder::getNamedGlobal` / `getNamedFunction` (and
`fir::createFuncOp`, `createGlobalOp`, `lookupTypeInfoOp`) fall back to
a linear `ModuleOp::lookupSymbol` walk whenever the bridge's
`mlir::SymbolTable` misses, and every new global is a miss. For a unit
that reaches N derived types (about 25 `linkonce_odr` type-info globals
each), lowering walks the module once per global: O(N^2) again, after
#232555 removed the larger codegen term.
The fallback existed because the table was not complete:
`fir::createFuncOp` took it by const pointer and never inserted the
function it created, so every runtime, intrinsic and procedure
declaration bypassed it, and three sites in OpenACC/OpenMP lowering
created `func.func` directly. This PR makes the table complete (creation
helpers insert what they create; the direct creations register through a
new `fir::registerSymbol`, which never renames on a clash; the sham
function of `createBuilderOutsideOfFuncOpAndDo` is erased through the
table) and then lets the lookups trust it. Under `EXPENSIVE_CHECKS`
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[AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms (#232526)
Replace `not` followed by `and` with `bic` for expressions such as:
```
return svand_u32_x(svptrue_b32(), a, svnot_u32_x(svptrue_b32(), b));
```
Combine ordinary `and` with `not` when the `not` predicate is all-active
or its inactive values are undefined.
Also combine matching-predicate SVE `and_x`-`not` pairs before lowering
discards the `and` predicate. `and_x` ignores inactive results, so the
`not`'s inactive values do not need preserving.
This applies to all integer element widths. Update the pre-commit LLVM
expectations, including cases where combining would change the
result.
[AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms (#232527)
Replace `not` followed by merging `and` with `bic` for expressions such
as:
```
return svand_u32_m(pg, a, svnot_u32_x(pg, b));
```
Combine when `not` is the second operand and its predicate matches the
`and` predicate or is all-active.
Use predicated `bic` to preserve the `and`'s first operand in inactive
lanes. Use unpredicated `bic` when the `and` predicate is all-active.
Do not commute merging `and` operands, since this would change inactive
results. Leave pairs with incompatible predicates unchanged.
This applies to all integer element widths. Update the pre-commit LLVM
expectations, including cases where combining would change the
result.
[AArch64][llvm] NFC: Add pre-commit tests for SVE AND-NOT combining (#232525)
Add LLVM tests for expressions where NOT followed by AND could
use BIC. Record the existing assembly so the following changes show the
missed optimisations being fixed.
Cover _x and _m AND forms using all-active and runtime predicates. Test
_m forms across all integer element widths. Include NOT with defined
inactive values and reversed AND operands.
Also test cases that must remain as NOT followed by AND because
combining would change the values in inactive lanes.
[InlineFunction] Simplify lifetime intrinsic check (NFC) (#235681)
The pointer type check always passes since the opaque pointers
migration. Additionally, we nowadays require that lifetime
intrinsics are direct users of the alloca.
locate.1: clarify bytes vs. characters
The database stores bytes, not characters. Remove the historical
note about 7-bit storage. Also document that -i ignores case only
for ASCII letters.
Reviewed by: ziaee
MFC after: 3 days
(cherry picked from commit a03b051f238eb78cfccbe834b0cc206e66d566e5)
find.1: rewrite the -s flag section for clarity
Restructure the description of -s flag:
1. what the option does
2. why it is useful (deterministic order, streaming output)
3. how its results can differ from `find | sort'
Reviewed by: ziaee
MFC after: 3 days
(cherry picked from commit ad0f86694157c998fec500e9a553550976cbc100)
[AArch64] Support FP atomic stores with memory hints
This patch extends the atomic-store-hint pseudos to accept preserved
floating-point atomic stores. It adds an FPR16 pseudo family and direct
half, bfloat, float, and double patterns for the supported addressing
modes.
The pseudos expand relaxed stores to STR and RCPC3 release and
sequentially consistent stores to STLUR, retaining memory hints without
cross-register-bank copies.
The existing AArch64::ATOMIC_STORE_HINT_H is renamed to
AArch64::ATOMIC_STORE_HINT_HH and AArch64::ATOMIC_STORE_HINT_H now means
FP16 instead of it's old association with integer half-word.
find.1: fix rendering of find -s example
The period here is part of the literal string in the example. Adding a
space caused the example to be quoted wrongly. Instead, a trailing
zero-width space keeps the linter mandoc -T happy.
Reviewed by: ziaee
Differential Revision: https://reviews.freebsd.org/D59353
(cherry picked from commit 3581b6db62b1a2146014b3196f18bde3fc33010d)
[AArch64] Support direct RCPC3 FP atomic loads and stores
Preserve half, bfloat, float, and double atomic loads and stores
through AtomicExpand for acquire and release orderings, and preserve
sequentially consistent stores, when RCPC3 and NEON are available.
Add SelectionDAG patterns for the RCPC3 LDAPUR and STLUR operations,
including unscaled offsets, and update the existing FP lane patterns to
match the preserved floating-point atomic nodes. Targets without the
required features continue to use integer lowering.
