LLVM/project 1d1c83aoffload/include/OpenMP Mapping.h, offload/libomptarget omptarget.cpp

Reland "[OpenMP][Offload] Handle `present/to/from` when a different entry did `alloc/delete`." (#184260)

Some tests that were checking for prints inside/outside `target` regions
needed to be updated to work on systems where the ordering wasn't
deterministic.

Reverts llvm/llvm-project#184240
    
Original description from #165494:

-----

OpenMP allows cases like the following:

```c
  int *p1, *p2, x;
  p1 = p2 = &x;
  ...
  #pragma omp target_exit_data map(delete: p1[:]) from(p2[0])

    [35 lines not shown]
DeltaFile
+223-50offload/libomptarget/omptarget.cpp
+103-15offload/include/OpenMP/Mapping.h
+50-0offload/test/mapping/map_ordering_tgt_exit_data_from_mapper_overlap.c
+49-0offload/test/mapping/map_ordering_ptee_tgt_data_alloc_tgt_mapper_present_delete_from_to.c
+48-0offload/test/mapping/map_ordering_ptee_tgt_alloc_mapper_alloc_from_to.c
+43-0offload/test/mapping/map_ordering_tgt_exit_data_delete_from_assumedsize.c
+516-6511 files not shown
+765-7617 files

LLVM/project d4d1824lldb/include/lldb/Utility LLDBLog.h, lldb/source/Initialization SystemInitializerCommon.cpp

[lldb] Terminate the LLDB Log in SystemInitializerCommon::Terminate (#184261)

Currently, when calling SBDebugger::Initialize after
SBDebugger::Terminate, you hit an assert in LLDBLog when trying to
register the LLDB log a second time. Also fix the awkward
capitalization.
DeltaFile
+3-1lldb/source/Initialization/SystemInitializerCommon.cpp
+3-1lldb/source/Utility/LLDBLog.cpp
+2-1lldb/include/lldb/Utility/LLDBLog.h
+8-33 files

LLVM/project 582b009llvm/test/Transforms/LoopVectorize vplan-based-stride-mv.ll, llvm/test/Transforms/LoopVectorize/VPlan vplan-based-stride-mv.ll

[NFC][VPlan] Add initial tests for future VPlan-based stride MV

I tried to include both the features that current
LoopAccessAnalysis-based transformation supports (e.g., trunc/sext of
stride) but also cases where the current implementation behaves poorly,
e.g., https://godbolt.org/z/h31c3zKxK; as well as some other potentially
interesting scenarios I could imagine.

The are two test files with the same content. One is for VPlan dump change of
the future transformation alone (I'll update `-vplan-print-after` in the next
PR), another is for the full vectorizer pipeline. The latter have two `RUN:`
lines:
 * No multiversioning, so the next PR diff can show the transformation itself
 * Stride multiversionin performed in LAA, so that we can compare future
   VPlan-based transformation vs old behavior.
DeltaFile
+4,627-0llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+3,306-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+7,933-02 files

LLVM/project f77a830llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h, llvm/test/Transforms/LoopVectorize/VPlan vplan-print-after-all.ll

[NFC][VPlan] Split `makeMemOpWideningDecisions` into subpasses

The idea is to have handling of strided memory operations (either from
https://github.com/llvm/llvm-project/pull/147297 or for VPlan-based
multiversioning for unit-strided accesses) done after some mandatory
processing has been performed (e.g., some types **must** be scalarized)
but before legacy CM's decision to widen (gather/scatter) or scalarize
has been committed.

And in longer term, we can uplift all other memory widening decision to
be done here directly at VPlan level. I expect this structure would also
be beneficial for that.
DeltaFile
+82-38llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+10-0llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+0-10llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
+95-484 files

LLVM/project d1080c4llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Braces for outer `if`
DeltaFile
+2-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-11 files

LLVM/project 7f998a9llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanTransforms.cpp

Move to VPlanTransforms, have to pass Legal explicitly
DeltaFile
+1-78llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+76-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+3-1llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+80-793 files

LLVM/project 10319e7llvm/lib/Transforms/Vectorize LoopVectorize.cpp

Don't make unnecessary captures
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1-11 files

LLVM/project c535af1llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPRecipeBuilder.h, llvm/test/Transforms/LoopVectorize/AArch64 predication_costs.ll

[NFCI][VPlan] Split initial mem-widening into a separate transformation

Preparation change before implementing stride-multiversioning as a
VPlan-based transformation. Might help
https://github.com/llvm/llvm-project/pull/147297/ as well.
DeltaFile
+92-31llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+14-12llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+3-2llvm/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
+4-0llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+1-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
+114-455 files

LLVM/project 03e2af7clang/lib/CIR/CodeGen CIRGenExpr.cpp CIRGenExprScalar.cpp, clang/test/CIR/CodeGen bitfield-assignment-loc.c

[CIR] Fix bitfield store locations for assignment codegen (#184005)

Update bitfield-assignment codegen to emit stores at
assignment-expression source locations.
Keep `cir.set_bitfield` aligned with other store-like operations.
Prevent regressions that reattach bitfield stores to declaration-site
locations.

Add a CIR test on `clang/test/CIR/CodeGen/bitfield-assignment-loc.c`.

Fix https://github.com/llvm/llvm-project/issues/183759
DeltaFile
+15-0clang/test/CIR/CodeGen/bitfield-assignment-loc.c
+2-2clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+2-0clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+19-23 files

LLVM/project db95cd9clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

fixup! Address Carol's comments and fix git clang-format issues
DeltaFile
+27-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+20-0llvm/lib/IR/Verifier.cpp
+12-6clang/lib/Sema/SemaARM.cpp
+0-11clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4-2clang/lib/Headers/arm_acle.h
+2-4llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+65-236 files

LLVM/project 8b53b60llvm/test/CodeGen/AArch64 pcdphint-atomic-store.ll

fixup! Sort out testcases
DeltaFile
+54-102llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+54-1021 files

LLVM/project be0dd19clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

fixup! Fixes for Caroline
DeltaFile
+27-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+1-12llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-2llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+0-3clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+30-174 files

LLVM/project e097c3bclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

fixup! More small fixes
DeltaFile
+15-37clang/lib/Sema/SemaARM.cpp
+11-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5-3clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-2clang/lib/Headers/arm_acle.h
+0-1clang/test/CodeGen/arm_acle.c
+33-435 files

LLVM/project 8e2ce3fclang/test/CodeGen arm_acle.c builtins-arm64.c, clang/test/Sema/AArch64 pcdphint-atomic-store.c

fixup! Fix more PR comments
DeltaFile
+19-9clang/test/Sema/AArch64/pcdphint-atomic-store.c
+8-6llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+10-0clang/test/CodeGen/arm_acle.c
+0-9llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5-0clang/test/CodeGen/builtins-arm64.c
+0-4llvm/include/llvm/IR/IntrinsicsAArch64.td
+42-282 files not shown
+44-328 files

LLVM/project 1a94e50clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen/AArch64 pcdphint-atomic-store.c

fixup! Ensure stshh always immediately precedes a store instruction
DeltaFile
+82-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+50-13clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+62-0llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+20-26clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+15-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+8-3llvm/lib/Target/AArch64/AArch64InstrFormats.td
+237-423 files not shown
+248-499 files

LLVM/project 7a9d1c2clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup! Fix Kerry's CR comments and add negative test for "must be an integer type"
DeltaFile
+16-6llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+3-7clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+3-3clang/lib/Sema/SemaARM.cpp
+5-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+3-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-1clang/lib/Headers/arm_acle.h
+31-176 files

LLVM/project 1b235b6clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/Sema/AArch64 pcdphint-atomic-store.c

fixup!

A few small tidyups
DeltaFile
+7-6clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4-4llvm/lib/Target/AArch64/AArch64InstrFormats.td
+4-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+15-103 files

LLVM/project 1d37ec3clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

fixup! Small fixes Kerry has suggested
DeltaFile
+112-40llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+7-11clang/lib/Sema/SemaARM.cpp
+7-9llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+127-614 files

LLVM/project 54a9230llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

fixup! Fix tests
DeltaFile
+2-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-01 files

LLVM/project 4310ee6clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup! Fix issues Kerry raised in PR
DeltaFile
+10-23clang/lib/Sema/SemaARM.cpp
+16-11clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5-12clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1-5clang/include/clang/Basic/DiagnosticSemaKinds.td
+32-514 files

LLVM/project d6f0d14clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td

fixup! Address more helpful review comments from Kerry
DeltaFile
+160-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4-4llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1-4clang/lib/Sema/SemaARM.cpp
+0-5llvm/lib/Target/AArch64/AArch64InstrFormats.td
+165-134 files

LLVM/project cc85d58clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

fixup! Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`

Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
and use tablegen pattern for intrinsic, plus other small review changes.
DeltaFile
+47-75llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+69-32llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+42-47clang/lib/Sema/SemaARM.cpp
+21-12llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+17-5clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+10-12llvm/lib/Target/AArch64/AArch64InstrInfo.td
+206-1835 files not shown
+220-19211 files

LLVM/project 4705fdellvm/include/llvm/IR IntrinsicsAArch64.td, llvm/lib/Target/AArch64 AArch64InstrFormats.td

fixup! remove mayLoad/mayStore as suggested by Kerry
DeltaFile
+0-5llvm/lib/Target/AArch64/AArch64InstrFormats.td
+1-1llvm/include/llvm/IR/IntrinsicsAArch64.td
+1-62 files

LLVM/project da5515bclang/include/clang/Basic BuiltinsAArch64.def, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup!

More small issues tidied, and remove gating.
DeltaFile
+6-2clang/test/Sema/AArch64/pcdphint-atomic-store.c
+2-2clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+0-2clang/lib/Headers/arm_acle.h
+1-1clang/lib/Sema/SemaARM.cpp
+1-1clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+1-1clang/include/clang/Basic/BuiltinsAArch64.def
+11-96 files

LLVM/project 636672bclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin

Add `__arm_atomic_store_with_stshh` implementation as defined
in the ACLE. Validate that the arguments passed are correct, and
lower it to the stshh intrinsic plus an atomic store with the
allowed orderings.

Gate this on FEAT_PCDPHINT so that availability matches
hardware support for the `STSHH` instruction. Use an i64
immediate and side-effect modeling to satisfy tablegen and decoding.
DeltaFile
+140-0clang/lib/Sema/SemaARM.cpp
+48-0clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+31-0clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+29-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+13-0llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+10-2llvm/lib/Target/AArch64/AArch64InstrFormats.td
+271-25 files not shown
+298-211 files

LLVM/project 675685eclang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup! Improve error diagnostics, and other cleanups
DeltaFile
+12-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4-2clang/lib/Sema/SemaARM.cpp
+2-1clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-0clang/lib/Headers/arm_acle.h
+1-1clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-1clang/test/Sema/AArch64/pcdphint-atomic-store.c
+22-56 files

NetBSD/pkgsrc UuVAZ6pmisc/window distinfo Makefile

   Teach window(1) how to deal with ANSI terminal escape sequences.
   Specifically: escape sequences begining with [ and which contain ? or numeric values.
   This allows window(1) to work better with those terminal programs, especially those which use
   readline(3) calls, which insist on emitting these extended escape sequences even if those
   definitions are not in the termcap or terminfo spec for the terminal in use.
   this new support is incomplete in the sense that we don't do anything with the numeric values,
   but we do honor the functions of the actions requested as long as they were actions this
   program already supported.
   Preliminary testing shows a vast improvement with programs like gdb and the interactive python
   shells.
VersionDeltaFile
1.6.32.1+4-4misc/window/distinfo
1.6.66.1+2-2misc/window/Makefile
+6-62 files

FreeBSD/ports 2fb3937java/netbeans pkg-plist distinfo

java/netbeans: Update 28 => 29

Changelog:
https://github.com/apache/netbeans/releases/tag/29

PR:     293537
MFH:    2026Q1
(cherry picked from commit bb8247385cbd3f1d98e02f5dd5a33af3636fb449)
DeltaFile
+60-110java/netbeans/pkg-plist
+3-3java/netbeans/distinfo
+1-1java/netbeans/Makefile
+64-1143 files

LLVM/project 0f8aa96lldb/source/Plugins/Process/minidump RegisterContextMinidump_ARM64.cpp

[lldb][NFC] Whitespace cleanup in RegisterContextMinidump_ARM64
Breaking out the whitespace changes turned up in a separate
contentful PR.
DeltaFile
+80-70lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.cpp
+80-701 files

FreeNAS/freenas c9ada68src/middlewared/middlewared/etc_files/local/nginx nginx.conf.mako, src/middlewared/middlewared/plugins/ports ports.py

Add nginx route for rwd

This commit adds an nginx reverse proxy route at /rwd/ pointing to the rwd service on 127.0.0.1:1700. Since rwd listens on TCP (not a unix socket), nginx handles the missing service gracefully — returning 502 when rwd is down without affecting startup or other routes. Port 1700 is also registered as a reserved system port to prevent conflicts.
DeltaFile
+13-0src/middlewared/middlewared/etc_files/local/nginx/nginx.conf.mako
+1-1src/middlewared/middlewared/plugins/ports/ports.py
+14-12 files