LLVM/project 2c31050.github/workflows libc-overlay-tests.yml

[libc][ci] Add qemu armhf overlay tests to precommit CI. (#203369)
DeltaFile
+10-1.github/workflows/libc-overlay-tests.yml
+10-11 files

FreeNAS/freenas 2325eaa

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas cd25426src/middlewared/middlewared/plugins/container attachments.py, src/middlewared/middlewared/plugins/vm attachments.py

NAS-141404 / 26.0.0-RC.1 / Restart autostart containers and VMs after an encrypted pool is unlocked (#19272)

## Problem

An autostart container or VM on a passphrase-encrypted pool doesn't come
back after you unlock the pool. After a reboot, the pool is locked and
its workloads are stopped; unlocking should start them again, but they
stay `STOPPED` and you have to start each one by hand.

Unlocking a dataset asks each attachment delegate to start what's
attached to it. That works for shares (SMB, NFS, …), but for containers
and VMs, the delegate only ever reports instances that are *already
running* — so a workload that's stopped *because* its pool was locked
never gets picked up. VMs had a one-off hack to work around this;
containers had nothing.

## Changes

- Added a `start_on_unlock` hook to the attachment-delegate base class.

    [19 lines not shown]
DeltaFile
+94-27src/middlewared/middlewared/plugins/container/attachments.py
+106-12src/middlewared/middlewared/plugins/vm/attachments.py
+89-0src/middlewared/middlewared/pytest/unit/plugins/test_vm_attachment_matching.py
+80-0tests/api2/test_pool_dataset_unlock_restart_containers.py
+40-35tests/api2/test_pool_dataset_unlock_restart_vms.py
+62-0src/middlewared/middlewared/pytest/unit/plugins/test_container_attachment_matching.py
+471-745 files not shown
+586-13811 files

LLVM/project 0b908e1clang/test/Driver msvc-link.c

[clang][test] Avoid relying on `-fuse-ld=ld` default value for marm64x test (#209597)

Test case added in #209324
DeltaFile
+4-4clang/test/Driver/msvc-link.c
+4-41 files

FreeBSD/ports 3573b50sysutils/nginx-ui distinfo Makefile

sysutils/nginx-ui: Update to 2.4.2

ChangeLogs:

- https://github.com/0xJacky/nginx-ui/releases/tag/v2.3.6
- https://github.com/0xJacky/nginx-ui/releases/tag/v2.3.7
- https://github.com/0xJacky/nginx-ui/releases/tag/v2.3.8
- https://github.com/0xJacky/nginx-ui/releases/tag/v2.3.9
- https://github.com/0xJacky/nginx-ui/releases/tag/v2.3.10
- https://github.com/0xJacky/nginx-ui/releases/tag/v2.3.11
- https://github.com/0xJacky/nginx-ui/releases/tag/v2.4.0
- https://github.com/0xJacky/nginx-ui/releases/tag/v2.4.1
- https://github.com/0xJacky/nginx-ui/releases/tag/v2.4.2
DeltaFile
+7-7sysutils/nginx-ui/distinfo
+2-3sysutils/nginx-ui/Makefile
+9-102 files

FreeBSD/ports 6df6e2cwww/py-httpx-retries distinfo Makefile

www/py-httpx-retries: Update to 0.6.0

ChangeLog: https://github.com/will-ockmore/httpx-retries/releases/tag/0.6.0
DeltaFile
+3-3www/py-httpx-retries/distinfo
+1-1www/py-httpx-retries/Makefile
+4-42 files

FreeNAS/freenas 3c55f77src/middlewared/middlewared/plugins/catalog config.py

Merge catalog update onto current config before persisting

## Problem
`catalog.update` wrote the raw partial request straight to the datastore and validated it directly. Because `CatalogUpdate` is a for-update model, a call that omits `preferred_trains` left the field as the `undefined` sentinel — so on ENTERPRISE systems `OFFICIAL_ENTERPRISE_TRAIN not in data.preferred_trains` raised a TypeError, and any partial write could drop the existing trains.

## Solution
Read the current config, merge the incoming update onto it, then validate and persist the merged result so partial updates keep untouched fields. Only `preferred_trains` is written back, since it's the sole stored column.
DeltaFile
+6-3src/middlewared/middlewared/plugins/catalog/config.py
+6-31 files

LLVM/project 3ba1b70llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp, llvm/test/CodeGen/AMDGPU vgpr-set-msb-coissue.mir

[AMDGPU][CodeGen] Fix `S_NOP` insertion during `S_SET_VGPR_MSB` placement (#209525)

The issue arises when co-issue optimizations move the initial insertion
position for `S_SET_VGPR_MSB` to an earlier spot, creating a mismatch
with the position used to determine whether a `S_NOP` is needed.
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+1-0llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
+2-12 files

LLVM/project fc298cclldb/source/Expression DWARFExpression.cpp, lldb/unittests/Expression DWARFExpressionTest.cpp

[lldb] Reject mixed typed DWARF binary operands (#201288)

## Summary

LLDB currently accepts and evaluates some ill-typed DWARF typed binary
operations whose two operands have different base types.

DWARF v5 typed-expression rules require arithmetic/logical and
relational binary operators to operate on operands of the same type,
either the same base type or the generic type. (see [DWARF v5
doc](https://dwarfstd.org/doc/DWARF5.pdf) Section 2.5.1.4)

This patch adds an explicit compatibility check before evaluating the
affected binary operators.

## Example

A DWARF expression illustrating the issue is:


    [49 lines not shown]
DeltaFile
+108-0lldb/source/Expression/DWARFExpression.cpp
+70-0lldb/unittests/Expression/DWARFExpressionTest.cpp
+178-02 files

LLVM/project fbba327llvm/cmake/modules HandleLLVMOptions.cmake

[CMake] Add -Wl,-z,pack-relative-relocs if supported (#208217)

We should aim to provide a good experience by default. Enable RELR for
PIC builds (which is on by default, even in non-dylib builds) if
supported by the linker (feature-tested) and the libc (currently
hardcoded as glibc 2.36+; musl has no easy way to determine support).

RELR substantially reduces the size of the dynamic relocations in PIE
executables and shared libraries and therefore also lowers max-rss and
startup time due to fewer page faults.
DeltaFile
+19-0llvm/cmake/modules/HandleLLVMOptions.cmake
+19-01 files

FreeBSD/ports 92a6804security/libfprint Makefile, security/libfprint/files patch-libfprint_drivers_focaltech__moc_focaltech__moc.c patch-data_autosuspend.hwdb

security/libfprint: Add Focaltech MOC PIDs 077A and 079A

This patch has been submitted upstream and should hopefully be available
in the next libfprint release.

PR:             296412
Approved by:    maintainer timeout
Sponsored by:   The FreeBSD Foundation
DeltaFile
+11-0security/libfprint/files/patch-libfprint_drivers_focaltech__moc_focaltech__moc.c
+11-0security/libfprint/files/patch-data_autosuspend.hwdb
+1-0security/libfprint/Makefile
+23-03 files

FreeBSD/ports 81e721bsecurity/libfprint distinfo Makefile

security/libfprint: Update to 1.94.10

Release notes:  https://gitlab.freedesktop.org/libfprint/libfprint/-/releases/v1.94.10
PR:             296411
Reviewed by:    jrm
Approved by:    maintainer timeout
Sponsored by:   Framework Computer Inc
DeltaFile
+3-3security/libfprint/distinfo
+2-3security/libfprint/Makefile
+1-0security/libfprint/pkg-plist
+6-63 files

LLVM/project d218bc4llvm/test/Assembler thinlto-bad-summary-5.ll

[ThinLTO] Fix thinlto-bad-summary-5.ll in read-only environments (#209513)

The test thinlto-bad-summary-5.ll was failing in read-only environments
(such as sandboxed test runners) because it attempted to write the
output bitcode file to the same directory as the input file, resulting
in a "Permission denied" error.

Fix this by redirecting the output to /dev/null using `-o /dev/null`.
We cannot use `-disable-output` here because the error we want to
test is triggered inside the BitcodeWriter, which is bypassed when
output is disabled.

assisted by gemini
DeltaFile
+1-1llvm/test/Assembler/thinlto-bad-summary-5.ll
+1-11 files

OPNSense/core 9b07670src/opnsense/service/modules/actions script_output.py

configd: script_output remove file on crash as well.
DeltaFile
+3-1src/opnsense/service/modules/actions/script_output.py
+3-11 files

LLVM/project 21cab1ellvm/test/CodeGen/AMDGPU eliminate-frame-index-v-add-co-u32.mir eliminate-frame-index-s-add-i32.mir

[AMDGPU] Fix CFI emission when scratch instructions are used to spill

4b1cfc5d7c606e "[NFCI][AMDGPU] Final touch before moving to
`GET_SUBTARGETINFO_MACRO` (#177401)" (or more generally the move to
hasFlatScratchEnabled over just enableFlatScratch) was missed during the
CFI upstreaming for AMDGPU, and so we currently define the CFA
incorrectly for the architected flat scratch case.

This incorrect CFI is generated for e.g. gfx942. For such architecture,
the stack pointer (s32) holds a swizzled address (per-lane offset) but
the CFA needs to be an unswizzled address (per-wave).

In the incorrect program, we have a prologue looking like:

        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
        s_mov_b32 s0, s33
        s_mov_b32 s33, s32
        [...]
        s_add_i32 s32, s32, 16

    [24 lines not shown]
DeltaFile
+76-76llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
+50-50llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
+57-37llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
+31-31llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
+20-20llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
+10-10llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+244-2249 files not shown
+286-26615 files

LLVM/project 0fae10bllvm/test/CodeGen/AMDGPU misaligned-vgpr-regsequence.mir

[AMDGPU] Add stackPtrOffsetReg to llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir (#209533)

Prepare for this being observable to the CFA generation code.
DeltaFile
+2-0llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
+2-01 files

FreeBSD/src 40cc9desys/dev/mlx5/mlx5_ib mlx5_ib_devx.c

mlx5ib: use the eventfd_ctx API for DEVX event subscriptions

The DEVX_SUBSCRIBE_EVENT redirect path resolved the user's eventfd with
fdget(), which on FreeBSD only finds LinuxKPI files.  rdma-core creates
the eventfd with the native FreeBSD eventfd(2), so the lookup failed and
subscription returned EBADF; the delivery side likewise assumed a
LinuxKPI-pollable file.

Use the LinuxKPI eventfd_ctx API instead: eventfd_ctx_fdget() resolves
the native eventfd, eventfd_signal() notifies it, and eventfd_ctx_put()
releases it.  DEVX async events can then be delivered through a redirect
eventfd.

Reviewed by: kib
Sponsored by: Nvidia networking
MFC after: 1 month
DeltaFile
+12-10sys/dev/mlx5/mlx5_ib/mlx5_ib_devx.c
+12-101 files

LLVM/project f69342fcompiler-rt/lib/sanitizer_common sanitizer_dl.cpp sanitizer_dl.h, compiler-rt/lib/tsan/go buildgo.sh

Reland "[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base" (#209576)

Attempt 2 at #206299, fixing a linkage issue with gotsan on older
versions of glibc. Rather than forcing linkage of libdl (which may not
be safe with go), this just disables the dladdr usage under go builds.
This bug only affected MSAN and DFSAN anyway, and the code should be
unused by TSAN.

`ForEachMappedRegion` processes dynamic linker map entries to track
loaded segments. However, it assumes map->l_addr is the address of the
ELF header. For DSOs linked with a custom preferred image base offset
(e.g. -Wl,--image-base=0x4000000), `map->l_addr` contains the relocation
bias: `map->l_addr = actual_load_address - preferred_base`

In this case, map->l_addr points below the first loaded segment in
unmapped or PROT_NONE memory. Doing a read dereference at this address
triggers a SIGSEGV. Add a call to dladdr() on the dynamic section
pointer map->l_ld to obtain the true ELF header base address.


    [8 lines not shown]
DeltaFile
+12-1compiler-rt/lib/sanitizer_common/sanitizer_dl.cpp
+4-0compiler-rt/lib/sanitizer_common/sanitizer_dl.h
+2-1compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
+3-0compiler-rt/lib/tsan/go/buildgo.sh
+2-0compiler-rt/lib/sanitizer_common/sanitizer_common_nolibc.cpp
+0-1compiler-rt/test/sanitizer_common/TestCases/Linux/dlopen_image_base.c
+23-36 files

FreeBSD/ports d58a81dcomms/py-pynitrokey Makefile distinfo

comms/py-pynitrokey: Update 0.10.0 => 0.12.3

Changelog:
https://github.com/Nitrokey/pynitrokey/releases/tag/v0.11.0
https://github.com/Nitrokey/pynitrokey/releases/tag/v0.11.1
https://github.com/Nitrokey/pynitrokey/releases/tag/v0.11.2
https://github.com/Nitrokey/pynitrokey/releases/tag/v0.11.3
https://github.com/Nitrokey/pynitrokey/releases/tag/v0.11.4
https://github.com/Nitrokey/pynitrokey/releases/tag/v0.12.0
https://github.com/Nitrokey/pynitrokey/releases/tag/v0.12.1
https://github.com/Nitrokey/pynitrokey/releases/tag/v0.12.2
https://github.com/Nitrokey/pynitrokey/releases/tag/v0.12.3

- Add py-pyscard as a dependency since some experimental commands needs
  it.
- Add _BR_DEPENDS with a list of common dependencies for BUILD and RUN.

PR:             296693
Sponsored by:   UNIS Labs
Co-authored-by: Vladimir Druzenko <vvd at FreeBSD.org>
DeltaFile
+6-17comms/py-pynitrokey/Makefile
+3-3comms/py-pynitrokey/distinfo
+9-202 files

NetBSD/pkgsrc UR6dfQydoc CHANGES-pkgsrc-2026Q2

   A bunch of security fixes, up to #7168
VersionDeltaFile
1.1.2.3+43-1doc/CHANGES-pkgsrc-2026Q2
+43-11 files

FreeNAS/freenas 66e8075src/middlewared/middlewared/plugins/reporting/netdata graphs.py

NAS-141692 / 26.0.0-RC.1 / Fix UPS Input Load graph showing Watts on a percentage axis (by Qubad786) (#19312)

## Problem
The "UPS Input Load" report has `vertical_label = 'Percentage'` but
pointed `get_chart_name()` at Netdata's `upsd_<id>.load_usage` chart,
whose units are Watts (`ups.realpower`, or `ups.load/100 ×
ups.realpower.nominal`). So the graph rendered absolute power draw (e.g.
~117W for a ~30% load on a 390W UPS) under a "Percentage" axis. This
regressed in the python.d→go.d Netdata migration, which renamed the
chart from `nut_<id>.load` to `load_usage` without updating the label —
the migration picked the wrong sibling chart.

## Solution
Point the chart at `upsd_<id>.load_percentage` (units: percentage),
which maps to the raw NUT `ups.load` variable and matches both the
existing label and title. This chart is gated on the same `ups.load`
variable as `load_usage`, so it's available under identical conditions,
and it populates even on UPSes that don't report realpower — where
`load_usage` would be empty.

    [3 lines not shown]
DeltaFile
+1-1src/middlewared/middlewared/plugins/reporting/netdata/graphs.py
+1-11 files

LLVM/project 5245afcllvm/test/CodeGen/SPIRV vk-pushconstant-layout.ll

[NFC][SPIR-V] Remove stale XFAIL in vk-pushconstant-layout.ll (#209447)
DeltaFile
+1-3llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll
+1-31 files

FreeBSD/ports c667f1bsecurity/py-nethsm Makefile distinfo

security/py-nethsm: Update 1.4.1 => 2.1.2, take maintainership

Changelogs:
https://github.com/Nitrokey/nethsm-sdk-py/releases/tag/v2.0.0
https://github.com/Nitrokey/nethsm-sdk-py/releases/tag/v2.0.1
https://github.com/Nitrokey/nethsm-sdk-py/releases/tag/v2.1.0
https://github.com/Nitrokey/nethsm-sdk-py/releases/tag/v2.1.1
https://github.com/Nitrokey/nethsm-sdk-py/releases/tag/v2.1.2

PR:             296691
Approved by:    awoonyaa at gmail.com (former maintainer, inactive for more than 2 years with multiple timeouts)
Sponsored by:   UNIS Labs
Co-authored-by: Vladimir Druzenko <vvd at FreeBSD.org>
DeltaFile
+4-3security/py-nethsm/Makefile
+3-3security/py-nethsm/distinfo
+7-62 files

LLVM/project fc0b032llvm/lib/Transforms/Utils CallPromotionUtils.cpp, llvm/test/Transforms/SampleProfile icp_target_feature.ll

Revert "[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features" (#209572)

Reverts llvm/llvm-project#208774

The failure that caused the revert last time should be fixed by
37b8e765ce4837a7577e6f762bcdffe4b232759c.
DeltaFile
+0-61llvm/test/Transforms/SampleProfile/icp_target_feature.ll
+0-21llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
+0-822 files

LLVM/project f2126c3llvm/test/CodeGen/AMDGPU xnack-subtarget-feature-disabled.ll xnack-subtarget-feature-any.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (38)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
+7-7llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-any.ll
+7-7llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
+5-5llvm/test/CodeGen/AMDGPU/xnor.ll
+4-4llvm/test/CodeGen/AMDGPU/xor_add.ll
+3-3llvm/test/CodeGen/AMDGPU/xor3.ll
+33-3313 files not shown
+54-5419 files

LLVM/project 6e90191llvm/test/CodeGen/AMDGPU vopd-combine.mir wave_dispatch_regs.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (37)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/vopd-combine.mir
+6-6llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
+6-6llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
+6-6llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
+5-5llvm/test/CodeGen/AMDGPU/wave32.ll
+5-5llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+35-3592 files not shown
+196-19698 files

LLVM/project f38f32bllvm/test/CodeGen/AMDGPU unsupported-image-sample.ll unsupported-av-load.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (35)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
+6-6llvm/test/CodeGen/AMDGPU/unsupported-av-load.ll
+6-6llvm/test/CodeGen/AMDGPU/unsupported-av-store.ll
+6-6llvm/test/CodeGen/AMDGPU/trap-abis.ll
+6-6llvm/test/CodeGen/AMDGPU/uaddsat.ll
+5-5llvm/test/CodeGen/AMDGPU/umed3.ll
+36-3687 files not shown
+197-19793 files

LLVM/project e7431c2llvm/test/CodeGen/AMDGPU vector-reduce-fmin.ll vector-reduce-fmax.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (36)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+20-20llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+20-20llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+16-16llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
+16-16llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
+16-16llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+16-16llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+104-10493 files not shown
+442-44299 files

LLVM/project 7b57de4llvm/test/CodeGen/AMDGPU strict_fadd.f16.ll strict_fmul.f16.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (34)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+12-12llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
+12-12llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
+12-12llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
+10-10llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
+8-8llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
+8-8llvm/test/CodeGen/AMDGPU/store-atomic-flat.ll
+62-6288 files not shown
+307-30794 files

LLVM/project 2493265llvm/test/CodeGen/AMDGPU si-unify-exit-return-unreachable.ll sram-ecc-default.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (33)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+76-80llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll
+8-8llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll
+6-6llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
+6-6llvm/test/CodeGen/AMDGPU/spill-agpr.mir
+6-6llvm/test/CodeGen/AMDGPU/spillv16.ll
+5-5llvm/test/CodeGen/AMDGPU/smed3.ll
+107-11194 files not shown
+294-298100 files