Remove parent ZIO from dbuf_prefetch()
I am not sure why it was added there 10 years ago, but it seems not
needed now. According to my tests removing it improves sequential
read performance with recordsize=4K by 5-10% by reducing the CPU
overhead in prefetcher.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Reviewed-by: Rob Norris <robn at despairlabs.com>
Reviewed-by: Ameer Hamza <ahamza at ixsystems.com>
Reviewed-by: Akash B <akash-b at hpe.com>
Signed-off-by: Alexander Motin <alexander.motin at TrueNAS.com>
Closes #18214
[libclc] Enable -ffp-contract=fast-honor-pragmas globally (#153137)
Enable -ffp-contract=fast-honor-pragmas globally improves performance.
Verified that exp, trig, and hyperbolic functions pass the OpenCL CTS on
Intel GPUs with this flag enabled.
Note: exp/exp2 still require the fixes proposed in #179875; however,
those failures are independent of the fp-contract changes in this patch.
[TableGen] Introduce RegisterByHwMode
This is useful for `InstAlias` where a fixed register may depend on the
HwMode. The motivating use case for this is the RISC-V RVY ISA where
certain instructions mnemonics are remapped to take a different
register class depending on the HwMode and can be used as follows:
```
def NullReg : RegisterByHwMode<PtrRC, [RV32I, RV64I, RV64Y, RV64Y],
[X0, X0, X0_Y, X0_Y]>;
```
Pull Request: https://github.com/llvm/llvm-project/pull/175227
HBSD: Bring in candidate patch to fix dns/unbound
This patch fixes the build of dns/unbound. We enable python support for
unbound by default, which is why we're hitting this.
Signed-off-by: Shawn Webb <shawn.webb at hardenedbsd.org>
Obtained-from: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=292625
[RISCV] Force a frame pointer when the max reserved call frame exceeds simm12. (#182124)
We need to be able to address emergency spill slots without requiring a
register scavenging. This requires the emergency spill slot to be near
the SP or the FP to keep the offset small enough. If there is a large
reserved call frame, we can't keep the emergency spill slot near SP. But
we might not have a frame pointer.
This patch forces the use of a frame pointer when the max reserved call
frame is large so we can keep the emergency spill slot near it. This
idea is borrowed from AArch64.
Multiple MIR tests had to be updated to set the max call frame size as
the reserved registers are frozen before mirFileLoaded is called. I
copied mirFileLoaded from AArch64, but it appears the register freezing
moved after the AArch64 code was written.
Fixes #180199.
[LSR][RISCV] Add support for cmp/branch fuse.
RISCV has cmp within branches, and therefore
costing using cmp/branch fuse in LSR is
useful to configure the proposed solution
cost for LSR.
