net-mgmt/monitoring-plugins: Add CURL option to build check_curl
Upstream deprecated check_http in 3.0.0 and declared check_curl its
stable replacement, so make the plugin available here as an option.
It is off by default, like every other option in this port that pulls
an external library.
check_curl requires libcurl and uriparser. configure only knows
--with-libcurl and --with-uriparser, so pass those explicitly instead
of relying on autodetection. The submitted patch used a --with-curl
knob that does not exist and was missing the libcurl dependency.
PR: 296901
Submitted by: franz at electromail.org
Sponsored by: Netzkommune GmbH
[NFC][AMDGPU] Remove redundant CodeGen test coverage
This PR removes duplicate test files, cases, and RUN commands while preserving all effective coverage.
Deleted files:
- `unexpected-reg-unit-state.mir` duplicates the bar case in `fast-ra-kills-vcc.mir`.
- `schedule-fs-loop.ll` produces the same bitcode and output as `schedule-fs-loop-nested-if.ll`.
- `regbankselect-add.s16.mir` duplicates the first four cases in `regbankselect-add.mir`.
- The dynamic-indirect-access LDS tests duplicate the static-dynamic versions, including their ASAN variants.
- The two removed NextUseAnalysis tests duplicate `sequence_2_loops.mir` and `triple-nested-loops.mir`.
Trimmed test cases:
- Remove generic OR cases from `atomicrmw-xor.ll`; `atomicrmw-or.ll` contains them.
- Remove the fcmp ord case from `fmax_legacy.ll`; `fmin_legacy.ll` contains it.
- Remove `variable_memcpy_caller1` from `lower-mem-intrinsics.ll`; `caller0` provides identical coverage.
Deduplicated test commands:
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[BOLT] Fix instr.cpp attribute warnings on arm (#218036)
The `force_align_arg_pointer` is exclusive to x86. This causes builds to
fail on arm with -Werror. Omit this attribute on non-x86 platforms.
[AMDGPU] Add custom lowering for E5M3 path for packed convert instructions through convert.{to|from}.arbitrary.fp
Change-Id: I2b7ef70332fcaafe63245e0afba58829ede8f3e4
[WebAssembly][NewPM] Add GISel Pass Skeleton
Mostly complete, but I still need to port a few more passes.
Reviewers: sbc100, dschuff, aheejin, QuantumSegfault
Pull Request: https://github.com/llvm/llvm-project/pull/217981
[GlobalISel][NewPM] Port InstructionSelect
Standard NewPM pass porting. We have to keep the Impl class in the
header given it is used by unittests, although it's not very big so it
shouldn't be a huge deal.
Reviewers: aemerson, arsenm, aengelke, vikramRH, lenary
Pull Request: https://github.com/llvm/llvm-project/pull/217968
[AMDGPU] Check register class when folding a redundant AND (#217900)
tryFoldRedundantAND accepts an SALU AND as the parent instruction. The
child
AND can be a VALU instruction, so the fold replaced a VGPR with an SGPR
in
every use of the child result. A use that requires a VGPR, for example
data0
of DS_BPERMUTE_B32, then fails the machine verifier. This aborted a
rocPRIM
build for gfx1010.
Call constrainRegClass on the replacement register with the register
class of
the folded register, and fold only when it succeeds. Every use of the
folded
register accepts its register class, so the constrained replacement
register
is legal in those uses, and no walk over the uses is needed.
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[SPIRV] Pass optLevel to InstructionSelect
Canonical with all other targets (minus m68k which I will fix next).
Seems to have been dropped in eab7d3639b3c6dc9dda9a0ab1643f0e45ad2d9d6
accidentally when introducing the InstructionSelect subclass to avoid
the need for RegBankSelect.
Reviewers: Keenuts, arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/217929
[GISel] Remove SPIRVInstructionSelect
This subclass only existed to remove the need for MFs to have the
RegBankSelected property coming into InstructionSelect. The NewPM plays
much less nicely with pass inheritance, so change this to an option
specified as a parameter in the InstructionSelect constructor to avoid
inheritance so the future NewPM port can have the ~same API for
creation.
The usage of CodeGenOptLevel::Default matches the existing behavior,
although is probably wrong. That should be fixed in a separate patch
though.
Reviewers: arsenm, Keenuts
Pull Request: https://github.com/llvm/llvm-project/pull/217928
[RISCV][MC] Add experimental Smip, and Ssip support (#215095)
Add support for version 0.20 of the Smip, and Ssip extensions from the
RISC-V fast interrupt specification. Also bump the existing extensions
of ACLIC to 0.20.
[PeepholeOpt] Erase optimized compare from LocalMIs earlier (#217848)
We need to drop the compare instruction that was optimized away from
LocalMIs before the LocalMIs-based load folding optimization a few lines
below. Addresses a regression from #194662.
Fixes https://github.com/llvm/llvm-project/issues/208746.
---------
Co-authored-by: woruyu <1214539920 at qq.com>
(cherry picked from commit b26a359753175bd5cc53fb0f2a168d12bb0498c8)
