LLVM/project 2c9a3d2 — offload Maintainers.md

offload: Remove Johannes from current maintainers (#228853)
DeltaFile
+0-3offload/Maintainers.md
+0-31 files

LLVM/project 33de671 — llvm/lib/Target/PowerPC PPCMIPeephole.cpp, llvm/test/CodeGen/PowerPC peephole-elim-extsw-subreg-input.mir

PPC: Fold 64-bit zero-extending word load feeding extsw subregister

A gprc LWZ/LWZX feeding EXTSW_32_64 is rewritten into a sign-extending
LWA/LWAX load. Extend the same fold to the 64-bit zero-extending word
loads LWZ8/LWZX8 when the EXTSW_32_64 reads their sub_32 subregister,
producing a single LWA/LWAX instead of a redundant lwz+extsw pair.

Co-authored-by: Claude (Claude Opus 4.8, claude-opus-4-8) <noreply at anthropic.com>
DeltaFile
+12-12llvm/test/CodeGen/PowerPC/peephole-elim-extsw-subreg-input.mir
+13-3llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+25-152 files

LLVM/project 4cd12d9 — llvm/test/CodeGen/PowerPC peephole-elim-extsw-subreg-input.mir

PPC: Add MIR examples for missed extsw+word-load fold on subregister input

A gprc LWZ/LWZX feeding EXTSW_32_64 folds into a sign-extending LWA/LWAX
load. The equivalent 64-bit zero-extending word loads (LWZ8/LWZX8) whose
sub_32 feeds EXTSW_32_64 are not folded, leaving a redundant lwz+extsw
(or lwzx+extsw) pair. Add MIR examples documenting the missed fold.

Co-authored-by: Claude (Claude Opus 4.8, claude-opus-4-8) <noreply at anthropic.com>
DeltaFile
+152-6llvm/test/CodeGen/PowerPC/peephole-elim-extsw-subreg-input.mir
+152-61 files

LLVM/project 87fab29 — llvm/lib/Target/PowerPC PPCMIPeephole.cpp

Remove NarrowSubReg check
DeltaFile
+1-2llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+1-21 files

LLVM/project 5bc30da — llvm/lib/Target/PowerPC PPCMIPeephole.cpp

review comments
DeltaFile
+3-4llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+3-41 files

LLVM/project 5c37893 — llvm/lib/Target/PowerPC PPCMIPeephole.cpp, llvm/test/CodeGen/PowerPC peephole-elim-extsw-subreg-input.mir

PPC: Fix extsw elimination when the input reads a subregister

The EXTSW_32_64 sign-extend elimination previously assumed its input
was a full register value. It would then try using that value as the
source of the new (unnecessary) INSERT_SUBREG.

The new test would then hit this verifier error:

```
bb.0:
  liveins: $x3
  %0:g8rc = COPY killed $x3
  %1:g8rc = RLDICL killed %0:g8rc, 0, 33
  %3:g8rc = IMPLICIT_DEF
  %2:g8rc = INSERT_SUBREG %3:g8rc(tied-def 0), %1:g8rc, %subreg.sub_32
  $x3 = COPY killed %2:g8rc
  BLR8 implicit $lr8, implicit $rm, implicit killed $x3

*** Bad machine code: INSERT_SUBREG expected inserted value to have equal or lesser size than the subreg it was inserted into ***

    [8 lines not shown]
DeltaFile
+27-12llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+30-0llvm/test/CodeGen/PowerPC/peephole-elim-extsw-subreg-input.mir
+57-122 files

LLVM/project efe5233 — llvm/lib/Target/PowerPC PPCInstrInfo.cpp

Add assert
DeltaFile
+9-4llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+9-41 files

LLVM/project 2087063 — llvm/lib/Target/PowerPC PPCInstrInfo.cpp, llvm/test/CodeGen/PowerPC sext_elimination.mir

PPC: Fix EXTSW elimination promoting a subregister operand

promoteInstr32To64ForElimEXTSW copies operands from the 32-bit
instruction verbatim into its promoted 64-bit form. When an operand
reads the sub_32 subregister of a 64-bit register, the promoted
instruction (which takes a full register) ended up with an illegal
subregister use and failed the machine verifier.

Drop the sub_32 subregister and use the original full register, which
provides the low 32 bits the promoted instruction operates on. This
avoids  verifier error regressions in a future change.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8, claude-opus-4-8)
DeltaFile
+36-10llvm/test/CodeGen/PowerPC/sext_elimination.mir
+7-0llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+43-102 files

LLVM/project a309249 — offload Maintainers.md

offload: Remove Johannes from current maintainers
DeltaFile
+0-3offload/Maintainers.md
+0-31 files

LLVM/project 33815c5 — llvm/lib/CodeGen PHIElimination.cpp

PHIElimination: Remove LiveVariables/LiveIntervals abstraction helpers

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+15-26llvm/lib/CodeGen/PHIElimination.cpp
+15-261 files

LLVM/project 5ab3aa0 — llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp TailDuplicator.cpp, llvm/lib/Target/AArch64 AArch64MCInstLower.cpp AArch64FrameLowering.cpp

CodeGen: Prefer getting the Triple from the Module

Continue replacing TargetMachine::getTargetTriple() with the module's
triple at sites where a Module is one hop away through an available
Function, GlobalValue or MachineModuleInfo.

Where the surrounding class already holds a Subtarget, use its triple
rather than routing through the Module.

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+7-3llvm/lib/CodeGen/TailDuplicator.cpp
+4-4llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+3-2llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+2-2llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+2-1llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
+2-1llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
+20-1313 files not shown
+34-2619 files

FreeBSD/ports 6f4b605 — www/immich-ml Makefile

www/immich-ml: Restrict to 64-bit platforms

The ONNX runtime does not build on i386.

Sponsored by:   Netzkommune GmbH
DeltaFile
+3-0www/immich-ml/Makefile
+3-01 files

FreeBSD/ports 8b37f0f — www/immich-cli Makefile

www/immich-cli: Unbreak the build with BUILD_AS_NON_ROOT

npm then has no writable HOME and cannot create its cache.  Restrict the
port to 64-bit, the TypeScript compiler has no FreeBSD/i386 binary.

PR:             299082
Reported by:    otis
Sponsored by:   Netzkommune GmbH
DeltaFile
+6-2www/immich-cli/Makefile
+6-21 files

FreeBSD/ports 99545d2 — www/immich Makefile

www/immich: Unbreak the build with BUILD_AS_NON_ROOT

npm then has no writable HOME and cannot create its cache.

PR:             299082
Reported by:    bruno at ruomad.net
Sponsored by:   Netzkommune GmbH
DeltaFile
+2-1www/immich/Makefile
+2-11 files

LLVM/project c275ebd — llvm/include/llvm/ADT DenseMap.h

[ADT] Use StorageT for temporary storage in DenseMapBase::grow (NFC) (#228802)

Without this patch, the non-relocatable path of DenseMapBase::grow
rehashes into a temporary DenseMapBase instance:

    DenseMapBase Tmp(NumBuckets, ExactBucketCount{});

This patch switches to:

    StorageT Tmp;

while converting initEmpty, initWithExactBucketCount, and moveFrom to
static helpers to operate directly on StorageT.  This brings the
following benefits:

- grow() no longer calls the destructor for Tmp because StorageT does
  not have one.  Without this patch, we call Tmp.~DenseMapBase(), which
  in turn calls destroyAll() even though the bucket array has no
  elements to destruct.  Even with inlining enabled, the host compiler

    [11 lines not shown]
DeltaFile
+36-52llvm/include/llvm/ADT/DenseMap.h
+36-521 files

LLVM/project 91bd43a — llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp TailDuplicator.cpp, llvm/lib/Target/AArch64 AArch64FrameLowering.cpp AArch64PointerAuth.cpp

CodeGen: Prefer getting the Triple from the Module

Continue replacing TargetMachine::getTargetTriple() with the module's
triple at sites where a Module is one hop away through an available
Function, GlobalValue or MachineModuleInfo.

Where the surrounding class already holds a Subtarget, use its triple
rather than routing through the Module.

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+7-3llvm/lib/CodeGen/TailDuplicator.cpp
+4-4llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+2-2llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+1-2llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+2-1llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
+1-1llvm/lib/Target/X86/X86IndirectThunks.cpp
+17-1313 files not shown
+30-2619 files

LLVM/project e9d4ced — llvm/test/CodeGen/AArch64 div-i256.ll phi.ll, llvm/test/CodeGen/RISCV abdu.ll idiv_large.ll

CodeGen: Run LiveIntervals before PHIElimination and drop LiveVariables from it

Move LiveIntervals to run before PHIElimination in the optimized register
allocation pipeline, and make PHIElimination maintain LiveIntervals only.

This removes the last explicit use of LiveVariables. The actual analysis is no
longer used. There are implicit dependencies on the side effects of running the
analysis due to adjustments of dead flags, so further work is still needed to
complete the removal.

This perturbs register allocation in a number of tests. The same codegen result
can be achieved by not preserving the analysis and recomputing fresh. Greedy is
just sensitive to the exact slot index and value numbering with identical MIR.

Measured across every affected test the emitted instruction count goes from
145124 to 145196, +0.050%, with changes in both directions. The largest
regression is AArch64/phi.ll, where the GlobalISel output gains about 30
instructions and no longer matches the SelectionDAG output; the largest
improvements are ARM/fpclamptosat.ll and PowerPC/common-chain.ll.

    [2 lines not shown]
DeltaFile
+1,648-1,642llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
+1,026-1,017llvm/test/CodeGen/X86/i128-udiv.ll
+396-396llvm/test/CodeGen/RISCV/idiv_large.ll
+452-210llvm/test/CodeGen/AArch64/phi.ll
+290-290llvm/test/CodeGen/RISCV/abdu.ll
+242-242llvm/test/CodeGen/AArch64/div-i256.ll
+4,054-3,797126 files not shown
+8,122-8,041132 files

LLVM/project 952926c — llvm/lib/CodeGen CodeGenOptions.cpp CodeGenOptions.h, utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[CodeGen] Declare command line options in TableGen

Move the cl::opts of TargetPassConfig.cpp and CodeGenPrepare.cpp into
CodeGenOptions.td, private to lib/CodeGen; other files will follow.
-enable-machine-outliner (cl::ValueOptional) and -regalloc
(RegisterPassParser) stay cl::opt.

CodeGenPrepare and its addressing-mode helpers hold
`const CodeGenOptions &Opts`; TargetPassConfig functions read
CodeGenOptions::Global. getCGPassBuilderOption() converts BoolOrDefault
members to the cl::boolOrDefault and std::optional<bool> fields of the
public CGPassBuilderOption. -basic-block-section-match-infer, which was
not cl::Hidden, is now listed by -help-hidden only.

Aided by Opus 5.5
DeltaFile
+144-318llvm/lib/CodeGen/TargetPassConfig.cpp
+96-220llvm/lib/CodeGen/CodeGenPrepare.cpp
+199-0llvm/lib/CodeGen/CodeGenOptions.td
+19-0llvm/lib/CodeGen/CodeGenOptions.h
+15-0llvm/lib/CodeGen/CodeGenOptions.cpp
+11-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+484-5383 files not shown
+504-5439 files

LLVM/project f176c98 — llvm/lib/CodeGen CodeGenPrepare.cpp, llvm/test/CodeGen/AArch64 arm64-codegen-prepare-extload.ll

[CodeGenPrepare] Prefix option names with cgp-

Rename the CodeGenPrepare options so that they start with cgp-, and turn
the -disable-* options into positive options that default to true:

```
-addr-sink-*                  -cgp-addr-sink-*
-cgpp-huge-func               -cgp-huge-func
-disable-cgp-X                -cgp-X=0
-disable-complex-addr-modes   -cgp-complex-addr-modes=0
-disable-preheader-prot       -cgp-preheader-prot=0
-enable-andcmp-sinking        -cgp-andcmp-sinking
-force-split-store            -cgp-force-split-store
-stress-cgp-X                 -cgp-stress-X
```

The section prefix options (-profile-guided-section-prefix, etc.) are
kept, as they are not specific to CodeGenPrepare.

Aided by Opus 5.5
DeltaFile
+42-43llvm/lib/CodeGen/CodeGenPrepare.cpp
+3-3llvm/test/CodeGen/X86/sink-blockfreq.ll
+3-3llvm/test/CodeGen/X86/phi-immediate-factoring.ll
+2-2llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
+2-2llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
+2-2llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
+54-5550 files not shown
+109-11056 files

LLVM/project d30940d — llvm/include/llvm/ADT BoolOrDefault.h, llvm/include/llvm/Option LibraryOptions.h LibraryOptions.td

[Option] Add BoolOrDefault for OptionalBoolField and DefaultOnOffField (#228835)

The members of OptionalBoolField and DefaultOnOffField are
std::optional<bool>, on which `if (X)` tests whether the option is
given, not its value. Make them a new 1-byte `enum class BoolOrDefault :
uint8_t { Default, True, False }`, which does not convert to bool, and
read them with `valueOr(X, Default)`.

Aided by Opus 5.5
DeltaFile
+27-0llvm/include/llvm/ADT/BoolOrDefault.h
+15-8llvm/unittests/Option/LibraryOptionsTest.cpp
+10-7llvm/include/llvm/Option/LibraryOptions.td
+8-5llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+9-0llvm/include/llvm/Option/LibraryOptions.h
+4-4llvm/lib/MC/MCAsmInfo.cpp
+73-242 files not shown
+76-278 files

NetBSD/src GMpmXRB — sys/arch/xen/xen xbd_xenbus.c

   Use indirect transfers when possible.
   Split arbitrary larger transfers to support MAXPHYS > 64k.
VersionDeltaFile
1.137+182-93sys/arch/xen/xen/xbd_xenbus.c
+182-931 files

NetBSD/src O4EjEAy — sys/arch/xen/xen xbdback_xenbus.c

   Validate blkif_request_segment to not span page boundaries instead
   of checking for a specific size.
VersionDeltaFile
1.111+8-6sys/arch/xen/xen/xbdback_xenbus.c
+8-61 files

LLVM/project 7aaa263 — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+146-93mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+219-0llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll
+78-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+74-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+68-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24-31llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+609-12419 files not shown
+855-17925 files

LLVM/project 8b12013 — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

Tighten PR cross-references in commit messages

Created using spr 1.3.7
DeltaFile
+146-93mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+219-0llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll
+78-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+74-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+68-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24-31llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+609-12419 files not shown
+855-17925 files

LLVM/project c033951 — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

Tighten PR cross-references in commit messages

Created using spr 1.3.7
DeltaFile
+146-93mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+219-0llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll
+78-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+74-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+68-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24-31llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+609-12419 files not shown
+855-17925 files

LLVM/project 6b4b4b1 — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+146-93mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+219-0llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll
+78-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+74-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+68-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24-31llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+609-12419 files not shown
+855-17925 files

LLVM/project ae95049 — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

Tighten PR cross-references in commit messages

Created using spr 1.3.7
DeltaFile
+146-93mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+219-0llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll
+78-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+74-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+68-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24-31llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+609-12419 files not shown
+855-17925 files

LLVM/project d356a33 — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+146-93mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+219-0llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll
+78-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+74-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+68-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24-31llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+609-12419 files not shown
+855-17925 files

LLVM/project f22093c — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

Tighten PR cross-references in commit messages

Created using spr 1.3.7
DeltaFile
+146-93mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+219-0llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll
+78-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+74-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+68-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24-31llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+609-12419 files not shown
+855-17925 files

LLVM/project f41fdf1 — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+146-93mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+219-0llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll
+78-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+74-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+68-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24-31llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+609-12419 files not shown
+855-17925 files