[ProfCheck] Add option to inject profcheck into pipelines
This allows setting an option in clang and verifying that all profile
information is preserved. This allows for more thorough testing of
profile preservation on real code rather than just in the LLVM tests.
Reviewers: aeubanks, mtrofin
Pull Request: https://github.com/llvm/llvm-project/pull/232052
[Passes] Add helpers for start/end passes
This refactors out instructionCounters into more generic start/end pass
blocks. This refactoring makes it easier to add ProfCheck passes at
these points without needing to manually add them at all the relevant
points in the various pipelines.
Reviewers: aeubanks, mtrofin
Pull Request: https://github.com/llvm/llvm-project/pull/232032
[libc][regex] Switch ExprPool to 32-bit ExprId and 16B Expr (#230687)
Refactored the regex AST and ExprPool in libc/src/__support/regex/ to
reduce per-pool memory overhead:
* Replaced pointer-based AST references with 1-based 32-bit ExprId
indices (with singleton IDs EMPTY_SET_ID = 1 and EMPTY_STR_ID = 2).
* Compacted Expr to 16 bytes with a cached 32-bit hash and precomputed
nullability flag.
* Replaced the fixed 16,384-slot hash table and 256-node linked blocks
with a growable hash table starting at 64 slots (256 bytes) and 32-node
blocks (512 bytes), allocated lazily on first intern so a
default-constructed pool uses 0 heap bytes and initial allocation is 832
bytes.
* Migrated block and hash-table storage to cpp::array and cpp::span with
a BucketProber iterator range and centralized slot_at indexing.
Assisted-by: Automated tooling, human reviewed.
[asan] Mark nothrow operator new and delete noexcept (NFC) (#231994)
Add `NOEXCEPT` to nothrow forms of `operator new` and `operator delete`
definitions to make them standards compliant and compatible with
declarations provided by the, soon to be included in this context,
`<new>` header.
[AMDGPU][SIMemoryLegalizer] Lower single-wave workgroup scope to wavefront in absence of LDSDMA (#224065)
This patch lowers workgroup-scoped instructions to wavefront if the
kernel's maximum workgroup size is at most one wavefront, so long as the
kernel does not contain any LDS DMA operations, as these operations are
performed asynchronously relative to other LDS instructions. This is
just a partial reland of #187673 (which was originally reverted due to
this issue; see #207473) with an additional check for LDS DMA
instructions.
[AMDGPU][Attributor] Add attribute to track for LDSDMA invocations (#229133)
This patch adds the `amdgpu-no-lds-dma` attribute, which indicates that
the decorated function does not execute any LDSDMA operations.
This attribute is used in #224065 to enable demoting suitable workgroup
sync scopes to wavefront only when there are no LDSDMA operations
present.
[BoundsSafety][Sema] Disallow using a bitfield as the counter
A counter that's a pointer to a bitfield breaks assumptions that are
present in other features, like '__builtin_counted_by_ref', which
returns a pointer to the counter. A bitfield cannot have its address
taken causing an ICE.
diff: support -qq to output absolutely nothing
This is similar to `cmp -s`, but can be combined with:
-B --ignore-blank-lines
-b --ignore-space-change
-w --ignore-all-space
To only report a difference if it doesn't involve whitespace
Reviewed by: des, bapt, markj (previous version), ziaee (man page)
MFC after: 1 week
Sponsored by: Klara, Inc.
Differential Revision: https://reviews.freebsd.org/D46717
[AMDGPU] Fix sc1 encoding of gfx940 fp atomics with AGPR results
The *_F64 FLAT and GLOBAL atomics have separate VI and GFX940 reals,
because the VI reals are defined with has_sccb=0 and so do not encode
bit 25, which is SC1 on GFX940. However:
- #129668 removed the isGFX90AOnly predicate from the VI reals, so on
GFX940+ both the VI and GFX940 reals matched in the assembler. The
GFX940 ones happened to win because they were defined later.
- The GFX940 multiclasses did not define *_RTN_agpr reals, so the AGPR
forms of the returning atomics always used the VI reals on GFX940+.
The assembler silently dropped sc1 for these, the disassembler could
not decode them with sc1 set, and codegen dropped sc1 from the
*_RTN_agpr pseudos.
Fix this by adding *_RTN_agpr (and *_SADDR_RTN_agpr) reals to the GFX940
atomic multiclasses, and restricting the VI f64 reals to
isGFX8GFX9NotGFX940, like the neighbouring f32 and pk_f16 ones.
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[AMDGPU] Precommit tests for gfx942 fp atomics with AGPR results
Add MC, disassembler and codegen tests for FLAT and GLOBAL fp atomics on
gfx942 and gfx950, with more complete coverage of the f64 atomics on
gfx90a and gfx942.
The returning forms of {flat,global}_atomic_{add,min,max}_f64 with AGPR
operands currently use the *_RTN_agpr_vi reals on gfx942, which do not
encode bit 25 (SC1), so:
- the assembler silently drops sc1
- the disassembler fails to decode them with sc1 set
- codegen drops sc1 from the *_RTN_agpr pseudos
Similarly for global_atomic_add_f32 and global_atomic_pk_add_f16, where
codegen drops sc1 from the *_RTN_agpr pseudos, and the assembler and
disassembler reject the AGPR returning forms altogether.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
AMDGPU: Only add address space AAs for flat pointers
AMDGPUAttributor created AAAddressSpace and AANoAliasAddrSpace for the
pointer operand of every memory access. For a pointer that is not
flat, both are at an optimistic fixpoint after initialization and
manifest nothing, so only create them for flat pointers.
Instructions spent in amdgpu-attributor
(opt, parse cost subtracted, median of 3 runs):
rocPRIM test_device_scan, gfx942: 1963M -> 1404M (-28.5%)
Blender Cycles HIP kernel, gfx1100: 636M -> 459M (-27.8%)
rocPRIM 16 tests, full LTO, closed world: 7415M -> 5590M (-24.6%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[mlir] Fix abort on string token in integer dense tensor parsing (#231876)
`getIntAttrElements` asserted on `Token::string` because
`parseElement()`
accepts string tokens but the integer path only handled `floatliteral`
before asserting. Add an explicit emitError for string tokens, matching
the existing floatliteral handling pattern.
Fixes #228850.
[InstCombine] Shrink fast logarithm intrinsics to float (#228805)
Allow the existing unsafe double-to-float shrink for `llvm.log`,
`llvm.log2` and `llvm.log10`. The current libc availability check looks
for names such as `llvm.log10.f64f`, so it blocks intrinsic overloads.
Keep the existing fast-math, input-precision and result-use
requirements.
Motivated by LAME's `calc_noise`, where Clang calls double `log10` but
GCC calls `log10f`. On an M1 Pro, the actual LLVM patch reduces full
encoding from 5.965 s to 5.844 s (**2.0% less time**, five-round
medians), with byte-identical MP3 output in this benchmark.
Implemented with assistance from OpenAI Codex.
[alpha.webkit.MemoryUnsafeCastChecker] Use canonical decl to check identity of types (#231833)
The checker used equalsBoundNode to relate the source and destination
classes of a cast, which compares declaration nodes by identity. When
the two types refer to different redeclarations of the same class (e.g.
one spelled before and one after a `class X;` redeclaration following
the definition), same-type casts such as `const_cast<X*>(p)` and upcasts
were reported as casts to an unrelated type, and downcasts were reported
as unrelated rather than as base-to-derived casts.
Add an hasSameCanonicalDeclAsBoundNode matcher that compares canonical
declarations and use it in place of equalsBoundNode. Also compare
canonical declarations in the CRTP exclusion.
Co-authored with Claude.
