LLVM/project c3e55declang/test/Driver openmp-invalid-target-id.c

clang: Add OpenMP driver test for invalid target IDs

Submit test that already exists in the rocm fork. This stresses
the error cases when using the legacy OpenMP -march target specifier,
which appears to be missing upstream.
DeltaFile
+129-0clang/test/Driver/openmp-invalid-target-id.c
+129-01 files

LLVM/project 5b3b76elibcxx/docs ReleaseNotes.rst, libcxx/docs/ReleaseNotes 24.rst

[libc++] Create libc++ 24 release notes (#208814)

Now that the LLVM 23 branch has been created, this adds LLVM 24 release
notes. The release notes contain a few TODOs which will be easy to
address in separate PRs.
DeltaFile
+74-0libcxx/docs/ReleaseNotes/24.rst
+2-1libcxx/docs/ReleaseNotes.rst
+76-12 files

LLVM/project 8c9a6fdmlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Add support for block scaled types in matmul_t (#207851)

Builds on https://github.com/llvm/llvm-project/pull/203894 to enable
MXFP block scaled fotmats within matmul_t.
DeltaFile
+524-41mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+30-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+27-0mlir/test/Dialect/Tosa/ops.mlir
+16-6mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+9-5mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
+11-0mlir/test/Dialect/Tosa/invalid_extension.mlir
+617-525 files not shown
+649-5311 files

LLVM/project d3f58ceflang/lib/Optimizer/OpenACC/Support FIROpenACCTypeInterfaces.cpp

[flang][openacc][NFC] remove useAccReductionCombine cl switch (#208756)

Follow-up of https://github.com/llvm/llvm-project/pull/208473 to remove
the switch altogether to simplify the compiler code.
DeltaFile
+0-8flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
+0-81 files

LLVM/project 0dccfdcclang/lib/Driver SanitizerArgs.cpp

[clang][Driver] Remove duplicate KernelAddress sanitizer kind. NFC. (#209079)

Remove the duplicate `SanitizerKind::KernelAddress` entry from the list
of sanitizers incompatible with `TypeSanitizer`.

Found using clang-tidy, with check `misc-redundant-expression`
DeltaFile
+1-1clang/lib/Driver/SanitizerArgs.cpp
+1-11 files

LLVM/project 96a53b1llvm/include/llvm/Transforms/Vectorize SLPVectorizer.h, llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP] Support memory runtime alias checks

Vectorize straight-line code blocked by runtime-checkable may-alias
dependencies by versioning the block. Drop the deps, and if the tree is
profitable, emit base-object address-range overlap checks branching to a
vector fast path or an original-order scalar fallback.

Fixes #201534

Original Pull Request: https://github.com/llvm/llvm-project/pull/203631

Recommit after revert in a9ba4d3fd27a05b31adfeaab5dcd42d8e43c1931,
related to late commit before the release and small after-commit change
request

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/209305
DeltaFile
+824-17llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+315-0llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
+41-10llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
+13-0llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
+1,193-274 files

LLVM/project dadccf8clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp, clang/test/Sema/LifetimeSafety dangling-field.cpp

[LifetimeSafety] Suppress false field-escape warnings in destructors (#209614)
DeltaFile
+10-0clang/test/Sema/LifetimeSafety/dangling-field.cpp
+5-2clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+15-22 files

FreeNAS/freenas d85bdaasrc/middlewared/middlewared/plugins/container lifecycle.py, tests/api2 test_container_mknod.py

Inject mknod for privileged Allow-All containers

## Problem
A privileged container with `capabilities_policy` "ALLOW" keeps every capability in the bounding set, but libvirt only widens the LXC cgroup device ACL when an explicit `<mknod state='on'/>` child is emitted. As a result "Allow All" can't create device nodes, so Docker fails to extract images whose layers contain overlay whiteouts (character 0:0 nodes made via mknod) even though CAP_MKNOD is present.

## Solution
For privileged containers (idmap None) under an ALLOW policy, inject the mknod capability unless the user set it explicitly, so libvirt emits `<mknod state='on'/>` and widens the device ACL — making "Allow All" actually allow device-node creation. Adds an api2 integration test asserting such a container can mknod a device node, run under the container's own cgroup (via systemd-run) since that is where the device ACL applies.
DeltaFile
+60-0tests/api2/test_container_mknod.py
+15-0src/middlewared/middlewared/plugins/container/lifecycle.py
+75-02 files

LLVM/project 54e36d6llvm/lib/Target/SPIRV SPIRVUtils.cpp, llvm/lib/Target/SPIRV/MCTargetDesc SPIRVInstPrinter.cpp

[SPIR-V] Emit UniformId decoration as OpDecorateId with a Scope id operand (#207958)

Per spec, UniformId operand is a Scope `<id>`, not a literal

Previously it was printed via `printSymbolicOperand<ScopeOperand>`,
which asserts on a real id operand, and never emitted correctly
DeltaFile
+20-3llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+11-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/vk-ext-builtin-input.ll
+1-1llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+32-43 files

LLVM/project 72a7b7allvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-private.mir

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (44)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+14-14llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+9-9llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
+78-7894 files not shown
+350-350100 files

LLVM/project 386ac56llvm/test/CodeGen/AMDGPU/GlobalISel legalize-intrinsic-trunc.mir legalize-load-constant.mir

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (43)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
+36-3694 files not shown
+291-291100 files

LLVM/project b18267dllvm/test/CodeGen/AMDGPU/GlobalISel lds-misaligned-bug.ll inst-select-store-global.mir

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (42)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
+42-4294 files not shown
+281-281100 files

LLVM/project 428b49fllvm/test/CodeGen/AMDGPU/GlobalISel inst-select-amdgpu-atomic-cmpxchg-global.mir inst-select-load-global.mir

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (41)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
+45-4594 files not shown
+349-349100 files

LLVM/project e13d89dllvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f32.ll fdiv.f16.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (40)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
+57-5794 files not shown
+296-296100 files

LLVM/project 54be876llvm/test/CodeGen/AMDGPU/GlobalISel combine-fma-sub-mul.ll combine-fma-add-fma-mul.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (39)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
+47-4794 files not shown
+242-242100 files

LLVM/project 62799adllvm/test/CodeGen/AMDGPU xnack-subtarget-feature-any.ll xnack-subtarget-feature-disabled.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (38)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-any.ll
+7-7llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
+7-7llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
+5-5llvm/test/CodeGen/AMDGPU/xnor.ll
+4-4llvm/test/CodeGen/AMDGPU/xor_add.ll
+3-3llvm/test/CodeGen/AMDGPU/xor3.ll
+33-3313 files not shown
+54-5419 files

FreeBSD/ports 4631b1fmisc/freebsd-doc-de pkg-plist

misc/freebsd-doc-de: Really fix pkg-list

Reported by:    fluffy@

(cherry picked from commit a56a8b9216003b4b6a95a39905c3df8413370bd4)
DeltaFile
+1-0misc/freebsd-doc-de/pkg-plist
+1-01 files

FreeBSD/ports eec4de4misc/freebsd-doc-de pkg-plist

misc/freebsd-doc-de: Remove article

Approved by:    blanket (fix build)

(cherry picked from commit 5619310d6612e2e3eed1f842456fbccee9efc0f1)
DeltaFile
+0-1misc/freebsd-doc-de/pkg-plist
+0-11 files

LLVM/project 1d41488llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV strided-accesses.ll strided-accesses-unroll.ll

[VPlan] Fix nowrap flags for strided access pointers from SCEV (#209453)

This patch addresses two things. First, the offset calculation
(canonical IV * stride) should not reuse the NSW flag of the add
recurrence. The NSW property from SCEV for the original scalar
recurrence does not necessarily hold for the reconstructed
multiplication using the vector canonical IV. The NUW flag, however, can
still be safely propagated.
Second, because vputils::getGEPFlagsForPtr currently doesn't support
recipes other than VPInstruction, and to avoid relying on LLVM IR
function (like calling stripPointerCasts()), we change
VPVectorPointerRecipe's GEP flags to use the add recurrence's flags to
prevent propagating unprovable GEP flags like inbounds.
DeltaFile
+7-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+5-5llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+1-3llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
+13-153 files

LLVM/project ca71592flang/lib/Optimizer/Builder FIRBuilder.cpp, flang/test/HLFIR inline-hlfir-assign-self-copy.fir inline-hlfir-assign-self-copy-runtime-stride.fir

Reland "[Flang]Add support for inlining hlfir.assign operation where both LHS and RHS are slices of the same array #204532" (#208159)

Added support for inlining hlfir.assign when both LHS and RHS are slices
of the same array. When overlap between the slices cannot be determined,
the pass introduces a disjointness check:

- genIndexBasedDisjointnessCheck(..) is used when both sides are
sections of the same array.
- genAddressBasedDisjointnessCheck(..) used as a fallback for more
complex cases.

At runtime:

- If the slices are disjoint, a direct element-wise copy is performed
without allocating a temporary buffer.
- If overlap is possible, a temporary buffer is allocated, the RHS is
first copied into it and then the data is copied from the temporary
buffer to the LHS.

Fixes https://github.com/llvm/llvm-project/issues/203228
DeltaFile
+190-0flang/test/HLFIR/inline-hlfir-assign-self-copy.fir
+149-0flang/test/HLFIR/inline-hlfir-assign-self-copy-runtime-stride.fir
+140-0flang/test/HLFIR/inline-hlfir-assign-pointer-overlap.fir
+137-0flang/lib/Optimizer/Builder/FIRBuilder.cpp
+125-0flang/test/Lower/inline-hlfir-assign-pointer-omp.f90
+119-0flang/test/Lower/inline-hlfir-assign-forall-threadprivate.f90
+860-04 files not shown
+1,042-1410 files

LLVM/project 11cc8d8llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination transfer-signed-facts-to-unsigned.ll

[ConstraintElim] Transfer SLE facts to unsigned (#209623)

Handle SLE analogous to SLT via getUnsignedPredicate.

Alive2 Proof: https://alive2.llvm.org/ce/z/yNjmL8

PR: https://github.com/llvm/llvm-project/pull/209623
DeltaFile
+3-7llvm/test/Transforms/ConstraintElimination/transfer-signed-facts-to-unsigned.ll
+3-1llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+6-82 files

FreeNAS/freenas b081385src/middlewared/middlewared/plugins boot.py, src/middlewared/middlewared/plugins/boot __init__.py format.py

NAS-141768 / 27.0.0-BETA.1 / Convert boot plugin to typesafe pattern (#19296)

## Problem
The boot service was old-style dict-based code spread across three files
(boot.py, boot_/format.py, boot_/boot_loader.py) that all declared the
same BootService, so the framework silently merged them into a
CompoundService. None of it was type-checked end to end, and every
in-process consumer reached it through untyped string
middleware.call('boot.*').

## Solution
- Consolidate everything into a single plugins/boot/ package using the
port pattern: a lean BootService in __init__.py that delegates to plain,
fully type-annotated module functions in disks.py/format.py/pool_ops.py,
with @api_method(check_annotations=True) public methods and @private
stubs. boot.get_state now returns a BootGetState model; internal callers
use a dict state helper so nothing breaks on attribute-vs-key access.
- Register boot in main.py's ServiceContainer and have it own
boot.environment as a sub-service, replacing BootServicesContainer.

    [17 lines not shown]
DeltaFile
+0-372src/middlewared/middlewared/plugins/boot.py
+182-0src/middlewared/middlewared/plugins/boot/__init__.py
+160-0src/middlewared/middlewared/plugins/boot/format.py
+160-0src/middlewared/middlewared/plugins/boot/pool_ops.py
+0-115src/middlewared/middlewared/plugins/boot_/format.py
+99-0src/middlewared/middlewared/utils/boot/pool.py
+601-48748 files not shown
+863-60054 files

LLVM/project f96628dclang/lib/Driver OffloadBundler.cpp

clang-offload-bundler: Reduce include of Cuda.h to OffloadArch.h (#209723)

This was only using OffloadArch, so use that header directly.
DeltaFile
+1-1clang/lib/Driver/OffloadBundler.cpp
+1-11 files

OpenBSD/src w54slFXusr.sbin/bgpd rde_filter.c

   NULL not 0 for last arg to community_match() since it is a pointer.
VersionDeltaFile
1.150+2-2usr.sbin/bgpd/rde_filter.c
+2-21 files

LLVM/project 0f24969clang/docs ReleaseNotes.md, clang/lib/Sema SemaAMDGPU.cpp

[Clang][AMDGPU] Deprecate icmp/fcmp builtins in favor of ballot (#209416)

Deprecate these builtins with a warning recommending
__builtin_amdgcn_ballot_w32 or __builtin_amdgcn_ballot_w64 instead:
  __builtin_amdgcn_uicmp
  __builtin_amdgcn_uicmpl
  __builtin_amdgcn_sicmp
  __builtin_amdgcn_sicmpl
  __builtin_amdgcn_fcmp
  __builtin_amdgcn_fcmpf

Assisted-by: Claude Opus 4.8
DeltaFile
+52-0clang/test/SemaOpenCL/builtins-amdgcn-cmp-deprecated.cl
+17-0clang/lib/Sema/SemaAMDGPU.cpp
+8-0clang/docs/ReleaseNotes.md
+77-03 files

LLVM/project a636e09lldb/test/API/commands/frame/var-dil/expr/Literals main.cpp TestFrameVarDILLiterals.py, lldb/test/API/commands/frame/var-dil/expr/NullptrVar TestFrameVarDILNullptrVar.py main.c

Add a test for a nullptr variable
DeltaFile
+24-0lldb/test/API/commands/frame/var-dil/expr/NullptrVar/TestFrameVarDILNullptrVar.py
+7-0lldb/test/API/commands/frame/var-dil/expr/NullptrVar/main.c
+4-0lldb/test/API/commands/frame/var-dil/expr/NullptrVar/Makefile
+3-1lldb/test/API/commands/frame/var-dil/expr/Literals/main.cpp
+1-1lldb/test/API/commands/frame/var-dil/expr/Literals/TestFrameVarDILLiterals.py
+39-25 files

LLVM/project 6b3b6a8lldb/include/lldb/Target StackID.h, lldb/source/Target StackID.cpp ThreadPlanStepOut.cpp

[lldb][NFC] Create StackID::IsYounger (#209402)

Currently, StackIDs are compared with a custom operator <. There are
some issues with that:
1. It's not clear what "<" means in this context. It really is a test of
"frame A is on top of frame B or not comparable". But this notion is not
expressed through "<".
2. This is not a real operator "<" in the sense that if "!<" does not
imply ">=". In particular, frames may not always be comparable (i.e.
(they are not part of the same stack).

To address these issues, this commit replaces `<` with a custom function
"IsYounger", which makes explicit what is being tested.
DeltaFile
+5-5lldb/source/Target/StackID.cpp
+5-4lldb/include/lldb/Target/StackID.h
+4-4lldb/source/Target/ThreadPlanStepOut.cpp
+3-2lldb/source/Target/ThreadPlanStepInstruction.cpp
+2-2lldb/source/Target/ThreadPlanStepUntil.cpp
+1-1lldb/source/Target/StackFrameList.cpp
+20-181 files not shown
+21-197 files

LLVM/project c58ba1cllvm/test/CodeGen/AMDGPU vopd-combine.mir wave_dispatch_regs.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (37) (#209601)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/vopd-combine.mir
+6-6llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
+6-6llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
+6-6llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
+5-5llvm/test/CodeGen/AMDGPU/wave32.ll
+5-5llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+35-3592 files not shown
+196-19698 files

LLVM/project d0a85f5llvm/test/CodeGen/AMDGPU vector-reduce-fmax.ll vector-reduce-fmin.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (36) (#209600)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+20-20llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+20-20llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+16-16llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+16-16llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+16-16llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+16-16llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
+104-10493 files not shown
+442-44299 files

LLVM/project 083acc3clang/lib/AST/ByteCode Interp.cpp Pointer.h, clang/test/AST/ByteCode cxx2a.cpp

[clang][bytecode] Fix uninitialized diagnostics (#209702)

... if the pointer is also outside its lifetime. In that case, prefer to
diagnose it as outside its lifetime.
DeltaFile
+13-11clang/lib/AST/ByteCode/Interp.cpp
+1-17clang/lib/AST/ByteCode/Pointer.h
+8-7clang/lib/AST/ByteCode/Interp.h
+12-0clang/test/AST/ByteCode/cxx2a.cpp
+34-354 files