[SPIR-V] Avoid crash on malformed mangled builtin name length (#207939)
Replace the assert on invalid length parsing with a graceful bail-out
since malformed names can potentially come from outside, it is not
necessarily always an error
All usages of `getOclOrSpirvBuiltinDemangledName` are being checked for
emptiness where it is needed anyway
[Clang] Fix null-pointer assertion reading CtorClosureDefaultArgs (#207917)
BuildCtorClosureDefaultArgs deliberately leaves the first default-arg
slot null for MS ABI copy-constructor closures (the closure itself
supplies that argument), and ASTWriterDecl.cpp serializes the null. But
e7924d50db0a deserialized it with cast<>, which asserts on null. This
only triggers under the MS C++ ABI, e.g. when throwing a class with a
non-trivial copy constructor by value across a PCH boundary, as in test
https://github.com/intel/llvm/blob/cb9b7b7/clang-tools-extra/clangd/test/sycl.test
Assisted by: Claude
AMDGPU: Replace tgsplit subtarget feature with attribute (#204216)
This is a per-entrypoint property and has a corresponding
assembler directive, so it should not be baked into the
subtarget. I couldn't find much documentation on what this
actually does, so the description isn't great.
Fixes #204149
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
[clang][bytecode] Add more checks for pseudo dtors (#207959)
Rename the `EndLifetimePop` op (which was only used for pseudo dtors) to
`PseudoDtor` and call `checkDestructor()` in there, so we get the full
suite of checks.
[libc] Implement if_nametoindex and if_indextoname (#206082)
This patch implements if_nametoindex and if_indextoname for Linux.
Both functions work by creating a temporary AF_UNIX socket and issuing
ioctl calls (SIOCGIFINDEX and SIOCGIFNAME, respectively).
The main implementation details:
- for if_nametoindex, I check that the interface name fits within
IF_NAMESIZE before issuing the ioctl
- for if_indextoname, if the kernel returns ENODEV for an unknown index,
I map it to ENXIO to comply with POSIX requirements
- added the definition of struct ifreq to support these operations.
Similar to the other net structure definitions, I'm using an anonymous
union to avoid #defining members.
Assisted by Gemini.
mlx5: propagate the DEVX uid through SRQ create and destroy
The SRQ command builders never stamped the owning DEVX uid into the
firmware CREATE_SRQ/CREATE_RMP/CREATE_XRC_SRQ commands, so a basic SRQ
was always created with uid 0. Every modern libmlx5 context runs with a
DEVX uid, and the QPs that reference the SRQ carry that uid, so firmware
rejected CREATE_QP with "bad resource": a uid-owned QP may not reference
a uid-0 SRQ.
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5: guard against a NULL CQ event handler in mlx5_cq_event()
DEVX and mlx5en created CQs are registered without an asynchronous
event handler (mcq.event is NULL). An asynchronous CQ_ERROR event for
such a CQ made mlx5_cq_event() call through a NULL pointer and panic.
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5: pass the full EQE to the DEVX event notifier
The DEVX event notifier and its helpers expect a full struct mlx5_eqe
and read eqe->data from it, but mlx5_eq_int() passed &eqe->data, so the
data offset was applied twice.
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
ofed/ib_uverbs: release rdma_user_mmap entry ref in rdma_umap_close()
Import Linux upstream commit 3411f9f01b76bd88aa6e0e013847ab6479cb4f24.
rdma_umap_priv_init() takes a reference on the rdma_user_mmap entry for
every VMA it maps, but rdma_umap_close() never dropped it. The entry
was therefore never freed and lingered in ucontext->mmap_xa, tripping
WARN_ON(!xa_empty(&ucontext->mmap_xa)) at context teardown and leaking
the firmware UAR on every context close.
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5ib: advertise write-combining support for dynamic BlueFlame UARs
Import Linux upstream commit 1f3db161881b7e21efb149e0ae8152b79a571a8f.
dev->wc_support was never set, so it was always false and the UAR ioctl
refused BlueFlame (write-combining) UAR allocations with EOPNOTSUPP.
That breaks QP creation in pure dynamic-UAR mode, where user space asks
for a BF doorbell UAR.
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5ib: encode dynamic UAR mmap offsets in the reserved command range
The UAR ioctl handed user space a raw mmap offset, so the first dynamic
UAR landed at page offset 0. mlx5_ib_mmap() decodes offset 0 as the
legacy regular-page command and routed the mapping through the old bfreg
path, which rejects dynamic-UAR contexts, so mmap() failed with EINVAL
and mlx5dv_devx_alloc_uar() returned NULL.
Follow the upstream scheme: reserve the mmap command range [9, 255] for
rdma_user_mmap entries and return command-encoded offsets, so the
dynamic-UAR mappings decode to the intended mlx5_ib_mmap() path.
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5ib: allocate IB queue counters as a shared resource
A QP owned by a DEVX uid references the port's queue counter. The
counter was allocated with uid 0, so RST2INIT_QP on a uid-owned QP
failed with "bad resource state".
Allocate and free the IB queue counters directly and, on devices that
support user contexts, stamp them with MLX5_SHARED_RESOURCE_UID so
uid-owned QPs can use them.
The code follows the Linux commit d2c8a1554c10d5e0443b1f97f480d7dacd55cf55
("IB/mlx5: Enable UAR to have DevX UID").
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5: mark completion EQs as a shared resource for DEVX uids
A firmware object owned by a DEVX uid may only reference resources owned
by the same uid or ones explicitly marked as shared. Completion EQs
were created with uid 0, so a CQ owned by a DEVX uid could not attach to
its EQ and CREATE_CQ failed with "bad resource".
Create completion EQs with MLX5_SHARED_RESOURCE_UID on devices that
support user contexts, so uid-owned CQs can use them.
The code follows the Linux commit d2c8a1554c10d5e0443b1f97f480d7dacd55cf55
("IB/mlx5: Enable UAR to have DevX UID").
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5ib: implement the MLX5_IB_OBJECT_UAR ioctl object
Import Linux upstream commit 342ee59de98a2ecdf15a46849a2534e7c808eb1f.
The dynamic UAR object was declared in the ABI headers but had no handler,
so the ioctl was rejected and dynamic-UAR contexts could not allocate a
doorbell UAR at all.
Implement the alloc and destroy methods following the upstream driver:
grab a UAR stamped with the caller's DEVX uid, expose it to user space
through an rdma_user_mmap entry (write-combining or non-cached as
requested), and free it on destroy.
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5_ib: register DEVX objects in the uverbs ioctl parse tree
Import Linux upstream commits a8b92ca1b0e5ce620e425e9d2f89ce44f1a82a82
and c59450c463695a016e823175bac421cff219935d.
The DEVX object and method definitions were already present, but nothing
pointed ib_device.driver_def at them. ibcore therefore never merged
them into the uverbs uapi tree and every DEVX ioctl came back as
EPROTONOSUPPORT.
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5_ib: do not consume CMD/PAGE_REQUEST events in the DEVX notifier
DEVX event notifier returned true for the command-completion and
page-request events. This is causing mlx5_eq_int() to skip the core EQ
handler, so the firmware command interface and the page supply stop
being serviced and the device wedges.
This commit also make notifier registration and dispatch safe against
the EQ interrupt running concurrently: publish the table pointer before
the callback and load it with acquire semantics. run the callback under
RCU, and drain it with synchronize_rcu() on teardown. Otherwise the
interrupt handler could observe a half-initialized notifier or race with
cleanup.
Reviewed by: kib
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
mlx5: extend mlx5_ib_create_cq struct with fields from the current Linux ABI
This is backward ABI-compatible, because the only place in kernel that
uses the structure, namely the mlx5_ib_cq.c:mlx5_ib_create_cq()
function, copies in as much structure members as provided by userspace.
Tested by: Wafa Hamzah <wafah at nvidia.com>
Sponsored by: Nvidia networking
MFC after: 1 month
[clang][bytecode] Fix getting typeid pointers of struct fields (#207946)
`getDeclPtr()` will return the declaration pointer, which might be
unrelated to the pointer we actually care about.
[NFC][mlir][bufferization] Align alloc/memcpy/cast options hooks to the rest (#206966)
There are three hooks that have a different, more complicated API than
the other ones: allocationFn, memCpyFn, castFn. All three are called via
"helper" functions that check whether the hooks are set to call them and
fall back to default implementations otherwise.
Other hooks (e.g. unknownTypeConverterFn) in the bufferization options
have a different "API": they are always set to some default
implementation and can be overwritten by the user. This is a simpler API
overall and seems it can be universal.
Note for LLVM integration: BufferizationOptions::{createAlloc,
createMemCpy, createCast} functions are "replaced" with direct calls to
the underlying std::function objects. At any call-site that relied on
any of the removed APIs, a call to the respective hook should now be
used instead. The exception is the `allocationFn` hook which needs an
explicit "bufferAlignment" parameter. Beforehand, it was implicitly
taken from BufferizationOptions::bufferAlignment field, so a
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[libc] Add inet_ntop (#204143)
The function converts from IPv4/6 addresses to their string forms. The
complication comes from the v6 part due to address compression and
v4-mapping.
The traditional implementation of this is to sprintf the address into a
temporary buffer. We cannot do that here due to the ban on calling other
entry points. Using the lower-level constructs is possible, but a
straight forward application of IntegerToString does not result in
particularly impressive performance: 50%-100% slower than what's in this
patch (and slower than glibc). It also doesn't make the code much
smaller as the majority of it is dedicated to v6 compression.
The IPv6 implementation uses a temporary buffer, but it also has a
fast-path which skips the buffer if its size is guaranteed to be
sufficient. The IPv4 implementation also has a fast path, but the
fallback here is to compute the precise length of the string instead
(the buffer option was slower and IPv4 makes it easier to compute the
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[AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to 0 <= Zn <= 7
The `luti6` instruction (table, four registers, 8-bit) should only
allow `0 <= Zn <= 7`, since there's only 3 bits. It actually allows:
```
luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```
Fix tablegen to ensure Zn is only allowed in correct range of 0 to 7.
[AMDGPU] Save entry EXEC in whole-wave prologue with no WWM spills (#207924)
PR #207781 replaced the prologue S_XOR_SAVEEXEC (which set EXEC to
~entryEXEC) with a plain S_MOV EXEC, -1, but dropped the save of the
entry EXEC that the return restores from, leaving an undefined register
read
se S_OR_SAVEEXEC to both save entry EXEC and set EXEC to -1
