FreeBSD/ports edb2f38biology/p5-transdecoder Makefile

biology/p5-transdecoder: Change WWW for portscout

Portscount doesn't seem to find it's way past github.io pages, so
changed WWW to the main github project page.
DeltaFile
+1-1biology/p5-transdecoder/Makefile
+1-11 files

FreeBSD/ports 052ca3fwww/code-server/files EXTENSIONS.md

www/code-server: Update EXTENSIONS.md

Add a section about switching the display language: language packs
must be installed through the Extensions view (the standalone CLI
does not register them), and the packs on Open VSX can lag behind
the bundled VS Code version.

Sponsored by:   Netzkommune GmbH
DeltaFile
+12-0www/code-server/files/EXTENSIONS.md
+12-01 files

LLVM/project cbbdbfcclang/test/Frontend optimization-remark-target-features-arm.c optimization-remark-target-features-aarch64.c, llvm/lib/CodeGen MachineFunction.cpp

[llc] add target-features optimization remark

In clang we have --print-enabled-extensions which will print the
AArch64 extensions enabled for a given TU. However, sometimes it is
useful to be able to print out the actual subtarget features for each
function, for debugging/testing purposes. Add an optimization remark
for that.
DeltaFile
+45-0llvm/test/CodeGen/AArch64/optimization-remark-target-features.ll
+30-0clang/test/Frontend/optimization-remark-target-features-aarch64.c
+30-0llvm/test/CodeGen/ARM/optimization-remark-target-features.ll
+19-0clang/test/Frontend/optimization-remark-target-features-arm.c
+17-0llvm/lib/CodeGen/MachineFunction.cpp
+1-1llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
+142-16 files

FreeBSD/ports 0756c83biology/p5-transdecoder pkg-plist distinfo

biology/p5-transdecoder: Update to 6.0.0

Add single entry point wrapper script and a couple new options
Changes: https://github.com/TransDecoder/TransDecoder/releases

Reported by:    Repology
DeltaFile
+5-3biology/p5-transdecoder/Makefile
+3-3biology/p5-transdecoder/distinfo
+1-0biology/p5-transdecoder/pkg-plist
+9-63 files

LLVM/project fee4360clang/include/clang/CIR/Dialect/IR CIRTypes.td, clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp

[CIR][NFC] Rewrite two comments based on reviewer feedback

Assisted-by: Cursor / claude-opus-5
DeltaFile
+4-10clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+3-7clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+7-172 files

FreeNAS/freenas 6ed2575src/middlewared/middlewared/alembic/versions/26.0 2026-09-03_15-00_truenas_s3_service.py 2026-09-08_18-00_truenas_s3_object_ownership.py

Fold object_ownership into the S3 service migration

The column is added where the table is created rather than altered
onto it a revision later: neither has shipped, so the pair of
migrations only asks a fresh install to make and then rewrite a
column it has no rows in.
DeltaFile
+0-54src/middlewared/middlewared/alembic/versions/26.0/2026-09-08_18-00_truenas_s3_object_ownership.py
+1-0src/middlewared/middlewared/alembic/versions/26.0/2026-09-03_15-00_truenas_s3_service.py
+1-542 files

FreeNAS/freenas 60def41src/middlewared/middlewared/plugins network.py, src/middlewared/middlewared/plugins/interface sync.py bridge.py

Fail interface.commit when a bridge member cannot be added, and reject members that host a VM or container NIC in MACVLAN mode
DeltaFile
+45-11src/middlewared/middlewared/plugins/interface/bridge.py
+51-0src/middlewared/middlewared/pytest/unit/plugins/test_interface.py
+51-0tests/api2/test_interface_bridge_member_busy.py
+49-0src/middlewared/middlewared/pytest/unit/plugins/test_interface_bridge_sync.py
+35-2src/middlewared/middlewared/plugins/network.py
+4-4src/middlewared/middlewared/plugins/interface/sync.py
+235-176 files

LLVM/project 08add38llvm/lib/CodeGen MachineLICM.cpp, llvm/test/CodeGen/X86 machinelicm-hoist-before-succ-args.mir

MachineLICM: Fix preheader insertion point with SUCC_ARGS

Hoist loop-invariant instructions to getBlockEndInsertPt() instead of
getFirstTerminator(), so they land before the SUCC_ARGS cluster rather
than inside it.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+48-0llvm/test/CodeGen/X86/machinelicm-hoist-before-succ-args.mir
+2-2llvm/lib/CodeGen/MachineLICM.cpp
+50-22 files

LLVM/project 42c0fb1llvm/lib/CodeGen MachineCSE.cpp, llvm/test/CodeGen/PowerPC machine-cse-pre-succ-args.mir

CodeGen: Fix MachineCSE PRE insert point with SUCC_ARGS

Hoist to getBlockEndInsertPt() instead of getFirstTerminator(), so a hoisted
instruction lands before the SUCC_ARGS cluster rather than inside it.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+99-0llvm/test/CodeGen/PowerPC/machine-cse-pre-succ-args.mir
+1-1llvm/lib/CodeGen/MachineCSE.cpp
+100-12 files

LLVM/project 7024b9eclang/lib/CIR/CodeGen CIRGenExprScalar.cpp, clang/test/CIR/CodeGen vector-strict-fp.cpp

[CIR] Support fp strict for vector logical and, or ops (#221808)

Support fp strict for vector logical `cir.or` and `cir.and` ops
DeltaFile
+88-8clang/test/CIR/CodeGen/vector-strict-fp.cpp
+6-10clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+94-182 files

LLVM/project b33a076llvm/include/llvm/CodeGen MachineBasicBlock.h, llvm/lib/CodeGen MachineVerifier.cpp

CodeGen: Add SUCC_ARGS pseudo-instruction

The sender half of a block-argument representation for Machine IR: a
"reverse PHI" that forwards values from a predecessor's bottom to a
successor block's arguments along one CFG edge. Operand 0 is the successor
block; the rest are the forwarded value registers, mapped positionally.

Like PHI, SUCC_ARGS is edge-specific: it must stay in its block, so it is
excluded from CSE and hoisting, and it defines no register but is not dead.
SUCC_ARGS are clustered contiguously immediately before the terminators,
mirroring how PHIs are clustered at the top of a block; the verifier
enforces this and the succ_args() range and getBlockEndInsertPt() let
consumers work with the cluster. Inert; no producer emits it yet.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+40-0llvm/test/CodeGen/MIR/X86/succ-args.mir
+38-0llvm/include/llvm/CodeGen/MachineBasicBlock.h
+34-0llvm/test/CodeGen/X86/machine-cse-succ-args.mir
+33-0llvm/test/MachineVerifier/X86/succ-args-empty.mir
+29-0llvm/test/CodeGen/X86/machinelicm-succ-args.mir
+27-0llvm/lib/CodeGen/MachineVerifier.cpp
+201-014 files not shown
+345-820 files

LLVM/project 19059d6llvm/lib/CodeGen MachineBasicBlock.cpp MachineVerifier.cpp, llvm/lib/CodeGen/MIRParser MIParser.cpp

CodeGen: Represent block arguments on MachineBasicBlock

The receiver half of the block-argument representation: a block declares a list
of virtual registers that receive values forwarded by each predecessor's
SUCC_ARGS. Unlike a PHI, a block argument is defined by the block itself, not by
an instruction.

MachineBasicBlock holds the argument list, printed and parsed as an "arguments:"
block header line. MachineRegisterInfo maps each argument to its defining block,
so getDefBlock works for these registers. The verifier treats an argument as
defined at block entry and requires each predecessor to supply one matching
SUCC_ARGS.

This is only building infrastructure, and is not yet used.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+131-0llvm/test/CodeGen/MIR/X86/block-args.mir
+53-0llvm/test/CodeGen/MIR/X86/block-args-invalid.mir
+48-2llvm/lib/CodeGen/MachineVerifier.cpp
+37-0llvm/lib/CodeGen/MIRParser/MIParser.cpp
+33-0llvm/lib/CodeGen/MachineBasicBlock.cpp
+32-0llvm/test/CodeGen/MIR/X86/block-args-named-blocks.mir
+334-213 files not shown
+539-619 files

LLVM/project 542ba89llvm/include/llvm/CodeGen MIRYamlMapping.h MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp MIRPrinter.cpp

CodeGen: Add UsesBlockArgs MachineFunction property

Bringup guard for block argument support.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+20-0llvm/test/CodeGen/MIR/X86/uses-block-args-property.mir
+3-1llvm/include/llvm/CodeGen/MachineFunction.h
+2-0llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+2-0llvm/include/llvm/CodeGen/MIRYamlMapping.h
+1-0llvm/lib/CodeGen/MachineFunction.cpp
+1-0llvm/lib/CodeGen/MIRPrinter.cpp
+29-16 files

LLVM/project f91b6a0llvm/lib/Target/PowerPC PPCVSXSwapRemoval.cpp, llvm/test/CodeGen/PowerPC vsx-swap-removal-undef.mir

PowerPC: Fix VSX swap removal crash on an undef register (#216714)

formWebs walks each vector-register use and unions its equivalence class
with that of its defining instruction, which it requires to be present
in the swap map. A use of an undef register has no defining instruction, so
the web formation crashed. Treat it like a physical-register mention so the
web is conservatively rejected.

Found by AI while working on something else.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+21-0llvm/test/CodeGen/PowerPC/vsx-swap-removal-undef.mir
+13-5llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
+34-52 files

LLVM/project ede01delibc/lib CMakeLists.txt

[libc] Generate a stub for libdl.a (#222098)

Avoid link errors when build rules explicitly add `-ldl` to the linker
invocation -
create an empty `libdl.a` static archive on Linux. It's necessary, for
example,
to build Clang (https://github.com/llvm/llvm-project/issues/97191) 

Follow the approach from f88e9de37a52abf9b269a7232bf4d4028bc4ace8
which added a similar stub for `libpthread.a`. Like pthread, dynamic
loader
functions (although they are mostly unimplemented in LLVM-libc as of
today)
are residing in the main `libc.a` archive instead.
DeltaFile
+1-1libc/lib/CMakeLists.txt
+1-11 files

LLVM/project 0f71c2dclang/test/OpenMP teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp, llvm/test/CodeGen/AArch64 arm64-big-endian-bitconverts.ll arm64-xaluo.ll

Merge branch 'main' into users/jmmartinez/build_shared_orc
DeltaFile
+4,997-0llvm/test/CodeGen/AArch64/overflow-vec.ll
+1,653-1,679llvm/test/CodeGen/AArch64/arm64-xaluo.ll
+1,299-431llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
+1,503-0llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll
+588-588clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+568-568clang/test/OpenMP/teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+10,608-3,266242 files not shown
+18,769-7,841248 files

LLVM/project 220294cllvm/lib/Transforms/Vectorize VPlan.h

[VPlan] Remove VPWidenInductionRecipe::getStartValue (NFC). (#222015)

It now shadows VPHeaderPHIRecipe::getStartValue, which returns the same
VPValue and, as the base class accessor, also has a non-const overload.
Narrowing the return type to VPIRValue * was its only purpose.
DeltaFile
+0-3llvm/lib/Transforms/Vectorize/VPlan.h
+0-31 files

LLVM/project 4afa58elldb/source/Utility ArchSpec.cpp, lldb/unittests/Utility ArchSpecTest.cpp

[lldb] Fix infinite recursion in ArchSpec's core matching (#221899)

`target create` never returns for a little-endian 32-bit MIPS ELF file,
on any host whose platform advertises `armv7m`/`armv7em` compatibility.
On Darwin that is every platform, since
`PlatformDarwin::GetCompatibleArchs()`
lists both for every arm64/arm64e host and falls through to that same
list
for any other host core.  It is found by `lldb-target-fuzzer`.

Reproduce with a 52-byte ELF32 header (`ELFCLASS32`, `ELFDATA2LSB`,
`e_machine = EM_MIPS`, `e_flags = EF_MIPS_ARCH_32`, everything else
zero),
saved as `mips32el.elf`:

```
(lldb) target create mips32el.elf
```


    [62 lines not shown]
DeltaFile
+17-25lldb/source/Utility/ArchSpec.cpp
+40-0lldb/unittests/Utility/ArchSpecTest.cpp
+57-252 files

LLVM/project 6a77c91llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/AArch64 scalar-steps-cost.ll

[VPlan] Don't cost scalar IV steps if the vector body runs at most once. (#221974)

If the vector loop executes exactly once, each scalar IV step folds to a
constant, and there's nothing to cost.

Similarly to BranchOnCount and VPRegionBlock::cost, treat
VPScalarIVSteps as free in that case.

This fixes a slight inaccuracy introduced when moving to computing
VPScalarIVSteps costs in VPlan directly.

PR: https://github.com/llvm/llvm-project/pull/221974
DeltaFile
+5-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1-1llvm/test/Transforms/LoopVectorize/AArch64/scalar-steps-cost.ll
+6-12 files

LLVM/project e4c2498llvm/lib/Target/SystemZ/MCTargetDesc SystemZHLASMAsmStreamer.cpp, llvm/test/CodeGen/SystemZ zos-ppa1.ll mixed-ptr-sizes.ll

[SystemZ][z/OS] Emit alignment in HLASM syntax

While trying to understand a crash, I noted that the emitted alignment
in HLASM is wrong. There are 2 issues:

 - The decision which suffix to use looks at `FillLen` instead of
   `Alignment`
 - The label alignment `DS 0H` is hard-coded

This change fixes the issues. To get the correct suffix for the
label alignment, the emission of the alignment is postponed in
certain cases, and the label definition picks up the alignment
suffix.
DeltaFile
+64-41llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+45-45llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+42-42llvm/test/CodeGen/SystemZ/call-zos-01.ll
+35-35llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
+17-17llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
+14-17llvm/test/CodeGen/SystemZ/zos-ppa1.ll
+217-19721 files not shown
+288-26227 files

FreeBSD/ports a89bae3www/reproxy distinfo Makefile

www/reproxy: the port had been updated to the latest version 1.7.1

Stop sed(1)-patching `main.go' and pass appropriate `main.revision'
via GO_LDFLAGS instead.

Reported by:    portscout
DeltaFile
+2-6www/reproxy/Makefile
+3-3www/reproxy/distinfo
+5-92 files

FreeBSD/doc f046385website/data/ru/news news.toml

website: update ru/news
DeltaFile
+5-0website/data/ru/news/news.toml
+5-01 files

LLVM/project 57e1aecoffload/plugins-nextgen/amdgpu/src rtl.cpp, offload/plugins-nextgen/common/include PluginInterface.h

implement feedback
DeltaFile
+5-4offload/plugins-nextgen/amdgpu/src/rtl.cpp
+3-1offload/plugins-nextgen/common/include/PluginInterface.h
+8-52 files

NetBSD/pkgsrc UAoRL1Ndoc TODO CHANGES-2026

   Updated www/py-zensical, devel/py-test-env
VersionDeltaFile
1.5948+3-1doc/CHANGES-2026
1.27876+1-2doc/TODO
+4-32 files

FreeNAS/freenas 49bd952src/middlewared/middlewared/plugins network.py, src/middlewared/middlewared/plugins/interface sync.py bridge.py

Fail interface.commit when a bridge member cannot be added, and reject members that host a VM or container NIC in MACVLAN mode
DeltaFile
+83-2src/middlewared/middlewared/pytest/unit/plugins/test_interface.py
+69-0src/middlewared/middlewared/pytest/unit/plugins/test_interface_bridge_sync.py
+45-11src/middlewared/middlewared/plugins/interface/bridge.py
+51-0tests/api2/test_interface_bridge_member_busy.py
+35-2src/middlewared/middlewared/plugins/network.py
+4-4src/middlewared/middlewared/plugins/interface/sync.py
+287-196 files

NetBSD/pkgsrc pXcREcUdevel/py-test-env Makefile distinfo

   py-test-env: updated to 1.7.1

   1.7.1
   Unknown changes
VersionDeltaFile
1.17+4-4devel/py-test-env/distinfo
1.17+2-2devel/py-test-env/Makefile
+6-62 files

NetBSD/pkgsrc ys4q5OTwww/py-zensical ALTERNATIVES

   py-zensical: added ALTERNATIVES
VersionDeltaFile
1.1+1-0www/py-zensical/ALTERNATIVES
+1-01 files

OpenBSD/ports xmicH4jtextproc/simdutf Makefile distinfo

   textproc/simdutf: Update to 9.1.1
VersionDeltaFile
1.9+2-2textproc/simdutf/distinfo
1.10+1-1textproc/simdutf/Makefile
+3-32 files

FreeBSD/ports 0fd1759net/td-system-tools Makefile distinfo

net/td-system-tools: Update 2.7.11 => 2.7.14

Changelog:
https://github.com/dreibh/system-tools/blob/td-system-tools-2.7.14/ChangeLog

Commit log:
https://github.com/dreibh/system-tools/compare/td-system-tools-2.7.11...td-system-tools-2.7.14

PR:             298315
Approved by:    osa, vvd (Mentors, implicit)
DeltaFile
+3-3net/td-system-tools/distinfo
+1-1net/td-system-tools/Makefile
+4-42 files

NetBSD/pkgsrc Xd8aArdwww/py-zensical Makefile PLIST, www/py-zensical/patches patch-Cargo.toml

   py-zensical: updated to 0.0.60

   0.0.60
   This version updates the user interface to 0.0.28, fixing navigation pruning
   and alternate-link handling while adding 51 new icons. It also adds direct
   support for the table-reader plugin and fixes template inclusion with macros on
   Windows extended-length paths.
VersionDeltaFile
1.11+353-31www/py-zensical/distinfo
1.7+115-9www/py-zensical/cargo-depends.mk
1.8+62-8www/py-zensical/PLIST
1.1+16-0www/py-zensical/patches/patch-Cargo.toml
1.12+10-3www/py-zensical/Makefile
+556-515 files