LLVM/project 72611fcllvm/test/CodeGen/AMDGPU/GlobalISel combine-binop-s64-with-s32-mask.mir

[AMDGPU] Fix combine-binop-s64-with-s32-mask.mir input to use i32 instead of s32 (NFC) (#217410)

With extended LLTs s32 and i32 compare equal, so the unconditional
setType could silently retype a register behind the CSE map

This fixes the failing test
(llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir)
introduced in https://github.com/llvm/llvm-project/pull/207419
DeltaFile
+20-21llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
+20-211 files

FreeNAS/freenas b982811tests/unit test_activedirectory_health.py

NAS-141691 / 26.0.0-RC.1 / Fix AD tests (by themylogin) (#19502)

http://jenkins.eng.ixsystems.net:8080/job/tests/job/unit_tests/4304/

Original PR: https://github.com/truenas/middleware/pull/19269

----
Passing CI
[here](http://jenkins-eng-ci.cmb1.ixsystems.net:8080/job/stable_26/job/unit_tests/49/).

Co-authored-by: Brian M <brian.meagher at ixsystems.com>
DeltaFile
+4-3tests/unit/test_activedirectory_health.py
+4-31 files

LLVM/project c119777llvm/include/llvm/IR CallingConv.h

Review fixes 2
DeltaFile
+1-1llvm/include/llvm/IR/CallingConv.h
+1-11 files

LLVM/project cbae644llvm/lib/Target/PISA/MCTargetDesc PISAMCExpr.cpp PISAInstPrinter.h

Review fixes
DeltaFile
+5-1llvm/lib/Target/PISA/MCTargetDesc/PISARegEncoder.h
+1-3llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.cpp
+2-0llvm/lib/Target/PISA/MCTargetDesc/PISARegEncoder.cpp
+0-1llvm/lib/Target/PISA/MCTargetDesc/PISAMCExpr.cpp
+0-1llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.h
+8-65 files

LLVM/project eba567cllvm/lib/Target/PISA/MCTargetDesc PISATargetStreamer.cpp

Formatting fix
DeltaFile
+2-2llvm/lib/Target/PISA/MCTargetDesc/PISATargetStreamer.cpp
+2-21 files

LLVM/project 2b643fbllvm/lib/Target/PISA PISAInstrInfo.cpp PISAInstrFormats.td, llvm/lib/Target/PISA/MCTargetDesc PISAInstPrinter.cpp PISATargetStreamer.cpp

Add PISA register file, instruction set, and MC layer

Add the PISA register file and register-bank descriptions, the instruction
formats and definitions, and the MC/assembly layer (instruction printer,
register and code encoders, target streamer, MC target description and the
supporting enums), replacing the stub descriptions from
the initial target skeleton.

This provides the instruction-set description and assembly-emission
foundation. The GlobalISel lowering and instruction selection that consume it
are added in the following changes.
DeltaFile
+2,511-11llvm/lib/Target/PISA/PISAInstrInfo.td
+1,075-0llvm/lib/Target/PISA/PISACombine.td
+834-0llvm/lib/Target/PISA/PISAInstrFormats.td
+572-0llvm/lib/Target/PISA/MCTargetDesc/PISATargetStreamer.cpp
+448-1llvm/lib/Target/PISA/PISAInstrInfo.cpp
+394-11llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.cpp
+5,834-2333 files not shown
+8,447-6239 files

LLVM/project 80baf62clang/include/clang/Basic AttrDocs.td, llvm/test/CodeGen/AMDGPU buffer-fat-pointer-atomicrmw-fadd.ll global-atomicrmw-fmin.ll

Merge branch 'main' into users/kparzysz/auto-modifiers-verify
DeltaFile
+4,294-4,283clang/include/clang/Basic/AttrDocs.td
+3,815-3,810llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+3,815-3,810llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+3,513-3,467llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+3,513-3,467llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+3,252-3,311llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+22,202-22,1486,024 files not shown
+271,296-181,0766,030 files

FreeBSD/src f236685sys/sys sched.h

kern/sched: Hide scheduler selection from C++

The scheduler selection interface uses names that are reserved words in
C++, causing problems for downstream projects that use C++ in the
kernel.  Work around this by hiding the interface from C++ compilers
until we can come up with a better solution.

Fixes:          ce38acee8d0b ("Add kern/sched_shim.c")
MFC after:      1 week
Sponsored by:   Klara, Inc.
Sponsored by:   NetApp, Inc.
Reviewed by:    siderop1_netapp.com, imp, kib
Differential Revision:  https://reviews.freebsd.org/D58991
DeltaFile
+12-2sys/sys/sched.h
+12-21 files

LLVM/project b62e0b3clang/docs/analyzer checkers.rst

Rewrite misleading sentence.
DeltaFile
+2-2clang/docs/analyzer/checkers.rst
+2-21 files

LLVM/project 0cfc219llvm/test/CodeGen/M68k/GlobalISel reg_bank_test.ll

[M68K] Prefer reg-bank-select (#217632)

Broken by #217486. This fixes the tests.

https://lab.llvm.org/buildbot/#/builders/27/builds/3837
DeltaFile
+1-1llvm/test/CodeGen/M68k/GlobalISel/reg_bank_test.ll
+1-11 files

FreeNAS/freenas b0c1f95src/middlewared/middlewared/utils/nvmet kernel.py, tests/sharing_protocols/nvmet test_nvmet_tcp.py

NAS-141762 / 26.0.0-RC.1 / Permit allow_any_host to be toggled (by bmeagherix) (#19526)

- Permit `allow_any_host` to be toggled off for a NVMe-oF subsystem
- Add unit test
`TestAllowAnyHostToggle::test__allow_any_host_toggle_with_active_host_link`.

----
Passing CI
[here](http://jenkins-eng-ci.cmb1.ixsystems.net:8080/job/master/job/sharing_protocols_tests/175/).

Original PR: https://github.com/truenas/middleware/pull/19521

---------

Co-authored-by: Brian M <brian.meagher at ixsystems.com>
DeltaFile
+93-0tests/sharing_protocols/nvmet/test_nvmet_tcp.py
+16-0src/middlewared/middlewared/utils/nvmet/kernel.py
+109-02 files

LLVM/project f8a076aclang/include/clang/Basic BuiltinsAMDGPUDocs.td BuiltinsAMDGPU.td, llvm/include/llvm/IR IntrinsicsAMDGPU.td

[NFC][AMDGPU] Introduce a new target feature for N=16 WMMAs (#217506)
DeltaFile
+30-28llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+28-28clang/include/clang/Basic/BuiltinsAMDGPU.td
+20-0clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+10-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+7-1llvm/lib/Target/AMDGPU/AMDGPU.td
+95-625 files

LLVM/project f47b8b0llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU sched_mfma_rewrite_diff_types.mir gfx-callable-argument-types.ll

[AMDGPU][CodeGen] Allow remat with multiple users in multiple regions

This relaxes one of the constraints on rematerialization candidates in
the scheduler's `PreRARematStage`. The current implementation only allows
rematerializing a register if it has users in a single region. This
allows it when a register has multiple users in multiple regions.

In such cases the register is rematerialized as many times as there are
using regions, just before the first user in each using region. The cost
model for assessing rematerialization opportunities now takes into
account that mutliple new instructions may be created for each candidate.
DeltaFile
+664-537llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
+202-167llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
+102-61llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+36-25llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
+22-24llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+17-12llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
+1,043-8262 files not shown
+1,047-8328 files

LLVM/project cce1e0cllvm/unittests/CodeGen RegisterPressureTest.cpp

Add missing include + newline
DeltaFile
+2-1llvm/unittests/CodeGen/RegisterPressureTest.cpp
+2-11 files

LLVM/project 5abe31ellvm/include/llvm/CodeGen RegisterPressure.h, llvm/lib/CodeGen MachineScheduler.cpp RegisterPressure.cpp

[CodeGen] Correctly classify/mark dead defs when adjusting lane liveness

Despite what the documentation of `adjustLaneLiveness` suggests, the
method never sets dead flags on dead def operands, even when missing
dead flags can later lead to machine verifier errors.

This makes the method identify dead definitions from definitions that
are initially thought to be alive, and makes it add a dead flag on the
last definition of a virtual register, matching the behavior expected
by the machine verifier (ref. "Instruction ending live segment on dead
slot has no dead flag").

`adjustLaneLiveness` and `detectDeadDefs` now also use the same
mechanism to identify dead definitions. It relies on comparing the
defined lanes of a definition with those that stay alive after it.
DeltaFile
+90-0llvm/unittests/CodeGen/RegisterPressureTest.cpp
+24-27llvm/lib/CodeGen/RegisterPressure.cpp
+13-8llvm/include/llvm/CodeGen/RegisterPressure.h
+2-2llvm/lib/CodeGen/MachineScheduler.cpp
+1-1llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+1-0llvm/unittests/CodeGen/CMakeLists.txt
+131-386 files

LLVM/project 588e5b6llvm/include/llvm/CodeGen RegisterPressure.h, llvm/lib/CodeGen MachineScheduler.cpp RegisterPressure.cpp

[CodeGen] Overload `adjustLaneLiveness` to cleanly split use cases (NFC) (#215594)

When providing a non-null `AddFlagsMI` it makes no sense to pass a `Pos`
that is not `AddFlagsMI`'s own position. In such cases the position can
be queried from the MI directly, avoiding possible inconsistencies.

This splits `RegisterOperands::adjustLaneLiveness` into two overloads
whose behavior only differ in whether an MI's operand flags are updated
in the process.
DeltaFile
+47-29llvm/lib/CodeGen/RegisterPressure.cpp
+19-5llvm/include/llvm/CodeGen/RegisterPressure.h
+2-4llvm/lib/CodeGen/MachineScheduler.cpp
+1-2llvm/unittests/CodeGen/RematerializerTest.cpp
+1-2llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+1-2llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
+71-446 files

LLVM/project 81c8ea8llvm/include/llvm/IR PISAIntrinsicUtils.h IntrinsicsPISA.td, llvm/include/llvm/Support PISAAddrSpace.h

Change ordering, add links to PISA spec
DeltaFile
+13-3llvm/include/llvm/IR/IntrinsicsPISA.td
+8-0llvm/include/llvm/IR/PISAIntrinsicUtils.h
+2-0llvm/include/llvm/Support/PISAAddrSpace.h
+23-33 files

LLVM/project eee3cf1llvm/test/CodeGen/AMDGPU scalar-float-sop1.ll, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.raw.buffer.store.format.f16.ll fma.bf16.ll

AMDGPU/GlobalISel: Bitcasting G_TRUNC combine

Creating the G_TRUNC that changes type as well. This is really
the LLT::scalar trunc style that we inherited from switching to
extended LLTs, very common on non-true16 targets.
Affects inst-select pattern matching that were blocked by bitcast.
DeltaFile
+99-115llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+65-139llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.bf16.ll
+6-22llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
+10-12llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
+6-10llvm/test/CodeGen/AMDGPU/GlobalISel/fma.bf16.ll
+5-9llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
+191-3078 files not shown
+216-34314 files

LLVM/project 8d03e3ellvm/test/CodeGen/AMDGPU load-atomic-flat.ll dagcombine-fmul-sel.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshr.ll fptrunc.bf16.ll

AMDGPU/GlobalISel: Fold (trunc (lshr x, 16)) to unmerge high half

Huge performance impact in some shaders with high register pressure.
What this really does is selects _hi16 register classes, and true16
machinery takes over later. Trunc + shift ends up in _lo16!
This requires allocating an extra register when the _lo16 half of the
original real 32-bit VGPR is still live.
DeltaFile
+566-304llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
+558-300llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
+387-222llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+275-158llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.bf16.ll
+231-126llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
+180-132llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+2,197-1,24224 files not shown
+3,192-2,28530 files

FreeBSD/ports c657ab4x11/xload Makefile distinfo

x11/xload: update to 1.2.2

PR:             297664
Approved by:    x11 (maintainer, arrowd)

Sponsored by:   tipi.work
DeltaFile
+3-3x11/xload/distinfo
+1-1x11/xload/Makefile
+4-42 files

LLVM/project c756203clang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/Driver hip-cuid.hip amdgpu-xnack-sramecc-flags.c

clang/AMDGPU: Stop passing redundant -target-cpu to cc1

Now that the exact target is encoded in the triple's subarch field,
-target-cpu is redundant. This avoids polluting the resultant IR with
unwanted "target-cpu" attributes. The net result is the desired codegen
when compiling libraries for a major subarch and linking it into a
program compiled for a specific arch. e.g., compiling for "gfx9-generic"
would pollute the IR with "target-cpu"="gfx9-generic", so codegen
would ultimately be performed for the generic target even after
linking into the concrete gfx9 cpu. The specialization will now be
achieved by merging the triples without the linker or optimization
passes needing to fixup function attributes.
DeltaFile
+62-62clang/test/Driver/amdgpu-mcpu.cl
+26-26clang/test/Driver/hip-sanitize-options.hip
+12-16clang/test/Driver/hip-rdc-device-only.hip
+18-8clang/lib/Driver/ToolChains/CommonArgs.cpp
+10-10clang/test/Driver/amdgpu-xnack-sramecc-flags.c
+5-7clang/test/Driver/hip-cuid.hip
+133-12926 files not shown
+188-20932 files

FreeBSD/src 2ff0ca5lib/libc/gen Makefile.inc

uexterror(3): install the right manpage

Reported by:    Herbert J. Skuhra
DeltaFile
+1-1lib/libc/gen/Makefile.inc
+1-11 files

LLVM/project d98d12clibcxx/docs/ReleaseNotes 24.rst, libcxx/include fstream

[libc++] Support file offsets larger than 2GB in basic_filebuf on 32-bit AIX and 32-bit glibc Linux (#215892)

Currently, opening files greater than 2GB on 32-bit AIX doesn't work,
even with `_LARGE_FILES` defined in the user program. A similar issue
exists with 32-bit glibc.

On AIX, the `_LARGE_FILES` macro enables programs to handle large files
(greater than 2GB). When `_LARGE_FILES` is defined, all data types,
structures, and subroutine names are mapped to their 64-bit versions
during preprocessing
([source](https://www.ibm.com/docs/en/aix/7.2.0?topic=volumes-writing-programs-that-access-large-files)).
Since the shared library is pre-compiled, defining the macro in user
programs doesn't affect fstream's open/seek/tell, causing failure with
large files on 32-bit.

Instead of building libc++ with `_LARGE_FILES` defined, which could
cause ODR violations, we can swap `fopen`/`fseeko`/`ftello` calls with
their 64-bit counter-parts.


    [3 lines not shown]
DeltaFile
+29-1libcxx/include/fstream
+0-5libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
+2-0libcxx/docs/ReleaseNotes/24.rst
+31-63 files

LLVM/project 7fe10a5utils/bazel/llvm-project-overlay/clang/unittests BUILD.bazel

[Bazel] Fixes c0125a7 (#217605)

This fixes c0125a7bf833b6cf0d5b4a085b63094e0893c85a (#206482).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=c0125a7bf833b6cf0d5b4a085b63094e0893c85a

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
+1-01 files

FreeNAS/freenas 881f04ctests/unit test_activedirectory_health.py

Fix stale-SID recovery test to match stable/26's call_sync-based restart

PR #19223 (call_sync2 migration) wasn't backported here, so
_recover_ad still restarts idmap via middleware.call_sync, not
call_sync2. Update the test to match, instead of pulling in the
unrelated migration.
DeltaFile
+4-3tests/unit/test_activedirectory_health.py
+4-31 files

LLVM/project 40b01d0clang/lib/AST/ByteCode InterpBuiltin.cpp

[clang][bytecode] Remove a Pointer::toAPValue() call (#217594)

We can just use `computeLayoutOffset()` instead.
DeltaFile
+8-4clang/lib/AST/ByteCode/InterpBuiltin.cpp
+8-41 files

LLVM/project a5b63a5llvm/utils profcheck-xfail.txt

[ProfCheck] Temporarily opt out new VectorCombine test (#217612)

Introduced in #211022, disable for now while it gets fixed.
DeltaFile
+1-0llvm/utils/profcheck-xfail.txt
+1-01 files

LLVM/project 5ef2f7fclang/lib/CIR/CodeGen CIRGenExprConstant.cpp, clang/test/CIR/CodeGen fixed-point-literal.c

[CIR] Implement fixed-point global literals (#217125)

These just have an integral representation. The implementation here is
identical to classic-codegen, so I just added some spot-check tests to
make sure we do the same thing.
DeltaFile
+23-44clang/test/CIR/CodeGen/fixed-point-literal.c
+4-3clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+27-472 files

LLVM/project cc61111llvm/include/llvm/CodeGen MachineBasicBlock.h

[CodeGen] Give NewPM SplitCriticalEdge default values

To match the legacyPM version. This is needed for migrating
RegBankSelect without explicitly passing nullptr to these parameters,
which is not ideal given the LegacyPM version already sets them to
defaults.

Reviewers: arsenm, nikic

Pull Request: https://github.com/llvm/llvm-project/pull/217504
DeltaFile
+10-6llvm/include/llvm/CodeGen/MachineBasicBlock.h
+10-61 files

LLVM/project b245826clang/lib/CIR/CodeGen CIRGenExprScalar.cpp, clang/test/CIR/CodeGen fixed-point-conversions.cpp

[CIR] Lower Fixed-point conversions to ints/floats/self (#217347)

As the next step in implementing fixed-point NYIs, this patch goes
through and implements the conversion operations. LLVM has a conversion
class for these that generates LLVM, so this duplicates that as
mechanically as possible to convert to CIR. The result is that we end up
with effectively identical IR.

I DID consider 'wiring' this through as its own type, however it is a
rarely used feature and I fear that doing so will result in lost
optimization opportunties vs converting it to 'int' early.
DeltaFile
+1,354-0clang/test/CIR/CodeGen/fixed-point-conversions.cpp
+300-11clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+1,654-112 files