java/jextract: new port
jextract is a tool which mechanically generates Java bindings from
native library headers. This tools leverages the clang C API in order
to parse the headers associated with a given native library, and the
generated Java bindings build upon the Foreign Function & Memory API.
Co-authored-by: Michael Osipov <michaelo at FreeBSD.org>
PR: 285159
[VPlan] Append recipes created via builder to worklist
The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.
This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:
```c
long f(const int *p, const int *q, long n) {
long a = 0, b = 0;
for (long i = 0;; i++) {
if (p[i] && q[i]) { a += i; b += i; }
if (i + 1 == n) break;
}
return a + b;
}
```
Before:
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[InterleavedLoadCombine] Do not combine loads across basic blocks (#223915)
This pass turns a group of interleaved loads into a single wide load
inserted at the first load. That is only valid when all of the loads are
in the same basic block. Otherwise the wide load can read memory that
the original program only accessed on a conditional path.
The offset index keyed candidates on base pointer, type and offset only,
so it could pair loads from different blocks. Restrict each block's
matching to candidates whose loads are in that block. This also keeps
the candidate list and index per block, so they stay small.
Fixes a miscompile introduced by #213053.
[clang][LoongArch] Emit "target-abi" module flag (#223647)
The LoongArch backend reads the ABI from the "target-abi" module flag,
but clang only emits that flag for ARM, PowerPC and RISC-V. Since LTO code
generation doesn't see the -target-abi option passed to clang, it falls
back to the default ABI of the target, which is lp64d for
loongarch64-unknown-elf, regardless of the ABI the code was compiled for.
When an FPU is enabled, this silently miscompiles code built for another
ABI. For example, with -mabi=lp64s, functions get the lp64d calling
convention after LTO, passing and returning floating-point values in FP registers
instead of general-purpose ones, and the output is marked as double-float. Nothing
reports this if every object goes through LTO. For instance, a shared library
built this way links without error, and so does lp64s code built without LTO that
uses it. Without an FPU, the generated code keeps the soft-float calling
convention, but the output is still marked as double-float.
The mismatch only shows up as an error when LTO output is linked
together with relocatable objects built without LTO, which LLD rejects with "cannot
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[LLVM][CodeGen][SME] Don't use non-streaming zeroing instruction when in streaming mode. (#222353)
When selecting scalable vector bf16-f32 converts we emit zip(0,vec).
Unfortunately, the typical zero-latency zeroing instruction is not
available when in streaming mode.
(cherry picked from commit 9679fbfea993cb2e815fe0fa5eefde310f917349)
[AMDGPU] Fix GlobalISel VGPR-to-VCC lowering types (#220987)
Register-bank legalization synthesized an untyped G_AND s32, but
instruction-selection patterns only matched typed G_AND i32, causing:
```
LLVM ERROR: cannot select: %:vgpr_32(s32) = G_AND ...
```
The source-level and i32 was valid; the incorrect type was introduced by
AMDGPU `VgprToVccCopy` lowering. SelectionDAG was unaffected because it
retained typed DAG nodes.
Assisted-by: Codex
---------
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
AMDGPU: Maintain LiveIntervals when removing blocks in SILowerControlFlow (#223642)
removeMBBifRedundant removed a redundant block's instructions from the
LiveIntervals maps but not the block itself, leaving a stale idx2MBBMap
entry that crashed getMBBFromIndex in the verifier.
Add SlotIndexes::removeMBBFromMaps to drop the erased block's slot
range, and recompute the intervals that spanned it.
Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
bootgrid: only schedule dimension changes after data processing, window resizing and table visibility changes
The height recalculation scheduled on renderComplete was too aggressive,
since Tabulator emits that event while virtual rows are rendered during scrolling.
Also prevent setHeight() from running mid-scroll at all times.
This commit fixes the visual glitch of resetting scroll positions introduced
by https://github.com/opnsense/core/commit/050f3c8277
NAS-143780 / 26.0.0 / Model HA as a license feature instead of a license type (#19732)
This commit adds changes to follow upstream collapsing enterprise_single
and enterprise_ha into a single enterprise type, with HA moving into the
features dict as its own key. The HA entitlement becomes an ordinary
matrix vector keyed on that feature, so LicenseTypeRule has nothing left
to decide and goes away with it.
Legacy blobs predate the feature vocabulary, so the shim injects the HA
key when the blob names a second controller serial. That is the same
condition which used to pick the enterprise_ha type, which is what keeps
every fielded legacy pair licensed for failover.
(cherry picked from commit 0a5a6e5fbb94007206df82a2916f8b043d7675ac)
[RISCV] Do not verify size for some Xqci instructions (#223913)
After instruction size verification was enabled by default in
https://github.com/llvm/llvm-project/pull/221687/ we were running into
crashes for certain 48-bit Xqci instructions. This was happening because
we have compress patterns for these 48-bit instructions to compress them
into 32-bit instructions which `getInstSizeInBytes` was not taking into
account.
The crash looks like:
```
Size mismatch for: QC_E_SW $x0, $x14, 0 :: (store (s32) into %stack.0)
Expected maximum size: 2
Actual size: 4
```
Do not verify size for such instructions until we can return the correct
size for them.
AMDGPU: Use LiveIntervals in SIOptimizeVGPRLiveRange when available (#222385)
LiveVariables has been long deprecated. Use LiveIntervals if available.
With the current pass structure, this will use LiveVariables.
Co-authored-by: Claude (Claude-Opus-4.8)
[IR] Simplify DIAssignID by storing its links in the node. NFC (#223324)
AssignmentTrackingPass generates DIAssignID metadata. A DIAssignID links
the instructions it is attached to, kept in
LLVMContextImpl::AssignmentIDToInstrs, with the dbg_assign records that
refer to it, found through a permanent use list (#78300 made DIAssignID
the only always-replaceable MDNode for this). Keep both lists in the
node as TinyPtrVector members instead (98% of instruction lists and
88-96% of record lists hold exactly one pointer), and drop the map and
`isAlwaysReplaceable()`.
Aided by Opus 5
[RISCV] Merge zeroing stores into wider LMUL vector stores (#223908)
memset lowers to LMUL1 vector stores (v2i64 for e64) that we rely on
store merging to widen. `storeOfVectorConstantIsCheap` counted the
number of MemVT-sized stores, so a v2i64 MemVT needed 4 stores before
merging kicked in, leaving two VL=2 m1 stores for a 32B zero region.
Use the total element count for zeroing stores so two v2i64 stores
merge into one VL=4 e64 m2 store.
Partially fixes #223906
Assisted-by: TRAE CLI (Opus 4.8)
[MustExecute] Use the loop predecessor instead of the preheader (#222096)
CanProveNotTakenFirstIteration() gets the IV start value via
LHS->getIncomingValueForBlock(CurLoop->getLoopPreheader()). If the loop
is not in simplified form, getLoopPreheader() returns null and the
lookup asserts. This is reachable from print<must-execute> on IR that is
not in LoopSimplify form (see the reproducer in #166488).
Fixed: use getLoopPredecessor() instead: it returns the unique
out-of-loop predecessor of the header even when it is not a dedicated
preheader, consequently the start value is still known. If there is no
such predecessor, bail out.
Fixes #166488.
