pfctl: remove the prototype of pfr_ina_define()
The function went when DIOCRINADEFINE was converted to netlink; pfctl
calls pfctl_ina_define() from libpfctl instead. Name that one in the
error message that pfctl_load_tables() prints when it fails.
Fixes: 219ce3063840 ("pf: convert DIOCRINADEFINE to netlink")
Sponsored by: Rubicon Communications, LLC ("Netgate")
[InstCombine] Don't fold `store undef` at non-byte-sized widths (#230955)
It's well known that we can't remove `store i1 undef` unless we can
prove the byte is non-`poison`. However, since
https://github.com/llvm/llvm-project/pull/180739 it's doubly wrong
unless we can prove that bits 1..7 in memory are already zero, since the
stored value is zero-extended to the next byte boundary.
X86/GlobalISel: Mark unused FP compare flag defs dead (#231003)
Fix not marking FPSW and EFLAGS clobbers as dead in the manual fcmp
selection.
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
[KnownFPClass] Apply denormal modes at the fmul/fdiv boundaries (#229638)
I added `applyInputDenormalMode`/`applyOutputDenormalMode` to
`KnownFPClass::fmul`/`KnownFPClass::fdiv`. I also inlined
`propagateXorSign` back into `fmul` and `fdiv` to make the logic easier
to follow, and because I have follow up PRs that would need to remove it
either way.
Adding `applyOutputDenormalMode` allowed `fmul`/`fdiv` to rule out
positive zero for these cases for the `FTPZ` and `dynamic` output modes:
- `fmul(+0.0, neg-normal)`
- `fmul(-0.0, pos-normal)`
- `fdiv(+0.0, neg-normal)`
- `fdiv(-0.0, pos-normal)`
This is because `fmul`/`fdiv` rule out subnormal if the LHS is a known
zero, which also means that a subnormal will not flush to positive zero.
Previously, the always zero LHS deduction was applied after
`propagateXorSign`, so `propagateXorSign` could not rule out a result
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AMDGPU: Move R600 subtarget features to R600Features.td
Split the R600 SubtargetFeature definitions and
R600FrontendVisibleFeatures out of R600Processors.td, mirroring
GCNFeatures.td.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AMDGPU: Move GCN subtarget features to GCNFeatures.td
Move the GCN SubtargetFeature definitions, the FeatureISAVersion lists
and AMDGPUFrontendVisibleFeatures out of AMDGPU.td, so they can be used
without parsing the instruction, register and intrinsic definitions.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AMDGPU: Move scheduling model defs to AMDGPUSchedModels.td (#230995)
Split the SchedMachineModel definitions out of SISchedule.td so the
processor definitions can be parsed without the InstRW and other
instruction-dependent scheduling information.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[KnownFPClass] Fix `KnownFPClass::log` deductions for ppcf128 (#223296)
Fixes https://github.com/llvm/llvm-project/issues/217658
AI Disclosure:
I used ChatGPT Codex (5.6 sol) and Claude (Opus 5) to help implement the
changes and write tests.
