[lldb] Improve PE remote debugging by falling back to the load address (#214023)
Fall back to the preferred load address from file in
DynamicLoaderWindowsDYLD to allow debugging e.g. PE kernels over QEMU
gdbstub without needing to specify a base (instead of not loading the
sections which causes e.g. breakpoints/symbolized backtraces to not
work).
[offload][omp] Manage events through liboffload (#226444)
Manage Events through the liboffload API.
Remove all Event APIs from GenericPluginTy.
Assisted by Claude
NAS-144459 / 27.0.0 / Fix api2.test_300_nfs.TestNFSops.test_nonroot_behavior (by themylogin) (#20014)
Mounts from localhost (SSH_NFS) as NAT between the CI test runner and
the appliance rewrites the privileged source port.
Original PR: https://github.com/truenas/middleware/pull/20011
Co-authored-by: themylogin <themylogin at gmail.com>
[LLVM][CodeGen][SVE] Use real instruction name as the key for SVE pseudo map. (#231494)
SVEPseudoMap previously used an instruction like string as the key
linking real and pseudo instructions. This requires additional state
when defining instructions that's effectively redundant. By using the
real instruction we remove the need for additional state while making it
possible for pseudo instructions to inherit state from their real
counterpart.
[lldb][test] Disable TestSignedTypes.py on Windows on Arm (#231933)
When the debug info type is not PDB. With PDB it works.
FAIL: test_dwarf (TestSignedTypes.SignedTypesTestCase.test_dwarf)
AssertionError: Ran command:
"frame variable --show-types --no-args"
Got output:
Expecting sub string: "(int) the_signed_int = 99" (was not found)
[offload][test] Mark xteam_reduction_no_parallel.c unsupported on intelgpu (#231927)
Some constructs are not properly supported by Level Zero yet, as for
other (already existing) offload tests.
[CIR][OpenMP] Add support for host_eval so that SPMD kernels can be used
This patch adds support for host_eval so that SPMD kernels and in the future
num_threads and other clauses can be implemented correctly.
Assisted-by: Cursor / Claude Sonnet 5 High
AArch64: Use minimal tablegen inputs for TargetParser
Generate AArch64TargetParserDef.inc from a minimal file instead of all
of AArch64.td. The scheduling models referenced by the processor
definitions are defined in the scheduling files, which depend on the
instruction definitions. TargetParser does not use them, so the minimal
file defines empty placeholder models instead. The generated file is
byte-identical.
llvm-min-tblgen -gen-arm-target-def
Gigainstructions Peak RSS .td deps
AArch64.td 3.36 169 MB 100
AArch64TargetParserDef.td 0.04 7 MB 8
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AArch64][llvm] Fix incorrect diagnostic (index/immediate in simm9)
Improve the error message in the simm9 diagnostics and use the word
'immediate' instead of 'index'. This was noticed when creating the
CFLT instructions for Armv9.8-A, but would have caused a lot of
unrelated churn if merged as part of that change.
Co-authored-by: Martin Wehking <martin.wehking at arm.com>
[AArch64][llvm] Improve diagnostics for invalid operands (#230436)
Return `DiagnosticPredicate` from `isSImm()`, `isImmInRange()`, and
`isUImm12Offset()` so invalid operand types do not produce misleading
immediate range errors, while out-of-range constants retain their
range diagnostics.
Keep the load/store fallback predicate boolean and remove the
CFLT-specific diagnostic workaround. Update affected diagnostic
tests and add prefetch and CFLT regression testcases.
[AArch64] Prefer tst + bcc over lsr + cbz/cbnz (#228005)
Lower (BR_CC eq/ne, (SRL val, imm), 0) to tst + bcc instead of
lsr + cbz/cbnz when the tst and bcc instructions can be fused.
