LLVM/project 6e9694allvm/test/tools/llvm-gsymutil cmdline.test, llvm/test/tools/llvm-gsymutil/ARM_AArch64 fat-macho-symtab-file.yaml

[llvm-gsymutil] Add --symtab-file option to specify separate symbol table file  (#184059)

Add a `--symtab-file` option that allows specifying a separate file from
which
to read the symbol table during GSYM conversion. This is useful when
DWARF and
  function symbols are stored in separate files.

  Example:
`llvm-gsymutil --convert debug_info.elf --symtab-file=symbols.elf -o
output.gsym`

  ## Changes
  - Added `--symtab-file` to `Opts.td` and command-line help.
- Parsed and used `--symtab-file` in `llvm-gsymutil.cpp` during
conversion.
  - Kept architecture validation for thin object inputs.
- Added support for universal Mach-O inputs by selecting the matching
symbol-table slice for each selected

    [15 lines not shown]
DeltaFile
+234-0llvm/test/tools/llvm-gsymutil/ARM_AArch64/fat-macho-symtab-file.yaml
+150-0llvm/test/tools/llvm-gsymutil/X86/elf-symtab-file.yaml
+118-16llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
+5-0llvm/tools/llvm-gsymutil/Opts.td
+1-0llvm/test/tools/llvm-gsymutil/cmdline.test
+508-165 files

LLVM/project f5b9995lldb/test/Shell/Commands command-source-embedded.test

[lldb] Fix Broken Test For Embedded Source in Binary (#197040)

A previous change to fix a regression when displaying source of programs
that embed their source code into their debugging information (using,
e.g., DW_LNCT_LLVM_source) should display included a test that was not
appropriately robust to all platforms.

Disable the regression on Windows systems and make the CHECKs robust
against output generated on different platforms.
DeltaFile
+4-2lldb/test/Shell/Commands/command-source-embedded.test
+4-21 files

LLVM/project 2e73d7fllvm/include/llvm/IR PatternMatch.h, llvm/lib/Analysis InstructionSimplify.cpp

[IR] Account for byte width in m_PtrAdd

The method has few uses yet, so just pass DL argument to it. The change
follows m_PtrToIntSameSize, and I don't see a better way of delivering
the byte width to the method.
DeltaFile
+19-6llvm/unittests/IR/PatternMatch.cpp
+8-5llvm/include/llvm/IR/PatternMatch.h
+4-3llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+3-2llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+1-1llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+1-1llvm/lib/Analysis/InstructionSimplify.cpp
+36-186 files

LLVM/project 389c766llvm/include/llvm/IR IRBuilder.h, llvm/lib/Transforms/Instrumentation SanitizerCoverage.cpp

[IRBuilder] Add getByteTy and use it in CreatePtrAdd

The change requires DataLayout instance to be available, which, in turn,
requires insertion point to be set. In-tree tests detected only one case
when the function was called without setting an insertion point, it was
changed to create a constant expression directly.
DeltaFile
+22-0llvm/unittests/IR/IRBuilderTest.cpp
+8-2llvm/include/llvm/IR/IRBuilder.h
+2-3llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
+32-53 files

LLVM/project 2160259llvm/lib/Transforms/Utils SimplifyLibCalls.cpp, llvm/test/Transforms/InstCombine/SimplifyLibCalls memcpy-b16.ll memset-b16.ll

[SimplifyLibCalls] Add initial support for non-8-bit bytes

The patch makes CharWidth argument of `getStringLength` mandatory
and ensures the correct values are passed in most cases.
This is *not* a complete support for unusual byte widths in
SimplifyLibCalls since `getConstantStringInfo` returns false for those.
The code guarded by `getConstantStringInfo` returning true is unchanged
because the changes are currently not testable.
DeltaFile
+126-67llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
+69-0llvm/test/Transforms/InstCombine/SimplifyLibCalls/memcpy-b16.ll
+66-0llvm/test/Transforms/InstCombine/SimplifyLibCalls/memset-b16.ll
+50-0llvm/test/Transforms/InstCombine/SimplifyLibCalls/strcmp-b32.ll
+47-0llvm/test/Transforms/InstCombine/SimplifyLibCalls/stpncpy-b16.ll
+45-0llvm/test/Transforms/InstCombine/SimplifyLibCalls/strchr-b16.ll
+403-6729 files not shown
+932-10435 files

LLVM/project 3ccd33fclang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, llvm/lib/Analysis ValueTracking.cpp

[ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC)

The method assumes that host chars and target chars have the same width.
Add a CharWidth argument so that it can bail out if the requested char
width differs from the host char width.

Alternatively, the check could be done at call sites, but this is more
error-prone.

In the future, this method will be replaced with a different one that
allows host/target chars to have different widths. The prototype will
be the same except that StringRef is replaced with something that is
byte width agnostic. Adding CharWidth argument now reduces the future
diff.
DeltaFile
+72-31llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
+9-3llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+5-2llvm/lib/Analysis/ValueTracking.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp
+2-2clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+2-2llvm/lib/Transforms/Utils/AMDGPUEmitPrintf.cpp
+92-424 files not shown
+96-4610 files

LLVM/project 611ae7ellvm/lib/Analysis ValueTracking.cpp

[ValueTracking] Make isBytewiseValue byte width agnostic

This is a simple change to show how easy it can be to support unusual
byte widths in the middle end.
DeltaFile
+14-13llvm/lib/Analysis/ValueTracking.cpp
+14-131 files

LLVM/project 966835dclang/lib/CodeGen ItaniumCXXABI.cpp, llvm/include/llvm/IR Constants.h

Use DL in ConstantExpr::getPtrAdd() / ConstantExpr::getInBoundsPtrAdd()
DeltaFile
+9-9llvm/lib/Analysis/ScalarEvolution.cpp
+9-9llvm/include/llvm/IR/Constants.h
+9-0llvm/lib/IR/Constants.cpp
+5-3llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+2-1clang/lib/CodeGen/ItaniumCXXABI.cpp
+2-1llvm/unittests/IR/PatternMatch.cpp
+36-237 files not shown
+43-3013 files

LLVM/project 3898351llvm/include/llvm/IR Intrinsics.td Intrinsics.h, llvm/lib/IR Intrinsics.cpp Core.cpp

[IR] Make @llvm.memset prototype byte width dependent

This patch changes the type of the value argument of @llvm.memset and
similar intrinsics from i8 to iN, where N is the byte width specified
in data layout string.
Note that the argument still has fixed type (not overloaded), but type
checker will complain if the type does not match the byte width.

Ideally, the type of the argument would be dependent on the address
space of the pointer argument. It is easy to do this (and I did it
downstream as a PoC), but since data layout string doesn't currently
allow different byte widths for different address spaces, I refrained
from doing it now.
DeltaFile
+39-26llvm/lib/IR/Intrinsics.cpp
+9-4llvm/include/llvm/IR/Intrinsics.td
+5-2llvm/include/llvm/IR/Intrinsics.h
+2-2llvm/lib/IR/Core.cpp
+3-1llvm/lib/IR/Function.cpp
+2-1llvm/lib/IR/AutoUpgrade.cpp
+60-366 files not shown
+69-4212 files

LLVM/project 63fa6c8llvm/include/llvm/IR DataLayout.h, llvm/lib/IR DataLayout.cpp

[DataLayout] Add byte specification

This patch adds byte specification to data layout string.
The specification is `b:<size>`, where `<size>` is the size of a byte
in bits (later referred to as "byte width").

Limitations:
* The only values allowed for byte width are 8, 16, and 32.
16-bit bytes are popular, and my downstream target has 32-bit bytes.
These are the widths I'm going to add tests for in follow-up patches,
so this restriction only exists because other widths are untested.
* It is assumed that bytes are the same in all address spaces.
Supporting different byte widths in different address spaces would
require adding an address space argument to all DataLayout methods
that query ABI / preferred alignments because they return *byte*
alignments, and those will be different for different address spaces.
This is too much effort, but it can be done in the future if the need
arises, the specification reserves address space number before ':'.
DeltaFile
+68-19llvm/lib/IR/DataLayout.cpp
+16-6llvm/include/llvm/IR/DataLayout.h
+84-252 files

LLVM/project 3ccf17dclang/include/clang/Basic Builtins.td, clang/lib/AST ExprConstant.cpp

[clang][NFC] Remove non-builtin generic <stdbit.h> bit functions (#197069)

The non-builtin generic bit functions

stdc_leading_zeros
stdc_leading_ones
stdc_trailing_zeros
stdc_trailing_ones
stdc_first_leading_zero
stdc_first_leading_one
stdc_first_trailing_zero
stdc_first_trailing_one
stdc_count_zeros
stdc_count_ones
stdc_has_single_bit
stdc_bit_width
stdc_bit_floor
stdc_bit_ceil


    [20 lines not shown]
DeltaFile
+0-84clang/include/clang/Basic/Builtins.td
+0-28clang/lib/AST/ExprConstant.cpp
+0-14clang/lib/Sema/SemaChecking.cpp
+0-14clang/lib/CodeGen/CGBuiltin.cpp
+0-14clang/lib/AST/ByteCode/InterpBuiltin.cpp
+0-1545 files

LLVM/project 02f987bllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

1
DeltaFile
+0-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+0-11 files

LLVM/project 5f686f1llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV xqciac.ll

[RISCV] Use getSignedTargetConstant for QC_MULIADD (#197032)

The coefficient is a signed value, and `getTargetConstant` is for
unsigned values. This was causing us assertion failures.
DeltaFile
+20-0llvm/test/CodeGen/RISCV/xqciac.ll
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+21-12 files

LLVM/project 476ba17llvm/test/CodeGen/X86 fold-int-pow2-with-fmul-or-fdiv.ll

update test
DeltaFile
+16-53llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+16-531 files

LLVM/project 26a410cllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 fold-int-pow2-with-fmul-or-fdiv.ll

[DAGCombiner] Use KnownBits in `combineFMulOrFDivWithIntPow2`
DeltaFile
+202-11llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+2-3llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+204-142 files

LLVM/project 7499188bolt/lib/Profile StaleProfileMatching.cpp, llvm/lib/CodeGen MachineBlockHashInfo.cpp

[CodeGen,IRNormalizer,BOLT] Duplicate stable hash_16_bytes locally. NFC (#196854)

llvm/ADT/Hashing.h doesn't guarantee cross-process stability.
llvm/ADT/StableHashing.h provides stability for a specific compiler
version.

They reserve the right the right to adjust the implementation as the
compiler evolves.

Some callers of hashing::detail::hash_16_bytes rely on hash output
embedded in persisted artifacts:

* MachineBlockHashInfo serializes block hashes into BB section
  profile data and pins the mixer's exact output with a static_assert.
* BOLT's stale profile matching records block hashes in its on-disk
  profile format and replays them against potentially-rebuilt
  binaries (possibly built from a later LLVM revision).
* IRNormalizer derives basic-block names from the hash; the names
  land in the normalized IR text used to diff modules.

    [2 lines not shown]
DeltaFile
+19-9llvm/lib/CodeGen/MachineBlockHashInfo.cpp
+18-5llvm/lib/Transforms/Utils/IRNormalizer.cpp
+16-2bolt/lib/Profile/StaleProfileMatching.cpp
+53-163 files

LLVM/project c583e32llvm/test/CodeGen/RISCV/rvv vdota4u.ll vdota4su.ll

[RISCV] Rename dota4 to dot4a (#196921)

I don't know how this slipped our eyes...
DeltaFile
+0-337llvm/test/CodeGen/RISCV/rvv/vdota4u.ll
+0-337llvm/test/CodeGen/RISCV/rvv/vdota4su.ll
+0-337llvm/test/CodeGen/RISCV/rvv/vdota4.ll
+337-0llvm/test/CodeGen/RISCV/rvv/vdot4au.ll
+337-0llvm/test/CodeGen/RISCV/rvv/vdot4asu.ll
+337-0llvm/test/CodeGen/RISCV/rvv/vdot4a.ll
+1,011-1,01171 files not shown
+6,414-6,41477 files

LLVM/project c0d51ddllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-bit-counting.ll

[AArch64] Improve fixed vector lowering for cttz/ctlz when sve (#192427)

When available we should be able to lower fixed size 64/128 bit
cttz/ctlz vector instructions using sve. Below are the performance
uplifts

  +--------------+--------------+--------------+
  |   Function   | CTTZ Speedup | CTLZ Speedup |
  +--------------+--------------+--------------+
  | u8x8         |    1.33x     |    1.00x     |
  | u16x4        |    1.26x     |    1.00x     |
  | u32x2        |    1.26x     |    1.00x     |
  | u64x1        |    1.00x     |    7.00x     |
  +--------------+--------------+--------------+
  | u8x16        |    1.67x     |    1.00x     |
  | u16x8        |    1.51x     |    1.00x     |
  | u32x4        |    1.51x     |    1.00x     |
  | u64x2        |    1.26x     |    7.00x     |
  +--------------+--------------+--------------+
DeltaFile
+5-4llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+4-4llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
+9-82 files

FreeBSD/ports 0683638x11-fm/sushi Makefile pkg-plist

x11-fm/sushi: update to 50.0

Update to 50.0

  50.0
  ====

  - Fix a typo (Danial Behzadi)
  - Translation updates

Switch to USES= gettext-tools

Rewrite COMMENT and pkg-descr

Adjust dependencies

PR:             294997
DeltaFile
+4-12x11-fm/sushi/Makefile
+8-1x11-fm/sushi/pkg-plist
+3-5x11-fm/sushi/distinfo
+2-1x11-fm/sushi/pkg-descr
+17-194 files

OpenBSD/ports cBdXF7Agames/godot/pack2/patches patch-platform_linuxbsd_joypad_linux_cpp patch-drivers_sdl_joypad_sdl_cpp

   Backport SDL3 gamecontroller backend, enabling gamecontroller support
   now also on godot/pack2. Also suspend XScreenSaver, so that Godot
   doesn't put display to sleep when playing with gamecontroller.
   Tested with Derelict Star and Primal Planet.
VersionDeltaFile
1.1+620-0games/godot/pack2/patches/patch-platform_linuxbsd_joypad_linux_cpp
1.1+280-0games/godot/pack2/patches/patch-drivers_sdl_joypad_sdl_cpp
1.1+216-0games/godot/pack2/patches/patch-drivers_sdl_SCsub
1.1+146-0games/godot/pack2/patches/patch-platform_linuxbsd_joypad_linux_h
1.1+137-0games/godot/pack2/patches/patch-drivers_sdl_SDL_build_config_private_h
1.1+76-0games/godot/pack2/patches/patch-drivers_sdl_joypad_sdl_h
+1,475-010 files not shown
+1,724-1616 files

LLVM/project 82800fallvm/test/Transforms/InstCombine mul_fold.ll

update test
DeltaFile
+1-6llvm/test/Transforms/InstCombine/mul_fold.ll
+1-61 files

LLVM/project 7a5e736llvm/lib/Transforms/InstCombine InstCombineAddSub.cpp InstCombineInternal.h, llvm/test/Transforms/InstCombine mul_fold.ll

[InstCombine] Use KnownBits in `foldBoxMultiply`
DeltaFile
+46-0llvm/test/Transforms/InstCombine/mul_fold.ll
+23-13llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+2-0llvm/lib/Transforms/InstCombine/InstCombineInternal.h
+71-133 files

FreeBSD/src e26b5e0share/man/man4 spkr.4

spkr.4: Reflect latest changes and add history

- speaker(4) was recently modernized to lock the driver per-playback
  instead of per-open. Update the man page to explain this change.

- added a reference to MML and SMX in the historical context to make
  it easier for users to find additional documentation online.

Signed-off-by:  Raphael Poss <knz at thaumogen.net>
Reviewed by:    ziaee
Closes:         https://github.com/freebsd/freebsd-src/pull/2183
DeltaFile
+78-24share/man/man4/spkr.4
+78-241 files

FreeBSD/ports 40b03c1x11/py-nwg-displays distinfo Makefile

x11/py-nwg-displays: Update to 0.4.2

Changelog: https://github.com/nwg-piotr/nwg-displays/releases/tag/v0.4.2

Reported by:    GitHub (watch releases)
DeltaFile
+3-3x11/py-nwg-displays/distinfo
+1-1x11/py-nwg-displays/Makefile
+4-42 files

LLVM/project 9c4f97allvm/test/CodeGen/AArch64 bf16-v8-instructions.ll bf16-instructions.ll, llvm/test/CodeGen/AMDGPU ctlz_zero_poison.ll ctlz_zero_undef.ll

Merge branch 'main' into users/el-ev/fold-multi-use-select
DeltaFile
+3,073-1,259llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+2,614-0llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
+0-2,614llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
+1,660-649llvm/test/CodeGen/AArch64/bf16-instructions.ll
+1,440-725llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
+1,670-0llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
+10,457-5,2471,386 files not shown
+54,420-25,2301,392 files

LLVM/project b4f7c93llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 bitreverse.ll sve-fixed-length-rev.ll

[AArch64][Isel] For fixed length vectors use sve for bitreverse when available (#196025)

Lowering bitreverse via the SVE path seems to be giving significant
performance improvements for fixed width vectors

Speedups after the patch

uint8x8_t   1.01x
uint16x4_t  2.02x
uint32x2_t  2.01x
uint64x1_t  2.02x
uint8x16_t  1.00x
uint16x8_t  2.03x
uint32x4_t  2.03x
uint64x2_t  2.02x
DeltaFile
+199-47llvm/test/CodeGen/AArch64/bitreverse.ll
+7-7llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-8llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
+2-6llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
+210-684 files

LLVM/project 3af3f03llvm/lib/Analysis InstructionSimplify.cpp, llvm/test/Transforms/InstSimplify call.ll

address review comments

Co-Authored-By: dtcxzyw <dtcxzyw2333 at gmail.com>
DeltaFile
+3-4llvm/lib/Analysis/InstructionSimplify.cpp
+0-3llvm/test/Transforms/InstSimplify/call.ll
+3-72 files

LLVM/project 7be5546llvm/test/Transforms/InstSimplify call.ll

update test
DeltaFile
+3-12llvm/test/Transforms/InstSimplify/call.ll
+3-121 files

LLVM/project 0e8f87fllvm/test/Transforms/InstSimplify call.ll

add test
DeltaFile
+81-0llvm/test/Transforms/InstSimplify/call.ll
+81-01 files

LLVM/project e3c0d11llvm/lib/Analysis InstructionSimplify.cpp

[InstSimplify] Fold fshl/fshr of complementary shifts to identity
DeltaFile
+11-0llvm/lib/Analysis/InstructionSimplify.cpp
+11-01 files