LLVM/project 04327b1libcxx/test/libcxx/text/text_encoding environment.pass.cpp

Revert "[libc++][test] XFAIL `text/text_encoding/environment.pass.cpp` test on Armv7/Linux Ubuntu targets." (#211112)

Reverts #206188

XFAIL'ed wrong test
DeltaFile
+0-4libcxx/test/libcxx/text/text_encoding/environment.pass.cpp
+0-41 files

LLVM/project 6f47123llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU expert_scheduling_gfx12.mir

[AMDGPU] Remove some unneeded waits for VA_VDST (#210741)

Add some internal consistency checks on WaitcntBrackets before and after
processing each instruction. In particular, check that VA_VDST_RD and
VA_VDST_WR agree on the range of values of the underlying hardware
counter. Fix some cases where this was not true, which has the effect of
removing some unneeded waits for VA_VDST where it was already known to
be zero.
DeltaFile
+23-4llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+2-3llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx12.mir
+25-72 files

LLVM/project 29575a3llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp, llvm/lib/MC MachObjectWriter.cpp

[MachO] Preserve weak linkage for aliases (#198148)

Mach-O aliases with weak or linkonce linkage were emitted as weak
references, which is appropriate for undefined references but not for
alias definitions. Emit Mach-O aliases through the same linkage path as
other global definitions so weak aliases get .weak_definition.

When writing aliased symbols, keep the aliasee flags and include the
alias symbol's own flags so N_WEAK_DEF is preserved in the Mach-O n_desc
field.

Fixes #111321

#196047 was closed as a duplicate of #111321.
DeltaFile
+17-0llvm/test/CodeGen/AArch64/macho-weak-alias.ll
+6-1llvm/lib/MC/MachObjectWriter.cpp
+3-1llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+26-23 files

LLVM/project f5430c5llvm/lib/CodeGen Rematerializer.cpp

[NFC] Reword comment per post-merge feedback on #211031 (#211234)

As discussed with krzysz00
DeltaFile
+3-6llvm/lib/CodeGen/Rematerializer.cpp
+3-61 files

LLVM/project 77c7993clang/include/clang/Basic BuiltinsAMDGPU.td, clang/test/CodeGenOpenCL builtins-amdgcn-global-async-load-lds.cl

[AMDGPU] Add gfx13 support for global_load_async_to_lds
DeltaFile
+91-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
+50-0clang/test/CodeGenOpenCL/builtins-amdgcn-global-async-load-lds.cl
+48-0llvm/test/MC/AMDGPU/gfx13_asm_vflat.s
+4-4clang/include/clang/Basic/BuiltinsAMDGPU.td
+6-2llvm/lib/Target/AMDGPU/FLATInstructions.td
+2-1llvm/lib/Target/AMDGPU/AMDGPU.td
+201-71 files not shown
+202-77 files

FreeBSD/src e27b1cacontrib/unbound/iterator iterator.c, contrib/unbound/services outside_network.c listen_dnsport.c

unbound: Update to 1.25.2

Release notes at
        https://community.nlnetlabs.nl/t/unbound-1-25-2-released

Merge commit 'c68e7bcd81d62e9f5364c6da22fd9917976acf85'

Security:       CVE-2026-14586
Security:       CVE-2026-32665
Security:       CVE-2026-40691
Security:       CVE-2026-41637
Security:       CVE-2026-42955
Security:       CVE-2026-44621
Security:       CVE-2026-44687
Security:       CVE-2026-44690
Security:       CVE-2026-46582
Security:       CVE-2026-50045
Security:       CVE-2026-50046
Security:       CVE-2026-50243

    [12 lines not shown]
DeltaFile
+321-67contrib/unbound/services/outside_network.c
+159-75contrib/unbound/services/listen_dnsport.c
+96-11contrib/unbound/services/outside_network.h
+47-20contrib/unbound/iterator/iterator.c
+52-14contrib/unbound/services/mesh.c
+56-3contrib/unbound/validator/validator.c
+731-19051 files not shown
+1,130-33757 files

LLVM/project 37314b8llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 fmuladd-copyable-add-part.ll resized-bv-values-non-power-of2-node.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+60-51llvm/test/Transforms/SLPVectorizer/X86/fmuladd-copyable-add-part.ll
+41-14llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+5-5llvm/test/Transforms/SLPVectorizer/X86/resized-bv-values-non-power-of2-node.ll
+106-703 files

LLVM/project bad9ad3llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-partial-reduce.ll

[AArch64][SVE] Fix v16i8 -> v2i64 partial_reduce for VL > 128 (#204938)

A fixed-length `llvm.vector.partial.reduce.add` reducing `<16 x i8>`
into `<2 x i64>` is lowered on `+sve` by converting the reduction to a
scalable one and finishing with `convertFromScalableVector`. The i8 ->
i64 fold splits the `(nx)v4i32` dot before converting it back to fixed
length, but splitting a scalable container is not equivalent to
splitting the fixed vector it holds: at vscale=2 an `nxv4i32` container
splits into two `nxv2i32`, each holding four i32s, not the two-lane
halves of the underlying `v4i32`. The high partial sums land in lanes
that `convertFromScalableVector` then discards, so any runtime VL > 128
silently drops them — on a 256-bit machine (e.g. Neoverse V1) exactly
half the result is lost (#204939; downstream miscompile
rust-lang/rust#158144).

Convert the dot back to a fixed-length i32 vector before splitting, so
the split, widen and accumulate all happen in fixed length and no lanes
are dropped. The fixed dot width is derived from the result (two i32
lanes per i64 result lane) so the wider, VL-pinned `<4 x i64> <- <32 x

    [3 lines not shown]
DeltaFile
+532-126llvm/test/CodeGen/AArch64/sve-fixed-length-partial-reduce.ll
+26-16llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+558-1422 files

FreeBSD/src c68e7bciterator iterator.c, services outside_network.c listen_dnsport.c

import unbound 1.25.2
DeltaFile
+321-67services/outside_network.c
+276-0testcode/unittcpreuse.c
+159-75services/listen_dnsport.c
+96-11services/outside_network.h
+47-20iterator/iterator.c
+52-14services/mesh.c
+951-18750 files not shown
+1,501-34456 files

LLVM/project 3369dddllvm/lib/Target/AMDGPU GCNVOPDUtils.cpp VOP3PInstructions.td, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

AMDGPU: Reland: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3 (#196516)

For V_DOT2_F32_F16 and V_DOT2_F32_BF16 add their VOPDName and mark
them with usesCustomInserter which will be used to add pre-RA register
allocation hints to preferably assign dst and src2 to the same physical
register. When the hint is satisfied, canMapVOP3PToVOPD recognises the
instruction as eligible for VOPD pairing by checking if it is VOP2 like:
dst==src2, no source modifiers, no clamp, and src1 is a register.
Mark both instructions as commutable to allow a literal in src1 to be
moved to src0, since VOPD only permits a literal in src0.

Original patch had a bug where it did not check if physical src
registers match register class of appropriate operand in fullVOPD
instructions, check is now done via isValidVOPDSrc.
DeltaFile
+442-520llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+163-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+34-1llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+8-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+8-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+661-5951 files not shown
+663-5977 files

LLVM/project 3407cd1llvm/lib/Target/AMDGPU GCNVOPDUtils.cpp

AMDGPU: Validate VOPD/VOPD3 physical source registers against operand RC (#196515)

Replace isVGPR checks with isValidVOPDSrc that validates physical source
registers against the actual combined VOPD/VOPD3 instruction's operand
register classes. Now we also validate operands for VOPD instructions.
DeltaFile
+56-10llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+56-101 files

NetBSD/pkgsrc-wip d22f3c9ncnn TODO

ncnn: Add reference to CVE-2026-50144
DeltaFile
+2-0ncnn/TODO
+2-01 files

NetBSD/pkgsrc-wip f55c1b2loki TODO

loki: Add reference to CVE-2026-21729
DeltaFile
+2-0loki/TODO
+2-01 files

NetBSD/pkgsrc-wip a67eba9gitleaks TODO

gitleaks: Add reference to CVE-2026-63728
DeltaFile
+2-0gitleaks/TODO
+2-01 files

NetBSD/pkgsrc-wip d169cc6zeek TODO

zeek: Add references to latest CVEs
DeltaFile
+1-1zeek/TODO
+1-11 files

NetBSD/pkgsrc-wip a635608xrdp TODO

xrdp: Add references to latest CVEs
DeltaFile
+3-1xrdp/TODO
+3-11 files

NetBSD/pkgsrc-wip 18ae17crlottie TODO

rlottie: Add references to CVE-2026-15551
DeltaFile
+1-1rlottie/TODO
+1-11 files

NetBSD/pkgsrc-wip 9b8a8e9py-keras TODO

py-keras: Add references to latest CVEs
DeltaFile
+2-1py-keras/TODO
+2-11 files

NetBSD/pkgsrc-wip 6c871adpipewire TODO

pipewire: Add references to CVE-2026-5674
DeltaFile
+3-0pipewire/TODO
+3-01 files

NetBSD/pkgsrc-wip 1a1a2dcnomad TODO

nomad: Add references to latest CVEs
DeltaFile
+2-1nomad/TODO
+2-11 files

LLVM/project 3ac7573clang/bindings/python/clang cindex.py, clang/docs ReleaseNotes.md

[libclang/python] Remove CompletionChunk.isKind methods (#210678)

This completes the third step of
https://github.com/llvm/llvm-project/issues/156680
This change is a follow-up to
https://github.com/llvm/llvm-project/pull/177854, following the release
branching, to ensure a one release-cycle deprecation period.
DeltaFile
+0-51clang/bindings/python/clang/cindex.py
+6-0clang/docs/ReleaseNotes.md
+6-512 files

NetBSD/pkgsrc-wip 5e81660java-netty TODO

java-netty: Add reference to latest CVEs
DeltaFile
+3-2java-netty/TODO
+3-21 files

NetBSD/pkgsrc-wip afe5f7cdendrite TODO

dendrite: Add references to latest CVEs
DeltaFile
+1-1dendrite/TODO
+1-11 files

NetBSD/pkgsrc-wip 856faf0busybox TODO

busybox: Add references to latest CVEs
DeltaFile
+2-1busybox/TODO
+2-11 files

NetBSD/pkgsrc-wip 04c750eterraform-provider-hcloud distinfo go-modules.mk

terraform-provider-hcloud: Update to 1.66.1

Several major/breaking changes:
- Server Types now depend on Locations
  (<https://docs.hetzner.cloud/changelog#2025-09-24-per-location-server-types>)
- New DNS API GA
  (<https://docs.hetzner.cloud/changelog#2025-11-10-dns-ga>)
- Experimental Storage Box support
  (<https://docs.hetzner.cloud/changelog#2025-10-21-storage-box-api-update>)
- Deprecation of datacenter attribute for Primary IPs and Servers
- Available and recommended Server Types have been moved
  (<https://docs.hetzner.cloud/changelog#2026-04-01-datacenter-deprecations>)
- Primary IPs assignee_type behavior change
  (<https://docs.hetzner.cloud/changelog#2026-04-27-primary-ips-will-return-unassigned>
  and
  <https://docs.hetzner.cloud/changelog#2026-04-27-primary-ips-make-assignee_type-optional>)
- Datacenter data sources are deprecated
  (<https://docs.hetzner.cloud/changelog#2026-06-02-datacenters-deprecated>)


    [2 lines not shown]
DeltaFile
+255-255terraform-provider-hcloud/distinfo
+84-84terraform-provider-hcloud/go-modules.mk
+1-1terraform-provider-hcloud/Makefile
+340-3403 files

LLVM/project 05daf2allvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp

[LLVM][AArch64TargetTransformInfo] Fix typos in SVEIntrinsicInfo. (#211230)

Correct Propery->Property and sprinkle a couple of extra comments.
DeltaFile
+13-5llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+13-51 files

FreeBSD/src 948ad32sys/netinet raw_ip.c in_pcb.c, sys/netinet6 raw_ip6.c in6_pcb.c

bind(2): Lookup local address in current FIB if '*.bind_all_fibs' is active

When a protocol-specific 'bind_all_fibs' tunable is set to 0, a
listening socket will only receive traffic originating from the FIB
it was bound to. However, there are no checks to determine whether
an address exists in the target FIB when binding the socket, which can
lead to a situation where a socket and the address it was bound to
belong to different FIBs.

Prevent this footgun by looking up the requested address in the current
FIB if 'bind_all_fibs' is active and returning an error if the address
does not exist.

Sponsored by:   Stormshield
Sponsored by:   Klara, Inc.
Differential Revision:  https://reviews.freebsd.org/D58281
Reviewed by:    glebius, pouria, markj
MFC after:      2 weeks
DeltaFile
+100-0tests/sys/netinet/fib_bind.py
+5-2sys/netinet6/raw_ip6.c
+5-2sys/netinet/raw_ip.c
+1-1sys/netinet6/in6_pcb.c
+1-1sys/netinet/in_pcb.c
+1-0tests/sys/netinet/Makefile
+113-66 files

LLVM/project 31810a1llvm/lib/Target/AMDGPU GCNVOPDUtils.cpp

AMDGPU: Refactor checkVOPDRegConstraints (#196514)
DeltaFile
+28-41llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+28-411 files

LLVM/project 9ca046eclang/lib/CodeGen CodeGenModule.cpp, clang/lib/CodeGen/Targets PPC.cpp

clang: Emit "long-double-type" module flag generically

Move emission of the "long-double-type" module flag out of PowerPC
and into generic code, so it describes the long double format for all
targets.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+26-0clang/lib/CodeGen/CodeGenModule.cpp
+23-0clang/test/CodeGen/long-double-type-module-flag.c
+0-23clang/lib/CodeGen/Targets/PPC.cpp
+0-17clang/test/CodeGen/ppc64-long-double-type-attr.c
+49-404 files

LLVM/project c2e9ff2clang/include/clang/Basic BuiltinsAMDGPU.td, clang/test/CodeGen amdgpu-builtin-processor-is.c amdgpu-builtin-is-invocable.c

[AMDGPU] Add FeatureSubtarget for global async load/store lds
DeltaFile
+18-8llvm/lib/Target/AMDGPU/FLATInstructions.td
+8-8clang/include/clang/Basic/BuiltinsAMDGPU.td
+10-0llvm/lib/Target/AMDGPU/AMDGPU.td
+2-2clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
+1-1clang/test/CodeGen/amdgpu-builtin-processor-is.c
+1-1clang/test/CodeGen/amdgpu-builtin-is-invocable.c
+40-201 files not shown
+42-207 files