NetBSD/pkgsrc-wip ed6a078clang distinfo, clang-tools-extra distinfo

llvm: updated to 22.1.7
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+3-3compiler-rt/distinfo
+3-3clang/distinfo
+3-3clang-tools-extra/distinfo
+3-3flang/distinfo
+3-3libcxx/distinfo
+3-3libcxxabi/distinfo
+18-189 files not shown
+43-4315 files

FreeBSD/ports 0217ba6devel/stack Makefile

devel/stack: fix build on powerpc64le

This architecture was added in 13.0-RELEASE.
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+1-1devel/stack/Makefile
+1-11 files

FreeBSD/ports b6357f8devel/libffi321/files patch-configure

devel/libffi321: fix build on powerpc64le

Adds powerpc64le to powerpc64 case.
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+7-5devel/libffi321/files/patch-configure
+7-51 files

FreeBSD/ports afdbd44cad/hs-verismith/files patch-__cabal__deps_tasty-1.5.3_tasty.cabal

cad/hs-verismith: fix build on powerpc64le

powerpc64le is 64-bit as well.
DeltaFile
+11-0cad/hs-verismith/files/patch-__cabal__deps_tasty-1.5.3_tasty.cabal
+11-01 files

FreeBSD/ports b46cbafdevel/libffi33 Makefile

devel/libffi33: fix build on powerpc64le

ld: error: version script assignment of 'LIBFFI_BASE_7.0' to symbol 'ffi_type_longdouble' failed: symbol not defined
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+2-0devel/libffi33/Makefile
+2-01 files

FreeBSD/ports d8780bbdevel/hs-cabal-plan/files patch-__cabal__deps_tasty-1.5.3_tasty.cabal

devel/hs-cabal-plan: fix build on powerpc64le

powerpc64le is also 64-bit.
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+11-0devel/hs-cabal-plan/files/patch-__cabal__deps_tasty-1.5.3_tasty.cabal
+11-01 files

FreeBSD/ports 5cf7a16finance/hs-hledger/files patch-__cabal__deps_tasty-1.5.3_tasty.cabal

finance/hs-hledger: fix build on powerpc64le

powerpc64le is also 64-bit.
DeltaFile
+11-0finance/hs-hledger/files/patch-__cabal__deps_tasty-1.5.3_tasty.cabal
+11-01 files

FreeBSD/ports d3e6c09dns/dq distinfo Makefile

dns/dq: update to 20260601
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+3-3dns/dq/distinfo
+2-2dns/dq/Makefile
+5-52 files

LLVM/project 6bcdd84llvm/lib/Target/X86 X86ISelLowering.cpp X86InstrCompiler.td, llvm/test/CodeGen/X86 bt-merge-fuse.ll bittest-big-integer.ll

[X86] Merge BT with a matching BTR/BTS/BTC (#193612)

Fixes #165291.

BTR/BTS/BTC set CF from the pre-operation bit value, so a subsequent BT
on the same source and bit index produces the same CF and is redundant.
We were emitting both.

```ll
define i1 @btr_eq_i32(ptr %word, i32 %position) nounwind {
  %ofs = and i32 %position, 31
  %bit = shl nuw i32 1, %ofs
  %mask = xor i32 %bit, -1
  %ld = load i32, ptr %word
  %test = and i32 %ld, %bit
  %res = and i32 %ld, %mask
  %cmp = icmp eq i32 %test, 0
  store i32 %res, ptr %word
  ret i1 %cmp

    [37 lines not shown]
DeltaFile
+343-0llvm/test/CodeGen/X86/bt-merge-fuse.ll
+116-194llvm/test/CodeGen/X86/bittest-big-integer.ll
+97-0llvm/lib/Target/X86/X86ISelLowering.cpp
+12-0llvm/lib/Target/X86/X86InstrCompiler.td
+8-0llvm/lib/Target/X86/X86InstrFragments.td
+576-1945 files

FreeBSD/ports 7c613bcx11/hamclock Makefile, x11/hamclock/files patch-Makefile patch-wsServer_Makefile

x11/hamclock: Remove expired port

2026-06-01 x11/hamclock: Upstream programmer is deceased upstream server discontinued in June
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+0-45x11/hamclock/Makefile
+0-21x11/hamclock/files/patch-Makefile
+0-11x11/hamclock/files/patch-wsServer_Makefile
+0-11x11/hamclock/files/patch-ArduinoLib_Makefile
+0-11x11/hamclock/files/patch-hamclock.desktop
+0-11x11/hamclock/files/patch-liveweb.cpp
+0-1105 files not shown
+1-12611 files

FreeBSD/ports f9af651. MOVED, devel Makefile

devel/rye: Remove expired port

2026-06-01 devel/rye: Rye is no longer developed. All users should migrate to uv, the successor project from the same maintainers, which is actively maintained and much more widely used.
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+0-607devel/rye/distinfo
+0-342devel/rye/Makefile
+0-6devel/rye/pkg-descr
+1-0MOVED
+0-1devel/Makefile
+1-9565 files

LLVM/project f813817llvm/lib/Target/SPIRV SPIRVBuiltins.cpp, llvm/test/CodeGen/SPIRV/transcoding/OpenCL convert_signedness.ll

[SPIR-V] Select int-to-int convert opcode from source signedness (#201116)

OpSConvert/OpUConvert sext/zext is determined by the source operand, not
the destination type. Discovered in
https://github.com/llvm/llvm-project/pull/200791/changes#r3341230426

Fix a regression caused by #200791
DeltaFile
+67-0llvm/test/CodeGen/SPIRV/transcoding/OpenCL/convert_signedness.ll
+3-4llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+70-42 files

LLVM/project 8dd5139lldb/include/lldb/Target Memory.h, lldb/source/Target Memory.cpp

[lldb][NFC] Factor out helper code from MemoryCache (#201120)

This will be reused in a subsequent commit.
DeltaFile
+17-12lldb/source/Target/Memory.cpp
+5-0lldb/include/lldb/Target/Memory.h
+22-122 files

LLVM/project afd040copenmp/tools/archer ompt-tsan.cpp

[OpenMP][OMPT] Remove unused var in archer (#201140)

Working on enabling the build of OpenMP and Offload in pre-merge checks
surfaced this unused var and pre-merge checks run with -Werror.

As I did not see where it should be used, remove the variable to address
the warning.

The pre-merge running into the warning as error is
https://github.com/llvm/llvm-project/actions/runs/26826349862/job/79094823845?pr=174955
DeltaFile
+0-2openmp/tools/archer/ompt-tsan.cpp
+0-21 files

LLVM/project 87b97d6clang-tools-extra/docs conf.py

[clang-tools-extra][docs] Do not require myst_parser when building man pages (#201138)
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+12-2clang-tools-extra/docs/conf.py
+12-21 files

LLVM/project 8f58a4cmlir/include/mlir/Dialect/EmitC/IR EmitC.td, mlir/lib/Dialect/EmitC/IR EmitC.cpp

[mlir][emitc]: Add MemberCallOpaque op (#200057)

Cf. https://discourse.llvm.org/t/method-calls-in-emitc/90898
DeltaFile
+55-19mlir/lib/Target/Cpp/TranslateToCpp.cpp
+53-20mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
+45-5mlir/test/Dialect/EmitC/invalid_ops.mlir
+31-18mlir/lib/Dialect/EmitC/IR/EmitC.cpp
+30-0mlir/test/Target/Cpp/call.mlir
+29-0mlir/test/Dialect/EmitC/member_call_opaque.mlir
+243-627 files not shown
+261-8013 files

LLVM/project e8f3866clang/docs LanguageExtensions.rst, clang/lib/CodeGen CodeGenModule.cpp CodeGenModule.h

[PowerPC][AIX] Add -mloadtime-comment-vars support to preserve variables
in the final object file.
DeltaFile
+180-83llvm/lib/Transforms/Utils/LowerCommentStringPass.cpp
+77-0clang/lib/CodeGen/CodeGenModule.cpp
+66-0clang/docs/LanguageExtensions.rst
+37-0clang/test/CodeGen/loadtime-comment-vars.c
+34-0llvm/test/Transforms/LowerCommentString/loadtime-comment-vars.ll
+8-0clang/lib/CodeGen/CodeGenModule.h
+402-833 files not shown
+417-839 files

LLVM/project 7a82fb8llvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp

Fix formatting
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+2-2llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+2-21 files

OPNSense/core 07ff1efsrc/opnsense/mvc/app/controllers/OPNsense/Firewall/Api SourceNatController.php

The automatic SNAT rules prio_group should be the same as automatic firewall rules at the end of the ruleset
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+4-4src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/SourceNatController.php
+4-41 files

LLVM/project ade0e1aclang/lib/CIR/Dialect/IR CIRDialect.cpp, clang/test/CIR/IR invalid-cast.cir

[cir] Refine cir::CastOp semantics for int <-> float casts (#200005)

Int-to-float and float-to-int casts in cir::CastOp are lowered directly
to their LLVM equivalents. Update the verifier to reflect this semantics
and ensure that, for vector casts, the source and destination vectors have
the same length.

This lets the CIR verifier reject invalid casts earlier, instead of relying
on errors reported later at the LLVM IR level.
DeltaFile
+14-4clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+12-0clang/test/CIR/IR/invalid-cast.cir
+11-0clang/test/CIR/Lowering/cast.cir
+37-43 files

LLVM/project 7f8c4b5llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/test/CodeGen/AArch64 special-reg.ll

Revert "[AArch64] Fix definition of system register move instructions (#185709)"

This reverts commit b115dd117ac109ac501b8bc044dbdefd6f5f2471.
DeltaFile
+1,044-1,044llvm/lib/Target/AArch64/AArch64SystemOperands.td
+17-19llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
+11-24llvm/test/CodeGen/AArch64/special-reg.ll
+17-17llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
+0-26llvm/test/MC/AArch64/armv9-msrr.s
+0-26llvm/test/MC/AArch64/armv9-mrrs.s
+1,089-1,15628 files not shown
+1,203-1,34534 files

FreeNAS/freenas 20da832src/middlewared/middlewared/plugins/device_ vrrp_events.py, src/middlewared/middlewared/plugins/failover_ event.py

Process BACKUP in vrrp rapid-succession branch

When VrrpEventThread saw a second rapid event after waiting
rapid_event_settle_time, it dropped the latest queued event and
logged a warning. On boot-time keepalived flaps where the
MASTER->BACKUP gap floors below max_wait, that drop swallowed
the only BACKUP signal middleware was going to see, so
vrrp_backup never ran.

Fire the hook for BACKUP (skipping if vrrp_backup already ran
this process lifetime, tracked via a new LAST_EVENT_TYPE
attribute on FailoverEventsService); keep the drop+warn for
MASTER, since acting on an unsettled MASTER would kick off
fenced + zpool import.

(cherry picked from commit 7d7d11c424a6aa374b1183487483d52116d1f649)
DeltaFile
+31-1src/middlewared/middlewared/plugins/device_/vrrp_events.py
+16-0src/middlewared/middlewared/plugins/failover_/event.py
+47-12 files

LLVM/project 66110feclang/docs LanguageExtensions.rst, clang/lib/CodeGen CodeGenModule.cpp CodeGenModule.h

[PowerPC][AIX] Add -mloadtime-comment-vars support to preserve variables
in the final object file.
DeltaFile
+181-84llvm/lib/Transforms/Utils/LowerCommentStringPass.cpp
+77-0clang/lib/CodeGen/CodeGenModule.cpp
+66-0clang/docs/LanguageExtensions.rst
+37-0clang/test/CodeGen/loadtime-comment-vars.c
+34-0llvm/test/Transforms/LowerCommentString/loadtime-comment-vars.ll
+8-0clang/lib/CodeGen/CodeGenModule.h
+403-843 files not shown
+418-849 files

FreeNAS/freenas 803d3a1src/middlewared/middlewared/plugins/device_ vrrp_events.py, src/middlewared/middlewared/plugins/failover_ event.py

NAS-141204 / 27.0.0-BETA.1 / Process BACKUP in vrrp rapid-succession branch (#19043)

When VrrpEventThread saw a second rapid event after waiting
rapid_event_settle_time, it dropped the latest queued event and logged a
warning. On boot-time keepalived flaps where the MASTER->BACKUP gap
floors below max_wait, that drop swallowed the only BACKUP signal
middleware was going to see, so vrrp_backup never ran.

Fire the hook for BACKUP (skipping if vrrp_backup already ran this
process lifetime, tracked via a new LAST_EVENT_TYPE attribute on
FailoverEventsService); keep the drop+warn for MASTER, since acting on
an unsettled MASTER would kick off fenced + zpool import.
DeltaFile
+31-1src/middlewared/middlewared/plugins/device_/vrrp_events.py
+16-0src/middlewared/middlewared/plugins/failover_/event.py
+47-12 files

LLVM/project 5d9e965clang/lib/AST ExprConstant.cpp, clang/lib/AST/ByteCode Compiler.cpp

[clang][ExprConst] Support DesignatedInitUpdateExpr of array type (#201000)

I think this should work.
DeltaFile
+8-0clang/lib/AST/ExprConstant.cpp
+8-0clang/test/Sema/constexpr.c
+0-1clang/lib/AST/ByteCode/Compiler.cpp
+16-13 files

NetBSD/pkgsrc cU1JlA8doc CHANGES-2026

   doc: Updated lang/sbcl to 2.6.5
VersionDeltaFile
1.3466+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc G06CfGYlang/sbcl distinfo Makefile

   sbcl: update to 2.6.5

   - minor incompatible change: the condition signalled when an
     accessed slot is missing from an object is no longer a TYPE-ERROR.
   - minor incompatible change: the condition signalled when accessing
     an uninitialized structure slot is no longer a TYPE-ERROR.
   -  minor incompatible change: the implementations of standardized
     functions treating lists as sets, such as INTERSECTION and UNION,
     take more advantage of the freedom to return the elements of the
     result in any order.
   - platform support:
     - add low-level support for floating point state manipulation on
       PPC64/FreeBSD
     - improve the software emulation of displaced instructions on
       ARM64
     - restore building the system using the musl C library
     - fix some SB-SIMD shifting instructions on AVX2
   - enhancement: definition sources for alien callbacks are now
     findable by name in SB-INTROSPECT.

    [24 lines not shown]
VersionDeltaFile
1.90+4-4lang/sbcl/distinfo
1.117+2-2lang/sbcl/Makefile
+6-62 files

LLVM/project 0697815flang/lib/Lower/OpenMP Atomic.cpp

[flang] Fix possibly unused variable (NFC) (#200905)
DeltaFile
+1-1flang/lib/Lower/OpenMP/Atomic.cpp
+1-11 files

FreeBSD/ports 38343dddevel/wasi-compiler-rt22 Makefile, devel/wasi-libcxx22 Makefile

devel/wasi-{compiler-rt,libcxx}22: sync to 22.1.7
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+1-1devel/wasi-compiler-rt22/Makefile
+1-1devel/wasi-libcxx22/Makefile
+2-22 files

LLVM/project 68883a8utils/bazel/llvm-project-overlay/libc BUILD.bazel

[bazel] Port 3db25f8 (#201132)
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+2-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2-01 files