AMDGPU: Add named ArgRange classes for common builtin operands
Name the ranges shared by many builtins after the operand they
constrain: byte/word select indexes, scale_sel, f8f6f4 matrix formats,
and wmma neg flags on variants that do not support negation. NFC.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AMDGPU: Use ArgRange for prefetch cache policy bounds
Only the reserved th value check remains in Sema.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AMDGPU: Use ArgRange for builtin constant argument range checks (#241585)
Replace the manual Sema range checks of constant builtin arguments
with the new ArgRange annotation on the builtin definitions.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[VectorUtils] Propagate cache hint metadata (#241114)
Update `propagateMetadata` in VectorUtils to propagate common cache
hints from the value array. This allows preserving cache hints through
the LoadStoreVectorizer and the SLPVectorizer.
[IR] Centralize cache-hint metadata helpers (#242154)
Cache hint metadata helpers exist in multiple places in LLVM. Centralize
them to a shared location.
[Flang] Fix crash and precision loss in SELECT CASE lowering (#240149)
Lowering INTEGER(16) case values may cause an assertion failure for
negative values and lose precision for large values.
Use createFIRExpr to lower all non-character case values.
Add regression tests for INTEGER(16) case values.
Fixes https://github.com/llvm/llvm-project/issues/239226
[SPIRV] Remove redundant bitcasts for OpLifetimeStart/Stop. (#230623)
These bitcasts were introduced at a time when LLVM lifetime intrinsics
allowed partial coverage of objects whose lifetimes were being
annotated. Now that LLVM `lifetime.start`/`lifetime.stop` annotations
only apply to `alloca`s and do not take in the size argument, it's
easier to follow the SPIR-V spec by emitting `Size = 0` directly on the
`OpVariable` instead. As per SPIR-V spec, void pointers must still be
annotated with their size.
This is similar to the changes at
https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/3278 and is
meant to reduce the output and match the SPIR-V - LLVM translator
implementation.
[BPF] Support preserve_access_index attribute for enum (#232498)
An enum value can only be relocated with __builtin_preserve_enum_value()
or bpf_core_enum_value(), which is easy to forget. Allow the
preserve_access_index attribute on an enum, so that with -g each use of
its enumerators becomes an ENUM_VALUE relocation:
```
enum cgroup_subsys_id {
cpuset_cgrp_id = 0,
memory_cgrp_id = 4,
} __attribute__((preserve_access_index));
struct css_set {
void *subsys[10];
} __attribute__((preserve_access_index));
void *get_mem_css(struct css_set *cset) {
return cset->subsys[memory_cgrp_id];
}
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[RISC-V][MC] Use CoerceFromRegClass for GPRPair operands (#241443)
Avoiding mutation of operands during parsing allows us to retire the
`GPRPair*RV{32,64}` operands that were only needed to avoid pruning
valid match candidates from the matcher search: `parseGPRPair<false>`
had to bail out on RV64 so RV32 pair variants would not prevent matching
RV64 instructions with the same mnemonic (such as `(c.)ld`, P-extension
ops, etc.).
Setting `CoerceFromRegClass = GPR` on `GPRPair*` ensures the register
remains a `GPR` during match and only converts it in `convertToMCInst`.
This allows remonving these old workarounds and fixes some TODOs with
bad diagnostics.
Also fix the malformed `(4)a0`/`(10)s2` memory operands in
`rv32zilsd-invalid.s` that were masked by `parseGPRPair` failing on the
first operand before parsing the memory operand.
Assisted-by: AI tooling
Pull-Request: https://github.com/llvm/llvm-project/pull/241443
[RISC-V][MC] Mostly avoid mutating RegisterOperands during validation (#241023)
Declare `CoerceFromRegClass` on `YGPRRegisterClass`, the non-64-bit
`FPR` classes, and the `VRM2`/`VRM4`/`VRM8` classes so the generated
`AsmMatcher` validates and coerces matched `GPR`/`FPR64`/`VR` operands
during `convertToMCInst` instead of mutating `RISCVOperand`
in-place inside `RISCVAsmParser::validateTargetOperandClass`.
The MCK_GPRAsFPR16/MCK_GPRAsFPR32 cases will be handled in a follow-up
commit.
This will eventually allow us to pass a const operand which will make
these mutation bugs impossible.
Assisted-by: AI tooling
Pull-Request: https://github.com/llvm/llvm-project/pull/241023
[TableGen][AsmMatcher] Support generated register coercion logic (#241022)
When multiple `RegisterClass`es share assembly register names (for
example as the RISC-V sub/super-register FP classes, vector register
groups, or GPR/YGPR), this currently needs to be resolved inside
`validateTargetOperandClass`. One downside of the current approach is
that we end up mutating a RegisterOperand before we have determined
whether it will actually end up being used by the instruction we end
up selecting.
Add a new `CoerceFromRegClass` field on `RegisterClass` so TableGen can
generate the `MCRegister` conversion in `convertToMCInst` automatically.
Once all operands pass `validateOperandClass`, the matched instruction's
ConversionTable row knows the target RegisterClass and emits the
appropriate `convertTo*` call in `convertToMCInst` (without ever calling
validateTargetOperandClass), which avoids mutating partially parsed
operands. Follow-up commits will use this feature to simplify the RISC-V
AsmParser, and I also have changes for other targets.
Assisted-by: AI tooling
Pull-Request: https://github.com/llvm/llvm-project/pull/241022
[RISC-V][MC] Add baseline tests for operand mutation during matching (#241021)
Mutating `RISCVOperand` in-place inside `validateTargetOperandClass` or
custom operand parsers (`parseGPRPair` and `parseGPRPairAsFPR64`)
corrupts operand state across subsequent match table rows when an
earlier row fails on a later operand or feature predicate.
My AI tool wasn't able to come up with a seriously bad mistake that
this causes, but the baseline tests do show a bug here.
Assisted-by: AI tooling
Pull-Request: https://github.com/llvm/llvm-project/pull/241021
IR: Skip parameter attribute combination checks for single attributes
The Verifier checks many pairs of parameter attributes for
incompatibility. Most sets have a single attribute, so only do these
checks when there are multiple.
Whole O3 instructions in opt: kimwitu++ k.bc -0.16%, SPASS cnf.bc
-0.12%, consumer-typeset z08.bc -0.07%, sqlite3 -0.05%.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[VectorUtils] Stabilize cache-hint vectorizer tests
Use the byte-array GEP element type emitted on main so the gather checks also pass in premerge CI. Document that sm_100 and ptx88 are necessary to exercise 256-bit masked stores.
[IR] Strengthen COFF IR verifier check (#159203)
Find issues like the whole-program-vtables one (#87503) earlier.
Also, combine a few of the comdat*.ll verifier checks into one file while I'm adding a diagnostic.
---------
Co-authored-by: Matheus Izvekov <mizvekov at gmail.com>
AMDGPU: Use ArgRange for builtin constant argument range checks
Replace the manual Sema range checks of constant builtin arguments
with the new ArgRange annotation on the builtin definitions.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
