[AMDGPU][GlobalISel] Fold conditional increments and decrements into carry ops (#241985)
#### Problem analysis
- discovered by an independent e-graph based folding rule discoverer
- `AMDGPUCodeGenPrepare` and the GlobalISel legalizer expand integer
division and remainder after the IR optimizations. Each
quotient/remainder correction step is a conditional increment or
decrement, `select c, (add x, 1), x`, so InstCombine never canonicalizes
it.
- The post-legalizer combiner folded `add x, (zext c)` into `G_UADDE`
only when `c` was the carry-out of another add/sub, although compare
results also live in `SCC`/`VCC`. The `select` form was not folded at
all.
- This is the GlobalISel counterpart of #241946, which adds the same
folds to SelectionDAG.
#### Fix
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hwpmc: switch in process PMCs on a thread's first run
A new thread starts in fork_exit(), not mi_switch(), so its PMCs are
not loaded until its next context switch. Call the switch-in hook
there.
Reviewed by: kib, Osvaldo Janeri Filho <ojanerif at amd.com>, mhorne
MFC after: 1 week
Sponsored by: Advanced Micro Devices, Inc.
Differential Revision: https://reviews.freebsd.org/D60565
[SystemZ][z/OS] Use Q-con relocations for references to NoLoad sections in GOFF (#231603)
Emit Q-con relocations instead of A-con relocations when referencing
symbols in NoLoad sections such as DWARF debug data. Because NoLoad
sections are not loaded into memory at runtime, absolute address
constants cannot be computed by the z/OS binder. This resolves binder
errors (IEW2353E / error code 250001) when processing debug information.
---------
Co-authored-by: Yusra Syeda <yusra.syeda at ibm.com>
Co-authored-by: Xing Xue <xingxue at outlook.com>
[libc] Use a syscall wrapper for auxv (#242255)
This PR move auxv initialization behind the centralized syscall
wrappers, following libc/docs/dev/syscall_wrapper_refactor.md.
[libc] Use a syscall wrapper for the Linux Dir helpers (#242254)
This PR move the Linux Dir helpers behind the centralized syscall
wrappers, following libc/docs/dev/syscall_wrapper_refactor.md.
[libc] Use a syscall wrapper for sigaltstack (#242252)
This PR move sigaltstack behind the centralized syscall wrappers,
following libc/docs/dev/syscall_wrapper_refactor.md.
lan867xphy: Add silicon rev D0 configuration
Apply hardware revision D0 configuration from Microchip AN1699
(Revision G). The LSCTL (0x0012) write is deferred until link state
reporting is implemented.
Sponsored by: The FreeBSD Foundation
Sponsored by: Microchip (Hardware)
Differential Revision: https://reviews.freebsd.org/D61269
[InstCombine] Avoid redundant masking of indices in foldCmpLoadFromIndexedGlobal (#242282)
The two checks when checking whether we can mask are currently out of
sync:
bool StrideIsValid = Expr.Flags.hasNoUnsignedSignedWrap()
? !Stride.isNegative()
: Stride.isPowerOf2();
...
if (!Expr.Flags.isInBounds() && Stride.countr_zero() != 0) { ... }
Update the second check to check nusw instead of inbounds.
Removes redundant masking when a GEP has nusw only (no inbounds).
https://alive2.llvm.org/ce/z/tK2bOZ
[AArch64][GlobalISel] Remove renderFPImm32SIMDModImmType4 (#241416)
Using the expansion checks in expandVectorMOVImm we can check that any
fp constant is materializable as a vector movi. This allows us to remove
the existing renderFPImm32SIMDModImmType4 that only handles one type of
immediate, relying on the backend selection instead.
[llvm-exegesis] Generate the random seed only once (#241986)
`randomGenerator()` computes `RandomSeed` on every call, but its static
`std::mt19937` only consumes the first seed. Without an explicit seed,
subsequent calls unnecessarily invoke `std::random_device`.
Make `RandomSeed` static so seed generation happens once.
Profiling `check-llvm` on Fedora x86-64 with libstdc++ showed 7.41% of
sampled CPU cycles in `__x86_rdseed_rdrand`, reached through
llvm-exegesis's `randomGenerator()`.
For the 114 llvm-exegesis regression tests with 14 workers, median
elapsed time across three runs decreased from 72.34s to 3.02s (~24x
faster).
Validation: the llvm-exegesis tests and `check-llvm` passed.
[clang-tidy][NFC] Disable bugprone-unchecked-optional-access check (#242287)
Since this check only consider local-functions, it fails such code:
bar(optional<int> a) {
assert(a && "must be initialized");
std::cout << a.value();
}
```
I think it right now bring too much churn on people writing code in clang-tidy (like https://github.com/llvm/llvm-project/pull/219182) so disable it for now.
mail/rspamd: Update to 4.3.0
Feature release. Adds SMTPUTF8 address syntax checks
(draft-ietf-mailmaint-smtputf8-syntax), explicit phishing rewrite trust
maps, and new symbols for truncated or unreadable archive, OOXML, SVG
and PDF content. HTML, CSS and URL parsing follow browsers more
closely, and the release carries many milter, Redis, DNS, SPF, DMARC,
DKIM and ARC fixes, among them a worker abort on an HTTP request with a
header line without a colon.
Incompatible changes: URL mismatches are scored separately from
phishing, SPF records are evaluated in term order, DKIM rejects
duplicated tags, l=0 and RSA keys under 1024 bits, and symbol options
are stored verbatim and percent-encoded only on output.
ChangeLog: https://github.com/rspamd/rspamd/blob/4.3.0/ChangeLog
[LoongArch] Use INSERT_SUBREG for PseudoXVINSGR2VR into an undefined vector. NFC
When inserting an element into the low half of an undefined LASX vector,
the insert is done on the low 128 bits and the result was widened with
SUBREG_TO_REG. That means that the instruction defining the low 128 bits
also defined the upper 128 bits, which is not the case. Insert the result
into the undefined source vector with INSERT_SUBREG instead, which keeps
its upper 128 bits undefined.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[LoongArch] Use INSERT_SUBREG of IMPLICIT_DEF to widen LSX vectors to LASX. NFC
Several patterns widen a 128-bit LSX vector to a 256-bit LASX vector
with SUBREG_TO_REG, for instructions that only use the low 128 bits:
vext2xv.*, and xvpermi.d followed by an instruction that only uses the
low half of each 128-bit lane. SUBREG_TO_REG means that the instruction
defining the LSX vector also defined the upper 128 bits, which is not
the case and is not needed. Add an lsx_to_lasx helper that uses
INSERT_SUBREG into an IMPLICIT_DEF instead, as other patterns already do
for this kind of widening.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[LoongArch] Use INSERT_SUBREG of IMPLICIT_DEF to put an FP scalar in a LASX vector
The patterns for vector_insert, scalar_to_vector and splat of an FP
scalar into a LASX vector used SUBREG_TO_REG to view the FPR as a vector
register. SUBREG_TO_REG means that the instruction defining the FPR also
defined the rest of the vector register, which is not the case. Only
element 0 is used, and scalar_to_vector leaves the other elements
undefined, which is what INSERT_SUBREG into an IMPLICIT_DEF expresses.
This changes the scheduling and register allocation in one test, but not
the number of instructions.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[LoongArch] Use INSERT_SUBREG of IMPLICIT_DEF for scalar FP rounding via LSX. NFC
fceil, ffloor, ftrunc and froundeven of an FP scalar are selected to a
splat of element 0 of the FPR viewed as an LSX vector, a vector rounding
instruction, and an extract of element 0. Only element 0 is used, so use
INSERT_SUBREG into an IMPLICIT_DEF instead of SUBREG_TO_REG, which means
that the instruction defining the FPR also defined the rest of the
vector register.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU][NFC] Pre-commit test for a deleted conditional f16 load on gfx1250
On gfx1250 (true16), a conditional f16 load whose value reaches a PHI
through a VGPR-to-SGPR copy is deleted: in the new test, the %ld block
ends up with only an implicit-def. Add the test with the current, wrong
output.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[LoongArch] Use INSERT_SUBREG of IMPLICIT_DEF to put an FP scalar in an LSX vector
The patterns for vector_insert, scalar_to_vector and splat of an FP
scalar into an LSX vector used SUBREG_TO_REG to view the FPR as a vector
register. SUBREG_TO_REG means that the instruction defining the FPR also
defined the rest of the vector register, which is not the case. Only
element 0 is used, and scalar_to_vector leaves the other elements
undefined, which is what INSERT_SUBREG into an IMPLICIT_DEF expresses.
This changes the scheduling and register allocation in some tests, but
not the number of instructions.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[flang] Address review comments on chained concatenation fusion
Let concatenation fusion cross operations that only allocate, like the
hlfir.declare of a character literal operand, so that chains ending with a
literal are fused into one buffer. Only operations that may write or free
memory, or whose effects are unknown, now prevent the fusion.
Remove CharacterExprHelper::createConcatenate, which no longer has users.
Add bufferization tests for concatenations whose operands all have a
compile-time length, and for character kind 4.
