13,237,855 commits found in 12 milliseconds
LLVM /project 93ea5b2 — llvm/test/Transforms/LoopInterchange loop-interchange-optimization-remarks.ll fix test
LLVM /project 9a454dd — llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-vectorization.ll loop-interchange-optimization-remarks.ll [LoopInterchange] Disable LoopCacheAnalysis-based heuristic by default
LLVM /project 30d2ac5 — llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange dependency-all-eq.ll pr43176-move-to-new-latch.ll [LoopInterchange] Relax legality check to accept more patterns
LLVM /project 45fe649 — llvm/test/Transforms/LoopInterchange profitability-vectorization.ll address review comment
[LoopInterchange] Add test with dependency `[* =]` and `[= *]` (NFC)
LLVM /project d8f51a2 — llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange dependency-all-eq.ll [LoopInterchange] Change the cost model to interchange `[* =]`
LLVM /project 5a02945 — llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-instorder.ll [LoopInterchange] Take base pointer into account in profitability check
[LoopInterchange] Add test for multiple accesses to same base ptr (NFC)
update test
LLVM /project 0e72407 — llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-instorder.ll interchangeable-outerloop-multiple-indvars.ll [LoopInterchange] Fix instorder profitability check
LLVM /project 5166350 — llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-instorder.ll update
address review comments
Apply suggestion by @tarunprabhu
[LoopInterchange] Add tests for a simple profitable case currently missed (NFC) (#181990)
This patch adds test cases where the heuristic function `instorder` is
somewhat inaccurate, causing the profitability decision to behave
unexpectedly. The root cause is that the heuristic function assumes that
the structure of GEPs "reflect" the original memory access patterns,
which is not always the case. For example, given the following code:
```c
int A[100][100];
for (i = 0; i < 100; i++)
for (j = 0; j < 100; j++)
A[i][j] = ...;
```
The heuristic assumes that the memory access will be transformed into
like:
```llvm
[14 lines not shown ] LLVM /project 661aae4 — clang/test/CXX/drs cwg27xx.cpp cwg31xx.cpp, clang/test/SemaCXX lambda-expressions.cpp [clang] Add tests for some of CWG issues resolved in Croydon (2026-03) (#189299)
This PR adds tests for the following Core issues:
- [CWG2765](https://cplusplus.github.io/CWG/issues/2765.html ) "Address
comparisons between potentially non-unique objects during constant
evaluation";
- [CWG2966](https://cplusplus.github.io/CWG/issues/2966.html ) "Alignment
and value representation of `std::nullptr_t`";
- [CWG3035](https://cplusplus.github.io/CWG/issues/3035.html ) "Lambda
expressions in anonymous unions";
- [CWG3128](https://cplusplus.github.io/CWG/issues/3128.html )
"Potentially-throwing unevaluated operands";
- [CWG3151](https://cplusplus.github.io/CWG/issues/3151.html ) "Closure
types that are `final`";
- [CWG3156](https://cplusplus.github.io/CWG/issues/3156.html ) "Handling
of deleted functions in unevaluated _lambda-captures_".
Additionally, the following Core issues are marked as "N/A", because I
don't think they can be tested:
[16 lines not shown ] cbonsai: Link to MRs
FreeNAS /freenas c373c2a — src/middlewared/middlewared/plugins/acme_dns_authenticator/authenticators ovh.py fix mypy
LLVM /project 9f6031c — llvm/test/CodeGen/AMDGPU/GlobalISel sdivrem.ll udivrem.ll, llvm/test/CodeGen/Thumb2 mve-clmul.ll rebase
Created using spr 1.3.7
Delta File +8,633 -8,584 llvm/test/CodeGen/Thumb2/mve-clmul.ll +1,243 -8,768 llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll +3,436 -2,769 llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll +2,801 -2,109 llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll +0 -4,752 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s +4,549 -0 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test +20,662 -26,982 2,583 files not shown +149,761 -81,866 2,589 files
LLVM /project 176512d — llvm/test/CodeGen/AMDGPU/GlobalISel sdivrem.ll udivrem.ll, llvm/test/CodeGen/Thumb2 mve-clmul.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Delta File +8,633 -8,584 llvm/test/CodeGen/Thumb2/mve-clmul.ll +1,243 -8,768 llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll +3,436 -2,769 llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll +2,801 -2,109 llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll +0 -4,752 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s +4,549 -0 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test +20,662 -26,982 2,583 files not shown +149,761 -81,866 2,589 files
LLVM /project 9365fe2 — llvm/test/CodeGen/AMDGPU/GlobalISel sdivrem.ll udivrem.ll, llvm/test/CodeGen/Thumb2 mve-clmul.ll rebase
Created using spr 1.3.7
Delta File +8,633 -8,584 llvm/test/CodeGen/Thumb2/mve-clmul.ll +1,243 -8,768 llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll +3,436 -2,769 llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll +2,801 -2,109 llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll +0 -4,752 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s +4,549 -0 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test +20,662 -26,982 2,583 files not shown +149,761 -81,866 2,589 files
LLVM /project d483a6a — llvm/test/CodeGen/AMDGPU/GlobalISel sdivrem.ll udivrem.ll, llvm/test/CodeGen/Thumb2 mve-clmul.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Delta File +8,633 -8,584 llvm/test/CodeGen/Thumb2/mve-clmul.ll +1,243 -8,768 llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll +3,436 -2,769 llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll +2,801 -2,109 llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll +0 -4,752 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s +4,549 -0 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test +20,662 -26,982 2,583 files not shown +149,761 -81,866 2,589 files
LLVM /project f1349c1 — llvm/test/CodeGen/AMDGPU/GlobalISel sdivrem.ll udivrem.ll, llvm/test/CodeGen/Thumb2 mve-clmul.ll Removed builtin and use of uintptr_t
Created using spr 1.3.7
Delta File +8,633 -8,584 llvm/test/CodeGen/Thumb2/mve-clmul.ll +1,243 -8,768 llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll +3,436 -2,769 llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll +2,801 -2,109 llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll +0 -4,752 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s +4,549 -0 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test +20,662 -26,982 2,583 files not shown +149,761 -81,866 2,589 files
LLVM /project 9deb4fd — llvm/test/CodeGen/AMDGPU/GlobalISel sdivrem.ll udivrem.ll, llvm/test/CodeGen/Thumb2 mve-clmul.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Delta File +8,633 -8,584 llvm/test/CodeGen/Thumb2/mve-clmul.ll +1,243 -8,768 llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll +3,436 -2,769 llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll +2,801 -2,109 llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll +0 -4,752 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s +4,549 -0 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test +20,662 -26,982 2,582 files not shown +149,758 -81,857 2,588 files
[X86] Add atomic vector store tests for unaligned >1 sizes. (#197372)
Unaligned atomic vector stores with size >1 are lowered to calls.
Adding their tests separately here.
Store-side counterpart to #148896. Stacked below #197165. LLVM /project 7d27a76 — llvm/lib/IR Constants.cpp AsmWriter.cpp, llvm/test/Assembler constant-splat.ll [LLVM][AsmWriter] Fix ConstantFP zeroinitializer check (#196097)
It turns out ppc_fp128 has a value where isPosZero() returns true but
isNullValue() returns false. LLVM /project 431f757 — llvm/test/CodeGen/AArch64 sve-multivector-loads.ll, llvm/test/Transforms/LoopVectorize/X86 masked_load_store.ll Merge branch 'main' into users/kasuga-fj/da-consolidate-acc-gcd LLVM /project e43fcb0 — llvm/lib/Target/X86/AsmParser X86AsmParser.cpp, llvm/test/CodeGen/X86 inline-asm-intel-negative-scale.ll [X86] Fix Invalid assembly given inverted meaning (#190460)
Previously, `lea rax, [rax - 8 * rdx]` would be misassembled as `lea rax, [rax + 8 * rdx]` when a program with this line should've been rejected.
This patch rejects the invalid program and cleans up some misleading `unknown token in expression` diagnostics that came up in similar programs.
Fixes: https://github.com/llvm/llvm-project/issues/96427 LLVM /project 84fab94 — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64Subtarget.cpp, llvm/test/CodeGen/AArch64 sve-multivector-loads.ll [LLVM][CodeGen][SVE] Lower to multivector loads instead of splitting them. (#150421)
NOTE: Transformation requires subreg liveness because otherwise register allocation can introduce unnecessary copies. NetBSD /pkgsrc SAaETvX — devel/gmake distinfo, devel/gmake/patches patch-src_getopt.h patch-lib_fnmatch.c gmake: Fix for modern C.
LLVM /project 393d3e4 — llvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel legalizer-info-validation.mir [RISCV][GlobalISel] Remove dependency on legal ruleset (#197377)
This fills in always legal rules, to remove the dependency on the legacy
ruleset. I'm really not sure about the truncate rule but all tests pass.
This is not guaranteed to be all the rules, just the ones that appear in
tests. 