AMDGPU: Use subarch triples in more unit tests
Avoid looking up the target by the cpu name with the legacy
amdgcn name.
Co-authored-by: Claude (Claude-Opus-4.8)
[DTLTO] Add remote compiler option forwarding coverage (#208589)
Add a cross-project DTLTO test that checks the existing LTO
configuration state serialized into the remote Clang command line. The
test uses the validate.py distributor to inspect the generated DTLTO
JSON.
Cover all the existing forwarded options.
Add paired negative checks for optional flags so the test also verifies
they are not emitted when the corresponding configuration state is not
set.
[CodeGen][ARM64EC] Copy first four arguments to FP registers in vararg exit thunks (#209581)
ARM64EC vararg functions receive all types of the first four arguments
in x0-x3. Because x86_64 expects floating-point arguments in FP
registers, always copy x0-x3 to d0-d3 in the exit thunks, matching
MSVC's behavior.
[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic
The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.
Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:
- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
Operations use APInt arithmetic at WideBits, chosen to guarantee no
intermediate overflow:
$$
WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
$$
This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
extra bits.
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mvc: tab/subtab form generation align with what base_form expects, closes https://github.com/opnsense/core/issues/10535
As these are hardly used, we missed these during our testing.
While here, cleanup the code a bit further and stop using index assignments to refer to content [0],[1],..
AMDGPU: Reland: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3
For V_DOT2_F32_F16 and V_DOT2_F32_BF16 add their VOPDName and mark
them with usesCustomInserter which will be used to add pre-RA register
allocation hints to preferably assign dst and src2 to the same physical
register. When the hint is satisfied, canMapVOP3PToVOPD recognises the
instruction as eligible for VOPD pairing by checking if it is VOP2 like:
dst==src2, no source modifiers, no clamp, and src1 is a register.
Mark both instructions as commutable to allow a literal in src1 to be
moved to src0, since VOPD only permits a literal in src0.
Original patch had a bug where it did not check if physical src
registers match register class of appropriate operand in fullVOPD
instructions, check is now done via isValidVOPDSrc.
[IR] Add elementwise modifier to atomic loads (#204556)
Add an `elementwise` modifier to atomic loads to represent
per-element atomic semantics for fixed-vector loads.
Without the modifier, a vector atomic load remains a whole-value
atomic operation. With `elementwise`, the load behaves as if it were
expanded into one scalar atomic load per fixed-vector element, without
providing atomicity for the vector value as a whole.
Discussion:
https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomic-loads-and-stores/91100
Revert "[X86] Remove redundant `cmp` before `adc` after `lzcnt` or `tzcnt`" (#210006)
Reverts #208392 - while we investigate a miscompile due to CF/ZF mismatch
AMDGPU: Validate VOPD/VOPD3 physical source registers against operand RC
Replace isVGPR checks with isValidVOPDSrc that validates physical source
registers against the actual combined VOPD/VOPD3 instruction's operand
register classes. Now we also validate operands for VOPD instructions.
[RISC-V] Make Short Forward Branches capable of matching Zibi instructions (#208637)
Add new SFB patterns to make `PseudoCCMOVGPR` capable of matching `beqi`
and `bnei`, so that it can be folded into `PseudoCC*` of `SFBALU_rr`
variants
[AMDGPU] Reject sub-dword format buffer loads and stores (#209703)
An i8 `buffer.{load,store}.format` has no corresponding hardware
instruction so diagnose it in SelectionDAG and fail legalization in
GlobalISel instead of emitting invalid format opcodes
netstat(1) prints interface multicast counter.
Use -g option as modifier for -i, -I, and -w to show per interface
multicast packet counter. Make -q more specific to suppress 0 for
values actually printed.
input and OK claudio@
AMDGPU: Convert tests to use subarch from triples in the file
This set was using target triple in the source rather than command
line arguments.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[CycleInfo] Store cycles in a flat preorder array. NFC
Store cycles by value in one array in cycle-forest preorder, each cycle
immediately followed by its descendants, instead of heap-allocating each
cycle and holding its children in a std::vector<std::unique_ptr<>>.
Child and top-level iteration become pointer arithmetic that skips a
subtree via a new NumDescendants count, and sizeof(GenericCycle) drops
from 72 to 48. GenericCycleInfoCompute builds the forest with temporary
nodes, then flatten() moves it into the array.
GenericCycle still exposes raw pointers into this array. The eventual
goal is to replace them with an opaque handle, so all access goes
through GenericCycleInfo and the storage stays an implementation detail.
Aided by Fable 5
Pull Request: https://github.com/llvm/llvm-project/pull/209981
AMDGPU: Migrate MIR parser tests to new subarch triples (59) (#209819)
Mechanical migration by script.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
AMDGPU: Migrate DebugInfo tests to new subarch triples (58) (#209818)
Mostly mechanical by script
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
