Dreckly/dreckly d50ba08 — textproc/libxls Makefile distinfo

libxls: Update to 1.6.3
DeltaFile
+4-4textproc/libxls/distinfo
+2-2textproc/libxls/Makefile
+6-62 files

LLVM/project d789b97 — llvm/include/llvm/ObjectYAML COFFYAML.h, llvm/lib/ObjectYAML COFFEmitter.cpp COFFYAML.cpp

[yaml2obj][COFF] Add BBAddrMap support to yaml2coff (#224504)
DeltaFile
+326-0llvm/test/tools/yaml2obj/COFF/bb-addr-map.yaml
+174-0llvm/test/tools/yaml2obj/COFF/bb-addr-map-pgo-analysis-map.yaml
+20-7llvm/lib/ObjectYAML/COFFYAML.cpp
+19-0llvm/lib/ObjectYAML/COFFEmitter.cpp
+16-0llvm/test/tools/yaml2obj/COFF/section-semantic-content.yaml
+3-0llvm/include/llvm/ObjectYAML/COFFYAML.h
+558-76 files

Dreckly/dreckly c09b656 — net/libslirp Makefile distinfo, net/libslirp/patches patch-src_libslirp.h

libslirp: Update to 4.9.3
DeltaFile
+5-5net/libslirp/patches/patch-src_libslirp.h
+5-5net/libslirp/distinfo
+3-4net/libslirp/Makefile
+13-143 files

LLVM/project 74f859b — clang-tools-extra/clang-tidy/readability TrailingCommaCheck.cpp, clang-tools-extra/docs ReleaseNotes.md

[clang-tidy] Fix readability-trailing-comma false positive on #endif (#219634)

The `readability-trailing-comma` check looks at the token immediately
before an enum's closing brace to decide whether a trailing comma is
present. When the last enumerators are wrapped in `#ifdef` / `#else` /
`#endif`, that token is the directive identifier `endif`, so the check
reports a missing comma and `-fix` inserts `,` after `#endif`. That is
outside the enumerator list and corrupts the source even when every
enumerator already has a trailing comma.

Skip the diagnostic when the token before `}` is a preprocessor
directive (`#` or a token preceded by `#`). An enumerator whose name
happens to be `endif` is still diagnosed, because it is not preceded by
`#`.

Fixes #218957
DeltaFile
+46-0clang-tools-extra/test/clang-tidy/checkers/readability/trailing-comma.cpp
+19-3clang-tools-extra/clang-tidy/readability/TrailingCommaCheck.cpp
+13-0clang-tools-extra/test/clang-tidy/checkers/readability/trailing-comma-cxx11.cpp
+4-0clang-tools-extra/docs/ReleaseNotes.md
+82-34 files

LLVM/project b5cae89 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer consecutive-access.ll

[SLP]Fix fmul/fadd fusion costs and retry FMA seeds after all blocks

Fix the cost for the scalar of fmul+fadd pairs: fused fmul lanes add
the full fmul cost, fadd lanes with gathered fmuls were costed as
fmuladd, and the FMulAdd combine missed fmuls in the second operand,
c - a*b and constant lanes. Cost fused fmul lanes at (fmuladd - fadd),
such fadd lanes at (fmuladd - fmul), form the combine for either
operand, and treat a multi-use reduction root as fused. Extract nodes
take no credit for extracts the target folds into their users.

Reviewers: RKSimon, bababuck, MrSidims

Pull Request: https://github.com/llvm/llvm-project/pull/226117
DeltaFile
+275-54llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+77-89llvm/test/Transforms/SLPVectorizer/AArch64/loop-accumulator-reduction.ll
+22-41llvm/test/Transforms/SLPVectorizer/consecutive-access.ll
+31-30llvm/test/Transforms/SLPVectorizer/AArch64/fma-chain-no-alt-node-reduction.ll
+31-18llvm/test/Transforms/SLPVectorizer/AArch64/hor-fp-reduction-instcount.ll
+25-23llvm/test/Transforms/SLPVectorizer/AArch64/fmul-constant-lane-fmuladd-combine.ll
+461-25512 files not shown
+568-34718 files

LLVM/project 2fa97ac — clang/lib/AST ExprConstShared.h ExprConstant.cpp, clang/lib/AST/ByteCode EvaluationResult.h Pointer.cpp

Reapply "[clang][bytecode] Stop relying on `CheckEvaluationResult()` … (#226879)

…(… (#226637)

This reverts commit e0316c1b4762263caa49e3c41ddde752a2b6b775.

This time we also check `Pointee.isInitialized()` in
`PtrView::isInitialized()` to catch cases where we call `invokeDtor()`
on a Block.
DeltaFile
+381-1clang/lib/AST/ByteCode/EvaluationResult.cpp
+49-100clang/lib/AST/ExprConstant.cpp
+49-27clang/lib/AST/ByteCode/EvalEmitter.cpp
+42-0clang/lib/AST/ExprConstShared.h
+17-23clang/lib/AST/ByteCode/Pointer.cpp
+22-10clang/lib/AST/ByteCode/EvaluationResult.h
+560-16114 files not shown
+629-18920 files

OPNSense/plugins 55856d4 — net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/Migrations M1_1_0.php

net/frr: Guard M1_1_0.php migration so it doesn't get executed for unrelated frr models
DeltaFile
+7-0net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/Migrations/M1_1_0.php
+7-01 files

OPNSense/plugins 7f5c7fd — net/frr/src/opnsense/mvc/app/views/OPNsense/Quagga ospf6.volt ospf.volt

net/frr: OSPF/OSPFv3 move tabs around to reflect natural configuration order
DeltaFile
+2-2net/frr/src/opnsense/mvc/app/views/OPNsense/Quagga/ospf.volt
+1-1net/frr/src/opnsense/mvc/app/views/OPNsense/Quagga/ospf6.volt
+3-32 files

OPNSense/plugins e6232ad — net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/Migrations M1_1_5.php

net/frr: The trim in M1_1_5.php is not needed
DeltaFile
+0-1net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/Migrations/M1_1_5.php
+0-11 files

OPNSense/plugins 9df97b5 — net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms ospf.xml dialogEditOSPFInterface.xml, net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga OSPF.xml

net/frr: OSPF passive interface moves to correct spot, the interface configuration
DeltaFile
+74-0net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/Migrations/M1_1_5.php
+5-8net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/OSPF.xml
+11-0net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/dialogEditOSPFInterface.xml
+3-7net/frr/src/opnsense/service/templates/OPNsense/Quagga/Config/ospfd.conf
+0-6net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/ospf.xml
+93-215 files

OPNSense/plugins 737b483 — net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms dialogEditOSPF6Area.xml, net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga OSPF6.xml OSPF.xml

net/frr: make OSPF and OSPFv3 areas explicit
DeltaFile
+130-0net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/Migrations/M1_1_4.php
+53-37net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/OSPF.xml
+52-8net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/OSPF6.xml
+56-0net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/dialogEditOSPF6Area.xml
+31-22net/frr/src/opnsense/service/templates/OPNsense/Quagga/Config/ospf6d.conf
+28-22net/frr/src/opnsense/service/templates/OPNsense/Quagga/Config/ospfd.conf
+350-8910 files not shown
+450-15116 files

OPNSense/plugins 4266881 — net/frr Makefile pkg-descr

net/frr: Bump version to 1.60 (new major release) and add additional migration notes and changelog
DeltaFile
+25-0net/frr/pkg-descr
+1-2net/frr/Makefile
+26-22 files

OPNSense/plugins fd1cbe2 — net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms dialogEditOSPFInterface.xml dialogEditOSPF6Interface.xml

net/frr: OSPF/OSPFv3 Passive interface should be visible by default in grid
DeltaFile
+0-1net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/dialogEditOSPFInterface.xml
+0-1net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/dialogEditOSPF6Interface.xml
+0-22 files

OPNSense/plugins 3f53a02 — net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga STATICd.xml RIP.xml

net/frr: Update model versions to the latest migration state so these won't trigger the migrations again in the future
DeltaFile
+1-1net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/STATICd.xml
+1-1net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/RIP.xml
+1-1net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/OSPF6.xml
+1-1net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/General.xml
+1-1net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/BGP.xml
+1-1net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/BFD.xml
+6-66 files

OPNSense/plugins 3a7b49a — net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga OSPF6.xml OSPF.xml

net/frr: OSPF/OSPFv3 Interface should be required and exclude firewall group interfaces
DeltaFile
+2-0net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/OSPF6.xml
+2-0net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/OSPF.xml
+4-02 files

LLVM/project 8af4ce8 — clang/include/clang/CIR/Dialect/IR CIROps.td, clang/test/CIR/CodeGen tls-model.cpp pragma-fenv_access.c

Make CIR assembly formats strict properties compatible (#226600)

Bind inherent attributes explicitly in CIR operation formats and update
assembly tests for the resulting syntax.

Assisted-by: Codex
DeltaFile
+367-367clang/test/CIR/CodeGen/pragma-fenv_access.c
+54-56clang/test/CIR/Lowering/fenv.cir
+51-52clang/test/CIR/IR/fenv.cir
+38-38clang/test/CIR/CodeGenCXX/vtable-linkage.cpp
+44-23clang/include/clang/CIR/Dialect/IR/CIROps.td
+32-32clang/test/CIR/CodeGen/tls-model.cpp
+586-56870 files not shown
+897-88776 files

FreeBSD/ports 3161082 — dns/knot3 Makefile pkg-plist

dns/knot3: Don't abuse DOCS for MANPAGES

The %%DOCS%% substitution was both installing the manpages
and the documentation, so fix that by using MANPAGES instead.

While here:
- Remove option descriptions for IDN and DOCS since
  they are already defined in Mk/bsd.options.desc.mk.
- Pet portclippy.

PR:             298789
Approved by:    osa, vvd (Mentors, implicit)
Co-authored-by: Vladimir Druzenko <vvd at FreeBSD.org>
DeltaFile
+13-13dns/knot3/pkg-plist
+12-11dns/knot3/Makefile
+25-242 files

LLVM/project bd20a94 — clang-tools-extra/docs/clang-tidy/checks/readability simplify-boolean-expr.md

address feedback

Amp-Thread-ID: https://ampcode.com/threads/T-01a0e7bb-8147-70b8-bc11-7e1797f4a174
Co-authored-by: Zeyi Xu <zeyi2 at nekoarch.cc>
DeltaFile
+6-6clang-tools-extra/docs/clang-tidy/checks/readability/simplify-boolean-expr.md
+6-61 files

LLVM/project 5d8b594 — llvm/lib/Frontend/OpenMP OMPDescriptors.inc

[OpenMP] Update modifier set properties on some clauses (#226508)

The modifier sets on DEPEND, NUM_TEAMS and REDUCTION in 6.1 only have
the exclusive property.
DeltaFile
+3-3llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
+3-31 files

LLVM/project cf5a39d — llvm/lib/Frontend/OpenMP OMPDescriptors.inc

[OpenMP] Add/update descriptors for extension clauses (#226509)
DeltaFile
+36-8llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
+36-81 files

LLVM/project f8c431c — llvm/lib/Target/AMDGPU CMakeLists.txt AMDGPUHWEvents.h, llvm/unittests/Target/AMDGPU CMakeLists.txt AMDGPUEventTrackingTest.cpp

[AMDGPU][NewInsertWaitcnt] Add Event Tracker

See #226335

Introduction

Adds the basic infrastructure needed to track in-flight records for each `InstCounterType`.
This is not a full replacement of `SIInsertWaitcnts::WaitcntBrackets` and it does not
aim to be one.

One goal with the new implementation is to avoid having a single "tracker" class
that does everything. Instead, the `EventTracker` aims to do one thing and do it right:
preserve the history of a counter (instructions + events issued) and the value of the counter.
Any specific queries, such as "what STORE_CNT do I need to use this RU" is something that belongs
to helper methods in the client of the class or a utils file.

Class Design

This class is designed to use a single "source of truth" for all information, which is a compact

    [33 lines not shown]
DeltaFile
+618-0llvm/unittests/Target/AMDGPU/AMDGPUEventTrackingTest.cpp
+477-0llvm/lib/Target/AMDGPU/AMDGPUEventTracking.cpp
+354-0llvm/lib/Target/AMDGPU/AMDGPUEventTracking.h
+27-0llvm/lib/Target/AMDGPU/AMDGPUHWEvents.h
+1-0llvm/unittests/Target/AMDGPU/CMakeLists.txt
+1-0llvm/lib/Target/AMDGPU/CMakeLists.txt
+1,478-06 files

LLVM/project d8b7da9 — llvm/include/llvm-c DebugInfo.h, llvm/include/llvm/BinaryFormat Dwarf.def Dwarf.h

[DWARF] Support Roc Language (#225631)

The Roc language has been assigned language codes for DWARF v5 and v6.
See [DWARF Issue 260821.1](https://dwarfstd.org/issues/260828.1.html).
DeltaFile
+29-0llvm/test/DebugInfo/Generic/compileunit-source-language-name-roc.ll
+7-0llvm/include/llvm/BinaryFormat/Dwarf.h
+2-0llvm/include/llvm/BinaryFormat/Dwarf.def
+1-0llvm/lib/BinaryFormat/Dwarf.cpp
+1-0llvm/include/llvm-c/DebugInfo.h
+40-05 files

LLVM/project 3eb90f5 — llvm/lib/Transforms/Vectorize VPlan.h VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize replicate-region-branch-weights.ll

[VPlan] Distribute execution frequencies with BlockFrequencyInfo's code. (#226841)

Instead of hand-rolling frequency propagating, manually construct BFI
and use BFI::distributeMass.

Adds a final step where frequencies are rounded up to at least one, to
distinguish between unreachable and almost never executed blocks. This
matches BFI behavior.

Note that we need to still track whether frequencies are from edges with
unknown profile info.

PR: https://github.com/llvm/llvm-project/pull/226841
DeltaFile
+46-45llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+31-43llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
+64-6llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
+18-18llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
+2-3llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+3-1llvm/lib/Transforms/Vectorize/VPlan.h
+164-1166 files

FreeBSD/ports 021c9ad — net/zsync distinfo pkg-message

net/zsync: Update 0.6.6 => 0.8.0

Upstream moved to GitHub and rewrote zsync in Go.
It's recommended to check the details from changelog.

While here:
- Create a pkg-message to include this information.
- Add TESTING_UNSAFE, since it requires Apache webserver
  running and have recursive directory problems.

Changelog:
https://github.com/cph6/zsync/blob/v0.8.0/NEWS

PR:             298908
Approved by:    osa, vvd (Mentors, implicit)
DeltaFile
+14-14net/zsync/Makefile
+12-0net/zsync/pkg-message
+5-3net/zsync/distinfo
+31-173 files

LLVM/project 141ad3d — mlir/include/mlir/Dialect/LLVMIR NVVMOps.td, mlir/test/Dialect/LLVMIR nvvm_check_target_sm.mlir

[MLIR][NVVM] Add SM version requirements to mbarrier Ops (#224105)

The mbarrier Ops had no `NVVMRequiresSM` trait, so a `gpu.module`
targeting an older chip (e.g. `sm_75`) accepted them, and the error only
showed up later. This adds the trait to all 13 of them, same as #192257
and `mbarrier.check_layout` in #217252.

| floor | Ops |
|---|---|
| `sm_80` | `init`, `inval`, `arrive`, `arrive_drop`,
`arrive.nocomplete`, `arrive_drop.nocomplete`, `test.wait` |
| `sm_90` | `expect_tx`, `complete_tx`, `arrive.expect_tx`,
`arrive_drop.expect_tx`, `try_wait`, `try_wait.parity` |

The floors come from the Target ISA Notes in the [PTX ISA
8.5](https://docs.nvidia.com/cuda/pdf/ptx_isa_8.5.pdf) (section
9.7.12.15), and they match the backend: every Op that lowers to an
intrinsic fails to compile one arch below its floor and compiles at it.
`arrive_drop` at sm_80 relies on #222916.

    [17 lines not shown]
DeltaFile
+206-0mlir/test/Dialect/LLVMIR/nvvm_check_target_sm.mlir
+22-13mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+228-132 files

LLVM/project a92cdc4 — llvm/lib/Target/AMDGPU CMakeLists.txt AMDGPUHWEvents.h, llvm/unittests/Target/AMDGPU CMakeLists.txt AMDGPUEventTrackingTest.cpp

[AMDGPU][NewInsertWaitcnt] Add Event Tracker

See #226335

Introduction

Adds the basic infrastructure needed to track in-flight records for each `InstCounterType`.
This is not a full replacement of `SIInsertWaitcnts::WaitcntBrackets` and it does not
aim to be one.

One goal with the new implementation is to avoid having a single "tracker" class
that does everything. Instead, the `EventTracker` aims to do one thing and do it right:
preserve the history of a counter (instructions + events issued) and the value of the counter.
Any specific queries, such as "what STORE_CNT do I need to use this RU" is something that belongs
to helper methods in the client of the class or a utils file.

Class Design

This class is designed to use a single "source of truth" for all information, which is a compact

    [33 lines not shown]
DeltaFile
+618-0llvm/unittests/Target/AMDGPU/AMDGPUEventTrackingTest.cpp
+476-0llvm/lib/Target/AMDGPU/AMDGPUEventTracking.cpp
+354-0llvm/lib/Target/AMDGPU/AMDGPUEventTracking.h
+28-0llvm/lib/Target/AMDGPU/AMDGPUHWEvents.h
+1-0llvm/unittests/Target/AMDGPU/CMakeLists.txt
+1-0llvm/lib/Target/AMDGPU/CMakeLists.txt
+1,478-06 files

LLVM/project 933d454 — clang/include/clang/Basic BuiltinsAMDGPUDocs.td, clang/test/CodeGenOpenCL builtins-amdgcn-gfx13.cl

[AMDGPU] Add intrinsics and builtins for v_wave_match_b32
DeltaFile
+91-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.match.b32.ll
+81-9llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+21-0clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+19-0clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
+12-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+9-0clang/test/SemaOpenCL/builtins-amdgcn-wave-match-err.cl
+233-99 files not shown
+262-1215 files

LLVM/project 68bf518 — llvm/include/llvm/Object OffloadBinary.h, llvm/lib/Object OffloadBinary.cpp

[Offloading] Add support for compressed OffloadBinary types

Summary:
Offload binaries are used to store many heterogenous architectures into
a singel offloading blob. These lists can get very large so this PR adds
the option to compress them with the LLVM provided compression
libraries.

The implementation is quite simple, we simply compress all the buffers
after the header into a single compressed blob, then re-construct the
header. Extracting is the reverse.

The biggest change is that the offload binary now **owns** the memory,
whereas before we simply took a reference to it. This is necessary
because the decompression must create new memory compared to what the
user provided. This adds an extra copy internally, but it also
simplifies the V2 additions.

This does not wire up any clang/HIP support, just providing the
functionality.
DeltaFile
+134-49llvm/lib/Object/OffloadBinary.cpp
+78-0llvm/unittests/Object/OffloadingTest.cpp
+28-19llvm/include/llvm/Object/OffloadBinary.h
+41-0llvm/test/tools/llvm-objdump/Offloading/compressed.test
+35-3llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp
+23-8llvm/tools/obj2yaml/offload2yaml.cpp
+339-7913 files not shown
+500-9719 files

LLVM/project e076201 — clang/lib/Serialization ASTReader.cpp

remove, rely on error
DeltaFile
+1-7clang/lib/Serialization/ASTReader.cpp
+1-71 files

LLVM/project 59ae066 — clang/lib/Serialization ASTReader.cpp, llvm/include/llvm/Support Compression.h

[Support] Infer compression format from zlib and zstd headers

Summary:
Identify compressed streams from their bitstream headers so callers can
decompress without naming the format. Recognize every valid RFC 1950
zlib header and the zstd frame magic, and reuse that for
getReasonIfUnsupported and decompress. Collapse the AST reader onto the
new helpers.
DeltaFile
+48-0llvm/lib/Support/Compression.cpp
+42-0llvm/unittests/Support/CompressionTest.cpp
+4-8clang/lib/Serialization/ASTReader.cpp
+7-0llvm/include/llvm/Support/Compression.h
+101-84 files