Keep zettarepl's encrypted record call working on targets
## Problem
Replication sources call `pool.dataset.insert_or_update_encrypted_record` over midclt on the target to store the target dataset's key. That private method was removed when encryption moved to `zfs.resource.encryption`, so replicating to a target on this version would fail after the stream was received and leave the encrypted dataset without a stored key, meaning it would not unlock on reboot.
## Solution
Restored the private method on `pool.dataset` with its original payload, forwarding to `zfs.resource.encryption.store_key`. Also trimmed encryption docstrings that repeated the API model field descriptions and corrected which supplied keys get stored on unlock.
AMDGPU: Stop relying on -amdgpu-scalarize-global-loads=false in ALU tests
Convert kernels which loaded operands from pointer arguments into
functions taking the operands as arguments. Scalar kernel arguments become
inreg arguments. Where a kernel is still useful, index the loads by the
workitem id so they remain vector loads. This also fixes a few tests where
the workitem id index was computed but unused, or where the uniform
workgroup id was used for indexing in VALU tests.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AArch64: Test trap-after-noreturn against the exception model (#229681)
Unfortunately, the AArch64TargetMachine modifies
TargetOptions::TrapUnreachable if MCAsmInfo::usesWindowsCFI(). Thus,
by default, a trap after a noreturn call is emitted on COFF targets with the
default exception mode. There was no test coverage for this case's interaction
with an overridden exception model. Add the missing test in preparation for
cleaning up both the MC side exception predicates and TrapUnreachable mutation.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
[TargetInstrInfo] Add C inline asm statements to greedy-inline-asm-fold.mir
Show the C source behind each test so it's clear which MIR operand
corresponds to which asm constraint. Also reword the first test's
comment per review.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
RISCV: Do not add a live VL def to inline asm that clobbers it (#229246)
Inline asm that already clobbers VL or VTYPE was given an additional
live implicit def of the same register, contradicting the dead clobber
def.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AArch64] Codegen for AArch64 Return Address Authentication Hardening (#176187)
This patch implements the code generation for AArch64's Return Address
Authentication Hardening, a mitigation [1] against the PACMAN attack [2]
[3].
A new function attribute, "sign-return-address-harden", is plumbed
through AArch64MachineFunctionInfo and interpreted by the AArch64
pointer authentication logic. When set to "load-return-address", the
backend emits a load from the return address before the return
instruction.
A corresponding module flag is also added. This is used by the compiler
to know if compiler-created functions should have the hardening or not.
The code sequence selected depends on whether or not the target has
FEAT_PAUTH. This feature indicates the availability of non-hint space
Pointer Authentication instructions. If FEAT_PAUTH is on, this is an
example of a code sequence:
[30 lines not shown]
LoongArch: Stop setting kill flags on virtual registers before FinalizeISel (#229019)
These is no point to maintaining these before register allocation anymore.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AMDGPU: Remove promotion of 32 and 64-bit atomic load/store types
The atomic load and store patterns now cover all 32 and 64-bit register types,
so there is no need to coerce to integer for selection. Mark the 16-bit vector
types as legal for atomic load and store rather than expanding them.
This fixes failing on atomic load and store of v2bf16 and v4bf16 which were
never promoted and ended up expanded.
The f16 and bf16 scalar cases are still promoted since the 16-bit atomic
patterns only cover i16 and i32, though that also should be fixed.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[CIR] Support __builtin_coro_align (#228821)
Support `__builtin_coro_align` in ClangIR:
- Add `CIR_CoroAlignOp` (`cir.coro.intrinsic.align`) in `CIROps.td` with
TableGen lowering to `llvm.coro.align`.
- Handle `Builtin::BI__builtin_coro_align` in `CIRGenBuiltin.cpp`.
- Add roundtrip (`clang/test/CIR/IR/coro-align.cir`) and DirectToLLVM
lowering (`clang/test/CIR/Lowering/coro-align.cir`) tests.
- Test `__builtin_coro_align()` in
`clang/test/CIR/CodeGenCoroutines/coro-builtins.cpp` with both CIR and
LLVM checks for parity with classic Clang CodeGen.
Closes #228764
Assisted by Antigravity and reviewed by Aman Maurya.
AMDGPU: Use normal load/store pattern type lists for atomics (#229688)
Atomic load and store of vector types are now permitted in the IR. Instead
of maintaining separate scalar-only atomic pattern lists, cover atomic
load/store in the existing per-register-type pattern loops. As a side effect
-flat-for-global is respected in more cases.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
