[APFloat][NFC] Generalize bitcast to also cover x87 semantics (#209781)
This removes the special case code for bitcasting APInt to a float with
x87 semantics in convertF80LongDoubleAPFloatToAPInt. This makes it
consistent with previous removal of special cases and will remove one
more small obstacle to making APFloat extensible.
[lldb] Fix C++ expression evaluation with the MS C++ ABI (#212521)
IRForTarget didn't correctly handle the Microsoft C++ ABI when preparing
JIT'd expressions:
- `CreateResultVariable` could match a compiler generated dynamic
initializer function instead of the result variable, since both share
the same mangled substring under the MS ABI.
- `RemoveCXAAtExit` only stripped `__cxa_atexit` calls (Itanium ABI). On
the MS ABI, static destructors are registered via plain `atexit`.
Example:
```cpp
struct Foo {
Foo() : x(42) {}
~Foo() {}
int x;
};
[20 lines not shown]
[mlir][tosa] Remove availability interfaces from profile conformance (#207809)
This commit removes the "QueryProfileInterface" and
"QueryExtensionInterface" as they are superfluous in most cases, with
TosaComplianceData.h.inc already providing much of the data we need.
Removing these also helps prevent mistakes as observed in:
https://github.com/llvm/llvm-project/pull/206687
This commit removes these interfaces and updates the profile conformance
to extract supported profile/extension information from
TosaComplianceData.h.inc instead.
One factor that isn't duplicated is operations that rely on extensions,
but do not declare any data type support. This is a small set of
operations, such as tosa.custom, tosa.cond_if, tosa.while_loop and
tosa.const_shape, and we can add them to the TosaComplianceData.h.inc
file as needed.
[Clang][AMDGPU] Add amdgpu_av("none") attribute for atomic expressions
Add a statement attribute that suppresses MakeAvailable/MakeVisible
cache operations on AMDGPU atomic instructions while preserving memory
ordering (waits).
The attribute takes a string argument specifying the mode. Currently "none" is
the only supported mode. The resulting atomic or fence instruction carries !mmra
!{!"amdgcn-av", !"none"} metadata.
Assisted-By: Claude Opus 4.6
[LLVM][InstCombine] Add simplification of SVE compare intrinsics. (#211249)
Extends SVEIntrinsicInfo to accept LLVM IR compare information, which is
then used to call simplifyCmpInst on the data operands of SVE compare
intrinsic calls.
[AArch64][SelectionDAG] Avoid cross-bank copy for NEON vcvtfp2fx result (#210275)
- Add SelectionDAG-only patterns for NEON vcvtfp2fx so integer result
select GPR instead of FPR, avoiding the need for cross-bank copies.
- Bitcast uses still select the FP/SIMD-register forms where available.
- Add testing for GPR-resulting and FPR-resulting patterns.
- Add missing tests in fp16_intrinsic_scalar_2op.ll:
test_vcvth_n_u64_f16_1 and test_vcvth_n_u64_f16_16.
A follow-up patch will also include the fix for GlobalIsel.
clang: Emit "float-abi" module flag
Emit the new module flag if it differs from the triple's
default.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[ORC] Add rt::sps::MainCaller for running main-like functions. (#212948)
rt::MainCaller is a controller-side interface for running functions with
a main-like signature (int(int argc, char *argv[])) in the executor.
rt::sps::MainCaller is rt::MainCaller's first implementation, which
invokes main functions using on ORC runtime's orc_rt_ci_sps_call_main
entrypoint (using Simple Packed Serialization for argument/return
encoding / decoding).
These utilities live under the ExecutionEngine/Orc/RTBridge directory,
which is intended to hold controller-side utilities for invoking ORC
runtime systems. Subdirectories (e.g. SPS) hold implementations for
specific serialization schemes.
Adds SPSCallersTest with coverage for direct construction, the
synchronous and asynchronous call operators, use through the
rt::MainCaller interface, and the Create / bootstrap-JITDylib lookup
path.
Add CHECK_RELRO_SUPPORTED=no to java-jna
This package uses a convoluted java build framework to build java
.so files, so wiring through relro looks non-trivial
[AMDGPU] Re-fold masked hi16 pack into v_or_b32_sdwa (#210735)
Follow-up to #206058, which selects the (hi << 16) | (z & 0xffff)
high-half pack to a fused v_lshl_or_b32. When z's high bits are not
known zero this needs an explicit v_and_b32 0xffff, and since
v_lshl_or_b32 has no SDWA form the mask can no longer fold into a single
v_or_b32_sdwa (src1_sel:WORD_0) as it did before -- a small but real
perf hole (~5% on a VALU-bound char4 kernel on gfx942).
Add a SIPeepholeSDWA rewrite of the masked pack back into v_lshlrev_b32
+ v_or_b32_sdwa, erasing the dead v_and. It fires only on the masked
form, so the mask-free #206058 win is preserved, and it never increases
the instruction count.
Assisted-by: Claude Opus
[flang][CodeGen] Replace fir.select* FIR-to-LLVM patterns with stubs
`fir.select`, `fir.select_case`, `fir.select_rank`, and `fir.select_type`
are lowered to cf.* earlier in the pipeline (`--fir-select-ops-conversion`
and `--fir-polymorphic-op`). Their FIR-to-LLVM conversion patterns are
dead in a correct pipeline. Replace them with a single templated stub
`SelectShouldHaveBeenConvertedStub<OP>` that emits `"'fir.<op>' op should
have already been converted"` and fails legalization, so running
`--fir-to-llvm-ir` standalone on stale IR reports a clear diagnostic
instead of "unable to legalize".
`Fir/convert-to-llvm.fir`'s six select* test blocks are removed (the
lowering no longer runs; CF-level coverage lives in
`Fir/SelectOpsConversion/`). `Fir/convert-to-llvm-invalid.fir` gains a
stub-error test per op. `Fir/Todo/select_case_with_character.fir` is
retargeted to check the equivalent diagnostic now emitted by
`--fir-select-ops-conversion`.
Co-Authored-By: Claude Sonnet 4.6 (1M context) <noreply at anthropic.com>
[Docs][AMDGPU] availability/visibility in addrspace(3) and other cleanups (#212707)
addrspace(3) on AMDGPU corresponds to LDS, which is a fast memory directly
accessed by all threads in a workgroup (there is no intervening cache). Thus,
any accesses to this addrspace have built-in availability and visibility at
"workgroup" scope.
Other cleanups:
- Update the intrinsic names to match the implementation.
- Explain store-available and load-visible.
- Rename to "make-available" and "make-visible" for consistent spelling.
ARM: Read float ABI from the "float-abi" module flag
Use the value from the module flag if present, otherwise
fall back on the legacy TargetOptions field until that is
removed.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
