Fix the S3 suite against CI run #374
467 passed, and the one failure was the case added last round. It put
the excluded bucket in the set of names a caller cannot reach, and main
holds a grant on that row like every other -- so it is told 503
ServiceUnavailable, the row's own condition, not the bare AccessDenied
the case asserted.
That is the rule, stated more exactly: 403 hides what the caller may not
reach, not everything. A grant buys the honest answer. The set is now
three names main genuinely cannot reach -- one nothing holds a row for,
one that stands and serves behind a DENY, and one that is not a bucket
name -- which is a sharper claim than the original, since a bucket that
exists and is refused is the member hardest to hide. The 503 stays
where it was already proved, beside a caller that holds the row.
[clang][CodeGen] Construct function type for callgraph from function definition (#212863)
When -fexperimental-call-graph-section is enabled, for unprototyped
function
definitions (such as C89 parameterless declarations or K&R definitions)
reconstruct their prototype from the parameter declarations in the
definition AST (applying default argument promotions to parameters).
Assisted by: Gemini
[llvm][AArch64] Fix FPDiff founding direction in non-sibcall tail calls (#223545)
This fixes another subtle bug in frame accounting (see: #217156 /
#220406), for tail calls that have a non-multiple of 16 bytes worth of
stack arg area, and need that stack arg re-use to be increased to cover
the alignment requirement. This is best illustrated with callers
containing 8 formal arguments covering the first 8 GPRs (x0-x7),
followed by 9 bytes of argument passed on the stack.
In a callee-pops tail call (e.g. tailcc/swifttailcc), the set of
reusable stack arg area bytes has already been sufficiently aligned by
LowerFormalArguments, so growing NumBytes up to StackAlign is enough to
consume that excess. Otherwise (e.g. a plain C-convention call, forced
off the sibcall path, as in the aarch64_inout_za tests), we can't rely
on either having been pre-aligned, so we round NumBytes up to the same
residue mod StackAlign as NumReusableBytes, which cancels the residue
out of their difference (FPDiff), thus keeping the stack aligned going
into the callee.
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NAS-143641 / 26.0.0-RC.1 / Stop parsing private keys in certificate.query (by yocalebo) (#19783)
certificate.query filled key_type and key_length by loading the private
key of every certificate it returned. Loading an RSA private key runs a
full consistency check, about 2 seconds per RSA-4096 key on the
reporter's system, so a query over 17 certificates took 34 seconds.
Parsing the certificate itself takes well under a millisecond.
Read key_type and key_length from the public key of the certificate, or
of the CSR for a request, which matches the private key for anything
that passed validation at create or import time. Parse the private key
only in cert_checks, which runs for the one certificate a service is
about to use.
Original PR: https://github.com/truenas/middleware/pull/19774
Co-authored-by: caleb <yocalebo at gmail.com>
NAS-143641 / 26.0.0 / Stop parsing private keys in certificate.query (#19774)
certificate.query filled key_type and key_length by loading the private
key of every certificate it returned. Loading an RSA private key runs a
full consistency check, about 2 seconds per RSA-4096 key on the
reporter's system, so a query over 17 certificates took 34 seconds.
Parsing the certificate itself takes well under a millisecond.
Read key_type and key_length from the public key of the certificate, or
of the CSR for a request, which matches the private key for anything
that passed validation at create or import time. Parse the private key
only in cert_checks, which runs for the one certificate a service is
about to use.
NAS-143641 / 27.0.0-BETA.1 / Stop parsing private keys in certificate.query (#19782)
certificate.query filled key_type and key_length by loading the private
key of every certificate it returned. Loading an RSA private key runs a
full consistency check, about 2 seconds per RSA-4096 key on the
reporter's system, so a query over 17 certificates took 34 seconds.
Parsing the certificate itself takes well under a millisecond.
Read key_type and key_length from the public key of the certificate, or
of the CSR for a request, which matches the private key for anything
that passed validation at create or import time. Parse the private key
only in cert_checks, which runs for the one certificate a service is
about to use.
Merge upstream/main into cir-callconv-vaarg-x86-64
FunctionInfo.h conflicted. Main added the CanBeFlattened bit exactly where
this branch added NeededIntRegs and NeededSseRegs, and both extended the same
ArgInfo constructor. All three fields are kept, the bools grouped ahead of
the two 3-bit fields, with the initializer in declaration order.
Assisted-by: Cursor / claude-opus-5
always trigger smbd service reload on attachment op
This commit adds a manual reload of the smb.conf whenever we
trigger a filesystem attachment event for an SMB share. Established
SMB sessions will only check for changes to smb.conf every 180
seconds which can cause TCON refused messages. This behavior
regressed when we transitioned from the old libzfs python
library, which necessitated a large-scale service / filesystem
attachment refactor.
[flang][cuda] Limit mem:managed generic matching to allocatable and pointer (#223801)
managed memory mode only puts allocatable and pointer allocations in
managed memory. Static and automatic host objects stay host-resident, so
they must not match a device/managed/unified dummy during generic
resolution.
Keep the -gpu=mem:unified relaxation for all host variables, which are
device-accessible in that mode.
This stops host calls such as sum(host_array(:)) from resolving to a
CUDA Fortran device-dummy specific.
[LV] Add tests for branch weights of branches and selects (NFC). (#224061)
Add for missing branch weights on branches and selects created by LV:
* Skeleton branches
* early exit branches
* various selects.
sysutils/edk2: fix network boot on bhyve
NetworkPkg's DxeNetLib needs EFI_RNG_PROTOCOL, and the Bhyve build's
only producer is VirtioRngDxe, which never binds since bhyve has no
virtio-rng device. RngDxe uses RDRAND instead and needs no device.
TcpDxe depexes gEfiHash2ServiceBindingProtocolGuid, so add
Hash2DxeCrypto too; without TcpDxe there is no HttpServiceBinding.
Also enable HTTP boot.
PR: 298499
Approved by: manu
Sponsored by: Netflix
[lldb] Add an option to build liblldb statically (#223210)
This builds on the Emscripten host and platform work from the previous
patches.
`liblldb` is currently always created as a shared library. That makes
sense for the normal LLDB installation, but it is restrictive for
embedders where dynamic libraries are unavailable, expensive to load or
simply not the preferred deployment model.
My immediate use case is bringing LLDB into
[WasmBolt](https://github.com/anutosh491/WasmBolt) (try
[here](https://anutosh21.github.io/WasmBolt/)). Loading the complete
`liblldb` WebAssembly side module dynamically has significant startup
overhead. A static build lets the browser application link the required
LLDB components and plugins into its main module during CI, after which
startup is much faster and the linker can remove unreachable code.
The use case is not specific to Emscripten, so this patch adds the
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[mlir] Migrate AMDGPU/ROCDL to targets, not chipset versions
**migration tl;dr:** Replace usages of `amdgpu::Chipset` with `ROCDL::TargetInfo`, ideally move from `chipset=` to `arch=`. If you don't use upstream pipelines, call 'TargetInfo::migrateArchFeaturesToModuleFlags` at the appropriate location.
Further note: if you've got a build pipeline that's getting a `gfxXXX` name from something like `rocm_agent_enumerator`, using a full triple name like the ones you get from `rocminfo` is preferred.
`amdgpu::Chipset` was an awkward hack that was hard to keep up to date
with changes in the compiler/new architectures, and didn't properly
support generic targets (and has been strongly disfavored by the
compiler team).
This PR replaces `amdgpu::Chipset` with `ROCDL::TargetInfo`, a
structure that uses LLVM's TargetParser and the underlying LLVM
features tables to get the real nature of the target being compiled
for.
This also helps MLIR move to
new-style (`-mtriple=amdgpuX.YZ-amd-amdhsa`) over "old
style" (`-mtriple=amdgcn-amd-amdhsa -mcpu=gfxXYZ`) triples.
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[mlir][ROCDL] Add TargetInfo to replace Chipset, allow features queries
Add a now ROCDL::TargetInfo struct that parses AMDGPU triples and
target names using the same logic that Clang and LLVM
use (TargetParser) and maintains the set of features available on a
given GPU.
This is an improvement over the old `amdgpu::Chipset` struct since
that was just a version number and often became stale compared to the
knowledge exposed by LLVM, such as gfx1170 having OCP FP8 support even
though other gfx11 chips don't have it.
This struct also allows for moving to new-style
triples (amdgpu9.42-amd-amdhsa vs amdgcn-amd-amdhsa--gfx942, for
example), which is an ongoing migration in other parts of the compiler
that this PR lets us follow.
It also enables compiling for generic targets, like `gfx11-generic`,
which can be run on all chips in a generation.
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ld.elf_so: g/c empty conditional
It was not empty for about two hours before the commit that introduced
it had been reverted. Its content was revered, but the conditional
itself was forgoten.
While here, add "compat32" in the comment for the MLIBDIR block to
make this place more easily findable.
Reland "[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors" (#221058)
This relands #217055
The original commit revealed a latent issue in eliminateFrameIndex in
SIRegisterInfo where SCC can be clobbered before reading it on
gfx900/gfx90a. This change itself has no known issues.
[AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering
When SCC is live into a scalar frame index user, the scaling path avoids
SALU ops that write SCC by computing the address in a VGPR and reading it
back with V_READFIRSTLANE_B32. If the destination of that readfirstlane is
scavenged with spilling allowed, an AMDGPU SGPR spill writes inactive
lanes, so it flips EXEC with S_NOT_B64 and clobbers SCC. Instead, scavenge
that register with AllowSpill=false.
[AMDGPU] Only scale the frame register in place for the last frame index
When nothing can be scavenged, eliminateFrameIndex falls back to scaling
FrameReg in place and restoring it after MI. With two frame indices on
one instruction that fallback fires while lowering the first one, and
FrameReg is left scaled for everything that follows: the second frame
index is then scaled a second time from the already-scaled value, and any
emergency spill emitted in between uses it as its scratch offset.
[AMDGPU] Prevent SCC clobber in frame index lowering in scaling path
eliminateFrameIndex has two lowering strategies, but only one has the
proper handling for checking SCC-liveness to prevent clobbering. Unify
them with a helper function to ensure both paths handle the same
[flang][openacc][cuda] Recover acc routine bind info in CUDA Fortran module reads (#223595)
CUDA Fortran device code can call a procedure whose device-side symbol
is given by `acc routine bind(...)` in the module that declares it.
The using translation unit is often compiled with CUDA Fortran enabled
and without an OpenACC target, so the `$acc` sentinel was never
recognized when re-parsing the module file and the bind clause was
dropped.
Enable OpenACC while reading module files under CUDA Fortran as well,
and resolve the recovered directives onto the imported symbols. User
`$acc` in the main source remains ignored without `-fopenacc`; only
directives that already survived into the `.mod` are honored.
A bind(C) host name and an acc bind device name on the same procedure
is the dual-name rule in OpenACC §2.15.1.
CodeGen: Remove PointerLikeRegClass
Remove PointerLikeRegClass and the related getPointerRegClass
TargetRegisterInfo hook. This is obsoleted by RegClassByHwMode.
Previously targets would have to map ptr_rc to an assumed pointer
register class by implementing this method, but this is now auto-resolvable
per instruction using RegClassByHwMode.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Remove getRegClassByHwMode
