LLVM/project ec18b92clang/lib/CIR/CodeGen CIRGenBuilder.h CIRGenBuiltinAArch64.cpp, clang/lib/CodeGen/TargetBuiltins ARM.cpp

[CIR][NEON] Add lowering for `vnegd_s64` and `vnegh_f16` (#180597)

Add CIR lowering support for the non-overloaded NEON intrinsics
`vnegd_s64` and `vnegh_f16`.

The associated tests are shared with the existing default codegen tests:
  * `neon-intrinsics.c` → `neon/intrinsics.c`
  * `v8.2a-fp16-intrinsics.c` → `neon/fullfp16.c`

A new test file,
  * `clang/test/CodeGen/AArch64/neon/fullfp16.c`

is introduced and is intended to eventually replace:
  * `clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c`

Since both intrinsics are non-overloaded, the CIR and default codegen
handling is moved to the appropriate switch statements. The previous
placement was incorrect.

This change also includes minor refactoring in `CIRGenBuilder.h` to
better group related hooks.
DeltaFile
+42-0clang/test/CodeGen/AArch64/neon/fullfp16.c
+17-0clang/lib/CIR/CodeGen/CIRGenBuilder.h
+12-2clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+11-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-10clang/test/CodeGen/AArch64/neon-intrinsics.c
+4-4clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+86-161 files not shown
+86-237 files

FreeNAS/freenas 1d1f3ebsrc/middlewared/middlewared/plugins/container container.py

NAS-139714 / 26.0.0-BETA.1 / Validate capabilities_state keys in container create/update (#18169)

## Context

We were missing validation for capabilities state which meant that any
invalid value provided by consumer would get stored in the database even
though if it won't have any effect in usage with `nsenter` but still we
should not allow this to happen in the first place.
DeltaFile
+7-0src/middlewared/middlewared/plugins/container/container.py
+7-01 files

FreeBSD/ports 95f2169devel/go-wire distinfo Makefile, devel/go-wire/files patch-vendor_modules.txt

devel/go-wire: Update 0.6.0 => 0.7.0, take maintainership

Changelog:
https://github.com/google/wire/releases/tag/v0.7.0

PR:             292969
Approved by:    Boris Korzun <drtr0jan at yandex.ru> (former maintainer)
DeltaFile
+5-5devel/go-wire/distinfo
+0-10devel/go-wire/files/patch-vendor_modules.txt
+2-3devel/go-wire/Makefile
+7-183 files

OPNSense/core 774a51dsrc/opnsense/mvc/app/views/OPNsense/Firewall alias.volt

Firewall: Aliases - allow TTL usage on host entries, closes https://github.com/opnsense/core/issues/9767
DeltaFile
+2-1src/opnsense/mvc/app/views/OPNsense/Firewall/alias.volt
+2-11 files

LLVM/project e84659bllvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoZvabd.td, llvm/test/CodeGen/RISCV/rvv fixed-vectors-sad.ll

[RISCV][CodeGen] Combine vwaddu+vabd(u) to vwabda(u)

Note that we only support SEW=8/16 for `vwabda(u)`.

Reviewers: topperc, lukel97, preames

Reviewed By: topperc, lukel97

Pull Request: https://github.com/llvm/llvm-project/pull/180162
DeltaFile
+44-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+14-10llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+19-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+14-2llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+91-134 files

LLVM/project 435a162mlir/include/mlir/Dialect/LLVMIR NVVMOps.td

[MLIR][NVVM][NFC] Fix PTX builder class api (#180787)

Previously, `NVVM_PTXBuilder_Op` included `BasicPtxBuilderOpInterface`
as part of the default value of the `traits` parameter. This meant any
subclass that provided an explicit traits list would silently replace
the default and lose the interface, defeating the purpose of the base
class. Callers had to redundantly re-specify the interface.
DeltaFile
+5-5mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+5-51 files

LLVM/project 6f0b8a7llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 aarch64-vector-functions.ll accelerate-vector-functions.ll

[SLP] Use the correct calling convention for vector math routines (#180759)

When vectorising calls to math intrinsics such as llvm.pow we
correctly detect and generate calls to the corresponding vector
math variant. However, we don't pick up and use the calling
convention for the vector math function. This matters for veclibs
such as ArmPL where the aarch64_vector_pcs calling convention
can improve codegen by reducing the number of registers that
need saving across calls.
DeltaFile
+1,656-0llvm/test/Transforms/SLPVectorizer/AArch64/aarch64-vector-functions.ll
+0-1,411llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
+1-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1,657-1,4113 files

LLVM/project 2a0b530llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 vec-combine-dup-trunc-sext.ll

[AArch64] Eliminate XTN/SSHLL for vector splats

Combine:
  sext(duplane(insert_subvector(undef, trunc(X), 0), idx))
Into:
  duplane(X, idx)

This avoids XTN/SSHLL instruction sequences that occur when splatting
elements from boolean vectors after type legalization, which is common
when using shufflevector with comparison results.
DeltaFile
+93-0llvm/test/CodeGen/AArch64/vec-combine-dup-trunc-sext.ll
+56-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+149-02 files

LLVM/project c84ab35llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility BUILD.gn

[gn build] Port 6b7dd97b1ff9
DeltaFile
+1-0llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
+1-01 files

LLVM/project 6b7dd97lldb/source/Plugins/Process/Utility RegisterInfoPOSIX_ppc64.cpp RegisterInfoPOSIX_ppc64.h

[lldb][AIX] Added RegisterInfo file for PPC64 (#165367)

This PR is in reference to porting LLDB on AIX.
Link to discussions on llvm discourse and github:

1. https://discourse.llvm.org/t/port-lldb-to-ibm-aix/80640
2. https://github.com/llvm/llvm-project/issues/101657
The complete changes for porting are present in this draft PR:
https://github.com/llvm/llvm-project/pull/102601

- Added register information file for PPC64 big-endian architecture
(used by AIX)
DeltaFile
+61-0lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.cpp
+31-0lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.h
+1-0lldb/source/Plugins/Process/Utility/CMakeLists.txt
+93-03 files

LLVM/project 56eb89ellvm/test/CodeGen/RISCV/rvv fixed-vectors-sad.ll

[RISCV] Add precommit test for vwabda(u) combine



Reviewers: preames, topperc, lukel97, mshockwave, VoltrexKeyva

Reviewed By: lukel97, mshockwave, VoltrexKeyva

Pull Request: https://github.com/llvm/llvm-project/pull/180161
DeltaFile
+120-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+120-01 files

FreeBSD/ports 9cb207fdevel/got distinfo Makefile

devel/got: update to 0.122

User-visible changes:
- make 'tog diff' indent log messages above patches for safety
DeltaFile
+3-3devel/got/distinfo
+1-1devel/got/Makefile
+4-42 files

LLVM/project 304c680lldb/include/lldb/Target Platform.h, lldb/source/Plugins/Architecture/Arm ArchitectureArm.cpp

[lldb] Step over non-lldb breakpoints (#174348)

Several languages support some sort of "breakpoint" function, which adds
ISA-specific instructions to generate an interrupt at runtime. However,
on some platforms, these instructions don't increment the program
counter. When LLDB sets these instructions it isn't a problem, as we
remove them before continuing, then re-add them after stepping over the
location. However, for breakpoint sequences that are part of the
inferior process, this doesn't happen - and so users might be left
unable to continue past the breakpoint without manually interfering with
the program counter.

This patch adds logic to LLDB to intercept SIGTRAPs, inspect the bytes
of the inferior at the program counter, and if the instruction looks
like a BRK or BKPT or similar, increment the pc by the size of the
instruction we found. This unifies platform behaviour (e.g. on x86_64,
LLDB debug sessions already look like this) and improves UX (in my
opinion, but I think it beats messing with stuff every break).


    [21 lines not shown]
DeltaFile
+87-61lldb/source/Target/Platform.cpp
+76-0lldb/test/API/functionalities/builtin-debugtrap/TestBuiltinDebugTrap.py
+0-71lldb/test/API/macosx/builtin-debugtrap/TestBuiltinDebugTrap.py
+42-0lldb/source/Target/StopInfo.cpp
+30-0lldb/source/Plugins/Architecture/Arm/ArchitectureArm.cpp
+29-0lldb/include/lldb/Target/Platform.h
+264-13213 files not shown
+344-14719 files

LLVM/project 75fb34alibcxx/include __tree map, libcxx/include/__functional operations.h

[libc++] Only make comparators transparent in __tree if they don't cause a conversion (#179453)

We're currently unwrapping `less<T>` even if the `key_type` isn't `T`.
This causes the removal of an implicit conversion to `const T&` if the
types mismatch. Making `less<T>` transparent in that case changes
overload resolution and makes it fail potentially.

Fixes #179319

(cherry picked from commit 9d2303103288f6110622644f78dbd26c8bcf28d5)
DeltaFile
+11-7libcxx/include/__type_traits/make_transparent.h
+12-0libcxx/test/std/containers/associative/map/map.ops/find.pass.cpp
+3-2libcxx/include/__tree
+2-2libcxx/include/map
+2-2libcxx/include/__functional/operations.h
+30-135 files

LLVM/project 4f551b5llvm/lib/Transforms/Scalar IndVarSimplify.cpp, llvm/test/Transforms/IndVarSimplify scev-update-loop-opt.ll

[IndVarSimplify] Add safety check for getTruncateExpr in genLoopLimit (#172234)

getTruncateExpr may not always return a SCEVAddRecExpr when truncating
loop bounds. Add a check to verify the result type before casting, and
bail out of the transformation if the cast would be invalid.

This prevents potential crashes from invalid casts when dealing with
complex loop bounds.

Co-authored by Michael Rowan

Resolves [#153090](https://github.com/llvm/llvm-project/issues/153090)
DeltaFile
+93-89llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
+149-0llvm/test/Transforms/IndVarSimplify/scev-update-loop-opt.ll
+242-892 files

LLVM/project d660455clang/lib/Basic/Targets AArch64.cpp AArch64.h

[AArch64][clang] Use DenseSet for target feature lookup (NFC) (#180734)

This resolves a recent AArch64 compile-time regression triggered by
#176755, which inadvertently grew the feature lookup `StringSwitch` too
large. This patch replaces the `StringSwitch` with a `DenseSet` of
target features. This is built with a new `FeatureLookupBuilder` helper,
which allows reusing all the existing cases (to avoid unintentionally
changing any of them).

Compiler-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=c9753859d19b07315c5a9a493efaa4df18db84ab&to=cb0684b602d5c741ca99b22bb3bc5f902b7a5a7e&stat=instructions:u
DeltaFile
+30-4clang/lib/Basic/Targets/AArch64.cpp
+7-0clang/lib/Basic/Targets/AArch64.h
+37-42 files

LLVM/project 728aa16mlir/include/mlir/Dialect/Tosa/IR TosaShapeOps.td, mlir/lib/Dialect/Tosa/IR TosaCanonicalizations.cpp

[mlir][tosa]: Add Unary Shape Ops folders (#180762)

* EXP2_SHAPE
* LOG2_CEIL_SHAPE
* LOG2_FLOOR_SHAPE

Signed-off-by: Udaya Ranga <udaya.ranga at arm.com>
DeltaFile
+108-11mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
+90-0mlir/test/Dialect/Tosa/constant_folding.mlir
+6-0mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
+204-113 files

LLVM/project 4688b97lld/ELF/Arch Hexagon.cpp, lld/test/ELF hexagon-tls-ie.s

[lld][Hexagon] Fix R_HEX_TPREL_11_X relocation on duplex instructions (#179860)

findMaskR11() was missing handling for duplex instructions. This caused
incorrect encoding when R_HEX_TPREL_11_X relocations were applied to
duplex instructions with large TLS offsets.

For duplex instructions, the immediate bits are located at positions
20-25 (mask 0x03f00000), not in the standard positions used for
non-duplex instructions.

This fix adds the isDuplex() check to findMaskR11() to return the
correct mask for duplex instruction encodings.

(cherry picked from commit 62d018b87a161bb2797c1ed03a482ffcdc8b162c)
DeltaFile
+35-1lld/test/ELF/hexagon-tls-ie.s
+2-0lld/ELF/Arch/Hexagon.cpp
+37-12 files

FreeBSD/ports 5671056databases/py-mysqlclient distinfo Makefile, databases/py-mysqlclient/files patch-pyproject.toml

databases/py-mysqlclient: update to 2.2.8 release (+)

Now support Python 3.14

Release notes:  https://github.com/PyMySQL/mysqlclient/releases/tag/v2.2.8
DeltaFile
+11-0databases/py-mysqlclient/files/patch-pyproject.toml
+3-3databases/py-mysqlclient/distinfo
+1-1databases/py-mysqlclient/Makefile
+15-43 files

OpenBSD/ports in0T84mx11/gnome/papers distinfo Makefile

   Update to papers-49.4.
VersionDeltaFile
1.4+2-2x11/gnome/papers/distinfo
1.4+1-1x11/gnome/papers/Makefile
+3-32 files

OpenBSD/ports S5SSCIxsysutils/firmware/intel distinfo Makefile

   update intel microcode to 20260210

   corrected release notes:
   https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260210-rev1
VersionDeltaFile
1.42+2-2sysutils/firmware/intel/distinfo
1.50+1-1sysutils/firmware/intel/Makefile
+3-32 files

OpenBSD/ports 8zJnGiJsysutils/py-pynetbox distinfo Makefile

   Update pynetbox 7.6.0 -> 7.6.1
   Changelog: https://github.com/netbox-community/pynetbox/releases/tag/v7.6.1
VersionDeltaFile
1.32+2-2sysutils/py-pynetbox/distinfo
1.47+1-1sysutils/py-pynetbox/Makefile
+3-32 files

LLVM/project fefbffelldb/source/Plugins/Process/FreeBSDKernel RegisterContextFreeBSDKernel_arm64.cpp RegisterContextFreeBSDKernel_i386.cpp

[lldb][Process/FreeBSDKernel] Add links to pcb.h (#180267)

We had consensus in #178556 to use cgit links for this kind of use
cases.

Signed-off-by: Minsoo Choo <minsoochoo0122 at proton.me>
DeltaFile
+1-0lldb/source/Plugins/Process/FreeBSDKernel/RegisterContextFreeBSDKernel_arm64.cpp
+1-0lldb/source/Plugins/Process/FreeBSDKernel/RegisterContextFreeBSDKernel_i386.cpp
+1-0lldb/source/Plugins/Process/FreeBSDKernel/RegisterContextFreeBSDKernel_x86_64.cpp
+3-03 files

FreeBSD/src 0233e3fsys/net if_lagg.c

lagg: Remove the member pr_num from struct lagg_proto

It is set but never used. Remove it to avoid confusion and save a
little space.

While here, use designated initializers to initialize the LAGG protocol
table. That improves readability, and it will be safer to initialize the
table if we introduce new protocols in the future.

No functional change intended.

Reviewed by:    glebius
MFC after:      5 days
Differential Revision:  https://reviews.freebsd.org/D55124

(cherry picked from commit 5ba503fc2cabc1a614997f102ace671d996bcc53)
DeltaFile
+6-13sys/net/if_lagg.c
+6-131 files

FreeBSD/src b8d2c1csys/dev/qlnx/qlnxe qlnx_os.c qlnx_def.h

qlnxe: Refactor setting the promiscuous and allmulti mode

There are two entry points to set the promiscuous and allmulti mode.
One is ioctl, and another is the init routine. Given they share almost
the identical logic, refactor a little to make the code more clear.

While here, for the ioctl, translate the error to EINVAL to avoid
confusing the net stack.

Reviewed by:    kbowling
MFC after:      5 days
Differential Revision:  https://reviews.freebsd.org/D54890

(cherry picked from commit 45b1718fadae7d56051ba04ef9d7a175a602a226)
DeltaFile
+38-46sys/dev/qlnx/qlnxe/qlnx_os.c
+0-1sys/dev/qlnx/qlnxe/qlnx_def.h
+38-472 files

FreeBSD/src 18c70c7sys/net if_lagg.c

lagg: Make the none protocol a first-class citizen

All the other protocols have corresponding start and input routines,
which are used in the fast path. Currently the none protocol is
treated specially. In the fast path it is checked to indicate whether
a working protocol is configured. There are two issues raised by this
design:

1. In production, other protocols are commonly used, but not the
none protocol. It smells like an overkill to always check it in the
fast path. It is unfair to other commonly used protocols.

2. PR 289017 reveals that there's a small window between checking the
protocol and calling lagg_proto_start(). lagg_proto_start() is possible
to see the none protocol and do NULL deferencing.

Fix them by making the none protocol a first-class citizen so that it
has start and input routines just the same as other protocols. Then we
can stop checking it in the fast path, since lagg_proto_start() and

    [15 lines not shown]
DeltaFile
+33-9sys/net/if_lagg.c
+33-91 files

FreeBSD/src 0cfc114sys/dev/qlnx/qlnxe qlnx_os.c ecore_l2.c

qlnxe: Overhaul setting the multicast MAC filters

When operating the multicast MAC filters, the current usage of
ECORE_FILTER_ADD and ECORE_FILTER_REMOVE are rather misleading.
ECORE_FILTER_ADD reads "adding new filter", but it actually removes
any existing filters and then addes a new one. ECORE_FILTER_REMOVE
reads "removing a filter", but it actually removes all filters.
Let's use ECORE_FILTER_REPLACE and ECORE_FILTER_FLUSH instead to
avoid confusion.

In the current implementation, only one MAC address is passed to
ecore_sp_eth_filter_mcast() and any previously installed filters are
removed, hence it breaks the multicast function. That can be observed
via either assigning new IPv6 addresses to the interface or putting
the interface as a member of lagg(4) interface with LACP aggregation
protocol. Fix that by calculating the multicast filter bins directly
from multicast MAC addresses and replace the filters every time
the bins changes.


    [20 lines not shown]
DeltaFile
+37-153sys/dev/qlnx/qlnxe/qlnx_os.c
+21-20sys/dev/qlnx/qlnxe/ecore_l2.c
+3-8sys/dev/qlnx/qlnxe/ecore_vf.c
+4-5sys/dev/qlnx/qlnxe/ecore_l2_api.h
+1-4sys/dev/qlnx/qlnxe/qlnx_def.h
+66-1905 files

FreeBSD/src 425b9cesys/dev/qlnx/qlnxe qlnx_os.c

qlnxe: Allow tapping the TX packets

Currently only the packets in the RX path can be captured by tcpdump
as the ETHER_BPF_MTAP call in the TX path is missing. Add it so that
packets in both directions can be captured.

PR:             290973
Reviewed by:    kbowling
MFC after:      5 days
Differential Revision:  https://reviews.freebsd.org/D54891

(cherry picked from commit 968647502ec21464ad3aecc7577ff0e8dfd41693)
DeltaFile
+1-0sys/dev/qlnx/qlnxe/qlnx_os.c
+1-01 files

FreeBSD/src 0f383f7sys/dev/qlnx/qlnxe qlnx_os.c, sys/modules/qlnx/qlnxe Makefile

qlnxe: Let ether_ioctl() handle SIOCSIFADDR ioctl

Since the change [1], the init routine qlnx_init() works as intended.
Let ether_ioctl() handle SIOCSIFADDR to simplify the code.

Combined with the change [1], this shall be a better fix for PR 287445.

[1] c10e6bc0f007 qlnxe: Avoid reinitializing the interface when it is already initialized

PR:             287445
Reviewed by:    kbowling
MFC after:      5 days
Differential Revision:  https://reviews.freebsd.org/D54888

(cherry picked from commit 4012b63889e40bb877bc0e4c8da1792bce472c08)
DeltaFile
+0-25sys/dev/qlnx/qlnxe/qlnx_os.c
+0-1sys/modules/qlnx/qlnxe/Makefile
+0-262 files

FreeBSD/src 8731ff4sys/dev/qlnx/qlnxe qlnx_os.c

qlnxe: Avoid reinitializing the interface when it is already initialized

qlnx_init_locked() unconditionally uninitialize the interface thus is
actually reinitializing the interface. Well the init routine qlnx_init()
is to initialize the interface by net stack when assigned with the first
inet or inet6 address. The ioctl SIOCSIFADDR for the first inet6 address
is handled by ether_ioctl() thus the interface is reinitialized no matter
it was initialized or not.

Add a driver status check for that to avoid reinitializing. Further plan
is removing SIOCSIFADDR ioctl from the driver and let ether_ioctl() handle
it.

Reviewed by:    kbowling
MFC after:      5 days
Differential Revision:  https://reviews.freebsd.org/D54887

(cherry picked from commit c10e6bc0f0079e90cb484323ad71d437f1882422)
DeltaFile
+2-1sys/dev/qlnx/qlnxe/qlnx_os.c
+2-11 files