NetBSD/pkgsrc kKK0azkdoc CHANGES-2026

   doc: Updated www/firefox153-l10n to 153.2.0
VersionDeltaFile
1.5736+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc idsrfUwwww/firefox153-l10n Makefile distinfo

   firefox153-l10n: update to 153.2
VersionDeltaFile
1.2+310-310www/firefox153-l10n/distinfo
1.2+2-2www/firefox153-l10n/Makefile
+312-3122 files

NetBSD/pkgsrc TWmlDVPdoc CHANGES-2026

   doc: Updated www/firefox153 to 153.2.0
VersionDeltaFile
1.5735+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc 0Kprwsdwww/firefox153 Makefile distinfo

   firefox153: update to 153.2

   Mozilla Foundation Security Advisory 2026-85
   Security Vulnerabilities fixed in Firefox ESR 153.2

   Announced
       September 1, 2026
   Impact
       high
   Products
       Firefox ESR
   Fixed in

           Firefox ESR 153.2

   #CVE-2026-75874: Sandbox escape in the Remote Settings Client component

   Reporter
       crixer

    [274 lines not shown]
VersionDeltaFile
1.2+4-4www/firefox153/distinfo
1.2+2-2www/firefox153/Makefile
+6-62 files

LLVM/project 7088c00llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Support KnownFPClass.cpp

[KnownFPClass] Refactor direct access to `KnownFPClass::SignBit` [NFC] (#218514)

Part of https://github.com/llvm/llvm-project/issues/217072

This PR is the first step in refactoring `KnownFPClass`. It replaces
direct access to the `SignBit` field with getters and setters.

The long-term goal is to eliminate the `SignBit` field so that
`KnownFPClass` can be represented by a single bitmask, rather than an
`FPClassTest` together with a `std::optional<bool>`.
```c++
struct KnownFPClass {
  FPClassTest KnownFPClasses = fcAllFlags;
  std::optional<bool> SignBit;
};

struct KnownFPClass {
  // Also distinguishes positive/negative qNaN and sNaN.
  KnownFPMask KnownFPClasses = kfcAllFlags;

    [13 lines not shown]
DeltaFile
+76-76llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
+32-22llvm/include/llvm/Support/KnownFPClass.h
+21-21llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+19-19llvm/unittests/Analysis/ValueTrackingTest.cpp
+13-12llvm/lib/Support/KnownFPClass.cpp
+12-11llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+173-1614 files not shown
+187-17510 files

NetBSD/pkgsrc hZPMJBzdoc CHANGES-2026

   doc: Updated www/firefox140-l10n to 140.15.0
VersionDeltaFile
1.5734+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc T8SGE6Nwww/firefox140-l10n Makefile distinfo

   firefox140-l10n: update to 140.15
VersionDeltaFile
1.16+307-307www/firefox140-l10n/distinfo
1.16+2-2www/firefox140-l10n/Makefile
+309-3092 files

NetBSD/pkgsrc cuhWR0xdoc CHANGES-2026

   doc: Updated www/firefox140 to 140.15.0
VersionDeltaFile
1.5733+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc NbuE2E0www/firefox140 Makefile distinfo

   firefox140: update to 140.15

   Mozilla Foundation Security Advisory 2026-84
   Security Vulnerabilities fixed in Firefox ESR 140.15

   Announced
       September 1, 2026
   Impact
       high
   Products
       Firefox ESR
   Fixed in

           Firefox ESR 140.15

   #CVE-2026-75874: Sandbox escape in the Remote Settings Client component

   Reporter
       crixer

    [126 lines not shown]
VersionDeltaFile
1.21+4-4www/firefox140/distinfo
1.23+2-2www/firefox140/Makefile
+6-62 files

LLVM/project 289b634lld/MachO SyntheticSections.h SyntheticSections.cpp, lld/docs ReleaseNotes.md

[lld][MachO] Order objc stubs by caller priority (#218732)

__objc_stubs is synthetic, so the input section sorting never reaches
its entries. A stub is faulted in when its caller runs, so stubs called
from hot code end up scattered across pages that startup otherwise never
touches.

Record the sections that branch to each stub, give each stub the lowest
priority among its callers, and stable-sort the stubs before addresses
are assigned. Stubs with no prioritized caller keep their relative order
at the end.

This reduces page faults in __objc_stubs by 40% for a large app.
DeltaFile
+87-0lld/test/MachO/objc-stubs-order-file.s
+60-0lld/test/MachO/objc-stubs-order-file-icf-safe-thunks.s
+41-0lld/MachO/Writer.cpp
+25-7lld/MachO/SyntheticSections.cpp
+6-0lld/MachO/SyntheticSections.h
+4-0lld/docs/ReleaseNotes.md
+223-76 files

FreeNAS/freenas a0a8fbdsrc/middlewared/middlewared/plugins/zettarepl_ state.py

Fix zettarepl supervisor thread crash when zettarepl is killed while a task runs
DeltaFile
+3-1src/middlewared/middlewared/plugins/zettarepl_/state.py
+3-11 files

LLVM/project 49d043fcompiler-rt/lib/fuzzer FuzzerDriver.cpp FuzzerUtilWindows.cpp

[libFuzzer] [Darwin] Let the kernel kill fuzzers when OOM (#216836)
DeltaFile
+11-0compiler-rt/lib/fuzzer/FuzzerUtilDarwin.cpp
+5-0compiler-rt/lib/fuzzer/FuzzerUtilPosix.cpp
+3-0compiler-rt/lib/fuzzer/FuzzerUtil.h
+2-0compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
+2-0compiler-rt/lib/fuzzer/FuzzerUtilFuchsia.cpp
+1-0compiler-rt/lib/fuzzer/FuzzerDriver.cpp
+24-06 files

LLVM/project 7315639flang/lib/Optimizer/Transforms AddDebugInfo.cpp

[flang][debug] Fix build after fir.global linkage became a typed enum (#220280)

#220243 replaced the string `linkName` on `fir.global` with a typed
`fir::LinkageAttr`, so `GlobalOp::getLinkName()` no longer exists.

It landed 46 minutes before #215369 was merged, and the two changes
touch
disjoint sets of files: #220243 never touched `AddDebugInfo.cpp`, and
#215369 added the only `getLinkName()` call in it. They merged cleanly
with
no textual conflict, and main is currently unable to build flang:

```
flang/lib/Optimizer/Transforms/AddDebugInfo.cpp:564:39: error:
  'class fir::GlobalOp' has no member named 'getLinkName';
  did you mean 'getLinkage'?
```

Use the typed accessor, matching what #220243 did for the same idiom in

    [9 lines not shown]
DeltaFile
+2-1flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
+2-11 files

NetBSD/pkgsrc D2zFTgYwww/firefox distinfo, www/firefox/patches patch-toolkit_components_remote_nsXRemoteServer.cpp

   www/firefox: Fix build error, Success is not declared

   Reported by Thomas Klausner and Marc Baudoin. Thank you.
VersionDeltaFile
1.1+15-0www/firefox/patches/patch-toolkit_components_remote_nsXRemoteServer.cpp
1.593+2-1www/firefox/distinfo
+17-12 files

LLVM/project fff9753clang/include/clang/Basic BuiltinsNVPTX.td, clang/test/CodeGen builtins-nvptx.c

[Clang][NVPTX] Add sm_107 to SM_Instantiate for NVPTX builtins (#220019)

Add sm_107 to the list of architectures instantiated for NVPTX builtins
in BuiltinsNVPTX.td.

Also add a test invocation with -target-cpu sm_107a to builtins-nvptx.c.
DeltaFile
+3-0clang/test/CodeGen/builtins-nvptx.c
+1-1clang/include/clang/Basic/BuiltinsNVPTX.td
+4-12 files

FreeBSD/ports c9a9bd9www/p5-HTTP-Tiny-Paranoid Makefile distinfo

www/p5-HTTP-Tiny-Paranoid: Update to 0.08

ChangeLog:      https://metacpan.org/dist/HTTP-Tiny-Paranoid/changes
Approved by:    hrs (mentor, blanket)
DeltaFile
+3-3www/p5-HTTP-Tiny-Paranoid/distinfo
+2-2www/p5-HTTP-Tiny-Paranoid/Makefile
+5-52 files

FreeBSD/src b557839sys/geom/virstor g_virstor.h g_virstor.c

gvirstor: Modernize the I/O path

 - Add unmapped I/O support.  The only case when the code needs data
access is BIO_READ returning zeroes for unallocated space.
 - Add BIO_FLUSH support.  Just send it to all allocated components.
 - Add BIO_DELETE support.  While current design does not allow
freeing allocated blocks, at least pass it to underlying providers.
 - Add direct I/O completion support.
 - Add rotation rate reporting.
 - Fix few minor issues.
DeltaFile
+267-55sys/geom/virstor/g_virstor.c
+3-0sys/geom/virstor/g_virstor.h
+270-552 files

LLVM/project d8b59c0llvm/lib/Target/AMDGPU SIRegisterInfo.h SIInstrInfo.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

[AMDGPU] Match the AsmParser's operand-side check and share its helper

In the upcoming PR AsmParser performs the same alignment check but differently:
it tests whether a concrete physreg, which carries no regclass, is in the
relaxed operand's regclass.

Change the verifier to work the same way, reusing
AMDGPUBaseInfo::getUnalignedEquivalentRC.

Co-Authored-By: Claude <noreply at anthropic.com>
DeltaFile
+87-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+0-15llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+7-6llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+0-10llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+5-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+99-315 files

LLVM/project 73851c2llvm/lib/Target/AMDGPU SIRegisterInfo.h SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU verify-gfx90a-aligned-vgprs.mir verify-ds-gws-align.mir

[AMDGPU] Verify VGPR tuple alignment from the operand register class

The machine verifier decided VGPR tuple alignment with isProperlyAlignedRC(),
which inspects only the register's own class. Alignment is not really a property
of the register in isolation: whether a 64-bit tuple must be even-aligned depends
on the operand it feeds, and on mixed-alignment targets the same register class
can be required to be aligned in one operand and exempt in another. Inspecting
only the register also conflates alignment with unrelated problems - a register
that is simply the wrong bank or size for the operand came out as "requires even
aligned vector registers" as well.

Make the operand's register class the source of truth instead: a register is
misaligned only when it does not satisfy the operand's class but its even-aligned
same-bank/width equivalent (SIRegisterInfo::getAlignedEquivalentRC) would. A
register that fits neither is a genuine class or bank mismatch and is left to the
illegal-register and sub-register checks. So an AGPR in a VGPR|SGPR (VS_64)
operand is now reported as an illegal register, and a wrong-size register (e.g. a
64-bit VGPR in a 128-bit MFMA source) or an invalid sub-register index is
reported by those checks alone, no longer doubled up as an "even aligned" error.

    [17 lines not shown]
DeltaFile
+32-38llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+15-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+0-10llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
+0-10llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
+10-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+0-4llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
+57-621 files not shown
+57-647 files

LLVM/project c29c94allvm/test/CodeGen/AMDGPU verify-ds-gws-align.mir verify-gfx90a-aligned-vgprs.mir

[AMDGPU] Restructure VGPR-alignment verifier tests, NFC

Rewrite verify-gfx90a-aligned-vgprs.mir and verify-ds-gws-align.mir so each case
documents inline what makes it invalid, and match the verifier's fuller output -
the "*** Bad machine code ***" kind and the "- instruction:" line - instead of a
single message fragment. Pure test restructure with no functional change, so the
follow-up commit that derives alignment from the operand register class shows
only the change in diagnostic wording.

Co-Authored-By: Claude <noreply at anthropic.com>
DeltaFile
+147-31llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
+62-26llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
+209-572 files

LLVM/project 012ea23llvm/docs AMDGPUUsage.rst

[AMDGPU][DOC] Fix private address space in CFI documentation (#220274)

The CFI implementation has always used the private wave address space.
Update the documentation, which erroneously referred to the private lane
address space.
DeltaFile
+1-1llvm/docs/AMDGPUUsage.rst
+1-11 files

OPNSense/core 8888678src/opnsense/mvc/app/controllers/OPNsense/Kea/Api LeasesController.php

src: style sweep
DeltaFile
+1-1src/opnsense/mvc/app/controllers/OPNsense/Kea/Api/LeasesController.php
+1-11 files

LLVM/project 10397ecllvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU lit.local.cfg

add machine verifier check
DeltaFile
+84-3llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+2-0llvm/test/CodeGen/AMDGPU/lit.local.cfg
+89-33 files

LLVM/project 4b0e16cllvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.alignbyte.ll true16-fold.mir

fold sgpr32 via vgpr16
DeltaFile
+122-0llvm/test/CodeGen/AMDGPU/true16-fold.mir
+26-58llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+57-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+4-11llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
+212-741 files not shown
+213-767 files

LLVM/project 80d14dbllvm/test/CodeGen/AMDGPU global-atomicrmw-fsub.ll global-atomicrmw-fmin.ll

fix pattern
DeltaFile
+8,380-0llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
+1,481-1,527llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+542-1,095llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
+542-1,095llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+542-1,095llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+542-1,095llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+12,029-5,90760 files not shown
+18,087-14,41766 files

LLVM/project 83acefdllvm/test/CodeGen/AMDGPU global-atomicrmw-fmin.ll global-atomicrmw-fmax.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-llvm.amdgcn.image.sample.a16.ll

calling conv update
DeltaFile
+748-1,428llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+1,308-842llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,248-856llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+1,251-722llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+1,251-722llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+1,251-722llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+7,057-5,292159 files not shown
+22,660-15,893165 files

LLVM/project 8d17da4llvm/test/CodeGen/AMDGPU isel-amdgpu-cs-chain-cc.ll fptoui-sat-scalar.ll, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.raw.tbuffer.store.f16.ll

update test
DeltaFile
+146-218llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+106-170llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+123-131llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+42-89llvm/test/CodeGen/AMDGPU/usubsat.ll
+13-41llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+21-27llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
+451-67611 files not shown
+561-82917 files

LLVM/project 6307808mlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/test/Dialect/Tosa ops.mlir invalid_extension.mlir

[mlir][tosa] Add support for mxfp in TRANSPOSE_CONV2D (#218953)

TOSA Speicifcation changes:
* https://github.com/arm/tosa-specification/pull/65
* https://github.com/arm/tosa-specification/pull/77

Signed-off-by: Jeremy Johnson <jeremy.johnson at arm.com>
DeltaFile
+1,343-2mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+20-0mlir/test/Dialect/Tosa/verifier.mlir
+18-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+10-0mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
+9-0mlir/test/Dialect/Tosa/ops.mlir
+9-0mlir/test/Dialect/Tosa/invalid_extension.mlir
+1,409-26 files

LLVM/project 1b762d3llvm/test/CodeGen/AMDGPU frem.ll fptoui-sat-vector.ll

Legalize sgpr16 in sdag
DeltaFile
+2,231-2,790llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,231-2,790llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+1,527-1,576llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+213-220llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+139-146llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+144-140llvm/test/CodeGen/AMDGPU/frem.ll
+6,485-7,66270 files not shown
+7,876-9,18676 files

LLVM/project 9218dcbutils/bazel/llvm-project-overlay/llvm BUILD.bazel

Revert "[Bazel] Fixes 16a770d (#220089)" (#220153)
DeltaFile
+0-8utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+0-81 files