FreeNAS/freenas 5cf0093 — src/middlewared/middlewared/alembic/versions/27.0 2026-09-25_09-46_webshare_mcp.py, src/middlewared/middlewared/api/v27_0_0 webshare.py

Add Webshare MCP option

## Context
Webshare ships an MCP server configured through the `mcp` block of the webshare-auth config, and there was no way to turn it on from middleware.

## Solution
- **New settings**: `webshare.update` accepts `mcp_enabled`, `mcp_allowed_groups` and `mcp_allow_write`, which are rendered into the `mcp` block. `allowed_hosts` is left unset.
- **MCP groups must be login groups**: webshare only checks login groups at OAuth consent, while token refresh and session spawn check only the MCP groups, so every MCP group must be `truenas_webshare` or an entry of `groups`. Otherwise MCP access could outlive Webshare access. Enabling MCP without a group is rejected, since webshare denies everyone on an empty list.
- **Canonical group names**: MCP groups are resolved through NSS, compared by gid and stored under their canonical name, so a directory service group typed differently from its NSS name still matches its login group entry.
- Validation now collects every error before raising, and the `truenas_webshare` group name lives in a single constant.
DeltaFile
+76-27src/middlewared/middlewared/plugins/webshare/config.py
+69-0tests/api2/test_webshare_mcp.py
+30-0src/middlewared/middlewared/alembic/versions/27.0/2026-09-25_09-46_webshare_mcp.py
+19-0src/middlewared/middlewared/api/v27_0_0/webshare.py
+7-2src/middlewared/middlewared/etc_files/webshare-auth/config.json.py
+3-2src/middlewared/middlewared/plugins/account.py
+204-311 files not shown
+205-317 files

LLVM/project f729b9a — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 extracted-subfields.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+38-0llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields.ll
+8-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+46-02 files

LLVM/project 1bde64b — llvm/lib/Transforms/Utils BuildLibCalls.cpp, llvm/test/Transforms/InferFunctionAttrs annotate.ll

[BuildLibCalls] Infer attributes for posix_memalign (#218681)

Handle posix_memalign in inferNonMandatoryLibFuncAttrs.
DeltaFile
+8-0llvm/lib/Transforms/Utils/BuildLibCalls.cpp
+2-1llvm/test/Transforms/InferFunctionAttrs/annotate.ll
+10-12 files

LLVM/project b1274eb — clang/test/OpenMP bug54082.c callback_capture_lifetime.cpp, flang/test/Integration/OpenMP callback-capture-lifetime.f90

[OpenMP] Seed noalias for host callback captures

The generic Attributor can derive noalias and the related lifetime facts for callback-mapped capture arguments, but OpenMPOpt does not seed AANoAlias in its restricted host run. Consequently capture-container loads remain in loops under dereferenceable-at-point semantics.

Seed AANoAlias for pointer arguments mapped to broker operands by callback metadata. Existing call-site reasoning checks every callback and direct call site and rejects escaped or aliased slots. LICM can then hoist immutable capture-container loads without changing the callback ABI or adding an OpenMP-specific hoisting transform.

Add LLVM, Clang, and Flang coverage for pointer, scalar, and aggregate captures together with escaped, duplicated, unmapped, and unknown-use negatives.
DeltaFile
+67-0llvm/test/Transforms/OpenMP/callback-capture-licm.ll
+40-0flang/test/Integration/OpenMP/callback-capture-lifetime.f90
+34-0llvm/test/Transforms/OpenMP/callback-noalias.ll
+29-0clang/test/OpenMP/callback_capture_lifetime.cpp
+19-2llvm/lib/Transforms/IPO/OpenMPOpt.cpp
+9-11clang/test/OpenMP/bug54082.c
+198-132 files not shown
+209-248 files

LLVM/project b7c4b21 — llvm/lib/Transforms/IPO AttributorAttributes.cpp, llvm/test/Transforms/Attributor callbacks.ll callback-noalias.ll

[Attributor] Check callback broker argument aliases correctly (#218672)

Fix a bug in AANoAliasCallSiteArgument. AbstractCallSite uses separate
callback argument and broker operand numbers. Example:
```llvm
call void @broker(
    ptr @callee, # broker arg 0
    ptr %slot,  # broker arg 1
    ptr %slot  # broker arg 2
) !callback !0
define internal void @callee(
    ptr align 8 dereferenceable(8) %a,  # callback arg 0
    ptr align 8 dereferenceable(8) %b   # callback arg 1
) {
```
In `mayAliasWithArgument`, `OtherArgNo` is the broker (call-site) arg
number (0, 1 or 2), so it should be compared against
`getCallSiteArgNo()` not `getCalleeArgNo()`. Otherwise it will compare
the argument with itself, and skip some comparisons with other args, and
wrongly infer/fail to infer `noalias`.
DeltaFile
+57-0llvm/test/Transforms/Attributor/callback-noalias.ll
+28-26llvm/test/Transforms/Attributor/callbacks.ll
+5-5llvm/test/Transforms/OpenMP/parallel_deletion.ll
+1-1llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+91-324 files

LLVM/project cb7500a — llvm/lib/Target/AMDGPU SILowerControlFlow.cpp, llvm/test/CodeGen/AMDGPU lower-control-flow-live-intervals.mir branch-folding-implicit-def-subreg.ll

AMDGPU: Mark the SCC def dead when expanding CF pseudos

The control flow pseudos start with dead flags on the implicit scc def,
but did not transfer to the replacement instruction

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+25-28llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
+25-25llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
+20-20llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
+19-6llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+10-10llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
+115-10513 files not shown
+165-15619 files

LLVM/project c6c8f30 —

Fix Bazel build for aa6b03e (#226426)

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=aa6b03ed5a9ffe5ba6f0d945fac9961884b5c6ed

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+0-00 files

LLVM/project 4d866ff — llvm/lib/Target/SystemZ SystemZFrameLowering.cpp SystemZISelLowering.cpp, llvm/test/CodeGen/SystemZ atomicrmw-fadd-04.ll cmpxchg-01.ll

SystemZ: Mark unread CC defs dead at build time

The custom inserters for the subword atomic pseudos and for probed
allocas, plus the inline stack probe emitted by frame lowering, build
instructions whose CC def is never read. Set the dead flags.

Marking the RISBG32 in the subword cmpxchg loop dead lets MachineSink
move it out of the compare block and into the store block, so it is
skipped when the comparison fails.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+75-0llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
+53-21llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+12-12llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
+10-10llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
+6-3llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+3-3llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
+159-496 files

LLVM/project e34e311 — clang/docs ReleaseNotes.md, clang/lib/CodeGen CGStmtOpenMP.cpp

[clang][OpenMP] Cast by-reference captures to the address space of the captured field (#226229)

Fixes #140069

Sema strips all qualifiers, including the address space, from the type
of a variable captured by an OpenMP region, so the outlined function for
a `target` region takes `int __seg_gs a;` as a plain `int &`, i.e. a
pointer in the default address space. That is the intended model: inside
the region the variable is an ordinary object, and the host's segment
address space means nothing on a device. `GenerateOpenMPCapturedVars`
ignored the captured field's type for by-reference captures though, and
passed the variable's own address. With `map(alloc: a)` that is a `ptr
addrspace(256)` argument for a `ptr` parameter, and emitting the host
fallback call tripped the "Calling a function with a bad signature"
assertion. The same call is emitted on the `omp_offload.failed` path
when offloading targets are given, so this wasn't limited to host-only
compiles.

By-reference captures now convert the address to the type of the

    [4 lines not shown]
DeltaFile
+41-0clang/test/OpenMP/target_map_address_space_codegen.c
+6-1clang/lib/CodeGen/CGStmtOpenMP.cpp
+1-0clang/docs/ReleaseNotes.md
+48-13 files

LLVM/project 76c1ac4 — utils/bazel/llvm-project-overlay/libc BUILD.bazel

[Bazel] Fixes 0a0e0fa (#226400)

This fixes 0a0e0fa181cf162bcc93be85abf2b1b911027e73 (#224644).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=0a0e0fa181cf162bcc93be85abf2b1b911027e73

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+1-01 files

LLVM/project 55b4984 — clang/lib/AST ExprConstShared.h ExprConstant.cpp, clang/lib/AST/ByteCode EvalEmitter.h EvaluationResult.h

[clang][bytecode] Stop relying on `CheckEvaluationResult()` (#186045)

We already have to do a lot of check in `EvaluationResult` ourselves, only to redo some of them on the `APValue` we create. Just do all the checks before creating the `APValue` in the first place.
DeltaFile
+381-1clang/lib/AST/ByteCode/EvaluationResult.cpp
+49-100clang/lib/AST/ExprConstant.cpp
+49-27clang/lib/AST/ByteCode/EvalEmitter.cpp
+42-0clang/lib/AST/ExprConstShared.h
+22-10clang/lib/AST/ByteCode/EvaluationResult.h
+14-3clang/lib/AST/ByteCode/EvalEmitter.h
+557-14114 files not shown
+604-16320 files

LLVM/project 3897817 — llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AArch64 sve-ldst.ll masked_ldst.ll

[AArch64][CostModel] Consider some nxv1 operations as legal (#214471)

This is allowing some operations on vscale x 1 types, namely:
 - load/store
 - masked load/store
 - arithmetic instructions like add/sub/mul

For those, there is already codegen coverage. See e.g.
 - llvm/test/CodeGen/AArch64/sve-int-arith.ll
 - llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
 - llvm/test/CodeGen/AArch64/sve-masked-gather.ll
 - llvm/test/CodeGen/AArch64/sve-masked-scatter.ll

These types are relevant for enabling REVEC in LoopVectorizer. For
AArch64, the main target there is turning NEON vector sizes into SVE
vector size, i.e. using VF = "vscale x 1". For loops with mixed vector
and scalar types, we'll want to allow vectorising scalar types with such
a VF.
DeltaFile
+22-41llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
+48-9llvm/test/CodeGen/AArch64/sve-int-arith.ll
+31-20llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+4-4llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
+0-6llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
+3-3llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
+108-834 files not shown
+114-8910 files

OpenBSD/src oqkTMve — usr.bin/tmux tty-keys.c

   Discard keys if there is no session, fixes crash reported by Artyom
   Pertsovsky.
VersionDeltaFile
1.215+11-1usr.bin/tmux/tty-keys.c
+11-11 files

FreeBSD/ports 421ec03 — filesystems Makefile, filesystems/fatsort distinfo pkg-descr

filesystems/fatsort: Add new port

FATSort is a C-based utility that sorts FAT12, FAT16, FAT32, and exFAT
partitions. It fully supports long file name entries and recursively
sorts directory structures by reading the file system’s boot sector.

WWW:    https://sourceforge.net/projects/fatsort
DeltaFile
+20-0filesystems/fatsort/Makefile
+19-0filesystems/fatsort/files/patch-src-Makefile
+11-0filesystems/fatsort/files/patch-Makefile
+7-0filesystems/fatsort/pkg-descr
+3-0filesystems/fatsort/distinfo
+1-0filesystems/Makefile
+61-06 files

LLVM/project ffcb13a — llvm/include/llvm/ExecutionEngine/Orc JITTargetMachineBuilder.h, llvm/lib/ExecutionEngine/Orc JITTargetMachineBuilder.cpp

Orc: Move getDefaultDataLayoutForTarget out of line (#226416)

Try to fix link errors with shared library builds.
DeltaFile
+6-0llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
+1-4llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
+7-42 files

FreeNAS/freenas d70bb3a — src/middlewared/middlewared/alembic/versions/27.0 2026-09-25_09-46_webshare_mcp.py, src/middlewared/middlewared/api/v27_0_0 webshare.py

Add Webshare MCP option

## Context
Webshare ships an MCP server configured through the `mcp` block of the webshare-auth config, and there was no way to turn it on from middleware.

## Solution
- **New settings**: `webshare.update` accepts `mcp_enabled`, `mcp_allowed_groups` and `mcp_allow_write`, which are rendered into the `mcp` block. `allowed_hosts` is left unset.
- **MCP groups must be login groups**: webshare only checks login groups at OAuth consent, while token refresh and session spawn check only the MCP groups, so every MCP group must be `truenas_webshare` or an entry of `groups`. Otherwise MCP access could outlive Webshare access. Enabling MCP without a group is rejected, since webshare denies everyone on an empty list.
- **Canonical group names**: MCP groups are resolved through NSS, compared by gid and stored under their canonical name, so a directory service group typed differently from its NSS name still matches its login group entry.
- Validation now collects every error before raising, and the `truenas_webshare` group name lives in a single constant.
DeltaFile
+142-0src/middlewared/middlewared/pytest/unit/plugins/webshare/test_webshare_config.py
+76-27src/middlewared/middlewared/plugins/webshare/config.py
+55-0tests/api2/test_webshare_mcp.py
+46-0src/middlewared/middlewared/pytest/unit/plugins/webshare/test_webshare_auth_render.py
+30-0src/middlewared/middlewared/alembic/versions/27.0/2026-09-25_09-46_webshare_mcp.py
+19-0src/middlewared/middlewared/api/v27_0_0/webshare.py
+368-273 files not shown
+379-319 files

LLVM/project 8450b5f — mlir/include/mlir/Transforms GreedyPatternRewriteDriver.h, mlir/lib/Transforms/Utils GreedyPatternRewriteDriver.cpp

[mlir] Avoid rewriting unreachable blocks in the greedy driver

A rewrite can disconnect a block after the iteration's initial CFG sweep.
Track reachability through rewriter notifications and skip worklist operations
in unreachable blocks until the next iteration removes them.

Cache reachability per region. Compare the final successors of changed blocks
after each rewrite, preserving the cache for successor-equivalent changes and
block merges that keep surviving blocks reachable. Recompute for other CFG
changes. This avoids repeated full CFG scans during branch canonicalization.

Single-block regions return before cache lookup or CFG traversal. In the same
Release build, canonicalizing 32,000 sibling single-block regions took 22.8 ms
versus 21.9 ms with the parent driver. With 16,000 regions containing folds,
the times were 35.7 ms and 34.3 ms, respectively. Nesting to 256 levels
showed no measurable difference.

On a synthetic CFG chain whose conditional branches have identical
successors, median CanonicalizerPass times with region simplification

    [8 lines not shown]
DeltaFile
+192-1mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
+50-1mlir/test/lib/Dialect/Test/TestPatterns.cpp
+50-0mlir/test/Transforms/greedy-cfg-reachability.mlir
+41-0mlir/test/Transforms/canonicalize-dce.mlir
+18-2mlir/test/Transforms/test-strict-pattern-driver.mlir
+3-0mlir/include/mlir/Transforms/GreedyPatternRewriteDriver.h
+354-46 files

LLVM/project 2231247 — llvm/docs LangRef.md, llvm/lib/IR Verifier.cpp

[IR] Reject a scalable byval argument in the verifier (#226170)

A byval argument is copied into the caller's frame, and the current
implementation needs the size of that copy at compile time, which a
scalable type does not have. Plain `llc` fails on such IR today, and
SafeStack crashed on it in #182759. Nothing in the tree produces it and
no target needs it yet, so rather than teach SafeStack to step around it
(#225067), disallow it in the LangRef and reject it in the verifier
until the necessary support exists. `isScalableTy()` also covers a
struct with a scalable member.

Fixes #182759.
DeltaFile
+25-0llvm/test/Verifier/byval-scalable.ll
+0-19llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
+4-0llvm/lib/IR/Verifier.cpp
+1-0llvm/docs/LangRef.md
+30-194 files

LLVM/project 07d1efe — llvm/lib/Transforms/Vectorize VPlanAnalysis.cpp, llvm/test/Transforms/LoopVectorize revec-reg-usage.ll

[LV][REVEC] Correctly compute register usage

For REVEC, the initial types might already be vectors, so make sure the
right register class is picked.
DeltaFile
+39-0llvm/test/Transforms/LoopVectorize/revec-reg-usage.ll
+17-12llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
+56-122 files

LLVM/project 543f519 — llvm/unittests/Transforms/Vectorize VPlanTest.cpp

Add explicit IRBuilder.h dependency after rebase
DeltaFile
+1-0llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
+1-01 files

LLVM/project 2b39cb7 — llvm/test/Transforms/LoopVectorize revec-liveout.ll revec-unroll.ll

Update test checks after rebase
DeltaFile
+3-4llvm/test/Transforms/LoopVectorize/revec-unroll.ll
+2-3llvm/test/Transforms/LoopVectorize/revec-liveout.ll
+5-72 files

LLVM/project d2a6ff4 — llvm/test/Transforms/LoopVectorize revec-predication.ll revec-invalid.ll

Harmonise tests by renaming IR values
DeltaFile
+54-54llvm/test/Transforms/LoopVectorize/revec-memory-interleaved.ll
+41-41llvm/test/Transforms/LoopVectorize/revec-memory-gather-scatter.ll
+36-36llvm/test/Transforms/LoopVectorize/revec-invalid.ll
+15-15llvm/test/Transforms/LoopVectorize/revec-predication.ll
+146-1464 files

LLVM/project 38c1a9e — llvm/lib/Target/AArch64 AArch64TargetTransformInfo.h, llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.cpp LoopVectorizationLegality.cpp

Stop using isElementTypeLegalForScalableVector as type check for REVEC
DeltaFile
+5-10llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+0-9llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+2-7llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+7-263 files

LLVM/project f1027a0 — llvm/test/Transforms/LoopVectorize revec-predication.ll revec-memory-gather-scatter.ll, llvm/test/Transforms/LoopVectorize/AArch64 revec-predication.ll revec-memory-gather-scatter.ll

Remove aarch64 triple and move tests out of AArch64/
DeltaFile
+0-293llvm/test/Transforms/LoopVectorize/AArch64/revec-select.ll
+293-0llvm/test/Transforms/LoopVectorize/revec-select.ll
+119-0llvm/test/Transforms/LoopVectorize/revec-memory-gather-scatter.ll
+0-118llvm/test/Transforms/LoopVectorize/AArch64/revec-memory-gather-scatter.ll
+103-0llvm/test/Transforms/LoopVectorize/revec-predication.ll
+0-102llvm/test/Transforms/LoopVectorize/AArch64/revec-predication.ll
+515-51312 files not shown
+962-95918 files

LLVM/project b45bdb3 — llvm/lib/Transforms/Vectorize VPlan.h VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize revec-liveout.ll

Test get(VPV, LaneIdx) for "vector lanes"

This requires a slight adjustment to type asserts in
VPInstruction::execute to be safe for REVEC.
DeltaFile
+77-0llvm/test/Transforms/LoopVectorize/revec-liveout.ll
+8-4llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+2-1llvm/lib/Transforms/Vectorize/VPlan.h
+87-53 files

LLVM/project 376bb51 — llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.cpp, llvm/test/Transforms/LoopVectorize revec-maximize-bandwidth.ll

Revert REVEC-specific useMaxBandwidth() change and add tests
DeltaFile
+50-0llvm/test/Transforms/LoopVectorize/AArch64/revec-maximize-bandwidth.ll
+45-0llvm/test/Transforms/LoopVectorize/revec-maximize-bandwidth.ll
+1-3llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+96-33 files

LLVM/project fc28abb — llvm/test/Transforms/LoopVectorize/AArch64 revec-memory-interleaved.ll revec-memory-contiguous.ll

[LV][REVEC][AArch64] Proof of concept for re-vectorisation

This shows the changes required to enable basic re-vectorisation support in LoopVectorizer. Most of the diff comes from the added tests, the changes to LoopVectorizer files are rather minimal. This proof-of-concept has obvious limitations and only represents the first building block.

My hope is that this helps discussions and complements the RFC at https://discourse.llvm.org/t/rfc-re-vectorisation-to-wider-vectors-in-loopvectorizer/91071.

Support for re-vectorisation is hidden behind a -vectorize-vector-loops flag and LV will bail out if it encounters constructs that are not yet supported. For example:
 - shufflevectors
 - gather/scatter and interleaved accesses
 - target intrinsics
 - reductions
 - if-conversion or tail folding
DeltaFile
+293-0llvm/test/Transforms/LoopVectorize/AArch64/revec-select.ll
+118-0llvm/test/Transforms/LoopVectorize/AArch64/revec-memory-gather-scatter.ll
+102-0llvm/test/Transforms/LoopVectorize/AArch64/revec-predication.ll
+100-0llvm/test/Transforms/LoopVectorize/AArch64/revec-unroll.ll
+90-0llvm/test/Transforms/LoopVectorize/AArch64/revec-memory-contiguous.ll
+89-0llvm/test/Transforms/LoopVectorize/AArch64/revec-memory-interleaved.ll
+792-013 files not shown
+1,169-4019 files

LLVM/project 2b0d085 — llvm/include/llvm/Analysis VectorUtils.h, llvm/lib/Analysis VectorUtils.cpp

Use updated vector.repeat intrinsic
DeltaFile
+37-0llvm/lib/Analysis/VectorUtils.cpp
+33-1llvm/test/Transforms/LoopVectorize/revec-livein.ll
+0-20llvm/lib/IR/IRBuilder.cpp
+11-0llvm/include/llvm/Analysis/VectorUtils.h
+2-2llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1-2llvm/lib/Transforms/Vectorize/VPlan.cpp
+84-251 files not shown
+85-267 files

LLVM/project 4b031ae — llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/unittests/Transforms/Vectorize VPlanTest.cpp

Test recipe execution for vector types

And ensure a value is correctly detected as "widened", even when
VF == VFScaleFactor
DeltaFile
+50-0llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
+8-3llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+58-32 files

LLVM/project 2362f7b — llvm/lib/Transforms/Vectorize VPlanRecipes.cpp

Restore type checks in computeScalarTypeForInstruction()
DeltaFile
+7-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+7-01 files