LLVM/project d30733a — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 scalable-expanding-load.ll

[AArch64][SVE] Support unpacked types for llvm.masked.expandload (#238810)

Assisted-by: Codex (tests)
DeltaFile
+67-0llvm/test/CodeGen/AArch64/scalable-expanding-load.ll
+11-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+78-22 files

LLVM/project 7fe8b7a — clang/test/CIR/CodeGen call-conv-lowering-amdgpu-cxx-records.cpp call-conv-lowering-amdgpu-return-types.c, clang/test/CIR/CodeGenHIP cleanup-alloca-addrspace.hip lambda-reference-var.hip

[CIR] Enable CallConvLowering for AMDGPU triples
DeltaFile
+165-0clang/test/CIR/CodeGen/call-conv-lowering-amdgpu-arg-types.c
+158-0clang/test/CIR/CodeGen/call-conv-lowering-amdgpu-return-types.c
+137-0clang/test/CIR/CodeGenHIP/call-conv-lowering-amdgpu-kernel-args.hip
+74-0clang/test/CIR/CodeGen/call-conv-lowering-amdgpu-cxx-records.cpp
+4-4clang/test/CIR/CodeGenHIP/cleanup-alloca-addrspace.hip
+6-2clang/test/CIR/CodeGenHIP/lambda-reference-var.hip
+544-64 files not shown
+560-1410 files

FreeBSD/src dbf51f8 — sys/dev/sound/pci envy24ht.c

snd_envy24ht: Fix out-of-bounds DMA buffer indexing

378e0c5c8967 reduced the number of playback channels from 5 to 1. This
introduced a regression, because the global DMA buffer indexing was not
adapted accordingly, which now results in kernel panics because of
out-of-bounds reads into the buffer. Additionally, because of wrong
indexing, recording channels ended up being serviced by the playback
part of envy24ht_intr().

Register 1 recording channel instead of 2 + sc->adcn, as the recording
DMA buffer only has room for 1 stereo stream. With 1 channel per
direction, give each channel the first index of its direction
(ENVY24HT_CHAN_PLAY_DAC1 and ENVY24HT_CHAN_REC_ADC1).

While here, fix the buffer wrap in envy24ht_r16sl(). It has to be
ch->size / ch->unit, but was copied verbatim from the 32-bit equivalent,
whose samples are twice as large, so 16-bit recording wrapped halfway
through the DMA buffer and never read the second half.


    [6 lines not shown]
DeltaFile
+11-22sys/dev/sound/pci/envy24ht.c
+11-221 files

LLVM/project 17f3955 — llvm/lib/Transforms/Vectorize LoopVectorize.cpp

[LV] Inline filterExtractingOperands (NFC) (#238745)

Inline filterExtractingOperands in its single use-site, and improve code
around it.
DeltaFile
+4-17llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+4-171 files

LLVM/project eb36b48 — llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Transforms/InstCombine/AArch64 sve-intrinsic-dupqlane.ll

[LLVM][AArch64] Ensure compatible indices when converting dupq to dup_lane. (#238488)

instCombineSVEDupqLane was not verifying the subvector being splatted
matched the one being inserted. At the same time I've also added a check
to ensure the quad index is zero because otherwise we'll generate the
wrong result for out-of-range indices.

Fixes https://github.com/llvm/llvm-project/issues/235610
DeltaFile
+38-0llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-dupqlane.ll
+6-1llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+44-12 files

LLVM/project e746e40 — .github CODEOWNERS

[SPIRV] Add codeowners for SPIR-V backend (#234652)
DeltaFile
+7-0.github/CODEOWNERS
+7-01 files

NetBSD/pkgsrc yCpxens — doc CHANGES-2026

   doc: Updated security/py-botan3 to 3.14.0
VersionDeltaFile
1.7668+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc AxjIC2F — doc CHANGES-2026

   doc: Updated security/botan3 to 3.14.0
VersionDeltaFile
1.7667+2-1doc/CHANGES-2026
+2-11 files

FreeBSD/ports c202e6c — games/anki Makefile.crates Makefile

games/anki: Update to 26.09.4

Changelog:

https://github.com/ankitects/anki/releases/tag/26.09.4

MFH:            2026Q4
Security:       117b053d-d8e3-11f1-985e-901b0edee044
(cherry picked from commit 5afc6d572e97bf7d4d801a563d02d185129284a1)
DeltaFile
+9-9games/anki/distinfo
+2-2games/anki/Makefile.crates
+2-2games/anki/Makefile
+13-133 files

FreeBSD/ports 465a6bf — games/anki distinfo Makefile, games/anki/files patch-build_ninja__gen_src_archives.rs

games/anki: fix build on powerpc64le

The prefetched node modules are created on amd64, where yarn also fetches
the FreeBSD/amd64 builds of esbuild, rollup and @parcel/watcher. On other
archs yarn skips them, so the archive doesn't match distinfo. Make yarn
resolve them for x64 on powerpc64le as well.

esbuild and rollup don't have FreeBSD binaries for powerpc64le, so use their
WebAssembly builds instead. Also let the build system know about powerpc64.

(cherry picked from commit ccf569423575b7fd8e9b87a7055c4466f02da305)
DeltaFile
+47-0games/anki/Makefile
+8-0games/anki/distinfo
+2-1games/anki/files/patch-build_ninja__gen_src_archives.rs
+57-13 files

NetBSD/pkgsrc 44p628Y — security/botan3 Makefile buildlink3.mk, security/botan3/patches patch-src_scripts_install.py

   Update botan3 to version 3.14.0

   CVE fixes from changelog since version 3.9.0:

   CVE-2026-118770 Fix a use after
   free in the TLS asio integration which depending on application
   usage patterns may allow leaking heap memory to the peer.

   CVE-2026-118771 Fix a bug in TLS 1.3 which could allow an
   unauthenticated peer to pin unlimited amounts of memory in the
   handshake by sending many dummy ChangeCipherSpec messages.

   CVE-2026-118766 Fix a blind SSRF during OCSP request processing.
   A malicious OCSP responder or network attacker could cause the
   application to perform a blind GET to an internal service.

   CVE-2026-118765 Fix a bug in AutoSeeded_RNG, affecting only platforms
   without a system RNG, where an API sequence of calling first clear,
   followed by randomize writing to an empty buffer, resulted in the RNG

    [22 lines not shown]
VersionDeltaFile
1.8+33-5security/botan3/PLIST
1.10+5-5security/botan3/distinfo
1.2+2-2security/botan3/patches/patch-src_scripts_install.py
1.13+2-2security/botan3/buildlink3.mk
1.8+2-2security/botan3/Makefile.common
1.26+1-2security/botan3/Makefile
+45-181 files not shown
+46-207 files

pkgng/pkgng 41c8685 — libpkg pkg_add.c

pkg_add: build the system shlibs cache only once (in a thread safe way)
DeltaFile
+13-5libpkg/pkg_add.c
+13-51 files

OPNSense/plugins 7c8cc95 — net/freeradius pkg-descr

net/freeradius: annotate previous
DeltaFile
+1-0net/freeradius/pkg-descr
+1-01 files

OPNSense/core 123b595 — src/opnsense/mvc/app/models/OPNsense/Hostdiscovery/Menu Menu.xml

change tag
DeltaFile
+1-1src/opnsense/mvc/app/models/OPNsense/Hostdiscovery/Menu/Menu.xml
+1-11 files

LLVM/project 459cd1e — llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AArch64/GlobalISel invoke-result-phi.ll

[GlobalISel] Fix dominance when legalizing PHI for results of invoke (#234603)

PHI legalization inserts type conversions before the first terminator so that
they execute on unwind edges. However, an invoke result is defined after
G_INVOKE_REGION_START (which can be the first terminator). Therefore conversions
of these results are inserted before the defs, causing a use before def.

Keep the existing insertion point for values available before the invoke. For
anything that is defined later, move the conversion point to after the def.

Assisted-by: Codex
DeltaFile
+151-0llvm/test/CodeGen/AArch64/GlobalISel/invoke-result-phi.ll
+50-2llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
+29-4llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+230-63 files

LLVM/project d8fbbb5 — utils/bazel/llvm-project-overlay/lldb/source/Plugins BUILD.bazel

[bazel] Resolve mid-air patch collision (#239181)
DeltaFile
+0-14utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
+0-141 files

OPNSense/plugins 2991997 — security/acme-client/src/opnsense/mvc/app/controllers/OPNsense/AcmeClient/Api ServiceController.php

security/acme-client: guard reset method and write access
DeltaFile
+5-0security/acme-client/src/opnsense/mvc/app/controllers/OPNsense/AcmeClient/Api/ServiceController.php
+5-01 files

OPNSense/plugins edbe6df — net/freeradius/src/opnsense/mvc/app/controllers/OPNsense/Freeradius/Api GeneralController.php EapController.php

net/freeradius: enforce config write denial on direct saves
DeltaFile
+11-0net/freeradius/src/opnsense/mvc/app/controllers/OPNsense/Freeradius/Api/ProxyController.php
+5-0net/freeradius/src/opnsense/mvc/app/controllers/OPNsense/Freeradius/Api/UserController.php
+5-0net/freeradius/src/opnsense/mvc/app/controllers/OPNsense/Freeradius/Api/LdapgroupController.php
+5-0net/freeradius/src/opnsense/mvc/app/controllers/OPNsense/Freeradius/Api/ClientController.php
+1-0net/freeradius/src/opnsense/mvc/app/controllers/OPNsense/Freeradius/Api/GeneralController.php
+1-0net/freeradius/src/opnsense/mvc/app/controllers/OPNsense/Freeradius/Api/EapController.php
+28-06 files

LLVM/project ed01ee7 — llvm/include/llvm/CodeGen SelectionDAGNodes.h, llvm/test/CodeGen/AArch64 scalable_masked_deinterleaved_loads.ll scalable_masked_interleaved_stores.ll

[AArch64] Don't fold expandloads/compressstores into (de)interleave ops (#239160)

Previously, `performVector(De)interleaveCombine` would miscompile by
combining expandloads and compressstores with deinterleaves and
interleaves respectively.

This is fixed by updating `ISD::isNormalMaskedLoad()` and
`ISD::isNormalMaskedStore()` to exclude isExpandingLoad() and
isCompressingStore().
DeltaFile
+25-2llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll
+24-1llvm/test/CodeGen/AArch64/scalable_masked_deinterleaved_loads.ll
+7-6llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+56-93 files

LLVM/project 29deede — llvm/test/CodeGen/AArch64 build-vector-extract.ll aarch64-neon-vector-insert-uaddlv.ll

Update Test Checks
DeltaFile
+644-665llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+170-92llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
+13-17llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
+1-3llvm/test/CodeGen/AArch64/build-vector-extract.ll
+828-7774 files

LLVM/project 7ea9945 — llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 shuffle-insert-zero.ll

[AArch64][DAG] Improve codegen for clearing upper vector lanes

Add patterns that use scalar fmov instruction to clear the upper lanes of a vector
DeltaFile
+307-16llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
+50-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+357-162 files

LLVM/project 858aff5 — mlir/include/mlir/IR EnumAttr.td, mlir/test/IR attribute.mlir enum-attr-roundtrip.mlir

[mlir][ODS] Allow a space-only separator for bit enums

Bit enums required a separator containing '|' or ',', so a flag set
could not use the bare keyword syntax of LLVM IR, e.g. `nuw nsw`.
Dialects that want it, such as ClangIR's overflow flags, had to hand-write
a parser and printer for an EnumProp.

Allow `separator = " "` on new-style BitEnums. The generated FieldParser
then reads case keywords until the next token is not one, symbolize
splits on spaces, and the op-format `enum` directive parses the same
way. Like the existing check for a separator literal, the format
verifier rejects a case literal right after such an enum. The separator
must now be '|', ',', or a space ' ', where '|' and ',' may still be
surrounded by spaces, so strings such as "||" are rejected. Legacy
BitEnumAttr keeps requiring '|' or ','.

Assisted-by: Claude Code (Claude Opus 5.5).
DeltaFile
+40-2mlir/tools/mlir-tblgen/EnumsGen.cpp
+30-7mlir/tools/mlir-tblgen/OpFormatGen.cpp
+24-0mlir/test/IR/enum-attr-roundtrip.mlir
+23-0mlir/test/IR/attribute.mlir
+13-8mlir/include/mlir/IR/EnumAttr.td
+20-0mlir/test/mlir-tblgen/enums-gen.td
+150-177 files not shown
+223-2313 files

LLVM/project 28a1768 — llvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp

AMDGPUCodeGenPrepare.cpp - fix MSVC "warning C4018: '<=': signed/unsigned mismatch" warnings. NFC. (#239168)

A possibly futile attempt to get /WX builds working again
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+4-41 files

LLVM/project b0203bd — mlir/lib/Support CMakeLists.txt, mlir/tools/mlir-src-sharder CMakeLists.txt

[MLIR] Add TableGen "variant" of MLIRSupport (#239165)

mlir-src-sharder currently depends on MLIRSupport. In a dylib build,
this brings in a dependency on an LLVM shared library. Since
mlir-src-sharder is a TableGen tool, it links statically against
LLVMSupport, which introduces an ODR violation caught at link-time on
Windows in an LLVM dylib build.

To work around this issue, this PR introduces MLIRSupport_tablegen, to
be used by mlir-src-sharder and other MLIR TableGen tools. This always
links against a static LLVMSupport and prevents ODR violations.

This approach follows the precedent set by clangSupport_tablegen.

The effort to build LLVM as a dylib is tracked in #109483.
DeltaFile
+24-14mlir/lib/Support/CMakeLists.txt
+1-1mlir/tools/mlir-src-sharder/CMakeLists.txt
+25-152 files

LLVM/project aa1bf89 — mlir/include/mlir/Dialect/LLVMIR NVVMOps.td, mlir/lib/Dialect/LLVMIR/IR NVVMDialect.cpp

[MLIR][NVVM] Add nvvm.mulf Op (#238395)

Adds `nvvm.mulf` Op to the NVVM dialect. `nvvm.mulf` performs a
floating-point multiplication between two operands of the same type and
lowers to the `llvm.nvvm.fmul` family of intrinsics.

PTX ISA Reference:
1.
https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-mul
2.
https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-mul
DeltaFile
+224-0mlir/test/Target/LLVMIR/nvvm/mulf/mulf_vector.mlir
+91-0mlir/test/Target/LLVMIR/nvvm/mulf/mulf.mlir
+65-0mlir/test/Target/LLVMIR/nvvm/mulf/mulf_invalid.mlir
+35-12mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
+29-0mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+19-8mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+463-204 files not shown
+489-3210 files

LLVM/project c324abe — llvm/lib/Transforms/Utils SimplifyIndVar.cpp, llvm/test/Transforms/IndVarSimplify iv-widen-elim-ext.ll

[IndVarSimplify] Use context to prove a narrow IV def non-negative

When IndVars widens an IV, it checks for each narrow def
(the IV and values computed from it) whether it is
non-negative on every iteration.

If it is, zext and sext of it are equal. Then when IndVars
idens the def's users, they can choose to use either
the sext or zext of the def.

Previously, we didn't use context to prove the non-negativity of def.

Now ask SCEV about the def non-negativity at its context -
the def instruction itself.
This allows SCEV to infer facts from the dominating guards and assumes.

This in turn allows eliminating unnecessary truncs/zexts. E.g. in

  if (m > 0)

    [9 lines not shown]
DeltaFile
+19-28llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
+2-2llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
+21-302 files

LLVM/project 6279d78 — llvm/test/Analysis/ScalarEvolution max-trip-count-smax-exit-bound.ll, llvm/test/Transforms/IndVarSimplify lftr-smax-exit-bound.ll

[IndVarSimplify][SCEV][NFC] Add tests for LFTR losing the constant max trip count

When LFTR of IndVars rewrites a loop exit like i >s C
to i + 1 == smax(start, C + 1),
SCEV's constant max backedge-taken count of the loop gets worse.

Add tests showing it.

Assisted-By: Claude
DeltaFile
+60-0llvm/test/Analysis/ScalarEvolution/max-trip-count-smax-exit-bound.ll
+43-0llvm/test/Transforms/IndVarSimplify/lftr-smax-exit-bound.ll
+103-02 files

LLVM/project f8665d1 — llvm/test/Transforms/IndVarSimplify iv-widen-elim-ext.ll

[IndVarSimplify][NFC] Add tests for widening non-negative IV users

Add tests for widening provably non-negative IV users.

Assisted-By: Claude
DeltaFile
+423-0llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
+423-01 files

LLVM/project 0b4229a — llvm/test/Transforms/LoopVectorize runtime-check-widened-iv-index.ll

[LoopVectorize][NFC] Add tests for runtime checks with a widened IV index

In

  if (start <u len && start - 32 <u len)   // len >=s 0
    for (int32_t i = start; i < n; i++) a[i] = a[i - 32];

i - 32 >=s 0, so the distance between a[i] and a[i - 32] is always 32.

If the loop has an i64 IV and i - 32 is computed in i64, it is
vectorized without runtime checks.
If i - 32 is computed in i32 and zero-extended, the vectorizer
emits an overflow check and an alias check.

Add tests for both forms.

Assisted-By: Claude
DeltaFile
+213-0llvm/test/Transforms/LoopVectorize/runtime-check-widened-iv-index.ll
+213-01 files

LLVM/project aa86359 — llvm/test/Transforms/IndVarSimplify iv-widen-elim-ext.ll

[IndVarSimplify][NFC] Add a negative test for zext elimination

Add a test for a zext of an nsw add of a sign-extended IV, where the
add may be negative.

Also rewrite a stale comment of an existing test.

Assisted-By: Claude
DeltaFile
+45-1llvm/test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll
+45-11 files