[lit][NFC] remove new-style class opt-ins (#199784)
In Python 3.0 and later it is no longer necessary to explicitly derive
from `object` to opt into "new-style" classes, they are the default.
Since the current minimum Python version is 3.8, this is no longer
required. This patch removes `object` from the base class lists of all
affected classes in lit.
.github: update workflows README
Describe the current zfs-qemu pipeline, ci_type selection, supported
guests, and the code-checking and other auxiliary workflows.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Christos Longros <chris.longros at gmail.com>
Closes #18590
Fixes for buildbot breaks in #183153
Attempt at fixing issues in #183153 caught by buildbots, specifically
no-assert and windows builds.
Not sure how to run those bots ahead of landing this?
Change-Id: I285adf09ac2df239d0ab05459f7388b6970247ad
[AArch64] Fix hasNearbyPairedStore to handle non-inbounds GEPs (#199137)
Problem: `hasNearbyPairedStore` uses
`stripAndAccumulateInBoundsConstantOffsets` to decompose store pointers
into (base, offset) pairs and check whether two stores are 16 bytes
apart. This fails when LSR has rewritten pointer arithmetic into
non-inbounds GEPs because the function refuses to look through them. The
two stores then appear to have different base pointers and the check
returns false. When this happens, `lowerInterleavedStore` proceeds to
emit `ST2` for a pattern that would be more profitable as `zip+stp`,
since the load-store optimizer can pair adjacent stores into `STP` but
cannot merge `ST2` with anything. On a bf16-to-fp32 NEON conversion loop
this causes a regression from 11 to 17 instructions per iteration.
Note: Interleaved stores support was added for RISCV in
https://github.com/llvm/llvm-project/pull/115354. Turning this off
produces the desired STP instructions.
https://godbolt.org/z/1afsjPd3e
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[flang] Enabled pulling of rebox into array_coor. (#199161)
This patch enables pulling slicing `fir.rebox` operations
into `fir.array_coor`. This helps preserve information about
the original rank of the array being accessed.
`FIRToMemRef` and later passes may benefit from this.
Assisted by: Claude
[flang][FIRToMemRef] Get strides from descriptor for some array_coor cases. (#199158)
This is a follow-up on Jean's comment
https://github.com/llvm/llvm-project/pull/198933#discussion_r3279535746
This patch makes use of the descriptor strides when `fir.array_coor`'s
memref is a `fir.box` that is not a fir.embox result.
[LoopFusion] Do not fuse loops with different guards (#199724)
The testcase that was originally contributed to #193641 exposed a
functional issue in which loop fusion can fuse functions with different
loop guards. There seem to two distinct bugs and each of them alone is
enough to let this happen.
- The condition that checks loop guards are identical, intends to
exclude loops that require peeling. But the condition is not correct and
it allows some loops that do not require peeling to pass.
- The condition that checks two guards are identical implicitly assume
conditions of guard branches are instructions, but this is not
necessarily always correct.
This patch fixes the problem for the loops that do not require peeling.
The issue still exists for loops that require peeling and will be fixed
separately.
pmap_bootstrap(): Fix an error intrduced in rev 1.127 - ensure pmap_membank
points to the first element in the array after building up the linked list.
[lldb] New expedited register specfication for unavailable regs (#193894)
When lldb-server/debugserver send a stop packet, they expedite the
vaLues of many of the general purpose registers in the stop packet, so
lldb doesn't need to fetch them separately.
On Darwin systems using an AArch64 M4 or newer SOC with SME, we need to
fetch the streaming vector length (svl) register when in Streaming SVE
Mode to correctly size the registers in lldb. On Darwin systems, when we
are not in SSVE mode, svl is undefined -- it is not included in the
expedited registers. However, lldb will still try to fetch the value, so
we get a register-read packet at every stop on M4 and newer systems,
trying to fetch the value.
This patch adds a new format for the expedited registers. They are
normally a `;` separated series of `{regnum}:{native endian bytes}`.
This allows for `{regnum}:` alone, indicating that the register value
for regnum cannot be fetched at this stop.
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Reland "[libc] Enable baremetal float printf using modular format" (#199758)
Reverts llvm/llvm-project#199114
#199118 fixed the issue uncovered in the Fuchsia CI build.
