LLVM/project 0dbd2c8llvm/include/llvm/CodeGen LiveDebugVariables.h, llvm/lib/CodeGen RegAllocGreedy.cpp LiveDebugVariables.cpp

[LiveDebugVariables] Repair stale SlotIndexes

The analysis keeps its indexes from before the first register allocator
until DBG_VALUEs are emitted, by which point passes in between have
erased some of the instructions they point at. Resolve them at the
start of each allocator run and before emitting.

SlotIndexes can then reclaim the entries of erased instructions without
sparing the ones held here, which would have made generated code depend
on -g. Emitted locations are unchanged, except that intervals resolving
to one position now emit a single DBG_VALUE rather than identical
consecutive ones.
DeltaFile
+135-0llvm/lib/CodeGen/LiveDebugVariables.cpp
+57-0llvm/test/DebugInfo/AMDGPU/live-debug-vars-stale-slot-indexes.ll
+8-4llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
+8-0llvm/include/llvm/CodeGen/LiveDebugVariables.h
+7-0llvm/lib/CodeGen/RegAllocGreedy.cpp
+4-2llvm/test/CodeGen/X86/debug-spilled-snippet.mir
+219-61 files not shown
+223-87 files

LLVM/project 0516edbllvm/include/llvm/CodeGen SlotIndexes.h, llvm/lib/CodeGen SlotIndexes.cpp

[SlotIndexes] Add queries for stale indexes

An erased instruction leaves its index list entry in place, making the
index indistinguishable from a block boundary entry. Add
isBlockBoundaryIndex() and isStaleIndex() to tell the two apart, and
canonicalizeIndex() to resolve a stale index to the closest preceding
instruction's register slot, or the block start if none survives.

NFC. No caller yet. LiveDebugVariables is next.
DeltaFile
+207-0llvm/unittests/CodeGen/SlotIndexesTest.cpp
+29-0llvm/lib/CodeGen/SlotIndexes.cpp
+14-0llvm/include/llvm/CodeGen/SlotIndexes.h
+1-0llvm/unittests/CodeGen/CMakeLists.txt
+251-04 files

LLVM/project 6486ab3flang/test/Fir/OpenACC acc-fir-map-info-prep-types.mlir acc-fir-map-info-prep-clauses.mlir, mlir/include/mlir/Dialect/OpenACC OpenACCCGEnums.td

[OpenACC] Add a map flag for the attach/detach clause (#224433)

Example:
```fortran
!$acc enter data create(arr)
p => arr(:,1)
!$acc enter data attach(p)
```

In this code, computeDataClauseMapFlags returns no flag for
acc_attach/detach, so the resulting acc.map_info is indistinguishable
from one formed for a create/delete of the target, and the clause itself
is gone by that point.

Fix: give the attach/detach clause its own map flag.
DeltaFile
+3-3mlir/test/Conversion/OpenACCToLLVM/data-runtime.mlir
+4-1mlir/include/mlir/Dialect/OpenACC/OpenACCCGEnums.td
+4-0mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
+1-1mlir/test/Conversion/OpenACCToLLVM/data.mlir
+1-1flang/test/Fir/OpenACC/acc-fir-map-info-prep-types.mlir
+1-1flang/test/Fir/OpenACC/acc-fir-map-info-prep-clauses.mlir
+14-76 files

LLVM/project 910483allvm/lib/Target/RISCV RISCVISelLowering.cpp

fixup! Add extra condition on VL
DeltaFile
+35-18llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+35-181 files

LLVM/project a4391cbllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 splat-gather-subtree-loop-extracts.ll splat-gather-subtree-trim-revert-cost.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+301-270llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+140-153llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-satd.ll
+12-14llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-trim-revert-cost.ll
+9-6llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-loop-extracts.ll
+462-4434 files

LLVM/project b8b115dllvm/include/llvm/CodeGen LiveDebugVariables.h, llvm/lib/CodeGen RegAllocGreedy.cpp LiveDebugVariables.cpp

[LiveDebugVariables] Repair stale SlotIndexes

The analysis keeps its indexes from before the first register allocator
until DBG_VALUEs are emitted, by which point passes in between have
erased some of the instructions they point at. Resolve them at the
start of each allocator run and before emitting.

SlotIndexes can then reclaim the entries of erased instructions without
sparing the ones held here, which would have made generated code depend
on -g. Emitted locations are unchanged, except that intervals resolving
to one position now emit a single DBG_VALUE rather than identical
consecutive ones.
DeltaFile
+135-0llvm/lib/CodeGen/LiveDebugVariables.cpp
+57-0llvm/test/DebugInfo/AMDGPU/live-debug-vars-stale-slot-indexes.ll
+8-4llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir
+8-0llvm/include/llvm/CodeGen/LiveDebugVariables.h
+7-0llvm/lib/CodeGen/RegAllocGreedy.cpp
+4-2llvm/test/CodeGen/X86/debug-spilled-snippet.mir
+219-61 files not shown
+223-87 files

LLVM/project 9889b04llvm/include/llvm/CodeGen SlotIndexes.h, llvm/lib/CodeGen SlotIndexes.cpp

[SlotIndexes] Add queries for stale indexes

An erased instruction leaves its index list entry in place, making the
index indistinguishable from a block boundary entry. Add
isBlockBoundaryIndex() and isStaleIndex() to tell the two apart, and
canonicalizeIndex() to resolve a stale index to the closest preceding
instruction's register slot, or the block start if none survives.

NFC. No caller yet. LiveDebugVariables is next.
DeltaFile
+207-0llvm/unittests/CodeGen/SlotIndexesTest.cpp
+29-0llvm/lib/CodeGen/SlotIndexes.cpp
+14-0llvm/include/llvm/CodeGen/SlotIndexes.h
+1-0llvm/unittests/CodeGen/CMakeLists.txt
+251-04 files

LLVM/project 41b7eedlibc/src/stdio/baremetal fclose.cpp fseeko.cpp

[libc] Embeddeding API for seek and close (#221880)

This change introduces two new symbols to the embedding API hooks:
__llvm_libc_stdio_seek and __llvm_libc_stdio_close. These are used to
implement fclose, fseek, fseeko, ftell and ftello for baremetal.

The implementation was extracted from #221211.

Authored-by: voltur01
DeltaFile
+60-0libc/src/stdio/baremetal/CMakeLists.txt
+38-0libc/src/stdio/baremetal/fseek.cpp
+38-0libc/src/stdio/baremetal/ftell.cpp
+38-0libc/src/stdio/baremetal/ftello.cpp
+37-0libc/src/stdio/baremetal/fseeko.cpp
+26-0libc/src/stdio/baremetal/fclose.cpp
+237-03 files not shown
+262-29 files

LLVM/project ea158b1clang/test/CodeGen/AArch64 abi-classify-arg-types.cpp abi-classify-arg-types.c, llvm/include/llvm/ABI Types.h

[LLVMABI][AARCH64] Support homogeneous aggregate arguments (#224138)

This adds support for handling homogeneous aggregate arguments in the
AArch64 implementation of the LLVM ABI library.

This required adding a new field to the llvm::abi::Type class to track
the unadjusted alignment of the field. This meant I needed to make
updates to the CIR calling convention lowering pass, but AArch64 isn't
supported in the CIR pass yet, so that part of the change is strictly
NFC at this point.

I'm removing the aarch64-pc-windows-msvc run lines from the
abi-classify-arg-types.cpp test because the new test cases added would
land in NYI diagnostic in isPermittedToBeHomogeneousAggregate(), and
they weren't adding any unique coverage.

Assisted-by: Cursor / various models
DeltaFile
+259-60llvm/unittests/ABI/AArch64TargetInfoTest.cpp
+134-12clang/test/CodeGen/AArch64/abi-classify-arg-types.c
+65-10clang/test/CodeGen/AArch64/abi-classify-arg-types.cpp
+24-12llvm/include/llvm/ABI/Types.h
+31-0llvm/lib/ABI/Targets/AArch64.cpp
+28-0llvm/unittests/ABI/TypesTest.cpp
+541-9410 files not shown
+612-11416 files

LLVM/project 846719alldb/test/API/lang/cpp/libcxx-internals-recognizer TestLibcxxInternalsRecognizer.py, lldb/test/API/lang/objc/modules-auto-import TestModulesAutoImport.py

[LLDB] Skip tests with older versions of clang (#224468)
DeltaFile
+2-2lldb/test/API/lang/objc/modules-auto-import/TestModulesAutoImport.py
+1-1lldb/test/API/lang/cpp/libcxx-internals-recognizer/TestLibcxxInternalsRecognizer.py
+1-0lldb/test/API/lang/objc/synthesized-property-accessor/TestSynthesizedPropertyAccessor.py
+4-33 files

LLVM/project dd0ee5elldb/source/Plugins/ScriptInterpreter/Python/Interfaces ScriptedThreadPlanPythonInterface.cpp, lldb/test/API/commands/frame/recognizer/step-through recognizer.py

[lldb] Read the bool that a scripted thread plan's should_step returns (#215521)

Fixes part (1) of #215189.

`ScriptedThreadPlanPythonInterface::GetRunState()` used
`GetUnsignedIntegerValue()` to read the script's `should_step` return
value. A
Python `bool` arrives as a `StructuredData::Boolean`, so the return
value was
discarded and every scripted thread plan reported `eStateStepping`: a
plan
returning `False` single-stepped exactly like one returning `True`.

The documented contract for `should_step` is a bool
(`lldb/docs/use/tutorials/automating-stepping-logic.md` and
`lldb/examples/python/templates/scripted_thread_plan.py`). Read it as
one; any
other return value is logged and causes the plan to step.


    [66 lines not shown]
DeltaFile
+58-0lldb/test/API/functionalities/step_scripted/TestStepScripted.py
+50-0lldb/test/API/functionalities/step_scripted/Steps.py
+15-2lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.cpp
+1-1lldb/test/API/functionalities/step_scripted/main.c
+2-0lldb/test/API/commands/frame/recognizer/step-through/recognizer.py
+126-35 files

LLVM/project 38c9957utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[Bazel] Fixes 01d1d4d (#224462)

This fixes 01d1d4dacb0e7726a7dc6c24ca10359251caa698 (#206380).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=01d1d4dacb0e7726a7dc6c24ca10359251caa698

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+3-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+3-01 files

LLVM/project e85bbe9mlir/lib/Dialect/OpenACC/Transforms ACCCGToGPU.cpp, mlir/test/Dialect/OpenACC acc-cg-to-gpu-predicate-region-worker-barrier.mlir

[ACCCGToGPU] Generate a per row barrier for a predicate region inside threadY loop. (#224461)

When a predicate region is inside a threadY (worker) loop, the generated
barrier should be to synchronize all threadsX (vector lanes) for that
threadY.

Previously, this code would generate a barrier for all inactive
dimensions and that can be problematic if we have no outer gang loop
(hence an inactive blockX dim) and trip count for worker loop isn't
divisible by number of workers. This would lead to a barrier for all
threads within the block leading to a deadlock.

Assisted-by: Codex
DeltaFile
+41-0mlir/test/Dialect/OpenACC/acc-cg-to-gpu-predicate-region-worker-barrier.mlir
+2-4mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+43-42 files

LLVM/project 69784acllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vector-interleave-fixed.ll

fixup! Loosen the mask condition
DeltaFile
+5-28llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+14-6llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+19-342 files

LLVM/project 5bc5d83llvm/lib/Target/AArch64 AArch64RegisterInfo.cpp, llvm/lib/Target/PowerPC PPCRegisterInfo.cpp

[CodeGen] Use SmallSetVectorImpl for getRegAllocationHints

Change TargetRegisterInfo::getRegAllocationHints and all target overrides
to accept SmallSetVectorImpl<MCPhysReg> &Hints instead of SmallVectorImpl,
structurally preventing duplicate register allocation hints while preserving
insertion order and avoiding hardcoding the inline capacity in virtual
method signatures.

Increase AllocationOrder's inline hint storage capacity from 16 to 32
registers to accommodate 32-register classes without heap allocations.
DeltaFile
+17-10llvm/unittests/CodeGen/AllocationOrderTest.cpp
+10-12llvm/lib/Target/X86/X86RegisterInfo.cpp
+10-8llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+7-9llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+6-6llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
+5-5llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+55-5014 files not shown
+81-8020 files

LLVM/project ed554f2mlir/include/mlir/Dialect/XeGPU/IR XeGPUOps.td, mlir/lib/Dialect/XeGPU/IR XeGPUOps.cpp

[mlir][xegpu] Remove chunk_size attribute; infer from types (#205122)

The chunk_size attribute on xegpu.load (LoadGatherOp) and xegpu.store
(StoreScatterOp) was redundant with the operand/result types: the XeVM
lowering never read it, VectorToXeGPU already built these ops with an
empty chunk_size, and the op docs noted it could be inferred from the
type.

Remove the attribute and infer the chunk size from the value/result and
mask types via a computed getChunkSize() op method. The mask carries one
element per lane, so the chunk size is the trailing value dimension when
the value has more elements than the mask, and 1 otherwise. This keeps
the existing op.getChunkSize() call sites working while respecting
library layering (no XeGPUUtils dependency from the IR library).

Update the gather/scatter builders, transforms (propagate-layout,
sg-to-lane, wg-to-sg, unroll), VectorToXeGPU lowerings, and lit tests.
Two invalid.mlir cases that were only invalid because a stated
chunk_size contradicted the type are removed; two others are

    [4 lines not shown]
DeltaFile
+129-0mlir/test/Conversion/XeGPUToXeVM/loadstore_gather_coalesce.mlir
+17-91mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
+58-47mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+39-57mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
+48-44mlir/test/Dialect/XeGPU/invalid.mlir
+16-66mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
+307-30517 files not shown
+570-58923 files

LLVM/project ad6f842llvm/lib/CodeGen RegisterPressure.cpp, llvm/test/CodeGen/AMDGPU schedule-pressure-dead-superreg-live-subreg.mir

Partially revert "RegisterPressure: Remove dead defs correctly" (#224371)

This partially reverts the lane-mask collector change from #222627
(bde5e74309f6). That flipped the dead-def reconciliation in both
RegisterOperandsCollector::collectInstr (register units) and
collectInstrLanes (lane masks). Instead of removing units covered by a
live def from the dead def set, it removed units covered by a dead def
from the live def set.

The flip regressed targets that track subregister liveness, which use
the
lane-mask collector path. When a live sub-register def overlaps a dead
super-register def, the shared register unit is flagged live on one
operand and dead on another. Removing the live def then drops the
genuinely-live unit, so the cached PressureDiff under-counts it and
trips
the EXPENSIVE_CHECKS pressure cross-check in GCNSchedStrategy.

Restore the original lane-mask path while keeping the new behavior on

    [14 lines not shown]
DeltaFile
+34-0llvm/test/CodeGen/AMDGPU/schedule-pressure-dead-superreg-live-subreg.mir
+3-5llvm/lib/CodeGen/RegisterPressure.cpp
+37-52 files

LLVM/project 01d1d4dmlir/lib/Conversion/ArithToLLVM ArithToLLVM.cpp, mlir/lib/Conversion/ControlFlowToLLVM ControlFlowToLLVM.cpp

[mlir][LowerToLLVM] Pass DataLayoutAnalysis to LowerToLLVMOptions in `ArithToLLVM`, `ControlFlowToLLVM`, and `VectorToLLVM` passes (#206380)

These three conversion passes constructed `LowerToLLVMOptions` without a
`DataLayout`, causing the index bitwidth to be hard-wired to 64 even
when the module declares a narrower index via `dlti.dl_spec`.

```cpp
// Before (all three passes):
LowerToLLVMOptions options(&getContext());
LLVMTypeConverter converter(&getContext(), options);

// After:
const auto &dataLayoutAnalysis = getAnalysis<DataLayoutAnalysis>();
LowerToLLVMOptions options(&getContext(),
                           dataLayoutAnalysis.getAtOrAbove(getOperation()));
LLVMTypeConverter converter(&getContext(), options, &dataLayoutAnalysis);
```

I used AI to investigate this problem and to write the tests.

    [3 lines not shown]
DeltaFile
+74-5mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
+67-0mlir/test/Conversion/VectorToLLVM/vector-load-store-to-llvm.mlir
+59-0mlir/test/Conversion/ControlFlowToLLVM/branch.mlir
+5-2mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
+5-2mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
+5-2mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
+215-113 files not shown
+220-119 files

LLVM/project 1b34344llvm/docs/tutorial BuildingAJIT3.md, llvm/docs/tutorial/MyFirstLanguageFrontend LangImpl08.md

docs: Compute the DataLayout from the triple in the tutorials

Update the exmaple code to avoid using TargetMachine::createDataLayout.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-1llvm/examples/Kaleidoscope/Chapter8/toy.cpp
+2-1llvm/docs/tutorial/BuildingAJIT3.md
+1-1llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl08.md
+5-33 files

LLVM/project 45cb52flldb/source/Plugins/ObjectFile/ELF ObjectFileELF.cpp

[lldb] Remove remaining ConstString section names in ObjectFileELF (#224407)
DeltaFile
+14-13lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+14-131 files

OpenBSD/ports SjeRGMJsysutils/firmware/vmm Makefile, sysutils/firmware/vmm/files vmm-dsdt.asl

   Update SeaBIOS and add EDK II OVMF images.

   dv@ and mlarkin@ did the work and tested this did not break old VMs.
   I only tweaked a few things in the port.

   ok mlarkin@
VersionDeltaFile
1.1+141-0sysutils/firmware/vmm/patches/patch-edk2_OvmfPkg_QemuRamfbDxe_QemuRamfb_c
1.1+127-0sysutils/firmware/vmm/files/vmm-dsdt.asl
1.37+104-5sysutils/firmware/vmm/Makefile
1.1+97-0sysutils/firmware/vmm/patches/patch-edk2_OvmfPkg_OvmfPkgX64_dsc
1.1+70-0sysutils/firmware/vmm/patches/patch-edk2_OvmfPkg_Library_PlatformBootManagerLib_BdsPlatform_c
1.1+66-0sysutils/firmware/vmm/patches/patch-edk2_OvmfPkg_Library_PlatformInitLib_MemDetect_c
+605-514 files not shown
+936-1020 files

LLVM/project e9e9439utils/bazel/llvm-project-overlay/libc/test libc_test_rules.bzl, utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil BUILD.bazel

[bazel][test][libc] Add tags to tests marking full-build compatibility

This allows Bazel to execute tests based on whether they support full-build mode or not, by running:

```
bazel test @llvm-project//libc/... --test_tag_filters=-llvm-libc-overlay-only --@llvm-project//libc:build_mode=full
```

Bazel is already able to tell which tests need to be skipped by using `target_compatible_with`, but using tags allows consumers to configure their CI so no tests get implicitly skipped.
DeltaFile
+14-1utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl
+3-0utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl
+1-0utils/bazel/llvm-project-overlay/libc/test/src/complex/BUILD.bazel
+19-14 files

LLVM/project a51479bmlir/lib/ExecutionEngine ExecutionEngine.cpp, mlir/lib/Target/LLVM ModuleToObject.cpp

mlir: Avoid using TargetMachine::createDataLayout

This should pass in an ABI name, but there doesn't appear to
be one around in context.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-1mlir/lib/Target/LLVMIR/Transforms/TargetUtils.cpp
+1-1mlir/lib/Target/LLVM/ModuleToObject.cpp
+1-1mlir/lib/ExecutionEngine/ExecutionEngine.cpp
+4-33 files

OpenBSD/ports FIxkIcpwww/webkitgtk4 Makefile

   BDEP on multimedia/gstreamer1/plugins-bad until I figure out if it's also
   needed at runtime; this quickly unbreaks the build

   spotted by naddy@
VersionDeltaFile
1.266+3-0www/webkitgtk4/Makefile
+3-01 files

LLVM/project 826f78dlldb/test/Shell/SymbolFile/NativePDB unknown-udt-decl.ll rust-unique-name.ll

lldb: Require x86_64 for x86_64-specific NativePDB tests (#224140)

These tests contained x86_64 datalayout and triples, but only
required system-windows. On an aarch64 windows host, %build will
be an incompatible datalayout, so require exactly x86_64 windows
hosts. Alternatively the test could be changed to not have the
datalayout, but I'm not sure if that's correct here.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+1-1lldb/test/Shell/SymbolFile/NativePDB/unknown-udt-decl.ll
+1-1lldb/test/Shell/SymbolFile/NativePDB/rust-unique-name.ll
+2-22 files

LLVM/project 33594a8.ci all_requirements.txt, clang/test/CodeGen builtin-clear-padding-codegen.c

Merge branch 'main' into users/adams381/cir-explicit-nothrow-willreturn
DeltaFile
+4,402-1,088clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+2,801-612clang/test/CodeGen/builtin-clear-padding-codegen.c
+602-459.ci/all_requirements.txt
+815-0llvm/test/Transforms/PhaseOrdering/ARM/arm_mat_mult_q31.ll
+478-308llvm/utils/git/requirements_linting.txt
+383-393llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+9,481-2,8601,267 files not shown
+49,708-13,2711,273 files

LLVM/project 42a1f57clang/test/CodeGen builtin-clear-padding-codegen.c, clang/test/CodeGenCXX builtin-clear-padding-codegen.cpp

Merge branch 'main' into users/adams381/cir-ptr-mask
DeltaFile
+4,377-4,141llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,753-0llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td
+2,822-2,774llvm/test/CodeGen/AMDGPU/bf16.ll
+4,402-1,088clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+2,633-2,496llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+2,801-612clang/test/CodeGen/builtin-clear-padding-codegen.c
+22,788-11,1112,078 files not shown
+111,378-56,3312,084 files

LLVM/project 870d762clang/lib/StaticAnalyzer/Checkers/WebKit RawPtrRefLambdaCapturesChecker.cpp, clang/test/Analysis/Checkers/WebKit uncounted-lambda-captures.cpp

[webkit.UncountedLambdaCapturesChecker] NOESCAPE is ignored in a template function (#223942)

RawPtrRefLambdaCapturesChecker only consults NOESCAPE when it can find a
FunctionDecl for a call. Because a lambda argument is type-dependent, a
call taking one inside a template is dependent, and its callee is often
still unresolved in the template pattern: an UnresolvedLookupExpr for an
unqualified call or a call to a function template, an
UnresolvedMemberExpr for an overloaded member function or a member
function template, and a CXXDependentScopeMemberExpr for a member of a
dependent object. checkParameters never ran for those, so a lambda was
reported even when the parameter it's passed to is annotated with
NOESCAPE. The same happened for a lambda passed to a constructor which
isn't resolved until the instantiation, which appears as a
CXXUnresolvedConstructExpr or as a dependent ParenListExpr /
InitListExpr.

Whether such a lambda can escape isn't known before the enclosing
template is instantiated, so ignore these lambdas and let the
instantiation check them, matching what RetainPtrCtorAdoptChecker

    [10 lines not shown]
DeltaFile
+165-0clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
+63-5clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
+228-52 files

LLVM/project c3bfaa8llvm/lib/Transforms/Scalar ConstraintElimination.cpp

[ConstraintElim] Move helper to create constraint row (NFC) (#224417)

Move logic to grate a new row for the constraint system to helper, to
more clearly separate logic, and allow re-use in follow-ups.

This includes minor code reodering in the moved logic.
DeltaFile
+56-47llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+56-471 files

OpenBSD/ports hh2otcadevel/quirks Makefile, devel/quirks/files Quirks.pm

   Register removal of gemini-cli.
VersionDeltaFile
1.1831+2-1devel/quirks/files/Quirks.pm
1.1817+1-1devel/quirks/Makefile
+3-22 files