[mlir][sparse][gpu] Add libgen support for transposed SpMV and SpMM (#230412)
This change adds libgen support for transposed SpMV and SpMM in the
sparse-gpu-codegen pass by recognizing `y = A^Tx` for SpMV and `y =
A^TB`, `y = AB^T`, and `y = A^TB^T` for SpMM. Tests have been added to
the SparseTensor dialect for these changes. Tests are also added in the
GPU dialect for lowering to GPU runtime calls as it was previously
missing.
Assisted by Codex
[Clang] Implement CWG2900 (#224291)
We did not implement the CWG200 changes to [dcl.type.auto.deduct] The
rest seems to be working - I added tests, both for this issue and all
examplars in the wording.
(i.e, deducing `auto` from a `decltype(auto)` template parameter is
rejected)
I thought it was cleaner to reuse getNTTParameterFromExpr rather than
duplicating it, so there is a bunch of churn there to rename it.
Note that GCC doesn't seem to fully support that resolution ( To say
nothing of other implementations).
Assisted-By: Opus 5.
[libc] Implement syncfs in unistd (#230855) (#231129)
Implement the Linux extension function `syncfs(int fd)` in `<unistd.h>`.
Fixes #230855.
Assisted by Antigravity and reviewed by Aman Maurya.
TableGen: Avoid heap allocation when resolving bits
Instruction encodings are commonly 64 to 128 bits, which overflowed the
16 element inline buffer and needed a heap allocation in 44% of the
calls when parsing AMDGPU.td.
Gigainstructions executed by llvm-tblgen --null-backend
before after
AMDGPU.td 16.97 16.95 -0.1%
X86.td 5.84 5.83 -0.1%
AArch64.td 3.00 2.99 -0.3%
RISCV.td 7.44 7.44 -0.1%
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Store classes and defs in a StringMap
Classes and defs were kept in a std::map ordered by name, which makes
every lookup a series of string comparisons over names that often share
long prefixes. Store them in a StringMap instead, and have getClasses()
and getDefs() return a list sorted by name, built when first needed
after records are added.
Gigainstructions executed by llvm-tblgen --null-backend
before after
AMDGPU.td 18.17 16.98 -6.6%
X86.td 6.15 5.84 -5.1%
AArch64.td 3.32 3.00 -9.7%
RISCV.td 8.26 7.44 -9.9%
Including the backends, all tablegen runs in a build of all targets and
clang execute 3.1% fewer instructions in total, and none are slower.
Peak memory parsing AMDGPU.td drops from 835 MB to 830 MB.
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TableGen: Cache resolved class instantiations
The same class instantiation is often referenced many times in one
record, and each reference was resolved from scratch along with
everything nested in its arguments. Cache the results in MapResolver and
RecordResolver, and share them with any TrackUnresolvedResolver wrapping
those.
Gigainstructions executed by llvm-tblgen --null-backend
before after
AMDGPU.td 71.75 18.22 -74.6%
X86.td 6.10 6.15 +0.8%
AArch64.td 3.28 3.32 +1.3%
RISCV.td 8.18 8.26 +1.0%
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
pf: Do not corrupt neighbour advertisements when translating
When an ICMPv6 query or reply matches a translated state,
pf_test_state_icmp() copies the state's virtual id into icmp6_id. Only
echo messages have an identifier there. For all other types the
virtual id is 0 and those two bytes hold something else; in a neighbour
advertisement they hold the R, S and O flags. The checksum was not
updated either, so icmp6_input() dropped the advertisement as a bad
checksum.
Unicast NUD probes to a link-local neighbour, such as the default
router, are sent from the link-local address. With a nat rule that
matches it (e.g. "from any"), every advertisement answering a probe was
dropped: NUD failed, the neighbour cache entry was deleted, and traffic
to the neighbour stalled until it was resolved again.
Only rewrite the id of echo messages, as the ICMPv6 error path already
does, and update the checksum, as the IPv4 path does.
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Revert "[clang][DepScan] Disable relocation checks" (#231244)
This reverts commit dd3534fd5af15575d0d8dea116740b2abb8f3328.
Which effectively re-enables relocation checking after the underlying
issue has been addressed in d397ab3cacd6
[clangd] Use timeout multiplier inside ClangdServer::blockUntilIdleForTest() for UBSan builds (#230221)
It looks like the reason of this failure
https://lab.llvm.org/buildbot/#/builders/25/builds/20042 is in missing
UBSan in the list of sanitizers for which we use multiplier for timeout
auditdistd: Use fixed-length protocol names
All communication between auditdistd senders and receivers and
internally between auditdistd and its worker children passes through the
same pair of send / receive functions. The receive function uses
recv(2) with the MSG_WAITALL flag, which in theory means we should never
get a short read. However, when handing off a socket to a worker child,
we also pass a variable-length string identifying the type of socket
we're passing, and reading this string relies on a short read. This
used to work because the arrival of the descriptor would interrupt the
recv(2) call, but this bug was fixed when the AF_UNIX code was rewritten
a while ago and auditdistd has been broken ever since.
Fixing the length of the protocol name to four characters including the
terminating null solves the short-read bug by never requiring a short
read (nothing else in auditdistd requires one).
PR: 296107
MFC after: 1 week
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pf: Free a table entry that cannot be routed
pfr_insert_kentry() returned the error of pfr_route_kentry() and
leaked the entry it had created; pfr_insert_kentries() stopped at the
first entry it could not route and leaked it and the rest of the work
queue, which no caller frees. Destroy an entry that cannot be routed
and go on with the next.
Reviewed by: kp
MFC after: 2 weeks
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D60532
NAS-144450 / 28.0.0-BETA.1 / Fix alerts test (#20006)
Wait for `VolumeStatus` alert by class instead of source. If another
alert from that source appears (e.g., boot pool status alert), the test
breaks because `volume` key is not there:
```
def wait_for_alert(timeout=120):
for _ in range(timeout):
for alert in call("alert.list"):
if (
alert["source"] == "VolumeStatus"
and alert["args"]["volume"] == pool_name
^^^^^^^^^^^^^^^^^^^^^^^
and alert["args"]["state"] == "DEGRADED"
):
E KeyError: 'volume'
```
x11/kitty: Add option CUSTOM_SHADERS
- The new option enables custom shaders in Kitty and is off by default
(to avoid the dependency on Linuxator at runtime).
- Add a patch to fix the error message when the user has added custom
shaders in the config file, but shader-slang is not installed
- Pet portfmt
- Bump PORTREVISION (list of dependencies changed)
PR: 299339
FunctionAttrs: Check all uses when inferring captures for argument SCCs (#231536)
When merging the capture components of an SCC of arguments, only the
first use of each argument was considered, because of a misplaced break.
If an argument was passed to another argument in the SCC first and to a
capturing argument outside of it later, it was incorrectly inferred to
not be captured.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Attributor: Don't privatize pointers to types with tail padding
isDenselyPacked checked for padding before and between struct elements, but
not after the last one, so { ptr, i32 } was considered densely packed. The
padding bytes are not passed when the argument is privatized, which broke
sqlite3 when the pointer was to a union containing such a struct.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
arm64/vmm: Treat Rt=31 as xzr in reg & instr emul
For certain instructions like msr, mrs, ldr & str, Rt=31 means the
operand is the Zero register (XZR) as opposed to the SP, even though the
two share the encoding of 31 on AArch64.
This is currently ignored in register and instruction emulation, so
emulated guest operations like "msr <reg>, xzr" will set the value of
<reg> to the current value of the SP instead of to 0.
Skip set and get operations when Rt=31 to correct the behaviour.
Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>
Reviewed by: andrew
Sponsored by: Arm Ltd
Pull Request: https://github.com/freebsd/freebsd-src/pull/2454
arm64: Relax memory barriers around DMA operations
Before and after DMA operations we need memory barriers to ensure
stores on the CPU are observed by the device, and stores by the device
are observed by the CPU.
Previously we used a "dsb sy" instruction, however this is too strong
and can lead to slower performance.
Drew Gallatin found and tested the issue with cache-coherent devices,
reducing the barriers to dmb instructions in the outer-shareable
domain. After discussing the issue with the Arm Linux DMA maintainer I
concluded it was safe for non-coherent devices as the only dsb
instructions we need are after cache operations and these already exist.
Replace the dsb before DMA with a "dmb oshst" when cache-coherent, or
the existing dsb after invalidating the cache when not coherent. This
ensures earlier stores have completed before we signal the device.
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Attributor: Count accesses through null pointers cast to another address space
AAMemoryLocation ignored accesses through null if null was not
dereferenceable in either the access or the null pointer's address space.
A null pointer cast to another address space may be a valid address there,
e.g. addrspacecast (ptr addrspace(5) null to ptr) where null is valid in
addrspace(5), so functions accessing memory through it were wrongly
deduced memory(none). Only ignore accesses through null in its own
address space, where they are undefined.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[LV] Don't fold outer mixed zext/sext into mul-acc reduction multiply. (#231189)
tryToMatchAndCreateMulAccumulateReduction rewrites in-loop reductions of
ext(mul(ext(A), ext(B))) to mul(wide_ext(A), wide_ext(B)). If both mul
operands are the same extend, the outer extend kind was allowed to
differ from the inner one, assuming the square is never negative. That
only holds for sext inner extends; the narrow mul of two zexts can set
the sign bit, e.g. sext(mul i16 (zext i8 200), (zext i8 200)) is
sext(-25536), not 40000.
Only allow differing kinds if the inner extend is a sext.
Alive2 Proof: https://alive2.llvm.org/ce/z/mKqprz
PR: https://github.com/llvm/llvm-project/pull/231189
[NVPTX] Follow up 9386502801a0: Disable bf16 comparison FTZ (#231444)
PTX does not define .ftz for bf16 comparisons, so commit 9386502801a0
could generate invalid PTX. This fixes that by not allowing FTZ for bf16
for these newly added patterns.
Rename variable names for consistency
mechnical changes: ncas to ca_tree, ncas_hist to nca_hist_tree, tree to
ca_tree, and needle to nca_hist_needle.
OK tb@
