AMDGPU: Remove dead code configuring f16 is_fpclass (#177626)
isTypeLegal can never be true here. The register classes
are registered at the end of the target lowering constructor,
and in the subclasses.
[NFCI][AMDGPU] Fix the predicate `HasDsSrc2Insts` (#177621)
I'm not sure why the predicate has a `!`, and more surprisingly,
removing it doesn't change anything.
MAINTAINERS: Remove some stale entries
Remove some stale entries, preen some others. Longer term, we need a
better format. Also, if there's mistakes, let us know: we want it to be
useful to people seeking review, not be perscriptive about who can do
what.
Reviewed by: srcmgr@
[clang][test] Fix builtin-rotate.c failure on ARM32 (#177290)
Replace unsigned __int128 with unsigned _BitInt(128) since __int128 is
not supported on ARM 32-bit targets.
Fixes https://lab.llvm.org/buildbot/#/builders/79/builds/2754
[VectorCombine] foldShuffleOfBinops - failure to track OperandValueInfo (#171934)
Resolves #170500.
Implemented mergeInfo static helper to return common
TTI::OperandValueInfo data .
Added common OperandValueInfo `Op0Info` && `Op1Info` to NewCost
calculation.
AMDGPU: Ignore type legality in isFAbsFree
This treats it as free on targets without legal f16. This
matches the existing logic in fneg, and they should be the same.
The test changes are mostly neutral with a few improvements.
[RISCV][llvm-objdump] Support --symbolize-operands (#166656)
This adds support for `--symbolize-operands`, so that local references
are turned back into labels by objdump, which makes it easier to tell
what is going on with a linked object.
When using `--symbolize-operands`, branch target addresses are not
printed, only the referenced symbol is printed, and the address is
elided:
```
# Without --symbolize-operands
0: 04a05263 blez a0, 0x44 <.text+0x44>
...
40: fd1ff06f j 0x10 <.text+0x10>
44: 00000613 li a2, 0x0
# With --symbolize-operands
0: 04a05263 blez a0, <L3>
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17835 Update AMD microcode to 20251202
Reviewed by: Robert Mustacchi <rm+illumos at fingolfin.org>
Reviewed by: Toomas Soome <tsoome at me.com>
Approved by: Gordon Ross <gordon.w.ross at gmail.com>
AMDGPU: Remove dead code configuring f16 is_fpclass
isTypeLegal can never be true here. The register classes
are registered at the end of the target lowering constructor,
and in the subclasses.
libc++ inttypes.h: define __STDC_CONSTANT_MACROS and __STDC_LIMIT_MACROS
Before transitively including the base version of inttypes.h, define
__STDC_CONSTANT_MACROS and __STDC_LIMIT_MACROS, because the base
inttypes.h directly includes sys/stdint.h, instead of going through the
'regular' stdint.h.
The libc++ version of the latter does define those macros, to ensure
things like UINT64_C() and SIZE_MAX are defined even in C++98 or C++03.
MFC after: 3 days
[NFCI][AMDGPU] Fix the predicate `HasDsSrc2Insts`
I'm not sure why the predicate has a `!`, and more surprisingly, removing it doesn't change anything.
[AMDGPU][GFX1250] Optimize s_wait_xcnt for back-to-back atomic RMWs
This patch optimizes the insertion of s_wait_xcnt instruction for
sequences of atomic read-modify-write (RMW) operations in the
SIInsertWaitcnts pass. The Memory Legalizer conservatively inserts a
soft xcnt instruction before each atomic RMW operation as part of PR
168852, which is correct given the nature of atomic operations.
However, for back-to-back atomic RMWs, only the first s_wait_xcnt is
necessary for better runtime performance. This patch tracks atomic
RMW blocks within each basic block and removes redundant soft xcnt
instructions, keeping only the first wait in each sequence. An atomic
RMW block continues through subsequent atomic RMWs and non-memory
instructions (e.g., ALU operations) but is broken by CU-scoped memory
operations, atomic stores, or basic block boundaries.
[SPIR-V] Implement sample and sample_clamp intrinsics for HLSL resources (#177234)
This patch implements the `sample` and `sample_clamp` intrinsics for
HLSL
resources in the SPIR-V backend. It adds the necessary intrinsic
definitions
in `IntrinsicsDirectX.td` and `IntrinsicsSPIRV.td`, and implements the
instruction selection logic in `SPIRVInstructionSelector.cpp`.
Key changes:
- Added `int_dx_resource_sample` and `int_dx_resource_sample_clamp`
intrinsics.
- Added `int_spv_resource_sample` and `int_spv_resource_sample_clamp`
intrinsics.
- Implemented `selectSampleIntrinsic` to handle
`OpImageSampleImplicitLod` generation.
- Added `ResourceDimension` enum in `DXILABI.h` and `HLSLResource.h`.
- Added a new test case
`llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll` to verify the
implementation.
[flang] Support -f(no-)protect-parens (#170505)
Driver/compiler option plumbing to get -f(no-)protect-parens supported
on flang. (This option was already supported in clang, so extended the
option config to enable it in flang.)
In the compiler, support it in code gen options and in lowering options.
Hooked up lowering options with the code by @alexey-bataev that turns
off reassociation transformations.
Co-authored-by: Alexey Bataev <a.bataev at outlook.com>
[lldb] Unconditionally setup posix spawn responsible flag (#177451)
# Problem
The TCC support in LLDB was added by
https://github.com/llvm/llvm-project/commit/041c7b84a4b925476d1e21ed302786033bb6035f.
However, on newer macOS machines, when launching and debugging an
Catalyst app on macOS (see
[Host.mm](https://github.com/llvm/llvm-project/blob/1286de408cc4a3ba1bd6cb6fed7d9517c0429462/lldb/source/Host/macosx/objcxx/Host.mm#L1208-L1219)),
the TCC doesn't work as expected. This is because, even though the
launch info doesn't specify `eLaunchFlagInheritTCCFromParent`, the app
is still launched to inherit TCC from its parent (the LLDB). This
prevents the user from granting privacy access to the Catalyst app,
which is usually reflected in macOS' "Privacy & Security" settings.
For example, in the following screenshot (see PR), even when the microphone
access has already been granted to WhatsApp, trying to use it will still
cause a prompt (as if it's not granted already).
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[clang-tidy] Add a new check 'modernize-use-string-view' (#172170)
Looks for functions returning `std::[w|u8|u16|u32]string` and suggests
to change it to `std::[...]string_view` if possible and profitable.
Example:
```cpp
std::string foo(int i) { // <---- can be replaced to `std::string_view foo(...) {`
switch(i) {
case 1:
return "case1";
case 2:
return "case2";
default:
return {};
}
}
```
Fix SATA NCQ error recovery after 25375b1415
Since that commit ahci(4), siis(4) and mvs(4) drivers ended up
using wrong command to fetch error information for NCQ commands.
Since ATA errors are not very informative to begin with, the only
noticeable effect is a lack of retries on those errors by CAM.
MFC after: 1 week
PR: 279978
(cherry picked from commit 87085c12ba8fa51f777bc636df67008b45e20d1c)
