LLVM/project bd3b06bllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.class.ll llvm.amdgcn.class.f16.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn.class (#178827)
DeltaFile
+71-32llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
+33-15llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
+8-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
+113-494 files

LLVM/project bb369f1libc/src/string/memory_utils op_x86.h, libc/src/string/memory_utils/x86_64 inline_memcpy.h

[libc][x86] Add Non-temporal code path for large memcpy (#187108)

Large memcopies are pretty rare, but are more common in ML workloads
(copying large matrixes/tensors, often to/from CPU host).

For large copies NTA stores can provide performance advantages for both
memcpy itself and the rest of the workload (by reducing cache
pollution). Other runtimes already have NTA path for large copies, so
add 1 to the llvm-libc.

Internal whole-program loadtests shows small, but statistically
significant improvement of 0.1%. ML specific bencahmrks showed 10-20%
performance gain, and fleetbench (https://github.com/google/fleetbench,
which has more up-to-date version of libc benchmarks) shows ~3% gain
(ns/byte for distributions taken from various applications).

```
[Memcpy_0]_L1      0.01950n ± 3%   0.01900n ± 5%       ~ (p=0.390 n=20)
[Memcpy_0]_L2      0.02300n ± 0%   0.02300n ± 0%       ~ (p=0.256 n=20)

    [35 lines not shown]
DeltaFile
+34-8libc/src/string/memory_utils/x86_64/inline_memcpy.h
+10-0libc/src/string/memory_utils/op_x86.h
+44-82 files

LLVM/project 827ddb2llvm/test/CodeGen/AMDGPU waitcnt-wcg-attributes.mir

[AMDGPU][SIInsertWaitcnts] Add test functions in waitcnt-wcg-attributes.mir (#186504)

This patch adds two more functions for exercising the target-cpu
attribute.
DeltaFile
+44-3llvm/test/CodeGen/AMDGPU/waitcnt-wcg-attributes.mir
+44-31 files

LLVM/project dd30239llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU convergent.mir

[AMDGPU] Add basic verification for source modifiers (#186733)

Source modifiers (input modifiers) should always be immediates.
This commit made machine verifier reject non-immediate source modifiers.

Closes #182243
DeltaFile
+30-0llvm/test/MachineVerifier/AMDGPU/invalid-vop3-source-modifiers.mir
+10-10llvm/test/CodeGen/AMDGPU/convergent.mir
+1-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+41-113 files

FreeNAS/freenas 2b09997src/middlewared/middlewared/common/ports __init__.py, src/middlewared/middlewared/plugins/ports ports.py

Add batch port validation endpoint port.validate_ports
DeltaFile
+178-0src/middlewared/middlewared/pytest/unit/plugins/test_port_attachments.py
+57-38src/middlewared/middlewared/plugins/ports/ports.py
+6-0src/middlewared/middlewared/common/ports/__init__.py
+241-383 files

LLVM/project 498dd13llvm/lib/Target/AMDGPU DSInstructions.td, llvm/test/MC/AMDGPU gfx13_asm_vds.s gfx13_asm_vds_alias.s

Add VDS encoding for gfx13 (#187693)

Co-authored-by: Jay Foad <jay.foad at amd.com>
DeltaFile
+1,987-0llvm/test/MC/AMDGPU/gfx13_asm_vds.s
+179-149llvm/lib/Target/AMDGPU/DSInstructions.td
+147-0llvm/test/MC/AMDGPU/gfx13_asm_vds_alias.s
+2,313-1493 files

LLVM/project 950eaaaclang/lib/Sema SemaLookup.cpp

[Clang] Use stable_sort for UnqualUsingDirectiveSet for determinism in ambiguity notes (#187750)

In SemaLookup.cpp, `UnqualUsingDirectiveSet::done()` uses `llvm::sort`
with a comparator that only checks the ancestor relationships. So, if
there are multiple "neighbor" namespaces, they are considered equal, and
thus `llvm::sort` may return the using directives in a non-deterministic
order.

This was observed as a test failure on clang/test/CXX/drs/cwg0xx.cpp at
line 220 after PR #187219 started verifying the diagnostics ordering.
The two "candidate found by name lookup" notes were emitted in the
opposite order from the test's expectations -- in some builds of Clang,
but not others.

Switching to `llvm::stable_sort` ensures that using-directives are
always traversed in a deterministic order, and thus the notes emitted
deterministically.
DeltaFile
+1-1clang/lib/Sema/SemaLookup.cpp
+1-11 files

LLVM/project cfc94a6flang/include/flang/Semantics openmp-utils.h, flang/lib/Semantics openmp-utils.cpp check-omp-loop.cpp

[flang][OpenMP] Introduce `WithReason<T>` for nest/sequence properties (#187563)

This helper class contains an optional value and a "reason" message. It
replaces the uses of std::pair<optional<...>, Reason>.

Issue: https://github.com/llvm/llvm-project/issues/185287
DeltaFile
+73-36flang/lib/Semantics/openmp-utils.cpp
+34-8flang/include/flang/Semantics/openmp-utils.h
+18-19flang/lib/Semantics/check-omp-loop.cpp
+125-633 files

FreeBSD/ports 04b7169cad/kicad pkg-plist, cad/kicad-doc pkg-plist

cad/kicad: update KiCad and libraries to 10.0.0

Announcement:
  https://www.kicad.org/blog/2026/03/Version-10.0.0-Released/
DeltaFile
+16-6,823cad/kicad-library-packages3d/pkg-plist
+169-95cad/kicad/pkg-plist
+0-134cad/kicad-doc/pkg-plist
+47-34cad/kicad-library-footprints/pkg-plist
+0-37cad/kicad/files/patch-eeschema_sch__io_easyedapro_sch__io__easyedapro.cpp
+18-0cad/kicad/files/patch-thirdparty_thread-pool_bs__thread_pool.hpp
+250-7,12314 files not shown
+288-7,16720 files

FreeNAS/freenas 779fdfcsrc/middlewared_docs/docs rbac.rst index.rst

NAS-140382 / 26.0.0-BETA.2 / Add API documentation for RBAC (by anodos325) (#18537)

This commit adds explicit documentation for how the API roles framework
works as well as some rough examples of how to create custom roles.

Original PR: https://github.com/truenas/middleware/pull/18529

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+221-0src/middlewared_docs/docs/rbac.rst
+1-0src/middlewared_docs/docs/index.rst
+222-02 files

LLVM/project 74f88c8clang/lib/CodeGen CodeGenTypes.cpp, clang/test/CodeGen builtins-extended-image.c builtins-image-load.c

[Clang][AMDGPU] Lower __amdgpu_texture_t to <8 x i32> instead of ptr addrspace(0)
DeltaFile
+220-264clang/test/CodeGen/builtins-extended-image.c
+210-252clang/test/CodeGen/builtins-image-load.c
+140-168clang/test/CodeGen/builtins-image-store.c
+5-5clang/test/CodeGen/amdgpu-image-rsrc-type-debug-info.c
+7-2clang/lib/CodeGen/CodeGenTypes.cpp
+582-6915 files

LLVM/project 78b651allvm/lib/Target/RISCV RISCVSchedSiFive7.td, llvm/test/tools/llvm-mca/RISCV/SiFiveX100 floating-point.test zfhmin.test

[RISCV] Fix the pipe used by `fmv.x.<fp>/<fp>.x` in SiFive7 sched model (#187740)

These FP <-> Integer conversion instructions should use PipeA instead.
DeltaFile
+9-9llvm/test/tools/llvm-mca/RISCV/SiFiveX100/floating-point.test
+6-6llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+5-5llvm/test/tools/llvm-mca/RISCV/SiFiveX100/zfhmin.test
+20-203 files

FreeNAS/freenas 174437fsrc/middlewared/middlewared/alembic/versions/26.0 2026-03-19_00-00_add_zfs_tier_config.py, src/middlewared/middlewared/alert/source zfs_tier.py

Make several changes

* Fix config file generation for new time-based backoff
* Use truenas_zfsrewrited_client APIs consistently
* Add new config field
DeltaFile
+29-95src/middlewared/middlewared/plugins/zfs/tier.py
+9-9src/middlewared/middlewared/alert/source/zfs_tier.py
+6-0src/middlewared/middlewared/api/v27_0_0/zfs_tier.py
+6-0src/middlewared/middlewared/api/v26_0_0/zfs_tier.py
+2-1src/middlewared/middlewared/alembic/versions/26.0/2026-03-19_00-00_add_zfs_tier_config.py
+1-1src/middlewared/middlewared/etc_files/truenas_zfsrewrited.py
+53-1066 files

FreeNAS/freenas 623fb27src/middlewared_docs/docs rbac.rst index.rst

NAS-140382 / 27.0.0-BETA.1 / Add API documentation for RBAC (#18529)

This commit adds explicit documentation for how the API roles framework
works as well as some rough examples of how to create custom roles.
DeltaFile
+221-0src/middlewared_docs/docs/rbac.rst
+1-0src/middlewared_docs/docs/index.rst
+222-02 files

FreeNAS/freenas 2e10364

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 0b6dff0src/middlewared/middlewared/common/ports __init__.py, src/middlewared/middlewared/plugins/ports ports.py __init__.py

NAS-140387 / 27.0.0-BETA.1 / Add batch port validation endpoint `port.validate_ports` (#18532)

This commit adds a new `port.validate_ports` endpoint that validates
multiple port/bindip combinations in a single call. Currently the apps
library calls `port.validate_port` once per port, each of which
internally queries all registered port delegates via `ports_mapping()`.
For apps with many ports (e.g. SeaweedFS with 15), this results in
redundant repeated work.

The new endpoint accepts a list of `{"port": int, "bindip": str}` dicts
and calls `ports_mapping()` only once for the entire batch. It supports
two modes:
- `raise_error=True`: raises a single `ValidationErrors` with all
conflicts (same pattern as the existing endpoint)
- `raise_error=False`: returns a JSON-serializable list of `(attribute,
errmsg, errno)` tuples

The existing `validate_port` endpoint is refactored to share a
`_validate_single_port` helper but its inputs, outputs, and behavior are
unchanged.
DeltaFile
+178-0src/middlewared/middlewared/pytest/unit/plugins/test_port_attachments.py
+57-8src/middlewared/middlewared/plugins/ports/ports.py
+26-1src/middlewared/middlewared/plugins/ports/__init__.py
+6-1src/middlewared/middlewared/common/ports/__init__.py
+267-104 files

LLVM/project 92187cdclang/test/OpenMP target_teams_distribute_parallel_for_simd_schedule_codegen.cpp teams_distribute_parallel_for_simd_schedule_codegen.cpp, libc/AOR_v20.02/math/test/traces sincosf.txt exp.txt

Rebase

Created using spr 1.3.7
DeltaFile
+0-31,999libc/AOR_v20.02/math/test/traces/sincosf.txt
+0-16,000libc/AOR_v20.02/math/test/traces/exp.txt
+5,294-4,814clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+5,238-4,758clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+4,350-4,098clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
+4,004-3,524clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
+18,886-65,1937,577 files not shown
+472,109-314,9597,583 files

LLVM/project 9b428dbllvm/test/Transforms/LoopVectorize pointer-induction-index-width-smaller-than-iv-width.ll

[NFC][LV] Fix what seems to be a typo in the test

The test was added in https://github.com/llvm/llvm-project/commit/4e9894498e166ef6b207c25e780db0b6f006cc89.

Alternative fixes would be:
* Remove unused GEP, although not clear why we'd want to overwrite
  stored `i64` with `ptr` store.
* Keep this patch, but perform both GEPs with `i64` element type to
  reduce the diff. It's not clear if the scalarization caused by that
  type mismatch is intentional/relevant for the original change.
DeltaFile
+14-33llvm/test/Transforms/LoopVectorize/pointer-induction-index-width-smaller-than-iv-width.ll
+14-331 files

FreeBSD/src e296211. Makefile.inc1

Makefile.inc1: Don't force LLVM_BINUTILS off for cross-tools

Because of this setting we were still using ELF Tool Chain tools for
buildworld.  The sets of binary utilities are largely equivalent and
this went unnoticed after commit 1cae7121c667 ("Enable LLVM_BINUTILS
by default").

This was discovered recently because ELF Tool Chain objcopy produces
standalone debug files without phdrs and this caused an issue with a
3rd party ELF parser [1].  Remove the forced setting so that we use
LLVM's binutils to build the system.

[1] https://sourceware.org/bugzilla/show_bug.cgi?id=33876

Re-commit after fixing a bootstrapping issue with LLVM binutils (in
17494c6e6b7d "build: Boostrap LLVM_BINUTILS for cross-tools").

Reviewed by:    imp, jhb
Sponsored by:   The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D55650
DeltaFile
+0-1Makefile.inc1
+0-11 files

FreeNAS/freenas 1d89e58src/middlewared/middlewared/plugins/iscsi_ iscsi_global.py

flake8
DeltaFile
+4-1src/middlewared/middlewared/plugins/iscsi_/iscsi_global.py
+4-11 files

LLVM/project 63c9573llvm/test/Transforms/LoopStrengthReduce/X86 reuse-existing-phi.ll

[LSR] Add regression test for unnecessary phi introduction (#187751)

Test case for https://github.com/llvm/llvm-project/issues/187728
DeltaFile
+34-0llvm/test/Transforms/LoopStrengthReduce/X86/reuse-existing-phi.ll
+34-01 files

Linux/linux 42bddabfs binfmt_elf_fdpic.c, fs/tests exec_kunit.c

Merge tag 'execve-v7.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux

Pull execve fixes from Kees Cook:

 - binfmt_elf_fdpic: fix AUXV size calculation (Andrei Vagin)

 - fs/tests: exec: Remove bad test vector

* tag 'execve-v7.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux:
  fs/tests: exec: Remove bad test vector
  binfmt_elf_fdpic: fix AUXV size calculation for ELF_HWCAP3 and ELF_HWCAP4
DeltaFile
+6-0fs/binfmt_elf_fdpic.c
+0-3fs/tests/exec_kunit.c
+1-1include/linux/auxvec.h
+7-43 files

LLVM/project ca05871clang/lib/CodeGen CodeGenTypes.cpp, clang/test/CodeGen builtins-extended-image.c builtins-image-load.c

[Clang][AMDGPU] Lower __amdgpu_texture_t to <8 x i32> instead of ptr addrspace(0)
DeltaFile
+220-264clang/test/CodeGen/builtins-extended-image.c
+210-252clang/test/CodeGen/builtins-image-load.c
+140-168clang/test/CodeGen/builtins-image-store.c
+5-5clang/test/CodeGen/amdgpu-image-rsrc-type-debug-info.c
+6-2clang/lib/CodeGen/CodeGenTypes.cpp
+581-6915 files

LLVM/project a5c6dd7flang/include/flang/Semantics openmp-utils.h

Delete unused header
DeltaFile
+0-1flang/include/flang/Semantics/openmp-utils.h
+0-11 files

LLVM/project 688090bllvm/test/CodeGen/AMDGPU llvm.amdgcn.class.ll llvm.amdgcn.class.f16.ll

Rebased and updated tests
DeltaFile
+91-163llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
+0-24llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
+91-1872 files

Linux/linux d46d5c8drivers/tty/serial/8250 8250_dw.c 8250_port.c, drivers/tty/vt vt.c

Merge tag 'tty-7.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

Pull tty/serial fixes from Greg KH:
 "Here are some small tty/vt and serial driver fixes for 7.0-rc5.
  Included in here are:

   - 8250 driver fixes for reported problems

   - serial core lockup fix

   - uartlite driver bugfix

   - vt save/restore bugfix

  All of these have been in linux-next for over a week with no reported
  problems"

* tag 'tty-7.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty:
  vt: save/restore unicode screen buffer for alternate screen

    [12 lines not shown]
DeltaFile
+239-65drivers/tty/serial/8250/8250_dw.c
+45-30drivers/tty/serial/8250/8250_port.c
+25-0drivers/tty/serial/8250/8250.h
+17-0drivers/tty/serial/8250/8250_pci.c
+15-0drivers/tty/serial/8250/8250_dma.c
+8-0drivers/tty/vt/vt.c
+349-954 files not shown
+356-9610 files

FreeBSD/src 1fd43eesys/dev/tpm tpm20.c tpm_tis_core.c

tpm: fix multi-threaded access with per-open state

The TPM driver currently has a single buffer per instance to hold the
result of a command, and does not allow subsequent commands to be sent
until the current result is read by the same OS thread that sent the
command, with a timeout to throw away the result after a while if the
result is not read in a timely fashion.  This has a couple problems:

 - The timeout code has a bug which causes all subsequent commands to
   hang forever if a different OS thread tries to read the result
   before the OS thread which sent the command, and the OS thread
   which sent the command never tries to read the result.

 - Even if the first problem is fixed, applications expect to be able
   to read the result from a different OS thread than the OS thread
   which sent the command. The particular case that we saw was a go
   application where the go runtime scheduled the goroutine which read
   the result to a different OS thread from one where the goroutine
   that sent the command ran, and there's no way to force these to

    [11 lines not shown]
DeltaFile
+46-70sys/dev/tpm/tpm20.c
+14-14sys/dev/tpm/tpm_tis_core.c
+9-10sys/dev/tpm/tpm_crb.c
+7-6sys/dev/tpm/tpm20.h
+5-0sys/dev/tpm/tpm_if.m
+81-1005 files

FreeNAS/freenas aab24aasrc/middlewared/middlewared/alembic/versions/26.0 2026-03-20_15-53_iscsi_mode.py

Add alembic migration for iSCSI mode
DeltaFile
+26-0src/middlewared/middlewared/alembic/versions/26.0/2026-03-20_15-53_iscsi_mode.py
+26-01 files

FreeNAS/freenas be83468src/middlewared/middlewared/api/v26_0_0 iscsi_global.py, src/middlewared/middlewared/plugins dlm.py

Add mode to iSCSI config
DeltaFile
+22-0src/middlewared/middlewared/plugins/iscsi_/iscsi_global.py
+10-6src/middlewared/middlewared/plugins/failover_/event.py
+10-5src/middlewared/middlewared/plugins/iscsi_/alua.py
+5-1src/middlewared/middlewared/plugins/dlm.py
+6-0src/middlewared/middlewared/utils/iscsi/constants.py
+2-0src/middlewared/middlewared/api/v26_0_0/iscsi_global.py
+55-126 files

FreeNAS/freenas 9305526src/middlewared/middlewared/utils interface.py

NAS-140381 / 26.0.0-BETA.2 / Use netlink API for default interface detection with IPv6 fallback (by sonicaj) (#18534)

This commit fixes Apps/Docker setup failing on IPv6 single-stack
deployments with "Unable to determine interface" error. The existing
get_default_interface() only read /proc/net/route (IPv4). This replaces
the procfs text parsing with the truenas_pynetif netlink API
(get_default_route), which tries IPv4 first and falls back to IPv6. Dead
constants RTF_GATEWAY and RTF_UP are removed.

Thank you @xionglingfeng for highlighting this issue and your
contribution.

Original PR: https://github.com/truenas/middleware/pull/18528

Co-authored-by: Waqar Ahmed <waqarahmedjoyia at live.com>
DeltaFile
+8-8src/middlewared/middlewared/utils/interface.py
+8-81 files