Revert "[SelectionDAG] Propagate demanded bits through casts" (#236883)
Reverts llvm/llvm-project#235829
SimplifyMultipleUseDemandedBits is not allowed to create nodes (apart
from bitcasts and zero constants) - just bypass them
This needs to be re-implemented in SimplifyDemandedBits instead
Test requires-clauses in defaulted postfix operators
Cover constrained copy constructors and destructors that delete the
operator, requires-expressions that check a defaulted postfix operator's
usability, exception specification and return type, and a postfix
operator constrained on its own prefix operator. Also check constrained
operators in the AST dump, their mangled names in codegen, their
round-trip through a PCH, and their use in C++20 and later as an
extension.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
Leave the defaulted postfix operator temporary unnamed
The synthesized 'tmp' variable is only ever referenced directly, so it
does not need a name. Build its reference with BuildDeclRefExpr instead
of a name-based lookup.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
CodeGen: Handle uses in unreachable blocks in LiveIntervals
Previously LiveIntervals had the unenforced assumption that the
function does not contain any unreachable blocks. A register which had
a definition somewhere but also a use in an unreachable block would
hit a "Use not jointly dominated by defs" assertion.
Avoiding no-unreachable-blocks as a hard requirement avoids assertions
in some pass configuration edge cases. In particular when the
MachinePipeliner is enabled in an optimized pipeline there could still
be unreachable blocks in an optnone function which would hit the
assert. Not handling unreachable blocks was also a large problem for
llvm-reduce's MIR support and was one of the main obstacles to landing
a basic block reduction.
Give a value live into an unreachable block a phi-def at the start of
the block. A block is treated as unreachable if it has no predecessors
and is not the entry, or if the search for reaching defs finds no def
without reaching the entry, which covers unreachable cycles.
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[M68k] Remove untested M68kISD::SETCC_CARRY. (#236854)
This operation was copied from X86 where it becomes a SBB to produce an
all 1s or all 0s value from the Carry flag.
On M68k, this was expanded to SUBX which only reads the X flag rather
than the Carry flag. One of the ways we created it was by using the
flags from a CMP, but CMP doesn't update the X flag.
This node carried a condition code that pointed at the Carry flag.
On X86, this was done to share some code between X86ISD::SETCC and
X86ISD::SETCC_CARRY. This doesn't make sense for M68k since SUBX uses
the X flag.
There are no tests for this operation so let's remove it until someone
can implement a proper version for M68k's differences.
[SandboxVec][LoadStoreVec] Fix unaligned (#236191)
This patch adds the missing legality check for unsupported unaligned
accesses by the target to the LoadStorVec's legality checks.
system: TunableField: collect current values correctly; closes #11109
"gather" was never meant for runtime value access in 2022. When the
field was added in 2025 it seemed to overlook the fact that we need
to fetch the current values which are not accessible through MVC.
devel/libreadline-java: Remove expired port
2026-10-28 devel/libreadline-java: 20 years old, does not build with jdk11+, not actively maintained, no users in the tree, forked(?) to https://github.com/aclemons/java-readline
[SandboxVec][LoadStoreVec] Reject bundles that cannot be scheduled
canVectorizeLSV() created a CantSchedule result when the scheduler
failed, but did not return it, so such bundles were still reported as
Widen. For a load chain like
%ld0 = load i32, ptr %p0
store i32 %ld0, ptr %p1
%ld1 = load i32, ptr %p1
the vector load was placed after %ld1 and the store was rewritten to
use a lane extracted from it, producing a use before its definition.
Return the CantSchedule result.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[mlir][vector][NFC] Merge the unit-dim helpers in LowerVectorTransfer (#235849)
`extendVectorRank` added outer unit dims and `extendMaskRank` inner
ones, so the names did not say what differed. Replace both with
`insertUnitDims`, which takes the positions of the unit dims. The vector
and the mask get the same positions as before.
Split out of #229852, which then only changes the mask's positions.
Part of #227821.
Assisted-by: Claude
[M68k] Use UADDO_CARRY/USUBO_CARRY instead of ADDC/ADDE/SUBC/SUBE. (#235569)
Type legalization now expands wide add/sub using UADDO/USUBO and
UADDO_CARRY/USUBO_CARRY, which are lowered to M68kISD::ADD/SUB and
M68kISD::ADDX/SUBX with the carry passed through the X flag of CCR.
ADDX/SUBX no longer receive a glue operand, so their verifyTargetNode
waivers can be removed.
This improves the code for i64 uadd/usub.with.overflow. Previously the
overflow bit was computed by redoing the subtraction, and usubo also
saved and restored CCR.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Reject bundles that cannot be scheduled
canVectorizeLSV() created a CantSchedule result when the scheduler
failed, but did not return it, so such bundles were still reported as
Widen. For a load chain like
%ld0 = load i32, ptr %p0
store i32 %ld0, ptr %p1
%ld1 = load i32, ptr %p1
the vector load was placed after %ld1 and the store was rewritten to
use a lane extracted from it, producing a use before its definition.
Return the CantSchedule result.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
devel/freebsd-git-arc: Depend on devel/phorgeit-arcanist-lib
Now that reviews.freebsd.org runs Phorge, depend on Phorge's fork of the
Arcanist library (devel/phorgeit-arcanist-lib) instead of
devel/arcanist-lib.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D60978
[TargetParser][Clang] Parse Intel GPU architecture names (#229247)
Add support for Intel GPU names in --offload-arch.
#222072 added the mapping from a detected GPU version to its name. This
PR adds the reverse mapping, needed when a user names a GPU through
--offload-arch. Previously, clang recognized only the hardcoded name
bmg_g21.
The shared Intel GPU list now recognizes device names such as
xe-bmg-g21, compatibility names such as xe-dg2, aliases for products on
the same GPU IP such as xe-arl-u, and numeric names such as xe_20.1.0.
The driver keeps each name as given, so it reaches ocloc unchanged.
bmg_g21 is replaced by xe-bmg-g21.
Building one device job per IGCA target follows once IGCA targets are an
OffloadArch (#227468). Selecting the SPIR-V target from an Intel GPU
name and diagnosing unknown names follow in #229248 and #229249.
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[SPARC] Fix the f128 one and ueq compares without hard quad (#234315)
_Q_cmp returns 0 for equal, 1 for less, 2 for greater, and 3 for
unordered. Masking with 3 does not do anything. fcmp one should return
true when ordered and not equal, so add 1 and mask with 2.
```
1 001 equal - false
2 010 less - true
3 011 greater - true
4 100 unordered - false
```
fcmp ueq is the complement.
Found when building glibc.
Assisted-by: Claude
[MemProf] Include callsite/alloc index in duplicate clone hash (#236790)
The ThinLTO backend computes a hash of each function clone's callsite
clone numbers and allocation hints, in order to detect clones that are
duplicates of an earlier clone (or the original function), which are
then emitted as aliases instead of separate copies. However, the hash
only included the non-default values, not which callsite or allocation
they were for. Therefore, for example, a clone whose callsites call
callee clones [1, 0] had the same hash as one with [0, 1], and was
incorrectly emitted as an alias of the latter, causing its callers to
call the wrong callee clones.
Include the index of each callsite or allocation, along with a tag
distinguishing the two kinds, in the hash.
Assisted-by: Gemini
[X86] Remove dead code from LowerADDSUBO_CARRY. Improve variable names. NFC (#236830)
The illegal type checks are unreachable as this code is only called
after type legalization.
Move a getValue(1) call earlier and give it its own variable name.
This matches the review feedback I received when copying the current
code structure to M68k in #235569.
