[MLIR][Python] Fix generic class signature of ir.Value (#182447)
In the type stub, `Generic` isn’t explicitly imported. This causes
Pyright/Pylance to report an error and treat `Value` as not being a
generic type. Explicitly using `typing.Generic` fixes this.
[AArch64][llvm] Tighten SYSP; don't disassemble invalid encodings
Tighten SYSP aliases, so that invalid encodings are disassembled
to `<unknown>`. This is because:
```
Cn is a 4-bit unsigned immediate, in the range 8 to 9
Cm is a 4-bit unsigned immediate, in the range 0 to 7
op1 is a 3-bit unsigned immediate, in the range 0 to 6
op2 is a 3-bit unsigned immediate, in the range 0 to 7
```
Ensure we check this when disassembling, and also constrain
tablegen for compile-time errors of invalid encodings.
Also adjust the testcases in `armv9-sysp-diagnostics.s` and
`llvm/test/MC/AArch64/armv9a-sysp.s` as they were invalid,
and added a few invalid (outside of range) SYSP-alikes to
test that `<unknown>` is printed
[Hexagon] Fix SplitVectors crash in HVX type legalization (#181377)
When LegalizeHvxResize splits a multi-step TL_EXTEND (e.g., v128i32 from
v128i8, which is i8->i32), SplitVectorOp halves both input and output
types. This creates operand types that are half the HVX vector width
(e.g., v64i8 = 512 bits on 128-byte HVX), which are not legal HVX types.
These sub-HVX intermediate types confuse the DAG type legalizer's map
tracking, causing "Unprocessed value in a map! SplitVectors" assertions
with EXPENSIVE_CHECKS or
-enable-legalize-types-checking.
Fix by first expanding multi-step TL_EXTEND/TL_TRUNCATE operations into
a chain of single-step operations via ExpandHvxResizeIntoSteps before
splitting. Each single-step operation (e.g., i16->i32) can be safely
split because halving its operand type produces a legal HVX type (e.g.,
v64i16 = HVX single vector).
(cherry picked from commit 4d3217d68914ddac47d760b215d71441b820720e)
[RISCV] Correct the LMUL operand for __riscv_sf_vc_i_se_u8mf4 and __riscv_sf_vc_i_se_u8mf2 intrinsics. (#182345)
mf2 is should 7 (-1 in 3 bits). mf4 should be 6 (-2 in 3 bits).
(cherry picked from commit d93ad10a2e9fb07132771cc5c9f356d4439c8950)
[PowerPC] Only set QualName symbol on first section switch (#179253)
We were setting it every time when switching to the section. This caused
problems when the debug_aranges emission performed a switch at the end
of the section, resulting in symbols incorrectly pointing to the end
instead of the start of the function.
(cherry picked from commit 90c632ab48748808e95d9bb8cd4f3028888dc1b0)
[Flang-RT][unittests] Fix buffer over-read (#182176)
The unittests `Reductions.InfSums` defines a test array descriptor with
shape 2x3 (i.e. 6 elements), but only provides values for 2 elements.
The result is access of likely uninitialized memory when accessing the
additional 4 elements. In most cases the additional values get gobbled
up by the infinity, but if it happens to be NaN or the negated infinity,
the result becomes NaN and fails the test.
Fix by reducing the shabe of the test array to 2. Fixes the flakyness of
the test of the flang-x86_64-windows buildbot.
zfs: add zfs_range_lock_try
i plan to use this to fix pgdaemon deadlock issue. (PR/60004)
(thus i didn't bother to implement RL_READER.)
note: recent openzfs has a similar function. (zfs_rangelock_tryenter)
this commit ought to be reverted when/if we switch to it.
https://gnats.netbsd.org/cgi-bin/query-pr-single.pl?number=60004
[AMDGPU] Update f16 builtin definitions to use _Float16 instead of __fp16 (#182331)
Change the type signature of 16-bit-insts half-precision builtins from
`__fp16` to `_Float16` in the tablegen builtin definitions.
apei_hest: fix a zero-sized kmem_zalloc issue
zero-sized kmem_zalloc is illigal.
this fixes a crash seen on HP Z4 G4.
when installing netbsd 10.1 on the machine, i had to
work this around by "userconf disable apei" and
```
userconf=disable apei*
```
in boot.cfg.
"acpidump -dt" on the machine said:
```
Error Source Count=0
```
under the "HEST:" section.
[13 lines not shown]
pchtemp: add a simple driver for intel pch thermal sensor
tested on PCI_PRODUCT_INTEL_2HS_THERM, which was found on HP Z4 G4.
although other variants look compatible, i have not actually tested them.
(no hardware)
dmesg:
```
[ 512.596379] pchtemp0 at pci0 dev 20 function 2: Intel PCH Temperature Sensor
```
envstat:
```
[pchtemp0]
pchtemp0 temperature: 41.500 degC
```
enable in kernel configs where amdtemp is enabled.
the man page is mostly copy-and-paste from amdtemp.4.
[mlir][Linalg][Tensor] Preserve attrs on `tensor.pad` when lowering to dst-style (#182064)
When canonicalizing to generic ops within `EliminateEmptyTensors`, we
should take care to preserve the attributes. For example, this attribute
mechanism is employed within IREE's SPIRV pipeline to pass on tiling
configurations together with the ops.
---------
Signed-off-by: Artem Gindinson <gindinson at roofline.ai>
databases/sqlcipher: Update to 4.13.0
Note that the binary and library renamed to sqlite3. CONFLICTS is set.
PR: 292688
Approved by: jharris at widomaker.com (maintainer)
