FreeBSD/ports 484ba2fdns/nsd Makefile distinfo

dns/nsd: Security update 4.15.0 => 4.15.1

Release Notes:
https://community.nlnetlabs.nl/t/nsd-4-15-1-security-release/3447

PR:             297994
Reported by:    Jaap Akkerhuis <jaap at NLnetLabs.nl> (maintainer)
Approved by:    osa, vvd (Mentors, implicit)
MFH:            2026Q3

(cherry picked from commit db5630c479ff232307716ab2b4dda131fa721b2e)
DeltaFile
+3-3dns/nsd/distinfo
+1-1dns/nsd/Makefile
+4-42 files

FreeBSD/ports 90a89d8security/vuxml/vuln 2026.xml

security/vuxml: Document dns/nsd vulnerabilities

PR:             297994
Reported by:    Jaap Akkerhuis <jaap at NLnetLabs.nl> (maintainer)
Approved by:    osa, vvd (Mentors, implicit)
DeltaFile
+37-0security/vuxml/vuln/2026.xml
+37-01 files

LLVM/project 2b042d9llvm/test/CodeGen/AMDGPU wave32.ll llvm.amdgcn.icmp.w32.ll, llvm/test/Transforms/InstCombine/AMDGPU amdgcn-intrinsics.ll

[AMDGPU] Remove icmp and fcmp intrinsics (#208183)

Remove these intrinsics in favour of llvm.amdgcn.ballot:
  llvm.amdgcn.icmp
  llvm.amdgcn.fcmp
DeltaFile
+0-2,905llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
+0-2,456llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
+0-2,074llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
+0-1,719llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
+26-754llvm/test/CodeGen/AMDGPU/wave32.ll
+0-756llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+26-10,66427 files not shown
+87-12,01533 files

FreeBSD/ports db5630cdns/nsd Makefile distinfo

dns/nsd: Security update 4.15.0 => 4.15.1

Release Notes:
https://community.nlnetlabs.nl/t/nsd-4-15-1-security-release/3447

PR:             297994
Reported by:    Jaap Akkerhuis <jaap at NLnetLabs.nl> (maintainer)
Approved by:    osa, vvd (Mentors, implicit)
MFH:            2026Q3
DeltaFile
+3-3dns/nsd/distinfo
+1-1dns/nsd/Makefile
+4-42 files

LLVM/project 047535cllvm/lib/CodeGen CodeGenPrepare.cpp, llvm/test/CodeGen/BPF/CORE offset-reloc-fieldinfo-2.ll offset-reloc-fieldinfo-2-bpfeb.ll

[CodeGenPrepare] Use make_early_inc_range to avoid iterator invalidation. (#215347)

While iterating users of a {s|z}ext's source operand in optimizeExtUses
we explicitly replace the use with a trunc instruction thereby
invalidating iterator of the loop. Update the loop to use
make_early_inc_range to avoid invalidation.
DeltaFile
+5-2llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll
+5-2llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2-bpfeb.ll
+1-1llvm/lib/CodeGen/CodeGenPrepare.cpp
+11-53 files

OPNSense/core 30d01b4src/etc rc.freebsd

rc: stop_result not used anymore
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+0-1src/etc/rc.freebsd
+0-11 files

LLVM/project dfec0b3lldb/source/Expression DWARFExpression.cpp, lldb/unittests/Expression DWARFExpressionTest.cpp

[lldb] Handle implicit values followed by full-width piece operations (#219160)

`DW_OP_implicit_value` stores its bytes in a `Value` whose internal type
is `HostAddress`. The `DW_OP_piece` and `DW_OP_bit_piece` evaluators
therefore mistook the backing-buffer address for a memory location and
rejected valid full-width pieces.

Use the saved implicit location-description kind to recognize this
storage representation. Full-width byte pieces and zero-offset
full-width bit pieces now preserve the backing bytes, while genuine host
addresses and partial pieces retain their existing behavior.

Add a unit test for both expressions from the issue.

Fixes #203224
DeltaFile
+22-1lldb/source/Expression/DWARFExpression.cpp
+11-0lldb/unittests/Expression/DWARFExpressionTest.cpp
+33-12 files

LLVM/project decfe59llvm/include/llvm/IR Intrinsics.h Intrinsics.td, llvm/test/TableGen intrinsic-rangeset-errors.td intrinsic-rangeset.td

[IR][TableGen] Add RangeSet TableGen intrinsic property (#203623)

This change introduces a `RangeSet` TableGen intrinsic property.
Existing `Range<idx, lo, hi>` keeps its current half-open semantics and
continues to emit the existing range attribute.

TableGen syntax: `RangeSet<idx, [[lo0, hi0], [lo1, hi1], ...]>` where
`[lo, hi]` are closed ordered and non-overlapped intervals.
DeltaFile
+132-0llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+63-0llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
+47-0llvm/test/TableGen/intrinsic-rangeset.td
+45-0llvm/test/TableGen/intrinsic-rangeset-errors.td
+19-0llvm/include/llvm/IR/Intrinsics.td
+12-6llvm/include/llvm/IR/Intrinsics.h
+318-63 files not shown
+339-69 files

LLVM/project 33605fdllvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Update comment for check BE formula in howManyLT (NFC) (#219170)

Update outdate comments around the code for picking the check BE
formula. It includes the following updates:

* define End = max(RHS,Start), as used later, use instead of incorrect
max(End,Start)
* precondition for the code use check min(RHS,Start) > Start - Stride
* update remaining test to be consistent
* Stride = umax(1, Stride) instead of umin, which matches the code
above; umin would not avoid divide by 0.


Preparation for https://github.com/llvm/llvm-project/pull/218694

PR: https://github.com/llvm/llvm-project/pull/219170
DeltaFile
+18-20llvm/lib/Analysis/ScalarEvolution.cpp
+18-201 files

LLVM/project 179c7dcllvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp

AMDGPU: Pass MachineRegisterInfo to getImmOrMaterializedImm (#219422)

The only used the operand to reach the MachineRegisterInfo. Pass it
directly so it no longer depends on MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+8-8llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+3-3llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+2-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+2-1llvm/lib/Target/AMDGPU/SIInstrInfo.h
+15-144 files

LLVM/project 2dad524lldb/source/Target Process.cpp, lldb/unittests/Target MemoryTest.cpp

[lldb] Reject an unusable memory-cache-line-size (#219217)

`target.process.memory-cache-line-size` is an unbounded `UInt64`, so
`settings set` accepts 0, and `MemoryCache` keeps the value in a
`uint32_t`, so it also accepts any multiple of 2^32, which truncates to
0.  Every consumer then takes a remainder by 0.

`Process::ReadCStringFromMemory` divides on the first iteration of its
loop, before it touches inferior memory, so any address reproduces it.
On an x86_64 host that is a `SIGFPE` and lldb dies; on AArch64 `udiv` by
zero yields 0, so `addr % 0` evaluates to `addr` and the subtraction
underflows to a huge chunk size, and the bug hides.

```
$ lldb -b \
    -o 'settings set target.process.memory-cache-line-size 0' \
    -o 'target create --core linux-x86_64.core'
Floating point exception: 8
```

    [36 lines not shown]
DeltaFile
+39-0lldb/unittests/Target/MemoryTest.cpp
+8-0lldb/source/Target/Process.cpp
+47-02 files

FreeBSD/ports a23cb63graphics/nvidia-drm-66-kmod distinfo, graphics/nvidia-drm-latest-kmod distinfo

x11/nvidia-driver, x11/nvidia-kmod, x11/linux-nvidia-libs, graphics/nvidia-drm*-kmod, x11/nvidia-settings, x11/nvidia-xconfig: Update to 595.99.02

Update to latest Production Branch of drivers 595.99.02:
https://www.nvidia.com/en-us/drivers/details/278287/

Linux counterparts for x11/linux-nvidia-libs:
https://www.nvidia.com/en-us/drivers/details/278285/

PR:             298013
Differential Revision:  https://reviews.freebsd.org/D59248
DeltaFile
+3-3x11/nvidia-xconfig/distinfo
+3-3x11/nvidia-settings/distinfo
+3-3x11/nvidia-driver/distinfo
+3-3x11/linux-nvidia-libs/distinfo
+3-3graphics/nvidia-drm-latest-kmod/distinfo
+3-3graphics/nvidia-drm-66-kmod/distinfo
+18-186 files not shown
+30-3012 files

OpenBSD/src buXzONlusr.bin/mandoc mandocdb.c

   Use unveil(2) to restrict write access to mandoc.db(5) and /tmp/
   and read access to the selected manpath directory or directories,
   but leave global read access open in -t mode.
   Tweaks from and looks correct to deraadt@.
VersionDeltaFile
1.224+65-15usr.bin/mandoc/mandocdb.c
+65-151 files

LLVM/project 0ab4db4llvm/lib/Target/AMDGPU AMDGPUUniformIntrinsicCombine.cpp, llvm/test/CodeGen/AMDGPU redundant-ballot-reads.ll

Revert "[AMDGPU] Combine redundant ballot intrinsic calls (#218357)" (#218962)

This reverts commit 2be211bb2ab35461520530f37e3faf382dc644d5.
DeltaFile
+0-448llvm/test/CodeGen/AMDGPU/redundant-ballot-reads.ll
+5-170llvm/lib/Target/AMDGPU/AMDGPUUniformIntrinsicCombine.cpp
+5-6182 files

OpenBSD/ports MmN5T2fx11/gnome/papers Makefile

   Lowercase COMMENT.
VersionDeltaFile
1.9+3-1x11/gnome/papers/Makefile
+3-11 files

NetBSD/pkgsrc eCBpymydoc CHANGES-2026

   Updated www/py-starlette, www/py-jwcrypto
VersionDeltaFile
1.5620+3-1doc/CHANGES-2026
+3-11 files

FreeBSD/ports 743416cmisc/fq Makefile distinfo, misc/fq/files modules.txt

misc/fq: update the port to version 0.18.0

Now it comes with the official manual page!

Notified by:    upstream (the author), portscout
DeltaFile
+21-21misc/fq/distinfo
+15-12misc/fq/Makefile
+10-11misc/fq/files/modules.txt
+46-443 files

LLVM/project 770ea2ellvm/lib/Target/RISCV RISCVInstrInfo.h RISCVVLOptimizer.cpp

RISCV: Pass MachineRegisterInfo to isVLKnownLE (#219402)

isVLKnownLE and its getEffectiveImm helper used the VL operands to reach
the MachineRegisterInfo. Pass it directly so they no longer depend on
MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+8-8llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+8-8llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+7-7llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+2-1llvm/lib/Target/RISCV/RISCVInstrInfo.h
+25-244 files

NetBSD/pkgsrc 28ApdLVwww/py-jwcrypto PLIST distinfo

   py-jwcrypto: updated to 1.5.9

   1.5.9

   Add ML-DSA post-quantum signature support (RFC 9964)
   Support fully specified algorithms per RFC 9864
   Skip unknown kty in JWKSet import per RFC 7517 §5
   Reject non-empty encrypted key in bare ECDH-ES
   Limit dot splits during JWE and JWS parsing
VersionDeltaFile
1.15+4-5www/py-jwcrypto/Makefile
1.11+4-4www/py-jwcrypto/distinfo
1.5+4-1www/py-jwcrypto/PLIST
+12-103 files

NetBSD/pkgsrc WDtjEYXwww/py-starlette PLIST distinfo

   py-starlette: updated to 1.6.0

   1.6.0 (August 8, 2026)

   Added

   * Add `max_body_size` to `Starlette` and route classes
   * Expose `http.response.debug` information via response extensions
VersionDeltaFile
1.18+8-7www/py-starlette/Makefile
1.17+4-4www/py-starlette/distinfo
1.3+4-1www/py-starlette/PLIST
+16-123 files

OPNSense/core 3fc11b2src/etc/inc system.inc

system: normalize output if gateways aren't provided. Closes https://github.com/opnsense/core/issues/10800
DeltaFile
+1-1src/etc/inc/system.inc
+1-11 files

OPNSense/core 689b926src/etc/inc interfaces.inc

interfaces: batch VIP post-reload for proxyarp/pfsync #10810
DeltaFile
+10-7src/etc/inc/interfaces.inc
+10-71 files

NetBSD/pkgsrc s5Sm3lzdoc CHANGES-2026

   doc: Updated net/pptp to 1.7.1nb2
VersionDeltaFile
1.5619+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc UATN6Ffnet/pptp distinfo Makefile, net/pptp/patches patch-ah

   pptp: honor CFLAGS and LDFLAGS

   Bump PKGREVISION.
VersionDeltaFile
1.4+17-6net/pptp/patches/patch-ah
1.13+2-2net/pptp/distinfo
1.24+2-2net/pptp/Makefile
+21-103 files

OpenBSD/ports mG7doC9multimedia/libcamera Makefile

   Tweak comment, no pkg change.
VersionDeltaFile
1.5+1-1multimedia/libcamera/Makefile
+1-11 files

OPNSense/core a410dc4src/opnsense/www/js opnsense_bootgrid.js

ui: Fix _showMaximized() height calculation when mobile navigation triggers below 768px width
DeltaFile
+3-1src/opnsense/www/js/opnsense_bootgrid.js
+3-11 files

LLVM/project f12785ellvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp

AMDGPU: Pass MachineRegisterInfo to getImmOrMaterializedImm

The only used the operand to reach the MachineRegisterInfo. Pass it
directly so it no longer depends on MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+8-8llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+3-3llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+2-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+2-1llvm/lib/Target/AMDGPU/SIInstrInfo.h
+15-144 files

OPNSense/core 3e4cc0fsrc/etc/inc interfaces.inc

interfaces: revert passing $all_devices for now

This is so that the next patch can be backported cleanly.
DeltaFile
+4-5src/etc/inc/interfaces.inc
+4-51 files

LLVM/project dc3696bllvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/CodeGen MachineVerifier.cpp

CodeGen: Pass instruction and operand index to isPCRelRegisterOperandLegal

Replace the MachineOperand argument to the
TargetInstrInfo::isPCRelRegisterOperandLegal hook with the containing
instruction and operand index. The M68k implementation only used the operand
to recover its parent instruction and operand number, so this drops the
dependence on MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+8-10llvm/lib/Target/M68k/M68kInstrInfo.cpp
+5-3llvm/include/llvm/CodeGen/TargetInstrInfo.h
+2-1llvm/lib/Target/M68k/M68kInstrInfo.h
+1-1llvm/lib/CodeGen/MachineVerifier.cpp
+16-154 files

NetBSD/pkgsrc bfhhZVbmeta-pkgs/bulk-test-go Makefile

   bulk-test-go: Update Terraform/OpenTofu dependencies

   Build all Terraform and OpenTofu versions and adjust DEPENDS for
   providers that have now version suffixes in PKGNAME and PKGPATH.

   Noticed via pkgsrc-bulk@ and thanks to <jperkin>!
VersionDeltaFile
1.17+16-7meta-pkgs/bulk-test-go/Makefile
+16-71 files