[Polly] Detect preconditions of cached user assumption translations (#226204)
`addUserAssumptions` detected preconditions of a user assumption by
checking whether building its condition recorded new assumptions, but
`SCEVAffinator` caches translated expressions, so a precondition shared
with an earlier assumption (e.g. the same truncation) was missed and the
assumption went into the context, removing the runtime check it relied
on. For example, with `__builtin_assume((signed char)n >= 0)` and
`__builtin_assume((signed char)n < 10)`, the `n >= 128` check was
dropped, although `n = 261` satisfies both assumptions. Instead, check
the invalid domain of each assumption, which is also cached, and if it
is non-empty, add the assumption to the defined behavior context as in
#189350.
Assisted-by: Claude (Anthropic)
NAS-141376 / 27.0.0-BETA.1 / Require a matching password secret seed to upload a configuration (#19823)
## Context
Support asked that we stop accepting a configuration that arrives
without its password secret seed. Such a restore cannot decrypt anything
it contains, so middleware generates a fresh (wrong) seed and wipes
everything that then fails validation — UPS and email credentials,
directory services config, cloud and keychain credentials, VM and
container device attributes, SMB user flags. That partial restore is
never what anyone actually wants.
## Solution
- **Export the seed by default.** `secretseed` defaults to true in the
current API version only; older versions keep the default they shipped
with. An archive is the only way to carry two files, so the default
`config.save` now returns one rather than a bare database.
- **Refuse an upload that cannot decrypt its own database.** The seed
has to be present, `stg_pwenc_check` has to be readable, and the seed
has to decrypt it, all before anything on this system is replaced. There
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[mlir] Avoid rewriting unreachable blocks in the greedy driver
A rewrite can disconnect a block after the iteration's initial CFG sweep.
Track reachability through rewriter notifications and skip worklist
operations in unreachable blocks until the next iteration removes them.
Cache reachability per region. Compare the final successors of changed
blocks after each rewrite, preserving the cache for successor-equivalent
changes and block merges that keep surviving blocks reachable. Recompute for
other CFG changes. This avoids repeated full CFG scans during branch
canonicalization.
Single-block regions return before cache lookup or CFG traversal. Before the
cache bookkeeping simplification, in the same Release build, canonicalizing
32,000 sibling single-block regions took 22.8 ms versus 21.9 ms with the
parent driver. With 16,000 regions containing folds, the times were 35.7 ms
and 34.3 ms, respectively. Nesting to 256 levels showed no measurable
difference.
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[mlir] Avoid rewriting unreachable blocks in the greedy driver
A rewrite can disconnect a block after the iteration's initial CFG sweep.
Track reachability through rewriter notifications and skip worklist
operations in unreachable blocks until the next iteration removes them.
Cache reachability per region. Compare the final successors of changed
blocks after each rewrite, preserving the cache for successor-equivalent
changes and block merges that keep surviving blocks reachable. Recompute for
other CFG changes. This avoids repeated full CFG scans during branch
canonicalization.
Single-block regions return before cache lookup or CFG traversal. Before the
cache bookkeeping simplification, in the same Release build, canonicalizing
32,000 sibling single-block regions took 22.8 ms versus 21.9 ms with the
parent driver. With 16,000 regions containing folds, the times were 35.7 ms
and 34.3 ms, respectively. Nesting to 256 levels showed no measurable
difference.
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[mlir][vector] Support fixed-size masks in `eliminateVectorMasks` (#221595)
`eliminateVectorMasks` returned immediately unless a `VscaleRange` was
supplied. The TODO above that early return argued the fixed-size case
was unlikely to be useful, because "for fixed-size code dimensions are
all static so masks tend to fold away".
That is only true when the mask operand is constant. When it comes from
an induction variable, which is what tiling produces, the operand is not
constant and no fold removes the mask, even though value-bounds analysis
can prove it all-true. For example, `-canonicalize` leaves this alone:
```mlir
scf.for %i = %c0 to %c1024 step %c4 {
%rem = arith.subi %c1024, %i : index
%mask = vector.create_mask %rem : vector<4xi1>
%v = vector.transfer_read %t[%i], %f0, %mask : tensor<1024xf32>, vector<4xf32>
...
}
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CodeGen: Remove TargetOptions::LoopAlignment
Delete the module-wide LoopAlignment override and llc's -align-loops
flag that fed it. Loop alignment is now expressed solely through
per-loop llvm.loop.align metadata.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
clang: Emit llvm.loop.align metadata for -falign-loops
Make -falign-loops=N attach per-loop llvm.loop.align metadata instead
of setting the module-wide TargetOptions::LoopAlignment. This reuses
the existing [[clang::code_align]] metadata path, with the source
attribute taking precedence over the flag.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
AMDGPU: Mark the SCC def dead when expanding CF pseudos (#226249)
The control flow pseudos start with dead flags on the implicit scc def,
but did not transfer to the replacement instruction
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
SystemZ: Mark unread CC defs dead at build time (#226434)
The custom inserters for the subword atomic pseudos and for probed
allocas, plus the inline stack probe emitted by frame lowering, build
instructions whose CC def is never read. Set the dead flags.
Marking the RISBG32 in the subword cmpxchg loop dead lets MachineSink
move it out of the compare block and into the store block, so it is
skipped when the comparison fails.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
ARM: Use divmod type signatures from RuntimeLibcallsInfo
Start moving towards an API to emit calls from RuntimeLibcallsInfo's
knowledge about the type signature of a function instead of manually
computing an IR type from the EVT of the operation.
Also change the swap of arguments to be based on the libcall impl,
rather than the ABI since it's logically a property of the function
itself.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
ARM: Use divmod type signatures from RuntimeLibcallsInfo
Start moving towards an API to emit calls from RuntimeLibcallsInfo's
knowledge about the type signature of a function instead of manually
computing an IR type from the EVT of the operation.
Also change the swap of arguments to be based on the libcall impl,
rather than the ABI since it's logically a property of the function
itself.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
RuntimeLibcalls: Describe register-returning divmod libcall ABIs (#217825)
Teach RuntimeLibcallsInfo::getFunctionTy about the ARM AEABI
(__aeabi_*divmod) and Windows (__rt_*div*) divmod signatures. Currently
the custom lowering to these calls hardcodes the call signature
information, but in the future this should be automatically handled.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[mlir] Avoid rewriting unreachable blocks in the greedy driver
A rewrite can disconnect a block after the iteration's initial CFG sweep.
Track reachability through rewriter notifications and skip worklist operations
in unreachable blocks until the next iteration removes them.
Cache reachability per region. Compare the final successors of changed blocks
after each rewrite, preserving the cache for successor-equivalent changes and
block merges that keep surviving blocks reachable. Recompute for other CFG
changes. This avoids repeated full CFG scans during branch canonicalization.
Single-block regions return before cache lookup or CFG traversal. In the same
Release build, canonicalizing 32,000 sibling single-block regions took 22.8 ms
versus 21.9 ms with the parent driver. With 16,000 regions containing folds,
the times were 35.7 ms and 34.3 ms, respectively. Nesting to 256 levels
showed no measurable difference.
On a synthetic CFG chain whose conditional branches have identical
successors, median CanonicalizerPass times with region simplification
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