LLVM/project deab742llvm/lib/Target/CSKY CSKYAsmPrinter.cpp

CSKY: Avoid constructing a temporary CSKYSubtarget in AsmPrinter

This was reconstructing a subtarget equivalent to the global
subtarget instead of just using the available one.
DeltaFile
+1-9llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
+1-91 files

LLVM/project b84c5f4llvm/include/llvm/Analysis BlockFrequencyInfoImpl.h

[BFI] Simplify/optimize getMass/getContainingLoop. NFC (#212938)

A block can head both a natural loop and the irreducible loop wrapping
it (`@crossloops` in BlockFrequencyInfo/irreducible.ll).

getContainingLoop and getMass unroll to a fixed depth of two through
isDoubleLoopHeader and isADoublePackage.  Depth two holds because
IrreducibleGraph::addEdge drops edges into the enclosing loop's headers,
keeping such a header out of any nested SCC.

(The old comment "If it's a node inside a packaged loop, it returns the
loop's mass." is wrong.)

Walk the Parent chain instead to drop the depth two assumption. Testing
`IsPackaged` before isHeader also skips the Nodes[0] load on the common
path.
DeltaFile
+19-25llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+19-251 files

OpenBSD/ports mGnxParx11/xfce4/xfce4-panel Makefile distinfo, x11/xfce4/xfce4-panel/pkg PLIST

   x11/xfce4/xfce4-panel: update to 4.20.8.

   see https://gitlab.xfce.org/xfce/xfce4-panel/-/raw/xfce4-panel-4.20.8/NEWS
VersionDeltaFile
1.49+2-2x11/xfce4/xfce4-panel/distinfo
1.44+4-0x11/xfce4/xfce4-panel/pkg/PLIST
1.106+1-1x11/xfce4/xfce4-panel/Makefile
+7-33 files

OpenBSD/ports BRGgUyzx11/xfce4/xfce4-settings distinfo Makefile, x11/xfce4/xfce4-settings/pkg PLIST

   x11/xfce4/xfce4-settings: update to 4.20.5.

   see https://gitlab.xfce.org/xfce/xfce4-settings/-/raw/xfce4-settings-4.20.5/NEWS
VersionDeltaFile
1.39+2-2x11/xfce4/xfce4-settings/distinfo
1.75+2-2x11/xfce4/xfce4-settings/Makefile
1.27+1-0x11/xfce4/xfce4-settings/pkg/PLIST
+5-43 files

OpenBSD/ports XUiSxaex11/xfce4/tumbler distinfo Makefile

   x11/xfce4/tumbler: update to 4.20.2.

   see https://gitlab.xfce.org/xfce/tumbler/-/raw/tumbler-4.20.2/NEWS
VersionDeltaFile
1.59+3-4x11/xfce4/tumbler/Makefile
1.25+2-2x11/xfce4/tumbler/distinfo
+5-62 files

OpenBSD/ports Ha6UrNYx11/xfce4/xfce4-power-manager distinfo Makefile, x11/xfce4/xfce4-power-manager/pkg PLIST

   x11/xfce4/xfce4-power-manager: update to 4.20.1.

   see https://gitlab.xfce.org/xfce/xfce4-power-manager/-/raw/xfce4-power-manager-4.20.1/NEWS
VersionDeltaFile
1.19+2-2x11/xfce4/xfce4-power-manager/distinfo
1.49+2-2x11/xfce4/xfce4-power-manager/Makefile
1.17+1-0x11/xfce4/xfce4-power-manager/pkg/PLIST
+5-43 files

LLVM/project 8a1ff7fllvm/lib/Target/RISCV RISCVOptWInstrs.cpp RISCVISelDAGToDAG.cpp, llvm/test/CodeGen/RISCV zilx-opt-w-instrs.mir zilx.ll

[RISCV] Support CodeGen of Zilx extension

Thanks for `XTheadMemIdx` extension that makes life easier.

Reviewers: lukel97, topperc, kito-cheng, tclin914

Reviewed By: topperc

Pull Request: https://github.com/llvm/llvm-project/pull/209420
DeltaFile
+1,880-0llvm/test/CodeGen/RISCV/zilx.ll
+182-0llvm/test/CodeGen/RISCV/zilx-opt-w-instrs.mir
+113-0llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
+29-4llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+19-11llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+14-1llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+2,237-161 files not shown
+2,239-177 files

LLVM/project b44c307llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp Triple.cpp

AMDGPU: TableGen the subarch triple name table

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+87-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+2-45llvm/lib/TargetParser/Triple.cpp
+23-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+17-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+4-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+133-655 files

LLVM/project 88554dcclang/test/Misc/target-invalid-cpu-note r600.c amdgcn.c, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

AMDGPU: Eliminate old macro driven processor name parsing

Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+162-114llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+72-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+18-18clang/test/Misc/target-invalid-cpu-note/amdgcn.c
+10-10clang/test/Misc/target-invalid-cpu-note/r600.c
+2-2llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+264-1875 files

LLVM/project 23a2224llvm/lib/Target/RISCV RISCVFeatures.td RISCVInstrInfoZilx.td, llvm/test/CodeGen/RISCV attributes.ll

[RISCV][MC] Support experimental Zilx extension

This adds the MC support for `Zilx` (Indexed Integer Load Instructions)
extension.

Doc: https://github.com/riscv/riscv-zilx

Reviewers: topperc, tclin914, kito-cheng

Pull Request: https://github.com/llvm/llvm-project/pull/209419
DeltaFile
+95-0llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
+68-0llvm/test/MC/RISCV/zilx-valid-rv64.s
+63-0llvm/test/MC/RISCV/zilx-valid-rv32.s
+40-0llvm/test/MC/RISCV/zilx-invalid.s
+7-0llvm/lib/Target/RISCV/RISCVFeatures.td
+4-0llvm/test/CodeGen/RISCV/attributes.ll
+277-07 files not shown
+287-013 files

LLVM/project b42621fllvm/lib/TargetParser AMDGPUTargetParser.cpp, llvm/utils/TableGen/Basic AMDGPUTargetDefEmitter.cpp

AMDGPU: TableGen the subarch to processor name mapping table (#212606)

Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical
GPU name) with a generated table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+23-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+61-5llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+84-482 files

LLVM/project 36f00d0llvm/test/CodeGen/AArch64 neon-dotreduce.ll, llvm/test/CodeGen/AArch64/GlobalISel split-wide-shifts-multiway.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+5,516-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmulh.ll
+4,862-0llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+2,988-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+1,045-1,527llvm/test/CodeGen/AMDGPU/frem.ll
+1,148-1,123llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
+1,023-1,030llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+16,582-3,6802,492 files not shown
+89,578-37,2752,498 files

LLVM/project 1af0f1fllvm/test/CodeGen/AArch64 neon-dotreduce.ll, llvm/test/CodeGen/AArch64/GlobalISel split-wide-shifts-multiway.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+5,516-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmulh.ll
+4,862-0llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+2,988-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+1,045-1,527llvm/test/CodeGen/AMDGPU/frem.ll
+1,148-1,123llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
+1,023-1,030llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+16,582-3,6802,492 files not shown
+89,578-37,2752,498 files

LLVM/project 6d5d631llvm/test/CodeGen/AArch64 neon-dotreduce.ll, llvm/test/CodeGen/AArch64/GlobalISel split-wide-shifts-multiway.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+5,516-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmulh.ll
+4,862-0llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+2,988-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+1,045-1,527llvm/test/CodeGen/AMDGPU/frem.ll
+1,148-1,123llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
+1,023-1,030llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+16,582-3,6802,492 files not shown
+89,578-37,2752,498 files

NetBSD/pkgsrc PxfjVh5doc CHANGES-2026

   Updated print/p5-LaTeX-Driver to 1.3.1
VersionDeltaFile
1.4830+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc UlDRNgqprint/p5-LaTeX-Driver Makefile distinfo, print/p5-LaTeX-Driver/patches patch-Makefile.PL

   Update to 1.3.1

   Upstream changes:
   1.3.1   2026-01-07
      - Fix version numbers
   1.3.0   2026-01-07
      - Fix RT #152478: program_path() exists even without executable
VersionDeltaFile
1.12+4-5print/p5-LaTeX-Driver/distinfo
1.36+3-4print/p5-LaTeX-Driver/Makefile
1.3+1-1print/p5-LaTeX-Driver/patches/patch-Makefile.PL
+8-103 files

FreeBSD/ports 8a5b308deskutils/fet Makefile distinfo

deskutils/fet: Update to 7.9.4

Changelog: https://lalescu.ro/liviu/fet/news.html
DeltaFile
+3-3deskutils/fet/distinfo
+1-1deskutils/fet/Makefile
+4-42 files

LLVM/project 4835810llvm/docs LangRef.md

Langref example
DeltaFile
+3-1llvm/docs/LangRef.md
+3-11 files

LLVM/project 9b65030llvm/lib/Target/ARM ARMISelLowering.cpp ARMTargetMachine.h, llvm/unittests/Target/ARM MachineInstrTest.cpp

ARM: Thread float ABI through ARMSubtarget (NFC)

Preparation to use the "float-abi" module flag. Store the resolved
float ABI in ARMSubtarget and fold it into the subtarget key. The
value is still sourced from TargetOptions::FloatABIType.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+12-6llvm/unittests/Target/ARM/MachineInstrTest.cpp
+9-3llvm/lib/Target/ARM/ARMTargetMachine.cpp
+11-1llvm/lib/Target/ARM/ARMSubtarget.h
+4-3llvm/lib/Target/ARM/ARMSubtarget.cpp
+0-6llvm/lib/Target/ARM/ARMTargetMachine.h
+2-3llvm/lib/Target/ARM/ARMISelLowering.cpp
+38-223 files not shown
+43-279 files

FreeBSD/ports 7c2c580net-mgmt/zabbix74-server pkg-plist.frontend Makefile

net-mgmt/zabbix74-server: Update to 7.4.13

Release notes:  https://www.zabbix.com/rn/rn7.4.13
DeltaFile
+3-3net-mgmt/zabbix74-server/distinfo
+1-1net-mgmt/zabbix74-server/Makefile
+1-0net-mgmt/zabbix74-server/pkg-plist.frontend
+5-43 files

FreeBSD/ports 4fe3133net-mgmt/zabbix6-server pkg-plist.frontend Makefile

net-mgmt/zabbix6-server: Update to 6.0.48

Release notes:  https://www.zabbix.com/rn/rn6.0.48
DeltaFile
+3-3net-mgmt/zabbix6-server/distinfo
+1-1net-mgmt/zabbix6-server/Makefile
+1-0net-mgmt/zabbix6-server/pkg-plist.frontend
+5-43 files

FreeBSD/ports f56995bnet-mgmt/zabbix7-server pkg-plist.frontend Makefile

net-mgmt/zabbix7-server: Update to 7.0.29

Release notes:  https://www.zabbix.com/rn/rn7.0.29
DeltaFile
+3-3net-mgmt/zabbix7-server/distinfo
+1-1net-mgmt/zabbix7-server/Makefile
+1-0net-mgmt/zabbix7-server/pkg-plist.frontend
+5-43 files

OpenBSD/src WjZgZiAusr.sbin/acme-client base64.c

   Handle '=' padding in base64url encoded EAB keys.

   bentley@ found one in the wild and confirmed that this makes it work
VersionDeltaFile
1.11+5-1usr.sbin/acme-client/base64.c
+5-11 files

LLVM/project 82da5a9llvm/lib/Target/AMDGPU VOP3PInstructions.td AMDGPUTargetTransformInfo.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[AMDGPU] Duplicate packed fp32 instructions

These have different semantics on gfx9 and gfx12 with respect to
scalar operands.
DeltaFile
+21-9llvm/lib/Target/AMDGPU/SIInstructions.td
+9-9llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+7-7llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+9-4llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+6-6llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
+5-5llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+57-409 files not shown
+89-5415 files

LLVM/project a50d01cllvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp Triple.cpp

AMDGPU: TableGen the subarch triple name table

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+87-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+2-45llvm/lib/TargetParser/Triple.cpp
+23-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+17-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+4-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+133-655 files

LLVM/project 015dcd4clang/test/Misc/target-invalid-cpu-note r600.c amdgcn.c, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

AMDGPU: Eliminate old macro driven processor name parsing

Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+162-114llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+72-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+18-18clang/test/Misc/target-invalid-cpu-note/amdgcn.c
+10-10clang/test/Misc/target-invalid-cpu-note/r600.c
+2-2llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+264-1875 files

LLVM/project ace49dcllvm/lib/TargetParser AMDGPUTargetParser.cpp, llvm/utils/TableGen/Basic AMDGPUTargetDefEmitter.cpp

AMDGPU: TableGen the subarch to processor name mapping table

Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical GPU
name) with a generated table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+23-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+61-5llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+84-482 files

LLVM/project 99e473allvm/docs LangRef.md, llvm/include/llvm/Support CodeGen.h

IR: Introduce "float-abi" module flag

This is intended to eliminate the FloatABIType TargetOptions field.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+33-8llvm/include/llvm/Support/CodeGen.h
+37-0llvm/test/Verifier/module-flags-float-abi.ll
+31-0llvm/docs/LangRef.md
+16-12llvm/lib/IR/AutoUpgrade.cpp
+28-0llvm/test/Linker/module-flags-float-abi.ll
+16-0llvm/test/Bitcode/upgrade-ppc-float-abi.ll
+161-204 files not shown
+199-2010 files

LLVM/project 76116e1llvm/lib/Target/ARM ARMSubtarget.cpp

Fix regression after removal of suffixed cmpeq calls
DeltaFile
+9-0llvm/lib/Target/ARM/ARMSubtarget.cpp
+9-01 files

LLVM/project 26d08c2llvm/lib/Target/RISCV RISCVRegisterInfo.td, llvm/test/MC/RISCV rv64zfh-invalid.s rv32d-invalid.s

[RISCV][MC] Improve FPR Error Messages (#212492)

This patch improves the error messages for the following register classes:
    
   1. FPR RegClasses (FPR16, FPR32, FPR64, FPR128, FPR256)
   2. Compressed FPR RegClasses (FPR16C, FPR32C, FPR64C)
   3. GPR-as-FPR classes used by Zfinx/Zdinx extensions (GPRAsFPR16, GPRAsFPR32, GPRF64AsFPR, GPRPairAsFPR).

---------

Co-authored-by: Saloni Shinde <saloshin at qti.qualcomm.com>
DeltaFile
+33-8llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+7-5llvm/test/MC/RISCV/rv32zfh-invalid.s
+9-3llvm/test/MC/RISCV/rv64d-invalid.s
+6-3llvm/test/MC/RISCV/rv32d-invalid.s
+7-2llvm/test/MC/RISCV/rv64f-invalid.s
+6-2llvm/test/MC/RISCV/rv64zfh-invalid.s
+68-2319 files not shown
+108-5925 files