HardenedBSD/ports c8fe873games/fs2open/files af833f059cc0cfc925792e019f6c2b754c6d53c1.patch, games/vcmi pkg-plist

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+497-317textproc/bookokrat/distinfo
+248-158textproc/bookokrat/Makefile.crates
+79-73graphics/resvg-capi/distinfo
+39-37graphics/resvg-capi/Makefile
+55-14games/vcmi/pkg-plist
+0-66games/fs2open/files/af833f059cc0cfc925792e019f6c2b754c6d53c1.patch
+918-66563 files not shown
+1,312-1,00669 files

LLVM/project f2441cbflang/include/flang/Lower OpenMP.h, flang/lib/Lower/OpenMP OpenMP.cpp

[flang][mlir] Add flang to mlir lowering for groupprivate
DeltaFile
+135-1flang/lib/Lower/OpenMP/OpenMP.cpp
+57-0flang/test/Lower/OpenMP/groupprivate.f90
+0-9flang/test/Lower/OpenMP/Todo/groupprivate.f90
+1-0flang/include/flang/Lower/OpenMP.h
+193-104 files

LLVM/project 54cdd90llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 select-zext-analysis.ll

[SLP]Skip operands comparing on non-matching (but compatible) instructions

If the instructions are compatible but non-matching (zext-select pair as
example), no need to perform operands analysis, just return that they
are matching.
DeltaFile
+42-0llvm/test/Transforms/SLPVectorizer/AArch64/select-zext-analysis.ll
+2-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+44-02 files

LLVM/project 9928f73lldb/test/API/riscv/conflicting-extensions-disassembly TestConflictingExtensions.py Makefile, lldb/test/API/riscv/disassembler TestDisassembler.py

update tests
DeltaFile
+8-32lldb/test/API/riscv/disassembler/TestDisassembler.py
+32-0lldb/test/API/riscv/conflicting-extensions-disassembly/TestConflictingExtensions.py
+17-0lldb/test/API/riscv/conflicting-extensions-disassembly/Makefile
+8-0lldb/test/API/riscv/conflicting-extensions-disassembly/main.c
+6-0lldb/test/API/riscv/conflicting-extensions-disassembly/file_with_zcd.c
+6-0lldb/test/API/riscv/conflicting-extensions-disassembly/file_with_zcmp.c
+77-321 files not shown
+82-327 files

FreeNAS/freenas 3cdaad7src/middlewared/middlewared/plugins auth.py

Fix SCRAM authentication bugs

1. Fix typo: auth_ctx.client_next_mech -> auth_ctx.next_mech
   The AuthenticationContext dataclass only has next_mech, not
   client_next_mech. This would cause AttributeError at runtime.

2. Set auth_ctx.auth_data when processing CLIENT_FIRST_MESSAGE
   Without this, abandoning a SCRAM exchange causes TypeError
   when check_auth_mechanism tries to access auth_data['user'].

https://claude.ai/code/session_01KgpPaDH8XqdXhrGjCS5vJ4
DeltaFile
+2-1src/middlewared/middlewared/plugins/auth.py
+2-11 files

LLVM/project 81e0de2mlir/lib/Dialect/Arith/Transforms ExpandOps.cpp, mlir/test/Dialect/Arith expand-ops.mlir

[MLIR][Arith] FastMath extf conversion without NaN checks (#180926)

This PR allows the expand op converter to consider the NoNaN fastmath
attribute to disable the runtime checks for NaNs in E8M0 types. Default
behaviour is still the same.

The OCP document provides all-ones as NaN for E8M0, but for pre-MX I8
quantization, the checks for NaNs are prohibitively expensive,
especially if the hardware doesn't have native support for that type.
DeltaFile
+20-5mlir/test/Dialect/Arith/expand-ops.mlir
+15-8mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
+35-132 files

LLVM/project 924f773clang/lib/Sema SemaExpr.cpp, clang/test/SemaCXX overload-resolution-deferred-templates.cpp

[Clang] Don't diagnose missing members when looking at the instantiating class template (#180725)

The perfect matching patch revealed another bug where recursive
instantiations could lead to the escape of SFINAE errors, as shown in
the issue.

Fixes https://github.com/llvm/llvm-project/issues/179118
DeltaFile
+81-0clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
+1-1clang/lib/Sema/SemaExpr.cpp
+82-12 files

OPNSense/core 29a74a2src/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Remove console log
DeltaFile
+0-1src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+0-11 files

OPNSense/core 6239603src/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

The hash was consumed too early now, fix it by shifting to the new spot where the variable is used last
DeltaFile
+2-1src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+2-11 files

LLVM/project 972aa59mlir/lib/Bindings/Python IRCore.cpp, mlir/python/mlir/dialects ext.py

[MLIR][Python] Make traits declarative in python-defined operations (#180748)

This will support two syntax in python-defined dialects.

First is that traits can now be declared in class parameters, e.g.
```python
class ParentIsIfTrait(DynamicOpTrait): #define a python-side trait
    @staticmethod
    def verify_invariants(op) -> bool:
        if not isinstance(op.parent.opview, IfOp):
            op.location.emit_error(
                f"{op.name} should be put inside {IfOp.OPERATION_NAME}"
            )
            return False
        return True

class YieldOp( # attach two traits: IsTerminatorTrait, ParentIsIfTrait
    TestRegion.Operation, name="yield", traits=[IsTerminatorTrait, ParentIsIfTrait]
):

    [39 lines not shown]
DeltaFile
+47-17mlir/test/python/dialects/ext.py
+22-1mlir/python/mlir/dialects/ext.py
+6-5mlir/lib/Bindings/Python/IRCore.cpp
+75-233 files

HardenedBSD/ports 2e64065audio/subtui distinfo Makefile

audio/subtui: Update to 2.2.3

Changelog: https://github.com/MattiaPun/SubTUI/releases/tag/v2.2.3
DeltaFile
+5-5audio/subtui/distinfo
+1-1audio/subtui/Makefile
+6-62 files

FreeBSD/ports 2e64065audio/subtui distinfo Makefile

audio/subtui: Update to 2.2.3

Changelog: https://github.com/MattiaPun/SubTUI/releases/tag/v2.2.3
DeltaFile
+5-5audio/subtui/distinfo
+1-1audio/subtui/Makefile
+6-62 files

LLVM/project e3bf84allvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64-cvt-simd-fptoi.ll arm64-cvtf-simd-itofp.ll

[AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe

For FEAT_FPRCVT instructions, allow them to run in streaming mode if safe
DeltaFile
+34-92llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+10-20llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
+2-2llvm/lib/Target/AArch64/AArch64InstrInfo.td
+3-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+49-1144 files

LLVM/project fa0b427llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64-cvt-simd-fptoi.ll arm64-cvtf-simd-itofp.ll

fixup!

Adjust code
DeltaFile
+46-178llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+10-40llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
+2-2llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+59-2214 files

LLVM/project 756ed8cllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64-cvt-simd-fptoi.ll

[AArch64][llvm] Improve codegen for FP_TO_*_SAT

Skip the SVE scalar-combine for saturating FP->INT when the scalar op
is legal, so we use simpler scalar codegen in streaming modes.
DeltaFile
+120-1,585llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+9-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+129-1,5852 files

OPNSense/core dc5be80src/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Only get the hash once, use it everywhere, re-add missing null fallback and initialized interface variable
DeltaFile
+4-6src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+4-61 files

OPNSense/core ed748aesrc/opnsense/mvc/app/controllers/OPNsense/Base ApiMutableModelControllerBase.php

mvc: catch empty data in CSV import

Catch empty lines.  A single "," will generate
an empty string instead of NULL so we are good
here.  It's safe to assume we have at least one
property in the line, otherwise the data is
useless to us anyway.

From the fgetcsv() manual:

A blank line in a CSV file will be returned as an array
comprising a single null field, and will not be treated
as an error.

See: https://www.php.net/manual/en/function.fgetcsv.php
DeltaFile
+1-1src/opnsense/mvc/app/controllers/OPNsense/Base/ApiMutableModelControllerBase.php
+1-11 files

LLVM/project 0c51020clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded vabs_v.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded vabs_v.c

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+400-0llvm/test/CodeGen/RISCV/rvv/vabs.ll
+238-0llvm/test/CodeGen/RISCV/rvv/vabd.ll
+238-0llvm/test/CodeGen/RISCV/rvv/vabdu.ll
+229-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs_v.c
+229-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs_v.c
+229-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs_v.c
+1,563-022 files not shown
+4,296-028 files

LLVM/project 9a07b1cllvm/utils/gn/secondary/lldb/source/Plugins/Process/Linux BUILD.gn, llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core BUILD.gn

[gn build] Port 5e5b799853af
DeltaFile
+2-2llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn
+1-1llvm/utils/gn/secondary/lldb/source/Plugins/Process/Linux/BUILD.gn
+3-32 files

LLVM/project 5e5b799lldb/source/Plugins/Process/FreeBSD NativeRegisterContextFreeBSD_x86.cpp NativeRegisterContextFreeBSD_x86_64.cpp, lldb/source/Plugins/Process/Linux NativeRegisterContextLinux_x86.cpp NativeRegisterContextLinux_x86_64.cpp

[lldb][NativeRegisterContext] Rename to x86 for shared files (#180624)

DeltaFile
+1,089-0lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.cpp
+0-1,089lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
+660-0lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.cpp
+0-660lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86_64.cpp
+0-648lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp
+648-0lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.cpp
+2,397-2,39720 files not shown
+3,161-3,16126 files

LLVM/project 3123d9cmlir/include/mlir/Dialect/Tosa/IR TosaShapeOps.td, mlir/test/Dialect/Tosa tosa-validation-version-1p1-valid.mlir

[mlir][tosa] Fix validation of `dim` op when reliant on datatype extension (#180915)

For example:
```
error: 'tosa.dim' op illegal: requires [bf16, shape] but not included in the profile compliance [shape]

    %0 = tosa.dim %arg0 {axis = 4 : i32} : (tensor<4x5x8x8x6x4xbf16>) -> !tosa.shape<1>
```
Here dim requires support to be declared for the BF16 and SHAPE
extensions, but only SHAPE was specified in the op declaration.
DeltaFile
+10-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+5-0mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
+15-02 files

LLVM/project d6b9930llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64-cvt-simd-fptoi.ll arm64-cvtf-simd-itofp.ll

[AArch64][llvm] Preserve FP_TO_*_SAT VT operand in SVE scalar-combine

Updated RUN lines and generated new `CHECK‑SME`/`CHECK‑SVE` lines in:

    llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
    llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll

by adding `-force-streaming` and `-force-streaming-compatible` runs,
as pre-commit tests for a future change to enable FPRCVT streaming.

This triggers a SVE scalar-combine path which requires a code update.
FP_TO_*_SAT nodes require operand 1 (the saturation VT) to be present.
Without it the node is malformed and hits the SelectionDAG assertion
“Invalid child # of SDNode!”.

Also, skip the SVE combine if the scalar/custom op is already legal.
DeltaFile
+3,017-0llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+282-0llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
+7-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+3,306-13 files

FreeBSD/ports 42e8dfd. MOVED, sysutils Makefile

sysutils/android-file-transfer-qt5: Remove qt5 port

- since qt5 is being deprecated in favor qt6, remove port
- qt6 option is available in sysutils/android-file-transfer

MFH:            2026Q1
(cherry picked from commit ff00ed2179f69bfad6d014d5db9575b64f044b7c)
DeltaFile
+0-9sysutils/android-file-transfer-qt5/Makefile
+1-0MOVED
+0-1sysutils/Makefile
+1-103 files

LLVM/project 2dcf858llvm/test/Transforms/LoopVectorize/RISCV tail-folding-bin-unary-ops-args.ll tail-folding-call-intrinsics.ll, llvm/test/Transforms/LoopVectorize/X86 masked_load_store.ll fminimumnum.ll

[LAA] Use SCEVPtrToAddr in tryToCreateDiffChecks. (#178861)

The checks created by LAA only compute a pointer difference and do not
need to capture provenance. Use SCEVPtrToAddr instead of SCEVPtrToInt
for computations.

To avoid regressions while parts of SCEV are migrated to use PtrToAddr
this adds logic to rewrite all PtrToInt to PtrToAddr if possible in the
created expressions. This is needed to avoid regressions.

Similarly, if in the original IR we have a PtrToInt, SCEVExpander tries
to re-use it if possible when expanding PtrToAddr.

Depends on https://github.com/llvm/llvm-project/pull/178727.

Fixes https://github.com/llvm/llvm-project/issues/156978.

PR: https://github.com/llvm/llvm-project/pull/178861
DeltaFile
+72-72llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
+46-46llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-call-intrinsics.ll
+36-36llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
+27-27llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
+20-20llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cast-intrinsics.ll
+18-18llvm/test/Transforms/LoopVectorize/X86/fminimumnum.ll
+219-21939 files not shown
+428-39645 files

OpenBSD/ports zWZU2tPsecurity/oath-toolkit distinfo Makefile, security/oath-toolkit/patches patch-pskctool_tests_tst_sign_sh patch-liboath_gl_fseeko_c

   update to oath-toolkit-2.6.14
VersionDeltaFile
1.2+3-3security/oath-toolkit/patches/patch-pskctool_tests_tst_sign_sh
1.15+2-2security/oath-toolkit/distinfo
1.30+1-1security/oath-toolkit/Makefile
1.3+0-0security/oath-toolkit/patches/patch-liboath_gl_fseeko_c
+6-64 files

OpenBSD/ports zOGc3Lqproductivity/khard Makefile distinfo, productivity/khard/patches patch-doc_source_conf_py

   update to khard-0.20.1
VersionDeltaFile
1.21+29-35productivity/khard/Makefile
1.4+10-8productivity/khard/patches/patch-doc_source_conf_py
1.12+7-3productivity/khard/pkg/PLIST
1.7+2-2productivity/khard/distinfo
+48-484 files

LLVM/project 0646941libcxx/test/benchmarks GenerateInput.h, libcxx/test/benchmarks/algorithms pop_heap.bench.cpp

[libc++] Rewrite the std::pop_heap benchmark (#179911)

Testing a bunch of random types has relatively little value. This
reduces the number of benchmarks so we can run them on a regular basis.
This saves ~90 seconds when running the benchmarks.
DeltaFile
+59-0libcxx/test/benchmarks/algorithms/sorting/pop_heap.bench.cpp
+0-38libcxx/test/benchmarks/algorithms/pop_heap.bench.cpp
+15-0libcxx/test/benchmarks/GenerateInput.h
+74-383 files

LLVM/project 1d719edlibclc/clc/include/clc/math math.h, libclc/clc/lib/clspv SOURCES

[libclc] Bring back fma for clspv (#180693)

This is a partial revert of #179428
DeltaFile
+274-0libclc/clc/lib/clspv/math/clc_sw_fma.cl
+16-0libclc/opencl/lib/clspv/math/fma.cl
+11-0libclc/clc/include/clc/math/math.h
+1-0libclc/clc/lib/clspv/SOURCES
+1-0libclc/opencl/lib/clspv/SOURCES
+303-05 files

HardenedBSD/ports cf03fa0games/fs2open/files af833f059cc0cfc925792e019f6c2b754c6d53c1.patch patch-cmake_toolchain-clang.cmake

games/fs2open: update to 25.0.0
DeltaFile
+0-66games/fs2open/files/af833f059cc0cfc925792e019f6c2b754c6d53c1.patch
+20-11games/fs2open/files/patch-cmake_toolchain-clang.cmake
+0-20games/fs2open/files/patch-code_graphics_opengl_gropenglopenxr.cpp
+0-18games/fs2open/files/patch-code_graphics_openxr__internal.h
+0-18games/fs2open/files/patch-code_CMakeLists.txt
+0-18games/fs2open/files/patch-code_graphics_openxr.cpp
+20-1513 files not shown
+25-1719 files

FreeBSD/ports cf03fa0games/fs2open/files af833f059cc0cfc925792e019f6c2b754c6d53c1.patch patch-cmake_toolchain-clang.cmake

games/fs2open: update to 25.0.0
DeltaFile
+0-66games/fs2open/files/af833f059cc0cfc925792e019f6c2b754c6d53c1.patch
+20-11games/fs2open/files/patch-cmake_toolchain-clang.cmake
+0-20games/fs2open/files/patch-code_graphics_opengl_gropenglopenxr.cpp
+0-18games/fs2open/files/patch-code_graphics_openxr__internal.h
+0-18games/fs2open/files/patch-code_CMakeLists.txt
+0-18games/fs2open/files/patch-code_graphics_openxr.cpp
+20-1513 files not shown
+25-1719 files