[LoopFusion] Document LoopFusion Pass (#192926)
The LoopFusion pass, currently disabled by default, lacks documentation. This patch is the first attempt to document the flow and current limitations.
Assisted by : Claude Opus 4.6
[LiveDebugValues] Avoid SmallSet for dead registers (#195841)
transferRegisterDef builds a list of dead registers and removes open ranges for
debug locations that use those registers. This list used a SmallSet, so each
insert also does uniquing in the hot per-instruction path. This showed up under
SmallSet<Register, 32>::insertImpl on profiles of sqlite on aarch64-O0-g.
Using a SmallVector instead and uniquing in collectIDsForRegs improves
compile-time.
CTMark geomean:
- stage1-O0-g: -0.35%
- stage1-aarch64-O0-g: -0.72%
- stage2-O0-g: -0.27%
https://llvm-compile-time-tracker.com/compare.php?from=c9d713aa48a714d20b8502d06b9feb24829e6f22&to=6c0d4aafb9e325259c88577d148ac13c643ea993&stat=instructions%3Au
Assisted-by: codex
[RegAlloc] consider urgent evict in evictInterference (#192631)
This assertion causes a crash in programs with high register pressure
when inline assembly is used.
```
assert((ExtraInfo->getCascade(Intf->reg()) < Cascade ||
VirtReg.isSpillable() < Intf->isSpillable()) &&
"Cannot decrease cascade number, illegal eviction");
```
It should account for the case where an urgent eviction may result in
cascade being less than `ExtraInfo->getCascade(Intf->reg())`
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
[CIR][NFC] Upstream mem2reg.cir from incubator (#194517)
Upstream `mem2reg.cir` from incubator.
Check that stack slots are promoted away after CFG flattening.
Partially addresses #156747.
makefs(8): improve fs-options documentation
Ensure all fs-options are documented, in alphabetical order.
Describe whether the option has a value (e.g., foo=str or foo=num),
and for numeric values describe the supported range.
Some markup consistency.
Remove my email from the man page.
18045 nvmeadm could list physical locations
Reviewed by: Andy Fiddaman <illumos at fiddaman.net>
Reviewed by: Dan Cross <cross at oxidecomputer.com>
Approved by: Gordon Ross <gordon.w.ross at gmail.com>
[RISCV] Rename and invert UseGPRForF16_F32/UseGPRForF16_F32. (#195971)
Rename to AllowFPR. We used to set these flags when we ran out of FPRs,
but we haven't for a while. I think rephrasing as allow FPR is a bit
clearer.
Size is the number of wide characters, not the number of bytes.
The correct amount of memory was allocated but the stored size did
not match the allocation due to being multiplied by sizeof(wchar_t).
Spotted by Frank Denis using the Swival Security Scanner
OK deraadt@
[RFC][Docs] Clarify brace omission for single-line bodies
Update the Coding Standards brace guidance to emphasize that braces should be
omitted only for simple bodies that do not wrap across multiple physical lines.
[SPIRV] Dummy implementation of the `returnaddress` and `frameaddress` intrinsics (#195976)
The SPIR-V specification doesn't define any operations for the
return and frame address. The valid implementation in this case is to
produce a null pointer.
Assisted-by: Claude Opus 4.6 <noreply at anthropic.com>
[SPIRV] Add support for SPV_KHR_abort extension (#193037)
This commit adds support for the SPV_KHR_abort extension in the SPIRV
backend. The extension allows shaders to abort execution with a custom
message.
Assisted-by: Claude Opus 4.7 <noreply at anthropic.com>
---------
Co-authored-by: Marcos Maronas <mmaronas at amd.com>
