LLVM/project 8a8c0cdmlir/lib/Dialect/MemRef/Transforms FoldMemRefAliasOps.cpp, mlir/test/Dialect/MemRef fold-memref-alias-ops.mlir

[mlir][MemRef] Make fold-memref-alias-ops use memref interfaces

This replaces the large switch-cases and operation-specific patterns
in FoldMemRefAliashops with patterns that use the new
IndexedAccessOpInterface and IndexedMemCopyOpInterface, which will
allow us to remove the memref transforms' dependency on the NVGPU
dialect.

This does also resolve some bugs and potential unsoundnesses:
1. We will no longer fold in expand_shape into vector.load or
vector.transfer_read in cases where that would alter the strides
between dimensions in multi-dimensional loads. For example, if we have
a `vector.load %e[%i, %j, %k] : memref<8x8x9xf32>, vector<2x3xf32>`
where %e is
`expand_shape %m [[0], [1], [2. 3]] : memref<8x8x3x3xf32> to 8x8x9xf32,
we will no longer fold in that shape, since that would change which
value would be read (the previous patterns tried to account for this
but failed).
2. Subviews that have non-unit strides in positions that aren't being

    [15 lines not shown]
DeltaFile
+425-440mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
+294-3mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
+719-4432 files

FreeBSD/src fe9e4ebsys/net pfvar.h, sys/netpfil/pf pf.c

pf: fix use of uninitialised variable

In pf_match_rule() we attempt to append matching rules to the end of
'match_rules'. We want to preserve the order to make the multiple
pflog entries easier to understand. So we keep track of the last added
rule item in 'rt'. However, that assumed that 'match_rules' was only
ever added to in that one call to pf_match_rules(). This isn't always
the case, for example if we have match rules in different anchors.
In that case we'd end up using the uninitialised 'rt' variable in the
SLIST_INSERT_AFTER call.

Instead track the match rules and the last matching rule (to enable
easy appending) in the struct pf_test_ctx.
This also allows us to reduce the number of arguments for some
functions, because we passed a ctx to most functions that needed
'match_rules'.

While here also make pf_match_rules() static, because it's only ever
used in pf.c

    [5 lines not shown]
DeltaFile
+58-0tests/sys/netpfil/pf/match.sh
+19-22sys/netpfil/pf/pf.c
+3-4sys/net/pfvar.h
+80-263 files

FreeBSD/src 895e1c6sys/kern kern_sysctl.c

sysctl(9): Booleans: Fix old value length discovery

When calling sysctl(3) with a null 'oldp', i.e., length discovery mode,
'oldix' can be equal to 'oldlen', and we should not fail.

More generally, let SYSCTL_OUT() and SYSCTL_IN() handle corner cases,
simply removing the comparisons between 'oldidx' and 'oldlen' and
'newidx' and 'newlen' done by hand as the test just after is an equality
that does not require to know if 'idx' is smaller than 'len'.

PR:             292917
Reported by:    cy
Fixes:          406da392ef8d ("sysctl(9): Booleans: Accept integers to ease knob conversion")
Sponsored by:   The FreeBSD Foundation
DeltaFile
+0-4sys/kern/kern_sysctl.c
+0-41 files

LLVM/project f665cf3llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+9-72 files

LLVM/project 4cae644libc/config/baremetal config.json

[libc] Disable strong stack protector for baremetal (#179559)

Strong stack protector introduces references to __stack_chk_guard
symbols with GOT relocation in ARM 32 bit targets which is not supported
in typical baremetal environments. Turning this off for baremetal.
DeltaFile
+5-0libc/config/baremetal/config.json
+5-01 files

NetBSD/pkgsrc-wip cecf2davalgrind-netbsd-git TODO Makefile

valgrind-netbsd-git: update to today's snapshot

fails later
DeltaFile
+10-6valgrind-netbsd-git/TODO
+3-3valgrind-netbsd-git/Makefile
+3-3valgrind-netbsd-git/distinfo
+16-123 files

LLVM/project efee25dllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+9-72 files

LLVM/project 65cc695llvm/include/llvm/CodeGen SelectionDAGISel.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGISel.cpp

Reapply "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/MorphNodeTo into their own table. (#178722)"

This includes a fix to use size_t instead of uint64_t in one place.
DeltaFile
+57-6llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+17-8llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+6-2llvm/test/TableGen/CPtrWildcard.td
+7-0llvm/test/TableGen/RegClassByHwMode.td
+3-3llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+1-1llvm/include/llvm/CodeGen/SelectionDAGISel.h
+91-206 files

LLVM/project 4f04770llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv sext.mir zext.mir, llvm/test/CodeGen/RISCV/rvv vl-opt-op-info.mir vl-opt.mir

[RISCV] Print MIR comments for AVL and VEC_RM operands (#179542)

Such that we can now have something like:
```
PseudoVFMACC_VV_M2_E64 %1, %28, %28, 7 /* frm=dyn */, %21 /* vl */, 6 /* e64 */, 0 /* tu, mu */
```
or
```
PseudoVFMACC_VV_M2_E64 %1, %28, %28, 7 /* frm=dyn */, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */
```
Hopefully this could make reading RISC-V MIR (a little) less painful.
DeltaFile
+414-414llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+115-115llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+60-60llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
+56-56llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
+56-56llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir
+56-56llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir
+757-75750 files not shown
+1,232-1,21856 files

LLVM/project b0b9046llvm/lib/Target/BPF BTFDebug.cpp BPFISelLowering.cpp

[BPF] Replace copy-assign by move-assign in llvm/lib/Target/BPF/ (#179462)

An SDLoc transitively contains a TrackingMDRef which have a specialized
move constructor. It's more efficient to move element to it instead of
copying them.

FileContent contains std::vector<...> values. It's more efficient to
move then to copy the whole vector.
DeltaFile
+1-1llvm/lib/Target/BPF/BTFDebug.cpp
+1-1llvm/lib/Target/BPF/BPFISelLowering.cpp
+2-22 files

FreeBSD/ports be1cb6asecurity/hockeypuck distinfo Makefile.modules

security/hockeypuck: update to 2.3.1

Approved by:            lwhsu (mentor, implicitly)
Signed-off-by:          Siva Mahadevan <siva at FreeBSD.org>
Sponsored by:           The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D54906
DeltaFile
+3-99security/hockeypuck/distinfo
+0-49security/hockeypuck/Makefile.modules
+1-3security/hockeypuck/Makefile
+4-1513 files

FreeBSD/ports c4faf46lang/python312 Makefile, lang/python313 Makefile

lang/python3{12,13}: limit parallel .pyc compilation to MAKE_JOBS

This option is available since python312[0]. This fixes
python312 and python313 builds with qemu-user-static
emulating riscv64.

[0] https://github.com/python/cpython/commit/9a7e9f9921804f3f90151ca42703e612697dd430

Approved by:            vishwin (#python), lwhsu (mentor)
Signed-off-by:          Siva Mahadevan <siva at FreeBSD.org>
Sponsored by:           The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D54906
DeltaFile
+2-1lang/python312/Makefile
+2-1lang/python313/Makefile
+4-22 files

FreeBSD/ports 919a4damultimedia/pipewire pkg-plist distinfo

multimedia/pipewire: update to 1.4.10

Approved by:            arrowd (maintainer), lwhsu (mentor)
Signed-off-by:          Siva Mahadevan <siva at FreeBSD.org>
Sponsored by:           The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D54906
DeltaFile
+5-4multimedia/pipewire/pkg-plist
+3-3multimedia/pipewire/distinfo
+1-1multimedia/pipewire/Makefile
+9-83 files

LLVM/project d0ee00bllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+9-72 files

LLVM/project 254b3b1mlir/lib/TableGen AttrOrTypeDef.cpp, mlir/test/IR test-verifiers-type.mlir

[mlir][tblgen] Add PredTypeTrait/PredAttrTrait support (#169153)

This patch adds support for `PredTypeTrait` and `PredAttrTrait` in type
and attribute definitions, enabling declarative predicate-based
verification similar to how `PredOpTrait` works for operations.

  ## Motivation

In 802bf02 (from 2021), `PredTypeTrait`/`PredAttrTrait` were defined in
TableGen but not implemented in the code generator. Using them causes
mlir-tblgen to crash with an assertion failure when trying to cast
`PredTrait` to `InterfaceTrait`. This patch fixes the crash and
implements the actual verification code generation.

  ## Usage

Use `$paramName` syntax in predicates to reference type/attribute
parameters:


    [15 lines not shown]
DeltaFile
+48-0mlir/test/IR/test-verifiers-type.mlir
+30-6mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
+30-0mlir/test/lib/Dialect/Test/TestTypeDefs.td
+5-3mlir/lib/TableGen/AttrOrTypeDef.cpp
+113-94 files

LLVM/project 43faefdllvm/lib/Transforms/IPO ArgumentPromotion.cpp, llvm/test/Transforms/ArgumentPromotion dbg.ll

[ArgPromotion] Add DW_CC_nocall to DISubprogram (#178973)

ArgumentPromotion pass may change function signatures. If this happens
and debuginfo is enabled, adding DW_CC_nocall allows dwarf to generate
    DW_AT_calling_convention        (DW_CC_nocall)
for DW_TAG_subprogram.
DeadArgumentElimination ([1]) already has similar implementation.

The pahole tool ([2]) is used in linux kernel build to generate vmlinux
BTF. One of its input is linux kernel dwarf. Currently, pahole
checks *all* DW_TAG_subprogram functions and find whether the source
signature matches the architecture ABI or not. If mismatch, pahole will
try to do some adjustment for those parameters. See [3]
and function parameter__new().

The linux kernel typically has ~65K functions and roughly 1100 functions
may have signature changed due to compile optimization. Without
DW_CC_nocall,
signatures of all of 64K functions will be checked in parameter__new().

    [34 lines not shown]
DeltaFile
+16-1llvm/test/Transforms/ArgumentPromotion/dbg.ll
+11-0llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
+27-12 files

FreeBSD/ports eba3ec5www/forgejo distinfo Makefile

www/forgejo: Update to 14.0.2

Changelog:
* https://codeberg.org/forgejo/forgejo/src/branch/forgejo/release-notes-published/14.0.2.md

MFH:            2026Q1
(cherry picked from commit 4358aecad4f3bf669a00f5428edd18ebb831cae2)
DeltaFile
+3-3www/forgejo/distinfo
+1-1www/forgejo/Makefile
+4-42 files

FreeBSD/ports 4358aecwww/forgejo distinfo Makefile

www/forgejo: Update to 14.0.2

Changelog:
* https://codeberg.org/forgejo/forgejo/src/branch/forgejo/release-notes-published/14.0.2.md

MFH:            2026Q1
DeltaFile
+3-3www/forgejo/distinfo
+1-1www/forgejo/Makefile
+4-42 files

LLVM/project d835071mlir/lib/Conversion/GPUToROCDL LowerGpuOpsToROCDLOps.cpp, mlir/test/Conversion/GPUToROCDL gpu-to-rocdl-subgroup-id.mlir

[mlir] GPUToROCDL: lower `gpu.subgroup_id` to the intrinsic where possible (#179422)

Lower `gpu.subgroup_id` to `wave.id` intrinsic on gfx12+, lower to
`linearized_thread_id / subgroup_size` on older.
DeltaFile
+63-2mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+40-0mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-subgroup-id.mlir
+103-22 files

LLVM/project f9b5ab1lldb/include/lldb/DataFormatters FormatterBytecode.h

[lldb] Add missing include guard in FormatterBytecode.h (#179528)

DeltaFile
+5-0lldb/include/lldb/DataFormatters/FormatterBytecode.h
+5-01 files

LLVM/project f646131llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+9-72 files

LLVM/project 7c29a09utils/bazel/llvm-project-overlay/lldb BUILD.bazel

[bazel][lldb] Port #179355: data formatters location (#179552)

DeltaFile
+1-2utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
+1-21 files

LLVM/project 19cf75cllvm/include/llvm/CodeGen SelectionDAGISel.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGISel.cpp

Revert "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/MorphNodeTo into their own table. (#178722)"

This reverts commit caab98284166784459a2fb76df7bca3f1d35e41e.

This is failing some build bots.
DeltaFile
+6-57llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+7-16llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+2-6llvm/test/TableGen/CPtrWildcard.td
+0-7llvm/test/TableGen/RegClassByHwMode.td
+3-3llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+1-1llvm/include/llvm/CodeGen/SelectionDAGISel.h
+19-906 files

LLVM/project 3ce60c4utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel][mlir][NFC] Run buildifier (#179554)

DeltaFile
+0-3utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+0-31 files

NetBSD/src bMIhgFusys/dev/isa if_ate.c if_fmv_isa.c, usr.sbin/makefs/cd9660 cd9660_write.c

   fix few typos in comments.
VersionDeltaFile
1.52+3-3sys/dev/isa/if_ate.c
1.14+3-3sys/dev/isa/if_fmv_isa.c
1.19+3-3usr.sbin/makefs/cd9660/cd9660_write.c
+9-93 files

LLVM/project 2dfd20dllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+9-72 files

LLVM/project a6c926bclang/lib/Analysis ThreadSafety.cpp, clang/test/SemaCXX warn-thread-safety-analysis.cpp

[Thread Safety Analysis] Fix a bug of context saving in alias-analysis (#178825)

The commit b4c98fcbe1504841203e610c351a3227f36c92a4 introduces
alias-analysis and conservatively invalidates variable definitions at
function calls. For each invalidated argument, it creates and pushes a
context. So if there are multiple arguments being invalidated, there are
more than one context being pushed. However, the analysis expects one
context at the program point of a call, causing context mismatch. This
issue could lead to false negatives.
For example,
```
    MyLock->Lock();               // 'MyLock' holds the lock
    Lock_t *Ptr = MyLock;      // 'Ptr' aliases with 'MyLock'
    // Before the fix, two contexts are saved and pushed at the call below, causing context mismatch later.
    escapeAliasMultiple(&Irrelevant, &Ptr);  
    Ptr->Unlock();                   // 'Ptr' may no longer hold the lock but the analyzer missed it due to context mismatch
```
This commit fixes the issue.


    [2 lines not shown]
DeltaFile
+10-0clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+4-3clang/lib/Analysis/ThreadSafety.cpp
+14-32 files

LLVM/project 4b4c32cllvm/utils/gn/secondary/compiler-rt/lib/builtins sources.gni

[gn] port e1f69ee8e847
DeltaFile
+3-0llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni
+3-01 files

LLVM/project 72d86a5llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+9-72 files

LLVM/project 6716acdllvm/test/TableGen TargetLibraryInfo.td, llvm/utils/TableGen/Basic TargetLibraryInfoEmitter.cpp

[NFC][TableGen] Adopt IfDefEmitter in TargetLibraryInfoEmitter (#179388)

DeltaFile
+29-34llvm/utils/TableGen/Basic/TargetLibraryInfoEmitter.cpp
+7-7llvm/test/TableGen/TargetLibraryInfo.td
+36-412 files