LLVM/project b8c6a39llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/AArch64 fp-maximumnum-minimumnum.ll

Merge branch 'main' into users/s-perron/dim_attribute
DeltaFile
+1,561-2,812llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+2,071-1,930llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
+3,114-0llvm/test/CodeGen/X86/andnot-sink-not.ll
+969-2,001llvm/test/CodeGen/X86/bit-manip-i512.ll
+538-1,357llvm/test/CodeGen/X86/shift-i512.ll
+348-707llvm/lib/Target/X86/X86ISelLowering.cpp
+8,601-8,8071,660 files not shown
+58,436-31,1201,666 files

FreeNAS/freenas 71da530src/middlewared/middlewared/plugins/pool_ pool.py, src/middlewared/middlewared/plugins/zfs_ pool.py

more over-engineering
DeltaFile
+6-2src/middlewared/middlewared/plugins/pool_/pool.py
+0-1src/middlewared/middlewared/plugins/zfs_/pool.py
+6-32 files

LLVM/project 6b059a0flang/include/flang/Optimizer/HLFIR Passes.td, flang/lib/Optimizer/HLFIR/Transforms SimplifyHLFIRIntrinsics.cpp

[flang] Inline max/minval according to -ffp-maxmin-behavior. (#185148)

This patch takes into account the option setting when inlining
max/minval intrinsics. It is not an NFC change for Flang, because:
  * Inlining for integer types now uses arith.max/minsi operations.
  * We do not mark the reduction loops as `unordered`
    under `reassoc` FMF. I think this was not quite correct.

Otherwise, the default Legacy setting should produce the same
MLIR as before.
DeltaFile
+557-0flang/test/HLFIR/simplify-hlfir-intrinsics-maxmin.fir
+161-35flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
+16-7flang/test/HLFIR/simplify-hlfir-intrinsics-maxval.fir
+16-7flang/test/HLFIR/simplify-hlfir-intrinsics-minval.fir
+16-1flang/include/flang/Optimizer/HLFIR/Passes.td
+6-4flang/lib/Optimizer/Passes/Pipelines.cpp
+772-541 files not shown
+773-547 files

FreeBSD/ports 3ad4a58net-mgmt/icingaweb2-module-grafana Makefile distinfo

net-mgmt/icingaweb2-module-grafana: Update 3.1.2 => 3.1.3

Changelog:
https://github.com/NETWAYS/icingaweb2-module-grafana/releases/tag/v3.1.3

Replace RM in do-install with EXTRACT_AFTER_ARGS.
Remove unnecessary MKDIR in do-install.

PR:     293689
DeltaFile
+4-3net-mgmt/icingaweb2-module-grafana/Makefile
+3-3net-mgmt/icingaweb2-module-grafana/distinfo
+7-62 files

FreeBSD/ports d6b1c6amisc/claude-code Makefile

misc/claude-code: Add USES=certs:fetch

... since some users report that this is required, ex. in bug#293676
DeltaFile
+2-2misc/claude-code/Makefile
+2-21 files

FreeBSD/ports 0a452bfmisc/grok-cli Makefile

misc/grok-cli: Add USES=certs:fetch

... since some users report that this is required, ex. in bug#293676
DeltaFile
+2-2misc/grok-cli/Makefile
+2-21 files

FreeBSD/ports d43f1damisc/github-copilot-language-server Makefile

misc/github-copilot-language-server: Add USES=certs:fetch

... since some users report that this is required, ex. in bug#293676
DeltaFile
+5-5misc/github-copilot-language-server/Makefile
+5-51 files

FreeBSD/ports 0455004misc/nanocoder Makefile

misc/nanocoder: Add USES=certs:fetch

... since some users report that this is required, ex. in bug#293676
DeltaFile
+2-2misc/nanocoder/Makefile
+2-21 files

FreeBSD/ports 1fed521misc/github-copilot-cli Makefile

misc/github-copilot-cli: Add USES=certs:fetch

... since some users report that this is required, ex. in bug#293676
DeltaFile
+6-6misc/github-copilot-cli/Makefile
+6-61 files

FreeBSD/ports b5694e0www/py-yt-dlp-ejs Makefile

www/py-yt-dlp-ejs: Add USES=certs:fetch

npm requires this for some users/systems and not for others.
It's not clear what the differentiating factor is.
See details in the bug report.

PR:             268638
Reported by:    James TD Smith
DeltaFile
+2-2www/py-yt-dlp-ejs/Makefile
+2-21 files

FreeBSD/ports 60817c5Mk/Uses certs.mk

Mk/Uses: Add certs.mk to handle dependency on security/ca_root_nss

... as USES=certs:{phase} instead of reciting the whole dependency.

Around one hundred ports depend on security/ca_root_nss.
DeltaFile
+54-0Mk/Uses/certs.mk
+54-01 files

FreeBSD/ports bccac39Tools/scripts npmjs-fetch-with-dependencies.sh

Tools/scripts: Use CA certificates in Tools/scripts/npmjs-fetch-with-dependencies.sh
DeltaFile
+9-1Tools/scripts/npmjs-fetch-with-dependencies.sh
+9-11 files

FreeBSD/ports f999339textproc/ctpp2 Makefile

textproc/ctpp2: update MASTER_SITES and WWW

The project website is from time to time unreachable
and the source archive is not accessible anymore which
blocks the build process.

Create an alternate MASTER_SITES archive and update the
WWW to point to the archive.org backup of the website.
DeltaFile
+2-2textproc/ctpp2/Makefile
+2-21 files

FreeBSD/ports f24f05btextproc/coccigrep distinfo Makefile

textproc/coccigrep: update 1.20 -> 1.21

Changelog: https://github.com/regit/coccigrep/releases/tag/v1.21

Major changes: fixes compatibility with Python 3.12
DeltaFile
+3-3textproc/coccigrep/distinfo
+1-2textproc/coccigrep/Makefile
+4-52 files

LLVM/project fd676d8mlir/lib/Dialect/LLVMIR/IR LLVMTypes.cpp, mlir/test/IR test-func-erase-result.mlir

[MLIR][LLVM] Fix crash in LLVMFunctionType::clone when erasing void function results (#185093)

LLVMFunctionType::clone(inputs, results) was asserting that
results.size() == 1, which caused a crash (later changed to return
null/failure) when erasing results from a void llvm.func via
FunctionOpInterface::eraseResults.

For LLVM function types, an empty results range maps to void return: the
FunctionOpInterface represents void llvm.func with 0 results, while the
underlying LLVMFunctionType stores an explicit LLVMVoidType. When
erasing all results (or no-op erasing 0 results from a void function),
the interface passes an empty TypeRange to clone(), which should produce
a void function type.

Fix by accepting an empty results range in LLVMFunctionType::clone() and
mapping it to LLVMVoidType. More than one result remains invalid.

Fixes #128322

Assisted-by: Claude Code
DeltaFile
+9-2mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
+3-1mlir/test/IR/test-func-erase-result.mlir
+12-32 files

LLVM/project f4e6226mlir/include/mlir/IR Iterators.h, mlir/test/IR visitors.mlir

[mlir] Fix crash in ForwardDominanceIterator when encountering graph regions (#185043)

ForwardDominanceIterator<NoGraphRegions=true> was asserting when it
encountered a region without SSA dominance (a "graph region"), such as
scf.forall.in_parallel's body. This crash was triggered by
-test-ir-visitors when walking functions that contain graph-region ops.

Change the behavior of ForwardDominanceIterator<true> and
ReverseDominanceIterator<true> to silently skip graph regions instead of
asserting, and update the documentation accordingly. This matches the
intended semantics of the NoGraphRegions flag: the traversal simply does
not enumerate blocks/ops inside such regions.

Fixes #116370

Assisted-by: Claude Code
DeltaFile
+26-16mlir/include/mlir/IR/Iterators.h
+22-0mlir/test/IR/visitors.mlir
+9-7mlir/test/lib/IR/TestVisitors.cpp
+57-233 files

FreeNAS/freenas 2a202ddsrc/middlewared/middlewared/plugins filesystem.py, src/middlewared/middlewared/utils io.py

Address review
DeltaFile
+13-13src/middlewared/middlewared/utils/io.py
+10-0src/middlewared/middlewared/plugins/filesystem.py
+23-132 files

LLVM/project 43a0e59llvm/lib/Target/Hexagon HexagonInstrInfo.cpp HexagonInstrInfo.h, llvm/lib/Target/Hexagon/MCTargetDesc HexagonBaseInfo.h

[Hexagon] Add new register input/output types for qf instructions (#184398)

The v81 iset has been updated with input and output register
types/extensions for instructions. Currently, it supports qf32/qf16
register types. This patch implements a qf reg type lookup to query
these types. In the future, the register type extractor can be improved
and more APIs can be added to support other register types.

Co-authored-by: <santdas at qti.qualcomm.com>
DeltaFile
+165-0llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+30-0llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
+11-0llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+206-03 files

LLVM/project 6d3517bllvm/utils/TableGen/Common CodeGenRegisters.cpp

[TableGen] Fix ordering of register classes with artificial members.

The current implementation wouldn't advance IB to skip artificial
registers once IA has reached the end.
DeltaFile
+8-10llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+8-101 files

LLVM/project 013bdbellvm/lib/Target/ARM MVEGatherScatterLowering.cpp, llvm/test/CodeGen/Thumb2 mve-gather-increment.ll

[MVEGatherScatter] Fix GEP scale calculations (#185437)

The GEP scale for a single index GEP is the type alloc size of the
source element type. The pass was mostly computing it correctly, but two
places were doing something different.
DeltaFile
+152-139llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
+2-2llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
+154-1412 files

LLVM/project e4580d2llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer DependencyGraph.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer DependencyGraph.cpp

[SandboxVec][DAG] Fix unscheduled succs when nodes are scheduled (#184946)

When we update use-def edges the DAG gets notified to update the
UnscheduledSuccs counters. However, if either edge node is already
scheduled we should not update UnscheduledSuccs because the
UnscheduledSuccs counter value should be treated as "undefined" after a
node has been scheduled, i.e., it's value has a meaning only before the
node gets scheduled.
DeltaFile
+36-0llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
+6-2llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
+2-1llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
+44-33 files

LLVM/project f7eba03clang/include/clang/Basic BuiltinsAMDGPU.td, clang/test/CodeGenHIP builtins-amdgcn-gfx12-f16-w64.hip builtins-amdgcn-gfx12-f16-w32.hip

[Clang][AMDGPU] Change __fp16 to _Float16 in builtin definitions
DeltaFile
+96-0clang/test/CodeGenHIP/builtins-amdgcn-gfx12-f16-w64.hip
+96-0clang/test/CodeGenHIP/builtins-amdgcn-gfx12-f16-w32.hip
+88-0clang/test/CodeGenHIP/builtins-amdgcn-f16-misc.hip
+70-0clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-f16-misc.hip
+27-0clang/test/CodeGenHIP/builtins-amdgcn-gfx950-f16.hip
+13-13clang/include/clang/Basic/BuiltinsAMDGPU.td
+390-138 files not shown
+399-2214 files

LLVM/project c0a3996llvm/utils/gn/secondary/llvm/lib/Target/X86 BUILD.gn, llvm/utils/gn/secondary/llvm/unittests/Target/X86 BUILD.gn

[gn] port 443ce5569ee9854c more
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/unittests/Target/X86/BUILD.gn
+2-02 files

OpenBSD/src 2S5h8eZusr.bin/tmux format.c tmux.1

   Add next/previous variables for windows in W: loop, from Conor Taylor in
   GitHub issue 4856.
VersionDeltaFile
1.348+43-1usr.bin/tmux/format.c
1.1036+21-2usr.bin/tmux/tmux.1
1.204+3-3usr.bin/tmux/options-table.c
+67-63 files

FreeNAS/freenas 7b9b6fdsrc/middlewared/middlewared/plugins zettarepl.py, src/middlewared/middlewared/plugins/snapshot __init__.py task.py

Make `pool.snapshottask.run` a job that can raise an error
DeltaFile
+49-11src/middlewared/middlewared/plugins/zettarepl.py
+59-0tests/api2/test_snapshot_task_run.py
+4-2src/middlewared/middlewared/plugins/snapshot/__init__.py
+3-2src/middlewared/middlewared/plugins/zettarepl_/state.py
+2-2src/middlewared/middlewared/plugins/snapshot/task.py
+117-175 files

FreeNAS/freenas 68c669btests/protocols iscsi_proto.py

Make running non-iscsi tests possible on the same TrueNAS machine
DeltaFile
+7-3tests/protocols/iscsi_proto.py
+7-31 files

LLVM/project 2a9372fclang/docs TypeSanitizer.rst, compiler-rt/lib/tysan tysan.cpp tysan_flags.inc

halt_on_error flag for TySan and docs (#182479)
DeltaFile
+23-0compiler-rt/test/tysan/halt_on_error.c
+12-0clang/docs/TypeSanitizer.rst
+5-0compiler-rt/lib/tysan/tysan.cpp
+2-0compiler-rt/lib/tysan/tysan_flags.inc
+42-04 files

LLVM/project ce22796mlir/include/mlir/Dialect/XeGPU/TransformOps XeGPUTransformOps.td, mlir/lib/Dialect/XeGPU/TransformOps XeGPUTransformOps.cpp

[mlir][xegpu] Add support for setting `order` in `SetDescLayoutOp` and `SetOpLayoutAttrOp` transform ops. (#184705)

Currently XeGPU transform dialect does not allow the user to set the
`order` attribute of a layout in `SetDescLayoutOp` and
`SetOpLayoutAttrOp`. This PR adds `order` as an optional argument to
these transform ops.
DeltaFile
+66-6mlir/test/Dialect/XeGPU/transform-ops.mlir
+51-0mlir/test/python/dialects/transform_xegpu_ext.py
+26-19mlir/lib/Dialect/XeGPU/TransformOps/XeGPUTransformOps.cpp
+14-2mlir/include/mlir/Dialect/XeGPU/TransformOps/XeGPUTransformOps.td
+16-0mlir/python/mlir/dialects/transform/xegpu.py
+173-275 files

FreeBSD/doc a7739edwebsite/content/en/releases/14.4R errata.adoc

14.4/errata: add issue - freebsd-update hanging when pkg is not bootstrapped

Add an erratum describing a problem where freebsd-update(8) commands such as
fetch or install may hang when pkg(8) is not bootstrapped.

The erratum also documents a workaround: bootstrap pkg(8) before running
freebsd-update(8).

Reviewed by: ziaee, grahamperrin
Approved by: ziaee, re (implicit)
Differential Revision: https://reviews.freebsd.org/D55754
PR: 293640
DeltaFile
+3-1website/content/en/releases/14.4R/errata.adoc
+3-11 files

LLVM/project 87e21efclang/lib/Sema SemaHLSL.cpp HLSLBuiltinTypeDeclBuilder.cpp, clang/test/AST/HLSL TypedBuffers-AST.hlsl

Gemini code review.
DeltaFile
+31-14clang/lib/Sema/SemaHLSL.cpp
+13-8clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+10-0clang/test/AST/HLSL/TypedBuffers-AST.hlsl
+4-1llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+2-2clang/test/CodeGenHLSL/resources/Texture2D-Mips.hlsl
+2-2clang/test/CodeGenHLSL/resources/Texture2D-default-explicit-binding.hlsl
+62-272 files not shown
+64-308 files