FreeNAS/freenas fed0683src/middlewared_docs changelog.py

JSON schema keys enum

(cherry picked from commit 0389d2a7860a07697f241f53f9fc7ccac5753e61)
DeltaFile
+70-43src/middlewared_docs/changelog.py
+70-431 files

FreeNAS/freenas c8b7f44.github/workflows mypy.yml, src/middlewared_docs generate_docs.py

fix mypy

(cherry picked from commit 9069788327d35d2a9eee4abb47391527da0640e3)
DeltaFile
+2-2src/middlewared_docs/generate_docs.py
+1-0.github/workflows/mypy.yml
+3-22 files

FreeNAS/freenas 38b26f2src/middlewared_docs generate_docs.py changelog.py

page for no schema changes

(cherry picked from commit 45d1a5e7c88833854dbf8a92913d6f63a5640bf4)
DeltaFile
+25-21src/middlewared_docs/generate_docs.py
+4-26src/middlewared_docs/changelog.py
+29-472 files

FreeNAS/freenas fb05836src/middlewared_docs generate_docs.py changelog.py

new module

(cherry picked from commit 8182d13aadd446aee86605136e6194820340b83a)
DeltaFile
+33-177src/middlewared_docs/generate_docs.py
+168-0src/middlewared_docs/changelog.py
+201-1772 files

FreeNAS/freenas 822f482.github/workflows mypy.yml, src/middlewared_docs test_changelog.py generate_docs.py

address review

(cherry picked from commit 39d0c5f8a890cf5348e412774d437f910a5e8d3a)
DeltaFile
+0-327src/middlewared_docs/test_changelog.py
+325-0src/middlewared_docs/tests/test_changelog.py
+52-46src/middlewared_docs/generate_docs.py
+19-62src/middlewared_docs/changelog.py
+10-0src/middlewared_docs/ruff.toml
+7-0.github/workflows/mypy.yml
+413-4353 files not shown
+423-4369 files

FreeNAS/freenas 8886a29src/middlewared_docs changelog.py generate_docs.py

generalize previous/current --> old/new

(cherry picked from commit 362dc596eb6c3de2b01f698ab20264b7fa3e220c)
DeltaFile
+12-12src/middlewared_docs/changelog.py
+5-4src/middlewared_docs/generate_docs.py
+17-162 files

FreeNAS/freenas 71abf80src/middlewared_docs changelog.py

field becoming required implies no default value

(cherry picked from commit 821c28b889d0a6b289040f9737dbaf35c960082e)
DeltaFile
+8-1src/middlewared_docs/changelog.py
+8-11 files

FreeNAS/freenas fa2a603src/middlewared_docs generate_docs.py changelog.py

remove repetitive word "field" from every change summary

(cherry picked from commit a13dc7dfff5820753b2c61d2377883146bc10b8c)
DeltaFile
+13-5src/middlewared_docs/generate_docs.py
+6-6src/middlewared_docs/changelog.py
+19-112 files

FreeNAS/freenas 63daf45src/middlewared_docs changelog.py test_changelog.py

ruff format

(cherry picked from commit 8bbfe6ddfebeeb2863403682c93ae53e6cf6cb4a)
DeltaFile
+87-23src/middlewared_docs/changelog.py
+76-32src/middlewared_docs/test_changelog.py
+163-552 files

FreeNAS/freenas 35ce882.github/workflows unittests.yml, src/middlewared_docs test_changelog.py

changelog unit tests

(cherry picked from commit aaafd0fb4c56d0c93815abd6a907f6fb7a91f902)
DeltaFile
+283-0src/middlewared_docs/test_changelog.py
+3-0.github/workflows/unittests.yml
+286-02 files

FreeNAS/freenas 404cbb9src/middlewared_docs generate_docs.py

consistent boldface method links

(cherry picked from commit e12e8d6fd6456ddc5c7d7b769e7736b15569fb25)
DeltaFile
+4-4src/middlewared_docs/generate_docs.py
+4-41 files

FreeNAS/freenas 840051bsrc/middlewared_docs changelog.py

rewrite

(cherry picked from commit f94f6df610fd343fbbdae6249357c2ea063d14ba)
DeltaFile
+307-94src/middlewared_docs/changelog.py
+307-941 files

FreeNAS/freenas eb908basrc/middlewared_docs generate_docs.py

link to removed method pages

(cherry picked from commit 8e91a25ea0d62844f0b3eedf1a3214ab8de7dc1e)
DeltaFile
+14-6src/middlewared_docs/generate_docs.py
+14-61 files

FreeNAS/freenas 76a3087src/middlewared_docs generate_docs.py

🪗

(cherry picked from commit 10ce85d3975f35505ec465bd431a532e03c6618f)
DeltaFile
+40-0src/middlewared_docs/generate_docs.py
+40-01 files

FreeNAS/freenas 95cf413src/middlewared_docs changelog.py

cut unnecessary defensive programming

(cherry picked from commit a7f823ae0aa7d4439ff07b0470ed2718c9445b9f)
DeltaFile
+41-35src/middlewared_docs/changelog.py
+41-351 files

FreeNAS/freenas 48bbadfsrc/middlewared_docs changelog.py

better type summaries

(cherry picked from commit a3440c5f81c2369f28ee49abbc279fb26be9df74)
DeltaFile
+42-6src/middlewared_docs/changelog.py
+42-61 files

FreeNAS/freenas 84024c4src/middlewared_docs changelog.py generate_docs.py

remove event sections (events are not versioned)

(cherry picked from commit 82b7633dff262c5366413278fa76d5d0500785f2)
DeltaFile
+8-18src/middlewared_docs/changelog.py
+0-16src/middlewared_docs/generate_docs.py
+8-342 files

FreeNAS/freenas 09fd3fbsrc/middlewared_docs generate_docs.py, src/middlewared_docs/docs index.rst

draft

(cherry picked from commit 797fb1e86233bb8d3999ddaa9fb5187c58de4b37)
DeltaFile
+259-4src/middlewared_docs/generate_docs.py
+1-0src/middlewared_docs/docs/index.rst
+260-42 files

FreeNAS/freenas a0787c7.github/workflows mypy.yml, src/middlewared_docs changelog.py generate_docs.py

NAS-141307 / 27.0.0-BETA.1 / Generate API changelog pages that compare adjacent versions (#19140)

## Summary

This branch adds an automatically generated Changelog page to the API
documentation site. For each documented API version, it computes a
semantic diff against the immediately preceding version and renders a
per-version page summarizing what changed in the API surface: methods
added, methods removed, and methods whose call-parameter or return-value
schemas changed.

The diff is semantic, not cosmetic. It reads the structural shape of
each method's JSON Schema (from middlewared --dump-api) and ignores
description/example wording and validation-constraint keys (minLength,
pattern, etc.). A method whose only change is reworded docs or a tweaked
regex produces no changelog entry.

## What's included


    [25 lines not shown]
DeltaFile
+446-0src/middlewared_docs/changelog.py
+325-0src/middlewared_docs/tests/test_changelog.py
+224-62src/middlewared_docs/generate_docs.py
+10-0src/middlewared_docs/ruff.toml
+8-0.github/workflows/mypy.yml
+6-0src/middlewared_docs/tests/conftest.py
+1,019-623 files not shown
+1,026-629 files

FreeBSD/ports 0c0055e. UPDATING, net-mgmt/librenms distinfo Makefile

net-mgmt/librenms: Update to 26.6.0

re: https://github.com/librenms/librenms/releases/tag/26.6.0

This release requires a database update and a new configuration item

Add this entry to $PREFIX/librenms.env

  XDG_CACHE_HOME=/var/db/librenms/font-cache
DeltaFile
+12-0UPDATING
+9-2net-mgmt/librenms/files/patch-.env.example
+5-5net-mgmt/librenms/distinfo
+2-2net-mgmt/librenms/Makefile
+28-94 files

FreeNAS/freenas 43e468esrc/middlewared/middlewared/plugins/pool_ pool.py, tests/api2 test_special_vdev.py

Relax special class vdev consistency validation

This commit relaxes the consistency checks for vdev types used in
special vdevs. Doing a mix-and-match topology is considered to be a
deviation generally from best practice, but as long as the
administrator is careful to make sure they don't spread it too wide
(for example, mirror + 5-wide RAIDZ1) then the impact should be
relatively minor. Allowing this is generally a loaded foot-gun for
administrators since the topology changes cannot be undone once they
are committed; and if they run into performance issues related to
the imbalanced topology then they may have little recourse to fix the
issues. It is generally best for users to follow best practices as
defined by the support / engineering teams.
DeltaFile
+104-58tests/api2/test_special_vdev.py
+37-1src/middlewared/middlewared/plugins/pool_/pool.py
+141-592 files

FreeBSD/src 76f9bb4sys/dev/rge if_rge.c

rge: fix VLAN hardware tagging

Set the correct value in the TX descriptor for the vlan header.

PR: kern/295175
DeltaFile
+1-1sys/dev/rge/if_rge.c
+1-11 files

LLVM/project c14a023llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-private.mir

AMDGPU/GlobalISel: Switch to extended LLTs

With minimal changes. Most notably because of changes to jumptable in isel
GIM_SwitchType requires explicit integer/float types and does not match scalar.
In most places change is in lowering to use LLT::integer or LLT::float.

Other changes:
- replaceRegWith can also change type on Dst register, this can cause CSE data
  corruption (fix is to notify observer)
- mixed i32/f32 in G_MERGE_VALUES/G_UNMERGE_VALUES, common in legalizing
  ray tracing and image intrinsics
- need extra bitcast between i32/f32 in some place
DeltaFile
+7,957-7,957llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+6,802-6,774llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+6,489-6,465llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+5,732-5,732llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+5,645-5,645llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+3,852-3,852llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+36,477-36,425590 files not shown
+100,631-94,775596 files

FreeNAS/freenas f028b63src/middlewared/middlewared/api/v26_0_0 pool.py, src/middlewared/middlewared/api/v27_0_0 pool.py

Fix
DeltaFile
+8-0src/middlewared/middlewared/plugins/pool_/pool.py
+2-2tests/api2/test_special_vdev.py
+1-1src/middlewared/middlewared/api/v26_0_0/pool.py
+1-1src/middlewared/middlewared/api/v27_0_0/pool.py
+12-44 files

LLVM/project aad993ellvm/lib/Target/AArch64 AArch64InstrFormats.td AArch64ISelDAGToDAG.cpp

fixup! Address CR comments
DeltaFile
+4-6llvm/lib/Target/AArch64/AArch64InstrFormats.td
+3-0llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+7-62 files

LLVM/project 961e7d1mlir/include/mlir/Dialect/EmitC/IR EmitC.td, mlir/test/Dialect/EmitC member_call_opaque.mlir

[MLIR][EmitC] Allow lvalue operands in (member_)call_opaque arg_operands (#204112)

Widen the `arg_operands` of `emitc.call_opaque` and
`emitc.member_call_opaque` from `Variadic<EmitCType>` to
`Variadic<AnyTypeOf<[EmitCType, EmitC_LValueType]>>` to support taking
arguments by reference (e.g., out-parameters in destination-passing
style, or move-only types that cannot be copied into the call).

No translation/emitter codegen changes are needed, the generated C++ for
`arg_operands` also works with reference parameters.
DeltaFile
+18-0mlir/test/Target/Cpp/call.mlir
+7-0mlir/test/Dialect/EmitC/member_call_opaque.mlir
+2-2mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
+27-23 files

LLVM/project d7a2e87llvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine icmp-mul.ll

[InstCombine] Fold square into comparison with constant (#197665)

Closes #196233 
Alive2 proof: https://alive2.llvm.org/ce/z/PQzYhb
DeltaFile
+166-0llvm/test/Transforms/InstCombine/icmp-mul.ll
+42-6llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+208-62 files

LLVM/project a07a6ffflang/lib/Lower/OpenMP OpenMP.cpp

address review comments
DeltaFile
+8-6flang/lib/Lower/OpenMP/OpenMP.cpp
+8-61 files

LLVM/project bec0465flang/lib/Lower/OpenMP OpenMP.cpp, flang/lib/Optimizer/OpenMP DoConcurrentConversion.cpp

[Flang][OpenMP] Add combined construct information

This patch adds the `omp.combined` attribute to OpenMP dialect
operations following changes to the `ComposableOpInterface`.

This attribute is added to operations representing non-innermost leaf
constructs of a combined construct and to standalone block-associated
constructs that can be combined with their parent construct.

Changes are made to the OpenMP lowering logic, as well as the
do-concurrent, workshare and workdistribute transformation passes.
DeltaFile
+1,094-0flang/test/Lower/OpenMP/compound.f90
+56-20flang/lib/Lower/OpenMP/OpenMP.cpp
+6-6flang/test/Transforms/DoConcurrent/use_loop_bounds_in_body.f90
+5-5flang/test/Transforms/DoConcurrent/local_device.mlir
+4-4flang/test/Transforms/DoConcurrent/reduce_device.mlir
+6-2flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
+1,171-3727 files not shown
+1,225-7133 files

LLVM/project af27c81clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen arm_neon_intrinsics.c

[AArch64] Remove aarch64_neon_vcvtfp2hf and aarch64_neon_vcvthf2fp (#203903)

This removes aarch64_neon_vcvtfp2hf and aarch64_neon_vcvthf2fp
intrinsics, relying on fp16 fpext and fptrunc instructions directly. Arm
is left using its version of the intrinsics, as the types in the backend
are more difficult without fullfp16.
DeltaFile
+92-0clang/test/CodeGen/AArch64/neon-misc-constrained.c
+8-20clang/test/CodeGen/AArch64/neon-misc.c
+12-12llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcvt_f32_su32.ll
+17-4clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+7-12clang/test/CodeGen/arm_neon_intrinsics.c
+19-0llvm/lib/IR/AutoUpgrade.cpp
+155-487 files not shown
+161-7713 files