www/immich-ml: Add missing pillow-jxl-plugin dependency
Since 3.4.0 the transforms module imports pillow_jxl unconditionally, so
the service does not start without it.
Sponsored by: Netzkommune GmbH
graphics/py-pillow-jxl-plugin: Add New Port
A Pillow plugin that adds reading and writing of JPEG XL images. The
codec comes from graphics/libjxl, the plugin binds it through Rust.
www: https://github.com/Isotr0py/pillow-jpegxl-plugin
Sponsored by: Netzkommune GmbH
[mlir][bufferization] In OptimizeAllocationLiveliness optimize `dealloc` placement for unused `alloc`'s (#227975)
Addresses issue https://github.com/llvm/llvm-project/issues/227363
As of this PR (https://github.com/llvm/llvm-project/pull/229296). The
position of the `dealloc` was correctly, and safely moved within
`OptimizeAllocationLiveliness`.
Issue https://github.com/llvm/llvm-project/issues/227363 raises a missed
optimization where if the `alloc` is unused, and the only other
reference to that memory buffer is a `dealloc` the optimization is not
run. This PR fixes this.
When a `lastUser` does not exist, implying the `memref` is unused, we
can just hoist the `dealloc` to be as close to the `allocOp` as possible
[AVR] Allow ICALL and IJMP on the reduced cores (#241840)
This patch fix a crash when using function pointer on AVRTiny devices,
for which llvm would emit `icall`.
Signed-off-by: Mintsuki <mintsuki at protonmail.com>
[AutoUpgrade] Add textual IR upgrade of alias scope domains (#241786)
Alias scope domains that have no disjointness flag are implicitly
non-disjoint. Bitcode upgrade functionality was already in #218768; we
move it from `MetadataLoader` to `AutoUpgrade`, to invoke it from
`LLParser::validateEndOfModule`. The alias scope lists are discovered by
iterating over the instructions in the module.
The existing upgrade test file can be used for both upgrade paths. The
test of the bitcode upgrade relied on a (non-upgrading) llvm-as
translation of the textual source; this is replaced by a checked-in
bitcode translation (made using LLVM 21.1.8).
[InstCombine] Clarify fixpoint error message (NFC) (#241889)
Give more detailed instructions on what to do when encountering this
error. Emphasize that no issue should be filed.
[mlir][bufferization] Narrow the call aliasing rule in BufferViewFlowAnalysis to memrefs (#240508)
In `BufferViewFlowAnalysis`, a call op's results are unconditionally
treated as possible views of its operands, regardless of their types.
This change narrows the rule to memrefs: a result is a possible view of
an operand only when both are memrefs. This rule is consistent with the
rest of the analysis, which recognizes only memrefs as buffers.
Without it, `optimize-allocation-liveness` counts a use of a call's
scalar result as a use of the buffer the call received, and places the
dealloc after that use instead of after the call.
Before #229296 the pass moved the free past the `func.return` on the new
test case and produced invalid IR.
Assisted-by: Claude
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[IRBuilder] Always create at least one GEP in CreateGEP() (#241925)
This makes the behavior more consistent with CreatePtrAdd etc, which
will not implicit drop a zero-offset ptradd. This will avoid additional
churn when switching callers to CreatePtrAdd in the future.
This also reduces the risk of breaking caller assumptions, in particular
that CreateGEP will always return either a constant or a
GetElementPtrInst (unless InstSimplifyFolder is used).
[LoongArch][NFC] Move XOR combine into performXORCombine (#242151)
Extract the inline ISD::XOR handling in PerformDAGCombine into a
dedicated performXORCombine helper, matching how the other opcodes (AND,
OR, SETCC, ...) are structured. No functional change.
Also fix a clang-format issue in emitPseudoVMSKCOND.
Assisted-By: LLM
[clang][CIR] Add tests for SVE RINTI intrinsics (#240757)
adds CIR tests for svrinti (plain SVE) intrinsics.
Moves and adapts `sve-intrinsics/acle_sve_rinti.c` to `sve/rinti.c`
Part of #223963
[clang][CIR] Add tests for SVE RINTX intrinsics (#241369)
adds CIR tests for svrintx (plain SVE) intrinsics.
Move sve-intrinsics/acle_sve_rintx.c to sve/rintx.c and add
CIR checks for all f16/f32/f64 variants with _z/_m/_x predication.
Part of #223963.
Co-authored-by: Ente Wang <ente.wang at h-partners.com>
[ConstantRange] Handle llvm.{sshl,ushl}.sat (#242178)
Wire up ConstantRange::intrinsic() to sshl_sat and ushl_sat, restricting
their shift range to [0, BitWidth).
Alive2: https://alive2.llvm.org/ce/z/9WSZqW
