[ARM] Use GOT indirection for weak symbols in PIC mode (#198577)
On ARM ELF PIC, weak dso_local symbols were incorrectly accessed via
PC-relative constant pool entries (e.g. .long xxx-(.LPC+8)). The
assembler eagerly resolves this expression when both the symbol and
label are in the same section, preventing the linker from overriding a
weak definition with a strong one from another object file.
Fix #183916 by treating weak symbols as indirect (requiring GOT) on ELF
PIC, matching GCC's behavior. This affects:
- isGVIndirectSymbol (ARMTargetMachine) — Darwin, GlobalISel, stack
prot.
- isGVInGOT (ARMSubtarget)
- LowerGlobalAddressELF (SelectionDAG path)
- ARMLowerPICELF (FastISel path)
Assisted-by: Claude Opus 4.7 <noreply at anthropic.com>
www/mattermost-server: Update to 10.11.19 and change LICENSE to AGPLv3
Mattermost can be licensed under either MIT or AGPLv3. AGPLv3 should
be used to create compiled versions not produced by Mattermost, Inc.
clang: Remove hacky OpenMP handling for appending bound arch
Use the same path as CUDA/HIP and stop doing a hacky search through
the arguments looking for -march.
[GlobalISel] Do not use recordsOperand() to check if a Combiner C++ predicate can be hoisted (#200815)
The combiner does not use RecordNamedOperand, so assume that any operand
is "recorded" in the sense that can be used by a C++ predicate.
[GlobalISel] Do not use recordsOperand() to check if a Combiner C++ predicate can be hoisted
The combiner does not use RecordNamedOperand, so assume that any operand is "recorded" in the sense
that can be used by a C++ predicate.
NAS-141183 / 27.0.0-BETA.1 / Replace constructed-filter `filter_list` calls with native Python (#19024)
## Summary
`filter_list()` is TrueNAS's query engine: it compiles a filter DSL
(`[['field', 'op', value]]`) and options (`get`, `select`, `order_by`,
...) and runs them through the `truenas_pyfilter` C extension. It exists
so that **caller-supplied** query-filters arriving from an API method
can be applied to an in-memory list.
Over time it has also been used internally with **hardcoded** filters —
places where the filter and options are literals written in the source,
not values received from a caller. In those cases the DSL buys nothing:
it's a less direct, less readable, and slightly more expensive way of
writing a predicate that Python already expresses with `any()`,
`next()`, or a comprehension.
This branch replaces those constructed-filter calls with the equivalent
native Python, while leaving every legitimate use of `filter_list`
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[AMDGPU][GIsel] Replace old C type castings with safer C++ (#201505)
AMDGPURegisterBankInfo.cpp still contains the old C style castings to int type which can be switched to much safer C++ variants.
[LV] Implement integer part of VPDerivedIV cost model (#198252)
Adds support for InductionDescriptor::IK_IntInduction variants of
inductions in VPDerivedIVRecipe::computeCost. Designing a cost model for
this recipe is tricky because it gets expanded in expandVPDerivedIV into
smaller individual recipes that will then be folded by simplifyRecipe.
Effectively the cost model has to guess how these will be folded
otherwise the costs will be too pessimistic. For example, 'add i32 %x,
0' and 'mul i32 %x, 1' should both be treated as zero cost since all
uses will be replaced with '%x'. Similarly,
'mul i32 %x, 4' will be converted to 'shl i32 %x, 2', and 'mul i32 %x,
-1' will be simplified to 'sub i32 0, %x'.
As can be seen by this PR, it's important to have non-zero costs for
cases where VPDerivedIVRecipe recipes will end up with non-foldable
instructions. Some of the tests now favour wider VFs to cover the
non-zero cost, or in other cases we prefer not to vectorise at all. I've
added loop attributes in some places to maintain the previous
vectorisation behaviour so that we're still matching the intent of the
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Update to autogen 5.16.2, requested by naddy
This fails one regress test which is quite a bit better than current:
PATH is /usr/local/bin:/usr/ports/pobj/autogen-5.16.2/bin:/usr/bin:/bin:/usr/sbin:/sbin:/usr/local/bin:/usr/X11R6/bin
creating cgi.tpl
creating html.tpl
creating html.out in /usr/ports/pobj/autogen-5.16.2/autogen-5.16.2/agen5/test/testdir
Abort trap (core dumped)
FAILURE: autogen unexpectedly succeeded
[AMDGPU][Uniformity Analysis] Marking G_DYN_STACKALLOC AlwaysUniform in uniformity analysis (#200390)
Mark G_DYN_STACKALLOC as AlwaysUniform.
The result of G_DYN_STACKALLOC is always derived from the wave-uniform
stack pointer and wave-wide max reduce alloca size hence its always uniform.
[alpha.webkit.UncountedCallArgsChecker] Protect the const member getter's this argument (#201147)
This PR fixes a bug that when a const member variable getter is
detected, we don't check if its object argument is kept alive for the
duration of the function call.
[GlobalISel] Do not depend on the RuleMatcher at MatchTable emission (#200799)
Some PredicateMatchers/MatchAction/OperandRenderers relied on accessing
RuleMatcher at emission as a crutch.
Instead, make these classes collect all necessary information in the
constructor so the `emit` methods don't depend on RuleMatcher anymore.
The primary motivation for this is that I've been looking at ways to
optimize the MatchTable better,
and the fact that Predicates/Actions/Renderers are not "pure" objects,
in the sense that they keep
accessing a bunch of data all over the place even as late as emission,
was a consistent pain.
This is NFCI. There are no changes to any of the match table for
AMDGPU/AArch64 in this patch.
This patch has a bunch of noise due to function signature changes so
I'll highlight the following interesting changes:
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[InstCombine] Fix assertion in GEP exact div/shr index canonicalization (#201431)
When canonicalizing the index of `(gep ptr, (div/shr exact X, C))`,
visitGetElementPtrInst builds the new index with Builder.CreateBinOp and
then sets the exact flag via
`cast<BinaryOperator>(NewOp)->setIsExact()`. If X is a constant (as can
be proved during InstCombine), the folding builder constant-folds NewOp
to a non-BinaryOperator, so the cast asserts.
Fix this by adding a CreateExactBinOp API, so the exact flag is set on creation.
Fixes #190324.
[mlir][EmitC] Convert MemRef::DeallocOp (#194591)
Add `memref.dealloc` lowering to EmitC by mapping pointer-backed
deallocations to `void*` cast + `free()` call. This complements the
existing `memref.alloc` lowering to `malloc()` / `aligned_alloc()` and
ensures the pass emits the required standard library include when
`free()` is used.
Assisted-by: Codex (refine implementation + tests). I reviewed all code
and tests before submission.
[AMDGPU][InstCombine] Match ds_swizzle rotate mode for cyclic lane shuffles (#199004)
Follow-up to 17cc4f77109d [AMDGPU][InstCombine] Optimize constant
shuffle patterns (#192246).
Adds matchDsSwizzleRotatePattern to recognise shuffles of the form
dst_lane = (src_lane + N) % 32 (N in [1, 31]) and lower them to a single
ds_swizzle with rotate-mode encoding (ROTATE_MODE_ENC | N << 5),
available on GFX9+. The bitmask mode cannot express such rotations since
the carry between bit positions makes the per-bit mapping
non-independent. On wave64 the pattern is accepted only when
hasPeriodicLayout<32> confirms both 32-lane groups rotate by the same
amount. Wave32-only ID forms (mbcnt.lo alone) are correctly rejected on
wave64 targets.
Co-authored-by: Barbara Mitic <Barbara.Mitic at amd.com>
