[MLIR] Validate directly parsed optional operand types (#212493)
Commit 6c51938067fa ([MLIR] Guard optional operand resolution in
generated op parsers) guarded resolution of every optional operand to
avoid indexing an empty inferred type range. The guard also skipped
resolveOperands when an optional operand was absent but an independently
optional type directive was present. This accepted malformed assembly
and silently discarded the orphan type when printing the operation.
Keep the guard for inferred type resolutions, which may access an empty
optional type vector, but always resolve directly parsed type ranges so
resolveOperands validates operand/type cardinality. Add coverage for
both valid forms and a type-only negative reproducer.
[Hexagon] Link static PIE executables against rcrt1.o (#210125)
We always selected crt1.o as the CRT start file, regardless of link
mode.
Select rcrt1.o - the self-relocating static-PIE start file when -static
and PIE are active
(cherry picked from commit c45b4e4d00bed488d6ece5608560561732ae5b9e)
[IR] Remove deprecated InsertPosition(Instruction*) constructor (#212640)
This implicit constructor has been marked deprecated since almost 2
years in favor of constructing an InsertPosition from a
BasicBlock::iterator.
Remove it now that in-tree users no longer rely on it.
Co-authored-by: Claude <noreply at anthropic.com>
mail/stalwart: Update to 0.16.15
The CLI utility has been splitted into an upcoming separate port
mail/stalwart-cli.
While here:
- properly define dual licensing (AGPLv3 and SELv2)
- mark as broken on i386 since it does not build due to out of memory
- remove obsolete patches and pkg-message
- remove sample configuration file, which is now auto-generated by
default
Changelog: https://github.com/stalwartlabs/stalwart/blob/v0.16.15/CHANGELOG.md
PR: 295646
Reported by: Adrian Gschwend <ktk at netlabs.org> (initial patch),
Herbert J. Skuhra <herbert at gojira.at> (committed patch)
Reviewed by: mickael.maillot at gmail.com,
mikael,
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[Hexagon] Fix compiler-rt install dir type, scope sanitizers (#209375)
COMPILER_RT_INSTALL_LIBRARY_DIR must be CACHE STRING, not CACHE PATH: a
relative PATH-typed cache entry resolves against the runtimes sub-build
directory instead of CMAKE_INSTALL_PREFIX, misplacing sanitizer libs.
Replace the explicit COMPILER_RT_BUILD_* ON list with
COMPILER_RT_SANITIZERS_TO_BUILD=all, since those options already default
ON upstream and infeasible sanitizers self-exclude via their own
ALL_<X>_SUPPORTED_ARCH lists.
Add FORCE to the dylib overrides so they take effect after
hexagon-unknown-linux-musl-clang-dist.cmake has already cached them OFF.
(cherry picked from commit 34aefe9744fa83fa222d7f28e073c693c2c4ff5b)
[RISCV] Don't move memory instructions across calls in isSafeToMove (#212236)
RISCVInstrInfo::isSafeToMove scans the instructions between From and To
to decide whether a memory instruction can be moved, but it only treated
mayStore() instructions as barriers. Calls on RISC-V are modeled with
isCall() and a register mask rather than mayStore(), so a load could be
moved across a call even though the callee may clobber the loaded
memory.
RISCVVectorPeephole::foldVMergeToMask uses this helper via ensureDominates()
to sink a load into a masked load when folding it into a vmerge, which
produced wrong code when the load was sunk past a call.
Instead of hand-rolling the barrier check, call MachineInstr::isSafeToMove
on each intervening instruction to populate SawStore. That is the same
helper used on From below, and it already treats calls (as well as PHIs
and ordered memory references) as stores.
This fixes #212226.
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[PAC][Headers] Fix incorrect comment in ptrauth.h (#207265)
The discriminator which is used to sign pointers to v-tables
is not always zero.
(cherry picked from commit 26643a89ddf98e48e986d25ceb10f673735bc7d7)
[ARM] Exclude TLS symbols from the .reloc/R_ARM_REL32 path (#212549)
The .reloc branch in emitMachineConstantPoolValue fired for any
isWeakForLinker() + isDSOLocal() symbol, including TLS (thread_local)
weak symbols. R_ARM_REL32 is wrong for TLS: TLS symbols need
TLS-specific relocations (R_ARM_TLS_GD32 etc.). Using R_ARM_REL32 for a
TLS symbol produces a wrong address at runtime.
This broke the 2-stage ARM 32-bit buildbots: stage 1 (with the .reloc
branch) miscompiled stage 2's BPF codegen (BTFDebug.cpp references
llvm::sys::sandbox::Enabled, an inline thread_local weak variable),
causing a SIGSEGV in the BPF Assembly Printer.
Add a regression test (tls_weak_var in elf-preemption.ll) verifying that
TLS weak symbols get TLSGD/TPOFF, not R_ARM_REL32.
Fix #212545
clang: Use TargetID parsing from AMDGPUTargetParser
We had grown 2 parallel parsing implementations for
triple+gpu name+feature flag target ID strings. Mostly
eliminate the redundant clang version.
Co-authored-by: Claude (Opus 4.8)
[WebAssembly] Fix v8i16-to-v8f32 uitofp cost (#212501)
I think there was a wrong duplication here. The WebAssembly SIMD
conversion cost table accidentally duplicated the
`UINT_TO_FP` entry for `v8i8` to `v8f32`. As a result, the unsigned
`v8i16` to `v8f32` conversion missed the target-specific table entry and
fell back to the generic cost of 5 instead of the intended cost of 10.
I've added ` llvm/test/Analysis/CostModel/WebAssembly/cast.ll` which I
think is good here as it would help test other casting errors in the
future too.
statfs(2): allow to interrupt busying
There are probably more places which could benefit from allowing to
interrupt vfs_busy() calls at syscalls top level.
Requested by: Peter Eriksson <pen at lysator.liu.se>
Reviewed by: jah, markj
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Differential revision: https://reviews.freebsd.org/D58477
vfs_busy(): add MBF_PCATCH flag to allow interrupting the sleep
Reviewed by: jah, markj
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Differential revision: https://reviews.freebsd.org/D58477
AMDGPU: Eliminate old macro driven processor name parsing
Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.
Co-authored-by: Claude (Claude-Opus-4.8)
AMDGPU: TableGen the subarch to processor name mapping table
Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical GPU
name) with a generated table.
Co-authored-by: Claude (Claude-Opus-4.8)
AMDGPU: TableGen subarch to major subarch table
Replace the hand-written AMDGPUMajorFamilies array with a
generated lookup table. Adds a special case for the major
arches missing a concrete generic target definition (we probably
should just define those to avoid this).
Co-authored-by: Claude (Claude-Opus-4.8)
AMDGPU: Handle more TargetParser queries in tablegen
Previously we had various enum switches. Start generated tables
indexed by enums. Avoid some special cases by defining the dummy
"generic" and "generic-hsa" targets as real processors.
Co-authored-by: Claude (Claude-Opus-4.8)
AMDGPU: Generate TargetParser table from TableGen (#212353)
Migrate .def file to tablegen. The initial TargetParser
AMDGPU backend only handled R600. Extend to modern targets.
Stub out some tablegen definitions which will be used in future
changes.
Co-authored-by: Claude (Claude-Opus-4.8)
