ptrace: Propagate errors from set_fpregs()
Otherwise ptrace(PT_SETREGSET) will not return errors to userspace.
Fixes: cef05c5a62ba ("amd64: do not allow to set reserved bits in MXCSR for ptrace(PT_SETFPREGS)")
Reviewed by: kib
Differential Revision: https://reviews.freebsd.org/D58577
uma: Fix KMSAN integration with malloc zones
In commit 459aa032e872 I dropped kmsan_mark() calls from malloc() on the
basis that UMA and kmem_malloc() would handle updates of the KMSAN
shadow map. However, I missed that UMA explicitly does not handle this.
Modify UMA to only omit origin map updates for malloc zones.
Fixes: 459aa032e872 ("malloc: Refactor redzone and sanitizer handling")
Reviewed by: rlibby
Differential Revision: https://reviews.freebsd.org/D58574
AMDGPU: Separate image_msaa_load from bvh-ray-tracing-insts (#213270)
Add a separate msaa-load-insts feature so image_msaa_load is available
on gfx13, which has it but not the BVH intersect-ray instructions. These
were assumed to be the same feature previously, but gfx13 does not have the
bvh instructions, but does have image_msaa_load.
Co-authored-by: Claude (Claude-Opus-4.8)
[Offload] add 'olIterateSymbols' runtime function (#213036)
Summary:
This provides users with a way to check all symbols present in a given
program. This is useful for many cases where a power user wants to do
something dynamic with the objects present.
Reland "[HIPSPV] Add in-tree SPIR-V backend support for chipStar" (#213052)
Relands #206910 (reverted in #213088) with the fix for the breakage.
IsIntegratedBackendDefault() was tied to whether the SPIR-V backend is
registered, but it also controls whether clang collapses the compile and
backend
jobs, so builds without the SPIR-V target split every HIPSPV RDC device
compile
and failed hipspv-toolchain-rdc.hip. The default is back to the base
class value
and the translator fallback is decided in
constructLinkAndEmitSpirvCommand.
Third commit adds a test not guarded by spirv-registered-target.
Validated in X86;SPIRV and X86 only builds: driver tests pass in both,
and
non-RDC plus RDC (new driver) flows run for real emit spirv-val clean
modules
via the backend and via llvm-spirv respectively.
NAS-141823 / 27.0.0-BETA.1 / Allow running disabled replication tasks (#19419)
Previously, disabled replication tasks were excluded from zettarepl
configuration. Now we include them, but we don't let them run
automatically.
[SLP]Fix miscompile from poison base in alias-check versioning
Emit the runtime alias check while the block is still fully connected.
LCSSA-preserving SCEV expansion rewrites out-of-loop uses of
loop-defined bases to poison in predecessor-less blocks, corrupting
both the moved body and the scalar fallback clone.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/213338
CSKY: Consume "float-abi" module flag (#212975)
Start respecting float-abi, and fall back on the TargetOptions
field if not present.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[CIR][AMDGPU] Add support for AMDGCN tanh builtins (#197852)
Adds codegen for the following AMDGCN tanh builtins:
- __builtin_amdgcn_tanhf (float)
- __builtin_amdgcn_tanhh (half)
- __builtin_amdgcn_tanh_bf16 (bfloat16)
These are lowered to the corresponding `llvm.amdgcn.tanh` intrinsic.
[CIR][AMDGPU] Add support for AMDGCN trig_preop builtins (#197399)
Adds codegen for the following AMDGCN trigonometric pre-operation
builtins:
- __builtin_amdgcn_trig_preop (double)
- __builtin_amdgcn_trig_preopf (float)
These are lowered to the corresponding `llvm.amdgcn.trig.preop`
intrinsic.
DAG: Skip poison elements in BUILD_VECTOR computeKnownBits
This defends against regressions in future patches. Copies the logic
from the IR version of computeKnownBits's handling of ConstantVector.
I'm not sure why the IR version doesn't directly return a value for poison,
but this follows suit.
Co-authored-by: Claude (Claude-Opus-4.8)
Merge tag 'spi-fix-v7.2-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"The drip of driver specific fixes, mostly from the device vendors
themselves, keeps on coming in. There's more than I'd like right now
but equally nothing hugely alarming"
* tag 'spi-fix-v7.2-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: spi-nxp-fspi: propagate clock reconfig failures in nxp_fspi_select_mem()
spi: spi-nxp-fspi: enter stop mode before reconfiguring MCR0 and DLL
spi: spi-nxp-fspi: add per-SoC SDR/DTR clock rate limits for all supported SoCs
spi: spi-qpic-snand: write the feature value before executing SET_FEATURE
spi: spi-cadence: Move TX FIFO full busy-wait into FIFO
spi: qcom-qspi: Correct max DMA length to avoid 64K boundary failure
spi: spacemit: prepare both DMA descriptors before submitting
[X86] Don't emit personality info when the personality is not a function (#212803)
Follow-up to #212417, another one in the same corner.
`llc -mtriple=x86_64-pc-windows-msvc` crashes on a function whose
personality isn't a function:
```llvm
define void @a() personality ptr null {
ret void
}
```
`dyn_cast<Function>` gives null, and `beginFunclet` hands that straight
to `getSymbol`, which dereferences it.
`DwarfCFIException` already guards against this, applying the null check
to both branches:
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net/fort: Update to 1.7.0.experimental
- Update to 1.7.0.experimental
- Changelog:
https://github.com/NICMx/FORT-validator/releases/tag/1.7.0.experimental
Please note that max-rtr-version defaults to zero. This is because
Fort's validation currently yields no router keys (defeating the purpose
of RTRv1), and the RTRv2 specification is still receiving updates.
The latter is all the ".experimental" suffix refers to. If you raise
max-rtr-version to 2, you'll be trying a feature that hasn't been RFC'd
yet.
(cherry picked from commit 4839e2b8d1026ae7f359c5b96ae8c8fff589064e)
[flang][NFC] move addPass* template utilities to header (#213288)
Move the addPass* template utilities to the header so external pipelines
can use them.
AMDGPU: Export the TargetParser feature bitset
Previously this bitset was only used to populate the feature
name string map used by clang. Eventually this will replace
the current bitmask integer. AArch64 already has a similar
interface.
Co-authored-by: Claude (Claude-Opus-4.8)
