[lldb] Make ScriptedPythonInterface::Dispatch return llvm::Expected<T> (#224988)
Until now, `Dispatch` returned the extracted value and reported failure
through a `Status &` out-parameter, which leaves the two outcomes
indistinguishable at the value level: a Python method that returns
`None` and one that raises both hand back a default-constructed `T`.
Only `error` told them apart, and because the signature advertises the
value, call sites reached for the value and dropped the error.
Three real instances of that:
- `ScriptedHookPythonInterface::HandleStop` returned `true` whenever the
object was null, discarding the backtrace of a raising `handle_stop`
(fixed separately).
- `GetStatusFromMethod` discarded `Dispatch<Status>`'s return value, so
the `SBError` returned by `ScriptedProcess.launch/attach/resume` and the
three `ScriptedPlatform` entry points was ignored entirely: a `launch()`
returning `SBError("no such file")` reported success.
- `GetThreadPlanMetadataForStepType` string-matched the exception text
[28 lines not shown]
[AMDGPU][InstCombine] Fold zero dot operands to accumulator
Fold AMDGPU dot intrinsics when either operand is zero.
`dot(a, 0) = 0` and `dot(0, b) = 0`, so replace the intrinsic with its accumulator.
This avoids unrelated clamp and add/sub reassociation cases.
[AMDGPU][InstCombine] Canonicalize dot constant operands
Move constant dot product source operands to the right hand side
and add tests for signed and unsigned dot intrinsics.
[AMDGPU][InstCombine] Fold constant add/sub into the dot accumulator
`amdgcn.{s,u}dot{2,4,8}(a, b, C) +/- K -> dot(a, b, C +/- K)` when both the
accumulator C and K are constants. The new constant is computed with
wrapping APInt arithmetic to match the non-clamping accumulate.
Only applies when clamp is false (the saturating accumulate does not
reassociate) and the dot has a single use. K - dot is left alone since it
would need the dot product negated.
[HLSL] Add `InterlockedMax` function and resource methods (#222160)
This PR adds the `InterlockedMax` standalone function and resource
methods.
It mimics the implementation of the `InterlockedMin` function and
resource
methods.
Like `min`, `max` is signedness aware. A signed operand lowers to
`atomicrmw max` and an unsigned operand lowers to `atomicrmw umax`. This
matches DXC, which selects between the `IMax` and `UMax` atomic binary
operations.
The PR also adds the 64-bit `InterlockedMax64` methods, which DXIL gates
on
shader model 6.6.
Fixes: https://github.com/llvm/llvm-project/issues/99124
Assisted by: Github Copilot
[Offloading] Add support for compressed OffloadBinary types
Summary:
Offload binaries are used to store many heterogenous architectures into
a singel offloading blob. These lists can get very large so this PR adds
the option to compress them with the LLVM provided compression
libraries.
The implementation is quite simple, we simply compress all the buffers
after the header into a single compressed blob, then re-construct the
header. Extracting is the reverse.
The biggest change is that the offload binary now **owns** the memory,
whereas before we simply took a reference to it. This is necessary
because the decompression must create new memory compared to what the
user provided. This adds an extra copy internally, but it also
simplifies the V2 additions.
This does not wire up any clang/HIP support, just providing the
functionality.
[Support] Infer compression format from zlib and zstd headers
Summary:
Identify compressed streams from their bitstream headers so callers can
decompress without naming the format. Recognize every valid RFC 1950
zlib header and the zstd frame magic, and reuse that for
getReasonIfUnsupported and decompress. Collapse the AST reader onto the
new helpers.
[AMDGPU] Add MemoryPipeline scheduling to Coexec sched (#192325)
This adds two pieces to the new scheduler:
Stalls between ds_load and fence
tryAsyncPipe
For both of these pieces we are making some assumptions about the
pipelining of memory instructions in the incoming IR. Namely, that the
long latency memory operations are pipelined and the shorter latency
memory operations (e.g. ds_loads) aren't. Moreover, this assumes that
any user added waitcnts appear directly before fences. These assumptions
are compensating for the fact that we don't have any analysis of the
pipeline available during scheduling.
Stalls between ds_load and fence
The main concept here is that when legalizing the fences we will insert
wait_dscnts for any outstanding ds_load instructions. By teaching the
scheduler about the stall between these instructions, we can hide
latency between ds_load -> wait_dscnt. A common idiom is:
[22 lines not shown]
Add match syntax rule test
The matching-rules chnage from case-insensitive to case-sensitive depends
on the case, which is strange.
To continue working in this area, here are some tests of the
default "behavior":
- test default glob(7) cookie name/key matching is case-insensitive
- test default glob(7) cookie value matching is case-insensitive
- test default glob(7) header name matching is case-insensitive
- test default glob(7) url lookup is case-insensitive
- test default glob(7) header value matching is case-sensitive
- test default glob(7) path matching is case-sensitive
- test default glob(7) query name/value matching is case-sensitive
- test that an omitted rule value defaults to "*" and matches any value
both with a plain glob(7) and patterns(7)
[2 lines not shown]
[CIR] Consume serialized LangOptions in post-CIRGen lowering (#225224)
Post-CIRGen lowering (LoweringPrepare, CallConvLowering) read a handful
of LangOptions facts from a live clang::LangOptions via the pass's
ASTContext. That prevented a reloaded .cir from lowering the same way it
was compiled, since a serialized module has no ASTContext. PR #224757
serialized those facts onto the module as #cir.lowering_lang_options;
this change makes lowering consume them from there.
To make sure the `lowering_lang_options` attribute is always available,
I moved the constrction of langOpts from release to the constructor. The
overall approach is very close to `LowerModule::getTarget()`
Currently there is still a reliance to `astContext` which I plan to
remove in upcoming PRs. The reliance blocks consuming .cir as an input
and test `cir-opt` with some of such passes.
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
[RISCV] Update the canonical extension order (#192392)
Fixes #192357.
Update the canonical order of one-letter standard RISC-V extensions in
RISCVISAUtils::AllStdExts to match the updated specification order,
where `p` moves after `v`.
vmimage.subr: Include dangling symlinks in images
When creating VM images, we filter the METALOG file created by pkg(8)
when installing non-base packages, rejecting any lines which correspond
to files which don't exist; this solves a problem which arose when a
package was installed and then deinstalled (or upgraded) later in the
image-building process.
Unfortunately [ -e ... ] follows symlinks and is not basedir-aware, so
an absolute symlink which is valid *inside* the image is omitted from
the image if it points to something which isn't present in the build
host system.
Replace [ -e ... ] with [ -e ... ] || [ -L ... ] so that symlinks are
included even if dangling.
While I'm here, add quoting in case future paths become problematic.
Sponsored by: Amazon
MFC after: 3 days
[RISC-V] Test ELF e_flags for llc -target-abi without module flag (#225128)
Verify that `llc -filetype=obj -target-abi=...` sets the ELF header
`e_flags`
according to `-target-abi` even when the input IR has no `"target-abi"`
module
flag and the enabled extensions (such as `+d`) would default to a
different ABI.
This commit was created with the help of AI tools
[CIR] Lowering for the C2Y `stdc` bit builtins (#218852)
Implemented CIR lowering for the C2Y `stdc` bit builtins currently
covered by this PR.
This adds support for:
- `stdc_rotate_left_*` / `__builtin_stdc_rotate_left`
- `stdc_rotate_right_*` / `__builtin_stdc_rotate_right`
- `stdc_memreverse8u8/u16/u32/u64`
- `stdc_memreverse8` / `__builtin_stdc_memreverse8`
The rotate builtins lower to `cir.rotate`, which then lowers to the LLVM
funnel-shift intrinsics.
For `stdc_memreverse8`, CIR matches classic CodeGen behavior:
- sizes `0` and `1` are no-ops, while still evaluating the pointer
argument
[5 lines not shown]
[CIR] Expand callee-side va_arg on x86_64 (#222420)
CallConvLowering now classifies every `cir.va_arg` on its own, as an
unnamed argument with a full register budget, and expands it in place. A
fetch that fits the budget reads from the saved register area, and
everything else reads the overflow area and bumps the cursor. An
aggregate, an x87 long double, and an `__int128` all lower correctly
now. Each fetch reads at the alignment the argument area gives it, which
for an over-aligned record is higher than its type reports.
A non-trivially-copyable type still reports NYI.
`rewriteVAArg` takes the register demand from the ABI library rather
than rebuilding it from the shape of the coerced type. The library
computes it in `classifyArgumentType` as the `NeededInt` and `NeededSSE`
out-parameters and used to drop it, so `llvm::abi::ArgInfo` and
`mlir::abi::ArgClassification` now carry it. Expanding a `cir.va_arg`
needs the inputs to that decision rather than its result, because the
choice has to become a runtime branch on the va_list cursor.
Assisted-by: Cursor / claude-opus-5
