[clang] Tests for CWG1670 and CWG1878: `auto` in conversion functions (#187850)
This PR adds tests for
[CWG1670](https://cplusplus.github.io/CWG/issues/1670.html) "`auto` as
_conversion-type-id_" and
[CWG1878](https://cplusplus.github.io/CWG/issues/1878.html) "`operator
auto` template". The long and short of it is that placeholder type
specifier (`auto`) cannot be used to declare conversion function or
conversion function template. We've always diagnosed template case but
not non-template case.
[clang] Enable part of CWG2598 test in C++20 mode (#189310)
This is a small fix for `#if __cplusplus >= 202002L` condition, which
accidentally disabled this part of the test in C++20 mode.
[libc][math] Refactor dsub family to header-only (#182160)
Refactors the dsub math family to be header-only.
Closes https://github.com/llvm/llvm-project/issues/182159
Target Functions:
- dsubf128
- dsubl
---------
Co-authored-by: bassiounix <muhammad.m.bassiouni at gmail.com>
[LoongArch] Combine rounded vector shifts to VSRLR/VSRAR (#192921)
Add DAG combines to recognize canonical rounded shift patterns and lower
them to target-specific vector rounded shift instructions.
The combines match vector arithmetic and logical right shifts with
rounding implemented as:
```
add (srl/sra X, shift),
(and (srl X, shift-1), 1)
```
and the shift-by-1 variant:
```
add (srl/sra X, 1),
(and X, 1)
```
[13 lines not shown]
[RISCV][GlobalISel] Support RISC-V specific inline asm constraints: 'I', 'J', 'K' and 'S' (#193765)
This patch implements some target-specific constraints for RISC-V: `I`,
`J`, `K` and `S`. These constraints are all for immediate values except
for `S`. The handling of these constraints is implemented with by adding
`RISCVInlineAsmLowering` subclass of `InlineAsmLowering`.
[LoongArch] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector.
On 64-bit targets the generic legalize will use an i64 load and a
scalar_to_vector for us. But on 32-bit targets i64 isn't legal and the
generic legalizer will end up emitting two 32-bit loads.
[LoongArch] Combine rounded vector shifts to VSRLR/VSRAR
Add DAG combines to recognize canonical rounded shift patterns and
lower them to target-specific vector rounded shift instructions.
The combines match vector arithmetic and logical right shifts with
rounding implemented as:
```
add (srl/sra X, shift),
(and (srl X, shift-1), 1)
```
and the shift-by-1 variant:
```
add (srl/sra X, 1),
(and X, 1)
```
[14 lines not shown]
[MC] Change MCContext::getTargetOptions to return a reference. NFC (#194112)
Since #180464, MCAsmInfo stores a non-null MCTargetOptions pointer set
by
TargetRegistry::createMCAsmInfo, and MCContext's constructor asserts
that
MAI->getTargetOptions() is non-null. Return the options by reference
instead of by pointer so callers can drop the null handling.
