FreeBSD/ports 702703fdevel/binaryen distinfo Makefile

devel/binaryen: Update to 128 (bugfix release)

ChangeLog:
https://github.com/WebAssembly/binaryen/compare/version_127...version_128
DeltaFile
+3-3devel/binaryen/distinfo
+1-1devel/binaryen/Makefile
+4-42 files

FreeBSD/ports 779f56ddeskutils/genius Makefile distinfo

deskutils/genius: Update to 1.0.29

- Add sintax highlighting (gtksourceview4)
- Add examples

ChangeLog: https://www.jirka.org/genius.NEWS
DeltaFile
+10-2deskutils/genius/Makefile
+3-3deskutils/genius/distinfo
+13-52 files

LLVM/project 5a3d71dutils/bazel/llvm-project-overlay/mlir BUILD.bazel, utils/bazel/llvm-project-overlay/mlir/test BUILD.bazel

[Bazel] Port 717d1a23c978e5fe25063a4a90ee31652b6912bf
DeltaFile
+4-1utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-1utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
+5-22 files

LLVM/project cbddc40clang/lib/Headers/hlsl hlsl_alias_intrinsics.h

[HLSL] Fix intrinsics header file for wave intrinsics using u/int16_t types, updating them to 6.2 (#186218)

This is actually a surprise part 2 to:
https://github.com/llvm/llvm-project/pull/185757

Fully addresses https://github.com/llvm/llvm-project/issues/185756
DeltaFile
+375-372clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+375-3721 files

LLVM/project 42804a5utils/bazel/llvm-project-overlay/libc BUILD.bazel

[Bazel] Port b7c4615e137815e2577a4795f33a9bcae2416cb8
DeltaFile
+19-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+19-01 files

LLVM/project 4e2bb58llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.ds.swizzle.ll

AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_ds_swizzle (#186024)
DeltaFile
+55-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
+20-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+79-93 files

FreeNAS/freenas 48863fasrc/middlewared/middlewared/plugins/service_/services nfs.py, tests/api2 test_300_nfs.py

Fix NFS CI: wait for nfs-idmapd, reset systemd counters
DeltaFile
+4-0tests/api2/test_300_nfs.py
+1-0src/middlewared/middlewared/plugins/service_/services/nfs.py
+5-02 files

LLVM/project 7f538fdllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.getreg.ll

AMDGPU/GlobalISel: RegBankLegalize rules for s_getreg (#186253)
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
+1-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+6-53 files

Linux/linux 9abff57kernel workqueue.c workqueue_internal.h, samples/workqueue/stall_detector wq_stall.c Makefile

Merge tag 'wq-for-7.0-rc3-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq

Pull workqueue fixes from Tejun Heo:

 - Improve workqueue stall diagnostics: dump all busy workers (not just
   running ones), show wall-clock duration of in-flight work items, and
   add a sample module for reproducing stalls

 - Fix POOL_BH vs WQ_BH flag namespace mismatch in pr_cont_worker_id()

 - Rename pool->watchdog_ts to pool->last_progress_ts and related
   functions for clarity

* tag 'wq-for-7.0-rc3-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq:
  workqueue: Rename show_cpu_pool{s,}_hog{s,}() to reflect broadened scope
  workqueue: Add stall detector sample module
  workqueue: Show all busy workers in stall diagnostics
  workqueue: Show in-flight work item duration in stall diagnostics
  workqueue: Rename pool->watchdog_ts to pool->last_progress_ts
  workqueue: Use POOL_BH instead of WQ_BH when checking pool flags
DeltaFile
+98-0samples/workqueue/stall_detector/wq_stall.c
+28-27kernel/workqueue.c
+1-0samples/workqueue/stall_detector/Makefile
+1-0kernel/workqueue_internal.h
+128-274 files

Linux/linux b073bcbkernel/cgroup cpuset.c cgroup.c

Merge tag 'cgroup-for-7.0-rc3-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup

Pull cgroup fixes from Tejun Heo:

 - Hide PF_EXITING tasks from cgroup.procs to avoid exposing dead tasks
   that haven't been removed yet, fixing a systemd timeout issue on
   PREEMPT_RT

 - Call rebuild_sched_domains() directly in CPU hotplug instead of
   deferring to a workqueue, fixing a race where online/offline CPUs
   could briefly appear in stale sched domains

* tag 'cgroup-for-7.0-rc3-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup:
  cgroup: Don't expose dead tasks in cgroup
  cgroup/cpuset: Call rebuild_sched_domains() directly in hotplug
DeltaFile
+31-28kernel/cgroup/cpuset.c
+6-0kernel/cgroup/cgroup.c
+37-282 files

LLVM/project 717d1a2mlir CMakeLists.txt, mlir/include/mlir/Config mlir-config.h.cmake

[mlir] Replace MLIR_ENABLE_ROCM_CONVERSIONS with LLVM_HAS_AMDGPU_TARGET (#182652)

`LLVM_HAS_NVPTX_TARGET` is already defined in `llvm/Config/Targets.h`
and used to gate NVPTX-related code in MLIR. The same macro exists for
AMDGPU as `LLVM_HAS_AMDGPU_TARGET`, but MLIR defined its own
`MLIR_ENABLE_ROCM_CONVERSIONS` variable for this purpose. This PR
removes `MLIR_ENABLE_ROCM_CONVERSIONS` and replaces it with
`LLVM_HAS_AMDGPU_TARGET`, bringing parity with the NVPTX target.

---------

Co-authored-by: William Moses <gh at wsmoses.com>
DeltaFile
+6-5mlir/lib/Target/LLVM/ROCDL/Target.cpp
+0-8mlir/CMakeLists.txt
+0-4mlir/include/mlir/Config/mlir-config.h.cmake
+2-2mlir/lib/Target/LLVM/CMakeLists.txt
+2-1mlir/unittests/Target/LLVM/SerializeROCDLTarget.cpp
+1-1mlir/test/lit.site.cfg.py.in
+11-212 files not shown
+13-238 files

LLVM/project c9a2f0bllvm/include/llvm/Transforms/Utils UnrollLoop.h, llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp

[LoopUnroll] Remove `computeUnrollCount()`'s return value  (#184529)

`computeUnrollCount()`'s return value is used to communicate whether
unrolling was explicitly requested. However, each of
`computeUnrollCount()`'s two callers can compute this directly:

- `LoopUnrollAndJamPass` already checks for loop unrolling metadata
[before calling
`computeUnrollCount()`](https://github.com/llvm/llvm-project/blob/43dbcdea98f5bb04ae967bdd81ece2d2144f4661/llvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp#L308).
The return value only added handling for `-unroll-count`, a testing flag
with no UnrollAndJam test coverage.

- `tryToUnrollLoop()` can use `PragmaInfo(L).ExplicitUnroll` directly at
the `setLoopAlreadyUnrolled()` call site.
- In all but one case where `computeUnrollCount()` explicitly `return`s
`false` instead of `ExplicitUnroll`, `UP.Count = 0` is set. This causes
`tryToUnrollLoop()` to early-exit before reaching
`setLoopAlreadyUnrolled`.
- The remaining case that `return`s false, but does not set `UP.Count =

    [7 lines not shown]
DeltaFile
+75-54llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+0-31llvm/lib/Transforms/Utils/LoopUnroll.cpp
+10-14llvm/include/llvm/Transforms/Utils/UnrollLoop.h
+3-12llvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
+2-3llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+90-1145 files

LLVM/project 9210b3aclang/lib/Headers/hlsl hlsl_alias_intrinsics.h, clang/lib/Sema SemaHLSL.cpp

[HLSL][DirectX] Add `transpose` HLSL intrinsic and DXIL lowering of `llvm.matrix.transpose` (#186263)

Fixes #184922

- [x] Implement `transpose` clang builtin in `Builtins.td`
- [x] Link `transpose` clang builtin with `hlsl_alias_intrinsics.h`
- [x] Add sema checks for `transpose` to `CheckHLSLBuiltinFunctionCall`
in `SemaHLSL.cpp`
- [x] Add codegen for `transpose` to `EmitHLSLBuiltinExpr` in
`CGHLSLBuiltins.cpp`
  - `transpose` lowers to the `llvm.matrix.transpose` intrinsic
- [x] Add codegen tests to
`clang/test/CodeGenHLSL/builtins/transpose.hlsl`
- [x] Add sema tests to
`clang/test/SemaHLSL/BuiltIns/transpose-errors.hlsl`
- [x] Implement lowering of the `llvm.matrix.transpose` intrinsic in the
DXIL backend in `DXILIntrinsicExpansion.cpp`
- The intrinsic lowers to a shufflevector like in DXC
https://hlsl.godbolt.org/z/Gj959q6sq

    [3 lines not shown]
DeltaFile
+65-0llvm/test/CodeGen/DirectX/matrix-transpose.ll
+42-0clang/test/CodeGenHLSL/builtins/transpose.hlsl
+32-0clang/test/SemaHLSL/BuiltIns/transpose-errors.hlsl
+21-0llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
+19-0clang/lib/Sema/SemaHLSL.cpp
+17-0clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+196-02 files not shown
+209-08 files

FreeBSD/ports 4f22c19graphics/libplacebo distinfo Makefile

graphics/libplacebo: update to 7.360.1

Changes:        https://code.videolan.org/videolan/libplacebo/-/tags/v7.360.1
Reported by:    GitHub (watch releases)
DeltaFile
+7-7graphics/libplacebo/distinfo
+3-3graphics/libplacebo/Makefile
+10-102 files

LLVM/project 305dc4emlir/lib/Dialect/Vector/Transforms LowerVectorGather.cpp, mlir/test/Dialect/Vector vector-gather-lowering.mlir

[mlir][vector] Lower vector.gather with delinearization approach (#184706)

The old implementation did not handle n-D memref correctly, which leads
to wrong access. E.g.,

```
 func.func @gather_memref_2d(%base: memref<?x?xf32>, %v: vector<2x3xindex>, %mask: vector<2x3xi1>, %pass_thru: vector<2x3xf32>) -> vector<2x3xf32> {
  %c0 = arith.constant 0 : index
  %c1 = arith.constant 1 : index
  %0 = vector.gather %base[%c0, %c1][%v], %mask, %pass_thru : memref<?x?xf32>, vector<2x3xindex>, vector<2x3xi1>, vector<2x3xf32> into vector<2x3xf32>
  return %0 : vector<2x3xf32>
 }
```

is lowered to

```
  func.func @gather_memref_2d(%arg0: memref<?x?xf32>, %arg1: vector<2x3xindex>, %arg2: vector<2x3xi1>, %arg3: vector<2x3xf32>) -> vector<2x3xf32> {
    %c0 = arith.constant 0 : index

    [26 lines not shown]
DeltaFile
+74-3mlir/test/Dialect/Vector/vector-gather-lowering.mlir
+49-9mlir/lib/Dialect/Vector/Transforms/LowerVectorGather.cpp
+6-1mlir/test/Dialect/XeGPU/xegpu-vector-linearize.mlir
+2-2mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
+131-154 files

LLVM/project b7c4615libc/src/stdio/printf_core string_converter.h CMakeLists.txt, libc/test/src/stdio sprintf_test.cpp

[libc] Support ls in printf (#178841)

Add support for %ls in printf by calling internal string converter and
add relevant end-to-end sprintf test. Additionally, modified printf
parser for recognizing length modifier. This also disables wide string
support on windows
and other unsupported platforms.

Co-authored-by: shubhe25p <shubhp at mbm3a24.local>
DeltaFile
+103-0libc/test/src/stdio/sprintf_test.cpp
+86-7libc/src/stdio/printf_core/string_converter.h
+4-0libc/src/stdio/printf_core/CMakeLists.txt
+1-1libc/src/stdio/printf_core/parser.h
+194-84 files

Linux/linux 8369b2eDocumentation/scheduler sched-ext.rst, kernel/sched ext_internal.h ext.c

Merge tag 'sched_ext-for-7.0-rc3-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/sched_ext

Pull sched_ext fixes from Tejun Heo:

 - Fix data races flagged by KCSAN: add missing READ_ONCE()/WRITE_ONCE()
   annotations for lock-free accesses to module parameters and dsq->seq

 - Fix silent truncation of upper 32 enqueue flags (SCX_ENQ_PREEMPT and
   above) when passed through the int sched_class interface

 - Documentation updates: scheduling class precedence, task ownership
   state machine, example scheduler descriptions, config list cleanup

 - Selftest fix for format specifier and buffer length in
   file_write_long()

* tag 'sched_ext-for-7.0-rc3-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/sched_ext:
  sched_ext: Use WRITE_ONCE() for the write side of scx_enable helper pointer
  sched_ext: Fix enqueue_task_scx() truncation of upper enqueue flags

    [7 lines not shown]
DeltaFile
+98-16kernel/sched/ext_internal.h
+27-3Documentation/scheduler/sched-ext.rst
+11-11kernel/sched/ext.c
+2-2tools/testing/selftests/sched_ext/util.c
+138-324 files

LLVM/project 55e626cclang/lib/CIR/Dialect/Transforms/TargetLowering/Targets AMDGPU.cpp

Add table-based CIR -> Target AS mapping
DeltaFile
+17-18clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
+17-181 files

LLVM/project a4e6d84llvm/lib/Target/AArch64 AArch64SystemOperands.td

[AArch64][llvm] Rewrite the TLBI multiclass to be much clearer (NFC)

The `tlbi` multiclass is really doing four jobs at once: base TLBI,
synthesized nXS, optional TLBIP, and synthesized TLBIP nXS. Also,
`needsreg` and `optreg` are really just a 3-state operand policy in
disguise. Likewise, the PLBI multiclass has this same issue.

Change `needsreg` and `optreg` into a combined fake enum, so it's
clearer whether the instruction takes no register operand, a required
register operand or an optional register operand.

This improves on my original change 66e8270e8.
DeltaFile
+127-121llvm/lib/Target/AArch64/AArch64SystemOperands.td
+127-1211 files

LLVM/project 836421allvm/include/llvm/IR Intrinsics.td, llvm/test/Transforms/Coroutines coro-async-noduplicate.ll

[coro] [async] There needs to be a one-to-one corespondance between the async resume function value and the suspend intrinsic (#186436)

We need to mark both the async.resume intrinsic function and the
supsend.async function as not duplicatable. The async.resume function
models the continuation after a suspend. It is non sense to not have a
one-to-one correspondance between the two: if the suspend intrinsic is
cloned so needs to be the matching async.resume intrinsic call.

rdar://172130181
https://github.com/swiftlang/swift/issues/87719
DeltaFile
+90-0llvm/test/Transforms/Coroutines/coro-async-noduplicate.ll
+2-2llvm/include/llvm/IR/Intrinsics.td
+92-22 files

LLVM/project 01571f1llvm/lib/CodeGen CodeGenPrepare.cpp ExpandMemCmp.cpp, llvm/lib/Target/AMDGPU AMDGPUUnifyDivergentExitNodes.cpp SIAnnotateControlFlow.cpp

[CodeGen] Drop uses of BranchInst (#186391)

Largely a straight-forward replacement with occasional simplifcations.

For AMDGPU, I assumed that unconditional branches are always uniform and
therefore "simplified"/changed AMDGPUAnnotateUniformValues to only
annotate conditional branches.

Target-specific FastISel only selects conditional branches,
unconditional branches are already handled by the non-target-specific
code.
DeltaFile
+43-44llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+20-22llvm/lib/CodeGen/CodeGenPrepare.cpp
+18-21llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
+15-15llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
+6-13llvm/lib/CodeGen/ExpandMemCmp.cpp
+4-11llvm/lib/CodeGen/HardwareLoops.cpp
+106-12629 files not shown
+168-21435 files

LLVM/project 20d7ae2clang/include/clang/Basic AttrDocs.td

Remove unicode character from AttrDocs.td

PR #185225 introduced a single unicode character, which is the only
unicode character in this file. Change this to a ASCII/Latin1 letter.
DeltaFile
+1-1clang/include/clang/Basic/AttrDocs.td
+1-11 files

LLVM/project 8885c37llvm/test/CodeGen/AMDGPU local-stack-alloc-add-references.gfx8.mir coalesce-copy-to-agpr-to-av-registers.mir, llvm/test/CodeGen/AMDGPU/GlobalISel irtranslator-inline-asm.ll

[AMDGPU] Remove unused regclass SGPR_HI16. NFCI. (#186431)
DeltaFile
+180-180llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
+120-120llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
+90-90llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
+18-18llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
+15-15llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
+439-43921 files not shown
+530-53827 files

OpenBSD/ports wxCnd9jgames/pokerth Makefile distinfo, games/pokerth/patches patch-src_net_clientstate_cpp patch-src_gui_qt6-qml_CMakeLists_txt

   update to pokerth-2.0.6, from Josh Grosse (maintainer)
   small tweaks, move WANTLIB to the usual location, drop RelWithDebInfo
   as DEBUG_PACKAGES sets this automatically on debug pkgs archs
VersionDeltaFile
1.60+16-21games/pokerth/Makefile
1.1+14-0games/pokerth/patches/patch-src_net_clientstate_cpp
1.1+9-0games/pokerth/patches/patch-src_gui_qt6-qml_CMakeLists_txt
1.13+2-2games/pokerth/distinfo
1.16+4-0games/pokerth/pkg/PLIST
1.2+0-0games/pokerth/patches/patch-src_game_defs_h
+45-231 files not shown
+45-237 files

LLVM/project 44eed39flang/lib/Lower OpenACC.cpp, flang/test/Lower/OpenACC acc-terminator.f90

[flang][openacc][cuda] Fix array section and implicit device attribute (#186513)

When CUDA Fortran is enabled, the copySymbolBinding block in
genACCHostDataOp did not handle ArrayElement designators (e.g.,
use_device(a(:,:,i))), causing a crash in getDataOperandBaseAddr
due to the copied symbol missing its IR binding.
DeltaFile
+5-0flang/lib/Lower/OpenACC.cpp
+1-0flang/test/Lower/OpenACC/acc-terminator.f90
+6-02 files

LLVM/project 7359b5dllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Typo

Change-Id: I8b8da8a07be84506483f474d0a5e10ad79178c15
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+1-11 files

LLVM/project 8e29cf6llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

[AMDGPU] Add stalls for DS FIFO buffer

Change-Id: I73e56da97a931349e0655e4e20b24aeb97920647
DeltaFile
+56-53llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+58-25llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+41-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+155-843 files

LLVM/project 0364298lldb/source/Plugins/SymbolLocator/Debuginfod CMakeLists.txt

[lldb] Fix liblldb linkage in libllvm build after 5eaf19a15129 (#186515)

Referencing libSupportHTTP under LINK_LIBS of add_lldb_library() pulls
in the archive even in a build configuration with
LLVM_LINK_LLVM_DYLIB=On, where libSupportHTTP is part of libLLVM. This
patch moves it to LINK_COMPONENTS to fix the issue.
DeltaFile
+3-1lldb/source/Plugins/SymbolLocator/Debuginfod/CMakeLists.txt
+3-11 files

FreeBSD/src 277830brelease/tools ec2.conf

EC2: Don't use unicode in boot loader

The boot loader menu is disabled by default in EC2, but if it is ever
turned on, the default (unicode) output breaks EC2's web interface to
the serial console.

Set loader_menu_frame="ascii" instead.

MFC after:      3 days
Sponsored by:   Amazon
DeltaFile
+3-1release/tools/ec2.conf
+3-11 files

NetBSD/pkgsrc tu3pN5owww/hiawatha options.mk

   Update version of external mbedtls to v4

   Build option does not currently work, because the security/mbedtls4
   package does not enable MBEDTLS_THREADING_PTHREAD and
   MBEDTLS_THREADING_C.
VersionDeltaFile
1.7+3-3www/hiawatha/options.mk
+3-31 files