[libc] Fix EOF handling in fscanf (#211982)
`fscanf` family of functions should return EOF if:
- end of input is reached before either the first successful conversion
or a matching failure occurs;
- a read error occurs.
This wasn't handled correctly before - in "system FILE" mode (in overlay
build) `EOF` return value from `getc` was passed through to parser,
violating `Reader` interface, which triggered infinite loops on
"while-not-EOF" `fscanf` loops. In llvm-libc-FILE mode `fscanf` simply
returned zero instead of EOF, because the code only checked error
indicator on a stream.
This PR removes _any_ lookups of eof/error indicators on an input stream
- instead we can simply rely on the `getc` (system or internal) function
behavior, which returns `EOF` on unsuccessful reads.
Extend the test cases for `fscanf` to cover various return values in
cases when `EOF` is reached (before or after conversions / matching
errors).
Tracks source location of the selector name within ObjCSelectorExpr (#211623)
Store selector name location alongside the existing @-sign and paren locations, exposed via getSelectorLoc(), so tools and diagnostics can reference the name rather than the @selector keyword. While here, rename things to disambiguate locations.
[VPlan] Strip dead code in optimizeEarlyExitIndUser (NFC) (#212463)
The check is already present in getOptimizableIVOf, and is an
impossiblity in the IVInc case.
[MIR2Vec] Handle registers without a register class (#212280)
getRegisterOperandIndex() hit an llvm_unreachable for registers in no
register class. That is a supported outcome, not an error: tablegen
emits InvalidRegClassID for such registers and getMinimalPhysRegClass()
returns nullptr. It hits classless physregs (X86 $mxcsr/$fpcw, AMDGPU
$mode), which crashed any function with FP math, and generic vregs
before ISel, where MRI.getRegClass() asserts -- so use
getRegClassOrNull().
Return std::nullopt instead. Both callers already handle the analogous
NoRegister and stack-slot cases, so the vocabulary layout is unchanged.
We could avoid the special casing by adding a special value for such
registers. It would actually hold some meaningful information for
models. I didn't include it in this patch since it would require seed
vocab re-generation.
[clang][CodeGen] Skip deleted globals in emitUsed (#210959)
A global on the `llvm.used`/`llvm.compiler.used` list can be deleted
before the module is released: CodeGen erases an unreferenced
`GlobalValue` without RAUW when the same mangled name is redefined with
a different type (`GetOrCreateLLVMGlobal`), which nulls the
`WeakTrackingVH` on the used list — value handles are not uses, so the
`use_empty()` guard does not protect them.
In whole-TU compilation this is unobservable because the accompanying
`err_duplicate_mangled_name` suppresses `Release()`. The incremental
interpreter, however, clears the diagnostic state after the failed parse
and keeps building the same module, so the next successful parse runs
`Release()` and crashes in `emitUsed` dereferencing the dead handle:
```
clang-repl> __attribute__((used)) int a asm("sym") = 1; float b asm("sym") = 2.0f;
clang-repl> int ok = 0;
clang-repl: .../ValueHandle.h:95: llvm::Value& llvm::ValueHandleBase::operator*() const: Assertion `V && "Dereferencing deleted ValueHandle"' failed.
[14 lines not shown]
[TableGen] Treat carriage return as line end in prepSkipRegion (#212411)
`prepSkipRegion` currently only treats newline and EOF as end of line.
However, in the TableGen Programmer's Reference:
LineEnd ::= newline | return | EOF
So carriage return is a valid end-of-line, but `prepSkipRegion` ignores
it and skips code after the carriage return that it shouldn't. This
change fixes the end-of-line check in `prepSkipRegion` so that it also
treats carriage return as end of line.
Related issue: #151476.
18290 add .$EXTEND to .gitignore
Reviewed by: Michael van der Westhuizen <r1mikey at gmail.com>
Reviewed by: Bill Sommerfeld <sommerfeld at hamachi.org>
Approved by: Gordon Ross <gordon.w.ross at gmail.com>
[CIR] Disallow mem2reg for volatile/atomic loads and stores (#212262)
Current mem2reg implementation for `cir.load` and `cir.store` does not
check whether the load/store is volatile or atomic. Fix this.
[AMDGPU] Stop iDot4 chain walker at non-ADD nodes (#198412)
The loop body in performAddCombine dot4 matcher unconditionally treats
TempNode operands as the next link's addends, so the chain only works
when TempNode is an `ISD::ADD`
The old getNumOperands() guard let AND/OR/XOR/etc. through, leaking
their non-addend operands (e.g. a constant mask) into the dot4
accumulator and miscompiling kernels
pmc_dmc620: drop unneeded includes
Neither of these options are checked in the file and cdefs.h should not
be included explicitly. No functional change.
Sponsored by: The FreeBSD Foundation
[flang] Stop running array-value-copy in the default pipeline (#211816)
Since the removal of the legacy expression lowering (#210385, #210621,
#210639, #210873), nothing in flang produces the array-value operations
(fir.array_load and friends) that the array-value-copy pass legalizes,
so the pass runs as a guaranteed no-op on every function. Remove it from
the default pipeline (addAVC and the disable-avc mlir option); the pass
itself and its fir-opt tests remain and still run via fir-opt
--array-value-copy.
The array-value operations themselves and the pass are planned for
removal in follow-up patches.
flang/test/Fir/arrexp.fir is deleted rather than updated: it feeds
legacy array-value ops through tco's full pipeline, which no longer
legalizes them (the ops have no codegen patterns), and the file
exercises no live feature beyond that legalization.
Assisted-by: AI
lang/konoha: Disable OpenGL/GLUT. It is not buildable.
* Use devel/cmake/build.mk instead of USE_CMAKE.
* Minimum CMake is 3.10 to suppress warnings.
* Bump PKGREVISION.
libpmc: userland support and pmc.rapl.3 for the RAPL class
Register PMC_CLASS_RAPL in libpmc: event table, allocator, class-table
descriptor, and the event-name/class-listing lookups, all x86-guarded
and modeled on the TSC class. Energy events are read-only and
unqualified. The class prefix (RAPL-) supplies the friendly spelling, so
pmcstat -S rapl-energy-pkg resolves to the canonical ENERGY_PKG event.
Add a pmc.rapl.3 manual page documenting the events, counter scope, the
microjoule unit and wrap handling, and the NUMA/package domain mapping;
link it from pmc.3.
Reviewed by: mhorne
Discussed with: Ali Mashtizadeh <ali at mashtizadeh.com>
Sponsored by: AMD
Differential Revision: https://reviews.freebsd.org/D58029
hwpmc: add RAPL energy-counter class (AMD + Intel)
Add hwpmc_rapl.c/.h implementing PMC_CLASS_RAPL, a read-only
system-scope class modeled on TSC and wired into x86 AMD and Intel MD
init. A per-vendor MSR table covers AMD/Hygon and Intel; energy is
reported in microjoules, with the Intel server 2^-16 J DRAM unit
handled and 32-bit wraps recovered into a 64-bit accumulator.
The overflow guard follows the PMC lifetime: armed on the first
allocated PMC, callout_drain()d on the last release, and each tick only
rendezvouses CPUs holding one. Per-CPU spin locks guard the accumulator
against torn reads on i386. PMC_CAP_DOMWIDE lets pmcstat(8) allocate
one counter per NUMA domain instead of per CPU.
Reviewed by: mhorne, Ali Mashtizadeh <ali at mashtizadeh.com>
Sponsored by: AMD
Differential Revision: https://reviews.freebsd.org/D58028
x86: add AMD RAPL MSR definitions to specialreg.h
specialreg.h is the tree's MSR registry and already carries the Intel
RAPL group. Add the AMD RAPL package/core energy and unit MSRs here so
the hwpmc RAPL class can reference them without a private driver copy.
Use the names Linux's msr-index.h gives these registers.
Reviewed by: mhorne, adrian, Ali Mashtizadeh <ali at mashtizadeh.com>
MFC after: 3 days
Sponsored by: AMD
Differential Revision: https://reviews.freebsd.org/D58027
[offload][lit] Run check-offload-unit as part of check-all (#212513)
I tried to do `check-offload` instead but that
[caused](https://github.com/llvm/llvm-project/pull/212500) a bloodbath,
so just enable `check-offload-unit` as part of `check-all`.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
