[RISCV] Account for the size of the constant pool in getConstantPoolLoadCost() with CostKind == CodeSize (#228134)
Constant pool contributes to the overall binary size.
riscv: support the new "riscv,isa-extensions" string-array.
Support the new "riscv,isa-extensions" property on RISC-V hart nodes
in FDT.
The "riscv,isa" property is deprecated, but cannot be removed because
doing so would break compatibility with existing DTBs. The new properties
replace it: "riscv,isa-base" describes the base ISA and
"riscv,isa-extensions" is a string array containing the supported ISA
extensions.
The "riscv,isa-extensions" property can be relatively large; on the
Spacemit K3 SoC it is approximately 300 bytes.
The FreeBSD OFW interface does not provide access to the underlying FDT
property data without copying it, and memory allocation is not possible
this early. So allocate a static buffer for the property instead.
Reuse the existing parse_riscv_isa() implementation to parse both the new
[5 lines not shown]
AMDGPU/GlobalISel: Split 4-byte aligned 64-bit LDS accesses on SI
SI cannot use ds_read2_b32/ds_write2_b32 for 4-byte aligned 64-bit
accesses due to the LDS bounds checking bug with negative base
addresses, and the selection patterns for them require
HasUsableDSOffset. The explicit legality rules still treated these as
legal, so they failed to select. Split them into 32-bit accesses as
SelectionDAG does, and enable the GFX6 run lines in the local load and
store tests.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[mlir][Vector] Guard scalable reduction dim in matmul lowering (#226024)
`ContractionOpToMatmulOpLowering` previously rejected scalable
`vector.contract` ops by checking only the result type. While this
covers the M and N dimensions, it misses the K (reduction) dimension.
For contractions with static M/N but a scalable K (e.g.,
`vector<2x[4]xf32>` times `vector<[4]x3xf32>`), the guard incorrectly
passed. The pattern then attempted to build a flattened, non-scalable
LHS/RHS type via `VectorType::get(lhsType.getNumElements(), ...)`,
followed by a `vector.shape_cast`. This caused the `shape_cast` verifier
to reject the conversion (source has a scalable dimension, result
doesn't), crashing the pass instead of gracefully failing the match.
Also check the LHS/RHS operand types for a scalable dimension, and add a
regression test.
[Clang] Fix crash on `__atomic_always_lock_free` with a size of zero (#229031)
Fixes #170139
Fixes #120082
`CharUnits::isPowerOfTwo()` returned true for zero, so the lock-free
builtins took a size of 0 for a lock-free size and went on to build
`llvm::Align(0)` from it when the pointer argument was a constant.
Without assertions the answer depended on how the pointer was written.
`isPowerOfTwo()` now returns false for zero and negative quantities, as
its comment says. A size of 0 is handled like any other size that isn't
lock-free, such as 3: `__atomic_always_lock_free` is false, and
`__atomic_is_lock_free` and `__c11_atomic_is_lock_free` are left to the
runtime call, as in GCC. The ObjC property code keeps a zero-size ivar
on its native path.
LLM tools (Gemini 3.1 Pro, not Agent) were used for this contribution.
I've reviewed, built, and tested the change myself before pushing to
GitHub.
[flang][OpenMP] Switch clause verification to descriptor-based
Delete all the scattered pieces of clause verification that are now
replaced by the unified handling.
[flang][OpenMP] Improve diagnostics about modifier properties
Use OpenMPDeprecated and OpenMPFuture warning categories for modifier
diagnostics as well, analogously to how they are used for clauses.
[flang][OpenMP] Account for using different versions for modifier checks
When a modifier from a past/future version is accepted, use its properties
from the nearest version in which it is allowed.
[flang][OpenMP] Create generic interfaces for "container" entities
In short, clauses are containers of modifiers, and directives are
containers of clauses. With the abstractions in place, clauses and
modifiers look almost the same from the point of view of syntactic
properties.
Use these functions to implement generic GetAllowedElements and
GetElementVersionRange functions.
[flang][OpenMP] Properly use GetAllowedElements
Allowed elements are not just those explicitly listed, but also those
from the union of allowed sets.
For example, the set of modifiers allowed on a clause are those that
are listed on a given clause, plus the union of all modifier sets that
the clause allows.
[lldb-dap] Mark unwritable variables as read-only (#229121)
Use SBValue::CanSetValue to add the "readOnly" presentation hint, so
clients don't offer to edit values with no writable storage, like
constants in optimized code.
rdar://181750474
AMDGPU: Fix SILoadStoreOptimizer dropping gds bit on DS merges
When forming read2/write2 from a pair of DS_READ/DS_WRITE
instructions, the gds operand was unconditionally set to 0, turning
GDS accesses into LDS accesses. Preserve the gds bit, refuse to pair
an LDS access with a GDS access, and select the M0-reading opcode
variant for GDS on targets that otherwise use the _gfx9 forms.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[lldb][NativePDB] Require native for thread locals (#229480)
Skips the test for builds that are not native and intends to fix the
still broken bot after #229340.
The test shouldn't require `native`, but, as I mentioned in the comment,
it seems like the linking in `build.py` doesn't set the correct
architecture or the build doesn't happen on the correct target. Either
way, I can't debug this locally, so this configuration is skipped.
hwpmc: handle delayed IBS NMIs on Zen 6
On Zen 6, an extra IBS NMI can arrive after later samples. Keep the
credit until the empty NMI arrives, and handle fetch and op samples when
both are ready.
Reviewed by: mhorne
Fixes: 34b00ed041a4 ("hwpmc: fix IBS fetch and op NMI handling")
Fixes: e51ef8ae490f ("hwpmc: Initial support for AMD IBS")
Sponsored by: AMD
Differential Revision: https://reviews.freebsd.org/D60367
pmc.h: bump PMC_VERSION_MINOR
Bump for the addition of PMC_OP_GETCAPS and the recently added Intel
CPUs.
Sponsored by: The FreeBSD Foundation
(cherry picked from commit e39d3a6b32331437da6c13a4aeb67e5bcca67625)
libpmc: Query hwpmc for caps
This change allows for fine-grained capabilities per counter index. This
is particularly useful for AMD where subclasses are not exposed to the
general PMC code, but other architectures also have asymmetric behaviors
when it comes to specific counter indices.
A new PMC_OP_GETCAPS op is added to the hwpmc(4) ioctl interface.
Reviewed by: mhorne
Sponsored by: Netflix
Pull Request: https://github.com/freebsd/freebsd-src/pull/2058
(cherry picked from commit 44a983d249d05d932b6cff333f130baf70febc22)
[CIR] Pass only 'this' to an inherited ctor from a virtual base
The base-object variant of an inheriting constructor whose inherited
constructor lives in a virtual base takes no arguments, since it doesn't
construct that base. We were hitting an NYI here. This change passes
just 'this', as classic codegen does.
Assisted-by: Claude Code / Claude Opus 5.5
lua-language-server: update to 3.19.1.
Un-BROKENs this package, patches were merged.
Over two years of development.
Provided by Sunil Nimmagadda in PR 60857.
[NVPTX] Use register-or-immediate operands for fns (#229224)
The PTX ISA is very abstract and high level, it supports immediate or
register operands in almost any instruction.
Prototype simplifying the NVPTX MIR opcodes and instruction selection by
no longer discriminating between registers and immediates.
[clang][deps] Track directory dependencies of modules (#222202)
In some cases a module depends on the contents of a directory in addition to
individual files. This happens for umbrella modules and framework modules, where
adding a header changes the module without changing any of its input files.
This records those directories in the module file, and adds
`-fmodules-validate-directory-dependencies` to treat an implicitly built module
as out of date when one of them changed after the module was built. It is off
by default.
Assisted-by: Claude Code: opus-5.5
[AMDGPU] Omit hardwired-on SRAMECC ELF mode
Mirror #227740 for SRAMECC. Without on/off modes, SRAMECC is implied
by EF_AMDGPU_MACH; encoding a mode makes consumers infer an
unsupported :sramecc+ modifier.
Depends on #225540.
Change-Id: I7bf76efbb86c7030eae36dc06ca7da0dd64cce87
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
