[orc-rt] Remove explicit addSimpleNativeMemoryMap call. NFCI. (#194766)
The SimpleNativeMemoryMap::Create call two lines below will add this
interface anyway, so the explicit call is redundant.
[WinEH] Diagnose SEH object unwinding in skipped __except bodies (#187718)
When an SEH __except block has no EH branches, CodeGen skips emitting the handler
body. This also skipped the existing diagnostic for local variables that require destruction
under C++ exceptions
Diagnose those variables before dropping the skipped handler body, and add coverage
for both sync and async exception modes
[TableGen] Fix indentation of generated code. NFC
This line was missing the indent(4) call. Noticed while looking at the
generated code.
Pull Request: https://github.com/llvm/llvm-project/pull/194765
[RISC-V][RVY] Add a DataLayout component for CHERI capabilities
This adds a new pointer address space to the data layout when RVY is
enabled, making use of the new 'e' flag for pointers with
[external state](https://github.com/llvm/llvm-project/pull/105735).
I chose address space 200 since that is what has been used in the
downstream CHERI forks for the past decade and therefore makes it slightly
easier to upstream tests, etc. but am happy to use any other value if that
is preferred. We can look at the ABI name parameter to detect
pure-capability ABIs, so this does not support the "hybrid" CHERI case that
is supported downstream where capability registers are supported (i.e.
the AS200 pointer attributes exist in the data layout), but the default
address spaces are still integers instead of AS200.
to handle the "hybrid" case where only some pointers use Y registers.
Reviewed By: topperc, lenary
Pull Request: https://github.com/llvm/llvm-project/pull/177249
[lldb] Pass `settings set` as a raw command (#194762)
To prevent settings start with a dash to be interpreter as a command
option, always pass them as raw values. An example of this is passing
`platform.plugin.wasm.runtime-args` with the dotest.py `--settings`
flag.
[flang] Do not mark CUDA device variables as dso_local (#194500)
A follow-up to https://github.com/llvm/llvm-project/pull/189709.
```fortran
integer, constant :: zzz = 4
bind(c, name='zzz_from_c') :: zzz
```
In this code, `zzz` is a CUDA `constant` variable with an initializer.
With PIE enabled, flang marks it as `dso_local`, causing LLVM to emit
direct addressing (`leaq`) instead of GOT-indirect addressing (`movq
@GOTPCREL`). The CUDA runtime interposes on these symbols via
`cudaRegisterVar`, so the wrong address gets registered, leading to a
segfault.
Fix: skip `dso_local` for globals with a CUDA data attribute.
[SSAF] Add SourcePassAnalysis framework
SourcePassAnalysis is for analyses/actions to be performed in a second
pass on source code, after the SSAF whole-program analysis.
SourcePassAnalysis is defined as an ASTConsumer abstraction that
depends on a whole-program analysis result.
This commit adds:
- SourcePassAnalysis base classes
- SourcePassAnalysis registry
- unit test for registry
rdar://175802731
[NFC][SSAF] Rename PointerFlowReachableAnalysis to UnsafeBufferReachableAnalysis
The previous-named PointerFlowReachableAnalysis is essentially
propagating unsafe buffers on a pointer flow graph. The pointer flow
analysis is a dependency, instead of the subject. So do the rename
and move.
[RFC][AMDGPU] Add AMDGPU_SUMMARY bitcode block for ThinLTO
With AMDGPU object linking, device functions are compiled separately from the
kernels that call them. Without whole-program visibility, the compiler must be
conservative about occupancy for every device function, leading to suboptimal
resource usage. However, GPU kernels typically carry explicit occupancy control
attributes that constrain the launch environment. ThinLTO is the natural place
to propagate these kernel attributes to callees: the combined module summary
index contains a cross-TU call graph, allowing occupancy information to be
propagated top-down from kernels to all reachable device functions. The backend
can then generate better code with the propagated constraints, achieving
whole-program awareness without the compile-time overhead of full LTO.
This patch introduces a dedicated AMDGPU_SUMMARY bitcode block that serializes
per-function summary data alongside the standard module summary. The block is
scoped to AMDGPU so that non-AMDGPU targets are completely unaffected. A
follow-up patch will add the ThinLTO propagation logic that reads these
summaries and applies conservative attribute bounds to device functions
reachable from multiple kernels.
[CIR] Always set base subobject type for C++ records (#194504)
For unions and final C++ classes, computeRecordLayout previously left
the base-subobject type as a default-constructed (null) cir::RecordType.
The non-virtual size always equals the size for those kinds of records,
so no separate ".base" variant is needed, but `BaseSubobjectType` itself
was never set to the complete type either.
That null leaked through
getCIRGenRecordLayout(RD).getBaseSubobjectCIRType(), which is called by
getStorageType(const CXXRecordDecl *) when laying out a
[[no_unique_address]] / potentially-overlapping field. The null
mlir::Type was then stored as MemberInfo::data and tripped a
SmallVector::back() !empty() assertion in
CIRRecordLowering::fillOutputFields, because a member with null data is
interpreted as a bitfield placeholder and reads fieldTypes.back() that
was never pushed.
Match classic CodeGen (CGRecordLayoutBuilder.cpp) and unconditionally
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