LLVM/project 1b27a4allvm/lib/Target/AMDGPU SIRegisterInfo.td AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU peephole-fold-imm.mir set-gpr-idx-peephole.mir

Revert "[AMDGPU] Remove definition of hi16 for scalar registers (#197467)"

This reverts commit 1a03c29cab6bc8c67023181cfdafbd5e0dbac815.
DeltaFile
+53-65llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+57-0llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
+16-16llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
+6-8llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+5-5llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+4-4llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
+141-9811 files not shown
+166-11717 files

FreeBSD/ports 494fafdmath/mate-calc Makefile distinfo

math/mate-calc: switch to GitHub release asset

Minor versions of 1.28.x are no longer published to the MATE mirror
and are only available on GitHub. Use USE_GITHUB=nodefault with a
release tarball instead of the auto-generated one, as recommended
by the porter's handbook.
DeltaFile
+7-6math/mate-calc/Makefile
+3-3math/mate-calc/distinfo
+10-92 files

LLVM/project 9b78555flang/lib/Semantics check-omp-variant.cpp, llvm/docs/AMDGPU AMDGPUAsmGFX12.rst gfx12_operands.rst

Merge branch 'main' into users/kasuga-fj/loop-interchange-lcssa-non-instr
DeltaFile
+1,087-1,602llvm/docs/AMDGPU/AMDGPUAsmGFX12.rst
+1,044-1,044llvm/lib/Target/AArch64/AArch64SystemOperands.td
+0-1,898llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+1,492-0llvm/docs/AMDGPU/gfx12_operands.rst
+754-0flang/lib/Semantics/check-omp-variant.cpp
+694-0llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
+5,071-4,5441,390 files not shown
+34,231-23,1261,396 files

LLVM/project 71bc583llvm/lib/Transforms/Scalar LoopInterchange.cpp

address review
DeltaFile
+2-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+2-21 files

LLVM/project 4cfaaa6mlir/include/mlir/Dialect/Bufferization/IR BufferizableOpInterface.h, mlir/lib/Dialect/Bufferization/IR BufferizableOpInterface.cpp BufferizationDialect.cpp

[NFC][mlir][bufferization] Remove getMemRefType() helper (#199034)

Replace getMemRefType() helper with a direct usage of
options.unknownTypeConverterFn() hook. This does not change any
behaviour since all the existing call-sites would already implicitly
call the hook. The major difference could have been in the handling of
the memref layout but this does not seem to be properly handled anyhow.

As the `getMemRefType()` helper is removed, there are two cases to keep
in mind for downstream users that need to adjust the code accordingly:
1. For creating memrefs without layouts, call
`options.unknownTypeConverterFn` hook directly (the same way this patch
is doing for upstream)
2. For creating memrefs with layouts (assuming, custom ones), please
(re)implement the same helper. As only ranked memrefs can have a layout,
a call to `mlir::MemRefType::get(shape, elementType, /*your custom
layout=*/myLayout, memorySpace)` should be sufficient.
DeltaFile
+3-26mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
+0-17mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
+1-1mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
+4-443 files

LLVM/project 1bde29ellvm/include/llvm/Target/GlobalISel Combine.td, llvm/test/CodeGen/AArch64/GlobalISel combine-or-of-and.mir combine-or-of-and.ll

[GlobalISel] Add `combine_or_of_and` from SelectionDAG (#198754)

This PR adds the pattern `// fold or (and x, y), x --> x` from
SelectionDAG.
DeltaFile
+161-0llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.mir
+94-0llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.ll
+18-1llvm/include/llvm/Target/GlobalISel/Combine.td
+1-4llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
+274-54 files

OpenBSD/ports ovIuaTunet/powerdns distinfo Makefile

   Update to PowerDNS Authoritative Server 5.1.0
VersionDeltaFile
1.61+2-2net/powerdns/distinfo
1.116+1-1net/powerdns/Makefile
+3-32 files

LLVM/project fb6153allvm/lib/CodeGen ShrinkWrap.cpp, llvm/test/CodeGen/RISCV shrinkwrap-save-restore-fixed-reg.ll

[CodeGen] Fix ShrinkWrap crash when FindIDom receives empty predecessor/successor list (#198995)

When using `-msave-restore` with `-ffixed-x5` on RISC-V,
`canUseAsPrologue` returns false for all blocks because the save-restore
prologue requires t0 (x5) which is reserved. This causes the shrink-wrap
loop to keep searching for a valid save point, eventually reaching the
entry block. On the next iteration, it calls FindIDom with the entry
block's empty predecessor list, triggering an assertion in
findNearestCommonDominator.

Fix by returning nullptr from FindIDom when the block list is empty,
which signals the caller to stop searching and give up the optimization.

Fixes #166759
DeltaFile
+38-0llvm/test/CodeGen/RISCV/shrinkwrap-save-restore-fixed-reg.ll
+2-0llvm/lib/CodeGen/ShrinkWrap.cpp
+40-02 files

LLVM/project 565fe7amlir/include/mlir/IR BuiltinDialectBytecode.td, mlir/lib/IR BuiltinDialectBytecode.cpp

[mlirbc] Add AffineMap serialization support

Add binary bytecode encoding for AffineMapAttr, replacing the textual fallback.
AffineMap is encoded as numDims, numSymbols, numResults, followed by the result
expressions. Where each expression, AffineExpr, is encoded as a recursive tree
with a VarInt kind tag followed by kind-specific data.

This uses pre-order encoding to avoid needing a sentinel and adds some special
casing for the common cases. To guard a bit more against malformed bytecode it
uses an iterative parser for these.

Updated the checked in mlirbc file as memref has a default affinemap, so
updating it pre snap.

Assisted-by: Antigravity : Gemini
DeltaFile
+298-0mlir/lib/IR/BuiltinDialectBytecode.cpp
+63-0mlir/test/Dialect/Builtin/Bytecode/attrs.mlir
+10-0mlir/include/mlir/IR/BuiltinDialectBytecode.td
+0-0mlir/test/Dialect/Builtin/Bytecode/builtin_fixed_0.mlirbc
+371-04 files

LLVM/project 5d00743llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU div-rem-fast-path.ll udivrem24.ll

[AMDGPU] Fix LowerDIVREM24 for the unsigned case (#196418)

This PR fixes the miscompilation bug found in
https://github.com/llvm/llvm-project/issues/194829.

The test revealed that there were missing checks for the unsigned case
in LowerDIVREM24. Without those checks, the optimization is wrongly
applied assuming that the division operands do fit in 24-bit integers,
triggering the miscompilation. One of the operands was 0xFFFFFFFF.

The bug is a regression introduced in
https://github.com/llvm/llvm-project/commit/81a709503d378c188462465918df161d664c4205.
The commit refactored the conditions that validated whether the
optimization could be applied. It moved them from each call site (signed
and unsigned cases) into the function, but missed the ones for the
unsigned case.

---------

Co-authored-by: Carlo Bertolli <carlo.bertolli at amd.com>
DeltaFile
+694-0llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
+70-78llvm/test/CodeGen/AMDGPU/udivrem24.ll
+19-22llvm/test/CodeGen/AMDGPU/udiv.ll
+20-8llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+803-1084 files

LLVM/project 62eaec6llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/AArch64 partial-reduce-chained.ll partial-reduce-costs.ll

[LV] Support partial reduce subs/fsubs without a mul operand (#199664)

This allows the `UpdateR(PrevValue, ext(...))` form for fsub/sub updates
(i.e, AddWithSub or Sub reductions). For sub reductions the
codegen/handling is identical to add reductions (with the sub handled
out of loop). For AddWithSub, reductions the sub is handled in-loop with
a NegatedExtendedReduction VP expression, which the encapsulates
`reduce.[f]add(neg(ext(op)))`.
DeltaFile
+135-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
+117-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-costs.ll
+51-66llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
+103-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
+68-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+12-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+486-733 files not shown
+519-779 files

LLVM/project 69d49a8mlir/include/mlir/IR BuiltinDialectBytecode.td, mlir/lib/IR BuiltinDialectBytecode.cpp

[mlirbc] Add AffineMap serialization support

Add binary bytecode encoding for AffineMapAttr, replacing the textual fallback.
AffineMap is encoded as numDims, numSymbols, numResults, followed by the result
expressions. Where each expression, AffineExpr, is encoded as a recursive tree
with a VarInt kind tag followed by kind-specific data.

This uses pre-order encoding to avoid needing a sentinel and adds some special
casing for the common cases. To guard a bit more against malformed bytecode it
uses an iterative parser for these.

Updated the checked in mlirbc file as memref has a default affinemap, so
updating it pre snap.

Assisted-by: Antigravity : Gemini
DeltaFile
+298-0mlir/lib/IR/BuiltinDialectBytecode.cpp
+75-0mlir/test/Bytecode/affine_map.mlir
+51-0mlir/test/Dialect/Builtin/Bytecode/attrs.mlir
+10-0mlir/include/mlir/IR/BuiltinDialectBytecode.td
+0-0mlir/test/Dialect/Builtin/Bytecode/builtin_fixed_0.mlirbc
+434-05 files

FreeBSD/ports 2fe0a91astro/traccar pkg-plist distinfo

astro/traccar: upgrade to 6.14.2
DeltaFile
+193-193astro/traccar/pkg-plist
+3-3astro/traccar/distinfo
+1-1astro/traccar/Makefile
+197-1973 files

LLVM/project 75dece7clang-tools-extra/clang-tidy/fuchsia StaticallyConstructedObjectsCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Avoid evaluating value-dependent static initializers in fuchsia-statically-constructed-objects (#201287)

Static data member initializers in class templates could crash the check
when they used non-type template parameters. This commit skips them
during analysis.

Closes https://github.com/llvm/llvm-project/issues/201110
DeltaFile
+8-0clang-tools-extra/test/clang-tidy/checkers/fuchsia/statically-constructed-objects.cpp
+2-2clang-tools-extra/clang-tidy/fuchsia/StaticallyConstructedObjectsCheck.cpp
+4-0clang-tools-extra/docs/ReleaseNotes.rst
+14-23 files

OpenBSD/ports elk4D4hwww/jupyter-notebook distinfo

   fix distinfo; spotted by tb@
VersionDeltaFile
1.24+2-2www/jupyter-notebook/distinfo
+2-21 files

OpenBSD/ports FFuOKqxdevel/harfbuzz Makefile distinfo

   Update to harfbuzz-14.2.1.
VersionDeltaFile
1.210+9-9devel/harfbuzz/Makefile
1.174+2-2devel/harfbuzz/distinfo
+11-112 files

OpenBSD/ports 8uWeCMgmisc/hwdata distinfo Makefile

   Update to hwdata-0.408.
VersionDeltaFile
1.132+2-2misc/hwdata/distinfo
1.134+1-1misc/hwdata/Makefile
+3-32 files

LLVM/project d27b4b6llvm/test/Transforms/LoopVectorize cast-costs.ll

[LV][NFC] Add another case to cast-costs.ll test (#201117)
DeltaFile
+25-2llvm/test/Transforms/LoopVectorize/cast-costs.ll
+25-21 files

LLVM/project 1a03c29llvm/lib/Target/AMDGPU SIRegisterInfo.td AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU peephole-fold-imm.mir set-gpr-idx-peephole.mir

[AMDGPU] Remove definition of hi16 for scalar registers (#197467)

The sub-register is not supported by the back-end pipelines and will
eventually cause an assert. With this change machine verifier can
enforce that hi16 is not being used. Asm parser is also updated to error
on invalid sub-registers, instead of asserting.

This is a follow up change on #188781.

Assisted-by: Claude Code
DeltaFile
+65-53llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+0-57llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
+16-16llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
+8-6llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+5-5llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+2-6llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
+96-14311 files not shown
+117-16617 files

LLVM/project 2cd87bfllvm/test/Transforms/AtomicExpand/X86 expand-atomic-non-integer.ll

[AtomicExpand][test] Regen CX16 CHECKs for atomic_vec2_half after cast removal
DeltaFile
+1-2llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+1-21 files

LLVM/project ceca051llvm/test/CodeGen/AArch64 arm64-zero-cycle-zeroing-fpr.ll

[AArch64] Fix arm64-zero-cycle-zeroing-fpr.ll check lines(NFC) (#200192)

Fix `mov`->`fmov` + add `--match-full-lines` to avoid such a pitfall
again.
DeltaFile
+67-67llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
+67-671 files

LLVM/project 979691ellvm/lib/Target/X86 X86ISelLowering.cpp X86ISelLowering.h, llvm/test/Transforms/AtomicExpand/X86 expand-atomic-non-integer.ll

[X86] Remove shouldCastAtomicLoadInIR; use DAG combine instead

Remove X86's shouldCastAtomicLoadInIR override that cast FP atomic
loads to integer at the IR level. Instead, handle this in a pre-legalize
DAG combine (combineAtomicLoad) that rewrites FP/FP-vector atomic loads
to integer atomic loads plus a bitcast.

This depends on #199310 which adds the necessary cmpxchg support for
non-integer atomic loads in AtomicExpand.
DeltaFile
+25-7llvm/lib/Target/X86/X86ISelLowering.cpp
+1-2llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+0-2llvm/lib/Target/X86/X86ISelLowering.h
+26-113 files

NetBSD/pkgsrc IM5s2LZdoc CHANGES-2026

   Updated security/py-service_identity, textproc/py-jsonschema-path
VersionDeltaFile
1.3475+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc 3hokNkotextproc/py-jsonschema-path PLIST Makefile

   py-jsonschema-path: updated to 0.5.0

   0.5.0

   Features

   Resolved cache enabled and SchemaPath per-instance cache removed
   Resolved cache evolution rebind
   Per-accessor identity

   Backward incompatible changes

   Resolved cache is enabled by default
   SchemaPath per-accessor __eq__/__hash__
VersionDeltaFile
1.3+13-1textproc/py-jsonschema-path/PLIST
1.8+4-4textproc/py-jsonschema-path/Makefile
1.5+4-4textproc/py-jsonschema-path/distinfo
+21-93 files

LLVM/project 1023990flang/lib/Semantics check-omp-variant.cpp check-omp-metadirective.cpp

[flang][OpenMP] Rename check-omp-metadirective.cpp (NFC). (#201159)

Both METADIRECTIVE and DECLARE VARIANT fall into the "variant
directives" category, so check-omp-variant.cpp is a more accurate name
for the file that hosts their semantic checks.

Suggested in
https://github.com/llvm/llvm-project/pull/198799#issuecomment-4576970335
DeltaFile
+754-0flang/lib/Semantics/check-omp-variant.cpp
+0-754flang/lib/Semantics/check-omp-metadirective.cpp
+1-1flang/lib/Semantics/CMakeLists.txt
+1-1flang/lib/Semantics/check-omp-structure.h
+756-7564 files

NetBSD/pkgsrc GqDXHCisecurity/py-service_identity Makefile distinfo

   py-service_identity: updated to 26.1.0

   26.1.0

   Added
   - Python 3.14 and 3.15 are now officially supported.

   Changed
   - *service-identity* now uses *cryptography*'s Rust-based ASN.1 decoder and doesn't depend on *pyasn1* and *pyasn1-modules* anymore.
     As a result, the oldest supported pyOpenSSL backend combination is now *pyOpenSSL* 26.1.0 with *cryptography* 47.0.0.

   Fixed
   - Verifying a single-label hostname (e.g. `localhost`) against a wildcard certificate pattern now raises `VerificationError` cleanly instead of crashing with an opaque `ValueError`.
VersionDeltaFile
1.18+5-8security/py-service_identity/Makefile
1.12+4-4security/py-service_identity/distinfo
+9-122 files

NetBSD/pkgsrc HRMUz6bdoc TODO

   doc/TODO: + llvm-22.1.7 [wip].
VersionDeltaFile
1.27340+2-2doc/TODO
+2-21 files

LLVM/project 86983a8llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir

Merge branch 'main' into users/MacDue/no_mul_sub_pr
DeltaFile
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,469-10llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+8,268-12llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+2,674-2,698llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+2,501-2,502llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+2,422-2,449llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+39,316-19,6015,548 files not shown
+289,600-145,9985,554 files

NetBSD/pkgsrc 8PZDQkrsecurity/vaultwarden options.mk

   vaultwarden: add s3 option
VersionDeltaFile
1.12+6-2security/vaultwarden/options.mk
+6-21 files

OpenBSD/ports n0UzAb2net/abaddon Makefile distinfo, net/abaddon/patches patch-src_platform_cpp

   net/abaddon: update to 0.2.4

   This update is backported to -stable by maintainer request to disable
   voice support because it can lead to a ban of user on stable.

   From izzy Meyer (maintainer)
VersionDeltaFile
1.1.1.1.2.1+14-16net/abaddon/Makefile
1.1.1.1.2.1+8-4net/abaddon/distinfo
1.1.1.1.2.1+3-4net/abaddon/pkg/PLIST
1.1.1.1.2.1+0-0net/abaddon/patches/patch-src_platform_cpp
+25-244 files