LLVM/project 6f57020flang/docs ParallelMultiImageFortranRuntime.md

docs/ParallelMultiImageFortranRuntime: Update link to latest PRIF Specification (#201403)

The PRIF Committee is pleased to announce the publication of the
Parallel Runtime Interface for Fortran (PRIF) Specification, Revision
0.8. The latest iteration of this specification represents the efforts
of a collaborative design process involving multiple individuals across
several institutions.

The document is available here: https://doi.org/10.25344/S4Z88F

The PRIF specification is governed by a formal PRIF Committee. For more
details, see: https://go.lbl.gov/prif-governance

The Committee vote to approve the technical content in this revision
began on 2026-04-30 and concluded successfully on 2026-05-18.

The 7-day committee comment period for cosmetic feedback began on
2026-05-21 and concluded on 2026-05-28 with no comments, and only minor
editorial changes by the Editor.

    [2 lines not shown]
DeltaFile
+1-1flang/docs/ParallelMultiImageFortranRuntime.md
+1-11 files

LLVM/project db33161llvm/lib/Transforms/Scalar StructurizeCFG.cpp, llvm/test/CodeGen/AMDGPU infinite-loop.ll si-unify-exit-multiple-unreachables.ll

[AMDGPU] Add islands to StructurizeCFG

Handle an "island", i.e. a block whose terminator is not rewritable
(e.g., a callbr) in this context and considered immutable from this
pass's perspective.

The island is left untouched; its edges are split into forwarders that
converge at a new Flow block (ExitFlow). The callbr's runtime target
choice is recovered as a per-target i1 "sel" phi and re-dispatched by a
structured ladder of 2-way branches:

                 callbr
               /   |   \
           fwd_0 fwd_1 fwd_2      forwarders (intermediate target blocks)
               \   |   /
            ExitFlow (Flow_0) -- sel_0? --> real_0
                  |  else
                Flow_1 --------- sel_1? --> real_1
                  |  else

    [2 lines not shown]
DeltaFile
+1,283-111llvm/test/Transforms/StructurizeCFG/callbr.ll
+356-36llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
+121-47llvm/test/CodeGen/AMDGPU/infinite-loop.ll
+100-39llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
+62-31llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
+30-12llvm/test/CodeGen/AMDGPU/callbr.ll
+1,952-2761 files not shown
+1,954-2787 files

LLVM/project a89a593llvm/include/llvm/IR ModuleSummaryIndex.h ModuleSummaryIndexYAML.h, llvm/lib/Bitcode/Reader BitcodeReader.cpp

[CFI] Refactor `CfiFunctionIndex` to externalize GUID calculation (#201635)

In preparation for PR #201370 - the goal is to decouple CFI from _how_
ThinLTO computes its GUIDs, and enable PR #184065 (for this
[RFC](https://discourse.llvm.org/t/rfc-keep-globalvalue-guids-stable/84801)).

This PR just changes APIs and the internal implementation of
CfiFunctionIndex, the subsequent one (201370) actually propagates GUIDs
through metadata. It's _almost_ NFC - the YAML format does change
though.
DeltaFile
+55-48llvm/include/llvm/IR/ModuleSummaryIndex.h
+28-11llvm/include/llvm/IR/ModuleSummaryIndexYAML.h
+11-10llvm/lib/LTO/LTO.cpp
+14-6llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+12-7llvm/test/Transforms/LowerTypeTests/Inputs/import-icall.yaml
+12-6llvm/test/Transforms/LowerTypeTests/export-icall.ll
+132-887 files not shown
+171-11413 files

FreeNAS/freenas 892d0cfsrc/middlewared/middlewared/api/v26_0_0 system_product.py, src/middlewared/middlewared/plugins/truenas license_legacy_utils.py license_utils.py

NAS-141068 / 26.0.0-RC.1 / Properly handle VM feature flag (by Qubad786) (#19056)

## Context

Middleware should expose the VM entitlement as "VMS" at the API boundary
and to any consumer that inspects license features. The signed license
PEM and signing daemon continue to carry "VM" as the JSON key, and
existing customer PEMs can't be re-keyed without re-signing, so the
translation has to happen middleware-side.

## Solution

A single `FEATURE_NAME_MAP` in license_utils.py translates "VM" → "VMS"
for both the daemon-signed and legacy parsers (the legacy-only JAILS →
APPS entry sits in the same map; it's a no-op on the modern path since
the daemon never emits "JAILS"). v26 and v27 SystemFeatureEnabledArgs
both accept "VMS" and carry from_previous / to_previous adapters so v25
/ v26 clients passing "VM" are translated transparently.


    [3 lines not shown]
DeltaFile
+77-0src/middlewared/middlewared/pytest/unit/plugins/truenas/test_license_utils.py
+7-1src/middlewared/middlewared/api/v26_0_0/system_product.py
+2-3src/middlewared/middlewared/plugins/truenas/license_legacy_utils.py
+2-2src/middlewared/middlewared/plugins/truenas/license_utils.py
+1-1src/middlewared/middlewared/pytest/unit/plugins/truenas/test_license_legacy_utils.py
+1-1src/middlewared/middlewared/plugins/vm/info.py
+90-86 files

LLVM/project e4828aaclang-tools-extra/clang-doc Serialize.cpp BitcodeReader.cpp, clang-tools-extra/clang-doc/tool ClangDocMain.cpp

[clang-doc] Wrap per thread arenas in an accessor for BUILD_SHARED (#201388)

It seems like for BUILD_SHARED builds of the toolchain on Windows,
specifically aarch64-windows-gnu hosts, the use of the `thread_local`
variables in Representation.cpp causes an issue at link time due to
non-explicit export. Instead, just wrap them in an accessor function,
which should solve the issue in a cross platform way.

Fixes #200915
DeltaFile
+26-23clang-tools-extra/clang-doc/Serialize.cpp
+25-24clang-tools-extra/clang-doc/BitcodeReader.cpp
+24-16clang-tools-extra/clang-doc/Representation.cpp
+9-8clang-tools-extra/clang-doc/Representation.h
+4-2clang-tools-extra/unittests/clang-doc/MergeTest.cpp
+3-2clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
+91-751 files not shown
+92-767 files

LLVM/project cac3e79flang/docs/MeetingNotes/2026 2026-06-03.md

[flang] Adding notes from the Flang Community Call June 3rd (#201458)
DeltaFile
+66-0flang/docs/MeetingNotes/2026/2026-06-03.md
+66-01 files

LLVM/project 7b4d5d0offload/plugins-nextgen/level_zero/include L0Event.h L0Device.h, offload/plugins-nextgen/level_zero/src L0Event.cpp L0Device.cpp

[OFFLOAD][L0] Implement Event APIs (#201306)

Introduce a new L0EventTy type used to implement most of the Event APIs
of PluginInterface (all but getEventElapsedTimeImpl).

---------

Co-authored-by: Kevin Sala Penades <kevinsala.ks at gmail.com>
DeltaFile
+129-0offload/plugins-nextgen/level_zero/include/L0Event.h
+96-0offload/plugins-nextgen/level_zero/src/L0Event.cpp
+60-0offload/plugins-nextgen/level_zero/src/L0Device.cpp
+19-37offload/plugins-nextgen/level_zero/include/L0Device.h
+0-52offload/plugins-nextgen/level_zero/include/L0Memory.h
+0-50offload/plugins-nextgen/level_zero/src/L0Memory.cpp
+304-1396 files not shown
+373-13912 files

FreeNAS/freenas 2d5c63ctests/protocols pynfs_proto.py, tests/sharing_protocols/nfs test_nfs_ha.py nfs_ha_utils.py

NFS HA Tests
DeltaFile
+620-0tests/sharing_protocols/nfs/test_nfs_ha.py
+310-2tests/protocols/pynfs_proto.py
+280-0tests/sharing_protocols/nfs/nfs_ha_utils.py
+35-24tests/sharing_protocols/nfs/conftest.py
+14-16tests/sharing_protocols/nfs/test_nfs_snapdir.py
+7-0tests/sharing_protocols/nfs/test_nfs_change_attr.py
+1,266-426 files

LLVM/project d32452fllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir frem.ll

handle RegisterOperand

Created using spr 1.3.8-beta.1
DeltaFile
+5,590-5,510llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,469-10llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+6,598-111llvm/test/CodeGen/X86/clmul-vector.ll
+3,092-2,392llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+2,237-668llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+2,211-642llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+30,197-9,3333,702 files not shown
+174,530-88,8863,708 files

LLVM/project 3230e14llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir frem.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+5,590-5,510llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,469-10llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+6,598-111llvm/test/CodeGen/X86/clmul-vector.ll
+3,092-2,392llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+2,237-668llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+2,211-642llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+30,197-9,3333,700 files not shown
+174,394-88,8623,706 files

LLVM/project e215e35llvm/lib/Target/RISCV RISCVRegisterInfo.td, llvm/test/MC/RISCV rv32c-invalid.s

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+476-0llvm/test/MC/RISCV/rvy/rvyc-valid-load-store.s
+199-0llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
+171-0llvm/test/TableGen/getRegClassFromMatchKind.td
+112-57llvm/test/MC/RISCV/rv32c-invalid.s
+144-0llvm/test/MC/RISCV/rvy/rvyc-invalid-load-store.s
+78-38llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+1,180-9524 files not shown
+1,875-22430 files

LLVM/project fc67ba1llvm/lib/Target/RISCV RISCVRegisterInfo.td, llvm/test/MC/RISCV rv32c-invalid.s

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+476-0llvm/test/MC/RISCV/rvy/rvyc-valid-load-store.s
+199-0llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
+112-57llvm/test/MC/RISCV/rv32c-invalid.s
+144-0llvm/test/MC/RISCV/rvy/rvyc-invalid-load-store.s
+78-38llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+93-0llvm/test/MC/RISCV/rvy/rvy-invalid-load-store.s
+1,102-9522 files not shown
+1,645-22428 files

LLVM/project 1525f57clang/test/OpenMP nvptx_SPMD_codegen.cpp nvptx_target_teams_generic_loop_codegen.cpp

[clang][OpenMP] Improve loop structure for distributed loops

This is a part of a series of patches that rework OpenMP cross-team
reductions.

This patches wires the existing
`kmp_sched_distr_static_chunk_sched_static_chunkone` to be used by
CodeGen.

Example of the intended change of this patch:
```
target teams distribute parallel for reduction(+:s)
  for (i = 0; i < N; i++) s += a[i];
```

Before:
```
__kmpc_distribute_static_init(91)
for (team_lb = team*nthreads; team_lb < N; team_lb += nteams*nthreads) {

    [67 lines not shown]
DeltaFile
+2,345-3,605clang/test/OpenMP/nvptx_SPMD_codegen.cpp
+316-1,156clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp
+301-1,141clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
+223-543clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
+120-360clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp
+59-179clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp
+3,364-6,98410 files not shown
+3,652-7,51016 files

FreeBSD/ports cbc8291dns/powerdns distinfo Makefile

dns/powerdns: Update to 5.0.5

PR:             295516
Security:       0823ac26-6040-11f1-ba4a-50ebf6bdf8e9
Approved by:    maintainer

(cherry picked from commit 824add6a167bd95eb178c5778b34cda742671ba0)
DeltaFile
+3-3dns/powerdns/distinfo
+1-1dns/powerdns/Makefile
+4-42 files

FreeNAS/freenas 5d8ab31src/freenas/usr/local/libexec disable-rootfs-protection, src/middlewared/middlewared/plugins boot.py

NAS-141261 / 26.0.0-RC.1 / Serialize rootfs read-only/sysext toggles with a shared lock (by anodos325) (#19070)

Remove the ability for concurrent calls to do things with root
filesystem unlocked (either administratively through
disable-rootfs-protection) or internal middleware callers that do things
in /usr to clobber each other.

Protection takes belt-and-suspenders approach of taking pthread lock,
then taking flock.

Original PR: https://github.com/truenas/middleware/pull/19069

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+29-0src/middlewared/middlewared/utils/rootfs_protection.py
+17-8src/middlewared/middlewared/plugins/boot.py
+12-7src/freenas/usr/local/libexec/disable-rootfs-protection
+6-2src/middlewared/middlewared/plugins/system_advanced/nvidia.py
+64-174 files

LLVM/project 034243ellvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AMDGPU dagcombine-freeze-extract-subvector-loop.ll

Style, named test vars
DeltaFile
+25-28llvm/test/CodeGen/AMDGPU/dagcombine-freeze-extract-subvector-loop.ll
+1-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+26-302 files

LLVM/project 90bb386llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AMDGPU dagcombine-freeze-extract-subvector-loop.ll

[SelectionDAG] Fold extracts of subvector inserts

Fold extract_subvector(insert_subvector(...)) when the extraction is
outside the inserted subvector or the inserted subvector only amends
the extracted

In particular,
1. vA extract_subvector (vB insert_subvector(vB X, vC Y, C1), C2) =>
vA extract_subvector(X, C2) when [C2, C2 + A) intersect [C1, C1 + C)
is the empty set
2. ... => extract_subvector(Y, C2 - C1) if [C2, C2 + Y) is a subset of
[C1, C1 + C) - an existing simplification
3. ... => vA insert_subvector(vA extract_subvector(vB X, C2), vC Y, C1 - C2)
if [C1, C1 + C) is a subset of [C2, C2 + A) - that is, if you're only
updating the extracted sub-part.

Adds a regresssion tests for an infinite SelectionDAG cycle that is
fixed by a stack of commits that ends with this one.


    [3 lines not shown]
DeltaFile
+72-56llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+44-48llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+45-0llvm/test/CodeGen/AMDGPU/dagcombine-freeze-extract-subvector-loop.ll
+28-7llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+15-17llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
+4-8llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
+208-1361 files not shown
+212-1447 files

LLVM/project 3434296llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-load-store-legalisation.ll

scalable vector test updates
DeltaFile
+772-772llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+4-20llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
+4-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+780-7943 files

LLVM/project 6fe756allvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 vector-shuffle-combining-avx512bwvl.ll

[SelectionDAG] Fold subvector inserts into concat operands

Push insert_subvector into the containing CONCAT_VECTORS operand when the insertion is wholly contained there.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+34-10llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+8-36llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
+42-462 files

LLVM/project 8c982f1llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

Make this work on scalable vectors
DeltaFile
+12-15llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+12-151 files

LLVM/project 93ad7e0llvm/test/CodeGen/AArch64 sve-fixed-vector-llrint.ll sve-fixed-vector-lrint.ll, llvm/test/CodeGen/AMDGPU bf16.ll

[SelectionDAG] Fold extracts spanning concat operands

Factor the extract_subvector-of-CONCAT_VECTORS logic and handle
extracts that cover multiple whole concat operands by rebuilding a
smaller concat directly.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+992-904llvm/test/CodeGen/AMDGPU/bf16.ll
+187-229llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+187-229llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+196-176llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
+142-140llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+120-120llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
+1,824-1,79811 files not shown
+2,204-2,27917 files

LLVM/project 956037fllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[SelectionDAG] Fold nonzero extract-of-extract indices

Generalize the extract_subvector-of-extract_subvector fold to compose
nonzero indices instead of only handling an outer index of zero.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+8-8llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+8-81 files

LLVM/project 9f3674cllvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

Review feedback I forgot to push lol
DeltaFile
+2-2llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+2-21 files

LLVM/project e6fb47allvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

Review style etc.
DeltaFile
+9-10llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+9-101 files

LLVM/project e28a0c1llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/X86 freeze-vector.ll

[SelectionDAG] Track bitcast demanded elements in noundef tests

Bitcasts preserve undef/poison status, but vector bitcasts can change
which source lanes cover a demanded result lane. Map the demanded
element mask through fixed-length vector bitcasts before checking the
source where possible.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+12-36llvm/test/CodeGen/X86/freeze-vector.ll
+41-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+53-362 files

LLVM/project 4e363a0llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

Review feedback
DeltaFile
+4-8llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+4-81 files

LLVM/project 49425d9llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/X86 freeze-vector.ll

[SelectionDAG] Track demanded select elements in noundef checks

Propagate demanded elements through to the two arms of a select, and
check the condition with or without demanded elements depending on if
it's a vector or not.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+17-2llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+0-11llvm/test/CodeGen/X86/freeze-vector.ll
+17-132 files

LLVM/project bb6627bllvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

Review comments
DeltaFile
+4-9llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+4-91 files

LLVM/project fc2b3efllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/X86 freeze-fp.ll pr91005.ll

[SelectionDAG] Look through freeze in undef demanded checks

There were cycles where the freeze combiner and thet
demanded-elements simplification code would get into fights about
whethere the operands to a shuffle or a concat should be
`freeze undef` or `undef` once the simplifier had concluded zero
elements were demanded from some operation. This PR prevents such
cases.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+11-7llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+2-1llvm/test/CodeGen/X86/freeze-fp.ll
+2-1llvm/test/CodeGen/X86/pr91005.ll
+15-93 files

LLVM/project 6014499llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/X86 freeze-vector.ll

[SelectionDAG] Track demanded concat elements in noundef checks

Teach isGuaranteedNotToBeUndefOrPoison to distribute fixed-length
demanded element masks across CONCAT_VECTORS operands. This is part of
the series of fixes needed to resolve a SelectionDAG hang by making it
possible to prove certain values don't need to be frozen.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+23-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+4-12llvm/test/CodeGen/X86/freeze-vector.ll
+27-122 files