LLVM/project 9567f47llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp

[AMDGPU][GlobalISel] Use single B32 rule for permlane16

B32 already covers s32, <2 x s16> and 32-bit pointers, so one StandardB
fast rule replaces the separate S32, V2S16 and DivPtr32 rules. This
matches permlane_bcast/up/down/xor and permlane64, which have the same
overloaded intrinsic shape.

Change-Id: I770a93d5e75e68df704e84d7ad165fdd2cf2fc53
DeltaFile
+4-11llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+4-111 files

LLVM/project 2ea101ellvm/include/llvm/IR PISAIntrinsicUtils.h IntrinsicsPISA.td, llvm/include/llvm/Support PISAAddrSpace.h

Add PISA IR intrinsics and address-space utilities

This patch adds the PISA IR intrinsics definitions, address space
utilities, and basic tests.
DeltaFile
+252-0llvm/include/llvm/IR/IntrinsicsPISA.td
+121-0llvm/lib/IR/PISAIntrinsicUtils.cpp
+72-0llvm/include/llvm/IR/PISAIntrinsicUtils.h
+59-0llvm/include/llvm/Support/PISAAddrSpace.h
+24-0llvm/test/CodeGen/PISA/intrinsics-attributes.ll
+20-0llvm/test/CodeGen/PISA/intrinsics-address-space.ll
+548-05 files not shown
+572-011 files

FreeBSD/ports 343e9b3print/py-pypdf Makefile distinfo

print/py-pypdf: Update to 6.9.2

PR:             294342
Reported by:    yuri@
DeltaFile
+3-3print/py-pypdf/distinfo
+1-1print/py-pypdf/Makefile
+4-42 files

GhostBSD/ghostbsd 53b736esys/conf package-version

bump version to p12
DeltaFile
+1-1sys/conf/package-version
+1-11 files

GhostBSD/ghostbsd 221e102contrib/netbsd-tests/lib/libc/locale t_iconv.c, contrib/tzdata africa

Merge remote-tracking branch 'freebsd/releng/15.0' into releng/15.0
DeltaFile
+375-0contrib/netbsd-tests/lib/libc/locale/t_iconv.c
+220-0tests/sys/kern/resolve_beneath_test.c
+32-159contrib/tzdata/africa
+114-77sys/kern/kern_proc.c
+169-3sys/contrib/openzfs/tests/zfs-tests/cmd/libzfs_input_check.c
+89-67sys/netinet/libalias/alias_smedia.c
+999-30673 files not shown
+2,559-66279 files

FreeBSD/ports 0e280a2www/py-soupsieve Makefile distinfo

www/py-soupsieve: Update to 2.8.4

PR:             297277
Reported by:    rozhuk.im at gmail.com
DeltaFile
+3-3www/py-soupsieve/distinfo
+1-1www/py-soupsieve/Makefile
+4-42 files

LLVM/project fc2f417llvm/lib/Target/PISA PISARegisterInfo.td PISATargetMachine.h, llvm/lib/Target/PISA/MCTargetDesc PISAMCAsmInfo.cpp PISAMCTargetDesc.cpp

Add PISA target registration and backend stub

Register the Intel GPU portable ISA (PISA) target. Add the pisa Triple
arch, data layout, and a minimal MC/TargetMachine skeleton.
DeltaFile
+85-0llvm/lib/Target/PISA/PISATargetMachine.cpp
+64-0llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.cpp
+61-0llvm/lib/Target/PISA/PISASubtarget.h
+46-0llvm/lib/Target/PISA/PISATargetMachine.h
+41-0llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.cpp
+39-0llvm/lib/Target/PISA/PISARegisterInfo.td
+336-025 files not shown
+880-031 files

FreeBSD/ports 9237de6www/py-django60 Makefile distinfo, www/py-django60/files patch-pyproject.toml

www/py-django60: Update to 6.0.8

(cherry picked from commit 6b2158cd821eba5539e713ef7ae25a635d6b7df6)
DeltaFile
+5-8www/py-django60/files/patch-pyproject.toml
+3-3www/py-django60/distinfo
+1-1www/py-django60/Makefile
+9-123 files

FreeBSD/ports 2e04bf2www/py-django52 Makefile distinfo, www/py-django52/files patch-pyproject.toml

www/py-django52: Update to 5.2.17

(cherry picked from commit cb8a86870593b9224554d71f04d1344b7a03db9f)
DeltaFile
+3-3www/py-django52/files/patch-pyproject.toml
+3-3www/py-django52/distinfo
+1-1www/py-django52/Makefile
+7-73 files

FreeBSD/ports cb8a868www/py-django52 Makefile distinfo, www/py-django52/files patch-pyproject.toml

www/py-django52: Update to 5.2.17
DeltaFile
+3-3www/py-django52/files/patch-pyproject.toml
+3-3www/py-django52/distinfo
+1-1www/py-django52/Makefile
+7-73 files

FreeBSD/ports 6b2158cwww/py-django60 Makefile distinfo, www/py-django60/files patch-pyproject.toml

www/py-django60: Update to 6.0.8
DeltaFile
+5-8www/py-django60/files/patch-pyproject.toml
+3-3www/py-django60/distinfo
+1-1www/py-django60/Makefile
+9-123 files

LLVM/project d7575bcllvm/lib/Target/RISCV RISCVInsertVSETVLI.cpp, llvm/test/CodeGen/RISCV/rvv xsfmm-vsetvl-removal.ll

[RISCV] coalesce between VSETVLI and SF_VSETTNT (#203438)

When twiden != 0, LMUL, tail policy, and mask policy from the user are
ignored. The tail policy and mask policy are always treated as agnostic.
The normal RVV instruction will ignore the twiden parameter. This
observation could allow the RVV instruction and xsfmm instruction to
share the same configuration instruction.

We need to make sure the AVL, SEW, and AltFmt is same between VSETVL and
VSETVLTN.

---------

Co-authored-by: Luke Lau <luke_lau at icloud.com>
DeltaFile
+666-0llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
+111-0llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+777-02 files

NetBSD/src aZ3pooRbin/sh sh.1 miscbltin.c

   /bin/sh - builtin read command fixes (miscbltin.c)

   This corrects a change made in the previous version, where
   in addition to the intended change, making a read error be
   treated differently than EOF, a change with unplanned
   consequences was also made, to treat the EINTR read error
   as a "try again" signal, rather than as a read error.
   That meant that caught traps no longer interrupted the read,
   and while that is how (some) other shells do it (like bash)
   it was a change to how our shell does things.

   So, now there is (in normal shells) a new -c (continue) option
   to cause this behaviour, when given, a trapped signal will be
   processed during the wait for input by the read built-in utility,
   but not end the read.   When absent, the trap will still be processed
   while the read is in progress, but will be treated as a read error
   (and produce the special (>1) exit code 130.

   While doing this, revert all these changes for SMALL shells, they

    [4 lines not shown]
VersionDeltaFile
1.59+67-26bin/sh/miscbltin.c
1.280+31-10bin/sh/sh.1
+98-362 files

NetBSD/src 92eZ01Lbin/sh trap.h trap.c

   /bin/sh - trap.c - new func and avoid lost memory

   Add run_traps() - which is just dotrap() except that it
   preserves the state of the stack around the trap executions,
   so is safe to call with the stack in any state.   It will also
   preserve the state of the growing string at the top of the
   stack if informed (by giving a non-zero value as its arg)
   that such a string currently exists.   This new function does
   not exist in SMALL shells.

   While here, fix an unlikely memory leak - if a shell error
   (not command error) occurs while processing a trap in dotrap()
   the copy of the trap string being parsed can be lost.  This is
   irrelevant in non-interactive shells, as the errors which would
   cause this loss, also cause a non-interactive shell to exit,
   the lost memory is only lost for a very short time.   Interactive
   shells rarely set traps (except possibly an EXIT trap - for which
   the memory loss is also immaterial for almost the same reason) at
   all, and if one were set, and generated a shell error (typically

    [3 lines not shown]
VersionDeltaFile
1.64+40-5bin/sh/trap.c
1.27+5-1bin/sh/trap.h
+45-62 files

NetBSD/src GHFZAOLbin/sh memalloc.h

   /bin/sh - memalloc.h - added STSTRLEN()

   Add a new stack string macro STSTRLEN() which returns the
   current length of the string being accumulated at the top
   of the (shell) stack.   As with all the other Stack String
   macros, it may only be used between a STARTSTACKSTR() call
   and the next call which allocates stack space (often
   grabstackstr(), but stalloc() stunalloc() grabstackblock()
   all count for this).   Use at any other time will give
   meaningless unspecified results.
VersionDeltaFile
1.23+2-1bin/sh/memalloc.h
+2-11 files

LLVM/project 1fc2b37llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.gfx950.ll llvm.amdgcn.smfmac.gfx950.ll

[AMDGPU][GISel] RegBankLegalize rules for BF16 variants of gfx950 MFMA intrinsics (#214042)
DeltaFile
+1,130-583llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
+668-345llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+75-37llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
+29-29llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1,902-9944 files

LLVM/project 02b5bebllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.scalef32.sr.ll llvm.amdgcn.cvt.scalef32.pk.ll

[AMDGPU][GISel] RegBankLegalize rules for CVT Scale and SR BF16-specific intrinsics (#214018)
DeltaFile
+352-172llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
+305-116llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
+235-65llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
+115-119llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
+62-27llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+85-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
+1,154-5006 files not shown
+1,258-56412 files

LLVM/project 20339dalldb/source/Target ThreadPlanStepInRange.cpp

[lldb] Step past a prologue the pc is inside (#213555)

A step into a function ran past its prologue only when the pc was
exactly the function's first address. A target whose entry point is not
a function's first address (such as WebAssembly) is entered past it.
This means that the check took every such call for one whose prologue
had already run, and the step stopped on the opening brace instead of
the first statement.

What says the prologue has yet to run is the pc being inside it, which
for a target that does enter at the first address is the condition that
was there before.
DeltaFile
+12-4lldb/source/Target/ThreadPlanStepInRange.cpp
+12-41 files

FreeBSD/src b95a859sys/fs/autofs autofs_vnops.c

autofs_lookup(): busy the mount point around autofs_trigger()

Since autofs_lookup() calls into autofs_trigger_vn() to perform
automounting, and autofs_trigger_vn() unlocks the vnode, it is possible
for the unmount to start meantime.  Then autofs_trigger() accesses freed
memory.

At this point, busy can be only done unblocking, and the transient
failure must abort the trigger operation.  This would cause spurious
automounter errors, but at least should prevent accesses to the freed
memory.

PR:     294361
Reviewed by:    markj, rew
Tested by:      rew
Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Differential revision:  https://reviews.freebsd.org/D58626
DeltaFile
+11-4sys/fs/autofs/autofs_vnops.c
+11-41 files

FreeBSD/ports 98f296ascience/psi4 distinfo Makefile, science/psi4/files patch-psi4_run__psi4.py

science/psi4: update 1.10.2 → 1.11
DeltaFile
+89-8science/psi4/pkg-plist
+5-4science/psi4/files/patch-psi4_run__psi4.py
+4-4science/psi4/Makefile
+3-3science/psi4/distinfo
+101-194 files

FreeBSD/ports 83c27d4math/deal.ii Makefile

math/deal.ii: Add missing run-time dependencies
DeltaFile
+3-0math/deal.ii/Makefile
+3-01 files

FreeBSD/ports 4be1b97science/libint2-psi4 Makefile distinfo

science/libint2-psi4: Update tarball used in build to make psi4 to succeed
DeltaFile
+3-3science/libint2-psi4/distinfo
+2-1science/libint2-psi4/Makefile
+5-42 files

LLVM/project bd41173llvm/lib/CodeGen/GlobalISel LoadStoreOpt.cpp, llvm/test/CodeGen/AArch64/GlobalISel store-merging-debug.mir store-merging.mir

[AArch64][GlobalISel] Use a concrete type for store merging. (#213740)

This is just to reduce the number of scalar types in the MIR, as the
value is between a constant and a store it should have little effect.
DeltaFile
+16-16llvm/test/CodeGen/AArch64/GlobalISel/store-merging.mir
+2-2llvm/test/CodeGen/AArch64/GlobalISel/store-merging-debug.mir
+1-1llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
+19-193 files

OpenBSD/src 61DmEPPusr.bin/ssh sshd_config.5

   document existence of mlkem768{brainpoolp256r1,nistp256}-sha256 KEXes
VersionDeltaFile
1.401+6-2usr.bin/ssh/sshd_config.5
+6-21 files

FreeBSD/ports b1eaa07devel/R-cran-sfsmisc Makefile distinfo

devel/R-cran-sfsmisc: Update to 1.1-25

Reported by:    portscout
DeltaFile
+3-3devel/R-cran-sfsmisc/distinfo
+1-1devel/R-cran-sfsmisc/Makefile
+4-42 files

LLVM/project 437ff36clang/lib/CIR/CodeGen CIRGenClass.cpp, clang/test/CIR/CodeGen partial-array-cleanup.cpp array-ctor.cpp

[CIR] Move array-ctor cleanup to properly cleanup temporaries (#213993)

This patch came out of self-build, any constructor temporary called
during the construction of an array element was being improperly cleaned
up (actually, no terminator?). This patch moves the RunCleanups RAII to
do so immediately in the body.

The OGCG/LLVM check lines are effectively equal, except OGCG uses a PHI
and we are doing so with an iterator loop, but the 'dtor called
immediately' is still correct.
DeltaFile
+178-0clang/test/CIR/CodeGen/array-ctor.cpp
+161-0clang/test/CIR/CodeGen/partial-array-cleanup.cpp
+59-60clang/lib/CIR/CodeGen/CIRGenClass.cpp
+398-603 files

LLVM/project bc6f2a9clang/lib/CIR/Dialect/IR CIRDialect.cpp, clang/test/CIR/IR invalid-global.cir

[CIR] Reject a global carrying a function type (#214065)

The verifier was accepting a `cir.global` whose `sym_type` is a
function. The LLVM dialect global takes one too, so it survives to LLVM
IR translation and crashes instead of reporting an error.
`GlobalOp::verify()` now rejects it.
DeltaFile
+9-0clang/test/CIR/IR/invalid-global.cir
+5-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+14-02 files

LLVM/project 99fabb8flang/lib/Lower/OpenMP Clauses.cpp

format
DeltaFile
+5-5flang/lib/Lower/OpenMP/Clauses.cpp
+5-51 files

LLVM/project 452467cllvm/lib/CodeGen/SelectionDAG LegalizeTypes.h LegalizeVectorTypes.cpp, llvm/test/CodeGen/NVPTX masked-divrem.ll

[SelectionDAG] Split masked div/rem operands with illegal masks (#214058)

PR description written by Codex

Split masked signed and unsigned division/remainder alongside illegal
vector masks to fix NVPTX SelectionDAG crashes. Covers all four
intrinsics and the original eight-lane reproducer; five focused LLVM
tests pass.
DeltaFile
+46-0llvm/test/CodeGen/NVPTX/masked-divrem.ll
+22-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+69-03 files

LLVM/project 95572b4llvm/test/MC/RISCV rv32i-invalid.s

[RISC-V][MC] Add a few more tests for invalid lw operands

To show the difference in diagnostic output as suggested in
https://github.com/llvm/llvm-project/pull/210901.

Pull Request: https://github.com/llvm/llvm-project/pull/214070
DeltaFile
+15-1llvm/test/MC/RISCV/rv32i-invalid.s
+15-11 files