LLVM/project 2746fc6llvm/test/CodeGen/AMDGPU/GlobalISel legalize-fceil.mir legalize-intrinsic-trunc.mir

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (43) (#209733)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+36-3694 files not shown
+291-291100 files

LLVM/project 567c6a7llvm/test/CodeGen/AMDGPU/GlobalISel inst-select-store-global.mir lds-misaligned-bug.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (42) (#209732)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
+42-4294 files not shown
+281-281100 files

LLVM/project 9744b47clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn.hip builtins-amdgcn-gfx1250.hip

[CIR][AMDGPU] Add support for AMDGCN rsq and rsq_clamp builtins (#197349)

Adds codegen for the following AMDGCN reciprocal square root builtins:

- __builtin_amdgcn_rsq (double)
- __builtin_amdgcn_rsqf (float)
- __builtin_amdgcn_rsqh (half)
- __builtin_amdgcn_rsq_bf16 (bfloat16)
- __builtin_amdgcn_rsq_clamp (double)
- __builtin_amdgcn_rsq_clampf (float)

These are lowered to the corresponding `llvm.amdgcn.rsq` and
`llvm.amdgcn.rsq.clamp` intrinsic calls.
DeltaFile
+32-0clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+10-2clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
+3-8clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+8-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
+53-104 files

FreeNAS/freenas 02f0e49src/middlewared/middlewared/plugins/keychain used_by.py

`ruff`
DeltaFile
+1-1src/middlewared/middlewared/plugins/keychain/used_by.py
+1-11 files

FreeNAS/freenas 103e0ffsrc/middlewared/middlewared/plugins replication.py boot.py, src/middlewared/middlewared/plugins/replication crud.py __init__.py

Merge branch 'master' into cloud_credentials-mypy
DeltaFile
+0-835src/middlewared/middlewared/plugins/replication.py
+650-0src/middlewared/middlewared/plugins/replication/crud.py
+0-372src/middlewared/middlewared/plugins/boot.py
+246-0src/middlewared/middlewared/plugins/replication/__init__.py
+196-0src/middlewared/middlewared/pytest/unit/plugins/pool/test_validate_topology.py
+193-0src/middlewared/middlewared/plugins/replication/methods.py
+1,285-1,20783 files not shown
+2,596-1,63389 files

LLVM/project 52eb051clang/test/Driver openmp-invalid-target-id.c

clang: Add OpenMP driver test for invalid target IDs (#209740)

Submit test that already exists in the rocm fork. This stresses
the error cases when using the legacy OpenMP -march target specifier,
which appears to be missing upstream.
DeltaFile
+129-0clang/test/Driver/openmp-invalid-target-id.c
+129-01 files

LLVM/project 437a679clang/docs ClangOffloadBundler.rst, clang/include/clang/Driver OffloadBundler.h

clang-offload-bundler: Remove conflicting-target-ID diagnostic

This was checking that you did not try to combine arches with
any mode vs. a specific mode (e.g, gfx90a and gfx90a:xnack+). I
don't see any point in this diagnostic. All the modes have a natural
interpretation as distinct targets with a selection preference. It's
more defensible to have this rule in the user facing clang driver,
but not the low level binary utilities. This reduces the surface area
of some special case target ID parsing.

Co-authored-by: Claude (Opus 4.8)
DeltaFile
+0-78clang/lib/Driver/OffloadBundler.cpp
+3-40clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
+15-6clang/test/OffloadTools/clang-offload-bundler/basic.c
+0-6clang/docs/ClangOffloadBundler.rst
+0-1clang/include/clang/Driver/OffloadBundler.h
+18-1315 files

LLVM/project cceae35llvm/test/CodeGen/AMDGPU/GlobalISel inst-select-load-global.mir inst-select-load-global-old-legalization.mir

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (41) (#209731)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-old-legalization.mir
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
+45-4594 files not shown
+349-349100 files

LLVM/project f482000clang/test/Driver/print-enabled-extensions aarch64-cortex-a320.c, llvm/lib/Target/AArch64 AArch64Processors.td AArch64Features.td

[AArch64] Remove HCX feature flag from backend (#209477)

This patch removes +hcx option from the llvm and removes guarding of
HCRX_EL2 system register on it.
DeltaFile
+4-6llvm/lib/Target/AArch64/AArch64Processors.td
+1-6llvm/test/MC/AArch64/armv8.7a-hcx.s
+1-5llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
+1-4llvm/lib/Target/AArch64/AArch64Features.td
+1-3llvm/lib/Target/AArch64/AArch64SystemOperands.td
+0-2clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c
+8-2632 files not shown
+8-5838 files

LLVM/project 1980283llvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f32.ll flat-scratch.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (40) (#209730)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
+57-5794 files not shown
+296-296100 files

LLVM/project 161e7fdllvm/docs AMDGPUUsage.rst

Update docs
DeltaFile
+20-13llvm/docs/AMDGPUUsage.rst
+20-131 files

LLVM/project 12f5f33llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll s-barrier-signal-var-gep.ll

[RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.
DeltaFile
+474-0llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+81-74llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
+72-61llvm/test/CodeGen/AMDGPU/s-barrier.ll
+59-43llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+52-14llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+32-32llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
+770-22448 files not shown
+1,234-57454 files

LLVM/project 2c1998dllvm/lib/Target/AMDGPU SIDefines.h AMDGPUMemoryUtils.cpp, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll

Comments
DeltaFile
+4-3llvm/lib/Target/AMDGPU/SIDefines.h
+1-3llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+9-106 files

LLVM/project b8eba57llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp

[AMDGPU] Add synthetic apertures and use them for barriers

Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
DeltaFile
+72-87llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+44-5llvm/docs/AMDGPUUsage.rst
+21-23llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+18-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-0llvm/lib/Target/AMDGPU/SIDefines.h
+9-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+176-1324 files not shown
+186-13710 files

LLVM/project e13698dclang/lib/AST Type.cpp, clang/lib/Sema SemaAMDGPU.cpp

[clang][AMDGPU] Clean-up handling of named barrier type

- Allow the type in struct/classes in very limited circumstances. The goal is to enable creating trivial wrappers around the named barrier variable, but ensure we can't get into situations where things would get awkward. Currently this means we only allow the named barrier in RecordDecls with exactly 1 field, that have no base class, and are not inherited.
- Use a `amdgpu_barrier` LangAS for this type that currently maps to the local AS. This allows easy switching to the barrier AS in a future patch.
DeltaFile
+85-0clang/lib/Sema/SemaAMDGPU.cpp
+72-0clang/test/SemaHIP/amdgpu-barrier.hip
+71-0clang/test/SemaCXX/amdgpu-barrier.cpp
+28-16clang/test/CodeGenHIP/amdgpu-barrier-type.hip
+26-1clang/lib/AST/Type.cpp
+24-0clang/test/SemaOpenCL/amdgpu-barrier.cl
+306-1722 files not shown
+377-3528 files

LLVM/project e41f5aallvm/runtimes CMakeLists.txt

[runtimes] Add explicit offload arch tool dependencies (#206076)

Needed for the offload unittests which detect the target arch at
configure time if not forced by OFFLOAD_TESTS_FORCE_AMDGPU_ARCH. Bug had
been masked by the dependency on flang, which we recently removed in
https://github.com/llvm/llvm-project/pull/198205.

Claude assisted with this patch.
DeltaFile
+7-0llvm/runtimes/CMakeLists.txt
+7-01 files

LLVM/project f10eda4clang/test/OffloadTools/clang-offload-bundler basic.c asserts-on.c

clang-offload-bundler: Fix host dependency of tests (#209720)

Use an explicit linux triple for the host target instead of using the
default/host target and marking most every other system as unsupported.
Fixes not running these tests on macos.

Co-authored-by: Claude (Opus 4.8)
DeltaFile
+72-73clang/test/OffloadTools/clang-offload-bundler/basic.c
+5-6clang/test/OffloadTools/clang-offload-bundler/asserts-on.c
+4-4clang/test/OffloadTools/clang-offload-bundler/zstd.c
+4-4clang/test/OffloadTools/clang-offload-bundler/zlib.c
+3-4clang/test/OffloadTools/clang-offload-bundler/fat-archive-unbundle-ext.c
+2-4clang/test/OffloadTools/clang-offload-bundler/standardize.c
+90-951 files not shown
+91-977 files

LLVM/project c8c0877llvm/test/CodeGen/AMDGPU/GlobalISel combine-fma-sub-mul.ll atomicrmw_fmin.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (39) (#209729)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to 
the folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping 
the redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
+47-4794 files not shown
+242-242100 files

LLVM/project eb2163allvm/test/CodeGen/AMDGPU xnack-subtarget-feature-disabled.ll xnack-subtarget-feature-any.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (38) (#209602)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
+7-7llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-any.ll
+7-7llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
+5-5llvm/test/CodeGen/AMDGPU/xnor.ll
+4-4llvm/test/CodeGen/AMDGPU/xor_add.ll
+3-3llvm/test/CodeGen/AMDGPU/xor3.ll
+33-3313 files not shown
+54-5419 files

OpenBSD/src 2giyHKzusr.sbin/bgpd rde_peer.c rde_update.c

   rework the force_update logic in the adj-rib-out

   On initial connect the system needs to sync the adj-rib-out of a peer with
   the Loc-RIB. This happens via peer_dump() and in this case the system
   needs to push out all updates (but can drop any withdraw).

   To do this a force_update flag was introduced but actually it is better to
   use the mode argument and introduce EVAL_SYNC for this case.
   If mode == EVAL_SYNC adjout_prefix_update needs to force the update and
   adjout_prefix_withdraw can drop the withdraw.

   The other user of peer_dump() is during config reloads where the RIB of a
   peer is altered. In that case the adj-rib-out is first flushed. Because of
   this flush peer_dump can be used to push out all updates.

   This also removes the NOTYET block in peer_generate_update() and
   replaces it with inside up_generate_addpath_all() with a call
   up_generate_addpath().

   OK tb@
VersionDeltaFile
1.80+14-22usr.sbin/bgpd/rde_peer.c
1.201+17-15usr.sbin/bgpd/rde_update.c
1.358+9-5usr.sbin/bgpd/rde.h
1.22+7-5usr.sbin/bgpd/rde_adjout.c
1.709+2-2usr.sbin/bgpd/rde.c
+49-495 files

FreeBSD/ports 6382948net-im/telegram-desktop distinfo Makefile, net-im/telegram-desktop/files patch-Telegram_SourceFiles_platform_linux_specific__linux.cpp patch-CMakeLists.txt

net-im/telegram-desktop: update to 7.0.1 release (+)

Release notes:  https://github.com/telegramdesktop/tdesktop/releases/tag/v6.9.4 \
                https://github.com/telegramdesktop/tdesktop/releases/tag/v7.0.1
DeltaFile
+7-7net-im/telegram-desktop/files/patch-Telegram_SourceFiles_platform_linux_specific__linux.cpp
+0-10net-im/telegram-desktop/files/patch-CMakeLists.txt
+5-5net-im/telegram-desktop/files/patch-Telegram_lib__webview_webview_platform_linux_webview__linux__webkitgtk__library.cpp
+3-3net-im/telegram-desktop/distinfo
+2-2net-im/telegram-desktop/files/patch-Telegram_lib__base_base_platform_linux_base__linux__xcb__utilities.cpp
+1-2net-im/telegram-desktop/Makefile
+18-296 files

LLVM/project c3e55declang/test/Driver openmp-invalid-target-id.c

clang: Add OpenMP driver test for invalid target IDs

Submit test that already exists in the rocm fork. This stresses
the error cases when using the legacy OpenMP -march target specifier,
which appears to be missing upstream.
DeltaFile
+129-0clang/test/Driver/openmp-invalid-target-id.c
+129-01 files

LLVM/project 5b3b76elibcxx/docs ReleaseNotes.rst, libcxx/docs/ReleaseNotes 24.rst

[libc++] Create libc++ 24 release notes (#208814)

Now that the LLVM 23 branch has been created, this adds LLVM 24 release
notes. The release notes contain a few TODOs which will be easy to
address in separate PRs.
DeltaFile
+74-0libcxx/docs/ReleaseNotes/24.rst
+2-1libcxx/docs/ReleaseNotes.rst
+76-12 files

FreeNAS/freenas d827c64src/middlewared/middlewared/api/v26_0_0 container.py, src/middlewared/middlewared/migration 0020_repair_incus_clone_origins.py

Relocate migrated container origins out of legacy .ix-virt

## Problem
Incus containers are ZFS clones of an image snapshot. The incus->container auto-migration relocated each container from `<pool>/.ix-virt/containers/<name>` to `<pool>/.truenas_containers/containers/<name>` with a bare `zfs rename` and did nothing else. A `zfs rename` does not change a clone's `origin`, so a migrated container stayed a clone of a snapshot still living inside `.ix-virt`. `.ix-virt` was visible in the UI and not delete-guarded, so deleting it recursively destroyed those origin snapshots and cascaded into the dependent migrated clones — silently destroying migrated containers.

## Solution
Relocate each container's origin image dataset out of `.ix-virt` before renaming the container, so no migrated container depends on anything under `.ix-virt`.

- **Shared relocation helper** — `container.relocate_container_origin` reads a container's live `origin`; if it points at an image under `.ix-virt/images` or `.ix-virt/deleted/images`, it renames that image dataset into the native `.truenas_containers/images/` tree, tags it `truenas:origin=incus-migration`, and sets `canmount=noauto`. All fan-out clones auto-repoint on the rename; an origin already outside `.ix-virt` is left alone; a relocation failure leaves the container wholly inside `.ix-virt` (best-effort, skip).
- **Migration path** — the incus->container migration calls the helper immediately before renaming each container, and skips any container whose base image cannot be relocated.
- **Repair migration** — new `0020_repair_incus_clone_origins` runs the same relocation over existing `container.container` rows for systems that already ran the old migration.
- **Delete guard** — `.truenas_containers` is added to `INTERNAL_PATHS` so it cannot be deleted out from under running containers; the plugin's own snapshot/clone/destroy calls that touch it now pass `bypass=True`.
- **Image garbage collection** — on container delete, a relocated origin image is destroyed once its last clone is gone, keyed on the `truenas:origin` tag so native image-cache datasets are never reaped. The image dataset is destroyed recursively so any snapshots it later accumulated (e.g. from a periodic snapshot task) do not block reclaim; this is safe because it only runs once the origin snapshot is confirmed clone-free.
- **Safer deletion** — `do_delete` destroys the dataset first (recursively, matching the apps stack, so a container that has snapshots is deletable) and removes the database and libvirt records only once the dataset is confirmed gone, so a failed destroy never orphans the dataset with no row pointing at it; an already-missing dataset is tolerated so a container whose data was lost to the old cascade can still be removed cleanly. Delete is now a single-locked job so concurrent deletes of fan-out siblings cannot race each other's image garbage collection.
- **Active-instance guards** — deleting or renaming a container that is not stopped (running or suspended) is refused; delete additionally accepts `force=True`, which stops it first, mirroring the VM delete flow. The container status model now includes the `SUSPENDED` state it can actually report.
DeltaFile
+124-8src/middlewared/middlewared/plugins/container/container.py
+105-0src/middlewared/middlewared/plugins/container/migrate.py
+41-0src/middlewared/middlewared/migration/0020_repair_incus_clone_origins.py
+11-1src/middlewared/middlewared/api/v26_0_0/container.py
+4-3src/middlewared/middlewared/plugins/container/image.py
+2-1src/middlewared/middlewared/plugins/zfs/utils.py
+287-131 files not shown
+288-147 files

LLVM/project 8c9a6fdmlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Add support for block scaled types in matmul_t (#207851)

Builds on https://github.com/llvm/llvm-project/pull/203894 to enable
MXFP block scaled fotmats within matmul_t.
DeltaFile
+524-41mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+30-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+27-0mlir/test/Dialect/Tosa/ops.mlir
+16-6mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+9-5mlir/lib/Dialect/Tosa/Utils/QuantUtils.cpp
+11-0mlir/test/Dialect/Tosa/invalid_extension.mlir
+617-525 files not shown
+649-5311 files

LLVM/project d3f58ceflang/lib/Optimizer/OpenACC/Support FIROpenACCTypeInterfaces.cpp

[flang][openacc][NFC] remove useAccReductionCombine cl switch (#208756)

Follow-up of https://github.com/llvm/llvm-project/pull/208473 to remove
the switch altogether to simplify the compiler code.
DeltaFile
+0-8flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
+0-81 files

OpenBSD/src OiJpL3Jsys/arch/octeon/dev if_cnmac.c

   cnmac: Fix packet corruption with veb(4)

   Account for VLAN header when setting IP packet offset for TCP/UDP
   checksum offload on transmit. Otherwise cnmac(4) can corrupt packets
   that are sent through veb(4).

   Initial patch from Sergii Rudchenko.
   ether_extract_headers() usage added by me.

   OK kirill@
VersionDeltaFile
1.92+13-4sys/arch/octeon/dev/if_cnmac.c
+13-41 files

OpenBSD/src GnZitsSusr.sbin/bgpd rde_attr.c

   test pointer against NULL not 0; ok claudio@
VersionDeltaFile
1.149+2-2usr.sbin/bgpd/rde_attr.c
+2-21 files

LLVM/project 0dccfdcclang/lib/Driver SanitizerArgs.cpp

[clang][Driver] Remove duplicate KernelAddress sanitizer kind. NFC. (#209079)

Remove the duplicate `SanitizerKind::KernelAddress` entry from the list
of sanitizers incompatible with `TypeSanitizer`.

Found using clang-tidy, with check `misc-redundant-expression`
DeltaFile
+1-1clang/lib/Driver/SanitizerArgs.cpp
+1-11 files

LLVM/project 96a53b1llvm/include/llvm/Transforms/Vectorize SLPVectorizer.h, llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP] Support memory runtime alias checks

Vectorize straight-line code blocked by runtime-checkable may-alias
dependencies by versioning the block. Drop the deps, and if the tree is
profitable, emit base-object address-range overlap checks branching to a
vector fast path or an original-order scalar fallback.

Fixes #201534

Original Pull Request: https://github.com/llvm/llvm-project/pull/203631

Recommit after revert in a9ba4d3fd27a05b31adfeaab5dcd42d8e43c1931,
related to late commit before the release and small after-commit change
request

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/209305
DeltaFile
+824-17llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+315-0llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
+41-10llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
+13-0llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
+1,193-274 files