RuntimeLibcalls: Define vector math libcall signatures in tablegen (#232005)
Give vector math libcalls a signature in tablegen. The vector modf,
sincos and sincospi types now come from the generated signature instead
of being manually constructed, though the attributes are still manually
applied.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[BoundsSafety][Sema] Disallow using a bitfield with __builtin_counted_by_ref() (#231591)
A counter that's a pointer to a bitfield breaks assumptions in
'__builtin_counted_by_ref', which returns a pointer to the counter, but
a bitfield cannot have its address taken causing an ICE.
Link: https://github.com/llvm/llvm-project/pull/228309#pullrequestreview-5494375815
[LV] Require the preheader to be terminated by an unconditional branch. (#232091)
The preheader terminator gets replaced when creating the vector loop. A
preheader terminated by an indirectbr or a switch with a single
destination passes the existing preheader check, but crashes when
executing the plan
This fixes crashes on the added tests in both inner and outer loop
paths.
TableGen: Avoid linear search for register class names
Inferring register classes checked whether a name was already used by
walking the list of all register classes. AMDGPU has thousands of
register classes, so this was a large part of building the register
bank. Keep a set of the names instead.
The 8 AMDGPU tablegen runs that build the register bank each execute
8% to 12% fewer cycles.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[CodeGen] Report an error for a direct inline asm output in memory
An inline asm output returned by value has no memory to write to, yet a
constraint such as "=rm" picks memory, the most general constraint, as
does "=m". SelectionDAG asserted on that ("Can only indirectify direct
input operands!"), and GlobalISel dereferenced a null pointer. Clang
never emits such an output, since it passes the address of a memory
output, but other IR can. Report "cannot handle direct memory outputs
yet for constraint 'm'" instead, like the other inline asm errors there.
Assisted-by: Claude Opus 5.5
[TargetInstrInfo] Fix folding inline asm operands next to tied operands
foldInlineAsmMemOperand() swapped a register operand for the target's
memory operands with MachineInstr::removeOperand(), which asserts when a
later operand is tied, because moving it would break the tie. Inline asm
lists every input after every output, so folding any operand that comes
before another tied pair asserted, e.g. an "rm" input followed by the
input of a "+r" operand, or one of two "+rm" operands. Without
assertions, the moved operands kept stale tie indices. Untie the
operands, rebuild the operand list, and re-tie the remaining pairs at
their new positions.
It also gave up when the register appears in more than one operand, e.g.
one value passed to two "rm" operands, which left the greedy allocator
unable to spill that value at all. Fold every such operand into the
stack slot.
Finally, take MayLoad from the folded operands rather than from every
read of the register: a folded def whose tied use is another virtual
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[MIR] Serialize the "foldable" inline asm register operand flag
The symbolic MIR syntax for inline asm operand flags dropped
InlineAsm::Flag's RegMayBeFolded bit, which marks a register operand
(from an "rm" constraint) that the register allocator may fold to a
stack slot. Printing MIR and parsing it back therefore silently changed
what the allocator was allowed to do, e.g. with -stop-before and
-run-pass, and a test could only set the bit through a raw numeric flag.
Print the bit as a trailing "foldable", as MachineInstr::print() already
does, and parse it back. A tied use stores its matched operand number in
the same bits, so it never prints the marker.
Assisted-by: Claude Opus 5.5
[AMDGPU] Reserve address space 20 for downstream use
NFC
Change-Id: Idadee2338474536df6d49a8706b89695a4e88032
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
