LLVM/project d1823a0 — libc/src/math/generic sin.cpp CMakeLists.txt, utils/bazel/llvm-project-overlay/libc BUILD.bazel

[libc][math] Fix LIBC_MATH_HAS_SMALL_TABLES check in sin.cpp and cos.cpp (#240076)
DeltaFile
+3-1libc/src/math/generic/cos.cpp
+1-1libc/src/math/generic/sin.cpp
+2-0libc/src/math/generic/CMakeLists.txt
+1-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+7-24 files

NetBSD/pkgsrc-wip f77b3f0 — cabal2pkg Makefile distinfo, cabal2pkg/patches patch-src_System_OsString_Posix_Instances.hs patch-cabal2pkg.cabal

cabal2pkg: Update to cabal2pkg-0.1.2

## 0.1.2 -- 2026-11-08

Compatibility changes:

* Fixed build with GHC 9.10. `cabal2pkg` no longer supports GHC 9.8.

New features:

* Added a global option `--fill-column=COLUMN` for specifying page
  width. Currently only used for generating `DESCR` files. Previously it
  was fixed to 80, but now it's defaulted to 76. This options is only meant
  to be used for debugging.
* `cabal2pkg init` now infers a package from the name of the directory if
  no package URI is given. The package is assumed to be available in
  Hackage in this case.

Behaviour changes:

    [66 lines not shown]
DeltaFile
+219-0cabal2pkg/PLIST
+0-20cabal2pkg/patches/patch-cabal2pkg.cabal
+0-15cabal2pkg/patches/patch-src_System_OsString_Posix_Instances.hs
+3-5cabal2pkg/distinfo
+4-3cabal2pkg/Makefile
+226-435 files

FreeNAS/freenas 73e9192 — src/middlewared/middlewared/plugins/container __init__.py lifecycle.py, src/middlewared/middlewared/plugins/vm __init__.py lifecycle.py

Fail graceful VM and container stop when the guest keeps running

## Problem
A graceful `vm.stop` / `container.stop` (no `force`, no `force_after_timeout`, the API default) waited `shutdown_timeout` and then reported SUCCESS even when the guest ignored the shutdown request and was still running. The UI showed the guest as stopped and a graceful container restart then failed on start with "already started". A suspended VM was also left suspended with a successful job, even with `force_after_timeout`, because the post-stop check only looked for `RUNNING`.

## Solution
After the shutdown request, both stop paths check the state again. If the guest has not stopped, it is powered off when `force_after_timeout` is set; otherwise the job fails with an ETIMEDOUT `CallError` saying it did not stop within the timeout. A suspended VM is resumed before the shutdown request so the guest can act on it, and library errors (e.g. stopping a guest that is not running) are raised as `CallError` like start already does. The docstrings describe the new behaviour and the container stop test now expects the graceful stop to fail.
DeltaFile
+20-9src/middlewared/middlewared/plugins/vm/lifecycle.py
+17-9src/middlewared/middlewared/plugins/container/lifecycle.py
+4-4tests/api2/test_container.py
+7-1src/middlewared/middlewared/plugins/container/__init__.py
+3-4src/middlewared/middlewared/plugins/vm/__init__.py
+51-275 files

LLVM/project e26b6cf — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 minmax-reduction-leaf-after-cmp.ll

[SLP] Emit min/max reduction at the root select, not its compare

The min/max matcher accepts select (cmp X, Y), X, Y' with Y' identical
to Y but defined after the compare. Emitting the reduction before the
compare used Y' before its definition. The compare position was needed
only while the reduction replaced the compare uses, removed in D99753.
The root compare now has a single use, so emit at the select, which
all reduced values dominate.

Fixes #240006.

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240133
DeltaFile
+61-0llvm/test/Transforms/SLPVectorizer/X86/minmax-reduction-leaf-after-cmp.ll
+1-17llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+62-172 files

FreeNAS/freenas 5f0d6e7 — src/middlewared/middlewared/plugins/container migrate.py crud.py, src/middlewared/middlewared/plugins/vm crud.py

Validate container configuration values when they are saved

## Problem
Several container settings passed create and update but only failed at start, often as a raw IndexError or ValueError: an unparseable or empty init, a cpuset with whitespace or CPUs that are not online, and a memory limit above host RAM. A missing initdir made start report success for a container that exited immediately.

## Solution
- **Save time**: init must parse to at least one token; cpuset must be well formed and online, and memory within host RAM. The cpuset and memory checks only run when the value changes, so a host that has since lost CPUs or memory does not block unrelated edits.
- **Start time**: initdir must resolve to a directory inside the container root.
- **Migration**: an incus CPU count, or a CPU set or memory limit this host can't satisfy, is dropped with a job log line instead of failing the container.
- An invalid pinned VM cpuset is a validation error instead of an unhandled ValueError, and autostart failures are logged with a traceback. Accepting `0-0` relies on the matching truenas_pylibvirt parser change.
DeltaFile
+44-3src/middlewared/middlewared/plugins/container/lifecycle.py
+34-11src/middlewared/middlewared/plugins/container/crud.py
+45-0src/middlewared/middlewared/pytest/unit/plugins/container/test_config_values.py
+22-2src/middlewared/middlewared/plugins/container/migrate.py
+12-6src/middlewared/middlewared/plugins/vm/crud.py
+6-0src/middlewared/middlewared/utils/cpu/info.py
+163-221 files not shown
+165-237 files

LLVM/project c324fc9 — llvm/test/CodeGen/AArch64 red_mla_f16_f32.ll peephole-insert-subreg.mir

[AArch64] Add tests for inserting 8/16/32 bit register values into 0. NFC (#240132)

peephole-insert-subreg.mir is cleaned up a bit at the same time.
DeltaFile
+352-51llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir
+209-0llvm/test/CodeGen/AArch64/red_mla_f16_f32.ll
+561-512 files

LLVM/project 6e0b2a4 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV revec-strided-store.ll basic-strided-stores.ll

[SLP]Fix stride of reversed strided stores

Keep the store stride in scalar order and apply the reverse in cost and
codegen, matching strided loads. Do not overwrite stride info of
already strided stores when they become reversed after reordering.

Fixes #240004.

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240131
DeltaFile
+8-7llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1-1llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll
+1-1llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-stores.ll
+10-93 files

NetBSD/pkgsrc-wip e22ee87 — . Makefile

add hs-isnull
DeltaFile
+1-0Makefile
+1-01 files

NetBSD/pkgsrc-wip dcdd16e — hs-isnull DESCR COMMIT_MSG

wip/hs-isnull: import IsNull-0.4.0.0

A typeclass to determine if a given foldable type (or other) is empty ~ null ~
invalid. The definition is intentionally vague, to cover types from Either to
Text and Sets.
DeltaFile
+19-0hs-isnull/PLIST
+17-0hs-isnull/Makefile
+14-0hs-isnull/buildlink3.mk
+5-0hs-isnull/COMMIT_MSG
+5-0hs-isnull/distinfo
+3-0hs-isnull/DESCR
+63-06 files

OPNSense/core c83cd64 — src/www interfaces_ppps_edit.php

Interfaces: Devices: Point-to-Point - extend line ending validation to other fields as well.

PR: GHSA-f35q-c34m-pfw3
DeltaFile
+5-2src/www/interfaces_ppps_edit.php
+5-21 files

LLVM/project ddd7529 — llvm/lib/Target/AArch64/GISel AArch64GlobalISelUtils.cpp, llvm/test/CodeGen/AArch64 shift.ll overflow-vec.ll

[GlobalISel][AArch64] Lower vector shift right by register in post-legalizer combiner (#231508)

GlobalISel emitted an extra `neg` for vector right shifts by a non-splat
constant. The negation is now folded into the constant, matching
SelectionDAG.

```llvm
define <16 x i8> @test(<16 x i8> %a) {
  %r = ashr <16 x i8> %a, <i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6, i8 7, i8 6>
  ret <16 x i8> %r
}
```

Before:
```
adrp x8, .LCPI0_0
ldr  q1, [x8, :lo12:.LCPI0_0]
neg  v1.16b, v1.16b
sshl v0.16b, v0.16b, v1.16b

    [9 lines not shown]
DeltaFile
+242-308llvm/test/CodeGen/AArch64/combine-sdiv.ll
+81-92llvm/test/CodeGen/AArch64/overflow-vec.ll
+108-0llvm/test/CodeGen/AArch64/shift.ll
+98-0llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-vshr-to-sshl.mir
+23-30llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
+23-0llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+575-4304 files not shown
+620-45010 files

LLVM/project bdbe428 — llvm/test/Transforms/SLPVectorizer/RISCV revec-strided-store.ll

[SLP][NFC]Add incorrect strided store in revec mode, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240130
DeltaFile
+17-0llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll
+17-01 files

LLVM/project 2001575 — llvm/test/Transforms/SLPVectorizer/RISCV basic-strided-stores.ll

[SLP][NFC]Add a test with incorrect stride stores, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240129
DeltaFile
+25-0llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-stores.ll
+25-01 files

NetBSD/pkgsrc wZSnRdo — lang/python pyversion.mk, lang/python315 buildlink3.mk ALTERNATIVES

   lang/python315: Add an option, pyfreethreading for free-threading

   This is not mature. Some packages do not build with pyfreethreading.
VersionDeltaFile
1.4+7,138-7,137lang/python315/PLIST
1.2+17-14lang/python315/Makefile
1.181+9-3lang/python/pyversion.mk
1.2+9-2lang/python315/options.mk
1.2+4-4lang/python315/ALTERNATIVES
1.2+4-1lang/python315/buildlink3.mk
+7,181-7,1616 files

NetBSD/pkgsrc wUADf6t — lang/python wheel.mk

   lang/python: Remove an extra slash between DESTDIR and PREFIX
VersionDeltaFile
1.27+2-2lang/python/wheel.mk
+2-21 files

LLVM/project 5ef6400 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 loads-from-single-predecessor.ll

[SLP]Fix external uses of the pointers of the jumbled copyable loads

The wide load of the copyable loads uses the pointer of the first load,
which may differ from the main op after reordering. Use it as the root
instruction to correctly detect the pointers, which need extracts.

Fixes https://github.com/llvm/llvm-project/pull/233297#issuecomment-6720659110

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240127
DeltaFile
+58-0llvm/test/Transforms/SLPVectorizer/X86/loads-from-single-predecessor.ll
+3-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+61-02 files

OPNSense/core 3d68473 — src/opnsense/mvc/app/models/OPNsense/Core/ACL ACL.xml, src/opnsense/mvc/app/models/OPNsense/Ntpd/ACL ACL.xml

System: Access - add authority/unrestricted to legacy pages to explain all of these should be handled with additional care (#11160)
DeltaFile
+9-0src/opnsense/mvc/app/models/OPNsense/Core/ACL/ACL.xml
+5-0src/opnsense/mvc/app/models/OPNsense/Ntpd/ACL/ACL.xml
+14-02 files

NetBSD/pkgsrc RGQwl7z — doc CHANGES-2026

   doc: Updated mail/thunderbird-l10n to 159.0
VersionDeltaFile
1.7752+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc qWVzxcT — mail/thunderbird-l10n Makefile distinfo

   mail/thunderbird-l10n: Update to 159.0

   * Sync with mail/thunderbird-159.0.
VersionDeltaFile
1.151+187-187mail/thunderbird-l10n/distinfo
1.157+2-2mail/thunderbird-l10n/Makefile
+189-1892 files

NetBSD/pkgsrc yS4GEnk — doc CHANGES-2026

   doc: Updated mail/thunderbird to 159.0
VersionDeltaFile
1.7751+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc 05TK46J — mail/thunderbird distinfo, mail/thunderbird/patches patch-python_sites_mach.txt patch-third__party_libwebrtc_modules_portal_portal__gn_moz.build

   mail/thunderbird: Update to 159.0

   Changelog:
   159.0:
   What's Fixed

   fixed
   Non-ASCII IMAP tags could exceed server length limits and be rejected

   fixed
   Zoom Text Only option did not work in the View menu

   fixed
   Multiple messages were printed even after canceling the print dialog

   fixed
   Save All and Detach All failed for attachments with invalid filename paths

   fixed

    [339 lines not shown]
VersionDeltaFile
1.10+7-17mail/thunderbird/patches/patch-config_makefiles_rust.mk
1.306+9-9mail/thunderbird/distinfo
1.8+2-11mail/thunderbird/patches/patch-config_gcc-stl-wrapper.template.h
1.3+5-5mail/thunderbird/patches/patch-third__party_libwebrtc_modules_portal_portal__gn_moz.build
1.9+5-5mail/thunderbird/patches/patch-browser_app_profile_firefox.js
1.5+4-4mail/thunderbird/patches/patch-python_sites_mach.txt
+32-512 files not shown
+37-568 files

OpenBSD/ports 4lbYrg6 — x11/cde/patches patch-programs_dtlogin_config_Xstartup_src patch-programs_dtlogin_util_c

   Add bsd_auth support to benefit from LOGIN_SETWSCONSGROUP.
   Mostly cargo cult from xenodm(1).
VersionDeltaFile
1.1+186-0x11/cde/patches/patch-programs_dtlogin_sysauth_c
1.1+135-0x11/cde/patches/patch-programs_dtlogin_session_c
1.1+75-0x11/cde/patches/patch-programs_dtsession_SmLock_c
1.3+1-19x11/cde/patches/patch-programs_dtlogin_config_Xreset_src
1.3+2-15x11/cde/patches/patch-programs_dtlogin_config_Xstartup_src
1.1+17-0x11/cde/patches/patch-programs_dtlogin_util_c
+416-343 files not shown
+442-359 files

LLVM/project 4706770 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer gathered-swapped-vectorized-lanes.ll extract-many-users-buildvector.ll

[SLP] Price gathered lanes of vectorized entries as a shuffle

A gathered lane already vectorized in another entry is moved out of
that vector with a shuffle, which a zero insert price misses. Add the
shuffle cost of these lanes when their insert price is zero.
DeltaFile
+35-32llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-operand-deps-direct-use.ll
+21-22llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
+34-0llvm/test/Transforms/SLPVectorizer/RISCV/gathered-lane-of-vectorized-entry-zve32.ll
+14-15llvm/test/Transforms/SLPVectorizer/AArch64/trimmed-subtree-schedule-operands.ll
+14-12llvm/test/Transforms/SLPVectorizer/gathered-swapped-vectorized-lanes.ll
+20-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+138-817 files not shown
+166-10713 files

LLVM/project 31b1858 — llvm/test/Transforms/SLPVectorizer gathered-swapped-vectorized-lanes.ll, llvm/test/Transforms/SLPVectorizer/AArch64 gathered-lane-of-vectorized-loads.ll

[NFC][SLP] Add tests for gathers of lanes from vectorized entries
DeltaFile
+92-0llvm/test/Transforms/SLPVectorizer/AMDGPU/gathered-load-strided-picks.ll
+58-0llvm/test/Transforms/SLPVectorizer/gathered-swapped-vectorized-lanes.ll
+25-0llvm/test/Transforms/SLPVectorizer/AArch64/gathered-lane-of-vectorized-loads.ll
+175-03 files

FreeBSD/src 9669115 — sys/netinet/tcp_stacks rack.c

Mark Johnsons Claude code found a duplicate call to rack_check_reorder_ack() in rack.c

Mark's Claude code properly points out an interesting bug case where if a new block is
created from a sack aka

        rsm |--------|
    sackblk    |--------->
Then when the new block is created rack_check_reorder_ack() is called and then called again when
the block is actually ack'ed. Proper thing is to *not* in this case call the function and only call
it at the processing to ACK. You leave the hookery side however since that is just transfering
the existing block pointers.

Differential Revision:https://reviews.freebsd.org/D61159
DeltaFile
+4-2sys/netinet/tcp_stacks/rack.c
+4-21 files

LLVM/project 38f7f72 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 freeze-multi-node.ll

[SLP]Do not vectorize the same freeze in several nodes

Each vector freeze may produce its own value for an undef or poison
lane, so a freeze vectorized in more than one node is duplicated.
Gather such bundles instead.

Fixes #240001

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240125
DeltaFile
+6-5llvm/test/Transforms/SLPVectorizer/X86/freeze-multi-node.ll
+9-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+15-52 files

LLVM/project 13bd52b — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 freeze-multi-node.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+6-5llvm/test/Transforms/SLPVectorizer/X86/freeze-multi-node.ll
+9-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+15-52 files

LLVM/project dacbab6 — llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 pmaddubsw.ll combine-pmaddwd.ll

[X86] `combineAdd` - add 256/512-bit handling to `combineAddOfPMADDWD` (#238323)

Fixes #223364
DeltaFile
+262-11llvm/test/CodeGen/X86/combine-pmaddwd.ll
+115-40llvm/test/CodeGen/X86/pmaddubsw.ll
+0-4llvm/lib/Target/X86/X86ISelLowering.cpp
+377-553 files

LLVM/project da54e66 — llvm/include/llvm/Transforms/Vectorize LoopVectorizationLegality.h, llvm/lib/Transforms/Vectorize LoopVectorizationLegality.cpp

[LV] Respect access type and alignment when speculating loads (#229379)

An unconditional access does not make a wider or more strongly aligned
load at the same pointer safe. Track the maximum fixed access size and
alignment for each pointer, skipping scalable accesses. Implemented with
assistance from OpenAI Codex.
DeltaFile
+356-12llvm/test/Transforms/LoopVectorize/predicated-load-access-safety.ll
+33-19llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+14-3llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+403-343 files

LLVM/project a00ed74 — llvm/test/Transforms/SLPVectorizer/X86 freeze-multi-node.ll

[SLP][NFC]Add a test with double freeze, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/240122
DeltaFile
+55-0llvm/test/Transforms/SLPVectorizer/X86/freeze-multi-node.ll
+55-01 files