LLVM/project 7a7c903 — llvm/tools/llvm-profdata llvm-profdata.cpp

[llvm-profdata] Remove exitWithError and LSan leak workaround

With all subcommands propagating llvm::Error to main, exitWithError,
exitWithErrorCode, and the LSan leak suppression workaround are no
longer needed.

Assisted-by: Gemini
DeltaFile
+0-31llvm/tools/llvm-profdata/llvm-profdata.cpp
+0-311 files

LLVM/project 5453f23 — llvm/tools/llvm-profdata llvm-profdata.cpp

[NFCI][llvm-profdata] Propagate Error in loadInput and mergeWriterContexts

Propagate Error from loadInput and mergeWriterContexts in mergeInstrProfile,
supplementInstrProfile, and overlapInstrProfile. In mergeInstrProfile's
ThreadPool, catch errors from worker threads, stop scheduling new jobs,
and return the first encountered fatal error.

Ensure ~WriterContext() consumes any pending unhandled errors in
WriterContext::Errors upon destruction.

Not NFC as destructors are run on the stack and ThreadPool workers exit
earlier on error.

Assisted-by: Gemini
DeltaFile
+64-26llvm/tools/llvm-profdata/llvm-profdata.cpp
+64-261 files

LLVM/project a7d53b8 — llvm/tools/llvm-profdata llvm-profdata.cpp

[NFCI][llvm-profdata] Propagate Error in merge subcommand

Change merge_main and its helpers to return Error and handle it
with reportError in main.

Not NFC as destructors are run on the stack.

Assisted-by: Gemini
DeltaFile
+146-111llvm/tools/llvm-profdata/llvm-profdata.cpp
+146-1111 files

LLVM/project 7ea006c — llvm/tools/llvm-profdata llvm-profdata.cpp

[NFCI][llvm-profdata] Propagate Error in show subcommand

Change show_main and its helpers to return Error and handle it
with reportError in main.

Not NFC as destructors are run on the stack.

Assisted-by: Gemini
DeltaFile
+43-45llvm/tools/llvm-profdata/llvm-profdata.cpp
+43-451 files

LLVM/project dcce818 — llvm/tools/llvm-profdata llvm-profdata.cpp

[NFCI][llvm-profdata] Propagate Error in overlap subcommand

Change overlap_main and its helpers to return Error and handle it
with reportError in main.

Not NFC as destructors are run on the stack.

Assisted-by: Gemini
DeltaFile
+36-34llvm/tools/llvm-profdata/llvm-profdata.cpp
+36-341 files

LLVM/project 5d794d5 — llvm/tools/llvm-profdata llvm-profdata.cpp

[NFCI][llvm-profdata] Propagate Error in order subcommand

Change order_main to return Error and handle it with reportError
in main.

Not NFC as destructors are run on the stack.

Assisted-by: Gemini
DeltaFile
+6-6llvm/tools/llvm-profdata/llvm-profdata.cpp
+6-61 files

LLVM/project af5f13a — llvm/tools/llvm-profdata llvm-profdata.cpp

[NFC][llvm-profdata] Introduce ProfdataError, makeError, and reportError (#228153)

Define ProfdataError, makeError, and reportError, and adapt
exitWithError and exitWithErrorCode to use reportError(makeError(...)).
This establishes the error infrastructure for propagating Error
up to main across incremental commits.

Assisted-by: Gemini
DeltaFile
+80-21llvm/tools/llvm-profdata/llvm-profdata.cpp
+80-211 files

LLVM/project 15cbda4 — clang/lib/Serialization ASTReader.cpp ASTWriter.cpp, clang/unittests/Serialization CMakeLists.txt ResolveImportedPathTest.cpp

[clang][Serialization] Fix latent bug in adjustFilenameForRelocatableAST (#227910)

This patch fixes a latent bug in `adjustFilenameForRelocatableAST`. It
relies on a null terminator, but `PreparePathForOutput` passes in a
`StringRef::data()` that has no null-terminator. Today this is benign as
nothing passes in a path that would hit the attempt at checking for a
null terminator, but future patches will.

The fix both makes the code safer by removing the C string usage, and
handles passing in the base path itself by representing it as `.` and
resolving that back to the (possibly relocated) base path on read.

No test on the writer part as it's not triggerable via an integration or
unit test.

Assisted-by: Claude Code: opus-5.5
DeltaFile
+18-21clang/lib/Serialization/ASTWriter.cpp
+32-0clang/unittests/Serialization/ResolveImportedPathTest.cpp
+4-0clang/lib/Serialization/ASTReader.cpp
+1-0clang/unittests/Serialization/CMakeLists.txt
+55-214 files

LLVM/project 75b218e — llvm/test lit.cfg.py

[lit] Preload ASan runtime for ld64 tests on arm64 too (#227873)

get_asan_rtlib() only preloaded the runtime on x86 hosts. On arm64 this
silently skipped the preload, so ASan-instrumented libLTO.dylib aborts
when ld64 dlopen()s it.

rdar://188411900
DeltaFile
+1-5llvm/test/lit.cfg.py
+1-51 files

LLVM/project c396e38 — llvm/test/Analysis/LoopAccessAnalysis num-iters-for-store-load-conflict.ll, llvm/test/Transforms/LoopVectorize memdep.ll

[LAA,LV] Add additional dependence distance tests. (NFC) (#222109)

Add test with dependence on access of type i8, but widest type is i64
and test with multiple load/store forward deps.

Extra tests for https://github.com/llvm/llvm-project/pull/191867,
showing behavior changes.

PR: https://github.com/llvm/llvm-project/pull/222109
DeltaFile
+60-0llvm/test/Transforms/LoopVectorize/memdep.ll
+59-0llvm/test/Analysis/LoopAccessAnalysis/num-iters-for-store-load-conflict.ll
+119-02 files

LLVM/project abb5ab2 — llvm/lib/Target/AMDGPU VOP3Instructions.td AMDGPU.td, llvm/test/MC/AMDGPU gfx1250-strict_err.s

[AMDGPU] Disable e5m3 conversions on gfx1250-strict (#227861)

Fixes: LCOMPILER-2845
DeltaFile
+9-9llvm/lib/Target/AMDGPU/VOPInstructions.td
+1-7llvm/lib/Target/AMDGPU/VOP1Instructions.td
+8-0llvm/test/MC/AMDGPU/gfx1250-strict_err.s
+2-2llvm/lib/Target/AMDGPU/VOP3Instructions.td
+3-1llvm/lib/Target/AMDGPU/AMDGPU.td
+23-195 files

LLVM/project 5d811c1 — llvm/include/llvm/CodeGen TargetPassConfig.h, llvm/lib/CodeGen TargetPassConfig.cpp

llc: Verify MIR outputs by default

MIR is validated by the machine verifier on read, but by default wasn't
validated on output. This differs from opt, which runs the verifier on
output unless explicitly disabled. -verify-machineinstrs is frequently used as
a much more expensive way of getting the verifier run, since that runs between
every pass.

Run the machine verifier at the end of the pipeline whenever it stops before code
emission. Add -disable-mir-output-verify to suppress this. It is separate from
-disable-verify, which still only controls verification of the IR input. The
extra verifier is skipped when the verifier already runs after every machine
pass, with -verify-machineinstrs in the legacy pass manager or -verify-each in
the new pass manager.

Some tests had to force disabling the verifier in a few tests which already fail
the verifier.

Unlike opt, the driver can't simply verify after the pass manager finishes.

    [5 lines not shown]
DeltaFile
+74-0llvm/test/tools/llc/disable-mir-output-verify.mir
+12-6llvm/lib/CodeGen/TargetPassConfig.cpp
+3-2llvm/lib/Passes/CodeGenPassBuilder.cpp
+5-0llvm/include/llvm/CodeGen/TargetPassConfig.h
+2-2llvm/test/tools/llc/new-pm/start-stop.ll
+3-1llvm/tools/llc/lib/NewPMDriver.cpp
+99-115 files not shown
+108-1311 files

LLVM/project 565bd79 — lldb/include/lldb/Core Disassembler.h, lldb/include/lldb/Target StackFrame.h

[lldb] Remove ConstString from Disassembler (#227810)

Disassembler was using it to store register names in its Operand class.
DeltaFile
+8-7lldb/source/Target/StackFrame.cpp
+5-5lldb/source/Core/Disassembler.cpp
+3-4lldb/include/lldb/Core/Disassembler.h
+3-3lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+2-2lldb/include/lldb/Target/StackFrame.h
+1-1lldb/source/Target/BorrowedStackFrame.cpp
+22-221 files not shown
+23-237 files

LLVM/project 0539024 — libc/src/__support/File dir_scan_impl.h, libc/src/dirent scandir.h scandir.cpp

[libc] Implement scandir and its unit tests (#223198)

scandir is a POSIX function from <dirent.h> header that scans the directory and returns all files
contained within, optionally applying user-provided filtering and comparator functions.

Provide implementation which allows substituting the `Dir` class to allow for dependency
injection to cover various error cases. 
DeltaFile
+250-0libc/test/src/__support/File/dir_scan_impl_test.cpp
+204-0libc/test/src/dirent/scandir_test.cpp
+133-0libc/src/__support/File/dir_scan_impl.h
+39-0libc/src/dirent/scandir.cpp
+28-0libc/src/dirent/scandir.h
+23-0libc/test/src/dirent/CMakeLists.txt
+677-09 files not shown
+750-115 files

LLVM/project 10d4fd1 — mlir/docs ReleaseNotes.md, mlir/include/mlir/Conversion Passes.td

Review feedback and typo fixes
DeltaFile
+22-7mlir/include/mlir/Conversion/Passes.td
+9-8mlir/docs/ReleaseNotes.md
+4-5mlir/unittests/Dialect/AMDGPU/AMDGPUUtilsTest.cpp
+6-1mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
+1-2mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
+1-2mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+43-251 files not shown
+44-277 files

LLVM/project e98c62d —

[CAS] Fix template export for unittest (#227908)
DeltaFile
+0-00 files

LLVM/project 353edd9 — flang/lib/Optimizer/Transforms/CUDA CUFOpConversion.cpp, flang/test/Fir/CUDA cuda-global-addr.mlir cuda-data-transfer.fir

[flang][cuda] Resolve scalar constant address to device copy for reads (#227802)

Example test.cuf:
```
  module m
    integer, constant :: int_0_d = 2
  end module
  program test
    use m
    integer :: e(10)

    e = 0
    e = int_0_d
    print *, e      ! expect 2 (x10)
  end program
```
During lowering, a data transfer from device to host is generated
because reads from a constant scalar consults the device copy. But the
address passed to the cudaMemcpy is the host shadow address. Depending

    [11 lines not shown]
DeltaFile
+56-35flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
+64-0flang/test/Fir/CUDA/cuda-data-transfer.fir
+9-3flang/test/Fir/CUDA/cuda-global-addr.mlir
+129-383 files

LLVM/project 86e7353 — llvm/include/llvm/CAS BuiltinObjectHasher.h, llvm/lib/CAS BuiltinObjectHasher.cpp

[CAS] Fix template export for unittest (#227908)
DeltaFile
+3-3llvm/lib/CAS/BuiltinObjectHasher.cpp
+3-0llvm/include/llvm/CAS/BuiltinObjectHasher.h
+6-32 files

LLVM/project 7380d5b — llvm/test/CodeGen/AArch64 machine-combiner-fma-chain.ll, llvm/test/CodeGen/RISCV machine-combiner-fma-chain.ll

[MachineCombiner][NFC]Add tests for long chain FMA reassociation, NFC (#224126)

Tests for https://github.com/llvm/llvm-project/pull/222676
DeltaFile
+348-0llvm/test/CodeGen/AArch64/machine-combiner-fma-chain.ll
+324-0llvm/test/CodeGen/X86/machine-combiner-fma-chain.ll
+112-0llvm/test/CodeGen/RISCV/machine-combiner-fma-chain.ll
+784-03 files

FreeNAS/freenas d1df37f — src/middlewared/middlewared/api/v28_0_0 pool_dataset.py, src/middlewared/middlewared/plugins/pool_ dataset.py

Move the dataset name space check into the zfs plugin
DeltaFile
+0-7src/middlewared/middlewared/plugins/zfs_/validation_utils.py
+6-1src/middlewared/middlewared/plugins/pool_/dataset.py
+7-0src/middlewared/middlewared/plugins/zfs/name_utils.py
+1-3src/middlewared/middlewared/api/v28_0_0/pool_dataset.py
+2-2tests/api2/test_pool_dataset_create.py
+1-1src/middlewared/middlewared/plugins/zfs/create_rules.py
+17-146 files

LLVM/project d216563 — llvm/test/CodeGen/AMDGPU/GlobalISel ashr.ll lshr.ll

[AMDGPU][GISel] Match constrained shifts across register bank copies
DeltaFile
+2,791-3,362llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+2,618-3,120llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+316-0llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shift-amount-mask.mir
+15-33llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+48-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-fadd-v2-fneg-lo.ll
+14-32llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+5,802-6,5475 files not shown
+5,843-6,60211 files

LLVM/project ed613a7 — clang/include module.modulemap

[clang] Fix the modules build after #224277 (#228223)

https://ci.swift.org/job/llvm.org/job/clang-stage2-Rthinlto/job/main/616/

rdar://188857378
DeltaFile
+1-0clang/include/module.modulemap
+1-01 files

LLVM/project 101b9ff — .github/workflows docs.yml

[Github] Run docs workflow on changes to utils/docs (#227101)

To ensure we catch any regressions premerge.
DeltaFile
+15-13.github/workflows/docs.yml
+15-131 files

LLVM/project 3423e3d — mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp, mlir/lib/Conversion/GPUToROCDL LowerGpuOpsToROCDLOps.cpp

[mlir] Migrate AMDGPU/ROCDL to targets, not chipset versions

**migration tl;dr:** Replace usages of `amdgpu::Chipset` with `ROCDL::TargetInfo`, ideally move from `chipset=` to `arch=`. If you don't use upstream pipelines, call 'TargetInfo::migrateArchFeaturesToModuleFlags` at the appropriate location.

Further note: if you've got a build pipeline that's getting a `gfxXXX` name from something like `rocm_agent_enumerator`, using a full triple name like the ones you get from `rocminfo` is preferred.

`amdgpu::Chipset` was an awkward hack that was hard to keep up to date
with changes in the compiler/new architectures, and didn't properly
support generic targets (and has been strongly disfavored by the
compiler team).

This PR replaces `amdgpu::Chipset` with `ROCDL::TargetInfo`, a
structure that uses LLVM's TargetParser and the underlying LLVM
features tables to get the real nature of the target being compiled
for.

This also helps MLIR move to
new-style (`-mtriple=amdgpuX.YZ-amd-amdhsa`) over "old
style" (`-mtriple=amdgcn-amd-amdhsa -mcpu=gfxXYZ`) triples.

    [36 lines not shown]
DeltaFile
+316-323mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+105-0mlir/test/Dialect/LLVMIR/rocdl-attach-target-arch.mlir
+87-4mlir/lib/Dialect/GPU/Transforms/ROCDLAttachTarget.cpp
+46-40mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
+49-24mlir/test/Dialect/AMDGPU/amdgpu-emulate-atomics.mlir
+30-30mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+633-421103 files not shown
+1,179-718109 files

LLVM/project b4d426e — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.768bit.ll amdgcn.bitcast.960bit.ll

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+43,021-43,093llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+8,092-8,330llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,501-5,654llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+5,473-5,576llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+5,285-5,462llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+4,549-4,668llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+71,921-72,7833,381 files not shown
+214,192-168,9203,387 files

FreeBSD/ports b324cf3 — devel/opengrok pkg-plist Makefile, devel/opengrok/files opengrok.in pkg-message.in

devel/opengrok: depend on opengrok-tools for wrapper script

This is the upstream supported path going forward.
DeltaFile
+16-0devel/opengrok/files/pkg-message.in
+8-6devel/opengrok/Makefile
+0-6devel/opengrok/files/opengrok.in
+3-3devel/py-opengrok-tools/distinfo
+3-1devel/py-opengrok-tools/Makefile
+0-1devel/opengrok/pkg-plist
+30-171 files not shown
+31-177 files

LLVM/project 4c520f2 — mlir/include/mlir/Dialect/LLVMIR ROCDLTargetInfo.h, mlir/lib/Dialect/LLVMIR CMakeLists.txt

[mlir][ROCDL] Add TargetInfo to replace Chipset, allow features queries (#223562)

Add a new ROCDL::TargetInfo struct that parses AMDGPU triples and
target names using the same logic that Clang and LLVM
use (TargetParser) and maintains the set of features available on a
given GPU.

This is an improvement over the old `amdgpu::Chipset` struct since
that was just a version number and often became stale compared to the
knowledge exposed by LLVM, such as gfx1170 having OCP FP8 support even
though other gfx11 chips don't have it.

This struct also allows for moving to new-style
triples (amdgpu9.42-amd-amdhsa vs amdgcn-amd-amdhsa--gfx942, for
example), which is an ongoing migration in other parts of the compiler
that this PR lets us follow.

It also enables compiling for generic targets, like `gfx11-generic`,
which can be run on all chips in a generation.

    [14 lines not shown]
DeltaFile
+334-0mlir/unittests/Dialect/LLVMIR/ROCDLTargetInfoTest.cpp
+242-0mlir/lib/Dialect/LLVMIR/IR/ROCDLTargetInfo.cpp
+193-0mlir/include/mlir/Dialect/LLVMIR/ROCDLTargetInfo.h
+2-0mlir/unittests/Dialect/LLVMIR/CMakeLists.txt
+2-0mlir/lib/Dialect/LLVMIR/CMakeLists.txt
+773-05 files

LLVM/project 23bc218 — clang/test/CodeGenOpenCL builtins-amdgcn-make-buffer-rsrc.cl, llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp

[AMDGPU] Canonicalize num_records to its actual width in InstCombine (#217068)

This PR adds code to InstCombineIntrinsic to change the width of the
num_recods field (by extension or truncation) to the correct width for
the target triple (if a concrete enough target triple has been set) so
that LLVM IR-level optimizations can see the lack of demand for the
high bits, for example.

Assisted by Claude, which also found those buffer lowering edge cases
DeltaFile
+36-44clang/test/CodeGenOpenCL/builtins-amdgcn-make-buffer-rsrc.cl
+22-12llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+21-1llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+1-1llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+80-584 files

FreeNAS/freenas ad31ee5 — tests/api2 test_pool_dataset_create.py

Fold the dataset name space tests into one test
DeltaFile
+10-32tests/api2/test_pool_dataset_create.py
+10-321 files

LLVM/project fde11d5 — llvm/docs WritingAnLLVMPass.md

Docs: remove gdb startup text from WritingAnLLVMPass. (#228236)

It is simply noise for readers of the doc.

Also, it is (incorrectly) flagged by license-compliance scanners as
indicating GPL-licensed content. Simplest to just drop it.
DeltaFile
+0-8llvm/docs/WritingAnLLVMPass.md
+0-81 files