[RISCV] Preserve call-preserved reg mask for LPAD-aligned calls (#210868)
RISCVISelDAGToDAG's lowering of RISCVISD::LPAD_CALL / LPAD_CALL_INDIRECT
to PseudoCALLLpadAlign / PseudoCALLIndirectLpadAlign (introduced in
#177515) only copied the callee, lpad label, chain, and glue operands,
dropping the argument-register and register-mask operands in between.
Without the register-mask operand, the register allocator treats these
calls as clobbering nothing but ra, so values live across the call are
not spilled/reloaded even though the callee is free to clobber
caller-saved registers. This caused a miscompile where a pointer held
live across a call to getcontext() (a returns_twice function) was
corrupted after the call returned, leading to a SIGSEGV in
llvm-test-suite's siod test.
Fix the operand copy to include the argument-register and register-mask
operands, matching the pseudo-instruction operands of a regular
PseudoCALL/PseudoCALLIndirect.
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[clang] Emit diagnostic for typedef+auto missed case in C++98/C23 (#210141)
CheckTypeSpec() converted 'auto' to a storage-class specifier without
checking whether 'typedef' was already set. [dcl.stc]p1 unconditionally
forbids typedef alongside any storage-class specifier regardless of C++
version.
This change add the check for tydef in the code handling auto.
(cherry picked from commit 34436db53d3e4ad36e86019109fb5ceee9bb4d8c)
[Polly][test] Add missing REQUIRES line (#210578)
The test was added by #201859. It's test uses --debug-only which
requires an LLVM_ENABLE_ASSERTIONS-build
(cherry picked from commit 5cae63bd0d31118a15481fc7e5b063a73492d77d)
[mlir][vector] Update CastAway{Extract|Insert}StridedSliceLeadingOneDim (#210902)
Update both:
* CastAwayExtractStridedSliceLeadingOneDim
* CastAwayInsertStridedSliceLeadingOneDim
to use vector.shape_cast, rather than vector.extract and
vector.broadcast, as the canonical form for stripping unit dimensions.
This change was originally implemented by @krzysz00 in #196206, but was
subsequently reverted in #199546. This PR intentionally restores only a
subset of #196206, making it easier to identify and triage any potential
regressions.
Co-authored-by: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
[WebAssembly] Port AsmPrinter
Lots of boilerplate, but this is standard and there's probably not much
we can do to improve the situation until we have deleted the LegacyPM.
Reviewers: dschuff, sbc100, aheejin
Pull Request: https://github.com/llvm/llvm-project/pull/210448
Simplify cloud_sync SyncRWLock internals
I noticed some changes to this code in a previous PR that has
since been merged and realized we're being inefficient when
it comes to the locking primitives. SyncRWLock kept a separate
threading.Lock and wrapped it in a Condition, but a Condition
can own its lock directly. The extra attribute is gone and
every critical section now enters the Condition itself.
Behavior is identical since the lock is never acquired reentrantly.
Also removes FsLockManager._choose_lock, dead code superseded by
_choose_sync_lock.
No public API changes. The only consumers use the manager's lock()
context managers, which are unchanged.
[SLP]Combine fma and fmuladd into a single vector fma node
fmuladd permits the fused form and fma requires it, so a mixed bundle is
vectorized as one vector fma, with fma as the representative to avoid
weakening the fma lanes; an all-fmuladd bundle still stays fmuladd.
Reviewers: bababuck, RKSimon, hiraditya
Pull Request: https://github.com/llvm/llvm-project/pull/211291
[AMDGPU] Add image_atomic_{min,max}_num_flt support to gfx13
GFX13 uses the num_flt suffix as the default assembler name for the 32-bit
FP image atomic min/max instructions. Keep flt as a backward-compatible
alias. GFX12 is unchanged (flt default, num_flt alias).
[mlir][tosa] Combine unranked/ranked tensor types into single type (#209737)
This commit refactors the defined TOSA types to combine unranked and
ranked tensor types into a single type `TosaTensorOf`. This helps
simplify the type definitions and allows all tensor types to support
both unranked and ranked tensors.
NAS-141916 / 26.0.0-RC.1 / work-around a firmware crash on a NVMe SED capable drive that (by yocalebo) (#19390)
we sell. The gist is of the problem is that we were running TCG
initialization commands to the disks in parallel with certain NVMe
register/acquire commands. Because the new SED library is considerably
faster (just issuing commands via kernel interface) this exposed the
crash (i.e. its a race). The OEM is being notified but in the meantime
we'll work around the issue by initializing the SED drives first, and
then reload/start fenced.
Original PR: https://github.com/truenas/middleware/pull/19388
Co-authored-by: Caleb St. John <30729806+yocalebo at users.noreply.github.com>
NAS-141916 / 26.0.0-BETA.3 / work-around a firmware crash on a NVMe SED capable drive that (by yocalebo) (#19389)
we sell. The gist is of the problem is that we were running TCG
initialization commands to the disks in parallel with certain NVMe
register/acquire commands. Because the new SED library is considerably
faster (just issuing commands via kernel interface) this exposed the
crash (i.e. its a race). The OEM is being notified but in the meantime
we'll work around the issue by initializing the SED drives first, and
then reload/start fenced.
Original PR: https://github.com/truenas/middleware/pull/19388
Co-authored-by: Caleb St. John <30729806+yocalebo at users.noreply.github.com>
[AMDGPU][GlobalISel] Don't combine uniform fmin/max into clamp/fmed3 (#211456)
Uniform fmin/fmax/fmed3 makes the reg-bank combiner produce a
clamp/fmed3 with an sgpr-banked destination. As these clamp/fmed3 only
have VALU selection patterns, the sgpr bank cannot be selected. Only
combine when the destination is vgpr-banked.
[PowerPC] improve performance on the isNan and !isNan function in case of -ffp-model=strict (#204170)
For the IR representation:
isnan(x) → %0 = tail call noundef i1 @llvm.is.fpclass.f64(double %x, i32
3)
!isnan(x) → %0 = tail call noundef i1 @llvm.is.fpclass.f64(double %x,
i32 1020)
Under `-ffp-model=strict`, the generic
TargetLowering::expandIS_FPCLASS() is used to lower these when
Subtarget.hasP9Vector() && Subtarget.useCRBits() is false. However,
PowerPC has more optimal assembly sequences for isnan(x) and !isnan(x)
on POWER7/8 and generic PPC targets.
We implement a custom lowering for isnan(x) and !isnan(x) under
`-ffp-model=strict`, using `fcmpu `for POWER7/8 and generic PPC targets,
and` xscmpudp` for targets where VSX is available.
NAS-141916 / 27.0.0-BETA.1 / work-around a firmware crash on a NVMe SED capable drive that (#19388)
we sell. The gist is of the problem is that we were running TCG
initialization commands to the disks in parallel with certain NVMe
register/acquire commands. Because the new SED library is considerably
faster (just issuing commands via kernel interface) this exposed the
crash (i.e. its a race). The OEM is being notified but in the meantime
we'll work around the issue by initializing the SED drives first, and
then reload/start fenced.
[libunwind] XFAIL the za unwind test on Apple targets older than OS 27.0 (#211379)
When linking against the system unwinder on macOS < 27, the test
fails on platforms that support SME.
redis/main port changes:
- use cc instead of ld to link modules for tests; when ld is run directly
this fails on at least i386 and clang+lld sparc64 with "undefined hidden
symbol: __guard_local". ("ld -o commandfilter.so commandfilter.xo -shared"
vs "cc -o commandfilter.so commandfilter.xo -shared")
- add STRICT_ALIGNMENT patch for the internal copy of xxHash
above ok tb@
- drop pkg/MESSAGE referring to test problems, I'm not sure what was
happening before (many tests were failing) but they seem in pretty good
shape at least on i386/amd64 when I run them now. a few failures but
don't seem particularly serious..
[libc++] Remove workaround for Clang < 20 in clang-tidy plugin (#211314)
The clang-tidy plugin is now always built with Clang >= 20, so the
workaround can be removed.
work-around a firmware crash on a NVMe SED capable drive that
we sell. The gist is of the problem is that we were running
TCG initialization commands to the disks in parallel with certain
NVMe register/acquire commands. Because the new SED library is
considerably faster (just issuing commands via kernel interface)
this exposed the crash (i.e. its a race). The OEM is being
notified but in the meantime we'll work around the issue by
initializing the SED drives first, and then reload/start fenced.
adjust include order when building tests, so that internal headers are
pulled in before system headers. fixes build of flavoured version if
unflavoured is installed, as found in bulk builds when pulled in via
p5-OPCUA-Open62541. ok bluhm
[AArch64] Add a ctpop cost with CSSC (#211189)
FEAT_CSSC adds a CNT instruction that can perform ctpop. This adds a
specific cost for it to prevent us from using the neon cost.
