FreeBSD/src 790a676stand/man loader.efi.8

loader.efi(8): document the ia32 loader

Reviewed by:    kib
MFC after:      3 days
Differential Revision:  https://reviews.freebsd.org/D57569

(cherry picked from commit 2e1f5b78976ad09bee41e602e75e79a0c3892e59)
DeltaFile
+12-0stand/man/loader.efi.8
+12-01 files

FreeBSD/src b8a7dd6stand/man loader.efi.8

loader.efi(8): the amd64 loader doesn't do protected mode

The amd64 UEFI loader executes in long mode, not protected mode.

Reviewed by:    kib
MFC after:      3 days
Differential Revision:  https://reviews.freebsd.org/D57568

(cherry picked from commit f771deb193d5743e74515614b7cec40d68ab02ca)
DeltaFile
+2-2stand/man/loader.efi.8
+2-21 files

FreeBSD/src 4aeeb4dstand/man loader.efi.8

loader.efi(8): document the ia32 loader

Reviewed by:    kib
MFC after:      3 days
Differential Revision:  https://reviews.freebsd.org/D57569

(cherry picked from commit 2e1f5b78976ad09bee41e602e75e79a0c3892e59)
DeltaFile
+12-0stand/man/loader.efi.8
+12-01 files

FreeBSD/src e3aba9estand/man loader.efi.8

loader.efi(8): the amd64 loader doesn't do protected mode

The amd64 UEFI loader executes in long mode, not protected mode.

Reviewed by:    kib
MFC after:      3 days
Differential Revision:  https://reviews.freebsd.org/D57568

(cherry picked from commit f771deb193d5743e74515614b7cec40d68ab02ca)
DeltaFile
+2-2stand/man/loader.efi.8
+2-21 files

FreeBSD/ports 9605747devel/jjui distinfo Makefile

devel/jjui: Update 0.10.2 => 0.10.6

Changelogs:
* https://github.com/idursun/jjui/releases/tag/v0.10.3
* https://github.com/idursun/jjui/releases/tag/v0.10.4
* https://github.com/idursun/jjui/releases/tag/v0.10.5
* https://github.com/idursun/jjui/releases/tag/v0.10.6

PR:             296099
MFH:            2026Q2
Approved by:    osa, vvd (Mentors, implicit)

(cherry picked from commit 867ce0413fab9afd3ec53b8d20a4069050577daa)
DeltaFile
+5-5devel/jjui/distinfo
+1-2devel/jjui/Makefile
+6-72 files

FreeBSD/ports 867ce04devel/jjui distinfo Makefile

devel/jjui: Update 0.10.2 => 0.10.6

Changelogs:
* https://github.com/idursun/jjui/releases/tag/v0.10.3
* https://github.com/idursun/jjui/releases/tag/v0.10.4
* https://github.com/idursun/jjui/releases/tag/v0.10.5
* https://github.com/idursun/jjui/releases/tag/v0.10.6

PR:             296099
MFH:            2026Q2
Approved by:    osa, vvd (Mentors, implicit)
DeltaFile
+5-5devel/jjui/distinfo
+1-2devel/jjui/Makefile
+6-72 files

FreeNAS/freenas 96f7222src/middlewared/middlewared/plugins network.py, src/middlewared/middlewared/plugins/zfs resource_crud.py

use doc refs
DeltaFile
+10-6src/middlewared/middlewared/plugins/network.py
+6-5src/middlewared/middlewared/plugins/zfs/resource_crud.py
+16-112 files

LLVM/project 431c300libc/src/string/memory_utils/arm inline_memset.h

[ARM][Libc] Fix ARM big-endian low-end inline_memset byte fills (#198777)

Fix inline_memset_arm_low_end to use the splatted 32-bit fill value for
all byte stores. This ensures that all stores, including unaligned and
trailing byte fills, write the requested repeated byte value on
big-endian ARM.

The low-end ARM memset path already builds value32 as value 0x01010101U
for aligned word/block stores, but its byte-wise prefix and tail
handling still passed the raw 8-bit value * widened to uint32_t. Use
value32 for the byte-wise alignment prefix and final tail loop as well.
This makes the low-end path endian-safe and consistent with
inline_memset_arm_mid_end, fixing incorrect NUL/truncated output in
printf-family formatting and direct memset tests on big-endian ARM
no-unaligned-access targets.
DeltaFile
+3-3libc/src/string/memory_utils/arm/inline_memset.h
+3-31 files

LLVM/project f87ac08lldb/docs/resources lldbgdbremote.md, lldb/include/lldb/Host ProcessLaunchInfo.h

[lldb][Windows] use pipes when no terminal dimensions are sent (#203562)

Plumb `eLaunchFlagUsePipes` from the lldb-dap client through the
gdb-remote protocol to lldb-server so the server's LaunchProcess can
choose between ConPTY and anonymous pipes for inferior stdio.

This is needed for LLDB DAP in `internalConsole` mode.

Fixes `TestDAP_launch_args.py`, `TestDAP_launch_basic.py`, and
`TestDAP_launch_shellExpandArguments_disabled.py` on Windows under
`LLDB_USE_LLDB_SERVER=1`.

rdar://178725958
DeltaFile
+9-6lldb/docs/resources/lldbgdbremote.md
+13-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+8-0lldb/include/lldb/Host/ProcessLaunchInfo.h
+6-2lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+4-1lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
+2-0lldb/source/Host/windows/PseudoConsole.cpp
+42-96 files

LLVM/project c10d23alldb/test/API/tools/lldb-dap/attach-commands TestDAP_attachCommands.py, lldb/test/API/tools/lldb-dap/launch TestDAP_launch_extra_launch_commands.py

[lldb-dap] subscribe to target events at the broadcaster-manager level (#201866)

https://github.com/llvm/llvm-project/pull/200133 added
`wait_for_module_events()` assertions to `TestDAP_attachCommands.py` and
`TestDAP_launch_extra_launch_commands.py`. However, `SetTarget` is
called after the `Run*Commands`, so this fails on Windows, because it
loads modules early during the process startup. The module-load events
are not listened to.

This patch moves the event subscription to
`DAPSessionManager::GetEventThreadForDebugger` and uses
`StartListeningForEventClass` so any target created in this debugger
automatically gets the listener attached. This is the same pattern we
already use for `SBThread` events.

This is a follow up to https://github.com/llvm/llvm-project/pull/201796
which skipped the tests.

rdar://179923440
DeltaFile
+1-18lldb/tools/lldb-dap/DAP.cpp
+11-2lldb/tools/lldb-dap/DAPSessionManager.cpp
+2-2lldb/tools/lldb-dap/EventHelper.cpp
+1-2lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_extra_launch_commands.py
+0-1lldb/test/API/tools/lldb-dap/attach-commands/TestDAP_attachCommands.py
+15-255 files

LLVM/project 64b11dblibcxx/docs/Status Cxx2cIssues.csv Cxx26Issues.csv

[libc++] Add WG21 issues and papers voted in Brno (#204191)

All papers were targeting C++29, so I created new CSV tracking files. A
few papers were forwarded by CWG in plenary but have library wording, so
they are included here. I believe at least some of them will be *nothing
to do*, but should still be included for completeness.

Minor drive-bys:
- rename Cxx2c to Cxx26
- synchronize RST notes from CSVs to Github issues

Assisted by Claude
DeltaFile
+0-348libcxx/docs/Status/Cxx2cIssues.csv
+348-0libcxx/docs/Status/Cxx26Issues.csv
+218-0libcxx/docs/Status/Cxx26Papers.csv
+0-218libcxx/docs/Status/Cxx2cPapers.csv
+44-0libcxx/docs/Status/Cxx29.rst
+0-44libcxx/docs/Status/Cxx2c.rst
+610-6105 files not shown
+705-61411 files

FreeBSD/ports ffdc5c1www/hs-yesod-bin distinfo Makefile, www/hs-yesod-bin/files patch-__cabal__deps_tasty-1.5.3_tasty.cabal

www/hs-yesod-bin: Update 1.6.2.3 => 1.6.2.4

* Remove upstreamed patch

Approved by:            haskell@ (alven@)
Approved by:            db@, yuri@ (Mentors, implicit)
DeltaFile
+195-209www/hs-yesod-bin/distinfo
+1-167www/hs-yesod-bin/Makefile
+163-0www/hs-yesod-bin/Makefile.cabal
+0-11www/hs-yesod-bin/files/patch-__cabal__deps_tasty-1.5.3_tasty.cabal
+359-3874 files

LLVM/project 9befd0bllvm/include/llvm/IR Intrinsics.td, llvm/lib/IR Verifier.cpp

[LLVM][Intrinsics] Add scalar-only and vector-only overload types (#204138)

Add integer/fp overload types that allow only scalar or only vector
types, and adopt them in some existing intrinsics.

Fixed ValueTracking unit test to not exercise invalid vp reduce
intrinsics as they now fail to parse (as opposed to fail to validate).

See
https://discourse.llvm.org/t/rfc-minor-change-in-overloaded-types-for-intrinsics/90880
DeltaFile
+44-27llvm/include/llvm/IR/Intrinsics.td
+0-52llvm/lib/IR/Verifier.cpp
+11-12llvm/unittests/Analysis/ValueTrackingTest.cpp
+13-8llvm/test/Verifier/masked-divrem.ll
+6-6llvm/test/Verifier/reduction-intrinsics.ll
+74-1055 files

FreeBSD/ports f9f6fd4mail/neomutt distinfo Makefile

mail/neomutt: update to 20260616

Release notes: https://github.com/neomutt/neomutt/releases/tag/20260616
DeltaFile
+3-3mail/neomutt/distinfo
+1-1mail/neomutt/Makefile
+4-42 files

LLVM/project 041262dllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp LegalizeVectorTypes.cpp, llvm/test/CodeGen/AMDGPU float-to-arbitrary-fp.ll

[SelectionDAG] Add expansion for llvm.convert.to.arbitrary.fp (#193595)

The expansion converts a native IEEE float to an arbitrary-precision FP
format, returning the result as an integer, following this algorithm:

1. Bitcast the source float to an integer and extract sign, exponent,
and mantissa bit fields via masks and shifts.
2. Classify the input (zero/denormal/normal/Inf/NaN).
3. Normalize the source via FFREXP.
4. Normal path: adjust the exponent bias from source to destination
format and truncate the mantissa with rounding (supports
NearestTiesToEven, TowardZero, TowardPositive, TowardNegative,
NearestTiesToAway).
5. Denormal destination path: when the biased destination exponent is <=
0, shift the mantissa right to produce a denormalized result with
rounding.
6. Handle mantissa overflow from rounding and exponent overflow. Produce
Inf or saturate to max finite, depending on format and saturation flag.
7. Build special-value results (canonical qNaN, signed Inf, signed zero)

    [13 lines not shown]
DeltaFile
+2,457-0llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll
+2,052-0llvm/test/CodeGen/NVPTX/float-to-arbitrary-fp.ll
+1,411-0llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
+414-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+72-23llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+77-0llvm/test/CodeGen/X86/float-to-arbitrary-fp-error.ll
+6,483-2310 files not shown
+6,597-2416 files

FreeBSD/ports 82b19a7www/chawan Makefile distinfo

www/chawan: Update 0.3.2 => 0.4.2

While here, sort LIB_DEPENDS order.

Changelog:
https://git.sr.ht/~bptato/chawan/tree/v0.4.2/item/NEWS

PR:             296100
MFH:            2026Q2
Approved by:    osa, vvd (Mentors, implicit)

(cherry picked from commit 259bb549b12abb7aebb66018814c18d123a791a8)
DeltaFile
+3-3www/chawan/Makefile
+3-3www/chawan/distinfo
+2-1www/chawan/pkg-plist
+8-73 files

FreeBSD/ports 259bb54www/chawan Makefile distinfo

www/chawan: Update 0.3.2 => 0.4.2

While here, sort LIB_DEPENDS order.

Changelog:
https://git.sr.ht/~bptato/chawan/tree/v0.4.2/item/NEWS

PR:             296100
MFH:            2026Q2
Approved by:    osa, vvd (Mentors, implicit)
DeltaFile
+3-3www/chawan/Makefile
+3-3www/chawan/distinfo
+2-1www/chawan/pkg-plist
+8-73 files

LLVM/project 894c214llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU wave-shuffle-patterns-wave64.ll wave-shuffle-patterns.ll

[AMDGPU][InstCombine] Fold identity wave shuffle to its source (#204121)

The constant-shuffle matcher emitted a self-targeting update_dpp
(quad_perm 0xe4) for an identity shuffle instead of eliminating it.
Return the source value when every lane reads itself so the intrinsic
folds away.

Add a separate wave64 test file that drives the matcher with the full
wave64 thread ID (mbcnt.hi(mbcnt.lo)), covering quad_perm and other DPP
forms plus identity folding.
DeltaFile
+114-0llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns-wave64.ll
+5-7llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns.ll
+2-4llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wave.shuffle.ll
+5-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+126-114 files

LLVM/project eea6fd6llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp AMDGPUHWEvents.h

[AMDGPU][InsertWaitCnts] Make HWEvent a BitMask

Follow up from comments on https://github.com/llvm/llvm-project/pull/202886

Make HWEvent a bitmask by default instead of having both the enum, and a separate HWEventSet. This has the advantage of streamlining the code a bit and opening the possibility of adding "modifiers" to events, e.g. I imagine we could now fold "VMemType" into the Events.
We already do this with things like SMEM_GROUP. At least now it's baked into the design.

I opted for a bit more verbosity by taking inspiration from FastMathFlags (FMF): instead of exposing a raw enum, I wrap it in a class w/ helper function. The downside is having to reimplement all the little bitwise ops, but the result is a cleaner, simpler interface than a raw enum (class) w/ many helper functions. I initially tried that but I recoiled at the sight of things like `contains(A, B)` which isn't very clear, while `A.contains(B)` is self explanatory.

Considering HWEvent is a bitmask, I also implemented a simple iterator to iterate over all set bits of the mask, which is a useful thing to have as some APIs in InsertWaitCnt rely on treating one event at a time.
DeltaFile
+100-106llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+109-91llvm/lib/Target/AMDGPU/AMDGPUHWEvents.h
+58-60llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
+28-34llvm/lib/Target/AMDGPU/AMDGPUHWEvents.def
+295-2914 files

LLVM/project 8f7b80bllvm/lib/Analysis Loads.cpp LoopAccessAnalysis.cpp, llvm/test/Transforms/LoopVectorize dereferenceable-info-from-assumption-variable-size.ll

[Loads][LAA] Properly handle multiple deref assumptions (#204083)

The current code uses a `DerefRK = std::max(DerefRK, RK)` pattern, which
mostly "works" by accident. The maximum here is based on RK.ArgValue,
which will be 0 on initialization and then (incorrectly) set to 1 for
variable dereferenceable assumptions, or N for constant ones. So if we
have a single variable dereferenceable assumption, this ends up working.
If we have multiple, or there are also constant assumptions, or we fix
the incorrect ArgValue initialization, this breaks down.

Fix this by individually inspecting the RK values. Do the checks for
each one until we have both align and dereferenceable proven. For the
LAA case, add all the applicable dereferenceable assumptions to the umax
expression.
DeltaFile
+176-14llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-variable-size.ll
+16-17llvm/lib/Analysis/Loads.cpp
+14-16llvm/lib/Analysis/LoopAccessAnalysis.cpp
+206-473 files

FreeBSD/ports 4ad7461sysutils/stackit distinfo Makefile

sysutils/stackit: Update 0.63.0 => 0.64.0

Changelog:
https://github.com/stackitcloud/stackit-cli/releases/tag/v0.64.0

PR:             296103
Approved by:    osa, vvd (Mentors, implicit)
DeltaFile
+5-5sysutils/stackit/distinfo
+1-2sysutils/stackit/Makefile
+6-72 files

LLVM/project 60ad6edclang/lib/CodeGen CGHLSLRuntime.cpp, clang/test/CodeGenHLSL preserve-interface-dce.hlsl preserve-interface.hlsl

Reapply "[clang][SPIR-V] Implement -fspv-preserve-interface (#196404)" (#204249)

This reverts commit 6746898d2bfc086947d86715e065f8dbf74e9690.

[clang][SPIR-V] Re-land -fspv-preserve-interface (#196404)

This had been reverted in #202558 due to a missing symbol
(llvm::removeFromUsedLists). That symbol is now available in main.

@jmmartinez @jplehr could you please review?

I did not need to modify the original PR #196404 . As I described in
https://github.com/llvm/llvm-project/pull/196404#issuecomment-4661219367,
the build failure on `main` was not due to it.

Tested locally. Will watch the bots once the PR is created.
DeltaFile
+69-0llvm/test/CodeGen/SPIRV/preserve-interface.ll
+51-0llvm/test/CodeGen/SPIRV/preserve-interface-dce.ll
+39-5llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+25-0clang/test/CodeGenHLSL/preserve-interface-dce.hlsl
+24-0clang/test/CodeGenHLSL/preserve-interface.hlsl
+15-0clang/lib/CodeGen/CGHLSLRuntime.cpp
+223-54 files not shown
+245-610 files

LLVM/project 2395e65llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-store-i16-stride-5.ll

[X86] Attempt to fold SHUF128(concat(x,y),concat(z,w),0x44) -> concat(x,z) (#204340)

Trying to yak shave the regressions on #201271 led me here - I really
want this to be done generically as a canonicalization inside
combineX86ShufflesRecursively, but hit some issues with the widening
code that is still causing trouble for #45319
DeltaFile
+2,274-2,366llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+214-242llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
+136-148llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
+16-2llvm/lib/Target/X86/X86ISelLowering.cpp
+2,640-2,7584 files

OpenBSD/src EBfeBDuusr.bin/tmux server-client.c

   Fix shifts to 1ULL and check scrollbar even if pane is not being redrawn.
VersionDeltaFile
1.474+8-7usr.bin/tmux/server-client.c
+8-71 files

NetBSD/pkgsrc-wip 2f97fff. Makefile, py-trollius PLIST Makefile

py-trollius: removed; obsolete and unmaintained
DeltaFile
+0-96py-trollius/PLIST
+0-23py-trollius/Makefile
+0-7py-trollius/DESCR
+0-4py-trollius/distinfo
+0-1Makefile
+0-1315 files

LLVM/project 81c35c7llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ISelLowering.h

[AArch64][SVE] Enable known bits for predicated shifts (#200347)

Allow SelectionDAG to query target known-bits information for scalable
vector nodes, and known-bits cases for SVE predicated SHL, SRL and SRA
nodes.

This enables DAG combines to prove disjointness for ORs involving
scalable vector shifts, enabling USRA/SSRA instruction selection.
DeltaFile
+222-8llvm/test/CodeGen/AArch64/sve2-sra.ll
+22-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+16-8llvm/test/CodeGen/AArch64/sve2-sli-sri.ll
+0-5llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.h
+261-245 files

NetBSD/pkgsrc-wip abf408eqtile PLIST Makefile, qtile/patches patch-libqtile_widget_battery.py patch-setup.py

qtile: updated to 0.36.0
DeltaFile
+334-89qtile/PLIST
+11-14qtile/Makefile
+0-24qtile/patches/patch-libqtile_widget_battery.py
+0-15qtile/patches/patch-setup.py
+3-5qtile/distinfo
+348-1475 files

NetBSD/pkgsrc-wip dd9d968py-xcffib PLIST Makefile, py-xcffib/patches patch-xcffib_____init____.py

py-xcffib: updated to 1.12.0
DeltaFile
+21-12py-xcffib/PLIST
+9-8py-xcffib/Makefile
+0-15py-xcffib/patches/patch-xcffib_____init____.py
+3-4py-xcffib/distinfo
+33-394 files

LLVM/project 024c82aclang/test/CodeGen/AArch64 neon-intrinsics.c, clang/test/CodeGen/AArch64/neon subtraction.c

Merge branch 'main' into users/kparzysz/single-check
DeltaFile
+632-322llvm/test/Transforms/GVN/PRE/pre-loop-load-through-select.ll
+215-109llvm/test/Transforms/GVN/PRE/pre-load-through-select.ll
+0-230clang/test/CodeGen/AArch64/neon-intrinsics.c
+199-1clang/test/CodeGen/AArch64/neon/subtraction.c
+110-81llvm/lib/IR/IRBuilder.cpp
+96-51llvm/test/Transforms/GVN/load-select-addr-store-fwd.ll
+1,252-79475 files not shown
+2,424-1,27581 files

Linux/linux 66affa3include/linux audit_arch.h, kernel audit_fsnotify.c audit_watch.c

Merge tag 'audit-pr-20260615' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/audit

Pull audit updates from Paul Moore:

 - Fix a recursive deadlock when duplicating executable file rules

   Avoid multiple lookups and attempted I_MUTEX_PARENT locks when moving
   watched files by passing the already resolved inodes through the
   audit code.

 - Fix removal of executable watch rules after the file is deleted

   Prior to this fix we were unable to remove an executable file watch
   where the file had been previously deleted due to a negative dentry
   check in the code that performs the lookup on the file watches.

 - Convert our basic "unsigned" type usage to "unsigned int".

* tag 'audit-pr-20260615' of git://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/audit:

    [3 lines not shown]
DeltaFile
+22-12kernel/audit_fsnotify.c
+17-8kernel/audit_watch.c
+13-6kernel/audit.h
+9-8kernel/auditfilter.c
+6-6lib/compat_audit.c
+6-6include/linux/audit_arch.h
+73-464 files not shown
+78-5110 files