FreeBSD/ports 475a60ewww/R-cran-webutils Makefile distinfo

www/R-cran-webutils: Update to 1.2.3

Changelog: https://cran.r-project.org/web/packages/webutils/NEWS
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LLVM/project 9cdb421mlir/test/IR invalid-ops.mlir, mlir/test/lib/Dialect/Test TestOpsSyntax.td

[MLIR] Validate directly parsed optional operand types (#212493)

Commit 6c51938067fa ([MLIR] Guard optional operand resolution in
generated op parsers) guarded resolution of every optional operand to
avoid indexing an empty inferred type range. The guard also skipped
resolveOperands when an optional operand was absent but an independently
optional type directive was present. This accepted malformed assembly
and silently discarded the orphan type when printing the operation.

Keep the guard for inferred type resolutions, which may access an empty
optional type vector, but always resolve directly parsed type ranges so
resolveOperands validates operand/type cardinality. Add coverage for
both valid forms and a type-only negative reproducer.
DeltaFile
+12-5mlir/tools/mlir-tblgen/OpFormatGen.cpp
+10-0mlir/test/lib/Dialect/Test/TestOpsSyntax.td
+6-0mlir/test/mlir-tblgen/op-format.mlir
+5-0mlir/test/IR/invalid-ops.mlir
+33-54 files

LLVM/project 02a26cbclang/lib/Driver/ToolChains Hexagon.cpp, clang/test/Driver hexagon-toolchain-linux.c

[Hexagon] Link static PIE executables against rcrt1.o (#210125)

We always selected crt1.o as the CRT start file, regardless of link
mode.

Select rcrt1.o - the self-relocating static-PIE start file when -static
and PIE are active

(cherry picked from commit c45b4e4d00bed488d6ece5608560561732ae5b9e)
DeltaFile
+43-0clang/test/Driver/hexagon-toolchain-linux.c
+8-5clang/lib/Driver/ToolChains/Hexagon.cpp
+51-52 files

LLVM/project ad300a7llvm/include/llvm/IR Instruction.h, llvm/lib/IR Instruction.cpp

[IR] Remove deprecated InsertPosition(Instruction*) constructor (#212640)

This implicit constructor has been marked deprecated since almost 2
years in favor of constructing an InsertPosition from a
BasicBlock::iterator.
Remove it now that in-tree users no longer rely on it.

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+0-3llvm/lib/IR/Instruction.cpp
+0-3llvm/include/llvm/IR/Instruction.h
+0-62 files

FreeBSD/ports c2cdc39mail/stalwart pkg-message Makefile, mail/stalwart/files patch-crates_cli_Cargo.toml stalwart.in

mail/stalwart: Update to 0.16.15

The CLI utility has been splitted into an upcoming separate port
mail/stalwart-cli.

While here:
- properly define dual licensing (AGPLv3 and SELv2)
- mark as broken on i386 since it does not build due to out of memory
- remove obsolete patches and pkg-message
- remove sample configuration file, which is now auto-generated by
  default

Changelog: https://github.com/stalwartlabs/stalwart/blob/v0.16.15/CHANGELOG.md

PR:             295646
Reported by:    Adrian Gschwend <ktk at netlabs.org> (initial patch),
                Herbert J. Skuhra <herbert at gojira.at> (committed patch)
Reviewed by:    mickael.maillot at gmail.com,
                mikael,

    [3 lines not shown]
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+859-869mail/stalwart/distinfo
+429-434mail/stalwart/Makefile.crates
+10-12mail/stalwart/Makefile
+1-20mail/stalwart/files/stalwart.in
+0-19mail/stalwart/files/patch-crates_cli_Cargo.toml
+0-18mail/stalwart/pkg-message
+1,299-1,3725 files not shown
+1,300-1,42611 files

LLVM/project 4d9c130clang/cmake/caches hexagon-unknown-linux-musl-clang-dylib-dist.cmake hexagon-unknown-linux-musl-clang-dist.cmake

[Hexagon] Fix compiler-rt install dir type, scope sanitizers (#209375)

COMPILER_RT_INSTALL_LIBRARY_DIR must be CACHE STRING, not CACHE PATH: a
relative PATH-typed cache entry resolves against the runtimes sub-build
directory instead of CMAKE_INSTALL_PREFIX, misplacing sanitizer libs.

Replace the explicit COMPILER_RT_BUILD_* ON list with
COMPILER_RT_SANITIZERS_TO_BUILD=all, since those options already default
ON upstream and infeasible sanitizers self-exclude via their own
ALL_<X>_SUPPORTED_ARCH lists.

Add FORCE to the dylib overrides so they take effect after
hexagon-unknown-linux-musl-clang-dist.cmake has already cached them OFF.

(cherry picked from commit 34aefe9744fa83fa222d7f28e073c693c2c4ff5b)
DeltaFile
+12-8clang/cmake/caches/hexagon-unknown-linux-musl-clang-dist.cmake
+3-3clang/cmake/caches/hexagon-unknown-linux-musl-clang-dylib-dist.cmake
+15-112 files

LLVM/project 0bb4a64llvm/lib/Target/RISCV RISCVInstrInfo.cpp, llvm/test/CodeGen/RISCV/rvv vmerge-peephole.mir

[RISCV] Don't move memory instructions across calls in isSafeToMove (#212236)

RISCVInstrInfo::isSafeToMove scans the instructions between From and To
to decide whether a memory instruction can be moved, but it only treated
mayStore() instructions as barriers. Calls on RISC-V are modeled with
isCall() and a register mask rather than mayStore(), so a load could be
moved across a call even though the callee may clobber the loaded
memory.

RISCVVectorPeephole::foldVMergeToMask uses this helper via ensureDominates()
to sink a load into a masked load when folding it into a vmerge, which
produced wrong code when the load was sunk past a call.

Instead of hand-rolling the barrier check, call MachineInstr::isSafeToMove
on each intervening instruction to populate SawStore. That is the same
helper used on From below, and it already treats calls (as well as PHIs
and ordered memory references) as stores.

This fixes #212226.

    [3 lines not shown]
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+24-0llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
+2-3llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+26-32 files

LLVM/project fc8295fllvm/docs ReleaseNotes.md

[lldb][Windows] Add missing release notes
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+7-0llvm/docs/ReleaseNotes.md
+7-01 files

LLVM/project 471d32fclang/lib/Headers ptrauth.h

[PAC][Headers] Fix incorrect comment in ptrauth.h (#207265)

The discriminator which is used to sign pointers to v-tables
is not always zero.

(cherry picked from commit 26643a89ddf98e48e986d25ceb10f673735bc7d7)
DeltaFile
+1-2clang/lib/Headers/ptrauth.h
+1-21 files

NetBSD/pkgsrc joLbOaNmeta-pkgs/bulk-test-icu Makefile

   bulk-test-icu: restrict php versions due to php-http4
VersionDeltaFile
1.22+2-1meta-pkgs/bulk-test-icu/Makefile
+2-11 files

FreeBSD/ports d9b5302textproc/py-jinjanator Makefile distinfo, textproc/py-jinjanator/files patch-pyproject.toml

textproc/py-jinjanator: Update to 25.3.1
DeltaFile
+3-3textproc/py-jinjanator/distinfo
+2-2textproc/py-jinjanator/files/patch-pyproject.toml
+1-1textproc/py-jinjanator/Makefile
+6-63 files

LLVM/project f4382bellvm/lib/Target/ARM ARMAsmPrinter.cpp, llvm/test/CodeGen/ARM elf-preemption.ll

[ARM] Exclude TLS symbols from the .reloc/R_ARM_REL32 path (#212549)

The .reloc branch in emitMachineConstantPoolValue fired for any
isWeakForLinker() + isDSOLocal() symbol, including TLS (thread_local)
weak symbols. R_ARM_REL32 is wrong for TLS: TLS symbols need
TLS-specific relocations (R_ARM_TLS_GD32 etc.). Using R_ARM_REL32 for a
TLS symbol produces a wrong address at runtime.

This broke the 2-stage ARM 32-bit buildbots: stage 1 (with the .reloc
branch) miscompiled stage 2's BPF codegen (BTFDebug.cpp references
llvm::sys::sandbox::Enabled, an inline thread_local weak variable),
causing a SIGSEGV in the BPF Assembly Printer.

Add a regression test (tls_weak_var in elf-preemption.ll) verifying that
TLS weak symbols get TLSGD/TPOFF, not R_ARM_REL32.

Fix #212545
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+35-0llvm/test/CodeGen/ARM/elf-preemption.ll
+5-4llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+40-42 files

LLVM/project 40f95afutils/bazel/llvm-project-overlay/llvm BUILD.bazel

[Bazel] Fixes c2fa412 (#212688)

This fixes c2fa4128681863d92b2fe1615beb73e2ed62876f (#212353).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=c2fa4128681863d92b2fe1615beb73e2ed62876f

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
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+12-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
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FreeBSD/ports eb58566textproc/py-jinjanator-plugins Makefile, textproc/py-jinjanator-plugins/files patch-pyproject.toml

textproc/py-jinjanator-plugins: Catch py-hatchling update

Reported by:    pkg-fallout
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+1-1textproc/py-jinjanator-plugins/files/patch-pyproject.toml
+1-0textproc/py-jinjanator-plugins/Makefile
+2-12 files

LLVM/project 161f2f7clang/lib/Basic/Targets AMDGPU.cpp, clang/lib/Driver OffloadBundler.cpp

Fixes and merge
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+8-4clang/lib/Basic/Targets/AMDGPU.cpp
+4-3clang/lib/Driver/OffloadBundler.cpp
+12-72 files

LLVM/project 0629daaclang/include/clang/Basic TargetID.h, clang/lib/Basic TargetID.cpp

clang: Use TargetID parsing from AMDGPUTargetParser

We had grown 2 parallel parsing implementations for
triple+gpu name+feature flag target ID strings. Mostly
eliminate the redundant clang version.

Co-authored-by: Claude (Opus 4.8)
DeltaFile
+30-165clang/lib/Basic/TargetID.cpp
+48-50clang/lib/Driver/ToolChains/AMDGPU.cpp
+27-41clang/lib/Driver/OffloadBundler.cpp
+7-33clang/include/clang/Basic/TargetID.h
+18-14clang/lib/Basic/Targets/AMDGPU.h
+17-14clang/lib/Basic/Targets/AMDGPU.cpp
+147-3175 files not shown
+172-34111 files

LLVM/project 848eac2clang/test/OffloadTools/clang-offload-bundler basic.c

test
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+11-0clang/test/OffloadTools/clang-offload-bundler/basic.c
+11-01 files

LLVM/project 113f08dclang/include/clang/Basic TargetID.h, clang/lib/Basic TargetID.cpp

Fix offload bundler usage of getConflictTargetIDCombination
DeltaFile
+14-9clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
+11-9clang/include/clang/Basic/TargetID.h
+12-2clang/lib/Driver/OffloadBundler.cpp
+9-4clang/lib/Driver/Driver.cpp
+2-3clang/lib/Basic/TargetID.cpp
+48-275 files

LLVM/project cf8b0adllvm/lib/Target/WebAssembly WebAssemblyTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/WebAssembly cast.ll

[WebAssembly] Fix v8i16-to-v8f32 uitofp cost (#212501)

I think there was a wrong duplication here. The WebAssembly SIMD
conversion cost table accidentally duplicated the
`UINT_TO_FP` entry for `v8i8` to `v8f32`. As a result, the unsigned
`v8i16` to `v8f32` conversion missed the target-specific table entry and
fell back to the generic cost of 5 instead of the intended cost of 10.

I've added ` llvm/test/Analysis/CostModel/WebAssembly/cast.ll` which I
think is good here as it would help test other casting errors in the
future too.
DeltaFile
+16-0llvm/test/Analysis/CostModel/WebAssembly/cast.ll
+1-1llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
+17-12 files

FreeBSD/src b72f9bfsys/kern vfs_syscalls.c

statfs(2): allow to interrupt busying

There are probably more places which could benefit from allowing to
interrupt vfs_busy() calls at syscalls top level.

Requested by:   Peter Eriksson <pen at lysator.liu.se>
Reviewed by:    jah, markj
Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Differential revision:  https://reviews.freebsd.org/D58477
DeltaFile
+1-1sys/kern/vfs_syscalls.c
+1-11 files

FreeBSD/src fb4d7bdsys/kern vfs_subr.c, sys/sys mount.h

vfs_busy(): add MBF_PCATCH flag to allow interrupting the sleep

Reviewed by:    jah, markj
Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Differential revision:  https://reviews.freebsd.org/D58477
DeltaFile
+16-1sys/kern/vfs_subr.c
+2-1sys/sys/mount.h
+18-22 files

LLVM/project 4e326b4llvm/lib/Analysis BlockFrequencyInfoImpl.cpp

[BFI] Remove redundant getHeaderIndex lookup in adjustLoopHeaderMass. NFC (#212679)

getHeaderIndex(Loop.Nodes[H]) is H.
DeltaFile
+1-1llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
+1-11 files

LLVM/project ab99380llvm/lib/Target/X86 X86InstrAVX512.td X86InstrSSE.td, llvm/test/CodeGen/X86 stack-folding-fp-avx1.ll fp-strict-scalar-inttofp-fp16.ll

[X86] Fix redundant zeroing operations when casting ints to FP vectors (#212065)
DeltaFile
+180-0llvm/test/CodeGen/X86/vector-uint-to-fp-zero.ll
+121-0llvm/test/CodeGen/X86/vector-sint-to-fp-zero.ll
+22-33llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
+47-0llvm/lib/Target/X86/X86InstrSSE.td
+8-10llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll
+18-0llvm/lib/Target/X86/X86InstrAVX512.td
+396-436 files

FreeBSD/ports 6324501databases Makefile, databases/php-memvector distinfo pkg-descr

databases/php-memvector: add new ports.

PR:             296871
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+20-0databases/php-memvector/Makefile
+8-0databases/php-memvector/pkg-descr
+3-0databases/php-memvector/distinfo
+1-0databases/Makefile
+32-04 files

LLVM/project fdbb411llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp Triple.cpp

AMDGPU: TableGen the subarch triple name table

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+87-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+2-45llvm/lib/TargetParser/Triple.cpp
+23-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+17-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+4-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+133-655 files

LLVM/project 9c326c8llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: Eliminate old macro driven processor name parsing

Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+167-106llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+72-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+2-2llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+241-1513 files

LLVM/project 36f3990llvm/lib/TargetParser AMDGPUTargetParser.cpp, llvm/utils/TableGen/Basic AMDGPUTargetDefEmitter.cpp

AMDGPU: TableGen the subarch to processor name mapping table

Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical GPU
name) with a generated table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+23-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+61-5llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+84-482 files

LLVM/project 67df2d4llvm/lib/Target/AMDGPU GCNProcessors.td AMDGPUTargetParser.td, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: TableGen subarch to major subarch table

Replace the hand-written AMDGPUMajorFamilies array with a
generated lookup table. Adds a special case for the major
arches missing a concrete generic target definition (we probably
should just define those to avoid this).

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+86-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+20-56llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+8-0llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
+6-0llvm/lib/Target/AMDGPU/GCNProcessors.td
+120-764 files

LLVM/project f17f940clang/lib/Basic/Targets AMDGPU.cpp, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

AMDGPU: Handle more TargetParser queries in tablegen

Previously we had various enum switches. Start generated tables
indexed by enums. Avoid some special cases by defining the dummy
"generic" and "generic-hsa" targets as real processors.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+63-82llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+87-30llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+7-4llvm/lib/Target/AMDGPU/GCNProcessors.td
+2-5clang/lib/Basic/Targets/AMDGPU.cpp
+2-4llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+4-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+165-1253 files not shown
+172-1269 files

LLVM/project c2fa412llvm/include/llvm/TargetParser AMDGPUTargetParser.def, llvm/lib/Target/AMDGPU AMDGPUTargetParser.td GCNProcessors.td

AMDGPU: Generate TargetParser table from TableGen (#212353)

Migrate .def file to tablegen. The initial TargetParser
AMDGPU backend only handled R600. Extend to modern targets.
Stub out some tablegen definitions which will be used in future
changes.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+255-191llvm/lib/Target/AMDGPU/GCNProcessors.td
+0-155llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
+117-7llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+22-22llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+35-7llvm/test/TableGen/AMDGPUTargetDefErrors.td
+28-2llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
+457-3846 files not shown
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