LLVM/project 1b2ccc1llvm/test/Transforms/LoopUnroll loop-probability-one.ll, llvm/test/Transforms/LoopUnroll/branch-weights-freq unroll-complete.ll unroll-partial-unconditional-latch.ll

[LoopUnroll] Fix freqs for unconditional latches: introduce tests (#191008)

This patch introduces all tests for PR #179520 but with current results
so that it is easier to see which results PR #179520 improves. This
patch should not land without PR #179520.
DeltaFile
+530-0llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-complete.ll
+280-0llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial-unconditional-latch.ll
+211-53llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-epilog.ll
+122-85llvm/test/Transforms/LoopUnroll/loop-probability-one.ll
+2-1llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial.ll
+1,145-1395 files

LLVM/project a20fea8llvm/test/CodeGen/AMDGPU fdiv.ll fdiv_flags.f32.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f64.ll fdiv.f16.ll

[AMDGPU] Use WriteSALUDummy for v_div_scale* (#191670)

This uses the new HWWriteRes for v_div_scale*

For an explanation of why we want to do this , see
https://github.com/llvm/llvm-project/pull/190095 . In short, the
scheduler will not try to cover the full latency of the instructions
without this new modelling.

For a clear example of this, see the changes to
llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir in the git log of
this PR.
DeltaFile
+269-269llvm/test/CodeGen/AMDGPU/fdiv.ll
+198-198llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
+196-196llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+120-120llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+45-157llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
+100-100llvm/test/CodeGen/AMDGPU/freeze-binary.ll
+928-1,04011 files not shown
+1,103-1,15717 files

LLVM/project cc216c4clang/lib/Sema SemaTemplate.cpp, clang/test/AST ast-dump-template-decls-json.cpp ast-dump-decl-context-json.cpp

[clang] fix some places where used decls were not marked as referenced
DeltaFile
+272-267clang/test/AST/ast-dump-template-decls-json.cpp
+31-28clang/test/AST/ast-dump-decl-context-json.cpp
+12-12clang/test/AST/ast-dump-decl.cpp
+17-0clang/test/AST/ast-dump-templates.cpp
+8-3clang/lib/Sema/SemaTemplate.cpp
+4-4clang/test/SemaTemplate/make_integer_seq.cpp
+344-31420 files not shown
+378-34726 files

LLVM/project e344124llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVTargetTransformInfo.h, llvm/test/CodeGen/RISCV/rvv bitreverse-vp.ll fixed-vectors-bitreverse-vp.ll

[RISCV] Remove codegen for vp_bitreverse, vp_bswap (#191643)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off 2 intrinsics from #179622.
DeltaFile
+1,619-1,823llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
+1,390-1,556llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
+788-972llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
+661-826llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
+2-9llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+0-2llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+4,460-5,1886 files

LLVM/project 68c10f6llvm/include/llvm/Support BranchProbability.h, llvm/lib/Transforms/Utils LoopUnroll.cpp LoopUnrollRuntime.cpp

[LoopUnroll] Record conditional latch info (#182403)

This patch makes no functional change and so introduces no new tests or
documentation, but it is not merely refactoring.

This patch gathers conditional latch info needed for PR #179520, which
fixes block frequencies when LoopUnroll converts a conditional latch in
an unrolled loop iteration to unconditional. Without PR #179520, this
patch is useless and should not land.
DeltaFile
+42-2llvm/lib/Transforms/Utils/LoopUnroll.cpp
+2-2llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
+1-0llvm/include/llvm/Support/BranchProbability.h
+45-43 files

FreeBSD/ports 48a7dd8deskutils/mytetra distinfo Makefile

deskutils/mytetra: update the port to version 1.44.232

While here, rephrase the COMMENT (inspired by provided
RPM spec file).

Reported by:    portscout
DeltaFile
+3-3deskutils/mytetra/distinfo
+2-2deskutils/mytetra/Makefile
+5-52 files

FreeBSD/ports b36cd4dsysutils/ansible-sshjail Makefile, sysutils/ansible-sshjail/files patch-sshjail.py

sysutils/ansible-sshjail: Fix at runtime with latest ansible

Import patch from upstream Pull request to allow it to work properly
with new ansible release.

Obtained from:  https://github.com/austinhyde/ansible-sshjail/pull/46
DeltaFile
+96-0sysutils/ansible-sshjail/files/patch-sshjail.py
+1-0sysutils/ansible-sshjail/Makefile
+97-02 files

LLVM/project f1a99ffflang/lib/Optimizer/Analysis AliasAnalysis.cpp, flang/test/Transforms licm-non-addressable-resource.mlir

[flang] Recognize non-addressable resources in FIR AA. (#191577)

Same as in #187423 change for CSE, we can assume that an effect
on a non-addressable resource cannot affect memory pointed to
by 'location'.
DeltaFile
+25-0flang/test/Transforms/licm-non-addressable-resource.mlir
+6-0flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
+31-02 files

LLVM/project b07a025flang/include/flang/Optimizer/Dialect FIROps.td, flang/include/flang/Optimizer/HLFIR HLFIROps.td

[flang] Make more [HL]FIR operations Pure. (#191309)

This patch addresses cases where an operation seems obviously Pure to me.

Made-with: Cursor
DeltaFile
+259-0flang/test/Transforms/licm.fir
+14-14flang/include/flang/Optimizer/Dialect/FIROps.td
+1-1flang/include/flang/Optimizer/HLFIR/HLFIROps.td
+274-153 files

LLVM/project c8430e2llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Expand `auto *MiddleBlock = ...`
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-11 files

LLVM/project 5f42836llvm/lib/Transforms/Vectorize VPRecipeBuilder.h

Update doc comment for replaceWithFinalIfReductionStore
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+4-41 files

LLVM/project 6d39df0llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 st1-lane.ll merge-store.ll

[AArch64] Add tablegen patterns for store of high-half. (#190320)

This helps remove the extract but mean less efficient addressing modes.
DeltaFile
+54-132llvm/test/CodeGen/AArch64/st1-lane.ll
+14-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+3-2llvm/test/CodeGen/AArch64/merge-store.ll
+3-2llvm/test/CodeGen/AArch64/arm64-stur.ll
+1-2llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
+75-1385 files

LLVM/project 9a6d5a0llvm/test/Transforms/LoopVectorize/AArch64 memop_widening.ll ordered-reduction-with-invariant-stores.ll

noalias + updated comment in/rename the test
DeltaFile
+0-114llvm/test/Transforms/LoopVectorize/AArch64/memop_widening.ll
+107-0llvm/test/Transforms/LoopVectorize/AArch64/ordered-reduction-with-invariant-stores.ll
+107-1142 files

LLVM/project 0dc230fllvm/lib/Transforms/Vectorize VPRecipeBuilder.h VPlanTransforms.cpp

Swap operands order in VPRecipeBuilder::replaceWithFinalIfReductionStore
DeltaFile
+2-2llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+2-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+5-53 files

FreeBSD/ports 03627c8comms/klog pkg-plist Makefile

comms/klog: Fix build take two

Delete %%PORTDOCS%% prefix
Bump PORTREVISION
DeltaFile
+11-11comms/klog/pkg-plist
+1-1comms/klog/Makefile
+12-122 files

LLVM/project 05411b9llvm/lib/Transforms/IPO SampleProfileMatcher.cpp

[SamplePGO] Optimize the basename matching logic for matching unused profiles (#191523)

This change optimizes the basename matching logic in
`SampleProfileMatcher::matchFunctionsWithoutProfileByBasename` by
replacing the existing O(N*M) nested loop with an O(N+M) hash-based
lookup, while strictly preserving the original matching semantics. The
previous implementation relied on a substring heuristic
(`ProfName.contains(BaseName)`) to bypass expensive demangling
operations during the nested iteration; however, in codebases with
common or overlapping function names, this heuristic frequently
evaluated to true, resulting in redundant demangling and quadratic time
complexity. The updated approach demangles each profile name exactly
once and utilizes a `StringMap` to perform O(1) lookups against the
orphan functions. This eliminates the need for the substring pre-check
while maintaining the exact same constraints: establishing a strict 1:1
mapping between orphaned IR functions and profile entries, and correctly
identifying and rejecting ambiguous matches where multiple entities
share the same demangled basename.

Results in a 9x speedup on a large module with common basenames.
DeltaFile
+12-12llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
+12-121 files

OPNSense/core ae32651src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api FilterController.php, src/opnsense/mvc/app/library/OPNsense/Base UIModelGrid.php

mvc: regression in c81417f26747a9e4e46f608c2791bbae805e79fd, missing descriptions.
DeltaFile
+6-1src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/FilterController.php
+6-1src/opnsense/mvc/app/library/OPNsense/Base/UIModelGrid.php
+12-22 files

NetBSD/pkgsrc pmopHJOdoc CHANGES-2026 TODO

   doc: Updated textproc/rumdl to 0.1.71
VersionDeltaFile
1.2285+2-1doc/CHANGES-2026
1.27088+1-2doc/TODO
+3-32 files

NetBSD/pkgsrc P0gue88textproc/rumdl distinfo Makefile

   textproc/rumdl: update to 0.1.71

   v0.1.71
   Added

       config: support bare rule name in rumdl config get (8369fb1)

   Fixed

       config: move test module to end of flavor.rs to satisfy clippy items_after_test_module (e30714d)
       config: load user config alongside discovered markdownlint project config (c0f79c1)
       config: display global.flavor as lowercase quoted string in rumdl config output (b162295)

   v0.1.70
   Fixed

       MD044: do not flag proper names inside bare-domain link text (56a45df)

   v0.1.69

    [9 lines not shown]
VersionDeltaFile
1.19+4-4textproc/rumdl/distinfo
1.21+2-2textproc/rumdl/Makefile
1.8+0-0textproc/rumdl/cargo-depends.mk
+6-63 files

NetBSD/pkgsrc MmfFO2jdoc CHANGES-2026

   doc: Updated devel/mise to 2026.4.11
VersionDeltaFile
1.2284+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc 2NxkFsUdevel/mise distinfo cargo-depends.mk, devel/mise/patches patch-.._vendor_rattler__pty-0.2.9_src_unix_pty__process.rs

   devel/mise: update to 2026.4.11

   This is an update over 36 releases which is impossible to reproduce here.
   Check upstream changelog for details.
VersionDeltaFile
1.103+1,124-712devel/mise/distinfo
1.102+373-236devel/mise/cargo-depends.mk
1.1+28-0devel/mise/patches/patch-.._vendor_rattler__pty-0.2.9_src_unix_pty__process.rs
1.108+2-2devel/mise/Makefile
+1,527-9504 files

LLVM/project 23361e1libc/src/__support/math CMakeLists.txt copysignf16.h, utils/bazel/llvm-project-overlay/libc BUILD.bazel

[libc][math] Refactor copysign family to header-only (#182137)

Refactors the copysign math family to be header-only.

Closes https://github.com/llvm/llvm-project/issues/182136

Target Functions:
  - copysign
  - copysignbf16
  - copysignf
  - copysignf128
  - copysignf16
  - copysignl

---------

Co-authored-by: bassiounix <muhammad.m.bassiouni at gmail.com>
DeltaFile
+88-3utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+65-0libc/src/__support/math/CMakeLists.txt
+36-0libc/src/__support/math/copysignf16.h
+31-0libc/src/__support/math/copysignf128.h
+30-0libc/src/__support/math/copysignf.h
+30-0libc/src/__support/math/copysign.h
+280-320 files not shown
+537-6126 files

FreeBSD/ports a580cddtextproc/gtk-doc distinfo Makefile

textproc/gtk-doc: update to 1.36.1

PR:             294439
DeltaFile
+3-3textproc/gtk-doc/distinfo
+1-1textproc/gtk-doc/Makefile
+4-42 files

FreeBSD/ports 9d7c6d5sysutils/lnav distinfo Makefile

sysutils/lnav: Update 0.13.2 => 0.14.0

Changelog:
https://github.com/tstack/lnav/releases/tag/v0.14.0

Port changes:
* Mark broken for i386.

PR:             294448
Reported by:    Marcel Bischoff <marcel at herrbischoff.com> (maintainer)
Approved by:    osa, vvd (mentors)
MFH:            2026Q2

(cherry picked from commit fa5570175477c5e35c82d394bdd78757b893c914)
DeltaFile
+3-3sysutils/lnav/distinfo
+4-1sysutils/lnav/Makefile
+7-42 files

FreeBSD/ports fa55701sysutils/lnav distinfo Makefile

sysutils/lnav: Update 0.13.2 => 0.14.0

Changelog:
https://github.com/tstack/lnav/releases/tag/v0.14.0

Port changes:
* Mark broken for i386.

PR:             294448
Reported by:    Marcel Bischoff <marcel at herrbischoff.com> (maintainer)
Approved by:    osa, vvd (mentors)
MFH:            2026Q2
DeltaFile
+3-3sysutils/lnav/distinfo
+4-1sysutils/lnav/Makefile
+7-42 files

OpenBSD/src VwcOZUXlib/libc/time ctime.3

   Document RETURN value for timegm(3)

   APIs with in-band errors that conflate the error with a legitimate return
   value are about the worst you can get. Near and dear to my heart is the API
   aptly described as "gibbering eidritch horror" by beck: ASN1_INTEGER_get(3).
   Adapt the wording of its RETURN VALUES to timegm() and mktime(), for which
   Dec 31, 1969 at 23:59:59 will yield the error return -1 and thereby errata.

   Missing docs pointed out by claudio a while back and yesterday by deraadt

   ok deraadt millert
VersionDeltaFile
1.51+7-4lib/libc/time/ctime.3
+7-41 files

LLVM/project 9a690a2llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/AArch64 memop_widening.ll

Fix bug/add test
DeltaFile
+114-0llvm/test/Transforms/LoopVectorize/AArch64/memop_widening.ll
+1-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+115-12 files

LLVM/project 69fe566llvm/lib/Transforms/Vectorize VPlanTransforms.h

Add doc comment
DeltaFile
+2-0llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+2-01 files

LLVM/project c1cc3b3llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h

Apply code review suggestions
DeltaFile
+5-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+3-4llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+9-123 files

LLVM/project 4c78affllvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPRecipeBuilder.h

Avoid exposing `RecipeBuilder.getVPBuilder()`
DeltaFile
+1-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-2llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+1-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+2-43 files