13,415,456 commits found in 8 milliseconds
LLVM /project 2cfd8fd — llvm/include/llvm/CodeGen MIRYamlMapping.h, llvm/lib/CodeGen/MIRParser MIRParser.cpp Merge branch 'users/mssefat/anti-hints-pr3-amdgpu-apply' into users/mssefat/anti-hints-pr4-amdgpu-pre-ra
LLVM /project 81673c8 — llvm/include/llvm/CodeGen MIRYamlMapping.h, llvm/lib/CodeGen/MIRParser MIRParser.cpp Merge branch 'users/mssefat/anti-hints-pr2-mir-serialize' into users/mssefat/anti-hints-pr3-amdgpu-apply
LLVM /project 99d15ad — llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.cluster.load.async.to.lds.ll llvm.amdgcn.cluster.load.ll [AMDGPU] Downgrade cluster loads in strict mode
LLVM /project bc9a3b8 — llvm/lib/Support FoldingSet.cpp, llvm/test/Analysis/CostModel/AArch64 sve-fround.ll fround.ll Merge branch 'main' into users/chinmaydd/refactor-wave-eu-queries LLVM /project bbedf74 — llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine ucmp.ll scmp.ll [InstCombine] Fold scmp/ucmp of extended operands (#218871)
Fixes #202467
`scmp`/`ucmp` compare their operands, and both `sext` and `zext` are
monotonic with respect to the unsigned order (`sext` additionally
preserves the signed order). So a common extension on both operands can
be dropped and the compare done in the narrower type:
scmp (sext X), (sext Y) --> scmp X, Y
scmp (zext X), (zext Y) --> ucmp X, Y
ucmp (ext X), (ext Y) --> ucmp X, Y
Zero-extended values are non-negative, which is why a signed compare of
them becomes an unsigned compare of the narrow operands.
Both operands must use the same extend opcode and source type. Since
these intrinsics are not commutative, the extend is looked for on either
side, and a constant operand is narrowed instead when truncating and
[4 lines not shown ] LLVM /project 7bd8ed7 — llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-private-object-vgprs.mir Propagate object liveness to every changed successor, not only back edges
LLVM /project 98fd900 — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-budget.ll Diagnose an object that does not fit the function's register budget
LLVM /project 4f7cb45 — llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-divergent.ll Treat a sub-dword VGPR-memory load as divergent too
LLVM /project 13fdd84 — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-allocate.ll as-vgpr-across-call.ll Do not add a second lifetime start when allocating VGPRs again
LLVM /project 9130a1e — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-across-call.ll as-vgpr-private-object-vgprs.mir Allocate and reserve registers for address space 13 objects
LLVM /project 464579b — llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-index-demanded-bits.ll Regenerate the demanded-bits expectations for the gfx1250 entry sequence
LLVM /project 629593c — llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-asm-clobber.ll Diagnose inline asm that clobbers a VGPR-memory object's registers
LLVM /project 89f44dc — llvm/lib/Target/AMDGPU SIInstructions.td SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-lower-idx-ops.mir Inherit the M0 operand when expanding the sub-dword VGPR-memory pseudos
LLVM /project e0a433d — llvm/lib/Target/AMDGPU AMDGPULowerIdxOps.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-lower-idx-ops.mir as-vgpr-verifier.mir Check the encodings of the sub-dword VGPR-memory accesses
LLVM /project 75365d9 — llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits-encoding.ll as-vgpr-bits.ll Regenerate the sub-dword expectations for the M0 setup change
Do not describe sub-dword VGPR-memory accesses by index and width
LLVM /project 577188d — llvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-verifier.mir as-vgpr-lower-idx-ops.mir Adopt subarch triples in the sub-dword tests and drop the redundant VALU
LLVM /project caea2af — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp Document the sub-dword access rules for the VGPR address space
LLVM /project 134f754 — llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits.ll as-vgpr-index-demanded-bits.ll Fix tests
LLVM /project 5a6629f — llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits-control-flow.ll Test sub-dword VGPR-memory accesses across control flow
Simplify the sub-dword VGPR-memory pseudo definitions
LLVM /project 5236ffe — llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-verifier-m0.mir Verify operand invariants of the VGPR-memory indexed accesses
NFC: track the downstream implementation more closely
LLVM /project 060788f — llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-index-demanded-bits.ll Test the bit-offset half of the VGPR-memory demanded-bits combine
Cover the remaining VGPR-memory operand invariants
Also build the sub-dword VGPR-memory tests for wave64
LLVM /project 49030a2 — llvm/lib/Target/AMDGPU AMDGPULowerIdxOps.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits.ll Run AMDGPULowerIdxOps for optnone functions in AMDGPULowerIdxOps
LLVM /project 4498473 — llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits.ll as-vgpr-unsupported.ll Correctly diagnose the mis-aligned sub-dowrd accesses instead of miscompiling them
LLVM /project fbb8899 — llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-lower-idx-ops.mir Add a MIR test for AMDGPULowerIdxOps
LLVM /project c31ac9d — llvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-unsupported.ll as-vgpr-bits.ll Add support for sub-dword types for address space 13
