Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)"
This re-applies commit f21e3593371c049380f056a539a1601a843df558 along
with the compile fix failure introduced in
8ab79377740789f6a34fc6f04ee321a39ab73724 before the initial patch was
reverted and fixes for the previously observed assert failure.
We were hitting the assert in the HIP Blender due to a combination of
two issues that could happen when rematerializations are being rolled
back.
1. Small changes in slots indices (while preserving instruction order)
compared to the pre-re-scheduling state meand that we have to
re-compute live ranges for all register operands of rolled back
rematerializations. This was not being done before.
2. Re-scheduling can move registers that were rematerialized at
arbitrary positions in their respective regions while their opcode
is set to DBG_VALUE, even before their read operands are defined.
This makes re-scheduling reverts mandatory before rolling back
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[CodeGen][NPM] dump slot index info with -debug while running LiveIntervals (#173488)
matches legacy. tests such as "CodeGen/AMDGPU/liveness.mir" and
"CodeGen/AMDGPU/phys-partial-liveness.mir" use this.
[Darwin] CMake warning when building sanitized libLTO on Darwin with system sanitizer library (#176976)
Due to a system security policy, libLTO built with `LLVM_USE_SANITIZER`
and a toolchain (i.e. Xcode) sanitizer library cannot be loaded into the
toolchain `ld`. This only affects Darwin.
This adds a warning when users try to do this, and suggests a workaround
(use just-built sanitizer libraries).
This affected the lldb-cmake-sanitized job:
https://github.com/llvm/llvm-zorg/commits/main/zorg/jenkins/jobs/jobs/lldb-cmake-sanitized
rdar://168502870
[AMDGPU][GlobalISel] Add RegBankLegalize rules for SMED3 and CVT_PK_I16_I32 (#176596)
These opcodes are created together for the i64->i16 signed clamp
pattern.
[Clang][WebAssembly] Fix crash when using __funcref in C++ code (#176237)
Enable address space map mangling for the WebAssembly target. This fixes
a crash in the Itanium name mangler when trying to mangle types with the
wasm_funcref address space qualifier in C++ mode.
Fixes #176154
[AMDGPU][Scheduler] Revert all regions when remat fails to increase occ.
When the rematerialization stage fails to increase occupancy in all
regions, the current implementation only reverts the effect of
re-scheduling in regions in which the increased occupancy target could
not be achieved. However, given that re-scheduling with a higher
occupancy target puts more pressure on the scheduler to achieve lower
maximum RP at the cost of potentially lower ILP as well, region
schedules made with higher occupancy targets are generally less
desirable if the whole function is not able to meet that target.
Therefore, if at least one region cannot reach its target, it makes
sense to revert re-scheduling in all affected regions to go back to
a schedule that was made with a lower occupancy target.
This implements such logic for the rematerialization stage, and adds a
test to showcase that re-scheduling is indeed interrupted/reverted as
soon as a re-scheduled region that does not meet the increased target
occupancy is encountered.
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[AMDGPU][Scheduler] Simplify scheduling revert logic
When scheduling must be reverted for a region, the current
implementation re-orders non-debug instructions and debug instructions
separately; the former in a first pass and the latter in a second pass
handled by a generic machine scheduler helper whose state is tied to the
current region being scheduled, in turns limiting the revert logic to
only work on the active scheduling region.
This makes the revert logic work in a single pass for all MIs, and
removes the restriction that it works exclusively on the active
scheduling region. The latter enables future use cases such as
reverting scheduling of multiple regions at once.
While the instruction order produced should be identical to what it was
before, small changes in slot indices of re-scheduled MIs yield
different RA decisions and significant test churn.
Improve pwenc handling
Add a common pwenc_rename function that resets caches on
config upload parsing and other places where we replace the
pwenc file. This also ensures that we never have a partially-
written pwenc file (for example sent by remote HA node).
When we rename / replace the pwenc file we'll keep a backup
of the old on so that we have potential to rebuild old
config if needed.
[PPC] Fix suspicious AltiVec VAVG patterns (#176891)
The existing ((X+Y+1)>>1) patterns didn't correct handle overflow, like
the VAVG instructions would
Remove the old patterns and correctly mark the altivec VAVGS/VAVGU
patterns as matching the ISD::AVGCEIL opcodes - the generic DAG folds
will handle everything else
I've updated the vavg.ll tests to correct match ISD::AVGCEILS/U patterns
and added the old tests as negative "overflow" patterns that shouldn't
fold to VAVG instructions
Fixes #174718
[LLVM][CodeGen] Remove pass initialization calls from pass constructors (#173061)
- Remove pass initialization calls from pass constructors.
- For some passes, add the initialization to `initializeCodeGen` or
`initializeGlobalISel`.
- Remove redundant initializations from llc and X86 target for some
passes.
[X86][Clang] allow CRC32 intrinsics to be used in constexp (#173908)
Mostly inspired by https://github.com/llvm/llvm-project/pull/152971
CRC32 implementation using reversed polynomial that does not match an
Intel manual, can be changed to canonical implementation if required (if
there is a canonical implementation we should use, please attach a link)
Closes #168881
Part of #30794
[ReachingDefAnalysis] Detect entry block correclty. (#176803)
Before a block was deemed an entry block if it did not have any
predecessors, which is wrong: entry block can be a loop header.
[IR] Make dead_on_return attribute optionally sized
This patch makes the dead_on_return parameter attribute optionally require a number
of bytes to be passed in to specify the number of bytes known to be dead
upon function return/unwind. This is aimed at enabling annotating the
this pointer in C++ destructors with dead_on_return in clang. We need
this to handle cases like the following:
```
struct X {
int n;
~X() {
this[n].n = 0;
}
};
void f() {
X xs[] = {42, -1};
}
```
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[RISC-V] Avoid using an allocated extension name in invalid-attributes.s
The Y extension has been allocated and will no longer trigger an error
once https://github.com/llvm/llvm-project/pull/176870 lands. Use 't' to
test this case instead which is still marked as reserved and as far as I
know is not currently reserved for any future extensions.
Pull Request: https://github.com/llvm/llvm-project/pull/177094
Address review
* move the update DB handling to original location
* raise CallError if we filesystem.file_receive called for pwenc
* add dedicated pwenc.replace method that is only valid if
called by remote node in truenas ha.
[AMDGPU][SPIRV] Correctly lower huge device function arguments (#176921)
In the ABIInfo implementations for both the SPIRV and AMDGPU targets,
the lowering of arguments too large to fit into registers is currently
prone to integer overflows when determining the number of needed
registers for the arguments. This causes arguments so large that they
need more registers than an `unsigned` can represent to look like they
fit into the available registers. To avoid this, the function for
determining the required number of registers is changed to return a
64-bit unsigned integer value instead.
Note that the SPIR-V target currently trips the verifier due to a check
that arguments passed by value don't exceed the representable size. This
also affects other targets, such as x86 and is outside the scope of
these changes.
See https://github.com/llvm/llvm-project/issues/118207.
---------
Signed-off-by: Steffen Holst Larsen <HolstLarsen.Steffen at amd.com>
Co-authored-by: Steffen Holst Larsen <HolstLarsen.Steffen at amd.com>
