[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#211715)
This recommits #119826, which taught `MachineLICM` to use
`RegisterClassInfo` when computing register pressure limits so
reserved registers are accounted for (#118787).
The original change was reverted by eeac0ff because it increased
compile time by causing repeated `RegisterClassInfo` computations.
This PR is based on #210826, in which `MachineRegisterClassInfo`
analysis pass was added. `MachineRegisterClassInfo` is required
by `MachineLICM` now, but the intervening machine passes that do
not affect `RegisterClassInfo` now preserve it, so the analysis
is reused instead of recomputed.
Assisted-by: TRAE CLI (GPT-5.5)
[Mips] Fix $gp was restored when used as global register variable (#201778)
The function `eliminateDeadMI` would check `if (MRI.isReserved(Reg))`,
now we only set GP to reserved when `!Subtarget.isABICalls()`. So
`eliminateDeadMI` delete the `move $gp, $4`. And we would restore $gp
after instr selection through `$gp_64 = LD $sp_64, 8`.
Check the module metadata `llvm.named.register.$28` to detect if $28 is
used as global register. Then append new conditon when set $gp to
reserverd status and return CalleeSavedRegs without $gp.
Fix #176546.
GlobalISel: Fix lowerMergeValues when dst type is float (#212795)
Lowering is done in the integer domain. Similar to the type
mismatch when dst is a pointer, make a bitcast when dst is float.
java/openjdk25: Update to version 25.0.4
Includes the following FreeBSD specific fixes:
- Set wxneeded flag for executables on FreeBSD.
- Fix build with clang 22
Sponsored by: The FreeBSD Foundation
AMDGPU: Give v_cvt_sr_pk_bf16_f32 its own subtarget feature (#213150)
v_cvt_sr_pk_bf16_f32 was gated on bf16-cvt-insts, but that feature is
also present on gfx950 where the (non-sr) v_cvt_pk_bf16_f32 was first
added. The stochastic-rounding v_cvt_sr_pk_bf16_f32 was only added
for gfx1250 and has no gfx950 encoding, so it would mis-select and
later hit the "Invalid opcode" assert. Introduce
cvt-sr-pk-bf16-f32-inst, currently added to gfx13 and 125*
Co-authored-by: Claude (Claude-Opus-4.8)
[lldb] Only preload a Module's symbols once (#213094)
Creating several targets for the same file concurrently could deadlock.
Targets share Module objects. Therefore, each concurrent
`SBDebugger::CreateTarget()` call creates a `PreloadSymbols()` task for
the *same* Module. The thread pool running those tasks can pick up a
duplicate preload task for the same Module. The mutex used by the Module
is recursive, so the thread starts the task again, enters the same
`std::call_once` and deadlocks.
Preloading only needs to happen once: it does work taht a later lookup
would do anyway. If it's already in progress, skip it. This deduplicate
the task that causes the deadlock.
At desk, this fixes a timeout in
`api/multiple-targets/TestMultipleTargets.py`, roughly 1/40 runs. To
reproduce the issue, I shrunk the thread pool to 2 threads, which makes
it always timeout.
ixgbe: isolate VF reset state
IXGBE_VF_INDEX() selects a 32-VF register bank. PFMBMEM() selects
one mailbox per VF, while ixgbe_toggle_txdctl() calculates queue
offsets from a VF number. Passing the bank index aliases VF1-31 to
VF0 and VF32-63 to VF1. Resetting one VF can therefore clear the peer
mailbox and leave its transmit queues disabled.
The VF raises its reset event before posting its mailbox request. The
PF checks reset events before mailbox messages. If both are pending,
clearing PFMBMEM during generic reset handling can erase the request
before ixgbe_read_mbx() consumes it. Clear the mailbox only from the
reset-message handler after the request has been read.
Use the VF number for queue toggling and document that API contract.
MFC after: 1 week
igc: Disable ASPM L1.2 on I226 to prevent RX stalls
I226 parts advertise support for the PCIe L1.2 link substate, but a
hardware erratum makes the exit latency from that low-power state
longer than the packet buffer can absorb under load. This stalls the
inbound packet stream. Disabling ASPM system-wide (BIOS or OS ASPM
policy) does not fix it. The L1.2 enable bit must be cleared directly
in the device's own PCIe L1 PM extended capability.
Add igc_is_device_id_i226() to identify affected parts and
igc_disable_broken_aspm_l1_2() to clear the ASPM L1.2 enable bit
on attach and after resume, since PCIe config space can be
reset across a suspend/resume cycle.
Adapted from the Linux igc driver:
0325143b59c6 igc: disable L1.2 PCI-E link substate to avoid
performance issue
1468c1f97cf3 igc: fix disabling L1.2 PCI-E link substate on I226
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[lldb] Convert generic register names in a case insensitive way (#213001)
Part of #212778.
There are 3 types of register name:
* The primary name, displayed by default.
* An optional alias, for example AArch64 "lr" is also "x30".
* Generic convenience names like "sp", "ra" and so on.
The first two types are handled case insensitively, but generic names
were not. For example:
(lldb) register read RA
error: Invalid register name 'RA'
(lldb) register read ra
lr = 0x0000fffff7e27400
In this change I've fixed that.
This does close a workaround for #212778, where you could get to the
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[SystemZ][z/OS] Implement emitCommonSymbol in MCGOFFStreamer (#210179)
Common globals were not emitted in GOFF object files due to a missing
emitCommonSymbol implementation. This adds the implementation to emit
the required SD/ED/PR ESD records in the GOFF object file.
(cherry picked from commit 705d0ec6115cef3232eafe6221f42f78e7b884e8)
[DTLTO] Overlap temporary file removal (#209423)
Deleting the temporary files produced by the DTLTO pipeline can be
expensive on Windows hosts. For a Clang link (Debug build with
sanitizers and instrumentation) using an optimized toolchain (PGO
non-LTO, llvmorg-22.1.0) on a Windows 11 Pro (Build 26200), AMD Family
25 @ ~4.5 GHz, 16 cores/32 threads, 64 GB RAM machine, the mean duration
of the "Remove DTLTO temporary files" time trace scope was 1267.789 ms
(measured over 10 runs).
This patch performs the deletions on a background thread, allowing them
to overlap with the tail of the link to hide this cost.
This is a re-implementation of the asynchronous cleanup idea from
https://github.com/llvm/llvm-project/pull/186988, which had to be
reverted in https://github.com/llvm/llvm-project/pull/189043 because
cleanup was not guaranteed to complete before LLD invoked
timeTraceProfilerCleanup(). In certain cases timeTraceProfilerCleanup()
was called before temporary file deletion had completed in LLD, which
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Mk/Uses/npm.mk: Quote TMPDIR and WRKDIR in shell comparisons
When TMPDIR is unset, the generated shell command becomes:
if [ != ${WRKDIR} ]; then
and /bin/sh reports:
[: !=: unexpected operator
Quoting both variables fixes the issue.
PR: 297181
Reported by: Shin-ichi Nagamura <core at zsc.jp>
GlobalISel: Don't use GISelMatchGenericTypes for floating point opcodes (#212814)
With GISelMatchGenericTypes, AMDGPU had the same input pattern for
G_ATOMICRMW_FADD that checks for v2s16, so the one that is first
in the tablegen table always fires (it was v2f16 in this case).
Should explicitly check for v2f16/v2bf16.
[LoopIdiom] Update MemorySSA when optimizing CRC with lookup table (#213054)
Although the lookup table optimization of CRC loops inserts a `load`
instruction, MemorySSA is not properly updated, and is oblivious to the
new memory access. Insert a memory use immediately after creating the
`load` instruction, and verify MemorySSA at the end of the optimization
if applicable.
[InlineSpiller][AMDGPU] Implement subreg reload during RA spill
Currently, when a virtual register is partially used, the
entire tuple is restored from the spilled location, even if
only a subset of its sub-registers is needed. This patch
introduces support for partial reloads by analyzing actual
register usage and restoring only the required sub-registers.
This improvement enhances register allocation efficiency,
particularly for cases involving tuple virtual registers.
For AMDGPU, this change brings considerable improvements
in workloads that involve matrix operations, large vectors,
and complex control flows.
[AMDGPU] Test precommit for subreg reload
This test currently fails due to insufficient
registers during allocation. Once the subreg
reload is implemented, it will begin to pass
as the partial reload help mitigate register
pressure.
Update to 5.10.2
Upstream changes:
2026-06-14 Maxime DOYEN
Made 5.10.2 release
* bugfix: #2156412 safety approve option mixup
* bugfix: #2156372 currency modification date is not persisted due to extra space in code
* bugfix: #2155966 main window different colours for 0.00 account balances
* bugfix: #2155959 cannot inherit a locked reconciled transaction
* bugfix: #2155844 quick search no longer works in account window (ledger)
2026-06-06 Maxime DOYEN
Made 5.10.1 release
* change: the input field helper icon + fixed some spacing inconsistency
* change: transaction, added some missing input tooltips and reworked existing
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