FreeBSD/ports 8974314 — irc/weechat Makefile distinfo

irc/weechat: Security update to 4.10.4

Security:       e107a804-dc3c-11f1-8135-8447094a420f
MFH:            2026Q4
(cherry picked from commit 90c3f24d417a0637995b994f0b9b98bf7946a36e)
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+3-3irc/weechat/distinfo
+1-1irc/weechat/Makefile
+4-42 files

FreeBSD/ports 5b9132f — graphics/gmic-qt Makefile distinfo

graphics/gmic-qt: Update to 4.0.7

Announce: https://gmic.eu/gmic40/
Changes: https://discuss.pixls.us/t/on-the-road-to-4-1/59573
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LLVM/project 1f4f996 — clang/tools/clang-linker-wrapper ClangLinkerWrapper.cpp, llvm/include/llvm/CodeGen CommandFlags.h

[Support] Pass tool options to parseCommandLineOptions

Add a `parseCommandLineOptions` overload that takes the libraries a tool
opts in to. Replace the global state `RegisterMCToolOptions` with
`mc::getToolOptions` and `codegen::getToolOptions`, which tools pass
where they parse, including lld's `-mllvm`, gold's `-plugin-opt`, and
libLTO's debug options.

`RegisterCodeGenFlags` no longer registers the MC options.

clang-linker-wrapper does not pass the MC options, so it now rejects
them in `-mllvm` and `--offload-opt`, which it forwards to the device
and host link steps. Its wrapper module uses the module's own context
instead of the user's `-mllvm`, as discussed on #233513.

`LibraryOptionsContext` records the library that parsed each argument,
so `assign`, which runs on each ThinLTO backend thread, replays without
looking up the registry.

LLM-aided
DeltaFile
+75-34llvm/lib/Support/CommandLine.cpp
+23-0llvm/unittests/Option/LibraryOptionsTest.cpp
+9-13clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+13-0llvm/include/llvm/Support/CommandLine.h
+5-5llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
+9-0llvm/include/llvm/CodeGen/CommandFlags.h
+134-5228 files not shown
+204-8034 files

LLVM/project 682294d — mlir/lib/Conversion/ComplexToSPIRV ComplexToSPIRV.cpp, mlir/test/Conversion/ComplexToSPIRV complex-to-spirv.mlir

[mlir][SPIR-V] Add ComplexToSPIRV lowering for complex.exp and complex.expm1 (#239284)

Decompose both ops into their real/imaginary component formulas using
GLSL.std.450/OpenCL extended instructions, mirroring the existing
component-decomposition patterns in this file
DeltaFile
+69-0mlir/test/Conversion/ComplexToSPIRV/complex-to-spirv.mlir
+51-2mlir/lib/Conversion/ComplexToSPIRV/ComplexToSPIRV.cpp
+120-22 files

LLVM/project dcfa872 — compiler-rt/test/cfi same-layout-delete.cpp devirtualize-speculatively.cpp

Add compiler-rt reproducers

Created using spr 2.0.0-beta.2
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+25-0compiler-rt/test/cfi/devirtualize-speculatively.cpp
+24-0compiler-rt/test/cfi/same-layout-delete.cpp
+49-02 files

LLVM/project 2bca05e — compiler-rt/test/cfi same-layout-delete.cpp devirtualize-speculatively.cpp

Add compiler-rt reproducers

Created using spr 2.0.0-beta.2
DeltaFile
+25-0compiler-rt/test/cfi/devirtualize-speculatively.cpp
+24-0compiler-rt/test/cfi/same-layout-delete.cpp
+49-02 files

LLVM/project 6e5126f — compiler-rt/test/cfi same-layout-delete.cpp devirtualize-speculatively.cpp

Add compiler-rt reproducers

Created using spr 2.0.0-beta.2
DeltaFile
+25-0compiler-rt/test/cfi/devirtualize-speculatively.cpp
+24-0compiler-rt/test/cfi/same-layout-delete.cpp
+49-02 files

LLVM/project 0c6b878 — compiler-rt/test/cfi devirtualize-speculatively.cpp same-layout-delete.cpp

Add compiler-rt reproducers

Created using spr 2.0.0-beta.2
DeltaFile
+27-0compiler-rt/test/cfi/same-layout-delete.cpp
+25-0compiler-rt/test/cfi/devirtualize-speculatively.cpp
+52-02 files

LLVM/project 9dcb936 — compiler-rt/test/cfi same-layout-delete.cpp devirtualize-speculatively.cpp

Add compiler-rt reproducers

Created using spr 2.0.0-beta.2
DeltaFile
+28-0compiler-rt/test/cfi/devirtualize-speculatively.cpp
+27-0compiler-rt/test/cfi/same-layout-delete.cpp
+55-02 files

LLVM/project a0846ed — compiler-rt/test/cfi same-layout-delete.cpp devirtualize-speculatively.cpp

Add compiler-rt reproducers

Created using spr 2.0.0-beta.2
DeltaFile
+28-0compiler-rt/test/cfi/devirtualize-speculatively.cpp
+27-0compiler-rt/test/cfi/same-layout-delete.cpp
+55-02 files

LLVM/project 113466a — compiler-rt/test/cfi same-layout-delete.cpp devirtualize-speculatively.cpp

Add compiler-rt reproducers

Created using spr 2.0.0-beta.2
DeltaFile
+28-0compiler-rt/test/cfi/devirtualize-speculatively.cpp
+27-0compiler-rt/test/cfi/same-layout-delete.cpp
+55-02 files

LLVM/project 5a99979 — compiler-rt/test/cfi same-layout-delete.cpp devirtualize-speculatively.cpp

Add compiler-rt reproducers

Created using spr 2.0.0-beta.2
DeltaFile
+28-0compiler-rt/test/cfi/devirtualize-speculatively.cpp
+27-0compiler-rt/test/cfi/same-layout-delete.cpp
+55-02 files

LLVM/project 2b19c3f — clang/lib/AST/ByteCode Pointer.h Interp.cpp

[clang][bytecode] Optimize `CheckStore()` (#241345)

Block pointers are the only writable pointer type, which is why we're
checking for them very early in `CheckStore`. Make the distinction more
explicit and use the block and the `PtrView` of the pointer explicitly.
DeltaFile
+28-17clang/lib/AST/ByteCode/Interp.cpp
+3-7clang/lib/AST/ByteCode/Pointer.h
+31-242 files

OpenZFS/src b054fbb — module/zcommon zfs_fletcher.c

Set fletcher4 fastest uses_fpu from both byte orders

The "fastest" fletcher4 implementation is assembled from two
benchmark winners: the native functions come from the fastest native
implementation and the byteswap functions from the fastest byteswap
implementation.  The two can differ.  It still has a single uses_fpu
flag, which FLETCHER_4_FASTEST_FN_COPY() overwrites with each new
winner.  The byteswap pass runs first, so the flag ends up as that of
the native winner.

When a SIMD implementation wins only the byteswap benchmark, as #14219
reports for the in-tree NEON code on a Yitian 710, byteswapped
fletcher4 then runs SIMD code without kfpu_begin() and kfpu_end().
That is reached by reading blocks written on a host of the other byte
order and by receiving such a send stream.  On Linux this can corrupt
the FPU/SIMD register state of user tasks; FreeBSD requires
fpu_kern_enter() for kernel FPU use.  This came in with 78289b8458,
which moved kfpu_begin()/kfpu_end() from each implementation's
init/fini, where the byte order was implied, into the callers.

    [11 lines not shown]
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+10-1module/zcommon/zfs_fletcher.c
+10-11 files

OpenZFS/src 11650ab — lib/libspl/include Makefile.am, lib/libspl/include/sys asm_linkage.h

libspl: remove the unused sys/asm_linkage.h

lib/libspl/include/sys/asm_linkage.h is a userspace copy of
include/sys/asm_linkage.h, but nothing includes it: config/Rules.am
puts include/ before lib/libspl/include, so <sys/asm_linkage.h> is
always include/sys/asm_linkage.h, which already covers userspace and
also defines ASMABI, which this copy lacks.  Since 0b2819872 removed
the gate around its FRAME_BEGIN and FRAME_END but kept the #endif,
the copy does not even preprocess.

Remove it, and stop installing it as libspl/sys/asm_linkage.h.
include/sys/asm_linkage.h is installed with the libzfs headers, so
code built against the installed headers still finds a working one.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Reviewed-by: Rob Norris <rob.norris at truenas.com>
Signed-off-by: Tigerblue77 <37409593+tigerblue77 at users.noreply.github.com>
Closes #19555
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+0-32lib/libspl/include/sys/asm_linkage.h
+0-1lib/libspl/include/Makefile.am
+0-332 files

HardenedBSD/src d059628 — sys/dev/ixgbe if_ix.c

Merge branch 'freebsd/current/main' into hardened/current/master
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+1-3sys/dev/ixgbe/if_ix.c
+1-31 files

HardenedBSD/src 33b40ad — contrib/bsnmp/lib asn1.c

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main
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+1-1contrib/bsnmp/lib/asn1.c
+1-11 files

LLVM/project b97e8d7 — llvm/lib/CodeGen PHIElimination.cpp, llvm/test/CodeGen/Hexagon phi-elim-subreg-lanes-debug-use.mir

PHIElim: Skip debug instructions when scanning for PHI source kills

readsRegister counts debug operands, so a DBG_VALUE of the PHI source
after the first inserted copy was treated as a read. Its slot index is
that of the next real instruction, so a lane kill was recorded there,
extending the lane past its last real read.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
DeltaFile
+51-0llvm/test/CodeGen/Hexagon/phi-elim-subreg-lanes-debug-use.mir
+2-1llvm/lib/CodeGen/PHIElimination.cpp
+53-12 files

LLVM/project 6c7adf2 — llvm/lib/CodeGen PHIElimination.cpp, llvm/test/CodeGen/Hexagon phi-elim-subreg-lanes.mir

Account for lane reads between PHI source copies
DeltaFile
+93-0llvm/test/CodeGen/Hexagon/phi-elim-subreg-lanes.mir
+19-8llvm/lib/CodeGen/PHIElimination.cpp
+112-82 files

LLVM/project c192ff7 — llvm/lib/CodeGen MachineBasicBlock.cpp PHIElimination.cpp, llvm/test/CodeGen/AMDGPU phi-elim-subreg-lanes-multi-pred.mir

PHIElim: Trim PHI source subranges without a full shrinkToUses

This contains a repurposed version of #226209, plus a supplemental fix branch
which was never posted. #228073 was an alternative implementation which landed
first; this replaces the brute-force shrinkToUses with targeted live range
adjustments. Some crude stress test benchmarking suggests this is 2-4x faster
measuring the pass in isolation.

shrinkToUses rescans every use of each subrange which is much more than is
necessary. The only segments that need changing are only the ones ending at the
inserted phi source copies. Instead, track the per-lane copies as they are
inserted and trim each lane at its last read, clamped to the predecessor block,
and stop SplitCriticalEdge from extending subranges for lanes the PHI does not
read. This keeps the live ranges correct while avoiding the per-subrange
rescans. The shrinkToUses implementation's cost scales with the number of uses,
but this remains relatively flat. An example with 640 uses is 7.2x faster.

Because this edits segments surgically instead of recomputing them, it has to
get the bounds exactly right in cases shrinkToUses handles. The clamp to the

    [13 lines not shown]
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+85-25llvm/lib/CodeGen/PHIElimination.cpp
+62-0llvm/test/CodeGen/AMDGPU/phi-elim-subreg-lanes-multi-pred.mir
+46-0llvm/test/CodeGen/Hexagon/phi-elim-subreg-lanes.mir
+18-9llvm/lib/CodeGen/MachineBasicBlock.cpp
+211-344 files

HardenedBSD/ports 6026c41 — devel/cargo-leptos Makefile distinfo, devel/py-pyproject-fmt distinfo

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+871-773devel/cargo-leptos/distinfo
+435-387devel/cargo-leptos/Makefile
+240-0sysutils/py-azure-cli/files/patch-pyproject.toml
+0-216sysutils/py-azure-cli/files/patch-setup.py
+57-63textproc/jql/distinfo
+65-51devel/py-pyproject-fmt/distinfo
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+6,329-5,8671,647 files

LLVM/project 7edee47 — llvm/docs ORCv2.md, llvm/include/llvm/ExecutionEngine/Orc LLJIT.h MapperJITLinkMemoryManager.h

[ORC] Add opt-in per-JITDylib colocating slab allocator (#207970)

MapperJITLinkMemoryManager can now keep each JITDylib's objects within a
single reserved slab, so they stay within range of one another for
direct (e.g. x86-64 REL32, +/-2GB) references instead of needing
GOT/stub indirection.
Adds:

- ColocatePerJITDylib mode (per-JITDylib reservation pools).

- A growth policy (allowSingleSlab/allowMultipleSlabs/setOnSecondSlab)
consulted before reserving a second slab for a pool.

- CreateColocatingInProcess() and defaultSlabSize() (1 GiB on 64-bit, 10
MiB on 32-bit).

- LLJITBuilder::setColocatingSlabAllocator() to opt in.

This is opt-in only; the default memory manager is unchanged.

    [38 lines not shown]
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+248-0llvm/unittests/ExecutionEngine/Orc/MapperJITLinkMemoryManagerTest.cpp
+102-11llvm/lib/ExecutionEngine/Orc/MapperJITLinkMemoryManager.cpp
+100-6llvm/include/llvm/ExecutionEngine/Orc/MapperJITLinkMemoryManager.h
+103-0llvm/unittests/ExecutionEngine/Orc/LLJITTest.cpp
+37-0llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
+30-0llvm/docs/ORCv2.md
+620-171 files not shown
+621-177 files

OpenZFS/src 7101721 — tests/zfs-tests/tests/functional/rsend send_raw_inherited_key.ksh

ZTS: fix send_raw_inherited_key's license boilerplate

The test added in f53b6403ea points at the old illumos.org CDDL URL,
so 'make checkstyle' fails in spdxcheck.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Matthew Ahrens <matt at mahrens.org>
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
Closes #19842
DeltaFile
+1-1tests/zfs-tests/tests/functional/rsend/send_raw_inherited_key.ksh
+1-11 files

OpenZFS/src cdad5a5 — tests/zfs-tests/tests Makefile.am, tests/zfs-tests/tests/functional/cli_root/zfs_change-key zfs_change-key_mismatch.ksh

ZTS: test change-key key mismatch with a pool image

Since f53b6403ea, an incremental raw receive into a dataset that
inherits its key from a passphrase-keyed encryption root keeps the
local key.  zfs_change-key_mismatch used that receive to make a dataset
whose key its encryption root can't unwrap, so the mismatch no longer
happens, 'zfs change-key' succeeds and the test fails every run.

Datasets damaged that way before that change still exist, and
change-key's error path for them (#17425) needs coverage.  Add a small
pool image, made with a build from before that change, that already
holds such a dataset, and run the same checks against it.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Matthew Ahrens <matt at mahrens.org>
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
Closes #19842
DeltaFile
+49-35tests/zfs-tests/tests/functional/cli_root/zfs_change-key/zfs_change-key_mismatch.ksh
+1-0tests/zfs-tests/tests/Makefile.am
+0-0tests/zfs-tests/tests/functional/cli_root/zfs_change-key/blockfiles/key_mismatch.dat.bz2
+50-353 files

LLVM/project 9f57664 — llvm/test/CodeGen/RISCV rvp-insert-subvector.ll

Pre-commit tests
DeltaFile
+154-0llvm/test/CodeGen/RISCV/rvp-insert-subvector.ll
+154-01 files

LLVM/project 28352a2 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-insert-subvector.ll

[RISCV][P-ext] Lower RV32 insert_subvector to extract_subector+concat_vectors.

Assisted-by: Claude
DeltaFile
+1-28llvm/test/CodeGen/RISCV/rvp-insert-subvector.ll
+11-13llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+12-412 files

LLVM/project 2431784 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

[RISCV][P-ext] Use nsrl to for 64-bit extract_vector_elt with variable index on RV32.
DeltaFile
+6-30llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+21-6llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+27-362 files

LLVM/project d466a88 — llvm/test/CodeGen/RISCV rvp-simd-32.ll rvp-simd-64.ll

[RISCV][P-ext] Add tests for extractelement with a variable index. NFC

Assisted-by: Claude
DeltaFile
+109-61llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+36-4llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+145-652 files

LLVM/project a5599e4 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

[RISCV][P-ext] Fix crash on v2i32 extract_vector_elt with a variable index on RV32.

Assisted-by: Claude
DeltaFile
+63-39llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+6-3llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+69-422 files

LLVM/project bf50d0e — llvm/lib/Target/RISCV RISCVInstrInfoP.td RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

[RISCV][P-ext] Make v2i32 insert_vector_elt with constant indices legal for RV32.

We can select to an insert_subreg.

The default lowering created a store+load to stack that got folded,
but left behind the stack slot allocation.

Assisted-by: Claude
DeltaFile
+73-47llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+6-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+5-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+84-473 files