LLVM/project 58bf038llvm/lib/Target/NVPTX NVPTXSubtarget.h NVPTXSubtarget.cpp, llvm/test/CodeGen/NVPTX sm-version.ll sm-110-rename.ll

[NVPTX] Rewrite sm_110* to sm_101* as demanded by PTX version (#218968)
DeltaFile
+44-0llvm/test/CodeGen/NVPTX/sm-110-rename.ll
+27-3llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+8-6llvm/test/CodeGen/NVPTX/sm-version.ll
+1-1llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+80-104 files

OPNSense/core a141823src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api SourceNatController.php

firewall: fix faulty import removal from a15e51634188c

On stable/26.7 Util is still being used.
DeltaFile
+1-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/SourceNatController.php
+1-01 files

FreeNAS/freenas d49b50atests/sharing_protocols/iscsi test_260_iscsi.py

NAS-142672 / 26.0.0-RC.1 / Remove ancient iSCSI tests (by bmeagherix) (#19552)

The same functionality has been replicated using libiscsi.

Original PR: https://github.com/truenas/middleware/pull/19550

Co-authored-by: Brian M <brian.meagher at ixsystems.com>
DeltaFile
+0-383tests/sharing_protocols/iscsi/test_260_iscsi.py
+0-3831 files

LLVM/project 68bdb06llvm/lib/Target/WebAssembly WebAssemblyInstrSIMD.td, llvm/test/CodeGen/WebAssembly f16-intrinsics.ll

[WebAssembly] Add v8f16 bitselect pattern (#218954)
DeltaFile
+12-0llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
+1-1llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+13-12 files

FreeNAS/freenas 8ede398tests/sharing_protocols/iscsi test_260_iscsi.py

NAS-142672 / 25.10.7 / Remove ancient iSCSI tests (by bmeagherix) (#19551)

The same functionality has been replicated using libiscsi.

Original PR: https://github.com/truenas/middleware/pull/19550

Co-authored-by: bmeagherix <118192357+bmeagherix at users.noreply.github.com>
DeltaFile
+0-383tests/sharing_protocols/iscsi/test_260_iscsi.py
+0-3831 files

FreeNAS/freenas 0ba5a21tests/sharing_protocols/iscsi test_260_iscsi.py

NAS-142672 / 27.0.0-BETA.1 / Remove ancient iSCSI tests (#19550)

The same functionality has been replicated using libiscsi.

(cherry picked from commit 33927a311672acefd5df411fac48a5e6b90c0d8c)
DeltaFile
+0-383tests/sharing_protocols/iscsi/test_260_iscsi.py
+0-3831 files

LLVM/project 731cb34llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV zicond-opts.ll

[RISCV] Optimize `(and (i1) f, (setcc a, b, eq))` to use the zicond extension (#217946)

This is a generalization of the previously existing rule, that required
one of the sides of the `setcc` to be zero.

With this commit we now support comparisons between any two variables.
This requires us to insert an additional instruction to compare the two.
But it is still beneficial vs the unoptimized lowering as it reduces 1
instruction in the output.

This fixes one of the issues identified in #179584. Namely `test_lt3`,
now uses `czero.{nez,eqz}` for those cases.

AI Disclosure: I have used AI to help me understand the LLVM build and
test system as well as to understand the existing codebase. The new code
add in this PR is authored by me.
DeltaFile
+124-8llvm/test/CodeGen/RISCV/zicond-opts.ll
+23-7llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+147-152 files

FreeNAS/freenas 2e1ec34src/middlewared/middlewared/plugins cache.py, tests/unit test_cache.py

NAS-142457 / 26.0.0-RC.1 / Fix TTL handling in cache.has_key and get_or_put (by Qubad786) (#19549)

## Problem
`cache.has_key` returned True whenever the TDB record existed and never
looked at the stored `timeout`, so it disagreed with `cache.get` — which
expires the entry and raises `KeyError` — for any key that had expired
but not yet been reaped. The only reaper is a 24h periodic with
`run_on_start=False` whose timer is re-armed from scratch on every
middlewared start, so on a box that restarts more often than daily it
never runs at all and the wrong answer sticks around indefinitely.

Separately, `get_or_put` always stored `now + timeout`, so unlike `put`
— where 0 means "never expires" — `get_or_put(key, 0, method)` stored an
expiry of now and the entry was already expired on the very next read.

## Solution
`has_key` now delegates to `get()` and maps `KeyError` to False.
Delegating rather than repeating the timeout comparison is deliberate:
the bug existed because two methods independently decided what "expired"

    [11 lines not shown]
DeltaFile
+15-9src/middlewared/middlewared/plugins/cache.py
+16-0tests/unit/test_cache.py
+31-92 files

FreeNAS/freenas a8ac9bftests/sharing_protocols/iscsi test_260_iscsi.py

Remove ancient iSCSI tests

The same functionality has been replicated using libiscsi.

(cherry picked from commit f00a9a1ec3d7af12c838ec7c5c06d43b0aae4d50)
DeltaFile
+0-383tests/sharing_protocols/iscsi/test_260_iscsi.py
+0-3831 files

LLVM/project 68fa1e1clang/docs ReleaseNotes.md

Update the release notes.
DeltaFile
+2-0clang/docs/ReleaseNotes.md
+2-01 files

FreeNAS/freenas 33927a3tests/sharing_protocols/iscsi test_260_iscsi.py

NAS-142672 / 27.0.0-BETA.1 / Remove ancient iSCSI tests (#19550)

The same functionality has been replicated using libiscsi.
DeltaFile
+0-382tests/sharing_protocols/iscsi/test_260_iscsi.py
+0-3821 files

LLVM/project fd62b48llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

Refactor to enable scalars inline instead of seperate helper function
DeltaFile
+23-38llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+50-0llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+73-382 files

LLVM/project f1e4e4cllvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

Testing updates per PR feedback, add some new test cases
DeltaFile
+87-6llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+87-61 files

LLVM/project 4f2cc7ellvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

[AMDGPU] PromoteAlloca: split scalar accesses that span several elements

promoteAllocaToVector already splits a *vector* access across several
elements when it is a multiple of the element size, but a *scalar* access
had to be bitcastable to the element type, so an i64 load from an alloca
promoted to <8 x i32> was rejected as "not a supported access type" and
the object stayed in scratch.

Accept a scalar access that is a whole multiple of the element size and
route it through the existing subvector path, which already builds the
value from consecutive elements and bitcasts. Accesses with padding are
still rejected, since splitting those would put the pieces at the wrong
offsets, as are non-integer non-float types.
DeltaFile
+78-0llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+28-4llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+106-42 files

LLVM/project ac2d1cfllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-select.ll promote-alloca-homogeneous-struct.ll

[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors

getVectorTypeForAlloca() peeled nested ArrayType and one inner
FixedVectorType, but stopped at any StructType. An alloca of an array of
structs was therefore rejected with "Cannot convert type to vector" and
fell back to scratch, even when the struct was a trivial wrapper around a
scalar.

Peel structs too, but only when every field has the same type and the
struct has no padding, so flattened elements keep the byte offsets the
surrounding index arithmetic assumes. Structs with differing field types
or with padding are left alone.
DeltaFile
+59-0llvm/test/CodeGen/AMDGPU/promote-alloca-homogeneous-struct.ll
+35-6llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+6-1llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
+100-73 files

LLVM/project 11e4850llvm/test/CodeGen/AMDGPU promote-alloca-homogeneous-struct.ll

Update script version and triple format per PR feedback
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/promote-alloca-homogeneous-struct.ll
+2-21 files

LLVM/project 79a6d76llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-select.ll promote-alloca-homogeneous-struct.ll

Simplify logic via suggestions from PR feedback. Add additional test cases, make tests a bit more complex so they don't fold into simple store of constant
DeltaFile
+101-8llvm/test/CodeGen/AMDGPU/promote-alloca-homogeneous-struct.ll
+4-16llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+4-4llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
+109-283 files

LLVM/project a8612a9libc/include/llvm-libc-types struct_sigevent.h

[libc] Add self-define for sigev_notify_thread_id field. (#219067)

Support downstream code that assumes `sigev_notify_thread_id`, even
though defined for Linux is a macro that expands to use private `struct
sigevent` fields.
DeltaFile
+3-0libc/include/llvm-libc-types/struct_sigevent.h
+3-01 files

LLVM/project 71d2dc2flang/include/flang/Semantics openmp-modifiers.h, flang/lib/Semantics check-omp-variant.cpp check-omp-structure.h

[flang][OpenMP] Remove OmpVerifyModifiers

Verification of clause modifiers is now done in a single place.
The OmpVerifyModifiers function was left in place, but was reduced
to always return "true".

Remove the definition and all calls to it.

The large amount of apparent changes is mostly due to unindenting
and reformatting previously indented code.
DeltaFile
+175-265flang/lib/Semantics/check-omp-structure.cpp
+44-49flang/lib/Semantics/check-omp-loop.cpp
+0-6flang/include/flang/Semantics/openmp-modifiers.h
+0-2flang/lib/Semantics/check-omp-variant.cpp
+0-2flang/lib/Semantics/check-omp-structure.h
+219-3245 files

LLVM/project fafffb0flang/test/Semantics/OpenMP declare-variant-v61.f90

Add testcase for missing required modifier group
DeltaFile
+30-0flang/test/Semantics/OpenMP/declare-variant-v61.f90
+30-01 files

FreeNAS/freenas ced6f73src/middlewared/middlewared/api/v27_0_0 iscsi_global.py

Allow iSCSI mode=2
DeltaFile
+1-1src/middlewared/middlewared/api/v27_0_0/iscsi_global.py
+1-11 files

FreeNAS/freenas bc5aacfsrc/middlewared/middlewared/plugins/iscsi_ extents.py target_to_extent.py

Skip SCST HA-internal target bookkeeping when LIO is in use
DeltaFile
+87-71src/middlewared/middlewared/plugins/iscsi_/fs_attachment_delegate.py
+89-58src/middlewared/middlewared/plugins/iscsi_/target_to_extent.py
+59-47src/middlewared/middlewared/plugins/iscsi_/extents.py
+235-1763 files

FreeNAS/freenas 66b7931src/middlewared/middlewared/plugins/failover_ event.py, src/middlewared/middlewared/plugins/iscsi_ iscsi_global.py alua.py

Add middleware support for LIO ALUA HA

Wire up the middleware side of LIO ALUA high-availability: load
lio_ha.ko with per-node addresses on service start, manage ALUA
state across failover events, clean up STANDBY configfs on pool
export, and add pre-flight validation that targets have static
initiator ACLs before ALUA can be enabled.

For each target, create a portal-less phantom TPG carrying the peer
node's controller group so that a single RTPG response from any
connected port lists both ALUA groups.  Write tpgt_N/rtpi explicitly
before enable so that relative target port IDs in RTPG match the
tag formula (portal.tag on Node A, portal.tag + 32000 on Node B)
rather than being auto-assigned sequentially by the kernel.

ALUA group states are driven by role and ha_state:

  MASTER  + synced        local=OPTIMIZED     remote=NONOPTIMIZED
  MASTER  + connected     local=OPTIMIZED     remote=TRANSITIONING

    [4 lines not shown]
DeltaFile
+510-128src/middlewared/middlewared/utils/lio/config.py
+214-2src/middlewared/middlewared/plugins/iscsi_/lio.py
+62-9src/middlewared/middlewared/plugins/iscsi_/alua.py
+37-21src/middlewared/middlewared/plugins/iscsi_/iscsi_global.py
+33-21src/middlewared/middlewared/plugins/failover_/event.py
+38-0src/middlewared/middlewared/utils/iscsi/constants.py
+894-1815 files not shown
+966-18811 files

NetBSD/src nCaCaMcsys/ufs/lfs lfs.h lfs_extern.h

   Remove the last vestiges of the freelist ordering code.  Addresses an issue
   observed in testing, also reported in PR kern/60523.
VersionDeltaFile
1.155+25-215sys/ufs/lfs/lfs_alloc.c
1.400+5-11sys/ufs/lfs/lfs_vfsops.c
1.132+2-3sys/ufs/lfs/lfs_extern.h
1.220+1-2sys/ufs/lfs/lfs.h
+33-2314 files

FreeBSD/poudriere 2e891d4src/poudriered poudriered.c

poudriered: retain queue while listing it

The list operation passes the global queue to send_object(), which
consumes its argument. A subsequent list request can then release the
stale queue again and terminate the daemon.

Take a temporary queue reference for the response so the global queue
remains valid.

(cherry picked from commit dbabedc99030f7d13696a8dd4382c4756c31fb9d)
DeltaFile
+1-1src/poudriered/poudriered.c
+1-11 files

FreeBSD/poudriere 8a640dbsrc/poudriered poudriered.c

Merge pull request #1369 from acts-1631/fix/poudriered-list-queue

poudriered: retain queue while listing it
DeltaFile
+1-1src/poudriered/poudriered.c
+1-11 files

LLVM/project 03fdf3elibc/src/time tzset.h tz_variables.h, libc/src/time/linux CMakeLists.txt tzset.cpp

[libc] Add stubs for tzset, tzname, timezone, and daylight. (#218979)

The variables are placed together in one entrypoint, as they will be
modified together by `tzset()` (and also `ctime()`, `localtime()`, and
`mktime()`).

For `tzname`, this PR updates hdrgen to handle array types for objects.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+28-0libc/src/time/tz_variables.h
+27-0libc/src/time/linux/tz_variables.cpp
+25-0libc/src/time/tzset.h
+25-0libc/test/src/time/tzset_test.cpp
+22-0libc/src/time/linux/tzset.cpp
+20-0libc/src/time/linux/CMakeLists.txt
+147-08 files not shown
+195-414 files

OPNSense/core 820f3bcsrc/etc/inc filter.inc, src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api MigrationController.php

Firewall: Rules: separate modern and legacy normalization pipelines

Emit match-based normalization after translation and before all filter rules so quick rules cannot bypass it. Keep the complete legacy scrub pipeline active while legacy rules exist, since legacy no-scrub cannot undo modern match actions and disables set reassemble semantics.

Stage imported match rules until legacy cleanup is complete, flag selective fragment reassembly for manual review, and clarify the remaining global normalization behavior in advanced settings.
DeltaFile
+66-21src/etc/inc/filter.inc
+32-2src/opnsense/mvc/app/library/OPNsense/Firewall/Plugin.php
+16-1src/opnsense/mvc/app/views/OPNsense/Firewall/firewall_migration.volt
+3-2src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/MigrationController.php
+5-0src/opnsense/scripts/filter/list_legacy_scrub.php
+2-2src/opnsense/mvc/app/models/OPNsense/Firewall/FieldTypes/FilterRuleField.php
+124-281 files not shown
+126-307 files

LLVM/project e475a0emlir/include/mlir/Dialect/Tosa/IR TosaComplianceData.h.inc, mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Add MXFP TRANSPOSE validation data (#218711)

These data type combinations were added in
https://github.com/arm/tosa-specification/pull/74

---------

Signed-off-by: Ian Tayler Lessa <ian.taylerlessa at arm.com>
DeltaFile
+25-1mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+8-0mlir/test/Dialect/Tosa/verifier.mlir
+8-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+8-0mlir/test/Dialect/Tosa/tosa-validation-version-1p0-valid.mlir
+8-0mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
+6-0mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+63-16 files

LLVM/project 545dcb6flang/lib/Optimizer/CodeGen CodeGen.cpp, mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp

[mlir] Migrate aggregate builders to explicit properties

Pass typed property structs and discardable attributes separately at ODS
aggregate builder call sites.

Assisted-by: Codex
DeltaFile
+45-70mlir/unittests/Dialect/OpenACC/OpenACCUtilsTest.cpp
+82-26flang/lib/Optimizer/CodeGen/CodeGen.cpp
+71-35mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
+71-23mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+50-33mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+33-42mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+352-22964 files not shown
+914-43370 files