LLVM/project 9040212clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 ms-x86-intrinsics.c

[CIR][X86]Implement handling for shiftleft/shiftright builtins in CIR (#176653)

Related to: #167765

---------

Co-authored-by: Roberto Turrado Camblor <rturrado at gmail.com>
DeltaFile
+49-0clang/test/CIR/CodeGenBuiltins/X86/ms-x86-intrinsics.c
+17-4clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+66-42 files

LLVM/project 80bce53llvm/include/llvm/IR DebugInfoMetadata.h

[llvm][DebugInfo] Alias DITypeRefArray to DITypeArray (#176938)

These two types serve the same purpose (providing an array-like view
over an `MDTuple`) and are pretty much implemented in the same way
(`DITypeArray` is itself an alias for `MDTupleTypedArrayWrapper`, the
generic array-like wrapper over typed metadata). IIUC `DITypeRefArray`
is a remnant of the old debug-info metadata hierarchy.

This patch aliases `DITypeRefArray` to `DITypeArray`.

In a follow-up patch I'm planning to turn all the `DITypeRefArray`
references into `DITypeArray` and remove the alias entirely. Splitting
this into two makes it easier to review imo
DeltaFile
+1-54llvm/include/llvm/IR/DebugInfoMetadata.h
+1-541 files

FreeNAS/freenas 93c4191src/middlewared/middlewared/plugins config.py pwenc.py

Shift the pwenc setup to setup of config plugin

We want all pwenc operations consolidated into one method to
avoid potentially bad interactions.
DeltaFile
+11-2src/middlewared/middlewared/plugins/config.py
+0-6src/middlewared/middlewared/plugins/pwenc.py
+11-82 files

LLVM/project e59ed9allvm/lib/Target/AMDGPU AMDGPU.td, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[AMDGPU] Introduce `AMDGPUSubtargetFeature` multiclass to reduce boilerplate (#176981)

Many `SubtargetFeature` definitions in `AMDGPU.td` follow a repetitive
pattern where a `FeatureXYZ` is paired with a `HasXYZ` predicate. This
creates significant code duplication.

This PR introduces `AMDGPUSubtargetFeature` multiclass that generates
both the `SubtargetFeature` and its corresponding `Predicate` from a
single definition. The multiclass accepts an optional `GenPredicate`
parameter (default 1) to skip predicate generation when not needed.

Not converted:

- Features with dependencies - multiclass doesn't support this yet. Will
do it in a follow-up.
- Features with irregular predicates (e.g., Predicate without
`AssemblerPredicate`, negated `Predicate`, complex multi-feature
conditions). For those without `AssemblerPredicate`, this can be done by
adding an extra optional argument to indicate whether

    [3 lines not shown]
DeltaFile
+292-821llvm/lib/Target/AMDGPU/AMDGPU.td
+1-1llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+293-8222 files

LLVM/project bbf1c01llvm/test/CodeGen/RISCV clmul.ll, llvm/test/CodeGen/X86 clmul-vector.ll clmul.ll

Merge branch 'main' into users/kparzysz/c01-omp-constexpr
DeltaFile
+12,546-0llvm/test/CodeGen/RISCV/clmul.ll
+6,171-5,115llvm/test/CodeGen/X86/clmul-vector.ll
+4,065-1,302llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
+3,137-2,053mlir/utils/vscode/package-lock.json
+2,373-2,733llvm/test/CodeGen/X86/clmul.ll
+0-4,569llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
+28,292-15,7721,943 files not shown
+122,016-61,3191,949 files

LLVM/project ef1f142llvm/utils/TableGen/Basic DirectiveEmitter.cpp

Extract more << operator calls into separate lines
DeltaFile
+8-4llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
+8-41 files

LLVM/project 3aea01blldb/source/Plugins/SymbolFile/DWARF DWARFASTParserClang.cpp, lldb/source/Plugins/TypeSystem/Clang TypeSystemClang.cpp

[lldb][DWARFASTParserClang] RequireCompleteType for ObjC types (#176765)

Currently we forcefully complete C++ types if we can't find their
definition for layout purposes. This ensures that we at least don't
crash in Clang when laying out the type. The definition is required for
types of members/array elements/base classes for the purposes of
calculating their layout. This is also true for Obj-C types, but we
haven't been forcefully completing those.

The test-case that's being un-XFAILed in this patch demonstrates a case
where not completing the super-class forcefully causes a clang crash.

rdar://168440264
DeltaFile
+7-12lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
+2-1lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
+0-1lldb/test/Shell/Expr/TestObjCIncompleteSuperclass.test
+9-143 files

LLVM/project cd7a062llvm/test/CodeGen/RISCV clmul.ll, llvm/test/CodeGen/X86 clmul-vector.ll

feedback

Created using spr 1.3.7
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+12,546-0llvm/test/CodeGen/RISCV/clmul.ll
+6,171-5,115llvm/test/CodeGen/X86/clmul-vector.ll
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+45,055-31,4504,090 files not shown
+347,797-219,0644,096 files

LLVM/project b62402ellvm/test/CodeGen/RISCV clmul.ll, llvm/test/CodeGen/X86 clmul-vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+12,546-0llvm/test/CodeGen/RISCV/clmul.ll
+6,171-5,115llvm/test/CodeGen/X86/clmul-vector.ll
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+45,055-31,4504,090 files not shown
+347,797-219,0644,096 files

LLVM/project 0ccdeccllvm/test/CodeGen/RISCV clmul.ll, llvm/test/CodeGen/X86 clmul-vector.ll

feedback

Created using spr 1.3.7
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+12,546-0llvm/test/CodeGen/RISCV/clmul.ll
+6,171-5,115llvm/test/CodeGen/X86/clmul-vector.ll
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+45,055-31,4504,090 files not shown
+347,797-219,0644,096 files

FreeBSD/ports ed0a5cfdevel/oci-cli distinfo Makefile

devel/oci-cli: Update 3.71.4 => 3.72.1

Changelogs:
https://github.com/oracle/oci-cli/releases/tag/v3.72.0
https://github.com/oracle/oci-cli/releases/tag/v3.72.1

PR:     292594
DeltaFile
+3-3devel/oci-cli/distinfo
+2-2devel/oci-cli/Makefile
+5-52 files

FreeBSD/ports 5a1837ddevel/py-oci distinfo Makefile

devel/py-oci: Update 2.164.2 => 2.165.1

Changelogs:
https://github.com/oracle/oci-python-sdk/releases/tag/v2.165.0
https://github.com/oracle/oci-python-sdk/releases/tag/v2.165.1

PR:     292594
DeltaFile
+3-3devel/py-oci/distinfo
+1-1devel/py-oci/Makefile
+4-42 files

LLVM/project bd70cf2flang/docs Directives.md, flang/include/flang/Optimizer/Builder HLFIRTools.h

[flang] Avoid descriptor conversion for descriptor args with ignore_tkr(c) (#176240)

For descriptor arguments marked with `!dir$ ignore_tkr(c)` we want to
leave them unmodified: don't create another descriptor or change the
existing descriptor.
DeltaFile
+79-0flang/lib/Lower/ConvertCall.cpp
+55-0flang/test/Lower/HLFIR/ignore-tkr-c-descriptor.f90
+5-2flang/docs/Directives.md
+1-0flang/include/flang/Optimizer/Builder/HLFIRTools.h
+140-24 files

FreeBSD/ports 3045e29devel/air-go distinfo Makefile

devel/air-go: Update to 1.64.2
DeltaFile
+5-5devel/air-go/distinfo
+1-1devel/air-go/Makefile
+6-62 files

LLVM/project f11a2abllvm/lib/MCA/Stages InOrderIssueStage.cpp, llvm/test/tools/llvm-mca/AArch64 cortex-a55-carry-over.s

[MCA] Retire all non-carried-over instructions in InOrderIssueStage (#176686)

Otherwise we might be left with instructions that never retire which can
create some weird results. This showed up originally on the MCA
timeline.

Fixes #176103.
DeltaFile
+82-0llvm/test/tools/llvm-mca/AArch64/cortex-a55-carry-over.s
+2-2llvm/lib/MCA/Stages/InOrderIssueStage.cpp
+84-22 files

FreeNAS/freenas 811ea84src/middlewared/middlewared/plugins pwenc.py config.py

Shift the pwenc setup to setup of config plugin

We want all pwenc operations consolidated into one method to
avoid potentially bad interactions.
DeltaFile
+0-6src/middlewared/middlewared/plugins/pwenc.py
+4-0src/middlewared/middlewared/plugins/config.py
+4-62 files

LLVM/project 8f21ec7llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-shuffle-combining-avx2.ll

[X86] combineX86ShuffleChainWithExtract - check inputs after resolveTargetShuffleInputsAndMask (#176980)

Make sure resolveTargetShuffleInputsAndMask hasn't removed the need for widening

Fixes #176951
DeltaFile
+131-0llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
+4-1llvm/lib/Target/X86/X86ISelLowering.cpp
+135-12 files

Linux/linux c03e9c4include/linux mmzone.h, kernel/dma pool.c

Merge tag 'dma-mapping-6.19-2026-01-20' of git://git.kernel.org/pub/scm/linux/kernel/git/mszyprowski/linux

Pull dma-mapping fixes from Marek Szyprowski:

 - minor fixes for the corner cases of the SWIOTLB pool management
   (Robin Murphy)

* tag 'dma-mapping-6.19-2026-01-20' of git://git.kernel.org/pub/scm/linux/kernel/git/mszyprowski/linux:
  dma/pool: Avoid allocating redundant pools
  mm_zone: Generalise has_managed_dma()
  dma/pool: Improve pool lookup
DeltaFile
+18-9kernel/dma/pool.c
+5-4include/linux/mmzone.h
+2-6mm/page_alloc.c
+25-193 files

FreeNAS/freenas db39135src/middlewared/middlewared/plugins/docker update.py

NAS-139392 / 25.10.2 / Properly make sure we return docker config in docker update (by sonicaj) (#18069)

DeltaFile
+1-1src/middlewared/middlewared/plugins/docker/update.py
+1-11 files

LLVM/project 4e43748flang/lib/Optimizer/OpenACC/Analysis CMakeLists.txt

[flang][OpenACC] Fix link failure with BUILD_SHARED_LIBS=ON (#176982)

```
/usr/bin/ld: tools/flang/lib/Optimizer/OpenACC/Analysis/CMakeFiles/FIROp enACCAnalysis.dir/FIROpenACCSupportAnalysis.cpp.o: in function `fir::acc ::FIROpenACCSupportAnalysis::isValidValueUse(mlir::Value, mlir::Region&) ':
FIROpenACCSupportAnalysis.cpp:(.text._ZN3fir3acc25FIROpenACCSupportAnaly sis15isValidValueUseEN4mlir5ValueERNS2_6RegionE+0xb): undefined referenc e to `mlir::acc::isValidValueUse(mlir::Value, mlir::Region&)' clang++: error: linker command failed with exit code 1 (use -v to see in vocation)
```
DeltaFile
+2-0flang/lib/Optimizer/OpenACC/Analysis/CMakeLists.txt
+2-01 files

FreeBSD/src 466bad4share/man/man5 src.conf.5, tools/build/options WITHOUT_SOUND

src.conf.5: Add WITHOUT_SOUND description

Fixes: f74f891581bc ("src.opts: Introduce MK_SOUND")
Sponsored by:   The FreeBSD Foundation
DeltaFile
+6-1share/man/man5/src.conf.5
+4-0tools/build/options/WITHOUT_SOUND
+10-12 files

FreeNAS/freenas 93b9079src/middlewared/middlewared/plugins/docker update.py

NAS-139392 / 26.04 / Properly make sure we return docker config in docker update (#18067)

DeltaFile
+1-1src/middlewared/middlewared/plugins/docker/update.py
+1-11 files

FreeNAS/freenas 784ff9esrc/middlewared/middlewared/migration 0017_tnc_ha_defaults.py

NAS-139296 / 25.10.2 / Update TNC defaults for HA systems (by sonicaj) (#18066)

DeltaFile
+9-0src/middlewared/middlewared/migration/0017_tnc_ha_defaults.py
+9-01 files

LLVM/project 60232f9llvm/lib/Target/AMDGPU AMDGPU.td, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[AMDGPU] Introduce `AMDGPUSubtargetFeature` multiclass to reduce boilerplate

Many `SubtargetFeature` definitions in `AMDGPU.td` follow a repetitive pattern where a `FeatureXYZ` is paired with a `HasXYZ` predicate. This creates significant code duplication.

This PR introduces `AMDGPUSubtargetFeature` multiclass that generates both the `SubtargetFeature` and its corresponding `Predicate` from a single definition. The multiclass accepts an optional `GenPredicate` parameter (default 1) to skip predicate generation when not needed.

Not converted:

- Features with dependencies - multiclass doesn't support this yet. Will do it in a follow-up.
- Features with irregular predicates (e.g., `Predicate` without `AssemblerPredicate`, negated `Predicate`, complex multi-feature conditions).
- Features where field name doesn't match the `HasXYZ` pattern.

148 features converted, saving ~529 lines of code.
DeltaFile
+292-821llvm/lib/Target/AMDGPU/AMDGPU.td
+1-1llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+293-8222 files

LLVM/project 6fdccdbclang/lib/Sema SemaHLSL.cpp, clang/test/SemaHLSL/Language EmptyInitializers.hlsl

[Sema][HLSL] Reject empty initializer lists for LHS containing an incomplete array. (#176075)

This PR rejects empty initializer lists when the LHS is or contains an
incomplete array type.
Without this early validation, an assumption would be made that there
was an argument in the initializer list.
This would cause an assertion failure.

Fixes https://github.com/llvm/llvm-project/issues/173076
DeltaFile
+96-0clang/test/SemaHLSL/Language/EmptyInitializers.hlsl
+47-0clang/lib/Sema/SemaHLSL.cpp
+143-02 files

LLVM/project 11b1836clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/test/CodeGenHLSL/builtins WaveActiveBallot.hlsl

[HLSL] Handle WaveActiveBallot struct return type appropriately (#175105)

The previous WaveActiveBallot implementation did not account for the
fact that the DXC implementation of the intrinsic returns a struct type
with 4 uints, rather than a vector of 4 uints. This must be respected,
otherwise the validator will reject the uses of WaveActiveBallot that
return a vector of 4 uints.
This PR updates the return type and adds the DXC-specific return type
`fouri32` to use for the intrinsic.
DeltaFile
+37-10llvm/test/CodeGen/DirectX/WaveActiveBallot.ll
+37-3clang/lib/CodeGen/CGHLSLBuiltins.cpp
+31-0llvm/test/tools/dxil-dis/waveactiveballot.ll
+10-10llvm/lib/Target/DirectX/DXIL.td
+14-3llvm/lib/Target/DirectX/DXILOpBuilder.cpp
+13-3clang/test/CodeGenHLSL/builtins/WaveActiveBallot.hlsl
+142-297 files not shown
+150-3813 files

FreeNAS/freenas 323dc74src/middlewared/middlewared/utils functools_.py cpu.py, src/middlewared/middlewared/utils/metrics arcstat.py

Type hints in utils
DeltaFile
+17-17src/middlewared/middlewared/utils/metrics/arcstat.py
+24-10src/middlewared/middlewared/utils/functools_.py
+18-15src/middlewared/middlewared/utils/cpu.py
+20-11src/middlewared/middlewared/utils/origin.py
+11-19src/middlewared/middlewared/utils/__init__.py
+14-10src/middlewared/middlewared/utils/threading.py
+104-8245 files not shown
+272-19251 files

pfSense/pfsense 0273368src/usr/local/pkg miniupnpd.xml

Add config description for changes to UPnP IGD & PCP
DeltaFile
+1-0src/usr/local/pkg/miniupnpd.xml
+1-01 files

NetBSD/src XVTCTgCexternal/gpl3/gcc/lib/libquadmath Makefile

   fix the build.
VersionDeltaFile
1.2+5-1external/gpl3/gcc/lib/libquadmath/Makefile
+5-11 files

FreeNAS/freenas e1e367dsrc/middlewared/middlewared/utils functools_.py cpu.py, src/middlewared/middlewared/utils/metrics arcstat.py

Type hints in utils
DeltaFile
+24-10src/middlewared/middlewared/utils/functools_.py
+17-17src/middlewared/middlewared/utils/metrics/arcstat.py
+18-15src/middlewared/middlewared/utils/cpu.py
+20-11src/middlewared/middlewared/utils/origin.py
+11-19src/middlewared/middlewared/utils/__init__.py
+14-10src/middlewared/middlewared/utils/threading.py
+104-8245 files not shown
+272-19251 files