[clang] [serialization] Step into UsingShadowDecl when find existing decl (#208393)
Close https://github.com/llvm/llvm-project/issues/207581
The root cause of the problem is that：enum constant decl, for which its
parent is not enum class, is special. They can be accessed directly
without access its parent. When modules join the game, it becomes more
complex. As for members in other entities like class, we can assume the
member is accessable if their parent are accesable. But it is a
different story for enums. See
https://github.com/llvm/llvm-project/issues/131058 for the whole story
of the backrgound.
Then we didn't write enum constant decl to the lookup table of its
parent of parent in the ASTWriter. So that if other consumer in Sema
wants to access them, they have to get it by entities like exported
using decls. However, the problem is, in ASTReader, when we merge decls,
we use noload_lookup to find existing decls. And the absense of unnamed
enum decl in the parent of its parent's lookup table makes the merge
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[dsymutil] Use DWARFDie::getLanguage instead of manually finding DW_AT_language (#208174)
With DWARFv6, CUs may not have a `DW_AT_language` (but a
`DW_AT_language_name` instead). In
https://github.com/llvm/llvm-project/pull/207151 we made
`DWARFDie::getLanguage` account for this possibility. However, dsymutil
explicitly tries to find `DW_AT_language` in several places.
This patch ensures we go through `DWARFDie::getLanguage` instead in most
of them.
The only way I found this to be testable/observable is by testing the
`isODRLanguage` code paths. Added a test that exercises this.
There is one remaining use of `DW_AT_language` in
`DependencyTracker.cpp`. But was going to address that in a separate
change.
AI usage:
- Test written with the help of Claude
[ObjectYAML] Fix issues found in review of #207306 (#208160)
- checkLimit(): avoid uint64_t overflow.
- writeAsBinary(): check the limit against the bytes actually written.
- updateDataAt(): take const void *Data.
Revert "[IR][NFC] Drop vtable from PassConcept/PassModel" (#208389)
Breaks ASan builds due to new-delete mismatch.
Closes #208381.
Reverts llvm/llvm-project#208168
firmware: cleansing using output_cmd is futile
Move the code back to where it was in early 26.1. A number of
regressions could have been avoided. The last straw was buffering
of "." characters for fetching.
The read-guard is still effective. As it reads the file it does
not need to run unbuffered. GUI reads are still properly filtered.
(cherry picked from commit 1eaefb6bc81052c5454d20333cbc32d1c1392ee1)
[AArch64][FastISel] Update arm64-fast-isel-int-ext.ll check lines (NFC) (#207996)
Similar to #207159 (merged as 15b3882), update the CHECK lines
automatically in prep for new tests and bug fixes.
Require GraphHasNodeNumbers in llvm::LoopInfoBase; drop the DenseMap fallback (#207905)
LoopInfoBase kept a DenseMap fallback for block types whose GraphTraits
has no getNumber() (std::conditional_t on GraphHasNodeNumbers). With the
last such in-tree users now numbered (mlir::Block #207617 and BOLT's
BinaryBasicBlock #207899), require GraphHasNodeNumbers via static_assert
and make BBMap unconditionally a SmallVector indexed by block number,
dropping the DenseMap branch in
getLoopFor/changeLoopFor/removeBlock/analyze/verify.
Aided by Claude Opus 4.8
[Clang][AMDGPU] Add amdgcn_av("none") attribute for atomic expressions
Add a statement attribute that suppresses MakeAvailable/MakeVisible
cache operations on AMDGPU atomic instructions while preserving memory
ordering (waits).
The attribute takes a string argument specifying the mode. Currently
"none" is the only supported mode. The resulting atomic or fence
instruction carries !mmra !{!"amdgcn-av", !"none"} metadata.
Support includes C/C++ atomic builtins, _Atomic type qualifier
operations, fence builtins, and AMDGPU-specific atomic builtins
marked with TargetAtomicMixin.
Uses Builtin::Context::isTargetAtomicBuiltin() to identify
target-specific atomic builtins in target-neutral Sema code.
Assisted-By: Claude Opus 4.6
[orc-rt] Move the regression tests into test/regression (#208391)
Move the regression lit config and the existing tests into
test/regression/, and point the check-orc-rt suite there.
This is a first step towards consolidating tests and test infrastructure
under orc-rt/test. Upcoming commits will add a test tools directory, and
move the existing unit tests (under orc-rt/unittests) into
orc-rt/test/unit.
[AArch64] Expand FORM_TRANSPOSED_REG_TUPLE to copies before regalloc (#207205)
Previously, we kept the FORM_TRANSPOSED_REG_TUPLE nodes around during
register allocation. The problem with this approach is that it does not
model the potential overlap in live ranges between the destination and
source operands.
As a result, the register allocator assumes it has complete freedom to
allocate registers to the operands. For example, there is nothing
stopping it from allocating:
```
{z0, z1, z2, z3} = FORM_TRANSPOSED_X4 z3, z2, z1, z0
```
However, such cases are hard to expand later, either requiring spills or
complex shuffles. The current expansions of FORM_TRANSPOSED_REG_TUPLE
miscompile in cases like this because, when naively expanded into copies
after register allocation, earlier copies can clobber values that are
still needed by later ones.
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[FIRToMemRef] Fix wrong indexing for converted array_coor over sliced fir.embox (#207749)
FIRToMemRef::convertArrayCoorOp routes through getMemrefIndices, which
only folds the first `rank` triples of sliceInfo.sliceVec into the
memref indices (i.e. the array_coor's own slice); the embox's slice
triples -- which sit at [rank*3 .. 2*rank*3-1] when both are present --
were dropped. Three consequences, three fixes here:
1. Non-collapsed embox slice lbs contribute (lb - 1) per Fortran dim to
each memref index. Fold them in in memref order (reversed Fortran order)
so the reinterpret_cast view lands at the right column.
2. The shapeVec-else stride path used shapeVec[0..rank-1] to build the
outer strides. With both slices present, that's the box's (slice's)
extents. Use shapeVec[rank..2*rank-1] instead -- the parent's extents --
so the outer stride is the parent's leading dim rather than the slice's
own size.
3. Rank-reducing embox slices (undef ub/step triples) have no memref
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[Clang] Identify target-specific atomic builtins
Add a tablegen class TargetAtomicMixin that targets can combine with their
builtin classes to mark atomic builtins. The emitter encodes this as an 'A'
character in the builtin attributes string, queryable at runtime via
Builtin::Context::isTargetAtomicBuiltin().
A mixin is a flexible way to add the "atomic" property to specific builtins
in the target without modifying the class hierarchy. We do not derive a
TargetAtomicBuiltin class from the combination of TargetBuiltin and
AtomicBuiltin. The class AtomicBuiltin is used to collect Clang's own
target-independent builtins, and we don't want to inject target-specific
builtins into that collection. Also, such a class will produce a diamond
inheritance pattern with the Builtin class.
Also mark AMDGPU atomic builtins (fence, atomic inc/dec, ds_fadd/fmin/fmax,
ds_atomic_fadd, global_atomic, flat_atomic) with TargetAtomicMixin.
Assisted-By: Claude Opus 4.6
[bazel][libc] Add htons function family and tests (#208201)
Add bazel build targets for the arpa/inet byte order functions (htonl,
htons, ntohl, ntohs) and their corresponding unittests.
Assisted by Gemini.
[lldb] Make SBType::FindDirectNestedType work with dynamic types (#207743)
This makes it possible to find the nested type just by knowing the
dynamic type of the value. To get the previous behavior, get the type
from a static view of the value (SBValue::GetStaticValue).
