[VPlan] Fold shifts by zero. (#223276)
Add trivial folds of shifts by zero. This allows us to match IR SCEV
behavior (which looks through trivial shifts), w/o explicitly handling
those in getSCEVExprForVPValue.
[VPlan] Add tests for narrowing users of a widened induction (NFC). (#223277)
Add additional narrowing tests for wide IV including pointer inductions
and FP inductions.
sysutils/ngbuddy: Update 1.0 => 1.1
This update also corrects rc.d service order
reported by feld@ in PR 298188.
While here, update maintainer address.
Commit log:
https://github.com/bellhyve/ngbuddy/compare/v1.0...v1.1
PR: 298371
Approved by: osa, vvd (Mentors, implicit)
MFH: 2026Q3
[AArch64] Make ImmInsnModel operands optional. NFC (#223280)
This helps make sure we do not use them incorrectly, and should allow
them to
be checked for values in the future.
[SSAF][SourceEdit] Wire in 'clang-ssaf-src-edit-merge' and add multi-TU tests (#220372)
With 'clang-ssaf-src-edit-merge', we can test source edits over multiple
translation units: their Replacements are merged before apply. This
covers both clean merges and conflicts.
[SSAF][SourceTransformation] Add transformation for new[] and malloc
For a PointerFlowPair, if RHS is an array-new or malloc call and LHS
has bounded type, transform RHS to the bounded-producing alternative
to new[]/malloc.
4th step of
rdar://187125348
[AMDGPU] Fix s_buffer_load crash for illegal result types (#215483)
i1, i4, v2i1, v3i16, v6i8, and i128 had no SBUFFER_LOAD selection
pattern and crashed
Load a legal i32/vNi32 carrier instead and narrow/bitcast down to the
requested type
[Clang][MinGW] Link default-manifest.o if exists (#223084)
Some MinGW distributions provide a pre-compiled manifest xml to disable
the UAC escalation dialog.
Link automatically the manifest only if it exists when linking an
executable.
Do the same as Cygwin (#220875) and align with GCC.
[VPlan] Don't create no-op casts in truncateToMinimalBitwidths. (#223271)
No-op casts get folded to the input operand, which caused applyFlags to
crash if that was not a cast. Fix by avoiding creating such trivial
casts in the first place.
acpi_cpu: only report unmapped processor objects enabled in the MADT
Firmware expose a DSDT sized for the largest SKU of the platform,
so a verbose boot prints an "ignored" line for every vacant
processor slot. A vacant slot has no enabled MADT entry; a CPU that
failed to come online does.
Reviewed by: olce, adrian
Differential Revision: https://reviews.freebsd.org/D59551
[AMDGPU] Support TFE D16 format buffer loads on gfx8/10/11/12 (#211465)
gfx90a has no hardware encoding for TFE D16 format buffer loads, so
reject the combination there with a diagnostic. Other targets
(gfx8/10/11/12) do have real encodings, so add codegen support for them
instead of rejecting unconditionally.
intel/intelpmc: Add Intel PMC Core driver
Add driver for Intel Power Management Controller (PMC) found on Sunrise Point PCH chipsets.
This device exposes S0ix sleep state residency counters and power management status.
Sysctls provided:
dev.intelpmc.0.slp_s0_residency_us - Time in deepest sleep (us)
dev.intelpmc.0.ltr_ignore - LTR ignore mask
dev.intelpmc.0.pm_cfg - PM configuration register
dev.intelpmc.0.pm_sts - PM status register
dev.intelpmc.0.access_denied - Firmware lock status
Supported devices for now:
- Sunrise Point-LP (0x9D21)
- Sunrise Point-H (0xA121)
Note: Later PCH generations (Cannon Lake, Tiger Lake, ect.) have different PMC register layouts according to the datasheet and would need per-generation tables.
I avoided adding untested hardware in case they have a quirk.
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editors/libreoffice: fix some crashes and VCL selection (+)
* Fix crash with SAL_USE_VCLPLUGIN=gen and enabled Skia [1]
* Allow Qt VCL plugin when LO started outside the known DE (e.g., pure X) [2]
PR: 298257 [1], 298227, [2]
[GlobalISel] Add KnownBits support for G_INSERT_SUBVECTOR (#215048)
## Summary
Add KnownBits support for `G_INSERT_SUBVECTOR` in GlobalISel value
tracking.
The implementation splits the demanded elements between the original
vector and inserted subvector, ignores overwritten source elements, and
intersects the KnownBits information from the contributing operands.
Part of #150515.
## Testing
- `llvm-lit
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir`
- `llvm-lit llvm/test/CodeGen/AArch64/GlobalISel/knownbits-*.mir`
- 40/40 passed
[TableGen] Use BitVector for RegisterSet in AsmMatcherEmitter (NFC) (#222525)
This patch replaces std::set with BitVector for RegisterSet in
AsmMatcherEmitter.
Without this patch, RegisterSet is represented as
std::set<const Record *, LessRecordByID>. On targets with large
register files like AMDGPU (~3,000 registers), repeatedly computing set
intersections and subset checks using std::set nodes incurs
significant overhead.
This patch assigns each register record a dense bit index ordered by
LessRecordByID. This allows us to represent RegisterSet as a
BitVector, enabling fast bitwise operations for set intersections and
subset checks.
This reduces the wall-clock time of generating AMDGPUGenAsmMatcher.inc
from 39.53s to 31.32s (a 20.8% speedup) across 3 runs while producing
bit-for-bit identical output across all targets.
Assisted-by: Antigravity
