pfSense/pfsense 0c28827src/etc/inc pfsense-utils.inc

Fix VirtIO ALTQ toggle behavior. Fixes #16166
DeltaFile
+1-0src/etc/inc/pfsense-utils.inc
+1-01 files

FreeNAS/freenas a85559fsrc/middlewared/middlewared/alembic/versions/26.0 2026-02-23_15-15_webshare_groups.py

webshare migration
DeltaFile
+32-0src/middlewared/middlewared/alembic/versions/26.0/2026-02-23_15-15_webshare_groups.py
+32-01 files

LLVM/project ac9f359llvm/lib/Target/Hexagon HexagonTfrCleanup.cpp HexagonGenMux.cpp, llvm/test/CodeGen/Hexagon copy-phys-int-dbl.mir truncating-copy-double-to-int.ll

Revert "[Hexagon] Handle subreg copies between DoubleRegs and IntRegs… (#182861)

… (#181360)"

This reverts commit 689ecf880373bb4e0f01ed5e004f19a466e869dc.
DeltaFile
+8-48llvm/lib/Target/Hexagon/HexagonTfrCleanup.cpp
+7-35llvm/lib/Target/Hexagon/HexagonGenMux.cpp
+0-32llvm/test/CodeGen/Hexagon/copy-phys-int-dbl.mir
+0-27llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+0-22llvm/test/CodeGen/Hexagon/truncating-copy-double-to-int.ll
+0-20llvm/test/CodeGen/Hexagon/tfr-cleanup-subreg-copy.ll
+15-1841 files not shown
+18-1957 files

LLVM/project b3637cdclang/lib/Analysis/FlowSensitive DataflowEnvironment.cpp, clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp MockHeaders.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+41-0clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp
+20-0clang/unittests/Analysis/FlowSensitive/MockHeaders.cpp
+5-0clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
+66-03 files

LLVM/project 758b43eclang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp MockHeaders.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+43-0clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp
+20-0clang/unittests/Analysis/FlowSensitive/MockHeaders.cpp
+63-02 files

LLVM/project 6f46681lldb/docs conf.py, lldb/docs/use variable.rst

[lldb][docs] Improve documentation typehints (#182892)

Some parts of the docs uses google style docstrings, but the generated
docstrings are note formatted properly.
Add the builtin napoleon extension.
Add typehints to the `SyntheticChildrenProvider` in variable docs.
DeltaFile
+46-23lldb/docs/use/variable.rst
+6-1lldb/docs/conf.py
+52-242 files

FreeBSD/doc 5e3d1d7documentation/content/nl/books/faq _index.po _index.adoc

books: add Dutch translation of the FAQ, via weblate.
DeltaFile
+1,720-0documentation/content/nl/books/faq/_index.po
+447-0documentation/content/nl/books/faq/_index.adoc
+2,167-02 files

LLVM/project e07cf56lld/test/ELF/lto linker-script-symbols-ipo.ll, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+27-0llvm/test/CodeGen/X86/prefalign.ll
+14-2llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+2-2llvm/test/Transforms/SampleProfile/pseudo-probe-emit.ll
+1-1llvm/test/tools/gold/X86/multiple-sections.ll
+1-1lld/test/ELF/lto/linker-script-symbols-ipo.ll
+45-65 files

FreeBSD/src 49ab036share/man/man4 multicast.4

multicast.4: Fix disabling multicast forwarding

Reviewed by: markj, glebius
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D55266

(cherry picked from commit f2c2e5b0bf9def01b10651b9802fa38d07d9d265)
DeltaFile
+22-4share/man/man4/multicast.4
+22-41 files

LLVM/project a56993allvm/test/CodeGen/AMDGPU flat-scratch.ll target-cpu.ll, llvm/test/CodeGen/AMDGPU/GlobalISel flat-scratch.ll

[AMDGPU] Remove `FeaturePromoteAlloca` (#177636)

It looks like `+promote-alloca` is always enabled, and `-promote-alloca`
is simply used as a switch to toggle the pass.
DeltaFile
+14-14llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+1-16llvm/test/CodeGen/AMDGPU/target-cpu.ll
+7-7llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
+6-6llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
+5-5llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
+43-5823 files not shown
+91-11829 files

NetBSD/src utfn40tsys/arch/ews4800mips/conf GENERIC, sys/dev/marvell ehci_mv.c

   fix various typos in comments.
VersionDeltaFile
1.69+3-3sys/arch/ews4800mips/conf/GENERIC
1.11+3-3sys/dev/marvell/ehci_mv.c
1.103+3-3sys/dev/usb/umass_quirks.c
1.44+3-3sys/ufs/lfs/lfs_rfw.c
1.3+2-2tests/bin/sh/t_input.sh
+14-145 files

LLVM/project ed6cd32utils/bazel/llvm-project-overlay/clang BUILD.bazel

[bazel][Clang][AMDGPU][Docs] Port e6f30334de720b0473f1d797c008ccf74fb300b8 (#182925)

Co-authored-by: Pranav Kant <prka at google.com>
DeltaFile
+10-1utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+10-11 files

LLVM/project 8910926clang/lib/Sema SemaExprCXX.cpp, clang/test/CodeGenHLSL/BasicFeatures MatrixSplat.hlsl

[HLSL][Matrix] Add implicit type conversions for constant matrix types (#181939)

Fixes #175853

This PR extends implicit type conversion support to Clang's HLSL
frontend for handling ConstantMatrix types in addition to Vectors. The
logic is pretty much identical when handling a ConstantMatrix versus a
Vector so the changes are rather simple.

Assisted-by: claude-opus-4.6
DeltaFile
+37-17clang/lib/Sema/SemaExprCXX.cpp
+37-0clang/test/CodeGenHLSL/BasicFeatures/MatrixSplat.hlsl
+35-0clang/test/SemaHLSL/Language/MatrixSplatCasts.hlsl
+3-2clang/test/SemaHLSL/MatrixElementOverloadResolution.hlsl
+112-194 files

FreeBSD/ports 65f0c24deskutils/qlipper Makefile distinfo

deskutils/qlipper: Update to 6.0.0

- Use QT6 support by default

Differential Revision:  <https://reviews.freebsd.org/D55465>
DeltaFile
+12-7deskutils/qlipper/Makefile
+3-3deskutils/qlipper/distinfo
+3-0deskutils/qlipper/pkg-plist
+18-103 files

FreeBSD/ports 9cc8f34devel/nextpnr-devel distinfo Makefile

devel/nextpnr-devel: Update to 2026-02-21
DeltaFile
+3-3devel/nextpnr-devel/distinfo
+2-3devel/nextpnr-devel/Makefile
+5-62 files

LLVM/project 3f742e9clang/lib/Driver/ToolChains SPIRV.cpp Clang.cpp, clang/test/Driver spirv-lto.c

[Clang][Driver][SPIRV] Support LTO through the llvm-lto tool (#182347)

There is no SPIR-V linker that supports LTO and a proposal to support
basic SPIR-V linking in `lld` was
[rejected](https://github.com/llvm/llvm-project/pull/178749), so support
a basic version of LTO just by calling `llvm-lto` directly from the
SPIR-V Toolchain. `-Xlinker` can be used to specify flags to `llvm-lto`.

This should be enough for our use case.

There is also the `llvm-lto2` tool, but that requires a list of symbol
resolutions in the command line, and we can't compute that in the
driver.

---------

Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
DeltaFile
+35-0clang/test/Driver/spirv-lto.c
+21-7clang/lib/Driver/ToolChains/SPIRV.cpp
+4-2clang/lib/Driver/ToolChains/Clang.cpp
+60-93 files

FreeNAS/freenas 7b23263tests/api2 test_300_nfs.py test_200_ftp.py

test
DeltaFile
+0-2,224tests/api2/test_300_nfs.py
+0-1,411tests/api2/test_200_ftp.py
+0-936tests/api2/test_345_acl_nfs4.py
+0-700tests/api2/test_011_user.py
+0-565tests/api2/test_audit_websocket.py
+0-495tests/api2/test_440_snmp.py
+0-6,331243 files not shown
+0-31,085249 files

FreeBSD/ports 9fe32c3www/freenginx-devel distinfo Makefile.extmod, www/freenginx-devel/files extra-patch-passenger-disable-telemetry extra-patch-passenger-Configuration.c

www/freenginx-devel: third-party module management (+)

- update passenger to 6.1.2

Bump PORTREVISION.

Sponsored by:   tipi.work
DeltaFile
+3-3www/freenginx-devel/distinfo
+2-2www/freenginx-devel/files/extra-patch-passenger-disable-telemetry
+2-2www/freenginx-devel/files/extra-patch-passenger-Configuration.c
+2-2www/freenginx-devel/files/extra-patch-passenger-build-nginx.rb
+1-1www/freenginx-devel/Makefile.extmod
+1-0www/freenginx-devel/Makefile
+11-106 files

FreeBSD/src b0476eesecure/lib/libcrypto/man/man3 Makefile

OpenSSL: install EVP_CIPHER_CTX_get_app_data.3 once

A separate EVP_CIPHER_CTX_get_app_data.3 was added in the OpenSSL 3.5.5
import, but the link to EVP_EncryptInit.3 was still being installed
which stomped on the file and created inconsistent entries in the METALOG.

Reviewed by:    emaste
Found by:       package_check script in Cirrus-CI
Fixes:          1731fc70f734 ("OpenSSL: update vendor sources to match 3.5.5 content")
Sponsored by:   Innovate UK
Differential Revision:  https://reviews.freebsd.org/D55332

(cherry picked from commit c4130a8a84e1ce0fc9c05d2b48f83e66ade302aa)
DeltaFile
+0-1secure/lib/libcrypto/man/man3/Makefile
+0-11 files

LLVM/project 202800fllvm/test/CodeGen/AMDGPU flat-scratch.ll target-cpu.ll, llvm/test/CodeGen/AMDGPU/GlobalISel flat-scratch.ll

[AMDGPU] Remove `FeaturePromoteAlloca`
DeltaFile
+14-14llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+10-10llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+1-16llvm/test/CodeGen/AMDGPU/target-cpu.ll
+7-7llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
+6-6llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
+5-5llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
+43-5823 files not shown
+91-11829 files

LLVM/project 5a756c8llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp GCNHazardRecognizer.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp AMDGPUBaseInfo.h

[AMDGPU][SIInsertWaitcnts][NFC] Make Waitcnt members private (#180772)

This patch makes Waitcnt member variables private and replaces their
accesses with calls to set() or get(). This will help us change the
implementation to an a array in the followup patch.
DeltaFile
+115-99llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+19-16llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+2-1llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+1-1llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+137-1174 files

LLVM/project b3f3b57lldb/include/lldb/Symbol SymbolContext.h, lldb/source/Core Module.cpp

[lldb] Speed up SymbolContextList::AppendIfUnique (#181952)

d7fb086668dff68 changed some calls from SymbolContextList::Append to
SymbolContextList::AppendIfUnique. This has unfortunately caused a huge
slow down in operations involving a large amount of symbol contexts (for
example, trying to autocomplete from an empty input "b <TAB>" will add
every function to the list), since AppendIfUnique scans the entire
symbol context list. Speed this up by adding a hash set to quickly
answer whether a symbol context is on the list or not.

This takes the time from running "b <TAB>" when debugging yaml2obj on my
machine from 600 seconds down to 13, which is about the same as before
d7fb086668dff68.

Note that AppendIfUnique has a logic error, which has been present since
its introduction. This has to do with the behavior controlled by
"merge_symbol_into_function", which will try to merge symbols with
symbol context containing the equivalent function to that symbol.


    [23 lines not shown]
DeltaFile
+75-11lldb/include/lldb/Symbol/SymbolContext.h
+22-27lldb/source/Symbol/SymbolContext.cpp
+1-1lldb/source/Core/Module.cpp
+98-393 files

LLVM/project 5edbaf9lldb/source/API liblldb-private.exports

[lldb] Export *all* private symbols when using LLDB_EXPORT_ALL_SYMBOLS (#182634)

Export *all* private symbols, from both LLDB and LLVM. The motivation
for this is to be able to create dynamically linked LLDB plugins. These
plugins cannot link any LLDB or LLVM code statically as that results in
duplicated symbols, and instead have to use the ones from libLLDB.
DeltaFile
+4-0lldb/source/API/liblldb-private.exports
+4-01 files

LLVM/project 66e4eabllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

Revert "[AMDGPU][SIInsertWaitcnts][NFC] Move instr events code into separate …"

This reverts commit bad9e4a84972056a17fc6803cab3674405a6d3f6.
DeltaFile
+68-63llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+68-631 files

LLVM/project e1acef5llvm/test/CodeGen/AMDGPU packed-fp32.ll bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel mul.ll

[AMDGPU] Update gfx1251 sched model to latest table
DeltaFile
+101-100llvm/test/CodeGen/AMDGPU/packed-fp32.ll
+73-75llvm/test/CodeGen/AMDGPU/bf16.ll
+54-52llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+28-31llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
+20-19llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
+16-16llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+292-2934 files not shown
+330-33110 files

LLVM/project effb521clang-tools-extra/clang-doc MDGenerator.cpp Serialize.cpp, clang-tools-extra/clang-doc/assets enum-template.mustache

[clang-doc] Display enum type along with enum name in HTML view (#181347)

Displays enum type along with name.

For named variables
Previous output : enum XYZ
Current output : enum XYZ : unsigned int

For unnamed variables
Previous output : enum
Current output : enum : unsigned int

Fixes #166652
DeltaFile
+281-104clang-tools-extra/test/clang-doc/enum.cpp
+7-4clang-tools-extra/clang-doc/MDGenerator.cpp
+2-2clang-tools-extra/clang-doc/Serialize.cpp
+1-1clang-tools-extra/clang-doc/assets/enum-template.mustache
+291-1114 files

FreeBSD/ports 904bbdawww/cinny pkg-plist distinfo

www/cinny: Update to 4.10.5
DeltaFile
+9-9www/cinny/pkg-plist
+3-3www/cinny/distinfo
+1-1www/cinny/Makefile
+13-133 files

LLVM/project bad9e4allvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

[AMDGPU][SIInsertWaitcnts][NFC] Move instr events code into separate function (#180864)

This patch moves the code that finds which events correspond to an
instruction into a separate `getEventsFor(MachineInstr)` function.
DeltaFile
+63-68llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+63-681 files

LLVM/project aa3489fllvm/lib/Target/AMDGPU AMDGPULanePackedABI.cpp AMDGPULanePackedABI.h, llvm/test/CodeGen/AMDGPU inreg-vgpr-lane-packing.ll

[AMDGPU] Pack overflow inreg args into VGPR lanes

When inreg function arguments overflow the available SGPRs, pack multiple values
into lanes of a single VGPR using writelane/readlane instead of consuming one
VGPR per overflow argument.

The feature is behind a flag (default off) and currently only supports the
SelectionDAG path.

Known issue: if the register allocator does not coalesce the COPY between the
writelane chain and the physical call argument register, the resulting v_mov_b32
is EXEC-dependent and will not transfer inactive lanes. This is correct when
EXEC is all-ones (the common case at call sites) but would be incorrect inside
divergent control flow.
DeltaFile
+282-0llvm/test/CodeGen/AMDGPU/inreg-vgpr-lane-packing.ll
+152-0llvm/lib/Target/AMDGPU/AMDGPULanePackedABI.cpp
+54-0llvm/lib/Target/AMDGPU/AMDGPULanePackedABI.h
+51-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-0llvm/lib/Target/AMDGPU/CMakeLists.txt
+540-35 files

LLVM/project 03b70cbllvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine icmp-vector-bitwise-reductions.ll

[InstCombine] Restrict foldICmpOfVectorReduce to one-use (#182833)

Follow up on 279b3dbe ([InstCombine] Fold icmp (vreduce_(or|and) %x),
(0|-1), #182684) to fix a regression by restricting the fold to one-use.

Regression: https://godbolt.org/z/f38b169MM
DeltaFile
+30-0llvm/test/Transforms/InstCombine/icmp-vector-bitwise-reductions.ll
+4-2llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+34-22 files