[RISCV][P-ext] Support Packed Slide (#234629)
This patch supports packed slide intrinsics using funnel shifts.
On RV32, the 64-bit funnel shift expands into select instructions, so it
involves branches.
libfetch: avoid buffering HTTP requests with TCP_NOPUSH on macOS
Darwin does not flush queued output when TCP_NOPUSH is cleared or TCP_NODELAY is enabled. Small HTTP requests can remain buffered while the client waits for a response and the server waits for the complete request, causing repository updates to time out.
Disable TCP_NOPUSH in the HTTP implementation on Apple platforms. Verified with two requests over a reused connection and the concurrent download integration suite on macOS without build-only workarounds.
*/wordpress*: deprecate localized variants
Localized WordPress tarballs are regenerated in place by upstream
whenever translations are updated, so the distfile checksums keep
breaking without a version change. The language packs have the same
problem, and other distributions only ship the English core and let
WordPress download language packs on its own.
Mark the localized ports deprecated, expiring on 2026-12-31. Users
should switch to www/wordpress and choose the site language in
WordPress.
{french,german,russian}/wordpress: chase upstream distfile re-roll
Upstream re-rolled the 7.1.3 de_DE, fr_FR and ru_RU tarballs again
with refreshed translations under wp-content/languages. The
WordPress core files are unchanged.
Update distinfo and bump PORTREVISION as package contents changed.
[CodeGen] Print x86 memory operands with their operand count in tests
The MIR printer now writes an inline asm flag's operand count when it isn't
1, so the five operands of an x86 memory reference print as "mem:m ops:5".
Assisted-by: Claude Opus 5.5
[RegAllocFast] Print x86 memory operands with their operand count in tests
The MIR printer now writes an inline asm flag's operand count when it isn't
1, so the five operands of an x86 memory reference print as "mem:m ops:5".
Assisted-by: Claude Opus 5.5
Merge tag 'drm-next-2026-10-21' of https://gitlab.freedesktop.org/drm/kernel
Pull drm updates from Dave Airlie:
"Highlights:
- core: a lot of atomic refactoring in progress, panic got split into
a core/helpers model
- amdgpu: enables HDMI 2.1 FRL and other good things finally, UAlink
over Ethernet support
- xe: has a bunch of CRI support, ras error for bad vram, memory
offlining support.
- msm: enables a bunch more GPUs.
Otherwise it's a the usual mountain of stuff all over the place.
Details:
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[CodeGen] Address review: report a memory constraint on a label as such
A direct label operand with a memory constraint (e.g. "!m") isn't an
input, so it was reported as a direct memory output. Give it its own
error, and update the comment above the check, which still described only
memory inputs.
Assisted-by: Claude Opus 5.5
[SPARC] Treat %g0 as a constant in the delay slot pass (#234152)
This allows instructions such as clr, that reads %g0, to be moved past a
compare, that writes to %g0, and into a delay slot. %g0 is always 0, so
there is no dependency.
Assisted-by: Claude
[mlir] Fix signed ceiling division of INT_MIN
Negating INT_MIN causes signed overflow even when its quotient is
representable. For INT_MIN / 2, the Index expansion included:
%zero = llvm.mlir.constant(0 : i64) : i64
%n = llvm.mlir.constant(-9223372036854775808 : i64) : i64
%m = llvm.mlir.constant(2 : i64) : i64
%neg_n = llvm.sub %zero, %n : i64 // Overflow: -INT_MIN is unrepresentable.
%div = llvm.sdiv %neg_n, %m : i64
%result = llvm.sub %zero, %div : i64
The first subtraction wraps back to INT_MIN, producing +2^62 instead of
-2^62. A range inference workaround copied this incorrect sign.
Compute a truncating quotient and increment it only for inexact divisions
with same-sign operands. Use this for Index folding and LLVM/SPIR-V
lowering, and remove the inference workaround to match the Arith expansion.
[mlir] Fix signed ceiling division of INT_MIN
Negating INT_MIN causes signed overflow even when its quotient is
representable. For INT_MIN / 2, the Index expansion included:
%zero = llvm.mlir.constant(0 : i64) : i64
%n = llvm.mlir.constant(-9223372036854775808 : i64) : i64
%m = llvm.mlir.constant(2 : i64) : i64
%neg_n = llvm.sub %zero, %n : i64 // Overflow: -INT_MIN is unrepresentable.
%div = llvm.sdiv %neg_n, %m : i64
%result = llvm.sub %zero, %div : i64
The first subtraction wraps back to INT_MIN, producing +2^62 instead of
-2^62. A range inference workaround copied this incorrect sign.
Compute a truncating quotient and increment it only for inexact divisions
with same-sign operands. Use this for Index folding and LLVM/SPIR-V
lowering, and remove the inference workaround to match the Arith expansion.
[clang][Sema] Expand `#embed` in braced lists that initialize non-aggregates (#231938)
Fixes #222796
A multi-byte `#embed` inside braces is one `EmbedExpr`, and only
aggregate initialization slices it. Every other consumer of the braced
list counted it as a single element, so `X x = { #embed ... }` called
the constructor with the first byte only, and a reference or fixed enum
silently took the first byte instead of being rejected.
`Sema::getInitsWithEmbedExpanded()` hands those consumers the list with
each multi-element `EmbedExpr` split into one single-element `EmbedExpr`
per byte, the same slices aggregate initialization already builds.
Constructor selection, braced-argument overload resolution and CTAD use
it; the single-element and excess-element checks go through the new
`InitListExpr::hasZeroInits()` / `hasOneInit()`. Aggregates still keep
the whole `EmbedExpr`.
For more reference, see https://github.com/llvm/llvm-project/pull/218262
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[MLIR][XeGPU] Rematerialize layout conversion sources after conflict resolution (#230669)
This PR separates layout conflict resolution from rematerialization. The
resolver now inserts xegpu.convert_layout for conflicts ....a following
step clones eligible, cheap vector producer chains in the target layout
and replaces those conversions. This avoids SLM round trips.
[RISCV][P-ext] Add isel patterns for mul.h01/mul.h11 and macc.h01/macc.h11 (#234976)
`mul.h01` multiplies the lower half word of rs1 by the upper half word
of rs2, and `mul.h11` multiplies the upper half words of both.
`macc.h01/h11` add the product to rd.
Previously, (sra X, 16) was selected as a separate srai feeding
`mul/macc.h00`. Match it directly so the shift is folded. As with
`macc.h00`, the macc patterns require the multiply to have a single use.
