LLVM/project 76a523c — llvm/lib/Target/RISCV RISCVVectorPeephole.cpp, llvm/test/CodeGen/RISCV/rvv vmand-to-masked-compare.mir vmerge-peephole.mir

RISCV: Fix ensureDominates crashes on operands without a vreg def

ensureDominates used an unchecked getVRegDef on every register
operand. This crashed on physical register uses or undef vregs. Also
fix dropping an incoming undef flag which would fail the verifier.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+49-0llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
+23-0llvm/test/CodeGen/RISCV/rvv/vmand-to-masked-compare.mir
+8-1llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+80-13 files

LLVM/project 5cc816a — llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AArch64 cast.ll

[AARCH64][COST]Cost non-pow2 i1 vector bitcast to int

No bitmask lowering for non-pow2 i1 vectors; lanes are extracted and
packed one by one. Price extracts plus N-1 combines instead of a
single cross-bank move.

Required to avoid regressions in non-power-of-2 SLP support

Assisted-by: Cursor

Reviewers: paulwalker-arm, huntergr-arm, sdesmalen-arm, davemgreen

Pull Request: https://github.com/llvm/llvm-project/pull/238357
DeltaFile
+13-0llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+6-0llvm/test/Analysis/CostModel/AArch64/cast.ll
+2-2llvm/test/Transforms/VectorCombine/AArch64/icmp-vector-reduce.ll
+21-23 files

LLVM/project ebb1565 — llvm/include/llvm/IR RuntimeLibcallsImpl.td RuntimeLibcalls.td, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Move divrem attributes to TableGen

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-21llvm/lib/IR/RuntimeLibcalls.cpp
+2-0llvm/include/llvm/IR/RuntimeLibcalls.td
+1-0llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+3-213 files

LLVM/project f52a50d — llvm/include/llvm/IR RuntimeLibcalls.td, llvm/test/Transforms/Util/DeclareRuntimeLibcalls systemz.ll bsd.ll

RuntimeLibcalls: Add missing attributes to memory and allocator libcalls

Add the attributes inferLibFuncAttributes would give these functions.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+69-26llvm/include/llvm/IR/RuntimeLibcalls.td
+49-35llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ppc.ll
+46-36llvm/test/Transforms/Util/DeclareRuntimeLibcalls/aarch64.ll
+36-28llvm/test/Transforms/Util/DeclareRuntimeLibcalls/windows.ll
+27-21llvm/test/Transforms/Util/DeclareRuntimeLibcalls/bsd.ll
+18-14llvm/test/Transforms/Util/DeclareRuntimeLibcalls/systemz.ll
+245-16015 files not shown
+415-28021 files

LLVM/project 8ca0f31 — llvm/include/llvm/IR RuntimeLibcalls.td, llvm/test/Transforms/Util/DeclareRuntimeLibcalls divmod.ll

RuntimeLibcalls: Annotate divrem libcall remainder out arguments

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+16-5llvm/include/llvm/IR/RuntimeLibcalls.td
+3-2llvm/test/Transforms/Util/DeclareRuntimeLibcalls/divmod.ll
+19-72 files

LLVM/project e9421b7 — llvm/include/llvm/IR RuntimeLibcalls.td RuntimeLibcallsImpl.td, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Move malloc, calloc and free attributes to TableGen

This requires new attribute plumbing for attributes that have an
argument value.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+2-70llvm/lib/IR/RuntimeLibcalls.cpp
+59-11llvm/test/TableGen/RuntimeLibcallEmitter-attributes.td
+38-18llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
+28-5llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+24-3llvm/include/llvm/IR/RuntimeLibcalls.td
+20-0llvm/test/TableGen/RuntimeLibcallEmitter-attributes-errors.td
+171-1072 files not shown
+179-1128 files

LLVM/project 66bc949 — llvm/include/llvm/IR RuntimeLibcallsImpl.td RuntimeLibcalls.td, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Move sqrt attributes to TableGen

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-20llvm/lib/IR/RuntimeLibcalls.cpp
+11-1llvm/include/llvm/IR/RuntimeLibcalls.td
+7-2llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+4-4llvm/test/Transforms/Util/DeclareRuntimeLibcalls/hexagon.ll
+3-3llvm/test/Transforms/Util/DeclareRuntimeLibcalls/systemz.ll
+3-2llvm/test/Transforms/Util/DeclareRuntimeLibcalls/arm64ec.ll
+28-326 files

LLVM/project 11546fa — .github CODEOWNERS

[github] Remove stale CODEOWNERS entries

GitHub reports that three existing owners no longer satisfy CODEOWNERS
access requirements. Their entries were added in 2024. Remove the invalid
owners while retaining the other reviewers for each path.

LLM-aided
DeltaFile
+7-4.github/CODEOWNERS
+7-41 files

LLVM/project 5fe23e3 — llvm/test/Transforms/Util/DeclareRuntimeLibcalls systemz.ll sparc.ll

RuntimeLibcalls: Add attributes to math libcall out arguments (#240705)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+43-43llvm/test/Transforms/Util/DeclareRuntimeLibcalls/aarch64.ll
+39-39llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ppc.ll
+35-35llvm/test/Transforms/Util/DeclareRuntimeLibcalls/windows.ll
+33-33llvm/test/Transforms/Util/DeclareRuntimeLibcalls/bsd.ll
+24-24llvm/test/Transforms/Util/DeclareRuntimeLibcalls/systemz.ll
+24-24llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sparc.ll
+198-19811 files not shown
+317-29917 files

LLVM/project 306deca — llvm/test/TableGen RegClassEmptyAllocationOrder.td, llvm/utils/TableGen/Common CodeGenRegisters.cpp

TableGen: Error on allocatable register classes with an empty allocation order

A register can never be allocated from a class with an empty
allocation order. This can happen when an alternative order excludes
every member, or when an inferred class inherits such an order from
its super class.

Classes with no members are exempt, since AMDGPU's VReg_1 is a verfy
hacky, intentionally empty allocatable class.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+49-0llvm/test/TableGen/RegClassEmptyAllocationOrder.td
+15-0llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+64-02 files

LLVM/project 814ab0e — libc/src/time time_utils.cpp time_utils.h, libc/test/src/time CMakeLists.txt time_utils_test.cpp

[libc] Use fast day-of-week and time-of-day algorithms in time_utils (#238163)

Add two constexpr helpers to time_utils.h and use them in
update_from_seconds:

- get_weekday(unix_days): Ben Joffe's mul-add-shift weekday algorithm
  (https://www.benjoffe.com/fast-day-of-week). Because 7 = 2^3 - 1,
  x mod 7 == floor(x * 8 / 7) mod 8. Multiplying by ceil(2^64 / 7) and
  adding a rotation constant puts the weekday in the top 3 bits. It is
  valid for about +/-631 trillion years, well beyond the range accepted
  by update_from_seconds.
- get_time_of_day(seconds_of_day): Ben Joffe's "V2 - Fixed-Point Hi/Low
  Bits" algorithm (https://www.benjoffe.com/fast-time-of-day). It splits
  seconds into hour, minute and second with four multiplications and no
  division. Hour and minute come from the high and low bits of one
  product and the second comes from a separate product, so the two run
in parallel instead of the hour -> remainder -> minute -> second chain.
  It is valid for [0, 2255818].


    [43 lines not shown]
DeltaFile
+197-0libc/test/src/time/time_utils_test.cpp
+75-0libc/src/time/time_utils.h
+21-0libc/test/src/time/CMakeLists.txt
+7-12libc/src/time/time_utils.cpp
+300-124 files

LLVM/project 9cebeba — llvm/lib/Target/ARM ARMRegisterInfo.td

Mark GPRip as not allocatable
DeltaFile
+3-1llvm/lib/Target/ARM/ARMRegisterInfo.td
+3-11 files

HardenedBSD/src 3821312 — sys/kern kern_module.c

HBSD: Resolve merge conflict

Signed-off-by:  Shawn Webb <shawn.webb at hardenedbsd.org>
DeltaFile
+0-7sys/kern/kern_module.c
+0-71 files

LLVM/project 7b06c97 — llvm/include/llvm/Target Target.td, llvm/test/TableGen AsmMatcherCoerceFromRegClass.td

[nspr] initial commit
DeltaFile
+108-29llvm/utils/TableGen/AsmMatcherEmitter.cpp
+99-0llvm/test/TableGen/AsmMatcherCoerceFromRegClass.td
+11-3llvm/include/llvm/Target/Target.td
+218-323 files

LLVM/project a8c1b60 — llvm/include/llvm/Target Target.td, llvm/test/TableGen AsmMatcherPredicatePassSubtarget.td

[nspr] initial commit
DeltaFile
+55-0llvm/test/TableGen/AsmMatcherPredicatePassSubtarget.td
+6-2llvm/utils/TableGen/AsmMatcherEmitter.cpp
+5-0llvm/include/llvm/Target/Target.td
+66-23 files

LLVM/project 52c378f — llvm/lib/Target/RISCV RISCVRegisterInfo.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[nspr] initial commit
DeltaFile
+6-104llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+44-31llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+7-11llvm/test/MC/RISCV/asm-matcher-no-mutation.s
+57-1463 files

LLVM/project b60e557 — llvm/test/MC/RISCV rv32i-invalid.s asm-matcher-no-mutation.s

[nspr] initial commit
DeltaFile
+51-0llvm/test/MC/RISCV/asm-matcher-no-mutation.s
+4-0llvm/test/MC/RISCV/rv32i-invalid.s
+55-02 files

LLVM/project d76773b — llvm/lib/CodeGen/GlobalISel IRTranslator.cpp, llvm/test/CodeGen/AArch64 bitinsert-bitextract-vector.ll

[GlobalISel] Lower vector `bitinsert` and `bitextract`
DeltaFile
+128-58llvm/test/CodeGen/AArch64/bitinsert-bitextract-vector.ll
+13-12llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+141-702 files

LLVM/project c4837f8 — llvm/test/CodeGen/X86 bitinsert-bitextract-vector.ll

[SelectionDAG] Use x86-64 levels in vector `bitinsert`/`bitextract` X86 test
DeltaFile
+361-58llvm/test/CodeGen/X86/bitinsert-bitextract-vector.ll
+361-581 files

LLVM/project 624461a — llvm/test/tools/llubi bitinsert_bitextract_le.ll bitinsert_bitextract_be.ll, llvm/tools/llubi/lib Interpreter.cpp

[llubi] Add support for vector `bitinsert` and `bitextract`
DeltaFile
+26-22llvm/tools/llubi/lib/Interpreter.cpp
+32-0llvm/test/tools/llubi/bitinsert_bitextract_le.ll
+32-0llvm/test/tools/llubi/bitinsert_bitextract_be.ll
+90-223 files

LLVM/project 506717c — llvm/test/CodeGen/AArch64 sve-bitinsert-bitextract.ll bitinsert-bitextract-vector.ll, llvm/test/CodeGen/AMDGPU bitinsert-bitextract-vector.ll

[SelectionDAG] Lower vector `bitinsert` and `bitextract`
DeltaFile
+928-0llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-vector.ll
+476-0llvm/test/CodeGen/X86/bitinsert-bitextract-vector.ll
+240-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitinsert-bitextract.ll
+138-0llvm/test/CodeGen/AArch64/bitinsert-bitextract-vector.ll
+34-0llvm/test/CodeGen/RISCV/rvv/bitinsert-bitextract.ll
+27-0llvm/test/CodeGen/AArch64/sve-bitinsert-bitextract.ll
+1,843-01 files not shown
+1,845-27 files

LLVM/project 5dc0668 — llvm/test/Transforms/InstCombine bitinsert-bitextract.ll, llvm/test/Transforms/InstSimplify bitinsert-bitextract.ll

[InstSimplify][InstCombine] Add vector tests for `bitinsert` and `bitextract`
DeltaFile
+140-0llvm/test/Transforms/InstSimplify/bitinsert-bitextract.ll
+93-0llvm/test/Transforms/InstCombine/bitinsert-bitextract.ll
+16-0llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+249-03 files

LLVM/project efbd9c3 — llvm/docs LangRef.md, llvm/lib/IR Instructions.cpp

[IR] Allow vectors in `bitinsert` and `bitextract`
DeltaFile
+108-4llvm/test/Assembler/bitinsert-bitextract-invalid.ll
+89-0llvm/test/Assembler/bitinsert-bitextract.ll
+29-20llvm/docs/LangRef.md
+27-14llvm/lib/IR/Instructions.cpp
+31-0llvm/test/Transforms/InstSimplify/ConstProp/bitinsert-bitextract.ll
+15-0llvm/test/Verifier/bitextract-bitinsert-invalid-verifier.ll
+299-386 files not shown
+336-4512 files

LLVM/project ff315fd — llvm/test/Assembler bitinsert-bitextract-invalid.ll

[IR] Remove dead CHECK lines in `bitinsert-bitextract-invalid.ll`
DeltaFile
+36-33llvm/test/Assembler/bitinsert-bitextract-invalid.ll
+36-331 files

LLVM/project 9ec8003 — .github CODEOWNERS

[clang] Fix CODEOWNERS errors for ClangIR

GitHub reports an unknown owner for the ClangIR rules. Remove Lanza from
all four active ownership rules and retain an emeritus owner comment.
This can be revisited if write access is restored.

LLM-aided
DeltaFile
+6-4.github/CODEOWNERS
+6-41 files

LLVM/project 71cd4b0 — llvm/lib/IR Core.cpp

[LLVM] Silence a deprecation warning; NFC (#241008)

MSVC deprecation warnings are a bit more aggressive than Clang and GCC
warnings in that calling a deprecated from another deprecated function
is still diagnosed.

LLVMCreateBuilder itself is deprecated, so that's why this is silenced
for Clang and GCC already.
DeltaFile
+2-0llvm/lib/IR/Core.cpp
+2-01 files

LLVM/project fa8e6e1 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-32.ll rvp-simd-64.ll

[RISCV][P-ext] Lower 2 element insert_vector_elt to scalar_to_vec+ppaire/ppaireo.

This avoids needing to match the srl+build_vec later which we only
do on RV64.
DeltaFile
+9-14llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-4llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+1-2llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+12-203 files

FreeBSD/src 7cb4d4d — share/man/man4 sched_ule.4, sys/kern sched_ule.c

sched_ule.4: sync current scheduler sysctls

Reviewed by:    bcr, jhb, olce
Approved by:    jhb, olce (mentor)
MFC after:      2 weeks
Sponsored by:   FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D60002
DeltaFile
+37-6share/man/man4/sched_ule.4
+1-0sys/kern/sched_ule.c
+38-62 files

FreeBSD/src be25f6d — share/man/man4 sched_4bsd.4, sys/kern sched_4bsd.c

sched_4bsd.4: sync current scheduler sysctls

Reviewed by:    bcr, jhb, olce
Approved by:    jhb, olce (mentor)
MFC after:      2 weeks
Sponsored by:   FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D60002
DeltaFile
+21-16share/man/man4/sched_4bsd.4
+1-0sys/kern/sched_4bsd.c
+22-162 files

FreeBSD/src fb797f8 — share/man/man4 Makefile smp.4

scheduler.4: document common scheduler sysctls

Reviewed by:    bcr, jhb, olce
Approved by:    jhb, olce (mentor)
MFC after:      2 weeks
Sponsored by:   FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D60002
DeltaFile
+61-0share/man/man4/scheduler.4
+5-2share/man/man4/sched_ule.4
+5-2share/man/man4/sched_4bsd.4
+2-1share/man/man4/smp.4
+2-1share/man/man4/dtrace_sched.4
+1-0share/man/man4/Makefile
+76-66 files