LLVM/project 052fb00clang/include/clang/Options Options.td, clang/test/Driver cl-options.c

[clang] Expose -fmodules-disable-diagnostic-validation as clang-cl option (#176285)

DeltaFile
+1-1clang/include/clang/Options/Options.td
+1-0clang/test/Driver/cl-options.c
+2-12 files

Illumos/gate 691ceb5usr/src/cmd/smbsrv/smbadm smbadm.c

17770 smbadm: double free of 'mname' is actually missing no return attribute
Reviewed by: Robert Mustacchi <rm+illumos at fingolfin.org>
Reviewed by: Gordon Ross <gordon.w.ross at gmail.com>
Approved by: Dan McDonald <danmcd at edgecast.io>
DeltaFile
+1-1usr/src/cmd/smbsrv/smbadm/smbadm.c
+1-11 files

FreeNAS/freenas ab673b6src/middlewared/middlewared/plugins network.py

switch back to list_interfaces() in configure
DeltaFile
+1-1src/middlewared/middlewared/plugins/network.py
+1-11 files

LLVM/project f97f53emlir/include/mlir/Dialect/Tosa/IR TosaOps.td, mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Add support for CONV2D_BLOCK_SCALED operator (#172294)

This commit adds support for an MXFP CONV2D operation,
CONV2D_BLOCK_SCALED, added to the specification in
https://github.com/arm/tosa-specification/commit/408a5e53f5a7357adef7121ba3cc88e2225d4231.

This includes:
- Operator definition
- Addition of the EXT_MXFP_CONV extension
- Verification logic for the operator
- Output shape inference for the operator
- Validation checks to ensure compliance with the TOSA specification.
DeltaFile
+315-79mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+132-0mlir/test/Dialect/Tosa/verifier.mlir
+71-0mlir/test/Dialect/Tosa/level_check.mlir
+49-2mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+48-0mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+37-0mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
+652-8111 files not shown
+766-9317 files

FreeBSD/ports d68e67emath/openblas64 distinfo Makefile, math/openblas64/files patch-CMakeLists.txt patch-cmake_system.cmake

math/openblas64: upgrade to 0.3.31

Release notes at https://github.com/OpenMathLib/OpenBLAS/releases/tag/v0.3.31
DeltaFile
+4-11math/openblas64/files/patch-CMakeLists.txt
+0-13math/openblas64/files/patch-cmake_system.cmake
+3-3math/openblas64/distinfo
+2-2math/openblas64/files/patch-exports_Makefile
+1-1math/openblas64/Makefile
+10-305 files

FreeBSD/ports adb8675lang/lfortran Makefile distinfo

lang/lfortran: upgrade to v0.59.0

Release note at https://github.com/lfortran/lfortran/releases/tag/v0.59.0

Remark: BFD is disbled for the moment.
DeltaFile
+4-4lang/lfortran/Makefile
+3-3lang/lfortran/distinfo
+7-72 files

FreeBSD/src 87c4d65sys/x86/cpufreq hwpstate_amd.c

hwpstate_amd: Use ipi instead of sched_bind + thread_lock

Reviewed by:    olce
Approved by:    markj (mentor)
MFC after:      2 weeks
Differential Revision: https://reviews.freebsd.org/D54505
DeltaFile
+79-67sys/x86/cpufreq/hwpstate_amd.c
+79-671 files

FreeBSD/src 5b61ef9sys/kern subr_smp.c, sys/sys smp.h

smp: add smp_rendezvous_cpu helper function

Reviewed by:    olce
Approved by:    markj (mentor)
MFC after:      2 weeks
Differential Revision:  https://reviews.freebsd.org/D54551
DeltaFile
+13-0sys/kern/subr_smp.c
+7-1sys/sys/smp.h
+20-12 files

OPNSense/core 1e4952asrc/opnsense/scripts/kea kea_prefix_watcher.py

dhcp/kea: exit prefix watcher if no lease file exists
DeltaFile
+5-0src/opnsense/scripts/kea/kea_prefix_watcher.py
+5-01 files

LLVM/project 6856ddallvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Apply monotonicity check for Strong SIV
DeltaFile
+83-55llvm/lib/Analysis/DependenceAnalysis.cpp
+27-35llvm/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
+18-18llvm/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll
+13-19llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
+9-13llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
+14-4llvm/include/llvm/Analysis/DependenceAnalysis.h
+164-14412 files not shown
+197-20318 files

LLVM/project d358d7bllvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Move some monotonicity declarations to header file (NFC)
DeltaFile
+35-111llvm/lib/Analysis/DependenceAnalysis.cpp
+80-0llvm/include/llvm/Analysis/DependenceAnalysis.h
+115-1112 files

LLVM/project 9587892llvm/include/llvm/TargetParser Triple.h, llvm/lib/TargetParser Triple.cpp

[Triple] Add "chipstar" OS components (#170655)

This new component is for Clang driver for selecting HIPSPV toolchain.
DeltaFile
+5-0llvm/unittests/TargetParser/TripleTest.cpp
+3-0llvm/lib/TargetParser/Triple.cpp
+2-1llvm/include/llvm/TargetParser/Triple.h
+10-13 files

LLVM/project 4afcc4bclang/include/clang/Options Options.td, clang/lib/Driver/ToolChains Clang.cpp

Add `-Xoffload-compiler` option (#170467)

... to forward input to clang-linker-wrapper's device compiler
invocation.

(a separate patch as requested in #168043)
DeltaFile
+10-5clang/lib/Driver/ToolChains/Clang.cpp
+6-0clang/test/Driver/openmp-offload-gpu.c
+4-0clang/include/clang/Options/Options.td
+20-53 files

LLVM/project 83ffe1emlir/test/python/dialects transform_interpreter.py

[MLIR][Python] add builtin module transform test
DeltaFile
+19-0mlir/test/python/dialects/transform_interpreter.py
+19-01 files

LLVM/project 5f697b3llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

AArch64: Use getLibcallImplCallingConv more consistently (#176377)

This was querying the calling conv from the Libcall instead of
the LibcallImpl.
DeltaFile
+2-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-11 files

LLVM/project 4c0f295llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPUGlobalISelUtils.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fpext.ll unmerge-sgpr-s16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES

Move G_UNMERGE_VALUES handling to AMDGPURegBankLegalizeRules.cpp.
Fix sgpr S16 unmerge by lowering using shift and using S32.
Previously sgpr S16 unmerge was selected using _lo16 and _hi16 subreg
indexes which are exclusive to vgpr register classes.
For remaing cases we do trivial mapping, assigns same reg bank
to all operands, vgpr or sgpr.
DeltaFile
+47-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+13-27llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
+36-0llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
+18-0llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+10-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+6-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+130-282 files not shown
+137-318 files

LLVM/project bd17d55llvm/lib/Target/AArch64 AArch64SelectionDAGInfo.cpp

AArch64: Avoid getLibcallName when emitting special mem libcalls (#176376)

Get the symbol through the RTLIB::LibcallImpl enum.
DeltaFile
+6-3llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
+6-31 files

FreeBSD/src b39662fsys/arm/broadcom/bcm2835 files.bcm283x, sys/conf kern.mk files.arm64

vchiq: fix build with clang 21

When compiling vchiq with clang 21, the following -Werror warning is
produced:

    sys/contrib/vchiq/interface/vchiq_arm/vchiq_arm.c:728:27: error: default initialization of an object of type 'VCHIQ_QUEUE_MESSAGE32_T' with const member leaves the object uninitialized [-Werror,-Wdefault-const-init-field-unsafe]
      728 |                 VCHIQ_QUEUE_MESSAGE32_T args32;
          |                                         ^
    sys/contrib/vchiq/interface/vchiq_arm/vchiq_ioctl.h:151:40: note: member 'elements' declared 'const' here
      151 |         const /*VCHIQ_ELEMENT_T * */ uint32_t elements;
          |                                               ^

While the warning is formally correct, the 'args32' object is
immediately initialized after its declaration. Therefore, suppress the
warning.

MFC after:      3 days
DeltaFile
+3-0sys/conf/kern.mk
+1-1sys/conf/files.arm64
+1-1sys/arm/broadcom/bcm2835/files.bcm283x
+5-23 files

LLVM/project 832b091llvm/test/TableGen directive2.td directive1.td, llvm/utils/TableGen/Basic DirectiveEmitter.cpp

Restore comment with a period at the end
DeltaFile
+2-0llvm/test/TableGen/directive2.td
+2-0llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
+2-0llvm/test/TableGen/directive1.td
+6-03 files

LLVM/project 129ccf9llvm/include/llvm/Transforms/Utils LowerMemIntrinsics.h, llvm/lib/Transforms/Utils LowerMemIntrinsics.cpp

Add an overload of `expandMemSetAsLoop` that takes an optional TTI pointer

This avoids breaking the API for out-of-tree tools like the
SPIRV-LLVM-Translator.
DeltaFile
+24-12llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
+7-0llvm/include/llvm/Transforms/Utils/LowerMemIntrinsics.h
+31-122 files

LLVM/project 14349bcllvm/lib/Target/AVR AVRISelLowering.cpp

AVR: Avoid getLibcallName (#176375)

Create the symbol through RTLIB::LibcallImpl
DeltaFile
+8-4llvm/lib/Target/AVR/AVRISelLowering.cpp
+8-41 files

LLVM/project 47689d2llvm/utils/release github-upload-release.py

[llvm][utils][release] Remove mention of sub-project source archives (#176348)

These are no longer provided as of llvm 22:
https://discourse.llvm.org/t/llvm-22-1-0-rc1-released/89479

> Please note: since the last release the subproject tarballs have been
> removed and are no longer provided. See RFC: Do "something" with the
> subproject tarballs in the release page for more details.

There are now only llvm-project and llvm-test-suite archives.
DeltaFile
+1-1llvm/utils/release/github-upload-release.py
+1-11 files

SmartOS/live ff3cb7esrc/vm/node_modules/cloudinit lofs-fat16.js index.js

Add license header to new files
DeltaFile
+22-1src/vm/node_modules/cloudinit/lofs-fat16.js
+21-0src/vm/node_modules/cloudinit/index.js
+21-0src/vm/node_modules/cloudinit/nocloud.js
+64-13 files

LLVM/project 9e6b658llvm/lib/Target/Hexagon HexagonSelectionDAGInfo.cpp

Hexagon: Avoid using getLibcallName for special memcpy (#176374)

Create the symbol through the RTLIB::LibcallImpl enum.
DeltaFile
+7-4llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
+7-41 files

LLVM/project 907b6c6llvm/test/CodeGen/AMDGPU fmul-to-ldexp.ll llvm.log10.ll

[AMDGPU] si-peephole-sdwa: Handle V_PACK_B32_F16_e64 (WIP)

Change si-peephole-sdwa to eliminate V_PACK_B32_F16_e64 instructions
by changing the second operand to write to the upper word of the
destination directly.
DeltaFile
+126-140llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+138-98llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+138-98llvm/test/CodeGen/AMDGPU/llvm.log.ll
+92-104llvm/test/CodeGen/AMDGPU/fpow.ll
+68-127llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+74-118llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+636-68529 files not shown
+1,251-1,34835 files

LLVM/project a536850llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.cos.f16.ll llvm.sin.f16.ll

[AMDGPU] Enable ISD::{FSIN,FCOS} custom lowering to work on v2f16

Currently ISD::FSIN and ISD::FCOS of type MVT::v2f16 are legalized by
first expanding and then using a custom lowering on the resulting f16
instructions. This ordering prevents using packed math variants of the
instructions introduced by the legalization (e.g. the multiplication),
if available, and makes it difficult to eliminate the packing of the
results by using SDWA form; previous attempts to deal with the latter
situation in the si-peephole-sdwa pass were unwieldly since it was
necessary to reconstruct the association between the source and target
vectors.

Change the legalization action for ISD::FSIN and ISD::FCOS of type
MTF::v2f16 to Custom and change the custom intrinsic lowering to deal
with the v2f16 for the intrinsics introduced in this way.
DeltaFile
+27-38llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
+27-38llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
+34-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+88-793 files

FreeBSD/ports 182d797textproc/py-dict2xml distinfo Makefile

textproc/py-dict2xml: Update to 1.7.8

Reported by:    portscout!
DeltaFile
+3-3textproc/py-dict2xml/distinfo
+1-1textproc/py-dict2xml/Makefile
+4-42 files

LLVM/project 2eb709bllvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp, llvm/test/CodeGen/AMDGPU whole-wave-functions.ll vgpr-set-msb-coissue.mir

[AMDGPU] Fix typo in `LowerVGPREncoding` to allow it to hoist past `waitcnt` instructions (#176355)

Fixes a typo which prevented `set_vgpr_msb` to be hoisted past `waitcnt`
instructions.
DeltaFile
+3-3llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+2-2llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+1-1llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
+6-63 files

LLVM/project 135744cllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Consider nsz when simplifying fabs/fneg uses (#176156)

Later this trick should also be applied in the single use
case.
DeltaFile
+11-4llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+3-3llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+14-72 files

LLVM/project 9d43694llvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/Transforms/AtomicExpand/AMDGPU expand-atomic-f64-system.ll expand-atomic-f32-agent.ll

AtomicExpand: Use LibcallLoweringInfo analysis
DeltaFile
+36-8llvm/lib/CodeGen/AtomicExpandPass.cpp
+8-8llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
+8-8llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
+8-8llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
+8-8llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
+8-8llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
+76-4855 files not shown
+220-18561 files