[SPIR-V] Fix validation errors for function pointers with CodeSectionINTEL storage class (#192973)
CodeSectionINTEL pointers are not valid operands for
PtrCastToGeneric/GenericCastToPtr (including inside OpSpecConstantOp)
[SPIR-V] Parse parameterized Memory Access operands with a shared helper (#209262)
Copy printing only special cased Aligned, so alias list and scope IDs
were then misread as additional masks
[X86] movmsk-cmp.ll - update PR39665_c_ray test to match middle-end output (#213659)
These now lower to vXi1 reduction (as bitcast) patterns
The PR39665_c_ray_opt test folds to the same IR, so I've merged the
tests
[OpenMP] target-fast implies teams/threads oversubscription (#205775)
Enable -fopenmp-assume-teams-oversubscription and
-fopenmp-assume-threads-oversubscription by default under
-fopenmp-target-fast. Adds driver test coverage for both.
Split out of #205325 as a standalone change.
Protect persistent keyring
This commit adds a daily periodic task to refetch the persistent
keyring for uid 0. By default, persistent keyrings are garbage
collected every 3 days with the timer reset on each fetch. Although
there are typically background tasks that fetch the keyring for uid
0, it's better to ensure that it's always preserved since we store
kerberos tickets, some session information, and API keys in it.
[NFC][analyzer] Eliminate NodeBuilder from ExprEngine visit methods and from their utility methods (#212186)
This patch eliminates the remaining uses of the class `NodeBuilder` from
the `ExprEngine::Visit*` methods and from their utility methods such as
`evalLocation`, `evalLoad`, `CreateCXXTemporaryObject` and
`handleConstructor`.
[CIR][AArch64] Lower remaining FP16 vfma and vfms builtins (#210359)
Complete CIR lowering coverage for the remaining AArch64 NEON FP16 fused
multiply-accumulate and fused multiply-subtract builtins.
This covers ACLE wrappers from section 2.6.1.9.3:
- vfma_n_f16, vfmaq_n_f16
- vfms_f16, vfmsq_f16
- vfms_lane_f16, vfmsq_lane_f16
- vfms_laneq_f16, vfmsq_laneq_f16
- vfms_n_f16, vfmsq_n_f16
- vfmsh_lane_f16, vfmsh_laneq_f16
The existing CIR lowering paths already handle these wrappers. Move
their tests from AArch64/v8.2a-neon-intrinsics.c into
AArch64/neon/fused-multiple-fullfp16.c, add direct LLVM, CIR-to-LLVM,
and CIR coverage, and remove the superseded tests.
Strengthen the LLVM checks by tracking operands from their defining
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[libc++] Remove opt-out of the LLVM 23 transitive includes removal (#213245)
We've removed transitive includes by default in LLVM 23, but added an
opt-in to keep the transitive includes for the release. Now that we've
branched we can remove the transitive includes unconditionally.
RFC: https://discourse.llvm.org/t/rfc-remove-unused-transitive-includes-from-the-libc-headers
[libc++] Add missing includes in the locale headers (#213035)
Several headers use entities from `<__locale>` but rely on picking them
up transitively, in most cases through `<ios>`. Fix this in preparation
for splitting up `<__locale>`.
[libc++] Don't rely on a transitively included BYTE_ORDER in ctype_base (#213032)
Use libc++'s own _LIBCPP_BIG_ENDIAN macro instead of BYTE_ORDER, which
was relied upon from a transitive <endian.h> include on Glibc.
Name alert applicability rules and detect black-holed alerts
This commit adds changes to give the alert applicability engine one name per population instead of thirty open-coded rule constructions, and to catch alerts that are created but can never be displayed.
The rules alert declarations gate on now live in a vocabulary module next to the engine, so TRUENAS_HARDWARE is defined once rather than built at eighteen sites in two competing conventions. LicenseRule collapses into EntitlementRule, which asks the entitlement policy about any feature rather than the two the old enum could spell, so STIG and everything after it is a one-line declaration. AllOf joins AnyOf in the algebra, listed_when becomes listed_only_when to say that it narrows, and AlertFacts is gone in favour of the identical EntitlementFacts that applies() was converting to anyway.
A source whose rule is satisfied where its class's rule is not creates alerts that are stored and never shown. Nothing checked for that, and since the failover declarations deliberately straddle the two axes it is no longer something a reviewer can spot by eye. A test now infers the source to class relation out of check() and asserts the implication across every population, with a runtime guard logging the cases static analysis cannot see. It found four pre-existing ones in memory_errors and sensors, which are fixed by narrowing the sources so nothing user visible moves.
One behaviour change worth a release note: failover_related was gating enclosure_status on an HA licence, which is a licensing predicate in front of a hardware question, so unlicensed appliances will now report enclosure faults they were previously silent about. The flag is renamed post_failover_blackout to name what it actually contributes.
[flang][Lower] Flatten signed real sum terms (#211829)
Second part of generalisations requested in #207377.
Extend real sum reassociation to flatten unparenthesized addition and
subtraction into signed terms. Rebuild split groups with addition and
subtraction while preserving parenthesized subtrees as opaque values.
I did not observe any benchmark result changes as a result of this
patch.
Assisted-by: Codex
ixgbe: supply PF transmit contexts under SR-IOV
X550-family malicious-driver detection validates the transmit
context selected by a data descriptor with Check Context set. ixgbe
sets that bit on every transmit data descriptor, but ordinary PF
packets without a VLAN or checksum offload do not create a context
descriptor. The empty context then reports an invalid MAC-header
length and blocks the PF queue as soon as MDD is enabled.
Create the existing context descriptor for every PF packet while
SR-IOV is active. This supplies the required MAC-header length and
keeps MDD from mistaking normal PF traffic for a malicious-driver
event.
MFC after: 1 week
igc: Add VLAN hardware filtering
Borrow the e1000 VLAN filter table
Ambiguous presence of the feature by Intel was settled by DPDK and
emperical testing.
MFC after: 2 weeks
Relnotes: yes
[lldb] Introduce RegisterType base class for all register type classes (#196960)
This is refactoring to prepare for
https://github.com/llvm/llvm-project/issues/87471. Where we will be
adding support for describing registers as unions and vectors. See:
https://sourceware.org/gdb/current/onlinedocs/gdb.html/Target-Description-Format.html
A union is like a C union and references other types defined in the XML.
Just like a set of register flags might reference an enum for one of
those flags.
By introducing this base class I'm making the treatment of all these
different types generic. So that when encoding them as XML we can emit
the type's dependencies recursively, and then emit the type itself.
This strategy will also be used later in RegisterTypeBuilderClang to
generate AST to represent these types.
As GDB decided to include size in enums, whenever we emit something it
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[GlobalISel] avoid G_TRUNC with floating-point G_MERGE_VALUES source (#206733)
With extended LLT, scalar LLT carry an integer/float kind information.
The `G_TRUNC(G_MERGE_VALUES)` fold in
`LegalizationArtifactCombiner::tryCombineTrunc` truncated, copied or
rebuilt a merge directly from the merge's source register.
**Problem**
When those sources are floating-point this produces artifacts with float
source operand - e.g. `i1 = G_TRUNC f32` or a rebuilt `iN =
G_MERGE_VALUES f32, ...` which are bit level integer operations and must
not take a float operand.
**Fix**
Reinterpret a floating-point merge source to an integer of the same size
via `G_BITCAST` before truncating, copying or rebuilding the merge. So
the emitted artifacts stay on integer operands. Non-float sources and
non-extended-LLT builds are unaffected.
