[VPlan] Add ExitingIVValue VPInstruction. (#175651)
Add a new VPInstruction opcode to compute the exiting value of an
induction variable after vectorization. This replaces the pattern of
extracting the last lane from the last part of the induction backedge
value when applicable.
This allows us to always use the pre-computed IV end value. It will also
allow unifying end value creation for both induction resume and exit
values.
PR: https://github.com/llvm/llvm-project/pull/175651
[NFC][analyzer] Remove IndirectGotoNodeBuilder::iterator (#180167)
My recent commit b96ef9c97bee44017bd832efab899ba1ed1f9b8f removed a
needlessly overcomplicated iterator class from SwitchNodeBuilder; this
commit repeats the same cleanup for IndirectGotoNodeBuilder.
(This is just for the sake of consistency -- I don't have plans to work
on indirect goto handling.)
[AArch64][SDAG] Legalise BSWAP for Neon types. (#179702)
GlobalISel legalised BSWAP for Neon types in #80036.
Legalising the types keeps them from being expanded to vector_shuffle
before being matched to REVs, and allows half-rotations on i16 vectors
to be combined to bswap (see
https://github.com/llvm/llvm-project/pull/178706#discussion_r2742804463).
AMDGPU: Correct value and name for ID_RTN_SAVE_WAVE_HAS_TDM
The old name and ID value do not match the documentation. The
documentation calls this RTN_SAVE_WAVE_HAS_TDM with the value
0x98.
[VectorCombine] Skip dead shufflevector in GetIndexRangeInShuffles to fix crash. (#179217)
Update GetIndexRangeInShuffles to skip unused shuffles. This matches the
behavior in the loop below and without it, we end up with an index
mis-match, causing a crash for the added test case.
PR: https://github.com/llvm/llvm-project/pull/179217
[lldb-dap] Remove end line and column from disassemble response (#180037)
The end line entry calculated from the instruction's end address is
unreliable and could produce incorrect source ranges. especially if the
instruction spans multiple lines.
We can end in situations where the current end line is the next start
line and the source line is show to the client twice. confusing users
what maps to what.
| With EndLine |
| :------------: |
| <img width="892" height="486" alt="Screenshot 2026-02-05 at 21 37 08"
src="https://github.com/user-attachments/assets/f2fef592-5754-4168-bf93-2baba4742c5d"
/> |
| Without Endline |
| :---------------: |
| <img width="892" height="486" alt="Screenshot 2026-02-05 at 21 59 29"
[17 lines not shown]
sys/conf/options: remove improper full stops
Only keep them when used in a sentence.
Reviewed by: vexeduxr
Signed-off-by: Quentin Thébault <quentin.thebault at defenso.fr>
Sponsored by: Defenso
Closes: https://github.com/freebsd/freebsd-src/pull/2004
NAS-139647 / 26.0.0-BETA.1 / optimize interface/sync.py (#18157)
This makes a single call to "get_links" before we configure any
interfaces to reduce the number of netlink calls we make when
configuring these interfaces. The truenas_pynetif functions were written
with this in mind and so this just changes it so that we take advantage
of it. Instead of calling "get_links" (which enumerates all interfaces)
for every interface, it only calls it once and the cache is updated with
each interface after it has been configured.
While here, fix the socket type annotation.
[ExpandIRInsts] Freeze input in itofp expansion (#180157)
We are introducing branches on the value, and branch on undef/poison is
UB, so the value needs to be frozen.
[LV] Support conditional scalar assignments of masked operations (#178862)
This patch extends the support added in #158088 to loops where the
assignment is non-speculatable (e.g. a conditional load or divide).
For example, the following loop can now be vectorized:
```
int simple_csa_int_load(
int* a, int* b, int default_val, int N, int threshold)
{
int result = default_val;
for (int i = 0; i < N; ++i)
if (a[i] > threshold)
result = b[i];
return result;
}
```
[2 lines not shown]
AMDGPU: Add llvm.amdgcn.s.wait.event intrinsic
Exactly match the s_wait_event instruction. For some reason we already
had this instruction used through llvm.amdgcn.s.wait.event.export.ready,
but that hardcodes a specific value. This should really be a bitmask that
can combine multiple wait types.
gfx11 -> gfx12 broke compatabilty in a weird way, by inverting the
interpretation of the bit but also shifting the used bit by 1. Simplify
the selection of the old intrinsic by just using the magic number 2, which
should satisfy both cases.
InstCombine: Only propagate callsite attributes in sqrt->sqrtf (#180160)
This was propagating the callee's attributes instead of just the
callsite. It's illegal to set denormal_fpenv on a callsite. This
was also losing callsite attributes which may have been more useful;
there's no point in setting the callee's attributes on the callsite.
[AArch64][GloballISel] Put result of fp16 -> s16 convert intrinsic on fpr
Previously, RegBankSelect would place the result of an fp16 -> s16 conversion intrinsic on a gpr. This would cause Instruction Selection to fail, as there are no 16-bit gprs.
Floating point convert intrinsics affected:
fcvtnu / fcvtns
fcvtau / fcvtas
fcvtmu / fcvtms
fcvtpu / fcvtps
