[IR2Vec] llvm-ir2vec python bindings scaffolding (#176571)
This patch adds the build infrastructure for Python bindings to
llvm-ir2vec.
Addresses https://github.com/llvm/llvm-project/issues/141839
Changes:
- Add `LLVM_IR2VEC_ENABLE_PYTHON_BINDINGS` CMake option (default OFF)
- Create minimal python module using nanobind
- Add lit test configuration that skips when the bindings have not been
requested
Build requires nanobind and is enabled via `cmake
-DLLVM_IR2VEC_ENABLE_PYTHON_BINDINGS=ON ... `
Future patches will add actual IR2Vec API functionality.
[RISCV][llvm] Simplify the name in VSD/VVL patterns. NFC (#177108)
Original PR:https://github.com/llvm/llvm-project/pull/176750 was
accepted but accidentally merged without merging its stacked PR first.
[llvm][utils] Remove source owner check from merge-release-pr script (#176949)
This check prevents landing PRs from branches on llvm/llvm-project which
is a thing now.
Add control-flow-hub-finalize-same-succ-crash.ll to xfail (#177105)
Introduced in #176620. It appears to expose a profile propagation issue
in FixIrreducible. That pass hasn't yet been addressed.
[RISCV][llvm] Support [v]select codegen for zvfbfa (#176865)
This enables [v]select to select vfmerge.vfm, it also enables bf16
to use vmerge.vxm and vmerge.vim where we haven't handled for zvfbfmin.
[LoongArch] Remove DAG combination for extractelement (#177083)
Combination for `trunc+extend+extractelement` to a single
`extractelement` may occur error, because the high bits of the extract
index truncated by `trunc` operation are reserved after the combination.
This commit remove this combination and the issue
https://github.com/llvm/llvm-project/issues/176839 will never appear.
[Linalg] Update Vectorization to work with both named as well as generic conv ops (#176339)
-- This commit updates Vectorization to work with both named as well as
generic convolution ops. This concerns an update to the specialized path
already taken for vectorizing named convolution op.
-- Therefore the functions updated are : `vectorizeConvolution`,
`vectorizeDynamicConvOpPrecondition`,
`vectorizeScalableVectorPrecondition` and `vectorizeOpPrecondition`.
-- Changes were made to the constructor of `Conv1DGenerator` which is
invoked by `vectorizeConvolution` to check the precondition iof the op
being a valid 1D Conv Op with extractable strides/dilations info.
-- In order to not duplicate the tests for generic convolution ops, we
add another `RUN:` line which would first generalize the named
convolution ops and then apply the vectorizing transformation.
Signed-off-by: Abhishek Varma <abhvarma at amd.com>
[AMDGPU] Fix insertSimulatedTrap to return correct continuation block (#174774)
`insertSimulatedTrap` was returning `HaltLoopBB` when the trap was in a
block with no successors and was the last instruction. Since
`HaltLoopBB` gets appended to the end of the function, `FinalizeISel`
would jump there and skip any intermediate blocks, leaving their pseudos
unexpanded.
Fix by returning `MBB.getNextNode()` unconditionally:
- After `splitAt()`: `getNextNode()` returns the split-off block
(`ContBB`)
- No split, `MBB` in middle: `getNextNode()` returns the next original
block
- No split, `MBB` was last: `getNextNode()` returns `HaltLoopBB` (just
pushed)
Since we always `push_back(HaltLoopBB)` before returning,
`getNextNode()` can never be `nullptr`: if `MBB` was the last block,
`HaltLoopBB` is now after it.
Fixes: SWDEV-572407