[ThinLTO][MemProf] Support remark emission for thin link and use in MemProf (#182570)
Enable optimization remark emission during the ThinLTO thin link phase.
This is useful for global analysis passes like MemProf context
disambiguation which operate on the summary index and may need to
report diagnostics before any IR modules are available.
Key changes:
- Create a dummy function ("thinlto_remark_dummy") in a private Module
within the LTO class to provide the necessary Function context for
OptimizationRemarkEmitter.
- Update MemProfContextDisambiguation to use a callback for remark
emission, allowing it to report hinted sizes and other diagnostics
during the thin link.
- Ensure the dummy module and function are safely cleaned up at the end
of the LTO session via the LTO::cleanup mechanism.
[RISCV] Remove srl from (srl (and X, (1 << C)), C) used as czero.eqz/nez condition. (#182598)
(setne (and X, 1 << C), 0) is canonicalized to (srl (and X, (1 << C)),
C).
If this is later used as a czero.eqz/nez condition, we can remove
the srl if the and can be represented as an ANDI.
NAS-139921 / 26.0.0-BETA.1 / Fix broken check for locked shares (#18266)
The fast path added for when we have dataset names can set None type for
locked rather than false. This commit ensures that we have boolean
output.
[HLSL] Enable `-Wconversion`, `-Wvector-conversion`, and `-Wmatrix-conversion` warnings for HLSL by default (#182607)
Fixes #180038 by enabling `-Wconversion`, `-Wvector-conversion`, and
`-Wmatrix-conversion` warnings for HLSL by default, both in the HLSL
clang driver and when fixing up clang invocations under HLSL in
CompilerInvocation.cpp (so that they are enabled even with clang -cc1).
This PR also updates existing tests to expect warnings that weren't
expected before, and removes the `-Wconversion` flags from existing HLSL
tests since it is now redundant due to being enabled by default.
Note that no existing HLSL tests use or exercise `-Wvector-conversion`
or `-Wmatrix-conversion`.
[AMDGPU] Use a general form of intrinsic for tensor load/store (#182334)
The intrinsic has five arguments for the tensor descriptor (D#), while the fifth one is reserved for future targets, and it will be silently ignored in codegen for gfx1250.
For tensor up to 2D, only the first two D# groups are meaningful and the rest should be zero-initialized.
libfetch: Gracefully skip unsupported protocols
If socket() fails because the address family or protocol is unsupported,
just continue with the next address.
MFC after: 1 week
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D55407
libfetch: Fail hard if interrupted while connecting
This fixes an issue where the first address that DNS returns is blocked
by a packet filter, so we hang for a while, then the user hits Ctrl-C,
interrupting connect(2), whereupon we move on to the next address, get
a connection, request the file, and return to fetch(1), which sees that
SIGINT was caught and bails.
Note that we make no attempt to enforce fetchTimeout in the connection
phase, and never have. It's feasible, but non-trivial, so we'll leave
it as an exercise for future us.
PR: 293312
MFC after: 1 week
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D55406
libfetch: Clean up fetch_info usage
* Provide a wrapper for the common if (verbose) fetch_info(...) idiom.
* Replace remaining instances of fprintf(stderr, ...) with fetch_info().
* Fix a few style nits.
MFC after: 1 week
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D55405
[Hexagon] Handle subreg copies between DoubleRegs and IntRegs (#181360)
ISel can generate truncating COPYs from DoubleRegs to IntRegs when a
64-bit result (e.g., C2_mask) is used in a 32-bit context. Several
passes crashed on this pattern:
BitTracker asserted WD >= WS for COPY instructions. Handle the WD < WS
case by extracting the low WD bits from the source.
HexagonInstrInfo::copyPhysReg had no case for IntRegs <- DoubleRegs or
DoubleRegs <- IntRegs. Add both directions, respecting the subreg index
on the operand (isub_lo/isub_hi) when present.
HexagonTfrCleanup asserted that source and destination register sizes
match. Replace with proper subreg resolution on both operands and a
hasNoVRegs() guard since the pass runs post-RA.
HexagonGenMux asserted no subregs on physical register operands.
Preserve subreg information when building mux instructions and resolve
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