FreeBSD/ports bb2e093print/hplip distinfo pkg-plist, print/hplip-plugin distinfo

print/hplip(-plugin): Update to 3.26.6
DeltaFile
+35-32print/hplip/files/patch-Makefile.in
+0-9print/hplip/files/patch-installer_pluginhandler.py
+0-9print/hplip/files/patch-fax_backend_hpfax.py
+6-1print/hplip/pkg-plist
+3-3print/hplip/distinfo
+3-3print/hplip-plugin/distinfo
+47-572 files not shown
+50-608 files

LLVM/project df66325llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 lowmaskedlanes.ll

Revert "[DAG] Optimize masked store of constant lane mask to standard store (#223665)" (#224250)

This reverts commit bdb0f5737844a53ae626a0c85aa7ebc593f38626 due to
illegal types undef avx512.
DeltaFile
+9-68llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+36-11llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
+12-15llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll
+10-2llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll
+4-2llvm/test/CodeGen/X86/pr179489.ll
+2-0llvm/test/CodeGen/X86/pr46532.ll
+73-986 files

LLVM/project 9e0686clibcxx/include/__locale_dir time.h num.h, libcxx/include/__locale_dir/support bsd_like.h

[libc++] Move _LIBCPP_GET_C_LOCALE to the locale base API (#222924)

How to retrieve the C locale is fundamentally a property of the
underlying libc, so it should really be part of the locale base API.
DeltaFile
+0-42libcxx/include/__locale_dir/get_c_locale.h
+32-0libcxx/include/__locale_dir/support/default/get_c_locale.h
+7-8libcxx/include/__locale_dir/num.h
+10-0libcxx/include/__locale_dir/support/bsd_like.h
+4-4libcxx/src/locale.cpp
+1-2libcxx/include/__locale_dir/time.h
+54-5610 files not shown
+69-6016 files

FreeBSD/ports 2487abcwww Makefile, www/py-webdavclient3 distinfo pkg-descr

www/py-webdavclient3:  new port

WebDAV client library based on requests, providing a Webdav API
(check, free, info, list, mkdir, clean, copy, move, download,
upload, publish, unpublish) and a higher-level Resource API.
DeltaFile
+28-0www/py-webdavclient3/Makefile
+7-0www/py-webdavclient3/pkg-descr
+3-0www/py-webdavclient3/distinfo
+1-0www/Makefile
+39-04 files

LLVM/project 47f9b70libcxx/include locale, libcxx/include/__locale_dir pad_and_output.h

[libc++] Fix performance regression in std::num_put (#223334)

`__pad_and_output` calls `std::copy` and `std::fill_n` unconditionally,
even though the calls are quite likely to do nothing. Adding conditions
also allows the compiler to do jump-threading.

Fixes #178685
DeltaFile
+89-0libcxx/test/std/localization/locale.categories/category.numeric/locale.nm.put/facet.num.put.members/put_long.pass.cpp
+59-20libcxx/test/benchmarks/text/localization/num_put.bench.cpp
+8-3libcxx/include/__locale_dir/pad_and_output.h
+1-0libcxx/include/locale
+157-234 files

LLVM/project c715ea1llvm/unittests/CodeGen PassManagerTest.cpp, llvm/unittests/ExecutionEngine/Orc RTDyldObjectLinkingLayerTest.cpp

unittests: Compute DataLayout from the triple, not the TargetMachine

Eventually createDataLayout should be removed, so migrate these uses.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+3-3llvm/unittests/ExecutionEngine/Orc/RTDyldObjectLinkingLayerTest.cpp
+2-2llvm/unittests/Target/SPIRV/SPIRVGlobalRegistryTests.cpp
+2-2llvm/unittests/CodeGen/PassManagerTest.cpp
+1-1llvm/unittests/tools/llvm-exegesis/X86/SnippetRepetitorTest.cpp
+1-1llvm/unittests/Target/X86/X86SelectionDAGTest.cpp
+1-1llvm/unittests/Target/X86/MachineSizeOptsTest.cpp
+10-1026 files not shown
+36-3632 files

LLVM/project 6c3604bllvm/test/CodeGen/NVPTX mixed-precision-sub-f32x2-downconvert-invalid.ll mixed-precision-f32x2-sm-version.ll

[NVPTX] Add support for f32x2 mixed-precision add/sub (#221957)

This change adds support for mixed precision addition and 
subtraction of `f16x2` and `bf16x2` with `f32x2`, where the
following upconverting patterns:
```
%e = fpext <2 x half> %h to <2 x float>
%res = fp-operation(%e, ...)
...
%e = fpext <2 x bfloat> %b to <2 x float>
%res = fp-operation(%e, ...)

where the fp-operation can be any of:
- fadd
- fsub
- llvm.nvvm.fadd.v2f32
```
are lowered to `add/sub.{rnd}.f32x2.{f16x2/bf16x2}.f32x2`, and the
following downconverting pattern:

    [22 lines not shown]
DeltaFile
+719-0llvm/test/CodeGen/NVPTX/mixed-precision-add-f32x2-upconvert-invalid.ll
+543-0llvm/test/CodeGen/NVPTX/mixed-precision-add-f32x2-upconvert.ll
+539-0llvm/test/CodeGen/NVPTX/mixed-precision-sub-f32x2-upconvert-invalid.ll
+394-0llvm/test/CodeGen/NVPTX/mixed-precision-sub-f32x2-upconvert.ll
+304-0llvm/test/CodeGen/NVPTX/mixed-precision-f32x2-sm-version.ll
+274-0llvm/test/CodeGen/NVPTX/mixed-precision-sub-f32x2-downconvert-invalid.ll
+2,773-05 files not shown
+3,369-411 files

FreeBSD/ports cf62ebcmultimedia/mkvtoolnix Makefile pkg-plist

multimedia/mkvtoolnix: Update to upstream release 102.0

Details:
Bug- and security fixes, see
https://mkvtoolnix.download/doc/NEWS.md

MFH:            2026Q3
Security:       CVE-2026-90783
(cherry picked from commit ba0bd566e87a7e4044a10f8a4a495c3ec86bcf7b)
DeltaFile
+3-3multimedia/mkvtoolnix/distinfo
+5-0multimedia/mkvtoolnix/pkg-plist
+1-1multimedia/mkvtoolnix/Makefile
+9-43 files

FreeBSD/ports 496178anet/traefik distinfo Makefile

net/traefik: Update to upstream release 3.7.13

Details:
* Bug- and security fixes, see
  https://github.com/traefik/traefik/releases/tag/v3.7.13
* Changes may require updating the configuration, see
  https://doc.traefik.io/traefik/v3.7/migrate/v3/#v3713

MFH:            2026Q3
Security:       https://github.com/traefik/traefik/security/advisories/GHSA-qqjf-53cj-pwvv
                https://github.com/traefik/traefik/security/advisories/GHSA-f52w-8j3h-j724
                https://github.com/traefik/traefik/security/advisories/GHSA-v67p-phpq-fc8x
                https://github.com/traefik/traefik/security/advisories/GHSA-w4v4-9rw7-5326
                https://github.com/traefik/traefik/security/advisories/GHSA-8fcf-v89g-xpg6
(cherry picked from commit 8fb2c0fd0883ce414ccb16202558fba160d35801)
DeltaFile
+3-2net/traefik/Makefile
+3-1net/traefik/distinfo
+6-32 files

FreeBSD/ports 6c06fd7net/rdma-core distinfo

net/rdma-core: Fix distinfo
DeltaFile
+3-3net/rdma-core/distinfo
+3-31 files

OpenBSD/ports RDUAxntwayland/labwc Makefile distinfo, wayland/labwc/pkg PLIST

   wayland/labwc: update to 0.20.2
VersionDeltaFile
1.11+2-2wayland/labwc/distinfo
1.17+1-1wayland/labwc/Makefile
1.9+1-0wayland/labwc/pkg/PLIST
+4-33 files

FreeBSD/src 43347e8sys/arm64/include armreg.h

arm64: Fix definition of CCSIDR_EL1_op0

Fix incorrect opcode on CCSIDR_EL1.

Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>
Reviewed by:    andrew
Sponsored by:   Arm Ltd
Pull Request:   https://github.com/freebsd/freebsd-src/pull/2433
DeltaFile
+1-1sys/arm64/include/armreg.h
+1-11 files

FreeBSD/src 9f24c7dsys/arm64/acpica acpi_iort.c, sys/dev/acpica acpivar.h acpi.c

dev: acpica: Add PCI device methods for aarch64

Add pci_get_id() and pci_alloc_msi() device methods for aarch64 platforms.

Reviewed by:    markj (earlier version), andrew
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D59169
DeltaFile
+60-0sys/arm64/acpica/acpi_iort.c
+39-0sys/dev/acpica/acpi.c
+2-0sys/dev/acpica/acpivar.h
+101-03 files

FreeBSD/src 67242ccsys/arm64/include _armreg.h, sys/arm64/vmm vmm_arm64.c

arm64/vmm: vtimer: Read CNTPCT_EL0 through a dedicated macro

CNTPCT_EL0 needs to be read after an ISB in order to ensure a consistent
value irrespective of speculative execution.

Make existing reads of CNTPCT_EL0 use a new dedicated accessor macro
that expands to the correct instruction sequence.

Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>
Reviewed by:    andrew
Sponsored by:   Arm Ltd
Pull Request:   https://github.com/freebsd/freebsd-src/pull/2423
DeltaFile
+7-7sys/arm64/vmm/io/vtimer.c
+7-0sys/arm64/include/_armreg.h
+1-1sys/arm64/vmm/vmm_arm64.c
+15-83 files

FreeBSD/src 9556306sys/arm/arm gic_acpi.c, sys/arm64/arm64 gicv5.c gicv5_iwb.c

arm64: Add ACPI support to GICv5 driver

Add ACPI support to the GICv5 IRS, ITS and IWB drivers. Device parameters are
derived from the MADT and IORT tables.

Reviewed by:    andrew
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D59171
DeltaFile
+455-0sys/arm64/arm64/gicv5_acpi.c
+138-0sys/arm64/arm64/gicv5_its.c
+93-0sys/arm64/arm64/gicv5_iwb.c
+50-0sys/arm64/arm64/gicv5.c
+3-2sys/conf/files.arm64
+3-0sys/arm/arm/gic_acpi.c
+742-22 files not shown
+745-38 files

LLVM/project 3f8625ellvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/lib/Target/X86 X86ISelLowering.cpp

[DAGCombiner] Narrow the integer source of sint_to_fp

Truncate the source of a `sint_to_fp` when it is known to fit in a narrower
type the target can convert from directly.
For example:
```
    sitofp (sext i32 %x to i64) to float
```
On AMDGPU this becomes a single `v_cvt_f32_i32` instead of the generic
i64 to f32 expansion.

Note: X86 marks i16 sint_to_fp as Custom, but SSE only supports conversion from
i32, so the custom lowering sign-extends i16 back to i32. Mark i16 as
undesirable to avoid a redundant movswl.
DeltaFile
+169-769llvm/test/CodeGen/AMDGPU/int_to_fp_narrow_i64.ll
+29-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+4-4llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+1-0llvm/lib/Target/X86/X86ISelLowering.cpp
+203-7734 files

LLVM/project 8ea2449clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp, clang/test/CIR/Lowering unlowered-address-spaces.cir

[CIR] Reject language address spaces in DirectToLLVM pointer conversion

Reject unlowered language address spaces in pointer types when bypassing TargetLowering. Guard pointer-producing lowerings, including generated patterns, so failed conversions report legalization failures instead of silently selecting address space zero or constructing invalid LLVM operations.

Assisted-by: Codex / GPT-6
DeltaFile
+545-0clang/test/CIR/Lowering/unlowered-address-spaces.cir
+64-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+2-0clang/utils/TableGen/CIRLoweringEmitter.cpp
+611-03 files

LLVM/project 3f9ca80llvm/include/llvm/ExecutionEngine/Orc/Shared Mangler.h, llvm/lib/ExecutionEngine/Orc CMakeLists.txt Mangler.cpp

[ORC] Move Mangler functions into header. (#224209)

Move Mangler functions into Mangler.h so that they can be used from
OrcTargetProcess without introducing a dependence on OrcJIT.

This is a temporary fix to enable use of SymbolNameSpec in
OrcTargetProcess (see https://github.com/llvm/llvm-project/pull/224188).
Future work will reorganize these libraries and should allow this code
to sink back down into a .cpp file.
DeltaFile
+0-53llvm/lib/ExecutionEngine/Orc/Mangler.cpp
+42-2llvm/include/llvm/ExecutionEngine/Orc/Shared/Mangler.h
+0-1llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
+42-563 files

LLVM/project b436b44clang/include/clang/CIR LoweringHelpers.h, clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR] Propagate initializer type adjustment failures

Reject initializers whose active members have no LLVM representation, including when an enclosing union's storage type is convertible. Propagate recursive adjustment failures before querying data layout or constructing LLVM operations.

Assisted-by: Codex / GPT-6
DeltaFile
+66-0clang/test/CIR/Lowering/unsupported-initializer-types.cir
+13-2clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+12-0clang/lib/CIR/Lowering/LoweringHelpers.cpp
+2-1clang/include/clang/CIR/LoweringHelpers.h
+1-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+94-45 files

LLVM/project d3cc1d7clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.h LowerToLLVM.cpp, clang/test/CIR/Lowering unsupported-type-conversions.cir

[CIR] Propagate type conversion failures in DirectToLLVM

Propagate failed type and constant conversions through DirectToLLVM so unsupported types produce legalization failures instead of invalid LLVM operations or a void function result.

Assisted-by: Codex / GPT-6
DeltaFile
+178-0clang/test/CIR/Lowering/unsupported-type-conversions.cir
+49-13clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+4-3clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
+231-163 files

FreeBSD/src e75f619sys/dev/ichiic ig4_reg.h ig4_acpi.c

ig4(4): fix attach of ACPI-enumerated LPSS controllers

Intel LPSS I2C controllers enumerated through ACPI rather than PCI never
attach on Haswell and Broadwell, so every device behind those buses is
lost. On a Dell XPS 13 9343 that hides the I2C HID touchpad and leaves
only the PS/2 fallback, which the firmware does not restore after S3.

Three causes, all on the ACPI path:

Firmware may leave an LPSS function in D3, where its registers read as
all-ones and set_controller() fails with "controller error during
attach-1". Run _PS0 before mapping them. The PCI path does not need
this, which is why the gap went unnoticed.

INT33C2, INT33C3, INT3432 and INT3433 are Lynx Point-LP and Wildcat
Point-LP, which ig4_pci.c already classifies as IG4_HASWELL; the ACPI
path called everything but APMC0D0F an Atom SoC.

The functional clock stays gated until bit 0 of IG4_REG_CLK_PARMS is

    [12 lines not shown]
DeltaFile
+11-0sys/dev/ichiic/ig4_iic.c
+10-0sys/dev/ichiic/ig4_acpi.c
+1-0sys/dev/ichiic/ig4_reg.h
+22-03 files

LLVM/project 1ebf89dllvm/lib/Target/AMDGPU SIRegisterInfo.td MIMGInstructions.td, llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.cpp

[AMDGPU][GFX13] MC support for indexed VIMAGE/VSAMPLE resources (#223429)
DeltaFile
+158-60llvm/lib/Target/AMDGPU/MIMGInstructions.td
+19-0llvm/test/MC/AMDGPU/gfx13_asm_vsample.s
+18-0llvm/test/MC/AMDGPU/gfx13_asm_vimage.s
+12-1llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+7-5llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+9-0llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+223-661 files not shown
+227-677 files

LLVM/project 5ee9be9llvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Analysis/DependenceAnalysis DifferentOffsets.ll MIVCheckConst.ll

[SCEV] Look thru more expressions in isKnownMultipleOf (#219951)

Generalize the existing logic to look through AddRecs to look through
Add, Mul, and MinMax expressions in isKnownMultipleOf, noting that this
simply increases precision of added predicates, allowing us to add more
fine-grained predicates. It also fixes an underlying bug in the case the
AddRec wraps. The patch has no optimization impact at the moment, and
only serves to have higher precision in its sole user,
DependenceAnalysis.

Proof: https://alive2.llvm.org/ce/z/JLCqGJ
DeltaFile
+23-9llvm/lib/Analysis/ScalarEvolution.cpp
+2-4llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
+3-1llvm/test/Analysis/DependenceAnalysis/DifferentOffsets.ll
+28-143 files

FreeNAS/freenas 29abc08src/middlewared/middlewared/api/v27_0_0 pool.py, src/middlewared/middlewared/plugins/zfs resource_processes.py resource.py

Rebase zfs.resource onto GenericCRUDService and a service part

## Problem
When zfs.resource became a CRUD service it was put on a plain `CRUDService`, because `GenericCRUDService` was read as machinery for datastore-backed services. It isn't: `CRUDServicePart` only annotates `_datastore`, and a part whose data doesn't live in the datastore omits it and overrides `query`/`get_instance` instead — which is exactly what `boot.environment` does over the same ZFS-backed, string-keyed shape. What we ended up with was a service carrying its own `get_instance` that called back into its own namespace by string, three `@overload` stubs (and three `# type: ignore` codes) that no in-process caller needed, and a `datastore_primary_key_type` override that nothing in the tree reads.

Separately, `processes` shipped with `check_annotations=True` and a `-> list[dict[str, Any]]` return annotation while its result model declares `list[PoolProcess]`. That check runs when the decorator is applied, so it raises while the class body is being evaluated — on import. `main.py` imports this module, so middlewared could not start. Nothing caught it: no unit test imported the module, and none of the static checks ever create the class.

## Solution
**Base class and config.** `GenericCRUDService[ZFSResourceEntry, str]` with `generic = True`, and the dead `datastore_primary_key_type` override dropped — the PK type comes from `ZFSResourceEntry.id`. That is visible in `core.get_services()["zfs.resource"]["config"]`: `datastore_primary_key_type` now reads `"integer"` (the framework always materialises the key) and `generic` reads `true`. No API method changes shape.

**New `plugins/zfs/resource_part.py`.** `ZFSResourceServicePart` owns `query` and `get_instance`. The sync walk still runs on an IO thread and still delegates into `resource_query.query`, so the threading and the module layout are unchanged.

**`query` and `get_instance` stay hand-declared on the service.** `query` because the inherited one gets wrapped with the stock `QueryArgs`, whose `extra` is a free dict — that would drop the field-by-field schema of `extra` from the docs and from `core.get_methods`, stop rejecting typos, and lose the `Private` guard on `exclude_internal_paths` at the API boundary. `get_instance` because the metaclass injects the concrete `E`/`PK` into whichever module declares `query`; with `query` declared here, the inherited `get_instance` would go looking for them in `crud_service`'s own globals and class creation would fail. `apps`, `apps_images` and `ix_volumes` pair the two overrides for the same reason. The part re-applies the `Private` guard on `extra` explicitly, since the generated args model types it as a plain dict.

**Rows are filtered as dicts and converted afterwards**, rather than built into entry models before `filter_list`. Handing `filter_list` the model changes `select` on the wire: the projected row is built with `model_construct`, which skips validation, so a field the caller didn't select comes back as its default instead of being absent, and a renaming select drops the value outright. Converting after the filter keeps the select behaviour this service already has.

**`processes` builds `PoolProcess` in `resource_processes.processes` and annotates through**, so the annotation agrees with the result model and the module imports again. The rows already carry all four fields, so the wire output is unchanged; what goes away is the `serialize_result` fallback that would otherwise log a warning and emit raw dicts. `PoolProcess` had to be added to the pool API module's `__all__` to be importable from `middlewared.api.current`. A new unit test imports the service module, which is what makes this whole class of failure visible — without it, a `check_annotations` mismatch is only reachable at middlewared startup.
DeltaFile
+58-0src/middlewared/middlewared/plugins/zfs/resource_part.py
+16-38src/middlewared/middlewared/plugins/zfs/resource.py
+25-0src/middlewared/middlewared/pytest/unit/plugins/zfs/test_resource_service.py
+3-3src/middlewared/middlewared/plugins/zfs/resource_processes.py
+2-1src/middlewared/middlewared/api/v27_0_0/pool.py
+104-425 files

LLVM/project 5781d4bllvm/lib/Support UnicodeCaseFold.cpp, llvm/utils unicode-case-fold.py

[llvm] Updates case folding rules to Unicode 18 (#223716)

This PR updates other Unicode tables started by
https://github.com/llvm/llvm-project/pull/198255

Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+63-8llvm/lib/Support/UnicodeCaseFold.cpp
+27-22llvm/utils/unicode-case-fold.py
+3-3llvm/utils/UnicodeData/UnicodeNameMappingGenerator.cpp
+93-333 files

LLVM/project 7232f3blld/test/ELF arm-thunk-overlay-reuse.s aarch64-thunk-bti-overlay-reuse.s

[LLD][ELF] Reduce memory and file size of overlay thunk tests (#222565)

Add AT(address) to linker script to force generation of a program header
for each address. Without AT we get a single large program header that
takes up a large amount of memory and causes a large file to be
generated. This may prevent the test from running on a 32-bit machine
without a lot of memory. See comment on #200415

Also removed a superfluous --print-map from
aarch64-thunk-bit-overlay-reuse.s. This was used when constructing the
test but it is not needed.
DeltaFile
+3-3lld/test/ELF/aarch64-thunk-bti-overlay-reuse.s
+2-2lld/test/ELF/arm-thunk-overlay-reuse.s
+5-52 files

FreeBSD/src b9cee18share/man/man4 ice.4, sys/conf NOTES

ice: Add a failure injection facility

Add compile-time optional, non-sleeping fail points around every VF
creation resource boundary, before VF VSI reconstruction, and in the
GET_STATS validation path.

Provide an ICE-wide wrapper and device selector so other driver
subsystems can add scoped points without duplicating the failpoint
plumbing.  Keep the current SR-IOV points and VF selector in an iov
child namespace.

Compile the facility only with options DRIVER_FAILPOINTS.  This shared
option avoids a separate kernel option for every driver that provides
test-only injection hooks.  Ordinary kernels contain no ICE failpoint
objects or sysctl nodes.  Require an exact PF device name and
optionally a VF index before any point can fire.  This prevents a stale
test setting from affecting another PF.

The hooks exposed two reset-lifetime defects while validating the

    [13 lines not shown]
DeltaFile
+71-0sys/dev/ice/ice_iov.c
+44-2share/man/man4/ice.4
+37-0sys/dev/ice/ice_fault.h
+28-0sys/dev/ice/ice_lib.c
+7-0sys/conf/NOTES
+1-0sys/modules/ice/Makefile
+188-22 files not shown
+190-28 files

LLVM/project 9a3d449flang/test/Driver fno-optimize-sibling-calls.f90, flang/test/Transforms function-attr-disable-tail-calls.fir

[Flang][Driver]Implemented the support for option -f[no-]optimize-sibling-calls in Flang (#216650)

Added support for -foptimize-sibling-calls and
-fno-optimize-sibling-calls in Flang.

- Sibling call optimization is on by default and the driver pass the
option `-f[no-]optimize-sibling-calls` to flang -fc1.
- When `-fno-optimize-sibling-calls` flag is passed, it sets boolen
`DisableTailCalls` and this results in adding the LLVM IR attribute
`"disable-tail-calls"="true"` which disables sibling call optimization.
DeltaFile
+16-0mlir/test/Target/LLVMIR/Import/disable-tail-calls.ll
+14-0mlir/test/Target/LLVMIR/disable-tail-calls.mlir
+11-0mlir/lib/Target/LLVMIR/ModuleImport.cpp
+11-0flang/test/Driver/fno-optimize-sibling-calls.f90
+11-0flang/test/Transforms/function-attr-disable-tail-calls.fir
+7-0mlir/test/Target/LLVMIR/Import/import-failure.ll
+70-010 files not shown
+102-516 files

LLVM/project 3d6cd38llvm/lib/Target/AMDGPU VOP3PInstructions.td VOPCInstructions.td

[AMDGPU] Set Format/FormatModifier directly instead of per-flag bits, NFC.

Remove the now-redundant individual InstSI format flag fields (SOP1/2/C/K/P,
VOP1/2/C/VOP3/VINTRP/VOPD3/LDSDIR, the memory formats, Spill, and DPP/SDWA) and
have instruction classes set the Format / FormatModifier enum fields directly.
The enum fields are packed into TSFlags exactly as before, so this is NFC (the
full instruction table is byte-identical).

Real instructions copy Format/FormatModifier from their pseudo in the base real
classes (kept next to the existing TSFlags copy), so the Format field is now
correct on real instructions too.

Two derived helper bits (IsVOP3Encoding, VOPD3) are computed from Format for the
getVOPe32/getVOPe64 relation maps and the VOPDPairs searchable table; they are
not part of TSFlags.

Co-Authored-By: Claude <noreply at anthropic.com>
DeltaFile
+21-73llvm/lib/Target/AMDGPU/SIInstrFormats.td
+21-17llvm/lib/Target/AMDGPU/VOPInstructions.td
+15-10llvm/lib/Target/AMDGPU/SOPInstructions.td
+11-11llvm/lib/Target/AMDGPU/SIInstructions.td
+9-8llvm/lib/Target/AMDGPU/VOPCInstructions.td
+7-7llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+84-12612 files not shown
+123-15818 files

LLVM/project 7d61d88llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIDefines.h, llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp

[AMDGPU] Decouple isVOP3P/isVINTERP from isVOP3 (#223448)

VOP3P and VINTERP instructions also set the VOP3 TSFlags bit, so isVOP3()
returned true for them. This overloaded isVOP3() to mean both "the VOP3
encoding" and "uses VOP3-style operand rules" (modifiers, constant bus,
literal legality).

Make VOP3P and VINTERP their own instruction-format enum values so
isVOP3() is strict (Format == VOP3). Callers that need "any VOP3-family
operand encoding" now use isVOP3Like() (VOP3 | VOP3P | VINTERP), added as
a SIInstrInfo wrapper. Redundant "isVOP3() && !isVOP3P()" tests are
simplified to isVOP3().

Resolves llvm/llvm-project#223448.

Co-Authored-By: Claude <noreply at anthropic.com>
DeltaFile
+19-17llvm/lib/Target/AMDGPU/SIInstrFormats.td
+12-13llvm/lib/Target/AMDGPU/SIDefines.h
+7-6llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+5-6llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+2-2llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+2-2llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+47-465 files not shown
+53-5211 files