FreeNAS/freenas df4d70esrc/middlewared/middlewared role.py, src/middlewared_docs/docs rbac.rst

NAS-140484 / 27.0.0-BETA.1 / Improve RBAC docs (#18594)

Address feedback from other teams:
* Improve phrasing for the individual vs compound roles
* Add table with list of current roles
DeltaFile
+189-22src/middlewared_docs/docs/rbac.rst
+2-0src/middlewared/middlewared/role.py
+191-222 files

FreeBSD/ports 3308817textproc/difftastic distinfo Makefile

textproc/difftastic: update 0.67.0 → 0.68.0
DeltaFile
+43-39textproc/difftastic/distinfo
+21-20textproc/difftastic/Makefile
+64-592 files

FreeBSD/ports 3a5b9bfgames/devilutionX distinfo Makefile

games/devilutionX: update 1.5.4 → 1.5.5
DeltaFile
+15-15games/devilutionX/distinfo
+7-8games/devilutionX/Makefile
+22-232 files

FreeBSD/ports 2377f9egames/pioneer distinfo Makefile

games/pioneer: update 2025050120260203
DeltaFile
+3-3games/pioneer/distinfo
+1-2games/pioneer/Makefile
+4-52 files

FreeNAS/freenas 1a7bc8asrc/middlewared/middlewared/plugins/container image.py

fix querying container images
DeltaFile
+13-10src/middlewared/middlewared/plugins/container/image.py
+13-101 files

FreeNAS/freenas 6f1af82src/middlewared/middlewared/plugins/container bridge.py

NAS-140441 / 26.0.0-BETA.2 / fix containers default network (by yocalebo) (#18598)

The auto-managed container bridge (truenasbr0) had two bugs preventing
containers from getting network access.

Bug 1: Wrong IP address assigned to bridge

_bridge_impl() in bridge.py assigned the network address (.0) to the
bridge instead of the first host address (.1):

Before (bug): assigns 172.200.0.0 to bridge
  add_address(sock, ip4.ip.exploded, ...)

After (fix): assigns 172.200.0.1 to bridge
  add_address(sock, ip4.network[1].exploded, ...)

The bridge got 172.200.0.0/24 but dnsmasq was told
--listen-address=172.200.0.1. Since ip_nonlocal_bind=1 is enabled
system-wide, dnsmasq could bind to the non-existent .1 address via

    [30 lines not shown]
DeltaFile
+8-3src/middlewared/middlewared/plugins/container/bridge.py
+8-31 files

FreeNAS/freenas 6ccc447src/middlewared/middlewared/plugins/container bridge.py

NAS-140441 / 26.0.0-BETA.1 / fix containers default network (by yocalebo) (#18597)

The auto-managed container bridge (truenasbr0) had two bugs preventing
containers from getting network access.

Bug 1: Wrong IP address assigned to bridge

_bridge_impl() in bridge.py assigned the network address (.0) to the
bridge instead of the first host address (.1):

Before (bug): assigns 172.200.0.0 to bridge
  add_address(sock, ip4.ip.exploded, ...)

After (fix): assigns 172.200.0.1 to bridge
  add_address(sock, ip4.network[1].exploded, ...)

The bridge got 172.200.0.0/24 but dnsmasq was told
--listen-address=172.200.0.1. Since ip_nonlocal_bind=1 is enabled
system-wide, dnsmasq could bind to the non-existent .1 address via

    [30 lines not shown]
DeltaFile
+8-3src/middlewared/middlewared/plugins/container/bridge.py
+8-31 files

FreeNAS/freenas 9c1fe0bsrc/middlewared/middlewared/plugins/container bridge.py

NAS-140441 / 27.0.0-BETA.1 / fix containers default network (#18596)

The auto-managed container bridge (truenasbr0) had two bugs preventing
containers from getting network access.

Bug 1: Wrong IP address assigned to bridge

_bridge_impl() in bridge.py assigned the network address (.0) to the
bridge instead of the first host address (.1):

Before (bug): assigns 172.200.0.0 to bridge
  add_address(sock, ip4.ip.exploded, ...)

After (fix): assigns 172.200.0.1 to bridge
  add_address(sock, ip4.network[1].exploded, ...)

The bridge got 172.200.0.0/24 but dnsmasq was told
--listen-address=172.200.0.1. Since ip_nonlocal_bind=1 is enabled
system-wide, dnsmasq could bind to the non-existent .1 address via

    [26 lines not shown]
DeltaFile
+8-3src/middlewared/middlewared/plugins/container/bridge.py
+8-31 files

LLVM/project 1f7a67fllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 fma-conversion-multi-use-guard.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+6-14llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
+16-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+22-142 files

LLVM/project b66d98alldb/examples/python formatter_bytecode.py, lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode RigidArrayLLDBFormatterSwift.txt

[lldb][bytecode] Improvements to compiler generated Swift (#189425)

Following feedback from @benrimmington in
https://github.com/apple/swift-collections/pull/607, this changes the
following:

1. Uses `objectFormat()` compiler conditional instead of `os()` (see
"Cross-platform object file format support" in
[SE-0492](https://github.com/swiftlang/swift-evolution/blob/main/proposals/0492-section-control.md#cross-platform-object-file-format-support))
2. Uses a raw identifier for the generated Swift symbol name, instead of
an escaped name (see
[SE-0451](https://github.com/swiftlang/swift-evolution/blob/main/proposals/0451-escaped-identifiers.md))
DeltaFile
+4-8lldb/examples/python/formatter_bytecode.py
+2-2lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterSwift.txt
+6-102 files

LLVM/project 67c3429mlir/docs Interfaces.md, mlir/docs/Tools mlir-reduce.md

[mlir][docs] dialect interfaces and mlir reduce documentation fix (#189258)

Two modifications:

1. Reflect newly added dialect interface methods in the documentation
2. Remove the bug in the `MLIR Reduce` documentation
DeltaFile
+24-2mlir/docs/Interfaces.md
+3-0mlir/docs/Tools/mlir-reduce.md
+27-22 files

LLVM/project e891812llvm/lib/CodeGen ExpandVectorPredication.cpp, llvm/lib/Target/RISCV RISCVISelLowering.cpp

[RISCV] Remove codegen for vp_minimum, vp_maximum (#189550)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off two intrinsics from #179622.
DeltaFile
+462-654llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
+462-654llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
+221-269llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
+221-269llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
+3-22llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+3-1llvm/lib/CodeGen/ExpandVectorPredication.cpp
+1,372-1,8691 files not shown
+1,372-1,8717 files

FreeBSD/ports 01f16cemath/octave-forge-fxp Makefile, math/octave-forge-fxp/files patch-DESCRIPTION

math/octave-forge-fxp: Bug fix.

- Fix version number in DESCRIPTION.
- Bump portrevision.
DeltaFile
+9-0math/octave-forge-fxp/files/patch-DESCRIPTION
+2-0math/octave-forge-fxp/Makefile
+11-02 files

LLVM/project 38c0f53llvm/test/Transforms/SLPVectorizer/AArch64 fma-conversion-multi-use-guard.ll

[SLP][NFC] Add a test for incorrect fma-conversion for fmuls with multi uses
DeltaFile
+153-0llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
+153-01 files

LLVM/project ff4e229llvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV riscv-vector-reverse.ll tail-folding-reverse-load-store.ll

Revert "[VPlan] Extract reverse mask from reverse accesses" (#189637)

Reverts llvm/llvm-project#155579

Assertion added triggers on some buildbots
clang:
/home/tcwg-buildbot/worker/clang-aarch64-sve2-vla/llvm/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp:3840:
virtual InstructionCost
llvm::VPWidenMemoryRecipe::computeCost(ElementCount, VPCostContext &)
const: Assertion `!IsReverse() && "Inconsecutive memory access should
not have reverse order"' failed.
PLEASE submit a bug report to
https://github.com/llvm/llvm-project/issues/ and include the crash
backtrace, preprocessed source, and associated run script.
Stack dump:
0. Program arguments:
/home/tcwg-buildbot/worker/clang-aarch64-sve2-vla/stage1.install/bin/clang
-DNDEBUG -mcpu=neoverse-v2 -mllvm -scalable-vectorization=preferred -O3
-std=gnu17 -fcommon -Wno-error=incompatible-pointer-types -MD -MT

    [3 lines not shown]
DeltaFile
+42-50llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+30-34llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+27-12llvm/lib/Transforms/Vectorize/VPlan.h
+21-18llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+8-8llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
+8-6llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
+136-1288 files not shown
+160-14914 files

LLVM/project 09c54a8mlir/include/mlir/Dialect/SPIRV/IR TargetAndABI.h, mlir/lib/Conversion/SCFToSPIRV SCFToSPIRV.cpp

[mlir][SPIR-V] Support spirv.loop_control attribute on scf.for and scf.while (#189392)

Propagate the `spirv.loop_control` attribute from `scf.for` and
`scf.while` operations to the generated `spirv.mlir.loop` during
SCFToSPIRV conversion
DeltaFile
+26-0mlir/test/Conversion/SCFToSPIRV/for.mlir
+17-0mlir/test/Conversion/SCFToSPIRV/while.mlir
+11-4mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp
+4-0mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
+3-0mlir/include/mlir/Dialect/SPIRV/IR/TargetAndABI.h
+2-0mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
+63-46 files

NetBSD/pkgsrc etBJQiLlang/ruby rubyversion.mk

   lang/ruby: fix build problem of ruby34

   Fix build problem of ruby34, correcting version of pstore gem.
VersionDeltaFile
1.317+2-2lang/ruby/rubyversion.mk
+2-21 files

OpenBSD/src vehNZ7ssys/dev/fdt xhci_fdt.c

   Attempt to power on attached USB hubs.  Add support for SpacemiT K1.

   ok phessler@, jca@, jsing@
VersionDeltaFile
1.27+19-3sys/dev/fdt/xhci_fdt.c
+19-31 files

NetBSD/pkgsrc 0wUwHBFdoc CHANGES-pkgsrc-2026Q1

   doc: update for tickets 7058, 7060-7066
VersionDeltaFile
1.1.2.3+55-1doc/CHANGES-pkgsrc-2026Q1
+55-11 files

OpenBSD/src YWkFpNVsys/arch/riscv64/riscv64 cpu.c

   Recognize SpacemiT X60 and X100 cores.

   ok jsg@
VersionDeltaFile
1.22+13-1sys/arch/riscv64/riscv64/cpu.c
+13-11 files

LLVM/project 2c5af14llvm/test/CodeGen/WebAssembly strided-int-mac.ll

[NFC][WebAssembly] More codegen tests (#189671)
DeltaFile
+235-0llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+235-01 files

NetBSD/pkgsrc 18J6k2zmail/roundcube distinfo Makefile.common, mail/roundcube-plugin-password distinfo

   Pullup ticket #7066 - requested by taca
   mail/roundcube-plugin-password: Security fix
   mail/roundcube: Security fix

   Revisions pulled up:
   - mail/roundcube-plugin-password/distinfo                       1.45
   - mail/roundcube/Makefile                                       1.103
   - mail/roundcube/Makefile.common                                1.43
   - mail/roundcube/distinfo                                       1.99

   ---
      Module Name:      pkgsrc
      Committed By:     taca
      Date:             Sun Mar 29 14:31:59 UTC 2026

      Modified Files:
        pkgsrc/mail/roundcube: Makefile Makefile.common distinfo
        pkgsrc/mail/roundcube-plugin-password: distinfo


    [21 lines not shown]
VersionDeltaFile
1.98.2.1+4-4mail/roundcube/distinfo
1.44.2.1+4-4mail/roundcube-plugin-password/distinfo
1.42.2.1+2-2mail/roundcube/Makefile.common
1.102.2.1+1-2mail/roundcube/Makefile
+11-124 files

FreeNAS/freenas fc2d008src/middlewared/middlewared/plugins keychain.py

update `keychaincredential.update` doc
DeltaFile
+1-1src/middlewared/middlewared/plugins/keychain.py
+1-11 files

FreeBSD/ports 4b86e22sysutils/hcloud distinfo Makefile

sysutils/hcloud: Update to 1.62.0

Changelog: https://github.com/hetznercloud/cli/releases/tag/v1.62.0
DeltaFile
+5-5sysutils/hcloud/distinfo
+1-2sysutils/hcloud/Makefile
+6-72 files

LLVM/project bb55c4bclang/include/clang/CIR/Dialect/IR CIRTypes.td, clang/lib/CIR/CodeGen CIRGenExprConstant.cpp

[CIR] Implement member-pointer members lowering/CXX ABI lowering (#187327)

Record types with a member pointer as a member require quite a bit of
work to get to function properly. First, we have to wire them through
the AST->CIR lowering to make sure we properly represent them, and
represent them when they're zero initializable. We also have to properly
initialize elements when we're NOT zero initializable.

More importantly, we have to implement the CXXABILowering of record
types. Before this patch, we just assumed that all RecordTypes were
legal, since we didn't have the above lowering. A vast majority of this
patch is around getting RecordTypes to lower properly. There isn't
really a good way to test this without the FE changes, so it wasn't
split off.

We accomplish this in 2 phases: First, we transform each individual
record type along the way, giving it a new cxx-abi specific name. We
have to ensure that recursive evaluation works correctly, so we pulled
the solution from the LLVM-IR dialect for that. Secondly, we rename all

    [13 lines not shown]
DeltaFile
+482-48clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
+88-0clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
+79-5clang/test/CIR/CodeGen/nonzeroinit-struct.cpp
+24-5clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+6-21clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+21-1clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+700-808 files not shown
+766-8614 files

HardenedBSD/ports 28e36afsecurity/nmap Makefile

HBSD: Resolave merge conflict

HardenedBSD does not support FreeBSD 13.

Signed-off-by:  Shawn Webb <shawn.webb at hardenedbsd.org>
DeltaFile
+0-4security/nmap/Makefile
+0-41 files

NetBSD/src rrGl6q1sys/uvm uvm_swap.c

   swread/swwrite: update a comment about swapdev stability

   https://gnats.netbsd.org/60147
   PR/60147
VersionDeltaFile
1.231+2-1sys/uvm/uvm_swap.c
+2-11 files

HardenedBSD/ports 1b1457cmath/heyoka pkg-plist, math/heyoka/files patch-test_llvm_helpers.cpp

Merge remote-tracking branch 'origin/freebsd/main' into hardenedbsd/main

Conflicts:
        security/nmap/Makefile (unresolved)
DeltaFile
+195-187sysutils/tldr/distinfo
+96-92sysutils/tldr/Makefile.crates
+33-33www/py-primp/distinfo
+28-28misc/github-copilot-cli/files/package-lock.json
+43-0math/heyoka/files/patch-test_llvm_helpers.cpp
+33-7math/heyoka/pkg-plist
+428-347177 files not shown
+1,245-1,043183 files

FreeNAS/freenas 57f01f2src/middlewared/middlewared/plugins/crypto_ renew_certs.py

accept the new org name in `renew_certs`
DeltaFile
+9-7src/middlewared/middlewared/plugins/crypto_/renew_certs.py
+9-71 files

LLVM/project 9d7b075llvm/lib/Target/AArch64 AArch64InstrFormats.td, llvm/test/MC/AArch64 armv9.6a-pcdphint.s

[AArch64][llvm] Fix encoding for `stshh` instruction (#189588)

The encoding for `stshh` was incorrect, and has been fixed. This
has been checked against the Arm ARM.
DeltaFile
+4-4llvm/test/MC/AArch64/armv9.6a-pcdphint.s
+1-1llvm/lib/Target/AArch64/AArch64InstrFormats.td
+5-52 files