GhostBSD/networkmgr bc51e9f — NetworkMgr query.py configuration.py

Merge pull request #129 from ghostbsd/validate-config-entries

Validate configuration window entries before writing them
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+218-0NetworkMgr/validate.py
+150-27NetworkMgr/configuration.py
+5-2NetworkMgr/query.py
+373-293 files

LLVM/project eb81f81 — llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes LoadStoreVec.h

[SandboxVec][LoadStoreVec] Support constant vectors of mixed types
DeltaFile
+109-27llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_mixed_types.ll
+42-23llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+24-24llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
+7-36llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+16-0llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
+0-5llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
+198-1152 files not shown
+202-1198 files

LLVM/project 0f85ccd — llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes LoadStoreVec.h

[SandboxVec][LoadStoreVec] Support constant vectors of mixed types

createConstantVector() previously packed the constant store operands
as-is, which only worked when every store had the same element type.
Take the lane type from VecUtils::getCombinedVectorTypeFor() instead and
reinterpret each constant's bits as that type, going through an integer
of matching width via ptrtoint/inttoptr/bitcast. Constants wider than a
lane (e.g. an i64 in an <N x i32>) are split across several lanes in
memory order. Bail out when a constant cannot be reinterpreted, such as
a non-integral pointer or a relocatable address that needs splitting.

Also flatten vector-typed ConstantPointerNull into per-lane nulls, and
bail out on the remaining vector constants such as poison rather than
packing them into the result.

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+383-0llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_mixed_types.ll
+100-13llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+18-0llvm/lib/SandboxIR/Constant.cpp
+11-2llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+12-0llvm/unittests/SandboxIR/SandboxIRTest.cpp
+11-0llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
+535-153 files not shown
+541-169 files

LLVM/project 81f7e67 — llvm/test/Transforms/LoopVectorize alloca-in-loop.ll

[LV] Add tests showing alloca miscompiles. (#229911)

Tests for https://github.com/llvm/llvm-project/issues/229389.
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+178-0llvm/test/Transforms/LoopVectorize/alloca-in-loop.ll
+178-01 files

LLVM/project 73944be — llvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[OpenMP][OMPIRBuilder] Allow multi-block bodies in createIteratorLoop

createIteratorLoop requires the body generator to leave a single block that
falls through or branches to the loop latch. A body generator that lowers
expressions with their own control flow cannot meet that requirement. The
upcoming user is omp.iterator translation, once its region can contain
several blocks (#227454).

Allow the body to span several blocks. If exactly one block is left without
a terminator, it is branched to the latch; otherwise some block must already
branch there. Bodies that leave more than one block unterminated, or that
branch out of the loop, are rejected with an error.

Assisted with Copilot and Claude Opus 5.
DeltaFile
+160-1llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+42-12llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+7-4llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+209-173 files

LLVM/project 1302f02 — llvm/lib/Transforms/InstCombine InstCombineCasts.cpp, llvm/test/Transforms/InstCombine/AArch64 lshr-trunc-sext-to-ashr-sext.ll

[InstCombine] Move sext(trunc(lshr(...))) combine before same type combine

The same type sext(trunc(...)) combine will fire on the lshr case, but the lshr produces one less shift. Move it afterwards to give the lshr combine a chance to fire first. Fixes the motivating x264 case
DeltaFile
+7-7llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+2-3llvm/test/Transforms/InstCombine/X86/lshr-trunc-sext-to-ashr-sext.ll
+2-3llvm/test/Transforms/InstCombine/RISCV/lshr-trunc-sext-to-ashr-sext.ll
+2-3llvm/test/Transforms/InstCombine/AArch64/lshr-trunc-sext-to-ashr-sext.ll
+13-164 files

LLVM/project 31d2f8d — llvm/lib/Transforms/InstCombine InstCombineCasts.cpp, llvm/test/Transforms/InstCombine/AArch64 lshr-trunc-sext-to-ashr-sext.ll

[InstCombine] Move sext(trunc(...)) combines before EvaluateInDifferentType
DeltaFile
+31-31llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+2-4llvm/test/Transforms/InstCombine/X86/lshr-trunc-sext-to-ashr-sext.ll
+2-4llvm/test/Transforms/InstCombine/RISCV/lshr-trunc-sext-to-ashr-sext.ll
+2-4llvm/test/Transforms/InstCombine/AArch64/lshr-trunc-sext-to-ashr-sext.ll
+37-434 files

LLVM/project 822f165 — llvm/test/Transforms/InstCombine/AArch64 lshr-trunc-sext-to-ashr-sext.ll, llvm/test/Transforms/InstCombine/RISCV lshr-trunc-sext-to-ashr-sext.ll

Precommit tests
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+34-0llvm/test/Transforms/InstCombine/AArch64/lshr-trunc-sext-to-ashr-sext.ll
+34-0llvm/test/Transforms/InstCombine/X86/lshr-trunc-sext-to-ashr-sext.ll
+34-0llvm/test/Transforms/InstCombine/RISCV/lshr-trunc-sext-to-ashr-sext.ll
+102-03 files

LLVM/project 55e6ae6 — llvm/lib/Transforms/InstCombine InstCombineCasts.cpp, llvm/test/Transforms/InstCombine lshr-trunc-sext-to-ashr-sext.ll

[InstCombine] Generalize sext (trunc (lshr Y, C)) -> sext/trunc (ashr Y, C) to other shift amounts
DeltaFile
+8-4llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+1-2llvm/test/Transforms/InstCombine/lshr-trunc-sext-to-ashr-sext.ll
+9-62 files

LLVM/project e59541d — llvm/test/Transforms/InstCombine lshr-trunc-sext-to-ashr-sext.ll

Precommit tests
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+52-0llvm/test/Transforms/InstCombine/lshr-trunc-sext-to-ashr-sext.ll
+52-01 files

LLVM/project 5bd7bb9 — llvm/lib/Transforms/InstCombine InstCombineCasts.cpp

Skip ComputeNumSignBits when C == TruncatedBits for compile time
DeltaFile
+2-1llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+2-11 files

LLVM/project 2102e5e — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

remove setters from CandidateState
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+14-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+14-21 files

LLVM/project 6355224 — lld/MachO Driver.cpp SyntheticSections.cpp, lld/MachO/Arch ARM64.cpp

[lld][MachO] Support Objective-C class selector stubs

Support Objective-C class selector stubs in lld's Mach-O backend.

This consumes the class-stub symbols emitted by Clang in [ObjC] Emit class
msgSend stub calls (#186433), using the form
`_objc_msgSendClass$<selector>$_OBJC_CLASS_$_<class>`.

Class stubs load the class object into `x0`, load the selector into `x1`, and
branch to `_objc_msgSend`. Local class symbols are materialized directly with
`adrp`/`add`; dylib or dynamic class symbols are loaded indirectly.

The implementation also tracks the resolved class symbol before dead stripping
so live class stubs can retain the needed class definition without keeping dead
dylib references alive.
DeltaFile
+369-0lld/test/MachO/arm64-objc-class-stubs.s
+110-15lld/MachO/SyntheticSections.cpp
+85-0lld/MachO/Arch/ARM64.cpp
+82-0lld/test/MachO/arm64-objc-class-stubs-dead.s
+46-0lld/test/MachO/objc-class-stubs-unsupported.s
+34-6lld/MachO/Driver.cpp
+726-214 files not shown
+762-2210 files

LLVM/project 66a38a5 — llvm/docs RISCVUsage.md, llvm/lib/Target/RISCV RISCVMachineFunctionInfo.h RISCVMachineFunctionInfo.cpp

[RISCV] Ensure Shadow Stack checks correct RA (#226309)

This primarliy applies to the save-restore case, which was using
`__riscv_restore_<N>` incorrectly, entirely circumventing the software
shadow call stack.

This fix keeps the code size improvements of `__riscv_save_<N>` when
there is a shadow call stack, but it avoids the incorrect use of
`__riscv_restore_<N>`, instead emitting the correct sequence inline.

In the future, when there are better versions of `__riscv_save_<N>` and
`__riscv_restore_<N>` which support the shadow call stack variants (both
hardware and software), then we can revisit this approach and use the
correct pairs in all cases.
DeltaFile
+1,871-0llvm/test/CodeGen/RISCV/shadow-stack-frame-opts.ll
+66-37llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+18-0llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
+8-7llvm/test/CodeGen/RISCV/saverestore-scs.ll
+7-0llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
+4-0llvm/docs/RISCVUsage.md
+1,974-446 files

LLVM/project 056605c — llvm/lib/CodeGen WasmEHPrepare.cpp, llvm/lib/Target/WebAssembly WebAssemblyCFGStackify.cpp WebAssemblyTargetMachine.cpp

Revert "Fall back to the TargetOptions exception model"

This reverts commit f34f3b4742934142115022fc320faa856798d20f.
DeltaFile
+9-21llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
+0-28llvm/test/CodeGen/WebAssembly/exception-model.ll
+6-16llvm/lib/CodeGen/WasmEHPrepare.cpp
+6-9llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+6-9llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+3-7llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
+30-906 files not shown
+40-12612 files

LLVM/project 4a1b39a — llvm/lib/Target/WebAssembly WebAssemblyTargetMachine.cpp WebAssemblyCodeGenPassBuilder.cpp, llvm/test/CodeGen/WebAssembly wasm-eh-prepare-exception-model.ll exception-model.ll

WebAssembly: Take the exception model from the module flag

The WebAssembly EH passes chose whether and how to run from
MCAsmInfo::getExceptionHandlingType() and TargetOptions::ExceptionModel,
A module that asked for Wasm EH through the module flag alone would have
its invokes rewritten by LowerInvoke before WasmEHPrepare ran.

Schedule the passes unconditionally and read the module flag inside the
passes instead. Passes for other models can noop on the models they are
not intended for.

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+133-0llvm/test/Transforms/LowerInvoke/respect-exception-model-flag.ll
+93-0llvm/test/CodeGen/WebAssembly/exception-model.ll
+60-0llvm/test/CodeGen/WebAssembly/wasm-eh-prepare-exception-model.ll
+8-20llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+10-18llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
+7-14llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+311-528 files not shown
+345-7914 files

LLVM/project d4b6565 — llvm/lib/CodeGen WasmEHPrepare.cpp, llvm/lib/Target/WebAssembly WebAssemblyCFGStackify.cpp WebAssemblyTargetMachine.cpp

Fall back to the TargetOptions exception model

Staging change to keep tests working until the full removal
DeltaFile
+21-9llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
+28-0llvm/test/CodeGen/WebAssembly/exception-model.ll
+16-6llvm/lib/CodeGen/WasmEHPrepare.cpp
+9-6llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+9-6llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+7-3llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
+90-306 files not shown
+126-4012 files

LLVM/project d3560b4 — llvm/test/CodeGen/AMDGPU usubo.ll sdwa-peephole.ll

AMDGPU: Stop relying on -amdgpu-scalarize-global-loads=false in ALU tests

Convert kernels which loaded operands from pointer arguments into
functions taking the operands as arguments. Scalar kernel arguments become
inreg arguments. Where a kernel is still useful, index the loads by the
workitem id so they remain vector loads. This also fixes a few tests where
the workitem id index was computed but unused, or where the uniform
workgroup id was used for indexing in VALU tests.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+14,421-15,276llvm/test/CodeGen/AMDGPU/frem.ll
+1,502-5,317llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+300-1,371llvm/test/CodeGen/AMDGPU/fma-combine.ll
+290-936llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
+275-670llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
+291-292llvm/test/CodeGen/AMDGPU/usubo.ll
+17,079-23,86222 files not shown
+18,647-27,38528 files

LLVM/project 67b0858 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

remove CandidateState getters
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+48-131llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+48-1311 files

LLVM/project f232777 — llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes LoadStoreVec.h

[SandboxVec][LoadStoreVec] Support constant vectors of mixed types
DeltaFile
+5-3llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+0-5llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
+2-1llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+1-1llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_mixed_types.ll
+8-104 files

LLVM/project e7c6ffc — llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes LoadStoreVec.cpp, llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec load_store_vec.ll load_store_vec_mixed_types.ll

Remove bit count and only collect constants
DeltaFile
+17-17llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_mixed_types.ll
+11-13llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+2-2llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec.ll
+2-2llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/AMDGPU/basic.ll
+32-344 files

LLVM/project b2ef26c — llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer VecUtils.cpp

Move getCombinedVectorTypeFor
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+7-38llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+18-13llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
+16-0llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
+4-4llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+45-554 files

LLVM/project 91e3226 —

[CIR][CodeGen][NFC] Share isEmptyFieldForLayout and isEmptyRecordForLayout (#223424)

Deduplicates `isEmptyFieldForLayout` and `isEmptyRecordForLayout` between CIR
and classic CodeGen into a new `RecordLayoutUtils.h`. The 25 callers now name
them as `CodeGenUtils::isEmptyFieldForLayout` and
`CodeGenUtils::isEmptyRecordForLayout`, like the other shared helpers.

Assisted-by: Claude Code (Claude Fable 5.1).
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+0-00 files

LLVM/project 663b88c — llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes LoadStoreVec.cpp, llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec load_store_vec_mixed_types.ll

Handle undef/poison
DeltaFile
+93-11llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_mixed_types.ll
+18-23llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
+27-7llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+138-413 files

LLVM/project 306ecdd —

[alpha.webkit.NoDeleteChecker] Handle CXXStdInitializerListExpr in trivial analysis (#224723)

TrivialFunctionAnalysisVisitor had no handler for
CXXStdInitializerListExpr, so a braced list bound to a
std::initializer_list fell through to VisitStmt and was conservatively
treated as non-trivial. This made any nodelete function containing e.g.
std::min({a, b, c}) report that it "contains code that could destruct an
object".

The backing array of a std::initializer_list is a temporary whose
lifetime ends in the enclosing function, so its elements really are
destructed there. Accept the node when the array's element type is
trivially destructible and recurse into the initializers, and keep
rejecting it otherwise.
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+0-00 files

LLVM/project 3d43396 —

[SLP]Vectorize aggregates of bit packs as a single vector

An insertvalue aggregate built of or-packs of zero-extended fields (e.g.
the { i64, i64 } returned for std::array<int16_t, 8>) was vectorized
pack by pack, leaving the vectors half as wide as possible. Vectorize
the fields of all packs as one tree and bitcast the result to the vector
of the packs.

Fixes #48223

Assisted-by: Cursor

Reviewers: bababuck, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/228955
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LLVM/project 87c23f0 —

[SLP][NFC]Add an extra test with the reodering of the aggregate bitpacks, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/229380
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LLVM/project 74fa966 —

[SLP][NFC]Add an extra test with the reodering of the aggregate bitpacks, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/229380
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LLVM/project a55c5fc —

[Support] Replace sprintf with snprintf in z/OS strsignal implementation (#224487)
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LLVM/project 494156c —

[SLP]Keep dbg_value of the lanes replaced by extractelement

Redirect the debug values of an erased scalar to the extract emitted for
its external user. A record placed before the extract is cloned right
after it, unless that passes a record of the same variable. Lanes
without external users still lose their debug values.

Part of #45507.

Assisted-by: Cursor

Reviewers: RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/228937
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