[libc] Add sys/xattr.h and entrypoints flistxattr, listxattr, and llistxattr. (#224357)
The header is non-POSIX, and the entrypoints, as described in
https://man7.org/linux/man-pages/man2/listxattr.2.html, have
Linux-specific signatures. BSD defines `listxattr` and `flistxattr`, but
with an additional parameter.
Assisted-by: Automated tooling, human reviewed.
Call FileID::getOpaqueValue() instead of getHashValue() for file identity (#224510)
The HTML diagnostics and rewriter code calls FileID::getHashValue() to
get a numeric identifier for each file.
#223794 changes getHashValue() so that it is no longer the identity
function, which breaks tests in clang/test/Analysis/html_diagnostics.
Call getOpaqueValue(), which is equivalent to the current implementation
of getHashValue(), from the HTML diagnostics/rewriter code instead. This
is a no-op today; it only matters once #223794 is reapplied.
[LiveDebugVariables] Repair stale SlotIndexes
The analysis keeps its indexes from before the first register allocator
until DBG_VALUEs are emitted, by which point passes in between have
erased some of the instructions they point at. Resolve them at the
start of each allocator run and before emitting.
SlotIndexes can then reclaim the entries of erased instructions without
sparing the ones held here, which would have made generated code depend
on -g. Emitted locations are unchanged, except that intervals resolving
to one position now emit a single DBG_VALUE rather than identical
consecutive ones.
[SlotIndexes] Add queries for stale indexes
An erased instruction leaves its index list entry in place, making the
index indistinguishable from a block boundary entry. Add
isBlockBoundaryIndex() and isStaleIndex() to tell the two apart, and
canonicalizeIndex() to resolve a stale index to the closest preceding
instruction's register slot, or the block start if none survives.
NFC. No caller yet. LiveDebugVariables is next.
NAS-143927 / 26.0.0 / Check etc files syntax and imports in CI and on build (by themylogin) (#19805)
https://github.com/truenas/middleware/pull/19801 would've been caught by
this check (instead, it is just logged to middleware log on runtime)
Also, legacy APIs are not imported by middleware, so any import-time
error there will only be detected when it crashes middleware on attempt
to access that API.
Original PR: https://github.com/truenas/middleware/pull/19804
Co-authored-by: themylogin <themylogin at gmail.com>
[SPIR-V] Preserve constexpr vectors as OpSpecConstantComposite (#215794)
Let SPIRVEmitIntrinsics handle these the same as structs/arrays, instead
of eagerly expanding them to runtime insertelement chains
umtx: do not sleep on an unowned mutex after a spurious CAS failure
On ll/sc architectures casueword32() may report a spurious
store-conditional failure (reservation lost to an interrupt, preemption,
or another CPU touching the same reservation granule), and this is
indistinguishable from a genuine comparison mismatch: both return 1.
That is intentional since D20772 and documented in casueword(9) ("The
store can fail on load-linked/store-conditional architectures."), so
callers must cope.
do_lock_normal() does not fully cope. When the initial
UMUTEX_UNOWNED -> id acquire CAS fails spuriously, the observed owner is
still UMUTEX_UNOWNED, so neither the UMUTEX_CONTESTED branch nor the
real-owner case applies, and execution falls through past the "rv == 1
but not contested, likely store failure" comment into the sleep path.
There, the contested-bit CAS (expecting the observed owner, i.e.
UMUTEX_UNOWNED) succeeds because the mutex really is unowned, stamping
m_owner = UMUTEX_CONTESTED with no owner tid, and the thread sleeps on
"umtxn" forever: nobody owns the mutex, so no unlock and no wakeup ever
[30 lines not shown]
[SPIRV] Translate {uinc/udec}_wrap as opaque intrinsics for AMD (#215507)
Translation of `uinc_wrap` and `udec_wrap` as if they were opaque llvm
intrinsics, so that they can be restored in the reverse translation to
the exact original code. This only applies to AMD targets.
Part 1 of #213685 split.
umtx: do not sleep on an unowned mutex after a spurious CAS failure
On ll/sc architectures casueword32() may report a spurious
store-conditional failure (reservation lost to an interrupt, preemption,
or another CPU touching the same reservation granule), and this is
indistinguishable from a genuine comparison mismatch: both return 1.
That is intentional since D20772 and documented in casueword(9) ("The
store can fail on load-linked/store-conditional architectures."), so
callers must cope.
do_lock_normal() does not fully cope. When the initial
UMUTEX_UNOWNED -> id acquire CAS fails spuriously, the observed owner is
still UMUTEX_UNOWNED, so neither the UMUTEX_CONTESTED branch nor the
real-owner case applies, and execution falls through past the "rv == 1
but not contested, likely store failure" comment into the sleep path.
There, the contested-bit CAS (expecting the observed owner, i.e.
UMUTEX_UNOWNED) succeeds because the mutex really is unowned, stamping
m_owner = UMUTEX_CONTESTED with no owner tid, and the thread sleeps on
"umtxn" forever: nobody owns the mutex, so no unlock and no wakeup ever
[30 lines not shown]
[offload] plumb HostPtr through PluginContextTy::allocate (#224622)
Restore the memory manager pool for libomptarget allocations. Fixes
regression introduced by: #222677
Assisted-By: Claude Opus
import ports/sysutils/p5-File-XDG, ok bluhm
This module provides a basic implementation of the XDG base directory
specification as exists by the Free Desktop Organization (FDO). It
supports all XDG directories except for the runtime directories, which
require session management support in order to function.
ipsec: Fix sizing and alignment in IPsec policy import and export.
Note: I'm not sure whether it makes sense to have mismatched src and
dst address families -- I doubt it, since userland libipsec rejects
it in ipsec_set_policy(3). I'm also not sure whether it makes sense
to have numbers of addresses other than 0 or 2. But those can be
addressed in a separate commit.
PR kern/60669: netipsec key_sp2msg buffer overrun
