LLVM/project c1972e2 — llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/test/DebugInfo/X86 sdag-order.ll

[DebugInfo][SelectionDAG] Stop unsalvageable debug values from sinking (#233667)

SelectionDAG resolves dangling debug values at the end of a block. When
a
value cannot be salvaged, the poison `DBG_VALUE` currently uses the
current
`SDNodeOrder`, so it can sink past later calls and stores instead of
ending the
earlier variable location at the original debug record.

Use the saved order of the debug record, as the successful salvage paths
already do. Extend `sdag-order.ll` with an unsalvageable call result
followed
by another call and a volatile store; without the fix the location
termination
appears after both instructions.

This completes the ordering correction from #94458 for the final
unsalvageable fallback.

AI assisted with the analysis and development of the fix.
DeltaFile
+69-0llvm/test/DebugInfo/X86/sdag-order.ll
+1-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+70-12 files

FreeBSD/ports 802d5a0 — security/keychain Makefile distinfo

security/keychain: Oops, forgot to include distfile change (for name change)
DeltaFile
+3-3security/keychain/distinfo
+1-1security/keychain/Makefile
+4-42 files

FreeBSD/src 7806832 — lib/libthr/thread thr_private.h thr_pshared.c

libthr: Cache recent pshared_key

For a pshare key, we can actually cache the last one as a fast path
instead of trapping into kernel directly. It makes sense as a lock and
unlock should be a pair on the same key and at the same time. For
example, lock(A) -> unlock(A) -> lock(B) -> unlock(B). Each unlock is
a hit and refresh later (50% hit).

For a single pshare lock, it is evne a 100% hit as the key never
changed.

For nested lock lock(A) -> lock(B) -> lock(C) -> unlock(C) ->
unlock(B) -> unlock(A). It only cache the last one. However, we should
really think about rewritting this logic as it is a pshare lock shared
by many processes and nested should be uncommon.

Reviewed by:    kib
MFC after:      2 weeks
Differential Revision: https://reviews.freebsd.org/D60957
DeltaFile
+45-4lib/libthr/thread/thr_pshared.c
+4-0lib/libthr/thread/thr_private.h
+49-42 files

LLVM/project c41163e — llvm/test/tools/llvm-cas subcommand.test validate-if-needed.test, llvm/tools/llvm-cas llvm-cas.cpp Options.td

address review comments

Created using spr 1.3.7
DeltaFile
+7-7llvm/test/tools/llvm-cas/validate-if-needed.test
+4-4llvm/tools/llvm-cas/Options.td
+2-3llvm/tools/llvm-cas/llvm-cas.cpp
+5-0llvm/test/tools/llvm-cas/subcommand.test
+18-144 files

FreeBSD/ports 934d2a4 — security/keychain pkg-descr Makefile

security/keychain: Small updates

Point at new GH location (old redirects to new), modernize pkg-descr,
and adopt my personal preferences (the port has been around for 21
years, we can probably stop guarding against its name changing.)

Note that keychain 3.x, which has been out for a couple months, is a
Python rewrite. It needs no third-party modules, but it's definitely
a change from the "one portable shell script" ethos I recall from
decades ago. I'm working on that update, and from what I can tell it
should require basically no adjustment on the end-user side of things,
so I'm unlikely to create a keychain298 port (happy to take input on
that!).
DeltaFile
+7-6security/keychain/Makefile
+6-5security/keychain/pkg-descr
+13-112 files

LLVM/project d6181d3 — llvm/include/llvm/IR RuntimeLibcalls.td, llvm/lib/CodeGen WasmEHPrepare.cpp

WasmEHPrepare: Use RuntimeLibcallsInfo

Take the function type, attributes and calling convention from
RuntimeLibcallsInfo instead of constructing them by hand. Also
validate the required functions are available.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+49-15llvm/lib/CodeGen/WasmEHPrepare.cpp
+27-0llvm/test/CodeGen/X86/wasm-eh-prepare-no-lpad-context-libcall.ll
+12-0llvm/test/CodeGen/WebAssembly/wasm-eh-prepare-missing-analysis.ll
+2-2llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
+2-2llvm/test/CodeGen/WebAssembly/wasm-eh-prepare-exception-model.ll
+3-1llvm/include/llvm/IR/RuntimeLibcalls.td
+95-206 files

LLVM/project d7303ed — utils/bazel/llvm-project-overlay/lldb/source/Plugins plugin_config.bzl BUILD.bazel, utils/bazel/llvm-project-overlay/lldb/unittests BUILD.bazel

[Bazel] Fix bazel build for 65074579a63b4db6657cb0f3c4bf4d2cb62fd3ef (#239009)
DeltaFile
+19-1utils/bazel/llvm-project-overlay/lldb/unittests/BUILD.bazel
+15-0utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
+35-13 files

LLVM/project ce73367 — llvm/lib/IR RuntimeLibcalls.cpp, llvm/test/TableGen RuntimeLibcallEmitter-attributes.td

RuntimeLibcalls: Mark vector libcall out pointers dereferenceable

The whole vector width will be written, so mark the vector width. To
maintain the element width alignment for some functions, we need to
start explicitly tracking if the element alignment is used or not.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+9-5llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
+10-3llvm/test/TableGen/RuntimeLibcallEmitter-attributes.td
+11-2llvm/lib/IR/RuntimeLibcalls.cpp
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef.ll
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/amdlibm.ll
+48-282 files not shown
+53-348 files

LLVM/project 11f3ffb — mlir/include/mlir/Conversion/VectorToXeGPU VectorToXeGPU.h, mlir/lib/Conversion/VectorToXeGPU VectorToXeGPU.cpp

[MLIR][XeGPU] Lower transfer_read with a broadcast permutation map (#225957)

Dequantization produces reads whose permutation map broadcasts some
vector dimensions — they load <1x64> and repeat it across <64x64>.
vector-to-xegpu rejected such maps.

```mlir
  %0 = vector.transfer_read %scales[%e, %g, %n], %pad
  {in_bounds = [true, true], permutation_map = affine_map<(d0,d1,d2) -> (d2, 0)>}
  : memref<256x32x512xf16>, vector<64x64xf16>
```
Solution: lowerBroadcastRead() rewrites the map: ((d2, 0) → (d2, d1),
vector<64x64> → vector<64x1>) and appends a vector.broadcast.
 
 So it now lowers to
```mlir
  %narrow = xegpu.load_nd %desc[%g, %n] : ... -> vector<1x64xf16>
  %t = vector.transpose %narrow, [1, 0] : vector<1x64xf16> to vector<64x1xf16>
  %r = vector.broadcast %t : vector<64x1xf16> to vector<64x64xf16>

    [4 lines not shown]
DeltaFile
+277-52mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
+192-51mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
+19-0mlir/test/Conversion/VectorToXeGPU/transfer-write-to-xegpu.mlir
+6-0mlir/include/mlir/Conversion/VectorToXeGPU/VectorToXeGPU.h
+494-1034 files

FreeBSD/ports 8353149 — Tools/scripts update-plist.py

Tools/scripts/update-plist.py: Bugfix

Remove stale pkg-plist lines preceded by an OPTIONS_SUB. E.g.: remove
%%FOO%%include/bar.h if it is no longer packaged.

MFH:            2026Q4
(cherry picked from commit 97856031311db3350b2e1428d7a9b00f9c2e5b85)
DeltaFile
+2-1Tools/scripts/update-plist.py
+2-11 files

LLVM/project 33127b7 — llvm/include/llvm/IR RuntimeLibcalls.td RuntimeLibcallsImpl.td, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Declare vector libcall attributes in TableGen

Replace the type-based heuristics for vector math libcall attributes
with attributes declared on the libcall definitions, emitted with the
same attribute table helpers as intrinsics.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+226-1llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
+103-0llvm/test/TableGen/RuntimeLibcallEmitter-attributes.td
+26-56llvm/lib/IR/RuntimeLibcalls.cpp
+52-0llvm/test/TableGen/RuntimeLibcallEmitter-attributes-errors.td
+44-3llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+23-9llvm/include/llvm/IR/RuntimeLibcalls.td
+474-691 files not shown
+478-737 files

FreeBSD/ports 9785603 — Tools/scripts update-plist.py

Tools/scripts/update-plist.py: Bugfix

Remove stale pkg-plist lines preceded by an OPTIONS_SUB. E.g.: remove
%%FOO%%include/bar.h if it is no longer packaged.

MFH:            2026Q4
DeltaFile
+2-1Tools/scripts/update-plist.py
+2-11 files

LLVM/project 442bbe1 — llvm/lib/Transforms/IPO InstrumentorUtils.cpp, llvm/test/Instrumentation/Instrumentor i128_filter_config.json i128_filter.ll

[Instrumentor] Fix large int comparisons in filter expressions (#227585)

Fixes #226941
DeltaFile
+59-0llvm/test/Instrumentation/Instrumentor/i128_filter.ll
+16-17llvm/lib/Transforms/IPO/InstrumentorUtils.cpp
+9-0llvm/test/Instrumentation/Instrumentor/i128_filter_config.json
+84-173 files

LLVM/project 36ab334 — llvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/CodeGen/RISCV atomic-cmpxchg.ll atomic-signext.ll

AtomicExpand: Use RuntimeLibcallsInfo signatures for atomic libcalls (#238972)

Take the function type and attributes of the emitted __atomic_* calls
from RuntimeLibcallsInfo instead of building them by hand.

This fixes missing extension attributes on the value operand and
result of the sized variants, which are unsigned integers of the
access size. On targets whose C ABI extends narrow integer arguments,
such as RISC-V and ARM, the callee could see unextended high bits. i8
and i16 values now get zeroext, and i32 values get signext on
RV64. Callers can also rely on the extended return value, which
removes redundant extensions after some calls.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+705-360llvm/test/CodeGen/RISCV/atomic-rmw.ll
+460-360llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+166-104llvm/test/CodeGen/RISCV/atomic-signext.ll
+105-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-and-or-xor.ll
+19-56llvm/lib/CodeGen/AtomicExpandPass.cpp
+70-0llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+1,525-88014 files not shown
+1,777-96120 files

FreeBSD/src 9d48e88 — sys/dev/gve gve_tx_dqo.c gve_rx_dqo.c

gve: Page-align DQO descriptor and completion rings

Currently, gve_rx_alloc_ring_dqo() and gve_tx_alloc_ring_dqo() request
CACHE_LINE_SIZE alignment when allocating DMA memory for the DQO TX/RX
descriptor and completion rings. The device requires stronger alignment
than cache line alignment, which was incidentally being met due to how
the kernel allocates memory. Explicitly meet this requirement by
requesting page aligned memory.

Signed-off-by: Tim Hostetler <thostet at google.com>

Reviewed by:    markj, Jasper Tran O'Leary <jtranoleary at google.com>
MFC after:      2 weeks
Differential Revision:  https://reviews.freebsd.org/D61211
DeltaFile
+2-2sys/dev/gve/gve_tx_dqo.c
+2-2sys/dev/gve/gve_rx_dqo.c
+4-42 files

FreeBSD/src 64ea2b9 — sys/dev/gve gve_main.c gve_adminq.c

gve: Fix AdminQ buffer DMA sync directions

In gve_verify_driver_compatibility(), the driver populates the
gve_driver_info buffer for the device to read. Sync this buffer with
BUS_DMASYNC_PREWRITE instead of BUS_DMASYNC_PREREAD before issuing
the command.

In gve_adminq_describe_device(), the device populates the
gve_device_descriptor buffer for the driver to read. Sync this buffer
with BUS_DMASYNC_PREREAD instead of BUS_DMASYNC_PREWRITE before
issuing the command.

In gve_adminq_get_ptype_map_dqo(), the device populates the
gve_ptype_map buffer for the driver to read. Add the missing
BUS_DMASYNC_PREREAD and BUS_DMASYNC_POSTREAD syncs around the
command.

In normal GCP environments this did not cause a functional failure
because the underlying platforms are DMA cache-coherent and

    [12 lines not shown]
DeltaFile
+5-1sys/dev/gve/gve_adminq.c
+1-1sys/dev/gve/gve_main.c
+6-22 files

FreeBSD/ports 50c8ef8 — security/keychain Makefile

security/keychain: Adopt port
DeltaFile
+1-1security/keychain/Makefile
+1-11 files

FreeBSD/ports 57b1adb — www/caddy Makefile distinfo, www/caddy-custom Makefile

www/caddy: Update to 2.11.8

This contains numerous fixes to handling broken-by-design scenarios,
such as PHP. All users should update, especially if caddy drives a
php_fastcgi backend.

Read the Changes for details.

Changes: https://github.com/caddyserver/caddy/releases/tag/v2.11.8
(cherry picked from commit 8158627dbaa5446d44a3752997d868870c804c39)
DeltaFile
+5-5www/caddy/distinfo
+1-2www/caddy/Makefile
+0-1www/caddy-custom/Makefile
+6-83 files

LLVM/project 3b35c40 — llvm/lib/Target/ARM MVETPAndVPTOptimisationsPass.cpp

ARM: Remove dead kill flag maintenance in MVETPAndVPTOptimisations

This pass runs before register allocation, and the verifier now
rejects kill flags on virtual registers.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+2-45llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
+2-451 files

LLVM/project b03f03c — llvm/lib/Target/AArch64 AArch64PostCoalescerPass.cpp

AArch64: Remove dead kill flag maintenance in AArch64PostCoalescer

The sources of the transposed tuple pseudos are virtual registers,
which can no longer carry kill flags.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-12llvm/lib/Target/AArch64/AArch64PostCoalescerPass.cpp
+0-121 files

LLVM/project e04c4cc — llvm/lib/CodeGen EarlyIfConversion.cpp

EarlyIfConversion: Remove dead kill flag maintenance

The verifier now rejects kill flags on virtual registers, so there are
never repeated kills of a virtual register in the two sides of a
diamond to clear.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-38llvm/lib/CodeGen/EarlyIfConversion.cpp
+0-381 files

LLVM/project 55f4d89 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.tanh.ll llvm.amdgcn.permlane.ll

[AMDGPU] Do not emit s_wait_bvhcnt on targets without BVH instructions (#238971)

GFX13 has image instructions but no BVH instructions or s_wait_bvhcnt
DeltaFile
+0-248llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
+0-105llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
+0-53llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+0-40llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
+0-36llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+0-36llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+0-51830 files not shown
+30-77636 files

FreeBSD/src 12b3c29 — sys/compat/linuxkpi/common/include/linux ioctl.h, sys/dev/sound/pcm mixer.c dsp.c

ioctl: Add a macro for extracting the ioctl number from a command

Sprinkle it in various drivers which hard-coded the command layout.

No functional change intended.

Reviewed by:    dumbbell, emaste
MFC after:      1 week
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D61045
DeltaFile
+6-5sys/dev/syscons/scvesactl.c
+2-2sys/dev/syscons/scvidctl.c
+1-1sys/netgraph/ng_eiface.c
+1-1sys/dev/sound/pcm/mixer.c
+1-1sys/dev/sound/pcm/dsp.c
+1-1sys/compat/linuxkpi/common/include/linux/ioctl.h
+12-111 files not shown
+13-117 files

LLVM/project 0e50208 — llvm/lib/CodeGen MachineVerifier.cpp, llvm/test/MachineVerifier/AMDGPU register-killed-inside-loop.mir verify-kill-flag-virtual-register.mir

MachineVerifier: Disallow kill flags on virtual registers

Kill flags are deprecated, and nothing introduces them on virtual
registers anymore. Reject them in the verifier to prevent new uses
from creeping back in. Kill flags on physical registers are still
permitted. There are still some lingering post-RA kill flag reliance.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+11-12llvm/unittests/MIR/MachineMetadata.cpp
+21-0llvm/test/MachineVerifier/AMDGPU/verify-kill-flag-virtual-register.mir
+3-5llvm/test/MachineVerifier/AMDGPU/register-killed-inside-loop.mir
+3-3llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/amdgpu-scattered-filter.mir.filter.expected
+3-3llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/amdgpu-scattered-filter.mir
+3-0llvm/lib/CodeGen/MachineVerifier.cpp
+44-236 files

FreeBSD/ports 8158627 — www/caddy Makefile distinfo, www/caddy-custom Makefile

www/caddy: Update to 2.11.8

This contains numerous fixes to handling broken-by-design scenarios,
such as PHP. All users should update, especially if caddy drives a
php_fastcgi backend.

Read the Changes for details.

Changes: https://github.com/caddyserver/caddy/releases/tag/v2.11.8
DeltaFile
+5-5www/caddy/distinfo
+1-2www/caddy/Makefile
+0-1www/caddy-custom/Makefile
+6-83 files

LLVM/project 1f224ad — llvm/lib/CodeGen LiveRangeCalc.cpp LiveInterval.cpp, llvm/test/CodeGen/AMDGPU liveintervals-unreachable-blocks-subranges.mir

Only join phi-def-only classes in unreachable blocks

Use the dominator tree for reachability in LiveRangeCalc
DeltaFile
+73-0llvm/unittests/MI/LiveIntervalTest.cpp
+60-1llvm/test/CodeGen/PowerPC/tls-dynamic-call-unreachable-block.ll
+27-15llvm/lib/CodeGen/LiveInterval.cpp
+0-24llvm/test/CodeGen/PowerPC/tls-dynamic-call-unreachable-block-optnone.ll
+3-4llvm/lib/CodeGen/LiveRangeCalc.cpp
+2-3llvm/test/CodeGen/AMDGPU/liveintervals-unreachable-blocks-subranges.mir
+165-472 files not shown
+170-518 files

LLVM/project 1ff387e — llvm/lib/CodeGen LiveRangeCalc.cpp LiveInterval.cpp, llvm/test/CodeGen/AMDGPU liveintervals-unreachable-blocks-subranges.mir

CodeGen: Handle uses in unreachable blocks in LiveIntervals

Previously LiveIntervals had the unenforced assumption that the
function does not contain any unreachable blocks. A register which had
a definition somewhere but also a use in an unreachable block would
hit a "Use not jointly dominated by defs" assertion.

Avoiding no-unreachable-blocks as a hard requirement avoids assertions
in some pass configuration edge cases. In particular when the
MachinePipeliner is enabled in an optimized pipeline there could still
be unreachable blocks in an optnone function which would hit the
assert. Not handling unreachable blocks was also a large problem for
llvm-reduce's MIR support and was one of the main obstacles to landing
a basic block reduction.

Give a value live into an unreachable block a phi-def at the start of
the block, using the dominator tree to identify unreachable blocks.
ConnectedVNInfoEqClasses::Classify joins a component made only of
phi-defs in unreachable blocks with a component that has a real def;

    [6 lines not shown]
DeltaFile
+244-0llvm/test/CodeGen/X86/liveintervals-unreachable-blocks.mir
+101-0llvm/test/CodeGen/AMDGPU/liveintervals-unreachable-blocks-subranges.mir
+27-0llvm/lib/CodeGen/LiveInterval.cpp
+23-3llvm/lib/CodeGen/LiveRangeCalc.cpp
+395-34 files

FreeBSD/src 9ca2cfe — lib/libsecureboot vesigned.c libsecureboot-priv.h

libsecureboot: add support for more signatures

For 2027 we need to support new, stronger signatures and hashes.

Re-work Makefile.inc and local.trust.mk to define
VE_SIGN_URL_LIST or VE_SIGNATURE_LIST (can be derrived from
VE_SIGN_URL_LIST) containing tuples of sig/method/hash/flags and
for VE_SIGN_URL_LIST the same plus /url.

From VE_SIGNATURE_LIST we derrive VE_SIGNATURE_EXT_LIST used to populate
signature_ext_list which defines the order in which we look for
signatures for a manifest.

We also populate signature_info_list which maps a signature ext to the
needed hash and flags to indicate whether that hash needs to be repeated.

verify_sig will lookup signature_info_list, no match means not
supported.  For asc we just call verify_asc() otherwise we call
verify_ec() or verify_rsa() depending on the key type found in the

    [15 lines not shown]
DeltaFile
+90-25lib/libsecureboot/vets.c
+63-31lib/libsecureboot/Makefile.inc
+37-35lib/libsecureboot/local.trust.mk
+44-3lib/libsecureboot/README.rst
+18-0lib/libsecureboot/libsecureboot-priv.h
+1-5lib/libsecureboot/vesigned.c
+253-991 files not shown
+254-1007 files

FreeBSD/src ca19042 — sys/fs/nfsclient nfs_clrpcops.c

nfs_clrpcops.c: Fix typo in commit db8444c1b7e4

Reported by:    markj
MFC after:      1 month
Fixes:  884ee8d6c9b4 ("nfscl: Add some glue for client side NFS over RDMA")
DeltaFile
+1-1sys/fs/nfsclient/nfs_clrpcops.c
+1-11 files

NetBSD/pkgsrc-wip 2c904fd — lightcraft COMMIT_MSG Makefile, lightcraft/patches patch-Cargo.toml

Update graphics/lightcraft to v.0.18.0
DeltaFile
+493-156lightcraft/distinfo
+160-51lightcraft/cargo-depends.mk
+57-0lightcraft/patches/patch-Cargo.toml
+10-3lightcraft/Makefile
+3-1lightcraft/COMMIT_MSG
+723-2115 files