FreeBSD/ports 54e992bdevel/nodeeditor distinfo Makefile

devel/nodeeditor: Update 3.0.12 => 3.0.16

Commit log:
https://github.com/paceholder/nodeeditor/compare/3.0.12...3.0.16

PR:             294139
Reported by:    Martin Filla <freebsd at sysctl.cz> (maintainer)
Approved by:    maintainer, vvd (mentor)
DeltaFile
+3-3devel/nodeeditor/distinfo
+1-1devel/nodeeditor/Makefile
+1-0devel/nodeeditor/pkg-plist
+5-43 files

pfSense/pfsense 85b1e4fsrc/etc/inc pfsense-utils.inc

Constrain regex for ifconfig parsing. Fix #16769

This avoids matching e.g. "ssid" on a line that contains "-hidessid".
DeltaFile
+13-13src/etc/inc/pfsense-utils.inc
+13-131 files

FreeBSD/ports ce104a2math/R-cran-RcppRoll distinfo Makefile

math/R-cran-RcppRoll: Update to 0.3.2

Reported by:    portscout
DeltaFile
+3-3math/R-cran-RcppRoll/distinfo
+1-1math/R-cran-RcppRoll/Makefile
+4-42 files

LLVM/project fcc69c3llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp GCNSchedStrategy.h

Format
DeltaFile
+5-5llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+1-1llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+6-62 files

LLVM/project 7a3b7f1clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen CIRGenCleanup.cpp CIRGenCleanup.h

[CIR] Implement handling of cleanups with active flag (#187389)

This implements handling of cleanup scopes in cases where a flag is
needed to indicate whether or not the cleanup is active. This happens in
cases where a cleanup is no longer required, but it isn't at the top of
the cleanup stack so it can't be popped. A temporary variable is used to
set the cleanup to an inactive state when it is no longer needed.

Assisted-by: Cursor / claude-4.6-opus-high (implementation)
Assisted-by: Cursor / gpt-5.3-codex (tests)
DeltaFile
+374-0clang/test/CIR/CodeGen/new-delete-deactivation.cpp
+95-8clang/lib/CIR/CodeGen/CIRGenCleanup.cpp
+20-0clang/lib/CIR/CodeGen/CIRGenCleanup.h
+0-1clang/include/clang/CIR/MissingFeatures.h
+489-94 files

NetBSD/pkgsrc-wip 770ce82gnucash PLIST Makefile

gnucash: fixed, updated in pkgsrc
DeltaFile
+0-1,181gnucash/PLIST
+0-89gnucash/Makefile
+0-48gnucash/options.mk
+0-21gnucash/DESCR
+0-20gnucash/PLIST.python
+0-15gnucash/buildlink3.mk
+0-1,3745 files not shown
+0-1,39511 files

FreeBSD/ports f6d97d1benchmarks/stress-ng distinfo Makefile

benchmarks/stress-ng: Update to 1.20.00
DeltaFile
+3-3benchmarks/stress-ng/distinfo
+1-2benchmarks/stress-ng/Makefile
+4-52 files

LLVM/project 54b7230mlir/lib/Dialect/Affine/IR AffineOps.cpp, mlir/lib/Dialect/Affine/Transforms AffineExpandIndexOpsAsAffine.cpp

[MLIR][Affine] Add vector support to affine.linearize_index and affine.delinearize_index (#188369)

Allow `affine.delinearize_index` and `affine.linearize_index` to operate
on `vector<...x index>` types in addition to scalar indices.

---------

Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
DeltaFile
+167-0mlir/test/Dialect/Affine/canonicalize.mlir
+96-18mlir/lib/Dialect/Affine/Transforms/AffineExpandIndexOpsAsAffine.cpp
+76-0mlir/test/Dialect/Affine/affine-expand-index-ops-as-affine.mlir
+47-0mlir/test/Dialect/Affine/affine-expand-index-ops.mlir
+42-0mlir/test/Dialect/Affine/ops.mlir
+27-11mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+455-293 files not shown
+506-379 files

LLVM/project 6e6dd04llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp GCNSchedStrategy.h, llvm/test/CodeGen/AMDGPU sched_mfma_rewrite_copies.mir misched-remat-revert.ll

[AMDGPU][Scheduler] Use MIR-level rematerializer in rematerialization stage

This makes the scheduler's rematerialization stage use the
target-independent rematerializer. Previosuly duplicate logic is
deleted, and restrictions are put in place in the stage so that the
same cosntraints as before apply on rematerializable registers (as the
rematerializer is able to expose many more rematerialization
opportunities than what the stage can track at the moment).
Consequently it is not expected that this change improves performance
overall, but it is a first step toward being able to use the
rematerializer's more advanced capabilities during scheduling.

This is *not* a NFC for 2 reasons.

- Score equalities between two rematerialization candidates with
  otherwise equivalent score are decided by their corresponding
  register's index handle in the rematerializer (previously the pointer
  to their state object's value). This is determined by the
  rematerializer's register collection order, which is different from

    [10 lines not shown]
DeltaFile
+551-551llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
+0-577llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
+103-294llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+47-72llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+36-36llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
+19-19llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
+756-1,5492 files not shown
+779-1,5728 files

FreeNAS/freenas a72c52asrc/middlewared/middlewared/etc_files truenas_zfstierd.py, src/middlewared/middlewared/plugins/service_/services truenas_zfstierd.py

Fix
DeltaFile
+13-0src/middlewared/middlewared/etc_files/truenas_zfstierd.py
+7-0src/middlewared/middlewared/plugins/service_/services/truenas_zfstierd.py
+20-02 files

LLVM/project ae835demlir/include/mlir/Dialect/AMDGPU/IR AMDGPUOps.td, mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp

[mlir][amdgpu] implement amdgpu.global_load_async_to_lds for gfx1250 (#189279)

This patch introduces an amdgpu wrapper for
`rocdl.global.load.async.to.lds.bN` intrinsics, which were introduced in
gfx1250.

Assisted-by: Claude

---------

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+73-0mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
+68-2mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+46-0mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
+35-0mlir/test/Dialect/AMDGPU/invalid.mlir
+31-0mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
+26-0mlir/test/Dialect/AMDGPU/ops.mlir
+279-26 files

LLVM/project 76f5c5dclang-tools-extra/clang-tidy/readability ImplicitBoolConversionCheck.cpp ImplicitBoolConversionCheck.h, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Add AllowLogicalOperatorConversion option to implicit-bool-conversion (#189149)

Fixes https://github.com/llvm/llvm-project/issues/176889.
DeltaFile
+94-0clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion-allow-logical-operators.c
+19-0clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
+7-0clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
+4-0clang-tools-extra/docs/ReleaseNotes.rst
+1-0clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.h
+125-05 files

FreeBSD/ports 44384e3benchmarks/hyperfine distinfo Makefile.crates

benchmarks/hyperfine: Update to 1.20.0
DeltaFile
+203-169benchmarks/hyperfine/distinfo
+100-83benchmarks/hyperfine/Makefile.crates
+1-2benchmarks/hyperfine/Makefile
+304-2543 files

LLVM/project 5f99854llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/IR AutoUpgrade.cpp

[AMDGPU] Drop A and B neg modifier from amdgcn_wmma_bf16_16x16x32_bf16 (#189468)

Fixes: LCOMPILER-1673
DeltaFile
+6-46llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+10-10llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
+13-0llvm/test/Bitcode/amdgpu-wmma-drop-ab-mods-upgrade.ll
+7-3llvm/lib/IR/AutoUpgrade.cpp
+3-5llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+3-5mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+42-6910 files not shown
+60-8816 files

NetBSD/src POQR3hosys/uvm uvm_swap.c

   uvm_swap.c: make the drum mpsafe (cont.)

   mark swapiod WQ_MPSAFE.
VersionDeltaFile
1.224+4-3sys/uvm/uvm_swap.c
+4-31 files

FreeNAS/freenas 9478148src/middlewared/middlewared/etc_files scst.conf.mako, src/middlewared/middlewared/plugins/failover_ event.py

Track and propagate STANDBY ALUA state explicitly

Drive the STANDBY target group through OFFLINE -> TRANSITIONING ->
NONOPTIMIZED across the failover and standby_after_start lifecycle,
updating both nodes at each transition so RTPG responses are accurate
on whichever node an initiator queries.  On reload, the current state
is consulted rather than hardcoding nonoptimized.
DeltaFile
+31-30src/middlewared/middlewared/plugins/iscsi_/scst.py
+24-1src/middlewared/middlewared/plugins/iscsi_/alua.py
+6-2src/middlewared/middlewared/plugins/failover_/event.py
+2-2src/middlewared/middlewared/etc_files/scst.conf.mako
+63-354 files

NetBSD/pkgsrc-wip c44fd79gnucash PLIST Makefile

gnucash: add update candidate

doesn't build, reported upstream
DeltaFile
+1,181-0gnucash/PLIST
+89-0gnucash/Makefile
+48-0gnucash/options.mk
+21-0gnucash/DESCR
+20-0gnucash/PLIST.python
+15-0gnucash/buildlink3.mk
+1,374-05 files not shown
+1,398-011 files

FreeBSD/ports ab01314science/R-cran-Epi distinfo Makefile

science/R-cran-Epi: Update to 2.64

Reported by:    portscout
DeltaFile
+3-3science/R-cran-Epi/distinfo
+1-1science/R-cran-Epi/Makefile
+4-42 files

LLVM/project e50f08bmlir/lib/Dialect/XeGPU/Transforms XeGPUSgToWiDistributeExperimental.cpp, mlir/test/Dialect/XeGPU sg-to-wi-experimental-unit.mlir

[MLIR] [XeGPU] Add distribution patterns for vector transpose, bitcast & mask ops in sg to wi pass  (#187392)

This PR adds patterns for following vector ops in the new sg-to-wi pass

1. Transpose
2. BitCast
3. CreateMask
4. ConstantMask
DeltaFile
+178-10mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
+108-0mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+286-102 files

LLVM/project 19caff4utils/bazel/llvm-project-overlay/mlir BUILD.bazel, utils/bazel/llvm-project-overlay/mlir/unittests BUILD.bazel

[Bazel] Fixes b6e4d27 (#189473)

This fixes b6e4d27c485af711214b3dafc96fa287e2fe33f6.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+13-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+2-0utils/bazel/llvm-project-overlay/mlir/unittests/BUILD.bazel
+15-02 files

LLVM/project 77bc575llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp GCNSchedStrategy.h

[AMDGPU][Scheduler] Prepare remat. stage for rematerializer integration (NFC)

This NFC prepares the scheduler's rematerialization stage for
integration with the target-independent rematerializer. It brings
various small design changes and optimizations to the stage's internal
state to make the not-exactly-NFC rematerializer integration as small as
possible.

The main changes are, in no particular order:

- Sort and pick useful rematerialization candidates by their index in
  the vector of candidates instead of directly sorting objects within
  the candidate vector. This reduces the amount of data movement and
  simplifies the candidate selection logic.
- Move some data members from `PreRARematStage::RematReg` to
  `PreRARematStage::ScoredRemat`. This makes the former a simplified
  version of the rematerializer's own internal register representation
  (`Rematerializer::Reg`), which can be cleanly deleted during
  integration.

    [8 lines not shown]
DeltaFile
+154-141llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+58-51llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+11-0llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+4-0llvm/lib/Target/AMDGPU/GCNRegPressure.h
+227-1924 files

FreeBSD/ports 40961b2devel/pecl-xdebug distinfo Makefile

devel/pecl-xdebug: Update to 3.5.1

PR:             290757
DeltaFile
+3-3devel/pecl-xdebug/distinfo
+1-3devel/pecl-xdebug/Makefile
+4-62 files

NetBSD/pkgsrc TAbO88ftextproc/py-sphinxfeed-lsaffre Makefile

   py-sphinxfeed-lsaffre: not for 310/311 because of py-sphinx
VersionDeltaFile
1.2+3-1textproc/py-sphinxfeed-lsaffre/Makefile
+3-11 files

LLVM/project 9d3079allvm/lib/CodeGen InlineAsmPrepare.cpp

[NFC][CodeGen] Prepare for expansion of InlineAsmPrepare (#189469)

Move some functions around so that the CallBrInst processing is
contained. The 'static' functions don't need to be declared at the top;
just place them before the calls. Fix the naming to use lower-case for
the first letter of function names.
DeltaFile
+151-137llvm/lib/CodeGen/InlineAsmPrepare.cpp
+151-1371 files

LLVM/project a0ffdf2clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/test/CIR/CodeGen ctor-alias-prev-decl.cpp dtor-alias-prev-decl.cpp

[CIR] Allow replacement of a structor declaration with an alias (#188320)

We had an errorNYI diagnostic to trigger when we generated an alias for
a ctor or dtor that had an existing declaration. Because functions are
used via flat symbol references, all that is needed is to erase the old
declaration. This change does that.
DeltaFile
+43-0clang/test/CIR/CodeGen/ctor-alias-prev-decl.cpp
+42-0clang/test/CIR/CodeGen/dtor-alias-prev-decl.cpp
+8-2clang/lib/CIR/CodeGen/CIRGenModule.cpp
+93-23 files

FreeNAS/freenas 16f7aa6src/middlewared/middlewared role.py, src/middlewared_docs/docs rbac.rst

Improve RBAC docs

Address feedback from other teams:
* Improve phrasing for the individual vs compound roles
* Add table with list of current roles
DeltaFile
+189-22src/middlewared_docs/docs/rbac.rst
+2-0src/middlewared/middlewared/role.py
+191-222 files

NetBSD/pkgsrc F6jtGk3doc TODO CHANGES-2026

   doc: Updated games/greed to 4.5
VersionDeltaFile
1.27027+3-1doc/TODO
1.2018+2-1doc/CHANGES-2026
+5-22 files

NetBSD/pkgsrc iKqHB39games/greed distinfo Makefile, games/greed/patches patch-greed.c

   greed: update to 4.5.

     Fix BSD build failure.

   (meaning, our pkgsrc patch was merged)
VersionDeltaFile
1.13+4-5games/greed/distinfo
1.9+2-2games/greed/Makefile
1.2+1-1games/greed/patches/patch-greed.c
+7-83 files

FreeBSD/ports 54132d5misc/ollama Makefile, misc/ollama/files ollama.in

misc/ollama: Fix Vulkan support; Fix home directory value in ollama service
DeltaFile
+8-3misc/ollama/Makefile
+2-2misc/ollama/files/ollama.in
+10-52 files

LLVM/project f732918clang/docs ClangIRCleanupAndEHDesign.md, clang/lib/CIR/Dialect/Transforms EHABILowering.cpp

[CIR] Handle throwing calls inside EH cleanup (#188341)

This implements handling for throwing calls inside an EH cleanup
handler. When such a call occurs, the CFG flattening pass replaces it
with a cir.try_call op that unwinds to a terminate block.

A new CIR operation, cir.eh.terminate, is added to facilitate this
handling, and the design document is updated to describe the new
behavior.

Assisted-by: Cursor / claude-4.6-opus-high
DeltaFile
+166-0clang/test/CIR/Transforms/flatten-throwing-in-cleanup.cir
+0-120clang/test/CIR/Transforms/flatten-cleanup-scope-nyi.cir
+118-0clang/test/CIR/CodeGen/cleanup-throwing-dtor.cpp
+91-4clang/docs/ClangIRCleanupAndEHDesign.md
+72-0clang/lib/CIR/Dialect/Transforms/EHABILowering.cpp
+57-0clang/test/CIR/Transforms/eh-abi-lowering-itanium.cir
+504-1242 files not shown
+579-1358 files