[mlir][Arith] Fix crash when folding operations with dynamic-shaped tensors (#178428)
- Add static shape check in `getBoolAttribute` to prevent crash when
folding comparison operations with dynamic-shaped tensor types
- Add static shape check in `SelectOp::fold` before creating
`DenseElementsAttr` for the result
- Add test case to verify the fix
Fixes #178415.
Co-authored-by: Claude Opus 4.5 <noreply at anthropic.com>
[AArch64] Mark X16 as clobbered in PAUTH_EPILOGUE for hint-based PAuthLR
When users request branch protection with PAuthLR on targets that do not
support the PAuthLR instructions, the PAUTH_EPILOGUE falls back to using
hint-space instructions. This fallback sequence uses X16 as a temporary
register, but X16 was not listed in the clobber set.
Because Speculative Load Hardening uses X16, this omission made SLH
incompatible with this PAUTH_EPILOGUE path.
Mark X16 as clobbered so the compiler does not assume X16 is preserved across
the epilogue, restoring compatibility with Speculative Load Hardening and
avoiding incorrect register liveness assumptions. The clobber is added in C++
rather than TableGen, as X16 is only clobbered when PAuthLR is requested as a
branch protection variation and should not be treated as clobbered
unconditionally.
[SLP]Support for tree throttling in SLP graphs with gathered loads
Gathered loads forming DAG instead of trees in SLP vectorizer. When
doing the throttling analysis for such graphs, need to consider partially
matched gathered loads DAG nodes and consider extract and/or gather
operations and their costs.
The patch adds this analysis and allows cutting off the expensive
sub-graphs with gathered loads.
Reviewers: hiraditya, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/177855
Recommit after revert in d733771113339608aff6002d1fa89aaf4a51c502, which
was related to a crash in SelectionDAG
[AArch64] Remove dead code emission in Pointer Authentication (#175989)
The AArch64 Pointer Authentication pass was emitting address
materialization instructions that were never used. These instructions
formed dead code and served no purpose in the final control flow.
Remove the unnecessary ADRP/ADD sequence from the Pointer Auth codegen
and update the corresponding test to reflect the simplified output.
This avoids generating dead instructions and keeps the PAUTH LR sequence
minimal and correct.
[AArch64] Refactor PACM emission in Pointer Authentication (NFC) (#175937)
Refactor the emission of PACM instructions in the AArch64 Pointer
Authentication code to simplify the control flow and reduce duplication.
This change consolidates the PACM generation logic, making the code
easier to follow and less error-prone, while preserving the existing
behavior and generated output.
No functional change is intended beyond the internal refactoring.
[flang] Converted five tests from old lowering to new lowering (part 9) (#176310)
Tests converted from test/Lower: c-interoperability-c-pointer.f90,
c-interoperability.f90, character-elemental.f90,
character-local-variables.f90, complex-operations.f90
Add umount utility
This commit exposes truenas_os.umount2 as an available utility
in mount.py, and replaces existing subprocess calls to the
umount command with the syscall-based utility.
[LV] Add support for llvm.vector.partial.reduce.fadd (#163975)
Allows the Loop Vectorizer to generate `llvm.vector.partial.reduce.fadd`
intrinsics when sequences which match its requirements are found.
NAS-138841 / 26.0.0-BETA.1 / Remove configuration of legacy NFS client tracking. (#18112)
Debian Trixie has removed support for the legacy NFS client tracking.
This PR makes the changes to follow that.
Update CI test to match.
CI tests run with no change in behavior.
Also confirmed, on single and HA systems, that multiple clients doing
active writing are correctly paused and restart write operations with no
loss of data or corruption across a reboot and sudden power loss.
This PR is part of a pair. The companion PR is
https://github.com/truenas/linux/pull/237
[AArch64][llvm] Allow some `tlbip` insns to be used with only +tlbid
Allow `tlbip` instructions containing *E1IS*, *E1OS*, *E2IS* or *E2OS*
to be used with `+tlbid` or `+d128`. This is because the 2025 Armv9.7-A
MemSys specification says:
```
All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions
that are currently dependent on FEAT_D128 are updated to be dependent
on FEAT_D128 or FEAT_TLBID
```
[AArch64][GlobalISel] Add support for scalar variants of neon right shifts (#178207)
Neon intrinsics are able to operate on single-element vectors (e.g <1 x
i64>). However, LLVM doesn't allow single-element vectors, and instead
converts them to scalar values (e.g i64) in the frontend.
To get around this, the backend must place these scalar values onto an
fpr register bank, in order for the intrinsic to operate on the value as
a vector.
Previously, scalar right shift intrinsics were not legalising due to
misconfigured logic in AArch64LegalizerInfo, which treated non-vector
variants of these intrinsics as invalid.
This has been fixed so that the following can lower:
sqshrn
sqshrun
sqrshrn
sqrshrun
uqshrn
uqrshrn
