DEVICE_IDENTIFY.9: Fix function call to detect driver in example code
Fixes: ccabc7c2e556 ("DEVICE_IDENTIFY.9: Modernize description and use cases")
MFC after: 3 days
Sponsored by: The FreeBSD Foundation
Replace pysnmp with truenas_pysnmp C extension for SNMP traps
Rewrites snmp_trap.py to use the truenas_pysnmp C extension and replaces
the python3-pysnmp4 dependency with python3-truenas-pysnmp.
[libc][math] Implement C23 half precision erfc function (#180930)
Add support for the half-precision complementary error function
`erfcf16``, using a Sollya generated polynomial implementation with
proper handling of special cases.
Extend the MPFR utilities with erfc support to allow tests.
closes: #180927
Revert "[MLIR] Fix ErasedOpsListener false positives for newly created ops/blocks" (#189010)
Reverts llvm/llvm-project#188956
Hit "merge" by accident on the wrong tab, juggling too may PRs in
parallel...
[SPIR-V] Support for C++ for OpenCL source language (#188791)
- Add CPP_for_OpenCL source language operand
- Handle opencl.cxx.version metadata
Align handling with SPIR-V translator logic and tests presented there
[CFG] Add shortcut if CycleInfo is available (#188928)
isPotentiallyReachable() currently returns "reachable" early if BB
dominates StopBB. If CycleInfo is available, and BB is not part of a
cycle, we can also perform the reverse inference: Return "not reachable"
if StopBB dominates BB.
This both allows aborting the walk earlier, and provides a more precise
result.
[Hexagon] Add coverage tests for CodeGen passes (#183951)
Add tests targeting specific Hexagon CodeGen passes with low coverage:
- peephole-sxtw-combine.mir: HexagonPeephole pass exercising SXTW
removal, combine generation, and LSR copy patterns. Improves
HexagonPeephole.cpp line coverage from 63.89% to 99.31%.
- vec-print-wq.ll: HexagonVectorPrint pass with V (single vector) and W
(double vector) register printing via 128b HVX. Improves
HexagonVectorPrint.cpp line coverage from 71.19% to 87.29%.
- tfr-cleanup-double-imm.mir: HexagonTfrCleanup pass exercising 64-bit
immediate rewrite paths. Improves HexagonTfrCleanup.cpp line coverage
from 80.85% to 88.30%.
- cfgopt-newpt-invert.ll: HexagonCFGOptimizer pass exercising branch
inversion with new-value predicate transfers.
[Hexagon] Add AP register to liveins when used for frame index access (#188942)
This is a follow-up to commit 3ef59d80c5ce ("[Hexagon] Fix
use-before-def of AP register in prologue CSR spills").
When the AP (alignment pointer) register is used as a base register for
frame index elimination, add it to the basic block's livein set. This
ensures liveness information is accurate for the machine verifier.
The original commit fixed the use-before-def issue by moving PS_aligna
after CSR spills. However, when the prologepilog pass is run in
isolation (as in MIR tests) with expensive checks enabled, the verifier
reports an error because AP is used in blocks where it's not marked as
live-in.
In the full compilation pipeline, the Hexagon Packetizer adds AP as an
implicit operand to instruction bundles, which satisfies the verifier.
However, when running only the prologepilog pass (before packetization),
AP remains an explicit operand and must be in the livein set.
This fix adds AP to liveins when AP is used as the base register,
ensuring correct liveness tracking regardless of whether packetization
has run.
[libunwind][PAC] Defang ptrauth's PC in valid CFI range abort (#184041)
It turns out making the CFI check a release mode abort causes many, if
not the majority, of JITs to fail during unwinding as they do not set up
CFI sections for their generated code. As a result any JITs that do
nominally support unwinding (and catching) through their JIT or assembly
frames trip this abort.
rdar://170862047
[XRay] Always register constructor(0) alongside .preinit_array (#188788)
On musl-based systems the dynamic linker does not process
DT_PREINIT_ARRAY, so the .preinit_array entry alone never calls
__xray_init(). Without initialization, the global XRay Flags struct is
zero-initialized and flags()->xray_mode is NULL. When the basic-mode or
FDR-mode static initializers run from .init_array and call
internal_strcmp(flags()->xray_mode, ...), they dereference NULL and
crash.
Fix this by always registering a constructor(0) in addition to the
.preinit_array entry. On glibc where .preinit_array works, __xray_init()
will have already run and the constructor returns immediately (the
function is idempotent). On musl, the constructor ensures __xray_init()
runs before other .init_array entries that depend on XRay flags being
initialized.
[lldb] Add PlatformWebInspectorWasm (#188751)
Add a new PlatformWebInspectorWasm, which is a Wasm platform that
automatically connects to the WebInspector platform server.
The existing "wasm" platform handles WebAssembly generally and allows
you to configure a runtime to launch under. The "webinspector-wasm"
platform does the inverse, and only supports attaching to an already
running WebAssembly instance in Safari. The workflow here is always
`platform process list` followed by `platform process attach`. This
explains why you can only force create this platform and it's never
automatically selected when loading a Wasm target.
[AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
[lldb][docs] Mention "Python Install Manager" in Windows build instructions (#188728)
It was reported to us that this new install manager does not, and
apparently will not, have an option to install a debug Python. Which we
must have to be able to build lldb in debug mode on Windows.
(because the debug C runtime has a different ABI so everything in the
build must use only that version)
https://discourse.llvm.org/t/pythonx-d-lib-build-requirement/90285/1
Developers will have to use the "Windows installer", or build thier own,
so I've linked to Python's documentation for that.
[AArch64][llvm] Rewrite the TLBI multiclass to be much clearer (NFC)
The `tlbi` multiclass is really doing four jobs at once: base TLBI,
synthesized nXS, optional TLBIP, and synthesized TLBIP nXS. Also,
`needsreg` and `optreg` are really just a 3-state operand policy in
disguise. Likewise, the PLBI multiclass has this same issue.
Change `needsreg` and `optreg` into a combined fake enum, so it's
clearer whether the instruction takes no register operand, a required
register operand or an optional register operand.
This improves on my original change 66e8270e8.
