[LoongArch] Mark VREPLGR2VR/XVREPLGR2VR as re-materializable
The VREPLGR2VR and XVREPLGR2VR instruction families replicate a
scalar general-purpose register value into all elements of a vector
register. These instructions are side-effect free and relatively
cheap, with their result depending only on the input register.
Mark them as isReMaterializable to allow the register allocator to
recompute the value when profitable instead of spilling and reloading
it from memory.
This can help reduce register pressure and avoid unnecessary memory
traffic in vectorized code.
AMDGPU: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3
Codegen for v_dual_dot2acc_f32_f16/bf16 for targets that only have VOP3
version of the instruction.
Since there is no VOP2 version, instroduce temporary mir DOT2ACC pseudo
that is selected when there are no src_modifiers. This DOT2ACC pseudo
has src2 tied to dst (like the VOP2 version), PostRA pseudo expansion will
restore pseudo to VOP3 version of the instruction.
CreateVOPD will recoginize such VOP3 pseudo and generate v_dual_dot2acc.
[lldb] Do not use mkdir -p in makefile on Windows (#187244)
`Make` uses systems's `mkdir` on Windows even if Git's mkdir.exe is
present in PATH. Windows's mkdir does not support the parameter `-p` and
creates the directory `-p` instead. Few other tests also use `mkdir -p`
but they are linux, objc or macosx related.
---------
Co-authored-by: Charles Zablit <c_zablit at apple.com>
[OpenMP] Map const-qualified target map variables as 'to'. (#185918)
This patch updates the mapping kind for const-qualified variables
from`tofrom` to `to`, ensuring correct and standards-compliant mapping
semantics for const variables.
[AArch64][llvm] Make SBZ/SBO insns warn not fail when disassembling (#187068)
Some instructions in the Arm ARM have bits which are marked as "Should
Be One" or "Should Be Zero", and they're marked as "Constrained
Unpredictable" as to what should happen if they're not.
This is to improve hardware decode efficiency. In all the cases where
this occurs, it's an instruction which in all other respects is closely
related to an adjacent instruction in the encoding space (for example a
similar load or store) but doesn't require one of the variable fields,
usually a register field. These fields are then defined as SBZ or SBO.
If one of these instructions didn't have the bits set to SBZ or SBO,
then the instruction would fail to disassemble. We had missed adding
`Unpredictable` to a few of these, and they would fail rather than
warn.
Update these AArch64 instructions to treat `Unpredictable` bitfields as
soft-fails with a warning, and add a comprehensive disassembler
[9 lines not shown]
libclc: Use select function instead of ?: for some fp selects
It seems that ?: is not quite equivalent to select for floating-point
vectors. With ?:, the resulting IR involves integer bitcasts and
integer vector typed select. Use select so this is an fp-select. This
enables finite math only contexts to optimize out the select.
This feels like it's a clang bug though.
[CycleInfo] Use block numbers for dfs numbering (NFC) (#187062)
Store the DFSInfo into a vector indexed by block number instead of a map
using the block pointer.
This is a small compile-time improvement for CycleInfo construction.
[orc-rt] Move CallViaSession into Session, add comments. (#187238)
Makes CallViaSession an inner class on Session, and adds comments and a
convenience method for creating instances.
Services: Kea: DHCPv4/v6: Add single client_class support to DHCP options (#9988)
Enhances the DHCP option MVP introduced in:
https://github.com/opnsense/core/commit/8350fcb73b9dd44e8b1e00d2ea03ced71e0f71achttps://github.com/opnsense/core/commit/b67a8fdc931936f768b3d6a2eea1e179320f257a
An single client_class can be attached to a DHCP option. This client_class contains a test. Right now a single test is possible, matching a DHCP option code, and the payload inside of it. A common example is matching option 93 to send different boot files to different client architectures.
A client_class is optional input, if none is given, the option will always be sent out as before.
[AArch64][llm] Make SBZ/SBO insns warn not fail when disassembling
Some instructions in the Arm ARM have bits which are marked as "Should
Be One" or "Should Be Zero", and they're marked as "Constrained
Unpredictable" as to what should happen if they're not.
This is to improve hardware decode efficiency. In all the cases where
this occurs, it's an instruction which in all other respects is closely
related to an adjacent instruction in the encoding space (for example a
similar load or store) but doesn't require one of the variable fields,
usually a register field. These fields are then defined as SBZ or SBO.
If one of these instructions didn't have the bits set to SBZ or SBO,
then the instruction would fail to disassemble. We had missed adding
`Unpredictable` to a few of these, and they would fail rather than
warn.
Update these AArch64 instructions to treat `Unpredictable` bitfields as
soft-fails with a warning, and add a comprehensive disassembler regression
[9 lines not shown]
