LLVM/project c9d3b8allvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUAsmUtils.cpp

AMDGPU: Add syntax for s_wait_event values

Previously this would just print hex values. Print names for the
recognized values, matching the sp3 syntax.
DeltaFile
+42-3llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+30-0llvm/test/MC/AMDGPU/gfx12_err.s
+27-0llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
+16-10llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
+20-0llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+18-0llvm/test/MC/AMDGPU/gfx11_asm_err.s
+153-138 files not shown
+209-1514 files

LLVM/project fbe1334clang/test/OpenMP task_codegen.cpp threadprivate_codegen.cpp, libc/src/__support/wctype wctype_classification_utils.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,458-2,041clang/test/OpenMP/task_codegen.cpp
+2,140-2,140clang/test/OpenMP/threadprivate_codegen.cpp
+4,100-13llvm/test/CodeGen/AArch64/clmul-fixed.ll
+3,681-0libc/src/__support/wctype/wctype_classification_utils.cpp
+23,221-14,0362,508 files not shown
+137,890-63,1702,514 files

LLVM/project f36e996clang/test/OpenMP task_codegen.cpp threadprivate_codegen.cpp, libc/src/__support/wctype wctype_classification_utils.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,458-2,041clang/test/OpenMP/task_codegen.cpp
+2,140-2,140clang/test/OpenMP/threadprivate_codegen.cpp
+4,100-13llvm/test/CodeGen/AArch64/clmul-fixed.ll
+3,681-0libc/src/__support/wctype/wctype_classification_utils.cpp
+23,221-14,0362,508 files not shown
+137,890-63,1702,514 files

LLVM/project bc17014clang/test/OpenMP task_codegen.cpp threadprivate_codegen.cpp, libc/src/__support/wctype wctype_classification_utils.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,458-2,041clang/test/OpenMP/task_codegen.cpp
+2,140-2,140clang/test/OpenMP/threadprivate_codegen.cpp
+4,100-13llvm/test/CodeGen/AArch64/clmul-fixed.ll
+3,681-0libc/src/__support/wctype/wctype_classification_utils.cpp
+23,221-14,0362,509 files not shown
+137,891-63,1712,515 files

LLVM/project 097a303clang/test/OpenMP task_codegen.cpp threadprivate_codegen.cpp, libc/src/__support/wctype wctype_classification_utils.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,458-2,041clang/test/OpenMP/task_codegen.cpp
+2,140-2,140clang/test/OpenMP/threadprivate_codegen.cpp
+4,100-13llvm/test/CodeGen/AArch64/clmul-fixed.ll
+3,681-0libc/src/__support/wctype/wctype_classification_utils.cpp
+23,221-14,0362,509 files not shown
+137,891-63,1712,515 files

LLVM/project e16f354llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/RISCV abs.ll

[RISCV][TTI] Adjust the cost of `llvm.abs` intrinsic when `Zvabd` exists

When `Zvabd` exists, `llvm.abs` is lowered to `vabs.v` so the cost
is 1.

Reviewers: mshockwave, topperc, lukel97, skachkov-sc, preames

Reviewed By: topperc

Pull Request: https://github.com/llvm/llvm-project/pull/180146
DeltaFile
+36-0llvm/test/Analysis/CostModel/RISCV/abs.ll
+5-0llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+41-02 files

LLVM/project 0c583e7clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaAMDGPU.cpp

AMDGPU: Add llvm.amdgcn.s.wait.event intrinsic (#180170)

Exactly match the s_wait_event instruction. For some reason we already
had this instruction used through llvm.amdgcn.s.wait.event.export.ready,
but that hardcodes a specific value. This should really be a bitmask
that
can combine multiple wait types.

gfx11 -> gfx12 broke compatabilty in a weird way, by inverting the
interpretation of the bit but also shifting the used bit by 1. Simplify
the selection of the old intrinsic by just using the magic number 2,
which should satisfy both cases.
DeltaFile
+42-9llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
+27-0clang/test/SemaOpenCL/builtins-amdgcn-s-wait-event.cl
+24-0clang/lib/Sema/SemaAMDGPU.cpp
+11-0llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+7-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+2-4llvm/lib/Target/AMDGPU/SOPInstructions.td
+113-131 files not shown
+114-137 files

OPNSense/core 49d5736. plist, src/opnsense/mvc/tests/app/library/OPNsense/Firewall FilterRuleTest.php

tests: one more for protocol replacements; closes #9744

The tests aren't complete but they do cover parseReplaceSimple()
in its latest form so that's good enough.

Just as a note the tests are designed to be render-agnostic so
that we always start with our rule input and produce pf.conf
compatible rulesets with the tests.  There are two purposes here:

1. Catch regressions when parsers are changed and that also includes
   switching the parser implementation completely in the future.

2. Make sure that the files are actually compilable by pf.conf and
   this should be covered later (the conf files are there on the
   disk for that purpose).

This is the right type of testing for the purpose since the pf.conf
syntax is virtually static and will require little maintenance.
Just needs a lot more coverage for the missing features/rule types.
DeltaFile
+20-0src/opnsense/mvc/tests/app/library/OPNsense/Firewall/FilterRuleTest.php
+5-0src/opnsense/mvc/tests/app/library/OPNsense/Firewall/FilterRuleTest/testProtocol.conf
+1-0plist
+26-03 files

FreeBSD/src dac3b99. CONTRIBUTING.md

CONTRIBUTING.md: Fix links to section

Signed-off-by: Minsoo Choo <minsoochoo0122 at proton.me>

Sponsored by:   The FreeBSD Foundation
Pull Request:   https://github.com/freebsd/freebsd-src/pull/2010
DeltaFile
+2-2CONTRIBUTING.md
+2-21 files

LLVM/project 700c1c9clang/test/OpenMP task_codegen.cpp threadprivate_codegen.cpp, libc/src/__support/wctype wctype_classification_utils.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,458-2,041clang/test/OpenMP/task_codegen.cpp
+2,140-2,140clang/test/OpenMP/threadprivate_codegen.cpp
+4,100-13llvm/test/CodeGen/AArch64/clmul-fixed.ll
+3,681-0libc/src/__support/wctype/wctype_classification_utils.cpp
+23,221-14,0362,506 files not shown
+137,867-63,1902,512 files

LLVM/project b141939clang/test/OpenMP task_codegen.cpp threadprivate_codegen.cpp, libc/src/__support/wctype wctype_classification_utils.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,458-2,041clang/test/OpenMP/task_codegen.cpp
+2,140-2,140clang/test/OpenMP/threadprivate_codegen.cpp
+4,100-13llvm/test/CodeGen/AArch64/clmul-fixed.ll
+3,681-0libc/src/__support/wctype/wctype_classification_utils.cpp
+23,221-14,0362,506 files not shown
+137,867-63,1902,512 files

LLVM/project fe73774llvm/lib/Target/ARM ARMISelLowering.cpp ARMInstrNEON.td, llvm/test/CodeGen/ARM fp-intrinsics-vector-v8.ll

[ARM] Treat strictfp vector rounding operations as legal

Previously, the strictfp variants of rounding operations (FLOOR, ROUND,
etc) were handled in SelectionDAG via the default expansion, which
splits vector operation into scalar ones. This results in less efficient
code.

This change declares the strictfp counterparts of the vector rounding
operations as legal and modifies existing rules in tablegen descriptions
accordingly.
DeltaFile
+25-40llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll
+20-0llvm/lib/Target/ARM/ARMISelLowering.cpp
+1-16llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll
+6-6llvm/lib/Target/ARM/ARMInstrNEON.td
+6-6llvm/lib/Target/ARM/ARMInstrMVE.td
+58-685 files

LLVM/project 972e73bllvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoZvabd.td, llvm/test/CodeGen/RISCV/rvv abs-vp.ll fixed-vectors-abs-vp.ll

[RISCV][CodeGen] Lower `ISD::ABS` to Zvabd instructions

We add pseudos/patterns for `vabs.v` instruction and handle the
lowering in `RISCVTargetLowering::lowerABS`.

Reviewers: topperc, 4vtomat, mshockwave, preames, lukel97, tclin914

Reviewed By: mshockwave

Pull Request: https://github.com/llvm/llvm-project/pull/180142
DeltaFile
+319-0llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+247-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+107-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+94-0llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
+16-10llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+26-0llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+809-103 files not shown
+833-389 files

LLVM/project 3b76dabllvm/unittests/CodeGen MFCommon.inc

BogusTargetmachine comment

Created using spr 1.3.5-bogner
DeltaFile
+3-3llvm/unittests/CodeGen/MFCommon.inc
+3-31 files

FreeBSD/ports 8845ac3www/gohugo distinfo Makefile

www/gohugo: Update to 0.155.3

ChangeLog: https://github.com/gohugoio/hugo/releases/tag/v0.155.3

 * hugolib: Don't render default site redirect for non-primary isHTML output
   formats
 * server: Fix stuck server global error logging
 * build(deps): bump github.com/evanw/esbuild from 0.27.2 to 0.27.3
 * server: Fix panic when the server browser error handler tried to use a config
   in a state of flux

Approved by:    doceng@ (implicit)
DeltaFile
+5-5www/gohugo/distinfo
+1-2www/gohugo/Makefile
+6-72 files

LLVM/project aa80896clang/include/clang/Sema Sema.h, clang/lib/Sema SemaType.cpp SemaDeclAttr.cpp

[Clang][HIP][CUDA] Validate that variable type fits in address spaces (#178909)

Currently, Clang only checks arrays and structures for size at a
top-level view, that is it does not consider whether they will fit in
the address space when applying the address space attribute. This can
lead to situations where a variable is declared in an address space but
its type is too large to fit in that address space, leading to
potentially invalid modules.

This patch proposes a fix for this by checking the size of the type
against the maximum size that can be addressed in the given address
space when applying the address space attribute.

This does not currently handle instantiations of dependent variables, as
the attributes are not re-processesd at that time. This is planned for
further investigation and a follow-up patch.

---------

Signed-off-by: Steffen Holst Larsen <HolstLarsen.Steffen at amd.com>
Co-authored-by: Steffen Holst Larsen <HolstLarsen.Steffen at amd.com>
DeltaFile
+23-0clang/test/SemaHIP/shared-variable-too-large.hip
+18-0clang/lib/Sema/SemaType.cpp
+13-0clang/test/SemaOpenCL/amdgpu-variables-too-large-for-address-space.cl
+11-0clang/include/clang/Sema/Sema.h
+8-0clang/lib/Sema/SemaDeclAttr.cpp
+6-0clang/lib/Sema/SemaDecl.cpp
+79-02 files not shown
+84-18 files

LLVM/project e992593llvm/lib/Target/RISCV RISCVInstrInfoVVLPatterns.td RISCVInstrInfoZvabd.td, llvm/test/CodeGen/RISCV/rvv fixed-vectors-abd.ll abd.ll

[RISCV][CodeGen] Lower `abds`/`abdu` to `Zvabd` instructions

We directly lower `ISD::ABDS`/`ISD::ABDU` to `Zvabd` instructions.

Note that we only support SEW=8/16 for `vabd.vv`/`vabdu.vv`.

Reviewers: mshockwave, lukel97, topperc, preames, tclin914, 4vtomat

Reviewed By: lukel97, topperc

Pull Request: https://github.com/llvm/llvm-project/pull/180141
DeltaFile
+312-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+156-0llvm/test/CodeGen/RISCV/rvv/abd.ll
+83-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+21-11llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+29-0llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+19-10llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+620-212 files not shown
+650-308 files

FreeBSD/ports 3b69c21security/vuxml/vuln 2026.xml

security/vuxml: add www/*chromium < 144.0.7559.132

Obtained from:  https://chromereleases.googleblog.com/2026/02/stable-channel-update-for-desktop.html
DeltaFile
+34-0security/vuxml/vuln/2026.xml
+34-01 files

NetBSD/pkgsrc qK8RIkBnet/speedtouch Makefile

   speedtouch: switch to sourceforge HOMEPAGE, other one is gone
VersionDeltaFile
1.33+2-2net/speedtouch/Makefile
+2-21 files

NetBSD/pkgsrc AwIAEMUx11/space_dapp Makefile

   space_dapp: comment out dead link
VersionDeltaFile
1.8+2-2x11/space_dapp/Makefile
+2-21 files

NetBSD/pkgsrc H1jqaGugames/solarus Makefile

   solarus: update HOMEPAGE
VersionDeltaFile
1.83+2-2games/solarus/Makefile
+2-21 files

NetBSD/pkgsrc sygFgQdwww/SOGo Makefile, www/SOGo5 Makefile

   SOGo*: switch to https
VersionDeltaFile
1.88+2-3www/SOGo/Makefile
1.8+2-2www/SOGo5/Makefile
+4-52 files

NetBSD/pkgsrc 6I9scBqsecurity/softhsm Makefile

   softhsm: update HOMEPAGE
VersionDeltaFile
1.62+2-2security/softhsm/Makefile
+2-21 files

NetBSD/pkgsrc z21sxm1security/softhsm2 Makefile

   softhsm2: update HOMEPAGE
VersionDeltaFile
1.35+2-2security/softhsm2/Makefile
+2-21 files

HardenedBSD/src f0037f2sys/amd64/include pcb.h, sys/arm/include pcb.h

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+11-10sys/amd64/include/pcb.h
+9-8sys/i386/include/pcb.h
+5-0sys/arm64/include/pcb.h
+5-0sys/powerpc/include/pcb.h
+5-0sys/riscv/include/pcb.h
+4-0sys/arm/include/pcb.h
+39-181 files not shown
+40-187 files

NetBSD/pkgsrc CYF6s7vwww/snownews Makefile

   snownews: update HOMEPAGE
VersionDeltaFile
1.85+3-3www/snownews/Makefile
+3-31 files

NetBSD/pkgsrc kn9w3Clsecurity/snortsnarf Makefile

   snortsnarf: comment out dead sites
VersionDeltaFile
1.32+3-4security/snortsnarf/Makefile
+3-41 files

NetBSD/pkgsrc p4SZ1ahmath/snns Makefile

   snns: comment out dead site
VersionDeltaFile
1.28+3-3math/snns/Makefile
+3-31 files

HardenedBSD/ports f6309a0Mk/Uses inotify.mk, audio/libvgm distinfo

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+34-0Mk/Uses/inotify.mk
+11-7audio/vgmplay/Makefile
+6-9net-im/libnice/Makefile
+0-11audio/vgmplay/files/patch-main.cpp
+3-3audio/libvgm/distinfo
+3-3audio/vgmplay/distinfo
+57-3316 files not shown
+89-6822 files

FreeBSD/src f418e65sys/dev/ice if_ice_iflib.c

ice(4): Handle allmulti flag in ice_if_promisc_set function

In the ice_if_promisc_set function, the driver currently disables the
IFF_ALLMULTI flag, thereby preventing the activation of multicast mode.
To address this issue, implement appropriate handling to ensure the
flag is managed correctly.

Signed-off-by: Yogesh Bhosale <yogesh.bhosale at intel.com>

Tested by:      Gowthamkumar K S <gowtham.kumar.ks at intel.com>
Differential Revision:  https://reviews.freebsd.org/D54186

(cherry picked from commit 98bdf63f6e94be42a1787de73608de15bcb3419a)
DeltaFile
+20-5sys/dev/ice/if_ice_iflib.c
+20-51 files