[SandboxVec][Scheduler] Reinsert deferred ready nodes to the ready list (#222054)
Up until now if trySchedule() failed, the ready instructions would be
removed from the ready list for no good reason.
This patch fixes this and reinserts the deferred nodes to the ready
list.
This also helps reduce the scan for ready instructions in trySchedule().
[Clang][Sema] Promote pointers to common address space in pointer subtraction (#217341)
fixes #216804
## Summary
This PR fixes pointer subtraction between pointers with different but
overlapping address spaces (e.g., `private` and `generic` in
OpenCL).
Previously, when subtracting a private pointer from a generic pointer on
AMDGPU:
- The private pointer (AS5, 32-bit) was converted directly to i32 via
`ptrtoaddr`
- The generic pointer (AS0, 64-bit) was converted to i64 via `ptrtoaddr`
- This resulted in incorrect comparison of 32-bit vs 64-bit values
Now, pointers are first promoted to the composite (superset) address
space using `addrspacecast` before the subtraction. This
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[MLIR][Transform] Enable strict property assembly format (#217290)
Enable strict property assembly format mode for the Transform dialect
and its extensions. Bind transform operation options directly in
declarative assembly formats so strict parsing does not rely on fallback
handling.
Update transform dialect, extension, and transform-driven tests to use
the direct property spelling.
Assisted-by: Codex
[VPlan] Add helper to add incoming values for last predecessor (NFC). (#222149)
Factor logic to helper function, so it can be re-used in follow-up
changes.
[VPlan] Collect predecessors/successors up front (NFC) (#222145)
Collect predecessors and successors up front in reassociateBlocks.
Currently NFC, but makes it more robust in the future, because it also
correctly handles self-edges.
[libc][bazel] Add a repo with linux kernel UAPI headers
This will be used to support libc's -DFULL_BUILD option, which uses `-nostdlibinc` and thus requires a copy of linux kernel headers.
[libc][bazel] Allow building with -DLIBC_FULL_BUILD
This PR defines a flag `--@llvm-project//libc:build_mode` that configures LLVM-libc to build with full-build flags. This is only compatible with clang at the moment, since it relies on the `-nostdlibinc` flag.
[OpenMP] [MLIR] [Flang] Replace all uses of variables in ALLOCATE directive to use new value which is created. (#212361)
Limitation:
Right now, added a TODO warning about lowering of variable with SAVE
attribute or named COMMON block are not completely supported end to end.
So a warning is emitted.
[AMDGPU] Update no-modifier operand tests for the dropped align diagnostic
The no-modifier reg-or-inline operands routed through the HwMode
predicate now report a misaligned tuple as a plain invalid operand,
matching the diagnostic dropped earlier in the stack.
[AMDGPU] Route no-modifier reg-or-inline AsmParser operands through HwMode predicate
Convert the reg-or-inline operands with no modifiers (MFMA VGPR/AGPR
sources, VCSrc, v_pk_mov_b32, VOP scalar f64) from the fixed-class
isRegOrInlineNoMods to the HwMode-aware isRegOrInlineNoModsByHwMode, so an
odd-aligned tuple is rejected at the offending operand column instead of by
the validateVGPRAlign catch-all.
Co-Authored-By: Claude <noreply at anthropic.com>
[AMDGPU] Drop the misaligned VGPR-tuple AsmParser diagnostic
The alignment-aware matchers already reject a misaligned tuple, so a
misaligned operand now fails as a plain invalid operand. Keeping the
dedicated "vgpr tuples must be 64 bit aligned" message only for that
case is not worth the extra match-error ranking, the per-operand
diagnostic, and getUnalignedEquivalentRC, so remove all of it.
[AMDGPU] Make custom AsmParser matchers alignment aware
Currently custom matchers accept registers belonging to unaligned classes,
leaving the alignment check and its diagnostic to validateVGPRAlign. The problem
is that validateVGPRAlign does not account for the operand register class, which
may have a different alignment requirement on mixed-alignment targets.
The fix is to make a custom matcher resolve the operand's _AlignTarget class via
HwMode and use that resolved class to accept a register. However, doing so alone
would reject a misaligned register with a generic "invalid operand for
instruction" diagnostic, so extra infrastructure conveys the alignment diagnostic
instead: on a class miss, diagnoseRegAlign re-checks the register against the same
class with alignment relaxed (getUnalignedEquivalentRC, new in AMDGPUBaseInfo);
if it fits, the only problem is alignment, so it records
OperandMatchError::VGPRAlignMismatch on the operand. matchAndEmitInstruction
selects that reason and prints the alignment error, now at the offending operand
column instead of column 1.
This commit converts the input-mods and DP-ALU DPP matchers. The no-modifier
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[AMDGPU] Factor the AsmParser match-specificity comparison into a helper, NFC (#221987)
Extract the "keep the most specific match status" comparison in
matchAndEmitInstruction into an atLeastAsSpecific() lambda ranking
Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature. No
functional change.
