[clang] Match MSVC ABI for over-aligned base tail padding on Arm64 (#210461)
When targeting aarch64-pc-windows-msvc, clang laid out a base following
an over-aligned, non-standard-layout base at the wrong offset. MSVC on
Arm64 reuses the over-aligned base's tail padding for the subsequent
base, but clang rounded the base up to a full slot, so the two disagreed
on member offsets, breaking interop between clang- and MSVC-built
binaries.
Fix: store each record's natural non-virtual alignment (excluding
`alignas`/`__declspec(align)` over-alignment) as
`getNonRequiredNVAlignment()`, and on Arm64 fold in a base's natural
alignment rather than its full alignment. This is gated to Arm64 only;
Arm64EC and x64 follow the x64 rule (no reuse) and are unchanged.
Validated against MSVC (Hostx64\arm64\cl.exe
/d1reportSingleClassLayout): clang now matches MSVC Arm64 exactly for
the reduced repro, the original polymorphic case (vftable + empty base +
template), and a range of probe cases covering natural vs.
[3 lines not shown]
[clang] Add __builtin_convert_to_arbitrary_fp
Expose the llvm.convert.to.arbitrary.fp intrinsic as a target-independent
builtin, the inverse of __builtin_convert_from_arbitrary_fp:
unsigned _BitInt(8) b =
__builtin_convert_to_arbitrary_fp(f, "Float8E4M3FN", "round.tonearest", 1);
The result type is derived from the format, so unlike the "from" direction this
is an ordinary CustomTypeChecking builtin with no parser or AST support needed.
It is unsigned _BitInt(N) for a scalar operand and an ext_vector_type of that
for a vector operand.
The rounding mode is a string literal validated with convertStrToRoundingMode,
matching what the IR verifier accepts, and the saturation flag must be an
integer constant expression equal to 0 or 1 since the intrinsic marks it ImmArg.
Clang only permits _BitInt vector elements of power-of-two width, so vector
operands are rejected for the 6-bit formats.
[3 lines not shown]
[HashRecognize] Use loop latch to determine step/start for conditional recurrence (#211916)
The function `matchConditionalRecurrence` iterates over both PHI inputs
and attempts to match each one to determine which is `Start` and which
is `Step`. However, some of the failure conditions in the loop `return
false`, which has the potential to classify some valid CRC loops as not
having a conditional recurrence. The loop here is not really needed at
all-- instead, use `L.getLoopLatch()` to determine `Start`/`Step`, since
the incoming value from the latch block will always be the `Step`. This
also avoids the aforementioned false negative classifications.
Assisted-by: Claude Opus 5
Outline widenUnitStridedLoadStore helper
Reuses it for both normal and speculative unit-strided memaccesses widening.
Apparently, I misread `createVectorPointer` interface (or maybe it changed
throughout the life of this PR), so this also fixes a bug in the new code.
[AMDGPU][GISel] Remove redundant AND on scalar shift amounts
A scalar shift only consumes the low log2(bitwidth) bits of its amount,
so an explicit (and amt, mask) feeding the amount is redundant whenever
mask has all of those low bits set. SelectionDAG already achieves this
via SimplifyDemandedBits on the shift-amount operand; this adds the
equivalent to the postlegalizer combiner for G_SHL/G_LSHR/G_ASHR.
Co-authored-by: Cursor <cursoragent at cursor.com>
