LLVM/project 9dc6b49llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp GCNSchedStrategy.h, llvm/test/CodeGen/AMDGPU sched_mfma_rewrite_copies.mir machine-scheduler-rematerialization-scoring.mir

Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#177206)

This re-applies commit f21e3593371c049380f056a539a1601a843df558 along
with the compile fix failure introduced in
8ab79377740789f6a34fc6f04ee321a39ab73724 before the initial patch was
reverted. It also fixes for the previously observed assert failure.

We were hitting the assert in the HIP Blender due to a combination of
two issues that could happen when rematerializations are being rolled
back.

1. Small changes in slots indices (while preserving instruction order)
compared to the pre-re-scheduling state means that we have to re-compute
live ranges for all register operands of rolled back rematerializations.
This was not being done before.
2. Re-scheduling can move registers that were rematerialized at
arbitrary positions in their respective regions while their opcode is
set to DBG_VALUE, even before their read operands are defined. This
makes re-scheduling reverts mandatory before rolling back

    [3 lines not shown]
DeltaFile
+949-949llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
+519-291llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+523-0llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
+194-194llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
+238-31llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
+210-51llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+2,633-1,5163 files not shown
+2,716-1,5999 files

LLVM/project fd146bellvm/test/Transforms/InstCombine bitcast-select-const-vector.ll

Add negative vselect test
DeltaFile
+15-0llvm/test/Transforms/InstCombine/bitcast-select-const-vector.ll
+15-01 files

LLVM/project 1bc655fllvm/test/CodeGen/ARM cls.ll

[ARM] Expand and regenerate llvm/test/CodeGen/ARM/cls.ll. NFC
DeltaFile
+128-17llvm/test/CodeGen/ARM/cls.ll
+128-171 files

FreeBSD/ports 74c9669textproc/py-grep-ast distinfo Makefile

textproc/py-grep-ast: update to 0.9.0
DeltaFile
+3-3textproc/py-grep-ast/distinfo
+1-1textproc/py-grep-ast/Makefile
+4-42 files

FreeBSD/ports b29c3a4databases/pg_textsearch pkg-plist

databases/pg_textsearch: fix pkg-plist

Fixes:  7064bf03ddba269dc3dc136f438663df3558c470

Approved by:    blanket (fix trivial build failures)
DeltaFile
+1-1databases/pg_textsearch/pkg-plist
+1-11 files

LLVM/project a37a67dclang/test/AST/ByteCode floats.cpp

[clang][bytecode][NFC] Clean up floats.cpp test (#179200)

Use the `both` verify prefix like we do in other tests these days.
DeltaFile
+18-34clang/test/AST/ByteCode/floats.cpp
+18-341 files

LLVM/project 93418b4clang/include/clang/AST HLSLResource.h

HLSLResource.h - fix MSVC "not all control paths return a value" warning. NFC. (#179203)

DeltaFile
+1-0clang/include/clang/AST/HLSLResource.h
+1-01 files

LLVM/project 9e97f0bllvm/test/CodeGen/SPIRV event-zero-const-64.ll event-zero-const.ll, llvm/test/CodeGen/SPIRV/transcoding spirv-event-null-64.ll OpGroupAsyncCopy-strided.ll

[SPIRV] Split async copy tests and fix invalid tests (#178718)

Some tests started failing recently because `spirv-val` now considers
their output invalid. This is likely due to an update in `spirv-val`.
I'm not familiar with what the tests are doing but here is my attempt to
fix them. At the LLVM-IR level, tests had for example incorrect
`addresspace` for certain arguments. To fix them, I used as a reference
some of the tests in the SPIRV-LLVM translator. The goal of the PR is
just to fix the tests in case they had incorrect IR.
DeltaFile
+101-0llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null-64.ll
+27-26llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided.ll
+28-25llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
+37-0llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided-64.ll
+27-0llvm/test/CodeGen/SPIRV/event-zero-const-64.ll
+6-6llvm/test/CodeGen/SPIRV/event-zero-const.ll
+226-576 files

LLVM/project fc6ad39llvm/include/llvm/AsmParser AsmParserContext.h LLParser.h, llvm/lib/AsmParser AsmParserContext.cpp LLParser.cpp

[AsmParser] Track value references and function arguments (#174566)

This PR is part of the LLVM IR LSP server project:
https://discourse.llvm.org/t/rfc-ir-visualization-with-vs-code-extension-using-an-lsp-server/87773

To be able to implement goto definition in LSP. One must first have to
know what values are referenced on what positions.
This PR implements a Location -> Value* map that allows looking up
values referenced on queried locations.

For example
```llvm
%inst = add i32 1, %arg
```
Querying on 0:20 (the location of %arg) would return the Value* of the
`%arg`.

`getInstuctionLocation(%arg)` would still return the definition of that
value

    [4 lines not shown]
DeltaFile
+34-12llvm/lib/AsmParser/AsmParserContext.cpp
+25-12llvm/include/llvm/AsmParser/AsmParserContext.h
+25-6llvm/unittests/AsmParser/AsmParserTest.cpp
+24-6llvm/lib/AsmParser/LLParser.cpp
+4-2llvm/include/llvm/AsmParser/LLParser.h
+112-385 files

LLVM/project 8e18cdcmlir/include/mlir/Dialect/X86Vector X86Vector.td, mlir/lib/Dialect/X86Vector/Transforms VectorContractToPackedTypeDotProduct.cpp

[mlir][x86vector] AVX10 I8 Dot Op (#178807)

Adds AVX10 i8 dot-product operation and defines lowering to LLVM
intrinsics.

Target assembly instruction: `llvm.x86.avx10.vpdpbssd.512`
DeltaFile
+72-2mlir/test/Dialect/X86Vector/vector-contract-to-packed-type-dotproduct.mlir
+52-0mlir/include/mlir/Dialect/X86Vector/X86Vector.td
+29-10mlir/lib/Dialect/X86Vector/Transforms/VectorContractToPackedTypeDotProduct.cpp
+8-0mlir/test/Target/LLVMIR/x86vector.mlir
+8-0mlir/test/Dialect/X86Vector/roundtrip.mlir
+8-0mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir
+177-126 files

LLVM/project aee5fa1clang-tools-extra/clang-tidy/modernize UseStructuredBindingCheck.cpp

UseStructuredBindingCheck.cpp - fix MSVC "not all control paths return a value" warning. NFC. (#179206)

DeltaFile
+1-0clang-tools-extra/clang-tidy/modernize/UseStructuredBindingCheck.cpp
+1-01 files

LLVM/project d591a4cllvm/lib/Transforms/InstCombine InstCombineCasts.cpp, llvm/test/Transforms/InstCombine bitcast-select-const-vector.ll copysign.ll

InstCombine: Fold bitcast of vector with constant to scalar

Fold bitcast (select cond, val, const) ->
  select cond, (bitcast val), (bitcast const)

Rocm device libs has an unfortunate amount of code that does bithacking
on the sign bit of double values by casting to <2 x i32> and operation
on the high element. This breaks value tracking optimizations on the
fp value.

The existing transform would only do this if the input to the select was
also a bitcast with a single use, and if it didn't convert between vector
and scalar.
DeltaFile
+58-0llvm/test/Transforms/InstCombine/bitcast-select-const-vector.ll
+8-1llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+3-4llvm/test/Transforms/InstCombine/copysign.ll
+3-3llvm/test/Transforms/InstCombine/fold-bin-operand.ll
+72-84 files

FreeBSD/ports e6a0a2fdevel/radicle Makefile distinfo

devel/radicle: Update to 1.6.1
DeltaFile
+3-4devel/radicle/Makefile
+3-3devel/radicle/distinfo
+6-72 files

OPNSense/core fe53eaesrc/opnsense/mvc/app/views/OPNsense/Firewall onat_rule.volt snat_rule.volt

firewall: Change toggle_log icon to help visibility of enabled/disabled status
DeltaFile
+10-3src/opnsense/mvc/app/views/OPNsense/Firewall/onat_rule.volt
+10-3src/opnsense/mvc/app/views/OPNsense/Firewall/snat_rule.volt
+10-3src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+10-3src/opnsense/mvc/app/views/OPNsense/Firewall/dnat_rule.volt
+10-3src/opnsense/mvc/app/views/OPNsense/Firewall/npt_rule.volt
+50-155 files

NetBSD/pkgsrc-wip adee2cf. Makefile, py-weboob PLIST Makefile

py-weboob: Remove, now it is py-woob
DeltaFile
+0-975py-weboob/PLIST
+0-29py-weboob/Makefile
+0-22py-weboob/patches/patch-setup.py
+0-5py-weboob/distinfo
+0-3py-weboob/DESCR
+0-1Makefile
+0-1,0356 files

NetBSD/pkgsrc-wip 8f42852. Makefile

wip: Add py-woob
DeltaFile
+1-0Makefile
+1-01 files

NetBSD/pkgsrc-wip 1b6f8b2py-woob PLIST Makefile

py-woob: import py-woob-3.7 as wip/py-woob

woob is a collection of applications able to interact with websites,
without requiring the user to open them in a browser.
It also provides well-defined APIs to talk to websites lacking one.
DeltaFile
+712-0py-woob/PLIST
+32-0py-woob/Makefile
+7-0py-woob/distinfo
+3-0py-woob/DESCR
+1-0py-woob/ALTERNATIVES
+755-05 files

LLVM/project fd1e37bllvm/include/llvm/IR BasicBlock.h, llvm/include/llvm/Transforms/Utils BasicBlockUtils.h

[IR] Remove Before argument from splitBlock APIs (NFC) (#179195)

We never need to use this conditionally (and it doesn't really make
sense, as the behavior is substantially different). Force the use of
separate APIs instead of a boolean argument.
DeltaFile
+12-17llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
+9-20llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+3-8llvm/include/llvm/IR/BasicBlock.h
+4-4llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+1-5llvm/lib/IR/BasicBlock.cpp
+1-2llvm/lib/CodeGen/CodeGenPrepare.cpp
+30-562 files not shown
+32-588 files

LLVM/project 9d5a42cllvm/lib/Target/X86/GISel X86PostLegalizerCombiner.cpp, llvm/test/CodeGen/X86 isel-icmp.ll isel-fpclass.ll

[X86][GISEL] Enable PostLegalize Combiner (#174696)

This patch adds post legalize combiner for X86 Target.

Use case for OptNone Combine: I am curious about OptNone usecase,
specifically when we are using -On on command line and no opt on
specific function.
DeltaFile
+187-0llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
+41-46llvm/test/CodeGen/X86/isel-icmp.ll
+14-39llvm/test/CodeGen/X86/isel-fpclass.ll
+14-18llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
+5-20llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll
+6-18llvm/test/CodeGen/X86/finite-libcalls.ll
+267-14125 files not shown
+315-22231 files

LLVM/project f4a8f30llvm/include/llvm/Transforms/Utils CodeExtractor.h

[CodeExtractor] Format CodeExtractor header, NFC (#178662)

This patch applies clang-format to the CodeExtractor header and updates
usage of the LLVM_ABI macro to prevent unrelated patches touching this
file from having to make these changes in order to pass pre-merge
checks.
DeltaFile
+217-227llvm/include/llvm/Transforms/Utils/CodeExtractor.h
+217-2271 files

OPNSense/core a52277csrc/opnsense/mvc/app/library/OPNsense/Core Shell.php

mvc: shield exec_safe() against "fatal" type errors

Allows the system to boot in the worst case and replaces the
command with a simple dummy command.

Formatters are still a work in progress as I'm not sure how
much preprocessing we should add here to fish for vsprintf()
doing type casts to int/float which is not something the command
line can/should support.

(cherry picked from commit d31faf7f7c9ca0bd461628b0d25a9e301cf9c989)
DeltaFile
+10-1src/opnsense/mvc/app/library/OPNsense/Core/Shell.php
+10-11 files

NetBSD/pkgsrc HW3sevGdoc CHANGES-2026

   Updated security/sqlmap, misc/py-tqdm
VersionDeltaFile
1.832+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc hf4X7kkmisc/py-tqdm distinfo PLIST

   py-tqdm: updated to 4.67.2

   4.67.2

   support pandas>=3
   fix format_interval for negative numbers
   misc linting
   framework updates
   bump CI workflow & pre-commit dependencies
   add pyupgrade
   add py3.13 support
   fix py3.7 tests
   update setuptools-scm usage
   support auto-dedented docstring when building docs in py3.13
   tests: relax flaky benchmarks
VersionDeltaFile
1.46+4-4misc/py-tqdm/distinfo
1.18+1-4misc/py-tqdm/PLIST
1.54+2-3misc/py-tqdm/Makefile
+7-113 files

NetBSD/pkgsrc HXstqTEsecurity/sqlmap PLIST distinfo

   sqlmap: updated to 1.10.2

   1.10.2
   Unknown changes
VersionDeltaFile
1.20+28-11security/sqlmap/PLIST
1.28+4-4security/sqlmap/distinfo
1.43+2-2security/sqlmap/Makefile
+34-173 files

LLVM/project f84c367mlir/include/mlir/Transforms RegionUtils.h, mlir/lib/Transforms/Utils RegionUtils.cpp

[mlir] Extend moveValueDefinitions/moveOperationDependencies with cross-region support (#176343)

Extends `moveValueDefinitions` and `moveOperationDependencies` to
support moving operations across basic blocks and out of nested regions
DeltaFile
+239-20mlir/test/Transforms/move-operation-deps.mlir
+126-18mlir/lib/Transforms/Utils/RegionUtils.cpp
+25-10mlir/include/mlir/Transforms/RegionUtils.h
+390-483 files

NetBSD/pkgsrc 20CyHy5doc CHANGES-2026

   Updated devel/py-poetry[-core]
VersionDeltaFile
1.831+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc CfMmtrtdevel/py-poetry Makefile distinfo

   py-poetry: updated to 2.3.2

   2.3.2
   Allow dulwich>=1.0

   2.3.1
   Fix an issue where cached information about each package was always considered outdated
VersionDeltaFile
1.31+6-5devel/py-poetry/Makefile
1.21+4-4devel/py-poetry/distinfo
+10-92 files

NetBSD/pkgsrc tFiQCPMdevel/py-poetry-core distinfo Makefile

   py-poetry-core: updated to 2.3.1

   2.3.1

   Fix an issue where platform_release could not be parsed on Windows Server
VersionDeltaFile
1.17+4-4devel/py-poetry-core/distinfo
1.20+2-2devel/py-poetry-core/Makefile
+6-62 files

OPNSense/core 9aaf675src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms dialogFilterRule.xml, src/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Firewall: Rules [new]: Statistics column is responsive now (#9679)

DeltaFile
+13-9src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+0-1src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogFilterRule.xml
+13-102 files

NetBSD/pkgsrc iaVBodUdoc CHANGES-2026

   Updated devel/py-babel, devel/py-blessed
VersionDeltaFile
1.830+3-1doc/CHANGES-2026
+3-11 files