LLVM/project ad91a2allvm/test/CodeGen/AMDGPU global_atomics_scan_fadd.ll global_atomics_scan_fsub.ll

[AMDGPU] Port Atomic-Optimizer to use Wave Reduction Intrinsics

Currently the atomic optimizer creates reductions via
intrinsics, and introduces new control flows.
Replace this sub-target dependent logic with existing
wave reduction intrinsics, which get lowered in the
backend.
This patch ports the uniform-value and divergent-no-return-value cases.
DeltaFile
+4,817-5,225llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+4,559-5,011llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,783-2,031llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+1,783-2,031llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+1,574-1,389llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+1,300-1,161llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+15,816-16,84821 files not shown
+19,142-20,50227 files

LLVM/project 2f20e46llvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.cpp LoongArchAsmBackend.h, llvm/test/MC/LoongArch/Relocations sub-expr.s

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+19-19llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+7-0llvm/test/MC/LoongArch/Relocations/sub-expr.s
+1-1llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+27-203 files

LLVM/project 21c03b9llvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.cpp LoongArchAsmBackend.h

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+19-19llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+1-1llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+20-202 files

LLVM/project 905ec41llvm/lib/Target/SPIRV SPIRVStructurizer.cpp

[NFC][SPIR-V] Remove unused LoopInfo member from structurizer splitter (#211538)

Splitter never used its LoopInfo reference

Based on the discussion in
https://github.com/llvm/llvm-project/pull/211198
DeltaFile
+2-3llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
+2-31 files

LLVM/project fd14ad5llvm/lib/Target/SPIRV SPIRVStructurizer.cpp SPIRVUtils.h

[NFC][SPIR-V] Reuse PartialOrderingVisitor DominatorTree in structurizer splitter (#211544)

Based on the discussion in
https://github.com/llvm/llvm-project/pull/211198
DeltaFile
+8-1llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
+4-0llvm/lib/Target/SPIRV/SPIRVUtils.h
+12-12 files

LLVM/project 7f9206allvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.cpp LoongArchAsmBackend.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+19-19llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+1-1llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+20-202 files

LLVM/project 2ae7310llvm/lib/Target/AMDGPU MIMGInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.image.atomic.flt.ll

[AMDGPU] Add image_atomic_{min,max}_num_flt support to gfx13 (#211564)

GFX13 uses the num_flt suffix as the default assembler name for the
32-bit FP image atomic min/max instructions. Keep flt as a
backward-compatible alias. GFX12 is unchanged (flt default, num_flt
alias).

---------

Co-authored-by: Petar Avramovic <Petar.Avramovic at amd.com>
DeltaFile
+54-0llvm/test/MC/AMDGPU/gfx13_asm_vimage.s
+26-14llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
+27-10llvm/lib/Target/AMDGPU/MIMGInstructions.td
+6-0llvm/test/MC/AMDGPU/gfx13_asm_vimage_alias.s
+113-244 files

LLVM/project cc22185llvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.cpp LoongArchAsmBackend.h, llvm/test/MC/LoongArch/Relocations sub-expr.s

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+19-19llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+7-0llvm/test/MC/LoongArch/Relocations/sub-expr.s
+1-1llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+27-203 files

LLVM/project a574b6allvm/lib/Target/LoongArch/MCTargetDesc LoongArchAsmBackend.cpp LoongArchAsmBackend.h, llvm/test/MC/LoongArch/Relocations sub-expr.s

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+36-39llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+5-0llvm/test/MC/LoongArch/Relocations/sub-expr.s
+1-1llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
+42-403 files

LLVM/project 5b355dallvm/docs AMDGPUUsage.rst

Update docs
DeltaFile
+20-13llvm/docs/AMDGPUUsage.rst
+20-131 files

LLVM/project 5362e8dllvm/lib/Target/AMDGPU SIDefines.h AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll

Comments
DeltaFile
+4-3llvm/lib/Target/AMDGPU/SIDefines.h
+1-3llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+9-106 files

LLVM/project 58b385bllvm/docs AMDGPUUsage.rst

Comments
DeltaFile
+1-1llvm/docs/AMDGPUUsage.rst
+1-11 files

LLVM/project 6285d9ellvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp

[AMDGPU] Add synthetic apertures and use them for barriers

Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
DeltaFile
+72-87llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+44-5llvm/docs/AMDGPUUsage.rst
+21-23llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+18-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-0llvm/lib/Target/AMDGPU/SIDefines.h
+9-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+176-1324 files not shown
+186-13710 files

LLVM/project 505366fllvm/lib/Target/AMDGPU AMDGPUMachineFunctionInfo.cpp, llvm/test/CodeGen/AMDGPU null-named-barrier-gv.ll s-barrier-lowering-bad-absolute-symbol.ll

comments
DeltaFile
+18-18llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+8-4llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
+1-1llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
+1-1llvm/test/CodeGen/AMDGPU/s-barrier-lowering-bad-absolute-symbol.ll
+28-244 files

OPNSense/core 4a20d0bsrc/www system_advanced_admin.php system_advanced_firewall.php

system: replace login/sysctl restart for #9352
DeltaFile
+1-1src/www/system_advanced_admin.php
+1-1src/www/system_advanced_firewall.php
+2-22 files

LLVM/project a00f27dllvm/lib/CodeGen MachineSink.cpp, llvm/test/CodeGen/AMDGPU machine-sink-cycle.mir

[MachineSink] Use RegisterClassInfo::getRegPressureSetLimit (#211746)

I think this part was missed in #210826.
DeltaFile
+106-294llvm/test/CodeGen/AMDGPU/machine-sink-cycle.mir
+1-2llvm/lib/CodeGen/MachineSink.cpp
+107-2962 files

OpenBSD/src 3qq2E0eusr.bin/tmux screen-redraw.c

   Replace outside as well as empty cells with the border.
VersionDeltaFile
1.157+3-2usr.bin/tmux/screen-redraw.c
+3-21 files

OPNSense/plugins 9a12b0fnet/isc-dhcp/src/www services_dhcp.php services_dhcpv6.php

net/isc-dhcp: switch to backend resolver reload

PR: https://github.com/opnsense/core/issues/9352
DeltaFile
+1-1net/isc-dhcp/src/www/services_dhcp.php
+1-1net/isc-dhcp/src/www/services_dhcpv6.php
+2-22 files

OPNSense/core 035c571src/www services_opendns.php system_advanced_admin.php

system: switch resolver reload for #9352
DeltaFile
+1-1src/www/services_opendns.php
+1-1src/www/system_advanced_admin.php
+1-1src/www/system_advanced_misc.php
+1-1src/www/system_general.php
+4-44 files

LLVM/project debd8a7llvm/lib/Target/AArch64 AArch64Subtarget.h, llvm/test/CodeGen/AArch64 aarch64-no-mov-spill-chain.ll ragreedy-local-interval-cost.ll

Revert "[AArch64] Enable Spillage Copy Elimination by default" (#211572)

Reverts llvm/llvm-project#186093

Issue https://github.com/llvm/llvm-project/issues/206839 shows that
EliminateSpillageCopies is not currently ready to be enabled by default
on AArch64. https://github.com/llvm/llvm-project/pull/207169 was raised
to fix the issue, but concerns were raised around complexity of the
function and change. Until a suitable solution can be found,
EliminateSpillageCopy will be disabled on AArch64 by default.

For those who wish to still use the pass, `-enable-spill-copy-elim=true`
will ensure the pass is run.
DeltaFile
+0-403llvm/test/CodeGen/AArch64/aarch64-no-mov-spill-chain.ll
+31-21llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
+0-1llvm/lib/Target/AArch64/AArch64Subtarget.h
+31-4253 files

LLVM/project f511571llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp AMDGPULegalizerInfo.cpp

Comments
DeltaFile
+7-12llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+8-10llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+8-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+6-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+4-1llvm/docs/AMDGPUUsage.rst
+1-1llvm/test/CodeGen/AMDGPU/s-barrier-lowering-wrong-gv-signature.ll
+34-243 files not shown
+38-269 files

LLVM/project b9b5fbcllvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll s-barrier-signal-var-gep.ll

[RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.
DeltaFile
+474-0llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+81-74llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
+72-61llvm/test/CodeGen/AMDGPU/s-barrier.ll
+59-43llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+52-14llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+32-32llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
+770-22448 files not shown
+1,234-57454 files

LLVM/project f0d6b5fclang/docs AMDGPUSupport.md

comments
DeltaFile
+16-8clang/docs/AMDGPUSupport.md
+16-81 files

LLVM/project 464ec96lld/test/ELF/lto amdgpu.ll, llvm/lib/IR AutoUpgrade.cpp

Add DL auto-upgrade
DeltaFile
+19-11llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+4-0llvm/lib/IR/AutoUpgrade.cpp
+1-1lld/test/ELF/lto/amdgpu.ll
+24-123 files

LLVM/project 5142852clang/docs AMDGPUSupport.md

Add docs
DeltaFile
+27-0clang/docs/AMDGPUSupport.md
+27-01 files

LLVM/project f605bb0clang/lib/AST Type.cpp, clang/lib/Sema SemaAMDGPU.cpp

[clang][AMDGPU] Clean-up handling of named barrier type

- Allow the type in struct/classes in very limited circumstances. The goal is to enable creating trivial wrappers around the named barrier variable, but ensure we can't get into situations where things would get awkward. Currently this means we only allow the named barrier in RecordDecls with exactly 1 field, that have no base class, and are not inherited.
- Use a `amdgpu_barrier` LangAS for this type that currently maps to the local AS. This allows easy switching to the barrier AS in a future patch.
DeltaFile
+85-0clang/lib/Sema/SemaAMDGPU.cpp
+72-0clang/test/SemaHIP/amdgpu-barrier.hip
+71-0clang/test/SemaCXX/amdgpu-barrier.cpp
+28-16clang/test/CodeGenHIP/amdgpu-barrier-type.hip
+26-1clang/lib/AST/Type.cpp
+24-0clang/test/SemaOpenCL/amdgpu-barrier.cl
+306-1715 files not shown
+366-3421 files

LLVM/project 620f7a6clang/docs AMDGPUSupport.md

docs
DeltaFile
+16-8clang/docs/AMDGPUSupport.md
+16-81 files

LLVM/project b624029clang/include/clang/Basic DiagnosticSemaKinds.td, clang/test/SemaCXX amdgpu-barrier.cpp

Comment
DeltaFile
+2-2clang/test/SemaCXX/amdgpu-barrier.cpp
+2-2clang/test/SemaHIP/amdgpu-barrier.hip
+1-1clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-1clang/test/SemaOpenCL/amdgpu-barrier.cl
+6-64 files

LLVM/project 100b615lldb/test/API/tools/lldb-dap/disassemble TestDAP_disassemble.py, lldb/test/API/tools/lldb-dap/threads TestDAP_threads.py

[lldb-dap] Migrate threads and disassemble DAP test (#211277)
DeltaFile
+64-64lldb/test/API/tools/lldb-dap/disassemble/TestDAP_disassemble.py
+52-46lldb/test/API/tools/lldb-dap/threads/TestDAP_threads.py
+116-1102 files

OPNSense/core 6c13660src/opnsense/mvc/app/views/OPNsense/Firewall alias.volt

aliases: enable virtualDOM here and refactor commands
DeltaFile
+13-9src/opnsense/mvc/app/views/OPNsense/Firewall/alias.volt
+13-91 files