OPNSense/core 837a134src/opnsense/mvc/app/views/OPNsense/Firewall nat_rule.volt

Firewall: NAT: Fix inverted source/destination cosmetic issue in SNAT and One-to-One NAT grids
DeltaFile
+2-1src/opnsense/mvc/app/views/OPNsense/Firewall/nat_rule.volt
+2-11 files

FreeBSD/ports 12c08b2audio/pt2-clone distinfo Makefile

audio/pt2-clone: Update to 1.88
DeltaFile
+3-3audio/pt2-clone/distinfo
+1-1audio/pt2-clone/Makefile
+4-42 files

FreeBSD/ports b309119textproc/dyff distinfo Makefile

textproc/dyff: Update to 1.12.0
DeltaFile
+7-7textproc/dyff/distinfo
+1-2textproc/dyff/Makefile
+8-92 files

OPNSense/core 40ace08src/opnsense/mvc/app/models/OPNsense/Kea KeaDhcpv6.php

Use new count() base method for hasPdPools()
DeltaFile
+1-4src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv6.php
+1-41 files

LLVM/project 58f2c18llvm/lib/Transforms/InstCombine InstCombineShifts.cpp, llvm/test/Transforms/InstCombine shift-sub.ll

[InstCombine] Fold shift of a constant into a reverse shift (#192982)

    C1 << (C2 - X) -> (C1 << C2) >> X
    C1 << (C2 ^ X) -> (C1 << C2) >> X (if equivalent to the above)
    C1 >> (C2 - X) -> (C1 >> C2) << X (right shift modes match)
    C1 >> (C2 ^ X) -> (C1 >> C2) << X (if equivalent to the above)

Proof: https://alive2.llvm.org/ce/z/q-4soi
DeltaFile
+513-0llvm/test/Transforms/InstCombine/shift-sub.ll
+66-31llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+579-312 files

FreeBSD/src 1102bff. configure.ac, lib xmlparse.c Makefile.in

Vendor import of expat 2.8.0
DeltaFile
+118-200lib/xmlparse.c
+156-14lib/Makefile.in
+13-143tests/Makefile.in
+117-18configure.ac
+90-0lib/random_getrandom.c
+88-0lib/random_rand_s.c
+582-37545 files not shown
+1,275-88051 files

FreeBSD/src c73cd9csys/arm/allwinner if_awg.c

if_awg: Add missing awg_poll() prototype

The function awg_poll() was missing a prototype, which causes the build
to fail if DEVICE_POLLING is enabled, which it is in the ARMADAXP config.

MFC after:      2 weeks
Reviewed by:    tuexen, mmel, adrian
Sponsored by:   https://www.patreon.com/bsdivy
Differential Revision:  https://reviews.freebsd.org/D56651
DeltaFile
+3-0sys/arm/allwinner/if_awg.c
+3-01 files

LLVM/project 9b78781clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn.hip

[CIR][AMDGPU] Add lowering for amdgcn_div_scale builtins (#192931)

Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/2050

This PR adds support for lowering of _builtin_amdgcn_div_scale* amdgpu
builtins to clangIR.
Followed similar lowering from reference clang->llvmir in
clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp.
DeltaFile
+49-0clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+27-4clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+76-42 files

LLVM/project 30c5cfdllvm/lib/CodeGen ExpandVectorPredication.cpp, llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVTargetTransformInfo.h

[RISCV] Remove codegen for vp_is_fpclass (#193222)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off vp_is_fpclass from #179622.
DeltaFile
+51-58llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll
+23-39llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll
+1-15llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+3-1llvm/lib/CodeGen/ExpandVectorPredication.cpp
+0-1llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+78-1145 files

OPNSense/core 72ce6b9src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes BaseField.php, src/opnsense/mvc/app/models/OPNsense/Base/Menu MenuItem.php

Merge remote-tracking branch 'origin/master' into kea-prefix-watcher-socket-polling
DeltaFile
+22-22src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes/AutoNumberFieldTest.php
+22-22src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes/TextFieldTest.php
+5-6src/opnsense/mvc/app/models/OPNsense/Base/Menu/MenuItem.php
+5-5src/opnsense/service/conf/actions.d/actions_zfs.conf
+10-0src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes/BaseField.php
+3-3src/opnsense/mvc/app/views/OPNsense/Auth/priv.volt
+67-587 files not shown
+79-6213 files

LLVM/project 48fc5a0flang/lib/Lower/OpenMP Utils.cpp OpenMP.cpp, flang/test/Lower/OpenMP metadirective-device-isa.f90 metadirective-implementation.f90

[flang][OpenMP] Support lowering of metadirective (part 1)

This patch implements following feature in metadirective:
- implementation={vendor(...)}
- device={kind(...), isa(...), arch(...)}
- user={condition(<constant-expr>)}
- construct={parallel, target, teams}
- default, nothing, and otherwise clause

Dynamic user conditions and loop-associated variants are deferred
to follow-up patches.

This patch is part of the feature work for #188820.

Assisted with copilot and GPT-5.4
DeltaFile
+204-0flang/lib/Lower/OpenMP/Utils.cpp
+180-1flang/lib/Lower/OpenMP/OpenMP.cpp
+162-0flang/test/Lower/OpenMP/metadirective-device-isa.f90
+121-0flang/test/Lower/OpenMP/metadirective-implementation.f90
+33-0flang/test/Lower/OpenMP/metadirective-static.f90
+30-0flang/test/Lower/OpenMP/metadirective-construct.f90
+730-16 files not shown
+786-1912 files

LLVM/project fda7c9fllvm/unittests/Frontend OpenMPIRBuilderTest.cpp

Try to fix unit tests
DeltaFile
+33-0llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+33-01 files

LLVM/project bee932fllvm/lib/Target/NVPTX NVPTXISelLowering.cpp NVPTXAsmPrinter.cpp, llvm/test/CodeGen/NVPTX unknown-intrinsic.ll

[NVPTX] Improve error diagnostic when handling unknown intrinsics (#191194)

Following up on #146726, it may be desirable to gracefully fail the
compilation in the presence of unknown NVVM intrinsics, which
cannot be lowered by the NVPTX backend, rather than silently
emitting invalid PTX.
DeltaFile
+15-10llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+12-0llvm/test/CodeGen/NVPTX/unknown-intrinsic.ll
+9-0llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+36-103 files

LLVM/project 4ab33dcllvm/test/CodeGen/RISCV/rvv vselect-vp.ll fixed-vectors-vmacc-vp.ll

[RISCV] Remove codegen for vp_select (#194199)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off vp.select from #179622
DeltaFile
+94-199llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
+123-162llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
+123-162llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
+96-129llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
+52-52llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
+52-52llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
+540-75613 files not shown
+872-1,09919 files

OPNSense/core 4c796dcsrc/opnsense/mvc/app/models/OPNsense/Base/FieldTypes BaseField.php, src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes OptionFieldTest.php NetworkFieldTest.php

mvc: BaseField: extend count() for value-based field types

So getValues() already uses isSet() which makes the count of
set values in the field type correct.  Add the tests to prove
it.
DeltaFile
+3-3src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes/BaseField.php
+5-0src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes/OptionFieldTest.php
+3-0src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes/NetworkFieldTest.php
+1-0src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes/TextFieldTest.php
+12-34 files

LLVM/project 4d2d6a0llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch vector-fp-imm.ll

[LoongArch] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector (#164943)

On 64-bit targets the generic legalize will use an i64 load and a
scalar_to_vector for us. But on 32-bit targets, i64 isn't legal, and the
generic legalizer will end up emitting two 32-bit loads. This patch uses
f64 to avoid the splitting entirely and the redundant int->fp
conversion.
DeltaFile
+26-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+8-18llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fpext.ll
+1-2llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
+35-203 files

LLVM/project be68b10llvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[MLIR][OpenMP] Post-translate declare-target USM indirection in OpenMPIRBuilder

When lowering OpenMP to LLVM IR for the target device, record pairs of the
`declare target` device global and the OMPIRBuilder "ref" pointer global
(used for unified shared memory) via `OpenMPIRBuilder`. During the
`OpenMPIRBuilder::finalize` pass, run a postpass that rewrites remaining uses of the
original global to load from the ref global and adjust the pointer (shared
path for `ConstantExpr` addrspace/bitcast chains and for direct
instruction uses).

This follows what is done by clang for similar cases:
https://reviews.llvm.org/D63108.

Co-authored-by: Composer
Co-authored-by: Gemini Pro
DeltaFile
+68-0llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+39-0offload/test/offloading/fortran/declare-target-usm-ref-ptr.f90
+24-0mlir/test/Target/LLVMIR/omptarget-declare-target-usm-ref-ptr.mlir
+20-0llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+11-3mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+162-35 files

LLVM/project 68e6968flang/lib/Optimizer/OpenMP MapInfoFinalization.cpp, flang/test/Transforms omp-map-info-finalization-usm.fir

[Flang][OpenMP] Clear close on descriptor members for box parents in USM

Extend the MapInfoFinalization walk introduced in #185330 so
parent/member close consistency is enforced whenever
unified_shared_memory is in effect, not only when the parent map's
variable is a fir.RecordType. Allocatable (box) roots expand to member
maps the same way as derived-type instances; getDescriptorMapType may
add OMP_MAP_CLOSE to implicit descriptor members while the parent map
does not set close, which led to bad device behavior under
-fopenmp-force-usm with multiple mapped allocatables.

Co-authored-by: Composer (Cursor) <ai at cursor.com>
DeltaFile
+49-0offload/test/offloading/fortran/usm-box-parent-descriptor-close.f90
+12-12flang/test/Transforms/omp-map-info-finalization-usm.fir
+6-12flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
+67-243 files

FreeBSD/ports ebdcc2bsysutils/cbsd distinfo Makefile

sysutils/cbsd: update to 15.0.8

Changes:        https://github.com/cbsd/cbsd/releases/tag/v15.0.8
DeltaFile
+3-3sysutils/cbsd/distinfo
+1-1sysutils/cbsd/Makefile
+1-0sysutils/cbsd/pkg-plist
+5-43 files

FreeBSD/doc 994b6ecwebsite/content/en/status/report-2026-01-2026-03 bananapi-r64-r2-pro-drivers.adoc, website/content/ru/status/report-2026-01-2026-03 bananapi-r64-r2-pro-drivers.adoc sbom.adoc

website: trivial typo fix

newline added before AsciiDoc list for correct render
Approved by: doceng (implicit)
DeltaFile
+3-0website/content/ru/status/report-2026-01-2026-03/bananapi-r64-r2-pro-drivers.adoc
+3-0website/content/en/status/report-2026-01-2026-03/bananapi-r64-r2-pro-drivers.adoc
+2-0website/content/ru/status/report-2026-01-2026-03/sbom.adoc
+1-0website/content/ru/status/report-2026-01-2026-03/lkpi-wireless.adoc
+1-0website/content/ru/status/report-2026-01-2026-03/portmgr.adoc
+1-0website/content/ru/status/report-2026-01-2026-03/jdk25default.adoc
+11-02 files not shown
+13-08 files

OpenBSD/src Vx1oZSpregress/usr.bin/ssh keyscan.sh

   Use supported hostkeyalgorithms specifically in sshd_config instead of
   supported key types, which is almost but not completely correct.
VersionDeltaFile
1.14+4-2regress/usr.bin/ssh/keyscan.sh
+4-21 files

FreeBSD/src 221b1d4packages Makefile

packages: Don't build quotacheck if WITHOUT_QUOTAS=yes

PR:     294775
Fixes:  bb75b0d581f7 ("packages: Convert world to a subdir build")
MFC after:      2 weeks
Reported by:    Alastair Hogge <agh at riseup.net>
Sponsored by:   https://www.patreon.com/bsdivy
Differential Revision:  https://reviews.freebsd.org/D56635
DeltaFile
+1-1packages/Makefile
+1-11 files

NetBSD/pkgsrc SvWMwugsecurity/py-authlib Makefile

   py-authlib: fix MASTER_SITES
VersionDeltaFile
1.37+2-2security/py-authlib/Makefile
+2-21 files

LLVM/project 1f9c611llvm/test/Transforms/LoopFusion triple_loop_nest_inner_guard.ll double_loop_nest_inner_guard.ll

[LoopFusion][NFC] UTC gen some tests (#193755)

Some variables need rename as UTC normalizes IR value names. Also,
remove dead variable `%M` and `%N` from
`double_loop_nest_inner_guard.ll`
DeltaFile
+68-51llvm/test/Transforms/LoopFusion/triple_loop_nest_inner_guard.ll
+50-37llvm/test/Transforms/LoopFusion/double_loop_nest_inner_guard.ll
+118-882 files

LLVM/project f115551llvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[MLIR][OpenMP] Post-translate declare-target USM indirection in OpenMPIRBuilder

When lowering OpenMP to LLVM IR for the target device, record pairs of the
`declare target` device global and the OMPIRBuilder "ref" pointer global
(used for unified shared memory) via `OpenMPIRBuilder`. During the
`OpenMPIRBuilder::finalize` pass, run a postpass that rewrites remaining uses of the
original global to load from the ref global and adjust the pointer (shared
path for `ConstantExpr` addrspace/bitcast chains and for direct
instruction uses).

This follows what is done by clang for similar cases:
https://reviews.llvm.org/D63108.

Co-authored-by: Composer
Co-authored-by: Gemini Pro
DeltaFile
+68-0llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+39-0offload/test/offloading/fortran/declare-target-usm-ref-ptr.f90
+24-0mlir/test/Target/LLVMIR/omptarget-declare-target-usm-ref-ptr.mlir
+20-0llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+11-3mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+162-35 files

LLVM/project 504930bllvm/test/CodeGen/X86 machine-block-hash.mir

[X86] Remove update_mir_test_checks.py NOTE (#194278)

The test checks printer output, not MIR.
It was probably copy-pasted in #193107 from other test.
DeltaFile
+0-1llvm/test/CodeGen/X86/machine-block-hash.mir
+0-11 files

FreeBSD/ports fd30becmisc/qwen-code Makefile distinfo, misc/qwen-code/files package-lock.json

misc/qwen-code: Update to 0.15.3
DeltaFile
+4-4misc/qwen-code/files/package-lock.json
+4-4misc/qwen-code/Makefile
+3-3misc/qwen-code/distinfo
+11-113 files

LLVM/project 5c77411flang/lib/Optimizer/OpenMP MapInfoFinalization.cpp, flang/test/Transforms omp-map-info-finalization-usm.fir

[Flang][OpenMP] Clear close on descriptor members for box parents in USM

Extend the MapInfoFinalization walk introduced in #185330 so
parent/member close consistency is enforced whenever
unified_shared_memory is in effect, not only when the parent map's
variable is a fir.RecordType. Allocatable (box) roots expand to member
maps the same way as derived-type instances; getDescriptorMapType may
add OMP_MAP_CLOSE to implicit descriptor members while the parent map
does not set close, which led to bad device behavior under
-fopenmp-force-usm with multiple mapped allocatables.

Co-authored-by: Composer (Cursor) <ai at cursor.com>
DeltaFile
+49-0offload/test/offloading/fortran/usm-box-parent-descriptor-close.f90
+12-12flang/test/Transforms/omp-map-info-finalization-usm.fir
+6-12flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
+67-243 files

FreeBSD/ports 2310409sysutils/bin distinfo Makefile

sysutils/bin: Update to 0.25.5

ChangeLog: https://github.com/marcosnils/bin/releases/tag/v0.25.5
DeltaFile
+5-5sysutils/bin/distinfo
+2-2sysutils/bin/Makefile
+7-72 files

LLVM/project 2a09db4llvm/lib/Target/AMDGPU SIWholeQuadMode.cpp, llvm/test/CodeGen/AMDGPU wqm-propagate-for-execz-side-effect.mir

AMDGPU: Back-propagate wqm for sources of side-effect instruction (#193395)

For readfirstlane instruction, as it would get undefined value if exec
is zero. To handle the case that only helper lanes execute the parent
block, we let the readfirstlane to execute under wqm. But this is not
enough. If the parent block was also executed by non-helper lanes, we
also need to make sure its sources were calculated under wqm. Otherwise,
if the instruction that generate the source of readfirstlane was
executed under exact mode, the value would contain garbage data in help
lane. The garbage data in helper lane maybe returned by the
readfirstlane running under wqm.

To fix this issue, we need to enforce the back-propagation of wqm for
instructions like readfirstlane. This was only done if the instruction
was possibly in the middle of wqm region (by checking OutNeeds).
DeltaFile
+35-4llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+1-1llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
+36-52 files