FreeBSD/doc bce272awebsite/content/en/cgi man.cgi

update to FreeBSD 15.1-STABLE
DeltaFile
+4-4website/content/en/cgi/man.cgi
+4-41 files

LLVM/project 0a55578amd/comgr/src/hotswap code-object-utils.cpp code-object-utils.h, amd/comgr/test-unit RaiserScaffoldingTest.cpp

[Comgr][hotswap] Address PR #2437 review comments

Reviewer feedback from chinmaydd and jmmartinez:

- readKernelDescriptor now returns Expected<KernelDescriptorFields> by
  value instead of writing through an out-parameter (jmmartinez), folding
  the byte read and field extraction into one function.
- Group the KD register fields into a KernelDescriptorFields struct stored
  as std::optional<KernelDescriptorFields> on KernelMeta, replacing the
  HasKernelDescriptor bool flag (jmmartinez). PrivateSegmentFixedSize now
  lives only in the descriptor struct, read authoritatively from .rodata.
- extractKernelMeta propagates a KD parse failure as an error rather than
  swallowing it into a partial success (ftynse/chinmaydd; martin-luecke
  agreed), so a successful KernelMeta always carries the descriptor.
- raiser.cpp reuses the shared kAMDGPUTriple from mc-state.h instead of a
  local duplicate constant (chinmaydd).
- Add TODOs flagging the non-thread-safe target init and the
  non-exhaustive stripEncoding suffix list (chinmaydd).

Assited-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
DeltaFile
+41-63amd/comgr/src/hotswap/code-object-utils.cpp
+49-52amd/comgr/src/hotswap/code-object-utils.h
+6-6amd/comgr/test-unit/RaiserScaffoldingTest.cpp
+4-5amd/comgr/src/hotswap/raiser.cpp
+8-0amd/comgr/src/hotswap/mc-state.cpp
+1-1amd/comgr/src/hotswap/raiser.h
+109-1276 files

LLVM/project 3c4ac7dllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU scalar-float-sop2.ll

AMDGPU/GlobalISel: Fix regBankLegalize rules for uniform cvt_pkrtz
DeltaFile
+84-192llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
+6-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+90-1932 files

FreeBSD/ports 79d8b62security/openssl35/files patch-CVE-2026-2673, security/openssl36/files patch-CVE-2026-2673

security/openssl35: Fix missing commit in recent update
DeltaFile
+0-487security/openssl35/files/patch-CVE-2026-2673
+0-479security/openssl36/files/patch-CVE-2026-2673
+0-9662 files

LLVM/project 4a3946fllvm/test/CodeGen/AMDGPU float-sopc-vopc.ll scalar-float-sopc.ll

[AMDGPU][NFC] New tests for uncovered cases in SIInstrInfo.cpp (#200414)

Several cases in [the AMDGPU
backend](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp)
are not covered by the existing tests. We are proposing a new set of
tests to cover these lines.

We demonstrate that these cases are not covered by showing that no test
fails when `abort` statements are included. These are removed for the
final PR. You can check the lines of interest in [this
commit](https://github.com/llvm/llvm-project/pull/200414/commits/84d4587b784014ace546d23beaf6ed8d703452d3).
DeltaFile
+2,214-0llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
+0-761llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
+2,214-7612 files

OPNSense/core 70853basrc/opnsense/mvc/app/views/layout_partials base_apply_button.volt, src/opnsense/www/js opnsense_ui.js

ui: simplify previous
DeltaFile
+2-3src/opnsense/www/js/opnsense_ui.js
+1-1src/opnsense/mvc/app/views/layout_partials/base_apply_button.volt
+3-42 files

LLVM/project ab5da4bllvm/test/CodeGen/X86 vector-shuffle-combining-avx512f.ll

[X86] Add test showing failure to concat X86ISD::PERMI nodes with different immediates (#203487)
DeltaFile
+16-0llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
+16-01 files

LLVM/project ef37a6cflang/lib/Lower/OpenMP OpenMP.cpp, mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

[flang][OpenMP] Lower target in_reduction for host fallback

Enable host-fallback lowering for target in_reduction in Flang and MLIR OpenMP translation.

Model target in_reduction through the matching map entry, force address-preserving implicit mapping for Flang in_reduction list items, and emit the host-side task-reduction lookup with __kmpc_task_reduction_get_th_data. Unsupported device/offload-entry and richer reduction forms remain diagnosed.

Add Flang lowering, MLIR verifier/translation, and LLVM IR tests for the supported host-fallback path and the remaining unsupported cases.
DeltaFile
+128-14mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+77-36mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+72-19flang/lib/Lower/OpenMP/OpenMP.cpp
+83-3mlir/test/Target/LLVMIR/openmp-todo.mlir
+75-0mlir/test/Target/LLVMIR/openmp-target-in-reduction-multi.mlir
+60-0mlir/test/Dialect/OpenMP/invalid.mlir
+495-726 files not shown
+615-8912 files

LLVM/project 125242ellvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV FCmpFalse_Vec.ll

[LLVM][CodeGen][SPIRV] Match NULL splat to OpConstantNull. (#201313)
DeltaFile
+62-0llvm/test/CodeGen/SPIRV/constant/local-zero-constants.ll
+16-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+2-3llvm/test/CodeGen/SPIRV/FCmpFalse_Vec.ll
+1-1llvm/test/CodeGen/SPIRV/llvm-intrinsics/is_fpclass.ll
+1-1llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
+82-55 files

FreeBSD/ports 55aaf9emisc/py-mcp distinfo Makefile

misc/py-mcp: Update to 1.27.2

ChangeLog:

- https://github.com/modelcontextprotocol/python-sdk/releases/tag/v1.27.2

Reported by:    Max <notifications at github.com>
DeltaFile
+3-3misc/py-mcp/distinfo
+1-1misc/py-mcp/Makefile
+4-42 files

LLVM/project 29e27fdclang/test/Sema warn-lifetime-safety.cpp warn-lifetime-analysis-nocfg.cpp, clang/test/Sema/LifetimeSafety safety.cpp nocfg.cpp

[LifetimeSafety] Reorganize tests into `LifetimeSafety/` subdirectory (#203363)
DeltaFile
+3,653-0clang/test/Sema/LifetimeSafety/safety.cpp
+0-3,653clang/test/Sema/warn-lifetime-safety.cpp
+0-1,301clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
+1,301-0clang/test/Sema/LifetimeSafety/nocfg.cpp
+0-922clang/test/Sema/warn-lifetime-safety-invalidations.cpp
+922-0clang/test/Sema/LifetimeSafety/invalidations.cpp
+5,876-5,87635 files not shown
+8,822-8,82341 files

LLVM/project bad2574compiler-rt/test/safestack sigaltstack.c

Fix typo in sigaltstack test

Created using spr 1.3.7
DeltaFile
+16-16compiler-rt/test/safestack/sigaltstack.c
+16-161 files

LLVM/project 1727b22llvm/lib/DTLTO DTLTO.cpp, llvm/test/ThinLTO/X86/dtlto timetrace.ll

[DTLTO] Added missing timetrace "Check cache for DTLTO" message. (#203215)

After the DTLTO refactor commit, the time trace "Chack cache for DTLTO"
message was unintentionally omitted. This patch corrects this omission.
DeltaFile
+9-0llvm/test/ThinLTO/X86/dtlto/timetrace.ll
+2-0llvm/lib/DTLTO/DTLTO.cpp
+11-02 files

LLVM/project 3922f3clldb/source/Plugins/Process/Windows/Common ExceptionRecord.h ExceptionRecord.cpp

[lldb][Windows] Use uint64 for GetExceptionArguments (#203485)

Intended to fix the build failure mentioned in
https://github.com/llvm/llvm-project/pull/203301#issuecomment-4688315446.

Makes sure we always use a 64 bit int, as the minidump exception record
specifies the arguments to be 64 bit. `unsigned long long` is also 64
bit on Windows, but I think `uint64_t` conveys that we actually want a
64bit int.
Then updates uses of the return value to use `uint64_t` over
`ULONG_PTR`.
DeltaFile
+2-4lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.h
+1-1lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.cpp
+1-1lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
+4-63 files

FreeNAS/freenas a0a6655src/middlewared/middlewared/plugins/pool_ pool_operations.py

Fix configure resilver priority
DeltaFile
+1-1src/middlewared/middlewared/plugins/pool_/pool_operations.py
+1-11 files

FreeNAS/freenas d6af206src/middlewared/middlewared/pytest/unit/plugins/pool test_resilver.py

Format tests file
DeltaFile
+14-14src/middlewared/middlewared/pytest/unit/plugins/pool/test_resilver.py
+14-141 files

OPNSense/core c26e4dasrc/opnsense/mvc/app/views/layout_partials base_apply_button.volt, src/opnsense/www/js opnsense_ui.js

ui: simplify previous
DeltaFile
+2-3src/opnsense/www/js/opnsense_ui.js
+1-1src/opnsense/mvc/app/views/layout_partials/base_apply_button.volt
+3-42 files

LLVM/project a0bad85llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU scalar-float-sop2.ll

[AMDGPU][GlobalIsel] Add RegBankLegalize rules and lowering for G_AMDGPU_S_BUFFER_LOAD (#192480)

Add RegBankLegalize rules and lowering for G_AMDGPU_S_BUFFER_LOAD and
sub-dword variants (UBYTE, SBYTE, USHORT, SSHORT). The lowering covers
all four rsrc/offset divergence combinations:
- Uniform rsrc + uniform offset → scalar SMEM (stays as-is)
- Uniform rsrc + divergent offset → MUBUF (S_BUF_to_BUF, no waterfall)
- Divergent rsrc + uniform offset → SMEM in waterfall loop over rsrc
- Divergent rsrc + divergent offset → MUBUF + waterfall over rsrc

TODO: 
1. Fix legalize rule for intrinsic amdgcn_cvt_pkrtz to emit scalar cvt
operation in _/AMDGPU/scalar-float-sop2.ll_
2. Fix offset for GFX1250 in
_/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll_ as done by
PR#178389
DeltaFile
+537-558llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
+1,046-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
+436-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
+214-210llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
+188-84llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
+150-9llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+2,571-8617 files not shown
+2,716-92613 files

FreeNAS/freenas d63eb58src/middlewared/middlewared/plugins/pool_ pool_operations.py

Organize imports
DeltaFile
+7-2src/middlewared/middlewared/plugins/pool_/pool_operations.py
+7-21 files

OPNSense/core 7a53cf1src/opnsense/mvc/app/views/layout_partials base_apply_button.volt, src/opnsense/www/js opnsense_ui.js

ui: fix excessive padding on apply section (#10409)
DeltaFile
+3-2src/opnsense/www/js/opnsense_ui.js
+1-1src/opnsense/mvc/app/views/layout_partials/base_apply_button.volt
+4-32 files

LLVM/project b7a3b3ellvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[AMDGPU] Pass sret pointers in SGPRs
DeltaFile
+56,760-55,584llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+19,496-18,806llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+8,642-8,161llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+2,097-1,748llvm/test/CodeGen/AMDGPU/bf16.ll
+866-672llvm/test/CodeGen/AMDGPU/function-returns.ll
+124-128llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
+87,985-85,09911 files not shown
+88,164-85,19117 files

FreeNAS/freenas 238b691src/middlewared/middlewared/plugins/pool_ pool_operations.py, src/middlewared/middlewared/pytest/unit/plugins/pool test_resilver.py

Fix the actual bug
DeltaFile
+0-9src/middlewared/middlewared/pytest/unit/plugins/pool/test_resilver.py
+1-1src/middlewared/middlewared/plugins/pool_/pool_operations.py
+1-102 files

FreeNAS/freenas a8ee6b7src/middlewared/middlewared/plugins/pool_ pool_operations.py, src/middlewared/middlewared/pytest/unit/plugins/pool test_resilver.py

Extract `calculate_resilver_priority` method
DeltaFile
+170-0src/middlewared/middlewared/pytest/unit/plugins/pool/test_resilver.py
+58-33src/middlewared/middlewared/plugins/pool_/pool_operations.py
+228-332 files

FreeBSD/ports e3ed786filesystems/httpdirfs distinfo Makefile

filesystems/httpdirfs: Update 1.3.2 => 1.3.3

Approved by:            db@, yuri@ (Mentors, implicit)
DeltaFile
+3-3filesystems/httpdirfs/distinfo
+1-1filesystems/httpdirfs/Makefile
+4-42 files

LLVM/project 688540allvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

Use new safestack_interface.h

Created using spr 1.3.7
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,291-641,09512,975 files

LLVM/project 86fba61llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,291-641,09512,975 files

LLVM/project 2b10b6dllvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

Use new safestack_interface.h

Created using spr 1.3.7
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,291-641,09512,975 files

LLVM/project 93e4d46llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,254-641,06412,975 files

LLVM/project d06bdafllvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

Use new safestack_interface.h

Created using spr 1.3.7
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,307-641,10312,975 files

LLVM/project 41d3bd2llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,291-641,09512,975 files