LLVM/project 4cc8083flang/test/Integration/OpenMP target-nesting-in-host-ops.f90 target-use-device-nested.f90, mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[MLIR][OpenMP] Simplify OpenMP device codegen (#137201)

After removing host operations from the device MLIR module, it is no
longer necessary to provide special codegen logic to prevent these
operations from causing compiler crashes or miscompilations.

This patch removes these now unnecessary code paths to simplify codegen
logic. Some MLIR tests are now replaced with Flang tests, since the
responsibility of dealing with host operations has been moved earlier in
the compilation flow.

MLIR tests holding target device modules are updated to no longer
include now unsupported host operations.
DeltaFile
+166-302mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+0-160mlir/test/Target/LLVMIR/openmp-target-nesting-in-host-ops.mlir
+87-0flang/test/Integration/OpenMP/target-nesting-in-host-ops.f90
+24-37mlir/test/Target/LLVMIR/omptarget-memcpy-align-metadata.mlir
+46-0flang/test/Integration/OpenMP/target-use-device-nested.f90
+0-46mlir/test/Target/LLVMIR/openmp-target-use-device-nested.mlir
+323-54512 files not shown
+484-73618 files

LLVM/project 1e4b4faflang/lib/Optimizer/OpenMP FunctionFiltering.cpp, flang/test/Lower/OpenMP host-eval.f90 declare-target-link-tarop-cap.f90

[Flang][OpenMP] Minimize host ops remaining in device compilation (#137200)

This patch updates the function filtering OpenMP pass intended to remove
host functions from the MLIR module created by Flang lowering when
targeting an OpenMP target device.

Host functions holding target regions must be kept, so that the target
regions within them can be translated for the device. The issue is that
non-target operations inside these functions cannot be discarded because
some of them hold information that is also relevant during target device
codegen. Specifically, mapping information resides outside of
`omp.target` regions.

This patch updates the previous behavior where all host operations were
preserved to then ignore all of those that are not actually needed by
target device codegen. This, in practice, means only keeping target
regions and mapping information needed by the device. Arguments for some
of these remaining operations are replaced by placeholder allocations
and `fir.undefined`, since they are only actually defined inside of the

    [4 lines not shown]
DeltaFile
+516-0flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir
+350-2flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
+137-0flang/test/Transforms/OpenMP/function-filtering.mlir
+0-137flang/test/Transforms/omp-function-filtering.mlir
+37-18flang/test/Lower/OpenMP/host-eval.f90
+10-9flang/test/Lower/OpenMP/declare-target-link-tarop-cap.f90
+1,050-1662 files not shown
+1,053-1718 files

LLVM/project 3a95117llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

Explicitly check fo 8bit source type

Created using spr 1.3.7
DeltaFile
+74,257-82,975llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+26,135-30,267llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,044-11,203llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+5,872-6,681llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+2,674-3,346llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,521-1,873llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+119,503-136,345353 files not shown
+131,707-144,047359 files

LLVM/project 40ebbb6llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange reduction2mem.ll reduction2mem-limitation.ll

[LoopInterchange] Initialize new_var to InitValue on first iteration (#178370)

Fixed a bug found during testing:
- If it is the first iteration, `new_var` should be initialized to
'InitValue'.
DeltaFile
+1-1llvm/test/Transforms/LoopInterchange/reduction2mem.ll
+1-1llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+1-1llvm/test/Transforms/LoopInterchange/reduction2mem-limitation.ll
+3-33 files

OPNSense/tools 04306c5config/26.1 make.conf

config: move suricata options
DeltaFile
+1-1config/26.1/make.conf
+1-11 files

LLVM/project deafb6bclang/lib/AST/ByteCode EvalEmitter.cpp

[clang][bytecode][NFC] Use `Block::deref()` in `EvalEmitter` (#178630)

Instead of doing the casting around `Block::data()` ourselves.
DeltaFile
+2-2clang/lib/AST/ByteCode/EvalEmitter.cpp
+2-21 files

LLVM/project 245043fclang/docs ReleaseNotes.rst, clang/lib/Sema SemaType.cpp

[Clang] avoid assertion in __underlying_type for enum redeclarations (#177984)

Fixes #177943

---

This patch addresses cases where `__underlying_type` is used with enum
redeclarations. The previously added assertion
(https://github.com/llvm/llvm-project/pull/155900) treated a missing
`int` on the referenced `EnumDecl` as an indicator of a _demoted
definition_, while this condition can also occur for redeclarations.
DeltaFile
+9-0clang/test/SemaCXX/underlying_type.cpp
+0-4clang/lib/Sema/SemaType.cpp
+1-0clang/docs/ReleaseNotes.rst
+10-43 files

FreeNAS/freenas b3becd0src/middlewared/middlewared/plugins sysdataset.py, src/middlewared/middlewared/plugins/system_dataset mount.py

Fix
DeltaFile
+17-1src/middlewared/middlewared/plugins/sysdataset.py
+1-1src/middlewared/middlewared/plugins/system_dataset/mount.py
+18-22 files

GhostBSD/ports a3e2e08x11/xconfig distinfo Makefile

x11/xconfig: update 3.0
DeltaFile
+3-3x11/xconfig/distinfo
+4-1x11/xconfig/Makefile
+0-2x11/xconfig/pkg-descr
+1-0x11/xconfig/pkg-plist
+8-64 files

LLVM/project e17374alldb/source/Host/windows MainLoopWindows.cpp, lldb/test/Shell/DAP TestSTDINConsole.test

[lldb-dap][windows] allow STDIN to be a console (#178642)

DeltaFile
+62-0lldb/test/Shell/DAP/TestSTDINConsole.test
+1-1lldb/source/Host/windows/MainLoopWindows.cpp
+63-12 files

LLVM/project 3f1386bllvm/lib/Target/AMDGPU SIInstrInfo.cpp

[AMDGPU] Add braces around a switch case. NFC. (#178637)

DeltaFile
+2-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+2-11 files

OPNSense/ports 8e59122opnsense/phpseclib distinfo Makefile

opnsense/phpseclib: update to 3.0.49
DeltaFile
+3-3opnsense/phpseclib/distinfo
+1-1opnsense/phpseclib/Makefile
+1-0opnsense/phpseclib/pkg-plist
+5-43 files

OPNSense/ports af46bfdopnsense/dnsmasq distinfo Makefile, opnsense/dnsmasq/files patch-src_util.c patch-src_dbus.c

opnsense/dnsmasq: update to 2.92
DeltaFile
+0-73opnsense/dnsmasq/files/patch-src_util.c
+0-21opnsense/dnsmasq/files/patch-src_dbus.c
+3-3opnsense/dnsmasq/distinfo
+2-2opnsense/dnsmasq/Makefile
+1-1opnsense/dnsmasq/files/pkg-message.in
+6-1005 files

OPNSense/ports 177bbbetextproc/libxml2 pkg-plist Makefile, textproc/libxml2/files xmllint.1 xmlcatalog.1

textproc/libxml2: sync with upstream

Taken from: FreeBSD
DeltaFile
+656-0textproc/libxml2/files/xmllint.1
+355-0textproc/libxml2/files/xmlcatalog.1
+4-60textproc/libxml2/pkg-plist
+21-20textproc/libxml2/Makefile
+32-0textproc/libxml2/files/xml2-config.1
+5-3textproc/libxml2/distinfo
+1,073-836 files

LLVM/project 73c7c56llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-ldst-sext.ll sve-ldst-zext.ll

[LLVM][DAGCombiner] Look through freeze when combining extensions of loads (#175022)

Following on from https://github.com/llvm/llvm-project/pull/172484 I
have added support to tryToFoldExtOfLoad for looking through freezes, in
order to catch more cases of extending loads. This type of code is
sometimes seen being generated by the loop vectoriser. For now I've
limited this to cases where the load is only used by the freeze, since
otherwise it leads to worse code in some X86 tests.
DeltaFile
+435-0llvm/test/CodeGen/AArch64/sve-ldst-sext.ll
+426-0llvm/test/CodeGen/AArch64/sve-ldst-zext.ll
+36-19llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+31-0llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
+4-8llvm/test/CodeGen/X86/avx512-ext.ll
+6-6llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
+938-339 files not shown
+966-4715 files

LLVM/project 3fb8601lldb/source/Interpreter Options.cpp

[lldb] Refactor command option printing (#178208)

So I have an easier time fixing #177570.

Changes I have made:
* Init a variable inside if statement to reduce scope.
* Added const to some variables.
* Early return if we print a single line, and dedent the "else" that
handles multiple lines.
* Only convert lldb's short codes into ansi codes once.
* Rename a couple of variables where they could have either referred to
the visible text or the raw data with the ansi codes in.
DeltaFile
+44-41lldb/source/Interpreter/Options.cpp
+44-411 files

LLVM/project aeee859llvm/lib/Target/AArch64 AArch64SystemOperands.td AArch64Features.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Gate some `tlbip` insns with +tlbid or +d128

Change the gating of `tlbip` instructions containing `*E1IS*`, `*E1OS*`,
`*E2IS*` or `*E2OS*` to be used with `+tlbid` or `+d128`. This is because
the 2025 Armv9.7-A MemSys specification says:

```
All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions
that are currently dependent on FEAT_D128 are updated to be dependent
on FEAT_D128 or FEAT_TLBID
```
DeltaFile
+259-0llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s
+110-110llvm/test/MC/AArch64/armv9a-sysp.s
+18-4llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+21-0llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+13-2llvm/lib/Target/AArch64/AArch64SystemOperands.td
+7-4llvm/lib/Target/AArch64/AArch64Features.td
+428-1204 files not shown
+449-12610 files

LLVM/project 4ebede7lldb/source/Host/windows MainLoopWindows.cpp, lldb/test/Shell/DAP TestSTDINConsole.test

Revert "[lldb-dap][windows] allow STDIN to be a console (#178409)" (#178641)

DeltaFile
+0-62lldb/test/Shell/DAP/TestSTDINConsole.test
+1-1lldb/source/Host/windows/MainLoopWindows.cpp
+1-632 files

NetBSD/pkgsrc KwJGsIMdoc pkg-vulnerabilities

   pkg-vulnerabilities: add (part of) last days CVEs

   + gnutls,
     gpac (fixed upstream, no stable releases with the fixes),
     hiawatha (no information from upstream, assume not fixed),
     py-gi-docgen, py-python-multipart,
     qgis (commented out because affects upstream CI/CD)
VersionDeltaFile
1.723+12-1doc/pkg-vulnerabilities
+12-11 files

LLVM/project 7f661d2llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/mcdc/nest/nest' into users/chapuni/mcdc/nest/trunk
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6065,137 files not shown
+778,450-525,5865,143 files

LLVM/project ad26fa5llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/mcdc/nest/covmapdesc' into users/chapuni/mcdc/nest/nest

Conflicts:
        clang/docs/ReleaseNotes.rst
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6065,137 files not shown
+778,450-525,5865,143 files

LLVM/project da7eac4llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/single/binop' into users/chapuni/mcdc/nest/covmapdesc
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,007-484,5894,121 files

LLVM/project 00df2aellvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/merge/merge-mcdc' into users/chapuni/cov/merge/trunk
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,005-484,5874,121 files

LLVM/project f08a00dllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/merge/strategy' into users/chapuni/cov/merge/merge-mcdc
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,005-484,5874,121 files

LLVM/project f0a9223llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/merge/forfile' into users/chapuni/cov/merge/strategy

Conflicts:
        llvm/test/tools/llvm-cov/Inputs/branch-templates.cpp
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,005-484,5874,121 files

LLVM/project a3aabe4llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/merge/region_segment' into users/chapuni/cov/merge/forfile
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,007-484,5894,121 files

LLVM/project c9faee1llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/single/binop' into users/chapuni/cov/merge/region_segment

Conflicts:
        llvm/test/tools/llvm-cov/branch-macros.test
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,007-484,5894,121 files

LLVM/project 94aea76llvm/lib/Target/LoongArch LoongArchInstrInfo.cpp, llvm/test/CodeGen/LoongArch disable-reloc-sched.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+48-0llvm/test/CodeGen/LoongArch/disable-reloc-sched.ll
+12-0llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+60-02 files

LLVM/project 1dd9e20lldb/packages/Python/lldbsuite/test decorators.py configuration.py, lldb/test/API/functionalities/ubsan/basic TestUbsanBasic.py

[lldb] Fix UbSan decorator (#177964)

the ubsan decorator previously assumes the platform is macOS.

macOS has an extra underscore in symbols names match two or more.
uses the llvm-nm that is built instead of the system's nm.
DeltaFile
+9-27lldb/packages/Python/lldbsuite/test/decorators.py
+12-0lldb/packages/Python/lldbsuite/test/configuration.py
+2-2lldb/test/API/functionalities/ubsan/basic/TestUbsanBasic.py
+3-0lldb/packages/Python/lldbsuite/test/dotest.py
+26-294 files

LLVM/project 3f2f920flang/test/Integration/OpenMP target-nesting-in-host-ops.f90 target-use-device-nested.f90, mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[MLIR][OpenMP] Simplify OpenMP device codegen

After removing host operations from the device MLIR module, it is no longer
necessary to provide special codegen logic to prevent these operations from
causing compiler crashes or miscompilations.

This patch removes these now unnecessary code paths to simplify codegen logic.
Some MLIR tests are now replaced with Flang tests, since the responsibility of
dealing with host operations has been moved earlier in the compilation flow.

MLIR tests holding target device modules are updated to no longer include now
unsupported host operations.
DeltaFile
+166-302mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+0-160mlir/test/Target/LLVMIR/openmp-target-nesting-in-host-ops.mlir
+87-0flang/test/Integration/OpenMP/target-nesting-in-host-ops.f90
+24-37mlir/test/Target/LLVMIR/omptarget-memcpy-align-metadata.mlir
+0-46mlir/test/Target/LLVMIR/openmp-target-use-device-nested.mlir
+46-0flang/test/Integration/OpenMP/target-use-device-nested.f90
+323-54512 files not shown
+484-73618 files