LLVM/project 531613emlir/lib/Dialect/MemRef/Transforms ExtractAddressComputations.cpp ElideReinterpretCast.cpp, mlir/lib/Dialect/Tensor/IR TensorOps.cpp

[mlir] Use Repeated<T> in more places to avoid temporary vectors. NFC. (#188846)

Replace `SmallVector<Type/Value>(n, x)` with `Repeated<Type/Value>(n,
x)`. This avoids heap allocations for repeated values.

Also change `ExtractAddressComputations` rebuild callbacks from
`ArrayRef<Value>` to `ValueRange` to enable `Repeated<Value>`
passthrough.

Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
DeltaFile
+9-8mlir/lib/Dialect/MemRef/Transforms/ExtractAddressComputations.cpp
+3-2mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+2-1mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
+2-1mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
+16-124 files

LLVM/project 2cbbc1aclang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsage.cpp, clang/test/Analysis/Scalable/UnsafeBufferUsage tu-summary-bad-ptr-level.json tu-summary-no-key.json

address comments
DeltaFile
+58-0clang/test/Analysis/Scalable/UnsafeBufferUsage/tu-summary-bad-ptr-level.json
+58-0clang/test/Analysis/Scalable/UnsafeBufferUsage/tu-summary-no-key.json
+53-0clang/test/Analysis/Scalable/UnsafeBufferUsage/tu-summary-bad-element.json
+15-1clang/test/Analysis/Scalable/UnsafeBufferUsage/tu-summary-serialization.test
+5-5clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.cpp
+3-4clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+192-101 files not shown
+194-127 files

LLVM/project 966d969llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.permlane64.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for amdgcn_permlane64 (#187840)

Add register bank legalization rules for the amdgcn_permlane64 intrinsic
in the new RegBankLegalize framework.

After GISel legalization, permlane64 always operates on S32 — sub-32-bit
types are anyext'd to S32 and types wider than 32 bits are split into
S32 parts by legalizeLaneOp. Add rules for B32 type.

Also enable -new-reg-bank-select in the permlane64 lit test and update
affected check lines.
DeltaFile
+1-31llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
+3-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+4-312 files

FreeBSD/src f7b368dlib/libc/gen rtld_get_var.3

rtld_get_var(3): provide explicit list of rtld vars that can be modified

Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Differential revision:  https://reviews.freebsd.org/D56055
DeltaFile
+17-0lib/libc/gen/rtld_get_var.3
+17-01 files

FreeBSD/src 9f16078libexec/rtld-elf/tests set_var_test.c Makefile

rtld: add a test for rtld_set_var (with LIBRARY_PATH_FDS)

PR:     294054
Reviewed by:    kib
MFC after:      1 week
DeltaFile
+38-0libexec/rtld-elf/tests/set_var_test.c
+1-0libexec/rtld-elf/tests/Makefile
+39-02 files

FreeBSD/src b9f046dlibexec/rtld-elf rtld.c

rtld: properly handle update of several vars in rtld_set_var()

Besides setting the value in the array of the values, rtld sometimes
needs to recalculate some internal control variable for the change to
take effect.  Allow the variable description to supply a method called
on the update.  Lock the function with the bind lock for safe operation.

Mark several variables as allowed for update, since the on_update method
is provided for them.  The list is LD_BIND_NOW, LD_BIND_NOT,
LD_LIBMAP_DISABLE, LD_LOADFLTR.

Reviewed by:    markj
Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Differential revision:  https://reviews.freebsd.org/D56055
DeltaFile
+152-36libexec/rtld-elf/rtld.c
+152-361 files

FreeBSD/src f39754dlib/msun/aarch64 fenv.h, lib/msun/amd64 fenv.c

fenv.h: stop declaring feclearexcept() extern inline

The function is already exported from libm.  We only need to stop
declare it extern inline, and instead provide a macro which uses the
internal inline function __feclearexcept_int() instead.

PR:     277958
Reviewed by:    dim (x86)
Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Differential revision:  https://reviews.freebsd.org/D55975
DeltaFile
+5-2lib/msun/aarch64/fenv.h
+6-1lib/msun/amd64/fenv.c
+6-1lib/msun/arm/fenv.c
+6-1lib/msun/i387/fenv.c
+6-1lib/msun/powerpc/fenv.c
+5-2lib/msun/x86/fenv.h
+34-85 files not shown
+58-1311 files

LLVM/project cdb4578lldb/test/API/lang/objc/objc-class-method TestObjCClassMethod.py

This new flag depends both on the compiler version AND the linker (#188864)

version, and clang will say it supports the flag even if the linker
can't use its output.
The compiler actually has code to know whether the linker version is
right, and sets it to the default if the stars align.

So I'm going to just test whether whatever is the default method for the
compiler and linker works.
DeltaFile
+3-16lldb/test/API/lang/objc/objc-class-method/TestObjCClassMethod.py
+3-161 files

LLVM/project 788ea11lld/MachO ICF.cpp, lld/test/MachO icf-safe-missing-addrsig.s icf-options.s

[lld-macho] Make safe ICF conservative without __llvm_addrsig (#188400)

MachO --icf=safe and --icf=safe_thunks used to keep folding code from
object files that did not contain __llvm_addrsig, which was inconsistent
with the conservative ELF/COFF behavior. Mark all symbols in such
objects as address-significant instead, and add regression coverage for
both safe ICF modes with and without addrsig.
DeltaFile
+112-0lld/test/MachO/icf-safe-missing-addrsig.s
+4-1lld/MachO/ICF.cpp
+1-0lld/test/MachO/icf-options.s
+117-13 files

LLVM/project b9b87ddllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.struct.buffer.atomic.ll llvm.amdgcn.struct.ptr.buffer.atomic.ll

AMDGPU/GlobalISel: RegBankLegalize rules for buffer atomics (#187550)

Add RegBankLegalize rules for the buffer atomics and/xor/or/inc/dec.
DeltaFile
+10-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
+10-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+3-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
+3-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
+31-195 files

LLVM/project 4562a95llvm/lib/Transforms/Vectorize VPlanUnroll.cpp, llvm/test/Transforms/LoopVectorize tail-folding-optimize-vector-induction-width.ll struct-return-replicate.ll

Revert "[VPlan] Explicitly unroll replicate-regions without live-outs by VF." (#188868)

Reverts llvm/llvm-project#170212

appears to cause a failure with expensive checks:
https://lab.llvm.org/buildbot/#/builders/187/builds/18306
DeltaFile
+0-156llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
+98-49llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
+80-40llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
+41-43llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
+18-9llvm/test/Transforms/LoopVectorize/tail-folding-optimize-vector-induction-width.ll
+14-6llvm/test/Transforms/LoopVectorize/struct-return-replicate.ll
+251-30354 files not shown
+531-42060 files

LLVM/project 1b667ebllvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! More optimisations
DeltaFile
+122-134llvm/lib/Target/AArch64/AArch64SystemOperands.td
+122-1341 files

LLVM/project ba142d8llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/test/MC/AArch64 armv8.7a-xs.s armv9.5a-tlbiw.s

fixup! Move nxs bit into TLBIEntry rather than override
DeltaFile
+57-56llvm/test/MC/AArch64/armv8.7a-xs.s
+21-33llvm/lib/Target/AArch64/AArch64SystemOperands.td
+10-10llvm/test/MC/AArch64/armv9.5a-tlbiw.s
+88-993 files

LLVM/project 2b8c171llvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! Another tablegen optimisation
DeltaFile
+117-184llvm/lib/Target/AArch64/AArch64SystemOperands.td
+117-1841 files

LLVM/project fe5a21allvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! More tablegen fixes
DeltaFile
+32-70llvm/lib/Target/AArch64/AArch64SystemOperands.td
+32-701 files

LLVM/project ebb827ellvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! Refactor TLBI tablegen
DeltaFile
+232-120llvm/lib/Target/AArch64/AArch64SystemOperands.td
+232-1201 files

LLVM/project ab4e564llvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! Change tablegen as suggested
DeltaFile
+52-30llvm/lib/Target/AArch64/AArch64SystemOperands.td
+52-301 files

LLVM/project d9c15d9llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/test/MC/AArch64 armv9a-tlbip.s

[AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases

Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.

The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.

Update testcases accordingly.
DeltaFile
+92-61llvm/lib/Target/AArch64/AArch64SystemOperands.td
+8-9llvm/test/MC/AArch64/armv9a-tlbip.s
+100-702 files

FreeBSD/ports 443ea17. MOVED

MOVED: Correct textproc/en-core-web-sm line

Reported by:    antoine at freebsd.org
DeltaFile
+1-1MOVED
+1-11 files

FreeBSD/ports 0c4a771misc/claude-code distinfo Makefile, misc/claude-code/files package-lock.json

misc/claude-code: update 2.1.81 → 2.1.84
DeltaFile
+34-4misc/claude-code/files/package-lock.json
+3-3misc/claude-code/distinfo
+1-1misc/claude-code/Makefile
+38-83 files

LLVM/project e251f57llvm/lib/Transforms/Vectorize VPlanUnroll.cpp, llvm/test/Transforms/LoopVectorize tail-folding-optimize-vector-induction-width.ll struct-return-replicate.ll

Revert "[VPlan] Explicitly unroll replicate-regions without live-outs by VF. …"

This reverts commit cb1661b0460627bac4407fda129febefbf3e738a.
DeltaFile
+0-156llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
+98-49llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
+80-40llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
+41-43llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
+18-9llvm/test/Transforms/LoopVectorize/tail-folding-optimize-vector-induction-width.ll
+14-6llvm/test/Transforms/LoopVectorize/struct-return-replicate.ll
+251-30354 files not shown
+531-42060 files

LLVM/project 67ea4dellvm/test/CodeGen/AMDGPU fract-match.ll

AMDGPU: Regenerate test checks (#188862)
DeltaFile
+23-2llvm/test/CodeGen/AMDGPU/fract-match.ll
+23-21 files

LLVM/project 781c303llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Push these changes further into the backend
DeltaFile
+25-14llvm/lib/Target/AArch64/AArch64SystemOperands.td
+11-6llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+6-9llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+4-4llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+46-334 files

LLVM/project 9151352llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h

Apply code review suggestions
DeltaFile
+5-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+3-4llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+9-123 files

NetBSD/pkgsrc 6PbnAw7textproc/json-schema Makefile

   json-schema: now needs C++17

   probably due to the jsoncpp update
VersionDeltaFile
1.14+4-1textproc/json-schema/Makefile
+4-11 files

FreeBSD/ports 7ab4325mail/addresses-goodies Makefile distinfo

mail/addresses-goodies: Update to 0.5.0

Take maintainership.
Update WWW.
Add LICENSE_FILE.
Remove WRKSRC= and add ALL_TARGET, INSTALL_TARGET.
Switch from post-patch:REINPLACE_CMD to MAKE_ENV+=.
Add STRIP_CMD.

News: https://savannah.nongnu.org/news/?id=10726

PR:             291159
Approved by:    fluffy (mentor)
DeltaFile
+14-20mail/addresses-goodies/Makefile
+3-2mail/addresses-goodies/distinfo
+0-2mail/addresses-goodies/pkg-descr
+17-243 files

LLVM/project 29886a1llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.ds.permute.ll llvm.amdgcn.ds.bpermute.ll

AMDGPU/GlobalISel: RegBankLegalize rules for ds_permute (#188266)
DeltaFile
+29-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
+3-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
+1-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
+36-86 files

FreeBSD/ports 40c3465mail/addresses pkg-plist Makefile

mail/addresses: Update to 0.5.0

Take maintainershp.
Add LICENSE_FILE.
Add STRIP_CMD.
Update pkg-descr.

News: https://savannah.nongnu.org/news/?id=10726

PR:             291121
Approved by:    fluffy (mentor)
DeltaFile
+60-63mail/addresses/pkg-plist
+10-5mail/addresses/Makefile
+5-2mail/addresses/pkg-descr
+3-2mail/addresses/distinfo
+78-724 files

FreeNAS/freenas 1fbf75csrc/middlewared/middlewared/plugins/failover_ event.py

Comment out iscsi.scst.suspend_logins for now
DeltaFile
+2-2src/middlewared/middlewared/plugins/failover_/event.py
+2-21 files

FreeBSD/ports 7e522b0devel/hs-hoogle distinfo Makefile.cabal

devel/hs-hoogle: Update 5.0.18.4 => 5.0.19.0

Approved by:            haskell@ (alven@)
Approved by:            db@, yuri@ (Mentors, implicit)
DeltaFile
+205-165devel/hs-hoogle/distinfo
+173-0devel/hs-hoogle/Makefile.cabal
+1-156devel/hs-hoogle/Makefile
+379-3213 files