LLVM/project e9a8eb5llvm/unittests/Frontend OpenMPIRBuilderTest.cpp, llvm/unittests/Target/AMDGPU AMDGPUUnitTests.cpp DwarfRegMappings.cpp

AMDGPU: Use subarch triples in more unit tests

Avoid looking up the target by the cpu name with the legacy
amdgcn name.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+38-32llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
+8-6llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
+2-3llvm/unittests/Target/AMDGPU/UniformityAnalysisTest.cpp
+2-2llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+2-1llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.h
+1-1llvm/unittests/Target/AMDGPU/AMDGPUMCExprTest.cpp
+53-455 files not shown
+58-5011 files

LLVM/project d94df00llvm/test/tools/llvm-reduce/mir preserve-max-call-frame-size.mir preserve-mem-operands.mir

AMDGPU: Convert llvm-reduce tests to new subarch triples (62) (#209868)

Pick arbitrary real subarch
DeltaFile
+1-1llvm/test/tools/llvm-reduce/mir/preserve-max-call-frame-size.mir
+1-1llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir
+1-1llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
+1-1llvm/test/tools/llvm-reduce/mir/reduce-instruction-flags.mir
+1-1llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir
+1-1llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
+6-619 files not shown
+25-2525 files

LLVM/project c012610cross-project-tests CMakeLists.txt, cross-project-tests/dtlto remote-options.test

[DTLTO] Add remote compiler option forwarding coverage (#208589)

Add a cross-project DTLTO test that checks the existing LTO
configuration state serialized into the remote Clang command line. The
test uses the validate.py distributor to inspect the generated DTLTO
JSON.

Cover all the existing forwarded options.

Add paired negative checks for optional flags so the test also verifies
they are not emitted when the corresponding configuration state is not
set.
DeltaFile
+90-0cross-project-tests/dtlto/remote-options.test
+1-0cross-project-tests/CMakeLists.txt
+91-02 files

LLVM/project 9c6a9f5llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64ec-exit-thunks.ll

[CodeGen][ARM64EC] Copy first four arguments to FP registers in vararg exit thunks (#209581)

ARM64EC vararg functions receive all types of the first four arguments
in x0-x3. Because x86_64 expects floating-point arguments in FP
registers, always copy x0-x3 to d0-d3 in the exit thunks, matching
MSVC's behavior.
DeltaFile
+21-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+12-0llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
+33-02 files

LLVM/project 770ccb3llvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic

The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.

Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:

- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
  Operations use APInt arithmetic at WideBits, chosen to guarantee no
  intermediate overflow:
  $$
    WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
  $$
  This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
  bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
  extra bits.

    [15 lines not shown]
DeltaFile
+382-429llvm/lib/Analysis/DependenceAnalysis.cpp
+104-3llvm/test/Analysis/DependenceAnalysis/banerjee-overflow.ll
+20-50llvm/include/llvm/Analysis/DependenceAnalysis.h
+2-4llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
+1-1llvm/test/Analysis/DependenceAnalysis/PR51512.ll
+509-4875 files

OPNSense/core 14710e7src/opnsense/mvc/app/controllers/OPNsense/Base ControllerBase.php, src/opnsense/mvc/app/views/layout_partials base_tabs_header.volt base_tabs_content.volt

mvc: tab/subtab form generation align with what base_form expects, closes https://github.com/opnsense/core/issues/10535

As these are hardly used, we missed these during our testing.
While here, cleanup the code a bit further and stop using index assignments to refer to content [0],[1],..
DeltaFile
+12-12src/opnsense/mvc/app/views/layout_partials/base_tabs_header.volt
+10-9src/opnsense/mvc/app/controllers/OPNsense/Base/ControllerBase.php
+4-4src/opnsense/mvc/app/views/layout_partials/base_tabs_content.volt
+26-253 files

FreeNAS/freenas 1bc12bdsrc/middlewared/middlewared/alembic/versions/27.0 2026-07-16_08-47_remove_snmp_loglevel.py, src/middlewared/middlewared/api/v27_0_0 snmp.py

Remove SNMP log level
DeltaFile
+32-0src/middlewared/middlewared/alembic/versions/27.0/2026-07-16_08-47_remove_snmp_loglevel.py
+6-2src/middlewared/middlewared/api/v27_0_0/snmp.py
+0-1src/middlewared/middlewared/plugins/snmp/config.py
+38-33 files

LLVM/project 9a839d5llvm/lib/Target/AMDGPU GCNVOPDUtils.cpp VOP3PInstructions.td, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

AMDGPU: Reland: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3

For V_DOT2_F32_F16 and V_DOT2_F32_BF16 add their VOPDName and mark
them with usesCustomInserter which will be used to add pre-RA register
allocation hints to preferably assign dst and src2 to the same physical
register. When the hint is satisfied, canMapVOP3PToVOPD recognises the
instruction as eligible for VOPD pairing by checking if it is VOP2 like:
dst==src2, no source modifiers, no clamp, and src1 is a register.
Mark both instructions as commutable to allow a literal in src1 to be
moved to src0, since VOPD only permits a literal in src0.

Original patch had a bug where it did not check if physical src
registers match register class of appropriate operand in fullVOPD
instructions, check is now done via isValidVOPDSrc.
DeltaFile
+442-520llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+163-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+34-1llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+8-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+8-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+661-5951 files not shown
+663-5977 files

LLVM/project bf397bellvm/docs LangRef.md, llvm/lib/AsmParser LLParser.cpp

[IR] Add elementwise modifier to atomic loads (#204556)

Add an `elementwise` modifier to atomic loads to represent
per-element atomic semantics for fixed-vector loads.

Without the modifier, a vector atomic load remains a whole-value
atomic operation. With `elementwise`, the load behaves as if it were
expanded into one scalar atomic load per fixed-vector element, without
providing atomicity for the vector value as a whole.

Discussion:
https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomic-loads-and-stores/91100
DeltaFile
+80-0llvm/unittests/IR/VerifierTest.cpp
+49-0llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
+18-8llvm/docs/LangRef.md
+15-10llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+18-4llvm/lib/IR/Verifier.cpp
+20-2llvm/lib/AsmParser/LLParser.cpp
+200-248 files not shown
+260-3514 files

LLVM/project 8a77787llvm/lib/Target/X86 X86InstrInfo.cpp, llvm/test/CodeGen/X86 remove-redundant-cmp-tzcnt.ll remove-redundant-cmp-lzcnt.ll

Revert "[X86] Remove redundant `cmp` before `adc` after `lzcnt` or `tzcnt`" (#210006)

Reverts #208392 - while we investigate a miscompile due to CF/ZF mismatch
DeltaFile
+0-199llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
+0-186llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
+0-76llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
+0-74llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
+0-12llvm/lib/Target/X86/X86InstrInfo.cpp
+3-1llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
+3-5486 files

LLVM/project b12b981llvm/lib/Target/AMDGPU GCNVOPDUtils.cpp

AMDGPU: Validate VOPD/VOPD3 physical source registers against operand RC

Replace isVGPR checks with isValidVOPDSrc that validates physical source
registers against the actual combined VOPD/VOPD3 instruction's operand
register classes. Now we also validate operands for VOPD instructions.
DeltaFile
+40-7llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+40-71 files

LLVM/project 65d3601llvm/lib/Target/RISCV RISCVInstrInfoSFB.td, llvm/test/CodeGen/RISCV short-forward-branch-opt-zibi.ll

[RISC-V] Make Short Forward Branches capable of matching Zibi instructions (#208637)

Add new SFB patterns to make `PseudoCCMOVGPR` capable of matching `beqi`
and `bnei`, so that it can be folded into `PseudoCC*` of `SFBALU_rr`
variants
DeltaFile
+550-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
+22-0llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
+572-02 files

LLVM/project e83e07bllvm/lib/Target/AMDGPU GCNVOPDUtils.cpp

AMDGPU: Refactor checkVOPDRegConstraints
DeltaFile
+28-41llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+28-411 files

FreeBSD/ports 45ec94esecurity/vuxml/vuln 2026.xml

security/vuxml: Document liboqs vulnerabilities
DeltaFile
+31-0security/vuxml/vuln/2026.xml
+31-01 files

FreeBSD/ports 2291aceeditors/vscode Makefile, graphics/drawio Makefile

*/*: Bump port revision after electron42 update (fd67ba2aab44)
DeltaFile
+1-1editors/vscode/Makefile
+1-1graphics/drawio/Makefile
+1-1net-im/deltachat-desktop/Makefile
+1-1net-im/signal-desktop/Makefile
+4-44 files

FreeBSD/ports fd67ba2devel/electron42 distinfo Makefile, devel/electron42/files patch-ui_views_focus_focus__manager.cc

devel/electron42: Update to 42.7.0

Changelog:
- https://github.com/electron/electron/releases/tag/v42.6.2
- https://github.com/electron/electron/releases/tag/v42.7.0

Reported by:    GitHub (watch releases)
DeltaFile
+7-7devel/electron42/distinfo
+3-3devel/electron42/files/patch-ui_views_focus_focus__manager.cc
+1-1devel/electron42/Makefile
+1-1devel/electron42/Makefile.version
+12-124 files

FreeBSD/ports 385ff6fmail/nextcloud-mail distinfo Makefile

mail/nextcloud-mail: Update to 5.10.8
DeltaFile
+3-3mail/nextcloud-mail/distinfo
+1-1mail/nextcloud-mail/Makefile
+4-42 files

LLVM/project 36d2fb9llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll

[AMDGPU] Reject sub-dword format buffer loads and stores (#209703)

An i8 `buffer.{load,store}.format` has no corresponding hardware
instruction so diagnose it in SelectionDAG and fail legalization in
GlobalISel instead of emitting invalid format opcodes
DeltaFile
+22-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+20-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
+19-0llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+61-03 files

FreeBSD/ports 7d5cfd0mail/roundcube-twofactor_gauthenticator pkg-plist distinfo, mail/roundcube-twofactor_gauthenticator/files patch-twofactor__gauthenticator.php

mail/roundcube-twofactor_gauthenticator: Update to 2026-04-08 snapshot
DeltaFile
+11-10mail/roundcube-twofactor_gauthenticator/pkg-plist
+0-12mail/roundcube-twofactor_gauthenticator/files/patch-twofactor__gauthenticator.php
+3-3mail/roundcube-twofactor_gauthenticator/distinfo
+2-2mail/roundcube-twofactor_gauthenticator/Makefile
+16-274 files

OpenBSD/src 226yizOusr.bin/netstat if.c netstat.1

   netstat(1) prints interface multicast counter.

   Use -g option as modifier for -i, -I, and -w to show per interface
   multicast packet counter.  Make -q more specific to suppress 0 for
   values actually printed.

   input and OK claudio@
VersionDeltaFile
1.82+72-27usr.bin/netstat/if.c
1.99+12-3usr.bin/netstat/netstat.1
+84-302 files

LLVM/project a179096llvm/test/CodeGen/AMDGPU hsa-generic-target-features.ll generic-targets-require-v6.ll

AMDGPU: Use subarch in tests using generic arches
DeltaFile
+21-21llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll
+18-18llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll
+1-1llvm/test/CodeGen/AMDGPU/convergent.mir
+40-403 files

LLVM/project fbb1d67llvm/test/CodeGen/AMDGPU pr155452.ll fmuladd.f32.ll, llvm/test/CodeGen/AMDGPU/GlobalISel flat-scratch-init.ll

AMDGPU: Convert tests to use subarch from triples in the file

This set was using target triple in the source rather than command
line arguments.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+51-55llvm/test/CodeGen/AMDGPU/pr155452.ll
+14-15llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
+2-5llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
+2-4llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+2-4llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
+2-3llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll
+73-8617 files not shown
+94-12423 files

LLVM/project 184ffa2llvm/test/tools/llvm-reduce/mir drop-ir-references.mir generic-vreg.mir

AMDGPU: Convert llvm-reduce tests to new subarch triples (62)
DeltaFile
+1-1llvm/test/tools/llvm-reduce/mir/drop-ir-references.mir
+1-1llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
+1-1llvm/test/tools/llvm-reduce/mir/infer-triple.mir
+1-1llvm/test/tools/llvm-reduce/mir/input-file-does-not-exist.mir
+1-1llvm/test/tools/llvm-reduce/mir/instr-reduce-dead-def.mir
+1-1llvm/test/tools/llvm-reduce/mir/multiple-functions.mir
+6-619 files not shown
+25-2525 files

LLVM/project 88acd42llvm/test/Analysis/KernelInfo/enable-kernel-info amdgpu.test, llvm/test/Analysis/KernelInfo/flat-addrspace amdgpu.test

AMDGPU: Migrate KernelInfo tests to new subarch triples (61) (#209867)

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+6-6llvm/test/Analysis/KernelInfo/openmp/amdgpu.ll
+1-1llvm/test/Analysis/KernelInfo/launch-bounds/amdgpu.ll
+1-1llvm/test/Analysis/KernelInfo/enable-kernel-info/amdgpu.test
+1-1llvm/test/Analysis/KernelInfo/openmp/README.md
+1-1llvm/test/Analysis/KernelInfo/flat-addrspace/amdgpu.test
+10-105 files

LLVM/project dab4c91llvm/utils/TableGen RegisterBankEmitter.cpp, llvm/utils/TableGen/Common CodeGenRegisters.cpp CodeGenRegisters.h

[TableGen] Optimize register bank and info emission. (#208297)

Don't go via a BitVector just to a read a single value out of it.
DeltaFile
+18-12llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+9-0llvm/utils/TableGen/Common/CodeGenRegisters.h
+1-3llvm/utils/TableGen/RegisterBankEmitter.cpp
+28-153 files

LLVM/project 4695cd3llvm/include/llvm/ADT GenericCycleImpl.h GenericCycleInfo.h, llvm/lib/Transforms/Utils FixIrreducible.cpp

[CycleInfo] Store cycles in a flat preorder array. NFC

Store cycles by value in one array in cycle-forest preorder, each cycle
immediately followed by its descendants, instead of heap-allocating each
cycle and holding its children in a std::vector<std::unique_ptr<>>.
Child and top-level iteration become pointer arithmetic that skips a
subtree via a new NumDescendants count, and sizeof(GenericCycle) drops
from 72 to 48. GenericCycleInfoCompute builds the forest with temporary
nodes, then flatten() moves it into the array.

GenericCycle still exposes raw pointers into this array. The eventual
goal is to replace them with an opaque handle, so all access goes
through GenericCycleInfo and the storage stays an implementation detail.

Aided by Fable 5

Pull Request: https://github.com/llvm/llvm-project/pull/209981
DeltaFile
+98-111llvm/include/llvm/ADT/GenericCycleImpl.h
+52-71llvm/include/llvm/ADT/GenericCycleInfo.h
+2-9llvm/lib/Transforms/Utils/FixIrreducible.cpp
+152-1913 files

LLVM/project 0411499llvm/test/tools/llvm-split/AMDGPU recursive-search-8.ll large-kernels-merging-weak_odr.ll

AMDGPU: Use amdgpu triples in llvm-split tests (60) (#209866)

Update by regex

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+2-2llvm/test/tools/llvm-split/AMDGPU/recursive-search-8.ll
+2-2llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging-weak_odr.ll
+2-2llvm/test/tools/llvm-split/AMDGPU/large-kernels-merging.ll
+2-2llvm/test/tools/llvm-split/AMDGPU/kernels-dependency-indirect-callee-md.ll
+2-2llvm/test/tools/llvm-split/AMDGPU/recursive-search-2.ll
+1-1llvm/test/tools/llvm-split/AMDGPU/kernels-load-balancing.ll
+11-1117 files not shown
+28-2823 files

LLVM/project 26c38d4llvm/lib/Target/X86 X86InstrInfo.cpp, llvm/test/CodeGen/X86 remove-redundant-cmp-tzcnt.ll remove-redundant-cmp-lzcnt.ll

Revert "[X86] Remove redundant `cmp` before `adc` after `lzcnt` or `tzcnt` (#…"

This reverts commit b1a6a90dff53b60d66f49516938ef47344a45699.
DeltaFile
+0-199llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
+0-186llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
+0-76llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
+0-74llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
+0-12llvm/lib/Target/X86/X86InstrInfo.cpp
+3-1llvm/test/CodeGen/X86/bitcnt-load-with-cmov.ll
+3-5486 files

LLVM/project 0f6a60fllvm/test/CodeGen/MIR/AMDGPU s_waitcnt-errors.mir s_wait_loadcnt_dscnt-errors.mir

AMDGPU: Migrate MIR parser tests to new subarch triples (59) (#209819)

Mechanical migration by script.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+16-16llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt-errors.mir
+12-12llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt-errors.mir
+8-8llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_soft.mir
+8-8llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt.mir
+6-6llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu-errors.mir
+3-3llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-mfi.ll
+53-5328 files not shown
+86-8634 files

LLVM/project 2bc2229llvm/test/DebugInfo/AMDGPU dbg-value-sched-crash.ll pointer-address-space.ll

AMDGPU: Migrate DebugInfo tests to new subarch triples (58) (#209818)

Mostly mechanical by script

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+2-2llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll
+2-2llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
+2-2llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
+2-2llvm/test/DebugInfo/AMDGPU/variable-locations.ll
+2-2llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
+1-1llvm/test/DebugInfo/AMDGPU/bitcast-store-combine-debugloc.ll
+11-115 files not shown
+16-1611 files