[clang][bytecode] Simplify Pointer::getByteOffset() (#223382)
Return `Offset` directly, except for block pointers. This also allows us
to remove `getRawOffset()`.
[clang-tidy] Fix function-cognitive-complexity crash on aliases (#222965)
Only match function definitions that have a body, since declarations
with the alias attribute satisfy `isDefinition()` without providing one.
Fixes #222958
Fix S3 test suites
- point boto3 at the server IP, not localhost
- match the daemon's reload/restart contract and share-root ownership
- give the manage_buckets test a key with SHARING_S3_WRITE
[SystemZ][z/OS] Align constant pool (#222980)
Follow-up to #222128: The call to emit the alignment was places on the
wrong line but the test did not catch it because it checked only the
textual output (which never emits the error message). Fix is to move the
call and update the test.
security/py-nitrokey: Update hidapi version range and add BR_DEPENDS
PR: 297992
Approved by: osa, vvd (Mentors, implicit)
Co-authored-by: Yusuf Yaman <nxjoseph at FreeBSD.org>
[SystemZ][z/OS] Handle constants with initializers with relocations
When the initializer of a constant needs relocations, the constant
cannot be placed into the code section, because the loader needs
a writable section to fixup the relocation.
This change
- sets the relocation model for z/OS to `DynamicNoPIC`, which better
fits the relocation handling than `Static`, and
- treats section kind `ReadOnlyWithRel` like a variable.
[SCEV] Return a SCEVUse from getAddExpr and propagate use flags. (#220007)
Add option to pass SCEVUse-specific flags to getAddExpr and propagate
them through, if valid conservatively. That is, the final expression
adds the same operands (potentially in different order). For example, it
is not valid to propagate the use flags if other (sub-)expressions have
been inlined.
It also includes a few mechanical changes, to update users that still
expected const SCEV *.
This slightly simplifies
https://github.com/llvm/llvm-project/pull/217378, which introduces the
first end-to-end user of SCEVUse.
PR: https://github.com/llvm/llvm-project/pull/220007
[lldb] Fix 32-bit narrowing conversions in the memory cache (#223402)
#222688 broke the 32-bit Arm bots. `lldb-arm-ubuntu` fails to
build `Memory.cpp`:
```
lldb/source/Target/Memory.cpp:187:49: error: non-constant-expression cannot be narrowed from type 'lldb::offset_t' (aka 'unsigned long long') to 'size_t' (aka 'unsigned int') in initializer list [-Wc++11-narrowing]
187 | InsertData(addr, {data_buffer_sp->GetBytes(), data_buffer_sp->GetByteSize()});
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```
`DataBuffer::GetByteSize` returns `lldb::offset_t`, which is always 64
bits wide, while the `llvm::ArrayRef` constructor takes a `size_t`.
Where
`size_t` is 32 bits the conversion narrows, and a braced initializer
list
rejects a narrowing conversion that is not a constant expression. The
same code compiles on a 64-bit host because there `size_t` is just as
wide
[15 lines not shown]
[NVPTX] Add clmad instruction selection (#216412)
Add instruction selection for the PTX 9.3 `clmad.{lo,hi}.u64`
instructions on SM80 and newer targets.
Select `clmad` for `i64` carryless multiply-add expressions represented
as an XOR of `ISD::CLMUL` or `ISD::CLMULH` with an accumulator.
Standalone carryless multiplies are selected as `clmad` with an
immediate zero-accumulator.
The first commit precommits tests showing the existing SelectionDAG
expansion.
[clang-repl] Resolve mapper symbols via lookupAndApply (#223383)
IncrementalExecutor's createSharedMemoryManager resolved the
SharedMemoryMapper instance and wrapper addresses with
EPC.getBootstrapSymbols. For consistency, switch to
lookupAndApply/recordAddr on the bootstrap JITDylib instead.
[llvm-jitlink] Use lookupAndApply for SharedMemoryMapper syms (#223379)
createSharedMemoryManager resolved the SharedMemoryMapper instance and
wrapper addresses with EPC.getBootstrapSymbols. For consistency, switch
to lookupAndApply/recordAddr on the bootstrap JITDylib instead.
[RISCV] Consider vmandn.mm hasAndNot
There's a few generic combines that we can take advantage of if we return true for hasAndNot, e.g. not (setcc x, y, cc) -> setcc x y !cc.
Found with Opus 5
[lldb][Fortran] Added support for base types to DWARFASTParserFortran, tests for DWARFASTParserFortran and a method to get the parser from TypeSystemFortran
throttle reads from the peer socket if more than MSG_PROCESS_LIMIT messages
are ready.
Only MSG_PROCESS_LIMIT messages are process once during a poll loop so it
makes no sense to buffer more messages by keeping the POLLIN enabled.
Once enough messages have been processed the POLLIN is enabled again
and more messages are read in. This should prevent excessive buffering
in the session engine.
OK tb@
[analyzer] Chain checkers in runCheckersForEndFunction (#220970)
The function `runCheckersForEndFunction` had an unusual behavior that it
invoked the callbacks in parallel (introducing a new execution path for
each checker callback that produced a transition), unlike all other
analogous functions, which "chained" the checkers, executing them after
each other.
This behavior was introduced before 2011, when this callback was called
`check::EndPath`, to ensure that the `EndPath` callbacks are _final_ and
nodes created by them end up at the end of the execution path. When
interprocedural analysis (inlining functions) was introduced in 2013,
the callback was renamed to `EndFunction` (to reflect that it also
activates at the end of inlined functions), but the unusual behavior was
preserved.
There were 8 "real" checkers with `check::EndFunction` callbacks, but
most of them only created error nodes or did "nice to have" cleanup, so
the irregular behavior of this callback did not cause visible trouble.
[12 lines not shown]
[ORC] Carry out-of-band errors in SimpleRemoteEPC results (#223378)
ORC Wrapper functions may produce out-of-band error results (e.g. due to
serialization errors), but SimpleRemoteEPC / SimpleRemoteEPCServer never
handled these cases (they incorrectly asserted that they never
appeared).
Update the SimpleRemote protocol to use the TagAddr field (previously
unused for result messages) to encode Result message kinds: either a
Value, or an OutOfBandError. This allows out-of-band errors to flow
across the wire and be passed as results to their callers.
encodeResultMessage and decodeResultMessage implement the format /
handling: out-of-band errors (or failures to deserialize out-of-band
errors) are now passed to handlers as out-of-band error results. An
invalid Result message kind in the TagAddr field results in an
llvm::Error, ending the session.
SimpleRemoteEPCUtilsTest covers both kinds' round-trips, an unrecognized
kind, and a malformed out-of-band payload.
[CIR][AMDGPU] Add support for AMDGCN permlane builtins (#223161)
Adds codegen for the following AMDGCN permlane builtins:
- __builtin_amdgcn_permlane_bcast
- __builtin_amdgcn_permlane_up
- __builtin_amdgcn_permlane_down
- __builtin_amdgcn_permlane_xor
These are lowered to the corresponding `llvm.amdgcn.permlane.*`
intrinsics.
Assisted by: Claude Opus 5
[X86][CodeGen] Support partial-reduce dot products (#205373)
Part of #187779
Lower the llvm.vector.partial.reduce dot product shapes onto the X86 dot
product instructions:
i8 x i8 -> i32: vpdpbusd (AVX512-VNNI, AVX-VNNI)
vpdpbssd / vpdpbuud (AVX-VNNI-INT8, AVX10.2)
i16 x i16 -> i32: vpdpwssd (AVX512-VNNI, AVX-VNNI)
vpdpwsud / vpdpwuud (AVX-VNNI-INT16, AVX10.2)
bf16 x bf16 -> f32: vdpbf16ps (AVX512-BF16)
f16 x f16 -> f32: vdpphps (AVX10.2)
The 128/256-bit shapes, and the 512-bit shapes on targets using 512-bit
registers, are registered as Custom. 512-bit shapes for which only the
VEX
encoding exists are split into two 256-bit dot products, and the
128/256-bit
[13 lines not shown]
powerpc/radix: acquire the pmap lock in mmu_radix_extract()
mmu_radix_extract() walks the page tables without holding the pmap lock,
unlike its hash MMU counterpart moea64_extract(). A concurrent unmap can
free and recycle the page table page being walked, so the read returns
whatever now occupies that memory and the caller gets a physical address
that never existed.
That is how mmu_radix_sync_icache() came to hand a bogus address to
__syncicache() and panic the machine. Commit 1574ca1955f5 worked around
it by taking the pmap lock in mmu_radix_sync_icache(), but the machine
independent callers of pmap_extract() - vm_sync_icache(), proc_rwmem()
and the vslock() paths - remain exposed to the same failure.
Rename the existing body to mmu_radix_extract_locked(), which asserts the
lock, and make mmu_radix_extract() a thin wrapper that acquires it.
mmu_radix_sync_icache() already holds the pmap lock, so it calls the
locked variant directly and neither recurses nor reacquires the lock once
per page.
[5 lines not shown]
