LLVM/project c73bd3elibclc CMakeLists.txt

libclc: Remove old mesa amdgcn targets (#185385)

amdgcn-- was probably dead when clover was being maintained, since
it switched to using amdgcn-mesa-mesa3d. Also remove amdgcn-mesa-mesa3d,
since clover is no longer in mesa.
DeltaFile
+0-2libclc/CMakeLists.txt
+0-21 files

LLVM/project 0be62beflang/test/Lower/Intrinsics date_and_time.f90 dim.f90

[flang][NFC] Converted five tests from old lowering to new lowering (part 27) (#185340)

Tests converted from test/Lower/Intrinsics: date_and_time.f90,
dconjg.f90, dim.f90, dimag.f90, dprod.f90
DeltaFile
+39-27flang/test/Lower/Intrinsics/date_and_time.f90
+17-11flang/test/Lower/Intrinsics/dim.f90
+9-5flang/test/Lower/Intrinsics/dprod.f90
+6-3flang/test/Lower/Intrinsics/dconjg.f90
+6-3flang/test/Lower/Intrinsics/dimag.f90
+77-495 files

OPNSense/core ff2fa25src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api FilterController.php

Firewall: Rules [new]: Fix automatically generated rules not showing label name, minor regression in 963b9a8c (#9911)
DeltaFile
+3-1src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/FilterController.php
+3-11 files

LLVM/project 0da00c3llvm/test/Transforms/LoopVectorize select-cmp.ll iv-select-cmp.ll, llvm/test/Transforms/LoopVectorize/AArch64 conditional-scalar-assignment.ll sve-select-cmp.ll

[LV] Support float and pointer FindLast reductions  (#184101)

This duplicates #182313 with some very small modifications on top, as
@dheaton-arm is unable
to finish the PR and I'm unable to push to his branch.

Expands support for the `FindLast` Reccurence Kind to floating-point and
pointer types, thereby
enabling conditional scalar assignment (CSA) for these types.

Originally authored by @dheaton-arm

---------

Co-authored-by: Damian Heaton <Damian.Heaton at arm.com>
DeltaFile
+210-26llvm/test/Transforms/LoopVectorize/select-cmp.ll
+137-38llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
+143-28llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
+121-30llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
+38-11llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
+13-2llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll
+662-1352 files not shown
+672-1378 files

LLVM/project 6bf37b0utils/bazel/llvm-project-overlay/llvm BUILD.bazel

Fix bazel build after #168421 (#185387)
DeltaFile
+4-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+4-01 files

LLVM/project 38d4509llvm/lib/Target/AMDGPU AMDGPULibCalls.cpp, llvm/test/CodeGen/AMDGPU amdgpu-simplify-libcall-rootn-codegen.ll amdgpu-simplify-libcall-rootn.ll

AMDGPU: Fix selection failure on fast vector rootn (#185035)

This was emitting the raw rcp intrinsic, which will fail for any
vector type. This is an afn context anyway, so just emit fdiv
which will select to rcp but also will undergo type legalization.
DeltaFile
+145-0llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
+40-44llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
+4-1llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+189-453 files

LLVM/project d840396clang/include/clang/Options Options.td, clang/lib/CodeGen CGCall.cpp

clang: Simplify emission of uniform-work-group-size attribute (#185066)
DeltaFile
+28-25clang/test/CodeGenCUDA/convergent.cu
+6-22clang/lib/CodeGen/CGCall.cpp
+9-9clang/test/CodeGenOpenCL/convergent.cl
+3-3clang/test/CodeGenHIP/default-attributes.hip
+2-2clang/test/CodeGenHIP/hip_weak_alias.cpp
+1-1clang/include/clang/Options/Options.td
+49-622 files not shown
+51-648 files

OPNSense/core 16bc9eesrc/opnsense/mvc/app/controllers/OPNsense/Firewall/Api FilterController.php

firewall: merge read of groups and interfaces

They are stored in the same location and used by the interface
field type as such.  This prevents showing unrendered groups
and also displays the consistent label between the rule and
rules selectors.
DeltaFile
+6-13src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/FilterController.php
+6-131 files

OPNSense/core b20af9dsrc/opnsense/mvc/app/controllers/OPNsense/Firewall/Api FilterController.php

Firewall: Rules [new]: Fix automatically generated rules not showing label name, minor regression in https://github.com/opnsense/core/commit/963b9a8caa6dd8dfbba19599621978a4cc941b89
DeltaFile
+3-1src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/FilterController.php
+3-11 files

LLVM/project 0d32195lldb/unittests/Platform PlatformDarwinTest.cpp

[lldb][test][NFC] PlatformDarwinTest.cpp: fix directory creation comment

To be consistent with the other comments in the same test.
DeltaFile
+2-2lldb/unittests/Platform/PlatformDarwinTest.cpp
+2-21 files

OPNSense/plugins 78e3906security/q-feeds-connector/src/opnsense/mvc/app/controllers/OPNsense/QFeeds/Api SettingsController.php

security/q-feeds-connector - on reconfigure, ensure alias cache is flushed to prevent consumers not knowing about our just registered dynamic entries. closes https://github.com/opnsense/plugins/issues/5288
DeltaFile
+3-0security/q-feeds-connector/src/opnsense/mvc/app/controllers/OPNsense/QFeeds/Api/SettingsController.php
+3-01 files

LLVM/project a1866b8mlir/include/mlir/Dialect/LLVMIR LLVMAttrDefs.td, mlir/lib/Target/LLVMIR DebugImporter.cpp

[mlir][llvm] Make name optional for DIBasicTypeAttr and DIStringTypeAttr (#185284)

The name field of DICompositeTypeAttr was already optional, but
DIBasicTypeAttr and DIStringTypeAttr were not handled consistently. Make
the name parameter of both an OptionalParameter to support LLVM debug
info nodes with no name. Update DebugImporter to use getStringAttrOrNull
when translating the name of these types. Add tests for the null-name
cases in the import and export test files.
DeltaFile
+17-20mlir/test/Target/LLVMIR/Import/debug-info.ll
+9-6mlir/test/Target/LLVMIR/llvmir-debug.mlir
+2-2mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+2-1mlir/lib/Target/LLVMIR/DebugImporter.cpp
+30-294 files

LLVM/project 1c1163ellvm/lib/Target/AMDGPU AMDGPULibCalls.cpp, llvm/test/CodeGen/AMDGPU amdgpu-simplify-libcall-rootn-codegen.ll amdgpu-simplify-libcall-rootn.ll

AMDGPU: Fix selection failure on fast vector rootn

This was emitting the raw rcp intrinsic, which will fail for any
vector type. This is an afn context anyway, so just emit fdiv
which will select to rcp but also will undergo type legalization.
DeltaFile
+145-0llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-codegen.ll
+40-44llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
+4-1llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+189-453 files

LLVM/project bdde262libclc/clc/include/clc/collective clc_work_group_reduce.h clc_work_group_reduce.inc, libclc/clc/lib/generic/collective clc_work_group_reduce.inc clc_work_group_reduce.cl

libclc: Add work_group_reduce_* functions (#185368)
DeltaFile
+86-0libclc/clc/lib/generic/collective/clc_work_group_reduce.inc
+30-0libclc/clc/lib/generic/collective/clc_work_group_reduce.cl
+23-0libclc/opencl/lib/generic/collective/work_group_reduce.inc
+20-0libclc/clc/include/clc/collective/clc_work_group_reduce.h
+17-0libclc/clc/include/clc/collective/clc_work_group_reduce.inc
+15-0libclc/opencl/lib/generic/collective/work_group_reduce.cl
+191-02 files not shown
+193-08 files

LLVM/project fef02d4llvm/lib/Target/AMDGPU VOPInstructions.td VOP2Instructions.td, llvm/test/MC/Disassembler/AMDGPU gfx908_mai.txt gfx12_dasm_vop3_from_vop1_dpp16.txt

[AMDGPU] Ignore unused VALU src0/1/2 fields when disassembling (#175182)

This enables a future patch to change the default encoding of these
fields, which are mostly ignored by hardware.

(cherry picked from commit 8099e127cde22a5989515ce940eaa2a0a944d95e)
DeltaFile
+41-41llvm/lib/Target/AMDGPU/VOPInstructions.td
+12-12llvm/lib/Target/AMDGPU/VOP2Instructions.td
+5-5llvm/lib/Target/AMDGPU/VOPCInstructions.td
+8-0llvm/test/MC/Disassembler/AMDGPU/gfx908_mai.txt
+3-3llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+4-0llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
+73-6112 files not shown
+110-6218 files

NetBSD/pkgsrc 7b0Yunfdevel/zix PLIST Makefile

   zix: fix PLIST for newer Sphinx; bump revision
VersionDeltaFile
1.4+5-1devel/zix/PLIST
1.4+2-2devel/zix/Makefile
+7-32 files

LLVM/project 05781f4mlir/lib/Dialect/Bufferization/Extensions ShardingExtensions.cpp, mlir/lib/Dialect/Shard/Transforms ShardingPropagation.cpp

[mlir][shard] Small fixes to partition pass (#185050)

- Empty functions (with no blocks) should are skipped by partition pass,
  blocks with more than one continue to get error-flagged
- fixed ShardingInterfaceImpl of bufferization.materialize_in_destination
DeltaFile
+11-13mlir/lib/Dialect/Bufferization/Extensions/ShardingExtensions.cpp
+10-6mlir/lib/Dialect/Shard/Transforms/ShardingPropagation.cpp
+8-1mlir/test/Dialect/Shard/sharding-propagation-failed.mlir
+29-203 files

LLVM/project 00efc1ellvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

[NFC] Fix spelling mistakes in emitted string replacing word anaylsis with analysis (#185233)

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp had spelling mistake in error
message string.
This PR fixes the spelling mistake and replaces 'anaylsis' with
'analysis'
DeltaFile
+1-1llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+1-11 files

LLVM/project 2b811f4clang/lib/CodeGen CGDebugInfo.cpp, clang/test/DebugInfo/CXX debug-info-constexpr-array.cpp

Reland "[DebugInfo] Emit DW_AT_const_value for constexpr array static members" (#184804)

Use `getElementAsAPInt(`) to read array elements and emit via
`addIntAsBlock()` which handles target endianness correctly, instead of
`getRawDataValues()` which exposes host endianness. This fixes test
failures on big-endian hosts cross-compiling for little-endian targets.

Reland of #182442 with endianness fix.
DeltaFile
+192-0llvm/test/DebugInfo/X86/debug-info-constexpr-array.ll
+53-0clang/test/DebugInfo/CXX/debug-info-constexpr-array.cpp
+52-0clang/lib/CodeGen/CGDebugInfo.cpp
+22-6llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+4-0llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
+323-65 files

LLVM/project 0cbd3d1mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp, mlir/test/Dialect/OpenMP cli-tile.mlir invalid-tile.mlir

Allow tile composition
DeltaFile
+197-0mlir/test/Target/LLVMIR/openmp-cli-tile03.mlir
+52-34mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+70-0mlir/test/Dialect/OpenMP/cli-tile.mlir
+23-4mlir/test/Dialect/OpenMP/invalid-tile.mlir
+342-384 files

FreeBSD/src 8f0ea06sys/netinet6 in6_ifattach.c

netinet6: Fix memory leak on auto_linklocal

release the refcount of link-local prefix information to ensure
it gets freed when the address is deleted.

Reviewed By: zlei, ivy
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D55593

(cherry picked from commit b55bffeaaf9bae5dc7aa21eae441d89c999ebab8)
DeltaFile
+2-2sys/netinet6/in6_ifattach.c
+2-21 files

LLVM/project 2ddac58libclc/clc/include/clc/collective clc_work_group_reduce.h clc_work_group_reduce.inc, libclc/clc/lib/generic/collective clc_work_group_reduce.inc clc_work_group_reduce.cl

libclc: Add work_group_reduce_* functions
DeltaFile
+86-0libclc/clc/lib/generic/collective/clc_work_group_reduce.inc
+30-0libclc/clc/lib/generic/collective/clc_work_group_reduce.cl
+23-0libclc/opencl/lib/generic/collective/work_group_reduce.inc
+20-0libclc/clc/include/clc/collective/clc_work_group_reduce.h
+17-0libclc/clc/include/clc/collective/clc_work_group_reduce.inc
+15-0libclc/opencl/lib/generic/collective/work_group_reduce.cl
+191-02 files not shown
+193-08 files

OPNSense/core fce8850src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api FilterController.php

firewall: reverse order of group listings in interface dropdown

This order is more correct.  But, personally, I dislike the name
"enc0" which needs to be explained and the explanations for WG
and OpenVPN are not very helpful and noisy.  Needs some discussion.
DeltaFile
+1-2src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/FilterController.php
+1-21 files

FreeBSD/ports f435a42sysutils/rust-coreutils distinfo Makefile.crates

sysutils/rust-coreutils: update to 0.7.0

Changelog:      https://github.com/uutils/coreutils/releases/tag/0.7.0
DeltaFile
+113-129sysutils/rust-coreutils/distinfo
+55-63sysutils/rust-coreutils/Makefile.crates
+1-1sysutils/rust-coreutils/Makefile
+169-1933 files

FreeBSD/ports 28220e6x11/slock distinfo Makefile

x11/slock: update to 1.6
DeltaFile
+3-3x11/slock/distinfo
+1-2x11/slock/Makefile
+4-52 files

FreeBSD/ports dfd5f9ex11-wm/dwm distinfo Makefile

x11-wm/dwm: update to 6.8

This fixes a regression in getatomprop(): https://git.suckless.org/dwm/commit/a9aa0d8ffbb548b0b1f9f755557aef2482c0f820.html

Threads:
* https://lists.suckless.org/dev/2601/35936.html
* https://lists.suckless.org/hackers/2601/19537.html
DeltaFile
+3-3x11-wm/dwm/distinfo
+1-1x11-wm/dwm/Makefile
+4-42 files

FreeBSD/src 105869asys/dev/acpi_support acpi_system76.c, sys/modules/acpi/acpi_system76 Makefile

acpi_system76: Add backlight(9) support for keyboard

Reviewed by: wulf
Differential Revision: https://reviews.freebsd.org/D55716
DeltaFile
+145-0sys/dev/acpi_support/acpi_system76.c
+1-0sys/modules/acpi/acpi_system76/Makefile
+146-02 files

FreeBSD/src f87ba45sys/dev/acpi_support acpi_system76.c

acpi_system76: Add support for battary charge thresholds

Reviewed by: wulf
Differential Revision: https://reviews.freebsd.org/D55710
DeltaFile
+116-31sys/dev/acpi_support/acpi_system76.c
+116-311 files

LLVM/project 4879f16clang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode memberpointers.cpp

[clang][bytecode] Check memberpointer exprs for errors (#185370)
DeltaFile
+13-2clang/test/AST/ByteCode/memberpointers.cpp
+7-0clang/lib/AST/ByteCode/Compiler.cpp
+20-22 files

OPNSense/ports 856aa31. UPDATING MOVED, Mk bsd.default-versions.mk

Framework: sync with upstream

Taken from: FreeBSD
DeltaFile
+111-0UPDATING
+40-13Mk/Uses/electron.mk
+35-18Mk/Uses/go.mk
+24-17Mk/Uses/perl5.mk
+10-6Mk/bsd.default-versions.mk
+11-2MOVED
+231-568 files not shown
+255-6814 files