[mlir][memref] Fold memref.reinterpret_cast operations with valid offset or size constants. (#189533)
When encountering an invalid offset or size, we only skip the current
invalid value and continue attempting to fold other valid offsets or
sizes.
[HLSL] Add CalculateLevelOfDetail methods to Texture2D
This adds the CalculateLevelOfDetail and CalculateLevelOfDetailUnclamped
methods to Texture2D using the establish pattern used for other methods.
Assisted-by: Gemini
[mlir][ods] resolve the wrong indent issue (#189277)
The `emitSummaryAndDescComments` is used to generate summary and
description for tablegen generated classes and structs such as Dialects
and Interfaces. The generated summary and description is indented
incorrectly in the output generated file. For example
`NVGPUDialect.h.inc ` looks like the following:
```cpp
namespace mlir::nvgpu {
/// The `NVGPU` dialect provides a bridge between higher-level target-agnostic
/// dialects (GPU and Vector) and the lower-level target-specific dialect
/// (LLVM IR based NVVM dialect) for NVIDIA GPUs. This allow representing PTX
/// specific operations while using MLIR high level dialects such as Memref
/// and Vector for memory and target-specific register operands, respectively.
class NVGPUDialect : public ::mlir::Dialect {
...
};
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[mlir][vector] Drop trailing 1-dims from constant_mask (#187383)
Generalize TransferReadDropUnitDimsPattern to also drop unit dimensions
when `vector::ConstantMaskOp` is used.
Previously TransferReadDropUnitDimsPattern would only drop unit
dimensions when `vector::CreateMaskOp` with a statically known operand
was used.
Assisted-by: Cursor
[lldb][AArch64][Linux] Add tests for SME only support (#165414)
This PR is the tests for #138717. I have split it from implementation as
there is a lot of code, and the two don't really overlap. The tests are
checking what a user will see in LLDB, and only indirectly what happens
in lldb-server.
There are two types of tests, the first is register access tests. These
start in a given mode, where a mode is a combination of the streaming
mode on or off, ZA on or off, and a vector length.
For register access tests I have used two states:
* Streaming mode, ZA on, default vector length
* Non-streaming mode, ZA off, default vector length
(changing mode and vector length is tested in existing SVE+SME tests and
the expression tests I'm adding in this same PR)
The test program:
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ndiff nmap zenma: updated to 7.99
Nmap 7.99 [2026-03-26]
o Integrated many of the most-frequently-submitted IPv4 and IPv6 OS
fingerprints, as well as dozens of updated service fingerprints.
o Upgraded included libraries: OpenSSL 3.0.19, libpcap 1.10.6, libpcre2 10.47,
liblinear 2.50, zlib 1.3.2
o [Windows] Upgraded the included version of Npcap from 1.83 to 1.87, resolving
several crashes and stability-related issues. See https://npcap.com/changelog
o [Zenmap][GH-3182] Zenmap is now distributed as a universal wheel
(zenmap-7.99-py3-none-any.whl) instead of an RPM package so that it can be
installed on any system with Python 3. [Daniel Miller]
o [Ncat][Windows] Limited the number of handles inherited by subprocesses
launched with -e, preventing interference between clients when -e and
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[lldb][docs] Add documentation for AArch64 Linux SME only support (#165415)
As for other features, this is a mixture of user facing decisions and
internal design decisions.
py-setuptools-gettext: added version 0.1.16
This plugin adds build_mo, clean_mo and install_mo subcommands for setup.py as
well as hooking those into standard commands.
[LAA] Catch load/store to invariant address in dependency checker. (#187023)
There are some accesses we cannot easily catch with the existing SSA
based tracking of uniform stores.
Extend the dependency checker to reject accesses the same invariant
address for cases SCEV can prove (distance is zero).
For those cases, we would not generate runtime checks for the
problematic pair, as they are part of the same group.
Note that this adds a new InvariantUnsafe kind, similar to
IndirectUnsafe, although maybe it would be sufficient to just have a
single Unsafe kind, with slight loss of precision.
Fixes https://github.com/llvm/llvm-project/issues/186922.
PR: https://github.com/llvm/llvm-project/pull/187023
[AMDGPU] Fix crash with dead frame indices in debug values (#183297)
When spill slots are eliminated (VGPR-to-AGPR, SGPR-to-VGPR lanes),
debug values referencing these frame indices were not always properly
cleaned up. This caused an assertion failure in getObjectOffset() when
PrologEpilogInserter tried to access the offset of a dead frame object.
The existing debug fixup code in SIFrameLowering and SILowerSGPRSpills
had two limitations:
1. It only checked one operand position, but DBG_VALUE_LIST instructions
can have multiple debug operands with frame indices.
2. It didn't handle all types of dead frame indices uniformly.
Fix by centralizing debug info cleanup in removeDeadFrameIndices(),
which already knows all frame indices being removed. This iterates over
all debug operands using MI.debug_operands().
Assisted-by: Claude Code.
py-sphobjinv: updated to 2.4
2.4
Merge v2.3.1.3 release branch back into main
Fix GitHub badge
Convert most remote inventory fetch tests to use a local server; bump Pythons and dev Sphinx
Lints config maintenance
Implement sphobjinv-textconv and remove CLI implementation section from docs
Update test infra & migrate http:// links to https://
[AMDGPU][SIFoldOperands] Fix OR -1 fold (#189655)
In SIFoldOperands, folding `or x, -1` to `v_mov_b32 -1` removed
`Src1Idx`, which is incorrect because `-1` is in `Src0Idx` (after
canonicalization).
Closes https://github.com/llvm/llvm-project/issues/189677.
