FreeBSD/ports 2fbfcd1databases/ladybug distinfo Makefile

databases/ladybug: Update 0.16.0 => 0.16.1

Changelog:
https://github.com/LadybugDB/ladybug/releases/tag/v0.16.1

PR:             295039
Sponsored by:   UNIS Labs
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+3-3databases/ladybug/distinfo
+1-1databases/ladybug/Makefile
+4-42 files

LLVM/project 5f72b7cllvm/docs AMDGPUUsage.rst, llvm/docs/AMDGPU DeveloperGuideline.rst

[NFC][AMDGPU][Doc] Add developer guideline

This guideline covers topics on top of existing LLVM guideline.
DeltaFile
+442-0llvm/docs/AMDGPU/DeveloperGuideline.rst
+1-0llvm/docs/AMDGPUUsage.rst
+443-02 files

FreeBSD/ports d71af7amisc/crush distinfo Makefile

misc/crush: Update to 0.65.3

Changelog:
- https://github.com/charmbracelet/crush/releases/tag/v0.65.2
- https://github.com/charmbracelet/crush/releases/tag/v0.65.3

Reported by:    GitHub (watch releases)
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+5-5misc/crush/distinfo
+1-1misc/crush/Makefile
+6-62 files

NetBSD/pkgsrc-wip 2100b0dcloudflare-speed-cli distinfo Makefile

cloudflare-speed-cli: update to 0.6.7
DeltaFile
+3-3cloudflare-speed-cli/distinfo
+1-1cloudflare-speed-cli/Makefile
+4-42 files

FreeBSD/ports 2c33242lang/hs-futhark distinfo Makefile

lang/hs-futhark: update 0.25.36 → 0.26.1
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+79-71lang/hs-futhark/distinfo
+36-27lang/hs-futhark/Makefile
+115-982 files

FreeBSD/ports f213cdclang/hs-koka distinfo Makefile

lang/hs-koka: update 3.2.2 → 3.2.3
DeltaFile
+141-159lang/hs-koka/distinfo
+65-62lang/hs-koka/Makefile
+206-2212 files

FreeBSD/ports 3a2108cdevel/py-uv-build distinfo Makefile

devel/py-uv-build: update 0.11.8 → 0.11.10
DeltaFile
+3-3devel/py-uv-build/distinfo
+1-1devel/py-uv-build/Makefile
+4-42 files

FreeBSD/ports 85d35c3net/wstunnel distinfo Makefile

net/wstunnel: update 10.5.4 → 10.5.5
DeltaFile
+3-3net/wstunnel/distinfo
+1-1net/wstunnel/Makefile
+4-42 files

FreeBSD/ports 75019f9www/cpp-httplib distinfo Makefile

www/cpp-httplib: update 0.43.2 → 0.43.3
DeltaFile
+3-3www/cpp-httplib/distinfo
+1-1www/cpp-httplib/Makefile
+4-42 files

FreeBSD/ports b337122editors/cpeditor distinfo Makefile

editors/cpeditor: update 7.0.1 → 7.1.1
DeltaFile
+9-7editors/cpeditor/distinfo
+6-4editors/cpeditor/Makefile
+15-112 files

FreeBSD/ports 07e9d69devel/py-uv distinfo Makefile, devel/uv distinfo Makefile.crates

devel/{,py-}uv: update 0.11.8 → 0.11.10
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+55-57devel/uv/distinfo
+26-27devel/uv/Makefile.crates
+3-3devel/py-uv/distinfo
+1-1devel/uv/Makefile
+1-1devel/py-uv/Makefile
+86-895 files

FreeBSD/ports d43f5c2sysutils/mise distinfo Makefile

sysutils/mise: update 2026.5.0 → 2026.5.1
DeltaFile
+209-215sysutils/mise/distinfo
+104-107sysutils/mise/Makefile
+313-3222 files

LLVM/project 7df4736clang/lib/CIR/CodeGen CIRGenBuiltinRISCV.cpp, clang/test/CIR/CodeGenBuiltins/RISCV riscv-zbkb.c

[CIR][RISCV] Support zbkb builtin codegen (#195401)

Include 4 builtins: __builtin_riscv_brev8_32, __builtin_riscv_brev8_64,
__builtin_riscv_zip_32, __builtin_riscv_unzip_32.
DeltaFile
+50-0clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zbkb.c
+12-3clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+62-32 files

LLVM/project 36122ebllvm/lib/Target/RISCV RISCVCallingConv.cpp

[RISCV] Rename and invert UseGPRForF16_F32/UseGPRForF16_F32. (#195971)

Rename to AllowFPR. We used to set these flags when we ran out of FPRs,
but we haven't for a while. I think rephrasing as allow FPR is a bit
clearer.
DeltaFile
+13-15llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+13-151 files

LLVM/project 9dd7c73llvm/lib/Target/RISCV RISCVInstrInfoP.td

[RISCV][P-ext] Remove VXSAT from SHL/SHLR/SHA/SHAR. Add to PSAS and PSSA. (#195488)
DeltaFile
+10-8llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+10-81 files

LLVM/project 6201b4ebolt/include/bolt/Profile DataAggregator.h DataReader.h, bolt/lib/Profile DataAggregator.cpp DataReader.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.4
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+18-55bolt/lib/Profile/DataAggregator.cpp
+1-13bolt/include/bolt/Profile/DataAggregator.h
+9-0bolt/include/bolt/Profile/DataReader.h
+4-0bolt/lib/Profile/DataReader.cpp
+32-684 files

NetBSD/pkgsrc-wip 7bc0729py-ksef2 PLIST distinfo

py-ksef2: update to 0.13.1
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+339-3py-ksef2/PLIST
+3-3py-ksef2/distinfo
+2-1py-ksef2/Makefile
+344-73 files

LLVM/project 2e4c72ellvm/docs CodingStandards.rst

[RFC][Docs] Clarify brace omission for single-line bodies

Update the Coding Standards brace guidance to emphasize that braces should be
omitted only for simple bodies that do not wrap across multiple physical lines.
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+22-9llvm/docs/CodingStandards.rst
+22-91 files

LLVM/project d4c0c7bllvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV returnaddress.ll

[SPIRV] Dummy implementation of the `returnaddress` and `frameaddress` intrinsics (#195976)

The SPIR-V specification doesn't define any operations for the
return and frame address. The valid implementation in this case is to
produce a null pointer.

Assisted-by: Claude Opus 4.6 <noreply at anthropic.com>
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+26-0llvm/test/CodeGen/SPIRV/returnaddress.ll
+9-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+35-02 files

LLVM/project 75428e9llvm/lib/Target/SPIRV SPIRVPrepareFunctions.cpp SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort abort-opencl-source.ll abort-post-terminator-suppression.ll

[SPIRV] Add support for SPV_KHR_abort extension (#193037)

This commit adds support for the SPV_KHR_abort extension in the SPIRV
backend. The extension allows shaders to abort execution with a custom
message.

Assisted-by: Claude Opus 4.7 <noreply at anthropic.com>

---------

Co-authored-by: Marcos Maronas <mmaronas at amd.com>
DeltaFile
+113-2llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+91-5llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+81-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/abort-opencl-source.ll
+68-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/abort-post-terminator-suppression.ll
+62-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/abort-opencl.ll
+59-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/no-abort-unaffected.ll
+474-724 files not shown
+1,178-1130 files

LLVM/project a8b0124llvm/include/llvm/TargetParser RISCVTargetParser.h, llvm/lib/Target/RISCV RISCVInstrInfoZvvmm.td

[RISCV][MC] Add experimental `Zvvmm` MC support (#193956)

Add initial MC-layer support for `Zvvmm` from the experimental [RISC-V
Integrated Matrix
Extension](https://github.com/riscv/integrated-matrix-extension/blob/d2e64b4922f5c2c416761f3c7c997d4f0cf814d9/src/integrated-matrix.adoc)
(version
[2026-04-23](https://github.com/riscv/integrated-matrix-extension/releases/tag/riscv-isa-release-d2e64b4-2026-04-23))

This patch:
- Adds the experimental `zvvmm` 0.1 extension feature, depending on
`zve32x`.
- Adds assembler/disassembler definitions for the integer matrix
multiply-accumulate instructions:
  - `vmmacc.vv`
  - `vwmmacc.vv`
  - `vqmmacc.vv`
  - `v8wmmacc.vv`
- Adds IME vtype helper modeling in `RISCVVType`, covering lambda
encoding/decoding, IME vtype field masks,

    [3 lines not shown]
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+89-0llvm/lib/TargetParser/RISCVTargetParser.cpp
+49-0llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
+37-0llvm/lib/Target/RISCV/RISCVInstrInfoZvvmm.td
+29-0llvm/include/llvm/TargetParser/RISCVTargetParser.h
+27-0llvm/test/MC/RISCV/rvv/zvvmm.s
+18-0llvm/test/MC/RISCV/rvv/zvvmm-invalid.s
+249-07 files not shown
+266-113 files

FreeBSD/ports 3d367b0devel/py-pytz distinfo Makefile

devel/py-pytz: Update to 2026.2
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+3-3devel/py-pytz/distinfo
+1-2devel/py-pytz/Makefile
+4-52 files

LLVM/project d9958cbmlir/lib/Dialect/AMDGPU/Transforms FoldMemRefsOps.cpp, mlir/test/Dialect/AMDGPU amdgpu-fold-memrefs.mlir

fold memref global async to lds

Signed-off-by: Eric Feng <Eric.Feng at amd.com>

nits

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
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+50-0mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
+40-0mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
+90-02 files

LLVM/project f5186aemlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp

format

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
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+5-2mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+5-21 files

LLVM/project e1ee69bmlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp

nit

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
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+2-2mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+2-21 files

LLVM/project 51d2a66clang/test/Analysis/Scalable/ssaf-analyzer analyzer.test, clang/test/Analysis/Scalable/ssaf-analyzer/Inputs lu.json

[clang][ssaf] Add `clang-ssaf-analyzer` (#188881)

This patch introduces `clang-ssaf-analyzer`, a new SSAF tool that runs whole-program analyses over an `LUSummary` and writes the resulting `WPASuite` to an output file.
DeltaFile
+141-0clang/test/Analysis/Scalable/ssaf-analyzer/analyzer.test
+134-0clang/tools/clang-ssaf-analyzer/SSAFAnalyzer.cpp
+126-0clang/test/Analysis/Scalable/ssaf-analyzer/Inputs/lu.json
+90-0clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/all.json
+81-0clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/both.json
+70-0clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/pairs.json
+642-015 files not shown
+931-021 files

LLVM/project d724231mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp, mlir/test/Conversion/AMDGPUToROCDL sparse-mfma-gfx950.mlir

support gfx942 bf16 sparse mfma in gfx950

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+7-5mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+10-1mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma-gfx950.mlir
+17-62 files

LLVM/project b8362b2clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow PointerFlowExtractor.cpp

[SSAF] Fix -Wunused-variable (#195975)

Add [[maybe_unused]] given the operation is side effecting/returns
multiple values.
DeltaFile
+1-1clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
+1-11 files

LLVM/project 2c27433libc/include sched.yaml, libc/test/include sched_test.cpp

[libc][sched] Fix generated scheduler prototypes (#195332)

Fixes generated <sched.h> prototypes for
sched_getscheduler/sched_setscheduler and adds compile-time
public-header coverage
DeltaFile
+8-0libc/test/include/sched_test.cpp
+2-2libc/include/sched.yaml
+10-22 files

FreeBSD/src 081d3absys/dev/ichsmb ichsmb_pci.c

ichsmb: add Ice Lake-LP (0x34a3) and Ice Lake-N (0x38a3) SMBus device IDs

Add PCI device IDs for two Ice Lake PCH SMBus controller variants:
- 0x34a3 (Ice Lake-LP), previously listed as the generic "Ice Lake" entry (ID_ICELAKE), renamed to ID_ICELAKELP for clarity.
- 0x38a3 (Ice Lake-N), a separate PCH variant not previously supported.

Reviewed by:    adrian
Differential Revision:  https://reviews.freebsd.org/D56732
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+6-3sys/dev/ichsmb/ichsmb_pci.c
+6-31 files