FreshBSD

FreeNAS/freenas b4cac52 — src/middlewared/middlewared/plugins auth.py

2026-01-13 01:29:58 UTC by Andrew Walker on ⎇

awalker_testing

Fix

Delta		File
+1	-1	src/middlewared/middlewared/plugins/auth.py
+1	-1	1 files

FreeBSD/ports 85819a4 — math/Imath Makefile

2026-01-13 01:29:28 UTC by Matthias Andree (mandree) on ⎇

main

math/Imath: default-enable PYTHON

Required for upcoming new port,
Reported by:    Martin Filla

Delta		File
+2	-1	math/Imath/Makefile
+2	-1	1 files

LLVM/project 5d45dfd — llvm/lib/CodeGen CodeGenPrepare.cpp

2026-01-13 01:27:39 UTC by Mircea Trofin on ⎇

users/mtrofin/10-06-_wip_profcheck_codegen_prepare

[WIP][profcheck] Codegen Prepare

Delta		File
+15	-2	llvm/lib/CodeGen/CodeGenPrepare.cpp
+15	-2	1 files

LLVM/project a01b7c2 — . .gitignore

2026-01-13 01:27:05 UTC by Daniil Fukalov via GitHub on ⎇

main

[LLVM] Ignore two Cursor specific files. (#175683)

Delta		File
+2	-0	.gitignore
+2	-0	1 files

LLVM/project ed9f5c9 — llvm/lib/Target/RISCV RISCVInstrInfoVPseudos.td, llvm/test/tools/llvm-mca/RISCV/SiFiveX390 vector-fp.s

2026-01-13 01:24:57 UTC by Min-Yih Hsu via GitHub on ⎇

main

[RISCV] Add the missing SEW search table field to vector FMA instructions (#175646)

We split vector floating point FMA (pseudo) instructions' opcodes by SEW
since c6b7944be4dfbb1fb35301c670812726845acaa7 , but forgot to populate
their `SEW` field, which is used by various search tables. This results
in incorrect pseudo instruction opcodes lookup -- and to a larger
extent, incorrect scheduling class lookups -- in llvm-mca. This patch
fixes such issue.

Delta		File
+129	-129	llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s
+48	-48	llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test
+32	-32	llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test
+1	-1	llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+210	-210	4 files

LLVM/project 438f887 — llvm CMakeLists.txt

2026-01-13 01:18:51 UTC by Reid Kleckner via GitHub on ⎇

main

[cmake] Make CMAKE_BUILD_TYPE=Release the default (#174520)

Currently, we report a fatal error if the user leaves CMAKE_BUILD_TYPE
blank. This was implemented in https://reviews.llvm.org/D124153 /
350bdf9227ceb , based on this RFC:

https://discourse.llvm.org/t/rfc-select-a-better-linker-by-default-or-warn-about-using-bfd/61899/1

Tom Stellard mentioned that he'd like to revisit this on Discord, and
Aiden, myself, and apparently most people on the original RFC agree, so
I'm proposing we do it. However, on the review, several folks objected
and insisted that Debug was a better default. I want to reopen the
question.

I think we've made the wrong tradeoff. I wish Debug builds worked out of
the box on most systems, but they don't, and LLVM has only gotten bigger
over the last four years, making the build scalability problems of Debug
builds worse. I think we should optimize our build configuration for new
developers, not experienced longtime contributors who are invested

    [9 lines not shown]

Delta		File
+3	-8	llvm/CMakeLists.txt
+3	-8	1 files

FreeNAS/freenas bea94ed — src/middlewared/middlewared/plugins/directoryservices_ connection.py, src/middlewared/middlewared/plugins/network_ common.py global_config.py

2026-01-13 01:18:42 UTC by Mark Grimes on ⎇

fix-network-domain-name-in-ds-mode

Avoid import of aiohttp, move DEFAULT_DOMAIN_NAME from utils/network.py to plugins/network_/common.py

Delta		File
+3	-0	src/middlewared/middlewared/plugins/network_/common.py
+0	-3	src/middlewared/middlewared/utils/network.py
+1	-1	src/middlewared/middlewared/plugins/directoryservices_/connection.py
+1	-1	src/middlewared/middlewared/plugins/network_/global_config.py
+5	-5	4 files

LLVM/project 2329d04 — llvm/test/CodeGen/AArch64 arm64-homogeneous-prolog-epilog-tail-call.mir

2026-01-13 01:16:54 UTC by Mircea Trofin via GitHub on ⎇

main

Remove cleanup of incorrect output in test dir (#171256)

This follows #171255 , removing the cleanup line.

Delta		File
+0	-1	llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir
+0	-1	1 files

LLVM/project a7ad427 — llvm/lib/Transforms/Vectorize VPlan.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize tripcount.ll

2026-01-13 01:15:34 UTC by Mircea Trofin on ⎇

users/mtrofin/01-08-capture_weights

capture weights

Delta		File
+23	-6	llvm/lib/Transforms/Vectorize/VPlan.cpp
+9	-6	llvm/test/Transforms/LoopVectorize/tripcount.ll
+2	-0	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+34	-12	3 files

LLVM/project 0dcd112 — llvm/test/Transforms/LoopVectorize tripcount.ll

2026-01-13 01:14:49 UTC by Mircea Trofin on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[NFC] use UTC for LoopVectorize/tripcount.ll

Delta		File
+213	-29	llvm/test/Transforms/LoopVectorize/tripcount.ll
+213	-29	1 files

LLVM/project f9c561b — llvm/lib/Transforms/Utils LoopUtils.cpp, llvm/test/Transforms/LoopVectorize branch-weights.ll

2026-01-13 01:12:35 UTC by Mircea Trofin via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[profcheck] Fix encoding of 0 loopEstimatedTrip count (#174896)

We currently encode an estimated trip count of 0 as the latch having branch probabilities 0-0. That's an invalid pair of weights. The probability of a branch is computed as a fraction of its corresponding weight and the sum of the weights. In fact, `BranchProbabilityInfo::calcMetadataWeights` will convert this to a 1-1, meaning 50% - 50%, which isn't quite what we want. To indicate the loop is never taken, we just need to initialize the exit probability to non-zero (hence, 1)

Related: https://reviews.llvm.org/D67905

Issue #147390

Delta		File
+5	-5	llvm/test/Transforms/LoopVectorize/AArch64/check-prof-info.ll
+4	-1	llvm/lib/Transforms/Utils/LoopUtils.cpp
+2	-2	llvm/test/Transforms/LoopVectorize/branch-weights.ll
+1	-1	llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
+12	-9	4 files

LLVM/project 26624d5 — clang/include/clang/Basic BuiltinsAMDGPU.def, clang/test/CodeGenOpenCL amdgpu-features.cl amdgpu-cluster-dims.cl

2026-01-13 01:10:09 UTC by Shoreshen via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[AMDGPU]Add specific instruction feature for multicast load (#175503)

Delta		File
+7	-7	clang/include/clang/Basic/BuiltinsAMDGPU.def
+11	-1	llvm/lib/Target/AMDGPU/AMDGPU.td
+2	-2	clang/test/CodeGenOpenCL/amdgpu-features.cl
+2	-2	clang/test/CodeGenOpenCL/amdgpu-cluster-dims.cl
+2	-2	llvm/lib/Target/AMDGPU/FLATInstructions.td
+3	-0	llvm/lib/Target/AMDGPU/GCNSubtarget.h
+27	-14	1 files not shown
+28	-14	7 files

LLVM/project a9037dc — orc-rt Maintainers.md

2026-01-13 01:08:27 UTC by Lang Hames via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[orc-rt] Add Maintainers.md. (#175691)

Delta		File
+10	-0	orc-rt/Maintainers.md
+10	-0	1 files

LLVM/project 587bac6 — llvm/lib/Target/RISCV RISCVMakeCompressible.cpp, llvm/test/CodeGen/RISCV make-compressible-xqci.mir

2026-01-13 01:04:18 UTC by Sudharsan Veeravalli via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[RISCV] Adjust base cost for Xqcilo loads/stores in RISCVMakeCompressible (#175572)

We only need two uses in Xqcilo load/store instructions for the base
adjustment to be profitable as compared to three uses in the base
load/store instructions.

Delta		File
+48	-5	llvm/test/CodeGen/RISCV/make-compressible-xqci.mir
+38	-7	llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+86	-12	2 files

LLVM/project c6fc6ad — clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 avx512vlvp2intersect-builtins.c avx512vp2intersect-builtins.c

2026-01-13 01:04:01 UTC by Vishruth Thimmaiah via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[CIR][X86] Add support for `intersect` builtins (#172554)

adds support for the
`__builtin_ia32_vp2intersect_d`/`__builtin_ia32_vp2intersect_q` x86
builtins.

Part of #167765

---------

Signed-off-by: vishruth-thimmaiah <vishruththimmaiah at gmail.com>

Delta		File
+161	-0	clang/test/CIR/CodeGenBuiltins/X86/avx512vlvp2intersect-builtins.c
+77	-0	clang/test/CIR/CodeGenBuiltins/X86/avx512vp2intersect-builtins.c
+64	-10	clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+302	-10	3 files

LLVM/project e4b2201 — clang/test/CodeGen/AMDGPU nullptr-in-different-address-spaces.cpp

2026-01-13 01:03:43 UTC by Shilei Tian on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[FIX] Add target requirement in `clang/test/CodeGen/AMDGPU/nullptr-in-different-address-spaces.cpp`

Delta		File
+1	-0	clang/test/CodeGen/AMDGPU/nullptr-in-different-address-spaces.cpp
+1	-0	1 files

LLVM/project 1b69dfe — flang CMakeLists.txt, flang/include/flang/Semantics expression.h

2026-01-13 01:02:53 UTC by Peter Klausler via GitHub on ⎇

main

[flang] Turn -Werror back off for Flang build (#175689)

Different build environments are picking up warnings that my testing
didn't expose; turn -Werror back off.
(And also delete an unused data member that was triggering some MSVC
warnings.)

Delta		File
+1	-1	flang/CMakeLists.txt
+0	-1	flang/include/flang/Semantics/expression.h
+1	-2	2 files

FreeBSD/ports fa5c456 — net-mgmt/librenms distinfo Makefile

2026-01-13 00:54:28 UTC by Dan Langille (dvl) on ⎇

main

net-mgmt/librenms: Update to 26.1.1

re: https://github.com/librenms/librenms/releases/tag/26.1.1

Delta		File
+5	-5	net-mgmt/librenms/distinfo
+2	-2	net-mgmt/librenms/Makefile
+7	-7	2 files

LLVM/project 9596c92 — llvm/lib/Target/RISCV RISCVInstrInfo.cpp, llvm/test/CodeGen/RISCV zilsd-spill.ll zdinx-spill.ll

2026-01-13 00:48:21 UTC by Sudharsan Veeravalli via GitHub on ⎇

main

[RISCV] Use LD_RV32/SD_RV32 for spills and reloads when Zilsd is enabled (#153595)

We are currently only using `PseudoRV32ZdinxSD/LD` for spills and
reloads when the register class is `GPRPairRegClass` . However, we can
use `LD_RV32/SD_RV32` when the `Zilsd` extension is enabled and certain
alignment requirements are met.

Delta		File
+220	-0	llvm/test/CodeGen/RISCV/zilsd-spill.ll
+147	-36	llvm/test/CodeGen/RISCV/zdinx-spill.ll
+18	-6	llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+385	-42	3 files

LLVM/project 30596a0 — clang/lib/Basic/Targets AMDGPU.h, clang/test/CodeGen/AMDGPU nullptr-in-different-address-spaces.cpp

2026-01-13 00:47:27 UTC by Shilei Tian via GitHub on ⎇

main

[Clang][AMDGPU] Get correct nullptr value for AS3 and AS5 (#175610)

Delta		File
+55	-0	clang/test/CodeGen/AMDGPU/nullptr-in-different-address-spaces.cpp
+15	-0	llvm/include/llvm/Support/AMDGPUAddrSpace.h
+7	-5	clang/lib/Basic/Targets/AMDGPU.h
+77	-5	3 files

LLVM/project 12ecbfb — compiler-rt/test lit.common.cfg.py

2026-01-13 00:44:41 UTC by Andrew Haberlandt via GitHub on ⎇

main

[Darwin] [compiler-rt] Normalize DYLD_LIBRARY_PATH to workaround LD bug (#175685)

There is an issue in certain versions of LD which causes the wrong
libLTO to be used if the DYLD_LIBRARY_PATH is not normalized.

Will fix these failures:
```
AddressSanitizer-x86_64-darwin.TestCases/Darwin.odr-lto.cpp
AddressSanitizer-x86_64h-darwin.TestCases/Darwin.odr-lto.cpp
```

https://green.lab.llvm.org/job/llvm.org/job/clang-stage1-cmake-RA-incremental/13428/

rdar://168024431

Delta		File
+6	-0	compiler-rt/test/lit.common.cfg.py
+6	-0	1 files

LLVM/project 998e0ae — flang/test/Semantics/OpenMP linear-clause01.f90

2026-01-13 00:39:38 UTC by Eugene Epshteyn via GitHub on ⎇

main

[flang] Temporarily disabled a check in a test that was breaking buildbots (#175684)

PR https://github.com/llvm/llvm-project/pull/175383 had breaking test
Semantics/OpenMP/linear-clause01.f90

I disabled problematic part of the test for now to let the builds pass.
I will file the issue for PR author to fix the test.

Delta		File
+5	-3	flang/test/Semantics/OpenMP/linear-clause01.f90
+5	-3	1 files

LLVM/project 393ba8c — clang/docs ReleaseNotes.rst, clang/lib/Tooling Tooling.cpp

2026-01-13 00:33:42 UTC by mitchell via GitHub on ⎇

main

[clang][Tooling] Fix assertion failure when processing CUDA files (#173762)

Running clang-tidy on CUDA files without specifying `--cuda-host-only`
or `--cuda-device-only` would trigger an assertion failure in
`Actions.size() > 1`, a related discussion:
https://github.com/llvm/llvm-project/pull/173699#discussion_r2649279975.

This occurred because the Clang Driver generates a single top-level
`OffloadAction` in `-fsyntax-only`, `-E`, `-M`. This commit removes the
overly strict assertions.

Closes #173777

Delta		File
+8	-7	clang/lib/Tooling/Tooling.cpp
+14	-0	clang/unittests/Tooling/ToolingTest.cpp
+4	-1	clang/docs/ReleaseNotes.rst
+26	-8	3 files

FreeNAS/freenas f8e9363 — src/middlewared/middlewared/plugins/directoryservices_ connection.py, src/middlewared/middlewared/plugins/network_ global_config.py

2026-01-13 00:33:01 UTC by Mark Grimes on ⎇

fix-network-domain-name-in-ds-mode

If joined to an AD or IPA domain the 'domain' field in the network configuration cannot be changed.
Renamed the test_ssh.py CI module to Test_directory_services_basic.py and added a CI test for domain name changing.

Delta		File
+70	-0	tests/directory_services/test_directory_services_basic.py
+0	-27	tests/directory_services/test_ssh.py
+20	-5	src/middlewared/middlewared/plugins/network_/global_config.py
+9	-0	src/middlewared/middlewared/plugins/directoryservices_/connection.py
+3	-0	src/middlewared/middlewared/utils/network.py
+102	-32	5 files

LLVM/project 552a696 — llvm/test/ExecutionEngine/JITLink/AArch64 backtrace-symbolication.s

2026-01-13 00:32:58 UTC by Lang Hames via GitHub on ⎇

main

[llvm-jitlink] Remove flaky testcase. (#175680)

On some systems, backtraces contain addresses with their high bits set*.
These high bits prevent symbolication using the JIT symbol table. Since
this test is for a best-effort debugging / diagnosis tool it seems best
to remove the test until/unless we can get it passing on all systems, or
find some way to identify systems that will fail.

See discussion in https://github.com/llvm/llvm-project/pull/175537.

* Note that the test does not use PAC or pointer tagging -- the high
bits are coming from somewhere else. Possibly libunwind, but that is
just speculation.

Delta		File
+0	-41	llvm/test/ExecutionEngine/JITLink/AArch64/backtrace-symbolication.s
+0	-41	1 files

LLVM/project af4427d — .github/workflows commit-create-issue.py commit-access-review.yml

2026-01-13 00:31:52 UTC by Tom Stellard via GitHub on ⎇

main

workflows/commit-access-review: Automatically create the issue (#175400)

We had been doing this manually, and this will be a lot more convenient.

Delta		File
+42	-0	.github/workflows/commit-create-issue.py
+9	-0	.github/workflows/commit-access-review.yml
+51	-0	2 files

OpenBSD/ports XPK48A5 — math/py-scikit-learn Makefile, math/py-scikit-learn/patches patch-pyproject_toml

2026-01-13 00:19:03 UTC by tb on ⎇

HEAD

   py-scikit-learn: drop upper bound on numpy to unbreak build

Version	Delta		File
1.1	+12	-0	math/py-scikit-learn/patches/patch-pyproject_toml
1.29	+1	-0	math/py-scikit-learn/Makefile
	+13	-0	2 files

LLVM/project ec13b59 — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 bit-test.ll

2026-01-13 00:18:38 UTC by Peter Collingbourne on ⎇

users/pcc/spr/aarch64-add-tbztbnz-matcher-for-x-1-y

Address review comments

Created using spr 1.3.6-beta.1

Delta		File
+18	-15	llvm/test/CodeGen/AArch64/bit-test.ll
+5	-6	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+23	-21	2 files

LLVM/project 766b446 — flang/lib/Semantics check-omp-loop.cpp, flang/test/Semantics/OpenMP simd-linear-array.f90 linear-clause01.f90

2026-01-13 00:15:56 UTC by Eugene Epshteyn via GitHub on ⎇

revert-175383-fix-flang-openmp-linear-array-crash

Revert "[flang][OpenMP] Fix crash when arrays used in LINEAR clause (#175383)"

This reverts commit b76c84e70f4fb420b26b3887d9270fdb90d41933.

Delta		File
+0	-80	flang/test/Semantics/OpenMP/simd-linear-array.f90
+0	-9	flang/lib/Semantics/check-omp-loop.cpp
+0	-2	flang/test/Semantics/OpenMP/linear-clause01.f90
+0	-2	flang/test/Semantics/OpenMP/linear-iter.f90
+0	-1	flang/test/Semantics/OpenMP/cray-pointer-usage.f90
+0	-94	5 files

FreeBSD/ports cf54c6e — devel/gamin Makefile

2026-01-13 00:13:18 UTC by Daniel Engberg (diizzy) on ⎇

main

devel/gamin: Unbreak and improve port

* Update MASTER_SITES and WWW
* Rework port Makefile to follow porters handbook more closely

Initial patch submitted by mew14930xvi

PR:             292327
Reported by:    Evgenii Khramtsov <2khramtsov at gmail.com>

Delta		File
+32	-39	devel/gamin/Makefile
+32	-39	1 files