[Clang][X86] Introduce Clang ABI Gate for MSVC alignment (#210305)
On x86_64-windows-msvc after 8ecec455183f, clang applies the MSVC
size-based global-alignment scheme (Microsoft64BitMinGlobalAlign) and
does not apply the Sys V "large array" alignment increase. Users may
want to preserve the earlier ABI for compatibility with objects produced
by older clang releases.
Gate this behavior on the Clang ABI compatibility level. When
`-fclang-abi-compat=22` (or lower) is in effect,
MicrosoftX86_64TargetInfo restores LargeArrayMinWidth/LargeArrayAlign to
128 and getMinGlobalAlign skips the Microsoft64BitMinGlobalAlign step,
matching the older alignment choices.
Assisted by Claude (Anthropic).
py-mistune: updated to 3.3.4
3.3.4
* Harden inline parsing against deeply nested and adversarial link, image,
emphasis, formatting, math, and reference inputs.
* Improve performance for repeated link suffixes, dense emphasis, unclosed
formatting markers, inline spoilers, and adjacent ruby tokens.
* Refactor the inline parser into dedicated emphasis and link modules.
* Escape literal ``*``/``_`` emphasis markers in the Markdown renderer so
round-tripping escaped text does not re-introduce emphasis.
[SPIRV] Lower llvm.ldexp via OpenCL/GLSL ldexp ext-inst (#195402)
## Summary
The SPIR-V backend handled only `G_STRICT_FLDEXP` (from
`llvm.experimental.constrained.ldexp`). Plain `Intrinsic::ldexp` lowers
to `G_FLDEXP` in `IRTranslator.cpp`, so device code that calls `ldexp()`
(or any libcall lowered to `llvm.ldexp.*`, including `scalbn`,
`scalbln`, integer-exponent `exp2`) failed legalization with `unable to
legalize instruction: G_FLDEXP`.
## Change
- `SPIRVLegalizerInfo.cpp`: extend the existing legalizer rule from
`{G_STRICT_FLDEXP}` to `{G_FLDEXP, G_STRICT_FLDEXP}`, sharing the same
`(allFloatScalarsAndVectors, allIntScalars)` cartesian product.
- `SPIRVInstructionSelector.cpp`: add a `case TargetOpcode::G_FLDEXP:`
next to the strict case, both selecting `selectExtInst(..., CL::ldexp,
GL::Ldexp)`. The `GL::Ldexp` opcode (53) was already declared in
[10 lines not shown]
py-discogs-client: updated to 2.9
2.9
Improved / Changed
Bump ubuntu version in build workflow
New
A new configuration option trust_per_page allows controlling how pagination is handled
Update threadingbuildingblocks (oneTBB) to 2023.1.0
- XXX cargo culted flag removal
- colloidal suspension simulation runs a tad faster
Highlights:
- Significantly improved scalability for concurrent ordered containers
on systems with many threads. This change results in greater than
3x performance for some use cases.
- Fixed ``concurrent_queue`` and ``concurrent_bounded_queue``
capacity preserving on copying, moving, and swapping
(https://github.com/uxlfoundation/oneTBB/issues/1598).
- Fixed issues with Flow Graph priorities when using limited
concurrency nodes (https://github.com/uxlfoundation/oneTBB/issues/1595).
[15 lines not shown]
[Polly] Fix memory leak in DependenceAnalysis::Result::abandonDepende… (#211514)
abandonDependences() uses unique_ptr::release() which releases
ownership without freeing the Dependences object, causing a memory
leak. Use unique_ptr::reset() instead to properly delete the object
before nullifying the pointer.
The issue was found when AddressSanitizer is enabled in the build.
igc: Disable ASPM L1.2 on I226 to prevent RX stalls
PR: 279245
I226 parts advertise support for the PCIe L1.2 link substate, but a
hardware erratum makes the exit latency from that low-power state
longer than the packet buffer can absorb under load. This stalls the
inbound packet stream. Disabling ASPM system-wide (BIOS or OS ASPM
policy) does not fix it. The L1.2 enable bit must be cleared directly
in the device's own PCIe L1 PM extended capability.
Add igc_is_device_id_i226() to identify affected parts and
igc_disable_broken_aspm_l1_2() to clear the ASPM L1.2 and PCI-PM L1.2
enable bits on attach and after resume, since PCIe config space can be
reset across a suspend/resume cycle.
Ported from the Linux igc driver:
0325143b59c6 igc: disable L1.2 PCI-E link substate to avoid
[5 lines not shown]
pci: Add L1 PM definitions
Add register/bit definitions for the L1 PM substates capability
(PCIZ_L1PM) to pcireg.h.
Signed-off-by: Michael Adler <madler at tapil.com>
[libc++] Update release procedure for libc++ & friends (#210383)
The release procedure implied that some tasks were done by the release
manager, but in practice they are done by the libc++ developers.
Also, mention using the `llvm-premerge-libcxx-release-runners` runner
set on the release branch, which was overlooked in the previous notes.
Other than that, minor reformulations.
Write original source language when writing and reading AST (#209353)
FAIL: Clang :: Frontend/ast-main.c
FAIL: Clang :: Frontend/ast-main.cpp
were failing on z/OS; this change fixes these lit failures.
The issue here is that on z/OS the original source code language needs
to be passed through to the IR so that the backend can encode this
information in the PPA2 in the object file. That means that it needs to
be exported to the AST so that going from saved AST -> IR will carry the
language through.
[SelectionDAG][AArch64][X86] Don't scalarize vector smul.fix.sat/umul.fix.sat (#209351)
Vector SMULFIXSAT/UMULFIXSAT were not handled by expandFixedPointMul in
the vector legalizer (a FIXME) and were unrolled to per-lane scalar
code: a single <8 x i16> smul.fix.sat was ~100 instructions on both
AArch64 and x86.
Expand the saturating variants like the non-saturating ones, and build
the saturation clamp with SETCC + VSELECT for vector types so it stays
vectorized instead of being scalarized by SELECT_CC legalization. Scalar
lowering is unchanged: the clamp change is guarded on isVector(), so
scalar fixed-point codegen on every target is bit-identical.
Additionally custom-lower SMULFIXSAT on AArch64 for scale == eltbits-1,
which is exactly sqdmulh, to a single instruction.
To the FIXME note - results in a ~12x speedup over the unroll fallback.
AI was used in the making of this PR, and if its feedback is to be
[2 lines not shown]
Enforce signed package size while fetching
The HTTP fetcher replaces the signed package size with server metadata.
It validates size only after writing the cache file. An HTTP attacker
can fill that filesystem before rejection.
Keep the trusted expected size separate from response metadata. Cap the
stream at that size, including unknown-length responses.
Reject invalid repository signature types
An unrecognized signature_type is silently treated as none. A misspelled
repository policy can disable verification. An HTTP attacker can then
replace package metadata.
Accept only pubkey, fingerprints, and none. Reject invalid values before
creating a repository or modifying an existing repository.
fetch: fix SRV/mirror server failover (#296955)
- move server-list discovery before the fetch loop and seed the
walking pointer once; it was reset to the list head every iteration,
so only the first SRV record / mirror was ever tried
- give each server its own FETCH_RETRY budget before advancing to the
next; the list is walked at most once then we give up
- report SRV and mirror-list lookup failures and fall back to the
configured URL host instead of silently trying host:0
- update pkg.conf.5 FETCH_RETRY docs to per-server semantics
Store filesite as compressed archive, parse in memory for rwhich
Remove pkg_files and file_dirs tables from the repo SQLite database
(~96% of the DB size). The compressed filesite archive is now saved
as a standalone "files" file in the repo directory during pkg update.
pkg rwhich decompresses and streams the archive on demand, keeping
only the directory dictionary in memory.
While at here: expand the path in the output for more clarity
Bound repository archive handling
Repository archives are downloaded and extracted before signatures are
verified. A spoofed response could use either a large download or a
compressed member to exhaust filesystem space before rejection.
Limit downloaded archives and extracted target members to 1 GiB or half
of currently free temporary storage. Limit repository metadata to 1 MiB.
Reject duplicate members and check target member size before extraction.
