LLVM/project c5654d5clang/lib/Analysis/LifetimeSafety Checker.cpp LoanPropagation.cpp, clang/lib/Sema SemaLifetimeSafety.h

[LifetimeSafety] Introduce buildOriginFlowChain for use-after-scope (#199345)

After adding `buildOriginFlowChain`, we need to choose a diagnostic type
that is as simple as possible to verify its feasibility during `Sema`
diagnostics.

I did not choose the annotation suggestions described in
https://github.com/llvm/llvm-project/pull/188467/#issuecomment-4359071778
as the first target to implement, because it does not seem to occur
within a single CFG block. The `IssueFact` always resides in the block
preceding the `OriginEscapesFact`, which causes me to always get an
empty `OriginFlowChain`.

Since we use `buildOriginFlowChain`, we can directly trace distinct
assignment steps that occur within a single source-level expression. For
example:

```cpp
#include <vector>

    [77 lines not shown]
DeltaFile
+128-70clang/test/Sema/LifetimeSafety/safety.cpp
+60-30clang/test/Sema/LifetimeSafety/nocfg.cpp
+37-3clang/lib/Sema/SemaLifetimeSafety.h
+19-2clang/lib/Analysis/LifetimeSafety/Checker.cpp
+16-0clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
+9-3clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
+269-1083 files not shown
+275-1099 files

LLVM/project 0269658llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll regalloc-hoist-spill-live-range-upd.mir

[AMDGPU][test] Use mir test for regalloc issue

Use the newly introduced split-from flag to produce a more robust test case
for the hoistSpillInsideBB live-range update issue.

NFC

DeltaFile
+0-2,870llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll
+71-0llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
+71-2,8702 files

LLVM/project 1686669llvm/include/llvm/IR Value.h, llvm/lib/Analysis ConstantFolding.cpp ScalarEvolution.cpp

[IR] Make CanBeFreed calculation optional (NFC) (#203490)

Make the CanBeFreed argument of getPointerDereferenceableBytes() a
pointer, so that nullptr can be passed if we're not interested in
whether frees are possible or not.

Nearly all places don't actually care about frees, including BasicAA,
which is the hottest caller of this API. This improves compile-time when
deref-at-point semantics are enabled.

I've kept the argument required so that callers still have to make an
explicit choice to ignore frees. (I'd be open to making it optional
though, given that only a single caller actually cares...)
DeltaFile
+9-7llvm/lib/IR/Value.cpp
+5-5llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+5-4llvm/include/llvm/IR/Value.h
+3-3llvm/lib/Analysis/ConstantFolding.cpp
+3-3llvm/lib/Analysis/ScalarEvolution.cpp
+3-2llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+28-245 files not shown
+37-3311 files

LLVM/project bbeb2d5flang/lib/Lower OpenACC.cpp, flang/test/Lower/OpenACC acc-unstructured.f90

[OpenACC][flang] Emit NYI when unstructured loops are associated with OpenACC directives (#202948)
DeltaFile
+123-16flang/lib/Lower/OpenACC.cpp
+120-0flang/test/Lower/OpenACC/Todo/acc-unstructured-loop-construct.f90
+90-16flang/test/Lower/OpenACC/acc-unstructured.f90
+69-0flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
+402-324 files

FreeNAS/freenas 7ea565csrc/middlewared/middlewared/test/integration/utils shell.py

Moar fixes
DeltaFile
+28-46src/middlewared/middlewared/test/integration/utils/shell.py
+28-461 files

FreeNAS/freenas 1001acftests/sharing_protocols/fibre_channel test_fibre_channel.py

Parse GROUP blocks in scst.conf test parser

The FC rendering in the tests now wrap LUNs in GROUP security_group.
Teach the test parser to recurse into GROUP blocks and update
assertions to match the nested structure.
DeltaFile
+64-12tests/sharing_protocols/fibre_channel/test_fibre_channel.py
+64-121 files

LLVM/project bdc0689flang/lib/Optimizer/Dialect FIROps.cpp, flang/test/Fir mem2reg.mlir

[flang] Avoid invalid declare_value for promoted dummy-scope variables (#202498)

This fixes a verifier failure in mem2reg after inlining a CUDA device
procedure. When a promoted FIR alloca had an associated fir.declare with
a dummy_scope, mem2reg could create a fir.declare_value at a loop header
where the original dummy scope did not dominate.

Skip creating block-argument fir.declare_value ops for such
declarations, matching the existing replaced-value handling. Add a FIR
mem2reg regression test for the loop-header block argument case.
DeltaFile
+27-0flang/test/Fir/mem2reg.mlir
+5-1flang/lib/Optimizer/Dialect/FIROps.cpp
+32-12 files

LLVM/project 8d2661bllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-shuffle-combining-avx512f.ll vector-shuffle-combining-avx512bwvl.ll

[X86] combineConcatVectorOps - concat(rotate(x,a),rotate(y,b)) -> rotate(concat(x,y),concat(a,b)) (#203553)

128/256-bit rotates are widened in tablegen, we don't need to limit
these to VLX targets - any AVX512 target can perform these

We already have test coverage to ensure 128-bit XOP rotates don't get
concatenated to 256-bit
DeltaFile
+12-0llvm/lib/Target/X86/X86ISelLowering.cpp
+3-5llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
+2-3llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
+17-83 files

LLVM/project 84b9a97llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td, llvm/test/MC/AArch64 arm64-aliases.s

[AArch64] Define GCS operations as SYS and SYSL aliases

Move the remaining `GCS` instructions from dedicated opcodes to `SYSxt/SYSLxt`
aliases, keeping a tied `SYSL` pseudo for codegen where `GCS` preserves the`
input register when disabled at runtime.

Update `GCS` intrinsic selection, scheduling, disassembly aliases, and MC
coverage for the generic `SYS/SYSL` encodings.
DeltaFile
+23-49llvm/lib/Target/AArch64/AArch64InstrInfo.td
+27-0llvm/test/MC/AArch64/arm64-aliases.s
+19-4llvm/lib/Target/AArch64/AArch64InstrFormats.td
+9-3llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+1-1llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+79-575 files

LLVM/project 802ac0bllvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td, llvm/test/MC/AArch64 arm64-aliases.s

[AArch64] Define APAS, BRB and TRCIT as SYS aliases

`APAS`, `BRB IALL/INJ` and `TRCIT` use `SYS` encodings, so define them
as aliases of SYSxt instead of separate instructions.

Check that the preferred architectural aliases are printed when their
features are enabled and that disassembly falls back to the generic SYS
spelling when not enabled.
DeltaFile
+24-0llvm/test/MC/AArch64/arm64-aliases.s
+8-13llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-19llvm/lib/Target/AArch64/AArch64InstrFormats.td
+32-323 files

FreeNAS/freenas 1074555src/middlewared/middlewared/etc_files scst.conf.mako

Render security_group ACG for FC targets on non-HA systems

The non-HA branch of the FC rendering in scst.conf.mako emitted bare
TARGET blocks with the LUN at target level, ignoring any configured
initiator setting on the target. Non-HA users could not restrict FC
initiator access by WWPN - middleware accepted the configuration but
silently dropped it during rendering.
DeltaFile
+16-5src/middlewared/middlewared/etc_files/scst.conf.mako
+16-51 files

FreeBSD/ports 5d99ca1lang/erlang-runtime28 distinfo Makefile

lang/erlang-runtime28: Update corba to 5.2.2
DeltaFile
+3-3lang/erlang-runtime28/distinfo
+2-1lang/erlang-runtime28/Makefile
+5-42 files

FreeBSD/ports a6c553blang/erlang-runtime27 distinfo Makefile

lang/erlang-runtime27: Update corba to 5.2.2
DeltaFile
+3-3lang/erlang-runtime27/distinfo
+2-1lang/erlang-runtime27/Makefile
+5-42 files

LLVM/project f92034fclang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp, clang/test/CIR/Transforms/abi-lowering direct-flatten.cir

[CIR] Load flattened struct args from coerce slot

At the call site, a struct argument that flattens into scalar wire
arguments was coerced to the ABI struct as a whole value and then
decomposed with cir.extract_member.  When the coercion goes through
memory, read each field from the coerced slot with cir.get_member +
cir.load instead, so the lowering takes pointers to the members it
wants rather than loading the entire structure and extracting from the
value.  The shared memory half of the coercion is factored into
emitCoercionToMemory, which returns the destination-typed pointer to
the coerce slot; emitCoercion now builds on it and loads the whole
value, so its existing callers are unchanged.  The no-coercion call
site (the operand already has the coerced type) keeps cir.extract_member
because that value has no backing slot to take member pointers from.

The remaining changes are mechanical: llvm::append_range and
SmallVector::append for the per-field loops, spelling out cir::RecordType
instead of auto at the getFlattenedCoercedType call sites, an enumerate
loop over the coerced members, and renaming the builder parameter from

    [5 lines not shown]
DeltaFile
+97-71clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+33-12clang/test/CIR/Transforms/abi-lowering/direct-flatten.cir
+130-832 files

OPNSense/tools 7793556build common.sh sign.sh

build: change this again, first try didn't work
DeltaFile
+7-5build/common.sh
+2-2build/sign.sh
+9-72 files

LLVM/project fd8096bllvm/test/CodeGen/AMDGPU splitkit-copy-live-lanes.mir ra-inserted-scalar-instructions.mir, llvm/test/CodeGen/X86 statepoint-invoke-ra-inline-spiller.mir

[MIR] Serialize/Deserialize MachineInstr::LRSplit attribute

The LRSplit MachineInstr flag is set by SplitKit on copies inserted for
live-range splitting.
Until now the flag had no MIR-text representation.

This patch fixes that so that it gets easier to reproduce/capture issues
that involves SplitKit.

Round-trip coverage in
llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir.
DeltaFile
+168-168llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
+36-36llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
+32-32llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
+27-27llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+22-22llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
+22-22llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
+307-30732 files not shown
+439-40538 files

FreeBSD/ports 2f968f9databases/postgis33 Makefile, databases/postgis36 Makefile

databases/sfcgal: Update to 2.3.0
DeltaFile
+24-1databases/sfcgal/pkg-plist
+5-6databases/sfcgal/Makefile
+0-11databases/sfcgal/files/patch-CMakeLists.txt
+5-5databases/sfcgal/distinfo
+1-1databases/postgis36/Makefile
+1-1databases/postgis33/Makefile
+36-253 files not shown
+39-279 files

LLVM/project c3a146allvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.sched.group.barrier.ll llvm.amdgcn.iglp.opt.ll

AMDGPU/GlobalISel: RegBankLegalize rules for sched barriers intrinsics (#203425)

Add rules for sched barrier intrinsics. Note, there are regressions due
to AGPR results being copied back to VGPR un-necessarily. That will be
addressed in a future follow-up patch.
DeltaFile
+1,813-654llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
+784-230llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
+2-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
+3-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+2,602-8854 files

NetBSD/pkgsrc-wip 622817bCodeWhale Makefile

Enable building under Linux - dbus-1 required.
DeltaFile
+2-0CodeWhale/Makefile
+2-01 files

LLVM/project 664a595llvm/lib/Target/AMDGPU SIISelLowering.cpp

Rebase for new isVALU calls

Change-Id: Id2280498a63994268e902d90b787e32fdccc912a
DeltaFile
+2-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-21 files

LLVM/project 044c9b7llvm/lib/IR AutoUpgrade.cpp, llvm/test/CodeGen/AArch64 ptrauth-init-fini-autoupgrade.ll

Fix module flag name spelling in AutoUpgrade.cpp
DeltaFile
+2-2llvm/lib/IR/AutoUpgrade.cpp
+1-1llvm/test/CodeGen/AArch64/ptrauth-init-fini-autoupgrade.ll
+3-32 files

LLVM/project a1811b8llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp SIInstrInfo.cpp

Formatting

Change-Id: I0fbcad129f96986d2a448bfa4b5a027a2a5c07bd
DeltaFile
+27-16llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+6-3llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+4-4llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+2-2llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+2-1llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
+2-1llvm/lib/Target/AMDGPU/SIInstrInfo.h
+43-271 files not shown
+45-287 files

LLVM/project f4ae9c3llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp SIInstrInfo.h

[AMDGPU] NFC: Obviously show isVALU includes LDSDMA instructions

Change-Id: I3854fe397cafad4484c5af53c739e2117287d2c9
DeltaFile
+41-41llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+13-7llvm/lib/Target/AMDGPU/SIInstrInfo.h
+8-8llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-3llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPUSetWavePriority.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
+69-637 files not shown
+78-7213 files

ELF Tool Chain/elftoolchain 4378trunk/tests/libtest/bin make-test-scaffolding, trunk/tests/libtest/lib test.h

libtest: simplify the protocol for test case setup/teardown.

Remove 'enum test_case_status': a true/false value suffices
to indicate setup and teardown failure.

DeltaFile
+11-29trunk/tests/libtest/lib/test.h
+1-0trunk/tests/libtest/bin/make-test-scaffolding
+12-292 files

LLVM/project 329b484llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU packed-fp64.ll

AMDGPU/GlobalISel: RegBankLegalize rules for pk_f64 fadd, fmul and fma
DeltaFile
+238-22llvm/test/CodeGen/AMDGPU/packed-fp64.ll
+9-2llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+247-242 files

LLVM/project deb0c89llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.wmma.gfx1251.w32.ll llvm.amdgcn.wmma.imod.gfx1251.w32.ll

AMDGPU/GlobalISel: RegBankLegalize rules for gfx1251 wmma intrinsics
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+5-34 files

LLVM/project 3f51f92llvm/test/CodeGen/AMDGPU llvm.log.ll llvm.log10.ll, llvm/test/CodeGen/AMDGPU/GlobalISel sdiv.i64.ll srem.i64.ll

AMDGPU/GlobalISel: Switch some tests to -new-reg-bank-select
DeltaFile
+1,134-744llvm/test/CodeGen/AMDGPU/llvm.log.ll
+1,134-744llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+808-685llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+806-681llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+555-426llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
+554-425llvm/test/CodeGen/AMDGPU/llvm.exp.ll
+4,991-3,7057 files not shown
+6,219-4,96913 files

LLVM/project 52751a0clang/lib/Driver/ToolChains Clang.cpp, clang/test/Driver hip-toolchain-no-rdc.hip

[AMDGPU][SPIR-V] Fix treating SPIR-V input as the wrong LLVM-IR (#202986)

Summary:
This hack is intended for non-RDC AMDGCN.
DeltaFile
+15-8clang/test/Driver/hip-toolchain-no-rdc.hip
+12-10clang/lib/Driver/ToolChains/Clang.cpp
+27-182 files

OPNSense/ports 63c5609devel/cjose Makefile

devel/cjose: at second glance why does this have to be conditional
DeltaFile
+1-1devel/cjose/Makefile
+1-11 files

FreeBSD/ports c5883e6audio/audacity distinfo Makefile

audio/audacity: Update 3.7.7 => 3.7.8

Changelog:
https://github.com/audacity/audacity/releases/tag/Audacity-3.7.8

PR:             296018
Sponsored by:   UNIS Labs
MFH:            2026Q2

(cherry picked from commit 052aa8dede8ba3454d900e5a4e9471efe8a7991b)
DeltaFile
+5-5audio/audacity/distinfo
+2-3audio/audacity/Makefile
+7-82 files