[RISCV] Remove rv32p.ll. NFC (#234476)
This has been replaced by rvp-scalar.ll in #232613. Due to large number
of changes when including the RV64 RUN lines, git didn't track it as a
rename. When resolving a merge conflict before commit, I failed to keep
the deletion of rv32p.ll.
[X86] Combine mask_beforefirst to (x - 1) & ~x in GPR
EVEX and libc use this pattern in strcpy etc. to set the bits before the lowest set bit. It works correctly for x=0 too, returning an all ones mask.
Because SSE/AVX/AVX2 promote vNi1 types, do this as a DAG combine before type legalization.
We need to restrict it to power of 2 types otherwise we hit a latent crash in combineToExtendBoolVectorInReg.
[VPlan] Use llvm.mask.beforefirst for computing early exit mask
This makes the cost more accurate and improves codegen for RISC-V. The codegen for an early exit loop with side effects then goes from:
.LBB0_3: # %vector.body
# =>This Inner Loop Header: Depth=1
vl1r.v v16, (a3)
vsetvli zero, zero, e8, m1, ta, ma
vmseq.vi v16, v16, 0
vfirst.m a7, v16
srli t0, a7, 63
czero.nez a7, a7, t0
czero.eqz t0, a1, t0
or a7, t0, a7
vsetvli zero, zero, e64, m8, ta, ma
vmsltu.vx v0, v8, a7
vle8.v v17, (a5), v0.t
vcpop.m t1, v16
vsetvli zero, zero, e8, m1, ta, ma
[20 lines not shown]
[SelectionDAG] Handle splitting in get_active_lane_mask expansion
Split when the type is legal, e.g. v64i1, but the step vector needed for expansion needs split, e.g. v64i8.
This can happen on avx512 when the 512 bit registers are disabled.
[BOLT] Prevent LBR parsing from crossing entry boundaries (#234216)
#202813 assumed that LBR entries strictly follow the
`FROM/TO/EVENT/INTX/ABORT/CYCLES/TYPE/SPEC` format. But the `TYPE/SPEC`
fields might not exist in older versions. This can cause the parser to
over-read into the next LBR entry, resulting in severely corrupted CFG
flow.
Therefore, this patch isolates and splits a complete LBR entry upfront
before reading its fields sequentially, which prevents parsing
misalignment and improves overall parsing efficiency.
[Clang] Do not assume existing substition for template specialization (#227501)
Mangled symbol is not always available when having template
specialization. For example, a template alias mangled the substituted
type when actually doing substitution. In previous code, B in```
A<B>::foo()``` is always mangled because ```A<B>``` do mangle the name.
When doing substition insides ```A<T>```, B is always available. Alias
is not the case here, B is mangled when reaching A<T> inside.
As now, TemplateName::SubstTemplateTemplateParm might needs to be
resolved further as B is not always defined, we remove it from the
switch case and find recursively like the origianl path.
Assisted-by: Claude # Tests, ReleaseNotes
[SelectionDAG] Fix get_active_lane_mask expansion on 32-bit targets
On e.g. wasm32, OpVT can be 32 bits whilst the StepVector type can be v2i64. When this happens DAG.getConstant asserts because maxUIntN doesn't fit into the 32 bits. Fix this by clamping it to OpVT's max size.
Attributor: Add only new attributes when manifesting
manifestAttrs collected the attributes to add in an AttrBuilder, then
copied the position's attribute set into another AttrBuilder to merge
them in. Collect them in an array and merge them into the set in one
pass. This requires the attributes passed to manifestAttrs to be sorted
like an attribute set, which all callers already do. The only one
passing more than one attribute is AMDGPUAttributor, whose implicit
argument attributes are sorted.
Instructions spent in amdgpu-attributor:
rocPRIM test_device_scan, gfx942: 770.2M -> 710.8M (-7.7%)
Blender Cycles HIP kernel, gfx1100: 380.0M -> 379.5M (-0.1%)
rocPRIM 16 tests, full LTO, closed world: 3019.8M -> 2855.9M (-5.4%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
IR: Add attributes from an array to an attribute set
Add AttributeSet::addAttributes and AttributeList::addAttributesAtIndex
overloads taking an array of attributes sorted like an attribute set,
with distinct kinds. They merge the attributes into the set in one pass,
without first copying the set into an AttrBuilder and adding each
attribute to it.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AtomicExpand][NVPTX] Add single-lane atomic RMW coverage
Record current expansion and code generation before changing single-lane RMW legalization. Check the full pipeline separately from direct instruction selection while their output differs.
[AtomicExpand][NVPTX] Add single-lane atomic RMW coverage
Record current expansion and code generation before changing single-lane RMW legalization. Check the full pipeline separately from direct instruction selection while their output differs.
[clang][Driver] Fix libc++ include path on OpenBSD (#212979)
`clang++` defaults to `-stdlib=libc++` on OpenBSD. When building with both
`clang` and `libcxx` included, the freshly built `clang++` uses the system
version of the `libc++` headers. However, this is from the bundled `libc++`
22.1.8, thus inconsistent with the `libc++` being built.
OpenBSD has its own version of addLibCxxIncludePaths which just includes
`/usr/include/c++/v1`.
This patch removes OpenBSD::addLibCxxIncludePaths in favour of the generic
version in `Gnu.cpp`.
[X86] Combine mask_beforefirst to (x - 1) & ~x in GPR
EVEX and libc use this pattern in strcpy etc. to set the bits before the lowest set bit. It works correctly for x=0 too, returning an all ones mask.
Because SSE/AVX/AVX2 promote vNi1 types, do this as a DAG combine before type legalization.
We need to restrict it to power of 2 types otherwise we hit a latent crash in combineToExtendBoolVectorInReg.
[VPlan] Use llvm.mask.beforefirst for computing early exit mask
This makes the cost more accurate and improves codegen for RISC-V. The codegen for an early exit loop with side effects then goes from:
.LBB0_3: # %vector.body
# =>This Inner Loop Header: Depth=1
vl1r.v v16, (a3)
vsetvli zero, zero, e8, m1, ta, ma
vmseq.vi v16, v16, 0
vfirst.m a7, v16
srli t0, a7, 63
czero.nez a7, a7, t0
czero.eqz t0, a1, t0
or a7, t0, a7
vsetvli zero, zero, e64, m8, ta, ma
vmsltu.vx v0, v8, a7
vle8.v v17, (a5), v0.t
vcpop.m t1, v16
vsetvli zero, zero, e8, m1, ta, ma
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