DAG: Canonicalize undef shuffle operands and results to poison
getVectorShuffle canonicalizes fully-undefined results and unused operands.
Make sure these use poison to avoid degrading poison to undef, defending against
future regressions.
Co-Authored-By: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[libc][test][NFC] Fix pthread_setschedparam_test flakiness (#212067)
Synchronised child thread execution in pthread_setschedparam_test using
a mutex lock. This prevents race conditions where the child thread
exited before scheduling parameter assertions ran on multi-core
platforms such as aarch64.
Added missing pthread target dependencies to CMakeLists.txt.
Assisted-by: Automated tooling, human reviewed.
[AMDGPU][GISel] Remove redundant AND on scalar shift amounts
A scalar shift only consumes the low log2(bitwidth) bits of its amount,
so an explicit (and amt, mask) feeding the amount is redundant whenever
mask has all of those low bits set. SelectionDAG already achieves this
via SimplifyDemandedBits on the shift-amount operand; this adds the
equivalent to the post-RegBankSelect combiner for G_SHL/G_LSHR/G_ASHR.
Co-authored-by: Cursor <cursoragent at cursor.com>
[LoopInfo] Identify loops with a single-pass DFS algorithm. NFC (#212000)
analyze() numbers the dominator tree, scans it in reverse preorder for
header candidates, floods backward through the CFG from each header's
latches, then walks the CFG again to order the blocks.
Do all of it in one forward DFS, with the algorithm of Wei et al.,
"A New Algorithm for Identifying Loops in Decompilation", which
GenericCycleInfo already implements.
On an irreducible CFG that algorithm may return an irreducible superset
of the natural loop subset `discoverAndMapSubloop` would return.
(Depending on the successor visiting order, the algorithm may report a
reducible loop nested in an irreducible loop, where the reducible one
exactly matches `discoverAndMapSubloop`.)
To satisfy verifyLoop and LoopSimplify, reduce each such ireducible loop
to the natural loop of its header's backedges instead: the latches the
header dominates, and the blocks reaching them without passing the
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[clang][bytecode] Don't check global variable init size (#212092)
The current interpreter doesn't do this either. If we do, the clang
build fails because AMDGPUGenGlobalISel.inc: contains a global constexpr
array called MatchTable0 with 1'926'005 elements.
ocaml-dune: downgrade to 3.23.1
Update to 3.24 removed the Coq Build Language, recommending
Rocq instead. Since we don't have that yet...
Requested by alnsn.
[clang][bytecode] Only override constant-context state if we have an EvalEmitter (#211475)
This does not make sense when emitting bytecode, as the bytecode would
just contain a `PushCC`/`PopCC` pair with nothing in between.
[AArch64] Add CAS instructions to NeoverseN2 schedule model (#211195)
CAS instructions (B, H, W, X variants) are not described in the ARM
Neoverse N2 Software Optimization Guide. There used to be no schedule
model for them, so `llvm-mca` was unable to analyze code containing
these instructions:
llvm-mca -mtriple=aarch64 -mcpu=cortex-a78 -mattr=+lse casb.s
error: found an unsupported instruction in the input assembly
sequence, use -skip-unsupported-instructions=lack-sched to ignore
these on the input.
note: instruction: casb w0, w1, [sp]
The patch adds a basic schedule model of 14 cycles (as measured on
Cortex-A78 with llvm-exegesis) and L/S utilized pipelines (this is a
guess, the reality is likely more complicated).
