18092 init_gdt: use gdt0_default_r
Reviewed by: Bill Sommerfeld <sommerfeld at hamachi.org>
Reviewed by: Dan Cross <cross at oxidecomputer.com>
Approved by: Robert Mustacchi <rm at fingolfin.org>
NAS-140911 / 27.0.0-BETA.1 / fix the build (remove isodate) (#18902)
`isodate` was never a declared
dependency of middleware — it was being pulled in transitively (via
`zettarepl`), and our code happened to work by pure chance. The
zettarepl change that drops it
(https://github.com/truenas/zettarepl/pull/357)
has already merged, so `import isodate` now fails at import time and
any module that touches it can't load. This PR removes our two
remaining usages and unbreaks the build.
### Changes
- **`src/middlewared/middlewared/sqlalchemy.py`** — the `Time` UDT used
`isodate.parse_time` on bind/result. Replaced with
`datetime.time.fromisoformat`. Both sides of the column already round-
trip through `time.isoformat()`, so the format read back is always
standard extended ISO 8601 — exactly what `fromisoformat` accepts on
Python 3.11+. The two `# type: ignore[no-any-return]` comments were
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[VPlan] Check for VInstruction in findCanonicalIVIncrement. (#195845)
There are cases where findCanonicalIVIncrement may discover a
non-VPInstruction add that matches the expected shape, but we expect a
VPInstruction. Add explicit check to fix crash.
[flang][cuda][openacc] Add UseDevice attribute to model host_data use_device symbols (#195182)
Symbols appearing in `!$acc host_data use_device(...)` were previously
marked with `CUDADataAttr::Device`, which caused generic resolution to
fail.
Introduce a new CUDADataAttr::UseDevice enumerator and use it in
`CopySymbolWithDevice` / `CloneDerivedTypeForUseDeviceImpl` instead of
Device. The new attribute is:
1. Compatible with any dummy in AreCompatibleCUDADataAttrs.
2. Ranked in the matching distance table (GetMatchingDistance): prefers
Device dummies (0), accepts Managed/Unified (2), and allows host dummies
(3).
3. Not user-spellable — only set internally during OpenACC name
resolution, never parsed from source or written to module files.
4. Treated like Device for non-host-array checks, I/O restrictions, and
MLIR lowering (mapped to `cuf::DataAttribute::Device`).
[clang-sycl-linker] Add per-kernel device code splitting (#195362)
Introduce a --sycl-module-split-mode option for clang-sycl-linker that
selects how the fully linked device module is split into device images:
- none (default): one device image containing all kernels
- kernel: one device image per kernel function, built by taking the
transitive closure of each kernel's dependencies
The split is implemented by delegating to
llvm::splitModuleTransitiveFromEntryPoints, providing a categorizer that
assigns each kernel definition a unique integer id.
Symbol collection now happens during splitting while the Module is still
in memory, avoiding a round-trip through disk to re-read the bitcode for
symbol extraction.
As part of this change, the splitModuleTransitiveFromEntryPoints API is
updated to accept an Error-returning callback and propagate errors from
it, replacing the previous void callback signature. The existing caller
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[NFC][VPlan] Split `makeMemOpWideningDecisions` into subpasses
The idea is to have handling of strided memory operations (either from
https://github.com/llvm/llvm-project/pull/147297 or for VPlan-based
multiversioning for unit-strided accesses) done after some mandatory
processing has been performed (e.g., some types **must** be scalarized)
but before legacy CM's decision to widen (gather/scatter) or scalarize
has been committed.
And in longer term, we can uplift all other memory widening decision to
be done here directly at VPlan level. I expect this structure would also
be beneficial for that.
[MLIR][Transform] Don't error when a structurally inlinable call exists (#195770)
Fixes bug introduced in https://github.com/llvm/llvm-project/pull/192956
Specifically transform-interpreter would crash if any op in the region
it is applied to is marked as no-inline via the inliner interface. This
is because the check added does a post processing to verify that all
operations can be inlined [and there isn't an issue due to symbol
merging]. However, it fails to account for the case where an operation
was already not inlinable (and not an error introduced by the transform
symbol merging).
[LAA] Enable diff checks for non-unit constant stride
This can be extended to non-constant loop-invariant strides but that is
left to a separate change.
[SandboxVec] SandboxVectorizerIR Boilerplate (#189515)
This patch introduces a new specialization of SandboxIR named
SandboxVectorizerIR that contains the new Pack instruction (though it is
just a placeholder for now). It also implements the necessary
boilerplate in SandboxIR to support adding such specializations.
Each specialization requires its own *Values.def file defining its new
instructions. The new .def file also needs to be added to
ValuesDefFilesList.def which allows SandboxIR to include entries from
all specializations and populate structures like the Opcode enum,
ClassID and others.
Given that we need to include both .def files in several places, I had
to (i) change the .def file to undefine its locally defined macros so
that they won't get redefined in the next #include .def, and (ii) add
the DEF_DISABLE_AUTO_UNDEF option to disable undefining the macros at
the end because otherwise the user-specified DEF_ macros would be
undefined by the time we reach the second .def file.
[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs
These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.
Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
[AMDGPU] Implement CFI for CSR spills
Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.
Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.
Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[NFC][SPIR-V] Rename vID register class to viID (#195711)
Rename the v2i64 register and its class from vID/vID0 to viID/viID0 so
it follows the same `v<element-kind>ID` convention as vfID (v2f64) and
vpID (v2p64) for better consistency
