FreeBSD/ports b496a8cwww/opengist Makefile distinfo

www/opengist: Update to 1.15.1

Changes since 1.14.0:

v1.15.1

Fixed

  * Admin pagination with new URLs (#782).
  * Stop unbounded diff content growth for large files (#787).

v1.15.0

Added

  * UI rework (#757).
  * Gist settings page, with metadata edition and danger zone (#757).
  * Explore users page, with search and sorting (#757).
  * Explore topics page (#757).

    [19 lines not shown]
DeltaFile
+7-7www/opengist/distinfo
+1-1www/opengist/Makefile
+8-82 files

LLVM/project 6c206e3llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU sched-dynamic-vgpr-blocks.mir

[AMDGPU] Fix refactoring mishap (#216974)

We ended up calling getAllocatedNumVGPRBlocks with the arguments in the
wrong order - it should take the number of VGPRs first, and then the
size of a dynamic VGPR block.

Assisted-by: Claude
DeltaFile
+72-0llvm/test/CodeGen/AMDGPU/sched-dynamic-vgpr-blocks.mir
+3-3llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+75-32 files

LLVM/project fd0d6dallvm/lib/Frontend/OpenMP OMPIRBuilder.cpp, mlir/test/Target/LLVMIR omptarget-debug-declare-mapper.mlir

[OMPIRBuilder] Don't use invalid debug loc in declare mapper function. (#148263)

This is similar to https://github.com/llvm/llvm-project/pull/147950 but
for declare mapper function.
DeltaFile
+50-0mlir/test/Target/LLVMIR/omptarget-debug-declare-mapper.mlir
+2-2llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+52-22 files

LLVM/project 437a849llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]
DeltaFile
+24-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+2-3llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+37-143 files

LLVM/project 72cc539llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

Precommit test
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163-01 files

LLVM/project e78974fllvm/test/Transforms/LoopVectorize blend-i1.ll

Precommit test
DeltaFile
+58-0llvm/test/Transforms/LoopVectorize/blend-i1.ll
+58-01 files

LLVM/project e2fa7d5llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Make simplifyRecipe more like InstCombine

Most combines in simplifyRecipe RAUW a value, but not all of them erase the old recipe.
Unify them and bring it in line with InstCombine by having it return a VPValue, which simplifyRecipes can then call RAUW with, and automatically erase the old recipe.

Similarly to InstCombine, combines that modify a recipe should return the same recipe.
DeltaFile
+1-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-01 files

LLVM/project 012970dllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize blend-i1.ll dont-fold-tail-for-divisible-TC.ll

[VPlan] Process simplifyRecipes in a worklist

This brings simplifyRecipes further in line with InstCombine, and asides from unlocking more simplifications it also helps avoid spurious test churn whenever passes are moved around simplifyRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification order as before.

I've gone through and checked every simplification we do is a canonicalisation that converges, and I checked on llvm-test-suite + SPEC CPU 2017 in various configurations that we don't hit any cycles.
DeltaFile
+23-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-8llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+2-3llvm/test/Transforms/LoopVectorize/blend-i1.ll
+29-253 files

LLVM/project 71b39c0llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/VPlan constant-fold.ll

[VPlan] Make simplifyRecipe more like InstCombine

Most combines in simplifyRecipe RAUW a value, but not all of them erase the old recipe.
Unify them and bring it in line with InstCombine by having it return a VPValue, which simplifyRecipes can then call RAUW with, and automatically erase the old recipe.

Similarly to InstCombine, combines that modify a recipe should return the same recipe.
DeltaFile
+116-153llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-11llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
+116-1642 files

LLVM/project 3b39559llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Update trunc combine, fix m_Not return position
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-41 files

LLVM/project de2b9f8clang/docs ReleaseNotes.md, clang/lib/Sema SemaRISCV.cpp

[Clang][RISCV] Allow three SiFive CLIC interrupt arguments (#216159)

The SiFive CLIC interrupt values may be combined with each other and
with the machine value, but the interrupt attribute previously accepted
at most two arguments.

This commit allows three arguments for the combination of machine,
SiFive-CLIC-preemptible, and SiFive-CLIC-stack-swap.

Fixes #216138
DeltaFile
+14-1clang/test/Sema/riscv-interrupt-attr-sifive.c
+12-0clang/test/Sema/riscv-interrupt-attr-qci.c
+4-4clang/lib/Sema/SemaRISCV.cpp
+5-1clang/test/Sema/riscv-interrupt-attr.c
+6-0clang/test/Sema/riscv-interrupt-attr-rnmi.c
+3-0clang/docs/ReleaseNotes.md
+44-66 files

LLVM/project 7271360llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 psadbw.ll shrink_vmul.ll

[X86] isTargetShuffleEquivalent - only use "known zero" element if its known never poison/undef as well (#217030)

We're starting to hit cases where we've used AND/ANDNP masking to zero
out vector elements, but SimplifyDemandedElts assumes the element is
unused, folds to poison and then later folds AND(poison,0) -> poison.

This needs a more thorough cleanup of a number of x86 folds that do this
(similar to #215538), but that would result in a great deal of churn,
and it looks like a #214388 fix requires backporting to 23.x.

So initially I'm taking the approach that @xyyy1420 found so we can get
this backported and I can then address the issue more thoroughly in
trunk. I'm not convinced that this will address all poison cases, but
I'm reluctant to attempt a larger backport patch.

Fixes #214388
DeltaFile
+1,014-1,012llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+122-0llvm/test/CodeGen/X86/pr214388.ll
+41-39llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
+4-12llvm/test/CodeGen/X86/psadbw.ll
+13-3llvm/test/CodeGen/X86/shrink_vmul.ll
+6-2llvm/lib/Target/X86/X86ISelLowering.cpp
+1,200-1,0682 files not shown
+1,205-1,0688 files

LLVM/project 3c6befelibc/src/__support/math atan2f128.h, libc/src/math/generic atan2l.cpp

[libc] Modify `atan2f128` to use emulated Float128 type  (#216508)
DeltaFile
+37-13libc/test/src/math/smoke/atan2f128_test.cpp
+10-13libc/src/__support/math/atan2f128.h
+10-7libc/test/src/math/atan2f128_test.cpp
+14-0utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
+2-7libc/src/math/generic/atan2l.cpp
+8-0utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
+81-4022 files not shown
+116-6028 files

NetBSD/pkgsrc Wn2DvY6textproc/tabiew Makefile cargo-depends.mk

   tabiew: update to 0.14.2.

   About a month of development.
VersionDeltaFile
1.9+454-481textproc/tabiew/distinfo
1.9+150-159textproc/tabiew/cargo-depends.mk
1.9+2-2textproc/tabiew/Makefile
+606-6423 files

LLVM/project 83d061allvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]
DeltaFile
+24-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+2-3llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+37-143 files

LLVM/project a9a62a6llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

Precommit test
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163-01 files

LLVM/project 9cf47b1llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize blend-i1.ll dont-fold-tail-for-divisible-TC.ll

[VPlan] Process simplifyRecipes in a worklist

This brings simplifyRecipes further in line with InstCombine, and asides from unlocking more simplifications it also helps avoid spurious test churn whenever passes are moved around simplifyRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification order as before.

I've gone through and checked every simplification we do is a canonicalisation that converges, and I checked on llvm-test-suite + SPEC CPU 2017 in various configurations that we don't hit any cycles.
DeltaFile
+23-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-8llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+2-3llvm/test/Transforms/LoopVectorize/blend-i1.ll
+29-253 files

LLVM/project 84ace96llvm/test/Transforms/LoopVectorize blend-i1.ll

Precommit test
DeltaFile
+58-0llvm/test/Transforms/LoopVectorize/blend-i1.ll
+58-01 files

LLVM/project 21db570llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/VPlan constant-fold.ll

[VPlan] Make simplifyRecipe more like InstCombine

Most combines in simplifyRecipe RAUW a value, but not all of them erase the old recipe.
Unify them and bring it in line with InstCombine by having it return a VPValue, which simplifyRecipes can then call RAUW with, and automatically erase the old recipe.

Similarly to InstCombine, combines that modify a recipe should return the same recipe.
DeltaFile
+116-153llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-11llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
+116-1642 files

LLVM/project 4ad24a0llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Update trunc combine, fix m_Not return position
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-41 files

FreeBSD/ports dc20e3cwww/opengist distinfo Makefile, www/opengist/files patch-package.json opengist.in

www/opengist: Update to v1.14.0

- Remove assets dir, they are already bundled in the binary
- Fix the broken rc service that would not shut down correctly
- Move the pidfiles to /var/run/ to avoid needing to create a dir
- Use the prebuilt frontend assets published upstream, dropping the
  npm build dependency
- Enable aarch64

Reviewed by:    fox
Differential Revision:  https://reviews.freebsd.org/D58255
DeltaFile
+0-79www/opengist/pkg-plist
+15-40www/opengist/Makefile
+28-14www/opengist/files/opengist.in
+7-7www/opengist/distinfo
+0-13www/opengist/files/patch-package.json
+50-1535 files

LLVM/project d92ae18llvm/test/Transforms/LoopVectorize/X86 funclet.ll

[LV] Make operand bundle test not constant-foldable/dead. NFC (#217253)

The test looks like it was originally added to check that operand
bundles were preserved, but the libcall is constant folded away and made
dead. Later PRs may end up removing this, see the conversation in
https://github.com/llvm/llvm-project/pull/212968#discussion_r3702373769
DeltaFile
+17-12llvm/test/Transforms/LoopVectorize/X86/funclet.ll
+17-121 files

OPNSense/core 5b9dff6src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms dialogSNatRule.xml dialogOneToOneRule.xml, src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes JsonAuditField.php

Add userdata container and note inside the JsonAuditField, so users can keep a small changelog if they want
DeltaFile
+24-2src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes/JsonAuditField.php
+13-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogSNatRule.xml
+13-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogOneToOneRule.xml
+13-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogNptRule.xml
+13-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogFilterRule.xml
+13-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogDNatRule.xml
+89-21 files not shown
+100-37 files

NetBSD/src 07R4orLsys/arch/arm/ti files.ti am18xx_sdmmc.c, sys/arch/evbarm/conf GENERIC_V5

   evbarm/am18xx: sdmmc driver

   A first version of the SD card driver for the TI am1808. The driver works fine, but the performance is lower than expected.
VersionDeltaFile
1.1+866-0sys/arch/arm/ti/am18xx_sdmmc.c
1.34+5-1sys/arch/arm/ti/files.ti
1.12+2-1sys/arch/evbarm/conf/GENERIC_V5
+873-23 files

NetBSD/pkgsrc-wip 02751e7litestream TODO Makefile, litestream/patches patch-go.mod patch-go.sum

litestream: Update to 0.5.16

pkgsrc changes:
- Bump modernc.org/sqlite to version that brings back NetBSD/amd64
  support

Changes:
Too long to include, sorry, please see:
<https://github.com/benbjohnson/litestream/releases>
DeltaFile
+722-432litestream/distinfo
+239-143litestream/go-modules.mk
+44-0litestream/patches/patch-go.sum
+24-0litestream/patches/patch-go.mod
+1-1litestream/Makefile
+1-0litestream/TODO
+1,031-5766 files

NetBSD/src cDwmij3sys/arch/arm/ti ti_edma.c

   evbarm/ti_edma: clear events before transfer

   The sdmmc controller on the am18xx fires dma events even in PIO mode. Clear these event before starting a DMA transfer.
VersionDeltaFile
1.9+5-2sys/arch/arm/ti/ti_edma.c
+5-21 files

LLVM/project 3c328a3llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Only try (A+B)/C distribution for nuw adds (NFC) (#212508)

Checking for NUW is cheaper to check and should be equivalent to
checking extended expression: https://alive2.llvm.org/ce/z/_VxSSD

Compile-time impact:
 * stage1-O3: -0.09%
 * stage1-ReleaseThinLTO: -0.07%
 * stage1-ReleaseLTO-g: -0.10%
 * stage1-aarch64-O3: -0.10%
 * stage2-O3: -0.09%
 * stage2-clang: -0.23%
 


https://llvm-compile-time-tracker.com/compare.php?from=e432cb12962f1619bc73c50a2dc4d2ad5ac6b44c&to=6e11321bd7308202d7973656dee8dc03ac6a4686&stat=instructions:u

PR: https://github.com/llvm/llvm-project/pull/212508
DeltaFile
+4-6llvm/lib/Analysis/ScalarEvolution.cpp
+4-61 files

NetBSD/pkgsrc gezAx1wmk/misc common.mk

   mk: Introduce support for ULIMIT_PRECMD.

   While this has potential to run any pre-command, it is primarily useful as a
   hook to insert ulimit(1) commands that will apply to shell commands, hence
   the name.

   In bulk builds there will occasionally be packages that end up spinning on
   CPU and hanging the build until the user has a chance to kill the process.

   For some builds this is desirable so that the issue can be debugged, but for
   others the user may prefer to avoid having to interact with the build to get
   it to complete, in which case they can set this to e.g. "ulimit -S -t 3600".
VersionDeltaFile
1.4+8-2mk/misc/common.mk
+8-21 files

LLVM/project a1fffdaclang/include/clang/AST TemplateBase.h, clang/lib/AST TemplateBase.cpp

[Clang][NFC] Remove unused constructor of ASTTemplateArgumentListInfo (#217200)

It turns out that its only client VarTemplateSpecializationDecl has
stopped copying template arguments since 2024, see
12028373020739b388eb2b8141742509f1764e3c
DeltaFile
+0-22clang/lib/AST/TemplateBase.cpp
+0-7clang/include/clang/AST/TemplateBase.h
+0-292 files

FreeBSD/ports 9ea903bsysutils/graylog Makefile distinfo

sysutils/graylog: Update 7.1.7 => 7.1.8

Changelog:
https://go2docs.graylog.org/current/changelogs/changelog.html#Graylog718

Sponsored by:   UNIS Labs
MFH:            2026Q3

(cherry picked from commit a4ab70e83084414793542c2d40e74ffe1d19f1b5)
DeltaFile
+3-3sysutils/graylog/distinfo
+1-1sysutils/graylog/Makefile
+4-42 files