[AMDGPU][GISel] Match constrained shifts across register bank copies
The constrained shift PatFrags (csh_mask_* wrapped by cshl_/csrl_/csra_)
supply GISelPredicateCode and are imported into the GlobalISel match
table, but they never fired for a divergent shift. AMDGPURegBankLegalize
places a cross-bank COPY in two positions inside the shape they match:
- the mask constant stays in the SGPR bank, so a divergent G_AND reads
it through a COPY and the frag's imm operand is not a G_CONSTANT;
- a uniform G_AND feeding a divergent shift is copied to the VGPR bank,
so the shift's amount operand is not a G_AND.
Either way GIM_CheckOpcode rejects the rule before isUnneededShiftMask
is ever consulted, and the redundant v_and_b32 survives into the output.
Set GIIgnoreCopies so the matcher emits GIM_RecordInsnIgnoreCopies for
those operands. A frag's flags only govern how its own operands are
found, so the first position needs the flag on csh_mask_* while the
second needs it on the node holding the shift; split the masked
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workflows: Merge release-doxygen into release-documenation
These two workflows use the same script and have the same structure,
so it's easier just to have one job that builds both.
