LLVM/project 318a1ealibcxx/test/std/algorithms/alg.sorting/alg.sort/sort ranges.sort.pass.cpp

[libc++][test] Unblock cases for `ranges::sort` with proxy ranges (#188490)

libc++ switched to use `iter_move`/`iter_swap` long time ago, so we
should unblock these cases.
DeltaFile
+0-3libcxx/test/std/algorithms/alg.sorting/alg.sort/sort/ranges.sort.pass.cpp
+0-31 files

LLVM/project 4a41e9cllvm/lib/Target/AMDGPU SIFrameLowering.cpp, llvm/test/CodeGen/AMDGPU callee-frame-setup.ll

AMDGPU: Don't save FP/BP for noreturn functions (#187668)

As suggested here:
https://github.com/llvm/llvm-project/pull/184616#discussion_r2889401998

We could probably skip saving other regs too, but that can be a future
patch.

Assisted-by: Sline with Claude Opus.
DeltaFile
+49-0llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+8-5llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+57-52 files

LLVM/project 24ec6d4llvm/lib/Target/SPIRV SPIRVBuiltins.cpp, llvm/test/CodeGen/SPIRV/transcoding OpImageSampleExplicitLod.ll OpImageReadMS.ll

[SPIR-V] Fix image query and sampler type (#190767)

- Use OpImageQuerySize instead of OpImageQuerySizeLod for multisampled
SPIR-V spec requires MS=0 for OpImageQuerySizeLod
- Use `target("spirv.Sampler")` instead of i32 for non-constant sampler
kernel parameters so they produce OpTypeSampler as required by
OpSampledImage

related to https://github.com/llvm/llvm-project/issues/190736
DeltaFile
+4-4llvm/test/CodeGen/SPIRV/transcoding/OpImageSampleExplicitLod.ll
+4-2llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+1-1llvm/test/CodeGen/SPIRV/transcoding/OpImageReadMS.ll
+9-73 files

NetBSD/src gHqDysusys/arch/atari/atari genassym.cf, sys/arch/hp300/hp300 genassym.cf

   Re-factor genassym.cf into common m68k definitions and platform-specific
   ones.
VersionDeltaFile
1.1+233-0sys/arch/m68k/m68k/genassym.cf
1.45+1-175sys/arch/x68k/x68k/genassym.cf
1.54+2-170sys/arch/mvme68k/mvme68k/genassym.cf
1.43+1-165sys/arch/atari/atari/genassym.cf
1.34+1-161sys/arch/luna68k/luna68k/genassym.cf
1.58+1-160sys/arch/hp300/hp300/genassym.cf
+239-83122 files not shown
+292-2,00828 files

LLVM/project 90ecec0clang/lib/Sema SemaARM.cpp

[clang][NFC] Simplify boolean return in `SemaARM::checkTargetClonesAttr` (#192832)
DeltaFile
+1-3clang/lib/Sema/SemaARM.cpp
+1-31 files

LLVM/project 050da78llvm/test/CodeGen/RISCV/rvv vfsub-vp.ll fixed-vectors-vfsub-vp.ll

[RISCV] Remove codegen for vp_fsub (#191832)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off the vp_fsub intrinsic from #179622.
DeltaFile
+378-564llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
+135-143llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
+45-45llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
+36-36llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
+8-12llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+9-6llvm/test/CodeGen/RISCV/rvv/fold-vp-fsub-and-vp-fmul.ll
+611-8063 files not shown
+616-8119 files

LLVM/project c3f8eccllvm/lib/Target/AMDGPU SIRegisterInfo.cpp

Refactor loop
DeltaFile
+16-23llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+16-231 files

LLVM/project d3141b4llvm/lib/Transforms/Scalar LoopFuse.cpp, llvm/test/Transforms/LoopFusion indirect-br.ll

[LoopFusion] Validate loop structure before creating LoopCandidates (#192280)

This patch deletes the assert which required the loop to have 
preheader. It is not guaranteed to have preheader when loops
are structured using `indirectbr`. Instead, we now rely on header.

Fixes #156670.
DeltaFile
+59-0llvm/test/Transforms/LoopFusion/indirect-br.ll
+6-3llvm/lib/Transforms/Scalar/LoopFuse.cpp
+65-32 files

LLVM/project 69c566blldb/source/Plugins/SymbolLocator/SymStore SymbolLocatorSymStore.cpp SymbolLocatorSymStoreProperties.td, lldb/test/API/symstore TestSymStore.py

[lldb] Add caching and _NT_SYMBOL_PATH parsing in SymbolLocatorSymStore (#191782)

The _NT_SYMBOL_PATH environment variable is the idiomatic way to set a
system-wide lookup order of symbol servers and a local cache for
SymStore. It holds a semicolon-separated list of entries in the
following notations:
* srv*[<cache>*]<source> sets a source and an optional explicit cache
* cache*<cache> sets an implicit cache for all subsequent entries
* all other entries are bare local directories

Since symbol paths are closely intertwined with the caching of symbol
files, this patch proposes support in LLDB for both features at once.
ParseEnvSymbolPaths() implements the parsing logic, which processes
entries of the symbol path string from left to right to create a series
of LookupEntry objects that each store a source and a cache location.
The source of a LookupEntry can be a local directory or an HTTP server
address. The cache is a local directory or empty. This representation
unifies the implicit vs. explicit caching options from the SymStore
protocol.

    [22 lines not shown]
DeltaFile
+256-18lldb/source/Plugins/SymbolLocator/SymStore/SymbolLocatorSymStore.cpp
+158-3lldb/test/API/symstore/TestSymStore.py
+113-0lldb/unittests/Symbol/SymStoreTest.cpp
+6-2lldb/source/Plugins/SymbolLocator/SymStore/SymbolLocatorSymStoreProperties.td
+8-0lldb/source/Plugins/SymbolLocator/SymStore/SymbolLocatorSymStore.h
+2-0lldb/unittests/Symbol/CMakeLists.txt
+543-236 files

NetBSD/pkgsrc FlwNZRumath/py-pandas distinfo, math/py-pandas/patches patch-pandas___libs_meson.build patch-pandas___libs_tslibs_meson.build

   py-pandas: fix build with meson 1.11
VersionDeltaFile
1.1+15-0math/py-pandas/patches/patch-pandas___libs_meson.build
1.1+15-0math/py-pandas/patches/patch-pandas___libs_tslibs_meson.build
1.47+3-1math/py-pandas/distinfo
+33-13 files

LLVM/project 3323903llvm/test/CodeGen/AArch64/GlobalISel knownbits-vector.mir, llvm/unittests/CodeGen/GlobalISel KnownBitsVectorTest.cpp

[AArch64][GlobalISel] Move KnownBitsVectorTest to mir. NFC (#192536)

This ports some of the older C++ GlobalISel known-bits tests to use
print<gisel-value-tracking> in a mir file. This is mostly autogenerated,
but attempts to keep the existing comments. Some tests have not been
ported as they are entirely in C++ or tested isKnownToBeAPowerOfTwo,
which is not tested in the print output.
DeltaFile
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+1,291-1,3702 files

LLVM/project 7a64225clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-misc.c neon-intrinsics.c

[CIR] add vsqrt and vsqrtq support (#192282)

Part of https://github.com/llvm/llvm-project/issues/185382

co-authored by: @Kouunnn <xerw1314 at gmail.com>

---------

Co-authored-by: Zile Xiong <xiongzile99 at gmail.com>
Co-authored-by: ZCkouun <1765074320 at qq.com>
DeltaFile
+62-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-39clang/test/CodeGen/AArch64/neon-misc.c
+1-13clang/test/CodeGen/AArch64/neon-intrinsics.c
+6-0clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+69-524 files

NetBSD/pkgsrc-wip 3b52540rust195 distinfo, rust195/patches patch-src_tools_cargo_src_bin_cargo_commands_help.rs

rust195: carry over 'cargo help build' patch from 1.94
DeltaFile
+20-0rust195/patches/patch-src_tools_cargo_src_bin_cargo_commands_help.rs
+1-0rust195/distinfo
+21-02 files

LLVM/project 57e35e9llvm/test/Transforms/LoopVectorize/X86 replicating-load-store-costs.ll

[LV][NFC] Regen CHECK lines in LoopVectorize/X86/replicating-load-store-costs.ll (#192682)
DeltaFile
+525-525llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
+525-5251 files

LLVM/project b37a607compiler-rt/lib/builtins CMakeLists.txt, compiler-rt/lib/builtins/aarch64 sme-abi.S

[compiler-rt] Don't provide `__arm_sme_state` for baremetal targets (#191434)

Previously, we required baremetal runtimes to implement an undocumented
`__aarch64_sme_accessible` hook to check if SME is available (as
checking CPU features may vary across targets).

This allowed us to provide a generic `__arm_sme_state` implementation
but caused some friction for toolchains that depend on compiler-rt.

This patch instead removes the implementation of `__arm_sme_state` for
baremetal. This makes it the responsibility of the runtime (e.g. libc)
to provide this function for baremetal targets.

The requirements of this function are documented in the AAPCS64:
https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#811__arm_sme_state

All other SME ABI rountines are still provided by compiler-rt.
DeltaFile
+21-16compiler-rt/lib/builtins/cpu_model/aarch64/fmv/baremetal.inc
+0-9llvm/test/CodeGen/AArch64/aarch64-sme-stubs.ll
+3-3compiler-rt/lib/builtins/cpu_model/aarch64.c
+0-5mlir/lib/ExecutionEngine/ArmSMEStubs.cpp
+4-1compiler-rt/lib/builtins/aarch64/sme-abi.S
+1-1compiler-rt/lib/builtins/CMakeLists.txt
+29-356 files

LLVM/project 6fd5b52mlir/lib/Dialect/Transform/IR Utils.cpp, mlir/test/Dialect/Transform normal-forms.mlir

[mlir] reduce excessive verification in transform (#192653)

`mergeSymbolsInto` called by the transform interpreter for named
sequence management was calling a full verifier after renaming symbols.
The renaming could have potentially broken symbol table-related
invariants, but not really anything else. Only verify the symbol
table-related invariants instead.
DeltaFile
+8-4mlir/lib/Dialect/Transform/IR/Utils.cpp
+4-5mlir/test/Dialect/Transform/normal-forms.mlir
+12-92 files

LLVM/project 75d63afllvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/test/CodeGen/AArch64 itofp-bf16.ll itofp.ll

[AArch64] Fix lowering of non-power2 uitofp (#190921)

The code in DAGTypeLegalizer::SplitVecOp_TruncateHelper attempts to use
getFloatingPointVT(InElementSize/2), which is invalid for non-power2
type sizes. Fall back to the existing SplitVecOp_UnaryOp in this case.
DeltaFile
+77-0llvm/test/CodeGen/AArch64/itofp-bf16.ll
+72-0llvm/test/CodeGen/AArch64/itofp.ll
+2-2llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+151-23 files

LLVM/project f2efeabllvm/include/llvm/CodeGen MIRYamlMapping.h MachineFrameInfo.h, llvm/lib/CodeGen TargetOptionsImpl.cpp MachineFunction.cpp

[CodeGen] Parse frame-pointer attribute once when creating MachineFunction (#191974)

TargetOptions::DisableFramePointerElim is hot and showing up in
compile-time profiles via AArch64FrameLowering::hasFPImpl on
aarch64-O0-g builds. Repeatedly looking up the function attribute is
expensive. Parsing it once at MachineFunction initialisation and storing
as FramePointerKind on MachineFrameInfo is a -0.21% geomean improvement
on CTMark stage1-aarch64-O0-g. Also helps debug builds on other targets.

https://llvm-compile-time-tracker.com/compare.php?from=215f35eb8f1c313ac135ad47db1cc0b99b3ae694&to=51f6617517177bea1cc49baeab3acaf62d5e9df9&stat=instructions%3Au
DeltaFile
+61-0llvm/test/CodeGen/MIR/Generic/frame-info.mir
+19-18llvm/lib/CodeGen/TargetOptionsImpl.cpp
+17-0llvm/lib/CodeGen/MachineFunction.cpp
+14-0llvm/include/llvm/CodeGen/MIRYamlMapping.h
+10-0llvm/include/llvm/CodeGen/MachineFrameInfo.h
+2-0llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+123-182 files not shown
+126-188 files

LLVM/project 920b203lldb/source/Plugins/ABI/RISCV ABISysV_riscv.cpp, lldb/source/Plugins/DynamicLoader/POSIX-DYLD DynamicLoaderPOSIXDYLD.cpp

[lldb][RISCV] Implement access to TLS variables on RISC-V (#191410)

On RISC-V Linux, LLDB computes TLS variable addresses incorrectly:
`GetThreadLocalData` returns a correct tls_block, but then
unconditionally adds tls_file_addr from `DW_OP_GNU_push_tls_address`,
which on RISC-V/glibc is a VMA inside PT_TLS, not a pure offset. This
results in an over-shifted address.

This patch:

* Adds a small helper that, for an ELF module, finds the PT_TLS program
header and reads its p_vaddr.

* In `DynamicLoaderPOSIXDYLD::GetThreadLocalData`, normalizes
tls_file_addr to an offset: if `PT_TLS` is found and tls_file_addr >=
p_vaddr, it uses tpoff = tls_file_addr - p_vaddr, otherwise keeps the
old value.

* Returns tls_block + tpoff instead of always tls_block + tls_file_addr.

    [9 lines not shown]
DeltaFile
+54-2lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
+2-1lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
+1-1lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
+1-1llvm/docs/ReleaseNotes.md
+58-54 files

OpenBSD/src K3jh61ousr.bin/vi/cl cl_funcs.c, usr.bin/vi/common recover.c

   vi: avoid set but not used warnings

   From Walter Alejandro Iglesias
   ok claudio
VersionDeltaFile
1.15+2-4usr.bin/vi/ex/ex_append.c
1.24+1-5usr.bin/vi/cl/cl_funcs.c
1.14+2-3usr.bin/vi/ex/ex_bang.c
1.17+1-4usr.bin/vi/vi/vs_split.c
1.33+1-3usr.bin/vi/common/recover.c
1.18+1-3usr.bin/vi/ex/ex_global.c
+8-226 files

LLVM/project 9366436mlir/lib/Dialect/Tensor/IR TensorOps.cpp, mlir/lib/Dialect/Tensor/Transforms EmptyOpPatterns.cpp

[mlir][tensor] Preserve tensor encodings when materializing tensor.empty in some passes (#192411)

This PR fixes tensor encoding propagation bugs in some `tensor.empty`
materialization paths that could produce type-invalid IR (encoded result
expected, unencoded value produced).

Assisted-by: Cursor (Codex 5.3)
DeltaFile
+27-0mlir/test/Interfaces/TilingInterface/tile-pad-using-interface.mlir
+16-0mlir/test/Dialect/Tensor/fold-empty-op.mlir
+6-3mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
+4-2mlir/lib/Dialect/Tensor/Transforms/EmptyOpPatterns.cpp
+53-54 files

LLVM/project c95a333llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir arm64-irtranslator.ll

[AArch64][GlobalISel] FP Info implementation for AArch64. (#177158)

This work sits on top of #155107. The aim is to implement support for
extended types in the AArch64 backend.

Much of the implementation just builds upon #155107 but features changes to
the MatchTableExecutor to allow for matching multiple patterns to reduce
the need for duplicated patterns. This patch also features a new match
table opcode to match a pattern based on the shape of a type.

---------

Co-authored-by: David Green <david.green at arm.com>
DeltaFile
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+642-640llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+422-422llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir
+385-385llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
+277-277llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
+271-271llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
+2,659-2,657269 files not shown
+11,356-10,827275 files

LLVM/project bafbd54libc/hdr/types struct_linger.h CMakeLists.txt, libc/include CMakeLists.txt

[libc] Add "struct linger" (#192606)

Add a simple test to get/set the socket option. I didn't try to test the
actual lingering behavior. That sounds complicated and I'm not sure if
it's even doable on a loopback connection.
DeltaFile
+22-0libc/hdr/types/struct_linger.h
+19-0libc/test/src/sys/socket/linux/socketopt_test.cpp
+17-0libc/include/llvm-libc-types/struct_linger.h
+9-0libc/hdr/types/CMakeLists.txt
+1-0libc/include/llvm-libc-types/CMakeLists.txt
+1-0libc/include/CMakeLists.txt
+69-02 files not shown
+71-08 files

LLVM/project 234bc02llvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchLSXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx srlr.ll srar.ll

[LoongArch] Combine rounded vector shifts to VSRLR/VSRAR

Add DAG combines to recognize canonical rounded shift patterns and
lower them to target-specific vector rounded shift instructions.

The combines match vector arithmetic and logical right shifts with
rounding implemented as:

```
  add (srl/sra X, shift),
      (and (srl X, shift-1), 1)
```

and the shift-by-1 variant:

```
  add (srl/sra X, 1),
      (and X, 1)
```

    [14 lines not shown]
DeltaFile
+272-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+12-65llvm/test/CodeGen/LoongArch/lasx/srlr.ll
+12-65llvm/test/CodeGen/LoongArch/lsx/srlr.ll
+12-65llvm/test/CodeGen/LoongArch/lasx/srar.ll
+12-65llvm/test/CodeGen/LoongArch/lsx/srar.ll
+12-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+332-2601 files not shown
+340-2607 files

LLVM/project 6bf0edalldb/include/lldb/Utility StringExtractorGDBRemote.h, lldb/packages/Python/lldbsuite/test/tools/lldb-server gdbremote_testcase.py

[lldbserver] Implement support for MultiBreakpoint packet

This is fairly straightfoward, thanks to the helper functions created in
the previous commit.

https://github.com/llvm/llvm-project/pull/192910
DeltaFile
+59-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+2-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
+2-0lldb/source/Utility/StringExtractorGDBRemote.cpp
+1-0lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+1-0lldb/include/lldb/Utility/StringExtractorGDBRemote.h
+0-1lldb/test/API/functionalities/multi-breakpoint/TestMultiBreakpoint.py
+65-16 files

LLVM/project 265b240lldb/source/Plugins/Process/gdb-remote GDBRemoteCommunicationServerLLGS.cpp GDBRemoteCommunicationServerLLGS.h

[lldbremote][NFC] Factor out code handling breakpoint packets

This commit extracts the code handling breakpoint packets into a helper
function that can be used by a future implementation of the
MultiBreakpointPacket.

It is meant to be purely NFC.

There are two functions handling breakpoint packets (`handle_Z`
and `handle_z`) with a lot of repeated code. This commit did not attempt
to merge the two, as that would make the diff much larger due to subtle
differences in the error message produced by the two. The only
deduplication done is in the code processing a GDBStoppointType, where a
helper struct (`BreakpointKind`) and function (`std::optional<BreakpointKind> getBreakpointKind(GDBStoppointType stoppoint_type)`) was created.

https://github.com/llvm/llvm-project/pull/192910
DeltaFile
+147-105lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+28-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
+175-1052 files

LLVM/project 76fdccelldb/docs/resources build.rst

[lldb][docs] Update standalone build instructions (#192613)

* LLVM requires CMake 3.20
(https://llvm.org/docs/GettingStarted.html#software) so we do not need
to mention 3.14 anymore.
* CMAKE_BUILD_TYPE was listed twice in one command.
* "ninja" only works when in the build directory or given `-C <dir>`, so
I have changed that to "cmake --build" which works with ninja and other
build tools.
DeltaFile
+6-10lldb/docs/resources/build.rst
+6-101 files

LLVM/project f1fe791llvm/include/llvm/ObjectYAML DWARFYAML.h, llvm/lib/ObjectYAML DWARFEmitter.cpp DWARFYAML.cpp

[DWARFYAML] Add support for v5 debug_line file/dir entries (#192226)

This lets us specify all fields in the v5 header. Since v5 entries are
form-based, I've extracted the relevant parts of the debug_info DIE
writing code so it could be reused here as well.

The v5 file and directory entries are more expressive than <=v4 ones, so
one could in theory store everything in the v5 format, while still
reading (YAML) and writing (raw DWARF) in the old format. However, that
would create more corner cases (what if the data cannot be represented
in the older format), and it didn't seem like it was particularly
worthwhile to handle those.
DeltaFile
+143-2llvm/test/tools/yaml2obj/ELF/DWARF/debug-line-v5.yaml
+80-39llvm/lib/ObjectYAML/DWARFEmitter.cpp
+8-4llvm/lib/ObjectYAML/DWARFYAML.cpp
+5-0llvm/include/llvm/ObjectYAML/DWARFYAML.h
+236-454 files

LLVM/project 255190dlibcxx/cmake/caches AArch64.cmake Armv7Arm.cmake

[libcxx][ci] Set CMAKE_C_COMPILER_TARGET for all Arm/AArch64 builds (#192645)

As requested on #192493.

This is not strictly needed for native builds, but setting only
CMAKE_CXX_COMPILER_TARGET does look suspicious. Especially as we often
set both CXX_FLAGS and C_FLAGS in the same builds.

Set both C_COMPILER_TARGET and CXX_COMPILER_TARGET so on one has to
wonder if it's the cause of a problem.

(note that picolibc builds are already setting both)
DeltaFile
+1-0libcxx/cmake/caches/AArch64.cmake
+1-0libcxx/cmake/caches/Armv7Arm.cmake
+1-0libcxx/cmake/caches/Armv7Thumb-no-exceptions.cmake
+1-0libcxx/cmake/caches/Armv8Arm.cmake
+1-0libcxx/cmake/caches/Armv8Thumb-no-exceptions.cmake
+5-05 files

OPNSense/core 2e89bb5src/opnsense/www/js/widgets Services.js BaseWidget.js, src/opnsense/www/js/widgets/Metadata Core.xml

system: distill service widget essence based on #9608
DeltaFile
+10-36src/opnsense/www/js/widgets/Services.js
+2-2src/opnsense/www/js/widgets/Metadata/Core.xml
+2-2src/opnsense/www/js/widgets/BaseWidget.js
+14-403 files