FreeNAS/freenas e3e60dbsrc/middlewared/middlewared/plugins/update_ trains.py, src/middlewared/middlewared/pytest/unit/plugins/update test_trains.py

Allow the trains to be marked as unstable to make "the system can be upgraded only to the next train" constraint feasible
DeltaFile
+35-0src/middlewared/middlewared/pytest/unit/plugins/update/test_trains.py
+13-7src/middlewared/middlewared/plugins/update_/trains.py
+48-72 files

LLVM/project 376907eclang/lib/CrossTU CrossTranslationUnit.cpp

[NFC][clang][analyzer] Complete enumeration in emitCrossTUDiagnostics (#187646)

Make handling of all `index_error_code` values in
`CrossTranslationUnitContext::emitCrossTUDiagnostics` explicit.

--
CPP-7804
DeltaFile
+24-6clang/lib/CrossTU/CrossTranslationUnit.cpp
+24-61 files

FreeBSD/ports 78731dbwww/tomcat9 distinfo Makefile

www/tomcat9: Update 9.0.115 => 9.0.116

Changelog:
https://tomcat.apache.org/tomcat-9.0-doc/changelog.html#Tomcat_9.0.116_(remm)

MFH:    2026Q1
DeltaFile
+3-3www/tomcat9/distinfo
+1-2www/tomcat9/Makefile
+4-52 files

OPNSense/core 9861da2src/opnsense/mvc/app/views/layout_partials base_bootgrid_table.volt

bootgrid: set visibility hidden for base_bootgrid_table

Since the structure is used to initialize the bootgrid, we shouldn't render
the original structure possibly causing a flash of content.
DeltaFile
+1-1src/opnsense/mvc/app/views/layout_partials/base_bootgrid_table.volt
+1-11 files

LLVM/project 9c44aeallvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! Refactor TLBI tablegen
DeltaFile
+229-132llvm/lib/Target/AArch64/AArch64SystemOperands.td
+229-1321 files

LLVM/project f064a99llvm/lib/Target/ARM ARMISelLowering.cpp, llvm/test/CodeGen/ARM select_const.ll

[DAGCombine] Optimize away cond ? 1 : 0 post-legalization (#186771)

Selects of the form `cond ? 1 : 0` are created during unrolling of
setcc+vselect. Currently these are not optimized away post-legalization
even if fully redundant. Having these extra selects sitting between
things can prevent other folds from applying.

Enabling this requires some mitigations in the ARM backend, in
particular in the interaction with MVE support. There's two changes
here:

* Form CSINV/CSNEG/CSINC from CMOV, rather than only creating it during
SELECT_CC lowering. (After this change, the lowering in SELECT_CC can be
dropped without test changes, let me know if I should do that.)
* Support pushing negations through CMOV in more cases, in particular if
the operands are constant or the negation can be handled by flipping
lshr/ashr.

Additionally, in the X86 backend, try to simplify CMOV to SETCC if only the
low bit is demanded.
DeltaFile
+43-11llvm/lib/Target/ARM/ARMISelLowering.cpp
+20-28llvm/test/CodeGen/X86/vec-strict-cmp-sub128.ll
+23-23llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
+17-24llvm/test/CodeGen/ARM/select_const.ll
+10-18llvm/test/CodeGen/Thumb2/mve-pred-and.ll
+14-12llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
+127-1167 files not shown
+184-16413 files

LLVM/project fa49ad5libcxx/include/__cxx03/__algorithm shuffle.h, libcxx/test/std/algorithms/alg.modifying.operations/alg.random.shuffle random_shuffle_rand.pass.cpp

[libc++] Fix random_shuffle signature in C++03 mode with frozen headers (#186443)

The frozen C++03 headers got an invalid simplification in #134045 that
changed the signature of random_shuffle to use a forwarding reference
instead of a lvalue reference. This patch fixes it and adds a test.

---------

Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
DeltaFile
+33-32libcxx/test/std/algorithms/alg.modifying.operations/alg.random.shuffle/random_shuffle_rand.pass.cpp
+1-1libcxx/include/__cxx03/__algorithm/shuffle.h
+34-332 files

FreeBSD/ports 5b0c414Mk/Uses cabal.mk

Uses/cabal.mk: Also create ${CABAL_HOME} before "cabal update"

Fixes:  87a12423c24377eb05ab20aa44897ecd443c0f9e
DeltaFile
+1-0Mk/Uses/cabal.mk
+1-01 files

LLVM/project 0506c03llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.writelane.ll llvm.amdgcn.readlane.ll

AMDGPU/GlobalISel: RegBankLegalize rules for readlane, writelane (#187386)
DeltaFile
+14-15llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
+8-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+3-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
+2-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
+32-236 files

LLVM/project 7cc4692llvm/test/Transforms/PhaseOrdering/ARM arm_var_q31.ll

[ARM] Add a phase ordering test for multiple reductions. NFC
DeltaFile
+395-0llvm/test/Transforms/PhaseOrdering/ARM/arm_var_q31.ll
+395-01 files

LLVM/project 7025821llvm/tools/llc llc.cpp

[llc] Flatten SkipModule branch and sink defs to their use(NFC) (#187661)

- Invert the condition to make the code more straight and sink
single-use variables there.
- Add a comment about on `createTargetMachine` side effects for
`-mcpu=help`.
- Remove redundant call to `setPGOOptions`
DeltaFile
+57-60llvm/tools/llc/llc.cpp
+57-601 files

LLVM/project f58b675clang/lib/Driver ModulesDriver.cpp

[clang][ModulesDriver] Fix build failure with Xcode 14 (#187713)

As pointed out by
https://github.com/llvm/llvm-project/pull/152770#issuecomment-4096179622,
81e8a1e causes build errors with older versions of Xcode (Xcode 14 and
older) when using std::not_fn() with llvm::make_filter_range().

This implements the same fix as in d1d9413.
DeltaFile
+1-2clang/lib/Driver/ModulesDriver.cpp
+1-21 files

FreeNAS/freenas de7b082src/middlewared/middlewared/utils interface.py

Use netlink API for default interface detection with IPv6 fallback

This commit fixes Apps/Docker setup failing on IPv6 single-stack
deployments with "Unable to determine interface" error. The existing
get_default_interface() only read /proc/net/route (IPv4). This replaces
the procfs text parsing with the truenas_pynetif netlink API
(get_default_route), which tries IPv4 first and falls back to IPv6.
Dead constants RTF_GATEWAY and RTF_UP are removed.
DeltaFile
+8-8src/middlewared/middlewared/utils/interface.py
+8-81 files

LLVM/project f5e2238mlir/include/mlir/Dialect/XeGPU/IR XeGPUAttrs.td, mlir/lib/Dialect/XeGPU/Transforms XeGPULayoutImpl.cpp XeGPUPropagateLayout.cpp

[MLIR][XeGPU] Enhance multi-reduction layout propagation rules (#186308)

This PR enhance the multi-reduction layout propagation: 
1. improve inst_data and lane_data to support fractional subgroup size
2. improve subgroup_layout/data setup to utilize the (nested) slice
layout from consumer op

It also removes the restriction in load_matrix/store_matrix layout
propagation to allow nd (n>2) layout
DeltaFile
+91-57mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+83-0mlir/test/Dialect/XeGPU/propagate-layout.mlir
+34-24mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
+36-0mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
+12-6mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+0-2mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+256-896 files

FreeBSD/ports 28c3b53net/samba423 Makefile, net/samba423/files patch-lib_util_time.h patch-source4_torture_ndr_ndr.h

net/samba423: Add patches to fix ndr.h consumers (i.e. SSSD)

This is the same change that was applied to net/samba416 in
fd6a710e199bdba2b2df37a481038e743da895dd

PR:             293566
Approved by:    samba (maintainer timeout)
DeltaFile
+11-0net/samba423/files/patch-lib_util_time.h
+11-0net/samba423/files/patch-source4_torture_ndr_ndr.h
+1-0net/samba423/Makefile
+23-03 files

FreeBSD/ports 6850edanet/samba422 Makefile, net/samba422/files patch-lib_util_time.h patch-source4_torture_ndr_ndr.h

net/samba422: Add patches to fix ndr.h consumers (i.e. SSSD)

This is the same change that was applied to net/samba416 in
fd6a710e199bdba2b2df37a481038e743da895dd

PR:             293566
Approved by:    samba (maintainer timeout)
DeltaFile
+11-0net/samba422/files/patch-lib_util_time.h
+11-0net/samba422/files/patch-source4_torture_ndr_ndr.h
+1-0net/samba422/Makefile
+23-03 files

FreeBSD/ports bc1bc4bnet/samba420 Makefile, net/samba420/files patch-lib_util_time.h patch-source4_torture_ndr_ndr.h

net/samba420: Add patches to fix ndr.h consumers (i.e. SSSD)

This is the same change that was applied to net/samba416 in
fd6a710e199bdba2b2df37a481038e743da895dd

PR:             293566
Approved by:    samba (maintainer timeout)
DeltaFile
+11-0net/samba420/files/patch-lib_util_time.h
+11-0net/samba420/files/patch-source4_torture_ndr_ndr.h
+1-0net/samba420/Makefile
+23-03 files

FreeBSD/ports 4ab6b6bnet/samba419 Makefile, net/samba419/files patch-source4_torture_ndr_ndr.h patch-lib_util_time.h

net/samba419: Add patches to fix ndr.h consumers (i.e. SSSD)

This is the same change that was applied to net/samba416 in
fd6a710e199bdba2b2df37a481038e743da895dd

PR:             293566
Approved by:    samba (maintainer timeout)
DeltaFile
+11-0net/samba419/files/patch-source4_torture_ndr_ndr.h
+10-0net/samba419/files/patch-lib_util_time.h
+1-1net/samba419/Makefile
+22-13 files

LLVM/project d906208llvm/lib/IR Instructions.cpp

suppress warnings in Instructions.cpp

Created using spr 1.3.8-wip
DeltaFile
+6-0llvm/lib/IR/Instructions.cpp
+6-01 files

FreeNAS/freenas 9a77922src/middlewared/middlewared/utils/iscsi constants.py

Add ISCSIMODE
DeltaFile
+6-0src/middlewared/middlewared/utils/iscsi/constants.py
+6-01 files

NetBSD/src SaXbcMasys/arch/m68k/m68k vectors.c trap_subr.s

   The Coprocessor Protocol Violation trap is not present on the 68010
   (the vector is "unassigned, reserved"), so don't install a handler
   for it on that CPU.
VersionDeltaFile
1.8+9-2sys/arch/m68k/m68k/vectors.c
1.26+3-1sys/arch/m68k/m68k/trap_subr.s
+12-32 files

LLVM/project 4c60d48clang/lib/Sema SemaDeclCXX.cpp, clang/test/CodeGenCXX dllexport-inherited-ctor.cpp

[clang] Don't dllexport inherited constructors with -fno-dllexport-inlines (#187684)

The inherited constructors are inline thunks, so like other inline
functions they are exempted from ABI compatibility concerns with this
flag, and should not be exported.

This is a follow-up to #182706
DeltaFile
+11-13clang/test/CodeGenCXX/dllexport-inherited-ctor.cpp
+3-8clang/lib/Sema/SemaDeclCXX.cpp
+1-0clang/test/SemaCXX/dllexport-constrained-inherited-ctor.cpp
+15-213 files

LLVM/project a3db68allvm/test/tools/llvm-debuginfod-find/Inputs capture_req.py

[llvm] Restrict llvm-debginfod-find test to localhost to fix winhttp case (#187705)

Listening on all interfaces is probably not permitted on the bots and
causes failures of llvm-debuginfod-find/headers-winhttp.test after
39d6bb21804d21abe2fa0ec019919d72104827ac. Restricting them to localhost
should fix that.
DeltaFile
+1-1llvm/test/tools/llvm-debuginfod-find/Inputs/capture_req.py
+1-11 files

LLVM/project d339d00llvm/utils/gn/secondary/clang/lib/Analysis BUILD.gn

[gn] port a021a93e5320d8
DeltaFile
+0-2llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
+0-21 files

LLVM/project 17d2890llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Core BUILD.gn

[gn] port 7bf871c39f739
DeltaFile
+1-0llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Core/BUILD.gn
+1-01 files

FreeBSD/src 8475cd9share/man/man4/man4.arm dwcotg.4 Makefile

dwcotg.4: Initial manual page

Create visibility in apropos and the Hardware Release Notes.

MFC after:              3 days
Reviewed by:            pauamma, ray
Differential Revision:  https://reviews.freebsd.org/D53287
DeltaFile
+29-0share/man/man4/man4.arm/dwcotg.4
+1-0share/man/man4/man4.arm/Makefile
+30-02 files

LLVM/project 4a1e9f7clang/include/clang/CIR LowerToLLVM.h, clang/lib/CIR/FrontendAction CIRGenAction.cpp

[CIR] Make the -save-temps flag emit .cir and .mlir files (#186814)

This patch makes ClangIR emit .cir and .mlir files when the-save-temps
flag is specified. Having these files emitted is useful e.g. when
inspecting the generated code for OpenMP offloading.

Co-authored-by: Claude Opus 4.6 noreply at anthropic.com
DeltaFile
+25-3clang/lib/CIR/FrontendAction/CIRGenAction.cpp
+20-0clang/test/CIR/CodeGen/save-temps.c
+10-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+3-1clang/include/clang/CIR/LowerToLLVM.h
+58-54 files

LLVM/project 40a6180flang/lib/Optimizer/Analysis AliasAnalysis.cpp, flang/test/Analysis/AliasAnalysis alias-analysis-omp-private-boxed-array.mlir

[Flang] - Fix AliasAnalysis to preserve Allocate source kind through box loads (#187152)

When a boxed array is privatized via `omp.private`, the `SourceKind` of
the loaded box data was being misclassified as `SourceKind::Indirect` by
the alias analyzer. Instead its `SourceKind::Allocate` should be
preserved. This caused AliasAnalysis to conservatively return `MayAlias`
for accesses to privatized arrays vs dummy arguments. This prevented
InlineHLFIRAssign from inlining array section assignments.

Propagate the Allocate source kind when the box source is classified as
`Allocate`, so that alias analysis correctly returns `NoAlias`.
DeltaFile
+68-0flang/test/Analysis/AliasAnalysis/alias-analysis-omp-private-boxed-array.mlir
+5-1flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
+73-12 files

FreeBSD/src 0661997stand/efi/loader main.c

loader(8): embedded MD should be the most preferred currdev

A loader built with MD_IMAGE_SIZE is almost always meant for use with
its embedded image and should try that as currdev before anything else.
Recent changes (d69fc3a9dc71, 784150fd2535) seem to have relaxed the ZFS
code's search for a rootfs and exposed this problem.

Reviewed by:    imp, tsoome
MFC after:      1 week
Sponsored by:   Chelsio Communications
Differential Revision:  https://reviews.freebsd.org/D55979
DeltaFile
+9-9stand/efi/loader/main.c
+9-91 files

OPNSense/core ff4602fsrc/opnsense/mvc/app/views/layout_partials base_apply_button.volt, src/opnsense/www/js opnsense_bootgrid.js

mvc: base apply button fixed positioning
DeltaFile
+11-2src/opnsense/www/js/opnsense_bootgrid.js
+5-4src/opnsense/mvc/app/views/layout_partials/base_apply_button.volt
+16-62 files