[mlir][Interfaces] Allow integer types for `ValueBoundsOpInterface` (#196082)
Allow integer-typed SSA values in the `ValueBoundsConstraintSet`
infrastructure. Only index types were allowed until now. This new
feature is opt-in only. The implementation assumes that integer
computation will not overflow.
A new `ValueBoundsOptions` struct is added. Public entry points now take
this struct instead of the `closedUB` flag. The flag was moved to the
options struct, along with the `allowIntegerType` flag.
Note for LLVM integration: Pass `ValueBoundsOptions` instead of `bool
closedUB`.
Assisted-by: gpt-5.5-extra-high
[RISCV][MC][NFC] Update IME vtype layout to match latest spec `riscv-isa-release-fa55752-2026-05-04` (#195998)
This updates the IME-specific vtype field layout to match the [latest
IME spec, version
riscv-isa-release-fa55752-2026-05-04](https://github.com/riscv/integrated-matrix-extension/blob/main/src/integrated-matrix.adoc#new-fields-in-the-vector-type-vtype-register).
The latest spec places the IME fields as:
| Field | New Position | Change Description |
|---------------|---------------------------|---------------------------------|
| `lambda[2:0]` | `vtype[XLEN-2:XLEN-4]` | Unchanged |
| `bs` | `vtype[XLEN-5]` | Moved from `vtype[XLEN-7]` |
| `altfmt_A` | `vtype[XLEN-6]` | Moved from `vtype[XLEN-5]` |
| `altfmt_B` | `vtype[XLEN-7]` | Moved from `vtype[XLEN-6]` |
Previously `bs`, `altfmt_A`, and `altfmt_B` followed the older ordering,
which was first introduced in #193956. The new position of altfmt
supports growing in the future for more datatypes.
This patch also updates tests to reflect field changes.
Currently this should be NFC since we didn't have any CodeGen
implementation that involves vtype in IME.
Avoid some premature optimization in pmap_enter() and pmap_changebit(),
flushing the ATC entry for the VA when more bits other than the "critical"
cache-inhibit and write-protect bits change. We want to avoid a situation
where the ATC has a stale U or M bit that's been cleared from the PTE out
in RAM, which can lead to a situation where the U or M bit doesn't get
written back because the MMU doesn't think it's transitioned from 0 to 1.
[libc][docs] Minor typos in Documentation (#196066)
- removed a duplicate "to" in dev/undefinde_behaviour.rst
- corrected "in order or link" to "inorder to link" in gpu/using.rst
Signed-off-by: udaykiriti <udaykiriti624 at gmail.com>
[InstCombine] Drop alignment assumptions more aggressively (#196060)
`computeKnownBits` gets a context instruction now, which allows dropping
assumes based on previous assumes.
ui: add save/cancel button support to form rendering
This is a fringe use case, but it's better to do this here
than to handroll upcoming changes in the ipsec connections page.
(cherry picked from commit 097f2e8fd070f3867bb02c88aa42bafd6af2c61e)
