LLVM/project ce53940llvm/test/CodeGen/Generic/GlobalISel irtranslator-byte-type.ll

Revert "[IRTranslator] Precommit tests for bitcasts of the byte type #203638 (#204378)

This reverts commit 7e5bc4c7bd23e390cdb0b08f807968ea256b0df2 as the
MachineVerifier identifies 'bad machine code'.
DeltaFile
+0-497llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
+0-4971 files

LLVM/project 4a9cb1flibcxx/docs PostMeetingProcedure.rst index.rst

[libc++] Document post-WG21-meeting conformance update procedure (#204357)

This patch adds a section in the documentation to explain the procedure
to follow after a WG21 meeting to properly track papers. This should
clear out some confusion about how this process happens and who should
be responsible for doing it.
DeltaFile
+100-0libcxx/docs/PostMeetingProcedure.rst
+1-0libcxx/docs/index.rst
+101-02 files

LLVM/project cbd76dclldb/source/Host/macosx/objcxx Host.mm

[lldb] Fix race in macOS's FindProcessesImpl (#204109)

Our current FindProcessImpl has a TOCTOU bug where we first query the
buffer size we should provide via sysctl and then later pass a buffer
with that size to be filled. If the list of processes grows larger than
the buffer we pass, then our current implementation fails by returning
an empty list of processes. This race only happens rarely in practice as
we pad the buffer size with 10 additional entries to account for some
process growth.

This patch replaces this logic by a backoff loop that retries fetching
the process list if our buffer is too small (sysctl tells us if this is
the case by setting ENOMEM). This new implementation can only fail in
the system consistently spawns thousands of new processes between
each retry.

This should fix the actual root-cause for the random failures in
TestSimulator.py
DeltaFile
+77-20lldb/source/Host/macosx/objcxx/Host.mm
+77-201 files

LLVM/project d84819dllvm/lib/Target/NVPTX NVPTXAsmPrinter.cpp

[NVPTX] Fix build break from #201217 (#204380)

#201217 added a third `SymbolSize` argument to `AggBuffer::addSymbol()`
but missed one call site, which was added by 98160521cb72 after the PR
branch was cut. Pass `AllocSize` like the sibling calls do.
DeltaFile
+1-1llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+1-11 files

FreeNAS/freenas 741f2e5src/middlewared/middlewared/plugins/hardware m_series_nvdimm.py __init__.py, src/middlewared/middlewared/pytest/unit/alert/source test_mseries_nvdimm.py

NAS-141417 / 27.0.0-BETA.1 / Convert hardware plugin to the typesafe pattern (#19145)

## Context
The hardware plugin is a directory of four mostly-private legacy
services (mseries.bios, mseries.nvdimm, hardware.memory, plus
hardware.virtualization). Only hardware.virtualization.variant is public
over the wire; the rest return plain dicts/bools consumed internally by
alert sources and usage reporting, so Pydantic models would be pure
overhead.

## Solution
Applied the port-plugin pattern: lean Service shims in __init__.py that
delegate to plain, fully type-annotated module functions, keeping the
existing dict/primitive return shapes so no consumer changes are needed.
The one public method gets check_annotations=True against the existing
HardwareVirtualizationVariant models. Registered the services in
main.py's ServiceContainer via nested hardware/mseries containers and
added the plugin to mypy.yml.
DeltaFile
+210-170src/middlewared/middlewared/plugins/hardware/m_series_nvdimm.py
+106-0src/middlewared/middlewared/pytest/unit/alert/source/test_mseries_nvdimm.py
+80-0src/middlewared/middlewared/plugins/hardware/__init__.py
+36-43src/middlewared/middlewared/plugins/hardware/mem_info.py
+50-0src/middlewared/middlewared/pytest/unit/api/handler/result/test_dataclasses.py
+11-35src/middlewared/middlewared/plugins/hardware/virt_detection.py
+493-2487 files not shown
+582-28813 files

FreeBSD/src 00c8e76usr.sbin/bsdconfig/dot USAGE

bsdconfig: Update dot USAGE

graphics/gx is no longer in ports, remove reference
DeltaFile
+0-7usr.sbin/bsdconfig/dot/USAGE
+0-71 files

FreeNAS/freenas d53d64fsrc/middlewared/middlewared/api/base/server doc.py, src/middlewared/middlewared/plugins/pool_ dataset_encryption_info.py dataset_processes.py

ruff appeasement
DeltaFile
+60-57src/middlewared/middlewared/pytest/unit/api/base/server/test_reflow_docstring.py
+5-1src/middlewared/middlewared/plugins/zfs/snapshot_crud.py
+1-1src/middlewared/middlewared/plugins/pool_/dataset_encryption_info.py
+1-1src/middlewared/middlewared/plugins/pool_/dataset_processes.py
+0-1src/middlewared/middlewared/api/base/server/doc.py
+67-615 files

LLVM/project 12d560dllvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU amdgpu-codegenprepare-idiv.ll srem64.ll

[AMDGPU] Remove unnecessary and broken sign/zero-extension (#203436)

When expanding div/rem by using floating-point operations,
sign/zero-extending the result from the calculated DivBits input width
to 32-bits is unnecessary. CreateFPToSI or CreateFPToUI is called with a
32-bit int type so the conversion instruction will already produce a
result with the desired width.

Also it is incorrect. For signed-division `DIVBITS_MAX_NEG/-1`, the
result should be `-DIVBITS_MAX_NEG` a positive value. Sign-extension
will incorrectly return a negative result. For example, for DivBits=4,
`-8/-1 = 8`, but adding code to do a 28-bit sign-extension will
incorrectly return `-8`.

Tested in https://github.com/llvm/llvm-test-suite/pull/423.

---------

Signed-off-by: John Lu <John.Lu at amd.com>
DeltaFile
+58-142llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+36-46llvm/test/CodeGen/AMDGPU/srem64.ll
+1-15llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+3-6llvm/test/CodeGen/AMDGPU/sdiv.ll
+0-4llvm/test/CodeGen/AMDGPU/sdiv64.ll
+1-2llvm/test/CodeGen/AMDGPU/divrem24-assume.ll
+99-2151 files not shown
+99-2167 files

LLVM/project 5786efbllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

Stray comment
DeltaFile
+0-3llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+0-31 files

LLVM/project 16e32c9llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-3.ll

Remove case that isn't needed here, update tests
DeltaFile
+8-4llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
+0-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+8-62 files

LLVM/project b949373llvm/lib/Target/M68k M68kInstrData.td M68kInstrAtomics.td, llvm/test/CodeGen/M68k/Atomics load-store.ll

[M68k] Do not allow addressing modes k and q as MOVE targets (llvm#200826) (#201653)

This is intended as a fix for #200826 by removing PC-relative address
modes from the m68k MOVE patterns. It also affects MOVEM, and the
"atomic store" pattern that maps to the respective MOVE instruction as
well. This patch is based on the big patch authored by Gemini at
https://github.com/llvm/llvm-project/issues/181481#issuecomment-4476933700
, but as has been carefully trimmed to just address one single issue,
and every change has been verified to make sense. Gemini also restricted
the list of source addressing modes for MOVEM to the valid destination
addressing modes, which is not required according to the Motorola
specification.
DeltaFile
+14-13llvm/lib/Target/M68k/M68kInstrData.td
+21-0llvm/test/CodeGen/M68k/Atomics/load-store.ll
+11-7llvm/test/CodeGen/M68k/CodeModel/Small/small-static.ll
+0-8llvm/lib/Target/M68k/M68kInstrAtomics.td
+4-3llvm/test/CodeGen/M68k/Control/cmp.ll
+3-2llvm/test/CodeGen/M68k/CodeModel/Small/small-pic.ll
+53-331 files not shown
+53-357 files

LLVM/project f77ca48llvm/test/tools/llvm-exegesis/X86 analysis-unknown-opcode-did-you-mean.test, llvm/tools/llvm-exegesis/lib BenchmarkResult.cpp

[llvm-exegesis] Add did-you-mean hint for unknown opcodes (#203463)

Fixes #203199

When skipping a benchmark entry with an unknown opcode name, suggest the
nearest matching opcode if the edit distance is <= 1 (similar to
OptTable::findNearest).

Example:
```text
warning: skipping benchmark entry: No opcode with name 'VADDPDYrrr' - did you mean 'VADDPDYrr' ?
```

And Tested with:
- `llvm-lit
llvm/test/tools/llvm-exegesis/X86/analysis-unknown-opcode-did-you-mean.test`
- `llvm-lit
llvm/test/tools/llvm-exegesis/X86/analysis-skip-unknown-opcode.test`


    [2 lines not shown]
DeltaFile
+53-0llvm/test/tools/llvm-exegesis/X86/analysis-unknown-opcode-did-you-mean.test
+36-1llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
+89-12 files

LLVM/project c625725llvm/lib/Target/NVPTX NVPTXAsmPrinter.cpp NVPTXAsmPrinter.h, llvm/test/CodeGen/NVPTX packed-aggr.ll

[NVPTX] Properly emit narrow ptrtoint in aggregate initializers. (#201217)

If you have a 64-bit pointer and use ptrtoint to convert it to an i32,
that's supposed to return the low 32 bits of the pointer.

But if you use a narrowing ptrtoint inside a global aggregate
initializer, we currently don't mask the bytes.  For this IR:

    @g = addrspace(1) global i32 0
    @s = addrspace(1) global { i32, i32 }
           { i32 ptrtoint (ptr addrspace(1) @g to i32), i32 0xdeadbeef }

on nvptx64 we emitted

    .u64 s[1] = {g};

i.e. we emitted the full 64-bit address of `@g`, and entirely dropped
the
trailing i32 (0xdeadbeef).

    [2 lines not shown]
DeltaFile
+12-7llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+14-1llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
+11-0llvm/test/CodeGen/NVPTX/packed-aggr.ll
+37-83 files

LLVM/project de2ad35llvm/lib/Target/DirectX DXContainerPDB.cpp

Use Twine in error message
DeltaFile
+2-2llvm/lib/Target/DirectX/DXContainerPDB.cpp
+2-21 files

FreeNAS/freenas 2e17be6src/middlewared/middlewared/plugins/apps/ix_apps query.py

map known exit codes to exited instead of crashed
DeltaFile
+8-2src/middlewared/middlewared/plugins/apps/ix_apps/query.py
+8-21 files

LLVM/project 264119fllvm/test/CodeGen/Generic/GlobalISel irtranslator-byte-type.ll

Revert "[IRTranslator] Precommit tests for bitcasts of the byte type (#203638)"

This reverts commit 7e5bc4c7bd23e390cdb0b08f807968ea256b0df2
as the MachineVerifier identifies 'bad machine code'.
DeltaFile
+0-497llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
+0-4971 files

LLVM/project 5a5d0fbllvm/lib/Transforms/Scalar SimpleLoopUnswitch.cpp, llvm/test/Transforms/PhaseOrdering unswitch-nontrivial-cold-func.ll

[SimpleLoopUnswitch] Generalize the notion of trivial unswitching (#193989)

For a loop like this 

```
     for (int j = 0; j < M; j++) {
       if (N <= 0) continue;          // invariant guard branches to latch
       for (int i = 0; i < N; i++)
         A[i] = B[i] + 1;
     }
```
Since none of the successors of the guard branch of the inner loop are
outside the loop `j`, unswitching treats this as a non-trivial branch.
In reality, this is a perfect loop nest. If the condition of the guard
of `i` loop is false, there is nothing to do and so if we unswitch this
branch, the loop does not need to be versioned. This matches the
requirements of a trivial unswitch. This patch extends trivial loop
unswitching to catch cases like this.


    [3 lines not shown]
DeltaFile
+1,031-0llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-loop-guard.ll
+114-0llvm/test/Transforms/PhaseOrdering/unswitch-nontrivial-cold-func.ll
+31-31llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
+29-29llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
+48-3llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
+19-30llvm/test/Transforms/SimpleLoopUnswitch/PGO-nontrivial-unswitch2.ll
+1,272-935 files not shown
+1,316-13411 files

LLVM/project 96127e6offload/plugins-nextgen/amdgpu/src rtl.cpp, offload/plugins-nextgen/common/include PluginInterface.h

[Offload] Fix pessimistic max block count sizing on AMDGPU (#204242)

Summary:
For whatever reason, HSA copied the questionable choices that OpenCL
made and represents its launch parameters in a threads * blocks grid.
The problem is that you then combine this with an `int32_t` interface,
so you have 31 bits to represent your launch. We were then
pessimistically stating that your launch always had 1024 threads, which
left us with 2^21. This is only about two million which people do all
the time, and this caused us to perform weird clamping in OpenMP. The
effect was that tests like ompx_saxpy_mixed.c was hitting that clamp and
returning wrong results.

Also fix the sanitizer tests failing because of HSA core dumps.
DeltaFile
+9-7offload/plugins-nextgen/common/src/PluginInterface.cpp
+12-0offload/plugins-nextgen/amdgpu/src/rtl.cpp
+5-1offload/plugins-nextgen/common/include/PluginInterface.h
+26-83 files

LLVM/project fed43e4llvm/test/CodeGen/AMDGPU float-to-arbitrary-fp.ll, llvm/test/CodeGen/Mips/msa f16-llvm-ir.ll

Merge branch 'main' into users/krzysz00/extract-insert-dagcombine
DeltaFile
+2,274-2,366llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+2,457-0llvm/test/CodeGen/X86/float-to-arbitrary-fp.ll
+1,067-1,096llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
+966-1,105llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
+2,052-0llvm/test/CodeGen/NVPTX/float-to-arbitrary-fp.ll
+1,411-0llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
+10,227-4,567885 files not shown
+33,303-13,455891 files

LLVM/project 22d7698mlir/lib/Dialect/GPU/Pipelines GPUToXeVMPipeline.cpp

[MLIR][GPUToXeVMPipeline] Expand MX scaling ops before XeVM conversion (#203632)

arith.scaling_extf/scaling_truncf were never lowered by the
gpu-lower-to-xevm pipeline, so micro-scaling (MX) GEMM kernels kept
these ops (and their narrow-float operands) live all the way to LLVM
translation.

Run arith-expand before the XeVM/LLVM conversions to break
scaling_extf/scaling_truncf into extf/truncf + mulf and to expand
f8E8M0FNU casts into integer bit manipulation. f4E2M1FN expansion is
intentionally left disabled: its casts are lowered by the XeVM
conversions (xevm.extf), whereas f8E8M0FNU is not handled there and must
be expanded here. The generic f4E2M1FN expansion would otherwise emit i4
vector arithmetic that the XeVM backend cannot legalize.
DeltaFile
+13-0mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
+13-01 files

LLVM/project 5fcb285mlir/lib/Conversion/XeGPUToXeVM XeGPUToXeVM.cpp, mlir/test/Conversion/XeGPUToXeVM loadstore_matrix.mlir

[MLIR][XeGPU] Fix load_matrix lowering for non-LLVM element types (#203629)

LoadStoreMatrixToXeVMPattern built the llvm.load result from the raw op
result element type. For element types without a direct LLVM
representation (e.g. f8E8M0FNU) this produced an illegal op: 'llvm.load'
op result #0 must be LLVM type with size, but got 'f8E8M0FNU'.

Derive the load result type from the type converter instead. This maps
such element types to an integer storage type of the same bit width,
collapses single-element vectors to a scalar, and flattens multi-element
vectors. The store path already used the converted operand and is
unchanged; the XeVM type converter's materialization casts bridge the
loaded value back to the original vector type for downstream consumers.

Add load_matrix regression tests for f8E8M0FNU (scalar and vector).
DeltaFile
+25-1mlir/test/Conversion/XeGPUToXeVM/loadstore_matrix.mlir
+8-10mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
+33-112 files

FreeBSD/ports f2d991cnet-mgmt/librenms distinfo Makefile

net-mgmt/librenms: Update to 26.6.1

re: https://github.com/librenms/librenms/releases/tag/26.6.1
DeltaFile
+5-5net-mgmt/librenms/distinfo
+2-2net-mgmt/librenms/Makefile
+7-72 files

LLVM/project d76dd87lldb/cmake/modules AddLLDB.cmake, lldb/source/Plugins/ScriptInterpreter/Lua CMakeLists.txt

[lldb] Fix LLDB_BUILD_FRAMEWORK with the dynamic script interpreters (#204265)

When using LLDB_ENABLE_DYNAMIC_SCRIPTINTERPRETERS (the default on Darwin
as of #204015), the PluginManager loads at runtime by scanning the
directory that holds liblldb. A framework build moves liblldb into
LLDB.framework, but the plugins were only emitted into lib/ and never
copied into the bundle, so they were never found.

Add lldb_add_scriptinterpreter_plugin_to_framework(), called from the
Python and Lua plugin CMakeLists, which copies the plugin next to the
framework binary and appends an rpath so it can resolve liblldb from
inside the bundle. The copy uses the plugin's unversioned name because
PluginManager derives the initializer symbol from it (a versioned copy
would load but never register). Non-framework builds are unaffected.
DeltaFile
+25-0lldb/cmake/modules/AddLLDB.cmake
+2-0lldb/source/Plugins/ScriptInterpreter/Lua/CMakeLists.txt
+2-0lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
+29-03 files

LLVM/project 0176227llvm/include/llvm/Transforms/Utils Local.h, llvm/lib/Transforms/Utils SimplifyCFG.cpp

[SimplifyCFG] Use context instruction in foldBranchToCommonDest() (#203516)

When determining whether instructions can be speculate, pass the
terminator of the predecessor as the context instruction.

Only do this for the single predecessor case, otherwise we'd have to
perform one query per predecessor. The multi-predecessor case is
excluded by the default cost model anyway.
DeltaFile
+246-0llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
+7-2llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+1-0llvm/include/llvm/Transforms/Utils/Local.h
+254-23 files

LLVM/project d398331lldb/unittests CMakeLists.txt

[lldb][unittests] Add LLDB_UNITTEST_STRIP_DEBUG_INFO to cut unittest link time (#203274)

Add an opt-in cache option (default OFF). When ON, every target declared
via `add_lldb_unittest` links without per-target debug info and
dead-strips:
- **MSVC**: `/DEBUG:NONE + /INCREMENTAL:NO + /OPT:REF + /OPT:ICF`
- **clang/gcc**: `-g0 + LINKER:--strip-debug` (or `LINKER:-S` on macOS).

This drastically speeds up linking the unittests executable when
building with debug info on Windows.
DeltaFile
+16-0lldb/unittests/CMakeLists.txt
+16-01 files

LLVM/project 616f771llvm/lib/Target/DirectX DXContainerPDB.cpp

Use c_str for formatv
DeltaFile
+2-2llvm/lib/Target/DirectX/DXContainerPDB.cpp
+2-21 files

LLVM/project a6ae624clang/include/clang/Options Options.td, clang/lib/Driver/ToolChains Clang.cpp

[Driver][DirectX] Add /Qembed_debug and /Fd flags
DeltaFile
+30-40llvm/lib/Target/DirectX/DXContainerGlobals.cpp
+38-0llvm/test/CodeGen/DirectX/ContainerData/ContainerFlags.ll
+18-9clang/include/clang/Options/Options.td
+22-0llvm/test/CodeGen/DirectX/ContainerData/DebugName.test
+19-0clang/lib/Driver/ToolChains/Clang.cpp
+15-0llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
+142-4913 files not shown
+201-6419 files

LLVM/project ef3499ellvm/lib/Target/AMDGPU GCNRegPressure.cpp GCNRegPressure.h

Changed method name from setPhysRegTracking to updatePhysRegTracking.
DeltaFile
+2-2llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+2-2llvm/lib/Target/AMDGPU/GCNRegPressure.h
+1-1llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+5-53 files

LLVM/project 16f0408llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU BUILD.gn

[gn build] Port 2964323a936c (#204374)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
+1-01 files

LLVM/project 0926a1bllvm/utils/gn/secondary/llvm/include/llvm/IR BUILD.gn

[gn] port dcda5e1719a5e (#204373)
DeltaFile
+5-0llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn
+5-01 files