FreeBSD/doc 11cd18cwebsite/content/en/cgi ports.cgi

ports.cgi: show and filter existing flavor(s)
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HardenedBSD/ports f12c5acaudio/musicpd distinfo, devel/radicle Makefile

Merge branch 'freebsd/main' into hardenedbsd/main
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+11-11editors/cudatext/distinfo
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+3-3textproc/py-grep-ast/distinfo
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+43-4214 files

LLVM/project d368773clang/lib/AST/ByteCode InterpBuiltin.cpp Context.cpp, clang/test/AST/ByteCode object-size-flex-array.c builtin-object-size-codegen.c

[clang][bytecode] Use in Expr::tryEvaluateObjectSize() (#179197)

This is like https://github.com/llvm/llvm-project/pull/179033, which
broke a few builders for reasons I still don't really understand. I ran
the other clang tests and this version fixes a few of the introduced
regressions.

This still regresses `CodeGen/pass-object-size.c`, but that's a
pre-existing issue.

Patch is of coursed based on #179033 by @mariusdr.
DeltaFile
+156-0clang/test/AST/ByteCode/object-size-flex-array.c
+44-33clang/lib/AST/ByteCode/InterpBuiltin.cpp
+37-0clang/test/AST/ByteCode/builtin-object-size-codegen.c
+31-0clang/lib/AST/ByteCode/Context.cpp
+13-0clang/lib/AST/ByteCode/Context.h
+6-6clang/lib/AST/ByteCode/EvalEmitter.cpp
+287-393 files not shown
+295-399 files

LLVM/project 98c38f4clang/lib/Analysis/LifetimeSafety LifetimeAnnotations.cpp, clang/test/Sema warn-lifetime-analysis-nocfg.cpp

stl algorithms lifetimebound
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+30-3clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
+23-0clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
+3-0clang/test/Sema/Inputs/lifetime-analysis.h
+56-33 files

LLVM/project c8d7791llvm/include/llvm/ADT GenericUniformityImpl.h, llvm/include/llvm/CodeGen TargetInstrInfo.h

Implement per-output machine uniformity analysis
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+76-14llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+27-11llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+14-14llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/per-output-uniformity.mir
+16-5llvm/include/llvm/ADT/GenericUniformityImpl.h
+4-4llvm/lib/Target/AMDGPU/SIInstrInfo.h
+4-3llvm/include/llvm/CodeGen/TargetInstrInfo.h
+141-512 files not shown
+146-548 files

LLVM/project b05946dllvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR per-output-uniformity.mir

[AMDGPU] Add test for amdgcn.if/else per-output uniformity (NFC)
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+78-0llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/per-output-uniformity.mir
+78-01 files

LLVM/project 0070a4allvm/lib/Target/AMDGPU VOP3PInstructions.td SIInstrInfo.h, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h

AMDGPU: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3

Codegen for v_dual_dot2acc_f32_f16/bf16 for targets that only have VOP3
version of the instruction.
Since there is no VOP2 version, instroduce temporary mir DOT2ACC pseudo
that is selected when there are no src_modifiers. This DOT2ACC pseudo
has src2 tied to dst (like the VOP2 version), PostRA pseudo expansion will
restore pseudo to VOP3 version of the instruction.
CreateVOPD will recoginize such VOP3 pseudo and generate v_dual_dot2acc.
DeltaFile
+62-56llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+48-47llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+35-4llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+13-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+8-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+7-1llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+173-1084 files not shown
+182-11310 files

LLVM/project 2f3419cllvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] Add const
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LLVM/project af0668ellvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] Avoid repeating the type
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+2-1llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+2-11 files

LLVM/project e6ce1a2llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] add const and rename
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+9-8llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+9-81 files

LLVM/project 9c7e6c8llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] reuse vector
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+2-2llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+2-21 files

LLVM/project 6461b82llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] miscleaneaous renaming
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+34-37llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+34-371 files

LLVM/project b29192dllvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] found -> reached
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+1-1llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+1-11 files

LLVM/project bfc0e2ellvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] Move loop body to helper method
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+19-14llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+19-141 files

LLVM/project 4f3bf04llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] move second loop to helper method
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+15-9llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+15-91 files

LLVM/project ab7b0f7llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] Address typo in .clear() and me being lazy and not doing a .find()
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+22-14llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+22-141 files

LLVM/project 80ced5cllvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2 exec_mode3.ll

[SPIRV] Emit intrinsics for globals only in function that references them

In the SPIRV backend, the SPIRVEmitIntrinscs::processGlobalValue
function adds intrinsic calls for every global variable of the module,
on every function.

These intrinsics are used to keep track of global variables, their types and
initializers.

In SPIRV everything is an instruction (even globals/constants). We currently
represent these global entities as individual instructions on every function.
Later, the `SPIRVModuleAnalysis` collects these entities and maps function _local_ registers
to _global_ registers. The `SPIRVAsmPrinter` is in charge of mapping back the _local_
registers to the appropiate _global_ register.

These instructions associated with global entities on functions that do not reference them leads
to a bloated intermediate representation and high memory consumption (as it happend
in https://github.com/llvm/llvm-project/issues/170339).


    [25 lines not shown]
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+48-38llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
+46-30llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll
+38-2llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+15-15llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_faddfsub_vec_float16.ll
+15-15llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_fminfmax_vec_float16.ll
+162-1005 files

LLVM/project fd47c99llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] Compute which functions reach which globals only once
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+82-26llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+82-261 files

NetBSD/pkgsrc HllTJD6doc CHANGES-2026

   doc: Updated pkgtools/mktool to 1.5.5
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1.835+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc ErDFM5Kpkgtools/mktool distinfo cargo-depends.mk

   mktool: Update to 1.5.5.

   ## Version 1.5.5 (2026-01-30)

   * fetch: Support connect timeouts for both HTTP and FTP, and read timeouts
     for FTP.  MKTOOL_CONNECT_TIMEOUT and MKTOOL_READ_TIMEOUT allow the
     defaults to be overriden, primarily useful for tests.

   * fetch: Fix temp file leak when HTTP body transfer fails mid-download.

   * CI: Add workflows to test both feature sets, and improve test coverage.
VersionDeltaFile
1.24+22-22pkgtools/mktool/distinfo
1.19+7-7pkgtools/mktool/cargo-depends.mk
1.27+2-2pkgtools/mktool/Makefile
+31-313 files

FreeBSD/doc b48dfa7website/content/en/cgi ports.cgi

ports.cgi: handle HTML in description
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FreeBSD/src e63ee5fsys/dev/e1000 if_em.c

e1000: Fix setting the promiscuous mode

The variable reg_rctl stores the value read from reg E1000_RCTL. It
may contain bits E1000_RCTL_VFE and E1000_RCTL_CFIEN which control
VLAN hardware filter feature. The promiscuous mode implies all tagged
or untagged packets should be accepted, so the VLAN hardware filter
feature should be disabled when enabling the promiscuous mode.
Calling em_if_vlan_filter_disable() did the task, but later writing
the value of reg_rctl back to the reg E1000_RCTL may restore the
feature.

Move the calling of em_if_vlan_filter_disable() after writing the reg
to fix that.

PR:             292759
Reviewed by:    kbowling
Tested by:      vova at zote.me
Fixes:          2796f7cab107 e1000: Fix up HW vlan ops
MFC after:      3 days
Differential Revision:  https://reviews.freebsd.org/D54973
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+1-1sys/dev/e1000/if_em.c
+1-11 files

LLVM/project 6b5b5cfllvm/lib/Target/AMDGPU VOP3PInstructions.td AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.fdot2.ll llvm.amdgcn.fdot2.f32.bf16.ll

AMDGPU: Fix src2_modifiers for v_dot2_f32_f16/bf16 on gfx11+
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+44-15llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+20-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+19-4llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+20-0llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+16-0llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+3-2llvm/lib/Target/AMDGPU/VOPInstructions.td
+122-344 files not shown
+131-3410 files

LLVM/project 8228474llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp AMDGPUISelDAGToDAG.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.fdot2.ll llvm.amdgcn.fdot2.f32.bf16.ll

AMDGPU: Improve codegen for VOP2 v_dot2c_f32_f16/bf16

Select VOP2 version when there are no src_modifers, otherwise VOP3.
DeltaFile
+44-116llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+45-13llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+10-24llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+22-0llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+8-2llvm/lib/Target/AMDGPU/VOP2Instructions.td
+8-0llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+137-1553 files not shown
+146-1559 files

LLVM/project 1a75d97llvm/test/CodeGen/AMDGPU llvm.amdgcn.fdot2.ll llvm.amdgcn.fdot2.f32.bf16.ll

AMDGPU: Add more tests for v_dot2_f32_f16/bf16

Test for src modifiers, inline constants and vopd codegen.
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+1,055-44llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+643-116llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+1,698-1602 files

LLVM/project 2edd2eeutils/bazel/llvm-project-overlay/llvm BUILD.bazel

[bazel] Port 9d5a42c8411b22fdcfb80dbbda4d68d6aa957328 (#179218)

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+7-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
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LLVM/project 371b9bdutils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Port 1e33b736ff3888b04206acb9fbd9f6623c0723aa (#179216)

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+36-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+36-01 files

FreeBSD/ports 474404cscience/py-scipy Makefile

science/py-scipy: switch back to cython0 to unbreak the package

PR:             292844
Reported by:    russo
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+2-2science/py-scipy/Makefile
+2-21 files

HardenedBSD/ports 474404cscience/py-scipy Makefile

science/py-scipy: switch back to cython0 to unbreak the package

PR:             292844
Reported by:    russo
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LLVM/project 9dc6b49llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp GCNSchedStrategy.h, llvm/test/CodeGen/AMDGPU sched_mfma_rewrite_copies.mir machine-scheduler-rematerialization-scoring.mir

Re-apply "[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)" (#177206)

This re-applies commit f21e3593371c049380f056a539a1601a843df558 along
with the compile fix failure introduced in
8ab79377740789f6a34fc6f04ee321a39ab73724 before the initial patch was
reverted. It also fixes for the previously observed assert failure.

We were hitting the assert in the HIP Blender due to a combination of
two issues that could happen when rematerializations are being rolled
back.

1. Small changes in slots indices (while preserving instruction order)
compared to the pre-re-scheduling state means that we have to re-compute
live ranges for all register operands of rolled back rematerializations.
This was not being done before.
2. Re-scheduling can move registers that were rematerialized at
arbitrary positions in their respective regions while their opcode is
set to DBG_VALUE, even before their read operands are defined. This
makes re-scheduling reverts mandatory before rolling back

    [3 lines not shown]
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+949-949llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
+519-291llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+523-0llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
+194-194llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
+238-31llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
+210-51llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
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+2,716-1,5999 files