[Clang] Remove clang/test/AST/Bytecode/constexpr.c (#185447)
Remove duplicate test since Sema/constexpr.c handles the constexpr
tests.
Discussed in #181965
[libc][math] correct the output of `asinpif` and `acospi` (#185544)
Currently, we have accuracy issues and some points fail in the asinpif
exhaustive test. This change fixes it by increasing the degree of the
used polynomial
```
-- Testing for FE_TONEAREST in range [0x0, 0x7f800000) --
Failed to match Func(x) against LIBC_NAMESPACE::testing::mpfr::get_mpfr_matcher<Op>( x, Func(x), 0.5, rounding).
Match value not within tolerance value of MPFR result:
Input decimal: 0.00000011348398487598387873731553554534912109375000
Input bits: 0x33F3B47B = (S: 0, E: 0x0067, M: 0x0073B47B)
Match decimal: 0.00000003612307253320068411994725465774536132812500
Match bits: 0x331B25BD = (S: 0, E: 0x0066, M: 0x001B25BD)
MPFR result: 0.00000003612307608591436292044818401336669921875000
MPFR rounded: 0x331B25BE = (S: 0, E: 0x0066, M: 0x001B25BE)
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[Clang][AMDGPU] Change __fp16 to _Float16 in builtin definitions (#185446)
Change the type signature of `SWMMAC, load, cvt` builtins from `__fp16
to _Float16` in the tablegen builtin definitions.
[HLSL][DXIL][SPRIV] Added WaveActiveProduct intrinsic (#184645)
From issue #99165, adds the implementation of WaveActiveProduct. This
time with the new types for SPIRVTypeInst
- [x] Implement WaveActiveProduct clang builtin,
- [x] Link WaveActiveProduct clang builtin with hlsl_intrinsics.h
- [x] Add sema checks for WaveActiveProduct to
CheckHLSLBuiltinFunctionCall in SemaChecking.cpp
- [x] Add codegen for WaveActiveProduct to EmitHLSLBuiltinExpr in
CGBuiltin.cpp
- [x] Add codegen tests to
clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl
- [x] Add sema tests to
clang/test/SemaHLSL/BuiltIns/WaveActiveProduct-errors.hlsl
- [x] Create the int_dx_WaveActiveProduct intrinsic in
IntrinsicsDirectX.td
- [x] Create the DXILOpMapping of int_dx_WaveActiveProduct to 119 in
DXIL.td
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[RISCV] Make Zbc imply Zbkc. (#185543)
Zbkc contains 2 of the 3 instructions from Zbc. Making Zbc imply Zbkc
will make the __riscv_zbkc define be set when Zbc is enabled.
This does not change the diagnostics printed by the assembler.
There's a PR to add this rule to the ISA manual too
https://github.com/riscv/riscv-isa-manual/pull/2524
[SampleProfileMatcher] Flatten profiles loaded on demand (#184255)
Fix an issue that after loading top-level function from profile during
CG matching, it's not flattened. This means the inlined callees of the
loaded nested profile don't get their own entries in
`FlattenedProfiles`, making them undiscoverable by subsequent CG
matching steps.
[SampleProfileMatcher] Add direct basename early matching for orphan functions (#184409)
When user code changes function signatures (e.g., adding/removing
parameters), the C++ mangled name changes while the base function name
stays the same. The existing stale profile CG matching can only recover
renamed functions when they appear as callees of already-matched
callers. If the caller has no profile (e.g., fully inlined in the
profiled binary, or from a different TU not loaded), the renamed callee
is never discovered and gets zero profile data.
Add `matchFunctionsWithoutProfileByBasename()` that pairs orphan IR
functions (no profile) with unused top-level profile functions by
demangled basename, without requiring a matched caller in the call
graph.
This direct basename matching runs before CG matching and writes to
`FuncToProfileNameMap`. CG matching can later overwrite these entries
(since `SymbolMap` is not updated until `UpdateWithSalvagedProfiles`),
so a contextually better CG match is not blocked.
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[FastISel] Lower call instruction with illegal type returned (#180322)
Fix issue https://github.com/llvm/llvm-project/issues/179100
When lowering the call instruction with illegal type returned, we should
bail out and transfer the lowering to DAG. Otherwise the return value is
not promoted to proper type, but DAG would assume it has been promoted.
---------
Co-authored-by: Yuanke Luo <ykluo at birentech.com>
Handle case when an FMV function is declared, used, then defined by:
fixing getMangledNameImpl such that it does not need to special case for FMV declarations because GetOrCreateLLVMFunction already can return the non-mangled name of declared FMV functions
unveil ssh-pkcs11-helper too; fixes breakage spotted by anton@
If SK/P11/askpass is overridden by environment, only unveil the requested
path and not both the requested one and the default.
feedback/ok deraadt@
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
When the Zilsd extension is enabled on RV32, use SD_RV32/LD_RV32
instructions to spill and restore pairs of callee-saved GPRs instead of
saving 2 separate 32 bit data.
Note that we need to ensure stack slot to be aligned.
[AMDGPU] Add structural stall heuristic to scheduling strategies
Implements a structural stall heuristic that considers both resource
hazards and latency constraints when selecting instructions. In coexec,
this changes the pending queue from a binary “not ready to issue”
distinction into part of a unified candidate comparison. Pending
instructions still identify structural stalls in the current cycle, but
they are now evaluated directly against available instructions by stall
cost, making the heuristics both more intuitive and more expressive.
- Add getStructuralStallCycles() to GCNSchedStrategy that computes the
number of cycles an instruction must wait due to:
- Resource conflicts on unbuffered resources (from the SchedModel)
- Sequence-dependent hazards (from GCNHazardRecognizer)
- Add getHazardWaitStates() to GCNHazardRecognizer that returns the number
of wait states until all hazards for an instruction are resolved,
providing cycle-accurate hazard information for scheduling heuristics.
[InferAS][NFC] Improve documentation for getAddrSpaceCastPreservedPtrMask (#185239)
Clarify the description of the preserved pointer bit mask and its
purpose in address space inference. Reformat the example for better
readability.
Co-authored-by: Yuanke Luo <ykluo at birentech.com>
[DA] Fix test case for the Weak Zero SIV tests (NFC) (#185555)
The IR does not match the pseudo code. The pseudo code is intentional,
so update the IR accordingly.
