ixl: Reset VSI statistics after initial sampling
The initial statistics update runs before the PF VSI has obtained its
firmware-assigned statistics counter index. Discard that provisional
VSI baseline so the first update after initialization records the
correct hardware counter.
Without this reset, subtracting a larger provisional value from a newly
selected counter can be mistaken for a 32-bit wrap and report nearly
UINT32_MAX receive drops immediately after boot.
Reported by: Daniel Braniss <danny at cs.huji.ac.il>
Tested by: Daniel Braniss <danny at cs.huji.ac.il>
Obtained from: Intel ixl 1.14.2
MFC after: 2 weeks
Sponsored by: BBOX.io
Differential Revision: https://reviews.freebsd.org/D59336
[LoongArch][MC] Add assembly syntax highlighting for LoongArch (#218946)
This PR adds color highlighting of registers and immediates in LoongArch
disassembly.
This is similar to #65853.
[RISCV] Andes: model fast unaligned accesses (#220756)
Mark the Andes 45 tuning profile as supporting efficient unaligned
scalar loads and stores. This lets fixed-size alignment-one copies lower
to scalar instructions instead of a memcpy call. On these in-order
cores, where performance is almost synonymous with instruction count,
this is a material win.
[AArch64] Form CCMP for CBB and CBH
AArch64ConditionalCompares forms CMP/CCMP chains to transform patterns
such as
Head Head
/ | CmpBB
/ | / |
| CmpBB => / |
| / | Tail |
| / | | |
Tail | | |
| | | |
... ... ... ...
where Head is terminated by a conditional branch and CmpBB contains
a cmp + conditional branch.
We usually try to split any fused conditional branches to be able to
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[AArch64][CMPBR] Fix splitting of CBB/CBH instructions into ext + cmp
We falsely split CBB/CBH instructions by explicitly extending the
second register operand instead of the first one, leading to the
following, wrong codegen:
cbh $wn, $wm, cc, trgt => sxth $wt, $wm
cmp $wn, $wt, cc, sxth
Correct is
cbh $wn, $wm, cc, trgt => sxth $wt, $wn
cmp $wt, $wm, cc, sxth
since cmp with extended register extends it's second, not its first
operand.
[AArch64] Allow forming CCMPs for CB branches
AArch64ConditionalCompares currently doesn't consider FEAT_CMPBR CB
instructions when trying to form CCMPs. This leads to a lot more
branches which is usually hurtful for performance.
The patchs adds handling CB instructions, just like we do for other
fused conditional branches such as CBZ or CBNZ.
[mlir][openacc] Add isCompilerGenerated to GlobalVariableOpInterface (#221096)
This function is used to determine if a global is compiler generated or
coming from user variables. This is useful when determining the handling
of globals for unified memory mode.
[AArch64] Fix missing :lo12: on the catchret address pair (#219200)
`llc -mtriple=aarch64-pc-windows-msvc` emits assembly it cannot assemble
itself.
A function with a `catchret` materialises its continuation block like
this:
```asm
"?catch$2@?0?f at 4HA":
adrp x0, .LBB0_1
add x0, x0, .LBB0_1
ret
```
Pipe that back through `llvm-mc` and you get:
```
error: expected compatible register, symbol or integer in range [0, 4095]
add x0, x0, .LBB0_1
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[clang][OpenMP] Add explicit default libomp value to test. (#221098)
The test OMPInvariantPredicateBoundOnIntraTileLoop, in AttrTest.cpp uses
'-fopenmp' without supplying an explcit value. In some places the
default value is 'libomp', which works just fine for this test. But in
envorinments where 'libomp' is not the default value (e.g. places that
use 'libgomp' by default) the test fails. This fixes that issue by
explicitly telling the test to use 'libomp'.
Compose a new imsg when relaying terminate to vmd(8) control.
Instead of forwarding the imsg, which was already consumed in the
parent vmd process, compose a new one to the control process. When
vmd was refactored to use the new imsg api for consuming the payload
instead of reading directly from the underlying ibuf, it caused
proc_forward_imsg() to forward incomplete data.
Instead of mucking about with the underlying ibuf and rewinding it,
update the only case of the consume-then-forward pattern to compose
a new imsg by using proc_compose_imsg().
Original diff and issue from Nick Owens.
18381 don't log about async event failure on NVMe drive pull
Reviewed by: Andy Fiddaman <illumos at fiddaman.net>
Reviewed by: Hans Rosenfeld <rosenfeld at grumpf.hope-2000.org>
Approved by: Robert Mustacchi <rm at fingolfin.org>
Do not complete a device removal that hit IO errors
spa_vdev_remove_thread() checks vca_read_error_bytes and
vca_write_error_bytes at the end of each metaslab it copies and sets
svr_thread_exit, so that the removal is cancelled instead of completed.
Both counters are incremented from the copy zio callbacks in
spa_vdev_copy_segment_read_done() and
spa_vdev_copy_segment_write_done(), so the errors of the segments
copied last can arrive after that check has already run. The loop then
ends with svr_thread_exit still B_FALSE and the thread calls
vdev_remove_complete(), dropping the vdev even though part of its data
was never written to the new location.
Write errors are the way to hit this. A write error is only known once
the write completes, while a read error is recorded before the write it
feeds is even issued, so read errors are almost always seen in time.
With enough data to copy, the errors of one metaslab are noticed while
the next one is being copied, which is why this mostly goes unnoticed;
it is the errors of the metaslab copied last that are missed.
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[mlir][gpu] Don't request C wrappers for private device functions (#214552)
GPU lowerings attach `llvm.emit_c_interface` to device functions
regardless of visibility. This causes private device functions to
receive external entry points and prevents such functions from being
culled by DCE.
On a real module lowered by a downstream compiler, we measured that
unconditional `llvm.emit_c_interface` inflated the generated PTX by 1.8x
by keeping unused private functions alive and by 7x for pipelines that
also give private functions internal linkage.
This change attaches `llvm.emit_c_interface` only to functions which are
not private for both the gpu->nvvm and gpu->rocdl lowerings. No behavior
change to existing unit tests, and new tests are added to witness the
new behavior for private functions.
Assisted-by: Claude Code
Increasing ZTS timeout as some PRs exceed the limit
Follow up work to better balance the work between the available
CI VMs is being evaluated to speed things up, but for the moment
increase the limit to prevent these timeout failures.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: tiehexue <tiehexue at hotmail.com>
Closes #18997
[DebugInfo] Ignore undefined constexpr constructors in constructor homing. (#218165)
The constructor homing optimization limits the amount of redundant debug
info generated for classes by only emitting forward declarations to
debug info in translation units that can't instantiate the class on
their own (i.e. they don't see the definitions of any constructors).
Currently, classes that have _any_ constexpr constructors are excluded
from the optimization. This is being changed to only exclude _defined_
constexpr constructors, as declared constexpr constructors are not
callable in a TU that doesn't see their definition.
Signed-off-by: Clayton Knittel <cknit1999 at gmail.com>
