LLVM/project 0bde74alld/ELF InputSection.cpp

[ELF] Pass SectionPiece by reference in getSectionPiece. NFC (#190110)

The generated assembly looks more optimized. In addition, this avoids
widened load, which would cause a TSan-detected data race with parallel
--gc-sections (#189321).
DeltaFile
+2-1lld/ELF/InputSection.cpp
+2-11 files

LLVM/project 3346a76llvm/include/llvm/ExecutionEngine/JITLink JITLink.h

[JITLink] Remove unnecessary SymbolStringPtr copy. (#190101)

This was probably intended to be a `const SymbolStringPtr&` originally,
but if we were going to copy it anyway it's better to just take the
argument by value and std::move it.
DeltaFile
+1-1llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
+1-11 files

LLVM/project 9725dc2clang/lib/CIR/Dialect/Transforms TargetLowering.cpp, clang/test/CIR/CodeGen amdgpu-target-lowering-as.cpp

Coverage for AS target lowering and fix generic lowering conversion pattern on alloca types.
DeltaFile
+66-0clang/test/CIR/CodeGen/amdgpu-target-lowering-as.cpp
+14-1clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
+80-12 files

LLVM/project a50308cclang/lib/CIR/CodeGen TargetInfo.cpp, clang/test/CIR/CodeGen amdgpu-address-spaces.cpp

proper amdgpu constant AS encoding
DeltaFile
+3-4clang/lib/CIR/CodeGen/TargetInfo.cpp
+2-2clang/test/CIR/CodeGen/amdgpu-address-spaces.cpp
+5-62 files

LLVM/project ee6b9adclang/lib/CIR/Dialect/Transforms/TargetLowering/Targets AMDGPU.cpp

Use AMDGPU enums to map CIR AS
DeltaFile
+7-6clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
+7-61 files

LLVM/project 5e53353clang/lib/CIR/Dialect/IR CIRDialect.cpp

fix code dup rebase bug
DeltaFile
+0-4clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+0-41 files

LLVM/project 4a919d3clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets AMDGPU.cpp

Add table-based CIR -> Target AS mapping
DeltaFile
+17-18clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
+17-181 files

LLVM/project a0abf04clang/test/CIR/CodeGenCUDA address-spaces.cu

add ogcg cuda checks and todo on nptx lowering
DeltaFile
+11-9clang/test/CIR/CodeGenCUDA/address-spaces.cu
+11-91 files

LLVM/project ae50e89clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

more fmt
DeltaFile
+2-2clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+2-21 files

LLVM/project 035e2e4clang/lib/CIR/CodeGen TargetInfo.cpp CIRGenModule.cpp, clang/test/CIR/CodeGen amdgpu-address-spaces.cpp

fix tests to represent pre-target lowering state of AS
DeltaFile
+0-85clang/test/CIR/Lowering/global-address-space.cir
+15-30clang/lib/CIR/CodeGen/TargetInfo.cpp
+24-2clang/test/CIR/CodeGenCUDA/address-spaces.cu
+14-6clang/test/CIR/CodeGen/amdgpu-address-spaces.cpp
+2-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+55-1265 files

LLVM/project f0a10bdclang/lib/CIR/Dialect/Transforms TargetLowering.cpp

handle formatting
DeltaFile
+38-42clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
+38-421 files

LLVM/project 535be16clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

more fmt yo
DeltaFile
+0-4clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+0-41 files

LLVM/project d42e95eclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

fix fmt
DeltaFile
+4-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+4-01 files

LLVM/project 4ddcd54clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Address Space support for GlobalOps
DeltaFile
+3-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+5-02 files

LLVM/project fdf1b4cclang/lib/CIR/CodeGen TargetInfo.cpp, clang/lib/CIR/Dialect/Transforms TargetLowering.cpp

[CIR][AMDGPU] Lower Language specific address spaces and implement AMDGPU target
DeltaFile
+252-1clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
+48-9clang/test/CIR/Lowering/global-address-space.cir
+51-0clang/test/CIR/CodeGen/amdgpu-address-spaces.cpp
+47-0clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
+46-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+9-2clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
+453-124 files not shown
+470-1810 files

LLVM/project 9fcbf82clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/lib/CIR/Dialect/IR CIRDialect.cpp

Global AS lowering For CUDA and CIRGen tests for target AS
DeltaFile
+0-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+2-32 files

LLVM/project 9a354fcllvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/AMDGPU fneg-modifier-casting.ll

[SelectionDAG] Use `KnownBits` to determine if an operand may be NaN. (#188606)

Given a bitcast into a fp type, use the known bits of the operand to
infer whether the resulting value can never be NaN.
DeltaFile
+67-0llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+19-1llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+2-2llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
+88-33 files

LLVM/project dbc206fclang/include/clang/CIR MissingFeatures.h, clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR][CIRGen] Support for section atttribute on cir.global (#188200)

Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/422

This PR implement support for `__attribute__((section("name")))` on
global variables in ClangIR, matching OGCG behavior.
DeltaFile
+26-13clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+20-4clang/lib/CIR/CodeGen/CIRGenModule.cpp
+18-0clang/test/CIR/CodeGen/global-section.c
+16-0clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
+7-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+1-2clang/include/clang/CIR/MissingFeatures.h
+88-206 files

LLVM/project 53bac5cclang/test/CodeGenHIP incorrect-atomic-scope.hip, clang/test/CodeGenOpenCL incorrect-atomic-scope.cl

move the new tests to Sema
DeltaFile
+35-0clang/test/SemaOpenCL/incorrect-atomic-scope.cl
+0-35clang/test/CodeGenOpenCL/incorrect-atomic-scope.cl
+31-0clang/test/SemaHIP/incorrect-atomic-scope.hip
+0-31clang/test/CodeGenHIP/incorrect-atomic-scope.hip
+66-664 files

DragonFlyBSD/src 4470b57sys/cpu/x86_64/misc x86_64-gdbstub.c

kernel: Fix an off-by-one overflow in the gdb stub.

Fix identical to GDB upstream.
DeltaFile
+1-1sys/cpu/x86_64/misc/x86_64-gdbstub.c
+1-11 files

LLVM/project 06aae40clang/lib/CodeGen CGDebugInfo.cpp, clang/test/CodeGenHLSL/debug source-language.hlsl

[HLSL][SPIRV] Restore support for -g to generate NSDI (#190007)

The original attempt (#187051) produced a regression for
`intel-sycl-gpu` because `SPIRVEmitNonSemanticDI` will now self-activate
whenever `llvm.dbg.cu` is present. This removed the need for the
explicit `--spv-emit-nonsemantic-debug-info` flag.

The pass is now entered unconditionally for all SPIR-V targets, but
`NonSemantic.Shader.DebugInfo.100` requires the
`SPV_KHR_non_semantic_info`. Targets like `spirv64-intel` do not enable
that extension by default. When `checkSatisfiable()` ran on those
targets, it issued a fatal error rather than silently skipping.

Adds an early-out from `emitGlobalDI()`: if
`SPV_KHR_non_semantic_info` is not available for the current target, the
pass returns without emitting anything.
DeltaFile
+34-0clang/test/CodeGenHLSL/debug/source-language.hlsl
+32-0llvm/test/CodeGen/SPIRV/debug-info/hlsl-debug-info-auto-activation.ll
+22-0llvm/test/CodeGen/SPIRV/debug-info/no-nonsemantic-without-extension.ll
+6-5llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+5-3llvm/docs/SPIRVUsage.rst
+6-2clang/lib/CodeGen/CGDebugInfo.cpp
+105-106 files not shown
+119-1512 files

NetBSD/src kRVSWMJsys/arch/m68k/include pmap_motorola.h pmap_68k.h, sys/arch/m68k/m68k m68k_trap.c

   Merge the m68k trap code.  Still a bit more tidying up to do here, but
   this eliminates a significant chunk of code duplication.

   Biggest change here is for Amiga, whose different-from-everyone-else's
   68040 write-back code was voted off the island.
VersionDeltaFile
1.8+623-23sys/arch/m68k/m68k/m68k_trap.c
1.1+125-0sys/arch/sun68k/sun68k/sun68k_trap.c
1.53+7-1sys/arch/m68k/include/pmap_motorola.h
1.12+7-1sys/arch/m68k/include/pmap_68k.h
1.33+7-1sys/arch/sun3/include/pmap3x.h
1.54+3-3sys/arch/sun2/sun2/pmap.c
+772-2930 files not shown
+820-8936 files

LLVM/project 18a0657llvm/lib/Target/RISCV RISCVLoadStoreOptimizer.cpp, llvm/test/CodeGen/RISCV xqcilsm-lwmi-swmi-multiple.mir

[RISCV] Move unpaired instruction back in RISCVLoadStoreOptimizer (#189912)

There are cases when the `Xqcilsm` vendor extension is enabled that we
are unable to pair non-adjacent load/store instructions. The
`RISCVLoadStoreOptimizer` moves the instruction adjacent to the other
before attempting to pair them but does not move them back when it
fails. This can sometimes prevent the generation of the `Xqcilsm`
load/store multiple instructions. This patch ensures that we move the
unpaired instruction back to it's original location.
DeltaFile
+20-1llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi-multiple.mir
+12-3llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+32-42 files

LLVM/project 8c2feeabolt/lib/Target/RISCV RISCVMCPlusBuilder.cpp, bolt/runtime sys_riscv64.h instr.cpp

[BOLT] Delete unnecessary instructions (#189297)
DeltaFile
+64-96bolt/runtime/sys_riscv64.h
+6-12bolt/runtime/instr.cpp
+3-6bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
+73-1143 files

Illumos/gate fc483d5usr/src/uts/common/fs/sockfs socktpi.c, usr/src/uts/common/idmap idmap_cache.c

17966 NCA & NL7S retirements forgot about AF_NCA and residual sockfs debris
Reviewed by: Robert Mustacchi <rm at fingolfin.org>
Reviewed by: Toomas Soome <tsoome at me.com>
Approved by: Gordon Ross <gordon.w.ross at gmail.com>
DeltaFile
+0-16usr/src/uts/intel/sockfs/Makefile
+0-16usr/src/uts/common/fs/sockfs/socktpi.c
+0-3usr/src/uts/common/idmap/idmap_cache.c
+0-353 files

FreeBSD/src db9bbe1lib/libsys procctl.2

procctl.2: Align list indentation

Remove 81 lines of whitespace at default manual rendering width.

MFC after: 3 days
DeltaFile
+24-24lib/libsys/procctl.2
+24-241 files

FreeBSD/ports 4ad6362games Makefile, games/qtads Makefile pkg-plist

games/qtads [New port]: Interpreter for TADS games

QTads is a cross-platform, multimedia interpreter for TADS games.  It is
fully compatible with HTML TADS, aka "Multimedia TADS".  Both TADS
versions in use today (v2 and v3) are supported.

PR:             290244
DeltaFile
+36-0games/qtads/Makefile
+16-0games/qtads/pkg-plist
+10-0games/qtads/pkg-descr
+3-0games/qtads/distinfo
+1-0games/Makefile
+66-05 files

FreeBSD/ports b1e257agames Makefile, games/frobtads pkg-plist Makefile

games/frobtads: [New port] Tools for adventure games

FrobTADS is a full version of TADS.  It includes everything you need for
playing and writing TADS games, including a text-only TADS interpreter
and the compilers for both TADS 2 and 3.

PR:             290209
DeltaFile
+161-0games/frobtads/pkg-plist
+25-0games/frobtads/Makefile
+8-0games/frobtads/pkg-descr
+3-0games/frobtads/distinfo
+1-0games/Makefile
+198-05 files

LLVM/project 495e1a4mlir/lib/Dialect/Math/Transforms SincosFusion.cpp, mlir/test/Dialect/Math sincos-fusion.mlir

[mlir] added a check in the walk to prevent catching a cos in a nested region (#190064)

The walk in SincosFusion may detect a cos within a nested region of the
sin block. This triggers an assertion in `isBeforeInBlock` later on.
Added a check within the walk so it filters operations in nested
regions, which are not in the same block and should not be fused anyway.

---------

Co-authored-by: Yebin Chon <ychon at nvidia.com>
DeltaFile
+23-0mlir/test/Dialect/Math/sincos-fusion.mlir
+2-4mlir/lib/Dialect/Math/Transforms/SincosFusion.cpp
+25-42 files

OpenBSD/ports cRNx5Ngsysutils/u-boot-asahi Makefile

   u-boot-asahi needs C11

   Move to ports-gcc on base-gcc arches to fix build on sparc64
VersionDeltaFile
1.18+4-0sysutils/u-boot-asahi/Makefile
+4-01 files