[LangRef] State that the memory model is an axiomatic one (#208710)
Currently, one could read large parts of the memory model without learning for
sure whether it is meant as an operational model that describes how individual
operations change some notion of state or if it is an axiomatic model (like the
C++ memory model) that lists constraints that a candidate execution must
satisfy to be allowed.
While the description of what a read returns sounds somewhat operational,
aspects like the definition of fence instructions, the monotonic modification
order, and the total order of sequentially consistent operations place it in
the realm of axiomatic models.
This is an attempt to make the nature of the model more explicit (and maybe a
place to discuss the nature of the model), as suggested by RalfJung in the
reviews for #204329.
[AMDGPU] Fix speculative register pressure queries (#208574)
There are two issues with the way we currently speculate register
pressure:
1. GCNDownwardRPTracker::advance(with UseInternalIterator=false), which
is called by the scheduler in schedNode, resets LastTrackedMI, so the
tracker (bumpDownwardPressure) doesn't know where the last scheduled
instruction is and falls back to the beginning of the basic block. As a
result, when we estimate RP impact for a given MI, we tend to find uses
that are often already scheduled and should be skipped.
2. When looking for the remaining uses between LastTrackedMI and the
candidate MI we should skip already scheduled instruction.
[GlobalISel] Fix crash in isConstantOrConstantSplatVectorFP for non-register operands
isConstantOrConstantSplatVectorFP unconditionally accessed operand 0 as
a register, which causes a crash when the instruction is INLINEASM
(whose operand 0 is the asm string, not a register def).
This can happen when matchRepeatedFPDivisor walks the use-def chain of a
G_FDIV operand and reaches an INLINEASM instruction that defines the
dividend.
crush: Update to 0.85.0
Changelog
New!
686a3f4: feat(dialog): hide list info column when it would crowd item names (@taciturnaxolotl)
75e7195: feat(question): add client server integration (@taciturnaxolotl)
6f33b66: feat(question): add mouse scrolling (@taciturnaxolotl)
321c661: feat(question): add mouse support (@taciturnaxolotl)
1b5994c: feat(question): add paste support in text areas (@taciturnaxolotl)
c2a6f76: feat(question): add question tool with structured UI (@taciturnaxolotl)
9f4f145: feat(question): adjust question prompts and error messages (@taciturnaxolotl)
5e611a7: feat(question): allow newlines and make free text like pop (@taciturnaxolotl)
f69a91e: feat(question): extend length limits on question tool (@taciturnaxolotl)
3bf4035: feat(question): make escape cancel the question instead of submitting empty answers (@taciturnaxolotl)
81a8ee4: feat(question): redo tab resizing and mouse -> keyboard transition (@taciturnaxolotl)
a5a5c6c: feat(question): tweak the confirmation tab (@taciturnaxolotl)
29f5691: feat(question): tweak yes/no to add shortcuts (@taciturnaxolotl)
dc16099: feat: elapsed seconds timer (#3223) (@andrinoff)
64bbbeb: feat: integrate fantasy OnAuthRefresh for transparent auth retry (@taciturnaxolotl)
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[LoongArch] Fix invalid VEXTH combines for unsupported type extensions
`performEXTENDCombine` could form `VEXTH`/`VEXTH_U` nodes for unsupported
type combinations, such as extending `v8i8` to `v8i32` or `v2i64` to `v2i128`.
These illegal nodes would later reach instruction selection and trigger
backend failures:
* `Cannot select: LoongArchISD::VEXTH`
* `Don't know how to legalize this operation`
Prevent these combines from firing by verifying that the destination type
is legal and has exactly twice the total bit width of the source before
forming a `VEXTH`/`VEXTH_U` node.
Apply the same checks to `performSHLCombine` for consistency.
[CodeGen] Fine-grained LIS updates on remat and dead-def handling (#202673)
This replaces the rematerializer's manual bulk LIS update paradigm in
favor of an automated fine-grained one that
1. performs LIS updates as rematerializations happen and
2. handles the removal of dead-definitions properly (this replaces the
prior partial handling of live interval splitting).
The new approach should be less error-prone (clients do not have to
periodically update the LIS, which is now up-to-date at all times from
the client's perspective) and faster in general (live intervals aren't
fully re-created every time a def or use of a register changes).
Handling dead-definitions (through a `LiveRangeEditor`) adds some
complexity to the rematerializer since unrematerializable MIs can now
also be deleted. This is exposed to listeners through a new event.
Furthermore, rematerializable registers can now become "permanently
dead" if all their users were unrematerializable MIs that became dead as
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Revert "[MergeFunctions] Preserve instruction-level profile metadata during merging" (#209987)
Reverts llvm/llvm-project#208009
Causes unit test failures.
[AMDGPU] Use v_pk_add_bf16 for scalar bf16 fadd on gfx1250/gfx13 (#209128)
Targets with packed bf16 instructions can do a scalar bf16 fadd with a
single `v_pk_add_bf16` operating on the low half, instead of promoting
to f32 and going through `v_fma_mix_f32_bf16 + v_cvt_pk_bf16_f32`.
