NetBSD/src JBco81cusr.sbin/user user.c

   PR/59415: ssszcmawo: group(8) can rename a group to an existing group name
VersionDeltaFile
1.136+13-9usr.sbin/user/user.c
+13-91 files

OPNSense/core 2346d3dsrc/opnsense/mvc/app/controllers/OPNsense/CaptivePortal/Api AccessController.php

fix: enforce POST-only on captiveportal logoffAction (#9989)
DeltaFile
+22-19src/opnsense/mvc/app/controllers/OPNsense/CaptivePortal/Api/AccessController.php
+22-191 files

FreeBSD/doc ed075dcwebsite/content/en/releng _index.adoc

14.4: Hand off to so@

The release engineering team is done with releng/14.4.

Approved by:    re (implicit)
DeltaFile
+1-1website/content/en/releng/_index.adoc
+1-11 files

FreeBSD/ports 6fec3f4math/mpfi distinfo Makefile

math/mpfi: make fetchable again with a silent update

MASTER_SITES moved to ENS Lyon.

Meanwhile the tarball has been rerolled:
- many auto* stuff: configure is now pre-generated;
- mpfi.pc is available
- change tests

but also some code has been modified.

Full diff available at https://people.freebsd.org/~thierry/mpfi-1.5.4.diff

PR:             293803
Reported by:    Daniel Engberg
DeltaFile
+3-3math/mpfi/distinfo
+3-2math/mpfi/Makefile
+0-2math/mpfi/pkg-descr
+1-0math/mpfi/pkg-plist
+7-74 files

FreeBSD/ports 9105908math/sprng pkg-plist distinfo, math/sprng/files patch-TESTS_mpitests_wolff.cpp patch-TESTS_wolfftest.cpp

math/sprng: make fetchable again with a silent update

The tarball for SPRNG 5.0 has been rerolled.
This includes several minor points:
- format change (dos to unix);
- code reformat and linting;
- code cleaning;

but also some other modifications.

Full diff available at https://people.freebsd.org/~thierry/sprng5.diff .

PR:             293802
Reported by:    Daniel Engberg
DeltaFile
+28-28math/sprng/files/patch-TESTS_mpitests_wolff.cpp
+28-28math/sprng/files/patch-TESTS_wolfftest.cpp
+28-28math/sprng/files/patch-TESTS_wolff.cpp
+13-17math/sprng/files/patch-SRC_pmlcg_pmlcg.cpp
+0-24math/sprng/pkg-plist
+3-3math/sprng/distinfo
+100-1282 files not shown
+103-1328 files

FreeBSD/ports 997c9bascience/medit Makefile

science/medit: make fetchable again

Université Pierre et Marie Curie merged with Sorbonne University, and
upstream site has been reorganized.

PR:             293800
Reported by:    Daniel Engberg
DeltaFile
+4-3science/medit/Makefile
+4-31 files

FreeBSD/ports e451e6atextproc/libtextcat Makefile

textproc/libtextcat: deprecate

Upstream disapeared, and LibreOffice adopted and adapted this program.
It has been renamed as libexttextcat, and can be replaced by the port
textproc/libexttextcat.

PR:             293799
Reported by:    Daniel Engberg
DeltaFile
+3-0textproc/libtextcat/Makefile
+3-01 files

LLVM/project 19fd930flang/lib/Lower/Support PrivateReductionUtils.cpp, flang/test/Lower/OpenMP delayed-privatization-cuda-device-array.cuf

[flang][OpenMP][CUDA] Set allocator_idx on privatized allocatable device array descriptors (#186945)

When an allocatable CUDA Fortran device array is privatized in an OpenMP
region, the null descriptor created in the omp.private init region was
missing the allocator_idx attribute. This caused a subsequent allocate()
inside the parallel region to call malloc instead of cudaMalloc, because
the runtime's Descriptor::Allocate() reads allocator_idx from the
descriptor to select the allocator. On some systems it caused
cudaErrorInvalidValue crashes.

This patch sets allocator_idx = 2 (device allocator) on the null
fir.embox in handleNullAllocatable() when the symbol has a CUDA device
attribute, so that the Fortran runtime correctly calls cudaMalloc for
the privatized array.
DeltaFile
+24-0flang/test/Lower/OpenMP/delayed-privatization-cuda-device-array.cuf
+8-3flang/lib/Lower/Support/PrivateReductionUtils.cpp
+32-32 files

NetBSD/src RTpuqb6sbin/cgdconfig cgdconfig.c

   PR/60086: Andrew Parker: cgdconfig may not always find ZFS device labels
   Updated cgdconfig to use the same alignment function as zdb
   (external/cddl/osnet/dist/cmd/zdb/zdb.c).
VersionDeltaFile
1.64+3-2sbin/cgdconfig/cgdconfig.c
+3-21 files

LLVM/project a4e2d20llvm/lib/Target/AArch64 AArch64InstrFormats.td, llvm/test/MC/Disassembler/AArch64 reserved-bits-softfail.txt

[AArch64][llm] Make SBZ/SBO insns warn not fail when disassembling

Some instructions in the Arm ARM have bits which are marked as "Should
Be One" or "Should Be Zero", and they're marked as "Constrained
Unpredictable" as to what should happen if they're not.

This is to improve hardware decode efficiency. In all the cases where
this occurs, it's an instruction which in all other respects is closely
related to an adjacent instruction in the encoding space (for example a
similar load or store) but doesn't require one of the variable fields,
usually a register field. These fields are then defined as SBZ or SBO.

If one of these instructions didn't have the bits set to SBZ or SBO,
then the instruction would fail to disassemble. We had missed adding
`Unpredictable` to a few of these, and they would fail rather than
warn.

Update these AArch64 instructions to treat `Unpredictable` bitfields as
soft-fails with a warning, and add a comprehensive disassembler regression

    [9 lines not shown]
DeltaFile
+559-0llvm/test/MC/Disassembler/AArch64/reserved-bits-softfail.txt
+6-0llvm/lib/Target/AArch64/AArch64InstrFormats.td
+565-02 files

LLVM/project b686f5ellvm/lib/Transforms/Vectorize/SandboxVectorizer Legality.cpp, llvm/test/Transforms/SandboxVectorizer bottomup_basic.ll

[SandboxVec][BottomUpVec] Fix crash caused by Cmps with different operand types (#186550)

This patch disables vectorizing Cmps with different operand types
because we can't form a legal vector.
This used to cause an assertion check crash once we attempted to pack
the bundle formed by Cmp's operands.
DeltaFile
+47-0llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
+6-3llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
+53-32 files

LLVM/project 9d94bdamlir/lib/Interfaces ControlFlowInterfaces.cpp

[mlir][Interfaces][NFC] Add early exit to MakeRegionBranchOpSuccessorInputsDead (#186325)

Optimize MakeRegionBranchOpSuccessorInputsDead patterns in
`ControlFlowInterfaces.cpp`:

- Add early exit to `computeReachableValuesFromSuccessorInput` when the
caller only needs to know if there is exactly one reachable value,
avoiding unnecessary traversal.

Assisted-by: Claude Code

Co-authored-by: Yang Bai <yangb at nvidia.com>
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
DeltaFile
+23-12mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+23-121 files

LLVM/project 333f6ab.ci all_requirements.txt, mlir/python requirements.txt

Reland Support float8_e3m4 and float8_e4m3 in np_to_memref (#186453) (#186833)

This patch adds support for `float8_e3m4` and `float8_e4m3` in
`np_to_memref.py` by adding the appropriate ctypes structures.
Additionally changes minimum numpy version to 2.1.0 and uses a single
ml_dtypes version of 0.5.0.
DeltaFile
+55-47.ci/all_requirements.txt
+85-1mlir/test/python/execution_engine.py
+24-5mlir/python/mlir/runtime/np_to_memref.py
+2-3mlir/python/requirements.txt
+166-564 files

FreeBSD/src 14e9744sys/arm64/arm64 trap.c

arm64: Have a common call to userret

Rather than each exception calling userret use a common copy. As
syscallret already calls userret we need to skip it in that case.

Reviewed by:    kib
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D55250
DeltaFile
+9-21sys/arm64/arm64/trap.c
+9-211 files

LLVM/project 1800651flang/lib/Optimizer/Builder IntrinsicCall.cpp, flang/test/Lower/Intrinsics anint.f90

[flang] Lower anint with math.round (#186039)

Use `math.round` in lowering of `anint` so we can use passes like
`MathToNVVM` to target device code differently.
DeltaFile
+6-6flang/test/Lower/math-lowering/anint.f90
+3-3flang/lib/Optimizer/Builder/IntrinsicCall.cpp
+3-3flang/test/Lower/Intrinsics/anint.f90
+12-123 files

LLVM/project 3c39166lldb/source/Interpreter CommandInterpreter.cpp

[lldb] Fix user-after-free in CommandInterpreter (#187032)

The variable `matches` may be assigned the address of block-scope
`local_matches`, which is defined in a scope strictly smaller than the
scope of `matches`. Towards the end of the function, after
`loacl_matches` has been destroyed, `matches` is accessed, possibly
triggering a user-after-free.
DeltaFile
+2-1lldb/source/Interpreter/CommandInterpreter.cpp
+2-11 files

LLVM/project 9c7e203flang/docs Directives.md, flang/lib/Lower ConvertCall.cpp

[flang] Fix ignore_tkr(c) passing descriptor instead of base address for non-descriptor dummies (#186894)

When ignore_tkr(c) is set and the actual argument is an allocatable or
pointer (stored as a descriptor), the lowering code was unconditionally
returning the descriptor pointer as-is, regardless of whether the dummy
argument expects a descriptor. For bind(c) interfaces with assumed-size
dummies (e.g., cuFFT), the dummy expects a raw pointer, not a
descriptor. Passing the descriptor caused the C function to receive the
wrong address, leading to silent data corruption and invalid descriptor
crashes at deallocation.

The fix adds a check that the early return for ignore_tkr(c) only
applies when the dummy type is itself a descriptor type. When the dummy
expects a base address, the normal path is taken, which correctly
extracts the base address from the descriptor via fir.box_addr.
DeltaFile
+40-0flang/test/Lower/HLFIR/ignore-tkr-c-base-addr.f90
+11-8flang/docs/Directives.md
+1-1flang/lib/Lower/ConvertCall.cpp
+52-93 files

LLVM/project 79d1a2cllvm/lib/Target/AMDGPU AMDGPUMCInstLower.h AMDGPULegalizerInfo.cpp

[AMDGPU] Standardize on using AMDGPU::getNullPointerValue. NFC. (#187037)

AMDGPUTargetMachine also had a static method which did the same thing.
Remove it so that we have a single source of truth.
DeltaFile
+4-8llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h
+5-4llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+0-8llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+3-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-4llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+0-3llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+13-305 files not shown
+18-3511 files

OpenBSD/src GkbO8nOshare/mk bsd.lib.mk

   rework the way we reconsturct the object file order for syspatches

   this change drops the exclude regex and just simply checks if the
   object files are actually available and then constucts a response
   file which we pass for linking and this seems to be good enough
   to have reproducible make build output (which is what we want here)

   ok tb@
VersionDeltaFile
1.106+9-12share/mk/bsd.lib.mk
+9-121 files

LLVM/project adf458clldb/packages/Python/lldbsuite/test lldbutil.py

[lldb] Add additional logging to wait_for_file_on_target (#186915)

Occasionally wait_for_file_on_target will time out on the Green Dragon
bots and we're not sure why. I'm adding this logging in an attempt to
get more clues as to what's happening when it fails.
DeltaFile
+8-1lldb/packages/Python/lldbsuite/test/lldbutil.py
+8-11 files

LLVM/project 10653adclang/test/CodeGenHIP builtins-amdgcn-buffer-format.hip, clang/test/CodeGenOpenCL builtins-amdgcn-raw-buffer-store-format.cl builtins-amdgcn-raw-buffer-load-format.cl

[Clang][AMDGPU] Add clang builtins for buffer format load/store intrinsics
DeltaFile
+208-0clang/test/CodeGenHIP/builtins-amdgcn-buffer-format.hip
+46-0clang/test/SemaHIP/builtins-amdgcn-buffer-format.hip
+44-0clang/test/CodeGenOpenCL/builtins-amdgcn-raw-buffer-store-format.cl
+44-0clang/test/CodeGenOpenCL/builtins-amdgcn-raw-buffer-load-format.cl
+35-0clang/test/CodeGenOpenCL/builtins-amdgcn-struct-buffer-store-format.cl
+35-0clang/test/CodeGenOpenCL/builtins-amdgcn-struct-buffer-load-format.cl
+412-04 files not shown
+497-010 files

FreeBSD/ports fdd1de0misc/py-misaki Makefile

misc/py-misaki: Correct maintainer field
DeltaFile
+1-1misc/py-misaki/Makefile
+1-11 files

FreeBSD/ports 045ff0dmisc/py-kokoro Makefile

misc/py-kokoro: Correct maintainer field
DeltaFile
+1-1misc/py-kokoro/Makefile
+1-11 files

LLVM/project 810ba55llvm/include/llvm/IR CycleInfo.h, llvm/include/llvm/Transforms/Utils BasicBlockUtils.h ControlFlowUtils.h

[CycleInfo] Support forward declarations (#187029)

Use a class instead of an alias, so that CycleInfo can be
forward-declared.

We can't do the same for Cycle without further changes (a LoopInfo like
CRTP scheme).
DeltaFile
+3-1llvm/include/llvm/IR/CycleInfo.h
+1-1llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
+0-1llvm/include/llvm/Transforms/Utils/ControlFlowUtils.h
+1-0llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+5-34 files

LLVM/project 832c959llvm/lib/Target/AArch64 AArch64ConditionOptimizer.cpp AArch64.h, llvm/test/CodeGen/AArch64 aarch64-condopt-cross-block-different-regs.mir aarch64-condopt-nzcvdef.mir

[NewPM] Port for AArch64ConditionOptimizer (#186941)

Adds a newPM pass for AArch64ConditionOptimizer.

- Refactors base logic into an Impl class
- Renames old pass with the "Legacy" suffix
- Adds the new pass manager pass using refactored logic
- Updates tests

Context and motivation in
https://llvm.org/docs/NewPassManager.html#status-of-the-new-and-legacy-pass-managers
DeltaFile
+65-35llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+9-2llvm/lib/Target/AArch64/AArch64.h
+2-2llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+1-0llvm/lib/Target/AArch64/AArch64PassRegistry.def
+1-0llvm/test/CodeGen/AArch64/aarch64-condopt-cross-block-different-regs.mir
+1-0llvm/test/CodeGen/AArch64/aarch64-condopt-nzcvdef.mir
+79-391 files not shown
+80-397 files

LLVM/project b04b9e5llvm/utils/gn/secondary/llvm/include/llvm/Config BUILD.gn

[gn] port 55b271ddc1fd968
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
+1-01 files

LLVM/project 6f68daallvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/InstCombine sext-nonneg-sub.ll

[InstCombine] Recognize non-negative subtraction patterns (#182597)

Alive2 proofs:
smin pattern: https://alive2.llvm.org/ce/z/-E2Tpc
DeltaFile
+63-0llvm/test/Transforms/InstCombine/sext-nonneg-sub.ll
+3-2llvm/lib/Analysis/ValueTracking.cpp
+66-22 files

LLVM/project 19c04cellvm/lib/Target/X86 X86ISelLowering.cpp X86ISelLowering.h, llvm/test/CodeGen/X86 sse-minmax-finite.ll avx512-broadcast-unfold.ll

[X86] Fix fcmp+select to min/max lowering (#185594)

This does a few changes that are hard to separate from each other:
* Consider forming minnum/maxnum from setcc+select non-profitable. X86
  has instructions specifically for the setcc+select pattern. (Without
  this it's hard to get good coverage on this code path.)
* Reduce duplication in the code for forming FMIN/FMAX, by using
  predicate inversion (to make setcc and select operand order match) and
  predicate invswap (to canonicalize to ordered predicates). This leaves
  us with just ordered and NaN-less predicates.
* For non-strict non-less predicates, convert them to strict ones via
  invswap (i.e. swapping the operands of both the setcc and select).
  Previously this just treated them the same as strict predicates, but I
  believe that's incorrect in terms of signed zero handling.
DeltaFile
+49-126llvm/lib/Target/X86/X86ISelLowering.cpp
+60-60llvm/test/CodeGen/X86/sse-minmax-finite.ll
+24-36llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
+17-5llvm/test/CodeGen/X86/sse-minmax.ll
+8-8llvm/test/CodeGen/X86/avx-minmax.ll
+6-0llvm/lib/Target/X86/X86ISelLowering.h
+164-2356 files

FreeNAS/freenas 2c9d5b6src/middlewared/middlewared/plugins/truenas_connect hostname.py, src/middlewared/middlewared/pytest/unit/plugins test_truenas_connect.py

Address reviews
DeltaFile
+36-24src/middlewared/middlewared/plugins/truenas_connect/hostname.py
+18-6src/middlewared/middlewared/pytest/unit/plugins/test_truenas_connect.py
+54-302 files

LLVM/project cb3e9eeclang/include/clang/AST TypeBase.h TypeProperties.td, clang/lib/AST ASTContext.cpp Type.cpp

[clang] DeducedTypes deduction kind fix and improvement (#186727)

This is a small refactor of how DeducedType and it's derived types are
represented.

The different deduction kinds are spelled out in an enum, and how this
is tracked is simplified, to allow easier profiling.

How these types are constructed and canonicalized is also brought more
in line with how it works for the other types.

This fixes a crash reported here:
https://github.com/llvm/llvm-project/issues/167513#issuecomment-3692962115
DeltaFile
+82-91clang/lib/AST/ASTContext.cpp
+81-38clang/include/clang/AST/TypeBase.h
+48-20clang/lib/AST/Type.cpp
+14-16clang/lib/Sema/TreeTransform.h
+9-18clang/include/clang/AST/TypeProperties.td
+20-4clang/lib/AST/TextNodeDumper.cpp
+254-18714 files not shown
+320-23920 files