FreeBSD/ports 2310409sysutils/bin distinfo Makefile

sysutils/bin: Update to 0.25.5

ChangeLog: https://github.com/marcosnils/bin/releases/tag/v0.25.5
DeltaFile
+5-5sysutils/bin/distinfo
+2-2sysutils/bin/Makefile
+7-72 files

LLVM/project 2a09db4llvm/lib/Target/AMDGPU SIWholeQuadMode.cpp, llvm/test/CodeGen/AMDGPU wqm-propagate-for-execz-side-effect.mir

AMDGPU: Back-propagate wqm for sources of side-effect instruction (#193395)

For readfirstlane instruction, as it would get undefined value if exec
is zero. To handle the case that only helper lanes execute the parent
block, we let the readfirstlane to execute under wqm. But this is not
enough. If the parent block was also executed by non-helper lanes, we
also need to make sure its sources were calculated under wqm. Otherwise,
if the instruction that generate the source of readfirstlane was
executed under exact mode, the value would contain garbage data in help
lane. The garbage data in helper lane maybe returned by the
readfirstlane running under wqm.

To fix this issue, we need to enforce the back-propagation of wqm for
instructions like readfirstlane. This was only done if the instruction
was possibly in the middle of wqm region (by checking OutNeeds).
DeltaFile
+35-4llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+1-1llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
+36-52 files

LLVM/project 4bf5bcbllvm/unittests/ADT StableHashingTest.cpp CMakeLists.txt

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+44-0llvm/unittests/ADT/StableHashingTest.cpp
+1-0llvm/unittests/ADT/CMakeLists.txt
+45-02 files

LLVM/project 75f6489llvm/test/CodeGen/RISCV/rvv fixed-vectors-vmacc-vp.ll fixed-vectors-vnmsac-vp.ll

rebase

Created using spr 1.3.7
DeltaFile
+438-234llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
+438-234llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
+241-326llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
+201-265llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
+175-179llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
+141-166llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
+1,634-1,40428 files not shown
+2,855-2,13734 files

LLVM/project 9cbf724llvm/lib/TargetParser TargetDataLayout.cpp

clang-format

Created using spr 1.3.8-beta.1
DeltaFile
+2-1llvm/lib/TargetParser/TargetDataLayout.cpp
+2-11 files

LLVM/project 04031a9llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

only look at ABI

Created using spr 1.3.8-beta.1
DeltaFile
+160,853-171,875llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+54,567-55,132llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+92,827-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+31,320-33,737llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+759,347-260,74429,181 files not shown
+4,174,883-1,618,10929,187 files

LLVM/project 2d9efd2llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+160,853-171,875llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+54,567-55,132llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+92,827-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+31,320-33,737llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+759,347-260,74429,180 files not shown
+4,174,851-1,618,08029,186 files

LLVM/project 41236fbllvm/lib/Transforms/Scalar GVN.cpp, llvm/test/Transforms/GVN tbaa.ll

[GVN] Propagate isMemorySSAEnabled() into ValueTable (#193938)

`GVNPass::runImpl()` calls `VN.setMemorySSA(MSSA)` with a single
argument. The second parameter of `ValueTable::setMemorySSA()`,
`MSSAEnabled`, defaults to `false`, so `ValueTable::IsMSSAEnabled`
remains false even when the pass is configured with
`-enable-gvn-memoryssa=1` or `-passes='gvn<memoryssa>'`.

The MemorySSA-backed value-numbering paths in
`ValueTable::lookupOrAddCall()` and `ValueTable::computeLoadStoreVN()`
are gated on `IsMSSAEnabled`, making them unreachable from runImpl() on
main today.

This patch forwards isMemorySSAEnabled() as the second argument to
setMemorySSA(), so selecting the MemorySSA backend actually enables
MemorySSA-aware value numbering.
DeltaFile
+36-90llvm/test/Transforms/GVN/tbaa.ll
+4-1llvm/lib/Transforms/Scalar/GVN.cpp
+40-912 files

NetBSD/pkgsrc-wip 8b013f0prusaslicer TODO

prusaslicer: Update TODO to reference wxGTK32 patch

Drop math/cgal patch, which has been committed.
DeltaFile
+14-2prusaslicer/TODO
+14-21 files

FreeBSD/ports 294be7asecurity/openssh-portable/files extra-patch-no-blocklistd-hpn-glue

security/openssh-portable: Fix blacklistd/HPN glue patch.

Reported by:    leres
Fixes: 899a7de9a078
DeltaFile
+12-12security/openssh-portable/files/extra-patch-no-blocklistd-hpn-glue
+12-121 files

LLVM/project 87e285c. pyproject.toml

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+10-0pyproject.toml
+10-01 files

LLVM/project ab6582bclang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded vfncvtbf16.c, llvm/test/CodeGen/RISCV/rvv setcc-int-vp.ll

update switch

Created using spr 1.3.8-beta.1
DeltaFile
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+704-882llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+980-230mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
+1,024-0llvm/test/Transforms/LoopUnroll/debug-and-remarks.ll
+0-987mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+472-472clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
+6,410-3,027759 files not shown
+31,136-15,914765 files

LLVM/project 161e56bclang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded vfncvtbf16.c, llvm/test/CodeGen/RISCV/rvv setcc-int-vp.ll fixed-vectors-setcc-int-vp.ll

Merge branch 'main' into users/ylzsx/v2f32-load-legalize
DeltaFile
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+704-882llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+980-230mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
+0-987mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+472-472clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
+345-558llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
+5,731-3,585576 files not shown
+25,323-14,291582 files

FreeBSD/ports b7c9c5dsysutils Makefile, sysutils/nvtop Makefile pkg-descr

sysutils/nvtop: New port: GPU & Accelerator process monitoring

NVTOP stands for Neat Videocard TOP, a (h)top like task monitor for GPUs
and accelerators. It can handle multiple GPUs and print information
about them in a htop-familiar way.

Currently supported vendors are AMD (Linux amdgpu driver), Apple
(limited M1 & M2 support), Huawei (Ascend), Intel (Linux i915/Xe
drivers), NVIDIA (Linux proprietary divers), Qualcomm Adreno (Linux MSM
driver), Broadcom VideoCore (Linux v3d driver), Rockchip, MetaX (MXSML
driver), Enflame (Linux EFML driver).

PR:             294825
Sponsored by:   UNIS Labs
DeltaFile
+19-0sysutils/nvtop/Makefile
+9-0sysutils/nvtop/pkg-descr
+5-0sysutils/nvtop/pkg-plist
+3-0sysutils/nvtop/distinfo
+1-0sysutils/Makefile
+37-05 files

LLVM/project db57208llvm/test/CodeGen/X86 machine-block-hash.mir

[X86] Mark machine-block-hash.mir as XFAIL on big-endian hosts (#194279)

Test introduced in #193107 assumes `stable_hash_combine` is stable,
but it turns out it's not true.
DeltaFile
+3-0llvm/test/CodeGen/X86/machine-block-hash.mir
+3-01 files

FreeBSD/ports 93c3712print/pdf-tools Makefile

print/pdf-tools: Add pkgconf build dependency and fix configure env

The recent import of pkgconf into the FreeBSD base system temporarily
caused a print/pdf-tools build failure and exposed two issues with the
port.  First, pkgconf should be a direct build dependency.  Second,
${CONFIGURE_ENV} should be passed to ./configure so that
PKG_CONFIG_LIBDIR is set correctly regardless of the pkgconf
implementation in the environment.

Sponsored by:   The FreeBSD Foundation
DeltaFile
+5-3print/pdf-tools/Makefile
+5-31 files

FreeBSD/src 912f9dfsys/amd64/ia32 ia32_syscall.c

amd64: ia32_fetch_syscall_args() does not need to check params != NULL

Whatever params pointer is, it does not matter.  copyin() handles any
values.  In fact, params cannot be ever NULL.

Reviewed by:    markj
Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Differential revision:  https://reviews.freebsd.org/D56630
DeltaFile
+1-1sys/amd64/ia32/ia32_syscall.c
+1-11 files

FreeBSD/src bd8edbasys/amd64/ia32 ia32_syscall.c

amd64 ia32_syscall(): only allow for ILP32 processes

64bit processes can issue INT $0x80 instruction, and get the syscall
dispatched through ia32_syscall().  This works because syscall argument
fetch and result return are selected from the process sysent.

But, ia32_syscall() does not verify some conditions and does not perform
some actions which are considered unnecessary because the caller is
supposed to only access lower 4G.  The INT syscall path breaks this
assumption.

We never supported such hack, so disable it.  Send the offending thread
SIGBUS as if #GP was issued by hardware due to IDT vector 0x80 having
not numerically high enough DPL value.

Reviewed by:    markj
Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Differential revision:  https://reviews.freebsd.org/D56630
DeltaFile
+9-0sys/amd64/ia32/ia32_syscall.c
+9-01 files

LLVM/project e042f67llvm/lib/Target/LoongArch LoongArchInstrInfo.cpp LoongArchInstrInfo.h, llvm/test/CodeGen/LoongArch stackslot.mir

[LoongArch] Override `isLoadFromStackSlot/isStoreToStackSlot` to expose more optimizations (#164561)
DeltaFile
+245-0llvm/test/CodeGen/LoongArch/stackslot.mir
+76-0llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+9-0llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
+330-03 files

FreeBSD/ports 1091ed9mail/mutt distinfo Makefile

mail/mutt: Update 2.3.1 => 2.3.2

Release Notes:
https://marc.info/?l=mutt-users&m=177718131918193&w=2

PR:             294821
Sponsored by:   UNIS Labs
MFH:            2026Q2

(cherry picked from commit 9cf55329fbe5185795c2706cc52afe76ce549d2a)
DeltaFile
+3-3mail/mutt/distinfo
+1-1mail/mutt/Makefile
+4-42 files

FreeBSD/ports 9cf5532mail/mutt distinfo Makefile

mail/mutt: Update 2.3.1 => 2.3.2

Release Notes:
https://marc.info/?l=mutt-users&m=177718131918193&w=2

PR:             294821
Sponsored by:   UNIS Labs
MFH:            2026Q2
DeltaFile
+3-3mail/mutt/distinfo
+1-1mail/mutt/Makefile
+4-42 files

FreeBSD/ports 4eb1378net-mgmt/andwatch distinfo Makefile

net-mgmt/andwatch: Update 2.2.0 => 2.3.0

Changelog:
https://github.com/dennypage/andwatch/releases/tag/v2.3.0

PR:             294818
Sponsored by:   UNIS Labs
DeltaFile
+3-3net-mgmt/andwatch/distinfo
+1-1net-mgmt/andwatch/Makefile
+4-42 files

LLVM/project 0d704c3llvm/test/CodeGen/X86 machine-block-hash.mir

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+3-0llvm/test/CodeGen/X86/machine-block-hash.mir
+3-01 files

LLVM/project a881a30llvm/lib/Target/AMDGPU SIWholeQuadMode.cpp

Apply suggestion from @ruiling
DeltaFile
+0-1llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+0-11 files

LLVM/project 37ac1efllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-fp-setcc.ll fixed-vectors-setcc-fp-vp.ll

Merge branch 'main' into users/ruiling/wqm-prop-sideeffect
DeltaFile
+4,811-4,818llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+1,872-1,883llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+565-2,727llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,117-1,613llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+11,921-16,1233,545 files not shown
+154,376-91,2463,551 files

LLVM/project ef09defllvm/test/CodeGen/AMDGPU wqm-propagate-for-execz-side-effect.mir

[test][AMDGPU] Precommit test for Back-propagate wqm for sources of side-effect instruction (#193394)
DeltaFile
+238-0llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
+238-01 files

LLVM/project b111f60llvm/test/CodeGen/X86 machine-block-hash.mir

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+0-1llvm/test/CodeGen/X86/machine-block-hash.mir
+0-11 files

FreeBSD/ports 899a7desecurity/openssh-portable distinfo Makefile, security/openssh-portable/files extra-patch-blacklistd patch-session.c

security/openssh-portable: Update to 10.3p1

Release notes: https://www.openssh.org/txt/release-10.3
DeltaFile
+33-22security/openssh-portable/files/extra-patch-blacklistd
+14-13security/openssh-portable/files/patch-session.c
+12-14security/openssh-portable/files/extra-patch-hpn
+5-5security/openssh-portable/distinfo
+4-4security/openssh-portable/Makefile
+0-8security/openssh-portable/files/patch-servconf.c
+68-661 files not shown
+71-707 files

FreeBSD/ports 8dc56cbsecurity/openssh-portable Makefile

security/openssh-portable: Fix `make test`

No changes here affect the build or package.
DeltaFile
+30-6security/openssh-portable/Makefile
+30-61 files

LLVM/project 3114d30llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-fp-setcc.ll fixed-vectors-setcc-fp-vp.ll

Merge branch 'main' into users/ruiling/add-wqm-test
DeltaFile
+4,811-4,818llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+1,872-1,883llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+565-2,727llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,117-1,613llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+11,921-16,1233,545 files not shown
+154,376-91,2463,551 files