OPNSense/plugins c4758d3 — net/upnp Makefile

by Franco Fichtner on ⎇
net/upnp: mark this release as development
DeltaFile
+1-1net/upnp/Makefile
+1-11 files

FreeBSD/ports 82ba594 — devel/aws-c-http distinfo Makefile

by Nuno Teixeira (eduardo) on ⎇
devel/aws-c-http: Update to 0.10.11

ChangeLog: https://github.com/awslabs/aws-c-http/releases/tag/v0.10.11
DeltaFile
+3-3devel/aws-c-http/distinfo
+1-1devel/aws-c-http/Makefile
+4-42 files

FreeBSD/ports 4efcf88 — x11/showmethekey distinfo Makefile

by Nuno Teixeira (eduardo) on ⎇
x11/showmethekey: Update to 1.21.0

ChangeLog: https://github.com/AlynxZhou/showmethekey/releases/tag/v1.21.0
DeltaFile
+3-3x11/showmethekey/distinfo
+1-1x11/showmethekey/Makefile
+4-42 files

FreeBSD/ports 4f6646c — security/s2n-tls distinfo Makefile

by Nuno Teixeira (eduardo) on ⎇
security/s2n-tls: Update to 1.7.1

ChangeLog: https://github.com/aws/s2n-tls/releases/tag/1.7.1
DeltaFile
+3-3security/s2n-tls/distinfo
+1-2security/s2n-tls/Makefile
+4-52 files

LLVM/project 7036495 — llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/X86 known-never-zero.ll

by Shekhar via GitHub on ⎇
[DAG] isKnownNeverZero - add ISD::OR DemandedElts handling (#183228)

This patch updates `SelectionDAG::isKnownNeverZero` to support `ISD::OR`
by forwarding the `DemandedElts` mask to its operands.

Previously, `ISD::OR` dropped the mask, causing the compiler to be
overly conservative if any lane in the vector was zero, even if that
lane wasn't demanded. This change allows the compiler to prove a vector
result is non-zero even if ignored lanes are zero.

Fixes #183037

**Tests:**

- Moved tests from the C++ file to the IR assembly file
(`known-never-zero.ll`) as requested.
- Confirmed the code now correctly tracks which parts of a vector are
actually needed for `ISD::OR`.
- This allows the compiler to prove a result is "never zero" even if
some unused lanes contain zeros.
DeltaFile
+9-18llvm/test/CodeGen/X86/known-never-zero.ll
+2-2llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+11-202 files

LLVM/project d908184 — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64-neon-select_cc.ll

by David Green via GitHub on ⎇
[AArch64] Limit support to f32 and f64 in performSelectCombine (#184315)

This prevents a crash with fp128 types, other types (f16) were already
excluded.

Fixes #184300
DeltaFile
+36-0llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+37-12 files

LLVM/project ec7f350 — mlir/test/Interfaces/LoopLikeInterface test-block-loop.mlir, mlir/test/lib/Interfaces/LoopLikeInterface TestBlockInLoop.cpp

by sweiglbosker via GitHub on ⎇
[MLIR] Make test-block-is-in-loop pass a module pass (#184036)

This pass can't run in parallel on function as it would trigger race conditions.

Fixes #183999
DeltaFile
+13-11mlir/test/lib/Interfaces/LoopLikeInterface/TestBlockInLoop.cpp
+1-1mlir/test/Interfaces/LoopLikeInterface/test-block-loop.mlir
+14-122 files

OPNSense/core 6233c15 — src/opnsense/mvc/app/views/OPNsense/Firewall dnat_rule.volt

by Stephan de Wit via Franco Fichtner on ⎇
Firewall: NAT: Destination NAT: do the same here as https://github.com/opnsense/core/commit/4bc542cc7fad2ccd11e08bcd7bd2266f2accefd1

(cherry picked from commit 196334c63b3dcf062016f39d8ad1692f49d42320)
DeltaFile
+5-0src/opnsense/mvc/app/views/OPNsense/Firewall/dnat_rule.volt
+5-01 files

OPNSense/ports 5a791dd — www/caddy-custom Makefile

by Franco Fichtner on ⎇
www/caddy-custom: clear revision as would be customary on version bump
DeltaFile
+1-1www/caddy-custom/Makefile
+1-11 files

OPNSense/ports dc32e40 — security/vuxml/vuln 2026.xml 2025.xml

by Franco Fichtner on ⎇
security/vuxml: sync with upstream

Taken from: FreeBSD
DeltaFile
+273-0security/vuxml/vuln/2026.xml
+10-6security/vuxml/vuln/2025.xml
+283-62 files

OPNSense/ports 7d129fd — www/caddy distinfo Makefile

by Franco Fichtner on ⎇
www/caddy: sync with upstream

Taken from: FreeBSD
DeltaFile
+5-5www/caddy/distinfo
+1-2www/caddy/Makefile
+6-72 files

OPNSense/ports 79fd620 — sysutils/cpu-microcode-intel distinfo Makefile

by Franco Fichtner on ⎇
sysutils/cpu-microcode-intel: sync with upstream

Taken from: FreeBSD
DeltaFile
+3-3sysutils/cpu-microcode-intel/distinfo
+1-1sysutils/cpu-microcode-intel/Makefile
+4-42 files

OPNSense/ports a789bbc — dns/dnscrypt-proxy2 distinfo Makefile

by Franco Fichtner on ⎇
dns/dnscrypt-proxy2: sync with upstream

Taken from: FreeBSD
DeltaFile
+3-3dns/dnscrypt-proxy2/distinfo
+1-2dns/dnscrypt-proxy2/Makefile
+4-52 files

LLVM/project a368bd4 — clang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenModule.h, clang/test/CIR/CodeGenCUDA kernel-args.cu

by sweiglbosker via GitHub on ⎇
[CIR][CUDA]: Handle duplicate mangled names (#183976)

Replace the NYI for duplicate function defs with the proper diagnostic
logic from OG codegen.

Related: #175871, #179278
DeltaFile
+40-0clang/test/CIR/CodeGenCUDA/kernel-args.cu
+23-1clang/lib/CIR/CodeGen/CIRGenModule.cpp
+5-0clang/lib/CIR/CodeGen/CIRGenModule.h
+68-13 files

OPNSense/core 5b1c0a3 — src/opnsense/mvc/app/models/OPNsense/Firewall DNat.php

by Monviech on ⎇
Simplify validation messages
DeltaFile
+6-6src/opnsense/mvc/app/models/OPNsense/Firewall/DNat.php
+6-61 files

LLVM/project acfc1a8 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/IR Verifier.cpp

by Jonathan Thackray on ⎇
fixup! More small optimisations Kerry spotted
DeltaFile
+7-12clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-3llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+1-2llvm/lib/IR/Verifier.cpp
+10-173 files

LLVM/project 2cbe5ee — clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/IR Verifier.cpp

by Jonathan Thackray on ⎇
fixup! More small optimisations Kerry spotted
DeltaFile
+3-6clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-3llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+1-2llvm/lib/IR/Verifier.cpp
+6-113 files

LLVM/project ac6fd51 — clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

by Jonathan Thackray on ⎇
fixup! Small fixes Kerry has suggested
DeltaFile
+112-40llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+7-11clang/lib/Sema/SemaARM.cpp
+7-9llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+127-614 files

LLVM/project 55bcb7c — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

by Jonathan Thackray on ⎇
fixup! Fix tests
DeltaFile
+2-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-01 files

LLVM/project c004dba — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

by Jonathan Thackray on ⎇
fixup! More small fixes
DeltaFile
+15-37clang/lib/Sema/SemaARM.cpp
+11-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5-3clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-2clang/lib/Headers/arm_acle.h
+0-1clang/test/CodeGen/arm_acle.c
+33-435 files

LLVM/project 4b3554b — llvm/test/CodeGen/AArch64 pcdphint-atomic-store.ll

by Jonathan Thackray on ⎇
fixup! Sort out testcases
DeltaFile
+54-102llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+54-1021 files

LLVM/project 1300ed5 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

by Jonathan Thackray on ⎇
fixup! Address Carol's comments and fix git clang-format issues
DeltaFile
+27-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+20-0llvm/lib/IR/Verifier.cpp
+12-6clang/lib/Sema/SemaARM.cpp
+0-11clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-4llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+4-2clang/lib/Headers/arm_acle.h
+65-236 files

LLVM/project e43f8bb — clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td

by Jonathan Thackray on ⎇
fixup! Address more helpful review comments from Kerry
DeltaFile
+160-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4-4llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1-4clang/lib/Sema/SemaARM.cpp
+0-5llvm/lib/Target/AArch64/AArch64InstrFormats.td
+165-134 files

LLVM/project 79c05bb — clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

by Jonathan Thackray on ⎇
fixup! Fixes for Caroline
DeltaFile
+27-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+1-12llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-2llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+0-3clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+30-174 files

LLVM/project e9692c2 — clang/test/CodeGen arm_acle.c builtins-arm64.c, clang/test/Sema/AArch64 pcdphint-atomic-store.c

by Jonathan Thackray on ⎇
fixup! Fix more PR comments
DeltaFile
+19-9clang/test/Sema/AArch64/pcdphint-atomic-store.c
+8-6llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+10-0clang/test/CodeGen/arm_acle.c
+0-9llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5-0clang/test/CodeGen/builtins-arm64.c
+0-4llvm/include/llvm/IR/IntrinsicsAArch64.td
+42-282 files not shown
+44-328 files

LLVM/project 4b07a1e — clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

by Jonathan Thackray on ⎇
fixup! Fix issues Kerry raised in PR
DeltaFile
+10-23clang/lib/Sema/SemaARM.cpp
+16-11clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5-12clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1-5clang/include/clang/Basic/DiagnosticSemaKinds.td
+32-514 files

LLVM/project 70993b1 — llvm/include/llvm/IR IntrinsicsAArch64.td, llvm/lib/Target/AArch64 AArch64InstrFormats.td

by Jonathan Thackray on ⎇
fixup! remove mayLoad/mayStore as suggested by Kerry
DeltaFile
+0-5llvm/lib/Target/AArch64/AArch64InstrFormats.td
+1-1llvm/include/llvm/IR/IntrinsicsAArch64.td
+1-62 files

LLVM/project 982af60 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen/AArch64 pcdphint-atomic-store.c

by Jonathan Thackray on ⎇
fixup! Ensure stshh always immediately precedes a store instruction
DeltaFile
+82-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+50-13clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+62-0llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+20-26clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+15-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+8-3llvm/lib/Target/AArch64/AArch64InstrFormats.td
+237-423 files not shown
+248-499 files

LLVM/project ca90752 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

by Jonathan Thackray on ⎇
fixup! Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`

Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
and use tablegen pattern for intrinsic, plus other small review changes.
DeltaFile
+47-75llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+69-32llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+42-47clang/lib/Sema/SemaARM.cpp
+21-12llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+10-12llvm/lib/Target/AArch64/AArch64InstrInfo.td
+17-5clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+206-1835 files not shown
+220-19211 files

LLVM/project 6a1744f — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/Sema/AArch64 pcdphint-atomic-store.c

by Jonathan Thackray on ⎇
fixup!

A few small tidyups
DeltaFile
+7-6clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4-4llvm/lib/Target/AArch64/AArch64InstrFormats.td
+4-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+15-103 files