LLVM/project b025f5bclang/test/CIR/CodeGen ptrdiff.cpp ptrdiff.c

[clang][cir] Fix tests post #210729 (#216963)
DeltaFile
+7-5clang/test/CIR/CodeGen/ptrdiff.c
+4-3clang/test/CIR/CodeGen/ptrdiff.cpp
+11-82 files

LLVM/project 3161d70llvm/lib/Target/SystemZ SystemZInstrInfo.cpp, llvm/test/CodeGen/SystemZ patchable-function-entry.ll

[SystemZ] Keep patchable function entries at function start (#216762)

Currently SystemZ's PostRA Scheduler is allowed to move
PATCHABLE_FUNCTION_ENTER around, defeating its purpose:

    bb.0 (%ir-block.0):
      PATCHABLE_FUNCTION_ENTER
      $r2d = LGHI 1

    [...]

# *** IR Dump After PostRA Machine Instruction Scheduler (postmisched)
***:

    [...]

    bb.0 (%ir-block.0):
      $r2d = LGHI 1
      PATCHABLE_FUNCTION_ENTER

    [7 lines not shown]
DeltaFile
+19-0llvm/test/CodeGen/SystemZ/patchable-function-entry.ll
+2-1llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+21-12 files

FreeNAS/freenas 11d38afsrc/middlewared/middlewared/pytest/unit datastore_harness.py, src/middlewared/middlewared/pytest/unit/plugins/alert test_lifecycle.py

Alert lifecycle unit tests
DeltaFile
+438-0src/middlewared/middlewared/pytest/unit/plugins/alert/test_lifecycle.py
+24-0src/middlewared/middlewared/pytest/unit/datastore_harness.py
+462-02 files

HardenedBSD/src 92450d2sys/arm64/arm64 vfp.c, sys/dev/ixgbe if_ix.c

Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/pledge
DeltaFile
+19-4sys/dev/ixgbe/if_ix.c
+3-4sys/arm64/arm64/vfp.c
+22-82 files

HardenedBSD/src 6c20a03sys/arm64/arm64 vfp.c, sys/dev/ixgbe if_ix.c

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+19-4sys/dev/ixgbe/if_ix.c
+3-4sys/arm64/arm64/vfp.c
+22-82 files

HardenedBSD/src c103eabusr.sbin/pmcstat pmcstat.8

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main
DeltaFile
+2-2usr.sbin/pmcstat/pmcstat.8
+2-21 files

HardenedBSD/ports e53ad94comms/rtl-sdr Makefile, deskutils/flameshot Makefile

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+573-701sysutils/yazi/distinfo
+286-350sysutils/yazi/Makefile.crates
+49-0sysutils/yazi/files/patch-yazi-fs_src_engine_local_casefold.rs
+0-46sysutils/yazi/files/patch-yazi-fs_src_provider_local_casefold.rs
+20-10deskutils/flameshot/Makefile
+12-12comms/rtl-sdr/Makefile
+940-1,11914 files not shown
+1,009-1,14420 files

OPNSense/core 7cf8d56src/opnsense/mvc/app/controllers/OPNsense/Interfaces/forms dialogAssignment.xml, src/opnsense/mvc/app/models/OPNsense/Interfaces NetworkInterface.php NetworkInterface.xml

Interfaces: Assignments - add interface configuration settings in new assignments page. for https://github.com/opnsense/core/issues/10568

Refactor NetworkInterface model to reuse existing property names as much as possible, move from/to legacy logic into a custom fieldtype and store all legacy settings in a container named "pending" to ease reconfiguration and updating legacy configurations.
DeltaFile
+191-0src/opnsense/mvc/app/controllers/OPNsense/Interfaces/forms/dialogAssignment.xml
+123-0src/opnsense/mvc/app/models/OPNsense/Interfaces/FieldTypes/NetworkInterfaceField.php
+91-1src/opnsense/mvc/app/models/OPNsense/Interfaces/NetworkInterface.xml
+66-10src/opnsense/mvc/app/models/OPNsense/Interfaces/NetworkInterface.php
+18-1src/opnsense/scripts/interfaces/apply_pending_if_changes.php
+16-1src/opnsense/mvc/app/views/OPNsense/Interface/assignment.volt
+505-132 files not shown
+517-158 files

LLVM/project a8bfa17mlir/include/mlir/IR OperationSupport.h

[MLIR] Document the OperationState properties invariant (#216686)

OperationState keeps `properties` together with the `propertiesDeleter`
and `propertiesSetter` hooks: the two `function_ref`s are non-null
whenever `properties` is non-null, and they are only ever called after
checking `properties`.

Static analyzers do not see that invariant. Because an empty
`function_ref` leaves its `callable` field indeterminate, Coverity
reports "Uninitialized scalar variable" at every site that copies an
OperationState: 6,436 of the 7,201 outstanding findings in the LLVM
Coverity project, nearly all in tblgen-generated `Op::create` methods.

Per review feedback, this no longer initializes `function_ref::callable`
in ADT. Instead it documents the invariant and suppresses the false
positive locally with a `// coverity[uninit_member]` annotation.
DeltaFile
+4-0mlir/include/mlir/IR/OperationSupport.h
+4-01 files

OPNSense/core 5c6f650src/opnsense/www/js opnsense_ui.js

ui: Add shortcut key f for ShowMaximized() modal
DeltaFile
+7-0src/opnsense/www/js/opnsense_ui.js
+7-01 files

OPNSense/core 0a13322src/opnsense/mvc/app/library/OPNsense/Firewall Plugin.php

firewall: deprecate old register function names due to overlaps
DeltaFile
+25-7src/opnsense/mvc/app/library/OPNsense/Firewall/Plugin.php
+25-71 files

LLVM/project 3c02e3amlir/include/mlir/Dialect/SCF/IR SCFOps.td, mlir/lib/Dialect/SCF/IR SCF.cpp

[mlir][scf] Sink ops into multi-block scf.execute_region (#216993)

Teach scf.execute_region to report its body is invoked exactly once via
RegionBranchOpInterface. This make the execute_region eligible for
sinking.

Also walk all blocks in a region instead of just the entry block so uses
in non-entry blocks can trigger sinking.

Fixes #216733
DeltaFile
+22-0mlir/test/Dialect/SCF/control-flow-sink.mlir
+4-2mlir/lib/Transforms/Utils/ControlFlowSinkUtils.cpp
+5-0mlir/lib/Dialect/SCF/IR/SCF.cpp
+2-1mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
+33-34 files

LLVM/project 9ad190eclang/lib/AST ASTContext.cpp, clang/test/CodeGen builtin-clear-padding-codegen.c

[Clang] Fix BitInt padding clearing on big-endian targets

This patch fixes the padding clearing logic of `_BitInt`s.

Before this patch, the clearing logic assumed little endian. But the
memory layout of BitInts differs between little and big endian:

 - In LE, the occupied bits start from the lowest address and go on
   contiguously up until the BitInt's declared size. The padding bits
   then start from that point and go contiguously until the end of the
   storage unit.
 - In BE, since the byte order is reversed, the occupied bit interval
   is not contiguous if the storage unit is larger than the BitInt's
   size.

Therefore, the logic must tell the two cases apart and perform the
calculations accordingly.
DeltaFile
+81-0clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+81-0clang/test/CodeGen/builtin-clear-padding-codegen.c
+46-0clang/lib/AST/ASTContext.cpp
+208-03 files

LLVM/project 2ee4f96llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-vector-deinterleave.ll sve-vector-interleave.ll

[AArch64][ISel] Enable factor 3 interleave/deinterleave i1 support (#215524)

Add support for factor 3 interleave/deinterleave SVE predicate vectors.
This works by converting predicate operands to packed integer vectors,
reusing the existing interleave/deinterleave lowering, then converting
the nonzero results back to predicates.
DeltaFile
+108-0llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
+52-0llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
+30-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+190-03 files

LLVM/project 3763110llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 long-non-power-of-2.ll abs-mul-buildvector-in-loop.ll

[SLP]Fix narrow-tree gate width and extract miscount

Measure the narrowness of in-loop trees by the actual vectorization
width instead of the feeder-load width, and skip vector-typed scalars
in the instruction count check to match the cost model.

Fixes #216715

Reviewers: efriedma-quic, bababuck, RKSimon, kartcq

Pull Request: https://github.com/llvm/llvm-project/pull/216797
DeltaFile
+15-14llvm/test/Transforms/SLPVectorizer/AArch64/abs-mul-buildvector-in-loop.ll
+17-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4-2llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
+36-173 files

LLVM/project 28c2341llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp, llvm/test/CodeGen/SystemZ inline-asm-i128.ll

[SystemZ] Support the 'M' code for the odd register in inline-asm (#215481)

GCC considers 'M' to be an alias of 'N' when it comes to register
operands - regardless of the actual operand size [1]:

    $ cat 1.c
    void f(void) {
        __int128 x;
        asm volatile("# M=%M0 N=%N0" : "=r" (x));
    }
    $ gcc -S -O3 1.c
    $ cat 1.s
    [...]
    # M=%r3 N=%r3
    [...]

Do the same in LLVM; duplicate the existing 'N' test.

[1]
https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/s390/s390.cc;h=038eb57759ef#l9104
DeltaFile
+38-2llvm/test/CodeGen/SystemZ/inline-asm-i128.ll
+2-2llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+40-42 files

LLVM/project bd4b632llvm/lib/ExecutionEngine/Orc LLJIT.cpp

[JITLink] Make JITLink default in LLJIT for SystemZ (#215486)

ClangReplInterpreterTests fails on SystemZ with:

    ExecutorNativePlatform requires ObjectLinkingLayer

JITLink seems to have become a superset of rtdyld on SystemZ. Make it
default.
DeltaFile
+3-0llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
+3-01 files

LLVM/project 05cfc88compiler-rt/test/orc/TestCases/Linux/systemz trivial-cxa-atexit.S trivial-atexit.S

[JITLink] Allocate frames in SystemZ atexit tests (#215482)

SystemZ JITLink atexit tests crash, because they call functions without
first allocating a frame.

Fix by allocating one. While at it, switch to the more conventional
slots for %r14 and %r15.
DeltaFile
+3-2compiler-rt/test/orc/TestCases/Linux/systemz/trivial-cxa-atexit.S
+3-2compiler-rt/test/orc/TestCases/Linux/systemz/trivial-atexit.S
+6-42 files

LLVM/project c1dc093clang/docs ReleaseNotes.md, clang/lib/Sema SemaTemplate.cpp

[clang] Fixed a crash when declaring a member template within a local class inside an OpenMP region (#216692)

When declaring a class template within an OpenMP region, the presence of
`CapturedDecl` causes `isLocalClass()` checks to fail, preventing the
compiler from taking the expected error path.

This patch adds traversal in `SemaTemplate` so that the compiler
properly emits an error and recovers.

Fix #216052
DeltaFile
+25-0clang/test/SemaOpenMP/gh216052.cpp
+13-4clang/lib/Sema/SemaTemplate.cpp
+1-0clang/docs/ReleaseNotes.md
+39-43 files

OpenBSD/ports ALhRbO3devel/indi Makefile

   this now bundles a header-only library which doesn't support 32-bit archs
VersionDeltaFile
1.13+3-0devel/indi/Makefile
+3-01 files

LLVM/project a0090c9llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 reduction-vals-used-as-load-indices.ll

[SLP]Extend GEP pointer-chain cost to casts and non-root external uses

Look through single-use zext/sext index promotions and cover trees whose
root scalars have no external users (e.g. reductions): escaped non-root
scalars may still drive load/store addresses, and extracting them puts
the vector dependency chain on the loads' address path.

Fixes #182306

Reviewers: RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/216520
DeltaFile
+27-30llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+36-19llvm/test/Transforms/SLPVectorizer/X86/reduction-vals-used-as-load-indices.ll
+63-492 files

OPNSense/core 61b93e7src/opnsense/mvc/app/library/OPNsense/Firewall Plugin.php

firewall: deprecate old register function names due to overlaps
DeltaFile
+24-6src/opnsense/mvc/app/library/OPNsense/Firewall/Plugin.php
+24-61 files

FreeNAS/freenas 0748ce4src/middlewared/middlewared/pytest/unit/alert test_applicability_matrix.py test_alert_black_holes.py

Drive the alert enforcement sites from unit tests

This commit adds changes to test the four sites in plugins/alert.py that consume an applicability rule, rather than only the rules themselves. The run and send axes had no execution coverage at all: emptying the excluded-source set, deleting the alert purge loop, or making the send filter answer True all left the suite green. These drive __run_alerts and send_alerts against stub sources through a shared harness, and record what the policies delete, since dropping the purge loop still leaves the alert list correct and nothing else can see it.

The purge is worth pinning on its own because it destroys state: a source whose rule stops admitting this system loses the alerts it had persisted, and when it applies again they come back with a fresh uuid and their dismissed flag cleared. There is also an asymmetry three lines apart in that loop, deliberate but unasserted until now, where a rule-excluded source is purged and a gate-blocked one is only skipped.

Also fixes both AST scanners. BondStatus is a shipped source that does not carry the AlertSource name suffix, so the black hole check never saw it or the three classes it creates; keying off the subclass relation the loader itself uses picks it up and keeps the two modules from disagreeing. Reading attribute-spelled bases stops a class written as base.AlertClass dropping out of the frozen inventory with nothing to show for it. Both scanners now carry an invariant test, so a shape they cannot model fails instead of silently shrinking what is covered.
DeltaFile
+207-0src/middlewared/middlewared/pytest/unit/alert/harness.py
+163-0src/middlewared/middlewared/pytest/unit/alert/test_alert_send_alerts.py
+124-0src/middlewared/middlewared/pytest/unit/alert/test_alert_run_loop.py
+31-25src/middlewared/middlewared/pytest/unit/alert/test_alert_plugin_applicability.py
+41-4src/middlewared/middlewared/pytest/unit/alert/test_alert_black_holes.py
+36-3src/middlewared/middlewared/pytest/unit/alert/test_applicability_matrix.py
+602-322 files not shown
+615-468 files

OpenBSD/ports AhBVYqAdevel/py-cffi Makefile distinfo, devel/py-cffi/patches patch-testing_cffi1_test_verify1_py patch-testing_cffi0_test_verify_py

   update to py3-cffi-2.1.1, fix some tests
VersionDeltaFile
1.1+14-0devel/py-cffi/patches/patch-testing_cffi1_test_re_python_py
1.1+14-0devel/py-cffi/patches/patch-testing_cffi0_test_ownlib_py
1.1+12-0devel/py-cffi/patches/patch-testing_cffi1_test_verify1_py
1.1+12-0devel/py-cffi/patches/patch-testing_cffi0_test_verify_py
1.15+2-2devel/py-cffi/distinfo
1.38+1-2devel/py-cffi/Makefile
+55-46 files

LLVM/project 841d6e4llvm/lib/Target/AMDGPU SILowerI1Copies.h SILowerI1Copies.cpp

AMDGPU: Extract mergeIncomingLaneMasks from SILowerI1Copies lowerPhis

Factor the SSA-updater lane-mask merge core out of lowerPhis into a
helper function for future use. The merge logic is independent of how
the incoming values are collected. NFC

Co-Authored-By: Claude <noreply at anthropic.com> claude-opus-4.8
DeltaFile
+85-84llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+10-0llvm/lib/Target/AMDGPU/SILowerI1Copies.h
+95-842 files

LLVM/project e08a592clang/lib/AST ExprConstant.cpp, clang/lib/AST/ByteCode State.cpp

Revert "[clang] Allow C-style casts in constexpr in MS compatible mode (#197005)"

This reverts commit 2336d2cec6b4845691251869ebc1442595008a60.
DeltaFile
+0-141clang/test/SemaCXX/microsoft-constexpr.cpp
+0-42clang/test/SemaCXX/microsoft-constexpr2.cpp
+11-18clang/lib/AST/ExprConstant.cpp
+7-21clang/lib/Sema/SemaOverload.cpp
+0-24clang/lib/AST/ByteCode/State.cpp
+0-20clang/test/SemaCXX/microsoft-constexpr-SFINAE2.cpp
+18-2669 files not shown
+27-36015 files

OpenBSD/src DWCsepxlib/libcrypto/man s2i_ASN1_INTEGER.3

   s2i_ASN1_INTEGER.3: mark up second use of usr_data for consistency
VersionDeltaFile
1.12+5-3lib/libcrypto/man/s2i_ASN1_INTEGER.3
+5-31 files

LLVM/project 836904bllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv zvdot4a8i-i64-sdnode.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+899-0llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-i64-sdnode.ll
+47-4llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+946-42 files

LLVM/project 3a7c2d9llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv zvdot4a8i-i64-sdnode.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+899-0llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-i64-sdnode.ll
+120-0llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product-costs.ll
+47-4llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+26-5llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+1,092-94 files

LLVM/project 9b7652cclang/include/clang/Basic AttrDocs.td, lldb/source/Plugins/Process/Utility RegisterInfos_riscv32.h

Rebase and split cost

Created using spr 1.3.6-beta.1
DeltaFile
+13,767-6,856llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-sve-instructions.s
+6,347-3,146llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-neon-instructions.s
+4,432-4,282clang/include/clang/Basic/AttrDocs.td
+5,067-2,506llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-basic-instructions.s
+375-4,097lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
+2,202-1,876llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+32,190-22,7634,784 files not shown
+220,178-111,3944,790 files