FreeBSD/ports f155b5enet-mgmt/monitoring-plugins pkg-plist Makefile

net-mgmt/monitoring-plugins: Add CURL option to build check_curl

Upstream deprecated check_http in 3.0.0 and declared check_curl its
stable replacement, so make the plugin available here as an option.
It is off by default, like every other option in this port that pulls
an external library.

check_curl requires libcurl and uriparser. configure only knows
--with-libcurl and --with-uriparser, so pass those explicitly instead
of relying on autodetection. The submitted patch used a --with-curl
knob that does not exist and was missing the libcurl dependency.

PR:             296901
Submitted by:   franz at electromail.org
Sponsored by:   Netzkommune GmbH
DeltaFile
+8-2net-mgmt/monitoring-plugins/Makefile
+1-0net-mgmt/monitoring-plugins/pkg-plist
+9-22 files

LLVM/project 97adc8fllvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU SIInstructions.td

[AMDGPU] Guard media instruction patterns with target feature

As well as their corresponding intrinsics.
DeltaFile
+1,608-357llvm/test/CodeGen/AMDGPU/sad.ll
+2-273llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
+2-121llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
+44-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intrinsics.sad.err.ll
+15-13llvm/lib/Target/AMDGPU/SIInstructions.td
+10-4llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+1,681-7686 files

LLVM/project 6a1dd3dllvm/lib/Target/M68k M68kTargetMachine.cpp

[M68k] Fix build after InstructionSelect rename (#218059)

Done in 8f543c25c44eb175b583bceaa9230dd981cdd463.

Fixes https://lab.llvm.org/buildbot/#/builders/27/builds/3952.
DeltaFile
+1-1llvm/lib/Target/M68k/M68kTargetMachine.cpp
+1-11 files

LLVM/project 9f5b384llvm/test/CodeGen/AMDGPU schedule-fs-loop.ll amdgpu-sw-lower-lds-dynamic-indirect-access.ll, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-add.s16.mir

[NFC][AMDGPU] Remove redundant CodeGen test coverage

This PR removes duplicate test files, cases, and RUN commands while preserving all effective coverage.

Deleted files:

- `unexpected-reg-unit-state.mir` duplicates the bar case in `fast-ra-kills-vcc.mir`.
- `schedule-fs-loop.ll` produces the same bitcode and output as `schedule-fs-loop-nested-if.ll`.
- `regbankselect-add.s16.mir` duplicates the first four cases in `regbankselect-add.mir`.
- The dynamic-indirect-access LDS tests duplicate the static-dynamic versions, including their ASAN variants.
- The two removed NextUseAnalysis tests duplicate `sequence_2_loops.mir` and `triple-nested-loops.mir`.

Trimmed test cases:

- Remove generic OR cases from `atomicrmw-xor.ll`; `atomicrmw-or.ll` contains them.
- Remove the fcmp ord case from `fmax_legacy.ll`; `fmin_legacy.ll` contains it.
- Remove `variable_memcpy_caller1` from `lower-mem-intrinsics.ll`; `caller0` provides identical coverage.

Deduplicated test commands:

    [4 lines not shown]
DeltaFile
+0-6,246llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
+0-4,877llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
+0-262llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
+0-142llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access.ll
+0-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
+0-84llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll
+0-11,71310 files not shown
+10-11,88816 files

LLVM/project 34aca4bllvm/lib/Target/RISCV RISCVMoveMerger.cpp RISCVInstrInfoZc.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV][NFC] Rename SR07 RegClass to GPRS07 (#218007)
DeltaFile
+3-3llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+3-3llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+2-2llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td
+12-125 files

LLVM/project 9413219llvm/test/Transforms/SLPVectorizer/AMDGPU store-chain-two-external-users.ll

[SLP] Precommit test to relax store chain user limit (#217990)

Precommit test for https://github.com/llvm/llvm-project/pull/215700
DeltaFile
+502-0llvm/test/Transforms/SLPVectorizer/AMDGPU/store-chain-two-external-users.ll
+502-01 files

LLVM/project b91e4dcbolt/runtime instr.cpp, utils/bazel/llvm-project-overlay/llvm BUILD.bazel

Merge branch 'main' into users/mtrofin/08-12-_wpd_dereference_globalalias_targets
DeltaFile
+12-7bolt/runtime/instr.cpp
+2-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+14-72 files

LLVM/project 2358932llvm/include/llvm/Frontend/HLSL SemanticSignaturePacking.h, llvm/lib/Frontend/HLSL SemanticSignaturePacking.cpp

implement stacked sort
DeltaFile
+32-2llvm/lib/Frontend/HLSL/SemanticSignaturePacking.cpp
+3-0llvm/include/llvm/Frontend/HLSL/SemanticSignaturePacking.h
+35-22 files

LLVM/project ae2d3c3llvm/unittests/Frontend HLSLSemanticSignaturePackingTest.cpp

add test cases
DeltaFile
+199-0llvm/unittests/Frontend/HLSLSemanticSignaturePackingTest.cpp
+199-01 files

LLVM/project 3dcda30llvm/docs/DirectX SemanticSignatures.md, llvm/include/llvm/Frontend/HLSL SemanticSignaturePacking.h

document stacked signature packing
DeltaFile
+48-0llvm/docs/DirectX/SemanticSignatures.md
+2-12llvm/include/llvm/Frontend/HLSL/SemanticSignaturePacking.h
+50-122 files

LLVM/project 75c7969llvm/include/llvm/Frontend/HLSL SemanticSignaturePacking.h, llvm/lib/Frontend/HLSL SemanticSignaturePacking.cpp

add error kind
DeltaFile
+28-1llvm/include/llvm/Frontend/HLSL/SemanticSignaturePacking.h
+9-3llvm/unittests/Frontend/HLSLSemanticSignaturePackingTest.cpp
+11-0llvm/lib/Frontend/HLSL/SemanticSignaturePacking.cpp
+48-43 files

LLVM/project 82a3418llvm/include/llvm/Frontend/HLSL SemanticSignaturePacking.h, llvm/lib/Frontend/HLSL CMakeLists.txt SemanticSignaturePacking.cpp

add test harness and snub
DeltaFile
+137-0llvm/unittests/Frontend/HLSLSemanticSignaturePackingTest.cpp
+42-0llvm/include/llvm/Frontend/HLSL/SemanticSignaturePacking.h
+22-0llvm/lib/Frontend/HLSL/SemanticSignaturePacking.cpp
+1-0llvm/unittests/Frontend/CMakeLists.txt
+1-0llvm/lib/Frontend/HLSL/CMakeLists.txt
+203-05 files

LLVM/project 9857c67utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[Bazel] Use MSVC spelling for trapping math (#218051)

Use `/fp:except` for clang-cl and MSVC, matching [the CMake
build](https://github.com/llvm/llvm-project/blob/da24a7e95694fcb4a1e78d81824cd6bb3d3cd0f6/llvm/lib/Analysis/CMakeLists.txt#L37-L49).
Emscripten and other compiler behavior is unchanged.
DeltaFile
+2-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+2-01 files

LLVM/project 9ccb39abolt/runtime instr.cpp

[BOLT] Fix instr.cpp attribute warnings on arm (#218036)

The `force_align_arg_pointer` is exclusive to x86. This causes builds to
fail on arm with -Werror. Omit this attribute on non-x86 platforms.
DeltaFile
+12-7bolt/runtime/instr.cpp
+12-71 files

LLVM/project e3cc6a3llvm/lib/Target/AMDGPU SIISelLowering.h VOP3Instructions.td, llvm/test/CodeGen/AMDGPU arbitrary-fp-to-float-fp8-hw.ll float-to-arbitrary-fp-fp8-hw.ll

[AMDGPU] Add custom lowering for E5M3 path for packed convert instructions through convert.{to|from}.arbitrary.fp

Change-Id: I2b7ef70332fcaafe63245e0afba58829ede8f3e4
DeltaFile
+1,540-3llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+460-1llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll
+49-14llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+10-0llvm/lib/Target/AMDGPU/SIInstrInfo.td
+2-2llvm/lib/Target/AMDGPU/VOP3Instructions.td
+2-1llvm/lib/Target/AMDGPU/SIISelLowering.h
+2,063-211 files not shown
+2,065-217 files

LLVM/project d878ddbclang/test/Preprocessor riscv-target-features.c, llvm/include/llvm/CodeGen/GlobalISel InstructionSelect.h

Merge branch 'main' into users/mtrofin/08-12-_wpd_dereference_globalalias_targets
DeltaFile
+91-10llvm/test/CodeGen/AMDGPU/redundant-and.mir
+68-13llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+39-21clang/test/Preprocessor/riscv-target-features.c
+59-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+50-7llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
+33-0llvm/test/MC/RISCV/smip-ssip-invalid.s
+340-5131 files not shown
+512-12837 files

LLVM/project 9675f27llvm/lib/Target/WebAssembly WebAssemblyCodeGenPassBuilder.cpp

[WebAssembly][NewPM] Add GISel Pass Skeleton

Mostly complete, but I still need to port a few more passes.

Reviewers: sbc100, dschuff, aheejin, QuantumSegfault

Pull Request: https://github.com/llvm/llvm-project/pull/217981
DeltaFile
+59-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+59-01 files

LLVM/project 8105839clang-tools-extra/docs/clang-tidy/checks/cert err33-c.md, lldb/test/API/functionalities/gdb_remote_client TestWasm.py

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-2,733llvm/docs/LangRef.md
+608-81lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
+288-208llvm/test/CodeGen/CSKY/atomic-rmw.ll
+407-0llvm/test/Transforms/Reassociate/fma-pairs.ll
+390-0llvm/test/Transforms/SLPVectorizer/X86/horizontal-fadd-with-sub.ll
+187-188clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.md
+1,880-3,210367 files not shown
+9,687-7,394373 files

LLVM/project 8f543c2llvm/include/llvm/CodeGen/GlobalISel InstructionSelect.h, llvm/lib/CodeGen/GlobalISel InstructionSelect.cpp

[GlobalISel][NewPM] Port InstructionSelect

Standard NewPM pass porting. We have to keep the Impl class in the
header given it is used by unittests, although it's not very big so it
shouldn't be a huge deal.

Reviewers: aemerson, arsenm, aengelke, vikramRH, lenary

Pull Request: https://github.com/llvm/llvm-project/pull/217968
DeltaFile
+66-13llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+45-4llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
+2-2llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+2-1llvm/unittests/CodeGen/GlobalISel/InstructionSelectTest.cpp
+1-1llvm/lib/Target/X86/X86TargetMachine.cpp
+1-1llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+117-2212 files not shown
+129-3218 files

LLVM/project e1c5ea2clang-tools-extra/docs/clang-tidy/checks/cert err33-c.md, lldb/test/API/functionalities/gdb_remote_client TestWasm.py

rebase

Created using spr 1.3.7
DeltaFile
+0-2,733llvm/docs/LangRef.md
+608-81lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
+288-208llvm/test/CodeGen/CSKY/atomic-rmw.ll
+407-0llvm/test/Transforms/Reassociate/fma-pairs.ll
+390-0llvm/test/Transforms/SLPVectorizer/X86/horizontal-fadd-with-sub.ll
+187-188clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.md
+1,880-3,210367 files not shown
+9,687-7,394373 files

LLVM/project c352f7dclang-tools-extra/docs/clang-tidy/checks/cert err33-c.md, lldb/test/API/functionalities/gdb_remote_client TestWasm.py

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-2,733llvm/docs/LangRef.md
+608-81lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
+288-208llvm/test/CodeGen/CSKY/atomic-rmw.ll
+407-0llvm/test/Transforms/Reassociate/fma-pairs.ll
+390-0llvm/test/Transforms/SLPVectorizer/X86/horizontal-fadd-with-sub.ll
+187-188clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.md
+1,880-3,210367 files not shown
+9,687-7,394373 files

LLVM/project 4c76122llvm/lib/Target/M68k M68kTargetMachine.cpp

[M68k] Pass optLevel to InstructionSelect

This makes it the same as every other in-tree target.

Reviewers: arsenm, mshockwave

Pull Request: https://github.com/llvm/llvm-project/pull/217930
DeltaFile
+1-1llvm/lib/Target/M68k/M68kTargetMachine.cpp
+1-11 files

LLVM/project c058dd2clang-tools-extra/docs/clang-tidy/checks/cert err33-c.md, lldb/test/API/functionalities/gdb_remote_client TestWasm.py

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-2,733llvm/docs/LangRef.md
+608-81lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
+288-208llvm/test/CodeGen/CSKY/atomic-rmw.ll
+407-0llvm/test/Transforms/Reassociate/fma-pairs.ll
+390-0llvm/test/Transforms/SLPVectorizer/X86/horizontal-fadd-with-sub.ll
+187-188clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.md
+1,880-3,210366 files not shown
+9,585-7,383372 files

LLVM/project b17bf71llvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU redundant-and.mir

[AMDGPU] Check register class when folding a redundant AND (#217900)

tryFoldRedundantAND accepts an SALU AND as the parent instruction. The
child
AND can be a VALU instruction, so the fold replaced a VGPR with an SGPR
in
every use of the child result. A use that requires a VGPR, for example
data0
of DS_BPERMUTE_B32, then fails the machine verifier. This aborted a
rocPRIM
build for gfx1010.

Call constrainRegClass on the replacement register with the register
class of
the folded register, and fold only when it succeeds. Every use of the
folded
register accepts its register class, so the constrained replacement
register
is legal in those uses, and no walk over the uses is needed.

    [11 lines not shown]
DeltaFile
+91-10llvm/test/CodeGen/AMDGPU/redundant-and.mir
+13-2llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+104-122 files

LLVM/project f75215doffload/languages/kernel/src LanguageRuntime.cpp, offload/test/offloading/CUDA launch_tu.cu basic_launch_multi_arg.cu

add proper deviceSync
DeltaFile
+98-0offload/test/offloading/CUDA/devicesync_streams.cu
+97-0offload/test/offloading/HIP/devicesync_streams.hip
+13-7offload/languages/kernel/src/LanguageRuntime.cpp
+1-1offload/test/offloading/CUDA/launch_tu.cu
+1-1offload/test/offloading/CUDA/basic_launch_multi_arg.cu
+1-1offload/test/offloading/CUDA/basic_launch_blocks_and_threads.cu
+211-107 files not shown
+218-1313 files

LLVM/project fbae994llvm/lib/Target/SPIRV SPIRVTargetMachine.cpp, llvm/test/CodeGen/SPIRV llc-pipeline.ll

[SPIRV] Pass optLevel to InstructionSelect

Canonical with all other targets (minus m68k which I will fix next).
Seems to have been dropped in eab7d3639b3c6dc9dda9a0ab1643f0e45ad2d9d6
accidentally when introducing the InstructionSelect subclass to avoid
the need for RegBankSelect.

Reviewers: Keenuts, arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/217929
DeltaFile
+0-5llvm/test/CodeGen/SPIRV/llc-pipeline.ll
+1-1llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+1-62 files

LLVM/project 290c07aclang-tools-extra/docs/clang-tidy/checks/cert err33-c.md, lldb/test/API/functionalities/gdb_remote_client TestWasm.py

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-2,733llvm/docs/LangRef.md
+608-81lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
+288-208llvm/test/CodeGen/CSKY/atomic-rmw.ll
+407-0llvm/test/Transforms/Reassociate/fma-pairs.ll
+390-0llvm/test/Transforms/SLPVectorizer/X86/horizontal-fadd-with-sub.ll
+187-188clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.md
+1,880-3,210366 files not shown
+9,585-7,383372 files

LLVM/project da24a7ellvm/include/llvm/CodeGen/GlobalISel InstructionSelect.h, llvm/lib/CodeGen/GlobalISel InstructionSelect.cpp

[GISel] Remove SPIRVInstructionSelect

This subclass only existed to remove the need for MFs to have the
RegBankSelected property coming into InstructionSelect. The NewPM plays
much less nicely with pass inheritance, so change this to an option
specified as a parameter in the InstructionSelect constructor to avoid
inheritance so the future NewPM port can have the ~same API for
creation.

The usage of CodeGenOptLevel::Default matches the existing behavior,
although is probably wrong. That should be fixed in a separate patch
though.

Reviewers: arsenm, Keenuts

Pull Request: https://github.com/llvm/llvm-project/pull/217928
DeltaFile
+3-12llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+7-5llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
+4-2llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+14-193 files

LLVM/project f37c1a8clang/test/Preprocessor riscv-target-features.c, llvm/lib/Target/RISCV RISCVInstrInfoSmip.td RISCVFeatures.td

[RISCV][MC] Add experimental Smip, and Ssip support (#215095)

Add support for version 0.20 of the Smip, and Ssip extensions from the
RISC-V fast interrupt specification. Also bump the existing extensions
of ACLIC to 0.20.
DeltaFile
+39-21clang/test/Preprocessor/riscv-target-features.c
+33-0llvm/test/MC/RISCV/smip-ssip-invalid.s
+20-12llvm/test/CodeGen/RISCV/attributes.ll
+18-12llvm/test/MC/RISCV/attribute-arch.s
+21-6llvm/lib/Target/RISCV/RISCVFeatures.td
+21-0llvm/lib/Target/RISCV/RISCVInstrInfoSmip.td
+152-518 files not shown
+211-6514 files

LLVM/project 4d842ccllvm/lib/CodeGen PeepholeOptimizer.cpp, llvm/test/CodeGen/X86 peephole-compare-load-fold-ext.mir

[PeepholeOpt] Erase optimized compare from LocalMIs earlier (#217848)

We need to drop the compare instruction that was optimized away from
LocalMIs before the LocalMIs-based load folding optimization a few lines
below. Addresses a regression from #194662.

Fixes https://github.com/llvm/llvm-project/issues/208746.

---------

Co-authored-by: woruyu <1214539920 at qq.com>
(cherry picked from commit b26a359753175bd5cc53fb0f2a168d12bb0498c8)
DeltaFile
+40-0llvm/test/CodeGen/X86/peephole-compare-load-fold-ext.mir
+1-1llvm/lib/CodeGen/PeepholeOptimizer.cpp
+41-12 files