LLVM/project efffb04llvm/lib/Target/DirectX/DXILWriter DXILBitcodeWriter.cpp, llvm/test/tools/dxil-dis debug-info.ll

[DirectX] Fix DILocalVariable (#192573)

LLVM 3.7 did not allow the DW_TAG_variable tag for them and had two
custom tags instead.
DeltaFile
+3-3llvm/test/tools/dxil-dis/debug-info.ll
+4-1llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
+7-42 files

FreeBSD/ports 06b5387devel/task distinfo Makefile

devel/task: Update to 3.50.0

Changelog: https://github.com/go-task/task/blob/v3.50.0/CHANGELOG.md

Reported by:    GitHub (watch releases)
DeltaFile
+5-5devel/task/distinfo
+2-3devel/task/Makefile
+7-82 files

LLVM/project 3de3198llvm/lib/Target/DirectX/DXILWriter DXILBitcodeWriter.cpp, llvm/test/tools/dxil-dis vla.ll

[DirectX] Replace non-const count of DISubrange with -1 (#192576)

Non-const count is only emitted for C99 VLA, which are not supported.

Co-authored-by: Andrew Savonichev <andrew.savonichev at gmail.com>
DeltaFile
+38-0llvm/test/tools/dxil-dis/vla.ll
+14-10llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
+52-102 files

OPNSense/core 5f5aa92src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes BaseField.php

allow zero count on container, needs unit test later
DeltaFile
+1-1src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes/BaseField.php
+1-11 files

FreeNAS/freenas f5cb74fsrc/middlewared/middlewared/api/v27_0_0 app_registry.py, src/middlewared/middlewared/plugins/app_registry crud.py __init__.py

Convert app.registry service to be typesafe
DeltaFile
+55-66src/middlewared/middlewared/plugins/app_registry/crud.py
+52-0src/middlewared/middlewared/plugins/app_registry/__init__.py
+10-4src/middlewared/middlewared/plugins/app_registry/utils.py
+9-2src/middlewared/middlewared/plugins/apps_images/dockerhub_ratelimit.py
+5-3src/middlewared/middlewared/plugins/apps_images/utils.py
+4-2src/middlewared/middlewared/api/v27_0_0/app_registry.py
+135-774 files not shown
+143-7910 files

LLVM/project ee88788llvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction avgfloor-ceil.ll

[LoongArch] Set `avg{floor/ceil}{s/u}` as legal for lsx and lasx

Suggested-by: tangaac <tangyan01 at loongson.cn>
Link: https://github.com/llvm/llvm-project/pull/161079#issuecomment-3420763377
DeltaFile
+16-64llvm/test/CodeGen/LoongArch/lasx/ir-instruction/avgfloor-ceil.ll
+16-64llvm/test/CodeGen/LoongArch/lsx/ir-instruction/avgfloor-ceil.ll
+8-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+4-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+4-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+48-1285 files

LLVM/project 8b3eac0llvm/lib/Target/DirectX/DXILWriter DXILBitcodeWriter.cpp, llvm/test/tools/dxil-dis di-compile-unit-versioned-language.ll

[DirectX] Convert DICompileUnit versioned language (#192574)

Versioned languages did not exist in LLVM 3.7.
DeltaFile
+13-0llvm/test/tools/dxil-dis/di-compile-unit-versioned-language.ll
+8-1llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
+21-12 files

LLVM/project eb6eb9fllvm/lib/Target/DirectX DXILPrepare.cpp, llvm/test/tools/dxil-dis debug-info.ll

[DirectX] Convert debug values to old style (#192162)
DeltaFile
+0-2llvm/test/tools/dxil-dis/debug-info.ll
+2-0llvm/lib/Target/DirectX/DXILPrepare.cpp
+2-22 files

OPNSense/core 2134ce2src/opnsense/mvc/script run_validations.php

mvc: remove unused import
DeltaFile
+0-2src/opnsense/mvc/script/run_validations.php
+0-21 files

LLVM/project 6114cbbllvm/lib/Target/DirectX/DXILWriter DXILValueEnumerator.cpp

[DirectX] Fix debug dump of ValueEnumerator (#191251)

Consistently print to OS, and do not try to print uses of values without
a use list.
DeltaFile
+16-12llvm/lib/Target/DirectX/DXILWriter/DXILValueEnumerator.cpp
+16-121 files

OPNSense/core fe6a530src/opnsense/mvc/app/views/OPNsense/Auth priv.volt

System: Access: Privileges: remove add/delete from page

(cherry picked from commit 3c5ae0f3b3d72e15efd852061a77d85c43bc3d74)
DeltaFile
+3-3src/opnsense/mvc/app/views/OPNsense/Auth/priv.volt
+3-31 files

OPNSense/core 383c5e9src/opnsense/scripts/system sysctl.py

system: only split first colon when reading sysctls

(cherry picked from commit 293e645d89edb53c7f3fd2388740f28f5ec50346)
(cherry picked from commit 791cc6f573a0b67808c7189544890c43c700f17f)
DeltaFile
+1-1src/opnsense/scripts/system/sysctl.py
+1-11 files

OPNSense/core 6ef039fMk git.mk

make: prevent error in new vim grepping step

(cherry picked from commit ea6f7103f1e27126abb3552cf30819c032b4549e)
DeltaFile
+1-1Mk/git.mk
+1-11 files

LLVM/project 6c16fc8lldb/test/API/commands/command/invalid-args TestInvalidArgsCommand.py, lldb/test/API/commands/frame/recognizer TestFrameRecognizer.py

[lldb][test] Remove full stop from expected error messages (#193748)

I am about to update a bunch of uses of AppendErrorWithFormat to not
have a full stop at the end, to confirm to
https://llvm.org/docs/CodingStandards.html#error-and-warning-messages.

Reviewing all those changes is going to be difficult so I am updating
the tests first and then we can land the other changes in batches
(because the tests will continue to pass as we do that).

Note that I have only run the test suite on Linux AArch64, so there are
probably more that need to be updated. We will catch those in CI or
post-commit.
DeltaFile
+10-10lldb/test/API/commands/frame/recognizer/TestFrameRecognizer.py
+2-4lldb/test/API/commands/log/invalid-args/TestInvalidArgsLog.py
+3-3lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
+2-4lldb/test/API/commands/command/invalid-args/TestInvalidArgsCommand.py
+3-3lldb/test/API/commands/process/signal/TestProcessSignal.py
+2-2lldb/test/API/commands/register/register_command/TestRegisters.py
+22-2612 files not shown
+39-4318 files

FreeBSD/src eb837cbusr.sbin/ctld login.cc

ctld: normalize iSCSI TargetName on login

Case-insensitive TargetName matching on logins was accidentally removed,
let's fix that by normalizing TargetName again according to RFC 3722.

PR:                     294522
Fixes:                  4b1aac931465f39c5c26bfa1d5539a428d340f20
Sponsored by:           ConnectWise
MFC after:              1 week
Reviewed by:            asomers, jhb
Approved by:            asomers (mentor)
Differential Revision:  https://reviews.freebsd.org/D56469
DeltaFile
+8-2usr.sbin/ctld/login.cc
+8-21 files

LLVM/project 248192dllvm/test/CodeGen/RISCV/rvv vector-interleave-fixed.ll fixed-vectors-shuffle-deinterleave2.ll

[RISCV] Add bf16 tests for interleave and deinterleave (#193720)

Add missing bf16 tests for interleave and deinterleave
DeltaFile
+744-8llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+212-6llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+210-4llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+32-6llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
+1,198-244 files

LLVM/project c9ed309llvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction sub.ll add.ll

[LoongArch] Add support for vector add/sub on vNi128 types

Legalize ADD/SUB for v1i128 and v2i128 and extend LSX/LASX instruction
selection patterns to support the Q element size. Update register classes
to include vNi128 types and add codegen tests to verify lowering to
VADD.Q/XVADD.Q and VSUB.Q/XVSUB.Q.
DeltaFile
+6-102llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+6-93llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+6-43llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+6-42llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+17-4llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+17-4llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+58-2882 files not shown
+66-2928 files

FreeBSD/ports 89a9f4fdevel/mimalloc distinfo Makefile

devel/mimalloc: Update to 3.3.1
DeltaFile
+3-3devel/mimalloc/distinfo
+1-1devel/mimalloc/Makefile
+4-42 files

FreeNAS/freenas caecd89src/middlewared/middlewared/api/v27_0_0 app_image.py, src/middlewared/middlewared/plugins/apps_images __init__.py update_alerts.py

Convert app.image service to be typesafe
DeltaFile
+132-0src/middlewared/middlewared/plugins/apps_images/__init__.py
+57-55src/middlewared/middlewared/plugins/apps_images/update_alerts.py
+0-106src/middlewared/middlewared/plugins/apps_images/images.py
+78-0src/middlewared/middlewared/plugins/apps_images/query.py
+34-23src/middlewared/middlewared/api/v27_0_0/app_image.py
+57-0src/middlewared/middlewared/plugins/apps_images/pull.py
+358-18418 files not shown
+524-25124 files

LLVM/project 6e6fbd4llvm/test/CodeGen/LoongArch/lasx/ir-instruction sub.ll add.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction add.ll sub.ll

[LoongArch][NFC] Add tests for vector add on vNi128
DeltaFile
+108-2llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+99-2llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+49-2llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+48-2llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+304-84 files

LLVM/project e4f1530flang/include/flang/Optimizer/Dialect FIROps.td, flang/lib/Optimizer/CodeGen CodeGen.cpp

[flang][debug] generate llvm.fake.use for arguments at -g and O0 (#187044)

Fix for https://github.com/llvm/llvm-project/issues/185432.

This patch extends the lifetime of procedure dummy arguments using llvm.fake.use
so that they are accessible in debugger during the whole lifetime of the function.

This is done by:
- adding a new fir.fake_use operation and emitting it in AddDebugInfo.cpp for
   dummy arguments at the end of the procedure scope.
- lower this new fir.fake_use to the llvm.fake.use intrinsic.

This is done under -g at O0 only to avoid pessimizing the generated code when
optimizations are requested.
DeltaFile
+56-0flang/test/Transforms/debug-fake-use.fir
+27-14flang/lib/Optimizer/CodeGen/CodeGen.cpp
+20-1flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
+12-0flang/test/Fir/fake_use-codegen.fir
+10-0flang/include/flang/Optimizer/Dialect/FIROps.td
+8-0flang/lib/Optimizer/Passes/Pipelines.cpp
+133-151 files not shown
+137-177 files

LLVM/project fc9f14elibc/test CMakeLists.txt, libc/test/include CMakeLists.txt

[libc] Switch check-libc from CTest to lit (#193798)

Renamed check-libc-lit to check-libc, replacing the old CTest-driven
target. Dependencies now use -build targets (e.g.
libc-hermetic-tests-build) so that check-libc only builds test
executables and delegates execution to lit.
DeltaFile
+7-10libc/test/CMakeLists.txt
+1-2libc/test/integration/CMakeLists.txt
+1-2libc/test/include/CMakeLists.txt
+9-143 files

LLVM/project 65e766dlibc/cmake/modules prepare_libc_gpu_build.cmake, libc/test lit.site.cfg.py.in

[libc] Honour LIBC_GPU_TEST_JOBS in lit test runs (#193797)

Under CTest, LIBC_GPU_TEST_JOBS controlled a ninja job pool that limited
concurrent GPU test processes. The AMD GPU buildbot sets this to 4 to
avoid overloading the GPU driver.

When running tests via lit, this constraint was lost because lit uses
its own -j flag (defaulting to nproc, or set to 64 on the AMD bot via
LLVM_LIT_ARGS). All GPU loader processes launched simultaneously,
leading to hangs from GPU resource exhaustion.

Propagated LIBC_GPU_TEST_JOBS into the lit site config as a parallelism
group so lit throttles GPU test concurrency independently of the global
-j setting.
DeltaFile
+5-0libc/test/lit.site.cfg.py.in
+1-0libc/cmake/modules/prepare_libc_gpu_build.cmake
+6-02 files

LLVM/project 7758ee5libc/test/src/time mktime_test.cpp

[libc] Fix implicit conversion warning in mktime_test (#193504)

Specified template argument time_t for Succeeds and Fails in
mktime_test.cpp to avoid implicit conversion warnings when matching
time_t results on 64-bit systems.
DeltaFile
+53-41libc/test/src/time/mktime_test.cpp
+53-411 files

LLVM/project eecfc9bllvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing alias-load-store-atomic.ll

[SPIRV] Do not add aliasing decorations to OpAtomicStore/OpAtomicLoad
DeltaFile
+6-19llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+4-9llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-load-store-atomic.ll
+10-282 files

LLVM/project 0d33284llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp SPIRVISelLowering.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing alias-load-store-atomic.ll

[SPIRV] Lower load/store atomic to OpAtomicLoad/OpAtomicStore (#185696)

Lower LLVM's `load atomic` `store atomic` as `OpAtomicStore` and
`OpAtomicLoad`.

Closes #185629
DeltaFile
+111-7llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+36-15llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+28-19llvm/test/CodeGen/SPIRV/transcoding/load-atomic.ll
+28-19llvm/test/CodeGen/SPIRV/transcoding/store-atomic.ll
+41-0llvm/test/CodeGen/SPIRV/transcoding/atomic-load-store-unsupported.ll
+30-7llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-load-store-atomic.ll
+274-674 files not shown
+310-7410 files

LLVM/project b548387llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize first-order-recurrence-tail-folding.ll optsize.ll

[LV] Simplify live-out extraction for first-order recurrence phis when tail folding (#176108)

The idea is similar to ba40a7bc2e65be86ac23c9cf6038ac085dda77eb. Due to
tail folding, the recurrence vector in the final iteration may contain
only a single active element, making it impossible to extract the
penultimate active element. This patch instead directly extracts the
last active element from the vector produced by splicing the recurrence
phi and the previous value, without needing to select which value to
extract based on the number of active lanes.
DeltaFile
+19-41llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
+10-25llvm/test/Transforms/LoopVectorize/optsize.ll
+0-27llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+10-10llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
+1-8llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
+1-8llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
+41-1196 files

LLVM/project e789f1allvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lsx/ir-instruction fptrunc.ll

avoid regression
DeltaFile
+20-7llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+4-8llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
+24-152 files

FreeBSD/ports e09e749devel/log4j Makefile

devel/log4j: expire in 3 months

Superseded by devel/apache-log4j2.

This port was already deprecated.
Expire together with databases/mysql-connector-java51, the only
user of log4j in the ports tree.

Approved-by:    no maintainer
DeltaFile
+2-1devel/log4j/Makefile
+2-11 files

FreeBSD/ports 20c9c6adatabases/mysql-connector-java51 Makefile

databases/mysql-connector-java51: unpin openjdk8 and deprecate

The build only needed to be less strict in javadoc to compile with modern JDK.

Deprecation:
- superseded by databases/mysql-connector-j
- mysql 5.1 is not in the ports tree anymore
- no users of this port in the tree anymore
- this is the only port keeping deprecated log4j in the ports tree
- this port only copies a jar. There are better ways to get a plain jar
  in your Java project.
- the original reason for this port was "to provide continued support for
  Java 1,6 and 1.7 users". Java 6 and 7 are removed from the ports tree
  in 2016 and 2023.

NB: removed the run depends on java. It is just a library. The final application
will decide the Java version it runs on. No need to install an extra JDK.

PR:     294389
Approved-by:    maintainer timeout (ultima@)
DeltaFile
+6-3databases/mysql-connector-java51/Makefile
+6-31 files