LLVM/project 95453e6flang/lib/Semantics check-omp-structure.cpp

format
DeltaFile
+2-1flang/lib/Semantics/check-omp-structure.cpp
+2-11 files

LLVM/project 0f4b1e1llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-trunc-stores.ll

[AArch64] Address issue reported in PR#196029 (#199122)

For certain types of truncating stores, the lowering action is set to
custom although no custom lowering exists for them.

This patch addresses issue reported in PR #196029 by removing the custom lowering entry.
DeltaFile
+26-0llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
+0-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+26-12 files

LLVM/project a4d841dclang/tools/cir-translate cir-translate.cpp CMakeLists.txt

handle cir-translate
DeltaFile
+3-3clang/tools/cir-translate/cir-translate.cpp
+1-1clang/tools/cir-translate/CMakeLists.txt
+4-42 files

FreeNAS/freenas 883227csrc/middlewared/middlewared/pytest/unit/plugins/vm test_suspend_vms.py

ruff format
DeltaFile
+23-20src/middlewared/middlewared/pytest/unit/plugins/vm/test_suspend_vms.py
+23-201 files

FreeNAS/freenas e31fdc1src/middlewared/middlewared/plugins zettarepl.py, src/middlewared/middlewared/plugins/vm vm_lifecycle.py

save VM context before suspending so that it is still resumed if `suspend_vms` fails/times out
DeltaFile
+17-4src/middlewared/middlewared/plugins/zettarepl.py
+1-1src/middlewared/middlewared/plugins/vm/vm_lifecycle.py
+18-52 files

LLVM/project abf77feclang/test/CodeGen scoped-atomic-ops.c, clang/test/CodeGenCUDA atomic-options.hip

Merge branch 'users/hvdijk/dxilprettyprinter-ir-printing' into users/hvdijk/directx-delay-converting-debug-info
DeltaFile
+1,547-723llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+1,521-697llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+568-852clang/test/CodeGen/scoped-atomic-ops.c
+867-373llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+144-216clang/test/CodeGenCUDA/atomic-options.hip
+256-63llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
+4,903-2,924131 files not shown
+8,662-4,283137 files

LLVM/project de2cf58clang/test/CodeGen scoped-atomic-ops.c, clang/test/CodeGenCUDA atomic-options.hip

Merge branch 'main' into users/hvdijk/dxilprettyprinter-ir-printing
DeltaFile
+1,547-723llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+1,521-697llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+568-852clang/test/CodeGen/scoped-atomic-ops.c
+867-373llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+144-216clang/test/CodeGenCUDA/atomic-options.hip
+256-63llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
+4,903-2,924131 files not shown
+8,662-4,283137 files

LLVM/project 0cea23aclang/test/Driver hipspv-toolchain.hip

[HIP] Fix another test for --no-lto (#201382)
DeltaFile
+2-1clang/test/Driver/hipspv-toolchain.hip
+2-11 files

LLVM/project 2d249cdllvm/docs GettingInvolved.rst

Remove incorrect gcal link from C/C++ language wg (#201374)

The C and C++ language working group meets on the first and third Wed of
the month, but Google Calendar does not support doing this via a single
event. Instead, we have one event for recurring on the 1st Wed and a
second event for recurring on the 3rd Wed. That means we cannot use a
single gcal link for the event. Instead of listing two links, this
removes the gcal link entirely because the meeting is also listed on the
community calendar itself. This reduces confusion for folks, but it
would be nice to get a replacement link at some point.
DeltaFile
+1-1llvm/docs/GettingInvolved.rst
+1-11 files

LLVM/project 12f60d0llvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp

[AMDGPU] Remove unneeded early outs in getDivNumBits. NFC. (#201366)
DeltaFile
+0-4llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+0-41 files

LLVM/project e97e676lldb/test/API/macosx/expedited-thread-pcs TestExpeditedThreadPCs.py

[lldb/test] Fix TestExpeditedThreadPCs on remote-darwin targets (#201275)
DeltaFile
+5-1lldb/test/API/macosx/expedited-thread-pcs/TestExpeditedThreadPCs.py
+5-11 files

LLVM/project 8ae895allvm/lib/Target/NVPTX NVPTXISelLowering.cpp, llvm/test/CodeGen/NVPTX atomicrmw-sm60.ll atomicrmw-sm70.ll

[NVPTX] Respect FTZ flag when lowering atomicrmw fadd. (#200732)

Previously we unconditionally lowered LLVM atomicrmw fadd to PTX
atom.add.  This is incorrect, because it ignores the FTZ behavior of the
LLVM and PTX instructions.
DeltaFile
+1,547-723llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+1,521-697llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+867-373llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+105-0llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
+54-12llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+26-8llvm/test/CodeGen/NVPTX/atomics.ll
+4,120-1,8131 files not shown
+4,128-1,8147 files

FreeBSD/src ce243dfsys/conf kern.post.mk, sys/i386/i386 genassym.c

i386: Fix build (of 'genassym.o')

i386's genassym.c needs to define some assembly symbols holding the size
of NFS structures to support NFS_ROOT while booting with a nfs_diskless
structure.  For this, it needs to include a few NFS headers, which
require definitions from <sys/mount.h> (fhandle_t, vfs_init_t), which
was removed by commit 72ab129799a2 ("x86: remove sys/mount.h from
genassym.c").

Since recently, <sys/mount.h> has been including <sys/vnode.h>, so needs
"vnode_if.h" to have been generated for the compilation of 'genassym.o'
not to fail.  Make sure this is the case (for all architectures for
simplicity) by tweaking the rule for 'genassym.o' in
'sys/conf/kern.post.mk', leaving a comment there so that it can be
removed when i386 is dropped (or if the above-mentioned dependency is
broken).

Fixes:          72ab129799a2 ("x86: remove sys/mount.h from genassym.c")
Sponsored by:   The FreeBSD Foundation
DeltaFile
+4-1sys/conf/kern.post.mk
+1-0sys/i386/i386/genassym.c
+5-12 files

LLVM/project 582d2fdllvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange function-attr.ll call-instructions.ll

[LoopInterchange] Bail out if function that may diverge is called (#201348)

This patch fixes the issue pointed out in
https://github.com/llvm/llvm-project/pull/200828#issuecomment-4593914293.
As demonstrated by the test cases added in #201331, it is not legal to
interchange loops that contain call instructions which may diverge. This
patch adds an additional check and bails out early when we cannot prove
that a call instruction in the loops doesn't diverge.
DeltaFile
+16-40llvm/test/Transforms/LoopInterchange/function-attr.ll
+7-3llvm/test/Transforms/LoopInterchange/call-instructions.ll
+4-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+27-453 files

NetBSD/src aHsRtcSsys/miscfs/genfs genfs_io.c

   genfs_do_io: fix a pagedaemon deadlock

   this should fix the following panic i observed on my machine.

   ```
   panic: out of memory before the pagedaemon thread exists
   cpu0: Begin traceback...
   vpanic() at netbsd:vpanic+0x189
   panic() at netbsd:panic+0x3c
   uvm_wait() at netbsd:uvm_wait+0xa5
   uvm_km_kmem_alloc() at netbsd:uvm_km_kmem_alloc+0x21b
   pool_page_alloc() at netbsd:pool_page_alloc+0x2c
   pool_grow() at netbsd:pool_grow+0x367
   pool_get() at netbsd:pool_get+0x9f
   pool_cache_get_slow() at netbsd:pool_cache_get_slow+0x136
   pool_cache_get_paddr() at netbsd:pool_cache_get_paddr+0x256
   getiobuf() at netbsd:getiobuf+0x23
   genfs_do_io() at netbsd:genfs_do_io+0xde
   genfs_gop_write() at netbsd:genfs_gop_write+0x52

    [5 lines not shown]
VersionDeltaFile
1.106+12-4sys/miscfs/genfs/genfs_io.c
+12-41 files

LLVM/project aa8e38fopenmp/module CMakeLists.txt

[OpenMP] FIx omp_lib.mod compilation for the GPU (#201377)
DeltaFile
+6-0openmp/module/CMakeLists.txt
+6-01 files

NetBSD/src ADyxF8csys/uvm uvm_swap.c

   sw_reg_strategy: fix a pagedaemon deadlock

   this should fix the following panic i observed on my machine.

   ```
   panic: out of memory before the pagedaemon thread exists
   cpu0: Begin traceback...
   vpanic() at netbsd:vpanic+0x189
   panic() at netbsd:panic+0x3c
   uvm_wait() at netbsd:uvm_wait+0xa5
   uvm_km_kmem_alloc() at netbsd:uvm_km_kmem_alloc+0x21b
   pool_page_alloc() at netbsd:pool_page_alloc+0x2c
   pool_grow() at netbsd:pool_grow+0x367
   pool_get() at netbsd:pool_get+0x9f
   pool_cache_get_slow() at netbsd:pool_cache_get_slow+0x136
   pool_cache_get_paddr() at netbsd:pool_cache_get_paddr+0x256
   getiobuf() at netbsd:getiobuf+0x23
   swstrategy() at netbsd:swstrategy+0x25a
   bdev_strategy() at netbsd:bdev_strategy+0x83

    [6 lines not shown]
VersionDeltaFile
1.233+7-3sys/uvm/uvm_swap.c
+7-31 files

LLVM/project 5816ef1cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers ScriptDebuggerController.py, cross-project-tests/debuginfo-tests/dexter/dex/evaluation RunMatch.py Metrics.py

[Dexter] Add basic result evaluation for structured scripts (#198803)

This patch adds evaluation for structured scripts, completing the
features required to run simple Dexter tests using structured scripts.
The basic output from these evaluations is a list of named metrics
aggregating the results of evaluating !value nodes. The verbose output
gives a per-step summary of the results for each expect node active at
that step.

Most of the new functionality is in the evaluation/ dir, which has also
absorbed some functionality previously stored in the
ScriptDebuggerController for matching !where nodes to a debugger StepIR,
as this is logic which is common to both managing a debugger session and
evaluating the end result.
DeltaFile
+162-0cross-project-tests/debuginfo-tests/dexter/dex/evaluation/RunMatch.py
+140-0cross-project-tests/debuginfo-tests/dexter/dex/evaluation/Metrics.py
+94-0cross-project-tests/debuginfo-tests/dexter/dex/evaluation/StateMatch.py
+4-82cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers/ScriptDebuggerController.py
+57-17cross-project-tests/debuginfo-tests/dexter/dex/tools/test/Tool.py
+42-0cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/evaluation/basic_evaluate.cpp
+499-994 files not shown
+575-9910 files

LLVM/project 05e8d9fllvm/include/llvm/IR AssemblyAnnotationWriter.h, llvm/lib/IR AsmWriter.cpp

[AsmWriter] Add emitMDNodeAnnot (#198317)

Similarly to the other AAW::emit*Annot functions, this may be used to
emit a comment before a metadata node.
DeltaFile
+5-0llvm/include/llvm/IR/AssemblyAnnotationWriter.h
+3-0llvm/lib/IR/AsmWriter.cpp
+8-02 files

FreeNAS/freenas 1120811src/middlewared/middlewared/api/v26_0_0 zfs_tier.py, src/middlewared/middlewared/plugins/zfs tier.py

NAS-141235 / 26.0.0-RC.1 / Fix ZFS tiering event subscription (by anodos325) (#19055)

During the course of development in our design documents subscriptions
shifted from being locked into dataset names to being locked into the
tier job id, which is dataset_name at uuid.

Original PR: https://github.com/truenas/middleware/pull/19054

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+23-21src/middlewared/middlewared/plugins/zfs/tier.py
+16-0tests/unit/test_zfs_tier_api_models.py
+4-4src/middlewared/middlewared/api/v26_0_0/zfs_tier.py
+4-4tests/api2/zfs_tier/test_jobs_extended.py
+3-2tests/api2/zfs_tier/test_smoke.py
+50-315 files

LLVM/project d307ba0llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp TargetLowering.cpp

[DAGCombiner] Remove untested vp_fma combines. (#201239)

RISC-V no longer uses vp_fma in SelectionDAG leaving these combines
untested.

This effectively reverts 2fe2a6d4b8a4647e49d69a5ff7161946aeb7cee1.
DeltaFile
+28-35llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+1-1llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+29-362 files

LLVM/project 88f72dbllvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge branch 'main' into users/aokblast/moneypunct_fbsd_test
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+583,792-20,92327,028 files not shown
+3,074,222-1,046,95427,034 files

FreeNAS/freenas 12feee6src/middlewared/middlewared/api/v26_0_0 zfs_tier.py, src/middlewared/middlewared/plugins/zfs tier.py

NAS-141236 / 27.0.0-BETA.1 / Fix ZFS tiering event subscription (#19054)

During the course of development in our design documents subscriptions
shifted from being locked into dataset names to being locked into the
tier job id, which is dataset_name at uuid.

(cherry picked from commit 3a765d25fab254f95636b61ad8de00b2f9bed9a4)
DeltaFile
+23-21src/middlewared/middlewared/plugins/zfs/tier.py
+16-0tests/unit/test_zfs_tier_api_models.py
+4-4src/middlewared/middlewared/api/v26_0_0/zfs_tier.py
+4-4tests/api2/zfs_tier/test_jobs_extended.py
+3-2tests/api2/zfs_tier/test_smoke.py
+50-315 files

LLVM/project fdf8fb6flang/lib/Semantics resolve-directives.cpp, flang/test/Lower/OpenACC acc-routine-multi-name.f90 acc-module-definition-multi-name.f90

[flang][openacc] add extension which accepts multiple names in a OpenACC routine directive (#200296)

This PR adds an extension which allows one or more function names in a
single named routine directive. This is treated as multiple named
routine directives with the same clauses. The bind clause is forbidden.
The empty list of names isn't excepted. Routine clauses are stable under
unparsing.

This PR tests Parsing, Unparsing, Semantics, and Lowering.
DeltaFile
+55-0flang/test/Parser/acc-routine-empty-parens.f90
+52-0flang/test/Lower/OpenACC/acc-routine-multi-name.f90
+47-0flang/test/Semantics/OpenACC/acc-routine-multi-name.f90
+44-0flang/test/Lower/OpenACC/acc-module-definition-multi-name.f90
+42-0flang/test/Semantics/OpenACC/acc-routine-multi-name-disabled.f90
+29-8flang/lib/Semantics/resolve-directives.cpp
+269-811 files not shown
+316-1417 files

LLVM/project f1b42dcllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize early_exit_with_stores.ll scalarized_conditional_ops_uncountable_exits.ll

[LV] Vectorize early exit loops with stores using masking (#178454)

This is an alternative approach to vectorizing early exit loops with
stores that avoids needing to add an extra check block. This is a
fairly straightforward approach that should work on vector ISAs
supporting masked memory ops.

The basic approach is to create a mask covering all lanes _before_ any
exiting lane, using cttz.elts and active.lane.mask (which sets all lanes
to true if the uncountable exit wasn't taken). If the uncountable exit
was taken, then there will still be one scalar iteration left to perform
after the vector loop, which will also handle which exit block we should
branch to.

We no longer need to advance exit conditions in the vector body to the
next iteration (compared to the other PR), though we still need to move
the recipes needed to generate the exit condition (depending on which
memory operations are first in the loop).


    [56 lines not shown]
DeltaFile
+256-63llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
+209-31llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+178-49llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
+168-39llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
+193-11llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+132-0llvm/test/Transforms/LoopVectorize/scalarized_conditional_ops_uncountable_exits.ll
+1,136-1939 files not shown
+1,411-22915 files

FreeNAS/freenas 3a765d2src/middlewared/middlewared/api/v26_0_0 zfs_tier.py, src/middlewared/middlewared/api/v27_0_0 zfs_tier.py

NAS-141235 / 27.0.0-BETA.1 / Fix ZFS tiering event subscription (#19054)

During the course of development in our design documents subscriptions
shifted from being locked into dataset names to being locked into the
tier job id, which is dataset_name at uuid.
DeltaFile
+23-21src/middlewared/middlewared/plugins/zfs/tier.py
+16-0tests/unit/test_zfs_tier_api_models.py
+4-4src/middlewared/middlewared/api/v27_0_0/zfs_tier.py
+4-4tests/api2/zfs_tier/test_jobs_extended.py
+4-4src/middlewared/middlewared/api/v26_0_0/zfs_tier.py
+3-2tests/api2/zfs_tier/test_smoke.py
+54-356 files

LLVM/project ad58ae7llvm/lib/Target/AArch64 AArch64RegisterInfo.td SMEInstrFormats.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to 0 <= Zn <= 7

The `luti6` instruction (table, four registers, 8-bit) should only
allow `0 <= Zn <= 7`, since there's only 3 bits. It actually allows:
```
   luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
   luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```

Fix tablegen to ensure Zn is only allowed in correct range of 0 to 7.
DeltaFile
+15-0llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+5-0llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s
+4-0llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+1-1llvm/lib/Target/AArch64/SMEInstrFormats.td
+25-14 files

LLVM/project 2f323c0llvm/lib/Target/AArch64 AArch64RegisterInfo.td

fixup! Address CR comments
DeltaFile
+10-19llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+10-191 files

LLVM/project 4a8c5d2clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-2velem.c v8.2a-neon-intrinsics.c

[CIR][AArch64] Lower vfmaq_lane_v and vfma_laneq_v (#197084)

Lower BI__builtin_neon_vfmaq_lane_v and BI__builtin_neon_vfma_laneq_v in
CIR.

This handles the covered vfmaq_lane_* and vfma_laneq_* ACLE wrappers by
bitcasting operands to the expected types, selecting the requested lane
from the lane source operand, and emitting fma through
emitCallMaybeConstrainedBuiltin.

For vfmaq_lane_v, the selected lane is splatted with emitNeonSplat.
For vfma_laneq_v, the lane is selected from the wider lane source; the
f64 case extracts the scalar lane before emitting scalar fma.

Neighboring scalar lane/laneq wrappers and other out-of-scope forms
remain explicit NYI cases.

Tests are moved into the existing CIR-enabled fused multiply files under
clang/test/CodeGen/AArch64/neon/, reusing upstream LLVM checks where

    [3 lines not shown]
DeltaFile
+109-1clang/test/CodeGen/AArch64/neon/fused-multiply.c
+0-96clang/test/CodeGen/AArch64/neon-2velem.c
+50-2clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+45-2clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c
+0-40clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
+0-23clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
+204-1646 files

LLVM/project f78d2a6llvm/lib/Target/AArch64 AArch64RegisterInfo.td SMEInstrFormats.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Address more CR comments
DeltaFile
+6-8llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+10-1llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+2-2llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+1-1llvm/lib/Target/AArch64/SMEInstrFormats.td
+19-124 files