LLVM/project 24bee56llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-dyn-stackalloc.mir regbankselect-widen-scalar-loads.mir

[AMDGPU][GISel] Rename amdgpu-regbankselect amdgpu-reg-bank-select

To be more consistent with reg-bank-select and other passes that are
hyphenated rather than concatenated.

Reviewers: arsenm, vikramRH, aeubanks

Pull Request: https://github.com/llvm/llvm-project/pull/217487
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
+17-17158 files not shown
+186-186164 files

LLVM/project 5432914flang/test/Integration/PowerPC ppc-vec-shift-be-le.f90 ppc-mma-outer-product-1.f90, flang/test/Lower/PowerPC ppc-mma-outer-product-1.f90

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+2,569-0llvm/test/CodeGen/AMDGPU/redundant-and.mir
+0-2,191llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
+0-1,763llvm/test/Analysis/CostModel/RISCV/cast.ll
+1,709-0flang/test/Integration/PowerPC/ppc-mma-outer-product-1.f90
+0-1,701flang/test/Lower/PowerPC/ppc-mma-outer-product-1.f90
+1,420-0flang/test/Integration/PowerPC/ppc-vec-shift-be-le.f90
+5,698-5,655996 files not shown
+35,764-30,6451,002 files

LLVM/project 10a1fe8llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-whole-wave-functions.mir regbankselect-mad_64_32.mir, llvm/test/CodeGen/X86/GlobalISel regbankselect-x87.ll

[GISel] Rename regbankselect reg-bank-select

To be more consistent with other pass names, use hypens between the
words. Noticed this when I went to do a NewPM porting.

Reviewers: aeubanks, arsenm, vikramRH

Pull Request: https://github.com/llvm/llvm-project/pull/217486
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
+2-2llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll
+20-20198 files not shown
+266-266204 files

FreeNAS/freenas 95d96eetests/sharing_protocols/nvmet test_nvmet_tcp.py

Add unit test TestAllowAnyHostToggle

(cherry picked from commit 7e1177b47b1f80f7ff4c2692ddf84e617d8f64db)
DeltaFile
+93-0tests/sharing_protocols/nvmet/test_nvmet_tcp.py
+93-01 files

FreeNAS/freenas a7bb96fsrc/middlewared/middlewared/utils/nvmet kernel.py

Permit allow_any_host to be toggled off

(cherry picked from commit eee4aecf624e2339129d6012f948dd2ecee9d0ee)
DeltaFile
+16-0src/middlewared/middlewared/utils/nvmet/kernel.py
+16-01 files

FreeNAS/freenas 1e98ac7src/middlewared/middlewared/utils/nvmet kernel.py, tests/sharing_protocols/nvmet test_nvmet_tcp.py

NAS-141762 / 27.0.0-BETA.1 / Permit allow_any_host to be toggled (#19521)

- Permit `allow_any_host` to be toggled off for a NVMe-oF subsystem
- Add unit test
`TestAllowAnyHostToggle::test__allow_any_host_toggle_with_active_host_link`.
DeltaFile
+93-0tests/sharing_protocols/nvmet/test_nvmet_tcp.py
+16-0src/middlewared/middlewared/utils/nvmet/kernel.py
+109-02 files

LLVM/project 5fff9d0clang/include/clang/Basic BuiltinsAMDGPUDocs.td BuiltinsAMDGPU.td, llvm/include/llvm/IR IntrinsicsAMDGPU.td

[NFC][AMDGPU] Introduce a new target feature for N=16 WMMAs
DeltaFile
+30-28llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+28-28clang/include/clang/Basic/BuiltinsAMDGPU.td
+20-0clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+10-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+7-1llvm/lib/Target/AMDGPU/AMDGPU.td
+95-625 files

LLVM/project 5298e75llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp, llvm/test/CodeGen/AArch64 extract-subvec-combine.ll

[GlobalISel] Add G_EXTRACT_SUBVECTOR to computeNumSignBits (#216798)

Port the SDAG EXTRACT_SUBVECTOR computeNumSignBits handling to
GlobalISel. Offsets the demanded elements by the subvector index to
propagate sign bits from the source vector to the extracted subvector.
For scalable vectors, conservatively demands all elements.

Part of #150515.
DeltaFile
+51-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-extract-subvector.mir
+10-25llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
+14-0llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+75-253 files

LLVM/project 4787504clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 poly64.c neon-vget.c

[CIR][AArch64] Lower NEON set vector lane intrinsics (#217198)

### summary

part of : https://github.com/llvm/llvm-project/issues/185382

Lower all intrinsics in
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#set-vector-lane

Assisted by : DeepSeek V4 Pro Max
DeltaFile
+312-0clang/test/CodeGen/AArch64/neon/getset.c
+0-195clang/test/CodeGen/AArch64/neon-vget.c
+1-24clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
+0-20clang/test/CodeGen/AArch64/poly64.c
+5-5clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+318-2445 files

OPNSense/core 5423ae8src/opnsense/mvc/app/views/OPNsense/Auth user.volt

system: approximate user being expired in the grid

This would only be correct if the backend gave us a
definitive expired message based on the time zone.
The historic issue is that the expiration no longer
sets disabled, but it's still a useful visual clue.

PR: https://forum.opnsense.org/index.php?topic=52759.0
DeltaFile
+7-1src/opnsense/mvc/app/views/OPNsense/Auth/user.volt
+7-11 files

OPNSense/core c7d3bd9src/opnsense/www/js opnsense_theme.js

ui: fix condition to check sidebar toggle loading (#10743)

Changed the sidebar guard from && to || so it aborts when either the CSS
or the navigation element is missing.
DeltaFile
+1-1src/opnsense/www/js/opnsense_theme.js
+1-11 files

NetBSD/pkgsrc qIjXdNVdoc CHANGES-2026

   doc: Updated sysutils/uutils-coreutils to 0.10.0nb1
VersionDeltaFile
1.5421+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc yWrV2Glsysutils/uutils-coreutils Makefile cargo-depends.mk

   sysutils/uutils-coreutils: import security fix

   Pull the package sources from unreleased git-hash https://github.com/sylvestre/coreutils/commit/dba580dc057007bc153098b7a5aac3f0bd9aeea7
   in order to fix the reported security issue in https://github.com/uutils/coreutils/issues/13939

   Bump package revison.
VersionDeltaFile
1.4+328-313sysutils/uutils-coreutils/distinfo
1.4+108-103sysutils/uutils-coreutils/cargo-depends.mk
1.4+3-1sysutils/uutils-coreutils/Makefile
+439-4173 files

NetBSD/pkgsrc-wip a1ff0c3rtl-sdr-git TODO DESCR, rtl-sdr-git/patches patch-src_rtl__fm_c

rtl-sdr-git: Remove as vastly behind pkgsrc

This was added in 2014 and is no longer useful.
DeltaFile
+0-50rtl-sdr-git/Makefile
+0-26rtl-sdr-git/patches/patch-src_rtl__fm_c
+0-14rtl-sdr-git/PLIST
+0-13rtl-sdr-git/buildlink3.mk
+0-6rtl-sdr-git/TODO
+0-6rtl-sdr-git/DESCR
+0-1152 files not shown
+0-1198 files

NetBSD/pkgsrc xN1pmc0doc CHANGES-2026

   doc: Updated sysutils/dust to 1.2.5
VersionDeltaFile
1.5420+2-1doc/CHANGES-2026
+2-11 files

LLVM/project 1171007llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU materialize-frame-index-sgpr.gfx10.ll frame-index.mir

[AMDGPU] Fix eliminateFrameIndex clobbering a scavenged register (#217470)

Writing the offset into an undefined scavenged register let the
scavenger alias it with another temp and corrupt the address
DeltaFile
+200-8llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+14-14llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+8-8llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
+8-8llvm/test/CodeGen/AMDGPU/frame-index.mir
+230-384 files

NetBSD/pkgsrc Gndb9icsysutils/dust Makefile cargo-depends.mk

   sysutils/dust: update to 1.2.5

    - fix: re-sort types after appending others row
VersionDeltaFile
1.26+226-244sysutils/dust/distinfo
1.20+74-80sysutils/dust/cargo-depends.mk
1.29+4-4sysutils/dust/Makefile
+304-3283 files

FreeBSD/ports 912412cwww/moodle50 Makefile distinfo

www/moodle50: Update to 5.0.9

(cherry picked from commit a8bbf5932b5f861a69165baca8c3304424034907)
DeltaFile
+3-3www/moodle50/distinfo
+1-1www/moodle50/Makefile
+4-42 files

FreeBSD/ports 76a98b7www/moodle51 Makefile distinfo

www/moodle51: Update to 5.1.6

(cherry picked from commit 4095efd8090573ca421f9d7d3086b80765fd23ab)
DeltaFile
+3-3www/moodle51/distinfo
+1-1www/moodle51/Makefile
+4-42 files

FreeBSD/ports 655d7b5www/moodle45 Makefile distinfo

www/moodle45: Update to 4.5.13

(cherry picked from commit ddcdd9566d783798917068087723deda6cac92d3)
DeltaFile
+3-3www/moodle45/distinfo
+1-1www/moodle45/Makefile
+4-42 files

FreeBSD/ports 5f0677awww/moodle52 Makefile distinfo

www/moodle52: Update to 5.2.2

(cherry picked from commit 91eaf818c1b19696face712e1b1add5152fd833f)
DeltaFile
+3-3www/moodle52/distinfo
+1-1www/moodle52/Makefile
+4-42 files

NetBSD/pkgsrc R5ASpHadoc CHANGES-2026

   doc: Updated graphics/simp to 3.11.0
VersionDeltaFile
1.5419+2-1doc/CHANGES-2026
+2-11 files

LLVM/project 78a37f3llvm/utils/gn/secondary/llvm/lib/Target/Lanai BUILD.gn, llvm/utils/gn/secondary/llvm/lib/Target/NVPTX BUILD.gn

[gn] port 050470e75fb67bfb05 (#217603)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/lib/Target/Lanai/BUILD.gn
+4-04 files

NetBSD/pkgsrc iUoLD8tgraphics/simp Makefile cargo-depends.mk

   graphics/simp: update to 3.11.0

    - Update egui and a bunch of others deps
    - Make smooth zoom
    - Add option to sort images in list by different values like name, time and size
    - Fix some text fields being impossible to enter text into
VersionDeltaFile
1.23+727-664graphics/simp/distinfo
1.20+241-220graphics/simp/cargo-depends.mk
1.45+4-4graphics/simp/Makefile
+972-8883 files

FreeBSD/ports 109d711math/unuran Makefile pkg-plist

math/unuran: Update to 1.12.0
DeltaFile
+3-3math/unuran/distinfo
+2-2math/unuran/pkg-plist
+1-1math/unuran/Makefile
+6-63 files

FreeBSD/ports 739856bwww/py-fastapi Makefile distinfo

www/py-fastapi: Update to 0.141.1
DeltaFile
+3-3www/py-fastapi/distinfo
+1-1www/py-fastapi/Makefile
+4-42 files

FreeBSD/ports 4095efdwww/moodle51 Makefile distinfo

www/moodle51: Update to 5.1.6
DeltaFile
+3-3www/moodle51/distinfo
+1-1www/moodle51/Makefile
+4-42 files

FreeBSD/ports a8bbf59www/moodle50 Makefile distinfo

www/moodle50: Update to 5.0.9
DeltaFile
+3-3www/moodle50/distinfo
+1-1www/moodle50/Makefile
+4-42 files

FreeBSD/ports 91eaf81www/moodle52 Makefile distinfo

www/moodle52: Update to 5.2.2
DeltaFile
+3-3www/moodle52/distinfo
+1-1www/moodle52/Makefile
+4-42 files

FreeBSD/ports da1ce84www/tcexam Makefile distinfo

www/tcexam: Update to 17.2.5
DeltaFile
+3-3www/tcexam/distinfo
+1-1www/tcexam/Makefile
+4-42 files