LLVM/project 96113acclang/lib/CodeGen CGExpr.cpp, clang/test/CodeGen ubsan-function-sugared.cpp ubsan-function.cpp

[Clang] Use llvm.ptrmask to mask out thumb bit (#183535)

Use llvm.ptrmask instead of a ptrtoint + and + inttoptr sequence to mask
out the thumb bit.
DeltaFile
+3-7clang/lib/CodeGen/CGExpr.cpp
+1-3clang/test/CodeGen/ubsan-function-sugared.cpp
+1-3clang/test/CodeGen/ubsan-function.cpp
+5-133 files

LLVM/project 037fd6ellvm/lib/Target/AMDGPU VINTERPInstructions.td AMDGPU.td, llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.cpp

[AMDGPU] Add VINTERP encoding to gfx13 (#182481)

DeltaFile
+21-26llvm/lib/Target/AMDGPU/VINTERPInstructions.td
+9-1llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPU.td
+2-0llvm/test/MC/Disassembler/AMDGPU/vinterp.txt
+1-0llvm/test/MC/AMDGPU/vinterp-fake16.s
+34-285 files

OPNSense/core bab283bsrc/opnsense/mvc/app/models/OPNsense/Firewall DNat.xml, src/opnsense/mvc/app/views/OPNsense/Firewall nat_rule.volt

Firewall: NAT: Destination NAT: Allow well known ports in local-port
DeltaFile
+1-0src/opnsense/mvc/app/models/OPNsense/Firewall/DNat.xml
+0-1src/opnsense/mvc/app/views/OPNsense/Firewall/nat_rule.volt
+1-12 files

LLVM/project 86b07a7llvm/test/CodeGen/AArch64 arm64-abi_align.ll machine-outliner.ll

[AArch64] Remove -aarch64-load-store-renaming=true from test. NFC

This is the default nowadays, and can be removed from tests not specific to the
feature.
DeltaFile
+2-2llvm/test/CodeGen/AArch64/arm64-abi_align.ll
+2-2llvm/test/CodeGen/AArch64/machine-outliner.ll
+1-1llvm/test/CodeGen/AArch64/ilp32-va.ll
+1-1llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
+1-1llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
+7-75 files

FreeBSD/ports 2135995devel Makefile, devel/hut Makefile distinfo

devel/hut: Add new port

Hut is a CLI companion utility to interact with sr.ht.

https://git.sr.ht/~xenrox/hut
DeltaFile
+30-0devel/hut/Makefile
+5-0devel/hut/distinfo
+1-0devel/hut/pkg-descr
+1-0devel/Makefile
+37-04 files

LLVM/project c7e1ec9flang/lib/Semantics resolve-directives.cpp, flang/test/Lower/OpenMP task-implicit-firstprivate.f90

[flang][OpenMP] Implicitly capture variables in enclosing task for nested firstprivate (#183770)

Fixes https://github.com/llvm/llvm-project/issues/181271
If a variable is marked firstprivate in a nested task but not actually
used in the outer task body, we still need the outer task to capture it
as firstprivate. Otherwise the nested task can end up pointing to the
parallel region’s stack frame, which might already be gone when the
deferred task runs, causing a use-after-free.
DeltaFile
+25-0flang/test/Lower/OpenMP/task-implicit-firstprivate.f90
+6-0flang/lib/Semantics/resolve-directives.cpp
+31-02 files

FreeBSD/ports d2b60fbsysutils/treemd distinfo Makefile.crates

sysutils/treemd: Update to 0.5.8

ChangeLog:      https://github.com/Epistates/treemd/releases/tag/v0.5.8
Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+25-23sysutils/treemd/distinfo
+11-10sysutils/treemd/Makefile.crates
+1-1sysutils/treemd/Makefile
+37-343 files

LLVM/project 4c2ac84mlir/include/mlir/Dialect/SPIRV/IR SPIRVTosaOps.td SPIRVTosaTypes.td, mlir/test/Dialect/SPIRV/IR tosa-ops-verification.mlir tosa-ops.mlir

[mlir][spirv] Add Element Binary Logical operators to TOSA Ext Inst Set (#183703)

This patch introduces the following element binary operators:
* spirv.Tosa.LogicalAnd
* spirv.Tosa.LogicalLeftShift
* spirv.Tosa.LogicalRightShift
* spirv.Tosa.LogicalOr
* spirv.Tosa.LogicalXor

Also dialect and serialization round-trip tests have been added.

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+173-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
+171-0mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
+100-0mlir/test/Target/SPIRV/tosa-ops.mlir
+55-0mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
+1-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
+500-05 files

FreeBSD/ports 70c1dabx11-wm/hyprland pkg-plist distinfo, x11-wm/hyprland/files patch-hyprpm_CMakeLists.txt patch-hyprtester_src_tests_clients_shortcut-inhibitor.cpp

x11-wm/hyprland: Update to 0.54.0

Release Announcement: https://hypr.land/news/update54/
Changelog: https://github.com/hyprwm/Hyprland/releases/tag/v0.54.0

Reported by:    GitHub (watch releases)
DeltaFile
+50-8x11-wm/hyprland/pkg-plist
+0-14x11-wm/hyprland/files/patch-hyprpm_CMakeLists.txt
+10-0x11-wm/hyprland/files/patch-hyprtester_src_tests_clients_shortcut-inhibitor.cpp
+10-0x11-wm/hyprland/files/patch-hyprtester_clients_shortcut-inhibitor.cpp
+3-3x11-wm/hyprland/distinfo
+3-3x11-wm/hyprland/files/patch-hyprpm_src_core_PluginManager.cpp
+76-281 files not shown
+77-307 files

LLVM/project 36c6c68compiler-rt/test/builtins CMakeLists.txt

[compiler-rt][ARM] Fix conditions for strict-mode FP testing (#183507)

On sufficiently old versions of the Arm architecture, the optimized FP
routines are not enabled. So commit a84ee1416b6c179 should not have
enabled the extra-strict tests that go with them.

Also in that commit, I wrote a comment saying I was setting two separate
compile-time definitions (-DCOMPILER_RT_ARM_OPTIMIZED_FP and
-DCOMPILER_RT_ARM_OPTIMIZED_FP_THUMB1), and then didn't actually do it!
This caused the strict mulsf3 tests to be wrongly disabled in Thumb2.
DeltaFile
+11-3compiler-rt/test/builtins/CMakeLists.txt
+11-31 files

LLVM/project 4922ab9llvm/lib/Target/RISCV RISCVInstrInfo.cpp RISCVAsmPrinter.cpp, llvm/test/CodeGen/RISCV prefetch.ll riscv-zihintpause.ll

[RISCV] Relax codegen predicates for HINT-based instructions (#179872)

Following the assembler/disassembler changes in #178609, this patch also
relaxes the codegen predicates for HINT-based instructions. Since these
instructions use encodings that are architecturally guaranteed not to
trap, the compiler can safely generate them regardless of extension
availability.

Changes:
- int_riscv_pause: Remove HasStdExtZihintpause predicate. The pause
intrinsic now generates the FENCE hint encoding unconditionally.
- NTL hints: Remove hasStdExtZihintntl() check in emitNTLHint().
Non-temporal locality hints are now emitted for all nontemporal memory
operations.
DeltaFile
+448-1,231llvm/test/CodeGen/RISCV/prefetch.ll
+17-9llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+9-6llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
+8-7llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+5-0llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+2-2llvm/lib/Target/RISCV/RISCVInstrInfo.td
+489-1,2551 files not shown
+492-1,2557 files

OpenBSD/ports qLrumBPx11/nagstamon Makefile distinfo, x11/nagstamon/patches patch-setup_py patch-Nagstamon_Config_py

   update to nagstamon-3.18.0
VersionDeltaFile
1.17+291-113x11/nagstamon/pkg/PLIST
1.45+13-5x11/nagstamon/Makefile
1.13+6-6x11/nagstamon/patches/patch-setup_py
1.17+2-2x11/nagstamon/distinfo
1.13+0-0x11/nagstamon/patches/patch-Nagstamon_Config_py
+312-1265 files

LLVM/project 0704b68llvm/test/tools/gold/X86 thinlto.ll

[gold] Fix test

Update for https://github.com/llvm/llvm-project/pull/183793.
DeltaFile
+3-3llvm/test/tools/gold/X86/thinlto.ll
+3-31 files

LLVM/project c62c00cllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize reuse-lcssa-phi-scev-expansion.ll pointer-induction.ll

[VPlan] Remove unused VPExpandSCEVRecipe before expansion (#181329)

VPExpandSCEVRecipe may become unused after VPlan optimizations. This
patch removes VPExpandSCEVRecipes with no users before expansion in
expandSCEVs, avoiding generating dead code during VPlan execution.
DeltaFile
+1-12llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
+1-3llvm/test/Transforms/LoopVectorize/pointer-induction.ll
+4-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-2llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll
+1-1llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll
+0-1llvm/test/Transforms/LoopVectorize/version-mem-access.ll
+7-191 files not shown
+7-207 files

LLVM/project 51d9b40llvm/test/CodeGen/AArch64 sve-lrint.ll

[AArch64] Remove iXLen from sve-lrint.ll. NFC
DeltaFile
+55-74llvm/test/CodeGen/AArch64/sve-lrint.ll
+55-741 files

FreeBSD/src fe53412usr.bin/diff3 diff3.c diff3.1

diff3: Produce correct exit status

Use exit status 2 for errors, 1 only to indicate that differences were
found between the inputs (in some operating modes).

MFC after:      1 week
Sponsored by:   Klara, Inc.
Reviewed by:    ngie, bapt
Differential Revision:  https://reviews.freebsd.org/D55608
DeltaFile
+13-13usr.bin/diff3/diff3.c
+16-1usr.bin/diff3/diff3.1
+29-142 files

OpenBSD/src chc8CUmusr.bin/tmux format.c

   Revert r1.343 for the moment since it breaks behaviour (#() in
   status-left) that we need to keep.
VersionDeltaFile
1.346+3-5usr.bin/tmux/format.c
+3-51 files

FreeBSD/ports 0e25377devel/py-setuptools-scm/files patch-pyproject.toml

devel/py-setuptools-scm: Fix build with Python 3.10 and py-tomli

Make this port build and run with an newer version of py-tomli by backporting
an upstream patch.

Co-authored-by: Michael Osipov <michaelo at FreeBSD.org>
PR:             293530
PR:             286779
Obtained from:  https://github.com/RonnyPfannschmidt/setuptools_scm/commit/c35b53ac0dcbd0528521886612540ac6478509ee
DeltaFile
+41-0devel/py-setuptools-scm/files/patch-pyproject.toml
+41-01 files

OpenBSD/src uLRuvxVusr.bin/tmux format.c

   Do not leak active/all strings in format_loop_windows; from Huihui Huang
   in GitHub issue 4898.
VersionDeltaFile
1.345+4-1usr.bin/tmux/format.c
+4-11 files

OpenBSD/src y6kLqN7usr.bin/tmux tmux.1

   Fix incorrect placement of It Xo, from Dane Jensen.
VersionDeltaFile
1.1034+3-3usr.bin/tmux/tmux.1
+3-31 files

OpenBSD/src MnoVt02usr.bin/tmux menu.c

   Fix memory leak, from Emmanuel Ugwu in GitHub issue 4900.
VersionDeltaFile
1.61+2-1usr.bin/tmux/menu.c
+2-11 files

LLVM/project ba2e9fbllvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Merge remote-tracking branch 'external-upstream/main' into users/mariusz-sikora-at-amd/gfx13/add-vinterp
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+11,178-0llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+10,242-0llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+88,536-14,9203,987 files not shown
+318,512-118,5743,993 files

LLVM/project b2c30acllvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Rewrite formula in the Weak Zero SIV tests
DeltaFile
+67-72llvm/lib/Analysis/DependenceAnalysis.cpp
+8-8llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll
+4-8llvm/include/llvm/Analysis/DependenceAnalysis.h
+2-6llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-overflow.ll
+2-2llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll
+83-965 files

LLVM/project f7b1107llvm/lib/Analysis IVDescriptors.cpp, llvm/test/Transforms/LoopVectorize minmax_reduction.ll float-minmax-instruction-flag.ll

[IVDescriptors] Remove function FMF attribute check for FP min/max reduction (#183523)

Remove the use of function attributes no-nans-fp-math and
no-signed-zeros-fp-math in FP min/max reduction detection. The required
fast-math flags nnan and nsz should be present on the intrinsic calls,
fcmp and select instructions themselves.
DeltaFile
+55-57llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
+26-47llvm/lib/Analysis/IVDescriptors.cpp
+35-36llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
+15-22llvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
+17-18llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
+10-11llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
+158-1913 files not shown
+179-2139 files

NetBSD/pkgsrc RvziH6Odoc CHANGES-2026 TODO

   Updated devel/py-maturin, devel/py-ruff
VersionDeltaFile
1.1486+3-1doc/CHANGES-2026
1.26880+1-3doc/TODO
+4-42 files

NetBSD/pkgsrc DbIwfTPdevel/py-ruff distinfo cargo-depends.mk, devel/py-ruff/patches patch-python_ruff___find__ruff.py patch-python_ruff_____main____.py

   py-ruff: updated to 0.15.4

   0.15.4

   Bug fixes

   Fix panic on access to definitions after analyzing definitions
   [pyflakes] Suppress false positive in F821 for names used before del in stub files

   Documentation

   Clarify first-party import detection in Ruff
   Fix incorrect import-heading example
VersionDeltaFile
1.94+98-74devel/py-ruff/distinfo
1.89+31-23devel/py-ruff/cargo-depends.mk
1.1+23-0devel/py-ruff/patches/patch-python_ruff___find__ruff.py
1.96+3-3devel/py-ruff/Makefile
1.3+4-1devel/py-ruff/PLIST
1.2+1-1devel/py-ruff/patches/patch-python_ruff_____main____.py
+160-1026 files

LLVM/project b4e01callvm/lib/Target/AMDGPU AMDGPUSubtarget.h

Remove unused getFlatOffsetBitWidth()
DeltaFile
+0-2llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+0-21 files

LLVM/project d7d26e5mlir/include/mlir/IR Region.h Operation.h, mlir/lib/Dialect/OpenACC/IR OpenACC.cpp

[mlir][IR] Add multi-type `getParentOfType` overloads
DeltaFile
+7-23mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+11-0mlir/include/mlir/IR/Region.h
+1-8mlir/lib/Dialect/OpenACC/Transforms/LegalizeDataValues.cpp
+8-0mlir/include/mlir/IR/Operation.h
+1-7mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
+2-4mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
+30-426 files

FreeBSD/ports c9d1effaudio/shairport-sync distinfo Makefile

audio/shairport-sync: Update to 5.0.1
DeltaFile
+3-3audio/shairport-sync/distinfo
+1-1audio/shairport-sync/Makefile
+4-42 files

LLVM/project 265c1f4llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize max-interleave-factor-debug.ll

[LV] Add debug print for TTI.MaxInterleaveFactor (NFC) (#183309)

As its not currently visible in the debug output.

---------

Co-authored-by: Sander de Smalen <sander.desmalen at arm.com>
DeltaFile
+24-0llvm/test/Transforms/LoopVectorize/max-interleave-factor-debug.ll
+2-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+26-02 files