HardenedBSD/src eef1bc3sys/dev/thunderbolt nhi.c

Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/pledge
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HardenedBSD/src 16e90casys/dev/thunderbolt nhi.c

Merge branch 'freebsd/current/main' into hardened/current/master
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HardenedBSD/src d774faesys/dev/dpaa2 dpaa2_ni.c, sys/kern kern_lock.c vfs_mount.c

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main
DeltaFile
+26-3sys/kern/vfs_mount.c
+11-0sys/dev/dpaa2/dpaa2_ni.c
+7-0sys/kern/kern_lock.c
+4-0tests/sys/kern/ptrace_test.c
+0-3sys/vm/vm_phys.c
+2-0sys/sys/vnode.h
+50-63 files not shown
+53-79 files

HardenedBSD/ports 003e6a3graphics/mesa-devel/files patch-clock_monotonic, graphics/satty Makefile.crates distinfo

Merge branch 'freebsd/main' into hardenedbsd/main
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+143-133graphics/satty/distinfo
+143-0x11/framework-autorotate/files/framework_autorotate.in
+70-65graphics/satty/Makefile.crates
+49-0x11/framework-autorotate/Makefile
+20-0japanese/skk-tools/files/patch-skk2cdb.py
+18-0graphics/mesa-devel/files/patch-clock_monotonic
+443-19833 files not shown
+542-26539 files

LLVM/project 6651a11llvm/lib/Target/Lanai LanaiTargetMachine.h, llvm/test/CodeGen/Lanai subword.ll sub-cmp-peephole.ll

[Lanai] Default to NewPM

Lanai should be fully functional with the NewPM, so try defaulting to
it. Also remove the now duplicate test coverage.

Setting this flag makes both clang and llc default to the NewPM.

Reviewers: jpienaar

Pull Request: https://github.com/llvm/llvm-project/pull/214574
DeltaFile
+0-4llvm/test/CodeGen/Lanai/codemodel.ll
+0-3llvm/test/CodeGen/Lanai/mem_alu_combiner.ll
+0-3llvm/test/CodeGen/Lanai/delay_filler.ll
+2-0llvm/lib/Target/Lanai/LanaiTargetMachine.h
+0-1llvm/test/CodeGen/Lanai/subword.ll
+0-1llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll
+2-1219 files not shown
+2-3125 files

LLVM/project 3526b35llvm/include/llvm/CodeGen TargetSubtargetInfo.h, llvm/lib/CodeGen RegisterClassInfo.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+19-0mlir/lib/Dialect/ArmSME/IR/ArmSME.cpp
+10-5llvm/lib/Target/ARM/ARMSubtarget.cpp
+7-7llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+5-8llvm/lib/CodeGen/RegisterClassInfo.cpp
+6-2mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
+6-2mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
+53-246 files not shown
+64-3112 files

LLVM/project 0c4f374llvm/lib/Target/MSP430 MSP430TargetMachine.h

[MSP430] Default to NewPM

MSP430 should be fully complete with the NewPM, so default to it.

This flag makes both clang and llc default to using the NewPM for
CodeGen.

Reviewers: asl

Pull Request: https://github.com/llvm/llvm-project/pull/214573
DeltaFile
+2-0llvm/lib/Target/MSP430/MSP430TargetMachine.h
+2-01 files

LLVM/project 2a4cb1fmlir/include/mlir/Dialect/ArmSME/IR ArmSMEOps.td, mlir/lib/Dialect/ArmSME/IR ArmSME.cpp

[mlir][ArmSME] Reject non-unit-stride `tile_load/tile_store` memrefs and pass `layout{IdentityLayoutMap}` to matmul tests (#214959)
DeltaFile
+19-0mlir/lib/Dialect/ArmSME/IR/ArmSME.cpp
+6-2mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir
+6-2mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
+2-0mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
+33-44 files

LLVM/project d7610f8llvm/include/llvm/CodeGen TargetSubtargetInfo.h, llvm/lib/CodeGen RegisterClassInfo.cpp

[CodeGen] Avoid querying allocation order for every CSR alias (#215752)

Profiling tramp3d-v4 on aarch64-O0-g shows ~0.30% of compile-time is
spent in RegisterClassInfo::runOnMachineFunction.

It currently walks every alias of every callee-saved register for every
MachineFunction, doing a virtual call to ignoreCSRForAllocationOrder for
each alias. ARM is the only target that overrides this hook; all other
targets construct a full-sized BitVector and perform the alias traversal
only to fill it with zeroes.

Replace the per-register hook with a target-populated mask. Most targets
leave the mask empty, avoiding the allocation and alias traversal. The
mask is also only consulted after getLastCalleeSavedAlias confirms the
physical register aliases a CSR, so ARM can populate all GPR bits
directly without rediscovering the CSR aliases.

Improves CTMark geomean by -0.10%, with tramp3d-v4 -0.34%.


    [2 lines not shown]
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+10-5llvm/lib/Target/ARM/ARMSubtarget.cpp
+7-7llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+5-8llvm/lib/CodeGen/RegisterClassInfo.cpp
+2-2llvm/lib/Target/ARM/ARMSubtarget.h
+24-224 files

HardenedBSD/ports 73d652dsysutils/py-dbuild Makefile distinfo

sysutils/py-dbuild: Update to 1.9.12

ChangeLogs:

- https://github.com/daemonless/dbuild/releases/tag/v1.9.10
- https://github.com/daemonless/dbuild/releases/tag/v1.9.11
- https://github.com/daemonless/dbuild/releases/tag/v1.9.12
DeltaFile
+3-3sysutils/py-dbuild/distinfo
+1-1sysutils/py-dbuild/Makefile
+4-42 files

FreeBSD/ports 2770150devel/py-ytmusicapi Makefile distinfo

devel/py-ytmusicapi: Update to 1.12.2

ChangeLog: https://github.com/sigma67/ytmusicapi/releases/tag/1.12.2
DeltaFile
+3-3devel/py-ytmusicapi/distinfo
+1-1devel/py-ytmusicapi/Makefile
+4-42 files

FreeBSD/ports 73d652dsysutils/py-dbuild Makefile distinfo

sysutils/py-dbuild: Update to 1.9.12

ChangeLogs:

- https://github.com/daemonless/dbuild/releases/tag/v1.9.10
- https://github.com/daemonless/dbuild/releases/tag/v1.9.11
- https://github.com/daemonless/dbuild/releases/tag/v1.9.12
DeltaFile
+3-3sysutils/py-dbuild/distinfo
+1-1sysutils/py-dbuild/Makefile
+4-42 files

HardenedBSD/ports 2770150devel/py-ytmusicapi Makefile distinfo

devel/py-ytmusicapi: Update to 1.12.2

ChangeLog: https://github.com/sigma67/ytmusicapi/releases/tag/1.12.2
DeltaFile
+3-3devel/py-ytmusicapi/distinfo
+1-1devel/py-ytmusicapi/Makefile
+4-42 files

FreeBSD/ports cc36937sysutils/appjail Makefile distinfo

sysutils/appjail: Update to 5.4.0

ChangeLog: https://github.com/DtxdF/AppJail/releases/tag/v5.4.0
DeltaFile
+3-3sysutils/appjail/distinfo
+1-1sysutils/appjail/Makefile
+4-42 files

FreeBSD/ports ba82ddcsysutils/appjail-devel Makefile distinfo

sysutils/appjail-devel: Update to 5.4.0.20260812

ChangeLog:
https://github.com/DtxdF/AppJail/commits/85f7a6a5b5f6c435cadbea3260d6d958c2cfeafd/
DeltaFile
+3-3sysutils/appjail-devel/distinfo
+2-2sysutils/appjail-devel/Makefile
+5-52 files

HardenedBSD/ports cc36937sysutils/appjail Makefile distinfo

sysutils/appjail: Update to 5.4.0

ChangeLog: https://github.com/DtxdF/AppJail/releases/tag/v5.4.0
DeltaFile
+3-3sysutils/appjail/distinfo
+1-1sysutils/appjail/Makefile
+4-42 files

HardenedBSD/ports ba82ddcsysutils/appjail-devel Makefile distinfo

sysutils/appjail-devel: Update to 5.4.0.20260812

ChangeLog:
https://github.com/DtxdF/AppJail/commits/85f7a6a5b5f6c435cadbea3260d6d958c2cfeafd/
DeltaFile
+3-3sysutils/appjail-devel/distinfo
+2-2sysutils/appjail-devel/Makefile
+5-52 files

HardenedBSD/src 7858a57sys/dev/thunderbolt nhi.c

thunderbolt: Explicitly read NHI ISR0 register to clear it

This fixes and issue where Pink Sardine controllers were not receiving
interrupts for more than the first command sent on the ring.

Reviewed by:    emaste, imp
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D52862
DeltaFile
+16-0sys/dev/thunderbolt/nhi.c
+16-01 files

FreeBSD/src 7858a57sys/dev/thunderbolt nhi.c

thunderbolt: Explicitly read NHI ISR0 register to clear it

This fixes and issue where Pink Sardine controllers were not receiving
interrupts for more than the first command sent on the ring.

Reviewed by:    emaste, imp
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D52862
DeltaFile
+16-0sys/dev/thunderbolt/nhi.c
+16-01 files

LLVM/project 1366911llvm/utils/gn/secondary/llvm/unittests/CodeGen BUILD.gn

[gn build] Port ff494c648aec (#215956)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
+1-01 files

LLVM/project e90f591llvm/utils/gn/secondary/clang/lib/Headers BUILD.gn

[gn build] Port c3792d66d2c1 (#215955)
DeltaFile
+3-0llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
+3-01 files

LLVM/project 087eff5llvm/utils/gn/secondary/llvm/unittests/ADT BUILD.gn

[gn build] Port 1e798c1343fa (#215954)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn
+1-01 files

OPNSense/core 2ba5677src/etc/inc/plugins.inc.d unbound.inc

Unbound: switch AAAA-only mode from respip to block_a_wdata
DeltaFile
+1-2src/etc/inc/plugins.inc.d/unbound.inc
+1-21 files

LLVM/project f9af10cllvm/utils/gn/secondary/llvm/tools/libCASPluginTest BUILD.gn

[gn] Attempt to get CASTests passing after #214856 (#215949)

See also
https://github.com/llvm/llvm-project/pull/213331#discussion_r3772630039
DeltaFile
+2-5llvm/utils/gn/secondary/llvm/tools/libCASPluginTest/BUILD.gn
+2-51 files

HardenedBSD/ports 6540141www/newsraft Makefile distinfo

www/newsraft: Update to 0.37

Changelog:
https://codeberg.org/newsraft/newsraft/releases/tag/newsraft-0.37
DeltaFile
+3-3www/newsraft/distinfo
+1-1www/newsraft/Makefile
+4-42 files

FreeBSD/ports 6540141www/newsraft Makefile distinfo

www/newsraft: Update to 0.37

Changelog:
https://codeberg.org/newsraft/newsraft/releases/tag/newsraft-0.37
DeltaFile
+3-3www/newsraft/distinfo
+1-1www/newsraft/Makefile
+4-42 files

LLVM/project 4b59bc2llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes LoadStoreVec.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes LoadStoreVec.cpp

[SandboxVectorizer] Dispatch LoadStoreVec::runOnRegion on seed kind

runOnRegion() previously assumed its seed slice was always a store chain,
unconditionally casting Bndl[0] to StoreInst. This crashed (assertion in
areConsecutive<StoreInst>) whenever -sbvec-collect-seeds included "loads",
since a load-seeded region's Aux holds LoadInsts.

Add a symmetric top-level path for load-kind seed slices: createVectorLoad()
builds the vector load, and vectorizeLoads() -- unlike a load that merely
feeds a store -- has to handle arbitrary uses, so it replaces each original
load with an extract from the vector load (VecUtils::unpack()) rather than
just discarding it. runOnRegion() determines the seed kind from Bndl[0]
(asserting the slice is homogeneous, which SeedCollection guarantees) and
dispatches to vectorizeStores()/vectorizeLoads() accordingly.

No sub-run search yet: vectorizeStores()/vectorizeLoads() are each still
tried once over the whole seed slice, same as before this commit for
stores. Sub-bundle partitioning for both kinds is a separate follow-up.


    [13 lines not shown]
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+96-17llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+99-0llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_load_seeds.ll
+24-2llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
+219-193 files

FreeBSD/ports d96158btextproc/R-cran-stringi Makefile distinfo

textproc/R-cran-stringi: Update to 1.8.9

Changelog: https://cran.r-project.org/web/packages/stringi/NEWS
DeltaFile
+3-3textproc/R-cran-stringi/distinfo
+1-1textproc/R-cran-stringi/Makefile
+4-42 files

HardenedBSD/ports d96158btextproc/R-cran-stringi Makefile distinfo

textproc/R-cran-stringi: Update to 1.8.9

Changelog: https://cran.r-project.org/web/packages/stringi/NEWS
DeltaFile
+3-3textproc/R-cran-stringi/distinfo
+1-1textproc/R-cran-stringi/Makefile
+4-42 files

LLVM/project d28009cflang/lib/Lower/OpenMP OpenMP.cpp, lldb/source/Symbol Symbol.cpp

rebase

Created using spr 1.3.7
DeltaFile
+699-0llvm/test/Transforms/ConstraintElimination/header-induction-start-bounds.ll
+70-324llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+47-285flang/lib/Lower/OpenMP/OpenMP.cpp
+315-0llvm/test/Transforms/CorrelatedValuePropagation/infer-nowrap-from-uses.ll
+206-89lldb/source/Symbol/Symbol.cpp
+138-138llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+1,475-836366 files not shown
+5,877-3,167372 files