LLVM/project 02f857f — compiler-rt/lib/tsan/rtl tsan_rtl.h tsan_rtl_thread.cpp

[NFC][TSan] Lock ThreadRegistryLock inside ScopedReport::AddThread and AddLocation (#228814)

Among ScopedReport methods, only AddThread and AddLocation
(via IsThreadStackOrTls) have ever accessed ctx->thread_registry;
AddMemoryAccess, AddMutex, AddStack, AddSleep, AddUniqueTid, and
SetCount only populate ScopedReport::rep_.

Now that ScopedReport's constructor (#228614) and ReportRace (#228813)
no longer require callers to hold ThreadRegistryLock, acquire
ThreadRegistryLock inside ScopedReport::AddThread and
ScopedReport::AddLocation instead of locking ctx->thread_registry in
each caller around ScopedReport population.

Assisted-by: Gemini
DeltaFile
+32-28compiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
+13-28compiler-rt/lib/tsan/rtl/tsan_rtl_mutex.cpp
+2-7compiler-rt/lib/tsan/rtl/tsan_rtl_thread.cpp
+2-0compiler-rt/lib/tsan/rtl/tsan_rtl.h
+49-634 files

LLVM/project dd023ad — llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU mai-hazards-gfx90a.mir load-constant-i1.ll

Merge branch 'main' into users/arsenm/clang/fix-nostdlib.c-CLANG_USE_XCSELECT
DeltaFile
+1,023-147llvm/test/Transforms/LoopVectorize/smax-idx.ll
+307-552llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+674-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
+671-0llvm/test/Transforms/LoopVectorize/AArch64/multi-vector-mem-ops.ll
+384-40llvm/test/Transforms/Attributor/nofpclass-frem.ll
+285-129llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+3,344-868224 files not shown
+8,122-2,656230 files

LLVM/project 6246d8f — compiler-rt/test/ubsan/TestCases/Misc/Posix hsa-missing.cpp

[compiler-rt][ubsan] Link -ldl in hsa-missing.cpp (#229343)

hsa-missing.cpp calls dlsym() directly without linking -ldl, relying on
dlsym being merged into libc (true on glibc >= 2.34, not on older
glibc). This fails to link on older glibc:
```
  ld.lld: error: undefined symbol: dlsym
```
Add -ldl explicitly, it is a no-op on newer glibc where libdl is kept as
an empty compatibility stub.

Co-authored-by: Riyaz Ahmad <riyaz.ahmad at ibm.com>
DeltaFile
+1-1compiler-rt/test/ubsan/TestCases/Misc/Posix/hsa-missing.cpp
+1-11 files

LLVM/project 4fa0c8c — clang/lib/CodeGen CGOpenMPRuntime.h CGStmtOpenMP.cpp, clang/test/OpenMP target_no_loop.c

Share one no-loop eligibility check between exec mode and body

The kernel is tagged SPMD_NO_LOOP by a single check, and the body is
emitted loop-free exactly when the kernel carries that tag. Add tests
for the clauses that block promotion.
DeltaFile
+58-1clang/test/OpenMP/target_no_loop.c
+34-19clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+11-3clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
+2-11clang/lib/CodeGen/CGStmtOpenMP.cpp
+4-5clang/lib/CodeGen/CGOpenMPRuntime.h
+109-395 files

FreeNAS/freenas f384052 — src/middlewared/middlewared/plugins zettarepl.py replication.py, src/middlewared/middlewared/plugins/failover_ event.py

NAS-144133 / 27.0.0 / Load zettarepl state from the database on failover (by themylogin) (#19957)

Original PR: https://github.com/truenas/middleware/pull/19899

Co-authored-by: themylogin <themylogin at gmail.com>
DeltaFile
+158-0tests/api2/test_zettarepl_state.py
+88-48src/middlewared/middlewared/plugins/zettarepl_/state.py
+6-3src/middlewared/middlewared/plugins/snapshot.py
+4-4src/middlewared/middlewared/plugins/replication.py
+3-2src/middlewared/middlewared/plugins/zettarepl.py
+4-0src/middlewared/middlewared/plugins/failover_/event.py
+263-576 files

LLVM/project e8c0429 — llvm/lib/CodeGen CodeGenPrepare.cpp

Remove outdated comment
DeltaFile
+0-2llvm/lib/CodeGen/CodeGenPrepare.cpp
+0-21 files

LLVM/project cf13144 — flang/lib/Optimizer/OpenMP MapsForPrivatizedSymbols.cpp, flang/test/Lower/OpenMP declare-mapper.f90

[flang][mlir][OpenMP] Report Fortran names for privatized target maps (#228195)

Privatized, firstprivate and implicitly captured variables offloaded to
a target device were reported as "unknown" in LIBOMPTARGET_INFO debug
output. This PR addresses this by adding the variable names to the
offload mapping information:
 
- `MapsForPrivatizedSymbols` now sets the name on the omp.map.info it
creates,
recovering it from the hlfir.declare uniq name or, for anonymously boxed
values (e.g. a firstprivate array), from a NameLoc on the descriptor's
   alloca.
- `privatizeSymbol` tags that alloca with a NameLoc carrying the symbol
name
   so the pass can recover it when there is no hlfir.declare.
- `createMappingInformation` gains an optional map name and prefers it
over the
location-derived name; the OpenMP translation forwards each map's name
   attribute for both parent and member entries.

    [64 lines not shown]
DeltaFile
+82-0offload/test/offloading/fortran/target-firstprivate-info.f90
+23-7mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+28-0mlir/test/Target/LLVMIR/omptarget-map-names.mlir
+11-11flang/test/Transforms/omp-map-info-finalization.fir
+10-10flang/test/Lower/OpenMP/declare-mapper.f90
+15-3flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
+169-3129 files not shown
+258-11335 files

LLVM/project aa2e46c — llvm/test/CodeGen/AMDGPU frem.ll atomic_optimizations_local_pointer.ll, llvm/test/CodeGen/AMDGPU/GlobalISel srem.i64.ll sdiv.i64.ll

rebase

Created using spr 1.3.7
DeltaFile
+733-5,435llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+1,609-1,040llvm/test/CodeGen/AMDGPU/frem.ll
+986-1,144llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+914-1,072llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+728-824llvm/test/CodeGen/X86/mul-constant-i32.ll
+585-680llvm/test/CodeGen/X86/mul-constant-i64.ll
+5,555-10,1951,501 files not shown
+61,850-34,1031,507 files

FreeBSD/ports 919d613 — textproc/obsidian Makefile distinfo

textproc/obsidian: Update to 1.14.4

Reported by:    GitHub Releases
DeltaFile
+3-3textproc/obsidian/distinfo
+1-2textproc/obsidian/Makefile
+4-52 files

FreeBSD/ports 93e99a7 — misc/qwen-code Makefile distinfo, misc/qwen-code/files package-lock.json

misc/qwen-code: update to 0.25.0
DeltaFile
+8-8misc/qwen-code/files/package-lock.json
+3-3misc/qwen-code/distinfo
+1-1misc/qwen-code/Makefile
+12-123 files

FreeNAS/freenas e2106dd — src/middlewared/middlewared/service crud_service.py config_service.py, tests/api2 test_legacy_api.py

NAS-144191 / 27.0.0 / Properly handle filterable methods versioned API (by themylogin) (#19961)
DeltaFile
+21-0tests/api2/test_legacy_api.py
+1-1src/middlewared/middlewared/service/crud_service.py
+1-1src/middlewared/middlewared/service/config_service.py
+23-23 files

LLVM/project dc17218 — llvm/lib/Target/AMDGPU AMDGPU.td DSInstructions.td

AMDGPU: Use HasUsableDSOffset for LDS read2/write2 patterns (#229446)

The 64-bit and 128-bit LDS patterns that split into read2/write2 were
predicated on isGFX7Plus, based on the usable offset condition. Use a
named predicate instead of the version check.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+2-2llvm/lib/Target/AMDGPU/DSInstructions.td
+1-0llvm/lib/Target/AMDGPU/AMDGPU.td
+3-22 files

FreeNAS/freenas d46abd8 — src/middlewared/middlewared/alembic/versions/27.0 2026-10-05_12-00_rsync_extra_json_list.py, src/middlewared/middlewared/alembic/versions/28.0 2026-10-06_12-56_merge.py

Store rsync extra args as list

(cherry picked from commit 67fd777b3b505ab6ebb1e045780d4d5328a8fd1b)
DeltaFile
+66-0src/middlewared/middlewared/alembic/versions/27.0/2026-10-05_12-00_rsync_extra_json_list.py
+57-0src/middlewared/middlewared/pytest/unit/plugins/test_rsync_extra_args.py
+56-0tests/api2/test_rsync_task_extra.py
+22-0src/middlewared/middlewared/alembic/versions/28.0/2026-10-06_12-56_merge.py
+12-0src/middlewared/middlewared/pytest/unit/helpers.py
+1-10src/middlewared/middlewared/plugins/rsync/crud.py
+214-101 files not shown
+219-147 files

FreeNAS/freenas 6113c3b — src/middlewared/middlewared/service crud_service.py config_service.py, tests/api2 test_legacy_api.py

NAS-144191 / 28.0.0-BETA.1 / Properly handle filterable methods versioned API (#19943)
DeltaFile
+21-0tests/api2/test_legacy_api.py
+1-1src/middlewared/middlewared/service/crud_service.py
+1-1src/middlewared/middlewared/service/config_service.py
+23-23 files

LLVM/project c9e13e0 — llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/lib/Target TargetLoweringObjectFile.cpp

[SystemZ][z/OS] Keep read-only data in the code section only if local and without relocations (#226683)

Read-only data stayed in the code section unless it was classified as
`ReadOnlyWithRel`. This is wrong in two cases:

- Externally visible read-only data: references from other translation
units are always parts in the WSA, so the binder cannot resolve them
against a label in the code section (IEW2456E, name space 3).
- Local read-only data with relocations to local symbols, such as a
`static const` table of pointers to internal functions: with the z/OS
relocation model `DynamicNoPIC`, `getKindForGlobal` returns `ReadOnly`
for an initializer that needs only local relocations. The entries point
to function descriptors in the WSA, and the binder rejects an address
constant from the code section into the deferred WSA (IEW2353E, error
code 250001). #223055 does not cover this case.

This patch:

- In `getKindForGlobal`, returns `ReadOnlyWithRel` on GOFF for every

    [24 lines not shown]
DeltaFile
+42-0llvm/test/CodeGen/SystemZ/zos-readonly-addressing.ll
+25-0llvm/test/CodeGen/SystemZ/zos-section-readonly-extern.ll
+4-5llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
+8-0llvm/lib/Target/TargetLoweringObjectFile.cpp
+4-1llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+83-65 files

LLVM/project 52281ef — llvm/test/Transforms/LoopVectorize/AArch64 induction-costs-sve.ll, llvm/test/Transforms/LoopVectorize/ARM mve-icmpcost.ll

[VPlan] Run CSE in VPlanTransforms::optimize (#203370)

For more accurate costing and optimization benefit.
DeltaFile
+50-50llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
+32-40llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
+31-34llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+25-26llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-metadata.ll
+17-20llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-chains-vplan.ll
+8-16llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
+163-18616 files not shown
+194-23922 files

LLVM/project b4280d6 — mlir/tools/mlir-tblgen OpFormatGen.cpp

[mlir][docs] Clarify operation parser generation context (NFC) (#229460)

Explain how GenContext and ODS optionality control attribute parsing,
and why attributes are required once an optional group selects a branch.

Assisted-by: Codex
DeltaFile
+14-5mlir/tools/mlir-tblgen/OpFormatGen.cpp
+14-51 files

FreeNAS/freenas 67b8ec3 — src/middlewared/middlewared/plugins/security validate.py, src/middlewared/middlewared/plugins/system_general update.py

NAS-144138 / 28.0.0-BETA.1 / Disallow non-STIG compliant nginx configuration when in STIG mode (by themylogin) (#19953)

Original PR: https://github.com/truenas/middleware/pull/19947

Co-authored-by: themylogin <themylogin at gmail.com>
DeltaFile
+79-2tests/stig/test_01_stig.py
+33-0src/middlewared/middlewared/plugins/system_general/update.py
+24-0src/middlewared/middlewared/plugins/security/validate.py
+23-0src/middlewared/middlewared/test/integration/assets/system_general.py
+5-0src/middlewared/middlewared/utils/security.py
+164-25 files

LLVM/project a63780f — compiler-rt/lib/tsan/rtl tsan_rtl_report.cpp

[NFC][TSan] Use ScopedReport::AddThread(Tid) in ReportRace (#228813)

Inline FindThreadByTidLocked into ScopedReport::AddThread(Tid) and
enable it on Go so ReportRace can call rep.AddThread(tid) directly
instead of manually looking up ThreadContext via GetThreadLocked.

Assisted-by: Gemini
DeltaFile
+5-17compiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
+5-171 files

LLVM/project c26bfb8 — llvm/lib/CodeGen CodeGenPrepare.cpp

Formatting
DeltaFile
+4-4llvm/lib/CodeGen/CodeGenPrepare.cpp
+4-41 files

LLVM/project 5731f58 — llvm/lib/Transforms/Scalar SeparateConstOffsetFromGEP.cpp, llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX zero-operands.ll

[SeparateConstOffsetFromGEP] Simplify zero operands when rebuilding indices (#229209)

Minor cleanup and simplification around removing redundant zero operands
when rebuilding GEP indices.
DeltaFile
+63-0llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/zero-operands.ll
+10-12llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+73-122 files

LLVM/project 8fac267 — llvm/lib/CodeGen CodeGenPrepare.cpp, llvm/test/CodeGen/AArch64 strength-reduce-vector-as-data.ll

Remove usage restrictions on GEP
DeltaFile
+8-8llvm/test/CodeGen/AArch64/strength-reduce-vector-as-data.ll
+9-3llvm/test/Transforms/CodeGenPrepare/AArch64/strength-reduce-vector-as-data.ll
+0-7llvm/lib/CodeGen/CodeGenPrepare.cpp
+17-183 files

FreeNAS/freenas 7129ace — src/middlewared/middlewared/plugins zettarepl.py replication.py, src/middlewared/middlewared/plugins/failover_ event.py

NAS-144133 / 28.0.0-BETA.1 / Load zettarepl state from the database on failover (#19899)

(cherry picked from commit 6bdbb87c85494becc85645f54104246a131cc107)
DeltaFile
+158-0tests/api2/test_zettarepl_state.py
+88-48src/middlewared/middlewared/plugins/zettarepl_/state.py
+6-3src/middlewared/middlewared/plugins/snapshot.py
+4-4src/middlewared/middlewared/plugins/replication.py
+3-2src/middlewared/middlewared/plugins/zettarepl.py
+4-0src/middlewared/middlewared/plugins/failover_/event.py
+263-576 files

LLVM/project 64c82d7 — llvm/test/CodeGen/AArch64 strength-reduce-vector-as-data.ll, llvm/test/Transforms/CodeGenPrepare/AArch64 strength-reduce-vector-as-data.ll

Add gather/scatter test for strided addresses
DeltaFile
+55-0llvm/test/Transforms/CodeGenPrepare/AArch64/strength-reduce-vector-as-data.ll
+47-0llvm/test/CodeGen/AArch64/strength-reduce-vector-as-data.ll
+102-02 files

LLVM/project ccb5c3d — llvm/lib/Analysis ValueTracking.cpp, llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp

[KnownFPClass] Fix KnownFPClass::frem subnormal handling and improve deductions. (#219303)

Fixes input/output subnormal handling for `KnownFPClass::frem` as
discovered here https://github.com/llvm/llvm-project/pull/219091

Also improves the deductions made by `KnownFPClass::frem`. Such as
ruling out sNaN if neither argument is sNaN.

`KnownFPClass::frem_self` deductions were also improved.
DeltaFile
+384-40llvm/test/Transforms/Attributor/nofpclass-frem.ll
+35-27llvm/lib/Analysis/ValueTracking.cpp
+36-25llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+31-14llvm/lib/Support/KnownFPClass.cpp
+17-0llvm/unittests/Analysis/ValueTrackingTest.cpp
+2-2llvm/test/CodeGen/AArch64/GlobalISel/knownfpclass-ops.mir
+505-1086 files

LLVM/project 4b327f1 — mlir/include/mlir/Dialect/LLVMIR LLVMOps.td, mlir/test/Dialect/LLVMIR roundtrip.mlir

[MLIR][LLVM] Use oilist for llvm.load and llvm.store flags (#228977)

Parse attributes in oilist clauses as required after the keyword
DeltaFile
+6-4mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+7-0mlir/test/Dialect/LLVMIR/roundtrip.mlir
+13-42 files

LLVM/project 681259d — llvm/lib/Target/X86 X86InstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/X86 crc32-const-fold.ll

[X86] Implement CRC32 const folding (#219452)

This replaces calls to `llvm.x86.sse42.crc32.32.8` and similar functions
with calculated value in the InstCombine pass.

AI Assistance (ChatGPT Web) was used to understand LLVM codebase
structure (as a beginner) and especially around the testcase generation.
DeltaFile
+187-0llvm/test/Transforms/InstCombine/X86/crc32-const-fold.ll
+20-0llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
+207-02 files

LLVM/project c4a8ff7 — flang-rt/unittests/Runtime Reduction.cpp, flang/include/flang/Common uint128.h numeric-limits.h

Add header numeric-limits.h
DeltaFile
+106-0flang/include/flang/Common/numeric-limits.h
+1-73flang/include/flang/Common/uint128.h
+13-10flang/unittests/Evaluate/uint128.cpp
+10-9flang-rt/unittests/Runtime/Reduction.cpp
+7-6flang/include/flang/Evaluate/integer.h
+6-6flang/lib/Evaluate/host.h
+143-10428 files not shown
+202-16434 files

LLVM/project 4af7835 — llvm/test/CodeGen/AMDGPU frem.ll atomic_optimizations_local_pointer.ll, llvm/test/CodeGen/AMDGPU/GlobalISel srem.i64.ll sdiv.i64.ll

rebase

Created using spr 1.3.7
DeltaFile
+733-5,435llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+1,609-1,040llvm/test/CodeGen/AMDGPU/frem.ll
+986-1,144llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+914-1,072llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+728-824llvm/test/CodeGen/X86/mul-constant-i32.ll
+585-680llvm/test/CodeGen/X86/mul-constant-i64.ll
+5,555-10,1951,470 files not shown
+60,756-33,7241,476 files

LLVM/project 3de83a1 — llvm/lib/CodeGen CodeGenPrepare.cpp, llvm/test/Transforms/CodeGenPrepare/AArch64 strength-reduce-vector-as-data.ll

* Update banner comment
* Use GEP for preheader addressing
* Combine checks for stride
* Drop unnecessary variable
* Add TODO for fixed vector support
DeltaFile
+18-25llvm/lib/CodeGen/CodeGenPrepare.cpp
+2-6llvm/test/Transforms/CodeGenPrepare/AArch64/strength-reduce-vector-as-data.ll
+20-312 files