OPNSense/core 54ed928src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes BaseSetField.php, src/opnsense/mvc/app/models/OPNsense/Unbound/FieldTypes AliasReflector.php

setValues() to BaseSetField, simplify reflector mapper
DeltaFile
+4-15src/opnsense/mvc/app/models/OPNsense/Unbound/FieldTypes/AliasReflector.php
+5-0src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes/BaseSetField.php
+9-152 files

LLVM/project 017b9f9llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine vector-reverse.ll

[InstCombine] Fix crash in `foldReversedIntrinsicOperands` for struct-return intrinsics (#186339)

Fixes #186334 

Similar to #176556 , add the missing result type check in
`foldReversedIntrinsicOperands()`. This prevents `CreateVectorReverse()`
from being applied to struct-returning intrinsics.
DeltaFile
+16-0llvm/test/Transforms/InstCombine/vector-reverse.ll
+2-1llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+18-12 files

LLVM/project fbd6d54llvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp AArch64SVEInstrInfo.td, llvm/test/CodeGen/AArch64 imm-splat-ops.ll zext-to-tbl.ll

[AArch64] Fold NEON splats into users by using SVE immediates (#165559)

This patch adds patterns that attempt to fold NEON constant splats into
users by promoting the users to use SVE, when the splat immediate is a
legal SVE immediate operand.

This is done as ISEL patterns to avoid folding to SVE too early, which
can disrupt other patterns/combines.
DeltaFile
+320-0llvm/test/CodeGen/AArch64/imm-splat-ops.ll
+92-16llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+48-50llvm/test/CodeGen/AArch64/zext-to-tbl.ll
+44-0llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+23-7llvm/test/CodeGen/AArch64/aarch64-smull.ll
+4-4llvm/test/CodeGen/AArch64/reassocmls.ll
+531-772 files not shown
+535-838 files

LLVM/project cf40936llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.umin.ll

Refactor Code:
Logical error in the code, was using the wrong register
to calculate some values.
DeltaFile
+34-34llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+114-1145 files not shown
+181-17111 files

LLVM/project 4c14969clang/include/clang/CIR/Dialect/IR CIRAttrs.td CIROps.td, clang/lib/CIR/CodeGen CIRGenModule.cpp

[CIR][CIRGen] Introduce ExtraFuncAttr to FuncOp
DeltaFile
+22-0clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+21-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+12-2clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+11-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
+4-6clang/lib/CIR/CodeGen/CIRGenModule.cpp
+6-0clang/include/clang/CIR/Dialect/IR/CIROps.td
+76-96 files not shown
+92-1212 files

LLVM/project ebb45a2llvm/docs AMDGPUUsage.rst

Comments
DeltaFile
+16-19llvm/docs/AMDGPUUsage.rst
+16-191 files

LLVM/project 526e992llvm/docs AMDGPUUsage.rst

Address comments
DeltaFile
+50-54llvm/docs/AMDGPUUsage.rst
+50-541 files

LLVM/project a16cde8llvm/docs AMDGPUUsage.rst

[AMDGPU][Doc] GFX12.5 Barrier Execution Model

- Document GFX12.5-specific intrinsics.
- Rename signal -> arrive, leave -> drop to match C++ terminology.
- Update execution model to support GFX12.5 semantics (e.g. threads can arrive w/o waiting)
- Various clean-ups & wording updates on the model.
- Added "mutually exclusive" barrier objects.
- Added barrier-phase-with + related constraints.
- Document that barriers can exist at cluster scope too.
- Update GFX12 target semantics/code sequences to include GFX12.5.

The model is no longer marked as incomplete, it is now just experimental.

There are more updates planned in the future to support more features, and
improve some known shortcomings of the model. e.g., currently many relations
encode too much semantic information, which means the model doesn't build
when barriers aren't used correctly. I'd like the model to eventually represent
broken executions as well, just like a memory model can.
DeltaFile
+329-180llvm/docs/AMDGPUUsage.rst
+329-1801 files

LLVM/project bf55243llvm/docs AMDGPUUsage.rst

small fix
DeltaFile
+1-1llvm/docs/AMDGPUUsage.rst
+1-11 files

OPNSense/core 25be324src/opnsense/mvc/app/models/OPNsense/Unbound/FieldTypes AliasReflector.php

switch to BaseSetField for AliasReflector
DeltaFile
+3-3src/opnsense/mvc/app/models/OPNsense/Unbound/FieldTypes/AliasReflector.php
+3-31 files

OPNSense/core c634290src/opnsense/mvc/app/models/OPNsense/Unbound/FieldTypes AliasRefCount.php

remove AliasRefCount.php as well
DeltaFile
+0-53src/opnsense/mvc/app/models/OPNsense/Unbound/FieldTypes/AliasRefCount.php
+0-531 files

LLVM/project c722f26llvm/include/llvm/Analysis ScalarEvolutionExpressions.h ScalarEvolution.h

!fixup address comments, thanks
DeltaFile
+3-8llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
+0-2llvm/include/llvm/Analysis/ScalarEvolution.h
+3-102 files

LLVM/project d38b24allvm/include/llvm/Analysis ScalarEvolution.h, llvm/lib/Analysis ScalarEvolution.cpp

!fixup more cleanups
DeltaFile
+22-33llvm/lib/Analysis/ScalarEvolution.cpp
+2-6llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+4-2llvm/include/llvm/Analysis/ScalarEvolution.h
+1-2llvm/lib/Transforms/Scalar/LoopFuse.cpp
+1-1llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
+30-445 files

LLVM/project 5260019llvm/include/llvm/Analysis ScalarEvolutionExpressions.h, llvm/lib/Transforms/Scalar LoopFuse.cpp LoopPredication.cpp

!fixup address latest comments, thanks
DeltaFile
+18-20llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
+3-3llvm/lib/Transforms/Scalar/LoopFuse.cpp
+1-4llvm/lib/Transforms/Scalar/LoopPredication.cpp
+1-4llvm/lib/Transforms/Scalar/NaryReassociate.cpp
+1-4llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
+1-2llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
+25-371 files not shown
+26-387 files

LLVM/project a612db7llvm/include/llvm/Analysis ScalarEvolution.h ScalarEvolutionExpressions.h, llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Introduce SCEVUse wrapper type (NFC)

Add SCEVUse as a PointerIntPair wrapper around const SCEV * to prepare
for storing additional per-use information.

This commit contains the mechanical changes of adding an intial SCEVUse
wrapper and updating all relevant interfaces to take SCEVUse. Note that
currently the integer part is never set, and all SCEVUses are
considered canonical.
DeltaFile
+280-246llvm/lib/Analysis/ScalarEvolution.cpp
+117-47llvm/include/llvm/Analysis/ScalarEvolution.h
+78-70llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
+36-29llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+25-26llvm/lib/Transforms/Scalar/NaryReassociate.cpp
+17-18llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+553-43622 files not shown
+656-52328 files

OPNSense/core 37add66src/opnsense/mvc/app/controllers/OPNsense/Unbound/Api SettingsController.php, src/opnsense/mvc/app/controllers/OPNsense/Unbound/forms dialogHostOverride.xml

ditch aliascount volatile field
DeltaFile
+0-5src/opnsense/mvc/app/controllers/OPNsense/Unbound/forms/dialogHostOverride.xml
+0-1src/opnsense/mvc/app/controllers/OPNsense/Unbound/Api/SettingsController.php
+0-1src/opnsense/mvc/app/models/OPNsense/Unbound/Unbound.xml
+0-73 files

LLVM/project 2ca8251llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.min.ll

Refactor Code:
Logical error in the code, was using the wrong register
to calculate some values.
DeltaFile
+34-34llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+114-1144 files not shown
+175-16510 files

LLVM/project f6add1emlir/lib/Dialect/OpenACC/IR OpenACC.cpp, mlir/test/Dialect/OpenACC invalid.mlir

[MLIR][OpenACC] Fix crash in verifyDeviceTypeCountMatch when deviceTypes is null (#186279)

When an acc.parallel op has async operands (via operandSegmentSizes) but
no corresponding asyncOperandsDeviceType attribute, the verifier called
verifyDeviceTypeCountMatch with a null ArrayAttr. The function then
dereferenced the null pointer via deviceTypes.getValue(), causing a
segfault instead of a diagnostic.

Fix by guarding the getValue() call with a null check. When deviceTypes
is absent but operands are present, the mismatch is now reported as a
proper verifier error.

Fixes #107027

Assisted-by: Claude Code
DeltaFile
+16-0mlir/test/Dialect/OpenACC/invalid.mlir
+2-1mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+18-12 files

OPNSense/core 5ea3f70src/opnsense/mvc/app/controllers/OPNsense/Unbound/Api SettingsController.php, src/opnsense/mvc/app/controllers/OPNsense/Unbound/forms dialogHostOverride.xml

quick alias update logic
DeltaFile
+73-64src/opnsense/mvc/app/views/OPNsense/Unbound/overrides.volt
+116-3src/opnsense/mvc/app/controllers/OPNsense/Unbound/Api/SettingsController.php
+56-27src/opnsense/www/js/opnsense_bootgrid.js
+1-1src/opnsense/mvc/app/controllers/OPNsense/Unbound/forms/dialogHostOverride.xml
+246-954 files

LLVM/project f2749f6llvm/lib/Transforms/Utils LowerMemIntrinsics.cpp, llvm/test/CodeGen/AMDGPU memset-pattern.ll lower-buffer-fat-pointers-mem-transfer.ll

[LowerMemIntrinsics][AMDGPU] Optimize memset.pattern lowering (#185901)

This patch changes the lowering of the [experimental.memset.pattern intrinsic](https://llvm.org/docs/LangRef.html#llvm-experimental-memset-pattern-intrinsic)
to match the optimized memset and memcpy lowering when possible. (The tl;dr of
memset.pattern is that it is like memset, except that you can use it to set
values that are wider than a single byte.)

The memset.pattern lowering now queries `TTI::getMemcpyLoopLoweringType` for a
preferred memory access type. If the size of that type is a multiple of the set
value's type, and if both types have consistent store and alloc sizes (since
memset.pattern behaves in a way that is not well suitable for access widening
if store and alloc size differ), the memset.pattern is lowered into two loops:
a main loop that stores a sufficiently wide vector splat of the SetValue with
the preferred memory access type and a residual loop that covers the remaining
set values individually.

In contrast to the memset lowering, this patch doesn't include a specialized
lowering for residual loops with known constant lengths. Loops that are
statically known to be unreachable will not be emitted.

    [6 lines not shown]
DeltaFile
+1,100-0llvm/test/CodeGen/AMDGPU/memset-pattern.ll
+273-0llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/memset-pattern.ll
+105-56llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
+104-30llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
+31-31llvm/test/CodeGen/RISCV/memset-pattern.ll
+14-14llvm/test/Transforms/PreISelIntrinsicLowering/RISCV/memset-pattern.ll
+1,627-1315 files not shown
+1,652-14511 files

LLVM/project 26ac669llvm/test/Analysis/CostModel/X86 arith-fp.ll fround.ll, llvm/test/CodeGen/Mips nmadd.ll

[LLVM] Remove "no-nans-fp-math" attribute support (#186285)

Now all `NoNaNsFPMath` uses have been removed, remove this attribute.
DeltaFile
+0-42llvm/test/Transforms/Inline/attributes.ll
+11-11llvm/test/CodeGen/Mips/nmadd.ll
+10-10llvm/test/Analysis/CostModel/X86/arith-fp.ll
+0-18mlir/test/Target/LLVMIR/fp-math-function-attributes.mlir
+9-9llvm/test/Analysis/CostModel/X86/fround.ll
+2-15llvm/test/CodeGen/X86/fabs.ll
+32-10533 files not shown
+71-21339 files

FreeBSD/src b4d8d9bcontrib/jemalloc/src jemalloc.c

rallocx path: only set errno on the realloc case.

PR:             291677
Obtained from:  jemalloc (commit 83b075789b4239035931c1ee212576d00153bbf0)
Fixes:          c43cad871720 ("jemalloc: Merge from jemalloc 5.3.0 vendor branch")
MFC after:      3 days
Pull Request:   https://github.com/freebsd/freebsd-src/pull/2059

(cherry picked from commit 2c5cd07828ad76c332e3bedc29fc641809e85396)
DeltaFile
+3-1contrib/jemalloc/src/jemalloc.c
+3-11 files

NetBSD/pkgsrc QubH1PYdoc CHANGES-2026

   Updated lang/nodejs20, devel/capnproto
VersionDeltaFile
1.1722+3-1doc/CHANGES-2026
+3-11 files

FreeBSD/src 3abef03contrib/jemalloc/src jemalloc.c

Set errno to ENOMEM on rallocx() OOM failures

realloc() and rallocx() shares path, and realloc() should set errno to
ENOMEM upon OOM failures.

PR:             291677
Obtained from:  jemalloc (commit 38056fea64c34ca4fef0a16212776eaa4de80b78)
Fixes:          c43cad871720 ("jemalloc: Merge from jemalloc 5.3.0 vendor branch")
MFC after:      3 days
Pull Request:   https://github.com/freebsd/freebsd-src/pull/2059

(cherry picked from commit 5583b64f230fe0ea4e3d4bf4566205b521190fbb)
DeltaFile
+1-0contrib/jemalloc/src/jemalloc.c
+1-01 files

NetBSD/pkgsrc dcajxO2devel/capnproto distinfo Makefile

   capnproto: updated to 1.4.0

   1.4.0
   Unknown changes
VersionDeltaFile
1.8+4-4devel/capnproto/distinfo
1.12+2-2devel/capnproto/Makefile
+6-62 files

LLVM/project 0e9f653clang/lib/Serialization ASTWriter.cpp, clang/test/Modules pr184957.cppm no-transitive-decl-change-4.cppm

[C++20] [Modules] [Reduced BMI] Try not write merged lookup table (#186337)

Update:

Close https://github.com/llvm/llvm-project/issues/184957

The roo cause of the problem is reduced BMI may not emit everything in
the lookup table, if Reduced BMI **partially** emits some decls, then
the generator may not emit the corresponding entry for the corresponding
name is already there. See
MultiOnDiskHashTableGenerator::insert and
MultiOnDiskHashTableGenerator::emit for details. So we won't emit the
lookup
table if we're generating reduced BMI.
DeltaFile
+216-0clang/test/Modules/pr184957.cppm
+35-9clang/lib/Serialization/ASTWriter.cpp
+1-1clang/test/Modules/no-transitive-decl-change-4.cppm
+252-103 files

LLVM/project 584f43cllvm/test/Verifier gc_relocate_out_of_bounds.ll

[Verifier] Add test for out of bounds gc.relocate reference
DeltaFile
+19-0llvm/test/Verifier/gc_relocate_out_of_bounds.ll
+19-01 files

LLVM/project 4e46eb7clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

more fmt
DeltaFile
+2-2clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+2-21 files

LLVM/project 3179726libc/src/string/memory_utils utils.h, libc/test/src/string/memory_utils utils_test.cpp

[libc] Fix load_aligned big-endian handling. (#185937)

The variadic template helper `load_aligned` performs a specific case of
an unaligned integer load, by loading a sequence of integers from memory
at addresses expected to be aligned, and glues the results back together
with shifts and ORs into an output.

The implementation works by performing the first load, recursing on a
shorter parameter type list for the rest, and recombining via

  first | (rest << size_of_first)           // if little-endian
  (first << size_of_first) | rest           // if big-endian

But the big-endian case is wrong: it should shift left by the size of
the _rest_ of the types, not the size of the first. In the case where
you load 8, 16 and 8 bits from an odd address, you want

  (first_byte << 24) | (middle_halfword << 8) | (last_byte)


    [5 lines not shown]
DeltaFile
+18-0libc/test/src/string/memory_utils/utils_test.cpp
+9-4libc/src/string/memory_utils/utils.h
+27-42 files

LLVM/project 93703b3llvm/test/CodeGen/AMDGPU memset-pattern.ll

Use inreg for AS7 pointer arguments to make them wave-uniform
DeltaFile
+296-1,007llvm/test/CodeGen/AMDGPU/memset-pattern.ll
+296-1,0071 files