[alpha.webkit.RetainPtrCtorAdoptChecker] Don't treat calling (void)copy:(id) as a leak (#179713)
UIResponderStandardEditActions defines (void)copy:(id)sender but this
selector should not be treated as a copy operation since it's a "copy"
in the sense of application triggering copy & paste for the system
pasteboard.
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
[AArch64] Add test coverage for funnel shift with undef amount. NFC (#179888)
Precommit tests for #57256 showing inconsistencies between SDAG and
GISel for funnel shift with undef amount. GISel is wrong and should
match SDAG.
[X86] lower1BitShuffle - recognise a blend shuffle that can lower to AND/MASKZ pattern (#179717)
Part of the missed-optimisation mentioned on #179630 - if the shuffle is
a blend with zero, then lower as a ISD::AND pattern
[lldb] [Process/FreeBSDKernel] List threads in correct order (#178306)
In FreeBSD, allproc is a prepend list and new processes are appended at
head. This results in reverse pid order, so we first need to order pid
incrementally then print threads according to the correct order.
Before:
```
Process 0 stopped
* thread #1: tid = 101866, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff8015882f780, flags=259) at sched_ule.c:2448:26, name = '(pid 12991) dtrace'
thread #2: tid = 101915, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff80158825780, flags=259) at sched_ule.c:2448:26, name = '(pid 11509) zsh'
thread #3: tid = 101942, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff80142599000, flags=259) at sched_ule.c:2448:26, name = '(pid 11504) ftcleanup'
thread #4: tid = 101545, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff80131898000, flags=259) at sched_ule.c:2448:26, name = '(pid 5599) zsh'
thread #5: tid = 100905, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff80131899000, flags=259) at sched_ule.c:2448:26, name = '(pid 5598) sshd-session'
thread #6: tid = 101693, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff8015886e780, flags=259) at sched_ule.c:2448:26, name = '(pid 5595) sshd-session'
thread #7: tid = 101626, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff801588be000, flags=259) at sched_ule.c:2448:26, name = '(pid 5592) sh'
...
```
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[AMDGPU][GFX12.5] Reimplement monitor load as an atomic operation
Load monitor operations make more sense as atomic operations, as
non-atomic operations cannot be used for inter-thread communication w/o
additional synchronization.
The previous built-in made it work because one could just override the CPol
bits, but that bypasses the memory model and forces the user to learn about
ISA bits encoding.
Making load monitor an atomic operation has a couple of advantages. First,
the memory model foundation for it is stronger. We just lean on the existing
rules for atomic operations. Second, the CPol bits are abstracted away from
the user, which avoids leaking ISA details into the API.
This patch also adds supporting memory model and intrinsics documentation to
AMDGPUUsage.
Solves SWDEV-516398.
[AMDGPU][PromoteAlloca] Set !amdgpu.non.volatile if promotion fails
I thought about doing this in a separate pass, but this pass already has all the necessary analysis for this to be a trivial addition.
We can simply set `!amdgpu.non.volatile` if all other attempts to promote the operation failed.
[AMDGPU][GFX12.5] Add support for emitting memory operations with nv bit set
- Add & document `!amdgpu.non.volatile` metadata and a corresponding `MONonVolatile` MachineMemOperand flag.
- Set nv=1 on memory operations on GFX12.5 if the operation accesses a constant address space,
is an invariant load, or has the `MONonVolatile` flag set.
[AMDGPU] Set MONonVolatile on memory accesses for spills
Mark the memory operand of spill load/stores as non-volatile, so that these
loads and stores are emitted with `nv` set.
The reason is that scratch memory used by spills will never be shared by
another thread. It's purely thread local and thus a good fit for the `nv` bit.
