LLVM/project ae78759llvm/test/CodeGen/AArch64 mul-i128-overflow.ll overflow.ll

[AArch64][GlobalISel] Update and extend the test coverage for overflow intrinsics. NFC (#222059)
DeltaFile
+4,997-0llvm/test/CodeGen/AArch64/overflow-vec.ll
+1,653-1,679llvm/test/CodeGen/AArch64/arm64-xaluo.ll
+122-63llvm/test/CodeGen/AArch64/i128-math.ll
+120-61llvm/test/CodeGen/AArch64/i256-math.ll
+0-26llvm/test/CodeGen/AArch64/overflow.ll
+9-1llvm/test/CodeGen/AArch64/mul-i128-overflow.ll
+6,901-1,8301 files not shown
+6,901-1,8327 files

LLVM/project 7cc5cfbllvm/include/llvm/Frontend/OpenMP OMPKinds.def, llvm/lib/Transforms/IPO OpenMPOpt.cpp

[OpenMPOpt] Look inside the callbacks the loop runtime functions are handed

The __kmpc_{distribute_,for_,distribute_for_}static_loop_* functions receive the
loop body as a callback, so a parallel region written inside that body is
reachable from the kernel through the runtime call. AAKernelInfo could not see
that, and recorded the call as reaching an unknown parallel region. A kernel
using these functions therefore always got a worker state machine whose only
option was to indirectly call whatever work function it was handed.

Describe the callback argument of each of these functions in OMPKinds.def and
attach the corresponding !callback metadata in OpenMPOpt, then fold the
callback's AAKernelInfo state into the caller's. The state machine can now
dispatch directly to the regions the loop body actually reaches. Relax the two
"more than one callee means give up" checks for functions carrying !callback,
since the callback edge is a second edge by construction and is analyzable.

The conservative unknown-region record is kept for the case that motivated it, a
callback we only see a declaration of.


    [37 lines not shown]
DeltaFile
+243-0llvm/test/Transforms/OpenMP/callback_parallel_regions.ll
+104-10llvm/lib/Transforms/IPO/OpenMPOpt.cpp
+51-0llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
+48-0offload/test/offloading/fortran/target-teams-distribute-nested-parallel-do.f90
+446-104 files

LLVM/project 413b182clang-tools-extra/docs/clang-tidy/checks/readability implicit-bool-conversion.md function-cognitive-complexity.md

~
DeltaFile
+959-397clang-tools-extra/docs/clang-tidy/checks/readability/identifier-naming.md
+42-17clang-tools-extra/docs/clang-tidy/checks/readability/identifier-length.md
+20-6clang-tools-extra/docs/clang-tidy/checks/readability/magic-numbers.md
+17-1clang-tools-extra/docs/clang-tidy/checks/readability/function-size.md
+8-2clang-tools-extra/docs/clang-tidy/checks/readability/function-cognitive-complexity.md
+8-0clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.md
+1,054-4231 files not shown
+1,058-4237 files

LLVM/project 14e941aopenmp/libompd/gdb-plugin ompdAPITests.c ompdDLService.h, openmp/libompd/test lit.cfg ompd_dl_service.c

[OpenMP][OMPD] Add symbol lookup helper for GDB plugin (#221956)

On LLVM today, `libompd.so` exists with `dlopen`, finds each API with
`dlsym` and checks error with `dlerror`.

**Missing piece**: There is no single place that:

load this library
look up this name
give me a real error string

**Issues**:

A later change would have to edit 30+ calls sites,
`dlerror()` is easy to misuse, 
failures often drop the OS error string.

**Fix**: Add these helpers:
 

    [5 lines not shown]
DeltaFile
+97-82openmp/libompd/gdb-plugin/ompdModule.c
+87-0openmp/libompd/gdb-plugin/ompdDLService.c
+55-0openmp/libompd/test/ompd_dl_service.c
+40-0openmp/libompd/gdb-plugin/ompdDLService.h
+17-0openmp/libompd/test/lit.cfg
+7-4openmp/libompd/gdb-plugin/ompdAPITests.c
+303-862 files not shown
+310-898 files

LLVM/project 97195b2mlir/lib/Dialect/Vector/IR VectorOps.cpp, mlir/test/Dialect/Vector canonicalize.mlir

[mlir][vector] Extend `ShapeCastCreateMaskFolderTrailingOneDim` (#219494)

Extends `ShapeCastCreateMaskFolderTrailingOneDim` so that it also works
for leading unit dims. For example,
```mlir
  %1 = vector.create_mask %c1, %c1, %dim, %c1 : vector<1x1x[4]x1xi1>
  %2 = vector.shape_cast %1 : vector<1x1x[4]x1xi1> to vector<[4]x1xi1>
```

is folded as:
```mlir
  %0 = vector.create_mask %c1, %dim : vector<[4]xi1>
```

To better reflect the extended functionality, the updated pattern is
renamed as:
* `ShapeCastCreateMaskFolderBoundaryUnitDim`.

It takes a template parameter to specify whether to consider
the leading or the trailing unit dims.
DeltaFile
+101-35mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+81-10mlir/test/Dialect/Vector/canonicalize.mlir
+182-452 files

LLVM/project 00d831fclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

[CIR][NFC] Fix build issue after Inlineasm convergent attr (#222041)

Fix build error after introducing InlineAsm convergent attribute in
https://github.com/llvm/llvm-project/pull/221990
DeltaFile
+2-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+2-01 files

LLVM/project ff188e2llvm/lib/CodeGen TwoAddressInstructionPass.cpp, llvm/test/CodeGen/AMDGPU early-lis-two-address-regsequence-undef.mir

TwoAddressInstruction: Don't repair the unchanged def of a degenerate REG_SEQUENCE

When every source operand of a REG_SEQUENCE is undef, eliminateRegSequence emits
no COPY and rewrites the instruction in place to an IMPLICIT_DEF. The dead def of
DstReg is left untouched, so its live range is already correct. Passing DstReg to
repairIntervalsInRange then makes it re-add an overlapping segment with a fresh
value for the unchanged def, asserting in LiveInterval::addSegment.

Drop DstReg from the repaired set in this case. Exposed by -early-live-intervals

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+21-0llvm/test/CodeGen/AMDGPU/early-lis-two-address-regsequence-undef.mir
+5-0llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+26-02 files

LLVM/project 028cdb4.github/workflows libcxx-pr-test-tools.yml libcxx-pr-conformance-tests.yaml

[libcxx] Move premerge jobs to k8s mode runner set (#221395)

This allows setting the container image in the workflow definition which
should vastly simplify maintenance. The issues that we were running into
previously with jobs randomly aborting (and getting marked as passed)
have been fixed with some cluster-side config changes.
DeltaFile
+12-3.github/workflows/libcxx-pr-conformance-tests.yaml
+5-1.github/workflows/libcxx-pr-test-tools.yml
+17-42 files

FreeNAS/freenas 127e755src/freenas/usr/local/bin truenas-hw-license.py, src/middlewared/middlewared/plugins/truenas license.py

NAS-143111 / 26.0.0-RC.1 / Write a hardware entitlement record on unlicensed iX appliances (by sonicaj) (#19656)

This PR adds changes to give an iX appliance that shipped without a
license a minimal legacy license record during upgrade, written by a new
script that runs chrooted in the new boot environment. The record is
stamped with a marker in customer_key, and parse_legacy_license grants
it exactly what bare appliance hardware already gives rather than
everything a legacy license implies. SED is the motivating case, since
its vector moves to hardware plus key later and these machines would
otherwise lose it.

LicenseInfo grows an origin field so we can tell a record we wrote from
one an issuer signed. Entitlements never read it, since a system
generated record has to resolve exactly as an issued one does; it is
there for the alert source, the unlicensed to licensed hook, TNC, and
support tickets, which all mean "iX issued this".


Original PR: https://github.com/truenas/middleware/pull/19643

    [3 lines not shown]
DeltaFile
+105-0src/freenas/usr/local/bin/truenas-hw-license.py
+32-8src/middlewared/middlewared/utils/license/legacy.py
+28-1src/middlewared/middlewared/plugins/truenas/license.py
+18-1src/middlewared/middlewared/utils/license/types.py
+6-3src/middlewared/middlewared/pytest/unit/plugins/test_truenas_connect.py
+6-3src/middlewared/middlewared/plugins/truenas_connect/register.py
+195-1614 files not shown
+233-2920 files

LLVM/project d3bd9e9libcxx/docs Contributing.md AddingNewCIJobs.md, libcxx/docs/DesignDocs ExperimentalFeatures.md FeatureTestMacros.md

[libc++][docs] Finish MyST migration
DeltaFile
+36-38libcxx/docs/ABIGuarantees.md
+8-9libcxx/docs/DesignDocs/FeatureTestMacros.md
+5-5libcxx/docs/CodingGuidelines.md
+3-4libcxx/docs/DesignDocs/ExperimentalFeatures.md
+2-3libcxx/docs/Contributing.md
+2-3libcxx/docs/AddingNewCIJobs.md
+56-6210 files not shown
+63-7416 files

LLVM/project 888c6dcflang/lib/Optimizer/Transforms/CUDA CUFDeviceGlobal.cpp CUFAddConstructor.cpp, flang/test/Fir/CUDA cuda-device-global.f90

[flang][cuda] Add compiler generated global to unified register global (#221135)

Treat compiler generated global the same way as other in unified mode.
Host has the initializer body and the device side is just a declaration.
DeltaFile
+19-0flang/test/Fir/CUDA/cuda-device-global.f90
+4-1flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
+3-1flang/lib/Optimizer/Transforms/CUDA/CUFDeviceGlobal.cpp
+26-23 files

LLVM/project 121656dflang/test/Fir/OpenACC acc-declare-gpu-module-insertion.fir, mlir/lib/Dialect/OpenACC/Transforms ACCDeclareGPUModuleInsertion.cpp

[mlir][openacc] Handle compiler generated global for unified mode (#221136)

Treat compiler generated global the same way as other global in unified
mode. This avoid having a host and device copy for runtime information
like type descriptors.
DeltaFile
+19-3flang/test/Fir/OpenACC/acc-declare-gpu-module-insertion.fir
+2-1mlir/lib/Dialect/OpenACC/Transforms/ACCDeclareGPUModuleInsertion.cpp
+21-42 files

LLVM/project feca7eelibcxx/docs FeatureTestMacroTable.md

[libc++][docs] Convert generated feature-test documentation with rst2myst
DeltaFile
+10-11libcxx/docs/FeatureTestMacroTable.md
+10-111 files

LLVM/project d1784aflibcxx/docs FeatureTestMacroTable.md, libcxx/utils generate_feature_test_macro_components.py

[libc++][docs] Generate the feature-test macro table as Markdown
DeltaFile
+284-562libcxx/docs/FeatureTestMacroTable.md
+95-102libcxx/utils/generate_feature_test_macro_components.py
+379-6642 files

LLVM/project 2dacb2blibcxx/docs conf.py FeatureTestMacroTable.rst, libcxx/utils generate_feature_test_macro_components.py

[libc++][docs] Rename generated feature-test documentation to Markdown
DeltaFile
+0-579libcxx/docs/FeatureTestMacroTable.rst
+579-0libcxx/docs/FeatureTestMacroTable.md
+1-1libcxx/utils/generate_feature_test_macro_components.py
+1-1libcxx/docs/conf.py
+581-5814 files

LLVM/project 295d2balibcxx/docs Hardening.rst Hardening.md

[libc++][docs] Rename documentation files to Markdown (batch 2)
DeltaFile
+0-676libcxx/docs/VendorDocumentation.rst
+676-0libcxx/docs/VendorDocumentation.md
+0-591libcxx/docs/TestingLibcxx.rst
+591-0libcxx/docs/TestingLibcxx.md
+0-575libcxx/docs/Hardening.rst
+575-0libcxx/docs/Hardening.md
+1,842-1,84226 files not shown
+3,490-3,49032 files

LLVM/project c237f0flibcxx/docs index.md Hardening.md

[libc++][docs] Convert documentation with rst2myst (batch 2)
DeltaFile
+384-405libcxx/docs/VendorDocumentation.md
+255-280libcxx/docs/TestingLibcxx.md
+220-221libcxx/docs/UserDocumentation.md
+210-208libcxx/docs/Modules.md
+174-183libcxx/docs/Hardening.md
+122-143libcxx/docs/index.md
+1,365-1,4409 files not shown
+1,639-1,76515 files

LLVM/project e1f8025libcxx/docs index.md Modules.md, libcxx/docs/DesignDocs VisibilityMacros.md

[libc++][docs] Finish MyST migration (batch 2)
DeltaFile
+141-145libcxx/docs/Hardening.md
+85-93libcxx/docs/TestingLibcxx.md
+62-62libcxx/docs/UserDocumentation.md
+51-52libcxx/docs/Modules.md
+14-15libcxx/docs/DesignDocs/VisibilityMacros.md
+6-3libcxx/docs/index.md
+359-3703 files not shown
+363-3779 files

LLVM/project 779191blibcxx/docs Contributing.rst Contributing.md, libcxx/docs/DesignDocs FileTimeType.rst FileTimeType.md

[libc++][docs] Rename documentation files to Markdown (batch 1)
DeltaFile
+0-797libcxx/docs/DesignDocs/AtomicDesign.rst
+797-0libcxx/docs/DesignDocs/AtomicDesign.md
+0-495libcxx/docs/DesignDocs/FileTimeType.rst
+495-0libcxx/docs/DesignDocs/FileTimeType.md
+0-349libcxx/docs/Contributing.rst
+349-0libcxx/docs/Contributing.md
+1,641-1,64126 files not shown
+2,883-2,88332 files

LLVM/project 155cedelibcxx/docs ABIGuarantees.md CodingGuidelines.md, libcxx/docs/DesignDocs ExperimentalFeatures.md FileTimeType.md

[libc++][docs] Convert documentation with rst2myst
DeltaFile
+608-614libcxx/docs/DesignDocs/AtomicDesign.md
+271-292libcxx/docs/DesignDocs/FileTimeType.md
+153-163libcxx/docs/Contributing.md
+119-138libcxx/docs/DesignDocs/ExperimentalFeatures.md
+104-119libcxx/docs/CodingGuidelines.md
+107-114libcxx/docs/ABIGuarantees.md
+1,362-1,4409 files not shown
+1,568-1,67215 files

FreeNAS/freenas d1a1037

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 46dbe3bsrc/freenas/usr/local/bin truenas-hw-license.py, src/middlewared/middlewared/plugins/truenas license.py

Log a preformatted message from the hardware entitlement script

This commit makes some changes where the script's outcome record was a JSON document whose schema was restated on the reading side, even though the file has exactly one consumer and that consumer deletes it on first boot. It now writes a single preformatted line, only when something actually failed, and middleware logs it verbatim.

Dropping the benign outcomes leaves the unknown-chassis, Mini and ineligible-platform branches doing nothing but returning, and the allowlist check already rejects all three, so they collapse into it.

(cherry picked from commit 4cef70e260a0bc85d5eed409ceb6d4d8bbef9e60)
DeltaFile
+14-55src/freenas/usr/local/bin/truenas-hw-license.py
+8-18src/middlewared/middlewared/plugins/truenas/license.py
+2-2src/middlewared/middlewared/utils/license/constants.py
+2-2src/middlewared/middlewared/utils/license/__init__.py
+26-774 files

FreeNAS/freenas 164bf0fsrc/freenas/usr/local/bin truenas-hw-license.py, src/middlewared/middlewared/plugins/truenas license.py

Record what the hardware entitlement script did on upgrade

This commit adds changes to leave a record under /data of every outcome from truenas-hw-license.py, since the installer discards the script's output and a failure to write the entitlement record was previously invisible. Middleware relays it into middlewared.log on first boot and then deletes it, and only says anything when the record carries an error.

Every outcome is recorded rather than just the failures because a chassis reading as unknown is indistinguishable in the script from dmidecode having failed, so which outcomes deserve attention is better decided in middleware.

Both writes now go through atomic_write instead of a hand-rolled open with fchmod and fchown, matching truenas-nvdimm.py which already uses it from the same chroot. That also closes a window where a failed write left behind a permanent zero-byte /data/license that no later upgrade would have retried.

(cherry picked from commit 9b62f94dbf19ac7f46647e4316be89ef85395825)
DeltaFile
+50-20src/freenas/usr/local/bin/truenas-hw-license.py
+35-0src/middlewared/middlewared/plugins/truenas/license.py
+3-0src/middlewared/middlewared/utils/license/constants.py
+2-0src/middlewared/middlewared/utils/license/__init__.py
+90-204 files

FreeNAS/freenas b221d05src/freenas/usr/local/bin truenas-hw-license.py, src/middlewared/middlewared/alert/source license_status.py

Distinguish system-generated license records from issued ones

This commit adds changes to record where a license record came from, since we now write one ourselves during upgrade on unlicensed appliance hardware and several consumers were treating it as though iX had issued it.

Entitlement resolution deliberately ignores the origin - a system-generated record is meant to resolve exactly as an issued one does. This only changes alerting, the unlicensed to licensed transition hook, and what we report outward to TrueNAS Connect and support.

(cherry picked from commit c677fe372fa16ece76e6abb51a39e0912e5afe3d)
DeltaFile
+11-11src/middlewared/middlewared/utils/license/legacy.py
+18-1src/middlewared/middlewared/utils/license/types.py
+6-3src/middlewared/middlewared/plugins/truenas_connect/register.py
+5-3src/middlewared/middlewared/pytest/unit/plugins/test_truenas_connect.py
+4-3src/freenas/usr/local/bin/truenas-hw-license.py
+4-1src/middlewared/middlewared/alert/source/license_status.py
+48-225 files not shown
+61-2811 files

FreeNAS/freenas b09269esrc/middlewared/middlewared/pytest/unit entitlements.py, src/middlewared/middlewared/pytest/unit/plugins/truenas test_entitlements_api.py

Require an explicit origin on every license record

This commit adds changes to drop the default on LicenseInfo.origin so every construction site has to state whether the record was issued or system-generated, instead of the daemon path inheriting ISSUED by omission.

The test factory in pytest/unit/entitlements.py takes origin as a parameter rather than hardcoding it, so a SYSTEM_GENERATED license can be constructed at all - it currently has no coverage anywhere. A side effect is that the legacy-parse and from_license_status equality assertions now genuinely pin origin, where before both sides of the comparison inherited the same default.

(cherry picked from commit 65d699a13b59bae8af6f07d8687cfa457ae41e24)
DeltaFile
+3-1src/middlewared/middlewared/pytest/unit/utils/test_license_utils.py
+3-1src/middlewared/middlewared/pytest/unit/entitlements.py
+2-1src/middlewared/middlewared/utils/license/daemon.py
+2-1src/middlewared/middlewared/pytest/unit/utils/test_get_license.py
+2-1src/middlewared/middlewared/pytest/unit/plugins/truenas/test_entitlements_api.py
+3-0src/middlewared/middlewared/pytest/unit/utils/test_license_legacy_utils.py
+15-54 files not shown
+21-810 files

FreeNAS/freenas 1874c58src/freenas/usr/local/bin truenas-hw-license.py, src/middlewared/middlewared/utils/license legacy.py

Write a legacy license record on unlicensed iX appliances

This commit adds changes to write a minimal legacy license record during upgrade on iX appliance hardware that carries no license at all, so those systems resolve entitlements as licensed hardware and future features have somewhere to be gated. Which features the record actually carries is deliberately minimal for now and a separate decision.

The record is stamped with a marker in customer_key so legacy normalization can tell it apart from a license an issuer signed, and it carries an empty HA serial so the parsed type stays ENTERPRISE_SINGLE and failover.licensed remains false.

(cherry picked from commit 0df55557ed90e72fe940330102d8ba7a0d609c06)
DeltaFile
+115-0src/freenas/usr/local/bin/truenas-hw-license.py
+30-6src/middlewared/middlewared/utils/license/legacy.py
+145-62 files

FreeNAS/freenas f5f9fe5src/freenas/usr/local/bin truenas-hw-license.py, src/middlewared/middlewared/plugins/truenas license.py

NAS-143111 / 26.0.0 / Write a hardware entitlement record on unlicensed iX appliances (#19643)

This PR adds changes to give an iX appliance that shipped without a
license a minimal legacy license record during upgrade, written by a new
script that runs chrooted in the new boot environment. The record is
stamped with a marker in customer_key, and parse_legacy_license grants
it exactly what bare appliance hardware already gives rather than
everything a legacy license implies. SED is the motivating case, since
its vector moves to hardware plus key later and these machines would
otherwise lose it.

LicenseInfo grows an origin field so we can tell a record we wrote from
one an issuer signed. Entitlements never read it, since a system
generated record has to resolve exactly as an issued one does; it is
there for the alert source, the unlicensed to licensed hook, TNC, and
support tickets, which all mean "iX issued this".
DeltaFile
+105-0src/freenas/usr/local/bin/truenas-hw-license.py
+32-8src/middlewared/middlewared/utils/license/legacy.py
+28-1src/middlewared/middlewared/plugins/truenas/license.py
+18-1src/middlewared/middlewared/utils/license/types.py
+6-3src/middlewared/middlewared/pytest/unit/plugins/test_truenas_connect.py
+6-3src/middlewared/middlewared/plugins/truenas_connect/register.py
+195-1614 files not shown
+233-2920 files

LLVM/project 841d4adclang/test/OpenMP distribute_parallel_for_simd_num_threads_codegen.cpp teams_distribute_parallel_for_simd_if_codegen.cpp

[Clang][OpenMP] Don't mark outlined parallel region functions norecurse (#218862)

Clang marks every outlined OpenMP region function `norecurse`, in both
`emitOutlinedFunctionPrologue` and
`emitOutlinedFunctionPrologueAggregate`, and
does the same for the GPU parallel wrapper. For a `parallel` region that
is not
true: the body is reached through the function pointer the runtime is
handed, and
if the body opens another parallel region the runtime's parallel entry
is
re-entered while the first call is still live, so the entry and the body
sit in a
call graph cycle. `rpo-function-attrs` propagates the annotation off the
body and
onto the device runtime's parallel entry once internalization makes it
internal,
and a nested parallel region can then be folded away.


    [18 lines not shown]
DeltaFile
+588-588clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+568-568clang/test/OpenMP/teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+455-455clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
+449-449clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
+445-445clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
+357-357clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp
+2,862-2,862111 files not shown
+5,039-5,134117 files

LLVM/project 1b59b61llvm/lib/CodeGen RegisterCoalescer.cpp, llvm/test/CodeGen/AArch64 coalescer-empty-subrange-early-lis.ll

RegisterCoalescer: Remove empty subranges after merging subranges

Merging subranges in joinVirtRegs didn't try to clear empty ranges after
refineSubRanges, manifesting in an assert in overlaps checks later.

Exposed with subregister liveness once LiveIntervals runs before TwoAddress.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+30-0llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
+3-0llvm/lib/CodeGen/RegisterCoalescer.cpp
+33-02 files

LLVM/project 5d53653clang/include/clang/Options FlangOptions.td, flang/docs ReleaseNotes.md

[flang] Enable FP sum reassociation by default (#218746)

Enable Fortran-standard-compliant reassociation within individual REAL
and COMPLEX sum expressions by default at all optimisation levels.
Preserve the explicit positive and negative Flang override flags.

Also enable by default on bbc to match flang.

RFC:
https://discourse.llvm.org/t/rfc-flang-reasssociate-within-real-and-complex-expressions-by-default/91626

Assisted-by: Codex
DeltaFile
+6-6flang/test/Lower/math-lowering/exponentiation.f90
+6-3flang/test/Lower/split-sum-expression-tree-lowering.f90
+7-0flang/tools/bbc/bbc.cpp
+3-2clang/include/clang/Options/FlangOptions.td
+5-0flang/docs/ReleaseNotes.md
+2-0flang/test/Driver/driver-help.f90
+29-111 files not shown
+30-127 files