LLVM/project 7176158 — clang/lib/AST/ByteCode Interp.cpp, clang/test/AST/ByteCode typeid.cpp

by Timm Baeder via GitHub on ⎇
[clang][bytecode] Improve diagnostics on typeid field access (#209101)

Do some extra work to extract the requested field name.
DeltaFile
+32-6clang/lib/AST/ByteCode/Interp.cpp
+5-0clang/test/AST/ByteCode/typeid.cpp
+37-62 files

LLVM/project 217d8da — llvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

by Lucas Ramirez on ⎇
Use a union instead of void* + static_cast for InsertBeforePos
DeltaFile
+32-17llvm/include/llvm/CodeGen/Rematerializer.h
+5-8llvm/lib/CodeGen/Rematerializer.cpp
+1-0llvm/unittests/CodeGen/RematerializerTest.cpp
+38-253 files

NetBSD/pkgsrc-wip 982d55b — . TODO, neatvnc distinfo Makefile

by Thomas Klausner on ⎇
neatvnc: update to 1.0.1
DeltaFile
+3-3neatvnc/distinfo
+1-1neatvnc/Makefile
+0-1TODO
+4-53 files

NetBSD/pkgsrc-wip 08a4461 — . TODO, wayvnc distinfo Makefile

by Thomas Klausner on ⎇
wayvnc: update to 0.10.1
DeltaFile
+3-3wayvnc/distinfo
+1-1wayvnc/Makefile
+0-1TODO
+4-53 files

LLVM/project f22a217 — offload/test lit.cfg

by Robert Imschweiler on ⎇
[offload][test] Add fallback to legacy AMDGPU triple library dir

After the amdgcn-amd-amdhsa -> amdgpu-amd-amdhsa rename, look up the
device runtime libraries in the legacy directory when the runtime was
built under the old triple name.

Claude assisted with this patch.
DeltaFile
+10-3offload/test/lit.cfg
+10-31 files

LLVM/project b563449 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU global-atomicrmw-fadd.ll bf16.ll

by Harrison Hao on ⎇
[AMDGPU] Use v_pk_add_bf16 for scalar bf16 fadd on gfx1250/gfx13
DeltaFile
+39-68llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+56-34llvm/test/CodeGen/AMDGPU/bf16.ll
+28-36llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+49-0llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-bf16.ll
+13-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+11-1llvm/lib/Target/AMDGPU/SIInstructions.td
+196-1392 files not shown
+209-1418 files

LLVM/project 19f9973 — llvm/lib/Target/SPIRV SPIRVBuiltins.cpp

by Arseniy Obolenskiy via GitHub on ⎇
[NFC][SPIR-V] Remove unused LowLevelType parameter from buildLoadInst (#208428)
DeltaFile
+5-6llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+5-61 files

LLVM/project dc8ee15 — mlir/lib/Conversion/SPIRVToLLVM SPIRVToLLVM.cpp, mlir/test/Conversion/SPIRVToLLVM arithmetic-ops-to-llvm.mlir

by Arseniy Obolenskiy via GitHub on ⎇
[mlir][SPIR-V] Add SPIRVToLLVM conversion for SNegate (#206950)
DeltaFile
+40-24mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+20-0mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
+60-242 files

LLVM/project d0ac84b — lldb/test/API/functionalities/gdb_remote_client TestXMLRegisterFlags.py

by David Spickett via GitHub on ⎇
[lldb][test] Fix XML register info test (#209124)

Missed by #208838, which is a follow up to #188049 which changed the
alignment rules.

Some of these tests have incorrect outputs now
and I will fix that later. For now at least
they pass again.

XML related tests are not being run in CI,
which I will also address later.
DeltaFile
+4-4lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py
+4-41 files

LLVM/project f8b0713 — llvm/lib/Target/SPIRV SPIRVAsmPrinter.cpp

by Arseniy Obolenskiy via GitHub on ⎇
[NFC][SPIR-V] Add emitSimpleExecutionMode helper to dedup single imm OpExecutionMode emission (#208674)
DeltaFile
+15-28llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
+15-281 files

FreeBSD/ports 123a28e — deskutils/latte-dock Makefile

by Max Brazhnikov (makc) on ⎇
deskutils/latte-dock: Schedule for removal before Q4

The project is abandoned
DeltaFile
+3-0deskutils/latte-dock/Makefile
+3-01 files

FreeBSD/ports c387677 — sysutils/plasma5-libksysguard Makefile

by Max Brazhnikov (makc) on ⎇
sysutils/plasma5-libksysguard: Remove option for Qt5WebEngine
DeltaFile
+4-5sysutils/plasma5-libksysguard/Makefile
+4-51 files

FreeBSD/ports 9cc1299 — graphics/peruse Makefile

by Max Brazhnikov (makc) on ⎇
graphics/peruse: Schedule for removal before Q4

The project is abandoned, Qt6 port is not usable.
DeltaFile
+3-0graphics/peruse/Makefile
+3-01 files

FreeBSD/ports 7393299 — devel/elf-dissector pkg-plist Makefile, devel/elf-dissector/files patch-src_lib_disassembler_disassembler.cpp

by Max Brazhnikov (makc) on ⎇
devel/elf-dissector: Update to the latest commit and switch to Qt6

- Remove unused dependencies
- Drop stale patch
DeltaFile
+35-2devel/elf-dissector/pkg-plist
+9-8devel/elf-dissector/Makefile
+0-11devel/elf-dissector/files/patch-src_lib_disassembler_disassembler.cpp
+3-3devel/elf-dissector/distinfo
+47-244 files

FreeBSD/ports 23b97aa — multimedia/kaffeine pkg-plist Makefile, multimedia/kaffeine/files patch-src_CMakeLists.txt

by Max Brazhnikov (makc) on ⎇
multimedia/kaffeine: Update to 2.1.0 and switch to Qt6

- Update WWW and LICENSE.
DeltaFile
+21-46multimedia/kaffeine/pkg-plist
+12-13multimedia/kaffeine/Makefile
+11-0multimedia/kaffeine/files/patch-src_CMakeLists.txt
+1-8multimedia/kaffeine/pkg-descr
+3-3multimedia/kaffeine/distinfo
+48-705 files

LLVM/project 95f1eab — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV setcc-logic.ll jump-cond-merging-optsize.ll

by Pengcheng Wang via GitHub on ⎇
[RISCV] Add getJumpConditionMergingParams to support branch condition merging (#206897)

Override `getJumpConditionMergingParams` so that
`shouldKeepJumpConditionsTogether`
can decide whether to keep `br (and/or cond1, cond2)` merged into a
single
branch or split it into two branches, based on a configurable cost
threshold.

Previously RISC-V used the default cost `{-1, -1, -1}`, which always
split
the conditions. Now it returns a base cost calculated from
`MispredictPenalty`
(via scaling it down by an assumed misprediction rate 25%).

These values are controllable via
`riscv-br-merging-base-cost/-likely-bias/-unlikely-bias`.

This is another approach to #191158 when `TuneJumpIsExpensive` is not
set.
DeltaFile
+348-244llvm/test/CodeGen/RISCV/setcc-logic.ll
+68-0llvm/test/CodeGen/RISCV/jump-cond-merging-optsize.ll
+29-25llvm/test/CodeGen/RISCV/or-is-add.ll
+54-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+21-24llvm/test/CodeGen/RISCV/select-or.ll
+19-21llvm/test/CodeGen/RISCV/double-previous-failure.ll
+539-31413 files not shown
+595-36219 files

LLVM/project d62c903 — libcxx/test/benchmarks/containers string.bench.cpp

by Nikolas Klauser via GitHub on ⎇
[libc++] Refactor the string benchmarks (#185397)

Fixes #179696
DeltaFile
+462-580libcxx/test/benchmarks/containers/string.bench.cpp
+462-5801 files

LLVM/project d097c2b — llvm/lib/IR Verifier.cpp

by disservin via GitHub on ⎇
[IR][NFC] Add parentheses around logical AND (#208512)

Fixes a `-Wparentheses` warning about unclear priority of operators.
DeltaFile
+2-2llvm/lib/IR/Verifier.cpp
+2-21 files

LLVM/project b5e94d5 — flang/include/flang/Optimizer/Builder MIFCommon.h, flang/lib/Optimizer/Builder MIFCommon.cpp IntrinsicCall.cpp

by Jean-Didier PAILLEUX via GitHub on ⎇
[flang][MIF] Fix lowering sub argument in IMAGE_INDEX #208318 (#208544)

This PR fixes issue #208318, which did not correctly prepare the SUB
argument for IMAGE_INDEX in the correct type.
DeltaFile
+23-0flang/lib/Optimizer/Builder/MIFCommon.cpp
+3-3flang/lib/Optimizer/Builder/IntrinsicCall.cpp
+3-3flang/test/Lower/MIF/image_index.f90
+5-0flang/include/flang/Optimizer/Builder/MIFCommon.h
+3-0flang/lib/Optimizer/Dialect/MIF/MIFOps.cpp
+1-0flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
+38-66 files

LLVM/project c4ebc6b — llvm/test/CodeGen/AMDGPU llvm.amdgcn.intersect_ray.ll llvm.amdgcn.fma.legacy.ll

by Matt Arsenault on ⎇
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (19)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
+10-10llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.d16.dim.ll
+10-10llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
+9-9llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
+66-6693 files not shown
+451-45199 files

LLVM/project e8df44c — llvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.f32.fp8.err.ll llvm.amdgcn.cvt.fp8.ll

by Matt Arsenault on ⎇
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (18)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+24-24llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
+85-8594 files not shown
+409-409100 files

LLVM/project 4cd68b2 — llvm/test/CodeGen/AMDGPU lds-limit-diagnostics.ll isel-amdgpu-cs-chain-preserve-cc.ll

by Matt Arsenault on ⎇
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (17)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+16-16llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
+12-12llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
+9-9llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
+8-8llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
+7-7llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
+6-6llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
+58-5894 files not shown
+212-212100 files

LLVM/project 7666bc9 — llvm/test/CodeGen/AMDGPU integer-mad-patterns.ll idot4u.ll

by Matt Arsenault on ⎇
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (16)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+24-24llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+8-8llvm/test/CodeGen/AMDGPU/idot4u.ll
+8-8llvm/test/CodeGen/AMDGPU/idot4s.ll
+8-8llvm/test/CodeGen/AMDGPU/idot8s.ll
+6-6llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
+6-6llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+60-6094 files not shown
+261-261100 files

LLVM/project 9822c95 — llvm/test/CodeGen/AMDGPU hsa-metadata-queue-ptr-v5.ll global-saddr-load.ll

by Matt Arsenault on ⎇
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (15)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+9-9llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll
+8-8llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+7-7llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
+6-6llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll
+6-6llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll
+6-6llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
+42-4291 files not shown
+265-26597 files

LLVM/project 7e1975c — llvm/test/CodeGen/AMDGPU fptrunc.f16.ll gfx11-user-sgpr-init16-bug.ll

by Matt Arsenault on ⎇
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (14)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+16-16llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+14-14llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
+14-14llvm/test/CodeGen/AMDGPU/freeze.ll
+13-13llvm/test/CodeGen/AMDGPU/fptrunc.ll
+13-13llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+12-12llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+82-8292 files not shown
+476-47698 files

LLVM/project c3a2020 — llvm/test/CodeGen/AMDGPU fmax3-maximumnum.ll fmin3-minimumnum.ll

by Matt Arsenault on ⎇
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (13)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+18-18llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+18-18llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+16-16llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
+14-14llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
+12-12llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
+11-11llvm/test/CodeGen/AMDGPU/fmin3.ll
+89-8994 files not shown
+374-374100 files

FreeBSD/src f2f50c8 — usr.bin/sockstat main.c

by Michael Tuexen (tuexen) on ⎇
sockstat: fix SCTP support

Provide a name for SCTP sockets.

Fixes:          8b2b62b49d88 ("sockstat: consolidate unix(4) protocols in the array of protocols")
DeltaFile
+2-0usr.bin/sockstat/main.c
+2-01 files

LLVM/project b4698d8 — llvm/test/CodeGen/AMDGPU fcanonicalize.ll flat-scratch-reg.ll

by Matt Arsenault via GitHub on ⎇
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (12) (#208896)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+18-18llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+15-15llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
+14-14llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll
+14-14llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+12-12llvm/test/CodeGen/AMDGPU/fma.f16.ll
+10-10llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
+83-8394 files not shown
+371-371100 files

LLVM/project e3e1569 — llvm/test/CodeGen/AMDGPU elf-header-flags-mach.ll elf-header-osabi.ll

by Matt Arsenault via GitHub on ⎇
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (11) (#208895)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+79-79llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
+18-18llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
+14-14llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
+10-10llvm/test/CodeGen/AMDGPU/dpp_combine.ll
+10-10llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
+9-9llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
+140-14093 files not shown
+377-37799 files

NetBSD/pkgsrc 3QHhrxc — doc CHANGES-2026

by adam on ⎇
   Updated devel/py-hypothesis, math/py-astropy-iers-data
VersionDeltaFile
1.4417+3-1doc/CHANGES-2026
+3-11 files