LLVM/project baac39clibclc/opencl/lib/amdgcn SOURCES, libclc/opencl/lib/amdgcn/async wait_group_events.cl

libclc: Add amdgpu wait_group_events (#185177)
DeltaFile
+23-0libclc/opencl/lib/amdgcn/async/wait_group_events.cl
+1-0libclc/opencl/lib/amdgcn/SOURCES
+24-02 files

FreeBSD/ports 2c3403csysutils/fastfetch distinfo Makefile

sysutils/fastfetch: update to 2.60.0

Changelog:      https://github.com/fastfetch-cli/fastfetch/releases/tag/2.60.0
DeltaFile
+3-3sysutils/fastfetch/distinfo
+1-1sysutils/fastfetch/Makefile
+1-0sysutils/fastfetch/pkg-plist
+5-43 files

LLVM/project d7ff97dlibcxx/utils/ci/lnt run-benchmarks

[libc++] Support build failures when running LNT benchmarks (#185234)

It's rare but possible for the codebase not to build. When that happens,
we should carry on and still submit an empty LNT report for that order,
otherwise we'll get stuck thinking that order hasn't been benchmarked
yet.
DeltaFile
+3-2libcxx/utils/ci/lnt/run-benchmarks
+3-21 files

LLVM/project 01d3479clang/test/CIR/CodeGenOpenACC private-clause-pointer-array-recipes-CtorDtor.cpp combined-reduction-clause-default-ops.cpp, clang/test/CIR/IR cmp.cir

[CIR] Change CmpOp assembly format to use bare keyword style

Update the assembly format of cir.cmp from the parenthesized style
  cir.cmp(gt, %a, %b) : !s32i, !cir.bool
to the bare keyword style used by other CIR ops like cir.cast:
  cir.cmp gt %a, %b : !s32i

The result type (!cir.bool) is now automatically inferred as it is
always cir::BoolType.
DeltaFile
+64-64clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-CtorDtor.cpp
+60-60clang/test/CIR/IR/cmp.cir
+57-57clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
+57-57clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
+352-35282 files not shown
+1,321-1,29488 files

FreeBSD/src 2a4e311lib/libc/riscv/string Makefile.inc

libc/riscv64: temporarily disable strnlen() implementation until a fix is developed

strnlen() doesn't seem to cope well with a length argument such that
string pointer plus length overflows past the end of the address space.

Reviewed by:    fuz
MFC after:      1 week
PR:             293353, 293296
Differential Revision:  https://reviews.freebsd.org/D55714
DeltaFile
+0-1lib/libc/riscv/string/Makefile.inc
+0-11 files

LLVM/project efdf43bclang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Split CIR_UnaryOp into individual operations

Split the monolithic cir.unary operation (which dispatched on a
UnaryOpKind enum) into four separate operations: cir.inc, cir.dec,
cir.minus, and cir.not.

This follows the same pattern used when cir.binop was split into
individual binary operations (AddOp, SubOp, etc.).

Changes:
- Add CIR_UnaryOpInterface with getInput()/getResult() methods
- Add CIR_UnaryOp and CIR_UnaryOpWithOverflowFlag base classes
- Define IncOp, DecOp, MinusOp, NotOp with per-op folds
- Add Involution trait to NotOp for not(not(x)) -> x folding
- Replace createUnaryOp() with createInc/Dec/Minus/Not builders
- Split LLVM lowering into four separate patterns
- Split LoweringPrepare complex-type handling per unary op
- Update CIRCanonicalize and CIRSimplify for new op types
- Update all codegen files to use bool params instead of UnaryOpKind

    [6 lines not shown]
DeltaFile
+91-105clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+56-88clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+111-28clang/include/clang/CIR/Dialect/IR/CIROps.td
+62-62clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-CtorDtor.cpp
+41-41clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-NoOps.cpp
+36-36clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
+397-36076 files not shown
+1,390-1,36482 files

LLVM/project 516347alibc/src/__support/math ceill.h, libc/test/shared shared_math_test.cpp

link issue
DeltaFile
+2-13libc/src/__support/math/ceill.h
+3-5libc/test/shared/shared_math_test.cpp
+5-182 files

LLVM/project 7370190libclc/opencl/lib/amdgcn SOURCES, libclc/opencl/lib/amdgcn/printf __printf_alloc.cl

libclc: Add __printf_alloc implementation

AMDGPU OpenCL printf implementation emits a call to this helper
function.
DeltaFile
+36-0libclc/opencl/lib/amdgcn/printf/__printf_alloc.cl
+1-0libclc/opencl/lib/amdgcn/SOURCES
+37-02 files

OpenBSD/ports SIWN2hPlang/gcc/15 Makefile, lang/gcc/15/patches patch-libphobos_libdruntime_config_sparc64_switchcontext_S patch-libphobos_libdruntime_Makefile_in

   lang/gcc/15: add dlang support at aarch64, amd64 and sparc64

   OK: sthen@
VersionDeltaFile
1.1+178-0lang/gcc/15/patches/patch-libphobos_libdruntime_config_sparc64_switchcontext_S
1.2+118-1lang/gcc/15/patches/patch-libphobos_libdruntime_Makefile_in
1.2+54-1lang/gcc/15/patches/patch-libphobos_libdruntime_core_thread_fiber_package_d
1.2+48-2lang/gcc/15/patches/patch-libphobos_configure
1.21+15-14lang/gcc/15/Makefile
1.2+12-1lang/gcc/15/patches/patch-gcc_d_Make-lang_in
+425-193 files not shown
+455-219 files

OpenBSD/ports AAHizrPlang/gcc/11/patches patch-libphobos_libdruntime_config_sparc64_switchcontext_S patch-libphobos_libdruntime_Makefile_in

   lang/gcc/11: add dlang support at sparc64
VersionDeltaFile
1.1+178-0lang/gcc/11/patches/patch-libphobos_libdruntime_config_sparc64_switchcontext_S
1.3+109-1lang/gcc/11/patches/patch-libphobos_libdruntime_Makefile_in
1.3+55-2lang/gcc/11/patches/patch-libphobos_libdruntime_core_thread_fiber_d
1.3+48-2lang/gcc/11/patches/patch-libphobos_configure
1.3+43-6lang/gcc/11/patches/patch-gcc_d_d-lang_cc
1.2+15-17lang/gcc/11/patches/patch-libphobos_libdruntime_core_stdc_stdio_d
+448-282 files not shown
+456-358 files

LLVM/project 0482fe0llvm/test/CodeGen/WebAssembly ctselect-fallback-vector.ll ctselect-fallback-patterns.ll

[LLVM][WebAssembly] Regenerate ct.select test CHECK lines

Update CHECK lines to match the new constant-time AND/OR/XOR expansion
from the CT_SELECT legalization fix.
DeltaFile
+196-238llvm/test/CodeGen/WebAssembly/ctselect-fallback-vector.ll
+166-256llvm/test/CodeGen/WebAssembly/ctselect-fallback-patterns.ll
+129-201llvm/test/CodeGen/WebAssembly/ctselect-fallback.ll
+127-186llvm/test/CodeGen/WebAssembly/ctselect-fallback-edge-cases.ll
+10-16llvm/test/CodeGen/WebAssembly/ctselect-side-effects.ll
+628-8975 files

LLVM/project ef02361llvm/test/CodeGen/WebAssembly ctselect-fallback-vector.ll ctselect-fallback-patterns.ll

[ConstantTime][WebAssembly] Add comprehensive tests for ct.select
DeltaFile
+714-0llvm/test/CodeGen/WebAssembly/ctselect-fallback-vector.ll
+641-0llvm/test/CodeGen/WebAssembly/ctselect-fallback-patterns.ll
+552-0llvm/test/CodeGen/WebAssembly/ctselect-fallback.ll
+376-0llvm/test/CodeGen/WebAssembly/ctselect-fallback-edge-cases.ll
+226-0llvm/test/CodeGen/WebAssembly/ctselect-side-effects.ll
+2,509-05 files

LLVM/project f6436b3llvm/lib/Target/X86 X86InstrInfo.cpp X86ISelLowering.cpp, llvm/test/CodeGen/X86 ctselect-i386-fp.ll

[LLVM][X86] Add f80 support for ct.select

Add special handling for x86_fp80 types in CTSELECT lowering by splitting
them into three 32-bit chunks, performing constant-time selection on each
chunk, and reassembling the result. This fixes crashes when compiling
tests with f80 types.

Also updated ctselect.ll to match current generic fallback implementation.
DeltaFile
+463-452llvm/lib/Target/X86/X86InstrInfo.cpp
+126-146llvm/test/CodeGen/X86/ctselect-i386-fp.ll
+63-0llvm/lib/Target/X86/X86ISelLowering.cpp
+9-12llvm/lib/Target/X86/X86InstrInfo.h
+661-6104 files

LLVM/project 63418f3. nasty-fix-constant.patch, llvm/lib/Target/X86 X86ISelLowering.cpp X86InstrInfo.cpp

[LLVM][X86] Add native ct.select support for X86 and i386

Add native X86 implementation with CMOV instructions and comprehensive tests:
- X86 ISelLowering with CMOV for x86_64 and i386
- Fallback bitwise operations for i386 targets without CMOV
- Post-RA expansion for pseudo-instructions
- Comprehensive test coverage:
  - Edge cases (zero conditions, large integers)
  - i386-specific tests (FP, MMX, non-CMOV fallback)
  - Vector operations
  - Optimization patterns

The basic test demonstrating fallback is in the core infrastructure PR.
DeltaFile
+2,994-0nasty-fix-constant.patch
+639-1,228llvm/test/CodeGen/X86/ctselect.ll
+1,274-0llvm/test/CodeGen/X86/ctselect-vector.ll
+763-28llvm/lib/Target/X86/X86ISelLowering.cpp
+722-0llvm/test/CodeGen/X86/ctselect-i386-fp.ll
+604-5llvm/lib/Target/X86/X86InstrInfo.cpp
+6,996-1,26112 files not shown
+8,721-1,26618 files

LLVM/project c494d57llvm/lib/Target/ARM ARMISelLowering.cpp ARMBaseInstrInfo.cpp, llvm/test/CodeGen/ARM ctselect-vector.ll ctselect-half.ll

[LLVM][ARM] Add native ct.select support for ARM32 and Thumb

This patch implements architecture-specific lowering for ct.select on ARM
(both ARM32 and Thumb modes) using conditional move instructions and
bitwise operations for constant-time selection.

Implementation details:
- Uses pseudo-instructions that are expanded Post-RA to bitwise operations
- Post-RA expansion in ARMBaseInstrInfo for BUNDLE pseudo-instructions
- Handles scalar integer types, floating-point, and half-precision types
- Handles vector types with NEON when available
- Support for both ARM and Thumb instruction sets (Thumb1 and Thumb2)
- Special handling for Thumb1 which lacks conditional execution
- Comprehensive test coverage including half-precision and vectors

The implementation includes:
- ISelLowering: Custom lowering to CTSELECT pseudo-instructions
- ISelDAGToDAG: Selection of appropriate pseudo-instructions
- BaseInstrInfo: Post-RA expansion of BUNDLE to bitwise instruction sequences

    [3 lines not shown]
DeltaFile
+2,179-0llvm/test/CodeGen/ARM/ctselect-vector.ll
+975-0llvm/test/CodeGen/ARM/ctselect-half.ll
+530-66llvm/lib/Target/ARM/ARMISelLowering.cpp
+555-0llvm/test/CodeGen/ARM/ctselect.ll
+335-2llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+327-2llvm/lib/Target/ARM/ARMISelLowering.h
+4,901-704 files not shown
+5,185-21310 files

LLVM/project a5ce1aallvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 ctselect.ll

[LLVM][AArch64] Add native ct.select support for ARM64

This patch implements architecture-specific lowering for ct.select on AArch64
using CSEL (conditional select) instructions for constant-time selection.

Implementation details:
- Uses CSEL family of instructions for scalar integer types
- Uses FCSEL for floating-point types (F16, BF16, F32, F64)
- Post-RA MC lowering to convert pseudo-instructions to real CSEL/FCSEL
- Handles vector types appropriately
- Comprehensive test coverage for AArch64

The implementation includes:
- ISelLowering: Custom lowering to CTSELECT pseudo-instructions
- InstrInfo: Pseudo-instruction definitions and patterns
- MCInstLower: Post-RA lowering of pseudo-instructions to actual CSEL/FCSEL
- Proper handling of condition codes for constant-time guarantees
DeltaFile
+153-0llvm/test/CodeGen/AArch64/ctselect.ll
+56-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+40-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+35-4llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+18-0llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
+11-0llvm/lib/Target/AArch64/AArch64ISelLowering.h
+313-46 files

LLVM/project 89b18c0llvm/test/CodeGen/Mips ctselect-fallback-vector.ll ctselect-fallback-patterns.ll

[LLVM][MIPS] Add comprehensive tests for ct.select
DeltaFile
+830-0llvm/test/CodeGen/Mips/ctselect-fallback-vector.ll
+426-0llvm/test/CodeGen/Mips/ctselect-fallback-patterns.ll
+371-0llvm/test/CodeGen/Mips/ctselect-fallback.ll
+244-0llvm/test/CodeGen/Mips/ctselect-fallback-edge-cases.ll
+183-0llvm/test/CodeGen/Mips/ctselect-side-effects.ll
+2,054-05 files

LLVM/project 1a0a014clang/docs LanguageExtensions.rst, clang/include/clang/Basic Builtins.td

[ConstantTime][Clang] Add __builtin_ct_select for constant-time selection
DeltaFile
+683-0clang/test/Sema/builtin-ct-select.c
+373-0clang/test/Sema/builtin-ct-select-edge-cases.c
+64-0clang/lib/Sema/SemaChecking.cpp
+44-0clang/docs/LanguageExtensions.rst
+13-0clang/lib/CodeGen/CGBuiltin.cpp
+8-0clang/include/clang/Basic/Builtins.td
+1,185-06 files

LLVM/project 882c497llvm/test/CodeGen/RISCV ctselect-fallback-vector-rvv.ll ctselect-fallback-edge-cases.ll

[LLVM][RISCV] Regenerate ct.select test CHECK lines

Update CHECK lines to match the new constant-time AND/OR/XOR expansion
from the CT_SELECT legalization fix.
DeltaFile
+132-344llvm/test/CodeGen/RISCV/ctselect-fallback-vector-rvv.ll
+66-78llvm/test/CodeGen/RISCV/ctselect-fallback-edge-cases.ll
+62-77llvm/test/CodeGen/RISCV/ctselect-fallback-patterns.ll
+6-7llvm/test/CodeGen/RISCV/ctselect-side-effects.ll
+266-5064 files

LLVM/project a3c8bb2llvm/test/CodeGen/RISCV ctselect-fallback-vector-rvv.ll ctselect-fallback-patterns.ll

[ConstantTime][RISCV] Add comprehensive tests for ct.select

Add comprehensive test suite for RISC-V fallback implementation:
- Edge cases (zero conditions, large integers, sign extension)
- Pattern matching (nested selects, chains)
- Vector support with RVV extensions
- Side effects and memory operations

The basic fallback test is in the core infrastructure PR.
DeltaFile
+804-0llvm/test/CodeGen/RISCV/ctselect-fallback-vector-rvv.ll
+383-0llvm/test/CodeGen/RISCV/ctselect-fallback-patterns.ll
+214-0llvm/test/CodeGen/RISCV/ctselect-fallback-edge-cases.ll
+176-0llvm/test/CodeGen/RISCV/ctselect-side-effects.ll
+1,577-04 files

LLVM/project 9d45e79llvm/test/CodeGen/Mips ctselect-fallback-vector.ll ctselect-fallback-patterns.ll

[LLVM][MIPS] Regenerate ct.select test CHECK lines

Update CHECK lines to match the new constant-time AND/OR/XOR expansion
from the CT_SELECT legalization fix.
DeltaFile
+262-320llvm/test/CodeGen/Mips/ctselect-fallback-vector.ll
+133-164llvm/test/CodeGen/Mips/ctselect-fallback-patterns.ll
+117-141llvm/test/CodeGen/Mips/ctselect-fallback.ll
+100-123llvm/test/CodeGen/Mips/ctselect-fallback-edge-cases.ll
+11-13llvm/test/CodeGen/Mips/ctselect-side-effects.ll
+623-7615 files

LLVM/project 43fdb1fllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV clmul.ll

Merge remote-tracking branch 'origin/main' into users/wizardengineer/ct-select-core

# Conflicts:
#       llvm/lib/CodeGen/TargetLoweringBase.cpp
DeltaFile
+84,317-78,372llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+246,942-186,4239,853 files not shown
+982,681-491,0609,859 files

NetBSD/pkgsrc kxvuEhyprint/mupdf Makefile

   mupdf: needs bash to build now
VersionDeltaFile
1.140+2-2print/mupdf/Makefile
+2-21 files

ELF Tool Chain/elftoolchain 4360trunk/tests/tet/libelf/tset/abi abi.m4, trunk/tests/tet/libelf/tset/elf_cntl cntl.m4

libelf/test-suite: Convert tests to not use 'result' variables.
DeltaFile
+61-114trunk/tests/tet/libelf/tset/elf_update/update.m4
+12-24trunk/tests/tet/libelf/tset/gelf_getehdr/ehdr.m4
+9-17trunk/tests/tet/libelf/tset/elf_cntl/cntl.m4
+5-9trunk/tests/tet/libelf/tset/elf_getbase/getbase.m4
+3-8trunk/tests/tet/libelf/tset/abi/abi.m4
+2-4trunk/tests/tet/libelf/tset/elf_hash/hash.m4
+92-1763 files not shown
+96-1879 files

Linux/linux fb07430drivers/video/fbdev au1100fb.c

Merge tag 'fbdev-for-7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev

Pull fbdev fix from Helge Deller:
 "Silence build error in au1100fb driver found by kernel test robot"

* tag 'fbdev-for-7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev:
  fbdev: au1100fb: Fix build on MIPS64
DeltaFile
+6-2drivers/video/fbdev/au1100fb.c
+6-21 files

FreeBSD/ports a2a8965comms/meshcore-cli distinfo Makefile

comms/meshcore-cli: upgrade to 1.4.9
DeltaFile
+3-3comms/meshcore-cli/distinfo
+1-1comms/meshcore-cli/Makefile
+4-42 files

FreeBSD/ports 3d69cf4comms/py-meshcore distinfo Makefile

comms/py-meshcore: upgrade to 2.2.25
DeltaFile
+3-3comms/py-meshcore/distinfo
+1-1comms/py-meshcore/Makefile
+4-42 files

FreeBSD/ports e8f735bsysutils/whowatch Makefile pkg-descr, sysutils/whowatch/files patch-src_sysinfo__freebsd.c patch-whowatch.c

sysutils/whowatch: Update 1.4 => 1.8.6.2, take maintainership

Switch to upstream with FreeBSD support:
- https://github.com/Zedai00/whowatch/
- The new update wasn't working on FreeBSD due to Linuxisms and FreeBSD
  wrong API usages.
- Overhauled the codebase in a fork and updated it to work on both
  Linux and FreeBSD.
- Uses of sysctl, libprocstat, kvm etc to gather the system informations.

PR:             293113
MFH:            2026Q1
Co-authored-by: Vladimir Druzenko <vvd at FreeBSD.org>
(cherry picked from commit 55476368ccbc3863cec96779d914046a39ac5299)
DeltaFile
+121-0sysutils/whowatch/files/patch-src_sysinfo__freebsd.c
+0-105sysutils/whowatch/files/patch-whowatch.c
+0-31sysutils/whowatch/files/patch-procinfo.c
+0-27sysutils/whowatch/files/patch-whowatch.h
+10-13sysutils/whowatch/Makefile
+8-5sysutils/whowatch/pkg-descr
+139-1813 files not shown
+142-2079 files

FreeBSD/ports 5547636sysutils/whowatch Makefile pkg-descr, sysutils/whowatch/files patch-src_sysinfo__freebsd.c patch-whowatch.c

sysutils/whowatch: Update 1.4 => 1.8.6.2, take maintainership

Switch to upstream with FreeBSD support:
- The new update wasn't working on FreeBSD due to Linuxisms and FreeBSD
  wrong API usages.
- Overhauled the codebase in a fork and updated it to work on both
  Linux and FreeBSD.
- Uses of sysctl, libprocstat, kvm etc to gather the system informations.

PR:             293113
MFH:            2026Q1
Co-authored-by: Vladimir Druzenko <vvd at FreeBSD.org>
DeltaFile
+121-0sysutils/whowatch/files/patch-src_sysinfo__freebsd.c
+0-105sysutils/whowatch/files/patch-whowatch.c
+0-31sysutils/whowatch/files/patch-procinfo.c
+0-27sysutils/whowatch/files/patch-whowatch.h
+10-15sysutils/whowatch/Makefile
+8-5sysutils/whowatch/pkg-descr
+139-1833 files not shown
+142-2109 files

NetBSD/src Pb7w57qsys/arch/sparc64/sparc64 locore.s

   sun4v: hook up trap 0x30 (data_access_exception in the UA2005 spec) properly so the generic slowtrap/trap code path is not used, but the sun4v_datatrap code path is used instead
VersionDeltaFile
1.439+3-2sys/arch/sparc64/sparc64/locore.s
+3-21 files