LLVM/project 52e9e82llvm/lib/Target/AArch64 AArch64ConditionOptimizer.cpp

[NFC][AArch64] ConditionOptimizer: refine cmp/cond instruction update code (#186724)

Split modifyCmp() into updateCmpInstr() and updateCondInstr() to
separate the concerns of updating the compare and its controlling
conditional. Rename parseCond() to parseCondCode() and return the
CondCode directly rather than via an out-parameter.

Also add applyCmpAdjustment() to pair the two update calls at a higher
level of abstraction, reducing call site verbosity.
DeltaFile
+52-46llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+52-461 files

Dreckly/dreckly 98a4c8edevel/ldpc distinfo, devel/ldpc/patches patch-distrib.c patch-make-gen.c

ldpc: Fix implicit function decls
DeltaFile
+14-0devel/ldpc/patches/patch-distrib.c
+14-0devel/ldpc/patches/patch-make-gen.c
+2-0devel/ldpc/distinfo
+30-03 files

LLVM/project 3ae428flibcxx/include/__functional operations.h, libcxx/include/__type_traits make_transparent.h

[libc++][NFC] Rename the template parameter of __make_transparent (#186435)

Renaming from _Tp to _ArgumentType makes it clearer that we're passing
the argument type intended for the comparator, which allows checking
whether *that specific use* of the comparator would be transparent.

Fixes #186396
DeltaFile
+11-10libcxx/include/__type_traits/make_transparent.h
+4-4libcxx/include/__functional/operations.h
+15-142 files

OPNSense/core f8364f4src/opnsense/mvc/app/controllers/OPNsense/Kea/Api Dhcpv6Controller.php, src/opnsense/mvc/app/views/OPNsense/Kea dhcpv6.volt

Kea: DHCPv6: Forgot to add option tab and API endpoint for b67a8fd (#9987)

* Kea: DHCPv6: Forgot to add option tab for https://github.com/opnsense/core/commit/b67a8fdc931936f768b3d6a2eea1e179320f257a

* Kea: DHCPv6: Forgot to add option API endpoint for https://github.com/opnsense/core/commit/b67a8fdc931936f768b3d6a2eea1e179320f257a
DeltaFile
+25-0src/opnsense/mvc/app/controllers/OPNsense/Kea/Api/Dhcpv6Controller.php
+9-0src/opnsense/mvc/app/views/OPNsense/Kea/dhcpv6.volt
+34-02 files

Dreckly/dreckly a808c3cdevel/glade distinfo, devel/glade/patches patch-gladeui_glade-previewer-main.c

glade: Fix implicit decl of fileno(3).
DeltaFile
+14-0devel/glade/patches/patch-gladeui_glade-previewer-main.c
+1-0devel/glade/distinfo
+15-02 files

LLVM/project 43ec60ellvm/include/llvm/Support GenericDomTree.h, llvm/lib/Analysis ScalarEvolution.cpp

Reland "[DomTree] Assert non-null block for pre-dom tree" (#187005)

Reland #186790 with fix for SCEV. A loop can have more than one latch,
in which case getLoopLatch returns null.
DeltaFile
+58-0llvm/test/Analysis/ScalarEvolution/two-loop-latches.ll
+6-2llvm/include/llvm/Support/GenericDomTree.h
+4-2llvm/lib/Analysis/ScalarEvolution.cpp
+2-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1-1polly/lib/Analysis/ScopBuilder.cpp
+71-55 files

FreeNAS/freenas 668a8bdsrc/middlewared/middlewared/plugins/disk_ format.py, src/middlewared/middlewared/pytest/unit/plugins/disk test_format.py

Allow lower partition alignment if it is necessary to replace a disk in a pool created without partition margins
DeltaFile
+74-3src/middlewared/middlewared/plugins/disk_/format.py
+17-0src/middlewared/middlewared/pytest/unit/plugins/disk/test_format.py
+91-32 files

Dreckly/dreckly cb613f5comms/minimodem distinfo, comms/minimodem/patches patch-src_fsk.c

minimodem: Fix implicit decl of bzero(3).
DeltaFile
+14-0comms/minimodem/patches/patch-src_fsk.c
+1-0comms/minimodem/distinfo
+15-02 files

LLVM/project 0f1ec17llvm/test/CodeGen/AMDGPU fp-min-max-buffer-atomics.ll fp-min-max-buffer-ptr-atomics.ll, llvm/test/CodeGen/AMDGPU/GlobalISel atomicrmw-fmin-fmax.ll atomicrmw_fmax.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for atomic fmin/fmax (#182824)

Add register bank legalization rules for
G_ATOMICRMW_FMIN/G_ATOMICRMW_FMAX (flat, global, LDS) and
G_AMDGPU_BUFFER_ATOMIC_FMIN/G_AMDGPU_BUFFER_ATOMIC_FMAX (S32 and S64)
under -new-reg-bank-select. Update existing GlobalISel tests to use the
new pass and add a new MIR test for register bank assignment.
DeltaFile
+596-0llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
+98-48llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
+98-48llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
+6-6llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
+5-5llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
+4-4llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
+807-1112 files not shown
+814-1178 files

OPNSense/core a687a9fsrc/opnsense/mvc/app/views/OPNsense/Kea dhcpv6.volt

Kea: DHCPv6: Forgot to add option tab for https://github.com/opnsense/core/commit/b67a8fdc931936f768b3d6a2eea1e179320f257a
DeltaFile
+9-0src/opnsense/mvc/app/views/OPNsense/Kea/dhcpv6.volt
+9-01 files

Dreckly/dreckly 7f1a5d4devel/acunia-jam distinfo, devel/acunia-jam/patches patch-ac patch-jam.c

acunia-jam: Fix build with recent gcc
DeltaFile
+18-2devel/acunia-jam/patches/patch-ac
+14-0devel/acunia-jam/patches/patch-jam.c
+14-0devel/acunia-jam/patches/patch-mkjambase.c
+3-1devel/acunia-jam/distinfo
+49-34 files

LLVM/project 026747fllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'main' into users/stellaraccident/mlir_py_pass_assert_fix
DeltaFile
+230,295-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,097-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+92,827-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+41,419-41,418llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+36,428-36,427llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+538,415-120,19397,972 files not shown
+15,008,171-5,607,53297,978 files

FreeNAS/freenas 434ad8bsrc/middlewared/middlewared/etc_files systemd.py, src/middlewared/middlewared/plugins/device_ netlink_events.py

fix deadlock
DeltaFile
+720-0src/middlewared/middlewared/plugins/service_/services/dbus_router.py
+7-684src/middlewared/middlewared/plugins/service_/services/base.py
+4-7src/middlewared/middlewared/plugins/interface/dhcp.py
+4-3src/middlewared/middlewared/plugins/service_/services/pseudo/misc.py
+3-3src/middlewared/middlewared/etc_files/systemd.py
+2-2src/middlewared/middlewared/plugins/device_/netlink_events.py
+740-6996 files

LLVM/project 85fcc0dmlir/include/mlir/Dialect/LLVMIR LLVMIntrinsicOps.td, mlir/test/Target/LLVMIR llvmir-intrinsics.mlir

[mlir][LLVM] add llvm.fake.use to LLVM dialect
DeltaFile
+14-0mlir/test/Target/LLVMIR/Import/intrinsic.ll
+12-0mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+5-0mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
+31-03 files

FreeBSD/ports fd571ceaudio/exaile Makefile, audio/exaile/files patch-xl_player_gst_sink.py

audio/exaile: fix runtime with recent gstreamer update

Gstreamer 1.28 introduced breaking change to python API, so add a quick
fix obtained from here: https://github.com/exaile/exaile/issues/999

Reported by:    Keith <ukyo-nyan at theia.ocn.ne.jp> (private email)
DeltaFile
+16-0audio/exaile/files/patch-xl_player_gst_sink.py
+1-0audio/exaile/Makefile
+17-02 files

LLVM/project 6e17b2eclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-intrinsics.c

[CIR][AArch64] Upstream NEON shift left builtins (#186406)

This PR adds CIR generation for the following AArch64 NEON builtins:

__builtin_neon_vshld_n_s64 and __builtin_neon_vshld_n_u64 (constant
shifts)

extracted the constant value and use it directly for shift left

__builtin_neon_vshld_s64  and __builtin_neon_vshld_u64 (variable shifts)
there is an existing function to handles SISD (SIngle Instruction Single
Data), reusing this to create the right CIR instructions


__builtin_neon_vshld_s64 -- call i64 @llvm.aarch64.neon.sshl.i64(i64
[[A]], i64 [[B]])
__builtin_neon_vshld_u64 -- call i64 @llvm.aarch64.neon.ushl.i64(i64
[[A]], i64 [[B]])


    [18 lines not shown]
DeltaFile
+49-3clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-40clang/test/CodeGen/AArch64/neon-intrinsics.c
+13-1clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+62-443 files

NetBSD/pkgsrc-wip f7d5a8cpowerdns-recursor distinfo COMMIT_MSG, powerdns-recursor/files/smf manifest.xml pdns_recursor.sh

powerdns-recursor: remove, updated in pkgsrc
DeltaFile
+0-299powerdns-recursor/distinfo
+0-234powerdns-recursor/COMMIT_MSG
+0-100powerdns-recursor/cargo-depends.mk
+0-51powerdns-recursor/Makefile
+0-30powerdns-recursor/files/smf/manifest.xml
+0-24powerdns-recursor/files/smf/pdns_recursor.sh
+0-7384 files not shown
+1-77010 files

LLVM/project 240bc0allvm/lib/Target/AMDGPU R600TargetTransformInfo.h

[AMDGPU] Remove R600TargetTransformInfo dependency on AMDGPUTargetLowering. NFC. (#187014)
DeltaFile
+2-3llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
+2-31 files

FreeNAS/freenas b70f651src/middlewared/middlewared/plugins/service_/services dbus_router.py

address review
DeltaFile
+90-74src/middlewared/middlewared/plugins/service_/services/dbus_router.py
+90-741 files

OPNSense/core 8b1a583src/opnsense/mvc/app/models/OPNsense/Firewall Alias.php

Firewall: Aliases: Add target to getAliasSource() (#9985)
DeltaFile
+1-0src/opnsense/mvc/app/models/OPNsense/Firewall/Alias.php
+1-01 files

OPNSense/core 985ad25src/opnsense/mvc/app/library/OPNsense/Firewall DNatRule.php

Firewall: NAT: One-to-One NAT: add missing log statement
DeltaFile
+1-0src/opnsense/mvc/app/library/OPNsense/Firewall/DNatRule.php
+1-01 files

LLVM/project 05f2b89clang/include/clang/StaticAnalyzer/Core CheckerManager.h

[NFC][analyzer] Update some incorrect doc-comments (#186852)

These were incorrectly copy-pasted more than ten years ago.
DeltaFile
+6-3clang/include/clang/StaticAnalyzer/Core/CheckerManager.h
+6-31 files

LLVM/project a114bbellvm/lib/Support KnownFPClass.cpp, llvm/test/Transforms/Attributor nofpclass.ll

[ValueTracking] fadd never produces subnormal with no underflow (#186985)

In the cases where the fadd does not underflow, the result is both
non-zero and non-subnormal.

alive2 results for the added positive testcases:

testcase 1: https://alive2.llvm.org/ce/z/Mxjott

testcase 2: https://alive2.llvm.org/ce/z/Q-_A-v

testcase 3: https://alive2.llvm.org/ce/z/Y3XpSk

testcase 4: https://alive2.llvm.org/ce/z/34n8MZ

Fix #186975.
DeltaFile
+71-0llvm/test/Transforms/InstCombine/fadd.ll
+12-12llvm/test/Transforms/Attributor/nofpclass.ll
+2-2llvm/lib/Support/KnownFPClass.cpp
+85-143 files

LLVM/project 2859621utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[Bazel] Port 429e9717 (#187019)
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

FreeNAS/freenas 3caaeb7src/middlewared/middlewared/plugins/service_/services base.py

Fix deadlock in systemd plugin
DeltaFile
+71-5src/middlewared/middlewared/plugins/service_/services/base.py
+71-51 files

FreeNAS/freenas 293db19src/middlewared/middlewared/etc_files systemd.py, src/middlewared/middlewared/plugins/device_ netlink_events.py

refactor and pull dbus class into its own file
DeltaFile
+7-686src/middlewared/middlewared/plugins/service_/services/base.py
+649-4src/middlewared/middlewared/plugins/service_/services/dbus_router.py
+4-7src/middlewared/middlewared/plugins/interface/dhcp.py
+4-3src/middlewared/middlewared/plugins/service_/services/pseudo/misc.py
+3-3src/middlewared/middlewared/etc_files/systemd.py
+2-2src/middlewared/middlewared/plugins/device_/netlink_events.py
+669-7056 files

LLVM/project a1a714bmlir/include/mlir/Dialect/OpenACC OpenACCOps.td, mlir/include/mlir/Dialect/SCF/IR SCFOps.td

[MLIR][Interfaces] Make `getMutableSuccessorOperands` overridable on `ReturnLike` ops (#186832)

Move the `getMutableSuccessorOperands` implementation from `ReturnLike`
trait to the `RegionBranchTerminatorOpInterface` to allow overriding of
the implementation. This allows to have the trait on operations that are
not a return of all of their operands. This can be used, for example, to
implement custom `ReturnLike` terminator that consumes non-returned
operands in combination with `func.func`.

The `RegionBranchTerminatorOpInterface` now provides a default
implementation for the `getMutableSuccessorOperands` method that returns
all of the operands.
DeltaFile
+18-3mlir/test/lib/Dialect/Test/TestOps.td
+6-13mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+9-0mlir/test/lib/Dialect/Test/TestOpDefs.cpp
+3-2mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
+2-1mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
+38-195 files

LLVM/project 9f4fbe8lldb/include/lldb/ValueObject DILEval.h, lldb/source/ValueObject DILEval.cpp

[lldb] Add pointer arithmetics for addition and subtraction to DIL (#184652)
DeltaFile
+131-0lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/TestFrameVarDILExprPointerArithmetic.py
+115-7lldb/source/ValueObject/DILEval.cpp
+20-0lldb/test/API/commands/frame/var-dil/expr/PointerArithmetic/main.cpp
+0-12lldb/test/API/commands/frame/var-dil/expr/Arithmetic/TestFrameVarDILArithmetic.py
+7-0lldb/include/lldb/ValueObject/DILEval.h
+273-195 files

LLVM/project dc5c6d0clang/docs SanitizerCoverage.rst, clang/include/clang/Basic CodeGenOptions.def

[sancov] add -fsanitize-coverage=trace-pc-entry-exit (#185972)

Add a SanCov flag for calling dedicated hook functions on function entry
and exit. This flag can be used either in combination with
-fsanitize-coverage=trace-pc (in which case this patch changes which
hook is called for the entry BB, and generates an additional hook call
before return), or it can be used by itself (in which case only the
dedicated entry/exit callbacks are invoked).

This can be used to track the call stack throughout a sancov trace.

cc @vitalybuka @dvyukov
DeltaFile
+52-0llvm/test/Instrumentation/SanitizerCoverage/trace-pc-entry-exit.ll
+32-4llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
+11-7clang/lib/Driver/SanitizerArgs.cpp
+16-0clang/docs/SanitizerCoverage.rst
+6-1clang/include/clang/Options/Options.td
+2-0clang/include/clang/Basic/CodeGenOptions.def
+119-123 files not shown
+122-129 files

FreeNAS/freenas 8811733src/middlewared/middlewared/plugins/service_/services dbus_router.py base.py

cache global dbus router connection
DeltaFile
+56-0src/middlewared/middlewared/plugins/service_/services/dbus_router.py
+7-5src/middlewared/middlewared/plugins/service_/services/base.py
+63-52 files