LLVM/project 056e5a3llvm/test/CodeGen/AMDGPU fneg-combines.f16.ll bf16.ll

AMDGPU: Change ABI of 16-bit scalar values for gfx6/gfx7 (#175795)

Keep bf16/f16 values encoded as the low half of a 32-bit register,
instead of promoting to float. This avoids unwanted FP effects
from the fpext/fptrunc which should not be implied by just
passing an argument. This also fixes ABI divergence between
SelectionDAG and GlobalISel.

I've wanted to make this change for ages, and failed the last
few times. The main complication was the hack to return
shader integer types in SGPRs, which now needs to inspect
the underlying IR type.
DeltaFile
+372-419llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
+247-430llvm/test/CodeGen/AMDGPU/bf16.ll
+116-174llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+139-139llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
+112-153llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
+140-114llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+1,126-1,42981 files not shown
+3,579-4,36087 files

FreeBSD/ports 29bc7b2net/netatalk4 distinfo Makefile

net/netatalk4: Update to 4.4.1

See https://github.com/Netatalk/netatalk/releases/tag/netatalk-4-4-1 for
a list of changes in this release.
DeltaFile
+3-3net/netatalk4/distinfo
+1-1net/netatalk4/Makefile
+4-42 files

FreeNAS/freenas 4c988bdsrc/middlewared/middlewared/plugins cache.py, src/middlewared/middlewared/plugins/catalog features.py apps_details.py

Add persistent option to cache plugin

This commit adds ability to persistently set cache entries
(survives across middleware restarts / reboots, but not system
upgrades), and set clustered cache entries (ditto about
lifecycle).

In basic benchmarking there wasn't that much perf difference
between implementations and so this reduces overall complexity
DeltaFile
+206-34src/middlewared/middlewared/plugins/cache.py
+226-0tests/unit/test_cache.py
+13-2src/middlewared/middlewared/utils/tdb.py
+6-3src/middlewared/middlewared/plugins/catalog/features.py
+4-4src/middlewared/middlewared/plugins/catalog/apps_details.py
+2-2src/middlewared/middlewared/plugins/directoryservices_/connection.py
+457-456 files

LLVM/project 4b939beclang/test/CodeGenObjC arc-foreach.m arc-unsafeclaim.m, clang/test/CodeGenObjCXX auto-release-result-assert.mm

Reapply "[CGObjC] Allow clang.arc.attachedcall on -O0 (#164875)" (#177285)

This reverts commit 8eac375a4bff84f0a10a9c8ee23c4da409a805f9.

A unit test needed to be updated, that was all.

I do not have merge permissions.
DeltaFile
+232-1llvm/test/CodeGen/AArch64/call-rv-marker.ll
+89-89clang/test/CodeGenObjC/arc-foreach.m
+45-5clang/test/CodeGenObjC/arc-unsafeclaim.m
+16-16clang/test/CodeGenObjC/os_log.m
+22-1clang/test/CodeGenObjC/arc-arm.m
+12-6clang/test/CodeGenObjCXX/auto-release-result-assert.mm
+416-11810 files not shown
+464-15516 files

LLVM/project 41c1905llvm/test/CodeGen/X86 clmul-vector-256.ll clmul-vector-512.ll

[X86] Add 256-bit and 512-bit vector CLMUL test coverage (#176718)

DeltaFile
+2,278-0llvm/test/CodeGen/X86/clmul-vector-256.ll
+622-0llvm/test/CodeGen/X86/clmul-vector-512.ll
+2,900-02 files

LLVM/project 0e9ded5flang/lib/Semantics check-call.cpp, flang/test/Semantics cuf23.cuf

[flang][cuda] Allow device descriptor in show_descriptor (#177424)

Descriptor are always in managed memory so it is safe to call
show_descriptor for them.
DeltaFile
+6-0flang/test/Semantics/cuf23.cuf
+3-2flang/lib/Semantics/check-call.cpp
+9-22 files

LLVM/project 9fc5fd0llvm/docs ReleaseNotes.md, llvm/lib/Target/NVPTX NVPTXSubtarget.h

[NVPTX] Update the default SM to 7.5 (#176021)

Update NVPTX's default SM to sm_75. This matches the behavior of offline
compilation tools in the CUDA Toolkit (nvcc, ptxas, ...)
DeltaFile
+10-0llvm/test/CodeGen/NVPTX/default-sm.ll
+4-4llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
+7-0llvm/docs/ReleaseNotes.md
+2-2llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+2-2llvm/test/CodeGen/NVPTX/i128.ll
+2-2llvm/test/CodeGen/NVPTX/math-intrins.ll
+27-101 files not shown
+28-117 files

FreeBSD/ports 01c5d9fsysutils/logwatch Makefile distinfo, sysutils/logwatch/files patch-scripts_services_postfix pkg-message.in

sysutils/logwatch: Update 7.13 => 7.14

Commit log:
https://sourceforge.net/p/logwatch/git/ci/93cb38bb54f0ca12f4e792d9167993c9213e2c66/log/

- Remove no longer needed files/pkg-message.in and
  files/patch-scripts_services_postfix.
- Optimize post-install-DOCS-on.

PR:     292655
DeltaFile
+0-43sysutils/logwatch/files/patch-scripts_services_postfix
+0-24sysutils/logwatch/files/pkg-message.in
+2-6sysutils/logwatch/Makefile
+3-3sysutils/logwatch/distinfo
+4-0sysutils/logwatch/pkg-plist
+2-0sysutils/logwatch/files/Makefile
+11-766 files

LLVM/project aca0df9clang/lib/CIR/CodeGen CIRGenExprAggregate.cpp CIRGenExprScalar.cpp, clang/test/CIR/CodeGen builtin-bit-cast.cpp

[Clang][CIR] Implement CIRGen logic for __builtin_bit_cast (#176782)

NOTE: This PR upstreams code from
  * https://github.com/llvm/clangir.

This logic was originally implemented by Sirui Mu in
https://github.com/llvm/clangir/pull/762. Further
modification were made by other ClangIR contributors.

Co-authored-by: Sirui Mu <msrlancern at gmail.com>
DeltaFile
+139-0clang/test/CIR/CodeGen/builtin-bit-cast.cpp
+23-0clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
+11-0clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+173-03 files

LLVM/project ca9b84ellvm/include/llvm/CodeGen TargetLoweringObjectFileImpl.h

Clang-format llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
DeltaFile
+1-1llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
+1-11 files

LLVM/project 68c67dbclang/test/CodeGenHLSL/builtins radians-overloads.hlsl

[HLSL] Make radians overload tests stricter. NFC (#177252)

This patch is updating
`clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl` to use -O1
instead of -disable-llvm-passes, and updating the check to match the
change accordenlly.

This work is part of #138016.
DeltaFile
+82-62clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl
+82-621 files

LLVM/project 2e08bf7llvm/utils/TableGen/Common CodeGenRegisters.cpp

[TableGen] Prefer base class on tied RC sizes (#177257)

When searching for a matching subclass tablegen behavior is non
deterministic if we have several classes with the same size.
Break the tie by choosing a class with smaller BaseClassOrder.
DeltaFile
+7-2llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+7-21 files

LLVM/project c4afcfdllvm/include/llvm/CodeGen TargetLoweringObjectFileImpl.h

Apply change for ids check
DeltaFile
+7-6llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
+7-61 files

LLVM/project 1131523llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp

Fix clang-format.
DeltaFile
+2-2llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+2-2llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+4-42 files

LLVM/project 429ef43llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp

Assert that the ADA symbol should already be set
DeltaFile
+1-2llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+1-21 files

LLVM/project 5462f07llvm/include/llvm/CodeGen TargetLoweringObjectFileImpl.h, llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp

Remove separate ctor/dtor section functions and add getStaticXtorSection
DeltaFile
+4-5llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+1-6llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+2-4llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
+7-153 files

LLVM/project a23a16bllvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp

Address review comments regarding sections, unused parameter/unnecessary code changes.
DeltaFile
+4-10llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+2-5llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+6-152 files

LLVM/project e012864llvm/include/llvm/CodeGen TargetLoweringObjectFileImpl.h, llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp

Set ADA section correctly.
DeltaFile
+8-9llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+12-3llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+2-2llvm/test/CodeGen/SystemZ/zos_sinit.ll
+1-2llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
+23-164 files

LLVM/project 012217ellvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp SystemZAsmPrinter.h

Remove ADASym.
DeltaFile
+5-5llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+0-4llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+2-2llvm/test/CodeGen/SystemZ/zos_sinit.ll
+1-2llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
+8-134 files

LLVM/project 713f3ffllvm/include/llvm/MC MCSectionGOFF.h, llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp

Update test, movove ADA symbol, fix call to target independent emitXXStructorList
DeltaFile
+7-5llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+0-11llvm/include/llvm/MC/MCSectionGOFF.h
+0-2llvm/test/CodeGen/SystemZ/zos_sinit.ll
+7-183 files

LLVM/project 7f8d520llvm/include/llvm/CodeGen TargetLoweringObjectFileImpl.h, llvm/include/llvm/MC MCSectionGOFF.h

[SystemZ] Implement ctor/dtor emission via @@SQINIT and .xtor sections

This patch implements support for constructors/destructors by introducing the
@@SQINIT section and emitting .xtor.<priority> sections within the SystemZ
AsmPrinter and in the GOFF object lowering layer. Improvements to ADA descriptor
handling is also done within this change.
DeltaFile
+60-0llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+49-0llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+36-0llvm/test/CodeGen/SystemZ/zos_sinit.ll
+11-0llvm/include/llvm/MC/MCSectionGOFF.h
+4-1llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
+4-0llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
+164-11 files not shown
+165-17 files

LLVM/project 5d1b80allvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen TargetLoweringBase.cpp

DAG: Remove softPromoteHalfType

Remove the now unimplemented target hook and associated DAG machinery
for the old half legalization path.

Really fixes #97975
DeltaFile
+7-22llvm/include/llvm/CodeGen/TargetLowering.h
+0-20llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+0-11llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+2-7llvm/lib/CodeGen/TargetLoweringBase.cpp
+0-8llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+0-2llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+9-701 files not shown
+9-717 files

LLVM/project 0381093llvm/lib/Transforms/Instrumentation MemorySanitizer.cpp, llvm/test/Instrumentation/MemorySanitizer/AArch64 arm64-vshift.ll

[msan] Handle NEON vsli/vsri (vector shift left/right and insert) (#177283)

This does a shift and combine on the two vectors, hence we can precisely
propagate the shadow by applying the intrinsic to the input shadows.
DeltaFile
+28-88llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
+19-1llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+47-892 files

LLVM/project 73549e6clang/utils reduce-clang-crash.py

reduce-clang-crash.py: Use creduce if cvise is not found (#177413)

See discussion on #128592.
DeltaFile
+7-3clang/utils/reduce-clang-crash.py
+7-31 files

FreeBSD/src 4b96204sbin/mdmfs mdmfs.c

mdmfs: Fix soft updates logic

Now that newfs(8) has a command-line argument to disable soft updates,
use that instead of running tunefs(8) after the fact to turn them off.

MFC after:      1 week
Sponsored by:   Klara, Inc.
Sponsored by:   NetApp, Inc.
Reviewed by:    mckusick, imp
Differential Revision:  https://reviews.freebsd.org/D54783
DeltaFile
+2-10sbin/mdmfs/mdmfs.c
+2-101 files

LLVM/project 84db4dalibc/src/__support/wchar character_converter.h

[libc] Fix character converter in C++20 (#177421)

Internally character converter uses char8_t to represent a character.
Before C++20 we provide a typedef for it, but since C++20 it's a
keyword. The keyword version isn't listed in our is_integral, causing
countl to reject it as an invalid type. This patch just casts from
char8_t to int8_t to sidestep the issue, but in future we may want to
add char8_t, char16_t, and char32_t to our is_integral.
DeltaFile
+2-1libc/src/__support/wchar/character_converter.h
+2-11 files

LLVM/project a1062d9llvm/lib/Transforms/Utils ProfileVerify.cpp, llvm/test/Transforms/PGOProfile profcheck-select.ll prof-verify.ll

[profcheck] Print the function name in the error (#177264)

This is helpful for tests with a lot of test cases and grepping for
instructions with missing profile data isn't feasible because it doesn't
account for things like vectors which are exempt.

Tracking issue: #147390
DeltaFile
+10-6llvm/lib/Transforms/Utils/ProfileVerify.cpp
+2-2llvm/test/Transforms/PGOProfile/profcheck-select.ll
+2-1llvm/test/Transforms/PGOProfile/prof-verify.ll
+1-1llvm/test/Transforms/PGOProfile/profcheck-llvm.global_ctors.ll
+1-1llvm/test/Transforms/PGOProfile/prof-verify-no-entrycount.ll
+16-115 files

LLVM/project dc41bffllvm/lib/ProfileData MemProfSummary.cpp

undo whitespace changes
DeltaFile
+3-3llvm/lib/ProfileData/MemProfSummary.cpp
+3-31 files

LLVM/project 4c5ffe7lld/ELF Writer.cpp Driver.cpp, lld/ELF/Arch ARM.cpp

[lld][ELF/MachO] Use `.contains` rather than `.count` for set membership. NFC (#177404)

This matches the usage in the other linker backends.

See #176610, #177067
DeltaFile
+5-5lld/ELF/Writer.cpp
+4-4lld/ELF/Arch/ARM.cpp
+4-4lld/ELF/Driver.cpp
+4-4lld/ELF/ScriptParser.cpp
+3-2lld/ELF/LinkerScript.cpp
+2-2lld/ELF/SyntheticSections.cpp
+22-216 files not shown
+29-2812 files

LLVM/project 6025178llvm/lib/Target/AMDGPU R600ISelLowering.cpp R600ISelLowering.h, llvm/test/CodeGen/AMDGPU kernel-args.ll

R600: Remove softPromoteHalfType

Also includes a kind of hacky, minimal change to avoid assertions
when softPromoteHalfType is removed to fix kernel arguments
lowered as f16. Half support was never really implemented
for r600, and there just happened to be a few incidental tests
which included a half argument (which were also not even meaningful,
since the function body just folded to nothing due to no callable
function support).
DeltaFile
+164-0llvm/test/CodeGen/AMDGPU/kernel-args.ll
+3-0llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+0-2llvm/lib/Target/AMDGPU/R600ISelLowering.h
+167-23 files