LLVM/project cb15e67llvm/docs LoopFusion.rst Passes.rst

[LoopFusion] Document LoopFusion Pass (#192926)

The LoopFusion pass, currently disabled by default, lacks documentation. This patch is the first attempt to document the flow and current limitations.

Assisted by : Claude Opus 4.6
DeltaFile
+442-0llvm/docs/LoopFusion.rst
+7-0llvm/docs/Passes.rst
+449-02 files

LLVM/project 9b0d277llvm/lib/CodeGen/LiveDebugValues VarLocBasedImpl.cpp

[LiveDebugValues] Avoid SmallSet for dead registers (#195841)

transferRegisterDef builds a list of dead registers and removes open ranges for
debug locations that use those registers. This list used a SmallSet, so each
insert also does uniquing in the hot per-instruction path. This showed up under
SmallSet<Register, 32>::insertImpl on profiles of sqlite on aarch64-O0-g.

Using a SmallVector instead and uniquing in collectIDsForRegs improves
compile-time.

CTMark geomean:
- stage1-O0-g: -0.35%
- stage1-aarch64-O0-g: -0.72%
- stage2-O0-g: -0.27%

https://llvm-compile-time-tracker.com/compare.php?from=c9d713aa48a714d20b8502d06b9feb24829e6f22&to=6c0d4aafb9e325259c88577d148ac13c643ea993&stat=instructions%3Au

Assisted-by: codex
DeltaFile
+8-9llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
+8-91 files

LLVM/project d97c568clang/test/Analysis/Scalable/ssaf-analyzer analyzer.test, clang/test/Analysis/Scalable/ssaf-analyzer/Inputs lu.json

Revert "[clang][ssaf] Add `clang-ssaf-analyzer` (#188881)" (#195993)

This reverts commit 51d2a66d52a95beeb31de81dd819c603062a5770 introduced by PR https://github.com/llvm/llvm-project/pull/188881 because of an HWSan failure.
DeltaFile
+0-141clang/test/Analysis/Scalable/ssaf-analyzer/analyzer.test
+0-134clang/tools/clang-ssaf-analyzer/SSAFAnalyzer.cpp
+0-126clang/test/Analysis/Scalable/ssaf-analyzer/Inputs/lu.json
+0-90clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/all.json
+0-81clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/both.json
+0-70clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/pairs.json
+0-64215 files not shown
+0-93121 files

LLVM/project dfb8d68llvm/include/llvm/CodeGen RegAllocEvictionAdvisor.h, llvm/lib/CodeGen RegAllocEvictionAdvisor.cpp RegAllocGreedy.cpp

[RegAlloc] consider urgent evict in evictInterference (#192631)

This assertion causes a crash in programs with high register pressure
when inline assembly is used.

```
    assert((ExtraInfo->getCascade(Intf->reg()) < Cascade ||
            VirtReg.isSpillable() < Intf->isSpillable()) &&
           "Cannot decrease cascade number, illegal eviction");
```

It should account for the case where an urgent eviction may result in
cascade being less than `ExtraInfo->getCascade(Intf->reg())`

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
DeltaFile
+17-12llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
+17-0llvm/test/CodeGen/RISCV/regalloc-greedy-urgent-evict.ll
+4-0llvm/include/llvm/CodeGen/RegAllocEvictionAdvisor.h
+2-0llvm/lib/CodeGen/RegAllocGreedy.cpp
+40-124 files

LLVM/project d6a1064clang/test/CIR/Transforms mem2reg.cir

[CIR][NFC] Upstream mem2reg.cir from incubator (#194517)

Upstream `mem2reg.cir` from incubator.

Check that stack slots are promoted away after CFG flattening.

Partially addresses #156747.
DeltaFile
+23-0clang/test/CIR/Transforms/mem2reg.cir
+23-01 files

NetBSD/src jquD50eusr.sbin/makefs makefs.8 TODO

   makefs(8): improve fs-options documentation

   Ensure all fs-options are documented, in alphabetical order.
   Describe whether the option has a value (e.g., foo=str or foo=num),
   and for numeric values describe the supported range.
   Some markup consistency.
   Remove my email from the man page.
VersionDeltaFile
1.76+202-142usr.sbin/makefs/makefs.8
1.8+1-5usr.sbin/makefs/TODO
+203-1472 files

FreeBSD/ports 2fbfcd1databases/ladybug distinfo Makefile

databases/ladybug: Update 0.16.0 => 0.16.1

Changelog:
https://github.com/LadybugDB/ladybug/releases/tag/v0.16.1

PR:             295039
Sponsored by:   UNIS Labs
DeltaFile
+3-3databases/ladybug/distinfo
+1-1databases/ladybug/Makefile
+4-42 files

LLVM/project 5f72b7cllvm/docs AMDGPUUsage.rst, llvm/docs/AMDGPU DeveloperGuideline.rst

[NFC][AMDGPU][Doc] Add developer guideline

This guideline covers topics on top of existing LLVM guideline.
DeltaFile
+442-0llvm/docs/AMDGPU/DeveloperGuideline.rst
+1-0llvm/docs/AMDGPUUsage.rst
+443-02 files

FreeBSD/ports d71af7amisc/crush distinfo Makefile

misc/crush: Update to 0.65.3

Changelog:
- https://github.com/charmbracelet/crush/releases/tag/v0.65.2
- https://github.com/charmbracelet/crush/releases/tag/v0.65.3

Reported by:    GitHub (watch releases)
DeltaFile
+5-5misc/crush/distinfo
+1-1misc/crush/Makefile
+6-62 files

NetBSD/pkgsrc-wip 2100b0dcloudflare-speed-cli distinfo Makefile

cloudflare-speed-cli: update to 0.6.7
DeltaFile
+3-3cloudflare-speed-cli/distinfo
+1-1cloudflare-speed-cli/Makefile
+4-42 files

FreeBSD/ports 2c33242lang/hs-futhark distinfo Makefile

lang/hs-futhark: update 0.25.36 → 0.26.1
DeltaFile
+79-71lang/hs-futhark/distinfo
+36-27lang/hs-futhark/Makefile
+115-982 files

FreeBSD/ports f213cdclang/hs-koka distinfo Makefile

lang/hs-koka: update 3.2.2 → 3.2.3
DeltaFile
+141-159lang/hs-koka/distinfo
+65-62lang/hs-koka/Makefile
+206-2212 files

FreeBSD/ports 3a2108cdevel/py-uv-build distinfo Makefile

devel/py-uv-build: update 0.11.8 → 0.11.10
DeltaFile
+3-3devel/py-uv-build/distinfo
+1-1devel/py-uv-build/Makefile
+4-42 files

FreeBSD/ports 85d35c3net/wstunnel distinfo Makefile

net/wstunnel: update 10.5.4 → 10.5.5
DeltaFile
+3-3net/wstunnel/distinfo
+1-1net/wstunnel/Makefile
+4-42 files

FreeBSD/ports 75019f9www/cpp-httplib distinfo Makefile

www/cpp-httplib: update 0.43.2 → 0.43.3
DeltaFile
+3-3www/cpp-httplib/distinfo
+1-1www/cpp-httplib/Makefile
+4-42 files

FreeBSD/ports b337122editors/cpeditor distinfo Makefile

editors/cpeditor: update 7.0.1 → 7.1.1
DeltaFile
+9-7editors/cpeditor/distinfo
+6-4editors/cpeditor/Makefile
+15-112 files

FreeBSD/ports 07e9d69devel/py-uv distinfo Makefile, devel/uv distinfo Makefile.crates

devel/{,py-}uv: update 0.11.8 → 0.11.10
DeltaFile
+55-57devel/uv/distinfo
+26-27devel/uv/Makefile.crates
+3-3devel/py-uv/distinfo
+1-1devel/uv/Makefile
+1-1devel/py-uv/Makefile
+86-895 files

FreeBSD/ports d43f5c2sysutils/mise distinfo Makefile

sysutils/mise: update 2026.5.0 → 2026.5.1
DeltaFile
+209-215sysutils/mise/distinfo
+104-107sysutils/mise/Makefile
+313-3222 files

Illumos/gate 73eca58usr/src/cmd/nvmeadm nvmeadm.c nvmeadm_ofmt.c, usr/src/man/man8 nvmeadm.8

18045 nvmeadm could list physical locations
Reviewed by: Andy Fiddaman <illumos at fiddaman.net>
Reviewed by: Dan Cross <cross at oxidecomputer.com>
Approved by: Gordon Ross <gordon.w.ross at gmail.com>
DeltaFile
+191-13usr/src/cmd/nvmeadm/nvmeadm.c
+23-12usr/src/man/man8/nvmeadm.8
+31-1usr/src/cmd/nvmeadm/nvmeadm_ofmt.c
+15-0usr/src/cmd/nvmeadm/nvmeadm.h
+1-0usr/src/cmd/nvmeadm/Makefile
+261-265 files

LLVM/project 7df4736clang/lib/CIR/CodeGen CIRGenBuiltinRISCV.cpp, clang/test/CIR/CodeGenBuiltins/RISCV riscv-zbkb.c

[CIR][RISCV] Support zbkb builtin codegen (#195401)

Include 4 builtins: __builtin_riscv_brev8_32, __builtin_riscv_brev8_64,
__builtin_riscv_zip_32, __builtin_riscv_unzip_32.
DeltaFile
+50-0clang/test/CIR/CodeGenBuiltins/RISCV/riscv-zbkb.c
+12-3clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+62-32 files

LLVM/project 36122ebllvm/lib/Target/RISCV RISCVCallingConv.cpp

[RISCV] Rename and invert UseGPRForF16_F32/UseGPRForF16_F32. (#195971)

Rename to AllowFPR. We used to set these flags when we ran out of FPRs,
but we haven't for a while. I think rephrasing as allow FPR is a bit
clearer.
DeltaFile
+13-15llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+13-151 files

LLVM/project 9dd7c73llvm/lib/Target/RISCV RISCVInstrInfoP.td

[RISCV][P-ext] Remove VXSAT from SHL/SHLR/SHA/SHAR. Add to PSAS and PSSA. (#195488)
DeltaFile
+10-8llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+10-81 files

LLVM/project 6201b4ebolt/include/bolt/Profile DataAggregator.h DataReader.h, bolt/lib/Profile DataAggregator.cpp DataReader.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.4
DeltaFile
+18-55bolt/lib/Profile/DataAggregator.cpp
+1-13bolt/include/bolt/Profile/DataAggregator.h
+9-0bolt/include/bolt/Profile/DataReader.h
+4-0bolt/lib/Profile/DataReader.cpp
+32-684 files

OpenBSD/src oCvmj7blib/libc/stdio open_wmemstream.c

   Size is the number of wide characters, not the number of bytes.
   The correct amount of memory was allocated but the stored size did
   not match the allocation due to being multiplied by sizeof(wchar_t).

   Spotted by Frank Denis using the Swival Security Scanner
   OK deraadt@
VersionDeltaFile
1.11+3-3lib/libc/stdio/open_wmemstream.c
+3-31 files

NetBSD/pkgsrc-wip 7bc0729py-ksef2 PLIST distinfo

py-ksef2: update to 0.13.1
DeltaFile
+339-3py-ksef2/PLIST
+3-3py-ksef2/distinfo
+2-1py-ksef2/Makefile
+344-73 files

LLVM/project 2e4c72ellvm/docs CodingStandards.rst

[RFC][Docs] Clarify brace omission for single-line bodies

Update the Coding Standards brace guidance to emphasize that braces should be
omitted only for simple bodies that do not wrap across multiple physical lines.
DeltaFile
+22-9llvm/docs/CodingStandards.rst
+22-91 files

LLVM/project d4c0c7bllvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV returnaddress.ll

[SPIRV] Dummy implementation of the `returnaddress` and `frameaddress` intrinsics (#195976)

The SPIR-V specification doesn't define any operations for the
return and frame address. The valid implementation in this case is to
produce a null pointer.

Assisted-by: Claude Opus 4.6 <noreply at anthropic.com>
DeltaFile
+26-0llvm/test/CodeGen/SPIRV/returnaddress.ll
+9-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+35-02 files

LLVM/project 75428e9llvm/lib/Target/SPIRV SPIRVPrepareFunctions.cpp SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort abort-opencl-source.ll abort-post-terminator-suppression.ll

[SPIRV] Add support for SPV_KHR_abort extension (#193037)

This commit adds support for the SPV_KHR_abort extension in the SPIRV
backend. The extension allows shaders to abort execution with a custom
message.

Assisted-by: Claude Opus 4.7 <noreply at anthropic.com>

---------

Co-authored-by: Marcos Maronas <mmaronas at amd.com>
DeltaFile
+113-2llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+91-5llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+81-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/abort-opencl-source.ll
+68-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/abort-post-terminator-suppression.ll
+62-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/abort-opencl.ll
+59-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/no-abort-unaffected.ll
+474-724 files not shown
+1,178-1130 files

LLVM/project a8b0124llvm/include/llvm/TargetParser RISCVTargetParser.h, llvm/lib/Target/RISCV RISCVInstrInfoZvvmm.td

[RISCV][MC] Add experimental `Zvvmm` MC support (#193956)

Add initial MC-layer support for `Zvvmm` from the experimental [RISC-V
Integrated Matrix
Extension](https://github.com/riscv/integrated-matrix-extension/blob/d2e64b4922f5c2c416761f3c7c997d4f0cf814d9/src/integrated-matrix.adoc)
(version
[2026-04-23](https://github.com/riscv/integrated-matrix-extension/releases/tag/riscv-isa-release-d2e64b4-2026-04-23))

This patch:
- Adds the experimental `zvvmm` 0.1 extension feature, depending on
`zve32x`.
- Adds assembler/disassembler definitions for the integer matrix
multiply-accumulate instructions:
  - `vmmacc.vv`
  - `vwmmacc.vv`
  - `vqmmacc.vv`
  - `v8wmmacc.vv`
- Adds IME vtype helper modeling in `RISCVVType`, covering lambda
encoding/decoding, IME vtype field masks,

    [3 lines not shown]
DeltaFile
+89-0llvm/lib/TargetParser/RISCVTargetParser.cpp
+49-0llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
+37-0llvm/lib/Target/RISCV/RISCVInstrInfoZvvmm.td
+29-0llvm/include/llvm/TargetParser/RISCVTargetParser.h
+27-0llvm/test/MC/RISCV/rvv/zvvmm.s
+18-0llvm/test/MC/RISCV/rvv/zvvmm-invalid.s
+249-07 files not shown
+266-113 files

FreeBSD/ports 3d367b0devel/py-pytz distinfo Makefile

devel/py-pytz: Update to 2026.2
DeltaFile
+3-3devel/py-pytz/distinfo
+1-2devel/py-pytz/Makefile
+4-52 files