LLVM/project ac8361dllvm/lib/Target/X86 X86InstrCompiler.td, llvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Remove extra MOV after widening atomic store

This change adds patterns to optimize out an extra MOV present after
widening the atomic store. Covers <2 x i8> (SSE4.1+), <2 x i16>,
<4 x i8>, <2 x i32>, <2 x float>, <4 x i16>, <2 x ptr addrspace(270)>.
DeltaFile
+47-64llvm/test/CodeGen/X86/atomic-load-store.ll
+99-0llvm/lib/Target/X86/X86InstrCompiler.td
+146-642 files

LLVM/project 6cdd328llvm/lib/AsmParser LLParser.cpp, llvm/test/Assembler thinlto-vtable-skip.ll thinlto-bad-summary1.ll

Handle typeidCompatibleVTable in skipModuleSummaryEntry (#196849)

This method needs to match the set of cases handled in parseSummaryEntry.
DeltaFile
+11-0llvm/test/Assembler/thinlto-vtable-skip.ll
+6-5llvm/lib/AsmParser/LLParser.cpp
+1-1llvm/test/Assembler/thinlto-bad-summary1.ll
+18-63 files

LLVM/project 12e06d7mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

Remove unrelated empty line
DeltaFile
+0-1mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+0-11 files

LLVM/project 83ae5ccflang/include/flang/Semantics semantics.h, flang/lib/Semantics resolve-directives.cpp rewrite-parse-tree.cpp

[flang][openacc] allow duplicate data sharing clauses (#197019)

This PR allows duplicate OpenACC `private` and `firstprivate` clauses.
While maintaining the restriction on `reduction` clauses.
DeltaFile
+122-0flang/test/Semantics/OpenACC/acc-dataclause-dedup.f90
+63-0flang/test/Lower/OpenACC/acc-dedup-private.f90
+27-16flang/lib/Semantics/resolve-directives.cpp
+28-0flang/test/Parser/acc-dedup-unparse.f90
+11-0flang/include/flang/Semantics/semantics.h
+10-0flang/lib/Semantics/rewrite-parse-tree.cpp
+261-161 files not shown
+262-177 files

LLVM/project 4f60fb9flang/docs Directives.md, flang/lib/Semantics expression.cpp

[flang][cuda] Honor !dir$ ignore_tkr(m) under -gpu=mem:{unified,managed} (#197518)

A device-typed dummy with `!dir$ ignore_tkr(m)` is meant to be an
overload discriminator (only selected for actuals with an explicit
`device/managed/unified` attribute). Skip the host->device relaxation in
AreCompatibleCUDADataAttrs when `IgnoreTKR::Managed` is set so
unattributed host actuals no longer bind to such a dummy.

Also document the §3.2.3 matching distance table next to
GetMatchingDistance and add LIT tests for the full Table 2 grid
and the ignore_tkr(m) carve-out.
DeltaFile
+90-0flang/test/Semantics/cuf-matching-distance.cuf
+56-0flang/test/Semantics/cuf-ignore-tkr-m-generic.cuf
+36-0flang/docs/Directives.md
+32-0flang/test/Semantics/cuf-ignore-tkr-m-error.cuf
+23-2flang/lib/Semantics/expression.cpp
+13-5flang/lib/Support/Fortran.cpp
+250-76 files

FreeBSD/ports c5c88acwww/deno/files patch-cargo-crates_cranelift-codegen-0.116.1_build.rs patch-build_config_compiler_BUILD.gn

www/deno: add powerpc64le support

1. Merge upstream cranelift-codegen patch for unsupported architectures.
2. Modify BUILD.gn to add freebsd/powerpc64le support.
DeltaFile
+16-0www/deno/files/patch-cargo-crates_cranelift-codegen-0.116.1_build.rs
+9-0www/deno/files/patch-build_config_compiler_BUILD.gn
+8-1www/deno/files/patch-build_toolchain_freebsd_BUILD.gn
+33-13 files

FreeBSD/ports 570eefbsecurity/nss Makefile, security/nss/files patch-lib_freebl_ppc-gcm.s patch-lib-freebl-Makefile

security/nss: drop binutils on powerpc64le

LLVM's integrated assembler rejects .set-aliased symbols inside memory
operand parentheses, e.g. `std 31,-8(SP)` with `.set SP, 1`.  Replace
the SP alias with its numeric value (r1) in the memory operands so the
IAS accepts them.  Other uses of SP outside parentheses are fine.
DeltaFile
+44-0security/nss/files/patch-lib_freebl_ppc-gcm.s
+1-2security/nss/files/patch-lib-freebl-Makefile
+0-2security/nss/Makefile
+45-43 files

LLVM/project e2b5048llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/test/MC/AMDGPU literals.s

[AMDGPU] Validate forced lit() immediate (#196623)

Right now it takes validation path of an inline constant if fits
even though it is forced to literal encoding.
DeltaFile
+7-8llvm/test/MC/AMDGPU/literals.s
+7-1llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+14-92 files

NetBSD/pkgsrc psaASCNdevel/qt6-qtwayland distinfo

   qt6-qtwayland: do the update
VersionDeltaFile
1.22+4-4devel/qt6-qtwayland/distinfo
+4-41 files

FreeBSD/ports bf62fa6lang/rubygem-rb_sys distinfo Makefile

lang/rubygem-rb_sys: update to 0.9.128

Changes:        https://github.com/oxidize-rb/rb-sys/releases
DeltaFile
+3-3lang/rubygem-rb_sys/distinfo
+2-3lang/rubygem-rb_sys/Makefile
+5-62 files

LLVM/project 1ee6e9cllvm/lib/ProfileData InstrProf.cpp, llvm/lib/Transforms/Instrumentation PGOMemOPSizeOpt.cpp

fix

Created using spr 1.3.7
DeltaFile
+0-58llvm/test/Transforms/PGOProfile/consecutive-zeros.ll
+33-16llvm/lib/ProfileData/InstrProf.cpp
+0-47llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
+4-38llvm/test/Transforms/JumpTableToSwitch/profile-no-guid-metadata.ll
+0-7llvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp
+37-1665 files

LLVM/project e780eb0llvm/lib/ProfileData InstrProf.cpp, llvm/lib/Transforms/Instrumentation PGOMemOPSizeOpt.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-58llvm/test/Transforms/PGOProfile/consecutive-zeros.ll
+33-16llvm/lib/ProfileData/InstrProf.cpp
+0-47llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
+4-38llvm/test/Transforms/JumpTableToSwitch/profile-no-guid-metadata.ll
+0-7llvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp
+37-1665 files

LLVM/project 5ad848ellvm/lib/ProfileData InstrProf.cpp, llvm/test/Transforms/JumpTableToSwitch profile-no-guid-metadata.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+0-58llvm/test/Transforms/PGOProfile/consecutive-zeros.ll
+0-47llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
+4-38llvm/test/Transforms/JumpTableToSwitch/profile-no-guid-metadata.ll
+33-4llvm/lib/ProfileData/InstrProf.cpp
+25-0llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros-metadata.proftext
+21-0llvm/test/Transforms/PGOProfile/consecutive-zeros-metadata.ll
+83-1472 files not shown
+86-1558 files

LLVM/project 0f43f70llvm/lib/ProfileData InstrProf.cpp, llvm/lib/Transforms/Instrumentation PGOMemOPSizeOpt.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-58llvm/test/Transforms/PGOProfile/consecutive-zeros.ll
+0-47llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
+33-4llvm/lib/ProfileData/InstrProf.cpp
+25-0llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros-metadata.proftext
+21-0llvm/test/Transforms/PGOProfile/consecutive-zeros-metadata.ll
+0-7llvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp
+79-1161 files not shown
+82-1177 files

LLVM/project d1eeb00llvm/lib/ProfileData InstrProf.cpp, llvm/lib/Transforms/Instrumentation PGOMemOPSizeOpt.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+0-58llvm/test/Transforms/PGOProfile/consecutive-zeros.ll
+0-47llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
+33-4llvm/lib/ProfileData/InstrProf.cpp
+25-0llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros-metadata.proftext
+21-0llvm/test/Transforms/PGOProfile/consecutive-zeros-metadata.ll
+0-7llvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp
+79-1161 files not shown
+82-1177 files

LLVM/project 3f6536ellvm/docs LangRef.rst, llvm/lib/ProfileData InstrProf.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-58llvm/test/Transforms/PGOProfile/consecutive-zeros.ll
+0-47llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
+33-4llvm/lib/ProfileData/InstrProf.cpp
+25-0llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros-metadata.proftext
+21-0llvm/test/Transforms/PGOProfile/consecutive-zeros-metadata.ll
+3-1llvm/docs/LangRef.rst
+82-1106 files

LLVM/project 44c2207llvm/lib/ProfileData InstrProf.cpp, llvm/test/Transforms/PGOProfile consecutive-zeros.ll

fix

Created using spr 1.3.7
DeltaFile
+0-58llvm/test/Transforms/PGOProfile/consecutive-zeros.ll
+33-16llvm/lib/ProfileData/InstrProf.cpp
+0-47llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
+33-1213 files

LLVM/project a2214e3llvm/test/Transforms/PGOProfile consecutive-zeros.ll, llvm/test/Transforms/PGOProfile/Inputs consecutive-zeros.proftext

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-58llvm/test/Transforms/PGOProfile/consecutive-zeros.ll
+0-47llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
+0-1052 files

LLVM/project e7852b5llvm/docs LangRef.rst, llvm/test/Transforms/PGOProfile consecutive-zeros.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+0-58llvm/test/Transforms/PGOProfile/consecutive-zeros.ll
+0-47llvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
+3-1llvm/docs/LangRef.rst
+3-1063 files

LLVM/project 70ac2f7llvm/docs LangRef.rst

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+3-1llvm/docs/LangRef.rst
+3-11 files

LLVM/project 409d4a6llvm/test/CodeGen/AMDGPU splitkit-copy-live-lanes.mir ra-inserted-scalar-instructions.mir, llvm/test/CodeGen/X86 statepoint-invoke-ra-inline-spiller.mir

[MIR] Serialize/Deserialize MachineInstr::LRSplit attribute

The LRSplit MachineInstr flag is set by SplitKit on copies inserted for
live-range splitting.
Until now the flag had no MIR-text representation.

This patch fixes that so that it gets easier to reproduce/capture issues
that involves SplitKit.

Round-trip coverage in
llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir.
DeltaFile
+168-168llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
+36-36llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
+32-32llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
+27-27llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+22-22llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
+22-22llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir
+307-30731 files not shown
+436-40237 files

LLVM/project 8baf11allvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll regalloc-hoist-spill-live-range-upd.mir

[AMDGPU][test] Use mir test for regalloc issue

Use the newly introduced split-from flag to produce a more robust test case
for the hoistSpillInsideBB live-range update issue.

NFC

DeltaFile
+0-2,870llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll
+71-0llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
+71-2,8702 files

LLVM/project 709aa05llvm/include/llvm/CodeGen MIRYamlMapping.h, llvm/lib/CodeGen MIRPrinter.cpp

[MIR] Save internal VirtRegMap state in MIR

Adds two optional fields to the per-vreg YAML record so MIR tests can
express VirtRegMap state that previously had no representation:

  registers:
    - { id: 1, class: vgpr_32, split-from: '%0', assigned-phys: '$vgpr5' }

Testing passes that consume sibling-register information (e.g.
InlineSpiller) requires constructing a VirtRegMap with split
relationships from a MIR test, which implies triggering live-range
splitting at minimum and make reproducers unnecessarily complicated.

So this change introduces a mechanism to serialize/deserialize the state
of the VirtRegMap pass.

Mechanism:
- For serialization:
  - MIRPrinter emits the new fields only when the VirtRegMap is available.

    [15 lines not shown]
DeltaFile
+48-0llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+24-9llvm/lib/CodeGen/MIRPrinter.cpp
+32-0llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
+18-0llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
+16-1llvm/include/llvm/CodeGen/MIRYamlMapping.h
+17-0llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
+155-105 files not shown
+214-1411 files

FreeBSD/ports ffbe943security/vuxml/vuln 2026.xml

security/vuxml: document Gitlab vulnerabilities
DeltaFile
+77-0security/vuxml/vuln/2026.xml
+77-01 files

LLVM/project d9e26c4flang/lib/Optimizer/OpenMP FunctionFiltering.cpp, mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

Reject target map iterators without captures

Reject target map iterators until the follow-up capture-binding
representation is added since currently map_iterated on omp.target
only represents the dynamic map list and does not consider the
target-region arguments required by IsolatedFromAbove.
DeltaFile
+0-23mlir/test/Dialect/OpenMP/ops.mlir
+0-19mlir/test/Target/LLVMIR/openmp-todo.mlir
+5-5mlir/test/Dialect/OpenMP/invalid.mlir
+5-0mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+0-1flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
+10-485 files

LLVM/project 98f2f8cclang-tools-extra/clang-tidy doc8.ini

[clang-tidy] Remove 80 char limit checking in CI. NFC. (#197609)

The
[RFC](https://discourse.llvm.org/t/rfc-remove-80-column-limit-in-documentation-files/89678/41)
on removing 80 columns limit got accepted. So we should no longer
enforce that rule in clang-tidy's code-linter workflow.
DeltaFile
+1-0clang-tools-extra/clang-tidy/doc8.ini
+1-01 files

LLVM/project ad8352fllvm/include/llvm/CodeGen MIRYamlMapping.h, llvm/lib/CodeGen MIRPrinter.cpp

[MIR] Save internal VirtRegMap state in MIR

Adds two optional fields to the per-vreg YAML record so MIR tests can
express VirtRegMap state that previously had no representation:

  registers:
    - { id: 1, class: vgpr_32, split-from: '%0', assigned-phys: '$vgpr5' }

Testing passes that consume sibling-register information (e.g.
InlineSpiller) requires constructing a VirtRegMap with split
relationships from a MIR test, which implies triggering live-range
splitting at minimum and make reproducers unnecessarily complicated.

So this change introduces a mechanism to serialize/deserialize the state
of the VirtRegMap pass.

Mechanism:
- For serialization:
  - MIRPrinter emits the new fields only when the VirtRegMap is available.

    [15 lines not shown]
DeltaFile
+48-0llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+25-8llvm/lib/CodeGen/MIRPrinter.cpp
+32-0llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
+18-0llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
+17-1llvm/include/llvm/CodeGen/MIRYamlMapping.h
+17-0llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
+157-95 files not shown
+216-1311 files

NetBSD/pkgsrc 0OMbc6xfilesystems Makefile

   sort
VersionDeltaFile
1.63+2-2filesystems/Makefile
+2-21 files

LLVM/project 6f65e88mlir/include/mlir/Dialect/OpenMP OpenMPOps.td, mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

Simplify map iterator clause assembly

- Split MLIR map syntax into separate map_entries(...) and map_iterated(...),
  removing the custom MapEntryList parser/printer.
- Moved omp.target map_iterated out of TargetOpRegion
  - it now prints before the target region instead of as map_iterated_entries(...) after the region.
- Renamed LLVMIR TODO helper to clause-style checkMap.
- Added DeclareMapperInfoOp builder from DeclareMapperInfoOperands
  and updated Flang call sites so they do not need to spell out newly
  added operands..
DeltaFile
+9-85mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+14-14mlir/test/Dialect/OpenMP/ops.mlir
+12-12mlir/test/Dialect/OpenMP/invalid.mlir
+6-8mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+7-7mlir/test/Target/LLVMIR/openmp-todo.mlir
+6-3mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
+54-1293 files not shown
+60-1379 files

LLVM/project 9b5d10fmlir/test/Dialect/OpenMP invalid.mlir

Fix operandSegmentSizes mismatch after rebase
DeltaFile
+1-1mlir/test/Dialect/OpenMP/invalid.mlir
+1-11 files