[GlobalISel] Add `or_and_xor_to_or` pattern from SelectionDAG (#204614)
PR #201108 was merged and then reverted due to a failing test. This PR
fixes the tests that failed.
[lldb] Don't enable Objective-C in expressions on unsupported formats (#204639)
Evaluating any expression against a WebAssembly target aborted LLDB:
```
(lldb) expr (int)sizeof(Point)
LLVM ERROR: Objective-C support is unimplemented for object file format
```
WebAssembly can't JIT expressions (RuntimeDyld doesn't support the Wasm
object format, so ProcessWasm sets CanJIT to false), but it can handle
simple expressions that can be IR interpreted.
When setting up the expression's language options, LLDB speculatively
enables Objective-C, which trips up the fatal error as Objective-C code
generation only supports Mach-O, ELF, and COFF.
Add ObjCLanguageRuntime::IsSupportedForArchitecture and disable
Objective-C in the expression's language options when the target's
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[AArch64][TTI] Surface per-CPU branch misprediction penalty to SimplifyCFG (#201484)
AArch64 scheduling models already define `MispredictPenalty` per CPU
(e.g.,
Neoverse V2 = 11, Cortex-A55 = 8, Cyclone = 16), but this value was
never surfaced through TargetTransformInfo. The base class default of 0
effectively disabled profile-guided speculation of unpredictable
branches
in SimplifyCFG's foldTwoEntryPHINode.
Override `getBranchMispredictPenalty` in AArch64TTIImpl to read from the
scheduling model, enabling SimplifyCFG to speculate instructions into
conditional selects when the speculation cost is justified by the
misprediction penalty, matching the behavior X86 already has (hardcoded
at 14 cycles).
Godbolt: https://godbolt.org/z/68czz556j
(note: I am not sure why godbolt is not showing the compiler I saved,
but essentially the example shows the comparison of aarch64 clang vs.
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[InstCombine] Drop assumption-cache update in freezeOtherUses (#204599)
Redundant now that freezeOtherUses re-queues the rewritten users
(#202306), which re-processes them in the same iteration. Added in
#192935 to avoid a fixpoint-verifier failure.
[AMDGPU][docs] Remove abandoned augementation-related changes
These haven't been carried forward in the DWARF committee proposal, and
we don't expect them to standardized (at least in the form presented
here). Drop them to avoid confusion.
Change-Id: I60dd6ffb5df1bb63d132733466ecf3d697f79276
[AMDGPU][docs] Correct DWARF extension attribute encodings
These were not updated when the final numbers were committed in
Dwarf.def, so update them now.
Change-Id: Ide931b835dc2c5def60dd7fad29525f598e8c8b6
Import nextcloud-34.0.0
Comment:
easy and universal access to shared and/or personal files
Description:
Access, share and protect your files, calendars,
contacts, communication & more at home and in your enterprise
Maintainer: Gonzalo L. R. <gonzalo at openbsd.org>
WWW: https://nextcloud.com/
OK landry@
[AMDGPU][docs] Correct DWARF extension attribute encodings (#204419)
These were not updated when the final numbers were committed in
Dwarf.def, so update them now.
Change-Id: Ide931b835dc2c5def60dd7fad29525f598e8c8b6
[AMDGPU][MFI] Implement missing deserialization of dynamicVGPRBlockSize (#201939)
dynamicVGPRBlockSize can be set by the amdgpu-dynamic-vgpr-block-size
attribute. MFI takes precedence when we deserialize.
[APFloat] Extend fltSemantics and drop special case E8M0 bit conversionJan/apfloat e8m0 (#204200)
This is one step towards being able to make APFloat extensible with
custom formats in the future.
fltSemantics gained a new flag to indicate lack of denormal support.
Combined with hasZero = 0 it means exponent 0 does not have a special
meaning. This makes it possible to remove the special case
implementation for initFromFloat8E8M0FNUAPInt and handle it in the
generic version.
The generic initFromIEEEAPInt function now also supports existing
fltSemantics flags for hasZero, and hasSignedRepr which where only
needed in the specialized initFromFloat8E8M0FNUAPInt.
Also adds new tests for bitcasting to and from APInt. There are several
tests involving bitcastToAPInt together with convert functions but none
explicitly verify the functionality of bitcastToAPInt.
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[AArch64] Move aggressive-interleaving.ll test to LoopVectorizer tests. NFC (#204652)
It looks like this test was put into CodeGen where it would better live
with
other vectorizer tests in Transforms/LoopVectorize/AArch64.
[lldb][Mach-O] Fix two fuzzer-found hangs/crashes parsing universal Mach-O fat headers (#204471)
This fixes two denial-of-service issues in the universal (fat) Mach-O
container parser, both found by `lldb-target-fuzzer` and both reachable
from
`SBDebugger::CreateTarget` → `ObjectFile::GetModuleSpecifications` →
`ObjectContainerUniversalMachO::{GetModuleSpecifications,ParseHeader}`.
### 1. Bound the fat header arch loop by available data
`ParseHeader` read the untrusted 32-bit `nfat_arch` field and used it
directly
as the loop bound when indexing the `fat_arch` records, without
validating it
against the data actually present. A crafted header claiming
`nfat_arch = 0xFFFFFFFF` with only a few bytes of payload made the loop
spin
~4.29 billion times — `ValidOffsetForDataOfSize()` fails on every
iteration
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[mlir][emitc] Apply type converter to memref element types in -convert-memref-to-emitc (#203742)
This change fixes a few places where the memref-to-emitc
conversion didn't properly convert memref element types.
This PR updates both memref.alloc and memref.copy to convert the memref
element type when using the element type for `sizeof` calls, as well as
generating the output pointer type (just for `alloc`).
This was missed because there are no `convert-to-emitc` tests that use a
type converter with custom types, so I added such a registration to the
test dialect. It is worth noting that, while this patch only affects
`-convert-memref-to-emitc`, the change has no impact without the
additional type converter registrations in `-convert-to-emitc` because
there are no builtin types that have nontrivial emit conversions today.
As a drive-by improvement, I deduped a "total size in bytes" calculation
that was happening in the lowerings for both `memref.alloc` and
`memref.copy`.
[RISCV][XCV] Fix incorrect llvm.ctlz lowering to cv.fl1 (#197288)
Fixes #197006.
The XCVbitmanip pattern `def : PatGpr<ctlz, CV_FL1, i32>;` is
semantically incorrect: `cv.fl1` returns a bit position while
`llvm.ctlz` returns a leading-zero count. They differ by up to 31 on
every non-zero input, miscompiling every use of `__builtin_clz`,
including compiler-rt's `__udivdi3`.
This PR:
- Replaces the pattern with one matching `llvm.ctlz` with
`is_zero_poison=true`, lowered to `xori (cv.fl1 rs1), 31`.
- Adds explicit `setOperationAction` calls in `RISCVISelLowering.cpp`
to route `ISD::CTLZ` to generic expansion and keep
`ISD::CTLZ_ZERO_*` matched by the `.td` pattern.
The companion `def : PatGpr<cttz, CV_FF1, i32>;` is correct as-is
(both return 32 on zero, coincide on non-zero), and is left
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[scudo] Remove static error info functions. (#204483)
Android was the only platform using the static error info functions. The
latest Android no longer uses them, so delete these unused functions.
These functions were implicitly exporting implementation details and
made it difficult to implement the multi-region code. This is the final
step to submit the multi-region code and modify how the region code
works.
Remove the error info fuzzer since that was only necessary since so many
values were passed in to the function.
[flang][OpenMP] Emit warning that REVERSE_OFFLOAD is not supported
Right now we quietly ignore it, whereas the OpenMP spec mandates a
compilation error for requirements that the implmentation does not
support.
The REVERSE_OFFLOAD was not causing a compilation error to allow
testing of incremental implementation improvements, but we should
at least warn about not supporting it.
