FreeBSD/src eccd366sys/dev/sound/midi midi.c midiq.h, sys/dev/sound/pci hdspe-pcm.c cs4281.c

sound: Replace MIN() with min()

We use min() in most places.

No functional change intended.

Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
DeltaFile
+5-5sys/dev/sound/midi/midi.c
+2-2sys/dev/sound/midi/midiq.h
+2-2sys/dev/sound/usb/uaudio.c
+2-2sys/dev/sound/pci/hdspe-pcm.c
+1-1sys/dev/sound/pci/cs4281.c
+12-125 files

FreeBSD/src aa58af0usr.sbin/sndctl sndctl.c sndctl.8

sndctl(8): Add libxo support

Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Reviewed by:    ziaee, mckusick
Differential Revision:  https://reviews.freebsd.org/D54032
DeltaFile
+100-51usr.sbin/sndctl/sndctl.c
+10-1usr.sbin/sndctl/sndctl.8
+1-1usr.sbin/sndctl/Makefile
+111-533 files

FreeNAS/freenas cd44d53src/middlewared/middlewared/plugins smb.py

NAS-139267 / 26.04 / Fix validation for netbios alias change (#18000)

This commit fixes a syntax error when validating netbios alias changes
when directory services are enabled.
DeltaFile
+1-1src/middlewared/middlewared/plugins/smb.py
+1-11 files

LLVM/project 986a1a5llvm/test/CodeGen/AMDGPU ran-out-of-sgprs-allocation-failure.mir

lit test update after rebase from main.
DeltaFile
+81-102llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+81-1021 files

FreeBSD/ports 4605922devel/ruby-build distinfo Makefile

devel/ruby-build: Update to 20260110

Changes:        https://github.com/rbenv/ruby-build/releases/tag/v20260110
DeltaFile
+3-3devel/ruby-build/distinfo
+1-1devel/ruby-build/Makefile
+4-42 files

LLVM/project 66cb85allvm/test/CodeGen/AMDGPU regpressure-mitigation-with-subreg-reload.mir

test rebase
DeltaFile
+12-12llvm/test/CodeGen/AMDGPU/regpressure-mitigation-with-subreg-reload.mir
+12-121 files

LLVM/project 710afcdllvm/lib/Target/AMDGPU #SIRegisterInfo.cpp#, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll skip-partial-reload-for-16bit-regaccess.mir

[InlineSpiller][AMDGPU] Implement subreg reload during RA spill

Currently, when a virtual register is partially used, the
entire tuple is restored from the spilled location, even if
only a subset of its sub-registers is needed. This patch
introduces support for partial reloads by analyzing actual
register usage and restoring only the required sub-registers.
This improvement enhances register allocation efficiency,
particularly for cases involving tuple virtual registers.
For AMDGPU, this change brings considerable improvements
in workloads that involve matrix operations, large vectors,
and complex control flows.
DeltaFile
+3,429-4,107llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+3,938-0llvm/lib/Target/AMDGPU/#SIRegisterInfo.cpp#
+91-0llvm/test/CodeGen/AMDGPU/skip-partial-reload-for-16bit-regaccess.mir
+35-56llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+40-40llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
+26-52llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+7,559-4,25568 files not shown
+7,886-4,48174 files

LLVM/project 7676097llvm/test/CodeGen/AMDGPU regpressure-mitigation-with-subreg-reload.mir

compacted the virt-reg numbers
DeltaFile
+14-14llvm/test/CodeGen/AMDGPU/regpressure-mitigation-with-subreg-reload.mir
+14-141 files

LLVM/project 6f69429llvm/test/CodeGen/AMDGPU regpressure-mitigation-with-subreg-reload.mir

[AMDGPU] Test precommit for subreg reload

This test currently fails due to insufficient
registers during allocation. Once the subreg
reload is implemented, it will begin to pass
as the partial reload help mitigate register
pressure.
DeltaFile
+37-0llvm/test/CodeGen/AMDGPU/regpressure-mitigation-with-subreg-reload.mir
+37-01 files

LLVM/project 5647ba0llvm/lib/Target/AMDGPU SIRegisterInfo.cpp SIRegisterInfo.h

[AMDGPU] Put back ProperlyAlighedRC helper functions

Putting back the functions that are recently deleted
as they were found unused. They are needed for
implementing subreg reload during RA.
DeltaFile
+22-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+5-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+27-02 files

LLVM/project 82cd3bfllvm/lib/Target/AMDGPU SIRegisterInfo.cpp

incorporated review comments.
DeltaFile
+3-3llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+3-31 files

LLVM/project 680089allvm/test/CodeGen/AMDGPU ran-out-of-sgprs-allocation-failure.mir ra-inserted-scalar-instructions.mir

[AMDGPU] Introduce Offset field in SGPR spill Pseudos

Currently, SGPR spill pseudo-instructions lack
an offset field to represent non-zero stack offsets.
This patch introduces an additional offset field to
SGPR spill pseudo-instructions and updates all
relevant passes that handle spill lowering to support
this new field. This field is essential for a future
patch that implements subreg reload of tuple registers
from their stack location during RA.
DeltaFile
+29-29llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+22-22llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
+16-16llvm/test/CodeGen/AMDGPU/remat-sop.mir
+14-14llvm/test/CodeGen/AMDGPU/remat-smrd.mir
+9-9llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
+8-8llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
+98-9835 files not shown
+167-16541 files

LLVM/project 975be2fllvm/include/llvm/CodeGen LiveRangeEdit.h, llvm/lib/CodeGen LiveRangeEdit.cpp

[CodeGen] Enhance createFrom for sub-reg aware cloning

Instead of just cloning the virtual register, this
function now creates a new virtual register derived
from a subregister class of the original value.
DeltaFile
+9-1llvm/lib/CodeGen/LiveRangeEdit.cpp
+5-2llvm/include/llvm/CodeGen/LiveRangeEdit.h
+14-32 files

LLVM/project b180da6llvm/include/llvm/CodeGen TargetRegisterInfo.h, llvm/lib/CodeGen TargetRegisterInfo.cpp

[AMDGPU] Make AMDGPURewriteAGPRCopyMFMA aware of subreg reload

AMDGPURewriteAGPRCopyMFMA pass is currently not subreg-aware.
In particular, the logic that optimizes spills into COPY
instructions assumes full register reloads. This becomes
problematic when the reload instruction partially restores
a tuple register. This patch introduces the necessary changes
to make this pass subreg-aware, for a future patch that
implements subreg reload during RA.
DeltaFile
+41-1llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+10-0llvm/lib/CodeGen/TargetRegisterInfo.cpp
+3-0llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+54-13 files

LLVM/project 0ebaff5llvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp

suggestions incorporated.
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+2-21 files

LLVM/project 4142195llvm/lib/Target/AMDGPU SIRegisterInfo.cpp SIInstrInfo.cpp

moved the implementation to SIInstrInfo.
DeltaFile
+1-149llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+146-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+0-2llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+150-1514 files

LLVM/project 3042367llvm/lib/Target/AMDGPU SIRegisterInfo.cpp SIRegisterInfo.h

[AMDGPU] Make getNumSubRegsForSpillOp externally available (NFC).
DeltaFile
+3-3llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+5-32 files

FreeBSD/ports 12ed3bdjava/openjdk19 Makefile distinfo

java/openjdk19: Bootstrap port from prebuilt package

Change the way the port is bootstrapped, by extracting a prebuild
package to the work dir, instead of installing the previous openjdk
version to the system.

Reviewed by:    bofh (mentor)
Approved by:    bofh (mentor)
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D54608
DeltaFile
+8-16java/openjdk19/Makefile
+11-1java/openjdk19/distinfo
+19-172 files

DragonFlyBSD/src 610965dusr.sbin/makefs/hammer2 hammer2_chain.c hammer2_vnops.c

usr.sbin/makefs: Sync with sys/vfs/hammer2

Sync with following sys/vfs/hammer2 commits.

$ git log --pretty="%h %s" fb6876367e661ff6b883baafc4e204432813da9b.. -- sys/vfs/hammer2/
d21046eeda Fix various typos
5f49e876b9 hammer2 - Add debugging
abe564f10e kernel - Minor Syntax cleanup
0d0182bdb4 hammer2 - disable FIOSEEKHOLE
a9d812fe50 sys/vfs/hammer2: Remove hardlink related obsolete comments
af1833426b sys/vfs/hammer2: Add missing ctime updates
DeltaFile
+24-3usr.sbin/makefs/hammer2/hammer2_chain.c
+10-17usr.sbin/makefs/hammer2/hammer2_vnops.c
+8-12usr.sbin/makefs/hammer2/hammer2_inode.c
+5-0usr.sbin/makefs/hammer2/hammer2_ioctl.c
+3-2usr.sbin/makefs/hammer2/hammer2_vfsops.c
+1-3usr.sbin/makefs/hammer2/hammer2_xops.c
+51-376 files

LLVM/project 0275c9fllvm/test/ExecutionEngine/JITLink/AArch64 backtrace-symbolication.s

[llvm-jitlink] Remove build_version directive. (#175523)

Fixes a warning on some bots.
DeltaFile
+0-1llvm/test/ExecutionEngine/JITLink/AArch64/backtrace-symbolication.s
+0-11 files

LLVM/project ce4fcfcllvm/include/llvm/ExecutionEngine RuntimeDyldChecker.h, llvm/test/ExecutionEngine/JITLink/AArch64 ELF_zero_sized_symbols_with_show_addrs.s

 [llvm-jitlink] Make -show-addrs work without -check, fix fallout. (#175491)

Ensures that the address scraping passes are added to the JIT linker pipeline
if either of the -check or -show-addrs are passed. Prior to this commit we only
considered -check, so passing -show-addrs on its own was printing an empty
(unpopulated) symbol table.

This change exposed bugs in RuntimeDyldChecker's `MemoryRegionInfo` type, aned
llvm-jitlink's symbol printing code:

 - `MemoryRegionInfo` was assuming that zero-sized symbols wouldn't be defined
   and was using Size == 0 as a proxy for "region info uninitialized". This was
   triggering assertions for valid LinkGraphs containing zero-sized symbols.

 - llvm-jitlink's symbol printing code was assuming that all defined symbols
   contained content, and was not correctly handling zero-fill / absolute
   symbols. This triggered assertions about requesting content addresses for
   non-content symbols.


    [3 lines not shown]
DeltaFile
+14-7llvm/include/llvm/ExecutionEngine/RuntimeDyldChecker.h
+11-6llvm/tools/llvm-jitlink/llvm-jitlink.cpp
+16-0llvm/test/ExecutionEngine/JITLink/AArch64/ELF_zero_sized_symbols_with_show_addrs.s
+14-0llvm/test/ExecutionEngine/JITLink/Generic/llvm-jitlink-option-show-addrs.test
+2-0llvm/tools/llvm-jitlink/llvm-jitlink-elf.cpp
+57-135 files

FreeNAS/freenas 73a8287src/middlewared/middlewared/plugins smb.py

Fix validation for netbios alias change

This commit fixes a syntax error when validating netbios alias
changes when directory services are enabled.
DeltaFile
+1-1src/middlewared/middlewared/plugins/smb.py
+1-11 files

LLVM/project ff005aautils/bazel/llvm-project-overlay/clang BUILD.bazel, utils/bazel/llvm-project-overlay/clang/unittests BUILD.bazel

Fix bazel test failures caused in #175435 (#175533)

DeltaFile
+1-1utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+2-12 files

FreeBSD/ports 606cb0cnet-mgmt/librenms distinfo Makefile

net-mgmt/librenms: Update to 26.1.0

re: https://github.com/librenms/librenms/releases/tag/26.1.0
DeltaFile
+5-5net-mgmt/librenms/distinfo
+3-4net-mgmt/librenms/Makefile
+8-92 files

NetBSD/pkgsrc seYIrXIdoc CHANGES-2026

   doc: Updated textproc/television to 0.14.5
VersionDeltaFile
1.260+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc C1FL4U8textproc/television/files files.toml

   textproc/television: remove obsolete file
VersionDeltaFile
1.4+0-0textproc/television/files/files.toml
+0-01 files

HardenedBSD/src aaca42b.github/workflows checklist.yml, lib/msun/powerpc fenv.c fenv.h

Merge remote-tracking branch 'origin/hardened/current/master' into hardened/current/cross-dso-cfi
DeltaFile
+96-10.github/workflows/checklist.yml
+0-96libexec/rtld-elf/powerpc/rtld_start.S
+0-36sys/powerpc/powerpc/trap.c
+0-34lib/msun/powerpc/fenv.c
+0-23lib/msun/powerpc/fenv.h
+0-22sys/powerpc/booke/trap_subr.S
+96-22116 files not shown
+117-28522 files

NetBSD/pkgsrc ROQfKrUnet/net-snmp distinfo, net/net-snmp/patches patch-agent_mibgroup_host_data__access_swinst__darwin.c

   net-snmp: darwin build fix
VersionDeltaFile
1.1+24-0net/net-snmp/patches/patch-agent_mibgroup_host_data__access_swinst__darwin.c
1.107+2-1net/net-snmp/distinfo
+26-12 files

OPNSense/core 6f47a0asrc/etc/inc/plugins.inc.d radvd.inc, src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms dialogEntry.xml

radvd: support nat64prefix; closes #7487 #8289
DeltaFile
+26-2src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.php
+10-0src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms/dialogEntry.xml
+5-0src/etc/inc/plugins.inc.d/radvd.inc
+4-0src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.xml
+45-24 files

HardenedBSD/src 5006ab9.github/workflows checklist.yml, lib/msun/powerpc fenv.c fenv.h

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+96-10.github/workflows/checklist.yml
+0-96libexec/rtld-elf/powerpc/rtld_start.S
+0-36sys/powerpc/powerpc/trap.c
+0-34lib/msun/powerpc/fenv.c
+0-23lib/msun/powerpc/fenv.h
+0-22sys/powerpc/booke/trap_subr.S
+96-22116 files not shown
+117-28522 files