ig4: unconditionally un-idle the controller core on resume
On controllers with the LPSS "additional registers" (Skylake and later,
IG4_HAS_ADDREGS), ig4iic_suspend() places the controller in the device
idle state (IG4_DEVICE_IDLE) and asserts core reset. While idle the
DesignWare core is power-gated: its register bank reads back as zero and
writes are dropped until the core is taken out of the idle state again.
ig4iic_set_config(), called from ig4iic_resume(), only performs that
un-idle handshake when it observes IG4_RESTORE_REQUIRED set in
DEVIDLE_CTRL. Some platforms (e.g. Intel Alder Lake-P) do not raise
that status across suspend-to-idle (S0ix). The core is then left gated:
set_config()'s register writes have no effect, it nevertheless returns
success, and every subsequent transfer fails with IIC_ETIMEOUT, leaving
child I2C-HID devices (touchpad, touchscreen) dead after resume.
Give ig4iic_set_config() a force_restore argument and pass it from
ig4iic_resume() so the un-idle handshake runs unconditionally for
IG4_HAS_ADDREGS controllers, regardless of the RESTORE_REQUIRED status.
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[tsan] fit Go/s390x mapping under QEMU (#204503)
QEMU linux-user first tries guest_base=0. In that identity-mapped mode,
fixed guest mappings use the same host addresses. On an x86-64 host
with four-level page tables, the Go/s390x meta shadow starts at
144 TiB, beyond the 128 TiB userspace limit, and its mmap fails with
ENOMEM during TSan initialization.
Move the meta shadow down by 32 TiB to
[0x700000000000, 0x780000000000), restoring the 16 TiB gap after the
shadow and placing all Go/s390x TSan regions below 2^47. Correct the
mapping comment's shadow size and ratio.
Failure report and native s390x comparison:
https://github.com/golang/go/issues/67881
QEMU identity guest-base selection:
https://github.com/qemu/qemu/blob/v10.2.3/linux-user/elfload.c#L1036-L1042
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[orc-rt] Sink Session::sendWrapperResult into Session.cpp. NFC. (#204956)
This function is never called inline (except by Session::wrapperReturn,
which is also in Session.cpp), so there's no need for it to be in the
header.
[SimplifyCFG] Avoid threading loop-header branches in convergent functions
SimplifyCFG can fold a conditional branch when the condition is known from
a predecessor. When the destination is a loop header in a convergent function,
this can change the dynamic convergence structure of the loop even though the
scalar CFG rewrite is otherwise valid.
Skip this fold for loop-header branches in convergent functions so convergent
control flow is preserved.
Fixes ROCM-26496.
pgpkeys: Add myself to the list
My pgp key has been in the repo for many years but apparently I wasn't
listed in the pgpkeys article.
PR: 296173
Reported by: elivoncoder
graphics/fractgen: Improve port
- Simplify option names: FRACTGEN_CLI => CLI and etc.
- Move CLI KDE QT to MULTI - at least on option must be enabled.
- Move examples from DATADIR to EXAMPLESDIR.
- Sort plist.
PR: 295702
Approved by: Thomas Dreibholz <thomas.dreibholz at gmail.com> (maintainer, timeout 2 weeks)
Sponsored by: UNIS Labs
[clang] Add clang-format-check-format instead to CLANG_TEST_DEPS (#204908)
Ensure that clang-format doesn't break the existing format of its own
source.
Reverts #199169 and #199638.
[AMDGPU][VOPD] Cache load reachability checks in VOPDpairing (#204854)
#201930 causes significant compilation time regression when building
ROCm mathlibs.
Major regressions are caused by repeated queries to `DAG->IsReachable`
to detect possible scalarisation of loads when fusing a pair of
VOPD-capable instructions.
This patch caches the set of reachable loads for every potentially
hazardous load instruction to avoid the need to invoke
`DAG->IsReachable` at all.
[SelectionDAG] Keep split vector atomic store value in a vector register (#201566)
When the value of an ATOMIC_STORE has a vector type whose legalization
action is split (e.g. <4 x half>/<4 x bfloat> on X86 without F16C),
SplitVecOp_ATOMIC_STORE bitcast the value straight to a scalar integer
spanning the memory width. For a split vector that bitcast is expanded
element by element, reassembling the value in GPRs (a long pextrw/shl/or
sequence) before the store.
Instead, keep the value in a vector register when a legal vector form
exists: reinterpret it as a same-shaped integer-element vector (an FP
element type may have no legal vector form, e.g. bfloat on SSE2, while
the integer-of-element-size form does), widen that to a legal vector,
and extract the low integer element of the memory width. This issues the
store directly from a vector register (a single MOVQ/MOVD on X86),
matching the widen-path codegen already produced on AVX targets. Falls
back to the scalar bitcast when no suitable legal vector type exists.
Stacked on top of https://github.com/llvm/llvm-project/pull/197861; and
below of #197862.
[VPlan] Properly check predicates and types in canNarrowOps. (#204948)
Update canNarrowOps to properly check the types of all members match.
Similarly, for recipes with predicates, the predicates must match.
da: Put the SYNC CACHE probing behind bootverbose
These have turned out to be too noisy, so put them behind bootverbose
Event: BSDCan 2026 (noticed during UFS demo)
Sponsored by: Netflix
MFC After: 2 weeks
