FreeBSD/ports 8b0601dsecurity/vuxml/vuln 2026.xml

security/vuxml: Add gitea vulnerabilities

 * CVE-2026-59774
 * CVE-2026-60004
DeltaFile
+38-0security/vuxml/vuln/2026.xml
+38-01 files

LLVM/project b3ccb71llvm/test/CodeGen/RISCV pr148084.ll

[RISCV] Remove experimental from extension names in a test. NFC (#215621)

These extensions are no longer experimental and were giving warnings.
DeltaFile
+1-1llvm/test/CodeGen/RISCV/pr148084.ll
+1-11 files

LLVM/project 2440e24llvm/lib/Target/NVPTX NVPTXPassRegistry.def NVPTXTargetMachine.cpp

[NVPTX] Add NewPM boilerplate to NVPTXPeephole (#215330)
DeltaFile
+40-27llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
+8-2llvm/lib/Target/NVPTX/NVPTX.h
+2-2llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+1-0llvm/lib/Target/NVPTX/NVPTXPassRegistry.def
+51-314 files

FreeBSD/ports bcd1516sysutils/screen-devel Makefile

sysutils/screen-devel: Remove unneeded WRKSRC assignment

Fixes:          92fefcf39e03
DeltaFile
+0-2sysutils/screen-devel/Makefile
+0-21 files

FreeBSD/ports d63f778mail/nmh-devel Makefile

mail/nmh-devel: Remove unneeded WRKSRC assignment

Fixes:          86516d72fab5
DeltaFile
+0-2mail/nmh-devel/Makefile
+0-21 files

LLVM/project 21f2d05llvm/lib/Target/NVPTX NVPTXPassRegistry.def NVPTXTargetMachine.cpp

[NVPTX] Add NewPM boilerplate to NVPTXAllocaHoisting (#215325)
DeltaFile
+39-25llvm/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp
+0-22llvm/lib/Target/NVPTX/NVPTXAllocaHoisting.h
+8-1llvm/lib/Target/NVPTX/NVPTX.h
+2-3llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+1-0llvm/lib/Target/NVPTX/NVPTXPassRegistry.def
+50-515 files

HardenedBSD/src dab0085sys/dev/e1000 if_em.c e1000_ich8lan.c, sys/dev/ice ice_drv_info.h

Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/pledge
DeltaFile
+29-14tools/tools/git/git-mfc
+30-0sys/dev/ice/ice_drv_info.h
+4-11usr.sbin/bhyve/amd64/bhyverun_machdep.c
+15-0sys/dev/e1000/e1000_ich8lan.c
+11-1usr.sbin/bhyve/bhyverun.c
+9-0sys/dev/e1000/if_em.c
+98-2630 files not shown
+158-6636 files

HardenedBSD/src 73712efsys/dev/e1000 if_em.c e1000_ich8lan.c, sys/dev/ice ice_drv_info.h

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+29-14tools/tools/git/git-mfc
+30-0sys/dev/ice/ice_drv_info.h
+4-11usr.sbin/bhyve/amd64/bhyverun_machdep.c
+15-0sys/dev/e1000/e1000_ich8lan.c
+11-1usr.sbin/bhyve/bhyverun.c
+9-0sys/dev/e1000/if_em.c
+98-2630 files not shown
+158-6636 files

FreeBSD/ports a545eecsecurity/vuxml/vuln 2026.xml

security/vuxml: Add Chromium vulnerabilities

 * CVE-2026-19137
 * CVE-2026-19149
 * CVE-2026-19154
 * CVE-2026-19157
 * CVE-2026-19170
 * CVE-2026-19172
DeltaFile
+73-0security/vuxml/vuln/2026.xml
+73-01 files

LLVM/project c4b896cclang-tools-extra/docs/clang-tidy/checks/bugprone unhandled-self-assignment.md

Update clang-tools-extra/docs/clang-tidy/checks/bugprone/unhandled-self-assignment.md

Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
DeltaFile
+1-1clang-tools-extra/docs/clang-tidy/checks/bugprone/unhandled-self-assignment.md
+1-11 files

LLVM/project 69a44d9llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-asm-clobber.ll

Diagnose inline asm that clobbers a VGPR-memory object's registers
DeltaFile
+93-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-asm-clobber.ll
+31-5llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+124-52 files

LLVM/project 3ff83ecclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen arm64-microsoft-intrinsics.c

[AArch64] Add __hvc and __svc MS intrinsics (#202582)

This series implements two additional Microsoft `intrin.h` intrinsics in
clang so MSVC-compatible code can build with clang.

| Target | Intrinsic | Description |
|--------|-----------|-------------|
| AArch64 | `__svc` | Supervisor Call (`SVC #imm`) |
| AArch64 | `__hvc` | Hypervisor Call (`HVC #imm`) |

`__hvc` and `__svc` each require a new LLVM intrinsic
(`llvm.aarch64.hvc` / `llvm.aarch64.svc`) to carry the immediate operand
down to instruction selection. The 16-bit immediate is encoded in the
instruction, up to four additional arguments are passed in X0-X3, and the
result is read back from X0. It should match MSVC calling convention.
DeltaFile
+78-0llvm/test/CodeGen/AArch64/arm64-svc.ll
+78-0llvm/test/CodeGen/AArch64/arm64-hvc.ll
+42-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+37-2clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+26-0clang/test/CodeGen/arm64-microsoft-intrinsics.c
+22-0clang/test/Sema/builtins-microsoft-arm64.c
+283-57 files not shown
+344-713 files

FreeBSD/ports 08256bebiology Makefile, biology/py-macs2 distinfo pkg-descr

biology/py-macs2: Remove

MACS2 is dead upstream, with no plans to make it compatible with
cython 3.x or other newer dependencies.  Though the port was
set to expire in another month, I'm removing it now to stop wasting
package building resources.  It has not been buildable for some time.
DeltaFile
+0-40biology/py-macs2/Makefile
+0-4biology/py-macs2/pkg-descr
+0-3biology/py-macs2/distinfo
+0-1biology/Makefile
+0-484 files

HardenedBSD/ports 08256bebiology Makefile, biology/py-macs2 distinfo pkg-descr

biology/py-macs2: Remove

MACS2 is dead upstream, with no plans to make it compatible with
cython 3.x or other newer dependencies.  Though the port was
set to expire in another month, I'm removing it now to stop wasting
package building resources.  It has not been buildable for some time.
DeltaFile
+0-40biology/py-macs2/Makefile
+0-4biology/py-macs2/pkg-descr
+0-3biology/py-macs2/distinfo
+0-1biology/Makefile
+0-484 files

LLVM/project 60850b6clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Headers/hlsl hlsl_compat_overloads.h

[HLSL] Add matrix support for isnan() and isinf() (#195586)

Addresses #184483 and #184505.

Assisted-by: Claude Sonnet 4
DeltaFile
+182-0clang/test/CodeGenHLSL/builtins/isinf_mat.hlsl
+182-0clang/test/CodeGenHLSL/builtins/isnan_mat.hlsl
+115-0clang/test/CodeGenHLSL/builtins/isinf_mat-overloads.hlsl
+115-0clang/test/CodeGenHLSL/builtins/isnan_mat-overloads.hlsl
+68-4clang/lib/Headers/hlsl/hlsl_compat_overloads.h
+14-14clang/lib/CodeGen/CGHLSLBuiltins.cpp
+676-189 files not shown
+731-5115 files

LLVM/project dd7636bllvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Fix compiler warning about copy in Rematerializer (#215609)

Fixes the following warning with the recommended suggestion:

```
llvm/lib/CodeGen/Rematerializer.cpp:329:21: warning: loop variable
'[Reg, Mask]' creates a copy from type 'const value_type' (aka 'const
std::pair<llvm::Register, llvm::LaneBitmask>') [-Wrange-loop-construct]
  329 |     for (const auto [Reg, Mask] :
getUnrematableDeps(DeletedRegIdx)) {
      |                     ^
llvm/lib/CodeGen/Rematerializer.cpp:329:10: note: use reference type
'const value_type &' (aka 'const std::pair<llvm::Register,
llvm::LaneBitmask> &') to prevent copying
  329 |     for (const auto [Reg, Mask] :
getUnrematableDeps(DeletedRegIdx)) {
      |          ^~~~~~~~~~~~~~~~~~~~~~~~
      |                     &
```
DeltaFile
+1-1llvm/lib/CodeGen/Rematerializer.cpp
+1-11 files

LLVM/project 144ab22llvm/lib/CodeGen/SelectionDAG LegalizeDAG.cpp, llvm/test/CodeGen/X86 fp128-ldexp-frexp-no-libcall-error.ll

DAG: Gracefully diagnose missing fp128 ldexp/frexp libcalls

When the fp128 ldexp/frexp libcall is unavailable (e.g. MSVC),
LegalizeDAG crashed instead of emitting a diagnostic. The expansion
path introduces a cast to an integer type, so we can't introduce that
wide integer if it's not legal at this point.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+18-2llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+17-0llvm/test/CodeGen/X86/fp128-ldexp-frexp-no-libcall-error.ll
+35-22 files

LLVM/project a475107mlir/include/mlir/Dialect/OpenACC OpenACCUtilsCG.h OpenACCCGAttributes.td, mlir/lib/Dialect/OpenACC/IR OpenACCCG.cpp

[mlir][acc] Add active parallel dimensions attribute (#215586)

This change adds `acc.active_par_dims` attribute to OpenACC dialect.
This attribute will be used to record which launch dimensions execute an
operation without predication.
DeltaFile
+46-18mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
+17-1mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
+18-0mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
+16-0mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
+13-0mlir/test/Dialect/OpenACC/ops-cg.mlir
+12-0mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
+122-196 files

NetBSD/pkgsrc Q0U5twdwayland/wlroots Makefile

   iwlroots: fix build on NetBSD

   linker complains about cabs etc. in libm
VersionDeltaFile
1.4+3-1wayland/wlroots/Makefile
+3-11 files

LLVM/project 0c38b8eclang/lib/Headers __clang_cuda_math.h, clang/test/CodeGenCUDA sqrtf-precise.cu

[CUDA] Lower device sqrtf through builtin sqrt (#205661)

Lower CUDA Device `sqrtf` through `__builtin_sqrtf` instead of the
libdevice `__nv_sqrtf` wrapper.

This lets the existing NVPTX lowering for `llvm.sqrt.f32` choose between
`sqrt.rn.f32` by default and `sqrt.approx.f32` under `-fapprox-func`.

Fixes #131749

Includes tests in clang/test/CodeGenCUDA/sqrtf-precise.cu

---------

Co-authored-by: Justin Fargnoli <jfargnoli at nvidia.com>
DeltaFile
+37-0clang/test/CodeGenCUDA/sqrtf-precise.cu
+1-1clang/lib/Headers/__clang_cuda_math.h
+38-12 files

LLVM/project 93e7190llvm/lib/CodeGen/GlobalISel CombinerHelper.cpp, llvm/test/CodeGen/AArch64 shift.ll arm64-vshift.ll

[AArch64][GlobalISel] Use PreferredShiftAmountTy in TruncOfShift combine (#213381)

This trunc of shift combine has always caused issues with the shift
amount type no longer matching the new shift type. This patch changes
the type of the shift amount to at least match the
getPreferredShiftAmountTy.
DeltaFile
+8-29llvm/test/CodeGen/AArch64/arm64-vshift.ll
+2-5llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
+5-0llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+2-2llvm/test/CodeGen/AArch64/shift.ll
+2-2llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
+2-2llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
+21-406 files

HardenedBSD/src 34718e0sys/compat/linux linux.h linux_netlink.c

linuxulator: map IFF_LOWER_UP through NETLINK_ROUTE for Linux apps

rtnl_if_flags_to_linux() translated the usual IFF_* bits but dropped
FreeBSD's IFF_LOWER_UP (IFF_NETLINK_1).  Chromium's AddressTrackerLinux
only treats a link as online when ifi_flags has UP|LOWER_UP|RUNNING; with
LOWER_UP missing, online_links stays empty, ConnectionType is
CONNECTION_NONE, and navigator.onLine is false even though TCP/HTTPS
work.  Linux Chromium under the Linuxulator (e.g. www/linux-brave) then
shows a spurious Offline UI; sites that ignore navigator.onLine do not.
Native www/chromium is on a different notifier path.

Map IFF_LOWER_UP to Linux's IFF_LOWER_UP (1<<16) and define
LINUX_IFF_LOWER_UP alongside the existing LINUX_IFF_* constants.

PR:     297424

Reviewed by:    pouria, adrian (previous revision)
Differential Revision:  https://reviews.freebsd.org/D58774
DeltaFile
+4-1sys/compat/linux/linux_netlink.c
+3-0sys/compat/linux/linux.h
+7-12 files

FreeBSD/src 34718e0sys/compat/linux linux.h linux_netlink.c

linuxulator: map IFF_LOWER_UP through NETLINK_ROUTE for Linux apps

rtnl_if_flags_to_linux() translated the usual IFF_* bits but dropped
FreeBSD's IFF_LOWER_UP (IFF_NETLINK_1).  Chromium's AddressTrackerLinux
only treats a link as online when ifi_flags has UP|LOWER_UP|RUNNING; with
LOWER_UP missing, online_links stays empty, ConnectionType is
CONNECTION_NONE, and navigator.onLine is false even though TCP/HTTPS
work.  Linux Chromium under the Linuxulator (e.g. www/linux-brave) then
shows a spurious Offline UI; sites that ignore navigator.onLine do not.
Native www/chromium is on a different notifier path.

Map IFF_LOWER_UP to Linux's IFF_LOWER_UP (1<<16) and define
LINUX_IFF_LOWER_UP alongside the existing LINUX_IFF_* constants.

PR:     297424

Reviewed by:    pouria, adrian (previous revision)
Differential Revision:  https://reviews.freebsd.org/D58774
DeltaFile
+4-1sys/compat/linux/linux_netlink.c
+3-0sys/compat/linux/linux.h
+7-12 files

LLVM/project c88aeafllvm/lib/Target/Hexagon HexagonPseudo.td HexagonAsmPrinter.cpp, llvm/test/CodeGen/Hexagon kcfi.ll kcfi-packetization.ll

[Hexagon] Fix KCFI check truncating type id (#211854)

The KCFI indirect-call check is lowered directly to MCInst in the
Hexagon AsmPrinter. It omitted the constant-extender, causing
mismatches.

Packet canonicalization is how we should apply constant extenders,
duplex, compounds, etc.

Assisted-by: Claude
DeltaFile
+193-0llvm/test/CodeGen/Hexagon/kcfi-packet-context.ll
+117-0llvm/test/CodeGen/Hexagon/kcfi-obj-vs-asm.ll
+113-0llvm/test/CodeGen/Hexagon/kcfi-packetization.ll
+32-30llvm/test/CodeGen/Hexagon/kcfi.ll
+31-8llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+3-1llvm/lib/Target/Hexagon/HexagonPseudo.td
+489-396 files

LLVM/project 9f93da9llvm/include/llvm/IR Use.h

Remove extra semi-colon; NFC (#215604)
DeltaFile
+1-1llvm/include/llvm/IR/Use.h
+1-11 files

OpenBSD/ports jt4C80Ewww/vimb distinfo Makefile, www/vimb/patches patch-config_mk

   update to vimb-4.0.0
   moves to webkitgtk60
VersionDeltaFile
1.30+6-7www/vimb/Makefile
1.15+2-2www/vimb/distinfo
1.4+1-1www/vimb/patches/patch-config_mk
+9-103 files

LLVM/project 2242caaclang/lib/CodeGen/Targets SPIR.cpp, clang/test/CodeGenCUDA amdgpu-kernel-attrs.cu

clang/SPIRV: Respect __launch_bounds__ for AMDHIP case

Follow the somewhat dodgy logic for packing amdgpu_flat_work_group_size
into the X field of max_work_group_size if the value is provided
to __launch_bounds__. The explicit amdgpu_flat_work_group_size takes
precedence, like in the AMDGPU case.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+6-1clang/lib/CodeGen/Targets/SPIR.cpp
+6-0clang/test/CodeGenCUDA/amdgpu-kernel-attrs.cu
+12-12 files

LLVM/project 73f6e56clang/lib/CodeGen/Targets AMDGPU.cpp, clang/lib/Sema SemaDeclAttr.cpp

clang/AMDGPU: Respect __launch_bounds__ attribute

Currently the HIP headers manually implement this with a
macro setting amdgpu attributes, and the proper clang attribute
is silently ignored. Directly map the proper attribute into
the target IR attributes. The first argument sets
"amdgpu-flat-work-group-size" and the second  (reinterpreted by HIP
as minimum waves per EU) sets "amdgpu-waves-per-eu". An explicit
amdgpu_flat_work_group_size / amdgpu_waves_per_eu attribute takes
precedence. This matches the launch_bounds macro in the HIP headers,
which can now be dropped.

The 3rd maxclusterrank argument is only handled for NVPTX, so restrict
the sm_90 arch check to NVPTX targets and ignore the third argument on
other targets.

Fixes #91468

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+31-0clang/test/CodeGenCUDA/amdgpu-kernel-attrs.cu
+28-1clang/lib/CodeGen/Targets/AMDGPU.cpp
+17-6clang/lib/Sema/SemaDeclAttr.cpp
+16-0clang/test/SemaCUDA/launch_bounds_amdgpu.cu
+92-74 files

LLVM/project 38607declang/include/clang/Analysis/Analyses/LifetimeSafety LifetimeAnnotations.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp LifetimeAnnotations.cpp

[Lifetime Safety] Highlight lifetimebound calls in alias chain diagnostics (#206337)

## Summary

This improves Lifetime Safety alias-chain diagnostics by explaining when
an aliasing step comes from a `[[clang::lifetimebound]]` contract.

For example:
```cpp
int *identity(int *p [[clang::lifetimebound]]) {
  return p;
}

void test() {
  int *q;
  {
    int i;
    q = identity(&i);
  }

    [17 lines not shown]
DeltaFile
+90-78clang/test/Sema/LifetimeSafety/safety.cpp
+44-44clang/test/Sema/LifetimeSafety/nocfg.cpp
+87-0clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
+15-49clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+26-6clang/lib/Sema/SemaLifetimeSafety.h
+27-0clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
+289-1773 files not shown
+300-1869 files

LLVM/project 277764fllvm/lib/Transforms/AggressiveInstCombine TruncInstCombine.cpp, llvm/test/Transforms/AggressiveInstCombine trunc_vector_instrs.ll

[AggressiveInstCombine] Bail out if irreducible uses exist (#215573)

Fixes #213688.
For the case below:
```llvm
define i8 @insert_index_is_reduced_value() {
  %cast = trunc i64 0 to i32
  %vecins = insertelement <1 x i32> zeroinitializer, i32 %cast, i32 %cast
  %vecext = extractelement <1 x i32> %vecins, i32 0
  %trunc = trunc i32 %vecext to i8
  ret i8 %trunc
}
```
We do not currently consider the index operand of insertelement
reducible. So `%vecins = insertelement <1 x i32> zeroinitializer, i32
%cast, i32 %cast` cannot be reduced without duplicating `%cast = trunc
i64 0 to i32`. In this case, we should reject the reduction.

Assisted-by: Codex
DeltaFile
+24-20llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
+16-0llvm/test/Transforms/AggressiveInstCombine/trunc_vector_instrs.ll
+40-202 files