[RISCV][P-ext] Add codegen for packed absolute difference sum (#207314)
The pabdsumu/pabdsumau instructions compute the sum of absolute differences
of packed unsigned bytes; pabdsumau also accumulates into rd.
Add the llvm.riscv.pabdsumu and pabdsumau intrinsics. A single-GPR source is
selected directly to pabdsumu.b/pabdsumau.b with isel patterns. A 64-bit
GPRPair source on RV32 has no paired instruction, so it is split during
lowering into two v4i8 halves: reduce the low half (folding in rd when
accumulating), then accumulate the high half into that partial sum.
Cases with a target-illegal result are handled in ReplaceNodeResults:
RV64, i32 result: reduce at i64 and truncate (a 32-bit source is
zero-extended first).
RV32, i64 result: reduce each half with pabdsumu.b and combine the
partial sums with a widening add (waddu/waddau).
[clang][test][darwin] Driver/clang-offload-bundler-zstd.c fails on macOS (#207876)
Driver/clang-offload-bundler-zstd.c isn't supported on Darwin, but
neglected to list the macosx target.
[TableGen] Separate string when digit follows octal escape (#207807)
Silence MSVC warning C4125 by separating the string literals when an
octal escape sequence is followed by a decimal char.
[FIRToMemRef] Doc collectSliceInfoFrom, getMemrefIndices, canonicalizeIndex (#207699)
Also drops the unused `converted` parameter from getMemrefIndices. The
internal workings of these functions were not easy to understand for me
so I worked with Claude to document with examples. Hopefully, that makes
the code easier to read. I reviewed the docs and corrected some obvious
hallucinations produced by the agent.
Co-Authored-By: Claude Sonnet 4.6 noreply at anthropic.com
[ELF,test] Fix FileCheck RUN line in gc-sections-keep-shared-start.s (#207678)
Fix a malformed multiline RUN line.
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Co-authored-by: Fangrui Song <i at maskray.me>
[RISCV][MC] Improve diagnostics for Zclsd RV32 GPR pair operands (#207639)
Add dedicated assembler diagnostics for the RV32 GPR pair operands used
by
Zclsd compressed load/store pair instructions.
After the RISC-V asm parser started reporting multiple near-miss
reasons, these
operands still fell back to the generic "invalid operand for
instruction" note.
Give them explicit diagnostic types and messages so invalid register
pairs report
the expected pair constraints.
[LLDB][FreeBSD] Fix build from FileSpec change (#207819)
FileSpec now returns llvm::StringRef instead of ConstString. As a
result, we don't need to use GetCString to get the raw string. Remove it
to fix build failure.
Fixes: f9b5264523b1 (#206802)
[LFI][X86] Add X86 LFI target and system instruction rewrites (#189569)
This PR introduces an x86-64 backend for Lightweight Fault Isolation
(LFI), similar to the one being developed for AArch64. LFI is a
compiler-based mechanism that enables efficient in-process sandboxing.
See the RFC from last fall for details.
This PR adds the `x86_64_lfi` target (similar to `aarch64_lfi`), sets up
reserved registers, and implements some initial rewrites for system
instructions (system calls and TLS accesses). The rewrites are done at
the MC level, using the `MCLFIRewriter` infrastructure. I have updated
the documentation to describe the x86-64 sandboxing scheme and to list
rewrites that will be implemented in future PRs (to keep each individual
PR small).
For performance and compatibility reasons, the plan is currently to use
bundling for maintaining control-flow integrity in the sandbox, which
is not yet supported. For now we are setting up the rewrites without using
bundling, but we can also use a CFI mechanism based on shadow
stack+endbr in order to have something usable while bundling is
in progress.
[AMDGPU] Fix whole-wave function prologue to set EXEC to -1 (#207781)
A whole-wave function body must run with all lanes on. With no WWM
spills the prologue emitted `S_XOR_SAVEEXEC`, giving `EXEC` =
`~entryEXEC`
[SPIR-V] Fix ArrayStride truncation to 0 for sub-byte element types (#207140)
addArrayStrideDecorations computed the stride as `getTypeSizeInBits/8`
which truncates to 0 for sub-byte element types such as i1
0 strides are disallowed in spec
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Co-authored-by: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
