LLVM/project 3db365dflang/include/flang/Runtime extensions.h

[flang-rt] Fix defining `pid_t` on GPU builds (#178470)

Summary:
We support building flang-rt on GPU targets. These do not have POSIX
types so we should not include this if it's not present.
DeltaFile
+2-2flang/include/flang/Runtime/extensions.h
+2-21 files

LLVM/project 3d5dc54llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

Merge branch 'main' into users/usx95/01-23-transparent_functions_for_all_gsl_pointers
DeltaFile
+74,257-82,975llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+26,135-30,267llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,044-11,203llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+5,872-6,681llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+2,674-3,346llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,521-1,873llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+119,503-136,345136 files not shown
+129,256-141,451142 files

LLVM/project c75d371llvm/test/CodeGen/AArch64 sve-calling-convention.ll stp-opt-with-renaming-undef-assert.mir, llvm/test/CodeGen/Mips optimizeAndPlusShift.ll

[LLVM] Fix typo "LABLE" in test checks (#178451)

DeltaFile
+9-9llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll
+2-2llvm/test/CodeGen/AArch64/sve-calling-convention.ll
+2-2llvm/test/CodeGen/X86/tailregccpic.ll
+1-1llvm/utils/DSAclean.py
+1-1llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
+1-1llvm/test/MC/AsmParser/altmacro_string_escape.s
+16-162 files not shown
+17-188 files

LLVM/project fd45140llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/AArch64 tbz-tbnz.ll

[DAG] SimplifyDemandedBits - ICMP_SLT(X,0) - only sign mask of X is required (#164946)

Resolves #164589
DeltaFile
+35-31llvm/test/CodeGen/X86/is_fpclass-fp80.ll
+21-28llvm/test/CodeGen/X86/test-shrink.ll
+28-16llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+22-19llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
+5-24llvm/test/CodeGen/AArch64/tbz-tbnz.ll
+8-11llvm/test/CodeGen/X86/combine-smax.ll
+119-1299 files not shown
+162-17515 files

LLVM/project 7e3859cllvm/lib/Target/X86 X86ISelLowering.cpp

[X86] LowerBUILD_VECTORvXbf16 - pull out repeated MVT::f16/bf16 selection. NFC. (#178467)

DeltaFile
+3-4llvm/lib/Target/X86/X86ISelLowering.cpp
+3-41 files

FreeBSD/ports efa59bbsysutils/fluent-bit Makefile, sysutils/fluent-bit/files fluent-bit.in

sysutils/fluent-bit: Improve RC script and fix issues

* Document 'fluent_bit_group' variable
* Install PID file with mode 0600 instead of 0755
* Reuse ${name}
* Pass '-t {name}' to daemon(8)
* Remove self-created PID file

PR:             292782
MFH:            2026Q1
Approved by:    girgen (maintainer)
DeltaFile
+10-3sysutils/fluent-bit/files/fluent-bit.in
+1-1sysutils/fluent-bit/Makefile
+11-42 files

FreeNAS/freenas a4ea77bsrc/middlewared/middlewared/plugins/boot_ boot_loader.py, src/middlewared/middlewared/plugins/update_ upload_location_linux.py utils_linux.py

NAS-139295 / 26.0.0-BETA.1 / Add umount utility (#18016)

This commit exposes truenas_os.umount2 as an available utility in
mount.py, and replaces existing subprocess calls to the umount command
with the syscall-based utility.
DeltaFile
+63-1src/middlewared/middlewared/utils/mount.py
+2-1src/middlewared/middlewared/plugins/boot_/boot_loader.py
+2-1src/middlewared/middlewared/plugins/update_/upload_location_linux.py
+2-1src/middlewared/middlewared/plugins/update_/utils_linux.py
+69-44 files

FreeNAS/freenas 7f97614src/middlewared/middlewared/utils mount.py

pass SB_SOURCE flag
DeltaFile
+2-1src/middlewared/middlewared/utils/mount.py
+2-11 files

LLVM/project ffeb7d7mlir/lib/Analysis DataFlowFramework.cpp

[mlir][dataflow ] Drop LLVM_DEBUG of DATAFLOW_DEBUG (NFC) (#177398)

We kept the DATAFLOW_DEBUG macro because when
LLVM_ENABLE_ABI_BREAKING_CHECKS is 0, the debugName in AnalysisState is
not defined, which prevents us from printing debug logs(In this case, we
define DATAFLOW_DEBUG(X) as an empty macro, so it won't print any logs).
Therefore, this PR only removes LLVM_DEBUG. We are now using LDBG, so
LLVM_DEBUG is no longer needed.
https://github.com/llvm/llvm-project/pull/176911
DeltaFile
+1-1mlir/lib/Analysis/DataFlowFramework.cpp
+1-11 files

LLVM/project c113a14flang/test/Lower computed-goto.f90 c_ptr-constant-init.f90

[flang][NFC] Converted five tests from old lowering to new lowering (part 10) (#178357)

Tests converted from test/Lower: c_ptr-constant-init.f90,
complex-real.f90,
computed-goto.f90, constant-literal-mangling.f90, control-flow.f90

---------

Co-authored-by: Jean Perier <jperier at nvidia.com>
DeltaFile
+36-28flang/test/Lower/computed-goto.f90
+19-18flang/test/Lower/c_ptr-constant-init.f90
+6-6flang/test/Lower/complex-real.f90
+1-1flang/test/Lower/constant-literal-mangling.f90
+1-1flang/test/Lower/control-flow.f90
+63-545 files

LLVM/project 662acc2llvm/test/CodeGen/AArch64 fcvt_combine.ll

[AArch64][GlobalISel] Update testing for fixed point fcvt. NFC

This adds GlobalISel test coverage for fcvt_combine.ll and adds more variants
for testing.
DeltaFile
+1,420-248llvm/test/CodeGen/AArch64/fcvt_combine.ll
+1,420-2481 files

LLVM/project 3943134clang-tools-extra/clang-tidy/readability NonConstParameterCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix false positive in readability-non-const-parameter for dependent expression (#177345)

Closes #176623
DeltaFile
+22-0clang-tools-extra/test/clang-tidy/checkers/readability/non-const-parameter.cpp
+9-5clang-tools-extra/clang-tidy/readability/NonConstParameterCheck.cpp
+4-0clang-tools-extra/docs/ReleaseNotes.rst
+35-53 files

LLVM/project e72c4fcclang/lib/AST ExprConstant.cpp, clang/lib/AST/ByteCode InterpBuiltin.cpp

[clang][constexpr] Move inf/nan/denormal handling into FP binop callbacks (#178421)

Update the callback signature for `EvaluateFpBinOpExpr` and
`interp__builtin_elementwise_fp_binop` to return
`std::optional<APFloat>`, allowing individual callbacks to decide
whether to handle special floating-point cases (inf/nan/denormal).

Previously, the helper functions had hardcoded validation that forced
all callbacks to reject these cases. This blocked intrinsics needing
custom validation (e.g., rounding mode checks). Now each callback
controls its own validation and returns `std::nullopt` when the fold is
invalid.

Fixes #178416
DeltaFile
+15-7clang/lib/AST/ByteCode/InterpBuiltin.cpp
+15-7clang/lib/AST/ExprConstant.cpp
+30-142 files

FreeNAS/freenas b46c351src/middlewared/middlewared/utils mount.py

statx fix
DeltaFile
+1-1src/middlewared/middlewared/utils/mount.py
+1-11 files

LLVM/project 6869509clang/lib/StaticAnalyzer/Checkers/WebKit NoDeleteChecker.cpp, clang/test/Analysis/Checkers/WebKit nodelete-annotation.cpp

[alpha.webkit.NoDeleteChecker] Fix a nullptr deference crash during lookupInBases (#178351)

Added a null check in the lambda passed to lookupInBases.
DeltaFile
+12-0clang/test/Analysis/Checkers/WebKit/nodelete-annotation.cpp
+3-0clang/lib/StaticAnalyzer/Checkers/WebKit/NoDeleteChecker.cpp
+15-02 files

LLVM/project bcf3c2dllvm/lib/Target/AArch64 AArch64SystemOperands.td AArch64Features.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Allow some `tlbip` insns to be used with only +tlbid

Allow `tlbip` instructions containing *E1IS*, *E1OS*, *E2IS* or *E2OS*
to be used with `+tlbid` or `+d128`. This is because the 2025 Armv9.7-A
MemSys specification says:

```
All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions
that are currently dependent on FEAT_D128 are updated to be dependent
on FEAT_D128 or FEAT_TLBID
```
DeltaFile
+110-110llvm/test/MC/AArch64/armv9a-sysp.s
+21-0llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+14-3llvm/lib/Target/AArch64/AArch64SystemOperands.td
+12-4llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+7-4llvm/lib/Target/AArch64/AArch64Features.td
+10-0llvm/unittests/TargetParser/TargetParserTest.cpp
+174-1213 files not shown
+185-1279 files

FreeBSD/ports a8cce21security/vuxml/vuln 2026.xml

security/vuxml: Add firefox vulnerabilities

 * CVE-2026-24868
 * CVE-2026-24869
DeltaFile
+29-0security/vuxml/vuln/2026.xml
+29-01 files

LLVM/project ff7bfb9llvm/lib/Analysis StaticDataProfileInfo.cpp, llvm/lib/Transforms/Instrumentation MemProfUse.cpp

Move option from transforms to analysis pass
DeltaFile
+8-1llvm/lib/Analysis/StaticDataProfileInfo.cpp
+1-8llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
+9-92 files

LLVM/project fa3b3a0lldb/tools/lldb-dap DAP.cpp

[lldb-dap] Fix debugger initialisation order in DAP::InitializeDebugger (#178022)

Validate the debugger before assigning it to the member debugger to
avoid setting an invalid debugger on error.

We usually have an existing session with that debugger ends up messing
with that session.
DeltaFile
+6-4lldb/tools/lldb-dap/DAP.cpp
+6-41 files

LLVM/project 5d018e9llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

AMDGPU: Perform zero/any extend combine into permute (#177370)

Increases opportunities to generate permutes.
Motivated sub-optimal code generation of a CK kernel.
DeltaFile
+74,257-82,975llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+26,135-30,267llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,044-11,203llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+5,872-6,681llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+2,674-3,346llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,521-1,873llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+119,503-136,34514 files not shown
+122,472-140,14520 files

LLVM/project d7f177ellvm/lib/Target/AArch64 AArch64SystemOperands.td AArch64Features.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Allow some `tlbip` insns to be used with only +tlbid

Allow `tlbip` instructions containing *E1IS*, *E1OS*, *E2IS* or *E2OS*
to be used with `+tlbid` or `+d128`. This is because the 2025 Armv9.7-A
MemSys specification says:

```
All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions
that are currently dependent on FEAT_D128 are updated to be dependent
on FEAT_D128 or FEAT_TLBID
```
DeltaFile
+110-110llvm/test/MC/AArch64/armv9a-sysp.s
+22-7llvm/lib/Target/AArch64/AArch64SystemOperands.td
+21-0llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+12-4llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+7-4llvm/lib/Target/AArch64/AArch64Features.td
+6-4llvm/test/MC/AArch64/directive-arch_extension-negative.s
+178-1293 files not shown
+193-1319 files

NetBSD/pkgsrc YKhSsjsdoc CHANGES-2026

   doc: Updated pkgtools/pkgin to 26.1.0
VersionDeltaFile
1.713+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc YzTpD8tpkgtools/pkgin distinfo Makefile

   pkgin: Update to 26.1.0.

   ## Version 26.1.0 (2026-01-28)

    * Fix upgrade issue where the full list of affected packages was not
      calculated correctly when upgrading just the core package tools.
VersionDeltaFile
1.88+4-4pkgtools/pkgin/distinfo
1.144+2-3pkgtools/pkgin/Makefile
+6-72 files

HardenedBSD/ports 1884bfasysutils Makefile, sysutils/py-ansible-core220 Makefile pkg-descr

HBSD: Revert "sysutils/py-ansible-core220: Add new port"

This reverts commit 2b0cca695ede66c78626c5bc687a6f9798209691. This
commit by upstream FreeBSD breaks the build.

Signed-off-by: Shawn Webb <shawn.webb at hardenedbsd.org>
DeltaFile
+0-95sysutils/py-ansible-core220/Makefile
+0-9sysutils/py-ansible-core220/files/patch-pyproject.toml
+0-5sysutils/py-ansible-core220/pkg-descr
+0-3sysutils/py-ansible-core220/distinfo
+0-1sysutils/Makefile
+0-1135 files

LLVM/project c98cdd4llvm/lib/Target/SPIRV SPIRVEmitNonSemanticDI.cpp, llvm/test/CodeGen/SPIRV/debug-info crash-000.ll debug-inlinedAt-Declare.ll

[SPIRV] Fix crash due to incorrect state of the SPIRVGlobalRegistry.

Also, simplified checks in test that were not stricly necessary and were failing with this fix.
DeltaFile
+15-0llvm/test/CodeGen/SPIRV/debug-info/crash-000.ll
+0-11llvm/test/CodeGen/SPIRV/debug-info/debug-inlinedAt-Declare.ll
+2-0llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
+17-113 files

FreeNAS/freenas 672999csrc/middlewared/middlewared/migration 0018_resolve_dataset_paths.py, src/middlewared/middlewared/plugins rsync.py smb.py

use service classes
DeltaFile
+31-77src/middlewared/middlewared/migration/0018_resolve_dataset_paths.py
+7-7src/middlewared/middlewared/plugins/nvmet/namespace.py
+7-7src/middlewared/middlewared/plugins/iscsi_/extents.py
+4-3src/middlewared/middlewared/plugins/rsync.py
+4-3src/middlewared/middlewared/plugins/smb.py
+7-0src/middlewared/middlewared/service/base.py
+60-972 files not shown
+64-1018 files

Illumos/gate 0aba8a6usr/src/cmd/bhyve/common pci_virtio_viona.c, usr/src/man/man5 bhyve_config.5

17814 bhyve: support asymmetric viona queue sizes
Reviewed by: Robert Mustacchi <rm at fingolfin.org>
Reviewed by: Dan Cross <cross at oxidecomputer.com>
Approved by: Gordon Ross <gordon.w.ross at gmail.com>
DeltaFile
+62-12usr/src/cmd/bhyve/common/pci_virtio_viona.c
+18-3usr/src/man/man5/bhyve_config.5
+18-2usr/src/man/man8/bhyve.8
+98-173 files

LLVM/project 596a835mlir/test/Dialect/Arith expand-ops.mlir, mlir/test/Dialect/Tensor fold-into-pack-and-unpack.mlir

[MLIR] Fix typo "LABLE" in test checks (#178448)

DeltaFile
+1-1mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir
+1-1mlir/test/Dialect/Arith/expand-ops.mlir
+2-22 files

LLVM/project c3d4375lldb/source/Plugins/SymbolFile/NativePDB PdbAstBuilderClang.cpp SymbolFileNativePDB.cpp, lldb/test/Shell/SymbolFile/NativePDB invalid-inlinee-not-in-ipi.yaml lit.local.cfg

[lldb][NativePDB] Fix crash in debugger when PDB has bad type index value (#166455)

Fix crash when an inline site record in the PDB file contains type index
which is out of bounds
DeltaFile
+300-0lldb/test/Shell/SymbolFile/NativePDB/invalid-inlinee-not-in-ipi.yaml
+10-5llvm/lib/DebugInfo/CodeView/LazyRandomTypeCollection.cpp
+10-5lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilderClang.cpp
+9-5lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
+1-1llvm/include/llvm/DebugInfo/CodeView/LazyRandomTypeCollection.h
+1-0lldb/test/Shell/SymbolFile/NativePDB/lit.local.cfg
+331-166 files

LLVM/project 5413a22llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 disjoint-or-reductions.ll

[SLP] Reordered disjoint or reduction of shl(zext, (0, stride, 2* stride)) modelled as bitcast

Added support for reorder reduction of shl(zext)-like construct. Such
constructs are modelled currently as shuffle + bitcast.

Reviewers: RKSimon, hiraditya

Pull Request: https://github.com/llvm/llvm-project/pull/178292
DeltaFile
+62-18llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+8-12llvm/test/Transforms/SLPVectorizer/X86/disjoint-or-reductions.ll
+70-302 files