LLVM/project 43f6b06 — llvm/lib/Transforms/IPO AttributorAttributes.cpp, llvm/test/Transforms/Attributor cleanup-no-seeding.ll

[Attributor] Skip the dead-internal-function walk for AAs that will not be updated

AAIsDeadFunction::initialize calls isAssumedDeadInternalFunction, which
runs checkForAllCallSites and so creates an AAIsDead for every internal
caller, each of which repeats the walk. Initialization therefore recurses
through the whole cone of internal callers.

When the AA will not be updated (outside of deduction, or for a function
the Attributor is not run on), getOrCreateAAFor fixes it pessimistically
right after initialize returns, discarding the walk's result. Skip the
walk in that case and assume the entry block live.

This is the dominant cost of the CGSCC OpenMPOpt pass, whose cleanupIR
queries the liveness of callers outside the current SCC on every SCC,
giving (#SCCs) x (depth of the internal caller chain). #222226 removed
the callee-seeding half of this cost; this removes the walk itself.

cleanup-no-seeding.ll drops a debug check that only the removed walk
printed.

    [2 lines not shown]
DeltaFile
+6-1llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+0-1llvm/test/Transforms/Attributor/cleanup-no-seeding.ll
+6-22 files

FreeBSD/ports 8801f12 — security/wazuh-agent distinfo, security/wazuh-dashboard pkg-plist

security/wazuh-*: Update to 4.14.8

ChangeLog at:   https://documentation.wazuh.com/current/release-notes/release-4-14-8.html
DeltaFile
+59-668security/wazuh-manager/pkg-plist
+75-73security/wazuh-manager/distinfo
+39-39security/wazuh-agent/distinfo
+9-10security/wazuh-manager/Makefile
+9-9security/wazuh-server/distinfo
+11-3security/wazuh-dashboard/pkg-plist
+202-8026 files not shown
+216-81612 files

LLVM/project f408506 — clang/lib/CIR/CodeGen CIRGenFunction.cpp CIRGenExprAggregate.cpp, clang/test/CIR/CodeGen pack-indexing.cpp

[CIR] Support PackIndexingExpr for LValue and Aggregates (#227040)

Support `PackIndexingExpr` in `CIRGenFunction::emitLValue` and
`AggExprEmitter` by visiting its selected expression, matching classic
Clang codegen (`CGExpr.cpp` and `CGExprAgg.cpp`) and completing
`PackIndexingExpr` support across all CIR expression emitters.

Fixes #226928

Assisted by Antigravity and Gemini
DeltaFile
+90-0clang/test/CIR/CodeGen/pack-indexing.cpp
+1-3clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+4-0clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
+95-33 files

FreeBSD/ports 7a466b6 — textproc/opensearch-dashboards219 Makefile distinfo

textproc/opensearch-dashboards219: Update to 2.19.6

With hat:       opensearch
DeltaFile
+5-5textproc/opensearch-dashboards219/distinfo
+1-2textproc/opensearch-dashboards219/Makefile
+6-72 files

FreeBSD/ports da73534 — textproc/opensearch219 Makefile distinfo

textproc/opensearch219: Update to 2.19.6

With hat:       opensearch
DeltaFile
+5-5textproc/opensearch219/distinfo
+1-1textproc/opensearch219/Makefile
+6-62 files

LLVM/project 15faa0a — llvm/lib/Transforms/IPO SampleProfileMatcher.cpp, llvm/test/Transforms/SampleProfile pseudo-probe-stale-profile-direct-basename-uniq.ll pseudo-probe-stale-profile-direct-basename-suffix.ll

[SampleProfileMatcher] Fix direct basename matching for suffixed function names

Direct basename matching (#184409) silently skips any function whose name
carries a suffix, for two reasons:

1. `getDemangledBaseName` demangles the raw name. For names such as
   `_ZL3fool.__uniq.123`, `_Z3fool.llvm.7`, `.part.N` or `.cfi` the Itanium
   demangler's root node is a DotSuffix, for which `getFunctionBaseName()`
   returns null, so the function is never a candidate on either the IR or
   the profile side.
2. `UpdateWithSalvagedProfiles` keys `FuncNameToProfNameMap` by the raw IR
   name, but `SampleProfileReader::getSamplesFor(const Function &)` looks it
   up by `getCanonicalFnName`. A salvaged `.llvm.N` (ThinLTO-promoted),
   `.part.N` or `.cfi` function therefore still gets no profile.

Canonicalize the name before demangling (additionally dropping `.__uniq.N`,
which `getCanonicalFnName` keeps when the profile has uniq names), and key
the map by the canonical name. Other suffixes such as coroutine `.resume`
are kept so those clones do not make a basename ambiguous.

    [12 lines not shown]
DeltaFile
+101-0llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-direct-basename-suffix.ll
+68-0llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-direct-basename-uniq.ll
+12-2llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
+12-0llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-stale-profile-direct-basename-suffix.prof
+6-0llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-stale-profile-direct-basename-uniq.prof
+199-25 files

LLVM/project fddfd6f — clang/lib/AST ExprConstant.cpp, clang/lib/AST/ByteCode InterpState.h InterpState.cpp

[clang][bytecode] Add `EvalSettings` struct and replace parent `State` (#226175)

We currently always construct a full `EvalInfo` when using the bytecode
interpreter, we then pass it to the `evaluate*` function, which only
copies a few values from it.

Introduce a new `EvalSettings` struct that we pass instead of a `State`.
This is cheaper to construct and we only pass what's needed. There is
one `evaluateAsRValue` overload left that takes a parent `State`, that
will be removed in a subsequent patch.
DeltaFile
+88-58clang/lib/AST/ExprConstant.cpp
+75-39clang/lib/AST/ByteCode/Context.cpp
+25-16clang/lib/AST/ByteCode/Context.h
+35-0clang/lib/AST/ByteCode/EvalSettings.h
+23-9clang/lib/AST/ByteCode/InterpState.cpp
+5-1clang/lib/AST/ByteCode/InterpState.h
+251-1232 files not shown
+259-1238 files

LLVM/project 25e66e4 — llvm/lib/CodeGen SpillPlacement.cpp, llvm/test/CodeGen/AMDGPU wave-profile-spill-zero-cost.mir wave-profile-spill.mir

[CodeGen] Enable validated AMDGPU wave spill costs by default

Use available validated wave counts for AMDGPU spill placement without an
explicit opt-in. Keep the existing target, mapping and normalization checks
and the ordinary block-frequency fallback for unavailable or rejected data.

Retain -enable-wave-profiled-spill=false for debugging and matched performance
comparisons. Test default behavior, explicit disabling, equivalence to explicit
enabling, fallback cases and the positive frequency floor.
DeltaFile
+14-11llvm/test/CodeGen/AMDGPU/wave-profile-spill.mir
+1-1llvm/test/CodeGen/AMDGPU/wave-profile-spill-zero-cost.mir
+1-1llvm/lib/CodeGen/SpillPlacement.cpp
+16-133 files

LLVM/project 623ddd9 — llvm/lib/CodeGen SpillPlacement.cpp, llvm/test/CodeGen/AMDGPU wave-profile-spill-zero-cost.mir

[CodeGen] Keep wave-profiled spill frequencies positive

SpillPlacement expects positive block weights, but a valid wave profile can
record zero executions for a CFG-reachable block. Giving such a block zero
spill cost can make the allocator choose a very different placement.

Clamp every accepted wave-derived frequency to at least one, as we already
do for nonzero counts that round down to zero. Unmeasured or rejected blocks
still use their existing MBFI frequency. Add a focused MIR test for a valid
zero-wave record.

This pattern arose in a profiled Composable Kernel convolution case. With
the separate spill correctness fixes and partial spilling enabled, the
zero-cost policy failed two CPU-reference checks; the positive floor passed
both. The test checks the cost directly; the application result was checked
separately on gfx950.

DeltaFile
+27-0llvm/test/CodeGen/AMDGPU/wave-profile-spill-zero-cost.mir
+3-2llvm/lib/CodeGen/SpillPlacement.cpp
+30-22 files

LLVM/project a1b347c — llvm/lib/CodeGen SpillPlacement.cpp, llvm/test/CodeGen/AMDGPU wave-profile-spill.mir

[CodeGen] Use validated wave counts for AMDGPU spill costs

Lane-based block frequencies can understate the cost of a spill in
divergent GPU code: a wave still executes a block with only some lanes
active. Use measured block-wave counts to weight SpillPlacement's costs
relative to the original entry-wave count.

Opt in on AMDGPU only. Accept a measured count only when its IR block
maps uniquely to a machine block with matching predecessors and
successors. Keep the existing MBFI cost for unmeasured or rejected
blocks, and leave branch probabilities and general BFI unchanged.



DeltaFile
+251-0llvm/test/CodeGen/AMDGPU/wave-profile-spill.mir
+97-1llvm/lib/CodeGen/SpillPlacement.cpp
+348-12 files

LLVM/project 8ed3cf6 — llvm/lib/Transforms/Utils LowerSwitch.cpp, llvm/test/Transforms/LowerSwitch wave-profile.ll profile-weights.ll

[Transforms] Preserve wave profiles across CFG rewrites

HIP device PGO attaches measured wave counts to IR blocks. Later CFG
rewrites can drop counts from unchanged blocks or leave stale counts
on blocks that now execute differently. Either case makes the profile
unreliable for later optimizations.

Preserve counts through switch lowering, structurization, and loop
rotation only when a block still represents the same executions. Keep
unaffected counts and their IDs even when a loop header's count must be
invalidated. Transfer branch hints only for equivalent decisions, and
avoid assigning switch weights when default traffic cannot be traced
to one edge.




DeltaFile
+157-0llvm/test/Transforms/LowerSwitch/profile-weights.ll
+113-10llvm/lib/Transforms/Utils/LowerSwitch.cpp
+68-0llvm/unittests/Transforms/Utils/LoopRotationUtilsTest.cpp
+56-0llvm/test/Transforms/LowerSwitch/wave-profile.ll
+53-0llvm/test/Transforms/StructurizeCFG/wave-profile-loop-prefix.ll
+50-0llvm/test/Transforms/StructurizeCFG/wave-profile.ll
+497-108 files not shown
+629-5114 files

LLVM/project 5331865 — llvm/lib/Transforms/Instrumentation PGOInstrumentation.cpp, llvm/test/Transforms/PGOProfile dense-wave-cfg.ll wave-profile-use.ll

[PGO] Load dense block wave counts from device profiles

Use the profile's dense layout flag to map appended wave-only slots after
the original block/select prefix. Reuse the producer's block selection so
eligible loop and reconvergence blocks retain their directly measured wave
frequencies. Keep select slots out of the block mapping.

Test dense and sparse profiles, measured zeros, generation and metadata
switches, and exact loop block identities after critical-edge splitting.
DeltaFile
+49-3llvm/test/Transforms/PGOProfile/wave-profile-use.ll
+15-1llvm/test/Transforms/PGOProfile/dense-wave-cfg.ll
+11-4llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
+75-83 files

LLVM/project 569cd7b — llvm/lib/Transforms/Instrumentation PGOInstrumentation.cpp, llvm/test/Transforms/PGOProfile wave-profile-use.ll

[PGO] Add a debugging switch for wave profile metadata

Add the hidden pgo-wave-metadata option, enabled by default, for debugging,
performance comparisons and disabling wave annotations when investigating
regressions without turning off ordinary PGO or uniformity hints.

Gate wave metadata emission while retaining the existing clearing of stale
function and block annotations during profile use. Profile collection and
ordinary count reconstruction are unchanged.

Test default/explicit enablement, disabling, retained counts and uniformity
hints, and replacement profiles with missing, mismatched or zero counts.

DeltaFile
+34-1llvm/test/Transforms/PGOProfile/wave-profile-use.ll
+6-1llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
+40-22 files

LLVM/project 654b615 — llvm/lib/Transforms/Instrumentation PGOInstrumentation.cpp, llvm/test/Transforms/PGOProfile wave-profile-use.ll

[PGO] Load GPU wave counts into IR metadata

GPU profiles contain wave counts alongside lane counts, but profile use
does not expose them to optimizations. Wave visits do not obey scalar
flow conservation, so unmeasured blocks cannot use counts reconstructed
from neighboring blocks or ordinary branch weights.

Map wave-counter indices to the blocks selected by PGO instrumentation,
after reproducing its critical-edge splits. Attach measured counts using
wave.profile metadata, retaining measured zeros and marking other blocks
unmeasured. Require a measured entry count for normalization and exclude
select-counter slots from the block mapping.

Validate the wave-counter layout against the accepted lane profile.
Clear old wave metadata when loading a replacement profile, including
when a function has no usable record. Do not emit wave metadata for
previously profiled functions: their branch weights may change counter
placement without changing the CFG hash. Keep ordinary lane-count
reconstruction and branch weights unchanged.

DeltaFile
+212-0llvm/test/Transforms/PGOProfile/wave-profile-use.ll
+44-0llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
+256-02 files

LLVM/project eff00c4 — llvm/docs LangRef.md, llvm/include/llvm/IR ProfDataUtils.h

[IR] Define GPU wave-profile metadata

Existing offload GPU profile counters measure lane executions, while
GPU instructions execute at wave granularity under an active-lane
mask. A block visited by every wave can therefore look cold when only
a few lanes are active. Scalar branch weights also cannot represent a
divergent wave visiting both successors before reconverging. These
profiles are a poor fit for optimizations that estimate work performed
by a wave.

Lane counters remain useful for measuring per-lane branch selectivity
and estimating work that scales with the number of active lanes.
Wave counters cannot replace them: a visit with one active lane and a
visit with all lanes active both count as one. The two profiles provide
complementary information about instruction execution and lane activity.

Introduce wave.profile and wave.profile.block metadata to represent
measured wave visits to IR blocks. Each dynamic visit with at least one
active lane contributes one to the count. A measured zero is distinct

    [18 lines not shown]
DeltaFile
+817-0llvm/unittests/IR/ProfDataUtilsTest.cpp
+396-0llvm/lib/IR/ProfDataUtils.cpp
+91-0llvm/test/Verifier/wave-profile.ll
+74-0llvm/include/llvm/IR/ProfDataUtils.h
+47-0llvm/docs/LangRef.md
+40-0llvm/test/Bitcode/wave-profile.ll
+1,465-05 files not shown
+1,525-011 files

LLVM/project 4cc5c32 — compiler-rt/include/profile InstrProfData.inc

[Profile] Synchronize the dense-wave profile header in compiler-rt

Keep the compiler-rt copy of InstrProfData.inc in sync with LLVM's
copy by adding the dense-wave variant bit and matching comments.
This fixes the shared-header consistency failure in profile CI.

CI failure: https://github.com/llvm/llvm-project/actions/runs/36506166214/job/109207990906
DeltaFile
+3-1compiler-rt/include/profile/InstrProfData.inc
+3-11 files

LLVM/project 2f13592 — mlir/include/mlir/Dialect/ControlFlow/IR ControlFlowOps.td, mlir/lib/Dialect/ControlFlow/IR ControlFlowOps.cpp

[mlir][cf] Fix cf.switch round-trip for case values wider than 64 bits (#221490)

The `cf.switch` parser reads case values into `int64_t`, and its printer
uses `APInt::getLimitedValue()`, preventing values wider than 64 bits
from round-tripping. Printing negative narrow values as unsigned can
also trigger an assertion when reparsing.

Parse case values into `APInt` and print them directly, so wide and
negative values round-trip correctly. Accept signed or unsigned literals
that fit the switch operand’s bit width, and report an error for values
that do not.

Add regression tests for wide and negative values, integer-width
boundaries, out-of-range diagnostics, and case selection after parsing.

Fixes #220609

Assisted-by: Codex
DeltaFile
+66-0mlir/test/Dialect/ControlFlow/invalid.mlir
+56-0mlir/test/Dialect/ControlFlow/ops.mlir
+28-0mlir/test/Dialect/ControlFlow/canonicalize.mlir
+8-3mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
+1-1mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
+159-45 files

LLVM/project eb3163c — utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Builder BUILD.bazel

[Bazel] Fixes ec1b3b1 (#227180)

This fixes ec1b3b10a71c2181b0dfb90f1178e2e739680e02 (#227089).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=ec1b3b10a71c2181b0dfb90f1178e2e739680e02

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Builder/BUILD.bazel
+1-01 files

LLVM/project 9ef45b1 — clang CMakeLists.txt, clang/cmake/modules ClangConfig.cmake.in CMakeLists.txt

fixup! [CMake] Link MLIR if CLANG_ENABLE_CIR
DeltaFile
+0-32clang/cmake/modules/CMakeLists.txt
+12-8clang/CMakeLists.txt
+9-3llvm/cmake/modules/AddLLVM.cmake
+0-2clang/cmake/modules/ClangConfig.cmake.in
+21-454 files

HardenedBSD/ports af6e19e — devel/pcre2 Makefile

HBSD: Disable JIT in devel/pcre2

PCRE2 JIT has long been a source of frustration on HardenedBSD because
of our PaX NOEXEC implementation. Now that the PCRE2 JIT implementation
has had a recent security advisory (a buffer overflow, nonetheless), we
probably should not trust PCRE2's JIT.

Signed-off-by:  Shawn Webb <shawn.webb at hardenedbsd.org>
See-Also:       GHSA-r9hj-j2rw-4q3m
DeltaFile
+1-4devel/pcre2/Makefile
+1-41 files

LLVM/project ec1b3b1 — flang/lib/Optimizer/Builder CUDAIntrinsicCall.cpp, flang/lib/Optimizer/Transforms/CUDA CUFOpConversion.cpp CUFFunctionRewrite.cpp

[flang][cuda] Add cuf.on_device op and lower to it (#227089)

Replace the CUFFunctionRewrite pass, which matched fir.call names and
folded them to constants, with a cuf.on_device operation emitted when
the intrinsic is lowered. CUFOpConversion folds the operation once the
code is in its host or device context, and leaves the host copy of an
OpenACC routine unfolded so the device clone is not baked to false. Any
operation that remains is folded by the late CUF conversion, and the
rewrite pass is dropped from the pipeline.
DeltaFile
+0-241flang/test/Fir/CUDA/cuda-function-rewrite.mlir
+0-133flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
+110-0flang/test/Fir/CUDA/cuda-on-device.mlir
+32-7flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
+34-0flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
+23-0flang/test/Lower/CUDA/cuda-on-device.cuf
+199-3818 files not shown
+276-40014 files

LLVM/project 3b0b6d8 — clang/lib/CodeGen BackendConsumer.h CodeGenAction.cpp, clang/lib/Interpreter Interpreter.cpp DeviceOffload.h

Revert "releand "[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation"" (#227123)

Reverts llvm/llvm-project#226930

AMD author has an additional step to perform, that is still needed.
in contact with Author.
DeltaFile
+8-209clang/lib/Interpreter/DeviceOffload.cpp
+9-55clang/lib/Interpreter/DeviceOffload.h
+0-50clang/unittests/Basic/TargetIDTest.cpp
+0-9clang/lib/CodeGen/CodeGenAction.cpp
+0-8clang/lib/CodeGen/BackendConsumer.h
+6-1clang/lib/Interpreter/Interpreter.cpp
+23-3324 files not shown
+25-34210 files

LLVM/project dae88f2 — clang/lib/CIR/CodeGen CIRGenExprAggregate.cpp CIRGenCoroutine.cpp, clang/test/CIR/CodeGenCoroutines coro-agg.cpp

[CIR] Support aggregate co_await / co_yield in AggExprEmitter (#225412)

Support evaluating `co_await` and `co_yield` expressions whose result is
an aggregate type in `AggExprEmitter`.

Fixes #225317
DeltaFile
+101-0clang/test/CIR/CodeGenCoroutines/coro-agg.cpp
+12-19clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
+3-5clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
+116-243 files

LLVM/project 60ac629 — llvm/lib/Transforms/Scalar TailRecursionElimination.cpp, llvm/test/Transforms/TailCallElim return-value-select-pgo.ll

[TailCallElim] Add profile annotations to return value selects

Tail call elimination in some cases can create selects on possible
return values conditioned on whether or not execution is currently in
what was a recursive call. That is equal to the probability with which
we recurse, which in turn can be computed from the block frequencies of
blocks that recurse and blocks that directly return.

Reviewers: mtrofin

Reviewed By: mtrofin

Pull Request: https://github.com/llvm/llvm-project/pull/202518
DeltaFile
+121-0llvm/test/Transforms/TailCallElim/return-value-select-pgo.ll
+29-0llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
+0-7llvm/utils/profcheck-xfail.txt
+150-73 files

LLVM/project 62e8956 — libc/test/src/math/exhaustive cos.wc sin.wc, llvm/lib/Support UnicodeNameToCodepointGenerated.cpp

feedback

Created using spr 1.3.7
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+82,648-81,221llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+31,001-87,165llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+40,941-24,498llvm/test/CodeGen/RISCV/clmul.ll
+24,053-23,916llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+2,359,906-216,80049,344 files not shown
+6,170,671-2,241,57949,350 files

LLVM/project 5e07950 — libc/test/src/math/exhaustive cos.wc sin.wc, llvm/lib/Support UnicodeNameToCodepointGenerated.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+82,648-81,221llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+31,001-87,165llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+40,941-24,498llvm/test/CodeGen/RISCV/clmul.ll
+24,053-23,916llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+2,359,906-216,80049,343 files not shown
+6,170,666-2,241,56949,349 files

LLVM/project efea234 — llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mul.i24.ll rotl.ll

[SelectionDAG] Handle constants in SimplifyMultipleUseDemandedBits

Replace a non-zero constant with zero when none of its set bits are
demanded.

This allows users of `SimplifyMultipleUseDemandedBits` to eliminate
irrelevant constant bits while preserving the convention that a null
SDValue indicates no simplification.
DeltaFile
+38-45llvm/test/CodeGen/AMDGPU/rotl.ll
+3-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+3-4llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll
+2-4llvm/test/CodeGen/SystemZ/shift-08.ll
+2-4llvm/test/CodeGen/SystemZ/shift-04.ll
+6-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+54-634 files not shown
+58-7110 files

LLVM/project 17cfb00 — llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mul.i24.ll

Check one user
DeltaFile
+44-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+2-2llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+46-22 files

LLVM/project 31d7b51 — clang/docs ReleaseNotes.md, clang/test/AST/ByteCode new-delete.cpp

[Clang] Add missing release note entry in #226753 (#227078)

As per the feedback from #226753, we add release note for GH-212211.
Also move the test to new-delete.cpp.

Assisted-by: Claude
DeltaFile
+0-29clang/test/SemaCXX/new-nothrow-by-value.cpp
+17-0clang/test/AST/ByteCode/new-delete.cpp
+5-0clang/docs/ReleaseNotes.md
+22-293 files

LLVM/project 2fc9681 — llvm/lib/CodeGen SpillPlacement.cpp, llvm/test/CodeGen/AMDGPU wave-profile-spill-zero-cost.mir wave-profile-spill.mir

[CodeGen] Enable validated AMDGPU wave spill costs by default

Use available validated wave counts for AMDGPU spill placement without an
explicit opt-in. Keep the existing target, mapping and normalization checks
and the ordinary block-frequency fallback for unavailable or rejected data.

Retain -enable-wave-profiled-spill=false for debugging and matched performance
comparisons. Test default behavior, explicit disabling, equivalence to explicit
enabling, fallback cases and the positive frequency floor.
DeltaFile
+14-11llvm/test/CodeGen/AMDGPU/wave-profile-spill.mir
+1-1llvm/test/CodeGen/AMDGPU/wave-profile-spill-zero-cost.mir
+1-1llvm/lib/CodeGen/SpillPlacement.cpp
+16-133 files