FreeBSD/ports 9fe8f80sysutils/hyprpolkitagent distinfo Makefile

sysutils/hyprpolkitagent: Update to 0.2.0

Changelog: https://github.com/hyprwm/hyprpolkitagent/releases/tag/v0.2.0

Reported by:    GitHub (watch releases)
DeltaFile
+12-9sysutils/hyprpolkitagent/Makefile
+3-3sysutils/hyprpolkitagent/distinfo
+15-122 files

LLVM/project 7ebc816llvm/include/llvm/CodeGen LiveRegMatrix.h, llvm/lib/CodeGen LiveRegMatrix.cpp

Rather than constructing a temporary "hull" LiveInterval and calling the
LiveInterval-based checkInterference overload -- which risks a query-cache
identity hazard when that temporary interval is stack-allocated and reused
across the AllocOrder loop (see the FIXME comment in
LiveRegMatrix::checkInterference(SlotIndex, SlotIndex, MCRegister)) -- this
patch switches the unspilling code to call the slot-index-based
checkInterference(SlotIndex, SlotIndex, MCRegister) overload directly with
the hull's [beginIndex, endIndex).

Doing so exposed a real bug in that overload: LiveRegMatrix.h documents
that returning false means "PhysReg is free at [Start, End)", but the
implementation only checked the matrix of already-assigned virtual
registers. It never checked fixed register-unit interference (e.g. PhysReg
is defined directly by some instruction in [Start, End)) or regmask
interference (e.g. PhysReg is clobbered by a call in [Start, End)) -- both
of which the LiveInterval-based overload does check. This patch adds both
checks to the slot-index-based overload, in the same priority order
(regmask -> regunit -> matrix) as the LiveInterval-based one, bringing the
two implementations in line.

    [27 lines not shown]
DeltaFile
+33-1llvm/lib/CodeGen/LiveRegMatrix.cpp
+22-4llvm/include/llvm/CodeGen/LiveRegMatrix.h
+55-52 files

LLVM/project 2a01771llvm/test/CodeGen/LoongArch memory-barrier-opt.ll

[LoongArch][NFC] Add tests for memory barrier optimization (#218596)
DeltaFile
+711-0llvm/test/CodeGen/LoongArch/memory-barrier-opt.ll
+711-01 files

LLVM/project c9a1fc8llvm/lib/Target/LoongArch LoongArch.h LoongArchTargetMachine.cpp, llvm/test/CodeGen/LoongArch opt-pipeline.ll memory-barrier-opt.ll

[LoongArch] Add memory barrier optimization pass (#218597)

Add a machine-level pass to remove redundant DBARs and merge them with
atomic memory operations. The pass uses machine dominator and
post-dominator trees to ensure the transformation is safe across basic
blocks.
DeltaFile
+976-205llvm/test/CodeGen/LoongArch/memory-barrier-opt.ll
+559-0llvm/lib/Target/LoongArch/LoongArchMemoryBarrierOpt.cpp
+3-0llvm/test/CodeGen/LoongArch/opt-pipeline.ll
+3-0llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+2-0llvm/lib/Target/LoongArch/LoongArch.h
+1-0llvm/utils/gn/secondary/llvm/lib/Target/LoongArch/BUILD.gn
+1,544-2051 files not shown
+1,545-2057 files

LLVM/project be09c15orc-rt/include/orc-rt-c/support Compiler.h

[orc-rt] Add a maybe-unused attribute macro. (#222834)

This will be used in upcoming commits to suppress unused function
warnings.
DeltaFile
+10-0orc-rt/include/orc-rt-c/support/Compiler.h
+10-01 files

LLVM/project a929f4aflang/lib/Optimizer/OpenMP MapInfoFinalization.cpp, flang/lib/Utils OpenMP.cpp

[Flang][OpenMP] Remove target implicit allocatable member mapping from MapInfoFinalization and extend lowering to support it (#219434)

This PR aims to remove the partially implemented implicit allocatable
member mapping code from MapInfoFinalization, and move it to the
lowering.

The MapInfoFinalization code should no longer be required as the
DeclareMapper infrastructure in the frontend is capable of handling
these cases now and already does so for the majority of them, so we are
better consolidating the implementation to one location and extending it
to support more cases.

This PR removes the old code from MapInfoFinalization, and enables the
default declare mapper generation that handles most other implicit
mapping cases for derived types in the initial lowering to handle the
previously supported cases and more.

The implicit default declare mapper generation has been modified to only
map the necessary bits of a derived type, which are record types (to

    [2 lines not shown]
DeltaFile
+0-191flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
+0-92flang/test/Transforms/omp-map-info-finalization-implicit-field.fir
+12-51flang/test/Lower/OpenMP/declare-mapper.f90
+21-24flang/test/Lower/OpenMP/implicit-mapper-no-pointer-map.f90
+21-24flang/test/Lower/OpenMP/default-mapper-no-pointer-map.f90
+21-15flang/lib/Utils/OpenMP.cpp
+75-39712 files not shown
+161-44418 files

FreeNAS/freenas 79d40fasrc/middlewared/middlewared/plugins disk.py, src/middlewared/middlewared/plugins/pool_ attach_disk.py replace_disk.py

Enforce the SED entitlement on pool and password paths

This commit adds changes to actually enforce the SED rule, which until now was checked almost nowhere — creating a pool with the all_sed flag had no entitlement check at all. Pool create, update, attach and replace now go through a shared validate_sed_license, and setting a global or per-disk SED password is gated too, though clearing one always works so a system that lost the entitlement can still drop a secret it is no longer allowed to use.

Unlock is deliberately left ungated. A license daemon that errors with anything other than "no license" reads as unlicensed, so gating unlock would turn a daemon hiccup into a failed pool import at boot and a failed unlock on an HA master transition. The drives are already provisioned by that point, so unlocking them grants nothing new. What this enforces is no new SED usage, rather than no SED usage at all.
DeltaFile
+16-1src/middlewared/middlewared/plugins/system_advanced/config.py
+12-0src/middlewared/middlewared/plugins/pool_/utils.py
+10-1src/middlewared/middlewared/plugins/disk.py
+6-0src/middlewared/middlewared/plugins/pool_/pool.py
+4-1src/middlewared/middlewared/plugins/pool_/attach_disk.py
+5-0src/middlewared/middlewared/plugins/pool_/replace_disk.py
+53-31 files not shown
+57-37 files

FreeNAS/freenas 2e77cc6src/middlewared/middlewared/pytest/unit/utils test_license_info_wire.py test_license_legacy_utils.py, src/middlewared/middlewared/utils/entitlements matrix.py

Require a SED feature key on TrueNAS hardware

This commit adds changes to narrow the SED entitlement so it only resolves on TrueNAS hardware carrying a license with the SED feature key, and to inject that key into legacy licenses so the existing installed base keeps working. Both halves have to land together: narrowing the vector on its own would deny every legacy licensee whose bitmask never carried the SED bit, and their pools would stop unlocking on upgrade. The injection is unconditional because the hardware conjunct lives in the vector, not in the license parser, which stays a pure function of the blob it is handed. This supersedes the earlier decision that allowed the keyless grants.
DeltaFile
+3-10src/middlewared/middlewared/pytest/unit/utils/test_entitlements.py
+6-4src/middlewared/middlewared/pytest/unit/utils/test_license_legacy_utils.py
+1-1src/middlewared/middlewared/utils/entitlements/matrix.py
+1-0src/middlewared/middlewared/utils/license/legacy.py
+1-0src/middlewared/middlewared/pytest/unit/utils/test_license_info_wire.py
+12-155 files

FreeBSD/ports 8f47e33multimedia/hyprpwcenter Makefile, x11/hyprland-guiutils Makefile

*/*: Bump port revision after hyprtoolkit shlib version bump (0685b1a33713)
DeltaFile
+1-1x11/hyprshutdown/Makefile
+1-1x11/hyprpaper/Makefile
+1-1x11/hyprlauncher/Makefile
+1-1multimedia/hyprpwcenter/Makefile
+1-0x11/hyprland-guiutils/Makefile
+5-45 files

FreeNAS/freenas af01971src/middlewared/middlewared/plugins disk.py, src/middlewared/middlewared/plugins/pool_ attach_disk.py replace_disk.py

Enforce the SED entitlement on pool and password paths

This commit adds changes to actually enforce the SED rule, which until now was checked almost nowhere — creating a pool with the all_sed flag had no entitlement check at all. Pool create, update, attach and replace now go through a shared validate_sed_license, and setting a global or per-disk SED password is gated too, though clearing one always works so a system that lost the entitlement can still drop a secret it is no longer allowed to use.

Unlock is deliberately left ungated. A license daemon that errors with anything other than "no license" reads as unlicensed, so gating unlock would turn a daemon hiccup into a failed pool import at boot and a failed unlock on an HA master transition. The drives are already provisioned by that point, so unlocking them grants nothing new. What this enforces is no new SED usage, rather than no SED usage at all.
DeltaFile
+16-1src/middlewared/middlewared/plugins/system_advanced/config.py
+12-0src/middlewared/middlewared/plugins/pool_/utils.py
+10-1src/middlewared/middlewared/plugins/disk.py
+6-0src/middlewared/middlewared/plugins/pool_/pool.py
+4-1src/middlewared/middlewared/plugins/pool_/attach_disk.py
+5-0src/middlewared/middlewared/plugins/pool_/replace_disk.py
+53-31 files not shown
+57-37 files

FreeNAS/freenas 1a5bb44src/middlewared/middlewared/pytest/unit/utils test_license_info_wire.py test_license_legacy_utils.py, src/middlewared/middlewared/utils/entitlements matrix.py

Require a SED feature key on TrueNAS hardware

This commit adds changes to narrow the SED entitlement so it only resolves on TrueNAS hardware carrying a license with the SED feature key, and to inject that key into legacy licenses so the existing installed base keeps working. Both halves have to land together: narrowing the vector on its own would deny every legacy licensee whose bitmask never carried the SED bit, and their pools would stop unlocking on upgrade. The injection is unconditional because the hardware conjunct lives in the vector, not in the license parser, which stays a pure function of the blob it is handed. This supersedes the earlier decision that allowed the keyless grants.
DeltaFile
+3-10src/middlewared/middlewared/pytest/unit/utils/test_entitlements.py
+6-4src/middlewared/middlewared/pytest/unit/utils/test_license_legacy_utils.py
+1-1src/middlewared/middlewared/utils/entitlements/matrix.py
+1-0src/middlewared/middlewared/utils/license/legacy.py
+1-0src/middlewared/middlewared/pytest/unit/utils/test_license_info_wire.py
+12-155 files

FreeBSD/ports 0685b1ax11-toolkits/hyprtoolkit distinfo pkg-plist, x11-toolkits/hyprtoolkit/files patch-src_palette_ConfigManager.cpp

x11-toolkits/hyprtoolkit: Update to 0.6.0

While here, remove upstreamd patch.

Changelog: https://github.com/hyprwm/hyprtoolkit/releases/tag/v0.6.0

Reported by:    GitHub (watch releases)
DeltaFile
+0-14x11-toolkits/hyprtoolkit/files/patch-src_palette_ConfigManager.cpp
+4-4x11-toolkits/hyprtoolkit/Makefile
+7-0x11-toolkits/hyprtoolkit/pkg-plist
+3-3x11-toolkits/hyprtoolkit/distinfo
+14-214 files

LLVM/project 2a26ae8llvm/include/llvm/Object OffloadBinary.h, llvm/lib/Object OffloadBinary.cpp

comments
DeltaFile
+14-15llvm/include/llvm/Object/OffloadBinary.h
+18-0llvm/test/ObjectYAML/Offload/malformed-compressed-offset.yaml
+5-9llvm/lib/Object/OffloadBinary.cpp
+3-1llvm/unittests/Object/OffloadingTest.cpp
+4-0llvm/test/tools/llvm-offload-binary/compress.test
+2-1llvm/tools/obj2yaml/offload2yaml.cpp
+46-261 files not shown
+47-277 files

FreeBSD/ports e8bea65net/py-bonsai Makefile

net/py-bonsai: convert OpenLDAP dependency to USES=ldap

Replace hardcoded openldap26-client dependency with USES=ldap,
letting the framework handle version selection.

PR:             ports/297391
Approved by:    maintainer timeout
DeltaFile
+2-5net/py-bonsai/Makefile
+2-51 files

LLVM/project 980c9bbclang/test/CodeGen/RISCV builtin-cpu-is.c, clang/test/Driver riscv-cpus.c

[RISCV] Remove VeyronV1 processor definition (#220623)

Processor no longer exists.
DeltaFile
+0-39llvm/lib/Target/RISCV/RISCVProcessors.td
+0-25clang/test/Driver/riscv-cpus.c
+1-19clang/test/CodeGen/RISCV/builtin-cpu-is.c
+0-4llvm/lib/Target/RISCV/RISCVFeatures.td
+0-2clang/test/Misc/target-invalid-cpu-note/riscv.c
+0-1llvm/test/CodeGen/RISCV/features-info.ll
+1-902 files not shown
+2-918 files

LLVM/project db70744llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-mul-parts-acc-fold.ll

[RISCV][P-ext] Fold an add of a multiply-parts product into the accumulate form (#222748)

An add of a multiply-parts product selects the accumulating instruction, so
that a loop written with `sum += __riscv_mul_h00_i32(a, b)` gets `macc.h00`
rather than a separate multiply and add.

Rewriting the add before type legalization keeps the shapes whose result is
illegal, so the existing accumulate lowering covers all of them.
DeltaFile
+429-0llvm/test/CodeGen/RISCV/rvp-mul-parts-acc-fold.ll
+67-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+496-02 files

LLVM/project 4267061llvm/lib/Target/AMDGPU AMDGPUUniformIntrinsicCombine.cpp, llvm/test/CodeGen/AMDGPU amdgpu-uniform-intrinsic-combine-analysis-invalidation.ll

[AMDGPU] Invalidate uniformity info after intrinsic combine (#222357)

The uniform intrinsic combine pass changed IR while preserving
uniformity information. Its result keeps references to cycle
information. Those references could be invalidated and later accessed
by another pass.

Invalidate uniformity information after a change. Before erasing an
instruction, remove it from the analysis state used by the pass. Also
report each erasure as a change so invalidation always runs.
DeltaFile
+108-0llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-combine-analysis-invalidation.ll
+11-7llvm/lib/Target/AMDGPU/AMDGPUUniformIntrinsicCombine.cpp
+119-72 files

LLVM/project 5f00f13llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Support KnownFPClass.cpp

[KnownFPClass] Refactor direct access to KnownFPClasses [NFC] (#220315)

Part of https://github.com/llvm/llvm-project/issues/217072

Follow up to https://github.com/llvm/llvm-project/pull/218514

Replaces direct uses of the `KnownFPClasses` field with getters/setters.
DeltaFile
+79-77llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
+48-38llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+36-32llvm/include/llvm/Support/KnownFPClass.h
+22-21llvm/lib/Support/KnownFPClass.cpp
+18-17llvm/unittests/Analysis/ValueTrackingTest.cpp
+15-15llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+218-2008 files not shown
+261-24214 files

FreeBSD/ports c253363x11/babl Makefile

x11/babl: Fix build

meson.build:1:0: ERROR: Value "false" (of type "string") for option "gi-docgen" is not one of the choices. Possible choices are (as string): "enabled", "disabled", "auto".

Approved by:    blanket (fix build)
Fixes:          90274e2e7fe3 (update to 0.1.128 release)
Sponsored by:   UNIS Labs
DeltaFile
+2-2x11/babl/Makefile
+2-21 files

OpenBSD/src NJjQBEisys/dev/pci/drm drm_prime.c, sys/dev/pci/drm/include/linux scatterlist.h

   unstub drm_prime_get_contiguous_size()

   called by xe, not currently used
VersionDeltaFile
1.12+4-1sys/dev/pci/drm/include/linux/scatterlist.h
1.14+0-4sys/dev/pci/drm/drm_prime.c
+4-52 files

FreeBSD/ports ed659c9mail/py-resend Makefile distinfo

mail/py-resend: Update to 2.44.0

Changelog: https://github.com/resend/resend-python/releases/tag/v2.44.0

Reported by:    Repology
DeltaFile
+3-3mail/py-resend/distinfo
+1-1mail/py-resend/Makefile
+4-42 files

LLVM/project cd7b268llvm/tools/llvm-offload-binary llvm-offload-binary.cpp

unnecessary
DeltaFile
+1-1llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp
+1-11 files

LLVM/project ef35765llvm/lib/Object OffloadBinary.cpp

fix alignment
DeltaFile
+3-2llvm/lib/Object/OffloadBinary.cpp
+3-21 files

FreeBSD/ports 66ac7d7databases/py-redisvl Makefile distinfo

databases/py-redisvl: Update to 0.27.2

Changelog: https://github.com/redis/redis-vl-python/releases/tag/v0.27.2

Reported by:    Repology
DeltaFile
+3-3databases/py-redisvl/distinfo
+1-1databases/py-redisvl/Makefile
+4-42 files

LLVM/project cbd89f8llvm/lib/Target/AArch64 AArch64ConditionalCompares.cpp, llvm/test/CodeGen/AArch64 cmpbr-ccmp.ll cmpbr-ccmp.mir

[AArch64] Form CCMP for CBB and CBH

AArch64ConditionalCompares forms CMP/CCMP chains to transform patterns
such as

                 Head                        Head
                 / |                         CmpBB
                /  |                         / |
               |  CmpBB        =>           /  |
               |  / |                    Tail  |
               | /  |                      |   |
              Tail  |                      |   |
                |   |                      |   |
               ... ...                    ... ...

where Head is terminated by a conditional branch and CmpBB contains
a cmp + conditional branch.

We usually try to split any fused conditional branches to be able to

    [8 lines not shown]
DeltaFile
+406-0llvm/test/CodeGen/AArch64/cmpbr-ccmp.mir
+232-0llvm/test/CodeGen/AArch64/cmpbr-ccmp.ll
+38-2llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
+676-23 files

FreeBSD/ports 516242dwww/py-sherlock-project distinfo Makefile

www/py-sherlock-project: Update to 0.16.2

Changelog: https://github.com/sherlock-project/sherlock/compare/v0.16.0...v0.16.2

Reported by:    Repology
DeltaFile
+3-3www/py-sherlock-project/distinfo
+3-3www/py-sherlock-project/Makefile
+6-62 files

LLVM/project 821ff7cllvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange no-partially-perfect-subnest.ll preserve-sibling-order.ll

[LoopInterchange] Supported partially-perfect Loop Nests (#199511)

In the current implementation when the outermost loop contains sibling
sub-loops (i.e. multiple independent loop nests at the same depth), the
pass silently skips the entire loop nest without attempting to
interchange any of the valid sub-nests (See Below Example).

Example:
```
for(int i=0; i<n; i++){  // Loop 1
    for(int j=0; j<m; j++){  // Loop 2
         for(int r=0; r<m; r++){  // Loop 3
         // Do something
         }
    }
    for(int k=0; k<p; k++){  // Loop 4
        for(int l=0; l<p; l++){  // Loop 5
            //Access A[l][k]
        }

    [7 lines not shown]
DeltaFile
+126-0llvm/test/Transforms/LoopInterchange/missed-outer-prefix-subnest.ll
+119-0llvm/test/Transforms/LoopInterchange/confused-dependence-subnest.ll
+111-0llvm/test/Transforms/LoopInterchange/dependency-matrix-padding.ll
+69-26llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+72-0llvm/test/Transforms/LoopInterchange/preserve-sibling-order.ll
+63-0llvm/test/Transforms/LoopInterchange/no-partially-perfect-subnest.ll
+560-263 files not shown
+622-579 files

LLVM/project 9526701llvm/docs/GlobalISel GenericOpcode.md, llvm/include/llvm/Target GenericOpcodes.td

[RISCV][GlobalISel] Add G_CLMULH support (#221686)

Add G_CLMULH to represent the high half of a carry-less multiplication
in generic Machine IR.

Translate llvm.riscv.clmulh to G_CLMULH and mark it legal for native
XLEN scalar types when Zbkc is available. Reuse the existing
SelectionDAG pattern to select the RISC-V CLMULH instruction.
DeltaFile
+60-0llvm/test/CodeGen/RISCV/GlobalISel/clmul-rv64.ll
+28-0llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+15-0llvm/test/CodeGen/RISCV/GlobalISel/clmul-rv32.ll
+10-0llvm/docs/GlobalISel/GenericOpcode.md
+8-0llvm/include/llvm/Target/GenericOpcodes.td
+2-2llvm/test/TableGen/get-named-operand-idx.td
+123-24 files not shown
+133-210 files

NetBSD/src 4EnPXgbsys/arch/arm/dts imx8mq-phanbell.dts

   Enable sdhc on Google i.MX8MQ Phanbell
VersionDeltaFile
1.1+36-0sys/arch/arm/dts/imx8mq-phanbell.dts
+36-01 files

NetBSD/pkgsrc NnkgsKhdoc CHANGES-2026

   doc: Updated wm/enlightenment16 to 1.0.32
VersionDeltaFile
1.6005+2-1doc/CHANGES-2026
+2-11 files