LLVM/project 2fc0733llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 faddv.ll faddv-fp16.ll

[AArch64] Decompose FADD reductions with known zero elements (#167313)

FADDV is matched into FADDPv4f32 + FADDPv2i32p but this can be relaxed
when one element (usually the 4th) or more are known to be zero.

Before:
```
movi d1, #0000000000000000
mov v0.s[3], v1.s[0]
faddp v0.4s, v0.4s, v0.4s
faddp s0, v0.2s
```

After:
```
mov s1, v0.s[2]
faddp s0, v0.2s
fadd s0, s0, s1
```

    [2 lines not shown]
DeltaFile
+301-0llvm/test/CodeGen/AArch64/faddv.ll
+130-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+68-0llvm/test/CodeGen/AArch64/faddv-fp16.ll
+2-3llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
+501-34 files

LLVM/project 6c41d12llvm/lib/Transforms/Vectorize VPlanTransforms.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize vplan-based-stride-mv.ll

[VPlan] Implement VPlan-based stride speculation
DeltaFile
+928-1,076llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+273-150llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+237-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+54-3llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+43-0llvm/lib/Transforms/Vectorize/VPlan.h
+5-5llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+1,540-1,2376 files not shown
+1,568-1,24012 files

LLVM/project e92dd71llvm/lib/Target/RISCV RISCVInstrInfoP.td

[RISCV] Add Defs = VXSAT to P extension instructions. (#183455)

DeltaFile
+91-2llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+91-21 files

FreeNAS/freenas ddf912esrc/middlewared/middlewared/plugins ntp.py, src/middlewared/middlewared/plugins/ntp peers.py __init__.py

NAS-140001 / 26.0.0-BETA.1 / Move ntp namespace to be typesafe (#18307)

## Context

Move ntp plugin to typesafe implemenation.
DeltaFile
+0-246src/middlewared/middlewared/plugins/ntp.py
+138-0src/middlewared/middlewared/plugins/ntp/peers.py
+86-0src/middlewared/middlewared/plugins/ntp/__init__.py
+61-0src/middlewared/middlewared/plugins/ntp/enums.py
+0-59src/middlewared/middlewared/plugins/ntp_/enums.py
+58-0src/middlewared/middlewared/plugins/ntp/crud.py
+343-3058 files not shown
+414-36314 files

NetBSD/pkgsrc nR7ywBjdevel/zycore-c PLIST Makefile

   Initial import of devel/zycore-c version 1.5.1.

   Internal library for zydis disassembler providing platform independent
   types, macros and a fallback for environments without LibC.
VersionDeltaFile
1.1+31-0devel/zycore-c/PLIST
1.1+19-0devel/zycore-c/Makefile
1.1+13-0devel/zycore-c/buildlink3.mk
1.1+5-0devel/zycore-c/distinfo
1.1+2-0devel/zycore-c/DESCR
+70-05 files

LLVM/project c6db35fmlir/lib/Dialect/XeGPU/Transforms XeGPUPeepHoleOptimizer.cpp, mlir/test/Dialect/XeGPU peephole-optimize.mlir

[mlir][xegpu] Retain order attribute during load + transpose optimization. (#183608)

As described in the title `order` attribute is ignored in this
transformation causing downstream test failures.
DeltaFile
+59-47mlir/test/Dialect/XeGPU/peephole-optimize.mlir
+3-2mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
+62-492 files

LLVM/project 1ab63d5llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize induction.ll single-value-blend-phis.ll

[VPlan] Process instructions in reverse order when widening

It doesn't matter right now because we're using CM's decision, but
https://github.com/llvm/llvm-project/pull/182595 introduces some
scalarization (first-lane-only) opportunites that aren't known in CM and
those require reverse iteration order to support as those are determined
by VPUsers and not operands.
DeltaFile
+27-27llvm/test/Transforms/LoopVectorize/induction.ll
+4-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-3llvm/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
+3-3llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
+1-1llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
+38-365 files

LLVM/project 6bc9ba7llvm/lib/Target/Hexagon HexagonISelLowering.cpp, llvm/test/CodeGen/Hexagon vgather-memvt.ll

[Hexagon] Fix memory type for vgather intrinsics (#183563)

Some of the Hexagon vgather intrinsics were picking the memory type
(memVT) from a fixed argument position, but for several variants (e.g.
the predicated ones), that argument isn’t actually the data vector being
gathered. As a result, LLVM could end up recording the wrong memory type
or size (e.g. i32 or mask instead of the vector arg). This patch fixes
that by always taking memVT from the last intrinsic argument, which is
the actual data vector.
DeltaFile
+35-0llvm/test/CodeGen/Hexagon/vgather-memvt.ll
+2-1llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+37-12 files

FreeBSD/src c944960sys/compat/linuxkpi/dummy/include/net/page_pool helpers.h

LinuxKPI: remove dumm header now in common

page_pool/helpers.h does exist in common/include/net/page_pool/helpers.h
so we can remove the dummy header file.

Sponosred by:   The FreeBSD Foundation
MFC after:      3 days
DeltaFile
+0-0sys/compat/linuxkpi/dummy/include/net/page_pool/helpers.h
+0-01 files

LLVM/project 10abb23flang/docs GettingInvolved.md

[flang] Update the Flang Community Call to the new MS Teams series (#183576)

DeltaFile
+10-10flang/docs/GettingInvolved.md
+10-101 files

FreeBSD/ports e37ae1cdns/nextdns distinfo Makefile

dns/nextdns: Update to 1.47.1

Approved by:    rs at nextdns.io (maintainer)
DeltaFile
+5-17dns/nextdns/distinfo
+3-15dns/nextdns/Makefile
+8-322 files

OPNSense/plugins 6ca5e21net/haproxy pkg-descr, net/haproxy/src/opnsense/mvc/app/views/OPNsense/HAProxy maintenance.volt index.volt

Merge pull request #5265 from fraenki/haproxy_501a

net/haproxy: modernize UI templates
DeltaFile
+104-147net/haproxy/src/opnsense/mvc/app/views/OPNsense/HAProxy/maintenance.volt
+56-105net/haproxy/src/opnsense/mvc/app/views/OPNsense/HAProxy/index.volt
+69-89net/haproxy/src/opnsense/mvc/app/views/OPNsense/HAProxy/statistics.volt
+27-31net/haproxy/src/opnsense/mvc/app/views/OPNsense/HAProxy/export.volt
+3-0net/haproxy/pkg-descr
+259-3725 files

LLVM/project 2c51e70llvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

Use createLoopSkeleton intead of manually building nested loop

Create flattened 1-dimension canonical loop for omp.iterator
DeltaFile
+92-52mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+0-82llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+0-27llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+92-1613 files

LLVM/project 2d6ec9cllvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

Implement lowering for omp.iterator in affinity

Create IteratorLoopNestScope for building nested loop for iterator.
Take advantage of RAII so that we can have correct exit for each
level of the loop.
DeltaFile
+158-22mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+82-0llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+27-0llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+1-0mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
+268-224 files

LLVM/project 675e34allvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

Refactor and support multiple affinity register for a task

- Support multiple affinity register for a task
- Move iterator loop generate logic to OMPIRBuilder
- Extract iterator loop body convertion logic
- Refactor buildAffinityData by hoisting the creation of affinity_list
- IteratorsOp -> IteratorOp
- Add mlir to llvmir test
DeltaFile
+143-123mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+226-0mlir/test/Target/LLVMIR/openmp-iterator.mlir
+68-16llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+34-1llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+33-0mlir/test/Target/LLVMIR/openmp-llvm.mlir
+504-1405 files

LLVM/project d5e5017llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanRecipes.cpp

Reapply "[VPlan] Use VPInstructionWithType for Load in VPlan0 (NFC)"

This reverts commit 97835516393311d681d1ff6bec67e1093f94890e.

Unit tests have been updated
DeltaFile
+7-0llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+6-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+4-0llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+1-0llvm/lib/Transforms/Vectorize/VPlan.h
+18-04 files

FreeBSD/ports 2d35193deskutils/cherrytree distinfo Makefile

deskutils/cherrytree: update the port to version 1.6.3

Reported by:    portscout
DeltaFile
+3-3deskutils/cherrytree/distinfo
+1-2deskutils/cherrytree/Makefile
+4-52 files

LLVM/project d392560llvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[mlir][llvmir][OpenMP] Translate affinity clause in task construct to llvmir

Translate affinity entries to LLVMIR by passing affinity information to
createTask (__kmpc_omp_reg_task_with_affinity is created inside PostOutlineCB).
DeltaFile
+92-0llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+59-13mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+19-3llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+12-6llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+0-12mlir/test/Target/LLVMIR/openmp-todo.mlir
+2-0mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
+184-346 files

LLVM/project 46c06a3llvm/unittests/Transforms/Vectorize VPlanHCFGTest.cpp

[VPlan] Fixup C++ unit test output after 2576ee1fd93f.
DeltaFile
+2-2llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
+2-21 files

FreeNAS/freenas 77598fesrc/middlewared/middlewared/plugins ntp.py, src/middlewared/middlewared/plugins/ntp peers.py __init__.py

Move ntp namespace to be typesafe
DeltaFile
+0-246src/middlewared/middlewared/plugins/ntp.py
+138-0src/middlewared/middlewared/plugins/ntp/peers.py
+86-0src/middlewared/middlewared/plugins/ntp/__init__.py
+61-0src/middlewared/middlewared/plugins/ntp/enums.py
+0-59src/middlewared/middlewared/plugins/ntp_/enums.py
+58-0src/middlewared/middlewared/plugins/ntp/crud.py
+343-3058 files not shown
+414-36314 files

LLVM/project 177cbedclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

more fmt yo
DeltaFile
+1-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+1-11 files

OpenBSD/ports dpxsFFldevel/py-icalendar-searcher Makefile distinfo, devel/py-icalendar-searcher/pkg PLIST

   update to py3-icalendar-searcher-1.0.5
VersionDeltaFile
1.2+2-10devel/py-icalendar-searcher/Makefile
1.2+2-2devel/py-icalendar-searcher/distinfo
1.2+3-0devel/py-icalendar-searcher/pkg/PLIST
+7-123 files

LLVM/project 9783551llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanRecipes.cpp

Revert "[VPlan] Use VPInstructionWithType for Load in VPlan0 (NFC)"

This reverts commit 2576ee1fd93fb87699650734ffafdb8092062d59.

This was causing test failures when running check-llvm-unit.
DeltaFile
+0-7llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+0-6llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+0-4llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+0-1llvm/lib/Transforms/Vectorize/VPlan.h
+0-184 files

LLVM/project dbaa4d1llvm/docs NVPTXUsage.rst, llvm/include/llvm/IR IntrinsicsNVVM.td

[NVPTX] Support intrinsics for reserved shared memory special registers (#182354)

Added reserved_smem_offset_{begin|end|cap|0} intrinsics to expose shared
memory special registers and NVPTX TableGen support for these
intrinsics.
DeltaFile
+40-0llvm/test/CodeGen/NVPTX/reserved-smem-offset.ll
+36-0llvm/docs/NVPTXUsage.rst
+19-4llvm/include/llvm/IR/IntrinsicsNVVM.td
+8-0llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+103-44 files

pfSense/pfsense 3d5544esrc/usr/local/bin iftop_parser.sh

Clean up and modernize the iftop_parser script
DeltaFile
+17-17src/usr/local/bin/iftop_parser.sh
+17-171 files

pfSense/pfsense c3234b3src/usr/local/bin iftop_parser.sh

Replace spaces with tabs
DeltaFile
+27-27src/usr/local/bin/iftop_parser.sh
+27-271 files

LLVM/project 1630c0eclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

fix fmt
DeltaFile
+9-4clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+9-41 files

LLVM/project 9e991a1clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/lib/CIR/Dialect/IR CIRDialect.cpp

Global AS lowering For CUDA and CIRGen tests for target AS
DeltaFile
+30-0clang/test/CIR/CodeGenCUDA/address-spaces.cu
+23-5clang/lib/CIR/CodeGen/CIRGenModule.cpp
+17-0clang/test/CIR/CodeGen/address-space.c
+2-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+72-54 files

FreeNAS/freenas 2ef0c3bsrc/middlewared/middlewared/plugins/iscsi_ scst.py

Address review
DeltaFile
+2-2src/middlewared/middlewared/plugins/iscsi_/scst.py
+2-21 files

LLVM/project e46ddc5llvm/include/llvm/Transforms/Utils MemoryTaggingSupport.h

cmt

Created using spr 1.3.7
DeltaFile
+3-0llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
+3-01 files