pci: Export pcie_flr_supported()
Move the capability and quirk checks used by pcie_flr() into a public
side effect free helper. This lets callers determine whether an FLR
can be attempted before quiescing a device or saving state.
The helper considers the advertised PCIe FLR capability and both the
enable and disable FLR quirks.
MFC after: 2 weeks
Sponsored by: BBOX.io
[APFloat][SelectionDAG] Support Float8E5M3FNU in convert.{to,from}.arbitrary.fp
Float8E5M3FNU was already accepted by the IR verifier, because
isValidArbitraryFPFormat is defined in terms of
getArbitraryFPFormatSizeInBits and that table covers it. It was missing
from getArbitraryFPSemantics, so SelectionDAGBuilder rejected
it with "not implemented format" and the verifier-clean IR failed to
compile. Add the mapping and the corresponding entries in the
expandCONVERT_{TO,FROM}_ARBITRARY_FP format allowlists.
Unlike every other format the expansions handle so far, Float8E5M3FNU is
unsigned: it has no sign bit, so all 8 bits go to a 5-bit exponent and a
3-bit significand.
Since an unsigned format cannot represent a negative value, a negative
input now saturates to zero when the saturate flag is set, and is poison
otherwise. -0.0 is excluded from that and still converts to +0, and the
check is ordered before the NaN case so a negative NaN still produces the
NaN encoding. APFloat treats constructing a negative value in an unsigned
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[APFloat][NFC] Add unit test coverage for `getArbitraryFPSemantics` (#216501)
`isValidArbitraryFPFormat` and `getArbitraryFPFormatSizeInBits` have
unit tests, but `getArbitraryFPSemantics`, the mapping the conversion
intrinsics actually lower through, had none. Cover the formats it
supports, the valid formats it does not support yet, and invalid format
strings, and check that the two tables agree on the size of every format
with lowerable semantics.
Also add the missing Float8E5M3FNU case to the
`getArbitraryFPFormatSizeInBits` test.
[AArch64][GlobalISel] Do not create atomic truncstore (#216522)
After #213935 the i64->i32 truncstore was failing to create a COPY
correctly.
We do not have tablegen patterns, so mirror what SDAG does and do not
create
atomic truncstore.
[MIPS][NFC] test mips variadic aggregate handling (#216509)
mips64 has some bugs here that I'll address in a followup. The problem
is that we get `inreg {float}` items in the variable argument list. That
breaks for aggregates like `_Complex long double` or just `struct { long
double a; b }`.
[libc][bazel] Update bazel overlay for ceilf128 emulated float128 changes (#216515)
This updates the Bazel overlay following commit
e5174fe683e882f6bbd2ef023c9c9e293b273a98:
- Remove `:llvm_libc_types_float128` from `__support_math_ceilf128` deps
as `include/llvm-libc-types/float128.h` is no longer included.
- Add `:__support_cpp_bit` to `ceilf128` additional_deps for `bit_cast`.
- Add `ceilf128` math MPFR test target in
`libc/test/src/math/BUILD.bazel`.
[analyzer] Correctly highlight the variables' range in UseAfterLifetimeEnd reports (#215905)
Currently in the emitted reports from the `UseAfterLifetimeEnd` checker
the highlight range of the variables is incorrect which can lead to
confusion for the user.
```
temp.cpp:5:31: note: Value's lifetime bound to the lifetime of 'y' here
4 | int x = 1, y = 2;
| ~~~~~~~~~~~~~~~~
```
In this emitted note the highlight of the variable `y` incorrectly spans
to the variable `x` as well and vice versa. This does not meet the
quality requirements of a core Clang Static Analyzer Checker.
In this PR I get the `VarDecl` of the `VarRegion` and then return the
`SourceRange` based on the `VarDecl`'s location through `getLocation`.
This leads to the following emitted notes:
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AArch64: Use MIPatternMatch in PostLegalizerCombiner ext checks
Replace the getVRegDef + opcode-check idiom with mi_match. Add an
m_GSExtInReg matcher for G_SEXT_INREG, which has an extra immediate
operand and so does not fit the plain unary-op matcher shape.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
