LLVM/project e5adddcmlir/lib/Transforms Mem2Reg.cpp, mlir/test/Dialect/MemRef mem2reg.mlir

[MLIR] [Mem2Reg] Fix unused block argument removal logic (#188484)

There was a problem with the way Mem2Reg was removing unused block
arguments, as it was incorrectly assuming the reaching definition was
still available when connecting the successor operands but it may have
been removed as part of the mem2reg process. This approach instead
places successor operands eagerly, and removes them along with the block
argument if unused (similarly to how it was done before the region
support).

This also fixes what I think was a long-standing issue where a block
argument only used by operations that will be deleted would not be
considered unused.

Fixes #188252
DeltaFile
+105-33mlir/lib/Transforms/Mem2Reg.cpp
+133-0mlir/test/Dialect/MemRef/mem2reg.mlir
+238-332 files

LLVM/project 6c8940cclang/lib/Sema SemaDeclAttr.cpp SemaAvailability.cpp, clang/test/CodeGen availability-check-anyappleos.c

Add support for anyAppleOS availability (#181953)

The number of Apple platforms has grown over the years, resulting in
availability annotations becoming increasingly verbose. Now that OS
version names have been unified starting with version 26.0, this patch
introduces a shorthand syntax that applies availability across all Apple
platforms:

```
// Declaration.
void foo __attribute__((availability(anyAppleOS, introduced=26.0)));

// Guard.
if (__builtin_available(anyAppleOS 27.0, *))
```

Implementation:

The `anyAppleOS` platform name is expanded at parse time into implicit

    [31 lines not shown]
DeltaFile
+203-0clang/test/Sema/attr-availability-anyappleos.c
+141-0clang/test/Sema/attr-availability-anyappleos-builtin.m
+128-0clang/test/CodeGen/availability-check-anyappleos.c
+62-2clang/lib/Sema/SemaDeclAttr.cpp
+35-0clang/test/Sema/attr-availability-anyappleos-ast.c
+20-6clang/lib/Sema/SemaAvailability.cpp
+589-810 files not shown
+667-1416 files

LLVM/project 0fa1c0allvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU frame-index-disjoint-s-or-b32.ll eliminate-frame-index-scalar-bit-ops.mir

AMDGPU: Fold frame indexes into disjoint s_or_b32

Some pointer adds get turned into ors, and sometimes and is
performed on pointers for masking.
DeltaFile
+220-0llvm/test/CodeGen/AMDGPU/frame-index-disjoint-s-or-b32.ll
+161-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
+6-2llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+387-23 files

LLVM/project 7e44db9lldb/source/Commands CommandObjectThread.cpp, lldb/source/Plugins/Process/gdb-remote GDBRemoteCommunication.cpp

[lldb][NFC] Remove unused variables (#188385)

Remove unused local variable `s` in
GDBRemoteCommunication::CheckForPacket and unused member
`m_step_thread_idx` in CommandObjectThreadUntil.
DeltaFile
+0-1lldb/source/Commands/CommandObjectThread.cpp
+0-1lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
+0-22 files

OPNSense/core 4be4290src/opnsense/mvc/app/controllers/OPNsense/Kea/forms dialogSubnet6.xml dialogSubnet4.xml, src/opnsense/mvc/app/models/OPNsense/Kea KeaDhcpv4.php KeaDhcpv6.php

Services: Kea: DDNS: Add subnet specific qualifying suffix and prevent updates if no server is set.
DeltaFile
+12-4src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv4.php
+11-2src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv6.php
+10-1src/opnsense/mvc/app/controllers/OPNsense/Kea/forms/dialogSubnet6.xml
+10-1src/opnsense/mvc/app/controllers/OPNsense/Kea/forms/dialogSubnet4.xml
+1-0src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv6.xml
+1-0src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv4.xml
+45-86 files

OPNSense/core 6ec7fc6src/opnsense/mvc/app/controllers/OPNsense/Kea/forms dialogSubnet6.xml dialogSubnet4.xml, src/opnsense/mvc/app/models/OPNsense/Kea KeaDhcpv4.php KeaDhcpv6.php

Services: Kea: DDNS: Add subnet specific qualifying suffix and prevent updates if no server is set.
DeltaFile
+13-4src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv4.php
+12-2src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv6.php
+10-1src/opnsense/mvc/app/controllers/OPNsense/Kea/forms/dialogSubnet6.xml
+10-1src/opnsense/mvc/app/controllers/OPNsense/Kea/forms/dialogSubnet4.xml
+1-0src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv6.xml
+1-0src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv4.xml
+47-86 files

LLVM/project 60c911allvm/lib/Target/AArch64 AArch64PointerAuth.cpp AArch64.h

[NewPM] Adds a port for AArch64PointerAuth (#188352)

Adds a standard NewPM port for AArch64PointerAuth.

No test updates since all `.mir` files referencing this pass run
combinations of passes, not all of which are ported.
DeltaFile
+35-15llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+7-1llvm/lib/Target/AArch64/AArch64.h
+1-1llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+1-0llvm/lib/Target/AArch64/AArch64PassRegistry.def
+44-174 files

LLVM/project ce6d3a4llvm/test/Transforms/SLPVectorizer/X86 select-logical-or-and-i1-vector.ll

[SLP][NFC]Add a test with incorrect cost model for short-circuit or/and, modeled via select
DeltaFile
+157-0llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
+157-01 files

LLVM/project 8491df6llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.trig.preop.ll

AMDGPU/GlobalISel: RegBankLegalize rules for trig_preop (#188312)
DeltaFile
+5-5llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+9-52 files

LLVM/project d893374flang/include/flang/Semantics openmp-utils.h, flang/lib/Semantics openmp-utils.cpp check-omp-atomic.cpp

[flang][OpenMP] Rename GetAllDesignators to GetTopLevelDesignators, NFC (#188520)

The function collects all top-level designators. Emphasize the "top
level" part for clarity.
DeltaFile
+3-3flang/lib/Semantics/openmp-utils.cpp
+1-1flang/include/flang/Semantics/openmp-utils.h
+1-1flang/lib/Semantics/check-omp-atomic.cpp
+5-53 files

LLVM/project 32720fbclang/docs LanguageExtensions.rst, clang/lib/CodeGen CGLoopInfo.cpp CGLoopInfo.h

[clang] Pragma for llvm.loop.licm.disable (#188108)

llvm.loop.licm.disable is already availabe at LLVM-IR level to disable
LICM per loop. This PR simply exposes that capability to the developers
at clang level.
DeltaFile
+15-10clang/lib/Parse/ParsePragma.cpp
+24-0clang/test/CodeGenCXX/pragma-loop-licm.cpp
+16-2clang/lib/CodeGen/CGLoopInfo.cpp
+17-0clang/docs/LanguageExtensions.rst
+10-1clang/lib/Sema/SemaStmtAttr.cpp
+8-0clang/lib/CodeGen/CGLoopInfo.h
+90-132 files not shown
+95-158 files

LLVM/project 3dd98b7llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU amdgpu-reloc-const.ll

 AMDGPU/GlobalISel: RegBankLegalize rules for reloc_constant (#188315)
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
+2-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+4-32 files

LLVM/project 69f9ff6llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.wqm.demote.ll regbankselect-amdgcn.wqm.demote.mir

AMDGPU/GlobalISel: RegBankLegalize rules for wqm_demote (#188288)
DeltaFile
+113-102llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
+7-11llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+122-1133 files

LLVM/project 6e916d0cross-project-tests/debuginfo-tests/llvm-prettyprinters/lldb pointer-union.test pointer-union.cpp, llvm/benchmarks PointerUnionBM.cpp

[llvm][ADT] Add variable-width tag encoding to PointerUnion (#188167)

PointerUnion stores a fixed-width `ceil(log2(N))`-bit tag in the low
bits of the pointer. This works only when every member type provides at
least that many low bits — if the least-aligned type doesn't,
compilation fails, even though the higher-aligned types may have plenty
of spare bits going to waste.

Introduce a variable-length escape-encoded tag that exploits the extra
low bits of higher-aligned types, analogous to UTF-8: types are grouped
into tiers by NumLowBitsAvailable; each non-final tier reserves one code
as an escape prefix, and the next tier extends the tag into the newly
available bits. This allows PointerUnion to hold more type variants than
a fixed-width tag permits.

The fixed-width path is used when the minimum alignment already provides
enough bits (the common case); the variable-width path activates only
when it doesn't, and requires types to be listed in non-decreasing
NumLowBitsAvailable order.

    [4 lines not shown]
DeltaFile
+480-9llvm/unittests/ADT/PointerUnionTest.cpp
+159-15llvm/include/llvm/ADT/PointerUnion.h
+121-4llvm/benchmarks/PointerUnionBM.cpp
+25-0cross-project-tests/debuginfo-tests/llvm-prettyprinters/lldb/pointer-union.test
+18-0cross-project-tests/debuginfo-tests/llvm-prettyprinters/lldb/pointer-union.cpp
+803-285 files

LLVM/project d362bd7llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp

[TargetLowering] use APInt::getLowBitsSet instead of APInt::getAllOnes+zext. (#188384)
DeltaFile
+1-1llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+1-11 files

OPNSense/ports 2ec811dopnsense/filterlog-go distinfo Makefile

opnsense/filterlog-go: update to 0.9.0
DeltaFile
+5-5opnsense/filterlog-go/distinfo
+1-1opnsense/filterlog-go/Makefile
+6-62 files

LLVM/project 18250fdclang/include/clang/Basic AttrDocs.td Attr.td, clang/lib/CodeGen CodeGenModule.cpp

[HLSL][SPIR-V] Add vk::ext_builtin_output attribute (#188268)

This attribute is similar to the already implemented ext_builtin_input
attribute.
One important bit is the `static` storage class: HLSL uses static
differently than C/C++. This is a known weirdness:
 See https://github.com/microsoft/hlsl-specs/issues/350

In C/C++, when we declare a variable as 'extern', we often expect
another module to declare the symbole. In HLSL, the pipeline will
'declare' the symbol. Hence in this case, we need to emit the global
variable.

Related WG-HLSL:
  https://github.com/llvm/wg-hlsl/blob/main/proposals/0031-semantics.md

---------

Co-authored-by: Steven Perron <stevenperron at google.com>
DeltaFile
+27-0clang/test/SemaHLSL/vk-ext-output-builtin.hlsl
+23-0clang/include/clang/Basic/AttrDocs.td
+21-0clang/lib/Sema/SemaHLSL.cpp
+15-0clang/test/CodeGenHLSL/vk-output-builtin.hlsl
+14-0clang/include/clang/Basic/Attr.td
+11-0clang/lib/CodeGen/CodeGenModule.cpp
+111-017 files not shown
+136-323 files

LLVM/project 414f0c3utils/bazel/llvm-project-overlay/clang BUILD.bazel

[Bazel] Fixes 731bcb5 (#188519)

This fixes 731bcb5a1c77403b496f13674ff1994795ce3a44.
DeltaFile
+19-0utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+19-01 files

LLVM/project 8afb462mlir/include/mlir/Bindings/Python IRCore.h, mlir/lib/Bindings/Python IRCore.cpp

[MLIR] [Python] Fixed a long standing bug in the `PyRegionListIterator` (#188475)

`PyRegionIterator` did not account for start index/step, so this commit
removes it in favor of the sequence iterator provided by CPython.

The previous attempt in #137232 bitrotted, so I decided to open a new
PR.
DeltaFile
+0-30mlir/lib/Bindings/Python/IRCore.cpp
+0-20mlir/include/mlir/Bindings/Python/IRCore.h
+12-1mlir/test/python/ir/operation.py
+12-513 files

LLVM/project 9a1ebaeclang/lib/Driver/ToolChains Clang.cpp, clang/test/CodeGen stack-protector-guard.c

[AARCH64] Support TPIDR_EL0 and TPIDRRO_EL0 as stack protector sysregs (#188054)

Even though the command line option suggests that arbitrary system
registers may be chosen, the sysreg option for the stack protector guard
currently only permits SP_EL0, as this is what the Linux kernel uses.

While it makes no sense to permit arbitrary system registers here (which
usually have side effects), there is a desire to switch to TPIDR_EL0 or
TPIDRRO_EL0 from the Linux side, both of which are part of the base v8.0
AArch64 ISA, and can hold arbitrary 64-bit values without side effects.

So add TPIDR_EL0 and TPIDRRO_EL0 to the set of accepted arguments for
the -mstack-protected-guard-reg= command line option. For good measure,
add TPIDR_EL1, TPIDR_EL2, FAR_EL1 and FAR_EL2 as well, all of which
could potentially be useful to privileged software such as the Linux
kernel to stash a per-thread pointer to the stack protector guard value.

Signed-off-by: Ard Biesheuvel <ardb at kernel.org>
DeltaFile
+31-12llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
+26-2clang/test/CodeGen/stack-protector-guard.c
+9-2clang/lib/Driver/ToolChains/Clang.cpp
+6-1clang/test/Driver/stack-protector-guard.c
+72-174 files

FreeNAS/freenas 74734f0src/middlewared/middlewared/plugins/failover_ event.py

NAS-140406 / 26.0.0-BETA.1 / Ensure remote disk.retaste during vrrp_master is quick (by bmeagherix) (#18560)
DeltaFile
+9-3src/middlewared/middlewared/plugins/failover_/event.py
+9-31 files

FreeBSD/src 648d0fetests/sys/netpfil/common utils.subr

ipfw: skip tests if required sysctl is not set

Since this is a configuration prerequisite rather than a test failure, use
atf_skip instead.

Sponsored by:   Netflix
Differential Revision:  https://reviews.freebsd.org/D56069
DeltaFile
+1-1tests/sys/netpfil/common/utils.subr
+1-11 files

FreeNAS/freenas 77c2beasrc/middlewared/middlewared/plugins/failover_ event.py

NAS-140406 / 26.0.0-BETA.2 / Ensure remote disk.retaste during vrrp_master is quick (by bmeagherix) (#18561)
DeltaFile
+9-3src/middlewared/middlewared/plugins/failover_/event.py
+9-31 files

LLVM/project 27abb7fllvm/lib/CodeGen/SelectionDAG LegalizeIntegerTypes.cpp, llvm/test/CodeGen/AArch64 vector-extract-last-active.ll

[SDAG] Follow target boolean semantics in `PromoteIntOp_VECTOR_FIND_LAST_ACTIVE`

Before handling `VECTOR_FIND_LAST_ACTIVE` expansion, ensure the vector
mask elements get extended accordingly, after the vector mask type is
promoted to its legal type.

Fixes: https://github.com/llvm/llvm-project/issues/187875.
DeltaFile
+58-42llvm/test/CodeGen/X86/vector-extract-last-active.ll
+12-8llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
+11-3llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+81-533 files

LLVM/project 0000e52llvm/utils/gn/secondary/clang/include/clang/Basic BUILD.gn, llvm/utils/gn/secondary/clang/lib/Basic BUILD.gn

[gn] port 731bcb5a1c774 (tblgen aarch64 builtins)
DeltaFile
+4-0llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
+1-0llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
+5-02 files

OpenBSD/ports iyZzeKOcomms/hylafax Makefile, comms/hylafax/patches patch-configure patch-faxd_pageSendApp_c++

   update to hylafax-7.0.11, switching to the less inactive hylafax+ fork
   from Larry Moore, some tweaks from me
VersionDeltaFile
1.25+68-264comms/hylafax/pkg/PLIST
1.17+35-82comms/hylafax/patches/patch-configure
1.92+25-25comms/hylafax/Makefile
1.1+46-0comms/hylafax/patches/patch-faxd_pageSendApp_c++
1.1+45-0comms/hylafax/patches/patch-faxd_faxSendApp_c++
1.5+27-6comms/hylafax/patches/patch-etc_faxsetup_sh_in
+246-37729 files not shown
+581-41535 files

FreeBSD/ports 0739235dns/bind-tools pkg-plist-devel, dns/bind9-devel pkg-plist distinfo

dns/bind9-devel: update to 9.21.20

Changes:        https://downloads.isc.org/isc/bind9/9.21.20/doc/arm/html/notes.html#notes-for-bind-9-21-20
Security:       CVE-2026-1519, CVE-2026-3104, CVE-2026-3119, CVE-2026-3591
DeltaFile
+13-13dns/bind9-devel/files/extrapatch-bind-min-override-ttl
+5-5dns/bind-tools/pkg-plist-devel
+5-5dns/bind9-devel/pkg-plist
+3-3dns/bind9-devel/distinfo
+1-1dns/bind9-devel/Makefile
+27-275 files

LLVM/project 6420dd8llvm/test/Transforms/LoopVectorize/AArch64 binop-costs.ll

[LV] Add missing REQUIRES: asserts to new test from #188126.

Test checks debug output, and requires asserts.
DeltaFile
+2-0llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
+2-01 files

FreeBSD/ports 0739234dns/bind-tools pkg-plist, dns/bind920 pkg-plist distinfo

dns/bind920: update to 9.20.21

Changes:        https://downloads.isc.org/isc/bind9/9.20.21/doc/arm/html/notes.html#notes-for-bind-9-20-21
Security:       CVE-2026-1519, CVE-2026-3104, CVE-2026-3119, CVE-2026-3591
DeltaFile
+8-8dns/bind920/files/extrapatch-bind-min-override-ttl
+5-5dns/bind920/pkg-plist
+5-5dns/bind-tools/pkg-plist
+3-3dns/bind920/distinfo
+1-1dns/bind920/Makefile
+22-225 files

FreeBSD/ports 0739233dns/bind918 pkg-plist distinfo, dns/bind918/files extrapatch-bind-min-override-ttl

dns/bind918: update to 9.18.47

Changes:        https://downloads.isc.org/isc/bind9/9.18.47/doc/arm/html/notes.html#notes-for-bind-9-18-47
Security:       CVE-2026-1519
DeltaFile
+7-7dns/bind918/pkg-plist
+7-7dns/bind918/files/extrapatch-bind-min-override-ttl
+3-3dns/bind918/distinfo
+1-1dns/bind918/Makefile
+18-184 files