LLVM/project 9b49aballvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.ll llvm.amdgcn.mfma.bf16.ll

format

Created using spr 1.3.7
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+138-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
+52-27llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+3,431-4685 files not shown
+3,507-47211 files

LLVM/project 8e7801ellvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.ll llvm.amdgcn.mfma.bf16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+138-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
+52-27llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+3,431-4684 files not shown
+3,488-46810 files

LLVM/project b4c6479llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.ll llvm.amdgcn.mfma.bf16.ll

format

Created using spr 1.3.7
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+138-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
+52-27llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+3,431-4684 files not shown
+3,488-46810 files

LLVM/project 11b266cllvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.ll llvm.amdgcn.mfma.bf16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+138-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
+52-27llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+3,431-4684 files not shown
+3,488-46810 files

LLVM/project fe88bd3llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.ll llvm.amdgcn.mfma.bf16.ll

format

Created using spr 1.3.7
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+138-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
+52-27llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+3,431-4684 files not shown
+3,488-46810 files

LLVM/project ce010aellvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.ll llvm.amdgcn.mfma.bf16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+138-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
+52-27llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+3,431-4684 files not shown
+3,488-46810 files

LLVM/project 5d1fe74llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.ll llvm.amdgcn.mfma.bf16.ll

format

Created using spr 1.3.7
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+138-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
+52-27llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+3,431-4684 files not shown
+3,488-46810 files

FreeBSD/ports 4f0eaf1devel/gitaly distinfo, net/gitlab-agent distinfo

www/gitlab: security and patch update to 18.11.1

Changes:        https://docs.gitlab.com/releases/patches/patch-release-gitlab-18-11-1-released/
Security:       73b927a6-3ecd-11f1-be20-2cf05da270f3
DeltaFile
+11-11devel/gitaly/distinfo
+6-6www/gitlab/distinfo
+5-5www/gitlab-workhorse/distinfo
+5-5www/gitlab-pages/distinfo
+5-5net/gitlab-agent/distinfo
+4-4www/gitlab/Makefile
+36-361 files not shown
+37-377 files

LLVM/project e3b3706compiler-rt/lib/asan asan_errors.cpp asan_report.cpp, compiler-rt/test/asan/TestCases assume_dereferenceable.cpp assume_dereferenceable_pass.cpp

Revert "[compiler-rt][asan] Add asan checks for __builtin_assume_dereferencable" (#193655)

Reverts llvm/llvm-project#190871

Why: it breaks tests, no reaction when I pointed it out:


https://ci.swift.org/job/llvm.org/job/clang-stage1-RA-as/job/main/1412/#showFailuresLink

Its looks like you're adding new instrumentation/entry points to ASAN -
can you make it conditional so it doesn't affect the test?

Here's the original PR where the test was defined:
https://reviews.llvm.org/D143675
DeltaFile
+0-87compiler-rt/test/asan/TestCases/assume_dereferenceable.cpp
+0-42llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+8-30compiler-rt/lib/asan/asan_errors.cpp
+0-35compiler-rt/test/asan/TestCases/assume_dereferenceable_pass.cpp
+0-22compiler-rt/test/asan/TestCases/assume_dereferenceable_halt_on_error.cpp
+2-19compiler-rt/lib/asan/asan_report.cpp
+10-2359 files not shown
+18-31315 files

LLVM/project 4363fe9flang/lib/Semantics check-deallocate.cpp, flang/test/Semantics deallocate08.f90

rebase

Created using spr 1.3.7
DeltaFile
+64-0flang/test/Semantics/deallocate08.f90
+16-1libc/docs/full_host_build.rst
+8-4flang/lib/Semantics/check-deallocate.cpp
+88-53 files

LLVM/project 7bdb225flang/lib/Semantics check-deallocate.cpp, flang/test/Semantics deallocate08.f90

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+64-0flang/test/Semantics/deallocate08.f90
+16-1libc/docs/full_host_build.rst
+8-4flang/lib/Semantics/check-deallocate.cpp
+88-53 files

LLVM/project 4f673b2flang/lib/Semantics check-deallocate.cpp, flang/test/Semantics deallocate08.f90

rebase

Created using spr 1.3.7
DeltaFile
+64-0flang/test/Semantics/deallocate08.f90
+16-1libc/docs/full_host_build.rst
+8-4flang/lib/Semantics/check-deallocate.cpp
+88-53 files

LLVM/project b77168fflang/lib/Semantics check-deallocate.cpp, flang/test/Semantics deallocate08.f90

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+64-0flang/test/Semantics/deallocate08.f90
+16-1libc/docs/full_host_build.rst
+8-4flang/lib/Semantics/check-deallocate.cpp
+88-53 files

LLVM/project 965023aflang/lib/Semantics check-deallocate.cpp, flang/test/Semantics deallocate08.f90

rebase

Created using spr 1.3.7
DeltaFile
+64-0flang/test/Semantics/deallocate08.f90
+16-1libc/docs/full_host_build.rst
+8-4flang/lib/Semantics/check-deallocate.cpp
+88-53 files

LLVM/project cb7bd77flang/lib/Semantics check-deallocate.cpp, flang/test/Semantics deallocate08.f90

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+64-0flang/test/Semantics/deallocate08.f90
+16-1libc/docs/full_host_build.rst
+8-4flang/lib/Semantics/check-deallocate.cpp
+88-53 files

LLVM/project b25ccddlibc/docs full_host_build.rst

[libc] Readd instructions on building kernel headers from sources

These existed in this page before
aa0e429576cfb496e66f6bbe76df8982aab6b083. Readd them given I enjoyed
being able to copy and paste them and they're short/simple enough that I
don't think there's a good reason not to just include them.

Reviewers: kaladron, michaelrj-google, nickdesaulniers

Pull Request: https://github.com/llvm/llvm-project/pull/193657
DeltaFile
+16-1libc/docs/full_host_build.rst
+16-11 files

LLVM/project c0ceeadlibcxx/cmake/caches Generic-llvm-libc.cmake, libcxx/test/configs llvm-libc++-llvm-libc.cfg.in

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-62libcxx/cmake/caches/Generic-llvm-libc.cmake
+0-27libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
+0-27libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
+0-20libcxx/utils/ci/run-buildbot
+0-4libcxx/utils/libcxx/test/features/platform.py
+0-3libcxx/test/std/language.support/support.runtime/csignal.pass.cpp
+0-14375 files not shown
+0-36481 files

LLVM/project bd612d7llvm/lib/Transforms/IPO LowerTypeTests.cpp

FIXME

Created using spr 1.3.7
DeltaFile
+1-0llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+1-01 files

LLVM/project 85c13ceflang/lib/Semantics check-deallocate.cpp, flang/test/Semantics deallocate08.f90

[Flang][Semantics] Allow EVENT_TYPE, LOCK_TYPE and NOTIFY TYPE to be deallocate (#192940)

It appears that variables of type `EVENT_TYPE`, `LOCK_TYPE`, and
`NOTIFY_TYPE` are not allowed in the DEALLOCATE statement (but allowed
in ALLOCATE).
The standard does not specify that this type of variable cannot be
ALLOCATABLE and/or cannot be called within a DEALLOCATE
DeltaFile
+64-0flang/test/Semantics/deallocate08.f90
+8-4flang/lib/Semantics/check-deallocate.cpp
+72-42 files

LLVM/project 2003b71llvm/lib/Transforms/IPO LowerTypeTests.cpp, llvm/test/Transforms/LowerTypeTests x86-jumptable-dbg.ll aarch64-jumptable-dbg.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+67-4llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+32-8llvm/test/Transforms/LowerTypeTests/x86-jumptable-dbg.ll
+16-4llvm/test/Transforms/LowerTypeTests/aarch64-jumptable-dbg.ll
+115-163 files

LLVM/project 95b9627llvm/test/CodeGen/AMDGPU wqm-propagate-for-execz-side-effect.mir

update test
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
+1-11 files

LLVM/project 1311d1dllvm/test/CodeGen/AMDGPU wqm-propagate-for-execz-side-effect.mir wqm-propagate-for-execz-side-effect.ll

Merge branch 'add-wqm-test' into wqm-prop-sideeffect
DeltaFile
+238-0llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
+0-127llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.ll
+238-1272 files

Illumos/gate 5f59dffusr/src/boot/efi/libefi env.c, usr/src/boot/efi/loader main.c

17903 loader: expose addresses of firmware tables in loader env
Reviewed by: Gordon Ross <gordon.w.ross at gmail.com>
Approved by: Dan McDonald <danmcd at edgecast.io>
DeltaFile
+34-21usr/src/boot/libsa/smbios.c
+8-0usr/src/boot/efi/libefi/env.c
+6-0usr/src/boot/i386/loader/main.c
+6-0usr/src/boot/efi/loader/main.c
+1-1usr/src/boot/i386/libi386/biosacpi.c
+0-2usr/src/boot/i386/gptzfsboot/Makefile
+55-243 files not shown
+58-269 files

LLVM/project 1bc5944llvm/lib/Target/AMDGPU SIWholeQuadMode.cpp

Do the propagation only once
DeltaFile
+3-0llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+3-01 files

LLVM/project a3fb927clang/test/CodeGenCUDA atomic-options.hip, libc/src/__support/threads CndVar.h

rebase

Created using spr 1.3.7
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+324-25libc/src/__support/threads/CndVar.h
+304-18clang/test/CodeGenCUDA/atomic-options.hip
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+3,869-415134 files not shown
+7,050-1,345140 files

LLVM/project 605b8eaclang/test/CodeGenCUDA atomic-options.hip, libc/src/__support/threads CndVar.h

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+324-25libc/src/__support/threads/CndVar.h
+304-18clang/test/CodeGenCUDA/atomic-options.hip
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+3,869-415134 files not shown
+7,050-1,345140 files

LLVM/project f9b978bclang/test/CodeGenCUDA atomic-options.hip, libc/src/__support/threads CndVar.h

rebase

Created using spr 1.3.7
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+324-25libc/src/__support/threads/CndVar.h
+304-18clang/test/CodeGenCUDA/atomic-options.hip
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+3,869-415135 files not shown
+7,050-1,346141 files

LLVM/project f883340clang/test/CodeGenCUDA atomic-options.hip, libc/src/__support/threads CndVar.h

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+324-25libc/src/__support/threads/CndVar.h
+304-18clang/test/CodeGenCUDA/atomic-options.hip
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+3,869-415135 files not shown
+7,050-1,346141 files

LLVM/project 2565ac6clang/test/CodeGenCUDA atomic-options.hip, libc/src/__support/threads CndVar.h

rebase

Created using spr 1.3.7
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+324-25libc/src/__support/threads/CndVar.h
+304-18clang/test/CodeGenCUDA/atomic-options.hip
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+3,869-415135 files not shown
+7,050-1,346141 files

LLVM/project 7a1618fclang/test/CodeGenCUDA atomic-options.hip, libc/src/__support/threads CndVar.h

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+1,859-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+523-268llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
+698-0llvm/test/CodeGen/WebAssembly/simd-bitmask.ll
+324-25libc/src/__support/threads/CndVar.h
+304-18clang/test/CodeGenCUDA/atomic-options.hip
+161-102llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
+3,869-415134 files not shown
+7,049-1,345140 files