LLVM/project 4b7cf46lldb/include/lldb/Host/windows PseudoConsole.h ProcessLauncherWindows.h, lldb/source/Host/windows PseudoConsole.cpp ProcessLauncherWindows.cpp

[lldb][windows] add STDIN and STDOUT forwarding support (#175812)

DeltaFile
+92-32lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
+66-0lldb/source/Host/windows/PseudoConsole.cpp
+16-8lldb/source/Host/windows/ProcessLauncherWindows.cpp
+10-0lldb/include/lldb/Host/windows/PseudoConsole.h
+8-1lldb/include/lldb/Host/windows/ProcessLauncherWindows.h
+1-1lldb/test/Shell/Settings/TestFrameFormatColor.test
+193-421 files not shown
+194-437 files

LLVM/project f5b62a7mlir/lib/Dialect/Linalg/Transforms Vectorization.cpp, mlir/test/Dialect/Linalg/vectorization insert-slice.mlir

[mlir][linalg] Update createWriteOrMaskedWrite (#174810)

`createWriteOrMaskedWrite` is used extensively in the Linalg vectorizer.
When a write uses non-zero indices, the helper currently computes mask
sizes as if the write started at 0 (`size = dim(d)`), which can produce
incorrect `vector.create_mask` operands for the generated
`vector.transfer_write`. Instead, the mask size should be computed as
`size = dim(d) - write_index(d)`.

EXAMPLE
-------
Let`s use this example to illustrate:
```mlir
%res = tensor.insert_slice
    %src into %dest[0, %c2] [5, 1] [1, 1] : tensor<5x1xi32> into tensor<?x3xi32>
```

This op is vectorized as a pair of `vector.transfer_read` +
`vector.transfer_write` ops. When calculating the mask for the

    [20 lines not shown]
DeltaFile
+73-20mlir/test/Dialect/Linalg/vectorization/insert-slice.mlir
+18-3mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
+91-232 files

OPNSense/core 5109d91src/opnsense/mvc/app/views/OPNsense/Firewall firewall_migration.volt

Firewall: Rules: Migration assistant: Fix typos and improve clarity in migration instructions

(cherry picked from commit a1404a24954f721b355ea4b7d2a11ba1a47a9e53)
DeltaFile
+5-5src/opnsense/mvc/app/views/OPNsense/Firewall/firewall_migration.volt
+5-51 files

OPNSense/core a1404a2src/opnsense/mvc/app/views/OPNsense/Firewall firewall_migration.volt

Firewall: Rules: Migration assistant: Fix typos and improve clarity in migration instructions
DeltaFile
+5-5src/opnsense/mvc/app/views/OPNsense/Firewall/firewall_migration.volt
+5-51 files

LLVM/project 689f978mlir/lib/Dialect/MLProgram/Transforms BufferizableOpInterfaceImpl.cpp, mlir/test/Dialect/MLProgram one-shot-bufferize.mlir

[ml_program] fix bufferizesToMemoryRead for ml_program.global_store (#177387)

This is a fix for the `BufferizableOpInterface` implementation for
`ml_program.global_store`.

`bufferizesToMemoryRead` currently returns false for
`GlobalStoreOpInterface`, but I believe it should return true as
`ml_program.global_store` needs to read its input buffer to know what
value to store to global.

This manifested in a bug where `one-shot-bufferize` would produce MLIR
that copies uninitialized data to the global var instead of the intended
value to be stored.

For the following MLIR:

```
module {
  ml_program.global private mutable @"state_tensor"(dense<0.0> : tensor<4x75xf32>) : tensor<4x75xf32>

    [61 lines not shown]
DeltaFile
+31-0mlir/test/Dialect/MLProgram/one-shot-bufferize.mlir
+1-1mlir/lib/Dialect/MLProgram/Transforms/BufferizableOpInterfaceImpl.cpp
+32-12 files

FreeBSD/ports 0bb32f6math/scilab Makefile

math/scilab: pin to java 8

Does not build with jdk11+.

[javac] /wrkdirs/usr/ports/math/scilab/work/scilab-6.1.1/modules/graphic_objects/src/java/org/scilab/modules/graphic_objects/xmlloader/CSSParser.java:17: error: package javax.annotation does not exist

PR:     272855
Approved-by:    no maintainer
DeltaFile
+1-0math/scilab/Makefile
+1-01 files

LLVM/project 51b8d45llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp

[AMDGPU][NFC] Refine the representation of MODE register values.

- Eliminate the field masks.
- Segregate the encoding logic.
- Simplify and clarify the user code.

This is supposed to help updating downstream branches where we
have a more advanced version of the same facility.
DeltaFile
+55-56llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+55-561 files

LLVM/project de8126dclang/lib/AST/ByteCode Interp.h, clang/test/AST/ByteCode c.c

[clang][bytecode] Fix mulc/divc op for IntegralAP types (#177565)

We need to allocate those.

Fixes https://github.com/llvm/llvm-project/issues/176740
DeltaFile
+23-1clang/lib/AST/ByteCode/Interp.h
+8-0clang/test/AST/ByteCode/c.c
+31-12 files

OPNSense/plugins 2b44156dns/ddclient Makefile

dns/ddclient: small bump for now
DeltaFile
+1-0dns/ddclient/Makefile
+1-01 files

OPNSense/plugins 4800383. LICENSE

LICENSE: sync
DeltaFile
+1-0LICENSE
+1-01 files

OPNSense/plugins d2024adnet/frr pkg-descr Makefile, net/frr/src/etc/rc.syshook.d/carp 50-frr

net/frr: sync with master
DeltaFile
+2-1net/frr/src/etc/rc.syshook.d/carp/50-frr
+1-0net/frr/pkg-descr
+1-0net/frr/Makefile
+4-13 files

OPNSense/plugins bc76f27net/frr Makefile pkg-descr, net/frr/src/etc/rc.syshook.d/carp 50-frr

net/frr: sync with master
DeltaFile
+2-1net/frr/src/etc/rc.syshook.d/carp/50-frr
+1-0net/frr/Makefile
+1-0net/frr/pkg-descr
+4-13 files

OPNSense/plugins b879d7bnet/frr pkg-descr

net/frr: annotate fix
DeltaFile
+1-0net/frr/pkg-descr
+1-01 files

OPNSense/plugins 48b4168net/frr Makefile

net/frr: fix hang in carp start hook
DeltaFile
+1-0net/frr/Makefile
+1-01 files

OPNSense/plugins 7de2634net/isc-dhcp pkg-descr Makefile, net/isc-dhcp/src/etc/inc/plugins.inc.d dhcpd.inc

net/isc-dhcp: small change for #5164
DeltaFile
+4-2net/isc-dhcp/src/etc/inc/plugins.inc.d/dhcpd.inc
+1-1net/isc-dhcp/src/www/services_dhcpv6.php
+1-1net/isc-dhcp/src/www/services_dhcp.php
+1-0net/isc-dhcp/pkg-descr
+1-0net/isc-dhcp/Makefile
+8-45 files

FreeBSD/src 498fe07sys/sys buf_ring.h

buf_ring: Rename some variables

The elements we store in buffer rings are buffers, so refer to them as
`buf` throughout instead of a mixture of `buf`, `ret`, and `new`,
especially since the latter breaks C++ code that directly or indirectly
includes this header.

MFC after:      1 week
Sponsored by:   Klara, Inc.
Sponsored by:   NetApp, Inc.
Reviewed by:    siderop1_netapp.com, markj
Differential Revision:  https://reviews.freebsd.org/D54827
DeltaFile
+5-7sys/sys/buf_ring.h
+5-71 files

OPNSense/core 4516d41src/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Firewall: Rules [new]: Escape selector in rule_protocol (#9642)

(cherry picked from commit b3fa25ee01d7b3050cb1a0149236901fbb20ea82)
DeltaFile
+5-3src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+5-31 files

OPNSense/core 4f784d0src/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Firewall: Rules [new]: Escape selector in rule_protocol (#9642)

(cherry picked from commit b3fa25ee01d7b3050cb1a0149236901fbb20ea82)
DeltaFile
+5-3src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+5-31 files

OPNSense/core d398482src/etc/inc/plugins.inc.d hostwatch.inc

Interfaces: Neighbors: Automatic Discovery - add xmlrpc registration, closes https://github.com/opnsense/core/issues/9628

(cherry picked from commit 63c3fe33f6b734373fa6a20a6843456843721bdf)
DeltaFile
+12-0src/etc/inc/plugins.inc.d/hostwatch.inc
+12-01 files

OPNSense/core bfd819fsrc/opnsense/scripts/openvpn ovpn_service_control.php

openvpn: account for CARP status in start and restart cases as well (#9634)

(cherry picked from commit 0b7c06f3a6d86c362ab9c9d81b6220d0c5a29814)
DeltaFile
+11-7src/opnsense/scripts/openvpn/ovpn_service_control.php
+11-71 files

LLVM/project 074485cllvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[CodeGen][NPM] Disable Machine verifier at the end of default pipelines
DeltaFile
+4-8llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+3-6llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+0-3llvm/include/llvm/Passes/CodeGenPassBuilder.h
+7-173 files

LLVM/project 1b3fa6fllvm/lib/Transforms/Scalar LoopStrengthReduce.cpp

[CodeGen][LSR][NPM] Make LoopStrengthReduce pass preserve LCSSA
DeltaFile
+4-0llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+4-01 files

LLVM/project 65f16e0llvm/lib/Target/AMDGPU SILowerControlFlow.cpp, llvm/test/CodeGen/AMDGPU si-lower-control-flow-preserve-dom-tree.mir

[AMDGPU] Fix DomTree preservation in SILowerControlFlow when nodes are deleted
DeltaFile
+59-0llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
+5-0llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+64-02 files

LLVM/project d765e1ellvm/test/CodeGen/AMDGPU si-lower-control-flow-preserve-dom-tree.mir

review comments
DeltaFile
+37-31llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
+37-311 files

LLVM/project 4ea3fccllvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[CodeGen][NPM] Specify Loop pass adaptor to not use MSSA
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+2-2llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+2-1llvm/include/llvm/Passes/CodeGenPassBuilder.h
+6-53 files

LLVM/project f5f8a49llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[AMDGPU][NPM] Complete fast regalloc pipeline
DeltaFile
+38-0llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+10-1llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+48-12 files

LLVM/project 1253a30llvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[CodeGen][NPM] Add "PhysicalRegisterUsageAnalysis" once
DeltaFile
+417-420llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+1-4llvm/include/llvm/Passes/CodeGenPassBuilder.h
+418-4242 files

FreeBSD/ports 98d61a3sysutils Makefile, sysutils/mdfried distinfo Makefile.crates

sysutils/mdfried: Add new port

Mdfried is a markdown viewer for the terminal that renders headers
as Bigger Text than the rest.

https://crates.io/crates/mdfried
DeltaFile
+983-0sysutils/mdfried/distinfo
+490-0sysutils/mdfried/Makefile.crates
+39-0sysutils/mdfried/Makefile
+2-0sysutils/mdfried/pkg-descr
+1-0sysutils/Makefile
+1,515-05 files

FreeBSD/ports 3042fe8devel/jiic/files build.xml

devel/jiic: support building with any jdk

Builds fine with jdk21.

PR:     292661
Approved-by:    ale@ (maintainer)
DeltaFile
+1-1devel/jiic/files/build.xml
+1-11 files

LLVM/project 854d088llvm/lib/CodeGen/SelectionDAG LegalizeFloatTypes.cpp LegalizeTypes.h

Delete the implementation functions
DeltaFile
+0-655llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+0-37llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+0-6922 files