[clang][ssaf] Add cpp-bounded-buffers source transformation (#210457)
Adds the first built-in transformation, `cpp-bounded-buffers`, which
rewrites buffers -- raw pointers and arrays -- into bounded types
(`bounded_ptr<T>`, `bounded_array<T, N>`) using the reachability
computed by `UnsafeBufferReachableAnalysis`.
The transformation collects every reachable pointer/array declarator and
function return declared in the translation unit, then either rewrites
it or records a SARIF note explaining why it did not. Shapes that are
not yet handled -- multi-level pointers, pointer to array, references to
pointers, multi-dimensional and unbounded arrays, multi-declarator
groups, macro-spelled declarators, and trailing return types -- are
reported rather than rewritten, and a final pass reports any reachable
entity that was neither rewritten nor otherwise accounted for. Edits are
validated and committed atomically, so a declarator whose edit cannot be
formed (such as a raw array of function pointers) is reported instead of
mangled.
[4 lines not shown]
workflows/release-binaries: Install Wix on Windows ARM64 (#217707)
Wix is used for generating the installer and is not installed by default
on Windows ARM64.
[MLIR][Python] Don't throw in PyDenseArrayIterator dunderNext
Signal iterator exhaustion via PyErr_SetNone(PyExc_StopIteration) instead
of throwing nanobind::stop_iteration(), matching the pattern used by the
other iterators in the Python bindings (see #175377). Raising a C++
exception to signal StopIteration incurs stack-unwinding cost on every
loop, which PyDenseArrayIterator was still paying. The return type changes
to nanobind::typed<nanobind::object, EltTy> so the method can return a null
object after setting the Python error indicator.
[RISCV] Merge RISCVISD::PMUL_H_B01 and RISCVISD::PMUL_W_H01. (#218046)
Same for RISCVISD::PMULU_H_B01/PMULU_W_H01 and
RISCVISD::PMULSU_H_B00/PMULSU_W_H00.
We can distquish by types, we don't need different nodes for each type.
ixgbe: Probe additional controller variants
The shared base code already selects and configures the 82598 BX,
82599 KR, 82599 SFP Express Module, X552 XFI, X553 QSFP, and X553 N
QSFP device IDs, but the FreeBSD probe table omits them while DPDK lists
them.
MFC after: 2 weeks
Sponsored by: BBOX.io
igb: Report 82580 memory ECC errors
82580 exposes clear-on-read, saturating corrected error counters for
the receive and transmit packet buffers. Its two PCIe command memories
expose RW1C indications for uncorrectable ECC errors.
Sample the packet buffer counters and PCIe indications from the regular
hardware statistics update. Fatal recovery samples the PCIe indications
from the serialized admin path rather than the interrupt filter. Thus,
either the regular statistics pass or recovery reads and clears each
indication, but they cannot both account it. Also preserve indications
observed while initialization is completing.
Expose the exact packet buffer error total and observed PCIe command
memory indications under the memory_errors sysctl node. Multiple PCIe
errors between samples can collapse into one indication per memory.
Validated on an Intel I340-T2 (82580, revision 1). A clean boot and
three down/up cycles left the packet-buffer, PCIe, and region-specific
[10 lines not shown]
e1000: Recover from 82580 memory errors
82580 reports fatal parity and uncorrectable ECC errors through ICR.FER
and its four region PEIND hierarchy. Region specific status registers
identify PCIe, DMA transmit, DMA receive, DMA host, and LAN port
memories that can leave traffic stopped.
Enable the documented DMA, PCIe, packet-buffer, and host-owned LAN
parity and ECC checks only after initializing queue and filter tables.
Leave the flexible filter parity controls under management firmware
ownership. Capture read-clear and RW1C status in the interrupt filter
and keep FER masked until the admin task resolves the event.
Reset for a host-owned region or an unknown FER source. Leave
management-only recovery to firmware. Use CTRL.RST before master
disable because fatal 82580 memory errors can stop PCIe traffic. Do not
use CTRL.DEV_RST: specification update item 9 declares that bit reserved
and says it must always be written as zero. Wait for EEPROM auto read
completion; STATUS bit 21 is reserved on 82580, not PF_RST_DONE.
[21 lines not shown]
[RISCV] Avoid fatal error for SiFive CLIC preemptible frame pointers (#217949)
SiFive CLIC `preemptible` interrupt handlers currently use `s0` to
preserve `mcause` and cannot be generated with a frame pointer. At
`-O0`, Clang enables frame pointers by default, causing the fatal error
to produce a backend crash report.
This commit switches to `DiagnosticInfoUnsupported` to emit a regular
source-located error and suggest considering `-fomit-frame-pointer`.
This does not change the existing code generation restriction.
Fixes https://github.com/llvm/llvm-project/issues/217936
[NewPM] Port LiveRangeShrink to the new pass manager
Follow the same pattern used for EHContGuardTargets and
CFGuardLongjmp: extract the pass body into a free function, rename
the legacy pass to LiveRangeShrinkLegacy, and add a
LiveRangeShrinkPass for the new pass manager. Register it in
MachinePassRegistry.def, replacing the DUMMY_MACHINE_FUNCTION_PASS
stub, and add the missing include to X86CodeGenPassBuilder.cpp,
which already called addMachineFunctionPass(LiveRangeShrinkPass(),
PMW) in its addPreRegAlloc.
Unlike EHContGuardTargets/CFGuardLongjmp, this pass is skippable
(runOnMachineFunction calls skipFunction), so the new-PM pass uses
OptionalPassInfoMixin rather than RequiredPassInfoMixin, matching
BreakFalseDepsPass.
Update llc-pipeline-npm.ll: the pass now prints its registered
"lrshrink" name instead of falling back to the raw C++ type name.
Add -enable-new-pm RUN lines to the three existing lrshrink tests;
[4 lines not shown]
[Clang] Remove dead code related to atomics (NFC) (#216614)
This PR cleans up dead code in `CGObjC.cpp` related to unaligned
atomics.
Because the synchronization strategy (native vs. objc_copyStruct) is
baked into the ABI for compiled frameworks, it can essentially never be
changed for existing architectures like x86 without breaking backwards
compatibility.
finance/fava: update to 1.30.16
Switch build system from setuptools to pep517.
Update dependencies: markdown2 replaced by markdown-it-py, remove
spurious pytest and requests runtime deps.
[LoopVectorize] Verify the function once per pass, not once per loop (#216448)
processLoop verifies the whole function once per vectorized loop, making
LoopVectorize quadratic in the number of loops per function on assertion
builds. In an `opt -O3` run the verifier accounts for 59% of the
instructions for a function with 800 vectorizable loops, and 5.6% for
SingleSource/Benchmarks/Linpack/linpack-pc.c.
Move the call to the end of runImpl. Assertion builds still verify what
LoopVectorize produces, but once per function instead of once per
vectorized loop, which costs 0.1-0.7% of the O3 run.
The call was added under DEBUG() in 2012 and became unconditional on
assertion builds in c9f63297e24a. 0aa75fb12faa hit the same problem in
SLPVectorizer and fixed it with EXPENSIVE_CHECKS (#48033).
[NewPM] Port CFGuardLongjmp to the new pass manager
Follow the same pattern used for EHContGuardTargets: extract the pass
body into a free function, rename the legacy pass to
CFGuardLongjmpLegacy, and add a CFGuardLongjmpPass for the new pass
manager. Register it in MachinePassRegistry.def and wire it into
X86's NewPM CodeGenPassBuilder pipeline (AArch64 and ARM do not yet
have a NewPM CodeGenPassBuilder).
The pass only adds post-instruction symbols and never modifies the
CFG, so mark it CFG-preserving in both the legacy getAnalysisUsage
override and the new-PM run() return value, matching the fix applied
to EHContGuardTargets in #217843.
Assisted-by: Claude Sonnet 5
[RISCV] Fix size of PseudoMERGE (#218171)
This can expand to two 4-byte instructions, so mark it as size 8.
Usually it will expand to just one 4-byte instruction.
This was found in #218170.
[NewPM] Port EHContGuardTargets to the new pass manager (#217843)
Adds a newPM pass for EHContGuardTargets (eh-cont-guard-targets).
- Extracts the pass's logic (which has no per-instance state) into a
shared runEHContGuardTargets free function, called by both the legacy
pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix, and (matching the same
convention already applied to CFIInstrInserter) renames
createEHContGuardTargetsPass() to createEHContGuardTargetsLegacy() at
all three legacy call sites (X86, AArch64, ARM).
- Adds the new pass manager pass EHContGuardTargetsPass, using
RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
calls skipFunction, so it always runs unconditionally and should not be
skippable in the new PM either.
- Updates MachinePassRegistry.def and PassBuilder.
- Wires the pass into X86's newPM pipeline, replacing an existing TODO
inside the already-correct TT.isOSWindows() conditional in
X86CodeGenPassBuilder.cpp. AArch64 and ARM have no newPM
[7 lines not shown]
workflows: Merge release-doxygen into release-documenation (#214366)
These two workflows use the same script and have the same structure,
so it's easier just to have one job that builds both.
