FreeBSD/ports 8a3448dmail/py-resend distinfo Makefile

mail/py-resend: Update to 2.26.0

Changelog: https://github.com/resend/resend-python/releases/tag/v2.26.0

Reported by:    portscout
DeltaFile
+3-3mail/py-resend/distinfo
+1-1mail/py-resend/Makefile
+4-42 files

LLVM/project da2d564llvm/lib/Target/Hexagon HexagonFrameLowering.cpp, llvm/test/CodeGen/Hexagon aligna-prologue-expansion.mir

Revert "[Hexagon] Fix use-before-def of AP register in prologue CSR spills (#…"

This reverts commit 3ef59d80c5ce51738a055d9e8eb98aa3c8effb2f.
DeltaFile
+0-92llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
+12-30llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+12-1222 files

LLVM/project 01b5b63llvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak-zero-siv-delta-signed-min.ll

[DA] Stop negating Delta in the Weak Zero SIV test
DeltaFile
+0-12llvm/lib/Analysis/DependenceAnalysis.cpp
+6-6llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-delta-signed-min.ll
+6-182 files

LLVM/project c4c6be9llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Remove absolute value calculations in the Weak Zero SIV tests
DeltaFile
+7-7llvm/lib/Analysis/DependenceAnalysis.cpp
+7-71 files

LLVM/project 6e49ff5clang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp, clang/test/CIR/CodeGenCUDA device-stub.cu

[CIR][CUDA] Handle CUDA module constructor and destructor emission.
DeltaFile
+121-2clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+41-0clang/test/CIR/CodeGenCUDA/device-stub.cu
+162-22 files

LLVM/project 207598allvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[DAG] Add command line option and TLI hook to enable DAG topological sorting (#188636)

The very first step towards #83422 - which will move DAG combines to be
processed in topological order.

There is a lot of churn on existing tests that need to be addressed
before this can be switched on globally, this patch gives the ability to
enable it both on a per-target basis, and via a command line option to
assist with testing and triage.

At the moment I'm focusing on addressing the x86 regressions (example in
the patch's basic test coverage) as that's the target I'm most familiar
with and will help with many other targets as well, but there might be
other/simpler targets that would benefit from earlier handling.
DeltaFile
+58-0llvm/test/CodeGen/X86/dag-topological-sort.ll
+18-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+5-0llvm/include/llvm/CodeGen/TargetLowering.h
+81-23 files

LLVM/project 929e072llvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak-zero-siv-addrec-wrap.ll

[DA] Add nsw check for addrecs in the Weak Zero SIV tests (#185579)

Check that the addrec has `nsw` in the Weak Zero SIV tests, as their
algorithm rely on the addrecs don't wrap.
Fix the test cases added in #185578 .
DeltaFile
+31-16llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-addrec-wrap.ll
+3-0llvm/lib/Analysis/DependenceAnalysis.cpp
+34-162 files

LLVM/project afd3ad4clang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp

fix twine crashes
DeltaFile
+5-6clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+5-61 files

LLVM/project 552e68dlldb/packages/Python/lldbsuite/test/builders builder.py

[lldb][test] Don't treat 'xcrun clang' as a path for finding clang++ (#188235)

[lldb][test] Don't treat 'xcrun clang' as a path for finding clang++
TestPrintObjectArray.py uses `xcrun clang` as the test compiler.
This is because the test source requires some Objective-C features
that are only available in downstream clang:

```
self.build(dictionary=[...], compiler="xcrun clang")
```

However, this currently just results in us running `clang++`
instead of `xcrun clang++` to compile test sources. If the downstream
`clang++` in PATH is not Apple's downstream version, this then causes
the tests to fail with compilation errors:

```
clang++: error: unknown argument: '-fno-constant-nsnumber-literals'
clang++: error: unknown argument: '-fno-constant-nsarray-literals'

    [6 lines not shown]
DeltaFile
+6-1lldb/packages/Python/lldbsuite/test/builders/builder.py
+6-11 files

FreeBSD/ports 87e6df1devel/py-cfn-lint distinfo Makefile, devel/py-cfn-lint/files patch-pyproject.toml

devel/py-cfn-lint: Update to 1.47.1

ChangeLog:      https://github.com/aws-cloudformation/cfn-lint/compare/v1.45.0...v1.47.1
Approved by:    hrs (mentor, blanket)
DeltaFile
+3-3devel/py-cfn-lint/distinfo
+3-3devel/py-cfn-lint/files/patch-pyproject.toml
+1-1devel/py-cfn-lint/Makefile
+7-73 files

FreeBSD/ports ca2421ddevel/py-aws-sam-translator distinfo Makefile

devel/py-aws-sam-translator: Update to 1.108.0

ChangeLog:      https://github.com/aws/serverless-application-model/releases/tag/v1.108.0
Approved by:    hrs (mentor, blanket)
DeltaFile
+3-3devel/py-aws-sam-translator/distinfo
+2-1devel/py-aws-sam-translator/Makefile
+5-42 files

LLVM/project 8e9e922libclc/opencl/lib/generic/atomic atomic_fetch_add.cl atomic_fetch_sub.cl

libclc: Fix missing overloads for atomic_fetch_add/sub (#188478)
DeltaFile
+65-8libclc/opencl/lib/generic/atomic/atomic_fetch_add.cl
+65-8libclc/opencl/lib/generic/atomic/atomic_fetch_sub.cl
+130-162 files

LLVM/project f8416c8llvm/include/llvm/ADT GenericUniformityImpl.h GenericSSAContext.h, llvm/lib/Analysis UniformityAnalysis.cpp

[UniformityAnalysis] Replace DivergentValues with UniformValues for conservative divergence queries (#180509)

This patch replaces DivergentValues with UniformValues as the single
source of truth for tracking divergence in UniformityInfo.

Old model: DivergentValues starts empty; values are added as divergence
is propagated. isDivergent(V) returns DivergentValues.count(V).

New model: UniformValues starts fully populated (all
instructions/arguments for IR, all register defs for MIR) during
initialize(). Values are removed as divergence is propagated.
isDivergent(V) returns !UniformValues.contains(V), so any value not
present in the set (e.g., a newly created instruction that was not
present during analysis) is conservatively treated as divergent. This
avoids silent miscompilations when transformation passes introduce new
values and query their uniformity.

---------

Co-authored-by: padivedi <padivedi at amd.com>
DeltaFile
+53-42llvm/include/llvm/ADT/GenericUniformityImpl.h
+95-0llvm/unittests/Target/AMDGPU/UniformityAnalysisTest.cpp
+59-24llvm/lib/Analysis/UniformityAnalysis.cpp
+14-0llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+6-0llvm/include/llvm/ADT/GenericSSAContext.h
+3-3llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform.mir
+230-696 files not shown
+243-7612 files

NetBSD/src A5Ftti0usr.sbin/tprof tprof.8

   tprof.8: document the lack of relationship with AIX tprof

   cf. https://www.ibm.com/docs/en/aix/7.2.0?topic=t-tprof-command
VersionDeltaFile
1.31+6-2usr.sbin/tprof/tprof.8
+6-21 files

LLVM/project 0959a2allvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/AArch64 memmove-inline.ll

Enable generic overlapping optimization for memmove (#177885)

Fixes: #165948
DeltaFile
+601-1,016llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
+334-131llvm/test/CodeGen/RISCV/memmove.ll
+269-0llvm/test/CodeGen/AArch64/memmove-inline.ll
+61-9llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+8-14llvm/test/CodeGen/AMDGPU/memmove-scalar-load.ll
+2-4llvm/test/CodeGen/X86/volatile-memstores-nooverlapping-load-stores.ll
+1,275-1,1746 files

FreeBSD/ports 7fab0cdeditors/zed distinfo Makefile.crates, editors/zed/files patch-crates_fs_src_fs.rs patch-crates_gpui_src_elements_div.rs

editors/zed: Update to 0.229.0

Changelog:
- https://github.com/zed-industries/zed/releases/tag/v0.228.0
- https://github.com/zed-industries/zed/releases/tag/v0.229.0

Reported by:    GitHub (watch releases)
DeltaFile
+79-47editors/zed/distinfo
+84-10editors/zed/files/patch-crates_fs_src_fs.rs
+89-0editors/zed/files/patch-crates_gpui_src_elements_div.rs
+64-0editors/zed/files/patch-crates_gpui_src_interactive.rs
+38-22editors/zed/Makefile.crates
+38-0editors/zed/files/patch-crates_image__viewer_src_image__viewer.rs
+392-7912 files not shown
+484-11418 files

LLVM/project 013cf4fclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 bf16-getset-intrinsics.c

[CIR][AArch64] Support BF16 Neon types and lower vdup lane builtins (#187460)

Part of https://github.com/llvm/llvm-project/issues/185382.

Lower:
-
[vdup_n_bf16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_bf16)
-
[vdupq_n_bf16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_bf16)
-
[vdup_lane_bf16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_bf16)
-
[vdupq_lane_bf16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_bf16)
-
[vdup_laneq_bf16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_bf16)
-
[vdupq_laneq_bf16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_bf16)

and add tests in

    [93 lines not shown]
DeltaFile
+96-10clang/test/CodeGen/AArch64/neon/bf16-getset.c
+0-76clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
+28-6clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+124-923 files

NetBSD/src HpaHkl9sys/uvm uvm_swap.c uvm_pager.c

   fix swap encryption data corruption issue

   when paging out, uvm_swap_io encrypts the page contents in-place
   and then issues write requests to swapdev. if the write fails
   for some reason, the pageout will be cancelled. but it leaves
   the data in the pages encrypted. ie. data corruption. note that
   this doesn't necessarily involve broken swap devices. as we are
   in the pagedaemon context, some kind of transient errors are
   rather normal. for example, ffs VOP_BMAP has special cases for
   the pagedaemon to return ENOMEM.

   this commit fixes the issue by simply reverting the encryption
   on error.

   PR/60082
   https://gnats.netbsd.org/60082
VersionDeltaFile
1.222+90-70sys/uvm/uvm_swap.c
1.135+27-7sys/uvm/uvm_pager.c
1.30+2-1sys/uvm/uvm_swap.h
+119-783 files

NetBSD/src fnN40OHsys/uvm uvm_swap.c

   uvm_swap.c: add a few assertions
VersionDeltaFile
1.221+14-0sys/uvm/uvm_swap.c
+14-01 files

NetBSD/src pkZVfZgsys/uvm uvm_swap.c

   simplify swap encryption a bit

   * disallow changes of vm.swap_encrypt sysctl when any swap
     is configured.  note: this doesn't affect the ability to
     set it in /etc/sysctl.conf because /etc/rc.d/sysctl is
     executed before /etc/rc.d/swap1.

   * retire per-page encryption tracking. (swd_encmap)
     from now on, the whole swap is encrypted or not.

   PR/60084
   https://gnats.netbsd.org/60084
VersionDeltaFile
1.220+45-48sys/uvm/uvm_swap.c
+45-481 files

LLVM/project f4b524cmlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp, mlir/test/Dialect/XeGPU move-gpu-func-to-warp-op.mlir

[mlir][XeGPU] Validate single-block requirement in MoveFuncBodyToWarpOp (#188471)

Add validation to ensure GPU function body has a single block before
applying the MoveFuncBodyToWarpOp transformation in XeGPU subgroup
distribution. This check prevents incorrect handling of multi-block GPU
functions. Fixes #185366.
DeltaFile
+22-0mlir/test/Dialect/XeGPU/move-gpu-func-to-warp-op.mlir
+4-0mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+26-02 files

LLVM/project b3b5395llvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis exact-siv-addrec-wrap.ll strong-siv-addrec-wrap.ll

[DA] Remove calls to the GCD MIV test from `testSIV`
DeltaFile
+9-19llvm/test/Analysis/DependenceAnalysis/exact-siv-addrec-wrap.ll
+9-19llvm/test/Analysis/DependenceAnalysis/strong-siv-addrec-wrap.ll
+9-16llvm/test/Analysis/DependenceAnalysis/infer_affine_domain_ovlf.ll
+12-12llvm/test/Analysis/DependenceAnalysis/run-specific-dependence-test.ll
+4-8llvm/lib/Analysis/DependenceAnalysis.cpp
+2-2llvm/test/Analysis/DependenceAnalysis/exact-siv-overflow.ll
+45-762 files not shown
+47-788 files

LLVM/project ad2e142llvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak-zero-siv-addrec-wrap.ll

[DA] Add nsw check for addrecs in the Weak Zero SIV tests
DeltaFile
+31-16llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-addrec-wrap.ll
+3-0llvm/lib/Analysis/DependenceAnalysis.cpp
+34-162 files

LLVM/project dc14111clang/lib/Headers __clang_spirv_libdevice_declares.h CMakeLists.txt, clang/lib/Headers/openmp_wrappers __clang_openmp_device_functions.h

[OFFLOAD] Introduce libdevice function declarations for future use for math OpenMP wrappers (#182215)

The purpose of this PR is to introduce libdevice functions declarations
for SPIRV for future use for math wrappers in order to reduce the PR
size
DeltaFile
+142-0clang/lib/Headers/__clang_spirv_libdevice_declares.h
+14-0clang/lib/Headers/openmp_wrappers/__clang_openmp_device_functions.h
+1-0clang/lib/Headers/CMakeLists.txt
+157-03 files

FreeBSD/ports 4fd8a0dcad/symbiyosys distinfo Makefile

cad/symbiyosys: Update 0.60 => 0.63

Approved by:            yuri@ (maintainer, Mentor)
Approved by:            db@, yuri@ (Mentors, implicit)
Differential Revision:  https://reviews.freebsd.org/D56074
DeltaFile
+3-3cad/symbiyosys/distinfo
+1-1cad/symbiyosys/Makefile
+4-42 files

FreeBSD/src aed3bc8sys/ofed/include/rdma ib_mad.h

ofed: Fix a typo in a source code comment

- s/refereced/referenced/

MFC after:      3 days
DeltaFile
+1-1sys/ofed/include/rdma/ib_mad.h
+1-11 files

FreeBSD/src 8bc31c8sys/net if_types.h

if_types: Fix a typo in a source code comment

- s/Circiut/Circuit/

Obtained from:  OpenBSD
MFC after:      3 days
DeltaFile
+1-1sys/net/if_types.h
+1-11 files

LLVM/project 8179135clang/include/clang/CIR MissingFeatures.h, clang/include/clang/CIR/Interfaces CIROpInterfaces.td

update CIRGlobalValueInterface for section
DeltaFile
+16-0clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
+2-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+0-1clang/include/clang/CIR/MissingFeatures.h
+18-43 files

LLVM/project 669632cclang/lib/CIR/CodeGen/Targets AMDGPU.cpp, clang/test/Analysis ctu-main.cpp

Merge branch 'main' into users/kasuga-fj/da-weak-zero-siv-add-nsw-check
DeltaFile
+290-378llvm/test/CodeGen/X86/srem-vector-lkk.ll
+624-0llvm/test/CodeGen/AMDGPU/ctls.ll
+285-101llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
+138-248llvm/test/CodeGen/X86/urem-vector-lkk.ll
+255-0clang/lib/CIR/CodeGen/Targets/AMDGPU.cpp
+0-249clang/test/Analysis/ctu-main.cpp
+1,592-976599 files not shown
+11,654-6,682605 files

LLVM/project 2d10261clang/include/clang/CIR MissingFeatures.h, clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR][CIRGen] Support for section atttribute
DeltaFile
+26-13clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+20-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+14-0clang/test/CIR/CodeGen/global-section.c
+7-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+0-1clang/include/clang/CIR/MissingFeatures.h
+67-185 files