LLVM/project 9502925orc-rt/unittests SessionTest.cpp CommonTestUtils.h

[orc-rt] De-duplicate some test helper APIs. (#187187)

Moves noErrors, mockExecutorProcessInfo, and NoDispatcher into
CommonTestUtils.h where they can be re-used between tests.
DeltaFile
+2-16orc-rt/unittests/SessionTest.cpp
+17-0orc-rt/unittests/CommonTestUtils.h
+2-14orc-rt/unittests/BootstrapInfoTest.cpp
+21-303 files

LLVM/project 9d43029clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVMIR.cpp, clang/test/CIR/CodeGenHIP amdgpu-module-flags.hip

Fix amendFunction and amendModule returns
DeltaFile
+19-10clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
+1-5clang/test/CIR/CodeGenHIP/amdgpu-module-flags.hip
+20-152 files

LLVM/project dc8fd02clang/test/CXX/drs cwg2947.cpp cwg14xx.cpp

[clang] Reshuffle compiler options in C++ DR tests

This patch changes the order of compiler options on RUN lines so that options that differ in length (like -verify with its multiple prefixes) are at the end. This way it's much easier to see what is common and what is different between RUN lines
DeltaFile
+27-27clang/test/CXX/drs/cwg2947.cpp
+14-14clang/test/CXX/drs/cwg14xx.cpp
+7-7clang/test/CXX/drs/cwg12xx.cpp
+7-7clang/test/CXX/drs/cwg13xx.cpp
+7-7clang/test/CXX/drs/cwg158.cpp
+7-7clang/test/CXX/drs/cwg15xx.cpp
+69-6935 files not shown
+311-31141 files

LLVM/project ee0ac74mlir/include/mlir/Dialect/X86 Transforms.h, mlir/include/mlir/Dialect/X86/TransformOps X86TransformOps.td

[mlir][x86] Lower packed type vector.contract to AMX dot-product (#182810)

A transform pass to lower `vector.contract` operation to (a)
`amx.tile_mulf` for BF16, or (b) `amx.tile_muli` for Int8 packed types.
DeltaFile
+1,034-0mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
+675-0mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
+11-0mlir/include/mlir/Dialect/X86/TransformOps/X86TransformOps.td
+6-0mlir/include/mlir/Dialect/X86/Transforms.h
+5-0mlir/lib/Dialect/X86/TransformOps/X86TransformOps.cpp
+1-0mlir/lib/Dialect/X86/Transforms/CMakeLists.txt
+1,732-06 files

LLVM/project 37d1e3dflang/lib/Lower/OpenMP ClauseProcessor.cpp, flang/test/Lower/OpenMP declare-simd.f90

[flang][mlir][OpenMP] Add linear modifier (val, ref, uval)

Add support for OpenMP linear modifiers `val`, `ref`, and `uval`
as defined in OpenMP 5.2 (5.4.6).
DeltaFile
+106-23mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+75-0mlir/test/Dialect/OpenMP/invalid.mlir
+71-0mlir/test/Dialect/OpenMP/ops.mlir
+54-6flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+43-2flang/test/Lower/OpenMP/declare-simd.f90
+16-0mlir/include/mlir/Dialect/OpenMP/OpenMPEnums.td
+365-318 files not shown
+409-5914 files

LLVM/project f4e64fdlld/ELF Writer.cpp, lld/test/ELF/linkerscript symbol-only-align.test nobits-offset.s

[ELF] Orphan placement: remove hasInputSections condition

https://reviews.llvm.org/D60131 (Change default output section type to
SHT_PROGBITS) caused a orphan placement regression for Fuchsia
`zircon.elf`: #40998 The orphan section `code_patch_table` was placed
before the first output section description `.text.boot0`, breaking the
address requirement.

https://reviews.llvm.org/D61197 (Fix getRankProximity to "ignore" not
live sections) fixed the regression by adding a `Live` condition (which
later became `hasInputSections`).

This condition added complexity, which turns out to be unneeded after

* 3bdc90e3ff4c9a18caeb3e6ad40fa5d15bbf9d5e ("[ELF] adjustOutputSections: update sortRank. NFC")
* 747d670baef35f0615b32652e93c97a2ff8dba18 ("[ELF] Make .interp/SHT_NOTE not special")
* #94099

The new orphan placement rule is slightly different (orphans can be

    [12 lines not shown]
DeltaFile
+5-11lld/ELF/Writer.cpp
+6-5lld/test/ELF/linkerscript/symbol-only-align.test
+1-1lld/test/ELF/linkerscript/nobits-offset.s
+1-1lld/test/ELF/linkerscript/tls-nobits-offset.s
+13-184 files

LLVM/project 2890f98offload/plugins-nextgen/level_zero/include L0Trace.h, offload/plugins-nextgen/level_zero/src L0Device.cpp

[OFFLOAD] Improve handling of synchronization errors in L0 plugin and reenable tests (#186927)

This change improves handling of errors during synchronization in Level
Zero plugin by ensuring cleanup of queues and events in case of an
synchronization error. As a result multiple tests stopped hanging.

---------

Co-authored-by: Duran, Alex <alejandro.duran at intel.com>
DeltaFile
+14-8offload/plugins-nextgen/level_zero/src/L0Device.cpp
+11-0offload/plugins-nextgen/level_zero/include/L0Trace.h
+1-2offload/test/api/omp_host_call.c
+1-2offload/test/sanitizer/ptr_outside_alloc_1.c
+1-2offload/test/sanitizer/ptr_outside_alloc_2.c
+1-2offload/test/libc/malloc_parallel.c
+29-1633 files not shown
+59-7439 files

LLVM/project 038c8d3llvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak-zero-siv-large-btc.ll weak-zero-siv-overflow.ll

[DA] Rewrite formula in the Weak Zero SIV tests (#183738)

This patch rewrites the formula in the Weak Zero SIV tests to match the
one used in the Strong SIV test that was updated in #179665. In this
form, `ConstantRange` is used so we don't need to pay attention to any
corner cases such as overflow.

Fix some test cases that were added in the past PRs to represent the
edge cases.
DeltaFile
+18-14llvm/lib/Analysis/DependenceAnalysis.cpp
+8-8llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll
+2-6llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-overflow.ll
+28-283 files

LLVM/project ce7fe20llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.umax.ll llvm.amdgcn.reduce.umin.ll

Rebase main + Remove compiler warning.
DeltaFile
+28-28llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+28-28llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+0-8llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+56-643 files

LLVM/project c909370llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.max.ll

Refactor Code:
Logical error in the code, was using the wrong register
to calculate some values.
DeltaFile
+34-34llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+114-1145 files not shown
+181-17111 files

LLVM/project 70933d1llvm/lib/Target/AMDGPU SIISelLowering.cpp

Add compiler warning
DeltaFile
+13-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+13-31 files

LLVM/project d063bd1llvm/lib/Target/AMDGPU SIISelLowering.cpp

Review comments and code cleanup.
DeltaFile
+18-27llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+18-271 files

LLVM/project 96b63c5llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

Overload `getVALUOp` to accept Opcodes as well.
DeltaFile
+26-26llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+26-26llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+2-26llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-8llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+67-865 files

LLVM/project bdd6039llvm/test/CodeGen/AMDGPU dynamic_stackalloc.ll llvm.amdgcn.reduce.sub.ll

[AMDGPU] DPP implementations for Wave Reduction

Adding DPP reduction support for i32 types.
Supported Ops: `umin`, `min`, `umax`, `max`,
`add`, `sub`, `and`, `or`, `xor`.
DeltaFile
+2,113-1,374llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+1,096-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,047-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+986-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+894-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+894-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+7,030-2,0108 files not shown
+11,269-2,82214 files

LLVM/project 5f6cd9bllvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis strong-siv-overflow.ll strong-siv-large-btc.ll

[DA] Fix overflow in symbolic RDIV test (#185805)

The symbolic RDIV test relies on computing the extremes of affine
expressions (e.g., `A1*N1` and `A2*N2`) to disprove dependencies. These
calculations were previously done using `SE->getMulExpr` and
`SE->getMinusSCEV` without guarding against signed integer overflow. If
large coefficients or loop bounds cause a wrap, `isKnownPredicate`
evaluates the wrapped values, potentially disproving a valid dependence
and leading to miscompilations.

This patch reimplements symbolicRDIVtest using `ConstantRange` to work
around overflows.

---------

Signed-off-by: Ruoyu Qiu <cabbaken at outlook.com>
Co-authored-by: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
DeltaFile
+11-102llvm/lib/Analysis/DependenceAnalysis.cpp
+10-18llvm/test/Analysis/DependenceAnalysis/strong-siv-overflow.ll
+10-17llvm/test/Analysis/DependenceAnalysis/strong-siv-large-btc.ll
+8-14llvm/test/Analysis/DependenceAnalysis/symbolic-rdiv-overflow.ll
+6-7llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
+3-6llvm/test/Analysis/DependenceAnalysis/symbolic-rdiv-addrec-wrap.ll
+48-1645 files not shown
+60-17911 files

LLVM/project 709ef15llvm/test/CodeGen/PowerPC bswap64.ll

[NFC][PowerPC] Pre-commit to optimize bswap64 builtin for power8 (#181776)

The current codegen (for power 8 targets specifically) does not make use
of the parallelism and does most of the operations sequentially.
This will be optimized in a future patch which will follow this NFC PR.
It will enhance the performance and also save us instructions.

---------

Co-authored-by: himadhith <himadhith.v at ibm.com>
DeltaFile
+41-0llvm/test/CodeGen/PowerPC/bswap64.ll
+41-01 files

LLVM/project 19c1eedmlir/include/mlir/Bindings/Python Globals.h, mlir/lib/Bindings/Python Globals.cpp

format
DeltaFile
+5-5mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
+1-2mlir/include/mlir/Bindings/Python/Globals.h
+2-1mlir/lib/Bindings/Python/Globals.cpp
+1-2mlir/python/mlir/ir.py
+0-1mlir/tools/mlir-tblgen/EnumPythonBindingGen.cpp
+9-115 files

LLVM/project 3a75683clang/bindings/python/clang cindex.py, clang/docs ReleaseNotes.rst

[libclang/python] Add type annotations to the TranslationUnit class (#180876)

This adds type annotations to the `TranslationUnit` class, enough to
pass a strict typecheck. This resolves 19 strict typing errors as the
next step towards https://github.com/llvm/llvm-project/issues/76664
DeltaFile
+67-31clang/bindings/python/clang/cindex.py
+2-0clang/docs/ReleaseNotes.rst
+69-312 files

LLVM/project 0f74f10mlir/include/mlir/Bindings/Python Globals.h, mlir/lib/Bindings/Python Globals.cpp IRCore.cpp

[mlir-python] Fix duplicate EnumAttr builder registration across dialects.

When multiple dialects share .td includes (e.g. affine includes arith),
each dialect's _*_enum_gen.py file registered attribute builders under
the same keys, causing "already registered" errors on the second import.

Two-pronged fix:

1. Add `allow_existing=True` to `register_attribute_builder` (and the
   underlying C++ `registerAttributeBuilder`). When set, silently skips
   registration if the key already exists (first-wins semantics). This
   handles EnumInfo-based builders (e.g. `AtomicRMWKindAttr`,
   `Arith_CmpFPredicateAttr`) that are emitted by every dialect whose
   .td file includes the defining file.

2. Filter EnumAttr-loop builders by `-bind-dialect` in
   `EnumPythonBindingGen.cpp` and register them under dialect-qualified
   keys (`"dialect.AttrName"`). Update `OpPythonBindingGen.cpp` to look
   up the same qualified keys for EnumAttr-typed op attributes (detected

    [5 lines not shown]
DeltaFile
+23-6mlir/tools/mlir-tblgen/EnumPythonBindingGen.cpp
+18-2mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
+10-6mlir/lib/Bindings/Python/Globals.cpp
+5-5mlir/test/mlir-tblgen/enums-python-bindings.td
+6-2mlir/include/mlir/Bindings/Python/Globals.h
+4-2mlir/lib/Bindings/Python/IRCore.cpp
+66-234 files not shown
+74-2910 files

LLVM/project 70665c6clang/test/CXX/drs cwg2947.cpp, clang/www cxx_dr_status.html

[clang] Update C++ DR status page
DeltaFile
+74-18clang/www/cxx_dr_status.html
+1-1clang/test/CXX/drs/cwg2947.cpp
+75-192 files

LLVM/project 8187875clang/lib/Driver/ToolChains Darwin.cpp, clang/test/Driver xcselect.c darwin-ld-platform-version-macos-nosdk.c

[clang][Driver][Darwin] Use `xcselect` for `*-apple-darwin*` targets too (#186683)

This is a follow-up to #119670. There, we introduced a CMake option
`CLANG_USE_XCSELECT`, which, when enabled, uses `libxcselect` to find
the right SDK to inject as an `-isysroot` flag when targeting
`*-apple-macos*`.

We intentionally left out `*-apple-darwin*` targets because it broke
many tests. This is unfortunate because `*-apple-darwin*` is the default
triple when building LLVM on macOS, so one isn't able to take advantage
of `xcselect` without an explicit `-target` flag or a change to the
toolchain's default target.

We fix this in two ways.

First, we move the injection of the `-isysroot` flag using `xcselect`
later, until after we are sure that we are targeting macOS. This avoids
confusing the earlier deployment target detection code when we inject
the macOS SDK but actually intended to target non-macOS.

    [3 lines not shown]
DeltaFile
+21-12clang/lib/Driver/ToolChains/Darwin.cpp
+30-3clang/test/Driver/xcselect.c
+0-17clang/test/Driver/darwin-ld-platform-version-macos-nosdk.c
+13-0clang/test/Driver/darwin-ld-platform-version-macos.c
+2-1clang/test/Driver/fsanitize-ignorelist.c
+2-1clang/test/Driver/darwin-builtin-modules.c
+68-341 files not shown
+70-347 files

LLVM/project a21c414clang/test/OpenMP target_teams_distribute_parallel_for_simd_schedule_codegen.cpp teams_distribute_parallel_for_simd_schedule_codegen.cpp, libc/AOR_v20.02/math/test/traces sincosf.txt exp.txt

Merge branch 'main' into users/kasuga-fj/da-rewrite-weak-zero-siv-formula
DeltaFile
+0-31,999libc/AOR_v20.02/math/test/traces/sincosf.txt
+0-16,000libc/AOR_v20.02/math/test/traces/exp.txt
+5,294-4,814clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+5,238-4,758clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+4,350-4,098clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
+4,004-3,524clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
+18,886-65,1934,105 files not shown
+247,605-244,4514,111 files

NetBSD/src NHnSCc7sys/arch/amiga/amiga locore.s, sys/arch/atari/atari locore.s

   Build m68k/m68k/trap_subr.s as a standalone file, remove yet more
   boilerplate from each m68k platform's locore.s
VersionDeltaFile
1.20+10-7sys/arch/m68k/m68k/trap_subr.s
1.131+1-6sys/arch/atari/atari/locore.s
1.55+1-6sys/arch/cesfic/cesfic/locore.s
1.202+1-6sys/arch/hp300/hp300/locore.s
1.98+1-6sys/arch/luna68k/luna68k/locore.s
1.176+1-6sys/arch/amiga/amiga/locore.s
+15-3710 files not shown
+26-9216 files

FreeBSD/ports 55f2678multimedia/pipewire pkg-plist, multimedia/pipewire/files patch-spa_include_spa_param_audio_raw-json.h patch-src_pipewire_context.c

multimedia/pipewire: update to 1.6.2

Reviewed by:    arrowd
Approved by:    lwhsu (mentor, implicitly)
Differential Revision:  https://reviews.freebsd.org/D55821
DeltaFile
+37-4multimedia/pipewire/pkg-plist
+28-0multimedia/pipewire/files/patch-spa_include_spa_param_audio_raw-json.h
+26-0multimedia/pipewire/files/patch-src_pipewire_context.c
+20-0multimedia/pipewire/files/patch-spa_include_spa_param_audio_layout-types.h
+0-19multimedia/pipewire/files/patch-spa_plugins_filter-graph_filter-graph.c
+14-0multimedia/pipewire/files/patch-spa_plugins_vulkan_vulkan-compute-utils.c
+125-2315 files not shown
+259-4021 files

FreeBSD/ports 5f92ed2multimedia/wireplumber pkg-plist Makefile, multimedia/wireplumber/files patch-lib_wp_log.c

multimedia/wireplumber: update to 0.5.13

Upstreamed patch: https://gitlab.freedesktop.org/pipewire/wireplumber/-/merge_requests/806

Reviewed by:    arrowd
Approved by:    lwhsu (mentor, implicitly)
Differential Revision:  https://reviews.freebsd.org/D55896
DeltaFile
+16-1multimedia/wireplumber/pkg-plist
+16-0multimedia/wireplumber/files/patch-lib_wp_log.c
+2-5multimedia/wireplumber/Makefile
+3-3multimedia/wireplumber/distinfo
+37-94 files

NetBSD/src k3izFvasys/arch/atari/atari locore.s intr.c, sys/arch/atari/include intr.h

   Remove the last vestigal remains of the simulated software interrupt
   register, or "ssir".  The NetBSD kernel long ago adopted a software
   interrupt thread model along with a "fast software interrupts" mechanism
   that m68k platforms do not (yet) implement, but a few m68k platforms
   were still consuling an "ssir" variable in the return from every exception
   that nothing ever set.

   This cleanup paves the way for futher consolidation of m68k trap handling
   code in future commits.
VersionDeltaFile
1.54+10-69sys/arch/cesfic/cesfic/locore.s
1.192+4-62sys/arch/mac68k/mac68k/locore.s
1.130+4-54sys/arch/atari/atari/locore.s
1.34+3-8sys/arch/mac68k/include/intr.h
1.26+3-6sys/arch/atari/include/intr.h
1.35+2-3sys/arch/atari/atari/intr.c
+26-2021 files not shown
+28-2057 files

LLVM/project ffcb574orc-rt/include/orc-rt BootstrapInfo.h Session.h, orc-rt/lib/executor BootstrapInfo.cpp Session.cpp

[orc-rt] Add BootstrapInfo: info for controller session bootstrap. (#187184)

BootstrapInfo holds information needed to bootstrap the ExecutionSession
in the controller. Future patches will update ControllerAccess to send
the bootstrap information at controller-connection time.

BootstrapInfo includes information about the executor process (via
Session::processInfo), an initial set of symbols (replacing
Session::controllerInterface()), and a simple key/value store.
DeltaFile
+152-0orc-rt/unittests/BootstrapInfoTest.cpp
+67-0orc-rt/include/orc-rt/BootstrapInfo.h
+52-0orc-rt/lib/executor/BootstrapInfo.cpp
+0-35orc-rt/unittests/SessionTest.cpp
+1-6orc-rt/lib/executor/Session.cpp
+0-5orc-rt/include/orc-rt/Session.h
+272-463 files not shown
+275-469 files

NetBSD/src veQJooLsys/arch/atari/vme if_le_vme.c

   splx() is defined to return (void).  Use _spl() directly here instead.
VersionDeltaFile
1.36+3-3sys/arch/atari/vme/if_le_vme.c
+3-31 files

LLVM/project c61d11dclang/include/clang/Basic riscv_vector.td, clang/lib/Sema SemaRISCV.cpp

[clang][RISCV] Add RequiredFeatures for zvknha and zvknhb (#186993)

zvknhb now implies zvknha so we dont need to check extensions manually
in SemaRISCV, we can just use RequiredFeatures instead.
DeltaFile
+13-5clang/include/clang/Basic/riscv_vector.td
+10-5clang/test/Sema/zvk-invalid-features.c
+0-12clang/lib/Sema/SemaRISCV.cpp
+23-223 files

LLVM/project 3a1d5b5clang/lib/Basic/Targets X86.h, clang/test/Sema x86-fixed-global-register.c

[X86] Support reserving EDI on x86-32 (#186123)

Which is under discussion in
https://github.com/llvm/llvm-project/issues/179036.
x86-64 support is added in
https://github.com/llvm/llvm-project/pull/180242.
Now add x86-32 support for reserving EDI via `-ffixed-edi` Update the
X86 backend to respect those reservations in register handling,
callee-save logic, and memcpy/memset lowering, and add driver/codegen
tests.

Add clang driver support for -ffixed-edi and map it to the reserve-edi
target feature on i386.

Teach the X86 backend to treat EDI as a user-reserved register in
register lookup, reserved-register tracking, and callee-save handling,
and avoid selecting REP MOVS/REP STOS when EDI is reserved.

Add driver, Sema, and codegen tests covering option handling, named

    [2 lines not shown]
DeltaFile
+63-0llvm/test/CodeGen/X86/reserveDIreg.ll
+36-0clang/test/Sema/x86-fixed-global-register.c
+25-1clang/lib/Basic/Targets/X86.h
+14-8llvm/lib/Target/X86/X86RegisterInfo.cpp
+16-5llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+3-5llvm/lib/Target/X86/X86ISelLowering.cpp
+157-197 files not shown
+180-2113 files