LLVM/project b93e243llvm/include/llvm/ExecutionEngine/Orc BacktraceTools.h

Remove LLVM_ABI from symbolicate declaration in BacktraceTools.h (#175764)

The class is already annotated with LLVM_ABI, so individual members shouldn't be.
DeltaFile
+1-1llvm/include/llvm/ExecutionEngine/Orc/BacktraceTools.h
+1-11 files

FreeNAS/freenas ff93701tests/api2 test_system_lifetime.py

Add 'limit' option to 'audit.query' call.

(cherry picked from commit adafbe2691e4ab1f68beca213b474a5c95985532)
DeltaFile
+1-0tests/api2/test_system_lifetime.py
+1-01 files

FreeNAS/freenas 14568cdtests/api2 test_system_lifetime.py

NAS-139298 / 26.04 / Add 'limit' option to 'audit.query' call. (#18018)

`audit.query` calls must include either a `count` or `limit` option,
else the test will fail.
Added the missing `limit` option for the `test_system_reboot` test in
`test_system_lifetime.py`
DeltaFile
+1-0tests/api2/test_system_lifetime.py
+1-01 files

LLVM/project 7c2f493offload/plugins-nextgen/amdgpu/dynamic_hsa hsa.cpp, offload/plugins-nextgen/amdgpu/src rtl.cpp

[OFFLOAD] Update CUDA and AMD plugins to new debug format (#175757)

This should be the last step before completely removing the DP macro.
DeltaFile
+8-4offload/plugins-nextgen/cuda/dynamic_cuda/cuda.cpp
+5-3offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
+4-4offload/plugins-nextgen/cuda/src/rtl.cpp
+3-3offload/plugins-nextgen/amdgpu/src/rtl.cpp
+1-1offload/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h
+21-155 files

LLVM/project 351d06amlir/include/mlir/Bindings/Python IRCore.h, mlir/lib/Bindings/Python IRCore.cpp IRAttributes.cpp

[MLIR][Python] Improve Iterator performance. Don't `throw` in `dunderNext` methods. (#175377)

In
https://github.com/llvm/llvm-project/pull/174139#issuecomment-3733259370
I wrote a scuffed benchmark that mostly iterates MLIR Container Types in
Python. My changes from that PR made the performance worse, so I closed
it.

However, when experimetning with that I also saw a large(?) performance
gain by changing the `dunderNext` methods of the various Iterators to
use `PyErr_SetNone(PyExc_StopIteration);` instead of `throw
nb::stop_iteration();`.

<details><summary>Benchmark attempt script</summary>

```python
import timeit

from mlir.ir import Context, Location, Module, InsertionPoint, Block, Region, OpView

    [93 lines not shown]
DeltaFile
+20-11mlir/lib/Bindings/Python/IRCore.cpp
+5-2mlir/lib/Bindings/Python/IRAttributes.cpp
+3-3mlir/include/mlir/Bindings/Python/IRCore.h
+28-163 files

LLVM/project 7581c70libcxx/include/__algorithm unwrap_iter.h

[libc++] Simplify __unwrap_iter a bit (#175153)

`__unwrap_iter` doesn't need to SFINAE away, so we can just check inside
the function body whether an iterator is copy constructible. This
reduces the overload set, improving compile times a bit.
DeltaFile
+8-10libcxx/include/__algorithm/unwrap_iter.h
+8-101 files

LLVM/project 403d8aaclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen/AArch64/sme-intrinsics acle_sme_str.c acle_sme_ldr.c

[AArch64][llvm] Improve codegen for svldr_vnum_za/svstr_vnum_za

When compiling `svldr_vnum_za` or `svstr_vnum_za`, the output
assembly has a superfluous `SXTW` instruction (gcc doesn't add
this); this should be excised, see https://godbolt.org/z/sz4s79rf8

In clang we're using int64_t, and `i32` in llvm. The extra `SXTW`
is due to a call to `DAG.getNode(ISD::SIGN_EXTEND...)`. Make them
both 64bit to make the extra `SXTW` go away.
DeltaFile
+56-62llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll
+56-62llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
+8-8llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5-6clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_str.c
+5-6clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ldr.c
+2-2clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+132-1461 files not shown
+133-1477 files

FreeBSD/ports ffc0586www/freenginx-devel Makefile Makefile.extmod

www/freenginx-devel: clean up the port infra

NJS_QJS knob and related patches have been removed a long time ago.
Do not bump PORTREVISION.

Sponsored by:   tipi.work
DeltaFile
+0-4www/freenginx-devel/Makefile
+0-2www/freenginx-devel/Makefile.extmod
+0-62 files

FreeNAS/freenas 9f38ac9src/middlewared/middlewared/scripts ctdb_ha_reclock.py

Fix reclock script
DeltaFile
+4-3src/middlewared/middlewared/scripts/ctdb_ha_reclock.py
+4-31 files

OpenBSD/ports iW1cDgFsecurity/vaultwarden distinfo crates.inc, security/vaultwarden/patches patch-modcargo-crates_webauthn-rs-core-0_5_4_src_crypto_rs patch-modcargo-crates_webauthn-rs-core-0_5_4_src_interface_rs

   Update to vaultwarden-1.35.2

   Changes:
   https://github.com/dani-garcia/vaultwarden/releases/tag/1.35.0
   https://github.com/dani-garcia/vaultwarden/releases/tag/1.35.1
   https://github.com/dani-garcia/vaultwarden/releases/tag/1.35.2

   Ed448 support in the WebAuthn framework has been patched out, as it is
   not supported by LibreSSL. Thanks to tb@ for this work.
   Enabled support for the S3 file backend. This feature was introduced in
   1.34.2 and should be stable enough.

   Add myself as co-maintainer.

   OK @aisha (maintainer), kirill@ (for initial patch)
VersionDeltaFile
1.30+620-496security/vaultwarden/distinfo
1.28+309-247security/vaultwarden/crates.inc
1.1+72-0security/vaultwarden/patches/patch-modcargo-crates_webauthn-rs-core-0_5_4_src_crypto_rs
1.1+23-0security/vaultwarden/patches/patch-modcargo-crates_webauthn-rs-core-0_5_4_src_interface_rs
1.1+12-0security/vaultwarden/patches/patch-modcargo-crates_webauthn-rs-core-0_5_4_src_internals_rs
1.1+10-0security/vaultwarden/patches/patch-modcargo-crates_webauthn-rs-core-0_5_4_build_rs
+1,046-7432 files not shown
+1,060-7468 files

OpenBSD/ports ExwdzASwww/vaultwarden-web Makefile distinfo, www/vaultwarden-web/pkg PLIST

   Update to vaultwarden-web-2025.12.1.3

   Changes:
   https://github.com/dani-garcia/bw_web_builds/compare/v2025.7.0...v2025.12.1+build.3

   Add myself as co-maintainer.

   OK @aisha (maintainer), kirill@ (for initial patch)
VersionDeltaFile
1.21+74-67www/vaultwarden-web/pkg/PLIST
1.23+4-3www/vaultwarden-web/Makefile
1.21+2-2www/vaultwarden-web/distinfo
+80-723 files

LLVM/project ed0eaa4llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 avx10_2bf16-fma.ll

[X86] Add bf16 support to isFMAFasterThanFMulAndFAdd for basic FMA optimizations (#172006)

This PR extends `isFMAFasterThanFMulAndFAdd` in `X86ISelLowering` to
handle
bfloat types. This enables basic FMA optimizations for bf16
operations on AVX10.2 targets.

Includes tests for scalar and vector bf16 cases:
- Scalar bf16 FMA lowering (AVX10.2 do not support scalar bf16
operations)
- Vector bf16 FMA fusion for 128-bit, 256-bit, and 512-bit widths
DeltaFile
+806-0llvm/test/CodeGen/X86/avx10_2bf16-fma.ll
+5-0llvm/lib/Target/X86/X86ISelLowering.cpp
+811-02 files

FreeNAS/freenas 352de58src/middlewared/middlewared/api/v26_04_0 pool_snapshottask.py

Fix periodic snapshot task model hierarchy
DeltaFile
+19-16src/middlewared/middlewared/api/v26_04_0/pool_snapshottask.py
+19-161 files

FreeBSD/ports 2374ca6math/R-cran-hdrcde distinfo pkg-plist

math/R-cran-hdrcde: upgrade to 3.5.0

Release notes at https://cran.r-project.org/web/packages/hdrcde/news/news.html
DeltaFile
+3-3math/R-cran-hdrcde/distinfo
+4-0math/R-cran-hdrcde/pkg-plist
+1-2math/R-cran-hdrcde/Makefile
+8-53 files

FreeBSD/ports 0d9fa6emath/frobby pkg-plist distinfo, math/frobby/files patch-Makefile

math/frobby: upgrade to v0.9.7

Release notes at https://github.com/Macaulay2/frobby/releases
DeltaFile
+964-842math/frobby/pkg-plist
+3-5math/frobby/distinfo
+4-4math/frobby/files/patch-Makefile
+2-6math/frobby/Makefile
+973-8574 files

FreeBSD/ports 024e45ddevel/py-guppy3 distinfo Makefile

devel/py-guppy3: upgrade to v3.1.6
DeltaFile
+3-3devel/py-guppy3/distinfo
+1-2devel/py-guppy3/Makefile
+4-52 files

LLVM/project 3a21ff2llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll

AMDGPU: Change ABI of 16-bit element vectors on gfx6/7

Fix ABI on old subtargets so match new subtargets, packing
16-bit element subvectors into 32-bit registers. Previously
this would be scalarized and promoted to i32/float.

Note this only changes the vector cases. Scalar i16/half are
still promoted to i32/float for now. I've unsuccessfully tried
to make that switch in the past, so leave that for later.

This will help with removal of softPromoteHalfType.
DeltaFile
+47,697-51,378llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+14,474-16,242llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+16,328-12,881llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+13,036-14,705llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+11,668-13,311llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+10,558-11,908llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+113,761-120,425151 files not shown
+200,130-204,067157 files

NetBSD/pkgsrc uPLunuxdoc CHANGES-2026

   doc: Updated devel/ruby-pkg-config to 1.6.5
VersionDeltaFile
1.299+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc OqSMylQdevel/ruby-pkg-config distinfo Makefile

   devel/ruby-pkg-config: update to 1.6.5

   1.6.5 (2025-12-01)

   Improvements

   * Improved pkgconf compatibility: Removed duplicated -D/-W flags.

        - ruby-gnome/pkg-config#43
        - Patch by takuya kodama

   Thanks

   * takuya kodama
VersionDeltaFile
1.44+4-4devel/ruby-pkg-config/distinfo
1.49+2-2devel/ruby-pkg-config/Makefile
+6-62 files

LLVM/project 186d520llvm/lib/CodeGen/GlobalISel CallLowering.cpp

GlobalISel: Fix mishandling vector-as-scalar in return values

This fixes 2 cases when the AMDGPU ABI is fixed to pass <2 x i16>
values as packed on gfx6/gfx7. The ABI does not pack values
currently; this is a pre-fix for that change.

Insert a bitcast if there is a single part with a different size.
Previously this would miscompile by going through the scalarization
and extend path, dropping the high element.

Also fix assertions in odd cases, like <3 x i16> -> i32. This needs
to unmerge with excess elements from the widened source vector.

All of this code is in need of a cleanup; this should look more
like the DAG version using getVectorTypeBreakdown.
DeltaFile
+24-2llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+24-21 files

LLVM/project ae2860ellvm/lib/Target/LoongArch LoongArchInstrInfo.td LoongArchExpandPseudoInsts.cpp, llvm/lib/Target/LoongArch/AsmParser LoongArchAsmParser.cpp

[llvm][LoongArch] Add call and tail macro instruction support

Link: https://sourceware.org/pipermail/binutils/2025-December/146091.html
DeltaFile
+43-14llvm/test/MC/LoongArch/Macros/macros-call.s
+21-15llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+21-10llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
+7-0llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+2-2llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+1-2llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+95-432 files not shown
+97-458 files

NetBSD/pkgsrc NDZABandoc CHANGES-2026

   doc: Updated devel/ruby-async to 2.35.2
VersionDeltaFile
1.298+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc teJTM7ldevel/ruby-async distinfo Makefile

   devel/ruby-async: update to 2.35.2

   2.35.0 (2025-11-30)

   * Process.fork is now properly handled by the Async fiber scheduler,
     ensuring that the scheduler state is correctly reset in the child process
     after a fork.  This prevents issues where the child process inherits the
     scheduler state from the parent, which could lead to unexpected behavior.

   2.35.1 (2026-01-02)

   * Fix incorrect handling of spurious wakeups in Async::Promise#wait, which
     could lead to premature (incorrect) resolution of the promise.

   2.35.2 (2026-01-11)

   * Improved handling of Process.fork on Ruby 4+.
   * Improve @promise state handling in Task#initialize, preventing incomplete
     instances being visible to the scheduler.
VersionDeltaFile
1.39+4-4devel/ruby-async/distinfo
1.43+2-2devel/ruby-async/Makefile
1.14+2-1devel/ruby-async/PLIST
+8-73 files

FreeNAS/freenas 265c2f9src/middlewared/middlewared/plugins sysdataset.py

Remove cifs restart from sysdataset
DeltaFile
+0-4src/middlewared/middlewared/plugins/sysdataset.py
+0-41 files

FreeNAS/freenas 338b400src/middlewared/middlewared/etc_files/ctdb ctdb.conf.mako nodes.mako, src/middlewared/middlewared/plugins etc.py smb.py

Add clustered SMB state

This commit adds working configuration for stateful SMB HA failover:
* reclock helper script - determines which node holds the cluster
  mutex lock based on presence of data pool system dataset.

* ctdb-related etc files. We can hard-code the nodes config based
  on our known HA nodes (this significantly eases past problems with
  gluster that we saw with dynamic nodes and ctdb stability).
DeltaFile
+82-0src/middlewared/middlewared/scripts/ctdb_ha_reclock.py
+22-0src/middlewared/middlewared/etc_files/ctdb/ctdb.conf.mako
+11-0src/middlewared/middlewared/utils/ctdb.py
+11-0src/middlewared/middlewared/etc_files/ctdb/nodes.mako
+11-0src/middlewared/middlewared/plugins/etc.py
+5-3src/middlewared/middlewared/plugins/smb.py
+142-33 files not shown
+152-49 files

LLVM/project c88cbafllvm/lib/Target/LoongArch LoongArchInstrInfo.td LoongArchMCInstLower.cpp, llvm/lib/Target/LoongArch/AsmParser LoongArchAsmParser.cpp

[llvm][LoongArch] Add call30 and tail30 macro instruction support (#175356)

Link:
https://sourceware.org/pipermail/binutils/2025-December/146091.html
DeltaFile
+52-12llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+15-1llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+14-1llvm/test/MC/LoongArch/Macros/macros-call.s
+2-2llvm/test/MC/LoongArch/Basic/Integer/invalid.s
+3-0llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp
+3-0llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCAsmInfo.cpp
+89-163 files not shown
+92-169 files

NetBSD/pkgsrc izDc8yBdoc CHANGES-2026

   doc: Updated devel/ruby-io-event to 1.14.2
VersionDeltaFile
1.297+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc gXZW98Ydevel/ruby-io-event distinfo Makefile

   devel/ruby-io-event: update to 1.14.2

   1.14.1 (2025-11-16)

   * Minor syntax tidy up.
   * Mark the thread from the worker pool. (#152)

   1.14.2 (2025-11-17)

   * Revert "Update ext/io/event/worker_pool.c"
   * Prefer self over poolval.
VersionDeltaFile
1.32+4-4devel/ruby-io-event/distinfo
1.34+2-2devel/ruby-io-event/Makefile
+6-62 files

LLVM/project e6bb35bllvm/test/CodeGen/AMDGPU bf16.ll llvm.exp2.bf16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel irtranslate-bf16.ll

AMDGPU: Directly use v2bf16 as register type for bf16 vectors.

Previously we were casting v2bf16 to i32, unlike the f16 case. Simplify
this by using the natural vector type. This is probably a leftover from
before v2bf16 was treated as legal. This is preparation for fixing a
miscompile in globalisel.
DeltaFile
+465-462llvm/test/CodeGen/AMDGPU/bf16.ll
+121-282llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
+122-133llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
+91-91llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+91-91llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+14-24llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
+904-1,0833 files not shown
+910-1,1009 files

NetBSD/pkgsrc o05LqSgdoc CHANGES-2026

   doc: Updated devel/ruby-i18n to 1.14.8
VersionDeltaFile
1.296+2-1doc/CHANGES-2026
+2-11 files