LLVM/project ed9178fllvm/test CMakeLists.txt

[Test] Add missing dependency for llvm-ordergen

Without this dependency, `llvm-ordergen` is not build when running the
tests only, resulting in failures for the tool.
DeltaFile
+1-0llvm/test/CMakeLists.txt
+1-01 files

LLVM/project 5101262llvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/CodeGen Rematerializer.cpp CalcSpillWeights.cpp

CodeGen: Pass instruction and operand index to isIgnorableUse (#219967)

Replace the MachineOperand argument to the TargetInstrInfo::isIgnorableUse hook 
with the containing instruction and operand index. The AMDGPU implementation only 
used the operand to recover its parent instruction, so this drops the dependence on 
MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+7-4llvm/lib/CodeGen/MachineSink.cpp
+7-4llvm/lib/CodeGen/MachineCSE.cpp
+3-3llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-3llvm/include/llvm/CodeGen/TargetInstrInfo.h
+2-1llvm/lib/CodeGen/Rematerializer.cpp
+2-1llvm/lib/CodeGen/CalcSpillWeights.cpp
+24-163 files not shown
+27-199 files

LLVM/project 3301803flang/test/Driver target-gpu-features.f90

[flang] No longer expect -target-cpu flag for AMDGPU targets

Update a failing test after
https://github.com/llvm/llvm-project/pull/206483.
DeltaFile
+0-1flang/test/Driver/target-gpu-features.f90
+0-11 files

LLVM/project 54d39dcllvm/lib/Target/PowerPC PPCReduceCRLogicals.cpp

PowerPC: Use use_instr_nodbg_begin in PPCReduceCRLogicals

Fetch the using instruction directly through the instruction iterator
instead of dereferencing an operand's parent.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+1-1llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
+1-11 files

LLVM/project 5245352llvm/docs AMDGPUMemoryModel.md AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUAnnotateUniformValues.cpp AMDGPUMemoryUtils.cpp

[AMDGPU] Make amdgpu.noclobber respect acquire operations

AMDGPUAnnotateUniformValues should annotate uniform global loads as
`!amdgpu.noclobber` if the memory they are reading is never clobbered (since
kernel launch) before the load is executed. That allows the backend to use
scalar `s_load_*` instructions instead of vector loads (which would otherwise
be illegal because the scalar cache is not kept coherent with the vector
cache).

So far, loads were annotated if the thread executing the load has not clobbered
the relevant memory location, but changes from concurrent threads that were
acquired via synchronization were ignored (which is unsound).

This patch defines a semantics for `!amdgpu.noclobber` metadata in the
AMDGPUUsage and changes AMDGPUAnnotateUniformValues to respect that semantics.
Now, loads are no longer annotated if they are atomic or if an acquire fence or
load can be executed before them (since they can read from stores in other
threads in these cases).


    [13 lines not shown]
DeltaFile
+288-280llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+42-51llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+24-12llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+12-0llvm/docs/AMDGPUUsage.rst
+7-0llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
+2-0llvm/docs/AMDGPUMemoryModel.md
+375-3436 files

LLVM/project 6e68218llvm/test/CodeGen/AMDGPU noclobber-barrier.ll

[AMDGPU] Add and generalize noclobber tests

Some noclobber tests included barrier-and-fence constructs that are unrelated
to what the tests are supposed to check. So far, that hasn't been an issue
because barriers and fences were ignored when inferring noclobber annotations.
However, fences do need to be considered for noclobber annotations (since they
can make clobbering stores from other threads visible in the considered
thread). This PR removes those unrelated barriers and fences so that the tests
will still be meaningful once a subsequent PR fixes the noclobber inference.
For the same reason, some `seq_cst` memory orderings in the tests are relaxed
to `monotonic`: `seq_cst` includes acquire semantics which can bring in
clobbering stores from other threads.

The PR also adds tests to cover more cases in the amdgpu.noclobber inference.
Some of them highlight more problematic cases in the current implementation
that subsequent PRs should fix.

The PR further regenerates all opt check lines via `update_test_checks.py`, so
that it's easier to keep them up to date.

    [2 lines not shown]
DeltaFile
+675-187llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+675-1871 files

OPNSense/core 60f3ed9src/opnsense/mvc/app/models/OPNsense/IPsec/FieldTypes IPsecProposalField.php

ipsec: shorten this a bit
DeltaFile
+4-4src/opnsense/mvc/app/models/OPNsense/IPsec/FieldTypes/IPsecProposalField.php
+4-41 files

LLVM/project 4aa9eadllvm/lib/CodeGen MachineInstr.cpp

CodeGen: Use use_instructions in changeDebugValuesDefReg (#219969)

The loop only inspects the using instruction, so iterate instructions
directly instead of operands and their parents.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+4-5llvm/lib/CodeGen/MachineInstr.cpp
+4-51 files

LLVM/project c600ef3llvm/test/Transforms/SLPVectorizer/X86 and-neg-pow2-copyable.ll

[SLP][NFC]Add a test with non-best vectorization of copyables, extended with identity value, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/219986
DeltaFile
+282-0llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
+282-01 files

OPNSense/core 4732880src/opnsense/service/templates/OPNsense/Syslog syslog-ng-local.conf, src/opnsense/service/templates/OPNsense/WebGui php.ini

system: audit log injection via login username in auth_log()

* prevent syslog.filter splitting our messages
* remove newlines when flushing out local files

PR: GHSA-jjm2-jg4p-3v9q
DeltaFile
+6-0src/opnsense/service/templates/OPNsense/Syslog/syslog-ng-local.conf
+1-0src/opnsense/service/templates/OPNsense/WebGui/php.ini
+7-02 files

FreeNAS/freenas d5adaac

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 1d5f4f7src/middlewared/middlewared/alert/source truenas_connect.py, src/middlewared/middlewared/plugins/truenas_connect heartbeat.py utils.py

NAS-141684 / 27.0.0-BETA.1 / Extend TNC heartbeat retry window to one week (#19567)

This commit adds changes to extend the TrueNAS Connect heartbeat retry
window from 48 hours to one week, so an outage or transient backend
problem lasting longer than two days no longer stops heartbeats
permanently. The threshold is now a named constant that the docstring
and the give-up log line derive from, and the alert text has been
corrected to match since it also stated the old figure.
DeltaFile
+6-4src/middlewared/middlewared/plugins/truenas_connect/heartbeat.py
+7-3src/middlewared/middlewared/plugins/truenas_connect/utils.py
+1-1src/middlewared/middlewared/alert/source/truenas_connect.py
+14-83 files

FreeBSD/ports a197121mail Makefile, mail/james distinfo pkg-descr

mail/james: Remove expired port

2026-06-30 mail/james: This is a version that is over 10 years old and has multiple vulnerabilities
DeltaFile
+0-195mail/james/files/james.in
+0-78mail/james/pkg-plist
+0-63mail/james/Makefile
+0-15mail/james/pkg-descr
+0-2mail/james/distinfo
+0-1mail/Makefile
+0-3541 files not shown
+1-3547 files

LLVM/project 8ba3300libsycl/src/detail device_image_wrapper.cpp, offload/liboffload/src OffloadImpl.cpp

[offload][sycl] add context parameter to olCreateProgram (#218387)

This patch is the 3rd patch in the context patch series. This change is
relatively simple compared to the others: we just introduce context to
the create program API and pass it down through the plugin interface to
the plugins.
DeltaFile
+37-13offload/unittests/OffloadAPI/program/olCreateProgram.cpp
+16-4offload/plugins-nextgen/level_zero/include/L0Program.h
+12-6offload/liboffload/src/OffloadImpl.cpp
+8-7offload/plugins-nextgen/level_zero/include/L0Device.h
+8-4libsycl/src/detail/device_image_wrapper.cpp
+7-3offload/plugins-nextgen/level_zero/src/L0Device.cpp
+88-3721 files not shown
+151-7327 files

FreeBSD/ports 081765b. MOVED, www Makefile

www/py-seafdav: Remove, was depending on removed net-mgmt/seafile-server

Reported by:    antoine
DeltaFile
+0-152www/py-seafdav/pkg-plist
+0-48www/py-seafdav/Makefile
+0-3www/py-seafdav/distinfo
+0-2www/py-seafdav/pkg-descr
+0-1www/Makefile
+1-0MOVED
+1-2066 files

LLVM/project b123e95llvm/lib/Target/AMDGPU AMDGPU.td

AMDGPU: Add visible features for aperture regs, doorbell ID and AGPR alloc

These fields are needed to migrate AMDGPUAttributor to using TargetParser
information instead of subtarget features.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+21-6llvm/lib/Target/AMDGPU/AMDGPU.td
+21-61 files

LLVM/project 87d449fllvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine icmp.ll

[InstCombine] Do not apply unsigned sub identities when flipping icmp strictness in `foldICmpBinOp` (#219904)

Folding `icmp ult A -nuw B, Op1 -> icmp ule A, Op1` may be unsound for
unsigned predicates with negative B, when the subtraction appears as a
`or disjoint`, previously matched as `add nuw`. nuw in `A + (-B)`
ensures that `A <u B` does not wrap unsigned, though the identity would
require proving `A >=u B` for the subtraction not to wrap. As the fold
relies on `NoOp0WrapProblem`, which proves the opposite of the latter,
simply avoid performing such an optimization.

Fixes: https://github.com/llvm/llvm-project/issues/218540.
DeltaFile
+44-0llvm/test/Transforms/InstCombine/icmp.ll
+13-6llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+57-62 files

OPNSense/core e2dbe04src/opnsense/mvc/app/models/OPNsense/IPsec/FieldTypes IPsecProposalField.php

ipsec: further reduce diff
DeltaFile
+0-3src/opnsense/mvc/app/models/OPNsense/IPsec/FieldTypes/IPsecProposalField.php
+0-31 files

OPNSense/core 0f18c29src/opnsense/mvc/app/models/OPNsense/IPsec/FieldTypes IPsecProposalField.php

ipsec: reduce diff
DeltaFile
+18-22src/opnsense/mvc/app/models/OPNsense/IPsec/FieldTypes/IPsecProposalField.php
+18-221 files

OPNSense/core 73f61fdsrc/opnsense/mvc/app/models/OPNsense/IPsec/FieldTypes IPsecProposalField.php

ipsec: further limit PQ options
DeltaFile
+44-57src/opnsense/mvc/app/models/OPNsense/IPsec/FieldTypes/IPsecProposalField.php
+44-571 files

LLVM/project d9d947fcompiler-rt/lib/sanitizer_common sanitizer_platform_limits_posix.h

Remove two declarations without definitions (#219511)

Commit 3dc4fd6d removed the definitions of struct_scc_modem_sz and
struct_scc_stat_sz, but left the declarations in a header. This patch
removes the leftovers.
DeltaFile
+0-2compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
+0-21 files

FreeNAS/freenas 3fcbc13src/middlewared/middlewared/plugins/rsync task.py

NAS-142605 / 27.0.0-BETA.1 / Specify rsync timeout (#19555)
DeltaFile
+7-2src/middlewared/middlewared/plugins/rsync/task.py
+7-21 files

NetBSD/pkgsrc 5SCnnLndoc CHANGES-2026

   doc: Updated net/openrsync to 0.20260730
VersionDeltaFile
1.5720+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc QTTNwgWnet/openrsync Makefile distinfo, net/openrsync/patches patch-compats.c patch-extern.h

   net/openrsync: update to openrsync-0.20260730

   Sync with upstream, pulling another year of commits.
   Noteworthy changes:
   * Many portability fixes (with specific regard to NetBSD)
   * Various bug fixes.
   * Several improvents merged from Apple.
   Refer to the github history for more details.
VersionDeltaFile
1.4+8-8net/openrsync/patches/patch-extern.h
1.7+6-6net/openrsync/distinfo
1.5+3-4net/openrsync/Makefile
1.2+3-3net/openrsync/patches/patch-compats.c
+20-214 files

LLVM/project f89861fllvm/lib/Target/SystemZ SystemZScheduleZ17.td

[SystemZ] Minor fixing in z17 SchedModel. (#219956)

A few insignificant updates to some opcodes.
DeltaFile
+3-4llvm/lib/Target/SystemZ/SystemZScheduleZ17.td
+3-41 files

LLVM/project 0b768f4clang/lib/Driver/ToolChains UEFI.cpp Solaris.cpp, clang/test/Driver fsanitize-undefined-device-offload.c

[Clang] Enable UBSan for AMDGPU device offload

Summary:
This enables the device UBSan runtime for AMDGPU decides. Primarily this
required modifications to the `addSanitizerRuntime` interface so we can
query the compilation's offload status. Also need to forward it through
the linker wrapper interface. Works on all AMDGPU offload, slight hacks
around the other targets as they do not advertise sanitizer
runtimes properly.

This is linked in via a new `-u __ubsan_device_initialize` hook to pull
in the side library. This is standard behavior and keeps the core logic
mostly unchanged and re-used.
DeltaFile
+50-0clang/test/Driver/fsanitize-undefined-device-offload.c
+32-3clang/lib/Driver/ToolChains/CommonArgs.cpp
+2-2clang/lib/Driver/ToolChains/Hexagon.cpp
+2-1clang/lib/Driver/ToolChains/Clang.cpp
+1-1clang/lib/Driver/ToolChains/UEFI.cpp
+1-1clang/lib/Driver/ToolChains/Solaris.cpp
+88-813 files not shown
+98-1819 files

OpenBSD/ports ORd1gYidevel/p5-Devel-Gladiator distinfo Makefile, devel/p5-Devel-Gladiator/pkg PLIST

   update p5-Devel-Gladiator to 0.08
VersionDeltaFile
1.3+2-2devel/p5-Devel-Gladiator/distinfo
1.11+2-2devel/p5-Devel-Gladiator/Makefile
1.5+1-1devel/p5-Devel-Gladiator/pkg/PLIST
+5-53 files

LLVM/project 37f1ab4mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp, mlir/test/Target/LLVMIR openmp-todo.mlir openmp-target-launch-device.mlir

Update logic with initSentinel and padTrailingDims
DeltaFile
+39-19mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+23-4mlir/test/Target/LLVMIR/openmp-target-launch-device.mlir
+25-2mlir/test/Target/LLVMIR/openmp-target-launch-host.mlir
+0-11mlir/test/Target/LLVMIR/openmp-todo.mlir
+87-364 files

LLVM/project f7d8632llvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Analysis/ScalarEvolution max-backedge-taken-count-guard-info.ll

[SCEV] Apply loop guards to Distance + 1 in howFarToZero. (#219944)

Apply loop guards on on `Distance + 1` before computing the unsinged
range. This improves results in a number of cases in practice, mostly
additional unrolling and some runtime check simplifications:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1138

Guards have already been collected on this code path, so applying them
is cheap.
Compile-time impact is in the noise:
https://llvm-compile-time-tracker.com/compare.php?from=918aa38d750cd40d4265c39817fb31efb628f7e1&to=33c51ea1c4748883dfef71bdd1007bd72ec9095f&stat=instructions:u

PR: https://github.com/llvm/llvm-project/pull/219944
DeltaFile
+194-0llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
+1-14polly/test/ScopInfo/multidim_fortran_srem.ll
+7-3llvm/lib/Analysis/ScalarEvolution.cpp
+1-1llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
+203-184 files

LLVM/project 41af3cacompiler-rt/lib/ubsan/device ubsan_device_symbolize.cpp hsa.h

[compiler-rt] Add AMDGPU Device UndefinedBehaviorSanitizer runtime

Summary:
This adds support for full UBSan on the AMDGPU target. The GPU build of
`compiler-rt` will now build `libclang_rt.ubsan_standalone.a` and the
host build will now provide `libclang_rt.ubsan_device.a` for the
host-side formatting.

The **core** approach is to simply gather arguments from the device and
replay them on the host. The RPC interface acts as the narrow shim to
pass data between the CPU and GPU.

The changes to the core runtime are kept minimal, only exposing a few
needed hooks to re-run and symbolize reports coming from an external
caller. The device archive is a side-library which will only be present
for GPU offloading builds.

Putting this in `compiler-rt` via interceptors avoids an ABI edge
between many consumers, (OpenMP, HIP, Pytorch, etc). The runtime code is

    [42 lines not shown]
DeltaFile
+364-0compiler-rt/lib/ubsan/device/ubsan_device_hsa.cpp
+279-0compiler-rt/lib/ubsan/device/ubsan_device_report.cpp
+233-0compiler-rt/lib/ubsan/device/ubsan_device_rpc.cpp
+199-0compiler-rt/lib/ubsan/device/ubsan_device_hsa_interceptors.cpp
+172-0compiler-rt/lib/ubsan/device/hsa.h
+148-0compiler-rt/lib/ubsan/device/ubsan_device_symbolize.cpp
+1,395-032 files not shown
+2,406-7938 files