LLVM/project a3e3fedllvm/include/llvm/CodeGen MachineCycleAnalysis.h TargetInstrInfo.h, llvm/lib/Target/AArch64 AArch64LoadStoreOptimizer.cpp

[CodeGen] Declare MachineCycleInfo in headers (#187494)

Transform MachineCycleInfo into a class that can be declared and remove
include from many source files.

Similar to 810ba55de9159932d498e9387d031f362b93fbea.
DeltaFile
+1-1llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
+1-1llvm/include/llvm/CodeGen/TargetInstrInfo.h
+1-0llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+1-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-0llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+5-25 files

FreeBSD/ports e2737dawww/gallery-dl distinfo Makefile

www/gallery-dl: update to 1.31.10

Changes:        https://github.com/mikf/gallery-dl/releases/tag/v1.31.10
Reported by:    GitHub (watch releases)

(cherry picked from commit f36b51f499c7d6398a9ce4c64c1ca703d5052423)
DeltaFile
+3-3www/gallery-dl/distinfo
+1-1www/gallery-dl/Makefile
+4-42 files

FreeBSD/ports f36b51fwww/gallery-dl distinfo Makefile

www/gallery-dl: update to 1.31.10

Changes:        https://github.com/mikf/gallery-dl/releases/tag/v1.31.10
Reported by:    GitHub (watch releases)
DeltaFile
+3-3www/gallery-dl/distinfo
+1-1www/gallery-dl/Makefile
+4-42 files

FreeNAS/freenas 299ee7esrc/middlewared/middlewared/alert/source zfs_tier.py, src/middlewared/middlewared/plugins/zfs tier.py

Fix alerts and validation
DeltaFile
+102-29src/middlewared/middlewared/alert/source/zfs_tier.py
+87-34src/middlewared/middlewared/plugins/zfs/tier.py
+189-632 files

LLVM/project 2e2bcf7llvm/lib/Target/AMDGPU AMDGPUInstrInfo.h

[AMDGPU] Remove unused forward declaration
DeltaFile
+0-1llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
+0-11 files

NetBSD/pkgsrc-wip 1aab0d7mattermost-server Makefile

mattermost: Remove duplicate .include
DeltaFile
+0-2mattermost-server/Makefile
+0-21 files

FreeNAS/freenas 1179277src/middlewared/middlewared/plugins/failover_ event.py, src/middlewared/middlewared/plugins/pool_ import_pool.py

fix PoolUpgraded alert
DeltaFile
+12-0src/middlewared/middlewared/plugins/pool_/import_pool.py
+6-4src/middlewared/middlewared/plugins/failover_/event.py
+18-42 files

FreeBSD/src d478715usr.bin/clang llvm.prog.mk

llvm: Link cross-tools with static libllvm.a

We generally use TOOLS_PREFIX being set to indicate that we are building
in the cross-build tools stage.  This check was missing for llvm.prog.mk
consumers other than *tblgen, which have not previously been built as
cross tools.

Reviewed by:    dim
Sponsored by:   The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D55930
DeltaFile
+1-1usr.bin/clang/llvm.prog.mk
+1-11 files

LLVM/project dddf01cllvm/lib/Target/RISCV RISCVInstrInfo.td RISCVInstrInfoXqci.td, llvm/lib/Target/RISCV/MCTargetDesc RISCVMCCodeEmitter.cpp RISCVAsmBackend.cpp

[RISCV] Relax out of range Zibi conditional branches (#186965)

If `.Label` is not within +-4KiB range, we convert

```
beqi/bnei reg, imm, .Label
```

to

```
bnei/beqi reg, imm, 8
j .Label
```

This is similar to what is done for the RISCV conditional branches
and `Xqcibi` conditional branches.

---------

Co-authored-by: Sudharsan Veeravalli <svs at qti.qualcomm.com>
DeltaFile
+110-0llvm/test/MC/RISCV/zibi-long-conditional-jump.s
+14-0llvm/lib/Target/RISCV/RISCVInstrInfo.td
+0-13llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+10-3llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+6-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+5-0llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
+145-161 files not shown
+148-187 files

LLVM/project 76f7252llvm/lib/CodeGen/SelectionDAG FastISel.cpp, llvm/test/CodeGen/X86 fake-use-fastisel.ll

[FastISel] generate FAKE_USE for llvm.fake.use (#187116)

FastISel was dropping llvm.fake.use because they are not meant to be
generated at O0 with clang.

This patch adds support in FastISel to generate FAKE_USE for llvm.fake.use.
The handling is simpler than in SelectionDagBuilder because no attempt is made to
get rid of useless FAKE_USE (e.g. for constant SSA values) to keep FastISel simple.

The motivation is that flang will generate llvm.fake.use for function arguments under
`-g` (and O0) because Fortran arguments are not copied to the stack (they are
reference like arguments in most cases) and one should be able to access these
variables from the debugger at any point of the function, even after their last use in the
function.
DeltaFile
+20-0llvm/test/CodeGen/X86/fake-use-fastisel.ll
+7-2llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+27-22 files

LLVM/project d641186clang/docs UsersManual.rst, clang/test/Driver cl-link.c

[clang-cl] test that `-Xlinker` works, update supported options docs (#187395)

closes #119179
DeltaFile
+709-95clang/docs/UsersManual.rst
+5-0clang/test/Driver/cl-link.c
+714-952 files

OPNSense/core 4bca318src/opnsense/mvc/app/views/OPNsense/Firewall alias.volt

firewall: match form style with apply button underneath for previous
DeltaFile
+8-7src/opnsense/mvc/app/views/OPNsense/Firewall/alias.volt
+8-71 files

LLVM/project a3f0a19llvm/lib/Target/AArch64 AArch64LoadStoreOptimizer.cpp, llvm/lib/Target/RISCV RISCVVLOptimizer.cpp

More include fixes

Created using spr 1.3.8-wip
DeltaFile
+1-0llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+1-0llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+2-02 files

LLVM/project 18ed1a9llvm/test/CodeGen/X86 bit-manip-i512.ll bit-manip-i256.ll

[X86] Add bitrevese/bswap i128/i256/i512 test coverage for #187353 (#187492)
DeltaFile
+2,986-1llvm/test/CodeGen/X86/bit-manip-i512.ll
+1,492-0llvm/test/CodeGen/X86/bit-manip-i256.ll
+459-0llvm/test/CodeGen/X86/bit-manip-i128.ll
+4,937-13 files

LLVM/project 78a8f00llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanConstruction.cpp

Revert "[VPlan] Create header phis once regions have been created (NFC)."

This reverts commit 91b928f919364b29e241821fc639b9ef56dab1a5.

This complicates some analysis that need the happen on the scalar VPlan,
before regions have been created, e.g.
https://github.com/llvm/llvm-project/pull/185323/.
DeltaFile
+9-11llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+6-1llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+15-122 files

FreeNAS/freenas d3076c3src/middlewared/middlewared/api/v25_04_1 user.py catalog.py, src/middlewared/middlewared/api/v25_04_2 user.py

Fix flake8 errors

This commit adds changes to fix flake8 errors present in the repo to simplify github action and avoid unnecessary complexity.
DeltaFile
+35-10src/middlewared/middlewared/plugins/dlm.py
+22-22src/middlewared/middlewared/api/v25_04_1/user.py
+22-22src/middlewared/middlewared/api/v25_04_2/user.py
+34-9src/middlewared/middlewared/plugins/iscsi_/targets.py
+29-10src/middlewared/middlewared/plugins/iscsi_/alua.py
+19-19src/middlewared/middlewared/api/v25_04_1/catalog.py
+161-92124 files not shown
+706-506130 files

NetBSD/pkgsrc-wip 03a9112mattermost-server Makefile

mattermost: Fix ldflags entry.
DeltaFile
+1-1mattermost-server/Makefile
+1-11 files

NetBSD/pkgsrc-wip 721a639mattermost-server Makefile DESCR

mattermost: Eye Candy.

Build errors reported upstream as
<https://github.com/mattermost/mattermost/issues/35690>.
DeltaFile
+5-4mattermost-server/Makefile
+1-1mattermost-server/DESCR
+6-52 files

LLVM/project 289c588llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 avx512-trunc.ll

[X86] Optimize load-trunc-store for v4i16/v2i32/v2i16 vectors (#186676)

This patch transform 
IR 
```
define void @cast_i16x4_to_u8x4(ptr %a0, ptr %a1) {
  %1 = load <4 x i16>, ptr %a1
  %2 = trunc <4 x i16> %1 to <4 x i8>
  store <4 x i8> %2, ptr %a0
  ret void
}
```
From Assembly
```
cast_i16x4_to_u8x4:                     # @cast_i16x4_to_u8x4
        vmovq   (%rsi), %xmm0                   # xmm0 = mem[0],zero
        vpmovwb %xmm0, %xmm0
        vmovd   %xmm0, (%rdi)
        retq

    [16 lines not shown]
DeltaFile
+119-0llvm/test/CodeGen/X86/avx512-trunc.ll
+22-0llvm/lib/Target/X86/X86ISelLowering.cpp
+141-02 files

LLVM/project 1078a1dllvm/lib/Transforms/InstCombine InstCombineAndOrXor.cpp, llvm/test/CodeGen/X86 bmi.ll

Lowering `~x | (x - 1)` to `~blsi(x)` (#186722)

Alive2 proof: 
https://alive2.llvm.org/ce/z/bK93Cn

I've implemented a fold in `InstCombineAndOrXor.cpp` to canonicalize `~x
| (x - 1)` to `~(x & -x)` which enables the CodeGen to emit the `blsi`
instruction.

I've also added a test in `CodeGen/X86`.

Fixes #184055

---------

Co-authored-by: Tim Gymnich <tim at gymni.ch>
DeltaFile
+68-0llvm/test/Transforms/InstCombine/fold-bmi.ll
+59-0llvm/test/CodeGen/X86/bmi.ll
+10-0llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+137-03 files

OPNSense/core 8dd012fsrc/opnsense/mvc/app/models/OPNsense/Kea/FieldTypes KeaOptionDataField.php

Fix int32 validator
DeltaFile
+6-2src/opnsense/mvc/app/models/OPNsense/Kea/FieldTypes/KeaOptionDataField.php
+6-21 files

OpenBSD/src HZ7zK5Jusr.sbin/bgpd config.c bgpd.c

   Implement imsg_send_config and imsg_recv_config which handle the
   sending of bgpd_config.

   struct bgpd_config includes various pointers and those should not be passed.
   Instead use an zeroed stack object and copy_config() to ensure that all
   pointers are NULL before passing the struct.
   Also implement imsg_recv_config() which does the reverse.

   Reported by Shibo, Shawn, Hugo, Systopia Team
   OK tb@
VersionDeltaFile
1.117+23-2usr.sbin/bgpd/config.c
1.288+4-9usr.sbin/bgpd/bgpd.c
1.691+5-6usr.sbin/bgpd/rde.c
1.529+4-5usr.sbin/bgpd/session.c
1.33+3-5usr.sbin/bgpd/rtr.c
1.538+4-2usr.sbin/bgpd/bgpd.h
+43-296 files

LLVM/project 1745706llvm/include/llvm/CodeGen MachineCycleAnalysis.h TargetInstrInfo.h, llvm/lib/Target/AMDGPU SIInstrInfo.cpp

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+1-1llvm/include/llvm/CodeGen/MachineCycleAnalysis.h
+1-1llvm/include/llvm/CodeGen/TargetInstrInfo.h
+1-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-23 files

NetBSD/pkgsrc Ja4q0Qzdoc CHANGES-2026

   doc: Updated www/php-nextcloud to 32.0.6
VersionDeltaFile
1.1792+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc jHLQ4Hfwww/php-nextcloud PLIST distinfo

   www/php-nextcloud: Update to 32.0.6

   This is 5 ~monthly micro updates; upstream has a long track record of
   stable micros.

   Tested on NetBSD 10 amd64 via nginx/fpm (the standard approach), both
   web interface and CalDAV.
VersionDeltaFile
1.68+2,205-1,885www/php-nextcloud/PLIST
1.71+4-4www/php-nextcloud/distinfo
1.85+2-2www/php-nextcloud/Makefile
+2,211-1,8913 files

NetBSD/src CNhj261sys/arch/sun3/sun3x locore.s

   Oops missed sun3x in previous changes:

   Now that all of the m68k copies of the "rei" function are functionally
   equivalent, pick the one that uses the fewest cycles in the "no AST
   pending" case and re-factor it into trap_subr.s.

   Re-factor badtrap into the shared trap_subr.s.  This time we pick the
   sun2/sun3 implementation of this trap stub because it provides more
   context to the stray trap reporting routine (adjust the N copies of
   straytrap() to compensate as needed, sigh).

   Re-factor trap0 (system calls) into trap_subr.s.  Here we pick the flavor
   that has the in-line astpending check bcause it's a few cycles faster in
   the (common) case where no AST is pending at the end of a system call.

   Re-factor trap12 ("cachectl") into trap_subr.s.  Already identical everywhere
   except for 68010, where it's a no-op.
VersionDeltaFile
1.81+1-99sys/arch/sun3/sun3x/locore.s
+1-991 files

LLVM/project 49a5192llvm/include/llvm/ADT GenericCycleImpl.h GenericCycleInfo.h

[CycleInfo] Don't store top-level cycle per block (#187488)

CycleInfo currently has a second map, that stores the top-level cycle
for a block. I don't think storing this per-block makes a lot of sense,
because the top-level cycle is always the same for all blocks in a
cycle.

So instead store it as a member of the cycle.
DeltaFile
+10-20llvm/include/llvm/ADT/GenericCycleImpl.h
+5-4llvm/include/llvm/ADT/GenericCycleInfo.h
+15-242 files

LLVM/project 7d02ca6mlir/include/mlir/Dialect/LLVMIR LLVMIntrinsicOps.td, mlir/test/Target/LLVMIR llvmir-intrinsics.mlir

[mlir][LLVM] add llvm.fake.use to LLVM dialect (#187026)

Add llvm.fake.use to the LLVM dialect intrinsics.
See https://llvm.org/docs/LangRef.html#llvm-fake-use-intrinsic.
DeltaFile
+14-0mlir/test/Target/LLVMIR/Import/intrinsic.ll
+12-0mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+5-0mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
+31-03 files

OPNSense/core 5d0fe33src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api AliasUtilController.php AliasController.php, src/opnsense/mvc/app/views/OPNsense/Firewall alias.volt alias_util.volt

aliases: Add force GeoIP update button (#9974)
DeltaFile
+16-0src/opnsense/mvc/app/views/OPNsense/Firewall/alias.volt
+0-15src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/AliasUtilController.php
+0-12src/opnsense/mvc/app/views/OPNsense/Firewall/alias_util.volt
+12-0src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/AliasController.php
+6-0src/opnsense/service/conf/actions.d/actions_filter.conf
+34-275 files

LLVM/project 796b218llvm/test/CodeGen/AArch64 rem-by-const.ll, llvm/test/CodeGen/RISCV split-udiv-by-constant.ll split-urem-by-constant.ll

[LegalizeTypes] Expand UDIV/UREM by constant via chunk summation (#146238)

This patch improves the lowering of 128-bit unsigned division and
remainder by constants (UDIV/UREM) by avoiding a fallback to libcall
(__udivti3/uremti3) for specific divisors.

When a divisor D satisfies the condition (1 << ChunkWidth) % D == 1, the
128-bit value is split into fixed-width chunks (e.g., 30-bit) and summed
before applying a smaller UDIV/UREM. This transformation is based on the
"remainder by summing digits" trick described in Hacker’s Delight.

This fixes #137514 for some constants.
DeltaFile
+2,859-7llvm/test/CodeGen/X86/i128-udiv.ll
+474-0llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
+84-69llvm/test/CodeGen/AArch64/rem-by-const.ll
+122-28llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
+74-28llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
+72-10llvm/test/CodeGen/RISCV/div-by-constant.ll
+3,685-1426 files not shown
+3,892-21912 files