LLVM/project 8c88faellvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/AArch64 scalable-strict-fadd.ll sve-tail-folding-unroll.ll

[VPlan] Lower CanIVIncrementForPart in convertToConcreteRecipes. (#190844)

Move the lowering of CanonicalIVIncrementForPart from generate() to
convertToConcreteRecipes, converting it to an Add VPInstruction at the
VPlan level. This enables VPlan-level simplifications (e.g., folding add
0, x) and prepares for adding a 3-operand form.

PR: https://github.com/llvm/llvm-project/pull/190844
DeltaFile
+9-18llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
+6-12llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
+13-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-8llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+28-384 files

LLVM/project 3af4275llvm/include/llvm/Transforms/Utils Cloning.h, llvm/lib/Transforms/IPO Inliner.cpp

[Inliner] Put inline history into IR as !inline_history metadata (#190876)

(Reland of #190700 with checks for RefSCCs with one function with a
self-reference, plus determinism fix)

(Reland of #190092 with verifier change to look through GlobalAliases)

So that it's preserved across all inline invocations rather than just
one inliner pass run.

This prevents cases where devirtualization in the simplification
pipeline uncovers inlining opportunities that should be discarded due to
inline history, but we dropped the inline history between inliner pass
runs, causing code size to blow up, sometimes exponentially.

For compile time reasons, we want to limit this to only call sites that
have the potential to inline through SCCs, potentially with the help of
devirtualization. This means that the callee is in a non-trivial
(Ref)SCC, or the call site was previously an indirect call, which can

    [8 lines not shown]
DeltaFile
+102-0llvm/test/Transforms/Inline/inline-history.ll
+57-28llvm/lib/Transforms/Utils/InlineFunction.cpp
+26-36llvm/lib/Transforms/IPO/Inliner.cpp
+61-0llvm/test/Verifier/inline-history-metadata.ll
+25-26llvm/lib/Transforms/Utils/CloneFunction.cpp
+19-17llvm/include/llvm/Transforms/Utils/Cloning.h
+290-10714 files not shown
+425-21320 files

LLVM/project cf8e6b9llvm/lib/Target/Hexagon HexagonTargetMachine.cpp HexagonMachineFunctionInfo.h, llvm/test/CodeGen/Hexagon aligna-prologue-expansion.mir

Revert "[Hexagon][MIR] Serialize HexagonMachineFunctionInfo::StackAlignBaseRe…"

This reverts commit cd66d79be19b6db00500ba4508b3946ef1caec88.
DeltaFile
+0-36llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+0-29llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
+0-24llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp
+9-6llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
+10-0llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+0-8llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+19-1036 files

LLVM/project 802c5cbflang/include/flang/Evaluate expression.h, flang/lib/Parser expr-parsers.cpp

[flang] Implement conditional expressions parser/semantics (F2023) (#186489)

## Implement Fortran 2023 Conditional Expressions (R1002)

***This PR contains the implementation for parsing and semantic
analysis. Lowering is implemented in a separate PR (#186490)***

Implements Fortran 2023 conditional expressions with syntax: `result =
(condition ? value1 : condition2 ? value2 : ... : elseValue)`

Issue: #176999
Discourse:
https://discourse.llvm.org/t/rfc-adding-conditional-expressions-in-flang-f2023/89869/1
-- note that some of the details provided in the RFC post are no longer
accurate

### Implementation Details
**Parser:**
- Added ConditionalExpr as primary expression (F2023 R1002)  

    [36 lines not shown]
DeltaFile
+429-0flang/test/Semantics/conditional-expr.f90
+286-0flang/test/Parser/conditional-expr.f90
+111-0flang/lib/Semantics/expression.cpp
+47-1flang/lib/Parser/expr-parsers.cpp
+39-8flang/include/flang/Evaluate/expression.h
+42-0flang/test/Evaluate/fold-conditional-expr.f90
+954-922 files not shown
+1,178-1428 files

LLVM/project 46dc97cllvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV split-gep.ll

[NFC][SeparateConstOffsetFromGEP] Add pre-commit test (#191006)
DeltaFile
+46-0llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll
+46-01 files

LLVM/project 5fdc35fllvm/test/tools/llvm-mca/RISCV/SiFiveX390 vector-fp.s, llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv arithmetic.test fp.test

[RISCV][MCA] Update `sifive-x390`'s tests to consume input files instead (#190883)

In the same spirit as #189785 , use the new input file system for
sifive-x390's llvm-mca tests.
DeltaFile
+0-4,851llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s
+4,526-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/arithmetic.test
+3,706-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/fp.test
+3,126-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/vlseg-vsseg.test
+2,878-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/bitwise.test
+2,334-0llvm/test/tools/llvm-mca/RISCV/SiFiveX390/rvv/permutation.test
+16,570-4,85129 files not shown
+28,366-9,99035 files

LLVM/project 179a6ballvm/lib/Target/BPF BPFISelLowering.cpp BPFISelLowering.h, llvm/test/CodeGen/BPF i128_return.ll sret.ll

bpf: Support aggregate returns (#190894)

i128 and 16 byte structs are now returned in R0:R2 which matches x86
that returns { i64, i32 } in RAX:RDX.
Both skip one register in between (RCX / R1).

Signed-off-by: Alexei Starovoitov <ast at kernel.org>
Co-authored-by: Alexei Starovoitov <ast at kernel.org>
DeltaFile
+30-24llvm/lib/Target/BPF/BPFISelLowering.cpp
+44-0llvm/test/CodeGen/BPF/i128_return.ll
+43-0llvm/test/CodeGen/BPF/sret.ll
+17-5llvm/test/CodeGen/BPF/struct_ret1.ll
+8-3llvm/test/CodeGen/BPF/struct_ret2.ll
+6-0llvm/lib/Target/BPF/BPFISelLowering.h
+148-322 files not shown
+151-378 files

LLVM/project fd09e8fclang/test/ExtractAPI availability.c objc_property.m

[ExtractAPI] fix filecheck annotation (#92231)

moved fix for ExtractAPI from
https://github.com/llvm/llvm-project/pull/91854,
https://github.com/llvm/llvm-project/pull/91854#pullrequestreview-2052128349

Also noticed typo here, prefix `E` but check for `C`, fixed too:

https://github.com/llvm/llvm-project/blob/ca4a405232cf170f20a2f111bf72beab82095935/clang/test/ExtractAPI/availability.c#L43-L65

Co-authored-by: klensy <nightouser at gmail.com>
Co-authored-by: Prajwal Nadig <pnadig at apple.com>
DeltaFile
+1-1clang/test/ExtractAPI/availability.c
+1-1clang/test/ExtractAPI/objc_property.m
+2-22 files

FreeNAS/freenas d9148f7src/middlewared/middlewared/etc_files/syslog-ng syslog-ng.conf.mako, src/middlewared/middlewared/etc_files/syslog-ng/conf.d tnfilters.conf.mako

Filter ctdb-related logs into dedicated files

This commit adds syslog-ng filters to ensure that ctdb
logs are written to /var/log/ctdb/ctdb.log rather than
by default landing in /var/log/syslog
DeltaFile
+7-0src/middlewared/middlewared/etc_files/syslog-ng/syslog-ng.conf.mako
+5-0src/middlewared/middlewared/etc_files/syslog-ng/conf.d/tnfilters.conf.mako
+12-02 files

OpenZFS/src eb5c93f.github/workflows zloop.yml

CI: set /etc/hostid in zloop runner

ztest can enable and disable the multihost property when testing.
This can result in a failure when attempting to import an existing
pool when multihost=on but no /etc/hostid file exists.  Update the
workflow to use zgenhostid to create /etc/hostid when not present.

Reviewed-by: Alexander Motin <alexander.motin at TrueNAS.com>
Signed-off-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Closes #18413
DeltaFile
+1-0.github/workflows/zloop.yml
+1-01 files

LLVM/project 0f3e448llvm/include/llvm/IR Instructions.h, llvm/test/Transforms/SimplifyCFG profile-update-unreachable.ll

[SimplifyCFG] Update profile metadata regardless of weight count (#190982)

Otherwise we miss updating in cases where we should be updating which
causes assertion failures later due to the fact that the number of cases
no longer matches the number of branch weights.

It looks like this was last touched in #160629, but it doesn't seem like
there is anything there specifically motivating this diff hunk.

Fixes #190901.
DeltaFile
+39-0llvm/test/Transforms/SimplifyCFG/profile-update-unreachable.ll
+11-2llvm/include/llvm/IR/Instructions.h
+50-22 files

LLVM/project 350d672flang/include/flang/Optimizer/Dialect/Support FIRContext.h, flang/lib/Optimizer/CodeGen CodeGen.cpp

[Flang] mark safe external globals as dso_local (#189709)

Globals inside a Fortran module are not marked as dso_local,
which results in their alignment not being promoted.
This fix mimics some of the functionality found in
shouldAssumeDSOLocal in /clang/lib/CIR/CodeGen/CIRGenModule.cpp

Fixes #189069
DeltaFile
+84-0flang/test/Fir/dso-local.fir
+34-0flang/lib/Optimizer/Dialect/Support/FIRContext.cpp
+17-0flang/test/Fir/dso-local-macho.fir
+13-0flang/include/flang/Optimizer/Dialect/Support/FIRContext.h
+12-0flang/lib/Optimizer/CodeGen/CodeGen.cpp
+2-2flang/test/Lower/common-block.f90
+162-21 files not shown
+164-27 files

NetBSD/pkgsrc Gi0noM7net/vnstati Makefile DESCR

   vnstati: Bump PKGREVISION and improve build

   Don't need gmake any longer.
   Its own Makefile now installs correctly, so don't roll our own.
   Remove incorrect path to check for a config file.
   Add blank line at top of DESCR fragment to improve final output.
VersionDeltaFile
1.2+6-1net/vnstati/Makefile
1.2+1-0net/vnstati/DESCR
+7-12 files

LLVM/project c135522

Merge branch 'fix-blockfreq-unroll-unconditional-latches--tests' into fix-blockfreq-unroll-unconditional-latches
DeltaFile
+0-00 files

NetBSD/pkgsrc Lf1nyHBnet/vnstat Makefile Makefile.common, net/vnstat/files vnstatd.sh

   vnstat: bump PKGREVISION and improve build

   Don't need gmake any longer.
   Its own Makefile now installs correctly, so don't roll our own.
   Move example configuration file to subdir.
   Move vnstatd daemon to sbin, from bin.
   Remove incorrect path to check for a config file.
VersionDeltaFile
1.32+13-16net/vnstat/Makefile
1.1+15-0net/vnstat/patches/patch-src_cfg.c
1.2+8-3net/vnstat/Makefile.common
1.5+3-3net/vnstat/PLIST
1.3+2-2net/vnstat/files/vnstatd.sh
1.2+2-2net/vnstat/MESSAGE
+43-261 files not shown
+45-277 files

LLVM/project dd57f60flang/lib/Optimizer/HLFIR/Transforms SimplifyHLFIRIntrinsics.cpp, flang/test/HLFIR simplify-hlfir-intrinsics-count.fir

[flang] Use reduction recognition friendly pattern for hlfir.count. (#190856)

The change is to select between `0` and `1` based on the condition
and then add the result to the current reduction value.
DeltaFile
+8-8flang/test/HLFIR/simplify-hlfir-intrinsics-count.fir
+5-4flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
+13-122 files

FreeNAS/freenas 55c4965src/middlewared/middlewared/plugins/service_/services dbus_router.py

flake8
DeltaFile
+1-0src/middlewared/middlewared/plugins/service_/services/dbus_router.py
+1-01 files

FreeBSD/ports 7227294japanese/p5-2chproxy Makefile

japanese/p5-2chproxy: Mark DEPRECATED and set EXPIRATION_DATE

PR:             292315
Approved by:    hrs (maintainer timeout > 2 weeks)
Approved by:    fluffy (mentor)
DeltaFile
+3-0japanese/p5-2chproxy/Makefile
+3-01 files

FreeBSD/ports 224f94djapanese/font-migmix Makefile

japanese/font-migmix: Refactor

Lint with portclippy.
Refactoring do-install*.
Switch from LN to RLN.

PR:             277645
Approved by:    fluffy (mentor), osa (mentor)
DeltaFile
+13-20japanese/font-migmix/Makefile
+13-201 files

FreeBSD/ports da49c0bjapanese/font-migmix Makefile distinfo

japanese/font-migmix: Update to 1.0.20231123 and take maintainership

In this release, the version numbers for 1? and 2? are different.
Update MASTER_SITES, DISTFILES and WWW.

Changelog (japanese):
https://itouhiro.github.io/mixfont-mplus-ipa/changelog.html

PR:             277645
Approved by:    hrs (maintainer timeout > 3 months)
Approved by:    fluffy (mentor), osa (mentor)
DeltaFile
+18-15japanese/font-migmix/Makefile
+9-8japanese/font-migmix/distinfo
+27-232 files

LLVM/project 1415b28llvm/test/Transforms/LoopUnroll loop-probability-one.ll, llvm/test/Transforms/LoopUnroll/branch-weights-freq unroll-complete.ll unroll-partial-unconditional-latch.ll

[LoopUnroll] Fix freqs for unconditional latches: introduce tests

This patch introduces all tests for PR #179520 but with current
results so that it is easier to see which results PR #179520 improves.
This patch should not land without PR #179520.
DeltaFile
+530-0llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-complete.ll
+280-0llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial-unconditional-latch.ll
+211-53llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-epilog.ll
+122-85llvm/test/Transforms/LoopUnroll/loop-probability-one.ll
+2-1llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial.ll
+1,145-1395 files

FreeNAS/freenas 4e52ecbtests/unit test_service_failure_logs.py

add unit tests
DeltaFile
+161-0tests/unit/test_service_failure_logs.py
+161-01 files

LLVM/project 0030f59llvm/lib/Target/AArch64 AArch64RedundantCopyElimination.cpp AArch64.h, llvm/test/CodeGen/AArch64 machine-copy-remove.mir machine-zero-copy-remove.mir

[NewPM] Port AArch64RedundantCopyElimination (#190582)

Adds a newPM pass for AArch64RedundantCopyElimination
- Refactors base logic into an Impl class
- Renames old pass with the "Legacy" suffix
- Adds the new pass manager pass using refactored logic
- Updated existing .mir tests to also test with the New Pass Manager.

Context and motivation in
https://llvm.org/docs/NewPassManager.html#status-of-the-new-and-legacy-pass-managers
DeltaFile
+39-15llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
+8-1llvm/lib/Target/AArch64/AArch64.h
+1-1llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+1-0llvm/test/CodeGen/AArch64/machine-copy-remove.mir
+1-0llvm/lib/Target/AArch64/AArch64PassRegistry.def
+1-0llvm/test/CodeGen/AArch64/machine-zero-copy-remove.mir
+51-176 files

LLVM/project 7b16d10llvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp

Added braces.
DeltaFile
+4-3llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+4-31 files

LLVM/project 7056d00llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/InstCombine clamp-to-minmax.ll

[InstCombine][ValueTracking] Add m_FMinNum and m_FMaxNum to matchFastFloatClamp. (#188149)

This allows us to recognize clamp patterns if the first part of the
clamp has been turned into minnum/maxnum.
DeltaFile
+89-0llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
+6-0llvm/lib/Analysis/ValueTracking.cpp
+95-02 files

FreeNAS/freenas 2dfa6c7src/middlewared/middlewared/plugins/failover_ configure.py, src/middlewared/middlewared/plugins/system product.py product_utils.py

New license
DeltaFile
+62-39src/middlewared/middlewared/plugins/system/product.py
+42-36src/middlewared/middlewared/plugins/truenas/license_utils.py
+72-0src/middlewared/middlewared/plugins/truenas/license_legacy_utils.py
+0-60src/middlewared/middlewared/plugins/failover_/configure.py
+0-58src/middlewared/middlewared/plugins/system/product_utils.py
+38-18src/middlewared/middlewared/plugins/truenas/license.py
+214-21122 files not shown
+385-33528 files

LLVM/project cd66d79llvm/lib/Target/Hexagon HexagonTargetMachine.cpp HexagonMachineFunctionInfo.h, llvm/test/CodeGen/Hexagon aligna-prologue-expansion.mir

[Hexagon][MIR] Serialize HexagonMachineFunctionInfo::StackAlignBaseReg to MIR (#190003)

This patch adds serialization of HexagonMachineFunctionInfo::StackAlignBaseReg
into MIR. This field stores the physical register used as the aligned-stack base pointer
when a function has both variable-sized stack objects and requires stack
alignment greater than the default.

This replaces the workaround from commit 2e10b6299591 ("[Hexagon] Add AP
register to liveins when used for frame index access") which manually added
AP to liveins. That approach was incorrect because it only updated one
block without updating predecessors, breaking liveness invariants.
DeltaFile
+36-0llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+29-0llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
+24-0llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp
+6-9llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
+0-10llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+8-0llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+103-196 files

LLVM/project f3155f0clang/include/clang/Basic HLSLIntrinsics.td, clang/lib/Headers/hlsl hlsl_alias_intrinsics.h

[HLSL] Add missing Shader Model 6.0 availability for wave intrinsics (#189445)

Depends on PR #188814 to be merged first.

This PR fixes Shader Model availability for HLSL wave intrinsics so that
they all require at least SM 6.0.

Furthermore, there wasn't an easy way to specify Shader Model 6.0
availability while maintaining the requirement for Shader Model 6.2 when
16-bit types is enabled and the overload uses half types.
To fix the issue, this PR extends `_HLSL_16BIT_AVAILABILITY` to accept a
3rd optional argument that specifies the Shader Model availability when
16-bit types is disabled.

Example:
```hlsl
// If 16-bit types is enabled, require SM 6.2. Else, require SM 6.0 otherwise.
_HLSL_16BIT_AVAILABILITY(shadermodel, 6.2, 6.0)
_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_all_equal)

    [6 lines not shown]
DeltaFile
+42-3clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
+11-29clang/utils/TableGen/HLSLEmitter.cpp
+8-12clang/include/clang/Basic/HLSLIntrinsics.td
+11-9clang/test/TableGen/hlsl-intrinsics.td
+3-2clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+75-555 files

FreeNAS/freenas d9687d8src/middlewared/middlewared/plugins/failover_ configure.py, src/middlewared/middlewared/plugins/system product.py product_utils.py

New license
DeltaFile
+62-39src/middlewared/middlewared/plugins/system/product.py
+40-36src/middlewared/middlewared/plugins/truenas/license_utils.py
+72-0src/middlewared/middlewared/plugins/truenas/license_legacy_utils.py
+0-60src/middlewared/middlewared/plugins/failover_/configure.py
+0-58src/middlewared/middlewared/plugins/system/product_utils.py
+38-18src/middlewared/middlewared/plugins/truenas/license.py
+212-21122 files not shown
+383-33528 files

FreeBSD/ports 8c143bfaudio/plasma6-kpipewire distinfo, audio/plasma6-ocean-sound-theme distinfo

KDE: Update KDE Plasma to 6.6.4

Announcement: https://kde.org/announcements/plasma/6/6.6.4/
DeltaFile
+3-3sysutils/plasma6-powerdevil/distinfo
+3-3audio/plasma6-kpipewire/distinfo
+3-3audio/plasma6-ocean-sound-theme/distinfo
+3-3audio/plasma6-oxygen-sounds/distinfo
+3-3audio/plasma6-plasma-pa/distinfo
+3-3deskutils/plasma6-milou/distinfo
+18-1853 files not shown
+168-16059 files