LLVM/project 5fcab35llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/test/MC/AMDGPU amdhsa-kernel-prologue.s hsa-gfx1250-v4.s

[AMDGPU] Add assembler check for GFX1250 unclaused vmem workaround (#209517)

Warn if an entrypoint does not start with the standard workaround
sequence.
DeltaFile
+49-0llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+28-0llvm/test/MC/AMDGPU/amdhsa-kernel-prologue.s
+12-0llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
+12-0llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s
+101-04 files

OPNSense/ports fdf63b0opnsense/update distinfo

opnsense/update: 26.7 tag was misplaced
DeltaFile
+3-3opnsense/update/distinfo
+3-31 files

LLVM/project 0e1b093llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV sitofp-with-bool.ll uitofp-with-bool.ll

[SPIR-V] Preserve signed i1 semantics in sitofp (#209232)

selectIToF hardcoded IsSigned=false when materializing the bool-to-int
conversion, so sitofp i1 true was miscompiled as 1.0 instead of -1.0
DeltaFile
+2-2llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll
+2-2llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
+1-1llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+5-53 files

LLVM/project f520e70llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp SPIRV.h

[SPIR-V][NewPM] Fix SPIRVEmitIntrinsics registration with the new pass manager (#209966)
DeltaFile
+133-122llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+1-1llvm/lib/Target/SPIRV/SPIRV.h
+1-1llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+135-1243 files

LLVM/project a3bcc01lld/COFF InputFiles.cpp Driver.cpp, lld/test/COFF link-dll-arm64x.s

[LLD] [COFF] Fix linking directly against an ARM64X DLL without import library (#210080)

In mingw mode, when linking against a DLL, the user can either provide a
regular import library, or provide the actual DLL. When importing ARM64X
image, add both native and EC views to the symbol table on EC targets.
Also getMachine() on such images returns ARM64X, treat it as ARM64
instead.
DeltaFile
+81-0lld/test/COFF/link-dll-arm64x.s
+3-20lld/COFF/InputFiles.cpp
+15-1lld/COFF/Driver.cpp
+4-2lld/COFF/InputFiles.h
+103-234 files

LLVM/project b46e6dellvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU global-saddr-load.ll

AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for applyD16Load
DeltaFile
+14-1llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+2-2llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+16-32 files

LLVM/project efd96f7llvm/test/CodeGen/AMDGPU llvm.log.ll llvm.log10.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fpow.ll

AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper

Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
DeltaFile
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log.ll
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+2,760-1,251llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+912-86llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+536-218llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+290-131llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+11,694-4,8624 files not shown
+12,158-5,07110 files

LLVM/project 120343dllvm/lib/Target/AMDGPU AMDGPUPreLegalizerCombiner.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-short-clamp.ll

AMDGPU/GlobalISel: Use integers for clamp i64 to i16 prelegalizer combine
DeltaFile
+26-46llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+6-6llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+32-522 files

LLVM/project e202910llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU codegen-prepare-addrspacecast-non-null.ll

GlobalISel: Use extended LLTs in extract lowering
DeltaFile
+60-29llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+1-1llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+79-485 files

LLVM/project 8980768llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU fptrunc.f16.ll fptrunc.ll

GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering
DeltaFile
+1,282-1,453llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+264-432llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+364-243llvm/test/CodeGen/AMDGPU/fptrunc.ll
+238-239llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
+176-91llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+47-47llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+2,371-2,5056 files

LLVM/project 977bdf5llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.prefetch.inst.ll llvm.amdgcn.s.prefetch.data.ll, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-load.mir regbankselect-waterfall-call.mir

AMDGPU/GlobalISel: Use integers for read-any-lane split type
DeltaFile
+150-72llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
+106-106llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+33-17llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
+24-24llvm/test/CodeGen/AMDGPU/indirect-call.ll
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+341-2476 files not shown
+364-27212 files

LLVM/project 132452fllvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel zextload.ll

AMDGPU/GlobalISel: Fix extending load narrow scalar

isAnyScalar is explicit LLT::scalar check but we want to narrow scalar
integer types as well.
DeltaFile
+6-7llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+7-82 files

LLVM/project 57a45e9llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-constant.mir

AMDGPU/GlobalISel: Use integer as MMO type for loads and stores lowering

We could get away with just the type from MMO in most cases, but MMO splitting
creates MMO with LLT::scalar and we prefer integer.
DeltaFile
+1,622-1,442llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,064-944llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+828-738llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+842-722llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+250-220llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+121-121llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+4,727-4,1878 files not shown
+4,995-4,28614 files

LLVM/project b0dd0f8llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

AMDGPU/GlobalISel: Explicitly widen scalar to i32 for load and store

Affects f16 and bf16. Earlier, they were widened to f32 and s32 respectively.
The actual error was the artifact combiner creating a copy between f32/i32
which fails in the machine verifier. Maybe we could create a bitcast there.
However i32 is more efficient for us and matches well with how argument
lowering keeps f16 and bf16 in i32 copies to/from physical registers.
Also starting from f16 store, G_STORE %0(f16), %1(p1) :: (store (f16),
and doing widen scalar to 32 bit type, i32 makes more sense since store
will store 16 least significant bits G_STORE %0(i32), %1(p1) :: (store (f16)
compared to G_STORE %0(f32), %1(p1) :: (store (f16), which looks incorrect if
we assume input was really in f32 format.
DeltaFile
+2,008-2,008llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,164-1,164llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+963-963llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+556-556llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+486-486llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+108-108llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+5,285-5,28515 files not shown
+5,362-5,36821 files

LLVM/project ea8d864llvm/test/CodeGen/AMDGPU vector-reduce-smin.ll vector-reduce-smax.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.i16.ll insertelement.i8.ll

AMDGPU/GlobalISel: Fix legalizer lowering for G_EXTRACT/INSERT_VECTOR_ELT

Use LLT::integer in bit twiddling lowering for extract/insert vector element.
DeltaFile
+2,741-4,467llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+1,627-4,750llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+990-990llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+975-439llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+8,357-11,51426 files not shown
+13,363-14,10532 files

LLVM/project 622392fllvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Stop using changeTo in legaizer actions

Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
DeltaFile
+855-425llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+783-389llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+759-377llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+253-160llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+232-138llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+58-80llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+2,940-1,56911 files not shown
+3,066-1,65117 files

FreeNAS/freenas c0841besrc/middlewared/middlewared/plugins/apps compose_progress.py, src/middlewared/middlewared/pytest/unit/plugins/apps test_compose_progress.py

Fix CI failures: type compose progress state as dataclasses for mypy --strict and apply ruff import sorting/formatting to new files

Co-Authored-By: Claude Fable 5 <noreply at anthropic.com>
DeltaFile
+64-52src/middlewared/middlewared/plugins/apps/compose_progress.py
+52-53src/middlewared/middlewared/pytest/unit/plugins/apps/test_compose_progress.py
+116-1052 files

LLVM/project 321e45ellvm/test/CodeGen/AMDGPU memset-param-combinations.ll shrink-add-sub-constant.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll saddsat.ll

AMDGPU/GlobalISel: Fix G_MERGE_VALUES lowering for extended LLTs

Use integer type for bit twiddling instead of scalar.
DeltaFile
+1,801-1,013llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
+1,584-1,032llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+1,583-1,004llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+1,449-654llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+1,314-625llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+989-704llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+8,720-5,032186 files not shown
+29,005-19,793192 files

LLVM/project 2580624libcxx/src/support/runtime exception_pointer_msvc.ipp

[libcxx] avoid include Uppercase windows headers (#208903)

We should use unknwn.h and windows.h instead of Unknwn.h and Windows.h
because Linux and other non‑Windows systems treat filenames as
case‑sensitive. Windows does not, so mixed‑case includes work there but
break elsewhere. Both mingw‑w64‑crt and windows‑msvc‑sysroot provide all
Windows headers in fully lowercase, so using the lowercase forms ensures
consistent cross‑platform builds.

Fixes #208901
DeltaFile
+2-2libcxx/src/support/runtime/exception_pointer_msvc.ipp
+2-21 files

LLVM/project a183398llvm/test/CodeGen/AMDGPU freeze.ll vector-reduce-fmax.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f16.ll

AMDGPU/GlobalISel: Fix G_UNMERGE_VALUES lowering for extended LLTs

Use integer type for bit twiddling instead of scalar.
DeltaFile
+1,623-486llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+1,155-361llvm/test/CodeGen/AMDGPU/freeze.ll
+663-347llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+663-347llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+590-290llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+545-261llvm/test/CodeGen/AMDGPU/mad-mix.ll
+5,239-2,092150 files not shown
+15,641-10,429156 files

LLVM/project d457e36llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

AMDGPU/GlobalISel: Switch legalizer intrinsic lowering to extended LLTs

Affects various buffer intrinsics.
DeltaFile
+5,162-5,142llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+4,767-4,791llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+4,321-4,345llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+2,172-2,164llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+2,119-2,107llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+965-965llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+19,506-19,51462 files not shown
+24,540-23,91268 files

LLVM/project f3b7bf5llvm/test/CodeGen/AMDGPU llvm.amdgcn.permlane.ll llvm.is.fpclass.f16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Handle G_BITCAST for 16 bit extendedLLTs

Handle bitcast between i16 and f16/bf16.
For true16 this was already legal, make it legal in regbanklegalize as well.
For non-true16 widen it using G_ANYEXT to i32 and G_TRUNC to dst.
The "i32 G_ANYEXT f16/bf16" and "f16/bf16 G_TRUNC i32" are already legal,
for example these are generated by common CallLowering argument lowering.
DeltaFile
+3,572-3,745llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+3,314-3,041llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+3,245-2,737llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1,670-1,373llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+1,239-552llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+656-996llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+13,696-12,444179 files not shown
+24,976-20,597185 files

FreeBSD/ports 72e9771www/nextcloud-groupfolders distinfo Makefile

www/nextcloud-groupfolders: Update to 22.0.3
DeltaFile
+3-3www/nextcloud-groupfolders/distinfo
+1-1www/nextcloud-groupfolders/Makefile
+4-42 files

NetBSD/pkgsrc u1QvnmMdevel/scons4 build.mk

   scons4: build.mk - honour MAKE_JOBS_SAFE
VersionDeltaFile
1.9+3-1devel/scons4/build.mk
+3-11 files

FreeBSD/ports b8a5260www/nextcloud-contacts distinfo Makefile

www/nextcloud-contacts: Update to 8.7.4
DeltaFile
+3-3www/nextcloud-contacts/distinfo
+1-1www/nextcloud-contacts/Makefile
+4-42 files

FreeBSD/ports 9cadeedwww/nextcloud-forms distinfo Makefile

www/nextcloud-forms: Update to 5.3.4
DeltaFile
+3-3www/nextcloud-forms/distinfo
+1-1www/nextcloud-forms/Makefile
+4-42 files

FreeBSD/ports 78d3ed0Mk/Uses linux.mk, graphics/linux-rl9-vulkan pkg-descr Makefile

graphics/linux-rl9-vulkan: Add vulkan-tools

Following the same Linux packaging pattern as x11/linux-rl9-xorg-libs,
we're simplifying any additional Linux Vulkan packaging into a single
port.

PR:             296502
Co-authored-by: Vincent <tmp386 at live.com>
Approved by:    arrowd (co-mentor)
DeltaFile
+16-0graphics/linux-rl9-vulkan/pkg-descr
+4-6graphics/linux-rl9-vulkan/Makefile
+8-2graphics/linux-rl9-vulkan/pkg-plist.aarch64
+8-2graphics/linux-rl9-vulkan/pkg-plist.amd64
+7-1graphics/linux-rl9-vulkan/distinfo
+1-1Mk/Uses/linux.mk
+44-126 files

OPNSense/src 54cfc12sys/kern uipc_ktls.c kern_mbuf.c, sys/sys mbuf.h

ktls: Propagate EPG_FLAG_ANON to mapped mbufs

Taken from: https://reviews.freebsd.org/D57557
DeltaFile
+2-1sys/kern/uipc_ktls.c
+3-0sys/kern/kern_mbuf.c
+1-0sys/sys/mbuf.h
+6-13 files

OPNSense/core 17a4f28src/opnsense/mvc/app/models/OPNsense/Firewall/FieldTypes FilterRuleField.php, src/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Collapse defunct bucket per default
DeltaFile
+1-1src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+0-1src/opnsense/mvc/app/models/OPNsense/Firewall/FieldTypes/FilterRuleField.php
+1-22 files

FreeNAS/freenas 4db6502src/middlewared/middlewared/test/integration/utils job.py, tests/api2 test_apps.py

Add stall-based job timeout to busy_wait_on_job and assert image reuse via pull progress in app reinstall test

Co-Authored-By: Claude Fable 5 <noreply at anthropic.com>
DeltaFile
+20-9tests/api2/test_apps.py
+21-2src/middlewared/middlewared/test/integration/utils/job.py
+41-112 files