Hexagon: Remove kill flags on virtual registers from MIR tests
Prepare to disallow this in the machine verifier. Move the one unique
case from qfp-remove-kill.mir into qfp-mix.mir; the rest only differed
from other tests in kill flags.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
RuntimeLibcalls: Move phantom llvm runtime functions out of compiler-rt (#236902)
These __llvm prefixed libcalls have no implementation provided by
compiler-rt or anywhere else I can see. It seems the intent was you
need to provide DIY implementations which is absurd. I assume this is
a product of aversion to touching compiler-rt.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Move contiguity check into canVectorizeLSV() (NFC)
Both vectorizeStores() and vectorizeLoads() (via createVectorLoad())
checked that the bundle is consecutive before calling canVectorize().
Move that check into LegalityAnalysis::canVectorizeLSV(), reporting
ResultReason::NotConsecutive, which mirrors how canVectorize() checks
consecutive loads and stores for BundleVec.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
Revert "[lldb] Speed up thread plan pruning for large thread counts" (#236903)
Reverts llvm/llvm-project#236269
This broke the
[lldb-remote-linux-win](https://lab.llvm.org/buildbot/#/builders/197)
bot.
lib/libifconfig: Fix pointer-sign warnings
Fix all pointer-sign warnings generated when compiling libifconfig.
One of these warnings comes from the misuse of snl_add_msg_attr_string
for a byte array. Though userland treats carpr_key as a string, it is
actually an array of bytes. Handle it as such in libifconfig.
While here, fix a small consistency nit in ifconfig_sfp_get_sfp_dump.
Signed-off-by: Ryan Moeller <rmoeller.dev at gmail.com>
Reviewed by: imp, zlei
Pull Request: https://github.com/freebsd/freebsd-src/pull/1850
(cherry picked from commit 20cd1b475a1ef9dfca30726999aa1b9a02d5bc39)
ifconfig: add CMIS support for 400GbE optics
Add support for CMIS based optics, typically used by 400GbE
and faster ethernet optics. The CMIS standard requires paged
support for i2c ioctls.
This has been tested on an Nvidia ConnectX-7 and Broadcom
Thor2 400GbE NIC, and I have verified that optics vendor information,
light levels, and temperatures match the information provided by
various vendor tools.
Differential Revision: https://reviews.freebsd.org/D56265
Reviewed by: kbowling, sumit.saxena_broadcom.com
Sponsored by: Netflix
(cherry picked from commit 963f1a5455c9f94457c1fa122d18ab9c059db834)
lib/libifconfig: Fix pointer-sign warnings
Fix all pointer-sign warnings generated when compiling libifconfig.
A couple more snuck in while the previous batch of fixes was landing.
Fixes: 963f1a5455c9 ("ifconfig: add CMIS support for 400GbE optics")
Reviewed by: kevans
Approved by: kevans (mentor)
Differential Revision: https://reviews.freebsd.org/D60573
(cherry picked from commit a3c57739ca07c655fbb0f9e7ddd38968186b8a76)
ifconfig: Improve CMIS parsing of breakout configs
This fixes a bug where we do not report all lanes when
a NIC configures a breakout. Eg, we reported all 4
lanes when a NIC configured the optics as 1x400g, but
only printed the first lane's strength when configured as
4x100g.
Fix this by actually parsing the active lane count, rather
than pulling it from the default descriptor.
While here, optionally print page 10h when -vvvv is
specified. This aids in determining how a breakout is configured.
I put it under an extra level of verbosity, as I don't want
to let things get out of hand printing CMIS pages.
Sponsored by: Netflix
Reviewed by: kib, sumit.saxena_broadcom.com
Differential Revision: https://reviews.freebsd.org/D58263
[2 lines not shown]
nfsserver: use the destination export for the COPY/CLONE write check
The write-permission check on the destination file in
nfsrvd_copy_file_range() and nfsrvd_clone() tested
NFSVNO_EXSTRICTACCESS() on the source export instead of the destination
export.
Rick notes:
The change is harmless and mostly meaningless.
NFSVNO_EXSTRICTACCESS() is a placeholder for some site that might
not want to let the file "owner" get access despite mode bits.
The "owner override" is a hack that has existed forever in NFS,
since applications often create files with O_WRONLY, but mode 444.
This works for POSIX, but would make NFS writes fail, since they
check mode on every write, instead of just at POSIX open(). The hack
is to always allow the file owner to have write access.
Without the hack, lots of applications would break over NFS, so I
[6 lines not shown]
[SelectionDAG] Fix reversed branch probabilities in condition merging (#233900)
`shouldKeepJumpConditionsTogether` assigns successor 0 to `IfFalse` and
successor 1 to `IfTrue`, but LLVM's conditional branches use the
opposite order.
This reverses the probability bias. For `A && B`, a hot true edge means
both operands are usually needed, so the heuristic should favor
combining their evaluation. Instead, it treats that edge as false and
favors splitting. The AND/cold and OR cases are reversed too.
Swap the successor indices and add X86 tests for hot/cold AND and OR.
This corrects the heuristic's inputs; it does not assume that one
instruction sequence is always faster.
Validation against main `9e5738a4`: tested all 14,120 cases in
CodeGen/X86, AArch64, RISCV and SystemZ (293 unsupported, 16 expected
failures). The 12 changed tests pass without the patch and failed with
it; all pass after regenerating their checks. The new regression test
[7 lines not shown]
RISCV: Remove kill flags on virtual registers from MIR tests
Soon the verifier will disallow these. Delete cases which differ from
another only in kill flag use.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
ARM: Remove kill flags on virtual registers from MIR tests
The verifier will soon disallow these. Delete tests which only differ
from another in the kill flags.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[BuildLibCalls] Fix attributes on sincospi[f]_stret (#235862)
Followup to #231273. Several issues:
* LibFunc_sincospif_stret, like all the other Darwin-specific trig
functions, shouldn't be marked as setting errno.
* LibFunc_sincospi_stret seems to have been omitted from attributes
altogether.
* In sincos_stret.ll, SINCOS_ATTRS was being redefined. This could allow
the test to pass even if the first attributes were wrong.
SystemZ: Remove kill flags on virtual registers from MIR tests
The verifier will soon disallow these, so prepare test inputs. Delete
tests that were identical except for the kill flags.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Vectorize store chains whose loads have external uses
vectorizeStores() used to give up on a load-store chain if any of the
loads had a user other than its store. Now that loads of mixed types
can be unpacked from a vector load, vectorize such chains as well: the
loads become a single vector load, and the external users are fed from
the lanes each load occupies, cast back to the load's type if needed.
The unpacking loop of vectorizeLoads() is factored out into
unpackLoads() (along with the canUnpackLoads() check) and shared by
both paths. Chains with a non-integral pointer load that has external
users are still left alone.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Support mixed-type store vectorization of arbitrary values
vectorizeStores() only handled chains whose stored values were all
consecutive loads or all constants. Any other chain, e.g., storing
function arguments or computed values, was left alone.
Pack such values into a vector with createPack(). For a chain of mixed
types the vector has integer lanes, so each value is first
reinterpreted (bitcast / ptrtoint) as the lanes it occupies with
Reinterpret::reinterpretValue(), and a value spanning several lanes is
inserted lane by lane. The pack is placed right before the vector
store, where every stored value is available. Whether this pays off is
left to the existing cost check in acceptOrRevert().
Chains storing a non-integral pointer are left alone.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Support mixed-type load vectorization
Remove the restriction that every load in a top-level load chain must
have the vector's element type. A chain of mixed types such as
{i32, float} or {double, i32, i32} is loaded as a vector of integers
(as chosen by VecUtils::getCombinedVectorTypeFor()), each original load
is unpacked from the lanes it occupies, and then reinterpreted back to
its own type with Reinterpret::reinterpretValue().
Chains involving a non-integral pointer are left alone, since such a
pointer cannot be recovered from an integer lane.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Add LLVM_ABI annotations to Reinterpret
Export the out-of-line static members of Reinterpret, as reported by
the LLVM_ABI annotation check. getCastChain() is private but is called
from the inline canReinterpret(), so it needs to be exported too.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Add Reinterpret helper for same-size type casts
Replace getEquivalentConstantWithType() with a Reinterpret utility that
reinterprets the bits of a value as another type of the same size. It
builds a chain of ptrtoint / bitcast / inttoptr casts, and applies it
either to a constant (folding) or to a runtime value (inserting casts).
The runtime form will be used to unpack mixed-type vector loads and to
pack mixed-type store operands.
Also add VecUtils::isNonIntegralPtr(). A non-integral pointer has no
stable integer representation, so it is no longer packed into an
integer lane. Previously only a non-integral destination type was
rejected (via an assert), while a non-integral source such as
'ptr addrspace(5) null' was silently converted with ptrtoint.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Move contiguity check into canVectorizeLSV() (NFC)
Both vectorizeStores() and vectorizeLoads() (via createVectorLoad())
checked that the bundle is consecutive before calling canVectorize().
Move that check into LegalityAnalysis::canVectorizeLSV(), reporting
ResultReason::NotConsecutive, which mirrors how canVectorize() checks
consecutive loads and stores for BundleVec.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
CodeGen: Remove kill flags on virtual registers from MIR tests
Stop using them in test inputs in preparation for disallowing them in
the verifier. This batch covers the generic tests Cover the generic
tests and some of the smaller targets. Delete a test which only
checked kill flag maintenance.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[ASan][test] Mark Posix/stack-overflow.cpp UNSUPPORTED on Android AArch64 (#236884)
Temporarily mark `TestCases/Posix/stack-overflow.cpp` unsupported on
Android AArch64 while waiting for #236879.
When the stack-overflow `SIGSEGV` hits right after `paciasp` + `sub sp`
in a PAC-RET prologue (enabled by default on Android AArch64),
`libunwind` skips `DW_CFA_def_cfa_offset` at the faulting PC during
signal-frame unwinding and traps with `SIGILL` on `FEAT_FPAC` CPUs
(https://lab.llvm.org/staging/#/builders/sanitizer-x86_64-linux-android).
Assisted-by: Gemini
[libc] Avoid large stack buffer in regex matcher_test (#235871)
`StarMatchingAndStabilization` (added in #233980) declares a 10,000-byte
input buffer on the stack. This overflows the stack when the test runs
on NVPTX and makes the test fail with:
```
error in cuMemcpyDtoHAsync: an illegal memory access was encountered
```
Make the buffer static, as 7cb6e6bced8c did for `SortingTest.h`.
Assisted-by: Devin
Co-authored-by: Devin <158243242+devin-ai-integration[bot]@users.noreply.github.com>
[mlir][tosa] Move SLICE constant-operand checks to tosa-validate (#234584)
Part of #233457.
`SliceOp::verify()` reads start/size from their tosa.const_shape
producers
and checks their values, which is not local to the operation. Move the
ERROR_IF conditions to checkErrorIfSlice():
- ERROR_IF(any(start < 0))
- ERROR_IF(any(size <= 0))
- ERROR_IF(is_block_scale && start[rank - 1] % innermost_block_size !=
0)
Drop the two MLIR-specific consistency checks (output shape matching the
size values, start + size within input bounds), following #233064.
This also fixes a latent out-of-bounds access: the block-scaled
alignment
[6 lines not shown]
[SandboxVec][LoadStoreVec] Move contiguity check into canVectorizeLSV() (NFC)
Both vectorizeStores() and vectorizeLoads() (via createVectorLoad())
checked that the bundle is consecutive before calling canVectorize().
Move that check into LegalityAnalysis::canVectorizeLSV(), reporting
ResultReason::NotConsecutive, which mirrors how canVectorize() checks
consecutive loads and stores for BundleVec.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Enforce MFMA C/D bank requests
Enforce explicit C/D policies in AMDGPUPrepareAGPRAlloc after the
original instruction selection, including at -O0 and for optnone.
Switch existing forms and insert bank copies when the request differs
from the selected form. Keep the original optimization optional.
Exclude explicit policies from scheduler and AGPR-copy form rewrites
so later optimizations preserve the requested bank.
