LLVM/project 814148eclang/test/CIR/CodeGen inherited-ctors.cpp vtt.cpp

[CIR] Insert on-demand functions at module scope (#207260)

This showed up building GROMACS with ClangIR at -O3, where compilation
hits an MLIR assertion about an operation already being in a block.

The problem is in vtable thunk emission. When we generate a thunk the
builder's insertion point is inside the thunk's entry block, and from
there we call getAddrOfFunction for the thunk's callee. If that callee
hasn't been created yet, as happens for a virtual-base override first
referenced by a construction-vtable thunk, createCIRFunction builds the
new function right there, parented under the thunk. The final push_back
then tries to move a function that is already in a block.

When there is no CIRGenFunction active, createCIRFunction should just
set the insertion point to module scope before creating the function
instead of creating it at the ambient point and pushing it back
afterward. This is what createGlobalOp already does for globals
materialized this way.


    [5 lines not shown]
DeltaFile
+152-162clang/test/CIR/CodeGen/lambda-static-invoker.cpp
+143-143clang/test/CIR/CodeGen/ctor.cpp
+127-137clang/test/CIR/CodeGen/lambda.cpp
+96-99clang/test/CIR/CodeGen/array-init-loop-exprs.cpp
+85-92clang/test/CIR/CodeGen/vtt.cpp
+46-46clang/test/CIR/CodeGen/inherited-ctors.cpp
+649-67983 files not shown
+1,407-1,37889 files

LLVM/project 4bfd08cllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv masked-load-vl-predicatable.ll

[RISCV] Turn certain cases of masked.load into vp.load + vp.merge (#217184)

Though RISC-V's loop vectorizer would never generate this, but I found
that other frontends like MLIR might generate "SVE-style" fixed vector
masked.load that looks like this:
```
%b = splat %base
%s = <0, 1, 2, 3, ...>
%a = add nuw %b, %s
%N = splat %n
%m = icmp ult %a, %N
%v = mask.load %p, %m, %passthru
```
By default RISC-V lowers this sequence verbatim and thus emitting masks.
To avoid masks, I think we could use vp.load + vp.merge instead with VL
equals to
```
min(%n - min(%n, %base + %offset), numElements)
```
where %offset is the start value of step vector %s and numElements is
the fixed vector size.
DeltaFile
+64-52llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
+59-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+123-522 files

LLVM/project fc70e3dllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 fp-int-fp-cvt.ll

[X86] lowerFPToIntToFP - handle signedness for fp->int and int->fp independently (#217404)

We were assuming that both conversions were for the same integer
signedness

Fixes #217355
DeltaFile
+30-8llvm/test/CodeGen/X86/fp-int-fp-cvt.ll
+10-5llvm/lib/Target/X86/X86ISelLowering.cpp
+40-132 files

LLVM/project 7e104f1lldb/tools/debugserver/source/MacOSX MachTask.mm

Use a fallback interval strategy for the task_for_pid request. (#217425)

We've seen cases on heavily loaded bots where task_for_pid requests get
denied because the authentication system is overloaded. Use an
increasing timeout to avoid piling on when this is happening.

The fallback I chose does:

0: 0.01
1: 0.02
2: 0.04
3: 0.07
4: 0.11
5: 0.16
6: 0.22
7: 0.29
8: 0.37
9: 0.46

which seems reasonable to me. At worst this will wait about a second,
which is still below our test launch timeouts.
DeltaFile
+8-1lldb/tools/debugserver/source/MacOSX/MachTask.mm
+8-11 files

LLVM/project 4058739llvm/lib/Target/X86/GISel X86InstructionSelector.cpp X86LegalizerInfo.cpp, llvm/test/CodeGen/X86/GlobalISel select-insert-vec256.mir select-insert-vec512.mir

X86/GlobalISel: Use mi_match for implicit-def and constant checks (#217444)

Also fix some broken tests using IMPLICIT_DEF without a set register
class. Ideally the verifier would check these. Real compiles should
have used G_IMPLICIT_DEF

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+4-4llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
+5-3llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+2-2llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
+3-1llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+14-104 files

LLVM/project ab962efllvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlan.h

[VPlan] Move requiresScalarEpilogue to VPlan (NFC). (#217447)

Move requiresScalarEpilogue fully to VPlan after no issues uncovered in
the transition period mentioned in
https://github.com/llvm/llvm-project/pull/207784.
DeltaFile
+12-24llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+7-0llvm/lib/Transforms/Vectorize/VPlan.h
+0-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+19-283 files

LLVM/project 9b8e7ebllvm/include/llvm/Analysis LibcallLoweringInfo.h

Adjust comment
DeltaFile
+1-1llvm/include/llvm/Analysis/LibcallLoweringInfo.h
+1-11 files

LLVM/project 593b290llvm/include/llvm/Analysis LibcallLoweringInfo.h, llvm/include/llvm/CodeGen LibcallLoweringInfo.h

Analysis: Move LibcallLoweringInfo from CodeGen to Analysis

Middle end passes need to be able to reason about library call
availability and potentially emit them without depending on codegen.
TargetLibraryInfo already lives in Analysis, and this is a step towards
the eventual merger. For now this is a mostly mechanical move, type erasing
the reference to TargetSubtargetInfo.

The per-subtarget customization (TargetSubtargetInfo::initLibcallLoweringInfo)
is inverted into a caller-supplied function_ref, so the Analysis types carry
no CodeGen/TargetSubtargetInfo reference. The module map is keyed on an opaque
erased pointer. CodeGen continues looking up based on the subtarget.

It is not yet in a state where it is usable from middle end passes; that will come
later. In principle we should be able to write arbitrary rules based on a function's
ABI attributes for which calls can be used.

Co-authored-by: Claude (Claude Opus 4.8) <noreply at anthropic.com>
DeltaFile
+160-0llvm/include/llvm/Analysis/LibcallLoweringInfo.h
+13-114llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
+23-35llvm/lib/CodeGen/LibcallLoweringInfo.cpp
+49-0llvm/lib/Analysis/LibcallLoweringInfo.cpp
+4-1llvm/unittests/CodeGen/GlobalISel/GISelMITest.h
+3-1llvm/lib/CodeGen/TargetLoweringBase.cpp
+252-15111 files not shown
+264-16117 files

LLVM/project 96ceaaeclang/include/clang/Sema Sema.h, clang/lib/AST Type.cpp

[HLSL][Matrix] Add comparison operator support (#216791)

fixes #216786

This change adds matrix cmp support similar to that done for vector
types.
DeltaFile
+83-0clang/test/CodeGenHLSL/BasicFeatures/MatrixComparisonOperators.hlsl
+54-0clang/test/SemaHLSL/Operators/matrix-comparisons.hlsl
+33-0clang/lib/Sema/SemaExpr.cpp
+3-0clang/lib/CodeGen/CGExprScalar.cpp
+3-0clang/include/clang/Sema/Sema.h
+2-0clang/lib/AST/Type.cpp
+178-06 files

LLVM/project 0be6014mlir/lib/Transforms/Utils Inliner.cpp, mlir/test/Transforms inlining-recursive.mlir

[mlir][inliner] Avoid re-expanding recursive calls across SCC iterations (#211377)

The MLIR inliner tracks inline history only within one invocation of
`inlineCallsInSCC`. This correctly detects recursion while processing
the current call worklist.

However, `inlineSCC` repeatedly runs optimization and inlining. On every
iteration, the inline history was recreated. A recursive call left from
the previous iteration was therefore treated as a new root call and
expanded again.

For example:

```mlir
func.func @caller(%arg: i32) -> i32 {
  %0 = call @a(%arg) : (i32) -> i32
  return %0 : i32
}


    [144 lines not shown]
DeltaFile
+94-0mlir/test/Transforms/inlining-recursive.mlir
+26-10mlir/lib/Transforms/Utils/Inliner.cpp
+120-102 files

LLVM/project 5477b12llvm/include/llvm/CodeGen/GlobalISel MIPatternMatch.h, llvm/lib/Target/AArch64/GISel AArch64PreLegalizerCombiner.cpp

GlobalISel: Add m_GAssertZext matcher and use it in AArch64 combiner (#217443)

Generalize the G_SEXT_INREG source+immediate matcher into a shared 
template and add m_GAssertZext on top of it. Use it to  replace the 
getVRegDef + G_ASSERT_ZEXT opcode and immediate checks. NFC.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+26-11llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+3-7llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+29-182 files

LLVM/project c87e675llvm/include/llvm/Target TargetMachine.h, llvm/lib/Target TargetMachine.cpp

CodeGen: Consolidate target-abi validation (#217426)

LoongArch and RISCV both implemented an error if the
"target-abi" module flag was inconsistent with the -target-abi
option flag. Consolidate these into one place, and change
from a fatal error to a nonfatal context error.

One untested incidental behavior change is for garbage names.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+15-0llvm/lib/Target/TargetMachine.cpp
+1-10llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-10llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+5-0llvm/include/llvm/Target/TargetMachine.h
+2-2llvm/test/CodeGen/RISCV/module-target-abi2.ll
+2-2llvm/test/CodeGen/RISCV/module-target-abi.ll
+26-246 files

LLVM/project e0c9e88utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[Bazel] Fixes b562ef5 (#217450)

This fixes b562ef546e46face7172d174e1a5f5454c470eee (#217415).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=b562ef546e46face7172d174e1a5f5454c470eee

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project 126ce9fllvm/include/llvm/CodeGen/GlobalISel MIPatternMatch.h, llvm/lib/Target/RISCV/GISel RISCVInstructionSelector.cpp

RISCV/GlobalISel: Use mi_match for all-ones check (#217441)

Introduce a new m_AllOnes matcher, like the IR version has

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+10-0llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+2-6llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+12-62 files

LLVM/project 3850af1llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU bitop3.ll

[AMDGPU][GlobalISel] Fix BITOP3 selecting B16 opcode for 32-bit vector types (#217048)

Key the opcode choice off bit width instead of an exact i32 match, since
`<2 x i16>` is also 32 bits wide
DeltaFile
+50-0llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitop3.mir
+47-0llvm/test/CodeGen/AMDGPU/bitop3.ll
+5-1llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+102-13 files

FreeBSD/ports a2cc1easecurity/zeek Makefile pkg-plist

security/zeek: Update to 8.0.10

    https://github.com/zeek/zeek/releases/tag/v8.0.10

This release fixes the following vulnerabilities:

 - HIGH: SMB: Chains of AndX messages can crash Zeek

 - HIGH: DNP3: Memory exhaustion via file control (g70v1) fields

 - HIGH: SIP: Memory exhaustion from long request/response paths

 - HIGH: DHCP: Memory exhaustion from retained options after analyzer
   violation

 - HIGH: SMTP: Memory exhaustion from large numbers of rcptto/to/cc/path
   entries

 - HIGH: SMB: DCE/RPC memory exhaustion from fragment state

    [63 lines not shown]
DeltaFile
+3-3security/zeek/distinfo
+4-0security/zeek/pkg-plist
+1-2security/zeek/Makefile
+8-53 files

LLVM/project 4d0039fllvm/include/llvm/CodeGen MachineCombiner.h, llvm/include/llvm/Passes MachinePassRegistry.def

[NewPM] Port MachineCombiner to the new pass manager (#217279)

Adds a newPM pass for MachineCombiner (machine-combiner).

- Refactors base logic into a MachineCombinerImpl class, with a run
method taking analysis pointers (RegisterClassInfo included) rather than
pulling them via getAnalysis, which only the legacy Pass subclass has
access to.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass MachineCombinerPass, using
RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
calls skipFunction, so it always runs unconditionally and should not be
skippable in the new PM either.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder.
- Enables MachineCombinerPass in X86CodeGenPassBuilder.
- Updates the existing .mir test to also verify MachineCombinerPass
under the new pass manager.

Assisted-by: Claude Sonnet 5
DeltaFile
+89-41llvm/lib/CodeGen/MachineCombiner.cpp
+24-0llvm/include/llvm/CodeGen/MachineCombiner.h
+2-4llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+1-1llvm/lib/CodeGen/CodeGen.cpp
+1-1llvm/include/llvm/Passes/MachinePassRegistry.def
+2-0llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+119-474 files not shown
+123-4810 files

FreeBSD/ports cbe03aasecurity/vuxml/vuln 2026.xml

security/vuxml: Mark security/zeek < 8.0.10 as vulnerable as per:

    https://github.com/zeek/zeek/releases/tag/v8.0.10

This release fixes the following vulnerabilities:

 - HIGH: SMB: Chains of AndX messages can crash Zeek

 - HIGH: DNP3: Memory exhaustion via file control (g70v1) fields

 - HIGH: SIP: Memory exhaustion from long request/response paths

 - HIGH: DHCP: Memory exhaustion from retained options after analyzer
   violation

 - HIGH: SMTP: Memory exhaustion from large numbers of rcptto/to/cc/path
   entries

 - HIGH: SMB: DCE/RPC memory exhaustion from fragment state

    [46 lines not shown]
DeltaFile
+68-1security/vuxml/vuln/2026.xml
+68-11 files

LLVM/project 077ec54llvm/docs LangRef.md, llvm/lib/IR Verifier.cpp

IR: Validate and document the "target-abi" module flag (#217397)

The "target-abi" module flag is already emitted by clang for RISC-V and
consumed by the RISC-V and LoongArch backends, but it was neither
validated by the IR Verifier nor documented in LangRef. Add a Verifier 
check that the flag's value operand is a non-empty string.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+25-0llvm/test/Verifier/module-flags-target-abi.ll
+18-0llvm/docs/LangRef.md
+13-0llvm/test/Assembler/module-flags-target-abi.ll
+6-0llvm/lib/IR/Verifier.cpp
+62-04 files

OpenBSD/ports WsOiQfXwww/nginx Makefile distinfo

   update some of the nginx extensions, ok robert

   nginx-modules-ngx_http_hmac_secure_link_module-2.0.0
   nginx-njs-1.0.0
   openresty-headers-more-nginx-module-v0.40
   owasp-modsecurity-ModSecurity-nginx-v1.0.4
   vision5-ngx_devel_kit-v0.3.4
VersionDeltaFile
1.102+10-10www/nginx/distinfo
1.209+10-6www/nginx/Makefile
+20-162 files

OpenBSD/src h5h7Kfgusr.bin/tmux window-copy.c

   Stop at the right end line when walking wrapped lines, GitHub issue 5479.
VersionDeltaFile
1.426+4-3usr.bin/tmux/window-copy.c
+4-31 files

LLVM/project a1deec9llvm/include/llvm/ADT FoldingSet.h, llvm/lib/Support FoldingSet.cpp

[ADT] Clean up FoldingSet growth (NFC) (#217424)

This patch cleans up hash table growth in FoldingSetBase:

- Remove GrowHashTable, a private 3-line wrapper around GrowBucketCount,
  in favor of calling GrowBucketCount(NumBuckets * 2, Info) directly in
  InsertNode.

- Refactor GrowBucketCount to use the RAII copy-and-swap pattern. Rehash
  nodes into a temporary FoldingSetBase and move-assign it to *this to
  avoid duplicating bucket allocation and deallocation logic.

Assisted-by: Antigravity
DeltaFile
+10-20llvm/lib/Support/FoldingSet.cpp
+0-3llvm/include/llvm/ADT/FoldingSet.h
+10-232 files

OpenBSD/ports aBuot1ctextproc/simdutf distinfo Makefile, textproc/simdutf/pkg PFRAG.tools

   textproc/simdutf: Update to 9.1.0
VersionDeltaFile
1.9+3-3textproc/simdutf/Makefile
1.8+2-2textproc/simdutf/distinfo
1.3+1-1textproc/simdutf/pkg/PFRAG.tools
+6-63 files

Linux/linux 98f21c5drivers/fwctl Kconfig, drivers/fwctl/bnxt main.c

Merge tag 'for-linus-fwctl' of git://git.kernel.org/pub/scm/linux/kernel/git/fwctl/fwctl

Pull fwctl updates from Jason Gunthorpe:

 - Support more commands in bnxt, this completes what they originally
   wanted to do

 - Rust bindings for fwctl. The Nova GPU is expected to use them next
   cycle

* tag 'for-linus-fwctl' of git://git.kernel.org/pub/scm/linux/kernel/git/fwctl/fwctl:
  rust: introduce abstractions for fwctl
  fwctl/bnxt: Add DMA buffer support for HWRM commands
  bnxt_en: Update bnxt firmware spec
DeltaFile
+593-0rust/kernel/fwctl.rs
+585-0include/linux/bnxt/hsi.h
+391-5drivers/fwctl/bnxt/main.c
+17-0rust/helpers/fwctl.c
+12-0drivers/fwctl/Kconfig
+4-0include/uapi/fwctl/bnxt.h
+1,602-54 files not shown
+1,610-610 files

FreeNAS/freenas b031c90tests/unit test_activedirectory_health.py

Fix stale-SID recovery test to match stable/26's call_sync-based restart

PR #19223 (call_sync2 migration) wasn't backported here, so
_recover_ad still restarts idmap via middleware.call_sync, not
call_sync2. Update the test to match, instead of pulling in the
unrelated migration.
DeltaFile
+4-3tests/unit/test_activedirectory_health.py
+4-31 files

FreeBSD/ports 7377f8bdatabases/heidisql Makefile distinfo, databases/heidisql/files patch-source_generic__types.pas patch-source_main.pas

databases/heidisql: Update to 12.21

ChangeLog at:   https://github.com/HeidiSQL/HeidiSQL/releases/tag/v12.21
DeltaFile
+6-6databases/heidisql/files/patch-source_main.pas
+3-3databases/heidisql/files/patch-source_generic__types.pas
+3-3databases/heidisql/distinfo
+1-1databases/heidisql/Makefile
+13-134 files

LLVM/project b562ef5flang/test/Fir/OpenACC acc-declare-ctor-dtor-conversion.fir, mlir/include/mlir/Dialect/OpenACC/Transforms Passes.td

[mlir][acc] Add pass to convert acc declare ctors and dtors to LLVM (#217415)

Adds the `acc-declare-ctor-dtor-conversion` pass which converts
`acc.global_ctor` and `acc.global_dtor` operations into LLVM functions
and registers them in `llvm.mlir.global_ctors` and
`llvm.mlir.global_dtors`.

The pass exposes a `priority` option to control when the generated
functions run relative to other module initializers.

---------

Co-authored-by: Susan Tan <zujunt at nvidia.com>
DeltaFile
+182-0mlir/lib/Dialect/OpenACC/Transforms/ACCDeclareCtorDtorConversion.cpp
+78-0flang/test/Fir/OpenACC/acc-declare-ctor-dtor-conversion.fir
+76-0mlir/test/Dialect/OpenACC/acc-declare-ctor-dtor-conversion.mlir
+25-0mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
+2-0mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
+363-05 files

Linux/linux 85e0d1dDocumentation/driver-api vfio.rst, drivers/iommu/iommufd ioas.c selftest.c

Merge tag 'for-linus-iommufd' of git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd

Pull iommufd updates from Jason Gunthorpe:
 "One small feature this cycle, the noiommu mode is useful in
  single-purpose VMs running something like DPDK. It avoids the double
  translation overhead and it seems to be commonly used with some hacks.

  Summary:

   - Formal API for "no iommu" mode in VFIO. iommufd now works in this
     environment and provides page pinning and phyiscal address services
     to userspace. This avoids nasty fragile tricks with mprotect and
     pgmap

   - Fix sykzaller crash racing change_process with map_pages

   - Various skyzkaller/AI fixes for the selftests"

* tag 'for-linus-iommufd' of git://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd:

    [13 lines not shown]
DeltaFile
+155-73drivers/iommu/iommufd/device.c
+105-0drivers/iommu/iommufd/hwpt_noiommu.c
+87-2Documentation/driver-api/vfio.rst
+79-1drivers/iommu/iommufd/io_pagetable.c
+40-3drivers/iommu/iommufd/selftest.c
+40-0drivers/iommu/iommufd/ioas.c
+506-7914 files not shown
+686-11620 files

Linux/linux 4994ef0Documentation/devicetree/bindings/iommu ti,omap-iommu.yaml, drivers/iommu rockchip-iommu.c

Merge tag 'iommu-updates-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux

Pull iommu updates from Joerg Roedel:
 "ARM SMMUv2:
   - Device-tree binding updates for Qualcomm Eliza, Maili, Shikra and
     IPQ9650 SoCs
   - Add support for Qualcomm SM8450
   - Numerous fixes for lifetime and ordering issues found by Sashiko in
     the Qualcomm driver

  ARM SMMUv3:
   - Fix interrupt type in device-tree binding example for NVIDIA CMDQV
   - Numerous fixes for issues identified by Sashiko in the NVIDIA CMDQV
     driver
   - Work around TLB erratum T264-SMMU-3 on Tegra264 by repeating the
     invalidation sequence
   - Add support for HAFT (hardware access flag in table entries) when
     using SVA
   - Probe for 52-bit addressing with a page size smaller than 64k

    [74 lines not shown]
DeltaFile
+155-69drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
+149-39drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+92-62drivers/iommu/intel/iommu.c
+59-58drivers/iommu/rockchip-iommu.c
+114-0Documentation/devicetree/bindings/iommu/ti,omap-iommu.yaml
+72-27drivers/iommu/amd/init.c
+641-25537 files not shown
+1,028-46543 files

LLVM/project 8dc7822llvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp

AArch64: Use m_GPtrAdd in selectAddrModeRegisterOffset

Replace the getVRegDef + G_PTR_ADD opcode check and operand accesses with an
m_GPtrAdd match binding the base and offset registers. NFC.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+5-9llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+5-91 files