[clang] make concept normalization a SFINAE context
It is incorrect to allow the substitution failures in concept normalization
to make the program ill-formed.
These can happen when comparing the equivalence of constraints for
redeclaration checking, and a failure here only means these declarations
are not equivalent.
For now, these diagnostics are simply discarded. It would be nice
if some day, as part of diagnostics for non-matching out-of-line definitions,
we would explain why matching failed for each candidate, and then add these
as notes explaining why the constraints were not equivalent.
[LifetimeSafety] Diagnose invalidated-global (#197220)
Teach lifetime safety invalidation diagnostics to handle origins that
escape through global or static storage before the referenced object is
invalidated. Previously they were skipped.
Follow up of #196680
Closes https://github.com/llvm/llvm-project/issues/195706
virtio(4): Allow virtio 0.9 BAR0 type to be memory rather than I/O.
This matches virtio>=1.0, and can't break working `hardware': any
existing virtio devices that worked must have reported I/O-type BAR0,
so they will continue to work; this will only enable previously
unusable virtio devices, reporting memory-type BAR0, to work.
Patch from Petri Koistinen.
PR kern/60247: virtio(4): legacy attach fails when BAR0 is MMIO
[RISCV] Make SFMM configuration instruction emit like VSETVLI (#196487)
Reuse the PseudoVSETVLI condition instead of its own condition.
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
math/py-numpy: Tweak workaround for missing log2l/log1pl/expm1l.
1. Put it in npy_math.c as needed by _umath_linalg.so.
2. Limit it to NetBSD<10, since NetBSD>=10 has at least stubs (just
like this workaround implements, in terms of double functions) if
not proper long double implementations (NetBSD>=11).
Fixes:
>>> import numpy
...
ImportError: /home/riastradh/pkgsrc/current/pkg/lib/python3.11/site-packages/numpy/linalg/_umath_linalg.so: Undefined PLT symbol "log1pl" (symnum = 20)
PR pkg/60256: devel/py-numpy: log1pl workaround no longer works around
Revert "[DirectX][ObjectYAML] Add ILDN part support" (#197348)
Reverts llvm/llvm-project#194508 due to
1. Compilation error on older cl.exe versions due to having a field
"DebugName" as a member of class "DebugName".
2. Layout violation between MC and Object
(see https://github.com/llvm/llvm-project/pull/197343).
[clang] Align x86 CR/DR intrinsic declarations with MSVC (#196886)
Align CR/DR and related MSR intrinsic declarations in intrin.h with
MSVC's x86/x64 signatures
Fixes #185457
[libclc] Apply hidden visibility to amdgpu / nvptx builds (#197235)
Summary:
This is not currently used because we force `--internalize` for
llvm-link, but if you ever want to link this normally we'd need hidden
visibility. SPIR-V does not currently handle hidden visibility, as it is
an extension still under discussion, so it is omitted for now.
[libclc] Create a static `.a` file in addition to the `.bc` file (#197247)
Summary:
This changes the libraries to be object libraries instead of static
libraries. We can then just link these into final static libraries that
contain everything we need.
The desire here is that we'd need static libraries if we wanted to move
away from `-mlink-builtin-bitcode` appraoches.
Effectively we'll have `libclc.a` next to `libclc.bc` and the idea is
that we could alternatively link it and let the target linker handle it.
[MIR] Save internal VirtRegMap state in MIR
Adds two optional fields to the per-vreg YAML record so MIR tests can
express VirtRegMap state that previously had no representation:
registers:
- { id: 1, class: vgpr_32, split-from: '%0', assigned-phys: '$vgpr5' }
Testing passes that consume sibling-register information (e.g.
InlineSpiller) requires constructing a VirtRegMap with split
relationships from a MIR test, which implies triggering live-range
splitting at minimum and make reproducers unnecessarily complicated.
So this change introduces a mechanism to serialize/deserialize the state
of the VirtRegMap pass.
Mechanism:
- For serialization:
- MIRPrinter emits the new fields only when the new -mir-emit-vrm
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[AMDGPU][test] Use mir test for regalloc issue
Use the newly introduced split-from flag to produce a more robust test case
for the hoistSpillInsideBB live-range update issue.
NFC
[MIR] Serialize/Deserialize MachineInstr::LRSplit attribute
The LRSplit MachineInstr flag is set by SplitKit on copies inserted for
live-range splitting.
Until now the flag had no MIR-text representation.
This patch fixes that so that it gets easier to reproduce/capture issues
that involves SplitKit.
Round-trip coverage in
llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir.
[CodeGen] Increase offset when calculating MBB hash (#196536)
Initially I was refactoring the test to not constantly update the hash
values for new GlobalISel nodes but I noticed that Offset is always zero
and assumed it should've been increased after each MBB. Fixing the
constant offset during MBB hash calculation.
---------
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
[OpenCL] Allow spirv-unknown-vulkan without shader stage environment (#197144)
Fix libclc spirv-unknown-vulkan target build error: `SPIR-V target
requires a valid shader stage environment`.
libclc clspv triple was canonicalized to `spirv-unknown-vulkan` in
6ef9671. Relax the restriction for libclc which is an OpenCL library
that a specific shader stage is not made yet.
