SystemZ: Replace AEXT128/ZEXT128/PAIR128 pseudos with patterns (#234297)
These pseudos only existed because GR128 values were untyped, so the
REG_SEQUENCE they expand to could not be written as a pattern. Now that
GR128 holds v2i64, select the extensions with REG_SEQUENCE output
patterns, and build GR128 pairs with a PAIR128 target node instead of a
custom inserter.
---------
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
SystemZ: Make v2i64 legal on subtargets without vector support (#234296)
Without the vector feature, the GR128 even/odd register pairs were
modeled with MVT::Untyped, since no 128-bit type was legal. Use v2i64
instead, which is what the pairs functionally are.
v2i64 values can be built from and split into their halves with
subregister operations. Everything else is expanded. Loads and stores
are split into i64 halves, so they don't tie up a register
pair. Bitcasts to and from f128 use the FPR pair halves.
This takes care to avoid changing the calling convention. Vectors that
would be broken down into v2i64 are still passed as individual i64
elements. Inline assembly operands still use untyped, which is listed
first in the GR128 type list, so i128 operands are not bitcast to
v2i64.
Co-authored-by: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
SystemZ: Add baseline tests for i64 vector handling (#234295)
Make sure nothing changes in future changes. Cover the ABI of other
i64-element vector types and a range of <2 x i64> operations on a
subtarget without the vector facility.
---------
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[libc++] Implement LWG3749: `common_iterator` should handle integer-class difference types (#233606)
Make `iterator_category` of `iterator_traits<common_iterator<I,S>>`
conditionally present only when `iter_difference_t<I>` is an integral
type.
Fixes #105291
[libc++][ci] Retarget the ARM BuildKite runners (#224107)
I enabled agent clusters in BuildKite since unclustered agents are not
supported anymore. As part of that, I created a new libcxx-builders-arm
queue to replace the existing queue. This patch switches the pipeline
definition so that new jobs start targeting the new queue with clustered
agents.
(cherry picked from commit 01edf187213105e35db8aef724a63f86241b6bd4)
py-importlib-metadata: updated to 9.1.0
v9.1.0
Features
- Removed support for Python 3.10, now end-of-life.
- Where a path supplies more than one metadata directory for a distribution,
as an interrupted or unclean upgrade may leave behind, discovery now prefers
the greater one by reverse lexicographic ordering of the directory names, so
the stale metadata no longer shadows the version in use.
Bugfixes
- A missing required metadata field (``Name`` or ``Version``) now raises a
``KeyError`` that names the field and identifies the distribution, which
``PathDistribution`` renders as its metadata path.
- Restored lazy validation of ``EntryPoint.value``, deferring the ``ValueError``
for an invalid value until a component is accessed or the entry point is
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[clang-repl][CodeGen] Add setOptLevel, #pragma clang repl optimize(N) (#214793)
clang-repl fixes its CodeGenOptions when the interpreter is created, so
the optimization level is the same for every input. This adds a way to
change it, similar to Cling:
- Add a new `CodeGenerator::StartModule` overload that takes a
CodeGenOptions, so the incremental path can start a module with
different codegen options than the ones fixed at construction.
- `Interpreter::setOptLevel` uses it to re-stage the pending module at
the new level.
- `#pragma clang repl optimize(N)` exposes this in source, the level
applies to the input the pragma appears in and stays in effect until
changed again.
assisted by claude-opus-5-5
[CIR] Support array coercions and flattened direct structs in CallConvLowering (#220207)
**Summary:**
- The AMDGPU classifier can pass or return an aggregate directly in
registers and can pack a 33-64 bit aggregate
into a [2 x i32] register pair. The CallConvLowering bridge handled
neither, so such signatures hit the NYI path. Handle both in
convertABIArgInfo/abiTypeToCIR.
**Changes:**
- `abiTypeToCIR` gets an `ArrayType` case
- A Direct struct argument with a null coerce type and `CanBeFlattened`
is split into one argument per field, as classic CGCall does. Returns,
unions and non-flattenable structs pass through unchanged.
- Added cir-opt coverage for 64-bit struct coerced to [2 x i32] and
larger struct passed directly in registers.
Addresses review feedback from @koparasy on #220197.
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[Clang] Rebuild lambda init-captures and their initialization in default initializers (#234793)
Fixes https://github.com/llvm/llvm-project/issues/196469.
Reland #196597 with the CodeGen crash fixed by rebuilding init-capture
initialization. Verified with focused Clang tests and runtime
capture/cleanup checks.
In addition to the added test, the main change since #196597 has been
```diff
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 3554e76a09cff5332a331e78aa54b2b8cfa9c0c2..43b0c86132172b3f8a42d4d2b3ebf379fc82a779 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -5801,13 +5801,10 @@ struct ImmediateCallVisitor : DynamicRecursiveASTVisitor {
struct EnsureImmediateInvocationInDefaultArgs
: TreeTransform<EnsureImmediateInvocationInDefaultArgs> {
- using Base = TreeTransform<EnsureImmediateInvocationInDefaultArgs>;
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SystemZ: Replace AEXT128/ZEXT128/PAIR128 pseudos with patterns
These pseudos only existed because GR128 values were untyped, so the
REG_SEQUENCE they expand to could not be written as a pattern. Now that
GR128 holds v2i64, select the extensions with REG_SEQUENCE output
patterns, and build GR128 pairs with a PAIR128 target node instead of a
custom inserter.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
SystemZ: Make v2i64 legal on subtargets without vector support
Without the vector feature, the GR128 even/odd register pairs were
modeled with MVT::Untyped, since no 128-bit type was legal. Use v2i64
instead, which is what the pairs functionally are.
v2i64 values can be built from and split into their halves with
subregister operations. Everything else is expanded. Loads and stores
are split into i64 halves, so they don't tie up a register
pair. Bitcasts to and from f128 use the FPR pair halves.
This takes care to avoid changing the calling convention. Vectors that
would be broken down into v2i64 are still passed as individual i64
elements. Inline assembly operands still use untyped, which is listed
first in the GR128 type list, so i128 operands are not bitcast to
v2i64.
Co-authored-by: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
