LLVM/project 466df93llvm/lib/Support APFloat.cpp, llvm/unittests/ADT APFloatTest.cpp

[APFloat] Fix sign bit corrupting exponent in unsigned FP8 formats (#223286)

`convertIEEEFloatToAPInt` unconditionally ORs the sign bit into the top
bit of the encoded value. `Float8E8M0FNU` and `Float8E5M3FNU` have no
sign bit (`hasSignedRepr = false`), so that top bit actually belongs to
the exponent field. Encoding a value with sign set therefore corrupts
the exponent, in one case colliding with the reserved NaN bit pattern.

Guard the OR with `hasSignedRepr`, matching the existing check in the
decode path (`initFromIEEEAPInt`).

Extend `ConvertLosesUnrepresentableSignAndZero` to also check
`bitcastToAPInt()` after dropping an unrepresentable sign, using `-1.0`
instead of `-2.0` so the corruption is actually visible in the bits.
DeltaFile
+8-4llvm/unittests/ADT/APFloatTest.cpp
+5-3llvm/lib/Support/APFloat.cpp
+13-72 files

LLVM/project d64a0a9llvm/include/llvm/Analysis ValueTracking.h, llvm/lib/Analysis ValueTracking.cpp

[ValueTracking] Make `getUnderlyingObjectsForCodegen()` preserve unidentified objects (#224584)

In some situations, it is useful to inspect the underlying objects of a
memory operation, even if they may alias with one another. A concrete
example comes from the approach to schedule DAG construction I've been
developing (see #205689) where these objects are used to infer that a
class of control dependencies between memory operations is redundant,
whereby eliminating the compile time cost of recording them. Update
`getUnderlyingObjectsForCodegen()` to return these objects.

Split from https://github.com/llvm/llvm-project/pull/205689
DeltaFile
+3-7llvm/lib/Analysis/ValueTracking.cpp
+4-1llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
+4-0llvm/include/llvm/Analysis/ValueTracking.h
+1-2llvm/lib/CodeGen/StackColoring.cpp
+12-104 files

LLVM/project 0da8b0fllvm/include/llvm/CodeGen ScheduleDAGInstrs.h, llvm/lib/CodeGen ScheduleDAGInstrs.cpp

[MachineScheduler](NFC) Remove separate handling for non-alias loads and stores (#224310)

The separate handling of non-alias loads and stores was always extra
complexity with no pay off. Remove this.

Split from #205689
DeltaFile
+13-39llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+2-10llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+15-492 files

LLVM/project 138ebe0llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp

WebAssembly: Don't duplicate implicit CALL operands in LowerCallResults

When recombining the CALL_PARAMS/CALL_RESULTS pseudo-pair into a real CALL,
LowerCallResults copied CallParams.uses() onto the new instruction. uses()
includes the implicit operands (implicit-def $arguments and the implicit
$sp32/$sp64 uses), which the freshly created CALL already carries. This
resulted in a duplicated implicit-def of $arguments. This avoids a future
verifier error.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-1llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+2-11 files

LLVM/project 72e9d33llvm/lib/CodeGen/SelectionDAG LegalizeTypes.h LegalizeVectorTypes.cpp, llvm/test/CodeGen/AArch64 arm64-zip.ll vselect-widen-mask-tree.ll

Reapply "[SelectionDAG] Recurse through mask expression trees in WidenVSELECTMask" (#217307)

WidenVSELECTMask currently handles only two mask shapes: a bare SETCC
or a single AND/OR/XOR of exactly two SETCCs. Anything deeper bails out
to the generic condition widening path, which often introduces
unnecessary narrow/widen roundtrips (xtn+sshll on AArch64,
packssdw+vpmovsxwd on X86).

Replace the hand-coded cases with a recursive widenMaskTree that walks
through SETCC, AND/OR/XOR, FREEZE, VECTOR_SHUFFLE, SELECT/VSELECT, and
all-ones/all-zeros BUILD_VECTORs.

I had to revert #188085 earlier this year. This PR resolves the flagged
issue and cleans up suggested approach to avoid that class of potential
errors.
DeltaFile
+209-51llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+200-0llvm/test/CodeGen/AArch64/vselect-widen-mask-tree.ll
+93-0llvm/test/CodeGen/X86/vselect-widen-mask-tree.ll
+31-34llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
+12-21llvm/test/CodeGen/AArch64/arm64-zip.ll
+25-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+570-1061 files not shown
+570-1107 files

LLVM/project 56e8f03llvm/lib/Target/Mips MipsISelLowering.cpp MipsRegisterInfo.td, llvm/lib/Target/Mips/AsmParser MipsAsmParser.cpp

[Mips] Introduce ABI-specific register names and accessors (#224284)

To accommodate the P32/P64 ABIs, we need to separate machine registers
from ABI register names and calling-convention roles. The existing
register IDs use OABI names, even when another ABI assigns a different
role to the same physical register.

As a first step, describe OABI, NABI and PABI names with
RegAltNameIndices. Extend TableGen's AsmMatcherEmitter with the opt-in
ShouldEmitMatchRegisterAltNameWithIndex flag, which generates
MatchRegisterAltName(StringRef, unsigned AltIdx). It matches only names
associated with the selected index, allowing the same spelling to
identify different registers across ABIs.

Use the indexed matcher in shared MIPS register lookup for the assembler
and named-register lowering, retaining compatibility aliases and
diagnostics for deprecated spellings.

Add ABI accessors for argument, temporary, saved and return registers,

    [2 lines not shown]
DeltaFile
+101-78llvm/lib/Target/Mips/MipsRegisterInfo.td
+121-18llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+28-96llvm/lib/Target/Mips/MipsISelLowering.cpp
+20-97llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+71-0llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+44-21llvm/utils/TableGen/AsmMatcherEmitter.cpp
+385-31016 files not shown
+593-34322 files

LLVM/project cdae908llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 externally-used-copyables.ll

[SLP]Pass operand info and context to TTI cost queries

Feed operand value info, the context instruction, cast context hints,
and the actual select condition predicate to the TTI cost queries, so
target discounts that depend on them (fused fmul/fma pricing, folded
read-modify-write, constant or uniform operands) apply to both scalar
and vector sides of the SLP cost model. Also make the reversed-store
query describe the stored value instead of the pointer, per the
getMemoryOpCost contract.

Assisted-by: Cursor

Reviewers: RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/224931
DeltaFile
+126-71llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+110-19llvm/test/Transforms/SLPVectorizer/AMDGPU/elementwise-fma-operand1.ll
+26-10llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
+7-6llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
+8-4llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
+5-5llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll
+282-1153 files not shown
+289-1229 files

LLVM/project 72fb4b9llvm/lib/Target/AArch64 AArch64ExpandPseudoInsts.cpp, llvm/test/CodeGen/AArch64 kcfi-bti.ll blr-bti-preserves-operands.mir

AArch64: Don't duplicate the branch's implicit defs in call pseudo expansion

These pseudo expansions started with an implicit LR def and are replaced with a
new instruction with a different LR def. Previously this would copy the old
instruction's operand list, merging with the newly build instruction def list.
Avoid creating a redundant def with inconsistent dead flags. This avoids failing
a future verifier check.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+12-12llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
+8-4llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+2-2llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
+1-1llvm/test/CodeGen/AArch64/kcfi-bti.ll
+23-194 files

LLVM/project 4c7e907llvm/lib/Target/ARM ARMExpandPseudoInsts.cpp, llvm/test/CodeGen/ARM cmse-vlldm-no-reorder.mir

ARM: Don't duplicate the LR def when expanding call pseudos

Several pseudo expansions in ARMExpandPseudoInsts built a real call and
then copied the pseudo's operands onto the new instruction. Each of these
call opcodes declares LR as an implicit-def, but the original instruction
already had that. The original def may have been marked as dead, so the result
would be a redundant operand with an inconsistent dead flag. This avoids
a failure in a future verifier check.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+35-19llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+1-1llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
+36-202 files

LLVM/project 4b99afbmlir/include/mlir/IR Remarks.h

[MLIR][NFC] Drop sentinel leftovers from DenseMapInfo<Remark> (#224612)

`DenseMap` no longer uses sentinel keys, and the `getEmptyKey` and
`getTombstoneKey` members of `DenseMapInfo<Remark>` were removed in
#200633 and #201991. Two leftovers stayed behind, the `"<EMPTY_KEY>"`
comparison at the top of `isEqual` and the static dummy `MLIRContext`
that used to back the sentinel remarks.

The comparison is also wrong. A remark literally named `<EMPTY_KEY>`
compares unequal to any other remark, including one with a matching
hash, which breaks the hash and equality contract. This change removes
both leftovers and adds a comment saying what the specialization
compares, which is location, remark name, combined category name and
kind.

No behaviour change for any remark with a normal name. Existing Remark
unit tests and `mlir/test/Pass/remark-final.mlir` cover the
specialization through `RemarkEmittingPolicyFinal`.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+2-17mlir/include/mlir/IR/Remarks.h
+2-171 files

FreeBSD/doc b82a2e6website/content/en/cgi cgi-style-responsive.pl

cgi: New design for the FreeBSD website

Implement new design for the cgi scripts, based on c9c518d9db
DeltaFile
+509-0website/content/en/cgi/cgi-style-responsive.pl
+509-01 files

FreeBSD/ports 0767741mail/imap-tools Makefile Makefile.crates

mail/imap-tools: update to 1.13.0
DeltaFile
+449-301mail/imap-tools/distinfo
+223-149mail/imap-tools/Makefile.crates
+1-4mail/imap-tools/Makefile
+673-4543 files

FreeBSD/ports 0767740net/s3req Makefile Makefile.crates

net/s3req: update to 1.3.1
DeltaFile
+267-151net/s3req/distinfo
+132-74net/s3req/Makefile.crates
+1-2net/s3req/Makefile
+400-2273 files

FreeBSD/src a4ea046sys/dev/sound/pci hdspe-pcm.c hdsp-pcm.c

snd_hdsp*: malloc(9) with M_WAITOK

Perform the allocations outside the lock section so that we can use
M_WAITOK. Holding the lock here is actually not really necessary and we
could just as well remove it, but keep it for consistency.

Sponsored by:   The FreeBSD Foundation
MFC after:      1 month
Reviewed by:    kib
Differential Revision:  https://reviews.freebsd.org/D59079

(cherry picked from commit b5c1ab6c8f2811278b801084713a6618f3b783d3)
DeltaFile
+15-2sys/dev/sound/pci/hdspe-pcm.c
+15-2sys/dev/sound/pci/hdsp-pcm.c
+30-42 files

FreeBSD/src 1490193sys/dev/sound dummy.c

snd_dummy: Bump primary channel count

Makes it easier to test scenarios involving more than 1 primary channels
per direction.

Sponsored by:   The FreeBSD Foundation
MFC after:      2 weeks
Reviewed by:    markj
Differential Revision:  https://reviews.freebsd.org/D59085

(cherry picked from commit 358fe149f591028945a8e5a51dff9121a2358c85)
DeltaFile
+2-2sys/dev/sound/dummy.c
+2-21 files

FreeBSD/src eefd556sys/dev/sound/pcm dsp.c

sound: Prefer idle primary channels when allocating

dsp_chn_alloc() stopped at the first primary channel that was either
idle or already had vchans. Since the list is walked in order, the first
channel matched both conditions once it had been used, so every client
after the first was stacked onto it as a vchan and the remaining primary
channels were never allocated at all.

This is invisible on devices with a single primary channel, but not on
those which provide several. snd_emu10kx(4), for instance, registers
four primary channels for its front device, each able to run with its
own rate.

Look for an idle primary channel first, and only fall back to sharing
one that already has vchans when there is none left.

Sponsored by:   The FreeBSD Foundation
MFC after:      2 weeks
Reviewed by:    markj

    [3 lines not shown]
DeltaFile
+17-7sys/dev/sound/pcm/dsp.c
+17-71 files

LLVM/project a734ad9llvm/lib/Target/Hexagon HexagonFrameLowering.cpp, llvm/test/CodeGen/Hexagon copy-to-combine-const64.mir

Hexagon: Don't duplicate the PC def when converting a return to L4_return

When replacing a PS_jmpret return with L4_return in the epilogue, the code built
L4_return which automatically inserted pc and r29 implicit-defs. This then copied
the original return's implicit operands, duplicating the overlapped pc operand
(which also would have inconsistent dead flags). Also update a few mir test inputs
which demonstrate the duplicated operand pattern.

This avoids a future verifier check failure.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+6-5llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+1-1llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
+1-1llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir
+8-73 files

LLVM/project 16cbb06llvm/docs/CommandGuide llvm-dwarfdump.md, llvm/test/tools/llvm-dwarfdump/X86 coverage.test

[llvm-dwarfdump][LineCov] Add --variable-coverage-maybe-undefined option (#220855)

This patch adds a `--variable-coverage-maybe-undefined` flag to
llvm-dwarfdump as part of the recently implemented feature that measures
DWARF coverage of local variables in terms of source lines. This causes
the IR-level analysis to consider variables live if they are defined on
any path, and therefore include lines where the variable may be
undefined. By default, variables must be defined on all paths to be
counted.

Additionally, it includes fixes for a few issues found by @SLTozer and
myself after merging the previous patches:
- Variables not present in the DWARF information that appear in the
baseline are now included in the output.
- The assertion that there are no `undef`/`poison` variable locations in
the IR has been removed, as in some circumstances it is possible to have
a `#dbg_declare(poison)` at `-O0`.
- A small error where entries were inserted into the file name map while
iterating through it has been fixed.
DeltaFile
+191-79llvm/test/tools/llvm-dwarfdump/X86/Inputs/coverage.ll
+133-68llvm/test/tools/llvm-dwarfdump/X86/Inputs/coverage-opt.ll
+84-10llvm/test/tools/llvm-dwarfdump/X86/coverage.test
+57-28llvm/tools/llvm-dwarfdump/Coverage.cpp
+10-2llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
+7-0llvm/docs/CommandGuide/llvm-dwarfdump.md
+482-1871 files not shown
+484-1887 files

FreeBSD/ports cb6f78ex11/xfd Makefile distinfo

x11/xfd: update to 1.1.6

PR:             298704
Approved by:    x11 (maintainer, arrowd)

Sponsored by:   tipi.work
DeltaFile
+3-3x11/xfd/distinfo
+1-2x11/xfd/Makefile
+4-52 files

NetBSD/src jJkoLNMtests/net/ipsec t_ipsec_policy.c

   tests/ipsec/t_ipsec_policy.c -- appease clang

   Cast to (void) not (void *) to explicitly ignore a function return
   value, even though that value is a pointer.

   Might fix the clang builds (should go part way at least).
VersionDeltaFile
1.3+3-3tests/net/ipsec/t_ipsec_policy.c
+3-31 files

LLVM/project 40f30eallvm/test/CodeGen/X86 sub-of-not.ll vector-bo-select.ll

[X86] Prefer sub-of-not for vector inc-of-add (#207695)

Avoids lengthening the dependency chain for vector conditional
increments by preferring sub-of-not for vectors. Keeps existing
inc-of-add for scalars.

Fixes #167441
DeltaFile
+78-81llvm/test/CodeGen/X86/vector-shift-lut.ll
+64-64llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
+36-36llvm/test/CodeGen/X86/masked-urem.ll
+36-36llvm/test/CodeGen/X86/masked-udiv.ll
+33-32llvm/test/CodeGen/X86/vector-bo-select.ll
+35-12llvm/test/CodeGen/X86/sub-of-not.ll
+282-2613 files not shown
+313-2739 files

OpenBSD/src aNSgZ78usr.bin/tmux window-copy.c

   Do not trim all lines to make a zero line grid which reflow does not like, from
   Kaixuan Li.
VersionDeltaFile
1.431+2-2usr.bin/tmux/window-copy.c
+2-21 files

LLVM/project ec707f4flang/docs ModFiles.md, flang/include/flang/Support Fortran-features.h

[flang][cuda] Restrict the MANAGED(IMPLICIT) spelling to module files
DeltaFile
+22-1flang/docs/ModFiles.md
+14-0flang/test/Semantics/CUDA/cuda-managed-implicit-modfile.cuf
+4-3flang/include/flang/Support/Fortran-features.h
+3-2flang/lib/Parser/Fortran-parsers.cpp
+4-0flang/lib/Semantics/mod-file.cpp
+3-0flang/lib/Support/Fortran-features.cpp
+50-66 files

LLVM/project d5401c5flang/include/flang/Parser parse-tree.h, flang/lib/Parser Fortran-parsers.cpp

[flang][cuda] Record implicit managed attribution in module files

An attribute the compiler applied under -gpu=mem:managed is written into the
module file the same way a user-written one is, so a reader cannot tell them
apart. It then treats the attribute as a user requirement: allocating such a
component in a DEVICE object is rejected, and the memory space the user did
ask for on the object no longer wins.

Spell the distinction in the module file as MANAGED(IMPLICIT), modelled on
INTENT(IN): CUDA-data-attr gains an optional parenthesized qualifier, carried
by a new CUDADataAttrSpec parse-tree node in AttrSpec and ComponentAttrSpec.
ATTRIBUTES(...) keeps the bare attribute, so the qualifier cannot be written
there.

The attribute itself is still written out, so a component keeps the same
memory space no matter which options a consumer is compiled with.

Also stop an implicitly applied attribute from making a module a definer of
CUDA symbols. Without this, adding -gpu=mem:managed to a module's build
rejects its OpenACC-only consumers over an attribute the user never wrote.
DeltaFile
+76-0flang/test/Semantics/CUDA/cuda-managed-implicit-modfile.cuf
+29-9flang/lib/Semantics/resolve-names.cpp
+19-3flang/lib/Semantics/mod-file.cpp
+13-2flang/include/flang/Parser/parse-tree.h
+10-2flang/lib/Parser/Fortran-parsers.cpp
+4-2flang/test/Parser/cuf-sanity-tree.CUF
+151-182 files not shown
+159-188 files

OPNSense/core f94982bsrc/opnsense/www/js/widgets Services.js, src/opnsense/www/js/widgets/Metadata Core.xml

system: revert latest service widget changes

As discussed internally there are no more complaints and this makes
it a bit harder to see the status at first glance, especially for the
color blind.  Let's try to not tempt fate any more than we already
have on the subject.

This reverts commit f2815fabed8e5f1b2ebc3a8ff98df867082256e9.
This reverts commit 73e154151b724a7bca4125d6a9b757001a53dbcf.
DeltaFile
+18-23src/opnsense/www/js/widgets/Services.js
+2-2src/opnsense/www/js/widgets/Metadata/Core.xml
+20-252 files

LLVM/project 419a152mlir/include/mlir/Dialect/OpenMP OpenMPOps.td OpenMPClauses.td, mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[MLIR][OpenMP] Support for dispatch construct with clauses nocontext & novariants (#215877)

Support for dispatch construct with clauses nocontext & novariants clauses in MLIR

This patch adds the omp.dispatch operation to the OpenMP dialect, along
with the nocontext and novariants clauses, the verifier, and LLVM IR
translation. It is limited to the MLIR layer. Flang lowering follows in
later patches.

Part 1 of 3 of the !$omp dispatch support.
This is derived from
[203320](https://github.com/llvm/llvm-project/pull/203320) (split into 3
parts).

This also Fixes[
#203317](https://github.com/llvm/llvm-project/issues/203317)

---------

Co-authored-by: Sunil Kuravinakop <kuravina at pe31.hpc.amslabs.hpecorp.net>
DeltaFile
+118-0mlir/test/Dialect/OpenMP/ops.mlir
+111-0mlir/test/Target/LLVMIR/openmp-dispatch.mlir
+62-0mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
+31-0mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
+30-0mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+15-0mlir/test/Target/LLVMIR/openmp-todo.mlir
+367-02 files not shown
+378-18 files

OpenBSD/src mmuNgcNusr.bin/tmux tmux.h cmd-resize-pane.c

   Do not unzoom when resizing a floating pane that was created with -A.
   Similarly, skip hidden floating panes when changing Z order. Reported by Clark
   Wang.
VersionDeltaFile
1.75+14-5usr.bin/tmux/cmd-join-pane.c
1.377+13-1usr.bin/tmux/window.c
1.69+3-2usr.bin/tmux/cmd-resize-pane.c
1.1443+2-1usr.bin/tmux/tmux.h
+32-94 files

LLVM/project 468d2e7clang/docs InternalsManual.md

[Clang] Document when to use ExtWarn and Extension (#223440)
DeltaFile
+11-0clang/docs/InternalsManual.md
+11-01 files

LLVM/project 017d946llvm/test/MC/AArch64 retired-feature-names.s retired-register-names.s

fixup! Amend after PR comments
DeltaFile
+0-21llvm/test/MC/AArch64/retired-names.s
+18-0llvm/test/MC/AArch64/retired-register-names.s
+9-0llvm/test/MC/AArch64/retired-feature-names.s
+27-213 files

LLVM/project 1758952llvm/include/llvm/ExecutionEngine/Orc LLJIT.h, llvm/include/llvm/SandboxIR Region.h

[llvm] Adjust remaining LLVM_ABI annotation issues (#224619)

Following up from #224293. Some annotations cannot be automatically
adjusted by the ids-check-helper and idt:
* Only headers under llvm/include are parsed. Source files and internal
headers are not.
* Headers are parsed in release mode, so debug-only declarations are
invisible.
* idt ignores private declarations.

These were found while performing a dylib build on Windows.

The effort to build LLVM as a dylib is tracked in #109483.
DeltaFile
+20-21llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+2-2llvm/lib/Transforms/Vectorize/VPlan.h
+2-2llvm/include/llvm/SandboxIR/Region.h
+1-1llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
+1-1llvm/include/llvm/Support/SMTAPI.h
+1-1llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
+27-282 files not shown
+29-308 files