[lldb] Add synthetic support to formatter_bytecode.py (#183804)
Updates formatter_bytecode.py to support compilation and disassembly for
synthetic formatters, in other words support for multiple functions
(signatures).
This includes a number of other changes:
* String parsing and encoding have bugs fixed
* CLI args are updated, primarily to support an output file
* Added uleb encoding/decoding support
This work is a prelude the ongoing work of a Python to formatter
bytecode compiler. The python compiler to emit assembly, and this module
(formatter_bytecode) will compile it into binary bytecode.
[mlir][arith] Add `exact` to `index_cast{,ui}` (#183395)
The `exact` flag with the following semantics
> If the `exact` attribute is present, it is assumed that the index type
width
> is such that the conversion does not lose information. When this
assumption
> is violated, the result is poison.
can be added to index_cast and index_castui operations. This unlocks
the following lowerings:
* index_cast (signed) exact -> trunc nsw
* index_castui (unsigned) exact -> trunc nuw
* index_castui nneg exact -> trunc nuw nsw
Changes:
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[VPlan] Support unrolling/cloning masked VPInstructions.
Account for masked VPInstruction when verifying the operands in the
constructor. Fixes a crash when trying to unroll VPlans for predicated
early exits.
NAS-139909 / 26.0.0-BETA.1 / Validate and sync registration details on token updates (#18298)
This PR adds token validation and registration details synchronization
for TrueNAS Connect. Previously, JWT tokens received during registration
finalization and heartbeat token rotation were stored without validating
required fields, and the heartbeat path did not update
`registration_details` when a new token was received — leaving stale
data in the database. Now both paths use a shared
`decode_and_validate_token` util that verifies the token contains
account/system id before persisting, and `registration_details` is
updated alongside the token to always reflect the current token's
claims.
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Will Deacon:
"The diffstat is dominated by changes to our TLB invalidation errata
handling and the introduction of a new GCS selftest to catch one of
the issues that is fixed here relating to PROT_NONE mappings.
- Fix cpufreq warning due to attempting a cross-call with interrupts
masked when reading local AMU counters
- Fix DEBUG_PREEMPT warning from the delay loop when it tries to
access per-cpu errata workaround state for the virtual counter
- Re-jig and optimise our TLB invalidation errata workarounds in
preparation for more hardware brokenness
- Fix GCS mappings to interact properly with PROT_NONE and to avoid
corrupting the pte on CPUs with FEAT_LPA2
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[mlir][LLVM] Let decomposeValue/composeVale pad out larger types (#183825)
Currently, as pointed out in the reviews for #183405, decomposeValues
and composeValues should be able to emit zexts and truncations for cases
like i48 and vector<3xi16> becoming i32s but currently that's an assert.
This commit fixes that limitation.
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Merge tag 'pci-v7.0-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci fixes from Bjorn Helgaas:
- Update MAINTAINERS email address (Shawn Guo)
- Refresh cached Endpoint driver MSI Message Address to fix a v7.0
regression when kernel changes the address after firmware has
configured it (Niklas Cassel)
- Flush Endpoint MSI-X writes so they complete before the outbound ATU
entry is unmapped (Niklas Cassel)
- Correct the PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value, which broke VMM use
of PCI capabilities (Bjorn Helgaas)
* tag 'pci-v7.0-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value
PCI: dwc: ep: Flush MSI-X write before unmapping its ATU entry
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Revert "[VPlan] Remove manual region removal when simplifying for VF and UF. (#181252)"
This reverts commit 9c53215d213189d1f62e8f6ee7ba73a089ac2269.
Appears to cause crashes with ordered reductions, revert while I
investigate
libpmc: Update event definitions for AMD Zen
The pmu event definitions for AMD Zen 5 was updated since it was
imported into the tree. As a bonus I also updated the recommended json
counters for Zen 1-3 even though we do not use that file yet.
Sponsored by: Netflix
Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/2048
hwpmc: Initial support for AMD IBS
This patch adds support for AMD IBS. It adds a new class of performance
counter that cotains two events: ibs-fetch and ibs-op events. Unlike
most existing sampled events, IBS events provide a number of values
containing extra information regarding the sample. To support this we
use the existing callchain event, and introduce a new flag for multipart
payloads. The first 8 bytes of the pc_sample contains a header that
defines up to four payloads.
Sponsored by: Netflix
Reviewed by: imp,mhorne
Pull Request: https://github.com/freebsd/freebsd-src/pull/2022
InstCombine: Stop applying nofpclass from use nofpclass attribute
Functionally reverts a80d4329ce96856a02bd279c800c3d08619da4c9, with new test.
This should be applied somewhere, but this is the wrong place.
Fixes regression reported after #182444
hwpmc: Fix PMC flags for AMD Zen cores
The PMC flags available for DF and L3 counters were not all implemented.
More importantly, the field encodings for the L3 counters changed in an
incompatible way between Family 17h and Family 19h. Similarly, the
field encodings for the DF coutners changed between Family 19h and 1Ah.
I also added the precise retire flag for the 3rd core counter.
Lastly, I added a warning in the jevent parser because ignoring the
unknown fields results in counters incorrectly programmed. We should
not just ignore that.
Sponsored by: Netflix
Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/2040
[WebAseembly] Fix -Wunused-variable in #181755
This variable ends up being unused in builds without assertions. Mark it
[[maybe_unused]] per the coding standards.
[BOLT][AArch64] Add a unittest for compare-and-branch inversion. (#181177)
Checks that isReversibleBranch() returns false
- when the immediate value is 63 and needs +1 adjustment
- when the immediate value is 0 and needs -1 adjustment
Checks that reverseBranchCondition() adjusts
- the opcode
- the immediate operand if necessary (+/-1)
- the register operands if necessary (swap)
