FreeBSD/src cbb7441sbin/nvmecontrol telemetry.c

nvmecontrol: Pass 1 to uint8_t arg

The rae arg is uint8_t (which we then shift over to the right bit. Pass
'1' instead of 'true' here to match the interface. While true is
promoted to (uint8_t)1, we don't use it as a bool in read_logpage().

Fixes:                  5322eec86ae4 ("nvmecontrol: Always set the RAE bit on telemetry-log requests")
Sponsored by:           Netflix
Reviewed by:            chs
Differential Revision:  https://reviews.freebsd.org/D55060
DeltaFile
+2-2sbin/nvmecontrol/telemetry.c
+2-21 files

LLVM/project 9727cfemlir/lib/IR SymbolTable.cpp

[NFC][MLIR] Simplify lookup of nested symbols (#179362)

Consolidate the handling of nested symbols in the loop over nested
references. This is an NFC refactor to make it simpler to enforce symbol
visibility here.
DeltaFile
+12-20mlir/lib/IR/SymbolTable.cpp
+12-201 files

LLVM/project 9bc1a89llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+9-72 files

LLVM/project 294e43cllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-minnum.ll simplify-demanded-fpclass-maxnum.ll

InstCombine: Handle minnum/maxnum in SimplifyDemandedFPClass (#179299)

DeltaFile
+111-180llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll
+109-169llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
+11-3llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+2-2llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+233-3544 files

LLVM/project 6981686llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU frame-index-disjoint-s-or-b32.ll eliminate-frame-index-scalar-bit-ops.mir

AMDGPU: Fold frame indexes into disjoint s_or_b32

Some pointer adds get turned into ors, and sometimes and is
performed on pointers for masking.
DeltaFile
+220-0llvm/test/CodeGen/AMDGPU/frame-index-disjoint-s-or-b32.ll
+161-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
+6-2llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+387-23 files

NetBSD/pkgsrc-wip 76b480ddovecot24 PLIST Makefile.common, dovecot24/files dovecot.sh

dovecot24: added dovecot version 2.4.x

contributed by Sad Clouds

I made some small changes /mail/ -> /wip/ to give it a chance to build
in wip/ instead of mail/, but there are some TODO items.
DeltaFile
+788-0dovecot24/PLIST
+73-0dovecot24/Makefile.common
+52-0dovecot24/options.mk
+50-0dovecot24/Makefile
+33-0dovecot24/files/smf/manifest.xml
+32-0dovecot24/files/dovecot.sh
+1,028-06 files not shown
+1,094-012 files

LLVM/project 572dabdclang/lib/CIR/CodeGen CIRGenCleanup.cpp CIRGenCleanup.h

[CIR] Propagate correct flags to EHCleanupScope (#179137)

Propagate correct flags to the EHCleanupScope, which will be needed to
trigger the invoke branch inside `emitCallLikeOp`. This code will make
ClangIR trigger NYI for cleanups that need to be called inside the
cleanup scope, but now they are produced in the main function scope,
which is wrong
DeltaFile
+14-2clang/lib/CIR/CodeGen/CIRGenCleanup.cpp
+4-5clang/lib/CIR/CodeGen/CIRGenCleanup.h
+18-72 files

LLVM/project 03d467bllvm/lib/Analysis InlineCost.cpp

[InlineCost] Replace getAllocatedType with getAllocationSize (#178355)

This now should correctly compute the size of the static alloca if it
was declared as an array.

Co-authored-by: Claude Opus 4.5 <noreply at anthropic.com>
DeltaFile
+12-11llvm/lib/Analysis/InlineCost.cpp
+12-111 files

FreeBSD/ports a87d5c2science/elmerfem Makefile

science/elmerfem: adding the forgotten docs
DeltaFile
+12-0science/elmerfem/Makefile
+12-01 files

FreeBSD/src 7f031c9sys/dev/acpica acpi.c

acpi: Move sysctl tree set up at end of initialization

Setting up the sysctl tree later:
1. Fixes not de-registering sysctl knobs on failure to attach.
2. Avoids having inconsistent knob values exposed during a brief moment.

Reviewed by:    imp, obiwac
MFC after:      2 weeks
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D54926
DeltaFile
+61-59sys/dev/acpica/acpi.c
+61-591 files

FreeBSD/src e401e6dsys/dev/acpica acpi.c acpivar.h

acpi: 'hw.acpi.s4bios' sysctl: Change type to bool, expand description

Another boolean, indicating hardware support, will be introduced in next commit.

Thanks to the previous commit modifying sysctl_handle_bool(), this
change is backwards-compatible with old programs using an integer in and
out of sysctl(3).

Reviewed by:    obiwac
MFC after:      2 weeks
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D54626
DeltaFile
+3-3sys/dev/acpica/acpi.c
+1-1sys/dev/acpica/acpivar.h
+4-42 files

FreeBSD/src 406da39sys/kern kern_sysctl.c

sysctl(9): Booleans: Accept integers to ease knob conversion

In sysctl_handle_bool(), if the output buffer (for the old value) has
room for exactly 4 bytes (sizeof(int)), then output the current boolean
value as an integer rather than a 'uint8_t'.  Conversely, if 4 bytes
exactly remain in the input buffer (for the new value), treat them as an
integer and derive the new boolean value from it.

Doing so allows to convert existing integer syscstl knobs that are
interpreted as a boolean into true boolean ones while staying
backwards-compatible.

That brings no drawback as no code currently uses sysctl_handle_bool()
as part of a series of calls to sysctl_handle_*() functions for
(de)serialization of some compound structure.  If that case ever
materializes, it can be easily solved, e.g., by creating
a sysctl_handle_bool_strict() variant.

In the future, we might want to go further and generally be more liberal

    [10 lines not shown]
DeltaFile
+33-5sys/kern/kern_sysctl.c
+33-51 files

FreeBSD/src 53bb020sys/amd64/amd64 machdep.c

amd64: parse_memmap(): Move comment about size at proper place

While here, declare 'size' only in the relevant block.

No functional change (intended).

MFC after:      1 week
Sponsored by:   The FreeBSD Foundation
DeltaFile
+9-10sys/amd64/amd64/machdep.c
+9-101 files

LLVM/project 983d866mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp, mlir/test/Dialect/XeGPU subgroup-distribute-unit.mlir

[MLIR] [XeGPU] SG distribution: adding tests for alloca/create_memdesc and remove unncessary check from shape_cast op lowering (#179018)

This PR add subgroup distribution tests for memref.alloca and
xegpu.create_memdesc ops.
It also removes the slice layout requirement for shape_cast.
DeltaFile
+37-8mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
+2-15mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+39-232 files

LLVM/project 4177b32llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.struct.tbuffer.store.d16.ll llvm.amdgcn.raw.tbuffer.store.d16.ll

[AMDGPU][GlobalISel] Add tbuffer store d16 RegBankLegalize rule (#179411)

DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
+2-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+11-105 files

FreeBSD/src a4f0e93sys/arm64/vmm vmm_reset.c vmm_hyp.c

arm64/vmm: Set and use the fine-grained traps

Set the Fine-grained trap registers to trap any features we don't
support. These are expected to be more useful when we support nested
virtualisation, so for now just the base features and GICv3 are not
trapped.

As nested virtualisation will require VHE we only set the fine-grained
trap registers when VHE is used.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D54687
DeltaFile
+405-0sys/arm64/vmm/vmm_reset.c
+22-0sys/arm64/vmm/vmm_hyp.c
+16-0sys/arm64/vmm/arm64.h
+443-03 files

FreeBSD/src 095a787sys/arm64/vmm vmm_arm64.c arm64.h

arm64/vmm: Add HYP_FEAT_FGT{,2}

Add the macros and detection for Fine-grained traps (FEAT_FGT and
FEAT_FGT2).

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D54686
DeltaFile
+12-0sys/arm64/vmm/vmm_arm64.c
+2-0sys/arm64/vmm/arm64.h
+14-02 files

FreeBSD/src 4f82ce5sys/arm64/include hypervisor.h

arm64: Add the Fine-Grained Trap registers

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D54685
DeltaFile
+1,744-0sys/arm64/include/hypervisor.h
+1,744-01 files

FreeBSD/src 2f3f505sys/dev/virtio/p9fs virtio_p9fs.c

virtio_p9fs: Use VIRTIO_SIMPLE_PNPINFO

This allows us to also use the common VIRTIO_SIMPLE_PROBE and to have
devmatch load the driver when detected.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D54684
DeltaFile
+3-7sys/dev/virtio/p9fs/virtio_p9fs.c
+3-71 files

FreeBSD/src 32d1f18lib/libc/aarch64/string memset_resolver.c Makefile.inc

libc/aarch64: Add memset for a 64 byte dc zva

On arm64 we can use the "dc zva" instruction to zero memory. The CPU
tells software if the instruction is implemented, and if so the size
and alignment it will use.

When the size is 64-bytes the Arm Optimized Routines implementation of
memset can use dc zva to zero memory, and has a build flag to skip
checking.

Use this flag to build a version of memset that will be used when this
assumption is true.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D54776
DeltaFile
+13-0lib/libc/aarch64/string/memset_resolver.c
+3-1lib/libc/aarch64/string/Makefile.inc
+4-0lib/libc/aarch64/string/memset_zva64.S
+20-13 files

FreeBSD/src f0516edlib/libc/aarch64/string Makefile.inc memcpy.S

libc/aarch64: Split out the MOPS functions

This allows static binaries to only include the functions they
reference.

Reviewed by:    imp
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D54775
DeltaFile
+14-0lib/libc/aarch64/string/Makefile.inc
+0-2lib/libc/aarch64/string/memcpy.S
+0-1lib/libc/aarch64/string/memset.S
+14-33 files

FreeBSD/src 00f6839lib/libc/aarch64/string Makefile.inc

libc/aarch64: Add a Makefile.inc dependency

If we update Makefile.inc it may be to change the contents of these
files.

Reviewed by:    imp
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D54774
DeltaFile
+2-2lib/libc/aarch64/string/Makefile.inc
+2-21 files

FreeBSD/src 64f7e3csys/kern uipc_socket.c uipc_usrreq.c, sys/netinet tcp_syncache.c

sockets: let protocols be responsible for socket buffer mutexes

Sockets that implement their own socket buffers (marked with PR_SOCKBUF)
are now also responsible for initialization of socket buffer mutexes in
pr_attach and for destruction in pr_detach (or pr_close).

This removes a big bunch of reported LORs, as now WITNESS is able to see
that tcp(4) socket buffer mutex and netlink(4) socket buffer mutex are two
different things.  Distinct names also improve diagnostics for blocked
threads.

This also removes a hack from unix(4), where we used to mtx_destroy().
Also removes an innocent bug from unix(4) where for accept(2)-ed socket
soreserve() was called twice.  This one was innocent since first call to
soreserve() was asking for 0 bytes of space.

This slightly increased amount of pasted code in TCP's syncache_socket().
The problem is that while for sockets created with socket(2) it is
pr_attach responsible for call to soreserve() (including !PR_SOCKBUF

    [7 lines not shown]
DeltaFile
+40-37sys/kern/uipc_socket.c
+8-9sys/kern/uipc_usrreq.c
+12-3sys/netinet/tcp_syncache.c
+8-2sys/netlink/netlink_domain.c
+68-514 files

LLVM/project 0b4147ellvm/lib/Target/X86 X86ISelDAGToDAG.cpp, llvm/test/CodeGen/X86 fold-add-32.ll dag-large-offset.ll

[X86] Restrict offset folding into address mode in 16-bit mode (#179399)

https://github.com/coreboot/seabios/blob/106549a4362f6b499da522f8f8f5ed9f98388f87/src/pnpbios.c#L70
has code that looks like
```
extern int X;
unsigned f(void) { return (unsigned)&X - 0xf0000; }
```

which compiles (-O1 or above, -fno-pic) to

```
.code16
leal X-983040, %eax  # R_386_16 relocation, [-65535,65535]
```
in 16-bit mode. This is rejected by both GNU Assembler and LLVM
integrated assembler (after #176827).

Restrict offset folding in 16-bit mode to the range [-65535, 65535].
DeltaFile
+47-0llvm/test/CodeGen/X86/fold-add-32.ll
+0-47llvm/test/CodeGen/X86/dag-large-offset.ll
+45-0llvm/test/CodeGen/X86/fold-add-16.ll
+5-0llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+97-474 files

LLVM/project e39d282clang/lib/Headers ptrauth.h, clang/lib/Sema SemaChecking.cpp

[CodeGen][AArch64] ptrauth intrinsic to safely construct relative ptr (#142047)

ptrauth intrinsic to safely construct relative ptr for swift coroutines.

A ptrauth intrinsic for swift co-routine support that allows creation of
signed pointer
 from offset stored at address relative to the pointer.

Following C-like pseudo code (ignoring keys,discriminators) explains its
operation:
      let rawptr = PACauth(inputptr);
return PACsign( rawptr + signextend64( *(int32*)(rawptr+addend) ))

What: Authenticate a signed pointer, load a 32bit value at offset
'addend' from pointer,
       add this value to pointer, sign this new pointer.
 builtin: __builtin_ptrauth_auth_load_relative_and_sign
 intrinsic: ptrauth_auth_resign_load_relative
DeltaFile
+570-0llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-relative-load.ll
+90-8llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+28-10llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+36-0llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+36-0clang/lib/Headers/ptrauth.h
+28-0clang/lib/Sema/SemaChecking.cpp
+788-188 files not shown
+870-1914 files

LLVM/project 38a8d6bllvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp, llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp

[NFC] Make constrainSelectedInstRegOperands return void (it always returned true)
DeltaFile
+65-49llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+34-56llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+41-31llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+44-22llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+24-30llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+14-9llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+222-1977 files not shown
+243-22113 files

FreeBSD/src dbe9fa0. Makefile.inc1

Makefile.inc1: Don't mark GCC broken for riscv64

Reviewed by:    mhorne
Differential Revision:  https://reviews.freebsd.org/D54969
DeltaFile
+0-3Makefile.inc1
+0-31 files

LLVM/project dfbf4ebllvm/lib/Target/AMDGPU GCNSchedStrategy.cpp

[AMDGPU][Scheduler] Fix incorrect region index in EXPENSIVE_CHECKS (#179461)

#177206 exposed a pre-existing typo in EXPENSIVE_CHECKS in the
scheduler's rematerialization stage. When rematerializing a register
that depends on other registers, the dependent registers should be live
at the live-ins of the rematerialized register's using region, but not
necessarily at the live-ins of its defining region, as it is written
right now.

This fixes that and also hoists the check from the loop on regions where
the rematerialized register is live, since it's only supposed to run
once for the using region anyway. This fixes the following unit tests
which were failing when building with EXPENSIVE_CHECKS.
- `CodeGen/AMDGPU/copy-hoist-no-spills.ll`
- `CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir`
DeltaFile
+27-30llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+27-301 files

LLVM/project 50f8d63llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+9-72 files

LLVM/project 299761dllvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: add mir test for sgpr s16 unmerge (#179440)

DeltaFile
+65-0llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+65-01 files