LLVM/project d4f4913mlir/lib/Dialect/SPIRV/IR SPIRVTypes.cpp

[mlir][spirv][nfc] Use function argument type in TypeCapabilityVisitor switch (#195918)

Addresses post commit review from #195796.
DeltaFile
+3-3mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
+3-31 files

LLVM/project eeaa29cllvm/lib/CodeGen MachineFunction.cpp, llvm/lib/MC MCDwarf.cpp

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c
DeltaFile
+67-67llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+30-0llvm/lib/MC/MCDwarf.cpp
+15-15llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+14-0llvm/lib/CodeGen/MachineFunction.cpp
+4-4llvm/test/CodeGen/AMDGPU/debug-frame.ll
+2-2llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
+132-885 files not shown
+145-9011 files

LLVM/project cd98648llvm/utils/gn/build sync_source_dir.py, llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn] use action() instead of copy() for libcxx headers (#195948)

copy() doesn't handle file deletions. Use an action() that syncs the
output directory with the input list via a response file, removing files
that are no longer in the list.

This works because if files are added or removed, ninja's command line
tracking re-runs the script, and if contents of existing files change,
ninja's input mtime checking reruns it.

This also makes the remove_float_h workaround unnecessary.

Motivated by all the recent header removals in libc++.
DeltaFile
+59-0llvm/utils/gn/build/sync_source_dir.py
+20-16llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+79-162 files

FreeNAS/freenas 49cce26src/middlewared/middlewared/plugins sysdataset.py

Fix
DeltaFile
+121-35src/middlewared/middlewared/plugins/sysdataset.py
+121-351 files

LLVM/project bc5f2c9llvm/docs AMDGPUUsage.rst, llvm/include/llvm/Support AMDGPUAddrSpace.h

[NFC][AMDGPU] Reserve address space 16

This is used in downstream.
DeltaFile
+2-0llvm/include/llvm/Support/AMDGPUAddrSpace.h
+1-0llvm/docs/AMDGPUUsage.rst
+3-02 files

LLVM/project c979debllvm/docs AMDGPUUsage.rst, llvm/include/llvm/Support AMDGPUAddrSpace.h

[NFC][AMDGPU] Reserve address space 16

This is used in downstream.
DeltaFile
+2-16llvm/include/llvm/Support/AMDGPUAddrSpace.h
+2-0llvm/docs/AMDGPUUsage.rst
+4-162 files

LLVM/project 8578a0aclang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow PointerFlowAnalysis.cpp PointerFlowFormat.cpp, clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageAnalysis.cpp

[SSAF][WPA] Add "no-op" PointerFlow and UnsafeBufferUsage analysis (#193089)

Added 'no-op' PointerFlow and UnsafeBufferUsage analyses to convert
summary data into AnalysisResult, which DerivedAnalysis can then consume.

Also, refactored the PointerFlow and UnsafeBufferUsage serialization
for code sharing.

rdar://174874942

---------

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Co-authored-by: Jan Korous <jkorous at apple.com>
DeltaFile
+140-0clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowWPATest.cpp
+131-0clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageWPATest.cpp
+128-0clang/test/Analysis/Scalable/PointerFlow/Inputs/wpa-result.json
+122-0clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageAnalysis.cpp
+116-0clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowAnalysis.cpp
+58-38clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowFormat.cpp
+695-3827 files not shown
+1,229-6233 files

LLVM/project 1a8d5d4clang/include/clang/Analysis/Analyses/LifetimeSafety Origins.h, clang/lib/Analysis/LifetimeSafety Origins.cpp FactsGenerator.cpp

[LifetimeSafety] Track per-field origins for record types
DeltaFile
+237-4clang/test/Sema/warn-lifetime-safety.cpp
+82-8clang/lib/Analysis/LifetimeSafety/Origins.cpp
+59-24clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
+39-10clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+21-12clang/lib/Analysis/LifetimeSafety/LiveOrigins.cpp
+4-6clang/test/Sema/warn-lifetime-safety-dangling-field.cpp
+442-642 files not shown
+447-648 files

LLVM/project 3cbd5fdclang/include/clang/Analysis/Analyses/LifetimeSafety Origins.h Facts.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp Origins.cpp

[LifetimeSafety][NFC] Refactor OriginList to OriginNode tree
DeltaFile
+129-131clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+42-30clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
+38-30clang/lib/Analysis/LifetimeSafety/Origins.cpp
+5-6clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h
+5-5clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+3-3clang/lib/Analysis/LifetimeSafety/LiveOrigins.cpp
+222-2053 files not shown
+231-2149 files

LLVM/project b9fc55eclang-tools-extra/clang-tidy/readability ImplicitBoolConversionCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix `implicit-bool-conversion` C ternary condition false positive (#195913)

Fixes #195604
DeltaFile
+16-0clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion.c
+8-2clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
+3-0clang-tools-extra/docs/ReleaseNotes.rst
+3-0clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
+30-24 files

LLVM/project 397d99dflang/lib/Optimizer/Transforms/CUDA CUFAddConstructor.cpp, flang/test/Fir/CUDA cuda-constructor-2.f90

[flang][cuda] Fix unregistered allocator (#195924)

#194290 changed how we register the constructor and made an early return
which then miss to add the constructor to `llvm.mlir.global_ctors` which
leads to runtime failure because the allocators for CUDA Fortran are not
registered.
DeltaFile
+93-95flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
+3-1flang/test/Fir/CUDA/cuda-constructor-2.f90
+96-962 files

LLVM/project c96aedellvm/lib/Target/AMDGPU SIFrameLowering.cpp SIMachineFunctionInfo.h, llvm/test/CodeGen/AMDGPU amdgpu-spill-cfi-saved-regs.ll

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
DeltaFile
+2,998-0llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
+17-0llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+10-0llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+9-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+3,036-05 files

LLVM/project 6393333llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll

[AMDGPU] Use register pair for PC spill

Change-Id: Ibedeef926f7ff235a06de65a83087c151f66a416
DeltaFile
+4,331-4,331llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,742-1,740llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+1,562-1,560llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,462-1,460llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+1,238-1,236llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+1,030-1,028llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+11,365-11,35589 files not shown
+18,153-18,04495 files

LLVM/project 928abbellvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll gfx-callable-argument-types.ll

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+3,568-2,598llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,912-1,913llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+2,700-12llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+631-631llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+505-510llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+394-399llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+9,710-6,063108 files not shown
+14,825-9,527114 files

LLVM/project 1d23e15llvm/lib/Target/AMDGPU SIFrameLowering.cpp, llvm/test/CodeGen/AMDGPU debug-frame.ll eliminate-frame-index-v-add-u32.mir

[AMDGPU] Emit entry function Dwarf CFI

Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.

Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+1,405-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+204-12llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
+134-6llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
+114-10llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
+42-5llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+34-0llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
+1,933-3322 files not shown
+2,044-5028 files

LLVM/project 00248ddclang/lib/Driver/ToolChains Gnu.cpp, clang/test/Driver amdgpu-unwind.cl

[Clang] Default to async unwind tables for amdgcn

To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.

There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.

Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
DeltaFile
+26-0clang/test/Driver/amdgpu-unwind.cl
+1-0clang/lib/Driver/ToolChains/Gnu.cpp
+27-02 files

LLVM/project b506b98llvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir

[AMDGPU] Implement CFI for non-kernel functions

This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.

Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+2,136-0llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
+1,671-1llvm/test/CodeGen/AMDGPU/debug-frame.ll
+16,779-16993 files not shown
+22,889-1,13299 files

LLVM/project 7db2461llvm/include/llvm/MC MCDwarf.h, llvm/lib/CodeGen MachineOperand.cpp

[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU

While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).

Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
DeltaFile
+186-0llvm/lib/MC/MCDwarf.cpp
+106-0llvm/lib/MC/MCParser/AsmParser.cpp
+91-1llvm/include/llvm/MC/MCDwarf.h
+75-0llvm/lib/CodeGen/MIRParser/MIParser.cpp
+75-0llvm/lib/MC/MCAsmStreamer.cpp
+58-0llvm/lib/CodeGen/MachineOperand.cpp
+591-115 files not shown
+995-721 files

LLVM/project fae74b2llvm/test/Transforms/LoopVectorize/VPlan/AArch64 call-decisions.ll

[VPlan] Add VPlan printing test for call widening decisions. (NFC) (#195930)

Add VPlan-printing test for
https://github.com/llvm/llvm-project/pull/195518.
DeltaFile
+110-0llvm/test/Transforms/LoopVectorize/VPlan/AArch64/call-decisions.ll
+110-01 files

FreeBSD/ports 67729f6net-mgmt/check_ssl_cert distinfo Makefile

net-mgmt/check_ssl_cert: update to 2.100.0

Release Notes:
  https://github.com/matteocorti/check_ssl_cert/releases/tag/v2.100.0
DeltaFile
+3-3net-mgmt/check_ssl_cert/distinfo
+1-1net-mgmt/check_ssl_cert/Makefile
+4-42 files

LLVM/project 461e473llvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlan.cpp

[VPlan] Add isFreeScalarIntrinsic helper (NFC). (#195929)

Split off from https://github.com/llvm/llvm-project/pull/195518.
DeltaFile
+7-18llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+8-0llvm/lib/Transforms/Vectorize/VPlan.cpp
+1-4llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+4-0llvm/lib/Transforms/Vectorize/VPlanHelpers.h
+20-224 files

LLVM/project 7d1a8f1flang/lib/Optimizer/Analysis AliasAnalysis.cpp, flang/test/Analysis/AliasAnalysis alias-analysis-zero-offset-view-chain.fir alias-analysis-pack-array.fir

[flang] Fix FIR AliasAnalysis for zero-offset view chains (#192710)

When subroutine `f` below is inlined, the `ACCImplicitData` pass fails
to recognize that `b` is already covered by the enclosing `!$acc data
deviceptr`. The deviceptr clause operates on a box (`fir.embox` result)
while the inner `acc.serial` uses the underlying ref.
`fir::AliasAnalysis` traces both back through the full def-chain, where
an upstream sliced `fir.embox` (from `a(:,5)`) sets
`approximateSource=true`, causing `MayAlias` instead of `MustAlias`. The
pass falls back to implicit `copyin`/`copyout`, causing a segfault.

```fortran
module test_mod
  real, allocatable :: a(:,:)
contains
  subroutine f(b)
    real, dimension(*) :: b
    !$acc data deviceptr(b(1:100))
    !$acc serial

    [23 lines not shown]
DeltaFile
+71-0flang/test/Analysis/AliasAnalysis/alias-analysis-zero-offset-view-chain.fir
+43-0flang/test/Transforms/OpenACC/acc-implicit-data.fir
+25-0flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
+2-4flang/test/Analysis/AliasAnalysis/alias-analysis-pack-array.fir
+141-44 files

FreeBSD/poudriere 169bdf0.builds freebsd.yml

Add sourcehut CI config
DeltaFile
+16-0.builds/freebsd.yml
+16-01 files

FreeBSD/ports 90aa381graphics/drm-515-kmod Makefile, graphics/drm-61-kmod Makefile

graphics/*drm*: remove CONFLICTS with now-deleted drm-510
DeltaFile
+1-2graphics/drm-latest-kmod/Makefile
+1-2graphics/drm-515-kmod/Makefile
+1-2graphics/drm-61-kmod/Makefile
+1-2graphics/drm-66-kmod/Makefile
+1-1graphics/nvidia-drm-515-kmod/Makefile
+1-1graphics/nvidia-drm-61-kmod/Makefile
+6-102 files not shown
+8-128 files

FreeBSD/ports 01291f5devel/py-pytest-regressions Makefile, devel/py-thinc Makefile

*/py-*: Update version requirement of *_DEPENDS
DeltaFile
+4-4devel/py-pytest-regressions/Makefile
+2-2devel/py-thinc/Makefile
+2-2devel/py-thinc8/Makefile
+2-2graphics/py-cartopy/Makefile
+2-2graphics/py-gdal/Makefile
+2-2graphics/py-h3/Makefile
+14-14117 files not shown
+159-159123 files

FreeBSD/ports ee25cb3textproc/rubygem-github-markup distinfo Makefile

textproc/rubygem-github-markup: Update to 6.0.0

Changes:        https://github.com/github/markup/blob/master/HISTORY.md
DeltaFile
+3-3textproc/rubygem-github-markup/distinfo
+1-1textproc/rubygem-github-markup/Makefile
+4-42 files

FreeBSD/ports 4f32b01misc/p5-Business-ISBN-Data distinfo Makefile

misc/p5-Business-ISBN-Data: Update to 20260502.001

Changes:        https://metacpan.org/dist/Business-ISBN-Data/changes
DeltaFile
+3-3misc/p5-Business-ISBN-Data/distinfo
+1-1misc/p5-Business-ISBN-Data/Makefile
+4-42 files

FreeBSD/ports ef5bfe9www/rubygem-bullet_train-themes distinfo Makefile

www/rubygem-bullet_train-themes: Update to 1.44.1

Changes:        https://github.com/bullet-train-co/bullet_train-core/releases
DeltaFile
+3-3www/rubygem-bullet_train-themes/distinfo
+1-1www/rubygem-bullet_train-themes/Makefile
+4-42 files

FreeBSD/ports e730f98www/rubygem-bullet_train-super_load_and_authorize_resource distinfo Makefile

www/rubygem-bullet_train-super_load_and_authorize_resource: Update to 1.44.1

Changes:        https://github.com/bullet-train-co/bullet_train-core/releases
DeltaFile
+3-3www/rubygem-bullet_train-super_load_and_authorize_resource/distinfo
+1-1www/rubygem-bullet_train-super_load_and_authorize_resource/Makefile
+4-42 files

FreeBSD/ports 311fe67www/rubygem-bullet_train-scope_validator distinfo Makefile

www/rubygem-bullet_train-scope_validator: Update to 1.44.1

Changes:        https://github.com/bullet-train-co/bullet_train-core/releases
DeltaFile
+3-3www/rubygem-bullet_train-scope_validator/distinfo
+1-1www/rubygem-bullet_train-scope_validator/Makefile
+4-42 files