[NVPTX] Fix the build after ce465594e239. (#201268)
ce465594e239 (#201177) added sm_90 / PTX ISA 7.8 instructions to
lower-aggr-copies.ll, so we need to guard the RUN line appropriately.
[AMDGPU] Added min operation for MCExprs (#199746)
The min operation is needed in MC Expressions for a future change that
caps the max number of registers used for indirect calls.
---------
Co-authored-by: JoshuaGrindstaff <jgrindst at amd.com>
[DAGCombiner] Remove no longer tested VP_MUL handling. (#201238)
We no longer use VP_MUL in SelectionDAG on RISC-V so this code isn't
tested.
This effectively reverts db6de1a20f75cbfe1024f41e64ad39def91fa70f
[RISCV] Make VSETTM/VSETTK not affect the VSETVL emit (#197890)
VSETTM/TK will modify VTYPE, but it only affects the TM/TK bits. This
modification is safe for other RVV operations. The TM/TK value will be
maintained in insertVSETMTK.
[clangd] Handle dependent call to function with explicit object parameter in InlayHintVisitor (#201264)
Dependent calls do not yet have the implicit object argument preprended
to the CallExpr's argument list, so the first argument should not be
expected to be present and dropped in this case.
Fixes https://github.com/llvm/llvm-project/issues/198588
[clang][CUDA] Avoid ambiguity in host/device template specializations (#201049)
This commit changes SemaOverload to resolve an otherwise diagnosed
ambiguity between addresses of template specializations of functions
that are overloaded for both device and host. Similar to how it works
for non-templated function overloads, these changes prioritizes the
specializations that corresponds to the target of the owning function,
i.e. if compiling for host, the address of the host specialization takes
precedence over the device specialization and vice versa.
Fixes https://github.com/llvm/llvm-project/issues/199299
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
[BOLT] Fix data race in multi-threaded DWP type unit processing and DWP type unit duplication (#197359)
## Summary
This PR fixes a race condition in LLVM BOLT's
DIEBuilder::buildTypeUnits() that is triggered when DWARF5 split-DWARF
(.dwo/.dwp) inputs are processed with multi-threaded CU processing.
Concurrent invocations from different worker threads share the same DWP
type-unit state, which results in duplicated DIE extraction, assertion
failures, and intermittent crashes. The fix serializes buildTypeUnits()
for DWP inputs via a function-local static std::mutex, leaving the
non-DWO fast path unchanged.
## Problem Description
When BOLT processes DWARF debug info with --debug-thread-count=4
--cu-processing-batch-size=4 on testcase
dwarf5-df-types-dup-dwp-input.test, multiple threads concurrently call
DIEBuilder::buildTypeUnits() on shared DWP type units. Since type units
within a DWP file are shared across compilation units, multiple threads
may attempt to extract DIEs from the same type unit simultaneously,
violating the assertion.
[5 lines not shown]
[lldb] Enable MyST colon_fence and deflist extensions (NFC) (#201250)
Enable the colon_fence and deflist MyST parser extensions in the LLDB
docs configuration. This is a preparatory step for converting the
remaining reStructuredText documentation pages to Markdown, where these
two extensions are needed to translate RST admonition directives
(:::{note}) and definition lists.
Context:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/
[docs][Kaleidoscope] fix function name InitializeModuleAndManagers in Kaleidoscope (#199601)
### Description
resloves #199477
The Kaleidoscope tutorial was not fully updated with the new Pass
Manager. This pr aligns the tutorial doc with the example code.
### Changes
- Use `InitializeModuleAndManagers` instead of
`InitializeModuleAndPassManager`.
- Remove `TheModule->setDataLayout(TheJIT->getDataLayout());` in line
141, as the `setDataLayout` was introduced later.
- Use `KaleidoscopeJIT` instead of `my cool jit` as the ModuleName, to
align with the final code.
[M68k] Add to LINK_COMPONENTS to fix BUILD_SHARED_LIBS build (#201248)
Fixes: 6897c5e24ce5 ("[M68k][MC] Add MC support for PCI w/ base
displacement addressing mode (#200696)")
[NVPTX] NVVMIntrRange: Handle maxntid > UINT32_MAX. (#201245)
Previously we computed the overall maxntid and downcast it to unsigned
int. This is not correct; it can be larger than UINT32_MAX.
This would cause reads of tid.xyz and ntid.xyz to have incorrect range
information. Also if maxntid was an exact multiple of 2^32, we'd get an
ICE (because we'd incorrectly think that maxntid is 0).
[CIR] Implement destruction of TLS and static global references (#200227)
This implements destruction of lifetime-extended reference temporaries
used to initialize TLS or static duration reference variables.
Assisted-by: Cursor / claude-opus-4.7
