LLVM/project d0cd530llvm/lib/Transforms/Scalar LoopInterchange.cpp

[LoopInterchange] Mark getAddRecCoefficient with static (#203624)

As this function is a file-scope non-member function, it's better to
mark it with static.
DeltaFile
+2-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+2-21 files

LLVM/project 2f8a39dllvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange lcssa-incoming-value-is-not-instr.ll

[LoopInterchange] Fix crash when followLCSSA returns constant (#203515)

Similar as the case in ##201069, `followLCSSA` may return a constant
value, but it was cast to Instruction unconditionally. We need to
explicitly check whether the returned value is an Instruction or not.

Fix #203375.
DeltaFile
+70-0llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
+7-5llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+77-52 files

LLVM/project ae026a5llvm/lib/Target/AMDGPU AMDGPU.td, llvm/test/CodeGen/AMDGPU branch-relaxation-gfx1250.ll

[AMDGPU] Enable S_ADD_PC_I64 on gfx1251 (#203613)
DeltaFile
+2-1llvm/lib/Target/AMDGPU/AMDGPU.td
+1-1llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
+3-22 files

LLVM/project c4c30cellvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/PhaseOrdering/X86 avg.ll

[SLP] Vectorize full insertvalue buildvector sequences

Treat a complete chain of insertvalue instructions building a homogeneous
literal struct from scalars as a buildvector, like insertelement sequences.
The scalars are vectorized into one vector; the aggregate is rebuilt from it
via a stack store + load, or stored directly when its only user is a store.

insertvalue is routed through the existing insertelement buildvector paths
(type/index helpers, reordering, tree build, cost model, min-bitwidth, and
codegen). Only single-index, non-vector inserts building from an undef
aggregate are handled.

Fixes #43353

Reviewers: hiraditya, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/200274
DeltaFile
+196-31llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+14-14llvm/test/Transforms/PhaseOrdering/X86/avg.ll
+4-6llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
+1-9llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
+215-604 files

LLVM/project 3abb8d8mlir/lib/Conversion/XeGPUToXeVM XeGPUToXeVM.cpp, mlir/lib/Conversion/XeVMToLLVM XeVMToLLVM.cpp

[MLIR][XeVM] Add xevm.extf op as the inverse of xevm.truncf (#203124)

Add a new xevm.extf operation that extends f8/bf8/f4 values to f16/bf16,
mirroring the existing xevm.truncf op, together with its lowering in
XeVMToLLVM.

Lowering details (XeVMToLLVM):

- bf8/f8 -> f16 via __builtin_IB_bf8tohf_16 / __builtin_IB_hf8tohf_16.

- bf8/f8 -> bf16 via f16 -> f32 (convert_float16) -> bf16
(__builtin_IB_ftobf_16).

- e2m1 (fp4) -> f16/bf16 via __builtin_IB_shfl_idx4_lut and
__builtin_IB_shfl_idx4_to_fp16_8_packed (LUT 7 for f16, 5 for bf16).

Adds the op definition and verifier, conversion/roundtrip/invalid unit
tests, and f8 and fp4 GPU round-trip integration tests.

Adds arith.extf to xevm.extf lowering and arith.truncf to xevm.truncf
lowering in XeGPU to XeVM conversion and unit tests.
DeltaFile
+149-25mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
+164-0mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_raw.mlir
+146-0mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
+120-0mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4_bf16.mlir
+119-0mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4.mlir
+114-0mlir/test/Conversion/XeVMToLLVM/xevm_mx-to-llvm.mlir
+812-257 files not shown
+1,231-3713 files

FreeNAS/freenas f4cf5acsrc/middlewared/middlewared/test/integration/utils shell.py, tests/api2 test_audit_websocket.py test_reporting_realtime.py

NAS-141383 / 27.0.0-BETA.1 / Fix a few API tests (#19133)

* Reporting realtime shows stats on boot pool and so we should expect
it.

* pam / auth stack now properly reports in *audit* messages why the
authentication failed (minimally including PAM error code).

* harden our webshell tests

(cherry picked from commit 7546c612061dc7ccbca9751a1d5103f943de033d)
DeltaFile
+47-28src/middlewared/middlewared/test/integration/utils/shell.py
+5-1tests/api2/test_audit_websocket.py
+5-1tests/api2/test_reporting_realtime.py
+57-303 files

LLVM/project ba338cfcmake/Modules GetTripleCMakeSystemName.cmake

Match android and cygwin from environment
DeltaFile
+13-5cmake/Modules/GetTripleCMakeSystemName.cmake
+13-51 files

LLVM/project 87d29e3llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

[AMDGPU] NFC: Drop constexpr from getFlavor*Name functions (#203603)

It seems specifying these as constexpr was causing some buildbot
failures due to llvm_unreachable --

```
[1/123] Building CXX object lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o
FAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o 
/usr/bin/c++ -DLLVM_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/path/to/build.AArch64.Release.main/lib/Target/AMDGPU -I/path/to/llvm-project/llvm/lib/Target/AMDGPU -I/path/to/build.AArch64.Release.main/include -I/path/to/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-array-bounds -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fvisibility=hidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -c /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
In file included from /path/to/llvm-project/llvm/include/llvm/ADT/Hashing.h:49,
                 from /path/to/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,
                 from /path/to/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:17,
                 from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h:17,
                 from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSubtarget.h:17,
                 from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNRegPressure.h:20,
                 from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h:16,
                 from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:17,
                 from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp:14:
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorName(llvm::AMDGPU::InstructionFlavor)':

    [56 lines not shown]
DeltaFile
+3-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+3-31 files

LLVM/project aa16f7dllvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/test/CodeGen/AMDGPU shl.v2i64.ll pk-lshl-add-u64.ll

[AMDGPU] Add gfx1251 V_PK_LSHL_ADD_U64
DeltaFile
+736-0llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
+241-0llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
+52-0llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
+46-0llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+39-0llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
+34-0llvm/test/MC/AMDGPU/gfx1251_err.s
+1,148-04 files not shown
+1,167-210 files

LLVM/project b312ae0llvm/lib/Target/AMDGPU VOP3PInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU packed-u64.ll

[AMDGPU] Add gfx1251 V_PK_ADD/SUB_NC_U64 (#203607)
DeltaFile
+1,313-0llvm/test/CodeGen/AMDGPU/packed-u64.ll
+96-0llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
+72-0llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
+58-0llvm/test/MC/AMDGPU/gfx1251_err.s
+16-1llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+15-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1,570-213 files not shown
+1,622-719 files

ELF Tool Chain/elftoolchain 4380trunk/tests/libtest/bin make-test-scaffolding, trunk/tests/libtest/driver driver_main.c test_driver.1

libtest: Simplify the test(3) & test_driver(3) APIs.

- Signal errors in setup/teardown functions using a plain
  'bool'.
- Do not place test tags and test descriptions in the C
  source code for a test.  These are better placed elsewhere
  alongside other metadata associated with the test.
DeltaFile
+4-103trunk/tests/libtest/driver/driver_main.c
+17-78trunk/tests/libtest/examples/simple_example.c
+2-53trunk/tests/libtest/bin/make-test-scaffolding
+0-32trunk/tests/libtest/lib/test.h
+2-20trunk/tests/libtest/lib/test.3
+2-19trunk/tests/libtest/driver/test_driver.1
+27-3054 files not shown
+29-33010 files

LLVM/project f248fecllvm/lib/Transforms/Scalar LoopInterchange.cpp

address review
DeltaFile
+1-1llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+1-11 files

LLVM/project 327ce1bcompiler-rt/test/fuzzer lit.cfg.py

[Fuzzer] Use the internal shell by default (#203450)

The external shell is going away soon and the internal shell is superior
in most ways (platform compatibility, performance, debugging). This now
causes no test failures and is blocking deprecation of the external
shell, so switch over.
DeltaFile
+1-13compiler-rt/test/fuzzer/lit.cfg.py
+1-131 files

LLVM/project ce09519llvm/test/Transforms/ConstraintElimination geps-unsigned-predicates.ll

[ConstraintElim] Add test with negative offset and NUW only GEP (NFC) (#203614)

Add test currently mis-compiled with NUW only GEP.

https://alive2.llvm.org/ce/z/7G8uE3
DeltaFile
+11-0llvm/test/Transforms/ConstraintElimination/geps-unsigned-predicates.ll
+11-01 files

LLVM/project 5f51294clang/docs ReleaseNotes.rst, clang/lib/Sema SemaOverload.cpp

Fix contextual implicit conversions to int: with _Atomic (#203522)

PerformContextualImplicitConversion was performing
default-lvalue-conversions, then basing decisions on viable conversion
functions on this type However, when we then went to add the candidates
we were using the 'old' value (pre-conversion) of the type, resulting in
us regaining the lost 'atomic' from the default Lvalue conversion.

This patch updates the 'from' variable to be the converted value so all
conversions are done post-conversion.

Fixes: #201770
DeltaFile
+25-0clang/test/Sema/atomic-conversions-to-int.cpp
+1-0clang/docs/ReleaseNotes.rst
+1-0clang/lib/Sema/SemaOverload.cpp
+27-03 files

FreeNAS/freenas a31a99d

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 7546c61src/middlewared/middlewared/test/integration/utils shell.py, tests/api2 test_audit_websocket.py test_reporting_realtime.py

NAS-141383 / 27.0.0-BETA.1 / Fix a few API tests (#19133)

* Reporting realtime shows stats on boot pool and so we should expect
it.

* pam / auth stack now properly reports in *audit* messages why the
authentication failed (minimally including PAM error code).

* harden our webshell tests
DeltaFile
+47-28src/middlewared/middlewared/test/integration/utils/shell.py
+5-1tests/api2/test_audit_websocket.py
+5-1tests/api2/test_reporting_realtime.py
+57-303 files

LLVM/project 0526807clang/test/AST tyloctype_alignment.cpp

[clang][z/OS] Add test for TypeLoc tail padding alignment (#202710)

This adds a test for the TypeLoc tail padding fix that was merged in
commit 89305c3.
DeltaFile
+10-0clang/test/AST/tyloctype_alignment.cpp
+10-01 files

LLVM/project 12d95c6llvm/lib/Transforms/Scalar LICM.cpp, llvm/test/Transforms/LICM vector-insert.ll

Revert "[LICM] Allow hoisting of InsertElementInst's past non-hoistable InsertElementInsts" (#203611)

Reverts llvm/llvm-project#200532
DeltaFile
+0-572llvm/test/Transforms/LICM/vector-insert.ll
+0-87llvm/lib/Transforms/Scalar/LICM.cpp
+0-6592 files

LLVM/project 6494225llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp SPIRVNonSemanticDebugHandler.h, llvm/test/CodeGen/SPIRV/debug-info debug-function-declaration-path-null.ll debug-function-declaration-skip-type-not-in-debug-type-regs.ll

[SPIRV] Emit NonSemantic DebugFunctionDeclaration for DISubprograms.
DeltaFile
+161-12llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+73-10llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+46-0llvm/test/CodeGen/SPIRV/debug-info/debug-function-declaration-path-null.ll
+45-0llvm/test/CodeGen/SPIRV/debug-info/debug-function-declaration-skip-type-not-in-debug-type-regs.ll
+44-0llvm/test/CodeGen/SPIRV/debug-info/debug-function-declaration.ll
+44-0llvm/test/CodeGen/SPIRV/debug-info/debug-function-declaration-composite-scope.ll
+413-226 files

FreeNAS/freenas 10ce85dsrc/middlewared_docs generate_docs.py

🪗
DeltaFile
+40-0src/middlewared_docs/generate_docs.py
+40-01 files

LLVM/project 6a5147allvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp SPIRVNonSemanticDebugHandler.h, llvm/test/CodeGen/SPIRV/debug-info debug-function-declaration-path-null.ll debug-function-declaration-skip-type-not-in-debug-type-regs.ll

[SPIRV] Emit NonSemantic DebugFunctionDeclaration for DISubprograms.
DeltaFile
+164-12llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+73-10llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+46-0llvm/test/CodeGen/SPIRV/debug-info/debug-function-declaration-path-null.ll
+45-0llvm/test/CodeGen/SPIRV/debug-info/debug-function-declaration-skip-type-not-in-debug-type-regs.ll
+44-0llvm/test/CodeGen/SPIRV/debug-info/debug-function-declaration.ll
+44-0llvm/test/CodeGen/SPIRV/debug-info/debug-function-declaration-composite-scope.ll
+416-226 files

FreeBSD/ports ae0e659lang/python314 pkg-plist

lang/python314: fix plist

Event: Works Must Run
DeltaFile
+2-2lang/python314/pkg-plist
+2-21 files

FreeNAS/freenas a13dc7dsrc/middlewared_docs generate_docs.py changelog.py

remove repetitive word "field" from every change summary
DeltaFile
+13-5src/middlewared_docs/generate_docs.py
+6-6src/middlewared_docs/changelog.py
+19-112 files

LLVM/project 2dec950llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Extend to getReasonName
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+1-11 files

FreeNAS/freenas e12e8d6src/middlewared_docs generate_docs.py

consistent boldface method links
DeltaFile
+4-4src/middlewared_docs/generate_docs.py
+4-41 files

LLVM/project e3c3a18llvm/lib/Target/AMDGPU AMDGPU.td, llvm/test/CodeGen/AMDGPU branch-relaxation-gfx1250.ll

[AMDGPU] Enable S_ADD_PC_I64 on gfx1251
DeltaFile
+2-1llvm/lib/Target/AMDGPU/AMDGPU.td
+1-1llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
+3-22 files

FreeBSD/ports 34ab40awww/evcc distinfo Makefile

www/evcc: update to 0.309.0

Changes:        https://github.com/evcc-io/evcc/releases
DeltaFile
+7-7www/evcc/distinfo
+2-2www/evcc/Makefile
+9-92 files

FreeBSD/ports c00e595www/grist-core distinfo Makefile

www/grist-core: update to 1.7.15

Changes:        https://github.com/gristlabs/grist-core/releases
DeltaFile
+5-5www/grist-core/distinfo
+1-1www/grist-core/Makefile
+6-62 files

FreeBSD/ports 3f9d5b9lang/python-doc-html distinfo

lang/python-doc-html: populate 3.14

Event: Works Must Run
DeltaFile
+5-1lang/python-doc-html/distinfo
+5-11 files