LLVM/project c99848c — llvm/lib/Target/AArch64 AArch64.h AArch64SLSHardening.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+14-5llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+7-0llvm/lib/Target/AArch64/AArch64.h
+21-52 files

LLVM/project aea7325 — llvm/lib/Target/AArch64 AArch64.h AArch64SLSHardening.cpp, llvm/lib/Target/X86 X86TargetMachine.cpp X86.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+39-6llvm/lib/Target/X86/X86IndirectThunks.cpp
+14-5llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+18-1llvm/lib/Target/X86/X86.h
+7-0llvm/lib/Target/AArch64/AArch64.h
+1-1llvm/lib/Target/X86/X86TargetMachine.cpp
+79-135 files

LLVM/project e5a911f — llvm/lib/Target/SPIRV SPIRVAPI.cpp, llvm/unittests/Target/SPIRV SPIRVAPITest.cpp

[SPIR-V][NewPM] Use runCodeGenPipeline in SPIRVTranslate (#238451)

SPIRVTranslate will be able to pick NewPM once SPIR-V defaults to it
DeltaFile
+18-0llvm/unittests/Target/SPIRV/SPIRVAPITest.cpp
+4-12llvm/lib/Target/SPIRV/SPIRVAPI.cpp
+22-122 files

FreeBSD/src 6a99232 — . Makefile.inc1

Makefile.inc1: Fix bare $ characters

The '$' characters inside awk commands need to be $$ when appearing
inside a Makefile.  Without this, we generate empty src and src-sys
packages.

Reported by:    Stefan Grundmann
Fixes:          a8be89928930 ("build: Support got")
MFC after:      1 day
DeltaFile
+2-2Makefile.inc1
+2-21 files

LLVM/project 5db9b2b — libc/src/__support str_to_float.h, libc/test/src/__support str_to_float_test.cpp str_to_double_test.cpp

[libc] Bound the decimal point check in simple_decimal_conversion (#238179)

HighPrecisionDecimal clamps the decimal point to 1 << 30, but
exp10_to_exp2
is only valid for inputs below 646456636. For larger decimal points the
result wrapped to a negative value, so the "too large" and "too small"
checks did not trigger and the shift loops ran tens of millions of
iterations until exp_2 overflowed (signed integer overflow).

Treat decimal points at or beyond the valid range of exp10_to_exp2 as
out of
range, and use add_overflow/sub_overflow for exp_2 in the shift loops so
that they stay well defined.

Assisted-by: Claude (Anthropic)
DeltaFile
+24-5libc/src/__support/str_to_float.h
+15-0libc/test/src/__support/str_to_double_test.cpp
+10-0libc/test/src/__support/str_to_float_test.cpp
+49-53 files

LLVM/project bfaf4cb — llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Only apply vector math attributes to floating point vectors

i128 is now <2 x i64> on Win64, which made the vector type checks treat
integer helpers like __atomic_load_16 as vector math functions and mark
them nosync and nofree. Check for a floating point vector argument.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
DeltaFile
+6-2llvm/lib/IR/RuntimeLibcalls.cpp
+6-21 files

LLVM/project e71256a — utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[Bazel] Fixes d1acd0e (#238460)

This fixes d1acd0ef6ff890d73593dbbd8caf2e2dc7f64169 (#237605).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=d1acd0ef6ff890d73593dbbd8caf2e2dc7f64169

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+2-1utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+2-11 files

LLVM/project 4025c5a — llvm/lib/Target/AArch64 AArch64.h AArch64SLSHardening.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+14-5llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+7-0llvm/lib/Target/AArch64/AArch64.h
+21-52 files

LLVM/project ba12fde — llvm/lib/CodeGen/SelectionDAG LegalizeDAG.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

SelectionDAG: Use the memory type for atomic libcall actions

The atomic libcall selection is driven by the memory type, not the
legalized value type. Convert targets to use the LibCall action
instead of Expand.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+18-11llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+6-12llvm/lib/Target/Mips/Mips16ISelLowering.cpp
+6-12llvm/lib/Target/ARM/ARMISelLowering.cpp
+16-0llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+9-6llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+7-7llvm/lib/Target/AVR/AVRISelLowering.cpp
+62-484 files not shown
+76-5110 files

LLVM/project 4aaea35 — clang/docs BoundsSafetyImplPlans.md BoundsSafety.md, clang/docs/BoundsSafety BoundsSafetyAdoptionGuide.md index.md

[BoundsSafety][Docs] Add an index page and upstream status for -fbounds-safety (#238142)

Move -fbounds-safety docs into BoundsSafety/ without changing their
content.

Add BoundsSafety/index.md as the landing page for the -fbounds-safety
docs. It covers how to contribute, standardization efforts in WG14,
open-source adoption efforts, RFCs, and talks.

Add upstream status and the link #238453, which lists what is available
upstream, what is in progress, and what is planned, with links to the
relevant PRs and issues.

Leave a stub at the old BoundsSafety.html location so existing links
keep working.

Assisted-by: Opus 5.5
DeltaFile
+5-967clang/docs/BoundsSafety.md
+969-0clang/docs/BoundsSafety/BoundsSafety.md
+0-238clang/docs/BoundsSafetyImplPlans.md
+237-0clang/docs/BoundsSafety/BoundsSafetyImplPlans.md
+117-0clang/docs/BoundsSafety/index.md
+79-0clang/docs/BoundsSafety/BoundsSafetyAdoptionGuide.md
+1,407-1,2053 files not shown
+1,410-1,2919 files

LLVM/project dc8efda — clang/test/AST ast-print-float-shortest.cpp, clang/test/PCH objc_literals.m

[clang][APFloat] Print floating-point literals in the shortest round-trip form (#218471)

StmtPrinter printed a `FloatingLiteral` at the maximum round-trip
precision, so `3.14` printed as `3.1400000000000001`. This patch adds
`APFloat::toStringShortest` and calls it from `PrintFloatingLiteral`.
NaN, infinity, and zero keep the old path.

`toStringShortest` computes the shortest digit count from the value's
rounding interval (Ryu's formulation with a Dragonbox-style grid anchor)
in exact APInt arithmetic, so every IEEEFloat semantics works. The
existing `toString` then formats at that count and the round trip is
verified. PPCDoubleDouble keeps a plain probe from precision 1.

Two cases keep the natural-precision form:
- An integer in fixed notation has exact digits; a shorter form would
only switch it to scientific notation. `100.0` prints as `100.`, not
`1.0E+2`.
- The largest value of a format with neither infinity nor NaN parses
back from any larger string by saturation, which is not a round trip.

    [24 lines not shown]
DeltaFile
+261-0llvm/unittests/ADT/APFloatTest.cpp
+175-0llvm/lib/Support/APFloat.cpp
+134-0clang/test/AST/ast-print-float-shortest.cpp
+15-0llvm/include/llvm/ADT/APFloat.h
+6-5mlir/lib/IR/AsmPrinter.cpp
+3-3clang/test/PCH/objc_literals.m
+594-85 files not shown
+605-1511 files

LLVM/project 2291989 — llvm/include/llvm/IR RuntimeLibcalls.td RuntimeLibcallsImpl.td, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Declare vector libcall attributes in TableGen

Replace the type-based heuristics for vector math libcall attributes
with attributes declared on the libcall definitions, emitted with the
same attribute table helpers as intrinsics.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+226-1llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
+103-0llvm/test/TableGen/RuntimeLibcallEmitter-attributes.td
+26-51llvm/lib/IR/RuntimeLibcalls.cpp
+52-0llvm/test/TableGen/RuntimeLibcallEmitter-attributes-errors.td
+44-3llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+23-9llvm/include/llvm/IR/RuntimeLibcalls.td
+474-641 files not shown
+478-687 files

LLVM/project 8fe8575 — llvm/utils/TableGen/Basic IntrinsicEmitter.cpp AttributeTableEmitter.h

TableGen: Move attribute set and sequence table helpers to a header

Move AttributeSetTable and AttributeSequenceTable out of
IntrinsicEmitter into a reusable header so the runtime libcall emitter
can use the same encoding.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+112-0llvm/utils/TableGen/Basic/AttributeTableEmitter.h
+1-83llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+113-832 files

LLVM/project 4a4f5ab — llvm/lib/IR RuntimeLibcalls.cpp, llvm/test/TableGen RuntimeLibcallEmitter-attributes.td

RuntimeLibcalls: Mark vector libcall out pointers dereferenceable

The whole vector width will be written, so mark the vector width. To
maintain the element width alignment for some functions, we need to
start explicitly tracking if the element alignment is used or not.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+9-5llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
+10-3llvm/test/TableGen/RuntimeLibcallEmitter-attributes.td
+11-2llvm/lib/IR/RuntimeLibcalls.cpp
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef.ll
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/amdlibm.ll
+48-282 files not shown
+53-348 files

LLVM/project 26a5520 — llvm/utils/TableGen/Basic IntrinsicEmitter.cpp

Use UniqueVector for the intrinsic attribute tables
DeltaFile
+15-24llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+15-241 files

LLVM/project 92537ed — llvm/utils/TableGen/Basic IntrinsicEmitter.cpp

TableGen: Unique intrinsic attribute tables by attribute value

Unique the intrinsic attribute tables by the attributes themselves
rather than by CodeGenIntrinsic, and separate the uniquing from the
emission in AttributeSetTable and AttributeSequenceTable so other
emitters can reuse them.

This also fixes MaxNumAttrs, which was computed from one representative
intrinsic per argument attribute sequence and could undercount.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+223-171llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+223-1711 files

LLVM/project df2e3bc — llvm/lib/CodeGen AtomicExpandPass.cpp, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Use <2 x i64> for i128 libcall types on Win64

Win64 passes __int128 by reference and returns it in XMM0. i128 uses
GPR pairs, and <2 x i64> uses the correct vector register. This
matches the type AtomicExpand and clang uses for these functions.

Also fix AtomicExpand to use the correct type for UEFI (which should
eventually use the type information in RuntimeLibcallsInfo).

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+581-144llvm/test/Transforms/Util/DeclareRuntimeLibcalls/windows.ll
+84-0llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall-i128-win64.ll
+8-2llvm/lib/IR/RuntimeLibcalls.cpp
+2-2llvm/lib/CodeGen/AtomicExpandPass.cpp
+1-0llvm/test/CodeGen/X86/atomic-nocx16-win.ll
+676-1485 files

LLVM/project d975373 — llvm/lib/Transforms/Scalar SimpleLoopUnswitch.cpp, llvm/test/Transforms/SimpleLoopUnswitch trivial-unswitch-droppable.ll

[SimpleLoopUnswitch] Do not let droppable instructions block trivial unswitching (#238292)

In a loop such as
```c
for (...) {
  __builtin_assume(i < n);
  if (c) break;   // c is loop-invariant
  ...
}
```
the invariant exit should be unswitched trivially as `c` is checked once
before the loop with no copy of the loop. Instead, the assume stops
trivial unswitching since the pass gives up at any instruction that may
have side effects before the branch, and `llvm.assume` claims to write
memory so that it is not deleted as dead code. The loop then goes
through non-trivial unswitching, which duplicates the loop body.

Skip droppable instructions (`llvm.assume`, `llvm.pseudoprobe`,
`llvm.experimental.noalias.scope.decl`) in that check. LoopDeletion uses
the same principle.
DeltaFile
+189-0llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-droppable.ll
+1-1llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
+190-12 files

LLVM/project 48c7bbd — llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp

Reviews.
DeltaFile
+2-3llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+2-31 files

LLVM/project 167216e — clang/lib/Driver/ToolChains Clang.cpp CommonArgs.cpp, clang/test/Driver lto.c openmp-offload-gpu.c

[Clang][Driver] Forward -f[no-]vectorize to clang-linker-wrapper and LTO (#231693)

Forward -fvectorize and -fno-vectorize through clang-linker-wrapper to
device compiler invocations.

The frontend flags are translated into -vectorize-loops=<0|1> for the
LTO backend, mirroring the existing SLP vectorization handling.

Assisted by gpt-5.6.
DeltaFile
+10-2clang/test/Driver/lto.c
+12-0clang/test/Driver/openmp-offload-gpu.c
+8-0clang/lib/Driver/ToolChains/CommonArgs.cpp
+2-0clang/lib/Driver/ToolChains/Clang.cpp
+32-24 files

LLVM/project 0f678c0 — llvm/lib/Target/AMDGPU SIInstrInfo.h AMDGPUAsmPrinter.cpp, llvm/test/CodeGen/AMDGPU vgpr-lowering-gfx1250.mir inline-mem-constraints.ll

[AMDGPU] Reapply "Support the RF and m inline asm constraints (#195123)" (#232540)

Relanding 6b58e144bee8, reverted in 6b804fdec943 due to a CI failure in
hazard-inlineasm.mir.

Root cause: the original commit fixed an incidental problem by adding
`&& !MI.isInlineAsm()` to the `isGenericOpcode` early-return in
SIInstrInfo::verifyInstruction, which caused the verifier to actually
check INLINEASM instructions. This exposed stale RC ID encodings in the
raw flag integers in hazard-inlineasm.mir. The original commit fixed
those values, but they became stale again at the time when the commit
was merged.

Fix: recompute all five INLINEASM flag operands using current RegClassID
assignments.

Original description:
This patch supports the RF inline asm constraint for memory operands in
the flat address space as well as the generic 'm' constraint.
DeltaFile
+334-0llvm/test/CodeGen/AMDGPU/inline-mem-constraints.ll
+27-0llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+12-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+10-0llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+8-1llvm/lib/Target/AMDGPU/SIInstrInfo.h
+4-4llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
+395-59 files not shown
+420-1015 files

LLVM/project 5f668c4 — clang/utils/perf-training lit.site.cfg.in lit.cfg, clang/utils/perf-training/llvm-support build.test

[CMake] Pass through -DCMAKE_MAKE_PROGRAM= when generating profdata for clang (#225970)

Since we're already passing the -DCMAKE_GENERATOR through, we need the
corresponding CMAKE_MAKE_PROGRAM, which CMake doesn't always know how to
find itself.

rdar://187916126
DeltaFile
+1-1clang/utils/perf-training/llvm-support/build.test
+1-0clang/utils/perf-training/lit.site.cfg.in
+1-0clang/utils/perf-training/lit.cfg
+1-0clang/utils/perf-training/bolt.lit.site.cfg.in
+1-0clang/utils/perf-training/bolt.lit.cfg
+5-15 files

LLVM/project 271e877 — llvm/lib/ExecutionEngine/Orc ReOptimizeLayer.cpp

[ORC] Match const void *Tag signature in orc_rt_lite_reoptimize_helper (#237757)

SelfExecutorProcessControl::jitDispatchViaWrapperFunctionManager takes a
const void *FnTag second parameter; using void *Tag in
orc_rt_lite_reoptimize_helper's JITDispatch function pointer trips
-fsanitize=cfi-icall.

This is needed to remove the `LIT_FILTER_OUT="ExecutionEngine/"`
workaround in
https://github.com/llvm/llvm-zorg/blob/d6d19aa00e80a00ee06119d173d1979dbeed1ab2/zorg/buildbot/builders/sanitizers/buildbot_functions.sh#L665
on
https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux-bootstrap-cfi
and
https://lab.llvm.org/buildbot/#/builders/sanitizer-aarch64-linux-bootstrap-cfi.

Assisted-by: Gemini
DeltaFile
+2-2llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp
+2-21 files

FreeNAS/freenas 8415a54 — src/middlewared/middlewared/alembic/versions/27.0 2026-11-03_14-00_webshare_mcp.py, src/middlewared/middlewared/alembic/versions/28.0 2026-09-25_09-46_webshare_mcp.py 2026-11-03_14-30_merge.py

NAS-142270 / 28.0.0-BETA.1 / Add Webshare MCP option (by Qubad786) (by bugclerk) (#20126)

## Context
Webshare ships an MCP server configured through the `mcp` block of the
webshare-auth config, and there was no way to turn it on from
middleware.

## Solution
- **New settings**: `webshare.update` accepts `mcp_enabled`,
`mcp_allowed_groups` and `mcp_allow_write`, which are rendered into the
`mcp` block. `allowed_hosts` is left unset.
- **MCP groups must be login groups**: webshare only checks login groups
at OAuth consent, while token refresh and session spawn check only the
MCP groups, so every MCP group must be `truenas_webshare` or an entry of
`groups`. Otherwise MCP access could outlive Webshare access. Enabling
MCP without a group is rejected, since webshare denies everyone on an
empty list.
- **Canonical group names**: MCP groups are resolved through NSS,
compared by gid and stored under their canonical name, so a directory

    [10 lines not shown]
DeltaFile
+32-0src/middlewared/middlewared/alembic/versions/27.0/2026-11-03_14-00_webshare_mcp.py
+21-0src/middlewared/middlewared/alembic/versions/28.0/2026-11-03_14-30_merge.py
+19-0src/middlewared/middlewared/api/v27_0_0/webshare.py
+4-11src/middlewared/middlewared/alembic/versions/28.0/2026-09-25_09-46_webshare_mcp.py
+76-114 files

LLVM/project 73fd9cd — llvm/lib/Target/AMDGPU SIFixSGPRCopies.cpp SIFixSGPRCopies.h, llvm/test/CodeGen/AMDGPU fix-sgpr-copies-nophis.mir

[AMDGPU] Clear NoPHIs after SIFixSGPRCopies under the new pass manager (#238429)

SIFixSGPRCopies can build waterfall loops, which add PHIs. The legacy
pass declares that it clears NoPHIs, but the new pass manager's
SIFixSGPRCopiesPass declared no properties and never applied them. So a
function kept NoPHIs after the pass added a PHI, and the machine
verifier rejected it. Declare the cleared property and apply it with
MFPropsModifier. The test waterfalls a buffer load's resource under both
pass managers.
DeltaFile
+31-0llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nophis.mir
+5-0llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
+1-0llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+37-03 files

LLVM/project f2eecdd — llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU fptoi.i128.ll amdgpu-mul24-knownbits.ll

[AMDGPU] Use the mul24 result width for known bits

Extend the low 24 operand bits to the destination width before multiplying. Using the i32 operand width for i64 results can incorrectly fold upper product bits to zero.

Cover signed and unsigned i64 results and restore the bf16-to-i128 sign-extension checks affected by the incorrect inference.
DeltaFile
+89-0llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+92-13 files

LLVM/project 90fb25a — llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU fptoi.i128.ll lshl64-to-32.ll

[AMDGPU] Track GlobalISel known bits for mul24 intrinsics

Sign or zero extend the low 24 operand bits before querying KnownBits::mul. This allows GlobalISel to narrow shifts and simplify address calculations through mul24 intrinsics.

Cover ignored high bits, zero operands and overflow, and update the affected codegen checks.
DeltaFile
+165-0llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
+78-0llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
+25-35llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
+18-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+0-2llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+286-375 files

LLVM/project ec9963c — llvm/test/Transforms/InstCombine mul-knownbits-negative.ll

[KnownBits] Cover negative multiplication boundaries

Exercise both operand orders and i8, i32, i65 and i128 results. Preserve cases where zero or signed and unsigned wraparound prevent leading-bit inference.
DeltaFile
+278-0llvm/test/Transforms/InstCombine/mul-knownbits-negative.ll
+278-01 files

LLVM/project daaa2f6 — llvm/utils/TableGen/Common CodeGenSchedule.cpp

TableGen: Keep the instregex prefix for patterns with a top-level ?

instregex discarded a pattern's literal prefix, and ran the regex on
every instruction, if the pattern had a ? outside parentheses, as in
LDPS?Wi. A ? only makes the atom before it optional, and an atom
directly before it is already dropped from the prefix. Only a top-level
| makes the prefix unusable.

AArch64GenSubtargetInfo.inc tablegen run:

            Gigainstructions  Gigacycles      CPU seconds
  Before    44.6              18.8            5.7
  After     43.1 (-3.4%)      17.8 (-4.9%)    5.4 (-4.6%)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+3-2llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+3-21 files

LLVM/project 92bb278 — llvm/tools/sancov sancov.cpp

Rename function.
DeltaFile
+7-6llvm/tools/sancov/sancov.cpp
+7-61 files