FreeBSD/ports 638ebd4filesystems/py-libzfs distinfo Makefile

filesystems/py-libzfs: v2.0.1

This fixes a bug with the ZFSVdev.Replace method.

https://github.com/asomers/py-libzfs/releases/tag/v2.0.1

Sponsored by:   ConnectWise
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+4-42 files

LLVM/project e2eaf1cllvm/lib/Target/Lanai LanaiDelaySlotFiller.cpp, llvm/test/CodeGen/Lanai machine-verifier-regression.ll delay_filler.ll

[Lanai] Make DelaySlotFiller handle implicit call operands

This allowed incorrectly moving an instruction defining a register
implicitly used by the call into the delay slot when the call dependend
on that register. We fix this by only skipping regmask operands.

Co-Authored-By: Jacques Pienaar <jpienaar at google.com>

Reviewers: jpienaar

Pull Request: https://github.com/llvm/llvm-project/pull/206192
DeltaFile
+25-15llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
+20-0llvm/test/CodeGen/Lanai/machine-verifier-regression.ll
+4-1llvm/test/CodeGen/Lanai/delay_filler.ll
+2-1llvm/test/CodeGen/Lanai/constant_multiply.ll
+2-1llvm/test/CodeGen/Lanai/multiply.ll
+53-185 files

LLVM/project e508d49llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 add-sub-nsw-intmin.ll

[SLP] Drop nsw when add/sub interchange negates INT_MIN

BinOpSameOpcodeHelper unifies add and sub by negating a constant operand.
Negating INT_MIN overflows and yields INT_MIN, but add nsw X, INT_MIN and
sub nsw X, INT_MIN have opposite validity domains, so nsw is invalid on the
converted lane and must be dropped.

Fixes #206474.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/206558
DeltaFile
+18-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-2llvm/test/Transforms/SLPVectorizer/X86/add-sub-nsw-intmin.ll
+20-22 files

LLVM/project 52799cbclang/lib/CIR/CodeGen CIRGenExprConstant.cpp, llvm/test/CodeGen/RISCV/GlobalISel atomicrmw-and-or-xor.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+10,260-9,388llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
+0-7,069llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+5,907-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc-fake16.txt
+3,268-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-and-or-xor.ll
+2,020-0llvm/test/MC/M68k/MOVE.s
+308-868clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+21,763-17,3251,109 files not shown
+51,374-29,9621,115 files

LLVM/project 387c0b0llvm/lib/Target/Lanai LanaiDelaySlotFiller.cpp, llvm/test/CodeGen/Lanai machine-verifier-regression.ll

[Lanai] Fix delay slot filler for ret instructions

Ret instructions have two delay slots, but only one was being bundled.
This had the potential to leave instructions after the terminator.

Co-Authored-By: Jacques Pienaar <jpienaar at google.com>

Reviewers: jpienaar

Pull Request: https://github.com/llvm/llvm-project/pull/206191
DeltaFile
+19-0llvm/test/CodeGen/Lanai/machine-verifier-regression.ll
+4-0llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
+23-02 files

LLVM/project b000729clang/lib/CIR/CodeGen CIRGenExprConstant.cpp, llvm/test/CodeGen/RISCV/GlobalISel atomicrmw-and-or-xor.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+10,260-9,388llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
+0-7,069llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+5,907-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc-fake16.txt
+3,268-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-and-or-xor.ll
+2,020-0llvm/test/MC/M68k/MOVE.s
+308-868clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+21,763-17,3251,081 files not shown
+50,910-29,9601,087 files

LLVM/project 6dbc062llvm/lib/Target/Hexagon HexagonPostRAHandleQFP.cpp, llvm/test/CodeGen/RISCV/GlobalISel atomicrmw-and-or-xor.ll

Merge branch 'main' into users/kparzysz/locator-utils
DeltaFile
+10,260-9,388llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
+0-7,069llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+5,907-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc-fake16.txt
+3,268-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-and-or-xor.ll
+2,020-0llvm/test/MC/M68k/MOVE.s
+1,755-0llvm/lib/Target/Hexagon/HexagonPostRAHandleQFP.cpp
+23,210-16,4571,334 files not shown
+68,311-34,9601,340 files

LLVM/project 1acc7ballvm/lib/Target/Lanai CMakeLists.txt

[Lanai] Add missing dependencies (#206546)

For LanaiCodeGenPassBuilder introduced in
016954e1489dbd8daf94baf3372dae2b7f2684e3.
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+3-0llvm/lib/Target/Lanai/CMakeLists.txt
+3-01 files

LLVM/project 7ef2305llvm/lib/Target/NVPTX NVPTXAddressFolder.cpp NVPTXInstrInfo.td, llvm/test/CodeGen/NVPTX address-folder.ll address-folder.mir

[NVPTX] Fold symbol addresses into memory operands (reland) (#205983)

Re-lands https://github.com/llvm/llvm-project/pull/202379, which was
reverted in https://github.com/llvm/llvm-project/pull/205852. The test
failures were introduced because the original PR was stale after
#204192, so I've updated the test in here.

---------

Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
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+123-0llvm/lib/Target/NVPTX/NVPTXAddressFolder.cpp
+111-0llvm/test/CodeGen/NVPTX/address-folder.ll
+60-0llvm/test/CodeGen/NVPTX/address-folder.mir
+2-2llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+3-0llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+3-0llvm/lib/Target/NVPTX/NVPTX.h
+302-24 files not shown
+307-210 files

LLVM/project 4e66964mlir/include/mlir-c IR.h, mlir/lib/CAPI/IR IR.cpp

[mlir-c] Add mlirOperationIsAncestor and mlirOperationIsProperAncestor
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+41-0mlir/test/CAPI/ir.c
+10-0mlir/include/mlir-c/IR.h
+8-0mlir/lib/CAPI/IR/IR.cpp
+59-03 files

LLVM/project e192ec4libc CMakeLists.txt, libunwind CMakeLists.txt

[CMake] Warn when the version of CMake is older than 3.31.0 (#204203)

This is a preparation to raise the minimum required CMake version to
3.31.0 in LLVM 24.

See
https://discourse.llvm.org/t/rfc-raising-minimum-required-cmake-version-to-3-31/91086.
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+8-0libc/CMakeLists.txt
+8-0libunwind/CMakeLists.txt
+8-0lld/CMakeLists.txt
+8-0lldb/CMakeLists.txt
+8-0llvm-libgcc/CMakeLists.txt
+8-0mlir/CMakeLists.txt
+48-014 files not shown
+154-020 files

LLVM/project 281e459mlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

[mlir-c] Add mlirOperationTryFold
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+51-0mlir/test/CAPI/rewrite.c
+19-0mlir/include/mlir-c/Rewrite.h
+15-0mlir/lib/CAPI/Transforms/Rewrite.cpp
+85-03 files

LLVM/project 6eacc16mlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

[mlir-c] Add mlirDialectMaterializeConstant
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+54-0mlir/test/CAPI/rewrite.c
+13-0mlir/include/mlir-c/Rewrite.h
+12-0mlir/lib/CAPI/Transforms/Rewrite.cpp
+79-03 files

LLVM/project 6a48ebbflang/lib/Parser openmp-utils.cpp

Update openmp-utils.cpp
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+1-1flang/lib/Parser/openmp-utils.cpp
+1-11 files

LLVM/project c4bb83eflang-rt/lib/runtime mma.f90 __ppc_intrinsics.f90

[Flang-RT] Make implicit PPC intrinsic uses explicit (#206493)

The PPC-specific builtin moduls have implicit dependencies insert by
flang. For CMake to correctly setup the build order, they must be made
explicit.

This replicates the implicit module uses from

https://github.com/llvm/llvm-project/blob/12b20b36737094b1c521adff0c8f58aaaf2f41fb/flang/lib/Semantics/semantics.cpp#L680-L693
in the modules themselves. The PPC-specific modules compiled by Flang-RT
are listed here:

https://github.com/llvm/llvm-project/blob/12b20b36737094b1c521adff0c8f58aaaf2f41fb/flang-rt/lib/runtime/CMakeLists.txt#L213-L219

This should fix the intermittend build error mentioned in
https://github.com/llvm/llvm-project/pull/205634#issuecomment-4829653483.
Unfortunately I do not have a PowerPC (cross-)compilation build
environment ready to test, nor does the Premerge-CI build it.
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+2-0flang-rt/lib/runtime/mma.f90
+1-0flang-rt/lib/runtime/__ppc_intrinsics.f90
+1-0flang-rt/lib/runtime/__ppc_types.f90
+4-03 files

LLVM/project bd1572abolt/lib/Passes SplitFunctions.cpp, bolt/test/X86 register-fragments-bolt-symbols.s

[BOLT] Fix register-fragments-bolt-symbol test on FreeBSD

std::uniform_int_distribution and std::shuffle are
implementation-defined, so binary built with libc++ and libstdc++ can
produce different fragment layouts when using SplitStrategy. In this
case, the FreeBSD build emits only one fragment instead of three.

The output geenrate by --bolt-seed should be deterministic for the same
binary regardless of the standard library implementation. Implement a
portable shuffle and uniform distribution to guarantee identical results
for a given seed.

After this change, we generate 1 fragment, which decrease the strength
of the testcase. As a result, we change the seed to different value to
allow it generate different number of fragments.

Also, replace in-place file modifcation with a write-and-replace
approach for better portability in sed.
DeltaFile
+24-12bolt/test/X86/register-fragments-bolt-symbols.s
+27-5bolt/lib/Passes/SplitFunctions.cpp
+51-172 files

LLVM/project a8918b6llvm/include/llvm/ADT GenericUniformityImpl.h, llvm/include/llvm/Bitcode BitcodeConvenience.h

Fix -Wunused-template in assorted LLVM library helpers (NFC) (#202988)

Function templates across a few low-level LLVM libraries trip
`-Wunused-template`. Two kinds of fix here:

- Header templates with internal linkage. `CheckedArithmetic.h`: move
`checkedOp` out of the anonymous namespace into `llvm::detail` and
update its callers. `BitcodeConvenience.h`: drop `static` on `emitOps`.
`MCDCTypes.h`: drop `static` on `getParams`. Templates are implicitly
inline, so this is a linkage-only change.
- Dead code with no callers, removed: `makeNode` in
`ItaniumManglingCanonicalizer.cpp` (a base-class helper shadowed by the
derived class), `addDirectiveHandler` in `GOFFAsmParser.cpp`, and
`getWithDefault` in `ResourceFileWriter.cpp`.

NFC.

Part of #202945.
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+7-10llvm/include/llvm/ADT/GenericUniformityImpl.h
+9-7llvm/include/llvm/Support/CheckedArithmetic.h
+0-9llvm/tools/llvm-rc/ResourceFileWriter.cpp
+0-8llvm/lib/MC/MCParser/GOFFAsmParser.cpp
+0-5llvm/lib/ProfileData/ItaniumManglingCanonicalizer.cpp
+2-2llvm/include/llvm/Bitcode/BitcodeConvenience.h
+18-411 files not shown
+19-427 files

LLVM/project 78e5e5clld/COFF ICF.cpp

[lld][COFF] Specialize ICF equality passes, NFC
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+30-25lld/COFF/ICF.cpp
+30-251 files

LLVM/project de178a7mlir/include/mlir-c Analysis.h, mlir/lib/CAPI/IR Analysis.cpp

[mlir-c] Add getBlocksSortedByDominance and topologicalSort
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+77-0mlir/test/CAPI/ir.c
+20-0mlir/lib/CAPI/IR/Analysis.cpp
+19-0mlir/include/mlir-c/Analysis.h
+116-03 files

OpenZFS/src 550f18etests/zfs-tests/tests/functional/devices devices_common.kshlib

ZTS: Pass dec instead of hex to mknod

On Ubuntu 26.04 the default mknod command returns an error when
provided the major and minor numbers in hex.  Switch to passing
decimal values.

Reviewed-by: Tino Reichardt <milky-zfs at mcmilk.de>
Reviewed-by: George Melikov <mail at gmelikov.ru>
Reviewed-by: Tony Hutter <hutter2 at llnl.gov>
Signed-off-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Closes #18547
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+6-61 files

OpenZFS/src d76cb2btests/zfs-tests/tests/functional/stat statx_dioalign.ksh

ZTS: statx_dioalign.ksh update to stride_dd

The uutils 0.8.0 version of dd appears to diverge from GNU behavior
and does not fail when an unaligned write O_DIRECT write is issued.
Update the test case to use stride_dd which is provided by the ZTS
so the expected syscall behavior can be verified.

Reviewed-by: Tino Reichardt <milky-zfs at mcmilk.de>
Reviewed-by: George Melikov <mail at gmelikov.ru>
Reviewed-by: Tony Hutter <hutter2 at llnl.gov>
Signed-off-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Closes #18547
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+6-5tests/zfs-tests/tests/functional/stat/statx_dioalign.ksh
+6-51 files

LLVM/project 88944b6mlir/include/mlir-c Analysis.h, mlir/lib/CAPI/IR Analysis.cpp

[mlir-c] Add backward slice analysis
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+63-0mlir/test/CAPI/ir.c
+14-0mlir/lib/CAPI/IR/Analysis.cpp
+14-0mlir/include/mlir-c/Analysis.h
+91-03 files

FreeBSD/ports 27af2dfwww/tor-browser Makefile, www/tor-browser/files patch-bug2046162

www/tor-browser: Unbreak build

The issue appears to be cbindgen 0.29.4:

    https://github.com/mozilla/cbindgen/issues/1165
    https://bugzilla.mozilla.org/show_bug.cgi?id=2046162

Obtained from:  Martin Filla
PR:             296327
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+30-0www/tor-browser/files/patch-bug2046162
+1-1www/tor-browser/Makefile
+31-12 files

FreeNAS/freenas b4ca219src/middlewared/middlewared/plugins/truenas_connect heartbeat.py, src/middlewared/middlewared/pytest/unit/plugins test_truenas_connect.py

NAS-140857 / 26.0.0-RC.1 / Handle TNC license delivery and token states in heartbeat (by sonicaj) (#19222)

This commit adds changes to read the TNC heartbeat response body so we
can report the system fingerprint and installed license id, install a
license PEM that TNC delivers, and drive token rotation and the terminal
token states off the body fields instead of the old X-New-Token header.
A delivered license is deduped against the one already installed so we
don't reinstall it every beat, and a 205 that carries no license or
token is logged as a TNC fault rather than silently skipped.

Original PR: https://github.com/truenas/middleware/pull/19153

Co-authored-by: Waqar Ahmed <waqarahmedjoyia at live.com>
DeltaFile
+211-0src/middlewared/middlewared/pytest/unit/plugins/test_truenas_connect.py
+83-34src/middlewared/middlewared/plugins/truenas_connect/heartbeat.py
+294-342 files

LLVM/project a0f26dbmlir/include/mlir-c Analysis.h, mlir/lib/CAPI/IR Analysis.cpp CMakeLists.txt

[mlir-c] Add forward slice analysis
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+74-0mlir/test/CAPI/ir.c
+44-0mlir/include/mlir-c/Analysis.h
+40-0mlir/lib/CAPI/IR/Analysis.cpp
+2-0mlir/lib/CAPI/IR/CMakeLists.txt
+160-04 files

LLVM/project 35343calld/COFF ICF.cpp

[lld][COFF] Refactor ICF section equality, NFC

This matches the pattern used in `segregate` (a constant bool
parameter).
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+39-58lld/COFF/ICF.cpp
+39-581 files

LLVM/project 1e1d455llvm/test/Transforms/LoopVectorize/VPlan buildvector-first-lane-only.ll

[LV] Add test with missing fold of buildvector (NFC). (#206540)

Add test where we create a build vector with only the first lane used.
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+51-0llvm/test/Transforms/LoopVectorize/VPlan/buildvector-first-lane-only.ll
+51-01 files

LLVM/project d0c6476compiler-rt/lib/sanitizer_common sanitizer_mac.cpp

[sanitizer_common] [Darwin] Update version mapping for macOS 27-aligned releases (#204608)

This updates `MapToMacos` et. al. to produce correct results for macOS
26 and macOS 27-aligned releases.

rdar://177997021
rdar://169356606
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+25-1compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp
+25-11 files

LLVM/project dc84cd3llvm/lib/Target/BPF BPFMIPeephole.cpp BPFTargetMachine.cpp

[BPF] Avoid stack argument fatal error with O0 optimization (#206398)

Upstream reported a compiler fatal error with stack arguments ([1]). The
source code:
```
  void f(int, int, int, int, int, int);
  int main(void)
  {
        f(0, 0, 0, 0, 0, 0);
        return 0;
  }
```
The compilation flag: `clang --target=bpf -O0 -c t.c`

The failure symptom:
```
  fatal error: error in backend: Unsupported instruction : <MCInst 338 <MCOperand Imm:-8> <MCOperand Reg:2>>
```
The failure reason is due to `BPF PreEmit Peephole Optimization`. It is

    [20 lines not shown]
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+6-7llvm/lib/Target/BPF/BPFMIPeephole.cpp
+2-3llvm/lib/Target/BPF/BPFTargetMachine.cpp
+8-102 files

LLVM/project eaa795fmlir/include/mlir-c Analysis.h, mlir/lib/CAPI/IR Analysis.cpp

[mlir-c] Add getBlocksSortedByDominance and topologicalSort
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+86-0mlir/test/CAPI/ir.c
+24-0mlir/include/mlir-c/Analysis.h
+18-0mlir/lib/CAPI/IR/Analysis.cpp
+128-03 files