[MLIR][NVVM] Add support for scaled n1 ue8m0 and ue5m3 packed Convert Ops (#239189)
This patch adds support for `scaled::n1::ue8m0` to existing
`f32/f16x2/bf16x2`
to `FP8` (`e4m3x2`, `e5m2x2`), `FP6` (`e2m3x2`, `e3m2x2`) and
`FP4` (`e2m1x2`) convert Ops.
This also adds support for `ue5m3x2` to `f16x2/bf16x2` and
`ff/f16/bf16` to `ue5m3` in existing convert Ops.
Lit tests are added to verify the lowering to the intrinsics.
Negative tests are also added to check the error-handling of invalid
combinations.
PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt
---------
Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
firmware: business now uses 26.10.0p1 for patch releases
Because 26.10p1 is bigger than 26.10.1 we need to add a .0 to the
releases even though we tried to avoid it for a decade. Initial
releaes are still without .0 which makes 26.10 equal 26.10.0 but
the lookup code doesn't know that.
Since we also don't use 26.07 we can split at .0 no problem.
[Transforms] Remove AssumeSimplify pass (#241939)
This removes the AssumeSimplify pass, which is part of the
KnowledgeRetention framework and not enabled by default.
Our general direction has been to instead simplify assumes directly as
part of other passes like InstCombine instead, and we generally don't
plan to further pursue the KnowledgeRetention framework in its current
form, so this deletes the pass.
If we wanted to have a dedicated assume simplification pass, we would
reimplement it from scratch without using KnowledgeRetention APIs
anyway.
net/geoclue: Update 2.8.1 to 2.8.2
- Translations for Georgian and Occitan.
- Building translations now works.
- Fix double free in on_desktop_id_set() and on_client_proxy_ready().
- Fix some gobject-linter rules in the correctness category.
- Document the command to register network NMEA sources to avahi.
Changelog: https://gitlab.freedesktop.org/geoclue/geoclue/-/blob/2.8.2/NEWS
Approved by: jrm (mentor), desktop (arrowd)
Differential Revision: https://reviews.freebsd.org/D61474
X86: Reuse the last subtarget for functions with same attributes
Add a utility for caching subtarget lookups. This returns the last
subtarget without building the subtarget key if the function has the
same attributes or same subtarget-relevant attributes as the last
query. RISCV and AArch64 already do something similar, and this
utility should be adopted across the targets (customized to the
relevant attributes). Also find the subtarget attributes in one
scan.
CTMark instructions executed, geomean: O3 -0.26%, ThinLTO -0.26%.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[APFloat] Support user defined bit conversions (#240920)
[APFloat] Support user provided conversion to/from bits
This change allows users to provide custom functions to convert to/from
bits.
- fltSemantics has function pointers for conversion and user provided
values of it are supported
- built-in semantics also use these instead of chained if, making the
code less repetitive and slightly faster
- APFloat/IEEFloat internals like types and ranges of significand,
mantissa etc. can only be accessed using FloatRepr interface so only
user defined bitcast functions will be affected by changes
Resubmitted #233961 with fixes for GCC 7
[LoongArch] Legalize BUILD_VECTOR into a broadcast when all non-undef elements are identical
When a BUILD_VECTOR consists of the same element (ignoring undefs),
it is better emitting a broadcast instead of multiple insertions.
Some floating-point cases suffer performance regressions, those
specific cases are excluded in this commit. Including when:
- only one element is non-undef,
- only two elements are non-undef, and one of them must at index 0,
- for v8f32 vector type, specially exclude the cases when the only
two non-undefs are at index (1,2)/(1,3)/(2,3).
amd64/vmm: Don't advertise AMD PerfMonV2 or performance counters
vmm does not handle CPUID leaf 0x80000022, so a FreeBSD guest on a
Family 19h or later host panics on "kldload hwpmc", which trusts the
PerfMonV2 bit and writes AMD_PMC_GLOBAL_CTL.
Tested by: Osvaldo Janeri Filho <ojanerif at amd.com>
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Reviewed by: markj, kib
Differential Revision: https://reviews.freebsd.org/D61141
(cherry picked from commit 8fb539b081dbfe3e93e607a5d4d36184c53c8aaf)
amd64/vmm: Don't advertise AMD PerfMonV2 or performance counters
vmm does not handle CPUID leaf 0x80000022, so a FreeBSD guest on a
Family 19h or later host panics on "kldload hwpmc", which trusts the
PerfMonV2 bit and writes AMD_PMC_GLOBAL_CTL.
Tested by: Osvaldo Janeri Filho <ojanerif at amd.com>
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Reviewed by: markj, kib
Differential Revision: https://reviews.freebsd.org/D61141
(cherry picked from commit 8fb539b081dbfe3e93e607a5d4d36184c53c8aaf)
netlink: Pre-register the missing devctl event systems
devctl_notify() can be called with a mutex held. If the event system is
not listed in devctl_systems[], sysevent_get_group() calls
sysevent_new_group(), which calls strdup() with M_WAITOK, and we may end
up sleeping while holding a non-sleepable mutex.
Add the missing systems.
While here, remove the nonexistent KERNEL system.
PR: 299272
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D61161
(cherry picked from commit 66d078c17294ca2ea225e4926a8cd9697dda57ed)
[libc][math][NFC] Fix GCC diagnostics in math tests (#241530)
Building the math test suite with GCC surfaces conversion, narrowing,
uninitialised-variable, and non-exhaustive return warnings, along with
-Wattributes visibility warnings under -fvisibility-inlines-hidden when
passing LIBC_ALWAYS_INLINE static_rounding functions as template
arguments.
Initialise tracking locals across range and shared tests, suffix float
and float16 test literals with exact f and f16 hexadecimal forms, cast
FModTest inputs with fputil::cast<T>, and wrap static_rounding helpers
in static functions for exhaustive expf and exp2f tests. Guard the
64-bit long exponent checks in LdExpTest with if constexpr and mark the
MPCUtils RoundingMode switch unreachable after covering all enumerators.
Assisted-by: Automated tooling, human reviewed.
---------
Co-authored-by: Tue Ly <lntue.h at gmail.com>
[lld-macho] Mark live sections and symbols in parallel (#240243)
Currently, `markLive()` walks the liveness graph with one serial
worklist in a single depth-first walk, taking about 4–8% of the wall
time of large `-dead_strip` links. This PR parallelizes it.
## Design
We started this work by mirroring lld/ELF's parallel markLive
(llvm/llvm-project#189321), which is a level-synchronized BFS. Workers
claim sections of the current level from an atomic index, visit newly
reached sections inline up to a depth of 3, and queue deeper ones for
the next level. However, we saw that this regressed markLive's
single-threaded performance by 4–35% on large links; investigation
showed that the depth-first walk had better memory locality.
So this keeps the levels but walks depth-first inside each one:
- Each worker takes chunks of the level and pushes every section it
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[lld-macho] Collect markLive roots in parallel
With the traversal parallel, most of markLive's remaining time goes to
the serial loops around it: finding the GC roots, which visits every
global symbol, every object file's local symbols and every input
section, and the S_ATTR_LIVE_SUPPORT scan over every input section.
Run those loops on all threads. The type-erased MarkLive interface now
takes a shard index with each root: each thread adds the roots it finds
to its own shard, and moves them to nextLevel after every chunk, so with
one thread the order is unchanged. The live-support scan does the same
with the sections it marks live, reading the live bits of sections that
other threads may be marking at the same time through the thread-safe
isLive(). A live-support section that refers only to another one marked
by the same scan may be found by the next iteration of the loop around
it instead; the final live set is the same.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
allwinner: a33: Fix the pin number of PE17
The PE17 entry of the pad table of the A33 had the pin number 16, the
one of PE16, so the pinctrl of PE17 configured PE16 and a <&pio 4 17>
specifier could not be mapped.
Reported by: llm-postcr
Fixes: cf72965fbf02 ("Allwinner: Add A33 support")
aw_ccu: h6: Allow the IR and W1 clocks to change their parent
The IR clock was defined without AW_CLK_REPARENT, so only the current
parent was used to find a rate. The firmware leaves the mux on osc32k,
from which the best rate is 32768Hz, and aw_cir asks for exactly 3MHz,
which osc24M can give. The request failed and r_ir did not attach. Do
the same as the main CCU for the CIR-TX clock and let the clock use the
best parent, and do the same for the 1-wire clock which is the same.
Reported by: llm-postcr
Fixes: 69919babdac7 ("aw_ccu: h6: Add the IR, W1, RSB and RTC clocks of the R CCU")
Tested on: H6
