LLVM/project 9cc094bllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.lerp.ll

[AMDGPU][GISel] RegBankLegalize rule for amdgcn_lerp (#214324)
DeltaFile
+60-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+64-32 files

OpenZFS/src a515918etc/systemd/system zfs-volume-wait.service.in zfs-mount@.service.in

Make systemd-udev-settle optional for the import units

systemd-udev-settle.service has been deprecated for years, recent
systemd releases warn about it at boot, and distributions have begun
shipping without it, which turns the hard Requires= in
zfs-import-cache and zfs-import-scan into a broken import: a
Requires= on a masked or removed unit keeps the service from ever
starting.  Issue #10891.

Demote the dependency to Wants= and keep the After= ordering.  Where
the settle unit exists and completes, the boot is what it always
was: Wants= pulls settle in, the import waits for it, and the
device-symlink guarantee it provided is intact.  Where it is masked
or gone the wish is quietly dropped and the import runs anyway,
which beats not importing at all.  One deliberate behavior change:
if settle itself fails, on a system so large that enumeration
overruns its timeout, the old Requires= cancelled the import while
the new units go ahead at the timeout mark with whatever has been
enumerated by then.

    [29 lines not shown]
DeltaFile
+3-1etc/systemd/system/zfs-import-scan.service.in
+3-1etc/systemd/system/zfs-import-cache.service.in
+0-1etc/systemd/system/zfs-volume-wait.service.in
+0-1etc/systemd/system/zfs-mount@.service.in
+0-1etc/systemd/system/zfs-mount.service.in
+6-55 files

LLVM/project b160ed8.github/workflows release-documentation.yml

Fixes
DeltaFile
+5-3.github/workflows/release-documentation.yml
+5-31 files

FreeBSD/ports 0bbc839x11/libxfce4windowing distinfo Makefile

x11/libxfce4windowing: Fix internationalization

- Import upstream patch to correctly link to libintl [1]
- Add USES=localbase:ldflags to make meson find the libintl library

PR:             297303
Obtained from:  https://gitlab.xfce.org/xfce/libxfce4windowing/-/commit/83ffd4ac83920ecd7ad190e997539d7a60c8dd60.patch [1]
MFH:            2026Q3

(cherry picked from commit e886a6665e37ecb3344dd3ebbb6f33832d9978ef)
DeltaFile
+6-2x11/libxfce4windowing/Makefile
+3-1x11/libxfce4windowing/distinfo
+9-32 files

LLVM/project 12df34blldb/source/Plugins/Process/elf-core ProcessElfCore.h ProcessElfCore.cpp, lldb/test/API/functionalities/postmortem/elf-core elf-NT_FILE-memory-region.yaml TestLinuxCore.py

[lldb][elf-core] Populate memory region names from NT_FILE (#212666)

## Summary

`ProcessElfCore` already parses `NT_FILE`, but its cached `PT_LOAD`
memory-region entries did not retain their backing filenames.

- cache a complete `MemoryRegionInfo` for each `PT_LOAD` instead of
rebuilding one from a custom permissions/name record on every query
- associate an `NT_FILE` pathname when the `PT_LOAD` and `NT_FILE`
starts match; their ends may differ, while a `PT_LOAD` beginning inside
an `NT_FILE` range remains unnamed
- finalize names and memory-tag state after all program headers are
parsed, making the result independent of `PT_LOAD` and `PT_NOTE`
ordering
- preserve regions with `p_filesz == 0` and return the cached region
directly from `DoGetMemoryRegionInfo`
- add API coverage for the same-start/different-end case, an interior
unnamed region, and an unnamed NT_FILE-only tail

    [19 lines not shown]
DeltaFile
+89-41lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
+69-0lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+30-0lldb/test/API/functionalities/postmortem/elf-core/elf-NT_FILE-memory-region.yaml
+8-4lldb/source/Plugins/Process/elf-core/ProcessElfCore.h
+196-454 files

FreeBSD/ports e886a66x11/libxfce4windowing distinfo Makefile

x11/libxfce4windowing: Fix internationalization

- Import upstream patch to correctly link to libintl [1]
- Add USES=localbase:ldflags to make meson find the libintl library

PR:             297303
Obtained from:  https://gitlab.xfce.org/xfce/libxfce4windowing/-/commit/83ffd4ac83920ecd7ad190e997539d7a60c8dd60.patch [1]
MFH:            2026Q3
DeltaFile
+6-3x11/libxfce4windowing/Makefile
+3-1x11/libxfce4windowing/distinfo
+9-42 files

LLVM/project 1addc8allvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp

[AArch64] Move tryFoldCselToFMaxMin to Select. NFC (#214346)

This moves the code out of PreprocessISelDAG into Select where it should
be performed.
DeltaFile
+25-25llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+25-251 files

NetBSD/src 96XC4Wosys/arch/evbmips/rmixl machdep.c

   Add  __diagused for mapname.
   Fixes non DIAGNOSTIC build for evbmips XLSATX(32/64) kernel config.
VersionDeltaFile
1.26+3-3sys/arch/evbmips/rmixl/machdep.c
+3-31 files

LLVM/project db3b067llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h GCNHazardRecognizer.h, llvm/test/CodeGen/AMDGPU wmma-trans-multi-shadow-hazard.mir coexec-hazardrec-preRA.mir

[AMDGPU] Model WMMA co-execution windows in the scheduler for gfx1250

WMMA instructions in gfx1250 expose an execution window during which
only certain other instruction classes may co-execute. Teach the hazard
recognizer about those windows so the scheduler can fill co-execution slots and
account for the resulting stalls. This adds a preRA hazard recognizer
mode.

Add AMDGPUCoExecInfo.h, a shared model of a co-execution window: the
per-stage capability bitmask, the stage types (CoExecStageType), and
CoExecInfo, which maps a multi-cycle instruction to its per-cycle slot
pattern via getCoExecInfo(). InstructionFlavor and its helpers move here
from AMDGPUCoExecSchedStrategy.h with no functional change so they can
be shared by the scheduler and the hazard recognizer.
DeltaFile
+505-0llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir
+463-0llvm/lib/Target/AMDGPU/AMDGPUCoExecInfo.h
+400-13llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+131-2llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+1-98llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+67-0llvm/test/CodeGen/AMDGPU/wmma-trans-multi-shadow-hazard.mir
+1,567-11310 files not shown
+1,634-14816 files

LLVM/project df5ba69llvm/test/CodeGen/AMDGPU bf16.ll flat-atomicrmw-fmin.ll

rebase to fix CI

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+9,385-9,006llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,575-5,393llvm/test/CodeGen/AMDGPU/maximumnum.ll
+5,454-5,259llvm/test/CodeGen/AMDGPU/minimumnum.ll
+4,720-5,590llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+4,720-5,590llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+4,729-4,972llvm/test/CodeGen/AMDGPU/bf16.ll
+34,583-35,81010,575 files not shown
+508,530-368,46810,581 files

LLVM/project f31478bllvm/test/CodeGen/AMDGPU bf16.ll flat-atomicrmw-fmin.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1-arichardson

[skip ci]
DeltaFile
+9,385-9,006llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,575-5,393llvm/test/CodeGen/AMDGPU/maximumnum.ll
+5,454-5,259llvm/test/CodeGen/AMDGPU/minimumnum.ll
+4,720-5,590llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+4,720-5,590llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+4,729-4,972llvm/test/CodeGen/AMDGPU/bf16.ll
+34,583-35,81010,576 files not shown
+508,532-368,47010,582 files

NetBSD/src fxO1rWqsys/arch/mips/rmi rmixl_cpu.c

   Fix typo in printf param: dp->ci_onproc -> ci->ci_onproc.
   Fixes evbmips XLSATX(32/64) DEBUG enabled kernel build.
VersionDeltaFile
1.16+3-3sys/arch/mips/rmi/rmixl_cpu.c
+3-31 files

LLVM/project 01de801llvm/include/llvm/IR RuntimeLibcalls.td, llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp

RuntimeLibcalls: Add generic FCMP3_F* three-way compare for single-symbol ABIs (#211618)

MSP430's __mspabi_cmpd/__mspabi_cmpf are one three-way compare symbol
serving every predicate, previously modeled as six suffixed impls each. Replace
them with a single generic operator FCMP3_*, and give softenSetCCOperands a
3rd lowering option. After the boolean O*_F* and the per-predicate
FCMP3_<pred>_F* helpers, use the generic FCMP3_F* helper tested with the predicate's
condition code.

Also opt __nedf2 out of the MSP430 default set: it was the only libgcc
F64 compare not already opted out, so it would otherwise provide
FCMP3_UNE_F64 and win over __mspabi_cmpd for not-equal.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+45-40llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+10-25llvm/include/llvm/IR/RuntimeLibcalls.td
+14-14llvm/lib/Target/MSP430/MSP430Subtarget.cpp
+69-793 files

LLVM/project 78da6bellvm/lib/Target/RISCV RISCVInstrInfo.td

fix inverted inheritance that broke tests

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+2-2llvm/lib/Target/RISCV/RISCVInstrInfo.td
+2-21 files

FreeBSD/ports 525e72bsysutils/tuptime distinfo Makefile

sysutils/tuptime: Update 5.2.3 => 5.2.6

Changelog:
https://github.com/rfmoz/tuptime/blob/5.2.6/CHANGELOG

- Replace spaces with tabs.
- Pet portclippy.

PR:             295072
Approved by:    Jeremy Johnston <jeremy at smart-serv.net> (maintaienr, timeout 3 months)
Sponsored by:   UNIS Labs
Co-authored-by: Vladimir Druzenko <vvd at FreeBSD.org>
DeltaFile
+5-6sysutils/tuptime/Makefile
+3-3sysutils/tuptime/distinfo
+8-92 files

FreeBSD/src 51acd75bin/sleep sleep.1

sleep: Fix man page about IGINFO output

Reviewed by:    des
MFC after:      1 week
Differential Revision:  https://reviews.freebsd.org/D58483

(cherry picked from commit 24983c4e9f9934282e8d81381095da819ad97c63)
DeltaFile
+2-4bin/sleep/sleep.1
+2-41 files

LLVM/project 9b2d1d4llvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp

[AArch64][GlobalISel] Cleanup old selection code for G_OR and fp instructions. (#213869)

G_OR can be selected via tablegen patterns, and other fp elements of
selectBinOp were no longer used. unsupportedBinOp was just testing
things that should always be true.
DeltaFile
+4-96llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+4-961 files

FreeBSD/src fc0d50abin/sleep sleep.1

sleep: Fix man page about IGINFO output

Reviewed by:    des
MFC after:      1 week
Differential Revision:  https://reviews.freebsd.org/D58483

(cherry picked from commit 24983c4e9f9934282e8d81381095da819ad97c63)
DeltaFile
+2-2bin/sleep/sleep.1
+2-21 files

LLVM/project 59a7bc1llvm/lib/CodeGen ReplaceWithVeclib.cpp, llvm/test/Transforms/ReplaceWithVeclib veclib-invalid-intrinsic.ll

[CodeGen] ReplaceWithVeclib assertion failure with invalid intrinsic (#211352)

Commit f6a359f (#194639) removed an intrinsic ID check against
Intrinsic::not_intrinsic.

This check is needed because a call instruction can be cast to an
intrinsic instruction if the called function's name starts with "llvm."
(see llvm::Function::isIntrinsic).

This means if ReplaceWithVeclib is given an invalid intrinsic, it will
fail with an assertion failure.
DeltaFile
+14-0llvm/test/Transforms/ReplaceWithVeclib/veclib-invalid-intrinsic.ll
+1-1llvm/lib/CodeGen/ReplaceWithVeclib.cpp
+15-12 files

LLVM/project 3212ba9llvm/lib/Target/PISA/MCTargetDesc PISATargetStreamer.cpp

Formatting fix
DeltaFile
+2-2llvm/lib/Target/PISA/MCTargetDesc/PISATargetStreamer.cpp
+2-21 files

LLVM/project 1bc9dc0llvm/include/llvm/IR RuntimeLibcalls.td, llvm/lib/Target/Hexagon HexagonSubtarget.h HexagonSubtarget.cpp

Hexagon: Stop excluding some generic compiler-rt functions from libcalls

RuntimeLibcalls should indicate any function that exists and is callable.
Historically the list of library functions was conflated with the library
functions which should be used, so the library definition was complicated
by excluding the overridden cases. My reading of the compiler-rt sources is
that the generically named functions are built alongside the __hexagon
prefixed variants. e.g., __divsi3 and __hexagon_divsi3 both exist.

It will simplify future libcall work the fewer special case target exclusions
there are, so allow the functions to be defined and apply the selection
preference for the __hexagon prefixed versions in LibcallLoweringInfo.

I do question why compiler-rt is built this way; why doesn't the hexagon
just replace the standard entrypoint names with the target implementations?

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+29-0llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+5-4llvm/include/llvm/IR/RuntimeLibcalls.td
+3-0llvm/lib/Target/Hexagon/HexagonSubtarget.h
+37-43 files

LLVM/project cde9747llvm/lib/Target/PISA PISAInstrInfo.cpp PISAInstrFormats.td, llvm/lib/Target/PISA/MCTargetDesc PISAInstPrinter.cpp PISATargetStreamer.cpp

Add PISA register file, instruction set, and MC layer

Add the PISA register file and register-bank descriptions, the instruction
formats and definitions, and the MC/assembly layer (instruction printer,
register and code encoders, target streamer, MC target description and the
supporting enums), replacing the stub descriptions from
the initial target skeleton.

This provides the instruction-set description and assembly-emission
foundation. The GlobalISel lowering and instruction selection that consume it
are added in the following changes.
DeltaFile
+2,511-11llvm/lib/Target/PISA/PISAInstrInfo.td
+1,075-0llvm/lib/Target/PISA/PISACombine.td
+834-0llvm/lib/Target/PISA/PISAInstrFormats.td
+572-0llvm/lib/Target/PISA/MCTargetDesc/PISATargetStreamer.cpp
+448-1llvm/lib/Target/PISA/PISAInstrInfo.cpp
+394-11llvm/lib/Target/PISA/MCTargetDesc/PISAInstPrinter.cpp
+5,834-2333 files not shown
+8,449-6439 files

LLVM/project 5270be7llvm/include/llvm/IR RuntimeLibcalls.td

RuntimeLibcalls: Add sqrtf to the Hexagon runtime libcall set (#210909)

The library definitions go out of the way to avoid adding sqrtf, in
favor of __hexagon_sqrtf. I'm assuming that libm does provide sqrtf, 
it just happens that there is a more-preferred function to use.
RuntimeLibcallsInfo should express the full set of functions that do exist, 
and LibcallLoweringInfo should express the preference for which calls 
should be used.

By the current ordering rules, it just so happens __hexagon_sqrtf will
win out for SQRT_F32. Add this to avoid a special case to faciliate future
libcall improvements.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+1-1llvm/include/llvm/IR/RuntimeLibcalls.td
+1-11 files

LLVM/project 63e29d4llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.sad.u8.ll llvm.amdgcn.sad.u16.ll

[AMDGPU][GISel] RegBankLegalize rules for SAD intrinsics (#214329)
DeltaFile
+141-11llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
+108-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
+108-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
+108-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
+6-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+471-295 files

LLVM/project df29e5ellvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.incperflevel.ll llvm.amdgcn.s.decperflevel.ll

[AMDGPU][GISel] RegBankLegalize rules for s_incperflevel/s_decperflevel (#214327)
DeltaFile
+2-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll
+2-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+6-03 files

NetBSD/pkgsrc JZaKNhmdoc CHANGES-2026

   doc: Updated www/resterm to 0.51.3
VersionDeltaFile
1.5002+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc iTOBCe2www/resterm go-modules.mk Makefile

   resterm: Update to 0.51.3

   Fixed
   Text wrapping
   The wrapper walked text one rune at a time, which broke down on anything past plain ASCII. Most of the time invisible, but it was an real bug. It now works in grapheme clusters.
   * Emoji sequences, combining accents and joined characters no longer get cut in half at a wrap point.
   * Zero-width runes no longer count as a cell, so lines containing combining marks stop wrapping earlier than they should have.
   * Double-width characters (CJK and similar) can no longer push a row past the pane width. A row that overflowed got wrapped a second time by the terminal, which put the cursor and selection on the wrong line.
   * A character too wide to fit beside an indent now moves down whole, and if it still does not fit, the indent is dropped rather than overflowing the row.
   * A character wider than the entire row is placed on a row of its own instead of looping.
   Row mapping was counted from the size of the output buffer. Blank lines add no bytes, so they were skipped and the map claimed more rows than existed. Cursor movement and selection in bodies with blank lines landed one or more lines off. Rows are counted directly now.

   Color handling had two leaks:
   * A reset arriving after the last visible character on a line was dropped together with the empty continuation row it landed on, so the color carried into everything below it.
   * An escape sequence that appeared inside a run of whitespace was discarded when that whitespace was trimmed at a wrap point.
   Also in this area:
   * Pre mode no longer produces rows containing only indentation.
   * CRLF, control bytes and invalid UTF-8 no longer throw off width accounting or get dropped from the output.
   * Extended color codes such as ESC[38;5;0m are read as a color, not as a reset.

    [7 lines not shown]
VersionDeltaFile
1.23+3-3www/resterm/distinfo
1.25+1-1www/resterm/Makefile
1.14+0-0www/resterm/go-modules.mk
+4-43 files

LLVM/project 7b40f0bllvm/include/llvm/IR PISAIntrinsicUtils.h IntrinsicsPISA.td, llvm/include/llvm/Support PISAAddrSpace.h

Add PISA IR intrinsics and address-space utilities

This patch adds the PISA IR intrinsics definitions, address space
utilities, and basic tests.
DeltaFile
+252-0llvm/include/llvm/IR/IntrinsicsPISA.td
+121-0llvm/lib/IR/PISAIntrinsicUtils.cpp
+72-0llvm/include/llvm/IR/PISAIntrinsicUtils.h
+59-0llvm/include/llvm/Support/PISAAddrSpace.h
+24-0llvm/test/CodeGen/PISA/intrinsics-attributes.ll
+20-0llvm/test/CodeGen/PISA/intrinsics-address-space.ll
+548-05 files not shown
+572-011 files

LLVM/project fec5310llvm/lib/Target/PISA PISARegisterInfo.td PISATargetMachine.h, llvm/lib/Target/PISA/MCTargetDesc PISAMCAsmInfo.cpp PISAMCTargetDesc.cpp

Add PISA target registration and backend stub

Register the Intel GPU portable ISA (PISA) target. Add the pisa Triple
arch, data layout, and a minimal MC/TargetMachine skeleton.
DeltaFile
+85-0llvm/lib/Target/PISA/PISATargetMachine.cpp
+64-0llvm/lib/Target/PISA/MCTargetDesc/PISAMCTargetDesc.cpp
+61-0llvm/lib/Target/PISA/PISASubtarget.h
+46-0llvm/lib/Target/PISA/PISATargetMachine.h
+41-0llvm/lib/Target/PISA/MCTargetDesc/PISAMCAsmInfo.cpp
+39-0llvm/lib/Target/PISA/PISARegisterInfo.td
+336-025 files not shown
+880-031 files

LLVM/project 4e3fb02llvm/lib/Target/PISA PISARegisterInfo.h, llvm/lib/Target/PISA/MCTargetDesc CMakeLists.txt

Review fixes
DeltaFile
+1-1llvm/lib/Target/PISA/PISARegisterInfo.h
+1-1llvm/lib/Target/PISA/MCTargetDesc/CMakeLists.txt
+2-22 files