[CIR][CodeGen] Emit cir.fmuladd for FP-contracted mul+add/sub (#215382)
Ports the FP-contraction fusion from classic CodeGen (`tryEmitFMulAdd` /
`buildFMulAdd`) to CIRGen. Under `-ffp-contract=on / fast`, `a * b + c`
and `a * b - c` fuse into `cir.fmuladd` (with the addend negated for the sub
form) instead of separate `cir.fmul` + `cir.fadd/fsub`.
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Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
routing: Fix table sizes
Tables that have one element per protocol or address family were
previously sized by AF_MAX + 1 since AF_MAX was off by one. Now that
AF_MAX has been corrected, we need to apply the opposite correction to
these tables.
Fixes: ddd850aa7720 ("sys/socket.h: Fix AF_MAX")
MFC after: 3 days
Sponsored by: Klara, Inc.
Sponsored by: NetApp, Inc.
Reviewed by: pouria, kevans, glebius
Differential Revision: https://reviews.freebsd.org/D58826
libifconfig: Fix table size
Tables that have one element per protocol or address family were
previously sized by AF_MAX + 1 since AF_MAX was off by one. Now that
AF_MAX has been corrected, we need to apply the opposite correction to
these tables.
Fixes: ddd850aa7720 ("sys/socket.h: Fix AF_MAX")
MFC after: 3 days
Sponsored by: Klara, Inc.
Sponsored by: NetApp, Inc.
Reviewed by: kevans
Differential Revision: https://reviews.freebsd.org/D58827
pciconf: Sort resource windows in order of decreasing alignment
instead of size.
Consider pci0 has two ppb's. ppb0 has a memory window larger in
size, but smaller in alignment. ppb1 has one smaller in size, but
larger in alignment.
In this case, the memory window of ppb1 must be allocated earlier.
Otherwise, total size of required memory exceeds pci0's mem_total,
in general, due to padding region.
[mlir][xegpu] Lower lane_data repack convert_layout to lane_shuffle (#210837)
Extend the SgToLaneConvertLayout pattern to lower a convert_layout that
only repacks lane_data between round-robin and contiguous form (keeping
lane_layout and order unchanged) into xegpu.lane_shuffle. Each lane
keeps the same elements and total bits along the repacked dimension, but
their assignment to lanes changes, so the data is moved across lanes
with a bit-preserving bitcast_shuffle.
assisted-by-claude
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Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
[mlir][XeGPU] Distribute create_nd_tdesc/load/store with SliceAttr layout (#216104)
## Summary
- `WgToSgCreateNdOp` and `XeGPUWgToSgDistributePass`'s dynamic legality
check only matched `xegpu::LayoutAttr` on a tensor_desc's layout, not
`xegpu::SliceAttr` (also a `DistributeLayoutAttr`).
- A tensor_desc feeding a unit-dim-expanding `vector.shape_cast` carries
a `SliceAttr`, so such `create_nd_tdesc`/`load_nd` ops were left
undistributed while their consumers were already converted to subgroup
shape, causing a `vector.shape_cast` element-count mismatch.
- Match on `DistributeLayoutAttr` instead, consistent with the rest of
the pass (`getSgShapeAndCount`, `genOffsetsList`, etc.).
## Test plan
- [x] Added a regression test to `xegpu-wg-to-sg.mlir`:
`create_nd_tdesc`/`load_nd` with a `SliceAttr` layout feeding
`shape_cast` (expand) → `arith.addf` → `shape_cast` (collapse) →
`store_nd`.
- [x] Verified the new test fails on `main` with the reported error and
passes with this fix.
Remove minor version from kmods repo
We don't have a kmods_quarterly_5 repo for releng/14.5 so don't point
users at it.
Direct commit to releng/14.5, hopefully to be reverted once the repo
exists.
Approved by: re (cperciva)
Sponsored by: OpenSats Initiative
[ORC] Align GDB-JIT alloc-action names with the ORC runtime (#216024)
Align LLVM's GDB-JIT registration alloc-action names with the names
added to the ORC runtime in 4a0fdbc25bb, and add a name for the
deregistration action.
Look these names up in the Bootstrap JITDylib rather than the Process
JITDylib. Since the lookup no longer depends on process symbols, drop
the "requires process symbols" preconditions guarding MachO debugger
support in llvm-jitlink and enableDebuggerSupport.
GDBJITDebugInfoRegistrationPlugin::Create also loses its Triple
parameter, which is now unused.
Together this lets GDBJITDebugInfoRegistrationPlugin work against either
the LLVM OrcTargetProcess or ORC runtime implementation of these
actions.
[lldb] Search for a corefile's images before loading any of them
A userland or kernel corefile can list hundreds of images, and searching for
one can shell out to a symbol server or fetch over the network. Searching for
them one at a time is where loading such a corefile spends its time.
Add a batch form of SymbolLocator::Locate that runs the searches on the
debugger's thread pool, gated on target.parallel-module-load. Results come
back in the order the requests were given, since that order decides the
Target's module order. Only the results are ordered, and anything a search
reports to the user arrives in whatever order the searches finish in.
Only the plugin searches run concurrently, so a platform hook does not have to
be thread safe to take part, and reading a binary's UUID out of memory stays
on the calling thread.
Setting up a platform binary can replace the Target's platform and dynamic
loader, and now happens for every image before any of them is searched for, so
the platform a corefile asks for is the one all of its images are searched
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[DWARFLinker] Constrain a function's high_pc to its own symbol
Mach-O objects built with .subsections_via_symbols make every symbol an
independently placeable atom, and the linker packs atoms without
preserving the spacing they had in the object file.
I have an example where the compiler describes such a subprogram as
extending past its own atom. While it's debatable whether that's a good
idea, it's not invalid in the object file. However, once linked, it is
invalid.
We can make dsymutil resilient against this by looking at the size of
the symbol in the debug map and adjusting the end_pc. I'm doing so
conservatively so that only a collision is repaired. Already
overlapping/invalid ranges remain untouched.
rdar://184768778
[CIR] Handle label address difference (#205437)
This change adds handling for emitting AddrLabelDiff constants. These
constants can be used to initialize static variables within a function
by computing the difference between the addresses of two labels. These
constant values are represented in the AST using the APValue class. The
code generator needs to emit them as initializers for the global
corresponding to the static variable.
This change introduces a new CIR attribute type, BlockAddrDiffAttr to
represent this constant value, deferring the label block address
resolution until we lower the initializer to the LLVM dialect.
Assisted-by: Cursor / claude-opus-4.8
[CIR] Implement CIRBasicAliasAnalysis::getUnderlyingObject (#215683)
This implements the CIRBasicAliasAnalysis::getUnderlyingObject to follow
casts, pointer strides, array element, and struct member accesses back
to the underlying alloca operation if the operation does not introduce
an offset from the original pointer operand.
This still conservatively returns MayAlias for any comparison involving
a pointer with a non-zero offset from its base alloca address. We could
go further, calculating the offset and determining non-alias or partial
alias from offset pointers, but that is deferred until a future PR.
Assisted-by: Claude / Sonnet-4.6
Revert "sys/socket.h: Fix AF_MAX"
Back out this change for 14.5-BETA2. It might come back with
changes, but in its current form it breaks ABI.
This reverts commit f77a60a27ad64e3acf26f3dc088c6e80fdd15754.
Approved by: re (cperciva)
