LLVM/project f14a8aallvm/test/CodeGen/X86 bit-manip-i512.ll bit-manip-i256.ll

[X86] add i256/i512 bit manipulation tests suggested by #132601 (#184813)

DeltaFile
+6,520-0llvm/test/CodeGen/X86/bit-manip-i512.ll
+3,257-0llvm/test/CodeGen/X86/bit-manip-i256.ll
+9,777-02 files

FreeBSD/src 6d2a147contrib/libedit map.c

libedit: fix use after free
DeltaFile
+2-2contrib/libedit/map.c
+2-21 files

LLVM/project 6b3f57dlldb/test/API/python_api/block TestFrameBlocks.py

[lldb] Skip SBBlock test on Windows. (#184818)

Skipping this test to unblock CI.
DeltaFile
+1-0lldb/test/API/python_api/block/TestFrameBlocks.py
+1-01 files

NetBSD/pkgsrc-wip 917b2delabwc distinfo Makefile

labwc: update to 0.9.5
DeltaFile
+3-3labwc/distinfo
+1-1labwc/Makefile
+4-42 files

LLVM/project a9fb8b0mlir/lib/Conversion/VectorToXeGPU VectorToXeGPU.cpp, mlir/test/Conversion/VectorToXeGPU contract-to-xegpu.mlir

[MLIR][XeGPU] Support vector.contract transpose_a/transpose_b via 'vector-to-gpu' patterns (#182885)

The PR adds [`vector.contract(transpose_a/transpose_b)` decomposition
patterns](https://github.com/llvm/llvm-project/blob/3215645b8d81bbef7db1d16b88de7ed0288f2274/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp#L1263)
from `vector-to-gpu` to `vector-to-xegpu` pass.

The `populatePrepareVectorToMMAPatterns` adds two patterns:
1. `PrepareContractToGPUMMA` that splits `vector.contract(transpose)`
into `vector.transpose + vector.contract`
2. `CombineTransferReadOpTranspose` that fuses `vector.transpose` into
the permutation map of `vector.transfer_read`

The second pattern doesn't always bring us to the desired result
(`xegpu.load_nd + vector.transpose + xegpu.dpas`) since [not all data
types are supported
](https://github.com/llvm/llvm-project/blob/1237bd6df05a4777f444677186e4814388916ea9/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp#L570-L575)
for the transposed-read case. There's a second PR (#182875) on this
matter that adds a decomposition-pattern for unsupported types (it might
seem strange that we first fuse and then decompose

    [5 lines not shown]
DeltaFile
+50-36mlir/test/Conversion/VectorToXeGPU/contract-to-xegpu.mlir
+2-0mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
+52-362 files

LLVM/project 3925d11mlir/lib/Conversion/VectorToXeGPU VectorToXeGPU.cpp, mlir/test/Conversion/VectorToXeGPU transfer-read-to-xegpu.mlir

[MLIR][XeGPU] Decompose unsupported 'vector.transfer_read'-transpose-permutations (#182875)

The PR adds a pattern to `vector-to-xegpu` pass that decomposes
`vector.transfer_read` with unsupported transpose-permutations
(unsupported element-type) into `vector.transfer_read +
vector.transpose`:

Example:

```mlir
// input-ir:
  %0 = vector.transfer_read %source[%offset, %offset], %c0
    {permutation_map = affine_map<(d0, d1) -> (d1, d0)>,
    in_bounds = [true, true]} : memref<32x64xf16>, vector<8x16xf16>

// mlir-opt %s --convert-vector-to-xegpu
// before PR (no conversion because of unsupported type):
  %0 = vector.transfer_read %source[%offset, %offset], %c0
    {permutation_map = affine_map<(d0, d1) -> (d1, d0)>,

    [10 lines not shown]
DeltaFile
+31-26mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
+6-4mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
+37-302 files

LLVM/project efb6f54llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-ext-rv64.ll

[RISCV] Don't make ISD::ABDS/ABDU legal for v2i32 with P extension. (#184753)

We don't have the instructions for this so it causes a cannot select
error.
DeltaFile
+36-6llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+3-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+39-72 files

LLVM/project 5c3d0ddmlir/lib/Dialect/MemRef/IR MemRefOps.cpp, mlir/test/Dialect/MemRef canonicalize.mlir

[mlir][memref] Fix crash in DimOp::fold for subview with ambiguous dropped dims (#183995)

When a rank-reducing subview has multiple size-1 source dimensions and
all strides are dynamic, `computeMemRefRankReductionMask` cannot
unambiguously determine which dimension is dropped. It would fall back
to an arbitrary choice that could be wrong.

In `DimOp::fold`, the code then maps a result dimension to that
(possibly incorrect) source dimension and asserts
`isDynamicSize(sourceIndex)`. If `getDroppedDims()` picked the wrong
dropped dim, the source dim at `sourceIndex` may be statically sized,
causing the assertion to fire.

Fix this by replacing the assert with a guard that returns `{}` (no
fold) when the resolved source dimension is not dynamic. This is safe
because the fold already handles the statically-sized result case
earlier.

Fixes #111244

Assisted-by: Claude Code
DeltaFile
+12-14mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
+21-0mlir/test/Dialect/MemRef/canonicalize.mlir
+33-142 files

LLVM/project 228dac2clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CIR/CodeGenBuiltins/AArch64 acle_sve_dup.c

Address PR comments
DeltaFile
+42-42clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c
+30-30clang/test/CodeGen/AArch64/neon/intrinsics.c
+6-6clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+4-4clang/test/CodeGen/AArch64/neon/fullfp16.c
+82-824 files

LLVM/project 2580ddfflang CMakeLists.txt

[flang] Fix distribution build of `ISO_Fortran_binding.h` to also install it in `CMAKE_INSTALL_INCLUDEDIR`. (#184284)

Currently with `-DLLVM_DISTRIBUTION_COMPONENTS="flang-fortran-binding"`,
header file `ISO_Fortran_binding.h` is only installed at
`./lib/clang/23/include/ISO_Fortran_binding.h`, but not in the user
include.
This PR is to fix that so that the `ISO_Fortran_binding.h` is also
installed at `./include/flang/ISO_Fortran_binding.h`, which is the same
as the "normal" (non-distribution) build.
DeltaFile
+4-0flang/CMakeLists.txt
+4-01 files

LLVM/project e9657a1lld/test/COFF base.test stack.test, llvm/lib/Object COFFModuleDefinition.cpp

COFF: Allow hex literals in .def files: BASE/HEAPSIZE/STACKSIZE (#184764)

For a Win32 DLL, a .def file can have a custom executable base:
```
LIBRARY "stub.dll" BASE=0x10000000
```

Currently the parser enforces Base 10, but [Microsoft's
documentation](https://learn.microsoft.com/en-us/cpp/build/reference/rules-for-module-definition-statements?view=msvc-170)
states "Numeric arguments are specified in base 10 or hexadecimal".

This fixes that, and also HEAPSIZE and STACKSIZE (which use the same
function).

There are a few more instances of `getAsInteger` that expect base10 -
for ordinals and the VERSION directive. Since I don't have an
in-the-wild example of a .def file using hexadecimal for these, I am
wary about changing those too.
DeltaFile
+15-0lld/test/COFF/base.test
+6-0lld/test/COFF/stack.test
+6-0lld/test/COFF/heap.test
+1-1llvm/lib/Object/COFFModuleDefinition.cpp
+28-14 files

FreeBSD/ports 5ddf3bemultimedia/navidrome distinfo Makefile

multimedia/navidrome: Update to 0.60.3

ChangeLog: https://github.com/navidrome/navidrome/releases/tag/v0.60.3
DeltaFile
+7-7multimedia/navidrome/distinfo
+3-3multimedia/navidrome/Makefile
+10-102 files

LLVM/project 8bcfd58flang-rt/lib/runtime execute.cpp, lldb/test/API/python_api/block TestFrameBlocks.py TestBlocks.py

asm

Created using spr 1.3.7
DeltaFile
+177-0mlir/unittests/IR/VerifierTest.cpp
+64-64flang-rt/lib/runtime/execute.cpp
+2-104llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+60-3mlir/lib/IR/Verifier.cpp
+59-0lldb/test/API/python_api/block/TestFrameBlocks.py
+0-59lldb/test/API/python_api/block/TestBlocks.py
+362-230133 files not shown
+887-519139 files

LLVM/project 749df98clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

fixup! More small fixes
DeltaFile
+15-37clang/lib/Sema/SemaARM.cpp
+11-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5-3clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-2clang/lib/Headers/arm_acle.h
+0-1clang/test/CodeGen/arm_acle.c
+33-435 files

LLVM/project 0b62aa3clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

fixup! Fixes for Caroline
DeltaFile
+27-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+1-12llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-2llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+0-3clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+30-174 files

LLVM/project 24fda04clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

fixup! Final changes before merge
DeltaFile
+47-0llvm/test/Verifier/AArch64/intrinsic-immarg.ll
+0-47llvm/test/Verifier/intrinsic-immarg.ll
+2-4clang/lib/Sema/SemaARM.cpp
+2-2clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+51-534 files

LLVM/project 5bb8e40clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

fixup! Address Carol's comments and fix git clang-format issues
DeltaFile
+27-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+20-0llvm/lib/IR/Verifier.cpp
+12-6clang/lib/Sema/SemaARM.cpp
+0-11clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-4llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+4-2clang/lib/Headers/arm_acle.h
+65-236 files

LLVM/project 3e8af58clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

fixup! Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`

Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
and use tablegen pattern for intrinsic, plus other small review changes.
DeltaFile
+47-75llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+69-32llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+42-47clang/lib/Sema/SemaARM.cpp
+21-12llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+10-12llvm/lib/Target/AArch64/AArch64InstrInfo.td
+17-5clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+206-1835 files not shown
+220-19211 files

LLVM/project f3b4f6fclang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td

fixup! Address more helpful review comments from Kerry
DeltaFile
+160-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4-4llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1-4clang/lib/Sema/SemaARM.cpp
+0-5llvm/lib/Target/AArch64/AArch64InstrFormats.td
+165-134 files

LLVM/project b2417b3llvm/lib/Target/AArch64 AArch64InstrFormats.td

fixup! Add $policy to MIOperandInfo
DeltaFile
+1-1llvm/lib/Target/AArch64/AArch64InstrFormats.td
+1-11 files

LLVM/project 7fadeedclang/lib/Sema SemaARM.cpp, clang/test/Sema/AArch64 pcdphint-atomic-store.c

fixup! Ensure Context.getTypeSize() is only called after checking ValType->isIntegerType()
DeltaFile
+6-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+3-2clang/lib/Sema/SemaARM.cpp
+9-22 files

LLVM/project eda89ebllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 pcdphint-atomic-store-diagnostic.ll

fixup! Move tests to llvm/test/Verifier
DeltaFile
+0-54llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+47-0llvm/test/Verifier/intrinsic-immarg.ll
+0-32llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+47-863 files

LLVM/project 723b0f0clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/IR Verifier.cpp

fixup! More small optimisations Kerry spotted
DeltaFile
+7-12clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-3llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+1-2llvm/lib/IR/Verifier.cpp
+10-173 files

LLVM/project ec158fallvm/test/CodeGen/AArch64 pcdphint-atomic-store.ll

fixup! Sort out testcases
DeltaFile
+54-102llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+54-1021 files

LLVM/project 8d54803clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

fixup! Small fixes Kerry has suggested
DeltaFile
+112-40llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+7-11clang/lib/Sema/SemaARM.cpp
+7-9llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+127-614 files

LLVM/project c47069allvm/lib/Target/AArch64 AArch64ISelLowering.cpp

fixup! Fix tests
DeltaFile
+2-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-01 files

LLVM/project c4dd5f0clang/include/clang/Basic BuiltinsAArch64.def, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup!

More small issues tidied, and remove gating.
DeltaFile
+6-2clang/test/Sema/AArch64/pcdphint-atomic-store.c
+2-2clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+0-2clang/lib/Headers/arm_acle.h
+1-1clang/include/clang/Basic/BuiltinsAArch64.def
+1-1clang/lib/Sema/SemaARM.cpp
+1-1clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+11-96 files

LLVM/project 42d910allvm/include/llvm/IR IntrinsicsAArch64.td, llvm/lib/Target/AArch64 AArch64InstrFormats.td

fixup! remove mayLoad/mayStore as suggested by Kerry
DeltaFile
+0-5llvm/lib/Target/AArch64/AArch64InstrFormats.td
+1-1llvm/include/llvm/IR/IntrinsicsAArch64.td
+1-62 files

LLVM/project 74593fbclang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup! Fix Kerry's CR comments and add negative test for "must be an integer type"
DeltaFile
+16-6llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+3-7clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+3-3clang/lib/Sema/SemaARM.cpp
+5-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+3-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-1clang/lib/Headers/arm_acle.h
+31-176 files

LLVM/project fb2087cclang/test/CodeGen arm_acle.c builtins-arm64.c, clang/test/Sema/AArch64 pcdphint-atomic-store.c

fixup! Fix more PR comments
DeltaFile
+19-9clang/test/Sema/AArch64/pcdphint-atomic-store.c
+8-6llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+10-0clang/test/CodeGen/arm_acle.c
+0-9llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5-0clang/test/CodeGen/builtins-arm64.c
+0-4llvm/include/llvm/IR/IntrinsicsAArch64.td
+42-282 files not shown
+44-328 files