LLVM/project 89e736dflang/lib/Optimizer/Analysis AliasAnalysis.cpp, flang/test/Analysis/AliasAnalysis modref-call-memory-effects.fir

[flang][test] Experimental support of MemoryEffectOpInterface for fir.call. (#191580)

I would like to experiment with `fir.call` implementing
`MemoryEffectOpInterface`. So the main change is the fall-through
path in FIR AA. It should be NFC for Flang.
DeltaFile
+49-0flang/test/lib/Analysis/AliasAnalysis/TestAliasAnalysis.cpp
+28-0flang/test/Analysis/AliasAnalysis/modref-call-memory-effects.fir
+7-2flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
+84-23 files

FreeNAS/freenas d5e3182src/middlewared/middlewared/plugins/pool_ scrub.py dedup.py, src/middlewared/middlewared/plugins/zpool scrub.py

not on Sphinx 9 yet
DeltaFile
+2-2src/middlewared/middlewared/plugins/pool_/scrub.py
+1-1src/middlewared/middlewared/plugins/pool_/dedup.py
+1-1src/middlewared/middlewared/plugins/zpool/scrub.py
+4-43 files

LLVM/project 25ccdfaclang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.h

fix build issue
DeltaFile
+1-0clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
+1-01 files

FreeBSD/doc 8fb7bbewebsite/content/ru art.adoc

website/ru: Update art.adoc

Update to EN edfc3c87d90223e2c11e0c76a524f4cc5c903010
DeltaFile
+35-39website/content/ru/art.adoc
+35-391 files

LLVM/project 1f93b92clang/lib/Sema SemaAttr.cpp

concise findCXXNewExpr
DeltaFile
+2-3clang/lib/Sema/SemaAttr.cpp
+2-31 files

FreeBSD/src 04b994dsys/net bpf.c

bpf: fix handling the read timeout on ppc64

On platforms other than amd64, BIOCSRTIMEOUT is equal to
BIOCSRTIMEOUT32. Therefore, running the COMPAT_FREEBSD32 code
basically clears tv_usec on big endian platforms. When tcpdump is
used, the timeout requested is 100ms, which gets cleared to 0 on
ppc64 platforms. This results in tcpdump showing the packets only
when the read buffer is full.
Thanks to kib for guiding me to the correct fix.

Reported by:            ivy
Reviewed by:            adrian, kib
MFC after:              3 days
Differential Revision:  https://reviews.freebsd.org/D56399
DeltaFile
+22-20sys/net/bpf.c
+22-201 files

FreeBSD/ports 5a3cba2sysutils/acpica-tools distinfo Makefile

sysutils/acpica-tools: Update to 20260408

https://github.com/acpica/acpica/releases/download/20260408/changes.txt
DeltaFile
+3-3sysutils/acpica-tools/distinfo
+1-1sysutils/acpica-tools/Makefile
+4-42 files

FreeNAS/freenas 6966d97src/middlewared/middlewared/plugins/iscsi_ lio.py global_linux.py, src/middlewared/middlewared/pytest/unit/plugins test_truenas_connect.py

Merge branch 'master' of https://github.com/truenas/middleware into NAS-140095
DeltaFile
+1,281-0src/middlewared/middlewared/utils/lio/config.py
+1,098-0tests/sharing_protocols/iscsi/test_264_iscsi_mode_compat.py
+283-750src/middlewared/middlewared/pytest/unit/plugins/test_truenas_connect.py
+369-0src/middlewared/middlewared/plugins/iscsi_/lio.py
+237-0tests/sharing_protocols/iscsi/test_265_iscsi_portal_binding.py
+87-99src/middlewared/middlewared/plugins/iscsi_/global_linux.py
+3,355-84939 files not shown
+4,432-1,25945 files

OPNSense/core a7ddcd8src/opnsense/mvc/app/controllers/OPNsense/Routing/forms dialogEditGateway.xml, src/opnsense/mvc/app/models/OPNsense/Routing Gateways.xml

system: allow gateway load balance weights from 1 to 10 for more flexibility (#10148)

fixes #10147
DeltaFile
+1-1src/opnsense/mvc/app/models/OPNsense/Routing/Gateways.xml
+1-1src/opnsense/mvc/app/controllers/OPNsense/Routing/forms/dialogEditGateway.xml
+2-22 files

FreeNAS/freenas e168c5csrc/middlewared/middlewared/api/v26_0_0 zpool_scrub.py, src/middlewared/middlewared/api/v27_0_0 zpool_scrub.py

fix
DeltaFile
+112-171tests/api2/test_zpool_scrub.py
+61-44src/middlewared/middlewared/plugins/zpool/scrub_impl.py
+3-7src/middlewared/middlewared/plugins/pool_/scrub.py
+0-2src/middlewared/middlewared/api/v27_0_0/zpool_scrub.py
+0-2src/middlewared/middlewared/api/v26_0_0/zpool_scrub.py
+1-0src/middlewared/middlewared/plugins/zpool/scrub.py
+177-2266 files

LLVM/project cdfd0b6clang/lib/Headers __clang_cuda_runtime_wrapper.h

[CUDA] Change __CUDACC__ definition to 1 (#189457)

I recently encountered an issue where `nccl` used `#if __CUDACC__` ,
assuming `__CUDACC__` is not only defined but having a #if-able value.


https://github.com/NVIDIA/nccl/blob/v2.28.3-1/src/include/nccl_device/coop.h#L18

Looking at nvcc invocation, I see that:
```
echo "" | nvcc -x cu -E -Xcompiler -dM - | grep __CUDACC__
#define __CUDACC__ 1
```

Changing __CUDACC__ to 1 to match what NVIDIA downstream code
assumptions.
DeltaFile
+5-5clang/lib/Headers/__clang_cuda_runtime_wrapper.h
+5-51 files

LLVM/project 7b24f05clang/lib/Sema SemaAttr.cpp

format
DeltaFile
+5-5clang/lib/Sema/SemaAttr.cpp
+5-51 files

LLVM/project f95a9b3clang/lib/Sema SemaAttr.cpp

add docs
DeltaFile
+4-0clang/lib/Sema/SemaAttr.cpp
+4-01 files

LLVM/project dc86abcllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484
DeltaFile
+7-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+7-01 files

LLVM/project e7db400llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

Formatting

Change-Id: I3d89fba145471141ef945b1de15330caa245e82d
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+8-72 files

LLVM/project dc80075llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Claude Code review

Change-Id: Iab06de2981b27667cc29a56931dd378ecf7a1b0c
DeltaFile
+115-109llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+16-26llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+5-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+136-1353 files

LLVM/project 66ff79fllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

clang-format

Change-Id: I534b1a979f55339a814ef3416c2492252845add5
DeltaFile
+6-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+6-31 files

LLVM/project 0a1d2e7llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Make fence heuristic work bottom-up

Change-Id: I629cbc8905b87a962e8b123287e5f60a3154df6b
DeltaFile
+19-17llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+19-171 files

LLVM/project 333b8d3llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add comment

Change-Id: I2180bba631fe4a01ed3c3fbcfa8c19cbefa84133
DeltaFile
+1-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-01 files

LLVM/project 7bd577ellvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

[AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5
DeltaFile
+323-0llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+77-23llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+18-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+418-233 files

LLVM/project 4a4e98fllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Typo

Change-Id: I8b8da8a07be84506483f474d0a5e10ad79178c15
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+1-11 files

LLVM/project de914f9llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

[AMDGPU] Add stalls for DS FIFO buffer

Change-Id: I73e56da97a931349e0655e4e20b24aeb97920647
DeltaFile
+61-54llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+41-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+41-5llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+143-653 files

LLVM/project 253d61allvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f
DeltaFile
+7-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+7-11 files

LLVM/project 646831cllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

[AMDGPU] Add block carried latency to CoExecSched

Change-Id: Ib04e40e57d38e127d6c5452d1719e32dacef2ade
DeltaFile
+880-4llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+167-67llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+0-37llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+23-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+0-4llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+1,070-1185 files

LLVM/project a21d492llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Merge conflicts

Change-Id: I33564a1e5d14f3b53577cb463ba2cb3a7993fd24
DeltaFile
+50-57llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+54-602 files

LLVM/project 508a211llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Merge conflict

Change-Id: I24f471688f9d0604b45e95a4fa4da85fb0d9ed76
DeltaFile
+23-22llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+27-4llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+50-262 files

LLVM/project 419867fllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h

Claude Code review

Change-Id: Id4983ca59270c8bb2d261d38a6e7f2483c9d237e
DeltaFile
+15-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+16-12 files

LLVM/project f898e26llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

[AMDGPU] Address follow-up concerns from 189121

Change-Id: I7ae986ab2a22d7e8a8a04a8d3923412b6688ad99
DeltaFile
+20-21llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+6-9llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+26-302 files

FreeBSD/ports 5af40b2devel/nextpnr Makefile, devel/nextpnr-devel Makefile

devel/nextpnr*: Bump after dependency change

The devel/prjpeppercorn112 dependency was changed from using a custom
distfile mirror to upstream provided distfiles.
Bumping the consumers to trigger a rebuild to take the custom mirror
offline afterwards.
DeltaFile
+1-0devel/nextpnr-devel/Makefile
+1-0devel/nextpnr/Makefile
+2-02 files

LLVM/project cc5cd70clang/lib/Sema SemaTemplateInstantiateDecl.cpp, clang/test/Sema/Inputs lifetime-analysis.h

fix spaces
DeltaFile
+1-1clang/test/Sema/Inputs/lifetime-analysis.h
+0-1clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
+1-22 files