LLVM/project 355b676mlir .clang-tidy

[MLIR][NFC] Ignore clang-tidy `modernize-use-using` check in C code (#180326)

In the MLIR C API headers, clang-tidy’s `modernize-use-using` check
reports a large number of type definitions that use `typedef`. In my
IDE, this even causes the `typedef` code to be shown as struck through.
However, in this case it is clearly not possible to replace them with
`using`. This PR suppresses the `modernize-use-using` check for the code
inside `extern "C"` blocks.
DeltaFile
+2-0mlir/.clang-tidy
+2-01 files

LLVM/project 3d2353bllvm/unittests/CodeGen MFCommon.inc MachineInstrTest.cpp

fix unittest

Created using spr 1.3.5-bogner
DeltaFile
+7-1llvm/unittests/CodeGen/MFCommon.inc
+3-0llvm/unittests/CodeGen/MachineInstrTest.cpp
+2-0llvm/unittests/CodeGen/MachineOperandTest.cpp
+12-13 files

LLVM/project 6b97a83llvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

Remove IsRVVWideningReduction

Created using spr 1.3.6-beta.1
DeltaFile
+3-5llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+3-51 files

LLVM/project 985116dllvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+1-11 files

LLVM/project 6bd4d28llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp AMDGPUMCInstLower.cpp, llvm/test/CodeGen/AMDGPU asyncmark-max-pregfx12.ll asyncmark-pregfx12.ll

[AMDGPU] Introduce asyncmark/wait intrinsics

Asynchronous operations are memory transfers (usually between the global memory
and LDS) that are completed independently at an unspecified scope. A thread that
requests one or more asynchronous transfers can use async marks to track their
completion. The thread waits for each mark to be completed, which indicates that
requests initiated in program order before this mark have also completed.

For now, we implement asyncmark/wait operations on pre-GFX12 architectures that
support "LDS DMA" operations. Future work will extend support to GFX12Plus
architectures that support "true" async operations.

Co-authored-by: Ryan Mitchell ryan.mitchell at amd.com

Fixes: SWDEV-521121
DeltaFile
+268-12llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+279-0llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
+194-75llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
+38-16llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
+19-0llvm/test/CodeGen/AMDGPU/asyncmark-err.ll
+15-1llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+813-1047 files not shown
+874-10913 files

LLVM/project 134e9b1llvm/docs AMDGPUAsyncOperations.rst, llvm/lib/Target/AMDGPU SIISelLowering.cpp FLATInstructions.td

[AMDGPU] Asynchronous loads from global/buffer to LDS on pre-GFX12

The existing "LDS DMA" builtins/intrinsics copy data from global/buffer pointer
to LDS. These are now augmented with their ".async" version, where the compiler
does not automatically track completion. The completion is now tracked using
explicit mark/wait intrinsics, which must be inserted by the user. This makes it
possible to write programs with efficient waits in software pipeline loops. The
program can now wait for only the oldest outstanding operations to finish, while
launching more operations for later use.

This change only contains the new names of the builtins/intrinsics, which
continue to behave exactly like their non-async counterparts. A later change
will implement the actual mark/wait semantics in SIInsertWaitcnts.

Fixes: SWDEV-521121
DeltaFile
+444-0llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
+238-0llvm/docs/AMDGPUAsyncOperations.rst
+91-0llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
+38-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+37-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
+13-12llvm/lib/Target/AMDGPU/FLATInstructions.td
+861-1723 files not shown
+1,066-7629 files

FreeBSD/ports a1184e5x11/wleave distinfo Makefile

x11/wleave: Update to 0.7.1

Changelog: https://github.com/AMNatty/wleave/releases/tag/0.7.1

Reported by:    GitHub (watch releases)
DeltaFile
+3-3x11/wleave/distinfo
+1-2x11/wleave/Makefile
+4-52 files

LLVM/project 9fd411fbolt/include/bolt/Core BinaryContext.h, bolt/lib/Core BinaryContext.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.5-bogner
DeltaFile
+5-2lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+4-2llvm/unittests/MC/AMDGPU/Disassembler.cpp
+2-1llvm/unittests/MC/SystemZ/SystemZMCDisassemblerTest.cpp
+3-0bolt/include/bolt/Core/BinaryContext.h
+2-1bolt/lib/Core/BinaryContext.cpp
+1-2lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+17-811 files not shown
+35-1617 files

LLVM/project 6e210f4bolt/lib/Core BinaryContext.cpp, lldb/source/Plugins/Disassembler/LLVMC DisassemblerLLVMC.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.5-bogner
DeltaFile
+15-11llvm/lib/MC/MCContext.cpp
+3-5llvm/lib/MC/MCObjectStreamer.cpp
+3-4llvm/lib/MC/ELFObjectWriter.cpp
+5-2lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+5-1bolt/lib/Core/BinaryContext.cpp
+5-1llvm/include/llvm/MC/TargetRegistry.h
+36-2418 files not shown
+70-4224 files

LLVM/project 5925521lldb/source/Plugins/Disassembler/LLVMC DisassemblerLLVMC.cpp, lldb/source/Plugins/Instruction/MIPS EmulateInstructionMIPS.cpp EmulateInstructionMIPS.h

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.5-bogner

[skip ci]
DeltaFile
+5-2lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+4-2llvm/unittests/MC/AMDGPU/Disassembler.cpp
+1-2lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+3-0lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
+1-2lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+2-1llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp
+16-911 files not shown
+35-1617 files

FreeBSD/src 8f23665sys/amd64/include pcb.h, sys/arm/include pcb.h

pcb.h: mark struct pcb to be preserved

There are programs that depend on this structure (e.g. kernel debuggers)
that breaks when the ABI changes.

Signed-off-by:  Minsoo Choo <minsoochoo0122 at proton.me>
Reviewed by:    kib
MFC after:      1 week
Differential Revision:  https://reviews.freebsd.org/D55149
DeltaFile
+11-10sys/amd64/include/pcb.h
+9-8sys/i386/include/pcb.h
+5-0sys/arm64/include/pcb.h
+5-0sys/riscv/include/pcb.h
+5-0sys/powerpc/include/pcb.h
+4-0sys/arm/include/pcb.h
+39-186 files

OpenBSD/ports zXElWKGemulators/libchdr Makefile distinfo, emulators/libchdr/patches patch-CMakeLists_txt

   Update to a newer revision of libchdr (last commit 2026-12-26).

   From "Matthew"; thanks!
VersionDeltaFile
1.6+4-4emulators/libchdr/Makefile
1.3+2-2emulators/libchdr/distinfo
1.2+0-0emulators/libchdr/patches/patch-CMakeLists_txt
+6-63 files

LLVM/project 7240aefllvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+1-11 files

LLVM/project 78f33e5llvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+1-11 files

LLVM/project 569d01fllvm/lib/Target/RISCV RISCVInstrInfoZvabd.td

Use VALUVs2

Created using spr 1.3.6-beta.1
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+1-11 files

LLVM/project bd4784allvm/lib/Target/RISCV RISCVSchedSpacemitX100.td, llvm/test/tools/llvm-mca/RISCV/SpacemitX100 atomic.test floating-point.test

[RISCV] Add SpacemiT X100 base scheduling model (#178189)

SpacemiT X100 is a 4-issue, out-of-order, RVA23 processor. This patch
introduces the base scheduling model for scalar instructions. The
scheduling model for RVV will be added in a future update.
DeltaFile
+370-0llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td
+224-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/atomic.test
+168-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/floating-point.test
+160-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/integer.test
+96-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/zbb.test
+78-0llvm/test/tools/llvm-mca/RISCV/SpacemitX100/zfh.test
+1,096-08 files not shown
+1,478-114 files

LLVM/project e4674b8bolt/lib/Profile DataAggregator.cpp

[BOLT][NFC] Stop populating unnecessary samples into MemSamples (#179472)

Currently, many unnecessary samples are populated into MemSamples,
including zero-initialized samples and samples in which the PC address
is not contained in any BinaryFunction. But these samples are totally
skipped during processing and the whole MemSamples vector is cleared
immediately after processing. So, we could just stop populating these
samples into MemSamples, which would reduce maximum resident set size
when processing a large perf.data.
DeltaFile
+3-3bolt/lib/Profile/DataAggregator.cpp
+3-31 files

FreeBSD/src 11b616dusr.bin/sockstat sockstat.c

sockstat: Surround explicit IPv6 addresses with brackets

Approved by:    re (cperciva)
PR:             254611
Approved by:    otis, tuexen, des
MFC after:      1 week
Differential Revision:  https://reviews.freebsd.org/D54375

(cherry picked from commit fe81e3944c085e765c83c4f78941d7529ceb556e)
(cherry picked from commit 03c8e3e77114530f61e0dd9f2b1757eeea033d0e)
DeltaFile
+9-0usr.bin/sockstat/sockstat.c
+9-01 files

FreeBSD/src 5d7d225lib/libpmc/pmu-events/arch/x86/graniterapids uncore-cache.json uncore-interconnect.json

pmc: Import Intel Granite Rapids events

Approved by:    re (cperciva)
Reviewed by:    mhorne
Sponsored by:   Klara, Inc.
Obtained from:  Intel perfmon (JSON event definitions)
Differential Revision:  https://reviews.freebsd.org/D55081
MFC after:      2 days

(cherry picked from commit a3ff85e11925ba1e25465c8ba633356f405f9214)
(cherry picked from commit 625ed651833e76a439a7010aa28c93bc83013168)
DeltaFile
+3,745-0lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-cache.json
+1,979-0lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-interconnect.json
+1,925-0lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-io.json
+1,230-0lib/libpmc/pmu-events/arch/x86/graniterapids/cache.json
+1,145-0lib/libpmc/pmu-events/arch/x86/graniterapids/pipeline.json
+890-0lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-memory.json
+10,914-010 files not shown
+12,550-016 files

LLVM/project 0f26436mlir/test/lib/Dialect/SPIRV TestEntryPointAbi.cpp

[MLIR][SPIRV][NFC] Fix header comment in TestEntryPointAbi.cpp (#177350)

DeltaFile
+1-1mlir/test/lib/Dialect/SPIRV/TestEntryPointAbi.cpp
+1-11 files

FreeBSD/ports 784116dx11-toolkits/amtk distinfo Makefile

x11-toolkits/amtk: update to 5.9.2

- Update to 5.9.2

    News in 5.9.2, 2025-11-17
    -------------------------
    * Translation updates.

- Switch to USES= gettext-tools

PR:             291494
DeltaFile
+3-3x11-toolkits/amtk/distinfo
+2-2x11-toolkits/amtk/Makefile
+1-0x11-toolkits/amtk/pkg-plist
+6-53 files

FreeBSD/ports e0363f9net-im/libnice Makefile distinfo, net-im/libnice-gst1 Makefile pkg-plist

net-im/libnice*: update to 0.1.23

Update to 0.1.23

libnice 0.1.23 (2025-11-26)
===========================
API: Added option NICE_AGENT_OPTION_CLOSE_FORCED to not wait for TURN when
  closing asynchronous
Reject invalid remote candidates with priority=0
Add missing mutex in tcp-bsd socket
Add buffer list support to nicesrc
Avoid dropping packing in nicesink, retry instead
Only create a new NiceCandidate if a socket can be opened, as it is
 a somewhat costly operation.
Many new tests
Fix leaks
Fix various test flakiness

Adjust dependencies.

    [12 lines not shown]
DeltaFile
+6-9net-im/libnice/Makefile
+3-3net-im/libnice/distinfo
+0-5net-im/libnice-gst1/Makefile
+1-1net-im/libnice-gst1/pkg-plist
+1-1net-im/libnice/pkg-plist
+11-195 files

FreeBSD/ports 9cb420ddevel/py-sqlfluff distinfo Makefile

devel/py-sqlfluff: Update to 4.0.4
DeltaFile
+3-3devel/py-sqlfluff/distinfo
+1-1devel/py-sqlfluff/Makefile
+4-42 files

FreeBSD/ports 4171ee0audio/vgmplay Makefile distinfo, audio/vgmplay/files patch-main.cpp

audio/vgmplay: Update to 0.52.0

While here:
- add DOCS option
- sort variable order to make portclippy happy

Changelog: https://github.com/ValleyBell/vgmplay-libvgm/blob/0.52.0/Updates.txt

Reported by:    portscout
DeltaFile
+11-7audio/vgmplay/Makefile
+0-11audio/vgmplay/files/patch-main.cpp
+3-3audio/vgmplay/distinfo
+14-213 files

FreeBSD/ports 6de0465audio/libvgm Makefile distinfo

audio/libvgm: Update to g20260121 (latest GitHub commit)

Changelog: https://github.com/ValleyBell/libvgm/compare/7cad783...57585ea
DeltaFile
+3-3audio/libvgm/Makefile
+3-3audio/libvgm/distinfo
+4-1audio/libvgm/pkg-plist
+10-73 files

FreeBSD/src 2088e74sys/x86/include frame.h

x86: Note that trapframe is used by kernel debuggers

Signed-off-by: Minsoo Choo <minsoochoo0122 at proton.me>
Reviewed by: kib
MFC after:      1 week
Differential Revision: https://reviews.freebsd.org/D55189
DeltaFile
+1-0sys/x86/include/frame.h
+1-01 files

NetBSD/src qmEHkVfshare/misc acronyms.comp

   +OVMF  Open Virtual Machine Firmware
VersionDeltaFile
1.421+2-1share/misc/acronyms.comp
+2-11 files

LLVM/project 80f627ellvm/include/llvm/MC TargetRegistry.h

TargetRegistry: Remove deprecated create*Info that take StringRef parameter (#180448)

DeltaFile
+0-43llvm/include/llvm/MC/TargetRegistry.h
+0-431 files

LLVM/project 84b5e9fllvm/lib/Target/RISCV RISCVFrameLowering.cpp, llvm/test/CodeGen/RISCV zcmp-cm-popretz.mir

[RISCV] Add used callee-saved registers as implicit/implicit-def registers to save/restore call (#180133)

We should add used callee-saved registers as implicit used to save
libcall and as implicit defined to restore libcall. It likes what we did
for CM_PUSH/CM_POPRET. That can help to construct correct dataflow. In
entry bb, save libcall implicitly uses the callee-saved registers which
live in. And in return bb, restore libcall implicitly defines the
callee-saved registers which live out.
DeltaFile
+24-19llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+8-8llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
+32-272 files

FreeBSD/ports a035f11emulators/wine-devel distinfo pkg-plist

emulators/wine-devel: Update 11.1 => 11.2

Changelog:
- More optimizations in PDB loading.
- Support for MSVC constructors in C runtime.
- Easier mechanism for creating version resources.
- Various bug fixes.
https://gitlab.winehq.org/wine/wine/-/releases/wine-11.2

PR:     293040
DeltaFile
+3-3emulators/wine-devel/distinfo
+2-3emulators/wine-devel/pkg-plist
+1-1emulators/wine-devel/Makefile
+6-73 files