LLVM/project fa136dfllvm/lib/Object RelocationResolver.cpp, llvm/test/DebugInfo/AArch64 tls-at-location.ll

[llvm-dwarfdump] Support R_AARCH64_TLS_DTPREL64 in Object/RelocationResolver.cpp (#187649)

In patch https://github.com/llvm/llvm-project/pull/146572 we have plan
to emit R_AARCH64_TLS_DTPREL64. This give us the warning while using
llvm-dwarfdump for the object file which has tls variables -

warning: failed to compute relocation: R_AARCH64_TLS_DTPREL64, Invalid
data was encountered while parsing the file

To fix this warning we have mark the relocation as supported however
final absolute address of a TLS variable is determined at runtime,
resolving to the symbol's section-relative offset in the object file is
mitigate the warning.
DeltaFile
+2-0llvm/lib/Object/RelocationResolver.cpp
+1-1llvm/test/DebugInfo/AArch64/tls-at-location.ll
+3-12 files

LLVM/project 0430ca0clang/test/CodeGenHIP incorrect-atomic-scope.hip, clang/test/CodeGenOpenCL incorrect-atomic-scope.cl

add a builtin that becomes an intrinsic with metadata scope
DeltaFile
+22-3clang/test/CodeGenOpenCL/incorrect-atomic-scope.cl
+18-2clang/test/CodeGenHIP/incorrect-atomic-scope.hip
+40-52 files

LLVM/project b4485bdclang-tools-extra/test/clang-doc enum.cpp, llvm/test/Analysis/CostModel/AMDGPU log.ll log10.ll

Merge branch 'main' into users/cabbaken/03-31-_da_refactor_the_signature_of_the_exact_rdiv_test_nfci_
DeltaFile
+464-226clang-tools-extra/test/clang-doc/enum.cpp
+328-349llvm/test/CodeGen/AMDGPU/fract-match.ll
+380-248llvm/test/Analysis/CostModel/AMDGPU/log.ll
+380-248llvm/test/Analysis/CostModel/AMDGPU/log10.ll
+606-0llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+296-190llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+2,454-1,261680 files not shown
+21,913-6,755686 files

OPNSense/core e78e0c0src/opnsense/scripts/kea/lib kea_ctrl.py

include command here
DeltaFile
+1-1src/opnsense/scripts/kea/lib/kea_ctrl.py
+1-11 files

LLVM/project e07cfeellvm/include/llvm/MC MCAssembler.h, llvm/lib/MC MCAssembler.cpp

Revert "[MC] Fuse relaxation and layout into a single forward pass (#184544)"

This reverts commit debb2514ea7f062a29e5e4740f9d6ee4cea3b978.
DeltaFile
+42-60llvm/lib/MC/MCAssembler.cpp
+0-37llvm/test/MC/X86/align-branch-convergence.s
+8-6llvm/test/MC/ELF/relax-branch-align.s
+1-6llvm/include/llvm/MC/MCAssembler.h
+51-1094 files

LLVM/project 598f353llvm/test/CodeGen/AArch64 sve-mask-partition.ll intrinsic-cttz-elts-sve.ll, llvm/test/CodeGen/PowerPC cttz-elts.ll

[SelectionDAG] Expand CTTZ_ELTS[_ZERO_POISON] and handle legalization (#188691)

This is a second attempt at "[SelectionDAG] Expand
CTTZ_ELTS[_ZERO_POISON] and handle splitting" (#188220)

That PR had to be reverted in 7d39664a6ae8daaf186b65578492244d96a50bf2
because we had crashes on AMDGPU since we didn't have scalarization
support, and other crashes on PowerPC because we didn't handle the case
when a vector needed widened. Tests for these are added in
AMDGPU/cttz-elts.ll, RISCV/rvv/cttz-elts-scalarize.ll and
PowerPC/cttz-elts.ll.

The former crash has been fixed by adding
DAGTypeLegalizer::ScalarizeVecOp_CTTZ_ELTS.

The second crash has been fixed by reworking
TargetLowering::expandCttzElts. The expansion for CTTZ_ELTS is nearly
identical to VECTOR_FIND_LAST_ACTIVE, except it uses a reverse step
vector and subtracts the result from VF. The easiest way to fix these

    [6 lines not shown]
DeltaFile
+412-24llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-elts.ll
+261-0llvm/test/CodeGen/RISCV/rvv/cttz-elts-scalarize.ll
+53-203llvm/test/CodeGen/AArch64/sve-mask-partition.ll
+73-79llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll
+33-98llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
+120-0llvm/test/CodeGen/PowerPC/cttz-elts.ll
+952-40414 files not shown
+1,174-56520 files

OPNSense/core 86132c3src/opnsense/mvc/app/controllers/OPNsense/Kea/Api LeasesController.php, src/opnsense/scripts/kea/lib kea_ctrl.py

improve error handling
DeltaFile
+9-1src/opnsense/mvc/app/controllers/OPNsense/Kea/Api/LeasesController.php
+5-1src/opnsense/scripts/kea/lib/kea_ctrl.py
+14-22 files

LLVM/project 40f53d2clang/test/CIR/CodeGen keep-persistent-storage-variables.cpp keep-static-consts.cpp

add tests persistent-storage-variables and keep-static-consts
DeltaFile
+20-0clang/test/CIR/CodeGen/keep-persistent-storage-variables.cpp
+11-0clang/test/CIR/CodeGen/keep-static-consts.cpp
+31-02 files

LLVM/project 45a12c8llvm/lib/Analysis DependenceAnalysis.cpp

Update
DeltaFile
+3-6llvm/lib/Analysis/DependenceAnalysis.cpp
+3-61 files

LLVM/project 0aa937fllvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU fract-match.ll

AMDGPU: Match fract from compare and select and minimum

Implementing this with any of the minnum variants is overconstraining
for the actual use. Existing patterns use fmin, then have to manually
clamp nan inputs to get nan propagating behavior. It's cleaner to express
this with a nan propagating operation to start with.
DeltaFile
+197-264llvm/test/CodeGen/AMDGPU/fract-match.ll
+124-85llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+321-3492 files

LLVM/project 32ad662llvm/lib/Analysis DependenceAnalysis.cpp

Update
DeltaFile
+2-6llvm/lib/Analysis/DependenceAnalysis.cpp
+2-61 files

LLVM/project f48425ellvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU fract-match.ll

AMDGPU: Match fract pattern with swapped edge case check (#189081)

A fract implementation can equivalently be written as
  r = fmin(x - floor(x))
  r = isnan(x) ? x : r;
  r = isinf(x) ? 0.0 : r;

or:
  r = fmin(x - floor(x));
  r = isinf(x) ? 0.0 : r;
  r = isnan(x) ? x : r;

Previously this only matched the previous form. Match
the case where the isinf check is the inner clamp. There are
a few more ways to write this pattern (e.g., move the clamp of
infinity to the input) but I haven't encountered that in the wild.

The existing code seems to be trying too hard to match noncanonical
variants of the pattern. Only handles the result that all 4 permutations
of compare and select produce out of instcombine.
DeltaFile
+328-349llvm/test/CodeGen/AMDGPU/fract-match.ll
+47-17llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+375-3662 files

FreeNAS/freenas cbf2fdasrc/middlewared/middlewared/plugins tunables.py

Do not HA propagate tunable values by default
DeltaFile
+22-23src/middlewared/middlewared/plugins/tunables.py
+22-231 files

LLVM/project 5b2363a. lib.out tmp.exe, libcxx/test/std/thread/futures/futures.async thread_create_failure.pass.cpp

[libc++][AIX] Fix force_thread_creation_failure by using RLIMIT_THREADS (#188787)

This patch fixes the test `force_thread_creation_failure.cpp` on AIX by
using platform specific `RLIMIT_THREADS` which helps in restricting the
thread creation as `RLIMIT_NPROC` on AIX restricts processes and not
threads.

---------

Co-authored-by: himadhith <himadhith.v at ibm.com>
DeltaFile
+38-0lib.out
+9-7libcxx/test/std/thread/futures/futures.async/thread_create_failure.pass.cpp
+0-0tmp.exe
+47-73 files

NetBSD/pkgsrc ywgjZWQdoc CHANGES-2026

   doc: Updated sysutils/xtop to 0.3.7
VersionDeltaFile
1.2024+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc qMS7zsgsysutils/xtop distinfo cargo-depends.mk

   sysutils/xtop: update to 0.3.7

    - No ChangeLog provided.
VersionDeltaFile
1.5+13-13sysutils/xtop/distinfo
1.5+3-3sysutils/xtop/cargo-depends.mk
1.5+2-2sysutils/xtop/Makefile
+18-183 files

FreeBSD/ports 46d38f9sysutils/vm-bhyve-devel distinfo Makefile

sysutils/vm-bhyve-devel: Update to the latest commit
DeltaFile
+3-3sysutils/vm-bhyve-devel/distinfo
+2-3sysutils/vm-bhyve-devel/Makefile
+5-62 files

FreeBSD/ports 161563dsysutils/vm-bhyve distinfo Makefile

sysutils/vm-bhyve: Update to 1.7.3

Changes:        https://github.com/freebsd/vm-bhyve/releases/tag/v1.7.3
DeltaFile
+3-3sysutils/vm-bhyve/distinfo
+1-1sysutils/vm-bhyve/Makefile
+4-42 files

LLVM/project f918f84clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen CIRGenModule.cpp

add opGlobalPragmaClangSection missing feature
DeltaFile
+4-0clang/test/CIR/CodeGen/global-section.c
+1-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+1-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+1-0clang/include/clang/CIR/MissingFeatures.h
+7-14 files

OpenBSD/ports RWweszJsysutils/terragrunt distinfo modules.inc

   Update to terragrunt-1.0.0.
VersionDeltaFile
1.387+938-1,564sysutils/terragrunt/distinfo
1.105+879-1,140sysutils/terragrunt/modules.inc
1.394+1-1sysutils/terragrunt/Makefile
+1,818-2,7053 files

LLVM/project 035ae02llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[RISCV] Fix discarded return value in RISCVOperand::print for FRM (#189530)

The roundingModeToString() return value was not being written to the
output stream, causing FRM operands to print as "<frm: >" with no
rounding mode name in debug output.

Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
DeltaFile
+1-1llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+1-11 files

OpenBSD/ports v3L4Ubnlang/vala Makefile distinfo

   Update to vala-0.56.19.
VersionDeltaFile
1.186+3-3lang/vala/Makefile
1.147+2-2lang/vala/distinfo
+5-52 files

LLVM/project 2f671faclang/test/CodeGenHIP incorrect-atomic-scope.hip, clang/test/CodeGenOpenCL incorrect-atomic-scope.cl

add an example of scoped atomics
DeltaFile
+9-3clang/test/CodeGenOpenCL/incorrect-atomic-scope.cl
+8-2clang/test/CodeGenHIP/incorrect-atomic-scope.hip
+17-52 files

LLVM/project 8037908clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenModule.cpp

[CIR] Add calling_conv attribute to FuncOp with lowering support
DeltaFile
+38-0clang/test/CIR/IR/calling-conv.cir
+34-0clang/test/CIR/Lowering/calling-conv.cir
+23-5clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+24-1clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+16-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+5-6clang/lib/CIR/CodeGen/CIRGenModule.cpp
+140-133 files not shown
+143-219 files

LLVM/project 7aa5fd5clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR] Add calling convention values to CIR_CallingConv
DeltaFile
+8-3clang/include/clang/CIR/Dialect/IR/CIROps.td
+8-31 files

OpenBSD/src ep7p8n9regress/usr.sbin/rpki-client/openssl unistd.h Makefile, regress/usr.sbin/rpki-client/openssl/build Makefile

   rpki-client regress: align guard with portable
VersionDeltaFile
1.6+2-2regress/usr.sbin/rpki-client/openssl/unistd.h
1.7+2-2regress/usr.sbin/rpki-client/openssl/build/Makefile
1.10+2-2regress/usr.sbin/rpki-client/openssl/Makefile
+6-63 files

FreeBSD/ports 82f4c0bmail/roundcube distinfo Makefile

mail/roundcube: update to 1.6.15 release.
DeltaFile
+3-3mail/roundcube/distinfo
+1-1mail/roundcube/Makefile
+4-42 files

LLVM/project 3d96b36llvm/include/llvm/Target Target.td, llvm/lib/Target/Hexagon HexagonHazardRecognizer.cpp

[Hexagon] Fix infinite loop in scheduler for RELOC_NONE instruction (#188690)

The llvm.reloc.none intrinsic (introduced in 5f08fb4d72f6) causes an
infinite loop when compiling for Hexagon target. The Hexagon scheduler's
hazard recognizer enters an infinite loop because RELOC_NONE

RELOC_NONE is a pseudo-instruction that doesn't correspond to real
hardware, but the Hexagon hazard recognizer was treating it as a regular
instruction requiring hardware resource allocation.

Mark RELOC_NONE as a meta-instruction and update Hexagon's hazard
recognizer to skip resource checks for meta-instructions, similar to how
it handles zero-cost instructions.
DeltaFile
+2-2llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
+1-0llvm/include/llvm/Target/Target.td
+0-1llvm/test/CodeGen/Generic/reloc-none.ll
+3-33 files

HardenedBSD/src 1a006d5share/man/man4 vmgenc.4 Makefile, sys/dev/amdsmu amdsmu.c amdsmu.h

Merge remote-tracking branch 'origin/hardened/current/master' into hardened/current/cross-dso-cfi
DeltaFile
+62-0share/man/man4/vmgenc.4
+12-22sys/dev/amdsmu/amdsmu.c
+15-4sys/dev/amdsmu/amdsmu.h
+4-1sys/dev/amdsmu/amdsmu_reg.h
+1-0share/man/man4/Makefile
+94-275 files

HardenedBSD/src 42efbb3share/man/man4 vmgenc.4 Makefile, sys/dev/amdsmu amdsmu.c amdsmu.h

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+62-0share/man/man4/vmgenc.4
+12-22sys/dev/amdsmu/amdsmu.c
+15-4sys/dev/amdsmu/amdsmu.h
+4-1sys/dev/amdsmu/amdsmu_reg.h
+1-0share/man/man4/Makefile
+94-275 files