LLVM/project 2a51267llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-scalar-scc-clobber.mir

[AMDGPU] Fix s_cselect scc clobber issue (#193498)

The frame index elimination e.g., for S_CSELECT_B32 (which reads SCC)
uses the SCC-preserving S_ADDC_U32+S_BITCMP1_B32+S_BITSET0_B32 sequence
instead of a plain S_ADD_I32, even when the regscavenger reports SCC as
unused due to its backward scan removing the SCC def from the live set.

Root cause: scavengeRegisterBackwards scans backward from MI and calls
LiveRegUnits::stepBackward() on each instruction. stepBackward removes
defs from the live set. When it processes the S_AND_B64 (which defines
SCC) immediately before S_CSELECT_B32, SCC is removed from LiveUnits.
This makes RS->isRegUsed(SCC) return false, so NeedSaveSCC was false
before the fix.

The fix adds MI->readsRegister(SCC) to the NeedSaveSCC condition so the
SCC-preserving ADDC+BITCMP1+BITSET0 sequence is always used when MI
reads SCC, regardless of what the regscavenger reports.

- commit message and the test are generated by claude
DeltaFile
+114-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
+3-2llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+117-22 files

FreeNAS/freenas 4b8143asrc/middlewared/middlewared/api/v26_0_0 truenas.py

NAS-140763 / 27.0.0-BETA.1 / Fix 26.0.0 license API (#18792)
DeltaFile
+11-2src/middlewared/middlewared/api/v26_0_0/truenas.py
+11-21 files

LLVM/project 49dad16flang/include/flang/Support LangOptions.def, flang/lib/Frontend CompilerInvocation.cpp

[flang] Ignore -fno-realloc-lhs for polymorphic allocatable LHS with warning (#192697)

When -fno-realloc-lhs is specified and the LHS of an assignment is a
polymorphic allocatable (class(*) or class(T)), reallocation semantics
are required by the Fortran 2003 standard for dynamic type tracking and
cannot be safely skipped. Previously, the compiler generated invalid FIR
in such cases (type mismatch between i32 and
!fir.class<!fir.heap<none>>), causing a compilation error.

With this change, when -fno-realloc-lhs is in effect and a polymorphic
allocatable LHS is detected, the compiler emits a warning that the
option is being ignored for that assignment and proceeds with
reallocation semantics.
DeltaFile
+26-0flang/test/Semantics/no-realloc-lhs-poly.f90
+13-5flang/lib/Lower/Bridge.cpp
+15-1flang/test/Lower/reallocate-lhs.f90
+4-0flang/include/flang/Support/LangOptions.def
+3-1flang/lib/Frontend/CompilerInvocation.cpp
+3-0flang/lib/Semantics/expression.cpp
+64-72 files not shown
+67-88 files

LLVM/project 0d6652allvm/utils/lit/tests progress-bar.py

[lit] Fix `progress-bar.py` flaky test

The `lit` progress-bar test was checking for exact progress-bar text
like `0.. 10.. 20.. 30.. 40..`, but that output is not stable from run
to run.

The progress bar is based on timing estimates, including saved timings
from earlier runs, so small timing differences can change which numbers
get printed.

That made the test flaky: FileCheck could match the wrong Testing: line
and then fail later, even though the actual test failures were correct.

Relax the test to verify ordering instead of exact progress-bar
contents. The updated checks assert that the test header is printed, that
each failing test result is separated by a Testing: progress-bar line,
and that the final failed-tests summary lists all expected tests in order.

This preserves coverage for the simple progress-bar path while removing

    [3 lines not shown]
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+16-9llvm/utils/lit/tests/progress-bar.py
+16-91 files

FreeNAS/freenas 22dac9csrc/middlewared/middlewared/api/v26_0_0 truenas.py

Fix 26.0.0 license API
DeltaFile
+11-2src/middlewared/middlewared/api/v26_0_0/truenas.py
+11-21 files

LLVM/project 41d05aellvm/utils/lit/lit TestRunner.py InprocBuiltins.py

Revert "[Lit][NFC] Refactor shell environment functionality and in-process builtins from TestRunner.py into new modules (Reopened)" (#193740)

Reverts llvm/llvm-project#177358

Bot failure: https://lab.llvm.org/buildbot/#/builders/181/builds/41934
DeltaFile
+577-34llvm/utils/lit/lit/TestRunner.py
+0-315llvm/utils/lit/lit/InprocBuiltins.py
+0-271llvm/utils/lit/lit/ShellEnvironment.py
+577-6203 files

LLVM/project ac59400llvm/utils/lit/lit TestRunner.py InprocBuiltins.py

Revert "[Lit][NFC] Refactor shell environment functionality and in-process bu…"

This reverts commit 9b986d49d6ca963bc22f265ce4045affbde427b4.
DeltaFile
+577-34llvm/utils/lit/lit/TestRunner.py
+0-315llvm/utils/lit/lit/InprocBuiltins.py
+0-271llvm/utils/lit/lit/ShellEnvironment.py
+577-6203 files

FreeNAS/freenas 0a487a6src/middlewared/middlewared/plugins/truenas license.py

Fix
DeltaFile
+1-1src/middlewared/middlewared/plugins/truenas/license.py
+1-11 files

FreeNAS/freenas 7c7659bsrc/middlewared/middlewared/api/v26_0_0 truenas.py

Fix 26.0.0 license API
DeltaFile
+11-2src/middlewared/middlewared/api/v26_0_0/truenas.py
+11-21 files

OPNSense/core b4d33d1src/opnsense/scripts/kea kea_prefix_watcher.py

No we still have do add state into the mix or the route lazy drop will not work anymore
DeltaFile
+2-1src/opnsense/scripts/kea/kea_prefix_watcher.py
+2-11 files

LLVM/project e5839ddllvm/test/CodeGen/AArch64 neon-matmul-f16.ll aarch64-matmul-f16f32mm.ll

fixup! Rename files to be more logical
DeltaFile
+15-0llvm/test/CodeGen/AArch64/neon-matmul-f16.ll
+0-15llvm/test/CodeGen/AArch64/aarch64-matmul-f16f32mm.ll
+0-15llvm/test/CodeGen/AArch64/aarch64-matmul-f16mm.ll
+15-0llvm/test/CodeGen/AArch64/neon-matmul-f16f32mm.ll
+0-14llvm/test/CodeGen/AArch64/sve-fmmla-f16.ll
+14-0llvm/test/CodeGen/AArch64/sve-intrinsics-matmul-bf16.ll
+44-442 files not shown
+58-588 files

LLVM/project e50528aclang/include/clang/Basic arm_neon.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup! Address Kerry's PR comments
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+1-3clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
+2-2clang/include/clang/Basic/arm_neon.td
+1-2clang/utils/TableGen/NeonEmitter.cpp
+1-1clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
+0-2clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1-1clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
+6-112 files not shown
+6-158 files

OPNSense/core c049664src/opnsense/scripts/filter/lib/alias __init__.py bgpasn.py

Firewall: Aliases - fix typo in error log (remove url as it has no value anyway) and make parser a bit more resilient by trapping all errors. closes https://github.com/opnsense/core/issues/10168

(cherry picked from commit 5b6913a0df45577f31a6a7777702cf876897c79e)
(cherry picked from commit 4e939d528cc7d4e38c1bfe777b71e1772fcc6edc)
DeltaFile
+3-2src/opnsense/scripts/filter/lib/alias/__init__.py
+1-1src/opnsense/scripts/filter/lib/alias/bgpasn.py
+4-32 files

OPNSense/core 4e939d5src/opnsense/scripts/filter/lib/alias bgpasn.py

firewall: small whitespace issue in prev
DeltaFile
+0-1src/opnsense/scripts/filter/lib/alias/bgpasn.py
+0-11 files

OPNSense/core f251331src/opnsense/scripts/kea kea_prefix_watcher.py

Remove duplicate state check, add documentation for the possible states
DeltaFile
+4-3src/opnsense/scripts/kea/kea_prefix_watcher.py
+4-31 files

LLVM/project 9b986d4llvm/utils/lit/lit TestRunner.py InprocBuiltins.py

[Lit][NFC] Refactor shell environment functionality and in-process builtins from TestRunner.py into new modules (Reopened) (#177358)

This is a fresh PR for https://github.com/llvm/llvm-project/pull/176761,
reopening after my rebasing error.

Original description:
This is the first in a series of PRs reworking Lit's handling of
in-process builtins to be run as part of command pipelines, and to
enable users to provide new in-process builtins via Lit's configuration.
The full series of patches can be found here:
https://github.com/BStott6/llvm-project/tree/lit-inproc-builtins.

This work is required for the test daemonization project:
https://discourse.llvm.org/t//88612/9


This PR moves the shell environment functionality and existing
in-process builtins from TestRunner.py into new modules. This is
important not just for organizational purposes but also because,

    [2 lines not shown]
DeltaFile
+34-577llvm/utils/lit/lit/TestRunner.py
+315-0llvm/utils/lit/lit/InprocBuiltins.py
+271-0llvm/utils/lit/lit/ShellEnvironment.py
+620-5773 files

LLVM/project 1ee288allvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV atomicrmw-storage-class-semantics.ll atomicrmw.ll

[SPIR-V] Combine storage class bit with atomic memory semantics (#193696)

Per SPIR-V spec section 3.32 (Memory Semantics), atomic operations must
combine the ordering bits
(Acquire/Release/AcquireRelease/SequentiallyConsistent) with the
relevant storage class bit (UniformMemory, WorkgroupMemory,
CrossWorkgroupMemory, ...)
DeltaFile
+58-0llvm/test/CodeGen/SPIRV/atomicrmw-storage-class-semantics.ll
+7-6llvm/test/CodeGen/SPIRV/atomicrmw.ll
+5-6llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomic_int16_load_store_xchg_cmpxchg.ll
+8-2llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+4-5llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+4-5llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_16bit_atomics/atomic_bfloat16_load_store_xchg.ll
+86-2414 files not shown
+115-4720 files

FreeNAS/freenas 3190e88src/middlewared/middlewared/plugins/failover_ configure.py, src/middlewared/middlewared/plugins/system product.py product_utils.py

NAS-140416 / 27.0.0-BETA.1 / add truenas.license API (#18559)

It introduces a new **`truenas.license`** API namespace, backed by a new
license daemon (`truenas_pylicensed`), while keeping backward
compatibility with old-format ("legacy") licenses already installed on
systems in the field.

---

New licenses are now PEM-wrapped files managed by a background daemon
(`truenas_pylicensed`). The file lives at
`/data/subsystems/truenas_license/license` (previously `/data/license`).

---

Systems with an old-style license at `/data/license` continue to work
without any migration step.

**When the legacy path activates**: `truenas.license.info_private` first

    [31 lines not shown]
DeltaFile
+212-0src/middlewared/middlewared/plugins/truenas/license_utils.py
+70-60src/middlewared/middlewared/plugins/system/product.py
+102-0src/middlewared/middlewared/plugins/truenas/license.py
+80-0src/middlewared/middlewared/plugins/truenas/license_legacy_utils.py
+0-60src/middlewared/middlewared/plugins/failover_/configure.py
+0-58src/middlewared/middlewared/plugins/system/product_utils.py
+464-17829 files not shown
+665-31435 files

LLVM/project 6563ec7llvm/lib/Target/AMDGPU AMDGPUMCResourceInfo.cpp

[NFC][AMDGPU] Make code consistent in MCResourceInfo::gatherResourceInfo

Some of the enums have the type name but some don't.
DeltaFile
+5-6llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
+5-61 files

OPNSense/core 5452c5bsrc/opnsense/mvc/app/models/OPNsense/Base/Menu MenuItem.php

system: minor style update in new menu code
DeltaFile
+5-6src/opnsense/mvc/app/models/OPNsense/Base/Menu/MenuItem.php
+5-61 files

LLVM/project 486f116llvm/test/CodeGen/LoongArch/lsx/ir-instruction fptrunc.ll

update tests
DeltaFile
+8-4llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll
+8-41 files

OPNSense/core 8c6b3e0. plist, src/opnsense/scripts/firmware/repos FreeBSD.php OPNsense.php

firmware: moved FreeBSD.php duty to opnsense-update

PR: https://github.com/opnsense/update/commit/aeb88a8fb9
(cherry picked from commit 0175c1e1f0a263fc2ef640f485a60f45d5448b7d)
DeltaFile
+0-33src/opnsense/scripts/firmware/repos/FreeBSD.php
+3-2src/opnsense/scripts/firmware/repos/OPNsense.php
+0-1plist
+3-363 files

FreeNAS/freenas 6aed29fsrc/middlewared/middlewared/plugins/failover_ configure.py, src/middlewared/middlewared/plugins/system product.py product_utils.py

NAS-140416 / 27.0.0-BETA.1 / add truenas.license API (#18559)

It introduces a new **`truenas.license`** API namespace, backed by a new
license daemon (`truenas_pylicensed`), while keeping backward
compatibility with old-format ("legacy") licenses already installed on
systems in the field.

---

New licenses are now PEM-wrapped files managed by a background daemon
(`truenas_pylicensed`). The file lives at
`/data/subsystems/truenas_license/license` (previously `/data/license`).

---

Systems with an old-style license at `/data/license` continue to work
without any migration step.

**When the legacy path activates**: `truenas.license.info_private` first

    [31 lines not shown]
DeltaFile
+212-0src/middlewared/middlewared/plugins/truenas/license_utils.py
+70-60src/middlewared/middlewared/plugins/system/product.py
+102-0src/middlewared/middlewared/plugins/truenas/license.py
+80-0src/middlewared/middlewared/plugins/truenas/license_legacy_utils.py
+0-60src/middlewared/middlewared/plugins/failover_/configure.py
+0-58src/middlewared/middlewared/plugins/system/product_utils.py
+464-17827 files not shown
+659-30433 files

NetBSD/pkgsrc ml0xDrpdoc CHANGES-2026 TODO

   doc: Updated textproc/rumdl to 0.1.80
VersionDeltaFile
1.2545+2-1doc/CHANGES-2026
1.27152+1-2doc/TODO
+3-32 files

LLVM/project 5a9d0cfllvm/lib/Target/PowerPC PPCOperands.td PPCInstrFuture.td, llvm/lib/Target/PowerPC/AsmParser PPCAsmParser.cpp

[PowerPC] Add mnemonics to paddis (#179979)

Add extended mnemonics to paddis:
```
  paddis RT,RA,SI  -> paddis RT,RA,SI,0
  plis RT,SI       -> paddis RT,0,SI,0
  psubis RT,RA,si  -> paddis RT,RA,-si,0
```

Assisted by AI.
DeltaFile
+67-33llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+98-0llvm/test/MC/PowerPC/ppc64-psubis.s
+30-0llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+18-0llvm/lib/Target/PowerPC/PPCOperands.td
+13-0llvm/lib/Target/PowerPC/PPCInstrFuture.td
+11-0llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+237-333 files not shown
+241-359 files

NetBSD/pkgsrc Oh5IxWxtextproc/rumdl distinfo cargo-depends.mk

   textproc/rumdl: update to 0.1.80

   72## [0.1.80](https://github.com/rvben/rumdl/compare/v0.1.79...v0.1.80) - 2026-04-22

   ### Added

   - **wasm**: validate rule-config value types at parse time ([ab3d3d5](https://github.com/rvben/rumdl/commit/ab3d3d547eb58ac093f52a5678b65d59e6602541))
   - **wasm**: honor exclude patterns via path-aware check() and fix() ([e578308](https://github.com/rvben/rumdl/commit/e578308978f04e582acedf014ff75b4890ceca44))

   ## [0.1.79](https://github.com/rvben/rumdl/compare/v0.1.78...v0.1.79) - 2026-04-22

   ### Fixed

   - **md051**: strip HTML comments from heading anchors ([e4e3c4b](https://github.com/rvben/rumdl/commit/e4e3c4b79126b7d8a90357edcba044ed7d473404))
   - **md077**: accept task-item post-checkbox column to break MD013 reflow cycle ([1c3cbef](https://github.com/rvben/rumdl/commit/1c3cbef4cb2a5e0c9ff9c810c5012018f9ee3e18))
   - **lint-context**: honor CommonMark Type-1 HTML blocks ([6f37e49](https://github.com/rvben/rumdl/commit/6f37e49cf9f54bf56c20bb88309cf7e9a052946a))

   ## [0.1.78](https://github.com/rvben/rumdl/compare/v0.1.77...v0.1.78) - 2026-04-21


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1.21+202-199textproc/rumdl/distinfo
1.10+66-65textproc/rumdl/cargo-depends.mk
1.23+2-2textproc/rumdl/Makefile
+270-2663 files

OPNSense/core 400dc45src/opnsense/mvc/app/models/OPNsense/Kea KeaDhcpv4.xml KeaDhcpv6.xml

Services: Kea DHCPv4/v6: Remove depend constraint of ddns_reverse_zone (#10182)

Since ddns_forward_zone already depends on ddns_dns_server, and the config generator bails if either of these are empty we do not need to protect ddns_reverse_zone in any specific way right now.

It's a good idea to keep it this way, only populating a reverse zone is very uncommon, and ISC also tethered it to the forward zone being there.

(cherry picked from commit 4a1d6cf0851940f352f6d414240792c9f66be91a)
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+0-9src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv4.xml
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+0-182 files

NetBSD/pkgsrc 2HC3D7Edoc CHANGES-2026

   doc: Updated net/xfr to 0.9.10
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1.2544+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc 64wdscanet/xfr distinfo Makefile

   net/xfr: update to 0.9.10

   v0.9.10
   Fixed

       TCP teardown no longer hangs under rate-limited paths (#54) — the v0.9.8 SO_LINGER=0 fix didn't take effect when the send loop was parked in stream.write().await under heavy backpressure (tc rate limiting, slow peers, MPTCP subflows filling). send_data and send_data_half now race the pending write() against cancel and deadline in a biased tokio::select!, so either signal breaks the loop and lets SO_LINGER=0 do its job. Confirmed by @matttbe against his MPTCP + tc reproducer.
       TUI elapsed time stays live during data gaps (#62) — app.elapsed was only updated when the server's Interval progress message arrived. On lossy paths that starved the control channel, the elapsed counter could freeze for several seconds, creating the impression of a "stall" even though the TUI was still redrawing at 20 Hz. The loop now refreshes elapsed from the wall clock every iteration. Pause handling shifts start_time forward by the paused duration on resume, so the counter excludes paused time. Reported by @brettowe.
       Infinite-duration (-t 0) TUI now shows a live elapsed counter — same fix covers this.

   Added

       Client/server version in the Configuration panel (#62) — the TUI now shows xfr/<client> ↔ <server> so cross-version test pairings are obvious at a glance.

   Changed

       TUI jitter line shows latest + smoothed together (#48 follow-up) — running display now reads Jitter: 0.02 ms (10s: 0.03 ms) so the instantaneous per-interval value and the 10-second rolling mean are side-by-side. Resolves the confusion where the rolling mean could stay above any single sample's value, making the live display look inconsistent with the final. Completed state still shows just the authoritative final.

   Security


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OPNSense/core c82e874src/opnsense/mvc/app/controllers/OPNsense/Routing/Api SettingsController.php

system: small note on legacy bindings
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+1-01 files