18575 Add 400GBASE-CR8 and 400GBASE-SR8 to Ethernet media types
Reviewed by: Robert Mustacchi <rm at fingolfin.org>
Approved by: Dan McDonald <danmcd at oxide.computer>
[lldb] Follow register moves when detecting saved registers (#225229)
[lldb] Follow register moves when detecting saved registers
Commit 5f23b5e14752 implements following outlined functions in the
unwind
assembly scanner. However, it incorrectly ignores a link register push
in the
following pseudo assembly:
move link register to x2 // ignored by the scanner
branch and link to OUTLINED_FUNCTION // clobbers link register
move x2 to link register // ignored by the scanner
push link register to stack // scanner should record this, but doesn't
On the pseudo-assembly above, the scanner records the write to lr in the
bl instruction,
and in the push instruction concludes that lr's contents must refer
to a local variable, not the parent's return address, and should be
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[lldb][Fortran] Addressed feedback about code styling and changed one of the tests to contain different types in arguments and return type, not just integers
[lldb][Fortran] Added llvm RTTI support to FortranFunction, renamed variable names in functions, GetFunctionType static function to get function type pointer and addressed feedback about code style
[DAG] Handle splitting in get_active_lane_mask expansion (#234488)
Split when the type is legal, e.g. v64i1, but the step vector needed for
expansion needs split, e.g. v64i8.
This can happen on avx512 when the 512 bit registers are disabled.
[Analysis] Remove unused CodeMetrics::exposesReturnsTwice (NFC) (#234845)
The last use of CodeMetrics::exposesReturnsTwice was removed on January
21, 2013 in commit bb9caa9241d3653185a0b510e4e02e2fa93e9f14.
Assisted-by: Antigravity
[lldb] Move Itanium and MSVC demangling into C++ language plugin (#232922)
Currently Mangled demangles Itanium and MSVC names itself, and other
language plugins have no way to demangle the names of their own
schemes.
This patch adds Language::DemangleSymbol() and moves the Itanium and
MSVC demangling code, unchanged, into CPlusPlusLanguage. Since Mangled
now looks up the C++ plugin for every name it demangles,
FindPluginForManglingScheme() caches the plugins it finds.
Assisted-by: Claude
Depends on https://github.com/llvm/llvm-project/pull/232921
[ADT] Add SmallVector(Size, for_overwrite) (#234861)
`SmallVector<T, 0> V(N, for_overwrite)` creates N default-initialized
elements. Trivial types such as integers and pointers are left
uninitialized, skipping the zero-fill done by `SmallVector(N)`. Use it
when every element is written before it is read, e.g. a buffer filled
by index:
```
SmallVector<uint64_t, 0> Keys(N, for_overwrite);
parallelFor(0, N, [&](size_t I) { Keys[I] = ...; });
```
LLM-aided
[Clang][RISCV][P-ext] Add Packed Widening Multiply Accumulate intrinsics (#226505)
Add intrinsics, Clang builtins and SelectionDAG support for the packed
widening multiply-accumulate operations.
See
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-widening-multiply-accumulate.
On RV32, the pwmacc.h family accumulates into the register pair holding
rd.
On RV64, the operations are lowered according to the spec decomposition
table, using zip16p and the pmacc.w.h01/pmaccu.w.h01 forms, or pwcvtu.wh
followed by pmaccsu.w.h00 for the signed-unsigned form.
[SLP]Keep fma lanes fused in copyable fmuladd bundles
Copyable modeling picked fmuladd as the main op while fma lanes still
matched it, so the vector node was emitted as fmuladd. Use an fma lane
as the main op and model the copyable lanes with fma identities.
Fixes #234924
Assisted-by: Cursor
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/235017
CodeGen: Stop adding kill flags in target MachineCombiner sequences (#234966)
Continue purging kill flag introduction from SSA passes.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Index defs by direct superclass for getAllDerivedDefinitions (#234952)
getAllDerivedDefinitions visited every def to find those derived from
the requested class. The results are cached per class, but adding a def
clears the cache, so each !instances during parsing scans again.
Generating the RISC-V DAG instruction selector scans all 260,000 defs 26
times.
Record each def under its direct superclasses when it is added, and have
a query test those superclasses instead of every def. A def with several
matching superclasses is found more than once, so remove the duplicates
after sorting.
RISCVGenDAGISel.inc tablegen run:
Gigainstructions Gigacycles CPU seconds
Before 61.4 33.8 10.5
After 60.9 (-0.8%) 31.7 (-6.0%) 9.9 (-5.8%)
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x11/xauth: Drop py-cmdtest from TEST_DEPENDS
xauth's "make check" runs tests/test_xauth, a plain sh driver "modelled
after cmdtest" that runs the *.script files and diffs their output; it
never calls cmdtest, so the dependency is not needed.
While here, fix portlint warnings.
PR: 299772
[lldb] Move parsing of mangled names into C++ language plugin (#232921)
Currently Symtab::InitNameIndexes() parses Itanium and MSVC names
itself, so a language plugin can't add its functions to the basename and
method indexes without patching Symtab.
This patch moves that parsing, along with
Mangled::GetRichManglingInfo(), into CPlusPlusLanguage using a new
Language::MangledNameParser interface. A parser reports a function's
basename, its context, and what the mangling says about that context.
Symtab still decides which index the name goes into, and still infers
which C++ contexts are classes from their constructors and destructors.
Assisted-by: Claude
[VPlan] Move extract-lane(0, canWideIV) combine before unrolling
Some extract-lane combines can't be performed before unrolling, e.g. the one that combines it to Instruction::ExtractElement can end up extracting from a different part. But the extract-lane(0, canWideIV) can because at index 0 you're always extracting from the first part. Do this before unrolling, which improves codegen of unrolled code.
[VPlan] Support interleaving early exit loops with side effects
We couldn't do this on main previously because the exit mask `active-lane-mask(0, FirstActiveLane(Cond))` doesn't get unrolled properly across parts. Now that we use mask.beforefirst we can unroll it properly in a chain. The unrolled form is:
unroll(mask.beforefirst, P) = mask.beforefirst(cond[P] | broadcast(anyof(not(unroll(mask.beforefirst, P-1)))))
On AArch64 this can be combined to brkpb in another patch.
