[MSP430] Declare command line options in TableGen (#234455)
Move the cl::opts into MSP430Options.td. MSP430TargetMachine holds
`const MSP430Options &CLOpts`, and MSP430Subtarget and
MSP430TargetLowering copy it.
MSP430Subtarget::HWMultEnum becomes `enum class MSP430::HWMult`.
-mhwmult is renamed to -msp430-hwmult, with the old spelling kept as an
alias.
LLM-aided
[DirectX][SPIRV] Add ImmArg to constant intrinsics arguments (#232470)
Adds `ImmArg` annotations to intrinsic arguments that should always be
constant.
For DirectX this applies to:
- `dx_thread_id`, `dx_group_id`, `dx_thread_id_in_group` - the index
argument
- `int_dx_resource_atomic_binop` - the binary op code argument
- `dx_resource_updatecounter` - the increment/decrement value argument
- `dx_resource_gather`, `dx_resource_gather_cmp` - the component
argument
- `dx_barrier_by_memory_type`, `int_dx_barrier_by_memory_handle` - flags
arguments
- `dx_load_input`, `dx_store_input` - signature element ID and row/col
indices
For SPIRV this applies to:
- `spv_resource_updatecounter` - the increment/decrement value argument
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[LFI][libunwind] Enable x86_64_lfi for compiler-rt and skip reserved registers in libunwind (#232552)
This enables `x86_64_lfi` as a CMake target in compiler-rt and skips
LFI's reserved registers for libunwind's save/restore sequence.
security/wazuh*: update to 4.14.9
- Update cpython bundle to 3.11.17
- Remove obsolete patch file
- Use PYTHON_DISTVERSION for avoid temporarily pkg-plist issues when
system python is updated. The best is keep system python and bundle
python with the same version.
ChangeLog at: https://documentation.wazuh.com/current/release-notes/release-4-14-9.html
PR: 299490
Switch the default compiler from gcc80 to gcc120 (2)
Missed the WORLD_ALTCOMPILER update in the previous default compiler
switch commit f832cd76a838d30fcf0743178ef47129113ff095. That caused the
nrelease failure in the package building phase (see below), because it
still uses CCVER=gcc80 but gcc80 was unavailable due to
WORLD_ALTCOMPILER not being updated.
```
===> Configuring for pkg-2.2.0
No installed jimsh or tclsh, building local bootstrap jimsh0
Host System...x86_64-unknown-dragonfly6.5
Build System...x86_64-unknown-dragonfly6.5
C compiler... cc -pipe -Wno-error -I/usr/include/priv -O2 -fno-strict-aliasing
C++ compiler... c++ -pipe -Wno-error -I/usr/include/priv -O2 -fno-strict-aliasing
Build C compiler...cc
Checking for stdlib.h...not found
Error: Compiler does not work. See config.log
Try: 'configure --help' for options
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[KnownFPClass] Use a dedicated routine for handling fmuladd/G_FMAD (#234038)
Fixes https://github.com/llvm/llvm-project/issues/229170
Treating `fmuladd` as `fma` has no bugs currently, but this guards
against future bugs such as `fmuladd(pnorm, nnorm, pzero)` ruling out
positive zero (which is valid for `fma(x, y, z)`, but not `fadd(fmul(x,
y), z)`).
AI Disclosure:
I used Claude Opus 5 to help write the tests.
[SystemZ, Clang] Enable verification of int args extensions. (#223755)
The verification that was previously enabled only with the -argext-abi-check CL
option is now enabled for clang by default (in an assertions build).
If you have run into any build problem and are looking at this commit, it means
you are building with clang and unfortunately found an issue that has not been
handled yet.
Handling the problem means adding the right extension attribute to the
call/ret IR instruction where it is missing. This is one of SExt/ZExt(/NoExt)
as given by the signedness of the int argument (or NoExt for struct in reg).
To disable this temporarily pass -argext-abi-check=false to clang.
The verification itself has been refined somewhat to strictly require an
extension attribute only in the case of a non-internal C-ABI Call/Function.
In the other cases, such as with internal functions, the attributes are checked
to match those found in the Function header.
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[NVPTX] Cleanup support for atomic loads/stores (#201468)
- Adds exhaustive python-scripted testing for codegen for loads and
stores in NVPTX, for all valid combinations of datatype x ordering x
scope x addrspace x volatility, in the style of atomicrmw/cmpxchg/fence.
- Migrates the emulation of seq_cst loads to AtomicExpandPass using
bracketInstructionWithFences. For this, updates AtomicExpandPass to set
load/store ordering after a fence split. Cleans up associated helper
functions.
- Emulates formerly-unsupported atomic loads and stores using fences in
AtomicExpandPass. This leads to all possible memory orders being
emulated even for SM60, using membar as a fence.
- Relaxes the lowering of seq_cst stores to fence.sc; st.relaxed instead
of fence.sc; st.release.
- Updates NVPTXAtomicLower to downgrade atomic local loads/stores to
nonatomic, in a fashion similar to atomicrmw.
- Note that volatile loads are currently being lowered incorrectly- will
be fixed in a followup PR.
[X86] Combine mask_beforefirst to (x - 1) & ~x in GPR
EVEX and libc use this pattern in strcpy etc. to set the bits before the lowest set bit. It works correctly for x=0 too, returning an all ones mask.
Because SSE/AVX/AVX2 promote vNi1 types, do this as a DAG combine before type legalization.
We need to restrict it to power of 2 types otherwise we hit a latent crash in combineToExtendBoolVectorInReg.
[VPlan] Use llvm.mask.beforefirst for computing early exit mask
This makes the cost more accurate and improves codegen for RISC-V. The codegen for an early exit loop with side effects then goes from:
.LBB0_3: # %vector.body
# =>This Inner Loop Header: Depth=1
vl1r.v v16, (a3)
vsetvli zero, zero, e8, m1, ta, ma
vmseq.vi v16, v16, 0
vfirst.m a7, v16
srli t0, a7, 63
czero.nez a7, a7, t0
czero.eqz t0, a1, t0
or a7, t0, a7
vsetvli zero, zero, e64, m8, ta, ma
vmsltu.vx v0, v8, a7
vle8.v v17, (a5), v0.t
vcpop.m t1, v16
vsetvli zero, zero, e8, m1, ta, ma
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[CSKY] Declare command line options in TableGen (#234452)
Move the cl::opts of CSKYDesc and CSKYAsmParser into
MCTargetDesc/CSKYMCOptions.td, registered by
LLVMInitializeCSKYTargetMC(). CSKYAsmParser, CSKYInstPrinter, and
CSKYAsmPrinter hold `const CSKYMCOptions &CLOpts`; the static
CSKYInstPrinter::getRegisterName takes it as a parameter.
`-M no-aliases` now clears MCInstPrinter::PrintAliases, and `-M numeric`
sets a file-static flag, instead of writing the cl::opts.
-enable-csky-asm-compressed-inst is renamed to
-csky-asm-compressed-inst, with the old spelling kept as an alias.
When unveil was used with a chroot environment it was possible for
unveil_find_cover to loop forever because it was missing a check for the
rootvnode. This would only happen if references existed to directories
outside the chroot, which correct chroot code must not do.
ok deraadt
lang/php74: Apply changes from PHP-7.4-CVE-2026-109618-109619
Apply changes from tagged as PHP-7.4-CVE-2026-109618-109619 from GitHub.
Quote from security advisory announce on https://www.php.net:
Given the severity of these vulnerabilities, the PHP security team
provided minimal source-backports for PHP 7.4, PHP 8.0, and PHP 8.1 to
help people building from source or without access to an LTS vendor.
Bump PKGREVISION.
[X86] Combine mask_beforefirst to (x - 1) & ~x in GPR
EVEX and libc use this pattern in strcpy etc. to set the bits before the lowest set bit. It works correctly for x=0 too, returning an all ones mask.
Because SSE/AVX/AVX2 promote vNi1 types, do this as a DAG combine before type legalization.
We need to restrict it to power of 2 types otherwise we hit a latent crash in combineToExtendBoolVectorInReg.
[VPlan] Use llvm.mask.beforefirst for computing early exit mask
This makes the cost more accurate and improves codegen for RISC-V. The codegen for an early exit loop with side effects then goes from:
.LBB0_3: # %vector.body
# =>This Inner Loop Header: Depth=1
vl1r.v v16, (a3)
vsetvli zero, zero, e8, m1, ta, ma
vmseq.vi v16, v16, 0
vfirst.m a7, v16
srli t0, a7, 63
czero.nez a7, a7, t0
czero.eqz t0, a1, t0
or a7, t0, a7
vsetvli zero, zero, e64, m8, ta, ma
vmsltu.vx v0, v8, a7
vle8.v v17, (a5), v0.t
vcpop.m t1, v16
vsetvli zero, zero, e8, m1, ta, ma
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