LLVM/project 8445ad1 — libcxx/test/benchmarks/numeric reduce.bench.cpp

[libc++] Added a benchmark for std::reduce with a trivial reduction operator (std::plus) (#236853)

This PR adds benchmarks for serial reductions with a trivial operator,
to specifically capture the cases where the compiler can do a good job
optimising the loop. This includes cases where the compiler can already
perform reordering without an explicit permission (e.g. with `int`s) and
where it requires an opt-int like `clang loop vectorize(enable)
interleave(enable)` (e.g. with `float`s, which libc++ currently doesn't
do).

Part of #234887.
DeltaFile
+35-1libcxx/test/benchmarks/numeric/reduce.bench.cpp
+35-11 files

FreeBSD/ports 1bbcfe5 — devel/subversion Makefile Makefile.common, devel/subversion-lts Makefile Makefile.common

devel/subversion{,-lts}: make apr_memcache opt-out explicit

configure otherwise silently autodetects a standalone apr_memcache installation
on the build host for fs_fs caching (server-side only FSFS repository caching);
this was never actually supported. Pass --without-apr_memcache explicitly
instead of leaving it to autodetection.

Co-Authored-By: Claude Sonnet 5 <noreply at anthropic.com>
DeltaFile
+2-1devel/subversion/Makefile.common
+2-1devel/subversion-lts/Makefile.common
+1-1devel/subversion/Makefile
+1-1devel/subversion-lts/Makefile
+6-44 files

LLVM/project 0bf17f8 — lldb/unittests/SymbolFile/DWARF DWARFDIETest.cpp

[lldb] Test that unterminated DW_FORM_strp names are rejected (#237354)

c38a7054a1d8 bounded DataExtractor::PeekCStr and converted
DWARFFormValue::AsCString, but only tested the DataExtractor and Mach-O
paths. Add a DWARF test so AsCString can't regress to returning a
pointer into a .debug_str string with no terminator.
DeltaFile
+53-0lldb/unittests/SymbolFile/DWARF/DWARFDIETest.cpp
+53-01 files

LLVM/project ae8f591 — llvm/include/llvm/IR RuntimeLibcalls.td RuntimeLibcallsImpl.td, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Use explicit types for F80, F128 and PPCF128 libcalls (#235145)

LDbl only makes sense for encoding the long double libm functions. Other
functions have need of the specific type. Separately, LDbl brokenly
assumes
double instead of checking the module's long double format. Some
functions
are inappropriately using a specific type instead of LDbl. I'll fix both
of these issues separately.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+96-96llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ppc.ll
+39-39llvm/test/Transforms/Util/DeclareRuntimeLibcalls/windows.ll
+39-39llvm/test/Transforms/Util/DeclareRuntimeLibcalls/bsd.ll
+8-0llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+3-3llvm/include/llvm/IR/RuntimeLibcalls.td
+6-0llvm/lib/IR/RuntimeLibcalls.cpp
+191-1771 files not shown
+194-1777 files

LLVM/project fcc84ae — llvm/test/tools/llubi icmp_ptr_non_address_bits.ll, llvm/tools/llubi/lib Interpreter.cpp

[llubi] Ignore non-address bits when comparing pointers (#237330)

Closes https://github.com/llvm/llvm-project/issues/233678.
DeltaFile
+19-0llvm/test/tools/llubi/icmp_ptr_non_address_bits.ll
+9-4llvm/tools/llubi/lib/Interpreter.cpp
+28-42 files

LLVM/project bd51cc5 — llvm/lib/CodeGen RegAllocBase.cpp RegAllocBasic.cpp, llvm/test/CodeGen/AMDGPU sgpr-regalloc-flags.ll llc-pipeline.ll

[CodeGen] Use shared RegClassInfo in basic, greedy and fast allocators (#226523)

Make RegAllocBase use the MachineRegisterClassInfo analysis and publish
the
newly frozen set to it with updateReservedRegs. This reuses the set
computed by
freezeReservedRegs() instead of calling TRI->getReservedRegs() again, so
the
shared state becomes correct for everyone without an additional
reserved-set
computation.

No allocator should keep a private RegisterClassInfo after this.
A pass that changes the reserved set and is followed by an allocator no
longer
has to publish it by hand.

AI-assisted.
DeltaFile
+23-14llvm/lib/CodeGen/RegAllocFast.cpp
+14-7llvm/lib/CodeGen/RegAllocGreedy.cpp
+9-4llvm/lib/CodeGen/RegAllocBasic.cpp
+5-5llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+6-4llvm/lib/CodeGen/RegAllocBase.cpp
+2-5llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
+59-397 files not shown
+68-4213 files

LLVM/project edf3c6a — llvm/test/CodeGen/AMDGPU local-atomicrmw-fmin.ll local-atomicrmw-fmax.ll, llvm/test/CodeGen/NVPTX fma-relu-contract.ll fma-relu-instruction-flag.ll

[SDAG] Improve bf16 converts with fast-math flags. (#231044)

This is a SDAG equivalent of #200741, where given NoNan flags we can
avoid creating for nan inputs.
DeltaFile
+1,016-1,873llvm/test/CodeGen/AMDGPU/bf16.ll
+669-1,244llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
+273-349llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
+144-182llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
+70-225llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+70-225llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+2,242-4,0987 files not shown
+2,403-4,40513 files

LLVM/project d1e7030 — llvm/lib/Target/AArch64 AArch64StackTagging.cpp, llvm/lib/Transforms/Utils MemoryTaggingSupport.cpp

[AArch64][MTE] Tag dynamic allocas in AArch64StackTagging

Instrument dynamic allocas in the memtag-stack pass, more or less
following the the way AddressSanitizer does: by instrumenting
stackrestore to un(poison/tag) allocas when free'd.

- Dynamic allocas are given 16-byte alignment and padded to 16-bytes.
- At lifetime.start (or at the alloca if no lifetimes), the dynamic
alloca is tagged.
- The most recently executed dynamic alloca is tracked in an extra
per-func static alloca. The address of this static alloca is used
as the bottom (highest address) of the dynamic alloca section of
the frame, while the value stored there is treated as the current
top (lowest address) of the frame.
- At llvm.stackrestores, memory is untagged from the restored sp
to the last executed dynamic alloca.
- At function returns, memory is untagged from the last executed
dynamic alloca to the bottom of the (dynamic alloca section of) the
frame.

    [2 lines not shown]
DeltaFile
+779-0llvm/test/CodeGen/AArch64/stack-tagging-dynamic-alloca.ll
+168-8llvm/lib/Target/AArch64/AArch64StackTagging.cpp
+100-0llvm/test/CodeGen/AArch64/stack-tagging-dynamic-alloca-history.ll
+17-7llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
+18-0llvm/test/CodeGen/AArch64/stack-tagging-dbg-declare-tag-offset.ll
+7-5llvm/test/CodeGen/AArch64/stack-tagging.ll
+1,089-202 files not shown
+1,097-228 files

LLVM/project 6dd4a38 — llvm/lib/Target/AArch64 AArch64StackTagging.cpp

[AArch64][MTE] Fix nondeterministic compare order causing windows failure
DeltaFile
+3-2llvm/lib/Target/AArch64/AArch64StackTagging.cpp
+3-21 files

LLVM/project 00e9861 — llvm/lib/Target/AMDGPU GCNSubtarget.h GCNFeatures.td

[AMDGPU] Bundle counter layouts as features

Generation feature lists stay plain lists: the shared gfx11 and gfx12
counter layouts become features implying their fields, instead of
defvars spliced in with !listconcat.

Change-Id: Id1656a599f7d9b4fa43c82bb811ca311881dd603
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+21-15llvm/lib/Target/AMDGPU/GCNFeatures.td
+2-1llvm/lib/Target/AMDGPU/GCNSubtarget.h
+23-162 files

LLVM/project 689eaf7 — llvm/lib/Target/AArch64 AArch64ExpandPseudoInsts.cpp, llvm/test/CodeGen/AArch64 settag.ll

[AArch64][MTE] Fix bit width in variable-size settag loop expansion

expandSetTagLoopVar peels a single STG granule when the size is an odd
multiple of 16 (bit 4 set). It built this test with TBZX, the bit-32..63
form (which checks bit 36), when it should have used the TBZW form, which
actually tests bit 4.

Assisted-By: Claude
DeltaFile
+4-4llvm/test/CodeGen/AArch64/settag.ll
+5-2llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+9-62 files

FreeNAS/freenas 50c1368 — src/middlewared/middlewared/alembic/versions/27.0 2026-10-30_12-00_container_default_nic.py, src/middlewared/middlewared/alembic/versions/28.0 2026-10-30_12-30_merge.py 2026-10-26_12-00_container_default_nic.py

NAS-144247 / 28.0.0-BETA.1 / Merge the stable/27 container default NIC migration (#20100)

## Problem
The stable/27 backport of #20059 adds its container default NIC
migration to the 27.0 chain as revision `36eb34176424`. Master does not
know that revision, so a system upgraded from a 27.0 build that already
ran it cannot find its current revision in master's history and fails to
migrate. Master's own `c9ebd3e3cfbc` would also run on that upgrade and
add a NIC to every container without one, including containers the user
deliberately left without a NIC on 27.

## Solution
Add the 27.0 migration to master with a 28.0 merge migration joining it
to the current head, and make `c9ebd3e3cfbc` a no-op so `36eb34176424`
is the only migration that adds the default NIC. Master installs that
already ran `c9ebd3e3cfbc` will run `36eb34176424` once, which only
touches containers that currently have no NIC.
DeltaFile
+59-0src/middlewared/middlewared/alembic/versions/27.0/2026-10-30_12-00_container_default_nic.py
+4-39src/middlewared/middlewared/alembic/versions/28.0/2026-10-26_12-00_container_default_nic.py
+21-0src/middlewared/middlewared/alembic/versions/28.0/2026-10-30_12-30_merge.py
+84-393 files

FreeNAS/freenas 43eb760 — src/middlewared/middlewared/alembic/versions/27.0 2026-10-30_12-00_container_default_nic.py, src/middlewared/middlewared/plugins/container bridge.py factory.py

NAS-144247 / 27.0.0 / Manage container NICs explicitly instead of adding one on the fly (by Qubad786) (#20097)

## Problem
A container without a NIC device row got an implicit bridge NIC with no
MAC added on the fly at every start, so libvirt generated a new MAC each
time and the container came up with a different DHCP address after every
restart. Containers migrated from incus are usually in this state
because their eth0 came from the incus profile. Beyond the MAC churn,
silently attaching a NIC the user never configured isn't always what
users want.

## Solution
Container networking is now managed explicitly through NIC devices.

- **No implicit NIC**: a container only has network through its NIC
devices, and one without any gets a private namespace with only
loopback. This relies on truenas/truenas_pylibvirt#97 emitting
`<privnet/>` for such containers, so that has to land first.
`default_network` is dropped from the v28 container entry since it no

    [19 lines not shown]
DeltaFile
+59-0src/middlewared/middlewared/alembic/versions/27.0/2026-10-30_12-00_container_default_nic.py
+11-26src/middlewared/middlewared/plugins/container/lifecycle.py
+27-4src/middlewared/middlewared/plugins/container/migrate.py
+18-0src/middlewared/middlewared/plugins/container/factory.py
+7-4tests/api2/test_container.py
+0-8src/middlewared/middlewared/plugins/container/bridge.py
+122-426 files not shown
+140-5612 files

FreeBSD/ports 2ff5290 — www Makefile, www/mod_dav_svn pkg-descr pkg-plist

www/mod_dav_svn: rename to www/mod_subversion

The port has always built and installed three Apache modules (mod_dav_svn,
mod_authz_svn, mod_dontdothat), not just DAV support, so a name promising
only one of the three was misleading. Add PKGNAMEPREFIX=${APACHE_PKGNAMEPREFIX},
matching other modules.

Co-Authored-By: Claude Sonnet 5 <noreply at anthropic.com>
DeltaFile
+34-0www/mod_subversion/Makefile
+0-33www/mod_dav_svn/Makefile
+0-5www/mod_dav_svn/pkg-plist
+5-0www/mod_subversion/pkg-plist
+0-2www/mod_dav_svn/pkg-descr
+1-1www/Makefile
+40-412 files not shown
+43-418 files

LLVM/project 0ed0e2a — llvm/include/llvm/TargetParser AMDGPUCounterLayout.h, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

[AMDGPU] Keep wait counter layout in the backend

Counter field layouts only matter for instruction encoding; no
frontend needs them. Drop the TargetParser copy, the GPU table column
and the emitter changes, and move CounterLayout and its encode/decode
helpers back into AMDGPUBaseInfo, replacing the IsaVersion parameter.

Unit tests now check per-GPU masks and encodings through
MCSubtargetInfo.

Change-Id: Iaa0d100af5e3f1885da9261fb97340709955488a
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+187-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+0-180llvm/lib/TargetParser/AMDGPUCounterLayout.cpp
+0-175llvm/include/llvm/TargetParser/AMDGPUCounterLayout.h
+167-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+79-16llvm/unittests/Target/AMDGPU/CounterLayoutTest.cpp
+0-76llvm/unittests/TargetParser/TargetParserTest.cpp
+433-4479 files not shown
+451-51615 files

FreeBSD/ports 9cb124a — finance/odoo distinfo Makefile, finance/odoo/files odoo.conf odoo.conf.in

finance/odoo: Update to 20261023

- devel/py-setuptools and devel/py-wheel are added to BUILD_DEPENDS
- SHEBANG_LANG=python is dropped; USES=shebangfix already handles python
- odoo.conf.sample is installed with INSTALL_DATA instead of
  INSTALL_SCRIPT, and is generated through SUB_FILES, so its commented
  addons_path names the right site-packages (it said python3.11)
- odoo.conf.sample sets http_interface = 0.0.0.0, the 19.0 default, with
  a note that 127.0.0.1 fits behind a local proxy and becomes the
  default in Odoo 20.0; 19.0 warned at start that the option was
  missing. Existing etc/odoo/odoo.conf files are not changed
- the rc script passes --without-demo=True instead of
  --without-demo=all, which 19.0 no longer accepts as a boolean (it
  logged "invalid boolean value: 'all', assume True"); the meaning, no
  demo data, is the same
- portclippy and portfmt warnings are fixed

PR:             300224
Reported by:    Patrick Crandol <patrick ___at__ crandol.com>
DeltaFile
+0-88,864finance/odoo/pkg-plist
+31-28finance/odoo/Makefile
+19-0finance/odoo/files/patch-setup.py
+10-0finance/odoo/files/odoo.conf.in
+0-7finance/odoo/files/odoo.conf
+3-3finance/odoo/distinfo
+63-88,9021 files not shown
+65-88,9047 files

FreeBSD/ports 04712ee — finance/py-ofxparse Makefile

finance/py-ofxparse: Drop the unused py-nose dependency

- the port switches to USE_PYTHON=pep517 (the package metadata becomes
  dist-info)
- concurrent is added to USE_PYTHON
- portlint warnings are fixed

PR:             300225
Reported by:    Patrick Crandol <patrick _at__ crandol.com>
DeltaFile
+4-3finance/py-ofxparse/Makefile
+4-31 files

LLVM/project 7be3130 — llvm/lib/Target/X86 X86LoadValueInjectionRetHardening.cpp X86IndirectThunks.cpp

X86: Remove kill argument from addRegOffset (#237316)

This is now unused / always false. A few were true but had no tests.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+32-32llvm/lib/Target/X86/X86FrameLowering.cpp
+6-6llvm/lib/Target/X86/X86ISelLowering.cpp
+3-3llvm/lib/Target/X86/X86InstrInfo.cpp
+2-3llvm/lib/Target/X86/X86InstrBuilder.h
+1-2llvm/lib/Target/X86/X86IndirectThunks.cpp
+1-1llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp
+45-476 files

LLVM/project 5b69905 — llvm/test/CodeGen/AArch64 peephole-opt-subreg-to-reg-copy.mir, llvm/test/CodeGen/AArch64/Atomics aarch64_be-atomicrmw-v8a.ll aarch64-atomicrmw-lse2.ll

PeepholeOptimizer: Fix value tracking through SUBREG_TO_REG

The tracked source of a SUBREG_TO_REG was reported as the subregister
index of the inserted value, rather than the full inserted value. The
inserted value is never a register class supporting that index, so
this never found a usable source.

Some of the tests are regressions but I have a separate patch which
recovers those.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+95-97llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+75-75llvm/test/CodeGen/X86/vector-compress.ll
+87-0llvm/test/CodeGen/AArch64/peephole-opt-subreg-to-reg-copy.mir
+38-38llvm/test/CodeGen/X86/MergeConsecutiveStores.ll
+30-30llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
+30-30llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+355-27019 files not shown
+577-59425 files

LLVM/project da73731 — llvm/lib/Analysis ScalarEvolution.cpp

Revert "[SCEV] Try other implications when sign-flipped ones fail" (#237320)

This reverts the code change of commit
8cd6cafe2e037733c4d7d9d768920453ed09b319 (PR
https://github.com/llvm/llvm-project/pull/234594).

It causes a large compile-time increase on loop chains where each loop's
IV starts at the previous loop's IV exit value.
DeltaFile
+4-7llvm/lib/Analysis/ScalarEvolution.cpp
+4-71 files

LLVM/project 66b06f9 — llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor nofpclass-fmul.ll

Revert "[ValueTracking] Check noundef before applying square (fmul_self)" (#237161)

This reverts commit 05404cec67c67215394d2253002961a1d97a2f20.

It reintroduces the performance regression reported in #174763 where the
same check was previously reverted. Also as mentioned on #232178 the
policy is not to fix pre-existing multi-use undef issues without a
real-world miscompile.
DeltaFile
+2-2llvm/lib/Analysis/ValueTracking.cpp
+1-1llvm/test/Transforms/Attributor/nofpclass-fmul.ll
+3-32 files

FreeBSD/ports 86a4959 — net-mgmt/py-pdagent Makefile, net-mgmt/py-pdagent/files patch-pdagent_config.py patch-pdagent_thirdparty_six.py

net-mgmt/py-pdagent: Fix on Python 3.12+

- The vendored six 1.13.0 only implements the find_module() import
  protocol, which Python 3.12 no longer uses, so every
  pdagent.thirdparty.six.moves import failed and the agent and pd-*
  tools could not start.  Add find_spec(), create_module() and
  exec_module() as in six 1.16.
- pdagent.config used SafeConfigParser, removed in Python 3.12; use
  ConfigParser, its equivalent.

While here, fix portlint warnings and document the patches.

PR:             300277
DeltaFile
+46-0net-mgmt/py-pdagent/files/patch-pdagent_thirdparty_six.py
+18-0net-mgmt/py-pdagent/files/patch-pdagent_config.py
+3-2net-mgmt/py-pdagent/Makefile
+67-23 files

LLVM/project c41549e — llvm/lib/Transforms/Scalar JumpTableToSwitch.cpp, llvm/test/Transforms/Coroutines coro-retcon-once-value.ll

[JumpTableToSwitch] Treat select of functions as two-element jump table (#235452)

Optimize a `call (select cond f1 f2)` the same way as a `call (load ...)` from
a two-element table.

Without this optimizing `load ...` as `select cond f1 f2` causes losing
inlining opportunities and regressions.

IR changes:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1842

Compile times:
- https://llvm-compile-time-tracker.com/compare.php?from=b87685fc2ae3d189a8737fd96a27cd26bbda93b0&to=dce652299e012b84258451e00a1262f8be6f26dc&stat=instructions%3Au
- https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1902

+1.65% in sqlite3 caused by fully inlining these functions, which are called
126 times in total before this patch: `@binCompare`, `@strCompare`, `@binHash`,
`@strHash`.


    [2 lines not shown]
DeltaFile
+84-0llvm/test/Transforms/JumpTableToSwitch/select.ll
+48-16llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
+4-6llvm/test/Transforms/Coroutines/coro-retcon-once-value.ll
+136-223 files

LLVM/project 3f311de — llvm/test/CodeGen/X86 pr235663.ll

[DAG] Add test coverage for #235663 (#237334)
DeltaFile
+63-0llvm/test/CodeGen/X86/pr235663.ll
+63-01 files

LLVM/project 529485f — llvm/lib/CodeGen MachineLICM.cpp

[MachineLICM] Cache regmask clobbered register units per function

HoistRegionPostRA calls applyBitsNotInRegMaskToRegUnitsMask for every
regmask operand (i.e. every call) in a loop, and again for each enclosing
loop. Each call walks every physical register and its register units,
which is expensive on targets with many registers (about 700 on AArch64),
even though the result depends only on the mask, and calls almost always
use one of a few calling-convention masks.

Compute the clobbered register units once per mask and function and OR
the cached set into RUClobbers. The result is identical by construction.
DeltaFile
+21-2llvm/lib/CodeGen/MachineLICM.cpp
+21-21 files

LLVM/project 076e150 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-scalar.ll

[RISCV][P-ext] Improve codegen for funnel shifts (#235245)

This patch improves RV32 code generation for 64-bit funnel shifts. It
splits them into 32-bit slx/srx operations and uses merge instructions
to select the appropriate halves.

This removes branches and reduces the worst-case dynamic instruction
count.
DeltaFile
+225-0llvm/test/CodeGen/RISCV/rvp-scalar.ll
+39-79llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+54-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+318-803 files

LLVM/project 3888d7a — llvm/lib/MC MCObjectFileInfo.cpp, llvm/test/CodeGen/SystemZ zos-dwarf-ada-crash.ll

[SystemZ][z/OS] Add missing ADA reference to DWARF sections (#237276)

Labels marked as DATA needs a reference to the ADA. However, this is
missing for the DWARF sections, which can lead to crashes in certain
scenarios. Fix is to set the ADA reference.

Assisted by: IBM Bob
DeltaFile
+39-0llvm/test/CodeGen/SystemZ/zos-dwarf-ada-crash.ll
+1-0llvm/lib/MC/MCObjectFileInfo.cpp
+40-02 files

FreeBSD/src 99a5880 — sys/kern kern_descrip.c

fdcopy(): properly update fd_freefile when skipping non-copyable fd

fd_freefile is maintained to fulfill the POSIX guarantee that the lowest
possible file descriptor is allocated on open.  If we skip copying an
fd, it is a possible candidate for the lowest index.

First, the file descriptor installed with a kqueue created
without KQUEUE_CPONFORK missed this handling [*].

Second, fd_freefile should be updated only when the current fd index is
below it.  A skipped fd above fd_freefile could raise it past a free slot.

PR:     300234 [*]
Reported by:    Andrea Venturoli <freebsd at netfence.it>
Reviewed by:    markj
Fixes:  1265516c5c61 ("struct file: add DFLAG_FORK, indicate copying on fork")
Fixes:  809f3121be66 ("fd: assign fd_freefile early when copying")
MFC after:      1 week
Differential revision:  https://reviews.freebsd.org/D61054
DeltaFile
+5-2sys/kern/kern_descrip.c
+5-21 files

FreeBSD/ports bb51f3f — www/py-selenium-wire Makefile

www/py-selenium-wire: Deprecate

The vendored mitmproxy imports blinker._saferef, which blinker 1.8
removed, so seleniumwire.webdriver no longer imports. Its certs.py
also uses pyOpenSSL crypto.X509Extension/X509Req, which pyOpenSSL 26.4
no longer has, so the TLS interception core would need porting to
cryptography. Upstream is archived; 5.1.0 (2022) is the last release.

PR:             299851
DeltaFile
+3-0www/py-selenium-wire/Makefile
+3-01 files

LLVM/project 1d07042 — llvm/utils/gn/secondary/libcxx/src BUILD.gn

[gn][NFC] Remove obsolete macro definition (#219000)

The _LIBCPP_DISABLE_NEW_DELETE_DEFINITIONS macro is not honoured anymore
since afc5cca0d401, 3 years ago. This has been dead code since then.
DeltaFile
+0-3llvm/utils/gn/secondary/libcxx/src/BUILD.gn
+0-31 files