[flang][OpenMP] Fix LINEAR clause validation to report all errors (#175938)
Fixes #175688
After #175383 was merged, test failures occurred because removing the
early return exposed additional errors that tests weren't expecting.
This PR comprehensively fixes the issue by:
1. **Removes the early return** in check-omp-loop.cpp (line 767) after
detecting a modifier error on DO/SIMD directives. Previously, when a
modifier error was found, the function would return immediately without
checking other restrictions like the scalar requirement. Now all
applicable errors are reported, improving diagnostics.
2. **Updates linear-clause01.f90** to expect both the modifier error AND
the scalar error for Case 1 and Case 2, where arrays are used
incorrectly in LINEAR clauses.
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[flang][NFC] Converted five tests from old lowering to new lowering (part 6) (#175485)
Modified the following tests: array-elemental-calls-2.f90,
array-expression-assumed-size.f90, array-temp.f90,
array-user-def-assignments.f90, array.f90
[NFC][IRBuilder] Reuse CreateGEP for helpers (#175979)
Many helper functions for single index GEP exist, but each implement the
same logic to then create the GetElementPtrInst. Refactoring to call a
single function.
This is some groundwork to prepare the SGEP implementation.
InstCombine: Improve SimplifyDemandedFPClass min/max handling
Refine handling of minimum/maximum and minimumnum/maximumnum. The
previous folds to input were based on sign bit checks. This was too
conservative with 0s. This can now consider -0 as less than or equal
to +0 as appropriate, account for nsz. It additionally can handle
cases like one half is known positive normal and the other subnormal.
InstCombine: Add more tests for min/max SimplifyDemandedFPClass
Test some more refined cases, such as ordering with 0s and within
known positive and known negative cases.
[clang][ssaf][docs] Document the Summary Extraction pipeline (#172876)
This patch adds some documentation about the design of the Scalable
Static Analysis Framework (SSAF) Summary Extraction part.
This mainly focuses on how the custom FrontendAction would load
different analyses (their extraction part), and the different formats it
should export into.
Each FrontendAction call would process a single TU by extracting
summaries from them and serializing the results into a file in the
desired format.
The details are not polished yet, but I think it's still beneficial to
have some guidance on how the upcoming components would fit together,
hence this document.
I'll come back to this document to keep it up-to-date as we proceed with
the upstreaming.
[NFC][PowerPC] add test cases for milicode (#175559)
In this PR, we do the following:
1. Simplify the test case for the millicode function `___memmove`.
2. Add test cases for the millicode functions `___memcpy` ,
`____memset`, `____memmove` which are supported in the patch
https://reviews.llvm.org/D143997.
3. Add pre-commit test cases for the functions `___strstr`,
`___memccpy`, `___strcmp`
[HLSL][Matrix] Add type conversions to support bool matrix single subscript operators (#175633)
Fixes #172711
Fixes the type mismatch issues preventing single matrix subscript
getters and setters from working with boolean matrices.
The changes from this PR also happens to make matrix splats work for
boolean matrices, but adding tests for that and (re)introducing
boolean-matrix-specific sema will be relegated to its own PR.
[SPIR-V] Fix store to first element array (#175546)
The IR can store to the first element of an array the same way it stores
to the first element of a struct by specifying the base pointer. This
commit fixes the pointercast legalization pass to support this.
[AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188)
When SubRegister Liveness Tracking (SRLT) is enabled, this pass adds
extra implicit-def's to instructions that define the low N bits of a
GPR/FPR register to represent that the top bits are written, because all
AArch64 instructions that write the low bits of a GPR/FPR also
implicitly zero the top bits.
These semantics are originally represented in the MIR using
`SUBREG_TO_REG`, but during register coalescing this information is lost
and when rewriting virtual -> physical registers the implicit-defs are
not added to represent the the top bits are written.
There have been several attempts to fix this in the coalescer (#168353),
but each iteration has exposed new bugs and the patch had to be
reverted. Additionally, the concept of adding 'implicit-def' of a
virtual register during the register allocation process is particularly
fragile and many places don't expect it (for example in
`X86::commuteInstructionImpl` the code only looks at specific operands
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[NFC][MLIR] Remove obsolete target device test from openmp-todo.mlir (#175894)
Remove the target device test from openmp-todo.mlir since MLIR-to-LLVM
IR lowering for the OpenMP target device clause is now implemented
(#173509, #174665).
[AArch64] Mark X16 as clobbered in PAUTH_EPILOGUE for hint-based PAuthLR
When users request branch protection with PAuthLR on targets that do not
support the PAuthLR instructions, the PAUTH_EPILOGUE falls back to using
hint-space instructions. This fallback sequence uses X16 as a temporary
register, but X16 was not listed in the clobber set.
Because Speculative Load Hardening uses X16, this omission made SLH
incompatible with this PAUTH_EPILOGUE path.
Mark X16 as clobbered so the compiler does not assume X16 is preserved across
the epilogue, restoring compatibility with Speculative Load Hardening and
avoiding incorrect register liveness assumptions. The clobber is added in C++
rather than TableGen, as X16 is only clobbered when PAuthLR is requested as a
branch protection variation and should not be treated as clobbered
unconditionally.
[AMDGPU] Ignore unused VALU src0/1/2 fields when disassembling (#175182)
This enables a future patch to change the default encoding of these
fields, which are mostly ignored by hardware.
[AMDGPU] Invert scc uses to delete s_cmp_eq* (#167382)
Delete s_cmp_eq* instructions by inverting instructions that use scc.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
NAS-139196 / 25.10.2 / Standardize repr output for listen delegates (by Qubad786) (#18024)
## Problem
The output of the `repr` method in the **port listen delegate** is not
standardized.
As a result, **attachment delegates** can produce two different output
formats. Since the **Pydantic model** supports only a single output
structure, this inconsistency leads to **validation errors**.
## Solution
Standardize the output of the **listen delegate** so it always matches
the expected **Pydantic model**, ensuring consistent behaviour and
preventing validation errors.
Original PR: https://github.com/truenas/middleware/pull/18022
Co-authored-by: M. Rehan <mrehanlm93 at gmail.com>
[flang][acc] Add ACCUseDeviceCanonicalizer pass (#175228)
This pass canonicalizes the use_device clause on acc.host_data
constructs to enable simpler runtime lowering. For use_device operands
that are box types or references to boxes, the pass:
1. Extracts the host base address for mapping to a device address using
acc.use_device
2. Creates a new boxed descriptor with the device address as the base
address for use inside the host_data region
The pass also removes unused use_device clauses to reduce runtime calls.
This canonicalization hoists load/box_addr patterns out of the host_data
region so they are applied to the host variable before acc.use_device,
ensuring the device pointer is used directly inside the region.
Example transformation for a reference to a box (!fir.ref<!fir.box<>>):
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