LLVM/project e9e714fclang/lib/StaticAnalyzer/Checkers/WebKit ASTUtils.cpp, clang/test/Analysis/Checkers/WebKit retain-ptr-ctor-adopt-use-arc.mm retain-ptr-ctor-adopt-use.mm

[alpha.webkit.RetainPtrCtorAdoptChecker] Don't treat calling (void)copy:(id) as a leak (#179713)

UIResponderStandardEditActions defines (void)copy:(id)sender but this
selector should not be treated as a copy operation since it's a "copy"
in the sense of application triggering copy & paste for the system
pasteboard.

---------

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
DeltaFile
+14-0clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use-arc.mm
+14-0clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use.mm
+6-1clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
+34-13 files

LLVM/project 135ec4ellvm/test/CodeGen/AArch64 funnel-shift.ll

[AArch64] Add test coverage for funnel shift with undef amount. NFC (#179888)

Precommit tests for #57256 showing inconsistencies between SDAG and
GISel for funnel shift with undef amount. GISel is wrong and should
match SDAG.
DeltaFile
+56-0llvm/test/CodeGen/AArch64/funnel-shift.ll
+56-01 files

OPNSense/core ad95bd1src/opnsense/mvc/app/models/OPNsense/Firewall Group.php

review comments @fichtner
DeltaFile
+2-4src/opnsense/mvc/app/models/OPNsense/Firewall/Group.php
+2-41 files

LLVM/project d61e411clang/include/clang/Analysis/Scalable/Serialization SerializationFormatRegistry.h

Update the SerializationFormatRegistry with the FormatInfo alias
DeltaFile
+1-0clang/include/clang/Analysis/Scalable/Serialization/SerializationFormatRegistry.h
+1-01 files

LLVM/project 7347b89llvm/lib/Target/AMDGPU SIISelLowering.cpp

rebase
DeltaFile
+4-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-11 files

FreeBSD/src 484bf5asbin/ifconfig ifgre.c

ifconfig: fix gre(4) status

Set `ifr->ifr_name` to display gre options
for the interface.

Reviewed by: glebius, zlei
Approved by: glebius (mentor)
MFC after: 1 day
Differential Revision: https://reviews.freebsd.org/D55099

(cherry picked from commit c2ba906fa63982d7aa799466d83716d39fe91d2b)
DeltaFile
+2-2sbin/ifconfig/ifgre.c
+2-21 files

LLVM/project 84cdaa4clang/lib/Driver Driver.cpp, clang/lib/Driver/ToolChains Gnu.cpp CommonArgs.cpp

Reland "[clang][RISCV] Add big-endian RISC-V target support" (#177939)

The problem was using the `--rtlib=platform` without
`--unwindlib=platform` conflicts the default unwindlib with the
Fuchsia's configuration, and that is why the test failed.

Orignal PR: https://github.com/llvm/llvm-project/pull/165599
The fail was reported at:
https://github.com/llvm/llvm-project/pull/165599#issuecomment-3751750804

Co-authored-by: Djordje Todorovic <djordje.todorovic at syrmia.com>
DeltaFile
+95-0clang/test/Driver/riscv-be.c
+34-5clang/lib/Driver/ToolChains/Gnu.cpp
+22-4clang/lib/Driver/Driver.cpp
+12-0clang/test/CodeGen/riscv-be-data-layout.c
+10-0clang/lib/Driver/ToolChains/CommonArgs.cpp
+7-2clang/lib/Driver/ToolChains/Clang.cpp
+180-1130 files not shown
+218-1736 files

LLVM/project 0e90d0eclang/unittests/Analysis/Scalable/Registries FancyAnalysisData.cpp

Move the FormatInfo alias closer to where it matters
DeltaFile
+1-1clang/unittests/Analysis/Scalable/Registries/FancyAnalysisData.cpp
+1-11 files

LLVM/project bf096a7clang/unittests/Analysis/Scalable/Registries FancyAnalysisData.cpp

Fix typo in Description string
DeltaFile
+1-1clang/unittests/Analysis/Scalable/Registries/FancyAnalysisData.cpp
+1-11 files

LLVM/project 75d12b4clang/unittests/Analysis/Scalable/Registries FancyAnalysisData.cpp

Remove unused include
DeltaFile
+0-1clang/unittests/Analysis/Scalable/Registries/FancyAnalysisData.cpp
+0-11 files

FreeBSD/src 6fd6fa4sbin/ifconfig ifgre.c

ifconfig: fix gre(4) status

Set `ifr->ifr_name` to display gre options
for the interface.

Reviewed by: glebius, zlei
Approved by: glebius (mentor)
MFC after: 1 day
Differential Revision: https://reviews.freebsd.org/D55099

(cherry picked from commit c2ba906fa63982d7aa799466d83716d39fe91d2b)
DeltaFile
+2-2sbin/ifconfig/ifgre.c
+2-21 files

LLVM/project 3eb4b93clang/unittests/Analysis/Scalable/Registries SerializationFormatRegistryTest.cpp

Also simplify the unittest file input
DeltaFile
+2-6clang/unittests/Analysis/Scalable/Registries/SerializationFormatRegistryTest.cpp
+2-61 files

FreeBSD/ports 9609a9fgraphics/gegl Makefile, graphics/gegl/files patch-gegl_gegl-init.c

graphics/gegl: deal with FreeBSD procfs in Right Way(tm)

FreeBSD procfs implementation is not equal the linux one.
Handle it correctly
DeltaFile
+63-0graphics/gegl/files/patch-gegl_gegl-init.c
+1-1graphics/gegl/Makefile
+64-12 files

FreeBSD/ports f8b5751x11/babl Makefile, x11/babl/files patch-babl_babl.c

x11/babl: deal with FreeBSD procfs in Right Way(tm)

FreeBSD procfs implementation is not equal the linux one.
Handle it correctly
DeltaFile
+49-0x11/babl/files/patch-babl_babl.c
+1-1x11/babl/Makefile
+50-12 files

LLVM/project a7891b2clang/unittests/Analysis/Scalable/Registries FancyAnalysisData.cpp

Apply suggested simplifications
DeltaFile
+5-34clang/unittests/Analysis/Scalable/Registries/FancyAnalysisData.cpp
+5-341 files

LLVM/project 9e052dellvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 avx512bwvl-arith.ll

[X86] lower1BitShuffle - recognise a blend shuffle that can lower to AND/MASKZ pattern (#179717)

Part of the missed-optimisation mentioned on #179630 - if the shuffle is
a blend with zero, then lower as a ISD::AND pattern
DeltaFile
+10-0llvm/lib/Target/X86/X86ISelLowering.cpp
+3-6llvm/test/CodeGen/X86/avx512bwvl-arith.ll
+13-62 files

LLVM/project 5349c66lldb/source/Plugins/Process/FreeBSDKernel ProcessFreeBSDKernel.cpp

[lldb] [Process/FreeBSDKernel] List threads in correct order (#178306)

In FreeBSD, allproc is a prepend list and new processes are appended at
head. This results in reverse pid order, so we first need to order pid
incrementally then print threads according to the correct order.

Before:
```
Process 0 stopped
* thread #1: tid = 101866, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff8015882f780, flags=259) at sched_ule.c:2448:26, name = '(pid 12991) dtrace'
  thread #2: tid = 101915, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff80158825780, flags=259) at sched_ule.c:2448:26, name = '(pid 11509) zsh'
  thread #3: tid = 101942, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff80142599000, flags=259) at sched_ule.c:2448:26, name = '(pid 11504) ftcleanup'
  thread #4: tid = 101545, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff80131898000, flags=259) at sched_ule.c:2448:26, name = '(pid 5599) zsh'
  thread #5: tid = 100905, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff80131899000, flags=259) at sched_ule.c:2448:26, name = '(pid 5598) sshd-session'
  thread #6: tid = 101693, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff8015886e780, flags=259) at sched_ule.c:2448:26, name = '(pid 5595) sshd-session'
  thread #7: tid = 101626, 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff801588be000, flags=259) at sched_ule.c:2448:26, name = '(pid 5592) sh'
...
```


    [14 lines not shown]
DeltaFile
+21-11lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp
+21-111 files

OPNSense/core b39a90bsrc/opnsense/mvc/app/models/OPNsense/Firewall Group.php

Firewall: Rules [new]: Fix group rename in source_net, destination_net and SNAT/DNAT target fields
DeltaFile
+20-1src/opnsense/mvc/app/models/OPNsense/Firewall/Group.php
+20-11 files

LLVM/project 5a19499clang/lib/CodeGen TargetInfo.h, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

Address comments
DeltaFile
+64-22clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
+33-51clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+28-36clang/lib/CodeGen/Targets/SPIR.cpp
+34-9clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
+6-10clang/lib/CodeGen/Targets/AMDGPU.cpp
+10-5clang/lib/CodeGen/TargetInfo.h
+175-1331 files not shown
+184-1347 files

LLVM/project f9196c6clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/lib/Sema SemaAMDGPU.cpp

Address comments
DeltaFile
+51-0clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
+24-14clang/lib/Sema/SemaAMDGPU.cpp
+32-0clang/test/SemaHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
+12-17clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+26-0clang/test/SemaHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
+25-0clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
+170-311 files not shown
+175-377 files

LLVM/project e48d77eclang/include/clang/Basic BuiltinsAMDGPU.td, clang/include/clang/Sema SemaAMDGPU.h

Use macros for syncscope instead
DeltaFile
+31-20clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
+41-8clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+19-12clang/lib/Sema/SemaAMDGPU.cpp
+6-6clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
+6-6clang/include/clang/Basic/BuiltinsAMDGPU.td
+0-4clang/include/clang/Sema/SemaAMDGPU.h
+103-566 files

LLVM/project 876cf2aclang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-load-monitor.cl

Revert to old name
DeltaFile
+42-42llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
+24-24clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
+21-21clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
+20-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+18-18clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+8-8llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+133-1339 files not shown
+173-17915 files

LLVM/project 20119f3clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/lib/Sema SemaAMDGPU.cpp

[AMDGPU][GFX12.5] Reimplement monitor load as an atomic operation

Load monitor operations make more sense as atomic operations, as
non-atomic operations cannot be used for inter-thread communication w/o
additional synchronization.
The previous built-in made it work because one could just override the CPol
bits, but that bypasses the memory model and forces the user to learn about
ISA bits encoding.

Making load monitor an atomic operation has a couple of advantages. First,
the memory model foundation for it is stronger. We just lean on the existing
rules for atomic operations. Second, the CPol bits are abstracted away from
the user, which avoids leaking ISA details into the API.

This patch also adds supporting memory model and intrinsics documentation to
AMDGPUUsage.

Solves SWDEV-516398.
DeltaFile
+73-53llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
+90-18llvm/docs/AMDGPUUsage.rst
+58-30llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+51-24clang/lib/Sema/SemaAMDGPU.cpp
+31-24clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+24-24clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
+327-17310 files not shown
+450-21016 files

LLVM/project 47620e7llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-non-volatile-accesses.ll promote-alloca-vgpr-ratio.ll

[AMDGPU][PromoteAlloca] Set !amdgpu.non.volatile if promotion fails

I thought about doing this in a separate pass, but this pass already has all the necessary analysis for this to be a trivial addition.
We can simply set `!amdgpu.non.volatile`  if all other attempts to promote the operation failed.
DeltaFile
+45-0llvm/test/CodeGen/AMDGPU/promote-alloca-non-volatile-accesses.ll
+23-18llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
+29-2llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+2-2llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
+99-224 files

LLVM/project 188f2b8llvm/lib/Target/AMDGPU SIISelLowering.cpp

Rename to MOThreadPrivate
DeltaFile
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-11 files

LLVM/project 9827825llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIISelLowering.cpp

Pull metadata impl at the top of the patch stack
DeltaFile
+218-0llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
+23-0llvm/docs/AMDGPUUsage.rst
+2-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+243-03 files

LLVM/project 95038fellvm/lib/Target/AMDGPU SIInstrInfo.h SIMemoryLegalizer.cpp

Rename to MOThreadPrivate
DeltaFile
+3-2llvm/lib/Target/AMDGPU/SIInstrInfo.h
+2-2llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+1-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+6-53 files

LLVM/project 7cfff4bllvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir

Rename to MOThreadPrivate
DeltaFile
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+1,260-1,260llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+902-902llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+180-180llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
+166-167llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+140-140llvm/test/CodeGen/AMDGPU/frame-index.mir
+6,962-6,96336 files not shown
+7,586-7,58742 files

LLVM/project 01ea3adllvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp SIInstrInfo.h

[AMDGPU][GFX12.5] Add support for emitting memory operations with nv bit set

- Add & document `!amdgpu.non.volatile` metadata and a corresponding `MONonVolatile` MachineMemOperand flag.
- Set nv=1 on memory operations on GFX12.5 if the operation accesses a constant address space,
  is an invariant load, or has the `MONonVolatile` flag set.
DeltaFile
+564-0llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
+48-13llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+23-0llvm/docs/AMDGPUUsage.rst
+4-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+2-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
+642-141 files not shown
+643-147 files

LLVM/project 7958bf8llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir

[AMDGPU] Set MONonVolatile on memory accesses for spills

Mark the memory operand of spill load/stores as non-volatile, so that these
loads and stores are emitted with `nv` set.

The reason is that scratch memory used by spills will never be shared by
another thread. It's purely thread local and thus a good fit for the `nv` bit.
DeltaFile
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+1,260-1,260llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+902-902llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+180-180llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
+166-166llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+12,350-12,35041 files not shown
+13,183-13,18147 files