[MLIR][XeGPU] Hoist i4 extensions above lane shuffles (#234760)
Hoist the i4-to-i8 portion of integer extensions through single-use
lane-shuffle and vector data-movement chains before XeGPU-to-XeVM
conversion. Legalize narrow casts into byte-level operations in a
separate preprocessing stage so the existing bitcast-shuffle lowering
can handle the widened fragments without repacking.
Cover signed and unsigned extensions, supported fragment widths,
layout-distribution shuffles, and unsupported consumers. Scope
preprocessing to casts and generated operations to preserve existing
conversion diagnostics.
converters/simdutf: update to 9.2.2
This is a backport, fixing a bug preventing use in C++23 projects.
The same issue will be fixed with an update to 9.3.3 in the main branch
shortly.
Changelog: https://github.com/simdutf/simdutf/releases/tag/v9.2.2
Reported by: mi
PR: 299350
[AMDGPU] Move wait counter layout to TargetParser (NFC)
Wait counter, HoldCnt and barrier member count field widths were derived
from IsaVersion comparisons, and callers parsed the CPU name to get the
version. Each new generation meant new C++ checks.
Describe each field shift/width that differs from the SI layout as a
numeric subtarget feature, and move the encode/decode logic to
TargetParser, keyed on the resulting CounterLayout. The backend builds
the same layout from feature bits. New hardware with known field values
now needs TableGen only. Pseudo and unknown targets keep the SI layout.
Change-Id: Id7dc2a50445eee45c5511ba4c0b68dcf2f547f98
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
contrib/kyua: update to 0.15.1
This new release contains multiple bugfixes. Please see the release
notes mentioned in the merge commit for more details.
MFC after: 2 weeks
Merge commit '3e05143b80d1537cdd51a5dcf742da31f400507e'
[RISCV][P-ext] Promote i32 sati/usati intrinsics to i64 on RV64. (#234346)
Instead of using p(u)sati.w. The trade off here is that p(u)sati.w
sometimes requires its output to be sign extended for ABI or compares.
While sati/usati sometimes requires its input to be sign extended
if it isn't a W instruction or an argument/return with the signext
attribute.
The sign extended input is what we would get a from a manually
written clamp pattern in C code. So there's an argument for
consistency.
It might be possible to have RISCVOptWInstrs convert to p(u)sati.w
if we aren't able to remove the sext.w from the input and only
the lower 32 bits of the result are used.
[ci] Add a workflow to run the LLVM test-suite
This adds a reusable workflow that builds and installs Clang at a given
commit, builds and runs the LLVM test-suite and creates a LNT v5 report.
The pipeline workflow can be dispatched manually or through the GitHub
API -- in the future we can trigger it via a cron job or a fancier system
like libc++'s.
Assisted by Claude
