LLVM/project 0b414fb — llvm/test/CodeGen/AMDGPU va-ssrc-sdst-hazard-sched.mir

Fix test

Change-Id: I1aef9ffd0713bed2af97fe758a32a013c83c2af7
DeltaFile
+4-2llvm/test/CodeGen/AMDGPU/va-ssrc-sdst-hazard-sched.mir
+4-21 files

LLVM/project 6f41962 — libc/src/__support/OSUtil/linux/syscall_wrappers shmdt.h, libc/src/sys/shm shmdt.h

[libc][sys/shm] Implement shmdt syscall wrapper on Linux. (#239785)

`shmdt` is a POSIX function (see
[docs](https://pubs.opengroup.org/onlinepubs/9799919799/functions/shmdt.html#))
that detaches the shared memory segment from the address space of a
calling process.

On Linux, it can be implemented as a simple wrapper around SYS_shmdt
syscall.

Provide the implementation, and add a simple test case verifying it only
works correctly on addresses returned by `shmat` call.
DeltaFile
+55-0libc/test/src/sys/shm/linux/shmdt_test.cpp
+33-0libc/src/__support/OSUtil/linux/syscall_wrappers/shmdt.h
+32-0libc/src/sys/shm/linux/shmdt.cpp
+25-0libc/src/sys/shm/shmdt.h
+11-9libc/test/src/sys/shm/linux/shmat_test.cpp
+19-0libc/test/src/sys/shm/linux/CMakeLists.txt
+175-97 files not shown
+217-913 files

LLVM/project 216a14a — llvm/lib/Target/RISCV RISCVInstrInfo.cpp RISCVFeatures.td, llvm/test/CodeGen/RISCV reserved-reg-errors-alias.ll

[RISCV] Report errors for user reserving argument/return registers with Zhinx/Zfinx. (#239384)

Zhinx/Zfinx can use X10_H-X17_H or X10_W-X10_H subregisters. These were
not tracked in the bitvector in RISCVSubtarget.

The subtarget now contains a 32 element bitset for just the X registers.
The full bitset has moved to RISCVRegisterInfo where it is populated
with the aliases in the constructor.

RISCVRegisterInfo::getReservedRegs now uses the 32 element bitset. This
required moving the constant registers out of the loop and reserving
them explicitly. Alternatively, we could use the full bitset here, but
since we use markSuperRegs, we'd end up visiting registers multiple
times.

I've kept an accessor for the full bitset in RISCVSubtarget to avoid
touching all callers.

Assisted-by: Claude
DeltaFile
+22-15llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+37-0llvm/test/CodeGen/RISCV/reserved-reg-errors-alias.ll
+14-1llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+9-2llvm/lib/Target/RISCV/RISCVSubtarget.h
+1-1llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+1-1llvm/lib/Target/RISCV/RISCVFeatures.td
+84-206 files

LLVM/project 7a08f39 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIFoldOperands.cpp

AMDGPU: Remove clearKillFlags calls

Kill flags on physical registers here are either never set by the
time this code runs or are on reserved or constant registers where
they carry no information. Remove the clearKillFlags calls.

SIPeepholeSDWA was adding a kill flag on the virtual register it ties
to the preserved destination and relying on the clear to remove it.
Stop adding it.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+1-18llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+0-13llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+0-9llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-403 files

LLVM/project b44013d — llvm/lib/CodeGen MachineSink.cpp

MachineSink: Remove clearKillFlags calls

Kill flags on physical registers here are either never set by the
time this code runs or are on reserved or constant registers where
they carry no information. Remove the clearKillFlags calls.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-20llvm/lib/CodeGen/MachineSink.cpp
+0-201 files

LLVM/project ce04062 — llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU va-ssrc-sdst-hazard-sched.mir atomic_optimizations_global_pointer.ll

Widen hazard conditions to account for VCC RegClass matching + fold hazard checking

Change-Id: If1a818206d383bababe156185cec1831229e7bec
DeltaFile
+18-159llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+18-18llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
+9-9llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+2-3llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+2-2llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+1-1llvm/test/CodeGen/AMDGPU/va-ssrc-sdst-hazard-sched.mir
+50-1926 files

LLVM/project 907aa7a — llvm/lib/Target/LoongArch LoongArchOptWInstrs.cpp

LoongArch: Remove clearKillFlags calls on virtual registers

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-1llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
+0-11 files

LLVM/project fdb5365 — llvm/lib/Target/PowerPC PPCMIPeephole.cpp

PowerPC: Remove clearKillFlags calls on virtual registers

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-2llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+0-21 files

FreeBSD/src 6129bc4 — share/man/man4 iscsi.4, sys/dev/iscsi iscsi.c

iSCSI: Fast and per-session timeouts

Support per-session configurable ping (SCSI NOP) and login timeouts
similar to what is supported in the Linux iSCSI initiator configuration file.

Reduce iscsi timer granularity to 0.1 sec.
For backwards compatibility, when all timers are selected on integer numbers,
all status messages are unchanged. If the higher granularity is used, the
log messages include sub-second granularity.

The sysctl(3) interface has changed from pure int to string, in order to
support fractional seconds in a human-readable, dotted notation.

Reviewed By: #netapp, #manpages, jhb, pauamma_chezdork.com, siderop1_netapp.com
Sponsored by: NetApp, Inc.
Differential Revision: https://reviews.freebsd.org/D32540
DeltaFile
+35-18sys/dev/iscsi/iscsi.c
+23-2usr.bin/iscsictl/parse.y
+8-6usr.bin/iscsictl/iscsictl.c
+6-2usr.sbin/iscsid/iscsid.c
+4-3share/man/man4/iscsi.4
+3-3usr.bin/iscsictl/iscsi.conf.5
+79-342 files not shown
+82-348 files

LLVM/project c69f817 — llvm/lib/Target/X86 X86OptimizeLEAs.cpp

X86: Remove clearKillFlags calls on virtual registers

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-6llvm/lib/Target/X86/X86OptimizeLEAs.cpp
+0-61 files

LLVM/project c16d477 — llvm/lib/Target/RISCV RISCVVectorPeephole.cpp RISCVOptWInstrs.cpp

RISCV: Remove clearKillFlags calls on virtual registers

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-6llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+0-1llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+0-1llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+0-83 files

LLVM/project fa61fe8 — llvm/lib/Target/RISCV RISCVZilsdOptimizer.cpp, llvm/test/CodeGen/RISCV O3-pipeline.ll

[RISCV] Drop MachineDominatorTreeWrapperPass in Zilsd optimizer (#239783)

The last use of MachineDominatorTreeWrapperPass in
RISCVZilsdOptimizer.cpp was removed on November 6, 2026 in commit
d8ce3e5f727698eacfc46687562e5c53ab7c7241.

This patch removes the unused MachineDominatorTreeWrapperPass dependency
and MachineDominators.h include from RISCVZilsdOptimizer.cpp.  Dropping
this dependency defers MachineDominator Tree Construction in the legacy
RISC-V -O3 pipeline until right before Slot index numbering.

Assisted-by: Antigravity
DeltaFile
+0-3llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+1-1llvm/test/CodeGen/RISCV/O3-pipeline.ll
+1-42 files

FreeBSD/ports 246708d — multimedia/droidcam Makefile distinfo

multimedia/droidcam: Update 2.1.5 => 2.1.7

Changelogs:
https://github.com/dev47apps/droidcam-linux-client/releases/tag/v2.1.6
https://github.com/dev47apps/droidcam-linux-client/releases/tag/v2.1.7

Reported by:    Repology, portscout
Approved by:    osa, vvd (mentors, implicit)
MFH:            2026Q4

(cherry picked from commit 1fc609e4d70f299a8be00c8c4c6b24f41775b579)
DeltaFile
+3-3multimedia/droidcam/distinfo
+1-1multimedia/droidcam/Makefile
+4-42 files

FreeBSD/ports 1fc609e — multimedia/droidcam Makefile distinfo

multimedia/droidcam: Update 2.1.5 => 2.1.7

Changelogs:
https://github.com/dev47apps/droidcam-linux-client/releases/tag/v2.1.6
https://github.com/dev47apps/droidcam-linux-client/releases/tag/v2.1.7

Reported by:    Repology, portscout
Approved by:    osa, vvd (mentors, implicit)
MFH:            2026Q4
DeltaFile
+3-3multimedia/droidcam/distinfo
+1-1multimedia/droidcam/Makefile
+4-42 files

LLVM/project ebcde07 — llvm/lib/Target/X86 X86AvoidStoreForwardingBlocks.cpp

X86: Remove dead kill flag maintenance in X86AvoidStoreForwardingBlocks (#239777)

This pass runs before register allocation, and the verifier now
rejects kill flags on virtual registers.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-33llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
+0-331 files

LLVM/project b9c30ea — llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination sadd-with-overflow.ll minmax.ll

[ConstraintElim] Split signed min/max across their operands when checking a compare

The existing constraint systems only record the bounds that hold for both
operands of a min/max (smax(a, b) >= a and >= b, smin(a, b) <= a and <= b). The
other direction is a disjunction, which cannot be recorded as a fact. When a
compare of signed decompositions involves a min/max result, split it into its
operands: the decomposition is monotonic in that result, so it is the max or min
of its values on each side, and the relation holds for all or for either side
respectively.

https://alive2.llvm.org/ce/z/zsGkJ-
DeltaFile
+366-3llvm/test/Transforms/ConstraintElimination/minmax.ll
+111-0llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+4-8llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+481-113 files

LLVM/project d72667b — llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination add-nsw.ll sadd-with-overflow.ll

[ConstraintElim] A signed sum of operands with opposite signs cannot wrap

If one operand is known non-negative and the other non-positive, the signed
sum is between them, so it cannot overflow.

https://alive2.llvm.org/ce/z/ZF5Yqr
DeltaFile
+97-2llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+19-0llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+3-6llvm/test/Transforms/ConstraintElimination/add-nsw.ll
+119-83 files

LLVM/project c40cf3d — llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination ssub-with-overflow.ll sadd-with-overflow.ll

[ConstraintElim] Prove sadd/ssub.with.overflow cannot overflow from the exact sum

Decompose the operands and show that the sum lies in the range of the type. This
handles patterns like A + (B - A), as well as sums involving signed min/max
results, which are split across their respective operands using monotonicity
(for example start + smax(end - start - 1, 0) <= end).

https://alive2.llvm.org/ce/z/ze8LCk
DeltaFile
+539-0llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+159-4llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+100-0llvm/test/Transforms/ConstraintElimination/ssub-with-overflow.ll
+798-43 files

LLVM/project e82d29c — llvm/lib/Transforms/Scalar ConstraintElimination.cpp

remove pair + destructuring
DeltaFile
+4-4llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+4-41 files

LLVM/project 54c4c97 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIISelLowering.cpp

AMDGPU: Remove clearKillFlags calls on virtual registers (#239780)

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-6llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
+0-6llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+0-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+0-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+0-174 files

DragonFlyBSD/src d82ad2e — sys/kern kern_subr.c

kernel - Rework comments for uiomovebp()

* Do a better job explaining uiomovebp() and why it doesn't solve
  issues with MSDOSFS.
DeltaFile
+18-8sys/kern/kern_subr.c
+18-81 files

Linux/linux a7963b1 — drivers/gpu/drm/amd/amdgpu amdgpu_drv.c amdgpu_device.c, drivers/iommu/amd amd_iommu_types.h init.c

Merge tag 'iommu-fixes-v7.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux

Pull iommu fixes from Joerg Roedel:
 "AMD IOMMU:

   - Move PerfOpt management into the IOMMU domain attachment paths,
     enabling it automatically for supported integrated GPUs in identity
     mode and clearing it before switching to translated or blocked
     domains

   - Fix a boot panic in the GPU identity-mapping quirk when a GPU has
     no upstream PCI bridge

   - Clear the IOMMU SNP enable flag when RMP table initialization
     fails, preventing subsequent initialization from assuming SNP setup
     succeeded

   - Check IVRS subtable types before parsing memory definitions,
     avoiding bogus PCI segments caused by misinterpreting IVHD entries

    [11 lines not shown]
DeltaFile
+48-225drivers/iommu/amd/iommu.c
+63-43drivers/iommu/amd/init.c
+0-50drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+0-12drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+0-11include/linux/amd-iommu.h
+3-3drivers/iommu/amd/amd_iommu_types.h
+114-3442 files not shown
+115-3478 files

LLVM/project 90c2c0c — llvm/lib/Target/Hexagon HexagonPeephole.cpp HexagonGenInsert.cpp

Hexagon: Remove clearKillFlags calls on virtual registers (#239781)

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-3llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+0-3llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+0-2llvm/lib/Target/Hexagon/HexagonPeephole.cpp
+0-83 files

LLVM/project 749ef4e — libc/src/string/memory_utils/generic inline_strlen.h, libc/src/string/memory_utils/x86_64 inline_strlen.h

[libc] Don't match the byte after the range in vector find_first_character (#235288)

The vectorized `find_first_character` implementations (`clang_vector`
and the x86_64 `arch_vector`) returned the position of a match that was
the first byte after the searched range. For example, `memchr("ab", 'b',
1)` returned a pointer to the `'b'` instead of `nullptr`.

The new test covers all implementations, since no configuration selects
the vectorized ones by default. On aarch64 Linux, it fails without the
fix and passes with it. The x86_64 changes were only compiled, not run.

Assisted-by: Claude Code (Claude Opus 5.5)
DeltaFile
+35-0libc/test/src/strings/wide_read_memory_test.cpp
+1-1libc/src/string/memory_utils/x86_64/inline_strlen.h
+1-1libc/src/string/memory_utils/generic/inline_strlen.h
+37-23 files

NetBSD/src iVP6std — sys/arch/m68k/include profile.h

   __mcount() relies on a standard m68k stack frame and the frame pointer for
   two things:

   1- return address in __mcount()'s frame is used to get selfpc (i.e. the
      function being instrumented).

   2- __mcount() uses the saved-%fp in its own frame to get the frame pointer
      of the instrumented function, which is then used to get return address
      in that frame in order to get frompc.

   Ensure __mcount()'s stack frame is always set up correctly by decorating
   wiht __attribute__((__optimize__("no-omit-frame-pointer"))).
VersionDeltaFile
1.24+5-3sys/arch/m68k/include/profile.h
+5-31 files

LLVM/project f1da939 — libc/src/string/memory_utils/generic inline_strlen.h, libc/src/string/memory_utils/x86_64 inline_strlen.h

[libc] Don't read memory in vector find_first_character if n is 0 (#235289)

The vectorized `find_first_character` implementations (`clang_vector`
and the x86_64 `arch_vector`) loaded the aligned block containing the
start pointer before checking the length. With a length of zero, the
pointer doesn't have to be dereferenceable, so `memchr(p, c, 0)` and
`strnlen(p, 0)` crashed if `p` was the start of an inaccessible page.

The new test covers all implementations, since no configuration selects
the vectorized ones by default. On aarch64 Linux, it segfaults without
the fix and passes with it. The x86_64 changes were only compiled, not
run.

Assisted-by: Claude Code (Claude Opus 5.5)
DeltaFile
+23-0libc/test/src/strings/wide_read_memory_test.cpp
+4-0libc/src/string/memory_utils/x86_64/inline_strlen.h
+4-0libc/src/string/memory_utils/generic/inline_strlen.h
+31-03 files

FreeNAS/freenas 2c192ce — src/middlewared/middlewared event.py main.py, src/middlewared/middlewared/api/base/server event.py

Document the event payloads pool.scan and the event sources actually send
DeltaFile
+58-0src/middlewared/middlewared/pytest/unit/api/base/server/test_event_source_models.py
+33-1src/middlewared/middlewared/api/base/server/event.py
+2-11src/middlewared/middlewared/main.py
+2-5src/middlewared/middlewared/api/v28_0_0/zfs_tier.py
+4-0src/middlewared/middlewared/event.py
+4-0src/middlewared/middlewared/api/v28_0_0/pool_scrub.py
+103-171 files not shown
+106-177 files

LLVM/project 4220670 — llvm/test/CodeGen/AMDGPU srem.ll amdgpu-codegenprepare-idiv.ll, llvm/test/CodeGen/RISCV half-round-conv-sat.ll half-round-conv.ll

[DAG] Fold fp_to_int(ftrunc(x)) -> fp_to_int(x) (#231060)

fp_to_[su]int already rounds toward zero, so an ftrunc in front of it
does nothing and can be dropped. fp_to_[su]int_sat is the same since it
truncates before it clamps.

x86 hits this through LowerFROUND which expands round into a copysign
add plus an ftrunc so (long)roundf(x) keeps a vroundss that the convert
makes pointless.

The AArch64 test changes are shapes its isel patterns don't cover,
mostly f16 and bf16.

On RISC-V llvm.trunc on some test cases turns into an fabs, a compare,
an fcvt round trip and an fsgnj, or a call to trunc, and all of it goes
away.

AMDGPU runs integer division through a float reciprocal. The i32 cases
each lose a v_trunc_f32. The i64 files only change register numbering

    [7 lines not shown]
DeltaFile
+408-518llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+0-462llvm/test/CodeGen/RISCV/half-round-conv.ll
+389-0llvm/test/CodeGen/X86/fp-round.ll
+44-288llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+16-168llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
+88-88llvm/test/CodeGen/AMDGPU/srem.ll
+945-1,52423 files not shown
+1,370-2,31529 files

FreeNAS/freenas b4f2435 — src/middlewared/middlewared/pytest/unit/api/base test_secret_default_wrap.py, src/middlewared/middlewared/utils pydantic_.py

Document a Secret field's default as its value in the API schema
DeltaFile
+15-1src/middlewared/middlewared/utils/pydantic_.py
+15-0src/middlewared/middlewared/pytest/unit/api/base/test_secret_default_wrap.py
+30-12 files

FreeNAS/freenas 8b82566 — src/middlewared/middlewared/api/v28_0_0 kerberos.py interface.py, src/middlewared/middlewared/plugins kerberos.py

Make interface.lag_supported_protocols and kerberos.keytab.kerberos_principal_choices public
DeltaFile
+8-3src/middlewared/middlewared/plugins/interface/lag_protocols.py
+11-0src/middlewared/middlewared/api/v28_0_0/kerberos.py
+11-0src/middlewared/middlewared/api/v28_0_0/interface.py
+7-1src/middlewared/middlewared/plugins/kerberos.py
+37-44 files