LLVM/project 58d9781llvm/lib/Transforms/Utils CallPromotionUtils.cpp, llvm/test/Transforms/SampleProfile icp_target_feature.ll

[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features (#192142)

Profile-driven indirect call promotion was promoting indirect calls to
functions requiring advanced CPU features (e.g., AVX512) even when the
caller function did not support those features. When these promoted
calls were subsequently inlined, it could lead to invalid IR and
backend crashes during instruction selection because the target CPU
could not handle the advanced instructions.

This patch addresses the issue by adding a target feature
compatibility check to `llvm::isLegalToPromote` in
`CallPromotionUtils.cpp`. If the callee requires target features
(prefixed with `+`) that are not present in the caller's target
features, the promotion is skipped.  By centralizing this check in
`isLegalToPromote`, we protect all passes relying on this utility
(such as `SampleProfileLoader` and `IndirectCallPromotion`) from
promoting to incompatible targets. This also prevents incorrect
inlining of `always_inline` functions that would otherwise be promoted
via indirect calls and then inlined.

    [3 lines not shown]
DeltaFile
+61-0llvm/test/Transforms/SampleProfile/icp_target_feature.ll
+21-0llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
+82-02 files

LLVM/project b907c14clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR][NFC] Rename SignBitOp to CIR_SignBitOp (#195477)

Align with the CIR_ prefix naming convention used by other op
definitions in CIROps.td.
DeltaFile
+1-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+1-11 files

LLVM/project 81bdba1mlir/docs/Traits _index.md, mlir/include/mlir/IR OpDefinition.h OpBase.td

[MLIR] Add HasAncestor op trait (#195447)

Add HasAncestor/AncestorOneOf traits that verify an operation has a
specific ancestor anywhere in the parent chain, unlike HasParent which
only checks the immediate parent.
DeltaFile
+79-0mlir/test/IR/traits.mlir
+26-0mlir/include/mlir/IR/OpDefinition.h
+10-0mlir/docs/Traits/_index.md
+9-0mlir/test/lib/Dialect/Test/TestOps.td
+8-0mlir/include/mlir/IR/OpBase.td
+132-05 files

FreeBSD/src 89b9793usr.sbin/bsdinstall Makefile FreeBSD-base.conf.in

bsdinstall: Always use pkg.FreeBSD.org

The FreeBSD-base bits are accessible via pkg.FreeBSD.org, even for
releases, so there is no need to point at pkgbase.FreeBSD.org.

MFC after:      3 days
DeltaFile
+1-5usr.sbin/bsdinstall/Makefile
+1-1usr.sbin/bsdinstall/FreeBSD-base.conf.in
+2-62 files

NetBSD/pkgsrc jTtkksHdevel/ccache distinfo Makefile

   ccache: updated to 4.13.6

   Ccache 4.13.6

   Bug fixes and improvements

   Fixed a potential manifest/result cache key collision in MSVC depend mode when compiling a source file with no included files.

   Improved robustness when parsing cache entry data structures.

   Test improvements

   Changed the remote_helper test suite to skip gracefully when the storage test helper is unavailable, avoiding failures when testing a system-installed ccache.
VersionDeltaFile
1.76+4-4devel/ccache/distinfo
1.96+2-2devel/ccache/Makefile
+6-62 files

FreeBSD/ports 56d8471misc/zoneinfo distinfo Makefile

misc/zoneinfo: update to 2026b

Release 2026b - 2026-04-22 23:06:43 -0700

Changes: https://github.com/eggert/tz/blob/2026b/NEWS

Briefly:
  British Columbia moved to permanent -07 on 2026-03-09.

Approved by:    skreuzer (maintainer)
MFH:            2026Q2

(cherry picked from commit 5faca35f7b2f1c3503aeeccb6d54dbdd82df6479)
DeltaFile
+3-3misc/zoneinfo/distinfo
+1-1misc/zoneinfo/Makefile
+4-42 files

LLVM/project 00562c5mlir/lib/CAPI/Interfaces CMakeLists.txt

fix libMLIRCAPIInterfaces after #195505 (#195789)

https://github.com/llvm/llvm-project/pull/195505 missed
`MLIRSideEffectInterfaces` in the CMakeLists.txt.
DeltaFile
+2-1mlir/lib/CAPI/Interfaces/CMakeLists.txt
+2-11 files

LLVM/project 2d5abf3orc-rt/lib/executor/sps-ci MemoryAccessSPSCI.cpp SimpleNativeMemoryMapSPSCI.cpp, orc-rt/unittests MemoryAccessSPSCITest.cpp SimpleNativeMemoryMapSPSCITest.cpp

[orc-rt] Change SPS controller-interface naming conventions. (#195614)

This commit makes two changes to the naming conventions for SPS CI
symbols:

1. The orc_rt_sps_ci_ prefix is replaced with orc_rt_ci_sps_ (for SPS
wrapper functions) and orc_rt_ci_ (without the "sps_" suffix) for data
symbols.

2. The _sps_wrapper suffix is dropped from wrapper functions, since the
prefix now distinguishes between SPS-wrappers and data symbols.
DeltaFile
+28-28orc-rt/lib/executor/sps-ci/MemoryAccessSPSCI.cpp
+26-26orc-rt/unittests/MemoryAccessSPSCITest.cpp
+16-21orc-rt/lib/executor/sps-ci/SimpleNativeMemoryMapSPSCI.cpp
+8-13orc-rt/unittests/SimpleNativeMemoryMapSPSCITest.cpp
+8-9orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
+6-6orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
+92-1033 files not shown
+102-1139 files

LLVM/project 23b330dclang/include/clang/Options Options.td, flang/test/Driver print-file-name.f90

Enable -print-file-name for flang
DeltaFile
+13-0flang/test/Driver/print-file-name.f90
+1-1clang/include/clang/Options/Options.td
+0-0flang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/x86_64-unknown-linux-gnu/libflang_rt.runtime.a
+0-0flang/test/Driver/Inputs/resource_dir/share/asan_ignorelist.txt
+14-14 files

NetBSD/pkgsrc EilsCwUdoc CHANGES-2026

   doc: Updated audio/fasttracker2 to 2.19
VersionDeltaFile
1.2797+2-1doc/CHANGES-2026
+2-11 files

FreeBSD/ports 5faca35misc/zoneinfo distinfo Makefile

misc/zoneinfo: update to 2026b

Release 2026b - 2026-04-22 23:06:43 -0700

Changes: https://github.com/eggert/tz/blob/2026b/NEWS

Briefly:
  British Columbia moved to permanent -07 on 2026-03-09.

Approved by:    skreuzer (maintainer)
MFH:            2026Q2
DeltaFile
+3-3misc/zoneinfo/distinfo
+1-1misc/zoneinfo/Makefile
+4-42 files

NetBSD/pkgsrc 3wdMawbaudio/fasttracker2 distinfo Makefile

   audio/fasttracker2: Update to 2.19

   Changes since 2.18:

   v2.19 - 03.05.2026
     * Set audio input/output device to default during config reset
     * If audio input device was set to default, properly open default
       audio input device before sampling audio.
VersionDeltaFile
1.134+4-4audio/fasttracker2/distinfo
1.150+2-2audio/fasttracker2/Makefile
+6-62 files

LLVM/project 227c3e4libcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,931 files not shown
+72,117-31,8281,937 files

NetBSD/src KD4gVugsys/arch/m68k/m68k pmap_68k.c

   In pmap_bootstrap1(), check to see if FIXEDVA entries in machine_bootmap[]
   are covered by any existing page table range, and if not, allocate additional
   page table ranges to cover them.

   This does not impact the one current user of FIXEDVA -- hp300 -- which
   uses it to map the last page of RAM VA==PA.  In the hp300 case, this
   was already covered by the PTs that map the alternate SYSMAP_VA that
   the hp300 uses (precisely because it needs the last VA==PA mapping).

   This will eventually be used to map the I/O region VA==PA for mac68k.
   Normally, we might otherwies use a TT register for that, but mac68k
   runs on 68020s, so we cannot.
VersionDeltaFile
1.58+58-12sys/arch/m68k/m68k/pmap_68k.c
+58-121 files

LLVM/project 808b2dblibcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,932 files not shown
+72,119-31,8301,938 files

LLVM/project 3975cdblibcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,932 files not shown
+72,119-31,8301,938 files

LLVM/project 85c92d4libcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,925 files not shown
+72,039-31,8241,931 files

LLVM/project 4059891lld/ELF/Arch TargetImpl.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+1-1lld/ELF/Arch/TargetImpl.h
+1-11 files

LLVM/project 4448636llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize BUILD.gn, llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer BUILD.gn

[gn build] Port cb2a64e7e5af



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/195783
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn
+2-02 files

LLVM/project 8c8e053llvm/lib/CodeGen TargetInstrInfo.cpp, llvm/lib/Target/RISCV RISCVInstrInfo.h

[X86][APX] Add VirtRegMap to non stack foldMemoryOperand too (#193423)

We need to query mapped physical register through VirtRegMap.

Fixes: https://godbolt.org/z/1KGj3aYeP
DeltaFile
+270-0llvm/test/CodeGen/X86/apx/memfold-no-physreg.ll
+6-5llvm/lib/Target/X86/X86InstrInfo.h
+6-5llvm/lib/Target/RISCV/RISCVInstrInfo.h
+5-6llvm/lib/CodeGen/TargetInstrInfo.cpp
+6-5llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+6-4llvm/lib/Target/X86/X86InstrInfo.cpp
+299-256 files not shown
+311-3412 files

OpenBSD/src nGuTtSmusr.bin/openssl speed.c

   openssl: centralize speed benchmark timer handling

   The speed benchmark currently arms alarm() from print_message() and
   pkey_print_message(), making the output helpers also control benchmark
   lifetime. This hidden coupling makes the code harder to maintain and led to
   missing alarm cleanup on Windows, as reported in #1245.

   Move alarm setup and run-state initialization into speed-specific timer
   helpers so benchmark timing is controlled explicitly at the start and stop
   points.

   ok tb joshua
VersionDeltaFile
1.53+135-124usr.bin/openssl/speed.c
+135-1241 files

FreeBSD/ports 9672479databases/py-redisvl distinfo Makefile

databases/py-redisvl: Update to 0.18.1

Changelog: https://github.com/redis/redis-vl-python/releases/tag/v0.18.1

Reported by:    portscout
DeltaFile
+3-3databases/py-redisvl/distinfo
+2-2databases/py-redisvl/Makefile
+5-52 files

LLVM/project 7c2c06cmlir/include/mlir-c Interfaces.h, mlir/lib/Bindings/Python IRInterfaces.cpp

[MLIR][Python] Add `ConditionallySpeculatable` interface and `Pure` specifier (#195505)

This PR brings two features: the `ConditionallySpeculatable` op
interface and the `Pure` specifier for Python-defined ops.

The result is that you can mark an op as pure like:
```python
class PureOp(
    TestPure.Operation,
    name="pure",
    traits=[Pure]  # just like in the ODS!
):
    a: Operand[IntegerType[32]]
    b: Operand[IntegerType[32]]
    res: Result[IntegerType[32]] = infer_result()
```

Then this op is both `NoMemoryEffect` and `AlwaysSpeculatable`.

Assisted-by: Copilot/GPT5.4
DeltaFile
+116-0mlir/test/python/dialects/ext.py
+99-0mlir/test/CAPI/ir.c
+97-0mlir/lib/CAPI/Interfaces/Interfaces.cpp
+77-1mlir/lib/Bindings/Python/IRInterfaces.cpp
+43-0mlir/include/mlir-c/Interfaces.h
+20-0mlir/python/mlir/dialects/ext.py
+452-11 files not shown
+453-17 files

FreeBSD/ports 2f56601biology/iqtree/files patch-terraphast_lib_clamped__uint.cpp

biology/iqtree: Fix build with clang 21

Fix build by removing redundant instantiations of function templates in
terraphast/lib/clamped_uint.cpp.

Sponsored by:   The FreeBSD Foundation
DeltaFile
+17-0biology/iqtree/files/patch-terraphast_lib_clamped__uint.cpp
+17-01 files

LLVM/project 040c2b2llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port f7329e61ad4b



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/195782
DeltaFile
+0-1llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+0-11 files

LLVM/project 852dd0dllvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port be8e0842a103



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/195781
DeltaFile
+0-1llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+0-11 files

FreeBSD/ports 9949231misc/py-huggingface-hub distinfo Makefile

misc/py-huggingface-hub: Update to 1.13.0

Changelog:
- https://github.com/huggingface/huggingface_hub/releases/tag/v1.12.2
- https://github.com/huggingface/huggingface_hub/releases/tag/v1.13.0

Reported by:    Repology
DeltaFile
+3-3misc/py-huggingface-hub/distinfo
+1-1misc/py-huggingface-hub/Makefile
+4-42 files

LLVM/project 239ca8dllvm/docs LangRef.rst, llvm/lib/AsmParser LLParser.cpp

[IR] Add elementwise modifier to atomicrmw (#189517)

This PR implements the IR side modifications of [[RFC] Add elementwise
modifier to atomicrmw](https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomicrmw/90134).

Design Decisions:

- In the IR, the current atomicrmw record layout looks like: [ptrty,
ptr, valty, val, operation, vol, ordering, syncscope, align]. To encode
elementwise, I decided to pack it into the operation field, which also
contains the math op (i.e. fadd, fmin, add etc...). I could have changed
the record structure, but that would be slightly more complicated.
- elementwise vector atomics can be vectors of integers because we can always scalarize legally
- elementwise vector atomics need to have power of 2 size. We can potentially remove this restriction later.

Assisted by AI.
DeltaFile
+101-1llvm/unittests/IR/VerifierTest.cpp
+69-27llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+31-18llvm/lib/AsmParser/LLParser.cpp
+33-0llvm/test/Assembler/invalid-atomicrmw-elementwise.ll
+11-9llvm/docs/LangRef.rst
+14-4llvm/lib/IR/Verifier.cpp
+259-5913 files not shown
+334-7619 files

LLVM/project a80d2a7llvm/lib/Passes PassBuilderPipelines.cpp, llvm/test/Other new-pm-defaults.ll new-pm-thinlto-postlink-pgo-defaults.ll

Reapply "[JTS][Passes] Enable JTS By Default" (#193409)" (#195776)

This reverts commit c74951c6c3074be23fd7b12843e1187ca98e98af.

The ASan issues on the buildbot should be fixed by
b5f4f16fd98cb57a13a96b7d7faa89326636c5bc.
DeltaFile
+1-5llvm/test/Other/new-pm-defaults.ll
+2-2llvm/lib/Passes/PassBuilderPipelines.cpp
+1-0llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
+1-0llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
+1-0llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
+1-0llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
+7-72 files not shown
+9-78 files

LLVM/project e37ca02compiler-rt/test/asan/TestCases asan_and_llvm_coverage_test.cpp

[compiler-rt] Add MSVC CRT flags to ASan coverage test (#195719)

The ASan coverage test also links clang_rt.profile because it uses
-coverage. On Windows MSVC, this can fail if the test is linked with the
static CRT but clang_rt.profile was built with the dynamic CRT.

For example, a profile runtime that uses /MD may reference DLL CRT
symbols
such as __imp_* symbols. Add the same dynamic CRT flags directly to this
one test on Windows MSVC so it keeps linking when clang_rt.profile
changes.
DeltaFile
+5-1compiler-rt/test/asan/TestCases/asan_and_llvm_coverage_test.cpp
+5-11 files