[AArch64][SVE] Use multi-vector spill/fill instructions in pseudo expansion
SVE tuple spill/fill pseudos (STR_ZZXI, LDR_ZZZZXI, etc.) currently expand into
N individual STR_ZXI/LDR_ZXI instructions. On targets with SVE2.1 or SME2 we can
directly generate a ptrue + multi-vec op. For the x2 case this is neutral in
code size but can still be beneficial depending on your uarch. I'm going to
assume this is a generally good thing for now.
rdar://168475826
[Utils] Add --use-gh-cli-token flag
This enables automatically getting the token from the gh CLI tool which
was a requested feature.
Reviewers: petrhosek, ilovepi
Reviewed By: petrhosek, ilovepi
Pull Request: https://github.com/llvm/llvm-project/pull/186695
[llvm-remarkutil] filter: Add --sort and --dedupe flags (#187338)
Add `--sort` to emit remarks in sorted order and `--dedupe` to
deduplicate identical remarks. Only if these options are requested,
remarks need to be buffered into a sorted map before emission.
Pull Request: https://github.com/llvm/llvm-project/pull/187338
[AArch64][SVE] Use multi-vector spill/fill instructions in pseudo expansion
SVE tuple spill/fill pseudos (STR_ZZXI, LDR_ZZZZXI, etc.) currently expand into
N individual STR_ZXI/LDR_ZXI instructions. On targets with SVE2.1 or SME2 we can
directly generate a ptrue + multi-vec op. For the x2 case this is neutral in
code size but can still be beneficial depending on your uarch. I'm going to
assume this is a generally good thing for now.
rdar://168475826
[NewPM] Adds a port for AArch64ExpandPseudo (#187332)
Adds a port for AArch64ExpandPseudo to NewPM.
- Refactored lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp to extract
base logic as Impl
- Renamed existing pass with "Legacy" suffix and updated references
- Added NewPM pass AArch64ExpandPseudoPass
- Updated tests
Following tests mention this pass but weren't migrated because they need
a full codegen pipeline which doesn't exist yet.
```
LLVM :: CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
LLVM :: CodeGen/AArch64/addg_subg.mir
LLVM :: CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
LLVM :: CodeGen/AArch64/spillfill-sve.mir
LLVM :: CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir
```