LLVM/project 9854532utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[Bazel] Remove WinHTTP from LLVMSupport link options (#218182)

LLVMSupport has no WinHTTP API references and CMake does not link it
with WinHTTP.
DeltaFile
+0-3utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+0-31 files

LLVM/project 8939dd7llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp, llvm/test/CodeGen/AArch64 fcvt-fixed.ll

Rebase

Created using spr 1.3.7
DeltaFile
+1,217-1,125llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+853-1,375llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
+815-788llvm/test/CodeGen/AMDGPU/bypass-div.ll
+753-757llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
+376-1,106llvm/test/CodeGen/AArch64/fcvt-fixed.ll
+17-1,275llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+4,031-6,426348 files not shown
+20,010-13,464354 files

LLVM/project 8da070dutils/bazel/llvm-project-overlay/llvm config.bzl, utils/bazel/llvm-project-overlay/llvm/include/llvm/Config config.h

[Bazel] Configure macOS Support capabilities (#218186)

Match CMake and LLVM GN for 3 macOS capablities.

These are safe to assume because these are invariants of the macOS SDK
and Darwin: arc4random is declared, the __crashreporter_info__
annotation is supported, and struct stat exposes st_mtimespec.tv_nsec.
DeltaFile
+12-3utils/bazel/llvm-project-overlay/llvm/config.bzl
+2-2utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
+14-52 files

LLVM/project 0c706f8clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/test/CIR/Transforms/abi-lowering x86_64-aggregate-nyi.cir x86_64-incomplete-record-declaration.cir

[CIR] Skip ABI classification for an incomplete-record declaration

A `cir.func` declaration whose signature carries an incomplete record
by value caused the pass to fail the whole module.

C++ requires a complete type at any call or definition, so only a declaration
can carry this shape, and no translation unit anywhere can ever call or define
it with real argument data.  Classic CodeGen skips full ABI lowering rather than
attempting one.  We now leave such a declaration unclassified and match classic.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+54-0clang/test/CIR/Transforms/abi-lowering/x86_64-incomplete-record-declaration.cir
+23-0clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+10-0clang/test/CIR/Transforms/abi-lowering/x86_64-aggregate-nyi.cir
+87-03 files

LLVM/project 0905c44flang/lib/Semantics check-acc-structure.cpp, flang/test/Lower/OpenACC acc-loop.f90 acc-serial-loop.f90

[flang][OpenACC] Reject valued gang/worker/vector outside kernels (#218695)

`gang(num:)`, `worker(n)`, and `vector(n)` are only valid on a loop
associated with kernels, and then only if that kernels construct does
not already specify `num_gangs`, `num_workers`, or `vector_length`.
DeltaFile
+513-0flang/test/Semantics/OpenACC/acc-loop-vector-value.f90
+119-1flang/lib/Semantics/check-acc-structure.cpp
+6-76flang/test/Lower/OpenACC/acc-parallel-loop.f90
+6-74flang/test/Lower/OpenACC/acc-serial-loop.f90
+22-6flang/test/Lower/OpenACC/acc-loop.f90
+21-0flang/test/Semantics/OpenACC/acc-loop.f90
+687-1572 files not shown
+697-1578 files

FreeBSD/ports 2a6ef48math/octave-forge-mqtt Makefile

math/octave-forge-mqtt: Bump PORTREVISION. net/libpaho-mqtt3 was updated to 1.3.16
DeltaFile
+1-1math/octave-forge-mqtt/Makefile
+1-11 files

FreeBSD/ports cc01218net/libpaho-mqtt3 Makefile distinfo

net/libpaho-mqtt3: Update to 1.3.16
DeltaFile
+4-4net/libpaho-mqtt3/pkg-plist
+3-3net/libpaho-mqtt3/distinfo
+1-1net/libpaho-mqtt3/Makefile
+8-83 files

GhostBSD/build edf2d09. build.sh

Stop shipping /etc/wall_cmos_clock in the image

The file makes the kernel read the RTC as local time, so the clock is
off by one UTC offset on any machine whose RTC keeps UTC. That applied
to the live session and to every install, since the install is a cpdup
of the live system and nothing in the installer revisited the file.

pc-sysinstall now creates or removes it from the utcClock= config key,
so the image no longer has to pick a side, and the live session gets a
correct clock while the installer is running. Machines that really do
keep local time in the RTC, which in practice means dual-booting
Windows, are handled by the installer front-end instead.

Resolves: ghostbsd/issues#390

Claude-Session: https://claude.ai/code/session_017h6mzC2bNskrWN2bHoYLzs
DeltaFile
+0-2build.sh
+0-21 files

LLVM/project 67c58e9llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 abd-combine.ll

DAG: Fix null dereference in visitABD for poison constant elements (#218766)

visitABD calls ISD::matchUnaryPredicate with AllowUndefs=true, which
passes a null ConstantSDNode to the predicate lambda for each undef or
poison element.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+17-0llvm/test/CodeGen/AArch64/abd-combine.ll
+2-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+19-02 files

FreeBSD/ports f2d0c8dmisc/mmv distinfo Makefile, misc/mmv/files patch-Makefile.am patch-bootstrap

misc/mmv: use upstream release abd clean up port

Use upstream release archive as recommended by Porters Handbook and
clean up port

PR:             297921
Reported by:    diizzy
DeltaFile
+0-20misc/mmv/files/patch-bootstrap
+5-13misc/mmv/Makefile
+0-11misc/mmv/files/patch-Makefile.am
+3-3misc/mmv/distinfo
+8-474 files

LLVM/project 1fc48e7flang/include/flang/Optimizer/Builder/Runtime Assign.h, flang/lib/Optimizer/Builder/Runtime Assign.cpp

[flang] - Call _FortranAAssignSimple instead of _FortranAAssign for intrinsic-type array assignments (#213705)

This patch adds support for calling _FortranAAssignSimple, a faster-path
for array assignments. `_FortranAAssignSimple` is called when ALL the
following conditions are true:
1. Intrinsic element type (not derived type)
2. Matching ranks (no scalar-to-array broadcasting)
3. Non-volatile
4. Not polymorphic
5. Not explicit-length character
6. Not temporary LHS

Otherwise, uses `_FortranAAssign` (or specialized variants like
`_FortranAAssignPolymorphic`, `_FortranAAssignExplicitLengthCharacter`).

This is the final part of the fix for
https://github.com/llvm/llvm-project/issues/203915

---------

Co-authored-by: Claude Opus 4 (1M context) <noreply at anthropic.com>
DeltaFile
+300-0flang/test/HLFIR/assign-simple-routing.fir
+32-4flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
+19-13flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
+13-0flang/lib/Optimizer/Builder/Runtime/Assign.cpp
+12-0flang/include/flang/Optimizer/Builder/Runtime/Assign.h
+2-2flang/test/HLFIR/assign-codegen.fir
+378-192 files not shown
+380-218 files

LLVM/project f1e48e0mlir/include/mlir/IR OpDefinition.h, mlir/test/Conversion/MemRefToEmitC memref-to-emitc-alloc-dealloc.mlir

[MLIR][ODS] Print prop-dict fields with custom printers

Generate a key-value prop-dict printer that dispatches each field to its ODS
printer while retaining attribute conversion for non-compositional default
parsers.

Keep operation-specific property printer hooks ahead of the generated
implementation and preserve legacy input compatibility.

Update the OpenACC cache checks for the generated custom property spelling.

Assisted-by: Codex
DeltaFile
+134-4mlir/tools/mlir-tblgen/OpFormatGen.cpp
+23-15mlir/test/IR/properties.mlir
+32-0mlir/test/mlir-tblgen/op-format-custom-properties-printer.td
+14-14mlir/test/Dialect/LLVMIR/rocdl.mlir
+19-3mlir/include/mlir/IR/OpDefinition.h
+8-8mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
+230-4424 files not shown
+320-10330 files

FreeBSD/ports 7afde95devel/py-time-machine Makefile distinfo

devel/py-time-machine: Update to 3.5.0

Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+3-3devel/py-time-machine/distinfo
+1-1devel/py-time-machine/Makefile
+4-42 files

LLVM/project 74f3e7bllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv masked-load-vl-predicatable.ll

[RISCV] Add additional conditions for signed icmp cases when canonicalizing masks for VL-predicate (#218068)

Fixes #217500 

Previously in #214877 we added a mask canonicalization to make it easier
for the mask-consuming instructions to use VL-predicated instead. But
the transformation will be incorrect if the icmp against boundary value
is signed. Specifically, the problem arises if `%base + %offset` is
negative. This patch fixes this issue by guarding `%base + %offset` to
ensure this expression (1) never overflow, and (2) is non-negative.

Alive2 Proof: https://alive2.llvm.org/ce/z/L2M_LL
DeltaFile
+46-19llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+29-4llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
+75-232 files

LLVM/project 4e5ba05clang/test/CIR/CodeGen record-type-metadata.cpp vtable-linkage-explicit-instantiation.cpp, clang/test/CIR/CodeGenCXX typeid-most-derived.cpp

[CIR] Drop the callconv opt-out from 4 more CIR tests

These four CIR tests now compile and check clean with x86_64 calling-convention
lowering on, unblocked by the packed-record (#218505) and vptr-record (#218457)
work.  Stripping the flag moved zero CHECK lines: the output the pass produces
for these four is exactly what was already pinned.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+2-4clang/test/CIR/CodeGenCXX/typeid-most-derived.cpp
+2-4clang/test/CIR/CodeGen/vtable-linkage-explicit-instantiation.cpp
+2-4clang/test/CIR/CodeGen/trivial-abi.cpp
+1-4clang/test/CIR/CodeGen/record-type-metadata.cpp
+7-164 files

FreeBSD/ports 706b9bfsysutils/vttest Makefile distinfo

sysutils/vttest: Update to 2025.12.05
DeltaFile
+3-3sysutils/vttest/distinfo
+2-2sysutils/vttest/Makefile
+5-52 files

FreeNAS/freenas 506f86csrc/middlewared/middlewared/utils/lio config.py

Run ALUA group cleanup in finally so a sibling render failure can't skip it
DeltaFile
+22-20src/middlewared/middlewared/utils/lio/config.py
+22-201 files

FreeBSD/src f86c3e6tools/tools/git git-arc.1 git-arc.sh

git-arc: Handle -h on subcommands and align usage with the man page

git-sh-setup treats -h as help against an empty USAGE, so
"git arc create -h" prints "usage: git arc". Handle -h before
sourcing it so every subcommand prints the real synopsis.

The create, stage, and update synopses showed optional commit-refs
while git-arc(1) and the code require them. Advertise -p parent on
create; the option was already implemented and documented.

Sort create sub-command option-arguments alphabetically in three
places: (1) synopsis from tool, (2) man-page synopsis, and (3)
man-page description.

Check for jq(1) / arc after checking for usage so -h always works.

While here, fix missing "local o" in gitarc__stage().

Reviewed by:    markj
Differential Revision:  https://reviews.freebsd.org/D59129
DeltaFile
+149-60tools/tools/git/git-arc.sh
+16-11tools/tools/git/git-arc.1
+165-712 files

NetBSD/src 7F9f5YEsys/arch/riscv/conf GENERIC64, sys/arch/riscv/starfive files.starfive jh7110_wdt.c

   risc-v: Add a driver for the jh7110 watchdog timer

   ok skrll@
VersionDeltaFile
1.1+262-0sys/arch/riscv/starfive/jh7110_wdt.c
1.13+6-1sys/arch/riscv/starfive/files.starfive
1.28+2-1sys/arch/riscv/conf/GENERIC64
+270-23 files

LLVM/project bb22b22mlir/include/mlir/IR OpDefinition.h DialectImplementation.h, mlir/test/IR properties-invalid.mlir properties.mlir

[MLIR][ODS] Parse prop-dict fields with custom parsers

Teach generated operation parsers to accept a key-value spelling for
prop-dict and dispatch known fields through their ODS parsers. Keep the
DictionaryAttr spelling as a compatibility path and use attribute
conversion when a property has no usable FieldParser.

Exercise FieldParser specialization dispatch with an existing test-dialect
storage type so incremental and sharded builds regenerate the operation code
that selects it.

See #155475

Assisted-by: Codex
DeltaFile
+225-0mlir/test/lib/Dialect/Test/TestOps.td
+218-0mlir/tools/mlir-tblgen/OpFormatGen.cpp
+94-1mlir/test/IR/properties.mlir
+76-4mlir/include/mlir/IR/DialectImplementation.h
+79-0mlir/test/IR/properties-invalid.mlir
+18-4mlir/include/mlir/IR/OpDefinition.h
+710-96 files not shown
+763-1312 files

LLVM/project cc7e50fmlir/include/mlir/Dialect/WasmSSA/IR WasmSSABase.td WasmSSAOps.td, mlir/test/Conversion/RaiseWasm wasm-func-to-func.mlir

[MLIR][WasmSSA] Enable strict property assembly format (#217285)

Enable the strict properties assembly format mode for the WasmSSA
dialect. Spell import operation type and limit metadata directly in the
assembly formats so those inherent attributes are not parsed from
attr-dict in strict mode.

Assisted-by: Codex
DeltaFile
+8-8mlir/test/Dialect/WasmSSA/custom_parser/import.mlir
+4-4mlir/test/Target/Wasm/import.mlir
+5-3mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAOps.td
+1-1mlir/test/Target/Wasm/add_div.mlir
+1-1mlir/test/Conversion/RaiseWasm/wasm-func-to-func.mlir
+1-0mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSABase.td
+20-176 files

FreeBSD/ports ac7047dwww/firefox Makefile, www/firefox/files patch-enable-webserial

www/firefox: a shot at enabling WebSerial

PR:                                     297874
Submitted by:           pcc

(cherry picked from commit 0074ee3b2ea7d87a02a6a3c345ddb0e634367675)
DeltaFile
+73-0www/firefox/files/patch-enable-webserial
+1-0www/firefox/Makefile
+74-02 files

FreeBSD/ports 0074ee3www/firefox Makefile, www/firefox/files patch-enable-webserial

www/firefox: a shot at enabling WebSerial

PR:                                     297874
Submitted by:           pcc
DeltaFile
+73-0www/firefox/files/patch-enable-webserial
+1-0www/firefox/Makefile
+74-02 files

LLVM/project ac0b990llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/AArch64 partial-reduce-with-predicate.ll partial-reduce-fold-tail.ll

[LV] Mask all links of a partial-reduction chain when tail-folding. (#215875)

transformToPartialReduction takes the reduction's mask from the
tail-folding select (select(mask, update, phi)), which by construction
only exists for the link that is the reduction's exit value. Links
earlier in the chain currently partially accumulate unconditionally.

If any lanes are masked off by tail-folding, the masked off value
(usually poison) propagates to active lanes, poisoning the result.

IIUC this is currently benign on SVE today, where ld1b p/z zeroes the
inactive lanes, but it is unsound at the IR level and does not hold for
targets whose masked loads leave the tail undisturbed.

Fall back to the header mask for the remaining links.

PR: https://github.com/llvm/llvm-project/pull/215875
DeltaFile
+4-2llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fold-tail.ll
+6-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-1llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-with-predicate.ll
+12-33 files

NetBSD/pkgsrc-wip f264ef1crush Makefile COMMIT_MSG

crush: Update to 0.91.1
DeltaFile
+117-117crush/distinfo
+38-38crush/go-modules.mk
+11-9crush/COMMIT_MSG
+1-1crush/Makefile
+167-1654 files

FreeBSD/src 90ed365tools/tools/git git-arc.sh

git-arc: Fix inconsistent whitespace

Reviewed by:    markj
Differential Revision:  https://reviews.freebsd.org/D59161
DeltaFile
+3-3tools/tools/git/git-arc.sh
+3-31 files

NetBSD/pkgsrc-wip baef14dyamusic-tui-git DESCR COMMIT_MSG, yamusic-tui-git/files README.pkgsrc

yamusic-tui-git: Add git package for yamusic-tui

yamusic-tui is a terminal user interface for the YAMusic music
server. It provides browsing and searching of the library,
playback with progress and volume control, lyrics display, and
playlist management, all from within a terminal.
DeltaFile
+284-0yamusic-tui-git/distinfo
+95-0yamusic-tui-git/go-modules.mk
+31-0yamusic-tui-git/Makefile
+10-0yamusic-tui-git/files/README.pkgsrc
+7-0yamusic-tui-git/DESCR
+7-0yamusic-tui-git/COMMIT_MSG
+434-01 files not shown
+437-07 files

LLVM/project f3571f8mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp, mlir/test/Dialect/LLVMIR inlining-alias-scopes.mlir

[mlir][LLVM] Use a disjoint scope domain when inlining noalias

This matches recent changes to the LLVM inliner.

AI disclosure: Claude wrote the code, I wrote the commit message and
have done initial review.
DeltaFile
+28-25mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+10-18mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
+38-432 files

LLVM/project 9caf31fmlir/include/mlir/Dialect/LLVMIR LLVMAttrDefs.td, mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp

[mlir][LLVM] Add disjointScopes to AliasScopeDomainAttr

This also updates the MLIR-side inliner to clone disjoint domains
while cloning alias scopes, matching changes to LLVM.

AI disclosure: Claude wrote the code, I wrote the commit message and
looked at the code.
DeltaFile
+34-5mlir/test/Target/LLVMIR/Import/metadata-alias-scopes.ll
+36-1mlir/test/Target/LLVMIR/Import/import-failure.ll
+23-0mlir/test/Target/LLVMIR/attribute-alias-scopes.mlir
+17-2mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+4-2mlir/lib/Target/LLVMIR/ModuleImport.cpp
+4-1mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+118-111 files not shown
+120-137 files

LLVM/project a3ac931llvm/lib/Target/AMDGPU AMDGPULowerModuleLDSPass.cpp, llvm/test/CodeGen/AMDGPU lower-lds-struct-aa-memcpy.ll remove-no-kernel-id-attribute.ll

[AMDGPU] Use a disjoint scope domain for merged LDS structs

When lowering LDS values, all the values are mutually disjoint, so we
can use the newly-added disjoint scopes feature to simplify the IR.

AI disclosure: Claude wrote this and I reviewed it and wrote the
 commit message
DeltaFile
+15-52llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+35-10llvm/test/CodeGen/AMDGPU/lower-module-lds-precise-allocate-to-module-struct.ll
+15-18llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
+11-13llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
+8-12llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
+9-10llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
+93-1156 files not shown
+139-16112 files