[AArch64] Adjust cost for min/max intrinsics using v2i8 and v2i16 (#212801)
When vectorizing min/max intrinsics with these types, using the changes
in #195823, the Type Promotion cost outweighs that of leaving the loop
as Scalar. The costs need to be adjusted to account for the promotion
costs to ensure loops of this kind will continue to be scalar.
[LV] Convert scatter stores with constant stride into strided stores (#206896)
Following up on #147297, this patch converts scatter accesses with a
constant stride into strided stores within convertToStridedAccesses.
Fixed #206662
[Clang] Add tests for ref-qualified operator new (#215644)
This adds test coverage for ref-qualified operator new declarations.
Adds regression tests for lvalue (&) and rvalue (&&) ref qualifiers
mentioned in issue #102422.
Fixes #102422
[AArch64][SDAG] Enable +sve2p2/+sme2p2 lowerings for VECTOR_COMPRESS (#215219)
Enables the +sve2p2/+sme2p2 lowerings for `VECTOR_COMPRESS`, which
allows lowering the full range of legal types to `compact`.
[SandboxVectorizer] Fix out-of-bounds SeedBundle access on cross-bundle erasure
SeedCollection::runOnFunction() indexed a SeedBundle at
Seeds.getFirstUnusedElementIdx() (and, separately, at a hardcoded 0) without
first checking whether the bundle was already fully used.
getFirstUnusedElementIdx() returns Seeds.size() -- one past the end -- once
everything is used, so indexing there reads out of bounds.
This was always a latent bug, but -sbvec-collect-seeds=stores,loads is what
actually exposes it: store and load seeds share one erase-instruction
callback (SeedContainer::erase()), so when vectorizing a store chain erases
a load it packed as an operand, that erase also marks the same load "used"
in its *independent* LoadSeeds bundle. Store seeds are processed first, so
by the time the outer loop reaches that LoadSeeds bundle, it can already be
fully consumed -- or, since cross-bundle erasure can mark any index used
(not just sequentially from the front), have its element 0 specifically
erased while other elements remain live, which broke the hardcoded Seeds[0]
address-space lookup the same way.
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py-dnsdiag: updated to 2.9.4
2.9.4
Fixed
fix: reset shutdown flag at the start of each CLI invocation
fix(dnsping): validate source IP address family against -4/-6 flag
fix(dnsping): fix variable shadowing and div-by-zero in stats
fix(dnsping): reuse TCP connection for fixed source port queries
[compiler-rt] Partially enable building compiler-rt unit tests for spirv64 target (#215717)
Currently, compilation/linking error will happen for all compiler-rt
builtin unit test when building them for spirv64 target, there are a
bunch of problem to resolve, this patch is the 1st one aiming to resolve
following 2 problems in building phase:
1. fatal error: error in backend:
SPV_EXT_relaxed_printf_string_address_space is required because printf
uses a format string not in constant address space.
2. -lc/-lm flags are not recognized by spirv64 toolchain.
For 1, unit tests are plain C source files and use printf, the format
string is a C-string which is not decorated by any address space, so
need to apply SPV_EXT_relaxed_printf_string_address_space to allow it
for spirv64.
For 2, spirv64 toolchain has not supported to use static archive
library, so this -lc/-lm is not accepted by clang. So, we need to use
bitcode libc in device compilation phase via -mlink-builtin-bitcode.
Currently, we only link libc since libm spirv64 library has not been
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pciconf: Fix round-up logics for total sizes of bridge resources
The previous ones are valid only if alignments are 4K or 1M,
for I/O or memory, respectively.
[LoongArch] Fold shifted vector extract comparisons (#214204)
Fold comparisons of the form:
(shl (extract_vector_elt X, I), GRLen - EleBits) ==/!= 0
into:
(extract_vector_elt X, I) ==/!= 0
When the shift amount equals `GRLen - EleBits`, the left shift only
moves the extracted element into the most significant bits without
affecting whether the value is zero. This canonicalization exposes
EXTRACT_VECTOR_ELT to later combines and enables selecting VPICKVE2GR_*
instructions directly.
[clang][test] Cache failed stats in a unit test (#215969)
I'd like to remove the possibility of disabling caching of failures in
`FileManager`, and this test is one of the few users of that feature.
There's no reason to disable failure caching in the `FileManager` here.
pciconf: Fix alignments of device memory and I/O resources
Resources must be their-size-aligned. While here:
- Switch *align variable from int to more suitable integer types.
- Make some conditions clearer (NFC).
py-duckdb: Pass CMAKE_BUILD_PARALLEL_LEVEL.
Any package that uses py-scikit-build-core to build does not honour MAKE_JOBS.
Some packages use make and so are single threaded, but some like duckdb use
ninja, and that defaults to ncores+2(!) per build.
On my 72-core build host, building 3 py-duckdb packages simultaneously, this is
enough to completely swamp things and cause knock-on failures that effectively
kill the bulk build.
Ideally this needs to be done in a build.mk or similar for py-scikit-build-core
but this gets us past this for now.
[BOLT][RISCV] Fix conditional tail call (#209474)
When BOLT encounters an external-reference branch,
`BinaryFunction::handleExternalReference()` first calls
`convertJmpToTailCall()`. The RISC-V implementation previously bailed
out with unsupported tail call opcode. As a result, conditional branches
targeting external symbols could not be converted into (conditional)
tail calls. This patch adds the RISC-V conditional-tail-call machinery.
[PR #160042](https://github.com/llvm/llvm-project/pull/160042)
explicitly adds every conditional branch opcode to
`convertJmpToTailCall().` That causes the instruction to first receive
the regular `kTailCall` annotation.
The implementation here instead returns false for conditional branches
because this is already the protocol expected by the generic BOLT code:
1. handleExternalReference() calls convertJmpToTailCall().
2. If it returns false, BOLT verifies that the instruction is a
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[flang][AArch64] Pass large BIND(C) VALUE derived types indirectly (#215508)
AAPCS64 "Parameter passing rules" B.4 states: "If the argument type is a
Composite Type that is larger than 16 bytes, then the argument is copied
to memory allocated by the caller and the argument is replaced by a
pointer to the copy." (see:
https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#parameter-passing-rules)
Flang instead marked such an argument byval, which lets the target lower
it as a by-value aggregate placed in the argument stack area, so it
consumed no register. A C function that follows the standard expects a
pointer in that register, so the arguments no longer lined up and the
callee read the wrong value.
Add an indirect attribute to the argument marshalling and use it on
AArch64 for records that are too large to be passed in registers. Like
byval it makes the caller copy the value into a temporary and pass its
address, but it does not attach the byval attribute to the argument.
Records of 16 bytes or less, records passed on the stack because no
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[X86][GlobalISel] Map a store of an FP-banked load to the FP bank (#215371)
`G_LOAD` and `G_STORE` didn't agree when to select the FP regbank, which
inserted a PSR -> GPR copy, hitting a "FP register expected" assertion.
Apply the load's rule in the store case as well so the two agree.
Co-authored-by: Claude (Claude-Opus-5) <noreply at anthropic.com>
Update to meson-1.12.0.
Remove upstream change that passes fatal-warnings flag to the linker as this
would break half of the ports tree due to our:
warning: str*() is almost always misused, please use strl*()
becoming an error.
[orc-rt] Update orc_rt::sps_ci::addAll to include new SPS CI. (#215973)
sps_ci::addAll should add all SPS CI (Controller Interface) symbols to
the given map.
Update it to include recently added SPS CI (Calls, GDBJITRegistrar,
MemoryAccess, NativeDylibManager, and
StandaloneMachOUnwindInfoRegistrar)
