LLVM/project bdaf20bllvm/lib/Target/PowerPC PPCReduceCRLogicals.cpp

PowerPC: Use use_instr_nodbg_begin in PPCReduceCRLogicals (#219988)

Fetch the using instruction directly through the instruction iterator
instead of dereferencing an operand's parent.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+1-1llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
+1-11 files

LLVM/project 7a845cellvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU lit.local.cfg

add machine verifier check
DeltaFile
+84-3llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+2-0llvm/test/CodeGen/AMDGPU/lit.local.cfg
+89-33 files

LLVM/project eda5507llvm/test/CodeGen/AMDGPU flat-atomicrmw-fsub.ll flat-atomicrmw-fmin.ll

fix pattern
DeltaFile
+8,380-0llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
+1,481-1,527llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+12,029-5,90761 files not shown
+18,100-14,42367 files

LLVM/project 4c500c9llvm/test/CodeGen/AMDGPU fptoui-sat-scalar.ll usubsat.ll, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.raw.tbuffer.store.f16.ll

update test
DeltaFile
+154-269llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+146-218llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+106-170llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+123-131llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+42-89llvm/test/CodeGen/AMDGPU/usubsat.ll
+13-41llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+584-91813 files not shown
+718-1,10319 files

LLVM/project 3cc35d0llvm/test/CodeGen/AMDGPU global-atomicrmw-fadd.ll amdgcn.bitcast.128bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-llvm.amdgcn.image.sample.a16.ll

calling conv update
DeltaFile
+4,190-4,346llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,769-2,019llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+1,592-1,625llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+748-1,428llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+1,308-842llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,248-856llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+11,855-11,116166 files not shown
+32,303-24,896172 files

LLVM/project 1e72279llvm/test/CodeGen/AMDGPU fptoui-sat-vector.ll fptosi-sat-vector.ll

Legalize sgpr16 in sdag
DeltaFile
+2,231-2,790llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,231-2,790llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+1,527-1,576llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+1,324-1,324llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+213-220llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+139-146llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+7,665-8,84634 files not shown
+8,915-10,24440 files

LLVM/project 854a747llvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp, llvm/test/CodeGen/AMDGPU llvm.frexp.ll flat_atomics.ll

add more cases
DeltaFile
+53-35llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+46-38llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+40-39llvm/test/CodeGen/AMDGPU/flat_atomics.ll
+18-12llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
+18-12llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
+10-18llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
+185-15425 files not shown
+352-28731 files

LLVM/project e36563cllvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.xor.ll, llvm/test/CodeGen/AMDGPU/GlobalISel bswap.ll

Legalize sgpr16 copy in gisel
DeltaFile
+393-208llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+55-167llvm/test/CodeGen/AMDGPU/fptrunc.ll
+106-99llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
+70-127llvm/test/CodeGen/AMDGPU/minmax.ll
+39-70llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+38-70llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+701-74141 files not shown
+1,236-1,46847 files

LLVM/project cda89a5llvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.alignbyte.ll true16-fold.mir

fold sgpr32 via vgpr16
DeltaFile
+122-0llvm/test/CodeGen/AMDGPU/true16-fold.mir
+26-58llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+57-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+4-11llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
+212-741 files not shown
+213-767 files

LLVM/project 7650392llvm/lib/ExecutionEngine/Orc/TargetProcess LibraryResolver.cpp, llvm/lib/Passes CodeGenPassBuilder.cpp

[llvm] Remove unused includes (NFC) (#219915)

Identified by clang-tidy and verified with local builds.
DeltaFile
+0-7llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryResolver.cpp
+0-6llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
+0-6llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
+0-6llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+0-6llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+0-6llvm/lib/Passes/CodeGenPassBuilder.cpp
+0-37263 files not shown
+0-396269 files

LLVM/project 435344cllvm/lib/Target/NVPTX NVPTXISelLowering.h NVPTXInstrInfo.td, llvm/test/CodeGen/NVPTX machinelicm-no-preheader.mir

[NVPTX] Use MCSymbols in Isel, remove mutable StrPool (NFC) (#219530)

Using MCSymbols is more idiomatic and allows us to remove mutable
members from the TM and simplifies MFI data structures.
DeltaFile
+36-37llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+11-19llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
+14-8llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+14-8llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+8-8llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
+5-5llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+88-858 files not shown
+107-10714 files

FreeBSD/src 698f424. fix-xmltest-log.sh Changes, lib xmltok.h xmlparse.c

Vendor import of expat 2.8.4
DeltaFile
+189-64lib/xmlparse.c
+79-0tests/basic_tests.c
+65-0Changes
+57-1tests/misc_tests.c
+2-2lib/xmltok.h
+3-0fix-xmltest-log.sh
+395-678 files not shown
+403-7414 files

FreeBSD/src 037d45asys/dev/e1000 if_em.h if_igbv.c

igbv: Fence DMA while sanitizing retained queues

The 82576 and I350 retain VF queue enable and DMA address state
across VFLR.  iflib enables PCI bus mastering before driver attach, so
stale state left by a previous owner can otherwise issue DMA before
igbvf has completed its first reset and queue sanitization.

Disable PCI bus mastering immediately after mapping the VF BAR.  Keep
it disabled until reset and queue sanitization succeed, verify both
disable and enable through PCI command-register readback, and wait for
pending transactions before treating the fence as complete.
Resanitize on stop before iflib releases queue mappings.

The sanitizer and recovery were exercised on I350 and 82576 VFs.  Forced
queue-disable failure left the VF down, and a later administrative
down/up recovered it; successful I350 VFs passed bidirectional traffic
with no errors or drops.

Sponsored by:   BBOX.io
DeltaFile
+85-1sys/dev/e1000/if_em.c
+1-1sys/dev/e1000/if_igbv.c
+1-0sys/dev/e1000/if_em.h
+87-23 files

LLVM/project 7622da6llvm/lib/Target/Hexagon HexagonXQFloatGenerator.cpp

Hexagon: Use use_instructions in checkHVXUses32/checkHVXUses16

The loops only inspect the using instruction, so iterate instructions
directly instead of operands and their parents.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+4-6llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
+4-61 files

OpenBSD/src 3yHoUXLinclude unistd.h

   provide prototype for getexecpath(3)
   ok kettenis beck kirill
VersionDeltaFile
1.115+4-1include/unistd.h
+4-11 files

OPNSense/core f2815fasrc/opnsense/www/js/widgets Services.js, src/opnsense/www/js/widgets/Metadata Core.xml

system: minor touches on widget styles
DeltaFile
+10-5src/opnsense/www/js/widgets/Services.js
+2-2src/opnsense/www/js/widgets/Metadata/Core.xml
+12-72 files

LLVM/project edbf358flang/docs ReleaseNotes.md, flang/lib/Optimizer/Passes Pipelines.cpp

[flang] Enable FIR loop invariant code motion by default (#218703)

The FIR loop invariant code motion pass was added in #173438, where it
was disabled by default. This enables it for optimization levels above
`-O0`. The option `-disable-fir-licm` has been added in place of
`-enable-fir-licm`. The pass itself is unchanged.

Relates to #208086 and fixes #110613. Tests updated.

Assisted-by: Copilot
DeltaFile
+5-0flang/docs/ReleaseNotes.md
+1-2flang/test/Driver/tco-test-gen.fir
+3-0flang/test/Fir/basic-program.fir
+3-0flang/test/Driver/mlir-pass-pipeline.f90
+3-0flang/test/Driver/bbc-mlir-pass-pipeline.f90
+1-1flang/lib/Optimizer/Passes/Pipelines.cpp
+16-32 files not shown
+18-58 files

OpenBSD/src DQqaqcVdistrib/sets/lists/base mi

   sync
VersionDeltaFile
1.1196+2-2distrib/sets/lists/base/mi
+2-21 files

OpenBSD/src NG9XuYflib/libc shlib_version

   bump major after symbol addition & removal
VersionDeltaFile
1.228+1-1lib/libc/shlib_version
+1-11 files

OpenBSD/src PkSF9RGregress/lib/libc Makefile, regress/lib/libc/getexecpath Makefile getexecpath.c

   small regression test for getexecpath(3)
VersionDeltaFile
1.1+24-0regress/lib/libc/getexecpath/getexecpath.c
1.1+8-0regress/lib/libc/getexecpath/Makefile
1.65+2-2regress/lib/libc/Makefile
+34-23 files

OpenBSD/src PV5kuMGdistrib/sets/lists/comp mi

   sync
VersionDeltaFile
1.1766+1-0distrib/sets/lists/comp/mi
+1-01 files

LLVM/project d746736llvm/lib/Target/AMDGPU AMDGPU.td, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: Add visible features for aperture regs, doorbell ID and AGPR alloc

These fields are needed to migrate AMDGPUAttributor to using TargetParser
information instead of subtarget features.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+21-6llvm/lib/Target/AMDGPU/AMDGPU.td
+4-3llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+25-92 files

FreeBSD/ports 2a6f398lang/lfortran Makefile distinfo

lang/lfortran: upgrade to v0.65.0

Release notes at
        https://github.com/lfortran/lfortran/releases/tag/v0.65.0
DeltaFile
+3-3lang/lfortran/distinfo
+1-1lang/lfortran/Makefile
+4-42 files

FreeBSD/ports 3200107math/suitesparse bsd.suitesparse.mk Makefile, math/suitesparse-Example Makefile

math/suitesparse: upgrade to v7.14.0

Release notes at
        https://github.com/DrTimothyAldenDavis/SuiteSparse/releases/tag/v7.14.0

This upgrades GraphBLAS to 10.5.0.
DeltaFile
+3-3math/suitesparse/distinfo
+1-1math/suitesparse/bsd.suitesparse.mk
+1-1math/suitesparse/Makefile
+1-1math/suitesparse-graphblas/Makefile
+1-1math/suitesparse-Example/Makefile
+7-75 files

FreeBSD/ports e1e0157cad/pythonocc-core/files patch-src_SWIG__files_wrapper_StepFEA.pyi patch-src_SWIG__files_wrapper_StepAP214.pyi

cad/pythonocc-core: fix build with py-numpy-stl 4.0.0

Other modifications:
-added PORTREVISION to 1
-adapted package name "numpy_stl"
-added python flavors
-disable PORTSCOUT (see also https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=297592)
-added pkg-message (install)
-added missing patches from 1 upstream PR:
https://github.com/tpaviot/pythonocc-core/pull/1493/changes/eb52a64e7d82db2ea195b7842c4e5a76cac3c663
(Fix invalid OCCT 8.0.0 .pyi type stubs so mypy passes)

PR:             298034
DeltaFile
+299-0cad/pythonocc-core/files/patch-src_SWIG__files_wrapper_TColgp.pyi
+224-0cad/pythonocc-core/files/patch-src_SWIG__files_wrapper_TColStd.pyi
+142-0cad/pythonocc-core/files/patch-src_SWIG__files_wrapper_StepElement.pyi
+140-0cad/pythonocc-core/files/patch-src_SWIG__files_wrapper_StepVisual.pyi
+133-0cad/pythonocc-core/files/patch-src_SWIG__files_wrapper_StepAP214.pyi
+109-0cad/pythonocc-core/files/patch-src_SWIG__files_wrapper_StepFEA.pyi
+1,047-086 files not shown
+3,225-292 files

OpenBSD/src WSfgmtjlib/libc/dlfcn init.c, lib/libc/gen Makefile.inc getexecpath.c

   Add getexecpath(3) which reliabily provides a realpath-like qualified
   copy of the ELF program's execution path.
   ok kettenis beck kirill
VersionDeltaFile
1.1+71-0lib/libc/gen/getexecpath.3
1.1+43-0lib/libc/gen/getexecpath.c
1.84+3-3lib/libc/gen/Makefile.inc
1.26+5-1lib/libc/dlfcn/init.c
1.61+3-2lib/libc/sys/execve.2
1.15+2-1lib/libc/hidden/unistd.h
+127-71 files not shown
+128-77 files

LLVM/project eb6b7bdllvm/lib/Target/RISCV/GISel RISCVInstructionSelector.cpp

RISCV: Pass instruction and operand index to replacePtrWithInt (#219958)

The helper used the operand's parent instruction as the insertion point.
Pass the containing instruction and operand index directly so it no
longer depends on MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+9-9llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+9-91 files

LLVM/project 2fd412ellvm/lib/Target/AMDGPU AMDGPUGlobalISelUtils.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.raw.ptr.buffer.offset-split.ll

[AMDGPU][GIsel] Make getBaseWithConstantantOffset see `or disjoint` (#219551)

This change is split from #207821, where it was made in the process of
implementing that change to make getBaseWithConstantOffset() have the
same behavior as the SelectionDAG version.

AI disclosure: I'm pretty sure this was Codex code, and I do recall it
being an AI-found discrepancy.
DeltaFile
+5-5llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
+4-3llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+9-82 files

OpenBSD/src nEfped5include spawn.h, lib/libc Symbols.list

   Implement posix_spawn_file_actions_add{f,}chdir(3)

   Now in posix and some ports need these.

   from sthen with feedback from daniel
VersionDeltaFile
1.11+59-3lib/libc/gen/posix_spawn.c
1.10+33-6lib/libc/gen/posix_spawn_file_actions_addopen.3
1.4+6-1include/spawn.h
1.2+3-1lib/libc/hidden/spawn.h
1.12+3-1lib/libc/gen/posix_spawn.3
1.97+2-0lib/libc/Symbols.list
+106-126 files

LLVM/project 702e97aclang/lib/AST/ByteCode ByteCodeEmitter.cpp

[clang][bytecode][NFC] Remove an unreachable parameter check (#219977)

We check this both in Context and in ByteCodeEmitter. The latter is not
reachable since the former will already not create Function instances
for such functions.
DeltaFile
+0-5clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
+0-51 files