LLVM/project 8a67df6

[Target] Remove declarations without definitions (NFC) (#225615)

initializeAArch64CFIFixupPass: Added on April 11, 2022 in commit
b4ad28da196d3c2b1bc064b4dc46c3e00e93438f without a definition.

AArch64InstructionSelector::selectReduction: The definition was removed
on November 13, 2023 in commit a604c4b562e99470e397f050f1e8707f923ebed7.

AArch64TargetELFStreamer::insertAttributeInPlace: Added on January 23,
2025 in commit ee99c4d4845db66c4daa2373352133f4b237c942 without a
definition.

ARMInstPrinter::printAM2PostIndexOp: The definition was removed on
September 22, 2012 in commit 2fdbdc58701ef41ab6b52c064723926e6ec4b44f.

ARMMCCodeEmitter::getMachineSoImmOpValue: The definition was removed on
October 12, 2010 in commit 12e493ace4fc5b499361122bc5f25d2c46bea5e4.

ARMMCCodeEmitter::getThumbSRImmOpValue: The definition was removed on

    [129 lines not shown]
DeltaFile
+0-00 files

LLVM/project d8ec5c8llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU si-instr-info-correct-implicit-operands.ll opt-sgpr-to-vgpr-copy.mir

AMDGPU: Mark dead carry-out when rewriting scalar carry op to VALU (#225738)

If an operation is expanded with a dead scc def, the resultant vcc def
will also be dead, so preserve the dead flag. Reduces implicit reliance on
LiveVariables recomputing dead flags later.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+116-0llvm/test/CodeGen/AMDGPU/move-scalar-carry-to-valu-dead-vcc.mir
+18-4llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+5-5llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
+2-2llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
+2-2llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir
+1-1llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
+144-146 files

LLVM/project 20c7e95llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp, llvm/test/CodeGen/AMDGPU inline-asm-out-of-bounds-register.ll

[AMDGPU] Fix assert on empty inline asm register constraint (#225743)

An empty register name reaches this parser from user source, where
StringRef::front() asserts
DeltaFile
+12-0llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll
+3-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+15-02 files

NetBSD/pkgsrc-wip 861cd0ario PLIST, rio/patches patch-corcovado_src_sys_unix_kqueue.rs patch-rio-backend_src_config_defaults.rs

Update x11/rio to v.0.5.28.
NetBSD-specific patches removed from this version
DeltaFile
+0-68rio/patches/patch-teletypewriter_src_unix_mod.rs
+0-30rio/patches/patch-misc_rio.terminfo
+0-24rio/patches/patch-rio-backend_src_config_defaults.rs
+0-24rio/patches/patch-misc_rio.desktop
+0-17rio/patches/patch-corcovado_src_sys_unix_kqueue.rs
+5-4rio/PLIST
+5-1672 files not shown
+9-1718 files

LLVM/project 53e9da7llvm/lib/Target/ARM/MCTargetDesc ARMMCCodeEmitter.cpp, llvm/lib/Target/DirectX/DXILWriter DXILBitcodeWriter.cpp

[Target] Remove declarations without definitions (NFC) (#225615)

initializeAArch64CFIFixupPass: Added on April 11, 2022 in commit
b4ad28da196d3c2b1bc064b4dc46c3e00e93438f without a definition.

AArch64InstructionSelector::selectReduction: The definition was removed
on November 13, 2023 in commit a604c4b562e99470e397f050f1e8707f923ebed7.

AArch64TargetELFStreamer::insertAttributeInPlace: Added on January 23,
2025 in commit ee99c4d4845db66c4daa2373352133f4b237c942 without a
definition.

ARMInstPrinter::printAM2PostIndexOp: The definition was removed on
September 22, 2012 in commit 2fdbdc58701ef41ab6b52c064723926e6ec4b44f.

ARMMCCodeEmitter::getMachineSoImmOpValue: The definition was removed on
October 12, 2010 in commit 12e493ace4fc5b499361122bc5f25d2c46bea5e4.

ARMMCCodeEmitter::getThumbSRImmOpValue: The definition was removed on

    [129 lines not shown]
DeltaFile
+0-27llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
+0-11llvm/lib/Target/Mips/MipsSubtarget.h
+0-9llvm/lib/Target/SystemZ/SystemZISelLowering.h
+0-6llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+0-6llvm/lib/Target/Hexagon/Hexagon.h
+0-6llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+0-6526 files not shown
+0-11932 files

LLVM/project 0f58d04clang/lib/Sema TreeTransform.h SemaTemplateInstantiate.cpp

[clang] Migrate away from PointerUnion::dyn_cast (NFC) (#225614)

Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:

  // FIXME: Replace the uses of is(), get() and dyn_cast() with
  //        isa<T>, cast<T> and the llvm::dyn_cast<T>

Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast on
UnexpandedParameterPack::first because it is always nonnull.
Specifically, UnexpandedParameterPack is constructed only in the
following places, all of which store a nonnull pointer in first, and
first is never modified afterward:

- CollectUnexpandedParameterPacksVisitor::addUnexpanded in
  SemaTemplateVariadic.cpp
- TransformLambdaExpr in TreeTransform.h
- TransformSizeOfPackExpr in TreeTransform.h

Assisted-by: Antigravity
DeltaFile
+14-19clang/lib/Sema/SemaTemplateVariadic.cpp
+1-1clang/lib/Sema/TreeTransform.h
+1-1clang/lib/Sema/SemaTemplateInstantiate.cpp
+1-1clang/lib/Sema/SemaTemplate.cpp
+17-224 files

LLVM/project f22fe77llvm/test/Analysis/CostModel/X86 masked-intrinsic-cost.ll masked-intrinsic-cost-inseltpoison.ll

[CostModel][X86] Add masked memory test coverage for VBMI2 capable CPUs (#225790)

Add tigerlake and znver4/5 coverage - znver4 is going to be a pain as it has awful compressstore perf :(

Prep work for #214613
DeltaFile
+199-0llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
+199-0llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
+398-02 files

FreeBSD/ports e4218fdmultimedia/flvmeta Makefile distinfo

multimedia/flvmeta: Update to 1.2.2.20260821

PR:             298165
Approved by:    earl at eeg3.net (maintainer timeout)
DeltaFile
+3-3multimedia/flvmeta/distinfo
+2-3multimedia/flvmeta/Makefile
+5-62 files

FreeBSD/ports f0513aadatabases/galera26 distinfo Makefile

databases/galera26: Update to 26.4.27

Reset MAINTAINER due to multiple previous timeouts.

PR:             298182
Approved by:    devel at galeracluster.com (maintainer timeout)
DeltaFile
+3-4databases/galera26/Makefile
+3-3databases/galera26/distinfo
+6-72 files

LLVM/project ae2e61allvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Analysis/ScalarEvolution ptrtoaddr-i32-index-width.ll

[SCEV] Fix sign bits of pointers wider than their index type. (#225786)

ComputeNumSignBits counts bits over the full pointer width. If all sign
bits are in the high bits, the code previously did not adjust the number
of signed bits. For narrow index types, this could result in the number
of sign bits > than the narrow bitwidth triggering an assert in APInt
(test example has 64 bit pointer with 16 bit index width.

If all sign bits are in the high bits outside the index width, they do
not add any information for the index, just use 1 in that case.

Fixes a crash in the added tests.

PR: https://github.com/llvm/llvm-project/pull/225786
DeltaFile
+67-1llvm/test/Analysis/ScalarEvolution/ptrtoaddr-i32-index-width.ll
+5-6llvm/lib/Analysis/ScalarEvolution.cpp
+72-72 files

LLVM/project 56af1fallvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.dot.ll

[AMDGPU][InstCombine] Fold zero dot operands to accumulator

Fold AMDGPU dot intrinsics when either operand is zero.

`dot(a, 0) = 0` and `dot(0, b) = 0`, so replace the intrinsic with its accumulator.
This avoids unrelated clamp and add/sub reassociation cases.
DeltaFile
+15-30llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
+3-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+18-302 files

LLVM/project 5e6f9aellvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp

Add comment
DeltaFile
+1-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+1-01 files

LLVM/project dbb888fllvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.dot.ll

[AMDGPU][InstCombine] Canonicalize dot constant operands

Move constant dot product source operands to the right hand side
and add tests for signed and unsigned dot intrinsics.
DeltaFile
+12-12llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
+9-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+21-122 files

LLVM/project f96f125llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.dot.ll

[AMDGPU][InstCombine] Fold constant add/sub into the dot accumulator (#225002)

`amdgcn.{s,u}dot{2,4,8}(a, b, C) +/- K -> dot(a, b, C +/- K)` when both
the
accumulator C and K are constants. The new constant is computed with
wrapping APInt arithmetic to match the non-clamping accumulate.

Only applies when clamp is false (the saturating accumulate does not
reassociate) and the dot has a single use. K - dot is left alone since
it
would need the dot product negated.
DeltaFile
+33-66llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
+28-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+61-662 files

FreeBSD/ports c0230aasysutils/cbsd Makefile distinfo, sysutils/cbsd/files cbsdd.in cbsd-statsd-jail.in

sysutils/cbsd: update to 15.1.2 release

changes:        https://github.com/cbsd/cbsd/releases/tag/v15.1.2
DeltaFile
+3-3sysutils/cbsd/distinfo
+4-2sysutils/cbsd/files/cbsd-statsd-bhyve.in
+1-1sysutils/cbsd/files/cbsdd.in
+1-1sysutils/cbsd/files/cbsd-statsd-jail.in
+1-1sysutils/cbsd/files/cbsd-statsd-hoster.in
+1-1sysutils/cbsd/Makefile
+11-91 files not shown
+12-97 files

LLVM/project f364fcellvm/test/TableGen AMDGPUTargetDefGenericFeatures.td AMDGPUTargetDefGenericClassification.td

[AMDGPU] Use synthetic fixtures for generic feature validation tests

Remove the classification test that includes the full AMDGPU target. Real targets are validated when generating AMDGPUTargetParserDef.inc during the build.

Extend the lightweight generic feature tests to cover inherited classifications of backend-only features, support through member-side implications, and unsupported generic-side implied features.

Change-Id: I54dd16affdc93039ce9d2dba9c99e036bd4afe48
Validation: all four AMDGPU target-definition lit tests pass; the enhanced generic feature test takes 3.44 seconds.
DeltaFile
+0-40llvm/test/TableGen/AMDGPUTargetDefGenericClassification.td
+21-2llvm/test/TableGen/AMDGPUTargetDefGenericFeatures.td
+21-422 files

LLVM/project d343b26llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 extract-fmul-cost.ll store-chain-leading-slice-wider-vf.ll

[SLP]Try the wider store slice when the leading VF=2 slice fails

With the register VF 2 the instruction count check may reject the
leading slice of a store chain.
Try the double-width slice at the same position first and keep the wider
slices for the rest of the chain once one is vectorized.

Fixes the remaining perf regression from #221717.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/225823
DeltaFile
+39-44llvm/test/Transforms/SLPVectorizer/AArch64/store-chain-leading-slice-wider-vf.ll
+43-12llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+6-22llvm/test/Transforms/SLPVectorizer/AArch64/extract-fmul-cost.ll
+88-783 files

LLVM/project a6e1f0ellvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp

Update again
DeltaFile
+1-2llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+1-21 files

LLVM/project 7ea9ed0llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp, llvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.sudot.ll

[AMDGPU] Fold a constant add/sub into the sudot4/sudot8 accumulator

Fold a constant add into the accumulator operand of sudot4 and sudot8 when
clamping is disabled:
```
  sudot(a, b, C1, false) + C2 -> sudot(a, b, C1 + C2, false)
```
Subtraction by a constant is canonicalized to addition of its negation.
DeltaFile
+10-20llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
+26-0llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+36-202 files

LLVM/project b904780llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp

Update for comments
DeltaFile
+3-3llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+3-31 files

LLVM/project dec20dfllvm/test/Transforms/InstCombine/AMDGPU llvm.amdgcn.sudot.ll

[AMDGPU][InstCombine] Add sudot zero/constant folding tests. NFC (#225321)

<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
DeltaFile
+356-0llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
+356-01 files

HardenedBSD/src b654415lib/libc/stdlib bsearch.3, lib/libc/string wmemchr.3

Merge remote-tracking branch 'rad/freebsd/15-stable/main' into hardened/15-stable/main
DeltaFile
+134-0lib/libc/tests/stdlib/bsearch_s_test.c
+106-7lib/libc/stdlib/bsearch.3
+92-0lib/libc/tests/stdlib/bsearch_test.c
+56-20lib/libc/string/wmemchr.3
+58-0lib/libc/tests/stdlib/bsearch_b_test.c
+51-0lib/libc/tests/stdlib/test-search.h
+497-2734 files not shown
+752-10140 files

LLVM/project 3eecc40llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h SPIRVNonSemanticDebugHandler.cpp, llvm/test/CodeGen/SPIRV/debug-info debug-value-unsupported.ll debug-value.ll

[SPIRV] Emit NonSemantic DebugValue (#224158)

This adds support for emitting `DebugValue` in
`SPIRVNonSemanticDebugHandler` for `DBG_VALUE` records.

NOTE: Much of the new code was necessary to emit constants and their
types at module scope. I also added a bunch of tests as I started
getting into corner cases.

Since
[`DebugValue`](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugValue)
cannot have forward references, it can only reference already emitted
instructions. `DebugValue` cannot come after merge instructions either,
and SPIR-V requires an id defined in a function block to dominate a
non-phi use. The change has four parts:

1. `analyzeDebugRecords()` resolves placement and availability before
emission begins. Each record stays at its source position unless it lies
between a merge instruction and its terminator, in which case it moves

    [16 lines not shown]
DeltaFile
+482-54llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+177-0llvm/test/CodeGen/SPIRV/debug-info/debug-value-constant.ll
+123-0llvm/test/CodeGen/SPIRV/debug-info/debug-value-constant-existing-type.ll
+99-13llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+101-0llvm/test/CodeGen/SPIRV/debug-info/debug-value.ll
+96-0llvm/test/CodeGen/SPIRV/debug-info/debug-value-unsupported.ll
+1,078-6712 files not shown
+1,396-8518 files

LLVM/project a5ba2cfllvm/test/Transforms/SLPVectorizer/AArch64 store-chain-leading-slice-wider-vf.ll

[SLP][NFC]Add a test with the regressed vectorization (2 vs 4 before), NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/225819
DeltaFile
+162-0llvm/test/Transforms/SLPVectorizer/AArch64/store-chain-leading-slice-wider-vf.ll
+162-01 files

LLVM/project 36f7f84clang/test/OffloadTools/clang-linker-wrapper linker-wrapper-image.c, llvm/lib/Frontend/Offloading Utility.cpp

[Offloading] Use getGetElementPtr() overload accepting DataLayout (#225766)

To produce constant GEP in canonical ptradd representation.
DeltaFile
+6-6clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-image.c
+3-2llvm/lib/Frontend/Offloading/Utility.cpp
+1-1llvm/test/tools/llvm-offload-wrapper/coff-opt-ref.ll
+10-93 files

LLVM/project 8f027f4mlir/lib/Transforms/Utils GreedyPatternRewriteDriver.cpp, mlir/test/Transforms canonicalize-dce.mlir greedy-cfg-reachability.mlir

[mlir] Avoid rewriting unreachable blocks in the greedy driver

A rewrite can disconnect a block after the iteration's initial CFG sweep.
Track possible reachability changes through rewriter notifications for blocks,
terminators, successors, and region owners. Refresh reachability between
rewrites and skip worklist operations in unreachable blocks until the next
iteration removes them.

Cover inserted and redirected blocks, blocks connected before rewrite
completion, and nested regions.

Assisted-by: Codex
DeltaFile
+62-4mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
+50-1mlir/test/lib/Dialect/Test/TestPatterns.cpp
+50-0mlir/test/Transforms/greedy-cfg-reachability.mlir
+41-0mlir/test/Transforms/canonicalize-dce.mlir
+203-54 files

FreeNAS/freenas 9b18b97src/middlewared/middlewared/plugins/device_ device_info.py, src/middlewared/middlewared/pytest/unit/utils test_disk_identifier.py

Parse udev's serial and lunid properties in one place
DeltaFile
+133-6src/middlewared/middlewared/pytest/unit/utils/test_disk_identifier.py
+43-0src/middlewared/middlewared/utils/disks_/udev.py
+14-9src/middlewared/middlewared/utils/disks.py
+7-11src/middlewared/middlewared/plugins/device_/device_info.py
+197-264 files

FreeNAS/freenas 0979036src/middlewared/middlewared/plugins/device_ device_info.py, src/middlewared/middlewared/pytest/unit/utils test_disk_identifier.py

Build a disk's identifier in one place instead of two
DeltaFile
+96-0src/middlewared/middlewared/pytest/unit/utils/test_disk_identifier.py
+47-0src/middlewared/middlewared/utils/disks_/identifier.py
+15-23src/middlewared/middlewared/utils/disks_/disk_class.py
+10-11src/middlewared/middlewared/utils/disks.py
+2-2src/middlewared/middlewared/plugins/device_/device_info.py
+170-365 files

FreeNAS/freenas ab9589dsrc/middlewared/middlewared/pytest/unit/utils test_disk_wwn_lunid.py test_disk_vpd_serial.py

Share the mock_sysfs fixture between the DiskEntry test modules
DeltaFile
+53-0src/middlewared/middlewared/pytest/unit/utils/conftest.py
+0-47src/middlewared/middlewared/pytest/unit/utils/test_disk_vpd_serial.py
+0-37src/middlewared/middlewared/pytest/unit/utils/test_disk_wwn_lunid.py
+53-843 files

LLVM/project 7b733c5llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU AMDGPUSearchableTables.td

Identify async intrinsics with marker class
DeltaFile
+8-91llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+56-21llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+4-26llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+68-1383 files