FreeBSD/ports e9cebacsecurity/wazuh-manager/files patch-src_data__provider_src-sysInfoFreeBSD.cpp patch-src-data_provider-src_sysInfoFreeBSD.cpp

security/wazuh-manager: Add users and groups functions support

- Now wazuh-manager can obtain users and groups information from host
- Fix start_time data to show correct datetime data from wazuh-dashboard processes option
- Bump PORTREVISION
DeltaFile
+634-0security/wazuh-manager/files/patch-src_data__provider_src-sysInfoFreeBSD.cpp
+0-434security/wazuh-manager/files/patch-src-data_provider-src_sysInfoFreeBSD.cpp
+262-0security/wazuh-manager/files/patch-src_data__provider_src_extended__sources_groups_src-user_groups_freebsd.hpp
+106-0security/wazuh-manager/files/patch-src_data__provider_src_extended__sources_users_src-users_freebsd.cpp
+96-0security/wazuh-manager/files/patch-src_data__provider_src_extended__sources_wrappers_unix_freebsd-passwd_wrapper.hpp
+95-0security/wazuh-manager/files/patch-src_data__provider_src_extended__sources_groups_src-groups_freebsd.hpp
+1,193-43416 files not shown
+1,866-44622 files

LLVM/project 8610d35llvm/include/llvm/IR DebugInfoMetadata.h, llvm/lib/CodeGen/AsmPrinter DwarfUnit.cpp

[DebugInfo] Only generate template parameters in the skeleton CU for a template function/type with simplified name (3/3) (#175879)

Currently, when generating debug info for skeleton units, all template
parameters are emitted unconditionally. To optimize debug info size, the
emission should be conditional — providing parameters only for template
types/functions whose names have actually been simplified. As described
in [this
RFC](https://discourse.llvm.org/t/rfc-debuginfo-selectively-generate-template-parameters-in-the-skeleton-cu/89395).
Previous patches: #175130, #175708
DeltaFile
+79-0llvm/test/DebugInfo/X86/fission-simple-template-names.ll
+8-3llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+3-0llvm/include/llvm/IR/DebugInfoMetadata.h
+0-3llvm/test/DebugInfo/X86/fission-template.ll
+90-64 files

LLVM/project 4346303llvm/lib/CodeGen MachinePipeliner.cpp, llvm/test/CodeGen/Hexagon swp-carried-dep2.mir swp-carried-dep1.mir

[MachinePipeliner] Remove cheap check in dependence analysis (#174390)

In loop-carried dependence analysis of MachinePipeliner, there is
special handling for a specific case, referred to as a "cheap check".
This check is not sound and sometimes misses dependencies. If there is
no significant performance regression, this special logic should be
deleted.

Split off from https://github.com/llvm/llvm-project/pull/135148
DeltaFile
+11-40llvm/lib/CodeGen/MachinePipeliner.cpp
+9-12llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
+7-1llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
+27-533 files

FreeBSD/ports 88938fcsecurity/wazuh-agent/files patch-src_data__provider_src-sysInfoFreeBSD.cpp patch-src-data_provider-src_sysInfoFreeBSD.cpp

security/wazuh-agent: Add users and groups function support

- Now wazuh-agent can obtain users and groups information
- Fix start_time data to show correct datetime data from wazuh-dashboard processes option
- Bump PORTREVISION
DeltaFile
+634-0security/wazuh-agent/files/patch-src_data__provider_src-sysInfoFreeBSD.cpp
+0-434security/wazuh-agent/files/patch-src-data_provider-src_sysInfoFreeBSD.cpp
+262-0security/wazuh-agent/files/patch-src_data__provider_src_extended__sources_groups_src-user_groups_freebsd.hpp
+106-0security/wazuh-agent/files/patch-src_data__provider_src_extended__sources_users_src-users_freebsd.cpp
+96-0security/wazuh-agent/files/patch-src_data__provider_src_extended__sources_wrappers_unix_freebsd-passwd_wrapper.hpp
+95-0security/wazuh-agent/files/patch-src_data__provider_src_extended__sources_groups_src-groups_freebsd.hpp
+1,193-43416 files not shown
+1,866-44622 files

LLVM/project c02ace3llvm/test/MC/AMDGPU gfx8_asm_vop3.s gfx7_asm_vop3.s, llvm/test/MC/Disassembler/AMDGPU gfx9_vop3.txt

Merge branch 'main' into users/kasuga-fj/pipeliner-remove-performcheap
DeltaFile
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+41,419-41,418llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+36,428-36,427llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+28,175-28,174llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
+22,711-22,884llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+22,276-22,275llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
+193,358-193,5265,591 files not shown
+1,438,292-1,248,9205,597 files

LLVM/project f7ac184llvm/lib/Transforms/Scalar DeadStoreElimination.cpp, llvm/test/Transforms/DeadStoreElimination simple.ll

feedback

Created using spr 1.3.7
DeltaFile
+14-0llvm/test/Transforms/DeadStoreElimination/simple.ll
+2-2llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+16-22 files

FreeBSD/ports bd5435fsysutils/elephant distinfo Makefile

sysutils/elephant: Update to 2.18.2

Changelog: https://github.com/abenz1267/elephant/releases/tag/v2.18.2

Reported by:    GitHub (watch releases)
DeltaFile
+5-5sysutils/elephant/distinfo
+1-1sysutils/elephant/Makefile
+6-62 files

LLVM/project c9f4bb6llvm/lib/Target/X86 X86PassRegistry.def

[X86][NewPM] Add rest of non-ported passes to X86PassRegistry (#176068)

I noticed these when writing up the pass builder. Put them in the pass
registry to make it easier to see what is not done yet for when people
start working on more porting.
DeltaFile
+7-0llvm/lib/Target/X86/X86PassRegistry.def
+7-01 files

LLVM/project b77f952llvm/utils/gn/secondary/clang/include/clang/Basic BUILD.gn, llvm/utils/gn/secondary/clang/lib/Basic BUILD.gn

gn build: Port d5442b8c963d
DeltaFile
+4-0llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
+1-0llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
+5-02 files

OpenBSD/ports 8fR42ykdevel/arm-compute-library Makefile distinfo, devel/arm-compute-library/patches patch-SConscript patch-SConstruct

   Update arm-compute-library to 52.7.0
VersionDeltaFile
1.15+6-6devel/arm-compute-library/patches/patch-SConscript
1.24+2-2devel/arm-compute-library/Makefile
1.18+2-2devel/arm-compute-library/distinfo
1.15+2-2devel/arm-compute-library/patches/patch-SConstruct
1.18+1-0devel/arm-compute-library/pkg/PLIST
+13-125 files

FreeBSD/ports 2c12a36misc/py-huggingface-hub distinfo Makefile

misc/py-huggingface-hub: Update to 1.3.2

Changelog: https://github.com/huggingface/huggingface_hub/releases/tag/v1.3.2

Reported by:    Repology
DeltaFile
+3-3misc/py-huggingface-hub/distinfo
+1-1misc/py-huggingface-hub/Makefile
+4-42 files

LLVM/project 4db68e4llvm/include/llvm/Passes MachinePassRegistry.def

[NewPM][CodeGen] Add missing non-ported pass to registry

Not sure why this did not make it in the list originally. But adding it
so that someone looking for passes to port in the registry will see it.
DeltaFile
+1-0llvm/include/llvm/Passes/MachinePassRegistry.def
+1-01 files

HardenedBSD/src 59096c6release Makefile.ec2

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main
DeltaFile
+5-1release/Makefile.ec2
+5-11 files

OpenZFS/src 8605bdfmodule/zfs vdev.c, tests/zfs-tests/cmd mmap_seek.c

FreeBSD: unbreak compilation on i386

tests/zfs-tests/cmd/mmap_seek.c: use correct printf specifier
module/zfs/vdev.c: vdev_clear(): correctly cast argument to
atomic_add_64().

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Martin Matuska <mm at FreeBSD.org>
Closes #18096
DeltaFile
+1-1module/zfs/vdev.c
+1-1tests/zfs-tests/cmd/mmap_seek.c
+2-22 files

FreeBSD/ports 9514ac9games/veloren-weekly distinfo Makefile

games/veloren-weekly: update to s20260114

Changes:        https://gitlab.com/veloren/veloren/-/compare/a5ef556b04...a95ccd4d76
(cherry picked from commit 1b873f3ec9c3f3109fa647e6de816d169ad53152)
DeltaFile
+3-3games/veloren-weekly/distinfo
+2-2games/veloren-weekly/Makefile
+5-52 files

FreeBSD/ports 4e2183egraphics/mesa-devel distinfo Makefile

graphics/mesa-devel: update to 25.3.b.3439

Changes:        https://gitlab.freedesktop.org/mesa/mesa/-/compare/5ac41be6777...6f076cdfda3
DeltaFile
+3-3graphics/mesa-devel/distinfo
+2-2graphics/mesa-devel/Makefile
+5-52 files

FreeBSD/ports 76b30a7emulators/rpcs3 distinfo Makefile

emulators/rpcs3: update to 0.0.39.18702

Changes:        https://github.com/RPCS3/rpcs3/compare/v0.0.39...d7b723cd7c
DeltaFile
+3-3emulators/rpcs3/distinfo
+2-2emulators/rpcs3/Makefile
+5-52 files

FreeBSD/ports 1b873f3games/veloren-weekly distinfo Makefile

games/veloren-weekly: update to s20260114

Changes:        https://gitlab.com/veloren/veloren/-/compare/a5ef556b04...a95ccd4d76
DeltaFile
+3-3games/veloren-weekly/distinfo
+2-2games/veloren-weekly/Makefile
+5-52 files

LLVM/project 036fa67llvm/lib/Target/AMDGPU SIRegisterInfo.td GCNSubtarget.cpp, llvm/test/CodeGen/AMDGPU regalloc-vgpr_lo128-gfx1250-t16.mir regalloc-vgpr_lo128-gfx1250.mir

[AMDGPU] Limit allocation of lo128 registers for occupancy

Parent change allows allocation of lo128 VGPRs from all 4 banks.
That may result in the undesired allocation leaving a hole of
maximum 128 registers in case if for example v0-v127 are allocated,
and v128-v255 are free.

Limit the available allocation order to the occupancy. Both hard
occupancy limits and occupancy achieved during scheduling are
considered. That is better to spill a register than to drop occupancy
in this case.
DeltaFile
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250-t16.mir
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250.mir
+53-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250-t16.mir
+30-4llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+29-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250.mir
+9-0llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+315-61 files not shown
+323-67 files

LLVM/project 9979f63llvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx11_asm_vop3_from_vopc.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge branch 'users/chapuni/mcdc/nest/nest' into users/chapuni/mcdc/nest/trunk
DeltaFile
+5,421-5,421llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+2,919-2,919llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,802-2,802llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
+2,645-2,645llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+22,912-22,912742 files not shown
+126,623-105,479748 files

LLVM/project 1b17f31llvm/test/MC/AMDGPU gfx8_asm_vop3.s gfx7_asm_vop3.s, llvm/test/MC/Disassembler/AMDGPU gfx9_vop3.txt

Merge branch 'users/chapuni/mcdc/nest/covmapdesc' into users/chapuni/mcdc/nest/nest

Conflicts:
        clang/lib/CodeGen/CodeGenPGO.cpp
DeltaFile
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+41,419-41,418llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+36,428-36,427llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+28,175-28,174llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
+22,711-22,884llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+22,276-22,275llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
+193,358-193,5265,661 files not shown
+1,449,922-1,252,6225,667 files

LLVM/project ef2ee43llvm/test/MC/AMDGPU gfx8_asm_vop3.s gfx7_asm_vop3.s, llvm/test/MC/Disassembler/AMDGPU gfx9_vop3.txt

Merge branch 'users/chapuni/mcdc/nest/bitmapaddr' into users/chapuni/mcdc/nest/covmapdesc
DeltaFile
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+41,419-41,418llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+36,428-36,427llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+28,175-28,174llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
+22,711-22,884llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+22,276-22,275llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
+193,358-193,5265,663 files not shown
+1,450,232-1,252,8205,669 files

LLVM/project a837107llvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx10_asm_vop1.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge branch 'users/chapuni/mcdc/nest/covgen' into users/chapuni/mcdc/nest/bitmapaddr
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+4,672-4,671llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+34,743-34,7392,431 files not shown
+225,579-160,7002,437 files

LLVM/project 11efca0llvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx11_asm_vop3_from_vopc.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge branch 'main' into users/chapuni/mcdc/nest/covgen
DeltaFile
+5,421-5,421llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+2,919-2,919llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+2,802-2,802llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc.s
+2,645-2,645llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vopc-fake16.s
+22,912-22,912747 files not shown
+126,682-105,505753 files

LLVM/project a7f489bllvm/lib/Target/AMDGPU SIRegisterInfo.td GCNSubtarget.h, llvm/test/CodeGen/AMDGPU regalloc-vgpr_lo128-gfx1250.mir regalloc-vgpr_lo128-gfx1250-t16.mir

[AMDGPU] Limit allocation of lo128 registers for occupancy

Parent change allows allocation of lo128 VGPRs from all 4 banks.
That may result in the undesired allocation leaving a hole of
maximum 128 registers in case if for example v0-v127 are allocated,
and v128-v255 are free.

Limit the available allocation order to the occupancy. Both hard
occupancy limits and occupancy achieved during scheduling are
considered. That is better to spill a register than to drop occupancy
in this case.
DeltaFile
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250.mir
+97-1llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250-t16.mir
+53-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250-t16.mir
+30-4llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+29-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250.mir
+8-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+314-61 files not shown
+321-67 files

LLVM/project 663647fcross-project-tests/dtlto multimodule.test, llvm/include/llvm/LTO LTO.h

[DTLTO] Fix handling of multi-module bitcode inputs (#174624)

This change fixes two issues when processing multi-module bitcode files
in DTLTO:

1. The DTLTO archive handling code incorrectly uses
getSingleBitcodeModule(), which asserts when the bitcode file contains
more than one module.
2. The temporary file containing the contents of an input archive member
was not emitted for multi-module bitcode files. This was due to
incorrect logic for recording whether a bitcode input contains any
ThinLTO modules. In a typical multi-module bitcode file, the first
module is a ThinLTO module while a subsequent auxiliary module is
non-ThinLTO. When modules are processed in order, the auxiliary module
causes the entire bitcode file to be classified as non-ThinLTO, and the
archive-member emission logic then incorrectly skips it.

In addition, this patch adds a test that verifies that multi-module
bitcode files can be successfully linked with DTLTO. The test reproduces

    [2 lines not shown]
DeltaFile
+42-0cross-project-tests/dtlto/multimodule.test
+3-1llvm/lib/LTO/LTO.cpp
+2-0llvm/include/llvm/LTO/LTO.h
+1-1llvm/lib/DTLTO/DTLTO.cpp
+48-24 files

LLVM/project d7b6df7clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 avx512vldq-builtins.c avx10_2bf16-builtins.c

[CIR][X86] Add CIR codegen support for fpclass x86 builtins (#172813)

This implements the handling for x86-specific fpclass builtin functions.
DeltaFile
+173-0clang/test/CIR/CodeGenBuiltins/X86/avx512vldq-builtins.c
+72-0clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
+72-0clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c
+60-4clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+37-0clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
+36-0clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
+450-41 files not shown
+451-47 files

FreeNAS/freenas 72cf61dsrc/middlewared/middlewared/plugins network.py

whoops, forgot commit
DeltaFile
+5-3src/middlewared/middlewared/plugins/network.py
+5-31 files

LLVM/project a11feefclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp, clang/test/CIR/IR vector.cir throw.cir

[CIR] Make cir.alloca alignment mandatory (#172663)

Fixed a crash in `CIRToLLVMAllocaOpLowering` where `cir.alloca`
operations without an explicit alignment attribute caused failures.

Modified the ODS definition of `cir.alloca` to use
`ConfinedAttr<I64Attr, [IntMinValue<0>]>`. This ensures the attribute is
always present.

Added a regression test in `clang/test/CIR/Lowering/alloca.cir`.

---------

Co-authored-by: Sirui Mu <msrlancern at gmail.com>
DeltaFile
+17-17clang/test/CIR/IR/vector.cir
+13-0clang/test/CIR/Lowering/alloca.cir
+3-3clang/test/CIR/IR/throw.cir
+3-3clang/test/CIR/IR/invalid-complex.cir
+2-2clang/test/CIR/Transforms/vector-extract-fold.cir
+2-2clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+40-2710 files not shown
+53-4016 files

LLVM/project 779c05aclang/lib/CodeGen CodeGenPGO.cpp CodeGenPGO.h, clang/test/Profile c-mcdc-logicalop-ternary.c

[MC/DC] Create dedicated MCDCCondBitmapAddr for each Decision (#125411)

MCDCCondBitmapAddr is moved from `CodeGenFunction` into `MCDCState` and
created for each Decision.

In `maybeCreateMCDCCondBitmap`, Allocate bitmaps for all valid Decisions
and emit them order by ID, to prevent nondeterminism.
DeltaFile
+44-10clang/lib/CodeGen/CodeGenPGO.cpp
+10-8clang/test/Profile/c-mcdc-logicalop-ternary.c
+3-5clang/lib/CodeGen/CodeGenPGO.h
+0-3clang/lib/CodeGen/CodeGenFunction.h
+2-0clang/lib/CodeGen/MCDCState.h
+59-265 files