[clang-format] Add support for additional C++ declaration specifiers in QualifierOrder (#160853)
Fixes #60866
This PR extends clang-formats `QualifierOrder` option to support
additional C++ declaration specifiers, addressing the limitation where
many common qualifiers were not recognized.
## Problem
Previously, `QualifierOrder` only supported a limited subset of C++
declaration specifiers:
- `const`, `volatile`, `static`, `inline`, `constexpr`, `restrict`,
`friend`
This meant that many common C++ qualifiers like `extern`, `mutable`,
`typedef`, `unsigned`, etc. were not recognized and could not be
properly reordered, limiting the usefulness of the feature.
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AMDGPU: Capture G_PTR_ADD flags via m_MIFlags in getBaseWithConstantOffset (#216809)
Read the nuw flag from the m_GPtrAdd match itself instead of a redundant
getVRegDef of the pointer register. NFC.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
AMDGPU: Use mi_match for G_BITCAST check in RegBankLegalize (#216808)
Replace the getVRegDef + G_BITCAST opcode check in
tryEliminateReadAnyLane
with m_GBitcast. NFC.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
AArch64: Guard optimizeCondBranch against a physical copy source (#216699)
optimizeCondBranch walks COPY chains from the branch condition register,
calling getVRegDef on each copy's source operand. A COPY source can be a
physical register which doesn't make sense to pass to getVRegDef.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[LLVMABI][AARCH64] Add support for simple direct return case (#216437)
This adds LLVM ABI library support for AArch64 return type
classification for scalar and matrix types that are classified as
Direct. Other types and all arguments are now reported as not yet
implemented.
This also introduces the hook in Clang to use the ABI library for
non-Windows AArch64 targets when `-fexperimental-abi-lowering` is passed
and adds a test for the ABI handling of types which are handled by the
library.
Assisted-by: Cursor / various models
[APFloat][SelectionDAG] Support Float8E5M3FNU in `convert.{to,from}.arbitrary.fp` (#216387)
Float8E5M3FNU was already accepted by the IR verifier, because
`isValidArbitraryFPFormat` is defined in terms of
`getArbitraryFPFormatSizeInBits` and that table covers it. It was
missing from `getArbitraryFPSemantics`, so `SelectionDAGBuilder`
rejected it with "not implemented format" and the verifier-clean IR
failed to compile. Add the mapping and the corresponding entries in the
`expandCONVERT_{TO,FROM}_ARBITRARY_FP` format allowlists.
Unlike every other format the expansions handle so far, Float8E5M3FNU is
unsigned: it has no sign bit, so all 8 bits go to a 5-bit exponent and a
3-bit significand.
Since an unsigned format cannot represent a negative value, a negative
input now saturates to zero when the saturate flag is set, and is poison
otherwise. -0.0 is excluded from that and still converts to +0, and the
check is ordered before the NaN case so a negative NaN still produces
the NaN encoding. APFloat treats constructing a negative value in an
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[AArch64] Restrict FP imm ISel by accurate subtarget macro-fusion (#214849)
This patch improves the accuracy of FP immediate lowering for runtime
performance builds. Until now we relaxed the instruction count limit
from 2 to 4 merely based on the satisfaction of `ST.hasFuseLiterals`,
but this could be wrong for example false-positive for `MOVN`
instructions which would relax the limit but are not macro fused. Here
we check exactly if immediate materialization parts can be macro fused
using a new subtarget helper which is shared with macro-fusion.
It adds exhaustive test cases for all code sequences that
`isFPImmLegal()` can enable using `expandMOVImm()`. Including f32 as
regression tests - those cannot trigger a subtarget feature check,
because a f32 immed can always be materialized by up to 2 instructions
which is the default limit. As well as an optsize test with
representative test cases.
---------
Co-authored-by: Jon Roelofs <jroelofs at gmail.com>
fts: fix file descriptor leak in fts_close
fts_build() stores a dup'd file descriptor in each directory
entry's fts_dirfd. When a traversal is abandoned before
completion and fts_close() is called, the cleanup loop freed
each pending entry with free() without first closing its
fts_dirfd, leaking one descriptor per pending directory.
Close fts_dirfd before freeing each entry in the cleanup loop,
matching the handling already applied to the dummy parent entry
after the loop.
Add a regression test that descends a couple of levels, abandons
the traversal, closes, and asserts the open descriptor count is
unchanged.
PR: 297557
Reported by: asomers
Fixes: 4bd01d6ae016
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[CIR] Fix array consts who change during layout (#216732)
The element types of an array can change for the purposes of lowering
depending on the contents of the initializer, particularly with unions.
This patch correctly mutates the array type such that it is either a
contiguous array (the correct way), or a struct that has the same
layout.
[VPlan][UTC] Number VPlan passes' instances in printing/filtering (#211424)
Allows to use UTC-generated CHECKs in more tests. First instance of a
given VPlan pass on a function doesn't have a number (would need
`-vplan-print-after=passName$`). Subsequent instances are numbered and
can be filtered as `-vplan-print-after=passName at 2`.
AMDGPU: Use mi_match in isFPExtFromF16OrConst (#216807)
Replace the getVRegDef + G_FPEXT/G_FCONSTANT opcode checks with m_GFPExt
and m_GFCst matchers. NFC.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[mlir][scf] Fully unroll SCF/Affine loops (#215220)
Adds a new transform op that fully unrolls given loops. Also, updates
'loop.unroll' documentation to better reflect its functionality.
A new op is added to avoid overloading and changing the default behavior
of the other existing unroll ops.
On its own, the new op complements the existing two transform ops and
mirrors available SCF/Affine utils.
Assisted-by: Copilot
[SystemZ][z/OS] Refactor switching section for HLASM
Emitting the HLASM instructions for switching section is distributed
between MCAsmInfoGOFF and SystemZHLASMAsmStreamer, with some code
duplication. This change consolidates the implementation in
SystemZHLASMAsmStreamer.
[1/2][AMDGPU] Fixed crash due to virtual register defs not dominating uses (#198472)
Fixes https://github.com/llvm/llvm-project/issues/196671.
Fixes duplicate ROCM-24494, LCOMPILER-2224.
In Rewrite AGPR-Copy-MFMA pass, a spill reload may not have a dominating
spill store. If such a slot is unspilled into a vreg, the elimination
phase crashes because virtual register defs do not dominate all uses.
This patch checks for that dominance property for all reloads and skips
unspilling if such a condition is found.
This patch is adapted from
https://github.com/llvm/llvm-project/pull/167347
Cherry-picked https://github.com/ROCm/llvm-project/commit/e5d02ddb
Authored by: Austin Kerbow <Austin.Kerbow at amd.com>
Instead of scanning through instructions within the reload basic block,
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