OPNSense/plugins 2392c95net-mgmt/net-snmp Makefile pkg-descr, net-mgmt/net-snmp/src/opnsense/mvc/app/models/OPNsense/Netsnmp General.xml

net-mgmt/net-snmp switch to StrictTextField (#5715)
DeltaFile
+4-4net-mgmt/net-snmp/src/opnsense/mvc/app/models/OPNsense/Netsnmp/General.xml
+4-0net-mgmt/net-snmp/pkg-descr
+1-2net-mgmt/net-snmp/Makefile
+9-63 files

LLVM/project 92d4f66llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] LowerFP_TO_INT_SAT - use original SDValue directly. NFC. (#223651)

No need to access everything via the SDNode

Cleanup to reduce diff in #199416
DeltaFile
+5-6llvm/lib/Target/X86/X86ISelLowering.cpp
+5-61 files

LLVM/project 184ef35llvm/lib/Transforms/AggressiveInstCombine AggressiveInstCombine.cpp, llvm/test/Transforms/AggressiveInstCombine memset.ll

[AggressiveInstCombine] Guard memset with length in [0, 1] (#213240)

Use computeKnownBits to identify nonconstant memset lengths whose
possible values are limited to zero and one. The check is integrated
into the existing instruction loop in foldUnusualPatterns via the
dedicated helper foldMemSetZeroOrOneLength.

Insert a conditional branch around the memset and specialize the
executed path to a constant length of one. A following InstCombine
pass can then replace it with a byte store, including for a
nonconstant fill value.

Do not transform wider ranges such as [0, 2].

Fixes #213027.

Assisted by GPT-5
DeltaFile
+111-0llvm/test/Transforms/AggressiveInstCombine/memset.ll
+43-4llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+154-42 files

LLVM/project 3a42f8aclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen builtins-arm64.c builtins-arm.c

[ARM] Emit llvm.clear_cache for __clear_cache() (#223398)

It looks like the ARM-specific __clear_cache() builtin emits different
IR than the generic __builtin___clear_cache() builtin (added later),
which uses the llvm.clear_cache intrinsic (which will typically lower to
a __clear_cache libcall, of course).

Use llvm.clear_cache for __clear_cache() as well, for consistency and to
slightly simplify the code.
DeltaFile
+8-18clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1-1clang/test/CodeGen/builtins-arm64.c
+1-1clang/test/CodeGen/builtins-arm.c
+10-203 files

FreeBSD/src 6949235sys/dev/sound/usb uaudio.c

snd_uaudio: Read the UAC2 sample rate back after setting it

Some devices only apply a new sample rate once it has been read back,
and produce no sound at all otherwise.

PR:             294803
Reported by:    tatsuki_makino at hotmail.com
Tested by:      tatsuki_makino at hotmail.com
MFC after:      2 weeks
Sponsored by:   The FreeBSD Foundation
Reviewed by:    emaste
Differential Revision:  https://reviews.freebsd.org/D59616
DeltaFile
+22-1sys/dev/sound/usb/uaudio.c
+22-11 files

LLVM/project d8e5c98llvm/lib/Target/ARM ARMTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/ARM shuffle.ll

[ARM] Add Neon costs for vrev shuffles (#223310)

This, like for AArch64 and MVE, allows some of the legal vrev shuffle
masks to be costed as if they are a single instruction, which can help
prevent the mid end from deoptimizing the code.
DeltaFile
+10-10llvm/test/Analysis/CostModel/ARM/shuffle.ll
+11-0llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+21-102 files

LLVM/project 7162999llvm/lib/Target/AArch64 AArch64PredicateAsCounterLoopRewrites.cpp

Fixup concat
DeltaFile
+13-13llvm/lib/Target/AArch64/AArch64PredicateAsCounterLoopRewrites.cpp
+13-131 files

LLVM/project 68747f2llvm/cmake config-ix.cmake, llvm/include/llvm/Config config.h.cmake

[CMake] Prune dead and unnecessary try_compiles from config.h (#223600)

Several config-ix checks either have no consumer or can be performed
directly by the source that needs the feature. Remove six compiler
invocations from a typical Linux configure:

* HAVE_PTHREAD_MUTEX_LOCK has been unused since LLVM switched its mutex
implementation to std::recursive_mutex in 2019.
* The Linux magic-header results have never been propagated to config.h,
so CMake builds already use Path.inc's fallback constants.
* FE_ALL_EXCEPT and FE_INEXACT can be tested directly after including
cfenv.
* The Valgrind and CrashReporter headers can be detected with
__has_include in their only consuming translation units.

Also remove the obsolete definitions from the GN and Bazel
configurations.

In a fresh minimal LLVM configure, CMake profiling attributed 2067.1 ms

    [3 lines not shown]
DeltaFile
+0-17utils/bazel/llvm_configs/config.h.cmake
+0-17utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
+0-17llvm/include/llvm/Config/config.h.cmake
+0-15llvm/cmake/config-ix.cmake
+6-8llvm/lib/Support/Valgrind.cpp
+4-9utils/bazel/llvm-project-overlay/llvm/config.bzl
+10-834 files not shown
+16-10410 files

LLVM/project 8397594llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] Move ISD::FP_TO_*INT_SAT actions to be with a Subtarget's other ops. (#223657)

Don't treat them differently to the general pattern we try to keep to
based on grouping each Subtarget abilities - they shouldn't allow
soft-float either.

Cleanup to reduce diff in #199416
DeltaFile
+25-32llvm/lib/Target/X86/X86ISelLowering.cpp
+25-321 files

FreeNAS/freenas 769f3a2src/middlewared/middlewared/plugins/filesystem_ acl.py, tests/api2 test_s3_bucket.py

Reject recursive permissions changes on S3 bucket mountpoints

filesystem.chown, filesystem.setperm and filesystem.setacl now refuse
a recursive change whose path is the mountpoint of a dataset consumed
by an S3 bucket, or that would traverse into one from above. The error
points the caller at the bucket's s3data directory instead, since a
recursive change over the whole bucket may have undefined behavior and
expose security risks.
DeltaFile
+57-0src/middlewared/middlewared/plugins/filesystem_/acl.py
+54-1tests/api2/test_s3_bucket.py
+111-12 files

LLVM/project aef91d6llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 conditional-subtract.ll

[AArch64] Reuse SUBS results for conditional subtraction (#223391)

For C++ code such as:

  uint64_t conditional_subtract(uint64_t x, uint64_t q) {
    return x - (x >= q ? q : 0);
  }

AArch64 currently uses three instructions for the conditional
subtraction (omitting the return):

  cmp  x0, x1
  csel x8, x1, xzr, hs
  sub  x0, x0, x8

The comparison already computes x - q to set the condition flags, but
its arithmetic result is discarded. Preserve that result with SUBS and
select between it and x, reducing the sequence to two instructions:


    [9 lines not shown]
DeltaFile
+439-0llvm/test/CodeGen/AArch64/conditional-subtract.ll
+37-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+476-02 files

HardenedBSD/src 66ed3cbshare/man/man4 ixv.4, sys/compat/linuxkpi/common/include/asm cpu_device_id.h

Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/cross-dso-cfi
DeltaFile
+48-6sys/dev/ixgbe/ixgbe_hv_vf.c
+14-1share/man/man4/ixv.4
+1-1sys/dev/ixgbe/if_ixv.c
+2-0sys/compat/linuxkpi/common/src/linux_compat.c
+2-0sys/compat/linuxkpi/common/include/asm/cpu_device_id.h
+1-0sys/dev/ixgbe/ixgbe_hv_vf.h
+68-86 files

HardenedBSD/src 1bc7387share/man/man4 ixv.4, sys/compat/linuxkpi/common/include/asm cpu_device_id.h

Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/pledge
DeltaFile
+48-6sys/dev/ixgbe/ixgbe_hv_vf.c
+14-1share/man/man4/ixv.4
+1-1sys/dev/ixgbe/if_ixv.c
+2-0sys/compat/linuxkpi/common/src/linux_compat.c
+2-0sys/compat/linuxkpi/common/include/asm/cpu_device_id.h
+1-0sys/dev/ixgbe/ixgbe_hv_vf.h
+68-86 files

HardenedBSD/src 8d879f3share/man/man4 ixv.4, sys/compat/linuxkpi/common/include/asm cpu_device_id.h

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+48-6sys/dev/ixgbe/ixgbe_hv_vf.c
+14-1share/man/man4/ixv.4
+1-1sys/dev/ixgbe/if_ixv.c
+2-0sys/compat/linuxkpi/common/src/linux_compat.c
+2-0sys/compat/linuxkpi/common/include/asm/cpu_device_id.h
+1-0sys/dev/ixgbe/ixgbe_hv_vf.h
+68-86 files

LLVM/project df05de8llvm/test/Transforms/LoopVectorize blend-i1.ll

remove store from test

The extra user prevents the combine from kicking in
DeltaFile
+5-9llvm/test/Transforms/LoopVectorize/blend-i1.ll
+5-91 files

LLVM/project 4510d55llvm/test/CodeGen/AArch64 umulh.ll smulh.ll, llvm/test/CodeGen/RISCV umulh.ll smulh.ll

[LLVM] Add llvm.[su]mulh intrinsics. (#220293)

These intrinsics correspond to (un)signed multiply-high operations. The
motivation for introducing them is to allow more accurate costing
(particularly for vectorisation) and to simplify code generation for
chained multiply-high operations.

Together with subsequent patches to combine and cost the intrinsics,
this gives an 8% speedup on 750.sealcrypto_r on Neoverse V2.
DeltaFile
+4,864-0llvm/test/CodeGen/RISCV/smulh.ll
+4,319-0llvm/test/CodeGen/RISCV/umulh.ll
+851-0llvm/test/CodeGen/X86/smulh.ll
+746-0llvm/test/CodeGen/X86/umulh.ll
+552-0llvm/test/CodeGen/AArch64/smulh.ll
+434-0llvm/test/CodeGen/AArch64/umulh.ll
+11,766-017 files not shown
+12,200-423 files

FreeBSD/ports 02f7743databases/py-harlequin Makefile distinfo

databases/py-harlequin: Update to 2.14.0

ChangeLog:

1. https://github.com/tconbeer/harlequin/releases/tag/v2.14.0

Reported by:Ted Conbeer <notifications at github.com>
DeltaFile
+3-3databases/py-harlequin/distinfo
+1-1databases/py-harlequin/Makefile
+4-42 files

HardenedBSD/ports 02f7743databases/py-harlequin Makefile distinfo

databases/py-harlequin: Update to 2.14.0

ChangeLog:

1. https://github.com/tconbeer/harlequin/releases/tag/v2.14.0

Reported by:Ted Conbeer <notifications at github.com>
DeltaFile
+3-3databases/py-harlequin/distinfo
+1-1databases/py-harlequin/Makefile
+4-42 files

LLVM/project fe69e13llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Simplify getElementSz using getLoadStore-helpers (NFC) (#222908)
DeltaFile
+3-13llvm/lib/Analysis/ScalarEvolution.cpp
+3-131 files

LLVM/project 0753606llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Remove (X && Y) | (X && !Y) -> X combine. NFC

We have smaller combines that can take care of this now that we process recipes in a worklist
DeltaFile
+1-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-81 files

LLVM/project 0e73bb8llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]
DeltaFile
+26-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+5-7llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+42-193 files

LLVM/project b96eb6dllvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

Precommit test
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163-01 files

LLVM/project 885af64llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Unindent loop
DeltaFile
+14-13llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+14-131 files

LLVM/project 6015194llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

No need to dyn_cast to singledef recipe anymore
DeltaFile
+1-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-31 files

LLVM/project a91d1ballvm/test/Transforms/LoopVectorize blend-i1.ll

Make then branch non-dead
DeltaFile
+10-6llvm/test/Transforms/LoopVectorize/blend-i1.ll
+10-61 files

LLVM/project 9a0ef7dllvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Address review comments

- Limit to double initial worklist size
- Use VPSingleDefRecipe type
DeltaFile
+11-6llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-61 files

LLVM/project e0614e9llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Switch to SmallVector with space on stack

SmallVector allows for much larger small sizes than SetVector, so use 256 to match InstructionWorklist.
We don't need to worry about duplicate worklist entries until we add users to the worklist.
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-41 files

LLVM/project fb6d199llvm/test/Transforms/LoopVectorize blend-i1.ll

Precommit test
DeltaFile
+58-0llvm/test/Transforms/LoopVectorize/blend-i1.ll
+58-01 files

LLVM/project 90d7782llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Use make_pointer_range
DeltaFile
+1-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-21 files

LLVM/project 2f49232llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize iv_outside_user.ll blend-i1.ll

[VPlan] Process simplifyRecipes in a worklist

This brings simplifyRecipes further in line with InstCombine, and asides from unlocking more simplifications it also helps avoid spurious test churn whenever passes are moved around simplifyRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification order as before.

I've gone through and checked every simplification we do is a canonicalisation that converges, and I checked on llvm-test-suite + SPEC CPU 2017 in various configurations that we don't hit any cycles.
DeltaFile
+23-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-8llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+2-3llvm/test/Transforms/LoopVectorize/blend-i1.ll
+1-2llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+30-274 files