FreeBSD/ports 7df10fc — lang/python-doc-html distinfo, lang/python312 Makefile Makefile.version

lang/python312: update to 3.12.15

Changelog: https://docs.python.org/3.12/whatsnew/changelog.html#python-3-12-15-final
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+5-5lang/python-doc-html/distinfo
+3-3lang/python312/distinfo
+1-1lang/python312/Makefile.version
+0-1lang/python312/Makefile
+9-104 files

LLVM/project 787c4f7 — llvm/include/llvm/Transforms/IPO Instrumentor.h, llvm/lib/Transforms/IPO InstrumentorConfigFile.cpp Instrumentor.cpp

[Instrumentor] Support multiple runtime bitcodes (#216333)

Replace the runtime_bitcode string option with runtime_bitcodes, an
ordered list of runtime bitcode files. Each file is parsed and linked
into the instrumented module in list order, so a runtime can be split
into separate modules, e.g., shared state and callbacks, without merging
them into one file first.

---------

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+43-26llvm/lib/Transforms/IPO/Instrumentor.cpp
+35-0llvm/lib/Transforms/IPO/InstrumentorConfigFile.cpp
+27-3llvm/include/llvm/Transforms/IPO/Instrumentor.h
+18-0llvm/test/Instrumentation/Instrumentor/runtime_bitcodes.ll
+17-0llvm/test/Instrumentation/Instrumentor/runtime_bitcodes_config.json
+16-0llvm/test/Instrumentation/Instrumentor/runtime_bitcodes_preserved_analyses.ll
+156-294 files not shown
+172-3310 files

FreeBSD/ports ce879d5 — lang/python311 distinfo Makefile, lang/python311/files patch-Modules__socketmodule.c

lang/python311: fix order of divert(4) commits

Use https://github.com/python/cpython/pull/96536 directly

PR: 267648, 298106
DeltaFile
+0-29lang/python311/files/patch-Modules__socketmodule.c
+3-2lang/python311/Makefile
+3-1lang/python311/distinfo
+6-323 files

NetBSD/pkgsrc-wip 5501f84 — roswell COMMIT_MSG

roswell: Clean-up COMMIT_MSG file
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+0-11roswell/COMMIT_MSG
+0-111 files

LLVM/project 509e09a — libc .clang-tidy, libc/src .clang-tidy

[libc] Establish clean baseline for implementation-in-namespace (#231639)

Scope libc/src/.clang-tidy down to llvmlibc-implementation-in-namespace
with WarningsAsErrors to establish a 100% green baseline.

Add NOLINT comments to replaceable global allocation functions in
new.cpp which must reside in the global namespace. Disable default
clang-analyzer checks in libc/.clang-tidy with a leading '-*'.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+9-1libc/src/__support/CPP/new.cpp
+2-5libc/src/.clang-tidy
+1-1libc/.clang-tidy
+12-73 files

NetBSD/pkgsrc-wip 272e7ca — gnu-apl distinfo DESCR

gnu-apl: initial import, tested against option pgsql, working, executed some scripts from home page with success
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+163-0gnu-apl/PLIST
+62-0gnu-apl/options.mk
+46-0gnu-apl/Makefile
+15-0gnu-apl/DESCR
+5-0gnu-apl/distinfo
+291-05 files

LLVM/project 3b6b7cb — llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer VecUtils.cpp

[SandboxVec][LoadStoreVec] Support constant vectors of mixed types
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+400-4llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_mixed_types.ll
+118-26llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+53-0llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
+23-23llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
+6-28llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+10-12llvm/unittests/Passes/PassBuilderBindings/PassBuilderBindingsTest.cpp
+610-937 files not shown
+657-9713 files

LLVM/project 8f0a6c6 — llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU AMDGPUSearchableTables.td

Identify async intrinsics with marker class
DeltaFile
+8-91llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+56-21llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+4-26llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+68-1383 files

LLVM/project 2604e32 — llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp SIISelLowering.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

[NFC][AMDGPU] Create tables for async-related intrinsics
DeltaFile
+101-0llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+37-31llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+4-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-15llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+3-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+147-635 files

LLVM/project 997d36e — llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU AMDGPUSearchableTables.td AMDGPUInstructionSelector.cpp

Narrow marker class to LDSDMA intrinsics
DeltaFile
+29-59llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+17-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5-13llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+4-13llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+15-2llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+0-3llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+70-946 files

FreeNAS/freenas ab114d8 — tests/api2 test_300_nfs.py, tests/protocols pynfs_proto.py

Fix api2.test_300_nfs.TestNFSops.test_nonroot_behavior
DeltaFile
+45-24tests/api2/test_300_nfs.py
+5-0tests/protocols/pynfs_proto.py
+50-242 files

FreeNAS/freenas e1f08dc — tests/api2 test_alert.py

NAS-144450 / 27.0.0 / Fix alerts test (by themylogin) (#20007)

Wait for `VolumeStatus` alert by class instead of source. If another
alert from that source appears (e.g., boot pool status alert), the test
breaks because `volume` key is not there:
```
    def wait_for_alert(timeout=120):
        for _ in range(timeout):
            for alert in call("alert.list"):
                if (
                    alert["source"] == "VolumeStatus"
                  and alert["args"]["volume"] == pool_name
                        ^^^^^^^^^^^^^^^^^^^^^^^
                    and alert["args"]["state"] == "DEGRADED"
                ):
E               KeyError: 'volume'
```

Original PR: https://github.com/truenas/middleware/pull/20006

Co-authored-by: themylogin <themylogin at gmail.com>
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+1-1tests/api2/test_alert.py
+1-11 files

FreeNAS/freenas 1d55f81 — src/middlewared/middlewared/test/integration/utils alert.py, tests/api2 test_smb_veeam_repo.py test_account_root_password.py

NAS-144445 / 27.0.0 / Properly wait for oneshot alerts in tests (by themylogin) (#20008)

`alert.oneshot_create` does not create the alert instantaneously because
it waits for alerts lock. Some of our tests do not expect that,
resulting in flakiness. The worst case is `test_root_password_disabled`
which also failed cleanup and left the system misconfigured.

Original PR: https://github.com/truenas/middleware/pull/20002

Co-authored-by: themylogin <themylogin at gmail.com>
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+20-30tests/api2/test_530_ups.py
+25-15tests/api2/test_account_root_password.py
+12-24tests/api2/test_smb_veeam_repo.py
+28-0src/middlewared/middlewared/test/integration/utils/alert.py
+85-694 files

LLVM/project b07ab20 — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp

Update attributor name
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+4-4llvm/docs/AMDGPUUsage.rst
+1-1llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+5-52 files

LLVM/project 4614b0c — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUSubtarget.cpp AMDGPULowerIntrinsics.cpp

Re-apply demotion logic

This reverts commit 992e6130ed441b82490f9a6cf01f5bba38293e4e.
DeltaFile
+1,321-821llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
+29-24llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll
+20-7llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+10-0llvm/docs/AMDGPUUsage.rst
+2-4llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+4-0llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+1,386-8562 files not shown
+1,390-8588 files

FreeBSD/ports 116481e — lang/python312 Makefile distinfo, lang/python312/files patch-Modules__socketmodule.c

lang/python312: use upstream commits for divert(4) fix

Backport of:
https://github.com/python/cpython/pull/142993
https://github.com/python/cpython/pull/143514

PR: 298106
DeltaFile
+0-14lang/python312/files/patch-Modules__socketmodule.c
+5-1lang/python312/distinfo
+2-0lang/python312/Makefile
+7-153 files

FreeBSD/ports 63f69f8 — lang/python311 Makefile distinfo

lang/python311: fix recvfrom() and sendto() on divert(4) socket

Backport of:
https://github.com/python/cpython/pull/142993
https://github.com/python/cpython/pull/143514

PR: 298106
DeltaFile
+5-1lang/python311/distinfo
+3-0lang/python311/Makefile
+8-12 files

FreeBSD/src 90c8c8e — sys/netinet in.h

netinet: garbage collect __IPPROTO_DIVERT
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+0-2sys/netinet/in.h
+0-21 files

FreeBSD/src a20bbab — sys/netpfil/ipfw ip_fw_private.h

ipfw: re-arrange declarations so that they match comments

No functional change.
DeltaFile
+9-8sys/netpfil/ipfw/ip_fw_private.h
+9-81 files

LLVM/project 3514c68 — llvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Transforms/IndVarSimplify ult-nonneg-bound-implies-nonneg.ll

[SCEV] Derive x >=s 0 from x <u y when y is non-negative

If x <u y and y <=u 2^(n-1) (e.g. y >=s 0), then x >=s 0.

Prove this in SCEV's isImpliedCondBalancedTypes so a guard
like "start <u len" proves start >=s 0. This also covers
x <=u y with y up to INT_MAX, which reaches the implication
code canonicalized as x <u y + 1.

The query is proven from the derived fact via
isImpliedCondOperands, so weaker bounds (x >=s c, c <= 0) follow
too.

y is checked via ranges only, to keep compile time low.

Co-Authored-By: Claude Sonnet 5.5 <noreply at anthropic.com>
DeltaFile
+15-19llvm/unittests/Analysis/ScalarEvolutionTest.cpp
+19-0llvm/lib/Analysis/ScalarEvolution.cpp
+4-10llvm/test/Transforms/IndVarSimplify/ult-nonneg-bound-implies-nonneg.ll
+38-293 files

FreeBSD/ports 3b68346 — devel Makefile, devel/R-cran-pbapply distinfo pkg-descr

devel/R-cran-pbapply: New port: Add progress bar to '*apply' functions

PR:                     296811
Approved by:            jrm (mentor)
Differential Revision:  https://reviews.freebsd.org/D60708
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+16-0devel/R-cran-pbapply/Makefile
+6-0devel/R-cran-pbapply/pkg-descr
+3-0devel/R-cran-pbapply/distinfo
+1-0devel/Makefile
+26-04 files

FreeBSD/ports 220f9b4 — www/qt6-webengine Makefile

www/qt6-webengine: do not special-case the version of node on i386.

In the past the build of this port would hang when using the
then-current www/node22 on i386, but a test build on 14.4-i386
with multiple parallel jobs went fine.

PR:             299234
Approved by:    kde (makc)
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+1-10www/qt6-webengine/Makefile
+1-101 files

LLVM/project 40d9fbf — llvm/test/Transforms/IndVarSimplify ult-nonneg-bound-implies-nonneg.ll, llvm/unittests/Analysis ScalarEvolutionTest.cpp

[SCEV][NFC] Precommit tests for x <u y && y >=s 0 implying x >=s 0

SCEV derives x <s y from x <u y && y >=s 0, but not x >=s 0, so a loop
guarded by "start <u len" with a non-negative len does not prove
start >=s 0.

Add unit tests for isImpliedCond and the end-to-end guard queries, and
an IndVars lit test.
Checks SCEV cannot prove yet are marked FIXME.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+340-0llvm/test/Transforms/IndVarSimplify/ult-nonneg-bound-implies-nonneg.ll
+209-0llvm/unittests/Analysis/ScalarEvolutionTest.cpp
+549-02 files

FreeBSD/src 0571d8a — sys/powerpc/powerpc swtch64.S swtch32.S

powerpc: Avoid deadlock when CPUs exchange threads

The PowerPC context switch waited for the incoming thread to leave
blocked_lock before releasing the outgoing thread.  If two CPUs selected
each other's running threads concurrently, both CPUs waited for the
other to perform the release and neither could progress.  This appeared
as intermittent boot hangs under QEMU MTTCG when taskqueue threads were
bound to opposite CPUs.

8df2e5421468 ("powerpc: put the isync inside the TD_LOCK()...")
attempted to fix the same hang by moving isync into the polling loop.
That did not address the circular wait: isync cannot cause either CPU to
execute the release store after the loop.  It only added context
synchronization to failed iterations and changed timing. Move isync back
to the successful exit, which preserves acquire ordering for subsequent
context loads.

Match the ordering used by other architectures: publish the outgoing
thread's new lock before waiting for the incoming thread.  Apply the

    [20 lines not shown]
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+11-7sys/powerpc/powerpc/swtch64.S
+11-7sys/powerpc/powerpc/swtch32.S
+22-142 files

LLVM/project 33f9999 — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULowerIntrinsics.cpp SIMemoryLegalizer.cpp

Split demotion logic out
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+7-20llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+0-10llvm/docs/AMDGPUUsage.rst
+3-4llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll
+3-3llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
+4-2llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+2-3llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma-async.ll
+19-422 files not shown
+19-508 files

LLVM/project 4f58f66 — llvm/test/CodeGen/AMDGPU amdgpu-attributor-no-lds-dma.ll

Clean up lit tests
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+22-23llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-lds-dma.ll
+22-231 files

LLVM/project f0c5a19 — llvm/lib/Target/AMDGPU AMDGPUAttributor.cpp, llvm/test/CodeGen/AMDGPU annotate-kernel-features-hsa.ll annotate-kernel-features-hsa-call.ll

Rename attribute and clean up qualifying set of instructions

"no-async" was based on an imprecise use of the word "async", which also
confused me during its implementation, so I also removed
unintentionally-added intrinsics from the set of intrinsics this
attribute checks for.
DeltaFile
+0-286llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-async.ll
+241-0llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-lds-dma.ll
+21-21llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
+21-21llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+16-16llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
+13-13llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
+312-35733 files not shown
+414-46439 files

LLVM/project c86db7c — llvm/test/CodeGen/AMDGPU memory-legalizer-single-wave-workgroup-lds-dma-async.ll memory-legalizer-single-wave-workgroup-memops.ll

Bring attributor changes to this PR in the stack
DeltaFile
+4-3llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll
+3-3llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
+3-2llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma-async.ll
+10-83 files

LLVM/project faef630 — llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp

Remove unnecessary condition on ordering strength
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+1-8llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+1-81 files

LLVM/project 1b50303 — llvm/docs AMDGPUUsage.rst

Remove unnecessary paragraph
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+0-5llvm/docs/AMDGPUUsage.rst
+0-51 files