LLVM/project 712ec9ellvm/unittests/ExecutionEngine/Orc OrcCAPITest.cpp

[ORC] Fix OrcCAPITestBase.ExecutionTest on Darwin/arm64e (#223577)

Switch to ExecutorAddr::toPtr to sign the function pointer. We'll need a
C API solution for this eventually, but this will do for now to get the
test passing.

rdar://186687669
DeltaFile
+3-1llvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
+3-11 files

LLVM/project b557f07mlir/lib/Dialect/Tosa/Transforms TosaProfileCompliance.cpp

[mlir][tosa] Use optnone for compliance initialization under MSan (NFC) (#223586)

The compliance-map constructor includes a ~5,000-line generated
initializer.
Under MemorySanitizer, shadow and origin tracking instrumentation on
this single mega-function causes extreme compilation times (>3.5
minutes),
dominated by InstCombine (~68s) and greedy register allocation (~71s).

Recently, LLVM_ATTRIBUTE_MINSIZE was added to optimize for size, but
MSan
instrumentation still inflates the function enough to trigger severe
slowdowns in the backend.

Mark the constructor with optnone under LLVM_MEMORY_SANITIZER_BUILD to
skip
expensive optimization and register allocation passes, bringing
compilation
time under MSan down from 3m38s to ~30s.

    [5 lines not shown]
DeltaFile
+10-1mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
+10-11 files

LLVM/project d9ccd8dllvm/test/CodeGen/AMDGPU int_to_fp_narrow_i64.ll amdgcn.bitcast.512bit.ll

rebase now that dependencies have landed

Created using spr 1.3.8-beta.1
DeltaFile
+6,151-6,581llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+4,692-4,496llvm/test/CodeGen/AMDGPU/bf16.ll
+2,809-3,010llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,809-3,010llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+2,754-2,970llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+3,957-0llvm/test/CodeGen/AMDGPU/int_to_fp_narrow_i64.ll
+23,172-20,067956 files not shown
+65,988-58,570962 files

LLVM/project c77f51allvm/test/CodeGen/AMDGPU int_to_fp_narrow_i64.ll amdgcn.bitcast.512bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+6,151-6,581llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+4,692-4,496llvm/test/CodeGen/AMDGPU/bf16.ll
+2,809-3,010llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,809-3,010llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+2,754-2,970llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+3,957-0llvm/test/CodeGen/AMDGPU/int_to_fp_narrow_i64.ll
+23,172-20,067956 files not shown
+65,988-58,570962 files

LLVM/project cecd28dllvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.cpp, llvm/lib/TargetParser RISCVISAInfo.cpp

[RISCV] Select the capability ABI by default when the Y extension is enabled

computeDefaultABI() previously had no knowledge of the RVY (CHERI) base,
so a target with Y enabled and no explicit -target-abi
would fall back to the plain integer ABI instead of il32pc64(d)/
l64pc128(d).

This adds explicit non-RVY ABIs to two tests since otherwise those would
hit the assertion that the ABI is not supported yet. As the ABI does not
matter for these tests, we can safely use the non-RVY ones.

This change was created with the help of AI tools

Reviewed By: lenary

Pull Request: https://github.com/llvm/llvm-project/pull/213411
DeltaFile
+31-0llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+9-7llvm/lib/TargetParser/RISCVISAInfo.cpp
+13-0llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+9-2llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+2-2llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
+1-1llvm/test/CodeGen/RISCV/attributes.ll
+65-126 files

LLVM/project b355ea4clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/test/CIR/CodeGen call-conv-lowering-x86_64-non-byval.cpp call-conv-lowering-x86_64-union-tail-padding.c

[CIR] Accept a union whose members do not cover its declared size

Past two eightbytes the x86_64 classifier never reads a union's members
to pick a coerce type.  It either classifies the record as memory, which
needs no coerce type at all, or it classifies SSE followed by SSEUP, and
then the coerce type is a vector as wide as the whole record.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+162-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-union-tail-padding.c
+64-0clang/test/CIR/Transforms/abi-lowering/x86_64-aggregate-nyi.cir
+44-12clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+41-0clang/test/CIR/Transforms/abi-lowering/x86_64-union.cir
+24-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-non-byval.cpp
+335-125 files

FreeBSD/ports 649a169www/py-yt-dlp Makefile pkg-plist, www/yt-dlp Makefile distinfo

www/{,py-}yt-dlp: update 2026.06.09 → 2026.08.19

(cherry picked from commit ece2973bbf55587b226d09646fddbb2d041d3c0e)
DeltaFile
+3-3www/yt-dlp/distinfo
+3-3www/py-yt-dlp/distinfo
+2-3www/py-yt-dlp/pkg-plist
+1-1www/yt-dlp/Makefile
+1-1www/py-yt-dlp/Makefile
+10-115 files

FreeBSD/ports 91a4bfdwww/srt Makefile

www/srt: Remove duplicate option OPENSSL

PR:             298392
Reported by:    Daniel Engberg <diizzy at FreeBSD.org>
DeltaFile
+2-1www/srt/Makefile
+2-11 files

FreeBSD/ports f3d7e39misc/grok-build Makefile distinfo

misc/grok-build: update 1.0.25 → 1.0.30
DeltaFile
+5-5misc/grok-build/distinfo
+1-1misc/grok-build/Makefile
+6-62 files

FreeBSD/ports af4f629www/srt pkg-plist Makefile

www/srt: update 1.5.6 → 1.5.7
DeltaFile
+3-3www/srt/distinfo
+2-2www/srt/Makefile
+1-1www/srt/pkg-plist
+6-63 files

FreeBSD/ports 0a143eemisc/antigravity-cli Makefile distinfo

misc/antigravity-cli: update 1.2.1 → 1.2.3
DeltaFile
+5-5misc/antigravity-cli/distinfo
+2-2misc/antigravity-cli/Makefile
+7-72 files

FreeBSD/ports 8922aa9devel/zizmor pkg-descr Makefile, devel/zizmor/files patch-crates_zizmor_src_main.rs patch-crates_zizmor_Cargo.toml

devel/zizmor: Add port: Static analysis for GitHub Actions

zizmor is a static analysis tool for CI/CD systems.

It can find and fix security issues in common CI/CD setups, including
GitHub Actions, Dependabot, and pre-commit. Some of the things zizmor
finds:

- Template injection vulnerabilities, leading to attacker-controlled
  code execution
- Accidental credential persistence and leakage
- Excessive permission scopes and credential grants to runners
- Impostor commits and confusable git references
- ...and much more!

WWW: https://docs.zizmor.sh/
WWW: https://github.com/zizmorcore/zizmor
DeltaFile
+885-0devel/zizmor/distinfo
+441-0devel/zizmor/Makefile.crates
+54-0devel/zizmor/Makefile
+12-0devel/zizmor/pkg-descr
+11-0devel/zizmor/files/patch-crates_zizmor_Cargo.toml
+10-0devel/zizmor/files/patch-crates_zizmor_src_main.rs
+1,413-01 files not shown
+1,414-07 files

LLVM/project a9c42a7llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.h AMDGPUMemoryUtils.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Promote private objects into the VGPR address space via flag
DeltaFile
+279-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+138-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+1-27llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+19-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+16-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+453-315 files

LLVM/project 2763527llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Refuse promotion only when the object is live across a call
DeltaFile
+183-4llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+117-15llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+300-192 files

LLVM/project 28dce21llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Count the intrinsics that really become calls when refusing promotion
DeltaFile
+81-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+43-36llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+124-362 files

LLVM/project af902eallvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Carry null operands and intrinsic names across when promoting to VGPRs
DeltaFile
+145-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+42-2llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+187-22 files

LLVM/project c02ba15llvm/lib/Target/AMDGPU AMDGPUMachineInstrs.h SIInstructions.td, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-private-object-vgprs.mir

Propagate object liveness to every changed successor, not only back edges
DeltaFile
+30-44llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+25-34llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+56-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-private-object-vgprs.mir
+7-12llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-8llvm/lib/Target/AMDGPU/SIInstructions.td
+3-4llvm/lib/Target/AMDGPU/AMDGPUMachineInstrs.h
+125-1026 files

LLVM/project ff12bfdllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-budget.ll

Diagnose an object that does not fit the function's register budget
DeltaFile
+82-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-budget.ll
+36-13llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+118-132 files

LLVM/project 44f43e9llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-allocate.ll as-vgpr-across-call.ll

Do not add a second lifetime start when allocating VGPRs again
DeltaFile
+21-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+17-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+0-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+38-43 files

LLVM/project 770f8f6llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-across-call.ll as-vgpr-private-object-vgprs.mir

Allocate and reserve registers for address space 13 objects
DeltaFile
+340-0llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+178-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-object-regalloc.ll
+140-12llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+133-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+106-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-private-object-vgprs.mir
+80-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+977-1218 files not shown
+1,280-2324 files

LLVM/project ee78d38llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-asm-clobber.ll

Diagnose inline asm that clobbers a VGPR-memory object's registers
DeltaFile
+93-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-asm-clobber.ll
+31-5llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+124-52 files

LLVM/project f0ca5a6llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits.ll

Set up M0 for sub-dword VGPR-memory accesses in the custom inserter
DeltaFile
+9-11llvm/lib/Target/AMDGPU/AMDGPULowerIdxOps.cpp
+5-9llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+7-6llvm/lib/Target/AMDGPU/SIInstructions.td
+3-7llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+5-5llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits.ll
+3-5llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+32-431 files not shown
+35-477 files

LLVM/project 5d5a262llvm/cmake/modules AddLLVM.cmake

[CMake] Factor check- target deps to reduce build.ninja size by 45%

Many LLVM developers are not aware, but our lit CMake logic creates a
check-* target for every eligible subdirectory inside a lit test suite.
There are thousands of these targets; in the benchmark configuration:

```
❯ ninja -C build -t targets all | grep '^check-' | wc -l
2667
```

Chris Bieneman originally added this feature in March 2015. The original
change suppressed these targets for Xcode and Visual Studio because the
target clutter hurt IDE usability; rL344555 later generalized that
behavior behind LLVM_ENABLE_IDE.

When using the Ninja generator, each of these check-${proj}-${subdir}
targets repeats its suite's transitive test dependencies, like so:


    [52 lines not shown]
DeltaFile
+62-12llvm/cmake/modules/AddLLVM.cmake
+62-121 files

FreeBSD/ports baf7cfbwww/srt Makefile

www/srt: Update WWW

The previous commit for 1.5.6 resolved the following CVEs:
* CVE-2026-55869: Heap-Based Buffer Overflow in KMREQ Handling
* CVE-2026-55868: Encryption State Machine Downgrade

ChangeLog: https://github.com/Haivision/srt/releases/tag/v1.5.6
(cherry picked from commit 88c18f3c4026ce1b5bdf10c758e5ea31da414706)
DeltaFile
+3-2www/srt/Makefile
+3-21 files

FreeBSD/ports 1b69519www/srt pkg-plist Makefile

www/srt: add SRTFFPLAY option

PR:             293009
(cherry picked from commit 7bf6e3c5bc1be48baacd5c7256c7a2621b2842ac)
DeltaFile
+9-3www/srt/Makefile
+1-1www/srt/pkg-plist
+10-42 files

FreeBSD/ports 97159ddwww/srt pkg-plist Makefile

www/srt: update 1.5.5 → 1.5.6

(cherry picked from commit 52763c825cdc227b0d635c5210deb94870fb4da2)
DeltaFile
+3-3www/srt/distinfo
+3-2www/srt/Makefile
+1-1www/srt/pkg-plist
+7-63 files

LLVM/project 3493720llvm/lib/Transforms/InstCombine InstCombineAndOrXor.cpp, llvm/test/Transforms/InstCombine trunc.ll

[InstCombine] Add fold combining adjacent extracted bit fields to restore optimization for separate truncations (#219598)

This restores the InstCombine optimization that was lost (regression)
starting from Clang 14, when assembling adjacent bit fields extracted
from a wider integer.

The fold combines:
```
(trunc (lshr X, S) & M0) | (lshr (trunc X), S & M1) --> (trunc (lshr X, S) & (C0 | C1))
```
The fold handles both orderings. I implemented tests for this fold in
trunc.ll

alive2 proof: https://alive2.llvm.org/ce/z/rPQN4D 

Fixes #215254
DeltaFile
+136-0llvm/test/Transforms/InstCombine/trunc.ll
+23-0llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+159-02 files

LLVM/project 61be2c5llvm/unittests/Target/AMDGPU VGPRAsMemory.cpp

Pin the width guard that keeps sub-dword accesses out of aliasing decisions
DeltaFile
+70-0llvm/unittests/Target/AMDGPU/VGPRAsMemory.cpp
+70-01 files

LLVM/project c412e72llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-divergent.ll

Treat a sub-dword VGPR-memory load as divergent too
DeltaFile
+83-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-divergent.ll
+2-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+85-12 files

LLVM/project d0a16b6llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-index-demanded-bits.ll

Regenerate the demanded-bits expectations for the gfx1250 entry sequence
DeltaFile
+24-16llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-index-demanded-bits.ll
+24-161 files