OpenZFS/src 3fffe4emodule Makefile.in

Fix --enable-invariants on FreeBSD

The make symbols were never getting forwarded to the correct make
subprocess.  As far as I can tell, this has never worked.  Either that,
or something has changed in the behavior of make.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Alan Somers <asomers at gmail.com>
Closes #18131
DeltaFile
+3-2module/Makefile.in
+3-21 files

OpenZFS/src 09e4e01module/zfs zfs_ioctl.c, tests/zfs-tests/tests/functional/cli_root/zpool_create zpool_create_tempname.ksh

Fix history logging for `zpool create -t`

`zpool create` is supposed to log the command to the new pool’s history,
as a special record that never gets evicted from the ring buffer. but
when you create a pool with `zpool create -t`, no such record is ever
logged (#18102). that bug may be the cause of issues like #16408.

`zpool create -t` (83e9986f6eefdf0afc387f06407087bba3ead4e9) and `zpool
import -t` (26b42f3f9d03f85cc7966dc2fe4dfe9216601b0e) are both designed
to override the on-disk zpool property `name` with an in-core
“temporary” name, but they work somewhat differently under the hood.

importing with a temporary name sets `spa->spa_import_flags |=
ZFS_IMPORT_TEMP_NAME` in ZFS_IOC_POOL_IMPORT, which tells
spa_write_cachefile() and spa_config_generate() to use the
ZPOOL_CONFIG_POOL_NAME in `spa->spa_config` instead of `spa->spa_name`.

creating with a temporary name permanently(!) sets the internal zpool
property `tname` (ZPOOL_PROP_TNAME) in the `zc->zc_nvlist_src` of

    [17 lines not shown]
DeltaFile
+8-2module/zfs/zfs_ioctl.c
+2-0tests/zfs-tests/tests/functional/cli_root/zpool_create/zpool_create_tempname.ksh
+10-22 files

LLVM/project 8ac6c4aclang/test/Frontend rewrite-includes-bom.c

[Clang] Fix rewrite-includes-bom.c to use POSIX-compliant regex (#176043)

As `\s` is a GNU extension, it is not supported by the system grep on
AIX and thus fails in the
[buildbot](https://lab.llvm.org/buildbot/#/builders/64/builds/6835):

```
******************** TEST 'Clang :: Frontend/rewrite-includes-bom.c' FAILED ********************
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
cat /home/llvm/llvm-external-buildbots/workers/aix-ppc64/clang-ppc64-aix/llvm-project/clang/test/Frontend/Inputs/rewrite-includes-bom.h | od -t x1 | grep -q 'ef\s*bb\s*bf'
# executed command: cat /home/llvm/llvm-external-buildbots/workers/aix-ppc64/clang-ppc64-aix/llvm-project/clang/test/Frontend/Inputs/rewrite-includes-bom.h
# executed command: od -t x1
# executed command: grep -q 'ef\s*bb\s*bf'
# note: command had no output on stdout or stderr
# error: command failed with exit status: 1
--

    [6 lines not shown]
DeltaFile
+2-2clang/test/Frontend/rewrite-includes-bom.c
+2-21 files

LLVM/project 95a1581llvm/include/llvm/CodeGen TargetLowering.h

[CodeGen] Remove legacy getTgtMemIntrinsic overload

It is now fully unused.

commit-id:028dd72d
DeltaFile
+1-19llvm/include/llvm/CodeGen/TargetLowering.h
+1-191 files

LLVM/project 4fbc3c6llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU waitcnt-unscoped.ll llvm.amdgcn.load.to.lds.ll

[AMDGPU] Return two MMOs for load-to-lds and store-from-lds intrinsics

Accurately represent both the load and the store part of those
intrinsics.

The test changes seem to be mostly fairly insignificant changes caused by
subtly different scheduler behavior.

commit-id:0269189c
DeltaFile
+61-51llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-4llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll
+2-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
+2-4llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
+68-634 files

LLVM/project 1c445d8llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/lib/Target/AMDGPU SIISelLowering.cpp

[CodeGen] Refactor targets to override the new getTgtMemIntrinsic overload (NFC)

This is a fairly mechanical change. Instead of returning true/false,
we either keep the Infos vector empty or push one entry.

commit-id:c7770af6
DeltaFile
+99-53llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+78-59llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+40-21llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+36-22llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+36-22llvm/lib/Target/ARM/ARMISelLowering.cpp
+26-18llvm/lib/Target/X86/X86ISelLowering.cpp
+315-19516 files not shown
+397-26822 files

LLVM/project 09515b2llvm/include/llvm/CodeGen SelectionDAGNodes.h TargetLowering.h, llvm/lib/CodeGen/GlobalISel IRTranslator.cpp

[CodeGen] Add getTgtMemIntrinsic overload for multiple memory operands (NFC)

There are target intrinsics that logically require two MMOs, such as
llvm.amdgcn.global.load.lds, which is a copy from global memory to LDS,
so there's both a load and a store to different addresses.

Add an overload of getTgtMemIntrinsic that produces intrinsic info in a
vector, and implement it in terms of the existing (now protected)
overload.

GlobalISel and SelectionDAG paths are updated to support multiple MMOs.
The main part of this change is supporting multiple MMOs in
MemIntrinsicNodes.

Converting the backends to using the new overload is a fairly mechanical step
that is done in a separate change in the hope that that allows reducing merging
pains during review and for downstreams. A later change will then enable
using multiple MMOs in AMDGPU.

commit-id:b4a924aa
DeltaFile
+83-32llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+64-25llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+38-29llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+19-28llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+20-3llvm/include/llvm/CodeGen/TargetLowering.h
+17-3llvm/include/llvm/CodeGen/SelectionDAG.h
+241-1203 files not shown
+246-1239 files

LLVM/project e08687bllvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx10_asm_vop1.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge branch 'main' into users/abhinavgaba/udp-fallback-2
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+4,672-4,671llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+34,743-34,7392,434 files not shown
+224,928-159,2972,440 files

LLVM/project 3a9e386llvm/include/llvm/Frontend/OpenMP OMPConstants.h, offload/include omptarget.h

[OpenMP][Offload] Add FB_NULLIFY map-type for `use_device_ptr(fb_nullify)`. (1/4) (#169603)

Depends on #174659.

This PR adds a new map-type bit to control the fallback behavior when
when a pointer lookup fails.

For now, this is only meaningful with `RETURN_PARAM`, and can be used
for `need_device_ptr` (for which the default is to use `nullptr` as the
result
when lookup fails), and OpenMP 6.1's `use_device_ptr(fb_nullify)`.

Eventually, this can be extended to work with assumed-size maps on
`target`
constructs, to control what the argument should be set to when lookup
fails (the OpenMP spec does not have a way to control that yet).

Dependent PR: #170578.
DeltaFile
+14-8offload/libomptarget/omptarget.cpp
+4-0llvm/include/llvm/Frontend/OpenMP/OMPConstants.h
+4-0offload/include/omptarget.h
+22-83 files

LLVM/project d446929libcxx/include/__bit byteswap.h, libcxx/src locale.cpp

[libc++] Add parentheses around shift operations in bitwise expressions (#175407)

This improves consistency within files that already use this style.
DeltaFile
+12-12libcxx/src/locale.cpp
+3-3libcxx/test/support/concat_macros.h
+1-1libcxx/include/__bit/byteswap.h
+16-163 files

LLVM/project d0c8735llvm/lib/Transforms/Vectorize VPlanUtils.cpp

[VPlan] Handle constant step for VPScalarIVSteps in getSCEVExpr (NFC).

Update getSCEVExprForVPValue to handle VPScalarIVSteps with any constant
step. getSCEVExprForVPValue computes the SCEV for lane 0, so we can
simply return the IV operand, truncated/extended as needed.

This should be NFC and is tested via the VPlan-based cost-model, which
should compute costs matching the legacy cost model.
DeltaFile
+2-4llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+2-41 files

LLVM/project a331728.github/workflows release-lit.yml release-tasks.yml

worklows/release-tasks: Remove the release-lit workflow (#174644)

This hasn't been working for a while, and I think we should wait until
lit is part of the llvm organization on pypi before we start trying to
automate its release again.
DeltaFile
+0-79.github/workflows/release-lit.yml
+0-10.github/workflows/release-tasks.yml
+0-892 files

GhostBSD/networkmgr 106d5ccNetworkMgr configuration.py query.py

Merge pull request #121 from Kernel-Error/feature/ipv6-support

Add IPv6 configuration support
DeltaFile
+167-44NetworkMgr/configuration.py
+106-0NetworkMgr/query.py
+61-0NetworkMgr/net_api.py
+334-443 files

FreeBSD/ports 81ff4cfdevel Makefile, devel/libigloo Makefile pkg-plist

devel/libigloo: New port: Generic C framework developed and used by the Icecast project

Abstracts memory allocation, provides high level types (including
support to define such types), and provides a library for common
programming problems.
DeltaFile
+27-0devel/libigloo/Makefile
+20-0devel/libigloo/pkg-plist
+3-0devel/libigloo/distinfo
+2-0devel/libigloo/pkg-descr
+1-0devel/Makefile
+53-05 files

LLVM/project 8c5352cllvm/test/Transforms/LoopVectorize cast-induction.ll select-folds.ll, llvm/test/Transforms/LoopVectorize/AArch64 hoist-predicated-loads-scalable.ll

[LV] Add additional cost and folding test coverage. (NFC)
DeltaFile
+331-56llvm/test/Transforms/LoopVectorize/cast-induction.ll
+259-0llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
+78-0llvm/test/Transforms/LoopVectorize/select-folds.ll
+65-0llvm/test/Transforms/LoopVectorize/AArch64/hoist-predicated-loads-scalable.ll
+733-564 files

FreeBSD/src eb9c65arelease Makefile.ec2

EC2: Add extra SSM Parameter names for releases

Record releases in the SSM Parameter Store not just as e.g.
  /aws/service/freebsd/arm64/small/ufs/15.0/RELEASE
but also as .../RELEASE/latest, e.g.
  /aws/service/freebsd/arm64/small/ufs/15.0/RELEASE/latest

The latter parameters will be updated when new AMIs are built with
security and errata updates appplied, and have been backfilled for
15.0.

MFC after:      3 days
MFC to:         stable/15 (14.x will not get security-update AMIs)
Sponsored by:   Amazon

(cherry picked from commit b558c92fd0005d311edbcd02953c17d4a34fb909)
DeltaFile
+5-1release/Makefile.ec2
+5-11 files

HardenedBSD/src b20d0f0release/tools arm.subr

HBSD: Resolve merge conflict

Signed-off-by:  Shawn Webb <shawn.webb at hardenedbsd.org>
DeltaFile
+1-7release/tools/arm.subr
+1-71 files

HardenedBSD/src 152cf02libexec/nuageinit nuageinit nuageinit.7, release/tools arm.subr vagrant.conf

Merge remote-tracking branch 'origin/freebsd/15-stable/main' into hardened/15-stable/main

Conflicts:
        release/tools/arm.subr (unresolved)
DeltaFile
+1,082-232share/misc/pci_vendors
+172-102libexec/nuageinit/nuageinit
+27-15libexec/nuageinit/nuageinit.7
+9-2share/misc/usb_vendors
+6-4release/tools/arm.subr
+1-7release/tools/vagrant.conf
+1,297-3625 files not shown
+1,302-37311 files

FreeNAS/freenas 83a8a0esrc/middlewared/middlewared/plugins dlm.py

In local_reset start any stopped lockspace on a BlockingIOError
DeltaFile
+9-1src/middlewared/middlewared/plugins/dlm.py
+9-11 files

LLVM/project 2fe9d90clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 sse41-builtins.c avx2-builtins.c

[CIR] Upstream CIR codegen for blend x86 builtins (#174236)

Part of https://github.com/llvm/llvm-project/issues/167752.
DeltaFile
+52-5clang/test/CIR/CodeGenBuiltins/X86/sse41-builtins.c
+42-0clang/test/CIR/CodeGenBuiltins/X86/avx2-builtins.c
+24-0clang/test/CIR/CodeGenBuiltins/X86/avx-builtins.c
+15-5clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+133-104 files

LLVM/project dc133c9clang/lib/Driver Driver.cpp, clang/lib/Driver/ToolChains Gnu.cpp CommonArgs.cpp

Revert "[clang][RISCV] Add big-endian RISC-V target support" (#176039)

Reverts llvm/llvm-project#165599
DeltaFile
+0-95clang/test/Driver/riscv-be.c
+5-34clang/lib/Driver/ToolChains/Gnu.cpp
+4-22clang/lib/Driver/Driver.cpp
+0-12clang/test/CodeGen/riscv-be-data-layout.c
+0-10clang/lib/Driver/ToolChains/CommonArgs.cpp
+2-7clang/lib/Driver/ToolChains/Clang.cpp
+11-18030 files not shown
+17-21836 files

LLVM/project cc1e10dllvm/lib/Target/AMDGPU AMDGPU.td GCNSubtarget.h, llvm/test/CodeGen/AMDGPU branch-relaxation-gfx1250.ll

[AMDGPU] Disable s_add_pc_i64 instruction (#175644)

s_add_pc_i64 instruction is broken on gfx1250. Disable it by default.
DeltaFile
+835-38llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
+6-0llvm/lib/Target/AMDGPU/AMDGPU.td
+3-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+845-394 files

LLVM/project 2bf35f3llvm/lib/Target TargetLoweringObjectFile.cpp, llvm/test/CodeGen/AArch64 ptrauth-global-no-pic.ll ptrauth-irelative.ll

[PAC][ELF] Place AUTH constants in .data.rel.ro for position dependent code (#150418)

For AArch64 target machine, effective relocation model on Windows and
Darwin is always PIC, while for ELF targets Static is used when
DynamicNoPIC is requested (see `getEffectiveRelocModel` in
AArch64TargetMachine.cpp).

This resulted in using .rodata section for AUTH constants, which is
wrong since these are filled with AUTH dynamic relocs and require the
section to be writeable during dynamic relocation resolving.

This patch adds a check ensuring if the constant itself or one of the
nested constants are AUTH ones. If so, use .data.rel.ro section.
DeltaFile
+53-0llvm/test/CodeGen/AArch64/ptrauth-global-no-pic.ll
+19-0llvm/lib/Target/TargetLoweringObjectFile.cpp
+8-8llvm/test/CodeGen/AArch64/ptrauth-irelative.ll
+80-83 files

LLVM/project aac296bclang/include/clang/Basic BuiltinsAMDGPU.td

[AMDGPU][NFC] Change AMDGPU builtins to use ExtVector (#176033)

Summary:
These currently use the GNU vectors, not the OpenCL vectors, which is
strange.
DeltaFile
+460-460clang/include/clang/Basic/BuiltinsAMDGPU.td
+460-4601 files

LLVM/project 523215fllvm/lib/Target/X86 X86SpeculativeLoadHardening.cpp X86.h

[X86][NewPM] Port x86-slh to new pass manager (#176014)

DeltaFile
+21-9llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+10-2llvm/lib/Target/X86/X86.h
+2-2llvm/lib/Target/X86/X86TargetMachine.cpp
+1-1llvm/lib/Target/X86/X86PassRegistry.def
+34-144 files

LLVM/project 4d9624cllvm/lib/Transforms/Instrumentation MemorySanitizer.cpp

[msan][NFCI] Refactor visitAnd body into helper function (#176031)

This allows reuse of the core visitAnd logic e.g., in
handleVectorPmaddIntrinsic().
DeltaFile
+34-30llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+34-301 files

LLVM/project 2c387b5clang/lib/Driver Driver.cpp, clang/lib/Driver/ToolChains Gnu.cpp CommonArgs.cpp

Revert "[clang][RISCV] Add big-endian RISC-V target support (#165599)"

This reverts commit 2bce962db211e20425c6d89afb56295c7022ee94.
DeltaFile
+0-95clang/test/Driver/riscv-be.c
+5-34clang/lib/Driver/ToolChains/Gnu.cpp
+4-22clang/lib/Driver/Driver.cpp
+0-12clang/test/CodeGen/riscv-be-data-layout.c
+0-10clang/lib/Driver/ToolChains/CommonArgs.cpp
+2-7clang/lib/Driver/ToolChains/Clang.cpp
+11-18030 files not shown
+17-21836 files

LLVM/project b3f2b19clang/include/clang/Options Options.td

Update the comment for -fpartition-static-data-sections
DeltaFile
+1-1clang/include/clang/Options/Options.td
+1-11 files

OpenBSD/src BfrefcOsys/arch/amd64/include cpu.h

   Increase MAXCPUs on amd64 to 255

   Now that we have larger bitmask support for more than 64 CPUs, we can increase
   the max to 255. 255 is the max that xapic can support; this number can be
   bumped later if we want to discriminate x2apic vs xapic.

   with input from and ok deraadt. also ok kettenis
VersionDeltaFile
1.183+2-2sys/arch/amd64/include/cpu.h
+2-21 files

SmartOS/live a974217src manifest

OS-8711 Add cloudinit module to live image manifest
DeltaFile
+4-0src/manifest
+4-01 files