[mlir][SPIR-V] Dispatch autogen serialization through a TypeID table (#236992)
Ops were matched by a linear isa chain over 408 op types
TypeID map lookup gives identical output and lower wall time on
synthetic modules
`mlir-translate --serialize-spirv` results on artificial input:
| Funcs | Runs | Before | After | Change |
|------:|-----:|----------:|----------:|-------:|
| 1 | 300 | 3.07 ms | 3.00 ms | -2.3% |
| 10 | 300 | 6.45 ms | 5.93 ms | -7.9% |
| 100 | 100 | 39.68 ms | 34.59 ms | -12.8% |
| 1000 | 40 | 236.52 ms | 215.34 ms | -9.0% |
| 1500 | 30 | 668.85 ms | 595.77 ms | -10.9% |
clk: rockchip: Add the MMC phase clock
Add a clock node type for the Rockchip MMC sample and drive clocks. These
clocks have a phase in degrees controlled by a delay line and a fine-grained
phase selector, and implement the new clknode phase methods.
Reviewed by: mmel
Differential Revision: https://reviews.freebsd.org/D60886
mmccam: Add a helper to change the host settings
The same five lines to build and send an XPT_SET_TRAN_SETTINGS request to the
controller were repeated for the bus timing, bus width, VCCQ and clock
changes. Add sdda_set_host_ios() and use it at those places.
No functional change.
Reviewed by: bz
Differential Revision: https://reviews.freebsd.org/D60921
clk: Add a clknode method to get and set the phase
Add clknode_get_phase/clknode_set_phase (and the clk_get_phase and
clk_set_phase consumer API) so that clocks which can shift their phase,
such as the MMC sample and drive clocks of some SoCs, can expose it.
Reviewed by: mmel
Differential Revision: https://reviews.freebsd.org/D60883
[AMDGPU] Make V_INTERP_P1_F32_16bank isCodeGenOnly. NFCI. (#231988)
V_INTERP_P1_F32_16bank is only needed for codegen, to add an earlyclobber
constraint on chips with 16-bank LDS. It was marked isAsmParserOnly to
avoid decoding conflicts with V_INTERP_P1_F32 in the disassembler, but
that left it visible to the asm matcher. The has16BankLDS and
has32BankLDS predicates are not assembler predicates, so the asm matcher
could not tell the two apart and picked the 16bank version on every target.
Use isCodeGenOnly instead, which hides it from both the asm matcher and
the disassembler. The encoding is the same so this does not change the
assembler output.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
[RISCV] Wire up GISel pipeline
Now that all the GISel passes are ported, we can wire up the GISel
pipeline.
Reviewers: wangpc-pp, topperc, lenary
Pull Request: https://github.com/llvm/llvm-project/pull/236158
[mlir][linalg] Hoist pad constants before fusion (#236686)
The pad fusion pattern can use a constant that is still inside the pad
region. Move it out before creating `linalg.fill`, so replacing the pad
does not leave a dangling use.
Fixes #236378.
disallow remote removal of PKCS#11 providers from ssh-agent by
default, as this permits an attacker with access to a forwarded agent
a silly path-validity oracle. It's better just to be symmetric with
the restrictions on adding providers.
Note: a user of a forwarded agent can still remove a provider's _keys_
as it is important that access to keys can be easily revoked, this just
block removing entire providers by name.
Anthropic ANT-2026-DYLIZ0VY
