Make systemd-udev-settle optional for the import units
systemd-udev-settle.service has been deprecated for years, recent
systemd releases warn about it at boot, and distributions have begun
shipping without it, which turns the hard Requires= in
zfs-import-cache and zfs-import-scan into a broken import: a
Requires= on a masked or removed unit keeps the service from ever
starting. Issue #10891.
Demote the dependency to Wants= and keep the After= ordering. Where
the settle unit exists and completes, the boot is what it always
was: Wants= pulls settle in, the import waits for it, and the
device-symlink guarantee it provided is intact. Where it is masked
or gone the wish is quietly dropped and the import runs anyway,
which beats not importing at all. One deliberate behavior change:
if settle itself fails, on a system so large that enumeration
overruns its timeout, the old Requires= cancelled the import while
the new units go ahead at the timeout mark with whatever has been
enumerated by then.
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[lldb][elf-core] Populate memory region names from NT_FILE (#212666)
## Summary
`ProcessElfCore` already parses `NT_FILE`, but its cached `PT_LOAD`
memory-region entries did not retain their backing filenames.
- cache a complete `MemoryRegionInfo` for each `PT_LOAD` instead of
rebuilding one from a custom permissions/name record on every query
- associate an `NT_FILE` pathname when the `PT_LOAD` and `NT_FILE`
starts match; their ends may differ, while a `PT_LOAD` beginning inside
an `NT_FILE` range remains unnamed
- finalize names and memory-tag state after all program headers are
parsed, making the result independent of `PT_LOAD` and `PT_NOTE`
ordering
- preserve regions with `p_filesz == 0` and return the cached region
directly from `DoGetMemoryRegionInfo`
- add API coverage for the same-start/different-end case, an interior
unnamed region, and an unnamed NT_FILE-only tail
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[AMDGPU] Model WMMA co-execution windows in the scheduler for gfx1250
WMMA instructions in gfx1250 expose an execution window during which
only certain other instruction classes may co-execute. Teach the hazard
recognizer about those windows so the scheduler can fill co-execution slots and
account for the resulting stalls. This adds a preRA hazard recognizer
mode.
Add AMDGPUCoExecInfo.h, a shared model of a co-execution window: the
per-stage capability bitmask, the stage types (CoExecStageType), and
CoExecInfo, which maps a multi-cycle instruction to its per-cycle slot
pattern via getCoExecInfo(). InstructionFlavor and its helpers move here
from AMDGPUCoExecSchedStrategy.h with no functional change so they can
be shared by the scheduler and the hazard recognizer.
RuntimeLibcalls: Add generic FCMP3_F* three-way compare for single-symbol ABIs (#211618)
MSP430's __mspabi_cmpd/__mspabi_cmpf are one three-way compare symbol
serving every predicate, previously modeled as six suffixed impls each. Replace
them with a single generic operator FCMP3_*, and give softenSetCCOperands a
3rd lowering option. After the boolean O*_F* and the per-predicate
FCMP3_<pred>_F* helpers, use the generic FCMP3_F* helper tested with the predicate's
condition code.
Also opt __nedf2 out of the MSP430 default set: it was the only libgcc
F64 compare not already opted out, so it would otherwise provide
FCMP3_UNE_F64 and win over __mspabi_cmpd for not-equal.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[AArch64][GlobalISel] Cleanup old selection code for G_OR and fp instructions. (#213869)
G_OR can be selected via tablegen patterns, and other fp elements of
selectBinOp were no longer used. unsupportedBinOp was just testing
things that should always be true.
[CodeGen] ReplaceWithVeclib assertion failure with invalid intrinsic (#211352)
Commit f6a359f (#194639) removed an intrinsic ID check against
Intrinsic::not_intrinsic.
This check is needed because a call instruction can be cast to an
intrinsic instruction if the called function's name starts with "llvm."
(see llvm::Function::isIntrinsic).
This means if ReplaceWithVeclib is given an invalid intrinsic, it will
fail with an assertion failure.
Hexagon: Stop excluding some generic compiler-rt functions from libcalls
RuntimeLibcalls should indicate any function that exists and is callable.
Historically the list of library functions was conflated with the library
functions which should be used, so the library definition was complicated
by excluding the overridden cases. My reading of the compiler-rt sources is
that the generically named functions are built alongside the __hexagon
prefixed variants. e.g., __divsi3 and __hexagon_divsi3 both exist.
It will simplify future libcall work the fewer special case target exclusions
there are, so allow the functions to be defined and apply the selection
preference for the __hexagon prefixed versions in LibcallLoweringInfo.
I do question why compiler-rt is built this way; why doesn't the hexagon
just replace the standard entrypoint names with the target implementations?
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Add PISA register file, instruction set, and MC layer
Add the PISA register file and register-bank descriptions, the instruction
formats and definitions, and the MC/assembly layer (instruction printer,
register and code encoders, target streamer, MC target description and the
supporting enums), replacing the stub descriptions from
the initial target skeleton.
This provides the instruction-set description and assembly-emission
foundation. The GlobalISel lowering and instruction selection that consume it
are added in the following changes.
RuntimeLibcalls: Add sqrtf to the Hexagon runtime libcall set (#210909)
The library definitions go out of the way to avoid adding sqrtf, in
favor of __hexagon_sqrtf. I'm assuming that libm does provide sqrtf,
it just happens that there is a more-preferred function to use.
RuntimeLibcallsInfo should express the full set of functions that do exist,
and LibcallLoweringInfo should express the preference for which calls
should be used.
By the current ordering rules, it just so happens __hexagon_sqrtf will
win out for SQRT_F32. Add this to avoid a special case to faciliate future
libcall improvements.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
resterm: Update to 0.51.3
Fixed
Text wrapping
The wrapper walked text one rune at a time, which broke down on anything past plain ASCII. Most of the time invisible, but it was an real bug. It now works in grapheme clusters.
* Emoji sequences, combining accents and joined characters no longer get cut in half at a wrap point.
* Zero-width runes no longer count as a cell, so lines containing combining marks stop wrapping earlier than they should have.
* Double-width characters (CJK and similar) can no longer push a row past the pane width. A row that overflowed got wrapped a second time by the terminal, which put the cursor and selection on the wrong line.
* A character too wide to fit beside an indent now moves down whole, and if it still does not fit, the indent is dropped rather than overflowing the row.
* A character wider than the entire row is placed on a row of its own instead of looping.
Row mapping was counted from the size of the output buffer. Blank lines add no bytes, so they were skipped and the map claimed more rows than existed. Cursor movement and selection in bodies with blank lines landed one or more lines off. Rows are counted directly now.
Color handling had two leaks:
* A reset arriving after the last visible character on a line was dropped together with the empty continuation row it landed on, so the color carried into everything below it.
* An escape sequence that appeared inside a run of whitespace was discarded when that whitespace was trimmed at a wrap point.
Also in this area:
* Pre mode no longer produces rows containing only indentation.
* CRLF, control bytes and invalid UTF-8 no longer throw off width accounting or get dropped from the output.
* Extended color codes such as ESC[38;5;0m are read as a color, not as a reset.
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Add PISA target registration and backend stub
Register the Intel GPU portable ISA (PISA) target. Add the pisa Triple
arch, data layout, and a minimal MC/TargetMachine skeleton.
