LLVM/project 1774a54llvm/lib/Target/NVPTX NVPTXISelLowering.cpp, llvm/test/CodeGen/NVPTX atomicrmw-ignore-denormal-mode.ll

[NVPTX] Honor !atomic.ignore.denormal.mode on atomicrmw fadd

PTX atom.add has a fixed denormal behavior that the program cannot
control: atom.add.f32 flushes denormals on global memory but not on
shared, and atom.add.f16 never flushes. When that disagrees with the
function's denormal mode, the backend expands the atomic into a CAS loop
so the denormal behavior is preserved.

!atomic.ignore.denormal.mode says the denormal behavior of this
particular atomic does not matter, so use the native instruction even
when it disagrees. This is the same thing -nvptx-allow-ftz-atomics does,
except per-instruction instead of per-compilation, which lets a frontend
opt in only the operations it knows about -- notably CUDA's atomicAdd(),
which is defined in terms of atom.add.

Note that -nvptx-allow-ftz-atomics defaults to true, so the new behavior
is only observable with -nvptx-allow-ftz-atomics=false.

Co-authored-by: Artem Belevich <tra at google.com>
DeltaFile
+258-0llvm/test/CodeGen/NVPTX/atomicrmw-ignore-denormal-mode.ll
+11-3llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+269-32 files

LLVM/project 7c7705bclang/lib/CodeGen TargetInfo.cpp TargetInfo.h, clang/lib/CodeGen/TargetBuiltins NVPTX.cpp

[clang][NVPTX] Emit !atomic.ignore.denormal.mode for CUDA atomics

CUDA's atomicAdd() family is defined in terms of PTX atom.add, whose
denormal behavior is fixed by the hardware. Without any annotation the
backend has to assume the function's denormal mode must be honored and
expands these into CAS loops whenever the two disagree. Mark them with
!atomic.ignore.denormal.mode so the native instruction is used.

That covers the __nvvm_atom_*_add_gen_f builtins that atomicAdd(),
atomicAdd_block() and atomicAdd_system() are written in terms of, plus
C11/C++11 atomics under -fatomic-ignore-denormal-mode and the
[[clang::atomic(ignore_denormal_mode)]] attribute, which requires
teaching the NVPTX target about AtomicOptions.

The condition for when the metadata is meaningful is now shared with the
AMDGPU and SPIR-V targets in addAtomicIgnoreDenormalModeMetadata(). It
takes an AllowHalf flag because whether f16 denormals are observable is
target specific: PTX exposes no FTZ control for f16 operations, so
atom.add.f16 never flushes and the opt-in is meaningful there, whereas

    [3 lines not shown]
DeltaFile
+321-0clang/test/CodeGenCUDA/atomic-ignore-denormal-mode-nvptx.cu
+19-4clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
+18-0clang/lib/CodeGen/TargetInfo.h
+15-0clang/lib/CodeGen/TargetInfo.cpp
+12-0clang/lib/CodeGen/Targets/NVPTX.cpp
+2-4clang/lib/CodeGen/Targets/SPIR.cpp
+387-85 files not shown
+402-1711 files

LLVM/project cdec519mlir/include/mlir/Dialect/LLVMIR LLVMOpBase.td LLVMOps.td, mlir/lib/Dialect/LLVMIR/IR LLVMDialect.cpp

[mlir][LLVM] Add ignore_denormal_mode UnitAttr to LLVM::AtomicRMWOp
DeltaFile
+22-5mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+8-7mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+8-0mlir/test/Dialect/LLVMIR/invalid.mlir
+7-0mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
+0-6mlir/lib/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.cpp
+4-0mlir/test/Target/LLVMIR/Import/instructions.ll
+49-184 files not shown
+56-2210 files

LLVM/project 0479ccdllvm/test/Transforms/AtomicExpand/AMDGPU expand-atomic-v2f16-agent.ll expand-atomic-f64-system.ll

[IR] Generalize !amdgpu.ignore.denormal.mode into !atomic.ignore.denormal.mode

The !amdgpu.ignore.denormal.mode metadata tells the backend that an
atomicrmw fadd need not honor the function's denormal mode, so a native
atomic instruction whose denormal behavior is fixed in hardware may be
used instead of a CAS loop. Nothing about that is AMDGPU specific: NVPTX
has exactly the same problem with atom.add, whose FTZ behavior depends on
the address space and cannot be controlled.

Promote it to a target independent fixed metadata kind,
!atomic.ignore.denormal.mode, and switch the AMDGPU, SPIR-V and OpenMP
producers and consumers over to it. Document it in LangRef, and point
AMDGPUUsage at that description rather than duplicating it.

Existing IR keeps working: AutoUpgrade renames the metadata on atomicrmw
instructions when parsing textual IR and when materializing bitcode. The
upgrade is deliberately scoped to atomicrmw rather than being applied to
every attachment of that name, since that is the only place the metadata
was ever meaningful. Because bitcode can be materialized one function at

    [6 lines not shown]
DeltaFile
+84-84llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
+78-78llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
+44-44llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
+43-43llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+41-41llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
+34-34llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-agent.ll
+324-32467 files not shown
+868-64873 files

LLVM/project a375339clang/lib/Sema Sema.cpp, clang/test/CodeGenCXX module-initializer-elision.cpp

[C++20] [Modules] Do not generate call to module initialization for const init (#218346)

Close https://github.com/llvm/llvm-project/issues/218305
DeltaFile
+94-0clang/test/CodeGenCXX/module-initializer-elision.cpp
+12-2clang/lib/Sema/Sema.cpp
+106-22 files

LLVM/project fc93689llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h LoopVectorizationPlanner.cpp

[LV] Move isCandidateForEpilogueVec to LoopVectorizationPlanner.cpp (NFC). (#195268)

isCandidateForEpilogueVectorization (together with its file-static
helper hasUnsupportedHeaderPhiRecipe) does not depend on anything in
LoopVectorize.cpp, move it to LoopVectorizationPlanner.cpp.

PR: https://github.com/llvm/llvm-project/pull/195268
DeltaFile
+3-71llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+59-0llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+4-0llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+66-713 files

FreeBSD/ports 8b92f9cwww/mod_gnutls distinfo Makefile

www/mod_gnutls: Update to 0.13.0

Fixes CVE-2026-33307 and CVE-2026-33308.  Upstream switched to Meson and
moved off the now dead mod.gnutls.org, so the port follows.  0.13.0 also
drops SRP and Monkeysphere support and enforces the client certificate
Key Purpose, see GnuTLSClientKeyPurpose.

Changelog:      https://github.com/airtower-luna/mod_gnutls/releases/tag/mod_gnutls/0.13.0
Security:       a7b4cdfc-9f9d-11f1-a655-3497f65b111b
Sponsored by:   Netzkommune GmbH

(cherry picked from commit f6c827424a26e9f5e403e72790b14a120c3cedbd)
DeltaFile
+11-14www/mod_gnutls/Makefile
+3-3www/mod_gnutls/distinfo
+14-172 files

FreeBSD/ports f6c8274www/mod_gnutls distinfo Makefile

www/mod_gnutls: Update to 0.13.0

Fixes CVE-2026-33307 and CVE-2026-33308.  Upstream switched to Meson and
moved off the now dead mod.gnutls.org, so the port follows.  0.13.0 also
drops SRP and Monkeysphere support and enforces the client certificate
Key Purpose, see GnuTLSClientKeyPurpose.

Changelog:      https://github.com/airtower-luna/mod_gnutls/releases/tag/mod_gnutls/0.13.0
Security:       a7b4cdfc-9f9d-11f1-a655-3497f65b111b
Sponsored by:   Netzkommune GmbH
DeltaFile
+11-14www/mod_gnutls/Makefile
+3-3www/mod_gnutls/distinfo
+14-172 files

FreeBSD/ports 830607dsecurity/vuxml/vuln 2026.xml

security/vuxml: Document mod_gnutls -- multiple vulnerabilities

CVE-2026-33307 is an out-of-bounds write when mod_gnutls receives a client
certificate chain longer than its buffer, CVE-2026-33308 a missing Key
Purpose check during client certificate verification.  Upstream fixed both
on 2026-03-20; in the tree the fix arrives with www/mod_gnutls 0.13.0.

Sponsored by:   Netzkommune GmbH
DeltaFile
+31-0security/vuxml/vuln/2026.xml
+31-01 files

OPNSense/core b2ca3ccsrc/opnsense/scripts/captiveportal/lib arp.py, src/opnsense/scripts/interfaces list_hosts.py

Emit hosts DESC, use first match in kea_prefix_watcher, cleanup arp.py redundant sorting
DeltaFile
+1-10src/opnsense/scripts/captiveportal/lib/arp.py
+3-2src/opnsense/scripts/kea/kea_prefix_watcher.py
+1-1src/opnsense/scripts/interfaces/list_hosts.py
+5-133 files

LLVM/project a3ac001llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/AArch64 vector-call-linear-args-no-wide-iv.ll

[VPlan] Split legalizeAndOptimizeIVs in 2 phases. (#217765)

Split the transform into 2 phases:

1. narrow all users of all IVs
2. replace wide IVs if all users are scalar.

Together with removing the old, wide recipes, this allows us to catch
slightly more cases.

PR: https://github.com/llvm/llvm-project/pull/217765
DeltaFile
+16-11llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+8-14llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args-no-wide-iv.ll
+5-8llvm/test/Transforms/LoopVectorize/VPlan/vplan-narrow-iv-users.ll
+29-333 files

FreeNAS/freenas 60c06cdsrc/middlewared/middlewared/api/v25_10_5 reporting.py

NAS-142197 / 25.10.7 / Allow null aggregations in the reporting.get_data result schema (#19535)
DeltaFile
+2-2src/middlewared/middlewared/api/v25_10_5/reporting.py
+2-21 files

LLVM/project dfa7876llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/test/Transforms/LoopVectorize/RISCV partial-reduce-dot-product-costs.ll

[RISCV] Cost i64 accumulator for Zvdot4a8i partial reductions

Now that `lowerPARTIAL_REDUCE_MLA` can lower an i64 accumulator with
i8 inputs using the dot-product instructions, teach the cost model
to price it so the vectorizer will form it.

- `getPartialReductionCost` accepts an i64 accumulator (reduction
  factor 8) and prices the `vdot4a*` plus the reduce-and-accumulate
  for both lowering shapes:
  - reduce the i32 partial sums with a `vadd.vv` and widen into the
    accumulator with a `vwadd.wv` (fixed-length vectors additionally
    extract the high i32 subvector with a `vslidedown`), and
  - for a single-vector scalable accumulator, whose i32 subvectors are
    a fractional LMUL, widen to i64 first and reduce/accumulate with
    two i64 `vadd.vv`.

The i64 case requires a wide enough VF (LMUL) to reach the scale-8 factor,
matching how AArch64 only forms it under SVE.


    [6 lines not shown]
DeltaFile
+212-0llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product-costs.ll
+69-5llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+281-52 files

FreeBSD/src e7aa5a5sys/dev/e1000 if_em.c e1000_osdep.h

e1000: Serialize 82579 CSR writes with the Management Engine

The 82579 PCIm2PCI arbiter can acknowledge a host MAC CSR write while
the Management Engine is accessing another CSR.  The host write can be
lost; subsequent target accesses may no longer be claimed by the MAC and
can hang the system.

For 82579 controllers with valid management firmware, wait for the ME
CSR access indication before every MAC CSR write.  Keep the wait bounded
and use DELAY because writes occur in interrupt and datapath contexts.
Verify every transmit and receive tail write.  If a tail does not hold
the requested value, disable its datapath direction and request a full
iflib reset.

Keep the ordinary register-write path as a direct MMIO write behind a
predicted per-device gate.  Contain the wait and tail recovery in the
82579 slow path rather than adding tail-specific accessors and state to
the rest of the e1000 family.


    [11 lines not shown]
DeltaFile
+60-0sys/dev/e1000/e1000_osdep.c
+13-7sys/dev/e1000/e1000_osdep.h
+9-0sys/dev/e1000/if_em.c
+82-73 files

LLVM/project 0b98a7clldb/test/API/functionalities/breakpoint/write_over_software_breakpoint TestWriteOverSoftwareBreakpoint.py

[lldb][test] Enable TestWriteOverSoftwareBreakpoint for debugserver (#218362)

Both the mentioned issues have been fixed.
DeltaFile
+0-4lldb/test/API/functionalities/breakpoint/write_over_software_breakpoint/TestWriteOverSoftwareBreakpoint.py
+0-41 files

LLVM/project cfae73dllvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU mai-hazards-gfx942.mir

[AMDGPU] Add wait states between different MFMAs sharing an accumulator
DeltaFile
+30-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
+18-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+48-02 files

LLVM/project c69228cllvm/docs LangRef.md

Remove duplicate "from"
DeltaFile
+2-2llvm/docs/LangRef.md
+2-21 files

LLVM/project f80f27elldb/test/API/tools/lldb-dap/databreakpoint TestDAP_setDataBreakpoints.py

[lldb][test] Disable lldb-dap watchpoint test on Arm Linux (#218360)

Added by #215228. The test assertions are fine, but when the program
continues at the end, it faults.

More details in https://github.com/llvm/llvm-project/issues/217961.
DeltaFile
+3-0lldb/test/API/tools/lldb-dap/databreakpoint/TestDAP_setDataBreakpoints.py
+3-01 files

OPNSense/core cd40213src/opnsense/mvc/app/views/OPNsense/Wireguard general.volt

Add a new row below the last row that contains these buttons so striping works
DeltaFile
+7-2src/opnsense/mvc/app/views/OPNsense/Wireguard/general.volt
+7-21 files

FreeBSD/ports 683f2bcmultimedia/minisatip Makefile distinfo

multimedia/minisatip: Update to 2.0.97
DeltaFile
+3-3multimedia/minisatip/distinfo
+1-1multimedia/minisatip/Makefile
+4-42 files

LLVM/project 568110fmlir/lib/Dialect/Linalg/Transforms EraseUnusedOperandsAndResults.cpp, mlir/test/Dialect/Linalg erase-unused-operands-and-results.mlir

[MLIR][Linalg] Fix segfault when an out operand is yielded by a nested op (#216977)

This closes
[203752](https://github.com/llvm/llvm-project/issues/203752), a smaller
reproducer is:
```mlir
#map = affine_map<(d0, d1) -> (d0, d1)>
#map1 = affine_map<(d0, d1) -> (d0)>
#map2 = affine_map<(d0) -> (d0)>

func.func @yield_of_nested_op_keeps_output(%arg0: tensor<1x1xi32>, %arg1: tensor<1xi32>,
                                           %arg2: memref<1xi1>) {
  %c42 = arith.constant 42 : i32
  %c0 = arith.constant 0 : index
  %false = arith.constant false
  %0 = linalg.generic {indexing_maps = [#map, #map1],
                       iterator_types = ["parallel", "reduction"]}
      ins(%arg0 : tensor<1x1xi32>) outs(%arg1 : tensor<1xi32>) {
  ^bb0(%in: i32, %out: i32):

    [20 lines not shown]
DeltaFile
+42-0mlir/test/Dialect/Linalg/erase-unused-operands-and-results.mlir
+4-2mlir/lib/Dialect/Linalg/Transforms/EraseUnusedOperandsAndResults.cpp
+46-22 files

LLVM/project 698f043clang/include/clang/Sema SemaAMDGPU.h, clang/lib/Sema SemaAMDGPU.cpp

[Clang][AMDGPU] Name the builtin in required target feature diagnostics
DeltaFile
+48-48clang/test/SemaOpenCL/builtins-image-load-image-feature-err.cl
+48-48clang/test/Sema/builtins-amdgcn-d16-image-16bit-error.c
+45-45clang/test/SemaOpenCL/builtins-extended-image-err.cl
+28-28clang/test/SemaOpenCL/builtins-image-store-image-feature-err.cl
+23-16clang/lib/Sema/SemaAMDGPU.cpp
+5-0clang/include/clang/Sema/SemaAMDGPU.h
+197-1856 files

LLVM/project 95f1eefllvm/lib/Target/AMDGPU GCNHazardRecognizer.h GCNHazardRecognizer.cpp

[AMDGPU][NFC] Move MFMA overlapped src2/C wait states into a helper
DeltaFile
+63-66llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+5-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+68-662 files

LLVM/project 83d8cf3llvm/lib/Target/AMDGPU AMDGPUUniformIntrinsicCombine.cpp, llvm/test/CodeGen/AMDGPU redundant-ballot-reads.ll

[AMDGPU] Combine redundant ballot intrinsic calls

Suppose there is a loop where there is a call to @llvm.amdgcn.ballot,
which maps to an instruction involving the exec mask as an operand. This
instruction duplicates if the loop is unrolled. With a higher number of
unrolled iterations, the code bloats with such redundant instructions
with $exec as there is no middle-end/backend pass which could combine
such instructions in a uniform CFG.

This patch introduces a transform in AMDGPUUniformIntrinsicCombine to
combine redundant calls to @llvm.amdgcn.ballot, to mitigate this issue.

The approach is to walk over the dominator tree and collect all calls to
@llvm.amdgcn.ballot. Map the result type and condition to the calls, to
avoid combining calls of different kinds. Calls A and B can be combined
into A iff:
- A and B are identical
- A dominates B
- all paths from A to B are uniform and exec-invariant.

    [2 lines not shown]
DeltaFile
+454-0llvm/test/CodeGen/AMDGPU/redundant-ballot-reads.ll
+165-5llvm/lib/Target/AMDGPU/AMDGPUUniformIntrinsicCombine.cpp
+619-52 files

LLVM/project 2f51e5bllvm/include/llvm/Transforms/Utils FunctionComparator.h, llvm/lib/Transforms/Utils FunctionComparator.cpp

[MergeFunc] Preserve observable function pointer identity (#213604)

Fixes #213206.

MergeFunc can replace one function with a forwarding thunk to another.
FunctionComparator treated self-references as equal in every context, so
functions that observe their own address (e.g. icmp %p, @g) could be
merged incorrectly.
Compare ordinary function-pointer uses as normal global values. Treat
self-references as equal only for corresponding call targets and
blockaddress.

AI assistance was used while preparing this change.
DeltaFile
+67-0llvm/test/Transforms/MergeFunc/self-reference.ll
+21-12llvm/lib/Transforms/Utils/FunctionComparator.cpp
+29-0llvm/test/Transforms/MergeFunc/recursive-self-reference.ll
+5-3llvm/include/llvm/Transforms/Utils/FunctionComparator.h
+122-154 files

FreeBSD/src 750cc05contrib/libarchive/libarchive/test test_read_format_zip_winzip_aes256_large_bzip2.zip.uu test_read_format_zip_winzip_aes256_large_lzma.zip.uu

libarchive: merge from vendor branch

libarchive 3.8.9

ChangeLog:
https://github.com/libarchive/libarchive/compare/v3.8.7...v3.8.9

Obtained from:  libarchive
Vendor commit:  27cbc7827172698143e440801fc0ba39ccb4f1f5
MFC after:      2 weeks

(cherry picked from commit 185becb1e1bd2657c156f78aeb52edac05ba5fb5)
DeltaFile
+23,307-0contrib/libarchive/libarchive/test/test_read_format_rar_newsub_rr_over_1m.rar.uu
+2,919-0contrib/libarchive/libarchive/test/test_read_format_cpio_symlink_trailer.cpio.uu
+2,053-0contrib/libarchive/libarchive/test/test_read_format_zip_winzip_aes256_large_zstd.zip.uu
+1,898-0contrib/libarchive/libarchive/test/test_read_format_zip_winzip_aes256_large_xz.zip.uu
+1,893-0contrib/libarchive/libarchive/test/test_read_format_zip_winzip_aes256_large_lzma.zip.uu
+1,616-0contrib/libarchive/libarchive/test/test_read_format_zip_winzip_aes256_large_bzip2.zip.uu
+33,686-0438 files not shown
+58,681-9,875444 files

LLVM/project 9cda466lldb/include/lldb/Breakpoint StopPointSiteList.h, lldb/test/API/functionalities/breakpoint/write_over_software_breakpoint TestWriteOverSoftwareBreakpoint.py

[lldb] Handle 0 size sites in StopPointSiteList::FindInRange (#217919)

Fixes #205120

In which due to delayed breakpoints, a breakpoint that would become an
external breakpoint later (meaning managed by the debug server) was
temporarily stored as a software breakpoint (which is managed by lldb)
with a zero size breakpoint site. That zero site site tripped an
assertion when you tried to write over the site.

To fix this, I've explicitly ignored zero size sites in FindInRange by
defining them as never overlapping. FindInRange is only used for
patching reads and writes, so I think this is safe to do. I have
documented this in the docstring.

I considered adding a breakpoint type "uncommitted", but software
breakpoints are actually handled in the most conservative manner (reads
and writes are always patched). So I think as a default it's fine (also
I don't want to go and audit all the places that use that enum and end

    [4 lines not shown]
DeltaFile
+88-0lldb/test/API/functionalities/breakpoint/write_over_software_breakpoint/TestWriteOverSoftwareBreakpoint.py
+9-2lldb/include/lldb/Breakpoint/StopPointSiteList.h
+97-22 files

FreeBSD/ports 4d0666cfilesystems/openzfs Makefile distinfo

filesystems/openzfs: update to 2.4.4

Changelog:      https://github.com/openzfs/zfs/releases/tag/zfs-2.4.4
DeltaFile
+22-0filesystems/openzfs/pkg-plist
+3-3filesystems/openzfs/distinfo
+1-1filesystems/openzfs/Makefile
+26-43 files

FreeBSD/ports c6cff33filesystems/openzfs-kmod Makefile distinfo

filesystems/openzfs-kmod: update to 2.4.4

Changelog:      https://github.com/openzfs/zfs/releases/tag/zfs-2.4.4
DeltaFile
+3-3filesystems/openzfs-kmod/distinfo
+1-1filesystems/openzfs-kmod/Makefile
+4-42 files

FreeBSD/ports 30529denews/tin pkg-plist distinfo, news/tin/files patch-configure

news/tin: Update to 2.6.6
DeltaFile
+9-15news/tin/files/patch-configure
+7-3news/tin/Makefile
+3-3news/tin/distinfo
+1-0news/tin/pkg-plist
+20-214 files