FreeBSD/ports 1c4d940finance/R-cran-timeDate distinfo Makefile

finance/R-cran-timeDate: Update to 4052.112
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+3-3finance/R-cran-timeDate/distinfo
+1-1finance/R-cran-timeDate/Makefile
+4-42 files

FreeBSD/ports eacae62databases/R-cran-dtplyr distinfo Makefile

databases/R-cran-dtplyr: Update to 1.3.3

PR:             293115
Reported by:    Einar Bjarni Halldórsson <einar at isnic.is>(maintainer)
DeltaFile
+3-3databases/R-cran-dtplyr/distinfo
+1-1databases/R-cran-dtplyr/Makefile
+4-42 files

FreeBSD/ports 3b10481finance/R-cran-AER distinfo Makefile

finance/R-cran-AER: Update to 1.2.16
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+3-3finance/R-cran-AER/distinfo
+1-1finance/R-cran-AER/Makefile
+4-42 files

OPNSense/core 4081092src/etc/inc interfaces.inc, src/opnsense/scripts/interfaces rtsold_script.sh

interfaces: multi-dhcp6c support and custom PD association #7647

This splits off rtsold and dhcp6c into separate processes
which frees us from the restrictions of faked iterative IDs
for PD associations.  For NA we simply default to 0 now.

I'm not entirely sure why we settled for a single deamon of
dhcp6c back in the day, but there are certianly downsides to
it and I don't see something that wasn't fixed in the meantime
that makes this not work.
DeltaFile
+22-58src/etc/inc/interfaces.inc
+58-4src/www/interfaces.php
+6-6src/opnsense/scripts/interfaces/rtsold_script.sh
+86-683 files

OPNSense/core c6db10fsrc/etc/pkg/repos OPNsense-aux.conf.shadow.in, src/opnsense/mvc/app/models/OPNsense/Core Firmware.xml

firmware: disable aux by default but enable when checked; closes #9275
DeltaFile
+26-16src/opnsense/mvc/app/views/OPNsense/Core/firmware.volt
+9-1src/opnsense/scripts/firmware/repos/OPNsense.php
+1-1src/etc/pkg/repos/OPNsense-aux.conf.shadow.in
+1-0src/opnsense/mvc/app/models/OPNsense/Core/Firmware.xml
+37-184 files

OPNSense/core c145e5csrc/opnsense/scripts/kea kea_prefix_watcher.py

kea: Add scope ID to prefix watcher link local address to fix route add (#9778)

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+2-1src/opnsense/scripts/kea/kea_prefix_watcher.py
+2-11 files

FreeNAS/freenas d601458tests/api2 test_staticroutes.py

NAS-139748 / 26.0.0-BETA.1 / ValidationErrors -> ValidationError in static route test (#18191)

Minor change to this test, static route plugin raises ValidationError
now and not ValidationErrors.
DeltaFile
+42-26tests/api2/test_staticroutes.py
+42-261 files

LLVM/project de05a01llvm/lib/Target/AMDGPU AMDGPUAttributor.cpp

[NFC][AMDGPU] Remove unused `getLDSSize`
DeltaFile
+0-8llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+0-81 files

LLVM/project 47331aemlir/lib/Dialect/Bufferization/IR BufferDeallocationOpInterface.cpp, mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation misc-other.mlir

Fix ownership based deallocation pass crash (#179357)

The `OwnershipBasedBufferDeallocation` pass crashes when the IR contains
memrefs that are live in the same Block but are defined in different
Blocks. During this pass, live memrefs in a given block are sorted
according to the comparison function `ValueComparator`. This causes an
assertion to be triggered when sorting memref values using
`ValueComparator` as the comparison function. The assertion triggered is
found in `Operation::isBeforeInBlock`, which requires `this` and `other`
to reside in the same block. (See the definition
[here](https://github.com/llvm/llvm-project/blob/main/mlir/lib/IR/Operation.cpp#L385-L386).)

The fix is to handle values from different blocks in the
`ValueComparator` by sorting based on Block number if the compared ops
aren't in the same block. While `computeBlockNumber` is intended for
debugging and error messages, it is a convenient utility that can
provide a sufficient weak ordering for `llvm::sort` while handling
operations from different parent blocks. I'm not aware of another
ordering relation for Blocks that would be appropriate as well as cheap

    [8 lines not shown]
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+49-5mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir
+14-3mlir/lib/Dialect/Bufferization/IR/BufferDeallocationOpInterface.cpp
+63-82 files

OPNSense/core 827376dsrc/etc/pkg/repos OPNsense-aux.conf.shadow.in, src/opnsense/mvc/app/models/OPNsense/Core Firmware.xml

firmware: disable aux by default but enable when set #9275
DeltaFile
+26-16src/opnsense/mvc/app/views/OPNsense/Core/firmware.volt
+9-1src/opnsense/scripts/firmware/repos/OPNsense.php
+1-1src/etc/pkg/repos/OPNsense-aux.conf.shadow.in
+1-0src/opnsense/mvc/app/models/OPNsense/Core/Firmware.xml
+37-184 files

LLVM/project c308be0llvm/lib/Target/AMDGPU AMDGPUAttributor.cpp AMDGPUSubtarget.h

[NFC][AMDGPU] Remove unused/unimplemented getWavesPerEU variants
DeltaFile
+0-10llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+0-7llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+0-172 files

LLVM/project 760f707mlir/include/mlir/Dialect/XeGPU/Transforms XeGPULayoutImpl.h, mlir/lib/Dialect/XeGPU/Transforms XeGPULayoutImpl.cpp XeGPUPropagateLayout.cpp

[MLIR][XeGPU] Use the `setupDpasLayout` utility for dpas layout propagation (#180937)

DeltaFile
+219-1mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+30-186mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+91-1mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
+8-0mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h
+348-1884 files

LLVM/project 02fcdc3llvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/CodeGen MachineUniformityAnalysis.cpp

review: address suggestion
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+8-1llvm/include/llvm/CodeGen/TargetInstrInfo.h
+2-5llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+5-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+4-2llvm/lib/Target/AMDGPU/SIInstrInfo.h
+19-94 files

OpenBSD/ports cHTRy7Ygraphics/py-Pillow Makefile, graphics/py-Pillow/patches patch-src_decode_c patch-src_encode_c

   pillow: backport fix for OOB write when loading crafted PSD images
   https://github.com/python-pillow/Pillow/security/advisories/GHSA-cfh3-3jmp-rvhc
VersionDeltaFile
1.1.2.1+18-0graphics/py-Pillow/patches/patch-src_decode_c
1.1.2.1+18-0graphics/py-Pillow/patches/patch-src_encode_c
1.74.2.1+1-0graphics/py-Pillow/Makefile
1.1+0-0graphics/py-Pillow/patches/patch-src_decode_c
1.1+0-0graphics/py-Pillow/patches/patch-src_encode_c
+37-05 files

LLVM/project 82447b9clang/lib/CIR/Dialect/Transforms TargetLowering.cpp, clang/test/CIR/CodeGen atomic-scoped.c

[CIR] Add cir.atomic.xchg to target lowering (#180744)

This patch adds the `cir.atomic.xchg` operation to the TargetLowering
pass. The synchronization scope attached to the operation will be
canonicalized there.
DeltaFile
+8-2clang/test/CIR/CodeGen/atomic-scoped.c
+1-1clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
+9-32 files

FreeNAS/freenas 3401004tests/api2 test_staticroutes.py

ValidationErrors -> ValidationError in static route test
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+42-26tests/api2/test_staticroutes.py
+42-261 files

LLVM/project 838be78llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 clmul-fixed.ll

[AArch64][ISel] Lower fixed-width i64 vector CLMUL intrinsics (#178876)

NEON's PMULL/PMULL2 can be used and its lower bits taken to lower CLMUL
intrinsics, so long as +aes is present.
DeltaFile
+648-629llvm/test/CodeGen/AArch64/clmul-fixed.ll
+13-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+3-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+664-6313 files

NetBSD/pkgsrc cTYfzpvdoc CHANGES-2026

   doc: Updated security/gpa to 0.11.1
VersionDeltaFile
1.1080+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc d3CZzpisecurity/gpa distinfo Makefile, security/gpa/patches patch-src_gpacontext.c patch-src_gpacontext.h

   gpa: update to 0.11.1.

   Noteworthy changes in version 0.11.1 (2026-02-12)
   -------------------------------------------------

    * Remove unused trust_item stuff to make it build with gpgme 2.x.
      [rGPAb6ba8bcc6d]

    * Fix a crash due to bad marshaling.  See
      https://bugs.gentoo.org/957196.  [rGPA45fc64a4ac]
VersionDeltaFile
1.15+4-6security/gpa/distinfo
1.81+2-2security/gpa/Makefile
1.2+1-1security/gpa/patches/patch-src_gpacontext.c
1.2+1-1security/gpa/patches/patch-src_gpacontext.h
+8-104 files

LLVM/project abc48e0bolt/include/bolt/Core MCPlusBuilder.h, bolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp

[BOLT][BTI] Patch ignored functions in place when targeting them with
indirect branches

When applying BTI fixups to indirect branch targets, ignored functions are
considered a special case:
- these hold no instructions,
- have no CFG,
- and are not emitted in the new text section.

The solution is to patch the entry points in the original location.

If such a situation occurs in a binary, recompilation using the
-fpatchable-function-entry flag is required. This will place a nop at all
function starts, which BOLT can use to patch the original section.

Without the extra nop, BOLT cannot safely patch the original .text section.

An alternative solution could be to also ignore the function from which
the stub starts. This has not been tried as LongJmp pass - where most

    [3 lines not shown]
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+45-16bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+39-0bolt/test/AArch64/long-jmp-bti-ignored-nop.s
+2-4bolt/test/AArch64/bti-long-jmp-ignored.s
+5-0bolt/include/bolt/Core/MCPlusBuilder.h
+91-204 files

LLVM/project 3fd8e21clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded vabd_vv.c vabdu_vv.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded vabd_vv.c vabdu_vv.c

Use RVVOutBuiltinSet for vabd/vabdu to match Intrinsics

Created using spr 1.3.6-beta.1
DeltaFile
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu_vv.c
+13-13clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd_vv.c
+78-783 files not shown
+106-1069 files

LLVM/project 8111a6cllvm/test/CodeGen/AArch64 qmovn.ll qshrn.ll

[AArch64][GlobalISel] Add some extra sqxtn test coverage. NFC
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+282-4llvm/test/CodeGen/AArch64/qmovn.ll
+65-16llvm/test/CodeGen/AArch64/qshrn.ll
+347-202 files

OPNSense/core 1d06cf4src/opnsense/scripts/firmware/repos OPNsense.php

firmware: opnsense-update does aux if found now
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+0-4src/opnsense/scripts/firmware/repos/OPNsense.php
+0-41 files

LLVM/project b8534e0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded vabs_v.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded vabs_v.c

Address comments

Created using spr 1.3.6-beta.1
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+0-202llvm/test/CodeGen/RISCV/rvv/vwabdacc.ll
+0-202llvm/test/CodeGen/RISCV/rvv/vwabdaccu.ll
+179-0llvm/test/CodeGen/RISCV/rvv/vwabda.ll
+179-0llvm/test/CodeGen/RISCV/rvv/vwabdau.ll
+66-67clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs_v.c
+66-67clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs_v.c
+490-53832 files not shown
+1,746-1,89138 files

NetBSD/pkgsrc TlF7WHKdoc CHANGES-2026

   Updated databases/py-mysqlclient, www/py-gunicorn
VersionDeltaFile
1.1079+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc XNKURmcwww/py-gunicorn distinfo Makefile

   py-gunicorn: updated to 25.0.3

   25.0.3 - 2026-02-07

   Bug Fixes

   - Fix RuntimeError when StopIteration is raised inside ASGI response body
     coroutine (PEP 479 compliance)

   - Fix deprecation warning for passing maxsplit as positional argument in
     `re.split()` (Python 3.13+)
VersionDeltaFile
1.21+4-4www/py-gunicorn/distinfo
1.29+2-2www/py-gunicorn/Makefile
+6-62 files

NetBSD/pkgsrc j9wzlp5databases/py-mysqlclient distinfo Makefile

   py-mysqlclient: updated to 2.2.8

   2.2.8

   * Add ``local_infile_dir`` option to restrict LOAD DATA LOCAL INFILE file path.
   * windows wheel: Update mariadb-connector to 3.4.8
   * Add Python 3.14 and drop Python 3.8, 3.9 support.
   * Experimental support for free threaded Python. Importing ``MySQLdb`` doesn't
     enable the GIL anymore. This doesn't mean mysqlclient is thread safe.
     You must not use same connection object from multiple threads concurrently.
VersionDeltaFile
1.11+4-4databases/py-mysqlclient/distinfo
1.15+2-3databases/py-mysqlclient/Makefile
+6-72 files

pkgng/pkgng 8f790d4libpkg pkg_jobs.c

pkg_jobs: try to break potential infinite recursion
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+10-3libpkg/pkg_jobs.c
+10-31 files

LLVM/project 79ec0cemlir/lib/Target/LLVMIR ModuleImport.cpp, mlir/test/Target/LLVMIR/Import constant.ll

[MLIR][LLVMIR] Add support for importing ConstantInt/FP vector splats. (#180946)

Updates LLVM IR importing to remove the assumption that
ConstantInt/ConstantFP are always scalar.
DeltaFile
+14-0mlir/lib/Target/LLVMIR/ModuleImport.cpp
+9-0mlir/test/Target/LLVMIR/Import/constant.ll
+23-02 files

LLVM/project 3c8016cllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 vec-combine-trunc-dup-ext.ll

[AArch64] Eliminate XTN/SSHLL for vector splats (#180913)

Combine:
  sext(duplane(insert_subvector(undef, trunc(X), 0), idx))
Into:
  duplane(X, idx)

This avoids XTN/SSHLL instruction sequences that occur when splatting
elements from boolean vectors after type legalization, which is common
when using shufflevector with comparison results.
DeltaFile
+119-0llvm/test/CodeGen/AArch64/vec-combine-trunc-dup-ext.ll
+65-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+184-02 files