Services: Dnsmasq DNS & DHCP: Since client-id is a valid IPv4 reservation type as well, ensure the lease view handles it correctly (#10003)
Remove some of the heuristics with the adding lease button. We cannot assume what the user want, so just offer both mac and hwaddr for any add lease command. The dnsmasq GUI we built has no constraints regarding this, and the application below renders both if given since there is no logic constraint here either.
(cherry picked from commit 15ba56587119e9998ac65829f62592e3e63d2389)
firewall: fix mvc code vs. legacy rules display issues #9931
These functions only pertain to printing automatic rules in the
old GUI so eventually we can all scrap them.
(cherry picked from commit 095a4d53a89b81c1726d1e342d9bb83e1b93e184)
make: make `vim' target even more lazy
Match the file name without left anchor and look for
a partial directory match if a director was specified.
(cherry picked from commit 286dfcb6a660105ec44955ee8ce8693af7fdb53a)
update to ruff-0.15.7, from maintainer Laurent Cheylus
switch back to a do-build step because overriding MODCARGO_CARGOTOML
doesn't work for modcargo-gen-crates. I tweaked his diff slightly to avoid
setting MODCARGO_CARGOTOML to the default and adjusted a comment.
[AMDGPU] Implement LSR cost model for GFX9+ (#184138)
AMDGPU previously had no target-specific LSR cost model, so the generic
heuristic would often introduce extra induction variables and base-add
chains that hurt VALU throughput on GFX9+ (observed on gfx942).
Implement a custom cost model:
- isLSRCostLess(): prioritize per-iteration instruction count over setup
costs, penalize IV multiplies, and demote register count. Pre-GFX9 falls
back to the default comparator.
- getScalingFactorCost(): report that base+scale*index addressing
requires an extra ADD instruction.
- isNumRegsMajorCostOfLSR(): return false.
- shouldDropLSRSolutionIfLessProfitable(): return true.
Assisted-by: Claude Opus
[BOLT][Perf2bolt] Add support to generate pre-parsed perf data (#171144)
Adding a generator into Perf2bolt is the initial step to support the
large end-to-end tests for Arm SPE. This functionality proves unified format of
pre-parsed profile that Perf2bolt is able to consume.
Why does the test need to have a textual format SPE profile?
* To collect an Arm SPE profile by Linux Perf, it needs to have
an arm developer device which has SPE support.
* To decode SPE data, it also needs to have the proper version of
Linux Perf.
* The minimum required version of Linux Perf is v6.15.
Bypassing these technical difficulties, that easier to prove
a pre-generated textual profile format.
The generator relies on the aggregator work to spawn the required
perf-script jobs based on the the aggregation type, and merges the
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[AMDGPU] Use s_cvt_i32/u32_f32 instructions for saturated uniform conversions (#187711)
We attempt to select `s_cvt_i32/u32_f32` where possible, with some
considerations:
* For `f64` default to `v_` instructions as there is no support for
`f64` in SALU.
* For `f16` to `i16` select `v_cvt_i16/u16_f16` which is consistent with
non-saturating conversions behavior. However we could emit
`s_cvt_f32_f16` followed by `s_cvt_i32/u32_f32` to keep the computation
in SALU, as SALU does not have `s_cvt_i16_f16`. Happy to look into it if
beneficial.
* When it comes to clamping, ISel turns min and max sequence into
`v_med3` with `v0` destination, whereas globalisel keeps min and max as
`s_min` and `s_max` and then moves the result into `v0`, as lit tests
expect the return value to be in `v0` in both cases. This is unrelated
to this change but I thought it is worth highlighting.
build: better PRODUCT_ZFS handling
Only VM images really handle ZFS. While here move the handling
to the core repository so rc.loader knows what to do.
We only need a 10 second boot relay on installer vga/serial/dvd/nano.
Also go back to setting the pool name using PRODUCT_ZFS which is
now safeguarded through ALLOWED/REQUESTED.
