[libc][complex] Add cargf and carg functions to libc complex math (#204087)
This PR adds carg and cargf function to libc complex and also add test
cases to cover some special inputs.
---------
Signed-off-by: jinge90 <ge.jin at intel.com>
hwpstate_intel(4): Fix error tests
How I failed to notice this during the review will remain a mistery.
Fixes: 29b8220b179b ("hwpstate_intel: Use ipi instead of thread_lock + sched_bind")
Event: Halifax Hackathon 202606
Location: jrm@'s bathroom
Sponsored by: The FreeBSD Foundation
[MLIR][XeGPU] Fix order remapping in layout transpose (#205212)
LayoutAttr::transposeDims and LayoutAttr::isTransposeOf mishandled the
`order` field when transposing a layout. The `order` field is
fundamentally different from the size-valued fields (sg_layout, sg_data,
inst_data, lane_layout, lane_data): its values are dimension indices
(order[0] is the fastest-varying dim), not per-position sizes. The two
require different transpose rules:
- Size fields — reindex by position: new[i] = orig[perm[i]]
- order — relabel values through the inverse permutation: newOrder[i] =
inversePerm[origOrder[i]]
Both functions incorrectly applied the size-field rule to `order`.
Because the bug was applied consistently in both places, it stayed
hidden for trivial/symmetric (e.g. 2D [1,0]) permutations, where the two
rules happen to coincide. It only surfaces for non-trivial permutations
such as the 3D [1,0,2] produced by a broadcast→transpose chain.
Assist-by-Claude
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[RISCV] Emit .option arch extensions without the "experimental-" prefix (#205471)
We currently emit the "experimental-" prefix in .option arch, e.g.
`.option arch, +experimental-zicfiss`, but the assembler can't parse
that back.
There are two ways to fix this:
1. Teach the assembler to accept `.option arch, +experimental-zicfiss`.
2. Emit `.option arch, +zicfiss` instead of `.option arch,
+experimental-zicfiss`.
This patch takes the second approach, which better fits the .option arch
syntax we defined. Experimental extensions are still guarded by
`-menable-experimental-extensions`.
nfs_clvnops.c: Fix the case where va_flags are being cleared
Commits c5d72d2 and 3b6d4c6 broke the case where the
archive/hidden/system attributes are being set false
(UF_ARCHIVE, UF_HIDDEN or UF_SYSTEM bits being cleared.)
and the NFS server does not support those attributes.
These patches only checked for support if the
archive/hidden/system attributes were non-zero.
This patch fixes the problem.
PR: 296088
(cherry picked from commit 572680712c317b81d66475203ac1b9d6bbeca5d5)
[DAG] Fix illegal type in srl(bitcast(build_vector)) fold (#205074)
The fold
```
(srl (bitcast (build_vector e1, ..., eN)), (N-1) * eltsize) -> (zext eN)
```
added in #181412 built the result through a narrow element integer type,
which
can be illegal (e.g. i16 on RV32 with the P extension, where `<2 x i16>`
is
legal). When the fold runs in the last DAG combine that illegal type
hits the
"Unexpected illegal type!" assert.
Build the result directly in the result type `VT` and mask off the high
bits
instead:
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[libclc] Delete wrong implementation nvptx clc_isinf (#205699)
The file calls __nv_isinf which return 1 for true on vector input, while
the generic clc_isinf which return -1 for true on vector input. Using
nvptx clc_isinf in OpenCL isinf violates OpenCL spec.
Found the issue in https://github.com/intel/llvm/pull/22413
[x86] Handle implicit sections when determining if a global is large (#204247)
Just like explicit sections.
We were seeing globals with implicit sections marked large under the
medium code model.
Assisted-by: Gemini
hwpstate_intel(4): sysctl_epp_select(): Cache again new EPP value
This caching was removed inadvertently in the commit mentioned below.
Fixes: 8452afeb5682 ("hwpstate_intel: Use 8bit scale instead of percentage scale")
Event: Halifax Hackathon 202606
Location: jrm@'s living room
Sponsored by: The FreeBSD Foundation
hwpstate_intel(4): Fix recent copyright formatting
Add an "empty" (comment) line between copyright and the Foundation text.
Fixes: 29b8220b179b ("hwpstate_intel: Use ipi instead of thread_lock + sched_bind")
Event: Halifax Hackathon 202606
Location: jrm@'s living room
Sponsored by: The FreeBSD Foundation
