[InstCombine] Fold `-X / -Y` to `X / Y` when it cannot overflow (#224025)
Fold:
```
(-X) / (-Y) -> X / Y
```
Do not combine when X may be INT_MIN and Y may be -1, as the result
could introduce signed division overflow.
For AMDGPU example:
https://godbolt.org/z/6jj6E8T5T
[lld][AArch64] Support R_AARCH64_TLSLE_ADD_TPREL_LO12 (#227173)
AArch64 local-exec TLS code sequences compiled with -mtls-size=12 use
the non-NC R_AARCH64_TLSLE_ADD_TPREL_LO12 relocation (emitted for 'add
xN, xN, :tprel_lo12:sym'), but lld only handles the _NC variant, so
linking such objects fails with 'unknown relocation'.
Add the relocation to the TLS LE group in scanSectionImpl (R_TPREL, same
group as the other TLSLE relocations, so it is also rejected for
-shared) and resolve it like the _NC variant, but with an unsigned
12-bit range check as the non-NC form requires the full offset to fit
into the imm12 field.
[Clang][HLSL] Reject matrix layout modifiers on array typedefs (#227364)
Fixes #226251
Require row_major and column_major modifiers to apply directly to a
matrix type rather than accepting an array typedef whose element type is
a matrix.
This preserves valid declarations of arrays of annotated matrix elements
while rejecting attempts to apply a layout modifier to the array type
itself.
[runtimes] Add llvm-dis to compiler-rt test dependency (#227212)
A recent commit 9a0c255ce1ef introduced dependency on llvm-dis to
compiler-rt test instrprof-thinlto-indirect-call-promotion.cpp. This
caused error "llvm-dis: command not found" in CI testing. Fix by adding
llvm-dis to the dependency list for compiler-rt test.
[orc-rt] Flatten C addressing regression tests. NFC. (#227529)
Move the tests out of same-object/ and cross-object/ subdirectories into
addressing/, and mark tests of references to entities in other objects
with a -cross-obj suffix. This keeps the variants of a construct
together, e.g. global-function-call.c next to
global-function-call-cross-obj.test, so gaps in coverage are easier to
spot.
[SystemZ][z/OS] Emit CELQMAIN for a module defining main (#226710)
The Language Environment startup routine `CELQSTRT` finds the main
routine and its environment through `CELQMAIN`. clang does not emit it;
the driver links with `-u CELQMAIN`, which pulls the copy from
`SCEEBND2`. That copy is in NORENT format and refers to the symbol
`MAIN`, so a program built with clang does not start (U4093 reason 218,
or a protection exception because no WSA is allocated and the ADA offset
is used as an absolute address).
For a module that defines `main`, emit `CELQMAIN` in RENT format as
described in "z/OS Language Environment Vendor Interfaces", chapter
"Program initialization and termination for AMODE 64 applications", plus
a reference to the bootstrap routine `CELQBST`, which `CELQSTRT` only
references weakly. `CELQMAIN` gets OS linkage, because `CELQSTRT`,
`CELQINPL` and `CELQBST` reference it with OS linkage (otherwise the
binder reports IEW2469E).
With this change `int main(void) { return 42; }` bound with `ld -e
[12 lines not shown]
[libc++] Bump machines to latest test suite (#227528)
We recently merged some fixes for the test suite which should make the
comparisons more meaningful. Since we haven't re-generated anything
since the recent LNT machine bumps, re-bumping now should not cause any
churn.
[AMDGPU] Fix inline constant for scalar_to_vector of bf16 math ops (#227479)
On targets with BF16InlineConstFromUpperFP32, an inline constant on a
packed bf16 instruction is expanded to FP32, so only a splat is
encodable and both lanes must use op_sel to read the upper half. Scalar
bf16 math lowers to V_PK_* with a dead high lane, so the constant
arrived as (scalar_to_vector bf16:c), which is not a splat yet still
looked inlinable and got folded without op_sel, reading the wrong half.
Combine (scalar_to_vector bf16:c) into a splat BUILD_VECTOR when c is an
inlinable bf16 constant on such subtargets, and in SIFoldOperands
disable the V2BF16 folding paths that would inline a literal without
op_sel. Also allow op_sel_lo on src1 in isOMod() for V_PK_MUL_BF16 so
omod folding still applies.
Fixes: LCOMPILER-2879 and ROCM-30938
[lldb] Find Python relative to LLDB.framework on Darwin (again) (#227521)
The PythonRuntimeLoaderDarwin is responsible for finding the Python
library at runtime. Previously, this was using `DEVELOPER_DIR` and
`xcrun` to avoid having to hard-code the same list of relative paths
that we have as RPATHs for the non-dynamic interpreter build.
However, that leads to some tricky behavior when launching `lldb` with
our without `xcrun`. Combined with some odd path combinations, I changed
my mind and went back to mimicking the RPATH approach.
While I was at it, I also dropped the fallback for looking for Python in
/Applications/Xcode.app. That was always a hack, and now that we support
falling back to a Homebrew or Pyhthon.org installed Python.framework, I
think we should just rely on that.
rdar://188746227
[libc++][docs] Convert documentation from reST to Markdown (batch 2) (#222064)
This is the second batch of changes to migrate libc++ documentation from
rst to markdown.
I use a local pixel diff tool to compare the rendered HTML, and all
diffs seem like fixes. They tend to fall into the following categories:
- dashed bullet lists were previously not rendered, but now they are
- extra indentation interpreted as blockquotes has been removed
- single backticks are now codefont spans, not italic spans
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is a stacked PR based on #222062, which will be a standalone commit
that
renames *.rst -> *.md before this PR lands for history preservation
purposes.
[libc++][docs] Rename documentation files to Markdown (batch 2) (#222062)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
[orc-rt] Add C addressing regression tests for functions. (#227518)
Add tests that check that JIT'd C code can call functions, both in the
same object and in other objects: direct calls, calls through function
pointers stored in initialized data, and tail calls. The tail call tests
only run at -O2, since an unoptimized build may not emit tail calls.
[SlotIndexes] Add queries for stale indexes
An erased instruction leaves its index list entry in place, making the
index indistinguishable from a block boundary entry. Add
isBlockBoundaryIndex() and isStaleIndex() to tell the two apart, and
canonicalizeIndex() to resolve a stale index to the closest preceding
instruction's register slot, or the block start if none survives.
NFC. No caller yet. LiveDebugVariables is next.
[LiveDebugVariables] Repair stale SlotIndexes
The analysis keeps its indexes from before the first register allocator
until DBG_VALUEs are emitted, by which point passes in between have
erased some of the instructions they point at. Resolve them at the
start of each allocator run and before emitting.
SlotIndexes can then reclaim the entries of erased instructions without
sparing the ones held here, which would have made generated code depend
on -g. Emitted locations are unchanged, except that intervals resolving
to one position now emit a single DBG_VALUE rather than identical
consecutive ones.
[TableGen] Support HwMode registers in CompressInstEmitter (#203599)
Previously, CompressInstEmitter only handled plain Register and
RegisterClass records when matching and validating operands in
CompressPat definitions. Attempting to use a RegisterByHwMode (such as a
mode-dependent stack pointer) or a RegClassByHwMode with mode-dependent
registers failed because CompressInstEmitter could not resolve the
underlying register or register class for a given subtarget
configuration.
Introduce HwModePredicates in CodeGenHwModes to resolve HwModeSelect
records using the subtarget features required by a CompressPat (with
predicates implying the absence of all non-default modes resolving to
DefaultMode). This allows using a single instruction definition for
compressed instructions like RISC-V C_ADDI4SPN/C_ADDI16SP across HwModes
instead of duplicating the instruction definitions for each mode.
This commit was created with the help of AI tools
