[Analysis] Cache generation of SCEV expander overflow checks (#213013)
When creating SCEV checks as part of loop vectorisation we often
generate overflow checks, which leads to lots of duplicated calls to the
umul_with_overflow intrinsic. These calls should be cleaned up during
codegen. However, it is unfortunate that the current LLVM method of
calculating the cost of IR in a block involves looping over each
instruction and adding the costs individually with no thought to the
trivial CSE or DCE optimisations that would take place. In the absence
of a more sophisticated method of cost analysis, for now I've chosen to
explicitly CSE these overflow checks during SCEV expansion.
[LoopPeel] Peel last iteration to enable load widening
In loops that contain multiple consecutive small loads (e.g., 3 bytes
loading i8's), peeling the last iteration makes it safe to read beyond
the accessed region, enabling the use of a wider load (e.g., b32) for
all other N-1 iterations.
Patterns such as:
```
%a = load i8, ptr %p
%b = load i8, ptr %p+1
%c = load i8, ptr %p+2
...
%p.next = getelementptr i8, ptr %p, 3
```
Can be transformed to:
```
%wide = load b32, ptr %p ; Read 4 bytes
[19 lines not shown]
AMDGPU/GlobalISel: Fix G_PTR_ADD handling in getBaseWithConstantOffset (#213968)
There was a discrepancy compared to SDAG when G_PTR_ADD was being matched
and there was no nuw flag check. In case of G_PTR_ADD, nuw flag comes
from inbounds flag on getelementptr. For reference, SDAG does not have
pointers so PTR_ADD is integer ADD in SDAG.
themes: opnsense-auto - add tokenize2.css in standard theme to ensure selection in automatic theme. closes https://github.com/opnsense/core/issues/10545
If a themed file is not available in the standard theme, the dark one won't be able to replace it.
[Clang][Sema] Fix an assertion crash when instantiating a nested requirement (#213660)
We should check if the expression is valid before getConstraintExpr.
Fixes #213575
[CIR][AArch64] Lower AArch64 scalar saturating subtract intrinsics (#213658)
### summary
This PR is a follow-up to #207189 and adds CIR lowering support for the
eight AArch64 scalar signed and unsigned saturating subtract intrinsics.
It reuses the common Neon SISD lowering infrastructure introduced by
#209389.
The legacy CodeGen tests are migrated to the ACLE-organized subtraction
test file with corresponding CIR and LLVM checks.
Assisted by : gpt5.6-sol high
net/coturn: Update to 4.17.0
Upstream NEWS content, less bugfixes and minor improvements:
Release 4.17.0
Changelist:
- Enable stateless nonce by default (#2036) (Pavel Punsky <eakraly at users.noreply.github.com>)
- Log format: ISO-8601 timestamp by default, no thread id, space delimiter (#2031) (Pavel Punsky <eakraly at users.noreply.github.com>)
- Start the DTLS listeners only when --dtls is given (#2026) (Pavel Punsky <eakraly at users.noreply.github.com>)
[analyzer] Generalize MemRegion::getDescriptiveName (#213991)
Previously `ArrayBoundChecker` had a utility function called
`getRegionName` that acted as a wrapper around
`MemRegion::getDescriptiveName` and provided fallback descriptions like
"the heap area" or "the string literal" in cases when there was no exact
name and `Memregion::getDescriptiveName` just returned an empty string.
As this functionality may be useful for other checkers in the future,
this commit moves it to `getDescriptiveName`, which now gains a second
optional parameter called `AllowFallback` (which defaults to false).
Calling `getDescriptiveName` with `AllowFallback == true` is almost
equivalent to the utility function `getRegionName`: the only difference
is that `getDescriptiveName` uses `getRawMemorySpace()` to remain
independent of the current `State` -- while `getRegionName` took the
`Space` (calculated with `Reg->getMemorySpace(State)`) as an argument.
This introduces a very minor functional change in
[10 lines not shown]
[lldb] Rename some register type classes (#213684)
Follow up to #196960.
So that when more types are added, the hierarchy is clear.
RegisterType
-> RegisterTypeEnum
-> RegisterTypeFlags
(in future also...)
-> RegisterTypeUnion
-> RegisterTypeVector
Renamed and moved the test file as it will cover all the classes derived
from RegisterType.
