[compiler-rt][ARM] Optimized single precision FP add/sub (#179929)
This adds new implementations of single-precision add/sub in both Thumb1
and Arm/Thumb2 assembler.
Both of the new implementations are included in the builtins library if
the `COMPILER_RT_ARM_OPTIMIZED_FP` cmake option is enabled (as it is by
default).
There was already a Thumb1 assembler implementation of single-precision
add/sub, slower but also smaller. I've kept it (although it's been moved
into the `thumb1` subdirectory), and if you _don't_ enable
`COMPILER_RT_ARM_OPTIMIZED_FP`, it will be selected in place of the new
version.
py-hpack: updated to 4.2.0
4.2.0 (2026-06-22)
**API Changes (Backward Incompatible)**
- Support for Python 3.9 has been removed.
- Support for PyPy 3.9 has been removed.
**API Changes (Backward Compatible)**
- Support for Python 3.14 has been added.
**Bugfixes**
- Headers marked as `sensitive` will no longer log their value at DEBUG level. Instead a placeholder value of `SENSITIVE_REDACTED` is logged.
- Fixed perfect match missed for headers with empty values.
- Restricted variable integer decoding to uint32 to prevent run-away computation. With thanks to `Hiroki Nishino`_.
[RISCV] Extend legal addressing modes to support 26-bit addi/Xqcilo offsets (#204734)
Extend `RISCVTargetLowering::isLegalAddImmediate` and `isLegalAddressingMode`
to accept 26-bit signed immediates/offsets when the corresponding Qualcomm uC
extensions are enabled
These callbacks are queried by some pre-ISel passes. Adding support for
the wider range lets those passes keep large immediates inline and large offsets
folded into addressing modes.
[AArch64] Add hip12 to release notes. (#205899)
This adds the hip12 cpu added in #203446 to the release notes, and
rejigs them to match the format used in previous releases.
[GVN] Support load PRE through select addresses (incl. indexed selects) (#203863)
This resurrects and extends the approach from the reverted
[D142705](https://reviews.llvm.org/D142705) ("[GVN] Support address
translation through select instructions"), adapting it to the current
GVN dependency model so that GVN can eliminate a redundant load whose
address is a `select` hidden behind cast/GEP indexing (the classic
`std::min_element` / min-index idiom, e.g. `data[*it] < data[*smallest]`
or returning the index `minloc`).
### What it does
When PHI translation of a load address fails along an edge because the
incoming value resolves to a `select`, we now translate **both** sides
of
that select to obtain the "true" and "false" addresses. If both
addresses
have a dominating, non-clobbered value of the right type, the load is
rematerialized as a `select` of those two values, letting the
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x509_vfy: sync get_crl_sk() with BoringSSL and OpenSSL
Among CRLs with the same score prefer the one with the most recent
lastUpdate (RFC 5280 thisUpdate). This pulls in OpenSSL commits
626aa248, e032117d, 8b7c51a0 from 2016, so before the license change.
This uses the annoying ASN1_TIME_diff() API, but there is no better
way, really. Every other ASN1_TIME API will be just as awkward.
This fixes the currently failing x509_crl test cases.
ok kenjiro
[clang][bytecode] Don't check instance pointers for mutability (#205820)
The instance pointer being mutable is perfectly fine, we just can't read
anything from it.
This regresses a test case in `cxx11.cpp` where we now diagnose an extra
frame for `U(g1.u)`, but this seems correct since the read is happening
in the copy constructor of `U`.
unbreak build on arm64 until the compiler is actually fixed
fatal error: error in backend: Cannot implicitly convert a scalable size to a fixed-width size in `TypeSize::operator ScalarTy()`
clang++: error: clang frontend command failed with exit code 70 (use -v to see invocation)
[SPIR-V] Fix correction shift for i8 bitreverse in shader mode (#203829)
selectBitreverse16 hardcoded the post-reverse shift to 16, but it also
handles i8, where the reversed bits land in [31:24] and a shift of 16
truncated to always 0
Compute the shift as `32 - bitwidth` instead
