[LoongArch] Lower vector sign extension with VSLLWIL and VEXTH
vsllwil.{h.b/w.h/d.w} with a zero shift amount sign-extends the low half
of the source elements, and vexth.{h.b/w.h/d.w} the high half. The old
lowering needed vslti + vilvl for the low half. Although vsllwil has a
higher latency and lower throughput than vilvl, it replaces two
single-cycle instructions with the same total latency and issue cost,
so it saves an instruction. For the custom SIGN_EXTEND legalization,
vsllwil + vexth also replaces vslti + vilvl + vilvh and shortens the
high-half path.
Chaining two vsllwil for a 4x SIGN_EXTEND_VECTOR_INREG would cost more
than the alternative, so interleave the source with itself twice with
vilvl, which replicates each element across its destination element,
and shift the top copy down with vsrai. When only the sign bits are
demanded, the vsrai is dropped.
[libc++] Fix incorrect size check when growing std::string (#232737)
When trying to grow very large amounts the `max_size()` check could fail
due to the result of adding the current capacity and the additional
capacity could wrap.
www/pomerium: Fix build with WITH_PIE
Go cannot internally link PIE executables on freebsd/amd64, so
-buildmode=pie (added by Uses/go.mk when WITH_PIE is set) requires
cgo and external linking. The port builds with CGO_ENABLED=0, like
upstream does, so the build failed with:
-buildmode=pie requires external (cgo) linking, but cgo is not enabled
Set PIE_UNSAFE to build a regular executable instead.
[TableGen] Share identical super-register class masks (#224633)
For a register class and one sub-register index, the register info
emitter generates a bit mask with a bit set for every class whose
registers have that sub-register in this class. A class gets one mask
for each sub-register index for which such classes exist. These masks
were stored in the SubClassMasks array right after the class's sub-class
mask and read by striding from it, so the position of a mask determined
which class and sub-register index it belonged to. Identical masks of
different classes and sub-register indices therefore could not be
shared. AMDGPU has 15,145 such masks, only 1,035 of them distinct, and
one is repeated 370 times.
This patch emits each distinct mask once, into a pool that follows the
sub-class masks in the SubClassMasks array, and gives each class an
array of offsets into that pool, one per mask. The offsets are relative
to the MCRegisterClass object, which is the convention SubClassMaskOff
and SuperRegIndicesOff already use, so the storage remains a constant
initializer that needs no relocations.
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