LLVM/project df3fb0cclang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

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LLVM/project fcc998eclang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

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LLVM/project 6b318beclang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] initial version

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LLVM/project cf45b55clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

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LLVM/project 9d8a9aeclang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] initial version

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LLVM/project 739e851clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

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LLVM/project 042e0dfclang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

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LLVM/project 89d22ffclang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] initial version

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LLVM/project cdbbdd8clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
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LLVM/project 61d74c1clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

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LLVM/project 2134fd1clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

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LLVM/project f387c40clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
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LLVM/project ee0fd44clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
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LLVM/project 975a1baclang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
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LLVM/project 08d77f0clang/docs ClangIRCleanupAndEHDesign.md index.rst

[CIR][docs] C++ cleanup and exception handling design for CIR (#177625)

This change adds a document describing a new design for C++ cleanups and
exception handling in CIR.
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+1-0clang/docs/index.rst
+1,428-02 files

OpenZFS/src 4f180e0module/zfs dmu_recv.c, tests/runfiles common.run

Fix activating large_microzap on receive

This ensures that the in-memory state of the feature is recorded and
that `dsl_dataset_activate_feature` is not called when the feature
is already active.

Reviewed-by: Alexander Motin <alexander.motin at TrueNAS.com>
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Austin Wise <AustinWise at gmail.com>
Closes #18143
Closes #18144
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+91-0tests/zfs-tests/tests/functional/rsend/send_large_microzap_incremental.ksh
+20-18module/zfs/dmu_recv.c
+2-0tests/zfs-tests/tests/Makefile.am
+1-0tests/zfs-tests/include/tunables.cfg
+1-0tests/runfiles/common.run
+215-186 files

FreeNAS/freenas 372cf57src/middlewared/middlewared/plugins/interface sync.py

flake8
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LLVM/project 34c98b2clang/unittests/Analysis/FlowSensitive UncheckedStatusOrAccessModelTestFixture.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
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LLVM/project 6a40596.github/workflows commit-access-review.yml

Run unbuffered
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FreeNAS/freenas 14841b0src/middlewared/middlewared/plugins/interface vlan.py bridge.py

optimizie interface/sync.py
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+11-5src/middlewared/middlewared/plugins/interface/vlan.py
+11-4src/middlewared/middlewared/plugins/interface/bridge.py
+11-4src/middlewared/middlewared/plugins/interface/bond.py
+9-3src/middlewared/middlewared/plugins/interface/sync.py
+42-164 files

OpenZFS/src 20f94efcontrib/pyzfs/docs/source index.rst, contrib/pyzfs/libzfs_core _libzfs_core.py _error_translation.py

pyzfs: remove unimplemented libzfs_core functions from pyzfs

As per #9008, pyzfs implements and documents several functions that
would be very useful, but then try to call c functions in libzfs_core.
These functions do not exist in libzfs_core, and in the ~7 years of
ticket creation still do not exist in libzfs_core.

It seems unlikely that these functions will get implemented, though 2
years ago, ~5 years after that ticket lzc_get_props was implemented in
23a489a41167890cdd227366a5f950170df8cc9b which enabled get properties in
pyzfs. Sadly the first thing the  pyzfs function for lzc_get_props does
is call _list, which cals lzc_list, which is not implmented. And the
functions to set or inherit properties are still missing.

Having these functions in pyzfs are misleading, footguns, and time
wasters when evaluating pyzfs.

Removing these functions from pyzfs means that _if_ these functions are
added in libzfs_core, then pyzfs will also need to re-implement these

    [8 lines not shown]
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+0-337contrib/pyzfs/libzfs_core/test/test_libzfs_core.py
+0-58contrib/pyzfs/libzfs_core/_error_translation.py
+0-10contrib/pyzfs/libzfs_core/__init__.py
+0-4contrib/pyzfs/libzfs_core/bindings/libzfs_core.py
+1-2contrib/pyzfs/docs/source/index.rst
+2-7606 files

LLVM/project 53ae315.github/workflows commit-access-review.py

Fix
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FreeBSD/ports 36632bcsecurity/boringssl distinfo Makefile, security/boringssl/files patch-CMakeLists.txt

security/boringssl: update to the recent snapshot

Sponsored by:   tipi.work
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+12-84 files

LLVM/project 265837dclang/test/CodeGenHLSL inline-functions.hlsl, llvm/test/CodeGen/DirectX/ShaderFlags lib-entry-attr-error.ll disable-opt-lib.ll

fix tests
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+0-30llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll
+10-5llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
+5-9clang/test/CodeGenHLSL/inline-functions.hlsl
+6-2llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
+21-464 files

LLVM/project 028fe25clang/lib/CodeGen CGHLSLRuntime.cpp, llvm/lib/Target/DirectX DXILShaderFlags.cpp

remove optnone from entry function and use module flag instead
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+8-1clang/lib/CodeGen/CGHLSLRuntime.cpp
+16-132 files

LLVM/project 67c3d5d.github/workflows commit-access-review.py

workflows/commit-access-review.py: Print rate limit info

This script is hitting the rate limits, so this extra debugging output
should make it easier to figure out why.
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+36-0.github/workflows/commit-access-review.py
+36-01 files

NetBSD/src bhffCRXusr.bin/make main.c, usr.bin/make/unit-tests Makefile

   Add .MAKE.VERSION as read-only variable

   If MAKE_VERSION is defined, create ${.MAKE.VERSION} read-only
   and retain ${MAKE_VERSION} for backwards compatibility.
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1.376+2-2usr.bin/make/unit-tests/Makefile
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FreeNAS/freenas d38605fsrc/middlewared/middlewared/plugins network.py, src/middlewared/middlewared/plugins/interface bridge.py sync.py

NAS-139642 / 26.0.0-BETA.1 / add configure_bridges_impl (#18155)

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+5-11src/middlewared/middlewared/plugins/network.py
+4-0src/middlewared/middlewared/plugins/interface/sync.py
+68-693 files

LLVM/project 6441f1cllvm/docs RISCVUsage.rst, llvm/lib/Target/RISCV RISCVFeatures.td

[RISCV] Introduce a new syntax for processor-specific tuning feature strings (#175063)

This patch proposes new a tuning feature string format that helps users
to build a performance model by "configuring" an existing tune CPU,
along with its scheduling model. For example, this string
```
"sifive-x280:single-element-vec-fp64"
```
takes ``sifive-x280`` as the "base" tune CPU and configured it with
``single-element-vec-fp64``. This gives us a performance model that
looks exactly like that of ``sifive-x280``, except some of the 64-bit
vector floating point instructions now produce only a single element per
cycle due to ``single-element-vec-fp64``.

This string could eventually be used in places like ``-mtune`` at the
frontend. Right now, this patch only implements the parser part, which
is put under the TargetParser library.

The grammar for this string is:

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+93-45llvm/lib/Target/RISCV/RISCVFeatures.td
+131-0llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
+119-1llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp
+40-0llvm/docs/RISCVUsage.rst
+32-1llvm/test/TableGen/riscv-target-def.td
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+658-528 files

NetBSD/pkgsrc tmkBOYTdoc CHANGES-2026

   Update of vim
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