[Flang][Driver] Add support for '-fprofile-sample-use' option (#188697)
When the `-fprofile-sample-use=sample.prof` option is passed, the
compiler records the profile file path in `SampleProfileFile` . This
value is later used by the `SampleProfileLoaderPass`, which loads the
sample profile and injects the corresponding profiling metadata in the
LLVM IR.
emulators/rpcs3: unbreak build after 1b59de75bd3d
In file included from rpcs3/Emu/Cell/lv2/sys_usbd.cpp:44:
rpcs3/Emu/../Emu/Io/LogitechG27.h:41:2: error: unknown type name 'SDL_HapticEffectID'; did you mean 'SDL_HapticEffect'?
41 | SDL_HapticEffectID effect_id = -1;
| ^~~~~~~~~~~~~~~~~~
| SDL_HapticEffect
/usr/local/include/SDL3/SDL_haptic.h:925:3: note: 'SDL_HapticEffect' declared here
925 | } SDL_HapticEffect;
| ^
In file included from rpcs3/Emu/Cell/lv2/sys_usbd.cpp:44:
rpcs3/Emu/../Emu/Io/LogitechG27.h:41:33: error: no viable conversion from 'int' to 'SDL_HapticEffect'
41 | SDL_HapticEffectID effect_id = -1;
| ^~
/usr/local/include/SDL3/SDL_haptic.h:915:15: note: candidate constructor (the implicit copy constructor) not viable: no known conversion from 'int' to 'const SDL_HapticEffect &' for 1st argument
915 | typedef union SDL_HapticEffect
| ^~~~~~~~~~~~~~~~
/usr/local/include/SDL3/SDL_haptic.h:915:15: note: candidate constructor (the implicit move constructor) not viable: no known conversion from 'int' to 'SDL_HapticEffect &&' for 1st argument
915 | typedef union SDL_HapticEffect
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Revert "Reland "[mlir][reducer] Add eraseRedundantBlocksInRegion and getSuccessorForwardOperands API to BranchOpInterface"" (#190727)
To decouple the BranchOpInterface implementation from the reduction-tree
changes. Reverts llvm/llvm-project#189253,
[mlir][CSE] Fix CSE markAnalysesPreserved<DominanceInfo, PostDominanceInfo> comment (#190471)
The original comment claimed that DominanceInfo and PostDominanceInfo
could be preserved because region operations are not removed. However,
the real reason was that the original CSE only deleted redundant
operations without moving any operation to a different block, leaving
the dominance tree structure unchanged. Part of
https://github.com/llvm/llvm-project/pull/180556.
[libc++][docs] Update paper and LWG issue lists after 2026-03 meeting (#189901)
[P3726R2](https://wg21.link/P3726R2) is a Core paper but adds
`std::start_lifetime`, so it needs to be listed in libc++'s
documentation.
For LWG issues, see [P4145R0](https://wg21.link/P4145R0) and
[P4146R0](https://wg21.link/P4146R0).
[CodeGenPrepare] Use Instruction::comesBefore instead of manual ordering (#190485)
After #172329, we noticed that some sources compiled with MSan take
1000x longer to compile. This is caused by quadratic complexity in
tryToSinkFreeOperands, which can be called on a significant number
of instructions within huge basic blocks.
This inefficiency was introduced in 9cfa9b4, which manually iterates
and creates a DenseMap of entire basic blocks for each interesting
instruction.
This patch avoids the manual ordering by using
Instruction::comesBefore(), which provides the exact same
ordering much more efficiently.
[clang-tidy] Fix performance-trivially-destructible with C++20 modules (#178471)
When a class definition is seen through both a header include and a
C++20 module import, destructors may appear multiple times in the AST's
redeclaration chain. The original matcher used `isFirstDecl()` which
fails in this scenario because the same declaration can appear as both
first and non-first depending on the view.
Replace `unless(isFirstDecl())` with `isOutOfLine()` which correctly
identifies out-of-line definitions by checking whether the lexical
context differs from the semantic context.
Also update clang-tools-extra's lit.cfg.py to call `use_clang()` instead
of `clang_setup()` to make the `%clang` substitution available for
tests.
Fixes #178102
Co-authored-by: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
fix timer emulation-related VM hangs
This fixes state machine issues that resulted in hangs with OpenBSD-i386 VMs
when using the i8254 hardware timecounter with vmm. This also manifested in
incorrect i8254 calibration (wrong CPU speed in dmesg).
tested with Debian 12 amd64, i386
Apine Linux 3.23 x86 (with 4GB memory), x86_64
OpenBSD 7.9 beta amd64, i386
ok mlarkin@
japanese/font-migu: Update to 1.0.20231123 and take maintainership
In this release, the version numbers for 1? and 2m are different.
Update MASTER_SITES, DISTFILES, WWW and pkg-descr.
Changelog (japanese):
https://itouhiro.github.io/mixfont-mplus-ipa/changelog.html
PR: 277658
Approved by: hrs (maintainer timeout > 3 months)
Approved by: osa (mentor)
[flang][cuda] Lower unified variables as cuf.alloc in main program scope (#190713)
Remove the unified exception from CanCUDASymbolBeGlobal so unified
variables follow the same cuf.alloc lowering path as other CUDA data
attributes.
[AMDGPU] asyncmark support for ASYNC_CNT (#185813)
The ASYNC_CNT is used to track the progress of asynchronous copies
between global and LDS memories. By including it in asyncmark, the
compiler can now assist the programmer in generating waits for
ASYNC_CNT.
Assisted-By: Claude Sonnet 4.5
This is part of a stack:
- #185813
- #185810
Fixes: LCOMPILER-332
[AMDGPU] Fix setreg handling in the VGPR MSB lowering
There are multiple issues with it:
1. It can skip inserting S_SET_VGPR_MSB if we set the mode via
piggybacking. We are now relying on the HW bug for correct
behavior. If/when the bug is fixed lowering will be incorrect.
2. We should just unconditionally update MSBs if immediate allows it.
We shall set correct bits and keep the rest of the immediate
(that is done). There is no reasonable way for an user to change
MSBs nor does it do anything good to set it with SETREG and then
immediately overwrite with S_SET_VGPR_MSB.
3. We can always update immediate if Offset is zero.
4. Redundant mode changes created as seen in the
hazard-setreg-vgpr-msb-gfx1250.mir.
With unconditional immediate update most of time and not relying on
the SETREG for setting MSBs there is no good reason to complicate
handling by supporting SETREG as a piggybacking target. Moreover,
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Update devel/p5-DateTime-TimeZone to 2.67
This release is based on version 206a of the Olson database. This
release includes contemporary changes for Moldova.
Move {load,store}(llvm.protected.field.ptr) lowering to InstCombine.
The previous position of llvm.protected.field.ptr lowering for loads
and stores was problematic as it not only inhibited optimizations such
as DSE (as stores to a llvm.protected.field.ptr were not considered to
must-alias stores to the non-protected.field pointer) but also required
changes to other optimization passes to avoid transformations that would
reduce PFP coverage.
Address this by moving the load/store part of the lowering to
InstCombine, where it will run earlier than the PFP-breaking and
AA-relying transformations. The deactivation symbol, null comparison
and EmuPAC parts of the lowering remain in PreISelLowering.
Now that the transformation inhibitions are no longer needed, remove them
(i.e. partially revert #151649, and revert #182976).
This change resulted in a 2.4% reduction in Fleetbench .text size and
the following improvements to PFP performance overhead for BM_PROTO_Arena
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[RISCV] Use per-SEW immediate inversion for vrol intrinsic patterns (#190113)
The VPatBinaryV_VI_VROL multiclass was using InvRot64Imm for all SEW
widths when converting vrol immediate intrinsics to vror.vi. This
produced unnecessarily large immediates for narrower element types
(e.g., 61 instead of 5 for SEW=8 rotate-left by 3).
Use the appropriate InvRot{SEW}Imm transform to match what the SDNode
patterns already do.
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
