FreeBSD/src 3a4e037sys/dev/ixgbe if_fdir.c

ixgbe: Leave run-state publication to iflib during FDIR recovery

Rebuilding the Flow Director tables does not initialize the interface
or restore its queues.  Do not set IFF_DRV_RUNNING from that operation:
iflib owns the flag, and may have cleared it while a watchdog reset is
pending.  Restoring it here could admit traffic before the deferred
stop and initialization have run.

Keep the table rebuild and Flow Director interrupt re-enable unchanged.
This path is conditional on IXGBE_FDIR.

MFC after:      2 weeks
Sponsored by:   BBOX.io
DeltaFile
+0-3sys/dev/ixgbe/if_fdir.c
+0-31 files

LLVM/project d905d39llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU schedule-amdgpu-trackers-attribute.ll

[AMDGPU] Add function attribute amdgpu-use-amdgpu-trackers
DeltaFile
+45-0llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers-attribute.ll
+15-2llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+60-22 files

LLVM/project 46fc5bdclang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

[CIR] Accept `_BitInt` wider than 128 bits in x86_64 callconv lowering

With byval in place, a `_BitInt` wider than 128 bits can classify
Indirect and flow through the same byval/sret path as an oversized
aggregate.

That turned up a latent bug, fixed here since it was not reachable or
testable before: the byval/sret pointee type was using the raw declared
width instead of the padded storage width (e.g. `i200` instead of
`i256`), understating the copy size.

Widths whose padded storage integer is not a whole number of 16 bytes,
such as `_BitInt(129)` at `i192`, still have no in-memory layout in CIR
and now reach that gap through the byval and sret pointee instead of
through the classifier.  They stay NYI.

Drop the opt-out from the three CIR lit tests gated on this.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+201-0clang/test/CIR/Transforms/abi-lowering/x86_64-bitint.cir
+61-35clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+22-24clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+24-10clang/test/CIR/CodeGen/bitint-split-storage-nyi.c
+34-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-bitint.c
+0-24clang/test/CIR/Transforms/abi-lowering/x86_64-int-nyi.cir
+342-933 files not shown
+350-1049 files

LLVM/project f77ec64llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP] Fix -Wunused-lambda-capture in #223016 (#223053)

Clang will warn on this despite this being required for MSVC, so add a
workaround for now.
DeltaFile
+2-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-21 files

NetBSD/pkgsrc-wip 645c111raven PLIST DESCR

raven: Initial package
DeltaFile
+284-0raven/distinfo
+95-0raven/go-modules.mk
+20-0raven/Makefile
+7-0raven/COMMIT_MSG
+5-0raven/DESCR
+2-0raven/PLIST
+413-06 files

OpenZFS/src 99831decmd/zdb zdb.c, include libzdb.h

zdb: Allow filtering on zvol objects

Allow "v" flag for object ID range filters for filtering on zvol
objects. Also, fixup tests so that "v" is now considered a valid
flag.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Glenn Washburn <development at efficientek.com>
Closes #19069
DeltaFile
+6-0cmd/zdb/zdb.c
+1-1tests/zfs-tests/tests/functional/cli_root/zdb/zdb_object_range_neg.ksh
+2-0man/man8/zdb.8
+2-0include/libzdb.h
+11-14 files

LLVM/project 778d915llvm/docs/CommandGuide llvm-ir2vec.md, llvm/docs/tutorial BuildingAJIT4.md

[docs] Repair stale LLVM documentation links

Use the Sphinx ref role for the IR2Vec section label so clean Sphinx
builds resolve it correctly. Remove the dangling BuildingAJIT Chapter 5
navigation text because that chapter no longer exists.

Fixes follow-up issues in #222506.
DeltaFile
+0-2llvm/docs/tutorial/BuildingAJIT4.md
+1-1llvm/docs/CommandGuide/llvm-ir2vec.md
+1-32 files

LLVM/project 393710bllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64ec-varargs.ll sme-za-tailcall-fpdiff-align.ll

Reland "[llvm][AArch64] Ensure stack alignment in non-sibcall tail calls with FPDiff" (#220406)

When a caller has a non-multiple of the minimum stack alignment more
argument stack space than the callee it is tail calling, we need to ensure that
the resulting FPDiff's magnitude has been rounded up to a multiple of the
platform's minimum stack alignment.

In this re-land there is a fixup to 234ce03692ede13ffd2fcb35570d801c1e332814,
which, because of the wrong order, wasn't actually moving NumBytes after
FPDiff had been re-aligned.

rdar://184474075
DeltaFile
+79-0llvm/test/CodeGen/AArch64/sme-za-tailcall-fpdiff-align.ll
+31-0llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
+10-4llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+120-43 files

LLVM/project 7af6d3allvm/lib/Target/ARM Thumb2SizeReduction.cpp, llvm/test/CodeGen/ARM cmse-harden-call-returned-values.ll

ARM: Track CPSR liveness in Thumb2SizeReduction without kill flags

Thumb2SizeReduction narrows a 32-bit instruction to its flag-setting
16-bit form only when CPSR is dead afterwards. It determined this from
kill flags on CPSR operands. Kill flags have been semi-deprecated
for over a decade, so avoid relying on them. Liveness should be evaluated
as a reverse walk over a block.

The existing forward walk over the block is still necessary as a separate
step for the different A9 avoidCPSRPartialUpdate optimization.

Co-Authored-By: Claude claude-opus-4.8 <noreply at anthropic.com>
DeltaFile
+122-0llvm/test/CodeGen/Thumb2/thumb2-reduce-size-cpsr.mir
+40-69llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
+2-2llvm/test/CodeGen/ARM/cmse-harden-call-returned-values.ll
+164-713 files

LLVM/project 364bed3clang/include/clang/Driver ToolChain.h, clang/lib/Driver ToolChain.cpp

(NFC)[Clang][Driver] Add ToolChain::GetFilePathIfExists and use it (#221063)

Replaces patterns like `if (TC.GetFilePath("file") != "file")` to avoid
repeating `"file"`.
DeltaFile
+8-0clang/lib/Driver/ToolChain.cpp
+2-3clang/lib/Driver/ToolChains/Cygwin.cpp
+1-2clang/lib/Driver/ToolChains/Gnu.cpp
+1-1clang/lib/Driver/ToolChains/WebAssembly.cpp
+1-0clang/include/clang/Driver/ToolChain.h
+13-65 files

LLVM/project 4a5bfd3llvm/test/Verifier llvm.loop.align.ll

Address comments
DeltaFile
+14-9llvm/test/Verifier/llvm.loop.align.ll
+14-91 files

LLVM/project 26c6f83llvm/docs LangRef.md, llvm/lib/CodeGen MachineBlockPlacement.cpp

IR: Add verifier checks and LangRef for llvm.loop.align

Verify the nested !{!"llvm.loop.align", i32 N} tag.
Require exactly two operands, an integer constant of type i32 or smaller,
and a positive power-of-two value

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+121-0llvm/test/Verifier/llvm.loop.align.ll
+28-0llvm/test/Assembler/llvm.loop.align.ll
+27-0llvm/lib/IR/Verifier.cpp
+15-0llvm/docs/LangRef.md
+0-3llvm/lib/CodeGen/MachineBlockPlacement.cpp
+191-35 files

FreeBSD/src 33be59bsys/dev/ice if_ice_iflib.c

ice: Use the mirror interface softc in PF callbacks

PF iflib callbacks receive struct ice_softc, not struct ice_mirr_if.
Resolve the mirror interface through sc->mirr_if before checking or
resetting subinterface state.

Use the same mirror softc when rebuilding its VSI.  This records the
required subinterface reset in the state consumed by the PF callback,
rather than overlaying the PF softc and leaving rebuilt queues stopped.

MFC after:      2 weeks
Sponsored by:   BBOX.io
DeltaFile
+12-8sys/dev/ice/if_ice_iflib.c
+12-81 files

LLVM/project 0cf16f9clang/test/AST/HLSL Textures-AST.hlsl, clang/test/CodeGenHLSL/resources Textures-SampleCmpLevelZero.hlsl Textures-SampleCmp.hlsl

Add missing macro descriptions to tests
DeltaFile
+5-0clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
+4-0clang/test/CodeGenHLSL/resources/Textures-SampleCmpLevelZero.hlsl
+4-0clang/test/CodeGenHLSL/resources/Textures-SampleCmp.hlsl
+4-0clang/test/CodeGenHLSL/resources/Textures-SampleBias.hlsl
+4-0clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
+4-0clang/test/AST/HLSL/Textures-AST.hlsl
+25-06 files not shown
+40-012 files

LLVM/project 8d6ce2fclang/lib/CodeGen CGHLSLBuiltins.cpp

Derive the coordinate width from the resource attribute for better readability
DeltaFile
+14-9clang/lib/CodeGen/CGHLSLBuiltins.cpp
+14-91 files

LLVM/project 5460725clang/test/CodeGenHLSL/resources Textures-SampleCmp.hlsl Textures-SampleGrad.hlsl

Reorganize RUN lines in tests. Remove unused macros
DeltaFile
+100-158clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
+106-132clang/test/CodeGenHLSL/resources/Textures-SampleBias.hlsl
+106-132clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
+105-131clang/test/CodeGenHLSL/resources/Textures-SampleLevel.hlsl
+93-109clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
+82-107clang/test/CodeGenHLSL/resources/Textures-SampleCmp.hlsl
+592-76921 files not shown
+1,214-1,34527 files

LLVM/project c782d0aclang/test/CodeGenHLSL/resources Textures-Mips.hlsl Textures-CalculateLevelOfDetail.hlsl, clang/test/SemaHLSL/Resources Textures-Subscript.hlsl

Fold Texture3D into the texture tests after the rebase
DeltaFile
+42-45clang/test/SemaHLSL/Resources/Textures-Subscript.hlsl
+43-37clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
+25-35clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
+25-23clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
+14-18clang/test/CodeGenHLSL/resources/Textures-CalculateLevelOfDetail.hlsl
+19-5clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
+168-16316 files not shown
+217-18722 files

LLVM/project 429c883clang/lib/Sema SemaHLSL.cpp

Apply clang-format
DeltaFile
+0-1clang/lib/Sema/SemaHLSL.cpp
+0-11 files

LLVM/project 1b30e18clang/test/AST/HLSL Textures-AST.hlsl Textures-vector-AST.hlsl, clang/test/CodeGenHLSL/resources Textures-SampleGrad.hlsl Textures-Subscript.hlsl

[HLSL] Implement Texture1D and its variants
DeltaFile
+297-159clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
+213-175clang/test/AST/HLSL/Textures-vector-AST.hlsl
+213-175clang/test/AST/HLSL/Textures-scalar-AST.hlsl
+245-106clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
+205-115clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
+162-115clang/test/AST/HLSL/Textures-AST.hlsl
+1,335-84524 files not shown
+2,670-1,42230 files

LLVM/project 2f20ecfclang/lib/Sema HLSLBuiltinTypeDeclBuilder.cpp

Assert that result ty vec and the Elts size are the same
DeltaFile
+2-0clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+2-01 files

LLVM/project 7188b03clang/include/clang/Basic Builtins.td, clang/lib/CodeGen CGHLSLBuiltins.cpp

Use CustomTypeChecking with texture builtins
DeltaFile
+42-82clang/lib/Sema/SemaHLSL.cpp
+117-0clang/test/SemaHLSL/BuiltIns/resource_sample-errors.hlsl
+52-0clang/test/SemaHLSL/BuiltIns/resource_load-errors.hlsl
+42-0clang/test/SemaHLSL/BuiltIns/resource_gather-errors.hlsl
+4-34clang/lib/CodeGen/CGHLSLBuiltins.cpp
+12-12clang/include/clang/Basic/Builtins.td
+269-1287 files not shown
+311-18213 files

FreeBSD/src 372803dsys/dev/ixl ixl_pf_iflib.c

ixl: Set critical-error state bits independently

ixl_set_state() takes a bit index, not a bit mask.  ORing the
reset request and critical error indices produced the global reset
index, so a critical interrupt could mask its cause without scheduling
the intended PF reset.

Set both state bits explicitly.

MFC after:      2 weeks
Sponsored by:   BBOX.io
DeltaFile
+2-2sys/dev/ixl/ixl_pf_iflib.c
+2-21 files

LLVM/project e03e9eellvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/lib/Target/SystemZ SystemZTargetMachine.cpp

[SystemZ][z/OS] Handle constants with initializers with relocations

When the initializer of a constant needs relocations, the constant
cannot be placed into the code section, because the loader needs
a writable section to fixup the relocation.
This change
 - sets the relocation model for z/OS to `DynamicNoPIC`, which better
   fits the relocation handling than `Static`, and
 - treats section kind `ReadOnlyWithRel` like a variable.
DeltaFile
+27-0llvm/test/CodeGen/SystemZ/zos-section-readonlywithrel.ll
+16-5llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+1-1llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+44-63 files

LLVM/project 5c27600clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl, llvm/lib/Target/DirectX DXILResourceAccess.cpp

[DirectX] Add texture support to atomicrmw lowering (#221369)

Fixes https://github.com/llvm/llvm-project/issues/218034
Fixes https://github.com/llvm/llvm-project/issues/186154

atomicrmw lowering didn't support textures. This PR adds that missing
support.

Assisted by: Claude Opus 5
DeltaFile
+57-16llvm/lib/Target/DirectX/DXILResourceAccess.cpp
+64-0llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-unsupported-kind.ll
+64-0llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
+62-0llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture.ll
+52-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+11-11llvm/test/CodeGen/DirectX/ResourceAtomicBinOp.ll
+310-273 files not shown
+320-359 files

LLVM/project 4829edbllvm/test/CodeGen/AArch64 vector-ldst-align-float.ll, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.960bit.ll amdgcn.bitcast.512bit.ll

rebase

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+58,041-56,845llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+17,286-3,454llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-sve-instructions.s
+13,787-6,856llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-sve-instructions.s
+7,201-7,331llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,576-5,657llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+9,921-0llvm/test/CodeGen/AArch64/vector-ldst-align-float.ll
+111,812-80,14321,743 files not shown
+1,412,013-706,39221,749 files

LLVM/project e39d404llvm/test/CodeGen/AArch64 vector-ldst-align-float.ll, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.960bit.ll amdgcn.bitcast.512bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1-arichardson

[skip ci]
DeltaFile
+58,041-56,845llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+17,286-3,454llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-sve-instructions.s
+13,787-6,856llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-sve-instructions.s
+7,201-7,331llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,576-5,657llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+9,921-0llvm/test/CodeGen/AArch64/vector-ldst-align-float.ll
+111,812-80,14321,743 files not shown
+1,412,015-706,39421,749 files

FreeBSD/src 99eaf07sys/dev/vmware/vmxnet3 if_vmx.c

vmxnet3: Propagate device-enable failure to iflib

Do not let iflib publish a running interface when the virtual device
rejected its enable command.  Mark initialization failed and leave the
interface stopped.

MFC after:      2 weeks
Sponsored by:   BBOX.io
DeltaFile
+4-1sys/dev/vmware/vmxnet3/if_vmx.c
+4-11 files

LLVM/project 5145033bolt/runtime instr.cpp sys_aarch64.h

[BOLT][AArch64][Android] Only the dumping thread can longjmp (#222719)

`__bolt_instr_recovery_active` is a process global flag and the reader
in `boltHandleFatalAndRecover()` runs on any thread. When a dump is in
flight, another thread that fails `assert()` or exhausts `GlobalAlloc`
in `instrumentIndirectCall()` could see the flag set, longjmp with the
dumping thread's buffer and restore the dump thread's sp/fp/lr. This
is wrong since the thread would then run on the dumping thread's stack
and later release a mutex that it does not own or hold.

`GlobalWriteProfileMutex` already serializes the writers, so one buffer
would be sufficient; only the reader side needs to know who owns the
buffer. Replace the flag with `__bolt_instr_recovery_tid` holding the
owner's thread ID, and longjmp only when it matches `__gettid()`. Other
threads will fall through to just record the failure and return.

Added a `__gettid()` syscall wrapper, for aarch64 only.

Assited-by: opus
DeltaFile
+9-6bolt/runtime/common.h
+11-0bolt/runtime/sys_aarch64.h
+3-3bolt/runtime/instr.cpp
+23-93 files

LLVM/project 105ff16llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp, llvm/lib/Target/RISCV/MCTargetDesc RISCVELFStreamer.cpp RISCVBaseInfo.cpp

[RISCV] Change RISCVABI::computeTargetABI() to return Expected<ABI>

Return Expected<ABI> instead of printing to errs()/reportFatalUsageError
internally, so callers decide whether to fall back to the default ABI
or treat the failure as fatal, and so it's unit-testable. Also fold the
duplicated Hard-float 'f'/'d' ABI checks from RISCVAsmParser.cpp and
RISCVISelLowering.cpp into computeTargetABI(), and add RISCVBaseInfoTest
coverage for the error paths.

This change was created with the help of AI tools

Reviewed By: lenary

Pull Request: https://github.com/llvm/llvm-project/pull/213410
DeltaFile
+61-59llvm/test/MC/RISCV/target-abi-invalid.s
+34-30llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+41-1llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+15-15llvm/test/CodeGen/RISCV/target-abi-invalid.ll
+10-16llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+17-2llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+178-1235 files not shown
+196-14211 files

LLVM/project 204b703utils/bazel/llvm-project-overlay/libc/test/UnitTest BUILD.bazel

Fix bazel build for libc/test/UnitTest:string_utils (#223051)

Fixes https://github.com/llvm/llvm-project/pull/222988 (commit
18db3eee9d04) by adding missing dependencies.
DeltaFile
+3-0utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
+3-01 files