[3/3][RegAlloc][LiveRegMatrix] Added validity check between VRM and LRM. (#197778)
Check that every VRM-assigned vreg with a non-empty live interval must
have its segments in the Matrix for its assigned physical reg.
Depends on https://github.com/llvm/llvm-project/pull/197773 and
https://github.com/llvm/llvm-project/pull/197776. While there are no
source conflicts, adding this verification without the other 2 patches
would make the following LIT tests fail.
CodeGen/X86/AMX/amx-gemm.ll
CodeGen/X86/apx/push2-pop2.ll
CodeGen/X86/udivmodei5.ll
CodeGen/X86/apx/pr191368.ll
Assisted-by: Cursor/Claude Opus
[CIR] Use target int and size_t widths in cir.libc.memchr (#217153)
This patch adds support for target sized operands on cir.libc.memchr.
The operation previously required a 32 bit pattern and a 64 bit length,
which made __builtin_memchr fail verification when size_t was 32 bits.
CIRGen now records the target int and size_t widths on the module as
cir.int_type_width and cir.size_type_width. The operands take any
fundamental width of the matching signedness. The verifier checks them
against the record, requires src to be in the default address space and
requires the result type to match src. The textual form prints the
operand types, so the previous textual form no longer parses. The
sizeTypeSize computation uses TargetInfo::getSizeType() now that it
feeds cir.size_type_width, which preserves the width while making the
source type explicit.
DirectToLLVM accepts x86_64 and AArch64 with a 32 bit int and a 64 bit
size_t, and x32 with a 32 bit int and size_t. AArch64 with 32 bit
pointers is rejected. The Linux and Darwin signatures are checked
against classic CodeGen and other target and width combinations are
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[lldb-dap] Migrate core file test (#217403)
- TestDAP_save_core.py
- TestDAP_coreFile.py
There is a bug in the number of modules reported from the core file in
TestDAP_save_core.py. The test previously assertsTrue instead of
assertsEqual.
[SLP]Keep originals when uniques do not reduce register uses
When the vector of unqiues occupies the same register width as the
original (counting a sub-register vector as a full one), packing only
adds the reshuffle cost; keep the original vector. Loads are excluded
since packing may instead enable a wider contiguous load.
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/218294
[CIR] Add cir.cxx_module_init_fn_name and cir.static_local_info attributes (#215921)
Adds two CIR attributes that record specific declaration facts, so
passes that consume them don't have to query the AST for those particular
facts.
[DirectX] Add shader flags for heap resources (#216461)
Descriptor-heap usage must be recorded in the shader feature flags. The
`DXILShaderFlags` pass inspects each `llvm.dx.resource.handlefromheap`
call and sets the `SamplerDescriptorHeapIndexing` shader flag when
`IsSamplerHeap` is `true`, or `ResourceDescriptorHeapIndexing` flag when
it is `false`.
Fixes #213825
[X86] Rewrite MOVUPD/MOVAPD to MOVUPS/MOVAPS in X86FixupInstTuning (#217676)
MOVUPD/MOVUPS and MOVAPD/MOVAPS perform identical 16-byte moves, but the
packed double forms carry a mandatory 0x66 prefix, making them one byte
larger. We rewrite only when no domain delay would happen after this
replacement. VEX/EVEX VMOVUPD/VMOVAPD are deliberately left alone, the
0x66 requirement is folded into the pp field of the prefix, so both
encode to the same size as their packed single versions and there is
nothing to gain.
Merge tag 'hwlock-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
Pull hwspinlock updates from Bjorn Andersson:
"Propagate single-lock registration failures from radix_tree_insert(),
making caller sanity checks effective.
Update the hwspinlock MAINTAINERS repository URL to the current
remoteproc tree"
* tag 'hwlock-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux:
hwspinlock: propagate errno when registering single lock
MAINTAINERS: Update remoteproc repo url for hwspinlock
[Bazel] Configure macOS Support capabilities (#218186)
Match CMake and LLVM GN for 3 macOS capablities.
These are safe to assume because these are invariants of the macOS SDK
and Darwin: arc4random is declared, the __crashreporter_info__
annotation is supported, and struct stat exposes st_mtimespec.tv_nsec.
[CIR] Skip ABI classification for an incomplete-record declaration
A `cir.func` declaration whose signature carries an incomplete record
by value caused the pass to fail the whole module.
C++ requires a complete type at any call or definition, so only a declaration
can carry this shape, and no translation unit anywhere can ever call or define
it with real argument data. Classic CodeGen skips full ABI lowering rather than
attempting one. We now leave such a declaration unclassified and match classic.
Assisted-by: Cursor / claude-opus-5
Merge tag 'rpmsg-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
Pull rpmsg updates from Bjorn Andersson:
"Fix a GLINK endpoint teardown deadlock during driver detach and order
SMEM FIFO reads after the remote-updated availability check.
Prevent duplicate rpmsg character endpoint teardown when remoteproc
shutdown races with RPMSG_DESTROY_EPT_IOCTL.
Replace unsafe string and sysfs formatting helpers, and correct the
unregister_rpmsg_driver() return value documentation"
* tag 'rpmsg-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux:
rpmsg: glink: smem: order FIFO read after availability check
rpmsg: glink: fix deadlock in endpoint destroy during driver detach
rpmsg: char: Check for ongoing chrdev destroy
rpmsg: glink: Replace strcpy() with strscpy()
rpmsg: core: Fix incorrect return value documentation
rpmsg: Replace sprintf() with sysfs_emit() in sysfs show
[flang][OpenACC] Reject valued gang/worker/vector outside kernels (#218695)
`gang(num:)`, `worker(n)`, and `vector(n)` are only valid on a loop
associated with kernels, and then only if that kernels construct does
not already specify `num_gangs`, `num_workers`, or `vector_length`.
Decode L2 cache associativity for VIA CPUs using the AMD cache lookup table for
the 0x80000006 CPUID function associativity value.
Use `cpuid leaf 4' to get cache parameters for Zhaoxin and late VIA CPU models.
VIA datasheets mention that associativity is stored as a decimal value. However,
in practice, it is encoded the AMD way and does not store the actual value.
Using the raw value leads to an incorrect CPU colors calculation, causing a
panic on KX-7000 (since the result is not a power of two) and incorrect CPU
colors values on other CPU models (e.g. as visible in `vmstat -s').
Decoding value using the AMD cache lookup table produces correct values in all
cases I have tested or verified using CPUID dumps available online.
Additionally, Zhaoxin and late VIA CPUs (CNQ and newer) prefer the Intel
`cpuid leaf 4' function to get cache parameters. Check whether cpuid_level
is equal to or greater than 4 to identify these CPUs and override cache values
(including L1) by calling cpu_dcp_cacheinfo(ci, 4). L3 cache information is
available only through this method.
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