[ELF] Pass SectionPiece by reference in getSectionPiece. NFC (#190110)
The generated assembly looks more optimized. In addition, this avoids
widened load, which would cause a TSan-detected data race with parallel
--gc-sections (#189321).
[JITLink] Remove unnecessary SymbolStringPtr copy. (#190101)
This was probably intended to be a `const SymbolStringPtr&` originally,
but if we were going to copy it anyway it's better to just take the
argument by value and std::move it.
[SelectionDAG] Use `KnownBits` to determine if an operand may be NaN. (#188606)
Given a bitcast into a fp type, use the known bits of the operand to
infer whether the resulting value can never be NaN.
[CIR][CIRGen] Support for section atttribute on cir.global (#188200)
Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/422
This PR implement support for `__attribute__((section("name")))` on
global variables in ClangIR, matching OGCG behavior.
[HLSL][SPIRV] Restore support for -g to generate NSDI (#190007)
The original attempt (#187051) produced a regression for
`intel-sycl-gpu` because `SPIRVEmitNonSemanticDI` will now self-activate
whenever `llvm.dbg.cu` is present. This removed the need for the
explicit `--spv-emit-nonsemantic-debug-info` flag.
The pass is now entered unconditionally for all SPIR-V targets, but
`NonSemantic.Shader.DebugInfo.100` requires the
`SPV_KHR_non_semantic_info`. Targets like `spirv64-intel` do not enable
that extension by default. When `checkSatisfiable()` ran on those
targets, it issued a fatal error rather than silently skipping.
Adds an early-out from `emitGlobalDI()`: if
`SPV_KHR_non_semantic_info` is not available for the current target, the
pass returns without emitting anything.
Merge the m68k trap code. Still a bit more tidying up to do here, but
this eliminates a significant chunk of code duplication.
Biggest change here is for Amiga, whose different-from-everyone-else's
68040 write-back code was voted off the island.
[RISCV] Move unpaired instruction back in RISCVLoadStoreOptimizer (#189912)
There are cases when the `Xqcilsm` vendor extension is enabled that we
are unable to pair non-adjacent load/store instructions. The
`RISCVLoadStoreOptimizer` moves the instruction adjacent to the other
before attempting to pair them but does not move them back when it
fails. This can sometimes prevent the generation of the `Xqcilsm`
load/store multiple instructions. This patch ensures that we move the
unpaired instruction back to it's original location.
17966 NCA & NL7S retirements forgot about AF_NCA and residual sockfs debris
Reviewed by: Robert Mustacchi <rm at fingolfin.org>
Reviewed by: Toomas Soome <tsoome at me.com>
Approved by: Gordon Ross <gordon.w.ross at gmail.com>
games/qtads [New port]: Interpreter for TADS games
QTads is a cross-platform, multimedia interpreter for TADS games. It is
fully compatible with HTML TADS, aka "Multimedia TADS". Both TADS
versions in use today (v2 and v3) are supported.
PR: 290244
games/frobtads: [New port] Tools for adventure games
FrobTADS is a full version of TADS. It includes everything you need for
playing and writing TADS games, including a text-only TADS interpreter
and the compilers for both TADS 2 and 3.
PR: 290209
[mlir] added a check in the walk to prevent catching a cos in a nested region (#190064)
The walk in SincosFusion may detect a cos within a nested region of the
sin block. This triggers an assertion in `isBeforeInBlock` later on.
Added a check within the walk so it filters operations in nested
regions, which are not in the same block and should not be fused anyway.
---------
Co-authored-by: Yebin Chon <ychon at nvidia.com>
