LLVM/project 4ee9dafllvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Use DecodeFilteredRegisterClass for DecodeGPRX1X5RegisterClass. (#223878)
DeltaFile
+3-11llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+3-111 files

OpenBSD/src UoKbIIksys/arch/amd64/include i82489reg.h

   Add a few x2apic MSRs to specialreg.h

   Add a few missing MSR defines to specialreg.h, will be needed soon
VersionDeltaFile
1.7+6-5sys/arch/amd64/include/i82489reg.h
+6-51 files

LLVM/project dec17c4flang/lib/Semantics expression.cpp

[flang][cuda] Fix matching distance for use_device and none (#223849)

https://docs.nvidia.com/hpc-sdk/compilers/cuda-fortran-prog-guide/#unified-data
the table set the matching distance for actual `use_device` and dummy
argument `none` to 1 but the implementation set it to 3.

@wangzpgi Was there a specific reason to set 3 instead of 1?
DeltaFile
+2-2flang/lib/Semantics/expression.cpp
+2-21 files

OpenBSD/src 7NOPpY5sys/arch/amd64/include i82489reg.h

   Add a few lapic register defines

   Adds a few register defines that will be needed soon. no code change.
VersionDeltaFile
1.6+8-1sys/arch/amd64/include/i82489reg.h
+8-11 files

LLVM/project 0454184llvm/test/Transforms/LoopVectorize uniform_across_vf_induction1.ll

Update uniform_across_vf_induction1.ll
DeltaFile
+74-90llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
+74-901 files

LLVM/project fa72130llvm/test/CodeGen/AMDGPU coexec-sched-ds-fifo.mir coexec-scheduler.ll

Fix lit

Change-Id: Id8c3f63acdce212f1030e5dfc7d9273c56945958
DeltaFile
+11-3llvm/test/CodeGen/AMDGPU/ds-latency-mode-flag.mir
+3-3llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
+0-4llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+2-2llvm/test/CodeGen/AMDGPU/coexec-sched-agpr-excess.mir
+1-1llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
+17-135 files

LLVM/project 4150e90llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Call DecodeGPRPairRegisterClass from DecodeGPRPairCRegisterClass. NFC (#223882)

GPRPairC is a subset of GPRPair. We just need to do the range check and
let DecodeGPRPairRegisterClass do the rest of the work.
DeltaFile
+1-8llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+1-81 files

LLVM/project 46f08d7llvm/lib/Target/RISCV RISCVInstrInfoZicfiss.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Remove Zicfiss DecoderNamespace. NFC (#223891)

This used to be needed to prioritize c.sspopchk and c.sspush over
c.mop.1 and c.mop.5, but those are treated as InstAliases now.
DeltaFile
+1-2llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+0-2llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+1-42 files

OpenBSD/src aKN4mxssys/kern subr_hibernate.c

   Make writes of the hibernate signature go through the I/O page of the
   piglet.  This fixes a potential issue on arm64 where the kernel might
   have been loaded into memory that isn't DMA reachable.  It will also
   help with implementing some future changes to make the side-effect free
   I/O functions support hardware without cache-coherent DMA or IOMMUs.

   ok deraadt@, mlarkin@
VersionDeltaFile
1.160+7-4sys/kern/subr_hibernate.c
+7-41 files

OpenBSD/src yhyeAm4sys/kern kern_exec.c exec_elf.c, sys/sys exec.h exec_elf.h

   Add a few more fields directly to exec_package so that the front-end
   and back-end of the ELF code doesn't need to communicate them via an
   malloc'd structure.  Much simpler.
   ok kettenis
VersionDeltaFile
1.206+15-29sys/kern/exec_elf.c
1.112+1-10sys/sys/exec_elf.h
1.273+2-8sys/kern/kern_exec.c
1.60+5-4sys/sys/exec.h
+23-514 files

OpenBSD/src LT0Ohbognu/usr.bin/binutils/gdb auxv.c, gnu/usr.bin/binutils/include/elf common.h

   Make our (legacy) gdb aware of the openbsd AUX values and what they
   mean (including the execpath variable)
   ok kettenis
VersionDeltaFile
1.14+2-0gnu/usr.bin/binutils/include/elf/common.h
1.4+2-0gnu/usr.bin/binutils/gdb/auxv.c
+4-02 files

LLVM/project 12992dcclang/docs ReleaseNotes.md, clang/lib/AST Decl.cpp

[clang] Fix handling of constexpr static data member template. (#220469)

[temp.expl.spec] says "An explicit specialization of a static data
member of a template or an explicit specialization of a static data
member template is a definition if the declaration includes an
initializer." The code did not match this rule for constexpr variables.
The check in question was only supposed to match the cases from
[depr.static.constexpr].

Fixes #219796
DeltaFile
+23-3clang/test/SemaTemplate/class-template-spec.cpp
+16-0clang/test/CodeGenCXX/cxx1z-inline-variables.cpp
+2-2clang/lib/AST/Decl.cpp
+3-0clang/docs/ReleaseNotes.md
+44-54 files

LLVM/project 8723e4allvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-mfma-interleave-gfx950.ll coexec-block-carried-latency.mir

[AMDGPU] Add block carried latency to CoExecSched (#192324)

This adds some rudimentary logic to check for load dependencies across
blocks. Since the scheduling algorithm is local scheduling per region,
we do not have about latencies carried from other blocks. Rather than
constructing a global DAG to accurately measure these latencies, this PR
uses a heuristic to estimate the incoming latency.

We limit our incoming dependencies to load instructions, as these are
expected to be the ones that cause problems. This uses the full latency
of the instruction as the incoming latency to cover. We check for any
use that occurred later in the def block - if we find such a use then we
do not have incoming latency as we have already waited for the load.
Using the incoming latency assumes that the load is the last instruction
in the block, and that the branch takes 0 cycles. Aside from not fully
understanding the dependencies of other blocks, a challenge in defining
a more accurate incoming latency is that it is possible that the block
with the load may be rescheduled.


    [2 lines not shown]
DeltaFile
+897-3llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+240-81llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+201-0llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
+0-36llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+26-5llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+5-5llvm/test/CodeGen/AMDGPU/coexec-mfma-interleave-gfx950.ll
+1,369-1303 files not shown
+1,372-1389 files

FreeBSD/ports ed8403fmath/py-SQNomad Makefile, math/py-SQNomad/files patch-setup.py

math/py-SQNomad: Unbreak
DeltaFile
+14-3math/py-SQNomad/files/patch-setup.py
+1-3math/py-SQNomad/Makefile
+15-62 files

FreeBSD/ports 945ff0baudio/lvtk Makefile, audio/lvtk/files patch-waflib_Context.py

audio/lvtk: Unbreak
DeltaFile
+25-0audio/lvtk/files/patch-waflib_Context.py
+1-4audio/lvtk/Makefile
+26-42 files

FreeBSD/ports 86b3f9baudio/lv2proc Makefile, audio/lv2proc/files patch-src_Makefile.in

audio/lv2proc: Unbreak
DeltaFile
+15-0audio/lv2proc/files/patch-src_Makefile.in
+0-2audio/lv2proc/Makefile
+15-22 files

OpenBSD/ports 764yOAUgraphics/openvdb Makefile

   Disable direct use of ccache.

   Found by tb@
VersionDeltaFile
1.14+2-0graphics/openvdb/Makefile
+2-01 files

LLVM/project b8373c3llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIInstrInfo.h

More documentation

Change-Id: I65ff1a1b605796d21a52766dcf04c64bc64aaa4e
DeltaFile
+21-6llvm/lib/Target/AMDGPU/SIInstrInfo.h
+1-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+22-72 files

LLVM/project cf656bdllvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU ds-latency-mode-flag.mir ds-latency-mode-branch-cost.mir

[AMDGPU] Add DSLatencyMode flag + attr to control LDS latency

Change-Id: Ia5fee7983adffdb837ba2e876a64d805263b60c3
DeltaFile
+119-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-default-scheduler.mir
+59-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+61-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
+53-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-branch-cost.mir
+29-0llvm/test/CodeGen/AMDGPU/ds-latency-mode-flag.mir
+10-13llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+331-158 files not shown
+373-2314 files

LLVM/project 0bf9309llvm/test/CodeGen/AMDGPU coexec-sched-flavor-classification.mir

Fix lit

Change-Id: Ia53e8f2317d4db93dcd87a616ae774137b8c0572
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
+1-11 files

OpenBSD/ports 0mu3gf4databases/arrow/cpp Makefile

   Disable direct use of ccache and sccache.

   Found by tb@
VersionDeltaFile
1.10+2-0databases/arrow/cpp/Makefile
+2-01 files

OpenBSD/src rAqgLPqusr.sbin/vmd mc146818.c

   vmd: Fix some broken interrupt behavior in mc146818 rtc

   Fix a few issues discovered during development of mp support.

   ok dv
VersionDeltaFile
1.33+22-9usr.sbin/vmd/mc146818.c
+22-91 files

FreeBSD/ports d7f694fdevel/opengrok Makefile

devel/opengrok: transfer maintanership

Siva Mahadevan <siva at FreeBSD.org> is the new MAINTAINER.
DeltaFile
+1-1devel/opengrok/Makefile
+1-11 files

NetBSD/src xQ6knI8sys/arch/mac68k/obio ascaudio.c

   Avoid use of lock before inited.

   Patch and testing by Ray Tran.
VersionDeltaFile
1.23+10-9sys/arch/mac68k/obio/ascaudio.c
+10-91 files

NetBSD/src PPhsLIDsys/arch/mac68k/obio ascaudio.c

   Respect maximum and minimum values when recording.

   Patch and testing by Ray Tran.
VersionDeltaFile
1.22+9-4sys/arch/mac68k/obio/ascaudio.c
+9-41 files

LLVM/project 423030dclang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp, clang/test/CIR/CodeGen var-arg-int128.c var-arg-direct-offset.cpp

[CIR] Address review on the x86-64 va_arg expansion

rewriteVAArg had grown to 254 lines, with the register arm alone taking
105 of them inside a nested builder callback.  The round-up, the overflow
arm, the register gate, the pair reassembly, the temp copy and the cursor
write-back are now named functions taking a small context struct, and the
48 and 176 register-file bounds sit in one place.

Four fixes come with it.

A va_arg of an empty record yielded a dummy value, which is an alloca and
a load of uninitialized memory.  It now yields the poison the file already
hands to an ignored block argument.

The register slot size came from the integer register count while the
address it described came from whichever area the vector count selected,
so the two disagreed for a fetch needing one register of each class.  Only
one class is ever in play, since a fetch needing both is a coerced pair
that takes the reassembly path, and an assert now says so.  Reachable

    [18 lines not shown]
DeltaFile
+303-194clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+85-6clang/test/CIR/CodeGen/var-arg-aggregate.c
+11-3clang/test/CIR/CodeGen/var-arg-empty.c
+3-3clang/test/CIR/CodeGen/var-arg-direct-offset.cpp
+1-1clang/test/CIR/CodeGen/var-arg-int128.c
+403-2075 files

NetBSD/src 5YnnW0lsys/arch/mac68k/obio ascaudio.c

   Fix typo for building ascaudio(4) as a module.

   Patch and testing by Ray Tran.
VersionDeltaFile
1.21+7-7sys/arch/mac68k/obio/ascaudio.c
+7-71 files

NetBSD/src 4qa7pXIsys/arch/mac68k/obio ascaudio.c

   Honor playback block size within resonable limits.

   Patch and testing by Ray Tran.
VersionDeltaFile
1.20+14-7sys/arch/mac68k/obio/ascaudio.c
+14-71 files

NetBSD/src gz1g1bnsys/arch/mac68k/obio ascaudio.c

   Return early if aux.interrupts.

   Patch and testing by Ray Tran.
VersionDeltaFile
1.19+5-2sys/arch/mac68k/obio/ascaudio.c
+5-21 files

LLVM/project aac546bllvm/cmake/modules AddLLVM.cmake

[CMake] Clean up factored lit dependency names

Replace the opaque SHA1-based stamp and anchor names with readable names
based on the lit project. Document why the symbolic outputs and internal
anchor target are needed.

Warn once when the active project minimum reaches CMake 3.27, making the
compatibility fallback obsolete.
DeltaFile
+17-5llvm/cmake/modules/AddLLVM.cmake
+17-51 files