FreeBSD/doc 3333373website/archetypes/release hardware.adoc

hardware: Add some 3G cellular drivers...
DeltaFile
+4-0website/archetypes/release/hardware.adoc
+4-01 files

OpenBSD/ports 0fM4Blcx11/gnome/contacts Makefile, x11/gnome/shell Makefile

   multimedia/pipewire/pipewire -> multimedia/pipewire/pipewire,-gst
VersionDeltaFile
1.310+2-2x11/gnome/shell/Makefile
1.116+2-2x11/gnome/contacts/Makefile
1.5+2-1x11/gnome/snapshot/Makefile
+6-53 files

LLVM/project e7302d9llvm/include/llvm/Analysis TargetTransformInfo.h, llvm/lib/Analysis TargetTransformInfo.cpp

[SLP] Reland: More accurately cost RISCV scalar splats (#224766)

Originally #213104, reverted due to assertion failure in cases of
reordered gather nodes.

Backends may have a fast path for splatting scalar operands (i.e. rather
than generating the splat vector, the vector instruction may be able to
take a scalar operand), for example RISCV `vfoo.vx` instructions. Pass a
hint to the TTI when costing the insert/shuffle sequence in such cases.

Fixes #212413.

Assisted By: Codex
DeltaFile
+131-55llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+67-0llvm/test/Transforms/SLPVectorizer/RISCV/reordered-gather.ll
+42-6llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+11-31llvm/test/Transforms/SLPVectorizer/RISCV/check-node-without-vector-user.ll
+29-2llvm/include/llvm/Analysis/TargetTransformInfo.h
+18-3llvm/lib/Analysis/TargetTransformInfo.cpp
+298-9723 files not shown
+401-17229 files

OpenBSD/ports nw2zzmMmultimedia/pipewire/pipewire Makefile, multimedia/pipewire/pipewire/pkg PLIST-main PLIST-gst

   Split GStreamer elements into its own subpackage.
VersionDeltaFile
1.70+12-6multimedia/pipewire/pipewire/Makefile
1.3+1-1multimedia/pipewire/pipewire/pkg/PLIST-gst
1.3+1-1multimedia/pipewire/pipewire/pkg/DESCR-gst
1.21+0-1multimedia/pipewire/pipewire/pkg/PLIST-main
+14-94 files

OpenBSD/ports aTaC1M9net/bitmagnet Makefile

   pass version through ldflags for the webui to show instead of "unknown"
VersionDeltaFile
1.2+2-0net/bitmagnet/Makefile
+2-01 files

LLVM/project 06c7e8dllvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

[SelectionDAG] Simplify computeKnownBits for EXTRACT_ELEMENT using KnownBits::extractBits. NFC (#225168)
DeltaFile
+1-6llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+1-61 files

FreeBSD/src b952821share/man/man4 ulpt.4

ulpt.4: Canonicalize SYNOPSIS, tag SPDX

MFC after:      3 days
DeltaFile
+6-11share/man/man4/ulpt.4
+6-111 files

FreeBSD/src 2784767share/man/man4 umct.4

umct.4: Canonicalize SYNOPSIS, HARDWARE, tag SPDX

MFC after:      3 days
DeltaFile
+8-14share/man/man4/umct.4
+8-141 files

FreeBSD/src 71a0ea7share/man/man4 umcs.4

umcs.4: Describe better, canonicalize SYNOPSIS

+ tag SPDX
+ improve apropos and hardware notes context
+ canonicalize SYNOPSIS

MFC after:      3 days
DeltaFile
+13-18share/man/man4/umcs.4
+13-181 files

FreeBSD/src 6204c60share/man/man4 uled.4

uled.4: Canonicalize SYNOPSIS, tag SPDX

MFC after:      3 days
DeltaFile
+6-11share/man/man4/uled.4
+6-111 files

LLVM/project 4a49d09llvm/lib/DebugInfo/DWARF DWARFDebugLine.cpp, llvm/unittests/DebugInfo/DWARF DWARFDebugLineTest.cpp

[DebugInfo] Fix overflow in DWARFDebugLine::SectionParser (#224770)

Adding a DWARF64 unit length can overflow and wrap back into the
section, causing an infinite loop. Saturate the addition so an
overflowing offset fails the bounds check.

rdar://186810393
DeltaFile
+20-0llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
+4-1llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
+24-12 files

LLVM/project fbbf5d2llvm/lib/Target/NVPTX NVPTXSubtarget.h NVPTXISelDAGToDAG.cpp, llvm/test/CodeGen/NVPTX volatile-local.ll

[NVPTX] Preserve volatile on atomic local loads and stores (#224719)

Local loads and stores discard atomic ordering during instruction
selection, but volatile accesses with acquire, release, or seq_cst
ordering also lose the volatile qualifier. Preserve volatile for all
valid load/store orderings when local volatile instructions are
supported. Follow up to #217764.
DeltaFile
+117-0llvm/test/CodeGen/NVPTX/volatile-local.ll
+14-15llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+1-0llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+132-153 files

LLVM/project 9906c58clang/lib/StaticAnalyzer/Checkers/WebKit RawPtrRefCallArgsChecker.cpp RawPtrRefLocalVarsChecker.cpp, clang/test/Analysis/Checkers/WebKit uncounted-local-vars.cpp

[WebKit Checkers] Trace through temporaries in tryToFindPtrOrigin (#224877)

RefPtr checking skips temporaries, reporting a path through any
temporary as unsafe. This is mostly correct, but not always. For
example, the following is a false positive:

    // makeKey() returns a temporary
    RefCountable* p = condition(makeKey()) ? guardian.ptr() : nullptr;

In the upcoming Borrow checker, it's even more important to trace
through temporaries because not tracing an expression can drop a
`lifetimebound` link, resulting in false **negatives**.

This patch adds tracing through temporaries. The logic is:

* In function call arguments, temporaries are lifetime safe because the
full expression does not end until the call returns

* In ranged for loops, temporaries are lifetime safe because lifetime

    [4 lines not shown]
DeltaFile
+82-32clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
+24-0clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp
+9-4clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h
+6-2clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
+4-1clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
+125-395 files

LLVM/project 8e63511clang/lib/Driver/ToolChains FreeBSD.cpp, clang/test/Driver fsanitize.c

[clang][FreeBSD] Enable KASAN and KMSAN for riscv64 (#202288)

enables KASAN and KMSAN for the riscv64 freebsd target in the Clang
driver.

The corresponding FreeBSD kernel runtime support for riscv64 KASAN is
currently under active review.

Depends on: https://reviews.freebsd.org/D57381

Co-authored-by: aokblast <aokblast at FreeBSD.org>
DeltaFile
+2-1clang/lib/Driver/ToolChains/FreeBSD.cpp
+2-0clang/test/Driver/fsanitize.c
+4-12 files

LLVM/project 4efc900llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-select.ll promote-alloca-homogeneous-struct.ll

Reland "[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors" (#221058)

This relands #217055

The original commit revealed a latent issue in eliminateFrameIndex in
SIRegisterInfo where SCC can be clobbered before reading it on
gfx900/gfx90a. This change itself has no known issues.
DeltaFile
+152-0llvm/test/CodeGen/AMDGPU/promote-alloca-homogeneous-struct.ll
+23-6llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+6-1llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
+181-73 files

LLVM/project 8fcba44llvm/lib/Target/AMDGPU SIRegisterInfo.cpp

[AMDGPU] Update based on review feedback

Replace the lambda with the check inlined at both sites, and report a fatal
error when neither a free SGPR nor FrameReg is available, rather than
silently falling back to the spilling scavenge.
DeltaFile
+24-19llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+24-191 files

LLVM/project 895a2d3llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir

[AMDGPU] Use the scavenger to test whether SCC is live after MI

The register scavenger is stepped backwards to the liveness state
immediately after MI, so RS->isRegUsed(SCC) already answers "is SCC live
after MI" directly. Replace the hand-rolled test with that query.
DeltaFile
+5-6llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir
+3-3llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+8-92 files

LLVM/project f4edcdallvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir

[AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering

When SCC is live into a scalar frame index user, the scaling path avoids
SALU ops that write SCC by computing the address in a VGPR and reading it
back with V_READFIRSTLANE_B32. If the destination of that readfirstlane is
scavenged with spilling allowed, an AMDGPU SGPR spill writes inactive
lanes, so it flips EXEC with S_NOT_B64 and clobbers SCC. Instead, scavenge
that register with AllowSpill=false.
DeltaFile
+81-45llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir
+29-10llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+110-552 files

LLVM/project ca063cdllvm/test/CodeGen/AMDGPU sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir

[NFC][AMDGPU] Add tests for SCC live into a frame index user

Pre-commit tests for the case where SCC is live into a frame index user and
no SGPR is free to hold the V_READFIRSTLANE_B32 result. Scavenging one
emergency-spills an SGPR, and an SGPR spill flips EXEC with S_NOT_B64, so the
EXEC flips land between the S_CMP_EQ_U32 that defines SCC and the read of SCC
that follows, clobbering it in between.
DeltaFile
+153-0llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir
+153-01 files

LLVM/project 6611de6llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-scalar-scc-clobber.mir

[AMDGPU] Prevent SCC clobber in frame index lowering in scaling path

eliminateFrameIndex has two lowering strategies, but only one has the
proper handling for checking SCC-liveness to prevent clobbering. Unify
them with a helper function to ensure both paths handle the same
DeltaFile
+343-4llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
+9-5llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+352-92 files

LLVM/project 7bed9e9clang/test/CIR/CodeGen union.c paren-list-agg-init.cpp

[CIR] Regenerate CHECK lines for two callconv opt-out tests

Neither `union.c` nor `paren-list-agg-init.cpp` is blocked by the
calling convention lowering pass any more, and both compile clean with
it running.  Remove the `-fno-clangir-call-conv-lowering` opt-out and
update their CHECK lines.  The coerced parameters and returns they now
pin match classic.

The bodies still differ, since CIR round-trips the record through a
fresh coerce slot, so those fragments move to the `LLVMCIR` and `OGCG`
prefixes the file already declares.  Four `define` lines in
`paren-list-agg-init.cpp` wildcarded their return type and now pin it.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+45-18clang/test/CIR/CodeGen/paren-list-agg-init.cpp
+35-16clang/test/CIR/CodeGen/union.c
+80-342 files

LLVM/project ae22af2llvm/lib/CodeGen TargetPassConfig.cpp, llvm/lib/Passes CodeGenPassBuilder.cpp

WebAssembly: Move target EH passes into backend (#225172)

Currently the wasm-specific EH lowering passes are added in the
generic pass configs, driven by the TargetOptions ExceptionModel.
As preparation for driving this process off the IR flag, move these
pass runs into the target. There should be no change in the relative
pass ordering.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+4-0llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
+3-0llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+0-2llvm/lib/Passes/CodeGenPassBuilder.cpp
+0-1llvm/lib/CodeGen/TargetPassConfig.cpp
+7-34 files

LLVM/project 0b04288

[clang][CodeGen] Compute the pointer-overflow offset from the index list (#225139)

Follow up to #223446. EmitGEPOffsetInBytes recreated the offset by
walking the GEP value that EmitCheckedInBoundsGEP had just created. That
required a separate path for the case where CreateGEP folded the result,
because a folded GEP need not be a GEP at all: `gep(null, 1)` becomes
`inttoptr(1)`, and `gep(@g, 0)` becomes `@g`.

Pass ElemTy and IdxList instead and walk those directly. This removes
the constant path, the cast to GEPOperator, and two asserts that
restated the caller's own behaviour.

This is not quite NFC. The constant path reported OffsetOverflows as
false unconditionally, so a constant GEP whose byte offset wrapped to
exactly zero satisfied the TotalOffset == Zero early return and emitted
no check. The unified path computes the flag, so such a GEP now emits
one. It is provably valid, since TotalOffset == 0 makes the computed
address equal the base, so this is extra IR at -O0 rather than a change
in behaviour.

    [5 lines not shown]
DeltaFile
+0-00 files

FreeBSD/ports 40f6ee7devel/immanent-checker Makefile distinfo

devel/immanent-checker: Upgrade from 0.42 to 0.50

  Add classification support for each check, which improves the performance fixing of checks massively

Sponsored by:   OTTRIA
DeltaFile
+7-7devel/immanent-checker/distinfo
+1-1devel/immanent-checker/Makefile
+8-82 files

LLVM/project b09f78dllvm/lib/CodeGen WasmEHPrepare.cpp

[WebAssembly] Remove an unnecessary variable (NFC) (#224962)

That `CPI` had a use when first written in
https://github.com/llvm/llvm-project/commit/99d60e0dabcf20f4db683da83cde905b7a1373de
but after
https://github.com/llvm/llvm-project/commit/445f4e74841e87da06743a4c126b09c9b9b05124
it's not necessary to cast it anymore.
DeltaFile
+1-2llvm/lib/CodeGen/WasmEHPrepare.cpp
+1-21 files

LLVM/project 1492dbcclang/lib/CodeGen CGExprScalar.cpp, clang/test/CodeGen ubsan-pointer-overflow-constant-fold.c

[clang][CodeGen] Compute the pointer-overflow offset from the index list (#225139)

Follow up to #223446. EmitGEPOffsetInBytes recreated the offset by
walking the GEP value that EmitCheckedInBoundsGEP had just created. That
required a separate path for the case where CreateGEP folded the result,
because a folded GEP need not be a GEP at all: `gep(null, 1)` becomes
`inttoptr(1)`, and `gep(@g, 0)` becomes `@g`.

Pass ElemTy and IdxList instead and walk those directly. This removes
the constant path, the cast to GEPOperator, and two asserts that
restated the caller's own behaviour.

This is not quite NFC. The constant path reported OffsetOverflows as
false unconditionally, so a constant GEP whose byte offset wrapped to
exactly zero satisfied the TotalOffset == Zero early return and emitted
no check. The unified path computes the flag, so such a GEP now emits
one. It is provably valid, since TotalOffset == 0 makes the computed
address equal the base, so this is extra IR at -O0 rather than a change
in behaviour.

    [5 lines not shown]
DeltaFile
+11-25clang/lib/CodeGen/CGExprScalar.cpp
+34-0clang/test/CodeGen/ubsan-pointer-overflow-constant-fold.c
+45-252 files

LLVM/project e7b5aa9mlir/lib/Dialect/Linalg/Transforms Vectorization.cpp

[mlir][linalg] Fix exponential walk of tensor.extract indices (#222319)

`isLoopInvariantIdx` showed exponential runtime behavior. Replaced with
a worklist and a visited set.

Encountered in iree-org/iree#24886.

Assisted-by: Claude

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+42-28mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
+42-281 files

HardenedBSD/src 19adf5bshare/man/man4 ufshci.4 uhso.4, sys/amd64/amd64 sigtramp.S

Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/cross-dso-cfi
DeltaFile
+94-26sys/arm64/iommu/smmu.c
+86-0tests/sys/netpfil/pf/pfsync.sh
+62-6sys/cddl/dev/dtrace/aarch64/dtrace_asm.S
+33-22share/man/man4/uhso.4
+18-28share/man/man4/ufshci.4
+27-17sys/amd64/amd64/sigtramp.S
+320-9928 files not shown
+552-23534 files

HardenedBSD/src b335505share/man/man4 ufshci.4 uhso.4, sys/amd64/amd64 sigtramp.S

Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/pledge
DeltaFile
+94-26sys/arm64/iommu/smmu.c
+86-0tests/sys/netpfil/pf/pfsync.sh
+62-6sys/cddl/dev/dtrace/aarch64/dtrace_asm.S
+33-22share/man/man4/uhso.4
+18-28share/man/man4/ufshci.4
+27-17sys/amd64/amd64/sigtramp.S
+320-9928 files not shown
+552-23534 files

HardenedBSD/src 610f4basys/kern vfs_lookup.c, usr.sbin/nfsuserd nfsuserd.c

Merge remote-tracking branch 'rad/hardened/15-stable/main' into hardened/15-stable/pledge
DeltaFile
+8-4sys/kern/vfs_lookup.c
+4-2usr.sbin/nfsuserd/nfsuserd.c
+12-62 files