FreeBSD/ports 5fc8b8cdevel/py-uv Makefile distinfo, devel/py-uv-build distinfo

devel/{py-,}uv{-build}: Update to 0.12.15

PR:             298441
Approved by:    yuri (maintainer)
DeltaFile
+65-69devel/uv/distinfo
+31-33devel/uv/Makefile.crates
+4-4devel/py-uv/files/patch-pyproject.toml
+3-3devel/py-uv/distinfo
+3-3devel/py-uv-build/distinfo
+2-2devel/py-uv/Makefile
+108-1142 files not shown
+110-1178 files

LLVM/project 83066e0llvm/docs NVPTXUsage.md, llvm/include/llvm/IR IntrinsicsNVVM.td

[LLVM][NVPTX] Add async bulk copy global to shared extensions (#222323)

This change adds following things to bulk copy intrinsics.
1. Relaxed memory ordering semantics with a scope argument.
2. Data-validity reporting patterns (introduced in Rubin).
3. 32-bit multicast mask for global to shared::cluster variants
(introduced in Rubin).
4. Ignore out of bound checks for global to shared::cta variants.

Note: MLIR lowering is updated to emit the new intrinsic signatures.
Support for the new features in MLIR will be done in a separate change.
DeltaFile
+166-71llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+169-49llvm/docs/NVPTXUsage.md
+108-108mlir/test/Target/LLVMIR/nvvm/tma_load_cluster_im2col.mlir
+72-72mlir/test/Target/LLVMIR/nvvm/tma_load_cluster_tile.mlir
+112-10llvm/lib/IR/AutoUpgrade.cpp
+73-19llvm/include/llvm/IR/IntrinsicsNVVM.td
+700-32923 files not shown
+1,269-41329 files

LLVM/project c7ddefdllvm/lib/Target/RISCV RISCVFeatures.td, llvm/test/MC/RISCV attribute-arch.s

[MC][RISCV] Make Zve32x a dependency of Zvabd (#223901)

The Zvabd specification defines Zve32x as a dependency. This commit
fixes the dependency problem in MC's implementation.

See:
https://github.com/riscv/integer-vector-absolute-difference/blob/0092c8451bb24b957d8358f261c0535ece88defb/src/unpriv/zvabd.adoc#L26
DeltaFile
+2-1llvm/lib/Target/RISCV/RISCVFeatures.td
+3-0llvm/test/MC/RISCV/attribute-arch.s
+5-12 files

LLVM/project 00fbc3fllvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

Precommit test
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163-01 files

LLVM/project 2443554llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Remove (X && Y) | (X && !Y) -> X combine. NFC

We have smaller combines that can take care of this now that we process recipes in a worklist
DeltaFile
+1-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-81 files

LLVM/project 2595cb9llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]
DeltaFile
+26-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+5-7llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+42-193 files

LLVM/project 6c1d20cllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize iv_outside_user.ll dont-fold-tail-for-divisible-TC.ll

[VPlan] Process combineRecipes in a worklist (#213899)

This brings combineRecipes further in line with InstCombine, and asides
from unlocking more simplifications it also helps avoid test churn
whenever passes are moved around combineRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification
order as before.
DeltaFile
+74-90llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
+57-0llvm/test/Transforms/LoopVectorize/blend-i1.ll
+25-13llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-8llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+1-2llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+161-1135 files

LLVM/project 8a512d6clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp

[CIR][ABI] Honor abi::ArgInfo::CanBeFlattened in the call-conv lowering
DeltaFile
+8-4clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+8-41 files

OpenBSD/src mWS8uHwusr.bin/ssh misc-agent.c

   leaks on error paths; spotted by Coverity CID 913598
VersionDeltaFile
1.9+3-3usr.bin/ssh/misc-agent.c
+3-31 files

OpenBSD/src cLtpsMDusr.bin/ssh channels.c

   fix inverted logic that could cause a memleak;
   spotted en passant by Coverity CID 913599
VersionDeltaFile
1.469+2-2usr.bin/ssh/channels.c
+2-21 files

LLVM/project 8b66604llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp, llvm/test/MC/RISCV zicfiss-valid.s

[RISCV] Remap mop.rr.7 and mop.r.28 to sspush/sspopchk/ssrdp in the assembler. (#223894)

This makes llvm-mc output match llvm-objdump. And is more consistent
with the InstAliases we use c.mop.
DeltaFile
+30-0llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+9-15llvm/test/MC/RISCV/zicfiss-valid.s
+39-152 files

OpenBSD/src nc7LWqaregress/usr.bin/ssh/unittests/authopt tests.c

   simpler
VersionDeltaFile
1.7+4-3regress/usr.bin/ssh/unittests/authopt/tests.c
+4-31 files

OpenBSD/src kVcQ7PUregress/usr.bin/ssh/unittests/authopt tests.c

   correctly check sshauthopt->restricted merging
VersionDeltaFile
1.6+22-21regress/usr.bin/ssh/unittests/authopt/tests.c
+22-211 files

LLVM/project 262cf39llvm/lib/MC/MCParser MCAsmParser.cpp, llvm/test/MC/AsmParser macro-max-depth.s

[MC] Increase asm-macro-max-nesting-depth default to 100 (#218455)

GNU as accepts assembly we reject at the current default of 20, e.g.
glibc's
`sysdeps/unix/sysv/linux/alpha/rt_sigaction.S`, which nests 31 deep.
Raise the
default to 100, matching GNU as.

Assisted-by: Claude Code
DeltaFile
+13-13llvm/test/MC/AsmParser/macro-max-depth.s
+1-1llvm/lib/MC/MCParser/MCAsmParser.cpp
+14-142 files

LLVM/project 9302119mlir/python/mlir/dialects/linalg __init__.py, mlir/test/python/dialects/linalg ops.py

[mlir][python] Register linalg.ElementwiseOp wrapper as op view

The hand-written ElementwiseOp wrapper subclassed the generated OpView but
was not registered in the op-view registry, so ops reconstructed from the
registry (e.g. Operation.opview) were instances of the generated base class
rather than the publicly exported subclass. This made
isinstance(op.opview, linalg.ElementwiseOp) and match/case dispatch return
False for real linalg.elementwise ops.

Register the wrapper with replace=True (as pdl.py does) so the exported
class is the one the registry instantiates.

Fixes #223673
DeltaFile
+21-0mlir/test/python/dialects/linalg/ops.py
+3-4mlir/python/mlir/dialects/linalg/__init__.py
+24-42 files

LLVM/project 2d7343amlir/test/python/dialects/linalg ops.py

Remove comment per review
DeltaFile
+0-2mlir/test/python/dialects/linalg/ops.py
+0-21 files

FreeBSD/ports 5929ae6misc/py-litellm Makefile Makefile.crates, misc/py-litellm/files patch-pyproject.toml

misc/py-litellm: Update to 1.101.0

Changelog: https://github.com/BerriAI/litellm/releases/tag/v1.101.0

Reported by:    portscout
DeltaFile
+45-13misc/py-litellm/distinfo
+21-5misc/py-litellm/Makefile.crates
+6-5misc/py-litellm/Makefile
+4-4misc/py-litellm/files/patch-pyproject.toml
+76-274 files

NetBSD/pkgsrc tn293LBx11/xfd distinfo, x11/xfd/patches patch-meson.build

   xfd: use upstream variant of patch
VersionDeltaFile
1.2+18-15x11/xfd/patches/patch-meson.build
1.11+2-2x11/xfd/distinfo
+20-172 files

FreeNAS/freenas 98e3998

Empty commit to create PR on github.

You should reset it
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+0-00 files

FreeNAS/freenas 4bafaa9

Empty commit to create PR on github.

You should reset it
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+0-00 files

FreeNAS/freenas 0a5a6e5src/middlewared/middlewared/pytest/unit/alert test_applicability_engine.py, src/middlewared/middlewared/pytest/unit/plugins test_failover.py

NAS-143780 / 27.0.0-BETA.1 / Model HA as a license feature instead of a license type (#19732)

This commit adds changes to follow upstream collapsing enterprise_single
and enterprise_ha into a single enterprise type, with HA moving into the
features dict as its own key. The HA entitlement becomes an ordinary
matrix vector keyed on that feature, so LicenseTypeRule has nothing left
to decide and goes away with it.

Legacy blobs predate the feature vocabulary, so the shim injects the HA
key when the blob names a second controller serial. That is the same
condition which used to pick the enterprise_ha type, which is what keeps
every fielded legacy pair licensed for failover.
DeltaFile
+22-16src/middlewared/middlewared/pytest/unit/utils/test_entitlements.py
+34-3src/middlewared/middlewared/pytest/unit/utils/test_license_legacy_utils.py
+3-25src/middlewared/middlewared/utils/entitlements/engine.py
+12-8src/middlewared/middlewared/pytest/unit/plugins/test_failover.py
+2-13src/middlewared/middlewared/utils/entitlements/policy.py
+7-8src/middlewared/middlewared/pytest/unit/alert/test_applicability_engine.py
+80-7319 files not shown
+120-12225 files

OpenBSD/src 1Lbye1hsys/kern vfs_lookup.c

   knf
VersionDeltaFile
1.94+1-3sys/kern/vfs_lookup.c
+1-31 files

LLVM/project c20428cmlir/lib/Dialect/LLVMIR/IR NVVMDialect.cpp, mlir/test/Target/LLVMIR/nvvm mbar_arrive_drop.mlir

[MLIR][NVVM] Fix the lowering of legacy mbar.arrive_drop (#222916)

`nvvm.mbarrier.arrive_drop` fails to compile for sm_80:

LLVM ERROR: Cannot select: intrinsic
%llvm.nvvm.mbarrier.arrive.drop.scope.cta.space.cta

The op always lowers to the `scope.*.space.*` intrinsics, which need
sm_90. The legacy `llvm.nvvm.mbarrier.arrive.drop{,.shared}` intrinsics
work from sm_80 but are never used.

This uses the legacy intrinsic for the basic case only, space=cta,
scope=cta, no relaxed, no explicit count, the same fix as #172476 for
`mbarrier.arrive`. The count forms need sm_90, so they are unchanged.

Assisted-by: Claude
DeltaFile
+15-2mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir
+8-2mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+23-42 files

OpenBSD/src VBC6C8jusr.sbin/rarpd rarpd.c

   NULL not 0
VersionDeltaFile
1.81+2-2usr.sbin/rarpd/rarpd.c
+2-21 files

LLVM/project 4ee9dafllvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Use DecodeFilteredRegisterClass for DecodeGPRX1X5RegisterClass. (#223878)
DeltaFile
+3-11llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+3-111 files

OpenBSD/src zfeDwUousr.bin/ssh channels.c

   Add missing semicolon after return.  CID 913599, ok deraadt@
VersionDeltaFile
1.468+2-2usr.bin/ssh/channels.c
+2-21 files

OpenBSD/src UoKbIIksys/arch/amd64/include i82489reg.h

   Add a few x2apic MSRs to specialreg.h

   Add a few missing MSR defines to specialreg.h, will be needed soon
VersionDeltaFile
1.7+6-5sys/arch/amd64/include/i82489reg.h
+6-51 files

LLVM/project dec17c4flang/lib/Semantics expression.cpp

[flang][cuda] Fix matching distance for use_device and none (#223849)

https://docs.nvidia.com/hpc-sdk/compilers/cuda-fortran-prog-guide/#unified-data
the table set the matching distance for actual `use_device` and dummy
argument `none` to 1 but the implementation set it to 3.

@wangzpgi Was there a specific reason to set 3 instead of 1?
DeltaFile
+2-2flang/lib/Semantics/expression.cpp
+2-21 files

OpenBSD/src 7NOPpY5sys/arch/amd64/include i82489reg.h

   Add a few lapic register defines

   Adds a few register defines that will be needed soon. no code change.
VersionDeltaFile
1.6+8-1sys/arch/amd64/include/i82489reg.h
+8-11 files

LLVM/project 0454184llvm/test/Transforms/LoopVectorize uniform_across_vf_induction1.ll

Update uniform_across_vf_induction1.ll
DeltaFile
+74-90llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
+74-901 files