OPNSense/core c5a438dsrc/etc/inc interfaces.inc

interfaces: run vlan configuration when bridge parent exists to fix bridge dependent vlan parents.
DeltaFile
+9-1src/etc/inc/interfaces.inc
+9-11 files

LLVM/project b8eebf2libcxx/include/__configuration availability.h

[libc++][NFC] Re-order availability mapping to `_LIBCPP_INTRODUCED_IN_LLVM_{N}` (#210694)

Noticed that the new additions (from 16f692338cf and 8a531c3608c) were placed
rather randomly. Put the mapping back to reverse chronological order, see 
783fd2f9d.
DeltaFile
+12-12libcxx/include/__configuration/availability.h
+12-121 files

LLVM/project ad3f09cclang/include/clang/Analysis/Analyses/LifetimeSafety Utils.h, clang/lib/Analysis LiveVariables.cpp

[ADT] Add single-pass merge for ImmutableSet/ImmutableMap (#209807)

The immutable-set/map dataflow joins merged two containers by inserting
the
elements of one into the other one at a time, costing O(|B| * log|A|)
and
re-copying shared spine nodes on every insert.

Add a single-pass, structure-sharing tree merge on ImutAVLFactory
(mergeTrees), exposed as ImmutableSet::Factory::unionSets and
ImmutableMap::Factory::mergeWith. It recurses over the larger operand
and
splits the smaller at each key, returning non-overlapping subtrees
unchanged,
so each spine node is copied at most once: O(|B| * log(|A|/|B| + 1)).

Two flags tune it for the different joins:
* KeepUnmatched - keep keys unique to one side (set union / a lattice
join

    [37 lines not shown]
DeltaFile
+379-0llvm/benchmarks/ImmutableMergeBM.cpp
+167-0llvm/include/llvm/ADT/ImmutableSet.h
+82-0llvm/unittests/ADT/ImmutableMapTest.cpp
+54-0llvm/unittests/ADT/ImmutableSetTest.cpp
+7-43clang/lib/Analysis/LiveVariables.cpp
+24-24clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
+713-672 files not shown
+735-678 files

FreeNAS/freenas c6da844src/middlewared/middlewared/plugins mail.py

Fix mail.send omitting Cc recipients from the SMTP envelope
DeltaFile
+17-3src/middlewared/middlewared/plugins/mail.py
+17-31 files

pkgng/pkgng 0bc2b7ftests/frontend repo.sh

tests: use bsdtar instead of tar in repo tests

GNU tar does not behave 100% like bsdtar, Use bsdtar explicitly
DeltaFile
+4-4tests/frontend/repo.sh
+4-41 files

LLVM/project a274aedllvm/docs LangRef.rst LangRef.md, llvm/lib/Support UnicodeNameToCodepointGenerated.cpp

remove static before constexpr

Created using spr 1.3.8-wip
DeltaFile
+24,053-23,916llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+20,246-21,270llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+0-33,180llvm/docs/LangRef.rst
+30,363-0llvm/docs/LangRef.md
+23,904-12llvm/test/CodeGen/RISCV/clmul.ll
+11,567-11,387llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+110,133-89,76515,675 files not shown
+805,268-475,99215,681 files

LLVM/project 90bb7c4llvm/lib/Target/AMDGPU GCNVOPDUtils.cpp VOP3PInstructions.td, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

AMDGPU: Reland: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3

For V_DOT2_F32_F16 and V_DOT2_F32_BF16 add their VOPDName and mark
them with usesCustomInserter which will be used to add pre-RA register
allocation hints to preferably assign dst and src2 to the same physical
register. When the hint is satisfied, canMapVOP3PToVOPD recognises the
instruction as eligible for VOPD pairing by checking if it is VOP2 like:
dst==src2, no source modifiers, no clamp, and src1 is a register.
Mark both instructions as commutable to allow a literal in src1 to be
moved to src0, since VOPD only permits a literal in src0.

Original patch had a bug where it did not check if physical src
registers match register class of appropriate operand in fullVOPD
instructions, check is now done via isValidVOPDSrc.
DeltaFile
+442-520llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+163-69llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+34-1llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+8-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+8-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+661-5951 files not shown
+663-5977 files

LLVM/project 115502fllvm/lib/Target/AMDGPU GCNVOPDUtils.cpp

AMDGPU: Validate VOPD/VOPD3 physical source registers against operand RC

Replace isVGPR checks with isValidVOPDSrc that validates physical source
registers against the actual combined VOPD/VOPD3 instruction's operand
register classes. Now we also validate operands for VOPD instructions.
DeltaFile
+56-10llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+56-101 files

LLVM/project df4bb1flibcxx/test CMakeLists.txt, libcxx/test/configs cmake-bridge.cfg.in harness-configuration.cfg.in

[libc++] Compose the test suite Lit site config from harness and installation substitutions (#209638)

This patch restructures how libc++'s Lit site config is generated.
Instead of relying on the user-selected configuration file to include
the CMake bridge, it composes a site configuration from multiple
independent bits.

Importantly, it splits substitutions that pertain to the harness setup
(e.g. where to find Python) and substitutions that pertain to libc++
itself (e.g. the path to libc++ headers). This split and the top-level
composition of a site config file are incremental steps towards
decoupling the test suite from libc++'s own build.
DeltaFile
+0-37libcxx/test/configs/cmake-bridge.cfg.in
+30-0libcxx/test/configs/harness-configuration.cfg.in
+19-4libcxx/test/CMakeLists.txt
+13-0libcxx/test/configs/libcxx-substitutions.cfg.in
+11-0libcxx/test/configs/lit.site.cfg.in
+0-2libcxx/test/configs/ibm-libc++-shared.cfg.in
+73-4316 files not shown
+73-7522 files

LLVM/project 7f49d95libcxx/include system_error

[libc++][NFC] Fix synopsis comment for error_condition::message() (#210724)

The method was marked as noexcept in the synopsis, but it's neither
marked noexcept in the spec nor in our implementation.
DeltaFile
+1-1libcxx/include/system_error
+1-11 files

LLVM/project f8e2588libcxx/test/benchmarks/containers string.bench.cpp

[libc++] Include sizes in string benchmark names (#210795)

Otherwise we'd have duplicate benchmark names.
DeltaFile
+40-20libcxx/test/benchmarks/containers/string.bench.cpp
+40-201 files

FreeNAS/freenas 2a65180src/middlewared/middlewared/plugins/mail send.py send_queue.py, src/middlewared/middlewared/test/integration/assets mail.py

Mail plugin test coverage
DeltaFile
+447-25tests/api2/test_mail.py
+46-35src/middlewared/middlewared/plugins/mail/send.py
+60-4src/middlewared/middlewared/test/integration/fake_servers/smtp.py
+29-6src/middlewared/middlewared/plugins/mail/send_queue.py
+5-0src/middlewared/middlewared/test/integration/assets/mail.py
+3-0src/middlewared/middlewared/plugins/mail/queue.py
+590-704 files not shown
+593-7510 files

LLVM/project 25f9838llvm/lib/Target/AMDGPU GCNVOPDUtils.cpp

AMDGPU: Refactor checkVOPDRegConstraints
DeltaFile
+28-41llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+28-411 files

pkgng/pkgng 90b994clibpkg/repo/binary update.c

repo: open catalogue read-only when checking validity

pkg_repo_binary_update opened the repo DB read-write just to sanity
check it, even when no update was needed. Open read-only instead;
the actual read-write open in pkg_repo_binary_init_update already
runs only after new data is fetched.
DeltaFile
+7-1libpkg/repo/binary/update.c
+7-11 files

LLVM/project beae6deflang/lib/Lower Bridge.cpp, flang/test/Lower/OpenMP wsloop-select-case.f90 wsloop-computed-goto.f90

[flang][PFT-to-MLIR] lazily allocate label-target blocks in branch lowering

Problem
-------
Under -mmlir --wrap-unstructured-constructs-in-execute-region, branch
lowering can hit a null Evaluation::block for a branch target.  For
example, genMultiwayBranch trips

    Bridge.cpp: Assertion `block && "missing multiway branch block"' failed

and genFIR(SelectCaseStmt) trips

    Bridge.cpp: Assertion `e->block && "missing CaseStmt block"' failed

The wrap machinery decides an unstructured DO/IF is wrappable and
therefore stops propagating its isUnstructured flag to the enclosing
construct.  The enclosing construct's isUnstructured stays false, so the
top-level createEmptyBlocks does not recurse into its body.  If that
enclosing construct's lowering then takes over the body itself instead

    [14 lines not shown]
DeltaFile
+35-15flang/lib/Lower/Bridge.cpp
+35-0flang/test/Lower/OpenMP/wsloop-select-case.f90
+25-0flang/test/Lower/OpenMP/wsloop-computed-goto.f90
+95-153 files

FreeNAS/freenas 6f8bfd5src/middlewared/middlewared/plugins/mail send.py send_queue.py, src/middlewared/middlewared/test/integration/assets mail.py

Mail plugin test coverage
DeltaFile
+447-25tests/api2/test_mail.py
+46-35src/middlewared/middlewared/plugins/mail/send.py
+60-4src/middlewared/middlewared/test/integration/fake_servers/smtp.py
+29-6src/middlewared/middlewared/plugins/mail/send_queue.py
+8-3src/middlewared/middlewared/plugins/mail/config.py
+5-0src/middlewared/middlewared/test/integration/assets/mail.py
+595-733 files not shown
+599-769 files

LLVM/project 136547cllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize vplan-vectorize-inner-loop-reduction.ll vplan-widen-select-instruction.ll

[VPlan] Detect contiguous accesses in outer loop VPlan path. (#203790)

Use SCEV analysis on VPValue pointer operands to detect stride-1 memory
accesses in the outer loop vectorization path. When a load or store
address is an affine AddRec w.r.t. the vectorized outer loop with stride
equal to the element size, mark it as consecutive so it generates a wide
load/store instead of a gather/scatter.

For example, in the column-scaling pattern:

```
  for (i = 0; i < N; i++)       // outer: vectorized
    for (j = 0; j < M; j++)     // inner: uniform
      A[i*M+j] *= scale[i];
```

The access scale[i] is now correctly identified as contiguous and
generates a vector load instead of a masked gather.

PR: https://github.com/llvm/llvm-project/pull/203790
DeltaFile
+43-24llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
+27-20llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+10-6llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll
+8-6llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
+7-4llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
+7-4llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
+102-6412 files not shown
+144-8818 files

LLVM/project aeda9aellvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/RISCV/rvv vecreduce-xor-constant-fold.ll vecreduce-or-constant-fold.ll

[SelectionDAG] Fold VECREDUCE_AND/OR/XOR of a constant BUILD_VECTOR (#210883)

Follows up on #207560 and #210126

Adds constant folding for `ISD::VECREDUCE_AND`, `ISD::VECREDUCE_OR`, and
`ISD::VECREDUCE_XOR` in SelectionDAG::FoldConstantArithmetic when the
input is a BUILD_VECTOR of integer constants. Does not fold undef/poison
elements.

Fixes #209108
DeltaFile
+55-0llvm/test/CodeGen/RISCV/rvv/vecreduce-xor-constant-fold.ll
+53-0llvm/test/CodeGen/RISCV/rvv/vecreduce-or-constant-fold.ll
+53-0llvm/test/CodeGen/RISCV/rvv/vecreduce-and-constant-fold.ll
+6-1llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+167-14 files

LLVM/project ea20554llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanLowering.cpp

[VPlan] Move lowering transforms to VPlanLowering.cpp (NFC) (#209885)

Following up to https://github.com/llvm/llvm-project/pull/209883,
 move transformations related to lowering/preparing for execution
to VPlanLowering.cpp

This moves materialize*, convertToConcreteRecipes,
dissolveLoopRegions, expandBranchOnTwoConds,
replaceWideCanonicalIVWithWideIV, expandSCEVsToVPInstructions, 
addBranchWeightToMiddleTerminator and the alias-mask materialization helpers.

The createScalarIVSteps and scalarizeVPWidenPointerInduction are
promoted to vputils.

Depends on https://github.com/llvm/llvm-project/pull/209883
DeltaFile
+3-1,220llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1,177-0llvm/lib/Transforms/Vectorize/VPlanLowering.cpp
+52-0llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+20-0llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+18-0llvm/lib/Transforms/Vectorize/VPlanUtils.h
+1-0llvm/lib/Transforms/Vectorize/CMakeLists.txt
+1,271-1,2206 files

LLVM/project 7f9f1acllvm/tools/llvm-ir2vec/Bindings CMakeLists.txt, llvm/tools/llvm-ir2vec/Bindings/python LICENSE.TXT README.md

[llvm-ir2vec] Adding metadata for llvm-ir2vec python binding wheel builds (#194222)

The next step is to setup the metadata for the wheel building process,
and subsequently follow it up with workflow jobs that can automate this.
DeltaFile
+279-0llvm/tools/llvm-ir2vec/Bindings/python/LICENSE.TXT
+83-0llvm/tools/llvm-ir2vec/Bindings/python/README.md
+35-0llvm/tools/llvm-ir2vec/Bindings/python/pyproject.toml
+35-0llvm/tools/llvm-ir2vec/Bindings/python/setup.py
+18-4llvm/tools/llvm-ir2vec/Bindings/CMakeLists.txt
+13-0llvm/tools/llvm-ir2vec/Bindings/python/ir2vec/__init__.py
+463-42 files not shown
+469-48 files

pkgng/pkgng 45874a6tests/frontend repo.sh

tests: add repo_filelist_data regression test

Verify that data.pkg never contains file lists or directories
regardless of --list-files, and that -l still generates the file
database (files.pkg) listing the package files.
DeltaFile
+38-1tests/frontend/repo.sh
+38-11 files

pkgng/pkgng 1891a25libpkg pkg_repo_create.c

repo: keep file lists out of the data catalog

The data catalog (data.pkg) and per-package manifest must not contain
file lists or directories; those belong only to the file database emitted
via -l/--list-files.  Emit the data catalog in compact form so data.pkg
is identical whether or not --list-files is used.  Previously -l caused the
full +MANIFEST (with files) to be read and re-emitted into data, ballooning
the catalog (e.g. a full i386 repo grew from ~60MB to ~2GB).
DeltaFile
+9-1libpkg/pkg_repo_create.c
+9-11 files

NetBSD/pkgsrc q6OMaW6doc CHANGES-2026

   Updated devel/py-jaraco.test, textproc/py-jsonrpclib-pelix
VersionDeltaFile
1.4631+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc DxppR9Itextproc/py-jsonrpclib-pelix distinfo Makefile

   py-jsonrpclib-pelix: updated to 1.1.0

   1.1

   - Fixed access to error message in results
   - Allow the request query ID to be set to 0 or empty string
   - Allow the definition of a classes registry to restrict dynamic imports
   - Allow the definition of a maximum content length to reject large requests
   - Overall code review
   - Disable `cjson` and `simplejson` tests on Python 3.15
VersionDeltaFile
1.10+4-4textproc/py-jsonrpclib-pelix/distinfo
1.14+2-2textproc/py-jsonrpclib-pelix/Makefile
+6-62 files

NetBSD/pkgsrc YWdl81edevel/py-jaraco.test distinfo Makefile

   py-jaraco.test: updated to 5.7.0

   v5.7.0

   Features
   - Added ``ensure_checkout`` fixture in ``jaraco.test.git`` to skip a test unless the project is a git checkout with an ``origin`` remote.
VersionDeltaFile
1.5+4-4devel/py-jaraco.test/distinfo
1.8+2-2devel/py-jaraco.test/Makefile
1.6+3-1devel/py-jaraco.test/PLIST
+9-73 files

LLVM/project 25d57b2llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp, llvm/test/CodeGen/AMDGPU amdgpu-sw-lower-lds-flat-ptr-arg-asan.ll

update
DeltaFile
+231-94llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+213-30llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-ptr-arg-asan.ll
+444-1242 files

LLVM/project c256325llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp, llvm/test/CodeGen/AMDGPU amdgpu-sw-lower-lds-flat-ptr-arg-asan.ll

[AMDGPU] Fix LDS access via flat pointer argument in amdgpu-sw-lower-lds
DeltaFile
+82-0llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+73-0llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-ptr-arg-asan.ll
+155-02 files

LLVM/project acfaabellvm/lib/Target/RISCV RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV O3-pipeline.ll

Revert "[RISCV] Run EarlyMachineLICM before VLOptimizer to hoist constant splats" (#210937)

Reverts llvm/llvm-project#210028

I've bisected the hangs on rva20 to this commit:
https://lab.llvm.org/buildbot/#/builders/210/builds/11806
DeltaFile
+0-119llvm/test/CodeGen/RISCV/rvv/vl-opt-licm.ll
+16-16llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
+1-9llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+4-5llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+0-4llvm/test/CodeGen/RISCV/O3-pipeline.ll
+21-1535 files

LLVM/project 6d8d3f8clang/docs UsersManual.md ReleaseNotes.md, clang/include/clang/Basic LangOptions.def

[clang] Add flag for making pointer subtraction defined (#196392)

The C and C++ standards require both operands of pointer subtraction to
refer to elements of the same array object. Clang/LLVM currently relies
on this rule in several optimizations:

- `inbounds` GEP introduces UB assumptions once the computed address
escapes the originating object bounds.

- `sdiv exact` assumes %op1 is divisable by %op2 otherwise it is a
poison value.

The first issue may be addressed with -fwrapv-pointer command line
option, however there is no option in clang to mitigate the second
issue. Patch adds a new -fdefined-pointer-subtraction to address this.
DeltaFile
+16-0clang/docs/UsersManual.md
+15-0clang/test/CodeGen/ptr-subtract-stable.c
+13-0clang/include/clang/Options/Options.td
+3-0clang/docs/ReleaseNotes.md
+3-0clang/lib/Driver/ToolChains/Clang.cpp
+2-0clang/include/clang/Basic/LangOptions.def
+52-01 files not shown
+54-07 files

NetBSD/pkgsrc BEJNoiLdoc CHANGES-2026

   doc: Updated textproc/groff to 1.24.1nb1
VersionDeltaFile
1.4630+2-1doc/CHANGES-2026
+2-11 files