LLVM/project 612b8b1 — llvm/lib/Target/AMDGPU SIPreEmitPeephole.cpp, llvm/test/CodeGen/AMDGPU si-pre-emit-peephole-unpack-dst-flags.mir unpack-non-coissue-insts-post-ra-scheduler.mir

[AMDGPU] Keep dst flags when unpacking packed F32 instructions (#234858)

performF32Unpacking copied the new instructions' dst operands by value,
so
its setIsUndef and setIsRenamable calls never reached the instructions.
Take
the operands by reference.


Assisted-by: Claude Opus 5.5
DeltaFile
+44-44llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
+20-0llvm/test/CodeGen/AMDGPU/si-pre-emit-peephole-unpack-dst-flags.mir
+2-2llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+66-463 files

FreeBSD/ports b070249 — databases/pg_citus Makefile pkg-plist

databases/pg_citus: update to 14.3.0

Changes:        https://github.com/citusdata/citus/releases/tag/v14.3.0
Reported-by:    portscout
DeltaFile
+3-3databases/pg_citus/distinfo
+4-0databases/pg_citus/pkg-plist
+1-1databases/pg_citus/Makefile
+8-43 files

LLVM/project 1a62c9c — llvm/test/CodeGen/AMDGPU flat-saddr-atomics.ll, llvm/test/CodeGen/AMDGPU/GlobalISel extractelement.ll llvm.amdgcn.image.atomic.dim.a16.ll

AMDGPU: Don't reserve the implicit buffer pointer with architected flat scratch

Mesa shaders always had s[0:1] reserved for the implicit buffer
pointer, which is only needed to set up the scratch buffer
resource. With architected flat scratch, scratch is initialized by the
hardware and the pointer is unused. The driver stopped passing this
pointer so all user SGPRs were off by 2.

Don't reserve it on targets with architected flat scratch, so the user
SGPRs of Mesa shaders start at s0. Diagnose the use in the unsupported
contexts. This fixes many test failures on my system when running
piglit.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+2,112-452llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+1,222-1,222llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+738-856llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+779-753llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+84-1,344llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
+673-574llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+5,608-5,201107 files not shown
+17,248-15,047113 files

FreeBSD/ports 0772739 — lang/perl5-devel version.mk Makefile, lang/perl5-devel/files patch-Configure

lang/perl5-devel: update to 5.45.4

Changes:        https://metacpan.org/release/EHERMAN/perl-5.45.4/view/pod/perldelta.pod
DeltaFile
+4-4lang/perl5-devel/files/patch-Configure
+3-3lang/perl5-devel/distinfo
+1-1lang/perl5-devel/version.mk
+1-1lang/perl5-devel/Makefile
+2-0lang/perl5-devel/pkg-plist
+11-95 files

FreeBSD/ports 2482ab2 — textproc/R-cran-XML Makefile distinfo

textproc/R-cran-XML: Update to 3.99-0.25

Reported by:    portscout
DeltaFile
+3-3textproc/R-cran-XML/distinfo
+1-1textproc/R-cran-XML/Makefile
+4-42 files

LLVM/project c2013b0 — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

Merge branch 'users/void/asm-rm-4-regallocfast-fold' into users/void/asm-rm-5-prefer-reg
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+3-7llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+63-686 files

LLVM/project ec468f3 — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

Merge branch 'users/void/asm-rm-3-direct-mem-output-error' into users/void/asm-rm-4-regallocfast-fold
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+3-7llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+63-686 files

LLVM/project 1863ded — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

Merge branch 'users/void/asm-rm-2-fold-tied-operands' into users/void/asm-rm-3-direct-mem-output-error
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+3-7llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+63-686 files

LLVM/project 3111c20 — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

Merge branch 'users/void/mir-inline-asm-operand-count' into users/void/asm-rm-2-fold-tied-operands
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+3-7llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+63-686 files

LLVM/project 54cda14 — llvm/lib/CodeGen/MIRParser MIParser.cpp, llvm/test/CodeGen/MIR/Generic inline-asm-ops-too-large.mir inline-asm-ops-missing-count.mir

[MIR] Address review: merge error tests, un-lambda count parsing

Merge the three "ops:N" error tests into one with split-file, move the
operand count parsing out of a lambda into MIParser, and shorten the
round-trip test's comment.

Assisted-by: Claude Opus 5.5
DeltaFile
+29-28llvm/lib/CodeGen/MIRParser/MIParser.cpp
+31-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-errors.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+0-11llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+2-6llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+62-676 files

LLVM/project 95384c3 — llvm/test/CodeGen/MIR/X86 inline-asm-operand-count.mir

Remove -verify-machineinstrs command line flag

Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
DeltaFile
+1-1llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+1-11 files

LLVM/project ee8cfbf — llvm/lib/Target/AMDGPU SOPInstructions.td, llvm/test/CodeGen/AMDGPU add-max.ll uaddsat.ll

AMDGPU: Use S_ADD_I32 to select uniform uaddsat (#235242)

95ff1fa00ed4 selected uniform uaddsat.i32 to an S_ADD_U32 sequence.
S_ADD_U32 defines a carry out, so when the instructions have to be
moved to the VALU it is replaced with V_ADD_CO_U32_e32, which doesn't
exist on gfx10+. This would later assert when encoded. moveToVALU
should probably learn to handle that correctly, or at least assert.
The carry isn't needed, so use S_ADD_I32 like the usubsat pattern,
which is moved to V_ADD_U32_e64 where available.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+83-4llvm/test/CodeGen/AMDGPU/uaddsat.ll
+1-1llvm/test/CodeGen/AMDGPU/add-max.ll
+1-1llvm/lib/Target/AMDGPU/SOPInstructions.td
+85-63 files

LLVM/project 29c09be — llvm/lib/Target/RISCV RISCVIndirectBranchTracking.cpp RISCVQCRelaxMarking.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+74-16llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+263-1245 files not shown
+366-16311 files

LLVM/project 664306a — llvm/lib/Target/RISCV RISCVIndirectBranchTracking.cpp RISCVQCRelaxMarking.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+61-14llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+250-1224 files not shown
+326-15110 files

LLVM/project 32d286f — llvm/lib/Target/RISCV RISCVIndirectBranchTracking.cpp RISCVQCRelaxMarking.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+61-14llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+250-1224 files not shown
+326-15110 files

LLVM/project 379eb89 — llvm/lib/Target/RISCV RISCVMakeCompressible.cpp RISCVIndirectBranchTracking.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+52-12llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+32-8llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+242-1173 files not shown
+283-1369 files

OpenBSD/ports Ecb2VDB — x11/kde-applications/keepsecret Makefile

   Add depends in KDE_DEPENDS
VersionDeltaFile
1.5+8-7x11/kde-applications/keepsecret/Makefile
+8-71 files

LLVM/project c467c6b — clang/lib/AST ExprConstant.cpp

[clang][ExprConst] Add missing `FastEvaluateAsRValue` in `EvaluateKnownConstInt{,CheckOverflow}` (#234552)

This was missing for some reason.
DeltaFile
+14-0clang/lib/AST/ExprConstant.cpp
+14-01 files

LLVM/project b968e74 — libcxx/test/benchmarks/numeric reduce.bench.cpp transform_reduce.bench.cpp

[libc++] Add benchmarks for std::reduce and std::transform_reduce (#233374)

The PR adds benchmarks for these algorithms:
- `std::reduce()`
- `std::transform_reduce()`, unary transform
- `std::transform_reduce()`, binary transform

The benchmarks run minimal reduction and transformation operators with
`int`, `float` and `double` parameters.
`std::vector` and `std::list` containers are tested, `std::deque` is not
included to reduce the number of added benchmarks.

Fixes #226211

---------

Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
DeltaFile
+127-0libcxx/test/benchmarks/numeric/transform_reduce.bench.cpp
+80-0libcxx/test/benchmarks/numeric/reduce.bench.cpp
+207-02 files

OpenBSD/ports BsV4hcj — devel/kdevelop distinfo, devel/kdevelop/pkg PLIST

   Update to KDE Gear 26.08.2
VersionDeltaFile
1.59+2-2devel/kdevelop/distinfo
1.61+3-0devel/kdevelop/pkg/PLIST
+5-22 files

OpenBSD/ports gN1upE7 — editors/calligra/pkg PLIST, meta/kde Makefile

   Update KDE Gear 26.08.2

   https://kde.org/announcements/gear/26.08.2/
VersionDeltaFile
1.28+25-0x11/kde-applications/step/pkg/PLIST
1.39+25-0editors/calligra/pkg/PLIST
1.35+23-0x11/kde-applications/konqueror/pkg/PLIST
1.31+19-0x11/kde-applications/kdepim-runtime/pkg/PLIST
1.4+5-5x11/kde-applications/keepsecret/Makefile
1.60+4-2meta/kde/Makefile
+101-7248 files not shown
+615-425254 files

LLVM/project 4531bae — llvm/lib/Target/RISCV RISCVLandingPadSetup.cpp RISCVMakeCompressible.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+43-10llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+32-8llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+22-7llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+194-642 files not shown
+210-748 files

LLVM/project bc18c48 — llvm/lib/Target/RISCV RISCVMakeCompressible.cpp RISCVIndirectBranchTracking.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+52-12llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+32-8llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+242-1173 files not shown
+283-1369 files

LLVM/project 9c20e5e — clang/lib/CIR/Dialect/IR CIRDialect.cpp, clang/test/CIR/Transforms canonicalize.cir

[CIR] Fix cir.cast fold crash on a same type integral cast (#234236)

The fold called fold() on the source defining op, which is null for
block arguments
DeltaFile
+1-7clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+7-0clang/test/CIR/Transforms/canonicalize.cir
+8-72 files

LLVM/project 73c0f4b — clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenExprScalar.cpp

[CIR] Narrow blanket -fopenmp NYI guards to OGCG conditions (#233671)

Ordinary code compiled with -fopenmp hit errorNYI on every assignment,
inc/dec, member access and global reference
DeltaFile
+76-0clang/test/CIR/CodeGenOpenMP/non-openmp-code.cpp
+4-5clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+2-4clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+2-4clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
+2-2clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-0clang/include/clang/CIR/MissingFeatures.h
+88-156 files

LLVM/project 471de9d — llvm/lib/Target/AMDGPU SOPInstructions.td, llvm/test/CodeGen/AMDGPU add-max.ll uaddsat.ll

AMDGPU: Use S_ADD_I32 to select uniform uaddsat

95ff1fa00ed4 selected uniform uaddsat.i32 to an S_ADD_U32 sequence.
S_ADD_U32 defines a carry out, so when the instructions have to be
moved to the VALU it is replaced with V_ADD_CO_U32_e32, which doesn't
exist on gfx10+. This would later assert when encoded. moveToVALU
should probably learn to handle that correctly, or at least assert.
The carry isn't needed, so use S_ADD_I32 like the usubsat pattern,
which is moved to V_ADD_U32_e64 where available.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+83-4llvm/test/CodeGen/AMDGPU/uaddsat.ll
+1-1llvm/test/CodeGen/AMDGPU/add-max.ll
+1-1llvm/lib/Target/AMDGPU/SOPInstructions.td
+85-63 files

OpenBSD/ports SHms6M2 — lang/ruby/3.4 Makefile distinfo

   Update to Ruby 3.4.12

   Fixes CVE-2026-89078, CVE-2026-93577, CVE-2026-97229 and CVE-2026-110264

   OK tb@
VersionDeltaFile
1.12+2-2lang/ruby/3.4/distinfo
1.17+1-1lang/ruby/3.4/Makefile
+3-32 files

OpenBSD/ports 5fR6EjS — lang/ruby/4.0 Makefile distinfo, lang/ruby/4.0/patches patch-common_mk

   Update to Ruby 4.0.9

   Fixes CVE-2026-89078, CVE-2026-93577, CVE-2026-97229 and CVE-2026-110264

   OK tb@
VersionDeltaFile
1.9+2-2lang/ruby/4.0/pkg/PLIST-main
1.9+2-2lang/ruby/4.0/distinfo
1.2+1-1lang/ruby/4.0/patches/patch-common_mk
1.14+1-1lang/ruby/4.0/Makefile
+6-64 files

OpenBSD/src bgYSpsv — usr.sbin/npppd/l2tp l2tp.h l2tp_ctrl.c

   Limit the number of pending L2TP connections.  Previously, an
   unlimited number of pending connections could exhaust npppd's memory.

   From acts1631
   ok mvs
VersionDeltaFile
1.28+15-2usr.sbin/npppd/l2tp/l2tp_ctrl.c
1.16+8-3usr.sbin/npppd/l2tp/l2tp.h
+23-52 files

OpenBSD/ports 7sZR0A5 — net/wstunnel Makefile crates.inc, net/wstunnel/patches patch-Cargo_lock patch-wstunnel-cli_src_main_rs

   Update to wstunnel-11.1.0

   Changes:
   https://github.com/erebe/wstunnel/releases#release-v11.1.0

   From Christoph Liebender <christoph AT liebender DOT dev> (MAINTAINER)
VersionDeltaFile
1.14+360-312net/wstunnel/distinfo
1.14+179-155net/wstunnel/crates.inc
1.3+41-41net/wstunnel/patches/patch-wstunnel-cli_src_main_rs
1.8+5-4net/wstunnel/patches/patch-Cargo_lock
1.2+1-1net/wstunnel/pkg/wstunnel.rc
1.14+1-1net/wstunnel/Makefile
+587-5141 files not shown
+587-5147 files