interfaces: remove newwanip even from DHCP alias handling #10988
The alias handling has nothing to do with what newwanip is trying
to achieve so simply exlude it from requesting a rerun.
interfaces: avoid unnecessary alias reconfiguration on DHCP renewals
Only configure the alias during BOUND and REBOOT, leaving it untouched
during RENEW and REBIND. This prevents unnecessary interface reloads
when the DHCP lease is renewed without address changes.
While here, rename the change tracking variable for clarity.
PR: https://github.com/opnsense/core/issues/10988
[Inliner] Change CalleeTTI -> CallerTTI (#231905)
It makes more sense to use the caller's TTI, as this way we can query
whether the instruction can be inlined into the parent function, using
state described by the caller's TTI.
For example, for AArch64 SME where a function can be in a different mode
(streaming/non-streaming), the cost-model gives different answers based
on the TTI used.
For now, we don't expect to see any changes in behaviour as there are
currently no targets where it makes different cost/inlining-decisions
based on which TTI is used.
[FuncSpec] Relax restrictions on code size growth (#196570)
This patch is a preparation for
https://github.com/llvm/llvm-project/pull/195886 , which affects code
size and thus causes more functions to be rejected by the current code
size growth restriction in function specialisation.
[flang][OpenMP] Improve diagnosing invalid operators in DECLARE_REDUCTION
Move the check out of the common MakeNameFromOperator function and
into OmpStructureChecker. Remove the no longer needed SemanticsContext
parameter in MakeNameFromOperator.
This will allow reusing at least some parts of the the name-mangling
code in DECLARE_INDUCTION.
[AMDGPU] Pre-commit tests with a sub-optimal codgen in PromoteAlloca (#236731)
Tests show that for large vectors with a divergent dynamic index
`AMDGPUPromoteAlloca` forces long chains of `cmp`/`cndmask` in the
codegen.
Assisted-by: Claude Code
[AMDGPU] Price under-aligned memory operations
Without unaligned access for the address space, an access aligned below
4 bytes is split into pieces of its alignment. LDS accesses aligned to 4
use 8-byte pieces, and take a 12-byte piece only when aligned to 16 or
when unaligned DS access is enabled.
[AMDGPU] Price memory operations by the number of memory instructions
Price a load or store as the number of memory instructions it is split
into.
Constant and buffer "fat" pointers are left alone (for now).
[NFC][AMDGPU] Store through a global pointer in recursive search llvm-split tests (#233260)
Their function sizes then do not depend on the cost of flat stores.
Assisted-By: Claude Code Opus 5