[RISCV][P-ext] Fold an add of a multiply-parts product into the accumulate form (#222748)
An add of a multiply-parts product selects the accumulating instruction, so
that a loop written with `sum += __riscv_mul_h00_i32(a, b)` gets `macc.h00`
rather than a separate multiply and add.
Rewriting the add before type legalization keeps the shapes whose result is
illegal, so the existing accumulate lowering covers all of them.
[AMDGPU] Invalidate uniformity info after intrinsic combine (#222357)
The uniform intrinsic combine pass changed IR while preserving
uniformity information. Its result keeps references to cycle
information. Those references could be invalidated and later accessed
by another pass.
Invalidate uniformity information after a change. Before erasing an
instruction, remove it from the analysis state used by the pass. Also
report each erasure as a change so invalidation always runs.
x11/babl: Fix build
meson.build:1:0: ERROR: Value "false" (of type "string") for option "gi-docgen" is not one of the choices. Possible choices are (as string): "enabled", "disabled", "auto".
Approved by: blanket (fix build)
Fixes: 90274e2e7fe3 (update to 0.1.128 release)
Sponsored by: UNIS Labs
[AArch64] Form CCMP for CBB and CBH
AArch64ConditionalCompares forms CMP/CCMP chains to transform patterns
such as
Head Head
/ | CmpBB
/ | / |
| CmpBB => / |
| / | Tail |
| / | | |
Tail | | |
| | | |
... ... ... ...
where Head is terminated by a conditional branch and CmpBB contains
a cmp + conditional branch.
We usually try to split any fused conditional branches to be able to
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[RISCV][GlobalISel] Add G_CLMULH support (#221686)
Add G_CLMULH to represent the high half of a carry-less multiplication
in generic Machine IR.
Translate llvm.riscv.clmulh to G_CLMULH and mark it legal for native
XLEN scalar types when Zbkc is available. Reuse the existing
SelectionDAG pattern to select the RISC-V CLMULH instruction.
[AMDGPU][lld] Remove "using namespace llvm" from AMDGPU.cpp (#222818)
AMDGPU class in anonymous namespace collides with llvm::AMDGPU, causing
an error with MSVC.
[CIR][AMDGPU] Add support for AMDGCN global/DS load builtins (#220611)
Adds codegen support for AMDGCN global and DS load/read builtins with
transpose variants. These builtins are lowered to their corresponding
`llvm.amdgcn.*` intrinsics.
[SSAF][PointerFlow] Factor out and make the pointer-flow matching reusable
The PointerFlowExtractor matches AST nodes representing pointer-flows
and converts them to entity-based data structures directly. This
commit divides this procedure into two steps: 1) match and represent
AST nodes as PointerFlowPairs; 2) convert PointerFlowPairs to
entity-based edges. Therefore, other SSAF tools may use
PointerFlowPairs.
The refactoring also improves coverage: it separates pointer-type
checking from structural matching, so structural matching alone now
discovers cases that were previously missed due to overly aggressive
type checking (e.g. a record-typed call argument or return value
initialized with a braced-init-list).
Along the way, this also fixes a bug for unnamed bit-fields.
First patch for
rdar://187125348
[SSAF][PointerFlow] Drop unused TUSummaryExtractor param from translateDeclPointerLevel
TUSummaryExtractor is only needed to mint EntityIds when building an
EntityPointerLevel; translateDeclPointerLevel just walks the Expr and
returns raw DeclPointerLevels, so it never touched Extractor.
This is the second patch the radar below depends on:
rdar://187125348
[Mips] Fix buildbot failure of MIPS I double store using SWC1 (#221912)
Expand ExtractElementF64_FPR to FMOV_S instead of MFC1 to avoid
incorrect integer store.
Fix x86_64-expensive-checks compile error as for pr
https://github.com/llvm/llvm-project/pull/209362.
Fix #62190.
NAS-143516 / 26.0.0 / rename the s3 service from truenas_s3 to s3 (by anodos325) (#19683)
service.query reported it as truenas_s3, the daemon's name rather than
the protocol's. The services_services row has to move with
ServiceInterface.name or nothing resolves it, so a migration renames it;
ServiceWriteRole is keyed by the name upper-cased and moves too.
Root is refused as an access key account and as a bucket owner. Both run
as uid 0, which no bucket grant and no file mode restrains.
The daemon's own messages get /var/log/truenas_s3.log, filtered on the
journal identifier it writes, s3d, and rotated the way scst and
truenas-discoveryd are. Its audit records are a separate path and are
untouched.
The systemd unit, the etc group and the tables keep the truenas_s3 name:
they are the daemon's, and nothing outside middleware names them.
Original PR: https://github.com/truenas/middleware/pull/19672
Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
correct dma_tag_lookup() loop
drm_cd.cd_ndevs[] has pointers to drm_softc not drm_device
Currently, dma_tag_lookup() is only used by the apldcp/apldrm drivers.
At the start of the softc for both of those is struct platform_device.
If the loop doesn't match the the function argument is cast to
struct platform_device *, so the problem was not noticed.
discussed with kettenis@ and apldcp/apldrm tested on m1 mac mini
[mlir][AMDGPU] Split the dialect declaration (NFC)
Introduce a self-contained dialect declaration so RegisterAllDialects does not
need the generated AMDGPU operation umbrella.
Across five controlled rebuilds of the affected TU, median instructions fell
from 71.757B to 70.331B (-1.987%) and median wall time fell from 11.01s to
10.77s (-2.180%).
Assisted-by: Codex
[mlir][Func] Split the dialect declaration (NFC)
Introduce a self-contained dialect declaration and use it in ten configured
consumers that do not need the generated operation umbrella.
Across three controlled -j16 rebuilds of the affected TUs, median instructions
fell from 224.883B to 220.787B (-1.821%) and median wall time fell from 8.44s
to 8.31s (-1.540%).
Assisted-by: Codex
