[Clang] Enable UBSan for AMDGPU device offload
Summary:
This enables the device UBSan runtime for AMDGPU decides. Primarily this
required modifications to the `addSanitizerRuntime` interface so we can
query the compilation's offload status. Also need to forward it through
the linker wrapper interface. Works on all AMDGPU offload, slight hacks
around the other targets as they do not advertise sanitizer
runtimes properly.
This is linked in via a new `-u __ubsan_device_initialize` hook to pull
in the side library. This is standard behavior and keeps the core logic
mostly unchanged and re-used.
[Clang] Honor -Xarch_gfx* when linking the UBSan offload runtime
Empty bound architecture misses per-GPU sanitizer flags, so inspect each
offload arch when deciding whether the host interceptor is required.
[BOLT][RISCV] Implement register analysis hooks (#220581)
This patch implements the RISC-V register-analysis hooks in
`RISCVMCPlusBuilder` that previously fell back to the unimplemented
base-class methods.
The `MCPlusBuilder` unittests fixture is also extended to create a
RISC-V binary context. New tests cover the flags-register result,
zeroing-XOR recognition, ABI register masks, general-purpose register
masks, and non-scavengeable registers. These hooks provide the
target-specific register information required by BOLT analyses and
transformations on RISC-V.
BTW, this is split out as a prerequisite fo LongJump pass implement for
RISCV.
[BOLT][RISCV] Remove redundant AUIPCs when rewriting call pairs (#221965)
`FixRISCVCallsPass` replaces the AUIPC instruction with a Noop when
converting an AUIPC/JALR pair into a call or tail-call pseudo. Add the
`NOP` annotation so the existing RemoveNops pass can remove it, avoiding
an unnecessary instruction in the output.
[compiler-rt] Rename ubsan_device to ubsan_offload
The host interceptor and GPU handler library serve offload, not a
generic device sanitizer. Keep the Apple add_ubsan_device_testsuite name.
[compiler-rt] Add AMDGPU Device UndefinedBehaviorSanitizer runtime
Summary:
This adds support for full UBSan on the AMDGPU target. The GPU build of
`compiler-rt` will now build `libclang_rt.ubsan_standalone.a` and the
host build will now provide `libclang_rt.ubsan_device.a` for the
host-side formatting.
The **core** approach is to simply gather arguments from the device and
replay them on the host. The RPC interface acts as the narrow shim to
pass data between the CPU and GPU.
The changes to the core runtime are kept minimal, only exposing a few
needed hooks to re-run and symbolize reports coming from an external
caller. The device archive is a side-library which will only be present
for GPU offloading builds.
Putting this in `compiler-rt` via interceptors avoids an ABI edge
between many consumers, (OpenMP, HIP, Pytorch, etc). The runtime code is
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[VPlan] Append recipes created via builder to worklist
The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.
This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:
```c
long f(const int *p, const int *q, long n) {
long a = 0, b = 0;
for (long i = 0;; i++) {
if (p[i] && q[i]) { a += i; b += i; }
if (i + 1 == n) break;
}
return a + b;
}
```
Before:
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Switch to SmallVector with space on stack
SmallVector allows for much larger small sizes than SetVector, so use 256 to match InstructionWorklist.
We don't need to worry about duplicate worklist entries until we add users to the worklist.
[VPlan] Process simplifyRecipes in a worklist
This brings simplifyRecipes further in line with InstCombine, and asides from unlocking more simplifications it also helps avoid spurious test churn whenever passes are moved around simplifyRecipes.
For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification order as before.
I've gone through and checked every simplification we do is a canonicalisation that converges, and I checked on llvm-test-suite + SPEC CPU 2017 in various configurations that we don't hit any cycles.
[VPlan] Split simplifyRecipes into simplifyRecipes and combineRecipes
Bringing it in line with InstSimplify and InstCombine, split up simplifyRecipe into a function that modifies and creates recipes (combineRecipe), and one that is analysis-only (simplifyRecipe).
This allows us to avoid adding simplficiation only folds to the worklist in #213899.
The funclet.ll test no longer erases the constant-folded intrinsic call because vputils::isDeadRecipe returns false.
