LLVM/project 743813dllvm/test/CodeGen/AMDGPU div_i128.ll div_v2i128.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

GlobalISel: Use extended LLTs in lshr narrow combine (#210298)
DeltaFile
+3,024-2,355llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+3,080-2,174llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1,894-2,067llvm/test/CodeGen/AMDGPU/div_i128.ll
+1,365-1,378llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+1,625-788llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+218-153llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+11,206-8,91510 files not shown
+12,049-9,47316 files

LLVM/project 8888665llvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU global-saddr-load.ll

AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for applyD16Load (#210103)
DeltaFile
+14-1llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+2-2llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+16-32 files

NetBSD/pkgsrc-wip 04c6ec8libreswan distinfo TODO

libreswan: bump to 5.3.2

v5.3.2 (July 15, 2026)
* Security: Fixes http://libreswan.org/security/CVE-2026-14957
* x509: tighten nss_compat BER check [Andrew]
DeltaFile
+3-3libreswan/distinfo
+2-3libreswan/TODO
+1-1libreswan/Makefile
+6-73 files

LLVM/project 03b7806libcxx/test/libcxx-03/strings/basic.string/string.capacity max_size.pass.cpp allocation_size.pass.cpp

[libc++][test] Fix build failure from typo in #171785 (#210552)

If `__STDCPP_DEFAULT_NEW_ALIGNMENT__` is not defined, these tests will
fail to build due to a typo that was added in #171785.
DeltaFile
+1-1libcxx/test/libcxx-03/strings/basic.string/string.capacity/max_size.pass.cpp
+1-1libcxx/test/libcxx-03/strings/basic.string/string.capacity/allocation_size.pass.cpp
+2-22 files

LLVM/project 499fd10.github/workflows libcxx-build-and-test.yaml

[libc++] Run macOS CI on self-hosted runners instead of Github ones (#210124)

This should increase our capacity and allow better turn around times,
and potentially unblock additional test coverage.

Note that this change implies that the self-hosted runners provide a
version of Xcode that is supported by libc++ (the latest released one),
which is currently the case.
DeltaFile
+12-11.github/workflows/libcxx-build-and-test.yaml
+12-111 files

LLVM/project 3529bacllvm/include/llvm/Transforms/Scalar GVN.h

[fixup] Add a forward declaration for GVNLegacyPass class

To work around GCC compilation failure.
DeltaFile
+1-0llvm/include/llvm/Transforms/Scalar/GVN.h
+1-01 files

LLVM/project 066fba2llvm/test/CodeGen/AMDGPU llvm.log.ll llvm.log10.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fpow.ll

AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper (#210102)

Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
DeltaFile
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log.ll
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+2,760-1,251llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+912-86llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+536-218llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+290-131llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+11,694-4,8624 files not shown
+12,158-5,07110 files

LLVM/project fc6fa9aclang/include/clang/Basic BuiltinsAMDGPUDocs.td BuiltinsAMDGPU.td, clang/test/CodeGenOpenCL builtins-amdgcn-gfx13.cl

[AMDGPU] Builtins and intrinsics for v_cvt_scalef32_pk32_(fp|bf)6_f32

- builtins with documentation
- instructions
- new subtarget feature only for gfx13
- GlobalISel RegBankLegalize rules
- tests
DeltaFile
+646-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx13.ll
+48-0clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
+31-0clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+12-0clang/include/clang/Basic/BuiltinsAMDGPU.td
+10-0llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+6-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+753-07 files not shown
+768-713 files

LLVM/project e896930llvm/lib/Target/AMDGPU AMDGPUPreLegalizerCombiner.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-short-clamp.ll

AMDGPU/GlobalISel: Use integers for clamp i64 to i16 prelegalizer combine (#210101)
DeltaFile
+26-46llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+6-6llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+32-522 files

LLVM/project e3016cellvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU codegen-prepare-addrspacecast-non-null.ll

GlobalISel: Use extended LLTs in extract lowering (#210100)
DeltaFile
+60-29llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+1-1llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+79-485 files

LLVM/project 4f93957llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU fptrunc.f16.ll fptrunc.ll

GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering (#210099)
DeltaFile
+1,282-1,453llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+264-432llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+364-243llvm/test/CodeGen/AMDGPU/fptrunc.ll
+238-239llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
+176-91llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+49-49llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+2,373-2,5076 files

FreeNAS/freenas 06aeebbsrc/middlewared/middlewared/api/v26_0_0 vm.py, src/middlewared/middlewared/plugins/vm clone.py vms.py

NAS-141839 / 26.0.0-RC.1 / Stop a VM before destroying its backing zvols on delete (by Qubad786) (#19347)

Deleting a VM with `zvols=true` tore down the backing zvols before
stopping the domain, so ZFS could be pulled out from under a live qemu
process — risking in-flight corruption and leaving zvols that fail to
destroy with EBUSY. The `force` option also didn't really gate deleting
a running VM despite what its description implied.

Reject deleting an active (running/suspended) VM unless `force` is set,
and stop/undefine the domain before touching its zvols so the block
devices are released first; the `force` field description now matches
that behaviour. Picked up a few smaller VM-plugin tidy-ups along the
way: clone rollback unwinds the snapshots/clones (and half-created VM
record) it made if something fails partway, the disk-convert guard
treats suspended VMs like running ones, and the convert path check looks
at the real destination directory rather than its parent — with unit
tests for the convert checks.

Original PR: https://github.com/truenas/middleware/pull/19346

Co-authored-by: M. Rehan <mrehanlm93 at gmail.com>
DeltaFile
+109-0src/middlewared/middlewared/pytest/unit/plugins/vm/test_convert_validation.py
+27-30src/middlewared/middlewared/plugins/vm/clone.py
+15-6src/middlewared/middlewared/plugins/vm/vms.py
+5-3src/middlewared/middlewared/plugins/vm/vm_devices.py
+6-1src/middlewared/middlewared/api/v26_0_0/vm.py
+1-1tests/vm/test_vm.py
+163-416 files

LLVM/project 92539cfllvm/lib/Transforms/Scalar MemCpyOptimizer.cpp, llvm/test/Transforms/MemCpyOpt callslot.ll

[MemCpyOpt] Ensure call slot optz does not lower destination alloca alignment (#210667)

A destination alloca's alignment could have been unconditionally
overwritten, letting a lower-aligned source incorrectly undo a
previous alignment increase. This issue has been addressed by
considering the maximum alignment between the new source target
and current destination, adhering to what the existing comment
already promises.

Fixes: https://github.com/llvm/llvm-project/issues/208092.
DeltaFile
+2-1llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
+1-1llvm/test/Transforms/MemCpyOpt/callslot.ll
+3-22 files

LLVM/project 1e18a0fllvm/test/Transforms/MemCpyOpt callslot.ll

[MemCpyOpt] Precommit tests for PR210667 (NFC) (#210708)
DeltaFile
+18-0llvm/test/Transforms/MemCpyOpt/callslot.ll
+18-01 files

LLVM/project 29faf91llvm/test/CodeGen/AMDGPU div_i128.ll div_v2i128.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

GlobalISel: Use extended LLTs in lshr narrow combine
DeltaFile
+3,024-2,355llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+3,080-2,174llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1,894-2,067llvm/test/CodeGen/AMDGPU/div_i128.ll
+1,365-1,378llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+1,625-788llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+218-153llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+11,206-8,91510 files not shown
+12,049-9,47316 files

LLVM/project 24e0791llvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU global-saddr-load.ll

AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for applyD16Load
DeltaFile
+14-1llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+2-2llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+16-32 files

LLVM/project 3b0dd85llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU codegen-prepare-addrspacecast-non-null.ll

GlobalISel: Use extended LLTs in extract lowering
DeltaFile
+60-29llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+1-1llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+79-485 files

LLVM/project 8d11406llvm/test/CodeGen/AMDGPU llvm.log.ll llvm.log10.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fpow.ll

AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper

Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
DeltaFile
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log.ll
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+2,760-1,251llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+912-86llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+536-218llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+290-131llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+11,694-4,8624 files not shown
+12,158-5,07110 files

LLVM/project eb01b84llvm/lib/Target/AMDGPU AMDGPUPreLegalizerCombiner.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-short-clamp.ll

AMDGPU/GlobalISel: Use integers for clamp i64 to i16 prelegalizer combine
DeltaFile
+26-46llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+6-6llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+32-522 files

NetBSD/pkgsrc O06xhbfdoc CHANGES-2026

   doc: Updated devel/cargo-release to 1.1.3
VersionDeltaFile
1.4606+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc rDpFe5ndevel/cargo-release distinfo cargo-depends.mk, devel/cargo-release/patches patch-.._vendor_mio-1.0.4_src_sys_unix_selector_kqueue.rs

   devel/cargo-release: update to 1.1.3

   1.1.3 - 2026-07-10
   Fixes

    - Preserve comments, whitespace around version strings being edited
VersionDeltaFile
1.15+334-344devel/cargo-release/distinfo
1.15+110-113devel/cargo-release/cargo-depends.mk
1.18+3-3devel/cargo-release/Makefile
1.2+1-1devel/cargo-release/patches/patch-.._vendor_mio-1.0.4_src_sys_unix_selector_kqueue.rs
+448-4614 files

LLVM/project fb69735llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU fptrunc.f16.ll fptrunc.ll

GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering
DeltaFile
+1,282-1,453llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+264-432llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+364-243llvm/test/CodeGen/AMDGPU/fptrunc.ll
+238-239llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
+176-91llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+49-49llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+2,373-2,5076 files

LLVM/project 9287355lldb/packages/Python/lldbsuite/test lldbutil.py, lldb/test/API/macosx/simulator hello.cpp TestSimulatorPlatform.py

[lldb][test] Bump safety timeout in simulator tests to fix flakyness (#209180)

On really slow machines, the current 10 second timeout can expire and
cause the test to randomly fail. Bump the timeout to 10 minutes which 60
times the current value and should be unreachable even on the slowest of
machines.

To avoid making the tests run for 10 minutes, we now consistently kill
the test process on shutdown using the subprocess list in lldbtest which
gets killed on tearDown.
DeltaFile
+9-5lldb/packages/Python/lldbsuite/test/lldbutil.py
+3-1lldb/test/API/macosx/simulator/hello.cpp
+2-1lldb/test/API/tools/lldb-server/apple-simulator/TestAppleSimulatorOSType.py
+1-0lldb/test/API/macosx/simulator/TestSimulatorPlatform.py
+15-74 files

LLVM/project 88a19bdllvm/test/CodeGen/AMDGPU llvm.amdgcn.s.prefetch.inst.ll llvm.amdgcn.s.prefetch.data.ll, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-load.mir regbankselect-waterfall-call.mir

AMDGPU/GlobalISel: Use integers for read-any-lane split type (#210098)
DeltaFile
+150-72llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
+106-106llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+33-17llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
+24-24llvm/test/CodeGen/AMDGPU/indirect-call.ll
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+341-2476 files not shown
+364-27212 files

LLVM/project 112aac3llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel zextload.ll

AMDGPU/GlobalISel: Fix extending load narrow scalar (#210097)

isAnyScalar is explicit LLT::scalar check but we want to narrow scalar
integer types as well.
DeltaFile
+6-7llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+7-82 files

LLVM/project 75ee393llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-constant.mir

AMDGPU/GlobalISel: Use integer as MMO type for loads and stores lowering (#210096)

We could get away with just the type from MMO in most cases, but MMO splitting
creates MMO with LLT::scalar and we prefer integer.
DeltaFile
+1,622-1,442llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,064-944llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+828-738llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+842-722llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+250-220llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+121-121llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+4,727-4,1878 files not shown
+4,995-4,28614 files

LLVM/project 16e213fllvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.wave.shuffle.ll

[AMDGPU][GlobalISel] Fix wrong half selection in wave.shuffle lowering (#210661)

selectWaveShuffleIntrin XORed ThreadID with the shifted index instead of
the original index, picking the wrong lane half on wave64 targets
without wave wide bpermute (GFX10/GFX11)
DeltaFile
+7-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
+10-1llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+17-72 files

OPNSense/src da06275sys/dev/igc if_igc.c

igc: some interrupt-specific logging
DeltaFile
+49-0sys/dev/igc/if_igc.c
+49-01 files

LLVM/project 65e4e40clang/include/clang/Basic BuiltinsAMDGPUDocs.td BuiltinsAMDGPU.td, clang/test/CodeGenOpenCL builtins-amdgcn-gfx13.cl

[AMDGPU] Builtins and intrinsics for v_cvt_scalef32_pk32_(fp|bf)6_f32

- builtins with documentation
- instructions
- new subtarget feature only for gfx13
- GlobalISel RegBankLegalize rules
- tests
DeltaFile
+646-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx13.ll
+48-0clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
+31-0clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+12-0clang/include/clang/Basic/BuiltinsAMDGPU.td
+10-0llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+3-3llvm/lib/Target/AMDGPU/VOP3Instructions.td
+750-37 files not shown
+768-713 files

NetBSD/pkgsrc-wip dd0f294chromium Makefile

chromium: sync esbuild version fix from www/chromium
DeltaFile
+1-1chromium/Makefile
+1-11 files