[Offload][Omp] Migrate ZeroCopy query to liboffload (#236735)
Add a new property to `olGetDeviceInfo` to query if host memory should
be preferred over device copies (`PREFERS_ZERO_COPY`). Use it to
implement libomptarget `AutoZeroCopy` logic.
Remove `GenericPluginTy::use_auto_zero_copy` interface as a result.
Assisted by Claude.
[AArch64][llvm] Ensure svnot_u32_x() intrinsic is optimised to subr
An all-active `svnot_u32_x()` currently generates `ptrue` followed by `not`.
Optimise this to subr `z0.b, z0.b, #255`, which subtracts each byte from
255 and therefore flips every bit. This implements bitwise `not` for
vectors of 8, 16, 32, or 64-bit elements. Test all these four widths.
[AArch64][llvm] Add pre-commit tests for all-active SVE not intrinsics
Cover all four integer widths with undefined and merging passthroughs,
plus a partially active predicate that must preserve inactive lanes.
[VPlan] Allow early exit loops with side effects by masking in the vector loop.
When all blocks with side effects are dominated by every early exit, we can vectorize the loop if we mask off any lanes past the exit. We can do this with control flow:
```mermaid
flowchart TD
header --> exiting
exiting -->| exit mask | sideeffects --> latch --> latch.split
exiting -->| !exit mask | latch.split
```
For every early exiting block we add a branch to the latch on `!mask.beforefirst(exitcond)`. This is implemented in UncountableExitStyle::ReadOnly which is now renamed to MaskedHandleExitInVectorLoop.
This is a complementary exit style to MaskedHandleExitInScalarLoop. If any of the side effects aren't dominated by the early exit it still falls back to the scalar loop style, which is why none of the existing early exit side effect tests changed. Masking in loop is profitable for RISC-V and I'm assuming it's also profitable for AArch64 too, but if not then we can add a TTI hook for a preferred exit style.
[libc++] Submit the results of PR benchmarks to LNT and link to them (#237102)
Now that we produce LNT v5 JSON in the benchmarking jobs, we can submit
it to LNT as a data point with an expiration date and include the link
in the comment we post to the PR.
The expiration date should help avoid bloating the LNT instance if this
kind of PR benchmarking becomes more mainstream.
[VPlan] Tighten findUserOf to singleton (NFC) (#236757)
Tighten findUserOf to findSingleUser, rewriting it in terms of
find_singleton.
Co-authored-by: Benjamin Maxwell <benjamin.maxwell at arm.com>
[mlir][ArmNeon][ArmSVE] Restrict vector operands and results to rank 1 (#236539)
Neither dialect needs multidimensional vectors, unless explictely
required (see e.g. `Sdot2dOp`). Restrict vector operands and results to
rank 1 to reject unsupported shapes during verification.
Since `AnyScalableVectorOfAnyRank` tablegen definition is no longer
used, this PR deletes it.
net-mgmt/netbox: Add compatibility for DRF 3.18.3
* Backport upstream compatibility fix for Django REST Framework (DRF) 3.18.3
from the 4.7.x branch and remove the no longer required monkey patch for
the uniqueness validation issue.
* Local test suite with PostgreSQL 14 and 18 runs fine. The same applies
to runtime tests.
MFH: 2026Q4
(cherry picked from commit da84e180cd71cc0850eae09db9324c988e64c200)
[SelectOpt] Fix dominance violations when converting select groups (#234349)
Converting a select group to a branch could break dominance:
- Aux instructions between the selects were sunk to the end block, but
may be used as true/false values of the group. Hoist them instead.
- The sinking slice could walk through a select-like group member and
sink its operands to one side, while its clone on the other uses them.
Assisted-By: Claude Opus 5.5 <noreply at anthropic.com>
Reapply - [AMDGPU] Reserve ENABLE_WAVEFRONT_SIZE32 on gfx125x (#236533)
Wave32-only targets (gfx1250, gfx1250-strict, gfx1251, gfx12-5-generic)
reserve the kernel descriptor's ENABLE_WAVEFRONT_SIZE32; it must be 0.
The compiler set it to 1.
The wave size is selectable only on targets with both supports-wave32
and supports-wave64. Elsewhere, clear the bit, stop printing
.amdhsa_wavefront_size32, and reject the directive in the assembler.
The disassembler now rejects a set bit on every target without a
selectable wave size. This replaces the gfx9-only check and also covers
GFX6-GFX8, matching the documentation.
Document which targets select the wave size through this bit.
[Hexagon] Disable machine verifier in namedregs.ll (#237065)
CS0/1 registers became allocatable in #236522 to properly support
circular instructions. The namedregs.ll tests used cs0/1 in a global
register variable but there is no option to reserve cs0/1. The same is
true to another pair of allocatable named registers, m0/1.
Machine verifier, enabled by default with EXPENSIVE_CHECKS, fails if a
non-reserved undefined physical register is used.
Since it's not clear if there is any use case for reserving cs0/1, just
disable the machine verifier in this test.
Signed-off-by: Alexey Karyakin <akaryaki at qti.qualcomm.com>
[C++26] Define the __cpp_pp_embed feature-test macro (#236263)
Follow-up to #233285, where the macro was deliberately left out per the
feature-test-macro criteria in the InternalsManual.
Going through those criteria now:
- Rejecting valid code / accepting invalid code: no known issues.
- Miscompilations: the multi-byte `#embed` braced-list miscompile
(#222796)
was fixed by #231938.
- Crashes/assertions: the parameter-lexing assertion (#212075) was fixed
by
#235934. The remaining open reports are crashes on invalid code only
(#182212 -- constant evaluator on an invalid cast, #219332 -- OOM on a
self-referential `prefix()`), plus tooling-side reports (#138439 clangd,
#118789 ASan).
I also smoke-tested every valid-code `#embed` form (constructor
list-init, arrays, scalars and fixed enums, `prefix`/`suffix`,
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[llvm] Remove unused local variables (NFC) (#237098)
This patch removes unused local variables of container, string, and
value types across llvm/.
Note that most of these variables did not trigger -Wunused-variable
because their types have non-trivial constructors or destructors, and
their initializers have no side effects.
Assisted-by: Antigravity
