LLVM/project 75a3379llvm/lib/Target/AMDGPU SIISelLowering.cpp

Review comments:
use input wave instruction for checks
DeltaFile
+7-7llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+7-71 files

LLVM/project f0593abcmake/Modules LLVMVersion.cmake, libcxx/include __config

Bump version to 22.1.4
DeltaFile
+1-1cmake/Modules/LLVMVersion.cmake
+1-1libcxx/include/__config
+1-1llvm/utils/gn/secondary/llvm/version.gni
+1-1llvm/utils/mlgo-utils/mlgo/__init__.py
+1-1llvm/utils/lit/lit/__init__.py
+5-55 files

LLVM/project b914982llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vfdiv-vp.ll fixed-vectors-vfdiv-vp.ll

[RISCV] Remove codegen for vp_fdiv (#190591)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off the vp.fdiv intrinsic from #179622.
DeltaFile
+344-594llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
+135-143llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
+45-45llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
+36-36llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
+8-12llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+1-4llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+569-8342 files not shown
+573-8358 files

LLVM/project 048a5e7llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fsub.ll llvm.amdgcn.reduce.fadd.ll

[AMDGPU] DPP wave reduction for double types - 2

Supported Ops: `fadd` and `fsub`
DeltaFile
+1,030-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+1,008-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+12-10llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,050-2703 files

LLVM/project c18c909llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmax.ll llvm.amdgcn.reduce.fmin.ll

[AMDGPU] DPP wave reduction for double types - 1

Supported Ops: `fmin` and `fmax`
DeltaFile
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+27-13llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,251-4813 files

OPNSense/core 816271dsrc/opnsense/www/js opnsense_bootgrid.js

bootgrid: shorten previous

(cherry picked from commit 7a6a581209024b2b08a846c3699330a067e611f1)
DeltaFile
+2-2src/opnsense/www/js/opnsense_bootgrid.js
+2-21 files

OPNSense/core 7a6a581src/opnsense/www/js opnsense_bootgrid.js

bootgrid: shorten previous
DeltaFile
+2-2src/opnsense/www/js/opnsense_bootgrid.js
+2-21 files

OPNSense/core 6e4cbcesrc/opnsense/www/js opnsense_bootgrid.js

bootgrid: limit maintaining scroll position to inplace=true, continuation of 75e60e8

This shouldn't be the default behavior, as a "refresh" would also
maintain scrolling position.

(cherry picked from commit e67ea610853257814b6f9f543a7ed70e26d47654)
DeltaFile
+3-3src/opnsense/www/js/opnsense_bootgrid.js
+3-31 files

LLVM/project 55a3382llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 half-fneg-fabs.ll

[X86] Add DAG combine to fold promoted f32 sequences for f16 fneg and fabs (#189395)

This patch optimizes f16 fneg and fabs on X86 targets by introducing 
a DAG combine to identify and collapse fpext -> fneg/fabs -> fptrunc.

Generally f16 operations are promoted to f32. For bitwise-equivalent 
operations like fneg and fabs, this results in unnecessary and 
expensive f32 library calls (__extendhfsf2 / __truncsfhf2) or 
hardware conversions (vcvtph2ps / vcvtps2ph) at -O0.

Fixes: https://github.com/llvm/llvm-project/issues/188201

---------

Co-authored-by: Phoebe Wang <phoebe.wang at intel.com>
DeltaFile
+79-0llvm/test/CodeGen/X86/half-fneg-fabs.ll
+14-4llvm/lib/Target/X86/X86ISelLowering.cpp
+93-42 files

LLVM/project 28faaffllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

[AMDGPU] DPP wave reduction for long types - 3

Supported Ops: `and`, `or`, `xor`
DeltaFile
+984-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+12-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,916-3494 files

LLVM/project 00f35a1llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] DPP wave reduction for long types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,113-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,079-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+72-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,264-3083 files

LLVM/project a455799llvm/test/CodeGen/AMDGPU frem.ll llvm.minimum.f16.ll

AMDGPU: Use SmallSet for VOPD scalar reg tracking

Use SmallSet instead of SmallVector for UniqueScalarRegs.
VCC_LO was pushed without uniqueness check, so when both
components used VCC implicitly it was counted twice,
rejecting valid VOPD pairings.

Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
DeltaFile
+38-41llvm/test/CodeGen/AMDGPU/frem.ll
+23-25llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
+23-25llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
+13-14llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
+13-14llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
+8-11llvm/test/CodeGen/AMDGPU/fmed3.ll
+118-1308 files not shown
+153-17014 files

OPNSense/core e67ea61src/opnsense/www/js opnsense_bootgrid.js

bootgrid: limit maintaining scroll position to inplace=true, continuation of 75e60e8

This shouldn't be the default behavior, as a "refresh" would also
maintain scrolling position.
DeltaFile
+3-3src/opnsense/www/js/opnsense_bootgrid.js
+3-31 files

LLVM/project 6b3d04cllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.max.ll llvm.amdgcn.reduce.min.ll

[AMDGPU] DPP wave reduction for long types - 1

Supported Ops: `min`, `max`, `umin`, `umax`
DeltaFile
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+185-43llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4,441-4755 files

OPNSense/core 7c8bda9src/opnsense/scripts/wireguard wg-service-control.php

wireguard: sprint clean related to #10094
DeltaFile
+19-18src/opnsense/scripts/wireguard/wg-service-control.php
+19-181 files

LLVM/project 4259dc2llvm/lib/Target/AMDGPU SIISelLowering.cpp

Use MachineInstrBuilder instead of BuildMI.
Return registers by value rather than MachineOperands.
Minor Code Cleanup/ Refactoring.
DeltaFile
+63-54llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+63-541 files

LLVM/project b12d54dllvm/lib/Transforms/Scalar LoopIdiomRecognize.cpp, llvm/test/Transforms/LoopIdiom non-integral-pointers.ll

[CHERI] Refine LoopIdiomRecognize handling of stable representation non-integral pointers. (#189402)

This makes two changes:
- memset can be formed from stores of null pointers, even if they are
non-integral. Null pointers are already assumed to be equivalent to the
all-zeros bit pattern, and it's not the goal of non-integral pointer
support to change that assumption.
- memcpy can be formed from copies of non-integral pointers. We assume
if the environment provides a memcpy implementation for a non-integral
pointer address space, then that memcpy is non-integral pointer aware.

These changes are not applied to pointers with unstable representation.
DeltaFile
+104-8llvm/test/Transforms/LoopIdiom/non-integral-pointers.ll
+15-5llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
+119-132 files

LLVM/project d4a20e7libc/src/__support/OSUtil/linux/syscall_wrappers connect.h CMakeLists.txt, libc/src/sys/socket connect.h

[libc] Implement connect(2) on linux (#189668)

I'm using the new syscall wrapper framework, and enabling the entry
point for x86_64, aarch64 and riscv. The associated test currently only
checks for the error code. Once we have listen&accept (which I'm
probably going to tackle next), we can test that the two can talk to
each other.
DeltaFile
+68-0libc/test/src/sys/socket/linux/connect_test.cpp
+48-0libc/src/__support/OSUtil/linux/syscall_wrappers/connect.h
+31-0libc/src/sys/socket/linux/connect.cpp
+23-0libc/src/sys/socket/connect.h
+20-0libc/test/src/sys/socket/linux/CMakeLists.txt
+15-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+205-05 files not shown
+229-011 files

LLVM/project 5c6ad65flang/lib/Optimizer/Transforms StackArrays.cpp, flang/test/Transforms stack-arrays-block-cfg-scope.fir stack-arrays-nested-scope.fir

[flang] Fix stack-arrays pass moving alloca across stackrestore scope (#184727)

When a operand is shared between two fir.allocmem ops in different
stacksave/stackrestore scopes, findAllocaInsertionPoint() placed both
allocas at the operand definition site inside the first scope. The first
stackrestore then reclaimed both, leaving the second call with a
dangling pointer.

Add a check for intervening stackrestore ops between the last operand
and the allocmem. If one is found, fall back to the allocmem's own
location, matching the existing bail-out for cross-block operands.

Fixes: https://github.com/llvm/llvm-project/issues/178812
DeltaFile
+42-0flang/test/Transforms/stack-arrays-block-cfg-scope.fir
+41-0flang/test/Transforms/stack-arrays-nested-scope.fir
+37-1flang/lib/Optimizer/Transforms/StackArrays.cpp
+33-0flang/test/Transforms/stack-arrays-scope.f90
+153-14 files

LLVM/project ded0088llvm/lib/Target/AArch64 AArch64InstrInfo.td

Improve a comment with better explanation
DeltaFile
+4-2llvm/lib/Target/AArch64/AArch64InstrInfo.td
+4-21 files

LLVM/project d662f9fllvm/lib/Target/AArch64 AArch64InstrInfo.cpp AArch64PrologueEpilogue.cpp, llvm/test/CodeGen/AArch64 sign-return-address-pauthlr-slh.ll

[AArch64] Mark X16 as clobbered in PAUTH_EPILOGUE for hint-based PAuthLR

When users request branch protection with PAuthLR on targets that do not
support the PAuthLR instructions, the PAUTH_EPILOGUE falls back to using
hint-space instructions. This fallback sequence uses X16 as a temporary
register, but X16 was not listed in the clobber set.

Because Speculative Load Hardening uses X16, this omission made SLH
incompatible with this PAUTH_EPILOGUE path.

Mark X16 as clobbered so the compiler does not assume X16 is preserved across
the epilogue, restoring compatibility with Speculative Load Hardening and
avoiding incorrect register liveness assumptions. The clobber is added in C++
rather than TableGen, as X16 is only clobbered when PAuthLR is requested as a
branch protection variation and should not be treated as clobbered
unconditionally.
DeltaFile
+103-0llvm/test/CodeGen/AArch64/sign-return-address-pauthlr-slh.ll
+13-3llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+2-5llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
+6-0llvm/lib/Target/AArch64/AArch64InstrInfo.h
+1-2llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+3-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+128-106 files

LLVM/project 33c23d5llvm/lib/Target/AArch64 AArch64InstrInfo.cpp

Remove assert
DeltaFile
+0-1llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+0-11 files

FreeBSD/ports bcdb07dnet-p2p/bazarr pkg-plist distinfo

net-p2p/bazarr: Update 1.5.4 => 1.5.6

Changelog:
https://github.com/morpheus65535/bazarr/releases/tag/v1.5.5
https://github.com/morpheus65535/bazarr/releases/tag/v1.5.6

PR:             294291
Security:       CVE-2024-40348
Sponsored by:   UNIS Labs
MFH:            2026Q2

(cherry picked from commit 24aae72732b36e6de66728afea00dc27ffc46000)
DeltaFile
+9-12net-p2p/bazarr/pkg-plist
+3-3net-p2p/bazarr/distinfo
+1-1net-p2p/bazarr/Makefile
+13-163 files

OpenBSD/src gj6emcqsys/arch/riscv64/dev smtcomphy.c

   Add PCIe PHY support.

   ok mlarkin@, deraadt@
VersionDeltaFile
1.2+107-4sys/arch/riscv64/dev/smtcomphy.c
+107-41 files

OpenBSD/src 01b5MNlsys/arch/riscv64/dev smtclock.c

   Add a few more PCIe related clocks and resets.

   ok mlarkin@, deraadt@
VersionDeltaFile
1.3+25-1sys/arch/riscv64/dev/smtclock.c
+25-11 files

NetBSD/pkgsrc-wip 7a3b417emacs-git PLIST

emacs-git: update PLIST
DeltaFile
+2-0emacs-git/PLIST
+2-01 files

FreeBSD/ports 24aae72net-p2p/bazarr pkg-plist distinfo

net-p2p/bazarr: Update 1.5.4 => 1.5.6

Changelog:
https://github.com/morpheus65535/bazarr/releases/tag/v1.5.5
https://github.com/morpheus65535/bazarr/releases/tag/v1.5.6

PR:             294291
Security:       CVE-2024-40348
Sponsored by:   UNIS Labs
MFH:            2026Q2
DeltaFile
+9-12net-p2p/bazarr/pkg-plist
+3-3net-p2p/bazarr/distinfo
+1-2net-p2p/bazarr/Makefile
+13-173 files

OPNSense/core 78c691fsrc/opnsense/www/js opnsense_bootgrid.js

bootgrid: maintain scrolling position for both datatree and command actions. Closes https://github.com/opnsense/core/issues/9151

The usage of scrollToRow has been considered, but this contains
too much magic causing all kinds of jumps in scroll position,
causing a user to lose track of the changes they made. The only
downside to this is that when a datatree is expanded at the bottom
of a grid, the associated rows aren't immediately visible until
manually scrolled to.

(cherry picked from commit 75e60e85194e7f2bf7e20e3891743ce801e05820)
DeltaFile
+14-2src/opnsense/www/js/opnsense_bootgrid.js
+14-21 files

OPNSense/core d6f9433src/opnsense/www/js/widgets Disk.js Memory.js

dashboard:gauge improvements (#10063)

Closes: #8356

*Makes the disk widget become table/bars from grid 2 size onwards
*Adds disk free/used size on the gauge
*Removes parentheses from the memory widget

---------

Co-authored-by: Fabian Rodriguez <317514+MagicFab at users.noreply.github.com>
(cherry picked from commit 7f3bcf5b787145b7cf185854758c3cddefdf1971)
DeltaFile
+13-1src/opnsense/www/js/widgets/Disk.js
+1-1src/opnsense/www/js/widgets/Memory.js
+14-22 files

OPNSense/core 0e999ccsrc/opnsense/mvc/app/views/layout_partials base_apply_button.volt, src/opnsense/www/js opnsense_bootgrid.js

bootgrid: automatic grid height calculation (#10011)

(cherry picked from commit 40a6243a3183dbba563aa551b45f9e237f95efd1)
(cherry picked from commit 2edab3dbff3ee07a1439429b6963a71bf708687e)
(cherry picked from commit 92fa22970b40789fa7479222213cf9cfcfd744f1)
DeltaFile
+71-50src/opnsense/www/js/opnsense_bootgrid.js
+0-4src/opnsense/www/themes/opnsense-dark/build/css/main.css
+0-4src/opnsense/www/themes/opnsense/build/css/main.css
+1-1src/opnsense/mvc/app/views/layout_partials/base_apply_button.volt
+72-594 files