LLVM/project 30969cclldb/test/API/tools/lldb-dap/stopped-events TestDAP_stopped_events.py

[lldb] Fix logic issue in TestDAP_stopped_events.py (#183382)

The subset should actually be the expected data because the real thread
data may have additional information.
DeltaFile
+1-1lldb/test/API/tools/lldb-dap/stopped-events/TestDAP_stopped_events.py
+1-11 files

FreeNAS/freenas ead01aetests/api2 test_300_nfs.py test_200_ftp.py

test
DeltaFile
+0-2,224tests/api2/test_300_nfs.py
+0-1,411tests/api2/test_200_ftp.py
+0-936tests/api2/test_345_acl_nfs4.py
+0-700tests/api2/test_011_user.py
+0-565tests/api2/test_audit_websocket.py
+0-495tests/api2/test_440_snmp.py
+0-6,331243 files not shown
+0-31,085249 files

FreeNAS/freenas c059890src/middlewared/middlewared/plugins/pool_ dataset_encryption_info.py

pass bytes in `pool.dataset.sync_db_keys`
DeltaFile
+10-2src/middlewared/middlewared/plugins/pool_/dataset_encryption_info.py
+10-21 files

FreeNAS/freenas c9c9bcdsrc/middlewared/middlewared/plugins/update_ utils.py

NAS-139992 / 26.0.0-BETA.1 / New update server (#18302)

DeltaFile
+1-1src/middlewared/middlewared/plugins/update_/utils.py
+1-11 files

FreeNAS/freenas b3f69cesrc/middlewared/middlewared/api/v26_0_0 webui_main_dashboard.py, src/middlewared/middlewared/plugins/apps logs.py

Merge branch 'master' of https://github.com/truenas/middleware into NAS-139874-test
DeltaFile
+133-78tests/stig/test_03_stig_auditing.py
+9-4src/middlewared/middlewared/plugins/pool_/dataset_encryption_lock.py
+4-2src/middlewared/middlewared/api/v26_0_0/webui_main_dashboard.py
+4-1src/middlewared/middlewared/plugins/apps/logs.py
+3-1tests/api2/test_001_ssh.py
+2-2tests/api2/test_006_pool_and_sysds.py
+155-888 files not shown
+160-9514 files

LLVM/project 642763cmlir/lib/Dialect/AMDGPU/Transforms FoldMemRefsOps.cpp, mlir/test/Dialect/AMDGPU amdgpu-fold-memrefs.mlir

[AMDGPU] Adding FoldMemRefOpsIntoTransposeLoadOp pattern (#183330)

Before the fix we wouldn't fold a trivial expand_shape as index
computation. This will later force expand_shape to materialize into a
extract_stride_metadata and a reinterpret_cast unnecessarily. The
example below showcase the motivation of a source IR that won't be able
to fold today.

```mlir
%expanded = memref.expand_shape %buf [[0, 1], [2, 3]]
    : memref<32x128xf16, strided<[128, 1], offset: ?>, #gpu.address_space<workgroup>>
    into memref<1x32x8x16xf16, strided<..., offset: ?>, #gpu.address_space<workgroup>>
amdgpu.transpose_load %expanded[%i, %j, %k, %l]
    : memref<1x32x8x16xf16, ...> -> vector<4xf16>
```

With this pattern that matches the more generic
`FoldMemRefAliasOpsPass`, the expand_shape can now fold into
transpose_load op like other load/stores.

    [4 lines not shown]
DeltaFile
+103-0mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
+23-2mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
+126-22 files

LLVM/project 3031ba9llvm/lib/CodeGen ExpandIRInsts.cpp, llvm/test/CodeGen/AMDGPU div_v2i128.ll div_i128.ll

[CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts. (#180654)

Previously, power-of-2 div/rem operations wider than
MaxLegalDivRemBitWidth were excluded from IR expansion and left for
backend peephole optimizations. Some backends can fail to process such
instructions in case we switch off DAGCombiner.

Now ExpandIRInsts expands them into shift/mask sequences:
- udiv X, 2^C  ->  lshr X, C
- urem X, 2^C  ->  and X, (2^C - 1)
- sdiv X, 2^C  ->  bias adjustment + ashr X, C
- srem X, 2^C  ->  X - (((X + Bias) >> C) << C)

Special cases handled:
- Division/remainder by 1 or -1 (identity, negation, or zero)
- Exact division (sdiv exact skips bias, produces ashr exact)
- Negative power-of-2 divisors (result is negated)
- INT_MIN divisor (correct via countr_zero on bit pattern)


    [2 lines not shown]
DeltaFile
+69-1,283llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+255-0llvm/test/Transforms/ExpandIRInsts/X86/divrem-pow2.ll
+57-95llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
+116-9llvm/lib/CodeGen/ExpandIRInsts.cpp
+44-60llvm/test/CodeGen/AMDGPU/div_i128.ll
+34-27llvm/test/CodeGen/AMDGPU/rem_i128.ll
+575-1,4742 files not shown
+579-1,4788 files

LLVM/project 5cd6bb0clang/lib/Driver ModulesDriver.cpp

[Clang][Modules] Fix -Wunused-variable from #182182

https://lab.llvm.org/staging/#/builders/227/builds/1093
DeltaFile
+1-1clang/lib/Driver/ModulesDriver.cpp
+1-11 files

LLVM/project fd1ffdbllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 faddv-fp16.ll faddv.ll

Address comments 1

Removed:
Flags.setNoSignedZeros(true);

Because technically the produced result can be a signed zero, it just
does not matter.
DeltaFile
+48-24llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+54-0llvm/test/CodeGen/AArch64/faddv-fp16.ll
+45-0llvm/test/CodeGen/AArch64/faddv.ll
+2-3llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
+149-274 files

LLVM/project 414c666llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 faddv.ll

[AArch64] Decompose FADD reductions with known zero elements

FADDV is matched into FADDPv4f32 + FADDPv2f32p but this can be relaxed
when one element (usually the 4th) or more are known to be zero.

Before:
movi d1, #0000000000000000
mov v0.s[3], v1.s[0]
faddp v0.4s, v0.4s, v0.4s
faddp s0, v0.2s

After:
mov s1, v0.s[2]
faddp s0, v0.2s
fadd s0, s0, s1
DeltaFile
+256-0llvm/test/CodeGen/AArch64/faddv.ll
+101-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+357-02 files

FreeBSD/ports e3f5fcbgraphics/converseen distinfo Makefile

graphics/converseen: Update to 0.15.2.0

ChangeLog: https://converseen.fasterland.net/changelog/

 * Fixed conversion and resolution issues with certain formats
 * Fixed a potential issue with file paths
 * Corrected a typo in the main window
 * Updated Italian translation
 * Various Bugfixes
DeltaFile
+3-3graphics/converseen/distinfo
+1-1graphics/converseen/Makefile
+4-42 files

LLVM/project b7ce37cllvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 arm64-cvt-simd-intrinsics.ll sve-fixed-vector-lrint.ll

Revert "[AArch64] Wrap integer SCALAR_TO_VECTOR nodes in bitcasts  (#172837)" (#183380)

This reverts commit eff183b6a7e351e10444977fc2110edc2a518e6f.

And followup commit commit 87d9dad579b9d947f6181d1736fb11e8f683e246.

Causes breakages, see
https://github.com/llvm/llvm-project/pull/172837#issuecomment-3961532435.
DeltaFile
+1-1,205llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
+533-499llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+277-246llvm/test/CodeGen/AArch64/vector-lrint.ll
+187-172llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+72-68llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
+32-47llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1,102-2,23726 files not shown
+1,366-2,53332 files

LLVM/project 4a8d532clang/docs ClangIRCleanupAndEHDesign.md, clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR] Update cir::ResumeOp to require an EH token (#183192)

This updates the cir::ResumeOp operation to require an EH token operand.
We already had the token available at both locations where the operation
was being created. Adding this operand makes finding the token more
robust during CFG flattening.

This change was entirely AI generated, but I have reviewed it closely.
DeltaFile
+11-9clang/include/clang/CIR/Dialect/IR/CIROps.td
+7-7clang/test/CIR/Transforms/flatten-cleanup-scope-eh.cir
+5-5clang/docs/ClangIRCleanupAndEHDesign.md
+4-4clang/test/CIR/IR/invalid-eh-flat.cir
+6-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+3-3clang/test/CIR/CodeGen/try-catch-tmp.cpp
+36-285 files not shown
+46-3711 files

NetBSD/pkgsrc dO2dxQ5devel/nss distinfo, devel/nss/patches patch-me

   nss: try fixing Solaris build using upstream suggestion
VersionDeltaFile
1.10+15-3devel/nss/patches/patch-me
1.206+3-3devel/nss/distinfo
+18-62 files

NetBSD/pkgsrc pi5gNFAdevel/nss/patches patch-md

   nss: regen patch
VersionDeltaFile
1.4+7-7devel/nss/patches/patch-md
+7-71 files

LLVM/project 33fd75fllvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU GCNProcessors.td

[AMDGPU] Add gfx12-5-generic subtarget (#183381)

This is functionally equivalent to gfx1250.
DeltaFile
+7-0llvm/docs/AMDGPUUsage.rst
+7-0llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
+5-0llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+5-0llvm/lib/Target/AMDGPU/GCNProcessors.td
+5-0llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
+4-0llvm/lib/TargetParser/TargetParser.cpp
+33-019 files not shown
+65-225 files

LLVM/project 9f46362offload/liboffload/src OffloadImpl.cpp

[Offload] Fix type mismatch by using `uint64_t` instead of `size_t` (#183375)

The variant uses uint64_t, so should the get.
DeltaFile
+3-2offload/liboffload/src/OffloadImpl.cpp
+3-21 files

LLVM/project af2b6edflang/lib/Lower/OpenMP ClauseProcessor.cpp, flang/test/Lower/OpenMP ordered-simd.f90

[flang][openmp] Add support for ordered regions in SIMD directives (#… (#183379)

Add support for ordered regions within SIMD directives (!$omp simd
ordered and !$omp do simd ordered). This initial implementation matches
Clang's behavior.

In SIMD directives, loop induction variables have an implicit linear
clause with deferred store semantics (storing to .linear_result). To
properly support ordered regions, the LinearClauseProcessor rewrites
variable references to use .linear_result in:
- omp.ordered.region: Code inside ordered blocks
- omp_region.finalize: Code after ordered blocks

Note: The vectorizer cannot currently vectorize loops with ordered
regions. Future enhancement would require generating lane loops or
unrolling ordered regions across SIMD lanes while maintaining ordering
semantics.

This PR is a reland for https://github.com/llvm/llvm-project/pull/181012
and fixes the regression caused by syntax change in IR for linear clause
DeltaFile
+90-0mlir/test/Target/LLVMIR/openmp-wsloop-simd-ordered.mlir
+87-0mlir/test/Target/LLVMIR/openmp-simd-ordered.mlir
+57-0flang/test/Lower/OpenMP/ordered-simd.f90
+18-6mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+0-11mlir/test/Target/LLVMIR/openmp-todo.mlir
+5-0flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+257-172 files not shown
+259-188 files

FreeBSD/ports 3a9d2abcad/ngspice_rework/files patch-src_include_cppduals_duals_dual

cad/ngspice_rework: fix build with libc++ 21

With libc++ 21 cad/ngspice_rework fails to build, with errors similar to:

    In file included from hicumL2temp.cpp:11:
    ../../../../src/include/cppduals/duals/dual:444:8: error: 'is_compound' cannot be specialized: Users are not allowed to specialize this standard library entity [-Winvalid-specialization]
      444 | struct is_compound<duals::dual<T>> : true_type {};
          |        ^
    /usr/include/c++/v1/__type_traits/is_compound.h:25:8: note: marked '_Clang::no_specializations' here
       25 | struct _LIBCPP_NO_SPECIALIZATIONS is_compound : _BoolConstant<__is_compound(_Tp)> {};
          |        ^
    /usr/include/c++/v1/__config:1167:9: note: expanded from macro '_LIBCPP_NO_SPECIALIZATIONS'
     1167 |       [[_Clang::__no_specializations__("Users are not allowed to specialize this standard library entity")]]
          |         ^

This is because libc++ 21 no longer allows specializing a number of
standard library entities. Delete out the specialization to make the
build complete.


    [5 lines not shown]
DeltaFile
+13-0cad/ngspice_rework/files/patch-src_include_cppduals_duals_dual
+13-01 files

FreeBSD/ports c6266b2cad/ngspice_rework/files patch-src_include_cppduals_duals_dual

cad/ngspice_rework: fix build with libc++ 21

With libc++ 21 cad/ngspice_rework fails to build, with errors similar to:

    In file included from hicumL2temp.cpp:11:
    ../../../../src/include/cppduals/duals/dual:444:8: error: 'is_compound' cannot be specialized: Users are not allowed to specialize this standard library entity [-Winvalid-specialization]
      444 | struct is_compound<duals::dual<T>> : true_type {};
          |        ^
    /usr/include/c++/v1/__type_traits/is_compound.h:25:8: note: marked '_Clang::no_specializations' here
       25 | struct _LIBCPP_NO_SPECIALIZATIONS is_compound : _BoolConstant<__is_compound(_Tp)> {};
          |        ^
    /usr/include/c++/v1/__config:1167:9: note: expanded from macro '_LIBCPP_NO_SPECIALIZATIONS'
     1167 |       [[_Clang::__no_specializations__("Users are not allowed to specialize this standard library entity")]]
          |         ^

This is because libc++ 21 no longer allows specializing a number of
standard library entities. Delete out the specialization to make the
build complete.


    [3 lines not shown]
DeltaFile
+13-0cad/ngspice_rework/files/patch-src_include_cppduals_duals_dual
+13-01 files

LLVM/project 2981f5fllvm/test/CodeGen/Generic shadow-stack-gc-lowering.ll

[CodeGen] Add tests for ShadowStackGCLowering IR pass (#183167)

Add llvm/test/CodeGen/Generic/shadow-stack-gc-lowering.ll testing the
opt-level behavior of the shadow-stack-gc-lowering module pass,
covering:
- Single root: frame push/pop at entry and return
- Two roots: multi-slot frame, NumRoots=2/NumMeta=0 in the frame map
- Root with non-null metadata: NumMeta=1, metadata array in gc_map
- Mixed metadata: CollectRoots ordering (metadata roots sorted first)
- No roots: pass must leave the function unchanged
- Invoke: EscapeEnumerator inserts pop on both normal and unwind exits

As requested in https://github.com/llvm/llvm-project/pull/178436, since
the only existing tests seem to be that llc doesn't crash (in
llvm/test/CodeGen/X86/GC)

Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+194-0llvm/test/CodeGen/Generic/shadow-stack-gc-lowering.ll
+194-01 files

LLVM/project 66ca3ebllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 faddv-fp16.ll faddv.ll

Address comments 1

Removed:
Flags.setNoSignedZeros(true);

Because technically the produced result can be a signed zero, it just
does not matter.
DeltaFile
+49-24llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+54-0llvm/test/CodeGen/AArch64/faddv-fp16.ll
+45-0llvm/test/CodeGen/AArch64/faddv.ll
+2-3llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
+150-274 files

OpenZFS/src f3d4c79config kernel-fst-mount.m4 kernel-fs-context.m4, module/os/linux/zfs zpl_super.c

zpl_super: prefer "new" mount API when available

This API has been available since kernel 5.2, and having it available
(almost) everywhere should give us a lot more flexibility for mount
management in the future.

Sponsored-by: TrueNAS
Reviewed-by: Tony Hutter <hutter2 at llnl.gov>
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Rob Norris <rob.norris at truenas.com>
Closes #18260
DeltaFile
+0-36config/kernel-fst-mount.m4
+33-0config/kernel-fs-context.m4
+12-15module/os/linux/zfs/zpl_super.c
+2-2config/kernel.m4
+47-534 files

ELF Tool Chain/elftoolchain 4327trunk/libelftc elftc_get_program_name.c Makefile

libelftc: add a convenience API to get the current program name.

This API is intend to replace the ELFTC_GETPROGNAME() macro.
DeltaFile
+49-0trunk/libelftc/elftc_get_program_name.c
+1-0trunk/libelftc/Makefile
+1-0trunk/libelftc/libelftc.h
+51-03 files

FreeBSD/src 8ae3f44lib/libc/stdlib system.c, lib/libc/tests/stdlib system_test.c

system(3): Fix null case

Our manual page states that if given a null pointer, system() returns
non-zero if the shell is available and zero if it is not.  This is
consistent with the C standard's description of system(), but it is not
what we actually do.  What we actually do is always return non-zero, as
required by POSIX.

As the POSIX rationale explains, implementing the logic required by the
C standard does not violate POSIX, since a conforming system always has
a shell, therefore the logic will always return non-zero.

Since our libc is commonly used in non-conforming situations such as
chroots or thin jails, we should implement the full logic required by
the C standard.

MFC after:      1 week
Sponsored by:   Klara, Inc.
Reviewed by:    obiwac, bnovkov, kevans
Differential Revision:  https://reviews.freebsd.org/D55484
DeltaFile
+10-0lib/libc/tests/stdlib/system_test.c
+1-1lib/libc/stdlib/system.c
+11-12 files

FreeBSD/src 7305604lib/libc/stdlib system.3

system(3): Clarify return values

Our manual page currently states that system() will return 127 if it
fails to execute the shell.  The actual return value is, to quote POSIX,
“as if the command language interpreter had terminated using exit(127)
or _exit(127)”.

MFC after:      1 week
Sponsored by:   Klara, Inc.
Reviewed by:    bnovkov, kevans
Differential Revision:  https://reviews.freebsd.org/D55483
DeltaFile
+5-3lib/libc/stdlib/system.3
+5-31 files

FreeBSD/src 7a1ade5lib/libc/tests/stdlib system_test.c Makefile

system(3): Write our own tests

Replace the somewhat perfunctory NetBSD tests with our own.

MFC after:      1 week
Sponsored by:   Klara, Inc.
Reviewed by:    bnovkov, kevans
Differential Revision:  https://reviews.freebsd.org/D55482
DeltaFile
+164-0lib/libc/tests/stdlib/system_test.c
+2-1lib/libc/tests/stdlib/Makefile
+166-12 files

FreeBSD/src 6e589e6lib/libc/stdlib system.c

system(3): Improve signal handling

Ignore SIGINT and SIGQUIT and block SIGCHLD, as POSIX requires.

To deal with the concurrency problem described in POSIX, we keep track
of the count of concurrent invocations.  We ignore and block signals
only when the counter was zero before we incremented it, and restore
them only when the counter reaches zero after we decrement it.

Note that this does not address the issue of thread cancellation.

MFC after:      1 week
Sponsored by:   Klara, Inc.
Reviewed by:    bnovkov, sef, kevans
Differential Revision:  https://reviews.freebsd.org/D55471
DeltaFile
+76-46lib/libc/stdlib/system.c
+76-461 files

LLVM/project 2d108ffllvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c
DeltaFile
+67-67llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+33-0llvm/lib/MC/MCDwarf.cpp
+15-15llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+10-0llvm/lib/CodeGen/MachineFunction.cpp
+4-4llvm/test/CodeGen/AMDGPU/debug-frame.ll
+4-0llvm/include/llvm/CodeGen/MachineFunction.h
+133-864 files not shown
+141-8810 files

LLVM/project 2ac7c3fllvm/lib/Target/AMDGPU SIFrameLowering.cpp SIMachineFunctionInfo.h, llvm/test/CodeGen/AMDGPU amdgpu-spill-cfi-saved-regs.ll

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
DeltaFile
+2,998-0llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
+37-12llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+11-2llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+9-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+7-0llvm/lib/Target/AMDGPU/SIFrameLowering.h
+2-1llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+3,064-152 files not shown
+3,067-168 files