LLVM/project a9605a9clang-tools-extra/clangd Diagnostics.cpp Diagnostics.h, clang-tools-extra/clangd/unittests ConfigCompileTests.cpp DiagnosticsTests.cpp

[clangd] Support suppressions for driver diagnostics (#182912)

Rebase of https://reviews.llvm.org/D127844
Fixes [#1142](https://github.com/clangd/clangd/issues/1142)
DeltaFile
+37-27clang-tools-extra/clangd/Diagnostics.cpp
+0-37clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp
+21-0clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
+15-0clang-tools-extra/clangd/unittests/CompilerTests.cpp
+2-6clang-tools-extra/clangd/Diagnostics.h
+0-5clang-tools-extra/clangd/ParsedAST.cpp
+75-751 files not shown
+75-807 files

LLVM/project e3b6c61llvm/lib/Target/LoongArch LoongArchLASXInstrInfo.td LoongArchLSXInstrInfo.td, llvm/test/CodeGen/LoongArch/lsx remat.ll

[LoongArch] Mark VREPLGR2VR/XVREPLGR2VR as re-materializable

The VREPLGR2VR and XVREPLGR2VR instruction families replicate a
scalar general-purpose register value into all elements of a vector
register. These instructions are side-effect free and relatively
cheap, with their result depending only on the input register.

Mark them as isReMaterializable to allow the register allocator to
recompute the value when profitable instead of spilling and reloading
it from memory.

This can help reduce register pressure and avoid unnecessary memory
traffic in vectorized code.
DeltaFile
+10-14llvm/test/CodeGen/LoongArch/lsx/remat.ll
+2-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+2-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+14-143 files

LLVM/project 81ecd00llvm/lib/Target/AMDGPU VOP3PInstructions.td SIFoldOperands.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h

AMDGPU: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3

Codegen for v_dual_dot2acc_f32_f16/bf16 for targets that only have VOP3
version of the instruction.
Since there is no VOP2 version, instroduce temporary mir DOT2ACC pseudo
that is selected when there are no src_modifiers. This DOT2ACC pseudo
has src2 tied to dst (like the VOP2 version), PostRA pseudo expansion will
restore pseudo to VOP3 version of the instruction.
CreateVOPD will recoginize such VOP3 pseudo and generate v_dual_dot2acc.
DeltaFile
+170-312llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+96-95llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+31-4llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+21-8llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+27-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+16-1llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+361-4204 files not shown
+380-42210 files

LLVM/project 9e6266cllvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp VOP2Instructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.fdot2.ll llvm.amdgcn.fdot2.f32.bf16.ll

AMDGPU: Improve codegen for VOP2 v_dot2c_f32_f16/bf16

Select VOP2 version when there are no src_modifers, otherwise VOP3.
DeltaFile
+64-212llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+20-48llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+41-9llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+14-12llvm/lib/Target/AMDGPU/VOP2Instructions.td
+22-0llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+8-0llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+169-2813 files not shown
+178-2819 files

LLVM/project 1fde846llvm/test/CodeGen/LoongArch/lsx remat.ll

[LoongArch] Add tests for VREPLGR2VR/XVREPLGR2VR rematerialization
DeltaFile
+43-0llvm/test/CodeGen/LoongArch/lsx/remat.ll
+43-01 files

LLVM/project e42fd5ellvm/lib/Target/AMDGPU VOP3PInstructions.td AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.fdot2.ll llvm.amdgcn.fdot2.f32.bf16.ll

AMDGPU: Fix src2_modifiers for v_dot2_f32_f16/bf16
DeltaFile
+14-21llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+23-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+16-0llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+6-9llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+9-0llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+4-2llvm/lib/Target/AMDGPU/VOPInstructions.td
+72-374 files not shown
+81-3710 files

LLVM/project 4186bcdllvm/test/CodeGen/AMDGPU llvm.amdgcn.fdot2.ll llvm.amdgcn.fdot2.f32.bf16.ll

AMDGPU: Add more tests for v_dot2_f32_f16/bf16

Test for src modifiers, inline constants and vopd codegen.
DeltaFile
+1,769-45llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+944-116llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+2,713-1612 files

LLVM/project 5d427d9flang/include/flang/Parser message.h

[flang] Add const-qualified version of parser::Messages::messages()
DeltaFile
+1-0flang/include/flang/Parser/message.h
+1-01 files

LLVM/project 0a5e51dllvm/test/CodeGen/AMDGPU dynamic_stackalloc.ll llvm.amdgcn.reduce.sub.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshr.ll

Merge branch 'main' into users/kparzysz/e11-use-ods-for-queries
DeltaFile
+2,113-1,374llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+1,412-1,169llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1,096-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,047-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+968-165llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+968-165llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+7,604-3,1611,158 files not shown
+28,779-9,9711,164 files

LLVM/project bbb8ab5llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.cpp

[AArch64][GlobalISel] Add patterns for scalar sqdmlal/sqdmlsl
DeltaFile
+8-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1-0llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+9-02 files

LLVM/project fd47fbelldb/test/API/lang/cpp/incomplete-types Makefile

[lldb] Do not use mkdir -p in makefile on Windows (#187244)

`Make` uses systems's `mkdir` on Windows even if Git's mkdir.exe is
present in PATH. Windows's mkdir does not support the parameter `-p` and
creates the directory `-p` instead. Few other tests also use `mkdir -p`
but they are linux, objc or macosx related.

---------

Co-authored-by: Charles Zablit <c_zablit at apple.com>
DeltaFile
+1-1lldb/test/API/lang/cpp/incomplete-types/Makefile
+1-11 files

LLVM/project cf89c33clang/lib/Sema SemaOpenMP.cpp, clang/test/OpenMP map_const_aggregate.cpp

[OpenMP] Map const-qualified target map variables as 'to'. (#185918)

This patch updates the mapping kind for const-qualified variables
from`tofrom` to `to`, ensuring correct and standards-compliant mapping
semantics for const variables.
DeltaFile
+246-0clang/test/OpenMP/map_const_aggregate.cpp
+50-4clang/lib/Sema/SemaOpenMP.cpp
+296-42 files

FreeBSD/ports 51e4c9aaudio/subtui distinfo Makefile

audio/subtui: Update to 2.12.2

Changelogs:
  - 2.12.2: https://github.com/MattiaPun/SubTUI/releases/tag/v2.12.2
  - 2.12.1: https://github.com/MattiaPun/SubTUI/releases/tag/v2.12.1
  - 2.12.0: https://github.com/MattiaPun/SubTUI/releases/tag/v2.12.0
DeltaFile
+5-5audio/subtui/distinfo
+1-1audio/subtui/Makefile
+6-62 files

LLVM/project c949c9bllvm/lib/Target/AArch64 AArch64InstrFormats.td, llvm/test/MC/Disassembler/AArch64 reserved-bits-softfail.txt

[AArch64][llvm] Make SBZ/SBO insns warn not fail when disassembling (#187068)

Some instructions in the Arm ARM have bits which are marked as "Should
Be One" or "Should Be Zero", and they're marked as "Constrained
Unpredictable" as to what should happen if they're not.

This is to improve hardware decode efficiency. In all the cases where
this occurs, it's an instruction which in all other respects is closely
related to an adjacent instruction in the encoding space (for example a
similar load or store) but doesn't require one of the variable fields,
usually a register field. These fields are then defined as SBZ or SBO.

If one of these instructions didn't have the bits set to SBZ or SBO,
then the instruction would fail to disassemble. We had missed adding
`Unpredictable` to a few of these, and they would fail rather than
warn.

Update these AArch64 instructions to treat `Unpredictable` bitfields as
soft-fails with a warning, and add a comprehensive disassembler

    [9 lines not shown]
DeltaFile
+563-0llvm/test/MC/Disassembler/AArch64/reserved-bits-softfail.txt
+6-0llvm/lib/Target/AArch64/AArch64InstrFormats.td
+569-02 files

LLVM/project 2563006clang/lib/CodeGen CGCleanup.cpp CodeGenFunction.cpp

[Clang][NFC] Drop uses of BranchInst (#187242)
DeltaFile
+20-20clang/lib/CodeGen/CGCleanup.cpp
+3-4clang/lib/CodeGen/CodeGenFunction.cpp
+2-5clang/lib/CodeGen/CGException.cpp
+3-3clang/lib/CodeGen/CGStmt.cpp
+1-1clang/lib/CodeGen/EHScopeStack.h
+1-1clang/lib/CodeGen/CGExpr.cpp
+30-341 files not shown
+31-357 files

LLVM/project f1b82dcutils/bazel/llvm-project-overlay/clang BUILD.bazel, utils/bazel/llvm-project-overlay/clang/unittests BUILD.bazel

[Bazel] Fixes c1f6fd2 (#187146)

This fixes c1f6fd24aa637d6aadb72aa08bf3d8a14c961ed2.
DeltaFile
+15-0utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
+16-02 files

LLVM/project f52b261mlir/test/Integration/Dialect/Vector/CPU gather.mlir

[mlir][vector] Use non-native runner in gather.mlir test (#187243)

Fix after https://github.com/llvm/llvm-project/pull/187071
DeltaFile
+1-1mlir/test/Integration/Dialect/Vector/CPU/gather.mlir
+1-11 files

LLVM/project 3f649d0llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64SVEInstrInfo.td, llvm/test/CodeGen/AArch64 f16f32dot-fixed-length-fdot.ll sve2p1-fixed-length-fdot.ll

[AArch64] Use SVE/NEON FMLAL top/bottom instructions (#186798)
DeltaFile
+47-10llvm/test/CodeGen/AArch64/f16f32dot-fixed-length-fdot.ll
+17-25llvm/test/CodeGen/AArch64/sve2p1-fixed-length-fdot.ll
+5-20llvm/test/CodeGen/AArch64/sve2p1-fdot.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+4-0llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+2-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+82-576 files

LLVM/project ee53973libclc/clc/lib/generic/math clc_cos.inc clc_sin.inc

libclc: Use select function instead of ?: for some fp selects

It seems that ?: is not quite equivalent to select for floating-point
vectors. With ?:, the resulting IR involves integer bitcasts and
integer vector typed select. Use select so this is an fp-select. This
enables finite math only contexts to optimize out the select.

This feels like it's a clang bug though.
DeltaFile
+3-3libclc/clc/lib/generic/math/clc_cos.inc
+3-2libclc/clc/lib/generic/math/clc_sin.inc
+3-2libclc/clc/lib/generic/math/clc_tan.inc
+9-73 files

LLVM/project 60dc4c7llvm/include/llvm/ADT GenericCycleImpl.h

[CycleInfo] Use block numbers for dfs numbering (NFC) (#187062)

Store the DFSInfo into a vector indexed by block number instead of a map
using the block pointer.

This is a small compile-time improvement for CycleInfo construction.
DeltaFile
+28-13llvm/include/llvm/ADT/GenericCycleImpl.h
+28-131 files

LLVM/project 2915519orc-rt/include/orc-rt Session.h, orc-rt/unittests SessionTest.cpp

[orc-rt] Move CallViaSession into Session, add comments. (#187238)

Makes CallViaSession an inner class on Session, and adds comments and a
convenience method for creating instances.
DeltaFile
+29-14orc-rt/include/orc-rt/Session.h
+3-3orc-rt/unittests/SessionTest.cpp
+32-172 files

OpenBSD/ports O9NgN55lang/python/3 Makefile, lang/python/3/files CHANGES.OpenBSD

   update to python-3.12.13 and patch for recent security fixes.
   backports from tb, .ok tb@ kmos@

   https://mail.python.org/archives/list/security-announce@python.org/thread/H6CADMBCDRFGWCMOXWUIHFJNV43GABJ7/
   Reject control characters in 'http.cookies.Morsel.update' (CVE-2026-3644)

   https://mail.python.org/archives/list/security-announce@python.org/thread/5M7CGUW3XBRY7II4DK43KF7NQQ3TPZ6R/
   Fix C stack overflow (CVE-2026-4224) when an Expat parser with a registered
   'ElementDeclHandler' parses inline DTD containing deeply nested content model.
VersionDeltaFile
1.2.2.1+23-35lang/python/3/patches/patch-Modules_pyexpat_c
1.1.2.1+15-21lang/python/3/patches/patch-Lib_test_test_pyexpat_py
1.1.2.1+15-16lang/python/3/patches/patch-Lib_test_test_http_cookies_py
1.1.2.1+12-10lang/python/3/patches/patch-Lib_http_cookies_py
1.15.2.1+4-1lang/python/3/Makefile
1.2.4.1+4-0lang/python/3/files/CHANGES.OpenBSD
+73-832 files not shown
+76-868 files

OpenBSD/ports b7cKapblang/python/3 Makefile, lang/python/3/patches patch-Lib_test_test_http_cookies_py patch-Lib_http_cookies_py

   update to python-3.13.12 and patch for recent security fixes. ok tb@ kmos@

   https://mail.python.org/archives/list/security-announce@python.org/thread/H6CADMBCDRFGWCMOXWUIHFJNV43GABJ7/
   Reject control characters in 'http.cookies.Morsel.update' (CVE-2026-3644)

   https://mail.python.org/archives/list/security-announce@python.org/thread/5M7CGUW3XBRY7II4DK43KF7NQQ3TPZ6R/
   Fix C stack overflow (CVE-2026-4224) when an Expat parser with a registered
   'ElementDeclHandler' parses inline DTD containing deeply nested content model.
VersionDeltaFile
1.1+79-0lang/python/3/patches/patch-Lib_test_test_http_cookies_py
1.1+71-0lang/python/3/patches/patch-Lib_http_cookies_py
1.2+65-1lang/python/3/patches/patch-Modules_pyexpat_c
1.1+47-0lang/python/3/patches/patch-Lib_test_test_pyexpat_py
1.11+17-0lang/python/3/pkg/PLIST-tests
1.23+1-5lang/python/3/Makefile
+280-63 files not shown
+288-89 files

LLVM/project 003ec3ellvm/test/CodeGen/AArch64 is_fpclass.ll

[NFC][AArch64] add tests for `is_fpclass` (#187231)

Preparation for https://github.com/llvm/llvm-project/pull/169402
DeltaFile
+894-0llvm/test/CodeGen/AArch64/is_fpclass.ll
+894-01 files

LLVM/project 49f9b4bllvm/test/Transforms/LoopVectorize runtime-checks-difference.ll

[LV] Add test for diff checks with ptrtoint subtract. (NFC)

Adds extra test coverage for
https://github.com/llvm/llvm-project/pull/180244.
DeltaFile
+132-0llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
+132-01 files

OPNSense/core 633fbc6src/opnsense/mvc/app/controllers/OPNsense/Kea/forms dialogOption4.xml dialogOption6.xml, src/opnsense/mvc/app/models/OPNsense/Kea KeaDhcpv4.xml KeaDhcpv6.xml

Services: Kea: DHCPv4/v6: Add single client_class support to DHCP options (#9988)

Enhances the DHCP option MVP introduced in:
https://github.com/opnsense/core/commit/8350fcb73b9dd44e8b1e00d2ea03ced71e0f71ac
https://github.com/opnsense/core/commit/b67a8fdc931936f768b3d6a2eea1e179320f257a

An single client_class can be attached to a DHCP option. This client_class contains a test. Right now a single test is possible, matching a DHCP option code, and the payload inside of it. A common example is matching option 93 to send different boot files to different client architectures.

A client_class is optional input, if none is given, the option will always be sent out as before.
DeltaFile
+43-9src/opnsense/mvc/app/controllers/OPNsense/Kea/forms/dialogOption4.xml
+43-9src/opnsense/mvc/app/controllers/OPNsense/Kea/forms/dialogOption6.xml
+50-0src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv4.xml
+50-0src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv6.xml
+31-2src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv6.php
+30-2src/opnsense/mvc/app/models/OPNsense/Kea/KeaDhcpv4.php
+247-221 files not shown
+266-267 files

LLVM/project c374678orc-rt/include/orc-rt Session.h, orc-rt/lib/executor Session.cpp

[orc-rt] Rename Session setController/detachFromController. NFC. (#187235)

These methods are renamed to attach and detach for simplicity.
DeltaFile
+5-5orc-rt/unittests/SessionTest.cpp
+3-3orc-rt/lib/executor/Session.cpp
+2-2orc-rt/include/orc-rt/Session.h
+10-103 files

LLVM/project b6ddf3cllvm/lib/Target/AArch64 AArch64InstrFormats.td, llvm/test/MC/Disassembler/AArch64 reserved-bits-softfail.txt

[AArch64][llm] Make SBZ/SBO insns warn not fail when disassembling

Some instructions in the Arm ARM have bits which are marked as "Should
Be One" or "Should Be Zero", and they're marked as "Constrained
Unpredictable" as to what should happen if they're not.

This is to improve hardware decode efficiency. In all the cases where
this occurs, it's an instruction which in all other respects is closely
related to an adjacent instruction in the encoding space (for example a
similar load or store) but doesn't require one of the variable fields,
usually a register field. These fields are then defined as SBZ or SBO.

If one of these instructions didn't have the bits set to SBZ or SBO,
then the instruction would fail to disassemble. We had missed adding
`Unpredictable` to a few of these, and they would fail rather than
warn.

Update these AArch64 instructions to treat `Unpredictable` bitfields as
soft-fails with a warning, and add a comprehensive disassembler regression

    [9 lines not shown]
DeltaFile
+563-0llvm/test/MC/Disassembler/AArch64/reserved-bits-softfail.txt
+6-0llvm/lib/Target/AArch64/AArch64InstrFormats.td
+569-02 files

FreeBSD/ports dc762c3devel/plasma6-kwrited distinfo, devel/plasma6-plasma-sdk distinfo

KDE: Update KDE Plasma to 6.6.3

Announcement: https://kde.org/announcements/plasma/6/6.6.3/

Ports changes:

sysutils/plasma6-kinfocenter:
 - Add AUX_UTILS option to install auxiliary utilities [1]
   and pull sysutils/sensors in addition.

PR:             293604
DeltaFile
+19-13sysutils/plasma6-kinfocenter/Makefile
+3-3devel/plasma6-kwrited/distinfo
+3-3devel/plasma6-plasma-sdk/distinfo
+3-3devel/plasma6-plasma5support/distinfo
+3-3graphics/plasma6-spectacle/distinfo
+3-3print/plasma6-print-manager/distinfo
+34-2853 files not shown
+188-17359 files

FreeBSD/ports f810303devel/kf6-kdoctools pkg-plist, misc/kf6-purpose Makefile

KDE: Update KDE Frameworks 6 to 6.24.0

Announcement: https://kde.org/announcements/frameworks/6/6.24.0/

Ports changes:

devel/kf6-kcmutils:
 - Renew USE_KDE

misc/kf6-purpose:
 - Renew USE_KDE

net/kf6-kholidays:
 - Use bison
DeltaFile
+74-59x11-toolkits/kf6-kirigami/pkg-plist
+21-0devel/kf6-kdoctools/pkg-plist
+3-5x11-themes/kf6-qqc2-desktop-style/distinfo
+8-0x11-themes/kf6-breeze-icons/pkg-plist
+4-4misc/kf6-purpose/Makefile
+3-3security/kf6-kdesu/distinfo
+113-7175 files not shown
+320-28781 files