[DAG] isKnownNeverZero - add ISD::OR DemandedElts handling (#183228)
This patch updates `SelectionDAG::isKnownNeverZero` to support `ISD::OR`
by forwarding the `DemandedElts` mask to its operands.
Previously, `ISD::OR` dropped the mask, causing the compiler to be
overly conservative if any lane in the vector was zero, even if that
lane wasn't demanded. This change allows the compiler to prove a vector
result is non-zero even if ignored lanes are zero.
Fixes #183037
**Tests:**
- Moved tests from the C++ file to the IR assembly file
(`known-never-zero.ll`) as requested.
- Confirmed the code now correctly tracks which parts of a vector are
actually needed for `ISD::OR`.
- This allows the compiler to prove a result is "never zero" even if
some unused lanes contain zeros.
[AArch64] Limit support to f32 and f64 in performSelectCombine (#184315)
This prevents a crash with fp128 types, other types (f16) were already
excluded.
Fixes #184300
[MLIR] Make test-block-is-in-loop pass a module pass (#184036)
This pass can't run in parallel on function as it would trigger race conditions.
Fixes #183999
[CIR][CUDA]: Handle duplicate mangled names (#183976)
Replace the NYI for duplicate function defs with the proper diagnostic
logic from OG codegen.
Related: #175871, #179278
fixup! Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
and use tablegen pattern for intrinsic, plus other small review changes.