LLVM/project d444e3eclang/docs ReleaseNotes.md, clang/lib/AST ExprCXX.cpp

[Clang][Sema] Fix crash in UnresolvedMemberExpr check (#209792)

This closes https://github.com/llvm/llvm-project/issues/209427

The test currently crashes because while iterating over the candidate
members of an unresolved member expression, `decl` is a `UsingShadowDecl`
with underlying decl as `UnresolvedUsingValueDecl`.

The current `isa<UnresolvedUsingValueDecl>(decl)` guard only checks the
outer `UsingShadowDecl` and misses the unresolved-using decl hidden
inside it, so `getAsFunction()` returns nullptr and
`cast<CXXMethodDecl>(nullptr)` asserts.
 
This patch checks the `UnresolvedUsingValueDecl` inside by calling
`getUnderlyingDecl()` before the guard.

This used to happen before a2794f9f363361f87a3538b90b78ff13381d5ce1.
DeltaFile
+11-0clang/test/SemaCXX/using-decl-templates.cpp
+2-3clang/lib/AST/ExprCXX.cpp
+3-0clang/docs/ReleaseNotes.md
+16-33 files

NetBSD/pkgsrc-wip c422e48CodeWhale distinfo cargo-depends.mk

Update to v.0.9.0. Multiple significant changes
DeltaFile
+87-57CodeWhale/distinfo
+28-18CodeWhale/cargo-depends.mk
+2-2CodeWhale/COMMIT_MSG
+1-1CodeWhale/Makefile
+118-784 files

LLVM/project e8f9589clang/include/clang/Options Options.td, clang/lib/Driver/ToolChains Clang.cpp

[Driver][DirectX] Add `/Qstrip_debug` flag (#204832)

Add the flag that removes ILDB part from the main DXContainer.
DeltaFile
+13-0llvm/test/CodeGen/DirectX/ContainerData/ContainerFlags.ll
+7-3llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
+4-1llvm/lib/MC/MCDXContainerWriter.cpp
+4-0clang/lib/Driver/ToolChains/Clang.cpp
+3-0clang/include/clang/Options/Options.td
+2-0clang/test/Driver/dxc_debug.hlsl
+33-46 files

FreeNAS/freenas 79520basrc/middlewared/middlewared/test/integration/assets kmip.py, tests/api2 test_kmip.py

Basic tests for KMIP
DeltaFile
+129-0src/middlewared/middlewared/test/integration/assets/kmip.py
+48-0tests/api2/test_kmip.py
+177-02 files

NetBSD/pkgsrc 0jSwEJSdoc CHANGES-2026

   Updated devel/nsis, net/libtorrent, net/rtorrent
VersionDeltaFile
1.4517+4-1doc/CHANGES-2026
+4-11 files

NetBSD/pkgsrc gxMSLXNnet/libtorrent distinfo PLIST, net/rtorrent distinfo Makefile

   libtorrent rtorrent: updated to 0.16.18

   0.16.18

   Encryption settings have changed to be easier to use, and changing listen or DHT ports can be done while rtorrent is running.
VersionDeltaFile
1.65+4-4net/rtorrent/distinfo
1.69+4-4net/libtorrent/distinfo
1.28+4-3net/libtorrent/PLIST
1.132+2-2net/rtorrent/Makefile
1.95+2-2net/libtorrent/Makefile
+16-155 files

NetBSD/pkgsrc AYVLKOCdevel/nsis Makefile distinfo, devel/nsis/patches patch-Docs_src_bin_halibut_halibut.h

   nsis: updated to 3.12

   3.12

   Security

   Don't use the Low IL temp directory when elevated
   This stops a possible privilege escalation for installers running as SYSTEM.

   Minor Changes

   Added StartsWith[S], EndsWith[S], Contains[S], IsLowerCase and IsUpperCase LogicLib operators.

   Build System

   Support Python older than 3.6 again
   Preliminary ARM64 support in makensis.nsi
VersionDeltaFile
1.27+23-20devel/nsis/Makefile
1.9+7-8devel/nsis/distinfo
1.5+8-3devel/nsis/PLIST
1.2+1-1devel/nsis/patches/patch-Docs_src_bin_halibut_halibut.h
+39-324 files

FreeBSD/ports bbc2d5ewww/librewolf distinfo Makefile

www/librewolf: Update 152.0.5-1 => 152.0.6-1

Release Notes:
https://www.firefox.com/en-US/firefox/152.0.6/releasenotes/

PR:             296845
Sponsored by:   UNIS Labs
MFH:            2026Q3

(cherry picked from commit b70f457b83c9404ab78fff00fdc6e9b6b463dbea)
DeltaFile
+3-3www/librewolf/distinfo
+1-1www/librewolf/Makefile
+4-42 files

LLVM/project 2ab3593llvm/lib/Target/AMDGPU AMDGPUWaitcntTracking.cpp

Fix merge
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPUWaitcntTracking.cpp
+2-21 files

FreeBSD/ports b70f457www/librewolf distinfo Makefile

www/librewolf: Update 152.0.5-1 => 152.0.6-1

Release Notes:
https://www.firefox.com/en-US/firefox/152.0.6/releasenotes/

PR:             296845
Sponsored by:   UNIS Labs
MFH:            2026Q3
DeltaFile
+3-3www/librewolf/distinfo
+1-1www/librewolf/Makefile
+4-42 files

FreeNAS/freenas f53abf2src/middlewared/middlewared/test/integration/assets kmip.py, tests/api2 test_kmip.py

Basic tests for KMIP
DeltaFile
+172-0src/middlewared/middlewared/test/integration/assets/kmip.py
+48-0tests/api2/test_kmip.py
+220-02 files

LLVM/project 6cafa88lldb/source/Plugins/SymbolFile/NativePDB UdtRecordCompleter.cpp, lldb/test/Shell/SymbolFile/NativePDB static-class-constants.cpp globals-fundamental.cpp

[lldb][NativePDB] Use active bits for constant width (#196104)

Static constants with bit widths less than 16 (e.g. char/unsigned char)
in classes were not available. These constants are still encoded with 16
bits
([here](https://github.com/llvm/llvm-project/blob/dd145eb8997878143f648a7601741f6409330963/llvm/lib/DebugInfo/CodeView/CodeViewRecordIO.cpp#L341-L343))
even though they only need less bits. When we tried to create an
initializer for them, we'd check if the bit width (=16) was small enough
to fit into the target (<16). This would fail.

This was a problem in the following code:
```cpp
struct Foo {
  // width(unsigned char) = 8, but 255 was encoded and read as 16 bit
  static constexpr unsigned char u8_max = 255;
};
```

This PR fixes the issue by using `APSInt::getActiveBits` for unsigned

    [2 lines not shown]
DeltaFile
+109-0lldb/test/Shell/SymbolFile/NativePDB/static-class-constants.cpp
+20-0lldb/test/Shell/SymbolFile/NativePDB/globals-fundamental.cpp
+13-5lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.cpp
+6-1lldb/test/Shell/SymbolFile/NativePDB/Inputs/globals-fundamental.lldbinit
+148-64 files

FreeBSD/ports 56b4b7beditors/vscode pkg-plist Makefile, editors/vscode/files patch-src_bootstrap-node.ts

editors/vscode: Update to 1.129.0

Changelog: https://code.visualstudio.com/updates/v1_129

Reported by:    GitHub (watch releases)
DeltaFile
+179-12,855editors/vscode/pkg-plist
+24-20editors/vscode/Makefile
+14-13editors/vscode/Makefile.reh
+9-9editors/vscode/distinfo
+3-3editors/vscode/Makefile.version
+2-2editors/vscode/files/patch-src_bootstrap-node.ts
+231-12,9022 files not shown
+235-12,9068 files

LLVM/project 5fcab35llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/test/MC/AMDGPU amdhsa-kernel-prologue.s hsa-gfx1250-v4.s

[AMDGPU] Add assembler check for GFX1250 unclaused vmem workaround (#209517)

Warn if an entrypoint does not start with the standard workaround
sequence.
DeltaFile
+49-0llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+28-0llvm/test/MC/AMDGPU/amdhsa-kernel-prologue.s
+12-0llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
+12-0llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s
+101-04 files

OPNSense/ports fdf63b0opnsense/update distinfo

opnsense/update: 26.7 tag was misplaced
DeltaFile
+3-3opnsense/update/distinfo
+3-31 files

LLVM/project 7168fbdllvm/lib/Analysis DependenceAnalysis.cpp

Strict the refine of < and > with intersection
DeltaFile
+26-14llvm/lib/Analysis/DependenceAnalysis.cpp
+26-141 files

LLVM/project 0e1b093llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV sitofp-with-bool.ll uitofp-with-bool.ll

[SPIR-V] Preserve signed i1 semantics in sitofp (#209232)

selectIToF hardcoded IsSigned=false when materializing the bool-to-int
conversion, so sitofp i1 true was miscompiled as 1.0 instead of -1.0
DeltaFile
+2-2llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll
+2-2llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
+1-1llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+5-53 files

LLVM/project f520e70llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp SPIRV.h

[SPIR-V][NewPM] Fix SPIRVEmitIntrinsics registration with the new pass manager (#209966)
DeltaFile
+133-122llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+1-1llvm/lib/Target/SPIRV/SPIRV.h
+1-1llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+135-1243 files

LLVM/project a3bcc01lld/COFF InputFiles.cpp Driver.cpp, lld/test/COFF link-dll-arm64x.s

[LLD] [COFF] Fix linking directly against an ARM64X DLL without import library (#210080)

In mingw mode, when linking against a DLL, the user can either provide a
regular import library, or provide the actual DLL. When importing ARM64X
image, add both native and EC views to the symbol table on EC targets.
Also getMachine() on such images returns ARM64X, treat it as ARM64
instead.
DeltaFile
+81-0lld/test/COFF/link-dll-arm64x.s
+3-20lld/COFF/InputFiles.cpp
+15-1lld/COFF/Driver.cpp
+4-2lld/COFF/InputFiles.h
+103-234 files

LLVM/project b46e6dellvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU global-saddr-load.ll

AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for applyD16Load
DeltaFile
+14-1llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+2-2llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+16-32 files

LLVM/project efd96f7llvm/test/CodeGen/AMDGPU llvm.log.ll llvm.log10.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fpow.ll

AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper

Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
DeltaFile
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log.ll
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+2,760-1,251llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+912-86llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+536-218llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+290-131llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+11,694-4,8624 files not shown
+12,158-5,07110 files

LLVM/project 120343dllvm/lib/Target/AMDGPU AMDGPUPreLegalizerCombiner.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-short-clamp.ll

AMDGPU/GlobalISel: Use integers for clamp i64 to i16 prelegalizer combine
DeltaFile
+26-46llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+6-6llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+32-522 files

LLVM/project e202910llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU codegen-prepare-addrspacecast-non-null.ll

GlobalISel: Use extended LLTs in extract lowering
DeltaFile
+60-29llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+1-1llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+79-485 files

LLVM/project 8980768llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU fptrunc.f16.ll fptrunc.ll

GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering
DeltaFile
+1,282-1,453llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+264-432llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+364-243llvm/test/CodeGen/AMDGPU/fptrunc.ll
+238-239llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
+176-91llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+47-47llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+2,371-2,5056 files

LLVM/project 977bdf5llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.prefetch.inst.ll llvm.amdgcn.s.prefetch.data.ll, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-load.mir regbankselect-waterfall-call.mir

AMDGPU/GlobalISel: Use integers for read-any-lane split type
DeltaFile
+150-72llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
+106-106llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+33-17llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
+24-24llvm/test/CodeGen/AMDGPU/indirect-call.ll
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+341-2476 files not shown
+364-27212 files

LLVM/project 132452fllvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel zextload.ll

AMDGPU/GlobalISel: Fix extending load narrow scalar

isAnyScalar is explicit LLT::scalar check but we want to narrow scalar
integer types as well.
DeltaFile
+6-7llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+7-82 files

LLVM/project 57a45e9llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-constant.mir

AMDGPU/GlobalISel: Use integer as MMO type for loads and stores lowering

We could get away with just the type from MMO in most cases, but MMO splitting
creates MMO with LLT::scalar and we prefer integer.
DeltaFile
+1,622-1,442llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,064-944llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+828-738llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+842-722llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+250-220llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+121-121llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+4,727-4,1878 files not shown
+4,995-4,28614 files

LLVM/project b0dd0f8llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

AMDGPU/GlobalISel: Explicitly widen scalar to i32 for load and store

Affects f16 and bf16. Earlier, they were widened to f32 and s32 respectively.
The actual error was the artifact combiner creating a copy between f32/i32
which fails in the machine verifier. Maybe we could create a bitcast there.
However i32 is more efficient for us and matches well with how argument
lowering keeps f16 and bf16 in i32 copies to/from physical registers.
Also starting from f16 store, G_STORE %0(f16), %1(p1) :: (store (f16),
and doing widen scalar to 32 bit type, i32 makes more sense since store
will store 16 least significant bits G_STORE %0(i32), %1(p1) :: (store (f16)
compared to G_STORE %0(f32), %1(p1) :: (store (f16), which looks incorrect if
we assume input was really in f32 format.
DeltaFile
+2,008-2,008llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,164-1,164llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+963-963llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+556-556llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+486-486llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+108-108llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+5,285-5,28515 files not shown
+5,362-5,36821 files

LLVM/project ea8d864llvm/test/CodeGen/AMDGPU vector-reduce-smin.ll vector-reduce-smax.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.i16.ll insertelement.i8.ll

AMDGPU/GlobalISel: Fix legalizer lowering for G_EXTRACT/INSERT_VECTOR_ELT

Use LLT::integer in bit twiddling lowering for extract/insert vector element.
DeltaFile
+2,741-4,467llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+1,627-4,750llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+990-990llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+975-439llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+8,357-11,51426 files not shown
+13,363-14,10532 files

LLVM/project 622392fllvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Stop using changeTo in legaizer actions

Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
DeltaFile
+855-425llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+783-389llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+759-377llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+253-160llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+232-138llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+58-80llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+2,940-1,56911 files not shown
+3,066-1,65117 files