LLVM/project cfef1aellvm/unittests/Support GlobPatternTest.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+14-0llvm/unittests/Support/GlobPatternTest.cpp
+14-01 files

NetBSD/pkgsrc-wip 4d95b79vorbis-tools PLIST Makefile, vorbis-tools/patches patch-configure patch-ogg123_status.c

vorbis-tools: remove, imported to pkgsrc
DeltaFile
+0-37vorbis-tools/PLIST
+0-32vorbis-tools/Makefile
+0-20vorbis-tools/COMMIT_MSG
+0-19vorbis-tools/patches/patch-configure
+0-14vorbis-tools/patches/patch-ogg123_status.c
+0-8vorbis-tools/DESCR
+0-1302 files not shown
+0-1388 files

FreeNAS/freenas a21a390src/middlewared/middlewared/api/v26_0_0 reporting.py, src/middlewared/middlewared/plugins/reporting graphs.py

NAS-141166 / 26.0.0-RC.1 / Remove stale ARC graph names from reporting API (by Qubad786) (#19107)

## Problem

`reporting.get_data` accepted three graph names — `arcrate`,
`arcactualrate`, `arcresult` — whose backing plugin classes were deleted
during the ZFS netdata plugin rewrite. The Pydantic `Literal` and the
in-memory `__graphs` dict drifted out of sync, so passing any of them
crashed `netdata_get_data` with an uncaught `KeyError`.

## Solution

Removed the dead names from `GraphIdentifier.name`'s `Literal` and
docstring in both `v26_0_0/reporting.py` and `v27_0_0/reporting.py`.
Added a `ReportingNetdataGetDataArgs.from_previous` on each so legacy WS
clients walking the adapter chain get the dead entries silently filtered
instead of a hard rejection at the final v27 boundary. Hardened the
dispatch site in `plugins/reporting/graphs.py` to raise
`CallError(ENOENT)` for any unknown name — mirroring what

    [5 lines not shown]
DeltaFile
+96-0src/middlewared/middlewared/pytest/unit/api/handler/version/test_reporting_graph_filter.py
+10-5src/middlewared/middlewared/api/v26_0_0/reporting.py
+4-1src/middlewared/middlewared/plugins/reporting/graphs.py
+110-63 files

LLVM/project cb3b127mlir/include/mlir/Dialect/SPIRV/IR SPIRVGLOps.td

[mlir][spirv] Account for undefined behaviour in GLSL ops (#203086)

Add only `NoMemoryEffect` to operations with an undefined behavior and
adjust the description to match the revision 17 of the spec w.r.t. undefined
behavior.

Assisted-by: Claude Code
DeltaFile
+68-68mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td
+68-681 files

LLVM/project 609d421llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 expanded-binop-copyable-operand-deps.ll

[SLP] Do not vectorize copyable operands of expanded binops

An operand modeled as a copyable element on one operand edge of an
expanded binop (shl X, 1 represented as add X, X) leaves the duplicated
operand edge as a plain gathered operand with no copyable. The scheduler
then decrements that operand's ScheduleData for a use calculateDependencies
never counted for it, so its unscheduled-deps counter goes negative and
trips the assertion. Reject such bundles instead.

Fixes #203193

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/203285
DeltaFile
+38-0llvm/test/Transforms/SLPVectorizer/X86/expanded-binop-copyable-operand-deps.ll
+23-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+61-02 files

LLVM/project 41fa982llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll

AMDGPU/GlobalISel: RegBankLegalize rules for gfx950 smfmac intrinsics
DeltaFile
+614-794llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+10-2llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+624-7962 files

LLVM/project 132d102llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.init.whole.wave-w32.ll llvm.amdgcn.init.whole.wave-w64.ll

AMDGPU/GlobalISel: RegBankLegalize rules for init_whole_wave intrinsic
DeltaFile
+47-63llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
+9-19llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+58-823 files

LLVM/project a065a17llvm/test/CodeGen/RISCV clmul.ll clmulr.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll clmul-sdnode.ll

Merge branch 'main' into users/kuilpd/generate-source-info-in-llc
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+10,281-12,374llvm/test/CodeGen/RISCV/clmulh.ll
+8,361-8,920llvm/test/CodeGen/RISCV/rvv/expandload.ll
+109,084-164,3692,709 files not shown
+325,776-324,5012,715 files

LLVM/project 730e7d3llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange reduction-extra-use-in-inner-loop.ll

[LoopInterchange] Reject if outer reduction value has extra user
DeltaFile
+13-25llvm/test/Transforms/LoopInterchange/reduction-extra-use-in-inner-loop.ll
+20-0llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+33-252 files

LLVM/project c17c858llvm/test/Transforms/LoopInterchange reduction-extra-use-in-inner-loop.ll

[LoopInterchange] Add test for extra reduction use in inner loop (NFC)
DeltaFile
+283-0llvm/test/Transforms/LoopInterchange/reduction-extra-use-in-inner-loop.ll
+283-01 files

FreeNAS/freenas 31da5d5

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 8677f5fsrc/middlewared/middlewared/api/v26_0_0 reporting.py, src/middlewared/middlewared/api/v27_0_0 reporting.py

NAS-141166 / 27.0.0-BETA.1 / Remove stale ARC graph names from reporting API (#19072)

## Problem

`reporting.get_data` accepted three graph names — `arcrate`,
`arcactualrate`, `arcresult` — whose backing plugin classes were deleted
during the ZFS netdata plugin rewrite. The Pydantic `Literal` and the
in-memory `__graphs` dict drifted out of sync, so passing any of them
crashed `netdata_get_data` with an uncaught `KeyError`.

## Solution

Removed the dead names from `GraphIdentifier.name`'s `Literal` and
docstring in both `v26_0_0/reporting.py` and `v27_0_0/reporting.py`.
Added a `ReportingNetdataGetDataArgs.from_previous` on each so legacy WS
clients walking the adapter chain get the dead entries silently filtered
instead of a hard rejection at the final v27 boundary. Hardened the
dispatch site in `plugins/reporting/graphs.py` to raise
`CallError(ENOENT)` for any unknown name — mirroring what
`netdata_graph` already does — so future schema/implementation drift
surfaces as a clean RPC error rather than an unhandled exception.
DeltaFile
+85-0src/middlewared/middlewared/pytest/unit/api/handler/version/test_reporting_graph_filter.py
+10-5src/middlewared/middlewared/api/v26_0_0/reporting.py
+2-5src/middlewared/middlewared/api/v27_0_0/reporting.py
+4-1src/middlewared/middlewared/plugins/reporting/graphs.py
+101-114 files

LLVM/project 4ed2525llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU scalar-float-sop2.ll

AMDGPU/GlobalISel: Fix regBankLegalize rules for uniform cvt_pkrtz
DeltaFile
+6-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+2-2llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
+8-32 files

LLVM/project 1c823ebllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.load.to.lds.gfx950.ll memory-legalizer-lds-dma-volatile-and-nontemporal.ll

AMDGPU/GlobalISel: RegBankLegalize rules for load_to_lds intrinsic
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.gfx950.ll
+1-1llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
+5-54 files

LLVM/project b0c6584libc/include/sys syscall.h.def

[libc] Add syscall number for recvmmsg_time64 (#203268)

I *think* this will fix the riscv32 bot.
DeltaFile
+4-0libc/include/sys/syscall.h.def
+4-01 files

LLVM/project ac49392llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU asyncmark-pregfx12.ll asyncmark-max-pregfx12.ll

AMDGPU/GlobalISel: RegBankLegalize rules for global_load_async_lds
DeltaFile
+17-19llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
+3-3llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
+3-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+23-223 files

LLVM/project 665fd6allvm/test/Transforms/LoopInterchange reduction-extra-use-in-inner-loop.ll

[LoopInterchange] Add test for extra reduction use in inner loop (NFC)
DeltaFile
+281-0llvm/test/Transforms/LoopInterchange/reduction-extra-use-in-inner-loop.ll
+281-01 files

LLVM/project 2dc0a06llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange reduction-extra-use-in-inner-loop.ll

[LoopInterchange] Reject if outer reduction value has extra user
DeltaFile
+13-23llvm/test/Transforms/LoopInterchange/reduction-extra-use-in-inner-loop.ll
+20-0llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+33-232 files

LLVM/project 7462c28llvm/lib/Transforms/Scalar LoopInterchange.cpp

address review
DeltaFile
+1-3llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+1-31 files

LLVM/project ad4bd90llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange inner-induciton-step-is-not-invariant.ll

[LoopInterchange] Reject if inner loop IV has outer-variant step
DeltaFile
+20-48llvm/test/Transforms/LoopInterchange/inner-induciton-step-is-not-invariant.ll
+7-1llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+27-492 files

LLVM/project 11a3ea6llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll

AMDGPU/GlobalISel: RegBankLegalize rules for mfma_scale
DeltaFile
+7-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
+9-23 files

NetBSD/pkgsrc-wip 8f88b75. Makefile, ipv6calc Makefile PLIST

ipv6calc: remove, imported to pkgsrc
DeltaFile
+0-31ipv6calc/Makefile
+0-19ipv6calc/PLIST
+0-12ipv6calc/COMMIT_MSG
+0-8ipv6calc/DESCR
+0-5ipv6calc/distinfo
+0-1Makefile
+0-766 files

FreeBSD/ports ec8766bwww/py-google-api-python-client distinfo Makefile

www/py-google-api-python-client: Update to 2.197.0

ChangeLog:      https://github.com/googleapis/google-api-python-client/releases/tag/v2.197.0
Reported by:    "release-please[bot]" <notifications at github.com>
DeltaFile
+3-3www/py-google-api-python-client/distinfo
+1-1www/py-google-api-python-client/Makefile
+4-42 files

NetBSD/pkgsrc 3LF410Wnet/ipv6calc Makefile PLIST

   net/ipv6calc: Update to version 4.4.0

   General:
   internal databases: update
   IP2Location 8.7.0 related (relates to https://github.com/chrislim2888/IP2Location-C-Library/releases/tag/8.7.0
   which has unfortunatly incompatible API changes)

   ipv6calcweb/ipv6calcweb.cgi.in: add support for new fields in DB26 with 8.7.0
   add support for additional data in DB26 usable with IP2Location >= 8.7.0
   check IP2Location > 8.6.1 related compatibility/fallback
   Extensions:
   add option --has-feature <NAME>
VersionDeltaFile
1.40+17-10net/ipv6calc/Makefile
1.6+10-0net/ipv6calc/PLIST
1.20+4-4net/ipv6calc/distinfo
+31-143 files

NetBSD/pkgsrc eEEgQaadoc CHANGES-2026 TODO

   doc: Updated net/ipv6calc to 4.4.0
VersionDeltaFile
1.3722+2-1doc/CHANGES-2026
1.27395+1-2doc/TODO
+3-32 files

LLVM/project 4c0e292llvm/include/llvm/TableGen Error.h SetTheory.h

[llvm] Fix most LLVM_ABI annotations in TableGen (#203246)

This updates most LLVM_ABI annotations in the TableGen headers to match
expected usage:
* All public APIs should be properly annotated.
* Inlined functions should not be annotated.

These changes were done by a script fixing annotations on LLVM public
headers and manually checked.

This effort is tracked in #109483.
DeltaFile
+31-25llvm/include/llvm/TableGen/Error.h
+8-8llvm/include/llvm/TableGen/SetTheory.h
+6-5llvm/include/llvm/TableGen/TableGenBackend.h
+4-4llvm/include/llvm/TableGen/TGTimer.h
+4-3llvm/include/llvm/TableGen/Main.h
+3-3llvm/include/llvm/TableGen/StringToOffsetTable.h
+56-482 files not shown
+60-508 files

LLVM/project 4ebce6ellvm/include/llvm/Frontend/HLSL CBuffer.h HLSLBinding.h, llvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h OMP.h

[llvm] Fix most LLVM_ABI annotations in Frontend (#203245)

This updates most LLVM_ABI annotations in the Frontend headers to match
expected usage:
* All public APIs should be properly annotated.
* Inlined functions should not be annotated.

These changes were done by a script fixing annotations on LLVM public
headers and manually checked.

This effort is tracked in #109483.
DeltaFile
+11-10llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+2-2llvm/include/llvm/Frontend/HLSL/CBuffer.h
+1-1llvm/include/llvm/Frontend/HLSL/HLSLBinding.h
+1-1llvm/include/llvm/Frontend/HLSL/RootSignatureMetadata.h
+1-1llvm/include/llvm/Frontend/OpenMP/OMP.h
+16-155 files

LLVM/project c6f0d5dllvm/include/llvm/IR PrintPasses.h NVVMIntrinsicUtils.h

[llvm] Fix most LLVM_ABI annotations in IR (#203244)

This updates most LLVM_ABI annotations in the IR headers to match
expected usage:
* All public APIs should be properly annotated.
* Inlined functions should not be annotated.

These changes were done by a script fixing annotations on LLVM public
headers and manually checked.

This effort is tracked in #109483.
DeltaFile
+22-20llvm/include/llvm/IR/PrintPasses.h
+13-7llvm/include/llvm/IR/NVVMIntrinsicUtils.h
+5-6llvm/include/llvm/IR/RuntimeLibcalls.h
+5-5llvm/include/llvm/IR/DebugInfoMetadata.h
+3-3llvm/include/llvm/IR/SafepointIRVerifier.h
+3-2llvm/include/llvm/IR/Statepoint.h
+51-438 files not shown
+63-5214 files

LLVM/project 1e283d4llvm/include/llvm/CAS ObjectStore.h OnDiskGraphDB.h

[llvm] Fix most LLVM_ABI annotations in CAS (#203243)

This updates most LLVM_ABI annotations in the CAS headers to match
expected usage:
* All public APIs should be properly annotated.
* Inlined functions should not be annotated.

These changes were done by a script fixing annotations on LLVM public
headers and manually checked.

This effort is tracked in #109483.
DeltaFile
+7-9llvm/include/llvm/CAS/ObjectStore.h
+8-7llvm/include/llvm/CAS/OnDiskGraphDB.h
+2-2llvm/include/llvm/CAS/ActionCache.h
+2-2llvm/include/llvm/CAS/CASID.h
+2-2llvm/include/llvm/CAS/OnDiskTrieRawHashMap.h
+2-2llvm/include/llvm/CAS/UnifiedOnDiskCache.h
+23-242 files not shown
+25-268 files

FreeNAS/freenas 93325f9src/middlewared/middlewared main.py, src/middlewared/middlewared/plugins/hardware m_series_nvdimm.py mem_info.py

Convert hardware plugin to the typesafe pattern

## Context
The hardware plugin is a directory of four mostly-private legacy services (mseries.bios, mseries.nvdimm, hardware.memory, plus hardware.virtualization). Only hardware.virtualization.variant is public over the wire; the rest return plain dicts/bools consumed internally by alert sources and usage reporting, so Pydantic models would be pure overhead.

## Solution
Applied the port-plugin pattern: lean Service shims in __init__.py that delegate to plain, fully type-annotated module functions, keeping the existing dict/primitive return shapes so no consumer changes are needed. The one public method gets check_annotations=True against the existing HardwareVirtualizationVariant models. Registered the services in main.py's ServiceContainer via nested hardware/mseries containers and added the plugin to mypy.yml.
DeltaFile
+179-170src/middlewared/middlewared/plugins/hardware/m_series_nvdimm.py
+36-43src/middlewared/middlewared/plugins/hardware/mem_info.py
+79-0src/middlewared/middlewared/plugins/hardware/__init__.py
+11-35src/middlewared/middlewared/plugins/hardware/virt_detection.py
+18-18src/middlewared/middlewared/plugins/hardware/m_series_bios.py
+22-0src/middlewared/middlewared/main.py
+345-2661 files not shown
+346-2667 files