LLVM/project 696aa3cllvm/lib/Target/Hexagon HexagonConstPropagation.cpp, llvm/test/CodeGen/Hexagon constp-extract-pair.ll

[Hexagon] Fix UB from signed left shift overflow in evaluateEXTRACTi (#181243)

The evaluateEXTRACTi function in HexagonConstPropagation uses a left
shift to position a bitfield at the top of a 64-bit word before
extracting it with a right shift. When the source value has high bits
set, the left shift of the int64_t value overflows, which is undefined
behavior.

Fix by performing the left shift in uint64_t, then casting to int64_t
only for the subsequent arithmetic right shift (signed extract case).
DeltaFile
+42-0llvm/test/CodeGen/Hexagon/constp-extract-pair.ll
+5-4llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+47-42 files

LLVM/project 1928839clang-tools-extra/clangd DumpAST.cpp, clang-tools-extra/clangd/unittests DumpASTTests.cpp

[clangd] Guard against null TemplateName in DumpVisitor (#181554)

Add a guard against null values for TemplateName in
DumpVisitor::TraverseTemplateName.

clangd’s DumpVisitor may attempt to traverse a null TemplateName when
handling dependent nested template names. On LLVM main this can lead to
a crash in TemplateName::getKind().

Add a defensive check in DumpVisitor::TraverseTemplateName() to skip
null TemplateName instances before invoking traverseNode(). Following
the same design as other functions in the class.

No functional change is intended beyond preventing the crash.

Fixes: #180902

---------

Signed-off-by: Emily Dror <emilydror01 at gmail.com>
DeltaFile
+29-0clang-tools-extra/clangd/unittests/DumpASTTests.cpp
+2-2clang-tools-extra/clangd/DumpAST.cpp
+31-22 files

FreeBSD/src 7c81bf5sys/netgraph ng_ksocket.c

ng_ksocket: use new macros to lock socket buffers

PR:             292885
Reported by:    Walker R. Thompson <walker.thompson at urz.uni-heidelberg.de>

(cherry picked from commit 1a3d1be4965afddded0b2582b9c4969c1e6a4129)
(cherry picked from commit 4dc38e71ccd522bc5460f3ded3977baa35dad4b9)
DeltaFile
+8-8sys/netgraph/ng_ksocket.c
+8-81 files

LLVM/project f5f8435clang-tools-extra/clangd InlayHints.cpp, clang/include/clang/AST PrettyPrinter.h

[clang][TypePrinter] Introduce AnonymousTagMode enum (#182317)

As part of https://github.com/llvm/llvm-project/pull/159592, we want to
emit unique lambda names into debug-info without relying on
`AnonymousTagLocations` (i.e., we don't want the source files included
in the names).

The plan is to implement this as a third `AnonymousTagMode`. This patch
turns the existing `AnonymousTagLocations` into an enum as preparation.

(full prototype is at https://github.com/llvm/llvm-project/pull/168533)
DeltaFile
+15-7clang/include/clang/AST/PrettyPrinter.h
+10-5clang/unittests/AST/TypePrinterTest.cpp
+6-2clang/tools/libclang/CIndex.cpp
+4-2clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
+4-2clang/lib/AST/Decl.cpp
+3-2clang-tools-extra/clangd/InlayHints.cpp
+42-2010 files not shown
+62-3016 files

LLVM/project f6c86bdllvm/docs LFI.rst, llvm/include/llvm/MC MCLFIRewriter.h MCLFI.h

[LFI] Add MCLFIRewriter infrastructure (#172906)

This is the second patch in the LFI series, adding the following
features:

* `MCLFIRewriter` class, which will be used to perform LFI rewrites on a
per-architecture basis. Each architecture where LFI is supported will
implement a subclass (for example,
`Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp`) that will
implement the `rewriteInst` function to perform the actual rewriting
(the AArch64 version will be added in the next PR). The generic rewriter
class provides some instruction info utilities (`mayLoad`, `mayStore`)
and is used to call `rewriteInst` during instruction emission. It also
provides `onLabel` which allows the rewriter to know possible branch
targets, making certain optimizations like guard elimination possible.
* LFI streamer initialization that marks object files with a NOTE
section to indicate that the object file is using LFI.
* A basic LFI assembly parser that introduces the `.lfi_rewrite_disable`
and `.lfi_rewrite_enable` directives that can be used to control whether
rewriting is enabled or not in hand-written assembly.
DeltaFile
+78-0llvm/lib/MC/MCLFI.cpp
+70-0llvm/lib/MC/MCParser/LFIAsmParser.cpp
+68-0llvm/include/llvm/MC/MCLFIRewriter.h
+54-0llvm/lib/MC/MCLFIRewriter.cpp
+27-0llvm/docs/LFI.rst
+26-0llvm/include/llvm/MC/MCLFI.h
+323-011 files not shown
+383-017 files

LLVM/project d93ad10clang/lib/Headers sifive_vector.h, clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded xsfvcp-x.c

[RISCV] Correct the LMUL operand for __riscv_sf_vc_i_se_u8mf4 and __riscv_sf_vc_i_se_u8mf2 intrinsics. (#182345)

mf2 is should 7 (-1 in 3 bits). mf4 should be 6 (-2 in 3 bits).
DeltaFile
+4-4clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
+2-2clang/lib/Headers/sifive_vector.h
+6-62 files

LLVM/project 63e04e9llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project e9eec7allvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project da3a05bllvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project 1d2fceellvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project f7f1190llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project b1272b4llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project 9c05245llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project fe2ce3ellvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project d4a468dllvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project fff715dllvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project 8521e28llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project 0a1d0d9llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

LLVM/project 3e65180llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir, llvm/test/CodeGen/PowerPC clmul-vector.ll

Rebase, address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+56,025-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+14,154-5,110llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+5,835-5,584llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+94,730-20,5368,262 files not shown
+539,884-182,9818,268 files

FreeBSD/src 10d5404usr.sbin/bhyve usb_mouse.c

bhyve: fix USB mouse requests

USB HCI requests may not include HCI transfer block structures (i.e.,
xfer->data[] == NULL), but in several places, the USB mouse emulation
code assumes one will exist. This can lead to a NULL pointer dereference
and a SEGV in the bhyve process as observed via experiments with an
Ubuntu guest and PyUSB code. Note that many of the cases processing
other request types already checked for data == NULL.

While in the neighborhood, fix a typo in the loop iterating over the
usb_data_xfer_block array which used the wrong variable to check for
valid data (idx vs. i).

Reported by: danmcd at edgecast.io
Obtained from: SmartOS
MFC after: 1 week
Relnotes: yes

Reviewed by:    imp
Differential Revision:  https://reviews.freebsd.org/D54661
DeltaFile
+17-9usr.sbin/bhyve/usb_mouse.c
+17-91 files

NetBSD/pkgsrc 3SeaB5Ydoc CHANGES-2026, editors/moe distinfo Makefile

   updated editors/moe to 1.16

   for changes from 1.15, please see ChangeLog in the sources
VersionDeltaFile
1.3+4-4editors/moe/distinfo
1.3+2-2editors/moe/Makefile
1.1272+2-1doc/CHANGES-2026
+8-73 files

LLVM/project 384bc40llvm/include/llvm/CodeGen SelectionDAGISel.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGISel.cpp

[TableGen][ISel] Add OPC_CheckTypeByHwMode0 to optimize the most frequent getValueTypeForHwMode index. (#182366)

Sort the unique ValueTypeByHwMode combinations by usage and add a
compressed opcode for the most common.

Reduces the RISCVGenDAGISel.inc table by about ~12K. The most common
being XLenVT.

I plan to add EmitIntegerByHwMode0 and EmitRegisterByHwMode0 in
subsequent patches.

Assisted-by: claude
DeltaFile
+61-13llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+10-2llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+4-4llvm/test/TableGen/RegClassByHwMode.td
+2-0llvm/include/llvm/CodeGen/SelectionDAGISel.h
+77-194 files

FreeBSD/src e334b70sys/x86/include x86_var.h, sys/x86/x86 cpu_machdep.c

x86: provide extended description for x86_msr_op(9)

(cherry picked from commit cb81a9c18db93a2046c47b0c7dc0bd6adcdd2495)
DeltaFile
+43-0sys/x86/x86/cpu_machdep.c
+2-4sys/x86/include/x86_var.h
+45-42 files

FreeBSD/src 0558fa8sys/x86/include x86_var.h, sys/x86/x86 cpu_machdep.c

x86: add a safe variant of MSR_OP_SCHED* operations for x86_msr_op(9)

(cherry picked from commit af99e40af1dd4e8b39ca986240ee8b9aea722958)
DeltaFile
+68-7sys/x86/x86/cpu_machdep.c
+2-1sys/x86/include/x86_var.h
+70-82 files

FreeBSD/src b0bc769sys/x86/x86 cpu_machdep.c

x86_msr_op(9): consistently return the value read from MSR

(cherry picked from commit 36ceb5509d01ff2e6482a78ca809c344574e9a25)
DeltaFile
+15-4sys/x86/x86/cpu_machdep.c
+15-41 files

LLVM/project 7513fbdllvm/test/Transforms/LoopVectorize predicated-multiple-exits.ll predicated-single-exit.ll

[LV] Add tests with predicated early exits.

Add test coverage for predicated early exits, without instructions that
need predication after the early exits.
DeltaFile
+592-0llvm/test/Transforms/LoopVectorize/predicated-multiple-exits.ll
+444-0llvm/test/Transforms/LoopVectorize/predicated-single-exit.ll
+1,036-02 files

LLVM/project a49c1ccllvm/cmake/modules HandleLLVMOptions.cmake

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+10-0llvm/cmake/modules/HandleLLVMOptions.cmake
+10-01 files

LLVM/project 7f631bbclang/docs OverflowBehaviorTypes.rst, clang/lib/AST ASTContext.cpp

[Clang] Introduce OverflowBehaviorType for fine-grained overflow control (#148914)

Introduce `OverflowBehaviorType` (OBT), a new type attribute in Clang
that provides developers with fine-grained control over the overflow
behavior of integer types. This feature allows for a more nuanced
approach to integer safety, achieving better granularity than global
compiler flags like `-fwrapv` and `-ftrapv`. Type specifiers are also
available as keywords `__ob_wrap` and `__ob_trap`.

These can be applied to integer types (both signed and unsigned) as well
as typedef declarations, where the behavior is one of the following:

* `wrap`: Guarantees that arithmetic operations on the type will wrap on
overflow, similar to `-fwrapv`. This suppresses UBSan's integer overflow
checks for the attributed type and prevents eager compiler
optimizations.
* `trap`: Enforces overflow checking for the type, even when global
flags like `-fwrapv` would otherwise suppress it.


    [7 lines not shown]
DeltaFile
+832-0clang/docs/OverflowBehaviorTypes.rst
+190-114clang/lib/CodeGen/CGExprScalar.cpp
+254-0clang/test/Sema/attr-overflow-behavior.c
+226-9clang/lib/AST/ASTContext.cpp
+191-12clang/lib/Sema/SemaExpr.cpp
+190-0clang/test/Sema/attr-overflow-behavior.cpp
+1,883-13576 files not shown
+4,112-17982 files

LLVM/project 24cc278llvm/docs/TableGen ProgRef.rst, llvm/lib/TableGen TGParser.cpp

[TableGen] Add let append/prepend syntax for field concatenation
DeltaFile
+110-0llvm/test/TableGen/let-append.td
+68-7llvm/lib/TableGen/TGParser.cpp
+41-2llvm/docs/TableGen/ProgRef.rst
+0-42mlir/lib/TableGen/AttrOrTypeDef.cpp
+20-20mlir/test/mlir-tblgen/op-decl-and-defs.td
+14-14mlir/test/mlir-tblgen/attrdefs.td
+253-8514 files not shown
+307-18320 files

LLVM/project 7ec6c71llvm/include/llvm/Analysis ScalarEvolution.h, llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Rewrite to always create canonical SCEV.
DeltaFile
+60-0llvm/lib/Analysis/ScalarEvolution.cpp
+9-1llvm/include/llvm/Analysis/ScalarEvolution.h
+69-12 files