LLVM/project 1727b22llvm/lib/DTLTO DTLTO.cpp, llvm/test/ThinLTO/X86/dtlto timetrace.ll

[DTLTO] Added missing timetrace "Check cache for DTLTO" message. (#203215)

After the DTLTO refactor commit, the time trace "Chack cache for DTLTO"
message was unintentionally omitted. This patch corrects this omission.
DeltaFile
+9-0llvm/test/ThinLTO/X86/dtlto/timetrace.ll
+2-0llvm/lib/DTLTO/DTLTO.cpp
+11-02 files

LLVM/project 3922f3clldb/source/Plugins/Process/Windows/Common ExceptionRecord.h ExceptionRecord.cpp

[lldb][Windows] Use uint64 for GetExceptionArguments (#203485)

Intended to fix the build failure mentioned in
https://github.com/llvm/llvm-project/pull/203301#issuecomment-4688315446.

Makes sure we always use a 64 bit int, as the minidump exception record
specifies the arguments to be 64 bit. `unsigned long long` is also 64
bit on Windows, but I think `uint64_t` conveys that we actually want a
64bit int.
Then updates uses of the return value to use `uint64_t` over
`ULONG_PTR`.
DeltaFile
+2-4lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.h
+1-1lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.cpp
+1-1lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
+4-63 files

FreeNAS/freenas a0a6655src/middlewared/middlewared/plugins/pool_ pool_operations.py

Fix configure resilver priority
DeltaFile
+1-1src/middlewared/middlewared/plugins/pool_/pool_operations.py
+1-11 files

FreeNAS/freenas d6af206src/middlewared/middlewared/pytest/unit/plugins/pool test_resilver.py

Format tests file
DeltaFile
+14-14src/middlewared/middlewared/pytest/unit/plugins/pool/test_resilver.py
+14-141 files

OPNSense/core c26e4dasrc/opnsense/mvc/app/views/layout_partials base_apply_button.volt, src/opnsense/www/js opnsense_ui.js

ui: simplify previous
DeltaFile
+2-3src/opnsense/www/js/opnsense_ui.js
+1-1src/opnsense/mvc/app/views/layout_partials/base_apply_button.volt
+3-42 files

LLVM/project a0bad85llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU scalar-float-sop2.ll

[AMDGPU][GlobalIsel] Add RegBankLegalize rules and lowering for G_AMDGPU_S_BUFFER_LOAD (#192480)

Add RegBankLegalize rules and lowering for G_AMDGPU_S_BUFFER_LOAD and
sub-dword variants (UBYTE, SBYTE, USHORT, SSHORT). The lowering covers
all four rsrc/offset divergence combinations:
- Uniform rsrc + uniform offset → scalar SMEM (stays as-is)
- Uniform rsrc + divergent offset → MUBUF (S_BUF_to_BUF, no waterfall)
- Divergent rsrc + uniform offset → SMEM in waterfall loop over rsrc
- Divergent rsrc + divergent offset → MUBUF + waterfall over rsrc

TODO: 
1. Fix legalize rule for intrinsic amdgcn_cvt_pkrtz to emit scalar cvt
operation in _/AMDGPU/scalar-float-sop2.ll_
2. Fix offset for GFX1250 in
_/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll_ as done by
PR#178389
DeltaFile
+537-558llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
+1,046-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
+436-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
+214-210llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
+188-84llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
+150-9llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+2,571-8617 files not shown
+2,716-92613 files

FreeNAS/freenas d63eb58src/middlewared/middlewared/plugins/pool_ pool_operations.py

Organize imports
DeltaFile
+7-2src/middlewared/middlewared/plugins/pool_/pool_operations.py
+7-21 files

OPNSense/core 7a53cf1src/opnsense/mvc/app/views/layout_partials base_apply_button.volt, src/opnsense/www/js opnsense_ui.js

ui: fix excessive padding on apply section (#10409)
DeltaFile
+3-2src/opnsense/www/js/opnsense_ui.js
+1-1src/opnsense/mvc/app/views/layout_partials/base_apply_button.volt
+4-32 files

LLVM/project b7a3b3ellvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[AMDGPU] Pass sret pointers in SGPRs
DeltaFile
+56,760-55,584llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+19,496-18,806llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+8,642-8,161llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+2,097-1,748llvm/test/CodeGen/AMDGPU/bf16.ll
+866-672llvm/test/CodeGen/AMDGPU/function-returns.ll
+124-128llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
+87,985-85,09911 files not shown
+88,164-85,19117 files

FreeNAS/freenas 238b691src/middlewared/middlewared/plugins/pool_ pool_operations.py, src/middlewared/middlewared/pytest/unit/plugins/pool test_resilver.py

Fix the actual bug
DeltaFile
+0-9src/middlewared/middlewared/pytest/unit/plugins/pool/test_resilver.py
+1-1src/middlewared/middlewared/plugins/pool_/pool_operations.py
+1-102 files

FreeNAS/freenas a8ee6b7src/middlewared/middlewared/plugins/pool_ pool_operations.py, src/middlewared/middlewared/pytest/unit/plugins/pool test_resilver.py

Extract `calculate_resilver_priority` method
DeltaFile
+170-0src/middlewared/middlewared/pytest/unit/plugins/pool/test_resilver.py
+58-33src/middlewared/middlewared/plugins/pool_/pool_operations.py
+228-332 files

FreeBSD/ports e3ed786filesystems/httpdirfs distinfo Makefile

filesystems/httpdirfs: Update 1.3.2 => 1.3.3

Approved by:            db@, yuri@ (Mentors, implicit)
DeltaFile
+3-3filesystems/httpdirfs/distinfo
+1-1filesystems/httpdirfs/Makefile
+4-42 files

LLVM/project 688540allvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

Use new safestack_interface.h

Created using spr 1.3.7
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,291-641,09512,975 files

LLVM/project 86fba61llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,291-641,09512,975 files

LLVM/project 2b10b6dllvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

Use new safestack_interface.h

Created using spr 1.3.7
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,291-641,09512,975 files

LLVM/project 93e4d46llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,254-641,06412,975 files

LLVM/project d06bdafllvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

Use new safestack_interface.h

Created using spr 1.3.7
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,307-641,10312,975 files

LLVM/project 41d3bd2llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+127,297-175,92812,969 files not shown
+1,030,291-641,09512,975 files

FreeBSD/src 23c99b6usr.sbin/bhyve bhyve.8

bhyve: Document vCPU range pinning

This change documents the recently introduced changes to -p
that allow users to specify CPU ranges instead of having to
specify each individual mapping.

While we're here, move the -p examples to the EXAMPLES section.

Reviewed by:    bcr
MFC after:      2 weeks
Differential Revision:  https://reviews.freebsd.org/D57480
DeltaFile
+25-13usr.sbin/bhyve/bhyve.8
+25-131 files

LLVM/project ec60d62llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize cast-costs.ll

[LV] Reland "Add costs for VPInstructionWithType::computeCost" (#202952)

The original change PR #198291 caused a crash due to an unreachable
opcode. I've added support for the missing opcode.
DeltaFile
+24-49llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
+44-0llvm/test/Transforms/LoopVectorize/RISCV/stepvector-cost.ll
+27-6llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+6-6llvm/test/Transforms/LoopVectorize/cast-costs.ll
+7-5llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
+2-2llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
+110-681 files not shown
+112-707 files

LLVM/project fc66eb4llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[AMDGPU] Pass sret pointers in SGPRs
DeltaFile
+56,760-55,584llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+19,496-18,806llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+8,642-8,161llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+2,097-1,748llvm/test/CodeGen/AMDGPU/bf16.ll
+866-672llvm/test/CodeGen/AMDGPU/function-returns.ll
+124-128llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
+87,985-85,09911 files not shown
+88,165-85,19117 files

LLVM/project 951c67dclang/lib/Driver ToolChain.cpp, clang/lib/Driver/ToolChains AMDGPU.cpp AMDGPUOpenMP.cpp

clang/AMDGPU: Use TranslateArgs from the base toolchain instead of the host (#198627)

This fixes -Xopenmp-target / -Xarch for arbitrary arguments. HIP and
OpenMP had cargo-cult broken implementations of TranslateArgs, which called the
host toolchain's implementation, and then special case transferred either
-march or -mcpu to the device argument list. The respective device forwarding
flags should work for any argument, not just this one. The main feature that
needs to be preserved is the shared filtering of unsupported sanitizers to
degrade them into warnings.

Most of the changes here are dealing with fallout observed when
the host target is darwin. The darwin toolchain happens to have
some hacky statefulness tracking the compile target version, which
gets written and rewritten on argument parsing. To maintain this hack,
there are a few unused calls to getArgsForToolChain; start passing
OFK_Host to these so the offload toolchains don't get confused and think 
they're in a non-offload context.
DeltaFile
+43-13clang/lib/Driver/ToolChains/AMDGPU.cpp
+0-43clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
+5-36clang/lib/Driver/ToolChains/HIPAMD.cpp
+5-25clang/lib/Driver/ToolChains/AMDGPU.h
+12-3clang/lib/Driver/ToolChain.cpp
+7-6clang/lib/Driver/ToolChains/Gnu.cpp
+72-1265 files not shown
+92-13411 files

FreeNAS/freenas b1f5621src/middlewared/middlewared/test/integration/runner ssh.py context.py, src/middlewared/middlewared/test/integration/utils legacy_functions.py

Cleanup SSH tests code
DeltaFile
+1-44src/middlewared/middlewared/test/integration/runner/ssh.py
+3-5src/middlewared/middlewared/test/integration/runner/context.py
+2-5tests/api2/test_001_ssh.py
+5-1src/middlewared/middlewared/test/integration/utils/legacy_functions.py
+1-1src/middlewared/middlewared/test/integration/runner/config.py
+12-565 files

FreeBSD/ports 53e4b97sysutils/k9s distinfo Makefile

sysutils/k9s: Update to 0.51.0

changelog: https://github.com/derailed/k9s/releases/tag/v0.51.0

PR:             295970
DeltaFile
+5-5sysutils/k9s/distinfo
+2-3sysutils/k9s/Makefile
+7-82 files

LLVM/project 6b078e9llvm/test/CodeGen/ARM estimate-size-copy.mir

Update an existing test for new more precise diagnostics
DeltaFile
+1-1llvm/test/CodeGen/ARM/estimate-size-copy.mir
+1-11 files

FreeBSD/ports d8821a2databases/sabiql distinfo Makefile.crates

databases/sabiql: Update to 1.12.4

ChangeLog:

- https://github.com/riii111/sabiql/releases/tag/v1.12.4

Reported by:    riii111 <notifications at github.com>
DeltaFile
+71-73databases/sabiql/distinfo
+34-35databases/sabiql/Makefile.crates
+1-1databases/sabiql/Makefile
+106-1093 files

OPNSense/core ebfe40fsrc/opnsense/mvc/app/controllers/OPNsense/Firewall/Api FilterBaseController.php, src/opnsense/mvc/app/models/OPNsense/Firewall Filter.php

Firewall: Rules: Remove safepoint actions, no consumers in GUI are left, and we don't know of any external API consumers
DeltaFile
+0-69src/opnsense/mvc/app/controllers/OPNsense/Firewall/Api/FilterBaseController.php
+0-25src/opnsense/mvc/app/models/OPNsense/Firewall/Filter.php
+0-942 files

LLVM/project a80153ellvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.smfmac.gfx950.ll

AMDGPU/GlobalISel: RegBankLegalize rules for gfx950 smfmac intrinsics (#203287)
DeltaFile
+614-794llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
+10-2llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+624-7962 files

LLVM/project b9339f0orc-rt/include/orc-rt-c ExternC.h

[orc-rt] Fix an incorrect comment. (#203482)
DeltaFile
+1-1orc-rt/include/orc-rt-c/ExternC.h
+1-11 files

LLVM/project 1a4f405flang CMakeLists.txt, flang-rt/lib/runtime __fortran_builtins.f90

[flang] __fortran_builtins: Update __builtin_team_type to meet PRIF specification (#202450)

The representation of `TEAM_TYPE` in the `ISO_FORTRAN_ENV` module is
opaque to the compiler, but the size (and alignment) needs to match the
PRIF specification for `prif_team_type` to ensure ABI compatibility with
the multi-image runtime library.

Flang's old definition as a derived type containing only an
`integer(int64)` component was leading to an 8-byte `TEAM_TYPE`. However
PRIF specifies the `prif_team_type` component as a `pointer` to an
opaque scalar type, which flang compiles to a 40-byte representation.

This mismatch was leading to incorrect behavior at runtime for programs
compiled with `-fcoarray` and using `TEAM_TYPE`, where `TEAM_TYPE`
values returned by PRIF were being silently truncated by the compiler.

Change the declaration of `__builtin_team_type` to match the PRIF
specification, thus ensuring the representation of `TEAM_TYPE` has the
required size.
DeltaFile
+6-1flang-rt/lib/runtime/__fortran_builtins.f90
+1-0flang/CMakeLists.txt
+7-12 files