[clang][bytecode][NFC] Refactor `alignOfType` (#232193)
Fix capitalization, define `AlignOfReturnsPreferred` only once it's
needed and fix the parameter name comment for `getDeclAlign()`.
The latter is also done in `ExprConstant.cpp`.
[MLIR][NVVM] Add support for pzo in FP8/FP6/FP4 convert Ops (#229660)
This patch adds support for `pzo` and `rz` rounding mode to existing
`FP8`, `FP6` and `FP4` Convert Ops.
Lit tests are added to verify the lowering to the intrinsics.
Negative tests are also added to check the error-handling of invalid
combinations.
PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt
---------
Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
[TargetLowering][X86] Prefer 'r' over 'm' for foldable "rm" inline asm operands
An "rm" (register-or-memory) inline asm operand has always resolved to
'm', because getConstraintPreferences() picks the most general
constraint present, and 'm' is more general than 'r'. That's safe, since
memory can't run out, but it forces a value that could stay in a
register through a stack slot even when there's no register pressure
(https://github.com/llvm/llvm-project/issues/20571).
Prefer 'r' instead where the register allocator can fold the register
back to a stack slot when it runs out of registers, and mark the
register operand foldable (InlineAsm::Flag::setRegMayBeFolded()) so it
does. Both allocators can: the greedy allocator folds an operand when it
spills its value, and the fast allocator folds operands up front when
the asm's register operands wouldn't fit.
ParseConstraints() sets AsmOperandInfo::MayFoldRegister for an operand
whose constraint codes include 'r' and 'm' and are otherwise only
immediate codes, above -O0, on a target that opts in through the new
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[RegAllocFast] Fold foldable inline asm operands under register pressure
An inline asm register operand marked foldable (from an "rm" constraint)
may be replaced with a stack slot when the register allocator runs out
of registers. The greedy allocator does that when it spills the value.
The fast allocator can't: it assigns the operands of an instruction one
at a time, and folding replaces the instruction. So it reported
"inline assembly requires more registers than available" instead.
Before allocating a block, estimate from each inline asm's own operands
whether they fit in registers, and fold as many foldable registers as
needed to make them fit, so the common case without pressure still gets
a register. Values that only live across the asm don't count, since the
allocator spills them when it needs their registers. The estimate
follows allocateInstruction():
- First all defs get distinct registers, avoiding physreg defs; then all
uses, along with the defs still occupied while the uses are read
(early-clobber and tied defs, see isLiveThroughDef()), get distinct
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[CodeGen] Report an error for a direct inline asm output in memory
An inline asm output returned by value has no memory to write to, yet a
constraint such as "=rm" picks memory, the most general constraint, as
does "=m". SelectionDAG asserted on that ("Can only indirectify direct
input operands!"), and GlobalISel dereferenced a null pointer. Clang
never emits such an output, since it passes the address of a memory
output, but other IR can. Report "cannot handle direct memory outputs
yet for constraint 'm'" instead, like the other inline asm errors there.
Assisted-by: Claude Opus 5.5
[TargetInstrInfo] Fix folding inline asm operands next to tied operands
foldInlineAsmMemOperand() swapped a register operand for the target's
memory operands with MachineInstr::removeOperand(), which asserts when a
later operand is tied, because moving it would break the tie. Inline asm
lists every input after every output, so folding any operand that comes
before another tied pair asserted, e.g. an "rm" input followed by the
input of a "+r" operand, or one of two "+rm" operands. Without
assertions, the moved operands kept stale tie indices. Untie the
operands, rebuild the operand list, and re-tie the remaining pairs at
their new positions.
It also gave up when the register appears in more than one operand, e.g.
one value passed to two "rm" operands, which left the greedy allocator
unable to spill that value at all. Fold every such operand into the
stack slot.
Finally, take MayLoad from the folded operands rather than from every
read of the register: a folded def whose tied use is another virtual
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Parse 'foldable' in one place and test the class-less form
Replace the ParseOptionalFoldable lambda with a single check at the end of
parseSymbolicInlineAsmOperand by making the ':' constraint parsing
conditional. Add class-less "regdef foldable" and "reguse foldable" operands
to inline-asm-foldable.mir, which take the path without a ':' constraint
that wasn't tested before.
Assisted-by: Claude Opus 5.5
Remove (mostly) redundant run line
The second run line showed that the *printed* form of the numeric flag (1076101129 -> reguse:GR32 foldable) parses back. But the first run line already contains the symbolic syntax, so it may be a bit overkill.
[flang] Reject oversized -ffixed-line-length values (#229972)
Fixes #227460
## Summary
Reject values of -ffixed-line-length that exceed
std::numeric_limits<int>::max().
The option value is parsed as a 64-bit integer but stored as an
int. Values exceeding the maximum representable int value could
therefore be narrowed without proper validation.
Add a diagnostic for oversized values and regression tests covering
the integer boundary for both flang and flang_fc1.
Tests:
- flang/test/Driver/fixed-line-length.f90
devel/llvm-devel: new snapshot, aarch64 improvements
Enable COMPILER_RT, FLANG, and OPENMP options. Flang requires a
patch to make not compile quadmath functions requiring C11 functionality
FreeBSD hasn't implemented. It's unclear to me why we're attemping
to compile them on aarch64 and not other targets, but it's easy to
just ifdef out the file and this should match x86.
[lldb] Add TSan supression for tests (#231565)
This adds a suppressions file for ThreadSanitizer. The goal is to hide
sanitizer for failures that we can't easily fix.
To actually have real content and test that this works, I put the TSan
error found by TestCancelAttach.py as the first ignored error.
assisted-by: Claude
[SPIR-V] Avoid duplicate untyped pointer types per storage class (#232184)
Each type is cached under one key, and adding it under a pointee key
dropped its untyped pointer entry
Then the next lookup made a second copy and select mixing the copies
crashed
[Analysis] Remove virtual functions in RegionInfoBase (#231958)
MSVC C4661 warns about no suitable definition being provided for an
explicit template instantiation request. In the LLVM dylib build, MSVC
instantiates the extern template base of a dllexported class. This
triggers C4661 for base class templates whose members are only declared,
with their definitions in a separate header.
The above applies to the two derived classes for `RegionInfoBase`,
`RegionInfo` and `MachineRegionInfo`. However, the only virtual method
of importance for `RegionInfoBase` can be moved to the `RegionTraits`
template specializations, removing the need to have class-level
annotations in the derived classes. The other virtual method was the
destructor, which is no longer virtual and kept private, so the base
class can only be destroyed via its friend (derived) classes.
The effort to build LLVM as a dylib is tracked in #109483.
[Clang][counted_by] Don't re-evaluate the base of a counted_by pointer access for -fsanitize=array-bounds
When indexing a 'counted_by' pointer field with -fsanitize=array-bounds,
EmitCountedByBoundsChecking was handed an invalid address and re-emitted
the field's l-value to locate the count. That re-evaluated the struct
base, duplicating its side-effects:
struct p { int count; int *buf __counted_by(count); };
struct p *q;
int f(int i) { return q++->buf[i]; } // 'q' incremented twice
int g(int i) { return get()->buf[i]; } // 'get' called twice
i.e. enabling the sanitizer changed the program's behavior.
When the subscript base is exactly the field load, emit the field's
l-value once, load the pointer from it (as the default case of
EmitPointerWithAlignment does, through EmitLoadOfLValue so that a
'__ptrauth'-qualified field is still authenticated), and pass the
field's address to the bounds check. When there's an intervening cast (e.g.
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[Clang][counted_by][NFC] Add missing tests for counted_by and __builtin_counted_by_ref
Add Sema coverage for __builtin_counted_by_ref:
- a bit-field counter on a 'counted_by' pointer (not just a FAM),
- the '_or_null' and 'sized_by' variants, which return 'void *',
- qualified, enum, and typedef counter types, which determine the
returned pointee type,
- nested, anonymous, by-value, and subscripted bases.
Add CodeGen coverage for the base-expression shapes reaching a counted_by
flexible array member, for both __builtin_dynamic_object_size and
-fsanitize=array-bounds: call and side-effecting bases (which __bdos
must not re-evaluate), pointer chains, conditional bases, negative
constant indices, enum counters, and mixed index widths.
Assisted-by: Claude Opus 5.5
[VPlan] Add missed maybe_unused to createSIVSteps (NFC) (#232216)
This was missed in bb12c270d7 ([VPlan] Strip IR trunc around IntOrFp
inductions, #231837).
TableGen: Store classes and defs in a StringMap (#231573)
Classes and defs were kept in a std::map ordered by name, which makes
every lookup a series of string comparisons over names that often share
long prefixes. Store them in a StringMap instead, and have getClasses()
and getDefs() return a list sorted by name, built when first needed
after records are added.
Gigainstructions executed by llvm-tblgen --null-backend
```
before after
AMDGPU.td 18.17 16.98 -6.6%
X86.td 6.15 5.84 -5.1%
AArch64.td 3.32 3.00 -9.7%
RISCV.td 8.26 7.44 -9.9%
```
Including the backends, all tablegen runs in a build of all targets and
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