LLVM/project e9a9dbcllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV mul.ll

Address review comments
DeltaFile
+45-45llvm/test/CodeGen/RISCV/mul.ll
+11-15llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+56-602 files

LLVM/project c74da90llvm/include/llvm/Demangle ItaniumDemangle.h, llvm/include/llvm/IR User.h

add preferred type annotations i inexplicably didn't add earlier and remove the MathExtras.h noise
DeltaFile
+0-5llvm/include/llvm/Support/MathExtras.h
+1-1llvm/include/llvm/Demangle/ItaniumDemangle.h
+2-0llvm/include/llvm/IR/User.h
+3-63 files

LLVM/project 56aa935flang-rt/include/flang-rt/runtime emit-encoded.h, flang-rt/lib/runtime edit-input.cpp

[flang-rt] Fix warnings

This patch fixes:

  flang-rt/include/flang-rt/runtime/emit-encoded.h:67:27: error:
  implicit conversion from 'const char16_t' to 'char32_t' may change
  the meaning of the represented code unit
  [-Werror,-Wcharacter-conversion]

  flang-rt/lib/runtime/edit-input.cpp:1114:18: error: implicit
  conversion from 'char32_t' to 'char16_t' may lose precision and
  change the meaning of the represented code unit
  [-Werror,-Wcharacter-conversion]

  flang-rt/lib/runtime/edit-input.cpp:1133:18: error: implicit
  conversion from 'char32_t' to 'char16_t' may lose precision and
  change the meaning of the represented code unit
  [-Werror,-Wcharacter-conversion]


    [9 lines not shown]
DeltaFile
+4-4flang-rt/lib/runtime/edit-input.cpp
+1-1flang-rt/include/flang-rt/runtime/emit-encoded.h
+5-52 files

LLVM/project 8d3a707mlir/include/mlir/Target/LLVMIR ModuleImport.h, mlir/lib/Target/LLVMIR ModuleImport.cpp

[MLIR][LLVM] Improve inline asm importer (#139989)

Add support for importing more information into InlineAsmOp:
elementtype, side effects, align stack, asm dialect and operand attrs.
DeltaFile
+43-2mlir/test/Target/LLVMIR/Import/instructions.ll
+40-3mlir/lib/Target/LLVMIR/ModuleImport.cpp
+23-1mlir/test/Target/LLVMIR/llvmir.mlir
+3-0mlir/include/mlir/Target/LLVMIR/ModuleImport.h
+2-0mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
+111-65 files

LLVM/project f73da9ellvm/test/CodeGen/RISCV mul-expand.ll ctz_zero_return_test.ll

[RISCV] Expand constant multiplication for targets without M extension
DeltaFile
+278-93llvm/test/CodeGen/RISCV/mul-expand.ll
+224-136llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
+253-97llvm/test/CodeGen/RISCV/mul.ll
+191-151llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+157-70llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+103-57llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
+1,206-6046 files not shown
+1,491-70012 files

LLVM/project 605f1a4llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV mul-expand.ll mul.ll

Address review comments
DeltaFile
+321-188llvm/test/CodeGen/RISCV/mul-expand.ll
+138-122llvm/test/CodeGen/RISCV/mul.ll
+89-83llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+15-81llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+44-52llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+607-5265 files

FreeBSD/src 96af6ac. UPDATING

UPDATING: Add an entry for commit 772258c89f28
DeltaFile
+4-0UPDATING
+4-01 files

FreeBSD/src 772258csys/fs/nfs nfs_commonsubs.c, sys/fs/nfsclient nfs_clrpcops.c

nfs_clrpcops.c: Fix acquisition of post-op attributes for link

Without this patch, the link RPC (done by nfsrpc_link()) did not
acquire post link operation attributes for the file object for NFSv4.
For some recent Linux NFSv4 servers that support delegations, this
would result in the client's cached attribute for st_nlinks not being
increased right away, because the delegation would indicate that the
now stale cached attributes were still valid.

This patch fixes the problem by acquiring post link attributes and
updating the client's cached copy in the same manner as the NFSv3
RPC did.

Detected at the recent NFSv4 Bakeathon testing event.

Applications will only be affected if they examine st_nlinks after
a new hard link is created for a file object.

MFC after:      2 weeks
DeltaFile
+27-13sys/fs/nfsclient/nfs_clrpcops.c
+1-1sys/fs/nfs/nfs_commonsubs.c
+28-142 files

LLVM/project de0bcd0llvm/lib/Target/RISCV RISCVRegisterInfo.cpp, llvm/test/CodeGen/RISCV stack-offset.ll

[RISCV] Use QC_E_ADDI while eliminating the frameindex (#139515)

The QC_E_ADDI instruction from the Xqcilia extension takes a signed
26-bit immediate and can be used instead of splitting the offset across
two ADDI's while eliminating the frameindex.
DeltaFile
+196-0llvm/test/CodeGen/RISCV/stack-offset.ll
+24-0llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+220-02 files

OpenBSD/ports ybE19KRsecurity/libgcrypt Makefile

   libgcrypt now needs thread-local storage, which base-gcc doesn't
   emulate. Move to ports-gcc on sparc64 to fix the build
VersionDeltaFile
1.98+4-0security/libgcrypt/Makefile
+4-01 files

LLVM/project 980a6faclang/include/clang/Basic DiagnosticCategories.h, clang/lib/Basic DiagnosticIDs.cpp

More changes to make things better, for a given value of better
DeltaFile
+8-4llvm/include/llvm/Bitstream/BitCodes.h
+4-5llvm/include/llvm/Demangle/ItaniumDemangle.h
+4-0clang/lib/Basic/DiagnosticIDs.cpp
+1-1clang/include/clang/Basic/DiagnosticCategories.h
+17-104 files

LLVM/project 5c25061.github new-prs-labeler.yml

[MLGO]{Github] Add MLGO docs page to the MLGO PR subscriber group

This ensures that the MLGO PR subscriber team gets pinged if the document gets
modified which makes sense given it is MLGO specific.
DeltaFile
+1-0.github/new-prs-labeler.yml
+1-01 files

HardenedBSD/src a452fc0lib/libusb libusb10.c libusb.3, share/man/man4 iwlwififw.4 iwlwifi.4

Merge remote-tracking branch 'origin/hardened/current/master' into hardened/current/cross-dso-cfi
DeltaFile
+1,023-1,006share/man/man4/iwlwififw.4
+78-8share/man/man4/iwlwifi.4
+5-0lib/libusb/libusb10.c
+4-0share/misc/committers-src.dot
+1-1lib/libusb/libusb.3
+2-0usr.sbin/usbconfig/dump.c
+1,113-1,0154 files not shown
+1,118-1,01510 files

HardenedBSD/src 127c7a1lib/libusb libusb10.c libusb.3, share/man/man4 iwlwififw.4 iwlwifi.4

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+1,023-1,006share/man/man4/iwlwififw.4
+78-8share/man/man4/iwlwifi.4
+5-0lib/libusb/libusb10.c
+4-0share/misc/committers-src.dot
+2-0usr.sbin/usbconfig/dump.c
+1-1lib/libusb/libusb.3
+1,113-1,0154 files not shown
+1,118-1,01510 files

HardenedBSD/src cda0eb4sys/dev/ichiic ig4_iic.c, sys/dev/iicbus iichid.c

Merge branch 'freebsd/14-stable/main' into hardened/14-stable/master
DeltaFile
+81-26sys/dev/iicbus/iichid.c
+5-6usr.sbin/bluetooth/rtlbtfw/rtlbt_hw.c
+8-0usr.sbin/bluetooth/rtlbtfw/rtlbtfw.conf
+1-4sys/dev/ichiic/ig4_iic.c
+1-0usr.sbin/bluetooth/rtlbtfw/main.c
+1-0sys/netgraph/bluetooth/drivers/ubt/ng_ubt_rtl.c
+97-361 files not shown
+97-377 files

FreeBSD/src a2ebf64sys/conf newvers.sh

14.3: Update to BETA3

Approved by:    re (implicit)
Sponsored by:   Amazon
DeltaFile
+1-1sys/conf/newvers.sh
+1-11 files

LLVM/project b07e19fclang/lib/CodeGen CGClass.cpp

[NFCI][cfi] Refactor into 'SanitizerInfoFromCFICheckKind' (#140117)

This refactors existing code into a 'SanitizerInfoFromCFICheckKind'
helper function. This will be useful in future work to annotate CFI
checks with debug info
(https://github.com/llvm/llvm-project/pull/139809).
DeltaFile
+24-24clang/lib/CodeGen/CGClass.cpp
+24-241 files

FreeNAS/freenas fbd43aasrc/middlewared/middlewared/utils security.py, tests/unit test_shadow_account_policy.py

Add special case handling of root password disable.
The shadow entry for a password disabled root will be '*:::::::'.
This is to avoid the root user getting disabled due to password requirements.

Also added a CI unit test.
Also fixed a small error in the unit test.  Reporting info on an assert was missing some data.
DeltaFile
+45-1tests/unit/test_shadow_account_policy.py
+5-0src/middlewared/middlewared/utils/security.py
+50-12 files

FreeBSD/doc 05c2883website/content/en/releases/14.3R _index.adoc

14.3: Uncomment some docs

Link to the release notes, hardware notes, and signatures.

Sponsored by:   Amazon
DeltaFile
+7-9website/content/en/releases/14.3R/_index.adoc
+7-91 files

FreeBSD/doc 8e7c1f0website/content/en/releases/14.3R schedule.adoc

14.3: Add BETA4 to the schedule

Due to a large number of outstanding issues, I'm adding 14.3-BETA4 to
the schedule.

Sponsored by:   Amazon
DeltaFile
+4-3website/content/en/releases/14.3R/schedule.adoc
+4-31 files

LLVM/project 2ecc621llvm/include/llvm/ProfileData DataAccessProf.h

move type comment before  statement
DeltaFile
+2-2llvm/include/llvm/ProfileData/DataAccessProf.h
+2-21 files

LLVM/project 6ec3604mlir/lib/Dialect/XeGPU/Transforms XeGPUInstructionlize.cpp, mlir/lib/Dialect/XeGPU/Utils XeGPUUtils.cpp

cleanup layout attr
DeltaFile
+46-26mlir/lib/Dialect/XeGPU/Transforms/XeGPUInstructionlize.cpp
+4-2mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
+50-282 files

FreeNAS/freenas 1dc3412src/middlewared/middlewared/utils security.py, tests/unit test_shadow_account_policy.py

Add special case handling of root password disable.
The shadow entry for a password disabled root will be '*:::::::'.
This is to avoid the root user getting disabled due to password requirements.

Also added a CI unit test.
Also fixed a small error in the unit test.  Reporting info on an assert was missing some data.
DeltaFile
+45-1tests/unit/test_shadow_account_policy.py
+5-0src/middlewared/middlewared/utils/security.py
+50-12 files

LLVM/project a29291ellvm/lib/Target/AMDGPU SIInstrInfo.td VOP1Instructions.td

[AMDGPU] Automate creation of byte_sel dags. NFCI.
DeltaFile
+20-7llvm/lib/Target/AMDGPU/SIInstrInfo.td
+0-11llvm/lib/Target/AMDGPU/VOP1Instructions.td
+1-10llvm/lib/Target/AMDGPU/VOP3Instructions.td
+21-283 files

LLVM/project 6d7b5c3clang/test/CIR/CodeGenOpenACC data.c kernels.c

[OpenACC][CIR] Update tests after #140122

Patch #140122 changed the format of OpenACC 'async', without changing
the clang tests.  This patch updates the test.
DeltaFile
+8-8clang/test/CIR/CodeGenOpenACC/data.c
+8-8clang/test/CIR/CodeGenOpenACC/kernels.c
+8-8clang/test/CIR/CodeGenOpenACC/parallel.c
+8-8clang/test/CIR/CodeGenOpenACC/serial.c
+3-3clang/test/CIR/CodeGenOpenACC/wait.c
+35-355 files

LLVM/project 642d5d7llvm/utils/gn/secondary/clang/unittests/CIR BUILD.gn

[gn] "port" fc7857ca95bb (CIRUnitTests)

CIRUnitTests depends on mlir, so create a dummy target to make
the sync script happy. (This is behind CLANG_ENABLE_CIR in cmake.)
DeltaFile
+5-0llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
+5-01 files

LLVM/project 6ab87b2llvm/lib/Passes PassRegistry.def

order

Created using spr 1.3.4
DeltaFile
+1-1llvm/lib/Passes/PassRegistry.def
+1-11 files

NetBSD/src sGHaxzFusr.bin/xlint/lint1 cgram.y

   lint: fix build on 32-bit platforms
VersionDeltaFile
1.529+4-4usr.bin/xlint/lint1/cgram.y
+4-41 files

LLVM/project 136f2baclang/docs ReleaseNotes.rst, clang/lib/AST ExprConstant.cpp

[Clang][AST] Fix HandleLValueBase to deal with references (#140105)

Since P2280R4 Unknown references and pointers was implemented,
HandleLValueBase now has to deal with referneces:

D.MostDerivedType->getAsCXXRecordDecl()

will return a nullptr if D.MostDerivedType is a ReferenceType. The fix
is to use getNonReferenceType() to obtain the Pointee Type if we have a
reference.

Fixes: https://github.com/llvm/llvm-project/issues/139452
DeltaFile
+21-0clang/test/SemaCXX/constant-expression-p2280r4.cpp
+5-1clang/lib/AST/ExprConstant.cpp
+2-0clang/docs/ReleaseNotes.rst
+28-13 files

LLVM/project f113cabllvm/lib/Target/AMDGPU VOPInstructions.td SIInstrInfo.td

[AMDGPU] Cleanup bytesel variables. NFC. (#140131)

Somehow we ended up with 2 sets of td variables: Is...ByteSel and
Has...ByteSel. Keep only Has... form.
DeltaFile
+8-8llvm/lib/Target/AMDGPU/VOPInstructions.td
+3-4llvm/lib/Target/AMDGPU/SIInstrInfo.td
+1-1llvm/lib/Target/AMDGPU/VOP1Instructions.td
+0-1llvm/lib/Target/AMDGPU/VOP3Instructions.td
+12-144 files