[lldb] Start using formatv() in RegisterContextUnwind (NFCI) (#191576)
This introduces two macros that do the same
`UnwindLogMsg()`/`UnwindLogMsgVerbose()` functions, but allow using
`formatv()`-style formatting. In addition to the benefits that the
`formatv()` function provides, this makes `log enable -F lldb unwind`
print the correct methods names from which the messages originate
(previously, it printed the name of one of those two helper methods).
I didn't replace all function calls with macros because there are too
many of them for one PR. This only replaces calls whose format string
contains no specifiers or only '%s' specifiers.
[mlir][spirv] Mark several SPIR-V TOSA Ext Inst ops as NoMemoryEffects (#191814)
Initially such ops were marked Pure wrongly since they could overflow or
underflow the accumulator and result in undefined behavior.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
[LFI][AArch64] Add AArch64 LFI rewrites for system instructions (#186896)
This builds on the MCLFIRewriter infrastructure to add the
AArch64-specific LFI rewriter, which rewrites AArch64 instructions for
LFI sandboxing during the assembler step.
The initial rewriter handles system instructions: system calls, thread
pointer accesses, and also rejects modifications to reserved registers.
[LifetimeSafety] Track origins through std::function (#191123)
1. Recognizes `std::function` and `std::move_only_function` as types
that can carry origins from a wrapped lambda's captures, propagating
origins through both construction and assignment.
2. Adds a kill-only mechanism (i.e., a new `KillOriginFact`) to clear
old loans when the RHS has no origins.
Fixes #186009
[CoroEarly][IR] Clarify semantic of llvm.coro.end (#191752)
We introduced a workaround for the following pattern in #139243:
``` LLVM
define void @fn() presplitcoroutine {
%__promise = alloca ptr, align 8
...
coro.ret:
call void @llvm.coro.end(ptr null, i1 false, token none)
store ptr null, ptr %__promise, align 8
ret void
}
```
where DSE considers `__promise` dead after the return and eliminates the
store, leading to a miscompilation.
However, after #151067, the problematic pattern is gone. And it
currently looks like:
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[NFC][SPIR-V] Fix cbuffer.ll test to pass spirv-val validation (#191940)
Mark `main()` function as a compute shader entry point with numthreads
attribute so the test produces valid SPIR-V
related to https://github.com/llvm/llvm-project/issues/190736
captive portal: regression in 369630d, allowed addresses missing from session ips
If a client is allowed through a statically configured IP, the MAC
becomes secondary, but in the roaming case the set of actual IPs
relied on the MAC address. Since a statically configured IP may not
have a MAC active at a given time, but we do want to keep this IP in
the captive portal pf zone at all time, we merge the primary IP
with the roaming IPs. As a set this will deduplicate automatically.
While here, no MAC address lookup was performed in the case of a
static IP, add it here so it can be actively seen in the sessions
GUI.
Closes https://github.com/opnsense/core/issues/10124
(cherry picked from commit 2b43ee5b87948347ac5a704c484001d169f059e4)
sys/abi_types.h: time32_t is 64-bit on non-x86 architectures
As long as 'sys/compat/freebsd32/freebsd32.h' is used unconditionally on
all platforms (in 'kern_umtx.c' at least), the rule of thumb is to
ensure that 'struct foo32' on a 32-bit arch is type-compatible with
'struct foo' on the same arch. In practice, this is very simple to
achieve: All 'foo32' types should be compatible with 'foo' on 32-bit
architectures, which is what we are supposed to do already for compat'
structures by design. The recently introduced 'freebsd32_uint64_t' type
typically supports that.
This change fixes commit 87632ddf67b0 ("openzfs sys/types32.h: use
abi_compat.h for time32_t") which was defining 'time32_t' to 'in32_t'
for all 32-bit architectures, which is wrong but on i386. By luck, this
did not change the size of whole 'struct ffclock_estimate32' (whose size
is compile-time asserted) because 'struct bintime32''s one would stay
the same, as even if its field 'sec' was incorrectly sized after that
commit, the 'frac' one is 64-bit and 64-bit aligned on all non-x86
architectures so its offset in 'struct bintime32' would stay the same.
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iflib: drain admin task and fix teardown order on register failure
When IFDI_ATTACH_POST() fails (or netmap attach fails), iflib tears down with
ether_ifdetach(), taskqueue_free(ifc_tq), and IFDI_DETACH(). CTX_LOCK is still
held after ether_ifattach. ether_ifdetach() and taskqueue_drain(admin) must not
run under CTX_LOCK.
Teardown ordering (match iflib_device_deregister):
- Free the per-interface admin taskqueue after IFDI_DETACH / IFDI_QUEUES_FREE, not before.
- Drop IFNET_WLOCK() across IFDI_DETACH / IFDI_QUEUES_FREE so driver detach can sleep in
LinuxKPI workqueue drain, then retake IFNET_WLOCK() before iflib_free_intr_mem and fail_unlock.
MFC after: 2 weeks
Reviewed by: gallatin, kgalazka, #iflib
Differential Revision: https://reviews.freebsd.org/D56316
iflib: Fix panic observed while doing sysctl -a with if_bnxt unload
Observed below kernel panic calltrace while performing sysctl -a
operation while unloading the if_bnxt driver,
Fatal trap 9: general protection fault while in kernel mode
KDB: stack backtrace:
db_trace_self_wrapper() at db_trace_self_wrapper+0x2b/frame 0xfffffe02a7569940
vpanic() at vpanic+0x136/frame 0xfffffe02a7569a70
panic() at panic+0x43/frame 0xfffffe02a7569ad0
trap_fatal() at trap_fatal+0x68/frame 0xfffffe02a7569af0
calltrap() at calltrap+0x8/frame 0xfffffe02a7569af0
trap 0x9, rip = 0xffffffff80c0b411, rsp = 0xfffffe02a7569bc0, rbp = 0xfffffe02a7569be0 ---
sysctl_handle_counter_u64() at sysctl_handle_counter_u64+0x61/frame 0xfffffe02a7569be0
sysctl_root_handler_locked() at sysctl_root_handler_locked+0x9c/frame 0xfffffe02a7569c30
sysctl_root() at sysctl_root+0x22f/frame 0xfffffe02a7569cb0
userland_sysctl() at userland_sysctl+0x196/frame 0xfffffe02a7569d50
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[AArch64] Add new dot insts. to cost model (#189642)
This patch builds on #184659 and #184649 and adds cost modelling for new
dot instructions variants, codegened in those patches.
