LLVM/project 94a8ca1libc/src/__support/math inv_trigf_utils.h asinpif.h

[libc][math] Optimize `asinpif` and `acospif` using estrin's scheme (#184286)

Optimize `asinpif` and `acospif` using [Estrin's
scheme](https://en.wikipedia.org/wiki/Estrin%27s_scheme).

## Benchmarking in **debug mode**
### **before**
**asinpif**

```
Ntrial = 40 ; Min = 0.000 + 350.920 clc/call; Median-Min = 450.477 clc/call; Max = 468.882 clc/call;
```

**acospif**
```
Ntrial = 40 ; Min = 0.000 + 309.248 clc/call; Median-Min = 384.386 clc/call; Max = 420.073 clc/call;
```

### **after**

    [7 lines not shown]
DeltaFile
+36-8libc/src/__support/math/inv_trigf_utils.h
+0-22libc/src/__support/math/asinpif.h
+36-302 files

LLVM/project 08a8c2bclang/test/SemaHLSL/Types/BuiltinMatrix MatrixFloatPrecisionWarnings.hlsl

Fix one more test.
DeltaFile
+3-3clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixFloatPrecisionWarnings.hlsl
+3-31 files

LLVM/project bf5d5dfclang/lib/Analysis UnsafeBufferUsage.cpp, clang/unittests/Analysis/Scalable/Analyses/UnsafeBufferUsage UnsafeBufferUsageTest.cpp

clean up
DeltaFile
+1-1clang/lib/Analysis/UnsafeBufferUsage.cpp
+1-1clang/unittests/Analysis/Scalable/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+2-22 files

LLVM/project b5be659clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/lib/CodeGen/TargetBuiltins ARM.cpp

[CIR][AArch64] Add missing lowerings for vceqz_* Neon builtins (#184893)

Implement the remaining CIR lowerings for the AdvSIMD (Neon)
`vceqz{|q|d|s}_*` intrinsic group (bitwise equal to zero).

The `vceqzd_s64` variant was already supported; this patch completes
the rest of the group [1].

Tests for these intrinsics are moved from:
  * test/CodeGen/AArch64/neon-misc.c
  
to:
  * test/CodeGen/AArch64/neon/intrinsics.c

The implementation largely mirrors the existing lowering in
CodeGen/TargetBuiltins/ARM.cpp.

`emitCommonNeonBuiltinExpr` is introduced to support these lowerings.
`getNeonType` is moved without functional changes.

    [2 lines not shown]
DeltaFile
+725-67clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+370-8clang/test/CodeGen/AArch64/neon/intrinsics.c
+1-306clang/test/CodeGen/AArch64/neon-misc.c
+6-0clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1,102-3814 files

FreeBSD/src b4269besys/dev/iwx if_iwx.c

iwx: Fix 32-bit compilation

- Avoid shifts wider than integer types, by wrapping the corresponding
  checks into '#if __SIZEOF_SIZE_T__ > 32' blocks.  'bus_addr_t'
  currently has the same width as 'size_t' on all architectures (and
  this is not going to change for 32-bit architectures).
- Use appropriate printf(3) format for 'wk_keytsc'.

Reviewed by:    adrian
MFC after:      1 minute
MFC to:         stable/15
Sponsored by:   The FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D55667

(cherry picked from commit 35da55c28dbb56dd7056b7863efc5b547950d885)
DeltaFile
+16-5sys/dev/iwx/if_iwx.c
+16-51 files

LLVM/project 9143f21llvm/lib/Transforms/Scalar LoopFuse.cpp

[LoopFusion] Correction in the comments (NFC) (#184689)

The comments in the code should have been updated following the change
in https://github.com/llvm/llvm-project/pull/183353. This PR addresses
that issue.
DeltaFile
+4-6llvm/lib/Transforms/Scalar/LoopFuse.cpp
+4-61 files

LLVM/project 4ad8104llvm/lib/Transforms/Instrumentation AddressSanitizer.cpp

Fixing codegen when using link.exe on arm64
DeltaFile
+1-1llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+1-11 files

LLVM/project 6695f1dllvm/docs AIToolPolicy.md

[docs] Add exception to AI tool policy for Bazel build fixer (#183408)

The Bazel RFC concluded earlier this month:
https://discourse.llvm.org/t/rfc-ai-assisted-bazel-fixer-bot/89178/93

I felt the best way to document this decision was to incorporate it into
this policy document.
DeltaFile
+12-0llvm/docs/AIToolPolicy.md
+12-01 files

LLVM/project dc62e28flang/include/flang/Parser openmp-utils.h, flang/lib/Lower/OpenMP Utils.cpp

[flang][OpenMP] Implement utility to locate OmpClause in ODS, NFC (#184866)

Simplify looking for a specific clause in OmpDirectiveSpecification.
This is alternative to DirectiveStructureChecker::FindClause for when
the internal checker structures have not yet been updated in the AST
traversal.
DeltaFile
+31-40flang/lib/Semantics/check-omp-loop.cpp
+4-14flang/lib/Semantics/check-omp-structure.cpp
+3-7flang/lib/Lower/OpenMP/Utils.cpp
+10-0flang/lib/Parser/openmp-utils.cpp
+2-6flang/lib/Parser/parse-tree.cpp
+3-0flang/include/flang/Parser/openmp-utils.h
+53-676 files

LLVM/project dce8586clang/include/clang/Analysis/Analyses UnsafeBufferUsage.h, clang/include/clang/Analysis/Scalable/Analyses/UnsafeBufferUsage UnsafeBufferUsage.h

[ssaf][UnsafeBufferUsage] Add support for extracting unsafe pointers from all kinds of contributors

- Generalize the -Wunsafe-buffer-usage API for finding unsafe pointers in all kinds of Decls
- Add support in SSAF-based UnsafeBufferUsage analysis for extracting from various contributors
- Mock implementation of HandleTranslationUnit

rdar://171735836
DeltaFile
+113-25clang/lib/Analysis/Scalable/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
+45-18clang/lib/Analysis/UnsafeBufferUsage.cpp
+58-4clang/unittests/Analysis/Scalable/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+8-1clang/include/clang/Analysis/Analyses/UnsafeBufferUsage.h
+2-0clang/include/clang/Analysis/Scalable/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.h
+226-485 files

LLVM/project 275a215flang/lib/Semantics check-acc-structure.cpp, flang/test/Lower/OpenACC acc-cache.f90

[flang][openacc] Relax semantic check on cache directive (#184887)

The specification doesn't really forbid the colon notation to be used to
specify the full array. Reference compiler accepts this and our lowering
can already handle it.
DeltaFile
+16-0flang/test/Lower/OpenACC/acc-cache.f90
+0-6flang/lib/Semantics/check-acc-structure.cpp
+2-4flang/test/Semantics/OpenACC/acc-cache-validity.f90
+18-103 files

LLVM/project a82e3a1llvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.fptrunc.round.ll

[AMDGPU] add back the true16 pattern for cvt_pk_rtz (#184857)

I found that the `SupportedRoundMode` pattern for true16 mode is removed
in https://github.com/llvm/llvm-project/pull/177069 by mistake. Added it
back in this patch and add gfx11 to the test which runs true16 mode
DeltaFile
+364-111llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+9-1llvm/lib/Target/AMDGPU/SIInstructions.td
+373-1122 files

LLVM/project 9548db8libc/shared/math ffmaf128.h, libc/src/__support/math ffmaf128.h CMakeLists.txt

[libc][math] Refactor ffmaf128 into a header only. (#184751)

closes #175325 
part of #147386
DeltaFile
+34-0libc/src/__support/math/ffmaf128.h
+29-0libc/shared/math/ffmaf128.h
+12-1utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+11-0libc/src/__support/math/CMakeLists.txt
+2-4libc/src/math/generic/ffmaf128.cpp
+1-2libc/src/math/generic/CMakeLists.txt
+89-73 files not shown
+93-79 files

OpenBSD/src X2fsVjkusr.sbin/bgpctl output.c

   Fix previous, I put the + stats->bitmap_size outside the fmt_mem() calculation.
VersionDeltaFile
1.72+2-2usr.sbin/bgpctl/output.c
+2-21 files

LLVM/project f629dc9clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/lib/CIR/FrontendAction CIRGenAction.cpp

Address PR comments
DeltaFile
+3-3clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+0-2clang/lib/CIR/FrontendAction/CIRGenAction.cpp
+3-52 files

LLVM/project 2253d5bclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/lib/CIR/FrontendAction CIRGenAction.cpp

[CIR][AArch64] Add missing lowerings for vceqz_* NEON builtins

Implement the remaining CIR lowerings for the AdvSIMD (NEON)
`vceqz{|q|d|s}_*` intrinsic group (bitwise equal to zero).

The `vceqzd_s64` variant was already supported; this patch completes
the rest of the group.

Tests for these intrinsics are moved from:
  test/CodeGen/AArch64/neon-misc.c
to:
  test/CodeGen/AArch64/neon/intrinsics.c

The implementation largely mirrors the existing lowering in
CodeGen/TargetBuiltins/ARM.cpp.

`emitCommonNeonBuiltinExpr` is introduced to support these lowerings.
`getNeonType` is moved without functional changes.


    [2 lines not shown]
DeltaFile
+726-68clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+370-8clang/test/CodeGen/AArch64/neon/intrinsics.c
+1-306clang/test/CodeGen/AArch64/neon-misc.c
+6-0clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-0clang/lib/CIR/FrontendAction/CIRGenAction.cpp
+1,105-3825 files

LLVM/project 43adf57flang/lib/Optimizer/OpenACC/Support RegisterOpenACCExtensions.cpp, flang/test/Fir/OpenACC offload-livein-value-canonicalization.fir

[flang][acc] Handle ViewLike ops with OutlineRematerializationOpInterface in OffloadLiveInValueCanonicalization (#184218)

`fir::ConvertOp` implements both `ViewLikeOpInterface` and
`OutlineRematerializationOpInterface`. `fir.convert` is also used for
ptr-to-int conversions like `(!fir.ref<i32>) -> i64`. That is not really
a "view" — it converts a pointer to an integer — but
`ViewLikeOpInterface` is still attached, so `getOriginalValue` traces
through it to the underlying value.

When the underlying value is not a rematerialization candidate (e.g.,
`fir.alloca`, a block argument, or a `fir.call` result),
`isRematerializationCandidate` returns false and the `fir.convert` is
left as a live-in. This prevents `ACCImplicitData` from tracing back to
the original pointer to create the data mapping.

This PR:
1. Registers `fir::ConvertOp` with
`OutlineRematerializationOpInterface`.
2. Adds a fallback in `isRematerializationCandidate`: when the traced

    [16 lines not shown]
DeltaFile
+118-0flang/test/Fir/OpenACC/offload-livein-value-canonicalization.fir
+15-1mlir/lib/Dialect/OpenACC/Transforms/OffloadLiveInValueCanonicalization.cpp
+2-0flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
+135-13 files

FreeBSD/ports fe5a3daaudio/subtui distinfo Makefile

audio/subtui: Update to 2.8.1

Changelog: https://github.com/MattiaPun/SubTUI/releases/tag/v2.8.1
DeltaFile
+5-5audio/subtui/distinfo
+1-1audio/subtui/Makefile
+6-62 files

LLVM/project aabae9dclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/lib/CodeGen/TargetBuiltins ARM.cpp

[Clang][CIR][AArch64] NFC: Cleanups in AArch64 builtins lowering (#184404)

This patch performs small cleanups and fixes in the AArch64 builtins
lowering code, with the goal of aligning the CIR path more closely
with the existing Clang CodeGen implementation.

Changes include:
* Make sure that `noundef` is consistently matched using `{{.*}}`.
* Rename `AArch64BuiltinInfo` to `armVectorIntrinsicInfo` for better
  consistency with the original CodeGen implementation.
* Simplify `emitAArch64CompareBuiltinExpr`, fix an incorrect
  assert condition (missing `!`) and make sure to use the input `kind`
  condition instead of hard-coding `cir::CmpOpKind::eq`.
* Improve and clarify comments.

No functional changes intended (NFC).
DeltaFile
+30-31clang/test/CodeGen/AArch64/neon/intrinsics.c
+30-22clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+11-1clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+0-4clang/test/CodeGen/AArch64/neon/fullfp16.c
+71-584 files

FreeNAS/freenas d0730f4src/middlewared/middlewared/plugins filesystem.py, src/middlewared/middlewared/utils/filesystem attrs.py

protect some more against TOCTOU in fs plugins/utils

This commit adds a few more usages of RESOLVE_NO_SYMLINKS and
fixes a TOCTOU concern in attrs utils.
DeltaFile
+6-6src/middlewared/middlewared/utils/filesystem/attrs.py
+3-2src/middlewared/middlewared/plugins/filesystem.py
+9-82 files

FreeNAS/freenas d6a9c03src/middlewared/middlewared/plugins snapshot.py, src/middlewared/middlewared/plugins/snapshot __init__.py crud.py

Convert pool.snapshottask to the new pattern
DeltaFile
+0-360src/middlewared/middlewared/plugins/snapshot.py
+195-0src/middlewared/middlewared/plugins/snapshot/__init__.py
+182-0src/middlewared/middlewared/plugins/snapshot/crud.py
+0-81src/middlewared/middlewared/plugins/snapshot_/task_retention.py
+73-0src/middlewared/middlewared/plugins/snapshot/retention.py
+46-0src/middlewared/middlewared/plugins/snapshot/attachment.py
+496-4415 files not shown
+531-46311 files

LLVM/project f271caeclang/lib/AST/ByteCode Compiler.cpp, clang/lib/Tooling DependencyScanningTool.cpp

Rebase

Created using spr 1.3.7
DeltaFile
+595-0llvm/test/Transforms/LoopVectorize/multiple-argmin-argmax.ll
+153-136llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
+243-0clang/test/CodeGenCXX/dllexport-inherited-ctor.cpp
+243-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+226-0clang/lib/AST/ByteCode/Compiler.cpp
+196-28clang/lib/Tooling/DependencyScanningTool.cpp
+1,656-164114 files not shown
+3,986-952120 files

LLVM/project 6b6b0dd. README.md

TEST
DeltaFile
+1-0README.md
+1-01 files

LLVM/project dfe7738mlir/include/mlir/Dialect/OpenACC OpenACCCGOps.td OpenACCOpsTypes.td, mlir/lib/Dialect/OpenACC/IR OpenACCCG.cpp

[mlir][acc] Add acc.compute_region and acc.par_width operations (#184864)

Introduce two new codegen operations to the acc dialect that model GPU
compute region execution and parallel launch configuration:
- acc.par_width: specifies a parallel dimension.
- acc.compute_region: wraps a region of code for GPU execution,
capturing
launch configuration (from acc.par_width results) and input values as
block arguments.

These operations bridge the gap between high-level OpenACC compute
constructs (acc.parallel, acc.kernels, acc.serial) and gpu.launch. The
passes that do these transformations will soon follow.

---------

Co-authored-by: Scott Manley <rscottmanley at gmail.com>
DeltaFile
+236-0mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
+194-0mlir/test/Dialect/OpenACC/ops-cg.mlir
+153-0mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
+20-0mlir/test/Dialect/OpenACC/invalid-cg.mlir
+8-0mlir/include/mlir/Dialect/OpenACC/OpenACCOpsTypes.td
+1-1mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
+612-16 files

LLVM/project 6bd8820clang/lib/CIR/CodeGen CIRGenExprCXX.cpp CIRGenCleanup.cpp, clang/test/CIR/CodeGen new-delete.cpp

[CIR] Add support for delete cleanup after new operators (#184707)

This adds support for calling operator delete when an exception is
thrown during initialization following an operator new call.

This does not yet handle the case where a temporary object is
materialized during the object initialization. That case is marked by
the "setupCleanupBlockActivation" diagnostic in deactivateCleanupBlock
and will be implemented in a future change.
DeltaFile
+247-57clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
+164-0clang/test/CIR/CodeGen/new-delete.cpp
+21-2clang/lib/CIR/CodeGen/CIRGenCleanup.cpp
+19-0clang/lib/CIR/CodeGen/EHScopeStack.h
+10-0clang/lib/CIR/CodeGen/CIRGenCall.cpp
+10-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+471-592 files not shown
+477-618 files

LLVM/project fea72daclang/lib/AST TypePrinter.cpp, clang/test/AST/HLSL ByteAddressBuffers-AST.hlsl Texture2D-vector-AST.hlsl

[HLSL] Fix interleaved vector and matrix return types in AST dump

HLSL vector and matrix types were previously printed with their closing
syntax (', N>') in 'printAfter', causing them to interleave with function
parameters when used as return types (e.g., 'vector<float (args), 4>').

This change moves the HLSL vector and matrix closing syntax into
'printBefore' when 'UseHLSLTypes' is enabled, ensuring the type is
printed completely before the parameter list.

Note that address space qualifiers are now printed after the type
(e.g., 'vector<float, 4>hlsl_device'). This is because
'canPrefixQualifiers' in 'TypePrinter.cpp' returns false for these types.
We cannot easily change this to check 'UseHLSLTypes' because
'canPrefixQualifiers' is a static method and does not have access to the
PrintingPolicy at that point.

Fixes interleaved output in HLSL AST tests.

Assisted-by: Gemini
DeltaFile
+60-40clang/lib/AST/TypePrinter.cpp
+30-30clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
+27-27clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
+16-16clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
+5-5clang/test/AST/HLSL/pch_with_matrix_element_accessor.hlsl
+2-2clang/test/SemaHLSL/BuiltIns/matrix-errors.hlsl
+140-1204 files not shown
+144-12410 files

FreeBSD/ports 5640cefMk/Uses go.mk

Mk/Uses/go.mk: Minor documentation improvements

- Add links to PHB sections on porting Go apps
- Reword the descriptions of most args to put the verb first (my
  theory is that this makes it easier to comprehend at a glance?)
- Use "set up" for verb form and "setup" for noun form (my own pet
  peeve)
- Consistently use tabs for leading whitespace
DeltaFile
+35-18Mk/Uses/go.mk
+35-181 files

LLVM/project f2cdf3fmlir/include/mlir/Dialect/Arith/IR ArithOpsInterfaces.td ArithOps.td, mlir/lib/Conversion/ArithToLLVM ArithToLLVM.cpp

Revert "[mlir][arith] Add `exact` to `index_cast{,ui}` (#183395)" (#184876)

This reverts commit 7ad2c6db54a0e77249f2edb3c589ccf4c930d455.

PR #183395 introduced the `exact` flag to `index_cast` and
`index_castui` and updated some canonicalization patterns.
These canonicalization patterns were found to be unsound. For example:

* `index_cast(index_cast(x)) -> x`
* where one first truncates and then widens x

the rewrite is unsound because information is lost on the first cast as
it **may** truncate the value of x, therefore losing information. The
`exact` flag was made to make this transformation sound. Its semantics
are that when the `exact` flag is present, then it is assumed that the
operand to index_cast does not lose information (i.e., fits perfectly in
the destination type).

In PR #183395, the canonicalization rule was rewritten such that would

    [25 lines not shown]
DeltaFile
+0-64mlir/test/Dialect/Arith/canonicalize.mlir
+0-52mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
+0-47mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td
+5-34mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+8-28mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
+0-28mlir/test/Dialect/Arith/ops.mlir
+13-2532 files not shown
+24-2718 files

FreeNAS/freenas a7e8a4btests/protocols nfs_proto.py

Update to match changes with the move to truenas_getfacl.

(cherry picked from commit 83dca12883ed76911c418d2ae42c74fd9364a20e)
DeltaFile
+6-1tests/protocols/nfs_proto.py
+6-11 files

FreeNAS/freenas a541f4ctests/protocols nfs_proto.py

Convert fix to using json.

(cherry picked from commit a91d91ab691760811d18c75e42bf9cd4dd4bf2db)
DeltaFile
+15-10tests/protocols/nfs_proto.py
+15-101 files