systutils/aoostar-rs: AOOSTAR WTR MAX / GEM12+ PRO LCD screen control tool
asterctl is an open-source tool to control the embedded LCD screen of the
AOOSTAR WTR MAX and GEM12+ PRO mini PCs.
Features:
- Switch the secondary display on or off
- Display custom images (auto-scaled to 960x376, RGB565)
- Render dynamic sensor panels compatible with AOOSTAR-X config files
- Partial screen update support for fast refresh
- USB device/serial port selection
The LCD screen communicates over USB UART (vendor ID 0x0416, product ID
0x90A1). On FreeBSD the device appears as /dev/cuaU0 (requires the umodem
kernel module).
All protocol commands have been reverse engineered from the original
AOOSTAR-X Windows software. No official documentation is available.
If a fd came from libc doing the __pledge_open(2) system call, do not
allow write(2), chmod(2), chflags(2), chown(2), ftruncate(2), or fdpassing.
pledge_open(2) is an unexported interface that libc will use (soon) to
open 2 devices (null and tty), about 9 files (based upon pledge promises),
and files within the zoneinfo directory. This works because libc only
reads from those fd. Currently those files are openable by non-libc code,
but soon only static libc code will be able to do those opens.
This does not transition libc to using the new system call, yet.
Based upon long discussions with david leadbeater and beck.
[mlir][bytecode] Add builtin dialect version (#184678)
This adds a singular Builtin dialect version for use with bytecode
serialization. This version is not currently print unless set and not 0
(not planned a bump until next LLVM version). Created a unit test as
this was easiest way to track.
Additionally add emitWarning virtual method to DialectBytecodeReader,
mirroring emitError.
Tested on old mlir-opt reader, and could read, so should be non-breaking
change.
[X86] Reduce -ffixed-r compile-time overhead (#184606)
PR #180242 added reserve-r support across the driver and backend, but it
also introduced avoidable compile-time work in hot paths.
In Clang, delay +egpr detection until -ffixed-r16 through -ffixed-r31
are actually queried instead of computing it for every x86_64
invocation.
In LLVM, store X86Subtarget::ReservedRReg in a fixed-size std::bitset
and update X86RegisterInfo::getReservedRegs() to iterate only over the
reserve-r register ranges instead of scanning every target register.
These changes keep reserve-r behavior unchanged while trimming the extra
compile-time overhead introduced by the PR.
Signed-off-by: ZhouGuangyuan <zhouguangyuan.xian at gmail.com>
[mlir][NVGPU] Fix double spaces in tests after ODS printer fix. NFC. (#185327)
Follow-up to #184253. Update tests that checked for the old double-space
output of GPU and NVVM ops using GPU_DimensionAttr and
SetMaxRegisterActionAttr.
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
[mlir][XeGPU] Fix double spaces in tests after ODS printer fix. NFC. (#185324)
Follow-up to #184253. Update tests that checked for the old double-space
output of gpu.block_id using GPU_DimensionAttr.
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Refactor createIteratorLoop to use OMPIRBuilder utility functions and make end-of-block insertion robust.
- Replace manual splitBasicBlock/branch with splitBB
and redirectTo()
- When insertion point is at BB.end() and the block is terminated, split
before the terminator so the original successor path is preserved
through omp.it.cont
- Add test for unterminated blocks
[Flang][OpenMP] Fix close map flag propagation for derived types in USM (#1557)
This fixes a bug in USM mode where the `close` map type modifer was
attached to some `map.info.op`'s corresponding to user-defined type
members while the parent type instance itself is not marked as `close`.
This fix ensures that if a parent record type map does not have the
'close' flag, it is cleared from its members as well, maintaining
consistency.
Gemini was used to create tests. AI generated test code was reviewed
line-by-line by me. Which were derived from a reproducer I was working
with to debug the issue.
Assisted-by: Gemini <gemini at google.com>
[AMDGPU] Add structural stall heuristic to scheduling strategies
Implements a structural stall heuristic that considers both resource
hazards and latency constraints when selecting instructions. In coexec,
this changes the pending queue from a binary “not ready to issue”
distinction into part of a unified candidate comparison. Pending
instructions still identify structural stalls in the current cycle, but
they are now evaluated directly against available instructions by stall
cost, making the heuristics both more intuitive and more expressive.
- Add getStructuralStallCycles() to GCNSchedStrategy that computes the
number of cycles an instruction must wait due to:
- Resource conflicts on unbuffered resources (from the SchedModel)
- Sequence-dependent hazards (from GCNHazardRecognizer)
- Add getHazardWaitStates() to GCNHazardRecognizer that returns the number
of wait states until all hazards for an instruction are resolved,
providing cycle-accurate hazard information for scheduling heuristics.
[AMDGPU] Add ML-oriented coexec scheduler selection and queue handling
This patch adds the initial coexec scheduler scaffold for machine
learning workloads on gfx1250.
It introduces function and module-level controls for selecting the
AMDGPU preRA and postRA schedulers, including an `amdgpu-workload-type`
module flag that maps ML workloads to coexec preRA scheduling and a nop
postRA scheduler by default.
It also updates the coexec scheduler to use a simplified top-down
candidate selection path that considers both available and pending
queues through a single flow, setting up follow-on heuristic work.
Refactor and support multiple affinity register for a task
- Support multiple affinity register for a task
- Move iterator loop generate logic to OMPIRBuilder
- Extract iterator loop body convertion logic
- Refactor buildAffinityData by hoisting the creation of affinity_list
- IteratorsOp -> IteratorOp
- Add mlir to llvmir test
[mlir][llvmir][OpenMP] Translate affinity clause in task construct to llvmir
Translate affinity entries to LLVMIR by passing affinity information to
createTask (__kmpc_omp_reg_task_with_affinity is created inside PostOutlineCB).
Implement lowering for omp.iterator in affinity
Create IteratorLoopNestScope for building nested loop for iterator.
Take advantage of RAII so that we can have correct exit for each
level of the loop.
