LLVM/project 96bd7b6llvm/include/llvm/CodeGen TargetLowering.h BasicTTIImpl.h, llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp LegalizeDAG.cpp

[CodeGen] Add additional params to `TargetLoweringBase::getTruncStoreAction` (#187422)

The truncating store analogue of #181104.

Adds `Alignment` and `AddrSpace` parameters to
`TargetLoweringBase::getTruncStoreAction` and dependents, and introduces
a `getCustomTruncStoreAction` hook for targets to customize legalization
behavior using this new information.

This change is fully backwards compatible from the target's point of
view, with `setTruncStoreAction` having identical functionality. The
change is purely additive.
DeltaFile
+41-15llvm/include/llvm/CodeGen/TargetLowering.h
+15-9llvm/lib/Target/X86/X86ISelLowering.cpp
+14-8llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+10-5llvm/include/llvm/CodeGen/BasicTTIImpl.h
+7-4llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+5-3llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+92-448 files not shown
+117-5614 files

FreeBSD/ports 851e6d9devel/meson Makefile distinfo, devel/meson/files patch-unittests_linuxliketests.py

devel/meson: update to 1.10.2

Changes: https://mesonbuild.com/Release-notes-for-1-10-0.html

PR: 287666
exp-run by: antoine
DeltaFile
+32-8devel/meson/Makefile
+0-13devel/meson/files/patch-unittests_linuxliketests.py
+3-3devel/meson/distinfo
+35-243 files

OpenZFS/src 4155d15module/os/linux/zfs zpl_super.c

Linux 7.0: ensure LSMs get to process mount options

Normally, kernel gives any LSM registering a `sb_eat_lsm_opts` hook a
first look at mount options coming in from a userspace mount request.
The LSM may process and/or remove any options. Whatever is left is
passed to the filesystem.

This is how the dataset properties `context`, `fscontext`, `defcontext`
and `rootcontext` are used to configure ZFS mounts for SELinux. libzfs
will fetch those properties from the dataset, then add them to the mount
options.

In 0f608aa6ca (#18216) we added our own mount shims to cover the loss of
the kernel-provided ones. It turns out that if a filesystem provides a
`.parse_monolithic callback`, it is expected to do _all_ mount option
parameter processing - the kernel will not get involved at all. Because
of that, LSMs are never given a chance to process mount options. The
`context` properties are never seen by SELinux, nor are any other
options targetting other LSMs.

    [9 lines not shown]
DeltaFile
+15-2module/os/linux/zfs/zpl_super.c
+15-21 files

LLVM/project c5fc4b2llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! Fix commits after rebase to main
DeltaFile
+19-29llvm/lib/Target/AArch64/AArch64SystemOperands.td
+5-6llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+6-0llvm/test/MC/AArch64/armv9a-tlbip.s
+30-353 files

FreeBSD/ports f6ac506audio/kapitonov-plugins-pack-lv2 distinfo Makefile

audio/kapitonov-plugins-pack-lv2: fix build with newer meson

https://github.com/olegkapitonov/Kapitonov-Plugins-Pack/pull/31

PR: 291451
Approved by: yuri (maintainer)
DeltaFile
+3-1audio/kapitonov-plugins-pack-lv2/distinfo
+3-0audio/kapitonov-plugins-pack-lv2/Makefile
+6-12 files

FreeBSD/ports dfab666audio/faust distinfo Makefile

audio/faust: fix build with LLVM 22

https://github.com/grame-cncm/faust/pull/1232

PR: 291450
Approved by: yuri (maintainer)
DeltaFile
+3-1audio/faust/distinfo
+2-1audio/faust/Makefile
+5-22 files

LLVM/project 8e20e40llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! Fix commits after rebase to main
DeltaFile
+19-29llvm/lib/Target/AArch64/AArch64SystemOperands.td
+5-6llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+4-0llvm/test/MC/AArch64/armv9a-tlbip.s
+28-353 files

LLVM/project 12319b3clang/lib/CodeGen CGCall.cpp, clang/test/CodeGenCXX microsoft-vector-deleting-dtors.cpp microsoft-vector-deleting-dtors2.cpp

[Clang] More aggressively mark this* dead_on_return in destructors (#183347)

Now also mark the this pointer dead_on_return for classes with a
non-zero number of base classes. We saw a limited number of failures
internally due to this change, so it doesn't seem like there are too
many problems with real world deployment.
DeltaFile
+45-45clang/test/OpenMP/for_reduction_codegen_UDR.cpp
+8-8clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
+6-6clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
+3-6clang/lib/CodeGen/CGCall.cpp
+4-4clang/test/CodeGenCXX/ms-vdtors-devirtualization.cpp
+1-1clang/test/CodeGenCXX/destructor-dead-on-return.cpp
+67-701 files not shown
+68-717 files

LLVM/project 0e7f715clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsage.h, clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsage.cpp

address comments
DeltaFile
+90-21clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.cpp
+0-96clang/unittests/ScalableStaticAnalysisFramework/Analyses/MockSerialization.h
+30-62clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+6-63clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.h
+126-2424 files

LLVM/project b85492bllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.sudot8.ll llvm.amdgcn.sudot4.ll

AMDGPU/GlobalISel: RegBankLegalize rules for sudot4/sudot8 (#189104)
DeltaFile
+14-1llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
+14-1llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+32-23 files

LLVM/project b15f94ellvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! Fix commits after rebase to main
DeltaFile
+19-29llvm/lib/Target/AArch64/AArch64SystemOperands.td
+3-5llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+2-0llvm/test/MC/AArch64/armv9a-tlbip.s
+24-343 files

LLVM/project 9887cd6llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Simplify logic after suggestions from Marian
DeltaFile
+13-10llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+13-101 files

LLVM/project 9306eebllvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

[AArch64][llvm] Gate some `tlbip` insns with +tlbid or +d128

Change the gating of `tlbip` instructions containing `*E1IS*`, `*E1OS*`,
`*E2IS*` or `*E2OS*` to be used with `+tlbid` or `+d128`. This is because
the 2025 Armv9.7-A MemSys specification says:

```
  All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions
  that are currently dependent on FEAT_D128 are updated to be dependent
  on FEAT_D128 or FEAT_TLBID
```
DeltaFile
+259-0llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s
+66-66llvm/test/MC/AArch64/armv9a-tlbip.s
+20-0llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+15-5llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+360-714 files

LLVM/project f7d1309llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! More simplification
DeltaFile
+413-443llvm/test/MC/AArch64/armv9a-tlbip.s
+1-15llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+7-9llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+421-4673 files

LLVM/project a425b7cllvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Don't use ExtraRequires. Instead, set a boolean in TLBITableBase
DeltaFile
+27-22llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+17-1llvm/lib/Target/AArch64/AArch64SystemOperands.td
+7-7llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+51-303 files

LLVM/project 9214a07llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! More optimisations
DeltaFile
+10-11llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+7-6llvm/lib/Target/AArch64/AArch64SystemOperands.td
+1-8llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+18-253 files

LLVM/project 68dba8cllvm/test/MC/AArch64 tlbip-tlbid-or-d128.s armv9a-tlbip.s

fixup! Fix using Marian's suggestion
DeltaFile
+0-259llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s
+160-0llvm/test/MC/AArch64/armv9a-tlbip.s
+160-2592 files

LLVM/project 8ca1cb7llvm/lib/Target/AArch64 AArch64SystemOperands.td

[AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (part 2) (#189503)

(This is the change message for 306e86be5, which GitHub unhelpfully discarded
when I enabled "auto-merge" when all tests had passed. It merged my change
and didn't merge the detailed commit message which I had carefully written(!)

So this is an NFC change, for those in the future looking for the lost message,
which explains the changes in 306e86be5)

-------------

Correct the `TLBI` system operand definitions so the emitted aliases are
generated from a single data table per feature group. The TLBI data is now
written once as anonymous `TLBI<...>` entries inside a defvar list, and we
iterate over it with a foreach to define those entries.

Hopefully this is clearer and more future-proof, since it is a complex set of
interactions between `tlbi`/`tlbip` with `*nXS` variants, and differing gating.


    [7 lines not shown]
DeltaFile
+1-1llvm/lib/Target/AArch64/AArch64SystemOperands.td
+1-11 files

LLVM/project 89d5d50clang/lib/CIR/CodeGen CIRGenBuiltin.cpp, llvm/include/llvm/IR Intrinsics.h

[NFC][LLVM] Rename `IITDescriptor` fields to confirm to LLVM CS (#189448)

Rename fields of `IITDescriptor` to conform to LLVM coding standards
naming conventions.
DeltaFile
+11-11llvm/include/llvm/IR/Intrinsics.h
+9-10llvm/lib/IR/Intrinsics.cpp
+3-3clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+23-243 files

LLVM/project 7b52dd6libc/src/__support/wchar CMakeLists.txt string_converter.h

[libc][NFC] Add LIBC_INLINE and cleanup wchar internals (#188856)

Some of the functions were missing LIBC_INLINE and some of the variable
names were less descriptive than I liked. This PR fixes both as well as
cleaning up dependencies.
DeltaFile
+10-2libc/src/__support/wchar/CMakeLists.txt
+5-5libc/src/__support/wchar/string_converter.h
+5-5libc/src/__support/wchar/mbrtowc.cpp
+4-6libc/src/__support/wchar/mbsnrtowcs.h
+5-4libc/src/__support/wchar/character_converter.h
+4-4libc/src/__support/wchar/wcrtomb.h
+33-262 files not shown
+36-298 files

FreeNAS/freenas 4186d0c

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 3c413e1src/middlewared pyproject.toml, src/middlewared/debian control

NAS-140368 / 27.0.0-BETA.1 / Replace pysnmp with truenas_pysnmp C extension for SNMP traps (#18581)

Rewrites `snmp_trap.py` to use the truenas_pysnmp C extension and
replaces the python3-pysnmp4 dependency with python3-truenas-pysnmp.
Depends on https://github.com/truenas/truenas_pysnmp/pull/1 and
https://github.com/iXsystems/truenas_build/pull/46
DeltaFile
+23-104src/middlewared/middlewared/alert/service/snmp_trap.py
+2-2src/middlewared/debian/control
+1-1src/middlewared/pyproject.toml
+26-1073 files

LLVM/project 824af5cllvm/lib/Target/AArch64 AArch64SystemOperands.td

[AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (part 2)

(This is the change message for 306e86be5, which GitHub unhelpfully lost
when I enabled "auto-merge" when all tests had passed. It merged my change
and didn't merge the commit message. So this is an NFC change, for those
in the future looking for the lost message, which explains the actual change)

-------------

Correct the `TLBI` system operand definitions so the emitted aliases are
generated from a single data table per feature group. The TLBI data is now
written once as anonymous `TLBI<...>` entries inside a defvar list, and we
iterate over it with a foreach to define those entries.

Hopefully this is clearer and more future-proof, since it is a complex set of
interactions between `tlbi`/`tlbip` with `*nXS` variants, and differing gating.

The gating was incorrect before. The gating is now:
  - `FeatureTLB_RMI`, `FeatureRME`, and `FeatureTLBIW` gate only TLBI aliases

    [6 lines not shown]
DeltaFile
+1-1llvm/lib/Target/AArch64/AArch64SystemOperands.td
+1-11 files

LLVM/project 974d663llvm/test/CodeGen/AMDGPU schedule-amdgpu-tracker-physreg.ll

Folded multiple RUN lines into one while maintaining debug msgs.
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
+4-41 files

LLVM/project acbf3f3mlir/lib/Conversion/SCFToControlFlow SCFToControlFlow.cpp, mlir/test/Conversion/SCFToControlFlow convert-to-cfg.mlir

[MLIR][SCF] Fix scf.index_switch lowering to preserve large case values (#189230)

`IndexSwitchLowering` stored case values as `SmallVector<int32_t>`,
which silently truncated any `int64_t` case value larger than INT32_MAX
(e.g. `4294967296` became `0`). The `cf.switch` flag was also created
via `arith.index_cast index -> i32`, losing the upper 32 bits on 64-bit
platforms.

Fix: store case values as `SmallVector<APInt>` with 64-bit width, cast
the index argument to `i64`, and use the `ArrayRef<APInt>` overload of
`cf::SwitchOp::create` so the resulting switch correctly uses `i64` case
values and flag type.

Fixes #111589

Assisted-by: Claude Code
DeltaFile
+28-2mlir/test/Conversion/SCFToControlFlow/convert-to-cfg.mlir
+5-6mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
+33-82 files

LLVM/project c69319bllvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! Fix commits after rebase to main
DeltaFile
+19-29llvm/lib/Target/AArch64/AArch64SystemOperands.td
+2-3llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+2-0llvm/test/MC/AArch64/armv9a-tlbip.s
+23-323 files

LLVM/project c64505fllvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/Utils AArch64BaseInfo.h

fixup! Fix commits after rebase to main
DeltaFile
+20-30llvm/lib/Target/AArch64/AArch64SystemOperands.td
+2-2llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+2-0llvm/test/MC/AArch64/armv9a-tlbip.s
+24-323 files

LLVM/project 5da2546mlir/lib/Dialect/SCF/IR SCF.cpp, mlir/test/Dialect/SCF canonicalize.mlir

[mlir][scf] Fix FoldTensorCastOfOutputIntoForallOp write order bug (#189162)

`FoldTensorCastOfOutputIntoForallOp` incorrectly updated the
destinations of `tensor.parallel_insert_slice` ops in the `in_parallel`
block by zipping `getYieldingOps()` with `getRegionIterArgs()`
positionally. This assumed that the i-th yielding op writes to the i-th
shared output, which is not required by the IR semantics. When slices
are written to shared outputs in non-positional order, the
canonicalization would silently reverse the write targets, producing
incorrect output.

Fix by replacing the positional zip with a per-destination check: for
each yielding op's destination operand, if it is a `tensor.cast` result
whose source is one of the new `scf.forall` region iter args (i.e., a
cast we introduced to bridge the type change), replace the destination
with the cast's source directly. This correctly handles all orderings.

Add a regression test that exercises the multi-result case where
`parallel_insert_slice` ops write to shared outputs in non-sequential

    [4 lines not shown]
DeltaFile
+38-0mlir/test/Dialect/SCF/canonicalize.mlir
+20-8mlir/lib/Dialect/SCF/IR/SCF.cpp
+58-82 files

LLVM/project e097875mlir/lib/Dialect/SparseTensor/Transforms SparseAssembler.cpp

[MLIR][SparseTensor] Fix fingerprint changes in SparseFuncAssembler (#188958)

SparseFuncAssembler::matchAndRewrite was calling funcOp.setName(),
funcOp.setPrivate(), and funcOp->removeAttr() directly without notifying
the rewriter, causing "operation fingerprint changed" errors under
MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS.

Wrap all in-place funcOp mutations with rewriter.modifyOpInPlace.

Assisted-by: Claude Code

Fix a failure present with MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON.

Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+7-3mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
+7-31 files

LLVM/project 27b9ea5mlir/lib/Dialect/SparseTensor/Transforms/Utils LoopEmitter.cpp

[MLIR][SparseTensor] Fix domination violation in co-iteration for dense iterators (#188959)

In exitWhileLoop, random-accessible (dense) iterators were being located
using whileOp.getResults().back() while the insertion point was still
inside the while loop's after block. This caused a domination violation:
the ADDI created by locate() was inside the after block, but it was
later used (via derefImpl's SUBI) after the while loop exits.

Move the locate() calls for random-accessible iterators to after
builder.setInsertionPointAfter(whileOp), where the while results are
properly in scope.

Fixes 10 failing tests under MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS.

Assisted-by: Claude Code

Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+14-5mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
+14-51 files