LLVM/project e5332f3llvm/include/llvm/MC MCGOFFObjectWriter.h, llvm/lib/MC GOFFObjectWriter.cpp

[SystemZ][GOFF] Implement reset() for GOFFObjectWriter (#201197)

The reset() methods is used to free memory before the object is
destructed or reused. This change adds this functionality to the GOFF
writer.
DeltaFile
+7-0llvm/lib/MC/GOFFObjectWriter.cpp
+2-0llvm/include/llvm/MC/MCGOFFObjectWriter.h
+9-02 files

LLVM/project 911eddeflang/lib/Frontend CompilerInvocation.cpp, flang/test lit.cfg.py

[Flang] Fix omp_lib.h location and search path (#201104)

Before this PR, omp_lib.h is emitted to `${PREFIX}/include` or
`${PREFIX}/lib/clang/<version>/include` (install prefix) and
`${PREFIX}/runtime/src/omp_lib.h` (builddir prefix). It is never found
there because the driver only adds `${PREFIX}/include/flang/OpenMP` to
the include path.

Fix the `omp_lib.h` include by using the same mechanism as the
omp_lib.mod; that is, move it to
`${PREFIX}/lib/clang/<version>/finclude/flang/<target-triple>`. The
search path is already added by the driver via
`-fintrinsics-modules-path` by the driver. Although omp_lib.h currently
does not contain anything target-specific, it could do so in the future
and I don't think it is worth the effort to add a mechanism without the
target triple. It should also me consistent with omp_lib.mod.

The changes in detail consist of:
1. Move the omp_lib.h output in the builddir to

    [16 lines not shown]
DeltaFile
+25-18flang/test/Driver/include-omp-header.f90
+0-14flang/lib/Frontend/CompilerInvocation.cpp
+0-8flang/test/lit.cfg.py
+3-3openmp/module/CMakeLists.txt
+28-434 files

LLVM/project 70d62e1clang/include/clang/Driver Driver.h ToolChain.h, clang/lib/Driver Driver.cpp ToolChain.cpp

[Clang] Rework LTO mode selection to be a Toolchain property (#201155)

Summary:
Currently, the LTO mode is a property of the Driver, which makes sense
because it is used to set up phases. However, we currently have `-flto`
and `-foffload-lto`, which is a split that doesn't fully work with the
full context of a heterogenous compilation as it is 'all-or-nothing'.

This PR seeks to be mostly NFC for now, just moving the queries to a
per-toolchain interface rather than the static driver mode setting we
have right now. The *single* use of this before ToolChains are created
is for the Webassembly toolchain to set an include path. This is now
just a direct check on the flag, which is consistent. In the future they
could shift to fat LTO objects as well.

The main goal for the PR is to allow the GPU / Offloading toolchains to
specify their "real" LTO behavior. Right now SPIR-V and AMDGCN both
default to LTO, but rather than re-use the LTO handling we hack through
the driver phases to override it. Allowing this split would let us

    [6 lines not shown]
DeltaFile
+39-75clang/lib/Driver/Driver.cpp
+53-0clang/lib/Driver/ToolChain.cpp
+3-29clang/include/clang/Driver/Driver.h
+13-12clang/lib/Driver/ToolChains/Clang.cpp
+13-0clang/include/clang/Driver/ToolChain.h
+7-5clang/lib/Driver/ToolChains/WebAssembly.cpp
+128-12121 files not shown
+175-18027 files

OpenBSD/ports T1Cj47Lcad/prusaslicer Makefile, cad/prusaslicer/patches patch-src_libslic3r_SupportSpotsGenerator_cpp patch-src_libslic3r_AABBTreeLines_hpp

   Fix cad/prusaslicer build with LLVM 22

   From maintainer Renato Aguiar.
VersionDeltaFile
1.3+18-11cad/prusaslicer/patches/patch-src_libslic3r_SupportSpotsGenerator_cpp
1.1+12-0cad/prusaslicer/patches/patch-src_libslic3r_AABBTreeLines_hpp
1.32+1-1cad/prusaslicer/Makefile
+31-123 files

LLVM/project 52cf94allvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU amdgpu-late-codegenprepare.ll widen_extending_scalar_loads.ll

[AMDGPU] Drop !noundef when widening sub-DWORD constant loads (#201085)

The widened i32 load reads bytes outside the original sub-DWORD load, so
new op cannot claim !noundef
DeltaFile
+59-0llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
+17-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+16-0llvm/test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll
+7-8llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+5-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+2-2llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
+106-106 files

LLVM/project 0fd2402offload/ci hip-tpl.py

[HIP] Remove explicit compiler-rt from bot recipe (#201329)

The same change was done to the AnnotatedBuilder script recently. Let's
keep them in sync.
https://github.com/llvm/llvm-zorg/pull/861
DeltaFile
+0-1offload/ci/hip-tpl.py
+0-11 files

LLVM/project cf1e507llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange function-attr.ll

[LoopInterchange] Bail out if function that may diverge is called
DeltaFile
+16-40llvm/test/Transforms/LoopInterchange/function-attr.ll
+4-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+20-422 files

LLVM/project 1a3e053llvm/lib/Transforms/Scalar LoopInterchange.cpp

address review
DeltaFile
+2-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+2-21 files

LLVM/project b1d5d7ellvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/AArch64 conditional-branches-cost.ll

[VPlan] Don't use the legacy cost model for loop conditions (#156864)

The current behaviour of using the legacy cost model for instructions
that compute the loop exit condition gets the wrong result when the loop
has been transformed to use a different exit condition, e.g. when have
tail-folded predicated vectorization the exit condition is based on the
predicate vector.

Fix this by adding cost computation for BranchOnCount and removing the
restriction on computing the cost for scalar ICmp/FCmp, and removing the
use of the legacy cost model for loop exit conditions.

This causes quite a lot of changes to expected output in tests. Some of
these are just changes to the -debug output, others are choosing a
different VF due to previously over or under-estimating the cost, and in
others the minimum trip count has changed as we now compute the cost for
compares in the middle block.
DeltaFile
+35-35llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+20-20llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
+0-39llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+27-9llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
+22-12llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+8-16llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
+112-1316 files not shown
+150-17812 files

LLVM/project 906968bllvm/test/Transforms/LoopInterchange function-attr.ll

[LoopInterchange] Add tests for func attributes called in loops (NFC) (#201331)

LoopInterchange has special handling for call instructions. In general,
loops that contain call instructions are not legal to interchange, but
if a call satisfies certain conditions, we allow the interchange to
proceed. Currently, the legality checker only verifies whether the call
reads or writes memory. However, as pointed out in
https://github.com/llvm/llvm-project/pull/200828#issuecomment-4593914293,
we also need to ensure that the call does not diverge. Otherwise, an
illegal interchange may occur.
This patch adds test cases that demonstrate the issue, which will be
fixed in a follow-up patch.
DeltaFile
+172-2llvm/test/Transforms/LoopInterchange/function-attr.ll
+172-21 files

LLVM/project d67b41allvm/test/CodeGen/X86 clmul-vector.ll

[X86] Add clmul vector allones baseline tests for #200592 (#201321)
DeltaFile
+13,610-111llvm/test/CodeGen/X86/clmul-vector.ll
+13,610-1111 files

FreeBSD/ports 996ff2fmisc/crush distinfo Makefile

misc/crush: Update to 0.75.0

Changelog: https://github.com/charmbracelet/crush/releases/tag/v0.75.0

Reported by:    GitHub (watch releases)
DeltaFile
+5-5misc/crush/distinfo
+1-1misc/crush/Makefile
+6-62 files

OPNSense/core ce499a9src/opnsense/mvc/app/views/OPNsense/Firewall nat_rule.volt

The other NAT pages should also be allowed to unhide their grid
DeltaFile
+7-2src/opnsense/mvc/app/views/OPNsense/Firewall/nat_rule.volt
+7-21 files

LLVM/project d3b2471flang/lib/Semantics resolve-directives.cpp

Update resolve-directives.cpp
DeltaFile
+2-0flang/lib/Semantics/resolve-directives.cpp
+2-01 files

LLVM/project 799af5dllvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp, llvm/test/CodeGen/AArch64 arm64-vcnt.ll

[AArch64][GlobalISel] Add handling for cls intrinsic (#200440)

Neon intrinsic neon.cls wasn't linked to the generic node G_CTLS.
Add in this link in Legalisation (LegalizeIntrinsic), to allow the intrinsic to properly lower.
DeltaFile
+32-12llvm/test/CodeGen/AArch64/arm64-vcnt.ll
+2-0llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+34-122 files

LLVM/project 92e40d8flang/lib/Semantics check-omp-variant.cpp check-omp-metadirective.cpp, llvm/lib/LTO LTO.cpp

Merge branch 'main' into users/shiltian/reqd_work_group_size-verifier
DeltaFile
+0-1,898llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+754-0flang/lib/Semantics/check-omp-variant.cpp
+0-754flang/lib/Semantics/check-omp-metadirective.cpp
+694-0llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
+0-682llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+93-541llvm/lib/LTO/LTO.cpp
+1,541-3,875607 files not shown
+16,259-10,008613 files

LLVM/project 0cd33adflang/lib/Semantics symbol.cpp

Update symbol.cpp
DeltaFile
+1-1flang/lib/Semantics/symbol.cpp
+1-11 files

LLVM/project 27fd70fclang/include/clang/Basic LangOptions.h, clang/lib/AST ItaniumMangle.cpp RecordLayoutBuilder.cpp

[clang][NFC] Introduce `LangOptions::isCompatibleWith(ClangABI)` (#201067)

This slightly improves readability and reduces the probability of
off-by-one errors.
DeltaFile
+10-12clang/lib/AST/ItaniumMangle.cpp
+10-11clang/lib/AST/RecordLayoutBuilder.cpp
+8-8clang/lib/CodeGen/Targets/X86.cpp
+3-3clang/lib/Basic/TargetInfo.cpp
+3-3clang/lib/Sema/SemaDeclCXX.cpp
+4-0clang/include/clang/Basic/LangOptions.h
+38-374 files not shown
+42-4310 files

OPNSense/core 9969711src/opnsense/mvc/app/controllers/OPNsense/Kea/Api Leases6Controller.php ServiceController.php, src/opnsense/mvc/app/controllers/OPNsense/Monit/Api SettingsController.php

mvc: fix a few stale imports via linter
DeltaFile
+0-4src/opnsense/mvc/app/controllers/OPNsense/Kea/Api/Leases6Controller.php
+0-2src/opnsense/mvc/app/models/OPNsense/Interfaces/FieldTypes/VipNetworkField.php
+0-2src/opnsense/mvc/app/controllers/OPNsense/Wireguard/Api/GeneralController.php
+0-1src/opnsense/mvc/app/controllers/OPNsense/Monit/Api/SettingsController.php
+0-1src/opnsense/mvc/app/controllers/OPNsense/Wireguard/Api/ServiceController.php
+0-1src/opnsense/mvc/app/controllers/OPNsense/Kea/Api/ServiceController.php
+0-116 files not shown
+0-1712 files

OPNSense/core 2571f8cScripts class-import.sh

make: improve import linter for edge cases
DeltaFile
+2-1Scripts/class-import.sh
+2-11 files

LLVM/project 036babellvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange function-attr.ll

[LoopInterchange] Bail out if function that may diverge is called
DeltaFile
+16-40llvm/test/Transforms/LoopInterchange/function-attr.ll
+4-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+20-422 files

LLVM/project 0385a1bllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 avx512-trunc.ll avg-mask.ll

[X86] combineSelect - fold select(c,trunc(x),y) -> X86ISD::MTRUNC(x,y,c) for non-BWI targets (#201339)

Fixes #200617
DeltaFile
+9-20llvm/test/CodeGen/X86/avx512-trunc.ll
+5-6llvm/test/CodeGen/X86/avg-mask.ll
+9-0llvm/lib/Target/X86/X86ISelLowering.cpp
+23-263 files

FreeBSD/ports 5d154bfnet-mgmt/iprange Makefile, net-mgmt/iprange/files patch-268d7d8794f3f8a6c2d6f08dc4351e767990e683

net-mgmt/iprange: Backport fix for 32-bit platforms

I've added it as a local patch instead of using PATCHFILES because
upstream patch touches CMakeLists.txt, which is not present on release
tarball for some unknown reason.

Obtained from:  upstream 268d7d8794f3f8a6c2d6f08dc4351e767990e683
Sponsored by:   Rubicon Communications, LLC ("Netgate")
DeltaFile
+1,083-0net-mgmt/iprange/files/patch-268d7d8794f3f8a6c2d6f08dc4351e767990e683
+4-3net-mgmt/iprange/Makefile
+1,087-32 files

FreeBSD/ports fc5acc9mail/mblaze distinfo Makefile

mail/mblaze: Update to 1.4

Changelog: https://inbox.vuxu.org/mblaze/874iokb3sq.fsf@vuxu.org/

This 1.4 release mainly adds bugfixes and small improvements.

* mcom: $MBLAZE_EDITOR is prefered to configure the editor
* mless: support OpenBSD less without LESSOPEN
  (needs mlesskey.example-openbsd)
* magrep: support multibyte regexps.
* Bug fixes.
* Documentation improvements.

PR:             295796
Submitted by:   Nico Sonack <nsonack at herrhotzenplotz.de>
DeltaFile
+3-3mail/mblaze/distinfo
+1-2mail/mblaze/Makefile
+4-52 files

OpenBSD/ports otGwqJndevel/cargo-c distinfo crates.inc

   Update to cargo-c 0.10.23

   https://github.com/lu-zero/cargo-c/releases/tag/v0.10.23
VersionDeltaFile
1.16+268-206devel/cargo-c/distinfo
1.16+132-101devel/cargo-c/crates.inc
1.16+3-1devel/cargo-c/Makefile
+403-3083 files

LLVM/project 8943bfbllvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPURegisterBankInfo.cpp, llvm/test/CodeGen/AMDGPU dynamic_stackalloc.ll amdgpu-cs-chain-fp-nosave.ll

[AMDGPU] Do not scale private alloca size when using flat-scratch (#201142)

When using flat-scratch, the `scratch_load/scratch_store` instructions
scale the stack offset by the wavefront size on their own.

Scaling the alloca-size by the wave-front size lead to accesses outside
of the private-memory limit.
DeltaFile
+99-134llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+24-32llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
+20-9llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5-16llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
+16-4llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+8-8llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
+172-2031 files not shown
+176-2117 files

FreeBSD/ports bfa4ce2misc/py-litellm distinfo Makefile, misc/py-litellm/files patch-pyproject.toml

misc/py-litellm: Update to 1.87.0

Changelog: https://github.com/BerriAI/litellm/releases/tag/v1.87.0

Reported by:    Repology
DeltaFile
+3-3misc/py-litellm/distinfo
+1-1misc/py-litellm/Makefile
+1-1misc/py-litellm/files/patch-pyproject.toml
+5-53 files

OPNSense/core 6986e49src/opnsense/mvc/app/views/OPNsense/Firewall nat_rule.volt

Hide grid when snat_mode is disabled
DeltaFile
+27-7src/opnsense/mvc/app/views/OPNsense/Firewall/nat_rule.volt
+27-71 files

NetBSD/pkgsrc-wip 3eb0c1fpy-mfusepy Makefile PLIST, py-mfusepy/patches patch-mfusepy.py

mfusepy: Add version 3.1.1

mfusepy is a Python module that provides a simple interface to FUSE
and macFUSE. It's just one file and is implemented using ctypes to use
libfuse.

mfusepy is a fork of fusepy (named py-fuse-bindings in pkgsrc).  The
main differences are support for the FUSE 3 API and efficiency
improvements.
DeltaFile
+51-0py-mfusepy/patches/patch-mfusepy.py
+17-0py-mfusepy/Makefile
+9-0py-mfusepy/PLIST
+7-0py-mfusepy/DESCR
+6-0py-mfusepy/distinfo
+3-0py-mfusepy/TODO
+93-06 files

LLVM/project 89d4276llvm/docs/AMDGPU AMDGPUAsmGFX12.rst, llvm/lib/Target/AArch64 AArch64SystemOperands.td

Merge branch 'main' into users/kparzysz/w02-declare-target-mod
DeltaFile
+1,087-1,602llvm/docs/AMDGPU/AMDGPUAsmGFX12.rst
+1,044-1,044llvm/lib/Target/AArch64/AArch64SystemOperands.td
+516-1,543llvm/test/Transforms/GVN/PRE/rle.ll
+0-1,898llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+887-803llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+855-771llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+4,389-7,6612,103 files not shown
+62,627-40,0482,109 files