TableGen: Only build the register bank in CallingConvEmitter when needed
CallingConvEmitter built the register bank to find registers named by
strings, which only CCAssignToRegTuple uses. No target does, but
building the register bank is most of the work for targets with many
registers. Build it when the first register name is looked up instead.
All 16 CallingConv tablegen runs in an LLVM build with all targets:
Gigainstructions Gigacycles CPU seconds
Before 73.5 43.4 15.1
After 47.1 (-35.9%) 27.7 (-36.2%) 10.2 (-32.2%)
For AMDGPU alone, the run executes 63% fewer cycles.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
RISCV: Use minimal tablegen inputs for TargetParser (#239104)
Generate RISCVTargetParserDef.inc from a reduced td file which
includes only the features, profiles and processors, instead of all of
RISCV.td. The processors reference scheduling models, which are
defined with the scheduling information for the instructions, so the
new file defines empty placeholder models instead, as was done for
AArch64 in #231954.
RISCV was the last TargetParser input that parsed the full target, and
took 1.74 of the 1.78 seconds spent in the TargetParser tablegen jobs.
llvm-min-tblgen -gen-riscv-target-def, mean of 5 runs
Gigainstructions Seconds Peak RSS .td deps
RISCV.td 7.47 1.74 407 MB 139
RISCVTargetParserDef.td 0.04 0.01 7 MB 9
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
RISCV: Define macro fusion features separately from predicates (#239103)
Move the fusion tuning features to RISCVFeatures.td with the other
tuning features, and attach the predicates with SimpleFusionFor and
FusionFor. The features no longer depend on the instruction definitions.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Allow macro fusion predicates for a separate subtarget feature (#239102)
Fusion defines a subtarget feature and its fusion predicates in a single
record. The predicates reference instructions, so the feature can't be
defined without the instruction definitions. Add FusionFor and
SimpleFusionFor to attach fusion predicates to a SubtargetFeature
defined elsewhere.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
comms/wsjtx: Update to 3.0.1
Release: WSJT-X 3.0.0-rc1
September 15, 2025
-------------------------
WSJT-X 3.0.0 introduces a number of new features and capabilities.
Release Candidates give advanced users an opportunity to exercise
new features and provide feedback to developers. If you use this
Release Candidate 1, please send related comments or questions to
one of our user forums.
The following features will be already familiar to those using one of
the WSJT-X Improved 2.8.0 i+ editions, but new to users of WSJT-X
2.7.0 and all earlier versions:
- Single-click Band Buttons can be enabled from the View menu.
- Filters can be used to suppress the display of various categories
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[flang] Fix references to a LOCAL variable of an enclosing DO CONCURRENT (#238647)
A `REDUCE` locality-spec on a nested `DO CONCURRENT` that names a
variable with `LOCAL` or `LOCAL_INIT` locality in the enclosing `DO
CONCURRENT` crashes lowering:
```fortran
subroutine s(n, nz, work)
integer :: n, nz, work(nz), j, k, tmp
do concurrent (k=1:nz) local(tmp)
tmp = 0
do concurrent (j=1:n) reduce(max:tmp)
tmp = max(tmp, j)
end do
work(k) = tmp
end do
end subroutine
```
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e6000sw: Write the value, not the register, in Clause 45 writes
e6000sw_write_xmdio() loaded the Clause 45 register address into the
SMI PHY data register a second time, where the value to write belongs,
so every Clause 45 write stored the register address.
Its only caller, e6000sw_serdes_power(), runs at attach for ports 9 and
10 of the 88E6190 and 88E6190X to power one SERDES interface up and the
other down. It wrote 0x2000 to the SGMII control register and 0x1000
to the 10GBASE-R PCS control register instead, so neither interface was
powered down and the rest of each register was overwritten.
Fixes: 9aba06377d26 ("Add support for the Marvell 88E6190 11 ports switch.")
Sponsored by: Rubicon Communications, LLC ("Netgate")
security/vuxml: Document Elixir vulnerabilities
- add CVE-2026-109821 for URI.parse port limits
- add CVE-2026-115274 for JSON integer decoding beyond float64 range
- mark elixir before 1.18.6 and 1.19.7, and elixir-devel before 1.20.5
- add CVE-2026-97209 for mix deps.partition config, elixir-devel only
Sponsored by: SkunkWerks, GmbH
x11-fonts/rubik: Add Rubik font family
- add sans-serif font family with slightly rounded corners
- distribute the variable Roman and Italic fonts from the googlefonts
upstream, pinned to the e337a5 commit ("New binaries")
- supports Latin, Cyrillic, Hebrew, and Arabic scripts
Sponsored by: SkunkWerks, GmbH
[BOLT] Connect inlined e843419 veneer block to its return target (#238108)
When an lld Cortex-A53 erratum 843419 veneer is inlined, the branch
being replaced is a tail call, so its block has no successors in the
CFG. The block then ends in the veneer's load/store with no edge to
the veneer's branch-back target. Block reordering and splitting are
free to separate the two, and fixBranches adds no branch, because a
block with no successors has no fall-through to fix up: execution
runs into whatever was laid out next.
Record the edge when inlining, and only inline over a branch that is
the block's unconditional terminator, which is what lld writes in
place of the patched load/store.
[clang][DepScan] Support subdirectory seach in getModuleMapsForModules (#238860)
Respect resolving modulemaps with
`-fmodulemap-allow-subdirectory-search` in `getModuleMapsForModules` to
match the normal scan's lookup. Note this option is default disabled.
[BOLT] Handle relative vtable slots covered by WPD aliases (#238065)
A PC-relative relocation in read-only data will be treated as a relative
vtable slot and resolved against its function symbol if and only if the
innermost data symbol containing it is a vtable. Otherwise BOLT will
treat it as a reference to S+A.
With ThinLTO split LTO units, WPD could export a hidden alias symbol
`__typeid_<id>_<offset>_unique_member` at a vtable's address point. It
inherits the vtable's size, so it extends past the vtable, is not nested
under it, and is the innermost symbol for the slots. A slot's addend is
its offset from the address point, so S+A can land inside the target
function, which is then incorrectly interpreted as having an unclaimed
internal reference and marked as non-simple.
The fix is to keep an address-sorted index of vtables, filled when
symbols are registered, and look up the vtable containing a slot
directly. Vtables do not overlap, so only the last one starting at or
before the slot can contain it. This would also handle any new kind of
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[CodeGen] Overwrite a 0 sized alloca to have same number of bytes as it's Frame Object (#232755)
Fix: instruction selection rounds a zero-sized `alloca`'s frame object
up to one byte without updating the `alloca`, leading to bad alias
information and wrong access conclusions in BasicAA.
---
#### Context
I ran into a bug where StackColoring (on a mix of C and Rust codebase)
would collapse 1 byte LLVM IR alloca into other 0 byte LLVM IR allocas
but their FrameObject would have a min-size of 1 byte. However, when
BasicAA runs it reads the LLVM IR `alloca` to get the size, and not the
Frame Object. The LLVM IR alloca would still show 0 bytes, and this can
break BasicAA's conclusions about whether two accesses can touch the
same memory and results in bad program behaviour (e.g. wrong values,
hangs, crashes, deadlocks, etc).
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[AMDGPU] Move the bitcast cost comments, document the i1 mask test
Put the comment about the scalarized parts of a vector bitcast above
the size check, and the comment about the shared registers inside it.
Say in the test which case @i1_mask covers.
Assisted-by: Claude Opus
[AMDGPU] Treat a bitcast between legal types as free
The generic cost model treats a bitcast as free only when both types
are integer types or both are not. AMDGPU keeps integer and
floating-point values in the same registers, so a bitcast between two
legal types is a no-op. A scalar bitcast from i32 to float cost 1, but
the vector bitcast from <2 x i32> to <2 x float> cost 0. The SLP
vectorizer counted this difference as a saving.
A bitcast that involves a type the target legalizes, such as a vector
of i8, keeps its cost, because the lanes may need repacking.
Assisted-by: Claude Opus
[AMDGPU][NFC] Add bitcast cost tests for legalized types and pointers
Add bitcasts that involve types the target legalizes, such as vectors
of i8, i24 and <2 x i24>, and bitcasts of pointers. Add a gfx7 RUN
line, where i16 and <2 x i16> are not legal.
Assisted-by: Claude Opus
[AMDGPU][NFC] Add tests for bitcasts between integer and FP types
Add cost model tests for bitcasts between integer and floating-point
types of the same size, as scalars and as vectors. Add an SLP test that
stores a pair of values bitcast from i32 to float.
Assisted-by: Claude Opus
[PseudoProbe] Avoid OOB in pseudo probe search (#239082)
There's an OOB access if `GUIDProbeFunctionMap` tries to find an invalid
GUID that over the biggest GUID. `lower_bound` returns the end of
vector, which makes the dereference invalid.
Assisted by: Opus 5.5
[libc++] Rewrite some std::allocator verify tests (#238802)
They were written in a way that makes it look like they are executed,
when in reality they aren't.
The underlying motivation for rewriting is that some of the verify
checks were written inside `assert(...)`, which made them fail if the
`assert` macro expands to nothing or expands to something that evaluates
the expression twice (both of which are terrible implementations of
assert).
Assisted by Claude
