AMDGPU: Migrate unittests to subarch triples (#206486)
Replace specifying a processor name with the triple
subarch.
The register-limit helpers in AMDGPUUnitTests.cpp that enumerate every
valid CPU via fillValidArchListAMDGCN still pass the CPU explicitly, as
does the MC Disassembler smoke test (its C disassembler API derives the
subtarget from the CPU, not the triple subarch).
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[flang][PFT-to-MLIR] Wrap unstructured Fortran constructs in scf.execute_region
Extend the PFT-to-MLIR (HLFIR/FIR) lowering so unstructured DO and IF
constructs are emitted inside scf.execute_region, hiding their multi-block
CFG behind a single op. OpenACC and OpenMP lowerings that reject
multi-block content (e.g. the "unstructured do loop in combined acc
construct" TODO in OpenACC.cpp) now see a structured op instead.
Flag: -mmlir --wrap-unstructured-constructs-in-execute-region (default on).
An evaluation is wrappable iff all of the following hold:
* wrap flag on
* eval is parser::DoConstruct or parser::IfConstruct
* eval.isUnstructured
* branchesAreInternal(eval) -- every controlSuccessor in the subtree
targets a nested eval or the constructExit
* !hasIncomingBranch(eval) -- no outside eval branches into the body
(PFT's synthetic IfConstruct around `if(c) goto X` absorbs label
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Change NOTHING (which means only redraw the indicator) to MOVE. And
redefine NOTHING as /actually/ nothing. Use it for commands which
actually make no change. Fixes flickering due to excessive redrawing of
indicator lines. Mostly from Michael Grant.
[LLD][AArch64] Make adrp+ldr relaxation per-symbol all-or-nothing (#208396)
We can't relax only some adrp+ldr pairs for a symbol, because there may
be a branch target between the adrp and ldr of this form:
adrp x1, :got:sym
.Lfoo:
ldr x1, [x1, :got_lo12:sym]
# ...
adrp x1, :got:sym
ldr x2, [x1, :got_lo12:sym]
b .Lfoo
Relaxing the first adrp+ldr here would be invalid. This was clarified in
the ARM ABI in:
https://github.com/ARM-software/abi-aa/commit/11fb4ef42898060189d6a34ee96966e696ecbd20.
The implementation already performed a pre-scan to check that the
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devel/flexdock: unpin openjdk8
Builds fine with modern JDK.
Dependency math/scilab uses openjdk8 so this needs to generate
Java 8 compatible class files.
NB: I think upstream moved here: https://gitlab.com/scilab/forge/flexdock
NB2: Remove java:run as it is a library. The final application will decide
what JDK to run with, so no need to install multiple JDKs.
Approved-by: no maintainer
[BOLT] Fix use-old-text-zero-padding on FreeBSD (#206581) (#208634)
BSD od supports only decimal value to -N parameter. To fix the test
failure, we use decimal value instead of hex value in this test case.
Co-authored-by: aokblast <aokblast at FreeBSD.org>
[BOLT] Fix use-old-text-zero-padding on FreeBSD (#206581)
BSD od supports only decimal value to -N parameter. To fix the test
failure, we use decimal value instead of hex value in this test case.
[ImplicitNullChecks] Preserve debug location on FAULTING_OP (#205560)
insertFaultingInstr() built the FAULTING_OP with an empty DebugLoc,
dropping the folded memory op's source location. As a result, the
faulting load is mislabeled in the line table, giving wrong source
attribution for the very instruction that traps on a null deref. Fix by
using MI->getDebugLoc().
The original report also flagged dropped MIFlags and def renamable/
sub-register/early-clobber bits, but those are not observable:
Unpredictable is never set on loads, the register bits are never read
(FAULTING_OP is opaque until AsmPrinter), and the sub-register write is
already modeled correctly. Only the debug location is fixed here.
PR lib/59067 (wctrans got error member)
Patches from the OP (ru_j217) and from RVP - see the PR
This looks to be just correcting what appear to be simple
errors in the code.
XXX pullup -11
Tighten up parsing of paged search controls in search results so we error
out if the control is badly formed rather than trusting that it contained
the right elements.
some problems pointed out by Frank Denis, some more identified after that
ok jan@
[Flang][OpenMP] Added diagnostic for ORDERED THREADS SIMD inside plain SIMD region (#205723)
Fixes [#205516 ](https://github.com/llvm/llvm-project/issues/205516)
#### Problem
Per OpenMP 4.5 Sec 2.13.8 Restrictions:
> An ordered region arising from an ordered construct with both the simd
and
> threads clauses must be closely nested inside a loop SIMD region.
Flang was missing this check. `!$OMP ORDERED THREADS SIMD` inside a
standalone `!$OMP SIMD` region was accepted without diagnostic.
#### Fix
`check-omp-structure.cpp`: Added a new check in
`ChecksOnOrderedAsBlock()`. If an ORDERED directive has both SIMD and
THREADS clauses and is nested inside a standalone SIMD region (but not a
DO SIMD region), emit the following error:
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[orc-rt] Add a coding conventions doc (#208623)
Add docs/CodingConventions.md, recording that ORC-RT follows the LLVM
Coding Standards and describing the C API naming conventions.
games/open-adventure: upgrade to version 1.22
Major changes in this version:
- Code hardening by chatGPT 5.5.
- Eliminate FORTRAN legacy 1-based indexing; required save version bump.
- Improved documentation of build dependencies.
'pfctl -s all' should not dump all OS fingerprints loaded to pf(4)
The '-s all' pfctl(8) option is supposed to report only the number
of OS fingerprints loaded to kernel instead. The issue was noticed
and kindly reported by David Adams (support _at_ tarma _dot_ com).
This is 7.9 regression.
OK @jsg
[mlir][emitc] Fix hasSideEffects of emitc.cast (#208607)
When `pure` attribute is set, the cast op is side-effect-free, so we
should return false in `hasSideEffects` method.
ipfw nat: Add assertion that mbuf is not a chain
Discarding m_free's return value will result in an mbuf leak if the mbuf
was in a chain.
In general we should use m_freem if the mbuf may be in a chain, or
assert that the return was NULL. There will not be a chain here due to
m_megapullup, so add an assert.
Reviewed by: ae
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D57479
(cherry picked from commit b16c731b0191d6c47de46a3c6057b0c5ec0dd420)
[AMDGPU] Fix scratch address materialization in SVS frame index fallback
The flat scratch SVS frame index fallback folded the offset in with
V_ADD_U32_e32 writing into FrameReg (an SGPR, an illegal VALU destination)
and added it to FrameReg instead of the scavenged VGPR used as vaddr, so the
offset never reached the address.
Materialize FrameReg + Offset into the scavenged VGPR instead, or just the
offset when there is no frame register.
NFC in practice: for flat scratch an SGPR saddr is always legal, so the
fallback is only entered with no frame register, where the behavior is
unchanged. The FrameReg != 0 path is currently unreachable.
Co-authored-by: Cursor <cursoragent at cursor.com>
Properly fix the libc build
I had this change in early testing, but convinced myself it couldn't
possibly be required, so deleted it - and all worked. But that's
because I do update builds, and this extra dependency required after
the first build.
It shouldn't be required ever, it is insane, but there will shortly
be a PR about that! For now, this does no harm.
