[GlobalISel][AMDGPU] Expand `isKnownNeverZero` for vector instructions (#211149)
A followup PR about adding some vector instruction patterns to
`isKnownNeverZero`, which firstly added in
https://github.com/llvm/llvm-project/pull/198438
The following instructions are added:
* `G_BUILD_VECTOR`
* `G_EXTRACT_VECTOR_ELT`
* `G_SHUFFLE_VECTOR`
[AMDGPU] Reschedule loads in clauses to improve throughput (#102595)
After clauses are formed their internal loads can be reordered to
facilitate some additional opportunities for overlapping computation.
This late stage rescheduling causes no change in register pressure.
pci: Ignore SR-IOV VFs when tuning MPS
The VF Device Control MPS and MRRS fields are reserved and preserved.
VF transactions use the PF MPS, so a hardwired VF value must not be
used to retune the shared PCIe hierarchy.
Document the previously undocumented tuning knob and clarify why a VF
may continue to display its reserved hardwired value.
This fixes an instant crash/reboot on my Zen3 system with 82599 VFs.
MFC after: 1 week
[LoongArch] Use unsigned vector extract for zero extension (#214120)
Add patterns to select VPICKVE2GR_BU/HU and [X]VPICKVE2GR_WU for vector
extraction followed by zero extension, eliminating redundant masking
instructions.
ixv: reconcile VLAN filters through the mailbox
VLAN registration callbacks only update the software shadow, leaving
the PF unaware until a later full initialization. Initialization then
retries each failed request in a tight loop, while skipping replay
entirely when local hardware filtering is disabled.
Send additions and removals as soon as the desired state changes,
independent of the VF local-filter capability. Replay the desired
memberships after reset and retry a bounded batch per timer tick. Stop
after the first failure so a silent PF can consume only one mailbox
timeout per pass, while a responsive PF can drain several requests.
Treat the retry window as a no-progress deadline: advance it when
pending work succeeds so a large backlog can drain, but leave entries
dormant after a sustained failure.
A successful mailbox request wakes a dormant backlog. Dispatch
timer-driven retries only while iflib marks the VF running, so a stale
timer tick cannot restore PF VLAN state after the stop path resets the
[14 lines not shown]
Merge tag 'mm-hotfixes-stable-2026-08-06-18-44' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
Pull MM fixes from Andrew Morton:
"17 hotfixes. 15 are cc:stable. 16 are for MM.
There's a patch series from Lorenzo "mm: fix UAF caused by race
between ptdump and vmap pgtable freeing" which addresses a quite old
bug in the ptdump code.
And another series also from Lorenzo which fixes a four year old bug
in the huge_zero_folio handling.
A series from SJ fixes a few possible divide-by-zero issues which
Sashiko sniffed out. And a series which fixes handling of the
commit_inputs parameters.
The remainder are singletons, please see their changelogs for details"
* tag 'mm-hotfixes-stable-2026-08-06-18-44' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm:
[17 lines not shown]
Merge tag 'v7.2-rc6-smb3-server-fixes' of git://git.samba.org/ksmbd
Pull smb server fixes from Steve French:
- Reject Pattern_V1 payloads when Pattern_V1 support was not
negotiated
- Validate compression transform flags and chained mode before
allocating the decompression buffer
- Enforce the pre-authentication PDU size limit before allocating
the decompression buffer, preventing compressed requests from
bypassing the limit
* tag 'v7.2-rc6-smb3-server-fixes' of git://git.samba.org/ksmbd:
ksmbd: apply the pre-authentication PDU limit when decompressing
ksmbd: validate compression Flags before kvmalloc
smb: compress: reject Pattern_V1 when not negotiated
[RISCV][CostModel] Fix invalid cost for vector select on targets without FP vector support (#183158)
Fixes #182047
**Issue:** Compiling floating-point vector selects (e.g., `<2 x float>`)
on RISC-V targets that only support integer vectors (like `zve32x`)
causes a compiler crash in the Loop Vectorizer (`emitInvalidCostRemarks`
unhandled `TypeSwitch`).
**Root Cause:** The Type Legalizer correctly scalarizes the unsupported
FP vector into `f32` operations. However,
`RISCVTTIImpl::getCmpSelInstrCost` attempted to cost
`Instruction::Select` natively without verifying floating-point vector
hardware support. It passed the scalarized type to
`getRISCVInstructionCost` to price a native vector merge instruction,
which returned `InstructionCost::getInvalid()`.
**Fix:** Added hardware support checks (`hasVInstructionsF16/32/64()`)
for floating-point types in the `Instruction::Select` block. If the
[9 lines not shown]
powerpc/pmap: Support booke64 kernel pmap growing
In preparation of increasing the KVA on powerpc64 to 2TB to mirror
amd64's, rework the 64-bit Book-E pmap to not allocate all page table
pages at boot time, since that would be a waste of a lot of memory.
Instead, allocate all page table pages for the higher levels, leaving
the leaves (page directories) for dynamic allocation. This cuts the
boot-time page table size down from ~64MB to ~8MB with the current 32GB
KVA size, and bumping to 2TB KVA the boot-time page table is still ~8MB
instead of ballooning to ~4GB of mostly wasted space.
[Clang][CodeGen] Respect FP pragma options for fneg and calls (#212141)
Apply expression-specific floating-point options when emitting fneg and
call instructions.
This prevents these instructions from retaining fast-math flags disabled
by local FP pragmas, such as #pragma clang fp reassociate(off).
Fixes #51905
[Docs][AMDGPU] fully specify volatile accesses in the memory model (#214168)
A non-atomic volatile access on AMDGPU includes store-available or
load-visible
semantics at the widest scope supported by its address space:
- system scope for global/generic,
- workgroup scope for local (LDS)
An atomic volatile access has the same availability and visibility as
its atomic
non-volatile variant.
Previous Reference: 2f499b9
This fully specifies the behavior that the LLVM memory model leaves
target-dependent, matching the implementation in SIMemoryLegalizer.
Assisted-By: Claude Opus 4.8
Deal with the absolutely pathological handling of the IDENTIFY command
on big-endian systems.
In wdc_datain_pio(), in the ATA_DRIVE_NOSTREAM case, if the bus.h
implementation does does not have __BUS_SPACE_HAS_STREAM_METHODS
and the system is _BIG_ENDIAN, individually swap each 16-bit value
rather than assuming the bus_space_read_*2() implementation will do
it.
This is necessary because IDENTIFY is treated differently than every
other command; all callers assume it will be returned in host-order,
when in reality it's an array of 256 16-bit little-endian integers (even
the string fields).
Ultimately, the correct fix is to stop special-casing IDENTIFY, but
that is a much larger change due to the confusing array of flags that
control I/O size and disposition, and requires much wider testing.
[LoongArch] Use unsigned vector extract for zero extension
Add patterns to select VPICKVE2GR_BU/HU and [X]VPICKVE2GR_WU for vector
extraction followed by zero extension, eliminating redundant masking
instructions.
[BOLT] Support runtime libraries built as thin archives (#214292)
In some configurations, BOLT runtime libraries may be built as thin
archive. Use the more generic `Archive::create` to handle these.
