Add PISA register file, instruction set, and MC layer
Add the PISA register file and register-bank descriptions, the instruction
formats and definitions, and the MC/assembly layer (instruction printer,
register and code encoders, target streamer, MC target description and the
supporting enums), replacing the stub descriptions from
the initial target skeleton.
This provides the instruction-set description and assembly-emission
foundation. The GlobalISel lowering and instruction selection that consume it
are added in the following changes.
[clang][StaticAnalyzer] Add support for variables and fields in GetEnclosingDeclContextSignature
Function `getIssueHash` relies on the name of the enclosing
declaration of the issue Decl for hashing. But the underlying
function `GetEnclosingDeclContextSignature` does not compute the
enclosing declaration for variables or fields, causing missing HTML
reports despite text warnings being printed.
The added
`clang/test/Analysis/Checkers/WebKit/html-diag-dedup-members.cpp`
example is a reproducer of this kind of issue we observed in WebKit.
Also, `RawPtrRefLocalVarsChecker` and `RawPtrRefMemberChecker` never
called `Report->setDeclWithIssue()`. This commit fixes it.
rdar://183700416
Assisted-by: Claude sonnet
nvpair: Fix operator precedence
59dc88602e23a436440e4164c6d9401da8f0dff2 made a mistake when doing a
check, which can cause us to continue processing when we should return
EFAULT.
Reported-by: Grok 4.5 Build Beta
Reviewed-by: Alexander Motin <alexander.motin at TrueNAS.com>
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Richard Yao <richard at ryao.dev>
Closes #18874
[CIR] Change previous coroutine builtins to have their own coro intrinsic ops (#211699)
This PR introduces dedicated CIR operations for the coroutine intrinsics
(`coro.intrinsic.id`, `coro.intrinsic.alloc`, `coro.intrinsic.begin`,
`coro.intrinsic.free`, `coro.intrinsic.end`, `coro.intrinsic.size`)
instead of emitting them as calls to hand-created builtin functions.
LLVM IR already has its own dedicated ops for these cases, so this
follows the same pattern at CIR.
Along the way this also changes how coroutine builtins are handled in
`CIRGenBuiltin`: previously the intrinsics emitted automatically as part
of lowering `EmitCoroutineBody` and the ones triggered by an explicit
`__builtin_coro_*` call written in user source code were going through
the same path. This PR separates the two, since they're conceptually
different emission points.
New tests covering these builtins are included as well.
Also added explicit `errorNYI` messages for the remaining
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ZTS: don't read a command's exit status as a missing binary
log_neg_expect() treats an exit status of 127 as a missing binary and
fails before it looks at what the command printed. That is only a
convention of the shell, and a command is free to return 127 for its
own reasons. fio returns the number of jobs which failed, so a run of
127 failing jobs is reported as though fio were not installed.
no_space/enospc_rm fills a pool with 200 fio jobs and requires them to
fail with ENOSPC. How many of them get that far varies with timing,
and on the occasions it comes to exactly 127 the test fails with
fio ... unexpectedly exited 127 (File not found)
even though the output holds the expected message. A dozen runs here
landed between 183 and 199, and the failure seen in CI reported 127.
Only read 127 as a missing binary when the expected output is absent.
A command which printed what was asked of it plainly ran, so nothing
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[AMDGPU][GlobalISel] Use single B32 rule for permlane16
B32 already covers s32, <2 x s16> and 32-bit pointers, so one StandardB
fast rule replaces the separate S32, V2S16 and DivPtr32 rules. This
matches permlane_bcast/up/down/xor and permlane64, which have the same
overloaded intrinsic shape.
Change-Id: I770a93d5e75e68df704e84d7ad165fdd2cf2fc53
Add PISA target registration and backend stub
Register the Intel GPU portable ISA (PISA) target. Add the pisa Triple
arch, data layout, and a minimal MC/TargetMachine skeleton.
