LLVM/project 3c191d6 — llvm/lib/ObjectYAML ELFEmitter.cpp, llvm/test/tools/yaml2obj/ELF bb-addr-map-pgo-analysis-map.yaml

by Haohai Wen via GitHub on ⎇
[ObjectYAML] Fix yaml2obj crash when BBAddrMap entry has invalid feature (#201729)

Warn and skip the entry instead of dereferencing the Error-holding
Expected returned by Features::decode.
DeltaFile
+21-3llvm/test/tools/yaml2obj/ELF/bb-addr-map-pgo-analysis-map.yaml
+5-4llvm/lib/ObjectYAML/ELFEmitter.cpp
+26-72 files

LLVM/project d20eca1 — orc-rt/include CMakeLists.txt, orc-rt/include/orc-rt/sps-ci CallSPSCI.h

by Lang Hames via GitHub on ⎇
[orc-rt] Add initial call-function SPS CIs. (#202860)

Adds orc_rt_call_void_void and orc_rt_call_main, which can be used to
call functions with `void(void)` and `int(int, char*[])` signatures,
respectively.
DeltaFile
+116-0orc-rt/unittests/CallSPSCITest.cpp
+61-0orc-rt/lib/executor/sps-ci/CallSPSCI.cpp
+26-0orc-rt/include/orc-rt/sps-ci/CallSPSCI.h
+1-0orc-rt/include/CMakeLists.txt
+1-0orc-rt/lib/executor/CMakeLists.txt
+1-0orc-rt/unittests/CMakeLists.txt
+206-06 files

LLVM/project edd3e4f — clang/include/clang/Basic BuiltinsAMDGPU.td, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

by Aaditya on ⎇
[AMDGPU] Add builtins for wave reduction intrinsics

Assisted by - Claude-sonnet:4.6
DeltaFile
+189-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+18-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+9-0clang/include/clang/Basic/BuiltinsAMDGPU.td
+216-03 files

LLVM/project 60b6529 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

by Aaditya on ⎇
Modify test run lines
DeltaFile
+154-74llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+134-64llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+134-64llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+422-2023 files

LLVM/project 6d3d523 — clang/test/Sema wave-reduce-builtins-validate-amdgpu.cl

by Aaditya on ⎇
Missing SEMA tests
DeltaFile
+26-0clang/test/Sema/wave-reduce-builtins-validate-amdgpu.cl
+26-01 files

LLVM/project a2315b5 — llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

by Aaditya on ⎇
Promote at legalization
DeltaFile
+32-25llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+25-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+25-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+4-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+90-665 files

LLVM/project 2e39890 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

by Aaditya on ⎇
[AMDGPU] Support Wave Reduction for true-16 types - 2

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+87-39llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+79-35llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+166-742 files

LLVM/project dbb421f — llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.and.ll llvm.amdgcn.reduce.or.ll

by Aaditya on ⎇
Use only SALU opcodes
DeltaFile
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+1-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+40-444 files

LLVM/project b902772 — llvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.min.ll

by Aaditya on ⎇
Use `REG_SEQUENCE` instead of `COPY`
Use SALU opcodes for all reductions
DeltaFile
+1-2llvm/lib/Target/AMDGPU/SIInstructions.td
+1-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+2-22 files

LLVM/project afee918 — llvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.umax.ll llvm.amdgcn.reduce.umin.ll

by Aaditya on ⎇
[AMDGPU] Support Wave Reduction for true-16 types - 1

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `min`, `umin`, `max`, `umax`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+162-53llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+134-64llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+63-29llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+63-28llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+2-1llvm/lib/Target/AMDGPU/SIInstructions.td
+0-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+424-1766 files

LLVM/project b839e57 — llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.or.ll

by Aaditya on ⎇
[AMDGPU] Support Wave Reduction for i16 types - 3

Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+591-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+491-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+491-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+8-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1,581-4334 files

LLVM/project 65e7673 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.or.ll llvm.amdgcn.reduce.xor.ll

by Aaditya on ⎇
Drop unsed test prefixes
DeltaFile
+16-21llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+16-21llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+16-21llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+48-633 files

LLVM/project 8db3a2f — llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

by Aaditya on ⎇
Promote at legalization
DeltaFile
+24-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+24-15llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+6-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-2llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+60-374 files

LLVM/project ab2f87c — llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

by Aaditya on ⎇
[AMDGPU] Support Wave Reduction for i16 types - 2

Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+642-177llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+621-173llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+2-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1,265-3503 files

LLVM/project 83c18d0 — llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp

by Aaditya on ⎇
Move variable decl to inner if-statement.
DeltaFile
+2-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+3-32 files

LLVM/project ac71616 — llvm/lib/Transforms/Utils LoopUtils.cpp, llvm/test/Transforms/LoopVectorize minmax-reduction-unknown-prof.ll

by Madhur Amilkanthwar via GitHub on ⎇
[LoopUtils] Mark createMinMaxOp's new select with unknown branch weights (#201750)

`createMinMaxOp()` lowers an FP min/max reduction to a freshly built
fcmp+select. That select is not derived from any existing branch, so it
carries no real profile data, and prof-verify reports a "select
annotation missing" failure. Mark the synthesized select's branch
weights as explicitly unknown when the enclosing function is profiled,
guarded by the existing profcheck-disable-metadata-fixes option.

Add a unit test covering the profiled and non-profiled cases.
DeltaFile
+156-0llvm/test/Transforms/LoopVectorize/minmax-reduction-unknown-prof.ll
+4-0llvm/lib/Transforms/Utils/LoopUtils.cpp
+160-02 files

LLVM/project a46c5ee — llvm/lib/Support GlobPattern.cpp

by Vitaly Buka via GitHub on ⎇
[NFC][Support] Refactor bracket parsing in GlobPattern (#202848)

Extract BitVector from Expected before flipping to
prepare for future modifications.

Assisted-by: Gemini
DeltaFile
+8-6llvm/lib/Support/GlobPattern.cpp
+8-61 files

LLVM/project 8b25b86 — bolt/docs profiles.md, bolt/include/bolt/Profile DataAggregator.h

by Amir Ayupov on ⎇
rebase

Created using spr 1.3.8-beta.1
DeltaFile
+27-0bolt/unittests/Profile/DataAggregator.cpp
+15-7bolt/lib/Profile/DataAggregator.cpp
+11-6bolt/test/X86/pre-aggregated-records.s
+2-1bolt/include/bolt/Profile/DataAggregator.h
+1-1bolt/docs/profiles.md
+56-155 files

LLVM/project a3ae9a6 — bolt/docs profiles.md, bolt/include/bolt/Profile DataAggregator.h

by Amir Ayupov on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+27-0bolt/unittests/Profile/DataAggregator.cpp
+11-6bolt/test/X86/pre-aggregated-records.s
+11-2bolt/include/bolt/Profile/DataAggregator.h
+6-3bolt/lib/Profile/DataAggregator.cpp
+2-2bolt/docs/profiles.md
+57-135 files

FreeBSD/ports ad096bc — shells/bash distinfo Makefile

by Emanuel Haupt (ehaupt) on ⎇
shells/bash: Update to 5.3.15
DeltaFile
+7-1shells/bash/distinfo
+1-1shells/bash/Makefile
+8-22 files

NetBSD/xsrc OkSNQum — external/mit/libdrm/dist xf86drm.c, external/mit/libdrm/dist/amdgpu amdgpu.h amdgpu_vamgr.c

by mrg on ⎇
   merge libdrm 2.4.134
VersionDeltaFile
1.6+154-0external/mit/libdrm/dist/amdgpu/amdgpu.h
1.16+87-12external/mit/libdrm/dist/include/drm/drm.h
1.35+79-7external/mit/libdrm/dist/xf86drm.c
1.6+50-3external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c
1.8+44-2external/mit/libdrm/dist/amdgpu/amdgpu_bo.c
1.21+24-7external/mit/libdrm/dist/tests/modetest/modetest.c
+438-3128 files not shown
+475-3734 files

NetBSD/xsrc G4AFnpu — external/mit/libdrm/dist/amdgpu amdgpu_asic_id.c, external/mit/libdrm/dist/data amdgpu.ids

by mrg on ⎇🏷
   initial import of libdrm-2.4.134
VersionDeltaFile
1.1.1.9+303-1external/mit/libdrm/dist/tests/util/pattern.c
1.1.1.14+300-0external/mit/libdrm/dist/include/drm/amdgpu_drm.h
1.1.1.11+230-32external/mit/libdrm/dist/include/drm/drm_fourcc.h
1.1.1.13+207-44external/mit/libdrm/dist/data/amdgpu.ids
1.1.1.4+189-5external/mit/libdrm/dist/amdgpu/amdgpu_asic_id.c
1.1.1.16+193-1external/mit/libdrm/dist/include/drm/drm_mode.h
+1,422-8341 files not shown
+2,263-21147 files

LLVM/project 51b373c — clang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-vector-callingconv-llvm-ir.c riscv-vector-callingconv-llvm-ir.cpp

by Vitaly Buka on ⎇
rebase

Created using spr 1.3.7
DeltaFile
+14-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+5-5llvm/lib/Support/GlobPattern.cpp
+8-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+2-2llvm/include/llvm/Support/GlobPattern.h
+2-1clang/lib/CodeGen/Targets/RISCV.cpp
+31-85 files

LLVM/project e4f2e11 — clang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-vector-callingconv-llvm-ir.c riscv-vector-callingconv-llvm-ir.cpp

by Vitaly Buka on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+14-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+8-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+2-1clang/lib/CodeGen/Targets/RISCV.cpp
+24-13 files

LLVM/project 4438ec9 — clang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-vector-callingconv-llvm-ir.c riscv-vector-callingconv-llvm-ir.cpp

by Vitaly Buka on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+14-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+8-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+2-1clang/lib/CodeGen/Targets/RISCV.cpp
+24-13 files

LLVM/project 48790cb — clang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-vector-callingconv-llvm-ir.c riscv-vector-callingconv-llvm-ir.cpp

by Vitaly Buka on ⎇
rebase

Created using spr 1.3.7
DeltaFile
+14-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+8-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+2-1clang/lib/CodeGen/Targets/RISCV.cpp
+24-13 files

LLVM/project a808f7a — clang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-vector-callingconv-llvm-ir.c riscv-vector-callingconv-llvm-ir.cpp

by Vitaly Buka on ⎇
rebase

Created using spr 1.3.7
DeltaFile
+14-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+8-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+2-1clang/lib/CodeGen/Targets/RISCV.cpp
+24-13 files

LLVM/project 8a546ac — clang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-vector-callingconv-llvm-ir.c riscv-vector-callingconv-llvm-ir.cpp

by Vitaly Buka on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+14-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+8-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+2-1clang/lib/CodeGen/Targets/RISCV.cpp
+24-13 files

LLVM/project d638272 — clang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-vector-callingconv-llvm-ir.c riscv-vector-callingconv-llvm-ir.cpp

by Vitaly Buka on ⎇
rebase

Created using spr 1.3.7
DeltaFile
+14-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+8-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+2-1clang/lib/CodeGen/Targets/RISCV.cpp
+24-13 files

LLVM/project 5868847 — clang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-vector-callingconv-llvm-ir.c riscv-vector-callingconv-llvm-ir.cpp

by Craig Topper via GitHub on ⎇
[RISCV] Add Zvfbfa to RISCVABIInfo::coerceVLSVector checks. (#202812)
DeltaFile
+14-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+8-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+2-1clang/lib/CodeGen/Targets/RISCV.cpp
+24-13 files