OPNSense/plugins 23cca9cnet/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms dialogEditOSPFNetwork.xml dialogEditOSPF6Network.xml, net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga OSPF6.xml OSPF.xml

Improve visibility for route-maps and prefix-lists in OSPF/OSPF6 and enable internalModelUseSafeDelete
DeltaFile
+12-12net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/OSPF6.xml
+12-12net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/OSPF.xml
+2-2net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/dialogEditOSPFNetwork.xml
+2-2net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/dialogEditOSPF6Network.xml
+1-1net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/dialogEditRedistribution.xml
+1-1net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/dialogEditOSPFRouteMaps.xml
+30-303 files not shown
+33-319 files

FreeBSD/ports 79ea5c1net/ntpd-rs distinfo Makefile.crates

net/ntpd-rs: Update to 1.8.0

PR:             295100
DeltaFile
+275-35net/ntpd-rs/distinfo
+136-16net/ntpd-rs/Makefile.crates
+1-1net/ntpd-rs/Makefile
+412-523 files

LLVM/project 26f5eb2clang/lib/Driver/ToolChains AMDGPU.cpp

clang/AMDGPU: Stop adding -m32/-m64 for OpenCL (#199005)

The pointer size is not configurable; you get what you get
based on the triple. I don't know what the point of this was,
I don't even see the argument in the final cc1 invocation.
DeltaFile
+0-4clang/lib/Driver/ToolChains/AMDGPU.cpp
+0-41 files

LLVM/project 3d126bdllvm/test/Analysis/CostModel/AArch64 masked_expand_load.ll mem-op-cost-model.ll, llvm/test/Analysis/CostModel/X86 masked-intrinsic-cost.ll masked-intrinsic-cost-inseltpoison.ll

[CostModel] Move the arbitrary load latency into getMemoryOpCost (#198790)

Currently TargetTransformInfoImpl returns an arbitrary cost of 4 for the
latency of loads in getInstructionCost. This means even if a target
correctly reports the latency for loads in getMemoryOpCost we still get
this arbitrary cost in getInstructionCost. It also means the latency
cost is inconsistent depending on whether you go through
getInstructionCost or getMemoryOpCost.

Solve this by moving the current arbitrary cost into getMemoryOpCost.
This has the side-effect of affecting the cost of masked loads if they
aren't handled by the target, as in BasicTTIImpl the cost for these is
calculated using getMemoryOpCost. This should mean the cost is more
accurate though, and likely won't have any effect as in any
transformation that could introduce masked loads (e.g. vectorization)
the current cost is probably high enough that it's already not worth
using.
DeltaFile
+520-520llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
+520-520llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
+36-36llvm/test/Analysis/CostModel/AArch64/masked_expand_load.ll
+24-24llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll
+20-20llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+18-18llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
+1,138-1,13812 files not shown
+1,174-1,14818 files

OPNSense/core ac55f10src/opnsense/mvc/app/models/OPNsense/Unbound Unbound.xml

unbound: trim option values

This works since https://github.com/opnsense/core/commit/b187227683de93cb705d6290090aaa708354edf1
DeltaFile
+11-11src/opnsense/mvc/app/models/OPNsense/Unbound/Unbound.xml
+11-111 files

LLVM/project e1570b8llvm/test/CodeGen/AArch64/GlobalISel postselectopt-dead-cc-defs-in-fcmp.mir

[AArch64] Delete llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir (NFC) (#198974)

It's bit-identical to
llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs.mir. The
-in-fcmp test is older (0f0fd383b487), but 84a6a057e60b later expanded
op coverage and left both files with the exact same contents.
DeltaFile
+0-366llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir
+0-3661 files

LLVM/project 5a2b8ccmlir/include/mlir/Interfaces MemorySlotInterfaces.h, mlir/lib/Interfaces MemorySlotInterfaces.cpp

revert getOpAliasSlot change and add back referencesAtMostOneAliasOfSlot
DeltaFile
+15-5mlir/lib/Interfaces/MemorySlotInterfaces.cpp
+14-4mlir/include/mlir/Interfaces/MemorySlotInterfaces.h
+7-7mlir/lib/Transforms/Mem2Reg.cpp
+36-163 files

LLVM/project 371f57cllvm/lib/Target/AArch64 AArch64ConditionOptimizer.cpp, llvm/test/CodeGen/AArch64 aarch64-condopt-cross-block-domtree.mir

[AArch64] ConditionOptimizer: replace per-block DenseMap with ScopedHashTable traversal (#196746)

The intra-block path used a DenseMap cleared at each block boundary, so
pairs from dominating blocks were never visible to descendants. Replace
it and the separate cross-block path with a unified recursive domtree
walk using a ScopedHashTable. Any dominating block's pair is now a
candidate, not just pairs within the same block.

Rename optimizeIntraBlock to optimizeBlock and remove dead code
DeltaFile
+48-193llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+118-0llvm/test/CodeGen/AArch64/aarch64-condopt-cross-block-domtree.mir
+166-1932 files

LLVM/project 45f8bdallvm/lib/Target/SPIRV SPIRVBuiltins.cpp, llvm/test/CodeGen/SPIRV/transcoding AtomicCompareExchangeExplicit_cl20.ll

[SPIR-V] Fix failure-order register reuse in atomic cmpxchg lowering (#199000)

Fix copy-paste issue, extend tests for cmpxchg atomic
DeltaFile
+10-2llvm/test/CodeGen/SPIRV/transcoding/AtomicCompareExchangeExplicit_cl20.ll
+1-1llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+11-32 files

OpenBSD/ports Qr8Vmhjgeo/gdal Makefile

   add hidden BDEP on math/exprtk (header-only "library")
VersionDeltaFile
1.173+2-0geo/gdal/Makefile
+2-01 files

FreeNAS/freenas 3076a81src/middlewared/middlewared/etc_files libvirt.py, src/middlewared/middlewared/plugins/container lifecycle.py

Set ACL restricting container root fs

libvirt has procedure whereby it changes to root UID of container
(non-zero) before executing pivot_root to its new filesystem.
This commit ensures that UID 0 of our container idmap ranges has
execute on the root directory (but no one else does). This allows
pivot_root to succeed, but prevents access by non-privileged users.
DeltaFile
+84-0tests/api2/test_container.py
+57-0src/middlewared/middlewared/plugins/container/lifecycle.py
+2-0src/middlewared/middlewared/etc_files/libvirt.py
+143-03 files

OpenBSD/ports GMH66ardevel/got distinfo Makefile

   update to got 0.126

   - remove dependency on xxd from the test suite (dep was added in got-0.125)
   - really add all relevant parent commits to newly created pack files
   - fix serving a branch of entirely unrelated history with gotd
   - fix test failures when tests are run with Git 2.54
   - initial sha256 support in the network protocol for got clone/fetch/send
VersionDeltaFile
1.127+2-2devel/got/distinfo
1.146+1-1devel/got/Makefile
+3-32 files

OpenBSD/ports AvnAWBQsysutils/borgmatic distinfo Makefile

   update to borgmatic-2.1.5
VersionDeltaFile
1.87+2-2sysutils/borgmatic/distinfo
1.107+1-1sysutils/borgmatic/Makefile
+3-32 files

NetBSD/src CHNqFBCsys/arch/riscv/include pte.h, sys/arch/riscv/riscv trap.c

   risc-v: fix ref/mod emulation PTE handling.

   The previous code has zero chance of working and now that pmap_test_mod_ref
   exists it can prove this code is correct.
VersionDeltaFile
1.32+19-18sys/arch/riscv/riscv/trap.c
1.20+15-14sys/arch/riscv/include/pte.h
+34-322 files

NetBSD/src 9ZdqsP5sys/arch/evbarm/conf GENERIC64_PMAPMI, sys/arch/evbmips/conf OCTEON

   mi pmap: provide pmap_test_mod_ref

   Sprinkle commented out PMAP_DEBUG for MI PMAP kernels
VersionDeltaFile
1.94+175-2sys/uvm/pmap/pmap.c
1.30+3-2sys/arch/evbppc/conf/MPC8548CDS
1.18+3-2sys/arch/evbmips/conf/OCTEON
1.31+3-2sys/arch/evbppc/conf/MPC8536DS
1.26+2-1sys/arch/riscv/conf/GENERIC64
1.3+1-0sys/arch/evbarm/conf/GENERIC64_PMAPMI
+187-96 files

LLVM/project 6255ecdclang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-load-monitor.cl

[AMDGPU][Clang] use ScopeModel to translate integer scopes [NFC] (#198250)

The assumption here is that AMDGPU builtins (typically suffixed with
`__builtin_amdgcn`) use the `__MEMORY_SCOPE_*` enumeration, and not the
`__HIP_MEMORY_SCOPE_*` enumeration (which is how it should be).

Assisted-By: Claude Opus 4.6
DeltaFile
+28-36clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+27-0clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
+1-1clang/test/SemaHIP/incorrect-atomic-scope.hip
+56-373 files

LLVM/project 6ccf74bllvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange dependency-all-eq.ll

[LoopInterchange] Change the cost model to interchange `[* =]`
DeltaFile
+30-53llvm/test/Transforms/LoopInterchange/dependency-all-eq.ll
+33-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+63-552 files

LLVM/project 93cae54llvm/test/Transforms/LoopInterchange dependency-all-eq.ll

[LoopInterchange] Add test with dependency `[* =]` and `[= *]` (NFC)
DeltaFile
+117-0llvm/test/Transforms/LoopInterchange/dependency-all-eq.ll
+117-01 files

LLVM/project 97f6932llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange dependency-all-eq.ll pr43176-move-to-new-latch.ll

[LoopInterchange] Relax legality check to accept more patterns
DeltaFile
+103-42llvm/test/Transforms/LoopInterchange/dependency-all-eq.ll
+15-0llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+8-6llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
+4-6llvm/test/Transforms/LoopInterchange/inner-only-reductions.ll
+6-3llvm/test/Transforms/LoopInterchange/legality-check.ll
+0-8llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
+136-651 files not shown
+140-697 files

LLVM/project 48ab6dellvm/test/Transforms/LoopInterchange loop-interchange-optimization-remarks.ll

fix test
DeltaFile
+3-2llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
+3-21 files

LLVM/project 72a1d34llvm/test/Transforms/LoopInterchange profitability-vectorization.ll

address review comment
DeltaFile
+1-1llvm/test/Transforms/LoopInterchange/profitability-vectorization.ll
+1-11 files

LLVM/project 970ec49llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-instorder.ll

[LoopInterchange] Take base pointer into account in profitability check
DeltaFile
+7-17llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+13-7llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+20-242 files

LLVM/project f81f221llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-vectorization.ll lcssa-phi-outer-latch.ll

[LoopInterchange] Disable LoopCacheAnalysis-based heuristic by default
DeltaFile
+3-3llvm/test/Transforms/LoopInterchange/profitability-vectorization.ll
+1-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+1-1llvm/test/Transforms/LoopInterchange/lcssa-phi-outer-latch.ll
+1-1llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
+1-1llvm/test/Transforms/LoopInterchange/perserve-lcssa.ll
+1-1llvm/test/Transforms/LoopInterchange/pr57148.ll
+8-91 files not shown
+9-107 files

LLVM/project 385701cllvm/test/Transforms/LoopInterchange profitability-instorder.ll

[LoopInterchange] Add test for multiple accesses to same base ptr (NFC) (#193476)

Currently `getInstrOrderCost` doesn't check the base pointers of the
accesses, which can lead to undesirable profitability decisions. This
patch adds a test that demonstrates such a case.
DeltaFile
+86-2llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+86-21 files

OPNSense/core 7484d4bsrc/opnsense/mvc/app/models/OPNsense/TrafficShaper TrafficShaper.xml

firewall: this works and I don't get it
DeltaFile
+1-1src/opnsense/mvc/app/models/OPNsense/TrafficShaper/TrafficShaper.xml
+1-11 files

LLVM/project 720c1adclang/lib/Driver/ToolChains AMDGPU.cpp

clang/AMDGPU: Stop adding -m32/-m64 for OpenCL

The pointer size is not configurable; you get what you get
based on the triple. I don't know what the point of this was,
I don't even see the argument in the final cc1 invocation.
DeltaFile
+0-4clang/lib/Driver/ToolChains/AMDGPU.cpp
+0-41 files

LLVM/project 93d8c2bllvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp, llvm/test/CodeGen/AArch64/GlobalISel knownbits-srem.mir

[GlobalISel][KnownBits] Port SREM to GlobalISel (#198956)

This PR also move case statement for or `G_UREM `that is being
introduced by https://github.com/llvm/llvm-project/pull/193455 So that
`G_[U|S][DIV|REM] ` being grouped together, just like in
`SelectionDAG.cpp`

Related: https://github.com/llvm/llvm-project/issues/150515

---------

Signed-off-by: ZakyHermawan <zaky.hermawan9615 at gmail.com>
DeltaFile
+161-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-srem.mir
+32-12llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+2-6llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
+1-3llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
+196-214 files

LLVM/project 63b905cllvm/include/llvm/IR IntrinsicsSPIRV.td, llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp

[SPIR-V] Add support for OpIsFinite and OpIsNormal intrinsics (#196961)
DeltaFile
+45-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/OpIsFinite.ll
+45-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/OpIsNormal.ll
+36-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+4-0llvm/include/llvm/IR/IntrinsicsSPIRV.td
+130-04 files

LLVM/project e453259lldb/source/Plugins/ScriptInterpreter/Python/Interfaces OperatingSystemPythonInterface.cpp ScriptedBreakpointPythonInterface.cpp

[lldb] Add missing includes. (#198996)

Failed to build in CI because,
ScriptedPythonInterface::CreatePlugingObject is a template function and
the arguments are of incomplete types gotten from `lldb-forward.h`
(typedef of lldb_private::XXXX = XXXXSP).

Introduced in commit 1b4a578a9f7760a00bf26525a603be1ec6e7d862
DeltaFile
+1-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/OperatingSystemPythonInterface.cpp
+1-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedBreakpointPythonInterface.cpp
+1-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedHookPythonInterface.cpp
+1-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStopHookPythonInterface.cpp
+1-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.cpp
+5-05 files

LLVM/project 1c305a3llvm/lib/Target/AMDGPU GCNRegPressure.h AMDGPUInstCombineIntrinsic.cpp

[AMDGPU] Coverity fixes - check ret val and init class members (#198570)

Coverity fixes:
* calling getIntrinsicSignature without checking return value (as is
done elsewhere 4 out of 5 times) in
llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
* non-static class member MaxSGPRs, MaxVGPRs and MaxUnifiedVGPRs is not
initialized in this constructor nor in any functions that it calls in
llvm/lib/Target/AMDGPU/GCNRegPressure.h
DeltaFile
+3-3llvm/lib/Target/AMDGPU/GCNRegPressure.h
+3-2llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+6-52 files