LLVM/project 9105d9clld/ELF/Arch Hexagon.cpp, lld/test/ELF hexagon-duplex-relocs.s

[lld][Hexagon] Fix findMaskR8 missing duplex support (#183936)

findMaskR8() lacked an isDuplex() check, unlike findMaskR6(),
findMaskR11(), and findMaskR16() which all handle duplex instructions.

When the assembler generates R_HEX_8_X on a duplex SA1_addi instruction
(e.g. `{ r0 = add(r0, ##target); memw(r1+#0) = r2 }`), the wrong mask
0x00001fe0 placed relocation bits at [12:5] instead of [25:20],
corrupting the low sub-instruction (e.g. memw became memb).

Add the isDuplex() check returning 0x03f00000, and add a comprehensive
test covering all duplex instruction x relocation type combinations
across findMaskR6, findMaskR8, findMaskR11, and findMaskR16.
DeltaFile
+40-0lld/test/ELF/hexagon-duplex-relocs.s
+2-0lld/ELF/Arch/Hexagon.cpp
+42-02 files

FreeBSD/src d1650d2sys/arm64/vmm vmm.c

arm64/vmm: Support PMU v3p9

The only new register is read-only. As the kernel just passes the
registers to the guest directly no further change should be needed.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D51764
DeltaFile
+1-1sys/arm64/vmm/vmm.c
+1-11 files

FreeBSD/src e40e545sys/arm64/arm64 identcpu.c

arm64: Treat the PMUVer field of ID_AA64DFR0 as unsigned

The PMUVer field of ID_AA64DFR0 contains an unsigned version of the
Performance Monitors Extension, but it is currently treated as signed.
Change it to unsigned.

Reviewed by:    andrew
Sponsored by:   Arm Ltd
Signed-off-by:  Kajetan Puchalski <kajetan.puchalski at arm.com>
Pull Request:   https://github.com/freebsd/freebsd-src/pull/2062
DeltaFile
+1-1sys/arm64/arm64/identcpu.c
+1-11 files

LLVM/project 958c68bllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Merge branch 'main' into users/arsenm/valuetracking/handle-constant-data-sequential-computeKnownFPClass
DeltaFile
+84,419-78,498llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,112-16,445llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+241,105-188,0741,532 files not shown
+409,008-294,5021,538 files

LLVM/project af3cea5llvm/test/Transforms/InstCombine simplify-demanded-fpclass-aggregates.ll

Drop fixme
DeltaFile
+0-1llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll
+0-11 files

LLVM/project 55d4280llvm/test/CodeGen/AArch64 aarch64-neonvector-tensorflow-regression.ll aarch64-addv.ll

Update tests, remove regression test
DeltaFile
+0-13llvm/test/CodeGen/AArch64/aarch64-neonvector-tensorflow-regression.ll
+6-6llvm/test/CodeGen/AArch64/aarch64-addv.ll
+2-2llvm/test/CodeGen/AArch64/bitcast-extend.ll
+8-213 files

LLVM/project 8778f23llvm/test/CodeGen/AArch64 aarch64-neonvector-tensorflow-regression.ll

Compile time regression test
DeltaFile
+13-0llvm/test/CodeGen/AArch64/aarch64-neonvector-tensorflow-regression.ll
+13-01 files

LLVM/project 9fcff00llvm/lib/Target/AArch64 AArch64MIPeepholeOpt.cpp, llvm/test/CodeGen/AArch64 peephole-insvigpr.mir fpclamptosat_vec.ll

[AArch64] Fold zero-high vector inserts in MI peephole optimisation

Summary
This patch follows on from #178227.
The previous ISel fold lowers the 64-bit case to:
    fmov d0, x0
    fmov d0, d0
which is not ideal and could be fmov d0, x0.
A redundant copy comes from the INSERT_SUBREG/INSvi64lane.

This peephole detects <2 x i64> vectors made of a zeroed upper and low
lane produced by FMOVXDr/FMOVDr, then removes the redundant copy.

Further updated tests and added MIR tests.
DeltaFile
+51-0llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
+47-4llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+24-24llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+7-8llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+6-6llvm/test/CodeGen/AArch64/aarch64-addv.ll
+2-2llvm/test/CodeGen/AArch64/bitcast-extend.ll
+137-442 files not shown
+137-468 files

FreeNAS/freenas b959c56src/middlewared/middlewared/api/base decorator.py, src/middlewared/middlewared/plugins/cron __init__.py

Enable check_annotations for query/get_instance on generic CRUDServices
DeltaFile
+26-0src/middlewared/middlewared/pytest/unit/api/base/test_decorator.py
+5-7src/middlewared/middlewared/plugins/cron/__init__.py
+5-7src/middlewared/middlewared/plugins/init_shutdown_script/__init__.py
+5-7src/middlewared/middlewared/plugins/ntp/__init__.py
+8-0src/middlewared/middlewared/api/base/decorator.py
+5-1src/middlewared/middlewared/service/crud_service.py
+54-221 files not shown
+57-237 files

FreeNAS/freenas 866da9asrc/middlewared/middlewared/plugins/failover_ datastore.py

NAS-140009 / 26.0.0-BETA.2 / prevent blocking sqlite write thread (by yocalebo) (#18350)

During a failover MASTER event, the inline hook_datastore_execute_write
hook blocks the SQLite thread for ~70 seconds:

1. 10s — call_remote('failover.datastore.sql') times out trying to
replicate SQL to the (unreachable) remote node
2. 60s — set_failure() calls call_remote('failover.status') with no
explicit timeout, inheriting the 60s CALL_TIMEOUT default

This stalls any middleware operation that needs DB writes (e.g.
pool.dataset.unlock) for the entire duration, directly delaying failover
completion.

To try and remedy the issue:
1. Short-circuit the hook when failover is in progress — Added a
failover.in_progress check to hook_datastore_execute_write. During a
failover event there is no reason to replicate individual SQL statements
to the remote node, so we skip the remote call entirely.

    [24 lines not shown]
DeltaFile
+13-1src/middlewared/middlewared/plugins/failover_/datastore.py
+13-11 files

FreeNAS/freenas 66e8fdasrc/middlewared/middlewared/plugins/failover_ datastore.py

NAS-140009 / 26.0.0-BETA.1 / prevent blocking sqlite write thread (by yocalebo) (#18349)

During a failover MASTER event, the inline hook_datastore_execute_write
hook blocks the SQLite thread for ~70 seconds:

1. 10s — call_remote('failover.datastore.sql') times out trying to
replicate SQL to the (unreachable) remote node
2. 60s — set_failure() calls call_remote('failover.status') with no
explicit timeout, inheriting the 60s CALL_TIMEOUT default

This stalls any middleware operation that needs DB writes (e.g.
pool.dataset.unlock) for the entire duration, directly delaying failover
completion.

To try and remedy the issue:
1. Short-circuit the hook when failover is in progress — Added a
failover.in_progress check to hook_datastore_execute_write. During a
failover event there is no reason to replicate individual SQL statements
to the remote node, so we skip the remote call entirely.

    [24 lines not shown]
DeltaFile
+13-1src/middlewared/middlewared/plugins/failover_/datastore.py
+13-11 files

LLVM/project 9cd054bllvm/lib/Target/AArch64 AArch64InstrFormats.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64-int-neon.ll arm64-vqadd.ll

[AArch64] Add lowering for misc NEON intrinsics (#183050)

This patch adds custom lowering for the following NEON intrinsics to
enable better codegen for convert and load/store operations:

- suqadd
- usqadd
- abs
- sqabs
- sqneg
DeltaFile
+144-4llvm/test/CodeGen/AArch64/arm64-int-neon.ll
+16-16llvm/test/CodeGen/AArch64/arm64-vqadd.ll
+16-8llvm/lib/Target/AArch64/AArch64InstrFormats.td
+11-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+8-4llvm/lib/Target/AArch64/AArch64InstrInfo.td
+5-6llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
+200-406 files

FreeNAS/freenas df69d24src/middlewared/middlewared/plugins/failover_ datastore.py

NAS-140009 / 25.10.2.2 / prevent blocking sqlite write thread (by yocalebo) (#18348)

During a failover MASTER event, the inline hook_datastore_execute_write
hook blocks the SQLite thread for ~70 seconds:

1. 10s — call_remote('failover.datastore.sql') times out trying to
replicate SQL to the (unreachable) remote node
2. 60s — set_failure() calls call_remote('failover.status') with no
explicit timeout, inheriting the 60s CALL_TIMEOUT default

This stalls any middleware operation that needs DB writes (e.g.
pool.dataset.unlock) for the entire duration, directly delaying failover
completion.

To try and remedy the issue:
1. Short-circuit the hook when failover is in progress — Added a
failover.in_progress check to hook_datastore_execute_write. During a
failover event there is no reason to replicate individual SQL statements
to the remote node, so we skip the remote call entirely.

    [24 lines not shown]
DeltaFile
+13-1src/middlewared/middlewared/plugins/failover_/datastore.py
+13-11 files

LLVM/project b9f1199llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-aggregates.ll

InstCombine: Support extractvalue in SimplifyDemandedFPClass (#184171)

Previously this only handled extractvalue of frexp.
DeltaFile
+67-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll
+6-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+73-12 files

LLVM/project 94fa697llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUTargetStreamer.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp AMDGPUBaseInfo.h

AMDGPU: Clean up print handling of AMDGPUTargetID

Provide print to raw_ostream method and use it where applicable.
DeltaFile
+7-5llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+8-3llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+9-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+24-83 files

LLVM/project fb664adllvm/test/CodeGen/AArch64 aarch64-neonvector-tensorflow-regression.ll aarch64-addv.ll

Update tests, remove regression test
DeltaFile
+0-13llvm/test/CodeGen/AArch64/aarch64-neonvector-tensorflow-regression.ll
+6-6llvm/test/CodeGen/AArch64/aarch64-addv.ll
+2-2llvm/test/CodeGen/AArch64/bitcast-extend.ll
+8-213 files

LLVM/project 34f1b86llvm/lib/Target/AArch64 AArch64MIPeepholeOpt.cpp, llvm/test/CodeGen/AArch64 peephole-insvigpr.mir fpclamptosat_vec.ll

[AArch64] Fold zero-high vector inserts in MI peephole optimisation

Summary
This patch follows on from #178227.
The previous ISel fold lowers the 64-bit case to:
    fmov d0, x0
    fmov d0, d0
which is not ideal and could be fmov d0, x0.
A redundant copy comes from the INSERT_SUBREG/INSvi64lane.

This peephole detects <2 x i64> vectors made of a zeroed upper and low
lane produced by FMOVXDr/FMOVDr, then removes the redundant copy.

Further updated tests and added MIR tests.
DeltaFile
+51-0llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
+47-4llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+24-24llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+7-8llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+6-6llvm/test/CodeGen/AArch64/aarch64-addv.ll
+2-2llvm/test/CodeGen/AArch64/bitcast-extend.ll
+137-442 files not shown
+137-468 files

LLVM/project 2383919llvm/test/CodeGen/AArch64 aarch64-neonvector-tensorflow-regression.ll

Compile time regression test
DeltaFile
+13-0llvm/test/CodeGen/AArch64/aarch64-neonvector-tensorflow-regression.ll
+13-01 files

OpenBSD/ports 6vhTiMRcomms/zigbee2mqtt distinfo Makefile

   update to zigbee2mqtt-2.9.1
VersionDeltaFile
1.15+4-4comms/zigbee2mqtt/distinfo
1.23+1-1comms/zigbee2mqtt/Makefile
+5-52 files

LLVM/project b0b5834llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/X86 known-pow2.ll

[DAG] Improved handling of ISD::ROTL and ISD::ROTR in isKnownToBeAPowerOfTwo (#182744)

Fixes #181642
DeltaFile
+80-0llvm/test/CodeGen/X86/known-pow2.ll
+1-1llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+81-12 files

OpenBSD/ports F8b6hjunet/wireshark Makefile distinfo, net/wireshark/patches patch-cmake_modules_FindPCAP_cmake patch-tools_radiotap-gen_CMakeLists_txt

   update to wireshark-4.6.4 using ports libpcap
VersionDeltaFile
1.1+33-0net/wireshark/patches/patch-cmake_modules_FindPCAP_cmake
1.22+19-10net/wireshark/pkg/PLIST-text
1.177+9-11net/wireshark/Makefile
1.1+10-0net/wireshark/patches/patch-tools_radiotap-gen_CMakeLists_txt
1.7+3-3net/wireshark/patches/patch-capture_capture-pcap-util_c
1.111+2-2net/wireshark/distinfo
+76-262 files not shown
+76-268 files

LLVM/project a14f9f8mlir/include/mlir/Dialect/XeGPU/IR XeGPUAttrs.td, mlir/lib/Dialect/XeGPU/Transforms XeGPUWgToSgDistribute.cpp

[mlir][xegpu] Add support for accessing the default order of a layout.  (#184451)

Currently, `getOrder` returns null if the user does not provide an
`order` in xegpu layout. This behavior is undesirable when coupled with
utility functions that work on top of layouts (like `isTransposeOf`).
This PR introduce a `getEffectiveOrder` which always returns the true
order, even if user decides to omit it.
DeltaFile
+46-15mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+5-4mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+4-4mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
+0-7mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
+3-2mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir
+2-2mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
+60-346 files

OpenBSD/ports R1HAw2vnet/libpcap Makefile distinfo, net/libpcap/patches patch-CMakeLists_txt patch-CMakeLists_txt

   Initial revision
VersionDeltaFile
1.1+107-0net/libpcap/pkg/PLIST
1.1+33-0net/libpcap/Makefile
1.1+27-0net/libpcap/patches/patch-CMakeLists_txt
1.1+10-0net/libpcap/pkg/DESCR
1.1+2-0net/libpcap/distinfo
1.1.1.1+0-0net/libpcap/patches/patch-CMakeLists_txt
+179-04 files not shown
+179-010 files

LLVM/project 87bb6e0libsycl/include/sycl/__impl usm_functions.hpp, libsycl/src usm_functions.cpp

fix my comments

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+2-2libsycl/include/sycl/__impl/usm_functions.hpp
+2-2libsycl/src/usm_functions.cpp
+4-42 files

FreeNAS/freenas e7c7a1asrc/middlewared/middlewared/plugins/failover_ datastore.py

address review

(cherry picked from commit f55c944358da46db548273bc9c3df24b729b34f7)
DeltaFile
+3-4src/middlewared/middlewared/plugins/failover_/datastore.py
+3-41 files

FreeNAS/freenas b391253src/middlewared/middlewared/plugins/failover_ datastore.py

go back to 10 timeout

(cherry picked from commit 037309952465f8246dec22ae3334d2dd199122e8)
DeltaFile
+1-1src/middlewared/middlewared/plugins/failover_/datastore.py
+1-11 files

FreeNAS/freenas aa44b1fsrc/middlewared/middlewared/plugins/failover_ datastore.py

prevent blocking sqlite write thread

(cherry picked from commit c89b9261cb447ce54a312d1579b502333ff9892f)
DeltaFile
+15-2src/middlewared/middlewared/plugins/failover_/datastore.py
+15-21 files

FreeNAS/freenas 017bbd0src/middlewared/middlewared/plugins/failover_ datastore.py

prevent blocking sqlite write thread

(cherry picked from commit c89b9261cb447ce54a312d1579b502333ff9892f)
DeltaFile
+15-2src/middlewared/middlewared/plugins/failover_/datastore.py
+15-21 files

FreeNAS/freenas 8396e5fsrc/middlewared/middlewared/plugins/failover_ datastore.py

go back to 10 timeout

(cherry picked from commit 037309952465f8246dec22ae3334d2dd199122e8)
DeltaFile
+1-1src/middlewared/middlewared/plugins/failover_/datastore.py
+1-11 files

FreeNAS/freenas a130f11src/middlewared/middlewared/plugins/failover_ datastore.py

address review

(cherry picked from commit f55c944358da46db548273bc9c3df24b729b34f7)
DeltaFile
+3-4src/middlewared/middlewared/plugins/failover_/datastore.py
+3-41 files