LinuxKPI: Update seq_file to properly implement the iterator interface
The seq_file.rst documentation in the Linux kernel documents the
iterator interface for the seq_file structure. In particular, the
ppos passed to seq_read is a logical offset into a seq_file managed by
the iterator interface, not an offset into the generated data. For
example, if a seq_file outputs state for each node in a linked-list or
array, *ppos might be used as the index of the node to output, not a
byte offset.
Rewrite seq_read to honor this contract which fixes a few bugs:
- Treat *ppos as a logical iterator offset that is only updated by the
next callback after outputting a single item via the show method.
- Use a loop to permit outputting descriptions of multiple items if
the user buffer is large enough.
- Always invoke the stop method after terminating the loop to cleanup
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[libc] Honor per-test timeout in lit test format (#193772)
The custom LibcTest format did not pass litConfig.maxIndividualTestTime
to executeCommand. This caused --timeout to be silently ignored, so
hanging tests like fdiv_test on AMDGPU blocked the entire suite until
the buildbot watchdog killed the process after 1200s.
Added timeout propagation and handling of ExecuteCommandTimeoutException
to return lit.Test.TIMEOUT. This follows the same pattern used by the
GoogleTest format in googletest.py.
arm64/vmm: Enable 16-bit VMIDs when in use by pmap
pmap_init always uses 16-bit VMIDs when supported, but we never enable
them in VTCR_EL2 (for ASIDs, locore enables them in TCR_EL1 and
pmap_init keys off whether they've been enabled, but the order in which
pmap_init and vmmops_modinit run is reversed). As a result, although the
full 16-bit value can be stored to VTTBR_EL2 and read back, the upper 8
bits are treated as 0, and so VMIDs that our VMID allocation believes
are distinct end up aliasing.
In future this interface may change such that vmm decides on the VMID
width and tells the pmap to use that, with appropriate support for
unloading and reloading vmm, but that can come as a follow-up change, as
this is a more minimal bug fix.
Reviewed by: markj
Obtained from: CheriBSD
Fixes: 47e073941f4e ("Import the kernel parts of bhyve/arm64")
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D55860
NAS-140741 / 26.0.0-BETA.2 / V-Series: DMI-gated X710 internode bond for v2.0 (NTG) controllers (by darkfiberiru) (#18793)
## Summary
Add middleware support for the new NTG V-Series switch board
(4IXGA_PEX89032). The NTG board replaces the older NTB board on v2.0
controllers, eliminates the external 10 GBaseT internode cable, and
provides the HA interconnect via a 2×10 GbE cross-connect over the
chassis backplane (dual X710-AT2 ports per controller). The freed-up 10
GBaseT port returns to the customer as a general-purpose interface.
## Why
Without this change, a v2.0 (NTG) controller returns `MANUAL` from
`failover.node` (new SES product string unrecognised) and HA won't come
up. This is a ship blocker for the NTG board.
## Behavior
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NAS-140741 / 27.0.0-BETA.1 / V-Series: DMI-gated X710 internode bond for v2.0 (NTG) controllers (#18788)
## Summary
Add middleware support for the new NTG V-Series switch board
(4IXGA_PEX89032). The NTG board replaces the older NTB board on v2.0
controllers, eliminates the external 10 GBaseT internode cable, and
provides the HA interconnect via a 2×10 GbE cross-connect over the
chassis backplane (dual X710-AT2 ports per controller). The freed-up 10
GBaseT port returns to the customer as a general-purpose interface.
## Why
Without this change, a v2.0 (NTG) controller returns `MANUAL` from
`failover.node` (new SES product string unrecognised) and HA won't come
up. This is a ship blocker for the NTG board.
## Behavior
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[libc++] Implement `ranges::fold_left_first` and `ranges::fold_left_first_with_iter` (#180214)
- Part of #105208.
- Closes #174059.
- Closes #121558.
---------
Co-authored-by: JCGoran <jcgoran at protonmail.com>
Co-authored-by: A. Jiang <de34 at live.cn>
[DAGCombiner] Fold bswap of single-byte-known-nonzero value to a shift (#193473)
When computeKnownBits proves that a bswap operand has at most one byte
of possibly-nonzero bits at a known byte-aligned position, the bswap is
equivalent to a shift that moves that byte to the mirror position. This
is a producer-side known-bits rule; it fires in visitBSWAP regardless
of how the narrow-value provenance was established, covering shapes
such as
bswap(and X, 0xFF)
bswap(and X, 0xFF00) ; all byte positions
bswap(zext i8 X to iN)
bswap(zext i16 X to i64)
Motivation. While investigating a RISCV codegen regression under
-combiner-topological-sorting (bswap-shift.ll), I traced the root cause
to the existing consumer-side rule in
TargetLowering::SimplifyDemandedBits
for ISD::BSWAP: when a consumer demands only one byte of the bswap
result, that rule rewrites the inner bswap as a shift. Under topological
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[Hexagon] Add SafeStack runtime libcall to HexagonSystemLibrary (#191673)
Register DefaultSafeStackGlobals for the Hexagon target so that the
SafeStack pass can locate the thread-local unsafe stack pointer during
codegen.
Without this, compiling with `-fsanitize=safe-stack` for Hexagon errors
with "no location available for safestack pointer address".
Status/2026Q1: Fixes
- Change syntax of a numbered list to fix warnings (use actual numbers
instead of repeating "1."'s)
- URL encode "..." to ensure links do not break (replacing ... with …)
[NFC][Clang][Analyses] Fix AccessPath to have deleted copy assignment (#193639)
Static analysis flagged AccessPath because it had a copy constructor but
did not declare a copy assignment. It appears the intent is not to allow
assignment, so declare it deleted.
[TySan] Fix size type mismatch in instrumentMemInst for 32-bit targets (#191601)
The outlined instrumentation path in instrumentMemInst passes Size
directly to the __tysan_instrument_mem_inst runtime call, which declares
its size parameter as uint64_t (i64). On 32-bit targets, Size is
IntptrTy (i32) for allocas and byval arguments, causing an assertion:
Calling a function with a bad signature!
Add CreateZExtOrTrunc to widen Size to U64Ty before the call. This is a
no-op on 64-bit targets where IntptrTy is already i64.
[CodeGenPrepare] Drop nuw on gep unmerging if the new index is negative (#193488)
Fixes #193487.
Drop nuw if unmerging would result in gep with a negative index.
[AArch64][clang][llvm] Add ACLE Armv9.7 MMLA intrinsics
Implement new ACLE matrix multiply-accumulate intrinsics for Armv9.7:
```c
// 16-bit floating-point matrix multiply-accumulate.
// Only if __ARM_FEATURE_SVE_B16MM
// Variant also available for _f16 if (__ARM_FEATURE_SVE2p2 && __ARM_FEATURE_F16MM).
svbfloat16_t svmmla[_bf16](svbfloat16_t zda, svbfloat16_t zn, svbfloat16_t zm);
// Half-precision matrix multiply accumulating to single-precision
// instruction from Armv9.7-A. Requires the +f16f32mm architecture extension.
float32x4_t vmmlaq_f32_f16(float32x4_t r, float16x8_t a, float16x8_t b)
// Non-widening half-precision matrix multiply instruction. Requires the
// +f16mm architecture extension.
float16x8_t vmmlaq_f16_f16(float16x8_t r, float16x8_t a, float16x8_t b)
```
[OpenMP][OMPIRBuilder] Convert cmpxchg memory order to C ABI constants (#193536)
`EmitAtomicCompareExchangeLibcall` passed LLVM AtomicOrdering enum
values directly as the success/failure ordering arguments to
`__atomic_compare_exchange`. However, the C ABI expects the `__ATOMIC_*`
constants instead.
`EmitAtomicLoadLibcall` and `EmitAtomicStoreLibcall` already use
`toCABI()` for this conversion. Apply the same conversion in
`EmitAtomicCompareExchangeLibcall`.
This PR is a reland of #191857 which was closed incorrectly due to
parent branch deleted.
[DAGCombine] Relax restriction on (bswap shl(x,c)) combine (#193679)
We can still do the
(bswap shl(x,c)) -> (zext(bswap(trunc(shl(x,sub(c,bw/2))))))
combine if the shift amount is a multiple of 8 not just 16.
https://alive2.llvm.org/ce/z/crnSB6
