interfaces: multi-dhcp6c support and custom PD association #7647
This splits off rtsold and dhcp6c into separate processes
which frees us from the restrictions of faked iterative IDs
for PD associations. For NA we simply default to 0 now.
I'm not entirely sure why we settled for a single deamon of
dhcp6c back in the day, but there are certianly downsides to
it and I don't see something that wasn't fixed in the meantime
that makes this not work.
NAS-139748 / 26.0.0-BETA.1 / ValidationErrors -> ValidationError in static route test (#18191)
Minor change to this test, static route plugin raises ValidationError
now and not ValidationErrors.
Fix ownership based deallocation pass crash (#179357)
The `OwnershipBasedBufferDeallocation` pass crashes when the IR contains
memrefs that are live in the same Block but are defined in different
Blocks. During this pass, live memrefs in a given block are sorted
according to the comparison function `ValueComparator`. This causes an
assertion to be triggered when sorting memref values using
`ValueComparator` as the comparison function. The assertion triggered is
found in `Operation::isBeforeInBlock`, which requires `this` and `other`
to reside in the same block. (See the definition
[here](https://github.com/llvm/llvm-project/blob/main/mlir/lib/IR/Operation.cpp#L385-L386).)
The fix is to handle values from different blocks in the
`ValueComparator` by sorting based on Block number if the compared ops
aren't in the same block. While `computeBlockNumber` is intended for
debugging and error messages, it is a convenient utility that can
provide a sufficient weak ordering for `llvm::sort` while handling
operations from different parent blocks. I'm not aware of another
ordering relation for Blocks that would be appropriate as well as cheap
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[CIR] Add cir.atomic.xchg to target lowering (#180744)
This patch adds the `cir.atomic.xchg` operation to the TargetLowering
pass. The synchronization scope attached to the operation will be
canonicalized there.
[AArch64][ISel] Lower fixed-width i64 vector CLMUL intrinsics (#178876)
NEON's PMULL/PMULL2 can be used and its lower bits taken to lower CLMUL
intrinsics, so long as +aes is present.
gpa: update to 0.11.1.
Noteworthy changes in version 0.11.1 (2026-02-12)
-------------------------------------------------
* Remove unused trust_item stuff to make it build with gpgme 2.x.
[rGPAb6ba8bcc6d]
* Fix a crash due to bad marshaling. See
https://bugs.gentoo.org/957196. [rGPA45fc64a4ac]
[BOLT][BTI] Patch ignored functions in place when targeting them with
indirect branches
When applying BTI fixups to indirect branch targets, ignored functions are
considered a special case:
- these hold no instructions,
- have no CFG,
- and are not emitted in the new text section.
The solution is to patch the entry points in the original location.
If such a situation occurs in a binary, recompilation using the
-fpatchable-function-entry flag is required. This will place a nop at all
function starts, which BOLT can use to patch the original section.
Without the extra nop, BOLT cannot safely patch the original .text section.
An alternative solution could be to also ignore the function from which
the stub starts. This has not been tried as LongJmp pass - where most
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py-mysqlclient: updated to 2.2.8
2.2.8
* Add ``local_infile_dir`` option to restrict LOAD DATA LOCAL INFILE file path.
* windows wheel: Update mariadb-connector to 3.4.8
* Add Python 3.14 and drop Python 3.8, 3.9 support.
* Experimental support for free threaded Python. Importing ``MySQLdb`` doesn't
enable the GIL anymore. This doesn't mean mysqlclient is thread safe.
You must not use same connection object from multiple threads concurrently.
[MLIR][LLVMIR] Add support for importing ConstantInt/FP vector splats. (#180946)
Updates LLVM IR importing to remove the assumption that
ConstantInt/ConstantFP are always scalar.
[AArch64] Eliminate XTN/SSHLL for vector splats (#180913)
Combine:
sext(duplane(insert_subvector(undef, trunc(X), 0), idx))
Into:
duplane(X, idx)
This avoids XTN/SSHLL instruction sequences that occur when splatting
elements from boolean vectors after type legalization, which is common
when using shufflevector with comparison results.
