FreshBSD

LLVM/project 437f391 — llvm/test lit.site.cfg.py.in, llvm/test/tools/llvm-ir2vec/bindings lit.local.cfg ir2vec-bindings.py

2026-01-21 07:41:45 UTC by Nishant Sachdeva via GitHub on ⎇

main

[IR2Vec] llvm-ir2vec python bindings scaffolding (#176571)

This patch adds the build infrastructure for Python bindings to
llvm-ir2vec.
Addresses https://github.com/llvm/llvm-project/issues/141839

Changes:
- Add `LLVM_IR2VEC_ENABLE_PYTHON_BINDINGS` CMake option (default OFF)
- Create minimal python module using nanobind
- Add lit test configuration that skips when the bindings have not been
requested

Build requires nanobind and is enabled via `cmake
-DLLVM_IR2VEC_ENABLE_PYTHON_BINDINGS=ON ... `

Future patches will add actual IR2Vec API functionality.

Delta		File
+14	-0	llvm/tools/llvm-ir2vec/Bindings/CMakeLists.txt
+12	-1	llvm/tools/llvm-ir2vec/CMakeLists.txt
+13	-0	llvm/tools/llvm-ir2vec/Bindings/PyIR2Vec.cpp
+9	-0	llvm/test/tools/llvm-ir2vec/bindings/lit.local.cfg
+7	-0	llvm/test/tools/llvm-ir2vec/bindings/ir2vec-bindings.py
+1	-0	llvm/test/lit.site.cfg.py.in
+56	-1	6 files

FreeBSD/doc d38b8ab — website/content/en/cgi ports.cgi

2026-01-21 07:37:00 UTC by Wolfram Schneider (wosch) on ⎇

main

ports.cgi: less perl warnings

Delta		File
+1	-0	website/content/en/cgi/ports.cgi
+1	-0	1 files

FreeBSD/ports 640cfe9 — graphics/wayland-protocols distinfo pkg-plist

2026-01-21 07:27:19 UTC by Jason E. Hale (jhale) on ⎇

main

graphics/wayland-protocols: Update to 1.47

Changes:
1.46: https://lore.freedesktop.org/wayland-devel/AzTKh6JewwfUBFKaOS86DT4obISpv5b5bjFghXGwYrMPyk6Wxpz6H4_trRcEOyF9VpVV-0p1-UTNv7_esjO6ppw5SyIyGxWB8R5xI_SJYfA=@emersion.fr/
1.47: https://lore.freedesktop.org/wayland-devel/aUAqqkhyv6-OKvUo@gmail.com/

PR:             292186
Reported by:    Simon Ser <contact at emersion.fr>
Approved by:    x11@ (manu)

Delta		File
+3	-3	graphics/wayland-protocols/distinfo
+2	-0	graphics/wayland-protocols/pkg-plist
+1	-1	graphics/wayland-protocols/Makefile
+6	-4	3 files

LLVM/project 72915ea — llvm/lib/Target/RISCV RISCVInstrInfoVSDPatterns.td RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv setcc-fp.ll fixed-vectors-fp-setcc.ll

2026-01-21 07:25:37 UTC by Brandon Wu via GitHub on ⎇

main

[RISCV][llvm] Support setcc codegen for zvfbfa (#176866)

Delta		File
+1,104	-628	llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
+426	-4	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+5	-4	llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+3	-2	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1,538	-638	4 files

FreeBSD/ports 7835075 — math/octave-forge-control distinfo Makefile

2026-01-21 07:25:21 UTC by Stephen Montgomery-Smith (stephen) on ⎇

main

math/octave-forge-control: Update to 4.2.1.

Delta		File
+3	-3	math/octave-forge-control/distinfo
+1	-1	math/octave-forge-control/Makefile
+4	-4	2 files

OPNSense/core 664c80e — src/opnsense/service/templates/OPNsense/Dnsmasq dnsmasq.conf

2026-01-21 07:21:18 UTC by Monviech via GitHub on ⎇

master

dnsmasq: Fix log conditions and some whitespace cleanup (#9632)

Delta		File
+6	-6	src/opnsense/service/templates/OPNsense/Dnsmasq/dnsmasq.conf
+6	-6	1 files

LLVM/project 30701dc — llvm/lib/Target/RISCV RISCVInstrInfoVVLPatterns.td RISCVInstrInfoVSDPatterns.td

2026-01-21 07:20:08 UTC by Brandon Wu via GitHub on ⎇

main

[RISCV][llvm] Simplify the name in VSD/VVL patterns. NFC (#177108)

Original PR:https://github.com/llvm/llvm-project/pull/176750 was
accepted but accidentally merged without merging its stacked PR first.

Delta		File
+28	-27	llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+21	-21	llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+49	-48	2 files

LLVM/project f63b438 — llvm/lib/Transforms/Vectorize VPlan.cpp, llvm/test/Transforms/LoopVectorize exact.ll tripcount.ll

2026-01-21 07:17:04 UTC by Mircea Trofin on ⎇

users/mtrofin/01-08-capture_weights

capture weights

Delta		File
+31	-7	llvm/lib/Transforms/Vectorize/VPlan.cpp
+30	-3	llvm/test/Transforms/LoopVectorize/exact.ll
+9	-6	llvm/test/Transforms/LoopVectorize/tripcount.ll
+70	-16	3 files

FreeBSD/src d8b8dc7 — sys/dev/dpaa2 dpaa2_ni.c

2026-01-21 07:16:46 UTC by Michael Tuexen (tuexen) on ⎇

main

dpaa2: cleanup

No functional change intended.

Reviewed by:            bz, dsl
MFC after:              3 days
Differential Revision:  https://reviews.freebsd.org/D54805

Delta		File
+4	-20	sys/dev/dpaa2/dpaa2_ni.c
+4	-20	1 files

LLVM/project 0f582c3 — llvm/lib/Target/RISCV RISCVInstrInfoVVLPatterns.td RISCVInstrInfoVSDPatterns.td

2026-01-21 07:14:19 UTC by Brandon Wu via GitHub on ⎇

main

[RISCV][llvm] Simplify bf16 _ALT suffix in VSD/VVL patterns. NFC (#176744)

Delta		File
+16	-24	llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+13	-20	llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+29	-44	2 files

OPNSense/core 4a4dde6 — src/opnsense/service/templates/OPNsense/Dnsmasq dnsmasq.conf

2026-01-21 07:10:14 UTC by Monviech on ⎇

dnsmasq-fix-log

dnsmasq: Fix log conditions and some whitespace cleanup

Delta		File
+6	-6	src/opnsense/service/templates/OPNsense/Dnsmasq/dnsmasq.conf
+6	-6	1 files

LLVM/project d9ca737 — llvm/utils/release merge-release-pr.py

2026-01-21 07:08:37 UTC by Cullen Rhodes via GitHub on ⎇

main

[llvm][utils] Remove source owner check from merge-release-pr script (#176949)

This check prevents landing PRs from branches on llvm/llvm-project which
is a thing now.

Delta		File
+0	-6	llvm/utils/release/merge-release-pr.py
+0	-6	1 files

LLVM/project d653947 — llvm/utils profcheck-xfail.txt

2026-01-21 07:05:45 UTC by Mircea Trofin via GitHub on ⎇

main

Add control-flow-hub-finalize-same-succ-crash.ll to xfail (#177105)

Introduced in #176620. It appears to expose a profile propagation issue
in FixIrreducible. That pass hasn't yet been addressed.

Delta		File
+1	-0	llvm/utils/profcheck-xfail.txt
+1	-0	1 files

LLVM/project 35dc6c6 — llvm/lib/Target/RISCV RISCVInstrInfoVVLPatterns.td RISCVInstrInfoVSDPatterns.td

2026-01-21 07:04:25 UTC by Brandon Wu via GitHub on ⎇

main

Revert "[RISCV][llvm] Simplify the name in VSD/VVL patterns. NFC" (#177102)

Reverts llvm/llvm-project#176750

Delta		File
+46	-39	llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+35	-28	llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+81	-67	2 files

HardenedBSD/src a42b3cf — etc/mtree BSD.debug.dist, lib/libexecinfo/tests sigtramp_test.c

2026-01-21 07:03:17 UTC by HardenedBSD Sync Services on ⎇

hardened/15-stable/main

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main

Delta		File
+8	-0	lib/libexecinfo/tests/sigtramp_test.c
+2	-0	etc/mtree/BSD.debug.dist
+10	-0	2 files

OPNSense/plugins e3bae8e — security/tinc Makefile

2026-01-21 06:51:20 UTC by Franco Fichtner on ⎇

master

security/tinc: update version

Delta		File
+1	-2	security/tinc/Makefile
+1	-2	1 files

LLVM/project 9ac14f2 — llvm/lib/Target/RISCV RISCVInstrInfoVSDPatterns.td RISCVInstrInfoVVLPatterns.td, llvm/test/CodeGen/RISCV/rvv fixed-vectors-select-bf16.ll select-bf16.ll

2026-01-21 06:45:51 UTC by Brandon Wu via GitHub on ⎇

main

[RISCV][llvm] Support [v]select codegen for zvfbfa (#176865)

This enables [v]select to select vfmerge.vfm, it also enables bf16
to use vmerge.vxm and vmerge.vim where we haven't handled for zvfbfmin.

Delta		File
+63	-2	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll
+63	-2	llvm/test/CodeGen/RISCV/rvv/select-bf16.ll
+4	-2	llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+4	-2	llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+134	-8	4 files

NetBSD/pkgsrc-wip 4a5c09e — emscripten PLIST Makefile

2026-01-21 06:45:36 UTC by Mayuresh on ⎇

master

emscripten: media files found needed at runtime, packaged

Delta		File
+9	-0	emscripten/PLIST
+1	-1	emscripten/Makefile
+10	-1	2 files

LLVM/project f537408 — llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx/ir-instruction extractelement.ll

2026-01-21 06:42:17 UTC by ZhaoQi via GitHub on ⎇

main

[LoongArch] Remove DAG combination for extractelement (#177083)

Combination for `trunc+extend+extractelement` to a single
`extractelement` may occur error, because the high bits of the extract
index truncated by `trunc` operation are reserved after the combination.

This commit remove this combination and the issue
https://github.com/llvm/llvm-project/issues/176839 will never appear.

Delta		File
+0	-43	llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+26	-12	llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
+26	-55	2 files

LLVM/project 6c0e529 — llvm/lib/Target/RISCV RISCVInstrInfoVVLPatterns.td RISCVInstrInfoVSDPatterns.td

2026-01-21 06:41:31 UTC by Brandon Wu via GitHub on ⎇

revert-176750-pat_suffix_nfc

Revert "[RISCV][llvm] Simplify the name in VSD/VVL patterns. NFC (#176750)"

This reverts commit 6bd97e4e7d3fa296b13ad3a9644901714d0e34f1.

Delta		File
+46	-39	llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+35	-28	llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+81	-67	2 files

LLVM/project 6bd97e4 — llvm/lib/Target/RISCV RISCVInstrInfoVVLPatterns.td RISCVInstrInfoVSDPatterns.td

2026-01-21 06:41:11 UTC by Brandon Wu via GitHub on ⎇

revert-176750-pat_suffix_nfc

[RISCV][llvm] Simplify the name in VSD/VVL patterns. NFC (#176750)

stack on: https://github.com/llvm/llvm-project/pull/176744

Delta		File
+39	-46	llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+28	-35	llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+67	-81	2 files

LLVM/project a62921f — mlir/lib/Dialect/Linalg/Transforms Vectorization.cpp, mlir/test/Dialect/Linalg/vectorization convolution-with-patterns.mlir convolution-with-patterns-flatten.mlir

2026-01-21 06:41:01 UTC by Abhishek Varma via GitHub on ⎇

revert-176750-pat_suffix_nfc

[Linalg] Update Vectorization to work with both named as well as generic conv ops (#176339)

-- This commit updates Vectorization to work with both named as well as
generic convolution ops. This concerns an update to the specialized path
already taken for vectorizing named convolution op.

-- Therefore the functions updated are : `vectorizeConvolution`,
`vectorizeDynamicConvOpPrecondition`,
`vectorizeScalableVectorPrecondition` and `vectorizeOpPrecondition`.

-- Changes were made to the constructor of `Conv1DGenerator` which is
invoked by `vectorizeConvolution` to check the precondition iof the op
being a valid 1D Conv Op with extractable strides/dilations info.

-- In order to not duplicate the tests for generic convolution ops, we
add another `RUN:` line which would first generalize the named
convolution ops and then apply the vectorizing transformation.

Signed-off-by: Abhishek Varma <abhvarma at amd.com>

Delta		File
+81	-40	mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
+27	-24	mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns.mlir
+7	-4	mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns-flatten.mlir
+6	-3	mlir/test/Dialect/Linalg/vectorization/convolution.mlir
+121	-71	4 files

LLVM/project d23c3a5 — llvm/test/CodeGen/RISCV/rvv vfmadd-constrained-sdnode.ll vfsub-constrained-sdnode.ll

2026-01-21 06:40:01 UTC by Brandon Wu via GitHub on ⎇

revert-176750-pat_suffix_nfc

[RISCV][llvm] Support strict fadd/fsub/fmul/fma codegen for zvfbfa (#176719)

This is same as normal version.

stack on: https://github.com/llvm/llvm-project/pull/176716

Delta		File
+386	-305	llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
+277	-193	llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
+259	-181	llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
+259	-181	llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
+352	-66	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
+346	-56	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
+1,879	-982	3 files not shown
+2,541	-1,107	9 files

HardenedBSD/src 53d6b23 — usr.sbin/cron/cron cron.8

2026-01-21 06:33:48 UTC by Xin LI (delphij) on ⎇

freebsd/current/main

cron.8: clarify system crontab format

PR:             234504
MFC after:      1 week

Delta		File
+6	-5	usr.sbin/cron/cron/cron.8
+6	-5	1 files

FreeBSD/src 53d6b23 — usr.sbin/cron/cron cron.8

2026-01-21 06:33:48 UTC by Xin LI (delphij) on ⎇

main

cron.8: clarify system crontab format

PR:             234504
MFC after:      1 week

Delta		File
+6	-5	usr.sbin/cron/cron/cron.8
+6	-5	1 files

NetBSD/pkgsrc-wip 059599a — emscripten PLIST Makefile, emscripten/patches patch-tools_config.py

2026-01-21 06:29:30 UTC by Mayuresh on ⎇

master

emscripten: very touchy about llvm version, downgraded to highest that works with llvm 19

Delta		File
+248	-2,157	emscripten/PLIST
+8	-3	emscripten/Makefile
+4	-4	emscripten/patches/patch-tools_config.py
+4	-4	emscripten/distinfo
+264	-2,168	4 files

LLVM/project 3bab752 — llvm/test/CodeGen/RISCV/rvv fixed-vectors-vfnmadd-sdnode.ll fixed-vectors-vfmsub-sdnode.ll

2026-01-21 06:26:20 UTC by Brandon Wu via GitHub on ⎇

main

[RISCV][llvm] Correct code generation of fma on zvfbfa (#176716)

Currently it's mapped to normal float16 instructions.

Delta		File
+20	-20	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-sdnode.ll
+20	-20	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-sdnode.ll
+20	-20	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-sdnode.ll
+20	-20	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-sdnode.ll
+13	-13	llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
+12	-12	llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
+105	-105	4 files not shown
+143	-141	10 files

LLVM/project 9429a1e — llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU simulated-trap-pseudo-expand.ll

2026-01-21 06:22:38 UTC by Dark Steve via GitHub on ⎇

main

[AMDGPU] Fix insertSimulatedTrap to return correct continuation block (#174774)

`insertSimulatedTrap` was returning `HaltLoopBB` when the trap was in a
block with no successors and was the last instruction. Since
`HaltLoopBB` gets appended to the end of the function, `FinalizeISel`
would jump there and skip any intermediate blocks, leaving their pseudos
unexpanded.

Fix by returning `MBB.getNextNode()` unconditionally:
- After `splitAt()`: `getNextNode()` returns the split-off block
(`ContBB`)
- No split, `MBB` in middle: `getNextNode()` returns the next original
block
- No split, `MBB` was last: `getNextNode()` returns `HaltLoopBB` (just
pushed)

Since we always `push_back(HaltLoopBB)` before returning,
`getNextNode()` can never be `nullptr`: if `MBB` was the last block,
`HaltLoopBB` is now after it.

Fixes: SWDEV-572407

Delta		File
+56	-0	llvm/test/CodeGen/AMDGPU/simulated-trap-pseudo-expand.ll
+2	-8	llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+58	-8	2 files

LLVM/project c307474 — clang/test/CIR/CodeGen inline-asm.c, llvm/lib/Target/AMDGPU AMDGPU.td

2026-01-21 06:21:59 UTC by Alex Richardson on ⎇

users/arichardson/spr/risc-vmc-introduce-initial-support-rvy-cheri

address most review commments, will continue tomorrow.

Created using spr 1.3.8-beta.1

Delta		File
+453	-975	llvm/test/CodeGen/X86/avgceils.ll
+1,197	-0	llvm/test/CodeGen/AArch64/nontemporal-store.ll
+292	-821	llvm/lib/Target/AMDGPU/AMDGPU.td
+259	-819	llvm/test/CodeGen/X86/avgceilu.ll
+0	-798	llvm/test/CodeGen/AArch64/nontemporal.ll
+751	-2	clang/test/CIR/CodeGen/inline-asm.c
+2,952	-3,415	577 files not shown
+19,891	-7,694	583 files

LLVM/project fa2bd97 — clang/test/CIR/CodeGen inline-asm.c, llvm/lib/Target/AMDGPU AMDGPU.td

2026-01-21 06:21:51 UTC by Alex Richardson on ⎇

users/arichardson/spr/main.risc-vmc-introduce-initial-support-rvy-cheri

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]

Delta		File
+453	-975	llvm/test/CodeGen/X86/avgceils.ll
+1,197	-0	llvm/test/CodeGen/AArch64/nontemporal-store.ll
+292	-821	llvm/lib/Target/AMDGPU/AMDGPU.td
+259	-819	llvm/test/CodeGen/X86/avgceilu.ll
+0	-798	llvm/test/CodeGen/AArch64/nontemporal.ll
+751	-2	clang/test/CIR/CodeGen/inline-asm.c
+2,952	-3,415	573 files not shown
+19,775	-7,558	579 files