[RISCV] Account for Libcall spill size in RVV Offsets (#234395)
We were not calculating and storing the libcall spill size early enough
to take account of it when calculating frame offsets for RVV objects.
The libcall spill size is accounted for separately to the push/pop size
and any interrupt spill size.
Now we calculate the libcall spill size earlier and save it in the
RISCVMachineFunctionInfo, so all later calls to `getReservedSpillsSize`
will include it, as intended, including those done in
`getFrameIndexReference` (which were missing it before).
Assisted-by: AI
[lldb-dap] Accept a failed CreateTarget when attaching by process name (#233684)
Attach by name passes a process name as program, so CreateTarget fails
and its error stayed in the shared SBError. attachCommands then failed
after succeeding. Give CreateTarget its own error and keep the dummy
target.
rdar://190247729
TableGen: Look up sub-registers by index in a sorted array (#232814)
inferMatchingSuperRegClass looks up a sub-register by index for every
member of every register class, and each lookup walked the register's
std::map of sub-registers. After computeSuperRegs, replace the map with
an array sorted by index, and binary search it instead. The map is only
needed while the sub-registers are being computed. The instruction count
is about the same, but there are far fewer cache misses, and the array
takes less memory than the map.
AMDGPU tablegen runs that build the register bank:
Gigacycles CPU seconds Peak RSS (RegisterBank)
Before 650 202 837 MB
After 540 (-16.9%) 169 (-16.2%) 792 MB (-5.4%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[llvm-ir2vec] Add numpy to Python bindings requirements.txt (#234681)
The IR2Vec Python bindings return nanobind::ndarray<nanobind::numpy,
double> objects, which require numpy at runtime as declared in
pyproject.toml. Add numpy>=1.23 to
llvm/tools/llvm-ir2vec/Bindings/requirements.txt so buildbot
environments initialized from requirements.txt alone install numpy.
Couples with https://github.com/llvm/llvm-zorg/pull/1011
[MLGO] Do not evict live ranges with the same cascade number (#230468)
The default advisor already refuses this
Allowing it caused a regalloc assert on AMDGPU
[LLDB] Documentation - add link to DIL to lldb.llvm.org website (#234692)
This should add a link to the dil user and developer documentation, in
lldb/docs/resources/dil.md, to the main lldb.llvm.org web page.
fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms
Select merging AND-NOT operations with TableGen patterns instead of the C++ combine. Preserve the first operand in inactive lanes and use an unpredicated BIC when both predicates are all-active.
[AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms
Replace NOT followed by merging AND with BIC for expressions such as:
return svand_u32_m(pg, a, svnot_u32_x(pg, b));
Combine when NOT is the second operand and its predicate matches the AND
predicate or is all-active.
Use predicated BIC to preserve the AND's first operand in inactive
lanes. Use unpredicated BIC when the AND predicate is all-active.
Do not commute merging AND operands, since this would change inactive
results. Leave pairs with incompatible predicates unchanged.
This applies to all integer element widths. Update the pre-commit LLVM
expectations, including cases where combining would change the
result.
fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms
Lower AND_U to an AArch64 target DAG node and match that node in TableGen. Keep the predicate for matching AND-NOT pairs, and combine other cases to ordinary AND so generic simplifications remain available. Name the data operands and iterate over them directly.
[AMDGPU] Count WMMA scale copies against both operands
Copying a shared scale while its partner stays an SGPR adds a va_ssrc
issue without removing one. Choose copies from both scale operands.
[AMDGPU] Materialize subregister WMMA scales at lane width
Copy an SGPR subregister scale into a VGPR of that lane's size so two
lanes of one tuple stay independent.
Co-authored-by: Cursor <cursoragent at cursor.com>
[AMDGPU] Materialize WMMA SGPR scales to VGPRs before scheduling
v_wmma_scale scale operands accept an SGPR or a VGPR. On GFX12,
depctr_va_ssrc is a 1-deep counter, so each VALU instruction that reads
an SGPR scale takes the only scalar-source slot. A run of WMMA ops that
all read SGPR scales therefore serializes. One cross-bank copy pays for
that slot once; later WMMA ops then read a VGPR and no longer contend
for va_ssrc.
SIMaterializeWMMAScale runs at the end of the machine SSA optimizations,
after SIShrinkInstructions and before scheduling. It is skipped at -O0
and on targets older than GFX12. GFX1250 is included: the separate VALU
read-after-write hazard no longer applies there, but the dependency
counter still does.
The pass walks every WMMA that has scale_src0 and records virtual SGPR
uses of scale_src0 and scale_src1, grouped by register. Physical
registers and subregister uses are left alone. For each SGPR it inserts
a COPY into a low aligned VGPR (the lo256 class matching the scale's
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[SCEV][IndVars][NFC] Add tests for x >=s 0 from x <u y and y <=u 2^(n-1)
Let n be the bit width of x and y. If x <u y and y <=u 2^(n-1), then
x >=s 0. SCEV can't prove this yet.
Add tests for it.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV] Prove signed/unsigned implications in either operand order
SCEV could prove these implications only with the operands in the same
order:
- If a <u b and a, b have the same sign, then a <s b.
- If a <s b and a, b have the same sign, then a <u b.
- If a <u b and b >=s 0, then a <s b.
- If a <s b and b <s 0, then a <u b.
For example, it proved a <s b from a <u b and b >=s 0, but not b >s a.
Now it proves them in either order.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV] Derive x >=s 0 from x <u y and y <=u 2^(n-1)
Let n be the bit width of x and y. If x <u y and y <=u 2^(n-1), then
x <u 2^(n-1), so x >=s 0. Here y <=u 2^(n-1) means y >=s 0 or
y == INT_MIN. In the same way, if x <=u y and y <u 2^(n-1), then
x >=s 0.
This lets a guard like x <u len prove x >=s 0 when len is non-negative.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][IndVars][NFC] Add tests for x >=s 0 from x <u y with swapped operands
Let n be the bit width of x and y. If x <u y and y <=u 2^(n-1), then
x >=s 0. SCEV can't prove this yet when the operands of the compare to
prove are in the opposite order to the guard, e.g. 0 <=s x with
x <u y known.
Add tests for it.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV] Try other implications when sign-flipped ones fail
SCEV's isImpliedCondBalancedTypes tries to prove an implication
through several rules. There are rules for when a predicate to prove
is sign-flipped from the found predicate, and also there are other
rules, which, for example, try to prove the implication through
ranges.
Before, if a proof for a sign-flipped rule implication returned false,
we wouldn't check other rules and just bail out with false result too.
Now make those rules fall-through - if one rule couldn't be proven,
try other rules in the function.
An example query is x - 5 <s 5 with x <u 10 known.
The implication "a <u b and b >=s 0 --> a <s b" matches it,
but x - 5 <u 5 with x <u 10 known does not hold (e.g. x = 0),
so SCEV gave up.
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[SCEV][IndVars][NFC] Add tests for implied conditions with different signedness
SCEV can prove some signed conditions from unsigned ones and the other
way around. For example, it proves a <s b from a <u b and b >=s 0. But
it fails when the operands are in the opposite order, like b >s a.
Add tests for this.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][NFC] Factor isImpliedCondViaSignFlippedPred out of isImpliedCondBalancedTypes
Move the code that proves a condition from a found condition with the
other signedness into a new private function.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][IndVars][NFC] Add a test for signed conditions implied by unsigned bounds
SCEV can't prove some signed conditions that hold because of an
unsigned bound on the same value. For example, if x <u 10, then
0 <= x < 10, so x - 5 <s 5.
Add a test for it.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Update lower-control-flow-live-variables-update.mir checks
Fix the test failure after #234197 stopped adding kill flags on virtual
registers. The test checks were updated by #234174 assuming kill flags
were still added; the two changes landed independently.
LLM-aided
