[clang][OpenMP] Match device and target_device ISA names separately (#232996)
A context selector can name ISAs in both `device={isa(...)}` and
`target_device={isa(...)}`. These are separate selectors, but their ISA
names were checked together, so an ISA that the target does not support
made both selectors fail. The default match_all needs both selectors
anyway, but the `match_any` and `match_none` extensions selected the
wrong variant. For example, on x86-64:
```c
#pragma omp declare variant(variant) \
match(device = {isa(sse2)}, target_device = {isa(bogus_isa)}, \
implementation = {extension(match_any)})
```
did not select variant, although `device={isa(sse2)}` matches. Likewise,
`match_none` accepted a variant whose `target_device` ISA matched.
This patch records which selector each ISA name belongs to and check
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[LSR] Refine target-specific equality loop exits
Query target interest before computing the SCEV exit count.
Also cover samesign comparisons and remove a redundant IV operand check.
Assisted-by: TRAE CLI (GPT-5.6-Sol)
[AtomicExpand][NVPTX] Add single-lane atomic RMW coverage
Record current expansion and code generation before changing single-lane RMW legalization. Check the full pipeline separately from direct instruction selection while their output differs.
[LoongArch] Implement `computeKnownBitsForTargetNode()` cases for `V{ALL,ANY}_{,NON}ZERO` (#230799)
Currently, `emitVecCondBranchPseudo()` loads an constant 0/1 into the
destination GPR for `Pseudo{,X}VB{Z,NZ}{,_B,_H,_W,_D}`:
https://github.com/llvm/llvm-project/blob/762316e293d1db4f495bdbb545c31d588a1a2d62/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp#L9099-L9112
Yet their corresponding `SDNode`s, `V{ALL,ANY}_{,NON}ZERO`, are not
marked with matching range information in
`computeKnownBitsForTargetNode()`. Doing so elides unnecessary sign
extensions and could also help pattern matching in a later optimization.
[CIR][AMDGPU] Honor __launch_bounds__ on HIP kernels (#233929)
Map max threads to amdgpu-flat-work-group-size and min blocks to
amdgpu-waves-per-eu matching classic codegen
[LoongArch] Lower vector sign extension with VSLLWIL and VEXTH
vsllwil.{h.b/w.h/d.w} with a zero shift amount sign-extends the low
half of the source elements, and vexth.{h.b/w.h/d.w} the high half.
Use them for the custom SIGN_EXTEND legalization and for
SIGN_EXTEND_VECTOR_INREG, instead of computing the sign mask with vslti
and interleaving it with vilvl/vilvh, which takes one more instruction
per step. SIGN_EXTEND_VECTOR_INREG now also handles 4x extensions, which
previously fell back to a shuffle followed by a vslli/vsrai pair.
[mlir][arith] Honor finite min/max reduction identities (#232257)
I hit this while compiling a JAX transformer block through IREE/WebGPU
in JupyterLite. `linalg.softmax` requests a finite reduction
initializer, but `getIdentityValueAttr` returns NaN for `maxnumf`, which
Tint rejects.
Honor `useOnlyFiniteValue` for `maxnumf` and `minnumf`, preserving the
existing NaN identities when the flag is false. Update the existing
softmax check and add finite min/max reduction cases.
rpki-client: report on non-canonically ordered addresses in ROAs
This adds a warning (under verbose) if the ROAIPAddress families contain
out of order elements. It also warns (always) if IPv6 comes before IPv4.
The JSON output for ROAs in filemode grows a new noncanonical boolean.
ok job
[mlir] Notify rewriter listeners when hoisting constants (#233776)
`OperationFolder` was calling `op->moveBefore` without notifying the
rewriter.
Also, fixed use-after-free exposed in `TestSingleFold`,
`notifyOperationInserted` called both when op is materialized and when
it moved in the block, causing same op to be added multiple times,
`notifyOperationErased` would only remove one instance leaving remaining
pointers dangling.
[X86] Combine mask_beforefirst to (x - 1) & ~x in GPR
EVEX and libc use this pattern in strcpy etc. to set the bits before the lowest set bit. It works correctly for x=0 too, returning an all ones mask.
Because SSE/AVX/AVX2 promote vNi1 types, do this as a DAG combine before type legalization.
We need to restrict it to power of 2 types otherwise we hit a latent crash in combineToExtendBoolVectorInReg.
[VPlan] Use llvm.mask.beforefirst for computing early exit mask
This makes the cost more accurate and improves codegen for RISC-V. The codegen for an early exit loop with side effects then goes from:
.LBB0_3: # %vector.body
# =>This Inner Loop Header: Depth=1
vl1r.v v16, (a3)
vsetvli zero, zero, e8, m1, ta, ma
vmseq.vi v16, v16, 0
vfirst.m a7, v16
srli t0, a7, 63
czero.nez a7, a7, t0
czero.eqz t0, a1, t0
or a7, t0, a7
vsetvli zero, zero, e64, m8, ta, ma
vmsltu.vx v0, v8, a7
vle8.v v17, (a5), v0.t
vcpop.m t1, v16
vsetvli zero, zero, e8, m1, ta, ma
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[SelectionDAG] Handle splitting in get_active_lane_mask expansion
Split when the type is legal, e.g. v64i1, but the step vector needed for expansion needs split, e.g. v64i8.
This can happen on avx512 when the 512 bit registers are disabled.
[SelectionDAG] Fix get_active_lane_mask expansion on 32-bit targets
On e.g. wasm32, OpVT can be 32 bits whilst the StepVector type can be v2i64. When this happens DAG.getConstant asserts because maxUIntN doesn't fit into the 32 bits. Fix this by clamping it to OpVT's max size.
