LLVM/project e044c4aclang/include/clang/Basic BuiltinsAMDGPU.td, clang/test/CodeGenOpenCL builtins-amdgcn-swmmac-gfx1250-err.cl builtins-amdgcn-swmmac-w32-gfx10-err.cl

[AMDGPU] Add target features for SWMMAC instructions (#185785)

Introduce `swmmac-gfx1200-insts` and `swmmac-gfx1250-insts`
DeltaFile
+36-36clang/include/clang/Basic/BuiltinsAMDGPU.td
+36-0clang/test/CodeGenOpenCL/builtins-amdgcn-swmmac-gfx1250-err.cl
+31-0clang/test/CodeGenOpenCL/builtins-amdgcn-swmmac-w32-gfx10-err.cl
+30-0clang/test/CodeGenOpenCL/builtins-amdgcn-swmmac-w64-gfx10-err.cl
+13-1llvm/lib/Target/AMDGPU/AMDGPU.td
+6-1llvm/lib/TargetParser/TargetParser.cpp
+152-381 files not shown
+156-387 files

LLVM/project f42df8cclang/include/clang/AST TemplateBase.h, clang/lib/AST TemplateBase.cpp TypeLoc.cpp

[clang] fix crash related to missing source locations for converted template arguments

This adds a way to attach source locations to trivially created template
arguments such as packs, or converted expressions when there is no
expression anymore.

This also avoids crashes due to missing source locations.

In a few places where this matters, we already create expressions
from the converted arguments, but this requires access to Sema,
where currently creating trivial typelocs only requires access to
to the ASTContext.

So this creates a new storage kind for TemplateArgumentLocs, where
a single SourceLocation is stored, embedded in the pointer where
possible.

As a drive-by, strenghten asserts by enforcing the TemplateArgumentLocs
are created with the right kinds of locations.

    [2 lines not shown]
DeltaFile
+54-3clang/include/clang/AST/TemplateBase.h
+19-0clang/lib/AST/TemplateBase.cpp
+4-4clang/lib/Sema/SemaExpr.cpp
+2-5clang/lib/AST/TypeLoc.cpp
+7-0clang/test/SemaCXX/type_pack_element.cpp
+3-3clang/lib/Sema/SemaTemplate.cpp
+89-152 files not shown
+91-168 files

LLVM/project 3de7814mlir/lib/Conversion/XeVMToLLVM XeVMToLLVM.cpp, mlir/test/Conversion/XeVMToLLVM legalize_large_vector.mlir

[MLIR][XeVM] Update HandleVectorExtractPattern (#186247)

isExtractContiguousSlice:
- Check if mask size is not greater than the vector size of the operand.
- Check if mask values do not exceed vector size. 

HandleVectorExtractPattern:
- Narrow the scope of matching to, 
  - Source shuffle doing contiguous extract
  - Source shuffle with at least the same mask size.
DeltaFile
+24-0mlir/test/Conversion/XeVMToLLVM/legalize_large_vector.mlir
+19-2mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
+43-22 files

LLVM/project a9181e8clang/lib/CIR/Dialect/Transforms FlattenCFG.cpp, clang/test/CIR/CodeGen loop-cond-cleanup.cpp

[CIR] Fix CFG flattening for loops with cleanup in special regions (#187369)

If a loop required a cleanup scope in the condition or step region of
the loop, we crashed during CFG flattening because the flattening of the
cleanup scope created multiple blocks in the region, but we were
assuming there would only be one block.

This change updates the CFG flattening code to look for the
cir.condition or cir.yield operation in the last block of the region.
DeltaFile
+243-0clang/test/CIR/CodeGen/loop-cond-cleanup.cpp
+12-5clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
+255-52 files

LLVM/project c95af40mlir/include/mlir/Dialect/LLVMIR XeVMOps.td, mlir/lib/Dialect/LLVMIR/IR XeVMDialect.cpp

[MLIR][XeVM] Add truncf and mma_mx op. (#180055)

truncf op converts 16 bit floats to 8 bit or 4 bit floats.
mma_mx op does cooperative matrix multiply accumulate on
8 or 4 bit float type with 8bit scale value.
DeltaFile
+100-4mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
+32-0mlir/test/Dialect/LLVMIR/xevm.mlir
+31-0mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
+25-0mlir/test/Dialect/LLVMIR/invalid.mlir
+188-44 files

LLVM/project 0b49adcllvm/lib/Target/AMDGPU AMDGPUMachineFunctionInfo.cpp AMDGPUMachineFunction.cpp

[AMDGPU] Rename AMDGPUMachineFunction to AMDGPUMachineFunctionInfo. NFC. (#187276)

This is derived from MachineFunctionInfo not MachineFunction.
DeltaFile
+237-0llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
+0-235llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
+0-137llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
+125-0llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.h
+6-6llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+5-4llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+373-38216 files not shown
+399-40722 files

LLVM/project fce100ellvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize predicated-multiple-exits.ll predicated-early-exits-interleave.ll

[VPlan] Fix masked_cond expansion.

masked_cond is used to combine early-exit conditions with masks from
predicate. The early-exit condition should only be evaluated if the mask
is true. Emit the mask first, to avoid incorrect poison propagation.

Fixes https://github.com/llvm/llvm-project/issues/187061.
DeltaFile
+24-24llvm/test/Transforms/LoopVectorize/predicated-multiple-exits.ll
+8-8llvm/test/Transforms/LoopVectorize/predicated-early-exits-interleave.ll
+5-5llvm/test/Transforms/LoopVectorize/predicated-single-exit.ll
+1-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+38-384 files

LLVM/project d1e625cclang-tools-extra/docs ReleaseNotes.rst, clang-tools-extra/docs/clang-tidy/checks/bugprone unchecked-optional-access.rst

[clang-tidy] `bugprone-unchecked-optional-access`: Add support for GTest asserts like `ASSERT_TRUE` and `ASSERT_FALSE` (#186363)

Resolves  https://github.com/llvm/llvm-project/issues/181737

Addresses false positives reported in
https://github.com/llvm/llvm-project/issues/181737 .

This PR is heavily inspired by
https://github.com/llvm/llvm-project/pull/170947 .

Many thanks to @fmayer for the prior work.

---------

Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
DeltaFile
+90-0clang/lib/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.cpp
+67-0clang/unittests/Analysis/FlowSensitive/UncheckedOptionalAccessModelTest.cpp
+19-0clang-tools-extra/docs/clang-tidy/checks/bugprone/unchecked-optional-access.rst
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+181-04 files

LLVM/project aeff312llvm/test/CodeGen/AMDGPU machine-scheduler-sink-trivial-remats-attr.mir

[AMDGPU] Remastered 1 test now that TargetOccupancy is clamped.
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
+2-21 files

LLVM/project 5a5c317mlir/include/mlir-c/Target ExportSMTLIB.h, mlir/include/mlir/Target/SMTLIB ExportSMTLIB.h

[MLIR][Python] Add optional emit reset to exportSMTLIB (#187366)

Previously, the MLIR's python binding `smt.export_smtlib(...)` always
emit `(reset)` to the end of smtlib string as a solver terminator.
This PR added an option to suppress this trailing, as downstream users
like python z3 module don't need it.
DeltaFile
+12-14mlir/lib/CAPI/Target/ExportSMTLIB.cpp
+9-8mlir/lib/Bindings/Python/DialectSMT.cpp
+8-3mlir/test/CAPI/smt.c
+4-4mlir/include/mlir-c/Target/ExportSMTLIB.h
+2-1mlir/lib/Target/SMTLIB/ExportSMTLIB.cpp
+2-0mlir/include/mlir/Target/SMTLIB/ExportSMTLIB.h
+37-306 files

OpenBSD/ports fJfY9kAwww/webkitgtk4 distinfo Makefile, www/webkitgtk4/patches patch-Source_WebCore_platform_graphics_gbm_MemoryMappedGPUBuffer_cpp

   Update to webkitgtk{41,60}-2.52.0.
VersionDeltaFile
1.10+1-8www/webkitgtk4/pkg/PFRAG.webkitgtk60
1.4+2-2www/webkitgtk4/patches/patch-Source_WebCore_platform_graphics_gbm_MemoryMappedGPUBuffer_cpp
1.143+2-2www/webkitgtk4/distinfo
1.254+1-1www/webkitgtk4/Makefile
1.37+0-1www/webkitgtk4/pkg/PLIST
1.9+1-0www/webkitgtk4/pkg/PFRAG.no-webkitgtk60
+7-146 files

LLVM/project 360fab6llvm/lib/Target/RISCV RISCVSchedSiFive7.td RISCVInstrPredicates.td, llvm/test/tools/llvm-mca/RISCV/Inputs mul-div-rv32.s

[RISCV] Fix IDiv/IRem scheduling data for RV32 cores that use the SiFive7 model (#187331)

The integer division and remainder instructions on a 32-bit core that
uses SiFive7 scheduling model should have the same latency and
throughput as its word counterparts on a 64-bit SiFive7 core.

This patch fixes those scheduling entries by adding a new SchedPred that
predicates on `Feature64Bit` to toggle the SchedVariant that is attached
on the affected integer division / remainder instructions.
DeltaFile
+59-0llvm/test/tools/llvm-mca/RISCV/SiFive7/mul-div-rv32.test
+15-6llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+10-0llvm/test/tools/llvm-mca/RISCV/Inputs/mul-div-rv32.s
+4-0llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+88-64 files

LLVM/project 2be4a9bllvm/test/Transforms/LoopVectorize predicated-multiple-exits.ll

[LV] Add predicated early-exit tests showing poison prop issue. (NFC)

Add tests showing incorrect poison propagation from
https://github.com/llvm/llvm-project/issues/187061.
DeltaFile
+135-0llvm/test/Transforms/LoopVectorize/predicated-multiple-exits.ll
+135-01 files

LLVM/project d226f1bllvm/test/CodeGen/AMDGPU memory-legalizer-flat-singlethread.ll memory-legalizer-private-workgroup.ll

[AMDGPU] Regenerate codegen tests to check extra stuff at end of line (#187325)

Regenerate checks after two recent commits that caused extra stuff to be
added at the end of assembly lines, so the existing checks did not fail.

- #179414 added "nv" to loads and stores on GFX1250.
- #185774 added "msbs" comments on setreg instructions.
DeltaFile
+336-336llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
+336-336llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
+336-336llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+336-336llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
+336-336llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
+336-336llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
+2,016-2,016150 files not shown
+12,910-12,686156 files

LLVM/project 6c371eelibc/src/__support/annex_k libc_constraint_handler.h

fix format
DeltaFile
+1-1libc/src/__support/annex_k/libc_constraint_handler.h
+1-11 files

LLVM/project b39cdc0libc/config/linux/aarch64 entrypoints.txt, libc/config/linux/x86_64 entrypoints.txt

[libc][stdlib][annex_k] Add ignore_handler_s.
DeltaFile
+22-0libc/src/stdlib/ignore_handler_s.h
+16-0libc/src/stdlib/ignore_handler_s.cpp
+13-0libc/src/stdlib/CMakeLists.txt
+9-0libc/include/stdlib.yaml
+2-1libc/config/linux/x86_64/entrypoints.txt
+1-0libc/config/linux/aarch64/entrypoints.txt
+63-12 files not shown
+65-18 files

LLVM/project d3328e6libc/config/linux/aarch64 entrypoints.txt, libc/config/linux/x86_64 entrypoints.txt

[libc][stdlib][annex_k] Add set_constraint_handler_s.
DeltaFile
+28-0libc/src/stdlib/set_constraint_handler_s.cpp
+21-0libc/src/stdlib/set_constraint_handler_s.h
+11-0libc/src/stdlib/CMakeLists.txt
+7-0libc/include/stdlib.yaml
+1-0libc/config/linux/x86_64/entrypoints.txt
+1-0libc/config/linux/aarch64/entrypoints.txt
+69-01 files not shown
+70-07 files

LLVM/project db0a7balibc/include stdlib.yaml, libc/src/__support/annex_k abort_handler_s.h CMakeLists.txt

[libc][annex_k] Add abort_handler_s.
DeltaFile
+43-0libc/src/__support/annex_k/abort_handler_s.h
+22-0libc/src/stdlib/abort_handler_s.h
+20-0libc/src/stdlib/abort_handler_s.cpp
+14-2libc/include/stdlib.yaml
+12-0libc/src/__support/annex_k/CMakeLists.txt
+10-0libc/src/stdlib/CMakeLists.txt
+121-25 files not shown
+126-211 files

LLVM/project 34310ablibc/src/__support/annex_k constraint_macros.h CMakeLists.txt

[libc][annex_k] Add libc_constraint_handler macros.
DeltaFile
+44-0libc/src/__support/annex_k/constraint_macros.h
+9-0libc/src/__support/annex_k/CMakeLists.txt
+53-02 files

LLVM/project 4b6a61dlibc/src/__support/annex_k libc_constraint_handler.h CMakeLists.txt

[libc][annex_k] Add libc_constraint_handler.
DeltaFile
+26-0libc/src/__support/annex_k/libc_constraint_handler.h
+9-0libc/src/__support/annex_k/CMakeLists.txt
+35-02 files

LLVM/project d1f6cb9libc/include/llvm-libc-types CMakeLists.txt

change location
DeltaFile
+1-2libc/include/llvm-libc-types/CMakeLists.txt
+1-21 files

LLVM/project 96299d8flang-rt/test lit.site.cfg.py.in, flang-rt/test/Driver safe-trampoline-gnustack.f90

[flang] Disable trampoline test for PPC (NFC) (#187194)
DeltaFile
+1-0flang-rt/test/lit.site.cfg.py.in
+1-0flang-rt/test/Driver/safe-trampoline-gnustack.f90
+2-02 files

LLVM/project af23906libc/hdr/types constraint_handler_t.h CMakeLists.txt, libc/include CMakeLists.txt stdlib.yaml

[libc][annex_k] Add constraint_handler_t.
DeltaFile
+21-0libc/include/llvm-libc-types/constraint_handler_t.h
+18-0libc/hdr/types/constraint_handler_t.h
+9-0libc/hdr/types/CMakeLists.txt
+2-0libc/include/llvm-libc-types/CMakeLists.txt
+1-0libc/include/CMakeLists.txt
+1-0libc/include/stdlib.yaml
+52-06 files

LLVM/project d4b86e5llvm/include/llvm/Analysis IVUsers.h, llvm/lib/Transforms/Scalar LoopStrengthReduce.cpp

[LSR] skip ephemeral IV users when collecting IV chains (#187282)

IVUsers records ephemeral values used only by `llvm.assume` as IV
operands in the Processed set. As a result, `CollectChains` picks them
up and builds unnecessary increment chains. Fix this by checking
`IVUsers::isEphemeral` before collecting the chains.

Fixes #187270
DeltaFile
+67-0llvm/test/Transforms/LoopStrengthReduce/X86/iv-chain-assume-ephemeral.ll
+4-0llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+2-0llvm/include/llvm/Analysis/IVUsers.h
+73-03 files

LLVM/project 170b87dlibc/hdr/types errno_t.h CMakeLists.txt, libc/include/llvm-libc-types CMakeLists.txt errno_t.h

apply suggestions from code review
DeltaFile
+14-2libc/hdr/types/errno_t.h
+1-1libc/include/llvm-libc-types/CMakeLists.txt
+2-0libc/include/llvm-libc-types/errno_t.h
+0-1libc/hdr/types/CMakeLists.txt
+17-44 files

LLVM/project 403ae32libc/hdr/types rsize_t.h CMakeLists.txt, libc/include/llvm-libc-types rsize_t.h CMakeLists.txt

[libc][annex_k] Add rsize_t.
DeltaFile
+23-0libc/hdr/types/rsize_t.h
+18-0libc/include/llvm-libc-types/rsize_t.h
+8-0libc/hdr/types/CMakeLists.txt
+1-0libc/include/llvm-libc-types/CMakeLists.txt
+50-04 files

LLVM/project 43cec7bmlir/tools/mlir-tblgen OpPythonBindingGen.cpp EnumPythonBindingGen.cpp

refactor to use external stoarge
DeltaFile
+9-6mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
+2-2mlir/tools/mlir-tblgen/EnumPythonBindingGen.cpp
+11-82 files

LLVM/project c630b09clang/lib/CIR/CodeGen CIRGenExprScalar.cpp

[CIR][NFC] Remove NYI checks in ternary with cleanup (#186870)

We added those checks when CleanupScopeOp is used to emit an error
message in this edge case until we fix it. Now it's already fixed, and
we don't need to keep the NYI
DeltaFile
+0-8clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+0-81 files

FreeNAS/freenas 4b3f8e0src/middlewared/middlewared/plugins/fc fc.py, src/middlewared/middlewared/plugins/rdma rdma.py

cli_private = True
DeltaFile
+3-0src/middlewared/middlewared/plugins/rdma/rdma.py
+1-0src/middlewared/middlewared/plugins/fc/fc.py
+4-02 files

LLVM/project 50fcaffllvm/lib/Target/AMDGPU GCNSubtarget.h GCNSchedStrategy.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp AMDGPUBaseInfo.h

[AMDGPU] Updated getMaxNumAGPRs to use getMaxNumVectorRegs.

Removed other variants of getMaxNumAGPRs. So with this patch, there
is only one way to get the maximum number of AGPRs. If the client
provides a target occupancy, that value will be used. Otherwise,
the function level attributes for waves-per-eu are used. In both the
cases, the utility uses getMaxNumVectorRegs.
DeltaFile
+330-330llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
+0-19llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+4-3llvm/lib/Target/AMDGPU/GCNSubtarget.h
+0-7llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+2-2llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+2-2llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
+338-3636 files