FreeNAS/freenas dbea9f2debian/debian control, src/freenas/debian control changelog

clean up maintainer/copyright names
DeltaFile
+2-2src/middlewared/debian/changelog
+1-1src/middlewared/debian/copyright
+1-1src/middlewared/debian/control
+1-1src/freenas/debian/control
+1-1src/freenas/debian/changelog
+1-1debian/debian/control
+7-73 files not shown
+10-109 files

LLVM/project a84d948lldb/source/Plugins/Process/gdb-remote ProcessGDBRemote.cpp ProcessGDBRemoteProperties.td, lldb/test/API/functionalities/gdb_remote_client TestPacketTestDelay.py

[lldb] Add a packet-test-delay setting for testing slow connections (#195440)

[lldb] Add a packet-test-delay setting for testing slow connections

Sending/receiving packets to/from a non-host devices adds latency to
the gdb-remote communication that induces substantial slowdown into the
debugging experience.

This patch adds an artificial delay before sending a packet to
simulate this latency without requiring an emulated/physical device.

The test checks only checks that there is a delay when this setting is
activated, but not that there is no delay when the setting is not
activated. The reason for this is that this negative test would either
require a large delay (which further slows down the test suite) or be
prone to accidential failures on overloaded test bots.

There is also the question whether we should have dynamic delays that
depend on the number of transferred bytes. From talking to Felipe it

    [10 lines not shown]
DeltaFile
+39-0lldb/test/API/functionalities/gdb_remote_client/TestPacketTestDelay.py
+11-0lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+6-0lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemoteProperties.td
+6-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
+2-0lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
+64-05 files

LLVM/project 6870932clang/include/clang/Basic AttrDocs.td, lldb/docs/resources lldbgdbremote.md

Merge branch 'main' into users/kasuga-fj/loop-interchange-test-ninf
DeltaFile
+26-5lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
+25-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+20-1lldb/include/lldb/Host/common/NativeProcessProtocol.h
+11-2lldb/docs/resources/lldbgdbremote.md
+12-0lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
+3-1clang/include/clang/Basic/AttrDocs.td
+97-92 files not shown
+102-108 files

LLVM/project ce82ed0llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange ninf.ll reduction2mem.ll

[LoopInterchange] Drop ninf from instructions involved in interchange
DeltaFile
+32-11llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+1-1llvm/test/Transforms/LoopInterchange/ninf.ll
+1-1llvm/test/Transforms/LoopInterchange/reduction2mem.ll
+34-133 files

LLVM/project ea922dalldb/docs/resources lldbgdbremote.md, lldb/include/lldb/Host/common NativeProcessProtocol.h

[lldb][windows] Plumb Windows DLL load/unload through lldb-server (#197901)
DeltaFile
+26-5lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
+25-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+20-1lldb/include/lldb/Host/common/NativeProcessProtocol.h
+11-2lldb/docs/resources/lldbgdbremote.md
+12-0lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
+3-0lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+97-86 files

LLVM/project 521469allvm/test/Transforms/LoopInterchange ninf.ll

fix typo
DeltaFile
+1-1llvm/test/Transforms/LoopInterchange/ninf.ll
+1-11 files

LLVM/project 88b3c4ellvm/test/Transforms/LoopInterchange ninf.ll

[LoopInterchange] Add test for poison can be produced due to ninf (NFC)
DeltaFile
+154-0llvm/test/Transforms/LoopInterchange/ninf.ll
+154-01 files

FreeBSD/src 65341ecsys/dev/sound/pci/hda hdaa.c

snd_hda: Reassign duplicate HDMI/DP pin sequences instead of disabling

Some firmware (e.g. Apple EFI on Sandy Bridge Mac hardware) programs all
HDMI/DP output pins in an association with identical sequence numbers.

The existing code disables the entire association on the first
duplicate, leaving HDMI/DP audio non-functional.

For digital output pins (HDMI/DP) with seq=0 duplicates, search for the
next free sequence slot and reassign the duplicate rather than
disabling.

The seq=0 restriction targets the known Apple firmware pattern; any
other duplicate sequence is more likely a genuine firmware error and the
association is still disabled.

Update first after reassignment so that hpredir is not left pointing at
a stale sequence. Non-digital and input associations retain the existing
disable behaviour.

    [4 lines not shown]
DeltaFile
+45-4sys/dev/sound/pci/hda/hdaa.c
+45-41 files

LLVM/project f8114d6llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange dependency-all-eq.ll pr43176-move-to-new-latch.ll

[LoopInterchange] Relax legality check to accept more patterns
DeltaFile
+103-42llvm/test/Transforms/LoopInterchange/dependency-all-eq.ll
+15-0llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+8-6llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
+4-6llvm/test/Transforms/LoopInterchange/inner-only-reductions.ll
+6-3llvm/test/Transforms/LoopInterchange/legality-check.ll
+0-8llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
+136-651 files not shown
+140-697 files

LLVM/project d7b3648llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange dependency-all-eq.ll

[LoopInterchange] Change the cost model to interchange `[* =]`
DeltaFile
+30-53llvm/test/Transforms/LoopInterchange/dependency-all-eq.ll
+33-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+63-552 files

LLVM/project be93ab8llvm/test/Transforms/LoopInterchange dependency-all-eq.ll

[LoopInterchange] Add test with dependency `[* =]` and `[= *]` (NFC)
DeltaFile
+117-0llvm/test/Transforms/LoopInterchange/dependency-all-eq.ll
+117-01 files

LLVM/project e66df94llvm/test/Transforms/LoopInterchange loop-interchange-optimization-remarks.ll

fix test
DeltaFile
+3-2llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
+3-21 files

LLVM/project 50f787fllvm/test/Transforms/LoopInterchange profitability-vectorization.ll

address review comment
DeltaFile
+1-1llvm/test/Transforms/LoopInterchange/profitability-vectorization.ll
+1-11 files

LLVM/project 3aae85ellvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-vectorization.ll lcssa-phi-outer-latch.ll

[LoopInterchange] Disable LoopCacheAnalysis-based heuristic by default
DeltaFile
+3-3llvm/test/Transforms/LoopInterchange/profitability-vectorization.ll
+1-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+1-1llvm/test/Transforms/LoopInterchange/lcssa-phi-outer-latch.ll
+1-1llvm/test/Transforms/LoopInterchange/loop-interchange-optimization-remarks.ll
+1-1llvm/test/Transforms/LoopInterchange/perserve-lcssa.ll
+1-1llvm/test/Transforms/LoopInterchange/pr57148.ll
+8-91 files not shown
+9-107 files

LLVM/project 33ac117llvm/lib/Transforms/Scalar LoopInterchange.cpp

update impl
DeltaFile
+5-13llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+5-131 files

LLVM/project cbddf99llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-instorder.ll

[LoopInterchange] Take base pointer into account in profitability check
DeltaFile
+18-7llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+7-17llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+25-242 files

LLVM/project b4aca7aclang/docs/analyzer/user-docs Annotations.rst, clang/include/clang/Basic AttrDocs.td

[NFC] Clarify behavior of ownership_holds in docs (#197933)

I misunderstood the behavior of the attribute `ownership_holds` based on
the claim that "using held memory is assumed to be legitimate".

To avoid similar misunderstandings in the future, I'm adding an extra
sentence to the documentation.

(This question came up during the discussion of #196798)
DeltaFile
+3-1clang/include/clang/Basic/AttrDocs.td
+2-1clang/docs/analyzer/user-docs/Annotations.rst
+5-22 files

FreeBSD/ports e65d87dgames/yquake2 distinfo Makefile, games/yquake2/files patch-Makefile patch-src_common_filesystem.c

games/yquake2: Update 8.60 => 8.70

Changelog:
https://github.com/yquake2/yquake2/blob/QUAKE2_8_70/CHANGELOG

PR:             295404
Sponsored by:   UNIS Labs
DeltaFile
+4-4games/yquake2/files/patch-Makefile
+3-3games/yquake2/distinfo
+3-3games/yquake2/Makefile
+2-2games/yquake2/files/patch-src_common_filesystem.c
+12-124 files

LLVM/project e408703llvm/test/Transforms/LoopInterchange profitability-instorder.ll

[LoopInterchange] Add test for multiple accesses to same base ptr (NFC)
DeltaFile
+86-2llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+86-21 files

LLVM/project 7b25585llvm/test/Transforms/LoopInterchange profitability-instorder.ll

address review comment
DeltaFile
+7-7llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+7-71 files

LLVM/project fdb9af5llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-instorder.ll

update
DeltaFile
+30-28llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+28-28llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+58-562 files

LLVM/project 1da8f18llvm/lib/Transforms/Scalar LoopInterchange.cpp

address review comment
DeltaFile
+17-14llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+17-141 files

LLVM/project ed3342dllvm/test/Transforms/LoopInterchange profitability-instorder.ll

update test
DeltaFile
+42-51llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+42-511 files

LLVM/project 72ec524llvm/lib/Transforms/Scalar LoopInterchange.cpp

address review comments
DeltaFile
+16-2llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+16-21 files

LLVM/project 1573cdbllvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-instorder.ll interchangeable-outerloop-multiple-indvars.ll

[LoopInterchange] Fix instorder profitability check
DeltaFile
+50-41llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+40-30llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+1-1llvm/test/Transforms/LoopInterchange/interchangeable-outerloop-multiple-indvars.ll
+91-723 files

LLVM/project 313cc46libc/cmake/modules LLVMLibCCheckCpuFeatures.cmake

[libc][cmake] Don't assume CPU features in cross builds (#198308)

Assuming all CPU features are available during cross builds will be
incorrect in some cases, such as armv8.0-a where FullFP16 is not
available and therefore FP16 instructions will not be understood.

Looking at the file history, the feature detection code previously
relied on try_run instead of try_compile, which might explain why it
couldn't be used in cross builds as cross built binaries wouldn't be
executable. But now the tests are compile only, they can work for cross
builds too, which would be better than assuming features.
DeltaFile
+13-19libc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
+13-191 files

LLVM/project 3361f70flang/include/flang/Frontend CompilerInvocation.h, flang/test lit.cfg.py

Post-merge fixes
DeltaFile
+11-43flang/test/Driver/intrinsic-module-path.f90
+9-9flang/test/Driver/intrinsic-module-path_per_target.f90
+9-2openmp/CMakeLists.txt
+6-1flang/test/lit.cfg.py
+0-7flang/include/flang/Frontend/CompilerInvocation.h
+1-1flang/test/Semantics/OpenMP/detach-symbols.f90
+36-633 files not shown
+38-659 files

LLVM/project 8111c07llvm/include/llvm/Transforms/Scalar Reassociate.h, llvm/lib/Transforms/Scalar Reassociate.cpp

[Reassociate] Use UniformityInfo to group uniform operands together
DeltaFile
+33-2llvm/lib/Transforms/Scalar/Reassociate.cpp
+9-9llvm/test/CodeGen/AMDGPU/reassoc-uniform-e2e.ll
+5-1llvm/include/llvm/Transforms/Scalar/Reassociate.h
+47-123 files

LLVM/project 75ae202llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ISelLowering.h, llvm/test/CodeGen/AArch64/GlobalISel knownbits-fcmeq.mir

[AArch64][GlobalISel] Add sign bits for G_FCMEQ (#198314)

This adds basic num-sign-bits for G_FCMEQ, G_FCMGE and G_FCMGT, which
all produce either all-ones or all-zeros in each vector lane. This
function apparently goes in AArch64ISelLowering.
DeltaFile
+45-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-fcmeq.mir
+19-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+6-0llvm/lib/Target/AArch64/AArch64ISelLowering.h
+70-03 files

OPNSense/plugins 0798cdenet/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms dialogEditOSPFRouteMaps.xml, net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga OSPF.xml

net/frr: OSPF improve many to one relationship between prefix lists and route maps, allow multiple selection
DeltaFile
+7-3net/frr/src/opnsense/service/templates/OPNsense/Quagga/ospfd.conf
+5-3net/frr/src/opnsense/mvc/app/models/OPNsense/Quagga/OSPF.xml
+0-1net/frr/src/opnsense/mvc/app/controllers/OPNsense/Quagga/forms/dialogEditOSPFRouteMaps.xml
+12-73 files