[libc] Add config option to use memory builtin functions. (#197977)
Add a new CMake and C++ definition configuration option
`LIBC_CONF_USE_MEM_BUILTINS` to allow users to use compiler builtins for
memory utility functions (memcpy, memset, memmove, memcmp, and bcmp)
instead of LLVM libc's internal implementations. Main use-cases are:
- when users want to bring their own memory functions implementations
that are highly optimized for their targets
- improve portability by providing a fallback for targets for which LLVM
libc does not have memory utility implementations yet
- to be used for libc/shared functions and their testings, as we expect
libc/shared functions to provide their own memory functions.
databases/Makefile: Remove deleted port
The port databases/leofs was removed but Makefile entry kept intact.
PR: 295318
Reported by: Robert William Vesterman <bob at vesterman.com>
Fixes: acf281bfdd77
Merge tag 'drm-fixes-2026-05-16' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Weekly fixes pull, small and all over fixes, mostly xe and amdgpu,
with some ttm and a core fix for the handle change pain.
core:
- fix for the fix for the handle change race
ttm:
- avoid infinite loop in swap out
- avoid infinite loop in BO shrinking
- convert -EAGAIN from dmem_cgroup_try_charge to -ENOSPC
bridge:
- imx8qxp-pxl2dpi: avoid ERR_PTR with device_node cleanup
i915:
- Skip __i915_request_skip() for already signaled requests
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[lldb] Fix data race in ObjectFile::GetSectionList (#197812)
The early `m_sections_up == nullptr` check was performed outside the
module mutex, so two threads sharing the same Module could both enter
the branch and race on the write in CreateSections. Restructure so the
check and populate both happen under the module mutex; this is a
standard double-checked locking fix.
Found by ThreadSanitizer as part of #197792.
filesystems/httpdirfs: Update 1.2.7 => 1.2.9
* Fit COMMENT within 70 characters limit
* Install more documentation files
* Prefer using pkg-plist for tracking installed files
* Combine 2 patches for the same file into one, remove upstreamed hunk
Approved by: db@, yuri@ (Mentors, implicit)
PGO] Drop consecutive-zeros.ll test
pgo-memop-opt has previously validated VP metadata and bailed if it runs
into duplicate values in the VP metadata. VP metadata values will soon
be deduplicated at construction, making this no longer necessary, and
will also cause this test to fail, so drop it. Keep the
verification/deduplication pgo-memop-opt for now to avoid leaving main
in a broken state.
Reviewers: mtrofin, ormris
Pull Request: https://github.com/llvm/llvm-project/pull/197615
drm: Replace old pointer to new idr
Commit 5e28b7b94408 introduced a logical error by failing to replace the
newly generated IDR pointer to old id's pointer at the correct location
within the "change handle" logic; this resulted in the issue reported by
syzbot [1].
Specifically, the new IDR object pointer is intended to replace the original
id's pointer during the normal execution flow.
Additionally, an unnecessary conditional check for the ret exit path has
been removed.
[1]
!RB_EMPTY_ROOT(&prime_fpriv->dmabufs)
WARNING: drivers/gpu/drm/drm_prime.c:224 at drm_prime_destroy_file_private+0x48/0x60 drivers/gpu/drm/drm_prime.c:224, CPU#0: syz.0.17/5833
Call Trace:
drm_file_free.part.0+0x7e6/0xcc0 drivers/gpu/drm/drm_file.c:269
drm_file_free drivers/gpu/drm/drm_file.c:237 [inline]
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[AMDGPU] Fix VOPD assembler validation for GFX12+ (#198034)
The related `codegen` side of this change was already landed by
https://github.com/llvm/llvm-project/commit/c510ee553e2057f94c2f023c72abb3c9afec0962
("[AMDGPU] VOPD: AllowSameVGPR on GFX12"), which changed
`GCNVOPDUtils.cpp` to use `hasGFX12Insts()` instead of
`hasGFX1250Insts()`.
However, the assembler validation in `AMDGPUAsmParser.cpp` was not
updated to match, causing it to reject valid VOPD instruction pairs that
share the same VGPR as src0 on `gfx1200`.
This fix aligns the assembler with the `codegen` by changing
`isGFX1250Plus()` to `isGFX12Plus()` in `checkVOPDRegBankConstraints`,
and adds a positive test case to verify same-VGPR src0 pairs assemble
correctly on `gfx12`.
[Instrumentor] Add call instrumentation support
We can now instrument call instructions and extract information about
the arguments, (de)allocation, intrinsic kind, etc.
[IR] Note that duplicate profile values are illegal in VP metadata
It is not legal to have duplicate VP metadata as it should be merged
appropriately before it actually ends up transcribed into the IR.
I will put up a verifier patch for this to follow this one, but do so
separately in case we need to revert due to detecting actual issues in
the code base.
Reviewers: david-xl, teresajohnson, mtrofin
Pull Request: https://github.com/llvm/llvm-project/pull/193077
[CIR][CUDA] Support device-side printf for NVPTX (#196573)
Implement device-side printf lowering for NVPTX targets in CIR codegen.
The variadic arguments are packed into a stack-allocated struct and
passed to vprintf, matching the classic codegen behavior in
CGGPUBuiltin.cpp
When the target triple is NVPTX and the builtin is
printf/__builtin_printf, we route to emitNVPTXDevicePrintfCallExpr
The no-varargs case passes a null pointer directly.
AMDGCN device printf remains NYI.
part of https://github.com/llvm/llvm-project/issues/179278
[MLIR] Add `IntegerDivisibilityAnalysis` and `InferIntDivisibilityOpInterface` (#197728)
This patch is a port from
https://github.com/iree-org/iree/blob/main/compiler/src/iree/compiler/Dialect/Util/Analysis/IntegerDivisibilityAnalysis.cpp
to upstream
It introduces a dataflow analysis that tracks integer divisibility
(divisor + remainder lattice) for SSA values, plus an op interface
`InferIntDivisibilityOpInterface` for ops to participate.
It adds:
* `IntegerDivisibilityAnalysis` produces a `Divisibility` lattice
`{divisor, remainder}`
* `InferIntDivisibilityOpInterface` interface
* External-model implementations for `arith` and `affine` ops
* `test-int-divisibility` test pass + lit tests
Example:
Here is the usual approach to laod element `i` from `i4` buffer emulated
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[flang][acc] Accept component of global variable in `acc declare` (#197819)
This MR partially extends the current implementation to accept cases of
`acc declare` on a `parent%comp` whenever the `parent` has been `acc
declare`d with the same clause. This is done by generating only the acc
global constructor only for mapping the parent as the child is expected
to be part of parent.
The limitations still remain as a TODO unless it can be proven parent is
mapped. A generic implementation would need either compiler generated
ordering on the global constructors used for mapping or runtime managed
ordering.
psci: ensure cores are in a known state before SYSTEM_OFF
The PSCI spec says that the caller must place all cores in a known state
prior to calling SYSTEM_OFF.
It doesn't really specify what a "known state" is, but it does suggest
that one way to do this is to call CPU_OFF on all other cores. So let's
do that.
This has the nice side effect of workaround around a heartbeat timeout
when attempting to power down a system with firmware that doesn't return
from a SYSTEM_OFF call but does not actually know how to power off the
system (like Rockchip's secure firmware on RK356x based boards).
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 MPAM fixes from Catalin Marinas:
- Fix NULL dereference and a false-positive warning when the driver
probes hardware with surprising version numbers
- Fix writing values to the wrong registers when probing
cache-utilisation counters. Replace 'NRDY' probing with a version
that is robust for platforms where the bit is writeable by both
hardware and software
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm_mpam: Check whether the config array is allocated before destroying it
arm_mpam: Fix false positive assert failure during mpam_disable()
arm_mpam: Improve check for whether or not NRDY is hardware managed
arm_mpam: Pretend that NRDY is always hardware managed
arm_mpam: Fix monitor instance selection when checking for hardware NRDY
[AArch64] Do not pass debug insn to liveness analysis (#198021)
Fix another stepBackward location.
Debug instructions must not affect liveness analysis. stepBackward has
an assertion failure on debug instructions after
https://github.com/llvm/llvm-project/pull/193104.
Signed-off-by: John Lu <John.Lu at amd.com>
[RISCV][MCA] Use the new infrastructure for SiFive P500 and P800's tests. NFC (#198016)
Some tests -- mostly vector crypto -- are kept for SiFive P800.
NFC.
