DragonFlyBSD/src 2a1028ccontrib/binutils-2.27/bfd elf.c, contrib/binutils-2.34/bfd elf.c

Fix some GCC 12.5 -Woverflow warnings (cast at initialization).
DeltaFile
+2-1usr.sbin/zic/zic.c
+2-1contrib/binutils-2.34/bfd/elf.c
+2-1contrib/binutils-2.27/bfd/elf.c
+6-33 files

LLVM/project 021672fllvm/test/Transforms/LowerTypeTests x86-jumptable.ll aarch64-jumptable.ll

[test][LowerTypeTests] Re-generate jump table tests with --check-globals (#192734)

Debug information will be updated in the
https://github.com/llvm/llvm-project/pull/192736,
so we want to track the difference.
DeltaFile
+74-9llvm/test/Transforms/LowerTypeTests/x86-jumptable.ll
+20-8llvm/test/Transforms/LowerTypeTests/aarch64-jumptable.ll
+94-172 files

LLVM/project e55bc19lldb/source/ValueObject DILEval.cpp

[lldb] Remove unused GetDynamicOrSyntheticValue (NFC) (#193111)
DeltaFile
+0-22lldb/source/ValueObject/DILEval.cpp
+0-221 files

LLVM/project 04f3d43llvm/lib/CodeGen InlineSpiller.cpp LiveRangeEdit.cpp, llvm/test/CodeGen/X86/apx foldmemory.mir

[X86][APX] Add assert isReserved if source operand is PhysReg (#192595)
DeltaFile
+112-0llvm/test/CodeGen/X86/apx/foldmemory.mir
+2-0llvm/lib/CodeGen/InlineSpiller.cpp
+2-0llvm/lib/CodeGen/LiveRangeEdit.cpp
+116-03 files

LLVM/project 89087c3llvm/test/CodeGen/RISCV/rvv vitofp-sdnode.ll vfptoi-sdnode.ll

rebase

Created using spr 1.3.7
DeltaFile
+878-428llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862-426llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+668-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
+619-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+4,183-87030 files not shown
+6,939-1,88436 files

LLVM/project 1d1ec7fllvm/test/CodeGen/RISCV/rvv vitofp-sdnode.ll vfptoi-sdnode.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+878-428llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862-426llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+668-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
+619-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+4,183-87030 files not shown
+6,939-1,88436 files

LLVM/project 6e63274llvm/test/CodeGen/RISCV/rvv vitofp-sdnode.ll vfptoi-sdnode.ll

rebase

Created using spr 1.3.7
DeltaFile
+878-428llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862-426llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+668-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
+619-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+4,183-87030 files not shown
+6,939-1,88436 files

LLVM/project 26ff57cllvm/test/CodeGen/RISCV/rvv vitofp-sdnode.ll vfptoi-sdnode.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+878-428llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862-426llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+668-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
+619-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+4,183-87030 files not shown
+6,939-1,88436 files

LLVM/project f0ab987llvm/test/CodeGen/RISCV/rvv vitofp-sdnode.ll vfptoi-sdnode.ll

rebase

Created using spr 1.3.7
DeltaFile
+878-428llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862-426llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+668-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
+619-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+4,183-87026 files not shown
+6,570-1,88232 files

LLVM/project 458e9c4llvm/lib/Target/Mips MipsDelaySlotFiller.cpp, llvm/test/CodeGen/Mips unalignedload.ll mips1-load-in-delay-slot.ll

Prevent undefined behavior caused by combination of branch and load delay slots on MIPS1 (#185427)

Under certain conditions the LLVM `MipsDelaySlotFiller` fills a branch
delay slot with an instruction requiring a load delay slot. However the
`MipsDelaySlotFiller` does not check the filled instruction for hazard
which leads to code like this:
```asm
        beqz    $1, $BB0_5
        lbu     $2, %lo(_RNvCs5jWYnRsDZoD_3app13CONTROLLERS_A)($2)
# --- Some other instructions
$BB0_5:
        andi    $1, $2, 1
```
`lbu` got moved into the branch delay slot but has a load delay slot -
so when jumping to `$BB0_5` the value for `$2` will not be ready, which
leads to undefined behavior.

This PR suggests to declare instructions with a load delay slot to be
hazardous for the branch delay slot, only for `MIPS1`. This will prevent

    [21 lines not shown]
DeltaFile
+221-84llvm/test/CodeGen/Mips/llvm-ir/load.ll
+225-35llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
+179-32llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+62-6llvm/test/CodeGen/Mips/unalignedload.ll
+61-0llvm/test/CodeGen/Mips/mips1-load-in-delay-slot.ll
+50-0llvm/test/CodeGen/Mips/gprestore.ll
+798-1571 files not shown
+800-1587 files

LLVM/project c7ed47dllvm/lib/CodeGen MachineBlockHashInfo.cpp, llvm/lib/Target/RISCV RISCVInstrInfoP.td

rebase

Created using spr 1.3.7
DeltaFile
+225-0llvm/test/CodeGen/RISCV/rv64p.ll
+135-0llvm/test/CodeGen/RISCV/rv32p.ll
+13-25llvm/lib/CodeGen/MachineBlockHashInfo.cpp
+5-1llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+378-264 files

LLVM/project f9b5aedclang/lib/CodeGen CGObjCMac.cpp, clang/test/CodeGenObjC objc2-constant-literals-ptrauth.m

[ObjC] Fix missing ptrauth signing of isa in constant ObjC literals (#191091)

154d2267b897 added support for emitting ObjC number, array, and
dictionary literals as constants, but did not sign the class pointer
fields in NSConstantIntegerNumber, NSConstantFloatNumber,
NSConstantDoubleNumber, NSConstantArray, and NSConstantDictionary
structs with the ObjCIsaPointers ptrauth schema on arm64e. Fix this by
using addSignedPointer instead of add when emitting those fields.

rdar://174359070
DeltaFile
+32-0clang/test/CodeGenObjC/objc2-constant-literals-ptrauth.m
+15-5clang/lib/CodeGen/CGObjCMac.cpp
+47-52 files

LLVM/project e08c1c5llvm/test/CodeGen/RISCV/rvv vitofp-sdnode.ll vfptoi-sdnode.ll

[RISCV][llvm] Support [s|u]int_to_fp and fp_to_[s|u]int for zvfbfa (#192287)
DeltaFile
+878-428llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862-426llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+369-109llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+201-73llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+114-2llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
+114-2llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
+2,538-1,0407 files not shown
+2,743-1,09413 files

LLVM/project 5fa31cbllvm/lib/Target/RISCV RISCVInstrInfoVSDPatterns.td RISCVInstrInfoVVLPatterns.td, llvm/test/CodeGen/RISCV/rvv vfwmacc-sdnode.ll fixed-vectors-vfwmacc.ll

[llvm][RISCV] Handle miscompile of widening fma in zvfbfa codegen (#192412)
DeltaFile
+40-40llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
+40-40llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
+14-10llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+3-2llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+97-924 files

LLVM/project 33c5aebllvm/test/CodeGen/RISCV/rvv fixed-vectors-vfwadd.ll fixed-vectors-vfwsub.ll

[RISCV][llvm] Support widening fadd, fsub and fmul codegen for zvfbfa (#192414)
DeltaFile
+668-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
+619-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+414-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
+326-4llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
+3,183-244 files not shown
+3,266-30110 files

LLVM/project acc3f73llvm/lib/Target/X86 X86InsertVZeroUpper.cpp X86VZeroUpper.cpp, llvm/test/CodeGen/X86 llc-pipeline-npm.ll

[NewPM] Port x86-insert-vzero-upper (#181597)

Had to move X86InsertVZeroUpper to its own file like in
https://github.com/llvm/llvm-project/pull/179864
No test coverage added for now as there are no MIR->MIR tests exercising
this pass and we do not have enough ported to run any end to end tests.

Redo of https://github.com/llvm/llvm-project/pull/180886
DeltaFile
+366-0llvm/lib/Target/X86/X86InsertVZeroUpper.cpp
+0-353llvm/lib/Target/X86/X86VZeroUpper.cpp
+6-1llvm/lib/Target/X86/X86.h
+4-0llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1-2llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+1-1llvm/lib/Target/X86/X86PassRegistry.def
+378-3572 files not shown
+380-3598 files

LLVM/project 890c3fcclang/lib/CodeGen CGObjCMac.cpp

[CodeGen] NFC: Fix and improve comments in CGObjCMac.cpp (#193119)

Extract comment changes from #191091.
DeltaFile
+37-31clang/lib/CodeGen/CGObjCMac.cpp
+37-311 files

LLVM/project 125fa54llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

rebase

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project d6c5a20llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project 2e1d160llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

rebase

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project 5585194llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project df4dd38llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

rebase

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project 3afda98llvm/lib/Target/RISCV RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rv64p.ll rv32p.ll

[RISCV][P-ext] Remateralize pli and plui (#193110)

Test cases were written by Claude Sonnet 4.5.
DeltaFile
+225-0llvm/test/CodeGen/RISCV/rv64p.ll
+135-0llvm/test/CodeGen/RISCV/rv32p.ll
+5-1llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+365-13 files

LLVM/project 4d2df3bllvm/utils/gn/secondary/llvm/lib/Target/AArch64 BUILD.gn

[gn] port c95a333de7108 (#193121)
DeltaFile
+4-1llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
+4-11 files

LLVM/project ad180declang/include/clang/AST ASTContext.h, clang/lib/AST ASTContext.cpp ItaniumMangle.cpp

[clang] implement CWG2064: ignore value dependence for decltype

The 'decltype' for a value-dependent (but non-type-dependent) should be known,
so this patch makes them non-opaque instead.

This patch also implements what's neceessary to allow overloading
on pure differences in instantiation dependence, making `std::void_t`
usable for SFINAE purposes.

This also readds a few test cases from da98651, which was a previous attempt
at resolving CWG2064.

Fixes #8740
Fixes #61818
Fixes #190388
DeltaFile
+906-175clang/lib/AST/ASTContext.cpp
+312-12clang/test/SemaTemplate/instantiation-dependence.cpp
+151-93clang/lib/AST/ItaniumMangle.cpp
+76-68clang/lib/AST/Type.cpp
+76-48clang/lib/Sema/SemaTemplate.cpp
+95-16clang/include/clang/AST/ASTContext.h
+1,616-41283 files not shown
+2,381-77789 files

NetBSD/src JRhn0GQexternal/bsd/jemalloc/dist/include/jemalloc/internal quantum.h, external/bsd/jemalloc/include/jemalloc/internal quantum.h

   Add missing archs
VersionDeltaFile
1.2+80-73external/bsd/jemalloc/dist/include/jemalloc/internal/quantum.h
1.6+7-2external/bsd/jemalloc/include/jemalloc/internal/quantum.h
+87-752 files

LLVM/project 0a5870dllvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge remote-tracking branch 'origin/main' into users/ziqingluo/PR-172429193-2-split-1

 Conflicts:
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.h
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevelFormat.h
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.h
        clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
        clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-03,037 files not shown
+986,155-65,8203,043 files

Linux/linux b4e0758kernel/trace .gitignore

tracing: tell git to ignore the generated 'undefsyms_base.c' file

This odd file was added to automatically figure out tool-generated
symbols.

Honestly, it *should* have been just a real honest-to-goodness regular
file in git, instead of having strange code to generate it in the
Makefile, but that is not how that silly thing works.  So now we need to
ignore it explicitly.

Fixes: 1211907ac0b5 ("tracing: Generate undef symbols allowlist for simple_ring_buffer")
Cc: Vincent Donnefort <vdonnefort at google.com>
Cc: Nathan Chancellor <nathan at kernel.org>
Cc: Steven Rostedt (Google) <rostedt at goodmis.org>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Marc Zyngier <maz at kernel.org>
Signed-off-by: Linus Torvalds <torvalds at linux-foundation.org>
DeltaFile
+1-0kernel/trace/.gitignore
+1-01 files

LLVM/project 1290b82clang/test/SemaCUDA float128.cu

[test] Remove redundant typedef (#193116)
DeltaFile
+0-1clang/test/SemaCUDA/float128.cu
+0-11 files

Linux/linux f154634tools/testing/selftests Makefile, tools/testing/selftests/kselftest runner.sh

Merge tag 'linux_kselftest-next-7.1-next-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest

Pull kselftest fixes from Shuah Khan:
 "Fix regressions in non-bash shells and busybox support, and revert a
  commit that regressed in build and installation when one or more tests
  fail to build.

  Fix duplicated test number reporting introduced in ktap support patch"

* tag 'linux_kselftest-next-7.1-next-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest:
  selftests: Fix duplicated test number reporting
  selftests: Fix runner.sh for non-bash shells
  selftests: Fix runner.sh busybox support
  selftests: Deescalate error reporting
DeltaFile
+24-25tools/testing/selftests/kselftest/runner.sh
+4-4tools/testing/selftests/Makefile
+28-292 files