LLVM/project 5f70043clang/docs ReleaseNotes.rst, clang/include/clang/Sema Initialization.h

[clang] Fix filler handling for new expression with unspecified bound. (#182203)

Array new with a runtime bound requires an "array filler" to initialize
elements which aren't explicitly initialized. Array new with an
unspecified bound doesn't need this; the array length is a compile-time
constant. Make sure SemaInit doesn't confuse the two cases.

Fixes #81157.
DeltaFile
+11-5clang/include/clang/Sema/Initialization.h
+16-0clang/test/SemaCXX/new-delete.cpp
+6-4clang/lib/Sema/SemaExprCXX.cpp
+1-0clang/docs/ReleaseNotes.rst
+34-94 files

LLVM/project b00e475llvm/test/Instrumentation/AddressSanitizer dynamic-shadow-windows.ll basic-msvc64.ll

Use preexisting test
DeltaFile
+0-20llvm/test/Instrumentation/AddressSanitizer/dynamic-shadow-windows.ll
+1-0llvm/test/Instrumentation/AddressSanitizer/basic-msvc64.ll
+1-202 files

LLVM/project bb1d53bllvm/lib/Target/RISCV RISCVInstrInfoP.td RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-ext-rv64.ll rvp-ext-rv32.ll

[RISCV][P-ext] Support vector ISD::ABS using PABD instructions. (#184822)
DeltaFile
+34-6llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+22-4llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+2-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+59-114 files

FreeBSD/ports 373b3edcad/iverilog Makefile distinfo

cad/iverilog: Update to 13.0
DeltaFile
+5-4cad/iverilog/Makefile
+3-3cad/iverilog/distinfo
+0-2cad/iverilog/pkg-plist
+8-93 files

LLVM/project bc8da0fllvm/lib/Target/Hexagon/MCTargetDesc HexagonAsmBackend.cpp, llvm/test/MC/Hexagon reloc-directive.s

[Hexagon] Support .reloc asm directive (#183849)

.reloc directive can be used in user assembly programs and created
internally by LLVM. In addition to Hexagon relocations, there are a few
generic names (BFD_RELOC_NONE, BFD_RELOC_8, BFD_RELOC_16,
and BFD_RELOC_32) that are mapped to Hexagon ones.
DeltaFile
+45-0llvm/test/MC/Hexagon/reloc-directive.s
+16-0llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+61-02 files

LLVM/project f305da7clang/lib/CIR/CodeGen CIRGenExprComplex.cpp, clang/test/CIR/CodeGen pack-indexing.cpp

[CIR] Implement PackIndexingExpr for ComplexType (#184878)

Implement the PackIndexingExpr for ComplexType
DeltaFile
+69-5clang/test/CIR/CodeGen/pack-indexing.cpp
+1-3clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
+70-82 files

LLVM/project dd155eallvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlan.h, llvm/test/Transforms/LoopVectorize vplan-based-stride-mv.ll

[VPlan] Implement VPlan-based stride speculation
DeltaFile
+986-1,148llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+289-160llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+248-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+43-0llvm/lib/Transforms/Vectorize/VPlan.h
+7-5llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+10-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1,583-1,3166 files not shown
+1,611-1,31912 files

LLVM/project 3fc27dclldb/source/DataFormatters FormatManager.cpp

[LLDB] Reformat comments
DeltaFile
+28-28lldb/source/DataFormatters/FormatManager.cpp
+28-281 files

LLVM/project 70509b5lldb/source/DataFormatters FormatManager.cpp, lldb/test/API/functionalities/data-formatter/synth_oneline_summaries TestSyntheticOneLineSummaries.py main.c

[LLDB] Allow one-line summaries in the presence of synthetic child providers (#184926)

This is driven by the Swift language. In Swift many data types such as
Int, and String are structs, and LLDB provides summary formatters and
synthetic child providers for them. For String, for example, a summary
formatter pulls out the string data from the implementation, while a
synthetic child provider hides the implementation details from users, so
strings don't expand their children.

rdar://171646109
DeltaFile
+21-0lldb/test/API/functionalities/data-formatter/synth_oneline_summaries/TestSyntheticOneLineSummaries.py
+16-0lldb/test/API/functionalities/data-formatter/synth_oneline_summaries/main.c
+12-0lldb/test/API/functionalities/data-formatter/synth_oneline_summaries/MyStringFormatter.py
+3-0lldb/test/API/functionalities/data-formatter/synth_oneline_summaries/Makefile
+1-1lldb/source/DataFormatters/FormatManager.cpp
+53-15 files

LLVM/project 56ea5c9llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Just use `vputils::onlyFirstLaneUsed`
DeltaFile
+1-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-71 files

LLVM/project d04ab32llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Use `reverse`/`IsaPred`
DeltaFile
+2-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-41 files

LLVM/project 69cb59fllvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h, llvm/test/Transforms/LoopVectorize pr37248.ll runtime-check-needed-but-empty.ll

[VPlan] Scalarize to first-lane-only directly on VPlan

This is needed to enable subsequent https://github.com/llvm/llvm-project/pull/182595.

I don't think we can fully port all scalarization logic from the legacy
path to VPlan-based right now because that would require us to introduce
interleave groups much earlier in VPlan pipeline, and without that we
can't really `assert` this new decision matches the previous CM-based
one. And without those `assert`s it's really hard to ensure we properly
port all the previous logic.

As such, I decided just to implement something much simpler that would
be enough for #182595. However, we perform this transformation before
delegating to the old CM-based decision, so it **is** effective
immediately and taking precedence even for consecutive loads/stores
right away.

Depends on https://github.com/llvm/llvm-project/pull/182592 but is stacked on
top of https://github.com/llvm/llvm-project/pull/182594 to enable linear
stacking for https://github.com/llvm/llvm-project/pull/182595.
DeltaFile
+65-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+6-0llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+2-2llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
+3-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1-1llvm/test/Transforms/LoopVectorize/pr37248.ll
+1-1llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
+78-41 files not shown
+79-47 files

LLVM/project dda7972llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h

Don't pass RecipeBuilder

Legacy calls `setRecipe` on all processed recipes but really queries `getRecipe`
for memory operations only, that we don't touch in the scalarization as that
happens after all memory recipes has been processed.
DeltaFile
+1-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-2llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-63 files

LLVM/project 7d48707lldb/source/Commands CommandObjectType.cpp

[lldb] Declare types of Python synthetic signatures (NFC) (#184914)

Similar to the changes in #182892

---------

Co-authored-by: Ebuka Ezike <yerimyah1 at gmail.com>
DeltaFile
+5-5lldb/source/Commands/CommandObjectType.cpp
+5-51 files

LLVM/project 5c15036llvm/test/Transforms/LoopVectorize vplan-based-stride-mv.ll, llvm/test/Transforms/LoopVectorize/VPlan vplan-based-stride-mv.ll

[NFC][VPlan] Add initial tests for future VPlan-based stride MV

I tried to include both the features that current
LoopAccessAnalysis-based transformation supports (e.g., trunc/sext of
stride) but also cases where the current implementation behaves poorly,
e.g., https://godbolt.org/z/h31c3zKxK; as well as some other potentially
interesting scenarios I could imagine.

The are two test files with the same content. One is for VPlan dump change of
the future transformation alone (I'll update `-vplan-print-after` in the next
PR), another is for the full vectorizer pipeline. The latter have two `RUN:`
lines:
 * No multiversioning, so the next PR diff can show the transformation itself
 * Stride multiversionin performed in LAA, so that we can compare future
   VPlan-based transformation vs old behavior.
DeltaFile
+4,730-0llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+3,421-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+8,151-02 files

LLVM/project d4efbf1clang/lib/AST ExprConstant.cpp, clang/test/CodeGen bitcast-based-lvalue.c

[Clang][ExprConst] Handle APValue::LValue in BitCast (#184865)

Instead of marking the branch unreachable, emit an unsupported type
diagnostic and return false when encountering `APValue::LValue` in
`APValueToBufferConverter`.

A good example of this is:
```
long fn() {
  return __builtin_bit_cast(long, (long)&fn);
}
```

Although `&fn` itself is a pointer type, the cast `(long)` converts it
to an integer type, which passes `checkBitCastConstexprEligibilityType`.
Thus, eventually, we see it in Converter, which does not expect an
LValue.

Fixes https://github.com/llvm/llvm-project/issues/44991
DeltaFile
+7-0clang/test/CodeGen/bitcast-based-lvalue.c
+1-3clang/lib/AST/ExprConstant.cpp
+8-32 files

LLVM/project 1a23e64mlir/test/IR test-symbol-uses.mlir, mlir/test/lib/IR TestSymbolUses.cpp

[mlir] Fix assertion crash in test-symbol-uses with nested modules (#185069)

The `SymbolUsesPass` walked all nested `SymbolOpInterface` ops in a
module, including those belonging to nested symbol tables (e.g., nested
modules). When an external `func.func` inside a nested module had no
uses in the outer module's body region, it was incorrectly added to
`deadFunctions` for erasure. Since the outer module's `SymbolTable` does
not contain the inner module's symbols, the subsequent
`table.lookup(name)` assertion would fail with:

Assertion `table.lookup(name) && "expected no unknown operations"`
failed.

Fix by only tracking functions that are direct children of the enclosing
module, skipping functions owned by nested symbol tables.

Fixes #60583

Assisted-by: Claude Code
DeltaFile
+12-0mlir/test/IR/test-symbol-uses.mlir
+6-1mlir/test/lib/IR/TestSymbolUses.cpp
+18-12 files

FreeNAS/freenas 964210esrc/middlewared/middlewared/plugins/pool_ dataset_encryption_info.py, src/middlewared/middlewared/plugins/zfs snapshot_hold_release_impl.py snapshot_rollback_impl.py

NAS-140090 / 27.0.0-BETA.1 / Don't need to instantiate `ZFSError` (#18391)

`ZFSError` is an `IntEnum`; its members can be treated like ints.
DeltaFile
+4-4src/middlewared/middlewared/plugins/zfs/snapshot_hold_release_impl.py
+3-3src/middlewared/middlewared/plugins/zfs/snapshot_rollback_impl.py
+2-2src/middlewared/middlewared/plugins/pool_/dataset_encryption_info.py
+2-2src/middlewared/middlewared/plugins/zfs/snapshot_query_impl.py
+1-1src/middlewared/middlewared/plugins/zfs/query_impl.py
+1-1src/middlewared/middlewared/plugins/zfs/utils.py
+13-131 files not shown
+14-147 files

LLVM/project 2c61992llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV clmul.ll

rebase

Created using spr 1.3.7
DeltaFile
+84,317-78,372llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+24,655-20,149llvm/test/CodeGen/RISCV/clmul.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+246,546-191,6526,300 files not shown
+769,708-462,7436,306 files

LLVM/project a8f0549llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV clmul.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+84,317-78,372llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+24,655-20,149llvm/test/CodeGen/RISCV/clmul.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+246,546-191,6526,300 files not shown
+769,708-462,7436,306 files

LLVM/project 80de1b7llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV clmul.ll

rebase

Created using spr 1.3.7
DeltaFile
+84,317-78,372llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+66,293-29,491llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+24,655-20,149llvm/test/CodeGen/RISCV/clmul.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+246,546-191,6526,300 files not shown
+769,708-462,7436,306 files

LLVM/project cba914cllvm/lib/Target/AArch64 AArch64Features.td, llvm/unittests/TargetParser TargetParserTest.cpp

[AArch64][llvm] Update Armv9.7-A dependencies (#185034)

Update Armv9.7-A dependenies:
  * `FeatureF16MM` to depend on `FeatureNEON`
  * `FeatureF16F32DOT` enabled by default for Armv9.7-A
DeltaFile
+4-3llvm/lib/Target/AArch64/AArch64Features.td
+3-0llvm/unittests/TargetParser/TargetParserTest.cpp
+7-32 files

LLVM/project e203da7clang/include/clang/Options Options.td, clang/lib/CodeGen CGCall.cpp

clang: Simplify emission of uniform-work-group-size attribute

This wasn't strictly using the LangOpt field for this property,
and hardcoding the OpenCL version. It was also going out of its
way to specifically annotate specific calling conventions. Just
unconditionally emit it on all functions. The uniform work group
assumption must hold in the entire module, not just the entrypoint.
This also theoretically saves work for the attributor propagation.

This will avoid the need to repeat the same logic in builtin function
codegen.
DeltaFile
+28-25clang/test/CodeGenCUDA/convergent.cu
+6-22clang/lib/CodeGen/CGCall.cpp
+9-9clang/test/CodeGenOpenCL/convergent.cl
+3-3clang/test/CodeGenHIP/default-attributes.hip
+2-2clang/test/CodeGenHIP/hip_weak_alias.cpp
+1-1clang/include/clang/Options/Options.td
+49-622 files not shown
+51-648 files

LLVM/project 832517flibcxx/include future, libcxx/include/__functional function.h

[libc++] Add alias template for __strip_signature::type (#181955)

Simplifying the internal implementation by providing a more concise
way to access the underlying type within the __strip_signature class.
DeltaFile
+3-0libcxx/include/__type_traits/strip_signature.h
+1-1libcxx/include/__functional/function.h
+1-1libcxx/include/future
+5-23 files

LLVM/project c5dff26llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h, llvm/test/Transforms/LoopVectorize/VPlan vplan-print-after-all.ll

[NFC][VPlan] Split `makeMemOpWideningDecisions` into subpasses

The idea is to have handling of strided memory operations (either from
https://github.com/llvm/llvm-project/pull/147297 or for VPlan-based
multiversioning for unit-strided accesses) done after some mandatory
processing has been performed (e.g., some types **must** be scalarized)
but before legacy CM's decision to widen (gather/scatter) or scalarize
has been committed.

And in longer term, we can uplift all other memory widening decision to
be done here directly at VPlan level. I expect this structure would also
be beneficial for that.
DeltaFile
+63-25llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+10-0llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+0-10llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
+76-354 files

LLVM/project 771dbc2llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPRecipeBuilder.h

Fold one `Legal` use into `tryToWidenHistogram` renamed to `widenIfHistogram`
DeltaFile
+10-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+6-6llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+3-5llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+19-133 files

LLVM/project 016715allvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanTransforms.cpp

Move to VPlanTransforms, have to pass Legal explicitly
DeltaFile
+1-78llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+76-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+3-1llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+80-793 files

LLVM/project d21e4ccllvm/lib/Transforms/Vectorize VPlanTransforms.cpp LoopVectorize.cpp

Move another `Legal` use to `VPRecipeBuilder::replaceWithFinalIfReductionStore`
DeltaFile
+10-21llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+21-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+8-0llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+1-3llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+40-254 files

LLVM/project 050a33dllvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Braces for outer `if`
DeltaFile
+2-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-11 files

LLVM/project c07a1dbllvm/lib/Transforms/Vectorize LoopVectorize.cpp

Don't make unnecessary captures
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1-11 files