LLVM/project c48be31libcxx/include/__algorithm ranges_swap_ranges.h swap_ranges.h

[libc++] Forward calls to ranges::swap_ranges to the 3-leg implementation if possible (#176762)

This allows us to make use of any optimizations to `std::swap_ranges` in
`ranges::swap_ranges`.

This patch also moves some code specific to `ranges::swap_ranges` into
`ranges_swap_ranges.h`.
DeltaFile
+30-3libcxx/include/__algorithm/ranges_swap_ranges.h
+0-27libcxx/include/__algorithm/swap_ranges.h
+30-302 files

LLVM/project e2e50f6llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp

[Review] Compute which functions reach which globals only once
DeltaFile
+82-26llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+82-261 files

FreeBSD/src eda3cd3share/man/man4 vt.4

vt.4: Document that hw.vga.textmode does not apply for UEFI(8) boot

PR:             292598
Approved by:    ziaee, imp
MFC after:      3 days
Differential Revision:  https://reviews.freebsd.org/D54842

(cherry picked from commit 28764001b504c3588fd9f8dd6e4c08144d20571c)
DeltaFile
+5-1share/man/man4/vt.4
+5-11 files

FreeBSD/ports 2b0cca6sysutils Makefile, sysutils/py-ansible-core220 Makefile pkg-descr

sysutils/py-ansible-core220: Add new port

Ansible-core 2.20.1 brings in new features and bugfixes. It will not
work with our default python311. Until Python 3.12 becomes default,
to build this port add DEFAULT_VERSIONS+=python=3.12 to make.conf
and rebuild all python packages needed to build this port prior to
building and installing this port.
DeltaFile
+95-0sysutils/py-ansible-core220/Makefile
+9-0sysutils/py-ansible-core220/files/patch-pyproject.toml
+5-0sysutils/py-ansible-core220/pkg-descr
+3-0sysutils/py-ansible-core220/distinfo
+1-0sysutils/Makefile
+113-05 files

FreeBSD/src 051d781share/man/man4 vt.4

vt.4: Document that hw.vga.textmode does not apply for UEFI(8) boot

PR:             292598
Approved by:    ziaee, imp
MFC after:      3 days
Differential Revision:  https://reviews.freebsd.org/D54842

(cherry picked from commit 28764001b504c3588fd9f8dd6e4c08144d20571c)
DeltaFile
+5-1share/man/man4/vt.4
+5-11 files

LLVM/project 28d621eflang/lib/Lower Bridge.cpp PFTBuilder.cpp, flang/test/Lower do-while-to-scf-while.f90

[flang] Lowering fortran structured do-while loops to `scf.while` (#177476)

WIP. Implemented structured do-while loops (i.e., the only control-flow
edge that can leave the outer loop is the one taken when the DO WHILE
condition becomes false) lowering to `scf.while`.
DeltaFile
+87-0flang/test/Lower/do-while-to-scf-while.f90
+54-0flang/lib/Lower/Bridge.cpp
+8-1flang/lib/Lower/PFTBuilder.cpp
+149-13 files

FreeBSD/src 4d36d18share/man/man4 vt.4

vt.4: Document that hw.vga.textmode does not apply for UEFI(8) boot

PR:             292598
Approved by:    ziaee, imp
MFC after:      3 days
Differential Revision:  https://reviews.freebsd.org/D54842

(cherry picked from commit 28764001b504c3588fd9f8dd6e4c08144d20571c)
DeltaFile
+5-1share/man/man4/vt.4
+5-11 files

NetBSD/pkgsrc-wip ad35b4bups-nut distinfo

ups-nut: fix distinfo
DeltaFile
+3-3ups-nut/distinfo
+3-31 files

LLVM/project f32c00fllvm/include/llvm/CodeGen LiveRegMatrix.h LiveIntervalUnion.h, llvm/lib/CodeGen LiveRegMatrix.cpp InlineSpiller.cpp

[regalloc][LiveRegMatrix][AMDGPU] Fix LiveInterval dangling pointers in LiveRegMatrix. (#168556)

This patch correctly removes segments from LiveRegMatrix that reference LiveIntervals removed after spilling. Added validity check that LiveRegMatrix doesn't contain invalid references to intervals.
DeltaFile
+45-7llvm/lib/CodeGen/LiveRegMatrix.cpp
+16-3llvm/lib/CodeGen/InlineSpiller.cpp
+14-1llvm/include/llvm/CodeGen/LiveRegMatrix.h
+13-0llvm/lib/CodeGen/LiveIntervalUnion.cpp
+4-2llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+5-0llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+97-131 files not shown
+101-137 files

LLVM/project e7063e8mlir/include/mlir/IR CommonTypeConstraints.td, mlir/test/Dialect/SPIRV/IR non-uniform-ops.mlir composite-ops.mlir

[mlir][spirv] Enforce `SPIRV_Vector` to have rank of one (#178185)

Currently only vector length is enforced however this allows vectors of
rank >1 to pass the verification as long as the length agrees. This
change restricts `SPIRV_Vector`s to be of rank 1 as required by the
SPIR-V spec.

This also fixes a bug where `SPIRV_Composite` allowed high ranked
vectors but `spirv::CompositeType` did not leading to cast assertions
where the composite type was assumed.

Finally, this change adds two new common constraints that can enforce
all three: rank, length and type.

fixes #178127
DeltaFile
+22-0mlir/include/mlir/IR/CommonTypeConstraints.td
+10-10mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
+8-0mlir/test/Dialect/SPIRV/IR/composite-ops.mlir
+3-3mlir/test/Dialect/SPIRV/IR/group-ops.mlir
+3-3mlir/test/Dialect/SPIRV/IR/image-ops.mlir
+3-3mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir
+49-194 files not shown
+57-2710 files

LLVM/project 3d07cc3llvm/test/CodeGen/RISCV/rvv vfmadd-sdnode.ll vfwmacc-sdnode.ll

[RISCV] Reorder some check-prefixes in a way that makes the update script work. NFC (#178120)

Prior to this, the update_llc_test_checks script would generate ZVFBFA
and ZVFBFWMA checks that were already included in ZVFHMIN.
DeltaFile
+6-6llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
+4-4llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
+10-102 files

FreeBSD/ports 2be9507games/flightgear-aircraft distinfo Makefile

games/flightgear-aircraft: Update to 20260126
DeltaFile
+42-42games/flightgear-aircraft/distinfo
+1-1games/flightgear-aircraft/Makefile
+43-432 files

FreeNAS/freenas a2816fesrc/freenas/etc/systemd/system sssd-pam-priv.socket sssd-pam.socket, src/middlewared/middlewared/etc_files/sssd sssd.conf.mako

disable sockets
DeltaFile
+2-0src/middlewared/middlewared/etc_files/sssd/sssd.conf.mako
+1-0src/freenas/etc/systemd/system/sssd-pam-priv.socket
+1-0src/freenas/etc/systemd/system/sssd-pam.socket
+1-0src/freenas/etc/systemd/system/sssd-nss.socket
+5-04 files

LLVM/project 0a53a55llvm/test/CodeGen/RISCV/rvv emergency-slot.mir

[RISCV] Remove 'implicit $vl' from PseudoVMV_X_S in emergency-slot.mir. NFC (#178015)

This instruction doesn't use VL and the pseudo doesn't have a VL
operand. According to VSETVLIInserter tests, this instruction only gets
implicit $vtype added to it.
DeltaFile
+2-2llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
+2-21 files

FreeBSD/ports e0b0b8edevel/simgear distinfo Makefile, games/flightgear distinfo Makefile

games/flightgear: Update to 2024.1.4
DeltaFile
+3-3games/flightgear-data/distinfo
+3-3devel/simgear/distinfo
+3-3games/flightgear/distinfo
+1-3devel/simgear/Makefile
+1-3games/flightgear/Makefile
+1-1games/flightgear-data/Makefile
+12-161 files not shown
+13-167 files

OPNSense/core cdbc597src/opnsense/scripts/filter list_legacy_rules.php

Normalize overload from name to uuid in list_legacy_rules
DeltaFile
+9-0src/opnsense/scripts/filter/list_legacy_rules.php
+9-01 files

LLVM/project f0bf972mlir/lib/Dialect/MemRef/Transforms MultiBuffer.cpp, mlir/test/Dialect/MemRef multibuffer.mlir

[MemRef] Propagate strided layout through view-like ops in multiBuffer (#176941)

The memref::multiBuffer transformation replaces an allocation with a
multi-buffered allocation and creates a strided memref.subview at each
loop iteration. When the original allocation is used through view-like
ops, the existing code only handles SubViewOp, leaving other view-like
ops with incorrect types.

This patch extends replaceUsesAndPropagateType to handle ExpandShapeOp,
CollapseShapeOp, and CastOp using TypeSwitch. For each view-like op, we
compute the correct result type (or assert on failure) and create a new
operation, then recursively propagate the updated type through chains.
New FileCheck tests cover expand_shape, collapse_shape, cast, and a
chained expand_shape->cast case.

A single ViewLikeOpInterface hook is not practical here: view-like ops
have distinct type inference and validity rules (e.g., subview uses
offset/size/stride inference, expand/collapse use reassociation, cast
requires compatibility checks). Ops like memref.view or

    [2 lines not shown]
DeltaFile
+120-0mlir/test/Dialect/MemRef/multibuffer.mlir
+90-27mlir/lib/Dialect/MemRef/Transforms/MultiBuffer.cpp
+210-272 files

FreeBSD/src a265c8bsys/netinet ip_mroute.c ip_mroute.h

ip_mroute: Convert to using a regular mutex

The multicast routing code was using spin mutexes for packet counting,
but there is no reason to use them instead of regular mutexes, given
that none of this code runs in an interrupt context.  Convert to using
default mutexes.

Reviewed by:    glebius
MFC after:      2 weeks
Sponsored by:   Stormshield
Sponsored by:   Klara, Inc.
Differential Revision:  https://reviews.freebsd.org/D54603
DeltaFile
+18-17sys/netinet/ip_mroute.c
+5-5sys/netinet/ip_mroute.h
+23-222 files

FreeBSD/src ef389b7tests/atf_python atf_pytest.py

atf_python: Fix a typo in a type annotation

No functional change intended.

MFC after:      1 week
Sponsored by:   Stormshield
Sponsored by:   Klara, Inc.
DeltaFile
+1-1tests/atf_python/atf_pytest.py
+1-11 files

FreeBSD/src 0f1e135sys/netinet ip_mroute.c

ip_mroute: EVENTHANDLER_REGISTER does not fail

No functional change intended.

MFC after:      1 week
Sponsored by:   Stormshield
Sponsored by:   Klara, Inc.
DeltaFile
+0-6sys/netinet/ip_mroute.c
+0-61 files

FreeNAS/freenas 8ccae17src/middlewared/middlewared/plugins/failover_ disabled_reasons.py enums.py, src/middlewared/middlewared/plugins/security update.py

NAS-139409 / 26.0.0-BETA.1 / Fix reboot reasons for HA (by Qubad786) (#18090)

## Problem

There were different problems identified with reboot reasons management
with HA:

1. We were setting reboot reason after rebooting remote node in case an
exception happened which meant that the remote would have to be rebooted
again because we would have stored it's boot_id as none at that point.
2. For any reboot reason, we always set disabled reasons as FIPS which
is wrong and we should show actual reason HA is being shown as disabled
3. Active node's reboot reason was added after remote had rebooted which
is not nice
4. We did not set appropriate reboot reason for FIPS/STIG if both were
toggled and only FIPS got added

## Solution


    [14 lines not shown]
DeltaFile
+53-34src/middlewared/middlewared/plugins/security/update.py
+8-7src/middlewared/middlewared/plugins/failover_/disabled_reasons.py
+4-0src/middlewared/middlewared/plugins/failover_/enums.py
+2-0src/middlewared/middlewared/plugins/failover_/reboot.py
+1-0src/middlewared/middlewared/plugins/system/reboot.py
+68-415 files

LLVM/project caa67f5clang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

Handle non-trivial view types of temporaries
DeltaFile
+22-75clang/test/Sema/warn-lifetime-safety.cpp
+10-7clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+1-0clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+33-823 files

LLVM/project 21b0fdfflang/lib/Lower/OpenMP OpenMP.cpp, flang/test/Lower/OpenMP defaultmap.f90

[Flan][OpenMP] Implement TODO support for compatible defaultmap types for implicit mappers (#177389)

Make implicit default mapper generation respect defaultmap categories so
unrelated defaultmap clauses no longer suppress mappers for derived
types.
Added related tests.
DeltaFile
+49-0offload/test/offloading/fortran/target-defaultmap-implicit-mapper.f90
+22-0flang/test/Lower/OpenMP/defaultmap.f90
+3-4flang/lib/Lower/OpenMP/OpenMP.cpp
+74-43 files

LLVM/project c41691cllvm/lib/Target/PowerPC PPCInstrInfo.cpp PPCMIPeephole.cpp, llvm/test/CodeGen/PowerPC peephole-livevars-tracking.mir

[PowerPC] Fix XXPERMDI peephole and ISEL LiveVariables bugs (#172122)

Fixes https://github.com/llvm/llvm-project/issues/159116
Prevent XXPERMDI splat optimization when the splat output register is
used in other instructions, which caused undefined register references. 
Also track removed ISEL operands in simplifyToLI to prevent 
LiveVariables corruption during ISEL-to-COPY conversion.
DeltaFile
+83-0llvm/test/CodeGen/PowerPC/peephole-livevars-tracking.mir
+9-2llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+6-1llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+2-1llvm/lib/Target/PowerPC/PPCInstrInfo.h
+100-44 files

LLVM/project cdb1948utils/bazel/llvm-project-overlay/libc BUILD.bazel

[bazel] Fix Bazel build for 90829e51 (#178210)

DeltaFile
+8-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+8-01 files

LLVM/project a73bdbaflang/lib/Semantics check-omp-loop.cpp openmp-modifiers.cpp, flang/test/Semantics/OpenMP linear-clause03.f90 clause-validity01.f90

[flang][OpenMP] Update semantic checks for LINEAR clause (#177055)

Fixes https://github.com/llvm/llvm-project/issues/173980.

In particular, make step-simple-modifier be compatible (i.e. not
exclusive) for OpenMP spec versions < 52, and update the modifier
validity checks for the construct on which the clause is located.
DeltaFile
+45-37flang/lib/Semantics/check-omp-loop.cpp
+23-0flang/test/Semantics/OpenMP/linear-clause03.f90
+4-3flang/test/Semantics/OpenMP/clause-validity01.f90
+2-1flang/lib/Semantics/openmp-modifiers.cpp
+74-414 files

FreeBSD/src 18d1e67sys/arm64/broadcom/genet if_genet.c

genet: Add a detach routine

PR:             288309
Co-authored by: Mike Belanger <mibelanger at qnx.com>
MFC after:      2 weeks

(cherry picked from commit 96a550e9dd892f24a479da00ead93fbfaafb7733)
DeltaFile
+35-0sys/arm64/broadcom/genet/if_genet.c
+35-01 files

LLVM/project 48565d9mlir/include/mlir/Analysis/DataFlow SparseAnalysis.h IntegerRangeAnalysis.h, mlir/lib/Analysis/DataFlow SparseAnalysis.cpp IntegerRangeAnalysis.cpp

[mlir][dataflow] Drop the firstIndex argument of visitNonControlFlowArguments (#175210)

This PR improves the signature of `visitNonControlFlowArguments`:
- The function now takes non-successor-inputs ("non-control-flow
arguments") instead of successor inputs. This is more consistent with
the naming of the function.
- `firstIndex` is no longer needed and dropped. (It was needed only to
identify the non-successor-inputs among the block arguments / op
results.)

Background: Successor inputs are forwarded values (e.g., iter_args / op
results of an `scf.for`) and non-successor-inputs are all other block
arguments / op results (e.g., the loop induction variable of an
`scf.for`.)

Note for LLVM integration: `visitNonControlFlowArguments` now receives
the non-successor-input directly. You no longer have to find those among
the list of all block arguments / op results based on `firstIndex`.

RFC:
https://discourse.llvm.org/t/rfc-drop-the-firstindex-argument-of-visitnoncontrolflowarguments-of-sparseforwarddataflowanalysis/89419/5
DeltaFile
+19-21mlir/include/mlir/Analysis/DataFlow/SparseAnalysis.h
+19-12mlir/lib/Analysis/DataFlow/SparseAnalysis.cpp
+12-5mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
+4-5mlir/include/mlir/Analysis/DataFlow/IntegerRangeAnalysis.h
+54-434 files

NetBSD/pkgsrc xDiwLBydoc CHANGES-2026

   doc: Updated security/acmesh to 3.1.2
VersionDeltaFile
1.682+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc vnROwcesecurity/acmesh PLIST distinfo

   security/acmesh: Update to 3.1.2

   Changelog:
   3.1.2:
    1. support cert profile and ip cert.
    2. a lot of bug fixes.
VersionDeltaFile
1.10+12-0security/acmesh/PLIST
1.19+4-4security/acmesh/distinfo
1.19+2-2security/acmesh/Makefile
+18-63 files