LLVM/project 7a0adcfclang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp, clang/test/CIR/CodeGenCUDA device-stub.cu

fix tests and remove unnecessary comments.
DeltaFile
+0-3clang/test/CIR/CodeGenCUDA/device-stub.cu
+0-1clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+0-42 files

FreeBSD/ports ae414d7multimedia/pipe-viewer distinfo Makefile

multimedia/pipe-viewer: Update to 0.5.7

ChangeLog: https://github.com/trizen/pipe-viewer/blob/0.5.7/Changes
DeltaFile
+3-3multimedia/pipe-viewer/distinfo
+1-1multimedia/pipe-viewer/Makefile
+4-42 files

FreeBSD/ports 5d5e50bgraphics/vhs distinfo Makefile

graphics/vhs: Update to 0.11.0

ChangeLog: https://github.com/charmbracelet/vhs/releases/tag/v0.11.0
DeltaFile
+5-5graphics/vhs/distinfo
+2-3graphics/vhs/Makefile
+7-82 files

LLVM/project 08070b7flang/include/flang/Evaluate tools.h, flang/lib/Evaluate tools.cpp

[flang][cuda] Do not check for implicit transfer on managed symbols (#188143)

Avoid to trigger a semantic error when only managed symbols are on the
right hand side.
DeltaFile
+17-0flang/test/Lower/CUDA/cuda-data-transfer-implicit.cuf
+11-1flang/lib/Evaluate/tools.cpp
+1-4flang/test/Lower/CUDA/cuda-managed.cuf
+1-3flang/test/Lower/CUDA/cuda-data-transfer.cuf
+2-1flang/lib/Semantics/check-cuda.cpp
+3-0flang/include/flang/Evaluate/tools.h
+35-96 files

HardenedBSD/ports 6256b43devel/RStudio Makefile, mail/mailpit/files patch-package-lock.json

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+0-563misc/ggml/files/patch-19504
+200-200mail/mailpit/files/patch-package-lock.json
+38-24misc/github-copilot-language-server/files/package-lock.json
+22-24math/freefem++/Makefile
+13-12misc/github-copilot-language-server/files/package-lock-kerberos.json
+11-10devel/RStudio/Makefile
+284-83322 files not shown
+359-90828 files

NetBSD/pkgsrc-wip 549718abasu distinfo Makefile, libscfg distinfo Makefile

basu, libscfg, wlrctl: use DIST_SUBDIR
DeltaFile
+3-3libscfg/distinfo
+3-3basu/distinfo
+3-3wlrctl/distinfo
+2-1libscfg/Makefile
+1-0basu/Makefile
+1-0wlrctl/Makefile
+13-106 files

NetBSD/src MzOk4lisys/uvm uvm_swap.c

   sw_reg_strategy: stop panicking on hole

   after the recent change to uvm_aio_aiodone_pages,
   it should be ok to report errors here. the swap slots
   will be marked bad as expected.

   tested with a swap file with 50% holes:
   ```
   Device                    Size     Used      Bad    Avail Capacity  Priority
   /dev/dk1                  2.0G     1.8G       0B     190M     91%      0
   /swapfile_with_half_holes 2.0G     2.0G     1.0G     5.6M    100%      0
   Total                     4.0G     3.8G     1.0G     196M     95%
   ```
VersionDeltaFile
1.219+0-10sys/uvm/uvm_swap.c
+0-101 files

NetBSD/src rOpo2U3sys/compat/common uvm_110.c

   swapctl: report npgbad (cont.)

   i forgot to this file while porting the patch from
   my local git repo to cvs.
VersionDeltaFile
1.1+74-0sys/compat/common/uvm_110.c
+74-01 files

NetBSD/src 6jaDOCisys/uvm uvm_pager.c

   uvm_aio_aiodone_pages: do not discard user data on swap out failure

   if swap out i/o failed, maybe the swap device is broken. it's
   reasonable to mark it bad. however, there is no point to discard
   the user data on the page being swapped out. unlike file pages,
   the association to the particular swap slot is not permanent.
   next time the page is picked as a victim by the page daemon, a
   different swap slot, which is hopefully good, will be allocated.
VersionDeltaFile
1.133+17-10sys/uvm/uvm_pager.c
+17-101 files

LLVM/project 8232460clang/include/clang/CIR MissingFeatures.h, clang/include/clang/CIR/Dialect/IR CIRCUDAAttrs.td CIRDialect.td

[CIR][CUDA] Global emission for fatbin symbols
DeltaFile
+154-0clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+50-0clang/test/CIR/CodeGenCUDA/device-stub.cu
+17-0clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
+10-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-0clang/include/clang/CIR/MissingFeatures.h
+1-0clang/include/clang/CIR/Dialect/IR/CIRDialect.td
+234-06 files

NetBSD/src X4SzJC5sbin/swapctl swaplist.c

   swapctl: print npgbad

   eg.
   ```
   Device                    Size     Used      Bad    Avail Capacity  Priority
   /dev/dk1                  2.0G     1.8G       0B     190M     91%      0
   /swapfile_with_half_holes 2.0G     2.0G     1.0G     5.6M    100%      0
   Total                     4.0G     3.8G     1.0G     196M     95%
   ```
VersionDeltaFile
1.24+30-15sbin/swapctl/swaplist.c
+30-151 files

NetBSD/src xnKriXlsys/compat/common compat_110_mod.c compat_mod.h, sys/compat/sys uvm.h

   swapctl: report npgbad

   the current layout of swapent is like the following on amd64:
   ```
   (gdb) ptype /o struct swapent
   /* offset    |  size */  type = struct swapent {
   /*    0      |     8 */    dev_t se_dev;
   /*    8      |     4 */    int se_flags;
   /*   12      |     4 */    int se_nblks;
   /*   16      |     4 */    int se_inuse;
   /*   20      |     4 */    int se_priority;
   /*   24      |  1025 */    char se_path[1025];
   /* XXX  7-byte padding  */

                              /* total size (bytes): 1056 */
                            }
   ```
   while it's tempting to use the padding for the new member
   to avoid versioning, i guess we can't because, on some
   architectures, 64-bit value only has 32-bit alignment. (eg. i386)
VersionDeltaFile
1.3+19-1sys/compat/sys/uvm.h
1.10+8-2sys/sys/swap.h
1.10+4-2sys/uvm/uvm_swapstub.c
1.3+4-2sys/compat/common/compat_110_mod.c
1.218+6-0sys/uvm/uvm_swap.c
1.13+3-1sys/compat/common/compat_mod.h
+44-82 files not shown
+48-118 files

NetBSD/src 5GBoumpexternal/cddl/osnet/sys/sys vnode.h

   zfs: fix "slow rm" issue (cont.)

   commit a change which was lost during a porting from
   my local git repo to cvs.
   fortunately, it was harmless to miss this change though.
VersionDeltaFile
1.23+0-1external/cddl/osnet/sys/sys/vnode.h
+0-11 files

LLVM/project 035bb3bclang/include/clang/CIR MissingFeatures.h, clang/include/clang/CIR/Dialect/IR CIRCUDAAttrs.td CIRDialect.td

[CIR][CUDA] Global emission for fatbin symbols
DeltaFile
+157-0clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+50-0clang/test/CIR/CodeGenCUDA/device-stub.cu
+17-0clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
+10-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-0clang/include/clang/CIR/MissingFeatures.h
+1-0clang/include/clang/CIR/Dialect/IR/CIRDialect.td
+237-06 files

FreeBSD/ports d8dfedddevel/RStudio distinfo.desktop Makefile

devel/RStudio: Improve Makefile by adding ELECTRON_VERSION variable

This port was a bit fragile, but it builds and works fine when
electron37 is available. (electron37 is currently broken).
DeltaFile
+0-21devel/RStudio/distinfo.desktop
+11-10devel/RStudio/Makefile
+11-312 files

HardenedBSD/ports d8dfedddevel/RStudio Makefile distinfo.desktop

devel/RStudio: Improve Makefile by adding ELECTRON_VERSION variable

This port was a bit fragile, but it builds and works fine when
electron37 is available. (electron37 is currently broken).
DeltaFile
+11-10devel/RStudio/Makefile
+0-21devel/RStudio/distinfo.desktop
+11-312 files

OpenBSD/ports lhTh7Xzaudio/gmpc Makefile

   Drop COMPILER lines now that devel/libnotify caters for base-gcc

   The recent COMPILER addition in those ports was only because of
   a base-gcc limitation exposed by a devel/libinotify header. Now that the
   affected header has been fixed, tb and kmos prefer to revert the
   COMPILER additions.
VersionDeltaFile
1.79+1-4audio/gmpc/Makefile
+1-41 files

LLVM/project 16578d5clang/include/clang/Basic arm_sve.td, clang/lib/Sema SemaARM.cpp

fixup! Address more PR comments
DeltaFile
+3-20clang/lib/Sema/SemaARM.cpp
+0-9clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_target_lane.c
+4-1clang/include/clang/Basic/arm_sve.td
+1-1clang/test/Sema/aarch64-sme2p3-intrinsics/acle_sme2p3_target_lane.c
+8-314 files

LLVM/project 0f9b741libclc/clc/lib/generic/conversion clc_convert_float.inc clc_convert_float2float.cl

libclc: Fix -cl-denorms-are-zero for rtp and rtn conversions
DeltaFile
+12-0libclc/clc/lib/generic/conversion/clc_convert_float.inc
+1-0libclc/clc/lib/generic/conversion/clc_convert_float2float.cl
+13-02 files

LLVM/project b26bf06clang/include/clang/Basic arm_sve.td, clang/test/CodeGen/AArch64/sve2p3-intrinsics acle_sve2p3_luti6.c

fixup! Fix final PR comments for now
DeltaFile
+118-8clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
+5-0llvm/lib/Target/AArch64/SVEInstrFormats.td
+1-1clang/include/clang/Basic/arm_sve.td
+1-0llvm/test/Verifier/AArch64/luti6-intrinsics.ll
+125-94 files

LLVM/project 3755a55llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h

Claude Code review

Change-Id: Id4983ca59270c8bb2d261d38a6e7f2483c9d237e
DeltaFile
+15-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+2-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+17-22 files

LLVM/project a08c141llvm/lib/CodeGen/GlobalISel CombinerHelper.cpp, llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[AMDGPU][DAGCombiner][GlobalISel] Extend allMulUsesCanBeContracted with FMA/FMAD pattern

Add conservative FMA/FMAD recognition to allMulUsesCanBeContracted:
a multiply used by an existing FMA/FMAD is assumed to be contractable
(it's already being contracted elsewhere). This avoids unnecessary
contraction blocking for multiplies that feed into FMA chains.

Also adds FMA/FMAD to the FPEXT user set (fpext(fmul) --> fma is
recognized as contractable when isFPExtFoldable).

Guards all remaining FMA-chain reassociation fold sites in both
SDAG (visitFADDForFMACombine/visitFSUBForFMACombine, 8 sites) and
GISel (matchCombineFAddFpExtFMulToFMadOrFMAAggressive, 4 sites).

This re-enables contractions that were conservatively blocked in
earlier patches where the multiply had an FMA use that wasn't yet
recognized: dagcombine-fma-crash.ll and dagcombine-fma-fmad.ll
CHECK lines revert to upstream behavior.

Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
DeltaFile
+95-96llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
+20-3llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+10-12llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
+17-2llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+142-1134 files

LLVM/project 56494b4llvm/include/llvm/CodeGen/GlobalISel CombinerHelper.h, llvm/lib/CodeGen/GlobalISel CombinerHelper.cpp

[AMDGPU][DAGCombiner][GlobalISel] Extend allMulUsesCanBeContracted with FPEXT pattern

Extend the allMulUsesCanBeContracted analysis to recognize FPEXT patterns
where the multiply result flows through fpext before being used in
contractable operations (fadd, fsub). This covers:
  - fmul --> fpext --> {fadd, fsub}: FPEXT folds if isFPExtFoldable
  - fmul --> fpext --> fneg --> fsub: FPEXT then FNEG to FSUB
  - fmul --> fneg --> fpext --> fsub: FNEG then FPEXT folds if foldable

Also adds allMulUsesCanBeContracted guards to all FPEXT fold sites in
both SDAG (visitFADDForFMACombine, visitFSUBForFMACombine) and GISel
(matchCombineFAddFpExtFMulToFMadOrFMA, matchCombineFSubFpExtFMulToFMadOrFMA,
matchCombineFSubFpExtFNegFMulToFMadOrFMA).

Fixes a missing isFPExtFoldable check in GISel's
matchCombineFSubFpExtFMulToFMadOrFMA which could fold without verifying
the extension is actually foldable.

Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
DeltaFile
+1,930-11llvm/test/CodeGen/AMDGPU/fma-multiple-uses-contraction.ll
+93-14llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+78-13llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+2-1llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+2,103-394 files

LLVM/project 3ef446allvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i64-stride-7.ll vector-interleaved-load-i8-stride-8.ll

Merge branch 'main' into users/bassiounix/upstream/perfect-hash
DeltaFile
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+5,208-5,214llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+3,046-3,042llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+2,034-2,026llvm/test/CodeGen/X86/clmul-vector.ll
+2,034-1,998llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+1,890-1,901llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
+21,047-20,979699 files not shown
+57,536-32,078705 files

LLVM/project 192d488llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Merge conflicts

Change-Id: I33564a1e5d14f3b53577cb463ba2cb3a7993fd24
DeltaFile
+50-57llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+54-602 files

LLVM/project bf75318llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Typo

Change-Id: I8b8da8a07be84506483f474d0a5e10ad79178c15
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+1-11 files

LLVM/project 78c263allvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

[AMDGPU] Add stalls for DS FIFO buffer

Change-Id: I73e56da97a931349e0655e4e20b24aeb97920647
DeltaFile
+61-54llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+41-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+41-5llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+143-653 files

NetBSD/pkgsrc-wip b4cc592basu distinfo Makefile

Revert "basu: switch to browser download filename"

This reverts commit d443f9931389e43df4e796c62d42e16318d3d6f2.

sr.ht download works again
DeltaFile
+3-3basu/distinfo
+2-0basu/Makefile
+5-32 files

LLVM/project 7f565d7llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h

Fix naming

Change-Id: Ic1b5d1c2729a20ef9810ef92f11d870ce5fa3d96
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+5-52 files

LLVM/project de818dcllvm/lib/Analysis LoopAccessAnalysis.cpp, llvm/test/Analysis/LoopAccessAnalysis single_strided_readwrite.ll

[LAA] Speculate `stride != 0` for single read-write access

Stacked on top of https://github.com/llvm/llvm-project/pull/186262.
DeltaFile
+4-12llvm/test/Analysis/LoopAccessAnalysis/single_strided_readwrite.ll
+7-1llvm/lib/Analysis/LoopAccessAnalysis.cpp
+11-132 files