[ValueTracking][NFC] Check whether assume and context in isValidAssumeForContext are equal first (#242796)
This check is really cheap, so we should do it at the start.
[AArch64][GlobalISel] Require asserts in direct-hasoneuse-postlegalizer-debug.mir (#242794)
The test selects combiner rules by name with
`-aarch64postlegalizercombiner-only-enable-rule`. Rule names are only
recognized in builds with assertions, so builders without them fail with
"Invalid rule identifier", for example
https://lab.llvm.org/buildbot/#/builders/11/builds/53689.
Fixes a test failure introduced by #237644.
net-p2p/gtk-gnutella: unbreak the build on 32-bit architectures
Turns out this version suffers from the same issue as 1.2.1 I have
fixed before; reapply lost part of commit 9a32701b738f as a remedy.
Fixes: 676a7a30328b
[GlobalISel][AArch64] Fold vector multiplication by 0/1 masks into AND (#240134)
Multiplying a vector by a constant whose elements are all 0 or 1 only
keeps or clears lanes, so it can be done with an AND mask, as
SelectionDAG does. This adds a generic combine,
`mul_by_zero_one_vector`: `(mul x, <0/1...>) -> (and x, <0/-1...>)`, for
either operand order. All-zero and all-one vectors are left to the
existing combines.
```
define <2 x i32> @test(<2 x i32> %a) {
%r = mul <2 x i32> <i32 1, i32 0>, %a
ret <2 x i32> %r
}
```
Before:
```
adrp x8, .LCPI1_0
[7 lines not shown]
[mlir][SPIR-V] Collect availability of optional enum attributes (#240532)
The availability generator skipped OptionalAttr enums, so update-vce
gave ImageRead with Nontemporal v1.0 instead of v1.6
[BasicAA] Drop nsw when folding an overflowing constant offset (#242541)
Folding the constants in a chain of `nsw` adds or subtracts can overflow
even when the operations themselves are defined. Keeping `nsw` on the
resulting linear expression lets BasicAA return `NoAlias` for overlapping
accesses. Check the folded offset for signed overflow and drop `nsw` if
it wraps.
Split from #241380.
Proofs: https://alive2.llvm.org/ce/z/nq85ze
Assisted-by: Claude Code
Assisted-by: OpenAI Codex
[CIR] Keep volatile and atomic return loads before cleanups
When FlattenCFG routes a cir.return through a cleanup, it sinks a load
of an entry-block alloca that feeds the return into the block after the
cleanup. For a volatile or atomic load this moved the access past the
cleanup code. Such a load is now spilled to a temporary before the
cleanup, like any other return operand.
Assisted-by: Claude Code (claude-opus-5-5).
[CIR][NFC] Add isVolatileOrAtomic() to cir.load and cir.store
Several places spelled out getIsVolatile() || getMemOrder() to decide
whether a load or store must stay as written. Name that check once on
both ops and use it in the load effects, mem2reg, CIRSimplify and the
ABI rewriter.
Assisted-by: Claude Code (claude-opus-5-5).
[CIR] Report side effects of volatile loads and memory asm operands (#242691)
Dead code elimination erased some unused CIR ops that have side effects,
because their declared memory effects were too weak:
- `cir.load`, `cir.get_bitfield` and `cir.matrix.column_major_load`
declared only a read of their address, so an unused volatile or atomic
load was erased. A volatile or atomic load now also reads and writes
unknown memory, as `llvm.load` does.
- `cir.asm` reported nothing for a memory operand such as `"=*m"`, so an
asm whose only output is in memory was erased. It now reads and writes
each memory operand. The new `InlineAsmOp::isMemoryOperand` identifies
those operands, and the LLVM lowering uses it too.
- `cir.asm` now has a verifier: `operand_attrs` needs one entry per
operand, either a unit attribute on a pointer operand (a memory operand)
or an empty dictionary.
Assisted-by: Claude Code (claude-opus-5-5).
[CIR] Keep volatile and atomic return loads before cleanups
When FlattenCFG routes a cir.return through a cleanup, it sinks a load
of an entry-block alloca that feeds the return into the block after the
cleanup. For a volatile or atomic load this moved the access past the
cleanup code. Such a load is now spilled to a temporary before the
cleanup, like any other return operand.
Assisted-by: Claude Code (claude-opus-5-5).
[CIR][NFC] Add isVolatileOrAtomic() to cir.load and cir.store
Several places spelled out getIsVolatile() || getMemOrder() to decide
whether a load or store must stay as written. Name that check once on
both ops and use it in the load effects, mem2reg, CIRSimplify and the
ABI rewriter.
Assisted-by: Claude Code (claude-opus-5-5).
[BasicAA] Restrict cross-iteration separate_storage hints (#241381)
A `separate_storage` assumption applies to its operand values when it
executes. If the operands change across loop iterations, it does not
imply that an operand from one iteration is separate from the other
operand in another iteration. BasicAA can nevertheless use it to return
`NoAlias` in cross-iteration queries, causing GVN and loop-vectorization
miscompiles.
After finding a matching assumption that is valid in the query context,
require both underlying objects to be invariant according to
`isValueEqualInPotentialCycles()` before using it. Queries without a
usable assumption skip these checks. Same-iteration queries and
hints about loop-invariant objects remain supported.
Fixes #241378.
Assisted-by: Claude Code
Assisted-by: OpenAI Codex
[LoongArch] Cast to unsigned before LSHing in LoongArchMergeBaseOffsetOpt::detectAndFoldOffset() (#242656)
Make one step ahead of #242761 to fix a latent, similar problem in
`LoongArchMergeBaseOffsetOpt::detectAndFoldOffset`, as suggested by
@heiher.
[RISCV][P-ext] Restrict P widening shift legalization to left shifts (#242773)
The RV32 P-extension custom legalization for i64 shifts shares a path
for `SHL`, `SRL`, and `SRA`. Its known-bits checks select `WSLL` or
`WSLA` when the input fits in an unsigned or signed 32-bit value, but
both instructions perform a left shift.
This commit restricts this selection to `SHL` so right shifts use the
existing legalization paths.
Closes https://github.com/llvm/llvm-project/issues/242771
[LLD] Disable bitcode verification in release builds (#242663)
Similar to the plugin for other linkers, disable running the IR verifier
on bitcode input files. This improves ThinLTO link times by 1.5-1.8% and
stage2-clang build times by 0.57%.
p5-JSON-XS: update to 4.05.
4.05 Fri 13 Nov 2026 05:21:06 CET
- the incremental parser would not properly reset parsing offset
after removing a top-level number json number, causing memory
corruption. this is potentially a very serious vulnerability.
(reported by Albert Gierlach).
- the ignore initial whitespace optimisation in the incremental
parser could result in the parser reading beyond the end of string,
potentially leading to parsing errors or skipping json texts.
- FREEZE method calls could move the stack and cause a use-after-free.
requires allow_tags and a suitable FREEZE method to be exploited
(reported by Albert Gierlach).
- json_sv_grow would not allocate space for the trailing 0 byte.
possibly exploitable. (reported by Albert Gierlach).
- the incremental parser did not properly detect embedded NUL
characters as an error (reported by Peter Juhasz and his LLM).
- string and object decoding failures could leak a partially
constructed perl scalar (reported by Peter Juhasz).
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pci_dw: Honor the max-link-speed property
The root port reports in LNKCAP the highest link speed the core was
synthesized for, which can be more than the PHY behind it supports. On
the RK3568 pcie2x1 the root port advertises 8GT/s while the PHY only
does 5GT/s. The link stays at 2.5GT/s after the directed speed change.
Read max-link-speed from the device tree and write it to the Max Link
Speed field of LNKCAP and to the Target Link Speed field of LNKCTL2
before requesting the speed change. Nothing changes when the property
is absent.
Tested on a Quartz64 Model A with a Samsung 970 EVO Plus NVMe drive: the
link now trains at 5GT/s and the sequential throughput goes from 200MB/s
to 400MB/s.
Differential Revision: https://reviews.freebsd.org/D61014
mcommphy: Set the 10/100 TX delay of the YT8511
The TX clock delay of the YT8511 is split in two registers. The delay
used in gigabit mode is in the clock gating page and was already set
from the RGMII mode, but the one used in the 10/100 modes is in the next
page and was left at its reset value of 2ns. With a phy-mode that does
not ask for a TX delay in the PHY, the MAC provides it and the PHY adds
another 2ns in the 10/100 modes.
Set it like the gigabit one, like Linux does.
Tested on a Quartz64 Model A, gigabit and 100Mbit links.
Reviewed by: oh
Differential Revision: https://reviews.freebsd.org/D61015
top: implement pid highlighting
Implement PID highlighting. This can be activated by pressing
'L' and entering a PID to highlight. Highlighting can be cleared
by entering '+' as a PID to highlight. This feature is inspired by
the OpenBSD top, which uses 'P' key for that. We have to use 'L'
because 'P' is already used for toggling per-CPU statistics.
Reviewed by: kib
Obtained from: OpenBSD (partially)
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D61090
Hexagon: Use LastSubtargetCache in getSubtargetImpl
Migrate to the new common target pattern
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
ip.4: Fix ip_mreqn imr_address field name
This manual used imr_interface when describing the second field of
struct ip_mreqn, but sys/netinet/in.h names that field imr_address.
Note that ip_mreq below does have imr_interface which is unchanged.
PR: 300680
MFC after: 3 days
Reviewed by: ziaee
Closes: https://github.com/freebsd/freebsd-src/pull/2553
