[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)
Per the psABI discussion in riscv-non-isa/riscv-elf-psabi-doc#474, the
conclusion was to NOT introduce a new build attribute for MOP/HINT
encoding reinterpretation. Instead, the toolchain should recognize these
mnemonics unconditionally in the assembler and disassembler.
The rationale is that these encodings occupy reserved hint/MOP space
that is architecturally guaranteed not to trap on any compliant
implementation. Requiring explicit extension flags creates unnecessary
friction for users who simply want to write or read these instructions,
while providing no real safety benefit since the encodings are always
valid.
Note: Ideally, the ISA specification would explicitly guarantee that
these MOP/HINT encodings will never be reassigned to conflicting
instructions. However, the ISA architects prefer to preserve flexibility
in this area rather than making such guarantees in the spec. Given the
practical reality that reassignment is highly unlikely, the toolchain
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mvc: BaseModel - improve legacy mapper support when parent item doesn't exist.
Fixes:
ErrorException: Undefined array key 0 in /usr/local/opnsense/mvc/app/models/OPNsense/Base/BaseModel.php:755
Stack trace:
If we can't find the specified root node, we should create one, which is similar to non legacy mapper nodes.
[libc][SVE] add sve handling for memcpy with count less than 32b (#167446)
Add SVE optimization for AArch64 architectures. The idea is to use
predicate registers to avoid branching.
Microbench in repo shows considerable improvements on NV GB10 (locked on
largest X925):
```
======================================================================
BENCHMARK STATISTICS (time in nanoseconds)
======================================================================
memcpy_Google_A:
Old - Mean: 3.1257 ns, Median: 3.1162 ns
New - Mean: 2.8402 ns, Median: 2.8265 ns
Improvement: +9.14% (mean), +9.30% (median)
memcpy_Google_B:
Old - Mean: 2.3171 ns, Median: 2.3159 ns
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NAS-139545 / 26.0.0-BETA.1 / Fix dhcpcd not waiting for IP before backgrounding (#18142)
This commit fixes an issue where ix-netif would complete before DHCP had
assigned an IP address, causing services like Docker to fail on boot due
to missing network connectivity.
The `background` option in dhcpcd.conf was overriding the `-w` (waitip)
flag, causing dhcpcd to fork immediately instead of waiting for an IP.
libpmc: Fix the L3 counters for AMD Zen 1-4
On AMD processors libpmc was using the topic field (based on filename) to
determine the counter's subclass. Unfortunately, the JSON definitions for
AMD Zen 1-4 have the L3 counters in files shared with other counters.
This change has libpmc to use the pmu field (which is derived from the Unit
field in JSON) to determine the correct counter subclass.
Reviewed by: mhorne
MFC after: 2 weeks
Sponsored by: Netflix
Pull Request: https://github.com/freebsd/freebsd-src/pull/1984
[LegalizeTypes] Don't promote operands to VP extends (#179475)
This is part of the work to remove trivial VP intrinsics.
When promoting the result of a VP node, if we need to extend an operand
then we also extend it with a VP node.
We don't check if the VP node is legal though which will cause crashes
if the target doesn't support VP_ZEXT/VP_SEXT. This switches it to use a
regular non-VP node to extend instead.
powerpc/pmap: Use a constant for HPT superpage shift
There are no plans to allow multiple sizes of HPT superpages, so just use a
constant for it.
MFC after: 3 weeks
Fixes: 1bc75d77e9 ("powerpc/pmap/oea64: Make PV_LOCK superpage sized")
[SPIRV] selectDot4AddPacked: add missing PackedVectorFormat4x8Bit optional operand
According to SPIRV:
```
PackedVectorFormat4x8Bit (PackedVectorFormat4x8BitKHR)
Interpret 32-bit scalar integer operands as vectors of four 8-bit
components. Vector components follow byte significance order with the
lowest-numbered component stored in the least significant byte.
```
And in OpSDot / OpUDot:
```
When Vector 1 and Vector 2 are scalar integer types, Packed Vector
Format must be specified to select how the integers are to be
interpreted as vectors.
```
[RISCV] Use RISCVWidth in interface for vector load/store classes in RISCVInstrFormatsV.td. NFC (#179348)
This avoids repeating the splitting into mew/width in multiple places.
---------
Co-authored-by: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
devel/ruby-cucumber-core: update to 15.4.0
Latest release is 16.1.1 but cucumber-wire require < 16.
14.0.0 (2024-08-08)
Changed
* Permit usage of gherkin up to v29 and messages up to v26
* Internal Breaking Change: Structure of Action classes have changed.
* See upgrading notes for 14.0.0.md
* (#282)
Removed
* Remove support for ruby 2.6 and below. 2.7 or higher is required now
(Autofixed to Ruby 2.7 styles)
15.0.0 (2024-12-24)
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[flang][OpenMP] Add source range to construct scopes (#179259)
Make sure to add the source range whenever we create a scope for an
OpenMP construct or a clause. This allows that scope to be located via
context.FindScope(source).
devel/ruby-cucumber-tag-expressions: update to 8.1.0
Latest release is 9.0.0 but ruby-cucuber-core require < 9.
6.1.1 (2024-10-28)
Changed
* [Python] Use the new action cucumber/action-publish-pypi in release
process (#147 #172 #178)
* [Ruby] Fixed up remaining simple cops and began to reduce complexity of
code (#158)
6.1.2 (2025-01-29)
Added
* [All] Run CI testing only for relevant areas of the codebase (#186)
* [Python] Extended documentation and type hints within docstrings (#182)
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