devel/glib2: Don't try to set TCP_NODELAY on AF_UNIX sockets.
glib2 was calling setsockopt(socket, IPPROTO_TCP, TCP_NODELAY, ...) on AF_UNIX
sockets and ignoring the error. This interacted badly with a future change in
the pledge subsystem to strictly scope options to the socket's protocol.
ok ajacoutot@
[Mips] Select GPR register class based on requested type size (#220012)
In MipsTargetLowering::getRegisterByName(), the register class was
previously selected solely based on Subtarget.isGP64bit(), ignoring the
requested value type size (VT).
When compiling for a 64-bit MIPS CPU with the 32-bit o32 ABI (such as
-mcpu=mips3 -target-abi=o32), Subtarget.isGP64bit() is true even though
32-bit registers are expected. Reading a 32-bit named register like $gp
(e.g., via llvm.read_register.i32) returned a 64-bit register ($gp_64).
This resulted in a cross-register-class copy from GPR64 to GPR32 that
MipsSEInstrInfo::copyPhysReg() could not lower. In builds without
assertions, this constructed an invalid TargetOpcode::PHI (opcode 0)
instruction and caused a crash in MipsMCCodeEmitter during object file
emission.
Inspect VT.getSizeInBits() in getRegisterByName() to select
GPR32RegClassID for 32-bit types and GPR64RegClassID for 64-bit types
when supported by the subtarget, reporting an error for invalid types.
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[llvm-mc] Propagate invalid-token errors from byteArrayFromString (#217533)
byteArrayFromString always returned false after skipping an invalid
non-hex token, so llvm-mc exited 0 despite printing errors. Track
whether an error occurred so the process status matches.
[mlir] [linalg] Fold reduce(broadcast(x)) max/min (#213190)
This patch tries to implement the optimization for
```
max(broadcast(x)) -> x # (or replace min)
```
We can extend the optimization to other reduce op like add, mul, and,
or, xor ... in the future. This patch tries to be small by implementing
the simplest case.
AI assisted.
---------
Co-authored-by: yedeng.yd <yedeng.yd at alibaba-inc.com>
[SLP][NFC] Pre-commit test for AArch64 store-to-load forwarding bail-out (#218116)
Add an AArch64 SLP test that locks in the current (pre-feature)
vectorization of a widened backward load that aliases a widened store,
plus a narrow-load control case that never straddles two widened stores.
The follow-up patch adding the store-to-load forwarding cost-model
bail-out will update these checks, making its effect visible as a diff
on a non-X86 target.
---------
Co-authored-by: Cursor <cursoragent at cursor.com>
[SandboxVec][LoadStoreVec] Extract LoadStoreVec::vectorizeStores from runOnRegion
Move runOnRegion()'s body -- the store-chain legality checks, operand
classification, vector value construction, and profitability decision
-- into a new vectorizeStores(Bndl, Rgn, Sched, A) method. runOnRegion()
now only builds the initial bundle from the region's Aux and calls
vectorizeStores() once.
Snapshot the region's cost in saveIR() and decide accept vs revert in
acceptOrRevert(), so vectorizeStores() does not thread ScoreBoard or
CostBefore through the profitability check. NFC.
Co-authored-by: Cursor <cursoragent at cursor.com>
converters/py-markitdown: Add a run dependency
- Add sysutils/py-magika as run dependency
- Pet portfmt
- Remove IGNORE tag
PR: 297500 285927
Approved by: wen (maintainer)
AMDGPU: Lowercase the unsupported fence sync scope diagnostic (#220081)
Error messages should start with a lowercase letter per the diagnostic
policy.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
clang/AMDGPU: Diagnose invalid fence sync scope (#220077)
Reject an unrecognized synchronization scope string passed to
__builtin_amdgcn_fence during semantic analysis instead of relying on
the backend to report it during codegen.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[MC,test] Use # comments in llvm-mc --disassemble inputs (#220163)
llvm-mc --disassemble recognizes only # as a comment marker; `//` lead
to invalid-token errors, which will change the exit status after an
upcoming llvm-mc change.
X86: Pass instruction to inline asm register printing helpers (#219473)
printAsmMRegister and printAsmVRegister only used the operand to recover
its parent instruction's inline asm dialect. Pass the containing instruction
directly so they no longer depend on MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[LoongArch][Disassembler] Add symbolic operands for decoded immediates (#217971)
Symbolize operands for decoded immediates when possible. This gives
`LoongArchDisassembler` non-raw immediate capabilities similar to that
of `{X86,RISCV}Disassembler`. See also #217550 for similar work on
RISC-V.
This is part of the preparatory work for a future port of BOLT to
LoongArch.
[LAA][NFC] Factor out MemoryDepChecker::isStoreLoadForwardingConflict (#212085)
Extract the store-to-load forwarding conflict predicate used inside
MemoryDepChecker::couldPreventStoreLoadForward into a static helper so
it
can be shared with other consumers (e.g. the SLP vectorizer's STLF cost
model).
The helper takes an optional LoadElementSize so callers that know the
load
width can ask whether the load actually straddles two widened stores:
(a) a misaligned load that starts R = Distance % VectorStoreSize bytes
below a widened-store boundary overruns into the next store only if it
is wider than those R bytes (LoadElementSize > R), and
(b) an aligned load (R == 0) overruns only if it is itself wider than
the
widened store window (LoadElementSize > VectorStoreSize).
LoadElementSize defaults to 0 (unknown width, both terms disabled).
couldPreventStoreLoadForward passes VF as the load width, so (a) reduces
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