HardenedBSD/src 2e5472cinclude/rpc xdr.h, lib/libc/xdr xdr.c

Merge remote-tracking branch 'origin/hardened/current/master' into hardened/current/cross-dso-cfi
DeltaFile
+5-7sys/sys/buf_ring.h
+8-2sys/dev/dpaa2/dpaa2_ni.c
+1-8sys/rpc/xdr.h
+1-8include/rpc/xdr.h
+7-0lib/libc/xdr/xdr.c
+7-0sys/xdr/xdr.c
+29-253 files not shown
+34-299 files

OPNSense/core fe145d9src/opnsense/service/templates/OPNsense/Hostdiscovery rc.conf.d

interfaces: do not handle hostwatch user/group from here
DeltaFile
+1-1src/opnsense/service/templates/OPNsense/Hostdiscovery/rc.conf.d
+1-11 files

LLVM/project 7a10fc8llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/RISCV combine-clmul.ll

[DAG] Add basic folds for CLMUL nodes (#176961)

Closes #176783

Adds support for folding `ISD::CMUL`/`CMULH`/`CMULR` nodes.
DeltaFile
+64-349llvm/test/CodeGen/X86/pclmulqdq.ll
+85-0llvm/test/CodeGen/RISCV/combine-clmul.ll
+27-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+176-3493 files

LLVM/project 5faa181mlir/include/mlir/Transforms RegionUtils.h, mlir/lib/Transforms/Utils RegionUtils.cpp

[mlir] Add side-effect check to moveOperationDependencies (#176361)

This patch adds a side-effect check to `moveOperationDependencies` to
match the behavior of `moveValueDefinitions`. Previously,
`moveOperationDependencies` would move operations with side-effecting
dependencies, which could change program semantics.

**Note** that the existing test changes are needed because unregistered
operations (e.g., "moved_op"()) are treated as side-effecting. These
tests were updated to use pure operations for operations in the moved
slice, while keeping unregistered ops for operations that aren't moved
(e.g., "before"(), "foo"()). This ensures that tests continue to
exercise their intended functionality without being blocked by the new
side-effect check.
DeltaFile
+113-52mlir/test/Transforms/move-operation-deps.mlir
+38-8mlir/lib/Transforms/Utils/RegionUtils.cpp
+2-0mlir/include/mlir/Transforms/RegionUtils.h
+153-603 files

LLVM/project f135632llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/test/CodeGen/AArch64 sve-load-store-legalisation.ll

DAG: Use poison in more vector legalization contexts
DeltaFile
+2-83llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
+28-27llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+30-1102 files

HardenedBSD/src 5c80af6include/rpc xdr.h, lib/libc/xdr xdr.c

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+5-7sys/sys/buf_ring.h
+8-2sys/dev/dpaa2/dpaa2_ni.c
+1-8include/rpc/xdr.h
+1-8sys/rpc/xdr.h
+7-0lib/libc/xdr/xdr.c
+7-0sys/xdr/xdr.c
+29-253 files not shown
+34-299 files

LLVM/project c4afdd9mlir/lib/Dialect/Linalg/Transforms Detensorize.cpp, mlir/test/Dialect/Linalg detensorize_if.mlir detensorize_while_impure_cf.mlir

[mlir][linalg] Remove abandoned Detensorize pass
DeltaFile
+0-569mlir/lib/Dialect/Linalg/Transforms/Detensorize.cpp
+0-177mlir/test/Dialect/Linalg/detensorize_if.mlir
+0-104mlir/test/Dialect/Linalg/detensorize_while_impure_cf.mlir
+0-102mlir/test/Dialect/Linalg/detensorize_0d.mlir
+0-71mlir/test/Dialect/Linalg/detensorize_while.mlir
+0-58mlir/test/Dialect/Linalg/detensorize_while_pure_cf.mlir
+0-1,0815 files not shown
+0-1,22911 files

HardenedBSD/ports d5e4ff9sysutils/mdfried distinfo Makefile.crates, x11/wleave distinfo Makefile.crates

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+983-0sysutils/mdfried/distinfo
+490-0sysutils/mdfried/Makefile.crates
+105-95x11/wleave/distinfo
+51-46x11/wleave/Makefile.crates
+39-0sysutils/mdfried/Makefile
+27-8x11/wleave/files/patch-layout.json
+1,695-14916 files not shown
+1,782-20922 files

LLVM/project 4205c25llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeVectorOps.cpp, llvm/test/CodeGen/AMDGPU vector-reduce-umax.ll vector-reduce-or.ll

DAG: Use poison for unused shuffle operands in legalizer
DeltaFile
+71-74llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+28-28llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
+16-16llvm/test/CodeGen/X86/x86-interleaved-access.ll
+4-4llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+4-3llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+2-2llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+125-1276 files

OPNSense/core 24e42ccsrc/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes ProtocolFieldTest.php

mvc: add setAddOptions() to ProtocolField test
DeltaFile
+6-4src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes/ProtocolFieldTest.php
+6-41 files

LLVM/project dc741f2mlir/include/mlir/Dialect/Tosa/IR TosaShapeOps.td, mlir/lib/Dialect/Tosa/IR TosaCanonicalizations.cpp

[mlir][tosa] Add constant folding for tosa.add_shape operation (#173112)

This commit introduces constant folding for the tosa.add_shape
operation. When both operands of the add_shape operation are constant
shapes, the operation is evaluated at compile-time.
DeltaFile
+49-17mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
+33-0mlir/test/Dialect/Tosa/constant_folding.mlir
+2-0mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
+84-173 files

FreeNAS/freenas 1b716ffsrc/middlewared/middlewared/plugins/pool_ attach_disk.py

missing closing curly brace
DeltaFile
+1-1src/middlewared/middlewared/plugins/pool_/attach_disk.py
+1-11 files

FreeNAS/freenas 50e13adsrc/middlewared/middlewared/plugins/pool_ attach_disk.py

missing closing bracket
DeltaFile
+1-1src/middlewared/middlewared/plugins/pool_/attach_disk.py
+1-11 files

NetBSD/pkgsrc nKfvmWpdoc CHANGES-2026

   doc: Updated sysutils/fd-find to 10.3.0nb1
VersionDeltaFile
1.577+2-1doc/CHANGES-2026
+2-11 files

FreeNAS/freenas 873e52fsrc/middlewared/middlewared/plugins/pool_ attach_disk.py

better verror
DeltaFile
+1-1src/middlewared/middlewared/plugins/pool_/attach_disk.py
+1-11 files

NetBSD/pkgsrc kbm0Lgpsysutils/fd-find Makefile PLIST

   fd-find: install without renaming.

   As proposed on tech-pkg a week ago.
   Thanks to @wiz for fixing misc/fd
   https://mail-index.netbsd.org/pkgsrc-changes/2026/01/23/msg338874.html

   Bump PKGREVISION
VersionDeltaFile
1.17+4-3sysutils/fd-find/Makefile
1.2+3-3sysutils/fd-find/PLIST
+7-62 files

LLVM/project 4b7cf46lldb/include/lldb/Host/windows PseudoConsole.h ProcessLauncherWindows.h, lldb/source/Host/windows PseudoConsole.cpp ProcessLauncherWindows.cpp

[lldb][windows] add STDIN and STDOUT forwarding support (#175812)

DeltaFile
+92-32lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
+66-0lldb/source/Host/windows/PseudoConsole.cpp
+16-8lldb/source/Host/windows/ProcessLauncherWindows.cpp
+10-0lldb/include/lldb/Host/windows/PseudoConsole.h
+8-1lldb/include/lldb/Host/windows/ProcessLauncherWindows.h
+1-1lldb/test/Shell/Settings/TestFrameFormatColor.test
+193-421 files not shown
+194-437 files

LLVM/project f5b62a7mlir/lib/Dialect/Linalg/Transforms Vectorization.cpp, mlir/test/Dialect/Linalg/vectorization insert-slice.mlir

[mlir][linalg] Update createWriteOrMaskedWrite (#174810)

`createWriteOrMaskedWrite` is used extensively in the Linalg vectorizer.
When a write uses non-zero indices, the helper currently computes mask
sizes as if the write started at 0 (`size = dim(d)`), which can produce
incorrect `vector.create_mask` operands for the generated
`vector.transfer_write`. Instead, the mask size should be computed as
`size = dim(d) - write_index(d)`.

EXAMPLE
-------
Let`s use this example to illustrate:
```mlir
%res = tensor.insert_slice
    %src into %dest[0, %c2] [5, 1] [1, 1] : tensor<5x1xi32> into tensor<?x3xi32>
```

This op is vectorized as a pair of `vector.transfer_read` +
`vector.transfer_write` ops. When calculating the mask for the

    [20 lines not shown]
DeltaFile
+73-20mlir/test/Dialect/Linalg/vectorization/insert-slice.mlir
+18-3mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
+91-232 files

NetBSD/pkgsrc DuHjdutdoc CHANGES-2026

   doc: Updated misc/fd to 3.01bnb2
VersionDeltaFile
1.576+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc RiqxDg2misc/fd PLIST Makefile, misc/fd/patches patch-Makefile.in

   fd: install files under different name

   to make space for fd-find

   as proposed by pin@ on pkgsrc-users

   Bump PKGREVISION.
VersionDeltaFile
1.4+24-24misc/fd/PLIST
1.36+12-6misc/fd/Makefile
1.5+5-3misc/fd/patches/patch-Makefile.in
1.17+2-2misc/fd/distinfo
+43-354 files

OPNSense/core 5109d91src/opnsense/mvc/app/views/OPNsense/Firewall firewall_migration.volt

Firewall: Rules: Migration assistant: Fix typos and improve clarity in migration instructions

(cherry picked from commit a1404a24954f721b355ea4b7d2a11ba1a47a9e53)
DeltaFile
+5-5src/opnsense/mvc/app/views/OPNsense/Firewall/firewall_migration.volt
+5-51 files

OPNSense/core a1404a2src/opnsense/mvc/app/views/OPNsense/Firewall firewall_migration.volt

Firewall: Rules: Migration assistant: Fix typos and improve clarity in migration instructions
DeltaFile
+5-5src/opnsense/mvc/app/views/OPNsense/Firewall/firewall_migration.volt
+5-51 files

OpenBSD/ports NlGjsUstextproc/py-commonmark Makefile, textproc/py-commonmark/patches patch-setup_cfg

   replace deprecated dash-separated vars in setup.cfg
VersionDeltaFile
1.18+12-12textproc/py-commonmark/Makefile
1.1+10-0textproc/py-commonmark/patches/patch-setup_cfg
+22-122 files

OpenBSD/ports OevaCrPtextproc/py-rst2ansi Makefile, textproc/py-rst2ansi/patches patch-setup_cfg

   replace deprecated dash-separated vars in setup.cfg
VersionDeltaFile
1.1+10-0textproc/py-rst2ansi/patches/patch-setup_cfg
1.5+2-2textproc/py-rst2ansi/Makefile
+12-22 files

LLVM/project 689f978mlir/lib/Dialect/MLProgram/Transforms BufferizableOpInterfaceImpl.cpp, mlir/test/Dialect/MLProgram one-shot-bufferize.mlir

[ml_program] fix bufferizesToMemoryRead for ml_program.global_store (#177387)

This is a fix for the `BufferizableOpInterface` implementation for
`ml_program.global_store`.

`bufferizesToMemoryRead` currently returns false for
`GlobalStoreOpInterface`, but I believe it should return true as
`ml_program.global_store` needs to read its input buffer to know what
value to store to global.

This manifested in a bug where `one-shot-bufferize` would produce MLIR
that copies uninitialized data to the global var instead of the intended
value to be stored.

For the following MLIR:

```
module {
  ml_program.global private mutable @"state_tensor"(dense<0.0> : tensor<4x75xf32>) : tensor<4x75xf32>

    [61 lines not shown]
DeltaFile
+31-0mlir/test/Dialect/MLProgram/one-shot-bufferize.mlir
+1-1mlir/lib/Dialect/MLProgram/Transforms/BufferizableOpInterfaceImpl.cpp
+32-12 files

HardenedBSD/ports 0bb32f6math/scilab Makefile

math/scilab: pin to java 8

Does not build with jdk11+.

[javac] /wrkdirs/usr/ports/math/scilab/work/scilab-6.1.1/modules/graphic_objects/src/java/org/scilab/modules/graphic_objects/xmlloader/CSSParser.java:17: error: package javax.annotation does not exist

PR:     272855
Approved-by:    no maintainer
DeltaFile
+1-0math/scilab/Makefile
+1-01 files

FreeBSD/ports 0bb32f6math/scilab Makefile

math/scilab: pin to java 8

Does not build with jdk11+.

[javac] /wrkdirs/usr/ports/math/scilab/work/scilab-6.1.1/modules/graphic_objects/src/java/org/scilab/modules/graphic_objects/xmlloader/CSSParser.java:17: error: package javax.annotation does not exist

PR:     272855
Approved-by:    no maintainer
DeltaFile
+1-0math/scilab/Makefile
+1-01 files

LLVM/project 51b8d45llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp

[AMDGPU][NFC] Refine the representation of MODE register values.

- Eliminate the field masks.
- Segregate the encoding logic.
- Simplify and clarify the user code.

This is supposed to help updating downstream branches where we
have a more advanced version of the same facility.
DeltaFile
+55-56llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+55-561 files

LLVM/project de8126dclang/lib/AST/ByteCode Interp.h, clang/test/AST/ByteCode c.c

[clang][bytecode] Fix mulc/divc op for IntegralAP types (#177565)

We need to allocate those.

Fixes https://github.com/llvm/llvm-project/issues/176740
DeltaFile
+23-1clang/lib/AST/ByteCode/Interp.h
+8-0clang/test/AST/ByteCode/c.c
+31-12 files

OPNSense/plugins 2b44156dns/ddclient Makefile

dns/ddclient: small bump for now
DeltaFile
+1-0dns/ddclient/Makefile
+1-01 files