LLVM/project 0212229.ci/green-dragon lldb-windows.groovy

[CI] install packaging before running lldb tests on Windows (#201112)

https://ci-external.swift.org/job/lldb-windows/job/main/ is failing
because lldb API tests require the `packaging` module.

This patch installs it before running the `check-lldb` target.
DeltaFile
+2-0.ci/green-dragon/lldb-windows.groovy
+2-01 files

LLVM/project 75334ffllvm/include/llvm/Analysis TargetLibraryInfo.h, llvm/lib/Analysis TargetLibraryInfo.cpp

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+135-48llvm/lib/Analysis/TargetLibraryInfo.cpp
+0-115llvm/unittests/Analysis/ReplaceWithVecLibTest.cpp
+34-19llvm/include/llvm/Analysis/TargetLibraryInfo.h
+0-1llvm/unittests/Analysis/CMakeLists.txt
+169-1834 files

FreeBSD/ports cd74c7bx11/wallutils Makefile

x11/wallutils: Mark broken with libheif 1.22.2

See also: https://github.com/xyproto/wallutils/issues/58
DeltaFile
+2-0x11/wallutils/Makefile
+2-01 files

LLVM/project 350fc57llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

[review] Reduce compile-time overhead.
DeltaFile
+13-11llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+13-111 files

LLVM/project 726aafcllvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

[reviews] reduce overhead
DeltaFile
+8-6llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+8-61 files

LLVM/project 436e661llvm/test/CodeGen/AMDGPU udiv-miscompilation.ll

[reviews] Improve test.
DeltaFile
+70-2llvm/test/CodeGen/AMDGPU/udiv-miscompilation.ll
+70-21 files

LLVM/project 2b8509cllvm/test/CodeGen/AMDGPU div-rem-fast-path.ll udiv-miscompilation.ll

[reviews] Add full pipeline test and remove previous one.

Co-authored-by: Carlo Bertolli <carlo.bertolli at amd.com>
DeltaFile
+694-0llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
+0-102llvm/test/CodeGen/AMDGPU/udiv-miscompilation.ll
+694-1022 files

LLVM/project 2f1ddc0llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU udivrem24.ll udiv.ll

[AMDGPU] Fix LowerDIVREM24 lowering for the unsigned case

The code was not properly checking that the operands were
24-bit integers for the unsigned case.
DeltaFile
+70-78llvm/test/CodeGen/AMDGPU/udivrem24.ll
+19-22llvm/test/CodeGen/AMDGPU/udiv.ll
+34-0llvm/test/CodeGen/AMDGPU/udiv-miscompilation.ll
+14-6llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+137-1064 files

LLVM/project b54d214llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp, llvm/test/MC/RISCV rvi-pseudos.s

[llvm][RISCV][MC] Fix arithmetic error in pseudo parsing (#200217)

When arithmetic was used in RISCV pseudo instructions, like lla, the
custom parsing breaks the associativity of the operators by parsing the
entire remainder of an expression. This would lead to scenarios where we
would parse `top - 0x100 -0x10` as `top - (0x100 -0x10)` and yield the
wrong offset (`0xF0`(wrong) vs. `0x110`(correct)).

Instead, don't advance the parser and just examine the token to
determine if it's an identifier and if we should handle this case or
bail out. In cases we do handle, just use `parseExpression()`, which
will handle this correctly.
DeltaFile
+5-31llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+6-0llvm/test/MC/RISCV/rvi-pseudos.s
+11-312 files

LLVM/project 3dfd4f7clang/include/clang/Analysis/Analyses/LifetimeSafety LoanPropagation.h, clang/lib/Analysis/LifetimeSafety LoanPropagation.cpp

[LifetimeSafety] Refactor buildOriginFlowChain to use PImpl pattern (#201071)

Move `buildOriginFlowChain` into `AnalysisImpl`, removing `FactManager`
parameter
DeltaFile
+46-40clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
+2-2clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
+0-1clang/unittests/Analysis/LifetimeSafetyTest.cpp
+48-433 files

LLVM/project f834b7foffload/plugins-nextgen/level_zero/include L0CmdListManager.h L0Queue.h, offload/plugins-nextgen/level_zero/src L0Device.cpp L0Queue.cpp

[OFFLOAD][L0] Move dataFence logic to L0Queue (#201046)

The dataFence device operation logic was still on L0Device. With this all the operations working on command lists have their logic consolidated in L0Queue.
DeltaFile
+1-12offload/plugins-nextgen/level_zero/src/L0Device.cpp
+8-0offload/plugins-nextgen/level_zero/include/L0CmdListManager.h
+6-2offload/plugins-nextgen/level_zero/include/L0Queue.h
+5-0offload/plugins-nextgen/level_zero/src/L0Queue.cpp
+20-144 files

LLVM/project e8f518dllvm/include/llvm/Analysis VectorUtils.h, llvm/lib/Analysis VectorUtils.cpp

[VectorUtils] Replace maskIsAll{Zero,One}OrUndef with PatternMatch (#200040)

As part of the ongoing effort to deprecate UndefValue, and also to take
better advantage of pattern matching, eliminate the VectorUtils
functions `maskIsAllZeroOrUndef`/`maskIsAllOneOrUndef` and replace them
with new matchers `m_ZeroOrPoison` and `m_AllOnesOrPoison`.

The new matchers are simply `m_CombineOr` on `m_Zero`/`m_AllOnes` and
`m_Poison`. `m_Zero` and `m_AllOnes` already match vectors where some
(but not all) elements are poison, so these matchers were created to
also match the case where all elements are poison.

This affects InstCombine/InstSimplify with a mask containing `undef` for
the intrinsics `llvm.masked.load`, `llvm.masked.store`,
`llvm.masked.gather`, and `llvm.masked.scatter`.

Some relevant tests were altered to use poison instead of undef, and
test coverage for masked loads/stores with poison was increased.
DeltaFile
+0-52llvm/lib/Analysis/VectorUtils.cpp
+19-3llvm/test/Transforms/InstCombine/masked_intrinsics.ll
+10-8llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+0-10llvm/include/llvm/Analysis/VectorUtils.h
+3-3llvm/test/Transforms/InstSimplify/call.ll
+3-3llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
+35-793 files not shown
+44-839 files

LLVM/project d81e8afllvm/lib/Target/AMDGPU GCNSchedStrategy.cpp GCNSchedStrategy.h, llvm/test/CodeGen/AMDGPU rewrite-mfma-form-spill-cost-reset.ll

[AMDGPU] RewriteMFMAFormStage: fix SpillCost early-return missing reset (#199708)

Extract resetRewriteCandsToVGPR() to consolidate the logic that restores
MFMA candidates from AGPR form back to VGPR form after cost analysis.

getRewriteCost() returned early when SpillCost > 0 without resetting the
AGPR-form register classes set by initHeuristics(), leaving MRI in a
corrupted state. Call resetRewriteCandsToVGPR() on both the early-return
path and the normal exit path to fix this.

Also change getRewriteCost() and rewrite() to take ArrayRef instead of
const std::vector& for cleaner API.

---------

Co-authored-by: Claude Sonnet 4 (1M context) <noreply at anthropic.com>
DeltaFile
+642-0llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
+33-27llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+6-3llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+681-303 files

NetBSD/pkgsrc-wip ed6a078clang distinfo, clang-tools-extra distinfo

llvm: updated to 22.1.7
DeltaFile
+3-3compiler-rt/distinfo
+3-3clang/distinfo
+3-3clang-tools-extra/distinfo
+3-3flang/distinfo
+3-3libcxx/distinfo
+3-3libcxxabi/distinfo
+18-189 files not shown
+43-4315 files

FreeBSD/ports 0217ba6devel/stack Makefile

devel/stack: fix build on powerpc64le

This architecture was added in 13.0-RELEASE.
DeltaFile
+1-1devel/stack/Makefile
+1-11 files

FreeBSD/ports b6357f8devel/libffi321/files patch-configure

devel/libffi321: fix build on powerpc64le

Adds powerpc64le to powerpc64 case.
DeltaFile
+7-5devel/libffi321/files/patch-configure
+7-51 files

FreeBSD/ports afdbd44cad/hs-verismith/files patch-__cabal__deps_tasty-1.5.3_tasty.cabal

cad/hs-verismith: fix build on powerpc64le

powerpc64le is 64-bit as well.
DeltaFile
+11-0cad/hs-verismith/files/patch-__cabal__deps_tasty-1.5.3_tasty.cabal
+11-01 files

FreeBSD/ports b46cbafdevel/libffi33 Makefile

devel/libffi33: fix build on powerpc64le

ld: error: version script assignment of 'LIBFFI_BASE_7.0' to symbol 'ffi_type_longdouble' failed: symbol not defined
DeltaFile
+2-0devel/libffi33/Makefile
+2-01 files

FreeBSD/ports d8780bbdevel/hs-cabal-plan/files patch-__cabal__deps_tasty-1.5.3_tasty.cabal

devel/hs-cabal-plan: fix build on powerpc64le

powerpc64le is also 64-bit.
DeltaFile
+11-0devel/hs-cabal-plan/files/patch-__cabal__deps_tasty-1.5.3_tasty.cabal
+11-01 files

FreeBSD/ports 5cf7a16finance/hs-hledger/files patch-__cabal__deps_tasty-1.5.3_tasty.cabal

finance/hs-hledger: fix build on powerpc64le

powerpc64le is also 64-bit.
DeltaFile
+11-0finance/hs-hledger/files/patch-__cabal__deps_tasty-1.5.3_tasty.cabal
+11-01 files

FreeBSD/ports d3e6c09dns/dq distinfo Makefile

dns/dq: update to 20260601
DeltaFile
+3-3dns/dq/distinfo
+2-2dns/dq/Makefile
+5-52 files

LLVM/project 6bcdd84llvm/lib/Target/X86 X86ISelLowering.cpp X86InstrCompiler.td, llvm/test/CodeGen/X86 bt-merge-fuse.ll bittest-big-integer.ll

[X86] Merge BT with a matching BTR/BTS/BTC (#193612)

Fixes #165291.

BTR/BTS/BTC set CF from the pre-operation bit value, so a subsequent BT
on the same source and bit index produces the same CF and is redundant.
We were emitting both.

```ll
define i1 @btr_eq_i32(ptr %word, i32 %position) nounwind {
  %ofs = and i32 %position, 31
  %bit = shl nuw i32 1, %ofs
  %mask = xor i32 %bit, -1
  %ld = load i32, ptr %word
  %test = and i32 %ld, %bit
  %res = and i32 %ld, %mask
  %cmp = icmp eq i32 %test, 0
  store i32 %res, ptr %word
  ret i1 %cmp

    [37 lines not shown]
DeltaFile
+343-0llvm/test/CodeGen/X86/bt-merge-fuse.ll
+116-194llvm/test/CodeGen/X86/bittest-big-integer.ll
+97-0llvm/lib/Target/X86/X86ISelLowering.cpp
+12-0llvm/lib/Target/X86/X86InstrCompiler.td
+8-0llvm/lib/Target/X86/X86InstrFragments.td
+576-1945 files

FreeBSD/ports 7c613bcx11/hamclock Makefile, x11/hamclock/files patch-Makefile patch-wsServer_Makefile

x11/hamclock: Remove expired port

2026-06-01 x11/hamclock: Upstream programmer is deceased upstream server discontinued in June
DeltaFile
+0-45x11/hamclock/Makefile
+0-21x11/hamclock/files/patch-Makefile
+0-11x11/hamclock/files/patch-wsServer_Makefile
+0-11x11/hamclock/files/patch-ArduinoLib_Makefile
+0-11x11/hamclock/files/patch-hamclock.desktop
+0-11x11/hamclock/files/patch-liveweb.cpp
+0-1105 files not shown
+1-12611 files

FreeBSD/ports f9af651. MOVED, devel Makefile

devel/rye: Remove expired port

2026-06-01 devel/rye: Rye is no longer developed. All users should migrate to uv, the successor project from the same maintainers, which is actively maintained and much more widely used.
DeltaFile
+0-607devel/rye/distinfo
+0-342devel/rye/Makefile
+0-6devel/rye/pkg-descr
+1-0MOVED
+0-1devel/Makefile
+1-9565 files

LLVM/project f813817llvm/lib/Target/SPIRV SPIRVBuiltins.cpp, llvm/test/CodeGen/SPIRV/transcoding/OpenCL convert_signedness.ll

[SPIR-V] Select int-to-int convert opcode from source signedness (#201116)

OpSConvert/OpUConvert sext/zext is determined by the source operand, not
the destination type. Discovered in
https://github.com/llvm/llvm-project/pull/200791/changes#r3341230426

Fix a regression caused by #200791
DeltaFile
+67-0llvm/test/CodeGen/SPIRV/transcoding/OpenCL/convert_signedness.ll
+3-4llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+70-42 files

LLVM/project 8dd5139lldb/include/lldb/Target Memory.h, lldb/source/Target Memory.cpp

[lldb][NFC] Factor out helper code from MemoryCache (#201120)

This will be reused in a subsequent commit.
DeltaFile
+17-12lldb/source/Target/Memory.cpp
+5-0lldb/include/lldb/Target/Memory.h
+22-122 files

LLVM/project afd040copenmp/tools/archer ompt-tsan.cpp

[OpenMP][OMPT] Remove unused var in archer (#201140)

Working on enabling the build of OpenMP and Offload in pre-merge checks
surfaced this unused var and pre-merge checks run with -Werror.

As I did not see where it should be used, remove the variable to address
the warning.

The pre-merge running into the warning as error is
https://github.com/llvm/llvm-project/actions/runs/26826349862/job/79094823845?pr=174955
DeltaFile
+0-2openmp/tools/archer/ompt-tsan.cpp
+0-21 files

LLVM/project 87b97d6clang-tools-extra/docs conf.py

[clang-tools-extra][docs] Do not require myst_parser when building man pages (#201138)
DeltaFile
+12-2clang-tools-extra/docs/conf.py
+12-21 files

LLVM/project 8f58a4cmlir/include/mlir/Dialect/EmitC/IR EmitC.td, mlir/lib/Dialect/EmitC/IR EmitC.cpp

[mlir][emitc]: Add MemberCallOpaque op (#200057)

Cf. https://discourse.llvm.org/t/method-calls-in-emitc/90898
DeltaFile
+55-19mlir/lib/Target/Cpp/TranslateToCpp.cpp
+53-20mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
+45-5mlir/test/Dialect/EmitC/invalid_ops.mlir
+31-18mlir/lib/Dialect/EmitC/IR/EmitC.cpp
+30-0mlir/test/Target/Cpp/call.mlir
+29-0mlir/test/Dialect/EmitC/member_call_opaque.mlir
+243-627 files not shown
+261-8013 files

LLVM/project e8f3866clang/docs LanguageExtensions.rst, clang/lib/CodeGen CodeGenModule.cpp CodeGenModule.h

[PowerPC][AIX] Add -mloadtime-comment-vars support to preserve variables
in the final object file.
DeltaFile
+180-83llvm/lib/Transforms/Utils/LowerCommentStringPass.cpp
+77-0clang/lib/CodeGen/CodeGenModule.cpp
+66-0clang/docs/LanguageExtensions.rst
+37-0clang/test/CodeGen/loadtime-comment-vars.c
+34-0llvm/test/Transforms/LowerCommentString/loadtime-comment-vars.ll
+8-0clang/lib/CodeGen/CodeGenModule.h
+402-833 files not shown
+417-839 files