FreeBSD/ports d276ac3x11/xev pkg-descr Makefile

x11/xev: Update to 1.2.7

Add WWW and update pkg-descr.

https://lists.x.org/archives/xorg/2026-May/062237.html

PR:             295593
Approved by:    x11 (arrowd)
Approved by:    fluffy (mentor)
DeltaFile
+7-1x11/xev/pkg-descr
+3-3x11/xev/Makefile
+3-3x11/xev/distinfo
+13-73 files

FreeBSD/ports 81547c9deskutils/mate-utils pkg-plist Makefile

deskutils/mate-utils: switch to GitHub source

Switch from MATE mirror to GitHub tarball using USE_GITHUB and
GH_ACCOUNT=mate-desktop, add autoreconf, mate-submodules GH_TUPLE,
autoconf-archive, yelp-tools, disable gtk-doc, and remove stale
API doc plist entries.
DeltaFile
+0-31deskutils/mate-utils/pkg-plist
+14-8deskutils/mate-utils/Makefile
+5-3deskutils/mate-utils/distinfo
+19-423 files

LLVM/project 705dff2llvm/lib/Target/RISCV RISCVInstrInfoY.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

update for version 0.9.8.2 of the spec

Created using spr 1.3.8-beta.1
DeltaFile
+241-0llvm/test/MC/RISCV/rvy/rvy-basic.s
+168-0llvm/lib/Target/RISCV/RISCVInstrInfoY.td
+42-0llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+39-0llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+37-0llvm/test/MC/RISCV/rvy/rvy-basic-invalid.s
+33-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+560-07 files not shown
+581-513 files

LLVM/project 0e0127elldb/source/ValueObject ValueObjectVTable.cpp, lldb/test/API/functionalities/vtable TestVTableValue.py

[lldb] Fix vtable support on arm64e (#199116)

There were 2 small issues.
1. ValueObjectVTableChild was not fixing the addresses it was pulling
from signed pointers. This broke things like `SBValue::GetLoadAddress`
and identifying the function pointer type from debug info.
2. TestVTableValue.py made a lot of assumptions that did not hold on
arm64e. a. GetValueAsUnsigned will return a raw pointer value. Most of
the time, we needed GetValueAsAddress. b. The test was reading pointers
out of memory without fixing them up. c. The summary for a function
pointer on arm64e includes the load address. This isn't true on other
platforms.
DeltaFile
+10-8lldb/test/API/functionalities/vtable/TestVTableValue.py
+4-0lldb/source/ValueObject/ValueObjectVTable.cpp
+14-82 files

NetBSD/pkgsrc 2LmKzeXtextproc/R-hunspell Makefile distinfo, textproc/R-hunspell/patches patch-src_Makevars

   (textproc/R-hunspell) Fix build against R 4.6.0
VersionDeltaFile
1.1+21-0textproc/R-hunspell/patches/patch-src_Makevars
1.5+3-1textproc/R-hunspell/Makefile
1.7+2-1textproc/R-hunspell/distinfo
+26-23 files

FreeBSD/doc fa8a0a2website/content/ru/community mailinglists.adoc

website/ru: Update community/mailinglists.adoc

Update to EN bc0477aa666e7393792c15236a95a366469e05b9
DeltaFile
+3-7website/content/ru/community/mailinglists.adoc
+3-71 files

LLVM/project aa1e02dllvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

minor cleanup, rebase

Created using spr 1.3.8-beta.1
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+16,047-2,4481,232 files not shown
+57,071-25,4751,238 files

LLVM/project c2b92d3llvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+16,047-2,4481,229 files not shown
+57,062-25,4741,235 files

LLVM/project 013587ellvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

add more tests

Created using spr 1.3.8-beta.1
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+16,047-2,4481,238 files not shown
+57,110-25,6361,244 files

LLVM/project f57f30bllvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+16,047-2,4481,237 files not shown
+57,063-25,6361,243 files

LLVM/project 3177b3ellvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, llvm/test/CodeGen/X86 horizontal-reduce-umax.ll

rebase

Created using spr 1.3.8-beta.1
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+0-2,353llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+13,851-4,8012,377 files not shown
+88,102-48,5232,383 files

LLVM/project 8a64511llvm/test/Analysis/LoopAccessAnalysis clamped-access-pattern.ll, llvm/test/Transforms/LoopVectorize runtime-check-small-clamped-bounds.ll hoist-predicated-loads-with-predicated-stores.ll

[LV] Add tests with pointers based on URem expressions (NFC). (#199763)

Add tests with loads and stores with pointers based on URem expressions.
DeltaFile
+1,076-0llvm/test/Analysis/LoopAccessAnalysis/clamped-access-pattern.ll
+633-176llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll
+427-0llvm/test/Transforms/LoopVectorize/AArch64/clamped-load.ll
+156-34llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
+152-0llvm/test/Transforms/LoopVectorize/clamped-load-vf-ranges.ll
+101-0llvm/test/Transforms/LoopVectorize/AArch64/discarded-interleave-group.ll
+2,545-2102 files not shown
+2,656-2108 files

LLVM/project 0eb28e6llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV get-vec-element-size.ll fmuladd_width_prop.ll

[SLP] Propagate through instrinsics in BoUpSLP::getVectorElementSize() (#199129)

We propagate through simple binary operations already, some operations
are excluded since it happens to be an intrinsic.

Motivated by case exposed when removing vectorization from pre-LTO, see
https://github.com/llvm/llvm-project/pull/195886#issuecomment-4486422243.
DeltaFile
+16-36llvm/test/Transforms/SLPVectorizer/RISCV/get-vec-element-size.ll
+18-18llvm/test/Transforms/SLPVectorizer/RISCV/fmuladd_width_prop.ll
+18-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+52-553 files

NetBSD/pkgsrc pP54lxbdoc CHANGES-2026

   doc: Updated time/R-RcppCCTZ to 0.2.14
VersionDeltaFile
1.3293+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc QaLZ9Swtime/R-RcppCCTZ distinfo Makefile, time/R-RcppCCTZ/patches patch-src_Makevars

   time/R-RcppCCTZ) Updated 0.2.13 to 0.2.14

   (pkgsrc)
     - Fix build against R 4.6.0
     - USE_TOOLS+= gmake only for ifne in patch-src_Makevars

   (upstream)
   News for Package 'RcppCCTZ'

   Changes in version 0.2.14 (2026-01-08):

           * Synchronized with upstream CCTZ (Dirk in #46).

           * Explicitly enumerate files to be compiled in 'src/Makevars*'
             (Dirk in #47)
VersionDeltaFile
1.1+18-0time/R-RcppCCTZ/patches/patch-src_Makevars
1.3+5-4time/R-RcppCCTZ/distinfo
1.5+5-2time/R-RcppCCTZ/Makefile
+28-63 files

LLVM/project 2c33687llvm/test/CodeGen/AMDGPU extract-vector-elt-binop-build-vector.ll

[AMDGPU] Add regression test for extract of vector binop scalarization (#198825)

Test that extracting both lanes from a binop of two build_vectors
sharing a variable operand at different lane positions correctly folds
per-lane constants.

Assisted-by: Cursor (Claude)
DeltaFile
+87-0llvm/test/CodeGen/AMDGPU/extract-vector-elt-binop-build-vector.ll
+87-01 files

FreeNAS/freenas 6bd8205src/middlewared/middlewared/api/v27_0_0 zpool_query.py

Update v27 pydantic model
DeltaFile
+3-0src/middlewared/middlewared/api/v27_0_0/zpool_query.py
+3-01 files

FreeNAS/freenas 4d93aeasrc/middlewared/middlewared/api/v26_0_0 zpool_query.py, src/middlewared/middlewared/plugins/zpool crud.py

Expose all_sed property on zpool.query

This commit adds changes to surface the all_sed flag on zpool.query entries so callers can identify pools made up entirely of Self-Encrypting Drives without going through pool.query.
DeltaFile
+11-1src/middlewared/middlewared/plugins/zpool/crud.py
+3-0src/middlewared/middlewared/api/v26_0_0/zpool_query.py
+14-12 files

LLVM/project a4c8cfdllvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUTargetStreamer.cpp, llvm/test/CodeGen/AMDGPU elf-note-null-terminator.ll

[AMDGPU] Fix ELF note emission to include null terminator (#199720)

The `AMDGPUTargetELFStreamer::EmitNote()` function claims the note name
includes a null terminator (NameSZ = Name.size() + 1) but only emits the
string bytes via `emitBytes(Name)`, relying on alignment padding to
provide the null byte. Works for most situations but breaks with 8-byte
names where padding lands exactly at the boundary.

Explicitly emit null terminator with `S.emitInt8(0)` after
`emitBytes(Name)`.
DeltaFile
+33-0llvm/test/CodeGen/AMDGPU/elf-note-null-terminator.ll
+1-0llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+34-02 files

NetBSD/pkgsrc 9KODei7doc CHANGES-2026

   add py-certipy and py-pamela
VersionDeltaFile
1.3292+3-1doc/CHANGES-2026
+3-11 files

LLVM/project c052a26clang/include/clang/Basic DarwinSDKInfo.h, clang/lib/Basic DarwinSDKInfo.cpp

Revert "[clang][driver][darwin] Hold onto full triples in Darwin SDKP… (#199756)

…latformInfo (#197791)"

This reverts commit 9c06c5de6a20df13cfe6d9a7022308e96f378955. It broke
downstream builds for compiler-rt builtins.

 Resolves: rdar://177813095
DeltaFile
+25-109clang/lib/Basic/DarwinSDKInfo.cpp
+33-35clang/include/clang/Basic/DarwinSDKInfo.h
+12-6clang/lib/Driver/ToolChains/Darwin.cpp
+2-2clang/unittests/Basic/DarwinSDKInfoTest.cpp
+1-1clang/lib/Driver/ToolChains/Darwin.h
+73-1535 files

NetBSD/pkgsrc SSk3Jm0security Makefile, security/py-pamela Makefile PLIST

   py-pamela: add version 1.2.0

   PAM interface using ctypes
VersionDeltaFile
1.1+19-0security/py-pamela/Makefile
1.1+9-0security/py-pamela/PLIST
1.1+5-0security/py-pamela/distinfo
1.1006+2-1security/Makefile
1.1+1-0security/py-pamela/DESCR
+36-15 files

LLVM/project 210323bllvm/lib/Target/AMDGPU SIFrameLowering.cpp SIMachineFunctionInfo.h, llvm/test/CodeGen/AMDGPU amdgpu-spill-cfi-saved-regs.ll

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
DeltaFile
+2,926-0llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
+12-0llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+10-0llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+9-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+2,959-05 files

LLVM/project 708acd4llvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c
DeltaFile
+67-67llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+33-0llvm/lib/MC/MCDwarf.cpp
+15-15llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+10-0llvm/lib/CodeGen/MachineFunction.cpp
+4-4llvm/test/CodeGen/AMDGPU/debug-frame.ll
+4-0llvm/include/llvm/CodeGen/MachineFunction.h
+133-865 files not shown
+143-9011 files

LLVM/project 3b7e787llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll

[AMDGPU] Use register pair for PC spill

Change-Id: Ibedeef926f7ff235a06de65a83087c151f66a416
DeltaFile
+4,331-4,331llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,742-1,740llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+1,562-1,560llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,462-1,460llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+1,238-1,236llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+1,030-1,028llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+11,365-11,35589 files not shown
+18,153-18,04495 files

LLVM/project b39f39dllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll gfx-callable-argument-types.ll

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+3,568-2,598llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,912-1,913llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+2,700-12llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+631-631llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+505-510llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+394-399llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+9,710-6,063108 files not shown
+14,819-9,521114 files

LLVM/project 17a001c

[AMDGPU] Implement CFI for non-kernel functions

This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.

Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+0-00 files

LLVM/project 9b4ad51

[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU

While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).

Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
DeltaFile
+0-00 files

LLVM/project 162b859

[AMDGPU] Emit entry function Dwarf CFI

Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.

Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+0-00 files

LLVM/project b87bafe

[Clang] Default to async unwind tables for amdgcn

To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.

There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.

Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
DeltaFile
+0-00 files