DDT: Add locking for table ZAP destruction
Similar to BRT, DDT ZAP can be destroyed by sync context when it
becomes empty. Respectively similar to BRT introduce RW-lock to
protect open context methods from the destruction.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Alexander Motin <alexander.motin at TrueNAS.com>
Closes #18115
[clang-tools-extra] Update Maintainers for Clang-Doc (#175822)
Currently, Erick Velez has been doing the bulk of clang-doc development.
We're also moving one of the old maintainers that hasn't participated in
almost a year to inactive.
Set default asyncio executor to shared IO thread pool
This commit sets the event loop's default executor to the existing IO thread pool, preventing asyncio.to_thread() from creating a separate thread pool.
x86: Add intr_enable_src()
Function to enable specific IRQ source.
This will be used by the s2idle code to enable just SCIs on x86 to break
the CPU out of idle.
Reviewed by: olce
Approved by: olce
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D48734
acpi: Suspend-to-idle support (s2idle)
Implement STYPE_SUSPEND_TO_IDLE sleep type added in c43473dc9b83
("sys/power: Generic sleep types").
This is a prerequisite for the firmware to enter the S0ix states. When
suspending to idle, the system stays in an ACPI S0 state, but the CPUs
are idled and devices are suspended/resumed before and after this as
they would be when entering any other sleep type (except for AWAKE and
POWEROFF).
Factor out do_standby, do_sleep, and add a new do_idle function for
idling the CPU (a future patch will make this an idle loop and not just
a simple cpu_idle() call). In do_idle, SCIs (interrupt 9) are enabled to
allow wake events to break the CPU out of idle.
Record all the steps made instead of just the last one in slp_state,
which allows for more flexible unwinding (will be useful to not have to
goto breakout if the SPMC entry call fails when that is committed).
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[AArch64] Let LoadStoreOptimizer handle renamable implicit-defs. (#174186)
The LoadStoreOptimizer is very conservative with handling instructions
that have implicit-def operands and only support them for 2
instructions. However, they can be considered when a MachineOperand is
marked explicitly as 'renamable'.
[AArch64] Enable subreg liveness tracking for streaming functions. (#174189)
Most use of subreg liveness tracking will be for streaming SME2
functions where it can use the strided- and contiguous form of the
multi-vector LD1, see #123081 for details.
Any regressions come from disabling coalescing of SUBREG_TO_REG when
sub-reg liveness tracking is enabled, which may introduce some scalar
`mov`s and may limit some peephole optimizations from the load-store
optimizer, but the impact of disabling coalescing seems limited in
practice (empirically from trying this on workloads) and we think the
regressions are offset by improvements to the handling of multi-vector
instructions (tuple registers) in SME2.
PR #174188 addresses these issues in a separate PR.
npf.conf(5): fix incorrect .Bl type
A list can't be -bullet and -hang at the same time. It's obviously
supposed to be -hang (as .It comes with text), but make it -tag
instead, as -hang is harder to read, IMO.
[libc] Support %lc in printf (#169983)
Add support for %lc in printf by calling internal wcrtomb function and
relevant end-to-end sprintf test. Additionally, modified printf parser
for recognizing length modifier and added two internal error codes. Also
added a flag to disable wchar support on windows platform. Resolves
#166598
Co-authored-by: shubh at DOE <shubhp at mbm3a24.local>
[clang] Restore diagnostic for certain jumps into VLA(ish) scopes. (#175833)
Commit 543f112e148a enabled diagnostics for C++ compatibility for jumps
over initialization of variables. However, inadvertently this may cause
a prior diagnostic for jumps into scopes of variables with variably
modified types to be replaced with the less severe C++ compatibility
warning, resulting in impossible codegen.
This skips the check for the C++ compatibility warning if there is
already another diagnostic planned for the scope.
Fixes #175540
[SPIRV] Handle `externally_initialized` for AMDGCN flavoured SPIRV (#175277)
SPIR-V doesn't currently have a way to encode the `externally_initialized` LLVM concept. Unfortunately, certain HIP constructs (e.g. `__managed__` or `__constant__` variables) rely on it. Hence, this patch allows AMDGCN flavoured SPIR-V to encode `externally_initialized` via the `HostAccessINTEL` decoration, which approximates some of the semantics; the decoration is handled during reverse translation. It also appears that we never fully implemented the decoration, which I intend to handle in a subsequent, independent patch.
[mlir][spirv] Allow complex element types in memref allocation checks (#175836)
Support for complex types in SPIR-V was introduced in
97f3bb73a29a566e99e33ae4338c2c3d9957e561, and memref type conversion was
updated accordingly to include them. However, the element type precheck
used during memref alloc/dealloc pattern matching in the SPIR-V lowering
was not updated to recognize complex element types. This patch resolves
this inconsistency.
Fixes: https://github.com/iree-org/iree/issues/23117
---------
Signed-off-by: Eric Feng <Eric.Feng at amd.com>
[AMDGPU] Return two MMOs for load-to-lds and store-from-lds intrinsics
Accurately represent both the load and the store part of those
intrinsics.
The test changes seem to be mostly fairly insignificant changes caused by
subtly different scheduler behavior.
commit-id:0269189c
