LLVM/project ab7bbbbflang/include/flang/Optimizer/Dialect FIRAttr.h, flang/lib/Lower ConvertVariable.cpp

[flang][AllocationPlacement] prevent promotion of mock result to allocmem (#212825)

Under the new experimental pass that can move automatic arrays to the
heap, "mock" result storage may be promoted to allocmem before
AbstractResult removes them and replace them by a hidden result.

Add a fir.must_be_stack attribute to these mock alloca so they are never
promoted. So that passes dealing with array function results ABI can
expect to find an fir.alloca and remove it.
DeltaFile
+15-2flang/lib/Lower/ConvertVariable.cpp
+15-0flang/test/Integration/allocation-placement-array-result.f90
+6-6flang/test/Lower/HLFIR/custom-intrinsic.f90
+11-0flang/lib/Optimizer/Transforms/AllocationPlacement.cpp
+10-0flang/include/flang/Optimizer/Dialect/FIRAttr.h
+4-4flang/test/Lower/HLFIR/array-ctor-index.f90
+61-124 files not shown
+67-1810 files

LLVM/project 551f3c8llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: Export the TargetParser feature bitset

Previously this bitset was only used to populate the feature
name string map used by clang. Eventually this will replace
the current bitmask integer. AArch64 already has a similar
interface.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+17-14llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+29-0llvm/unittests/TargetParser/TargetParserTest.cpp
+16-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+62-143 files

LLVM/project 30aafd8clang/test/CodeGen link-builtin-bitcode.c, llvm/lib/Target/AMDGPU AMDGPU.td

AMDGPU: Tablegenerate TargetParser feature sets

Traditionally we maintained 2 parallel feature mechanisms,
one in clang (later moved to TargetParser), with largely
mirrored subtarget features defined in the backend. Start
directly taking feature information from the backend and putting
it into TargetParser. This is still in a compromise mid-migration
state. We still have both the legacy "ArchAttr" bitfield integer,
plus a new AMDGPUFeatureBitset field stored in the table, which
isn't yet exported.

For the moment, the new bitset is only used to populate the
feature string name map, which is the big maintainability win.
This also lists an explicit subset of exported features to
avoid churn.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+51-508llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+115-3llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+43-0llvm/unittests/TargetParser/TargetParserTest.cpp
+39-0llvm/lib/Target/AMDGPU/AMDGPU.td
+3-3clang/test/CodeGen/link-builtin-bitcode.c
+251-5145 files

LLVM/project 51ed0aeflang/lib/Lower/OpenMP ClauseProcessor.cpp, flang/lib/Optimizer/OpenMP LowerWorkdistribute.cpp

[flang][OpenMP] Lower allocate align modifier on parallel

Lower the align modifier on OpenMP allocate clauses for parallel constructs.
Carry per-item alignments through the OpenMP dialect and select
__kmpc_aligned_alloc for aligned private storage while retaining the existing
allocation and cleanup behavior for unaligned items.

Add source, verifier, preservation, LLVM IR, i386 ABI, and overflow coverage.
Keep unsupported construct kinds and device lowering unchanged.

Assisted-by: GitHub Copilot
DeltaFile
+81-49mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+115-10mlir/test/Target/LLVMIR/openmp-allocate-clause.mlir
+52-0mlir/test/Dialect/OpenMP/invalid.mlir
+20-16flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
+19-10flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+25-0flang/test/Semantics/OpenMP/allocate-clause01.f90
+312-8512 files not shown
+383-11018 files

LLVM/project d3ca4e5libcxx/include streambuf, libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.get.area setg.assert.pass.cpp

[libc++][NFC] Rename the streambuf members (#212277)

This refactors `streambuf` to contain a `_GetArea` and a `_PutArea`.
This makes the code significantly easier to read, since the pointers
belonging together are bundled in a struct.
DeltaFile
+41-47libcxx/include/streambuf
+3-3libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.get.area/setg.assert.pass.cpp
+1-1libcxx/test/std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.put.area/setp.assert.pass.cpp
+45-513 files

LLVM/project 0d78fb5llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize epilog-vectorization-reductions.ll

[VPlan] Make simplifyRecipe more like InstCombine

Most combines in simplifyRecipe RAUW a value, but not all of them erase the old recipe.
Unify them and bring it in line with InstCombine by having it return a VPValue, which simplifyRecipes can then call RAUW with, and automatically erase the old recipe.

Similarly to InstCombine, combines that modify a recipe should return the same recipe.
DeltaFile
+113-149llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-11llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll
+0-2llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
+113-1623 files

LLVM/project 98cdcbalibcxx/include __locale, libcxx/include/__locale_dir num.h

[libc++] Move numpunct into <__locale_dir/num.h> (#212465)

`numpunct` is part of the `num` family of facets, so it should live in
`num.h`.
DeltaFile
+0-98libcxx/include/__locale
+98-0libcxx/include/__locale_dir/num.h
+8-0libcxx/test/libcxx/transitive_includes/cxx23.csv
+6-0libcxx/test/libcxx/transitive_includes/cxx26.csv
+1-0libcxx/test/std/utilities/format/format.functions/locale-specific_form.pass.cpp
+1-0libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/locale-specific_form.pass.cpp
+114-983 files not shown
+117-989 files

LLVM/project c27b357libcxx/include tuple

[libc++] Remove SFINAE checks in tuple which are always true (#212765)

We have a specialization for `tuple` with no arguments, so checking
`sizeof...(_Tp) >= 1` in the primary template will never be false.
DeltaFile
+5-7libcxx/include/tuple
+5-71 files

LLVM/project 6ddd80alldb/source/Target Memory.cpp, lldb/unittests/Target MemoryTest.cpp

[lldb] Fix stale L1 memory cache read after memory write (#208347)

A `memory write` can leave stale bytes in the L1 memory cache, so a later
`memory read` of the address that was just written returns the old value.

The L1 cache (`m_L1_cache`) is a map keyed by each chunk's start address, and
chunks can overlap: a read larger than an L2 cache line
(`target.memory-cache-line-size`, 512 by default) bypasses L2 and is stored
whole in L1, so two large reads can produce two chunks that both cover the same
address.

`Flush()` invalidates the L1 cache on a write. It started at the chunk at or
below the flushed address and walked forward, stopping at the first chunk that
did not intersect. It therefore never inspected a chunk that starts below the
flushed address but is long enough to reach into it, leaving that chunk behind
with the stale byte. A later read fully contained in that chunk is served from
the cache and returns the old value.

Fix `Flush()` to walk the whole L1 cache and erase every chunk that intersects

    [7 lines not shown]
DeltaFile
+117-0lldb/unittests/Target/MemoryTest.cpp
+8-8lldb/source/Target/Memory.cpp
+125-82 files

LLVM/project 506d70dllvm/lib/Analysis BlockFrequencyInfoImpl.cpp

[BFI] Compute the minimum frequency only when dumping. NFC (#212957)
DeltaFile
+13-16llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
+13-161 files

LLVM/project 9814675llvm/lib/Target/Sparc/AsmParser SparcAsmParser.cpp, llvm/test/MC/Sparc/Directives seg.s

[SPARC] Support the .seg directive (#209001)

Support the legacy .seg directive used by SunOS SPARC assembly. Map
"text", "data", "data1", and "bss" to their corresponding MC sections,
using subsection 1 for "data1".
DeltaFile
+36-0llvm/test/MC/Sparc/Directives/seg.s
+22-0llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+58-02 files

FreeBSD/ports a8df53cmath/suitesparse-Example Makefile

math/suitesparse-Example: upgrade to 1.8.11

Lost in the latest SuiteSparse’s upgrade.
DeltaFile
+1-1math/suitesparse-Example/Makefile
+1-11 files

FreeBSD/ports d8da5e2devel/py-cfn-lint distinfo Makefile, devel/py-cfn-lint/files patch-src_cfnlint_maintenance.py

devel/py-cfn-lint: Update to 1.52.1

ChangeLog:      https://github.com/aws-cloudformation/cfn-lint/compare/v1.50.1...v1.52.1
Approved by:    hrs (mentor, blanket)
DeltaFile
+6-5devel/py-cfn-lint/Makefile
+3-3devel/py-cfn-lint/distinfo
+2-2devel/py-cfn-lint/files/patch-src_cfnlint_maintenance.py
+11-103 files

OpenBSD/ports GWQK8HLnet/monitoring-plugins Makefile distinfo, net/monitoring-plugins/patches patch-plugins_check_ntp_time_c patch-plugins_check_snmp_d_check_snmp_helpers_c

   update to monitoring-plugins-3.0.2, from Alvar Penning
VersionDeltaFile
1.3+2-2net/monitoring-plugins/patches/patch-plugins_check_snmp_d_check_snmp_helpers_c
1.20+2-2net/monitoring-plugins/distinfo
1.63+1-1net/monitoring-plugins/Makefile
1.5+0-0net/monitoring-plugins/patches/patch-plugins_check_ntp_time_c
+5-54 files

FreeBSD/ports 965df0cdevel/py-aws-sam-translator Makefile distinfo

devel/py-aws-sam-translator: Update to 1.111.0

ChangeLog:      https://github.com/aws/serverless-application-model/compare/v1.109.0...v1.111.0
Approved by:    hrs (mentor, blanket)
DeltaFile
+3-3devel/py-aws-sam-translator/distinfo
+2-2devel/py-aws-sam-translator/Makefile
+5-52 files

LLVM/project 58c12ffllvm/test/CodeGen/AMDGPU atomic_optimizations_mul_one.ll, llvm/test/CodeGen/AMDGPU/GlobalISel atomic_optimizations_mul_one.ll

1. Move test out of globalIsel directory.
2. Rename functions with type.
DeltaFile
+0-972llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
+972-0llvm/test/CodeGen/AMDGPU/atomic_optimizations_mul_one.ll
+972-9722 files

FreeBSD/ports d529dd7sysutils/hcloud Makefile distinfo

sysutils/hcloud: Update to 1.67.0

Changelog: https://github.com/hetznercloud/cli/releases/tag/v1.67.0
DeltaFile
+5-5sysutils/hcloud/distinfo
+1-2sysutils/hcloud/Makefile
+6-72 files

FreeBSD/ports 00dfac3devel/codebase-memory-mcp Makefile, devel/codebase-memory-mcp/files patch-src_main.c freebsd-src.cbmignore

devel/codebase-memory-mcp: new port

MCP server that indexes source code into a persistent knowledge graph for AI
coding agents.
DeltaFile
+87-0devel/codebase-memory-mcp/files/patch-src_cli_cli.c
+43-0devel/codebase-memory-mcp/Makefile
+31-0devel/codebase-memory-mcp/files/pkg-message.in
+28-0devel/codebase-memory-mcp/files/freebsd-src.cbmignore
+28-0devel/codebase-memory-mcp/files/patch-src_mcp_mcp.c
+27-0devel/codebase-memory-mcp/files/patch-src_main.c
+244-04 files not shown
+266-010 files

LLVM/project ddb662dllvm/lib/Target/WebAssembly WebAssemblyTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/WebAssembly vector-shift.ll

[WebAssembly][TTI] Avoid crash when costing scalable vector shifts (#212759)

I see the following 

```
 anutosh491 at Anutoshs-MacBook-Air llvm-project % cat /private/tmp/wasm-scalable-shift-cost.ll
define <vscale x 4 x i32> @shift(<vscale x 4 x i32> %x,
                                 <vscale x 4 x i32> %amount) {
  %result = shl <vscale x 4 x i32> %x, %amount
  ret <vscale x 4 x i32> %result
}


 anutosh491 at Anutoshs-MacBook-Air llvm-project % build-assert/bin/opt \
  -mtriple=wasm32-unknown-unknown \
  -mattr=+simd128 \
  -passes='print<cost-model>' \
  -disable-output \
  /private/tmp/wasm-scalable-shift-cost.ll

    [27 lines not shown]
DeltaFile
+42-0llvm/test/Analysis/CostModel/WebAssembly/vector-shift.ll
+2-2llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
+44-22 files

FreeBSD/ports 199db27cad/klayout Makefile distinfo

cad/klayout: Update to 0.30.10

PR:             297149
DeltaFile
+3-3cad/klayout/distinfo
+1-1cad/klayout/Makefile
+4-42 files

FreeBSD/ports 497ab7btextproc/oyo Makefile distinfo

textproc/oyo: Update to 0.1.56

- Update WWW address

ChangeLog:

- https://github.com/ahkohd/oyo/releases/tag/v0.1.55
- https://github.com/ahkohd/oyo/releases/tag/v0.1.56

Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+3-3textproc/oyo/distinfo
+2-2textproc/oyo/Makefile
+5-52 files

LLVM/project 9aee371llvm/docs LangRef.md, llvm/include/llvm/Support CodeGen.h

IR: Introduce "float-abi" module flag (#210821)

This is intended to eliminate the FloatABIType TargetOptions field.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+33-8llvm/include/llvm/Support/CodeGen.h
+37-0llvm/test/Verifier/module-flags-float-abi.ll
+33-0llvm/docs/LangRef.md
+16-12llvm/lib/IR/AutoUpgrade.cpp
+28-0llvm/test/Linker/module-flags-float-abi.ll
+16-0llvm/test/Bitcode/upgrade-ppc-float-abi.ll
+163-204 files not shown
+201-2010 files

NetBSD/pkgsrc-wip ab683d1postgresql-pgvector TODO

postgresql-pgvector: Add reference to CVE-2026-18022
DeltaFile
+1-1postgresql-pgvector/TODO
+1-11 files

NetBSD/pkgsrc-wip 5d66eb2java-netty TODO

java-netty: Add reference to recent CVEs
DeltaFile
+2-1java-netty/TODO
+2-11 files

OPNSense/core 4f30f46src/opnsense/scripts/interfaces reconfigure_gifs.php

Interfaces: Devices: Gif: Fix typo in reconfigure_gifs, variable gre should be gif
DeltaFile
+4-4src/opnsense/scripts/interfaces/reconfigure_gifs.php
+4-41 files

LLVM/project ef7f2f6llvm/lib/Target/RISCV RISCVVectorPeephole.cpp, llvm/test/CodeGen/RISCV/rvv vlmax-peephole.mir

[RISCV] Fix crash in convertToVLMAX when AVL is an ADDI of a frame index (#212923)

`getConstant()` recognizes an AVL that is an immediate by checking
the opcode is `ADDI`, then reading the second operand and checking
if it is `X0`. However the second operand may be a frame index and
`getReg()` asserts with "This is not a register operand!".

We should guard the register access with `isReg()` before comparing
against `X0`.

Fixes #212797.
DeltaFile
+25-0llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir
+1-1llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+26-12 files

OPNSense/core 0eb084bsrc/etc/inc interfaces.inc, src/opnsense/mvc/app/controllers/OPNsense/Interfaces/forms dialogGif.xml

Interfaces: Devices: Gif: add noclamp flag
DeltaFile
+11-0src/opnsense/mvc/app/controllers/OPNsense/Interfaces/forms/dialogGif.xml
+3-1src/etc/inc/interfaces.inc
+1-0src/opnsense/mvc/app/models/OPNsense/Interfaces/Gif.xml
+15-13 files

LLVM/project 27c7355mlir/test/Target/SPIRV debug.mlir non-uniform-ops.mlir

[NFC][mlir][SPIR-V] Use Subgroup scope in GroupNonUniform tests (#212928)

After https://github.com/KhronosGroup/SPIRV-Tools/pull/6811 spirv-val
rejects Workgroup scope on these ops
DeltaFile
+26-26mlir/test/Target/SPIRV/non-uniform-ops.mlir
+1-1mlir/test/Target/SPIRV/debug.mlir
+27-272 files

FreeBSD/ports 2624273security/vuxml/vuln 2026.xml

security/vuxml: add www/*chromium < 151.0.7922.71

Obtained from:  https://chromereleases.googleblog.com/2026/07/stable-channel-update-for-desktop_0887107924.html
DeltaFile
+771-0security/vuxml/vuln/2026.xml
+771-01 files

LLVM/project 46919d2llvm/docs AMDGPUAsyncOperations.md

[Docs][AMDGPU] Explain completion of async operations (#212756)

This improves the somewhat hand-wavey "memory model" currently described
for async operations. While this version is also not complete, it
prepares for the more complete memory model being written down.
DeltaFile
+26-12llvm/docs/AMDGPUAsyncOperations.md
+26-121 files