LLVM/project 182ca95llvm/lib/IR Verifier.cpp, llvm/test/Verifier funclet-unreachable-block.ll

[Verifier] Don't look up the funclet color of an unreachable block (#222500)

Fixes #192015.
DeltaFile
+23-17llvm/lib/IR/Verifier.cpp
+17-0llvm/test/Verifier/funclet-unreachable-block.ll
+40-172 files

LLVM/project 6a31f4cllvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.alignbyte.ll true16-fold.mir

fold sgpr32 via vgpr16
DeltaFile
+116-12llvm/test/CodeGen/AMDGPU/true16-fold.mir
+26-58llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+57-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+4-11llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
+206-861 files not shown
+207-887 files

LLVM/project fb68217llvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU lit.local.cfg

add machine verifier check
DeltaFile
+84-3llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+2-0llvm/test/CodeGen/AMDGPU/lit.local.cfg
+89-33 files

LLVM/project 31ba9fbllvm/test/CodeGen/AMDGPU llvm.amdgcn.image.d16.dim.ll float-to-arbitrary-fp-fp8-hw.ll

fix pattern
DeltaFile
+8,380-1llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
+1,481-1,527llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+1,021-1,456llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+172-359llvm/test/CodeGen/AMDGPU/bf16.ll
+210-215llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+359-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.d16.dim.ll
+11,623-3,55833 files not shown
+12,685-4,58839 files

LLVM/project daad92bllvm/test/CodeGen/AMDGPU flat-atomicrmw-fmax.ll flat-atomicrmw-fadd.ll

rebase and update test
DeltaFile
+3,288-3,225llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+2,102-1,533llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,514-1,093llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+1,141-782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+9,129-8,82346 files not shown
+16,525-19,50352 files

LLVM/project d9ba48ellvm/test/CodeGen/AMDGPU amdgcn.bitcast.96bit.ll amdgcn.bitcast.64bit.ll

calling conv update
DeltaFile
+6,170-6,382llvm/test/CodeGen/AMDGPU/bf16.ll
+2,693-2,459llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,693-2,459llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+2,257-2,804llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,437-1,838llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+1,341-1,683llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+16,591-17,625158 files not shown
+39,905-35,725164 files

LLVM/project 46436bellvm/test/CodeGen/AMDGPU fptoui-sat-scalar.ll usubsat.ll, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.raw.tbuffer.store.f16.ll combine-fma-add-fma-mul.ll

update test
DeltaFile
+434-434llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
+146-218llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+106-170llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+134-134llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+42-89llvm/test/CodeGen/AMDGPU/usubsat.ll
+13-41llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+875-1,0869 files not shown
+1,006-1,26315 files

LLVM/project a1166edllvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU fminimum3.ll fmaximum3.ll

legalizeOpWithMove check for sgpr32 to vgpr16 case
DeltaFile
+36-39llvm/test/CodeGen/AMDGPU/select.f16.ll
+32-36llvm/test/CodeGen/AMDGPU/bf16.ll
+4-8llvm/test/CodeGen/AMDGPU/minmax.ll
+10-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+2-2llvm/test/CodeGen/AMDGPU/fminimum3.ll
+2-2llvm/test/CodeGen/AMDGPU/fmaximum3.ll
+86-884 files not shown
+91-9410 files

LLVM/project e10b4a1llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU constant-bus-illegal-fold-true16.ll

added mir test
DeltaFile
+54-0llvm/test/CodeGen/AMDGPU/constant-bus-illegal-fold-true16.ll
+1-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+55-12 files

LLVM/project f5d0b36llvm/test/CodeGen/AMDGPU amdgcn.bitcast.96bit.ll amdgcn.bitcast.64bit.ll

rebase and update test
DeltaFile
+4,514-4,291llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,630-2,495llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,272-1,259llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+610-596llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+452-453llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+406-397llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+9,884-9,4914 files not shown
+9,990-9,59310 files

LLVM/project 3168070llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU fminimum3.ll fmaximum3.ll

split legalizeOpWithMove
DeltaFile
+39-36llvm/test/CodeGen/AMDGPU/select.f16.ll
+36-32llvm/test/CodeGen/AMDGPU/bf16.ll
+8-4llvm/test/CodeGen/AMDGPU/minmax.ll
+0-9llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+2-2llvm/test/CodeGen/AMDGPU/fminimum3.ll
+2-2llvm/test/CodeGen/AMDGPU/fmaximum3.ll
+87-854 files not shown
+93-9010 files

LLVM/project c4e8e11llvm/test/CodeGen/AMDGPU amdgcn.bitcast.128bit.ll float-to-arbitrary-fp-widen.ll

address comment, add sgpr32 reg_seq optimization and hi16 fix
DeltaFile
+6,154-6,576llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,754-2,970llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+2,433-2,655llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,433-2,655llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+1,441-1,431llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+673-705llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+15,888-16,99239 files not shown
+18,542-20,37845 files

LLVM/project 2daaaa9llvm/test/CodeGen/AMDGPU amdgcn.bitcast.832bit.ll amdgcn.bitcast.256bit.ll

Legalize sgpr16 in sdag
DeltaFile
+26,193-18,947llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,727-8,485llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,708-2,866llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+5,324-2,688llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+4,605-3,063llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+4,942-2,490llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+57,499-38,539126 files not shown
+105,453-71,135132 files

LLVM/project ef326feclang/test/CodeGenHLSL/builtins ldexp.hlsl ddy.hlsl, clang/test/SemaHLSL/BuiltIns ldexp-errors.hlsl

[HLSL][LongVec] Add more intrinsic support (#222043)

resolves #220699
resolves #220655
resolves #220639
resolves #220638
resolves #220614
DeltaFile
+46-1clang/test/CodeGenHLSL/builtins/mad.hlsl
+34-7clang/test/CodeGenHLSL/builtins/asdouble.hlsl
+0-8clang/test/SemaHLSL/BuiltIns/ldexp-errors.hlsl
+7-0clang/test/CodeGenHLSL/builtins/ddy.hlsl
+7-0clang/test/CodeGenHLSL/builtins/ddx.hlsl
+6-0clang/test/CodeGenHLSL/builtins/ldexp.hlsl
+100-161 files not shown
+105-167 files

LLVM/project bb65118lldb/include/lldb/Interpreter/Interfaces ScriptedFrameInterface.h, lldb/include/lldb/Target StackFrameRecognizer.h

[lldb] Report a scripted frame's variables with the frame's value type (#221708)

A scripted frame's variable exists as two objects: a Variable holding
the scope the frame assigned it, and a ValueObject holding what the
frame built. SBValue::GetValueType() reports the ValueObject's, and
GetValueObjectForFrameVariable handed that ValueObject back unchanged,
so the scope never reached a client. A ValueObject built in Python is a
ValueObjectConstResult, which reports how it was produced rather than
which variable it stands for, leaving anything that groups a frame's
variables by scope unable to place it. `frame variable` was unaffected
because it reads the Variables directly.

This patch presents the ValueObject under that scope instead. A class
for this already existed as ValueObjectRecognizerSynthesizedValue, which
frame recognizers use to name an argument: both take a ValueObject that
cannot report the ValueType it is being presented as and supply that
ValueType for it, so generalize that one into
ValueObjectSynthesizedValue and use it for both. ValueObjectVariable is
the other class that pairs a ValueObject with a ValueType, but it cannot

    [28 lines not shown]
DeltaFile
+71-0lldb/source/ValueObject/ValueObjectSynthesizedValue.cpp
+65-0lldb/include/lldb/ValueObject/ValueObjectSynthesizedValue.h
+4-36lldb/include/lldb/Target/StackFrameRecognizer.h
+21-2lldb/source/Plugins/Process/scripted/ScriptedFrame.cpp
+17-0lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py
+13-1lldb/include/lldb/Interpreter/Interfaces/ScriptedFrameInterface.h
+191-392 files not shown
+192-428 files

LLVM/project 81c7e6ellvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-sched-ds-fifo.mir coexec-block-carried-latency.mir

Address comments.

Avoid prioritizing DMA and fence candidates while they still have an effective stall.

Make the top-down requirement explicit and remove unreachable bottom-up handling.
DeltaFile
+41-42llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+29-0llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+14-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+1-1llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
+1-1llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
+86-455 files

LLVM/project 8d2597dllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

Adrress comments from https://github.com/llvm/llvm-project/pull/188658

Change-Id: Ia94c567a753168c1ffa16dc5d91195e7dd0ba044
DeltaFile
+114-114llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+3-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+117-1172 files

LLVM/project d562696llvm/test/CodeGen/AMDGPU coexec-block-carried-latency.mir coexec-sched-effective-stall.mir

Update tests

Change-Id: Ided5a4e6968d4670d1fd09bcb327a75a25273d4e
DeltaFile
+99-99llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+2-2llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
+101-1012 files

LLVM/project a33e068llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add comment

Change-Id: I2180bba631fe4a01ed3c3fbcfa8c19cbefa84133
DeltaFile
+1-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-01 files

LLVM/project 06ea0d6llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f
DeltaFile
+6-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+6-01 files

LLVM/project a92cbbdllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

Make fence heuristic work bottom-up

Change-Id: I629cbc8905b87a962e8b123287e5f60a3154df6b
DeltaFile
+22-19llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+7-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+29-252 files

LLVM/project b79aaf5llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484
DeltaFile
+7-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+7-01 files

LLVM/project fe825a4llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

[AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5
DeltaFile
+323-0llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+76-20llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+20-2llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+419-223 files

LLVM/project 534f247llvm/test/CodeGen/AMDGPU coexec-block-carried-latency.mir

Test update
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
+3-31 files

LLVM/project c793abbmlir/include/mlir/Conversion Passes.td, mlir/lib/Conversion/MathToXeVM MathToXeVM.cpp

[mlir][MathToXeVM] Route math ops by fastmath: native for `afn`, OCL otherwise. (#223816)

The pass had two lowerings for the same math ops. `afn` fastmath ops
went to the OpenCL `native_` intrinsics. Everything else was only
lowered when the `convert-to-ocl` option was set, which defaulted to
off, so those ops were left untouched.

Make `convert-to-ocl` default to true. The fastmath flag now picks the
intrinsic on its own:

  - `afn` set   -> `__spirv_ocl_native_*`, fast but approximate.
  - `afn` unset -> `__spirv_ocl_*`, precise.

`fastmath<fast>` is a group that expands to include `afn`, so it takes
the native path too. Other flags without `afn` do not.

The precedence already worked: the native patterns get a higher pattern
benefit than the precise ones, so an `afn` op still gets the native
intrinsic when both pattern sets are live. Spell the benefits out

    [8 lines not shown]
DeltaFile
+34-2mlir/test/Conversion/MathToXeVM/math-to-ocl.mlir
+15-10mlir/include/mlir/Conversion/Passes.td
+7-5mlir/test/Conversion/MathToXeVM/math-to-xevm.mlir
+7-5mlir/lib/Conversion/MathToXeVM/MathToXeVM.cpp
+63-224 files

LLVM/project eb5f248lldb/source/Plugins/SymbolFile/DWARF SymbolFileDWARFDebugMap.cpp, lldb/test/Shell/SymbolFile/DWARF missing-oso.cpp

[lldb] Report an error when a debug map object file is missing (#223576)

When an OSO in the debug map does not exist on disk, LLDB records the
load error on the CompileUnitInfo but never surfaces it. The sibling
mod-time-mismatch branch does report, so a stale .o produces a
diagnostic while a deleted one fails silently.

This is easy to hit with LTO. The linker writes the merged object to a
temporary path and deletes it, so unless the build passes
-object_path_lto the debug map points at a file that is already gone.

rdar://162327417
DeltaFile
+11-0lldb/test/Shell/SymbolFile/DWARF/missing-oso.cpp
+2-0lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
+13-02 files

OpenBSD/src scfkFYWlib/libc/gen readpassphrase.c

   Don't override ignored signals when setting up signal handlers
   for readpassphrase(3), avoids spin when called with no controlling TTY,
   in a background process group, and with SIGTTIN and/or SIGTTOU already
   set to SIG_IGN by its parent.

   Portable OpenSSH b3995; with/ok millert and guenther
VersionDeltaFile
1.30+34-19lib/libc/gen/readpassphrase.c
+34-191 files

LLVM/project 59ae8d3.github/workflows build-ci-container.yml, .github/workflows/containers/github-action-ci Dockerfile

[CI] Use Ubuntu 26.04 for Premerge Image (#223883)

Mainly so that we pull in a newer CMake version given the minimum is
getting bumped soon, but also to get the upgrade over with.
DeltaFile
+1-1.github/workflows/containers/github-action-ci/Dockerfile
+1-1.github/workflows/build-ci-container.yml
+2-22 files

LLVM/project 32a8fd5utils/bazel/llvm-project-overlay/mlir/test/Dialect BUILD.bazel

[bazel] Fix 82004b076831331b0567bc9d8b53263a4fabd74b (#223892)

Add split-file dep for mlir test in
82004b076831331b0567bc9d8b53263a4fabd74b
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/test/Dialect/BUILD.bazel
+1-01 files

LLVM/project b2d656cllvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.alignbyte.ll true16-fold.mir

fold sgpr32 via vgpr16
DeltaFile
+116-12llvm/test/CodeGen/AMDGPU/true16-fold.mir
+26-58llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+57-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+4-11llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
+206-861 files not shown
+207-887 files