OPNSense/core 6e0c447src/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes ProtocolFieldTest.php

sfd
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OPNSense/core 7f52f4csrc/opnsense/mvc/tests/app/models/OPNsense/Base/FieldTypes ProtocolFieldTest.php

fix and extend test case
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OPNSense/core 826c29esrc/opnsense/mvc/app/models/OPNsense/Base/FieldTypes ProtocolField.php

of
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OPNSense/core 77ad946src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes ProtocolField.php

my mistake
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LLVM/project cc0b331llvm/lib/Transforms/InstCombine InstCombineMulDivRem.cpp InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine binop-itofp.ll pow-to-ldexp.ll

InstCombine: Use SimplifyDemandedFPClass on fmul

Start trying to use SimplifyDemandedFPClass on instructions, starting
with fmul. This subsumes the old transform on multiply of 0. The
main change is the introduction of nnan/ninf. I do not think anywhere
was systematically trying to introduce fast math flags before, though
a few odd transforms would set them.

Previously we only called SimplifyDemandedFPClass on function returns
with nofpclass annotations. Start following the pattern of
SimplifyDemandedBits, where this will be called from relevant root
instructions.

I was wondering if this should go into InstCombineAggressive, but that
apparently does not make use of InstCombineInternal's worklist.
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+12-12llvm/test/Transforms/InstCombine/binop-itofp.ll
+10-10llvm/test/Transforms/InstCombine/pow-to-ldexp.ll
+9-7llvm/test/Transforms/InstCombine/fsqrtdiv-transform.ll
+2-13llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+13-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+4-4llvm/test/Transforms/InstCombine/pow_fp_int16.ll
+50-4714 files not shown
+79-7820 files

NetBSD/pkgsrc xjMmTcDdoc CHANGES-2026

   Updated www/py-soupsieve, devel/py-blessed
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NetBSD/pkgsrc WVLPoaRdevel/py-blessed distinfo Makefile

   py-blessed: updated to 1.27.0

   1.27
     * bugfix missing tests, bin, and docs folder in 1.26 release, :ghpull:`341`.

   1.26
     * introduced: :meth:`Terminal.detect_ambiguous_width`, :ghpull:`339`.
     * introduced: :meth:`Terminal.no_line_wrap`, context manager for attributes
       ``disable_line_wrap`` and ``enable_line_wrap`` :ghpull:`337`.
     * introduced: New methods :meth:`Terminal.color_hex` and :meth:`Terminal.on_color_hex` and bugfix
       parsing of uncommon responses in :meth:`Terminal.get_fgcolor` and bgcolor, :ghpull:`335`.
     * improved: performance of :meth:`Terminal.wrap`, :ghpull:`331` by :ghuser:`grayjk`.
     * improved: :meth:`Terminal.wrap` gets break_on_hyphen support, matching
       behavior of :func:`textwrap.wrap` by :ghuser:`ps06756` in :ghpull:`330`.
     * bugfix: for missing leading sequences in :meth:`Terminal.center`, :meth:`Terminal.wrap()`, add
       support for emojis containing Zero Width Joiner (`\u200D`) or Variation Selector-16 (`\uFE0F`),
       :ghpull:`338`
VersionDeltaFile
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1.13+2-2devel/py-blessed/Makefile
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NetBSD/pkgsrc X4vPjEfwww/py-soupsieve distinfo Makefile

   py-soupsieve: updated to 2.8.3

   2.8.3
   - **FIX**: Fix inefficient attribute pattern.

   2.8.2
   - **FIX**: Ensure custom selectors or namespace dictionaries reject non-string keys (@mundanevision20).
   - **FIX**: Fix handling of `:in-range` and `:out-of-range` with end of year weeks (@mundanevision20).
   - **FIX**: Fix a potential infinite loop in the pretty printing debug function (@mundanevision20).
VersionDeltaFile
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LLVM/project a01e091llvm/lib/Target/ARC ARCRegisterInfo.cpp

[NFC][ARC] Tidy Up RegState in ARC Backend (#177546)

This was missed in llvm/llvm-project#177090 because Github CI and my
local build don't have experimental targets enabled.

This is the only problematic RegState use in the experimental targets.
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+1-11 files

LLVM/project adc64c6clang/include/clang/Sema Sema.h, clang/lib/Sema SemaConcept.cpp SemaTemplateInstantiate.cpp

[Clang] Fix the normalization of fold constraints (#177531)

Fold constraints can contain packs expanded from different locations.
For `C<Ps...>`, where the ellipsis immediately follows the argument, the
pack should be expanded in place regardless of the fold expression. For
`C<Ps> && ...`, the fold expression itself is responsible for expanding
Ps.

Previously, both kinds of packs were expanded by the fold expression,
which broke assumptions within concept caching. This patch fixes that by
preserving PackExpansionTypes for the first kind of pack while rewriting
them to non-packs for the second kind.

This patch also removes an unused function and performs some cleanup of
the evaluation contexts. Hopefully it is viable for backporting.

No release note, as this issue was a regression.

Fixes https://github.com/llvm/llvm-project/issues/177245
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+12-30clang/lib/Sema/SemaTemplateInstantiate.cpp
+16-0clang/test/SemaCXX/cxx2c-fold-exprs.cpp
+1-11clang/include/clang/Sema/Sema.h
+1-1clang/lib/Sema/TreeTransform.h
+119-955 files

LLVM/project 11ba240clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-load-monitor.cl

Revert to old name
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+24-24clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
+21-21clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
+20-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+18-18clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+8-8llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+133-1339 files not shown
+173-17915 files

LLVM/project fe29ae0clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/lib/Sema SemaAMDGPU.cpp

[AMDGPU][GFX12.5] Reimplement monitor load as an atomic operation

Load monitor operations make more sense as atomic operations, as
non-atomic operations cannot be used for inter-thread communication w/o
additional synchronization.
The previous built-in made it work because one could just override the CPol
bits, but that bypasses the memory model and forces the user to learn about
ISA bits encoding.

Making load monitor an atomic operation has a couple of advantages. First,
the memory model foundation for it is stronger. We just lean on the existing
rules for atomic operations. Second, the CPol bits are abstracted away from
the user, which avoids leaking ISA details into the API.

This patch also adds supporting memory model and intrinsics documentation to
AMDGPUUsage.

Solves SWDEV-516398.
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+90-18llvm/docs/AMDGPUUsage.rst
+58-28llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+51-24clang/lib/Sema/SemaAMDGPU.cpp
+31-24clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+24-24clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
+327-17110 files not shown
+450-20816 files

LLVM/project 7119dccclang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-load-monitor.cl

Revert to old name
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+24-24clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
+21-21clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
+20-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+18-18clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+8-8llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+133-1339 files not shown
+173-17915 files

OPNSense/core e786aafsrc/opnsense/mvc/app/models/OPNsense/Base/FieldTypes ProtocolField.php

any is very special
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LLVM/project a648128clang/bindings/python/clang cindex.py, clang/bindings/python/tests/cindex test_code_completion.py test_enums.py

[libclang/python] Add CompletionChunkKind enum and deprecate old CompletionChunk.Kind (#176631)

This adresses point 1 from
https://github.com/llvm/llvm-project/issues/156680.
Since step 4 is already completed, `CompletionChunk.Kind` becomes unused
in this PR, so it is removed.
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+42-2clang/bindings/python/tests/cindex/test_code_completion.py
+8-1clang/docs/ReleaseNotes.rst
+2-0clang/bindings/python/tests/cindex/test_enums.py
+111-564 files

OPNSense/core 34cc30fsrc/opnsense/mvc/app/models/OPNsense/Base/FieldTypes ProtocolField.php

another
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+2-11 files

OPNSense/core f3f36besrc/opnsense/mvc/app/models/OPNsense/Base/FieldTypes ProtocolField.php

any is in there twice when not required, also uppercase
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LLVM/project e85bbd0llvm/lib/Target/AMDGPU AMDGPUSubtarget.cpp, llvm/test/CodeGen/AMDGPU waves-per-eu-hints-lower-occupancy-target.ll default-flat-work-group-size-overrides-waves-per-eu.ll

Revert "[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range" (#177544)

Reverts llvm/llvm-project#168358

Buildbot failure as commented in original PR.
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+61-0llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll
+14-20llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+12-13llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
+0-12llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
+2-2llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
+89-1311 files not shown
+90-1347 files

LLVM/project f1eb1f2llvm/test/tools/llvm-exegesis/AArch64 debug-gen-asm.s

[llvm-exegesis] Add -mtriple to AArch64 test (#177485)

Similar to https://github.com/llvm/llvm-project/pull/148968

(cherry picked from commit 12b3a9f52e76611b3d3ceb746559d2c384b2565e)
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+2-21 files

OPNSense/core e6a583asrc/opnsense/mvc/app/models/OPNsense/Base/FieldTypes BaseField.php ProtocolField.php

change inheritance
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+2-22 files

LLVM/project 2d62af8bolt/test lit.local.cfg, bolt/test/X86 lit.local.cfg

[NFCI][bolt][test] Enable AT&T syntax generally (#172355)

Having it in the X86 subdirectory only affects tests in that directory.
That's however not sufficient as for example runtime/X86/pie-exceptions-split.test is affected but
isn't located in the X86 directory.
This essentially fixes the fix for the original commit by guarding it properly for when the X86
target has been built and the flag is recognized.

Fixes: 6c48fbc1dcfbd44a47f126f21e575340b67aac06
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LLVM/project 84b2f12llvm/docs ReleaseNotes.md, llvm/include/llvm/MC MCStreamer.h

[MC][X86/M68k] Emit syntax directive for AT&T (#167234)

This eases interoperability by making it explicit in emitted assembly code which syntax is used.
Refactored to remove X86-specific directives and logic from the generic MC(Asm)Streamer.

Motivated by building LLVM with `-mllvm -x86-asm-syntax=intel` (i.e. a global preference for Intel
syntax). A Bolt test (`runtime/X86/fdata-escape-chars.ll`) was using `llc` to compile to assembly
and then assembling with `clang`. The specific option causes Clang to assume Intel syntax but only
for assembly and not inline assembly.
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+7-0llvm/test/CodeGen/X86/asm-dialect-directive.ll
+5-1llvm/lib/Target/X86/X86AsmPrinter.cpp
+4-0llvm/docs/ReleaseNotes.md
+0-4llvm/lib/Target/M68k/M68kAsmPrinter.cpp
+1-1llvm/include/llvm/MC/MCStreamer.h
+23-153 files not shown
+25-179 files

OpenBSD/ports wlFDpYrnet/mcast-proxy Makefile distinfo

   Update mcast-proxy to HEAD

   - Router Alert added to MLD and IGMP queries
   - IGMP checksum fix and added bounds checks
   - MLDv1 queries aligned with RFC 2710 (reference added)
   - MLD upstream filtering aligned with IGMP; fixes for MLD unregistration
     and IPv6 address tracking
   - Safety/cleanup: socket validity checks, default IGMP switch case,
     restricted file-local visibility, moved local prototypes

   Tested by Joel Knight.

   OK Paul de Weerd (MAINTAINER)
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1.7+2-2net/mcast-proxy/distinfo
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OPNSense/core ff0f692src/opnsense/mvc/app/models/OPNsense/Base/FieldTypes BaseField.php

fix
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+1-11 files

OpenBSD/src 410YmTyregress/lib/libcrypto/bn bn_ffdh.c

   bn_ffdh: unifdef HAVE_SCAPY_SPECIAL
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NetBSD/pkgsrc sADu4m1textproc/television Makefile

   television: remove outdated comment
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+1-51 files

NetBSD/pkgsrc MaRemXwdoc CHANGES-2026

   doc: Updated textproc/rumdl to 0.0.224
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+2-11 files

OpenBSD/src pJ3Zoeulib/libcrypto/dh dh_check.c

   DH_check: teach this DoS vector about RFC 7919 primes

   ok beck
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+6-11 files

OpenBSD/src UBezA0fregress/lib/libcrypto/bn bn_ffdh.c

   bn_ffdh: unifdef HAVE_RFC7919_PRIMES
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NetBSD/pkgsrc HHtbMX4textproc/rumdl distinfo Makefile

   textproc/rumdl: update to 0.0.224

   ## [0.0.224] - 2026-01-22

   ### Added

   - **GitHub Action: `fail-on-error` and `output-file` inputs** ([#324](https://github.com/rvben/rumdl/issues/324), [#325](https://github.com/rvben/rumdl/issues/325))
     - `fail-on-error`: Control whether the workflow fails on violations (default: `true`)
     - `output-file`: Write lint results to a file for use in subsequent steps

   - **LSP: `source.fixAll.rumdl` code action for fix-on-save**
     - Enables VS Code's "Fix All on Save" feature for rumdl
     - Configure with `editor.codeActionsOnSave: { "source.fixAll.rumdl": "explicit" }`

   ## [0.0.223] - 2026-01-21

   ### Added

   - **MD060: `column-align` option for table cell text alignment** ([#317](https://github.com/rvben/rumdl/issues/317))

    [24 lines not shown]
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