LLVM/project 980c9bbclang/test/CodeGen/RISCV builtin-cpu-is.c, clang/test/Driver riscv-cpus.c

[RISCV] Remove VeyronV1 processor definition (#220623)

Processor no longer exists.
DeltaFile
+0-39llvm/lib/Target/RISCV/RISCVProcessors.td
+0-25clang/test/Driver/riscv-cpus.c
+1-19clang/test/CodeGen/RISCV/builtin-cpu-is.c
+0-4llvm/lib/Target/RISCV/RISCVFeatures.td
+0-2clang/test/Misc/target-invalid-cpu-note/riscv.c
+0-1llvm/test/CodeGen/RISCV/features-info.ll
+1-902 files not shown
+2-918 files

LLVM/project db70744llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-mul-parts-acc-fold.ll

[RISCV][P-ext] Fold an add of a multiply-parts product into the accumulate form (#222748)

An add of a multiply-parts product selects the accumulating instruction, so
that a loop written with `sum += __riscv_mul_h00_i32(a, b)` gets `macc.h00`
rather than a separate multiply and add.

Rewriting the add before type legalization keeps the shapes whose result is
illegal, so the existing accumulate lowering covers all of them.
DeltaFile
+429-0llvm/test/CodeGen/RISCV/rvp-mul-parts-acc-fold.ll
+67-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+496-02 files

LLVM/project 4267061llvm/lib/Target/AMDGPU AMDGPUUniformIntrinsicCombine.cpp, llvm/test/CodeGen/AMDGPU amdgpu-uniform-intrinsic-combine-analysis-invalidation.ll

[AMDGPU] Invalidate uniformity info after intrinsic combine (#222357)

The uniform intrinsic combine pass changed IR while preserving
uniformity information. Its result keeps references to cycle
information. Those references could be invalidated and later accessed
by another pass.

Invalidate uniformity information after a change. Before erasing an
instruction, remove it from the analysis state used by the pass. Also
report each erasure as a change so invalidation always runs.
DeltaFile
+108-0llvm/test/CodeGen/AMDGPU/amdgpu-uniform-intrinsic-combine-analysis-invalidation.ll
+11-7llvm/lib/Target/AMDGPU/AMDGPUUniformIntrinsicCombine.cpp
+119-72 files

LLVM/project 5f00f13llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Support KnownFPClass.cpp

[KnownFPClass] Refactor direct access to KnownFPClasses [NFC] (#220315)

Part of https://github.com/llvm/llvm-project/issues/217072

Follow up to https://github.com/llvm/llvm-project/pull/218514

Replaces direct uses of the `KnownFPClasses` field with getters/setters.
DeltaFile
+79-77llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
+48-38llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+36-32llvm/include/llvm/Support/KnownFPClass.h
+22-21llvm/lib/Support/KnownFPClass.cpp
+18-17llvm/unittests/Analysis/ValueTrackingTest.cpp
+15-15llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+218-2008 files not shown
+261-24214 files

FreeBSD/ports c253363x11/babl Makefile

x11/babl: Fix build

meson.build:1:0: ERROR: Value "false" (of type "string") for option "gi-docgen" is not one of the choices. Possible choices are (as string): "enabled", "disabled", "auto".

Approved by:    blanket (fix build)
Fixes:          90274e2e7fe3 (update to 0.1.128 release)
Sponsored by:   UNIS Labs
DeltaFile
+2-2x11/babl/Makefile
+2-21 files

FreeBSD/ports ed659c9mail/py-resend Makefile distinfo

mail/py-resend: Update to 2.44.0

Changelog: https://github.com/resend/resend-python/releases/tag/v2.44.0

Reported by:    Repology
DeltaFile
+3-3mail/py-resend/distinfo
+1-1mail/py-resend/Makefile
+4-42 files

LLVM/project cd7b268llvm/tools/llvm-offload-binary llvm-offload-binary.cpp

unnecessary
DeltaFile
+1-1llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp
+1-11 files

LLVM/project ef35765llvm/lib/Object OffloadBinary.cpp

fix alignment
DeltaFile
+3-2llvm/lib/Object/OffloadBinary.cpp
+3-21 files

FreeBSD/ports 66ac7d7databases/py-redisvl Makefile distinfo

databases/py-redisvl: Update to 0.27.2

Changelog: https://github.com/redis/redis-vl-python/releases/tag/v0.27.2

Reported by:    Repology
DeltaFile
+3-3databases/py-redisvl/distinfo
+1-1databases/py-redisvl/Makefile
+4-42 files

LLVM/project cbd89f8llvm/lib/Target/AArch64 AArch64ConditionalCompares.cpp, llvm/test/CodeGen/AArch64 cmpbr-ccmp.ll cmpbr-ccmp.mir

[AArch64] Form CCMP for CBB and CBH

AArch64ConditionalCompares forms CMP/CCMP chains to transform patterns
such as

                 Head                        Head
                 / |                         CmpBB
                /  |                         / |
               |  CmpBB        =>           /  |
               |  / |                    Tail  |
               | /  |                      |   |
              Tail  |                      |   |
                |   |                      |   |
               ... ...                    ... ...

where Head is terminated by a conditional branch and CmpBB contains
a cmp + conditional branch.

We usually try to split any fused conditional branches to be able to

    [8 lines not shown]
DeltaFile
+406-0llvm/test/CodeGen/AArch64/cmpbr-ccmp.mir
+232-0llvm/test/CodeGen/AArch64/cmpbr-ccmp.ll
+38-2llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
+676-23 files

FreeBSD/ports 516242dwww/py-sherlock-project distinfo Makefile

www/py-sherlock-project: Update to 0.16.2

Changelog: https://github.com/sherlock-project/sherlock/compare/v0.16.0...v0.16.2

Reported by:    Repology
DeltaFile
+3-3www/py-sherlock-project/distinfo
+3-3www/py-sherlock-project/Makefile
+6-62 files

LLVM/project 821ff7cllvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange no-partially-perfect-subnest.ll preserve-sibling-order.ll

[LoopInterchange] Supported partially-perfect Loop Nests (#199511)

In the current implementation when the outermost loop contains sibling
sub-loops (i.e. multiple independent loop nests at the same depth), the
pass silently skips the entire loop nest without attempting to
interchange any of the valid sub-nests (See Below Example).

Example:
```
for(int i=0; i<n; i++){  // Loop 1
    for(int j=0; j<m; j++){  // Loop 2
         for(int r=0; r<m; r++){  // Loop 3
         // Do something
         }
    }
    for(int k=0; k<p; k++){  // Loop 4
        for(int l=0; l<p; l++){  // Loop 5
            //Access A[l][k]
        }

    [7 lines not shown]
DeltaFile
+126-0llvm/test/Transforms/LoopInterchange/missed-outer-prefix-subnest.ll
+119-0llvm/test/Transforms/LoopInterchange/confused-dependence-subnest.ll
+111-0llvm/test/Transforms/LoopInterchange/dependency-matrix-padding.ll
+69-26llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+72-0llvm/test/Transforms/LoopInterchange/preserve-sibling-order.ll
+63-0llvm/test/Transforms/LoopInterchange/no-partially-perfect-subnest.ll
+560-263 files not shown
+622-579 files

LLVM/project 9526701llvm/docs/GlobalISel GenericOpcode.md, llvm/include/llvm/Target GenericOpcodes.td

[RISCV][GlobalISel] Add G_CLMULH support (#221686)

Add G_CLMULH to represent the high half of a carry-less multiplication
in generic Machine IR.

Translate llvm.riscv.clmulh to G_CLMULH and mark it legal for native
XLEN scalar types when Zbkc is available. Reuse the existing
SelectionDAG pattern to select the RISC-V CLMULH instruction.
DeltaFile
+60-0llvm/test/CodeGen/RISCV/GlobalISel/clmul-rv64.ll
+28-0llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+15-0llvm/test/CodeGen/RISCV/GlobalISel/clmul-rv32.ll
+10-0llvm/docs/GlobalISel/GenericOpcode.md
+8-0llvm/include/llvm/Target/GenericOpcodes.td
+2-2llvm/test/TableGen/get-named-operand-idx.td
+123-24 files not shown
+133-210 files

NetBSD/src 4EnPXgbsys/arch/arm/dts imx8mq-phanbell.dts

   Enable sdhc on Google i.MX8MQ Phanbell
VersionDeltaFile
1.1+36-0sys/arch/arm/dts/imx8mq-phanbell.dts
+36-01 files

NetBSD/pkgsrc NnkgsKhdoc CHANGES-2026

   doc: Updated wm/enlightenment16 to 1.0.32
VersionDeltaFile
1.6005+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc MNuCM9Dwm/enlightenment16 Makefile distinfo

   enlightenment16: update to 1.0.32

   e16 v1.0.32 - 2026-09-03
   ------------------------
   - 1.0.32
   - snaps: Fix potential crash in title match feature
   - Spec file: Add a %conf section
   - Update po
   - French translation update (Philippe J. Guillaumie)
   - De-iconify windows demanding attention
   - edge: Re-enable button press/release events on top/bottom edge windows
   - .gitignore: Add missing item
   - autofoo: Fix configure.ac for gettext v1.0
   - menus: Remove definitions for horizontal menus
   - manus: Remove broken support for horizontal menus
   - backgrounds: Show progress bars when compositing is enabled
   - pagers: Forgot cast
   - backgrounds: Tweak background scaling heuristics
   - backgrounds: Cosmetics

    [11 lines not shown]
VersionDeltaFile
1.21+4-4wm/enlightenment16/distinfo
1.48+2-3wm/enlightenment16/Makefile
+6-72 files

LLVM/project fd7eac5lld/ELF/Arch AMDGPU.cpp

[AMDGPU][lld] Remove "using namespace llvm" from AMDGPU.cpp (#222818)

AMDGPU class in anonymous namespace collides with llvm::AMDGPU, causing
an error with MSVC.
DeltaFile
+0-1lld/ELF/Arch/AMDGPU.cpp
+0-11 files

LLVM/project c410bbfllvm/test/MC/LoongArch/Relocations sub-expr.s

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+24-2llvm/test/MC/LoongArch/Relocations/sub-expr.s
+24-21 files

LLVM/project 7c3849aclang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-global-load-tr-w64.hip builtins-amdgcn-global-load-tr-w32.hip

[CIR][AMDGPU] Add support for AMDGCN global/DS load builtins (#220611)

Adds codegen support for AMDGCN global and DS load/read builtins with
transpose variants. These builtins are lowered to their corresponding
`llvm.amdgcn.*` intrinsics.
DeltaFile
+131-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250-load-tr.hip
+78-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx950-read-tr.hip
+43-22clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+60-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-global-load-tr-w32.hip
+59-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-global-load-tr-w64.hip
+371-225 files

FreeBSD/ports 8443f06misc/crush Makefile distinfo, misc/crush/files extra-patch-disable-command-blocking

misc/crush: Update to 0.93.1

Changelog: https://github.com/charmbracelet/crush/releases/tag/v0.93.1

Reported by:    GitHub (watch releases)
DeltaFile
+5-5misc/crush/distinfo
+2-3misc/crush/Makefile
+2-2misc/crush/files/extra-patch-disable-command-blocking
+9-103 files

NetBSD/src YqEEPIzsys/dev/acpi acpi_bat.c

   acpi_bat.c: add Surface Go 3 support

   This device uses a non-standard HID. Addresses PR kern/60709 from
   Ron Ben Aroya, who provided the patch.
VersionDeltaFile
1.124+3-2sys/dev/acpi/acpi_bat.c
+3-21 files

LLVM/project 81e4717clang/include/clang/ScalableStaticAnalysis/Analyses/PointerFlow PointerFlowPairs.h, clang/lib/ScalableStaticAnalysis/Analyses SSAFAnalysesCommon.h

[SSAF][PointerFlow] Factor out and make the pointer-flow matching reusable

The PointerFlowExtractor matches AST nodes representing pointer-flows
and converts them to entity-based data structures directly. This
commit divides this procedure into two steps: 1) match and represent
AST nodes as PointerFlowPairs; 2) convert PointerFlowPairs to
entity-based edges. Therefore, other SSAF tools may use
PointerFlowPairs.

The refactoring also improves coverage: it separates pointer-type
checking from structural matching, so structural matching alone now
discovers cases that were previously missed due to overly aggressive
type checking (e.g. a record-typed call argument or return value
initialized with a braced-init-list).

Along the way, this also fixes a bug for unnamed bit-fields.

First patch for
rdar://187125348
DeltaFile
+433-0clang/unittests/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowPairsTest.cpp
+300-0clang/lib/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowPairs.cpp
+67-232clang/lib/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowExtractor.cpp
+122-0clang/include/clang/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowPairs.h
+7-1clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
+1-0llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
+930-2333 files not shown
+933-2339 files

LLVM/project dc7fb83clang/include/clang/ScalableStaticAnalysis/Analyses/EntityPointerLevel EntityPointerLevel.h, clang/include/clang/ScalableStaticAnalysis/Analyses/PointerFlow PointerFlowPairs.h

[SSAF][PointerFlow] Drop unused TUSummaryExtractor param from translateDeclPointerLevel

TUSummaryExtractor is only needed to mint EntityIds when building an
EntityPointerLevel; translateDeclPointerLevel just walks the Expr and
returns raw DeclPointerLevels, so it never touched Extractor.

This is the second patch the radar below depends on:
rdar://187125348
DeltaFile
+24-20clang/lib/ScalableStaticAnalysis/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
+2-3clang/include/clang/ScalableStaticAnalysis/Analyses/EntityPointerLevel/EntityPointerLevel.h
+2-2clang/lib/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowExtractor.cpp
+2-0clang/include/clang/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowPairs.h
+30-254 files

LLVM/project 07d6729llvm/lib/Target/Mips MipsSEInstrInfo.cpp MipsScheduleP5600.td, llvm/test/CodeGen/Mips mips1-not-support-ldc1-sdc1.ll

[Mips] Fix buildbot failure of MIPS I double store using SWC1 (#221912)

Expand ExtractElementF64_FPR to FMOV_S instead of MFC1 to avoid
incorrect integer store.

Fix x86_64-expensive-checks compile error as for pr
https://github.com/llvm/llvm-project/pull/209362.

Fix #62190.
DeltaFile
+4-8llvm/test/CodeGen/Mips/mips1-not-support-ldc1-sdc1.ll
+6-5llvm/lib/Target/Mips/MipsInstrFPU.td
+1-1llvm/lib/Target/Mips/MipsScheduleP5600.td
+1-1llvm/lib/Target/Mips/MipsScheduleGeneric.td
+0-1llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+12-165 files

LLVM/project e152f54llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port f896082fb9ea (#222824)
DeltaFile
+1-0llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+1-01 files

FreeNAS/freenas 50b45a8src/freenas/etc/logrotate.d truenas_s3, src/middlewared/middlewared/alembic/versions/26.0 2026-09-09_21-00_s3_service_name.py

NAS-143516 / 26.0.0 / rename the s3 service from truenas_s3 to s3 (by anodos325) (#19683)

service.query reported it as truenas_s3, the daemon's name rather than
the protocol's. The services_services row has to move with
ServiceInterface.name or nothing resolves it, so a migration renames it;
ServiceWriteRole is keyed by the name upper-cased and moves too.

Root is refused as an access key account and as a bucket owner. Both run
as uid 0, which no bucket grant and no file mode restrains.

The daemon's own messages get /var/log/truenas_s3.log, filtered on the
journal identifier it writes, s3d, and rotated the way scst and
truenas-discoveryd are. Its audit records are a separate path and are
untouched.

The systemd unit, the etc group and the tables keep the truenas_s3 name:
they are the daemon's, and nothing outside middleware names them.

Original PR: https://github.com/truenas/middleware/pull/19672

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+34-0src/middlewared/middlewared/alembic/versions/26.0/2026-09-09_21-00_s3_service_name.py
+20-1tests/api2/test_s3_bucket.py
+12-2src/middlewared/middlewared/plugins/truenas_s3/bucket_crud.py
+12-0src/freenas/etc/logrotate.d/truenas_s3
+11-0tests/api2/test_s3_accesskey.py
+11-0src/middlewared/middlewared/plugins/truenas_s3/accesskey_crud.py
+100-39 files not shown
+132-2015 files

OpenBSD/src V4lFtvgsys/dev/pci/drm drm_drv.c drm_linux.c, sys/dev/pci/drm/include/drm drm_device.h

   correct dma_tag_lookup() loop

   drm_cd.cd_ndevs[] has pointers to drm_softc not drm_device

   Currently, dma_tag_lookup() is only used by the apldcp/apldrm drivers.
   At the start of the softc for both of those is struct platform_device.
   If the loop doesn't match the the function argument is cast to
   struct platform_device *, so the problem was not noticed.

   discussed with kettenis@ and apldcp/apldrm tested on m1 mac mini
VersionDeltaFile
1.146+5-5sys/dev/pci/drm/drm_linux.c
1.207+0-6sys/dev/pci/drm/drm_drv.c
1.13+6-0sys/dev/pci/drm/include/drm/drm_device.h
+11-113 files

FreeBSD/ports 5a3985fdevel/p5-Test-Pod-Links distinfo Makefile

devel/p5-Test-Pod-Links: Update 0.003 => 0.004

Changelog:
https://metacpan.org/release/SKIRMESS/Test-Pod-Links-0.004/source/Changes

- Respect license change.
- Fix antipattern "BUILD_DEPENDS=RUN_DEPENDS".

PR:             298380 283227
Sponsored by:   UNIS Labs (vvd, commit patch)
DeltaFile
+7-5devel/p5-Test-Pod-Links/Makefile
+3-3devel/p5-Test-Pod-Links/distinfo
+10-82 files

LLVM/project 96a51a0mlir/include/mlir/Dialect/AMDGPU/IR AMDGPUDialect.h AMDGPUDialectDecl.h, mlir/lib RegisterAllDialects.cpp

[mlir][AMDGPU] Split the dialect declaration (NFC)

Introduce a self-contained dialect declaration so RegisterAllDialects does not
need the generated AMDGPU operation umbrella.

Across five controlled rebuilds of the affected TU, median instructions fell
from 71.757B to 70.331B (-1.987%) and median wall time fell from 11.01s to
10.77s (-2.180%).

Assisted-by: Codex
DeltaFile
+16-0mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUDialectDecl.h
+1-2mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h
+1-1mlir/lib/RegisterAllDialects.cpp
+18-33 files

LLVM/project 93a5d4fmlir/include/mlir/Dialect/Func/IR FuncOps.h FuncDialect.h, mlir/test/lib/Dialect/GPU TestGpuRewrite.cpp

[mlir][Func] Split the dialect declaration (NFC)

Introduce a self-contained dialect declaration and use it in ten configured
consumers that do not need the generated operation umbrella.

Across three controlled -j16 rebuilds of the affected TUs, median instructions
fell from 224.883B to 220.787B (-1.821%) and median wall time fell from 8.44s
to 8.31s (-1.540%).

Assisted-by: Codex
DeltaFile
+16-0mlir/include/mlir/Dialect/Func/IR/FuncDialect.h
+1-3mlir/include/mlir/Dialect/Func/IR/FuncOps.h
+1-1mlir/unittests/Dialect/Transform/BuildOnlyExtensionTest.cpp
+1-1mlir/unittests/Dialect/OpenACC/OpenACCUtilsTypeTest.cpp
+1-1mlir/unittests/Dialect/Linalg/InferConvolutionDimsTest.cpp
+1-1mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
+21-77 files not shown
+28-1413 files