LLVM/project 0d79745llvm/lib/Target/X86 X86ISelDAGToDAG.cpp, llvm/test/CodeGen/X86 is_fpclass.ll cmp.ll

[X86] Emit ADD instead of SHL by 1 when shrinking TEST with a mask (#217508)

The immediate-TEST shrink rewrites (and x, 0x7fffffffffffffff) == 0 into
SHL64ri $1 + TEST64rr, expecting the redundant TEST to be "subsequently
eliminated" (per the comment). For shift amounts 1-3 it never is:
isDefConvertible() rejects those SHLs so that they stay convertible to
LEA, and the dead TEST survives into final binaries.

Emit ADD64rr x, x instead when the shift amount is 1. Doubling is value-
and ZF-identical to the shift at the same encoding length, executes on
more ports, and ADDrr is def-convertible, so the peephole really does
fold the TEST away, leaving add+jcc/setcc instead of shl+test+jcc/setcc.

The shape is common: it is Rust libstd's panic-counter fast path
(GLOBAL_PANIC_COUNT & ~(1 << 63) == 0, inlined at every
std::thread::panicking() check -- 249 copies in uutils coreutils) and
LLVM's own is_fpclass zero-class lowering, as the is_fpclass.ll diff
shows.


    [7 lines not shown]
DeltaFile
+101-0llvm/test/CodeGen/X86/cmp.ll
+15-1llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+2-4llvm/test/CodeGen/X86/is_fpclass.ll
+118-53 files

LLVM/project e803e57clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

[RISCV][P-ext] Support Packed "Q-format" Multiply Parts Accumulate Intrinsics(#217918)
DeltaFile
+388-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+177-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+169-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+126-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+88-4llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+87-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+1,035-46 files not shown
+1,210-912 files

LLVM/project aa09790mlir/lib/Dialect/SparseTensor/Transforms Sparsification.cpp SparseReinterpretMap.cpp, mlir/lib/Dialect/SparseTensor/Transforms/Utils CodegenUtils.cpp

[mlir][SparseTensor] Use split discardable/inherent attribute APIs (#218904)

Migrate SparseTensor IR, lowering, code generation, and loop emission to
explicit discardable or operation-specific attribute access.

Assisted-by: Codex
DeltaFile
+5-4mlir/lib/Dialect/SparseTensor/Transforms/SparseVectorization.cpp
+5-4mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
+4-3mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
+2-2mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
+2-2mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
+2-2mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
+20-172 files not shown
+23-198 files

LLVM/project 7b6eb69mlir/docs SymbolsAndSymbolTables.md

address comments
DeltaFile
+3-2mlir/docs/SymbolsAndSymbolTables.md
+3-21 files

LLVM/project 20ad451mlir/lib/Conversion/FuncToEmitC FuncToEmitC.cpp, mlir/lib/Conversion/FuncToLLVM FuncToLLVM.cpp

[mlir][Func][Async][EmitC] Use split discardable/inherent attribute APIs (#218905)

Use operation-specific accessors and explicit discardable attribute APIs
in the Func, Async, and EmitC dialects and their associated conversions.

Assisted-by: Codex
DeltaFile
+25-19mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
+16-5mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
+7-4mlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
+5-4mlir/lib/Dialect/EmitC/IR/EmitC.cpp
+4-4mlir/lib/Dialect/Func/IR/FuncOps.cpp
+4-3mlir/lib/Dialect/Async/IR/Async.cpp
+61-397 files not shown
+76-5213 files

LLVM/project a908adbllvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU cttz_zero_poison.ll ctlz_zero_poison.ll

[AMDGPU] Fix unsaturated add when moving 64-bit ctlz/cttz to the VALU (#216707)

The ffbh/ffbl add is saturated via a clamp modifier, but on gfx6/7/8 it
lowers to V_ADD_CO_U32_e32, which has no clamp operand, so
ctlz/cttz.i64(0, false) returns 31 instead of 64 there

ffbh/ffbl only produce 0..31 or -1, so uaddsat(x, 32) is just x | 32

Use V_OR_B32_e32 instead, which needs no clamp and works everywhere
DeltaFile
+484-8llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
+4-7llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+2-2llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
+2-2llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
+492-194 files

LLVM/project 2e32621mlir/include/mlir/Dialect/Shape/IR ShapeBase.td ShapeOps.td, mlir/test/Dialect/Shape ops.mlir invalid.mlir

[MLIR][Shape] Enable strict property assembly format (#218903)

Enable the strict properties assembly format mode for the Shape dialect.

Bind the broadcast diagnostic attribute directly. Keep its optional
clause unambiguous after variadic operands, and cover the custom and
rejected attr-dict spellings.

Assisted-by: Codex
DeltaFile
+10-1mlir/test/Dialect/Shape/ops.mlir
+10-1mlir/test/Dialect/Shape/invalid.mlir
+2-1mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
+1-0mlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
+23-34 files

OPNSense/core 0334d52src/opnsense/mvc/app/views/layout_partials form_input_tr.volt base_form.volt

mvc: advanced marker for form/dialog fields (#10795)

Add a marker for advanced options behind their respective field
name in order to better spot what was toggled.  In OpenVPN
the dialog extends beyond the screen size so having a visual
clue helps navigate the additional settings.
DeltaFile
+7-3src/opnsense/mvc/app/views/layout_partials/base_form.volt
+7-3src/opnsense/mvc/app/views/layout_partials/base_dialog.volt
+5-2src/opnsense/mvc/app/views/layout_partials/form_input_tr.volt
+19-83 files

HardenedBSD/src eca9c21sys/arm64/iommu smmu.c, sys/arm64/vmm/io vgic.c vgic_internal.h

Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/pledge
DeltaFile
+13-177sys/arm64/vmm/io/vgic_v3.c
+132-0sys/arm64/vmm/io/vgic_internal.h
+78-1sys/arm64/vmm/io/vgic.c
+1-1sys/arm64/iommu/smmu.c
+224-1794 files

HardenedBSD/src 893c2b9contrib/elftoolchain/libelftc libelftc_dem_gnu2.c, contrib/libucl/src ucl_util.c

Merge remote-tracking branch 'rad/hardened/15-stable/main' into hardened/15-stable/pledge
DeltaFile
+13-6usr.bin/rpcgen/rpc_svcout.c
+7-7usr.bin/mkimg/mkimg.c
+6-4contrib/mandoc/read.c
+4-3contrib/libucl/src/ucl_util.c
+2-3contrib/elftoolchain/libelftc/libelftc_dem_gnu2.c
+4-1sys/amd64/vmm/x86.c
+36-2410 files not shown
+49-3616 files

HardenedBSD/src 80f4602sys/arm64/iommu smmu.c, sys/arm64/vmm/io vgic.c vgic_internal.h

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+13-177sys/arm64/vmm/io/vgic_v3.c
+132-0sys/arm64/vmm/io/vgic_internal.h
+78-1sys/arm64/vmm/io/vgic.c
+1-1sys/arm64/iommu/smmu.c
+224-1794 files

HardenedBSD/src 160f743contrib/elftoolchain/libelftc libelftc_dem_gnu2.c, contrib/libucl/src ucl_util.c

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main
DeltaFile
+13-6usr.bin/rpcgen/rpc_svcout.c
+7-7usr.bin/mkimg/mkimg.c
+6-4contrib/mandoc/read.c
+4-3contrib/libucl/src/ucl_util.c
+2-3contrib/elftoolchain/libelftc/libelftc_dem_gnu2.c
+4-1sys/amd64/vmm/x86.c
+36-2410 files not shown
+49-3616 files

NetBSD/pkgsrc-wip 6700907. Makefile

wip: Add py-datamodel-code-generator
DeltaFile
+1-0Makefile
+1-01 files

HardenedBSD/ports dffab10databases/cassandra-cpp-driver/files patch-e5a486ac52b99ae74d40e285b4438252fcf3b07a, misc/qwen-code/files package-lock.json

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+702-0net/samba424/files/patch-source3_modules_vfs__freebsd.c
+622-0net/samba424/pkg-plist.python
+505-0databases/cassandra-cpp-driver/files/patch-e5a486ac52b99ae74d40e285b4438252fcf3b07a
+483-0net/samba424/pkg-plist
+458-0net/samba424/Makefile
+180-140misc/qwen-code/files/package-lock.json
+2,950-140158 files not shown
+6,778-802164 files

NetBSD/pkgsrc-wip 63cfbe5py-datamodel-code-generator ALTERNATIVES DESCR

py-datamodel-code-generator: Import py-datamodel_code_generator-0.75.1 as wip/py-datamodel-code-generator

Generate Pydantic v2 models, dataclasses, TypedDict, and msgspec.Struct
from OpenAPI, JSON Schema, GraphQL, Avro, Protobuf, and raw
JSON/YAML/CSV.
DeltaFile
+391-0py-datamodel-code-generator/PLIST
+33-0py-datamodel-code-generator/Makefile
+5-0py-datamodel-code-generator/distinfo
+3-0py-datamodel-code-generator/DESCR
+1-0py-datamodel-code-generator/ALTERNATIVES
+433-05 files

NetBSD/pkgsrc-wip 2eabd25. Makefile

wip: Add py-genson
DeltaFile
+1-0Makefile
+1-01 files

LLVM/project 776df1emlir/docs SymbolsAndSymbolTables.md, mlir/include/mlir/IR SymbolTable.h SymbolInterfaces.td

[mlir][IR] Fix symbol table visibility API
DeltaFile
+51-40mlir/include/mlir/IR/SymbolInterfaces.td
+52-32mlir/lib/IR/SymbolTable.cpp
+11-5mlir/include/mlir/IR/SymbolTable.h
+7-4mlir/docs/SymbolsAndSymbolTables.md
+4-3mlir/lib/Interfaces/FunctionImplementation.cpp
+7-0mlir/unittests/IR/SymbolTableTest.cpp
+132-844 files not shown
+142-9210 files

LLVM/project 1341c9dclang/docs/analyzer checkers.md

Update clang/docs/analyzer/checkers.md

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
DeltaFile
+1-2clang/docs/analyzer/checkers.md
+1-21 files

LLVM/project 8d735a0mlir/lib/Conversion/ArithToLLVM ArithToLLVM.cpp, mlir/lib/Dialect/LLVMIR/IR LLVMDialect.cpp

[mlir][LLVM] Verify that constant attribute and result types match

`llvm.mlir.constant` only checked that the kind of the value attribute suits
the kind of the result type, never that the types themselves agree. All of the
following verified:

  %0 = llvm.mlir.constant(1 : index) : i64
  %1 = llvm.mlir.constant(1 : i8) : i16
  %2 = llvm.mlir.constant(dense<1> : vector<4xi32>) : vector<4xi64>

Translation ignores the attribute type and uses the result type, so the
attribute type was effectively decorative for integers, and passes that read it
back could observe a type that has nothing to do with the value.

Require exact type equality for integer attributes and exact element type
equality for integer elements attributes, mirroring the `AllTypesMatch`
constraint `arith.constant` gets from ODS. The op cannot use that trait itself
because `value` is an `AnyAttr` that also holds `StringAttr` and `ArrayAttr`.
The element type check is also run on the scalable vector path, which

    [11 lines not shown]
DeltaFile
+56-0mlir/test/Dialect/LLVMIR/invalid.mlir
+42-11mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+12-12mlir/test/Dialect/LLVMIR/roundtrip.mlir
+23-0mlir/test/Conversion/ArithToLLVM/constant-index-bitwidth.mlir
+11-4mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
+7-7mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
+151-3414 files not shown
+180-5920 files

NetBSD/pkgsrc-wip 4e52002py-genson distinfo DESCR

py-genson: Import py-genson-1.4.0 as wip/py-genson

GenSON is a powerful, user-friendly JSON Schema generator built in
Python.

GenSON's core function is to take JSON objects and generate schemas
that describe them, but it is unique in its ability to merge schemas.
It was originally built to describe the common structure of a large
number of JSON objects, and it uses its merging ability to generate a
single schema from any number of JSON objects and/or schemas.
DeltaFile
+43-0py-genson/PLIST
+18-0py-genson/Makefile
+8-0py-genson/DESCR
+5-0py-genson/distinfo
+74-04 files

NetBSD/pkgsrc-wip 03423e7oras TODO

oras: Add reference to CVE-2026-55588
DeltaFile
+2-0oras/TODO
+2-01 files

FreeBSD/ports ca68146deskutils/podman-desktop Makefile, editors/vscode Makefile

*/*: Bump port revision after electron42 update (d346072f67be)
DeltaFile
+1-1net-im/signal-desktop/Makefile
+1-1net-im/deltachat-desktop/Makefile
+1-1graphics/drawio/Makefile
+1-1deskutils/podman-desktop/Makefile
+1-0net-im/teams/Makefile
+1-0editors/vscode/Makefile
+6-46 files

HardenedBSD/ports ca68146deskutils/podman-desktop Makefile, editors/vscode Makefile

*/*: Bump port revision after electron42 update (d346072f67be)
DeltaFile
+1-1net-im/signal-desktop/Makefile
+1-1net-im/deltachat-desktop/Makefile
+1-1graphics/drawio/Makefile
+1-1deskutils/podman-desktop/Makefile
+1-0net-im/teams/Makefile
+1-0editors/vscode/Makefile
+6-46 files

FreeBSD/ports d346072devel/electron42/files patch-electron_shell_common_node__bindings__linux.cc patch-electron_shell_browser_api_electron__api__web__contents.cc

devel/electron42: Update to 42.10.0

Changelog: https://github.com/electron/electron/releases/tag/v42.10.0

Reported by:    GitHub (watch releases)
DeltaFile
+29-20devel/electron42/files/patch-electron_spec_api-app-spec.ts
+21-21devel/electron42/files/patch-electron_shell_browser_native__window__views.cc
+16-17devel/electron42/files/patch-electron_shell_browser_electron__browser__main__parts.cc
+10-10devel/electron42/files/patch-electron_spec_api-browser-window-spec.ts
+8-8devel/electron42/files/patch-electron_shell_browser_api_electron__api__web__contents.cc
+8-7devel/electron42/files/patch-electron_shell_common_node__bindings__linux.cc
+92-8320 files not shown
+167-13126 files

HardenedBSD/ports d346072devel/electron42/files patch-electron_shell_common_node__bindings__linux.cc patch-electron_shell_browser_api_electron__api__web__contents.cc

devel/electron42: Update to 42.10.0

Changelog: https://github.com/electron/electron/releases/tag/v42.10.0

Reported by:    GitHub (watch releases)
DeltaFile
+29-20devel/electron42/files/patch-electron_spec_api-app-spec.ts
+21-21devel/electron42/files/patch-electron_shell_browser_native__window__views.cc
+16-17devel/electron42/files/patch-electron_shell_browser_electron__browser__main__parts.cc
+10-10devel/electron42/files/patch-electron_spec_api-browser-window-spec.ts
+8-8devel/electron42/files/patch-electron_shell_browser_api_electron__api__web__contents.cc
+8-7devel/electron42/files/patch-electron_shell_common_node__bindings__linux.cc
+92-8320 files not shown
+167-13126 files

LLVM/project 0181e05clang/docs/analyzer checkers.md

Explanation for suppressing the fp report.
DeltaFile
+3-1clang/docs/analyzer/checkers.md
+3-11 files

LLVM/project 6f21734libcxx/utils/ci/lnt dispatch-benchmarks

[libc++] Remove confusing summary (#218897)

It doesn't add much more than the preceding output.
DeltaFile
+1-9libcxx/utils/ci/lnt/dispatch-benchmarks
+1-91 files

FreeBSD/ports ca65a02. UPDATING

UPDATING: Belatedly document sddm keyboard layout changes

PR:             296696
Reported by:    mikael
DeltaFile
+13-0UPDATING
+13-01 files

HardenedBSD/ports ca65a02. UPDATING

UPDATING: Belatedly document sddm keyboard layout changes

PR:             296696
Reported by:    mikael
DeltaFile
+13-0UPDATING
+13-01 files

LLVM/project 7d62df8llvm/include/llvm/Transforms/Utils LoopUtils.h, llvm/lib/Transforms/Utils LoopUtils.cpp

Fixups
DeltaFile
+128-181llvm/test/Transforms/LoopVectorize/compress-idioms.ll
+40-9llvm/test/Transforms/LoopVectorize/compress-idioms-negative-tests.ll
+16-20llvm/test/Transforms/LoopVectorize/AArch64/compress-idioms.ll
+12-16llvm/test/Transforms/LoopVectorize/VPlan/compress-idioms.ll
+9-1llvm/lib/Transforms/Utils/LoopUtils.cpp
+4-3llvm/include/llvm/Transforms/Utils/LoopUtils.h
+209-2301 files not shown
+212-2337 files