LLVM/project 373e23ellvm/test/CodeGen/AMDGPU fix-sgpr-copies-f16-true16.mir

Merge update to new test case

Merge branch 'users/zGoldthorpe/wide-copies/precommit' into users/zGoldthorpe/wide-copies/materialise
DeltaFile
+7-9llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+7-91 files

FreeNAS/freenas a351f94src/middlewared/middlewared/plugins rsync.py, tests/api2 test_rsync_ssh_authentication.py

NAS-143926 / 26.0.0 / Fix nonstandard rsync SSH port handling

(cherry picked from commit 9d611a24869a01261280d9c8c3566bb5d6d30ce0)
DeltaFile
+150-1tests/api2/test_rsync_ssh_authentication.py
+12-5src/middlewared/middlewared/plugins/rsync.py
+162-62 files

LLVM/project 8afb2a0llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 splat-gather-subtree-root-order.ll

[SLP]Keep splat subtree load roots in memory order

The roots have no users and the gathers reuse their lanes by value, but
the group or reordering-pass order added a reorder shuffle and non-free
extracts, so the profitable vector load was dropped.

Fixes the perf regression from #221717.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/225527
DeltaFile
+11-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+3-6llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-root-order.ll
+14-62 files

FreeNAS/freenas 9d611a2src/middlewared/middlewared/plugins/rsync validate.py, tests/api2 test_rsync_ssh_authentication.py

NAS-143926 / 27.0.0-BETA.1 / Fix nonstandard rsync SSH port handling (#19836)
DeltaFile
+142-1tests/api2/test_rsync_ssh_authentication.py
+12-5src/middlewared/middlewared/plugins/rsync/validate.py
+154-62 files

LLVM/project 2dc4f2dllvm/test/CodeGen/AMDGPU fix-sgpr-copies-f16-true16.mir

Switch vgpr16 -> vgpr32 in test case
DeltaFile
+5-7llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+5-71 files

LLVM/project 2d7cde0compiler-rt/test/hwasan/TestCases/Linux decorate-proc-maps.c

[NFC][compiler-rt][hwasan] Avoid variable length array warning in test (#225497)

Replace the non-constant array size expression for the static buffer
with a fixed size.

Assisted-by: Gemini
DeltaFile
+2-3compiler-rt/test/hwasan/TestCases/Linux/decorate-proc-maps.c
+2-31 files

LLVM/project ab49f33llvm/test/Transforms/SLPVectorizer/AArch64 splat-gather-subtree-root-order.ll

[SLP][NFC]Add an extra test for missing reordering skipping, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/225525
DeltaFile
+45-0llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-root-order.ll
+45-01 files

GhostBSD/gib 61b1fc5src welcome_live.py create_cfg.py

Merge pull request #90 from Avicennasis/docs/fix-typos

docs: fix 7 typos and grammar errors in comments
DeltaFile
+5-5src/gbi_common.py
+2-2src/install.py
+1-1src/welcome_live.py
+1-1src/create_cfg.py
+9-94 files

LLVM/project 9d5881fllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU arbitrary-fp-to-half-fallback.ll

[AMDGPU] Fall back for FP8-to-half conversions without native support

The custom v2i8 source action also handles half results on gfx950, which
has native OCP FP8-to-f32 conversions but lacks FP8-to-f16 instructions.
Converting FP8 vectors to half therefore reached lowerFromFP8 and asserted
that FP8F16ConversionInsts was available.

Use generic legalization for half results when the subtarget lacks the
required instructions. Preserve native f32 conversions and native f16
conversions on targets that support them.

Add gfx950 regression coverage for both OCP encodings, including vectors
that widen or split into pairs, and check that native f32 instructions
remain selected.
DeltaFile
+361-0llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-half-fallback.ll
+6-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+367-02 files

LLVM/project 095b554libc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll bf16.ll

Merge and update reviewer test case

Merge branch 'users/zGoldthorpe/wide-copies/precommit' into users/zGoldthorpe/wide-copies/materialise
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+9,382-9,576llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+10,637-154llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+4,770-4,849llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+2,212,421-20,7046,978 files not shown
+2,596,392-211,3376,984 files

GhostBSD/gib 5e0a564src install.py

Update src/install.py

Co-authored-by: sourcery-ai[bot] <58596630+sourcery-ai[bot]@users.noreply.github.com>
DeltaFile
+1-1src/install.py
+1-11 files

LLVM/project b864af1llvm/include/llvm/Analysis ValueTracking.h, llvm/lib/Analysis ValueTracking.cpp

[ValueTracking] Strip computeKnownBits variant from ABI (NFC) (#225478)

It is unused.
DeltaFile
+0-10llvm/lib/Analysis/ValueTracking.cpp
+0-9llvm/include/llvm/Analysis/ValueTracking.h
+0-192 files

LLVM/project 6ad7027llvm/lib/CodeGen MachineOutliner.cpp, llvm/test/CodeGen/AArch64 machine-outliner-call-debugloc.mir

[MachineOutliner] Preserve debug locations on outlined call sequences (#224189)

Machine Outliner replacement call sequences currently have no DebugLoc.
When one immediately follows another call, its address can be emitted
with DWARF line 0, meaning “unknown source location,” so symbolication
finds the function but not the source line.

Copy the first usable source location from each candidate to its
replacement call sequence, including any target-inserted save and
restore instructions. If none exists, leave the sequence locationless.
This matches the IR Outliner’s policy: preserve each replacement call’s
location while leaving the shared outlined body locationless because it
represents multiple source regions.
DeltaFile
+204-0llvm/test/CodeGen/AArch64/machine-outliner-call-debugloc.mir
+84-0llvm/test/DebugInfo/AArch64/machine-outliner-call-debugloc.ll
+27-1llvm/lib/CodeGen/MachineOutliner.cpp
+315-13 files

FreeBSD/ports 92d81e1www/pocketbase Makefile distinfo

www/pocketbase: Update 0.40.3 => 0.40.4

Changelog:
https://github.com/pocketbase/pocketbase/releases/tag/v0.40.4

PR:             298771
Approved by:    osa, vvd (Mentors, implicit)
Signed-off-by:  Christos Longros <chris.longros at gmail.com>
DeltaFile
+5-5www/pocketbase/distinfo
+1-1www/pocketbase/Makefile
+6-62 files

LLVM/project bb397eallvm/test/CodeGen/AMDGPU fix-sgpr-copies-f16-true16.mir

Add reviewer test case
DeltaFile
+40-0llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+40-01 files

NetBSD/pkgsrc YMqBdpdmultimedia/libdvdread Makefile

   libdvdread: add pkg-config to USE_TOOLS

   Library failed to link when dvdcss option was set.  Fix is to
   add pkg-config to USE_TOOLS, as suggested by Taylor Campbell.
VersionDeltaFile
1.38+2-1multimedia/libdvdread/Makefile
+2-11 files

LLVM/project dc245a0clang/lib/CIR/CodeGen CIRGenFunction.cpp, clang/test/CIR/CodeGen class.cpp

[CIR] Fixup 'zero' branch of Null Initialization (#225490)

The zero branch has a test for an NYI based on whether the thing is a
VLA or not. However, classic codegen uses 'dyn_cast_or_null', and we
used 'isa', so a nullptr caused an assert. This patch fixes it.
DeltaFile
+64-0clang/test/CIR/CodeGen/class.cpp
+1-1clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+65-12 files

NetBSD/pkgsrc c2W7aTpnet/rrsync distinfo

   rrsync: update distinfo for rsync update
VersionDeltaFile
1.2+4-4net/rrsync/distinfo
+4-41 files

LLVM/project bd4b8fcclang/lib/Headers avx10v2auxintrin.h, clang/test/CodeGen/AArch64 neon-ldst-one.c

Merge branch 'main' into users/vitalybuka/spr/nfccompiler-rthwasan-avoid-variable-length-array-warning-in-test
DeltaFile
+4,372-0clang/test/OpenMP/structured-bindings-codegen.cpp
+1,413-1,413clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+1,403-1,403clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+1,403-1,403clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
+0-2,567clang/test/CodeGen/AArch64/neon-ldst-one.c
+2,403-0clang/lib/Headers/avx10v2auxintrin.h
+10,994-6,7861,985 files not shown
+114,685-56,0761,991 files

NetBSD/pkgsrc USRd2kqnet/py-netsnmp Makefile

   py-netsnmp: add missing tool dependency
VersionDeltaFile
1.16+3-1net/py-netsnmp/Makefile
+3-11 files

LLVM/project 755e4d4llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/X86 arbitrary-fp-to-half.ll

[SelectionDAG] Fix FP8 conversions to half for subnormals and overflow (#224984)

This PR contains 2 fixes:

* Preserve subnormal values when the source format and destination have
the same exponent bias. Normalizing these inputs previously produced a
nonpositive destination exponent and an invalid floating-point encoding.

* Convert finite values beyond the destination exponent range to
infinity, while preserving the existing NaN handling. This fixes
Float8E5M3FNU to half conversions that previously produced NaNs on
overflow.

Assisted by: Codex (Astra)
DeltaFile
+208-0llvm/test/CodeGen/X86/arbitrary-fp-to-half.ll
+16-3llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+224-32 files

LLVM/project 365851eclang/lib/CIR/CodeGen CIRGenExprComplex.cpp CIRGenFunction.h, clang/test/CIR/CodeGen cleanup-conditional-with-wrapper-eh.cpp cleanup-conditional-with-wrapper.cpp

[CIR] Fix a problem with cleanup active flag initialization (#225507)

While working on another problem related to conditional cleanups, I came
across a problem with the way CIR was initializing the cleanup active
flag. We were often clearing the flag below the body of a conditional
cleanup region that the flag was meant to guard. As a result, we would
sometimes skip a conditional cleanup becuase the body of the cleanup
region set the active flag to true, but then we cleared the flag
unconditionally before control flow reached the cleanup.

This change fixes that problem and aligns the active flag initialization
placement with classic codegen.

Assisted-by: Cursor / various models
DeltaFile
+101-0clang/test/CIR/CodeGen/cleanup-conditional-eh.cpp
+73-0clang/test/CIR/CodeGen/cleanup-conditional.cpp
+27-6clang/lib/CIR/CodeGen/CIRGenFunction.h
+19-3clang/test/CIR/CodeGen/cleanup-conditional-with-wrapper.cpp
+16-4clang/test/CIR/CodeGen/cleanup-conditional-with-wrapper-eh.cpp
+2-2clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
+238-153 files not shown
+245-189 files

NetBSD/pkgsrc MrrTmXuwww/py-aiohttp-cors Makefile

   py-aiohttp-cors: sync not-for-python versions with py-aiohttp
VersionDeltaFile
1.7+3-1www/py-aiohttp-cors/Makefile
+3-11 files

FreeBSD/doc f25cc54documentation/content/en/books/handbook/x11 _index.adoc

handbook/x11: Add nvidia-driver-580

Reported by:    jbo
DeltaFile
+5-0documentation/content/en/books/handbook/x11/_index.adoc
+5-01 files

NetBSD/pkgsrc 6Kyibxstextproc/py-yamlordereddictloader Makefile

   py-yamlordereddictloader: sync not-for-python versions with py-yaml
VersionDeltaFile
1.4+3-1textproc/py-yamlordereddictloader/Makefile
+3-11 files

FreeBSD/ports c5d6228net-mgmt/telegraf Makefile distinfo

net-mgmt/telegraf: Update to 1.40.1

Release notes:  https://github.com/influxdata/telegraf/releases/tag/v1.40.1
DeltaFile
+5-5net-mgmt/telegraf/distinfo
+1-2net-mgmt/telegraf/Makefile
+6-72 files

LLVM/project eaf501bllvm/utils/gn/secondary/clang/lib/Headers BUILD.gn

[gn build] Port aa7a0c3c318b (#225517)
DeltaFile
+2-0llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
+2-01 files

NetBSD/pkgsrc mdlV4oGdoc CHANGES-2026

   doc: + Updated sysutils/gam to 7.48.11 [sborrill 2026-09-22]
VersionDeltaFile
1.6243+2-1doc/CHANGES-2026
+2-11 files

OpenBSD/ports FGFzgqqdevel/llvm/23/patches patch-llvm_lib_MC_MCAsmInfoELF_cpp patch-llvm_include_llvm_CodeGen_AsmPrinter_h

   make emitTrapAlignment() behave like emitAlignment()
VersionDeltaFile
1.3+16-7devel/llvm/23/patches/patch-llvm_lib_CodeGen_AsmPrinter_AsmPrinter_cpp
1.2+4-3devel/llvm/23/patches/patch-llvm_include_llvm_CodeGen_AsmPrinter_h
1.3+1-1devel/llvm/23/patches/patch-llvm_lib_MC_MCAsmInfoELF_cpp
+21-113 files

LLVM/project 370326fclang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.h CIRABIRewriteContext.cpp

[CIR][NFC] Clarify the non-byval parameter helper's name and docs

Assisted-by: Cursor / claude-opus-5
DeltaFile
+9-8clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+1-1clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
+10-92 files