[libc++][pstl] Implementation of parallel inclusive scan based on decoupled lookback (#238772)
This PR adds a new basis operation to the `statpart` backend:
`__lookback_scan()`.
This function is a basic building block for the family of single-pass
scanning operations: `inclusive_scan`, `exclusive_scan`,
`transform_inclusive_scan`, `transform_exclusive_scan`, `copy_if`,
`remove`, `remove_if`, `remove_copy`, `remove_copy_if`, `unique`,
`unique_copy`.
The approach is based on the paper "Single-pass Parallel Prefix Scan
with Decoupled Look-back".
The first algorithm to use it is `std::transform_inclusive_scan()`,
whose implementation is also included in the patch.
Since the declarations and the tests were already provided previously,
now this algorithm becomes parallel when the `statpart` backend is used.
[AMDGPU] Implement AsyncMark Stages (#220442)
Enables asyncmark operations to append and remove asyncmarks from
per-stage sequences, instead of a single sequence. Both
llvm.amdgcn.asyncmark and llvm.amdgcn.wait.asyncmark take a constant
stage mask in which a set bit names a stage; the operation acts only on
the sequences of the stages it names. The zero mask is special and names
every stage, which preserves the original behavior; old IR is
auto-upgraded to pass a zero mask.
[mlir][XeGPU] Fix matrix op lowering for a payload that is not contiguous (#228638)
This PR fixes LoadStoreMatrixToXeVMPattern, which discards the payload
shape and emits one flat llvm.load/llvm.store at the linearized offset
of the first coordinate. That assumes the payload occupies that many
consecutive elements, which only holds when its extent lies along the
dimension whose stride is 1.
For a vector<2x1xf32> payload of a row-major 4x4 tile at [1, 2], the two
elements are (1,2) and (2,2) — linear 6 and 10. The lowering writes 6
and 7, so one element lands in the wrong row. The shape was never
checked against the strides, only asserted to have at most one non-unit
dimension, which 2x1 satisfies.
This is required to support convert_layout lowering whose shape size is
driven by producer/consumer op, so when it lowers to slm store and load,
it may not fit to one slm load/store instruction.
The payload is now split into the largest pieces that are contiguous in
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[OpenACC] Fix FixedPoint/ObjC types in a OpenACC directive (#239643)
The original patches for OpenACC didn't consider that ObjC types are
'anyPointerType', which we don't have proper semantics to use. This
patch alters them to reject them.
While working through examples, I discovered that we have a similar
problem with the 'fixed point' types, so reject them for now.
AI Disclosure: Claude helped write tests.
Fixes: #239483
[flang][acc] Introduce data mapping optimization pass for copy (#239398)
Change an implicit copy to a copyin for named constants and for
variables that are not modified inside the compute region.
[Hexagon] Add V83 support to compiler and assembler (#238007)
[Hexagon] Add V83 support to compiler and assembler
Add Hexagon V83 as an architecture target, including new V83
instructions.
Plumbing: arch/HVX subtarget features and predicates, processor model
and scheduling itineraries, subtarget queries, MC target support, and
clang driver/preprocessor support.
Instructions: scalar RTOS call/jump (_rb) and allocframe variants,
trap2, the vallocframe/vdeallocframe vector-stack ops, scalar
floating-point audio ops (F7_*), and new HVX ALU and multiply
instructions, together with their intrinsics, and clang builtins.
Also defines the VFRAMELIMIT and VSP control registers used by
the vector-stack instructions.
Adds MC and clang tests.
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[LifetimeSafety] Track a temporary materialized by a default argument (#239586)
The CFG does not visit a default argument's expression (PR13385), but it
does expire the temporaries it creates. Such a temporary therefore had
no loan, and a view of it could dangle unreported. Issue the loan at the
CXXDefaultArgExpr, so it is reported at the call.
Assisted-by: Claude Opus 5.5
---------
Co-authored-by: Gabor Horvath <gaborh at apple.com>
net/librdkafka: Update 2.8.0 => 2.16.0
Since it's a lot of version updates, it's advised to see the Changelog.
Changelog:
https://github.com/confluentinc/librdkafka/blob/v2.16.0/CHANGELOG.md
Port changes:
- Update WWW to the redirected URL.
- Switch to CMake to modernize the build system and generate proper
SONAME entries.
- Add build option for SASL support.
- Disable building static libraries.
- Attempt to fix some test suite build and run issues.
PR: 299455
Sponsored by: PANS Jarosław
Reviewed by: diizzy
Approved by: pizzamig (maintainer timeout)
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[libc][docs] Migrate docgen output to MyST Markdown (#239413)
The rest of libc/docs/ has migrated to MyST Markdown, leaving docgen as
the last generator emitting reStructuredText list-tables with plain
checkmark substitutions.
Switch docgen to emit MyST Markdown with styled HTML status tables that
adapt to Furo's light and dark colour themes and include screen-reader
labels for symbol status badges.
Assisted-by: Automated tooling, human reviewed.
net/librdkafka: Update 2.8.0 => 2.16.0
Since it's a lot of version updates, it's advised to see the Changelog.
Changelog:
https://github.com/confluentinc/librdkafka/blob/v2.16.0/CHANGELOG.md
Port changes:
- Update WWW to the redirected URL.
- Switch to CMake to modernize the build system and generate proper
SONAME entries.
- Add build option for SASL support.
- Disable building static libraries.
- Attempt to fix some test suite build and run issues.
PR: 299455
Sponsored by: PANS Jarosław
Reviewed by: diizzy
Approved by: pizzamig (maintainer timeout)
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[NFC][RISCV] Add curly braces around case statement (#239653)
Since TRI is declared after this case statement without a new scope, it
is scoped to the whole switch statement, and thus adding a new case
statement after it would try to jump over the initialisation, which is
not permitted. Add braces so this issue is no longer lurking and new
case statements can be added at the end in future.
Fixes: 228f88fdc8e9 ("[RISCV] Inline Assembly: RVC constraint and N
modifier (#112561)")
amd64/vmm: Don't advertise AMD PerfMonV2 or performance counters
vmm does not handle CPUID leaf 0x80000022, so a FreeBSD guest on a
Family 19h or later host panics on "kldload hwpmc", which trusts the
PerfMonV2 bit and writes AMD_PMC_GLOBAL_CTL.
Tested by: Osvaldo Janeri Filho <ojanerif at amd.com>
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Reviewed by: markj, kib
Differential Revision: https://reviews.freebsd.org/D61141
hwpmc: Decline the AMD PerfMonV2 path when GLOBAL_CTL is absent
The v2 path writes AMD_PMC_GLOBAL_CTL whenever the PerfMonV2 CPUID bit
is set. bhyve passes that bit through from the host but does not emulate
the register, so loading hwpmc in a guest on a Family 19h or later host
panics the kernel.
amd_v2_hwcheck_cpu() already probes EVSEL MSRs, so probe GLOBAL_CTL
there too, in order to reject the v2 path and fall back to the generic
CPU class.
Fixes: 9d3064010590 ("hwpmc_amd: add PerfMonV2 global-control path")
Tested by: Osvaldo Janeri Filho <ojanerif at amd.com>
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Reviewed by: mhorne, afscoelho at gmail.com
Differential Revision: https://reviews.freebsd.org/D61133
science/py-lifelines: update to 0.30.3
This fixes runtime with modern python versions and dependencies stack.
PR: 300002
Reported by: Patrick Crandol <patrick at crandol.com>
math/py-autograd-gamma: add new port
autograd compatible approximations to the derivatives of the Gamma-family of
functions.
This is a requirement to update science/py-lifelines to latest version.
[LoongArch] Enable LoopDataPrefetch for LA464/LA664 (#239076)
Enable LoopDataPrefetch by default for LA464/LA664, move the prefetch
parameters into `LoongArchSubtarget::initializeProperties` and also
limit the MinPrefetchStride to 2KB.
We've created a micro-benchmark which implements one 8-byte load per
iteration with 50 dependent ALU ops of other work, measured on a
Loongson 3B6000 (LA664).
```
stride no preld best preld
<= 64 B 26.2 ns 25.8 ns
1 KiB 30.2 ns 25.9 ns (only when prefetching 32 iterations ahead)
2 KiB 108.4 ns 28-30 ns (4+ iterations ahead)
16 KiB 110.7 ns 28.5 ns
```
The hardware prefetchers stop tracking a stream somewhere between a 1
KiB and a 2 KiB stride. Below that, software prefetches only add
instructions and increase the run time.
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