[CodeGenPrepare] Use make_early_inc_range to avoid iterator invalidation. (#215347)
While iterating users of a {s|z}ext's source operand in optimizeExtUses
we explicitly replace the use with a trunc instruction thereby
invalidating iterator of the loop. Update the loop to use
make_early_inc_range to avoid invalidation.
[lldb] Handle implicit values followed by full-width piece operations (#219160)
`DW_OP_implicit_value` stores its bytes in a `Value` whose internal type
is `HostAddress`. The `DW_OP_piece` and `DW_OP_bit_piece` evaluators
therefore mistook the backing-buffer address for a memory location and
rejected valid full-width pieces.
Use the saved implicit location-description kind to recognize this
storage representation. Full-width byte pieces and zero-offset
full-width bit pieces now preserve the backing bytes, while genuine host
addresses and partial pieces retain their existing behavior.
Add a unit test for both expressions from the issue.
Fixes #203224
[IR][TableGen] Add RangeSet TableGen intrinsic property (#203623)
This change introduces a `RangeSet` TableGen intrinsic property.
Existing `Range<idx, lo, hi>` keeps its current half-open semantics and
continues to emit the existing range attribute.
TableGen syntax: `RangeSet<idx, [[lo0, hi0], [lo1, hi1], ...]>` where
`[lo, hi]` are closed ordered and non-overlapped intervals.
[SCEV] Update comment for check BE formula in howManyLT (NFC) (#219170)
Update outdate comments around the code for picking the check BE
formula. It includes the following updates:
* define End = max(RHS,Start), as used later, use instead of incorrect
max(End,Start)
* precondition for the code use check min(RHS,Start) > Start - Stride
* update remaining test to be consistent
* Stride = umax(1, Stride) instead of umin, which matches the code
above; umin would not avoid divide by 0.
Preparation for https://github.com/llvm/llvm-project/pull/218694
PR: https://github.com/llvm/llvm-project/pull/219170
AMDGPU: Pass MachineRegisterInfo to getImmOrMaterializedImm (#219422)
The only used the operand to reach the MachineRegisterInfo. Pass it
directly so it no longer depends on MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[lldb] Reject an unusable memory-cache-line-size (#219217)
`target.process.memory-cache-line-size` is an unbounded `UInt64`, so
`settings set` accepts 0, and `MemoryCache` keeps the value in a
`uint32_t`, so it also accepts any multiple of 2^32, which truncates to
0. Every consumer then takes a remainder by 0.
`Process::ReadCStringFromMemory` divides on the first iteration of its
loop, before it touches inferior memory, so any address reproduces it.
On an x86_64 host that is a `SIGFPE` and lldb dies; on AArch64 `udiv` by
zero yields 0, so `addr % 0` evaluates to `addr` and the subtraction
underflows to a huge chunk size, and the bug hides.
```
$ lldb -b \
-o 'settings set target.process.memory-cache-line-size 0' \
-o 'target create --core linux-x86_64.core'
Floating point exception: 8
```
[36 lines not shown]
Use unveil(2) to restrict write access to mandoc.db(5) and /tmp/
and read access to the selected manpath directory or directories,
but leave global read access open in -t mode.
Tweaks from and looks correct to deraadt@.
RISCV: Pass MachineRegisterInfo to isVLKnownLE (#219402)
isVLKnownLE and its getEffectiveImm helper used the VL operands to reach
the MachineRegisterInfo. Pass it directly so they no longer depend on
MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
py-jwcrypto: updated to 1.5.9
1.5.9
Add ML-DSA post-quantum signature support (RFC 9964)
Support fully specified algorithms per RFC 9864
Skip unknown kty in JWKSet import per RFC 7517 §5
Reject non-empty encrypted key in bare ECDH-ES
Limit dot splits during JWE and JWS parsing
py-starlette: updated to 1.6.0
1.6.0 (August 8, 2026)
Added
* Add `max_body_size` to `Starlette` and route classes
* Expose `http.response.debug` information via response extensions
AMDGPU: Pass MachineRegisterInfo to getImmOrMaterializedImm
The only used the operand to reach the MachineRegisterInfo. Pass it
directly so it no longer depends on MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
CodeGen: Pass instruction and operand index to isPCRelRegisterOperandLegal
Replace the MachineOperand argument to the
TargetInstrInfo::isPCRelRegisterOperandLegal hook with the containing
instruction and operand index. The M68k implementation only used the operand
to recover its parent instruction and operand number, so this drops the
dependence on MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
bulk-test-go: Update Terraform/OpenTofu dependencies
Build all Terraform and OpenTofu versions and adjust DEPENDS for
providers that have now version suffixes in PKGNAME and PKGPATH.
Noticed via pkgsrc-bulk@ and thanks to <jperkin>!
