LLVM/project 5249f5allvm/include/llvm/MCA/HardwareUnits ResourceManager.h, llvm/lib/MCA/HardwareUnits ResourceManager.cpp

[MCA] Make `ResourceSizeMask` const (#189453)

This patch marks the already effectively constant `ResourceSizeMask` as
`const`. It adds a helper `computeResourceSizeMask()` to initialize it
in the member initializer list.
DeltaFile
+10-7llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
+7-3llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
+17-102 files

FreeBSD/ports d8d62c7biology/ugene Makefile

biology/ugene: adopt
DeltaFile
+1-1biology/ugene/Makefile
+1-11 files

LLVM/project 0d33a15clang/test/Modules pr189415.cppm

Add a target triple to clang/test/Modules/pr189415.cppm (#189937)

Not all targets support thread_local, so in some environments the test
would fail with:

  tools/clang/test/Modules/Output/pr189415.cppm.tmp/counter.cppm:6:1:
  error: thread-local storage is not supported for the current target

Follow-up to #189796
DeltaFile
+2-2clang/test/Modules/pr189415.cppm
+2-21 files

FreeBSD/src 0dbbed2sys/netinet6 ip6_mroute.c

ip6_mroute: Fix the type name in sysctl_mfctable()

No functional change since apparently it's fine to compute the size of
a pointer type when the base type is undefined.

Fixes:  0bb9c2b665d9 ("ip6_mroute: FIBify")
DeltaFile
+1-1sys/netinet6/ip6_mroute.c
+1-11 files

FreeBSD/src f3c7723sys/dev/vmm vmm_dev.c, sys/kern kern_jail.c

vmm: Restore the ability to create VMs as root in a jail

The new PRIV_VMM_CREATE and DESTROY permissions should be allowed by
jails, so need to be added to the list in prison_priv_check().  Then,
modify vmmdev_create() to verify that the jail was created with the
allow.vmm flag.  This is already verified when opening /dev/vmmctl, but
checking again doesn't hurt and ensures that one can't pass the
allow.vmm policy by passing a vmmctl fd along a unix domain socket from
outside the jail.

Rename vmm_priv_check() to vmm_jail_priv_check() to make the function's
purpose more clear.

Reported by:    novel
Reviewed by:    bnovkov
Fixes:          d4c05edd410e ("vmm: Add privilege checks to vmmctl operations")
Differential Revision:  https://reviews.freebsd.org/D56119
DeltaFile
+11-5sys/dev/vmm/vmm_dev.c
+8-0sys/kern/kern_jail.c
+19-52 files

FreeBSD/src c6a1c12sys/i386/i386 pmap.c, sys/powerpc/aim mmu_oea64.c mmu_radix.c

pmap: Do not use PMAP_LOCK_INIT with kernel_pmap

The kernel_pmap lock is a bit special: it does not need the DUPOK flag,
and it really belongs to a different lock class.  If it belongs to the
same class as regular pmap locks, then witness may report warnings when
performing UMA allocations under a regular pmap lock, if the allocation
triggers a pmap_growkernel() call.

Replace instances of PMAP_LOCK_INIT(kernel_pmap) with inline mtx_init()
calls to silence some witness warnings for harmless behaviour I see with
some uncommitted test programs.

Reviewed by:    alc, kib
MFC after:      2 weeks
Differential Revision:  https://reviews.freebsd.org/D56185
DeltaFile
+1-1sys/i386/i386/pmap.c
+1-1sys/powerpc/aim/mmu_oea64.c
+1-1sys/powerpc/aim/mmu_radix.c
+1-1sys/powerpc/booke/pmap.c
+1-1sys/riscv/riscv/pmap.c
+1-1sys/powerpc/aim/mmu_oea.c
+6-63 files not shown
+9-99 files

LLVM/project effcd18llvm/test/CodeGen/RISCV/rvv roundtozero-vp.ll roundeven-vp.ll

[RISCV] Remove codegen for VP float rounding intrinsics (#189896)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off seven intrinsics from #179622.

We now generate vfcvt.rtz for llvm.vp.roundtozero. It looks like we
should have been using the codegen for llvm.trunc for it, but we somehow
missed that.
DeltaFile
+474-1,054llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
+431-799llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
+431-799llvm/test/CodeGen/RISCV/rvv/round-vp.ll
+431-799llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
+406-774llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
+376-744llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
+2,549-4,96911 files not shown
+4,375-8,74017 files

LLVM/project f2685faclang/lib/AST/ByteCode Interp.cpp

[clang][bytecode] Disable tail calls on sparc (#189887)

Looks like this causes problems there as well:
https://lab.llvm.org/buildbot/#/builders/114/builds/252

Interp.cpp:2572:21: error: cannot tail-call: target is not able to
optimize the call into a sibling call
 2572 |   MUSTTAIL return Fn(S, PC);
      |                   ~~^~~~~~~
DeltaFile
+1-1clang/lib/AST/ByteCode/Interp.cpp
+1-11 files

LLVM/project 7a33b1dllvm/lib/Target/AArch64 AArch64InstrInfo.td

[AArch64][GlobalISel] Move new SQDMULLi32 pattern to join the others
DeltaFile
+4-4llvm/lib/Target/AArch64/AArch64InstrInfo.td
+4-41 files

LLVM/project 853cbc2llvm/lib/IR Metadata.cpp

second attempt of perf regression fix...

Created using spr 1.3.8-wip
DeltaFile
+2-0llvm/lib/IR/Metadata.cpp
+2-01 files

LLVM/project a5b9abcllvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 arm64-vmul.ll

[AArch64][GlobalISel] Selet SQDMLSLv1i64_indexed when vector_extract present

Like SQDMLALv1i64_indexed, selecting this intrinsic reduces the number of instructions generated by 1, as it performs both the vector extract and the sqdmlal in one instruction.

This only works when the vector to extract from is v4i32, not v2i32. This is due to some issues GlobalISel has selecting intrinsics using v2i32.
DeltaFile
+7-16llvm/test/CodeGen/AArch64/arm64-vmul.ll
+6-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+13-162 files

FreeBSD/ports 1b0d5ddwww/lexbor pkg-plist distinfo

www/lexbor: Update 2.7.0 => 3.0.0

Approved by:            db@, yuri@ (Mentors, implicit)
DeltaFile
+15-2www/lexbor/pkg-plist
+3-3www/lexbor/distinfo
+1-2www/lexbor/Makefile
+19-73 files

FreeNAS/freenas a950391src/middlewared/middlewared/apps webshell_app.py

NAS-140428 / 26.0.0-BETA.2 / Fix apps container UI shell (by Qubad786) (#18607)

Automatic cherry-pick failed. Please resolve conflicts by running:

    git reset --hard HEAD~1
    git cherry-pick -x 6c3fd6dbef123c4ed72aef7833aafe53c0603fbe

If the original PR was merged via a squash, you can just cherry-pick the
squashed commit:

    git reset --hard HEAD~1
    git cherry-pick -x 90803d549bee3d9d77ce6d38018870fa26d3c948

## Problem

Opening a shell for a Docker app container (`app_name` + `container_id`)
failed because the `container_id` block ran unconditionally before the
`app_name` check — passing a Docker container name (string) to
`container.nsenter`, which expects an integer incus/libvirt container

    [10 lines not shown]
DeltaFile
+6-7src/middlewared/middlewared/apps/webshell_app.py
+6-71 files

LLVM/project a3ebf37llvm/lib/Target/AMDGPU GCNVOPDUtils.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.fdot2.ll llvm.amdgcn.fdot2.f32.bf16.ll

AMDGPU: Fix generation for dot2 VOPD with sgpr inputs

There was no check for sgpr in src1 operand.
DeltaFile
+204-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+108-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+6-4llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+318-43 files

LLVM/project d482215llvm/test/CodeGen/AArch64 arm64-vmul.ll

[AArch64][GlobalISel] Add test for v4i32 vector extract sqdmlal/sqdmlsl

1. Tests only test v4i32 versions of the intrinsic, as v2i32 currently doesn't work.
2. GlobalISel currently generates poor code in the sqdmlsl case. To fix, the sqdmlalvi64_indexed pattern needs to be copied over for sqdmlsl.
DeltaFile
+42-6llvm/test/CodeGen/AArch64/arm64-vmul.ll
+42-61 files

LLVM/project f6ffdbcmlir/lib/Dialect/Affine/Utils Utils.cpp, mlir/test/Dialect/Affine scalrep.mlir

[MLIR][Affine] Fix dead store elimination for vector stores with different types (#189248)

affine-scalrep's findUnusedStore incorrectly classified an
affine.vector_store as dead when a subsequent store wrote to the same
base index but with a smaller vector type. A vector<1xi64> store at
[0,0] does not fully overwrite a vector<5xi64> store at [0,0], so the
first store must be preserved.

The loadCSE function in the same file already had the correct
type-equality check for loads; this patch adds the analogous check for
stores in findUnusedStore.

Fixes #113687

Assisted-by: Claude Code
DeltaFile
+37-0mlir/test/Dialect/Affine/scalrep.mlir
+13-2mlir/lib/Dialect/Affine/Utils/Utils.cpp
+50-22 files

LLVM/project 67a4c90libsycl/src/detail program_manager.cpp program_manager.hpp

fix comments

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+9-9libsycl/src/detail/program_manager.cpp
+5-0libsycl/src/detail/program_manager.hpp
+14-92 files

LLVM/project 16a3e0allvm/lib/Target/AArch64 AArch64InstrInfo.td

[AArch64][GlobalISel] Select lane index sqdmlal when vector_extract of v4i32 present

SQDMLALv1i64_indexed takes in an index of a vector as its final operand, meaning it doesn't need to extract the element in a separate instruction.

This only works when the vector to extract from is a v4i32. Currently, extracting from a v2i32 doesn't work, and I'm unsure why.
DeltaFile
+6-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+6-01 files

LLVM/project b655050llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.cpp

[AArch64][GlobalISel] Add patterns for scalar sqdmlal/sqdmlsl
DeltaFile
+86-44llvm/test/CodeGen/AArch64/arm64-vmul.ll
+12-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1-2llvm/test/CodeGen/AArch64/arm64-int-neon.ll
+1-0llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+100-464 files

LLVM/project 5a3abf9llvm/include/llvm/ADT Uniformity.h, llvm/lib/Analysis UniformityAnalysis.cpp TargetTransformInfo.cpp

[NFC] Rename InstructionUniformity to ValueUniformity
DeltaFile
+25-26llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+7-7llvm/include/llvm/ADT/Uniformity.h
+6-7llvm/lib/Analysis/UniformityAnalysis.cpp
+5-6llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+5-5llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+4-4llvm/lib/Analysis/TargetTransformInfo.cpp
+52-557 files not shown
+68-7513 files

OpenBSD/ports wPVFEXueditors/vim-classic Makefile distinfo, editors/vim-classic/patches patch-src_configure_ac

   update vim-classic to newer checkout, use new vim-classic.org HOMEPAGE,
   update AUTOCONF_VERSION now that warnings are gone
VersionDeltaFile
1.9+9-5editors/vim-classic/Makefile
1.4+2-2editors/vim-classic/distinfo
1.3+1-1editors/vim-classic/patches/patch-src_configure_ac
+12-83 files

LLVM/project d6cd159llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (#178913)

Change the gating of `tlbip` instructions (`sysp` aliases) containing
`*E1IS*`, `*E1OS*`, `*E2IS*` or `*E2OS*` to be used with `+tlbid` or
`+d128`. This is because the 2025 Armv9.7-A MemSys specification says:

```
  All TLBIP *E1IS*, TLBIP *E1OS*, TLBIP *E2IS* and TLBIP *E2OS*
  instructions that are currently dependent on FEAT_D128 are updated
  to be dependent on FEAT_D128 or FEAT_TLBID
```

See also change #178912 where the gating of `+d128` for `sysp` was
removed.
DeltaFile
+498-366llvm/test/MC/AArch64/armv9a-tlbip.s
+17-14llvm/lib/Target/AArch64/AArch64SystemOperands.td
+17-2llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+2-4llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+534-3864 files

FreeBSD/ports 49d9108net-im/py-zapzap Makefile distinfo

net-im/py-zapzap: Update to 6.4.0

- Update list of build dependencies
- Add a post-patch target to fix the program version that does not match
  the distribution version. This discrepancy causes the following error:

===>   Generating temporary packing list
Traceback (most recent call last):
  File "<frozen runpy>", line 198, in _run_module_as_main
  File "<frozen runpy>", line 88, in _run_code
  File "/usr/local/lib/python3.11/site-packages/installer/__main__.py", line 98, in <module>
    _main(sys.argv[1:], "python -m installer")
  File "/usr/local/lib/python3.11/site-packages/installer/__main__.py", line 86, in _main
    with WheelFile.open(args.wheel) as source:
  File "/usr/local/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/usr/local/lib/python3.11/site-packages/installer/sources.py", line 162, in open
    with zipfile.ZipFile(path) as f:

    [12 lines not shown]
DeltaFile
+7-2net-im/py-zapzap/Makefile
+3-3net-im/py-zapzap/distinfo
+10-52 files

LLVM/project eed5592llvm/lib/IR Instruction.cpp Metadata.cpp

fix perf regression

Created using spr 1.3.8-wip
DeltaFile
+1-2llvm/lib/IR/Instruction.cpp
+2-0llvm/lib/IR/Metadata.cpp
+3-22 files

FreeBSD/ports af412b8cad/magic distinfo Makefile, cad/magic/files patch-textio__txInput.c patch-textio__textioInt.h

cad/magic: Update 8.3.570 => 8.3.629

Approved by:            yuri@ (maintainer, Mentor)
Approved by:            db@, yuri@ (Mentors, implicit)
Differential Revision:  https://reviews.freebsd.org/D56206
DeltaFile
+3-89cad/magic/files/patch-textio__txInput.c
+0-11cad/magic/files/patch-textio__textioInt.h
+3-3cad/magic/distinfo
+1-1cad/magic/Makefile
+1-0cad/magic/pkg-plist
+8-1045 files

LLVM/project 97562e7compiler-rt/cmake/Modules CheckAssemblerFlag.cmake

pass target triple to `check_assembler_flag` (#188521)

Target specific flags (Notably `-mimplict=always` for ARM) are not
recognized by the clang assembler unless the target is specified. This
PR passes the value of `CMAKE_C_COMPILER_TARGET` to the assembler so
that target specific flags are recognized.

## Previous behaviour

When configuring builtins for an ARMv7 target:

```
-- Builtin supported architectures: armv7
-- Checking for assembler flag -mimplicit-it=always
-- Checking for assembler flag -mimplicit-it=always - Not accepted
-- Checking for assembler flag -Wa,-mimplicit-it=always
-- Checking for assembler flag -Wa,-mimplicit-it=always - Not accepted
CMake Warning at CMakeLists.txt:462 (message):
  Don't know how to set the -mimplicit-it=always flag in this assembler; not

    [18 lines not shown]
DeltaFile
+1-0compiler-rt/cmake/Modules/CheckAssemblerFlag.cmake
+1-01 files

OpenBSD/ports CJ0062Nx11/xscreensaver Makefile distinfo, x11/xscreensaver/patches patch-hacks_glx_triangle_c patch-driver_subprocs_c

   update to xscreensaver-6.15
VersionDeltaFile
1.1+59-0x11/xscreensaver/patches/patch-hacks_glx_triangle_c
1.59+52-0x11/xscreensaver/pkg/PLIST
1.2+8-5x11/xscreensaver/patches/patch-driver_subprocs_c
1.123+6-5x11/xscreensaver/Makefile
1.30+3-3x11/xscreensaver/patches/patch-configure
1.52+2-2x11/xscreensaver/distinfo
+130-151 files not shown
+130-157 files

LLVM/project 6bf794allvm/test/CodeGen/AMDGPU memory-legalizer-private-singlethread.ll memory-legalizer-private-workgroup.ll

[AMDGPU] Disable generic DAG combines at -O0 to preserve debuggability. (#176304)

Disable generic DAG combines for AMDGPU at -O0 via
disableGenericCombines() to preserve instructions that users may want to
set breakpoints on during debugging.

Assisted-by: Cursor / Claude Opus 4.6
DeltaFile
+8,544-1,366llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
+8,544-1,366llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
+8,544-1,366llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+8,449-1,355llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
+8,449-1,355llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
+8,069-1,315llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
+50,599-8,12371 files not shown
+191,551-26,12277 files

OpenBSD/ports wfmSNRVgraphics/gimp/resynthesizer3 Makefile

   set HOMEPAGE
   (there is an update, but I'm not sure how to retrieve WRKINST
   to fix an install dir without a messy hack)
VersionDeltaFile
1.2+9-6graphics/gimp/resynthesizer3/Makefile
+9-61 files

LLVM/project c5363f2llvm/lib/IR Core.cpp, llvm/tools/llvm-c-test echo.cpp

[IR] Fix C API after getTerminator() change (#189922)

The C API function LLVMGetBasicBlockTerminator should return NULL when
the basic block is not well-formed.
DeltaFile
+5-0llvm/tools/llvm-c-test/echo.cpp
+1-1llvm/lib/IR/Core.cpp
+6-12 files