LLVM/project a3d9354llvm/include/llvm/CodeGen MachineMemOperand.h, llvm/test/CodeGen/X86 branchfolding-atomic-mmo.ll

[CodeGen] Compare MMO atomic ordering and syncscope. (#199892)

MachineMemOperand::operator== compared the address, flags, AA metadata,
range, alignment, and address space, but not atomic success ordering,
failure ordering, or syncscope. Users such as
MachineInstr::cloneMergedMemRefs could therefore treat atomic and
non-atomic MMOs, or atomics with different syncscopes, as identical.

This bug was found by a large run of Opus 4.7 looking for bugs in LLVM.
DeltaFile
+42-0llvm/test/CodeGen/X86/branchfolding-atomic-mmo.ll
+4-1llvm/include/llvm/CodeGen/MachineMemOperand.h
+46-12 files

LLVM/project 0d8ba69utils/bazel MODULE.bazel.lock .bazelrc

[bazel] Add config for hermetic clang toolchain (#192528)

This config uses the https://github.com/hermeticbuild/hermetic-llvm
toolchain to avoid any dependency on the host compiler. This makes it
trivial to test with remote execution and also supports cross
compilation.
DeltaFile
+33-3utils/bazel/MODULE.bazel.lock
+22-0utils/bazel/.bazelrc
+2-0utils/bazel/MODULE.bazel
+57-33 files

FreeNAS/freenas a476cb1src/middlewared/middlewared/plugins/enclosure_ nvme2.py

fix vseries rear nvme bay mapping
DeltaFile
+77-28src/middlewared/middlewared/plugins/enclosure_/nvme2.py
+77-281 files

FreeNAS/freenas c8b5fb3

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 90a99a5src/middlewared/middlewared/plugins/container lifecycle.py __init__.py, src/middlewared/middlewared/plugins/vm lifecycle.py

NAS-141142 / 27.0.0-BETA.1 / VM/container: parallelize shutdown and fix force_after_timeout (#19000)

## Problem

When middleware itself stops VMs and containers — on system
shutdown/reboot via the `system.shutdown` event, or during HA failover —
it loops through guests one at a time, waiting up to the per-guest
shutdown timeout (90s by default) for each. With many guests this
serializes into a long wait, even though stopping different guests has
no dependency on one another.

Separately, `vm.stop(force_after_timeout=True)` was silently ignored —
`stop_vm` only checked `options.force`. A VM that didn't respond to ACPI
within its `shutdown_timeout` was left running, contradicting the API
docstring and behaving inconsistently with the container path which
honored the flag correctly.

## Solution


    [7 lines not shown]
DeltaFile
+21-9src/middlewared/middlewared/plugins/vm/lifecycle.py
+14-3src/middlewared/middlewared/plugins/container/lifecycle.py
+2-2src/middlewared/middlewared/plugins/container/__init__.py
+37-143 files

LLVM/project b48d66allvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c
DeltaFile
+67-67llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+33-0llvm/lib/MC/MCDwarf.cpp
+15-15llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+10-0llvm/lib/CodeGen/MachineFunction.cpp
+4-4llvm/test/CodeGen/AMDGPU/debug-frame.ll
+4-0llvm/include/llvm/CodeGen/MachineFunction.h
+133-865 files not shown
+143-9011 files

LLVM/project 4e99a0fllvm/lib/Target/AMDGPU SIFrameLowering.cpp SIMachineFunctionInfo.h, llvm/test/CodeGen/AMDGPU amdgpu-spill-cfi-saved-regs.ll

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
DeltaFile
+2,926-0llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
+12-0llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+10-0llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+9-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+2,959-05 files

LLVM/project 74b5fc0llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll gfx-callable-argument-types.ll

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+3,568-2,598llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,912-1,913llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+2,700-12llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+631-631llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+505-510llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+394-399llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+9,710-6,063108 files not shown
+14,819-9,521114 files

LLVM/project 9df27a0llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll

[AMDGPU] Use register pair for PC spill

Change-Id: Ibedeef926f7ff235a06de65a83087c151f66a416
DeltaFile
+4,331-4,331llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,742-1,740llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+1,562-1,560llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,462-1,460llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+1,238-1,236llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+1,030-1,028llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+11,365-11,35589 files not shown
+18,153-18,04495 files

LLVM/project b29c1f7

[Clang] Default to async unwind tables for amdgcn

To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.

There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.

Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
DeltaFile
+0-00 files

LLVM/project a8f3ad8

[AMDGPU] Implement CFI for non-kernel functions

This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.

Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+0-00 files

LLVM/project d85a6f0

[AMDGPU] Emit entry function Dwarf CFI

Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.

Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+0-00 files

LLVM/project e384b89

[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU

While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).

Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
DeltaFile
+0-00 files

LLVM/project ec9a1c5

[MIR] Error on signed integer in getUnsigned

Previously we effectively took the absolute value of the APSInt, instead
diagnose the unexpected negative value.

Change-Id: I4efe961e7b29fdf1d5f97df12f8139aac12c9219
DeltaFile
+0-00 files

LLVM/project bf3622ellvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch musttail-tailcc.ll

[LoongArch] Support `tail` calling convention
DeltaFile
+163-0llvm/test/CodeGen/LoongArch/musttail-tailcc.ll
+1-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+164-02 files

OpenZFS/src dc58596config kernel-fs-parse.m4 kernel.m4, module/os/linux/zfs zpl_super.c

Linux 5.6 compat: fix fs_parse API mismatch

Added m4 macro to check fs_parse API signature and wrappers.  Before 
5.6, fs_parse() took a struct fs_parameter_description which wraps
the parameter specs with name and enum pointers. From 5.6, the 
description struct was removed and fs_parse() accepts the 
fs_parameter_spec directly.

Reviewed-by: Rob Norris <robn at despairlabs.com>
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: tiehexue <tiehexue at hotmail.com>
Closes #18585
DeltaFile
+34-0config/kernel-fs-parse.m4
+23-2module/os/linux/zfs/zpl_super.c
+2-0config/kernel.m4
+59-23 files

FreeNAS/freenas 72d79f3src/middlewared/middlewared/pytest/unit/utils test_cpu_temperatures.py test_cpu_info_impl.py, src/middlewared/middlewared/utils sensors.py cpu.py

Rewrite CPU temperature reading via sysfs hwmon
DeltaFile
+733-206src/middlewared/middlewared/pytest/unit/utils/test_cpu_temperatures.py
+0-481src/middlewared/middlewared/utils/sensors.py
+347-0src/middlewared/middlewared/utils/cpu/hwmon.py
+329-0src/middlewared/middlewared/pytest/unit/utils/test_cpu_info_impl.py
+0-232src/middlewared/middlewared/utils/cpu.py
+231-0src/middlewared/middlewared/utils/cpu/temperatures.py
+1,640-9198 files not shown
+2,253-98314 files

FreeBSD/src 6880405usr.bin/cap_mkdb cap_mkdb.c

cap_mkdb: Fix memory leak

This is not a big deal since it only iterates once before exiting, but
that's no reason to set a bad example.

PR:             195128
MFC after:      1 week
Reviewed by:    ngie
Differential Revision:  https://reviews.freebsd.org/D57251
DeltaFile
+2-1usr.bin/cap_mkdb/cap_mkdb.c
+2-11 files

FreeBSD/src f2a89e7sys/sys resource.h, usr.bin/limits limits.c

limits: Improve consistency

Historical precedent seems pretty consistent: size limits have singular
names, number limits have plural names.  RLIMIT_VMM broke this, and I
made matters worse by referring to this limit as “vmms” in limits(1).
Consistently use “vms” everywhere user-visible, while leaving the
question of whether or not to rename RLIMIT_VMM itself for another day.

Fixes:          1092ec8b3375 ("kern: Introduce RLIMIT_VMM")
Fixes:          53af2026f213 ("limits: Unbreak after RLIMIT_VMM addition")
Reviewed by:    bnovkov
Differential Revision:  https://reviews.freebsd.org/D57265
DeltaFile
+1-1sys/sys/resource.h
+1-1usr.bin/limits/limits.c
+2-22 files

LLVM/project 3a8b5e3lldb/tools/lldb-dap OutputRedirector.cpp OutputRedirector.h

[lldb-dap] Use MainLoop instead of a background thread in OutputRedirector. (#199970)

Replace the background thread in OutputRedirector with LLDB's MainLoop
event loop. This reduces the number of threads created and ensures file
descriptors are properly closed when no longer needed.

Since debugger's output is not I/O intensive, there is no risk of
hitting the pipe buffer limit with this approach.
DeltaFile
+39-34lldb/tools/lldb-dap/OutputRedirector.cpp
+23-12lldb/tools/lldb-dap/OutputRedirector.h
+14-11lldb/tools/lldb-dap/DAP.cpp
+76-573 files

LLVM/project d627924mlir/lib/Analysis SliceAnalysis.cpp, mlir/test/Dialect/Affine slicing-utils.mlir

[mlir][SliceAnalysis] Fix visited set to avoid infinite recursion  (#200008)

Fixes #139694, which introduced use-def cycle detection during slice
analysis, but some cycles were still not detected, potentially leading
to infinite recursion.

This PR fixes the handling of the visited set, which tracks the current
DFS path during recursion. Previously, the set could fail to detect
double cycles because entries were erased even when no recursive call
was made. The insert/erase operations are now only performed when
recursion actually occurs, ensuring that cycle detection correctly
reflects the active DFS path.
DeltaFile
+23-0mlir/test/Dialect/Affine/slicing-utils.mlir
+12-8mlir/lib/Analysis/SliceAnalysis.cpp
+35-82 files

LLVM/project f8bf8afclang/lib/Headers wasm_simd128.h, cross-project-tests/intrinsic-header-tests wasm_simd128.c

[WebAssembly] Add f16x8.demote_f32x4_zero to wasm_simd128.h. (#199795)

Missing header intrinsic.
DeltaFile
+8-0clang/lib/Headers/wasm_simd128.h
+6-0cross-project-tests/intrinsic-header-tests/wasm_simd128.c
+14-02 files

LLVM/project 5dc633bllvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp, llvm/test/CodeGen/AArch64 fabs.ll bf16-instructions.ll

[AArch64][GlobalISel] Add BF16 fabs and fneg (#198655)

These should be very simple as they are just legal or expanded based on
whether fullfp16 is available, as the FP16 FNEG and FABS instructions can
be used equally for BF16.
DeltaFile
+42-17llvm/test/CodeGen/AArch64/fabs.ll
+35-12llvm/test/CodeGen/AArch64/bf16-instructions.ll
+21-8llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
+17-8llvm/test/CodeGen/AArch64/fneg.ll
+12-9llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+3-2llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+130-566 files

LLVM/project f16c0ec.github/workflows issue-release-workflow.yml

workflows/issue-release-workflow: Remove template expansion of login names (#199772)

https://github.com/llvm/llvm-project/security/code-scanning/1609
https://github.com/llvm/llvm-project/security/code-scanning/1610
DeltaFile
+2-1.github/workflows/issue-release-workflow.yml
+2-11 files

LLVM/project a8e1f5cflang-rt/cmake/modules AddFlangRTOffload.cmake, flang-rt/include/flang-rt/runtime io-stmt.h

[flang-rt][cuda] Use a thinner I/O in CUDA build (#199769)

Reduce the footprint of IO in the CUDA build. This helps including IO
when using non relocatable device code mode.
DeltaFile
+194-0flang-rt/lib/runtime/io-stmt-minimal.cpp
+36-0flang-rt/lib/runtime/io-api-common.h
+9-0flang-rt/include/flang-rt/runtime/io-stmt.h
+4-1flang-rt/lib/runtime/CMakeLists.txt
+3-0flang-rt/cmake/modules/AddFlangRTOffload.cmake
+246-15 files

FreeBSD/doc 26ff6f4website/archetypes/release hardware.adoc

hardware: update missing powerpc entries

Previous patch (4c396c5b7fd7) missed `archetypes/release/hardware.adoc`
which is used for creating new hardware notes. Update the file to
reflect the patch.

Reviewed by:    cperciva
Fixes:          4c396c5b7fd7 ("hardware: Update pSeries entries")
Differential Revision:  https://reviews.freebsd.org/D57260
DeltaFile
+3-5website/archetypes/release/hardware.adoc
+3-51 files

FreeBSD/ports bddef8bscience/packmol distinfo Makefile

science/packmol: Update to 21.2.3

ChangeLog:
        https://github.com/m3g/packmol/releases/tag/v21.2.3
        https://github.com/m3g/packmol/releases/tag/v21.2.2
DeltaFile
+3-3science/packmol/distinfo
+1-1science/packmol/Makefile
+4-42 files

LLVM/project 5b38edd.github/workflows pr-code-lint.yml

workflows/pr-code-lint: Pin container image (#199767)

https://github.com/llvm/llvm-project/security/code-scanning/1678
DeltaFile
+1-1.github/workflows/pr-code-lint.yml
+1-11 files

LLVM/project ed918c1llvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/Transforms/AtomicExpand/RISCV atomicrmw-widen-volatile.ll

[AtomicExpand] Preserve volatile in widenPartwordAtomicRMW. (#199722)

widenPartwordAtomicRMW widens a sub-word atomicrmw to the target's
minimum cmpxchg size by calling CreateAtomicRMW, which has no
IsVolatile parameter, and didn't copy isVolatile() from the original.
Every other expansion path in this file already does.  Affects targets
whose MinCmpXchgSizeInBits exceeds the value width (RISC-V without
Zabha, LoongArch base, SPARC, AMDGPU, etc.).

This bug was found by a large run of Opus 4.7 looking for bugs in LLVM.
DeltaFile
+41-0llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-widen-volatile.ll
+1-0llvm/lib/CodeGen/AtomicExpandPass.cpp
+42-02 files

LLVM/project 8275507llvm/utils profcheck-xfail.txt

[ProfCheck] Fix #199174 (#200013)

The patch added another large fp conversion test, which we currently are
missing some profile annotations for, so add it to the xfail list for
now.
DeltaFile
+1-0llvm/utils/profcheck-xfail.txt
+1-01 files