[Clang][RISCV] Add packed widening multiply intrinsics (#217534)
Add the 32-bit forms of the RISC-V P-extension packed widening multiply
intrinsics to riscv_packed_simd.h using generic extend-and-multiply IR.
Recognize the generic widening multiply pattern in the RISC-V backend
and select the spec-listed RV32 instructions and RV64 composed
sequences.
Add Clang CodeGen, LLVM CodeGen, and intrinsic header tests for the new
forms.
[AMDGPU] Fix SIPeepholeSDWA crash on OR with VOPC SDWA operand (#217084)
VOPC SDWA instructions have no dst_sel operand, but the OR folding
pattern assumed that one existed
dns/adns: update 1.6.0 -> 1.6.2, pet repology
- Disable debugging output to stderr from adns_addr2text and
adns_text2addr, when used with exciting values (eg scoped addresses)
- Suppress warning about `trust-ad` in resolv.conf
intelspi: sort PCI ID table by device ID
Sort the existing LPSS peripheral SPI controller PCI ID table by
numeric device ID so new entries have an unambiguous insertion point.
Reviewed by: wulf
Differential Revision: https://reviews.freebsd.org/D58996
intelspi: add Apollo Lake SPI controller IDs
Add PCI device IDs for Apollo Lake-generation LPSS peripheral SPI
controllers.
Reviewed by: adrian
Differential Revision: https://reviews.freebsd.org/D58998
[mlir][acc] Update par_dims format for reduction combine (#217678)
For consistency after https://github.com/llvm/llvm-project/pull/217643
this MR adds par_dims as inherent attribute to reduction_combine as was
intended. And thus ensures consistency in IR printing of this attribute.
[libc] Add pthread_getstack_np extension (#217049)
The function returns the stack (size and address) of the given thread,
much like a combination of pthread_getattr_np+pthread_attr_getstack.
However, unlike that combination, this function is guaranteed to be
async-signal-safe. I'm adding it because guaranteeing
async-signal-safety for pthread_getattr_np is tricky because of the
increased scope. In particular, it's hard to avoid memory allocation as
that function would need to store CPU affinity for an unknown number of
CPUs.
I'm not trying to emulate OpenBSD's
[pthread_stackseg_np](https://man.openbsd.org/pthread_stackseg_np.3) as
we discussed previously, because the function has an unusual interface
(it returns the stack through a stack_t, but it has ss_sp point to the
top of the stack instead of the base). It also does not claim to be
async-signal-safe. With a view towards a standardization attempt, I
tried to design something that fits in with the existing APIs. Note that
this does not mean that the design is final, and I am open to changing
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[flang][openacc] Recurse into OpenACC constructs when matching labeled DO (#217984)
GetFinalLabel() already walked an OpenACC loop or combined construct to
find a shared terminating label, but the Block walker did not recurse
into nested OpenACC constructs. Three labeled DO loops that share one
terminator, each associated with its own !$acc loop, then failed with
"Label is not in DO loop scope".
Look through OpenACCConstruct in GetFinalLabel(const Block &) the same
way OpenMP constructs are already handled.
[flang] Support -gline-directives-only (#217132)
Do the same as -gline-tables-only but set DIEmissionKind to DebugDirectivesOnly instead of LineTablesOnly.
[mlir][ROCDL] Enable useStrictPropertiesInAssemblyFormat
**Migration note:** Separate out inherent and discardable attributes
on your `rocdl.*` operations and put a `<>` around the inherent ones.
This commit adds `prop-dict` clauses to all the ROCDL-dialect
operations that have inherent attributes but don't have better syntax
for them.
I looked at creating better syntaxes here, but these are fairly
low-level operations and it was hard to put together comma-separated
lists of optional arguments in tablegen. So I've gone with the rather
straightforward and consistent fix of adding in `prop-dict`s.
AI note: Claude did the changes here, I reviewed the designs.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
[mlir][AMDGPU] Enable useStrictPropertiesInAssemblyFormat
This is part of the migration to keeping inherent and discardable
attributes separate touched.
**Migration note:** this'll change the syntax of a bunch of `amdgpu`
dialect ops to keep inherent attributes out of the `attr-dict`.
Syntax changes:
1. Operations like the dpp operations have had their inherent operands
turned into oilists that use `name(value)` syntax, such as
`bound_ctrl(false)`, which also leads to the elision of default
values.
2. Buffer operations now use `boundsCheck(true/false)` before the main
operation (keeping the visibility from the old attr-dict) and have
moved to `sgprOffset(%offset)` and `indexOffset(constant)` as optional
syntax alements after the main specification.
3. WMMA operations also now have the same `attribute[(value)]` element
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[mlir] Don't print a stray space for a fully-elided prop-dict (#216810)
**Migration note**: if you have a custom `prop-dict` printer, add a
leading space into the format - it'll no longer be printed implicitly.
The `prop-dict` printer generated by mlir-tblgen would always print
a space before dispatching to printProperties(). When every property is
elided (because it is bound elsewhere in the assembly format or matches
its default value) printProperties() prints nothing, leaving a stray
space in the output. We had a test TODO about this.
This PR makes the leading space the responsibility of the properties
printer, so
it's emitted only when needed. The generic
printer in OpState::genericPrintProperties() and all in-tree custom
printers have been updated accordingly.
XeGPU had worked around the stray space by writing an empty space
directive (``) after prop-dict to suppress the space before ':'. Those
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[SimpleLoopUnswitch] Tweak token live-out behavior (#217916)
The previous check (moved into Loop::isSafeToCloneConditionally in the
preceding NFC commit) rejected any token instruction with a use outside
its defining basic block. This is both too strict and too lax:
- Too strict: cloning only requires forming phis for values that are
live-out of the *loop*. Token uses that cross blocks but stay within the
loop are cloned along with their defs and need no phis, so they do not
inhibit non-trivial unswitching.
- Too lax: `isTokenTy()` misses token-like target extension types
(`isTokenLikeTy()`), which cannot be used in phi nodes either. A
live-out token-like value would have made unswitching produce invalid
IR.
Switch the check to reject exactly the token-like values that are
live-out of the loop, reusing the same use-scanning logic as
`isBlockInLCSSAForm` (`loopContainsUser`): a use in a phi is treated as
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[DAG] Remove trivial VP SDNodes. NFC
This removes the codegen parts of the trivial VP intrinsics. It's quite far reaching, but the general categories of code removed are:
- Removing definitions from VPIntrinsics.def
- Legalization and expansion code
- MatchContext used to match over both VP and non-VP nodes
- Some dead DAGCombines and folds in SelectionDAGBuilder
There are still more things to be cleaned up after this, e.g. removing more of the VPIntrinsic class hierarchy, removing ExpandVectorPredication/moving expansion into other places, removing MatchContext from SDPatternMatch
[DAG] Expand vp.*rem and vp.cttz.elts with non-vp nodes.
Trivial VP SDNodes will be removed in an upcoming patch. The division is still predicated so we avoid UB.
[IR] Remove trivial VP intrinsics. NFC (#217863)
Trivial VP intrinsics are now all autoupgraded to their non-VP
counterparts, so the intrinsics themselves are dead.
This removes the intrinsics and their corresponding LangRef definitions,
as well as the VPIntrinsic subclasses and some methods in
ExpandVectorPredication which are now dead. Removing the SDNodes is
deferred to a separate patch.
RFC: https://discourse.llvm.org/t/rfc-remove-trivial-vp-intrinsics/90972
