OPNSense/core 67d6f60src/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Firewall Rules: clean this up as well
DeltaFile
+29-32src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+29-321 files

LLVM/project 6019583llvm/utils/TableGen GlobalISelCombinerEmitter.cpp GlobalISelEmitter.cpp, llvm/utils/TableGen/Common/GlobalISel/MatchTable Matchers.cpp Matchers.h

[NFC][GlobalISel] Refactor ownership of InstructionMatchers (#200798)

- Clarify that the array of InstructionMatchers in the RuleMatcher are
for the roots only.
- Let RuleMatcher own all of the InstructionMatcher used for/by
predicates.
They are all kept in an array in which the index of the
InstructionMatcher is equal to its
InsnID, which eliminates some redundant tracking.
- Remove duplicate tracking of InsnID from RuleMatcher;
InstructionMatcher does it on its own already.

Co-authored-by: Pierre-vh <29600849+Pierre-vh at users.noreply.github.com>
DeltaFile
+48-64llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
+29-43llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
+3-3llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+2-2llvm/utils/TableGen/GlobalISelEmitter.cpp
+82-1124 files

LLVM/project 06a0c06llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp, llvm/test/CodeGen/AMDGPU memory-legalizer-non-volatile.mir

Comments
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.mir
+1-1llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+4-42 files

FreeBSD/ports 78fa189sysutils Makefile, sysutils/reqlog Makefile pkg-descr

sysutils/reqlog: New port: Search, trace, and stream logs
DeltaFile
+19-0sysutils/reqlog/Makefile
+7-0sysutils/reqlog/pkg-descr
+5-0sysutils/reqlog/distinfo
+1-0sysutils/Makefile
+32-04 files

FreeBSD/ports bf43367editors Makefile, editors/croft distinfo Makefile.crates

editors/croft: New port: VS Code style terminal editor
DeltaFile
+855-0editors/croft/distinfo
+426-0editors/croft/Makefile.crates
+25-0editors/croft/Makefile
+10-0editors/croft/pkg-descr
+1-0editors/Makefile
+1,317-05 files

FreeBSD/ports da7084ddatabases Makefile, databases/memtui Makefile pkg-descr

databases/memtui: New port: Modern TUI client for Memcached
DeltaFile
+19-0databases/memtui/Makefile
+8-0databases/memtui/pkg-descr
+5-0databases/memtui/distinfo
+1-0databases/Makefile
+33-04 files

LLVM/project 8455183llvm/utils/TableGen GlobalISelEmitter.cpp GlobalISelCombinerEmitter.cpp, llvm/utils/TableGen/Common/GlobalISel/MatchTable Matchers.cpp Matchers.h

[GlobalISel] Do not depend on the RuleMatcher at MatchTable emission (#200799)

Some PredicateMatchers/MatchAction/OperandRenderers relied on accessing
RuleMatcher at emission as a crutch.
Instead, make these classes collect all necessary information in the
constructor so the `emit` methods don't depend on RuleMatcher anymore.

The primary motivation for this is that I've been looking at ways to optimize the MatchTable better,
and the fact that Predicates/Actions/Renderers are not "pure" objects, in the sense that they keep
accessing a bunch of data all over the place even as late as emission, was a consistent pain.

This is NFCI. There are no changes to any of the match table for AMDGPU/AArch64 in this patch.

This patch has a bunch of noise due to function signature changes so I'll highlight the following interesting changes:
- `SameOperandMatcher` needed a bit of an update in its `canHoistOutsideOf` function. I had to rewrite it
  but I think the end result is the same.
- `EraseInstAction` has been updated as well, and its users in both Combiner/ISel backends have been updated to.
  Instead of ignoring this action if the Inst was already erased, it's now the responsibility of the
  builder to never insert it in the first place. `BuildMIAction` had a small update because of that too.

    [4 lines not shown]
DeltaFile
+109-194llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
+161-134llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
+21-19llvm/utils/TableGen/GlobalISelEmitter.cpp
+7-5llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+298-3524 files

LLVM/project a4d1cb4llvm/utils/TableGen GlobalISelCombinerEmitter.cpp GlobalISelEmitter.cpp, llvm/utils/TableGen/Common/GlobalISel/MatchTable Matchers.cpp Matchers.h

[NFC][GlobalISel] Refactor ownership of InstructionMatchers (#200798)

- Clarify that the array of InstructionMatchers in the RuleMatcher are for the roots only.
- Let RuleMatcher own all of the InstructionMatcher used for/by predicates.
They are all kept in an array in which the index of the InstructionMatcher is equal to its
InsnID, which eliminates some redundant tracking.
- Remove duplicate tracking of InsnID from RuleMatcher; InstructionMatcher does it on its own already.
DeltaFile
+48-64llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
+29-43llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
+3-3llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+2-2llvm/utils/TableGen/GlobalISelEmitter.cpp
+82-1124 files

LLVM/project b47d4bcllvm/docs AMDGPUUsage.rst, llvm/test/CodeGen/AMDGPU memory-legalizer-non-volatile.ll memory-legalizer-non-volatile.mir

Restack + comments
DeltaFile
+2-14llvm/docs/AMDGPUUsage.rst
+4-4llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
+1-1llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.mir
+7-193 files

LLVM/project 2f1c759llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp SIInstrInfo.h

[AMDGPU][SIMemoryLegalizer] Consider scratch operations as NV=1 if GAS is disabled

- Clarify that `thread-private` MMO flag is still useful.
- If GAS is not enabled (which is the default as of last patch), consider an op as `NV=1` if it's a `scratch_` opcode, or if the MMO is in the private AS.
- Add tests for the new cases.
- Update AMDGPUUsage GFX12.5 memory model
DeltaFile
+181-0llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.mir
+75-36llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
+13-6llvm/docs/AMDGPUUsage.rst
+14-3llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+3-1llvm/lib/Target/AMDGPU/SIInstrInfo.h
+286-465 files

LLVM/project b44c2a4llvm/test/CodeGen/AMDGPU memory-legalizer-non-volatile.mir

Fix MIR test
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.mir
+3-31 files

LLVM/project 1d88b83llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU GCNSubtarget.cpp AMDGPU.td

Comments
DeltaFile
+74-64llvm/docs/AMDGPUUsage.rst
+9-0llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+1-7llvm/lib/Target/AMDGPU/AMDGPU.td
+1-4llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll
+1-1llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
+87-778 files not shown
+95-8514 files

LLVM/project 6c33fecllvm/test/CodeGen/AMDGPU memory-legalizer-private-singlethread.ll memory-legalizer-private-wavefront.ll

Rebase
DeltaFile
+1,994-950llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
+1,994-950llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+1,994-950llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
+1,971-939llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
+1,971-939llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
+1,879-899llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
+11,803-5,6276 files

LLVM/project a0fe215llvm/test/CodeGen/AMDGPU memory-legalizer-private-agent.ll memory-legalizer-private-system.ll

[AMDGPU] Make globally-addressable-scratch opt-in

This feature is meant to be opt-in for more advanced users, not default-enabled.
It may reduce performance otherwise as we can't assume private AS is thread-local
when it is enabled.

- Add `HasGloballyAddressableScratchSupport` feature to check if a target's scratch
  addressing is changed due to support for globally addressable scratch.
- Use `EnableGloballyAddressableScratch` to check whether the user opted into
  globally addressable scratch. This affects whether to lower scratch atomics as flat,
  and in the future will affect whether NV=1 can be set on scratch accesses.
DeltaFile
+4,816-4,142llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
+4,584-3,938llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
+4,595-3,921llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
+4,564-3,881llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
+4,412-3,729llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
+4,412-3,729llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
+27,383-23,34013 files not shown
+27,647-23,49719 files

LLVM/project 73802c2offload/test/offloading array_reductions.cpp multiple_reductions.cpp

[OpenMP][offload] Add enhanced array-reduction tests (#201040)
DeltaFile
+172-0offload/test/offloading/array_reductions.cpp
+2-0offload/test/offloading/multiple_reductions.cpp
+174-02 files

LLVM/project f02dd4allvm/lib/Analysis CaptureTracking.cpp, llvm/test/Transforms/Attributor nofpclass.ll

[CaptureTracking] Volatile operations only capture address (#201316)

The fact that a volatile access was performed on a certain address is an
observable effect in the abstract machine, so volatile operations
capture the address of the accessed pointer. However, they do not
capture the provenance. This matches what we document in LangRef.

While I'm pretty sure that this models the semantics correctly, I'm
slightly concerned that we might be using the provenance capture here to
paper over some other issue, though nothing specific comes to mind (and
the test changes don't show anything problematic).
DeltaFile
+28-61llvm/test/Transforms/Attributor/nofpclass.ll
+18-13llvm/lib/Analysis/CaptureTracking.cpp
+13-13llvm/test/Transforms/FunctionAttrs/nofpclass.ll
+11-5llvm/test/Transforms/FunctionAttrs/nonnull.ll
+4-4llvm/test/Transforms/FunctionAttrs/initializes.ll
+2-2llvm/test/Transforms/FunctionAttrs/atomic.ll
+76-989 files not shown
+86-10815 files

LLVM/project 375fa6fllvm/lib/Analysis Loads.cpp, llvm/test/Analysis/ValueTracking memory-dereferenceable.ll

[Loads] Use willNotFreeBetween() for dereferenceable-at-point (#201353)

If dereferenceable-at-point semantics are enabled, use
willNotFreeBetween() to check whether frees are known to not occur
between the definition point of the value and the context instruction.

We already use this logic for dereferenceable assumptions, this enables
it for other dereferenceability fact (under deref-at-point).
DeltaFile
+75-0llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll
+24-3llvm/lib/Analysis/Loads.cpp
+99-32 files

LLVM/project 96c0f5alldb/include/lldb/Target Memory.h Process.h, lldb/source/Target Memory.cpp Process.cpp

[lldb] Use MemoryCache in Process::ReadRangesFromMemory (#201166)

There are scenarios (especially in the ObjectiveC metadata reading) in
which multiple strings are read over and over again, but through
different code paths. In order to make that part of the code use
MultiMemRead effectively, the memory cache must be integrated into
ReadRangesFromMemory before we can migrate the string reading to
vectorized version.
DeltaFile
+51-0lldb/source/Target/Memory.cpp
+14-0lldb/include/lldb/Target/Memory.h
+1-1lldb/unittests/Target/MemoryTest.cpp
+2-0lldb/source/Target/Process.cpp
+1-0lldb/include/lldb/Target/Process.h
+69-15 files

OPNSense/src 68047c9sys/net rss_config.c if_gre.c, sys/netinet ip_input.c

rss: add sysctl enable toggle

This commit also includes the original refactoring changes

This change allows the kernel to operate with the default netisr cpu-affinity settings while having RSS compiled in. Normally, RSS changes quite a bit of the behaviour of the kernel dispatch service - this change allows for reducing impact on incompatible hardware while preserving the option to boost throughput speeds based on packet flow CPU affinity.

Make sure to compile the following options in the kernel:

    options  RSS

As well as setting the following sysctls:

    net.inet.rss.enabled: 1
    net.isr.bindthreads: 1
    net.isr.maxthreads: -1 (automatically sets it to the number of CPUs)

And optionally (to force a 1:1 mapping between CPUs and buckets):

    net.inet.rss.bits: 3 (for 8 CPUs)

    [5 lines not shown]
DeltaFile
+37-1sys/net/rss_config.c
+20-0sys/netinet6/ip6_input.c
+19-0sys/netinet/ip_input.c
+12-7sys/net/if_gre.c
+7-0sys/netinet6/frag6.c
+6-0sys/netinet6/ip6_output.c
+101-811 files not shown
+131-1017 files

LLVM/project bdd7b4cflang/lib/Semantics resolve-names.cpp, flang/test/Semantics entry01.f90

[Flang][Semantics] Throw diagnostics for identical entry and result names. (#198500)

Fixes https://github.com/llvm/llvm-project/issues/198499

In flang entry name and result names cannot be same as per
[C1583](https://j3-fortran.org/doc/year/25/25-007r1.pdf).
Previously, Flang did not diagnose cases where the ENTRY name and RESULT
name were identical, e.g.
```
 function m1f1()
  integer :: m1f1
  real :: m1f1e1
  m1f1 = 0
  entry m1f1e1() result(m1f1e1)
  m1f1e1 = 0.1
end function
```
DeltaFile
+8-2flang/lib/Semantics/resolve-names.cpp
+2-1flang/test/Semantics/entry01.f90
+10-32 files

LLVM/project b8c18e9mlir/lib/Conversion/ArithToLLVM ArithToLLVM.cpp, mlir/test/Conversion/ArithToLLVM arith-to-llvm.mlir

[mlir][ArithToLLVM] Lower arith.subui_extended (#197737)
DeltaFile
+49-0mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
+24-0mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
+73-02 files

LLVM/project ee1fe94mlir/lib/Dialect/Arith/Transforms EmulateWideInt.cpp, mlir/test/Dialect/Arith emulate-wide-int.mlir

[mlir][arith] Use subui_extended in wide integer emulation of subi (#197762)
DeltaFile
+10-14mlir/test/Dialect/Arith/emulate-wide-int.mlir
+9-9mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
+19-232 files

LLVM/project 364a883clang/lib/Driver/ToolChains Flang.cpp, flang/test/Driver frelaxed-c-loc-checks.f90

[Flang] Fix -frelaxed-c-loc-checks being ignored when using the driver (#200733)

`-frelaxed-c-loc-checks` worked correctly when passed directly to -fc1,
but was silently ignored when using the driver (e.g., flang -c
-frelaxed-c-loc-checks), causing the flag to go unused. This patch fixes
it by adding `OPT_relaxed_c_loc` to the `addAllArgs` call in Flang.cpp
Also extend the existing test with a driver-mode RUN line to cover this
path.
DeltaFile
+4-0flang/test/Driver/frelaxed-c-loc-checks.f90
+2-1clang/lib/Driver/ToolChains/Flang.cpp
+6-12 files

FreeBSD/ports df84c7fmisc/R-cran-xfun distinfo Makefile

misc/R-cran-xfun: Update to 0.58

Changelog: https://github.com/yihui/xfun/releases/tag/v0.58
DeltaFile
+3-3misc/R-cran-xfun/distinfo
+1-1misc/R-cran-xfun/Makefile
+4-42 files

FreeBSD/ports 47499f5www/redmine60/files patch-Gemfile

www/redmine60: chase rubygem mail 2.9.0 update.
DeltaFile
+2-1www/redmine60/files/patch-Gemfile
+2-11 files

LLVM/project b8cc594mlir/include/mlir/Conversion Passes.td, mlir/lib/Conversion/TosaToSPIRVTosa TosaToSPIRVTosaConstants.cpp TosaToSPIRVTosaPass.cpp

[mlir][spirv] Add TOSA graph constant marking (#201095)

Add a TOSA to SPIR-V TOSA preprocessing pass that marks large tosa.const
and tosa.const_shape operations for lowering to spirv.ARM.GraphConstant.

Keep small constants inline as spirv.Constant, assign graph constant IDs
with a grapharm-prefixed marker attribute, and teach the existing
constant conversion to use the marker when present.

Expose the grapharm source-side attribute names used for interface ABI
annotations and graph constant IDs.

Add tests for marking large constants, leaving small constants unmarked,
increasing graph constant IDs across mixed constants, and lowering
pre-marked constants to spirv.ARM.GraphConstant.

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+92-0mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaConstants.cpp
+48-0mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-mark.mlir
+23-1mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaPass.cpp
+23-0mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-invalid.mlir
+18-0mlir/test/Conversion/TosaToSPIRVTosa/tosa-to-spirv.mlir
+14-2mlir/include/mlir/Conversion/Passes.td
+218-35 files not shown
+256-1011 files

LLVM/project 192c013llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 dup.ll

[AArch64] Fix DUP-of-extload combine to ignore chain uses (#201351)

The original combine bailed when the load had more than one use, but
counted chain uses too.
DeltaFile
+6-6llvm/test/CodeGen/AArch64/dup.ll
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+7-72 files

OpenBSD/ports H7tIvbVdevel/autogen Makefile, devel/autogen/patches patch-config_ag_macros_m4 patch-agen5_test_error_test

   autogen: unbreak build with llvm22, ok jca

   The {,sig}setjmp() detection was broken. They want a sigjmp_buf, not a
   sigjmp_buf *, so change from &bf to bf twice to avoid a configure time
   error due to a -Wincompatible-pointer-types error.

   As naddy points out, this port could be only one decade outdated rather
   than almost two. I may deal with this when I find myself very bored.
VersionDeltaFile
1.1+21-0devel/autogen/patches/patch-config_ag_macros_m4
1.3+4-3devel/autogen/patches/patch-agen5_test_error_test
1.29+3-1devel/autogen/Makefile
+28-43 files

LLVM/project 3192648orc-rt/include/orc-rt NativeDylibManager.h, orc-rt/lib/executor NativeDylibManager.cpp

[orc-rt] Make NativeDylibManager::lookup return optional addresses. (#201519)

NativeDylibManager::lookup used to return (asynchronously) a vector of
void *s where null represented not-present. This commit updates it to
return a vector of std::optional<void *>s where std::nullopt represents
not-present and an address of zero indicates that the symbol is present
with an address of zero.

This matches the resolve semantics of SimpleExecutorDylibManager,
completing the alignment of the two implementations after the earlier
additions of the Mode argument to load() and the
required/weakly-referenced flag on lookup symbols.
DeltaFile
+32-18orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
+28-17orc-rt/unittests/NativeDylibManagerTest.cpp
+8-16orc-rt/lib/executor/NativeDylibManager.cpp
+15-5orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
+6-4orc-rt/include/orc-rt/NativeDylibManager.h
+1-1orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
+90-616 files

NetBSD/pkgsrc KGWclP0doc CHANGES-2026

   Updated net/freeradius
VersionDeltaFile
1.3489+2-1doc/CHANGES-2026
+2-11 files