LLVM/project dbebcb0mlir/lib/Target/SPIRV/Deserialization DeserializeOps.cpp

[mlir][spirv] Remove unnecessary assertion (#200137)

The use of the variable in the assertion was causing a build failure
when compiling with assertion off and hence the variable becomes unused.

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+0-3mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp
+0-31 files

LLVM/project 1e348callvm/docs AMDGPUMemoryModel.rst

new mmra syntax; use system scope; fix indentation; fix chains;
DeltaFile
+27-24llvm/docs/AMDGPUMemoryModel.rst
+27-241 files

LLVM/project aa0d012llvm/utils/TableGen/Common/GlobalISel GlobalISelMatchTable.h GlobalISelMatchTable.cpp, llvm/utils/TableGen/Common/GlobalISel/MatchTable Matchers.h Matchers.cpp

[NFC][TableGen] Reorganize GlobalISelMatchTable.h

This file was a bit of a kitchen sink, and the implementation of the
match table is sufficiently difficult to get comfortable with already.
I spent the past few weeks looking at it, finding improvements, etc. and
I think a nice way to make it a bit easier to approach is to split up
the file a bit so that the main implementation (Matchers.h/.cpp) only
contains the code pertaining to the Matchers (RuleMatchers, Preds, etc.).

We now have 3 files:

- One for type (LLT) related utilities.
- One for the MatchTable emission logic, which is generic and should not
  be tied to any specific implementation. It just has the tools to emit
  the opcodes for the table.
- One for the entire Matcher system, including PredicateMatchers and so on.
DeltaFile
+0-2,624llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
+0-2,619llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+2,414-0llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
+2,250-0llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
+253-0llvm/utils/TableGen/Common/GlobalISel/MatchTable/MatchTable.cpp
+180-0llvm/utils/TableGen/Common/GlobalISel/MatchTable/MatchTable.h
+5,097-5,2436 files not shown
+5,353-5,25112 files

FreeBSD/ports caec74ctextproc/moor distinfo Makefile

textproc/moor: Update 2.13.2 => 2.13.3

Changelog:
https://github.com/walles/moor/releases/tag/v2.13.3

Approved by:    osa, vvd (Mentors, implicit)
DeltaFile
+5-5textproc/moor/distinfo
+1-1textproc/moor/Makefile
+6-62 files

LLVM/project eb1b57cllvm/docs LangRef.rst

[LangRef] Specify that syncscopes can affect the monotonic modification order (#189017)

If a target specifies that atomics with mismatching syncscopes appear
non-atomic to each other, there is no point in requiring them to be ordered in
the monotonic modification order. Notably, the [AMDGPU target user
guide](https://llvm.org/docs/AMDGPUUsage.html#memory-scopes) has specified
syncscopes to relax the modification order for years.

So far, I haven't found an example where this less constrained ordering would
be observable (at least with the AMDGPU inclusive scope rules). Whenever a load
would be able to see two monotonic stores with non-inclusive scope, that's
considered a data race (i.e., the load would return `undef`), so it cannot be
used to observe the order of the stores.

Related RFC: https://discourse.llvm.org/t/rfc-clarifying-llvm-irs-concurrent-memory-model/90480
DeltaFile
+12-8llvm/docs/LangRef.rst
+12-81 files

FreeBSD/ports daffc46chinese/ibus-rime distinfo Makefile

chinese/ibus-rime: Update 1.6.0 => 1.6.1

While here, add missing depends from stage-qa

Changelog:
https://github.com/rime/ibus-rime/blob/1.6.1/CHANGELOG.md
Commit log:
https://github.com/rime/ibus-rime/compare/1.6.0...1.6.1

PR:             295612
Reported by:    Eric Camachat <eric at camachat.org> (maintainer)
Approved by:    osa, vvd (Mentors, implicit)
MFH:            2026Q2

(cherry picked from commit 71ff0031321ee94450c6678dffa5abe870040a78)
DeltaFile
+3-3chinese/ibus-rime/distinfo
+3-2chinese/ibus-rime/Makefile
+6-52 files

LLVM/project a554a19clang/test/Driver dxc_section_emission.hlsl, llvm/lib/Target/DirectX DXContainerGlobals.cpp

[DirectX] Generate shader debug file name part in llc (#199555)

This change modifies DXContainerGlobals pass to generate debug name
(ILDN) part in DXContainer. ILDN part allows consumers to find PDB file
containing shader debug info.

As ILDB emission PR is not merged yet, and PDB file creation is not
upstreamed yet, debug name is generated based on MD5-hash of bitcode
module in DXIL part.
This corresponds to DXC behavior when a shader is compiled with `/Zi
/Qembed_debug /Zsb` flags (with `/Qembed_debug`, DXC does not produce an
actual PDB file, but still emits ILDN, `/Zsb` tells DXC to use bitcode
from DXIL to compute hash).
However, here ILDN is emitted for any debug info flag configuration.
assuming that it won't break debug info consumers, and that PDB creation
will be added later.
DeltaFile
+42-10llvm/lib/Target/DirectX/DXContainerGlobals.cpp
+38-0llvm/test/CodeGen/DirectX/ContainerData/DebugName-DXIL.ll
+25-0clang/test/Driver/dxc_section_emission.hlsl
+12-0llvm/test/CodeGen/DirectX/lit.local.cfg
+117-104 files

FreeBSD/ports 71ff003chinese/ibus-rime distinfo Makefile

chinese/ibus-rime: Update 1.6.0 => 1.6.1

While here, add missing depends from stage-qa

Changelog:
https://github.com/rime/ibus-rime/blob/1.6.1/CHANGELOG.md
Commit log:
https://github.com/rime/ibus-rime/compare/1.6.0...1.6.1

PR:             295612
Reported by:    Eric Camachat <eric at camachat.org> (maintainer)
Approved by:    osa, vvd (Mentors, implicit)
MFH:            2026Q2
DeltaFile
+3-3chinese/ibus-rime/distinfo
+3-2chinese/ibus-rime/Makefile
+6-52 files

LLVM/project 8023956llvm/docs LangRef.rst

[LangRef] Specify that syncscopes can affect the monotonic modification order (#189017)

If a target specifies that atomics with mismatching syncscopes appear
non-atomic to each other, there is no point in requiring them to be ordered in
the monotonic modification order. Notably, the [AMDGPU target user
guide](https://llvm.org/docs/AMDGPUUsage.html#memory-scopes) has specified
syncscopes to relax the modification order for years.

So far, I haven't found an example where this less constrained ordering would
be observable (at least with the AMDGPU inclusive scope rules). Whenever a load
would be able to see two monotonic stores with non-inclusive scope, that's
considered a data race (i.e., the load would return `undef`), so it cannot be
used to observe the order of the stores.

Related RFC: https://discourse.llvm.org/t/rfc-clarifying-llvm-irs-concurrent-memory-model/90480
DeltaFile
+12-8llvm/docs/LangRef.rst
+12-81 files

LLVM/project b115dd1llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/test/CodeGen/AArch64 special-reg.ll machine-sme-abi-find-insert-pt.mir

[AArch64] Fix definition of system register move instructions (#185709)

Current implementation of these instructions makes bit20 in the encoding
part of the system register operand, which is incorrect since
[specification](https://developer.arm.com/documentation/ddi0602/latest)
specifies that bit must be set to 1. This patch changes that and removes
the bit 20 from the encoding of the operand and makes it fixed field for
these instructions. It also fixes the parser and codegen by checking
that Op0 in system register name/encoding is correctly constrained to 2
or 3.

Depends on #185970
DeltaFile
+1,044-1,044llvm/lib/Target/AArch64/AArch64SystemOperands.td
+19-17llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
+24-11llvm/test/CodeGen/AArch64/special-reg.ll
+17-17llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
+13-13llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir
+26-0llvm/test/CodeGen/AArch64/arm64-invalid-sys-reg.ll
+1,143-1,10228 files not shown
+1,345-1,20334 files

FreeBSD/ports d8cfc25x11/histui distinfo Makefile

x11/histui: Update to 0.0.11

ChangeLog:      https://github.com/jmylchreest/histui/releases/tag/v0.0.11
Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+5-5x11/histui/distinfo
+2-2x11/histui/Makefile
+7-72 files

LLVM/project 51d8231compiler-rt/include/sanitizer tysan_interface.h, compiler-rt/lib/tysan tysan_interceptors.cpp tysan.h

[TySan] Expose __tysan_set_type_unknown interface (#198800)

This can help work around issues like
[#143587](https://github.com/llvm/llvm-project/issues/143587)
The function is renamed with two trailing underscores to match the
naming scheme of the other sanitizers.
DeltaFile
+12-12compiler-rt/lib/tysan/tysan_interceptors.cpp
+21-0compiler-rt/test/tysan/set_type_unknown-interface.c
+8-1compiler-rt/include/sanitizer/tysan_interface.h
+1-1compiler-rt/lib/tysan/tysan.h
+1-1compiler-rt/lib/tysan/tysan.cpp
+43-155 files

OPNSense/core f058c12src/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Tweak previous, also offer 20 as option for small screen devices
DeltaFile
+1-1src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+1-11 files

LLVM/project 66ee43cclang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaLifetimeSafety.h

[LifetimeSafety] Improve diagnostics for use-after-scope (#200031)

Reuses the function for getting object information that was added in
#199432

Comes as part of completing #186002

Co-authored-by: Utkarsh Saxena <usx at google.com>
DeltaFile
+142-141clang/test/Sema/warn-lifetime-safety.cpp
+44-44clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
+6-6clang/test/Sema/warn-lifetime-safety-suggestions.cpp
+6-4clang/lib/Sema/SemaLifetimeSafety.h
+3-3clang/include/clang/Basic/DiagnosticSemaKinds.td
+2-2clang/test/Sema/warn-lifetime-safety-cfg-bailout.cpp
+203-2006 files

FreeBSD/ports a3926b6x11/xwaylandvideobridge Makefile distinfo, x11/xwaylandvideobridge/files patch-CMakeLists.txt

x11/xwaylandvideobridge: Update to 0.5.0
DeltaFile
+0-15x11/xwaylandvideobridge/files/patch-CMakeLists.txt
+4-8x11/xwaylandvideobridge/Makefile
+3-3x11/xwaylandvideobridge/distinfo
+3-0x11/xwaylandvideobridge/pkg-plist
+10-264 files

FreeBSD/ports a250cd2. MOVED, x11/xwaylandvideobridge pkg-plist Makefile

x11/xwaylandvideobridge: Restore port
DeltaFile
+32-0x11/xwaylandvideobridge/pkg-plist
+29-0x11/xwaylandvideobridge/Makefile
+15-0x11/xwaylandvideobridge/files/patch-CMakeLists.txt
+6-0x11/xwaylandvideobridge/pkg-descr
+3-0x11/xwaylandvideobridge/distinfo
+0-1MOVED
+85-11 files not shown
+86-17 files

FreeBSD/ports 80243fdsysutils/treemd distinfo Makefile.crates

sysutils/treemd: Update to 0.5.11

ChangeLog:      https://github.com/Epistates/treemd/releases/tag/v0.5.11
Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+245-207sysutils/treemd/distinfo
+121-102sysutils/treemd/Makefile.crates
+2-2sysutils/treemd/Makefile
+368-3113 files

OpenBSD/src YBh5kkpsbin/iked pfkey.c, sbin/isakmpd pf_key_v2.c

   Avoid infinite loop when parsing PFKEY replies

   In bgpd, iked, isakmpd, ldpd and sasyncd we have similar code to
   parse PFKEY replies from the kernel.  To avoid an infinite loop on
   malformed replies validate the SADB extension size.

   For consistency with the other daemons rewrite the parsing loop of
   iked.

   sasyncd already validates the extension size, so no change needed.

   ok claudio@ tb@ tobhe@
VersionDeltaFile
1.86+8-6sbin/iked/pfkey.c
1.206+5-2sbin/isakmpd/pf_key_v2.c
1.74+3-1usr.sbin/bgpd/pfkey.c
1.14+3-1usr.sbin/ldpd/pfkey.c
+19-104 files

LLVM/project 9f5df3ccompiler-rt/lib/builtins/arm floatsidf.S floatunsdidf.S

Update for rename of crt_endian.h
DeltaFile
+1-1compiler-rt/lib/builtins/arm/floatsidf.S
+1-1compiler-rt/lib/builtins/arm/floatunsdidf.S
+1-1compiler-rt/lib/builtins/arm/floatunssidf.S
+1-1compiler-rt/lib/builtins/arm/floatdidf.S
+1-1compiler-rt/lib/builtins/arm/floatdisf.S
+5-55 files

LLVM/project 6b66808llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge from main
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+583,792-20,92323,063 files not shown
+2,663,308-745,31023,069 files

LLVM/project 2b53e12llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll gfx-callable-argument-types.ll

Rebase, address comment

Created using spr 1.3.7
DeltaFile
+7,498-6,528llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,501-2,502llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+2,151-2,154llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+1,981-1,979llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,802-1,805llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+1,502-1,500llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+17,435-16,468759 files not shown
+58,530-31,524765 files

OPNSense/core 1603a9fsrc/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Higher default rowCount because all rules is the default view and we always show automatic rules now which inflates count here.
DeltaFile
+1-0src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+1-01 files

LLVM/project 0c741c6compiler-rt/lib/builtins/arm floatsisf.S floatunssisf.S

Reverse all the #if !__thumb__
DeltaFile
+26-30compiler-rt/lib/builtins/arm/floatsisf.S
+21-21compiler-rt/lib/builtins/arm/floatunssisf.S
+6-6compiler-rt/lib/builtins/arm/floatdidf.S
+6-6compiler-rt/lib/builtins/arm/floatunsdidf.S
+6-6compiler-rt/lib/builtins/arm/floatdisf.S
+65-695 files

OPNSense/core 16a929asrc/opnsense/mvc/app/views/OPNsense/Firewall filter_rule.volt

Change title of the category grouping button
DeltaFile
+1-1src/opnsense/mvc/app/views/OPNsense/Firewall/filter_rule.volt
+1-11 files

LLVM/project 172ea47llvm/lib/Target/AMDGPU VOPDInstructions.td SIInstrInfo.td, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[AMDGPU] Use separate tables for VOPD3X and VOPDY in `getCanBeVOPD` (NFC) (#199072)

With this change tables for valid VOPD3X (VOPDX still uses
`getVOPDComponentHelper`) and VOPDY operations are
generated through TableGen. This simplifies the look-up
leading to a 2-3% compile-time speed-up for tested shaders
where `getCanBeVOPD` is on a hot path.

Assisted-by: Claude Code
DeltaFile
+21-21llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+24-0llvm/lib/Target/AMDGPU/VOPDInstructions.td
+22-1llvm/lib/Target/AMDGPU/SIInstrInfo.td
+67-223 files

LLVM/project cee1c3bmlir/include/mlir/Dialect/Tosa/IR TargetEnv.h TosaOps.td, mlir/lib/Dialect/Tosa/IR TosaCanonicalizations.cpp TargetEnv.cpp

[mlir][tosa] Limit consecutive concat rewrite to MAX_TENSOR_LIST_SIZE (#199051)

Previously folding could produce an operation that would later be
considered invalid in validation due to the number of operands it has.
This change adds a check to prevent rewriting consecutive concat
operations if the resulting operation has more than MAX_TENSOR_LIST_SIZE
operands, based on the selected target environment level. If no level is
specified, folding will proceed as before.

In addition, this change rewrites the concat folder as a
canonicalization pattern, since it is not a fold of constant operands.
The change also consolidates testing in
canonicalize.mlir.
DeltaFile
+0-93mlir/test/Dialect/Tosa/fold_concats.mlir
+54-35mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
+88-0mlir/test/Dialect/Tosa/canonicalize.mlir
+6-10mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h
+10-0mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp
+0-1mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
+158-1396 files

LLVM/project 174eb79compiler-rt/lib/builtins/arm fixdfdi.S fixunsdfdi.S, compiler-rt/test/builtins/Unit fixunsdfsinew_test.c

[compiler-rt][ARM] Optimized FP -> integer conversions (#179927)

This commit adds a total of 8 new functions, all converting a
floating-point number to an integer, varying in 3 independent choices:

* input float format (32-bit or 64-bit)
* output integer size (32-bit or 64-bit)
* output integer type (signed or unsigned)
DeltaFile
+251-0compiler-rt/test/builtins/Unit/fixunsdfsinew_test.c
+211-0compiler-rt/lib/builtins/arm/fixdfdi.S
+159-0compiler-rt/lib/builtins/arm/fixunsdfdi.S
+138-0compiler-rt/lib/builtins/arm/fixsfdi.S
+132-0compiler-rt/lib/builtins/arm/fixdfsi.S
+129-0compiler-rt/lib/builtins/arm/fixunsdfsi.S
+1,020-011 files not shown
+2,002-017 files

FreeBSD/src a667352usr.sbin/virtual_oss/virtual_oss main.c virtual_oss.8

virtual_oss(8): Create loopback devices with GID_AUDIO

Make sure the user is part of the audio group to avoid unintended
snooping of loopback audio by unprivileged users.

While here, retire voss_dsp_perm, since we don't use the same value
everywhere now.

Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Reviewed by:    emaste
Pull-Request:   https://ron-dev.freebsd.org/FreeBSD/src/pulls/26

(cherry picked from commit 5f904cb1b05c94453727abb606d6109fe504b10b)
DeltaFile
+22-5usr.sbin/virtual_oss/virtual_oss/main.c
+3-1usr.sbin/virtual_oss/virtual_oss/virtual_oss.8
+25-62 files

FreeBSD/src a181c51etc group, sys/sys conf.h

Add audio group

To be initially used by virtual_oss(8) loopback devices.

Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Reviewed by:    emaste
Pull-Request:   https://ron-dev.freebsd.org/FreeBSD/src/pulls/26

(cherry picked from commit 6024e3f99a1e3f5e52fd50c26789fc2dc98fd9c1)
DeltaFile
+1-0etc/group
+1-0sys/sys/conf.h
+2-02 files

FreeBSD/src 6524505libexec/rc/rc.d virtual_oss

rc: virtual_oss: Create a loopback device in the default configuration

The loopback device allows us to record desktop sound by reading from
it, or even use it as an input device, for example during a call.

Sponsored by:   The FreeBSD Foundation
MFC after:      1 week
Reviewed by:    emaste
Pull-Request:   https://ron-dev.freebsd.org/FreeBSD/src/pulls/16

(cherry picked from commit 8532b4a436364d04d5c1feb7af5ecd4b5df71a9f)
DeltaFile
+1-0libexec/rc/rc.d/virtual_oss
+1-01 files