NAS-141404 / 26.0.0-RC.1 / Restart autostart containers and VMs after an encrypted pool is unlocked (#19272)
## Problem
An autostart container or VM on a passphrase-encrypted pool doesn't come
back after you unlock the pool. After a reboot, the pool is locked and
its workloads are stopped; unlocking should start them again, but they
stay `STOPPED` and you have to start each one by hand.
Unlocking a dataset asks each attachment delegate to start what's
attached to it. That works for shares (SMB, NFS, …), but for containers
and VMs, the delegate only ever reports instances that are *already
running* — so a workload that's stopped *because* its pool was locked
never gets picked up. VMs had a one-off hack to work around this;
containers had nothing.
## Changes
- Added a `start_on_unlock` hook to the attachment-delegate base class.
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Merge catalog update onto current config before persisting
## Problem
`catalog.update` wrote the raw partial request straight to the datastore and validated it directly. Because `CatalogUpdate` is a for-update model, a call that omits `preferred_trains` left the field as the `undefined` sentinel — so on ENTERPRISE systems `OFFICIAL_ENTERPRISE_TRAIN not in data.preferred_trains` raised a TypeError, and any partial write could drop the existing trains.
## Solution
Read the current config, merge the incoming update onto it, then validate and persist the merged result so partial updates keep untouched fields. Only `preferred_trains` is written back, since it's the sole stored column.
[AMDGPU][CodeGen] Fix `S_NOP` insertion during `S_SET_VGPR_MSB` placement (#209525)
The issue arises when co-issue optimizations move the initial insertion
position for `S_SET_VGPR_MSB` to an earlier spot, creating a mismatch
with the position used to determine whether a `S_NOP` is needed.
[lldb] Reject mixed typed DWARF binary operands (#201288)
## Summary
LLDB currently accepts and evaluates some ill-typed DWARF typed binary
operations whose two operands have different base types.
DWARF v5 typed-expression rules require arithmetic/logical and
relational binary operators to operate on operands of the same type,
either the same base type or the generic type. (see [DWARF v5
doc](https://dwarfstd.org/doc/DWARF5.pdf) Section 2.5.1.4)
This patch adds an explicit compatibility check before evaluating the
affected binary operators.
## Example
A DWARF expression illustrating the issue is:
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[CMake] Add -Wl,-z,pack-relative-relocs if supported (#208217)
We should aim to provide a good experience by default. Enable RELR for
PIC builds (which is on by default, even in non-dylib builds) if
supported by the linker (feature-tested) and the libc (currently
hardcoded as glibc 2.36+; musl has no easy way to determine support).
RELR substantially reduces the size of the dynamic relocations in PIE
executables and shared libraries and therefore also lowers max-rss and
startup time due to fewer page faults.
security/libfprint: Add Focaltech MOC PIDs 077A and 079A
This patch has been submitted upstream and should hopefully be available
in the next libfprint release.
PR: 296412
Approved by: maintainer timeout
Sponsored by: The FreeBSD Foundation
[ThinLTO] Fix thinlto-bad-summary-5.ll in read-only environments (#209513)
The test thinlto-bad-summary-5.ll was failing in read-only environments
(such as sandboxed test runners) because it attempted to write the
output bitcode file to the same directory as the input file, resulting
in a "Permission denied" error.
Fix this by redirecting the output to /dev/null using `-o /dev/null`.
We cannot use `-disable-output` here because the error we want to
test is triggered inside the BitcodeWriter, which is bypassed when
output is disabled.
assisted by gemini
[AMDGPU] Fix CFI emission when scratch instructions are used to spill
4b1cfc5d7c606e "[NFCI][AMDGPU] Final touch before moving to
`GET_SUBTARGETINFO_MACRO` (#177401)" (or more generally the move to
hasFlatScratchEnabled over just enableFlatScratch) was missed during the
CFI upstreaming for AMDGPU, and so we currently define the CFA
incorrectly for the architected flat scratch case.
This incorrect CFI is generated for e.g. gfx942. For such architecture,
the stack pointer (s32) holds a swizzled address (per-lane offset) but
the CFA needs to be an unswizzled address (per-wave).
In the incorrect program, we have a prologue looking like:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_mov_b32 s0, s33
s_mov_b32 s33, s32
[...]
s_add_i32 s32, s32, 16
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[AMDGPU] Add stackPtrOffsetReg to llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir (#209533)
Prepare for this being observable to the CFA generation code.
mlx5ib: use the eventfd_ctx API for DEVX event subscriptions
The DEVX_SUBSCRIBE_EVENT redirect path resolved the user's eventfd with
fdget(), which on FreeBSD only finds LinuxKPI files. rdma-core creates
the eventfd with the native FreeBSD eventfd(2), so the lookup failed and
subscription returned EBADF; the delivery side likewise assumed a
LinuxKPI-pollable file.
Use the LinuxKPI eventfd_ctx API instead: eventfd_ctx_fdget() resolves
the native eventfd, eventfd_signal() notifies it, and eventfd_ctx_put()
releases it. DEVX async events can then be delivered through a redirect
eventfd.
Reviewed by: kib
Sponsored by: Nvidia networking
MFC after: 1 month
Reland "[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base" (#209576)
Attempt 2 at #206299, fixing a linkage issue with gotsan on older
versions of glibc. Rather than forcing linkage of libdl (which may not
be safe with go), this just disables the dladdr usage under go builds.
This bug only affected MSAN and DFSAN anyway, and the code should be
unused by TSAN.
`ForEachMappedRegion` processes dynamic linker map entries to track
loaded segments. However, it assumes map->l_addr is the address of the
ELF header. For DSOs linked with a custom preferred image base offset
(e.g. -Wl,--image-base=0x4000000), `map->l_addr` contains the relocation
bias: `map->l_addr = actual_load_address - preferred_base`
In this case, map->l_addr points below the first loaded segment in
unmapped or PROT_NONE memory. Doing a read dereference at this address
triggers a SIGSEGV. Add a call to dladdr() on the dynamic section
pointer map->l_ld to obtain the true ELF header base address.
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NAS-141692 / 26.0.0-RC.1 / Fix UPS Input Load graph showing Watts on a percentage axis (by Qubad786) (#19312)
## Problem
The "UPS Input Load" report has `vertical_label = 'Percentage'` but
pointed `get_chart_name()` at Netdata's `upsd_<id>.load_usage` chart,
whose units are Watts (`ups.realpower`, or `ups.load/100 ×
ups.realpower.nominal`). So the graph rendered absolute power draw (e.g.
~117W for a ~30% load on a 390W UPS) under a "Percentage" axis. This
regressed in the python.d→go.d Netdata migration, which renamed the
chart from `nut_<id>.load` to `load_usage` without updating the label —
the migration picked the wrong sibling chart.
## Solution
Point the chart at `upsd_<id>.load_percentage` (units: percentage),
which maps to the raw NUT `ups.load` variable and matches both the
existing label and title. This chart is gated on the same `ups.load`
variable as `load_usage`, so it's available under identical conditions,
and it populates even on UPSes that don't report realpower — where
`load_usage` would be empty.
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Revert "[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features" (#209572)
Reverts llvm/llvm-project#208774
The failure that caused the revert last time should be fixed by
37b8e765ce4837a7577e6f762bcdffe4b232759c.
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (38)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (37)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (35)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (36)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (34)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (33)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
