[Offload] Update skip list for level_zero Offload API tests (#220937)
olDestroyQueueTest.SuccessDelayedResolution - passes
olLaunchKernelFooTest.SuccessThreaded - ran 1000 times, all passed
olMemFillTest.SuccessLargeByteAlignedEnqueue - passes after fixes from
@311Volt
olLaunchKernelLocalMemStaticTest - it's not using dynamic shared memory,
just a static array which is valid
[ConstraintElim] Rewrite usub.sat to sub when it cannot saturate. (#220865)
usub.sat(A, B) is max(A - B, 0), so it is exactly A - B when A >=u B.
Check if we can prove the precondition, and if so replace it with a
plain sub nuw. We can also add NSW if A is non-negative.
This helps to both remove unnecessary usub.sat, as well as enables a
number of additional folds (once the usub.sat has been replaced by sub
it can be decomposed when checking conditions involving it, as we do the
rewrite before simplifying any condition involving it):
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1181
Alive2 Proofs: https://alive2.llvm.org/ce/z/v6gZwL
PR: https://github.com/llvm/llvm-project/pull/220865
[MemCpyOpt] Avoid stack-move optzn for out-of-bounds copy reading at offset zero (#220931)
Following up on #217607, avoid performing stack-move optimization on
out-of-bounds memcpys in dead code, in this variant when the read starts
at offset zero.
Fixes: https://github.com/llvm/llvm-project/issues/220904.
[offload][nfc] Return an explicit error from createInterop (#220951)
The return type is Expected<omp_interop_val_t *> so a nullptr can be
incorrectly interpreted as a success and subsequently the nullptr could
get dereferenced. Make the error explicit.
[AMDGPU] Mark the async marker intrinsics nocallback (#219099)
llvm.amdgcn.asyncmark and llvm.amdgcn.wait.asyncmark only set and await
a marker in the stream of async requests. They cannot transfer control
out of the module, so they qualify for nocallback.
Without it, AAAMDGPUMinAGPRAlloc takes its conservative arm for calls
that are not nocallback and reaches a pessimistic fixpoint, so no
amdgpu-agpr-alloc attribute is manifested. getMaxNumVectorRegs then
falls back to reserving half of the vector register file for AGPRs,
which halves the arch VGPRs available to any kernel that uses async LDS
copies.
---------
Co-authored-by: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
[AMDGPU] Avoid slow 64-bit max/min/multiply instructions on GFX1250 (#207006)
On GFX1250 64-bit integer VALU max/min instructions are slower than
expanding to compare and select, and 64-bit integer VALU multiply is
slower than expanding to a sequence of 32-bit multiplies and adds. Avoid
them by pretending that these cases are not legal during instruction
selection.
Fixes: LCOMPILER-2207
[AArch64] Use multi-vector intrinsics for masked load/store users of predicate-as-counter
If the user of the original wide mask is a masked load or store
intrinsic (matching the element size of the predicate-as-counter),
rewrite it directly to a masked multi-vector load/store.
This avoids materializing the vector mask and is easier to handle here
than later (e.g. in SelectionDAG), since we do not need to match the
concatenation of all `pext` segments of the predicate-as-counter.
Assisted-by: Codex
[AArch64] Avoid materializing full masks for extractelement users of predicate-as-counter
If the user of the original wide mask is an `extractelement` and the
index is known to be within the first segment of the
predicate-as-counter, replace it with `extractelement(pext(counter, 0))`.
This avoids materializing the vector mask and produces a form that can
be folded into a conditional branch when the predicate-as-counter is
produced by a `whilelo`.
Assisted-by: Codex
[AArch64] Add predicate-as-counter loop rewrite pass
This patch adds an AArch64 IR loop pass that rewrites wide loop-carried
`llvm.get.active.lane.mask` phis to predicate-as-counter `whilelo` phis
(for SVE2.1 or streaming SME2 targets).
Users of the original mask are preserved by materializing vector
predicates with `aarch64.sve.pext`.
The element size and vector scale (VLx2 or VLx4) of the
predicate-as-counter is inferred from the mask load/store users within
the loop. These could be optimized to multi-vector loads/stores (though
that is not included in this patch).
For example, a loop like:
```
entry:
%step = vscale x 64
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[mlir][tosa] Add support for mxfp IDENTITY (#220624)
Tosa specification changes in
https://github.com/arm/tosa-specification/pull/61
Change-Id: Ib938e4915c14e14aeb465944875b2fed7e5e3698
Signed-off-by: Yuvaraj Venkatesh <yuvaraj.venkatesh at arm.com>
[Clang] Always apply `-frtlib-add-rpath` if requested (#220697)
Summary:
This path used to try to infer if it was needed by using the language
options. The result was that if you tried to use this on a `.o` link job
you would not get the rpath behavior you would expect.
The reason it was this way stems from the fact that this used to be
implicit behavior, so it was being conservative. At some point one of
the maintainers dictated that we cannot add rpath by default, so we
ended up with this, but still being conservative.
If the user passes `-frtlib-add-rpath`, just add the rpath. Flang does
this already.
biology/py-macs2: Remove
MACS2 is dead upstream, with no plans to make it compatible with
cython 3.x or other newer dependencies. Though the port was
set to expire in another month, I'm removing it now to stop wasting
package building resources. It has not been buildable for some time.
(cherry picked from commit 08256be5a8582d2a23383495dc6a1ab477da3f97)
iflib: update rs_pending based on descriptors consumed by isc_txd_encap
The new watchdog code triggers spurious watchdog resets on
NICs doing KTLS offload. Fix this by using the actual segments
consumed by the NIC driver's isc_txd_encap.
The issue is that rs_pending is updated using an estimate of
the descriptors that will be used for the current packet,
based on what bus_dma produced. However, NICs which support
ktls offload may do extra DMAs (and consume extra
descriptors) to derive crypto state when re-transmitting
TLS segments. This is the reason for allowing drivers to control
ift_pad. When this happens, the estimated rs_pending may undercount.
This may also happen if NIC drivers consume extra descriptors for
other reasons. (eg, hw errata handling on e1000)
Reviewed by: kbowling
Differential Revision: https://reviews.freebsd.org/D59321
Sponsored-by: Netflix
[clang][bytecode] Remove Record::VirtualBaseMap (#220907)
Virtual bases are so rarely used that I don't think having a dedicated
map for them in every record is worth it.
riscv: Fix bus_space_{alloc,free,mmap} macros
The macros bus_space_alloc, bus_space_free, and bus_space_mmap were
incorrectly passing the bus space cookie as their first parameter.
This patch updates these macros to pass the entire bus space tag pointer
instead as per other macros.
[SPIRV] Converge different `resolveDebugParentScope` versions into a single one (#219925)
These 4 functions do more or less the same thing: they map the parent
scope of a debug entity to its associated register.
* resolveDebugFunctionParent
* resolveTypeScopeParent
* resolveLexicalBlockParent
* resolveGlobalVariableParent
This patch merges these 4 functions into a single one.
This patch also pipes the parent scope resolution for typedefs through
the new `resolveScope` function.
Closes #210331
[CIR] Enable callconv lowering in the x86_64 C++ argument test
Two cases here hit the coercion NYI this branch removes. The pass now
runs on the file.
The `LLVM` lines for those two stopped at the open paren and passed whatever
the pass did with the argument. Both prefixes now pin the coerced parameter
and the byte-8 access.
Assisted-by: Cursor / claude-opus-5
risc-v: fix assemble opcode helper macros
- remove *_SUBI variants as these instructions don't exist and the
assembler doesn't help. *_ADDI should be used.
- use 'iw' instead of 'wi' to match real instructions.
