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Created using spr 1.3.7

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Created using spr 1.3.7

[X86] Pin debug variable locations mode in pr228950.ll (#231278)

The CHECK lines in pr228950.ll assume instruction-referencing variable
locations, which is the x86_64 default. Under VarLoc-based
LiveDebugValues, llc emits a #DEBUG_VALUE comment between ldtilecfg and
tilezero, and the CHECK-NEXT fails.

Pass -experimental-debug-variable-locations=true so the test does not
depend on the default. This does not change upstream output.

rdar://189810853

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[NFC] Fix wrong comment in insertFastDivAndRem (#230879)

The branch checks that the divisor IS a constant, not the opposite.

   Split the rge(4) microcode into sys/dev/microcode/rge

   Suggested by deraadt@

[RISCV][GlobalISel] Promote f16 to f32 for G_FCMP without Zfh (#231097)

Without Zfh, G_FCMP with f16 operands had no matching legalization rule,
so GlobalISel failed to legalize it.
This commit widen the operands to f32 instead, matching SelectionDAG,
which promotes f16 SETCC when Zfh is not available.

Godbolt link: https://godbolt.org/z/Y9P7Yqa8d

[RISCV][GlobalISel] Use Zfhmin for G_FCONSTANT s16 (#230723)

`fmv.h.x` is available with Zfhmin, and the selector already
materializes f16 constants through a GPR and `fmv.h.x`. SelectionDAG
handles f16 constants with Zfhmin, but GlobalISel would abort because
G_FCONSTANT s16 was only legal with Zfh.

SelectionDAG: https://godbolt.org/z/coMc7j3x9
GlobalISel: https://godbolt.org/z/MqzdG1r4v

[RISCV][GlobalISel] Use Zfhmin for G_FPEXT from f16 to f64 (#230721)

From SPEC: If the D extension is present, the fcvt.d.h and fcvt.h.d
instructions are also included.

Link:
https://github.com/riscv/riscv-isa-manual/blob/1b9ca13819259df4b3bc87a7d7dcda06dd2fb6a9/src/unpriv/zfhmin.adoc?plain=1#L14-L17

Follow up of https://github.com/llvm/llvm-project/pull/227225

security/vuxml: Document DSA sig vuln in pycryptodome(x) < 3.24.1

Sponsored by: Saltant Solutions LLC

   update to scummvm 2026.4.0

net/freerdp3: Update 3.32.1 => 3.32.2

Changelog:
https://github.com/FreeRDP/FreeRDP/releases/tag/3.32.2
https://github.com/FreeRDP/FreeRDP/blob/3.32.2/ChangeLog

Security:       GHSA-4g67-jhpc-q5xp
Security:       GHSA-799q-hjgw-g55g
Security:       GHSA-cg4f-57hc-v7w7
Security:       GHSA-rrp5-666j-g6gp
Security:       GHSA-wg7g-gx9g-r96c
Security:       GHSA-f53w-3364-jr35
Security:       GHSA-66mr-7wc7-23vc
Security:       GHSA-hqf8-95c7-6r92
Security:       GHSA-8g9g-hqqp-fw69
Security:       GHSA-jq25-3374-4262
Security:       GHSA-7qw2-8h66-pvpw
Security:       GHSA-5j39-x36c-x9pm
Security:       GHSA-6p3w-fv52-cf24

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[InstCombine] Fix profiles in FoldSelectWithAndOrCond (#231327)

3b38314a2b69847305b692677dbe64f1eb43235a also incorrectly applied branch
weights. The fact that the true and false arms have the same value says
little about the value distribution of the condition. For example, if we
take the following case:

```llvm
%A = icmp ne i32 %x, %z
%B = icmp eq i32 %y, %z
%C = and i1 %A, %B
%D = select i1 %C, i32 %z, i32 %x, !prof !1
ret i32 %D
```

which LLVM folds to

```llvm
%B = icmp eq i32 %y, %z

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net/freerdp3: Update 3.32.1 => 3.32.2

Changelog:
https://github.com/FreeRDP/FreeRDP/releases/tag/3.32.2
https://github.com/FreeRDP/FreeRDP/blob/3.32.2/ChangeLog

Security:       GHSA-4g67-jhpc-q5xp
Security:       GHSA-799q-hjgw-g55g
Security:       GHSA-cg4f-57hc-v7w7
Security:       GHSA-rrp5-666j-g6gp
Security:       GHSA-wg7g-gx9g-r96c
Security:       GHSA-f53w-3364-jr35
Security:       GHSA-66mr-7wc7-23vc
Security:       GHSA-hqf8-95c7-6r92
Security:       GHSA-8g9g-hqqp-fw69
Security:       GHSA-jq25-3374-4262
Security:       GHSA-7qw2-8h66-pvpw
Security:       GHSA-5j39-x36c-x9pm
Security:       GHSA-6p3w-fv52-cf24

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[JITLink][AArch64] Preserve destination addends on external branches (#231231)

Currently, an external branch such as `b target + addend` is incorrectly
redirected to `stub + addend` instead of `target + addend`. With an
addend of 4, for example, this skips the `adrp` in the stub's `adrp +
ldr + br` sequence, leaving `x16` without the expected page address,
which may cause a segmentation fault.

Reproducer on AArch64:
```asm
// caller.s
.text
.p2align 2
.globl main
main:
    mov x16, #0     // Make the skipped adrp expose the bug.
    b target + 4
```
```asm

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ncal(1): handle Sweden's transitional calendar (1700-1712)

Sweden used a unique intermediate calendar during 1700-1712.  In 1700,
Sweden omitted the Julian leap day (Feb 29, 1700) to begin a gradual
transition to the Gregorian calendar.  The transition was abandoned
mid-way due to the Great Northern War; to revert to the Julian calendar,
an extra day "Feb 30, 1712" was added.  Sweden finally adopted the
Gregorian calendar in 1753 (already handled correctly by ncal).

ncal previously displayed Feb 1700 as a 29-day month and Feb 1712 as a
29-day month, both incorrect for the Swedish (-s SE) calendar mode.

Add flag_sweden, which is set when the SE country code is selected (via
-s SE or the locale) and cleared by -J, since -J selects the plain
Julian calendar.  When active, sndaysr() and sdater() apply the one-day
offset that characterised the Swedish transitional calendar:

  - Feb 1700: displayed with 28 days (no leap day)
  - 1700-03-01 to 1712-02-30: dates run one day ahead of Julian, so

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Reland "[compiler-rt][asan] Add asan checks for __builtin_assume_dereferencable" (#224163)

This relands commit bf8cf4b7b31b956ea4dfec93b0b4d77b359b188b (#190871),
which was reverted in commit e3b3706ceeea94ade3557275628a0e589e10ba24
(#193655).

This checks that the range covered by this intrinsic is dereferenceable.
Specifically it checks for `llvm.assume` intrinsics using the
`dereferenceable` operator bundle and asserts that the shadow for this
range is zero.

Fixes included in this reland:
1. Darwin Stable ABI: Added `__asan_report_assume_dereferenceable` and
`__asan_report_assume_dereferenceable_noabort` to `asan_abi_tbd.txt` to
resolve the interface symbols diff failure in
llvm_interface_symbols.cpp.
2. MSVC Support: Added `UNSUPPORTED: msvc` to the new
`assume_dereferenceable*.cpp` tests, as
`__builtin_assume_dereferenceable` is a Clang builtin not supported by

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   Add RX queues/RSS/TSO support and update microcode for RTL8127.

   On the RTL8127, the RX and TX descriptors use the 16-byte format
   instead of the 32-byte one.

[ProfCheck] Update XFAIL list (#231328)

This test was apparently fixed by other patches.

zio: drop a queued scan read only when its block is freed

zio_free_sync() tells the scan that a block is freed before it knows
whether the space will be released. A dedup or cloned block with other
references is only dereferenced, but the scan still removes its queued
read. The sorted scan queue holds one read per location, so the block's
remaining references are never verified or repaired: a scrub reports
nothing and a resilver can leave the block missing on the new device.

Notify the scan where the space is actually released: in zio_free_sync()
just before an immediate free, which also receives a dedup block's last
free from ddt_phys_free(), and in zio_dva_free(), which cloned and gang
blocks reach once they are no longer referenced.

The regression verifies physical sharing, forces sorted scanning, and
bounds in-flight I/O so the shared block remains queued behind a larger
file after traversal. Removing one reference must leave the other file
readable from the replacement alone.


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Merge remote-tracking branch 'rad/hardened/current/master' into hardened/current/pledge

Merge remote-tracking branch 'rad/hardened/15-stable/main' into hardened/15-stable/pledge

Merge branch 'freebsd/current/main' into hardened/current/master

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main

Add vector test

Merge branch 'freebsd/main' into hardenedbsd/main

Update editors/fresh to v.0.5.3

   Fix TLV handling which lacks the check length checks for padding.
   This could out-of-bounds memory write, stack disclosure, and SIGSEGV.

   Reported and fix provided by Franz Bettag

[InstCombine] Fold trunc(ctpop(A)) + trunc(ctpop(B)) -> trunc(ctpop(A) + ctpop(B))

This allows the combine added in #231321 to kick in and fold the motivating ctpop case in automotive-bitcount:

```c
static char bits[256] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8};

int CDECL ntbl_bitcount(long int x)
{
      return
            bits[ (int) (x & 0x0000000FUL)       ] +
            bits[ (int)((x & 0x000000F0UL) >> 4) ] +
            bits[ (int)((x & 0x00000F00UL) >> 8) ] +
            bits[ (int)((x & 0x0000F000UL) >> 12)] +
            bits[ (int)((x & 0x000F0000UL) >> 16)] +
            bits[ (int)((x & 0x00F00000UL) >> 20)] +
            bits[ (int)((x & 0x0F000000UL) >> 24)] +
            bits[ (int)((x & 0xF0000000UL) >> 28)];
}
```

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