LLVM/project 0f74f10mlir/include/mlir/Bindings/Python Globals.h, mlir/lib/Bindings/Python Globals.cpp IRCore.cpp

[mlir-python] Fix duplicate EnumAttr builder registration across dialects.

When multiple dialects share .td includes (e.g. affine includes arith),
each dialect's _*_enum_gen.py file registered attribute builders under
the same keys, causing "already registered" errors on the second import.

Two-pronged fix:

1. Add `allow_existing=True` to `register_attribute_builder` (and the
   underlying C++ `registerAttributeBuilder`). When set, silently skips
   registration if the key already exists (first-wins semantics). This
   handles EnumInfo-based builders (e.g. `AtomicRMWKindAttr`,
   `Arith_CmpFPredicateAttr`) that are emitted by every dialect whose
   .td file includes the defining file.

2. Filter EnumAttr-loop builders by `-bind-dialect` in
   `EnumPythonBindingGen.cpp` and register them under dialect-qualified
   keys (`"dialect.AttrName"`). Update `OpPythonBindingGen.cpp` to look
   up the same qualified keys for EnumAttr-typed op attributes (detected

    [5 lines not shown]
DeltaFile
+23-6mlir/tools/mlir-tblgen/EnumPythonBindingGen.cpp
+18-2mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
+10-6mlir/lib/Bindings/Python/Globals.cpp
+5-5mlir/test/mlir-tblgen/enums-python-bindings.td
+6-2mlir/include/mlir/Bindings/Python/Globals.h
+4-2mlir/lib/Bindings/Python/IRCore.cpp
+66-234 files not shown
+74-2910 files

LLVM/project 70665c6clang/test/CXX/drs cwg2947.cpp, clang/www cxx_dr_status.html

[clang] Update C++ DR status page
DeltaFile
+74-18clang/www/cxx_dr_status.html
+1-1clang/test/CXX/drs/cwg2947.cpp
+75-192 files

LLVM/project 8187875clang/lib/Driver/ToolChains Darwin.cpp, clang/test/Driver xcselect.c darwin-ld-platform-version-macos-nosdk.c

[clang][Driver][Darwin] Use `xcselect` for `*-apple-darwin*` targets too (#186683)

This is a follow-up to #119670. There, we introduced a CMake option
`CLANG_USE_XCSELECT`, which, when enabled, uses `libxcselect` to find
the right SDK to inject as an `-isysroot` flag when targeting
`*-apple-macos*`.

We intentionally left out `*-apple-darwin*` targets because it broke
many tests. This is unfortunate because `*-apple-darwin*` is the default
triple when building LLVM on macOS, so one isn't able to take advantage
of `xcselect` without an explicit `-target` flag or a change to the
toolchain's default target.

We fix this in two ways.

First, we move the injection of the `-isysroot` flag using `xcselect`
later, until after we are sure that we are targeting macOS. This avoids
confusing the earlier deployment target detection code when we inject
the macOS SDK but actually intended to target non-macOS.

    [3 lines not shown]
DeltaFile
+21-12clang/lib/Driver/ToolChains/Darwin.cpp
+30-3clang/test/Driver/xcselect.c
+0-17clang/test/Driver/darwin-ld-platform-version-macos-nosdk.c
+13-0clang/test/Driver/darwin-ld-platform-version-macos.c
+2-1clang/test/Driver/fsanitize-ignorelist.c
+2-1clang/test/Driver/darwin-builtin-modules.c
+68-341 files not shown
+70-347 files

LLVM/project a21c414clang/test/OpenMP target_teams_distribute_parallel_for_simd_schedule_codegen.cpp teams_distribute_parallel_for_simd_schedule_codegen.cpp, libc/AOR_v20.02/math/test/traces sincosf.txt exp.txt

Merge branch 'main' into users/kasuga-fj/da-rewrite-weak-zero-siv-formula
DeltaFile
+0-31,999libc/AOR_v20.02/math/test/traces/sincosf.txt
+0-16,000libc/AOR_v20.02/math/test/traces/exp.txt
+5,294-4,814clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+5,238-4,758clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+4,350-4,098clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
+4,004-3,524clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
+18,886-65,1934,105 files not shown
+247,605-244,4514,111 files

FreeBSD/ports 55f2678multimedia/pipewire pkg-plist, multimedia/pipewire/files patch-spa_include_spa_param_audio_raw-json.h patch-src_pipewire_context.c

multimedia/pipewire: update to 1.6.2

Reviewed by:    arrowd
Approved by:    lwhsu (mentor, implicitly)
Differential Revision:  https://reviews.freebsd.org/D55821
DeltaFile
+37-4multimedia/pipewire/pkg-plist
+28-0multimedia/pipewire/files/patch-spa_include_spa_param_audio_raw-json.h
+26-0multimedia/pipewire/files/patch-src_pipewire_context.c
+20-0multimedia/pipewire/files/patch-spa_include_spa_param_audio_layout-types.h
+0-19multimedia/pipewire/files/patch-spa_plugins_filter-graph_filter-graph.c
+14-0multimedia/pipewire/files/patch-spa_plugins_vulkan_vulkan-compute-utils.c
+125-2315 files not shown
+259-4021 files

FreeBSD/ports 5f92ed2multimedia/wireplumber pkg-plist Makefile, multimedia/wireplumber/files patch-lib_wp_log.c

multimedia/wireplumber: update to 0.5.13

Upstreamed patch: https://gitlab.freedesktop.org/pipewire/wireplumber/-/merge_requests/806

Reviewed by:    arrowd
Approved by:    lwhsu (mentor, implicitly)
Differential Revision:  https://reviews.freebsd.org/D55896
DeltaFile
+16-1multimedia/wireplumber/pkg-plist
+16-0multimedia/wireplumber/files/patch-lib_wp_log.c
+2-5multimedia/wireplumber/Makefile
+3-3multimedia/wireplumber/distinfo
+37-94 files

LLVM/project ffcb574orc-rt/include/orc-rt BootstrapInfo.h Session.h, orc-rt/lib/executor BootstrapInfo.cpp Session.cpp

[orc-rt] Add BootstrapInfo: info for controller session bootstrap. (#187184)

BootstrapInfo holds information needed to bootstrap the ExecutionSession
in the controller. Future patches will update ControllerAccess to send
the bootstrap information at controller-connection time.

BootstrapInfo includes information about the executor process (via
Session::processInfo), an initial set of symbols (replacing
Session::controllerInterface()), and a simple key/value store.
DeltaFile
+152-0orc-rt/unittests/BootstrapInfoTest.cpp
+67-0orc-rt/include/orc-rt/BootstrapInfo.h
+52-0orc-rt/lib/executor/BootstrapInfo.cpp
+0-35orc-rt/unittests/SessionTest.cpp
+1-6orc-rt/lib/executor/Session.cpp
+0-5orc-rt/include/orc-rt/Session.h
+272-463 files not shown
+275-469 files

LLVM/project c61d11dclang/include/clang/Basic riscv_vector.td, clang/lib/Sema SemaRISCV.cpp

[clang][RISCV] Add RequiredFeatures for zvknha and zvknhb (#186993)

zvknhb now implies zvknha so we dont need to check extensions manually
in SemaRISCV, we can just use RequiredFeatures instead.
DeltaFile
+13-5clang/include/clang/Basic/riscv_vector.td
+10-5clang/test/Sema/zvk-invalid-features.c
+0-12clang/lib/Sema/SemaRISCV.cpp
+23-223 files

LLVM/project 3a1d5b5clang/lib/Basic/Targets X86.h, clang/test/Sema x86-fixed-global-register.c

[X86] Support reserving EDI on x86-32 (#186123)

Which is under discussion in
https://github.com/llvm/llvm-project/issues/179036.
x86-64 support is added in
https://github.com/llvm/llvm-project/pull/180242.
Now add x86-32 support for reserving EDI via `-ffixed-edi` Update the
X86 backend to respect those reservations in register handling,
callee-save logic, and memcpy/memset lowering, and add driver/codegen
tests.

Add clang driver support for -ffixed-edi and map it to the reserve-edi
target feature on i386.

Teach the X86 backend to treat EDI as a user-reserved register in
register lookup, reserved-register tracking, and callee-save handling,
and avoid selecting REP MOVS/REP STOS when EDI is reserved.

Add driver, Sema, and codegen tests covering option handling, named

    [2 lines not shown]
DeltaFile
+63-0llvm/test/CodeGen/X86/reserveDIreg.ll
+36-0clang/test/Sema/x86-fixed-global-register.c
+25-1clang/lib/Basic/Targets/X86.h
+14-8llvm/lib/Target/X86/X86RegisterInfo.cpp
+16-5llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+3-5llvm/lib/Target/X86/X86ISelLowering.cpp
+157-197 files not shown
+180-2113 files

LLVM/project 21ac860mlir/test/python/dialects affine.py

[mlir-python] Emit only dialect EnumAttr registrations.
DeltaFile
+5-0mlir/test/python/dialects/affine.py
+5-01 files

LLVM/project 6a84823mlir/python/mlir ir.py, mlir/python/mlir/dialects llvm.py nvvm.py

[mlir-python] Emit only dialect EnumAttr registrations.
DeltaFile
+54-54mlir/python/mlir/ir.py
+106-1mlir/python/mlir/dialects/llvm.py
+76-0mlir/python/mlir/dialects/nvvm.py
+56-0mlir/python/mlir/dialects/gpu/__init__.py
+35-0mlir/python/mlir/dialects/arith.py
+26-0mlir/python/mlir/dialects/nvgpu.py
+353-5519 files not shown
+512-8325 files

LLVM/project 495c518clang/lib/Basic/Targets PPC.cpp, clang/lib/CodeGen CodeGenFunction.cpp

[FMV][AIX] Implement target_clones (cpu-only) (#177428)

This PR implements Function Multi-versioning on AIX using `__attribute__
((target_clones(<feature-list>)))`.
Initially, we will only support specifying a cpu in the version list. 
Feature strings (such as "altivec" or "isel") on target_clones will be
implemented in a future PR.

Accepted syntax:
```
__attribute__((target_clones(<OPTIONS>)))
```
where `<OPTIONS>` is a comma separated list of strings, each string is
either:
1) the default string `"default"`
2) a cpu string `"cpu=<CPU>"`, where `<CPU>`is a value accepted by the
`-mcpu` flag.
For example, specifying the following on a function
```

    [10 lines not shown]
DeltaFile
+142-0clang/test/CodeGen/PowerPC/attr-target-clones.c
+132-0clang/test/Sema/PowerPC/attr-target-clones.c
+62-53clang/lib/CodeGen/TargetBuiltins/PPC.cpp
+77-2clang/lib/CodeGen/CodeGenFunction.cpp
+69-0clang/lib/Sema/SemaPPC.cpp
+51-0clang/lib/Basic/Targets/PPC.cpp
+533-5510 files not shown
+633-7416 files

FreeBSD/ports e49599fsysutils/lsblk Makefile distinfo

sysutils/lsblk: update to 4.1

Changelog between 4.0 and 4.1 is as follows:

- Fix column align for 1000-1023k size.
- Fix single disk argument.
- Properly calculate provider size.
- Add lsblk(8) man page.
- Fix disks listing.
- Extend column size for better formatting.
- Add -V to sort(1) for proper order of devices.
- Ignore card readers that have '0B' size.
- Fix listing devices with 0B size.
- Fix SUMMARY printing.
- Other minor fixes.

PR: 293887
DeltaFile
+3-3sysutils/lsblk/Makefile
+3-3sysutils/lsblk/distinfo
+6-62 files

FreeBSD/ports e623816math Makefile, math/py-torchsde Makefile pkg-descr

math/py-torchsde: New port: SDE solvers and stochastic adjoint sensitivity analysis in PyTorch
DeltaFile
+26-0math/py-torchsde/Makefile
+9-0math/py-torchsde/pkg-descr
+3-0math/py-torchsde/distinfo
+1-0math/Makefile
+39-04 files

FreeBSD/ports 42181e5graphics Makefile, graphics/py-kornia Makefile pkg-descr

graphics/py-kornia: New port: Differentiable computer vision library for PyTorch
DeltaFile
+26-0graphics/py-kornia/Makefile
+9-0graphics/py-kornia/pkg-descr
+3-0graphics/py-kornia/distinfo
+1-0graphics/Makefile
+39-04 files

FreeBSD/ports d9c895fdevel Makefile, devel/py-trampoline Makefile pkg-descr

devel/py-trampoline: New port: Simple and tiny yield-based trampoline implementation
DeltaFile
+22-0devel/py-trampoline/Makefile
+5-0devel/py-trampoline/pkg-descr
+3-0devel/py-trampoline/distinfo
+1-0devel/Makefile
+31-04 files

FreeBSD/ports 1371441graphics Makefile, graphics/py-kornia-rs distinfo Makefile

graphics/py-kornia-rs: New port: Differentiable computer vision library for PyTorch
DeltaFile
+2,505-0graphics/py-kornia-rs/distinfo
+2,207-0graphics/py-kornia-rs/files/Cargo.lock
+1,288-0graphics/py-kornia-rs/Makefile
+14-0graphics/py-kornia-rs/files/patch-Cargo.toml
+10-0graphics/py-kornia-rs/pkg-descr
+1-0graphics/Makefile
+6,025-06 files

FreeBSD/ports a16fdc4misc Makefile, misc/py-spandrel Makefile pkg-descr

misc/py-spandrel: New port: Library for loading and running pre-trained PyTorch models
DeltaFile
+27-0misc/py-spandrel/Makefile
+6-0misc/py-spandrel/pkg-descr
+3-0misc/py-spandrel/distinfo
+1-0misc/Makefile
+37-04 files

LLVM/project 3661bf7clang/test/Modules pr179178.cpp

[Clang][Modules] Add regression test for #179178 (#187173)

This patch adds a regression test for a clang header modules failure we
saw after #179178 landed.

I'm too familiar with the norms for clang modules tests, so feel free to
nit-pick.

I've verified that this test passes at HEAD and fails with #179168
applied (i.e., the revert reverted).
DeltaFile
+120-0clang/test/Modules/pr179178.cpp
+120-01 files

LLVM/project aa2defcllvm/lib/Target/X86 X86InstrArithmetic.td X86InstrUtils.td, llvm/test/CodeGen/X86/apx sbb.ll adc.ll

[X86][APX] Remove patterns for ArithBinOp (#187018)

We should never select to these _EVEX variants. A follow up of #186049.
DeltaFile
+16-20llvm/test/CodeGen/X86/apx/sbb.ll
+12-12llvm/lib/Target/X86/X86InstrArithmetic.td
+8-10llvm/test/CodeGen/X86/apx/adc.ll
+2-2llvm/lib/Target/X86/X86InstrUtils.td
+38-444 files

LLVM/project c4137a6orc-rt/include/orc-rt SimpleSymbolTable.h

[orc-rt] Relax addUnique assertion to match error condition.

Duplicates are now permitted as long as they're identical (dbdf1accf55).
DeltaFile
+3-2orc-rt/include/orc-rt/SimpleSymbolTable.h
+3-21 files

LLVM/project 350385elibclc/clc/lib/generic/conversion clc_convert_int2float.cl, libclc/clc/lib/generic/math clc_lgamma_r.cl clc_atan2pi.cl

[libclc][NFC] Change include style from <...> to "..." (#186537)

project-specific headers should use "". Keep #include <amdhsa_abi.h>

llvm-diff shows no change to libclc.bc for spir--, spir64--, nvptx64--,
nvptx64--nvidiacl, nvptx64-nvidia-cuda and amdgcn-amd-amdhsa-llvm when
LIBCLC_TARGETS_TO_BUILD is "all".
Verified that reversing spir64--/libclc.spv and spir--/libclc.spv to
LLVM bitcode shows no diff.

Also fix `__CLC_INTEGER_CLC_BITFIELD_EXTRACT_SIGNED_H__` guard per
copilot review.

---------

Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot at users.noreply.github.com>
DeltaFile
+26-26libclc/clc/lib/generic/conversion/clc_convert_int2float.cl
+17-17libclc/clc/lib/generic/math/clc_lgamma_r.cl
+17-17libclc/clc/lib/generic/math/clc_atan2pi.cl
+17-17libclc/clc/lib/generic/math/clc_atan2.cl
+16-16libclc/clc/lib/generic/math/clc_frexp.cl
+16-16libclc/clc/lib/generic/math/clc_remainder.cl
+109-109688 files not shown
+2,349-2,349694 files

FreeNAS/freenas 31d0cb1src/middlewared/middlewared/plugins/vm __init__.py vms.py

Move VM namespace to be typesafe
DeltaFile
+519-0src/middlewared/middlewared/plugins/vm/__init__.py
+0-463src/middlewared/middlewared/plugins/vm/vms.py
+0-426src/middlewared/middlewared/plugins/vm/vm_devices.py
+320-0src/middlewared/middlewared/plugins/vm/crud.py
+148-153src/middlewared/middlewared/plugins/vm/clone.py
+246-0src/middlewared/middlewared/plugins/vm/vm_device_convert.py
+1,233-1,04248 files not shown
+2,746-2,39654 files

LLVM/project ae9b5a4clang/docs InternalsManual.rst, clang/include/clang/Frontend VerifyDiagnosticConsumer.h

[clang] Add `-verify-directives` cc1 flag (#179835)

Matheus once told me that the various rules I enforce in C++ DR tests
should be checked automatically. This is the patch to check some of
them.

`-verify-directives` is a cc1 flag that checks how `expected` directives
themselves are written. It enforces the following rules on top of
`-verify` mode:
1. Directives have to fully match diagnostic text (but regular
expressions are still allowed).
2. Lexical order of directives must match the order in which diagnostics
are emitted.
3. Each directive must match exactly one diagnostic.
4. Directives has to specify exact source location of the diagnostic,
i.e. wildcards (`*`) are not allowed.

The second rule (about order) is the most significant: it doesn't allow
to e.g. have `expected-note {{declared here}}` somewhere far away from

    [20 lines not shown]
DeltaFile
+276-16clang/docs/InternalsManual.rst
+269-22clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
+45-0clang/test/Frontend/verify-directives-one-diag.cpp
+19-4clang/include/clang/Frontend/VerifyDiagnosticConsumer.h
+14-0clang/test/Frontend/verify-directives-order.cpp
+14-0clang/test/Frontend/verify-directives-wildcard.cpp
+637-426 files not shown
+673-4312 files

LLVM/project dbdf1acorc-rt/include/orc-rt SimpleSymbolTable.h, orc-rt/lib/executor SimpleSymbolTable.cpp Session.cpp

[orc-rt] Rename SimpleSymbolTable::addSymbolsUnique, relax error cond… (#187171)

…ition.

Renames the SimpleSymbolTable addSymbolsUnique method to addUnique. The
new class name (from c727cd9a4b2) already implies that we're adding
symbols.

This commit also relaxes the error condition for addUnique: Rather than
rejecting any duplicate symbols, it only rejects symbols that were
previously added with a different address. This makes it safe to add the
same symbol(s) multiple time, as long as all definitions point to the
same address. The intent of this is to allow ORC runtime components to
unconditionally add their interfaces to symbols, even if that interface
might have been added previously.
DeltaFile
+22-12orc-rt/unittests/SimpleSymbolTableTest.cpp
+15-9orc-rt/include/orc-rt/SimpleSymbolTable.h
+8-7orc-rt/lib/executor/SimpleSymbolTable.cpp
+2-2orc-rt/unittests/SessionTest.cpp
+1-1orc-rt/lib/executor/sps-ci/SimpleNativeMemoryMapSPSCI.cpp
+1-1orc-rt/lib/executor/Session.cpp
+49-326 files

LLVM/project 1fee51cllvm/lib/Target/WebAssembly WebAssemblyFastISel.cpp, llvm/test/CodeGen/WebAssembly load-ext.ll offset-fastisel.ll

[WebAssembly] Fold sign-extending shifts into signed loads in FastISel (#185906)

WebAssembly FastISel currently fails to fold sign-extension patterns
composed of zero-extending loads followed by shift operations. This
results in redundant shift and constant instructions in the output.

Before:
  i32.load8_u $push3=, 0($0)
  i32.const $push0=, 24
  i32.shl $push1=, $pop3, $pop0
  i32.const $push4=, 24
  i32.shr_s $push2=, $pop1, $pop4

The matched shift instruction sequence is removed and safely folded into
a single sign-extending load, erasing the dead code via the
MachineBasicBlock iterator.

After:
  i32.load8_s $push0=, 0($0)

Fixed: #184302
DeltaFile
+68-132llvm/test/CodeGen/WebAssembly/load-ext.ll
+65-3llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+7-18llvm/test/CodeGen/WebAssembly/offset-fastisel.ll
+140-1533 files

LLVM/project 8b265cfllvm/lib/IR AutoUpgrade.cpp, llvm/test/Assembler auto_upgrade_nvvm_intrinsics.ll

[NVPTX][AutoUpgrade] atom.load intrinsics should be autoupgraded to monotonic atomicrmw for NVPTX (#187140)

Prior to https://github.com/llvm/llvm-project/pull/179553, the seq_cst
qualifier was being ignored. The expected codegen for these intrinsics
is `atom.relaxed`- which corresponds to `Monotonic`. The fix does to
AutoUpgrade what https://github.com/llvm/llvm-project/pull/185822 does
to clang.
DeltaFile
+4-4llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
+2-2llvm/lib/IR/AutoUpgrade.cpp
+0-3llvm/test/CodeGen/NVPTX/atomics.ll
+6-93 files

LLVM/project 3eb8b78llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll low-trip-count.ll

Revert "[LV] Replace remaining LogicalAnd to vp.merge in EVL optimization." (#187170)

Reverts llvm/llvm-project#184068

This hit the cost model assertion in rva23 stage2 build bot.
https://lab.llvm.org/buildbot/#/builders/213/builds/2497
DeltaFile
+0-16llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+6-2llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+3-1llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
+9-193 files

LLVM/project c727cd9orc-rt/include/orc-rt ControllerInterface.h SimpleSymbolTable.h, orc-rt/lib/executor ControllerInterface.cpp SimpleSymbolTable.cpp

[orc-rt] Rename ControllerInterface to SimpleSymbolTable. NFCI. (#187164)

This type will be used more contexts than just the controller interface.
DeltaFile
+146-0orc-rt/unittests/SimpleSymbolTableTest.cpp
+0-146orc-rt/unittests/ControllerInterfaceTest.cpp
+0-81orc-rt/include/orc-rt/ControllerInterface.h
+80-0orc-rt/include/orc-rt/SimpleSymbolTable.h
+0-34orc-rt/lib/executor/ControllerInterface.cpp
+34-0orc-rt/lib/executor/SimpleSymbolTable.cpp
+260-26110 files not shown
+276-27716 files

LLVM/project 52089f8llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll low-trip-count.ll

[LV] Replace remaining LogicalAnd to vp.merge in EVL optimization. (#184068)

This patch replace the remaining LogicalAnd to vp.merge in the second
pass to not break the `m_RemoveMask` pattern in the optimizeMaskToEVL.

This can help to remove header mask for FindLast reduction (CSA) loops.

PR: https://github.com/llvm/llvm-project/pull/184068
DeltaFile
+16-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-6llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+1-3llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
+19-93 files