[bazel][lldb] Add lldb-test binary to prepare for shell tests (#236762)
lldb-test is the test driver many lldb Shell tests run (for example
`lldb-test object-file` and `lldb-test symbols`). CMake builds it with
every plugin linked in.
https://github.com/llvm/llvm-project/blob/2f7a16ae3f634b1e889d13b01e6a65914a4d13c1/lldb/tools/lldb-test/CMakeLists.txt#L1-L23
The bazel overlay had no target for it, and the Shell tests need it
before they can be modeled.
Add it, getting the plugins through //lldb:API like liblldb does.
I can't run bazel locally. Through Meta's bazel->BUCK translation, the
target builds, and `lldb-test object-file` / `lldb-test symbols` work on
a test binary.
assisted with: claude
[bazel][lldb] Lldb bazel unit test expansion to core libraries (#236749)
Follow up to #232715. This adds the unit tests for lldb's core
libraries: Breakpoint, Callback, Core, DataFormatter, Expression,
Highlighter, Interpreter, Process, Protocol, Symbol, Target, Thread and
ValueObject. It also adds the lldbSymbolHelpers TestingSupport library
that several of them use. As before, target names and dependencies
follow the add_lldb_unittest() calls in CMake. SymbolTests and
TargetTests stage their Inputs/ the same way UtilityTests does.
Differences from CMake:
- //lldb:Interpreter is listed wherever //lldb:Core is. CMake gets it
through lldbCore, but the bazel Core library doesn't ddepend on
Interpreter, to avoid a cycle.
- Tests depend directly on the libraries providing the headers they
include, for layering_check. That includes testingSupport helpers, which
CMake finds through its global include directory.
- ExpressionTests assumes the AArch64 target is configured, like llvm's
target_aarch64_tests. CMake only builds that part when AArch64 is
[4 lines not shown]
Add missing devfs vmmctl rule and the volmode=dev to the example
When vmmctl is not set to unhide in devfs.rules, the example will fail.
Add it to the instructions. Further, add a volmode=dev to the zvol
creation command to not get an input/output error.
PR: 299724
Event: Olso Hackathon 2026
[libcxx] Optimize __split_buffer::__relocate by using size-based __set_valid_range (#216822)
The new size is already known.
We can directly call the `(pointer, size_type)` overload.
This avoids redundant pointer arithmetic.
[SPARC] Fix recognition of condition code clobbers (#235674)
Condition code clobbers were not detected correctly in
getRegForInlineAsmConstraint() which caused miscompilations when
building GMP.
Assisted-by: Claude
[CodeGen] Add missing vector types of up to 4096 elements (#207782)
There are vector types of 4096 elements, but some previous powers of
two lengths were missing. Add missing i8, i16, f16, bf16 vector lengths
so the sequence is complete up to 4096 elements.
Signed-off-by: Alexey Karyakin <akaryaki at qti.qualcomm.com>
[Hexagon] Allocate M and CS registers as a pair (#236522)
M and CS registers are used by circular memory instructions. One of the
M0/1 registers is used as an argument and the matching CS0/1 is used
implicitly. Currently, the CS registers are not assigned when the
corresponding intrinsics are lowered.
Currently, CS registers are reserved. Instructions using them are marked
to use both CS1 and CS0, which is incorrect. Additionally, CS is marked
as a def for PS_load* pseudoinstructions, which is also incorrect.
Problems with using undefined CS are not caught in existing code because
CS registers are reserved.
To pass inputs in both CS and M registers, define a new register class
for the M:CS pair and allow it to be allocatable.
To support multiple live cs/m pairs, implement their spilling on the
stack.
Signed-off-by: Alexey Karyakin <akaryaki at qti.qualcomm.com>
[Hexagon] NFC: Flatten calling conventions (#234977)
Hexagon calling conventions had conditions based on enabled ISA
extensions. These conditions were effectively checked twice: once in the
C backend code which selected which CC to use and another time by
conditions in the CC itself e.g. CCIfHvx64, CCIfHvx128.
Flatten the calling conventions into one and remove the checks in the
backend code.
Signed-off-by: Alexey Karyakin <akaryaki at qti.qualcomm.com>
[mlir][x86] Move AVX rsqrt approximation from Math to X86 transforms
The `math.rsqrt` polynomial approximation emitted `x86.avx.rsqrt`, which made
`MLIRMathTransforms` depend on `MLIRX86Dialect` even
though the pattern was only enabled behind an AVX2 opt-in.
Move the pattern into `MLIRX86Transforms` and expose it as
`x86::populateMathRsqrtApproximationPatterns` and the transform op
`transform.apply_patterns.x86.math_rsqrt_approximation`.
Users who relied on the AVX2 rsqrt approximation should call
`x86::populateMathRsqrtApproximationPatterns` (C++) or use
`transform.apply_patterns.x86.math_rsqrt_approximation`.
NAS-144959 / 28.0.0-BETA.1 / Retry DNS errors in catalog sync tests (#20088)
```
truenas_api_client.exc.ClientException: [EFAULT] Failed to clone 'https://github.com/truenas/apps' repository at '/run/middleware/ix-apps/catalogs' destination: fatal: unable to access 'https://github.com/truenas/apps/': Could not resolve host: github.com. See /var/log/git.log for full git output
```
happens a lot on our CI.
[mlir][Tosa] Include generated interface declarations outside of namespaces (#236103)
`TosaInterfaces.h.inc` was included from within `namespace mlir::tosa`,
relying on the interfaces in `TosaInterfaces.td` having an empty
`cppNamespace`. The interfaces now specify `cppNamespace =
"::mlir::tosa"` and the generated header is included at global scope.
---------
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
make uncm(4) NCM 1.0 spec compliant
- Payload alignment now matches NCM 1.0
- Reserved bits in bmNtbFormatsSupported are now ignored by the host as
needed for NCM 1.0
- IN NTB size was clamped to 65535 without telling the device
- Initialization order is now alt setting 0 -> NCM parameter requests
-> alt setting 1
- Stop ignoring bmNetworkCapabilities and use GET_ as fallback
- Some cleanup for printing with the right placeholder and moving
variables around
From Jan Scheiber
Tested by Jan and myself on Android phones
[flang][Semantics] Check defined-operator purity at the use site (#229976)
AnalyzeDefinedOp passed the generic's declaration to MakeFunctionRef, so
F2023 C15105 ran in the module instead of in the pure subprogram that
used the operator. This is fixed by using the call site instead of
name.source (the generic's own name). The diagnostic message now
includes the operator referenced in the pure subprogram.
Added the semantics tests that validate this feature.
Fixes #222888
Assisted by Cursor to get the root cause of issue
[DebugInfo][FLMD] Add bitcode printing/parsing for function context
This patch adds support for bitcode printing/parsing for
MDFunctionLocalContext. This is an unusual entry in that it contains
multiple variable-length arrays, and collectively comprises a potentially
very large (technically up to ~2^32, realistically >10000 is possible)
number of records. There is no abbreviation, since the existing
abbreviation mechanism does not easily translate to this case.
Also unique is that, as with the LLParser, we use a custom forward
reference resolution. In this case, we track the metadata IDs rather than
maintaining a TrackingMDRef, and resolve these at the general metadata
resolution step, where the MetadataList has been finalized.
[libunwind] Fix -Wunused-function for hasPAuthLR in ra_sign_state_lr (#236660)
hasPAuthLR() is a static function defined unconditionally in
ra_sign_state_lr.pass.cpp but it is only called from checkHasPAuthLR()
when _LIBUNWIND_HAVE_GETAUXVAL, LIBUNWIND_HAVE_ELF_AUX_INFO or
LIBUNWIND_IS_BAREMETAL is defined. On targets where none of these macros
are set (e.g. embedded AArch64 variants built against picolibc), the
#else branch is taken and hasPAuthLR() is unused causing a
-Werror,-Wunused-function build failure.
Guard hasPAuthLR() with the same preprocessor conditions as its
call-sites so it is only compiled when reachable.
Signed-off-by: Naveen <naveen.siddegowda at oss.qualcomm.com>
Co-authored-by: Naveen <naveen.siddegowda at oss.qualcomm.com>
Co-authored-by: Jack Styles <jack.styles at arm.com>
Add v81 direct-instruction lowering for IEEE HVX intrinsics (#235945)
On v81+, use direct QFloat instructions instead of v79 splat/call-based
sequences for: vabs.hf, vabs.sf, vfneg.hf, vfneg.sf, vcvt.h.hf,
vcvt.b.hf, vcvt.ub.hf, vcvt.hf.sf, vcvt.uh.hf, and vadd.sf.hf.
The vadd.sf.hf translation is the same on both v79 and v81 (no version
gating needed). vcvt.uh.hf gets a full v81 instruction sequence
replacing the call-based lowering used on v79.
Co-authored-by: Sumanth Gundapaneni <sgundapa at qti.qualcomm.com>
