sysutils/sg3_utils: 1.49
This is the first new release in three years. Among other changes, it
updates sg_opcodes with features needed by CTL's ATF tests. Also,
switch the build to cmake and take maintainership.
Much thanks to diizzy for help with the patch.
https://github.com/doug-gilbert/sg3_utils/blob/main/ChangeLog
PR: 296938
Sponsored by: ConnectWise
Approved by: diizzy (ports)
e1000: fix rx accounting for multi-descriptor packets
The receive paths accumulate ri->iri_len across the descriptors making
up a packet, then add that running total to rxr->rx_bytes on every
iteration of the loop. A packet spanning descriptors of length l1, l2
and l3 thus contributes 3*l1 + 2*l2 + l3 instead of l1 + l2 + l3.
Single descriptor packets, the common case, are accounted correctly,
so this only shows up on jumbo frames.
Add the per descriptor length instead. iflib memsets the if_rxd_info
before each isc_rxd_pkt_get() call, so summing len gives the same total
as the final iri_len, and the frame error path that returns without
incrementing rx_packets keeps counting bytes exactly as before.
MFC after: 1 week
[LV] Extract fixupHeaderPhiBackedges from VPlan::execute (NFC) (#212063)
Hoist the header-phi backedge fixup loop at the end of VPlan::execute
into a helper VPTransformState::fixupHeaderPhiBackedges.
e1000: fix 82574 MSI-X interrupt throttling
em_newitr() and the per-queue interrupt_rate sysctl both tested
que->msix to decide whether an 82574 is running in MSI-X mode. 0 is a
valid MSI-X vector so queue 0 was misclassified as legacy/MSI.
Test sc->intr_type == IFLIB_INTR_MSIX instead. While here, index the tx
EITR read by tque->msix rather than tque->me so it matches the register
em_newitr() actually writes; the two differ once tx_num_queues exceeds
rx_num_queues.
Also seed que->itr_setting in em_initialize_receive_unit() with the rate
the hardware was just programmed with. Otherwise an itr_setting left
over from AIM across an interface re-init makes the change detection in
em_newitr() suppress the write that would restore it, leaving the
hardware at the default rate while software believes otherwise.
Fixes: 3e501ef89667 ("e1000: Re-add AIM")
MFC after: 3 days
clang/AMDGPU: Rename amdgcn triples to amdgpu in cc1 tests (14)
Replace the legacy amdgcn architecture name with amdgpu in various
test triples. This set of updates covers cases that did not have
a set -target-cpu.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DAG: Use poison in getLoad/getStore for offsets
The painful part of this is due to a few unfortunate things.
1. poison is legalized to undef
2. Non-indexed load/store encode the offset as an undef (which is
not like a TargetConstant, and does get legalized)
3. 2 asserts in DAGCombiner expect identical load/store nodes,
which assumes the offset will be preserved and not converted
between poison and undef
4. The getLoad/getStore overloads are a mess, and a path was missing
to recreate the store case with the original offset.
Firewall: NAT: Destination NAT - fix missing "well-known" in local-port, closes https://github.com/opnsense/core/issues/10612
While here, also suppress a php warning for an non-existing entry.
e1000: Defer link-up notification until after TSO reset
em_automask_tso() changes the enabled TSO capabilities when the link
moves between 10/100 and 1000 Mb/s. A running interface must be
reinitialized to apply the new capability set. Do not publish
LINK_STATE_UP until the requested iflib reset has completed.
Replace link_active with an explicit state machine that distinguishes
the physical link, its publication to iflib, and an outstanding reset
barrier. Preserve that barrier across a link flap with
DOWN_RESET_PENDING, and only publish DOWN if UP was previously
published.
Only request a reset for a running interface or for an initialization
while the interface is administratively up. In other states the next
initialization will apply the capability changes, avoiding a reset
request that iflib's admin task could discard.
Reviewed by: Faraz Vahedi <kfv at kfv.io>
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clang/AMDGPU: Migrate -aux-triple amdgcn in cc1 tests to amdgpu (13) (#212052)
Update to the new architecture name.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
clang/AMDGPU: Migrate OpenMP cc1 tests to amdgpu triples (12) (#212051)
Migrate the OpenMP offload cc1 tests to the new amdgpu triple scheme:
* -fopenmp-targets=amdgcn-amd-amdhsa ->
-fopenmp-targets=amdgpu-amd-amdhsa
(the offload toolchain triple, the generic amdgpu arch).
* The device -triple amdgcn-amd-amdhsa -> amdgpu-amd-amdhsa, or to the
specific subarch triple (dropping -target-cpu) where a -target-cpu was
present.
Autogenerated CHECK lines are regenerated, and the few -Wopenmp-target-
exception diagnostics that embed the triple string are updated. Tests
that
intentionally assert the "target-cpu" function attribute are left
unchanged.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[VPlan] Add VPRegionBlock::getEntryBranchOnMask helper (NFC) (#212060)
Add an accessor returning the VPBranchOnMaskRecipe guarding a replicate
region, i.e. the sole recipe of the region's entry block.
