[OffloadBundler] Bound compressed bundles by header size, not magic scan
When multiple offload bundles are concatenated, the unbundler
(clang-offload-bundler) and llvm-objdump --offloading located the end of a
compressed bundle, and the start of the next one, by scanning for the next
"CCOB" magic string starting right after the current header.
A zstd/zlib-compressed payload can legally contain those four bytes, so the
scan could stop in the middle of the compressed data and truncate the
bundle, corrupting the embedded code object. In practice this produced a
"decomposition" failure for hipBLASLt bf16 GEMMs on gfx942.
Use the authoritative total-size field recorded in the compressed bundle
header (format V2/V3) to compute the exact bundle boundary, and only scan
for the next magic past that point. Legacy bundles without a recorded size
(V1) keep the previous magic-scan fallback.
A skippable-frame fixture that embeds "CCOB" inside the compressed payload
is added to exercise the boundary logic from both clang-offload-bundler and
llvm-objdump --offloading.
[VPlan] Eliminate some vec temps with ArrayRef (NFC) (#207432)
The enabling change is e56187575 ([ArrayRef] Make iterator_range
constructor const-agnostic, #205183).
dashboard: include interfaces widget in dashboard default. Closes https://github.com/opnsense/core/issues/10456
This is the only one that makes sense from a functional perspective.
While here, adjust the resize/style logic a bit such that
updates are also propagated on first load, which makes sure the
interfaces table renders the correct amount of columns to prevent
wasted space.
(cherry picked from commit 83236171bb98b61b2aeb97e273f8ee28a53385f8)
[libc++] Implement LWG4472: std::atomic_ref<const T> can be constructed from temporaries (#208131)
## Summary
- Implements LWG4472, i.e., adds a deleted `atomic_ref(T&&)` overload to
the primary template and three partial specializations of `atomic_ref`.
## Test
- Added `static_assert`s in `ctor.pass.cpp` asserting
`atomic_ref<T>`/`atomic_ref<const T>` reject construction from
`T&&`/`const T&&`.
Resolve #189840
[Offload] Make compressed offload bundle header little-endian (#206744)
The compressed offload bundle (CCOB) header integer fields (Version,
Method, FileSize, UncompressedFileSize, Hash) were serialized and read
in
host-native byte order. The on-disk format is little-endian, so on
big-endian hosts these fields were byte-swapped: writing produced a
malformed header, and reading misparsed the size, making
`llvm-objdump --offloading` crash/misbehave on s390x. This is also why
the
earlier bundle-size fix had to be reverted.
Make the header little-endian on every host:
- Read side: declare the `RawCompressedBundleHeader` fields as
`support::ulittle16_t` / `ulittle32_t` / `ulittle64_t`, so the bytes are
always interpreted as little-endian regardless of host.
- Write side: emit the header with
`support::endian::Writer(OS, endianness::little)` instead of host-native
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firewall: adjust alias rename according to address_to_pconfig(); closes #10024
Looking at stable/25.7 where all three components where still in
the tree they all use the function which could potentially write
'address'. It's better than not having those and strive for
consistency although in practice this will die with the removal
of legacy rules support.
[NVPTX] Add native `tanh.approx` support for f16/f16x2/bf16/bf16x2 (#203257)
Adds NVPTX backend support for the native PTX `tanh.approx` instructions on half-precision and bfloat types:
- `tanh.approx.f16` and `tanh.approx.f16x2` (PTX 7.0+, sm_75+)
- `tanh.approx.bf16` and `tanh.approx.bf16x2` (PTX 7.8+, sm_90+)
Adds a `FTANHInst` TableGen class with the new patterns in NVPTXInstrInfo.td and splits `ISD::FTANH` out of the unconditional `f16/bf16 -> f32` promotion loop in NVPTXISelLowering.cpp, marking it Legal when the target supports it (scalars promote, vectors expand on older targets). Also guards `tanh.approx.f32` behind sm_75 and adds the
missing `AddPromotedToType` for bf16.
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-tanh
Signed-off-by: Varad Rahul Kamthe <vkamthe at nvidia.com>
[SelectionDAG] Widen even 33-bit-magic udiv on free-zext targets (#207634)
On 64-bit targets, #181288 lowers a 32-bit unsigned division by a
constant with a 33-bit magic number (the `IsAdd` case) to a widened
64-bit high-multiply (`MULHU`/`UMUL_LOHI`), e.g. `x / 7` becomes a
single `mulq`/`umulh`/`mulhu`. That only reaches odd divisors. This
patch extends it to even divisors on targets where the `i32 -> i64`
zero-extension is free.
[AMDGPU] Clean up GFX13 feature list
GFX13 features were previously mostly inherited from GFX12/GFX1250.
- define an explicit gfx13 target parser feature list, including
gfx13-insts and cvt-pknorm-vop3-insts.
- remove transpose load F4/F6 support from gfx13 (previously copied from gfx12)
[VPlan] Add VPInstruction::Intrinsic opcode, use for scalar intrinsics. (#207541)
This patch adds a new Intrinsic opcode to VPInstruction, initially used
for generating calls to scalar intrinsics. The intrinsic ID as integer
is the last operand (i.e. the called function). Alternatively we could
also create the needed intrinsic declarations and pass the function
directly, but that would add potentially unused declarations, if we
decide to not vectorize.
The first patch migrates just VScale, but there are other opcodes
matching directly to intrinsics, which will be replaced in follow ups.
It also gives more flexibility going forward, e.g. allows emitting
min/max intrinsics when expanding SCEV min/max expressions.
PR: https://github.com/llvm/llvm-project/pull/207541
[flang][Driver] Add option for real sum reassociation (#207377)
Compiler driver option for #207371: -freal-sum-reassociation.
Disabled by default.
Assisted-by: Codex
[AArch64] Add missing TB(N)Z achors to arith+CBZ clustering (#207725)
This patch adds missing TBZ+TBNZ anchors for arith+CBZ clustering. They
have similar nature to CBZ as specific kinds of it, so this patch
classifies them under the same subtarget feature name compactly. This is
better for Apple CPU. They can be reasonably expected to behave
similarly on AArch64 targets.
acpidmar(4): Unload maps before destruction
Remove dmar_dumpseg() as dmar_dmamap_unload() also calls dmar_dumpseg().
This changes slightly the trace output with enabled debugging. But
avoids duplicate information.
ok kettenis@
[RISCV] Adjust max stack-threshold on 64bit systems (#208223)
Shouldn't emit [-Wframe-larger-than] warning on 64-bit systems, when
stack-size is greater than UINT32_MAX (the previous default). Update the
maximum stack-size-threshold on 64-bit systems to INT64_MAX.
NOTE: GCC has both rv32/rv64 thresholds set to the respective signed
maximum unlike LLVM.
[Offload] Make compressed offload bundle header little-endian
The compressed offload bundle (CCOB) header integer fields (Magic,
Version, Method, FileSize, UncompressedFileSize, Hash) were serialized
and read in host-native byte order. The on-disk format is little-endian,
so on big-endian hosts these fields were byte-swapped: writing produced a
malformed header and reading misparsed the size, making
llvm-objdump --offloading crash/misbehave on s390x.
Use support::ulittleN_t for the header fields on the read side and
support::endian::Writer on the write side, so the header is always
little-endian regardless of host endianness.
Co-authored-by: Nikita Popov <npopov at redhat.com>
