LLVM/project 1e8c7cfllvm/include/llvm/IR OptBisect.h, llvm/lib/IR OptBisect.cpp

[OptBisect] Merge shouldRun logic of -opt-bisect and -opt-disable (#177122)

Hi everyone,

After the introduction of `-opt-disable` in,
one of its main limitations has been that it cannot be used together
with `-opt-bisect`, since `getGlobalPassGate()` returns either
`getOptDisabler()` or `getOptBisector()`, but not both. Allowing them to
work simultaneously would be useful for disabling individual passes
while still restricting the pipeline. This is especially relevant given
the recent updates to `-opt-bisect`, such as interval support.

For example, when a defect is caused by a particular pass but its impact
is masked by another, it can be difficult to identify the actual culprit
through bisecting alone. Being able to disable passes individually while
using `-opt-bisect` would make this process much more efficient.

In this PR, I have merged the logic of the two flags so that they can
interoperate. Specifically:

    [11 lines not shown]
DeltaFile
+77-0llvm/test/Other/opt-disable-and-bisect.ll
+11-37llvm/lib/IR/OptBisect.cpp
+11-32llvm/include/llvm/IR/OptBisect.h
+14-18llvm/test/Other/opt-disable.ll
+113-874 files

LLVM/project bf02d3bllvm/test/MC/AMDGPU gfx12_asm_vop3_from_vop1.s gfx12_asm_vop1.s

[AMDGPU][AsmParser] Forbid Fake16 instructions in Real16 mode (#176934)

We don't need to support both simultaneously in tests now that all
True16 instructions are supported.
DeltaFile
+56-56llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
+30-45llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
+46-19llvm/test/MC/AMDGPU/literals.s
+32-32llvm/test/MC/AMDGPU/gfx11_asm_vinterp.s
+14-47llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
+28-28llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
+206-22712 files not shown
+319-34218 files

FreeBSD/ports 9614f79x11-wm/mangowc distinfo Makefile

x11-wm/mangowc: Update to 0.11.0

ChangeLog:      https://github.com/DreamMaoMao/mangowc/releases/tag/0.11.0
Reported by:    DreamMaoMao <notifications at github.com>
DeltaFile
+3-3x11-wm/mangowc/distinfo
+1-1x11-wm/mangowc/Makefile
+4-42 files

LLVM/project cee36b2llvm/docs LangRef.rst, llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp

[IR] Allow non-constant offsets in @llvm.vector.splice.{left,right} (#174693)

Following on from #170796, this PR implements the second part of
https://discourse.llvm.org/t/rfc-allow-non-constant-offsets-in-llvm-vector-splice/88974
by allowing non-constant offsets in the vector splice intrinsics.

Previously @llvm.vector.splice had a restriction enforced by the
verifier that the offset had to be known to be within the range of the
vector at compile time. Because we can't enforce this with non-constant
offsets, it's been relaxed so that offsets that would slide the vector
out of bounds return a poison value, similar to
insertelement/extractelement.

@llvm.vector.splice.left also previously only allowed offsets within the
range 0 <= Offset < N, but this has been relaxed to 0 <= Offset <= N so
that it's consistent with @llvm.vector.splice.right.

In lieu of the verifier checks that were removed, InstSimplify has been
taught to fold splices to poison when the offset is out of bounds.

    [5 lines not shown]
DeltaFile
+94-0llvm/test/Transforms/InstSimplify/vector-splice.ll
+80-0llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+52-11llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
+24-20llvm/docs/LangRef.rst
+19-24llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+37-0llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
+306-5513 files not shown
+377-14119 files

FreeBSD/ports 7a7bd06net-im/linux-discord distinfo Makefile

net-im/linux-discord: Update to 0.0.121
DeltaFile
+3-3net-im/linux-discord/distinfo
+1-1net-im/linux-discord/Makefile
+4-42 files

LLVM/project c286dc2llvm/docs LangRef.rst, llvm/include/llvm/IR FixedMetadataKinds.def

IR: Add !nofpclass metadata

This adds the analagous metadata to the nofpclass attribute
to assert values are not a certain set of floating-point classes.
This allows the same information to be expressed if a function
argument is passed indirectly. This matches the bitmask encoding
of nofpclass.

I also think this should be allowed for stores to symmetrically handle
sret, but leave that for later.

Alternatively we could add a more expressive !fprange metadata,
but that would be much more complex. It's useful to match the attribute,
and more annotations can always be added.

Fixes #133560
DeltaFile
+101-0llvm/test/Verifier/nofpclass-metadata.ll
+58-0llvm/test/Transforms/Attributor/nofpclass.ll
+31-0llvm/docs/LangRef.rst
+25-0llvm/lib/IR/Verifier.cpp
+11-0llvm/lib/Analysis/ValueTracking.cpp
+1-0llvm/include/llvm/IR/FixedMetadataKinds.def
+227-06 files

FreeBSD/ports 76db1d9ports-mgmt/pkg_replace distinfo Makefile

ports-mgmt/pkg_replace: Update 20260115 => 20260121

Changelog:
https://github.com/kdeguchi/pkg_replace/releases/tag/20260121

PR:     292623
DeltaFile
+3-3ports-mgmt/pkg_replace/distinfo
+1-1ports-mgmt/pkg_replace/Makefile
+4-42 files

LLVM/project 7dfd963clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp, clang/lib/Sema SemaOpenMP.cpp

[clang] Fix a couple of gcc Wparentheses warnings. NFC. (#177134)

DeltaFile
+3-3clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+2-3clang/lib/Sema/SemaOpenMP.cpp
+5-62 files

FreeBSD/ports ed25d4ebiology/gkl Makefile

biology/gkl: pin to jdk 8 and 11

Error on jdk17+:
Could NOT find JNI (missing: JAVA_INCLUDE_PATH JAVA_INCLUDE_PATH2 AWT JVM)
...
CMake Error: The following variables are used in this project, but they are set to NOTFOUND.
Please set them or make sure they are set and tested correctly in the CMake files:
JAVA_AWT_INCLUDE_PATH (ADVANCED)

PR:     292244
Approved-by:    maintainer timeout
DeltaFile
+1-0biology/gkl/Makefile
+1-01 files

LLVM/project 5afabf1llvm/test/CodeGen/AArch64 arm64-neon-simd-ldst-one.ll

[AArch64] Correct SD/GI test checks in arm64-neon-simd-ldst-one.ll. NFC
DeltaFile
+29-29llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
+29-291 files

FreeBSD/ports 30bfbb1comms/java-simple-serial-connector Makefile, devel/arduino18 Makefile pkg-plist

devel/arduino18: support jdk11+

Java 8 had a jre/lib/ext directory which does not exist anymore.
Put the jssc-2.8.0.jar in JAVALIBDIR and embed it in arduino18 so we
are sure it is properly on the classpath.

NB: the patch is modified a little bit over the attachment in the
issue. It now uses less local patches than the original patch.

PR:     292242
Approved-by:    maintainer timeout
DeltaFile
+8-6devel/arduino18/Makefile
+4-5comms/java-simple-serial-connector/Makefile
+1-0devel/arduino18/pkg-plist
+13-113 files

LLVM/project d106397flang/lib/Optimizer/OpenACC/Support CMakeLists.txt

[flang][acc] fix shared libs after #176924 (#177135)

Fix https://lab.llvm.org/buildbot/#/builders/204/builds/33651
DeltaFile
+2-0flang/lib/Optimizer/OpenACC/Support/CMakeLists.txt
+2-01 files

LLVM/project 521c50allvm/lib/Target/AArch64 AArch64AsmPrinter.cpp, llvm/test/CodeGen/AArch64 ptrauth-intrinsic-auth-resign-with-blend.ll

[AArch64][PAC] Rework the expansion of AUT/AUTPAC pseudos

Refactor `AArch64AsmPrinter::emitPtrauthAuthResign` to improve
readability and fix the conditions when `emitPtrauthDiscriminator` is
allowed to clobber AddrDisc.

* do not clobber `AUTAddrDisc` when computing `AUTDiscReg` on resigning
  if `AUTAddrDisc == PACAddrDisc`, as it would prevent passing raw,
  64-bit value as the new discriminator
* move the code computing `ShouldCheck` and `ShouldTrap` conditions to a
  separate function
DeltaFile
+63-42llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+67-10llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-with-blend.ll
+130-522 files

LLVM/project 2746245llvm/lib/Target/AArch64 AArch64AsmPrinter.cpp

[AArch64][PAC] Group arguments of emitPtrauthAuthResign (NFC)

The caller of `AArch64AsmPrinter::emitPtrauthAuthResign` has to analyze
the operands of MachineInstr being emitted and pass them explicitly to
this method, which leads to large number of function arguments, some of
them being optional.

This commit introduces `struct PtrAuthSchema` to pass semantically-
related parameters as a single argument and to better express the idea
that the second schema can only be passed or omitted as a whole.

Furthermore, `AUTVal` argument is renamed to `Pointer`, as unlike other
arguments with the `AUT` prefix, it does not relate to the authentication
schema, but represents a tied in-out operand used throughout the entire
expanded instruction sequence.
DeltaFile
+68-39llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+68-391 files

LLVM/project 790bcc5llvm/tools/llvm-objcopy llvm-objcopy.cpp

[NFC][llvm-objcopy] Eliminate else after return in llvm-objcopy (#177112)

Eliminate else after return in `getDriverConfig`.

Signed-off-by: Ruoyu Qiu <cabbaken at outlook.com>
DeltaFile
+6-4llvm/tools/llvm-objcopy/llvm-objcopy.cpp
+6-41 files

NetBSD/pkgsrc 61FV7DCdoc CHANGES-2026

   Updated textproc/py-elementpath, mail/py-mailsuite
VersionDeltaFile
1.536+3-1doc/CHANGES-2026
+3-11 files

LLVM/project 064cbecmlir/lib/Dialect/GPU/Transforms KernelOutlining.cpp, mlir/test/Dialect/GPU outlining.mlir

[MLIR][GPU] Make sure to propagate known cluster sizes in kernel outlining (#176894)

Otherwise, the changes from #174404 don't kick in.
DeltaFile
+4-0mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
+1-0mlir/test/Dialect/GPU/outlining.mlir
+5-02 files

NetBSD/pkgsrc FewVLjGmail/py-mailsuite distinfo Makefile

   py-mailsuite: updated to 1.11.2

   1.11.2
   Support Python 3.14+
VersionDeltaFile
1.9+4-4mail/py-mailsuite/distinfo
1.12+2-2mail/py-mailsuite/Makefile
+6-62 files

NetBSD/pkgsrc i9xf20Ctextproc/py-elementpath distinfo Makefile

   py-elementpath: updated to 5.1.1

   v5.1.1 (2026-01-20)

   * Fix external function registrations
   * Add ExternalFunction and SchemaConstructor token classes
VersionDeltaFile
1.48+4-4textproc/py-elementpath/distinfo
1.50+2-2textproc/py-elementpath/Makefile
+6-62 files

NetBSD/pkgsrc Qdfzo4odoc CHANGES-2026

   Updated sysutils/py-Send2Trash, net/py-xandikos
VersionDeltaFile
1.535+3-1doc/CHANGES-2026
+3-11 files

LLVM/project cde22d7clang/include/clang/Basic BuiltinsAMDGPU.td, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.td
+96-03 files

LLVM/project de56a2bllvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+70-4llvm/docs/AMDGPUUsage.rst
+70-41 files

LLVM/project 17e7357llvm/lib/Target/AMDGPU SIISelLowering.cpp

Refactor code and add some comments
DeltaFile
+8-6llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+8-61 files

LLVM/project 0d4a35dllvm/test/CodeGen/AArch64 f16-convert.ll, llvm/test/CodeGen/Mips/msa f16-llvm-ir.ll

IR: Remove llvm.convert.to.fp16 and llvm.convert.from.fp16 intrinsics (#174484)

These are long overdue for removal. These were originally a hack
to support loading half values before there was any / decent support
for the half type through the backend. There's no reason to continue
supporting these, they're equivalent to fpext/fptrunc with a bitcast.

SelectionDAG stopped translating these directly, and used the
bitcast + fp cast since f7a02c17628e825, so there's been no reason
to use these since 2014.
DeltaFile
+203-298llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
+29-319llvm/test/CodeGen/PowerPC/half.ll
+0-256llvm/test/CodeGen/AArch64/f16-convert.ll
+0-171llvm/test/CodeGen/X86/cvt16.ll
+0-171llvm/test/CodeGen/X86/cvt16-2.ll
+12-155llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll
+244-1,37024 files not shown
+562-2,34430 files

NetBSD/pkgsrc aZ1z1nEnet/py-xandikos PLIST distinfo

   py-xandikos: updated to 0.3.1

   0.3.1

   Bump docker/metadata-action from 5.7.0 to 5.9.0
   deps(deps-dev): bump ruff from 0.14.2 to 0.14.6 in the pip group
   Bump actions/checkout from 4 to 6
   Bump docker/metadata-action from 5.9.0 to 5.10.0
   deps(deps-dev): bump the pip group with 2 updates
   Fix two RRULE related bugs
   Fix caldav server tester
   Move tests to root
   Publish Docker images for every commit with commit SHA tags
   Add ARMv7 platform support to container builds
   Add basic chunked encoding support
   Improve error
   Limit recurrence expansion for unbounded queries
   Implement limit-freebusy-set
   Restrict supported dulwich versions

    [20 lines not shown]
VersionDeltaFile
1.13+88-58net/py-xandikos/PLIST
1.19+4-4net/py-xandikos/distinfo
1.22+2-2net/py-xandikos/Makefile
+94-643 files

LLVM/project 6dcf425mlir/include/mlir/Dialect/Tosa/IR TosaShapeOps.td, mlir/lib/Dialect/Tosa/Transforms TosaValidation.cpp

[mlir][tosa] Add support for assert equal shape op (#176900)

Adds support for assert_equal_shape operation after spec change:
https://github.com/arm/tosa-specification/commit/575a50016de50d227eb517775eb4e7b137421fa1

This includes:
- Operator definition
- Tests


Change-Id: I6652bbcbd5e3716f140681b9d73ef8940564d7d3

Signed-off-by: Iliyan Georgiev <Iliyan.Georgiev at arm.com>
DeltaFile
+19-1mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
+6-4mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+10-0mlir/test/Dialect/Tosa/level_check.mlir
+9-0mlir/test/Dialect/Tosa/ops.mlir
+8-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+8-0mlir/test/Dialect/Tosa/verifier.mlir
+60-51 files not shown
+61-57 files

LLVM/project 9c8b4dellvm/lib/Target/AMDGPU SIISelLowering.cpp

Use `WAVE_REDUCE_FSUB_PSEUDO_F64` in switch statements
DeltaFile
+18-14llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+18-141 files

LLVM/project 779d9e5llvm/lib/Target/AMDGPU SIISelLowering.cpp

Use `e32` encoding as placeholder
DeltaFile
+10-10llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+10-101 files

LLVM/project 80a87bcllvm/lib/Target/AMDGPU SIISelLowering.cpp

Use enum values for source modifiers
DeltaFile
+3-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-31 files

LLVM/project b063f1bllvm/lib/Target/AMDGPU SIISelLowering.cpp

Use pseudo opcode for switch statements
DeltaFile
+10-10llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+10-101 files