[Mips] Restrict rdhwr+synci to Linux on MIPS R6 (#222566)
The rdhwr instruction reads synci_step, which is not allowed by OpenBSD
and is not available for ISA older than mips{32/64}r2.
Restrict the rdhwr+synci to Linux on MIPS R6 and fall back to
_flush_cache on all other MIPS targets including OpenBSD and pre-R6
Linux.
Fix #219896.
[mlir][Tensor] Reject empty expand_shape reassociation groups (#222648)
`tensor.expand_shape` with an empty reassociation group (e.g. `[[]]`)
used to abort the compiler: ExpandShapeOp::verify forwarded the group to
getSymbolLessAffineMaps, which asserts on missing affine expressions.
The sibling `tensor.collapse_shape` already rejects this input with a
clean diagnostic.
Extract the empty-group check into a helper shared by both tensor
reshape verifiers, invoke it from `ExpandShapeOp::verify`, and add an
invalid.mlir regression test that used to SIGABRT.
Fixes: #222602
[mlir] Add support for multi-parts diagnostics (#217804)
Under the current MLIR diagnostic infrastructure, emitting multiple
remarks at the same location requires calling the remark API multiple
times; moreover, every call to remark prints a note. This PR introduces
the concepts of "parts" To diagnostics. A streaming manipulator, called
`next`, similar to `std::endl` can be used to split multiple parts into
a single `InFlightDiagnostic`. This can be used for example to emit
multiple remarks at the same location, share the notes for those
remarks.
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
[CFI] Don't create alias->alias chains. (#225951)
Discovered downstream after PR #225173, when CFI and HWASAN are
combined.
See also
https://github.com/llvm/llvm-project/pull/225173#issuecomment-5802301926
If there is an alias, we should leave it alone, find its aliasee, and
create a new external linkage alias to that. Even if local linkage, the
existing alias may be referenced by name by e.g. inline assembly.
[CIR] Don't create EH paths for lifetime-marker-only cleanups (#224829)
### summary
fix https://github.com/llvm/llvm-project/issues/224821
A lifetime marker is not a real cleanup, so it must never be the reason
an unwind edge exists.
Assisted by : Claude Opus5
[mlir] Fix canonicalizer crash when folding poison or kDynamic-sentinel index values (#223609)
Fixes two canonicalizer crashes, both in foldDynamicIndexList:
* #223333: tensor.extract_slice with a ub.poison offset/size crashes
canonicalization. ub.poison is matched as a constant but is not an
IntegerAttr, so getConstantIntValue returns nullopt and the subsequent
dereference asserts.
* #223336: a memref.subview offset/size/stride that wraps to
ShapedType::kDynamic (INT64_MIN) crashes canonicalization. Folding
INT64_MIN into the static array collides with the "dynamic" marker,
leaving dynamic-looking entries with no matching dynamic operands;
getMixedStrides() then asserts.
Only fold an operand when it is an integer constant whose value is not
ShapedType::kDynamic; poison and sentinel values stay dynamic operands.
Since foldDynamicIndexList is shared, this hardens all its callers.
Adds regression tests in mlir/test/Dialect/MemRef/canonicalize.mlir and
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[CIR] Make sure ptr-cast-to-vbase is guarded. (#225969)
It isn't clear how we missed this, but classic codegen does checks this,
so we should too.
Claude Helped diagnose/debug, but I did the copy/pasting :D
[clang] Inconsistent attributes for `dllexport __cxxabiv1:: __fundamental_type_info` with `-fvisibility=hidden` (#215859)
Fixes #207963
The issue is `__declspec(dllexport)` and `hidden` visibility cannot be
used together. LLVM rejects `globals` that have both attributes.
For normal globals, `CodeGenModule::setGlobalVisibility` already handles
this by giving `dllexport` priority over the visibility implied by
`-fvisibility=hidden`. RTTI follows a different code path, though.
`ItaniumRTTIBuilder::BuildTypeInfo` applies the visibility and DLL
storage class separately to the generated `_ZTI*` and `_ZTS*` globals,
so the conflict was not resolved.
As a result, marking `__cxxabiv1::__fundamental_type_info` as
`dllexport` while compiling with `-fvisibility=hidden` could generate
RTTI globals with both hidden visibility and `dllexport`, causing LLVM
to fail verification with Broken module found. The same problem can
occur for `dllexport`-ed polymorphic classes when targeting Windows with
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ig4: Add Lunar Lake-M I2C controllers 4 and 5
Commit 851dffef532a added the Lunar Lake-M I2C controllers 0 through 3
(0xa878-0xa87b), which sit on PCI device 0x15. The platform exposes two
further controllers at 0xa850 and 0xa851 on PCI device 0x19, reported by
Intel as I2C #4 and #5. This mirrors the layout already handled for
Arrow Lake-U, where both the 0x777x and 0x775x ranges are listed.
On an HP OmniBook X Flip 16-as0xxx (Core Ultra 9 288V) the firmware
enables only four of the six controllers, and both HID devices sit on
the two that were missing: an ELAN2514 touchscreen on controller 4 and
a SYNA3503 touchpad on controller 5. Neither attaches without this
change, so the machine has no working pointing device.
Like the other four, these use the Tiger Lake revision of the I2C IP;
Linux treats 0xa850/0xa851 identically to 0xa878-0xa87b in
intel-lpss-pci.c.
Tested on: HP OmniBook X Flip 16-as0xxx (Intel Core Ultra 9 288V)
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ig4: Add support for Lunar Lake-M I2C
this patch adds PCI IDs to the ig4(4) driver:
- Lunar Lake-M (0xa878, 0xa879, 0xa87a, 0xa87b)
These controllers use the Tiger Lake hardware revision of the I2C IP.
Adding these IDs enables support for peripherals connected to the I2C Bus.
Tested on: Intel Lunar Lake (LENOVO_MT_21QX_BU_Think_FM_ThinkPad T14s Gen 6)
Signed-off-by: Defenso-EBO <etienne.bonnand at defenso.fr>
MFC after: 2 weeks
Sponsored by: Defenso
Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/1995
(cherry picked from commit 851dffef532ad9611fcaf02318744c8de9f397b0)
CI: Remove centos-streamX from default builders
In practice, we've seen limited benefit from always running the
centos-stream9 and centos-stream10 builders as part of the CI.
Remove them from the default set of builders to reduce the CI
load per PR. They may still be optionally requested.
Reviewed-by: Alexander Moch <mail at alexmoch.com>
Reviewed-by: George Melikov <mail at gmelikov.ru>
Reviewed-by: Tony Hutter <hutter2 at llnl.gov>
Signed-off-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Closes #19182
[BOLT] Include indirect calls/branches in basic block count estimation (#225104)
**Before:** When BOLT adjusts basic block counts in LBR mode it
considers outgoing branch counts when `--fix-block-counts` is enabled.
This adjustment was made according to the counts of direct calls and
branches which are recorded in the `Count` annotation made in
`DataReader::convertBranchData`. Indirect calls and branches are also
recorded within the `CallProfile` annotation, however they do not
contribute to the adjustment of basic block counts.
**After:** When making this adjustment to basic block counts, also
consider the counts of indirect calls and branches within the
`CallProfile` annotation. Do this by summing the execution counts of the
targets from this call/branch and considering them in determining the
maximum execution count of the basic block.
Assisted by: Codex. This was to write the tests for `x86` and `RISCV`
targets.
ig4: Add Lunar Lake-M I2C controllers 4 and 5
Commit 851dffef532a added the Lunar Lake-M I2C controllers 0 through 3
(0xa878-0xa87b), which sit on PCI device 0x15. The platform exposes two
further controllers at 0xa850 and 0xa851 on PCI device 0x19, reported by
Intel as I2C #4 and #5. This mirrors the layout already handled for
Arrow Lake-U, where both the 0x777x and 0x775x ranges are listed.
On an HP OmniBook X Flip 16-as0xxx (Core Ultra 9 288V) the firmware
enables only four of the six controllers, and both HID devices sit on
the two that were missing: an ELAN2514 touchscreen on controller 4 and
a SYNA3503 touchpad on controller 5. Neither attaches without this
change, so the machine has no working pointing device.
Like the other four, these use the Tiger Lake revision of the I2C IP;
Linux treats 0xa850/0xa851 identically to 0xa878-0xa87b in
intel-lpss-pci.c.
Tested on: HP OmniBook X Flip 16-as0xxx (Intel Core Ultra 9 288V)
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ig4: Add support for Lunar Lake-M I2C
this patch adds PCI IDs to the ig4(4) driver:
- Lunar Lake-M (0xa878, 0xa879, 0xa87a, 0xa87b)
These controllers use the Tiger Lake hardware revision of the I2C IP.
Adding these IDs enables support for peripherals connected to the I2C Bus.
Tested on: Intel Lunar Lake (LENOVO_MT_21QX_BU_Think_FM_ThinkPad T14s Gen 6)
Signed-off-by: Defenso-EBO <etienne.bonnand at defenso.fr>
MFC after: 2 weeks
Sponsored by: Defenso
Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/1995
(cherry picked from commit 851dffef532ad9611fcaf02318744c8de9f397b0)
[mlir][Affine] Prevent buffer hoisting out of affine.parallel (#225324)
I noticed that `buffer-loop-hoisting` can move allocations out of
`affine.parallel`, making a buffer that should be local to each
iteration shared between the parallel iterations.
`AffineParallelOp` implements `LoopLikeOpInterface` but was missing the
`HasParallelRegion` trait, so `isSequentialLoop` treated it as
sequential. This adds the missing trait to `affine.parallel`, allowing
the pass to recognize the parallel boundary without changing the
hoisting logic.
I’ve added a regression test based on the reproducer in #225149, which
checks that the allocation stays inside `affine.parallel` and that the
store and load still use that allocation.
Fixes #225149.
[Clang][RISCV] Add packed widening subtraction accumulate intrinsics (#225764)
Add Clang header intrinsics for the RISC-V P-extension packed widening
subtraction accumulate operations:
- __riscv_pwsuba_i16x4
- __riscv_pwsuba_i32x2
- __riscv_pwsubau_u16x4
- __riscv_pwsubau_u32x2
Each computes rd + (a - b). The header wrappers use generic LLVM IR,
so RV32 selects the direct `pwsuba.*` / `pwsubau.*` instructions while
RV64 lowers the generic IR to the decomposition specified by the
P-extension intrinsic spec.
[Clang][RISCV] Add packed subvector insert intrinsics (#225771)
Add __riscv_pset_i8x4_i8x8, __riscv_pset_u8x4_u8x8,
__riscv_pset_i16x2_i16x4 and __riscv_pset_u16x2_u16x4, which insert a
32-bit packed subvector into a 64-bit packed vector. The index selects
the low or high half and must be a constant, enforced with
__enable_if__ as for the element insert intrinsics.
[flang][cuda] Defer data-transfer conversion in OpenACC routines (#225906)
Add an option so cuf-convert can leave cuf.data_transfer in the
host copy of an OpenACC routine until host/device specialization.
After that, transfers in a specialized device body become
assignments. Place allocas inside IsolatedFromAbove offload
regions so later FIR lowering does not store into a temporary
defined outside acc.compute_region.
[RISCV][P-ext] Select PPAIREO.W when packing with the high word of a value (#225763)
The low-half packed subvector insert is a v2i32 whose low word is the
subvector and whose high word is the high word of the wide vector,
which is exactly `ppaireo.w` (the low word comes from `rs1`, the high
word from `rs2`). Select it directly instead of `srli` + `pack`.
Adds `rvp-ppaireo-w.ll`; `rvp-simd-64.ll` is updated because the scalar
low insert in `test_insert_vector_32` now selects `ppaireo.w`.
[SCCP] Call correct simplifyBinOp in FP operation
This simplify FPOps with correct FMF, which covers non-inlined function
that can not be simplified by InstComb pass.
Also, update the TODO as we have cover that case in simplifyBinOp. But
per-element optimization is not enable as we don't have structure-like
LatticeMap for vector.
