[RISCV] Fix vp-intrinsics args in cost model tests. NFC (#112463)
This patch contains following changes to fix vp intrinsics tests.
1. v\*float -> v\*f32, v\*double -> v\*f64 and v\*half -> v\*f16
2. Fix the order of the vp-intrinsics.
GlobalISel: Fix combine duplicating atomic loads
The sext_inreg (load) combine was not deleting the old load instruction,
and it would never be deleted if volatile or atomic.
[mlir][LLVMIR] Add operand bundle support for llvm.intr.assume (#112143)
This patch adds operand bundle support for `llvm.intr.assume`.
This patch actually contains two parts:
- `llvm.intr.assume` now accepts operand bundle related attributes and
operands. `llvm.intr.assume` does not take constraint on the operand
bundles, but obviously only a few set of operand bundles are meaningful.
I plan to add some of those (e.g. `aligned` and `separate_storage` are
what interest me but other people may be interested in other operand
bundles as well) in future patches.
- The definitions of `llvm.call`, `llvm.invoke`, and
`llvm.call_intrinsic` actually define `op_bundle_tags` as an operation
property. It turns out this approach would introduce some unnecessary
burden if applied equally to the intrinsic operations because properties
are not available through `Operation *` but we have to operate on
`Operation *` during the import/export of intrinsics, so this PR changes
it from a property to an array attribute.
[Coroutines] Improve dump of BB label to avoid str copies (#112374)
* This avoids the need to call printAsOperand that requires use of an
ostream and thus avoids a str copy.
* ModuleSlotTracker is used to get a BB # for BB's without names when
dumping SuspendCrossingInfo and materialization info.
* getBasicBlockLabel() is changed to dumpBasicBlockLabel() that directly
prints the label to dbgs()
* The label corresponds with the print-before BB #s.
* This change does not require any additional arguments to be added to
dump() methods, at least those that currently do not require any args.
Co-authored-by: tnowicki <tnowicki.nowicki at amd.com>
[lld] Fix warning in SymbolTable.cpp (#112323)
Fix gcc warning:
lld/ELF/SymbolTable.cpp:340:33: warning: enumeral and non-enumeral type
in conditional expression [-Wextra]
Update to R48 ("Cadmium"):
Features/Fixes
* Emulated VERA SPI clock has been updated to half of the VERA clock speed
rather than the CPU clock.
* Trace for ROM banks 13-15 (x16edit and Basload) is now supported
[stefan-b-jakobsson]
* Fixed debug reads from the stack and a few unbounded values in the
debugger display
* VERA PSG: for the saw and triangle waves, the inverse of the pulse width
value is XORed with the value of the wave. This is the behavior of VERA
47.0.2 on hardware. [m00dawg]
* Allow setting the amount of RAM in the web version of the emulator
[JimmyDansbo]
* Windows 11: Rounded corners should no longer cut off the lower left and
lower right of the emulator window.
* New memory statistics feature [irmen]
* HostFS: Implement DOS "T"ell command
* Debugger now includes elapsed cpu clocks since the last breakpoint or step
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[ORC][llvm-jitlink] Add support for forced loading of archive members.
This patch adds support for forced loading of archive members, similar to the
behavior of the -all_load and -ObjC options in ld64. To enable this, the
StaticLibraryDefinitionGenerator class constructors are extended with a
VisitMember callback that is called on each member file in the archive at
generator construction time. This callback can be used to unconditionally add
the member file to a JITDylib at that point.
To test this the llvm-jitlink utility is extended with -all_load (all platforms)
and -ObjC (darwin only) options. Since we can't refer to symbols in the test
objects directly (these would always cause the member to be linked in, even
without the new flags) we instead test side-effects of force loading: execution
of constructors and registration of Objective-C metadata.
rdar://134446111
Update to R48 ("Cadmium"). Changelog:
Changelog:
BUILD
* Building BASLOAD and X16EDIT now outputs trace headers to facilitate
instruction traces in the emulator for those banks. [stefan-b-jakobsson]
KERNAL
* Fix a few issues applying the PS/2 typematic (speed/delay) preference
after a boot. [stefan-b-jakobsson]
* Num Lock can now be turned off.
* Added extapi command kbd_leds to fetch or set the keyboard LED state
* Added extapi command scnsiz to override the KERNAL's text resolution
* ioinit now disables all stock interrupt sources (VERA, VIAs, and YM2151)
* 65C816 default native NMI handler now chains to the 65C02 one
* Fixed a bug which caused backspace and quote mode glitches in the BASIC
editor when the background color was set to 8 or above.
* Removed some unused code for softclock and C64 RS-232 [Fulgen301]
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release.sh: Pass ARCH_FLAGS when setting VMSIZE
The default VM size may depend on the architecture. In particular,
it is currently larged on riscv64 due to a toolchain issue which
results in bloated binaries.
MFC after: 3 days
Fixes: 59c21ed6e811 "release: Bump default VM size for riscv64 to 6 GB"
Sponsored by: Amazon
(cherry picked from commit ed807f7bcaecbf32b0b81a7d18cee489a3666157)
release: Bump default VM size for riscv64 to 6 GB
Due to issues with the riscv64 toolchain, some binaries end up
significantly larger on riscv64 than they should be. This results
in riscv64 VM images -- and at present *only* riscv64 images -- not
fitting within the default 5 GB filesystem size.
Bump the default size for riscv64 to 6 GB until the toolchain issues
can be resolved.
MFC after: 1 week
Sponsored by: Amazon
(cherry picked from commit 59c21ed6e811c753f7806766ba45a5bfa71ae2ed)
devel/xtensa-esp-elf: Add espressif bin wrappers
Build and install the espressif rust based wrapper.
According to upstream, the target xtensa cpu is set via the
XTENSA_GNU_CONFIG environment variable for gcc 12 and later.
In addition to esp32 the esp32s2 and esp32s3 target cpus are now
supported.
While we're here, change to USE_GCC=yes:build.
PR: 281951
