monit: allow spaces in places
Monit model never had a security concept and GHSA-fq94-cxvc-9r7w made
sure to restrict the fields, but went a bit too far with them.
PR: https://forum.opnsense.org/index.php?topic=52263.0
[RFC][AMDGPU][lld] Add object linking support
Add AMDGPU ELF object-linking support in lld, including resource propagation,
LDS layout, indirect-call handling, named-barrier updates, target compatibility
checks, and kernel descriptor/metadata patching.
This is a large PR because the linker needs to understand and validate several
AMDGPU object-linking concepts end to end. I tried to keep the changes scoped to
the necessary linker support and related metadata plumbing, but I'm open to
suggestions on how to split or structure the review to make it easier.
[RISCV] Constant fold bitcast of constant 0 in combineVectorSizedSetCCEquality. (#207112)
There seem to be some combinations of vector type and scalar type where
a bitcast of constant 0 doesn't get folded or type legalized to a
build_vector of 0 with the vector type we want. I think it's when the
integer type is 2*xlen and <2 x iXLen> is a legal type, but I'm not
sure.
I don't have any other tests to know if adding/improving a DAG combine
is worthwhile so I just did this quick fix at the source.
[RISCV] Rework vmsge(u).vx pseudos to work better with near-miss assembler support (#207097)
Previously we had 3 pseudos:
vr destination with no mask
vrnov0 destination with mask
vr destination with mask and temporary dest
This was intended to prevent a v0 destination with mask and no
temporary. The vrnov0 case confused the near miss code and caused
multiple errors.
This patch reduces to 2 pseudos:
vr destination with optional mask
vr destination with mask and pseudo
The v0 destination with mask error is moved to validateInstruction which
allows us to give a better error.