[AMDGPU] Support partial and empty WWM pools for SGPR spills
SGPR lane spilling currently treats the WWM VGPR pool as all-or-nothing. This
can fail compilation when the requested pool cannot be formed, even though
scratch spilling or a smaller spillable pool could make progress.
This PR lets ordinary SGPR spills fall back to scratch when the pool is empty
and lets WWM register allocation use a nonempty partial pool. It keeps the
full-pool requirement for strict WWM/WQM and explicit spill-carrier
preallocation.
The no-pool fallback is recorded in SIMachineFunctionInfo so frame lowering can
provide enough emergency scavenging slots. The state is also serialized to
preserve the behavior across MIR round trips.
Add a MKRAID build option, which defaults to yes everywhere except
m68000, which controls building of RAID-related utilities (including
hardware RAID controllers).
[mlir-c] Add structural operation equivalence (#206537)
Exposes `OperationEquivalence` through the MLIR C API so callers can compare operations structurally rather than by handle identity.
Assisted by: Claude
[lld][MachO] Avoid quadratic iteration over already-folded symbols during ICF (#213339)
`ConcatInputSection::foldIdentical()` clears the folded functions
`originalUnwindEntry`.
However, it cleared every symbol: with N members, the repeated clearing
is **O(N²)**.
This is redundant: we should only remove the incoming `copy->symbols`.
This patch moves the removing loop ahead and adds more clear comments on
why we need to skip the first element.
Also added a new `lld/test/MachO/icf-scale-same-class.s` with 500K
identical functions as a stress test, which would've taken minutes to
link, and less than a second with the patch.
Testing on real-world app (IRPGO instrumentation + ICF) find that we
achieved a 19x speed up (1:14:42 -> 3:55)
clang/AMDGPU: Require 16-bit-insts for half typed image builtins
Typed image load/store operations with 16-bit elements require d16
support which was introduced in gfx8. They were previously gated only
on image-insts, so they were wrongly accepted on targets that have
images but lack 16-bit support (e.g. gfx700), where the backend then
fails to select.
Co-Authored-By: Claude (Opus 4.8) <noreply at anthropic.com>
clang/AMDGPU: Require 16-bit-insts for half typed buffer format builtins
Typed buffer format load/store operations with 16-bit elements require
d16 support which was introduced in gfx8. These builtins previously had
no required features at all, so they were accepted (and then crashed the
backend) on targets without 16-bit support.
Diagnose these in Sema, parallel to the image builtins. The manual
verification here suprised me. The automatic builtin feature verification
is enforced in codegen, which seems like a layering violation which
should be fixed.
Co-Authored-By: Claude (Opus 4.8) <noreply at anthropic.com>
clang: Replace Is*OffloadArch free functions with OffloadArch methods
Drop the IsNVIDIAOffloadArch/IsAMDOffloadArch/IsIntel*OffloadArch free
functions in favor of the OffloadArch member predicate functions.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
