LLVM/project a967cb6llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx/ir-instruction shuffle-as-xvpermi.ll shuffle-as-xvshuf.ll

fix
DeltaFile
+6-3llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll
+4-4llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpermi.ll
+4-4llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpermi.ll
+4-2llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vshuf.ll
+3-3llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvshuf.ll
+2-2llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+23-186 files

LLVM/project f38bb55llvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchLSXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction shuffle-as-xvpermi.ll shuffle-as-xvshuf.ll

[LoongArch] Custom legalize vector_shuffle to `[x]vpermi.w`
DeltaFile
+118-14llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+3-7llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpermi.ll
+2-8llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vshuf.ll
+3-7llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpermi.ll
+3-6llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvshuf.ll
+7-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+136-422 files not shown
+144-468 files

LLVM/project cbc59b5llvm/test/CodeGen/LoongArch/lasx/ir-instruction shuffle-as-xvpermi.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction shuffle-as-vpermi.ll

[LoongArch][NFC] Pre-commit tests for `[x]vpermi.w`
DeltaFile
+41-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpermi.ll
+41-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpermi.ll
+82-02 files

LLVM/project ea9ec7corc-rt/include/orc-rt WrapperFunction.h SimpleNativeMemoryMap.h, orc-rt/include/orc-rt-c WrapperFunction.h

[orc-rt] Rename 'Session' variables to avoid ambiguity with type. NFCI. (#168999)

Re-using Session as a variable name risks confusion with the Session
type.
DeltaFile
+24-27orc-rt/include/orc-rt/WrapperFunction.h
+20-26orc-rt/unittests/SPSWrapperFunctionTest.cpp
+8-12orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
+8-10orc-rt/unittests/DirectCaller.h
+8-8orc-rt/include/orc-rt/SimpleNativeMemoryMap.h
+2-3orc-rt/include/orc-rt-c/WrapperFunction.h
+70-861 files not shown
+72-887 files

LLVM/project e4a4bb0llvm/lib/Target/PowerPC PPCISelLowering.cpp, llvm/test/CodeGen/PowerPC addition-vector-all-ones.ll vec_add_sub_doubleword.ll

[PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for adding the vector {1, 1, 1, 1} (#160882)

This patch optimizes vector addition operations involving **`all-ones`**
vectors by leveraging the generation of vectors of -1s(using `xxleqv`,
which is cheaper than generating vectors of 1s(`vspltisw`). These are
the respective vector types.
`v2i64`: **`A + vector {1, 1}`**
`v4i32`: **`A + vector {1, 1, 1, 1}`**
`v8i16`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1}`**
`v16i8`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1}`**

The optimized version replaces `vspltisw (4 cycles)` with `xxleqv (2
cycles)` using the following identity:
`A - (-1) = A + 1`.

---------

Co-authored-by: himadhith <himadhith.v at ibm.com>
Co-authored-by: Tony Varghese <tonypalampalliyil at gmail.com>
DeltaFile
+45-0llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+9-10llvm/test/CodeGen/PowerPC/addition-vector-all-ones.ll
+2-3llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
+56-133 files

LLVM/project afb9692llvm/lib/Target/LoongArch LoongArchISelLowering.cpp

rebase after vshuf4i_d was defined
DeltaFile
+1-1llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+1-11 files

LLVM/project 332f981llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx vec-shuffle-byte-rotate.ll

[LoongArch] Custom legalize vector_shuffle to `xvshuf4i.d`
DeltaFile
+28-4llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+3-7llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-rotate.ll
+2-7llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvshuf4i.ll
+33-183 files

LLVM/project 636d1dellvm/lib/Target/LoongArch LoongArchISelLowering.cpp

fix typo
DeltaFile
+1-1llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+1-11 files

LLVM/project 31e5b93llvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchISelLowering.h, llvm/test/CodeGen/LoongArch/lasx vselect.ll

[LoongArch] Custom legalize vselect to vector_shuffle for most constant condition cases
DeltaFile
+48-36llvm/test/CodeGen/LoongArch/lasx/vselect.ll
+44-34llvm/test/CodeGen/LoongArch/lsx/vselect.ll
+49-2llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+1-0llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+142-724 files

LLVM/project cc5185bclang/lib/Sema SemaModule.cpp, clang/test/Modules reference-tu-local-var.cppm

[C++20] [Modules] Check TULocal entity within exported entities

See the attached test for example.
DeltaFile
+20-1clang/lib/Sema/SemaModule.cpp
+9-0clang/test/Modules/reference-tu-local-var.cppm
+29-12 files

LLVM/project b4a0d7ellvm/lib/Target/NVPTX NVPTXIntrinsics.td NVPTXSubtarget.h

[NVPTX] Fix PTX and SM conditions for narrow FP conversions (#168680)

This change fixes the PTX and SM conditions for narrow FP
conversion intrinsics and adds support for family-conditionals.
DeltaFile
+27-25llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+21-0llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+48-252 files

LLVM/project 5b60734llvm/lib/Target/AMDGPU SIShrinkInstructions.cpp

clang-format
DeltaFile
+5-3llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+5-31 files

LLVM/project e1a745bllvm/lib/Target/AMDGPU SIShrinkInstructions.cpp

[AMDGPU] Make SIShrinkInstructions pass return valid changed state
DeltaFile
+60-35llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+60-351 files

LLVM/project 5c5c83dllvm/lib/Target/PowerPC PPCISelLowering.cpp

[PowerPC] Fix Wparentheses warning

PPCISelLowering.cpp:15567:27: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
15567 |          CC == ISD::SETEQ && "CC mus be ISD::SETNE or ISD::SETEQ");
      |          ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DeltaFile
+2-2llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+2-21 files

LLVM/project cc6b9efllvm/lib/Target/AMDGPU SIISelLowering.cpp

Using `memcpy` for bit pattern
DeltaFile
+4-6llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-61 files

LLVM/project b9cb447llvm/test/CodeGen/AMDGPU constant-address-space-32bit.ll llvm.amdgcn.reduce.min.ll, llvm/test/CodeGen/X86 ldexp-avx512.ll

clear min runtime args

Created using spr 1.3.7
DeltaFile
+2,069-0llvm/test/tools/dsymutil/AArch64/stmt-seq-macho.test
+0-2,069llvm/test/tools/dsymutil/ARM/stmt-seq-macho.test
+200-1,637llvm/test/CodeGen/X86/ldexp-avx512.ll
+1,156-0mlir/test/Interfaces/TilingInterface/tile-and-fuse-consumer-using-slices.mlir
+824-144llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
+911-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+5,160-3,850431 files not shown
+18,353-11,390437 files

LLVM/project 0a231c9clang/lib/Sema SemaOpenMP.cpp, clang/test/OpenMP parallel_default_variableCategory_codegen.cpp

[Clang][OpenMP] Bug fix Default clause variable category (#168846)

Same changes as in fix for
https://github.com/llvm/llvm-project/pull/165276 except for changes in
test case :
  1)   remove unnecessary include in test to restore Ubuntu build.
This is not needed as allocatable modifier is not applicable to the
default clause in C/C++.
2) Changes in CHECK statements to accommodate testing failure on
toolchain
builders at Google, Reported by Prabhu Rajasekaran.

---------

Co-authored-by: Sunil Kuravinakop <kuravina at pe31.hpc.amslabs.hpecorp.net>
DeltaFile
+86-0clang/test/OpenMP/parallel_default_variableCategory_codegen.cpp
+3-3clang/lib/Sema/SemaOpenMP.cpp
+89-32 files

LLVM/project 645e0dcllvm/lib/Target/RISCV RISCVZilsdOptimizer.cpp RISCVLoadStoreOptimizer.cpp, llvm/test/CodeGen/RISCV zilsd-ldst-opt-prera.mir zilsd-ldst-opt-postra.mir

[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)

This commit implements a complete load/store optimization pass for the
RISC-V Zilsd extension, which combines pairs of 32-bit load/store
instructions into single 64-bit LD/SD instructions when possible.
Default alignment is 8, it also provide zilsd-4byte-align feature for
looser condition.

Related work: https://reviews.llvm.org/D144002

---------

Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
DeltaFile
+1,242-0llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
+529-0llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+219-11llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+216-0llvm/test/CodeGen/RISCV/zilsd-ldst-opt-postra.mir
+83-0llvm/test/CodeGen/RISCV/zilsd-regalloc-hints.mir
+69-0llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+2,358-118 files not shown
+2,398-1114 files

LLVM/project 8624316llvm/test/DebugInfo/RISCV relax_dwo_ranges.ll

fix
DeltaFile
+3-6llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
+3-61 files

LLVM/project 86303fbllvm/test/DebugInfo/RISCV relax_dwo_ranges.ll

fix
DeltaFile
+1-1llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
+1-11 files

LLVM/project 03ddd5cllvm/lib/CodeGen/AsmPrinter DwarfCompileUnit.cpp, llvm/test/DebugInfo/RISCV relax_dwo_ranges.ll

[dwarf] make dwarf fission compatible with RISCV relaxations 2/2

This patch makes DWARF fission compatible with RISC-V relaxations by
using indirect addressing for the DW_AT_high_pc attribute. This
eliminates the remaining relocations in .dwo files.
DeltaFile
+30-14llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
+5-3llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
+35-172 files

LLVM/project 453d7b6llvm/lib/CodeGen/AsmPrinter DwarfDebug.cpp, llvm/lib/MC MCSymbol.cpp

add comments
DeltaFile
+6-0llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+4-0llvm/lib/MC/MCSymbol.cpp
+10-02 files

LLVM/project 9436a86llvm/lib/MC MCSymbol.cpp

fix
DeltaFile
+4-9llvm/lib/MC/MCSymbol.cpp
+4-91 files

LLVM/project f01e48bllvm/include/llvm/MC MCSymbol.h, llvm/lib/CodeGen/AsmPrinter DwarfDebug.cpp

[dwarf] make dwarf fission compatible with RISCV relaxations 1/2

Currently, -gsplit-dwarf and -mrelax are incompatible options in
Clang. The issue is that .dwo files should not contain any
relocations, as they are not processed by the linker. However,
relaxable code emits relocations in DWARF for debug ranges that
reside in the .dwo file when DWARF fission is enabled.

This patch makes DWARF fission compatible with RISC-V relaxations.
It uses the StartxEndx DWARF forms in .debug_rnglists.dwo, which
allow referencing addresses from .debug_addr instead of using
absolute addresses. This approach eliminates relocations from .dwo
files.
DeltaFile
+187-0llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
+33-25llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+18-3llvm/lib/MC/MCSymbol.cpp
+2-0llvm/include/llvm/MC/MCSymbol.h
+240-284 files

LLVM/project cf837e2lldb/include/lldb/Utility NonNullSharedPtr.h

[lldb] Add assert to NonNullSharedPtr move constructor (#168979)

As suggested by Augusto, add an assert to the NonNullSharedPtr move
constructor.
DeltaFile
+6-4lldb/include/lldb/Utility/NonNullSharedPtr.h
+6-41 files

LLVM/project fb63260llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx/ir-instruction mulwev_od.ll

including v2i128
DeltaFile
+58-870llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mulwev_od.ll
+13-4llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+71-8742 files

LLVM/project 956f882llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lsx/ir-instruction mulwev_od.ll

deal with lsx i128
DeltaFile
+96-356llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mulwev_od.ll
+34-22llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+130-3782 files

LLVM/project 264d57allvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchLSXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction mulwev_od.ll

[LoongArch] Perform DAG combine for MUL to generate `[x]vmulw{ev/od}`
DeltaFile
+124-2,144llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mulwev_od.ll
+32-154llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mulwev_od.ll
+112-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+50-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+41-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+359-2,2985 files

LLVM/project decdcc9llvm/test/CodeGen/LoongArch/lasx/ir-instruction mulwev_od.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction mulwev_od.ll

using poison
DeltaFile
+64-64llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mulwev_od.ll
+48-48llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mulwev_od.ll
+112-1122 files

LLVM/project cbf5cc5llvm/test/CodeGen/LoongArch/lasx/ir-instruction mulwev_od.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction mulwev_od.ll

[LoongArch][NFC] Pre-commit tests for `[x]vmulw{ev/od}` instructions
DeltaFile
+3,475-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mulwev_od.ll
+1,145-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mulwev_od.ll
+4,620-02 files