[InferAddressSpaces] Treat addrspacecast constant expressions from flat as roots (#241118)
The pass uses the pointer operand of an `addrspacecast` instruction as a
root, but it misses the same cast folded into a constant expression
unless the constant is itself in a root position, such as a load or
store pointer. So a round trip from LDS through flat back to LDS is not
folded when it is, for example, a call operand.
This PR treats such casts in any operand as roots, including nested
ones. Other constant expressions only produce another flat pointer.
Fixes LCOMPILER-3204.
This PR was assisted by AI but I reviewed all the changes.
[clang] Add -fpch-base-dir-is-cwd (#239791)
Serialize PCH input paths relative to the current working directory, so
a build tree can be moved while preserving its relative layout. Reuse
the existing relocatable AST prefix stripping without storing a reader
base directory or enabling sysroot-based re-rooting.
This is the PCH equivalent of -fmodule-file-home-is-cwd.
Assisted-by: Muse
[lldb] Fix struct return values on SysV arm64 (#242068)
d963a7c39891 inverted the byte size check in
LoadValueFromConsecutiveGPRRegisters, so the function failed for every
type with a known size. LLDB never read struct values from registers on
non-Apple AArch64 targets.
This fixes TestReturnValueSynthetic on AArch64 Linux and removes the
AArch64 parts of the llvm.org/pr44132 and llvm.org/pr44161 workarounds.
assisted by claude
[github] Remove stale CODEOWNERS entries (#241029)
If you navigate to
[.github/CODEOWNERS](http://github.com/llvm/llvm-project/blob/main/.github/CODEOWNERS),
GitHub reports invalid owners in the rules for MLIR Sparsifier, MLIR
Python bindings, and BOLT.
I assume this happened because these owners previously had commit
access, but it lapsed due to the removal of commit rights that haven't
been exercised in the last year. (See
[AdminTasks.md](https://llvm.org/docs/AdminTasks.html))
I confirmed that each owners entry is at least over a year old, and is
therefore probably stale.
I decided to leave a comment of "Emeritus owner" for each owner. The
idea is that, if one ever wants to reclaim commit access rights, you can
just do that, it just requires filing a ticket for a github admin, and
regaining ownership is just a matter of moving your name out of the
comment section.
Fix CODEOWNERS error, remove Lanza from ClangIR owners (#207294)
The github project reports:
Unknown owner on line 39: make sure <name> exists and has write access
to the repository
I assume Nathan's commit access lapsed and he has the `triage` role now.
I added a comment saying he is an emeritus owner. This is reversible,
and I assume if he needs or wants write access, we can revisit this in
the future.
[clang][deps][test] Migrate more module graph tests to scan-deps-filter, NFC (#242019)
Pipe these tests' output through `scan-deps-filter` so they only assert
on the fields they check. Unrelated fields that are added or reordered
no longer break them.
[VPlan] Precommit test updates for #237684 (#241476)
Pulling out for
https://github.com/llvm/llvm-project/pull/237684/changes#r4537003281
from that PR.
This just makes us check globals so we can assert for profile data, and
then also adds profile metadata to the function so we can see the
addition to the select afterwards.
[CIR] Implement 'ctor/dtor returns this' (#240954)
This is a blocking feature for a few of the ABIs, plus is a command line
option for existing itanium ABIs. This patch fills in the handful of
"NYI" spots.
The real 'interesting' part of this is the tests. This was well-tested
in the CodeGenCXX classic codegen test, so this patch enables those of
which can be enabled trivially (or with minor SSA name removals).
SOME of those run-lines are not yet converted because they have
unsupported platforms in their RUN lines, but we intend to convert those
eventually.
CodeGen: Add missing '...' end markers to MIR tests
The MIR parser is overly permissive and accepts a '---' start of
function document after a function ends without the end
marker. update_mir_test_checks will silently stop emitting checks
after the last properly terminated function. Add the missing markers
and fix tests that were missing checks. Found and corrected by slop
script.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[SPIR-V] Fix scalar to equal-width vector storage casts (#241032)
The HLSL any api recently switch from a target intrinsic to using a
vector reduce intrinsic. This made the intrinsic subject to instcombine
scalar representations of a vector.
Specifically it is possible now to produce an i64 load from <4 x i16>
storage. Pointer-cast legalization then incorrectly changed the
pointer’s element type, generating invalid OpAccessChain instructions.
The fix was to preserve the vector storage type and bitcast values for
equal-width scalar loads and stores.
IR: Add LoadInst::isAtomic and StoreInst::isAtomic
isSimple and the many callers of isAtomic on a LoadInst or StoreInst
went through the out of line opcode switch in Instruction::isAtomic.
Shadow it with an inline ordering check, like isVolatile.
CTMark instructions:u, geomean: O3 -0.05%, ThinLTO -0.08%
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
IR: Check willreturn before volatility in Instruction::willReturn
Most calls are not volatile intrinsics, so check the attribute first
and skip the intrinsic volatility switch for calls without
willreturn. Found while trying to squeeze a little more out of
attributor-light, but it shows a tiny improvement with the current
defaults.
CTMark instructions:u, geomean: O3 -0.04%, ThinLTO -0.04%
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AArch64][COST]Cost non-pow2 i1 and/or/xor reductions
A non-pow2 i1 vector is padded with the identity and reduced as the
promoted integer vector; the i1 umaxv/uminv lowering does not apply.
Zero identity costs one masking and, all-ones costs lane inserts.
Required to support non-power-of-2 vectorization in SLP
Assisted-by: Cursor
Pull-request: https://github.com/llvm/llvm-project/pull/238380
Reviewers: davemgreen, david-arm, huntergr-arm, paulwalker-arm, sdesmalen-arm
Reviewed-by: paulwalker-arm
ARM: Use inline register class syntax in MIR tests
Delete the registers section when unnecessary.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[Offload][Omp] Manage memory through liboffload APIs (#241895)
Remove the liboffload allocation helpers and use `olMemAlloc` and
`olMemFree`.
For allocations, this means the `HstPtr` is no longer passed and can be
dropped from the internal interfaces (many of the mechanical changes in
this PR are because of this).
For free, the kind is no longer passed and so the wrong pointer kind
errors can longer be detected.
Also, because liboffload checks on its internal structures before
calling the plugins, double_free and free_host pointers errors return
different errors (so tests are adjusted).
After this, parts of the support of `OFFLOAD_TRACK_ALLOCATION_TRACES`
are effectively dead and could be removed in a later PR.
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