LLVM/project de3633fllvm/test/MC/Disassembler/AMDGPU gfx1011_dlops.txt gfx12_dasm_vop3c.txt

AMDGPU: Migrate disassembler tests to use subarch triples
DeltaFile
+9-9llvm/test/MC/Disassembler/AMDGPU/gfx1011_dlops.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp8.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx_dpp16.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
+49-49286 files not shown
+609-609292 files

LLVM/project 6014b01llvm/test/CodeGen/AMDGPU llvm.amdgcn.raw.atomic.buffer.load.ll llvm.amdgcn.raw.ptr.atomic.buffer.load.ll

[NFC][AMDGPU] Remove reundant run lines from two test cases
DeltaFile
+0-44llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
+0-44llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
+0-882 files

LLVM/project e22e9e1llvm/test/MC/AMDGPU gfx7_unsupported.s gfx8_unsupported.s

AMDGPU: Migrate assembler tests to subarch triples with error changes

Since these cases dropped the -mcpu argument, the error messages changed
to use the canonical name.
DeltaFile
+864-864llvm/test/MC/AMDGPU/gfx7_unsupported.s
+614-614llvm/test/MC/AMDGPU/gfx8_unsupported.s
+223-223llvm/test/MC/AMDGPU/literals.s
+135-135llvm/test/MC/AMDGPU/vopc-vi.s
+28-28llvm/test/MC/AMDGPU/flat-scratch-st-mode.s
+24-24llvm/test/MC/AMDGPU/add-sub-no-carry.s
+1,888-1,8884 files not shown
+1,938-1,93810 files

LLVM/project 9003e17llvm/test/Transforms/LowerMatrixIntrinsics double-transpose-asserts-shape.ll

undef -> zeroinitializer
DeltaFile
+44-44llvm/test/Transforms/LowerMatrixIntrinsics/double-transpose-asserts-shape.ll
+44-441 files

LLVM/project 217aba7llvm/test/MC/AMDGPU vcc_tuples.s smem.s

AMDGPU: Mostly migrate mc tests to subarch triples

Migrate cases by script that don't fail
DeltaFile
+17-17llvm/test/MC/AMDGPU/vcc_tuples.s
+14-14llvm/test/MC/AMDGPU/smem.s
+14-14llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
+12-12llvm/test/MC/AMDGPU/ds_swizzle.s
+12-12llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+10-10llvm/test/MC/AMDGPU/sopk.s
+79-79719 files not shown
+1,693-1,693725 files

LLVM/project 3beb48bllvm/lib/Target/AMDGPU SIPreAllocateWWMRegs.cpp, llvm/test/CodeGen/AMDGPU si-pre-allocate-wwm-regs.mir

[AMDGPU] Fix SIPreAllocateWWMRegs to reserve AV-class WWM defs (#211560)

isVGPR() rejects the unified VGPR+AGPR register class used on gfx90A+,
so strict-WWM defs allocated to an AV-class register were left out of
WWMReservedRegs and could be clobbered by the post-WWM allocator
DeltaFile
+39-0llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
+1-1llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+40-12 files

LLVM/project 8e47346llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU minimumnum.ll maximumnum.ll

[AMDGPU] Fix v32f16 FMINIMUMNUM/FMAXIMUMNUM lowering in non-IEEE mode (#207896)

v32f16 was marked Custom but omitted from the handler split-list, so it
fell through to selection and failed with "Cannot select"

The dead v16bf16 branch (never marked Custom) is dropped in the same
change
DeltaFile
+561-2llvm/test/CodeGen/AMDGPU/minimumnum.ll
+561-2llvm/test/CodeGen/AMDGPU/maximumnum.ll
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1,123-53 files

LLVM/project badfb18llvm/lib/Target/AMDGPU AMDGPU.td

[NFC][AMDGPU] Fix redundant target feature datacachelinesize128
DeltaFile
+1-2llvm/lib/Target/AMDGPU/AMDGPU.td
+1-21 files

LLVM/project 8543a5bllvm/test/MC/AMDGPU amdgcn-target-directive-subarch-cpu-field.s hsa-diag-v4.s

AMDGPU: Use llvm-mc -triple= arguments instead of space separator (#211510)

-triple=amdgcn... is the dominant form over -triple amdgcn. Convert
the outliers for easier subarch triple conversion.
DeltaFile
+9-9llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
+8-8llvm/test/MC/AMDGPU/hsa-diag-v4.s
+7-7llvm/test/MC/AMDGPU/isa-version-unk.s
+7-7llvm/test/MC/AMDGPU/isa-version-hsa.s
+7-7llvm/test/MC/AMDGPU/isa-version-pal.s
+5-5llvm/test/MC/AMDGPU/elf-header-cov.s
+43-4343 files not shown
+121-12149 files

LLVM/project 6a12e18llvm/test/CodeGen/MIR/AMDGPU machine-metadata-error.mir syncscopes.mir

AMDGPU: Migrate misc. tests to subarch triples
DeltaFile
+1-1llvm/test/CodeGen/MIR/AMDGPU/machine-metadata-error.mir
+0-1llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
+0-1llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
+1-33 files

LLVM/project 4806135clang/lib/Driver/ToolChains AMDGPU.cpp, clang/test/Driver rocm-detect-libdir.hip

[HIP][Driver] Use alternative `/lib64` if `/lib` doesn't exist

On non-standard ROCm installations, `libamdhsa64.so` may be under `/lib64`
instead of `/lib`. To accomodate for these, if `/lib` does not exists
and `/lib64` does, use the later.

If both exist `/lib` is preferred.

By default we conservatively use `/lib`.
DeltaFile
+26-0clang/test/Driver/rocm-detect-libdir.hip
+5-0clang/lib/Driver/ToolChains/AMDGPU.cpp
+1-0clang/test/Driver/Inputs/rocm/lib/libamdhip64.so
+32-03 files

LLVM/project e2a39f5llvm/test/CodeGen/AMDGPU llvm.amdgcn.raw.ptr.buffer.load.ll llvm.amdgcn.wmma.gfx1250.w32.ll

[AMDGPU] Use global_prefetch_b8 for GFX1250 unclaused VMEM workaround (#210874)

Replace GLOBAL_WB with GLOBAL_PREFETCH_B8
DeltaFile
+962-40llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
+250-250llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+232-232llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+196-196llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+183-183llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+174-174llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+1,997-1,075194 files not shown
+7,196-6,270200 files

LLVM/project a3e2f70llvm/test/CodeGen/AMDGPU module-flag-xnack.ll module-flag-xnack-sramecc-combined.ll, llvm/test/CodeGen/AMDGPU/GlobalISel combine-ctlz-cttz-zero-poison-disable-rule.ll

AMDGPU: Convert new tests to subarch triples

These are tests added after the recent batch migration to new
triples.
DeltaFile
+10-10llvm/test/CodeGen/AMDGPU/module-flag-xnack.ll
+3-3llvm/test/CodeGen/AMDGPU/module-flag-xnack-sramecc-combined.ll
+2-2llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma-fake16.mir
+2-2llvm/test/CodeGen/AMDGPU/v_swap_b16.mir
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison-disable-rule.ll
+1-1llvm/test/Transforms/Inline/AMDGPU/inline-max-bb-debug.ll
+19-196 files not shown
+25-2512 files

LLVM/project d2f1642llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU anyext-s16-to-s64.ll

AMDGPU/GlobalISel: RegBankLegalize G_ANYEXT s16 to s64 (#205470)

Add rules for G_ANYEXT s16->s64 matching SEXT and ZEXT s16->s64.
DeltaFile
+69-0llvm/test/CodeGen/AMDGPU/anyext-s16-to-s64.ll
+38-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+109-03 files

LLVM/project ed917bcllvm/test/MachineVerifier/AMDGPU dpp-imm-src1.mir dpp-sgpr-src1.mir

AMDGPU: Migrate more machine verifier tests to subarch triples
DeltaFile
+3-3llvm/test/MachineVerifier/AMDGPU/dpp-imm-src1.mir
+3-3llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir
+1-1llvm/test/MachineVerifier/AMDGPU/verifier-sdwa-selection.mir
+1-1llvm/test/MachineVerifier/AMDGPU/verify-av-mov-imm-pseudo.mir
+1-1llvm/test/MachineVerifier/AMDGPU/verify-ds-vdata-vdst-both-agpr-or-vgpr.mir
+1-1llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
+10-1020 files not shown
+30-3026 files

LLVM/project d6f0e6bllvm/include/llvm/Frontend/OpenMP OMP.h, llvm/unittests/Frontend EnumSetTest.cpp

Fix out of bounds word access in iterator
DeltaFile
+77-0llvm/unittests/Frontend/EnumSetTest.cpp
+4-4llvm/include/llvm/Frontend/OpenMP/OMP.h
+81-42 files

LLVM/project 4d777c1mlir/include/mlir/IR Region.h, mlir/include/mlir/Interfaces LoopLikeInterface.td

[mlir] Handle null region in LoopLikeOpInterface::isDefinedOutsideOfLoop (#204521)

Fixes #203860 

In LoopLikeOpInterface::isDefinedOutsideOfLoop default implementation,
value.getParentRegion() can return null during signature conversion
rollbacks when blocks/ops are unlinked. Check for null region to avoid a
segmentation fault.

Also, add a regression test for convert-func-to-llvm with
index-bitwidth=32 on functions with affine.for loops.
DeltaFile
+15-0mlir/test/Conversion/FuncToLLVM/func-to-llvm.mlir
+2-1mlir/include/mlir/Interfaces/LoopLikeInterface.td
+3-0mlir/include/mlir/IR/Region.h
+20-13 files

LLVM/project 6690cd6clang/docs HIPSupport.md

[DOC] Update SPIR-V Support on HIPAMD ToolChain (#211542)

SPIR-V backend now is the default path.
DeltaFile
+9-4clang/docs/HIPSupport.md
+9-41 files

LLVM/project 9b3cc3cllvm/include/llvm/IR ConstantRange.h, llvm/lib/Analysis LazyValueInfo.cpp ValueTracking.cpp

[LVI] Infer ranges from mul nuw square conditions (#173127)

A non-poison comparison involving `mul nuw X, X` implies that the
multiplication does not overflow.  This bounds X by:

    X <= floor(sqrt(2^bitwidth(X) - 1)) (e.g., i16: X <= 255)

An unsigned constant comparison can tighten the bound, e.g.,
`X * X <= 120` implies `X <= 10`.

Fixes https://github.com/llvm/llvm-project/issues/122412
DeltaFile
+114-0llvm/test/Transforms/CorrelatedValuePropagation/mul-nuw-square.ll
+30-0llvm/lib/Analysis/LazyValueInfo.cpp
+10-0llvm/lib/IR/ConstantRange.cpp
+8-0llvm/lib/Analysis/ValueTracking.cpp
+5-0llvm/unittests/IR/ConstantRangeTest.cpp
+3-0llvm/include/llvm/IR/ConstantRange.h
+170-06 files

LLVM/project 2697ad1llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize BUILD.gn

[gn build] Port e04cf35fc64c (#211576)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
+1-01 files

LLVM/project 5023ca1llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp AMDGPUMemoryUtils.h

[AMDGPU] Consult AA for non-atomic clobbers in isReallyAClobber

isReallyAClobber (used by AMDGPUAnnotateUniformValues to decide whether a uniform
load may be marked !amdgpu.noclobber) only queried alias analysis for atomics;
every other memory-writing MemoryDef (plain stores, memory intrinsics, calls)
fell through to an unconditional "return true", declaring it a clobber without
asking AA.

As a result a uniform, read-only load is denied !amdgpu.noclobber whenever
MemorySSA's clobber walk surfaces such a def through a loop MemoryPhi, even when
AA can trivially prove NoAlias (e.g. an LDS/addrspace(3) write vs a
global/addrspace(1) load). Without noclobber the load is selected as a vector
GLOBAL_LOAD instead of a scalar s_load, adding a v_readfirstlane round-trip when
the value feeds a scalar operand.

Query AA generally via getModRefInfo for the fall-through case, while keeping the
fence/barrier whitelist and the pointer-level atomic special case (getModRefInfo
over-reports Mod for an atomic's ordering effects). The load's MemoryLocation is
threaded through so addressing/size precision applies.
DeltaFile
+15-6llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+5-4llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+20-102 files

LLVM/project 5fa154fllvm/test/CodeGen/AMDGPU llvm.amdgcn.raw.atomic.buffer.load.ll llvm.amdgcn.raw.ptr.atomic.buffer.load.ll

[NFC][AMDGPU] Remove reundant run lines from two test cases
DeltaFile
+0-23llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
+0-23llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
+0-462 files

LLVM/project 97a5889clang/docs ReleaseNotes.md, clang/lib/Sema SemaAccess.cpp

[Clang][Sema] Don't delay the access check when computing implicit deletion (#210254)

Sema::isMemberAccessibleForDeletion treats AR_delayed as unreachable,
but CheckAccess returns AR_delayed whenever it runs inside an enclosing
delayed-diagnostics scope. That happens when deletion checking runs
synchronously while parsing a later declaration -- e.g. while explaining
why a defaulted operator<=> is deleted for an expression in that
declaration's initializer. The caller cannot consume a delayed
diagnostic, so letting CheckAccess delay always hits
llvm_unreachable("cannot delay =delete computation") and crashes.

Force an immediate answer by wrapping the CheckAccess call in
DelayedDiagnostics.pushUndelayed()/popUndelayed() via llvm::scope_exit,
mirroring the existing Sema::CheckEnableIf pattern in SemaOverload.cpp.

Fixes https://github.com/llvm/llvm-project/issues/210692

Co-authored-by: Claude-Sonnet
DeltaFile
+14-0clang/test/SemaCXX/cxx20-default-compare.cpp
+10-0clang/lib/Sema/SemaAccess.cpp
+4-0clang/docs/ReleaseNotes.md
+28-03 files

LLVM/project 9d38605llvm/lib/Target/AArch64 AArch64Subtarget.h, llvm/test/CodeGen/AArch64 aarch64-no-mov-spill-chain.ll ragreedy-local-interval-cost.ll

Revert "[AArch64] Enable Spillage Copy Elimination by default (#186093)"

This reverts commit cf30e4b5c2d55e217ade2483c4672f2488da48df.
DeltaFile
+0-403llvm/test/CodeGen/AArch64/aarch64-no-mov-spill-chain.ll
+31-21llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
+0-1llvm/lib/Target/AArch64/AArch64Subtarget.h
+31-4253 files

LLVM/project 8b690a0mlir/test/Conversion/VectorToLLVM vector-to-llvm-interface.mlir, mlir/test/Dialect/Vector vector-mem-transforms.mlir invalid.mlir

[mlir][vector] Make CompressstoreOp + ExpandloadOp support scalable vectors (#210288)

Extends `vector.compressstore` + `vector.expandload` to support scalable
vectors and updates relevant tests.

An e2e test for `vector.compressstore` is added. For
`vector.expandload`, we need to wait for QEMU support:
https://github.com/llvm/llvm-project/issues/210942.
DeltaFile
+214-0mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/compress.mlir
+41-12mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
+50-0mlir/test/Dialect/Vector/vector-mem-transforms.mlir
+14-15mlir/test/Dialect/Vector/invalid.mlir
+24-0mlir/test/Dialect/Vector/vector-dropleadunitdim-transforms.mlir
+20-0mlir/test/Dialect/Vector/ops.mlir
+363-272 files not shown
+371-338 files

LLVM/project bb22aa8llvm/lib/IR Constants.cpp

[IR] Slightly optimize getElementAsInteger() (#211550)

This regressed with the introduction of the byte type, because
getElementPointer() calls getElementByteSize() calls
getPrimitiveSizeInBits(), but the switch used getScalarTypeInBits(),
which means we need to do two separate calls for the element size. Use
getElementByteSize() in both places so these can be CSEd.
DeltaFile
+10-10llvm/lib/IR/Constants.cpp
+10-101 files

LLVM/project dcbf875mlir/lib/Dialect/SparseTensor/Transforms SparseVectorization.cpp, mlir/test/Dialect/SparseTensor sparse_vector_coo.mlir

[mlir][sparse] Avoid vectorizing non-contiguous COO coordinate loads (#211004)

`SparseVectorization` assumes direct loop accesses (`a[lo:hi]`) are
contiguous and vectorizes them with `vector.maskedload/maskedstore`.
This is false for `sparse_tensor.coordinates` of a level inside a
trailing AoS COO region, whose buffer is interleaved with other levels:
a silent miscompile.

The true stride is already known from the tensor's encoding, even though
the memref type is still dynamic at this point. Use it to fall back to a
scalar loop when the stride is provably non-unit.

---------

Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
DeltaFile
+105-0mlir/test/Dialect/SparseTensor/sparse_vector_coo.mlir
+50-0mlir/lib/Dialect/SparseTensor/Transforms/SparseVectorization.cpp
+155-02 files

LLVM/project 63a847allvm/test/Transforms/LoopVectorize/AArch64 interleave-with-gaps.ll reduction-recurrence-costs-sve.ll

Revert "[LV] Allow scalable epilogue VFs matching the MainLoop VF (#208686)"

This reverts commit 308393ede14cc8533d1be122b5df88bf9ba4173b.
DeltaFile
+53-61llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
+38-38llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
+27-27llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
+17-24llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
+19-14llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
+13-13llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
+167-1772 files not shown
+185-1928 files

LLVM/project d2823bfclang/include/clang/StaticAnalyzer/Core/PathSensitive SMTConv.h, clang/test/Analysis/z3 z3-crosscheck.c

[analyzer][z3] Fix crash in Z3 SMTConv when casting atomic int (#211489)

CPP-7675

(cherry picked from commit f953ed4ec657bef2b92b798faa2872b75f1f4e81)
DeltaFile
+8-0clang/test/Analysis/z3/z3-crosscheck.c
+2-2clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConv.h
+10-22 files

LLVM/project d944c39llvm/lib/Target/RISCV RISCVISelDAGToDAG.cpp, llvm/test/CodeGen/RISCV lpad-setjmp-regmask.ll

[RISCV] Preserve call-preserved reg mask for LPAD-aligned calls (#210868)

RISCVISelDAGToDAG's lowering of RISCVISD::LPAD_CALL / LPAD_CALL_INDIRECT
to PseudoCALLLpadAlign / PseudoCALLIndirectLpadAlign (introduced in
#177515) only copied the callee, lpad label, chain, and glue operands,
dropping the argument-register and register-mask operands in between.

Without the register-mask operand, the register allocator treats these
calls as clobbering nothing but ra, so values live across the call are
not spilled/reloaded even though the callee is free to clobber
caller-saved registers. This caused a miscompile where a pointer held
live across a call to getcontext() (a returns_twice function) was
corrupted after the call returned, leading to a SIGSEGV in
llvm-test-suite's siod test.

Fix the operand copy to include the argument-register and register-mask
operands, matching the pseudo-instruction operands of a regular
PseudoCALL/PseudoCALLIndirect.


    [2 lines not shown]
DeltaFile
+35-0llvm/test/CodeGen/RISCV/lpad-setjmp-regmask.ll
+13-3llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+48-32 files