LLVM/project 6b37416 — llvm/lib/Transforms/IPO AttributorAttributes.cpp, llvm/test/Transforms/Attributor align.ll noundef-return-poison-attrs.ll

Attributor: Deduce noundef returns if poison-generating attributes hold

Instead of giving up on noundef for returns with poison-generating
attributes, check that the attributes are assumed to hold for all
returned values. This uses the Attributor's own deductions for the
returned values (AANonNull, AAAlign, AAValueConstantRange and
AANoFPClass), so e.g. a range only known from a callee is enough.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+207-15llvm/test/Transforms/Attributor/noundef-return-poison-attrs.ll
+61-9llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+1-1llvm/test/Transforms/Attributor/align.ll
+269-253 files

LLVM/project c9d8023 — llvm/include/llvm/IR Attributes.h, llvm/lib/IR Attributes.cpp Instruction.cpp

Attributor: Don't infer noundef returns with poison-generating attributes (#231796)

Returning a value that violates an existing return attribute results
in poison. AANoUndef did not account for this and could mark such
returns noundef. Give up on returns with poison-generating attributes.

Unlike FunctionAttrs, this does not try to prove that the attributes
hold for the returned values. This loses 2 of 3 noundef returns that
would have been proven over CTMark with -attributor-enable=full, and
no call site attributes. In the future it should check if they can be
preserved for parity with functionattrs.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+48-0llvm/test/Transforms/Attributor/noundef-return-poison-attrs.ll
+15-0llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+4-10llvm/lib/IR/Instruction.cpp
+9-0llvm/lib/IR/Attributes.cpp
+4-0llvm/include/llvm/IR/Attributes.h
+1-1llvm/test/Transforms/Attributor/align.ll
+81-116 files

LLVM/project 2909199 — llvm/lib/Passes CodeGenPassBuilder.cpp, llvm/test/CodeGen/RISCV O3-newpm-pipeline.ll O0-newpm-pipeline.ll

[Passes] Wire up CFIFixup into NewPM (#237484)

Not sure how this got missed. This has been in TargetPassConfig for
quite a while, and this patch mirrors it in the base CGPB.
DeltaFile
+4-0llvm/lib/Passes/CodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+1-0llvm/test/CodeGen/RISCV/O0-newpm-pipeline.ll
+6-03 files

LLVM/project 38f8b88 — llvm/lib/Target/AArch64 AArch64AsmPrinter.cpp, llvm/lib/Target/PowerPC PPCAsmPrinter.cpp

[AArch64][PowerPC][RISCV] Ignore debug instructions when trimming stackmap shadows (#219756)

Debug instructions do not emit code and therefore must not consume
stackmap
shadow bytes.

The AArch64, PowerPC, and RISC-V `LowerSTACKMAP` implementations scan
subsequent fixed-width instructions to determine how many NOP bytes are
still
required. Previously, `DBG_VALUE` stopped this scan, while other debug
instructions such as `DBG_LABEL` were incorrectly counted as encoded
instructions. This could either inhibit shadow optimization or underfill
the
requested shadow.

Skip all debug instructions without decrementing the remaining shadow
size.
Add `DBG_LABEL` and `DBG_VALUE` regression coverage for all three
targets.

    [4 lines not shown]
DeltaFile
+80-0llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll
+41-0llvm/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll
+38-0llvm/test/CodeGen/AArch64/arm64-stackmap-nops.ll
+4-1llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+4-1llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+4-1llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+171-36 files

LLVM/project c16e63d — llvm/include/llvm/IR RuntimeLibcallsImpl.td

RuntimeLibcalls: Describe vector FuncArgTypes by element type and count

Define the vector libcall argument types from an element type and
count. Derive the matching integer and mask vector types from them
instead of spelling each one out.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+18-12llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+18-121 files

LLVM/project 713f497 — llvm/test/Instrumentation/MemorySanitizer vector-extract-last-active.ll

[MSan][Test] Add baseline test for llvm.experimental.vector.extract.last.active (#237415)

This is a baseline test before patching
https://github.com/llvm/llvm-project/pull/233552.

This test shows vector.extract.last.active is being handled strictly.

Assisted-by: Gemini
DeltaFile
+281-0llvm/test/Instrumentation/MemorySanitizer/vector-extract-last-active.ll
+281-01 files

LLVM/project eda03ab — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Merge branch 'users/void/asm-rm-4-regallocfast-fold' into users/void/asm-rm-5-prefer-reg
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project d4cc7c6 — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Merge branch 'users/void/asm-rm-3-direct-mem-output-error' into users/void/asm-rm-4-regallocfast-fold
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project 6494293 — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Merge branch 'users/void/asm-rm-2f-peephole-asm-load-fold' into users/void/asm-rm-3-direct-mem-output-error
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project 52e3d4f — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Merge branch 'users/void/asm-rm-2e-fold-asm-memoperands' into users/void/asm-rm-2f-peephole-asm-load-fold
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project 7c8110e — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Merge branch 'users/void/asm-rm-2d-prefer-spilling-foldable' into users/void/asm-rm-2e-fold-asm-memoperands
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project 32b963a — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Merge branch 'users/void/asm-rm-2c-fold-subreg-offset' into users/void/asm-rm-2d-prefer-spilling-foldable
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project 51e4dff — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Merge branch 'users/void/asm-rm-2-fold-tied-operands' into users/void/asm-rm-2b-fold-all-reg-operands
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project 220b4f2 — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Merge branch 'users/void/asm-rm-2b-fold-all-reg-operands' into users/void/asm-rm-2c-fold-subreg-offset
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project 650925d — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Merge branch 'users/void/mir-inline-asm-func-kind' into users/void/asm-rm-2-fold-tied-operands
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project 4ea0568 — llvm/test/DebugInfo/Generic debug-label-inline.ll PR20038.ll, llvm/test/Linker subprogram-linkonce-weak.ll

[SPARC] Remove XFAILs fixed by not filling the delay slots at -O0 (#237186)

The tests now pass with the change introduced in 6a9fc6603b3f.
DeltaFile
+0-3llvm/test/Linker/subprogram-linkonce-weak.ll
+0-3llvm/test/DebugInfo/Generic/debug-label-inline.ll
+0-3llvm/test/DebugInfo/Generic/PR20038.ll
+0-93 files

LLVM/project 0896198 — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Remove unneeded -global-isel=0
DeltaFile
+3-3llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+3-31 files

LLVM/project 0bd1402 — llvm/lib/Target/NVPTX NVPTXISelLowering.cpp NVPTXInstrInfo.td, llvm/test/CodeGen/NVPTX cttz.ll ctlz.ll

[NVPTX] Use target nodes for clz.b64 and popc.b64 (#236435)

Since #130668, 64-bit ctlz and ctpop are lowered to an i32 ctlz/ctpop of
the i64 operand. DAG combines assume the result is as wide as the
operand, so e.g. `__builtin_clzll(x | 1) >> 5` gets folded to 0, and
some compares of a 64-bit cttz hit an assertion. Use NVPTX-specific
nodes for clz.b64 and popc.b64 instead.

Fixes #235271.

Assisted-by: Claude Code (Claude Opus 5.5)
DeltaFile
+46-0llvm/test/CodeGen/NVPTX/ctlz.ll
+12-4llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+12-0llvm/test/CodeGen/NVPTX/cttz.ll
+5-2llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+75-64 files

LLVM/project 4679872 — llvm/test/CodeGen/MIR/X86 inline-asm-func-kind.ll

Output null filetype instead of piping to /dev/null

Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
DeltaFile
+1-1llvm/test/CodeGen/MIR/X86/inline-asm-func-kind.ll
+1-11 files

LLVM/project 171a9e9 — clang/lib/Driver/ToolChains Darwin.cpp, clang/test/Driver darwin-static-lib-universal.c sysroot.c

clang: Do not pass an empty -syslibroot for --sysroot= on Darwin (#229421)

-isysroot and DEFAULT_SYSROOT, but it checked only for the presence
of the option. An empty --sysroot= then produced -syslibroot "",
where previously it fell through to -isysroot. An empty --sysroot= is
the usual way to defeat DEFAULT_SYSROOT, so treat it as absent.

Use this to fix the darwin-static-lib tests when clang is built with
DEFAULT_SYSROOT or CLANG_USE_XCSELECT.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+11-11clang/test/Driver/darwin-static-lib.c
+12-0clang/test/Driver/sysroot.c
+2-1clang/lib/Driver/ToolChains/Darwin.cpp
+1-1clang/test/Driver/darwin-static-lib-universal.c
+26-134 files

LLVM/project 5f74906 — llvm/lib/Target/PowerPC PPCTLSDynamicCall.cpp, llvm/test/CodeGen/PowerPC O3-pipeline.ll O0-pipeline.ll

PowerPC: Remove LiveVariables run and unused LiveIntervals requirement (#235059)

PPCTLSDynamicCall has not used LiveIntervals since 3ff319c69047, but
still required the analysis. LiveIntervals requires there to be no
unreachable blocks or otherwise it asserts. These blocks were
indirectly removed by adding the extra LiveVariables run, because
LiveVariables has a declared requirement on
UnreachableMachineBasicBlockElim.

Drop the dead analysis requirements along with the LiveVariables run.
This also avoids computing LiveIntervals at -O0 for PIC. This is
still broken if the pipeliner is explicitly enabled on optnone
functions which requires a separate fix.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+54-0llvm/test/CodeGen/PowerPC/tls-dynamic-call-unreachable-block.ll
+24-0llvm/test/CodeGen/PowerPC/tls-dynamic-call-unreachable-block-optnone.ll
+2-9llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
+0-3llvm/test/CodeGen/PowerPC/O0-pipeline.ll
+0-2llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+80-145 files

LLVM/project a67dc85 — libcxx/test/extensions/gnu/hash specializations.verify.cpp

[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+1-2libcxx/test/extensions/gnu/hash/specializations.verify.cpp
+1-21 files

LLVM/project fe2bb56 — llvm/lib/IR RuntimeLibcalls.cpp, llvm/test/Transforms/Util/DeclareRuntimeLibcalls sleef-riscv.ll amdlibm.ll

RuntimeLibcalls: Use element alignment for vector libcall out pointers

The pointer arguments of the vector modf, sincos and sincospi functions
are linear pointers to the scalar element type (e.g. the l4 in
_ZGVnN4vl4l4_sincosf), not pointers to the vector type. Only the element
alignment is guaranteed, so stop declaring them with the ABI alignment
of the vector.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+12-12llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef.ll
+12-12llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef-riscv.ll
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/amdlibm.ll
+1-1llvm/lib/IR/RuntimeLibcalls.cpp
+37-375 files

LLVM/project a220202 — llvm/test/CodeGen/AMDGPU avgpr-banking.ll

Address review comments

Drop -O3, check scratch for all configs, and use named values.
DeltaFile
+175-179llvm/test/CodeGen/AMDGPU/avgpr-banking.ll
+175-1791 files

LLVM/project c46e2f7 — llvm/include/llvm/CodeGen MachineLoopUtils.h ModuloSchedule.h, llvm/lib/CodeGen MachineLoopUtils.cpp MachinePipeliner.cpp

CodeGen: Maintain the dominator tree in MachinePipeliner

LiveIntervals computes live ranges using the dominator tree, but the
modulo schedule expanders change the CFG without updating
it. Intervals computed later in the pass therefore see a tree missing
the new prolog, kernel and epilog blocks. This is latent today, but
reachability. The unregistered blocks would be incorrectly treated as
unreachable.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+64-12llvm/lib/CodeGen/ModuloSchedule.cpp
+35-12llvm/lib/CodeGen/MachinePipeliner.cpp
+15-5llvm/include/llvm/CodeGen/ModuloSchedule.h
+7-5llvm/include/llvm/CodeGen/MachineLoopUtils.h
+9-2llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
+7-1llvm/lib/CodeGen/MachineLoopUtils.cpp
+137-375 files not shown
+151-4411 files

LLVM/project b5f241e — clang/docs ReleaseNotes.md, clang/lib/CodeGen CGExprCXX.cpp CGCall.cpp

[clang][CodeGen] Fix missing terminator when a new-expression initializer starts with a loop (#230902)

Fixes #175427

`EmitCXXNewExpr` marks the point where the operator delete cleanup
becomes active with a placeholder `unreachable` and erases it once the
initializer is emitted. If the initializer starts with a loop or a
label, `EmitBlock` takes that terminator as the end of the block and
emits no fall-through branch, so erasing the placeholder leaves the
block unterminated and valid code fails with "Broken module found".

The marker only has to be an instruction that the deactivation can
insert a store before, while the rest of CodeGen assumes the current
block has no terminator until a real one is written. The placeholder is
now the `i1` load from null that the other cleanup markers already use,
so the block stays open and `EmitBlock` branches normally. The same
marker in `EmitDelegateCallArg` is switched for consistency.

LLM tools were used for this contribution. 
DeltaFile
+216-0clang/test/CodeGenCXX/new-init-stmt-expr.cpp
+3-2clang/lib/CodeGen/CGCall.cpp
+2-1clang/lib/CodeGen/CGExprCXX.cpp
+1-0clang/docs/ReleaseNotes.md
+222-34 files

LLVM/project ca385fa — llvm/lib/Target/AMDGPU GCNSchedStrategy.h GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU avgpr-banking-rigid-peak.mir avgpr-banking-bank-excess.mir

[AMDGPU] Address review comments on AVGPR banking

Keep the larger bank excess in initCandidate.

In checkScheduling, distribute the AVGPR pressure of each program point
across the banks instead of the region maximum, which can hide a rigid
ArchVGPR peak at another point.

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+57-24llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+64-0llvm/test/CodeGen/AMDGPU/avgpr-banking-bank-excess.mir
+62-0llvm/test/CodeGen/AMDGPU/avgpr-banking-rigid-peak.mir
+6-1llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+189-254 files

LLVM/project cb1276d — llvm/lib/Target/Mips MipsCodeGenPassBuilder.cpp MipsOptimizePICCall.cpp, llvm/test/CodeGen/Mips newpm-pipeline.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+417-427llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
+336-345llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+302-0llvm/test/CodeGen/Mips/newpm-pipeline.ll
+135-118llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
+128-119llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
+161-0llvm/lib/Target/Mips/MipsCodeGenPassBuilder.cpp
+1,479-1,00917 files not shown
+2,025-1,22623 files

LLVM/project 26a235a — llvm/lib/Target/Mips Mips.h MipsOptimizePICCall.cpp, llvm/test/CodeGen/Mips newpm-pipeline.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+417-427llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
+336-345llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+302-0llvm/test/CodeGen/Mips/newpm-pipeline.ll
+135-118llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
+128-119llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
+123-17llvm/lib/Target/Mips/Mips.h
+1,441-1,02617 files not shown
+1,982-1,22623 files

LLVM/project 8d3d02b — llvm/lib/Transforms/Vectorize VPlanUnroll.cpp, llvm/test/Transforms/LoopVectorize/X86 replicate-recipe-with-only-first-lane-used.ll

[VPlan] Replace first lane for single-scalars in replicateByVF. (#237472)

If DefR is a single scalar, all lanes are equal and all scalar users can
use lane 0.

This fixes a crash due when trying to match an extract from a
single-scalar.

Fixes https://github.com/llvm/llvm-project/issues/237456
DeltaFile
+174-0llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll
+6-3llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
+180-32 files