LLVM/project 3b17fa2lld/MachO ObjC.h ObjC.cpp, lld/test/MachO objc-category-merging-minimal.s objc-category-merging-swift-protocol-conformance.s

[lld-macho] Remove symbol name assumptions from category merging (#217276)

The category merger required every __objc_catlist entry to point to a
symbol named with the `__OBJC_$_CATEGORY_` or `__CATEGORY_` prefix and
hit llvm_unreachable otherwise. Such names cannot be relied upon: `ld
-r` rewrites the names of category body symbols to generated names like
`l002`, and linking its output crashes lld.

The merger also used symbol names to predict the layout of protocol
lists, which is fragile even for conventionally named inputs. The repro
https://github.com/llvm/llvm-project/pull/95124#issuecomment-4267900795
fired the "Protocol list does not match expected size" assertion.

Remove the category symbol name requirement, and drop the layout
assertion together with the SourceLanguage machinery.
DeltaFile
+394-0lld/test/MachO/objc-category-merging-swift-protocol-conformance.s
+15-72lld/MachO/ObjC.cpp
+6-0lld/test/MachO/objc-category-merging-minimal.s
+0-3lld/MachO/ObjC.h
+415-754 files

LLVM/project fb9a86cmlir/include/mlir/Dialect/LLVMIR NVVMOps.td, mlir/lib/Dialect/LLVMIR/IR NVVMDialect.cpp

[MLIR][NVVM] Add S2G and Reduce override NVVM Dialect ops (#216481)

This change adds S2G and Reduction NVVM Dialect operations with tensor
map override capability.
DeltaFile
+371-0mlir/test/Target/LLVMIR/nvvm/tma_store_reduce_override.mlir
+211-0mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+179-0mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+153-0mlir/test/Target/LLVMIR/nvvm/tma_store_override.mlir
+66-0mlir/test/Target/LLVMIR/nvvm/nvvmir-invalid/tma_store_override_invalid.mlir
+59-0mlir/test/Target/LLVMIR/nvvm/nvvmir-invalid/tma_reduce_override_invalid.mlir
+1,039-06 files

LLVM/project 6e170cebolt/lib/Target/RISCV RISCVMCPlusBuilder.cpp, bolt/test/RISCV plt-call.test

[BOLT][RISCV] Implement indirect PLT calls (#219184)

This patch implements `MCPlusBuilder::createIndirectPLTCall` for RISC-V,
enabling BOLT's `--plt=hot` and `--plt=all` optimizations for RISC-V
binaries.

The PLT call pass replaces direct calls and tail calls to PLT entries
with indirect calls through the corresponding resolved GOT slot. The
generated sequence is:

    auipc  t3, %pcrel_hi(target at GOT)
    l[dw]  t3, %pcrel_lo(.Lpcrel_hi)(t3)
    jalr   ra, t3, 0
DeltaFile
+53-0bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
+44-0bolt/test/RISCV/plt-call.test
+97-02 files

LLVM/project 2876d94llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/WebAssembly f16-intrinsics.ll

[WebAssembly] Expand v8f16 SELECT_CC (#218922)

Follow up for #213280 (read
https://github.com/llvm/llvm-project/pull/213280#discussion_r3797603654)

Mark `v8f16 SELECT_CC` for expansion so scalar comparison-based selects
lower through the existing comparison and `v128.select` patterns
DeltaFile
+32-0llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
+2-2llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+34-22 files

LLVM/project 49f7deaorc-rt/include/orc-rt/bedrock Error.h SimplePackedSerialization.h, orc-rt/include/orc-rt/support Error.h SimplePackedSerialization.h

[orc-rt] Split headers into support/ and bedrock/ layers. NFC. (#219374)

Follow-up to 8c7563a40a5b, which nested the runtime's headers under
include/orc-rt/bedrock/ and noted that library-neutral headers would
later be split back out.

The split names a layer -- who may include whom. support/ holds
vocabulary and utilities that depend on nothing else in orc-rt; bedrock/
holds the runtime components (Session, Service, the memory map, the
dylib manager, the SPS controller interfaces) and may include support/.
SPIRE will be able to include both. orc-rt-c/ gains the same layering.

Note that support/ is a layer inside the bedrock library, not a separate
one: Error.cpp and RTTI.cpp still compile into orc-rt-bedrock.

Also folded in: bedrock/sps-ci/ -> bedrock/sps/ in both include/ and
lib/; include guards derived from each header's path, as LLVM does
(ORC_RT_SUPPORT_ERROR_H); test/unit/ mirrored onto the new layout, with
cross-layer test helpers left at its root; test-target FOLDER properties

    [3 lines not shown]
DeltaFile
+0-1,194orc-rt/test/unit/SessionTest.cpp
+1,194-0orc-rt/test/unit/bedrock/SessionTest.cpp
+0-826orc-rt/include/orc-rt/bedrock/SimplePackedSerialization.h
+826-0orc-rt/include/orc-rt/support/SimplePackedSerialization.h
+0-714orc-rt/include/orc-rt/bedrock/Error.h
+714-0orc-rt/include/orc-rt/support/Error.h
+2,734-2,734236 files not shown
+16,547-16,529242 files

LLVM/project 5715274mlir/lib/Dialect/SPIRV/Transforms SPIRVConversion.cpp, mlir/test/Conversion/MemRefToSPIRV memref-to-spirv.mlir bitwidth-emulation.mlir

[mlir][SPIRV] Fix `StorageBuffer` access conversion for emulated i16 (#218693)

Follows up on commit 202ece6. In the absence of `Int16` and
`StorageBuffer16BitAccess` in the target, `i16` isn't any different from
byte & sub-byte types. As exposed by downstream smoke tests of the IREE
project, an edge case where this causes issues is a 0/1-rank memref.
Semantically:
```
memref<i16>  ->  ptr<struct<array<1 x i32>>>
```
Since the array lengths are the same in the absence of actual packing,
just the index bounds check doesn't catch this and `InBoundsAccessChain`
still gets chosen. In the end, the memref op fails to lower through the
same restriction in `MemRefToSPIRV` that the original change apparently
had to work around - only `AccessChain` is expected there.

As a more general criterion, the change just compares array the element
types and picks `AccessChain` upon mismatch.


    [6 lines not shown]
DeltaFile
+17-19mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
+20-0mlir/test/Conversion/MemRefToSPIRV/bitwidth-emulation.mlir
+6-1mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
+43-203 files

LLVM/project fe5a382llvm/lib/MC/MCParser AsmParser.cpp

[MCParser] Fix some bound checking when scanning macro body (#219367)
DeltaFile
+5-5llvm/lib/MC/MCParser/AsmParser.cpp
+5-51 files

LLVM/project 57f293fllvm/lib/Target/X86 X86InstrPredicates.td X86InstrFragments.td, llvm/test/CodeGen/X86 adox-flags.ll adox.ll

[X86] Emit adox instead of adc for overflow add (#216609)

ADOX is like ADC but with OF instead of the CF and can only be encoded
with a pair of 32 or 64 bit regs.

Basically this applies in cases where the overflow flag is being added.
DeltaFile
+273-0llvm/test/CodeGen/X86/adox.ll
+137-0llvm/test/CodeGen/X86/adox-flags.ll
+67-0llvm/lib/Target/X86/X86ISelLowering.cpp
+32-1llvm/lib/Target/X86/X86InstrArithmetic.td
+1-0llvm/lib/Target/X86/X86InstrPredicates.td
+1-0llvm/lib/Target/X86/X86InstrFragments.td
+511-16 files

LLVM/project 7dee60allvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Remove (X && Y) | (X && !Y) -> X combine. NFC

We have smaller combines that can take care of this now that we process recipes in a worklist
DeltaFile
+0-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-81 files

LLVM/project 7d9c222llvm/lib/Target/WebAssembly WebAssemblyInstrSIMD.td, llvm/test/CodeGen/WebAssembly simd-load-lane-offset.ll

[WebAssembly] Select lane stores for floating-point vectors (#219186)

This extends the existing integer vector lane-store patterns to the
equivalent floating-point vector types. The underlying WebAssembly
instructions are type-agnostic lane stores.

That being said I think something like `STORE_LANE_I32x4_A32` can be
misleading when dealing with floating-point vectors. (should there be a
rename or something ?)
DeltaFile
+90-0llvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
+19-12llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+109-122 files

LLVM/project e67a285llvm/lib/Target/WebAssembly WebAssemblyInstrSIMD.td, llvm/test/CodeGen/WebAssembly simd-offset.ll simd-load-promote-wide.ll

[WebAssembly] Fold offsets into extending SIMD loads (#219144)

I saw this TODO and realized that instead of lowering to 
```
local.get 0
i32.const 8
i32.add
v128.load64_zero 0
f64x2.promote_low_f32x4
```
We could choose 
```
local.get 0
v128.load64_zero 8
f64x2.promote_low_f32x4
```

So I used the existing WebAssembly address operand patterns when
lowering v2f32-to-v2f64 extending loads.

    [3 lines not shown]
DeltaFile
+17-31llvm/test/CodeGen/WebAssembly/simd-load-promote-wide.ll
+6-10llvm/test/CodeGen/WebAssembly/simd-offset.ll
+8-6llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+31-473 files

LLVM/project a7831dcclang-tools-extra/clang-tidy/bugprone ImplicitWideningOfMultiplicationResultCheck.cpp, clang-tools-extra/docs ReleaseNotes.md

[Clang-Tidy] Improve `bugprone-implicit-widening-of-multiplication-result`. (#214501)

Implicit integer promotions make it a bit difficult to deduce the
correct type in the following expression:
```
std::uint64_t calc_array_size(std::uint16_t width, std::uint16_t height) {
    return width * height;
}
```

Originally, Clang-Tidy suggested to use the following code:
```
return static_cast<long long>(width) * height;
```

It is fully correct according to the C++ rules, but it makes it a bit
harder to reason for people. This change adds a more readable "FixIt"
taking into account the source type and avoid intermediate
representations.

Co-authored-by: Dmitrii Kuragin <dkuragin at adobe.com>
DeltaFile
+34-8clang-tools-extra/test/clang-tidy/checkers/bugprone/implicit-widening-of-multiplication-result-short.cpp
+13-5clang-tools-extra/clang-tidy/bugprone/ImplicitWideningOfMultiplicationResultCheck.cpp
+7-1clang-tools-extra/docs/ReleaseNotes.md
+54-143 files

LLVM/project b0d94cborc-rt/include/orc-rt/bedrock IntervalSet.h ExecutorAddress.h

[orc-rt] Fix relative paths in includes. NFC. (#219340)
DeltaFile
+2-2orc-rt/include/orc-rt/bedrock/BitmaskEnum.h
+1-1orc-rt/include/orc-rt/bedrock/IntervalSet.h
+1-1orc-rt/include/orc-rt/bedrock/ExecutorAddress.h
+1-1orc-rt/include/orc-rt/bedrock/Endian.h
+5-54 files

LLVM/project 58b67abclang/lib/Driver OffloadBundler.cpp

[clang][OffloadBundler] Fix uninitialized iterator in BinaryFileHandler (#219346)

This patch initializes NextBundleInfo at the top of ReadHeader to
prevent an uninitialized iterator comparison.

ReadHeader has several early return points where it exits without
reading any bundles.  Upon an early return, NextBundleInfo never reaches
the assignment at the bottom of ReadHeader:

  NextBundleInfo = BundlesInfo.begin();

leaving NextBundleInfo default-constructed.  A subsequent call to
ReadBundleStart then attempts an invalid iterator comparison:

  if (NextBundleInfo == BundlesInfo.end())

where NextBundleInfo is still default-constructed.

This bug was discovered with tightened epoch checks in

    [2 lines not shown]
DeltaFile
+3-1clang/lib/Driver/OffloadBundler.cpp
+3-11 files

LLVM/project b0c1de2flang/lib/Parser parsing.cpp openmp-parsers.cpp, flang/lib/Semantics check-omp-structure.cpp

[flang][OpenMP] Support omx/ompx extension sentinels (#218475)

This adds support for the OpenMP 5.2 extension sentinels: !$omx, c$omx,
*$omx in fixed form and !$ompx in free form. Known directives after
these sentinels are handled just like !$omp, and unknown ones are
ignored with a warning so code using vendor extensions stays portable.
Added lit tests covering fixed form, free form, and the
ignore-with-warning behavior.

Assisted-by: Claude Opus 4.6

---------

Co-authored-by: Chandra Ghale <ghale at pe34genoa.hpc.amslabs.hpecorp.net>
Co-authored-by: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
DeltaFile
+45-0flang/test/Parser/OpenMP/sentinel-omx.f
+39-4flang/lib/Parser/openmp-parsers.cpp
+43-0flang/test/Parser/OpenMP/sentinel-ompx.f90
+34-0flang/test/Parser/OpenMP/sentinel-extension-ignored.f90
+18-7flang/lib/Parser/parsing.cpp
+17-1flang/lib/Semantics/check-omp-structure.cpp
+196-125 files not shown
+232-1611 files

LLVM/project e565c72flang/test/Lower/OpenMP metadirective-loop.f90

Improve metadirective loop tests
DeltaFile
+271-12flang/test/Lower/OpenMP/metadirective-loop.f90
+271-121 files

LLVM/project 06bfa42llvm/lib/Transforms/Scalar ScalarizeMaskedMemIntrin.cpp, llvm/utils profcheck-xfail.txt

[ScalarizeMaskedMemIntrin][ProfCheck] Correctly annotate branch weights (part 2) (#219286)

https://github.com/llvm/llvm-project/pull/218753 broke LLVM CI because
it added a new test in `ScalarizeMaskedMemIntrin` that was not opted out
of during profcheck. Profcheck failed because this pass creates new
branches that did not attach branch weight metadata. We don't have any
information on the distribution of masks at runtime, so we have to mark
branch weights as explicitly unknown.

This basically extends https://github.com/llvm/llvm-project/pull/181568,
Aiden am I missing something for why you didn't add the branch weight
metadata for all branch creation before?

Tested the `ScalarizeMaskedMemIntrin` tests with profcheck locally and
they all pass.
DeltaFile
+35-7llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
+0-7llvm/utils/profcheck-xfail.txt
+35-142 files

LLVM/project 50d4fbcllvm/include/llvm/ADT FoldingSet.h, llvm/include/llvm/Analysis ScalarEvolution.h

[ADT] Remove unused IDHash parameter from Equals (NFC) (#219313)

This patch removes the unused IDHash parameter from several functions.
Now that FoldingSetTrait<SDVTListNode>::Equals no longer checks IDHash,
no implementation of Equals uses this parameter.

Assisted-by: Antigravity
DeltaFile
+8-12llvm/include/llvm/ADT/FoldingSet.h
+3-4llvm/lib/Support/FoldingSet.cpp
+2-2llvm/include/llvm/Analysis/ScalarEvolution.h
+1-1llvm/include/llvm/CodeGen/SelectionDAG.h
+14-194 files

LLVM/project ce4f490llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Use make_pointer_range
DeltaFile
+1-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-21 files

LLVM/project be0676allvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

Precommit test
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163-01 files

LLVM/project 3099e1cllvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]
DeltaFile
+24-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+5-7llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+40-183 files

LLVM/project b8bd749llvm/test/Transforms/LoopVectorize blend-i1.ll

Precommit test
DeltaFile
+58-0llvm/test/Transforms/LoopVectorize/blend-i1.ll
+58-01 files

LLVM/project fe1edc7llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize blend-i1.ll dont-fold-tail-for-divisible-TC.ll

[VPlan] Process simplifyRecipes in a worklist

This brings simplifyRecipes further in line with InstCombine, and asides from unlocking more simplifications it also helps avoid spurious test churn whenever passes are moved around simplifyRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification order as before.

I've gone through and checked every simplification we do is a canonicalisation that converges, and I checked on llvm-test-suite + SPEC CPU 2017 in various configurations that we don't hit any cycles.
DeltaFile
+23-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-8llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+2-3llvm/test/Transforms/LoopVectorize/blend-i1.ll
+29-253 files

LLVM/project 5eaa5caflang/lib/Lower ConvertConstant.cpp, flang/lib/Optimizer/CodeGen CodeGen.cpp

[flang] Speed up large CHARACTER DATA initializers (#218813)

[flang] Speed up large CHARACTER DATA initializers

Repeated CHARACTER(KIND=1) array constants were lowered as one
fir.insert_value per element. Converting those chains to LLVM IR is
quadratic and can make compilation take tens of minutes.

Lower consecutive equal KIND=1 character elements with
fir.insert_on_range
and emit full-range initializers as a single flattened [N x i8] LLVM
global
string, keeping Fortran blank padding.

A 160000-element character DATA statement now compiles in well under a
second and before was more than 10 minutes.
DeltaFile
+51-11flang/lib/Optimizer/CodeGen/CodeGen.cpp
+40-0flang/test/Lower/character-array-constant.f90
+20-13flang/lib/Lower/ConvertConstant.cpp
+111-243 files

LLVM/project f6dbeb9libcxxabi/src/demangle ItaniumDemangle.h, libcxxabi/test DemangleTestCases.inc

[ItaniumDemangle] Fix conversion operators failing to demangle types with substitutions
DeltaFile
+9-0llvm/unittests/Demangle/DemangleTest.cpp
+5-0llvm/include/llvm/Testing/Demangle/DemangleTestCases.inc
+5-0libcxxabi/test/DemangleTestCases.inc
+4-0llvm/include/llvm/Demangle/ItaniumDemangle.h
+4-0libcxxabi/src/demangle/ItaniumDemangle.h
+27-05 files

LLVM/project 92efec0clang/docs ReleaseNotes.md, clang/lib/AST RecordLayoutBuilder.cpp

[AST] Make err_struct_too_large check target-aware (#218749)

ASTContext::getASTRecordLayout used a fixed 1ULL << 60 threshold for
err_struct_too_large, regardless of the target's size_t width.

Scale the threshold to the target's size_t width instead, so it is below
(1 << 32) on 32-bit architectures. Diagnosing the overflow in Sema
avoids the crash in codegen.

rdar://183351516
DeltaFile
+15-4clang/test/AST/absurdly_big_struct.cpp
+4-1clang/lib/AST/RecordLayoutBuilder.cpp
+4-0clang/docs/ReleaseNotes.md
+23-53 files

LLVM/project 1442b18llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/test/CodeGen/X86 code-model-elf-text-sections.ll

[X86] Properly inherit all section flags from parent for basic block sections (#219289)

Or else we miss flags like SHF_X86_64_LARGE.
DeltaFile
+18-0llvm/test/CodeGen/X86/code-model-elf-text-sections.ll
+3-1llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+21-12 files

LLVM/project 8950c53utils/bazel/llvm-project-overlay/lldb/source/Plugins plugin_config.bzl BUILD.bazel

[Bazel] Fixes 8921ec7 (#219331)

This fixes 8921ec7e89e024c6185bc99cc195d787b3537ea6 (#217791).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=8921ec7e89e024c6185bc99cc195d787b3537ea6

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+9-3utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
+1-1utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
+10-42 files

LLVM/project 860a07blibc/include netdb.yaml, libc/include/llvm-libc-macros/linux netdb-macros.h

[libc] Add stubs for POSIX netdb.h and getaddrinfo (#219337)

* Add the `<netdb.h>` POSIX header and declare `struct addrinfo` and
`freeaddrinfo` and `getaddrinfo` methods
as defined in
https://pubs.opengroup.org/onlinepubs/9799919799/functions/getaddrinfo.html
;
* Provide Linux-specific definitions for `EAI_` macro family;
* Add header/entrypoints to the list of "experimental" (i.e. WIP)
entrypoints on Linux systems;
* Create the proxy header harness for types / Linux-specific macro.
* Provide stub implementations - no-op `freeaddrinfo` and `getaddrinfo`
that returns `EAI_SYSTEM` and sets errno to `ENOSYS`. Validate this
behavior in unit tests.

Assisted by automated tooling, human-reviewed
DeltaFile
+44-0libc/include/netdb.yaml
+34-0libc/src/netdb/getaddrinfo.cpp
+34-0libc/test/src/netdb/netdb_test.cpp
+31-0libc/include/llvm-libc-types/struct_addrinfo.h
+29-0libc/src/netdb/getaddrinfo.h
+28-0libc/include/llvm-libc-macros/linux/netdb-macros.h
+200-019 files not shown
+423-025 files

LLVM/project 0309576libc/src/__support/macros config.h, libc/src/unistd/linux execle.cpp

[libc] Do not suppress -Wvla-cxx-extension for older clang versions. (#219342)
DeltaFile
+4-0libc/src/__support/macros/config.h
+1-1libc/src/unistd/linux/execle.cpp
+5-12 files