LLVM/project 626d568clang/lib/StaticAnalyzer/Core CallEvent.cpp

Run clang-format once again.
DeltaFile
+2-1clang/lib/StaticAnalyzer/Core/CallEvent.cpp
+2-11 files

LLVM/project e7abbe9clang/lib/StaticAnalyzer/Core CallEvent.cpp

[analyzer] Replace getAdjustedParameterIndex with getDeclaredParameterIndex in CallEvent.cpp
DeltaFile
+3-3clang/lib/StaticAnalyzer/Core/CallEvent.cpp
+3-31 files

LLVM/project 6b2ef39llvm/include/llvm/CodeGen MachineRegisterInfo.h, llvm/lib/CodeGen/GlobalISel IRTranslator.cpp

[GlobalISel] Reserve IRTranslator value map and virtual register storage (NFC) (#222311)

Reserve storage based on the number of IR arguments and instructions to
avoid unnecessary container growth.

Improves CTMark geomean -0.08% on aarch64-O0-g, including 0.18% on
sqlite.

https://llvm-compile-time-tracker.com/compare.php?from=cec101b15dd27fb1c51b6c87cb6e9d78517d2b09&to=996caa798ca6e27dfc657296db4b8ae6519701b0&stat=instructions:u

Assisted-by: codex
DeltaFile
+9-0llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+6-0llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+15-02 files

LLVM/project 65ed1d6llvm/lib/CodeGen MachineSink.cpp

CodeGen: Remove dead LiveVariables plumbing from MachineSink

MachineSink threaded a LiveVariables pointer through to
SplitCriticalEdge so the analysis would be updated. It never used
LiveVariables for any decision, and MachineSinking runs before
LiveVariables pass in every pipeline.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+9-15llvm/lib/CodeGen/MachineSink.cpp
+9-151 files

LLVM/project 246beebllvm/lib/Transforms/Utils BuildLibCalls.cpp

[BuildLibCalls] Use emitLibCall() in more places (NFCI) (#222557)
DeltaFile
+12-106llvm/lib/Transforms/Utils/BuildLibCalls.cpp
+12-1061 files

LLVM/project add15b3llvm/lib/Target/AMDGPU SIOptimizeVGPRLiveRange.cpp, llvm/test/CodeGen/AMDGPU si-opt-vgpr-liverange-bug-deadlanes.mir opt-vgpr-live-range-verifier-error.mir

AMDGPU: Use LiveIntervals in SIOptimizeVGPRLiveRange when available

LiveVariables has been long deprecated. Use LiveIntervals if available.
With the current pass structure, this will use LiveVariables.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+76-18llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
+2-0llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
+2-0llvm/test/CodeGen/AMDGPU/opt-vgpr-live-range-verifier-error.mir
+80-183 files

LLVM/project 14ec791llvm/lib/Target/AMDGPU SIOptimizeVGPRLiveRange.cpp

Address review comments
DeltaFile
+8-13llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
+8-131 files

LLVM/project 35a6d33llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/Target/AMDGPU AMDGPUTargetParser.td GCNProcessors.td

AMDGPU: Remove deprecated getArchAttr and ArchFeatures TableGen (#222462)

Everything should now use getFeatureBitset*

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+92-159llvm/lib/Target/AMDGPU/GCNProcessors.td
+0-44llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+20-21llvm/unittests/TargetParser/TargetParserTest.cpp
+2-23llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+0-21llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
+0-20llvm/test/TableGen/AMDGPUTargetDefErrors.td
+114-2885 files not shown
+121-31611 files

LLVM/project 182f0eacompiler-rt/test/fuzzer stop-file.test

[libFuzzer] Modify stop-file.test to support remote devices (#222012)

Currently this test fails when running on remote devices because the
'rm' command only removes the file from the host, and the second part of
the test expects the file to have been removed. This patch changes the later 
run command to point to a non-existent file in order to work around this.

rdar://186683123
DeltaFile
+1-3compiler-rt/test/fuzzer/stop-file.test
+1-31 files

LLVM/project 404ceballvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 neon-implicit-zero-filling.ll

[AArch64][NEON] Fold insert(zero, extract(X, 0), 0) -> X when X is known to zero lanes 1-N (#213940)

Add patterns for NEON across-lane reductions whose scalar result
is inserted into lane zero of a zero vector.

This is valid because these instructions place their result in lane zero
and
clear the remaining lanes.

Limit this change to matching input and result vector types. Mixed
vector
sizes and scalar conversions are not part of this PR.

Handle llvm.vector.reduce.add.v2i64 separately because it lowers to
ADDP.
NEON has no equivalent instruction for v2i64 signed or unsigned min/max
reductions, so they cannot use this fold. Double-precision
floating-point
reductions are already handled by pairwise instruction patterns.
DeltaFile
+400-0llvm/test/CodeGen/AArch64/neon-implicit-zero-filling.ll
+59-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+459-02 files

LLVM/project 24d30a5llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU sgpr-scavenge-fi-stack-id.ll sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir

[AMDGPU] Scale the frame register in place when lowering scalar frame indices
DeltaFile
+184-0llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir
+73-7llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+3-23llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
+260-303 files

LLVM/project 48b81ddllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/lib/Transforms/Vectorize/SLPVectorizer SLPTree.h

[SLP][modularisation][NFC] Move BoUpSLP class declaration to SLPTree.h

Move the BoUpSLP class declaration and its nested types out of
SLPVectorizer.cpp into SLPVectorizer/SLPTree.h. This is a pure relocation:
method definitions stay in SLPVectorizer.cpp, and the prerequisite changes
(de-inlining the cl::opt users; seeding SLPTree.h with ReductionVectorPart
and MinScheduleRegionSize) landed earlier in the stack.

The header is included after DEBUG_TYPE is defined because BoUpSLP inline
methods use LLVM_DEBUG. The DenseMapInfo/GraphTraits specializations remain
in SLPVectorizer.cpp.

Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
DeltaFile
+4,958-3llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPTree.h
+4-4,863llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4,962-4,8662 files

LLVM/project f5eb6f9llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[AMDGPU][GIsel][NPM] Complete Global Isel pipeline
DeltaFile
+976-476llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+46-0llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1,022-4762 files

LLVM/project 8016407mlir/include/mlir/Dialect/Linalg/IR LinalgNamedStructuredOps.yaml, mlir/lib/Dialect/Linalg/Transforms NamedToElementwise.cpp CategoryToNamedOp.cpp

[MLIR][Linalg] Remove Linalg named ops (#220916)

Removes the named ops from the Linalg dialect.

I have also updated the ElementwiseOp builder to simplify the default
case: kind + no affine map.

Depends on both unary and binary removal branches. #220905 #220912

This PR also has the final cleanup, which turned out to be simple
enough.

Ref:

https://discourse.llvm.org/t/rfc-update-semantics-of-linalg-named-operations-unary-binary-ternary/91531

Assisted by: Claude Opus
DeltaFile
+95-100mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
+9-57mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
+0-61mlir/lib/Dialect/Linalg/Transforms/CategoryToNamedOp.cpp
+0-57mlir/lib/Dialect/Linalg/Transforms/NamedToElementwise.cpp
+0-57mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
+0-48mlir/test/Dialect/Linalg/named-ops-fail.mlir
+104-38012 files not shown
+121-53018 files

LLVM/project 70f5696mlir/include/mlir/Dialect/Linalg/IR LinalgNamedStructuredOps.yaml, mlir/python/mlir/dialects/linalg/opdsl/ops core_named_ops.py

[MLIR][Linalg] Remove binary named ops (#220912)

Remove ops, change tests to elementwise to continue working as is.

Depends on the unary removal branch. #220905 

Ref:

https://discourse.llvm.org/t/rfc-update-semantics-of-linalg-named-operations-unary-binary-ternary/91531

Assisted by: Claude Opus
DeltaFile
+0-395mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
+0-272mlir/test/Dialect/Linalg/named-ops.mlir
+0-202mlir/test/Dialect/Linalg/generalize-named-ops.mlir
+0-160mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-named-ops.mlir
+0-155mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
+33-105mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
+33-1,28924 files not shown
+235-1,86530 files

LLVM/project 3b99e79mlir/include/mlir/Dialect/Linalg/IR LinalgNamedStructuredOps.yaml, mlir/python/mlir/dialects/linalg/opdsl/ops core_named_ops.py

[MLIR][Linalg] Remove unary named ops (#220905)

Remove ops, change tests to elementwise to continue working as is.

Ref:

https://discourse.llvm.org/t/rfc-update-semantics-of-linalg-named-operations-unary-binary-ternary/91531

Assisted by: Claude Opus
DeltaFile
+1-456mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
+0-403mlir/test/Dialect/Linalg/named-ops.mlir
+0-275mlir/test/Dialect/Linalg/generalize-named-ops.mlir
+0-208mlir/test/Dialect/Linalg/named-ops-fail.mlir
+1-157mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
+63-63mlir/test/Dialect/Linalg/transform-op-fuse.mlir
+65-1,56222 files not shown
+184-2,15128 files

LLVM/project 51daef2llvm/lib/Target/X86 X86FixupSetCC.cpp X86FastISel.cpp, llvm/lib/Target/X86/GISel X86InstructionSelector.cpp

X86: Mark EFLAGS dead on MOV32r0 emitted outside SelectionDAG (#222464)

Currently these get set by LiveVariables after the fact, but
ideally we would not rely on that since it's long overdue for
deletion.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+13-7llvm/lib/Target/X86/X86FastISel.cpp
+2-2llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+2-1llvm/lib/Target/X86/X86FixupSetCC.cpp
+17-103 files

LLVM/project 0573ec9mlir/lib/Tools/mlir-lsp-server MLIRServer.cpp, mlir/test/mlir-lsp-server diagnostics.test definition.test

[mlir][lsp] Handle unrepresentable file locations (#220913)
DeltaFile
+89-0mlir/test/mlir-lsp-server/definition.test
+28-7mlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp
+20-0mlir/test/mlir-lsp-server/diagnostics.test
+137-73 files

LLVM/project bab513bllvm/test/CodeGen/AMDGPU amdgcn.bitcast.768bit.ll amdgcn.bitcast.832bit.ll

[AMDGPU] Use new CSR cost calculation (#219220)

So far, AMDGPU backend relied on the legacy calculation for the cost of
the first use of a callee-save register. This legacy path scales the
entry block frequency by a fixed value, making a comparison with
alternatives, e.g., rematerialization, difficult due to different
scales. One example for that is the work in
https://github.com/llvm/llvm-project/pull/206756, where comparison of
rematerialization cost and first use of a CSR is hard to compare due to
the different scales.

Change to instead use the new calculation path with different target
hooks for better comparability.

As the new scale is different, the cost was changed. The new cost value
accounts for various factors impacting CSR cost.

This change (with different cost value) was originally part of
https://github.com/llvm/llvm-project/pull/202007. Another part of that

    [5 lines not shown]
DeltaFile
+57,327-55,762llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,634-6,608llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,576-5,657llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+4,486-4,550llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+2,884-2,534llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+2,268-1,797llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+79,175-76,90815 files not shown
+83,791-80,79221 files

LLVM/project dbda42allvm/test/CodeGen/AMDGPU select-flags-to-fmin-fmax.ll fptosi-sat-vector.ll

Add COPY_TO_REGCLASS
DeltaFile
+1,049-1,046llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+358-358llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+272-152llvm/test/CodeGen/AMDGPU/fpow.ll
+188-187llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
+162-162llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+144-144llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
+2,173-2,04941 files not shown
+3,226-3,13147 files

LLVM/project d9b301dllvm/test/CodeGen/AMDGPU float-to-arbitrary-fp-widen.ll amdgcn.bitcast.512bit.ll

[AMDGPU] Select trunc(srl x, 16) as hi16 subregister on true16
DeltaFile
+6,170-6,593llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+4,692-4,496llvm/test/CodeGen/AMDGPU/bf16.ll
+2,809-3,010llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,809-3,010llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+2,754-2,970llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,545-1,574llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+20,779-21,653127 files not shown
+30,851-47,532133 files

LLVM/project 672843alibcxx/include/__algorithm pstl.h, libcxx/include/__pstl/backends serial.h

[libc++][pstl] Implementation of parallel std::minmax_element() based on parallel reduce (#221572)

This PR adds an implementation of parallel `std::minmax_element()` based
on parallel reduce.

The implementation formulates `minmax_element` as a reduction of
iterators over the input range.
The iterators are first transformed into a min-max iterator pair.
The reduction is provided in two forms: 2-element reduction that makes
an iterator pair pointing to a smaller and a greater value, and a
range-based reduction with init value.
The latter delegates the heavy-lifting to the serial implementation of
`std::minmax_element()`.

Part of #99938.
DeltaFile
+212-0libcxx/test/std/algorithms/alg.sorting/alg.min.max/pstl.minmax_element_comp.pass.cpp
+209-0libcxx/test/std/algorithms/alg.sorting/alg.min.max/pstl.minmax_element.pass.cpp
+93-0libcxx/include/__pstl/cpu_algos/minmax_element.h
+25-0libcxx/include/__algorithm/pstl.h
+11-0libcxx/include/__pstl/backends/serial.h
+8-0libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
+558-08 files not shown
+589-014 files

LLVM/project ab7245dlibclc/clc/lib/generic/math clc_fmod.cl

libclc: Update fmod implementations (#222369)

This was originally ported from rocm device libs in
93af966747b59d37c57312a0c0242151076c072b. Merge in more
recent changes. This should also approximately match the default
expansion in ExpandIRInsts

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+96-124libclc/clc/lib/generic/math/clc_fmod.cl
+96-1241 files

LLVM/project 02a6e6ellvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/Target/AMDGPU AMDGPUTargetParser.td GCNProcessors.td

AMDGPU: Remove deprecated getArchAttr and ArchFeatures TableGen

Everything should now use getFeatureBitset*

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+92-159llvm/lib/Target/AMDGPU/GCNProcessors.td
+0-44llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+20-21llvm/unittests/TargetParser/TargetParserTest.cpp
+2-23llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+0-21llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
+0-20llvm/test/TableGen/AMDGPUTargetDefErrors.td
+114-2885 files not shown
+121-31611 files

LLVM/project 96295a1clang/lib/Parse ParseExpr.cpp, clang/test/SemaCXX cxx2d-pack-indexing-template.cpp

[Clang] Fix a crash when forming a type from an indexed TTP. (#222326)

Unreported 24 issue so no release note.
DeltaFile
+12-0clang/test/SemaCXX/cxx2d-pack-indexing-template.cpp
+1-1clang/lib/Parse/ParseExpr.cpp
+13-12 files

LLVM/project ad6d0b9clang/lib/AST/ByteCode Pointer.h InterpBuiltin.cpp, llvm/test/tools/llvm-rc show-includes.test

rebase

Created using spr 1.3.7
DeltaFile
+186-32clang/lib/AST/ByteCode/Interp.cpp
+80-27clang/lib/AST/ByteCode/Interp.h
+71-15clang/lib/AST/ByteCode/Pointer.cpp
+39-18clang/lib/AST/ByteCode/InterpBuiltin.cpp
+29-8clang/lib/AST/ByteCode/Pointer.h
+26-0llvm/test/tools/llvm-rc/show-includes.test
+431-10016 files not shown
+505-13822 files

LLVM/project 22d7c0bclang/lib/AST/ByteCode Pointer.h InterpBuiltin.cpp, llvm/test/tools/llvm-rc show-includes.test

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+186-32clang/lib/AST/ByteCode/Interp.cpp
+80-27clang/lib/AST/ByteCode/Interp.h
+71-15clang/lib/AST/ByteCode/Pointer.cpp
+39-18clang/lib/AST/ByteCode/InterpBuiltin.cpp
+29-8clang/lib/AST/ByteCode/Pointer.h
+26-0llvm/test/tools/llvm-rc/show-includes.test
+431-10016 files not shown
+505-13822 files

LLVM/project f5ce708clang/lib/AST/ByteCode Pointer.h InterpBuiltin.cpp, llvm/test/tools/llvm-rc show-includes.test

rebase

Created using spr 1.3.7
DeltaFile
+186-32clang/lib/AST/ByteCode/Interp.cpp
+80-27clang/lib/AST/ByteCode/Interp.h
+71-15clang/lib/AST/ByteCode/Pointer.cpp
+39-18clang/lib/AST/ByteCode/InterpBuiltin.cpp
+29-8clang/lib/AST/ByteCode/Pointer.h
+26-0llvm/test/tools/llvm-rc/show-includes.test
+431-10016 files not shown
+505-13822 files

LLVM/project 0e3cda1clang/lib/AST/ByteCode Pointer.h InterpBuiltin.cpp, llvm/test/tools/llvm-rc show-includes.test

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+186-32clang/lib/AST/ByteCode/Interp.cpp
+80-27clang/lib/AST/ByteCode/Interp.h
+71-15clang/lib/AST/ByteCode/Pointer.cpp
+39-18clang/lib/AST/ByteCode/InterpBuiltin.cpp
+29-8clang/lib/AST/ByteCode/Pointer.h
+26-0llvm/test/tools/llvm-rc/show-includes.test
+431-10015 files not shown
+501-13521 files

LLVM/project 4f90f14clang/lib/AST/ByteCode Pointer.h InterpBuiltin.cpp, llvm/test/tools/llvm-rc show-includes.test

rebase

Created using spr 1.3.7
DeltaFile
+186-32clang/lib/AST/ByteCode/Interp.cpp
+80-27clang/lib/AST/ByteCode/Interp.h
+71-15clang/lib/AST/ByteCode/Pointer.cpp
+39-18clang/lib/AST/ByteCode/InterpBuiltin.cpp
+29-8clang/lib/AST/ByteCode/Pointer.h
+26-0llvm/test/tools/llvm-rc/show-includes.test
+431-10015 files not shown
+501-13521 files