[clang][Driver]: Skip crti.o/crtn.o on LoongArch FreeBSD (#228689)
FreeBSD will not provides crti.o and crtn.o for LoongArch: the
_init/_fini interface they assemble is obsolete, and constructors and
destructors run exclusively through .init_array/.fini_array.
Skip both objects when the target is loongarch FreeBSD. Other FreeBSD
architectures are unchanged, and LoongArch on other operating systems is
not affected.
FreeBSD reference: https://reviews.freebsd.org/D59892
Signed-off-by: xiaoqiang zhao <zxq_yx_007 at 163.com>
[clang-repl] Added -hip option (#231783)
This PR adds a hidden `-hip` option to clang-repl, with `-rocm-path` for
the SDK location. It sets up the HIP host and device compilers and the
HIP device parser. HIP code doesn't execute yet, because binary
generation is still a stub that returns an unsupported error. That will
come in follow-up PRs.
I have also added a lit test in `clang/test/Interpreter/HIP` which runs
clang repl with the option hip and expects for not supported message for
now. This test will be removed in the future PR when the HIP kernel will
be built.
Prerequisite PR : #231391
Assisted by Claude Sonnet 5.5
[LoongArch] Add scheduler definitions for LoongArch with schedule model for LA464/LA664 (#226064)
This patch adds full scheduler definitions for LoongArch backend and
schedule models for LA464/LA664, covering basic instructions and
LSX/LASX SIMD instructions, along with a series of `llvm-mca` tests.
The model are base on a Chip and Cheese microarchitecture analysis
article, [Loongson 3A6000: A Star among Chinese
CPUs](https://chipsandcheese.com/p/loongson-3a6000-a-star-among-chinese-cpus/),
which has a detailed analysis for LA464/LA664 microarchitecture. The
latency/throughput numbers were measured from actual machine, so many of
them depend on estimate.
`PostRAScheduler` was not set because we found that it will cause
regression on SPEC CPU2006 470.lbm testcase. `MispredictPenalty` is also
based on a raw guess. Besides, even if `LoopMicroOpBufferSize` will have
a positive impact on performance due to loop unrolling, these
microarchitecture details is still unknown, so I would perfer override
the `getUnrollingPreferences` in future TTI patches, or waiting for more
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[mlir][tblgen] Define enum `FieldParser` specializations out-of-line (#233730)
The `FieldParser` specializations generated for every enum were defined
inline in the enum declarations header. Since their bodies do not depend
on the `ParserT` template parameter, they are type-checked eagerly in
every translation unit including the header, which instantiates
`FailureOr<E>`, `FailureOr<std::optional<E>>` and their `std::optional`
bases and type traits for every enum. Only a small fraction of these
specializations is ever used, and only from the generated attribute and
op parsers of the dialect itself.
This patch changes `parse` to a non-template taking an `AsmParser &`,
declares it in the header and emits its definition into the enum
definitions file instead.
Compiling all of MLIR (clang 18 with 64 cores) takes 4.5% less CPU time,
with the median translation unit compiling 2.8% faster and some up to
15% faster. The summed peak memory usage of all translation units drops
by 4.5% and the largest peak memory usage of a single translation unit
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[offload] Add direct-write memcpys to liboffload and implement them on AMDGPU
olMemcpy gets a variant with a flag parameter. The flags are an enum and
DIRECT_WRITE is the first member of it. Specifying DIRECT_WRITE means
that the olMemcpy may issue the copy as a direct H2D write, which means
that it will be unordered with respect to the currently enqueued
operations. It will, however, be completed upon completion of olMemcpy,
so it will not be unordered with respect to operations that get enqueued
afterwards.
The AMDGPU implementation is a transfer of the ROCr/HIP implementation.
It more or less boils down to a std::memcpy with fences around it.
Claude assisted with this patch.
[lldb] Select the thread before reading its siginfo (#233814)
qXfer:siginfo:read returns the siginfo of the thread selected by the Hg
packet (that's how gdb uses it, and it's also what lldb-server expects),
but ThreadGDBRemote::GetSiginfo didn't select the thread. This meant we
returned the siginfo of whichever thread happened to be selected last.
With lldb-server, that's usually (but not always) the thread which
caused the stop.
This hasn't been a big problem so far, as the siginfo was only used by
the "thread siginfo" command, but I'd like to use it to compute the stop
descriptions of crashing threads, where this matters more.
Assisted-by: Claude
[CodeGen] Clear call site info when resetting a MachineFunction (#229331)
MachineFunction::clear() deletes the instructions but keeps the call
site info and called globals that refer to them. After
ResetMachineFunction, which GlobalISel uses to fall back to
SelectionDAG, the entries point to deleted instructions, and printing
the MIR hangs. Clear both maps with the rest of the function, as is done
for the variable debug info that GlobalISel records.
No GlobalISel target records call site info yet, so the test resets a
MIR function marked failedISel.
[IR] Remove SyntheticFunctionEntryCount label (#233351)
And everything that uses it. Synthetic profile counts have been mostly
removed at this point, so this is unnecessary to keep around.
[mlir] Fix false positive loops in RegionBranchOpInterface::hasLoop
hasLoop reported a loop whenever its traversal popped a region it had
already visited. The worklist gets one entry per successor of each
terminator, so a region reachable along two paths was popped twice even
without a cycle, for example when two terminators of a region branch to
the same successor region.
hasLoop now reports a loop only if a region reachable from the parent op
can reach itself, which is the check isRepetitiveRegion already does.
Drop the now unused visited argument of the traversal stop condition.
Assisted-by: Claude Code (Claude Opus 5.5)
[Sema][CUDA][HIP] Report deferred diagnostics of force-emitted functions (#229008)
Deferred diagnostics of a __host__ __device__ function are reported once
the function is known to be emitted, which Sema decided from its uses
and external linkage. CodeGen also emits a function regardless of its
uses if it has the used, constructor or destructor attribute, or with
-femit-all-decls, so such inline functions were emitted without their
diagnostics. Treat these functions as emitted, like what
ASTContext::DeclMustBeEmitted does.
Assisted-by: Claude Opus 5.5
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
[RISCV][GlobalISel] Support i64 load/store for RV32+Zilsd (#221148)
Extend the legalizer, register bank info, and instruction selector to
handle i64 load/store via LD_RV32/SD_RV32.
Assisted-by: Claude
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
[CSPreInliner] Use always_inline/noinline attributes in pre-inliner
Teach the CSSPGO pre-inliner to respect the always_inline and noinline
attributes encoded in pseudo probe descriptors
(-preinliner-use-inline-attributes, default off). The attributes are stamped
onto the context profiles of each function. shouldInline() never inlines a
noinline callee and always inlines an always_inline one, since the compiler
enforces both whatever the plan says.
An always_inline callee is not charged to the caller's size budget, and it is
admitted even when that budget is exhausted: the budget loop used to stop
before shouldInline() was reached, so the plan recorded the callee as not
inlined while the compiler inlines it anyway.
-preinliner-charge-always-inline-size (default off) charges an always_inline
callee's size to the budget instead, so an always_inline subtree can crowd out
ordinary candidates; the callee itself is still always inlined.
[mlir][LLVM] Verify LLVMStructType element types in get()
`using Base::verifyInvariants` pulled in StorageUserBase's variadic no-op
verifier. `StorageUserBase::get` passes a `unique_function` emitter, which
binds to that template exactly, so `getLiteral` skipped the element type
check even in assertions builds.
Drop the `using` and add a storage-key overload. Sub-element replacement
needs it because it rebuilds literal structs with `Base::get(ctx, key)`.
Assisted-by: Claude Code (Claude Opus 5.5)
[CIR] Reject void record members, array elements and union padding
!cir.void has no data layout, so a record or array that holds one has
none either. The verifiers accepted such types, and the first size query
crashed. CallConvLowering hit a DataLayout fatal error on a union
argument, and LowerToLLVM asserted in LLVMStructType::setBody.
The record and array verifiers now reject void, so no consumer has to
guard against it. CallConvLowering still accepts void as a parameter
type, which the x86_64 classifier ignores.
Assisted-by: Claude Code (Claude Opus 5.5)
[PseudoProbe] Encode inline attributes in probe descriptor
Record a function's always_inline and noinline attributes in its pseudo probe
descriptor, so that the profile generator can see them. The
!llvm.pseudo_probe_desc metadata gets a trailing i8 attributes operand (GUID,
hash, name, attributes); a descriptor without it, from older IR, has no
attributes. In the .pseudo_probe_desc section the attributes take bits [60:63]
of the 64-bit hash field, which the function hash leaves free, and
MCPseudoProbeDecoder splits them back into MCPseudoProbeFuncDesc::Attributes
and the hash.
