[LoopFusion] Do not fuse loops with different guards (#199724)
The testcase that was originally contributed to #193641 exposed a
functional issue in which loop fusion can fuse functions with different
loop guards. There seem to two distinct bugs and each of them alone is
enough to let this happen.
- The condition that checks loop guards are identical, intends to
exclude loops that require peeling. But the condition is not correct and
it allows some loops that do not require peeling to pass.
- The condition that checks two guards are identical implicitly assume
conditions of guard branches are instructions, but this is not
necessarily always correct.
This patch fixes the problem for the loops that do not require peeling.
The issue still exists for loops that require peeling and will be fixed
separately.
[lldb] New expedited register specfication for unavailable regs (#193894)
When lldb-server/debugserver send a stop packet, they expedite the
vaLues of many of the general purpose registers in the stop packet, so
lldb doesn't need to fetch them separately.
On Darwin systems using an AArch64 M4 or newer SOC with SME, we need to
fetch the streaming vector length (svl) register when in Streaming SVE
Mode to correctly size the registers in lldb. On Darwin systems, when we
are not in SSVE mode, svl is undefined -- it is not included in the
expedited registers. However, lldb will still try to fetch the value, so
we get a register-read packet at every stop on M4 and newer systems,
trying to fetch the value.
This patch adds a new format for the expedited registers. They are
normally a `;` separated series of `{regnum}:{native endian bytes}`.
This allows for `{regnum}:` alone, indicating that the register value
for regnum cannot be fetched at this stop.
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Reland "[libc] Enable baremetal float printf using modular format" (#199758)
Reverts llvm/llvm-project#199114
#199118 fixed the issue uncovered in the Fuchsia CI build.
[lldb] Fix vtable support on arm64e (#199116)
There were 2 small issues.
1. ValueObjectVTableChild was not fixing the addresses it was pulling
from signed pointers. This broke things like `SBValue::GetLoadAddress`
and identifying the function pointer type from debug info.
2. TestVTableValue.py made a lot of assumptions that did not hold on
arm64e. a. GetValueAsUnsigned will return a raw pointer value. Most of
the time, we needed GetValueAsAddress. b. The test was reading pointers
out of memory without fixing them up. c. The summary for a function
pointer on arm64e includes the load address. This isn't true on other
platforms.
[SLP] Propagate through instrinsics in BoUpSLP::getVectorElementSize() (#199129)
We propagate through simple binary operations already, some operations
are excluded since it happens to be an intrinsic.
Motivated by case exposed when removing vectorization from pre-LTO, see
https://github.com/llvm/llvm-project/pull/195886#issuecomment-4486422243.
[AMDGPU] Add regression test for extract of vector binop scalarization (#198825)
Test that extracting both lanes from a binop of two build_vectors
sharing a variable operand at different lane positions correctly folds
per-lane constants.
Assisted-by: Cursor (Claude)
[AMDGPU] Fix ELF note emission to include null terminator (#199720)
The `AMDGPUTargetELFStreamer::EmitNote()` function claims the note name
includes a null terminator (NameSZ = Name.size() + 1) but only emits the
string bytes via `emitBytes(Name)`, relying on alignment padding to
provide the null byte. Works for most situations but breaks with 8-byte
names where padding lands exactly at the boundary.
Explicitly emit null terminator with `S.emitInt8(0)` after
`emitBytes(Name)`.
Revert "[clang][driver][darwin] Hold onto full triples in Darwin SDKP… (#199756)
…latformInfo (#197791)"
This reverts commit 9c06c5de6a20df13cfe6d9a7022308e96f378955. It broke
downstream builds for compiler-rt builtins.
Resolves: rdar://177813095
[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs
These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.
Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
[AMDGPU] Implement CFI for CSR spills
Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.
Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.
Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Implement CFI for non-kernel functions
This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.
Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU
While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).
Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
[AMDGPU] Emit entry function Dwarf CFI
Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.
Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[Clang] Default to async unwind tables for amdgcn
To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.
There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.
Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
