[flang][OpenMP] Ignore DECLARE_SIMD and warn about missing implementa… (#232712)
…tion
Currently DECLARE_SIMD emits a "not yet implemented" error in the MLIR
to LLVM IR translation.
DECLARE_SIMD is a hint to the compiler and ignoring it is technically
speaking a conforming implementation (although obviously not desirable).
Do not abort compilation when DECLARE_SIMD is encountered, but emit a
warning that it's currently ignored.
[SLP]Compare main lanes of same-opcode and copyable states
For a same-opcode state both main lanes were skipped, so the original
main lane (potenitally with copyables) was never compared.
Fixes #230578
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/233266
[RISCV][P-ext] Use concat_vectors with 0 in widenPackedVectorWithZeros. (#232940)
This will be legalized and combined to a vector_shuffle. That shuffle
can then be matched to a pack with x0 after #232892.
This changes the zext.w to a pack, but that's not obviously worse. If we
need to canonicalize we can add a DAG combine later.
[RISCV][P-ext] Remove custom lowering of insert_subvector for v2i16/v4i8 on RV64. (#232899)
This was for handling inserting into a zero vector. After #232892 we let
the insert_subvector legalize to a shuffle_vector which we can then
lower as pack.
This changes the codegen from zext.w to pack, but that's not necessarily
worse. If it turns out to be a problem we can canonicalize pack with
zero with a DAGCombine or isel patterns in the future.
[flang][OpenMP] Switch clause verification to descriptor-based
Delete all the scattered pieces of clause verification that are now
replaced by the unified handling.
[X86] combineConcatVectorOps - ensure at least one of the VSELECT/BLENDV selection operands fully concatenates (#233245)
Don't rely on IsConcatFree - we might still end up with temporary
CONCAT_VECTORS nodes that might not get folded away before another
combine recognises a vector that can be freely split.
Fixes #233185
[InstCombine] Added log2-ceil check for non-power-of-two integer widths (#232418)
The log2-ceil fold is only valid for power-of-two integer bit widths.
Adding check for verifying bit width is power of two.
Fixes #227862
[AMDGPU] Price memory operations by the number of memory instructions
Price a load or store as the number of memory instructions it is split
into.
Constant and buffer "fat" pointers are left alone (for now).
[AMDGPU] Price under-aligned memory operations
Without unaligned access for the address space, an access aligned below
4 bytes is split into pieces of its alignment. LDS accesses aligned to 4
use 8-byte pieces, and take a 12-byte piece only when aligned to 16 or
when unaligned DS access is enabled.
[X86] Allow bf16 masked load/store with AVX512BW (#230953)
bf16 masked loads/stores don't use any avx512bf16 instructions, but
isLegalMaskedLoadStore only accepted bfloat with hasBF16(). Without it
they got scalarized, which is pretty bad (one branch plus an
extend/truncate libcall per element). With BWI they can use vmovdqu16
the same way f16 does, and the existing mask_move_lowering_f16_bf16
patterns only need BWI.
This relaxes the TTI check to BWI like half, and makes
v8bf16/v16bf16/v32bf16 legal with BWI. They were only legal with
BF16/AVXNECONVERT before, so on plain BWI the masked ops were split
before isel ever saw them (avx512bf16 implies BWI anyway). To go with
that:
- v8bf16/v16bf16 masked loads/stores use the same non-VLX widening as
f16.
- A few broadcast/insert/extract/subvector zeroing patterns that don't
need any bf16 instructions are now enabled with BWI (or folded into the
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RegisterPressure: Detect dead physreg defs from LiveIntervals with lane masks (#233215)
Extend the fix from #225079 to the lane mask tracking path used by
targets with subregister liveness. adjustLaneLiveness also needs to
force the physreg unit ranges to be computed to identify dead defs,
rather than taking the conservative default when they are not cached.
Without this, an overlapping physreg def missing a dead flag is
counted as a live def. Conservatively assuming it is live doesn't work
because PressureDiff disagrees with the tracker and fails the
EXPENSIVE_CHECKS consistency assert.
This avoids an ll asm test failing when LiveVariables removed; #233202
fixes the missing dead flag for that case. I had additional patches
which nearly eliminate all missing dead flags. Unless the verifier
enforces accurate dead flags, we still need to handle this edge case.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[LV] Thread an explicit CM param through VPlan-building/costing helpers (#224836)
Parameterize `cost()`, `tryToBuildVPlan1()`, `tryToBuildVPlan()`,
`buildVPlans()` and `addReductionResultComputation` with an explicit
`LoopVectorizationCostModel &PlanCM` argument instead of always reaching
for the planner's own CM member.
This is preparation for tail-folded vector epilogue support, which will
plan against a separate CM from the one used for the main vector loop.
Passing the CM in explicitly lets these functions to be called with
whichever CM applies to what's currently being planned.
All existing call sites still pass *CM, so this is NFC.
[clang][docs] fix grammar and spelling errors in cir docs (#220877)
Fix some obvious typos and grammar mistakes in the CIR docs.
Signed-off-by: Hardik Kumar <hardikxk at gmail.com>
[flang][OpenMP] Switch clause verification to descriptor-based
Delete all the scattered pieces of clause verification that are now
replaced by the unified handling.
[AMDGPU][GlobalISel]: Fix uniform unmerge into 16-bit values (#232954)
UnmergeI32 replaces UnmergeV2S16: it produces the same 32-bit chunks
directly in the scalar representation that the unpack helper needs.
These previous <2 x s16> pieces were immediately passed to unpackAExt,
which bitcast each one to i32 before extracting its halves.
This preserves the previously valid vector case and also supports the
scalar i64 case, where producing vector chunks directly was invalid. The
<4 x s16> MIR regression checks the resulting four 16-bit outputs in
order.
Assisted by: Claude Opus 5.5
[Option] Allow subcommand names as positional arguments (#227077)
ArgList::getSubCommand() treats every positional argument that matches
a subcommand name as a subcommand, and reports multiple subcommands if
more than one does. That rejects valid command lines where a later
positional argument happens to be spelled like a subcommand, e.g.
git branch clone # create a new branch named "clone"
Add an AllowSubCommandNamesAsPositionals parameter to getSubCommand().
When set, the first positional argument that matches a subcommand name
is the subcommand, and later ones are passed to HandleOtherPositionals
instead of being reported as multiple subcommands.
This is needed by tools that can take a name or path as positional
argument.
Since name and path can be arbitrary strings including subcommand names.
AMDGPU: Mark unread physreg defs dead in a scheduler test (#233214)
These registers defined by IMPLICIT_DEF but never read. Without the
dead flags, the pressure tracker assumes the uncached physreg units
are live out of the region. Ideally physreg dead flags would be
accurate, though this is currently not a verifier enforced rule. This
avoids some test churn in a future pressure tracking commit.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[flang][OpenMP] Switch clause verification to descriptor-based
Delete all the scattered pieces of clause verification that are now
replaced by the unified handling.
[flang][OpenMP] Improve diagnostics about modifier properties
Use OpenMPDeprecated and OpenMPFuture warning categories for modifier
diagnostics as well, analogously to how they are used for clauses.
