LLVM/project d5f0b9ellvm/include/llvm/Analysis AliasAnalysis.h, llvm/lib/Transforms/Scalar LICM.cpp

[LLVM][LICM] Skip unrelated accesses when looking for hoist/sink conflicting instructions. (#195132)

Essentially uses ModRef analysis in place of getClobberingMemoryAccess()
because the former has more accurate information as to how in loop
accesses and the hoist/sink target relate.
DeltaFile
+10-41llvm/lib/Transforms/Scalar/LICM.cpp
+38-3llvm/test/Transforms/LICM/hoist-inaccesiblemem-call.ll
+3-0llvm/include/llvm/Analysis/AliasAnalysis.h
+1-2llvm/test/Transforms/LICM/call-hoisting.ll
+1-1llvm/test/Transforms/LICM/pr54495.ll
+53-475 files

LLVM/project 4899e71llvm/lib/Target/AMDGPU VOP3PInstructions.td SIInsertWaitcnts.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp AMDGPUBaseInfo.h

[AMDGPU] Increment VA_VDST twice for each VOP3PX2 instruction (#196353)

In expert scheduling mode, change the VA_VDST counts to match the
hardware implementation. The inserted waits were conservatively correct
before. This just makes them more precise in some cases.
DeltaFile
+29-0llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx1250.mir
+6-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+7-1llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+5-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+4-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+51-65 files

LLVM/project 2e2d90blibcxx/include any, libcxx/include/__chrono file_clock.h

[libc++] Introduce implicit and explicit ABI annotations (#193045)

This patch introduces `_LIBCPP_{BEGIN/END}_EXPLICIT_ABI_ANNOTATIONS` and
marks everything within an
`_LIBCPP_{BEGIN,END}_UNVERSIONED_NAMESPACE_STD` (and any derivatives
like `_LIBCPP_{BEGIN,END}_NAMESPACE_STD`) implicitly by default. This
allows us to drop `_LIBCPP_HIDE_FROM_ABI` in most of the code base,
except for functions which shouldn't be `_LIBCPP_HIDE_FROM_ABI`.

This patch doesn't remove any `_LIBCPP_HIDE_FROM_ABI`s, since we have
over 13k of them in the code base. Actually dropping them will happen
over some time to avoid too many merge conflicts.
DeltaFile
+22-0libcxx/include/__configuration/utility.h
+14-2libcxx/include/__configuration/namespace.h
+4-0libcxx/include/__new/new_handler.h
+4-0libcxx/include/__chrono/file_clock.h
+4-0libcxx/include/any
+4-0libcxx/src/expected.cpp
+52-2138 files not shown
+331-5144 files

LLVM/project 0bdf71dlldb/source/Core IOHandlerCursesGUI.cpp Debugger.cpp, lldb/test/API/commands/gui/console-output TestGuiConsoleOutput.py main.cpp

Revert "[lldb] Real-time console pane for output in lldb tui" (#196507)

Reverts llvm/llvm-project#177160

The new test is timing out on the AArch64 Linux buildbot
(https://lab.llvm.org/buildbot/#/builders/59/builds/34166) and on my own
machine.

I suspect something to do with the requested terminal size. If what we
get is smaller than requested, it could time out waiting for expected
program output.
DeltaFile
+23-357lldb/source/Core/IOHandlerCursesGUI.cpp
+0-138lldb/test/API/commands/gui/console-output/TestGuiConsoleOutput.py
+0-34lldb/test/API/commands/gui/console-output/main.cpp
+0-6lldb/source/Core/Debugger.cpp
+0-4lldb/source/Core/CoreProperties.td
+0-2lldb/test/API/commands/gui/console-output/Makefile
+23-5412 files not shown
+23-5448 files

LLVM/project ca7fe08clang/test/OpenMP spirv_target_teams_reduction_addrspace.c, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[llvm][OpenMP][SPIRV] Fix assertion for GPU reductions (#194879)

Currenty compiling a `target reduction` results in the following assert
for spirv64-intel target:

> Assertion `New->getType() == getType() && "replaceUses of value with
new value of different type!"' failed.

This patch fixes it by adding an addrespace cast where necessary to make
the types of the expressions match.

Assisted-by: claude-sonnet-4-5
DeltaFile
+33-0clang/test/OpenMP/spirv_target_teams_reduction_addrspace.c
+9-1llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+42-12 files

LLVM/project 11c0c42clang/lib/Driver/ToolChains Darwin.cpp AMDGPU.cpp

clang: Add BoundArch argument to addClangTargetOptions

addClangTargetOptions already has an OffloadKind argument,
but it kind of doesn't make sense for any function to know the
OffloadKind, but not the associated BoundArch.

The current process is kind of convoluted. TranslateArgs
synthesizes a -mcpu argument from BoundArch, and later
addClangTargetOptions re-parses that -mcpu argument each
time it wants the architecture. Add this argument so this
can be cleaned up in a future change.

Co-authored-by: Claude Sonnet 4 <noreply at anthropic.com>
DeltaFile
+9-5clang/lib/Driver/ToolChains/Darwin.cpp
+7-5clang/lib/Driver/ToolChains/AMDGPU.cpp
+7-3clang/lib/Driver/ToolChains/Darwin.h
+6-3clang/lib/Driver/ToolChains/AMDGPU.h
+5-3clang/lib/Driver/ToolChains/Gnu.h
+5-3clang/lib/Driver/ToolChains/Cuda.cpp
+39-2248 files not shown
+115-5654 files

LLVM/project 23590a8llvm/test/Transforms/InstSimplify compare.ll

update test
DeltaFile
+1-3llvm/test/Transforms/InstSimplify/compare.ll
+1-31 files

LLVM/project 88bb0e6llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 shuffles.ll build-vector-two-dup.ll

[AArch64]  Use EXT for byte shuffles with leading zeros (#193466)

Fixes: https://github.com/llvm/llvm-project/issues/191735

Teach AArch64 LowerVECTOR_SHUFFLE to recognize byte shuffles that are a
zero fill right shift and lower them to EXT with a zero vector. Adds a
regression test too.

Change-Id: Iffe97ff7e35cfaff790f537b4f1f5ba9aded4f92
DeltaFile
+184-0llvm/test/CodeGen/AArch64/shuffles.ll
+81-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-3llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
+1-3llvm/test/CodeGen/AArch64/build-vector-extract.ll
+268-64 files

LLVM/project b10baa4llvm/lib/Target/AMDGPU AMDGPU.td

Remove extra space
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPU.td
+1-11 files

LLVM/project 9698c4dlldb/packages/Python/lldbsuite/test lldbtest.py, lldb/packages/Python/lldbsuite/test/tools/lldb-server gdbremote_testcase.py

[lldb][test] Move DAP processes to own group to avoid random SIGHUPs (#195816)

On macOS, LLDB's test suite randomly receives SIGHUP signals that stop
the test suite early. The source of these SIGHUP's seems to be a bug in
the kernel (most likely job control).

The exact steps for reproducing this are not clear, but I have a set of
three tests of which two need to run concurrently for this to trigger:

* TestDAP_runInTerminal
* TestDAP_launch_io_integratedTerminal
* TestDAP_launch_stdio_redirection_and_console

I was also running UBSan on this build which may or may not be necessary
to make this random failure more persistent.

When these tests run, macOS job control will send SIGHUP to the process
group of the spawned subprocesses in that test. As LIT is in the same
process group, it also receives the SIGHUP and shuts down.

    [8 lines not shown]
DeltaFile
+9-3lldb/test/API/tools/lldb-server/commandline/TestStubSetSID.py
+10-0lldb/packages/Python/lldbsuite/test/lldbtest.py
+5-1lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+24-43 files

LLVM/project 0041fa4clang/test/Tooling clang-linker-wrapper-spirv.cpp, llvm/test/tools/llvm-objdump/Offloading nested-offload-binary.test nested-offload-binary-fails.test

[llvm][tools] Extend llvm-objdump to support nested OffloadBinaries (#185425)

Extends llvm-objdump to print the information of images contained in
nested OffloadBinaries. For example, for a binary compiled with #185413
it shows
```
 $llvm-objdump --offloading ./a.out

./a.out:        file format elf64-x86-64

OFFLOADING IMAGE [0]:
kind            elf
arch
triple          spirv64-intel
producer        openmp
image size      43104 bytes
  [Nested OffloadBinary format detected]
  Number of inner images: 1
  kind            spir-v

    [13 lines not shown]
DeltaFile
+85-0llvm/test/tools/llvm-objdump/Offloading/nested-offload-binary.test
+49-7llvm/tools/llvm-objdump/OffloadDump.cpp
+38-0llvm/test/tools/llvm-offload-binary/llvm-offload-binary.ll
+19-0llvm/test/tools/llvm-objdump/Offloading/nested-offload-binary-fails.test
+13-0clang/test/Tooling/clang-linker-wrapper-spirv.cpp
+4-0llvm/test/tools/llvm-objdump/Offloading/elf.test
+208-71 files not shown
+212-77 files

LLVM/project 218b7b4llvm/lib/Target/X86 X86InstrGISel.td, llvm/lib/Target/X86/GISel X86InstructionSelector.cpp X86LegalizerInfo.cpp

[X86][GlobalISel] Support globals in pic mode (#170038)

Introduce G_WRAPPER_RIP it is the same node as in DAG. It is required to
make legalization possible when a load from stub is required to obtain a
pointer to a global value. It allows to avoid manual selection in
X86InstructionSelector.

Also added a missing check on X86SelectAddress failure.
DeltaFile
+82-35llvm/test/CodeGen/X86/GlobalISel/GV.ll
+12-34llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+32-1llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+6-6llvm/test/CodeGen/X86/machine-block-hash.mir
+9-0llvm/lib/Target/X86/X86InstrGISel.td
+4-2llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir
+145-781 files not shown
+148-787 files

LLVM/project d1ac3dfllvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

[DAG] canCreateUndefOrPoison - ISD::AssertSext/Zext/Align/NoFPClass only generate poison (#196492)
DeltaFile
+1-1llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+1-11 files

LLVM/project 8484aeaopenmp/device/src Reduction.cpp

remove unneeded always_inline instances
DeltaFile
+0-5openmp/device/src/Reduction.cpp
+0-51 files

LLVM/project 11e06callvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

[DAG] canCreateUndefOrPoison - poison generating flags / out of range shift amounts only generate poison (#196489)

Matches ValueTracking / GISel implementations - although testing options are limited until DAG has actual uses of UndefPoisonKind::UndefOnly
DeltaFile
+3-2llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+3-21 files

LLVM/project 589f419llvm/lib/Target/X86/GISel X86LegalizerInfo.cpp X86RegisterBankInfo.cpp, llvm/test/CodeGen/X86 isel-fneg.ll

[X86][GlobalISel] Added support for FNEG (#167919)
DeltaFile
+116-0llvm/test/CodeGen/X86/GlobalISel/isel-fneg.mir
+57-12llvm/test/CodeGen/X86/isel-fneg.ll
+6-0llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+1-0llvm/lib/Target/X86/GISel/X86RegisterBankInfo.cpp
+180-124 files

LLVM/project 2423265lldb/tools/lldb-dap CMakeLists.txt

[lldb-dap] Fix build when using precompiled header and Xcode generator. (#196366)

When building with precompiled headers and Xcode as a generator, It adds
`obj.lldbDAP.dir/${BUILD_TYPE}/cmake_pch.xxx` but does not generate one
causing the build to fail.
This might have to do with `add_llvm_library` adding a source file
`Dummy.c` to any object it creates if using Xcode as a generator and
`lldbDAP` object not declaring it's LINK_LIBS and LINK_COMPONENTS.
DeltaFile
+7-0lldb/tools/lldb-dap/CMakeLists.txt
+7-01 files

LLVM/project 0168948libclc README.md

[libclc] Use spirv[64]-mesa-mesa3d triple in README.md (#196483)

Now that #194607 landed we use a normalized triple in the README for the
SPIRV targets. Before `spirv-mesa3d-` and `spirv64-mesa3d-` were being
used and those will be normalized to `spirv-unknown-mesa3d` and
`spirv64-unknown-mesa3d` by the following command in
`runtimes/CMakeLists.txt` with this command:

```console
$ clang --target=spirv-mesa3d- -print-target-triple
spirv-unknown-mesa3d
```

This is because in `llvm/lib/TargetParser/Triple.cpp` the term `mesa3d`
is recognized as an OS and placed in third position. The install path
for `libclc.spv` there ends up in `spirv-unknown-mesa3d/libclc.spv`.

With this change we suggest to use triples that "survive" the
normalization:

    [7 lines not shown]
DeltaFile
+3-3libclc/README.md
+3-31 files

LLVM/project 54e6a03llvm/test/CodeGen/AArch64 bf16-v8-instructions.ll bf16-v4-instructions.ll, llvm/test/CodeGen/AMDGPU amdgpu-simplify-libcall-pow.ll arbitrary-fp-to-float.ll

Merge branch 'users/el-ev/icmp_strict_form' into users/el-ev/pr145204-comment
DeltaFile
+5,910-880llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+3,306-504llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
+0-775llvm/utils/Reviewing/find_interesting_reviews.py
+665-0llvm/test/CodeGen/NVPTX/arbitrary-fp-to-float.ll
+329-329llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
+595-8llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float.ll
+10,805-2,4961,244 files not shown
+33,651-14,6661,250 files

LLVM/project 4223779llvm/lib/Analysis InstructionSimplify.cpp, llvm/test/Transforms/InstSimplify compare.ll

[InstSimplify] Recognize strict-form variants in icmp simplification
DeltaFile
+73-0llvm/test/Transforms/InstSimplify/compare.ll
+26-8llvm/lib/Analysis/InstructionSimplify.cpp
+99-82 files

LLVM/project 863282bclang/test/Sema inline-asm-constraint-embedded-null.c

...
DeltaFile
+3-3clang/test/Sema/inline-asm-constraint-embedded-null.c
+3-31 files

LLVM/project 3531440cross-project-tests/debuginfo-tests/dexter/dex/debugger DAP.py DebuggerBase.py, cross-project-tests/debuginfo-tests/dexter/dex/debugger/dbgeng dbgeng.py

[Dexter][NFC] Add split step-data collection methods for DAP (#196350)

This patch adds some extra state collection methods to DebuggerBase and
implements them for DAP only. These methods are used to fetch a
stacktrace without variable information, and to populate variable
information into a StepIR containing only a stacktrace. These methods
are currently unused, making this patch NFC, but this is a necessary
precursor to the new script model, where we examine the stacktrace to
determine what variable info we will collect.

As part of the stacktrace-collection function, we also fetch the
instruction address for each stack frame, if it is made available by the
debugger; to enable this, this patch adds a new value with default
`None` to `FrameIR`.
DeltaFile
+65-1cross-project-tests/debuginfo-tests/dexter/dex/debugger/DAP.py
+11-0cross-project-tests/debuginfo-tests/dexter/dex/debugger/visualstudio/VisualStudio.py
+10-1cross-project-tests/debuginfo-tests/dexter/dex/dextIR/FrameIR.py
+9-0cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerBase.py
+7-0cross-project-tests/debuginfo-tests/dexter/dex/debugger/dbgeng/dbgeng.py
+7-0cross-project-tests/debuginfo-tests/dexter/dex/debugger/lldb/LLDB.py
+109-26 files

LLVM/project 5ff13aflibc/include wchar.yaml, libc/src/wchar CMakeLists.txt fwide.cpp

[libc] implement fwide (#196157)

Add fwide function and tests. Part 1/11. All build file changes are in
part 11.

Assisted by Gemini
DeltaFile
+178-2libc/test/src/wchar/CMakeLists.txt
+138-1libc/src/wchar/CMakeLists.txt
+67-0libc/include/wchar.yaml
+54-0libc/test/src/wchar/fwide_test.cpp
+44-0libc/src/wchar/fwide.cpp
+27-0libc/src/wchar/fwide.h
+508-33 files not shown
+543-49 files

LLVM/project b039667clang/lib/Driver/ToolChains AMDGPU.h PS4CPU.cpp

clang: Add BoundArch/OffloadKind argument to getSupportedSanitizers

Currently the AMDGPU HIP and OpenMP toolchains falsely report
all host sanitizers are supported, and then go out of their way
to skip forwarding those to the device compiles. Add an offloading
kind argument so that in the future this can be handled in one
place in the base toolchain.

Co-authored-by: Claude Sonnet 4 <noreply at anthropic.com>
DeltaFile
+11-2clang/lib/Driver/ToolChains/AMDGPU.h
+8-4clang/lib/Driver/ToolChains/PS4CPU.cpp
+6-3clang/lib/Driver/ToolChains/HIPSPV.cpp
+6-2clang/lib/Driver/ToolChains/PS4CPU.h
+5-2clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
+5-2clang/lib/Driver/ToolChains/BareMetal.cpp
+41-1540 files not shown
+190-7246 files

LLVM/project d791e3allvm/lib/Target/AArch64 MachineSMEABIPass.cpp, llvm/test/CodeGen/AArch64 sme-zt0-state.ll sme-peephole-opts.ll

[AArch64][SME] Elide private ZA setup when possible (#196090)

In private ZA functions without any instructions that require "active"
ZA we can omit all ZA setup (and saves/restores). This is equivalent to
removing the `__arm_new("za/zt0")` attribute when ZA state is unused.
DeltaFile
+11-36llvm/test/CodeGen/AArch64/sme-zt0-state.ll
+2-34llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
+16-1llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+29-713 files

LLVM/project d0d5daeclang/test/Sema inline-asm-constraint-embedded-null.c

update test
DeltaFile
+3-3clang/test/Sema/inline-asm-constraint-embedded-null.c
+3-31 files

LLVM/project dabb079llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU pseudo-scalar-transcendental.ll

AMDGPU/GlobalISel: Implement RegBankLegalizeRules for amdgcn_log, amdgcn_rcp, and amdgcn_sqrt (#195099)
DeltaFile
+440-61llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
+9-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+449-622 files

LLVM/project 59aaa53llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Transforms/LoopVectorize/AArch64 partial-reduce-costs.ll partial-reduce-chained.ll

[AArch64] Reflect cost of integer sub-reductions. (#194594)

The cost of sub-reductions is either the cost of *mlslb + *mlslt, or the
cost of a dot operation with 2 negations:
```
       partial_reduce_umls acc, lhs, rhs
  <=> -partial_reduce_umla -acc, lhs, rhs
```
(codegen for this was added by #186809)

The cost-model was previously a bit of a hack, since sub-reductions were
expanded and therefore expensive, although we made the expansion cost
artifically cheaper so that it would still be a candidate for cdot
instructions.
DeltaFile
+666-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-costs.ll
+23-21llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+8-6llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
+2-2llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-sdot.ll
+699-294 files

LLVM/project 3e2a1ddclang/include/clang/Basic DiagnosticSemaKinds.td

Update clang/include/clang/Basic/DiagnosticSemaKinds.td

Co-authored-by: Corentin Jabot <corentinjabot at gmail.com>
DeltaFile
+1-1clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-11 files

LLVM/project 8b9cfeaclang/test/Driver print-supported-extensions-riscv.c, clang/test/Preprocessor riscv-target-features.c

[RISCV] Add support for Ziccid 1.0 (#196459)

No codegen and instruction.
It may be ratified in the future. https://github.com/riscv/riscv-isa-manual/pull/2598
DeltaFile
+9-0clang/test/Preprocessor/riscv-target-features.c
+4-0llvm/lib/Target/RISCV/RISCVFeatures.td
+3-0llvm/test/MC/RISCV/attribute-arch.s
+2-0llvm/test/CodeGen/RISCV/attributes.ll
+1-0llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+1-0clang/test/Driver/print-supported-extensions-riscv.c
+20-03 files not shown
+23-09 files