[flang] Enable wrap-unstructured-constructs-in-execute-region by default
More extensive testing since the flag was introduced, with the
regressions it uncovered now fixed.
[RISCV] Andes: model fast unaligned accesses for the 45-series (#221166)
The 45-series cores support unaligned scalar accesses. Add
FeatureUnalignedScalarMem to each 45-series processor (andes-n45,
andes-nx45, andes-a45, andes-ax45 and andes-ax45mpv), so that it is
selected by -mcpu rather than -mtune. Other processors declare it this
way too. The feature is somewhat architectural: -mtune is only supposed
to affect performance, but reaching it through tune features lets -mtune
introduce unaligned accesses that crash on a CPU which does not support
them.
Cover this in memcpy.ll using -mcpu=andes-a45/-mcpu=andes-ax45. The new
RUN lines pass -mtune=rocket so that the 45-series scheduling model does
not reorder the output, letting them reuse the existing check lines.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
[SLP][modularisation][NFC] Move getNumberOfParts, isAllowedNonPowerOf2VF (#220827)
Move the following BoUpSLP-independent type/width helpers out of
SLPVectorizer.cpp into SLPVectorizer/SLPTypeUtils.{h,cpp}:
getNumberOfParts
isAllowedNonPowerOf2VF
Both read a file-local cl::opt (SLPReVec and VectorizeNonPowerOf2
respectively). The options stay static in SLPVectorizer.cpp; the moved
helpers take their values as explicit bool parameters. Behavior is
unchanged.
Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
[InterleavedLoadCombine] Index candidates to avoid quadratic matching (#213053)
Matching scanned every candidate against every other candidate, which
got very slow on functions with many interleaved loads. Index by address
offset and look up neighbors instead.
llc's Compile-time drops from 212s to ~2s on a Grace machine for the
test case in the issue.
[ Compile-time remains flat
](https://llvm-compile-time-tracker.com/?config=Overview&stat=instructions%3Au&remote=madhur13490)
Fixes #162299.
Assisted by Cursor.
[libc++] Implement LWG4072: std::optional comparisons: constrain harder (#209968)
Resolves #118345.
Previously, the heterogeneous comparison operators (`==`, `!=`, `<`,
`<=`, `>`, `>=`) for arguments `T` and `U` don't check that `T` or `U`
are not a `std::optional` themselves. This allowed the operators to
cause ambiguous overload resolution instead of falling back to
`optional`'s own operators, which possibly caused hard error when there
should not be a matched overload.
This patch implements the resolution by adding
`!__is_std_optional_v<_Up>` (and the `_Tp` equivalent for the reversed)
to the constraints in all twelve involved operators.
As required by the LLVM Project's AI use policy:
- The fix and test processes were revised and verified with AI
assistance.
Revert "[ELF] Omit zero-range FDEs from .eh_frame_hdr" (#221624)
Reverts llvm/llvm-project#220492
This causes the RISC-V buildbots to fail in the exception handling
tests, see https://lab.llvm.org/buildbot/#/builders/210/builds/12623 for
the gauntlet build logs
Apologies this revert is coming in so late, there is a proposed fix at
https://github.com/llvm/llvm-project/pull/221342 but it looks like it
might require additional rounds of review so reverting to get the
buildbots back to green for now
cc @MaskRay @Prabhuk
[AMDGPU] Introduce ABI occupancy for object linking
This PR introduces ABI occupancy as the contract used to compile functions under
object linking. The default is the occupancy needed for a 1024 workitem
workgroup. It can be overridden for a module by the `amdgpu_abi_waves_per_eu`
module flag, replaced for a function by `amdgpu-flat-work-group-size`, or
tightened by an accepted `amdgpu-waves-per-eu` hint.
The ABI occupancy replaces the workgroup-derived minimum that an
`amdgpu-waves-per-eu` hint is validated against, so the hint can only make the
contract stricter.
The backend emits the selected occupancy in `.amdgpu.info` and uses it to
enforce the object linking register budget.
Implement pay-for-what-you-use warnings in LifetimeSafetyChecker
We split IsLifetimeSafetyEnabled into individual check functions
in SemaLifetimeSafety.h:
- ShouldCheckSafety
- ShouldCheckNoescapeViolations
- ShouldCheckLifetimeboundViolations
- ShouldCheckMisplacedLifetimebound
- ShouldCheckInapplicableLifetimebound
- ShouldSuggestLifetimeAnnotations
These properties are stored in LifetimeSafetyOpts, which are then checked
inside the Checker to avoid invoking expensive reporting functions mapping
to diagnostics that are disabled.
TAG=agy
CONV=a79c61c3-92c6-404e-83e3-3e3088f77c0e
[orc-rt] Split unit tests into SupportTests and BedrockTests (#221562)
Replace CoreTests with one test binary per layer. SupportTests links the
Support object library and nothing else, so a new support-to-bedrock
dependency fails to link rather than going unnoticed.
Making that work required splitting CommonTestUtils.h: its
Bedrock-dependent helpers move to a new BedrockTestUtils.h, so that no
SupportTests translation unit includes a Bedrock header. That in turn
lets ProxyTest join SupportTests -- Proxy.h only forward-declares
Session, so the test can define its own instead of constructing a real
one.
[AArch64] Form CCMP for CBB and CBH
AArch64ConditionalCompares forms CMP/CCMP chains to transform patterns
such as
Head Head
/ | CmpBB
/ | / |
| CmpBB => / |
| / | Tail |
| / | | |
Tail | | |
| | | |
... ... ... ...
where Head is terminated by a conditional branch and CmpBB contains
a cmp + conditional branch.
We usually try to split any fused conditional branches to be able to
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[AArch64][CMPBR] Fix splitting of CBB/CBH instructions into ext + cmp
We falsely split CBB/CBH instructions by explicitly extending the
second register operand instead of the first one, leading to the
following, wrong codegen:
cbh $wn, $wm, cc, trgt => sxth $wt, $wm
cmp $wn, $wt, cc, sxth
Correct is
cbh $wn, $wm, cc, trgt => sxth $wt, $wn
cmp $wt, $wm, cc, sxth
since cmp with extended register extends it's second, not its first
operand.
[AArch64] Allow forming CCMPs for CB branches (#221111)
AArch64ConditionalCompares currently doesn't consider FEAT_CMPBR CB
instructions when trying to form CCMPs. This leads to a lot more
branches which is usually hurtful for performance.
The patchs adds handling CB instructions, just like we do for other
fused conditional branches such as CBZ or CBNZ.
[MachineOutliner] Properly handle Debug MachineInstrs (#219326)
Fixes #219176.
Debug instructions could affect `MachineOutliner` output in two ways:
- The minimum basic-block size check used `MachineBasicBlock::size()`,
which includes debug instructions. A block containing one ordinary
instruction and one debug instruction could therefore enter the mapper
even though it was too small to outline.
- Mapping an invisible debug instruction cleared `AddedIllegalLastTime`.
This changed the separator state and could affect persistent token
numbering, outlined-function ordering, and ultimately the generated
object code.
This patch makes debug instructions transparent to both decisions:
- Use the non-debug instruction count for the minimum block-size check.
- Preserve the mapper's separator state for debug instructions while
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