LLVM/project b738491llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp SIInstrInfo.h, llvm/test/CodeGen/AMDGPU memory-legalizer-non-volatile.ll promote-constOffset-to-imm-gfx12.mir

[AMDGPU][GFX12.5] Add support for emitting memory operations with nv bit set (#179413)

- Add `MONonVolatile` MachineMemOperand flag.
- Set nv=1 on memory operations on GFX12.5 if the operation accesses a
constant address space,
  is an invariant load, or has the `MONonVolatile` flag set.
DeltaFile
+365-0llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
+43-13llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+5-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+1-1llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
+1-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+415-145 files

LLVM/project 134bf19llvm/test/CodeGen/RISCV/rvv abs-vp.ll fixed-vectors-abd.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+319-0llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+308-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+247-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+203-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+156-0llvm/test/CodeGen/RISCV/rvv/abd.ll
+107-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+1,340-020 files not shown
+1,764-6026 files

LLVM/project aa64ae5llvm/test/CodeGen/RISCV/rvv abs-vp.ll fixed-vectors-abd.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+319-0llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+308-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+247-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+207-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+156-0llvm/test/CodeGen/RISCV/rvv/abd.ll
+107-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+1,344-020 files not shown
+1,846-6226 files

LLVM/project 35ab0e2llvm/test/CodeGen/RISCV/rvv abs-vp.ll fixed-vectors-abd.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+319-0llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+308-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+247-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+156-0llvm/test/CodeGen/RISCV/rvv/abd.ll
+107-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+94-0llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
+1,231-020 files not shown
+1,644-6026 files

LLVM/project 59d1eadllvm/test/CodeGen/RISCV/rvv abs-vp.ll fixed-vectors-abd.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+319-0llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+308-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+247-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+203-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+156-0llvm/test/CodeGen/RISCV/rvv/abd.ll
+107-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+1,340-020 files not shown
+1,764-6026 files

LLVM/project ce07248llvm/lib/Transforms/Utils SimplifyLibCalls.cpp, llvm/test/Transforms/InstCombine double-float-shrink-1.ll sqrt.ll

InstCombine: Only propagate callsite attributes in sqrt->sqrtf

This was propagating the callee's attributes instead of just the
callsite. It's illegal to set denormal_fpenv on a callsite. This
was also losing callsite attributes which may have been more useful;
there's no point in setting the callee's attributes on the callsite.
DeltaFile
+48-22llvm/test/Transforms/InstCombine/double-float-shrink-1.ll
+5-4llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
+3-3llvm/test/Transforms/InstCombine/sqrt.ll
+56-293 files

LLVM/project 60f74c9clang/lib/CodeGen TargetInfo.h TargetInfo.cpp, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

Use StringRef
DeltaFile
+29-42clang/lib/CodeGen/Targets/AMDGPU.cpp
+3-3clang/lib/CodeGen/TargetInfo.h
+3-3clang/lib/CodeGen/Targets/SPIR.cpp
+1-1clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+1-1clang/lib/CodeGen/TargetInfo.cpp
+37-505 files

LLVM/project d64a609llvm/lib/Target/X86 X86.h

[NewPM] Uninitialize x86-cleanup-local-dynamic-tls in llvm/lib/Target/X86/X86.h (#180122)

I believe I exposed in
https://github.com/llvm/llvm-project/pull/179864/changes#diff-5b9707ff829bc5b6523a59982f375d99d6b4ded670fbd91dd095555f4ac80a14R428
. Getting rid of it to avoid possible undefined reference/linker errors.
DeltaFile
+0-1llvm/lib/Target/X86/X86.h
+0-11 files

LLVM/project 8cc0642llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel strict_fma.f64.ll strict_fma.f32.ll

Adding support for G_STRICT_FMA in new reg bank select (#170330)

This patch adds legalization rules for G_STRICT_FMA opcode.

---------

Co-authored-by: Abhinav Garg <abhigarg at amd.com>
DeltaFile
+1,048-65llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
+987-65llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
+913-98llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+2,949-2294 files

LLVM/project a262589llvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.cpp

[AArch64][GloballISel] Put result of fp16 -> s16 convert intrinsic on fpr

Previously, RegBankSelect would place the result of an fp16 -> s16 conversion intrinsic on a gpr. This would cause Instruction Selection to fail, as there are no 16-bit gprs.
Example floating point convert intrinsics:
fcvtnu / fcvtns
fcvtau / fcvtas
fcvtzu / fcvtzs
DeltaFile
+3-2llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+3-21 files

LLVM/project b214f6dllvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoZvabd.td, llvm/test/CodeGen/RISCV/rvv fixed-vectors-abd.ll abd.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+42-14llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+24-8llvm/test/CodeGen/RISCV/rvv/abd.ll
+14-5llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+10-5llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+90-324 files

LLVM/project 15d8489llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoZvabd.td, llvm/test/CodeGen/RISCV/rvv fixed-vectors-abd.ll abd.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+42-14llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+24-8llvm/test/CodeGen/RISCV/rvv/abd.ll
+13-5llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+10-5llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+89-324 files

LLVM/project 9d11a66llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU freeze.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_FREEZE (#179796)

Move G_FREEZE handling to AMDGPURegBankLegalizeRules.cpp.
Added support for uniform S1.
DeltaFile
+134-0llvm/test/CodeGen/AMDGPU/freeze.ll
+21-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+9-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+0-7llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+166-105 files

LLVM/project 4e6282allvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoZvabd.td, llvm/test/CodeGen/RISCV/rvv fixed-vectors-abd.ll abd.ll

Limit SEW to 8/16

Created using spr 1.3.6-beta.1
DeltaFile
+42-14llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+24-8llvm/test/CodeGen/RISCV/rvv/abd.ll
+13-5llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+10-5llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+89-324 files

LLVM/project 4af27b0clang/docs ReleaseNotes.rst, clang/lib/CodeGen CGExprScalar.cpp

[Clang] Fix atomic boolean compound assignment (#178220)

Fixes #33210
DeltaFile
+29-0clang/test/CodeGen/compound-assign-atomic-bool.c
+6-1clang/lib/CodeGen/CGExprScalar.cpp
+3-0clang/docs/ReleaseNotes.rst
+38-13 files

LLVM/project 7037e6eflang/lib/Optimizer/Dialect FIRType.cpp, flang/test/Lower polymorphic.f90 derived-type-sequence-alias-assign.f90

Revert "[flang] Use alias analysis in lowering record assignments" (#180150)

Reverts llvm/llvm-project#180010

Still breaking builds
DeltaFile
+202-202flang/test/Lower/polymorphic.f90
+0-56flang/test/Lower/derived-type-sequence-alias-assign.f90
+27-27flang/test/Lower/default-initialization.f90
+21-21flang/test/Lower/HLFIR/proc-pointer-comp-pass.f90
+1-18flang/lib/Optimizer/Dialect/FIRType.cpp
+9-9flang/test/Lower/HLFIR/cray-pointers.f90
+260-3335 files not shown
+261-35411 files

LLVM/project 6e3e74alldb/test/API/tools/lldb-dap/variables TestDAP_variables.py, lldb/tools/lldb-dap Variables.cpp JSONUtils.cpp

lldb-dap: Stop using replicated variable ids (#124232)

Closes #119784

Probably closes #147105 as well, but I couldn't test due to #156473:

This PR fixes two bugs:
1. It generates unique variable reference IDs per suspended debuggee
state.
2. It stores all created variables in a stopped state instead of
dropping variables in unselected scopes. So it can properly handle all
scope/variable requests

It does this by storing all variables in their respective scopes and
using that mapping in request handlers that relied on the old mapping.
It dynamically creates new variable/scope IDs instead of resetting IDs
whenever a new scope is created.

I also removed some unused code as well.

    [7 lines not shown]
DeltaFile
+116-16lldb/tools/lldb-dap/Variables.cpp
+0-85lldb/tools/lldb-dap/JSONUtils.cpp
+72-10lldb/tools/lldb-dap/Variables.h
+3-56lldb/tools/lldb-dap/Handler/ScopesRequestHandler.cpp
+46-9lldb/unittests/DAP/VariablesTest.cpp
+36-0lldb/test/API/tools/lldb-dap/variables/TestDAP_variables.py
+273-1764 files not shown
+318-18910 files

LLVM/project 3fe109ellvm/lib/Target/AArch64 MachineSMEABIPass.cpp, llvm/test/CodeGen/AArch64 sme-zt0-state.ll

[AArch64][SME] Add missing ZT0 transition (#179193)

This transition was missed off the switch, but is already supported (see
the test for the expected behavior).

(cherry picked from commit c7dd96e6f29b032a4879a7fe2fb0ff2ee1406aa5)
DeltaFile
+75-0llvm/test/CodeGen/AArch64/sme-zt0-state.ll
+1-0llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+76-02 files

LLVM/project d38f096llvm/lib/Transforms/Vectorize VPlanPredicator.cpp, llvm/test/Transforms/LoopVectorize predicate-switch.ll

[VPlan] Create edge mask for single-destination switch (#179107)

When converting phis to blends, the `VPPredicator` expects to have edge
masks to the phi node if the phi node has different incoming blocks.
This was not the case if the predecessor of the phi was a switch where a
conditional destination was the same as the default destination.

This was because when creating edge masks in `createSwitchEdgeMasks`,
edge masks are set in a loop through the *non-default* destinations. But
when there are no non-default destinations (but at least one condition,
otherwise an earlier condition would trigger and just forward the source
mask), this loop is never executed, so the masks are never set.

To resolve this, we explicitly forward the source mask for these cases
as well, which is correct because it is an unconditional branch, just a
very convoluted one.

fixes #179074

(cherry picked from commit 3bbf748a63a3cb38271a478b520789be57d5e2c8)
DeltaFile
+160-4llvm/test/Transforms/LoopVectorize/predicate-switch.ll
+4-0llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
+164-42 files

LLVM/project b02a636lldb/tools/driver Options.td

[lldb] Remove --debug/-d option from lldb (#179978)

The functionality was removed in
d3173f4ab61c17337908eb7df3f1c515ddcd428c after being broken for a long
time.

There's a small risk someone is still passing the option, but I think
it's time to remove it and they can fix their scripts.
DeltaFile
+0-5lldb/tools/driver/Options.td
+0-51 files

LLVM/project 95f5269flang/lib/Optimizer/Dialect FIRType.cpp, flang/test/Lower polymorphic.f90 derived-type-sequence-alias-assign.f90

[flang] Use alias analysis in lowering record assignments (#180010)

Without alias analysis Flang assumes no aliasing in lowering record
assignments which can result in miscompilation of programs using
SEQUENCE types and EQUIVALENCE.

Use alias analysis to guard the fast path in `genRecordAssignment`;
otherwise fall back to element-wise expansion.
Update FIR FileCheck expectations
Add `FIRAnalysis` to `"flang/unittests/Optimizer/CMakeLists.txt"` to fix
the Windows x64 build failure (linker error).
Add `SEQUENCE` handling and update tests accordingly.

Fixes #175246 (and includes the fix to
flang/lib/Optimizer/Builder/CMakeLists.txt in PR #176483).

Co-authored-by: Matt P. Dziubinski <matt-p.dziubinski at hpe.com>
DeltaFile
+202-202flang/test/Lower/polymorphic.f90
+56-0flang/test/Lower/derived-type-sequence-alias-assign.f90
+27-27flang/test/Lower/default-initialization.f90
+21-21flang/test/Lower/HLFIR/proc-pointer-comp-pass.f90
+18-1flang/lib/Optimizer/Dialect/FIRType.cpp
+9-9flang/test/Lower/HLFIR/cray-pointers.f90
+333-2605 files not shown
+354-26111 files

LLVM/project 88b78bclibcxx/include any, libcxx/test/std/utilities/any/any.class/any.cons value.pass.cpp

[libc++] Short-cut constraints of single-argument `any` constructor (#177082)

When a default template argument of a function template uses
`std::is_copy_constructible<T>::value` and `T` is convertible from and
to `any`, the changes in 21dc73f6a46cd786394f10f5aef46ec4a2d26175 would
introduce constraint meta-recursion when compiling with Clang.

This patch short-cuts constraints of the related constructor to avoid
computing `is_copy_constructible<T>` when `decay_t<T>` is `any`, which
gets rid of constraint meta-recursion in the overload resolution of copy
construction of `T`.

Fixes #176877.

(cherry picked from commit aa5428864e86f8e38806fc92d14cadc68b3d0667)
DeltaFile
+21-1libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp
+7-4libcxx/include/any
+28-52 files

LLVM/project 1573738utils/bazel/llvm-project-overlay/mlir/python BUILD.bazel

[bazel] Run builidifer. NFC.
DeltaFile
+3-3utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel
+3-31 files

LLVM/project 743116autils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Add missing dependency for 61b8a5783972f03d2a5a72713fa0daa095802ce (#180145)

DeltaFile
+2-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+2-01 files

LLVM/project a8b3872llvm/test/CodeGen/RISCV/rvv abs-vp.ll fixed-vectors-abd.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+319-0llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+280-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+247-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+140-0llvm/test/CodeGen/RISCV/rvv/abd.ll
+107-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+94-0llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
+1,187-020 files not shown
+1,585-5926 files

LLVM/project 5b01ef6llvm/test/CodeGen/RISCV/rvv abs-vp.ll fixed-vectors-abd.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+319-0llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+280-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+247-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+140-0llvm/test/CodeGen/RISCV/rvv/abd.ll
+107-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+94-0llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
+1,187-018 files not shown
+1,544-5924 files

LLVM/project b1bc9cbllvm/lib/Target/RISCV RISCVInstrInfoZvabd.td RISCVInstrInfoVVLPatterns.td, llvm/test/CodeGen/RISCV/rvv fixed-vectors-abd.ll abd.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+284-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+140-0llvm/test/CodeGen/RISCV/rvv/abd.ll
+83-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+63-0llvm/test/MC/RISCV/rvv/zvabd.s
+51-0llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+21-11llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+642-1113 files not shown
+720-2919 files

LLVM/project 9f59959llvm/test/CodeGen/RISCV/rvv abs-vp.ll fixed-vectors-abd.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+319-0llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+280-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
+247-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+140-0llvm/test/CodeGen/RISCV/rvv/abd.ll
+107-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
+94-0llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
+1,187-018 files not shown
+1,544-5924 files

LLVM/project 6f5b842utils/bazel/llvm-project-overlay/llvm BUILD.bazel

Fix Bazel build for d005cb2 (#180134)

Co-authored-by: Pranav Kant <prka at google.com>
DeltaFile
+25-5utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+25-51 files

LLVM/project 5654ecdllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AMDGPU div_v2i128.ll div_i128.ll

[DAGCombiner] Fix exact power-of-two signed division for large integers (#177340)

Previously, the DAG combiner did not optimize exact signed division by a
power-of-two constant divisor for integer types exceeding the size of
division supported by the target architecture (e.g., i128 on x86-64).
However, such an optimization was expected by the division expansion
logic, leading to unsupported division operations making it to
instruction selection.
This commit addresses this issue by making an exception to the existing
exclusion of signed division with the exact flag for the aforementioned
operations. That is, the DAG combiner will now optimize exact signed
division if the divisor is a power-of-two constant and the integer type
exceeds the size of division supported by the target architecture.

---------

Signed-off-by: Steffen Holst Larsen <HolstLarsen.Steffen at amd.com>
DeltaFile
+1,380-72llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+405-0llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
+182-0llvm/test/CodeGen/AMDGPU/div_i128.ll
+6-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+1,973-744 files