LLVM/project ea75745clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/test/CIR/CodeGen call-conv-lowering-x86_64-empty.cpp

[CIR] Handle an empty C++ class in x86_64 callconv lowering (#214742)

CIR lays a C++ empty class out as a record that is nothing but padding,
and isSupportedType rejected every padded record, so any signature
naming one failed the pass with an NYI. Ordinary C++ hits this
constantly through tag dispatch, allocators, and empty bases.

Implement empty C++ class support. Every record member now carries a
kind, so a record holds no data exactly when none of them is marked
data, which `RecordType::isEmptyForABI()` answers and the pass reads. An
empty record then maps with no fields, so the classifier drops it on its
own.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+268-0clang/test/CIR/Transforms/abi-lowering/x86_64-empty-class.cir
+179-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-empty.cpp
+50-4clang/test/CIR/Transforms/abi-lowering/x86_64-aggregate-nyi.cir
+35-9clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+532-134 files

LLVM/project 92ec4d7llvm/lib/Object Archive.cpp

Add assert into getZOSAttributes()
DeltaFile
+2-2llvm/lib/Object/Archive.cpp
+2-21 files

LLVM/project d62d5d1llvm/test/tools/llvm-nm zos-armap.test

Update test comment.
DeltaFile
+2-2llvm/test/tools/llvm-nm/zos-armap.test
+2-21 files

LLVM/project 775d99bllvm/include/llvm/Object Archive.h, llvm/test/tools/llvm-nm zos-armap.test

Address review comments.
DeltaFile
+19-20llvm/tools/llvm-nm/llvm-nm.cpp
+21-15llvm/test/tools/llvm-nm/zos-armap.test
+3-1llvm/include/llvm/Object/Archive.h
+43-363 files

LLVM/project d97bed5llvm/include/llvm/Object Archive.h, llvm/lib/Object Archive.cpp

[llvm-nm][GOFF] Display archive attributes in GOFF archives through --print-armap

GOFF archive symbol table entries contain an attribute word in addition
to the archive member offset. The low three bits describe whether the symbol is
64-bit, uses XPLink, or belongs to the WSA namespace (which was briefly mentioned
in e2c8fa09872cfacba7f73599dcf8557971ebe865).

This patch extends `llvm-nm --print-armap` to print the attribute value (in hex) and
its decoded description beside a symbol and its corresponding member when processing
a GOFF archive. This will functionality will be used to help validate full support for writing
GOFF archives in a subsequent llvm-ar patch.

The output for non-z/OS archives is unchanged.
DeltaFile
+44-5llvm/tools/llvm-nm/llvm-nm.cpp
+42-0llvm/test/tools/llvm-nm/zos-armap.test
+12-0llvm/lib/Object/Archive.cpp
+10-0llvm/include/llvm/Object/Archive.h
+108-54 files

LLVM/project bc45c1cllvm/tools/llvm-nm llvm-nm.cpp

Address review comments on the parameter.
DeltaFile
+2-3llvm/tools/llvm-nm/llvm-nm.cpp
+2-31 files

LLVM/project 879d6c8bolt/include/bolt/Utils CommandLineOpts.h, bolt/lib/Core BinaryContext.cpp

[BOLT] Skip data-hole filling unless data reordering is enabled

BinaryContext::postProcessSymbolTable unconditionally called
fixBinaryDataHoles(), which walks every allocatable section and, for
each gap in its address space, either grows a zero-sized data symbol
or creates a synthetic "HOLEat" BinaryData (plus an MCSymbol and
GlobalSymbols/BinaryDataMap entries).  This machinery was introduced
(0e4d86bf, 2017) for one purpose: to give static data reordering
(-reorder-data) a movable object covering every byte of a section. It
has no other consumer.

On a large binary, these synthetic objects are live from
buildFunctionsCFG through the end of the run and, at the RSS peak
(during debug info rewriting), fixBinaryDataHoles accounted for 1669
MB (2.5%) of peak RSS -- memory spent entirely for a feature that is
off by default.

Gate fixBinaryDataHoles() (and the zero-sized-symbol validation loop
that presumes it ran) on a non-empty opts::ReorderData, keeping
generateSymbolHashes() unconditional.
DeltaFile
+15-13bolt/lib/Core/BinaryContext.cpp
+1-7bolt/lib/Passes/ReorderData.cpp
+4-0bolt/lib/Utils/CommandLineOpts.cpp
+1-0bolt/include/bolt/Utils/CommandLineOpts.h
+21-204 files

LLVM/project cd6bc26bolt/include/bolt/Core BinaryContext.h, bolt/lib/Core BinaryContext.cpp

[BOLT] Key GlobalSymbols on MCContext-owned names to reduce memory (#214891)

BinaryContext::registerNameAtAddress registers every symbol name twice.
It first calls MCContext::getOrCreateSymbol(Name), which interns the
name in MCContext's symbol table (the MCSymbol owns the string via its
table entry). It then also stored the name in the GlobalSymbols map,
which was a StringMap<BinaryData *>. StringMap owns its keys, so each
global name was duplicated: one copy in MCContext and a second copy in
GlobalSymbols. Both grow with the number of symbols and, for large
binaries with long mangled names, this duplication is a meaningful
source of memory use during file object discovery.

This change makes MCContext the single owner of these name strings and
have GlobalSymbols merely reference them. GlobalSymbols becomes a
DenseMap<StringRef, BinaryData *> keyed on the MCContext-owned name
(MCSymbol::getName() of the symbol just created/looked up). No string is
copied into the map: each entry is a fixed-size (StringRef, pointer)
pair regardless of name length. Lookups (getBinaryDataByName, count) are
unchanged because DenseMap<StringRef> hashes and compares by content,

    [7 lines not shown]
DeltaFile
+7-4bolt/lib/Core/BinaryContext.cpp
+10-1bolt/include/bolt/Core/BinaryContext.h
+17-52 files

LLVM/project 503bfb4llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

[AMDGPU] Correct DS FIFO buffer size semantics

There was some ambiguity in how buffersize 0 and 1 are handled. The
correct semantics are:
- `BufferSize == 0`: unlimited, no FIFO stall
- `BufferSize == 1`: unbuffered, only one instruction in flight
- `BufferSize > 1`: buffered FIFO
DeltaFile
+9-7llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+13-102 files

LLVM/project ccc664cbolt/include/bolt/Utils Utils.h, bolt/lib/Core BinaryContext.cpp

[BOLT] Page out .dwo files (#214903)

Split-DWARF inputs at big binaries scale ship 100+ GiB of .dwo files.
BOLT opened a fair number of them during readDebugInfo, putting a lot of
pressure on the OS memory management: mmap'd reads always populate the
page cache; with every .dwo mapped at once those pages accumulated,
refaulted, and registered as memory pressure that got the process
oomd-killed.

Now, .dwo page-cache pages are reclaimed as soon as BOLT is done with
each file: madvise(MADV_PAGEOUT) on the live mapping, then
posix_fadvise(POSIX_FADV_DONTNEED) once it is unmapped. Controlled by
-drop-dwo-page-cache, OFF by default, as it is unlikely upstream will be
processing gigantic sets of dwo files.
DeltaFile
+68-2bolt/lib/Core/BinaryContext.cpp
+37-0bolt/lib/Utils/Utils.cpp
+11-0bolt/include/bolt/Utils/Utils.h
+116-23 files

LLVM/project 775dc9bbolt/include/bolt/Core BinaryContext.h, bolt/lib/Core BinaryContext.cpp

[BOLT] Create and release .dwo DWARF contexts incrementally (#214900)

BOLT opened a DWARFContext for every .dwo during
readDebugInfo and kept them all alive until teardown. On large
split-DWARF targets that is tens of GiB held resident through emission,
the point of peak RSS.

Make the DWOCUs map a lazily-populated cache instead:

* Use the newly added DWARFUnit::clearDWO()/hasDWO() to directly manage
DWARFUnit's DIE caching mechanism.
* BinaryContext::getDWOCU() opens a context on demand (keyed off a
stable DWOId -> skeleton CU map).
* Release contexts as soon as they are done with: all of them at the end
of readDebugInfo, and per-bucket at the DWARF rewrite merge point.
* Remove DWOCUs map, which became redundant and whose purpose can now be
served by the new id-to-skeleton map, and then fetching the split CU
from the skeleton via getNonSkeletonUnitDIE().


    [3 lines not shown]
DeltaFile
+110-52bolt/lib/Core/BinaryContext.cpp
+31-10bolt/include/bolt/Core/BinaryContext.h
+9-14bolt/lib/Rewrite/DWARFRewriter.cpp
+2-0bolt/lib/Rewrite/RewriteInstance.cpp
+152-764 files

LLVM/project 6f61ef9clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR][NFC] Fix loop op examples in CIROps.td (#216457)

### summary
The cir.while example had cond and body swapped, and several loop
examples used outdated cir.condition / cir.for syntax. Also add short
examples of the optional per-iteration cleanup region.

Generated by Grok 4.6, but manually reviewed.
DeltaFile
+24-8clang/include/clang/CIR/Dialect/IR/CIROps.td
+24-81 files

LLVM/project 7e5995dllvm/test/CodeGen/AMDGPU flat-saddr-atomics.ll llvm.amdgcn.wmma.imm.gfx1250.w32.ll

[AMDGPU] Improve the sequence for initial unclaused VMEM

Fixes LCOMPILER-2619.
DeltaFile
+250-250llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+232-232llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+196-196llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+183-183llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+174-174llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+166-166llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+1,201-1,201200 files not shown
+6,443-6,354206 files

LLVM/project a929515bolt/include/bolt/Utils Utils.h, bolt/lib/Core BinaryContext.cpp

[BOLT] Page out .dwo files

Split-DWARF inputs at big binaries scale ship 100+ GiB of .dwo
files. BOLT opened a fair number of them during readDebugInfo, putting
a lot of pressure on the OS memory management: mmap'd reads always
populate the page cache; with every .dwo mapped at once those pages
accumulated, refaulted, and registered as memory pressure that got the
process oomd-killed.

Now, .dwo page-cache pages are reclaimed as soon as BOLT is done with
each file: madvise(MADV_PAGEOUT) on the live mapping, then
posix_fadvise(POSIX_FADV_DONTNEED) once it is unmapped. Controlled by
-drop-dwo-page-cache, OFF by default, as it is unlikely upstream
will be processing gigantic sets of dwo files.
DeltaFile
+68-2bolt/lib/Core/BinaryContext.cpp
+37-0bolt/lib/Utils/Utils.cpp
+11-0bolt/include/bolt/Utils/Utils.h
+116-23 files

LLVM/project a888a81bolt/include/bolt/Core BinaryContext.h, bolt/lib/Core BinaryContext.cpp

[BOLT] Create and release .dwo DWARF contexts incrementally

BOLT opened a DWARFContext for every .dwo during
readDebugInfo and kept them all alive until teardown. On large
split-DWARF targets that is tens of GiB held resident through
emission, the point of peak RSS.

Make the DWOCUs map a lazily-populated cache instead:

 * Use the newly added DWARFUnit::clearDWO()/hasDWO() to directly
   manage DWARFUnit's DIE caching mechanism.
 * BinaryContext::getDWOCU() opens a context on demand (keyed off a
   stable DWOId -> skeleton CU map).
 * Release contexts as soon as they are done with: all of them at the
   end of readDebugInfo, and per-bucket at the DWARF rewrite merge
   point.
 * Remove DWOCUs map, which became redundant and whose purpose can
   now be served by the new id-to-skeleton map, and then fetching
   the split CU from the skeleton via getNonSkeletonUnitDIE().

    [5 lines not shown]
DeltaFile
+110-52bolt/lib/Core/BinaryContext.cpp
+31-10bolt/include/bolt/Core/BinaryContext.h
+9-14bolt/lib/Rewrite/DWARFRewriter.cpp
+2-0bolt/lib/Rewrite/RewriteInstance.cpp
+152-764 files

LLVM/project 334accallvm/include/llvm/DebugInfo/DWARF DWARFUnit.h, llvm/lib/DebugInfo/DWARF DWARFContext.cpp

[DebugInfo] Add DWARFUnit::clearDWO() (#214899)

Add DWARFUnit::clearDWO() so a skeleton unit can drop the DWO context it
owns without being destroyed itself. Also add DWARFUnit::getDWO() to
answer, without creating a new one, if that skeleton CU is currently
caching a DWO context.

For example, BOLT opened a DWARFContext for every .dwo during
readDebugInfo and kept them all alive until teardown. On large
split-DWARF targets that is tens of GiB held
resident. clearDWO()/getDWO() expose to users DWARFUnit's caching
capacity, allowing them to spontaneously drop the cache/look it
up/re-load it for memory management. To demonstrate this, in
llvm-dwarfdump we now make use of the same technique to avoid ballooning
peak RSS when dumping binaries with dwos. Whenever --debug-info --dwo is
used, during the loop dumping non-skeleton DIEs, we clearDWO as soon as
we're done with that unit. Testing on a large binary, this was shown to
reduce peakRSS from 50GB to 590MB.
DeltaFile
+17-5llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
+10-0llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h
+9-0llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
+36-53 files

LLVM/project fd19af1llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

Handle DS FIFO accounting edge cases

Saturate hardware-unit pressure decrements and treat buffer sizes zero
and one as disabling buffering to avoid underflow and inconsistent stall
costs.
DeltaFile
+4-5llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+6-72 files

LLVM/project 7c13a92llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll coexec-hazardrec-preRA.mir

[AMDGPU] Use DS latency for FIFO scheduling

Use instruction latency for DS hardware-unit cycle accounting so the FIFO
model can identify a full buffer. Add focused MIR coverage for the resulting
stall cost and scheduling decision, and regenerate the integration checks.

Change-Id: I2f4df2e97d145af4935872dbd43108e1b55077ab
DeltaFile
+48-0llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
+5-5llvm/test/CodeGen/AMDGPU/coexec-hazardrec-preRA.mir
+4-4llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+61-94 files

LLVM/project 82ef03fllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Merge conflicts

Change-Id: I33564a1e5d14f3b53577cb463ba2cb3a7993fd24
DeltaFile
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+4-31 files

LLVM/project 7fe0afdllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h

[AMDGPU] Add stalls for DS FIFO buffer

Change-Id: I73e56da97a931349e0655e4e20b24aeb97920647
DeltaFile
+41-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+41-5llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+82-112 files

LLVM/project 8a8f9f6llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h

Address Review comments

Change-Id: I6972e887edd5db44ee9bcaed1f79e0c9933f611e
DeltaFile
+17-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+6-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+23-42 files

LLVM/project 29cb18dllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

Claude Code review

Change-Id: Id4983ca59270c8bb2d261d38a6e7f2483c9d237e
DeltaFile
+18-4llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+19-42 files

LLVM/project 80c4762llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Typo

Change-Id: I8b8da8a07be84506483f474d0a5e10ad79178c15
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+1-11 files

LLVM/project a0e9910utils/bazel .bazelrc MODULE.bazel.lock, utils/bazel/llvm-project-overlay/libc BUILD.bazel

[bazel] Add support for targeting wasm with emsdk (#217145)

This allows producing wasm binaries of tools that can then be run in the
browser.
DeltaFile
+817-11utils/bazel/MODULE.bazel.lock
+27-4utils/bazel/llvm-project-overlay/llvm/config.bzl
+13-0utils/bazel/.bazelrc
+7-1utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+4-2utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2-2utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h
+870-202 files not shown
+872-218 files

LLVM/project 38daf36llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv masked-load-vl-predicatable.ll

[RISCV] Turn certain cases of masked.load into vp.load + vp.merge
DeltaFile
+64-52llvm/test/CodeGen/RISCV/rvv/masked-load-vl-predicatable.ll
+59-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+123-522 files

LLVM/project 607991borc-rt/lib/executor NativeDylibManager.cpp ExecutorProcessInfo.cpp, orc-rt/lib/executor/Unix NativeDylibAPIs.inc

[orc-rt] Use StringOutputStream in executor error messages (#217167)

Replace std::ostringstream and std::to_string in the executor's
error-message construction with orc_rt::StringOutputStream, dropping
<sstream> (and its iostreams + locale machinery) from the executor,
which runs on-target including on freestanding platforms.

Converted SimpleNativeMemoryMap.cpp, ExecutorProcessInfo.cpp, and
Unix/NativeDylibAPIs.inc; NativeDylibManager.cpp no longer needs to
include <sstream> for the latter. Messages that only feed an error are
built from a StringOutputStream temporary; one all-literal message drops
the stream entirely.

Hex values now carry a "0x" prefix (StringOutputStream::hex always emits
one), where the old std::hex produced bare digits. No test depends on
the exact message text.
DeltaFile
+26-26orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
+7-6orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
+4-3orc-rt/lib/executor/ExecutorProcessInfo.cpp
+0-2orc-rt/lib/executor/NativeDylibManager.cpp
+37-374 files

LLVM/project c3af148flang/lib/Lower OpenACC.cpp, flang/test/Lower/OpenACC acc-present-cuda-device.f90

[flang][Lower] Rewrite present of device variable to deviceptr (#217164)

A cuda device variable is always "present" on the device. Rewrite such
occurrences to deviceptr in the front end while we still have the
information about which variable is a cuda device variable.
DeltaFile
+50-16flang/lib/Lower/OpenACC.cpp
+55-0flang/test/Lower/OpenACC/acc-present-cuda-device.f90
+105-162 files

LLVM/project 8f7a36fllvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp, llvm/test/CodeGen/AMDGPU packed-u64.ll pk-lshl-add-u64.ll

[AMDGPU] Re-implement splat scalar handling for packed 64-bit ops (#216896)

In instruction selection, we identify the splat scalar pattern and set opsel to 0.
The legalizer is responsible for moving SGPRs to VGPRs if opsel is not 0.
A future optimization could save SGPR copies for upper lanes since hardware
only reads the first SGPR.

This new implementation fixes the issue when an uniform value has to be
computed by a VALU-only instruction, and thus the result is in a VGPR. This will
lead to the missing data in the upper lane with the previous approach.
DeltaFile
+123-0llvm/test/CodeGen/AMDGPU/packed-fp64-uniform-vgpr-splat-operand.ll
+25-15llvm/test/CodeGen/AMDGPU/packed-fp64.ll
+5-2llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
+5-1llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+1-0llvm/test/CodeGen/AMDGPU/packed-u64.ll
+159-185 files

LLVM/project 806dddallvm/cmake/modules AddSphinxTarget.cmake

[docs] Parallelize Sphinx builds by default

Sphinx supports building documents in parallel with -j. Default LLVM_PARALLEL_SPHINX_JOBS to half the logical cores, rounded up, using CMake's native host system information query, and pass it to sphinx-build. If LLVM_PARALLEL_SPHINX_JOBS is explicitly set empty, omit the -j flag.

3-run hyperfine comparison for clean docs-llvm-html builds, removing the html output and doctree cache before each timing run:

  before (no sphinx -j): 97.897 s +/- 1.231 s
  after (-j 8):          52.334 s +/- 15.348 s
  speedup:               1.87x +/- 0.55x

Validation:
- cmake -S llvm -B build-docs-preview-all
- ninja -C build-docs-preview-all docs-llvm-html
- hyperfine --runs 3 comparing docs-llvm-html before/after
- git diff --check
- scanned touched file for internal-only markers
DeltaFile
+13-0llvm/cmake/modules/AddSphinxTarget.cmake
+13-01 files

LLVM/project b1f7419llvm/include/llvm/CodeGen/GlobalISel Legalizer.h, llvm/lib/CodeGen/GlobalISel Legalizer.cpp

[GISel][NewPM] Port Legalizer

Standard NewPM pass porting.

Reviewers: arsenm, vikramRH

Pull Request: https://github.com/llvm/llvm-project/pull/217046
DeltaFile
+71-28llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
+35-17llvm/include/llvm/CodeGen/GlobalISel/Legalizer.h
+3-3llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
+2-2llvm/test/CodeGen/MIR/AArch64/deactivation-symbols.mir
+1-1llvm/lib/Target/X86/X86TargetMachine.cpp
+1-1llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+113-5212 files not shown
+125-6318 files