[flang][NFC] Allow simplify-region-lite to run on any op (#220698)
The pass only walks the regions of getOperation(). Pinning it to
ModuleOp forced a single liveness lattice over the whole compile unit
and blocked scheduling it under a nested pass manager. Drop the
ModuleOp constraint so callers can run it per IsolatedFromAbove op.
Existing module-level addPass() uses are unchanged.
[offload][nfc] Extract libomptarget infrastructure into libompaccsupport (#213784)
libompaccsupport will become the support library for both OpenMP and
OpenACC. This patch extracts the files that will become part of it.
Currently it only moves the files and the build configuration is
unchanged.
Next patches will start refactoring libompaccsupport to flesh out the
subset of the infrastructure that will be shared between OpenMP and
OpenACC in small verifiable chunks while maintaining libomptarget's
existing behaviour.
Gradually adding the libacctarget implementation that uses
libompaccsupport will also follow.
[VPlan][Predicator] Preserve some uniform control flow
Implements "Partial Control-Flow Linearization" by Simon Moll and
Sebastian Hack.
That should allow implementation of an alternative to
https://github.com/llvm/llvm-project/pull/141900 based on this
functionality (see BOSCC in the paper).
[VPlan] Use compact RPOT instead of just RPOT
This is necessary for the future partial linearization change, but I
wanted to commit this bit independently because it changes some tests on
itself and could potentially provide more blend optimization
opportunites (at least I hoped) but that didn't seem to happen.
[VPlan] Make blend operands non-reorderable to optimize their masks in predicator
Sort the incoming edges according to RPOT order so that we could use
simpler source block mask instead of the edge mask.
[orc-rt] Add darwin subdir for regression tests. (#220754)
All tests in the new subdirectory are implicitly gated on lit's
"system-darwin" feature flag.
Move check-rt-process-info.test into the darwin subdirectory and drop
its "system-darwin" guard, since it will now be covered by the darwin
directory's guard.
[MLIR][XeGPU] Promote mixed-size vector.shuffle in xegpu-vector-linearize (#217141)
Linearizing an insert of a narrow chunk into a wider tile produces a
`vector.shuffle` whose operands have different lengths:
%0 = vector.insert_strided_slice %chunk, %tile {offsets = [1, 0],
strides = [1]}
: vector<4xbf16> into vector<8x4xbf16>
// becomes shuffle(vector<32xbf16>, vector<4xbf16>)
MLIR permits that, but LLVM and SPIR-V shuffles require both operands to
have the
same type, so `convert-vector-to-llvm` falls off its fast path and emits
one
`extractelement` plus one `insertelement` per result element. In a
workgroup-level
mxfp GEMM the linearizer emits ~1000 such shuffles, and scalarizing them
accounts
for roughly 70% of the emitted LLVM IR.
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[Offload] Build LLVMOffloadKernel with add_library (#220748)
Depending on system and cmake configuration, LLVMOffloadKernel cannot
find LLVMOffload when testing because they live in different directories
in the build.
This patch aligns LLVMOffloadKernel's library build/install directory
configuration with LLVMOffload's, which makes sure it can always be
found.
The cause is that llvm_add_library adds some implicit handling which can
throw off the directories we need (see
3383f0d6fe01374b91845e7cd3ee949594c4bfc6)
[AMDGPU] Track BUFFER_INV during waitcnt insertion (#220694)
Currently SIInsertWaitcnts doesn't mark `BUFFER_INV` instructions as
incrementing `VM_CNT`, though according to gfx942/gfx950 ISA `VM_CNT`
does increment. This PR teaches SIInsertWaitcnts to handle `BUFFER_INV`,
akin to how `GLOBAL_INV` is handled for gfx12+. No changes in behavior
are made for gfx12+ codegen.
Similar to `GLOBAL_INV` the implementation elides waits when inv
instructions are the only pending load events because they do not write
VGPRs.
The motivation is to use `BUFFER_INV 0` as a nop to increment `VM_CNT`
in branches to allow relaxed `s_waitcnt vmcnt` instructions (coming in a
separate PR).
[RISCV] Lower `CONVERT_FROM_ARBITRARY_FP` of Float8E5M2 with Zvfofp8min (#220132)
The new(-ish) `llvm.convert.from.arbitrary.fp` intrinsics (`ISD::
CONVERT_FROM_ARBITRARY_FP`) can be lowered into `vfwcvtbf16.f.f.v` from
Zvfofp8min if the input operand is a Float8E5M2 / Float8E4M3 vector
(represented by i8 vector in LLVM), and producing a bf16 vector result.
This patch adds such lowering for the Float8E5M2 type
(SelectionDAGBuilder hasn't supported the Float8E4M3 variant of
`CONVERT_FROM_ARBITRARY_FP`).
Note that although Zvfofp8min does not require Zvfbfmin or Zvfbfa[^1],
in reality it'll be pretty difficult to implement that (lower of
`vfwcvtbf16.f.f.v` even though there is only no bf16 vector support) in
legalization. So for this patch, I emit `vfwcvtbf16.f.f.v` only if both
Zvfofp8min _and_ bf16 vector support are present.
[^1]: Rationale:
https://github.com/riscv/riscv-isa-manual/pull/2979#issuecomment-4320773526
