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[gn build] Port c59c19bf5921 (#194167)

[gn build] Port a693efcc40b1 (#194166)

[gn build] Port 2f28e1db535b (#194165)

[clang] Make serenity.cpp more independent of the host (#193981)

Tests matching crt files previously relied on the host system not using
the same file paths as Serenity. This breaks on AIX, as both systems use
`/usr/lib/crt0.o`.

Redirect most tests to an empty sysroot so they match only on the
filename and remain independent of the host system. Also add a test that
verifies crt files can be found in a normal sysroot.

[clang][bytecode] Fix crash involving labels and null sub (#194115)

For null pointers, getDeclDesc() may return null, so we can't call
asExpr() on it.

[flang][OpenMP] Replace llvmOmpClause with llvm::omp::Clause (#194162)

Both types, llvmOmpClause (alias of const llvm::omp::Clause) and
llvm::omp::Clause are in use, let's just stick with one.

[NewPM] Adds a port for AArch64SIMDInstrOpt (#188177)

Adds a port for AArch64SIMDInstrOpt

- Refactored to extract base logic as Impl.
- **Note**: Moved theI nstruction Replacement Table and cross-function
cached maps as members of the Impl class.
- **Note**: Updated `InstReplInfo::RC` to be a pointer rather than a
stack object, because we're putting it into MRI
[here](https://github.com/llvm/llvm-project/blob/704c60fe9110256d2698d8e56b8c44ec5d1e733f/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp#L532).
- Renamed existing pass with "Legacy" suffix and updated references
- Added NewPM pass AArch64SIMDInstrOptPass
- Updated pass type to `aarch64-simd-instr-opt` (prev:
`aarch64-simdinstr-opt`)

No existing `.mir` tests to update.

[RISCV] Remove codegen for vp.icmp (#193606)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off vp.icmp from #179622

[libc++] P4144R1: Remove `span`'s `initializer_list` constructor for C++26 (#191428)

Reverts P2447R6 (implemented in
dbbeee6b8357c5a68543f612f3b2b607f1911b4c). Some test cases that indicate
"old" behavior mentioned in P2447R6 are kept.

[flang][OpenMP] Replace llvmOmpClause with llvm::omp::Clause

Both types, llvmOmpClause (alias of const llvm::omp::Clause) and
llvm::omp::Clause are in use, let's just stick with one.

[mlir][math] Add rounding modes to `math.fma` (#192839)

Rounding modes have recently been added for `arith` FP operations
(#188458). This commit adds rounding modes to `math.fma`, following the
same design as for `arith` FP operations.

If a rounding mode is present, the LLVM lowering produces
`llvm.intr.experimental.constrained.fma`.

In the absence of a rounding mode, the rounding behavior is deferred to
the target backend.

Assisted-by: claude-opus-4.7-thinking-high

[CIR] Add support for atomic-to-non-atomic cast (#193784)

This patch adds support for atomic-to-non-atomic casts in CIR.

Related to #192319 .

Assisted-by: Github Copilot / GPT-5.4

[RISCV] Expand vp.shl, vp.lshr, vp.ashr (#193603)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off 3 intrinsics from #179622. The codegen is left in for
now as other places can generate those nodes. performVP_TRUNCATECombine
needs to be updated to match the plain non-VP node when forming vaaddu.

[RISCV] Remove codegen for vp_fp_round, vp_fp_extend (#193219)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off 2 intrinsics from #179622. vp.fpext was previously
expanded in #190589, we only need to expand vp.fptrunc in this PR.

[SCEVExp] Use Builder.CreateBinOp in InsertBinOp. (#154148)

SCEVExpander's builder already uses InstSimplifyFolder. Use it to
construct binary ops via CreateBinOp instead of BinaryOperator::Create.

This helps to simplify away a few more instructions during SCEV
expansion.

PR: https://github.com/llvm/llvm-project/pull/154148

[SLP][NFC]Rename test, add other non-vectorizable inst candidates tests, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194153

[flang][OpenMP] Clear branch labels in all program units (#194152)

The semantic check for branching in or out of an OpenMP construct did
not reset its label information in some cases, leading to false positive
error messages in valid Fortran code.

[clang][lit] Substitute cir-opt when CIR is enabled (#194129)

Fix the CIR lit substitution introduced by #193665 to use `cir-opt`.

format

[flang][OpenMP] Clear branch labels in all program units

The semantic check for branching in or out of an OpenMP construct
did not reset its label information in some cases, leading to false
positive error messages in valid Fortran code.

[NFC][WebAssembly] strided-int-mac.ll - regenerate test checks (#194146)

Use update_llc_test_checks regeneration

[GlobalISel] Remove duplicate patterns. NFC (#194131)

This looks like a merge conflict from #194010 cause a duplicate line to
appear, causing warning about constant_fold_cast_op and fabs_fneg_fold
being used multiple times.

[SLP][NFC]Add a test with non-vectorizable functions/intrinsics, but vectorizable operands



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194143

[AVR] Fix allocating DREGS (#193908)

[ARM][MVE] Transform sext and zext of i1 buildvector (#192519)

This helps by avoiding the difficult predicate generation in scalar, using
natural extends to all-zero or all-ones in scalar as opposed to re-extending
them in vector registers.

[AArch64] Use `AArch64ISD::UADDLP` for manual widening adjacent arithmetic (zext/shuffle combination) (#189255)

[Clang][RISCV] Introduce OFP8(E4M3, E5M2) RISC-V vector types (#191349)

Currently there's no OFP8 scalar type supported in both clang and llvm
type system, the vector OFP8 RVV types are lowered to i8 llvm types for
now.
The reason to support only clang type is because of intrinsics
definition capability. If we make the clang type also using uint8 vector
types, it's not able to distinguish between E4M3 type and E5M2 type so
that we have to append additional type suffix to it.
intrinsic spec update pr:
https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/pull/432
vreinterpret intrinsic PR:
https://github.com/llvm/llvm-project/pull/191626

DONT MERGE: We have to get the intrinsic spec merged first to be able to
make zvfofp8min change

[libc++] Fix constant_wrapper::operator() (#193573)

As Tomasz pointed out on mattermost, 
given

```cpp
template <class T>
struct MustBeInt {
  static_assert(std::same_as<T, int>);
};

struct Poison {
  template <class T>
  constexpr auto operator()(T) const noexcept -> MustBeInt<T> {
    return {};
  }
};

std::cw<Poison{}>(std::cw<5>);

    [59 lines not shown]

[ARM][MVE] Add tests for sext and zext of i1 buildvector. NFC (#194141)

[ORC] Wrap unconditional dbgs() in LLVM_DEBUG in JITLoaderPerf (#188903)

Fixes #188900