[lldb-dap] Return raw stop info from exceptionInfo (#231760)
lldb-dap folds the thread's extended stop info and the process's
extended crash information into the exceptionInfo description as
formatted text. Clients that want interpret these themselves currently
have to parse them back out.
Return both as raw JSON in two new lldb-dap extension fields,
`$__lldb_stopReasonExtendedInfo` and `$__lldb_extendedCrashInformation`.
rdar://188761988
[Clang][counted_by] Load the count through unions by byte offset (#228309)
`getGEPIndicesToField()` indexed into a union with 0 and kept walking the
counter's struct field numbers, but the union's IR type is its largest
member, so the count was loaded from inside that member instead.
In Linux, `landlock_domain` hits this and FORTIFY panics on every nested
`landlock_restrict_self()` on kernel 7.3.0-rc5-next as of this writing.
I ran into this bug when trying to daily drive the aforementioned
kernel.
Below is a reduced version of `landlock_domain`. The `work` member
stands in for the kernel's `struct work_struct`, which is larger than the
anonymous struct holding the count, so it becomes the union's IR type.
```c
struct dom {
void *rules[3];
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[WebAssembly] Preserve tail-call pseudos during stack-protector splitting (#230073)
WebAssembly tail calls use a parameter/result pseudo-instruction pair
that is combined during FinalizeISel. Before that, stack-protector
insertion looks for the first terminator so it can move the terminating
sequence into the success block. The tail-call pseudos lack those flags,
causing an assertion in findSplitPointForStackProtector.
This reproduces with an assertions-enabled build:
```llvm
declare i32 @callee(i32)
define i32 @caller(i32 %x) sspreq {
%r = tail call i32 @callee(i32 %x)
ret i32 %r
}
```
```sh
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[scudo] Re-check freelist before populating blocks in popBlocksWithCV (#231750)
In popBlocksWithCV, the region freelist may become non-empty before the
thread calls populateFreeListAndPopBlocks. This can happen in two
scenarios:
1. Another thread may push blocks or finish
populateFreeListAndPopBlocks() in the window between releasing FLLock in
popBlocks() and reacquiring it in popBlocksWithCV().
2. releaseToOSMaybe() holds MMLock while temporarily extracting
GroupsToRelease with FLLock unlocked, and merges those groups back into
BlockList before releasing MMLock.
When this does happen, popBlocksWithCV unconditionally calls
populateFreeListAndPopBlocks, permanently growing the region mapping and
BatchClassId freelist metadata.
The fix here is to re-check popBlocksImpl() under FLLock before setting
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[lld][MachO] Don't create thunkMap entries for branches without a thunk (#231594)
This is part of the ld64.lld performance improvements tracked by
#222068.
TextOutputSection::finalize() created a thunkInfo for every thunkMap
entry found using []. However, the DenseMap::operator[] inserts an empty
default constructed entry whenever the key is not in thunkMap.
This led to millions of unnecessary empty entries. This change adds a
TextOutputSection::findThunkInRange that first uses find() to check if
the thunk exists.
It then calls getThunkInRange(), so the reads in finalize() still
function the same, just without adding a default entry that counted as a
cache miss anyways.
This commit is output preserving.
[sanitizer_common] Implement address sanitizer on AIX: process memory mapping (#138537)
Implement process memory mapping on AIX using `sys/procfs.h`. We don't
have direct access to the full path in the case of user libraries or
executables, so we use the path `/proc/<pid>/object/<object_id>` for
now.
Issue: https://github.com/llvm/llvm-project/issues/138916
---------
Co-authored-by: Midhunesh <midhunesh.p at ibm.com>
[CIR] Move records through memory in x86_64 call lowering (#231663)
CIR lowers a union to its storage type, so moving one as an SSA value
can drop bytes. An x86_fp80 member stores only 10 of its 16 bytes, for
example. The calling-convention rewriter now passes records through
memory at every coercion site, the way classic CodeGen does. That lets
us drop the union check #230302 added, which broke std::format.
Assisted-by: Cursor / Claude Opus 5.5
[AArch64] Add pre-commit tests for SVE AND-NOT folding
Add pre-commit tests demonstrating missed BIC selection for SVE AND-NOT
operations. Record the current NOT plus AND sequences for all-active and
undefined NOT results, and for intrinsic pairs with matching predicates.
Cover merging inactive lanes, commuted operands, all integer element
widths, and multiple uses of NOT. Include negative cases where folding
would change defined inactive lanes.
Both test files pass with SVE, SVE2p2, and streaming SME, with machine
instruction verification enabled.
[AArch64] Combine SVE AND-NOT operations into BIC
Fold a scalable-vector AND of an SVE NOT into BIC when the NOT predicate
is all-active or its inactive lanes are undefined.
Also fold SVE AND-NOT intrinsic pairs with matching predicates before
lowering discards the AND predicate. The NOT passthru is irrelevant in
the active lanes, allowing defined passthru values to fold as well.
Preserve the first operand's inactive lanes for merging AND, and only
commute the undef form. Keep standalone NOTs available for predicated
instruction selection.
Update the pre-commit tests to show BIC replacing NOT plus AND, while
retaining the negative cases. Both test files pass with SVE, SVE2p2, and
streaming SME, with machine instruction verification enabled.
[RISCV][P-ext] Use ISD::AVGSUBFLOOR(S/U) for (p)asub(u).
This replaces RISCVISD::ASUB(U) with ISD::AVGSUBFLOOR(S/U).
Co-Authored-By: Claude Sonnet 5.5 <noreply at anthropic.com>
RuntimeLibcalls: Define vector math libcall signatures in tablegen (#232005)
Give vector math libcalls a signature in tablegen. The vector modf,
sincos and sincospi types now come from the generated signature instead
of being manually constructed, though the attributes are still manually
applied.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[BoundsSafety][Sema] Disallow using a bitfield with __builtin_counted_by_ref() (#231591)
A counter that's a pointer to a bitfield breaks assumptions in
'__builtin_counted_by_ref', which returns a pointer to the counter, but
a bitfield cannot have its address taken causing an ICE.
Link: https://github.com/llvm/llvm-project/pull/228309#pullrequestreview-5494375815
[LV] Require the preheader to be terminated by an unconditional branch. (#232091)
The preheader terminator gets replaced when creating the vector loop. A
preheader terminated by an indirectbr or a switch with a single
destination passes the existing preheader check, but crashes when
executing the plan
This fixes crashes on the added tests in both inner and outer loop
paths.
TableGen: Avoid linear search for register class names
Inferring register classes checked whether a name was already used by
walking the list of all register classes. AMDGPU has thousands of
register classes, so this was a large part of building the register
bank. Keep a set of the names instead.
The 8 AMDGPU tablegen runs that build the register bank each execute
8% to 12% fewer cycles.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[CodeGen] Report an error for a direct inline asm output in memory
An inline asm output returned by value has no memory to write to, yet a
constraint such as "=rm" picks memory, the most general constraint, as
does "=m". SelectionDAG asserted on that ("Can only indirectify direct
input operands!"), and GlobalISel dereferenced a null pointer. Clang
never emits such an output, since it passes the address of a memory
output, but other IR can. Report "cannot handle direct memory outputs
yet for constraint 'm'" instead, like the other inline asm errors there.
Assisted-by: Claude Opus 5.5
[TargetInstrInfo] Fix folding inline asm operands next to tied operands
foldInlineAsmMemOperand() swapped a register operand for the target's
memory operands with MachineInstr::removeOperand(), which asserts when a
later operand is tied, because moving it would break the tie. Inline asm
lists every input after every output, so folding any operand that comes
before another tied pair asserted, e.g. an "rm" input followed by the
input of a "+r" operand, or one of two "+rm" operands. Without
assertions, the moved operands kept stale tie indices. Untie the
operands, rebuild the operand list, and re-tie the remaining pairs at
their new positions.
It also gave up when the register appears in more than one operand, e.g.
one value passed to two "rm" operands, which left the greedy allocator
unable to spill that value at all. Fold every such operand into the
stack slot.
Finally, take MayLoad from the folded operands rather than from every
read of the register: a folded def whose tied use is another virtual
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[MIR] Serialize the "foldable" inline asm register operand flag
The symbolic MIR syntax for inline asm operand flags dropped
InlineAsm::Flag's RegMayBeFolded bit, which marks a register operand
(from an "rm" constraint) that the register allocator may fold to a
stack slot. Printing MIR and parsing it back therefore silently changed
what the allocator was allowed to do, e.g. with -stop-before and
-run-pass, and a test could only set the bit through a raw numeric flag.
Print the bit as a trailing "foldable", as MachineInstr::print() already
does, and parse it back. A tied use stores its matched operand number in
the same bits, so it never prints the marker.
Assisted-by: Claude Opus 5.5
