[clangd] Resolve __builtin_offsetof designator components precisely (#194407)
Building on the new TraverseOffsetOfNode hook in RecursiveASTVisitor and
the OffsetOfNode DynTypedNode kind, teach SelectionTree, FindTarget, and
the explicit-references collector to address each designator component
individually. Cursor positions inside a nested designator (for example
the 'B' in __builtin_offsetof(A, B.c)) now resolve to the corresponding
field instead of always picking the innermost component.
- SelectionTree: wrap each OffsetOfNode visit in traverseNode so it
becomes a selectable node alongside its enclosing OffsetOfExpr.
- FindTarget::allTargetDecls: resolve OffsetOfNode (Field kind) to its
FieldDecl, and drop the OffsetOfExpr fallback so non-component
selections do not guess a field target.
- ExplicitReferenceCollector: emit one ReferenceLoc per component via a
new VisitOffsetOfNode hook, replacing the manual component loop in
refInStmt.
Tests:
[12 lines not shown]
[AMDGPU][MC] update USER_SGPR_COUNT bits for GFX1250 (#192579)
When we work on the triton kernel with tensor descriptor created on the
host side, there is a error message `amdgpu_user_sgpr_count smaller than
than implied by enabled user SGPRs`.
After some debugging, we find the `USER_SGPR_COUNT` is not updated with
GFX125 and this patch updates it for USER_SGPR_COUNT from
https://llvm.org/docs/AMDGPUUsage.html#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx12-table.
On GFX125, COMPUTE_PGM_RSRC2::USER_SGPR_COUNT is 6 bits wide. The MC
helper S_00B84C_USER_SGPR only masks to 5 bits; when the true user SGPR
count is 32 or more, the masked value wraps (e.g. 32 -> 0).
`AMDGPUAsmPrinter` then emits a .amdhsa_user_sgpr_count with 0, that
disagrees with the implied count from enabled user SGPRs (including
kernarg preload), and finally assembling llc output with `llvm-mc` fails
in `AMDGPUAsmParser`
---------
Co-authored-by: Shilei Tian <i at tianshilei.me>
[clang][Fuchsia] Factor getFuchsiaDefines out of FuchsiaTargetInfo class (#194775)
Most of the template class's getOSDefines definition is not
template-dependent, so move it to a shared subroutine that's
outside the header file and reused by all the FuchsiaTargetInfo
instantiations.
[mlir][xevm] Fix greedy rewriter crash in HandleVectorExtractPattern matches shuffles on block arguments (#192213)
`HandleVectorExtractPattern` could report `success()` without rewriting
the IR when `llvm.shufflevector` extracted a contiguous slice from a
**block argument** (no defining op). The greedy rewriter’s expensive
checks then aborted with *“pattern returned success but IR did not
change”*.
The pattern only performs work when the shuffle’s operand is defined by
another op (`FPExt`, `FPTrunc`, `bitcast`, nested `shufflevector`, or
`load`). For operands like function arguments, `getDefiningOp()` is
null, so nothing is rewritten; the function still fell through to
`return success()` without changing the IR and would crash when
`MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS` is on. `mlir-opt
--convert-xevm-to-llvm --split-input-file
mlir/test/Conversion/XeVMToLLVM/xevm_mx-to-llvm.mlir` no longer hits the
fatal error.
Assisted-by: Cursor (Composer 2)
[RISCV] Rename rvp-ext-rv32/64.ll to rvp-simd-32/64.ll. Shorten check prefixes. NFC (#194770)
The rv32/rv64 here were the length of the vector types. The
rvp-ext-rv32.ll test has rv32 and rv64 RUN lines. Rename to make this
clearer.
I want to add rv32 RUN lines to the rvp-simd-64.ll, but we need to fix
some crashes first.
[CodeGen] Use SmallMapVector for SpillPlacement::Node::Links (#194653)
Previously, `SpillPlacement::Node::Links` was implemented as a
`SmallVector` of `(Weight, BundleNo)` pairs.
This patch replaces the `SmallVector` with a `SmallMapVector<unsigned,
BlockFrequency, 4>`, which stores `(BundleNo, Weight)` pairs. This
allows for more efficient lookups and weight accumulations when multiple
links to the same bundle are added.
Reapply "Reland "[llvm-profgen] Add support for ETM trace decoding"" … (#194730)
…(#194695)
This relands the original commit
e3bd61890e68303a33fdd33fbdd9abeda1037450 (#191584).
The original change was reverted in the following commits:
1) ec9d7d18bdfe21c30c94c02f14f3613f7b69a17b (#194087)
2) c26ae41c8765fdd073c71061f21a83a161598901 (#194695)
This reland incorporates the following fixes:
1) Change LLVM_ENABLE_OPENCSD to default to OFF (opt-in).
2) Parse the OpenCSD version from ocsd_if_version.h and gate OpenCSD
support on a minimum version of 1.5.4 to avoid compilation errors.
[2 lines not shown]
[WebAssembly] Fix -Wunused-function (#194776)
After 4aee20b8caa9b8477aef94d10c37b2f00805de07, getBBName is only used
within an assertion so mark it [[maybe_unused]] so it does not cause a
-Wunused-function warning in non-asserts builds.
[Github] Disable prune-unused-branches workflow (#194773)
It decided to delete 237 branches today which is probably not correct
and at least one of them was tied to an open PR which is definitely not
correct, so disable for now until we can investigate fully.
[ORC] Move JITLinkMemoryManager ownership out of ExecutorProcessControl. (#192665)
Removes the JITLinkMemoryManager pointer and getMemMgr() accessor from
ExecutorProcessControl, replacing them with a
createDefaultMemoryManager() virtual factory method. This follows the
same decoupling pattern applied to DylibManager and MemoryAccess in
earlier patches.
JITLinkMemoryManager ownership moves to the client:
- LLJIT gains a MemMgr member and a MemoryManagerCreator builder hook.
- EPCIndirectionUtils takes a JITLinkMemoryManager& parameter.
- LinkGraphLinkingLayer and ObjectLinkingLayer lose their no-arg
constructors (MemMgr is now required).
- SimpleRemoteEPC::Setup is removed; custom memory manager selection now
happens at the client level rather than during EPC setup.
[orc-rt] Remove explicit addSimpleNativeMemoryMap call. NFCI. (#194766)
The SimpleNativeMemoryMap::Create call two lines below will add this
interface anyway, so the explicit call is redundant.
[WinEH] Diagnose SEH object unwinding in skipped __except bodies (#187718)
When an SEH __except block has no EH branches, CodeGen skips emitting the handler
body. This also skipped the existing diagnostic for local variables that require destruction
under C++ exceptions
Diagnose those variables before dropping the skipped handler body, and add coverage
for both sync and async exception modes
[TableGen] Fix indentation of generated code. NFC
This line was missing the indent(4) call. Noticed while looking at the
generated code.
Pull Request: https://github.com/llvm/llvm-project/pull/194765
[RISC-V][RVY] Add a DataLayout component for CHERI capabilities
This adds a new pointer address space to the data layout when RVY is
enabled, making use of the new 'e' flag for pointers with
[external state](https://github.com/llvm/llvm-project/pull/105735).
I chose address space 200 since that is what has been used in the
downstream CHERI forks for the past decade and therefore makes it slightly
easier to upstream tests, etc. but am happy to use any other value if that
is preferred. We can look at the ABI name parameter to detect
pure-capability ABIs, so this does not support the "hybrid" CHERI case that
is supported downstream where capability registers are supported (i.e.
the AS200 pointer attributes exist in the data layout), but the default
address spaces are still integers instead of AS200.
to handle the "hybrid" case where only some pointers use Y registers.
Reviewed By: topperc, lenary
Pull Request: https://github.com/llvm/llvm-project/pull/177249
