[CIR] Add Commutative/Idempotent traits to binary ops (#185163)
Add missing MLIR traits to CIR binary operations:
- AndOp, OrOp: Commutative, Idempotent
- AddOp, MulOp, XorOp, MaxOp: Commutative
Add these ops to the CIRCanonicalize pass op list so trait-based
folding is exercised by applyOpPatternsGreedily.
[CIR] Add cir.min op and refactor cir.max lowering
Add cir.min operation for integer minimum computation. Refactor cir.max
lowering into a shared lowerMinMaxOp template reused by both ops. Includes
lowering tests for signed, unsigned, and vector types, plus canonicalization
tests.
[CIR] Split CIR_UnaryOp into individual operations
Split the monolithic cir.unary operation (which dispatched on a
UnaryOpKind enum) into four separate operations: cir.inc, cir.dec,
cir.minus, and cir.not.
This follows the same pattern used when cir.binop was split into
individual binary operations (AddOp, SubOp, etc.).
Changes:
- Add CIR_UnaryOpInterface with getInput()/getResult() methods
- Add CIR_UnaryOp and CIR_UnaryOpWithOverflowFlag base classes
- Define IncOp, DecOp, MinusOp, NotOp with per-op folds
- Add Involution trait to NotOp for not(not(x)) -> x folding
- Replace createUnaryOp() with createInc/Dec/Minus/Not builders
- Split LLVM lowering into four separate patterns
- Split LoweringPrepare complex-type handling per unary op
- Update CIRCanonicalize and CIRSimplify for new op types
- Update all codegen files to use bool params instead of UnaryOpKind
[6 lines not shown]
[CIR] Remove cir.unary(plus, ...) and emit nothing for unary plus
Traditional codegen never emits any operation for unary plus — it just
visits the subexpression as a pure identity at the codegen level. Align
CIRGen with this behavior by removing Plus from UnaryOpKind entirely
and having VisitUnaryPlus directly visit the subexpression with the
appropriate promotion/demotion handling.
[CIR] Add Commutative/Idempotent traits to binary ops
Add missing MLIR traits to CIR binary operations, matching the arith
dialect conventions:
- AndOp, OrOp: Commutative, Idempotent (fixes FIXME)
- AddOp, MulOp, XorOp, MaxOp: Commutative
Add these ops to the CIRCanonicalize pass op list so trait-based
folding is exercised by applyOpPatternsGreedily.
Update testFloatingPointBinOps in binop.cpp to use computed values,
preventing DCE of the now-canonicalized ops.
[StructurizeCFG] Fix incorrect zero-cost hoisting in nested control flow (#183792)
hoistZeroCostElseBlockPhiValues() hoists zero-cost instructions from
else blocks to their common dominator with the then block. When the
merge point has additional predecessors beyond the simple if-else
pattern, the hoisted instruction ends up in a dominator that feeds
a Flow phi on every edge, including edges where the else block was
never taken. simplifyHoistedPhis() then replaces poison entries in
those Flow phis with the hoisted value, causing it to leak into
unrelated paths.
This manifests as miscompilation in sorting kernels compiled with
code coverage: the PGO counter blocks create deeply nested CFGs
where the hoisted shufflevector (used for swapping sort keys)
reaches the no-swap path, corrupting sort results.
Fix by requiring a simple if-else CFG shape before hoisting: ThenBB
must branch directly to ElseSucc and ElseSucc must have exactly 2
predecessors. This matches the structure that simplifyHoistedPhis
assumes.
[X86] apply mulx optimization for two-wide mul instruction (mull, mulq) (#185127)
References: https://github.com/llvm/llvm-project/pull/184462
In the discussion for the linked PR, which removes unnecessary register
to register moves when one operand is in %rdx for mulx, the point was
brought up that this pattern also happens for mull and mulq.
The IR below:
```llvm
declare i32 @foo32()
declare i64 @foo64()
define i32 @mul32_no_implicit_copy(i32 %a0) {
%a1 = call i32 @foo32()
%a2 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a0, i32 %a1)
%a3 = extractvalue { i32, i1 } %a2, 0
ret i32 %a3
[53 lines not shown]
[CIR] Remove cir.unary(plus, ...) and emit nothing for unary plus
Traditional codegen never emits any operation for unary plus — it just
visits the subexpression as a pure identity at the codegen level. Align
CIRGen with this behavior by removing Plus from UnaryOpKind entirely
and having VisitUnaryPlus directly visit the subexpression with the
appropriate promotion/demotion handling.
[CIR] Split CIR_UnaryOp into individual operations
Split the monolithic cir.unary operation (which dispatched on a
UnaryOpKind enum) into four separate operations: cir.inc, cir.dec,
cir.minus, and cir.not.
This follows the same pattern used when cir.binop was split into
individual binary operations (AddOp, SubOp, etc.).
Changes:
- Add CIR_UnaryOpInterface with getInput()/getResult() methods
- Add CIR_UnaryOp and CIR_UnaryOpWithOverflowFlag base classes
- Define IncOp, DecOp, MinusOp, NotOp with per-op folds
- Add Involution trait to NotOp for not(not(x)) -> x folding
- Replace createUnaryOp() with createInc/Dec/Minus/Not builders
- Split LLVM lowering into four separate patterns
- Split LoweringPrepare complex-type handling per unary op
- Update CIRCanonicalize and CIRSimplify for new op types
- Update all codegen files to use bool params instead of UnaryOpKind
[6 lines not shown]
[CIR] Add cir.min op and refactor cir.max lowering
Add cir.min operation for integer minimum computation. Refactor cir.max
lowering into a shared lowerMinMaxOp template reused by both ops. Includes
lowering tests for signed, unsigned, and vector types, plus canonicalization
tests.
[CIR] Add Commutative/Idempotent traits to binary ops
Add missing MLIR traits to CIR binary operations, matching the arith
dialect conventions:
- AndOp, OrOp: Commutative, Idempotent (fixes FIXME)
- AddOp, MulOp, XorOp, MaxOp: Commutative
Add these ops to the CIRCanonicalize pass op list so trait-based
folding is exercised by applyOpPatternsGreedily.
Update testFloatingPointBinOps in binop.cpp to use computed values,
preventing DCE of the now-canonicalized ops.
[x86][GlobalISel] Select MOV32ri64 for unsigned 32-bit i64 constants (#185182)
x86 GlobalISel currently selects `MOV64ri32` for signed 32-bit `i64`
constants and falls back to `MOV64ri` otherwise.
That misses the unsigned 32-bit case, where `MOV32ri64` is a better
match.
FastISel already handles this case by using `MOV32ri64` for
zero-extended
32-bit values.
Update `X86InstructionSelector::selectConstant()` to select `MOV32ri64`
for `i64` constants that fit in `uint32_t`, while keeping `MOV64ri32`
for signed 32-bit values and `MOV64ri` for larger constants.
This reduces the encoding size for these constants and fixes the
`0xffffffff` boundary case to use the correct zero-extending move.
[CIR] Support addr-of-label in constant initializer context
Previously, using the GNU address-of-label extension (&&label) in an
array initializer like `void *labels[] = {&&a, &&b}` would hit an NYI
error in ConstantLValueEmitter::VisitAddrLabelExpr.
The scalar expression path already handles &&label correctly via
BlockAddressOp. The fix is to return null from the constant emitter,
which makes the caller fall through to the non-constant initialization
path that emits individual BlockAddressOp stores per element.
This is consistent with CIR's approach of preferring non-constant
emission to preserve source-level semantics (see CIRGenDecl.cpp:278).
[Transforms][NFC] Drop uses of BranchInst in headers (#186580)
Replace BranchInst with CondBrInst/UncondBrInst/Instruction in headers
and handle the related fall out.
The removed code in simplifyUncondBranch was made dead in
0895b836d74ed333468ddece2102140494eb33b6, where FoldBranchToCommonDest
was changed to only handle conditional branches.
[lldb] Fix heap.py crashes on recent Darwin embedded targets
Two fixes for the ptr_refs/cstr_refs/find_variable heap commands:
1. Move the `task` variable declaration into the common expression
preamble. Previously it was only declared inside the `search_heap`
code path, causing compilation errors when using `--ignore-heap`
with stack or segment scanning.
2. On recent iOS, some shared cache __DATA_CONST pages are remapped to
non-accessible at runtime, even though the Mach-O section metadata
still marks them as readable. The segment scan would crash with
EXC_BAD_ACCESS when reading these pages. Fix by querying actual
VM region permissions via SBProcess.GetMemoryRegionInfo() and
splitting sections at region boundaries to only scan readable
portions.
rdar://172543652
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
[clang-tidy] Fix virtual inheritance FP in misc-multiple-inheritance (#186103)
Avoid double-counting concrete bases introduced through virtual
inheritance in `misc-multiple-inheritance`.
As of AI-Usage: Gemini 3 is used for pre-commit reviewing.
Closes https://github.com/llvm/llvm-project/issues/186059
[clang-format] Ignore imports in comments for Java import sorting (#177326)
Java source files can contain apparent import statements inside block
comments (e.g., showing a code example). These can get mixed up with
real import statements when run through clang-format.
This patch tracks block comments (/* ... */) so that we skip lines that
are inside them.
Fixes #176771
---------
Co-authored-by: Natalia Kokoromyti <knatalia at yost-cm-01-imme.stanford.edu>
Co-authored-by: owenca <owenpiano at gmail.com>
[clang-format] Fix incorrect trailing comment and escaped newlines when AlignArrayOfStructures is enabled (#180305)
This change fixes how the spaces are modified during alignment.
Previously it was inconsistent whether the `StartOfTokenColumn` and
`PreviousEndOfTokenColumn` members of `WhitespaceManager::Change`s were
also updated when their `Spaces` member was changed to align tokens.
A new function has been added that properly maintains the relationship
between these members, and all places that directly modified `Spaces`
have been replaced with calls to this new function.
Fixes https://github.com/llvm/llvm-project/issues/138151. Fixes
https://github.com/llvm/llvm-project/issues/85937. Fixes
https://github.com/llvm/llvm-project/issues/53442. Tests have been added
to ensure they stay fixed.
Attribution Note - I have been authorized to contribute this change on
behalf of my company: ArenaNet LLC
