[RISCV][LLVM] Enable atomics for 'Zalrsc' (#163672)
The 'A' atomics extension is composed of two subextensions, 'Zaamo'
which has atomic memory operation instructions, and 'Zalrsc' which has
load-reserve / store-conditional instructions.
For machines where 'Zalrsc' is present, but 'Zaamo' is not, implement
and enable atomics memory operations through pseudo expansion. Updates the
predication and lowering control to be more precise about which 'Zaamo'/'Zalrsc'
feature was truly requisite.
There will be no functional change to subtargets supporting 'A', while
allowing 'Zalrsc' only subtargets to utilize atomics at an increased code
footprint.
[CIR] Implement inline builtin functions (#163911)
This patch implements the handling of inline builtin functions in CIR.
There is a known limitation in CIR where direct calls to shadowed inline
builtin functions are generated instead of the intrinsic. This is
expected to be fixed by the introduction of the nobuiltin attribute in a
future patch.
[compiler-rt] [CMake] Skip find_darwin_sdk_dir on disabled platforms (#163591)
find_darwin_sdk_dir can be slow, especially if xcrun does not
immediately find the corresponding SDK (i.e. because it is missing).
This skips those checks if the user has already set the corresponding
CMake variable to disable the platform anyway.
[acc][flang] lowering of acc declare on COMMON variables (#163676)
COMMON variables are treated as locals and lowered to structured
declares currently. This is incorrect because variables that are COMMON
should be treated as globals. Added implementation to treat these
variables differently.
[CIR] Atomic fetch operation (#161631)
This patch adds CIR support for atomic fetch-and-update operations,
including the intrinsic functions `__atomic_fetch_<binop>`,
`__atomic_<binop>_fetch`, and `__c11_atomic_fetch_<binop>`, where
`<binop>` could be `add`, `sub`, `max`, `min`, `and`, `or`, `xor`, and
`nand`.
[SPIR-V] Use `OpImageFetch` instead of `OpImageRead` when loading from read-only `Buffer` resource. (#163626)
Currently, the spir-v validator fails if `OpImageRead` instruction is
used when loading from read-only `Buffer`.
### Unit Test
```hlsl
RWBuffer<uint> rwbuff;
Buffer<uint> buff;
[numthreads(1,1,1)]
void main() {
rwbuff[99] = buff[98];
rwbuff[97] = rwbuff[96];
}
```
This also unblocks adding a test case that adds a special capability
when using a non-uniform index on `Buffer` arrays.
(https://github.com/llvm/llvm-project/pull/162540).
Resolves https://github.com/llvm/llvm-project/issues/162891
[libc] implement `inet_aton` (#162651)
This patch adds the implementation for `inet_aton` function. Since this
function is not explicitly included in POSIX, I have marked it with
`llvm_libc_ext`. It is widely available and commonly used, and can also
be used to implement `inet_addr`, which is included in POSIX.
[NFC][Clang][Diagnostics] Remove the DeferHint parameter of Diags(...) in favour of DeferHintRAII (#161517)
The `DeferHint` was misused at several callsites, where a `Decl*` was
implicitly casted to `bool`.
This patch proposes removing the `DeferHint` parameter and relying on
`DeferDiagsRAII` to set if Clang should defer the diagnostics.
[X86] Manage atomic load of fp -> int promotion in DAG
When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
[AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpand fails for aligned `load atomic <n x T>` because it
does not find a compatible library call. This change adds appropriate
bitcasts so that the call can be lowered. It also adds support for
128 bit lowering in tablegen to support SSE/AVX.
[SelectionDAG] Widen <2 x T> vector types for atomic load
Vector types of 2 elements must be widened. This change does this
for vector types of atomic load in SelectionDAG
so that it can translate aligned vectors of >1 size.
[SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.
IR/Verifier: Allow vector type in atomic load and store
Vector types on atomics are assumed to be invalid by the verifier. However,
this type can be valid if it is lowered by codegen.
[X86] Cast atomic vectors in IR to support floats
This commit casts floats to ints in an atomic load during AtomicExpand to support
floating point types. It also is required to support 128 bit vectors in SSE/AVX.
