[SPIR-V] Fix OpDecorate insertion point for non-PHI defs in decorateUsesAsNonUniform (#212524)
Inserting before the defining instruction placed the decoration ahead of
its own operand, breaking dominance for the loop-carried case
Fix machine code errors from
https://github.com/llvm/llvm-project/pull/208224#issuecomment-5095074660
[clang] Improve diagnostics around constexpr limits (#212091)
1) Mention the limit in the "constexpr evaluation hit maximum step
limit" diagnostic as well
2) Move the "use -fconstexpr-steps" instruction to its own note so we
can reuse it for two different diagnostics
For
```c++
struct S {
constexpr S() {}
};
constexpr S foo[1'500'000] = {};
```
we used to emit
```console
array.cpp:1028:13: error: constexpr variable 'foo' must be initialized by a constant expression
1028 | constexpr S foo[1'500'000] = {};
| ^ ~~
[21 lines not shown]
[test] Migrate Hexagon/PowerPC thunk tests to the default thunk order (#212693)
Drop -z nosort-thunks (added by #211721 to keep creation order) and
update expectations to the default order: forward thunks sorted by
descending destination.
[Clang][X86] Introduce Clang ABI Gate for MSVC alignment (#210305)
On x86_64-windows-msvc after 8ecec455183f, clang applies the MSVC
size-based global-alignment scheme (Microsoft64BitMinGlobalAlign) and
does not apply the Sys V "large array" alignment increase. Users may
want to preserve the earlier ABI for compatibility with objects produced
by older clang releases.
Gate this behavior on the Clang ABI compatibility level. When
`-fclang-abi-compat=22` (or lower) is in effect,
MicrosoftX86_64TargetInfo restores LargeArrayMinWidth/LargeArrayAlign to
128 and getMinGlobalAlign skips the Microsoft64BitMinGlobalAlign step,
matching the older alignment choices.
Assisted by Claude (Anthropic).
(cherry picked from commit cb383a37440d27238f8a01eee05228910d65d63e)
Revert "[AArch64] Enable Spillage Copy Elimination by default" (#211572)
Reverts llvm/llvm-project#186093
Issue https://github.com/llvm/llvm-project/issues/206839 shows that
EliminateSpillageCopies is not currently ready to be enabled by default
on AArch64. https://github.com/llvm/llvm-project/pull/207169 was raised
to fix the issue, but concerns were raised around complexity of the
function and change. Until a suitable solution can be found,
EliminateSpillageCopy will be disabled on AArch64 by default.
For those who wish to still use the pass, `-enable-spill-copy-elim=true`
will ensure the pass is run.
(cherry picked from commit debd8a7f889b29551dff7897f807e17f90eeee1d)
[AArch64][SVE] Support lowering masked loads/stores of <4 x bf16> and <8 x bf16> (#208744)
Add support for lowering masked loads/stores of <4 x bf16> and <8 x
bf16> when target features contain "+sve" and "+bf16".
Fixes: #201149
(cherry picked from commit b9869c8c920a7dfa983e215bc30729b13d8b353b)
[Docs] don't stylize syntax errors in code blocks
When a code block in the documentation contains (almost) pseudocode, the
Pygments parses flags erros and renders them with red-bordered boxes. This is
unnecessarily ugly. We can see examples of this in the LangRef with LLVM code
blocks.
Instead set the style to just render them as plain text. This still stands out
as unrecognized syntax, but does not distract the reader from reading the actual
example.
Assisted-by: Claude Opus 4.8
[AArch64] Add lowering for fixed-vector bf16 masked gather/scatter. (#210273)
Similar to #208744, this makes sure that bf16 masked gather and scatter
work with fixed-length sve enabled. Without +bf16 the operations are
currently expanded pre-isel, but that will not be fixed in this patch as
it is a larger change and this patch is intended to be ported to the
branch.
(cherry picked from commit 32221d9ff8f4772972193ebf7b8ba4974cd8458f)
[AArch64][SVE] Fix v16i8 -> v2i64 partial_reduce for VL > 128 (#204938)
A fixed-length `llvm.vector.partial.reduce.add` reducing `<16 x i8>`
into `<2 x i64>` is lowered on `+sve` by converting the reduction to a
scalable one and finishing with `convertFromScalableVector`. The i8 ->
i64 fold splits the `(nx)v4i32` dot before converting it back to fixed
length, but splitting a scalable container is not equivalent to
splitting the fixed vector it holds: at vscale=2 an `nxv4i32` container
splits into two `nxv2i32`, each holding four i32s, not the two-lane
halves of the underlying `v4i32`. The high partial sums land in lanes
that `convertFromScalableVector` then discards, so any runtime VL > 128
silently drops them — on a 256-bit machine (e.g. Neoverse V1) exactly
half the result is lost (#204939; downstream miscompile
rust-lang/rust#158144).
Convert the dot back to a fixed-length i32 vector before splitting, so
the split, widen and accumulate all happen in fixed length and no lanes
are dropped. The fixed dot width is derived from the result (two i32
lanes per i64 result lane) so the wider, VL-pinned `<4 x i64> <- <32 x
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[LLDB] Hide unresolvable children from ObjC tagged pointers (#211936)
Foundation's small value inline representations have valid summaries and
sometimed synthetic children, but LLDB cannot access any ivars from
their base classes (such as [NSObject isa]).
Use a synthetic child provider to hide them.
rdar://182434208
Assisted-by: claude
(cherry picked from commit 4f02e1e45c2711a94dae0eac2051ad7c2e5ca8c2)
[Clang] Avoid querying tag definitions for invalid DeclSpecs (#210085)
Guard hasTagDefinition() against invalid type-specifier state so
recovery from invalid auto/tag combinations does not assert.
Fixes #210014
---------
Signed-off-by: Osama Abdelkader <osama.abdelkader at gmail.com>
(cherry picked from commit de4b1f5572f8ff5a38a17655584ae200774551c6)
[MLIR] Validate directly parsed optional operand types (#212493)
Commit 6c51938067fa ([MLIR] Guard optional operand resolution in
generated op parsers) guarded resolution of every optional operand to
avoid indexing an empty inferred type range. The guard also skipped
resolveOperands when an optional operand was absent but an independently
optional type directive was present. This accepted malformed assembly
and silently discarded the orphan type when printing the operation.
Keep the guard for inferred type resolutions, which may access an empty
optional type vector, but always resolve directly parsed type ranges so
resolveOperands validates operand/type cardinality. Add coverage for
both valid forms and a type-only negative reproducer.
[Hexagon] Link static PIE executables against rcrt1.o (#210125)
We always selected crt1.o as the CRT start file, regardless of link
mode.
Select rcrt1.o - the self-relocating static-PIE start file when -static
and PIE are active
(cherry picked from commit c45b4e4d00bed488d6ece5608560561732ae5b9e)
[IR] Remove deprecated InsertPosition(Instruction*) constructor (#212640)
This implicit constructor has been marked deprecated since almost 2
years in favor of constructing an InsertPosition from a
BasicBlock::iterator.
Remove it now that in-tree users no longer rely on it.
Co-authored-by: Claude <noreply at anthropic.com>
[Hexagon] Fix compiler-rt install dir type, scope sanitizers (#209375)
COMPILER_RT_INSTALL_LIBRARY_DIR must be CACHE STRING, not CACHE PATH: a
relative PATH-typed cache entry resolves against the runtimes sub-build
directory instead of CMAKE_INSTALL_PREFIX, misplacing sanitizer libs.
Replace the explicit COMPILER_RT_BUILD_* ON list with
COMPILER_RT_SANITIZERS_TO_BUILD=all, since those options already default
ON upstream and infeasible sanitizers self-exclude via their own
ALL_<X>_SUPPORTED_ARCH lists.
Add FORCE to the dylib overrides so they take effect after
hexagon-unknown-linux-musl-clang-dist.cmake has already cached them OFF.
(cherry picked from commit 34aefe9744fa83fa222d7f28e073c693c2c4ff5b)
[RISCV] Don't move memory instructions across calls in isSafeToMove (#212236)
RISCVInstrInfo::isSafeToMove scans the instructions between From and To
to decide whether a memory instruction can be moved, but it only treated
mayStore() instructions as barriers. Calls on RISC-V are modeled with
isCall() and a register mask rather than mayStore(), so a load could be
moved across a call even though the callee may clobber the loaded
memory.
RISCVVectorPeephole::foldVMergeToMask uses this helper via ensureDominates()
to sink a load into a masked load when folding it into a vmerge, which
produced wrong code when the load was sunk past a call.
Instead of hand-rolling the barrier check, call MachineInstr::isSafeToMove
on each intervening instruction to populate SawStore. That is the same
helper used on From below, and it already treats calls (as well as PHIs
and ordered memory references) as stores.
This fixes #212226.
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[PAC][Headers] Fix incorrect comment in ptrauth.h (#207265)
The discriminator which is used to sign pointers to v-tables
is not always zero.
(cherry picked from commit 26643a89ddf98e48e986d25ceb10f673735bc7d7)
[ARM] Exclude TLS symbols from the .reloc/R_ARM_REL32 path (#212549)
The .reloc branch in emitMachineConstantPoolValue fired for any
isWeakForLinker() + isDSOLocal() symbol, including TLS (thread_local)
weak symbols. R_ARM_REL32 is wrong for TLS: TLS symbols need
TLS-specific relocations (R_ARM_TLS_GD32 etc.). Using R_ARM_REL32 for a
TLS symbol produces a wrong address at runtime.
This broke the 2-stage ARM 32-bit buildbots: stage 1 (with the .reloc
branch) miscompiled stage 2's BPF codegen (BTFDebug.cpp references
llvm::sys::sandbox::Enabled, an inline thread_local weak variable),
causing a SIGSEGV in the BPF Assembly Printer.
Add a regression test (tls_weak_var in elf-preemption.ll) verifying that
TLS weak symbols get TLSGD/TPOFF, not R_ARM_REL32.
Fix #212545
clang: Use TargetID parsing from AMDGPUTargetParser
We had grown 2 parallel parsing implementations for
triple+gpu name+feature flag target ID strings. Mostly
eliminate the redundant clang version.
Co-authored-by: Claude (Opus 4.8)
