LLVM/project 1dbb1b1lldb/source/Plugins/Process/gdb-remote ProcessGDBRemote.cpp

[lldb] Restore autosense for expedited memory-cache address parsing (#211846)

PR #211495 changed the expedited "memory:<addr>=<bytes>" address parse
in SetThreadStopInfo from autosense (radix 0) to explicit base 16.
debugserver sends this address with a "0x" prefix, and
StringRef::getAsInteger only strips that prefix in autosense mode. With
an explicit base 16 the parse stops at the 'x' and fails, so the
expedited stack bytes are never seeded into the L1 memory cache.

Restore BASE_AUTOSENSE here, matching the documented format for this key
(0x hex, 0 octal, otherwise decimal). Fixes TestExpeditedStackMemory.py.
DeltaFile
+1-1lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+1-11 files

LLVM/project f7c908bflang/lib/Semantics check-omp-variant.cpp check-omp-structure.h, flang/test/Semantics/OpenMP metadirective-default-none.f90

[flang][OpenMP] Check DEFAULT(NONE) on metadirective loop variants (#210172)

Flang does not enforce `DEFAULT(NONE)` for variables referenced in a
loop
associated with a standalone METADIRECTIVE. Consequently, it accepts
invalid
programs when a potentially selectable loop variant specifies
DEFAULT(NONE) but
omits a referenced variable from its data-sharing clauses. This change
checks the
associated loop for each potentially selectable `DEFAULT(NONE)` variant
and
diagnoses missing data-sharing attributes as it does for ordinary OpenMP
loop
constructs.

Standalone metadirectives and their associated loops are separate
parse-tree
nodes. For example:

    [34 lines not shown]
DeltaFile
+251-0flang/test/Semantics/OpenMP/metadirective-default-none.f90
+156-1flang/lib/Semantics/check-omp-variant.cpp
+4-0flang/lib/Semantics/check-omp-structure.h
+411-13 files

LLVM/project 0dd2c57llvm/test/CodeGen/AMDGPU llvm.log10.ll llvm.log.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-fpext.mir

AMDGPU/GlobalISel: Add lowering for bf16 fpext (#210887)

Add lowering for bf16 fpext based on SDAG's ISD::BF16_TO_FP lowering.
DeltaFile
+107-105llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
+139-66llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+139-66llvm/test/CodeGen/AMDGPU/llvm.log.ll
+119-58llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+94-46llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
+94-46llvm/test/CodeGen/AMDGPU/llvm.exp.ll
+692-3875 files not shown
+955-43511 files

LLVM/project 57af943clang/test/CodeGenHIP builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip builtins-amdgcn-vi-f16.hip

clang/AMDGPU: Migrate cc1 tests to subarch triples (3) (#211825)

Rewrite CodeGenHIP cc1 test RUN lines to the new subarch triple form,
dropping the redundant -target-cpu, and regenerate autogenerated CHECK
lines. Tests whose behavior depends on the implicit wave32 default
(which is not enabled by a bare subarch triple) are left for a later change.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+6-6clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
+4-4clang/test/CodeGenHIP/builtins-amdgcn-vi-f16.hip
+3-3clang/test/CodeGenHIP/builtins-amdgcn-dl-insts.hip
+3-3clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
+2-2clang/test/CodeGenHIP/ballot.cpp
+1-1clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-wmma-f16.hip
+19-1921 files not shown
+40-4027 files

LLVM/project 4473085clang/lib/Driver/ToolChains AMDGPU.cpp

Fix
DeltaFile
+1-0clang/lib/Driver/ToolChains/AMDGPU.cpp
+1-01 files

LLVM/project b7fa8b2llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/PhaseOrdering/X86 fmaddsub.ll

[VectorCombine] Fold binop(shuffle(V1, Mask), shuffle(V2, Mask)) -> shuffle(binop(V1, V2), Mask) (#211530)

This is a general, cost driven version of the InstCombine fold (which
was limited to non-length changing cases in #211115), and also permits
folds with multiuse shuffles.

Fixes #210948
DeltaFile
+27-64llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
+69-0llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+8-9llvm/test/Transforms/VectorCombine/X86/shuffletoidentity-bitcast.ll
+3-4llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
+2-4llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll
+2-3llvm/test/Transforms/VectorCombine/pr197910.ll
+111-846 files

LLVM/project d5e0624clang/docs UsersManual.md, flang/lib/Lower ConvertExpr.cpp

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+13,068-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+5,575-5,393llvm/test/CodeGen/AMDGPU/maximumnum.ll
+5,454-5,259llvm/test/CodeGen/AMDGPU/minimumnum.ll
+0-7,750flang/lib/Lower/ConvertExpr.cpp
+5,000-0libcxx/test/std/input.output/iostream.objects/many-ints.dat
+2,162-2,303clang/docs/UsersManual.md
+31,259-20,7054,164 files not shown
+109,019-107,7384,170 files

LLVM/project 22116c9clang/test/CodeGenCUDA fp-contract.cu amdgpu-atomic-ops.cu

clang/AMDGPU: Migrate cc1 tests to subarch triples (2) (#211823)

Rewrite CodeGenCUDA cc1 test RUN lines from `-triple amdgcn...
-target-cpu gfxNNN` to the new subarch triple form, dropping the redundant
-target-cpu.
Autogenerated CHECK lines are regenerated. Tests that intentionally
assert the "target-cpu" function attribute are left unchanged.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+40-40clang/test/CodeGenCUDA/fp-contract.cu
+8-8clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu
+6-6clang/test/CodeGenCUDA/host-used-extern.cu
+4-4clang/test/CodeGenCUDA/implicit-host-device-fun.cu
+4-4clang/test/CodeGenCUDA/unused-global-var.cu
+4-4clang/test/CodeGenCUDA/correctly-rounded-div.cu
+66-6611 files not shown
+83-8317 files

LLVM/project 165121ellvm/lib/Transforms/Utils SimplifyCFG.cpp, llvm/test/Transforms/SimplifyCFG switch-simplify-default.ll

Reland "[SimplifyCFG] Simplify switch default branch when branch proves operand value" (#211427)

Original PR: https://github.com/llvm/llvm-project/pull/206597
Revert PR: https://github.com/llvm/llvm-project/pull/211341

Relands abe757b. It was reverted due to my PR failing to update PHINode
entries in the default block, causing invalid IR in certain
circumstances. Original reproducer can be found
[here](https://github.com/llvm/llvm-project/pull/206597#issuecomment-5049789740).

We will now properly remove a PHINode entry if we remove a path from the
switch's block to the default block.

-------------------------------------------------------

If the default branch of a switch proves that there is only one value
that can be sent to the default branch, we can transform the default
branch into an explicit case of the switch. This can assist in further
simplification of the CFG during the simplification loop.

    [13 lines not shown]
DeltaFile
+456-0llvm/test/Transforms/SimplifyCFG/switch-simplify-default.ll
+47-0llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+503-02 files

LLVM/project 13040fbllvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers BUILD.gn

[gn build] Port 10e0a2ee03b0 (#211834)
DeltaFile
+1-0llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
+1-01 files

LLVM/project e6c604ellvm/utils/gn/secondary/llvm/unittests/Frontend BUILD.gn

[gn build] Port 19857baa713d (#211835)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
+1-01 files

LLVM/project f1bf19bllvm/lib/Target/AMDGPU SIFixSGPRCopies.cpp

[AMDGPU] Avoid quadratic MapVector::erase in SIFixSGPRCopies (#211740)
DeltaFile
+7-6llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+7-61 files

LLVM/project fb42025llvm/include/llvm/IR PassManagerInternal.h PassManager.h

[IR][NFC] Remove vtables from AnalysisResultConcept (#211810)

Similar to #209414 but for AnalysisResultConcept. This avoids vtables
for every analysis result type.

As a side effect, this improves the build times of PassBuilder.cpp by
~8% due to substantially fewer unique_ptr instantiations (instantiating
unique_ptr is expensive, at least with libstdc++).
DeltaFile
+47-57llvm/include/llvm/IR/PassManagerInternal.h
+1-1llvm/include/llvm/IR/PassManager.h
+48-582 files

LLVM/project 227ef98clang/test/AST ast-print-amdgcn-predicate.c, clang/test/CodeGen amdgpu-builtin-is-invocable.c amdgpu-builtin-processor-is.c

clang/AMDGPU: Migrate cc1 tests to subarch triples (1) (#211822)

Mechanically rewrite cc1 test RUN lines from the old
`-triple amdgcn... -target-cpu gfxNNN` form to the new subarch triple
form (e.g. `-triple amdgpu9.00-amd-amdhsa`), dropping the now-redundant
-target-cpu. The subarch encodes the exact target, so the emitted IR no
longer carries a "target-cpu" function attribute; autogenerated CHECK
lines are regenerated accordingly.

This batch covers the small CodeGen, Frontend, Layout, and Preprocessor
test directories.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+12-12clang/test/AST/ast-print-amdgcn-predicate.c
+7-7clang/test/CodeGen/AMDGPU/full-bf16.c
+4-4clang/test/CodeGen/amdgpu-builtin-is-invocable.c
+4-4clang/test/CodeGen/amdgpu-builtin-processor-is.c
+2-2clang/test/Frontend/openmp-warn-gpu-max-threads-per-block.c
+2-2clang/test/Layout/ms-x86-declspec-empty_bases.cpp
+31-3110 files not shown
+42-4216 files

LLVM/project 7a3208cflang/include/flang/Evaluate tools.h, flang/lib/Lower Bridge.cpp

[flang][cuda] Emit data transfers for whole-array and function-result managed assignments (#211640)

Assignments that read or write device/managed/unified data are
synchronous data transfers on stream 0 that wait for previously launched
kernels. Previously, whole-array managed = managed / host = managed
assignments, and assignments consuming a managed/unified/device function
result, were lowered as host copies (hlfir.assign), which can race an
asynchronous kernel that produced the data.

Emit cuf.data_transfer for these cases. Element-wise (scalar) accesses
and right-hand-side expressions involving managed data remain host
operations (the latter avoids materializing a temporary), and a
whole-allocatable left-hand side keeps reallocation semantics.
DeltaFile
+65-0flang/test/Lower/CUDA/cuda-managed-assign.cuf
+35-3flang/lib/Lower/Bridge.cpp
+20-6flang/include/flang/Evaluate/tools.h
+4-6flang/test/Lower/CUDA/cuda-data-transfer.cuf
+124-154 files

LLVM/project 1ad3b9ecross-project-tests/amdgpu builtins-amdgcn-gfx12-wmma-w32.cl builtins-amdgcn-gfx12-wmma-w64.cl

cross-project-tests: Migrate amdgpu tests to use subarch triples (#210115)
DeltaFile
+1-1cross-project-tests/amdgpu/builtins-amdgcn-gfx12-wmma-w32.cl
+1-1cross-project-tests/amdgpu/builtins-amdgcn-gfx12-wmma-w64.cl
+1-1cross-project-tests/amdgpu/builtins-amdgcn-swmmac-w32.cl
+1-1cross-project-tests/amdgpu/builtins-amdgcn-swmmac-w64.cl
+1-1cross-project-tests/amdgpu/builtins-amdgcn-wmma-w32.cl
+1-1cross-project-tests/amdgpu/builtins-amdgcn-wmma-w64.cl
+6-66 files

LLVM/project 6fd30f3clang/include/clang/Driver RocmInstallationDetector.h, clang/lib/Driver/ToolChains AMDGPU.cpp

Update
DeltaFile
+19-7clang/lib/Driver/ToolChains/AMDGPU.cpp
+16-0clang/test/Driver/rocm-detect-libdir.hip
+1-1clang/include/clang/Driver/RocmInstallationDetector.h
+1-0clang/test/Driver/Inputs/rocm/lib/amdhip64.lib
+37-84 files

LLVM/project 570a19dclang/lib/StaticAnalyzer/Checkers CStringChecker.cpp, clang/test/Analysis string-search-modeling.c

[analyzer] Fix false positive in strchr/strrchr with constant args (#210154)

When both the source string and the search target are compile-time
constants, determine the outcome precisely and only emit the feasible
branch (found or not-found).
Handles strchr, strrchr, strchrnul, memchr, strstr, and strpbrk.

Fixes #209905

Assisted by: Kiro-cli

---------

Co-authored-by: Vladislav Aranov <vladislav.aranov at ericsson.com>
DeltaFile
+404-0clang/test/Analysis/string-search-modeling.c
+214-26clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
+618-262 files

LLVM/project 044d346flang/include/flang/Optimizer/Transforms Passes.td Passes.h, flang/lib/Optimizer/Transforms FIRToSCF.cpp

[flang] Set nsw on FIRToSCF loop induction increments (#211796)

Example:
```fortran
subroutine sum_loop(a, n)
  integer :: a(n), i
  do i = 1, n
    a(i) = i
  end do
end
```

In this code, the DO induction variable `i` is stepped each iteration.
`FIRToSCF` lowered that increment to a plain `arith.addi` with no
overflow flag — unlike the CFG-conversion path (`ControlFlowConverter`),
which marks it `overflow<nsw>` — so LLVM must assume the IV may wrap and
cannot form an affine recurrence, blocking analysis/vectorization of
loops lowered via `fir-to-scf`.


    [3 lines not shown]
DeltaFile
+31-10flang/lib/Optimizer/Transforms/FIRToSCF.cpp
+6-6flang/test/Fir/FirToSCF/iter-while.fir
+4-1flang/include/flang/Optimizer/Transforms/Passes.td
+2-2flang/test/Fir/FirToSCF/do-loop.fir
+2-2flang/test/Fir/FirToSCF/iterate-while-extra.fir
+2-1flang/include/flang/Optimizer/Transforms/Passes.h
+47-221 files not shown
+48-237 files

LLVM/project 26f5da1clang/lib/ScalableStaticAnalysis/Core/Serialization/JSONFormat JSONFormatImpl.cpp

[SystemZ][z/OS] Add text flag when parsing json (#211805)

This patch adds the text flag when we are opening json files to parse. 
This fixes two lit failures on z/OS
DeltaFile
+1-1clang/lib/ScalableStaticAnalysis/Core/Serialization/JSONFormat/JSONFormatImpl.cpp
+1-11 files

LLVM/project cdc6669flang/lib/Semantics check-omp-structure.h check-acc-structure.h

[flang] Add missing std includes

Addressing post-commit review comments for
https://github.com/llvm/llvm-project/pull/211326.
DeltaFile
+12-0flang/lib/Semantics/check-omp-structure.h
+5-0flang/lib/Semantics/check-acc-structure.h
+0-1flang/lib/Semantics/check-directive-structure.h
+17-13 files

LLVM/project a443ddbllvm/test/Transforms/LoopVectorize interleave-and-scalarize-only.ll, llvm/test/Transforms/LoopVectorize/VPlan interleave-and-scalarize-only.ll icmp-uniforms.ll

[NFC][VPlan][Tests] Some CHECKs cleanup (#211425)

* Fix RUN-line in `VPlan/AArch64/call-decisions.ll` to work with UTC

"; -RUN" was resulting in

```
Error: Failed to update test <...>/call-decisions.ll
Traceback (most recent call last):
  File "<...>/update_analyze_test_checks.py", line 228, in main
    update_test(opt_basename, ti)
  File "<...>/update_analyze_test_checks.py", line 131, in update_test
    check_label_prefix = "VPlan for loop in " if regex == common.VPLAN_RE else ""
UnboundLocalError: local variable 'regex' referenced before assignment
```

* Regenerate CHECKs in VPlan/X86/vplan-vp-intrinsics.ll with UTC

* Split VPlan/interleave-and-scalarize-only.ll in two (VPlan/LLVM dumps)

    [5 lines not shown]
DeltaFile
+392-269llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
+477-0llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
+68-55llvm/test/Transforms/LoopVectorize/VPlan/X86/vplan-vp-intrinsics.ll
+5-5llvm/test/Transforms/LoopVectorize/VPlan/AArch64/call-decisions.ll
+0-2llvm/test/Transforms/LoopVectorize/VPlan/icmp-uniforms.ll
+942-3315 files

LLVM/project cfb5068flang/lib/Evaluate tools.cpp, flang/test/Lower split-sum-expression-tree-lowering.f90

[Flang][Lower] Flatten signed real sum terms

Second part of generalisations requested in #207377.

Extend real sum reassociation to flatten unparenthesized addition and
subtraction into signed terms. Rebuild split groups with addition and
subtraction while preserving parenthesized subtrees as opaque values.

I did not observe any benchmark result changes as a result of this
patch.

Assisted-by: Codex
DeltaFile
+224-27flang/test/Lower/split-sum-expression-tree-lowering.f90
+78-25flang/lib/Evaluate/tools.cpp
+302-522 files

LLVM/project 030c644llvm/lib/TargetParser AMDGPUTargetParser.cpp, llvm/unittests/TargetParser TargetParserTest.cpp

AMDGPU: Validate processor is consistent with subarch in TargetID parsing

TargetID::parse checked that a named processor was a recognized GPU, but
not that it was consistent with the triple's subarch. A target id like
"amdgpu9.00-amd-amdhsa--gfx803" was accepted even though gfx803 does not
belong to the amdgpu9.00 subarch, silently taking the processor and
ignoring the mismatched subarch.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+18-0llvm/unittests/TargetParser/TargetParserTest.cpp
+3-2llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+21-22 files

LLVM/project dd78a67llvm/lib/Target/AArch64/MCTargetDesc AArch64MCAsmInfo.cpp, llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUMCAsmInfo.cpp

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+87-84llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
+31-29llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
+27-25llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
+17-15llvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.cpp
+18-14llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
+12-10llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
+192-1778 files not shown
+256-22214 files

LLVM/project f9b1295llvm/lib/Target/AMDGPU SIOptimizeVGPRLiveRange.cpp

[AMDGPU] Use erase_if for Kills transfer in SIOptimizeVGPRLiveRange (#211800)
DeltaFile
+6-9llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
+6-91 files

LLVM/project 5b7188fllvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp SIISelLowering.cpp

AMDGPU: Handle ISD::POISON in fp16SrcZerosHighBits and isCanonicalized

We can choose to interpret poison however we choose at any point, so just
assume it's a free 0. This defends against regressions when poison is made
legal; it's not yet, so this should not yet have a practically observable
change.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+2-0llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+2-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-02 files

LLVM/project 5018aebllvm/lib/Transforms/Vectorize VPlan.h

[VPlan] Drop redundant member LLVM_ABI annotations (#205767)

Classes that are annotated with `LLVM_ABI[_FOR_TEST]` should not have
individual member annotations. This PR drops the redundant member
annotations.

The effort to build LLVM as a dylib is tracked in #109483.
DeltaFile
+14-14llvm/lib/Transforms/Vectorize/VPlan.h
+14-141 files

LLVM/project f7228c3clang/test/OpenMP openmp-read-only-feature.c ompx_attributes_codegen.cpp

clang/AMDGPU: Migrate cc1 tests to subarch triples (5)

Rewrite OpenMP cc1 test RUN lines to the new subarch triple form,
dropping the redundant -target-cpu, and regenerate autogenerated CHECK
lines. Tests that intentionally assert the "target-cpu" attribute are
left unchanged.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+2-2clang/test/OpenMP/openmp-read-only-feature.c
+2-2clang/test/OpenMP/ompx_attributes_codegen.cpp
+1-1clang/test/OpenMP/dims_modifier_messages.cpp
+1-1clang/test/OpenMP/metadirective_device_arch_codegen.cpp
+1-1clang/test/OpenMP/metadirective_device_isa_codegen_amdgcn.cpp
+1-1clang/test/OpenMP/target_num_teams_num_threads_attributes.cpp
+8-82 files not shown
+10-108 files

LLVM/project acd3765clang/test/CodeGenHIP builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip builtins-amdgcn-vi-f16.hip

clang/AMDGPU: Migrate cc1 tests to subarch triples (3)

Rewrite CodeGenHIP cc1 test RUN lines to the new subarch triple form,
dropping the redundant -target-cpu, and regenerate autogenerated CHECK
lines. Tests whose behavior depends on the implicit wave32 default (which
is not enabled by a bare subarch triple) are left for a later change.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+6-6clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
+4-4clang/test/CodeGenHIP/builtins-amdgcn-vi-f16.hip
+3-3clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
+3-3clang/test/CodeGenHIP/builtins-amdgcn-dl-insts.hip
+2-2clang/test/CodeGenHIP/ballot.cpp
+1-1clang/test/CodeGenHIP/builtins-amdgcn-buffer-format.hip
+19-1921 files not shown
+40-4027 files