LLVM/project 9aee371 — llvm/docs LangRef.md, llvm/include/llvm/Support CodeGen.h

by Matt Arsenault via GitHub on ⎇
IR: Introduce "float-abi" module flag (#210821)

This is intended to eliminate the FloatABIType TargetOptions field.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+33-8llvm/include/llvm/Support/CodeGen.h
+37-0llvm/test/Verifier/module-flags-float-abi.ll
+33-0llvm/docs/LangRef.md
+16-12llvm/lib/IR/AutoUpgrade.cpp
+28-0llvm/test/Linker/module-flags-float-abi.ll
+16-0llvm/test/Bitcode/upgrade-ppc-float-abi.ll
+163-204 files not shown
+201-2010 files

LLVM/project ef7f2f6 — llvm/lib/Target/RISCV RISCVVectorPeephole.cpp, llvm/test/CodeGen/RISCV/rvv vlmax-peephole.mir

by Pengcheng Wang via GitHub on ⎇
[RISCV] Fix crash in convertToVLMAX when AVL is an ADDI of a frame index (#212923)

`getConstant()` recognizes an AVL that is an immediate by checking
the opcode is `ADDI`, then reading the second operand and checking
if it is `X0`. However the second operand may be a frame index and
`getReg()` asserts with "This is not a register operand!".

We should guard the register access with `isReg()` before comparing
against `X0`.

Fixes #212797.
DeltaFile
+25-0llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir
+1-1llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+26-12 files

LLVM/project 27c7355 — mlir/test/Target/SPIRV debug.mlir non-uniform-ops.mlir

by Arseniy Obolenskiy via GitHub on ⎇
[NFC][mlir][SPIR-V] Use Subgroup scope in GroupNonUniform tests (#212928)

After https://github.com/KhronosGroup/SPIRV-Tools/pull/6811 spirv-val
rejects Workgroup scope on these ops
DeltaFile
+26-26mlir/test/Target/SPIRV/non-uniform-ops.mlir
+1-1mlir/test/Target/SPIRV/debug.mlir
+27-272 files

LLVM/project 46919d2 — llvm/docs AMDGPUAsyncOperations.md

by Sameer Sahasrabuddhe via GitHub on ⎇
[Docs][AMDGPU] Explain completion of async operations (#212756)

This improves the somewhat hand-wavey "memory model" currently described
for async operations. While this version is also not complete, it
prepares for the more complete memory model being written down.
DeltaFile
+26-12llvm/docs/AMDGPUAsyncOperations.md
+26-121 files

LLVM/project 6007408 — llvm/lib/Target/RISCV RISCVSchedTTAscalonX.td RISCVSchedSpacemitX60.td

by LiqinWeng via GitHub on ⎇
[RISCV] Split and rename WriteVSlideI/WriteVISlide1X/WriteVFSlide1F (#212184)

Split each of these SchedWrites into separate slide-up and slide-down
variants:
  - WriteVSlideI     -> WriteVSlideUpI, WriteVSlideDownI
  - WriteVISlide1X   -> WriteVISlide1Up, WriteVISlide1Down
  - WriteVFSlide1F   -> WriteVFSlide1Up, WriteVFSlide1Down

SpacemiT X100 and A100 have different latencies and/or throughput for
slide up vs. slide down operations, so they need separate SchedWrites to
model that difference.
DeltaFile
+12-11llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+12-9llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+12-6llvm/lib/Target/RISCV/RISCVScheduleV.td
+8-4llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+6-3llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td
+6-3llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+56-365 files not shown
+82-5011 files

LLVM/project a4b3c7e — clang/lib/Driver/ToolChains CommonArgs.cpp AMDGPU.h, clang/test/Driver amdgpu-assembler-xnack-sramecc.s

by Matt Arsenault on ⎇
clang/AMDGPU: Forward xnack/sramecc mode to the assembler

When assembling a .s file with no target ID directive, the requested
xnack/sramecc mode has no module flag to carry it. Forward the mode
requested via -mxnack/-msramecc (or the -mcpu target ID modifiers) to the
assembler as a target feature so it is recorded in the object's e_flags.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+33-0clang/test/Driver/amdgpu-assembler-xnack-sramecc.s
+18-1clang/lib/Driver/ToolChains/AMDGPU.cpp
+2-1clang/lib/Driver/ToolChains/AMDGPU.h
+1-1clang/lib/Driver/ToolChains/CommonArgs.cpp
+54-34 files

LLVM/project cb8513d — llvm/lib/Target/CSKY CSKYAsmPrinter.cpp

by Matt Arsenault via GitHub on ⎇
CSKY: Avoid constructing a temporary CSKYSubtarget in AsmPrinter (#212944)

This was reconstructing a subtarget equivalent to the global
subtarget instead of just using the available one.
DeltaFile
+1-9llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
+1-91 files

LLVM/project 2b45696 — llvm/lib/Target/Mips/AsmParser MipsAsmParser.cpp, llvm/test/MC/Mips macro-ddivu-bad.s macro-divu-bad.s

by yingopq via GitHub on ⎇
[Mips] Fix Clang crashes when assembling MIPS div/rem with register-name symbol as divisor (#200354)

Add check before getimm().

Fix #185363.
DeltaFile
+7-4llvm/test/MC/Mips/macro-ddiv-bad.s
+5-2llvm/test/MC/Mips/macro-divu-bad.s
+5-2llvm/test/MC/Mips/macro-div-bad.s
+4-1llvm/test/MC/Mips/macro-ddivu-bad.s
+2-0llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+23-95 files

LLVM/project 07897c2 — llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp Triple.cpp

by Matt Arsenault via GitHub on ⎇
AMDGPU: TableGen the subarch triple name table (#212627)

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+87-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+2-45llvm/lib/TargetParser/Triple.cpp
+23-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+17-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+4-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+133-655 files

LLVM/project 8e28a0b — flang/lib/Lower/OpenMP OpenMP.cpp, flang/test/Lower/OpenMP allocate-clause-allocator.f90

by Sairudra More on ⎇
[flang][OpenMP] Fix allocate indices for common blocks

Co-authored-by: Copilot <223556219+Copilot at users.noreply.github.com>
DeltaFile
+17-5flang/lib/Lower/OpenMP/OpenMP.cpp
+18-0flang/test/Lower/OpenMP/allocate-clause-allocator.f90
+35-52 files

LLVM/project 70e39de — llvm/test/CodeGen/X86 vec_int_to_fp.ll

by Simon Pilgrim via GitHub on ⎇
[X86] vec_int_to_fp.ll - regenerate tests with missing VPADD constant asm comments (#212941)

Reduces diff in a future patch
DeltaFile
+4-4llvm/test/CodeGen/X86/vec_int_to_fp.ll
+4-41 files

LLVM/project 13e5ce4 — llvm/test/CodeGen/X86 avx512-gather-scatter-intrin.ll avx512-gather-scatter-intrin-deprecated.ll

by Simon Pilgrim via GitHub on ⎇
[X86] Regenerate gather tests with missing VPADD constant asm comments (#212940)

Reduces diff in a future patch
DeltaFile
+9-9llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
+9-9llvm/test/CodeGen/X86/avx512-gather-scatter-intrin-deprecated.ll
+18-182 files

LLVM/project a4d1a09 — flang/include/flang/Evaluate complex.h integer.h, flang/lib/Evaluate initial-image.cpp character.h

by Michael Kruse on ⎇
[Flang] Use abstraction for binary scalar data
DeltaFile
+151-0flang/include/flang/Evaluate/character.h
+0-122flang/lib/Evaluate/character.h
+27-18flang/include/flang/Evaluate/initial-image.h
+17-21flang/lib/Evaluate/initial-image.cpp
+21-0flang/include/flang/Evaluate/integer.h
+18-0flang/include/flang/Evaluate/complex.h
+234-1614 files not shown
+263-17310 files

LLVM/project fc764a7 — llvm/include/llvm/IR RuntimeLibcalls.td, llvm/lib/Target/ARM ARMSubtarget.cpp

by Matt Arsenault via GitHub on ⎇
ARM: Mark more generic libgcc functions as available (#210961)

Generic libgcc/compiler-rt functions coexist with aeabi variants
(e.g., __divsi3  and __aeabi_idiv) according to my reading of the
build. At least in compiler-rt, some are aliases.

They were previously removed from the available set on AEABI+AAPCS
targets to force selection of the preferred __aeabi_* variants, back when
only one implementation per libcall could be recorded.

Now that multiple implementations can be available per libcall, stop
hiding the generics and select the __aeabi_* variant explicitly as the
preferred implementation. This reduces the number of special cases to 
consider for future libcalls info improvements.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+71-0llvm/lib/Target/ARM/ARMSubtarget.cpp
+1-7llvm/include/llvm/IR/RuntimeLibcalls.td
+72-72 files

LLVM/project fb93fdd — llvm/docs AMDGPUUsage.rst AMDGPUMemoryModel.md

by Sameer Sahasrabuddhe on ⎇
[Docs][AMDGPU] availability/visibility in addrspace(3) and other cleanups

addrspace(3) on AMDGPU corresponds to LDS, which is a fast memory directly
accessed by all threads in a workgroup (there is no intervening cache). Thus,
any accesses to this addrspace have built-in availability and visibility at
"workgroup" scope.

Other cleanups:

- Update the intrinsic names to match the implementation.
- Explain store-available and load-visible.
- Rename to "make-available" and "make-visible" for consistent spelling.
DeltaFile
+92-53llvm/docs/AMDGPUMemoryModel.md
+2-0llvm/docs/AMDGPUUsage.rst
+94-532 files

LLVM/project f08211e — llvm/lib/Target/AArch64 AArch64RegisterInfo.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

by Cullen Rhodes via GitHub on ⎇
[AArch64] Remove assembler-only register classes (#211527)

ZPRMul2, ZPRMul4 and PPRMul2 register classes are used solely by the asm
parser to validate other register classes (ZPR2Mul2, ZPR4Mul4,
PPR2Mul2). Since they're real register classes TableGen synthesizes
numerous intersection classes and pressure sets from them.

Removing them and validating the constraint directly in the assembly
parser reduces:

- generated register classes: 521 -> 403 (~22%)
- generated pressure sets: 188 -> 60 (68%)
- generated register-info size: 11.9 MB -> 9.1 MB (23%)

Also improves CTMark geomean -0.23% on stage1-aarch64-O3.

https://llvm-compile-time-tracker.com/compare.php?from=a90dbb43cd67856f681feba82d51a0d5fbcae3c2&to=5565d4907cdf960cc142a7507f16e551f51919b0&stat=instructions%3Au

Assisted-by: codex
DeltaFile
+32-33llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+5-3llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+3-3llvm/test/TableGen/aarch64-register-info-stats.td
+3-3llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
+1-1llvm/test/CodeGen/AArch64/fmlal-loreg.ll
+44-435 files

LLVM/project df272b1 — llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp

by Matt Arsenault on ⎇
AMDGPU: Export the TargetParser feature bitset

Previously this bitset was only used to populate the feature
name string map used by clang. Eventually this will replace
the current bitmask integer. AArch64 already has a similar
interface.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+17-14llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+29-0llvm/unittests/TargetParser/TargetParserTest.cpp
+16-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+62-143 files

LLVM/project 4802519 — llvm/lib/Target/AMDGPU AMDGPU.td, llvm/lib/TargetParser AMDGPUTargetParser.cpp

by Matt Arsenault on ⎇
AMDGPU: Tablegenerate TargetParser feature sets

Traditionally we maintained 2 parallel feature mechanisms,
one in clang (later moved to TargetParser), with largely
mirrored subtarget features defined in the backend. Start
directly taking feature information from the backend and putting
it into TargetParser. This is still in a compromise mid-migration
state. We still have both the legacy "ArchAttr" bitfield integer,
plus a new AMDGPUFeatureBitset field stored in the table, which
isn't yet exported.

For the moment, the new bitset is only used to populate the
feature string name map, which is the big maintainability win.
This also lists an explicit subset of exported features to
avoid churn.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+51-508llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+115-3llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+43-0llvm/unittests/TargetParser/TargetParserTest.cpp
+39-0llvm/lib/Target/AMDGPU/AMDGPU.td
+248-5114 files

LLVM/project 588ce16 — llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp Triple.cpp

by Matt Arsenault on ⎇
AMDGPU: TableGen the subarch triple name table

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+87-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+2-45llvm/lib/TargetParser/Triple.cpp
+23-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+17-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+4-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+133-655 files

LLVM/project de26036 — clang/test/Misc/target-invalid-cpu-note r600.c amdgcn.c, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

by Matt Arsenault via GitHub on ⎇
AMDGPU: Eliminate old macro driven processor name parsing (#212608)

Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+162-114llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+72-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+18-18clang/test/Misc/target-invalid-cpu-note/amdgcn.c
+10-10clang/test/Misc/target-invalid-cpu-note/r600.c
+2-2llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+264-1875 files

LLVM/project deab742 — llvm/lib/Target/CSKY CSKYAsmPrinter.cpp

by Matt Arsenault on ⎇
CSKY: Avoid constructing a temporary CSKYSubtarget in AsmPrinter

This was reconstructing a subtarget equivalent to the global
subtarget instead of just using the available one.
DeltaFile
+1-9llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
+1-91 files

LLVM/project b84c5f4 — llvm/include/llvm/Analysis BlockFrequencyInfoImpl.h

by Fangrui Song via GitHub on ⎇
[BFI] Simplify/optimize getMass/getContainingLoop. NFC (#212938)

A block can head both a natural loop and the irreducible loop wrapping
it (`@crossloops` in BlockFrequencyInfo/irreducible.ll).

getContainingLoop and getMass unroll to a fixed depth of two through
isDoubleLoopHeader and isADoublePackage.  Depth two holds because
IrreducibleGraph::addEdge drops edges into the enclosing loop's headers,
keeping such a header out of any nested SCC.

(The old comment "If it's a node inside a packaged loop, it returns the
loop's mass." is wrong.)

Walk the Parent chain instead to drop the depth two assumption. Testing
`IsPackaged` before isHeader also skips the Nodes[0] load on the common
path.
DeltaFile
+19-25llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+19-251 files

LLVM/project 8a1ff7f — llvm/lib/Target/RISCV RISCVOptWInstrs.cpp RISCVISelDAGToDAG.cpp, llvm/test/CodeGen/RISCV zilx-opt-w-instrs.mir zilx.ll

by Pengcheng Wang via GitHub on ⎇
[RISCV] Support CodeGen of Zilx extension

Thanks for `XTheadMemIdx` extension that makes life easier.

Reviewers: lukel97, topperc, kito-cheng, tclin914

Reviewed By: topperc

Pull Request: https://github.com/llvm/llvm-project/pull/209420
DeltaFile
+1,880-0llvm/test/CodeGen/RISCV/zilx.ll
+182-0llvm/test/CodeGen/RISCV/zilx-opt-w-instrs.mir
+113-0llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
+29-4llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+19-11llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+14-1llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+2,237-161 files not shown
+2,239-177 files

LLVM/project b44c307 — llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp Triple.cpp

by Matt Arsenault on ⎇
AMDGPU: TableGen the subarch triple name table

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+87-20llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+2-45llvm/lib/TargetParser/Triple.cpp
+23-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+17-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+4-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+133-655 files

LLVM/project 88554dc — clang/test/Misc/target-invalid-cpu-note r600.c amdgcn.c, llvm/include/llvm/TargetParser AMDGPUTargetParser.h

by Matt Arsenault on ⎇
AMDGPU: Eliminate old macro driven processor name parsing

Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+162-114llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+72-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+18-18clang/test/Misc/target-invalid-cpu-note/amdgcn.c
+10-10clang/test/Misc/target-invalid-cpu-note/r600.c
+2-2llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+264-1875 files

LLVM/project 23a2224 — llvm/lib/Target/RISCV RISCVFeatures.td RISCVInstrInfoZilx.td, llvm/test/CodeGen/RISCV attributes.ll

by Pengcheng Wang via GitHub on ⎇
[RISCV][MC] Support experimental Zilx extension

This adds the MC support for `Zilx` (Indexed Integer Load Instructions)
extension.

Doc: https://github.com/riscv/riscv-zilx

Reviewers: topperc, tclin914, kito-cheng

Pull Request: https://github.com/llvm/llvm-project/pull/209419
DeltaFile
+95-0llvm/lib/Target/RISCV/RISCVInstrInfoZilx.td
+68-0llvm/test/MC/RISCV/zilx-valid-rv64.s
+63-0llvm/test/MC/RISCV/zilx-valid-rv32.s
+40-0llvm/test/MC/RISCV/zilx-invalid.s
+7-0llvm/lib/Target/RISCV/RISCVFeatures.td
+4-0llvm/test/CodeGen/RISCV/attributes.ll
+277-07 files not shown
+287-013 files

LLVM/project b42621f — llvm/lib/TargetParser AMDGPUTargetParser.cpp, llvm/utils/TableGen/Basic AMDGPUTargetDefEmitter.cpp

by Matt Arsenault via GitHub on ⎇
AMDGPU: TableGen the subarch to processor name mapping table (#212606)

Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical
GPU name) with a generated table.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+23-43llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+61-5llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+84-482 files

LLVM/project 36f00d0 — llvm/test/CodeGen/AArch64 neon-dotreduce.ll, llvm/test/CodeGen/AArch64/GlobalISel split-wide-shifts-multiway.ll

by Pengcheng Wang on ⎇
Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+5,516-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmulh.ll
+4,862-0llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+2,988-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+1,045-1,527llvm/test/CodeGen/AMDGPU/frem.ll
+1,148-1,123llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
+1,023-1,030llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+16,582-3,6802,492 files not shown
+89,578-37,2752,498 files

LLVM/project 1af0f1f — llvm/test/CodeGen/AArch64 neon-dotreduce.ll, llvm/test/CodeGen/AArch64/GlobalISel split-wide-shifts-multiway.ll

by Pengcheng Wang on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+5,516-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmulh.ll
+4,862-0llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+2,988-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+1,045-1,527llvm/test/CodeGen/AMDGPU/frem.ll
+1,148-1,123llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
+1,023-1,030llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+16,582-3,6802,492 files not shown
+89,578-37,2752,498 files

LLVM/project 6d5d631 — llvm/test/CodeGen/AArch64 neon-dotreduce.ll, llvm/test/CodeGen/AArch64/GlobalISel split-wide-shifts-multiway.ll

by Pengcheng Wang on ⎇
Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+5,516-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmulh.ll
+4,862-0llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+2,988-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+1,045-1,527llvm/test/CodeGen/AMDGPU/frem.ll
+1,148-1,123llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
+1,023-1,030llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+16,582-3,6802,492 files not shown
+89,578-37,2752,498 files