LLVM/project 919f72a.github CODEOWNERS, libc/docs porting.rst

[docs] Remove all references to Maintainers.rst (#200368)

All projects are using Maintainers.md files as of #200365.
DeltaFile
+4-5llvm/docs/DeveloperPolicy.rst
+2-2llvm/docs/Contributing.rst
+1-1.github/CODEOWNERS
+1-1libc/docs/porting.rst
+8-94 files

LLVM/project 105e8cellvm/include/llvm/IR CFG.h, llvm/lib/AsmParser LLParser.cpp

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+0-51llvm/lib/AsmParser/LLParser.cpp
+0-42llvm/test/Assembler/uselistorder_bb.ll
+5-17llvm/include/llvm/IR/CFG.h
+2-14llvm/lib/CodeGen/IndirectBrExpandPass.cpp
+0-11llvm/test/Assembler/invalid-uselistorder_bb-numbered.ll
+0-11llvm/test/Assembler/invalid-uselistorder_bb-float-literal.ll
+7-14616 files not shown
+21-19022 files

LLVM/project 050c202clang-tools-extra Maintainers.md, clang-tools-extra/docs conf.py Maintainers.md

[clang-tools-extra][docs] Convert maintainers file to Markdown (#200365)

Following the way clang does it.

* Moved files to .md (done in #200769).
* Reformatted into Markdown.
* Changed the stub file docs/Maintainers.rst into docs/Maintainers.md
and used a myst directive for the include.
* In the config file, added myst parser and ".md" as a recognised file
extension.

After this change, all maintainers files in llvm-project will be in
Markdown format.
DeltaFile
+54-56clang-tools-extra/Maintainers.md
+3-2clang-tools-extra/docs/conf.py
+2-1clang-tools-extra/docs/Maintainers.md
+1-1llvm/Maintainers.md
+60-604 files

LLVM/project 1b24a40clang-tools-extra Maintainers.md Maintainers.rst, clang-tools-extra/docs Maintainers.rst Maintainers.md

[clang-tools-extra] Move maintainer files to .md files (#200769)

Without any formatting changes. This will break the docs build, but a
follow up (#200365) will fix the formatting and so on.
DeltaFile
+84-0clang-tools-extra/Maintainers.md
+0-84clang-tools-extra/Maintainers.rst
+0-1clang-tools-extra/docs/Maintainers.rst
+1-0clang-tools-extra/docs/Maintainers.md
+85-854 files

LLVM/project 044b63dclang/lib/AST/ByteCode Compiler.cpp

[clang][bytecode][NFC] Avoid some code duplication for `ScalarValueInitExpr` (#200755)
DeltaFile
+13-26clang/lib/AST/ByteCode/Compiler.cpp
+13-261 files

LLVM/project 1678d2elibsycl/src/detail queue_impl.cpp

fix liboffload usage

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+5-3libsycl/src/detail/queue_impl.cpp
+5-31 files

LLVM/project 4176fb6lld/test/ELF aarch64-reloc-pauth.s

Address review comments
DeltaFile
+5-11lld/test/ELF/aarch64-reloc-pauth.s
+5-111 files

LLVM/project 9a0f9dallvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll llvm.amdgcn.av.load.b128.ll

Merge branch 'main' into users/KseniyaTikhomirova/kernel_submit_single_3
DeltaFile
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+12,982-11,930llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+12,365-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
+10,469-10llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+8,268-12llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+2,674-2,698llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+70,631-35,5736,841 files not shown
+387,475-197,6156,847 files

LLVM/project ea8f3dfllvm/test/Transforms/LoopVectorize cast-costs.ll vscale-cost.ll

[LV][NFC] Add cost model tests for VPInstructionWithType (#200135)
DeltaFile
+80-0llvm/test/Transforms/LoopVectorize/cast-costs.ll
+36-0llvm/test/Transforms/LoopVectorize/vscale-cost.ll
+116-02 files

LLVM/project f2f9eaellvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-shuffle-combining-avx512vbmi2.ll

[X86] matchShuffleAsVSHLD - fix incorrect shift factor (#200754)

#200604 left the non-commuted case to still scale by 8bits instead of the src scalar bit size
DeltaFile
+17-0llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi2.ll
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+18-12 files

LLVM/project 581c37autils/bazel/llvm-project-overlay/libc BUILD.bazel

[bazel] Port ae1d75e (#200758)
DeltaFile
+1-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+1-01 files

LLVM/project 63c29dfclang/lib/Serialization ASTReaderDecl.cpp, clang/test/PCH friend-template-spec-redecl.cpp

[Serialization] Fix assertion on re-deserialized friend template spec… (#200566)

…ialization in PCH (#198133)

A friend function-template specialization declared inside a class
template is serialized into a PCH. When the class template is later
instantiated while loading the PCH, the friend specialization can be
deserialized re-entrantly (VisitFriendDecl -> VisitFunctionDecl -> ...
-> VisitFunctionDecl for the same specialization) at the same time as
the canonical copy, producing two redeclarations of the same
specialization in the template's specialization set.

ASTDeclReader::VisitFunctionDecl asserted that this collision could only
happen when merging declarations from different modules. Since
38b3d87bd384, friend functions defined inside dependent class templates
are loaded eagerly, so the collision can now also occur within a single
PCH/AST file (non-modules build), tripping the assertion:

  Assertion failed: (Reader.getContext().getLangOpts().Modules &&

    [7 lines not shown]
DeltaFile
+34-0clang/test/PCH/friend-template-spec-redecl.cpp
+0-2clang/lib/Serialization/ASTReaderDecl.cpp
+34-22 files

LLVM/project ae1d75elibc/src/__support/math hypotf16.h expxf16_utils.h

[libc][math] Guard f16 math headers to fix certain 32-bit ARM builds (#200715)

Wrap hypotf16.h and expxf16_utils.h in LIBC_TYPES_HAS_FLOAT16 macros
like other flaot16 math headers. This fixes build breaks on systems
where float16 is unsupported (like some 32-bit ARM).
DeltaFile
+6-0libc/src/__support/math/hypotf16.h
+6-0libc/src/__support/math/expxf16_utils.h
+12-02 files

LLVM/project e9556fcmlir/lib/Conversion/MathToSPIRV MathToSPIRV.cpp, mlir/test/Conversion/MathToSPIRV math-to-gl-spirv.mlir math-to-opencl-spirv.mlir

[mlir][SPIR-V] Convert math.trunc to GL Trunc and CL trunc (#200739)
DeltaFile
+4-0mlir/test/Conversion/MathToSPIRV/math-to-gl-spirv.mlir
+4-0mlir/test/Conversion/MathToSPIRV/math-to-opencl-spirv.mlir
+2-0mlir/lib/Conversion/MathToSPIRV/MathToSPIRV.cpp
+10-03 files

LLVM/project 52e2280clang/lib/CodeGen TargetInfo.h CodeGenModule.cpp, clang/lib/CodeGen/Targets AMDGPU.cpp SPIR.cpp

[NFCI][clang] Allow overriding any global variable address space

Allow the target to change the AS of a global variable at will, not just whenever Clang cannot assign one.
This enables the next patch that will specialize LDS GVs for barriers as a separate address space.
DeltaFile
+10-9clang/lib/CodeGen/Targets/AMDGPU.cpp
+12-6clang/lib/CodeGen/TargetInfo.h
+7-8clang/lib/CodeGen/Targets/SPIR.cpp
+11-2clang/lib/CodeGen/CodeGenModule.cpp
+5-6clang/lib/CodeGen/TargetInfo.cpp
+6-3clang/lib/CodeGen/Targets/AVR.cpp
+51-346 files

LLVM/project c9f6a05llvm/test/CodeGen/AMDGPU s-barrier-id-allocation.ll, mlir/include/mlir/Dialect/LLVMIR ROCDLOps.td

Fix MLIR
DeltaFile
+21-21llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
+8-6mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+4-4mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir
+2-2mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+1-1mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+36-345 files

LLVM/project 005e564llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll s-barrier.ll

[RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.
DeltaFile
+442-0llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+62-45llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+54-31llvm/test/CodeGen/AMDGPU/s-barrier.ll
+52-14llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+35-31llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
+32-32llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
+677-15342 files not shown
+1,108-44148 files

LLVM/project 7e5a386llvm/lib/Target/AMDGPU AMDGPULowerExecSync.cpp

clang-format
DeltaFile
+1-2llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
+1-21 files

LLVM/project 62b7cf9llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU buffer-store-dwordx4-vpk-mul-war-hazard-gfx942.mir

[AMDGPU] Widen MUBUF/MTBUF source-vgpr WAR hazard on gfx940-family to SGPR soffset (#197267)

createsVALUHazard previously gated the MUBUF/MTBUF source-vgpr WAR
hazard to fire only when SOFFSET was a literal or absent. On
gfx940-family subtargets that gate is too narrow: the hazard also fires
when SOFFSET is sourced from an SGPR.

Concretely, on gfx950 a sequence of the form

```
  buffer_store_dwordx4 v[X:X+3], voff, descr, sN offen
  v_pk_mul_f32 v[X:X+1], <src>, <src>           # next VALU cycle
```

deterministically commits the post-pk_mul value of v[X+1] to memory for
the second dword of the store; the other three dwords store correctly.

The wait-state window depends on the SOFFSET shape:


    [20 lines not shown]
DeltaFile
+122-0llvm/test/CodeGen/AMDGPU/buffer-store-dwordx4-vpk-mul-war-hazard-gfx942.mir
+58-21llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+180-212 files

LLVM/project dc01d53llvm/test/CodeGen/AMDGPU s-barrier-id-allocation.ll, mlir/include/mlir/Dialect/LLVMIR ROCDLOps.td

Fix MLIR
DeltaFile
+21-21llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
+8-6mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+4-4mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir
+2-2mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+1-1mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+36-345 files

LLVM/project 683c367lldb/test/Shell/lldb-server TestGdbserverErrorDarwin.test TestGdbserverErrorMessages.test, lldb/tools/lldb-server lldb-server.cpp

[lldb][lldb-server][Darwin] Error when gdbserver mode is requested (#199654)

Fixes #199035

lldb-server's platform mode works on Apple platforms but the gdbserver
mode does not. Users should use debugserver instead, and platform mode
knows to spawn debugserver instead of lldb-server.

I'm adding an error to state this, because until now it would maybe
appear to work, or crash in strange ways. None of which can be fixed by
a user and are a waste of our time dealing with the bug reports.
DeltaFile
+6-0lldb/tools/lldb-server/lldb-server.cpp
+4-0lldb/test/Shell/lldb-server/TestGdbserverErrorDarwin.test
+3-0lldb/test/Shell/lldb-server/TestGdbserverErrorMessages.test
+13-03 files

LLVM/project 51b54ffclang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode cxx23.cpp

[clang][bytecode] Fix discarded dynamic casts (#200723)

If they are checked.
DeltaFile
+4-0clang/test/AST/ByteCode/cxx23.cpp
+2-0clang/lib/AST/ByteCode/Compiler.cpp
+6-02 files

LLVM/project 40b722dmlir/include/mlir/Dialect/SPIRV/IR SPIRVGLOps.td SPIRVCLOps.td, mlir/test/Dialect/SPIRV/IR ocl-ops.mlir gl-ops.mlir

[mlir][SPIR-V] Add GL Trunc and CL trunc ops (#200738)
DeltaFile
+24-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td
+21-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td
+20-0mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
+18-0mlir/test/Dialect/SPIRV/IR/gl-ops.mlir
+2-0mlir/test/Target/SPIRV/gl-ops.mlir
+2-0mlir/test/Target/SPIRV/ocl-ops.mlir
+87-06 files

LLVM/project abdab06mlir/lib/Conversion/MathToSPIRV MathToSPIRV.cpp, mlir/test/Conversion/MathToSPIRV math-to-gl-spirv.mlir

[mlir][SPIR-V] Convert math.fpowi to spirv.GL.Pow (#200563)
DeltaFile
+44-1mlir/lib/Conversion/MathToSPIRV/MathToSPIRV.cpp
+34-0mlir/test/Conversion/MathToSPIRV/math-to-gl-spirv.mlir
+78-12 files

LLVM/project 24b8cfamlir/test/Target/SPIRV selection.mlir

[mlir][SPIR-V] Add roundtrip and validation test for spirv.Switch (NFC) (#200572)

Add missing `spirv-val` tests for spirv.Switch operation
DeltaFile
+29-0mlir/test/Target/SPIRV/selection.mlir
+29-01 files

LLVM/project 2b95597mlir/test/Conversion/MemRefToSPIRV bitwidth-emulation.mlir

[mlir][SPIR-V] Add i64 tests for MemRef bitwidth emulation (NFC) (#200724)
DeltaFile
+40-1mlir/test/Conversion/MemRefToSPIRV/bitwidth-emulation.mlir
+40-11 files

LLVM/project 0cb280fllvm/lib/Target/AArch64 AArch64RegisterInfo.td SMEInstrFormats.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to 0 <= Zn <= 7

The `luti6` instruction (table, four registers, 8-bit) should only
allow `0 <= Zn <= 7`, since there's only 3 bits. It actually allows:
```
   luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
   luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```

Fix tablegen to ensure Zn is only allowed in correct range of 0 to 7.
DeltaFile
+15-0llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+5-0llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s
+4-0llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+1-1llvm/lib/Target/AArch64/SMEInstrFormats.td
+25-14 files

LLVM/project fb8cb1blldb/include/lldb/Target Process.h, lldb/source/Plugins/Process/gdb-remote ProcessGDBRemote.cpp ProcessGDBRemote.h

[lldb] Strip pointer metadata in ReadMemoryRanges (#200398)

The Process base class is generally responsible for fixing pointer
metadata before delegating memory reads to concrete Process
specializations. However, ReadMemoryRanges was a direct path into the
derived classes, which made it so that pointer metadata was never
stripped.

This commit creates a non-virtual ReadMemoryRanges in Process, which
clears pointer metadata, before delegating to the new virtual method
DoReadMemoryRanges. This also allows, in the future, to plug into the
memory cache system.
DeltaFile
+86-0lldb/unittests/Target/MemoryTest.cpp
+8-4lldb/include/lldb/Target/Process.h
+11-0lldb/source/Target/Process.cpp
+5-5lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+4-4lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
+114-135 files

LLVM/project fe4b56cutils/bazel/llvm-project-overlay/llvm BUILD.bazel

[bazel] Port 7a435ca (#200749)
DeltaFile
+2-2utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+2-21 files

LLVM/project ce9de13llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll s-barrier.ll

[RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.
DeltaFile
+442-0llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+62-45llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+54-31llvm/test/CodeGen/AMDGPU/s-barrier.ll
+52-14llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+35-31llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
+32-32llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
+677-15342 files not shown
+1,108-44148 files