LLVM/project 71d63d6lldb/test/API/functionalities/inline-sourcefile Makefile

[lldb][test] Fix Makefile for TestInlineSourceFiles.py (#194078)

The test did not build hidden.o with a custom target triple when
specified. Use CFLAGS from Makefile.rules to fix.
DeltaFile
+1-1lldb/test/API/functionalities/inline-sourcefile/Makefile
+1-11 files

LLVM/project cf4f678offload/plugins-nextgen/common/src PluginInterface.cpp

[Offload] Make kernel dynamic memory handling more generic (#194403)

Make sure we do not get unexpected NumThreads and NumBlocks values when
launching non-bare kernels, and generalize the computation of the
dynamic block memory allocation to handle multi-dimensional blocks.

The DynBlockMem fallback is never used in a non-bare context where
`NumBlocks[1]` and `NumBlocks[2]` are not 1 so the code was correct, but
this patch makes sure that assumption is made explicit, and also
future-proofs the code in case we decide to allow multi-dimensional
blocks for fallback dyn block mem in some path.
DeltaFile
+6-2offload/plugins-nextgen/common/src/PluginInterface.cpp
+6-21 files

LLVM/project 916cd55clang/docs ReleaseNotes.rst, clang/include/clang/Parse Parser.h

[Clang] Avoid an extra `FunctionPrototypeScope` for lambda trailing requires-clauses (#194068)

`ParseTrailingRequiresClause` currently always creates a synthetic
`FunctionPrototypeScope`. This is needed for ordinary function
declarators
whose prototype scope has already ended, but it is wrong for lambda
trailing
requires-clauses because they are parsed while the lambda prototype
scope is
still active.

The extra counted scope gives parameters in nested requires-expressions
an
incorrect function scope depth. Split the synthetic prototype-scope
setup from
the trailing requires-clause parser so the lambda path can parse the
clause in
the existing prototype scope.

Fixes: #123854
Fixes: #100774
DeltaFile
+25-0clang/test/CodeGenCXX/mangle-requires.cpp
+14-5clang/lib/Parse/ParseDeclCXX.cpp
+2-2clang/lib/Parse/ParseDecl.cpp
+1-0clang/docs/ReleaseNotes.rst
+1-0clang/include/clang/Parse/Parser.h
+43-75 files

LLVM/project d071e4bclang/lib/CIR/Dialect/Transforms FlattenCFG.cpp, clang/test/CIR/CodeGen try-no-throwing-calls.cpp

[CIR] Fix eraseOp assertion in TryOp flattening with unreachable handlers (#193615)

When a try block has catch handlers but no throwing calls, the handler
regions are unreachable and the TryOp is erased. However, ops inside the
handler regions may reference values that were inlined from the try body
into the parent block, causing an assertion in `eraseOp` ("expected that
op has no uses").

This drops all defined value uses from handler regions before erasing
the TryOp.

Made with [Cursor](https://cursor.com)
DeltaFile
+37-0clang/test/CIR/CodeGen/try-no-throwing-calls.cpp
+7-3clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
+44-32 files

LLVM/project 1b06544clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenBuiltin.cpp

[CIR] Emit frexp, modf, and powi builtins as library calls (#193795)

`__builtin_frexpf`, `__builtin_modf`, `__builtin_powi`, and related
builtins were incorrectly falling through to the `__builtin_isnan`
handler in `emitBuiltinExpr`, which calls `createBoolToInt` /
`createIsFPClass`. This produced a `cir.cast` with an integer result
type when the actual return type is floating-point, failing CIR
verification.

Break out of the switch so these builtins fall through to the
`isLibFunction()` path, which emits them as regular library calls.

Made with [Cursor](https://cursor.com)
DeltaFile
+376-0clang/test/CIR/CodeGenBuiltins/builtin-float.c
+62-4clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+52-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+48-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+14-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+552-55 files

LLVM/project 35fffe0mlir/include/mlir/Dialect/SPIRV/IR SPIRVBase.td, mlir/lib/Dialect/SPIRV/IR SPIRVTypes.cpp

[mlir][spirv] Add missing capabilities for CoopMatrix in TypeExtensionVisitor (#193803)

This adds missing capabilities when CoopMatrix is used with bf16 and
fp8.

Assisted-by: Codex
DeltaFile
+39-0mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
+10-1mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
+8-1mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+57-23 files

LLVM/project c309f17llvm/lib/Transforms/Vectorize VPlanRecipes.cpp

More conservative isSafeToSpeculativelyExecute
DeltaFile
+19-10llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+19-101 files

LLVM/project 0e9ccc1llvm/test/Transforms/LoopVectorize extract-value-widen.ll

Update test after rebase
DeltaFile
+2-5llvm/test/Transforms/LoopVectorize/extract-value-widen.ll
+2-51 files

LLVM/project 65370d6llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Use `post_order` directly as `vp_post_order_shallow` has been removed
DeltaFile
+2-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-21 files

LLVM/project 9bb907bllvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlanTransforms.cpp

Add VPRecipeBase::isSafeToSpeculativelyExecute
DeltaFile
+16-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+2-6llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-0llvm/lib/Transforms/Vectorize/VPlan.h
+22-63 files

LLVM/project 09a556ellvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Update llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Co-authored-by: Ramkumar Ramachandra <artagnon at tenstorrent.com>
DeltaFile
+3-5llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+3-51 files

LLVM/project b9785fcllvm/lib/Transforms/Vectorize VPlanTransforms.cpp

use VPWidenIntOrFpInductionRecipe for canonical IV bailouts
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-11 files

LLVM/project e192fc2llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Addressing code review comments
DeltaFile
+21-22llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+21-221 files

LLVM/project 7722a1fllvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Extend post_order's lifetime
DeltaFile
+5-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+5-31 files

LLVM/project c742b3cllvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Minor stylistic cleanup
DeltaFile
+12-12llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+12-121 files

LLVM/project ada4b13llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h

Don't pass RecipeBuilder

Legacy calls `setRecipe` on all processed recipes but really queries `getRecipe`
for memory operations only, that we don't touch in the scalarization as that
happens after all memory recipes has been processed.
DeltaFile
+1-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-2llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-63 files

LLVM/project 3850033llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Use `reverse`/`IsaPred`
DeltaFile
+2-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-41 files

LLVM/project ff7e66dllvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Just use `vputils::onlyFirstLaneUsed`
DeltaFile
+1-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-71 files

LLVM/project 1c504b3llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h, llvm/test/Transforms/LoopVectorize/AArch64 binop-costs.ll

[VPlan] Scalarize to first-lane-only directly on VPlan

This is needed to enable subsequent https://github.com/llvm/llvm-project/pull/182595.

I don't think we can fully port all scalarization logic from the legacy
path to VPlan-based right now because that would require us to introduce
interleave groups much earlier in VPlan pipeline, and without that we
can't really `assert` this new decision matches the previous CM-based
one. And without those `assert`s it's really hard to ensure we properly
port all the previous logic.

As such, I decided just to implement something much simpler that would
be enough for #182595. However, we perform this transformation before
delegating to the old CM-based decision, so it **is** effective
immediately and taking precedence even for consecutive loads/stores
right away.

Depends on https://github.com/llvm/llvm-project/pull/182592 but is stacked on
top of https://github.com/llvm/llvm-project/pull/182594 to enable linear
stacking for https://github.com/llvm/llvm-project/pull/182595.
DeltaFile
+65-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+5-5llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
+6-0llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+4-2llvm/test/Transforms/LoopVectorize/X86/funclet.ll
+2-2llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
+3-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+85-93 files not shown
+88-119 files

LLVM/project 4d20831llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp WebAssemblyInstrSIMD.td, llvm/test/CodeGen/WebAssembly f16-intrinsics.ll

[WebAssembly] Support f16x8.demote_f32x4_zero (#193564)

Add support for the f16x8.demote_f32x4_zero instruction. This
instruction converts a v4f32 vector to a v4f16 and pads the result with
zeros to fill the 128-bit register.

This enables efficient lowering of fptrunc operations from v4f32 to
v4f16 when the result is zero-extended or when only the low lanes are
needed. A DAG combine is included to recognize these patterns and fold
them into the new instruction.
DeltaFile
+49-18llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+19-0llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
+2-1llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+70-193 files

LLVM/project e52e9e3mlir/test/Dialect/SPIRV/IR types.mlir

[mlir][spirv] Add CoopMatrix type tests for fp8 and bf16 element types (#193805)
DeltaFile
+12-0mlir/test/Dialect/SPIRV/IR/types.mlir
+12-01 files

LLVM/project 0b8f826llvm/lib/Target/PowerPC PPCISelLowering.cpp PPCInstrInfo.td

[PowerPC] Simplify implementation of atomis loads (#191044)

The code for atomic loads is verbose. There are 10 different operations
and 4 memory sizes to support, which means 40 pseudo instructions are
used, with all the details repeated. This PR changes the following:

- Use a loop over the operations and the sizes to create the pseudo
instruction
 - Adds the memory size as last operand to the pseudo instruction
- Updates the C++ code to take advantage of the memory size in the
pseudo instruction
DeltaFile
+75-83llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+32-109llvm/lib/Target/PowerPC/PPCInstrInfo.td
+21-35llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+0-2llvm/lib/Target/PowerPC/PPCISelLowering.h
+128-2294 files

LLVM/project b5f3c12llvm/lib/Target/SPIRV SPIRVPrepareFunctions.cpp SPIRVPrepareFunctions.h, llvm/test/CodeGen/SPIRV/passes SPIRVPrepareFunctions.ll SPIRVPrepareGlobals.ll

[SPIR-V][NewPM] Register SPIRVPrepareFunctions and SPIRVPrepareGlobals with the new pass manager (#194024)

Rename the legacy pass IDs to spirv-prepare-functions and
spirv-prepare-globals for consistency with the other SPIR-V passes and
add opt-driven lit tests for both passes
DeltaFile
+59-0llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareFunctions.ll
+53-0llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareGlobals.ll
+28-14llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+28-0llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.h
+20-7llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.cpp
+23-0llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.h
+211-215 files not shown
+221-2711 files

LLVM/project 4f3bed1llvm/lib/Target/DirectX/DirectXIRPasses PointerTypeAnalysis.cpp, llvm/test/CodeGen/DirectX global-variable.ll

[DirectX] Emit unresolved ptr as i8* (#192086)

We cannot use dxilOpaquePtrReservedName in this test as that is the
wrong type for the null initializer.
DeltaFile
+6-0llvm/test/CodeGen/DirectX/global-variable.ll
+5-0llvm/test/tools/dxil-dis/opaque-pointers-var.ll
+4-0llvm/lib/Target/DirectX/DirectXIRPasses/PointerTypeAnalysis.cpp
+15-03 files

LLVM/project e33bac0lldb/include/lldb/Utility StringExtractorGDBRemote.h, lldb/packages/Python/lldbsuite/test/tools/lldb-server gdbremote_testcase.py

[lldbremote] Implement support for MultiBreakpoint packet (#192919)

This is fairly straightforward, thanks to the helper functions created
in the previous commit.

The following PRs are related to the MultiBreakpoint feature:

* https://github.com/llvm/llvm-project/pull/192910
* https://github.com/llvm/llvm-project/pull/192914
* https://github.com/llvm/llvm-project/pull/192915
* https://github.com/llvm/llvm-project/pull/192919
* https://github.com/llvm/llvm-project/pull/192962
* https://github.com/llvm/llvm-project/pull/192964
* https://github.com/llvm/llvm-project/pull/192971
* https://github.com/llvm/llvm-project/pull/192988
DeltaFile
+68-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+2-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
+2-0lldb/source/Utility/StringExtractorGDBRemote.cpp
+1-0lldb/include/lldb/Utility/StringExtractorGDBRemote.h
+0-1lldb/test/API/functionalities/multi-breakpoint/TestMultiBreakpoint.py
+1-0lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+74-16 files

LLVM/project 2a83068llvm/lib/Target/PowerPC PPCRegisterInfo.td PPCMacroFusion.def

[PowerPC] Enable using HwMode for instructions (#191051)

The HwMode is already used for operands representing an effective
address. It can also be used for general purpose registers but this is
not clear from the naming. This change

- introduces the hw-mode dependent register class `GxRC`, and the
associated register operands
- removes register class `ptr_rc_idx_by_hwmode`, and replaces the only
use with `gxrc`
 - uses the `EQV` instruction as an example how to use the new class
DeltaFile
+8-13llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+3-3llvm/lib/Target/PowerPC/PPCMacroFusion.def
+2-2llvm/lib/Target/PowerPC/PPCInstrInfo.td
+2-2llvm/lib/Target/PowerPC/PPCRegisterClasses.td
+0-4llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
+0-3llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+15-272 files not shown
+17-308 files

LLVM/project fd28e95lldb/source/Plugins/Process/gdb-remote GDBRemoteCommunicationServerLLGS.cpp

fixup! rework static assert for older compilers
DeltaFile
+5-3lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+5-31 files

LLVM/project 42704d2lldb/include/lldb/Utility StringExtractorGDBRemote.h, lldb/packages/Python/lldbsuite/test/tools/lldb-server gdbremote_testcase.py

[lldb-server] Implement support for MultiBreakpoint packet

This is fairly straightforward, thanks to the helper functions created
in the previous commit.

https://github.com/llvm/llvm-project/pull/192910
DeltaFile
+66-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+2-0lldb/source/Utility/StringExtractorGDBRemote.cpp
+2-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
+1-0lldb/include/lldb/Utility/StringExtractorGDBRemote.h
+0-1lldb/test/API/functionalities/multi-breakpoint/TestMultiBreakpoint.py
+1-0lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+72-16 files

LLVM/project 395a563clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-intrinsics.c

[CIR] Vector-Saturating-shift-left intrinsics (#190728)

Part of #185382 

1. Added NEON::BI__builtin_neon_vqshlud_n_s64:
2. Added NEON::BI__builtin_neon_vqshld_n_u64:
3. Added NEON::BI__builtin_neon_vqshld_u_u64:
DeltaFile
+40-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-30clang/test/CodeGen/AArch64/neon-intrinsics.c
+22-2clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+62-323 files

LLVM/project 2e5f8b2libc/config/linux/x86_64 headers.txt, libc/include CMakeLists.txt

[libc] Add sys/ucontext.h header (#194329)

POSIX historically provided <sys/ucontext.h> as an alias for
<ucontext.h>. Some software still includes the sys/ path. Added the
header as a simple wrapper that includes <ucontext.h>, gated to x86_64
alongside the existing ucontext support.
DeltaFile
+14-0libc/include/sys/ucontext.h
+6-0libc/include/CMakeLists.txt
+1-0libc/config/linux/x86_64/headers.txt
+21-03 files