LLVM/project aaf8d4elldb/source/Target AssertFrameRecognizer.cpp, lldb/test/Shell/Recognizer assert.test

Revert "[lldb][windows] add assert frame recognizer Windows (#197282)" (#198263)

This reverts commit 9144646bed5684833fd4c7874c5d1ad78f3f3fe0.
DeltaFile
+13-40lldb/source/Target/AssertFrameRecognizer.cpp
+2-1lldb/test/Shell/Recognizer/assert.test
+15-412 files

LLVM/project d7aa289mlir/lib/ExecutionEngine CudaRuntimeWrappers.cpp

[MLIR][ExecutionEngine] Revert stream/event teardown error suppressions (#194440)

#190717 fixed the race that produced CUDA_ERROR_CONTEXT_IS_DESTROYED on
mgpuStreamDestroy, mgpuStreamWaitEvent, mgpuEventDestroy, and
mgpuEventSynchronize. This changes restores CUDA_REPORT_IF_ERROR on
those four sites.

Keep the CUDA_ERROR_DEINITIALIZED tolerance on mgpuModuleUnload because
that's a separate global-destructor ordering issue, and an error on
module unload is benign anyway.

This is a partial revert of #190563.

Assisted-by: Claude
DeltaFile
+9-29mlir/lib/ExecutionEngine/CudaRuntimeWrappers.cpp
+9-291 files

LLVM/project ae265f5llvm/lib/Transforms/Vectorize VPlanValue.h VPlan.cpp, llvm/unittests/Transforms/Vectorize VPlanTest.cpp

[VPlan] Remove Def pointer from for VPSingleDefRecipes (NFC) (#195483)

For VPSingleDefRecipe, the VPRecipeValue's Def pointer always points
back to the containing VPRecipeBase, which is computable via
static_cast.

Introduce 2 VPRecipeValue subclasses to distinguish the VPValues defined
by VPSingleDefRecipes (VPSingleDefValue), and VPStandaloneValue for
other recipes.

The former does not need to store a pointer to the defining recipe, as
it can be computed via static_cast. This saves 8 bytes for most recipes.
I plan to use the extra bytes to store the type directly in VPValue as
follow-ups.

PR: https://github.com/llvm/llvm-project/pull/195483
DeltaFile
+56-15llvm/lib/Transforms/Vectorize/VPlanValue.h
+23-12llvm/lib/Transforms/Vectorize/VPlan.cpp
+7-7llvm/lib/Transforms/Vectorize/VPlan.h
+2-2llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
+88-364 files

LLVM/project cc16911llvm/include/llvm/Analysis ScalarEvolution.h, llvm/lib/Analysis ScalarEvolution.cpp

Reapply "[SCEV] Introduce loop-uniform SCEV classification." (#196357)

This reverts commit 45d94f67b84bdc5a85aa8e3c5c266914062dcfef.

This recommit contains a small fix: when `loop-computable` are mixed
with `loop-uniform`, it returns `loop-variant (unknown)`.

Original message:
This patch extends `ScalarEvolution::LoopDisposition` with a new
`LoopUniform` state to describe SCEVs that are invariant across all
iterations of a given loop, but may still depend on inner-loop induction
variables.

Unlike `LoopInvariant`, which requires the value to be fully invariant
with respect to the loop, LoopUniform captures expressions that do not
depend on the loop’s own induction variables, yet may vary in nested
loops. This distinction is useful for analyses and optimizations that
reason about per-iteration stability at a specific loop level.


    [12 lines not shown]
DeltaFile
+36-2llvm/test/Analysis/ScalarEvolution/scev-dispositions.ll
+12-12llvm/test/Analysis/ScalarEvolution/max-expr-cache.ll
+24-0llvm/include/llvm/Analysis/ScalarEvolution.h
+20-2llvm/lib/Analysis/ScalarEvolution.cpp
+9-9llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll
+7-7llvm/test/Analysis/ScalarEvolution/different-loops-recs.ll
+108-3210 files not shown
+137-6116 files

LLVM/project d656159mlir/lib/Dialect/Vector/Transforms VectorLinearize.cpp, mlir/test/Dialect/Vector linearize.mlir

[MLIR][Vector] Add linearization patterns for interleave/deinterleave (#197123)
DeltaFile
+64-1mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
+28-0mlir/test/Dialect/Vector/linearize.mlir
+92-12 files

LLVM/project 86a4aa8llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/opencl ddx_fine-error.ll ddy-error.ll

[SPIR-V] Route ISel errors through diagnoseUnsupported (#196899)

Replace report_fatal_error in ISel with diagnoseUnsupported so user gets
readable diagnostics with source location instead of simple errors
DeltaFile
+54-58llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+1-1llvm/test/CodeGen/SPIRV/opencl/ddx_fine-error.ll
+1-1llvm/test/CodeGen/SPIRV/opencl/ddy-error.ll
+1-1llvm/test/CodeGen/SPIRV/opencl/ddy_coarse-error.ll
+1-1llvm/test/CodeGen/SPIRV/opencl/ddy_fine-error.ll
+1-1llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll
+59-637 files not shown
+66-7013 files

LLVM/project 3c6fe49clang/lib/Basic Targets.cpp, clang/lib/Basic/Targets SPIR.h

[OpenCL] Allow mesa3d OS in spirv32 and spirv64 targets (#197148)

Fix libclc `spirv32-mesa-mesa3d` target build error: unknown target
triple 'spirv32-mesa-mesa3d'

Fix libclc `spirv-mesa-mesa3d` target build error: SPIR-V target
requires a Vulkan environment.

mesa3d is a valid OS in llvm triple. This PR enables libclc build for
spirv32-mesa-mesa3d and spirv64-mesa-mesa3d targets.

Note previously spirv[64]-mesa3d- targets used spir[64]-unknown-unknown.
This PR canonicalizes the triples to spirv32[64]-mesa-mesa3d.
DeltaFile
+14-9clang/lib/Basic/Targets/SPIR.h
+12-0clang/test/CodeGen/target-data.c
+9-1clang/test/Frontend/spirv-target-validation.c
+2-2clang/lib/Basic/Targets.cpp
+37-124 files

LLVM/project c47de2fclang/lib/Sema SemaLifetimeSafety.h, clang/test/Sema warn-lifetime-safety-fixits.cpp

[LifetimeSafety] Fix lifetimebound fix-it location for defaulted parameters (#198092)

Earlier, we placed the attribute after the full parameter declaration.
Now, in the default-argument case, we place it after the parameter name.

Fixes #192271
DeltaFile
+14-1clang/test/Sema/warn-lifetime-safety-fixits.cpp
+6-0clang/lib/Sema/SemaLifetimeSafety.h
+20-12 files

LLVM/project f48501bllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp AMDGPUAnnotateUniformValues.cpp, llvm/lib/Transforms/Scalar StructurizeCFG.cpp

[AMDGPU] Replace !isDivergentAt with isUniformAt and vice versa. NFC. (#198253)
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPURewriteUndefForPHI.cpp
+1-1llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
+6-65 files

LLVM/project 1a4e0c9mlir/include/mlir/Dialect/Vector/IR VectorOps.td, mlir/lib/Dialect/Vector/IR VectorOps.cpp

[MLIR][Vector] Add canonicalization for interleave/deinterleave chain (#196979)
DeltaFile
+28-0mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+15-0mlir/test/Dialect/Vector/canonicalize.mlir
+3-2mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
+46-23 files

LLVM/project 14b7250llvm/lib/Target/AMDGPU AMDGPU.td GCNSubtarget.h, llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUMCTargetDesc.cpp

Add Wave64Only
DeltaFile
+20-14llvm/test/MC/AMDGPU/vop3-literal.s
+8-4llvm/lib/Target/AMDGPU/AMDGPU.td
+3-3llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+2-2llvm/test/MC/Disassembler/AMDGPU/gfx1250_wave64_feature.s
+0-4llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+0-2llvm/lib/Target/AMDGPU/GCNSubtarget.h
+33-291 files not shown
+34-307 files

LLVM/project 041f41bllvm/test/tools/llvm-objdump/ELF/RISCV mapping-sym-isa-disassembly.s mapping-sym-isa-bad-string.test, llvm/tools/llvm-objdump llvm-objdump.cpp

[llvm-objdump][RISCV] Use ISA mapping symbols for per-region disassembly (#193448)

llvm-objdump now honours "$x<ISAString>" mapping symbols emitted by the
RISC-V assembler to select the correct instruction decoder for each code
region.

Note that this also makes the --mattr= option of llvm-objdump much less
useful (only regions without an ISA mapping symbol are affected by
--mattr=).

The implementation also caches parsed ISA mapping symbols. We learned
this lesson from our downstream binutils implementation, where the first
version had no cache and made disassembling large binaries very slow, so
I decide introduce cache from the beginning here.

Test changes summary:

- zibi-valid.s: fix a bug where the rv64 test did not pass +64bit to
llvm-objdump, so address operands were not printed correctly.

    [16 lines not shown]
DeltaFile
+133-0llvm/tools/llvm-objdump/llvm-objdump.cpp
+47-0llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-disassembly.s
+46-0llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-bad-string.test
+37-0llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-plain-x.test
+33-0llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-data.s
+33-0llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-rvc.s
+329-07 files not shown
+489-213 files

LLVM/project 84cd7efutils/bazel/llvm-project-overlay/libc BUILD.bazel

[Bazel] Fixes aa1081f (#198236)

This fixes aa1081f2c4cc28477ccbf473302c94d027b7fd1f.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+3-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+3-01 files

LLVM/project e15ce19lldb/source/Commands CommandObjectApropos.cpp, lldb/source/Core UserSettingsController.cpp

[LLDB] Include components of settings paths in apropos search (#194873)

Fixes #188479.

`apropos` was previously only looking at the "name" of the setting,
which is the final part of what I as a user think of as the "name" as in
the "platform.plugin.something.something-else" form. That that form is
in fact the "qualified name".

In this change, I've extended apropos to look in the paths of settings,
that is the part of the settings name isn't the final name. For example,
"qemu-user" will now show a "path" as a result, which you can then look
up with "settings list".

(the alternative was to apply the search to the qualified name of all
settings, but this would result in a lot of results for top level things
like "platform")

This is the new behaviour:

    [37 lines not shown]
DeltaFile
+37-14lldb/source/Commands/CommandObjectApropos.cpp
+28-22lldb/source/Interpreter/OptionValueProperties.cpp
+25-5lldb/test/API/commands/apropos/formatting/TestAproposFormatting.py
+13-0lldb/test/API/commands/settings/TestSettings.py
+9-4lldb/source/Interpreter/Property.cpp
+5-5lldb/source/Core/UserSettingsController.cpp
+117-507 files not shown
+139-6013 files

LLVM/project 2a619c4clang/lib/Analysis BodyFarm.cpp, clang/test/Analysis OSAtomic_mac.cpp

[clang] Fix OSAtomicCompareAndSwap* bodyfarm crash (#197489)

When the user-declared OSAtomicCompareAndSwap* prototype has mismatched
oldValue/ newValue/ *theValue types, BodyFarm previously asserted while
synthesizing the body. It should bail out gracefully and let the
analyzer fall back to generic call semantics.

Fixes #197211

Fix for the crash reproduced with: 
https://godbolt.org/z/9dcb837YE

```
int foo = 0;
bool OSAtomicCompareAndSwap(char32_t __oldValue, int __newValue,
                            volatile int *__theValue);

void baz() {
  if (OSAtomicCompareAndSwap(0, 0, &foo))

    [2 lines not shown]
DeltaFile
+20-0clang/test/Analysis/OSAtomic_mac.cpp
+9-2clang/lib/Analysis/BodyFarm.cpp
+29-22 files

LLVM/project 24dc0d0llvm/include/llvm/Transforms/Utils LoopUtils.h, llvm/lib/Transforms/Scalar LICM.cpp

[LICM][NFC] Factor canHoistLoad out of canSinkOrHoistInst into LoopUtils (#197870)

This patch moves the load-only legality logic from `canSinkOrHoistInst`
into a new `canHoistLoad` helper, declared in
`llvm/Transforms/Utils/LoopUtils.h` and defined in `LICM.cpp`.
`canSinkOrHoistInst` delegates to it for `LoadInst`, so its behavior is
unchanged.

This exposes the load-hoist check for reuse by other passes (e.g. the
GVN min-finding select transform in PR #162259).
DeltaFile
+43-34llvm/lib/Transforms/Scalar/LICM.cpp
+12-0llvm/include/llvm/Transforms/Utils/LoopUtils.h
+55-342 files

LLVM/project 8fb1715llvm/test/Transforms/LoopVectorize/X86 masked_load_store.ll predicate-switch.ll

[LV][NFC] Regenerate CHECK lines for some tests (#197939)
DeltaFile
+897-897llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
+302-339llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
+239-239llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+133-145llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
+91-114llvm/test/Transforms/LoopVectorize/X86/interleave-ptradd-with-replicated-operand.ll
+95-93llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
+1,757-1,8272 files not shown
+1,860-1,9308 files

LLVM/project f5f7f8dllvm/docs AMDGPUUsage.rst, llvm/test/CodeGen/AMDGPU memory-legalizer-non-volatile.ll memory-legalizer-non-volatile.mir

Restack + comments
DeltaFile
+2-14llvm/docs/AMDGPUUsage.rst
+4-4llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
+1-1llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.mir
+7-193 files

LLVM/project a7758a9llvm/test/CodeGen/AMDGPU memory-legalizer-non-volatile.mir

Fix MIR test
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.mir
+3-31 files

LLVM/project 1db57b7llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp SIInstrInfo.h

[AMDGPU][SIMemoryLegalizer] Consider scratch operations as NV=1 if GAS is disabled

- Clarify that `thread-private` MMO flag is still useful.
- If GAS is not enabled (which is the default as of last patch), consider an op as `NV=1` if it's a `scratch_` opcode, or if the MMO is in the private AS.
- Add tests for the new cases.
- Update AMDGPUUsage GFX12.5 memory model
DeltaFile
+181-0llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.mir
+75-36llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
+13-6llvm/docs/AMDGPUUsage.rst
+14-3llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+3-1llvm/lib/Target/AMDGPU/SIInstrInfo.h
+286-465 files

LLVM/project 466eda6lld/test/ELF/lto amdgcn-oses.ll amdgcn.ll

Fix LLD tests
DeltaFile
+3-3lld/test/ELF/lto/amdgcn-oses.ll
+1-1lld/test/ELF/lto/amdgcn.ll
+4-42 files

LLVM/project 2f966a9clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-load-monitor.cl

[AMDGPU][Clang] use a ScopeModel when emitting load_monitor

Assisted-By: Claude Opus 4.6
DeltaFile
+17-9clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+20-0clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
+37-92 files

LLVM/project f020095llvm/test/Transforms/LoopVectorize/RISCV early-exit-live-out.ll

[LV][RISCV] Add strided search test for early-exit vectorization. nfc (#198080)

Co-authored-by: Florian Hahn <flo at fhahn.com>
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
+163-01 files

LLVM/project 0d0f441clang/docs ReleaseNotes.rst, clang/www c_status.html

add exposure
DeltaFile
+27-5clang/docs/ReleaseNotes.rst
+1-1clang/www/c_status.html
+28-62 files

LLVM/project 751f96eclang/test/CodeGenHIP amdgpu-barrier-type.hip, llvm/lib/Target/AMDGPU AMDGPU.h

Address comments
DeltaFile
+25-9clang/test/CodeGenHIP/amdgpu-barrier-type.hip
+16-0llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
+2-2llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
+0-3llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
+45-165 files

LLVM/project 76d2e53llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULowerExecSync.cpp, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll s-barrier.ll

[RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.
DeltaFile
+442-0llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+62-45llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+34-54llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
+54-31llvm/test/CodeGen/AMDGPU/s-barrier.ll
+36-31llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
+33-33llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
+661-19436 files not shown
+1,076-45842 files

LLVM/project 276a3adclang/lib/CodeGen TargetInfo.h CodeGenModule.cpp, clang/lib/CodeGen/Targets AMDGPU.cpp SPIR.cpp

[NFCI][clang] Allow overriding any global variable address space

Allow the target to change the AS of a global variable at will, not just whenever Clang cannot assign one.
This enables the next patch that will specialize LDS GVs for barriers as a separate address space.
DeltaFile
+10-9clang/lib/CodeGen/Targets/AMDGPU.cpp
+12-6clang/lib/CodeGen/TargetInfo.h
+7-8clang/lib/CodeGen/Targets/SPIR.cpp
+11-2clang/lib/CodeGen/CodeGenModule.cpp
+5-6clang/lib/CodeGen/TargetInfo.cpp
+6-3clang/lib/CodeGen/Targets/AVR.cpp
+51-346 files

LLVM/project 5a47757.github CODEOWNERS

[AMDGPU] Add @Pierre-vh and @ritter-x2a as memory model code owners

Covers both SIMemoryLegalizer (code sequence lowering) and InsertWaitcnt.
DeltaFile
+7-3.github/CODEOWNERS
+7-31 files

LLVM/project 3bdd54ebolt/lib/Rewrite RewriteInstance.cpp, bolt/test/AArch64 crel-relocs.s

[BOLT] Add support for CREL code relocations (#196383)

BOLT only checked for .rela sections when deciding whether relocation
mode could be enabled. This caused binaries with SHT_CREL code
relocations (such as .crel.text) to be rejected as missing relocations.

No support for SHT_REL has been added in this patch.

Reference:
https://discourse.llvm.org/t/rfc-crel-a-compact-relocation-format-for-elf/77600

Based on https://github.com/llvm/llvm-project/pull/119150 to address
issue https://github.com/llvm/llvm-project/issues/110407.

Co-Author: @0xfk0
DeltaFile
+34-0bolt/test/AArch64/crel-relocs.s
+11-3bolt/lib/Rewrite/RewriteInstance.cpp
+45-32 files

LLVM/project 17bc1caclang/test/Sema attr-counted-by-late-parsed-struct-ptrs-anon.c, llvm/test/TableGen/GlobalISelEmitter MatchTableOptimizerRecursion.td

Merge branch 'main' into users/kasuga-fj/da-consolidate-acc-gcd
DeltaFile
+204-0llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerRecursion.td
+84-0clang/test/Sema/attr-counted-by-late-parsed-struct-ptrs-anon.c
+64-19llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+46-1mlir/lib/Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp
+3-34llvm/utils/TableGen/GlobalISelEmitter.cpp
+1-34llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+402-886 files not shown
+459-11412 files