LLVM/project 3ad91ceclang/lib/CIR/CodeGen CIRGenModule.cpp

crash on sycl tempAlloca
DeltaFile
+1-1clang/lib/CIR/CodeGen/CIRGenModule.cpp
+1-11 files

LLVM/project a88714blld/ELF/Arch LoongArch.cpp RISCV.cpp, lld/test/ELF loongarch-relocatable-align.s riscv-relocatable-align.s

[ELF] -r: Don't let a weaker offset-0 R_RISCV_ALIGN suppress ALIGN synthesis (#198147)

PR #151639 skipped synthesizing the section-start R_RISCV_ALIGN whenever
any R_RISCV_ALIGN existed at offset 0, regardless of its alignment. This
works with newer LLVM integrated assembler (#150816).

However, older MC and GNU Assembler as of today
(https://sourceware.org/bugzilla/show_bug.cgi?id=33236) can carry a weak
offset-0 R_RISCV_ALIGN (addend 2 => align 4) while its real alignment
requirement comes from a `.option norelax` .balign, which emits no
relocation.

Fix the condition to not suppress synthesis.

Link: https://sourceware.org/bugzilla/show_bug.cgi?id=33236#c4
DeltaFile
+25-0lld/test/ELF/loongarch-relocatable-align.s
+24-0lld/test/ELF/riscv-relocatable-align.s
+12-5lld/ELF/Arch/LoongArch.cpp
+12-5lld/ELF/Arch/RISCV.cpp
+73-104 files

LLVM/project 87fb6b5lldb/source/Plugins/Platform/WebAssembly PlatformWebInspectorWasm.cpp

[lldb] Recheck connection state in webinspector-wasm EnsureConnected (#198701)

m_remote_platform_sp can be non-null while the remote is disconnected
(PlatformWasm::ConnectRemote installs the pointer before the connect
call). Also check IsConnected() so a prior failed connect doesn't make
EnsureConnected falsely report success.
DeltaFile
+1-1lldb/source/Plugins/Platform/WebAssembly/PlatformWebInspectorWasm.cpp
+1-11 files

LLVM/project 6113e16clang-tools-extra/clangd/test non-existent.test, clang/lib/Parse Parser.cpp

[clang] Don't cutoff parsing when load C++ named module failed (#187858)

Since https://github.com/llvm/llvm-project/pull/173130, clang convert
module name pp-token sequence into a annot_module_name token for C++20
module/import directive. This PR follows the changes and correct the
module name handling in clangd.

This PR avoid parsing cutoff when hit an C++ named module loading.

Fixes https://github.com/llvm/llvm-project/issues/181358.

Signed-off-by: yronglin <yronglin777 at gmail.com>
DeltaFile
+82-0clang-tools-extra/clangd/test/non-existent.test
+12-0clang/test/Modules/cxx20-fatal-module-loader-error.cpp
+7-1clang/lib/Parse/Parser.cpp
+101-13 files

LLVM/project d691b3dclang/lib/Tooling/Syntax Tokens.cpp, clang/unittests/Tooling/Syntax TokensTest.cpp

[clang][tooling] Handle C++20 annot_module_name in syntax tokens (#198544)

The token collector will ignore all the annotation tokens, but IIUC, the
annot_module_name shoulde not be ignored.

Signed-off-by: yronglin <yronglin777 at gmail.com>
DeltaFile
+31-3clang/unittests/Tooling/Syntax/TokensTest.cpp
+11-2clang/lib/Tooling/Syntax/Tokens.cpp
+42-52 files

LLVM/project f7fd42bllvm/test/tools/dsymutil/X86 modules.m

[dsymutil] Update modules test for divergence between the two linkers (#198661)

The parallel linker keeps DW_AT_GNU_dwo_id on linked CUs while the
classic linker drops it. Gate the four `CHECK-NOT: DW_AT_GNU_dwo_id`
assertions to a CLASSIC-only prefix so the test reflects the actual,
intended behavior of each linker.
DeltaFile
+9-10llvm/test/tools/dsymutil/X86/modules.m
+9-101 files

LLVM/project 97d8931llvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c
DeltaFile
+67-67llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+33-0llvm/lib/MC/MCDwarf.cpp
+15-15llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+10-0llvm/lib/CodeGen/MachineFunction.cpp
+4-4llvm/test/CodeGen/AMDGPU/debug-frame.ll
+4-0llvm/include/llvm/CodeGen/MachineFunction.h
+133-865 files not shown
+143-9011 files

LLVM/project 20dec1ellvm/lib/Target/AMDGPU SIFrameLowering.cpp SIMachineFunctionInfo.h, llvm/test/CodeGen/AMDGPU amdgpu-spill-cfi-saved-regs.ll

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
DeltaFile
+2,926-0llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
+12-0llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+10-0llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+9-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+2,959-05 files

LLVM/project fff1235llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll gfx-callable-argument-types.ll

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+3,568-2,598llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,912-1,913llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+2,700-12llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+631-631llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+505-510llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+394-399llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+9,710-6,063108 files not shown
+14,825-9,526114 files

LLVM/project 93f5fe8llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll

[AMDGPU] Use register pair for PC spill

Change-Id: Ibedeef926f7ff235a06de65a83087c151f66a416
DeltaFile
+4,331-4,331llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,742-1,740llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+1,562-1,560llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,462-1,460llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+1,238-1,236llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+1,030-1,028llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+11,365-11,35589 files not shown
+18,153-18,04495 files

LLVM/project 0d844f1

[Clang] Default to async unwind tables for amdgcn

To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.

There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.

Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
DeltaFile
+0-00 files

LLVM/project 5ae601fllvm/lib/Target/AMDGPU SIFrameLowering.cpp, llvm/test/CodeGen/AMDGPU debug-frame.ll eliminate-frame-index-v-add-u32.mir

[AMDGPU] Emit entry function Dwarf CFI

Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.

Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+1,405-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+204-12llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
+134-6llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
+114-10llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
+42-5llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+34-0llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
+1,933-3322 files not shown
+2,044-5028 files

LLVM/project b01748fllvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir

[AMDGPU] Implement CFI for non-kernel functions

This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.

Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+2,136-0llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
+1,671-1llvm/test/CodeGen/AMDGPU/debug-frame.ll
+16,779-16993 files not shown
+22,925-1,04999 files

LLVM/project 77a4ba0

[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU

While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).

Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
DeltaFile
+0-00 files

LLVM/project 2dd3cef

[MIR] Error on signed integer in getUnsigned

Previously we effectively took the absolute value of the APSInt, instead
diagnose the unexpected negative value.

Change-Id: I4efe961e7b29fdf1d5f97df12f8139aac12c9219
DeltaFile
+0-00 files

LLVM/project 45f519bmlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

Remove unrelated empty line
DeltaFile
+0-1mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+0-11 files

LLVM/project 52998b1clang/lib/Parse ParseStmt.cpp

format
DeltaFile
+2-2clang/lib/Parse/ParseStmt.cpp
+2-21 files

LLVM/project 403880eclang/docs LanguageExtensions.rst, clang/include/clang/Basic DiagnosticParseKinds.td

rethink parsing
DeltaFile
+10-27clang/lib/Parse/ParseExprCXX.cpp
+22-12clang/lib/Parse/ParseStmt.cpp
+6-6clang/include/clang/Parse/Parser.h
+3-4clang/test/C/C2y/n3267.c
+6-0clang/include/clang/Basic/DiagnosticParseKinds.td
+1-0clang/docs/LanguageExtensions.rst
+48-496 files

LLVM/project 69e298dllvm/lib/Target/DirectX DXILPrettyPrinter.cpp

Reduce use of auto.
DeltaFile
+9-7llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
+9-71 files

LLVM/project 5db7a42llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp, llvm/unittests/Frontend OpenMPIRBuilderTest.cpp

[OpenMP][OMPIRBuilder] Fix nondeterministic dead block removal

The openmp-cli-fuse02.mlir test can fail nondeterministically when
fuseLoops leaves a dead block in the generated function. On AArch64 this
was reproduced as omp_omp.loop.cond3 being emitted with no predecessors,
which breaks CHECK-NEXT in the MLIR LLVM IR translation test.

The issue is in removeUnusedBlocksFromParent. It used
SmallPtrSet::remove_if while HasRemainingUses also queried the same set.
SmallPtrSet iteration order depends on pointer addresses, which can vary
with ASLR, allocation order, or object layout. Erasing one block while
walking the set can therefore change the keep/erase decision for blocks
visited later. The older make_early_inc_range form had the same underlying
defect.

Fix this by collecting all blocks that still have external uses before
erasing any of them. This evaluates every block against the same snapshot
of the erase set and removes the iteration-order dependency.


    [4 lines not shown]
DeltaFile
+51-0llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+11-2llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+62-22 files

LLVM/project 7d2d4a4llvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction avg.ll

[LoongArch] Revert "Add patterns to support vector type average instructions generation" (#198306)

Fixes #198254
DeltaFile
+0-321llvm/test/CodeGen/LoongArch/lasx/ir-instruction/avg.ll
+0-321llvm/test/CodeGen/LoongArch/lsx/ir-instruction/avg.ll
+0-30llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+0-18llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+0-6904 files

LLVM/project 05c1a26libclc/opencl/lib/generic/relational bitselect.inc bitselect.cl

[libclc][NFC] Use clc/shared/ternary_def.inc for bitselect (#198495)

Delete opencl/lib/generic/relational/bitselect.inc
DeltaFile
+0-12libclc/opencl/lib/generic/relational/bitselect.inc
+4-2libclc/opencl/lib/generic/relational/bitselect.cl
+4-142 files

LLVM/project 301e89fllvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction avg.ll

[LoongArch] Revert "Add patterns to support vector type average instructions generation" (#198306)

Fixes #198254
DeltaFile
+0-321llvm/test/CodeGen/LoongArch/lsx/ir-instruction/avg.ll
+0-321llvm/test/CodeGen/LoongArch/lasx/ir-instruction/avg.ll
+0-28llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+0-16llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+0-6864 files

LLVM/project be0ba5clibc/src/__support/math issignaling.h

[libc][math] Undefine issignaling macro for issignaling implementation. (#198686)
DeltaFile
+4-0libc/src/__support/math/issignaling.h
+4-01 files

LLVM/project b8456acmlir/lib/Target/LLVM CMakeLists.txt

[MLIR][CMake] Downgrade ocloc not found diagnostic from WARNING to STATUS (#198296)

When ocloc is not found, the CMake configuration emits a WARNING which
can be noisy for users who have no interest in Intel XeVM native binary
compilation (e.g., those targeting only AMDGPU or NVPTX). Downgrade the
diagnostic to STATUS since this is an expected configuration when ocloc
is not installed. 
For example:
```bash
CMake Warning at /llvm-project/mlir/lib/Target/LLVM/CMakeLists.txt:246 (message):
ocloc not found, MLIRXeVMTarget will not be able to use ocloc for native
binary compilation.
```
DeltaFile
+1-1mlir/lib/Target/LLVM/CMakeLists.txt
+1-11 files

LLVM/project cec3a52libcxx/test/std/numerics/numeric.ops/numeric.ops.midpoint midpoint.float.pass.cpp midpoint.integer.pass.cpp

[libc++] Refactor `std::midpoint` tests and add constraint checks (#175388)

Refactor the `std::midpoint` tests and replace the verify test with
constraint checks.
DeltaFile
+124-99libcxx/test/std/numerics/numeric.ops/numeric.ops.midpoint/midpoint.float.pass.cpp
+79-96libcxx/test/std/numerics/numeric.ops/numeric.ops.midpoint/midpoint.integer.pass.cpp
+50-51libcxx/test/std/numerics/numeric.ops/numeric.ops.midpoint/midpoint.pointer.pass.cpp
+0-44libcxx/test/std/numerics/numeric.ops/numeric.ops.midpoint/midpoint.verify.cpp
+253-2904 files

LLVM/project 1133ca7llvm/tools/llvm-gpu-loader llvm-gpu-loader.h llvm-gpu-loader.cpp

[Offload] Fix llvm-gpu-loader after new argument (#198681)

Summary:
New argument added but was not included here. This gets out of sync just
because there's no reasonable way to build offload and this tool, it's
an unsolvable phase ordering problem so we just dlopen it.
DeltaFile
+12-1llvm/tools/llvm-gpu-loader/llvm-gpu-loader.h
+1-1llvm/tools/llvm-gpu-loader/llvm-gpu-loader.cpp
+13-22 files

LLVM/project 8175b06llvm/lib/Target/DirectX/DirectXIRPasses DXILDebugInfo.cpp, llvm/test/tools/dxil-dis di-subrangetype.ll

[DirectX] Replace DISubrangeType with DIBasicType (#197471)

DISubrangeType did not exist in LLVM 3.7.
DeltaFile
+34-0llvm/test/tools/dxil-dis/di-subrangetype.ll
+12-0llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
+46-02 files

LLVM/project 1e1f3ddlldb/include/lldb/Host JSONTransport.h, lldb/unittests/Host JSONTransportTest.cpp

Fix use-after-free in IOTransport::OnRead on client disconnect (#198548)

When an MCP client disconnects (EOF), `IOTransport::OnRead` called
`handler.OnClosed()` before resetting `m_read_handle`. The MCP server's
`OnClosed` handler erases the client from `m_instances`, destroying both
  the transport (`this`) and the binder (`handler`). The subsequent
`m_read_handle.reset()` then accessed the destroyed transport's member,
  causing a use-after-free (SIGSEGV).

* thread #1, stop reason = signal SIGSEGV: address not mapped to object
(fault address=0x28)
* frame #0: 0x00007ff5d4d5afda
liblldb.so.23.2`lldb_private::transport::IOTransport<lldb_protocol::mcp::ProtocolDescriptor>::OnRead(lldb_private::MainLoopBase&,
lldb_private::transport::JSONTransport<lldb_protocol::mcp::ProtocolDescriptor>::MessageHandler&)
+ 1274
frame #1: 0x00007ff5d1140ad8
liblldb.so.23.0`lldb_private::MainLoopPosix::Run() + 408
frame #2: 0x00007ff5d1760c1c
liblldb.so.23.0`std::thread::_State_impl<std::thre

    [14 lines not shown]
DeltaFile
+18-0lldb/unittests/Host/JSONTransportTest.cpp
+4-2lldb/include/lldb/Host/JSONTransport.h
+22-22 files

LLVM/project 5399e1dclang/lib/StaticAnalyzer/Checkers/WebKit RawPtrRefCallArgsChecker.cpp PtrTypesSemantics.cpp, clang/test/Analysis/Checkers/WebKit call-args.cpp uncounted-obj-arg.cpp

[alpha.webkit.UncountedCallArgsChecker] Check arguments of CXXConstructExpr (#198454)

Check arguments of CXXConstructExpr like CallExpr.

This PR fixes a subtle bug in isCtorOfRetainPtrOrOSPtr that it was missing a check for OSObjectPtr, and it was getting an empty string for the name when getting called on a CXXConstructorDecl as well as similar bugs in isCtorOf* functions.
DeltaFile
+31-9clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
+24-1clang/test/Analysis/Checkers/WebKit/call-args.cpp
+12-7clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
+12-3clang/test/Analysis/Checkers/WebKit/uncounted-obj-arg.cpp
+1-1clang/test/Analysis/Checkers/WebKit/mock-types.h
+80-215 files