[CIR] Upstream missing support for fixed point literal (#193445)
- Upstream CIR CodeGen for fixed point builtin types `_Fract`, `_Accum`
and `_Sat`.
- Upstream CIR CodeGen for fixed point literal
- Part of task https://github.com/llvm/llvm-project/issues/192316
[SLP]Initial support for non-power-of-2 vectorization
Enables non-power-of-2 vectorization within the SLP tree. The root nodes
are still required to be power-of-2, will be addressed in a follow-up
patches.
Reviewers: bababuck, RKSimon, preames, hiraditya, HanKuanChen
Pull Request: https://github.com/llvm/llvm-project/pull/151530
[libc++] Remove full header path from assertion messages (#190060)
This creates additional bloat in programs or debug info, without much
additional value beyond just the file name.
Fixes #190058
[libc++] Implement P1899 `ranges::stride_view` (#65200)
Implement `ranges::stride_view` in libc++. This PR was migrated from
Phabricator (https://reviews.llvm.org/D156924).
Closes #105198
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Co-authored-by: A. Jiang <de34 at live.cn>
[lldb-server] Implement support for MultiBreakpoint packet
This is fairly straightforward, thanks to the helper functions created
in the previous commit.
https://github.com/llvm/llvm-project/pull/192910
[lldb-server][NFC] Factor out code handling breakpoint packets
This commit extracts the code handling breakpoint packets into a helper
function that can be used by a future implementation of the
MultiBreakpointPacket.
It is meant to be purely NFC.
There are two functions handling breakpoint packets (`handle_Z`
and `handle_z`) with a lot of repeated code. This commit did not attempt
to merge the two, as that would make the diff much larger due to subtle
differences in the error message produced by the two. The only
deduplication done is in the code processing a GDBStoppointType, where a
helper struct (`BreakpointKind`) and function (`std::optional<BreakpointKind> getBreakpointKind(GDBStoppointType stoppoint_type)`) was created.
https://github.com/llvm/llvm-project/pull/192910
[asan] API for getting multiple pointer ranges (#181446)
Add an API that, unlike __asan_get_report_address(), can return multiple
addresses and sizes. This allows a handler to inspect the source and the
destination ranges of errors that have more than one pointer involved
(e.g., memcpy-param-overlap).
Fixes #155406.
Assisted-by: Gemini
---------
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
[clang] Tests for CWG1670 and CWG1878: `auto` in conversion functions (#187850)
This PR adds tests for
[CWG1670](https://cplusplus.github.io/CWG/issues/1670.html) "`auto` as
_conversion-type-id_" and
[CWG1878](https://cplusplus.github.io/CWG/issues/1878.html) "`operator
auto` template". The long and short of it is that placeholder type
specifier (`auto`) cannot be used to declare conversion function or
conversion function template. We've always diagnosed template case but
not non-template case.
[clang] Enable part of CWG2598 test in C++20 mode (#189310)
This is a small fix for `#if __cplusplus >= 202002L` condition, which
accidentally disabled this part of the test in C++20 mode.
[libc][math] Refactor dsub family to header-only (#182160)
Refactors the dsub math family to be header-only.
Closes https://github.com/llvm/llvm-project/issues/182159
Target Functions:
- dsubf128
- dsubl
---------
Co-authored-by: bassiounix <muhammad.m.bassiouni at gmail.com>
[LoongArch] Combine rounded vector shifts to VSRLR/VSRAR (#192921)
Add DAG combines to recognize canonical rounded shift patterns and lower
them to target-specific vector rounded shift instructions.
The combines match vector arithmetic and logical right shifts with
rounding implemented as:
```
add (srl/sra X, shift),
(and (srl X, shift-1), 1)
```
and the shift-by-1 variant:
```
add (srl/sra X, 1),
(and X, 1)
```
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[RISCV][GlobalISel] Support RISC-V specific inline asm constraints: 'I', 'J', 'K' and 'S' (#193765)
This patch implements some target-specific constraints for RISC-V: `I`,
`J`, `K` and `S`. These constraints are all for immediate values except
for `S`. The handling of these constraints is implemented with by adding
`RISCVInlineAsmLowering` subclass of `InlineAsmLowering`.
[LoongArch] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector.
On 64-bit targets the generic legalize will use an i64 load and a
scalar_to_vector for us. But on 32-bit targets i64 isn't legal and the
generic legalizer will end up emitting two 32-bit loads.
