LLVM/project 2b07bbflibcxx/docs/Status Cxx26Issues.csv, libcxx/include/__expected expected.h

[libc++] Resolve LWG4366: Heterogeneous comparison of `expected` may be ill-formed  (#185342)

Resolves #171362
- Implement proposed resolution
- Refactor `operator==` code to be more in line with the standard as the
current way was making an explicit `bool()` conversion in the `x.meow()
== y.meow()` cases
- Add test cases
- Update issues paper

---------

Co-authored-by: A. Jiang <de34 at live.cn>
DeltaFile
+20-0libcxx/test/std/utilities/expected/expected.expected/equality/equality.unexpected.pass.cpp
+17-0libcxx/test/support/test_comparisons.h
+12-0libcxx/test/std/utilities/expected/expected.expected/equality/equality.T2.pass.cpp
+8-4libcxx/include/__expected/expected.h
+1-1libcxx/docs/Status/Cxx26Issues.csv
+58-55 files

LLVM/project 4c27981compiler-rt/cmake/Modules CompilerRTUtils.cmake

[compiler-rt] Support triples that start with thumb*- (#206848)

thumb*- can be used as an alias for arm*- (implying -mthumb).
DeltaFile
+5-0compiler-rt/cmake/Modules/CompilerRTUtils.cmake
+5-01 files

LLVM/project 3ad796aorc-rt/unittests ErrorExceptionInteropTest.cpp

[orc-rt] Fix unused function warning in testcase. (#206894)

Fixes -Wunused-function warning on peekAtErrorMessage by only defining
that function when ORC_RT_ENABLE_EXCEPTIONS has been turned on.
DeltaFile
+2-0orc-rt/unittests/ErrorExceptionInteropTest.cpp
+2-01 files

LLVM/project ac493bbclang/lib/Basic/Targets AArch64.cpp, clang/lib/Driver ToolChain.cpp

[TargetParser][AArch64][NFC] Reference ArchInfo via index (#206699)

This removes all relocations from CpuInfos so that the 3-4 kiB structure
can be stored in .rodata. Additionally, the ArchInfos pointer array is
replaced by an ArchInfos value array and the architecture names are
replaced by constexpr references.
DeltaFile
+18-15llvm/utils/TableGen/Basic/ARMTargetDefEmitter.cpp
+9-8llvm/unittests/TargetParser/TargetParserTest.cpp
+8-8llvm/lib/TargetParser/AArch64TargetParser.cpp
+3-3clang/lib/Basic/Targets/AArch64.cpp
+2-2clang/lib/Driver/ToolChain.cpp
+1-1llvm/include/llvm/TargetParser/AArch64TargetParser.h
+41-376 files

LLVM/project 030e141orc-rt/unittests CallableTraitsHelperTest.cpp

[orc-rt] Silence an unneeded-internal-decl warning in testcase. (#206892)

Add an ODR-use of freeVoidVoidNoexcept to silence clang's
-Wunneeded-internal-declaration warning.
DeltaFile
+1-0orc-rt/unittests/CallableTraitsHelperTest.cpp
+1-01 files

LLVM/project 25d46e4llvm/lib/Transforms/IPO MergeFunctions.cpp, llvm/test/Transforms/MergeFunc merge-functions-entry-count-no-alias.ll merge-functions-entry-count-alias.ll

[MergeFunctions] Fix build failure in PR #202218 (#206651)

Address the build issue that caused the original change to be reverted
and reapply the fix.
DeltaFile
+157-0llvm/test/Transforms/MergeFunc/merge-functions-entry-count-no-alias.ll
+51-0llvm/test/Transforms/MergeFunc/merge-functions-entry-count-alias.ll
+23-0llvm/lib/Transforms/IPO/MergeFunctions.cpp
+231-03 files

LLVM/project 0b413b7llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/lib/Target/ARM/AsmParser ARMAsmParser.cpp

[MC][TableGen] Make MCRegisterClasses relocation-free (#206753)

MCRegisterClasses currently store pointers to the register list and the
bit set. Store these three types together in one data structure and use
relative offsets to avoid these relocations and move the large
MCRegisterClasses array from .data.rel.ro into .data. This reduces the
amount of data that needs to be relocated by 86 KB.

This has two side effects: first, MCRegisterClass is not copyable and
the few uses that did copy were changed. Second, the MCRegisterClasses
array is no longer easily accessible as a global (well, it *technically*
is, but that requires the type of the entire storage struct, which I
don't want to expose). Therefore, these accesses need to go through a
function; which shouldn't be too costly and be inlined in an LTO build.
DeltaFile
+98-97llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+95-58llvm/utils/TableGen/RegisterInfoEmitter.cpp
+51-50llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+52-49llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+30-30llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+26-26llvm/test/TableGen/RegClassByHwModeCompressPat.td
+352-31025 files not shown
+482-42431 files

LLVM/project 8461c3borc-rt/include/orc-rt CallableTraitsHelper.h Error.h, orc-rt/unittests CallableTraitsHelperTest.cpp

[orc-rt] CallableTraitsHelper - record operator()'s noexcept-specifier (#206891)

Adds a `bool IsNoexcept` template parameter to CallableTraitsHelper's
impl-class template argument (after the existing IsConst from
4bab60f2c63). It records the noexcept-specification on the callable's
function type.

Specializations are added for noexcept-qualified forms. Existing
specializations propagate `IsNoexcept = false`. CallableArgInfoImpl
exposes the captured bool as `static constexpr bool is_noexcept`.

Existing pass-through adapters (ErrorHandlerTraitsImplAdapter,
ErrorWrapImplAdapter, WFHandlerTraitsImplAdapter) are updated to accept
and discard the additional argument.
DeltaFile
+68-14orc-rt/include/orc-rt/CallableTraitsHelper.h
+73-0orc-rt/unittests/CallableTraitsHelperTest.cpp
+3-2orc-rt/include/orc-rt/Error.h
+1-1orc-rt/include/orc-rt/WrapperFunction.h
+145-174 files

LLVM/project 33b81e3llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/MC/AMDGPU gfx11_asm_vopc.s

rebase

Created using spr 1.3.8-wip
DeltaFile
+19,967-19,033llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+13,779-6,871llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+10,260-9,388llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
+6,927-5,721llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,374-4,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+6,359-3,161llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-neon-instructions.s
+62,666-48,7512,347 files not shown
+262,318-138,9092,353 files

LLVM/project 3d8fafbllvm/lib/Target/X86 X86InsertX87Wait.cpp, llvm/test/CodeGen/X86 x87-insert-wait.mir

[X86] Insert WAIT before fnstenv/fnsave and skip meta-instructions (#204108)

fnstenv/fnsave (FSTENVm/FSAVEm) are non-waiting, so they don't
synchronize a pending FP exception; the WAIT pass shouldn't skip the
WAIT before them.

Also skip meta-instructions when finding the next op so WAIT placement
doesn't depend on -g.

Added a new X87ControlKind enum class to classify x87 control
instructions in the pass, replacing the existing ad-hoc switches.

Found via @jlebar's X86 LLVM bug-hunt / FuzzX effort:

https://github.com/SemiAnalysisAI/FuzzX/blob/master/x86/bugs/047-x87-insertwait-too-eager-skip

cc @jlebar
DeltaFile
+72-0llvm/test/CodeGen/X86/x87-insert-wait.mir
+25-27llvm/lib/Target/X86/X86InsertX87Wait.cpp
+97-272 files

LLVM/project 1ec43aeflang/lib/Lower/OpenMP OpenMP.cpp, mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

[flang][OpenMP] Lower target in_reduction for host fallback

Enable host-fallback lowering for target in_reduction in Flang and MLIR OpenMP translation.

Model target in_reduction through the matching map entry, force address-preserving implicit mapping for Flang in_reduction list items, and emit the host-side task-reduction lookup with __kmpc_task_reduction_get_th_data. The runtime entry point takes and returns a generic, default-address-space pointer, so normalize a non-default-address-space captured pointer to the generic address space before the call and cast the returned private pointer back to the map block argument's address space, mirroring the in_reduction handling on omp.taskloop. Unsupported device/offload-entry and richer reduction forms remain diagnosed.

Add Flang lowering, MLIR verifier/translation, and LLVM IR tests for the supported host-fallback path, including a non-default-address-space case, and the remaining unsupported cases.
DeltaFile
+131-14mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+95-21mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+110-3mlir/test/Target/LLVMIR/openmp-todo.mlir
+107-0mlir/test/Target/LLVMIR/openmp-target-in-reduction.mlir
+88-15flang/lib/Lower/OpenMP/OpenMP.cpp
+77-0mlir/test/Target/LLVMIR/openmp-target-in-reduction-multi.mlir
+608-5314 files not shown
+977-8020 files

LLVM/project 67f027cclang/lib/Driver ToolChain.cpp, clang/lib/Driver/ToolChains Clang.cpp

[TargetParser][AArch64][NFC] Use StringTable (#206698)

Store strings in a StringTable instead of referencing them via pointers.
This permits some data structures to be stored in .rodata instead of
.data.rel.ro, as they no longer require relocations. In particular this
affects the 16 kiB AArch64::Extensions.
DeltaFile
+35-32llvm/lib/TargetParser/AArch64TargetParser.cpp
+40-18llvm/utils/TableGen/Basic/ARMTargetDefEmitter.cpp
+27-20llvm/include/llvm/TargetParser/AArch64TargetParser.h
+20-20llvm/unittests/TargetParser/TargetParserTest.cpp
+8-8clang/lib/Driver/ToolChain.cpp
+2-1clang/lib/Driver/ToolChains/Clang.cpp
+132-991 files not shown
+133-1007 files

LLVM/project 4bab60forc-rt/include/orc-rt CallableTraitsHelper.h Error.h, orc-rt/unittests CallableTraitsHelperTest.cpp

[orc-rt] CallableTraitsHelper - record call operator's const-qualifier (#206889)

Adds a leading `bool IsConst` template parameter to
CallableTraitsHelper's impl-class template argument to record the
const-qualifier on the callable's function type.

Existing specializations are updated to report their const qualifiers,
and a new specialization handles `RetT(ArgTs...) const`.

CallableArgInfo is updated to expose the captured bool as `static
constexpr bool is_const`.

Existing impls that do not consume the new parameter are adapted via
pass-through wrappers (ErrorHandlerTraitsImplAdapter,
ErrorWrapImplAdapter, WFHandlerTraitsImplAdapter) that discard the
leading bool.
DeltaFile
+63-0orc-rt/unittests/CallableTraitsHelperTest.cpp
+28-19orc-rt/include/orc-rt/CallableTraitsHelper.h
+8-2orc-rt/include/orc-rt/Error.h
+4-1orc-rt/include/orc-rt/WrapperFunction.h
+103-224 files

LLVM/project bae9ddcclang/lib/Format WhitespaceManager.cpp, clang/unittests/Format FormatTestComments.cpp

[clang-format] Fix a bug in recognizing trailing comments (#206393)

Test cases are borrowed/adapted from #196760.

Fixes #196663
DeltaFile
+36-0clang/unittests/Format/FormatTestComments.cpp
+2-0clang/lib/Format/WhitespaceManager.cpp
+38-02 files

LLVM/project 2301475flang/lib/Lower OpenACC.cpp, flang/test/Lower/OpenACC acc-declare-managed-no-global-ctor.f90

Revert "[flang][openacc] Skip implicit global declare constructor in managed mode" (#206884)

Reverts llvm/llvm-project#206610 as this might not be the right approach
DeltaFile
+0-30flang/test/Lower/OpenACC/acc-declare-managed-no-global-ctor.f90
+4-19flang/lib/Lower/OpenACC.cpp
+4-492 files

LLVM/project 7306ea2flang/lib/Lower OpenACC.cpp, flang/test/Lower/OpenACC acc-declare-managed-no-global-ctor.f90

Revert "[flang][openacc] Skip implicit global declare constructor in managed …"

This reverts commit b213a5454f178dabb07514454cf83dc38e41fdad.
DeltaFile
+0-30flang/test/Lower/OpenACC/acc-declare-managed-no-global-ctor.f90
+4-19flang/lib/Lower/OpenACC.cpp
+4-492 files

LLVM/project 4a11eb3orc-rt/include/orc-rt CallableTraitsHelper.h

[orc-rt] Drop redundant 'public' base access specifiers. NFC. (#206883)
DeltaFile
+9-10orc-rt/include/orc-rt/CallableTraitsHelper.h
+9-101 files

LLVM/project 3f849ffflang/lib/Lower/OpenMP OpenMP.cpp, mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

[flang][OpenMP] Lower target in_reduction for host fallback

Enable host-fallback lowering for target in_reduction in Flang and MLIR OpenMP translation.

Model target in_reduction through the matching map entry, force address-preserving implicit mapping for Flang in_reduction list items, and emit the host-side task-reduction lookup with __kmpc_task_reduction_get_th_data. The runtime entry point takes and returns a generic, default-address-space pointer, so normalize a non-default-address-space captured pointer to the generic address space before the call and cast the returned private pointer back to the map block argument's address space, mirroring the in_reduction handling on omp.taskloop. Unsupported device/offload-entry and richer reduction forms remain diagnosed.

Add Flang lowering, MLIR verifier/translation, and LLVM IR tests for the supported host-fallback path, including a non-default-address-space case, and the remaining unsupported cases.
DeltaFile
+131-14mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+95-21mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+110-3mlir/test/Target/LLVMIR/openmp-todo.mlir
+107-0mlir/test/Target/LLVMIR/openmp-target-in-reduction.mlir
+88-15flang/lib/Lower/OpenMP/OpenMP.cpp
+77-0mlir/test/Target/LLVMIR/openmp-target-in-reduction-multi.mlir
+608-5315 files not shown
+1,000-8021 files

LLVM/project e7290b1llvm/docs/CommandGuide llvm-debuginfo-analyzer.rst, llvm/include/llvm/DebugInfo/LogicalView/Readers LVIRReader.h

[llvm-debuginfo-analyzer] Add support for LLVM IR format. (#202120)

llvm-debuginfo-analyzer is a command line tool that processes debug
info contained in a binary file and produces a debug information
format agnostic “Logical View”, which is a high-level semantic
representation of the debug info, independent of the low-level format.

Add support for the LLVM IR format and be able to generate logical
views. Both textual representation (.ll) and bitcode (.bc) formats
are supported.

This relands https://github.com/llvm/llvm-project/pull/135440,
which was:
reverted in: https://github.com/llvm/llvm-project/pull/199890
relanded in: https://github.com/llvm/llvm-project/pull/200603
reverted in: https://github.com/llvm/llvm-project/pull/201019

It includes the fixes for the buildbots problems.
DeltaFile
+2,630-0llvm/lib/DebugInfo/LogicalView/Readers/LVIRReader.cpp
+362-0llvm/unittests/DebugInfo/LogicalView/IRReaderTest.cpp
+303-0llvm/include/llvm/DebugInfo/LogicalView/Readers/LVIRReader.h
+87-134llvm/docs/CommandGuide/llvm-debuginfo-analyzer.rst
+168-0llvm/test/tools/llvm-debuginfo-analyzer/IR/08-ir-multiple-compile-units.test
+151-0llvm/test/tools/llvm-debuginfo-analyzer/IR/01-ir-select-logical-elements.test
+3,701-13435 files not shown
+5,420-15941 files

LLVM/project 62ee075llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

[AArch64][ISel] Fix comment misalignment (NFC) (#206878)

Fix comment misalignment introduced by newly-added code in commit
2668971e14219205ddf6b1f753cf83f7cb22022a
DeltaFile
+2-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-21 files

LLVM/project b5c5551orc-rt/include/orc-rt CallableTraitsHelper.h

[orc-rt] Simplify CallableTraitsHelper specialization inheritance NFC. (#206869)

Make CallableTraitsHelper specializations inherit directly from ImplT.
This is a no-op, but will simplify upcoming patches that will capture
more information about the callable type.
DeltaFile
+4-4orc-rt/include/orc-rt/CallableTraitsHelper.h
+4-41 files

LLVM/project 905c6d9llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv pr206788.ll

[RISCV] Disable combineVectorSizedSetCCEquality when fixed length vectors are disabled. (#206829)

With VLEN=32 we don't support fixed vectors even if vector instructions are
enabled.

Fixes #206788
DeltaFile
+30-0llvm/test/CodeGen/RISCV/rvv/pr206788.ll
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+31-12 files

LLVM/project f5ebc1allvm/lib/Target/AMDGPU AMDGPUMCInstLower.cpp, llvm/test/CodeGen/AMDGPU mcinstlower-external-symbol-reloc.mir

[AMDGPU] Apply target flag specifier when lowering MO_ExternalSymbol operands (#202389)

The MO_ExternalSymbol case in AMDGPUMCInstLower dropped the operand
target flags emitting the wrong relocation type
DeltaFile
+19-0llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
+2-1llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+21-12 files

LLVM/project e3f2e35clang/lib/Serialization ASTCommon.cpp

[Serialization] Delete an unreachable BlockDecl check (NFC) (#206298)

`needsAnonymousDeclarationNumber()` takes a `const NamedDecl *`. Both
`BlockDecl` and `NamedDecl` derive from `Decl`, in other words they're
siblings.

* https://clang.llvm.org/doxygen/classclang_1_1BlockDecl.html
* https://clang.llvm.org/doxygen/classclang_1_1NamedDecl.html

Thus `isa<BlockDecl>(D)` is statically false.
DeltaFile
+1-1clang/lib/Serialization/ASTCommon.cpp
+1-11 files

LLVM/project b0e490aclang/lib/Serialization ASTCommon.cpp, clang/test/Modules modules-lambda-dependent-crash.cppm modules-local-class-dependent-crash.cppm

[Clang][Modules] Skip anonymous declaration numbering for local tags in dependent contexts (#202248)

Local tag declarations (classes, structs, enums, and lambdas) defined
within function template bodies or class templates do not require ODR
merging at the local declaration level across different modules. ODR
consistency is already guaranteed because the instantiator only walks
the canonical template definition body, which instantiates its own copy
of the local class.

Merging them across different modules causes their member definitions
(like methods or call operators) to be canonicalized to one module,
while the instantiator walks the template body from another module.
Since local variables within template bodies are not merged, this
mismatch leads to assertion crashes during template instantiation in
`LocalInstantiationScope::findInstantiationOf`.

Fixes https://github.com/llvm/llvm-project/issues/206203.

Co-authored-by: ipopov <ipopov at google.com>
DeltaFile
+73-0clang/test/Modules/modules-lambda-dependent-crash.cppm
+70-0clang/test/Modules/modules-local-class-dependent-crash.cppm
+6-2clang/lib/Serialization/ASTCommon.cpp
+149-23 files

LLVM/project 58e1038llvm/lib/Target/X86 X86TargetVerifier.cpp, llvm/test/Verifier/X86 inline-asm-registers.ll

[X86] Verify inline-asm register operands against the subtarget

Inline asm can name physical registers that require a subtarget feature
the selected subtarget lacks: zmm and mask (k) registers need AVX-512,
ymm registers need AVX. The subtarget is derived from the function's
target-cpu/target-features, so no MachineFunction is required.
DeltaFile
+33-0llvm/lib/Target/X86/X86TargetVerifier.cpp
+27-0llvm/test/Verifier/X86/inline-asm-registers.ll
+60-02 files

LLVM/project b9a267cclang CMakeLists.txt

fixup! [clang] Rename CLANG_DEFAULT_PIE_ON_LINUX to CLANG_DEFAULT_PIE
DeltaFile
+5-0clang/CMakeLists.txt
+5-01 files

LLVM/project 14a19cellvm/lib/Support/Windows Path.inc

Fix Windows Path Separator issues in create_symlink and readlink (#206665)

- Force create_symlink target path to use backslashes on Windows, as
NTFS reparse points require backslashes.
- Normalize readlink output to native path separators to match preferred
style.

This fixes the following test failure:

```
PS C:\src\chromium\src\third_party\llvm> .\build_repro\unittests\Support\SupportTests.exe --gtest_filter=FileSystemTest.CreateRelativeDirectorySymlink
[ RUN      ] FileSystemTest.CreateRelativeDirectorySymlink
Test Directory: C:/src/temp/file-system-test-a3fd42
C:\src\chromium\src\third_party\llvm\llvm\unittests\Support\Path.cpp(896): error: Value of: fs::is_directory(Link)                                                                                                                                                                                                                     Actual: false
Expected: true
```
DeltaFile
+2-1llvm/lib/Support/Windows/Path.inc
+2-11 files

LLVM/project 14d9c0cllvm/test/MC/ARM cde-integer.s mve-load-store.s, llvm/utils/TableGen AsmMatcherEmitter.cpp

[AsmMatcher] Report a near-miss when all candidates mismatch multiple operands (#206390)

In the ReportMultipleNearMisses path, an opcode that mismatches more
than one operand is dropped, and its first near-miss is dropped with it. If
every opcode is dropped this way, the parser only reports a generic
"invalid instruction".

Now keep the first near-miss of each such opcode, and use it only when
no other opcode gives a near-miss.

Assisted-by: claude-opus
DeltaFile
+25-25llvm/test/MC/ARM/cde-integer.s
+16-16llvm/test/MC/ARM/mve-load-store.s
+21-1llvm/utils/TableGen/AsmMatcherEmitter.cpp
+10-10llvm/test/MC/ARM/bfloat16-a32-errors2.s
+8-8llvm/test/MC/ARM/mve-misc.s
+8-8llvm/test/MC/ARM/diagnostics.s
+88-6813 files not shown
+129-11019 files

LLVM/project 483d534llvm/include/llvm/TargetParser SubtargetFeature.h, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[TargetParser][NFC] Make FeatureBitset iterable (#206394)

FeatureBitset had no way to iterate its bits, so callers scanned all
MAX_SUBTARGET_FEATURES positions by hand.
This adds begin()/end() that yield the index of each set bit, skipping
unset bits with countr_zero.
Callers can now write `for (unsigned Feature: Features)`. 

Assisted-by: claude-opus
DeltaFile
+40-0llvm/include/llvm/TargetParser/SubtargetFeature.h
+31-0llvm/unittests/TargetParser/TargetParserTest.cpp
+4-6llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+4-6llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+3-5llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
+3-5llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+85-222 files not shown
+89-298 files