LLVM/project be43dcelibc/src/__support/CPP string.h, libc/test/src/__support/CPP string_test.cpp

Handle self-move-assignment
DeltaFile
+7-0libc/test/src/__support/CPP/string_test.cpp
+3-0libc/src/__support/CPP/string.h
+10-02 files

LLVM/project 5cac910libc/src/string/memory_utils utils.h op_generic.h

[libc][memory_utils] Rename shadowed load/store to avoid ADL ambiguity

When compiling with MSVC for non-x86 architectures, `op_generic.h` picks a non-builtin type for generic_v128 and friends: https://github.com/llvm/llvm-project/blob/cad3c95a89c48d714a71f6e8b4af6f3e3ab100ea/libc/src/string/memory_utils/op_generic.h#L54-L57

This means calls to `load` and `store` trigger ADL with the `load` definition in `memory_utils/utils.h` as the other candidate.
DeltaFile
+5-5libc/src/string/memory_utils/utils.h
+3-3libc/src/string/memory_utils/op_generic.h
+8-82 files

LLVM/project f5c4beelibc/src/__support/CPP string.h CMakeLists.txt, libc/test/src/__support/CPP string_test.cpp

Handling aliasing
DeltaFile
+86-40libc/src/__support/CPP/string.h
+36-9libc/test/src/__support/CPP/string_test.cpp
+1-0libc/src/__support/CPP/CMakeLists.txt
+123-493 files

LLVM/project ed99f7elibc/src/__support/CPP string.h CMakeLists.txt, libc/test/UnitTest LibcTest.cpp

[libc][cpp::string] Allocate fewer temp strings in operator= and +=

This PR generally updates `cpp::string` to avoid incidental allocations. Specifically, it:

- Updates `opreator=(string_view)` to avoid allocating a temporary string: https://github.com/llvm/llvm-project/blob/67ebc4b221c3e94028b33004cd5cd08deee95048/libc/src/__support/CPP/string.h#L106-L108
- Changes `operator+=(const string&)` to accept a `string_view` so that strings may be appended without allocation.
- Makes the `string(string_view)` constructor explicit. Before, there were non-obvious allocations because of the implicit conversion.

This PR assumes that self-assignment and self-appends are not supported with `cpp::string`, and adds debug asserts preventing them. Currently, assignment doesn't work. `cpp::string s = "abc"; s = s;` will just zero out the string. This PR is a slight regression in that `operator+=(const cpp::string&)` previously worked, but now it errors in debug mode, and would result in a use-after-free without the assert statement. I don't think self-append/self-assignment is something `cpp::string` needs to support, so I omitted it, but if a reviewer thinks this behavior is important happy to amend this PR.
DeltaFile
+24-14libc/src/__support/CPP/string.h
+13-0libc/test/src/__support/CPP/string_test.cpp
+4-1libc/test/src/stdlib/realpath_test.cpp
+4-1utils/bazel/llvm-project-overlay/libc/test/src/__support/CPP/BUILD.bazel
+2-0libc/src/__support/CPP/CMakeLists.txt
+1-1libc/test/UnitTest/LibcTest.cpp
+48-172 files not shown
+51-178 files

LLVM/project 2ba865dlibc/src/__support/CPP string.h, libc/test/src/__support/CPP string_test.cpp

Remove now unused deps
DeltaFile
+18-17libc/src/__support/CPP/string.h
+14-5libc/test/src/__support/CPP/string_test.cpp
+32-222 files

LLVM/project 4f8de76llvm/lib/Transforms/Coroutines CoroSplit.cpp, llvm/test/Transforms/Coroutines coro-split-dbg-labels.ll coro-split-resume-entry-count-no-suspend.ll

[profcheck][coro] Adding Branch weights PGO in Coroutines Passes (#184466)

The CoroSplit and CoroFrame generate several control flow instructions
(`br`, `select`, `switch`) that previously lacked `!prof` branch weight
metadata.

When a coroutine is split, most basic blocks are simply cloned into the
generated functions (`.resume`, `.destroy`, and `.cleanup`) and don't
actually change their internal structure or layout. This PR changes:

1. Dispatch Branch Weights:
Since the original coroutine already ran through PGO, we already have
the `SuspendFreqs` records telling us exactly how many times each
suspension point was executed in the real world.

In the new clone `.resume` functions, the compiler generates new routing
`switch` instruction to direct the traffic. Instead of guessing the
probabilities for these new routes, we simply look back at the
`SuspendFreqs` records, calculate the exact execution frequency and

    [55 lines not shown]
DeltaFile
+200-18llvm/test/Transforms/Coroutines/coro-split-dbg-labels.ll
+72-0llvm/test/Transforms/Coroutines/coro-split-resume-entry-count-no-suspend.ll
+66-2llvm/lib/Transforms/Coroutines/CoroSplit.cpp
+65-0llvm/test/Transforms/Coroutines/coro-split-resume-entry-count.ll
+0-44llvm/utils/profcheck-xfail.txt
+18-14llvm/test/Transforms/Coroutines/coro-noop.ll
+421-788 files not shown
+527-10114 files

LLVM/project f835756clang/lib/Sema SemaOverload.cpp, clang/test/SemaCXX deleted-function-deduction-failure.cpp deduced-return-type-cxx14.cpp

[clang][sema] Call expressions are constructed for undeduced deleted functions (#208488)

The deleted function path of overload resolution always constructed a CallExpr node
for the called function even if the function could not be deduced.
This case is handled in other paths by DiagnoseUseOfDecl which does perform that
test. The delete path cannot use that path though, as DiagnoseUseOfDecl rejects
deleted functions, and the entire point of this code is to permit the continued
evaluation of code even if the resolved function was deleted.

To fix this we now manually check for a complete type before continuing to construct
a potentially bogus CallExpr.
DeltaFile
+49-0clang/test/SemaCXX/deleted-function-deduction-failure.cpp
+4-0clang/lib/Sema/SemaOverload.cpp
+3-0clang/test/SemaCXX/deduced-return-type-cxx14.cpp
+56-03 files

LLVM/project a61b4c3libc/src/__support/CPP string.h, libc/test/src/__support/CPP string_test.cpp

Handle self-move-assignment
DeltaFile
+7-0libc/test/src/__support/CPP/string_test.cpp
+3-0libc/src/__support/CPP/string.h
+10-02 files

LLVM/project 3101edflibc/src/__support/CPP string.h CMakeLists.txt, libc/test/src/__support/CPP string_test.cpp

Handling aliasing
DeltaFile
+86-40libc/src/__support/CPP/string.h
+36-9libc/test/src/__support/CPP/string_test.cpp
+1-0libc/src/__support/CPP/CMakeLists.txt
+123-493 files

LLVM/project 709fba5libc/src/__support/CPP string.h CMakeLists.txt, libc/test/UnitTest LibcTest.cpp

[libc][cpp::string] Allocate fewer temp strings in operator= and +=

This PR generally updates `cpp::string` to avoid incidental allocations. Specifically, it:

- Updates `opreator=(string_view)` to avoid allocating a temporary string: https://github.com/llvm/llvm-project/blob/67ebc4b221c3e94028b33004cd5cd08deee95048/libc/src/__support/CPP/string.h#L106-L108
- Changes `operator+=(const string&)` to accept a `string_view` so that strings may be appended without allocation.
- Makes the `string(string_view)` constructor explicit. Before, there were non-obvious allocations because of the implicit conversion.

This PR assumes that self-assignment and self-appends are not supported with `cpp::string`, and adds debug asserts preventing them. Currently, assignment doesn't work. `cpp::string s = "abc"; s = s;` will just zero out the string. This PR is a slight regression in that `operator+=(const cpp::string&)` previously worked, but now it errors in debug mode, and would result in a use-after-free without the assert statement. I don't think self-append/self-assignment is something `cpp::string` needs to support, so I omitted it, but if a reviewer thinks this behavior is important happy to amend this PR.
DeltaFile
+24-14libc/src/__support/CPP/string.h
+13-0libc/test/src/__support/CPP/string_test.cpp
+4-1libc/test/src/stdlib/realpath_test.cpp
+4-1utils/bazel/llvm-project-overlay/libc/test/src/__support/CPP/BUILD.bazel
+2-0libc/src/__support/CPP/CMakeLists.txt
+1-1libc/test/UnitTest/LibcTest.cpp
+48-172 files not shown
+51-178 files

LLVM/project 09fad8elibc/src/__support/CPP string.h, libc/test/src/__support/CPP string_test.cpp

Remove now unused deps
DeltaFile
+18-17libc/src/__support/CPP/string.h
+14-5libc/test/src/__support/CPP/string_test.cpp
+32-222 files

LLVM/project a10a36dlibc/src/string/memory_utils utils.h op_generic.h

[libc][memory_utils] Rename shadowed load/store to avoid ADL ambiguity

When compiling with MSVC for non-x86 architectures, `op_generic.h` picks a non-builtin type for generic_v128 and friends: https://github.com/llvm/llvm-project/blob/cad3c95a89c48d714a71f6e8b4af6f3e3ab100ea/libc/src/string/memory_utils/op_generic.h#L54-L57

This means calls to `load` and `store` trigger ADL with the `load` definition in `memory_utils/utils.h` as the other candidate.
DeltaFile
+5-5libc/src/string/memory_utils/utils.h
+3-3libc/src/string/memory_utils/op_generic.h
+8-82 files

LLVM/project fec3679mlir/lib/Conversion/VectorToLLVM ConvertVectorToLLVM.cpp

[mlir][VectorToLLVM] Fix comment still referring to undef instead of poison (NFC) (#211196)

When updating operators from undef (deprecated) to poison, the
associated comment wasn't updated accordingly. This PR fixes it.
DeltaFile
+1-1mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
+1-11 files

LLVM/project 30fb6a7llvm/lib/Target/X86 X86RegisterInfo.cpp, llvm/test/CodeGen/X86 zero-call-used-regs-soft-float.ll

[X86] Don't emit x87 register scrub when x87 is unavailable (#211146)

### Summary

`-fzero-call-used-regs=all` always emits the x87 `fldz`/`fstp` scrub
sequence, without checking whether x87 is enabled. In a function built
with `-mno-x87` or `-msoft-float`, this injects 16 `x87` instructions
into a translation unit that must not touch the FPU:

```asm
// test.c
int f(int x) { return x + 1; }

$ clang -O2 -S -mno-x87 -msoft-float -mno-sse \
        -fzero-call-used-regs=all --target=x86_64-linux-gnu test.c -o -
f:
        leal    1(%rdi), %eax
        fldz
        ...          # 8x fldz

    [30 lines not shown]
DeltaFile
+99-0llvm/test/CodeGen/X86/zero-call-used-regs-soft-float.ll
+6-0llvm/lib/Target/X86/X86RegisterInfo.cpp
+105-02 files

LLVM/project cad3c95clang/test/CodeGen/LoongArch/lsx inline-asm-operand-types.c, llvm/lib/Target/LoongArch LoongArchISelLowering.cpp

[LoongArch] Support i128 operands for LSX inline assembly (#211464)

Allow `i128` values to be used with the `f` inline assembly constraint
when targeting LSX.

Although `i128` is not a legal LSX value type, it naturally maps to a
single 128-bit LSX vector register for inline assembly. This enables
instructions such as `vadd.q` to operate directly on `__int128` operands
without requiring explicit vector types.
DeltaFile
+21-0llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-types.ll
+15-0clang/test/CodeGen/LoongArch/lsx/inline-asm-operand-types.c
+2-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+38-03 files

LLVM/project 050c2efmlir/include/mlir/Dialect/Tosa/IR TosaTypesBase.td, mlir/test/Conversion/TosaToLinalg tosa-to-linalg-pipeline.mlir

Reland "[mlir][tosa] Combine unranked/ranked tensor types into single type" (#211708)

Reverts llvm/llvm-project#211701
Relands llvm/llvm-project#209737

The buildbot failure was misattributed to this change.
Real cause is https://github.com/llvm/llvm-project/pull/207274
DeltaFile
+40-68mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
+20-20mlir/test/Dialect/Tosa/invalid.mlir
+5-5mlir/test/Dialect/Tosa/verifier.mlir
+1-1mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
+66-944 files

LLVM/project dd22220mlir/include/mlir/Dialect/Tosa/IR TosaTypesBase.td, mlir/test/Conversion/TosaToLinalg tosa-to-linalg-pipeline.mlir

Revert "Revert "[mlir][tosa] Combine unranked/ranked tensor types into single…"

This reverts commit 257e81f2e9a67cb857bd6f801e1708c96bee99e4.
DeltaFile
+40-68mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
+20-20mlir/test/Dialect/Tosa/invalid.mlir
+5-5mlir/test/Dialect/Tosa/verifier.mlir
+1-1mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
+66-944 files

LLVM/project 755f3e4llvm/lib/Target/ARM ARMAsmPrinter.cpp ARMISelLowering.cpp, llvm/test/CodeGen/ARM elf-preemption.ll weak-hidden-pic.ll

[ARM] Use .reloc for dso_local weak symbols in PIC mode instead of GOT indirection (#209660)

In ARM ELF PIC mode, weak symbols referenced via the constant pool use a
PC-relative expression like `.long sym-(.LPC+8)`. The assembler eagerly
resolves this when the symbol and reference are in the same section,
which prevents the linker from overriding a weak definition with a
non-weak one from another object file.

The previous approach forced *all* weak symbols through GOT indirection.
That works, but `dso_local` weak symbols with hidden/protected
visibility are non-preemptible — they don't need GOT indirection, and
the extra load is wasteful. This patch emits a `.reloc` directive for
such symbols instead, forcing the assembler to produce an `R_ARM_REL32`
relocation while keeping a direct PC-relative reference from the
constant pool.

Default-visibility weak symbols (even `dso_local`) remain routed through
the GOT because they stay exported and preemptible in shared objects,
and `R_ARM_REL32` against an external symbol cannot be used when making

    [2 lines not shown]
DeltaFile
+103-4llvm/test/CodeGen/ARM/elf-preemption.ll
+34-0llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+8-6llvm/test/CodeGen/ARM/weak-hidden-pic.ll
+3-8llvm/lib/Target/ARM/ARMISelLowering.cpp
+0-9llvm/lib/Target/ARM/ARMTargetMachine.h
+1-2llvm/lib/Target/ARM/ARMFastISel.cpp
+149-291 files not shown
+150-317 files

LLVM/project fac6cddllvm/lib/Target/ARM ARMISelLowering.cpp ARMConstantPoolValue.cpp, llvm/test/CodeGen/ARM subtarget-features-long-calls.ll

[ARM] support -mlong-calls -fPIC on arm32 (#147313)

support -mlong-calls -fPIC on arm32
try fixing issuse https://github.com/llvm/llvm-project/issues/39970 and
maybe helpful for soving the problem encourted in
https://github.com/llvm/llvm-project/pull/142982
DeltaFile
+235-27llvm/test/CodeGen/ARM/subtarget-features-long-calls.ll
+43-5llvm/lib/Target/ARM/ARMISelLowering.cpp
+5-4llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
+4-2llvm/lib/Target/ARM/ARMConstantPoolValue.h
+287-384 files

LLVM/project 55f9031llvm/lib/Target/AMDGPU SISchedule.td GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU wmma-hazards-gfx1250-w32.mir wmma-coexecution-valu-hazards.mir

[AMDGPU] Fix gfx1250 WMMA latencies

- 16x16x64 FP8/BF8 WMMA run in 4 cycles, not 8. Add a 4-cycle
  WriteXDL1PassWMMA write and split the FP8/BF8 InstRW by shape so that
  16x16x128 FP8/BF8 (and F16/BF16) keep the 8-cycle latency.
- f8f6f4 WMMA run in 4 cycles when both matrix inputs are f4 and 8 cycles
  when any input is f6 or f8, instead of the previous 8/16. Update the
  scheduling predicate accordingly.

The co-execution hazard category is derived from the WMMA latency. The
4-cycle WMMAs have a single co-execution slot, so give them their own
category (2 wait states before a dependent WMMA, 1 before a dependent VALU)
rather than bucketing them with the 8-cycle WMMAs.
DeltaFile
+0-117llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
+0-67llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
+66-0llvm/test/tools/llvm-mca/AMDGPU/gfx1250-wmma-cycles.s
+17-10llvm/lib/Target/AMDGPU/SISchedule.td
+14-8llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+0-4llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
+97-2066 files

LLVM/project 0ee40c5llvm/test/Analysis/CostModel/AArch64 sve-intrinsics.ll, llvm/test/CodeGen/AArch64 sve-fixed-length-masked-64-128bit-loads.ll sve-fixed-length-masked-64-128bit-stores.ll

[AArch64][SVE] Prefer SVE over scalarization for masked load/store of bf16 vectors (#210986)

During lowering of masked load/store for bf16 fixed-length vectors,
prefer emitting SVE instructions instead of scalarized branching code
whenever "+sve" is enabled in "target-features", regardless of whether
"+bf16" is present. The resulting changes can be seen in the following
test cases.
- llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
- llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-stores.ll

The direct cause of generating scalarized branching code is that the
"scalarize-masked-mem-intrin" optimization uses isLegalMaskedLoadStore
to determine whether the target natively supports masked load/store
operations. In AArch64TTIImpl::isLegalMaskedLoadStore,
isElementTypeLegalForScalableVector only treats bf16 vector operations
as legalizable when "+bf16" is enabled in "target-features". This
introduces an unnecessary restriction.

Therefore, this patch removes this restriction from

    [3 lines not shown]
DeltaFile
+217-0llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always-bf16.ll
+10-86llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
+9-83llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-stores.ll
+68-0llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
+4-5llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
+4-5llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
+312-1791 files not shown
+314-1837 files

LLVM/project c45be99llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize select-cmp-blend-chain.ll debugloc.ll

[LV] Simplify Blend/Select chain for tail folding outer loop reductions (#209659)

Predicated tail-folding outer loop reductions will generate a `Blend`
recipe for the predicate in-loop op and a `select` for tail-folding.

E.g.
```llvm
%blend = select %pred.mask, %inloop.op, %red.phi
%sel   = select %header.mask, %blend, %red.phi
```

This patch simplifies this Blend/Select chain to
```llvm
%logical.and = select %header.mask, %pred.mask, false
%sel         = select %logical.and, %inloop.op, %red.phi
```

This enables further optimization opportunities from CSE and further
simplification since the `%header.mask` will become an all-true-mask in

    [3 lines not shown]
DeltaFile
+82-4llvm/test/Transforms/LoopVectorize/select-cmp-blend-chain.ll
+46-0llvm/test/Transforms/LoopVectorize/debugloc.ll
+16-16llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
+6-12llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
+7-7llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
+14-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+171-396 files not shown
+184-5712 files

LLVM/project 99992e5flang/lib/Lower OpenACC.cpp, flang/test/Lower/OpenACC acc-reduction-remapping.f90

[flang][acc] fix array-section reductions on boxed arrays (#211648)

Reduction lowering (genReductions in flang/lib/Lower/OpenACC.cpp) only
remapped the reduced symbol to the acc.reduction result when the object
was a whole array (`isWholeSymbol` guard). For sections, the remap was
skipped, so hlfir.designate for element accesses inside the compute
region kept resolving through the original host declare's box instead of
the private reduction copy — the reduction ran on a private buffer that
never got read back.

Checked and confirmed dropping the boolean is safe for: non-1-starting
sections (recipe already compensates via a deliberate base-pointer
shift), SIZE/UBOUND/LBOUND inside privatized sections (intended
semantics), OPTIONAL dummies (pre-existing TODO, now fails loudly
instead of silently), combined constructs.
DeltaFile
+87-0flang/test/Lower/OpenACC/acc-reduction-remapping.f90
+22-0flang/test/Lower/OpenACC/Todo/acc-reduction-component.f90
+7-10flang/lib/Lower/OpenACC.cpp
+116-103 files

LLVM/project 3a418e3clang/lib/Sema SemaOverload.cpp, clang/test/SemaCXX deleted-function-deduction-failure.cpp

[clang][sema] Call expressions are constructed for undeduced deleted functions (#208488)

The deleted function path of overload resolution always constructed a CallExpr node
for the called function even if the function could not be deduced.
This case is handled in other paths by DiagnoseUseOfDecl which does perform that
test. The delete path cannot use that path though, as DiagnoseUseOfDecl rejects
deleted functions, and the entire point of this code is to permit the continued
evaluation of code even if the resolved function was deleted.

To fix this we now manually check for a complete type before continuing to construct
a potentially bogus CallExpr.
DeltaFile
+49-0clang/test/SemaCXX/deleted-function-deduction-failure.cpp
+4-0clang/lib/Sema/SemaOverload.cpp
+53-02 files

LLVM/project 31f6ba3llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp

Fix error reported by -Wrange-loop-construct (#211657)

One system I'm building on adds -Wrange-loop-construct to the list of
-W<group> options. This results in the compile error:

```
/home/perry/llvm/Woz/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp:37:19: error: loop variable '[ID, N]' creates a copy from type 'std::pair<unsigned int, llvm::MDNode *> const' [-Werror,-Wrange-loop-construct]
  for (const auto [ID, N] : MD) {
                  ^
/home/perry/llvm/Woz/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp:37:8: note: use reference type 'std::pair<unsigned int, llvm::MDNode *> const &' to prevent copying
  for (const auto [ID, N] : MD) {
       ^~~~~~~~~~~~~~~~~~~~
                  &
1 error generated.
```
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+1-11 files

LLVM/project 725737bllvm/lib/IR AutoUpgrade.cpp, llvm/test/Assembler auto_upgrade_coro_end_result.ll

[LLVM] Auto-upgrade legacy coro.end results (#211081)

When `llvm.coro.end` and `llvm.coro.end.async` changed from returning
`i1`
to returning `void` in #159278, the bitcode auto-upgrader continued to
handle
only the older two-argument `llvm.coro.end` form.

As a result, valid bitcode produced before that transition fails
verification
when a current LLVM ThinLTO backend materializes a module containing
either:

* the three-argument, `i1`-returning `llvm.coro.end`; or
* the `i1`-returning `llvm.coro.end.async`.

Teach `AutoUpgrade` to recognize both legacy declarations and rebuild
their
calls with the current `void`-returning intrinsics. If the legacy result

    [15 lines not shown]
DeltaFile
+49-0llvm/test/Assembler/auto_upgrade_coro_end_result.ll
+24-4llvm/lib/IR/AutoUpgrade.cpp
+73-42 files

LLVM/project 257e81fmlir/include/mlir/Dialect/Tosa/IR TosaTypesBase.td, mlir/test/Conversion/TosaToLinalg tosa-to-linalg-pipeline.mlir

Revert "[mlir][tosa] Combine unranked/ranked tensor types into single type" (#211701)

Reverts llvm/llvm-project#209737

Breaks bots, see
https://github.com/llvm/llvm-project/pull/209737#issuecomment-5064857765
DeltaFile
+68-40mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
+20-20mlir/test/Dialect/Tosa/invalid.mlir
+5-5mlir/test/Dialect/Tosa/verifier.mlir
+1-1mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
+94-664 files

LLVM/project 125113ellvm/test/CodeGen/AMDGPU soft-waitcnt-deletion.mir soft-waitcnt-loop-deletion.ll

Rebase

Change-Id: I5f8b91764af1964f6b4b68f07f08170546a5c83b
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/soft-waitcnt-deletion.mir
+2-2llvm/test/CodeGen/AMDGPU/soft-waitcnt-loop-deletion.ll
+9-92 files

LLVM/project 1538937mlir/include/mlir/Dialect/Tosa/IR TosaTypesBase.td, mlir/test/Conversion/TosaToLinalg tosa-to-linalg-pipeline.mlir

Revert "[mlir][tosa] Combine unranked/ranked tensor types into single type (#…"

This reverts commit aab7e0b08d30ddca5858069a4c14c1ea3da042e6.
DeltaFile
+68-40mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
+20-20mlir/test/Dialect/Tosa/invalid.mlir
+5-5mlir/test/Dialect/Tosa/verifier.mlir
+1-1mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-pipeline.mlir
+94-664 files

LLVM/project 5acf75dllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU expert_scheduling_gfx12.mir soft-waitcnt-deletion.mir

[AMDGPU] Check all incoming edges before deleting soft waits

Change-Id: I92ca9784405e53f46aa4c8701e417d32f00bbff7
DeltaFile
+724-1llvm/test/CodeGen/AMDGPU/expert_scheduling_gfx12.mir
+431-0llvm/test/CodeGen/AMDGPU/soft-waitcnt-deletion.mir
+128-38llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+118-0llvm/test/CodeGen/AMDGPU/soft-waitcnt-loop-deletion.ll
+46-0llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+36-0llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+1,483-3910 files not shown
+1,607-6116 files