[MLIR][LLVM] Share LLVM metadata attribute translation (#203016)
Share LLVM dialect metadata materialization through `ModuleTranslation`
so named metadata and metadata-as-value lowering use one conversion
path. Resolve metadata symbol references to functions, globals, aliases,
and ifuncs, and diagnose malformed required metadata before lowering.
Rename `MDFuncAttr` to `MDGlobalValueAttr` to reflect its support for
symbol-backed global values.
[MLIR][LLVM] Reject distinct generic metadata on import (#212455)
Reject distinct nodes when converting generic LLVM metadata into LLVM
dialect attributes because `MDNodeAttr` cannot preserve node identity.
Apply the policy recursively so top-level and nested nodes use the
existing unsupported-metadata failure path while finite acyclic uniqued
nodes remain importable.
[clang-tidy] Fix trailing semicolon and lost comment in readability-use-std-min-max (#208782)
Fix two bugs in readability-use-std-min-max when the if body has no
braces.
For brace-less if bodies, If->getEndLoc() points to the expression end
rather than the trailing semicolon, truncating replacements and losing
comments. We find the semicolon via findNextToken and extend the range
consistent with compound statement logic.
Before:
if (n < -1) n = -1 ; -> n = std::max(n, -1); ;
if (n > 1) n = 1/*comment*/; -> n = std::min(n, 1);;
After:
if (n < -1) n = -1 ; -> n = std::max(n, -1);
if (n > 1) n = 1/*comment*/; -> n = std::min(n, 1); /*comment*/
Fixes #208708.
AI Usage: This patch is AI-assisted, reviewed and verified by me.
[AMDGPU] Use SubtargetPredicates for the f32/f16 -> fp8/bf8 conversions (#213383)
The follow-up #212888 left for the other direction. HasCvtFP8SDWASrcSel
and HasCvtFP8ByteSel replace isGFX940Plus and isGFX11Plus on the f32 ->
fp8/bf8 conversions, which split by the same encoding characteristic, so
the two feature descriptions become direction-neutral. The f16 ->
fp8/bf8 conversions had no feature at all, so add
FeatureF16FP8ConversionInsts, the mirror of the existing
FeatureFP8F16ConversionInsts, and use it in place of isGFX1250Plus.
Assisted-By: Claude Opus 5
[libc++] Implement LWG4169: `std::atomic<T>`'s default constructor should be constrained (#131950)
Drive-by: Rename `constexpr_noexcept.compile.pass.cpp` to
`ctor.default.pass.cpp` as test coverage is added to it, and compile and
run it in all modes.
[MLIR][CMake] Extend MLIRIR PCH reuse to transitive dependants
llvm_update_pch() only offers a PCH to targets that name the defining
library as a *direct* dependency, because across LLVM subprojects a
transitively reused PCH drags in unrelated headers and causes name
collisions. Within MLIR that concern is much weaker: mlir/IR/pch.h holds
MLIR core headers that essentially every MLIR library includes anyway.
Add mlir_reuse_ir_pch(), which offers MLIRIR's PCH to any target that
actually reaches MLIRIR through its link graph. The reachability check
matters: a PCH containing MLIR IR headers emits out-of-line symbols that
only libMLIRIR provides, so handing it to a Support-only target such as
tblgen-lsp-server breaks the link.
The helper is called from add_mlir_library() and add_mlir_tool(), and
again from mlir_target_link_libraries(), where most tests, unittests and
libMLIR.so-avoiding libraries actually attach their MLIR dependencies. It
is idempotent and skips targets that define their own PCH, that opt out
with DISABLE_PCH_REUSE, that override RTTI/EH, or that contain C/ObjC
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[AMDGPU] Generalize MFMA VGPR->AGPR opcode mapping (NFC) (#213274)
Move the VGPR/AGPR pairing out of MFMATable into a generalized
AGPRFormTable class and rename getMFMASrcCVDstAGPROp to getAGPRFormOp.
MFMATable inherits AGPRFormTable, so the instantiation sites and the
generated table are unchanged.
Other instruction families with paired VGPR/AGPR pseudos, such as DS,
can now be tagged with AGPRFormTable.
Related to #168983
clang: Store vendor GPU kinds in OffloadArch instead of re-listing GPUs (#213362)
OffloadArch was a flat enum that hand-duplicated every AMDGPU and NVPTX
target, plus a few edge cases. This was yet another place that needed
updating every time a new target is added, which should now be avoided.
Replace with a tagged union-like scheme.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[MLIR][CMake] Add PCH for MLIRIR
Add a precompiled header for MLIRIR, following the infrastructure added in
llvm#176420 and the per-component PCHs for llvm/IR (llvm#183303),
llvm/CodeGen (llvm#183346) and clang/AST (llvm#183358).
The header list was selected with the same methodology: compile all 1173
CUs under mlir/lib with -ftime-trace, rank mlir headers by the time spent
parsing them (including transitively included headers), then greedily pick
the header with the largest marginal coverage until the marginal gain
falls off. Candidates were restricted to headers already reachable from
MLIRIR's own sources, so the PCH does not invert the library layering.
Over the mlir/lib CUs, the selected set covers 1227s of 3674s total
frontend time (33%). On a Release+assertions build of mlir-opt
(Apple M-series, -j16), clean build wall time goes from 468.3s to 440.8s
(-5.9%); 715 of 1536 MLIR objects reuse the PCH.
mlir/lib/CMakeLists.txt gains an explicit add_subdirectory(IR) before the
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[RISCV] Fix ISCVISAInfo::computeDefaultABI() result for xcheriot (#212129)
XCheriot was not considered in this function, so RV32E+XCheriot
defaulted
to ilp32e instead of cheriot when no -target-abi was given.
Since this function does not have unit test coverage, this adds new
tests
for the ABI inference functions: RISCVISAInfo::computeDefaultABI() and
RISCVABI::computeTargetABI.
This change was created with the help of AI tools
[X86AsmBackend] Define reset() hook (#213409)
Noticed when reviewing #175830: MCObjectStreamer::reset frees the
fragments PendingBA and PrevInstPosition point into, but X86AsmBackend
keeps them. Define the hook.
