[libc++] Build the library with C++26 (#181021)
All supported compilers support C++26. This allows simplifying some of
the upcoming <text_encoding> implementation.
[NFC][analyzer] Improve computeObjectUnderConstruction (#186186)
Previously the method `ExprEngine::computeObjectUnderConstruction` took
a `NodeBuilderContext` parameter which was only used to call its
`blockCount()` method; this commit replaces this with directly taking
`NumVisitedCaller` (= number of times the caller was visited, the
`blockCount`) as an unsigned value.
In `CallEvent::getReturnValueUnderConstruction` this method is invoked
with `getNumVisitedCurrent()`, the visitation count of the _current_
`LocationContext` and `Block`; instead of calling `getNumVisited()` on
the `LocationContext` and `Block` corresponding to the `CallEvent`
instance (available through its data members). This is logically
incorrect, but (at least within the lit testsuite) there is no situation
where it leads to actually incorrect behavior. This is currently marked
with a FIXME comment; it will be fixed in a follow-up commit.
[Flang][OpenMP] Add semantic support for OpenMP Loop Interchange and permutation clause in Flang (#183435)
This patch adds semantics for the `omp interchange` directive in flang
and the permutation clause, as specified in OpenMP 6.0.
Relevant tests have been added in every step.
[SPIR-V] Handle undef aggregate initializers for global variables (#186785)
Expand undef aggregate global initializers into per-element spv_undef
intrinsics
[mlir][tosa] Remove 'Pure' trait from operations that are not speculatable (#185700)
This commit removes the 'Pure' trait from a number of TOSA operations.
Instead of marking most ops as pure by default, the trait is now opt-in
for operations that are provably side-effect free and speculatable.
Several operations were previously marked as pure unintentionally.
The following operations have had 'Pure' removed (reason in brackets):
- ARGMAX (out-of-range index)
- AVG_POOL2D (accumulator overflow/underflow)
- AVG_POOL2D_ADAPTIVE (same as above)
- CONV2D (accumulator overflow/underflow)
- CONV2D_BLOCK_SCALED (accumulator overflow/underflow)
- CONV3D (accumulator overflow/underflow)
- DEPTHWISE_CONV2D (accumulator overflow/underflow)
- MATMUL (accumulator overflow/underflow)
- MATMUL_T_BLOCK_SCALED (accumulator overflow/underflow)
- TRANSPOSE_CONV2D (accumulator overflow/underflow)
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[X86] Improve handling of i512 SHL(-1,Amt) + SRL(-1,Amt) "mask shifts" (#186806)
An extension of the existing one-bit shift patterns - perform an initial
select to handle 'allones/allzeros' elements and then insert the element
that has a partial mask on top of it.
Often turns up in bit manipulation patterns
[X86][APX] Enable NDD tunings (#186049)
For latest Intel processors with APX, mem form of all NDD instructions
(except for RIP based addressing) and imm form of NDD add/sub (include
inc/dec) instructions needed to be turned off by default for optimal
hardware performance.
Two new tunings enable-ndd-mem and enable-ndd-imm was added then
disabled by default. The new isa attributes is adopted for different
alternatives for NDD related patterns to control the generation of
mem/imm form.
[mlir][vector] Add missing tests (nfc) (#186990)
Currently, `ConvertVectorToLLVM` rejects strided memrefs when lowering
`vector.gather` and `vector.scatter`. This PR adds tests to document
that behavior.
Supporting strided memrefs in the lowering is left as future work.
However, it is still unclear whether gather/scatter on strided memrefs
should be supported at all (see the Discourse discussion [1]).
This PR also adds tests for `vector.load` and `vector.store` in
`invalid.mlir` to document that these ops do not support strided
memrefs.
[1] https://discourse.llvm.org/t/rfc-semantics-of-vector-gather-indices-with-strided-memrefs
[AArch64][llvm] Redefine some isns as an alias of `SYS`
Some instructions are not currently defined as an alias of `SYS`
when they should be, so they don't disassemble back into the
native instruction, but instead disassemble into `SYS`.
Fix these cases and add additional testcase.
Note that I've left `GCSPUSHM` due to a `mayStore`, `GCSSS1` and
`GCSSS2` as they're used in AArch64ISelDAGToDAG.cpp, and `GCSPOPM`
has an intrinsic pattern in AArch64InstrInfo.td. They will disassemble
correctly though, as they use `InstAlias`.
[mlir][bufferization] Fix crash with copy-before-write + bufferize-function-boundaries (#186446)
When `copy-before-write=1` is combined with
`bufferize-function-boundaries=1`, `bufferizeOp` creates a plain
`AnalysisState` (not `OneShotAnalysisState`) and passes it to
`insertTensorCopies`. Walking `CallOp`s during conflict resolution
called `getCalledFunction(callOp, state)`, which unconditionally cast
the `AnalysisState` to `OneShotAnalysisState` via `static_cast`, causing
UB and a stack overflow crash.
Fix by guarding the cast with `isa<OneShotAnalysisState>()` so that when
the state is a plain `AnalysisState`, the function falls through to
building a fresh `SymbolTableCollection` — the same safe fallback
already present.
Fixes https://github.com/llvm/llvm-project/issues/163052
Assisted-by: Claude Code
[NFC][NVPTX] Fix tcgen05.mma PTX instruction encoding (#186602)
.ashift should be before .collector::a::* according to PTX ISA.
ptxas accepts both orderings, but the spec-correct order is used now.
[mlir] Fix crash in diagnostic verifier for unmatched @unknown expectations (#186148)
When an expected-* directive uses the @unknown location specifier, the
associated ExpectedDiag record has an invalid (null) SMLoc as its
fileLoc. If the expected diagnostic is never produced, emitError() is
called to report the unmatched expectation, but it unconditionally
constructs an SMRange from fileLoc, triggering a null-pointer
dereference (UBSan) and an assertion failure in SMRange's constructor
which requires both endpoints to have equal validity.
Fix by guarding the SMRange construction with a fileLoc.isValid() check.
When fileLoc is invalid, call PrintMessage without a source range.
Fixes #163343
Assisted-by: Claude Code
Merge branch 'arm-fp-flt' into arm-fp-faddsub
The merged changes on main include a fix for the previous denormal
handling bug in the old Thumb1 addsf3. So one of my reasons to replace
it completely is gone. Therefore I'm reinstating it, and putting the
new one alongside it as a different time/space tradeoff.
[WebAssembly] combine `bitmask` with `setcc <X>, 0, setlt` (#179065)
The rust `simd_bitmask` intrinsic is UB when the lanes of its input are
not either `0` or `!0`, presumably so that the implementation can be
more efficient because it could look at any bit. To get the "mask of
MSB" behavior of webassembly's `bitmask`, we would like to simply first
compare with a zero vector.
```llvm
define i32 @example(<2 x i64> noundef %v) {
entry:
%1 = icmp slt <16 x i8> %v, zeroinitializer
%2 = bitcast <16 x i1> %1 to i16
%3 = zext i16 %2 to i32
ret i32 %3
}
```
On x86_64, this additional comparison optimizes away, but for wasm it
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Stop trying to crt_supersede one Arm .S file with another
Turns out that doesn't work: both versions of the assembly language
comparison were included in the output library, and the linker would
make an arbitrary choice of which to pull in to the link. Instead,
just put the old files on to the SOURCES list in an else clause.
