LLVM/project 2184774clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/test/CIR/CodeGen call-conv-lowering-x86_64-abi-compat.c call-conv-lowering-x86_64.c

[CIR] Accept fixed-width vectors in x86_64 callconv lowering (#215118)

The CallConvLowering bridge rejects a vector in a parameter or return
position, so a function taking one fails the pass. It also never reads
the AVX level, which is what decides whether a vector wider than 128
bits reaches a register.

A vector is accepted now where the classifier and clang size it the same
way, which means a whole-byte element and a power-of-two width. Scalable
vectors and the other widths stay rejected. The module's AVX level comes
from the target ABI name, as `CodeGenModule` does. A classifier per
level lets a target attribute raise it for one function. An ABI older
than the rule pins every function back to the module's level. A direct
call takes its callee's level, and an indirect call the level of the
function containing it.

CIRGen records target features on a definition but not on a declaration,
so a declaration carrying the attribute is classified at the module's
level until [#214986](https://github.com/llvm/llvm-project/pull/214986)

    [4 lines not shown]
DeltaFile
+165-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-avx.c
+129-33clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+77-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64.c
+69-6clang/test/CIR/Transforms/abi-lowering/x86_64-vector.cir
+43-28clang/test/CIR/Transforms/abi-lowering/x86_64-variadic-call.cir
+56-6clang/test/CIR/CodeGen/call-conv-lowering-x86_64-abi-compat.c
+539-734 files not shown
+613-8510 files

LLVM/project 3de6fefmlir/include/mlir/Dialect/SCF/Utils Utils.h, mlir/lib/Dialect/SCF/Utils Utils.cpp

[mlir] Add shouldPromoteIfSingleIteration option to loopUnrollByFactor (#215080)

Add a shouldPromoteIfSingleIteration parameter to loopUnrollByFactor to
control whether single-iteration loops are promoted during unrolling.
When set to false, the function skips calls to promoteIfSingleIteration
on the main loop, epilogue loop, and the unroll-factor-1 early-exit
path.

The parameter defaults to true to preserve existing behavior.
DeltaFile
+40-0mlir/test/Dialect/SCF/loop-unroll.mlir
+9-5mlir/lib/Dialect/SCF/Utils/Utils.cpp
+9-2mlir/test/lib/Dialect/SCF/TestLoopUnrolling.cpp
+4-1mlir/include/mlir/Dialect/SCF/Utils/Utils.h
+62-84 files

LLVM/project e3b0d11llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h SPIRVNonSemanticDebugHandler.cpp

[reviews] Remove helper.
DeltaFile
+3-5llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+0-2llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+3-72 files

LLVM/project 0a9d67bllvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h SPIRVNonSemanticDebugHandler.cpp

[reviews] Remove state variable.
DeltaFile
+1-4llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+0-2llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+1-62 files

LLVM/project 3b7142clldb/test/API/tools/lldb-dap/launch TestDAP_launch_stdio_redirection_and_console.py, lldb/test/API/tools/lldb-dap/launch/io TestDAP_launch_io_integratedTerminal.py

[lldb-dap][NFC] Use wildcard imports for test decorators (#216235)

Replace explicit imports `from ... import (a, b, c)` with wildcard
imports `from ... import *` for `lldbsuite.test.decorators`,

This lets downstream forks introduce extra decorators (e.g. to skip
tests on private configurations) without needing to patch each test's
import list.

[Related
discourse](https://discourse.llvm.org/t/do-we-want-to-tighten-up-imports-in-the-api-testcases/91557/3)
DeltaFile
+2-8lldb/test/API/tools/lldb-dap/module/TestDAP_module.py
+1-8lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py
+1-7lldb/test/API/tools/lldb-dap/stopped-events/TestDAP_stopped_events.py
+1-7lldb/test/API/tools/lldb-dap/restart/TestDAP_restart_console.py
+1-7lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_integratedTerminal.py
+2-6lldb/test/API/tools/lldb-dap/stackTrace/TestDAP_stackTrace.py
+8-4357 files not shown
+70-14763 files

LLVM/project cbf19fdllvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Transforms/LoopVectorize/AArch64 partial-reduce-add-sdot-i16-i32.ll vector-reverse.ll

[AArch64][CostModel] Adjust the cost of pure partial add reductions. (#214723)

These reductions can lower to a [SU]ADALP rather than a widening add
pair, so using partial reductions becomes profitable for two-way
widening reduction loops such as (https://godbolt.org/z/v8vr9Pzqb):
```c
long sadalp(const int *a, long n) {
  long s = 0;
  for (long i = 0; i < n; i++)
    s += (long)a[i];
  return s;
}
```
DeltaFile
+18-18llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
+14-4llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-costs.ll
+9-7llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-usabs.ll
+4-4llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
+3-2llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+2-2llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-add-sdot-i16-i32.ll
+50-371 files not shown
+51-387 files

LLVM/project 8d95903clang/test/Analysis lifetime-bound.cpp

Correct CHECK-NEXT lines.
DeltaFile
+4-4clang/test/Analysis/lifetime-bound.cpp
+4-41 files

LLVM/project 6b04339clang/docs ReleaseNotes.md, clang/lib/Sema SemaDeclCXX.cpp

[Clang][Sema] Fix an ICE where structured binding packs within a lambda were not added to the CapturingScopeInfo (#214716)

Fixed a bug where structured binding packs within a lambda were not
added to the `CapturingScopeInfo` during `ActOnDecompositionDeclarator`,
which also led to invalid expressions being considered for delayed
lambda diagnostics, when they should have been diagnosed immediately.

Fixes #214160

Signed-off-by: Baba Dan Constantin <babadany2999 at gmail.com>
DeltaFile
+42-0clang/test/SemaCXX/cxx2c-binding-pack.cpp
+5-0clang/lib/Sema/SemaDeclCXX.cpp
+1-0clang/docs/ReleaseNotes.md
+48-03 files

LLVM/project e6be2fdclang/lib/CodeGen BackendUtil.cpp, llvm/include/llvm/Analysis RuntimeLibcallInfo.h

CodeGen: Remove TargetOptions::FloatABIType

This is now fully replaced with the "float-abi" module flag.
If the module flag is not present, the default is computed
from the triple. Consumers are updated to read the module flag.

RuntimeLibraryAnalysis now defers analysis until run() on a Module,
instead of during the pass constructor as before. This requires copying
all of the remaining relevant TargetOptions so they are available
when the module is seen.

Unfortunately, ARM still depends on TargetOptions for determining
the float-abi. -target-abi=aapcs16 still changes the default float-abi,
but an explicit module flag wins.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+45-0llvm/test/LTO/ARM/float-abi-module-flag.ll
+19-17llvm/include/llvm/Analysis/RuntimeLibcallInfo.h
+15-20llvm/lib/Target/ARM/ARMTargetMachine.cpp
+28-0llvm/test/Transforms/Util/DeclareRuntimeLibcalls/float-abi-module-flag.ll
+5-18llvm/lib/Analysis/RuntimeLibcallInfo.cpp
+3-14clang/lib/CodeGen/BackendUtil.cpp
+115-6923 files not shown
+174-12629 files

LLVM/project 9c7fa49llvm/lib/CodeGen CommandFlags.cpp, llvm/test/CodeGen/ARM float-abi-synthesize-flag.ll

CodeGen: Synthesize "float-abi" module flag from -float-abi

Avoid annoying test updates when the corresponding TargetOptions
field is removed. Make the -float-abi llc/opt option a lit test
convenience that records the floating-point ABI in the IR,
mirroring how -mcpu/-mattr are recorded as function attributes.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+32-0llvm/test/CodeGen/ARM/float-abi-synthesize-flag.ll
+11-1llvm/lib/CodeGen/CommandFlags.cpp
+43-12 files

LLVM/project 0a6f574llvm/lib/CodeGen CommandFlags.cpp, llvm/test/CodeGen/ARM float-abi-module-flag.ll float-abi-synthesize-flag.ll

Error on -float-abi conflicting with the "float-abi" module flag
DeltaFile
+17-5llvm/lib/CodeGen/CommandFlags.cpp
+5-3llvm/test/CodeGen/ARM/float-abi-module-flag.ll
+6-2llvm/test/CodeGen/ARM/float-abi-synthesize-flag.ll
+3-2llvm/test/CodeGen/CSKY/float-abi-module-flag.ll
+31-124 files

LLVM/project 6d7e249llvm/lib/CodeGen CommandFlags.cpp

Remove opt description change
DeltaFile
+1-3llvm/lib/CodeGen/CommandFlags.cpp
+1-31 files

LLVM/project 52c14ccllvm/include/llvm/ExecutionEngine/Orc LLJIT.h, llvm/lib/ExecutionEngine/Orc LLJIT.cpp

lli: Record the host triple on triple-less modules (#216132)

The JIT compiles for the host, but modules without a target triple kept
an empty triple, which module-triple-based analyses (e.g. runtime
libcall selection) cannot resolve. Set the resolved JIT triple on the
module. This defends against jit test regressions when
RuntimeLibraryInfo
starts getting computed from the module instead of TargetOptions.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+6-3llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
+6-1llvm/tools/lli/lli.cpp
+1-1llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
+13-53 files

LLVM/project ff5e780llvm/lib/Target/AMDGPU GCNSubtarget.h SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU fdot2.ll

[AMDGPU] Fix performFMACombine FDOT2 fold for subnormal handling (#205101)

The fold from v_fma_mix_f32 pairs to v_dot2_f32_f16/v_dot2c_f32_f16
was gated only on fp-contract flags, ignoring how each instruction
handles f16 subnormal inputs under different denormal modes.

Hardware testing across multiple GPU generations shows that gfx90a
(CDNA2) is the sole outlier: v_dot2c unconditionally flushes f16
subnormal inputs to zero in all MODE configurations, while v_fma_mix_f32
preserves them when ieee=1 (the default compute kernel mode). All other
tested GPUs with dot2 instruction do not flush f16 subnormal inputs.
Add GCNSubtarget::dot2UnconditionalFlush() to capture this hardware
quirk.

Gate the fold on the function's f32 denormal mode:
- dot2UnconditionalFlush(): allow fold only when f32 denorm =
  PreserveSign, so both instructions flush f16 subnormals.
- All other GPUs: allow fold only when f32 denorm = IEEE, so both
  instructions preserve f16 subnormals. Dynamic mode is also rejected

    [9 lines not shown]
DeltaFile
+89-6llvm/test/CodeGen/AMDGPU/fdot2.ll
+32-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+127-93 files

LLVM/project 74b6413llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-allocate.ll as-vgpr-across-call.ll

Do not add a second lifetime start when allocating VGPRs again
DeltaFile
+21-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+17-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+0-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+38-43 files

LLVM/project 8c52b03llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-asm-clobber.ll

Diagnose inline asm that clobbers a VGPR-memory object's registers
DeltaFile
+93-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-asm-clobber.ll
+31-5llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+124-52 files

LLVM/project f5f16ecllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-across-call.ll as-vgpr-private-object-vgprs.mir

Allocate and reserve registers for address space 13 objects
DeltaFile
+340-0llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+178-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-object-regalloc.ll
+140-12llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+133-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+106-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-private-object-vgprs.mir
+80-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+977-1218 files not shown
+1,280-2324 files

LLVM/project 42a986f.github/workflows libcxx-pr-conformance-tests.yaml, libcxx/include/__functional weak_result_type.h

[libc++] Upgrade to GCC 16 (#206235)

This also removes a few `// UNSUPPORTED: gcc` which are unnecessary as a
drive-by.
DeltaFile
+8-3libcxx/include/__functional/weak_result_type.h
+0-9libcxx/test/std/utilities/utility/pairs/pairs.pair/assign_pair.pass.cpp
+4-4.github/workflows/libcxx-pr-conformance-tests.yaml
+0-6libcxx/src/experimental/time_zone.cpp
+2-3libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/is_implicit_lifetime.pass.cpp
+2-3libcxx/include/__ranges/concat_view.h
+16-2820 files not shown
+44-4726 files

LLVM/project 1b3b7e5llvm/lib/Target/X86 X86PartialReduction.cpp, llvm/test/CodeGen/X86 byte-sum.ll

[X86][PartialReduction] Lower zext-byte add reductions to vpsadbw (#201076)

Loops of the form `for (i) sum += bytes[i];` (`uint8_t` input, `i32`/`i64` accumulator)
lower to `vpmovzxbd` + `vpaddd` today, although `PSADBW(x, 0)`
computes the same sum in one instruction per 128/256/512-bit lane.

Teach `X86PartialReduction` to rewrite the `zext <N x i8> to <N x i32|i64>`
leaves of an add reduction (N >= 16) into `PSADBW(x, 0)`, split across
SSE2/AVX2/AVX-512BW lanes per the subtarget. `i64` accumulators consume
`PSADBW`'s natural `<N/8 x i64>` output directly.

Tests: `x86-partial-reduction-byte-sum*.ll` (matcher in isolation),
`byte-sum-{positive,negative}.ll` (full CodeGen on +sse2/+avx2/+avx512bw).
DeltaFile
+1,278-0llvm/test/CodeGen/X86/byte-sum.ll
+679-0llvm/test/Transforms/PhaseOrdering/X86/x86-partial-reduction-byte-sum.ll
+115-1llvm/lib/Target/X86/X86PartialReduction.cpp
+43-0llvm/test/Transforms/PhaseOrdering/X86/x86-partial-reduction-byte-sum-debugloc.ll
+2,115-14 files

LLVM/project 7c517dallvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-unsupported.ll

Reject under-aligned whole-dword VGPR-memory accesses
DeltaFile
+34-8llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-unsupported.ll
+14-7llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+14-6llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+62-213 files

LLVM/project 1e6b055llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp

[reviews] Relax handling of untracked locations.
DeltaFile
+12-7llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+12-71 files

LLVM/project e4a3922llvm/include/llvm/Analysis VectorUtils.h, llvm/lib/Transforms/Vectorize LoopVectorizationLegality.cpp

Fixups
DeltaFile
+1-2llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+1-1llvm/include/llvm/Analysis/VectorUtils.h
+2-32 files

LLVM/project 77673e2llvm/lib/Frontend/OpenMP OMPDescriptors.inc

Apply property-related errata for 6.0 spec
DeltaFile
+4-4llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
+4-41 files

LLVM/project 79a0078llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h SPIRVNonSemanticDebugHandler.cpp

[reviews] Use SetVector.
DeltaFile
+6-10llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+2-1llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+8-112 files

LLVM/project 17930a3lldb/source/Plugins/Process/Linux NativeRegisterContextLinux_arm64.h NativeRegisterContextLinux_arm64.cpp

[lldb][AArch64][Linux] Add function to get register buffers (#213977)

Replaces Get<set>Buffer methods.
DeltaFile
+115-63lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+2-22lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+117-852 files

LLVM/project 42b0f56llvm/lib/Target/AArch64 AArch64SVEInstrInfo.td, llvm/test/CodeGen/AArch64 vector-absolute-difference.ll

[LLVM][CodeGen][SVE] Prefer uadalp over sabalb/sabalt. (#216301)

Partially reverts https://github.com/llvm/llvm-project/pull/212800
becuase for SVE2 using uadalp has better accumulator throughput than a
sabalb/sabalt sequence.
DeltaFile
+24-12llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
+0-14llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+24-262 files

LLVM/project 0132faclldb/test/API/tools/lldb-dap/attach TestDAP_attachByPortNum.py

[lldb-dap] Spawn debug sever in the build directory. (#216078)

The debugserver may create files such as the socket in the working
directory.
DeltaFile
+4-1lldb/test/API/tools/lldb-dap/attach/TestDAP_attachByPortNum.py
+4-11 files

LLVM/project f5418f3llvm/lib/Target/X86 X86InstrInfo.cpp, llvm/test/CodeGen/X86/apx memfold-remat-physreg.ll

[X86][APX] Add missing VRM argument (#216240)

It happens when a rematerialized load is from global variable, see
https://godbolt.org/z/ddsh8PP4K

Assisted-by: Claude Opus 4.8
DeltaFile
+74-0llvm/test/CodeGen/X86/apx/memfold-remat-physreg.ll
+1-1llvm/lib/Target/X86/X86InstrInfo.cpp
+75-12 files

LLVM/project 3faf820clang/include/clang/CIR/Dialect/IR CIRDialect.h CIRAttrs.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Drop `cir.offload.container` and represent offload modules through a unit market on MLIR modules.
DeltaFile
+106-60clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+52-26clang/test/CIR/IR/invalid-offload-container.cir
+0-59clang/include/clang/CIR/Dialect/IR/CIROps.td
+42-0clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+17-21clang/test/CIR/IR/offload-container.cir
+12-0clang/include/clang/CIR/Dialect/IR/CIRDialect.h
+229-1661 files not shown
+232-1667 files

LLVM/project 207f72dlldb/packages/Python/lldbsuite/test decorators.py

[lldb] introduce the requireMacOS decorator (#216135)

This is not used in llvm.org yet, but will be used in swiftlang with
https://github.com/swiftlang/llvm-project/pull/13750.
DeltaFile
+7-0lldb/packages/Python/lldbsuite/test/decorators.py
+7-01 files