LLVM/project 8d06a65clang/lib/Sema SemaDeclCXX.cpp SemaExprCXX.cpp

Sigh formatting is the bane of my existence
DeltaFile
+4-7clang/lib/Sema/SemaDeclCXX.cpp
+2-2clang/lib/Sema/SemaExprCXX.cpp
+6-92 files

LLVM/project 78f193bllvm/lib/Transforms/Utils AssumeBundleBuilder.cpp, llvm/test/Transforms/InstCombine assume.ll

[AssumeBuilder] Fix incorrect nonnull optimization (#195676)

We can only optimize nonnull assumes to refer to the base of a GEP if
the GEP is inbounds.

From #195650.
DeltaFile
+24-1llvm/test/Transforms/InstCombine/assume.ll
+1-1llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp
+25-22 files

LLVM/project 45a4a26clang/lib/Sema SemaExprCXX.cpp SemaDeclCXX.cpp

Clean up some of the logic
DeltaFile
+15-14clang/lib/Sema/SemaExprCXX.cpp
+15-7clang/lib/Sema/SemaDeclCXX.cpp
+30-212 files

LLVM/project c91f835libcxx/docs/Status Cxx2cIssues.csv, libcxx/include/__mdspan extents.h mdspan.h

[libc++][mdspan] Fix `mdspan::operator[]` bounds checking and implement LWG4020 (#192269)

This example fails to compile with libc++ in hardened mode without this
fix.
```c++
#include <mdspan>

struct RValueInt {
  constexpr operator int() && noexcept { return 0; }
};

int main() {
  int data[1] = {42};
  std::mdspan m(data, std::extents<int, 1>{1});

  m[RValueInt{}];
}
```

Fixes: #171311
DeltaFile
+12-0libcxx/include/__mdspan/extents.h
+5-5libcxx/include/__mdspan/mdspan.h
+9-0libcxx/test/std/containers/views/mdspan/mdspan/index_operator.pass.cpp
+4-0libcxx/test/libcxx/containers/views/mdspan/mdspan/assert.index_operator.pass.cpp
+1-1libcxx/docs/Status/Cxx2cIssues.csv
+31-65 files

LLVM/project df7bd95llvm/lib/Transforms/Vectorize LoopVectorize.cpp LoopVectorizationPlanner.cpp

[LV] Use isLegalMaskedLoadOrStore for interleaved accesses too (NFC)

isLegalMaskedLoadOrStore is now the central place for querying target
capabilities for masked accesses. Access pattern legality checks are
hoisted outside of it.
DeltaFile
+4-6llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+0-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+4-102 files

LLVM/project 531b8acclang/include/clang/AST OpenACCClause.h Expr.h

[clang][AST][NFC] const-correctness improvements for member functions returing `ArrayRef` (#195784)

- Add const qualifiers to member functions.
- Drop non-const-qualified member functions whose const-qualified
versions return same thing.
DeltaFile
+0-27clang/include/clang/AST/OpenACCClause.h
+6-4clang/include/clang/AST/Expr.h
+0-4clang/include/clang/AST/ExprCXX.h
+0-3clang/include/clang/AST/StmtOpenACC.h
+6-384 files

LLVM/project f634c2bllvm/lib/Transforms/Vectorize LoopVectorizationPlanner.cpp LoopVectorize.cpp

[LV] Introduce isLegalMaskedLoadOrStore (NFC) (#195242)

This simplifies legality checks, and eventually will become the single
point querying TTI hooks for masked ld/st. Currently, legality checks
for interleaved accesses still query TTI directly.
DeltaFile
+13-13llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+2-12llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-9llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+18-343 files

LLVM/project 597111ellvm/test/CodeGen/AArch64 fsh.ll rem-by-const.ll

[AArch64][GlobalISel] Match G_DUP with undef elements (#195237)

This helps us match more vector splats that contain undef elements,
matching build vectors that contain undef so long as they contain at
least 2 duplicate entries.
DeltaFile
+305-532llvm/test/CodeGen/AArch64/fsh.ll
+172-416llvm/test/CodeGen/AArch64/rem-by-const.ll
+82-154llvm/test/CodeGen/AArch64/fcmp.ll
+8-58llvm/test/CodeGen/AArch64/fcvt_combine.ll
+15-47llvm/test/CodeGen/AArch64/arm64-vhadd.ll
+13-32llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+595-1,23914 files not shown
+695-1,38420 files

LLVM/project 28360f7clang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp, clang/test/CIR/CodeGenCUDA device-stub.cu

[CIR][CUDA] Fix typed StringAttr on globals and Add CIR-to-LLVM lowering checks for existing registration support (#195002)
DeltaFile
+25-2clang/test/CIR/CodeGenCUDA/device-stub.cu
+3-3clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+28-52 files

LLVM/project b29636fllvm/test/CodeGen/AArch64 addp-shuffle.ll

[AArch64][GlobalISel] Add gisel test coverage for addp-shuffles.ll. NFC (#195803)
DeltaFile
+445-112llvm/test/CodeGen/AArch64/addp-shuffle.ll
+445-1121 files

LLVM/project 32c6548mlir/include/mlir/IR AffineExprVisitor.h, mlir/lib/Dialect/XeGPU/IR XeGPUDialect.cpp

[mlir][NFC] Fix typo (flattend => flattened) (#195780)
DeltaFile
+4-4mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+4-4mlir/include/mlir/IR/AffineExprVisitor.h
+1-1mlir/lib/IR/BuiltinAttributeInterfaces.cpp
+9-93 files

LLVM/project 81b9c27libcxx/test/libcxx/strings/basic.string asan_vector_integration.pass.cpp asan_deque_integration.pass.cpp, llvm/test/CodeGen/X86/apx memfold-no-physreg.ll

Merge branch 'main' into users/vitalybuka/spr/lit-use-dbg-instead-of-note-for-tool-detection
DeltaFile
+270-0llvm/test/CodeGen/X86/apx/memfold-no-physreg.ll
+0-182libcxx/test/libcxx/strings/basic.string/asan_vector_integration.pass.cpp
+0-182libcxx/test/libcxx/strings/basic.string/asan_deque_integration.pass.cpp
+116-0mlir/test/python/dialects/ext.py
+101-1llvm/unittests/IR/VerifierTest.cpp
+99-0mlir/test/CAPI/ir.c
+586-36575 files not shown
+1,641-73681 files

LLVM/project c0a8d9fclang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaExprCXX.cpp SemaDeclCXX.cpp

[clang][P2719] Relax requirements for matching operator new and delete

The most recent revision of P2719 introduced very strict rules about
matching parameter sets between type aware operators new and delete.

The intention was to resolve the classic "no matching operator delete
has been found so the object will silently leak" problem. The strict
rules however made deleting objects that had a placement new
"impossible".

I missed this however as all of our large scale tests involved
projects that were already using manually implemented allocators
(often trying to support type isolation). The problem with this from
a validation point of view is simple: all of these projects had
existing class scoped operators, and the untyped delete was silently
selected, avoiding the need for a non-placement type-aware delete
that would conflict with the placement cleanup delete.

The next revision of P2719 resolves this by removing the exact type

    [6 lines not shown]
DeltaFile
+60-42clang/lib/Sema/SemaExprCXX.cpp
+52-33clang/test/SemaCXX/type-aware-class-scoped-mismatched-constraints.cpp
+59-17clang/test/SemaCXX/type-aware-new-delete-basic-resolution.cpp
+38-27clang/lib/Sema/SemaDeclCXX.cpp
+7-4clang/include/clang/Basic/DiagnosticSemaKinds.td
+0-6clang/test/SemaCXX/type-aware-coroutines.cpp
+216-1292 files not shown
+218-1318 files

LLVM/project c9d713allvm/lib/CodeGen/GlobalISel IRTranslator.cpp

[GlobalISel] Fast-path single reg loads and stores in IRTranslator (#195245)

IRTranslator::translateLoad is hot in compile-time profiles of sqlite on
aarch64-O0-g. Aggregates are flattened into multiple vregs with offsets.
Most loads and stores lower to a single register so this offset
materialization can be avoided.

Small -0.07% geomean improvement on aarch64-O0-g with -0.24% for sqlite.

https://llvm-compile-time-tracker.com/compare.php?from=a7a2dc59616a8cb1198d933bcdf55ebdbd78894c&to=e535e96fd0952cfa646d48ef84cf5948c0a8a2ab&stat=instructions%3Au
DeltaFile
+34-17llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+34-171 files

LLVM/project d30d5fellvm/lib/CodeGen/GlobalISel IRTranslator.cpp

[GlobalISel] Fast-path single vreg values in getOrCreateVRegs (#195244)

IRTranslator::translateLoad is hot in compile-time profiles of sqlite on
aarch64-O0-g. Aggregates are flattened into multiple vregs with offsets.
Avoiding this path for single vregs is a small -0.11% compile-time win.

https://llvm-compile-time-tracker.com/compare.php?from=a7a2dc59616a8cb1198d933bcdf55ebdbd78894c&to=96fcfe733947db64effd5e1d1413697981cbe357&stat=instructions%3Au
DeltaFile
+25-20llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+25-201 files

LLVM/project 36b95famlir/include/mlir/Dialect/SPIRV/IR SPIRVBase.td, mlir/lib/Dialect/SPIRV/Transforms UpdateVCEPass.cpp

[mlir][SPIR-V] Add Weak linkage type and SPV_AMD_weak_linkage extension (#195660)

- add 'Weak' linkage type (SPV_AMD_weak_linkage)
- deduce the Linkage capability and linkage-type extension from
linkage_attributes in UpdateVCE pass

---------

Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
DeltaFile
+45-0mlir/test/Target/SPIRV/linkage-types.mlir
+28-0mlir/lib/Dialect/SPIRV/Transforms/UpdateVCEPass.cpp
+28-0mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
+9-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+110-24 files

LLVM/project edb9645flang/include/flang/Lower OpenMP.h AbstractConverter.h, flang/lib/Lower Bridge.cpp

support device_type groupprivate lowering
DeltaFile
+22-3flang/lib/Lower/OpenMP/OpenMP.cpp
+22-0flang/test/Lower/OpenMP/groupprivate.f90
+11-0flang/lib/Lower/Bridge.cpp
+11-0flang/include/flang/Lower/OpenMP.h
+11-0flang/include/flang/Lower/AbstractConverter.h
+77-35 files

LLVM/project 58d9781llvm/lib/Transforms/Utils CallPromotionUtils.cpp, llvm/test/Transforms/SampleProfile icp_target_feature.ll

[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features (#192142)

Profile-driven indirect call promotion was promoting indirect calls to
functions requiring advanced CPU features (e.g., AVX512) even when the
caller function did not support those features. When these promoted
calls were subsequently inlined, it could lead to invalid IR and
backend crashes during instruction selection because the target CPU
could not handle the advanced instructions.

This patch addresses the issue by adding a target feature
compatibility check to `llvm::isLegalToPromote` in
`CallPromotionUtils.cpp`. If the callee requires target features
(prefixed with `+`) that are not present in the caller's target
features, the promotion is skipped.  By centralizing this check in
`isLegalToPromote`, we protect all passes relying on this utility
(such as `SampleProfileLoader` and `IndirectCallPromotion`) from
promoting to incompatible targets. This also prevents incorrect
inlining of `always_inline` functions that would otherwise be promoted
via indirect calls and then inlined.

    [3 lines not shown]
DeltaFile
+61-0llvm/test/Transforms/SampleProfile/icp_target_feature.ll
+21-0llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
+82-02 files

LLVM/project b907c14clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR][NFC] Rename SignBitOp to CIR_SignBitOp (#195477)

Align with the CIR_ prefix naming convention used by other op
definitions in CIROps.td.
DeltaFile
+1-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+1-11 files

LLVM/project 81bdba1mlir/docs/Traits _index.md, mlir/include/mlir/IR OpDefinition.h OpBase.td

[MLIR] Add HasAncestor op trait (#195447)

Add HasAncestor/AncestorOneOf traits that verify an operation has a
specific ancestor anywhere in the parent chain, unlike HasParent which
only checks the immediate parent.
DeltaFile
+79-0mlir/test/IR/traits.mlir
+26-0mlir/include/mlir/IR/OpDefinition.h
+10-0mlir/docs/Traits/_index.md
+9-0mlir/test/lib/Dialect/Test/TestOps.td
+8-0mlir/include/mlir/IR/OpBase.td
+132-05 files

LLVM/project 00562c5mlir/lib/CAPI/Interfaces CMakeLists.txt

fix libMLIRCAPIInterfaces after #195505 (#195789)

https://github.com/llvm/llvm-project/pull/195505 missed
`MLIRSideEffectInterfaces` in the CMakeLists.txt.
DeltaFile
+2-1mlir/lib/CAPI/Interfaces/CMakeLists.txt
+2-11 files

LLVM/project 2d5abf3orc-rt/lib/executor/sps-ci MemoryAccessSPSCI.cpp SimpleNativeMemoryMapSPSCI.cpp, orc-rt/unittests MemoryAccessSPSCITest.cpp SimpleNativeMemoryMapSPSCITest.cpp

[orc-rt] Change SPS controller-interface naming conventions. (#195614)

This commit makes two changes to the naming conventions for SPS CI
symbols:

1. The orc_rt_sps_ci_ prefix is replaced with orc_rt_ci_sps_ (for SPS
wrapper functions) and orc_rt_ci_ (without the "sps_" suffix) for data
symbols.

2. The _sps_wrapper suffix is dropped from wrapper functions, since the
prefix now distinguishes between SPS-wrappers and data symbols.
DeltaFile
+28-28orc-rt/lib/executor/sps-ci/MemoryAccessSPSCI.cpp
+26-26orc-rt/unittests/MemoryAccessSPSCITest.cpp
+16-21orc-rt/lib/executor/sps-ci/SimpleNativeMemoryMapSPSCI.cpp
+8-13orc-rt/unittests/SimpleNativeMemoryMapSPSCITest.cpp
+8-9orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
+6-6orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
+92-1033 files not shown
+102-1139 files

LLVM/project 23b330dclang/include/clang/Options Options.td, flang/test/Driver print-file-name.f90

Enable -print-file-name for flang
DeltaFile
+13-0flang/test/Driver/print-file-name.f90
+1-1clang/include/clang/Options/Options.td
+0-0flang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/x86_64-unknown-linux-gnu/libflang_rt.runtime.a
+0-0flang/test/Driver/Inputs/resource_dir/share/asan_ignorelist.txt
+14-14 files

LLVM/project 227c3e4libcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,931 files not shown
+72,117-31,8281,937 files

LLVM/project 808b2dblibcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,932 files not shown
+72,119-31,8301,938 files

LLVM/project 3975cdblibcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,932 files not shown
+72,119-31,8301,938 files

LLVM/project 85c92d4libcxx/lib/abi i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+2,928-1,388llvm/test/CodeGen/X86/vector-reduce-smin.ll
+2,924-1,389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+2,677-1,279llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2,628-1,271llvm/test/CodeGen/X86/vector-reduce-umin.ll
+2,656-120utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2,338-0libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
+16,151-5,4471,925 files not shown
+72,039-31,8241,931 files

LLVM/project 4059891lld/ELF/Arch TargetImpl.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+1-1lld/ELF/Arch/TargetImpl.h
+1-11 files

LLVM/project 4448636llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize BUILD.gn, llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer BUILD.gn

[gn build] Port cb2a64e7e5af



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/195783
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn
+2-02 files

LLVM/project 8c8e053llvm/lib/CodeGen TargetInstrInfo.cpp, llvm/lib/Target/RISCV RISCVInstrInfo.h

[X86][APX] Add VirtRegMap to non stack foldMemoryOperand too (#193423)

We need to query mapped physical register through VirtRegMap.

Fixes: https://godbolt.org/z/1KGj3aYeP
DeltaFile
+270-0llvm/test/CodeGen/X86/apx/memfold-no-physreg.ll
+6-5llvm/lib/Target/X86/X86InstrInfo.h
+6-5llvm/lib/Target/RISCV/RISCVInstrInfo.h
+5-6llvm/lib/CodeGen/TargetInstrInfo.cpp
+6-5llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+6-4llvm/lib/Target/X86/X86InstrInfo.cpp
+299-256 files not shown
+311-3412 files