[libclang/python] Move SPELLING_CACHE into CodeCompletion (#177586)
This adresses point 2 from
https://github.com/llvm/llvm-project/issues/156680.
Also add a dummy object that serves as an alias to `SPELLING_CACHE`,
used to replicate the old behavior and throw a `DeprecationWarning`.
[libc++][ranges] implement `ranges::shift_left` (#83231)
Implement the `ranges::shift_left` algorithm from
[P2440R1](https://wg21.link/P2440R1).
Closes: #134061
---------
Co-authored-by: Hui Xie <hui.xie1990 at gmail.com>
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
[mlir][Affine] affine-super-vectorize transform op (#177755)
Added an operation in the transform dialect to apply the
affine-super-vectorize pass locally.
The operation vectorizes the loops that are children of the provided
operation, itself included.
Also added a test file verifying the operation behaves.
[mlir][python] Support Arbitrary Precision Integers in MLIR C API and Python Bindings (#177733)
This PR extends the MLIR C API and Python bindings to support
**arbitrary-precision integers (`APInt`)**, overcoming the previous
limitation where `IntegerAttr` values were restricted to 64 bits.
Cryptographic applications often require integer types much larger than
standard machine words (e.g., the 256-bit modulus for the BN254 curve).
Previously, attempting to bind these values resulted in truncation or
errors. This PR exposes the underlying word-based `APInt` structure via
the C API and updates the Python bindings to seamlessly handle Python's
arbitrary-precision integers.
[AMDGPU] Fix DomTree preservation in SILowerControlFlow when nodes are removed (#176691)
I would think the "applyUpdates" API should also take care of deleting
the nodes from the analyses objects but this does not seem to be the
case. https://godbolt.org/z/38a7rfzjd shows an example where
SILowerControlFlow removes a basic block which is not removed in the
Post dominator tree.
[RISCV] Use decodeVMaskReg for VMaskCarryInOp. NFC (#177742)
After #177678 we don't need DecodeVMV0RegisterClass to reject vm=1
cases. All instructions that use VMaskCarryInOp have set vm=0 in their
tablegen classes.
[AArch64][SME] Use LibcallLoweringInfo in the MachineSMEABIPass (#177762)
This adds a new helper to add calls to SME routines (addSMELibCall) and
check they are using the expected CC.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
[clang-tidy] Add llvm-use-vector-utils (#177722)
This new check suggests the following replacements:
* `llvm::to_vector(llvm::map_range(X, Fn))` -> `llvm::map_to_vector(X,
Fn)`
* `llvm::to_vector(llvm::make_filter_range(X, Fn))` ->
`llvm::filter_to_vector(X, Fn)`
and add the `SmallVectorExtras.h` include when necessary.
The check is called `vector-utils` because we may want to handle more
cases in the future, like turning explicit calls to SmallVector
constructor to `llvm::to_vector` (which lives in `SmallVector.h`, not
`SmallVectorExtras.h`).
Assisted-by: claude
SystemZ: Use correctly offset MachinePointerInfo in CC lowering (#177793)
Previously this was just using the original base address as
the pointer info.
[lldb] improve Doxygen rendering of an existing comment (#177785)
This commit improves the way how the example code attached to
`SBDebugger::GetSetting` method is rendered by Doxygen.
Co-authored-by: Matej Košík <matej.kosik at codasip.com>
[VPlan] Share and re-use logic to find FindIVResult (NFC).
Move logic to look for FindIVResult pattern out of LoopVectorize to
allow for re-use in current code and follow-up patches.
[MLIR][XeGPU] Preserve Leading dimension when blocking rank-sensitive operations (#177489)
This PR preserves leading dimensions for
xegpu.load_matrix/store_matrix/atomic_rmw/convert_layout, and vector
operations which have impact on shapes:
broadcast/multi-reduction/shape_cast/transpose.
Rank-sensitive operations are operations whose semantics depend on the
tensor rank (and consequently its shape), and therefore must not alter
the input tile rank or shape, such as by dropping leading dimensions.