LLVM/project 3c6b487orc-rt/include/orc-rt TaskGroup.h Session.h, orc-rt/test/unit TaskGroupTest.cpp SessionTest.cpp

[orc-rt] Add TaskGroup::TokenSource; drop raw group accessor (#210240)

Session::managedCodeTaskGroup() returned the raw
std::shared_ptr<TaskGroup> for the managed-code group, exposing the
group's full interface -- including close() and addOnComplete() -- to
callers, even though those operations are reserved for the Session.

Add TaskGroup::TokenSource, a strong handle whose sole role is to serve
as an argument to the TaskGroup::Token constructor. Session now exposes
managedCodeTokenSource() in its place, so clients can acquire tokens (to
keep managed code alive across shutdown) without gaining the ability to
close the group or register completion callbacks.
DeltaFile
+50-0orc-rt/test/unit/TaskGroupTest.cpp
+24-0orc-rt/include/orc-rt/TaskGroup.h
+5-5orc-rt/include/orc-rt/Session.h
+2-2orc-rt/test/unit/SessionTest.cpp
+81-74 files

LLVM/project fe64fbbllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/lib/Transforms/Vectorize/SLPVectorizer SLPUtils.cpp SLPUtils.h

[SLP][modularisation][NFC] Extract mask, shuffle and AA helpers into SLUtils 3/3 (#209973)

Move the mask/shuffle construction and alias-analysis free helpers out
of SLPVectorizer.cpp into SLPVectorizer/SLPUtils.{h,cpp} (namespace
llvm::slpvectorizer).

Moved:
  transformScalarShuffleIndiciesToVector
  getShufflevectorNumGroups
  calculateShufflevectorMask
  UseMask (enum)
  buildUseMask
  isUndefVector
  doesInTreeUserNeedToExtract
  getLocation
  isSimple
  addMask
  fixupOrderingIndices
  getAltInstrMask

    [2 lines not shown]
DeltaFile
+9-342llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+259-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
+112-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
+380-3423 files

LLVM/project 963e226.github/workflows release-binaries.yml, .github/workflows/validate-release-version action.yml

workflows: Fixes for release-binaries and upload-release-artifact (#209246)

There were some bugs in upload-release-artifact workflow and
release-binaries was not including this action in its checkout.
DeltaFile
+2-2.github/workflows/validate-release-version/action.yml
+1-0.github/workflows/release-binaries.yml
+3-22 files

LLVM/project ddd21a5flang/include/flang/Lower CUDA.h, flang/lib/Lower ConvertVariable.cpp Allocatable.cpp

[flang][cuda] Managed backing for -gpu=unified allocatables/pointers (#210149)

Under `-gpu=unified`, allocatables and pointers with no explicit CUDA data
attribute must be reachable from the device. Back them with CUDA managed
memory by selecting the unified allocator index at the ALLOCATE site (in
lowering), instead of stamping an implicit `Unified`/`Managed` CUDA data attribute
on the symbol in the frontend — the approach introduced in PR #209292.
This is necessary because attributing the symbol in the frontend routed every
plain allocatable/pointer through the CUDA Fortran managed descriptor
pipeline (constructor registration, `cuf.allocate`/`cuf.free`), which added
per-`ALLOCATE` overhead, forced special-casing for objects that may not legally carry a
CUDA attribute (COMMON members, derived-type components, module globals), and
changed symbol semantics used well beyond allocation. Choosing the allocator
index at the `ALLOCATE` site keeps the object a plain host allocatable/pointer while
the storage still comes from the managed allocator.
DeltaFile
+103-0flang/test/Lower/CUDA/cuda-gpu-unified.cuf
+0-80flang/test/Lower/CUDA/cuda-implicit-managed-alloc.cuf
+22-53flang/lib/Semantics/resolve-names.cpp
+18-17flang/lib/Lower/ConvertVariable.cpp
+30-3flang/lib/Lower/Allocatable.cpp
+16-0flang/include/flang/Lower/CUDA.h
+189-1536 files

LLVM/project e5f3ebeflang/lib/Semantics check-omp-variant.cpp check-omp-structure.h, flang/test/Semantics/OpenMP metadirective-default-none.f90

[flang][OpenMP] Check DEFAULT(NONE) on metadirective loop variants

Standalone metadirectives and their associated loops are separate parse-tree
nodes. For example:

```fortran
!$omp metadirective &
!$omp& when(implementation={vendor(llvm)}: &
!$omp& parallel do default(none) shared(n, a)) default(nothing)
do i = 1, n
  a(i) = x
end do
```

Unlike an ordinary PARALLEL DO, the loop is not nested under the directive:

```text
METADIRECTIVE
`-- WHEN

    [15 lines not shown]
DeltaFile
+224-0flang/test/Semantics/OpenMP/metadirective-default-none.f90
+166-1flang/lib/Semantics/check-omp-variant.cpp
+4-0flang/lib/Semantics/check-omp-structure.h
+394-13 files

LLVM/project d0047eellvm/test/CodeGen/RISCV zilx.ll

Add RUNs with zba and zba+zilx

Created using spr 1.3.6-beta.1
DeltaFile
+912-0llvm/test/CodeGen/RISCV/zilx.ll
+912-01 files

LLVM/project 8aaa15ellvm/include/llvm/ObjectYAML BBAddrMapYAML.h, llvm/lib/ObjectYAML BBAddrMapYAML.cpp ELFEmitter.cpp

[ObjectYAML][NFC] Hoist BBAddrMap yaml2obj encoder into a shared helper (#205991)

Preparatory NFC refactor to let the upcoming COFF emitter reuse the
BBAddrMap YAML encoder.
DeltaFile
+124-0llvm/lib/ObjectYAML/BBAddrMapYAML.cpp
+2-110llvm/lib/ObjectYAML/ELFEmitter.cpp
+12-3llvm/include/llvm/ObjectYAML/BBAddrMapYAML.h
+138-1133 files

LLVM/project 73eb817llvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic

The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.

Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:

- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
  Operations use APInt arithmetic at WideBits, chosen to guarantee no
  intermediate overflow:
  $$
    WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
  $$
  This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
  bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
  extra bits.

    [15 lines not shown]
DeltaFile
+412-417llvm/lib/Analysis/DependenceAnalysis.cpp
+104-3llvm/test/Analysis/DependenceAnalysis/banerjee-overflow.ll
+20-50llvm/include/llvm/Analysis/DependenceAnalysis.h
+2-4llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
+1-1llvm/test/Analysis/DependenceAnalysis/PR51512.ll
+539-4755 files

LLVM/project 4a75259llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx xvexth.ll issue207316.ll

[LoongArch] Fix invalid VEXTH combines for unsupported type extensions (#209725)

`performEXTENDCombine` could form `VEXTH`/`VEXTH_U` nodes for
unsupported type combinations, such as extending `v8i8` to `v8i32` or
`v2i64` to `v2i128`. These illegal nodes would later reach instruction
selection and trigger backend failures:

* `Cannot select: LoongArchISD::VEXTH`
* `Don't know how to legalize this operation`

Prevent these combines from firing by verifying that the destination
type is legal and has exactly twice the total bit width of the source
before forming a `VEXTH`/`VEXTH_U` node.
    
Apply the same checks to `performSHLCombine` for consistency.


Fixes
https://github.com/llvm/llvm-project/pull/207316#issuecomment-4978234865
Fixes
https://github.com/llvm/llvm-project/pull/207316#issuecomment-4979233899
DeltaFile
+78-2llvm/test/CodeGen/LoongArch/lasx/xvexth.ll
+56-2llvm/test/CodeGen/LoongArch/lsx/vexth.ll
+8-13llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+18-0llvm/test/CodeGen/LoongArch/lasx/issue207316.ll
+160-174 files

LLVM/project 27d7b61llvm/lib/Transforms/Scalar GVN.cpp

[GVN][NFC] Use LoadInst::getProperties() when creating PRE load (#208605)

Use load's properties via getProperties() instead of individually
forwarding isVolatile(), getAlign(), getOrdering() and getSyncScopeID().

Reference: https://github.com/llvm/llvm-project/pull/206470
DeltaFile
+4-4llvm/lib/Transforms/Scalar/GVN.cpp
+4-41 files

LLVM/project 1a3347futils/bazel/llvm-project-overlay/clang BUILD.bazel

[bazel][clang][ssaf] Fix 398f2117379f42764e433d19ea0d0cd65009a4aa (#210222)
DeltaFile
+5-1utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+5-11 files

LLVM/project 9d2181cllvm/lib/CodeGen/AsmPrinter DwarfExpression.cpp

[NFC] Reuse DwarfExpression fragment (#210181)

Reuse DwarfExpression fragment information since nothing changes it
between the outside of the loop and the inside of the loop.

Tested via make check.

Assisted by AI.
DeltaFile
+4-6llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
+4-61 files

LLVM/project 3aed01blibcxx/utils/libcxx/test format.py

fix

Created using spr 1.3.7
DeltaFile
+1-3libcxx/utils/libcxx/test/format.py
+1-31 files

LLVM/project 797cb3bllvm/lib/Target/WebAssembly WebAssemblyMemIntrinsicResults.cpp WebAssembly.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+78-30llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
+64-12llvm/lib/Target/WebAssembly/WebAssembly.h
+46-21llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
+45-12llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+36-12llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
+30-9llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
+299-964 files not shown
+351-12610 files

LLVM/project 2722579llvm/lib/Target/WebAssembly WebAssemblyMemIntrinsicResults.cpp WebAssemblyLateEHPrepare.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+78-30llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
+46-21llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
+54-10llvm/lib/Target/WebAssembly/WebAssembly.h
+45-12llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+30-9llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
+26-10llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
+279-923 files not shown
+301-1099 files

LLVM/project dd94ca5llvm/lib/Target/WebAssembly WebAssemblyMemIntrinsicResults.cpp WebAssemblyLateEHPrepare.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+78-30llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
+46-21llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
+54-10llvm/lib/Target/WebAssembly/WebAssembly.h
+45-12llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+30-9llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
+26-10llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
+279-923 files not shown
+301-1099 files

LLVM/project b596894llvm/lib/Target/WebAssembly WebAssemblyMemIntrinsicResults.cpp WebAssemblyLateEHPrepare.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+78-30llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
+46-21llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
+39-8llvm/lib/Target/WebAssembly/WebAssembly.h
+30-9llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
+26-10llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp
+8-8llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+227-862 files not shown
+237-928 files

LLVM/project dc071c3clang/docs DebuggingCoroutines.rst DebuggingCoroutines.md, llvm/test/CodeGen/AArch64 sve-fixed-length-fp-extend-trunc-bf16.ll sve-fixed-length-fp-extend-bf16.ll

rebase

Created using spr 1.3.7
DeltaFile
+0-1,295clang/docs/DebuggingCoroutines.rst
+1,270-0clang/docs/DebuggingCoroutines.md
+852-327llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
+0-1,007clang/docs/BoundsSafety.rst
+0-994llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
+994-0llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
+3,116-3,6231,102 files not shown
+37,356-16,5991,108 files

LLVM/project c7c236aclang/docs DebuggingCoroutines.rst DebuggingCoroutines.md, llvm/test/CodeGen/AArch64 sve-fixed-length-fp-extend-bf16.ll sve-fixed-length-fp-extend-trunc-bf16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-1,295clang/docs/DebuggingCoroutines.rst
+1,270-0clang/docs/DebuggingCoroutines.md
+852-327llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
+0-1,007clang/docs/BoundsSafety.rst
+994-0llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
+0-994llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
+3,116-3,6231,102 files not shown
+37,356-16,5991,108 files

LLVM/project 13a7c58clang/docs DebuggingCoroutines.rst DebuggingCoroutines.md, llvm/test/CodeGen/AArch64 sve-fixed-length-fp-extend-bf16.ll sve-fixed-length-fp-extend-trunc-bf16.ll

rebase

Created using spr 1.3.7
DeltaFile
+0-1,295clang/docs/DebuggingCoroutines.rst
+1,270-0clang/docs/DebuggingCoroutines.md
+852-327llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
+0-1,007clang/docs/BoundsSafety.rst
+994-0llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
+0-994llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
+3,116-3,6231,102 files not shown
+37,356-16,5991,108 files

LLVM/project 26a04b8clang/docs DebuggingCoroutines.rst DebuggingCoroutines.md, llvm/test/CodeGen/AArch64 sve-fixed-length-fp-extend-bf16.ll sve-fixed-length-fp-extend-trunc-bf16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-1,295clang/docs/DebuggingCoroutines.rst
+1,270-0clang/docs/DebuggingCoroutines.md
+852-327llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
+0-1,007clang/docs/BoundsSafety.rst
+994-0llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
+0-994llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
+3,116-3,6231,102 files not shown
+37,356-16,5991,108 files

LLVM/project cfff16cclang/docs DebuggingCoroutines.rst DebuggingCoroutines.md, llvm/test/CodeGen/AArch64 sve-fixed-length-fp-extend-bf16.ll sve-fixed-length-fp-extend-trunc-bf16.ll

rebase

Created using spr 1.3.7
DeltaFile
+0-1,295clang/docs/DebuggingCoroutines.rst
+1,270-0clang/docs/DebuggingCoroutines.md
+852-327llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
+0-1,007clang/docs/BoundsSafety.rst
+994-0llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
+0-994llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
+3,116-3,6231,102 files not shown
+37,356-16,5991,108 files

LLVM/project b3c5e68clang/docs DebuggingCoroutines.rst DebuggingCoroutines.md, llvm/test/CodeGen/AArch64 sve-fixed-length-fp-extend-bf16.ll sve-fixed-length-fp-extend-trunc-bf16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-1,295clang/docs/DebuggingCoroutines.rst
+1,270-0clang/docs/DebuggingCoroutines.md
+852-327llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
+0-1,007clang/docs/BoundsSafety.rst
+994-0llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
+0-994llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
+3,116-3,6231,102 files not shown
+37,356-16,5991,108 files

LLVM/project 7981e43clang/docs DebuggingCoroutines.rst DebuggingCoroutines.md, llvm/test/CodeGen/AArch64 sve-fixed-length-fp-extend-trunc-bf16.ll sve-fixed-length-fp-extend-bf16.ll

rebase

Created using spr 1.3.7
DeltaFile
+0-1,295clang/docs/DebuggingCoroutines.rst
+1,270-0clang/docs/DebuggingCoroutines.md
+852-327llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
+0-1,007clang/docs/BoundsSafety.rst
+0-994llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
+994-0llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
+3,116-3,6231,102 files not shown
+37,356-16,5991,108 files

LLVM/project 2fd1dbdclang/docs DebuggingCoroutines.rst DebuggingCoroutines.md, llvm/test/CodeGen/AArch64 sve-fixed-length-fp-extend-trunc-bf16.ll sve-fixed-length-fp-extend-bf16.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-1,295clang/docs/DebuggingCoroutines.rst
+1,270-0clang/docs/DebuggingCoroutines.md
+852-327llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
+0-1,007clang/docs/BoundsSafety.rst
+0-994llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc-bf16.ll
+994-0llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-bf16.ll
+3,116-3,6231,102 files not shown
+37,356-16,5991,108 files

LLVM/project d7929b0llvm/lib/Target/AMDGPU SOPInstructions.td, llvm/test/CodeGen/AMDGPU uaddsat.ll

[AMDGPU] Lower uniform uaddsat to SALU instructions

Map uniform uaddsat.i16(i16 a, i16 b) to the following:

```
s_and_b32 s2, s0, 0xffff    ; s0 = i16 a
s_and_b32 s3, s1, 0xffff    ; s1 = i16 b
s_add_i32 s4, s3, s2
s_min_u32 s5, s4, 0xffff
```
DeltaFile
+122-82llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+56-0llvm/test/CodeGen/AMDGPU/uaddsat.ll
+8-2llvm/lib/Target/AMDGPU/SOPInstructions.td
+186-843 files

LLVM/project 7fec267libc/test/src/stdfix DiviFxTest.h

[libc][stdfix] Guard DiviFxTest shift edge cases against narrow IntType (#209970)

Fixes riscv32 buildbot failure from #206115.
DeltaFile
+4-2libc/test/src/stdfix/DiviFxTest.h
+4-21 files

LLVM/project 718a361clang/lib/Analysis ThreadSafety.cpp

fix clang-format
DeltaFile
+1-3clang/lib/Analysis/ThreadSafety.cpp
+1-31 files

LLVM/project 464b46aclang/lib/CodeGen CGCall.cpp CodeGenTypes.h, clang/lib/CodeGen/Targets X86.cpp

[clang][CodeGen][X86_64] Honor per-function AVX ABI in C/C++ call paths, maintain old psABI for PlayStation. (#193298)

Fixes https://github.com/llvm/llvm-project/issues/64706

Wire per function x86 AVX ABI level into CodeGen arrangement methods so
__attribute(__target("avx"))) / __attribute(__target("avx512f"))) on
methods, ctors, and free-functions affects ABI lowering consistently.
    
Specifically:
- Added X86AVXABILevel member to CGFunctionInfo.
- Populated X86AVXABILevel member in CGFunctionInfo objects via
arrangement methods declared in CodeGenTypes.h.
- Respect CGFunctionInfo AVX Level in X86_64ABIInfo::computeInfo.
- Add/extend regression tests for:
- free-function target-attribute AVX ABI lowering
- C++ method/ctor target-attribute AVX ABI lowering
- PS4/PS5 legacy ABI behavior (no per-function AVX ABI change)

---------

Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
DeltaFile
+105-51clang/lib/CodeGen/CGCall.cpp
+128-15clang/unittests/CodeGen/CodeGenExternalTest.cpp
+121-0clang/test/CodeGenCXX/target-avx-method-abi.cpp
+71-0clang/test/CodeGen/target-avx-function-abi.c
+54-1clang/lib/CodeGen/Targets/X86.cpp
+24-13clang/lib/CodeGen/CodeGenTypes.h
+503-8022 files not shown
+626-12328 files

LLVM/project b9869c8llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ISelLowering.h, llvm/test/CodeGen/AArch64 sve-fixed-length-masked-64-128bit-loads.ll sve-fixed-length-masked-64-128bit-stores.ll

[AArch64][SVE] Support lowering masked loads/stores of <4 x bf16> and <8 x bf16> (#208744)

Add support for lowering masked loads/stores of <4 x bf16> and <8 x
bf16> when target features contain "+sve" and "+bf16".

Fixes: #201149
DeltaFile
+148-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-loads.ll
+143-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-64-128bit-stores.ll
+13-7llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+4-1llvm/lib/Target/AArch64/AArch64ISelLowering.h
+308-84 files