LLVM/project e0a8d72 — llvm/test/Transforms/PhaseOrdering/X86 vector-reduction-known-first-value.ll

[PhaseOrdering][X86] vector-reduction-known-first-value.ll - add x86-64/x86-64-v2/x86-64-v3/x86-64-v4 test coverage (#230506)

Inspired by #229997
DeltaFile
+298-28llvm/test/Transforms/PhaseOrdering/X86/vector-reduction-known-first-value.ll
+298-281 files

LLVM/project 1fcf35c — lldb/test/API lit.cfg.py, lldb/test/Shell lit.cfg.py

[lldb][test] Use a fake dsymForUUID in tests (#201547)

Our test should not invoke dsymForUUID as it creates an unnecessary
dependency on the OS and is also incredibly slow. For example, all
Crashlog tests on my system run for more than 30s and all of this is
just spent waiting for dsymForUUID to return "not found".

This patch provides a simple dummy dsymForUUID script we set for all
tests. This is automatically picked up by LLDB with the existing
dsymForUUID environment variable. As a result, all crashlog tests which
previously run in total for about 4 minutes with one job, now run in
about 10s.

assisted-by: claude
DeltaFile
+10-0lldb/test/API/lit.cfg.py
+9-0lldb/test/Utils/fake-dsymForUUID.sh
+7-0lldb/test/Shell/lit.cfg.py
+0-2lldb/test/Shell/ScriptInterpreter/Python/Crashlog/lit.local.cfg
+26-24 files

LLVM/project 04fc855 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 disjoint-or-reductions.ll

[SLP]Fix miscompile with mixed sext/zext in disjoint or reduction

matchesShlZExt accepted an alternate zext/sext node, so a sext lane
passed the check and the reduction was folded to a plain wide load,
dropping the sign extension. Reject alt-shuffle operand nodes.

Fixes #230400

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/230534
DeltaFile
+6-1llvm/test/Transforms/SLPVectorizer/X86/disjoint-or-reductions.ll
+1-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+7-22 files

LLVM/project a51e9d9 — offload/include/OpenMP OffloadRTL.h, offload/libomptarget OffloadRTL.cpp

add fullstops
DeltaFile
+1-1offload/libomptarget/OffloadRTL.cpp
+1-1offload/include/OpenMP/OffloadRTL.h
+2-22 files

LLVM/project af8f312 — offload/include PluginManager.h, offload/include/OpenMP OffloadRTL.h

[offload][nfc] Pull OpenMP's InteropTbl out of PluginManager

PluginManager is shared with OpenACC, so the OpenMP interop table moves
to OmpPluginManager in libomptarget. The OpenMP PM is defined there, and
interop cleanup is registered from initRuntime.
DeltaFile
+12-4offload/libomptarget/OffloadRTL.cpp
+10-1offload/include/OpenMP/OffloadRTL.h
+0-7offload/libompaccsupport/PluginManager.cpp
+0-5offload/include/PluginManager.h
+22-174 files

LLVM/project 7714af1 — offload/include PluginManager.h, offload/include/OpenMP OffloadRTL.h

make loadImagesOntoDevice a member
DeltaFile
+6-6offload/libompaccsupport/PluginManager.cpp
+3-6offload/include/PluginManager.h
+6-0offload/include/OpenMP/OffloadRTL.h
+15-123 files

LLVM/project df2b808 — llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine minmax-fold.ll

[InstCombine] Mark profiles unknown in foldClampRangeOfTwo (#230297)

Within the function we only have the intrinsic rather than a select from
which to derive profile information. In the test case there is a select
we could derive profile information from, but it gets folded to an
intrinsic which then gets re-expanded into a select, dropping the
profile information in the process.
DeltaFile
+8-3llvm/test/Transforms/InstCombine/minmax-fold.ll
+4-1llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+0-2llvm/utils/profcheck-xfail.txt
+12-63 files

LLVM/project 628ee3d — llvm/include/llvm/CodeGen MachineBlockHashInfo.h AsmPrinter.h, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

[NewPM] [AsmPrinter] Correctly query analysis in NewPM and legacy (#230225)

While running llc under NewPM, we may get a crash due to no logic to
correctly query analysis depending whether we run NewPM / legacy
DeltaFile
+60-16llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+10-0llvm/include/llvm/CodeGen/AsmPrinter.h
+1-2llvm/lib/Target/X86/X86MCInstLower.cpp
+3-0llvm/test/CodeGen/X86/branch-hint.ll
+2-0llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
+76-185 files

LLVM/project ef15c4f — llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] LowerMSTORE - fix copy+paste assert message typo. NFC. (#230507)

MSTORE can be a compressing store (badly copied from MLOAD which can be
an expanding load).
DeltaFile
+2-2llvm/lib/Target/X86/X86ISelLowering.cpp
+2-21 files

LLVM/project c99d1d9 — llvm/test/Transforms/SLPVectorizer/X86 disjoint-or-reductions.ll

[SLP][NFC]ADd a test with incorrect optimization, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/230530
DeltaFile
+24-0llvm/test/Transforms/SLPVectorizer/X86/disjoint-or-reductions.ll
+24-01 files

LLVM/project 45e374f — llvm/utils profcheck-xfail.txt

[ProfCheck] Add xfail for new-values-after-pass.ll (#230523)

Added in #221519. This uses lower-atomic which hasn't been fixed yet.
DeltaFile
+1-0llvm/utils/profcheck-xfail.txt
+1-01 files

LLVM/project a7974c5 — clang/lib/Sema SemaOpenACC.cpp, clang/test/CIR/CodeGenOpenACC declare-const-var.cpp

[OpenACC] Make sure we mark vars as 'used' in OpenACC var references (#230503)

We weren't properly marking variables as 'used', which caused the bug in
issue #230329. There is a function to clean this up at the end of an
expression(CleanupVarDeclMarking) that we would never call as part of
this handling. OpenMP does this correctly, so we do too.

I wasn't able to reproduce it, but the 'invalid var' reference needs to
be set as well, as I believe this will leave Sema in a 'bad' state if we
don't, particularly if the function were to immediately end after the
invalid reference (ActOnFinishFunctionBody asserts here, but it isn't
    clear to me we would have run afoul of this).

Fixes: #230329
DeltaFile
+25-0clang/test/SemaOpenACC/const-var-used.cpp
+10-0clang/test/CIR/CodeGenOpenACC/declare-const-var.cpp
+5-0clang/lib/Sema/SemaOpenACC.cpp
+40-03 files

LLVM/project b3e5963 — llvm/test/CodeGen/AMDGPU frame-index-elimination.ll, llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs amdgpu_asm.ll.expected amdgpu_isel.ll.expected

Test: Make the load/store alloca to volatile to stop promotion (#230426)

This would help making the test checks unchanged in the upcoming alloca
promotion change.

Co-Authored-By: Claude
DeltaFile
+82-43llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected
+82-43llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected
+23-23llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll
+15-14llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
+11-11llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_asm.ll.expected
+8-7llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
+221-1415 files not shown
+240-16411 files

LLVM/project 3b15a59 — offload/libomptarget omptarget.cpp

[Offload][Omp] Add extra comments to register/unregister memory (#230512)

Add missed comments from #226450
DeltaFile
+2-0offload/libomptarget/omptarget.cpp
+2-01 files

LLVM/project 5949beb — clang/test/CodeGenHIP amdgpu-barrier-type.hip, clang/test/SemaCXX amdgpu-barrier.cpp

[AMDGPU] Make named barrier type 1 byte to fix barrier IDs of array elements

Since #209746, a pointer in the barrier address space (15) is the barrier ID,
and the backend reads the ID as `ptr & 0x3F`. But `target("amdgcn.named.barrier", 0)`
is still 16 bytes, so GEP to element `i` of a barrier array adds `16 * i` to the
barrier ID. For example, if `@bars` gets barrier ID 1, `&bars[2]` selects barrier
33 instead of 3.

This PR changes the type to 1 byte, so one array element is one barrier ID.

Fixes LCOMPILER-2898.
DeltaFile
+10-78llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
+14-22llvm/test/CodeGen/AMDGPU/s-barrier-array-index.ll
+5-5clang/test/CodeGenHIP/amdgpu-barrier-type.hip
+2-4llvm/lib/IR/Type.cpp
+2-2clang/test/SemaHIP/amdgpu-barrier.hip
+2-2clang/test/SemaCXX/amdgpu-barrier.cpp
+35-1134 files not shown
+39-11710 files

LLVM/project cceb4e6 — llvm/test/CodeGen/AMDGPU s-barrier-array-index.ll

[NFC][AMDGPU] Add test for indexing into named barrier arrays
DeltaFile
+152-0llvm/test/CodeGen/AMDGPU/s-barrier-array-index.ll
+152-01 files

LLVM/project 626eeb8 — libc/src/__support/macros attributes.h optimization.h

[libc] Fix LIBC_LIKELY/LIBC_UNLIKELY and add LIBC_NOINLINE. (#230505)

`__builtin_expect(value, expected)` requires the second argument to be a
constant expression. Previously, `LIBC_LIKELY` and `LIBC_UNLIKELY`
wrapped `__builtin_expect(value, expected)` inside
`details::expects_bool_condition(T value, T expected)`, where `expected`
was a function parameter rather than a constant expression. So the hints
were silently dropped by the compilers.

Also add LIBC_NOINLINE macro to `attributes.h` to outlining slow paths.
DeltaFile
+11-4libc/src/__support/macros/optimization.h
+8-0libc/src/__support/macros/attributes.h
+19-42 files

LLVM/project c3f2376 — mlir/lib/Dialect/Affine/IR AffineOps.cpp, mlir/test/Conversion/AffineToStandard lower-affine.mlir

Revert "[mlir][affine] Admit signless integers for affine.parallel maxs/mins/…"

This reverts commit 380fcd8b4334846838412960c1117932b6a60364.
DeltaFile
+0-34mlir/test/Conversion/AffineToStandard/lower-affine.mlir
+0-24mlir/test/Dialect/Affine/invalid.mlir
+0-19mlir/test/Dialect/Affine/parallelize.mlir
+10-7mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+0-12mlir/test/Dialect/Affine/ops.mlir
+10-965 files

LLVM/project cab70db — llvm/test/MC/AArch64 armv9.8a-cflt-diagnostics.s arm64-diags.s, llvm/test/MC/AArch64/SVE str-diagnostics.s ldr-diagnostics.s

[AArch64][llvm] Fix incorrect diagnostic (index/immediate in simm9)

Improve the error message in the simm9 diagnostics and use the word
'immediate' instead of 'index'. This was noticed when creating the
CFLT instructions for Armv9.8-A, but would have caused a lot of
unrelated churn if merged as part of that change.

Co-authored-by: Martin Wehking <martin.wehking at arm.com>
DeltaFile
+82-82llvm/test/MC/AArch64/basic-a64-diagnostics.s
+39-39llvm/test/MC/AArch64/armv8.4a-ldst-error.s
+5-5llvm/test/MC/AArch64/arm64-diags.s
+4-4llvm/test/MC/AArch64/SVE/str-diagnostics.s
+4-4llvm/test/MC/AArch64/SVE/ldr-diagnostics.s
+2-2llvm/test/MC/AArch64/armv9.8a-cflt-diagnostics.s
+136-1361 files not shown
+137-1377 files

LLVM/project a9f73fc — llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/test/MC/AArch64 armv8.5a-mte-error.s basic-a64-diagnostics.s

fixup! And fix all the other cases
DeltaFile
+69-69llvm/test/MC/AArch64/basic-a64-diagnostics.s
+53-53llvm/test/MC/AArch64/armv8.5a-mte-error.s
+37-29llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+16-16llvm/test/MC/AArch64/SVE/st1h-diagnostics.s
+16-16llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s
+14-14llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s
+205-197113 files not shown
+667-659119 files

LLVM/project e7e7e84 — llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/test/MC/AArch64 armv8.5a-mte-error.s armv9.8a-cflt-diagnostics.s

[AArch64][llvm] Improve diagnostics for invalid operands

Return `DiagnosticPredicate` from `isSImm()`, `isImmInRange()`, and
`isUImm12Offset()` so invalid operand types do not produce misleading
immediate range errors, while out-of-range constants retain their
range diagnostics.

Keep the load/store fallback predicate boolean and remove the
CFLT-specific diagnostic workaround. Update affected diagnostic
tests and add prefetch and CFLT regression testcases.
DeltaFile
+16-17llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+14-14llvm/test/MC/AArch64/basic-a64-diagnostics.s
+5-5llvm/test/MC/AArch64/neon-diagnostics.s
+9-0llvm/test/MC/AArch64/armv9.8a-cflt-diagnostics.s
+3-3llvm/test/MC/AArch64/SME2p1/zero-diagnostics.s
+2-2llvm/test/MC/AArch64/armv8.5a-mte-error.s
+49-4121 files not shown
+71-6327 files

LLVM/project bd58c85 — llvm/lib/Target/AArch64 AArch64InstrFormats.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Fix constant expressions in CMPBR immediate aliases (#230050)

Use the standard immediate parser for CMPBR aliases so that
parenthesized
expressions and explicit unary plus are accepted. This also simplifies
the amount of code required, since we can remove `tryParseAdjImm0_63`,
and reuse code in `AdjImmAsmOperand` which does the same job.

Check immediates in their original ranges and apply the adjustment
when rendering MC operands. Add coverage for constant expressions in
`cbge`, `cbhs`, `cble` and `cbls`.

---

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href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
DeltaFile
+17-30llvm/lib/Target/AArch64/AArch64InstrFormats.td
+0-35llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+13-0llvm/test/MC/AArch64/CMPBR/cmpbr_aliases.s
+30-653 files

LLVM/project 4dc2239 — llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Armv9.8-A: Add support for FEAT_RLCS (release consistency scoping) (#229364)

Add support for FEAT_RLCS (release consistency scoping) instructions:
  - SRLS
  - SLBND

---

<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
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DeltaFile
+33-0llvm/test/MC/AArch64/armv9.8a-rlcs.s
+31-0llvm/test/MC/AArch64/armv9.8a-rlcs-diagnostics.s
+3-1llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+3-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+70-14 files

LLVM/project f24645c — llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td, llvm/test/MC/AArch64 directive-arch_extension-negative.s directive-arch-negative.s

[AArch64][llvm] Armv9.8-A: Add support for FEAT_LSC64B (single-copy atomic 64-byte load/store) (#229363)

Add support for FEAT_LSC64B (single-copy atomic 64-byte load/store)
instructions:

  - LDA64B
  - STL64B
  - STL64BV
  - STL64BV0

---

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DeltaFile
+81-0llvm/test/MC/AArch64/armv9.8a-lsc64b.s
+67-0llvm/test/MC/AArch64/armv9.8a-lsc64b-diagnostics.s
+10-10llvm/lib/Target/AArch64/AArch64InstrFormats.td
+13-4llvm/lib/Target/AArch64/AArch64InstrInfo.td
+6-0llvm/test/MC/AArch64/directive-arch_extension-negative.s
+6-0llvm/test/MC/AArch64/directive-arch-negative.s
+183-147 files not shown
+203-1513 files

LLVM/project a8f1f81 — llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Armv9.8-A: Add support for FEAT_CFLT (Conditional Fault instructions) (#229362)

Add support for FEAT_CFLT (Conditional Fault instructions), which
are optional from Armv9.7 onwards:
```
 CFLTEQ, CFLTNE,
 CFLTGT, CFLTLT,
 CFLTGE, CFLTLE,
 CFLTHI, CFLTLO,
 CFLTHS, CFLTLS,
 CFLTZ,  CFLTNZ,
 TFLTZ,  TFLTNZ,
 FLT.NE, FLT.EQ,
 FLT.MI, FLT.PL,
 FLT.VS, FLT.VC,
 FLT.HI, FLT.LS,
 FLT.GE, FLT.LT,
 FLT.GT, FLT.LE,
 FLT.AL, FLT.NV,

    [8 lines not shown]
DeltaFile
+341-0llvm/test/MC/AArch64/armv9.8a-cflt.s
+136-0llvm/lib/Target/AArch64/AArch64InstrFormats.td
+95-0llvm/test/MC/AArch64/armv9.8a-cflt-diagnostics.s
+49-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+30-2llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+6-0llvm/test/MC/AArch64/directive-arch_extension-negative.s
+657-27 files not shown
+682-213 files

LLVM/project 2e61419 — clang/lib/Basic/Targets AArch64.cpp, clang/test/Driver arm-cortex-cpus-1.c aarch64-v98a.c

[ARM][AArch64] Introduce the Armv9.8-A architecture version (#229361)

This introduces the Armv9.8-A architecture version, including the
relevant command-line option for -march.

More details about the Armv9.8-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2026
*
https://support.arm.com/documentation/109697/2026_09/2026-Architecture-Extensions
*
https://support.arm.com/documentation/109697/2026_09/Future-Architecture-Technologies
  * https://support.arm.com/documentation/ddi0602/2026-09/

---

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DeltaFile
+19-0clang/test/Driver/aarch64-v98a.c
+16-0clang/test/Driver/arm-cortex-cpus-1.c
+12-0llvm/lib/Target/ARM/ARMArchitectures.td
+11-0clang/lib/Basic/Targets/AArch64.cpp
+8-2llvm/unittests/TargetParser/TargetParserTest.cpp
+7-0llvm/lib/Target/AArch64/AArch64Features.td
+73-216 files not shown
+116-522 files

LLVM/project 380fcd8 — mlir/lib/Dialect/Affine/IR AffineOps.cpp, mlir/test/Conversion/AffineToStandard lower-affine.mlir

[mlir][affine] Admit signless integers for affine.parallel maxs/mins/maxu/minu reductions (#230332)

🤖 Generated with [Claude Code](https://claude.com/claude-code)

https://claude.ai/code/session_016zErYp7upmqr4NHfhod9UD

Co-authored-by: Claude Fable 5.1 <noreply at anthropic.com>
DeltaFile
+34-0mlir/test/Conversion/AffineToStandard/lower-affine.mlir
+24-0mlir/test/Dialect/Affine/invalid.mlir
+19-0mlir/test/Dialect/Affine/parallelize.mlir
+7-10mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+12-0mlir/test/Dialect/Affine/ops.mlir
+96-105 files

LLVM/project cd7002b — offload/include device.h, offload/libompaccsupport device.cpp

[offload][omp] Use olMemRegister for memory locking (#226450)

Use olMemRegister for dataLock/Unlock operations.
Move OpenMP specific notifyDataMapped/UnMapped to libomptarget
implemented on top of olMemRegister.

Remove all associated interfaces in GenericPluginTy.

Assisted by Claude.
DeltaFile
+0-80offload/plugins-nextgen/common/src/PluginInterface.cpp
+61-6offload/libompaccsupport/device.cpp
+0-43offload/plugins-nextgen/common/include/PluginInterface.h
+9-9offload/libomptarget/omptarget.cpp
+15-0offload/include/device.h
+85-1385 files

LLVM/project dd289cc — libc/hdr/types idtype_t.h, libc/src/__support/OSUtil/linux/syscall_wrappers waitid.h

[libc] Implement waitid in sys/wait (#227815)

Implement the standard POSIX.1-2008 / POSIX.1-2024 function `waitid` in
`<sys/wait.h>`, bringing functions declared in `<sys/wait.h>` to 100%
completion.

Fixes #227798

### Notes
- Defines the POSIX `idtype_t` enumeration in `llvm-libc-types` along
with its proxy header.
- In `linux/sys-wait-macros.h`, undefines the kernel `P_*` macros
originating from `<linux/wait.h>` to prevent macro expansion over the
`idtype_t` enum constants.
- Adds unit tests in `libc/test/src/sys/wait/` and live process reaping
integration tests in `libc/test/integration/src/unistd/fork_test.cpp`.
DeltaFile
+44-0libc/test/src/sys/wait/waitid_test.cpp
+39-4libc/test/integration/src/unistd/fork_test.cpp
+38-0libc/src/__support/OSUtil/linux/syscall_wrappers/waitid.h
+36-0libc/src/sys/wait/linux/waitid.cpp
+28-0libc/src/sys/wait/waitid.h
+27-0libc/hdr/types/idtype_t.h
+212-413 files not shown
+310-419 files

LLVM/project 661b63e — llvm/lib/CodeGen MachineBasicBlock.cpp

CodeGen: Find PHI sources while rewriting PHIs in SplitCriticalEdge

SplitCriticalEdge scanned every operand of every PHI in Succ twice per
split: once in replacePhiUsesWith to retarget the incoming block, then
again with LiveIntervals to find the registers now coming from the new
block. Collect the source registers while retargeting the operands, so
each split scans Succ's PHIs only once.

Instructions retired in phi-node-elimination, x86_64 -O3, on a generated
chain of N compare blocks branching to a shared PHI block:

  N     before          after           after/before
  1k       89,072,376      69,208,524   0.78
  2k      330,305,622     251,128,551   0.76
  4k    1,140,509,526     818,125,849   0.72
  8k    4,134,353,260   2,851,571,872   0.69
  16k  15,538,463,961  10,437,522,736   0.67

gcc-c-torture compile/20001226-1.c (liveintervals,phi-node-elimination

    [5 lines not shown]
DeltaFile
+22-25llvm/lib/CodeGen/MachineBasicBlock.cpp
+22-251 files