LLVM/project dd0c192 — mlir/lib/Conversion/ArithToLLVM ArithToLLVM.cpp, mlir/test/Conversion/ArithToLLVM arith-to-llvm.mlir

[mlir][ArithToLLVM] Do not lower sitofp to unsupported float types (#230975)

The LLVM type converter maps float types with no LLVM equivalent (for
example
f8E4M3FN, f8E5M2 and f8E8M0FNU) to an integer of the same width. Unlike
`UIToFPOpLowering`, `FPToSIOpLowering` and `FPToUIOpLowering`,
`SIToFPOpLowering` did not set `FailOnUnsupportedFP`. As a result, it
produced an invalid op that the verifier rejects:

  'llvm.sitofp' op result #0 must be floating point LLVM type or LLVM
  dialect-compatible vector of floating point LLVM type, but got 'i8'

Reproducer (`mlir-opt --convert-arith-to-llvm`, or `--convert-to-llvm`):

  %0 = arith.sitofp %arg0 : i32 to f8E4M3FN

Set `FailOnUnsupportedFP` so that the op stays unconverted, as the other
int/float conversions already do. Users can emulate the op first with
`arith-emulate-unsupported-floats`.

    [5 lines not shown]
DeltaFile
+19-0mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
+3-1mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
+22-12 files

LLVM/project db36cde — mlir/include/mlir/Dialect/GPU/IR GPUOps.td, mlir/include/mlir/Dialect/OpenACC OpenACCOps.td

[mlir] `HasParallelRegion` means region may be parallel
DeltaFile
+64-0mlir/test/Dialect/Bufferization/Transforms/buffer-loop-hoisting.mlir
+22-19mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
+6-4mlir/include/mlir/Interfaces/LoopLikeInterface.h
+3-3mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
+4-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+2-1mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
+101-276 files not shown
+107-2912 files

LLVM/project cadc31b — llvm/lib/CodeGen MachineOutliner.cpp, llvm/lib/IR StructuralHash.cpp

[CodeGen] Source-qualify hashes of module-local globals for GFM and outliner (#219938)

Global function merging and outliner compare hashes across modules. Some
globals are hashed by name, so two modules that each define a same-named
global with local linkage produce identical operand hashes although they
denote different storage. The hash collision caused both GFM and GFO to
make quite a few non-beneficial optimization decisions.

Add a `SourceQualifyLocalGlobals` option to IR `StructuralHash` and MIR
`stableHashValue`. When set, the name-based hash of a global with local
linkage is combined with the source file name of its module. The module
identifier itself is not suitable: the linker may name the module after
an unstable temporary LTO object file, which would make the supposedly
stable hash vary from run to run and between the generate and use
rounds. Content-based hashes are unchanged, so equivalent literals still
merge across modules.

The option defaults to off, so other users of `stableHashValue` and
`StructuralHash` keep their hashes.
DeltaFile
+94-0llvm/unittests/MIR/MachineStableHashTest.cpp
+79-0llvm/test/CodeGen/AArch64/cgdata-outline-source-qualified-globals.ll
+60-0llvm/test/CodeGen/AArch64/cgdata-merge-source-qualified-globals.ll
+50-0llvm/unittests/IR/StructuralHashTest.cpp
+38-10llvm/lib/IR/StructuralHash.cpp
+12-2llvm/lib/CodeGen/MachineOutliner.cpp
+333-124 files not shown
+365-2210 files

LLVM/project f113621 — clang-tools-extra/clang-tidy/performance NoAutomaticMoveCheck.cpp, clang-tools-extra/docs ReleaseNotes.md

[clang-tidy] Fix false positive in performance-no-automatic-move for captured variables (#231359)

performance-no-automatic-move matched any `return x` where `x` is a
const local
variable, without checking whether `x` is actually local to the function
doing
the return. Inside a lambda, a captured variable still points at the
enclosing
function's VarDecl, so `[&x] { return x; }` was diagnosed. But captured
variables
are never implicitly moved from (Sema bails on
refersToEnclosingVariableOrCapture()
before it looks at constness), so dropping the const still gives a copy.

Now we skip DeclRefExprs that refer to a capture, same as
UseStdMoveCheck. A const
local declared inside the lambda body is still diagnosed.

AI Usage: an AI assistant was used while working on this fix, and I went

    [2 lines not shown]
DeltaFile
+30-1clang-tools-extra/test/clang-tidy/checkers/performance/no-automatic-move.cpp
+9-2clang-tools-extra/clang-tidy/performance/NoAutomaticMoveCheck.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.md
+44-33 files

LLVM/project 04aa80a — mlir/lib/Dialect/X86/Transforms VectorContractToAMXDotProduct.cpp, mlir/test/Dialect/X86/AMX vector-contract-to-tiled-dp.mlir

[mlir][x86] Fix AMX loop carried accumulation (#231170)

Fixes the AMX contraction lowering of reduction loops whose accumulators
are carried in by an enclosing loop.

The values accumulated by the enclosing loop were dropped and replaced
with the initial accumulator, which produced wrong results.

Assisted-by: Claude
DeltaFile
+699-0mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
+58-2mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
+757-22 files

LLVM/project 860e0b5 — clang/docs ReleaseNotes.md, clang/test/Sema pragma-weak.c

fixup! Merge branch 'main' into users/aokblast/clang/sema_accept_weak_after_decl
DeltaFile
+17-18clang/test/Sema/pragma-weak.c
+0-3clang/docs/ReleaseNotes.md
+17-212 files

LLVM/project c50d8f7 — llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.896bit.ll amdgcn.bitcast.960bit.ll

Merge branch 'main' into users/aokblast/clang/sema_accept_weak_after_decl
DeltaFile
+87,171-106,572llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+24,803-30,605llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+32,751-17,382llvm/test/CodeGen/AMDGPU/frem.ll
+23,347-23,371llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+17,152-20,808llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+15,838-19,315llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+201,062-218,05312,024 files not shown
+938,689-679,68312,030 files

LLVM/project 6c43b4f — clang/docs ReleaseNotes.md, clang/lib/AST ItaniumMangle.cpp

fixup! [Clang] Do not assume existing substition for template specialization
DeltaFile
+20-0clang/test/CodeGenCXX/mangle-subst-template-template-parm-gh88592.cpp
+0-15clang/test/CodeGenCXX/mangle-template.cpp
+6-2clang/docs/ReleaseNotes.md
+2-0clang/lib/AST/ItaniumMangle.cpp
+28-174 files

LLVM/project 4a51cf1 — clang/include/clang/Basic BuiltinsRISCV.td, clang/lib/CodeGen/TargetBuiltins RISCV.cpp

[RISCV][P-ext] Add scalar rev16 intrinsic (#230704)

Assisted-by: Claude
DeltaFile
+10-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+9-0llvm/test/CodeGen/RISCV/rv64p.ll
+5-0clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+4-0llvm/include/llvm/IR/IntrinsicsRISCV.td
+4-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+3-0clang/include/clang/Basic/BuiltinsRISCV.td
+35-02 files not shown
+37-08 files

LLVM/project f1e644b — clang/include/clang/Lex ModuleMap.h, clang/lib/Lex ModuleMap.cpp

[clang][Serialization] Make directory dependencies absolute when read (#231319)

Directory dependencies under a module's base directory are stored
relative to it, and the reader's base directory isn't always absolute:
with relocation checks enabled it is taken from where header search
found the module, which is relative through a relative search path, and
with -fmodule-file-home-is-cwd there is none. These directories were
then read back relative, so `directory-deps` reported them relative and
they never matched the absolute paths a build system reports as
invalidated.

Canonicalize them when reading the same way they are when recorded.

Assisted-by: Claude Code: opus-5.5
DeltaFile
+28-0clang/test/ClangScanDeps/modules-directory-deps.c
+13-0clang/test/Modules/validate-directory-dependencies.c
+7-2clang/lib/Serialization/ASTReader.cpp
+7-2clang/lib/Lex/ModuleMap.cpp
+5-0clang/include/clang/Lex/ModuleMap.h
+60-45 files

LLVM/project 00a93a0 — llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.896bit.ll amdgcn.bitcast.960bit.ll

Merge branch 'main' into users/aokblast/clang/itanium_mangle_fix_alias
DeltaFile
+87,171-106,572llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+24,803-30,605llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+32,751-17,382llvm/test/CodeGen/AMDGPU/frem.ll
+23,347-23,371llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+17,152-20,808llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+15,838-19,315llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+201,062-218,05312,024 files not shown
+938,685-679,68312,030 files

LLVM/project dff64a2 — llvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel legalizer-info-validation.mir

[RISCV][GlobalISel] Use minScalar for f16 sources of G_LROUND/G_LRINT. NFC (#231352)

Follow up of #231097
DeltaFile
+8-8llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+2-2llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+10-102 files

LLVM/project 3d93e07 — llvm/lib/Target/RISCV/GISel RISCVInstructionSelector.cpp, llvm/test/CodeGen/RISCV/GlobalISel half-fcmp.ll

[RISCV][GlobalISel] Mark manually selected FP comparisons as nofpexcept (#231360)

Like AArch64 (https://reviews.llvm.org/D115352), set `NoFPExcept` on the
FP compares built manually in `selectFPCompare`, matching what the
generated selector does for non-strict operations. This lets MachineCSE
combine identical compares.

This is safe because `selectFPCompare` only handles non-strict `G_FCMP`,
constrained comparison uses `G_STRICT_FCMP/G_STRICT_FCMPS`.
DeltaFile
+30-30llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-rv64.mir
+30-30llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-rv32.mir
+15-15llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir
+15-15llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir
+2-4llvm/test/CodeGen/RISCV/GlobalISel/half-fcmp.ll
+6-0llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+98-946 files

LLVM/project fda66c5 — llvm/lib/Support KnownFPClass.cpp, llvm/test/Transforms/Attributor nofpclass-trig.ll

[KnownFPClass] Teach KnownFPClass that tanh(non-positive) = non-positive (#229752)

tanh is sign-preserving, so if the source is known to never be a
non-zero positive value (pinf, psub, pnorm), the result can never be a
positive subnormal or normal either. Zero is intentionally not ruled
out: tanh(+-0.0) = +-0.0, and a flushed subnormal may become +0.0 under
the positive-zero denormal modes.

Add Attributor tests for the new deduction, for the cases where it must
not fire (+inf, positive normal or positive subnormal still possible),
and for the dynamic and positive-zero denormal modes. Update the
existing tanh tests whose result is now stronger.

Fixes #229535
DeltaFile
+136-12llvm/test/Transforms/Attributor/nofpclass-trig.ll
+12-2llvm/lib/Support/KnownFPClass.cpp
+148-142 files

LLVM/project 8da53b2 — llvm/lib/ObjCopy/ELF ELFObject.h ELFObject.cpp, llvm/unittests/ObjCopy ObjCopyTest.cpp

[llvm-objcopy] Stream ELF output to regular files

Write ELF output directly to seekable regular files instead of first allocating a buffer for the entire output. Keep buffered output for stdout and other non-seekable streams.

Use separate buffered and file-backed output implementations. Serialize regenerated metadata sequentially, seeking once per output range, and report sticky file errors after writing finishes. Truncate and extend seekable output up front so unwritten layout gaps read as zero without being materialized; explicitly overwrite only removed section contents within copied segments.

On a synthetic stamping-style ELF containing a 1 GiB payload, three warm-cache no-op copies had median peak RSS of 2,102,916 KiB before and 1,053,844 KiB after (49.9% lower). Median wall time improved from 1.06 s to 0.77 s, and the outputs were byte-identical.

Co-authored-by: Jeremy Braun <jtbraun at meta.com>
Co-authored-by: Fangrui Song <i at maskray.me>
Assisted-by: OpenAI Codex
DeltaFile
+152-100llvm/lib/ObjCopy/ELF/ELFObject.cpp
+86-9llvm/lib/ObjCopy/ELF/ELFObject.h
+62-0llvm/unittests/ObjCopy/ObjCopyTest.cpp
+300-1093 files

LLVM/project 4ad5aa3 — llvm/include/llvm/Support raw_ostream.h, llvm/lib/Support raw_ostream.cpp

[Support] Support seekable temporary output streams

Use raw_fd_stream for temporary outputs so callbacks can perform positioned writes and resize the destination. Add raw_fd_ostream::takeError and raw_fd_stream::resize, and return stream failures through Error while preserving an existing destination.

Co-authored-by: Jeremy Braun <jtbraun at meta.com>

Assisted-by: OpenAI Codex
DeltaFile
+66-0llvm/unittests/Support/raw_ostream_test.cpp
+48-3llvm/lib/Support/raw_ostream.cpp
+7-0llvm/include/llvm/Support/raw_ostream.h
+121-33 files

LLVM/project 40c2ffc — llvm/lib/ObjCopy/ELF ELFObject.h ELFObject.cpp, llvm/test/tools/llvm-objcopy/ELF many-sections.test

[llvm-objcopy] Route section copies through writeSectionContents

Centralize section byte copies behind a virtual helper so ELF output can later target either a memory buffer or a seekable stream. Materialize SHT_SYMTAB_SHNDX entries using the target ELF word type to preserve output endianness.

Co-authored-by: Jeremy Braun <jtbraun at meta.com>

Assisted-by: OpenAI Codex
DeltaFile
+25-15llvm/lib/ObjCopy/ELF/ELFObject.cpp
+4-0llvm/test/tools/llvm-objcopy/ELF/many-sections.test
+1-0llvm/lib/ObjCopy/ELF/ELFObject.h
+30-153 files

LLVM/project 6c2da1b — llvm/lib/Target/RISCV RISCVGISel.td, llvm/lib/Target/RISCV/GISel RISCVRegisterBankInfo.cpp RISCVLegalizerInfo.cpp

[RISCV][GlobalISel] Support orc.b (#230401)

Support llvm.riscv.orc.b in GlobalISel on RV32 and RV64 with Zbb,
including i32 on RV64.
DeltaFile
+39-0llvm/test/CodeGen/RISCV/GlobalISel/orc-b-rv64.ll
+20-0llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+12-0llvm/test/CodeGen/RISCV/GlobalISel/orc-b-rv32.ll
+7-0llvm/lib/Target/RISCV/RISCVGISel.td
+2-1llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+80-15 files

LLVM/project cbc50c0 — bolt/lib/Core Relocation.cpp, bolt/test/RISCV reloc-align.s

[BOLT][RISCV] Ignore alignment markers in linked binaries (#223994)

Skip `R_RISCV_ALIGN` when reading input relocations. It describes
padding used for linker relaxation rather than an address to relocate.
Since BOLT processes an already-linked binary, retained alignment
markers should not enter the ordinary relocation handling path.
DeltaFile
+29-0bolt/test/RISCV/reloc-align.s
+1-0bolt/lib/Core/Relocation.cpp
+30-02 files

LLVM/project 33a9c79 — bolt/lib/Core BinaryEmitter.cpp, bolt/test/RISCV patch-entry-size.s

[BOLT][RISCV] Emit PCREL_LO12 labels during size estimation (#224202)

BOLT skips instruction labels when emitting code for size estimation
with `EmitCodeOnly`. On RISC-V, however, `%pcrel_lo` fixups reference
labels on the corresponding `AUIPC` instructions. Omitting these labels
causes size estimation of entry patches to fail with **“ could not find
corresponding `%pcrel_hi` ”** when using `--force-patch`. Emit existing
RISC-V instruction labels in this mode so that PC-relative fixups can be
resolved.
DeltaFile
+22-0bolt/test/RISCV/patch-entry-size.s
+6-0bolt/lib/Core/BinaryEmitter.cpp
+28-02 files

LLVM/project 313665c — clang/lib/CIR/CodeGen TargetInfo.h CIRGenModule.cpp, clang/lib/CIR/CodeGen/Targets SPIRV.cpp

[CIR][SPIR-V] Move global address space selection to a target hook (#231098)

Discussed in https://github.com/llvm/llvm-project/pull/230813
DeltaFile
+20-0clang/test/CIR/CodeGenHIP/spirv-constant-addrspace.hip
+12-0clang/lib/CIR/CodeGen/Targets/SPIRV.cpp
+1-8clang/lib/CIR/CodeGen/CIRGenModule.cpp
+7-0clang/lib/CIR/CodeGen/TargetInfo.h
+40-84 files

LLVM/project 7680acb — llvm/lib/Target/SPIRV SPIRVLegalizePointerCast.cpp, llvm/test/CodeGen/SPIRV/pointers byte-address-buffer-load4.ll byte-address-buffer-store.ll

[SPIR-V] Fix crash on byte buffer vector access at dynamic offset (#230934)
DeltaFile
+43-8llvm/test/CodeGen/SPIRV/pointers/byte-address-buffer-store.ll
+27-0llvm/test/CodeGen/SPIRV/pointers/byte-address-buffer-load4.ll
+4-2llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
+74-103 files

LLVM/project eb5d41c — llvm/test/tools/llvm-ar error-opening-permission.test

Reword comment

Created using spr 1.3.7
DeltaFile
+2-2llvm/test/tools/llvm-ar/error-opening-permission.test
+2-21 files

LLVM/project 531c589 — llvm/test/tools/llvm-ar error-opening-permission.test

Move comment next to chmod line

Created using spr 1.3.7
DeltaFile
+2-2llvm/test/tools/llvm-ar/error-opening-permission.test
+2-21 files

LLVM/project a2dbe81 — llvm/test/CodeGen/X86/AMX pr228950.ll

[X86] Pin debug variable locations mode in pr228950.ll (#231278)

The CHECK lines in pr228950.ll assume instruction-referencing variable
locations, which is the x86_64 default. Under VarLoc-based
LiveDebugValues, llc emits a #DEBUG_VALUE comment between ldtilecfg and
tilezero, and the CHECK-NEXT fails.

Pass -experimental-debug-variable-locations=true so the test does not
depend on the default. This does not change upstream output.

rdar://189810853

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+1-1llvm/test/CodeGen/X86/AMX/pr228950.ll
+1-11 files

LLVM/project d6df1a3 — llvm/test/tools/llvm-ar error-opening-permission.test

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+2-0llvm/test/tools/llvm-ar/error-opening-permission.test
+2-01 files

LLVM/project d814497 — llvm/lib/Transforms/Utils BypassSlowDivision.cpp

[NFC] Fix wrong comment in insertFastDivAndRem (#230879)

The branch checks that the divisor IS a constant, not the opposite.
DeltaFile
+1-1llvm/lib/Transforms/Utils/BypassSlowDivision.cpp
+1-11 files

LLVM/project f7e87c3 — llvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel half-fcmp.ll

[RISCV][GlobalISel] Promote f16 to f32 for G_FCMP without Zfh (#231097)

Without Zfh, G_FCMP with f16 operands had no matching legalization rule,
so GlobalISel failed to legalize it.
This commit widen the operands to f32 instead, matching SelectionDAG,
which promotes f16 SETCC when Zfh is not available.

Godbolt link: https://godbolt.org/z/Y9P7Yqa8d
DeltaFile
+341-0llvm/test/CodeGen/RISCV/GlobalISel/half-fcmp.ll
+1-0llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+342-02 files

LLVM/project 106392e — llvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel half-imm.ll

[RISCV][GlobalISel] Use Zfhmin for G_FCONSTANT s16 (#230723)

`fmv.h.x` is available with Zfhmin, and the selector already
materializes f16 constants through a GPR and `fmv.h.x`. SelectionDAG
handles f16 constants with Zfhmin, but GlobalISel would abort because
G_FCONSTANT s16 was only legal with Zfh.

SelectionDAG: https://godbolt.org/z/coMc7j3x9
GlobalISel: https://godbolt.org/z/MqzdG1r4v
DeltaFile
+46-0llvm/test/CodeGen/RISCV/GlobalISel/half-imm.ll
+1-1llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+47-12 files

LLVM/project fc7cdf2 — llvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel half-convert.ll

[RISCV][GlobalISel] Use Zfhmin for G_FPEXT from f16 to f64 (#230721)

From SPEC: If the D extension is present, the fcvt.d.h and fcvt.h.d
instructions are also included.

Link:
https://github.com/riscv/riscv-isa-manual/blob/1b9ca13819259df4b3bc87a7d7dcda06dd2fb6a9/src/unpriv/zfhmin.adoc?plain=1#L14-L17

Follow up of https://github.com/llvm/llvm-project/pull/227225
DeltaFile
+42-0llvm/test/CodeGen/RISCV/GlobalISel/half-convert.ll
+2-1llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+44-12 files