Add spirv-val compilation step when targeting SPIR-V (#188150)
Clang-dxc.exe currently uses dxv by default after compiling HLSL that
targets DXIL, assuming dxv can be found. However, there is no
counterpart for SPIR-V. This PR changes clang-dxc.exe so that the DXC
driver inserts a step to run spirv-val when SPIR-V is the target. It
also accounts for whether or not the -Fo option is passed. In all cases,
spirv-val will be run, as long as the target is SPIR-V and the spirv-val
executable can be found on the PATH.
This PR also adds a new option --spirv-val-path, a counterpart to
--dxv-path, for specifying an explicit path to spirv-val.
Key differences from dxv: Unlike dxv, which validates and signs DXIL
containers and produces an output file, spirv-val is a pure validator —
it checks the SPIR-V binary and exits with a status code without
producing output. Because of this, the compile step writes directly to
-Fo and spirv-val validates the file in-place.
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Reapply "[VPlan] Handle calls in VPInstruction:opcodeMayReadOrWriteFromMemory." (#191886)
This reverts commit
https://github.com/llvm/llvm-project/commit/3bf9639ec04544902670ab4199401ac470c1fcca.
The reapply adds trivial support for ExtractValue and InsertValue to fix
the crash causing the revert.
Original message:
Retrieve the called function and check its memory attributes, to
determine if a VPInstruction calling a function reads or writes memory.
Use it to strengthen assert in areAllLoadsDereferenceable.
PR: https://github.com/llvm/llvm-project/pull/190681
[AMDGPU] Add object linking support for LDS and named barrier lowering in the middle end
This is the first patch in a series introducing object linking support for
AMDGPU.
This PR adds the -amdgpu-enable-object-linking flag to enable object linking in
the backend. It also updates the AMDGPULowerModuleLDSPass and
AMDGPULowerExecSync passes to support lowering LDS and named barrier globals
when object linking is enabled.
[NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates
Inverted predicates can be used freely in PTX. If we can invert a
predicate and CSE the generating instruction we can save calculating
the inverse.
Teach the NVPTX commuteInstructionImpl that SETP instructions can be
inverted to allow CSEing with previous SETP that match the inverted
form. This also inverts the branch users of the predicate to maintain
correctness.
Currently only allow the SETP inversion if all users are branches.
Future work can extend this to sel and not instructions.
Made-with: Cursor
[NVPTX] Add reverseBranchCondition and CBranchOther
Add CBranchOther instruction for inverted predicate branches (@!p bra)
and implement reverseBranchCondition to support branch condition
inversion. Update analyzeBranch, insertBranch, and removeBranch to
handle both CBranch and CBranchOther.
This enables passes like branch folding to properly reverse branch
conditions, and is a prerequisite for SETP predicate inversion CSE.
Made-with: Cursor
[mlir][SPIR-V] Add support for SPV_INTEL_masked_gather_scatter extension (#189099)
Add MaskedGather/MaskedScatter ops and VectorOfPointerType for
SPV_INTEL_masked_gather_scatter extension implemented in #185418
[MLIR][XeGPU] Adding Layout Utility inferMaskOffsetLayoutForScatterIO (#191573)
This PR add a new layout utility function, named
inferMaskOffsetLayoutForScatterIO(), to support the propagation and
lowering of XeGPU scatter IO operations.
[[CIR]] Implement 'to-union' cast. (#191485)
This ends up being pretty trivial/can only really happen in 2 ways, the
only useful way is via an extension. This patch implements this.
This doesn't really affect anything as it is a pretty rarely used
feature and thus doesn't appear in the test suite I've seen, but I saw
it while investigating something else.
[X86][regcall] Rework struct classification for non-Windows x86-64 targets (#187134)
Currently, when `X86_64ABIInfo::classifyRegCallStructTypeImpl`
classifies a struct argument or return value as direct, it leaves the
LLVM IR coerce type unspecified, implicitly relying on
`CodeGenTypes::ConvertType` to eventually construct a default IR type
based on the struct's layout. This conversion is neither stable nor
guaranteed to adhere to the ABI's classification rules.
Instead, rewrite `classifyRegCallStructTypeImpl` to construct an
explicit sequence of coerce types, using the existing field
classification to obtain a coerce type for each member of the struct.
Also, rename the function to `passRegCallStructTypeDirectly` and return
a boolean instead, so that now `classifyRegCallStructType` is the only
place that computes `ABIArgInfo`.
This rewrite also fixes several other issues with the `X86_64ABIInfo`
implementation of `__regcall`:
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[NFC] Try to unbreak the module builds due to missing `StringRef.h` include in `UniqueBBID.h` (#191877)
The modules build of LLVM broke when this patch landed
```
commit 2f422a52fde267757ce48041af6e731421fed2a3
Author: Rahman Lavaee <rahmanl at google.com>
Date: Fri Apr 10 15:58:16 2026 -0700
[Codegen, X86] Add prefetch insertion based on Propeller profile (#166324)
```
with an error like:
```
[2026-04-11T10:33:41.699Z] While building module 'LLVM_Utils' imported from /Users/ec2-user/jenkins/workspace/m.org_clang-stage2-Rthinlto_main/llvm-project/llvm/lib/Demangle/Demangle.cpp:13:
[2026-04-11T10:33:41.699Z] In file included from <module-includes>:321:
[2026-04-11T10:33:41.699Z] /Users/ec2-user/jenkins/workspace/m.org_clang-stage2-Rthinlto_main/llvm-project/llvm/include/llvm/Support/UniqueBBID.h:40:3: error: missing '#include "llvm/ADT/StringRef.h"'; 'StringRef' must be declared before it is used
[2026-04-11T10:33:41.699Z] 40 | StringRef TargetFunction;
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[SLP][NFC] Add tests for runtime strided loads during revectorization (#191875)
Depending on the case, SLP either misses optimizing re-vectorized runtime
strided loads (and use a gather instead) or produces the incorrect
strided load.
[ORC] Add UUID support to MachOPlatform::HeaderOptions. (#191873)
MachOPlatform::HeaderOptions now includes an optional UUID field. If
set, this will be used to build an LC_UUID load command for the
JITDylib's MachO header.
No testcase: MachOPlatform construction requires the ORC runtime, which
we can't require in LLVM regression or unit tests. In the future we
should test this through the ORC runtime.
[lldb] Fix tests on Linux on Arm (32-bit) after #181071 (#191861)
PR #181071 caused regressions on Linux on Arm. These are being tracked
in:
- #191855
- #191859
This PR disables the failing tests for now, to fix the broken buildbot.
[CIR][NFC] Add LLVM and OGCG checks to six codegen tests (#191536)
Add CIR-to-LLVM and classic codegen RUN lines to empty.cpp,
c89-implicit-int.c, expressions.cpp, binop.c, forward-enum.c, and
static-vars.c so each test verifies LLVM IR output from both pipelines.
Made with [Cursor](https://cursor.com)
[CIR] Exclude _BitInt from fundamental integer type constraints (#191493)
Follow-up to #188113 per @erichkeane's feedback: `isFundamentalIntType`
and `isFundamental()` should not disagree.
The previous patch added `!isBitInt()` only inside
`IntType::isFundamental()`, leaving the underlying TableGen predicates
(`CIR_AnyFundamentalIntType` etc.) unaware of `_BitInt`. That meant
`isSignedFundamental()` and `isUnsignedFundamental()` were silently
wrong — a `_BitInt(32)` would pass them.
This patch adds a `CIR_IsNotBitIntPred` to the three fundamental-int
constraint defs so everything stays consistent. `isFundamental()` now
just forwards to `isFundamentalIntType()` with no extra logic.
Includes an `invalid-bitint.cir` test that checks a `_BitInt(32)` is
rejected where a fundamental unsigned int is required.
Made with [Cursor](https://cursor.com)
