LLVM/project ee08b1cllvm/test/CodeGen/AMDGPU/GlobalISel llvm.memcpy.inline.ll regbankselect-amdgcn.struct.ptr.buffer.load.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (53) (#209779)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
+12-1287 files not shown
+109-10993 files

LLVM/project d0231d2llvm/test/Transforms/LoopVectorize/X86/CostModel strided-load-i8.ll strided-load-i16.ll

[LV] Fix LoopVectorize/X86/CostModel tests when regenerated with UTC. NFC (#209802)

Some of the cost model tests were passing, but their UTC arguments
were outdated and CHECK lines disappeared when regenerating them.

- Add additional --filter lines for VPlan cost model CHECK lines,
  which were manually written previously
- Update the --filter argument for the updated INTERLEAVE-GROUP print
  output
- Regenerate strided-load-*.ll tests with UTC
- Pass -vplan-print-metadata=false for tests that were using
  hand-written regexes in CHECK lines
DeltaFile
+37-32llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
+33-28llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
+30-30llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll
+30-30llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll
+30-30llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
+27-27llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll
+187-177105 files not shown
+549-530111 files

LLVM/project 4596278llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses BUILD.gn, llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis BUILD.gn

[gn build] Port ef118b5b3a61 (#209800)
DeltaFile
+1-0llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
+1-0llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
+2-02 files

LLVM/project ff58fb1llvm/test/CodeGen/AMDGPU trap.ll verify-sop.mir

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (52) (#209778)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+18-18llvm/test/CodeGen/AMDGPU/trap.ll
+2-2llvm/test/CodeGen/AMDGPU/verify-sop.mir
+2-2llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
+2-2llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
+2-2llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
+2-2llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
+28-2840 files not shown
+75-7546 files

LLVM/project bfc2d55llvm/test/CodeGen/AMDGPU llvm.amdgcn.unreachable.ll set-wave-priority.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (51) (#209777)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
+4-4llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
+3-3llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+2-2llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
+2-2llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
+17-1794 files not shown
+132-132100 files

LLVM/project 21db8e9llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly BUILD.gn

[gn build] Port 9a4deccf90ae (#209799)
DeltaFile
+3-0llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
+3-01 files

LLVM/project 0429183llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly BUILD.gn

[gn build] Port 2375505c7c19 (#209797)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
+1-01 files

LLVM/project 5699900clang/test/AST/ByteCode virtual-bases.cpp

[clang][bytecode] Fix virtual-bases.cpp on 32 bit hosts (#209766)

It currently fails on clang-armv8-quick with:
```console
# | error: diagnostics with 'error' severity seen but not expected: 
# |   File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 441: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.c) ? ((char *)&c.c) : ((char *)&c.c)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 12'
# |   File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 442: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.b) ? ((char *)&c.b) : ((char *)&c.b)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 8'
# |   File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 443: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.a) ? ((char *)&c.a) : ((char *)&c.a)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 20'
# |   File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 444: static assertion failed due to requirement '((__builtin_constant_p((char *)&c.x) ? ((char *)&c.x) : ((char *)&c.x)) - (__builtin_constant_p((char *)&c) ? ((char *)&c) : ((char *)&c))) == 16'
# | error: diagnostics with 'note' severity seen but not expected: 
# |   File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 441: expression evaluates to '8 == 12'
# |   File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 442: expression evaluates to '4 == 8'
# |   File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 443: expression evaluates to '16 == 20'
# |   File /home/tcwg-buildbot/worker/clang-armv8-quick/llvm/clang/test/AST/ByteCode/virtual-bases.cpp Line 444: expression evaluates to '12 == 16'
# | 8 errors generated.
```
DeltaFile
+7-0clang/test/AST/ByteCode/virtual-bases.cpp
+7-01 files

LLVM/project 7d638b4llvm/test/CodeGen/AMDGPU debug_frame.ll fadd-fma-fmul-combine.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (50) (#209776)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on
llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 ->
-mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu
following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/debug_frame.ll
+4-4llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
+4-4llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
+3-3llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
+3-3llvm/test/CodeGen/AMDGPU/allow-check.ll
+3-3llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll
+21-2193 files not shown
+136-13699 files

LLVM/project 6352d84llvm/test/CodeGen/AMDGPU/GlobalISel xor.ll xnor.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (49) (#209757)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
+5-5llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
+24-245 files not shown
+34-3411 files

LLVM/project ea9175fllvm/include/llvm/Transforms/Vectorize SLPVectorizer.h, llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Revert "[SLP] Support memory runtime alias checks"

This reverts commit 96a53b1c5356754b4708c0fee8517fd0d69cb1fd to fix
buildbots https://lab.llvm.org/buildbot/#/builders/223/builds/7209
reported in https://github.com/llvm/llvm-project/pull/209305?email_source=notifications&email_token=ABI45DXMMB4TIQHXXWA6NYD5E57EVA5CNFSNUABFM5UWIORPF5TWS5BNNB2WEL2JONZXKZKDN5WW2ZLOOQXTIOJYGA4TIMZVGU3KM4TFMFZW63VMON2GC5DFL5RWQYLOM5S2KZLWMVXHJLDGN5XXIZLSL5RWY2LDNM#issuecomment-4980943556

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/209793
DeltaFile
+17-824llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+0-315llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
+10-41llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
+0-13llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
+27-1,1934 files

LLVM/project 930327eclang/test/OpenMP teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-llvm.amdgcn.image.sample.a16.ll legalize-store-global.mir

Rebase

Created using spr 1.3.7
DeltaFile
+23,904-12llvm/test/CodeGen/RISCV/clmul.ll
+6,603-5,923llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+12,190-0clang/test/OpenMP/teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+12,098-0clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+4,734-4,734llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+4,076-4,028llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+63,605-14,6978,214 files not shown
+363,898-245,1558,220 files

LLVM/project 4279d52llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp, llvm/test/CodeGen/AMDGPU vgpr-setreg-pred-block.mir

[AMDGPU][CodeGen] Place `S_NOP` after `S_SETREG_IMM32_B32` in predecessor MBB (#209620)

When placing a `S_SET_VGPR_MSB` at the beginning of a block, check
whether there exists a `S_SETREG_IMM32_B32(MODE)` in the predecessor
block that falls-through into it; if there is one a `S_NOP` has to be
inserted in between them.
DeltaFile
+165-0llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
+30-11llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+195-112 files

LLVM/project 2cd090acompiler-rt/cmake base-config-ix.cmake builtin-config-ix.cmake, compiler-rt/cmake/Modules CompilerRTUtils.cmake AllSupportedArchDefs.cmake

[compiler-rt] Fix amdgcn -> amdgpu conversion for compiler-rt (#209765)

Summary:
We are apparently transitioning to using `amdgpu` everywhere, so these
need to be updated.
DeltaFile
+1-1compiler-rt/cmake/Modules/CompilerRTUtils.cmake
+1-1compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+1-1compiler-rt/cmake/base-config-ix.cmake
+1-1compiler-rt/cmake/builtin-config-ix.cmake
+1-0compiler-rt/lib/builtins/CMakeLists.txt
+5-45 files

LLVM/project 4b415b1clang/lib/Driver ToolChain.cpp, clang/test/Driver amdgpu-toolchain.c

[Clang][AMDGPU] Search both amdgcn and amdgpu libraries (#209770)

Summary:
Temporary workaround as we transition triples from amdgcn to amdgpu.
DeltaFile
+8-0clang/lib/Driver/ToolChain.cpp
+6-0clang/test/Driver/amdgpu-toolchain.c
+0-0clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/amdgpu-amd-amdhsa/libclang_rt.profile.a
+14-03 files

LLVM/project 6526c5bllvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU udivrem24.ll div-rem-fast-path.ll

[AMDGPU] Avoid errors with 24-bit div/rem (#209711)

Avoid errors when using floating-point reciprocal to calculate Y/X when
Y = (0x7FFFFF/X)*X-1. Limit expansion to 23-bit signed and 22-bit
unsigned to avoid this issue.

This change is analogous to the change done in
https://github.com/llvm/llvm-project/pull/202753, but in
AMDGPUISelLowering.cpp.

Signed-off-by: John Lu <John.Lu at amd.com>
DeltaFile
+138-121llvm/test/CodeGen/AMDGPU/udivrem24.ll
+114-76llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
+44-38llvm/test/CodeGen/AMDGPU/udiv.ll
+33-23llvm/test/CodeGen/AMDGPU/sdiv.ll
+15-11llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+8-12llvm/test/CodeGen/AMDGPU/sdivrem24.ll
+352-2813 files not shown
+369-2989 files

LLVM/project 78c8cf7utils/bazel/llvm-project-overlay/lldb/source/Plugins BUILD.bazel

[lldb][bazel] Add ObjectFileXCOFF plugin library to the Bazel overlay (#209747)

Adds the PluginObjectFileXCOFF cc_library to the lldb Bazel overlay,
modeled on PluginObjectFileELF/PluginObjectFileCOFF and mirroring
source/Plugins/ObjectFile/XCOFF/CMakeLists.txt (lldbCore, lldbHost,
lldbSymbol, lldbTarget; llvm BinaryFormat/Object/Support). The library
is intentionally left out of DEFAULT_PLUGINS.

bazel rule assisted with: claude

Can confirm this library will convert to BUCK internally at Meta and
build with buck2 where we do have in the default plugin list. I left it
out here, unless there's a desire to add it in.
DeltaFile
+19-0utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
+19-01 files

LLVM/project 35182ecutils/bazel/llvm-project-overlay/lldb/source/Plugins BUILD.bazel

[lldb][bazel] Add PlatformWasm plugin library to the Bazel overlay (#209749)

Adds the PluginPlatformWasm cc_library plus its PlatformWasmProperties
gentbl_cc_library (settings .td, modeled on PlatformQemuUserProperties)
to the lldb Bazel overlay. Deps mirror
source/Plugins/Platform/WebAssembly/CMakeLists.txt (lldbCore, lldbHost,
lldbTarget, lldbUtility, Support) plus the :PluginPlatformGDB and
:PluginProcessWasm plugin deps its GDB-remote/Web-Inspector sources use.
The library is intentionally left out of DEFAULT_PLUGINS.

bazel rule assisted with: claude

Can confirm this library will convert to BUCK internally at Meta and
build with buck2 where we do have in the default plugin list. I left it
out here, unless there's a desire to add it in.
DeltaFile
+32-0utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
+32-01 files

LLVM/project 15a2007clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn.hip builtins-amdgcn-gfx1250.hip

[CIR][AMDGPU] Add support for AMDGCN sqrt builtins (#197342)

Adds codegen for the following AMDGCN square root builtins:

- __builtin_amdgcn_sqrt (double)
- __builtin_amdgcn_sqrtf (float)
- __builtin_amdgcn_sqrth (half)
- __builtin_amdgcn_sqrt_bf16 (bfloat16)

These are lowered to the corresponding `llvm.amdgcn.sqrt` intrinsic calls.
DeltaFile
+16-0clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+8-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
+8-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
+1-4clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+33-44 files

LLVM/project 1725c53mlir/include/mlir/Dialect/OpenACC OpenACCCGAttributes.td OpenACCUtilsCG.h, mlir/lib/Dialect/OpenACC/Transforms ACCCGToGPU.cpp

[mlir][acc] Add attribute for redundant execution marking (#209784)

Adds `acc.gpu_block_redundant` attribute for correct gang-redundant
lowering.

OpenACC gang-redundant regions execute on every gang rather than
partitioning work across gangs. When lowering to the GPU dialect, such
regions must not be assigned block-level par dims; only thread-level
parallelism applies. This marks loops with this attribute to ensure
proper execution and to avoid incorrect predication.

Co-authored-by: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
DeltaFile
+38-0mlir/test/Dialect/OpenACC/acc-cg-to-gpu-block-redundant.mlir
+11-0mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
+10-0mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
+7-2mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+9-0mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
+75-25 files

LLVM/project 649466amlir/include/mlir/Dialect/OpenACC OpenACCCGOps.td

[NFC][OpenACC] fix doc formatting for reduction ops (#209739)

Was not printing correctly due to the matching `$`
DeltaFile
+7-7mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
+7-71 files

LLVM/project 39ff4dallvm/test/CodeGen/AMDGPU trap.ll verify-sop.mir

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (52)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+18-18llvm/test/CodeGen/AMDGPU/trap.ll
+2-2llvm/test/CodeGen/AMDGPU/verify-sop.mir
+2-2llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
+2-2llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
+2-2llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
+2-2llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
+28-2840 files not shown
+75-7546 files

LLVM/project 87cbc79llvm/test/Transforms/AtomicExpand/AMDGPU expand-atomic-f32-agent.ll expand-atomic-f32-system.ll

AMDGPU: Migrate tests with regenerated checks to amdgpu subarch triple (54)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on autogenerated tests where the folded triple changes output relative to the previous default subtarget (e.g. cost-model BASE lines, scheduling). CHECK lines were regenerated with the update_*_test_checks.py scripts.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+803-803llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
+284-284llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
+244-244llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
+202-202llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
+194-194llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
+149-141llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-flat-noalias-addrspace.ll
+1,876-1,86865 files not shown
+3,799-3,82071 files

LLVM/project 8519b92llvm/test/CodeGen/AMDGPU/GlobalISel udiv.i32.ll udiv.i64.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (53)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
+12-1287 files not shown
+109-10993 files

LLVM/project 3e7de3fllvm/test/CodeGen/AMDGPU set-wave-priority.ll llvm.amdgcn.unreachable.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (51)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
+3-3llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
+2-2llvm/test/CodeGen/AMDGPU/lds-size.ll
+2-2llvm/test/CodeGen/AMDGPU/liveness.mir
+17-1794 files not shown
+132-132100 files

LLVM/project 7eccd5dllvm/test/CodeGen/AMDGPU fadd-fma-fmul-combine.ll debug_frame.ll

AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (50)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on llc/opt RUN lines (e.g. -mtriple=amdgcn -mcpu=gfx600 -> -mtriple=amdgpu6.00), now that these tests carry an explicit -mcpu following the default-subtarget pinning. Codegen output is unchanged.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
+4-4llvm/test/CodeGen/AMDGPU/debug_frame.ll
+4-4llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
+3-3llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
+3-3llvm/test/CodeGen/AMDGPU/allow-check.ll
+3-3llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll
+21-2193 files not shown
+136-13699 files

LLVM/project 8c08803llvm/test/CodeGen/AMDGPU/GlobalISel xor.ll xnor.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (49)

Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
+5-5llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
+24-245 files not shown
+34-3411 files

LLVM/project c78147allvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll shl-ext-reduce.ll

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (48) (#209756)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
+36-3695 files not shown
+229-229101 files

LLVM/project f1cb3d3llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-copy.mir regbankselect-icmp.mir

AMDGPU: Migrate GlobalISel CodeGen tests to amdgpu subarch triple (47) (#209755)

Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
+19-1994 files not shown
+124-124100 files

LLVM/project 703e9b3llvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[Flang][OpenMP] Implement DEPEND clause for TASKWAIT directive (#193568)

Implements support for the `DEPEND` clause on `TASKWAIT`, added in
OpenMP 5.0.
DeltaFile
+63-19llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+53-0mlir/test/Target/LLVMIR/openmp-taskwait-depend.mlir
+13-5mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+8-6llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+9-4mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+0-11mlir/test/Target/LLVMIR/openmp-todo.mlir
+146-453 files not shown
+158-579 files