BSD Commit Log Search

[clang][CodeGen] Construct function type for callgraph from function definition (#212863)

When -fexperimental-call-graph-section is enabled, for unprototyped
function
definitions (such as C89 parameterless declarations or K&R definitions)
reconstruct their prototype from the parameter declarations in the
definition AST (applying default argument promotions to parameters).

Assisted by: Gemini

[llvm][AArch64] Fix FPDiff founding direction in non-sibcall tail calls (#223545)

This fixes another subtle bug in frame accounting (see: #217156 /
#220406), for tail calls that have a non-multiple of 16 bytes worth of
stack arg area, and need that stack arg re-use to be increased to cover
the alignment requirement. This is best illustrated with callers
containing 8 formal arguments covering the first 8 GPRs (x0-x7),
followed by 9 bytes of argument passed on the stack.

In a callee-pops tail call (e.g. tailcc/swifttailcc), the set of
reusable stack arg area bytes has already been sufficiently aligned by
LowerFormalArguments, so growing NumBytes up to StackAlign is enough to
consume that excess. Otherwise (e.g. a plain C-convention call, forced
off the sibcall path, as in the aarch64_inout_za tests), we can't rely
on either having been pre-aligned, so we round NumBytes up to the same
residue mod StackAlign as NumReusableBytes, which cancels the residue
out of their difference (FPDiff), thus keeping the stack aligned going
into the callee.


    [9 lines not shown]

Merge upstream/main into cir-callconv-vaarg-x86-64

FunctionInfo.h conflicted.  Main added the CanBeFlattened bit exactly where
this branch added NeededIntRegs and NeededSseRegs, and both extended the same
ArgInfo constructor.  All three fields are kept, the bools grouped ahead of
the two 3-bit fields, with the initializer in declaration order.

Assisted-by: Cursor / claude-opus-5

clang: Require x86 to be built for PR44896.ll test

[flang][cuda] Limit mem:managed generic matching to allocatable and pointer (#223801)

managed memory mode only puts allocatable and pointer allocations in
managed memory. Static and automatic host objects stay host-resident, so
they must not match a device/managed/unified dummy during generic
resolution.

Keep the -gpu=mem:unified relaxation for all host variables, which are
device-accessible in that mode.

This stops host calls such as sum(host_array(:)) from resolving to a
CUDA Fortran device-dummy specific.

[LV] Add tests for branch weights of branches and selects (NFC). (#224061)

Add for missing branch weights on branches and selects created by LV:
 * Skeleton branches
 * early exit branches
 * various selects.

[lldb] Add an option to build liblldb statically (#223210)

This builds on the Emscripten host and platform work from the previous
patches.

`liblldb` is currently always created as a shared library. That makes
sense for the normal LLDB installation, but it is restrictive for
embedders where dynamic libraries are unavailable, expensive to load or
simply not the preferred deployment model.

My immediate use case is bringing LLDB into
[WasmBolt](https://github.com/anutosh491/WasmBolt) (try
[here](https://anutosh21.github.io/WasmBolt/)). Loading the complete
`liblldb` WebAssembly side module dynamically has significant startup
overhead. A static build lets the browser application link the required
LLDB components and plugins into its main module during CI, after which
startup is much faster and the linker can remove unreachable code.

The use case is not specific to Emscripten, so this patch adds the

    [22 lines not shown]

Merge branch 'main' into users/adams381/cir-callconv-argmem-memory-effects

[mlir] Migrate AMDGPU/ROCDL to targets, not chipset versions

**migration tl;dr:** Replace usages of `amdgpu::Chipset` with `ROCDL::TargetInfo`, ideally move from `chipset=` to `arch=`. If you don't use upstream pipelines, call 'TargetInfo::migrateArchFeaturesToModuleFlags` at the appropriate location.

Further note: if you've got a build pipeline that's getting a `gfxXXX` name from something like `rocm_agent_enumerator`, using a full triple name like the ones you get from `rocminfo` is preferred.

`amdgpu::Chipset` was an awkward hack that was hard to keep up to date
with changes in the compiler/new architectures, and didn't properly
support generic targets (and has been strongly disfavored by the
compiler team).

This PR replaces `amdgpu::Chipset` with `ROCDL::TargetInfo`, a
structure that uses LLVM's TargetParser and the underlying LLVM
features tables to get the real nature of the target being compiled
for.

This also helps MLIR move to
new-style (`-mtriple=amdgpuX.YZ-amd-amdhsa`) over "old
style" (`-mtriple=amdgcn-amd-amdhsa -mcpu=gfxXYZ`) triples.

    [36 lines not shown]

[mlir][ROCDL] Add TargetInfo to replace Chipset, allow features queries

Add a now ROCDL::TargetInfo struct that parses AMDGPU triples and
target names using the same logic that Clang and LLVM
use (TargetParser) and maintains the set of features available on a
given GPU.

This is an improvement over the old `amdgpu::Chipset` struct since
that was just a version number and often became stale compared to the
knowledge exposed by LLVM, such as gfx1170 having OCP FP8 support even
though other gfx11 chips don't have it.

This struct also allows for moving to new-style
triples (amdgpu9.42-amd-amdhsa vs amdgcn-amd-amdhsa--gfx942, for
example), which is an ongoing migration in other parts of the compiler
that this PR lets us follow.

It also enables compiling for generic targets, like `gfx11-generic`,
which can be run on all chips in a generation.

    [15 lines not shown]

Reland "[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors" (#221058)

This relands #217055

The original commit revealed a latent issue in eliminateFrameIndex in
SIRegisterInfo where SCC can be clobbered before reading it on
gfx900/gfx90a. This change itself has no known issues.

[AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering

When SCC is live into a scalar frame index user, the scaling path avoids
SALU ops that write SCC by computing the address in a VGPR and reading it
back with V_READFIRSTLANE_B32. If the destination of that readfirstlane is
scavenged with spilling allowed, an AMDGPU SGPR spill writes inactive
lanes, so it flips EXEC with S_NOT_B64 and clobbers SCC. Instead, scavenge
that register with AllowSpill=false.

[AMDGPU] Only scale the frame register in place for the last frame index

When nothing can be scavenged, eliminateFrameIndex falls back to scaling
FrameReg in place and restoring it after MI. With two frame indices on
one instruction that fallback fires while lowering the first one, and
FrameReg is left scaled for everything that follows: the second frame
index is then scaled a second time from the already-scaled value, and any
emergency spill emitted in between uses it as its scratch offset.

[AMDGPU] Prevent SCC clobber in frame index lowering in scaling path

eliminateFrameIndex has two lowering strategies, but only one has the
proper handling for checking SCC-liveness to prevent clobbering. Unify
them with a helper function to ensure both paths handle the same

[flang][openacc][cuda] Recover acc routine bind info in CUDA Fortran module reads (#223595)

CUDA Fortran device code can call a procedure whose device-side symbol
is given by `acc routine bind(...)` in the module that declares it.
The using translation unit is often compiled with CUDA Fortran enabled
and without an OpenACC target, so the `$acc` sentinel was never
recognized when re-parsing the module file and the bind clause was
dropped.
Enable OpenACC while reading module files under CUDA Fortran as well,
and resolve the recovered directives onto the imported symbols. User
`$acc` in the main source remains ignored without `-fopenacc`; only
directives that already survived into the `.mod` are honored.
A bind(C) host name and an acc bind device name on the same procedure
is the dual-name rule in OpenACC §2.15.1.

CodeGen: Remove PointerLikeRegClass

Remove PointerLikeRegClass and the related getPointerRegClass
TargetRegisterInfo hook. This is obsoleted by RegClassByHwMode.
Previously targets would have to map ptr_rc to an assumed pointer
register class by implementing this method, but this is now auto-resolvable
per instruction using RegClassByHwMode.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

Remove getRegClassByHwMode

CodeGen: Add getInlineAsmMemoryOperandRegClass

Replace the use of getPointerRegClass to determine the register
class from an asm memory constraint, working to delete it. When
there are multiple pointer types there can't be just a single
answer.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

CodeGen: Replace some getPointerRegClass() uses with operand reg classes (#223930)

Try to take the register class from the contexual instruction being
emitted instead. This is a step towards fully replacing PointerLikeRegClass with
RegClassByHwMode.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

Merge branch 'main' into users/adams381/cir-callconv-union-tail-padding

[NFC][IR][GlobalValue] Move externalize helpers to GlobalValue (#223654)

This PR is a revised refactoring of #221181.
To improve generality, it makes the splitting helpers
externalizeGlobal() and nameUnnamedGlobalValue() generic members of
GlobalValue and removes SplitModuleCommon:

- GlobalValue::externalize() promotes a local-linkage global to external
+ hidden and names it if unnamed.
- GlobalValue::nameUnnamed() names unnamed globals __llvm_unnamed.

Co-authored-by: maojiaping <maojiaping1.huawei.com>

[Offload] Minor changes to address build issues (#224047)

This patch includes a few changes to fix customized build process of
offload components with relatively old build compilers. Current LLVM
build does not need this change since it uses just-built clang to build
offload components, but it does not hurt to make the code buildable with
other compilers.

Assisted by Claude Code.

CodeGen: Read the exception model from the module flag in EH lowering (#223970)

Resolve the exception model as the exception-model module flag if
present, otherwise the TargetOptions default.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[flang][OpenMP] Lower iterator modifiers in map and motion clauses

Add iterator lowering for `target data`, `target enter/exit data`,
`target update`, and map clauses inside `declare mapper`.

For example:

```fortran
!$omp target update to(iterator(i=1:n): a(i), b)
```

Conceptually, this becomes:

```text
entries = omp.iterator(i = 1 through n) {
  yield map_info(base = a, bounds = element i)
}
target_update(iterated_maps = entries, ordinary_maps = [b])
```

    [37 lines not shown]

[libc++][ci] Retarget the ARM BuildKite runners (#224107)

I enabled agent clusters in BuildKite since unclustered agents are not
supported anymore. As part of that, I created a new libcxx-builders-arm
queue to replace the existing queue. This patch switches the pipeline
definition so that new jobs start targeting the new queue with clustered
agents.

[ORC] Link LLVMOrcShared against TargetParser

Mangler::fromTriple() calls Triple::computeDataLayout(), which lives in
LLVMTargetParser, but LLVMOrcShared only lists Support as a link
component.

This goes unnoticed in a static build: the component is an archive, so
the reference is not resolved until the final executable link, where
LLVMTargetParser is present anyway. With BUILD_SHARED_LIBS=ON each
component becomes a shared library linked with -Wl,-z,defs, and linking
LLVMOrcShared itself fails:

  ld.lld: error: undefined symbol:
    llvm::Triple::computeDataLayout[abi:cxx11](llvm::StringRef) const
  >>> referenced by Mangler.cpp:50

[RelLookupTableConverter] Allow multiple uses of loaded value (#223853)

RelLookupTableConverter previously required `!Load ||
!Load->hasOneUse()`, which prevented converting lookup tables if the
loaded pointer was used more than once in the function.

This restriction is unnecessary since the loaded value itself can be
used many times. The check was likely an over-zealous carryover from
`GV->hasOneUse()` and `GEP->hasOneUse()`.

Remove the check and add a test verifying that lookup tables with
multiple uses of the loaded pointer are converted.

[flang][OpenMP] Lower iterator modifiers in map and motion clauses

Add iterator lowering for `target data`, `target enter/exit data`,
`target update`, and map clauses inside `declare mapper`.

For example:

```fortran
!$omp target update to(iterator(i=1:n): a(i), b)
```

Conceptually, this becomes:

```text
entries = omp.iterator(i = 1 through n) {
  yield map_info(base = a, bounds = element i)
}
target_update(iterated_maps = entries, ordinary_maps = [b])
```

    [20 lines not shown]

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[AMDGPU][Doc] Add documentation about ABI occupancy

This PR introduces ABI occupancy in documentation. The actual code
implementation will be in follow-up PRs.