LLVM/project adad1a6 — llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] Rename combineVectorShiftVar -> combineVectorShiftUniformVar. NFC. (#237700)

Prep work before adding combines for non-uniform X86ISD::VSHLV/VSRAV/VSRLV nodes
DeltaFile
+5-4llvm/lib/Target/X86/X86ISelLowering.cpp
+5-41 files

LLVM/project 6262936 — llvm/lib/Target/Sparc SparcISelLowering.cpp, llvm/test/CodeGen/SPARC reserved-regs-named.ll

[SPARC] Accept rN register names in getRegisterByName (#237528)

Accept r0-r31 as names for the integer registers in llvm.read_register
and llvm.write_register, matching the %rN syntax of the assembler.

This completes #212838, which was reverted because reading %r31/%i7 in
a leaf procedure produced a use of an undefined physical register once
leaf remapping turned it into %o7. That is fixed by #236654, which adds
live-ins for reserved registers remapped in leaf procedures. The %
prefix
and the sp/fp aliases from #212838 have since been added by #234875.

Also run the test with -verify-machineinstrs, which catches that failure
without an expensive checks build.

Co-authored-by: Kirill A. Korinsky <kirill at korins.ky>
DeltaFile
+32-32llvm/lib/Target/Sparc/SparcISelLowering.cpp
+42-2llvm/test/CodeGen/SPARC/reserved-regs-named.ll
+74-342 files

LLVM/project 5f72fd5 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll amdgcn.bitcast.832bit.ll

Merge branch 'main' into users/void/libclang-dependent-cursor-referenced
DeltaFile
+88,705-91,244llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,383-26,405llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,311-9,381llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,998-9,209llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+8,016-8,194llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+7,335-7,432llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+147,748-151,8655,564 files not shown
+485,231-368,6705,570 files

LLVM/project 11eb8e7 — llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/test/CodeGen/X86 callbr-asm-error.ll

[SelectionDAG] Don't crash after an error in a callbr's asm

When a callbr's asm has an error, such as a constraint it can't satisfy,
visitInlineAsm() reports it and returns before creating the INLINEASM_BR.
But the callbr's block still got edges to the indirect targets, which
BranchFolding rejects since nothing branches there, and a landing pad in
an indirect target looked for the registers that the INLINEASM_BR would
have defined.

Don't add the edges to the indirect targets, and make a landing pad's
value poison, since nothing reaches it.

Fixes #98379 and #172657. Part of #173609, whose asm is still rejected,
since LLVM picks the "k" alternative of "+kr", which needs AVX-512.

Assisted-by: Claude Opus 5.5
DeltaFile
+69-0llvm/test/CodeGen/X86/callbr-asm-error.ll
+11-2llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+80-22 files

LLVM/project 214aeb3 — llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/test/CodeGen/X86 callbr-asm-indirect-output.ll

[SelectionDAG] Report an error for a callbr's indirect register output

An indirect output with a register constraint, e.g. "=*r", is stored to its
pointer after the asm. But a callbr's asm can branch to an indirect target
before then, so the store was silently skipped on the indirect paths. Clang
emits such an output for a _Complex lvalue with a register constraint:

  _Complex float c;
  asm goto("" : "=r"(c) : : : l);

Report an error instead. A callbr without indirect targets has no such
path, so it's still allowed.

Assisted-by: Claude Opus 5.5
DeltaFile
+47-0llvm/test/CodeGen/X86/callbr-asm-indirect-output.ll
+8-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+55-02 files

LLVM/project 8a301d8 — llvm/include/llvm/CodeGen FunctionLoweringInfo.h, llvm/lib/CodeGen/SelectionDAG FunctionLoweringInfo.cpp SelectionDAGBuilder.h

Replay each output's read in the indirect targets

The indirect targets re-parsed the constraints, recomputed each output's
registers and types, and paired them with the recorded registers in order,
so they were right only if both computations agreed. Record each output's
operand info and registers when lowering the callbr instead, and read them
in the indirect targets with the same code as visitInlineAsm().

This also marks a flag output's register (NZCV on AArch64, CC on SystemZ)
live into the indirect targets, as a register output's already was. And the
indirect targets no longer create virtual registers they don't use, which
renumbers some in the AArch64 test.

Assisted-by: Claude Opus 5.5
DeltaFile
+65-93llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+14-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+0-7llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
+3-3llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
+0-1llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+82-1045 files

LLVM/project 6ab65c1 — llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/test/CodeGen/X86 callbr-asm-error.ll

Move the asm error handling to its own PR

This PR now fixes only valid asm whose outputs crash the indirect targets.
Lowering a callbr whose asm has an error, which crashes after reporting
it, moves to its own PR stacked on this one.

Assisted-by: Claude Opus 5.5
DeltaFile
+0-37llvm/test/CodeGen/X86/callbr-asm-error.ll
+2-17llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+2-542 files

LLVM/project 3258808 — llvm/include/llvm/CodeGen FunctionLoweringInfo.h, llvm/lib/CodeGen/SelectionDAG FunctionLoweringInfo.cpp SelectionDAGBuilder.cpp

[SelectionDAG] Read callbr outputs from the INLINEASM_BR's registers

An indirect target of a callbr found the registers holding the asm's
outputs by walking back from the callbr's exported value through COPYs to
the INLINEASM_BR, and asserted that the chain held nothing else ("start of
copy chain MUST be COPY"). An output whose type differs from its register's,
such as a float in a general-purpose register, is converted, e.g. with
MOVDI2SSrr on x86, so the assertion fired. And the target didn't convert the
output to its result type, as visitInlineAsm() does.

After an error in the asm, nothing defines the exported value, so the walk
crashed, and the callbr block kept edges to the indirect targets with no
INLINEASM_BR to branch there, which later passes reject.

Record the registers that the INLINEASM_BR defines its outputs in when
lowering the callbr, and read the outputs from them in the indirect target,
converting each to its result type as visitInlineAsm() does. After an error,
give the indirect targets undefined outputs and no edges from the callbr.

Fixes #98379, #112914, #143795, #170100, #172657, and #173609.
DeltaFile
+122-110llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+76-0llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll
+37-0llvm/test/CodeGen/X86/callbr-asm-error.ll
+7-0llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
+1-0llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+243-1105 files

LLVM/project 3834fa6 — llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp

Remove the stale FollowCopyChain comment and unrelated comment changes

The comment that explained FollowCopyChain's walk was left above
visitCallBrLandingPad() when the walk was removed. Also put the BTI comment
in visitCallBr() back as it was, and fix a double space.

Assisted-by: Claude Opus 5.5
DeltaFile
+6-29llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+6-291 files

LLVM/project f80f324 — llvm/test/CodeGen/AArch64 callbr-asm-outputs-indirect-isel.ll, llvm/test/CodeGen/RISCV callbr-asm-outputs.ll

Test more outputs that the indirect targets convert

Add the RISC-V shape of #143795, where an i32 output is sign-extended on
each path, a float in a specific physical register on x86, a double in a
pair of registers on i686, and a flag output on AArch64, whose NZCV is now
live into the indirect target. Also check that a callbr with direct and
indirect register outputs now only reports the error.

Assisted-by: Claude Opus 5.5
DeltaFile
+87-0llvm/test/CodeGen/RISCV/callbr-asm-outputs.ll
+39-0llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll
+39-0llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel-m32.ll
+36-0llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
+13-0llvm/test/CodeGen/X86/callbr-asm-indirect-output.ll
+214-05 files

LLVM/project aaa5ddc — llvm/lib/CodeGen MachineCSE.cpp, llvm/test/CodeGen/X86 machine-cse-inlineasm-br.mir

[MachineCSE] Don't reuse an instruction after an INLINEASM_BR elsewhere

An INLINEASM_BR can branch to its indirect targets before the instructions
after it in its block run, but MachineCSE let those instructions replace
ones in any block that their block dominates, including the indirect
targets. E.g., when both paths out of a callbr sign-extend its output, the
indirect target reused the extension on the path to the default target and
read a register that its own path never wrote.

Reuse an instruction after an INLINEASM_BR only in its own block. MachineSink
already refuses to sink into an indirect target for the same reason.

Assisted-by: Claude Opus 5.5
DeltaFile
+83-0llvm/test/CodeGen/X86/machine-cse-inlineasm-br.mir
+22-0llvm/lib/CodeGen/MachineCSE.cpp
+105-02 files

LLVM/project 9d02ab7 — llvm/lib/CodeGen InlineAsmPrepare.cpp, llvm/test/CodeGen/AArch64 inline-asm-prepare.ll

[InlineAsmPrepare] Rewrite callbr result uses that indirect dests reach

updateSSA() left a use of a callbr's result alone if the callbr's default
dest dominated it. But an indirect dest can reach the default dest too,
e.g. when they're the same block or when the indirect dest branches to it,
so such a use still read the callbr's result on the indirect path.
SelectionDAG copies that result to a virtual register after the
INLINEASM_BR, on the path to the default dest only, so the indirect path
read a register that it never defined.

Leave a use alone only if the edge to the default dest dominates it, and
don't make the result the value at the end of the default dest, so that
SSAUpdater merges it with the landing pad's value there.

Assisted-by: Claude Opus 5.5
DeltaFile
+65-0llvm/test/CodeGen/AArch64/inline-asm-prepare.ll
+4-3llvm/lib/CodeGen/InlineAsmPrepare.cpp
+69-32 files

LLVM/project 075db14 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll amdgcn.bitcast.832bit.ll

Merge branch 'main' into users/void/interp-strip-mangling-escape
DeltaFile
+88,705-91,244llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,383-26,405llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,311-9,381llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,998-9,209llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+8,016-8,194llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+7,335-7,432llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+147,748-151,8655,564 files not shown
+485,231-368,6705,570 files

LLVM/project 2df3cd1 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll amdgcn.bitcast.832bit.ll

Merge branch 'main' into users/void/arm-gisel-constant-fold-barrier
DeltaFile
+88,705-91,244llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,383-26,405llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,311-9,381llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,998-9,209llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+8,016-8,194llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+7,335-7,432llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+147,748-151,8655,564 files not shown
+485,231-368,6705,570 files

LLVM/project 0587e82 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll amdgcn.bitcast.832bit.ll

Merge branch 'main' into users/void/asm-aggregate-mem-input-main
DeltaFile
+88,705-91,244llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,383-26,405llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,311-9,381llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,998-9,209llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+8,016-8,194llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+7,335-7,432llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+147,748-151,8654,386 files not shown
+404,304-339,7124,392 files

LLVM/project b1bef0b — flang/lib/Lower/Support ReductionProcessor.cpp, libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan pstl.transform_inclusive_scan_bop_uop_init.pass.cpp

Merge branch 'main' into users/void/pbqp-inline-asm-error
DeltaFile
+405-387flang/lib/Lower/Support/ReductionProcessor.cpp
+379-392llvm/lib/Target/Sparc/DelaySlotFiller.cpp
+424-173llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+497-8llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
+335-0llvm/unittests/DWARFLinkerParallel/TypePoolTest.cpp
+323-0libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan/pstl.transform_inclusive_scan_bop_uop_init.pass.cpp
+2,363-960510 files not shown
+16,565-4,151516 files

LLVM/project 3aefd97 — llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp

[SelectionDAG] Use the Func kind for inline asm operands only on x86 (#237504)

The only platform that currently uses the "Func" kind is x86. The other
targets aren't able to handle it. For instance, SystemZ asserts "This is
not a register operand!" and Hexagon hits an llvm_unreachable.

Gate the use of the Func kind behind a new hook
TargetLowering::supportsInlineAsmFuncOperands(), which only x86
overrides.

Assisted-by: Claude Opus 5.5
DeltaFile
+52-0llvm/test/CodeGen/SystemZ/inline-asm-addr.ll
+8-0llvm/include/llvm/CodeGen/TargetLowering.h
+4-0llvm/lib/Target/X86/X86ISelLowering.h
+1-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+65-14 files

LLVM/project 90f8a7b — .github CODEOWNERS

[OpenMP] Add code owners for OpenMP runtime (#236211)
DeltaFile
+3-0.github/CODEOWNERS
+3-01 files

LLVM/project 281f323 — clang/test/utils/update_cc_test_checks opt-pipeline.test, clang/test/utils/update_cc_test_checks/Inputs opt-pipeline.c opt-pipeline.c.expected

[UpdateTestChecks] Fix Windows error when piping outputs (#237636)

On Windows, `update_cc_test_checks` fails to update tests that pipe
outputs since opening an already open `NamedTemporaryFile` errors when
it's set to automatically delete. This PR fixes this by closing the file
after initially writing to it and then manually removing it.
DeltaFile
+8-0clang/test/utils/update_cc_test_checks/Inputs/opt-pipeline.c.expected
+4-2llvm/utils/update_cc_test_checks.py
+4-0clang/test/utils/update_cc_test_checks/opt-pipeline.test
+3-0clang/test/utils/update_cc_test_checks/Inputs/opt-pipeline.c
+19-24 files

LLVM/project 474a958 — llvm/lib/Analysis InstructionSimplify.cpp, llvm/test/Transforms/InstSimplify ptrtoaddr.ll gep.ll

[InstSimplify] Only fold gep of a pointer difference when the division is exact (#237685)

The `ashr` and `sdiv` folds in simplifyGEPInst (`gep V, (ashr (sub P,
V), C) -> P` and its `sdiv` form) are only correct if the divisions are
exact.

Fixes #234269.

Assisted-by: Claude Opus 5.5
DeltaFile
+39-0llvm/test/Transforms/InstSimplify/gep.ll
+12-10llvm/lib/Analysis/InstructionSimplify.cpp
+2-2llvm/test/Transforms/InstSimplify/ptrtoaddr.ll
+53-123 files

LLVM/project 4575c05 — mlir/lib/Dialect/SCF/Transforms LoopSpecialization.cpp, mlir/test/Dialect/SCF for-loop-specialization.mlir

[mlir][scf] fix loop specialization crash when an scf.for result is used (#236046)

the replacement `scf.if` now has the original loop result types, if the
condition is satisfied (i.e bound equal to constant) the then branch
replaces the upper bound of the cloned loop with the constant, else the
original operation with bound is cloned as such.

the yield op is created inside both the branches if there is any
resullt, the original op's result users are redirected to the `scf.if`
results and the original loop is erased.

fixes #235552

assisted by: claude
DeltaFile
+34-0mlir/test/Dialect/SCF/for-loop-specialization.mlir
+13-3mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
+47-32 files

LLVM/project a8f5f38 — clang/lib/CodeGen CGRecordLayoutBuilder.cpp, clang/test/CodeGenCUDA record-layout.cu

[clang][CodeGen] Use globals address space for vptr record members (#235794)
DeltaFile
+17-0clang/test/CodeGenCXX/vtable-pointer-initialization-address-space.cpp
+10-2clang/test/CodeGenCXX/bitfield-access-tail.cpp
+3-5clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
+4-4clang/test/CodeGenCXX/vtable-consteval-address-space.cpp
+2-1clang/test/CodeGenCUDA/record-layout.cu
+36-125 files

LLVM/project f6eae19 — mlir/lib/Target/SPIRV/Serialization SerializeOps.cpp

[mlir][SPIR-V] Clear value and block ID maps after each function (#237171)
DeltaFile
+2-0mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp
+2-01 files

LLVM/project ceed346 — clang/lib/AST/ByteCode Interp.h

[clang][bytecode][NFC] Remove useless IsOpaqueConstantCall function (#237689)

We're already including ExprConstShared.h, which has a copy of this
function, so just use that.
DeltaFile
+1-9clang/lib/AST/ByteCode/Interp.h
+1-91 files

LLVM/project 2b54d70 — llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/AArch64 ignore-signed-zero.ll frem-power2.ll

[SelectionDAG] Rework `nsz` handling (#232762)

Fixes #232307, #232320, and a few other unreported miscompiles.

Since #180906, `nsz` only allows instructions to non-deterministically
flip the sign of _input_ zeros. SelectionDAG (and many other things)
still has code that assumes output zero signs can also be flipped.

My hope is that these changes will make it a bit harder to gloss over
`nsz` without thinking more carefully about it.

The `frem` regressions here are inevitable if we want correctness. If we
want to see the old codegen, we could add `nsz` consumers to the tests.

---------

Assisted-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+142-0llvm/test/CodeGen/X86/frem-power2.ll
+77-10llvm/test/CodeGen/AArch64/frem-power2.ll
+82-0llvm/test/CodeGen/X86/fp-fold.ll
+68-0llvm/test/CodeGen/AArch64/ignore-signed-zero.ll
+62-5llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+59-0llvm/test/CodeGen/RISCV/frem-power2.ll
+490-154 files not shown
+520-3010 files

LLVM/project 701960d — llvm/lib/Target/Sparc Sparc.td SparcSchedule.td

[SPARC][NFC] Move Leon processor scheduling information to its own file (#234160)

The itineraries in SparcSchedule.td must be included before
SparcInstrInfo.td, and that prevents InstRW definitions from being added
to SparcSchedule.td.

Keep the itinerary class definitions in SparcSchedule.td and move the
Leon specific information to SparcSchedLeon.td instead.

Assisted-by: Claude
DeltaFile
+126-0llvm/lib/Target/Sparc/SparcSchedLeon.td
+0-115llvm/lib/Target/Sparc/SparcSchedule.td
+1-0llvm/lib/Target/Sparc/Sparc.td
+127-1153 files

LLVM/project b592673 — llvm/lib/IR RuntimeLibcalls.cpp, llvm/test/Transforms/Util/DeclareRuntimeLibcalls sleef-riscv.ll amdlibm.ll

RuntimeLibcalls: Use element alignment for vector libcall out pointers

The pointer arguments of the vector modf, sincos and sincospi functions
are linear pointers to the scalar element type (e.g. the l4 in
_ZGVnN4vl4l4_sincosf), not pointers to the vector type. Only the element
alignment is guaranteed, so stop declaring them with the ABI alignment
of the vector.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+12-12llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef.ll
+12-12llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sleef-riscv.ll
+6-6llvm/test/Transforms/Util/DeclareRuntimeLibcalls/amdlibm.ll
+1-1llvm/lib/IR/RuntimeLibcalls.cpp
+37-375 files

LLVM/project f4b3c91 — llvm/include/llvm/IR RuntimeLibcalls.td, llvm/test/Transforms/Util/DeclareRuntimeLibcalls sparc.ll systemz.ll

Use unsigned argument types for ctlz/ctpop
DeltaFile
+4-4llvm/test/Transforms/Util/DeclareRuntimeLibcalls/systemz.ll
+4-4llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ppc.ll
+2-2llvm/test/Transforms/Util/DeclareRuntimeLibcalls/sparc.ll
+2-2llvm/include/llvm/IR/RuntimeLibcalls.td
+12-124 files

LLVM/project 038a942 — llvm/test/Transforms/Util/DeclareRuntimeLibcalls arm.ll systemz.ll

RuntimeLibcalls: Add signatures for more runtime functions

Add type missing signatures for assorted functions which were missing
type information.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+474-474llvm/test/Transforms/Util/DeclareRuntimeLibcalls/aarch64.ll
+305-305llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ppc.ll
+279-279llvm/test/Transforms/Util/DeclareRuntimeLibcalls/bsd.ll
+276-276llvm/test/Transforms/Util/DeclareRuntimeLibcalls/windows.ll
+198-198llvm/test/Transforms/Util/DeclareRuntimeLibcalls/systemz.ll
+192-192llvm/test/Transforms/Util/DeclareRuntimeLibcalls/arm.ll
+1,724-1,72411 files not shown
+2,947-2,93317 files

LLVM/project 9fad02d — llvm/include/llvm/IR RuntimeLibcallsImpl.td

RuntimeLibcalls: Describe vector FuncArgTypes by element type and count

Define the vector libcall argument types from an element type and
count. Derive the matching integer and mask vector types from them
instead of spelling each one out.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+18-12llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+18-121 files