LLVM - FreshBSD

LLVM/project 9642bc5 — .github/workflows prune-unused-branches.py

2026-01-13 04:34:11 UTC by Aiden Grossman on ⎇

users/boomanaiden154/github-add-initial-workflow-to-prune-unused-user-branches

feedback

Created using spr 1.3.7

Delta		File
+0	-4	.github/workflows/prune-unused-branches.py
+0	-4	1 files

LLVM/project fb0d7df — llvm/unittests/IR MetadataTest.cpp

2026-01-13 04:14:06 UTC by Snehasish Kumar on ⎇

users/snehasish/01-13-_metadata_profcheck_handle_identical_mdnodes_in_getmergedprofmetadata

Drop the summation unittest since it's already covered by the gvn lit tests

Delta		File
+0	-26	llvm/unittests/IR/MetadataTest.cpp
+0	-26	1 files

LLVM/project fccfd89 — llvm/lib/IR Metadata.cpp

2026-01-13 04:11:53 UTC by Snehasish Kumar on ⎇

users/snehasish/01-13-_metadata_profcheck_handle_identical_mdnodes_in_getmergedprofmetadata

Move the check after merging for calls to simplify the condition

Delta		File
+3	-6	llvm/lib/IR/Metadata.cpp
+3	-6	1 files

LLVM/project 1c88701 — llvm/lib/IR Metadata.cpp, llvm/unittests/IR MetadataTest.cpp

2026-01-13 03:57:34 UTC by Snehasish Kumar on ⎇

users/snehasish/01-13-_metadata_profcheck_handle_identical_mdnodes_in_getmergedprofmetadata

[Metadata][profcheck] Handle identical MDNodes in getMergedProfMetadata

This fixes a bug where !prof metadata was dropped from SelectInsts when GVN simplified/merged them.
Guarded by -profcheck-disable-metadata-fixes. Exposed by the tests in
Transforms/SampleProfile.

Delta		File
+50	-0	llvm/unittests/IR/MetadataTest.cpp
+12	-0	llvm/lib/IR/Metadata.cpp
+62	-0	2 files

LLVM/project e4b8d8a — libcxx/include istream, libcxx/test/libcxx/input.output/iostream.format nodiscard.verify.cpp

2026-01-13 03:55:03 UTC by Hristo Hristov via GitHub on ⎇

main

[libc++][istream] Removed `[[nodiscard]]` from `peek()` (#175591)

Calling `peek()` after constructing a stream is something one can use to
make the stream ignore empty inputs:

```
#include <sstream>

int main() {
  std::istringstream s;
  s.peek();
  while (s && !s.eof()) {
    char c;
    s >> c;
    printf("not eof; read \'%c\' (%d)\n", c, c);
  }
}
```


    [2 lines not shown]

Delta		File
+0	-3	libcxx/test/libcxx/input.output/iostream.format/nodiscard.verify.cpp
+1	-1	libcxx/include/istream
+1	-4	2 files

LLVM/project bd28c6a — llvm/include/llvm/IR DebugInfoFlags.def, llvm/test/Assembler debug-info.ll disubprogram.ll

2026-01-13 03:11:14 UTC by Liu Ke via GitHub on ⎇

main

[DebugInfo] Add a new DI flag to record if the name of a template function/type has been simplified (1/3). (#175130)

This flag is used during debug info generation in the LLVM backend to
guide the selective generation of template parameters in the skeleton
CU. As described in [this
RFC](https://discourse.llvm.org/t/rfc-debuginfo-selectively-generate-template-parameters-in-the-skeleton-cu/89395).

Delta		File
+5	-2	llvm/test/Assembler/debug-info.ll
+5	-2	llvm/test/Assembler/disubprogram.ll
+2	-1	llvm/include/llvm/IR/DebugInfoFlags.def
+12	-5	3 files

LLVM/project bb008e7 — llvm/utils git-llvm-push

2026-01-13 03:06:38 UTC by Petr Hosek via GitHub on ⎇

main

[llvm][utils] Make git-llvm-push set the skip-precommit-approval label (#174833)

skip-precommit-approval label is intended for simple PR that don't
require approval. To reduce the volume of notifications, label all PRs
created using the git-llvm-push script with the skip-precommit-approval
label.

Fixes #174825

Delta		File
+33	-0	llvm/utils/git-llvm-push
+33	-0	1 files

LLVM/project 9e16060 — llvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/Target/RISCV RISCVFrameLowering.cpp

2026-01-13 02:51:58 UTC by Christudasan Devadasan via GitHub on ⎇

main

[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subreg-reload (#175581)

This preparatory patch introduces an additional argument to the target hook
loadRegFromStackSlot. Ths is essential for targets to handle subregister-specific
reload in the future. See how this is used for AMDGPU target with PR #175002.

Delta		File
+9	-6	llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+6	-3	llvm/include/llvm/CodeGen/TargetInstrInfo.h
+2	-3	llvm/lib/Target/X86/X86InstrInfo.h
+2	-3	llvm/lib/Target/XCore/XCoreInstrInfo.h
+1	-2	llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+1	-2	llvm/lib/Target/VE/VEInstrInfo.h
+21	-19	42 files not shown
+63	-53	48 files

LLVM/project b21228b — llvm/lib/IR Metadata.cpp, llvm/unittests/IR MetadataTest.cpp

2026-01-13 02:50:55 UTC by Snehasish Kumar on ⎇

users/snehasish/01-13-_metadata_profcheck_handle_identical_mdnodes_in_getmergedprofmetadata

[Metadata][profcheck] Handle identical MDNodes in getMergedProfMetadata

This fixes a bug where !prof metadata was dropped from SelectInsts when GVN simplified/merged them.
Guarded by -profcheck-disable-metadata-fixes. Exposed by the tests in
Transforms/SampleProfile.

Delta		File
+24	-0	llvm/unittests/IR/MetadataTest.cpp
+8	-0	llvm/lib/IR/Metadata.cpp
+32	-0	2 files

LLVM/project b3d3759 — llvm/lib/IR Metadata.cpp, llvm/unittests/IR MetadataTest.cpp

2026-01-13 02:40:51 UTC by Snehasish Kumar on ⎇

users/snehasish/01-13-_metadata_profcheck_handle_identical_mdnodes_in_getmergedprofmetadata

[Metadata][profcheck] Handle identical MDNodes in getMergedProfMetadata

This fixes a bug where !prof metadata was dropped from SelectInsts when GVN simplified/merged them.
Guarded by -profcheck-disable-metadata-fixes. Exposed by the tests in
Transforms/SampleProfile.

Delta		File
+24	-0	llvm/unittests/IR/MetadataTest.cpp
+8	-0	llvm/lib/IR/Metadata.cpp
+32	-0	2 files

LLVM/project ee3f4bc — llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

2026-01-13 02:35:35 UTC by Mel Chen via GitHub on ⎇

main

[LV][NFC] Follow-up fix for #173262 (#175513)

Delta		File
+6	-7	llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+6	-7	1 files

LLVM/project da94edf — llvm/include/llvm/ADT GenericUniformityImpl.h, llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible reducible-subgraph.ll

2026-01-13 02:19:58 UTC by Sameer Sahasrabuddhe via GitHub on ⎇

main

[UniformityAnalysis] Jump over reducible cycles when locating join blocks (#174938)

When locating the join blocks of a divergent block, the algorithm relies
on pseudo-edges from the header of a reducible cycle to the cycle exits.
This was missed in the actual traversal, producing unnecessary joins
inside the reducible cycle. This caused an assert in the included test,
which expected that if a join existed in a reducible cycle for a
divergent branch outside the cycle, then it must be header.

This fixes the reverted commit from #174117

Delta		File
+56	-0	llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-subgraph.ll
+22	-24	llvm/include/llvm/ADT/GenericUniformityImpl.h
+78	-24	2 files

LLVM/project 77613aa — flang/lib/Semantics resolve-names.cpp, flang/test/Lower/CUDA cuda-gpu-managed.cuf

2026-01-13 02:07:29 UTC by Zhen Wang via GitHub on ⎇

main

[flang][CUDA] Apply implicit managed attribute when `-gpu=mem:managed` is used. (#175648)

When `-gpu=mem:managed` is used, allocatable arrays without explicit
CUDA data attributes are implicitly treated as managed. The
`-gpu=mem:managed` flag to enable this feature is currently only
supported in `bbc`.

Delta		File
+166	-0	flang/test/Lower/CUDA/cuda-gpu-managed.cuf
+7	-0	flang/lib/Semantics/resolve-names.cpp
+2	-2	flang/tools/bbc/bbc.cpp
+175	-2	3 files

LLVM/project e054384 — .github/workflows prune-unused-branches.py prune-branches.yml

2026-01-13 01:40:45 UTC by Aiden Grossman on ⎇

users/boomanaiden154/github-add-initial-workflow-to-prune-unused-user-branches

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

Delta		File
+89	-0	.github/workflows/prune-unused-branches.py
+30	-0	.github/workflows/prune-branches.yml
+119	-0	2 files

LLVM/project 13cd700 — offload/plugins-nextgen/level_zero/src L0Memory.cpp

2026-01-13 01:40:17 UTC by Hansang Bae via GitHub on ⎇

main

[NFC][Offload] Rename a function (#175673)

Renamed a function as suggested in #175664.

Delta		File
+6	-6	offload/plugins-nextgen/level_zero/src/L0Memory.cpp
+6	-6	1 files

LLVM/project 99d6141 — llvm/include/llvm/Transforms/Utils LowerMemIntrinsics.h, llvm/lib/Transforms/Utils LowerMemIntrinsics.cpp

2026-01-13 01:32:27 UTC by Mircea Trofin on ⎇

users/mtrofin/12-15-memset

Memset

Delta		File
+112	-37	llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
+31	-18	llvm/test/Transforms/PreISelIntrinsicLowering/X86/memcpy-inline-non-constant-len.ll
+20	-8	llvm/test/Transforms/PreISelIntrinsicLowering/X86/memset-inline-non-constant-len.ll
+4	-2	llvm/include/llvm/Transforms/Utils/LowerMemIntrinsics.h
+0	-3	llvm/utils/profcheck-xfail.txt
+167	-68	5 files

LLVM/project adf7824 — llvm/lib/Transforms/Vectorize VPlan.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize tripcount.ll

2026-01-13 01:27:39 UTC by Mircea Trofin on ⎇

users/mtrofin/01-08-capture_weights

capture weights

Delta		File
+23	-6	llvm/lib/Transforms/Vectorize/VPlan.cpp
+9	-6	llvm/test/Transforms/LoopVectorize/tripcount.ll
+2	-0	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+34	-12	3 files

LLVM/project 5d45dfd — llvm/lib/CodeGen CodeGenPrepare.cpp

2026-01-13 01:27:39 UTC by Mircea Trofin on ⎇

users/mtrofin/10-06-_wip_profcheck_codegen_prepare

[WIP][profcheck] Codegen Prepare

Delta		File
+15	-2	llvm/lib/CodeGen/CodeGenPrepare.cpp
+15	-2	1 files

LLVM/project a204658 — llvm/test/Transforms/LoopVectorize tripcount.ll

2026-01-13 01:27:39 UTC by Mircea Trofin on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[NFC] use UTC for LoopVectorize/tripcount.ll

Delta		File
+213	-29	llvm/test/Transforms/LoopVectorize/tripcount.ll
+213	-29	1 files

LLVM/project a01b7c2 — . .gitignore

2026-01-13 01:27:05 UTC by Daniil Fukalov via GitHub on ⎇

main

[LLVM] Ignore two Cursor specific files. (#175683)

Delta		File
+2	-0	.gitignore
+2	-0	1 files

LLVM/project ed9f5c9 — llvm/lib/Target/RISCV RISCVInstrInfoVPseudos.td, llvm/test/tools/llvm-mca/RISCV/SiFiveX390 vector-fp.s

2026-01-13 01:24:57 UTC by Min-Yih Hsu via GitHub on ⎇

main

[RISCV] Add the missing SEW search table field to vector FMA instructions (#175646)

We split vector floating point FMA (pseudo) instructions' opcodes by SEW
since c6b7944be4dfbb1fb35301c670812726845acaa7 , but forgot to populate
their `SEW` field, which is used by various search tables. This results
in incorrect pseudo instruction opcodes lookup -- and to a larger
extent, incorrect scheduling class lookups -- in llvm-mca. This patch
fixes such issue.

Delta		File
+129	-129	llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s
+48	-48	llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fp.test
+32	-32	llvm/test/tools/llvm-mca/RISCV/SpacemitX60/rvv/fma.test
+1	-1	llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+210	-210	4 files

LLVM/project 438f887 — llvm CMakeLists.txt

2026-01-13 01:18:51 UTC by Reid Kleckner via GitHub on ⎇

main

[cmake] Make CMAKE_BUILD_TYPE=Release the default (#174520)

Currently, we report a fatal error if the user leaves CMAKE_BUILD_TYPE
blank. This was implemented in https://reviews.llvm.org/D124153 /
350bdf9227ceb , based on this RFC:

https://discourse.llvm.org/t/rfc-select-a-better-linker-by-default-or-warn-about-using-bfd/61899/1

Tom Stellard mentioned that he'd like to revisit this on Discord, and
Aiden, myself, and apparently most people on the original RFC agree, so
I'm proposing we do it. However, on the review, several folks objected
and insisted that Debug was a better default. I want to reopen the
question.

I think we've made the wrong tradeoff. I wish Debug builds worked out of
the box on most systems, but they don't, and LLVM has only gotten bigger
over the last four years, making the build scalability problems of Debug
builds worse. I think we should optimize our build configuration for new
developers, not experienced longtime contributors who are invested

    [9 lines not shown]

Delta		File
+3	-8	llvm/CMakeLists.txt
+3	-8	1 files

LLVM/project 2329d04 — llvm/test/CodeGen/AArch64 arm64-homogeneous-prolog-epilog-tail-call.mir

2026-01-13 01:16:54 UTC by Mircea Trofin via GitHub on ⎇

main

Remove cleanup of incorrect output in test dir (#171256)

This follows #171255 , removing the cleanup line.

Delta		File
+0	-1	llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir
+0	-1	1 files

LLVM/project a7ad427 — llvm/lib/Transforms/Vectorize VPlan.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize tripcount.ll

2026-01-13 01:15:34 UTC by Mircea Trofin on ⎇

users/mtrofin/01-08-capture_weights

capture weights

Delta		File
+23	-6	llvm/lib/Transforms/Vectorize/VPlan.cpp
+9	-6	llvm/test/Transforms/LoopVectorize/tripcount.ll
+2	-0	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+34	-12	3 files

LLVM/project 0dcd112 — llvm/test/Transforms/LoopVectorize tripcount.ll

2026-01-13 01:14:49 UTC by Mircea Trofin on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[NFC] use UTC for LoopVectorize/tripcount.ll

Delta		File
+213	-29	llvm/test/Transforms/LoopVectorize/tripcount.ll
+213	-29	1 files

LLVM/project f9c561b — llvm/lib/Transforms/Utils LoopUtils.cpp, llvm/test/Transforms/LoopVectorize branch-weights.ll

2026-01-13 01:12:35 UTC by Mircea Trofin via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[profcheck] Fix encoding of 0 loopEstimatedTrip count (#174896)

We currently encode an estimated trip count of 0 as the latch having branch probabilities 0-0. That's an invalid pair of weights. The probability of a branch is computed as a fraction of its corresponding weight and the sum of the weights. In fact, `BranchProbabilityInfo::calcMetadataWeights` will convert this to a 1-1, meaning 50% - 50%, which isn't quite what we want. To indicate the loop is never taken, we just need to initialize the exit probability to non-zero (hence, 1)

Related: https://reviews.llvm.org/D67905

Issue #147390

Delta		File
+5	-5	llvm/test/Transforms/LoopVectorize/AArch64/check-prof-info.ll
+4	-1	llvm/lib/Transforms/Utils/LoopUtils.cpp
+2	-2	llvm/test/Transforms/LoopVectorize/branch-weights.ll
+1	-1	llvm/unittests/Transforms/Utils/LoopUtilsTest.cpp
+12	-9	4 files

LLVM/project 26624d5 — clang/include/clang/Basic BuiltinsAMDGPU.def, clang/test/CodeGenOpenCL amdgpu-features.cl amdgpu-cluster-dims.cl

2026-01-13 01:10:09 UTC by Shoreshen via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[AMDGPU]Add specific instruction feature for multicast load (#175503)

Delta		File
+7	-7	clang/include/clang/Basic/BuiltinsAMDGPU.def
+11	-1	llvm/lib/Target/AMDGPU/AMDGPU.td
+2	-2	clang/test/CodeGenOpenCL/amdgpu-features.cl
+2	-2	clang/test/CodeGenOpenCL/amdgpu-cluster-dims.cl
+2	-2	llvm/lib/Target/AMDGPU/FLATInstructions.td
+3	-0	llvm/lib/Target/AMDGPU/GCNSubtarget.h
+27	-14	1 files not shown
+28	-14	7 files

LLVM/project a9037dc — orc-rt Maintainers.md

2026-01-13 01:08:27 UTC by Lang Hames via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[orc-rt] Add Maintainers.md. (#175691)

Delta		File
+10	-0	orc-rt/Maintainers.md
+10	-0	1 files

LLVM/project 587bac6 — llvm/lib/Target/RISCV RISCVMakeCompressible.cpp, llvm/test/CodeGen/RISCV make-compressible-xqci.mir

2026-01-13 01:04:18 UTC by Sudharsan Veeravalli via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[RISCV] Adjust base cost for Xqcilo loads/stores in RISCVMakeCompressible (#175572)

We only need two uses in Xqcilo load/store instructions for the base
adjustment to be profitable as compared to three uses in the base
load/store instructions.

Delta		File
+48	-5	llvm/test/CodeGen/RISCV/make-compressible-xqci.mir
+38	-7	llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+86	-12	2 files

LLVM/project c6fc6ad — clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 avx512vlvp2intersect-builtins.c avx512vp2intersect-builtins.c

2026-01-13 01:04:01 UTC by Vishruth Thimmaiah via GitHub on ⎇

users/mtrofin/01-08-_nfc_use_utc_for_loopvectorize/tripcount.ll

[CIR][X86] Add support for `intersect` builtins (#172554)

adds support for the
`__builtin_ia32_vp2intersect_d`/`__builtin_ia32_vp2intersect_q` x86
builtins.

Part of #167765

---------

Signed-off-by: vishruth-thimmaiah <vishruththimmaiah at gmail.com>

Delta		File
+161	-0	clang/test/CIR/CodeGenBuiltins/X86/avx512vlvp2intersect-builtins.c
+77	-0	clang/test/CIR/CodeGenBuiltins/X86/avx512vp2intersect-builtins.c
+64	-10	clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+302	-10	3 files