LLVM/project 7adcd9b — llvm/test/CodeGen/LoongArch/lasx vec-sext-invec-mask.ll build-vector.ll, llvm/test/CodeGen/LoongArch/lsx vec-reduce-add.ll scalar-load-to-vector.ll

[LoongArch] Load scalars into vector lane 0 with FLD/VLDREPL

Inserting a loaded integer into lane 0 of an undefined vector, which is
also how sub-128-bit vector loads are legalized, was lowered to a scalar
load plus [X]VINSGR2VR. VINSGR2VR merges into its destination, so it
carries a false dependency on the previous value of that register, and
it needs a GPR-to-vector move.

Use FLD.{S/D} for 32/64-bit elements and [X]VLDREPL.{B/H} for 8/16-bit
elements instead. They write the whole register in one instruction.

When the register allocator reuses one vector register for several such
loads, the false dependency serializes otherwise independent chains. In
the GSM autocorrelation loop (9 x i64 multiply-accumulate over i16 taps)
on LA664:

  VF2: 0.953s -> 0.724s
  VF4: 1.446s -> 0.856s
DeltaFile
+76-80llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
+33-41llvm/test/CodeGen/LoongArch/lsx/scalar-load-to-vector.ll
+32-36llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
+30-36llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
+20-32llvm/test/CodeGen/LoongArch/lasx/vec-sext-invec-mask.ll
+18-30llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll
+209-25521 files not shown
+508-65227 files

LLVM/project 34e9274 — mlir/test/Dialect/Vector vector-transfer-full-partial-split-copy-transform.mlir

address review comment
DeltaFile
+31-0mlir/test/Dialect/Vector/vector-transfer-full-partial-split-copy-transform.mlir
+31-01 files

LLVM/project 781f924 — llvm/include/llvm/LTO Config.h, llvm/test/LTO/AMDGPU parallel-diagnostics.ll

[LTO] Prevent crashes if a diagnostic is emitted while compiling with `--lto-partitions`

Claude found this bug for me while working on the earlier path.
I checked it and I think this fix makes sense. Without the fix in Config.h, the test crashes with `bad_function_call`.

There were other ways to fix it but I think this makes the most sense as it fixes all users.
I only check the full LTO path as all thinLTO paths set a diagnostic handler, and I don't think adding a unit test just to check
the thinLTO path without a diag handler was worth it.

Assisted-By: Claude Sonnet 5.5
DeltaFile
+28-0llvm/test/LTO/AMDGPU/parallel-diagnostics.ll
+4-0llvm/include/llvm/LTO/Config.h
+32-02 files

LLVM/project 4597657 — llvm/test/CodeGen/LoongArch/lasx scalar-load-to-vector.ll, llvm/test/CodeGen/LoongArch/lsx scalar-load-to-vector.ll

[LoongArch][NFC] Pre-commit tests for loading a scalar into a vector
DeltaFile
+243-0llvm/test/CodeGen/LoongArch/lsx/scalar-load-to-vector.ll
+137-0llvm/test/CodeGen/LoongArch/lasx/scalar-load-to-vector.ll
+380-02 files

LLVM/project d5a6314 — clang/test/CIR/Lowering offload-printf-amdgpu.cir offload-printf-amdgpu-unsupported.cir

[NFC][CIR][AMDGPU] Use amdgpu-amd-amdhsa triple in offload printf tests (#237225)

Follow-up to #235901 for tests added later in
https://github.com/llvm/llvm-project/pull/231563
DeltaFile
+1-1clang/test/CIR/Lowering/offload-printf-amdgpu.cir
+1-1clang/test/CIR/Lowering/offload-printf-amdgpu-unsupported.cir
+2-22 files

LLVM/project 1e662a7 — llvm/lib/Target/SPIRV SPIRVPrepareFunctions.cpp, llvm/test/CodeGen/SPIRV expect.ll

[SPIR-V] Lower llvm.expect.with.probability to OpExpectKHR (#237712)

The hint was silently dropped with SPV_KHR_expect_assume

OpExpectKHR has no probability operand, so lower to spv_expect with the
first two operands
DeltaFile
+27-0llvm/test/CodeGen/SPIRV/expect.ll
+15-1llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+42-12 files

LLVM/project a08763b — llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array vararr_spec_const.ll vararr.ll

[NFC][SPIR-V] Re-enable spirv-val on untyped pointer vararr tests (#237880)

Related SPIRV-Tools fix accepting untyped pointers in
OpLifetimeStart/Stop:
https://github.com/KhronosGroup/SPIRV-Tools/pull/7012
DeltaFile
+1-3llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll
+1-3llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll
+2-62 files

LLVM/project 0537585 — mlir/include/mlir/TableGen EnumInfo.h, mlir/lib/TableGen EnumInfo.cpp

[mlir][ODS] Add EnumInfo accessors for the bit enum separator (NFC) (#237962)

The generators read the bit enum `separator` field through
`getValueAsString` in nine places, and EnumsGen and OpFormatGen each had
a copy of the `StringSwitch` that maps it to the `AsmParser` method that
parses it. This adds `EnumInfo::getBitEnumSeparator`,
`getBitEnumSeparatorKind` and `getBitEnumSeparatorParser` and uses them
at every site; the comma checks now compare the kind. Generated code is
unchanged for the in-tree enums. A separator other than `|` or `,` used
to produce C++ that did not compile and is now a TableGen error. Split
out of llvm/llvm-project#237149, which adds a space-only separator on
top of this.

Assisted-by: Claude Code (Claude Opus 5.5).
DeltaFile
+25-0mlir/lib/TableGen/EnumInfo.cpp
+9-12mlir/tools/mlir-tblgen/EnumsGen.cpp
+4-9mlir/tools/mlir-tblgen/OpFormatGen.cpp
+12-0mlir/include/mlir/TableGen/EnumInfo.h
+2-1mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
+1-1mlir/tools/mlir-tblgen/EnumPythonBindingGen.cpp
+53-236 files

LLVM/project 66549bc — offload/test/offloading target-no-loop.c

Add explicit map for lastprivate value

Add explicit map for lastprivate scalar value to allow copy back due to
missing implicit map (known issue #49496).
DeltaFile
+3-9offload/test/offloading/target-no-loop.c
+3-91 files

LLVM/project 25ef8e1 — llvm/test/CodeGen/AArch64 build-vector-extract.ll aarch64-neon-vector-insert-uaddlv.ll

Update Test Checks
DeltaFile
+644-665llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+72-48llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
+13-17llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
+1-3llvm/test/CodeGen/AArch64/build-vector-extract.ll
+730-7334 files

LLVM/project d831651 — llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 shuffle-insert-zero.ll

[AArch64][DAG] Improve codegen for clearing upper vector lanes

Add patterns that use scalar fmov instruction to clear the upper lanes of a vector
DeltaFile
+227-406llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
+49-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+276-4062 files

LLVM/project f38815f — llvm/lib/Transforms/InstCombine InstCombineVectorOps.cpp, llvm/test/Transforms/InstCombine vec_shuffle.ll

[InstCombine] Canonicalise Vector Shuffle that clears upper bits

Currently, shuffle vectors that are equivalent to preserving lane 0 and clearing the uppers lanes of a vector result in different shuffle vectors and masks

Recognise and canonicalise the shuffleVectors to the same form allowing for easier recognition in the backend
DeltaFile
+57-0llvm/test/Transforms/InstCombine/vec_shuffle.ll
+47-0llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
+104-02 files

LLVM/project 7c37afe — llvm/test/Transforms/InstCombine insert-element-shuffle-vector-debugloc.ll vec_shuffle.ll

Update test checks
DeltaFile
+5-5llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
+4-4llvm/test/Transforms/InstCombine/vec_shuffle.ll
+1-1llvm/test/Transforms/InstCombine/insert-element-shuffle-vector-debugloc.ll
+10-103 files

LLVM/project 667688a — llvm/test/CodeGen/AArch64 llvm-masked-scatter-legal-for-sve.ll llvm-masked-gather-legal-for-sve.ll

[AArch64][NFC] Fix fixed-width gather/scatter expand tests (#238013)

The tests were ensuring that the IR didn't contain a call to
`@llvm.masked.gather.v4i32(`, etc. However, in reality the CHECK-NOT
lines always pass even if we do generate a masked gather call because
the intrinsic name is actually llvm.masked.gather.v4i32.v4p0, etc.
DeltaFile
+2-8llvm/test/CodeGen/AArch64/llvm-masked-scatter-legal-for-sve.ll
+2-8llvm/test/CodeGen/AArch64/llvm-masked-gather-legal-for-sve.ll
+4-162 files

LLVM/project ad24690 — llvm/lib/Target/AArch64 AArch64Options.td

Document -aarch64-enable-async-unwind-for-minsize as a temporary option
DeltaFile
+2-1llvm/lib/Target/AArch64/AArch64Options.td
+2-11 files

LLVM/project 6fc3f11 — lld/ELF LTO.cpp, lld/test/ELF/lto lto-partitions-cache.ll

Comments
DeltaFile
+31-0llvm/test/LTO/AMDGPU/parallel-cache.ll
+27-0lld/test/ELF/lto/lto-partitions-cache.ll
+18-2llvm/lib/LTO/LTOCodeGenerator.cpp
+1-7lld/ELF/LTO.cpp
+4-0llvm/tools/llvm-lto/llvm-lto.cpp
+81-95 files

LLVM/project fed20e0 — llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp, llvm/test/CodeGen/X86 null-pointer-vector-object.ll

[AsmPrinter] Emit null pointer vector splats as zero bytes (#235980)

Emitting a global such as `@x = global <2 x ptr> zeroinitializer` with
`llc -data-sections -filetype=obj` asserts on 64-bit targets.
`ConstantPointerNull` can represent a vector splat since #195486, but
AsmPrinter passes the entire allocation size to
`MCStreamer::emitIntValue`, which accepts at most eight bytes.

Route pointer-vector splats through `emitGlobalConstantVector`, matching
the existing handling of integer and floating-point splats. Its
zero-value path emits the full allocation with `emitZeros`. Keep scalar
pointers on the existing `emitIntValue` path.

Fixes #235977

Assisted-by: OpenAI Codex
DeltaFile
+20-0llvm/test/CodeGen/X86/null-pointer-vector-object.ll
+2-0llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+22-02 files

LLVM/project f80b0f3 — llvm/lib/CodeGen MachineLICM.cpp, llvm/test/CodeGen/AArch64 freeze-load-zext-copytoreg.ll

[MachineLICM] Fix incorrect hoisting from a speculation cache shared between loops (#234138)

Since 5ec9699, MachineLICM may check a block against both an outer loop
and its subloops, but whether the block is guaranteed to execute was
cached once per block. A result computed for an inner loop could then be
reused for the outer loop, so a load was hoisted above the guard that
made it safe. This causes wrong code in #233340, and in the reverse case
some loads were no longer hoisted to the inner preheader (the existing
test changes).

Use `SmallDenseMap` to cache the result per loop.

Fixes #233340

Assisted-by: Claude Opus 5.5
DeltaFile
+42-38llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
+79-0llvm/test/CodeGen/X86/machinelicm-subloop-speculation.mir
+18-16llvm/test/CodeGen/AArch64/freeze-load-zext-copytoreg.ll
+9-15llvm/lib/CodeGen/MachineLICM.cpp
+6-6llvm/test/CodeGen/RISCV/freeze-load-zext-copytoreg.ll
+154-755 files

LLVM/project d6a4b2a — llvm/cmake/modules TableGen.cmake, llvm/include/llvm/IR CMakeLists.txt

[CMake][NFC] Add llvm_tablegen and use it instead of tablegen(LLVM ...) (#235796)

Other subprojects invoke their TableGen through a project-specific
wrapper (clang_tablegen, mlir_tablegen, lldb_tablegen). Add
llvm_tablegen for llvm-tblgen and replace every tablegen(LLVM ...) call
with it.

The llvm-tblgen-specific logic in tablegen() moves into llvm_tablegen:
the DAGISel/GlobalISel coverage and -omit-comments flags, and the extra
outputs of -gen-register-info, which tablegen() now accepts generically
through a new EXTRA_OUTPUTS argument.

My motivation is general cleanliness but also as a use-case to add the
`EXTRA_OUTPUTS` cmake option to the `tablegen` command
DeltaFile
+40-25llvm/cmake/modules/TableGen.cmake
+25-25llvm/lib/Target/AMDGPU/CMakeLists.txt
+23-23llvm/lib/Target/AArch64/CMakeLists.txt
+23-23llvm/include/llvm/IR/CMakeLists.txt
+21-21llvm/lib/Target/X86/CMakeLists.txt
+21-21llvm/lib/Target/RISCV/CMakeLists.txt
+153-138105 files not shown
+524-493111 files

LLVM/project ed01afe — mlir/lib/Dialect/Transform/IR TransformOps.cpp, mlir/test/Dialect/Transform ops-invalid.mlir

[mlir][transform] Fix crash on empty type converter region (#237717)

The default type converter region of transform.apply_conversion_patterns is
declared MaxSizedRegion<1>, so it may have no blocks. The verifier called
front() on it unconditionally, which hits an assertion on an empty region.

Check for an empty region first and report the existing "expected exactly one op
in default type converter region" error. Add tests for both an empty block
(custom syntax) and a region without blocks, which is only expressible in the
generic form.

Assisted-by: Claude

Fixes #234636
DeltaFile
+28-0mlir/test/Dialect/Transform/ops-invalid.mlir
+2-1mlir/lib/Dialect/Transform/IR/TransformOps.cpp
+30-12 files

LLVM/project 4580f79 — llvm/test/CodeGen/SPIRV addrspacecast-ptradd-global.ll

Replace undef with poison in test case
DeltaFile
+1-1llvm/test/CodeGen/SPIRV/addrspacecast-ptradd-global.ll
+1-11 files

LLVM/project 2120c3d — llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV addrspacecast-ptradd-non-null.ll addrspacecast-ptradd-global.ll

[SPIR-V] Fix G_PTR_ADD selection for addrspacecast global initializers
DeltaFile
+61-9llvm/test/CodeGen/SPIRV/addrspacecast-ptradd-global.ll
+31-9llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+7-8llvm/test/CodeGen/SPIRV/addrspacecast-ptradd-non-null.ll
+99-263 files

LLVM/project 4474a33 — llvm/test/CodeGen/SPIRV addrspacecast-ptradd-non-null.ll addrspacecast-ptradd-global.ll

Pre-commit test cases
DeltaFile
+30-0llvm/test/CodeGen/SPIRV/addrspacecast-ptradd-global.ll
+20-0llvm/test/CodeGen/SPIRV/addrspacecast-ptradd-non-null.ll
+50-02 files

LLVM/project cb20860 — flang/include/flang/Evaluate type.h expression.h, flang/lib/Evaluate tools.cpp fold-logical.cpp

[Flang] KIND De-templatization (#216960)

Avoid template instantiation based on a type's kind, but pass the kind
as runtime value. The cross-product of template instantiations
(including nested `visit` calls of methods that are already per-kind)
leads to super-linear compile-time bloat.
For more details, see the RFC:
https://discourse.llvm.org/t/rfc-the-cost-of-templates-when-building-flang/91197.

### Implementation notes

* The conversion is meant to be mostly mechanical, wherever possible.
That is, the following rules were applied:

1. If a function implementation is independent of KIND, just remove the
template argument
2. If another object is passed as argument (or exists as a field of the
class) with the same KIND, get KIND from its `.kind()` method, and store
it in a variable `const int kind`.

    [74 lines not shown]
DeltaFile
+383-321flang/lib/Evaluate/fold-integer.cpp
+395-298flang/lib/Evaluate/fold-implementation.h
+208-351flang/lib/Evaluate/fold-logical.cpp
+305-137flang/include/flang/Evaluate/expression.h
+141-197flang/lib/Evaluate/tools.cpp
+147-110flang/include/flang/Evaluate/type.h
+1,579-1,414123 files not shown
+4,238-3,603129 files

LLVM/project 9200229 — flang/test/Integration/OpenMP collapse-worksharing.f90, llvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h

[OpenMP][MLIR] Add virtual collapse for constant static worksharing (#235822)

This patch adds virtual collapse for OpenMP loop nests in
`OpenMPIRBuilder` and enables it in Flang through MLIR-to-LLVM IR
translation. It retains the physical nest and decodes the start of each
assigned logical range once.

This is the first patch in a proposed series, introducing the basic
functionality. Virtual collapse is enabled by default when these
conditions hold:

- Host standalone worksharing with `collapse(2)` and directly nested
loops.
- Constant normalized trip counts.
- Static or default scheduling without a chunk size.
- No `ordered` or `linear` clauses.

Other cases retain the existing lowering. Follow-up patches will extend
the supported cases. Flang can opt out with `-mmlir

    [9 lines not shown]
DeltaFile
+510-0mlir/test/Target/LLVMIR/openmp-collapse-virtual-constant.mlir
+465-0llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+288-21llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+241-0flang/test/Integration/OpenMP/collapse-worksharing.f90
+98-3llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+68-9mlir/test/Target/LLVMIR/openmp-nsw-collapsed.mlir
+1,670-335 files not shown
+1,745-3311 files

LLVM/project 95f39bd — compiler-rt/lib/sanitizer_common sanitizer_platform.h sanitizer_mac.cpp

[compiler-rt][Darwin] Add SANITIZER_ macros for individual Darwin OSes (#237765)

`SANITIZER_IPHONEOS` is now exactly `TARGET_OS_IOS` (iOS only), while
`SANITIZER_IOS` (derived from `TARGET_OS_IPHONE`) remains "iOS-like".
Also add `SANITIZER_VISIONOS` for `TARGET_OS_VISION`.

Update the shared macOS-aligned mapping computation to use the new
macro.

Assisted-By: Claude

rdar://191534752
DeltaFile
+10-10compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp
+15-1compiler-rt/lib/sanitizer_common/sanitizer_platform.h
+25-112 files

LLVM/project 247d373 — offload/unittests/OffloadAPI/common Properties.hpp Fixtures.hpp, offload/unittests/OffloadAPI/context olCreateContext.cpp

[Offload] Add multi-device testing (#233387)

This PR changes the way our fixtures group devices - instead of grouping
each device separately, we group compatible devices into a vector.
`OFFLOAD_TESTS_INSTANTIATE_DEVICE_FIXTURE` still has the same behavior -
a test is instantiated for each device separately, but
`OFFLOAD_TESTS_INSTANTIATE_MULTI_DEVICE_FIXTURE` can be used so a test
is instantiated with many `std::vector<ol_device_handle_t> Devices`. I
kept `ol_device_handle_t Device`, so single device tests stay simple.

For now I added simple memcpy tests, later we can add more complex tests
with kernels that communicate across devices. Such tests might require
additional APIs to express p2p connection between devices though.

Assisted with: claude
DeltaFile
+124-0offload/unittests/OffloadAPI/memory/olMemcpy.cpp
+83-26offload/unittests/OffloadAPI/common/Fixtures.hpp
+5-4offload/unittests/OffloadAPI/common/Properties.hpp
+3-2offload/unittests/OffloadAPI/context/olCreateContext.cpp
+215-324 files

LLVM/project 5cd8ac8 — llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV addrspacecast-ptradd-non-null.ll addrspacecast-ptradd-global.ll

[SPIR-V] Fix G_PTR_ADD selection for addrspacecast global initializers
DeltaFile
+61-9llvm/test/CodeGen/SPIRV/addrspacecast-ptradd-global.ll
+31-9llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+7-8llvm/test/CodeGen/SPIRV/addrspacecast-ptradd-non-null.ll
+99-263 files

LLVM/project 8929c78 — llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/test/MC/COFF ir-to-imgrel-reject.ll ir-to-imgrel.ll

[CodeGen] Lower differences from __ImageBase to image relative references on MinGW (#237118)

`TargetLoweringObjectFileCOFF::lowerRelativeReference` returned early
for Cygwin and MinGW, so a constant of the form `ptrtoint(X) -
ptrtoint(__ImageBase)` reached the object writer as a plain symbol
difference and failed with `symbol '__ImageBase' can not be undefined in
a subtraction expression`. MSVC targets lower the same expression to
`X at IMGREL`, an `IMAGE_REL_AMD64_ADDR32NB` relocation

The early return looks inherited and not decided. The transform was
added in dee105772c5b (D2523) behind `isTargetWindows()`, which then
meant MSVC only. 98117a47e649 (D47783) moved it into the shared COFF
code and wrote the MinGW and Cygwin exclusion explicitly, and
2f07c2e9d9cc turned it into `isOSCygMing()`. GNU ld has defined
`__ImageBase` since 2008 and lld defines it too, and the object file
only needs the relocation, so there is no reason to treat the
environment differently

The MinGW cases are added to `llvm/test/MC/COFF/ir-to-imgrel.ll` and

    [7 lines not shown]
DeltaFile
+0-4llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+3-0llvm/test/MC/COFF/ir-to-imgrel.ll
+2-0llvm/test/MC/COFF/ir-to-imgrel-reject.ll
+5-43 files

LLVM/project 24e9df9 — llvm/include/llvm/DTLTO DTLTO.h, llvm/include/llvm/LTO LTO.h

Comments
DeltaFile
+6-9llvm/include/llvm/LTO/LTO.h
+2-10llvm/lib/LTO/LTO.cpp
+1-3llvm/lib/LTO/LTOBackend.cpp
+1-1llvm/include/llvm/DTLTO/DTLTO.h
+10-234 files