[lldb] Fix use-after-free in jThreadsInfo stop info cache (#223488)
WillPublicStop iterates over the array borrowed from m_jthreadsinfo_sp
while WillResume concurrently resets the pointer on another thread,
freeing the array during the walk.
Protect the cached stop info with a mutex and copy the shared pointer
out before processing. Also modernize m_shared_cache_info to Guarded.
rdar://186776438
[BOLT][AArch64] Make Android instrumentation runtime fail safe (#223110)
Profiling failure in BOLT instrumentation runtime should not kill the
host app on Android. Under `ANDROID_AARCH64`, we now handle failures
in instrumentation setup, memory allocation, hash table operations,
data dumping, opening profile output file, zero-counter binary, etc..
Since the first failure, we will disable profiling and directly return
from various instrumentation entry points, instead of assert/exit.
Only for Android AArch64; the behavior is unchanged otherwise.
[CIR] Atomic compare-and-exchange via libcall (#206073)
This patch adds support for atomic compare-and-exchange operations via libcall.
Assisted-by: Codex / gpt-5.5 xhigh
[SystemZ][z/OS] Add AMODE to PR symbols
Contrary to the documentation, setting the AMODE at PR symbols is
required. The symptom is that references to variables `optind` and
`optarg` (from include `<getopt.h>`, the LE-provided C runtime)
results in "missing symbol" errors.
Fix is to add AMODE to PrAttr, analog to LdAttr.
[CIR] Fix 'isConstant' calc when looking at an incomplete type (#223444)
This popped up in a benchmark. Classic codegen ALWAYS sets this as
'excludeCtor'/'excludeDtor', but CIR tried 'harder' to get this right.
However, with an incomplete type, we can't actually look into it to see
if it has any mutable members, so determining 'constness' isn't
possible.
We could PROBABLY do better with enums since I would assume they can be
constant most of the time, but we fall-back to classic-codegen's
behavior here instead: which marks it as non-const.
Thanks to 'trying harder' than classic codegen as mentioned above, there
IS a slight LLVM-IR difference, but for the better.
Also note: Claude helped me with the tests.
[libc] feat(filemode): implement class and helper functions to handle file modes for an opened file (#220906)
I moved the logic from `mode_flags` function to the `FileMode`
constructor.
The `FileMode` class has several helper methods to work with modes which
can then be called in `File` class.
Issue: #213374
---------
Signed-off-by: tdadadavid <davidtofunmidada at gmail.com>
Co-authored-by: Michael Jones <michaelrj at google.com>
[RISCV] Teach RISCVOptWInstrs that zext.w is fixable to sext.w. (#223559)
Note, in some cases erasing the zext.w and fixing an earlier
instruction would be even better but that requires more extensive
changes.
[mlir] Migrate AMDGPU/ROCDL to targets, not chipset versions
**migration tl;dr:** Replace usages of `amdgpu::Chipset` with `ROCDL::TargetInfo`, ideally move from `chipset=` to `arch=`. If you don't use upstream pipelines, call 'TargetInfo::migrateArchFeaturesToModuleFlags` at the appropriate location.
Further note: if you've got a build pipeline that's getting a `gfxXXX` name from something like `rocm_agent_enumerator`, using a full triple name like the ones you get from `rocminfo` is preferred.
`amdgpu::Chipset` was an awkward hack that was hard to keep up to date
with changes in the compiler/new architectures, and didn't properly
support generic targets (and has been strongly disfavored by the
compiler team).
This PR replaces `amdgpu::Chipset` with `ROCDL::TargetInfo`, a
structure that uses LLVM's TargetParser and the underlying LLVM
features tables to get the real nature of the target being compiled
for.
This also helps MLIR move to
new-style (`-mtriple=amdgpuX.YZ-amd-amdhsa`) over "old
style" (`-mtriple=amdgcn-amd-amdhsa -mcpu=gfxXYZ`) triples.
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[mlir][ROCDL] Add TargetInfo to replace Chipset, allow features queries
Add a now ROCDL::TargetInfo struct that parses AMDGPU triples and
target names using the same logic that Clang and LLVM
use (TargetParser) and maintains the set of features available on a
given GPU.
This is an improvement over the old `amdgpu::Chipset` struct since
that was just a version number and often became stale compared to the
knowledge exposed by LLVM, such as gfx1170 having OCP FP8 support even
though other gfx11 chips don't have it.
This struct also allows for moving to new-style
triples (amdgpu9.42-amd-amdhsa vs amdgcn-amd-amdhsa--gfx942, for
example), which is an ongoing migration in other parts of the compiler
that this PR lets us follow.
It also enables compiling for generic targets, like `gfx11-generic`,
which can be run on all chips in a generation.
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[AMDGPU] Expose more subtarget features for MLIR
- `FeatureAtomitFaddNoRtnInsts` is needed to control when atomic emulation
for buffer operations happens
- `FeatureBackOffBarrier` controls an inline-assembly workaround for
LDS-only barriers on old gfx9
- `FeatureLfsBarrierArriveAtomic` is a precise flag compared to arch versions
- `FeatureORPFP8ConversionInsts` controls which MLIR FP8 types can be
lowered to LLVM
- `FeaturePermlane16Insts`is another feature check
Clang and flang tests are updated since they look at the feature set
AI disclosure: Claude made these changes, I wrote this message
[ScalarEvolution] howManyLessThans infer stride isPositive from guard (#214014)
Infer Stride is positive from loop guard.
This enables SCEV to compute symbolic-max backedge-taken count for
multi-exit loops.
Motivating example:
void example(int *p, int n, int stride, int bound) {
if (stride <= 0) __builtin_trap(); // dominating guard => stride > 0
for (int i = 0; i < n; i += stride) {
if (i > bound) __builtin_trap(); // per-iteration bounds check (2nd
exit)
p[i] = 0;
}
}
[CIR][AMDGPU] Add support for AMDGCN bitop3 builtins (#223104)
Adds codegen for the following AMDGCN bitop3 builtins:
- __builtin_amdgcn_bitop3_b32
- __builtin_amdgcn_bitop3_b16
These are lowered to the corresponding `llvm.amdgcn.bitop3` intrinsic.
[AMDGPU] Model the cost of the expanded integer to/from floating point casts
No instruction converts to or from a 64 bit integer, and narrow vector
lanes are converted one at a time. Price these expansions by the FP64
rate, sdwa and 16 bit instruction support, and price i33 to i63 like
i64 and bf16 like f32 plus rounding.
Assisted-by: Claude Code Opus 5
[SystemZ][z/OS] Add AMODE to PR symbols
Contrary to the documentation, setting the AMODE at PR symbols is
required. The symptom is that references to variables `optind` and
`optarg` (from include `<getopt.h>`, the LE-provided C runtime)
results in "missing symbol" errors.
Fix is to add AMODE to PrAttr, analog to LdAttr.
