Reapply "[VPlan] Remove manual region removal when simplifying for VF and UF. (#181252)" (#188589)
This reverts commit e30f9c19464bcf1bf1e9f69b63884fb78ad2d05d.
Re-land, now that the reported crash causing the revert has been fixed
as part of 77fb84889 (#187504).
Original message:
Replace manual region dissolution code in
simplifyBranchConditionForVFAndUF with using general
removeBranchOnConst. simplifyBranchConditionForVFAndUF now just creates
a (BranchOnCond true) or updates BranchOnTwoConds.
The loop then gets automatically removed by running removeBranchOnConst.
This removes a bunch of special logic to handle header phi replacements
and CFG updates. With the new code, there's no restriction on what kind
of header phi recipes the loop contains.
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[lldb/test] Remove stale arm Linux expectedFailure decorators (NFC)
These tests no longer fail on arm Linux after the frame provider
re-entrancy fixes, so remove the decorators.
XPASS: https://lab.llvm.org/buildbot/#/builders/18/builds/25348
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
[llvm-debuginfo-analyzer] Support `S_DEFRANGE_REGISTER_REL_INDIR` (#187531)
#186410 added support for reading `S_DEFRANGE_REGISTER_REL_INDIR` in
LLVM's CodeView. This adds support for printing it in
llvm-debuginfo-analyzer. This record is not (yet) generated by LLVM. It
encodes an indirect location like `S_REGREL32_INDIR` but for a range (so
it's conceptually a child of `S_LOCAL` which only encodes _some_
variable in a function).
---------
Co-authored-by: Javier Lopez-Gomez <javier.lopez.gomez at proton.me>
[lldb][Module][NFC] Extract script loading logic into helper (#188712)
Planning on re-using this within the same function. Extracting into
helper makes that slightly more readable.
[compiler-rt][ARM] Double-precision FP support functions (#179920)
This commit adds C helper functions `dnan2`, `dnorm2` and `dunder` for
handling the less critical edge cases of double-precision arithmetic,
similar to `fnan2`, `fnorm2` and `funder` that were added in commit
f7e652127772e93.
It also adds a header file that defines some register aliases for
handling double-precision numbers in AArch32 software floating point in
an endianness-independent way, by providing aliases `xh` and `xl` for
the high and low words of the first double-precision function argument,
regardless of which of them is in r0 and which in r1, and similarly `yh`
and `yl` for the second argument in r2/r3.
libclc: Update erf (#188569)
This was originally ported from rocm device libs in
c374cb76f467f01a3f60740703f995a0e1f7a89a. Merge in more
recent changes. Also enables vectorization.
[AArch64] Sink NOT to be fold into BIC/ORN/EON (#176194)
Undoes a negation being hoisted out of a loop, so that if can be fold
into an inverted bitwise operation in the loop.
Implements #108840 on AArch64
[DA] Fix overflow of calculation in weakCrossingSIVtest
This patch fixes a correctness issue where integer overflow in the
upper bound calculation of weakCrossingSIVtest caused the pass to
incorrectly prove independence.
The previous logic used `SCEV::getMulExpr` to calculate
`2 * ConstCoeff * UpperBound` and compared it to `Delta` using
`isKnownPredicate`. In the presence of overflow, this could yield
unsafe results.
This change replaces the SCEV arithmetic with `ConstantRange` and
its operation (`smul_fast`). If the calculation overflows,
`intersectWith(MLRange).isEmptySet()` would be false, ensures we
conservatively assume a dependence if the bounds cannot be proven
safe.
Signed-off-by: Ruoyu Qiu <cabbaken at outlook.com>
[DA] Hoist division check for early exit in weakCrossingSIVtest (NFC)
This patch moves the check that `Coeff` divides `Delta` earlier in the
function to enable an early exit. Potentially improve performance.
Signed-off-by: Ruoyu Qiu <cabbaken at outlook.com>
[DA] Consolidate the core logic of the Weak Zero SIV tests (NFCI) (#185577)
There have existed two functions `weakZeroSrcSIVtest` and
`weakZeroDstSIVtest`, which are almost identical, except for some minor
differences (e.g., the Direction to be updated). This patch consolidates
the shared core logic into a single function `weakZeroSIVtestImpl` then
calls it from both `weakZeroSrcSIVtest` and `weakZeroDstSIVtest`,
passing the appropriate parameters to handle the differences. This
reduces code duplication and improves maintainability.
[LLVM-Flang] Add support for -fdebug-info-for-profiling option (#188022)
Added support for option "-fdebug-info-for-profiling" in flang.
- When the option `-fdebug-info-for-profiling` option is passed,
compiler sets the `DebugInfoForProfiling` flag and triggers the
`AddDiscriminatorsPass`. This pass inserts additional debug metadata,
specifically discriminator values into the IR to improve the profiling
precision.
- Additionally `-add-debug-info` pass has been updated to emit an extra
field, `debugInfoForProfiling: true` inside the generated DICompileUnit
metadata node.
[lldb] Protect frame provider construction from re-entrant frame access
When a scripted frame provider calls HandleCommand or other
frame-accessing APIs during __init__, GetStackFrameList() re-enters
without the re-entrancy guard, causing infinite recursion. On Windows
(1MB default stack), this results in a stack overflow (0xC00000FD)
before Python's recursion limit can intervene.
The existing PushProviderFrameList/PopProviderFrameList guard only
protected GetFrameAtIndex calls in FetchFramesUpTo. This wraps the
CreateInstance call in LoadScriptedFrameProvider with the same guard
so that provider construction is also protected.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Fix lld/wasm/SyntheticSections.cpp after SyntheticSections.h #undef
SyntheticSections.cpp uses LLVM_DEBUG but had no #define DEBUG_TYPE,
relying on the leaked "lld" from SyntheticSections.h. Add an
explicit #define DEBUG_TYPE.
Fix lld/wasm/Relocations.cpp after SyntheticSections.h #undef
Relocations.cpp uses LLVM_DEBUG but had no #define DEBUG_TYPE,
relying on the leaked "lld" from SyntheticSections.h. Add an
explicit #define DEBUG_TYPE.
[RISCV] Add TunePreferAscendingLoadStore for SpacemiT X60 LD/ST fusion (#186967)
Add a tune feature that reverses the callee-saved register spill/restore
order so that addresses are ascending, enabling LD/ST fusion on
processors like SpacemiT X60.
Co-authored-by: LiqinWeng <liqin.weng at spacemit.com>
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
