LLVM/project 79fa36flldb/source/Plugins/Process/Linux NativeRegisterContextLinux.h, lldb/source/Plugins/Process/Utility NativeRegisterContextRegisterInfo.h

[lldb][Windows] Invalidate cached register values on thread stop (#192430)

Invalidate cached values in register context data structures on every
thread stop.

NativeRegisterContextRegisterInfo::InvalidateAllRegisters performs no
operation by default. Subclasses may override it to clear cached values
within their register context data structures whenever a thread stops.

This change intends to set up the necessary infrastructure to support
caching of the thread context in NativeRegisterContextWindows_arm64,
which will improve read performance. Currently, the thread context is
retrieved for every read or write operation.
DeltaFile
+3-0lldb/source/Plugins/Process/Windows/Common/NativeThreadWindows.cpp
+0-3lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h
+3-0lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h
+6-33 files

LLVM/project af1d9cdllvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/PhaseOrdering/X86 horizontal-reduce-smax.ll horizontal-reduce-smin.ll

Revert "[VectorCombine] foldShuffleChainsToReduce - add support for partial v…"

This reverts commit a2942d472aac907af6f47f8c7658288609b6e1de.
DeltaFile
+0-50llvm/test/Transforms/VectorCombine/fold-shuffle-chains-to-reduce.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
+32-8llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
+6-33llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+134-1156 files

LLVM/project 43ef21fllvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 store-float-conversion.ll tbl-loops.ll

[AArch64] Improve post-inc stores of SIMD/FP values

Add patterns to match post-increment truncating stores from lane 0 of
wide integer vectors (v4i32/v2i64) to narrower types (i8/i16/i32).
This avoids transferring the value through a GPR when storing.

Also remove the pre-legalization early-exit in combineStoreValueFPToInt
as it prevented the optimization from applying in some cases.
DeltaFile
+260-0llvm/test/CodeGen/AArch64/store-float-conversion.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/test/CodeGen/AArch64/tbl-loops.ll
+268-54 files

LLVM/project 53ce9fbllvm/lib/CodeGen/SelectionDAG ExpandMulByConstant.cpp, llvm/test/CodeGen/Lanai constant_multiply.ll

[TargetLowering] Add target-independent mul-by-constant expansion algorithm
DeltaFile
+176-379llvm/test/CodeGen/RISCV/mul-expand.ll
+307-0llvm/lib/CodeGen/SelectionDAG/ExpandMulByConstant.cpp
+130-164llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+88-152llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
+73-128llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+82-78llvm/test/CodeGen/Lanai/constant_multiply.ll
+856-90119 files not shown
+1,356-1,40825 files

LLVM/project 9a1da2elibcxx/include algorithm

address review comments
DeltaFile
+4-4libcxx/include/algorithm
+4-41 files

LLVM/project fd89940llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 store-float-conversion.ll tbl-loops.ll

[AArch64] Improve post-inc stores of SIMD/FP values

Add patterns to match post-increment truncating stores from lane 0 of
wide integer vectors (v4i32/v2i64) to narrower types (i8/i16/i32).
This avoids transferring the value through a GPR when storing.

Also remove the pre-legalization early-exit in combineStoreValueFPToInt
as it prevented the optimization from applying in some cases.
DeltaFile
+260-0llvm/test/CodeGen/AArch64/store-float-conversion.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/test/CodeGen/AArch64/tbl-loops.ll
+268-54 files

LLVM/project 6b9b1c2llvm/lib/Transforms/Utils LoopPeel.cpp, llvm/test/Transforms/LoopUnroll peel-last-iteration-load-widening.ll peel-last-iteration-load-widening-be.ll

Address comments 1
DeltaFile
+1,694-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening.ll
+0-616llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening.ll
+117-79llvm/lib/Transforms/Utils/LoopPeel.cpp
+0-104llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening-be.ll
+67-0llvm/test/Transforms/LoopUnroll/PowerPC/peel-last-iteration-load-widening-be.ll
+56-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening-disabled.ll
+1,934-7994 files not shown
+1,948-80910 files

LLVM/project 719b58cllvm/include/llvm/Transforms/Utils LoopPeel.h UnrollLoop.h, llvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopPeel] Peel last iteration to enable load widening

In loops that contain multiple consecutive small loads (e.g., 3 bytes
loading i8's), peeling the last iteration makes it safe to read beyond
the accessed region, enabling the use of a wider load (e.g., i32) for
all other N-1 iterations.

Patterns such as:
```
  %a = load i8, ptr %p
  %b = load i8, ptr %p+1
  %c = load i8, ptr %p+2
  ...
  %p.next = getelementptr i8, ptr %p, 3
```

Can be transformed to:
```
  %wide = load i32, ptr %p  ; Read 4 bytes

    [9 lines not shown]
DeltaFile
+616-0llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening.ll
+230-1llvm/lib/Transforms/Utils/LoopPeel.cpp
+104-0llvm/test/Transforms/LoopUnroll/peel-last-iteration-load-widening-be.ll
+19-13llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+7-1llvm/include/llvm/Transforms/Utils/LoopPeel.h
+2-1llvm/include/llvm/Transforms/Utils/UnrollLoop.h
+978-166 files

LLVM/project c522ad0clang-tools-extra/clang-tidy/readability ContainerSizeEmptyCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix FP in readability-container-size-empty with compairing to unrelated type (#190535)

Fixes https://github.com/llvm/llvm-project/issues/162287.
DeltaFile
+74-0clang-tools-extra/test/clang-tidy/checkers/readability/container-size-empty.cpp
+19-9clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp
+3-0clang-tools-extra/docs/ReleaseNotes.rst
+96-93 files

LLVM/project d66420cllvm/test/CodeGen/X86 call-range-attr.ll

update test

Co-Authored-By: nikic <github at npopov.com>
DeltaFile
+2-3llvm/test/CodeGen/X86/call-range-attr.ll
+2-31 files

LLVM/project ddfbf5dllvm/test/CodeGen/X86 call-range-attr.ll

add test
DeltaFile
+74-0llvm/test/CodeGen/X86/call-range-attr.ll
+74-01 files

LLVM/project 90c1ba7llvm/test/CodeGen/AMDGPU bit-op-reduce-width-known-bits.ll, llvm/test/CodeGen/X86 argument-range-attr.ll

update test
DeltaFile
+12-14llvm/test/CodeGen/X86/argument-range-attr.ll
+3-3llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
+15-172 files

LLVM/project 0ae088fllvm/test/CodeGen/X86 argument-range-attr.ll

add test
DeltaFile
+123-0llvm/test/CodeGen/X86/argument-range-attr.ll
+123-01 files

LLVM/project ccb3861llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp SelectionDAGBuilder.h

[SelectionDAG] Emit `AssertZext` for function argument range attributes
DeltaFile
+6-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+2-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+8-12 files

LLVM/project b3ff86bllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp SelectionDAGBuilder.cpp

[SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt
DeltaFile
+4-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+0-4llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+4-42 files

LLVM/project e535d2fllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 abds.ll

[DAGCombiner] Fix abs(add) to abdu miscompile in foldABSToABD
DeltaFile
+9-9llvm/test/CodeGen/X86/abds.ll
+1-3llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+10-122 files

LLVM/project 86ba661mlir/docs Tokens.md, mlir/lib/Conversion/AsyncToLLVM AsyncToLLVM.cpp

[mlir][IR] Add builtin `TokenTypeInterface`

type instead of type interface

add bytecode
DeltaFile
+104-0mlir/docs/Tokens.md
+60-0mlir/test/IR/token-type.mlir
+36-24mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
+18-17mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
+30-0mlir/test/lib/Dialect/Test/TestOps.td
+12-12mlir/test/Dialect/SparseTensor/invalid.mlir
+260-5324 files not shown
+365-9530 files

LLVM/project d6f6cdallvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls inttoptr-no-double-pointer.ll

[SPIR-V] Fix inttoptr type deduction with ptr.annotation (#189219)

Opaque pointer inttoptr was recording ptr as a pointee type, so
OpConvertUToPtr was emitted as pointer-to-pointer and then bitcasted
back. Please see an example below.

LLVM IR:
```
%p = inttoptr i64 %x to ptr addrspace(1)
%a = call ptr addrspace(1) @llvm.ptr.annotation(... %p ...)
call spir_func void @prefetch(ptr addrspace(1) %a, ...)
```

SPIR-V (before the change):
```
%p2 = OpConvertUToPtr %_ptr_CrossWorkgroup__ptr_CrossWorkgroup_uchar %x
%p1 = OpBitcast %_ptr_CrossWorkgroup_uchar %p2
OpFunctionCall ... %p1 ...
```

    [2 lines not shown]
DeltaFile
+37-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cache_controls/inttoptr-no-double-pointer.ll
+2-0llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+39-02 files

LLVM/project 9076fffllvm/test/CodeGen/AMDGPU ctlz_zero_undef.ll ctlz_zero_poison.ll, llvm/test/CodeGen/RISCV/rvv ctlz-vp.ll cttz-vp.ll

[DAG][GISel] Rename CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF/CTTZ_ELTS_ZERO_UNDEF -> CTTZ_ZERO_POISON/CTLZ_ZERO_POISON/CTTZ_ELTS_ZERO_POISON (#196732)

DAG/GISel are ambiguous about whether zero-input results in
UNDEF/POISON, unlike the rest of LLVM which makes it clear its POISON.

I've tried to clean this up once and for all by ensuring
SelectionDAG::canCreateUndefOrPoison does a includesPoison(Kind) check,
renaming the opcodes (including the VP variants) and updating as many
comments/tests as possible (I may still have missed some...).
DeltaFile
+0-2,614llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
+2,614-0llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
+0-1,670llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
+1,670-0llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
+153-153llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
+147-147llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+4,584-4,584127 files not shown
+7,132-7,116133 files

LLVM/project 4175ddallvm/lib/Target/AArch64 AArch64InstrInfo.cpp, llvm/unittests/Target/AArch64 InstSizes.cpp

[AArch64] Report accurate sizes for MOVaddr and MOVimm pseudos
DeltaFile
+89-0llvm/unittests/Target/AArch64/InstSizes.cpp
+25-0llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+114-02 files

LLVM/project 694c081llvm/lib/Target/AArch64 AArch64ExpandPseudoInsts.cpp AArch64ExpandImm.cpp

[NFC][AArch64] Extract MOVaddr* expansion model into common header

This makes the expansion logic reusable by getInstSizeInBytes in a
follow-up patch.
DeltaFile
+71-53llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+15-0llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
+8-1llvm/lib/Target/AArch64/AArch64ExpandImm.h
+94-543 files

LLVM/project 1558618clang-tools-extra/clang-tidy/hicpp HICPPTidyModule.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Remove hicpp module [1/4] (#194516)

This is part one of removing the `hicpp-*` checks.

RFC:
https://discourse.llvm.org/t/rfc-regarding-the-current-status-of-hicpp-checks/89883

Part of https://github.com/llvm/llvm-project/issues/183462
DeltaFile
+74-0clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value-remove.cpp
+0-72clang-tools-extra/test/clang-tidy/checkers/hicpp/ignored-remove-result.cpp
+25-13clang-tools-extra/docs/ReleaseNotes.rst
+0-34clang-tools-extra/clang-tidy/hicpp/HICPPTidyModule.cpp
+0-23clang-tools-extra/docs/clang-tidy/checks/hicpp/explicit-conversions.rst
+0-12clang-tools-extra/docs/clang-tidy/checks/hicpp/function-size.rst
+99-15411 files not shown
+100-23417 files

LLVM/project 3be2eaallvm/cmake config-ix.cmake

[cmake] use target names instead of legacy variables (#185463)

Use the [name of the imported
targets](https://cmake.org/cmake/help/latest/module/CheckSymbolExists.html)
when testing the libraries during cmake configuration. This removes the
need to also set `CMAKE_REQUIRED_INCLUDES` and
`CMAKE_REQUIRED_DEFINITIONS` and reflects more modern CMake usage where
targets are preferred over variables.

This is already the case when checking libcurl in the same file.
DeltaFile
+2-5llvm/cmake/config-ix.cmake
+2-51 files

LLVM/project 7e2821eclang/lib/Sema SemaTemplateInstantiate.cpp SemaConcept.cpp, clang/test/SemaTemplate concepts-lambda.cpp

[Clang] Transform lambda's constraints when instantiating parameter mapping (#195995)

This way we can remove a few workarounds of lambda expressions where
outer template arguments of concepts have to be preserved through
ImplicitConceptSpecializationDecls.

Fixes #193944
DeltaFile
+33-3clang/test/SemaTemplate/concepts-lambda.cpp
+32-4clang/lib/Sema/SemaTemplateInstantiate.cpp
+8-22clang/lib/Sema/SemaConcept.cpp
+12-2clang/lib/Sema/TreeTransform.h
+0-14clang/lib/Sema/SemaTemplateDeduction.cpp
+7-0clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
+92-452 files not shown
+93-528 files

LLVM/project 2d1c25bllvm/test/CodeGen/X86 argument-range-attr.ll

add test
DeltaFile
+123-0llvm/test/CodeGen/X86/argument-range-attr.ll
+123-01 files

LLVM/project e373fabllvm/test/CodeGen/AMDGPU bit-op-reduce-width-known-bits.ll, llvm/test/CodeGen/X86 argument-range-attr.ll

update test
DeltaFile
+12-14llvm/test/CodeGen/X86/argument-range-attr.ll
+3-3llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
+15-172 files

LLVM/project 5ec2116llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp SelectionDAGBuilder.h

[SelectionDAG] Emit `AssertZext` for function argument range attributes
DeltaFile
+6-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+2-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+8-12 files

LLVM/project 4cb20fellvm/test/CodeGen/X86 call-range-attr.ll

update test
DeltaFile
+2-3llvm/test/CodeGen/X86/call-range-attr.ll
+2-31 files

LLVM/project 984eef8llvm/test/CodeGen/X86 call-range-attr.ll

add test
DeltaFile
+84-0llvm/test/CodeGen/X86/call-range-attr.ll
+84-01 files

LLVM/project 4714c18llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp SelectionDAGBuilder.cpp

[SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt
DeltaFile
+4-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+0-4llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+4-42 files