LLVM/project 7687a14llvm/docs GettingInvolved.rst

[docs] Update ics for my office hours
DeltaFile
+1-1llvm/docs/GettingInvolved.rst
+1-11 files

LLVM/project c2d510fflang/include/flang/Optimizer/Builder HLFIRTools.h, flang/include/flang/Optimizer/Dialect FIROpsSupport.h

[flang] fix DIR IVDEP for array assignments inside loops (#177940)

The access attribute set on hlfir.assign for arrays was lost in
InlineHLFIRAssign.cpp. This patch propagates it to the creates loads and
stores.
DeltaFile
+22-10flang/lib/Optimizer/Builder/HLFIRTools.cpp
+20-0flang/test/Lower/ivdep-array.f90
+7-4flang/include/flang/Optimizer/Builder/HLFIRTools.h
+6-1flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
+5-0flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
+2-1flang/lib/Lower/Bridge.cpp
+62-161 files not shown
+63-177 files

LLVM/project 14cd8f0clang/lib/AST/ByteCode InterpState.h State.h

[clang][bytecode][NFC] Clean up InterpState includes (#178130)

DeltaFile
+0-7clang/lib/AST/ByteCode/InterpState.h
+1-0clang/lib/AST/ByteCode/State.h
+1-72 files

LLVM/project e3284b9llvm/lib/Transforms/Utils LowerMemIntrinsics.cpp, llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU expand-mem-intrinsics.ll

[LowerMemIntrinsics][AMDGPU] Propagate Debug Value (#178131)

Propagate debug value to expanded loops for `memcpy`, `memmove` and
`memset` intrinsics.
DeltaFile
+330-0llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll
+34-6llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp
+364-62 files

LLVM/project ba833a6mlir/include/mlir/Dialect/EmitC/Transforms Transforms.h, mlir/lib/Dialect/EmitC/IR EmitC.cpp

Revert "[mlir][emitc] Fix recurring operands in expression (#175535)"

This reverts commit 4a50d99a50ef10da020cc7de6d9f10a07398b25a.

Fails the buildbot.
DeltaFile
+0-52mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
+10-34mlir/lib/Dialect/EmitC/IR/EmitC.cpp
+1-23mlir/test/Dialect/EmitC/ops.mlir
+0-19mlir/test/Dialect/EmitC/form-expressions.mlir
+0-13mlir/test/Dialect/EmitC/invalid_ops.mlir
+0-4mlir/include/mlir/Dialect/EmitC/Transforms/Transforms.h
+11-1451 files not shown
+11-1467 files

LLVM/project b232970libcxx/include/__ranges subrange.h join_with_view.h, libcxx/test/libcxx/ranges/range.adaptors/range.join.with nodiscard.verify.cpp

[libc++][ranges] Updated `[[nodiscard]]` implementation for `subrange` and `join_with_view` (#176936)

Added or removed `[[nodiscard]]` according to the guidelines and updated
the tests.

 - https://libcxx.llvm.org/CodingGuidelines.html
 - https://wg21.link/range.subrange
 -  https://wg21.link/range.join.with.view

Towards #172124
DeltaFile
+24-65libcxx/test/libcxx/ranges/range.adaptors/range.join.with/nodiscard.verify.cpp
+75-0libcxx/test/libcxx/ranges/range.utility/range.subrange/nodiscard.verify.cpp
+5-5libcxx/include/__ranges/subrange.h
+2-3libcxx/include/__ranges/join_with_view.h
+106-734 files

LLVM/project 8488263compiler-rt/lib/builtins CMakeLists.txt, compiler-rt/lib/builtins/aarch64 sme-libc-opt-memcpy-memmove-sve.S sme-libc-opt-memcpy-memmove.S

[compiler-rt][aarch64][sme] Add SVE/FP variant of `__arm_sc_memcpy` (#127093)

When SVE is available use the `-sve` variant of memcpy from AOR for
`__arm_sc_memcpy`. From:
https://github.com/ARM-software/optimized-routines/blob/71e36403858ab3ff743fcde336fb31890e57af7e/string/aarch64/memcpy-sve.S

This implementation uses FPR/ZPR load/store instructions to do the copy,
so should not cause memory hazards if called in streaming mode (with the
memory later being accessed in the streaming mode with SVE/SME
instructions).

The implementation has been slightly modified from AOR to use local
labels (matching other compiler-rt functions) but still passes the
memcpy and memmove tests from AOR.
DeltaFile
+180-0compiler-rt/lib/builtins/aarch64/sme-libc-opt-memcpy-memmove-sve.S
+3-0compiler-rt/lib/builtins/aarch64/sme-libc-opt-memcpy-memmove.S
+1-1compiler-rt/lib/builtins/CMakeLists.txt
+184-13 files

LLVM/project c8010daclang/docs/analyzer checkers.rst

[analyzer][docs] Add basic description of checker 'core.CallAndMessage' (#177179)

The checker had very little documentation. Now a more detailed (but
still not much) description of the features and options is added.
DeltaFile
+43-1clang/docs/analyzer/checkers.rst
+43-11 files

LLVM/project 7404fdeflang/lib/Lower/OpenMP OpenMP.cpp Clauses.cpp, flang/test/Lower/OpenMP num-threads-dims.f90

[OpenMP][MLIR] Add num_threads clause with dims modifier support
DeltaFile
+61-0flang/test/Lower/OpenMP/num-threads-dims.f90
+35-4mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
+13-5mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+7-7flang/lib/Lower/OpenMP/OpenMP.cpp
+10-3flang/lib/Lower/OpenMP/Clauses.cpp
+12-0mlir/test/Dialect/OpenMP/ops.mlir
+138-195 files not shown
+165-2911 files

LLVM/project d933238clang/lib/AST/ByteCode InterpState.h

[clang][bytecode][NFC] Make InterpState::Allocator private (#178129)

DeltaFile
+2-2clang/lib/AST/ByteCode/InterpState.h
+2-21 files

LLVM/project a47b42ecmake/Modules LLVMVersion.cmake

Bump version to 22.1.0-rc2
DeltaFile
+1-1cmake/Modules/LLVMVersion.cmake
+1-11 files

LLVM/project 9d85db7flang/lib/Optimizer/OpenMP DoConcurrentConversion.cpp, flang/test/Transforms/DoConcurrent multiple_iteration_ranges.f90

[flang][OpenMP][DoConcurrent] Add `collapse` clause to generated `omp.loop_nest` op

Adds the collpase clause to the generated loop nest both on host and
device.
DeltaFile
+1-1flang/test/Transforms/DoConcurrent/multiple_iteration_ranges.f90
+2-0flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
+3-12 files

LLVM/project 4ae6d8fclang/lib/CodeGen CGStmt.cpp

Merge branch 'users/chapuni/cov/single/switch' into users/chapuni/cov/single/trunk
DeltaFile
+1-1clang/lib/CodeGen/CGStmt.cpp
+1-11 files

LLVM/project 673b883llvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx10_asm_vop1.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge branch 'users/chapuni/cov/single/binop' into users/chapuni/cov/single/trunk

Conflicts:
        clang/docs/ReleaseNotes.rst
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+4,672-4,671llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+34,743-34,7393,638 files not shown
+304,037-203,6663,644 files

LLVM/project 4de64f7clang/lib/CodeGen CGExprScalar.cpp CodeGenFunction.cpp

Use hasSkipCounter
DeltaFile
+18-18clang/lib/CodeGen/CGExprScalar.cpp
+6-7clang/lib/CodeGen/CodeGenFunction.cpp
+24-252 files

LLVM/project 3852734llvm/test/MC/AMDGPU gfx8_asm_vop3.s gfx7_asm_vop3.s, llvm/test/MC/Disassembler/AMDGPU gfx9_vop3.txt

Merge branch 'users/chapuni/cov/single/binop-base' into users/chapuni/cov/single/binop

Conflicts:
        clang/lib/CodeGen/CoverageMappingGen.cpp
DeltaFile
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+41,419-41,418llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+36,428-36,427llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+28,175-28,174llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
+22,711-22,884llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+22,276-22,275llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
+193,358-193,5266,687 files not shown
+1,508,374-1,275,5866,693 files

LLVM/project d97cfc2clang/lib/CodeGen CGStmt.cpp

Merge branch 'users/chapuni/cov/single/if' into users/chapuni/cov/single/binop-base
DeltaFile
+4-4clang/lib/CodeGen/CGStmt.cpp
+4-41 files

LLVM/project 64da410llvm/test/MC/AMDGPU gfx8_asm_vop3.s gfx7_asm_vop3.s, llvm/test/MC/Disassembler/AMDGPU gfx9_vop3.txt

Merge branch 'users/chapuni/cov/single/loop' into users/chapuni/cov/single/binop-base
DeltaFile
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+41,419-41,418llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+36,428-36,427llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+28,175-28,174llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
+22,711-22,884llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+22,276-22,275llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
+193,358-193,5266,687 files not shown
+1,508,370-1,275,5826,693 files

LLVM/project d0881c8clang/lib/CodeGen CGStmt.cpp

Use hasSkipCounter
DeltaFile
+1-1clang/lib/CodeGen/CGStmt.cpp
+1-11 files

LLVM/project 73ddb13llvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx10_asm_vop1.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge commit 'cead042fd7b57f7bb454d4ffe6f0413658a4b069' into users/chapuni/cov/single/switch
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+4,672-4,671llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+34,743-34,7393,638 files not shown
+304,003-203,6293,644 files

LLVM/project 7df15fcclang/lib/CodeGen CGStmt.cpp

Use hasSkipCounter
DeltaFile
+4-4clang/lib/CodeGen/CGStmt.cpp
+4-41 files

LLVM/project 8618e1allvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx10_asm_vop1.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge commit 'cead042fd7b57f7bb454d4ffe6f0413658a4b069' into users/chapuni/cov/single/if
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+4,672-4,671llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+34,743-34,7393,638 files not shown
+304,003-203,6293,644 files

LLVM/project 1e160c8clang/lib/CodeGen CGStmt.cpp

Use hasSkipCounter
DeltaFile
+5-7clang/lib/CodeGen/CGStmt.cpp
+5-71 files

LLVM/project c090d9cllvm/test/MC/AMDGPU gfx10_asm_vopc_e64.s gfx10_asm_vop1.s, llvm/test/MC/Disassembler/AMDGPU gfx10_vop3c.txt gfx10_vop3.txt

Merge commit 'cead042fd7b57f7bb454d4ffe6f0413658a4b069' into users/chapuni/cov/single/loop
DeltaFile
+10,845-10,844llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,425-5,424llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+4,676-4,675llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+4,672-4,671llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+34,743-34,7393,638 files not shown
+304,003-203,6293,644 files

LLVM/project 4a50d99mlir/include/mlir/Dialect/EmitC/Transforms Transforms.h, mlir/lib/Dialect/EmitC/IR EmitC.cpp

[mlir][emitc] Fix recurring operands in expression (#175535)

The pretty-printing for `emitc.expression` breaks for expressions taking
the same value as operand multiple times.

Passing the same value as operand more than once is redundant, and is
therefore not the canonical form of `emitc.expression`. However, since
transformations affecting `emitc.expression` operands may cause this to
happen, `emitc.expression` must retain its support for recurring
operands.

This PR fixes this issue by shadowing the region arguments only when the
operands are unique, printing and parsing an explicit basic block
otherwise. In addition, a canonicalization pattern removing recurring
operands is added.

Fixes https://github.com/llvm/llvm-project/issues/172952.
DeltaFile
+52-0mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
+34-10mlir/lib/Dialect/EmitC/IR/EmitC.cpp
+23-1mlir/test/Dialect/EmitC/ops.mlir
+19-0mlir/test/Dialect/EmitC/form-expressions.mlir
+13-0mlir/test/Dialect/EmitC/invalid_ops.mlir
+4-0mlir/include/mlir/Dialect/EmitC/Transforms/Transforms.h
+145-111 files not shown
+146-117 files

LLVM/project cead042clang/lib/CodeGen CodeGenFunction.h CodeGenPGO.cpp

[Coverage] Introduce the predicate `hasSkipCounter(S)`. NFC.

Also, rename s/getIsCounterPair/getExecSkipCounterExistence/.
DeltaFile
+7-1clang/lib/CodeGen/CodeGenFunction.h
+5-3clang/lib/CodeGen/CodeGenPGO.cpp
+1-1clang/lib/CodeGen/CodeGenPGO.h
+13-53 files

LLVM/project 60f4508clang/docs ReleaseNotes.rst

[LoongArch] Update release notes for LoongArch32 support
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+2-0clang/docs/ReleaseNotes.rst
+2-01 files

LLVM/project f5101f1llvm/docs ReleaseNotes.md

[LoongArch] Update release notes for LoongArch32 support
DeltaFile
+1-0llvm/docs/ReleaseNotes.md
+1-01 files

LLVM/project ad1addbflang/lib/Lower Bridge.cpp

[flang][Lower] Fix UB in location handling (#177944)

Previously `prov` received the address of a variable allocated in stack
memory (the contents of `include`). `prov` would then access that memory
outside of the lifetime of that stack allocation: leading to UB.

This only manifested on thinLTO builds. No added test because
flang/test/Lower/location.f90 covers it (when thinLTO is enabled) and
there are bots guarding the thin-lto configuration.

Fixes #156629
Fixes #176404

(cherry picked from commit 9be7c1037f26146e469c85061d6685a9172c5de9)
DeltaFile
+3-3flang/lib/Lower/Bridge.cpp
+3-31 files

LLVM/project e80b4d9llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVRegisterInfo.td, llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv select.mir

[RISCV] Add ZZZ_ to some inline assembly vector register classes to sort them after VR/VRNoV0 in regclass enum. (#177087)

This prevents getCommonSubClass from finding them before VR/VRNoV0.

Fixes a crash reported post-commit in #171231. getCommonSubClass
returned one of these classes, but it doesn't have the same VTs as
VR/VRNoV0 leading to an assertion failure.

The subregister-undef-early-clobber.mir still ends up finding these
register classes in the InitUndef pass.

(cherry picked from commit 73a309e20e92ff8e9af295c81ee74a58b07a93ba)
DeltaFile
+71-0llvm/test/CodeGen/RISCV/rvv/pr171231.ll
+13-12llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+12-12llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
+14-8llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+10-10llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir
+3-3llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+123-456 files not shown
+133-5512 files