LLVM/project 0c38b8eclang/lib/Headers __clang_cuda_math.h, clang/test/CodeGenCUDA sqrtf-precise.cu

[CUDA] Lower device sqrtf through builtin sqrt (#205661)

Lower CUDA Device `sqrtf` through `__builtin_sqrtf` instead of the
libdevice `__nv_sqrtf` wrapper.

This lets the existing NVPTX lowering for `llvm.sqrt.f32` choose between
`sqrt.rn.f32` by default and `sqrt.approx.f32` under `-fapprox-func`.

Fixes #131749

Includes tests in clang/test/CodeGenCUDA/sqrtf-precise.cu

---------

Co-authored-by: Justin Fargnoli <jfargnoli at nvidia.com>
DeltaFile
+37-0clang/test/CodeGenCUDA/sqrtf-precise.cu
+1-1clang/lib/Headers/__clang_cuda_math.h
+38-12 files

LLVM/project 93e7190llvm/lib/CodeGen/GlobalISel CombinerHelper.cpp, llvm/test/CodeGen/AArch64 shift.ll arm64-vshift.ll

[AArch64][GlobalISel] Use PreferredShiftAmountTy in TruncOfShift combine (#213381)

This trunc of shift combine has always caused issues with the shift
amount type no longer matching the new shift type. This patch changes
the type of the shift amount to at least match the
getPreferredShiftAmountTy.
DeltaFile
+8-29llvm/test/CodeGen/AArch64/arm64-vshift.ll
+2-5llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
+5-0llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+2-2llvm/test/CodeGen/AArch64/shift.ll
+2-2llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
+2-2llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
+21-406 files

LLVM/project c88aeafllvm/lib/Target/Hexagon HexagonPseudo.td HexagonAsmPrinter.cpp, llvm/test/CodeGen/Hexagon kcfi.ll kcfi-packetization.ll

[Hexagon] Fix KCFI check truncating type id (#211854)

The KCFI indirect-call check is lowered directly to MCInst in the
Hexagon AsmPrinter. It omitted the constant-extender, causing
mismatches.

Packet canonicalization is how we should apply constant extenders,
duplex, compounds, etc.

Assisted-by: Claude
DeltaFile
+193-0llvm/test/CodeGen/Hexagon/kcfi-packet-context.ll
+117-0llvm/test/CodeGen/Hexagon/kcfi-obj-vs-asm.ll
+113-0llvm/test/CodeGen/Hexagon/kcfi-packetization.ll
+32-30llvm/test/CodeGen/Hexagon/kcfi.ll
+31-8llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+3-1llvm/lib/Target/Hexagon/HexagonPseudo.td
+489-396 files

LLVM/project 9f93da9llvm/include/llvm/IR Use.h

Remove extra semi-colon; NFC (#215604)
DeltaFile
+1-1llvm/include/llvm/IR/Use.h
+1-11 files

LLVM/project 2242caaclang/lib/CodeGen/Targets SPIR.cpp, clang/test/CodeGenCUDA amdgpu-kernel-attrs.cu

clang/SPIRV: Respect __launch_bounds__ for AMDHIP case

Follow the somewhat dodgy logic for packing amdgpu_flat_work_group_size
into the X field of max_work_group_size if the value is provided
to __launch_bounds__. The explicit amdgpu_flat_work_group_size takes
precedence, like in the AMDGPU case.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+6-1clang/lib/CodeGen/Targets/SPIR.cpp
+6-0clang/test/CodeGenCUDA/amdgpu-kernel-attrs.cu
+12-12 files

LLVM/project 73f6e56clang/lib/CodeGen/Targets AMDGPU.cpp, clang/lib/Sema SemaDeclAttr.cpp

clang/AMDGPU: Respect __launch_bounds__ attribute

Currently the HIP headers manually implement this with a
macro setting amdgpu attributes, and the proper clang attribute
is silently ignored. Directly map the proper attribute into
the target IR attributes. The first argument sets
"amdgpu-flat-work-group-size" and the second  (reinterpreted by HIP
as minimum waves per EU) sets "amdgpu-waves-per-eu". An explicit
amdgpu_flat_work_group_size / amdgpu_waves_per_eu attribute takes
precedence. This matches the launch_bounds macro in the HIP headers,
which can now be dropped.

The 3rd maxclusterrank argument is only handled for NVPTX, so restrict
the sm_90 arch check to NVPTX targets and ignore the third argument on
other targets.

Fixes #91468

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+31-0clang/test/CodeGenCUDA/amdgpu-kernel-attrs.cu
+28-1clang/lib/CodeGen/Targets/AMDGPU.cpp
+17-6clang/lib/Sema/SemaDeclAttr.cpp
+16-0clang/test/SemaCUDA/launch_bounds_amdgpu.cu
+92-74 files

LLVM/project 38607declang/include/clang/Analysis/Analyses/LifetimeSafety LifetimeAnnotations.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp LifetimeAnnotations.cpp

[Lifetime Safety] Highlight lifetimebound calls in alias chain diagnostics (#206337)

## Summary

This improves Lifetime Safety alias-chain diagnostics by explaining when
an aliasing step comes from a `[[clang::lifetimebound]]` contract.

For example:
```cpp
int *identity(int *p [[clang::lifetimebound]]) {
  return p;
}

void test() {
  int *q;
  {
    int i;
    q = identity(&i);
  }

    [17 lines not shown]
DeltaFile
+90-78clang/test/Sema/LifetimeSafety/safety.cpp
+44-44clang/test/Sema/LifetimeSafety/nocfg.cpp
+87-0clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
+15-49clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+26-6clang/lib/Sema/SemaLifetimeSafety.h
+27-0clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
+289-1773 files not shown
+300-1869 files

LLVM/project 277764fllvm/lib/Transforms/AggressiveInstCombine TruncInstCombine.cpp, llvm/test/Transforms/AggressiveInstCombine trunc_vector_instrs.ll

[AggressiveInstCombine] Bail out if irreducible uses exist (#215573)

Fixes #213688.
For the case below:
```llvm
define i8 @insert_index_is_reduced_value() {
  %cast = trunc i64 0 to i32
  %vecins = insertelement <1 x i32> zeroinitializer, i32 %cast, i32 %cast
  %vecext = extractelement <1 x i32> %vecins, i32 0
  %trunc = trunc i32 %vecext to i8
  ret i8 %trunc
}
```
We do not currently consider the index operand of insertelement
reducible. So `%vecins = insertelement <1 x i32> zeroinitializer, i32
%cast, i32 %cast` cannot be reduced without duplicating `%cast = trunc
i64 0 to i32`. In this case, we should reject the reduction.

Assisted-by: Codex
DeltaFile
+24-20llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
+16-0llvm/test/Transforms/AggressiveInstCombine/trunc_vector_instrs.ll
+40-202 files

LLVM/project e902871clang/docs InternalsManual.md CMakeLists.txt, clang/include/clang/Basic AttrDocs.td

[clang][docs] Finish Markdown AttrDocs migration
DeltaFile
+500-518clang/include/clang/Basic/AttrDocs.td
+21-14clang/utils/TableGen/ClangAttrEmitter.cpp
+2-2clang/docs/InternalsManual.md
+2-2clang/docs/CMakeLists.txt
+1-1llvm/docs/TableGen/BackEnds.rst
+526-5375 files

LLVM/project d10eb99mlir/lib/Dialect/OpenACC/Transforms ACCImplicitData.cpp, mlir/test/Dialect/OpenACC acc-implicit-data.mlir

Revert "[mlir][acc] Fold present() clauses on device values" (#215610)

Reverts llvm/llvm-project#212815

Managed memory array may still be in the present table, but are
classified as device memory in this pass, erroneously removing the
present clause.
DeltaFile
+20-56mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
+0-46mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
+20-1022 files

LLVM/project 290bdc3clang/include/clang/Basic AttrDocs.td

[clang][docs] Convert AttrDocs.td with rst2myst
DeltaFile
+4,273-4,314clang/include/clang/Basic/AttrDocs.td
+4,273-4,3141 files

LLVM/project 9c2156cclang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedXor.hlsl RWByteAddressBuffer-InterlockedOr.hlsl

[HLSL] Use the right memory scope on atomic instructions (#214592)

Atomic instructions have incorrect memory scope, and spirv-val diagnoses
with validation errors.
The memory scope is left unassigned (OpConstantNull) and is scopeless,
and so it is interpreted as `CrossDevice`.
Instead, we need the scope to be `Workgroup` if the atomic is operating
on a groupshared variable, or `Device` otherwise.
This PR changes the memory scope assignment to be one of the two legal
choices, rather than leaving the scope unset and the resulting value
being interpreted to the illegal `CrossDevice` variant.
Regression test was added to verify this scope operand is set.

spirv-val will still fail due to one more issue, but it is out of scope
and is left to a separate PR.

Assisted by: Github Copilot
Fixes: https://github.com/llvm/llvm-project/issues/214591
DeltaFile
+13-13clang/test/CodeGenHLSL/builtins/InterlockedXor.hlsl
+12-12clang/test/CodeGenHLSL/builtins/InterlockedOr.hlsl
+12-12clang/test/CodeGenHLSL/builtins/InterlockedAdd.hlsl
+17-0clang/test/CodeGenHLSL/builtins/InterlockedOr-SPIRV-scope.hlsl
+8-8clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedXor.hlsl
+8-8clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedOr.hlsl
+70-536 files not shown
+105-8012 files

LLVM/project e49259fllvm/lib/Target/Hexagon HexagonEarlyIfConv.cpp, llvm/test/CodeGen/Hexagon early-if-duplicate.mir

[Hexagon] Clang throws "Assertion `Inc.size() <= 2' failed" (#212913)

Adding a check in EarlyIfConv.cpp to consider whether one of SplitB,
TrueB, or FalseB appears in multiple operands to a phi in JoinB. If one
does, we do not consider it valid for if conversion.

A PHI may legitimately have more than one operand for the same incoming
block, and a single MUX cannot represent it. Without assertions enabled
the pattern was converted anyway and updatePhiNodes() silently kept only
one of the duplicated values, so the test checks that the flow pattern
is left unconverted rather than checking for the assertion.

Co-authored-by: John Wallace <johnwall at quicinc.com>
DeltaFile
+32-0llvm/test/CodeGen/Hexagon/early-if-duplicate.mir
+14-0llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+46-02 files

LLVM/project f9d6befclang/lib/CodeGen CGHLSLRuntime.cpp, clang/test/CodeGenHLSL/semantics semantic.array.output.hlsl semantic.struct.output.hlsl

[HLSL][DirectX] Correct codegen of `dx.load.input`/`dx.store.output` intrinsic calls (#212656)

This pr updates the placeholder calls with their correctly computed
operands. It also removes unused operands from the intrinsic.

Note: this doesn't account for a matrix type as the leaf type as this is
blocked on a resolution to
https://github.com/llvm/llvm-project/issues/211977. This is tracked
separately.

Each call will be emit per register row, it is then the job of the
scalarizer to ensure the element relative column is updated correctly.
This means that this col will always be assigned 0 at codegen time.

Resolves #204876

Assisted by: Claude Opus 4.8 and GPT 5.6 Sol
DeltaFile
+134-30clang/lib/CodeGen/CGHLSLRuntime.cpp
+56-0clang/test/CodeGenHLSL/semantics/semantic.output.hlsl
+53-0clang/test/CodeGenHLSL/semantics/semantic.input.hlsl
+18-18clang/test/CodeGenHLSL/semantics/semantic.struct.output.hlsl
+12-16llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
+15-12clang/test/CodeGenHLSL/semantics/semantic.array.output.hlsl
+288-7615 files not shown
+400-15721 files

LLVM/project 19d6e63mlir/lib/Dialect/OpenACC/Transforms ACCImplicitData.cpp, mlir/test/Dialect/OpenACC acc-implicit-data.mlir

Revert "[mlir][acc] Fold present() clauses on device values (#212815)"

This reverts commit c405fd3870aadfce5a9cf1a13f0da8aaeb8d3854.
DeltaFile
+20-56mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
+0-46mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
+20-1022 files

LLVM/project 1cc909dlldb/packages/Python/lldbsuite/test lldbinline.py decorators.py

[lldb][test] Give each inline test its own function object (#215400)

`MakeInlineTest` handed every generated test class the one shared
`InlineTest._test` function object, and several decorators record their
state on the function object they are handed rather than on a wrapper.
Some tests would mutate this state, causing some tests to unexpectedly
run with decorators thei weren't annotated with.

Assisted-by: Claude
DeltaFile
+14-0lldb/packages/Python/lldbsuite/test/decorators.py
+3-1lldb/packages/Python/lldbsuite/test/lldbinline.py
+17-12 files

LLVM/project 2894595llvm/lib/Target/NVPTX NVPTXPassRegistry.def NVPTXTargetMachine.cpp

[NVPTX] Add NewPM boilerplate to NVPTXLowerUnreachable (#215324)
DeltaFile
+52-35llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp
+15-3llvm/lib/Target/NVPTX/NVPTX.h
+3-3llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+3-0llvm/lib/Target/NVPTX/NVPTXPassRegistry.def
+73-414 files

LLVM/project 14bb8e3llvm/lib/Target/NVPTX NVPTXPassRegistry.def NVPTXTargetMachine.cpp

[NVPTX] Add NewPM boilerplate to NVPTXAtomicLower (#215322)
DeltaFile
+32-26llvm/lib/Target/NVPTX/NVPTXAtomicLower.cpp
+0-22llvm/lib/Target/NVPTX/NVPTXAtomicLower.h
+8-1llvm/lib/Target/NVPTX/NVPTX.h
+2-3llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+1-0llvm/lib/Target/NVPTX/NVPTXPassRegistry.def
+43-525 files

LLVM/project c907406llvm/lib/Target/NVPTX NVPTXPassRegistry.def NVPTXTargetMachine.cpp

[NVPTX] Add NewPM boilerplate to NVPTXImageOptimizer (#215133)
DeltaFile
+33-21llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
+7-1llvm/lib/Target/NVPTX/NVPTX.h
+1-1llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+1-0llvm/lib/Target/NVPTX/NVPTXPassRegistry.def
+42-234 files

LLVM/project 80c3b73clang/test/CodeGen/LoongArch/lasx builtin.c builtin-alias.c, llvm/test/CodeGen/AMDGPU float-to-arbitrary-fp-widen.ll

rebase

Created using spr 1.3.7
DeltaFile
+13,767-6,856llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-sve-instructions.s
+6,347-3,146llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-neon-instructions.s
+5,067-2,506llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-basic-instructions.s
+2,728-2,728clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+2,724-2,724clang/test/CodeGen/LoongArch/lasx/builtin.c
+3,763-0llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+34,396-17,9601,637 files not shown
+92,167-43,6341,643 files

LLVM/project 72e27b6clang/docs/HLSL ResourceTypes.rst, clang/include/clang/Basic Attr.td AttrDocs.td

[HLSL] Document all spellable attributes (#213346)

This adds documentation for all of the hlsl-specific attributes that are
user spellable.

The `branch` and `flatten` control flow hints are user facing, and I've
updated
the docs to describe what they do and refer to MSDN documentation.

The various resource handle related attributes are clang implementation
details. I've improved the clang docs for these and referred back to
there from
the attribute docs themselves.

Resolves llvm/llvm-project#211340
DeltaFile
+139-0clang/include/clang/Basic/AttrDocs.td
+39-12clang/docs/HLSL/ResourceTypes.rst
+24-24clang/include/clang/Basic/Attr.td
+3-3clang/lib/Sema/SemaHLSL.cpp
+1-1clang/lib/Sema/SemaType.cpp
+1-1clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+207-411 files not shown
+208-427 files

LLVM/project 6335f40lldb/source/Plugins/Platform/Windows PlatformWindows.cpp

[lldb][Windows] Derive the loader one-thread timeout from settings (#215593)

Timeouts always lead to hard to debug behavior on slow bots. Instead of
hard coding the value, use half of
`target.process.utility-expression-timeout` instead, which is the same
split `RunThreadPlan` applies when no one-thread timeout is set.
That setting is already the one used for LLDB internal utility
expressions: it can be set by the user and its default is raised from
15s to 60s in sanitized builds.
DeltaFile
+5-5lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
+5-51 files

LLVM/project 08c8112libc/cmake/modules LLVMLibCTestRules.cmake, libc/src/math/docs add_math_function.md

[libc] Run tests in matching build configurations only (#215333)

This patch sets it up so that unit tests only run in overlay mode (this
is the new change), while hermetic tests only run in the full build mode
(this has always been the case). Running the unit tests in full build
mode was an inconsistent configuration because we were building code
that expects to be run with our own startup code, but then we did not
link that into the unit test.

With this change, it does not make much sense to distinguish between
unit and hermetic tests, as one can think of it just as a "test", which
runs using whatever is the current build configuration. As such, this
patch removes the use of the unit/hermetic test terminology from the
most obvious place -- the add_libc_test macro. UNIT_TEST_ONLY and
HERMETIC_TEST_ONLY are replaced by OVERLAY_BUILD_ONLY and
FULL_BUILD_ONLY, respectively. Since there will only ever be one kind of
a test in a given build, the tests also lose the __unit__ and
__hermetic__ suffixes.


    [3 lines not shown]
DeltaFile
+16-21libc/cmake/modules/LLVMLibCTestRules.cmake
+8-8libc/test/src/CMakeLists.txt
+6-6libc/src/math/docs/add_math_function.md
+0-9libc/test/src/stdio/CMakeLists.txt
+3-6libc/utils/libctest/format.py
+2-6libc/test/CMakeLists.txt
+35-5610 files not shown
+42-7316 files

LLVM/project 7e8f40blibc/src/__support/CPP expected.h, libc/src/__support/OSUtil/linux/stat stat_via_statx.h

[libc] Implement expected<void, E> and use it in internal utilities (#215020)

Add the expected<void, E> partial template specialization to support
functions that return an error on failure and nothing on success,
matching std::expected<void, E>.

I've used this to resolve a TODO in if_nameindex and converted a few
other simple internal functions (pwd_utils::open/close,
update_from_seconds, stat_via_statx).

Assisted by Gemini.
DeltaFile
+62-0libc/test/src/__support/CPP/expected_test.cpp
+23-0libc/src/__support/CPP/expected.h
+5-5libc/src/__support/OSUtil/linux/stat/stat_via_statx.h
+4-4libc/src/pwd/pwd_utils.cpp
+3-4libc/src/net/linux/if_nameindex_impl.h
+2-2libc/src/time/time_utils.h
+99-155 files not shown
+106-2211 files

LLVM/project 64285f6mlir/include/mlir/Interfaces IndexingMapOpInterface.h

[mlir] Remove dead declaration verifyIndexingMapOpInterface (#215478)

The declaration was added on June 23, 2025 in commit
d31ba5256327d30f264c2f671bf197877b242cde without a corresponding
function definition.
DeltaFile
+0-7mlir/include/mlir/Interfaces/IndexingMapOpInterface.h
+0-71 files

LLVM/project ff1bb9butils/bazel/llvm-project-overlay/libc BUILD.bazel

Revert "[libc][bazel] Remove full-build dependency from __support_libc_assert" (#215601)

Reverts llvm/llvm-project#215588

it is breaking other libc tests
DeltaFile
+3-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+3-01 files

LLVM/project fd615b6llvm/test/CodeGen/AMDGPU merge-tbuffer-gfx12.mir merge-tbuffer-gfx10.mir

Remove dummy function
DeltaFile
+189-332llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
+127-232llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
+127-231llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
+127-231llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
+570-1,0264 files

LLVM/project 10936a1llvm/lib/Target/AMDGPU SILoadStoreOptimizer.cpp, llvm/test/CodeGen/AMDGPU merge-tbuffer-gfx12.mir merge-tbuffer-gfx10.mir

[AMDGPU] Gate TBUFFER merging on relaxed OOB mode
DeltaFile
+75-0llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
+57-0llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
+56-0llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
+56-0llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
+6-0llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+250-05 files

LLVM/project 9afe775llvm/lib/Target/RISCV RISCVZacasABIFix.cpp

[RISCV] Fix -Wunused-variable in #214866 (#215581)

ST was unused (outside of assertions) as a class member, and it turns
out we can just make the implementation common for what the ST is
actually used for.
DeltaFile
+4-3llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+4-31 files

LLVM/project a558267compiler-rt/lib/scudo/standalone wrappers_c.cpp

[scudo] Remove malloc_enable_child from API. (#215439)

The malloc_enable_child does not need to be a public API, instead move
the function to be static and reference it that way.
DeltaFile
+3-4compiler-rt/lib/scudo/standalone/wrappers_c.cpp
+3-41 files