LLVM/project b6fcf55 — clang-tools-extra/clang-tidy/bugprone UnusedLocalNonTrivialVariableCheck.cpp, clang-tools-extra/clang-tidy/cppcoreguidelines InitVariablesCheck.cpp

[clang-tidy][NFC] Move isLocalVarDecl matcher into utils::Matchers (#228544)

The second commit of Matcher cleanup in Clang-tidy

AI Usage: Assisted by Grok 4.6 (Cursor)

---------

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+5-9clang-tools-extra/clang-tidy/google/GlobalVariableDeclarationCheck.cpp
+2-4clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
+3-3clang-tools-extra/clang-tidy/llvm/PreferStaticOverAnonymousNamespaceCheck.cpp
+2-1clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
+2-0clang-tools-extra/clang-tidy/utils/Matchers.h
+0-1clang-tools-extra/clang-tidy/bugprone/UnusedLocalNonTrivialVariableCheck.cpp
+14-186 files

LLVM/project 99b3efc — llvm/include/llvm/Transforms/Vectorize LoopVectorizationLegality.h, llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanTransforms.cpp

Fixups
DeltaFile
+75-0llvm/test/Transforms/LoopVectorize/compress-idioms.ll
+8-5llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1-1llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+85-74 files

LLVM/project f9b9d02 — llvm/lib/AsmParser LLParser.cpp

Simplify further, clang-format
DeltaFile
+23-48llvm/lib/AsmParser/LLParser.cpp
+23-481 files

LLVM/project 63f3660 — llvm/lib/Transforms/Scalar SROA.cpp, llvm/test/Transforms/SROA phi-and-select.ll select-load.ll

[SROA] Speculate selects through addrspacecasts (#234350)

Enable select speculation to look past addrspacecast operations.
Previously, a load or store of `addrspacecast (select c, p, q)` was not
recognized as a memory operation of the select, so SROA gave up and the
alloca was not promoted. This pattern is added for GPU targets, which
make use of multiple address spaces.

The cast is recreated on each select operand so the new accesses keep
their original pointer type. Volatile accesses still block the
transform.
DeltaFile
+277-0llvm/test/Transforms/SROA/select-load.ll
+26-6llvm/lib/Transforms/Scalar/SROA.cpp
+2-10llvm/test/Transforms/SROA/phi-and-select.ll
+305-163 files

LLVM/project 794ef53 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll amdgcn.bitcast.832bit.ll

[AMDGPU] Enable SlotIndexes compaction by default (#235806)

Add TargetRegisterInfo::shouldCompactSlotIndexes() so targets can opt
in to dropping dead SlotIndexes entries before greedy allocation, one
target at a time. An explicit -greedy-compact-slot-indexes still
overrides the target. Enable it for AMDGPU.
DeltaFile
+82,724-82,770llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+22,718-22,674llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,311-9,381llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,998-9,209llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+8,016-8,194llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+7,335-7,432llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+139,102-139,660279 files not shown
+232,294-232,827285 files

LLVM/project 83ede63 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 minbw-gep-demoted-index.ll

[SLP]Extend demoted GEP index to original type

GEP sign-extends narrow indices, so a demoted unsigned index
produced wrong addresses.

Fixes #236182

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/236791
DeltaFile
+8-4llvm/test/Transforms/SLPVectorizer/X86/minbw-gep-demoted-index.ll
+7-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+15-42 files

LLVM/project 65becfc — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 minbw-gep-demoted-index.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+8-4llvm/test/Transforms/SLPVectorizer/X86/minbw-gep-demoted-index.ll
+7-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+15-42 files

LLVM/project cceded7 — llvm/lib/Target/AMDGPU AMDGPUCoExecInfo.h, llvm/unittests/Target/AMDGPU MFMACoExecRules.cpp

[AMDGPU] Address review: note MI308X with PTL off, test 32x32 SMFMAC

Say in getVALUIssueCycle's comment which gfx942 parts the helpers model:
MI300X, which has no limiter setting, and MI308X with the peak TOPS
limiter enabled. With the limiter disabled, MI308X holds VALU until an
XDL's passes end.

Add v_smfmac_f32_32x32x16_f16 to the gfx942 and gfx950 issue cycle
tests. Measured with ATT on MI308X (limiter enabled) and MI350X: VALU at
cycle 2 and PK_F32 at cycle 10.
DeltaFile
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecInfo.h
+2-0llvm/unittests/Target/AMDGPU/MFMACoExecRules.cpp
+6-32 files

LLVM/project 2a52fb1 — llvm/include/llvm/AsmParser LLParser.h, llvm/lib/AsmParser LLParser.cpp

Remove some dependence on MDField, update tests
DeltaFile
+55-82llvm/lib/AsmParser/LLParser.cpp
+118-0llvm/test/Assembler/flmd-context-singleline.ll
+60-0llvm/test/Assembler/flmd-context-errors.ll
+1-15llvm/lib/IR/AsmWriter.cpp
+5-2llvm/include/llvm/AsmParser/LLParser.h
+239-995 files

LLVM/project d95056d — llvm/test/CodeGen/AMDGPU/GlobalISel regbanklegalize-unmerge-i64-v2s16.ll

[AMDGPU][GlobalISel] Add IR test for uniform i64 unmerge into i16 (#233415)

Follow-up to #232954: add an end-to-end test where RegBankLegalize
unmerges a uniform i64 into 16-bit pieces.
DeltaFile
+40-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-unmerge-i64-v2s16.ll
+40-01 files

LLVM/project 09bb8a4 — offload/liboffload/src OffloadImpl.cpp, offload/libompaccsupport device.cpp PluginManager.cpp

[Offload][Omp] Remove references to GenericKernelTy from libomptarget (#236732)

Two new properties (`KERNEL_STATIC_BLOCK_MEM_SIZE` and
`KERNEL_MAX_THREADS`) were added to query the kernel properties that
libomptarget was querying directly.

Decouple RecordReplay from `GenericKernelTy` by introducing a new
`KernelInfoTy` structure that only carries the subset of information
that RR needs.

For now, libomptarget still needs access to `DeviceImageTy` to get some
that information.

Assisted by Claude.
DeltaFile
+34-15offload/plugins-nextgen/common/include/RecordReplay.h
+16-17offload/plugins-nextgen/common/src/RecordReplay.cpp
+24-9offload/libompaccsupport/PluginManager.cpp
+10-4offload/liboffload/src/OffloadImpl.cpp
+5-6offload/libompaccsupport/device.cpp
+0-9offload/plugins-nextgen/common/include/PluginInterface.h
+89-603 files not shown
+93-629 files

LLVM/project 2528a75 — clang-tools-extra/clang-tidy/llvm RedundantCastingCheck.cpp PreferIsaOrDynCastInConditionalsCheck.cpp, clang-tools-extra/clang-tidy/misc RedundantExpressionCheck.cpp

[clang-tidy][NFC] Move isMacroID matcher into utils::Matchers (#228541)

The first part of Matcher cleanup in Clang-tidy
DeltaFile
+3-5clang-tools-extra/clang-tidy/misc/RedundantExpressionCheck.cpp
+2-4clang-tools-extra/clang-tidy/llvm/PreferIsaOrDynCastInConditionalsCheck.cpp
+2-1clang-tools-extra/clang-tidy/llvm/RedundantCastingCheck.cpp
+2-0clang-tools-extra/clang-tidy/utils/Matchers.h
+9-104 files

LLVM/project 3a2b026 — llvm/test/Transforms/SLPVectorizer/X86 minbw-gep-demoted-index.ll

[SLP][NFC]Add a test with incorrect geps index promotion, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/236788
DeltaFile
+600-0llvm/test/Transforms/SLPVectorizer/X86/minbw-gep-demoted-index.ll
+600-01 files

LLVM/project 14ba63a — libcxx/include/__memory uninitialized_algorithms.h, libcxx/test/std/containers/sequences/vector common.h

[libc++] Add __uninitialized_allocator_{fill_n,value_construct_n,move} and use them in vector (#167112)

This makes us more predictable in when we destruct elements and makes us
consistently use `__uninitialized_allocator_` throughout `vector`.

Fixes #59293

---------

Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Co-authored-by: Nikolas Klauser <nikolasklauser at berlin.de>
DeltaFile
+86-0libcxx/test/std/containers/sequences/vector/vector.capacity/resize_size_value_exceptions.pass.cpp
+82-0libcxx/test/std/containers/sequences/vector/vector.capacity/resize_size_exceptions.pass.cpp
+40-0libcxx/include/__memory/uninitialized_algorithms.h
+36-0libcxx/test/std/containers/sequences/vector/vector.modifiers/insert_iter_size_value.pass.cpp
+36-0libcxx/test/std/containers/sequences/vector/vector.cons/assign_size_value.pass.cpp
+24-0libcxx/test/std/containers/sequences/vector/common.h
+304-03 files not shown
+312-129 files

LLVM/project 09c1667 — libcxx/test/std/numerics/numarray/valarray.nonmembers/valarray.transcend tanh_valarray.pass.cpp sinh_valarray.pass.cpp

[libc++][test] Remove `XFAIL` for LLVM libc in `valarray` tests (#236629)

Now these tests pass due to completion of several math functions in LLVM
libc.
- `sinh` in 1866d4cc5634d9edb54d703f191981093b3ca51b
- `cosh` in 075a6cb1402543bc3a1dd87a8720807d35c1eacc
- `tanh` in ff9ad993c2b90a78f23b988333e05accae1147df
DeltaFile
+0-3libcxx/test/std/numerics/numarray/valarray.nonmembers/valarray.transcend/tanh_valarray.pass.cpp
+0-3libcxx/test/std/numerics/numarray/valarray.nonmembers/valarray.transcend/sinh_valarray.pass.cpp
+0-3libcxx/test/std/numerics/numarray/valarray.nonmembers/valarray.transcend/cosh_valarray.pass.cpp
+0-93 files

LLVM/project 57e4aa8 — offload/plugins-nextgen/level_zero CMakeLists.txt, offload/plugins-nextgen/level_zero/include L0Plugin.h L0Context.h

[offload][L0][NFC] Move LevelZeroPluginContextTy to L0Context.{h,cpp} (#236111)

Move `LevelZeroPluginContextTy` out of `L0Plugin.h`/`L0Plugin.cpp` into
its own `L0Context.h`/`L0Context.cpp`.

The #236105 rename (`L0ContextTy` -> `L0DriverTy`, `L0Context.*` ->
`L0Driver.*`) freed up the `L0Context` file names, so they now hold the
plugin-side context type, matching their name.

Other changes are limited to wiring:
- Add `src/L0Context.cpp` to `LEVEL_ZERO_SRC_FILES`.
- Include `L0Context.h` from `L0Plugin.h`, `L0Plugin.cpp` and
`L0Driver.cpp`
  (`L0DriverTy` owns the default `LevelZeroPluginContextTy`).

No functional change.

Assisted-by: Claude Opus 5.5

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+133-0offload/plugins-nextgen/level_zero/src/L0Context.cpp
+1-112offload/plugins-nextgen/level_zero/src/L0Plugin.cpp
+92-0offload/plugins-nextgen/level_zero/include/L0Context.h
+1-66offload/plugins-nextgen/level_zero/include/L0Plugin.h
+1-0offload/plugins-nextgen/level_zero/src/L0Driver.cpp
+1-0offload/plugins-nextgen/level_zero/CMakeLists.txt
+229-1786 files

LLVM/project 2675f61 — llvm/utils/gn/secondary/llvm/tools/llc/lib BUILD.gn

[gn] add missing deps to llvm/tools/llc/lib (#236774)

llcdriver.cpp and NewPMDriver.cpp transitively include
generated llvm/IR/Attributes.inc and
llvm/Analysis/TargetLibraryInfo.inc,
so add a dep on them.

(In CMake, it depends on  intrinsics_gen, and intrinsics_gen depends on
analysis_gen.)
DeltaFile
+5-1llvm/utils/gn/secondary/llvm/tools/llc/lib/BUILD.gn
+5-11 files

LLVM/project 4395862 — llvm amgpu-waves-per-eu.md, llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp

[AMDGPU][CodeGen] Allow remat with multiple users in multiple regions (#215598)

This relaxes one of the constraints on rematerialization candidates in
the scheduler's `PreRARematStage`. The current implementation only
allows rematerializing a register if it has users in a single region.
This allows it when a register has multiple users in multiple regions.

In such cases the register is rematerialized as many times as there are
using regions, just before the first user in each using region. The cost
model for assessing rematerialization opportunities now takes into
account that multiple new instructions may be created for each
candidate.
DeltaFile
+665-538llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
+559-167llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
+109-59llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+96-0llvm/amgpu-waves-per-eu.md
+36-25llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
+17-12llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
+1,482-8013 files not shown
+1,505-8169 files

LLVM/project 1efaf20 — clang/lib/AST Type.cpp, clang/lib/Sema SemaARM.cpp

[Clang][AArch64] Reject attempts to cast to multivector SVE ACLE types. (#236116)

Fixes https://github.com/llvm/llvm-project/issues/234170.
DeltaFile
+27-20clang/lib/Sema/SemaARM.cpp
+21-9clang/test/Sema/aarch64-sve-lax-vector-conversions.c
+4-0clang/test/Sema/attr-arm-sve-vector-bits.c
+0-2clang/lib/AST/Type.cpp
+52-314 files

LLVM/project 342acc8 — libcxxabi/src private_typeinfo.h private_typeinfo.cpp

[libc++abi] Return whether a dynamic_cast/catch search finished (#230445)

This avoids reading/writing memory in a lot of places for a simple,
commonly used flag.
DeltaFile
+227-219libcxxabi/src/private_typeinfo.cpp
+18-24libcxxabi/src/private_typeinfo.h
+245-2432 files

LLVM/project 636ef1c — lld/MachO SyntheticSections.cpp Options.td

[lld/mac] Fix comment typos to cycle bots (#236781)
DeltaFile
+1-1lld/MachO/SyntheticSections.cpp
+1-1lld/MachO/Options.td
+1-1lld/MachO/InputSection.h
+1-1lld/MachO/ICF.cpp
+1-1lld/MachO/ConcatOutputSection.cpp
+5-55 files

LLVM/project fc94f37 — llvm/include/llvm/IR IntrinsicsAArch64.td, llvm/lib/Target/AArch64 AArch64SMEInstrInfo.td AArch64ISelLowering.cpp

[AArch64] Remove unused SME intrinsics (#236707)

These intrinsics are a remnant of the initial implementation of SME in
LLVM. SME state is now handled by function attributes so these
intrinsics should not be used.
DeltaFile
+6-86llvm/test/CodeGen/AArch64/sme-peephole-opts.ll
+0-23llvm/test/CodeGen/AArch64/sme-read-write-tpidr2.ll
+0-21llvm/test/CodeGen/AArch64/sme-toggle-pstateza.ll
+0-19llvm/include/llvm/IR/IntrinsicsAArch64.td
+0-10llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+0-6llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+6-1656 files

LLVM/project 318ebd4 — llvm/include/llvm/CodeGen SDPatternMatch.h, llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp

[LLVM][SelectionDAG] Improve vector index clamping. (#235033)

Refactor clampDynamicVectorIndex to make the result more consistent
across fixed-length and scalable vectors. Originally the function
assumed Idx will be scaled by vscale when SubEC is scalable. This PR
makes things more explicit by ensuring callers first compute the real
index to be clamped.

While this makes clampDynamicVectorIndex useful in more contexts, the
existing uses remain unchanged. Those are: (1) clamping a variable index
for a single lane; and (2) clamping a constant index for a subvector.

To make (2) more explicit this PR adds the necessary assert to
getVectorSubVecPointer. Doing this allows ISD::VSCALE to be used for
scalable subvector indices, removing the need for discrete arithmetic.
This in turn allows clampDynamicVectorIndex to better support scalable
vectors by removing unecessary clamping to maintain existing code
quality.


    [2 lines not shown]
DeltaFile
+33-44llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
+32-29llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+24-30llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
+20-28llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
+17-25llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
+32-0llvm/include/llvm/CodeGen/SDPatternMatch.h
+158-1567 files not shown
+212-22413 files

LLVM/project 4d3ebe4 — llvm/utils/gn/secondary BUILD.gn, llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn] port 749d82099196 (#236771)

Uses len(), which needs GN version 2281 or newer, so bump the
minimum GN version to that.

(Run `llvm/utils/gn/get.py` to update your GN binary.)
DeltaFile
+6-2llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+3-3llvm/utils/gn/secondary/BUILD.gn
+9-52 files

LLVM/project c8e96bc — mlir/lib/Dialect/OpenACC/IR OpenACC.cpp, mlir/test/Dialect/OpenACC canonicalize.mlir

[mlir][OpenACC] Fold constant-false host_data with an empty region (#236052)

`RemoveConstantIfConditionWithRegion` replaces a construct whose `if`
condition is constant false with the contents of its region. The helper
it uses asserts that the region has exactly one block, but
`acc.host_data` accepts an empty region, so canonicalizing one crashed.

An empty region has nothing to inline, so the op is now simply erased in
that case, which matches what happens for a non-empty region.
Multi-block regions now bail out instead of asserting.

Fixes #231828
DeltaFile
+17-3mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+17-0mlir/test/Dialect/OpenACC/canonicalize.mlir
+34-32 files

LLVM/project 816d82c — mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

clang-format
DeltaFile
+0-1mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+0-11 files

LLVM/project 312d6b9 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer logical-ops-poisonous-repeated.ll bool-logical-op-reduction-with-poison.ll

[SLP]Keep original order of poisonous values in logical reductions

Logical and/or ops mask the poison of a reduced value by all preceding
values. Repeated values, constants and leftovers were combined out of
order, and an operand-0 leaf was assumed unconditional. Combine only
non-poisonous parts out of order; emit poisonous scalars after them,
sorted by original position, with repeated values dropped.

Fixes #236181

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/236778
DeltaFile
+51-84llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+16-24llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
+15-20llvm/test/Transforms/SLPVectorizer/X86/logical-reduction-poison-order.ll
+4-8llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
+2-3llvm/test/Transforms/SLPVectorizer/logical-ops-poisonous-repeated.ll
+2-3llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll
+90-1421 files not shown
+91-1437 files

LLVM/project 28be5fe — llvm/utils/gn/secondary/compiler-rt/lib/asan BUILD.gn, llvm/utils/gn/secondary/compiler-rt/lib/tsan/rtl BUILD.gn

[gn] port 2e7d07a33725 (#236775)
DeltaFile
+1-0llvm/utils/gn/secondary/compiler-rt/lib/ubsan/BUILD.gn
+1-0llvm/utils/gn/secondary/compiler-rt/lib/tsan/rtl/BUILD.gn
+1-0llvm/utils/gn/secondary/compiler-rt/lib/asan/BUILD.gn
+3-03 files

LLVM/project 0016fcc — llvm/utils/gn/secondary/llvm/lib/Target/AVR BUILD.gn

[gn] port faba310ff3e7 (#236773)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
+1-01 files

LLVM/project fa0b3ab — llvm/utils/gn/secondary/lldb/include/lldb/Host BUILD.gn

[gn] port 6c21fa19aa4b (#236772)
DeltaFile
+1-0llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
+1-01 files