[orc-rt] Add TaskGroup::TokenSource; drop raw group accessor (#210240)
Session::managedCodeTaskGroup() returned the raw
std::shared_ptr<TaskGroup> for the managed-code group, exposing the
group's full interface -- including close() and addOnComplete() -- to
callers, even though those operations are reserved for the Session.
Add TaskGroup::TokenSource, a strong handle whose sole role is to serve
as an argument to the TaskGroup::Token constructor. Session now exposes
managedCodeTokenSource() in its place, so clients can acquire tokens (to
keep managed code alive across shutdown) without gaining the ability to
close the group or register completion callbacks.
[SLP][modularisation][NFC] Extract mask, shuffle and AA helpers into SLUtils 3/3 (#209973)
Move the mask/shuffle construction and alias-analysis free helpers out
of SLPVectorizer.cpp into SLPVectorizer/SLPUtils.{h,cpp} (namespace
llvm::slpvectorizer).
Moved:
transformScalarShuffleIndiciesToVector
getShufflevectorNumGroups
calculateShufflevectorMask
UseMask (enum)
buildUseMask
isUndefVector
doesInTreeUserNeedToExtract
getLocation
isSimple
addMask
fixupOrderingIndices
getAltInstrMask
[2 lines not shown]
workflows: Fixes for release-binaries and upload-release-artifact (#209246)
There were some bugs in upload-release-artifact workflow and
release-binaries was not including this action in its checkout.
[flang][cuda] Managed backing for -gpu=unified allocatables/pointers (#210149)
Under `-gpu=unified`, allocatables and pointers with no explicit CUDA data
attribute must be reachable from the device. Back them with CUDA managed
memory by selecting the unified allocator index at the ALLOCATE site (in
lowering), instead of stamping an implicit `Unified`/`Managed` CUDA data attribute
on the symbol in the frontend — the approach introduced in PR #209292.
This is necessary because attributing the symbol in the frontend routed every
plain allocatable/pointer through the CUDA Fortran managed descriptor
pipeline (constructor registration, `cuf.allocate`/`cuf.free`), which added
per-`ALLOCATE` overhead, forced special-casing for objects that may not legally carry a
CUDA attribute (COMMON members, derived-type components, module globals), and
changed symbol semantics used well beyond allocation. Choosing the allocator
index at the `ALLOCATE` site keeps the object a plain host allocatable/pointer while
the storage still comes from the managed allocator.
[flang][OpenMP] Check DEFAULT(NONE) on metadirective loop variants
Standalone metadirectives and their associated loops are separate parse-tree
nodes. For example:
```fortran
!$omp metadirective &
!$omp& when(implementation={vendor(llvm)}: &
!$omp& parallel do default(none) shared(n, a)) default(nothing)
do i = 1, n
a(i) = x
end do
```
Unlike an ordinary PARALLEL DO, the loop is not nested under the directive:
```text
METADIRECTIVE
`-- WHEN
[15 lines not shown]
[ObjectYAML][NFC] Hoist BBAddrMap yaml2obj encoder into a shared helper (#205991)
Preparatory NFC refactor to let the upcoming COFF emitter reuse the
BBAddrMap YAML encoder.
[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic
The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.
Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:
- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
Operations use APInt arithmetic at WideBits, chosen to guarantee no
intermediate overflow:
$$
WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
$$
This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
extra bits.
[15 lines not shown]
[LoongArch] Fix invalid VEXTH combines for unsupported type extensions (#209725)
`performEXTENDCombine` could form `VEXTH`/`VEXTH_U` nodes for
unsupported type combinations, such as extending `v8i8` to `v8i32` or
`v2i64` to `v2i128`. These illegal nodes would later reach instruction
selection and trigger backend failures:
* `Cannot select: LoongArchISD::VEXTH`
* `Don't know how to legalize this operation`
Prevent these combines from firing by verifying that the destination
type is legal and has exactly twice the total bit width of the source
before forming a `VEXTH`/`VEXTH_U` node.
Apply the same checks to `performSHLCombine` for consistency.
Fixes
https://github.com/llvm/llvm-project/pull/207316#issuecomment-4978234865
Fixes
https://github.com/llvm/llvm-project/pull/207316#issuecomment-4979233899
[GVN][NFC] Use LoadInst::getProperties() when creating PRE load (#208605)
Use load's properties via getProperties() instead of individually
forwarding isVolatile(), getAlign(), getOrdering() and getSyncScopeID().
Reference: https://github.com/llvm/llvm-project/pull/206470
[NFC] Reuse DwarfExpression fragment (#210181)
Reuse DwarfExpression fragment information since nothing changes it
between the outside of the loop and the inside of the loop.
Tested via make check.
Assisted by AI.
[clang][CodeGen][X86_64] Honor per-function AVX ABI in C/C++ call paths, maintain old psABI for PlayStation. (#193298)
Fixes https://github.com/llvm/llvm-project/issues/64706
Wire per function x86 AVX ABI level into CodeGen arrangement methods so
__attribute(__target("avx"))) / __attribute(__target("avx512f"))) on
methods, ctors, and free-functions affects ABI lowering consistently.
Specifically:
- Added X86AVXABILevel member to CGFunctionInfo.
- Populated X86AVXABILevel member in CGFunctionInfo objects via
arrangement methods declared in CodeGenTypes.h.
- Respect CGFunctionInfo AVX Level in X86_64ABIInfo::computeInfo.
- Add/extend regression tests for:
- free-function target-attribute AVX ABI lowering
- C++ method/ctor target-attribute AVX ABI lowering
- PS4/PS5 legacy ABI behavior (no per-function AVX ABI change)
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
[AArch64][SVE] Support lowering masked loads/stores of <4 x bf16> and <8 x bf16> (#208744)
Add support for lowering masked loads/stores of <4 x bf16> and <8 x
bf16> when target features contain "+sve" and "+bf16".
Fixes: #201149
