[ORC] Call Perf/VTune support wrappers through Proxies (#226677)
Hold PerfSupportPlugin's start/end registration wrappers and
VTuneSupportPlugin's unregister wrapper as Proxy members, replacing
their callSPSWrapper calls. Each proxy is built in the constructor from
the address it already takes, so the constructor signatures are
unchanged. The Perf impl and VTune register wrappers are only used as
alloc-action tags and stay ExecutorAddrs.
[clang] Unique NamespaceAndPrefixStorages with a UniquingSet (NFC) (#224221)
This patch migrates NamespaceAndPrefixStorages in ASTContext from
llvm::FoldingSet to llvm::UniquingSet.
NamespaceAndPrefixStorage keys on a pair of const NamespaceBaseDecl *
and NestedNameSpecifier. Switching to UniquingSet allows us to look
up storages with a typed key, eliminating FoldingSetNodeID
serialization at lookup sites and removing
NamespaceAndPrefixStorage::Profile.
Assisted-by: Antigravity
[AMDGPU] Price scalar integer to fp casts by source width and sign
Scalar sources between a byte and 31 bits fell to the default cost of one
while the matching vector lanes were already priced, which skewed the
difference SLP weighs a bundle against. Such a source is extended before
the conversion, and what the extension takes depends on the width, on the
sign and on whether the subtarget has SDWA and 16 bit instructions.
Sources narrower than a byte are left alone, because their vector form is
not priced either.
[AMDGPU] Price narrow integer to bfloat vector casts
A vector lane of 9 to 15 or 17 to 31 bits converted to bfloat got the
generic cost, which leaves out the rounding. Such a lane is converted to
f32 first like any other narrow lane, so price it as the f32 conversion of
the same source plus the rounding. Lanes of 8 and 16 bits keep their cost.
[AMDGPU] Model the cost of the expanded integer to/from floating point casts
No instruction converts to or from a 64 bit integer, and narrow vector
lanes are converted one at a time. Price these expansions by the FP64
rate, sdwa and 16 bit instruction support, and price i33 to i63 like
i64 and bf16 like f32 plus rounding.
Assisted-by: Claude Code Opus 5
[NFC][AMDGPU] Add cost tests for narrow integer to fp casts
Covers integer sources from a byte to 31 bits converted to half, float,
bfloat and double, as vector lanes and as scalars, over the subtarget
combinations that change the expansion. The existing cast tests get the
same subtarget coverage and the cases they were missing. The costs
recorded here are the ones the model reports today.
[LV] Remove EpilogueLoopVectorizationInfo::EpilogueUF (NFC). (#226792)
The epilogue vector loop is always unrolled by 1: the only construction
site passes 1 and the constructor asserted it. Drop the field and use 1
directly at its users, and drop the now always 1 EpilogueUF parameter of
addMinimumVectorEpilogueIterationCheck.
Clean-up in preparation for removing/simplifying
EpilogueLoopVectorizationInfo.
CodeGen: Merge TargetLoweringObjectFile::getModuleMetadata into Initialize
getModuleMetadata had a single caller, which invoked it immediately after
Initialize. Pass the module to Initialize and fold it in.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
CodeGen: Initialize TargetLoweringObjectFile from MachineModuleInfo
MachineModuleInfo passes TLOF to the MCContext the TargetLoweringObjectFile
but nothing initialized it until the AsmPrinter pass ran, so every codegen pass
in between saw it uninitialized. Initialize it from MachineModuleInfo, and drop
the calls llc and SPIRVTranslate used to work around this.
SPIRVTranslate's MachineModuleInfoWrapperPass was never passed on to
addPassesToEmitFile, so it was initializing a throwaway context.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
[unittests] Fix a recent test on Windows with LLVM_WINDOWS_PREFER_FORWARD_SLASH (#224963)
This fixes errors like these:
```
Expected equality of these values:
Context.Path
Which is: "D:/a/llvm-mingw/llvm-mingw/llvm-project/build/unittests/Support/LLVMToolSession/./LLVMToolSessionTests.exe"
ExecutablePath.c_str()
Which is: "D:\\a\\llvm-mingw\\llvm-mingw\\llvm-project\\build\\unittests\\Support\\LLVMToolSession\\.\\LLVMToolSessionTests.exe"
```
[DenseMap] Share rehash and grow for relocatable bucket types. NFC (#225018)
DenseMap is heavily instantiated and moveFrom and grow are among the
largest code families. For trivially copy constructible and destructible
bucket types (also satisfied by std::pair), call an out-of-line
`growRelocatable` with size/align/hasher (dictionary passing style).
A pointer key hashed by its value hashes inline, which a null
BucketHasher asks for, sparing a call per entry.
DenseMapInfo<T *>::PointerValueHash names the class declaring it, so an
info that specializes or inherits it to hash the pointee -- Attributor's
InstExclusionSet, VPCSEDenseMapInfo, MachineInstrExpressionTrait --
keeps its own hash. Any other key hashes through a thunk, one per
(KeyT, KeyInfoT) whatever the map's value type.
SmallDenseMap's in-place rehash for remove_if shares the loop through
`rehashRelocatable`. It rehashes once rather than into a temporary map
and back, which can reorder a probe chain that wraps around the table.
[3 lines not shown]
[IR] Memory effects for floating-point operations
Floating-point operations in a strictfp function have side effects,
which are modeled using memory effects in the form of a read-write
access to "inaccessible memory". This helps maintain strictfp semantics
but may hinder optimizations. Floating-point operations may depend on
rounding mode or not - this fact may be used to reorder them in a more
optimal way. Similarly, functions that control floating-point
environment (like `set_rounding`, `set_fpmode` etc.) also have more
specific access than generic read-write. Also, "inaccessible memory" is
used in cases other than FP operation, this results in unnecessary
restrictions.
This change implements two new memory location to use instead of the
access to "inaccessible memory". The "fpcontrol" location is used to
represent access to floating-point control modes, of which only rounding
mode is currently supported. The other location, "fpstatus", represents
access to floating-point exceptions. Together they replace the use of
"inaccessible memory".
[21 lines not shown]
Remove cl::callback from AArch64CodeLayoutOpt and AddressSanitizer (#226757)
cl::callback will be removed to enable migration to TableGen based
representation
LLM-aided
[libc++][AIX] Add system library path via blibpath for lldb (#223837)
On AIX some tools we use for testing libc++, like lldb, are linked
against the system libc++, which has additional members (e.g
`shr2_64.o`) that the newly built libc++.a doesn't have. But the current
test harness set the `LIBPATH` to point at the newly built libc++, which
can load break these tools.
This change removes the `LIBPATH` and instead sets the `blibpath`
(equivalent to rpath on other systems), which helps lldb find the system
libc++.a, while still running the tests against the libc++ build under
test.
[AMDGPU] Remove remaining BaseInfo duplicates of TargetParser APIs
Use TargetParser for LDS sizes and architectural VGPR limits, preserving
the distinction between VGPRs and AGPRs on unified-register-file targets.
Remove the TargetID factory wrapper and redundant type and SGPR constant
aliases, updating the remaining callers.
Cover physical LDS allocation boundaries across GPU generations and
full/half-SIMD modes in the assembler tests.
Change-Id: I9fa8447a69de3649792809424d2b0251dae0155b
[AMDGPU] Move dynamic VGPR addressability to TargetParser
Extend getAddressableNumVGPRs with a dynamic block size and share the
eight-block limit through TargetParser. Remove the BaseInfo counterpart
and update its subtarget, occupancy, scheduler, and diagnostic callers.
Cover dynamic addressability, static limits, and unified register files.
Change-Id: Ie4dae7ba34cce8e8ea50e24f7075242a8a045505
[AMDGPU] Move dynamic VGPR allocation granules to TargetParser
Extend getVGPRAllocGranule with a dynamic block size and preserve the
fixed gfx90a-family granule. Remove the BaseInfo counterpart and migrate
its occupancy, scheduler, frame lowering, and register-block callers.
Cover dynamic allocation, static mode, and gfx90a-family exceptions.
Change-Id: Id441ddcea2d7a33121ddb4139af4c5f52f273ff3
[AMDGPU] Move getVGPREncodingGranule to TargetParser
Add GPUKind and SubArch encoding-granule queries with an explicit wave size.
Remove the BaseInfo counterpart and update codegen, assembler, and
disassembler callers, preserving kernel descriptor wave-size overrides.
Cover encoding granules across GPU generations and both wave sizes.
Change-Id: I1982fef776e5a0b7c613c274e544ba3e3f86f136
[AMDGPU] Extend TargetParser VGPR queries for dynamic mode and encoding
Add a VGPR encoding granule query with explicit GPU kind and wave size.
Extend the allocation granule and addressable VGPR queries with an optional
dynamic block size, including the eight-block limit and gfx90a-family
exceptions already used by the backend.
Cover static and dynamic limits, encoding granules, wave sizes, and the
GPUKind and SubArch overloads in TargetParser unit tests. Existing callers
continue to select static mode by default.
Change-Id: I1d389875d25f02b07beb0ea788f16735220007fd
[SimplifyCFG] Cost speculated selects with their real scalar condition (#217664)
`validateAndCostRequiredSelects()` priced the selects that
`speculativelyExecuteBB()` would create using
`CmpInst::makeCmpResultType(PN->getType())` as the condition type. For a
vector phi, that asks the target for the cost of a per-lane vector
select, but the select actually created uses the branch condition, which
is always a scalar `i1`.
This only changes behaviour where a target's cost model distinguishes
the two condition types. Of the targets checked, only AArch64 does.
This may worsen the compiler's output in RISC-V, X86, ARM, so no
intention to merge soon before collecting more feedback on how the
different targets should communicate this property.
