LLVM/project 545b328llvm/lib/Transforms/Vectorize VPlan.h LoopVectorize.cpp

[VPlan] Strip VPRecipeBase::isScalarCast (NFC) (#197695)

This is done in preparation to consolidate more recipes into
VPInstruction.
DeltaFile
+6-7llvm/lib/Transforms/Vectorize/VPlan.h
+4-5llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+2-7llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+12-193 files

LLVM/project 3e15a19offload/test CMakeLists.txt, offload/test/unit lit.cfg.py lit.site.cfg.in

[Offload] fix OffloadAPI unittests discovery (#198750)

Commit 3383f0d repointed LIBOMPTARGET_LIBRARY_DIR to a different
runtimes lib dir, but the unit lit config still derived the unittest
binary path from it. Pass the unittest directory explicitly instead.
DeltaFile
+1-1offload/test/unit/lit.cfg.py
+1-0offload/test/CMakeLists.txt
+1-0offload/test/unit/lit.site.cfg.in
+3-13 files

LLVM/project a8c6535mlir/docs PrivateNameObfuscation.md, mlir/include/mlir/TableGen PrivateName.h

strip op and pass names
DeltaFile
+175-0mlir/test/mlir-tblgen/private-name-obfuscation.td
+174-0mlir/docs/PrivateNameObfuscation.md
+139-0mlir/tools/mlir-tblgen/PrivateName.cpp
+74-0mlir/test/mlir-tblgen/private-pass-obfuscation.td
+59-0mlir/include/mlir/TableGen/PrivateName.h
+39-8mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+660-817 files not shown
+813-3623 files

LLVM/project 08abd96llvm/test/CodeGen/X86 sad.ll sad_variations.ll, llvm/test/Transforms/PhaseOrdering/X86 sad.ll sad_variations.ll

[X86] Update PSADBW tests to more closely match middle-end vector.reduce.add codegen (#198760)

The middle-end will detect vector.reduce.add patterns - update the
Codegen tests to use the intrinsics directly and add PhaseOrdering tests
to ensure vector.reduce.add intrinsics are created
DeltaFile
+658-0llvm/test/Transforms/PhaseOrdering/X86/sad.ll
+259-0llvm/test/Transforms/PhaseOrdering/X86/sad_variations.ll
+14-106llvm/test/CodeGen/X86/sad.ll
+7-49llvm/test/CodeGen/X86/sad_variations.ll
+938-1554 files

LLVM/project 898dd90clang/include/clang/Serialization ASTRecordReader.h, clang/lib/AST ASTContext.cpp Type.cpp

trivial changes
DeltaFile
+20-14clang/lib/Sema/SemaOpenMP.cpp
+18-14clang/lib/AST/ASTContext.cpp
+16-15clang/lib/Sema/SemaTemplate.cpp
+14-11clang/lib/AST/Type.cpp
+14-8clang/lib/AST/ASTDiagnostic.cpp
+11-6clang/include/clang/Serialization/ASTRecordReader.h
+93-6833 files not shown
+202-15239 files

LLVM/project 4256608clang/include/clang/AST ASTContext.h, clang/lib/AST ASTContext.cpp ItaniumMangle.cpp

[clang] implement CWG2064: ignore value dependence for decltype

The 'decltype' for a value-dependent (but non-type-dependent) should be known,
so this patch makes them non-opaque instead.

This patch also implements what's neceessary to allow overloading
on pure differences in instantiation dependence, making `std::void_t`
usable for SFINAE purposes.

This also readds a few test cases from da98651, which was a previous attempt
at resolving CWG2064.

Fixes #8740
Fixes #61818
Fixes #190388
DeltaFile
+888-161clang/lib/AST/ASTContext.cpp
+328-12clang/test/SemaTemplate/instantiation-dependence.cpp
+176-96clang/lib/AST/ItaniumMangle.cpp
+100-98clang/lib/Sema/SemaCXXScopeSpec.cpp
+62-57clang/lib/AST/Type.cpp
+88-11clang/include/clang/AST/ASTContext.h
+1,642-43570 files not shown
+2,396-78776 files

LLVM/project b588ad8flang/test/Integration/OpenMP atomic-compare.f90

[Flang][tests] Add a missing REQUIRES. (#198753)

A newly added test uses `x86_64-unknown-linux-gnu` as a triple, without
a `REQUIRES: x86-registered-target` line, so that it will fail in builds
of LLVM specific to other architectures.
DeltaFile
+1-0flang/test/Integration/OpenMP/atomic-compare.f90
+1-01 files

LLVM/project 77cdd6cllvm/lib/Target/AArch64 AArch64SchedA64FX.td, llvm/test/tools/llvm-mca/AArch64/A64FX A64FX-sve-instructions.s

[AArch64] Fix fmaxv/fminv/fmaxnmv/fminnmv/lasta/lastb sched info in A64FX (#198483)

I've been experimenting with a new TableGen warning on unused defs and
it found a couple bugs in the A64FX scheduling model [1]:

llvm/lib/Target/AArch64/AArch64SchedA64FX.td:2288:5: warning: def
'A64FXWrite_FMAXVD' appears to be unused
llvm/lib/Target/AArch64/AArch64SchedA64FX.td:2334:5: warning: def
'A64FXWrite_LAST_R' appears to be unused

It looks like similarly named defs were used where they should have been
and the microarchitecture manual [2] seems to confirm it.

[1] https://raw.githubusercontent.com/c-rhodes/llvm-project/860eb23fae9bd40b36bcc56534f3d43b36522173/tblgen-unused-defs-warnings.unique.txt
[2] https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitecture_Manual_en_1.8.pdf
DeltaFile
+17-17llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s
+2-2llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+19-192 files

LLVM/project 0425d1ellvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp AArch64TargetTransformInfo.h, llvm/test/Transforms/EarlyCSE/AArch64 intrinsics-1xN.ll

[AArch64][TTI][EarlyCSE] Add support for ld1xN and st1xN intrinsics

Handle ld1x2, ld1x3, ld1x4, st1x2, st1x3, st1x4 in:
- AArch64TTIImpl::getTgtMemIntrinsic
- AArch64TTIImpl::getOrCreateResultFromMemIntrinsic

This enables EarlyCSE to optimize these NEON load/store intrinsics.

To test the changes, a new testcase (intrinsics-1xN.ll) derived from
llvm/test/Transforms/EarlyCSE/AArch64/intrinsics.ll is added.
DeltaFile
+365-0llvm/test/Transforms/EarlyCSE/AArch64/intrinsics-1xN.ll
+28-3llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+0-6llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+393-93 files

LLVM/project 8736eeamlir/docs PrivateNameObfuscation.md, mlir/include/mlir/TableGen PrivateName.h

strip op and pass names
DeltaFile
+175-0mlir/test/mlir-tblgen/private-name-obfuscation.td
+170-0mlir/docs/PrivateNameObfuscation.md
+140-0mlir/tools/mlir-tblgen/PrivateName.cpp
+74-0mlir/test/mlir-tblgen/private-pass-obfuscation.td
+59-0mlir/include/mlir/TableGen/PrivateName.h
+39-8mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+657-817 files not shown
+808-3623 files

LLVM/project 7af7cb0llvm/include/llvm/CodeGen SelectionDAGNodes.h, llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[LLVM][ConstantFP] Replace uses of isExactlyValue(+/-0.0) with isPosZero/isNegZero. (#198496)
DeltaFile
+4-6llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+4-4llvm/lib/Target/PowerPC/PPCInstrInfo.td
+4-4llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+4-4llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+3-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-0llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+25-2113 files not shown
+48-4119 files

LLVM/project 46ac7a6llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 extractelements-vector-ops-shuffle.ll scatter-vectorize-reorder-non-empty.ll

Revert "[SLP] Support ordered fadd reduction via reduction intrinsics" (#198756)

This caused assertion failures, see discussion on the original PR.

Reverts llvm/llvm-project#189451
DeltaFile
+5-348llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+13-8llvm/test/Transforms/SLPVectorizer/X86/extractelements-vector-ops-shuffle.ll
+9-8llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder-non-empty.ll
+14-2llvm/test/Transforms/SLPVectorizer/X86/phi.ll
+41-3664 files

LLVM/project a88c0b1flang/test/Driver intrinsic-module-path.f90

break long RUN: lines
DeltaFile
+48-12flang/test/Driver/intrinsic-module-path.f90
+48-121 files

LLVM/project 5b16893clang/lib/Sema SemaDecl.cpp, clang/test/SemaCXX attr-modular-format.cpp

[libc] Fix modular printf attributes (#194003)

This fixes the validation error related to modular printf missing format attribute in C++ code by moving the validation after the implicit format attribute is added for builtins and known library functions.

This also adds a simple C++ test since the C code did compile successfully because the implicit attributes were added in time for the validation happening for C code.

Assisted-by: codex, reviewed and cross checked, also tested with ATfE,
by me. Modular printf reduced code size from ~37K to ~13K for int-only
printf sample.
DeltaFile
+6-0clang/test/SemaCXX/attr-modular-format.cpp
+4-1clang/lib/Sema/SemaDecl.cpp
+1-1libc/include/llvm-libc-macros/CMakeLists.txt
+11-23 files

LLVM/project ba5d182clang/include/clang/Serialization ASTRecordReader.h, clang/lib/AST ASTContext.cpp Type.cpp

trivial changes
DeltaFile
+20-14clang/lib/Sema/SemaOpenMP.cpp
+18-14clang/lib/AST/ASTContext.cpp
+16-15clang/lib/Sema/SemaTemplate.cpp
+14-11clang/lib/AST/Type.cpp
+14-8clang/lib/AST/ASTDiagnostic.cpp
+11-6clang/include/clang/Serialization/ASTRecordReader.h
+93-6833 files not shown
+202-15239 files

LLVM/project 60f95e2clang/include/clang/AST ASTContext.h, clang/lib/AST ASTContext.cpp ItaniumMangle.cpp

[clang] implement CWG2064: ignore value dependence for decltype

The 'decltype' for a value-dependent (but non-type-dependent) should be known,
so this patch makes them non-opaque instead.

This patch also implements what's neceessary to allow overloading
on pure differences in instantiation dependence, making `std::void_t`
usable for SFINAE purposes.

This also readds a few test cases from da98651, which was a previous attempt
at resolving CWG2064.

Fixes #8740
Fixes #61818
Fixes #190388
DeltaFile
+888-161clang/lib/AST/ASTContext.cpp
+328-12clang/test/SemaTemplate/instantiation-dependence.cpp
+176-96clang/lib/AST/ItaniumMangle.cpp
+100-98clang/lib/Sema/SemaCXXScopeSpec.cpp
+62-57clang/lib/AST/Type.cpp
+88-11clang/include/clang/AST/ASTContext.h
+1,642-43570 files not shown
+2,396-78776 files

LLVM/project 379194cllvm/lib/CodeGen MachineBlockHashInfo.cpp, llvm/test/CodeGen/X86 machine-block-hash.mir

[CodeGen] Always print 64 bit hash value in MachineBlockHashInfoPrinterPass (#198598)

Hash length must be fixed-size. 0x prefix is counted against the width in
format_hex. Increasing from 16 to 18.
DeltaFile
+7-0llvm/test/CodeGen/X86/machine-block-hash.mir
+1-1llvm/lib/CodeGen/MachineBlockHashInfo.cpp
+8-12 files

LLVM/project 79599ballvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 extractelements-vector-ops-shuffle.ll scatter-vectorize-reorder-non-empty.ll

Revert "[SLP] Support ordered fadd reduction via reduction intrinsics"

This reverts commit 230980947083c2309f135c82f10c735b0e06461f.
DeltaFile
+5-348llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+13-8llvm/test/Transforms/SLPVectorizer/X86/extractelements-vector-ops-shuffle.ll
+9-8llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder-non-empty.ll
+14-2llvm/test/Transforms/SLPVectorizer/X86/phi.ll
+41-3664 files

LLVM/project b57ab3dllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

[DAGCombiner] Don't fold cheap extracts of multiple use splats (#134120)

For out-of loop sum reductions, the loop vectorizer will emit an initial
reduction vector like this in the preheader, where there might be an
initial value to begin summing from:

```llvm
%v = insertelement <vscale x 4 x i32> zeroinitializer, i32 %initial, i64 0
```

On RISC-V we currently lower this quite poorly with two splats of 0, one
at m1 and one at m2:

    vsetvli a1, zero, e32, m1, ta, ma  
    vmv.v.i v10, 0                     
    vsetvli zero, zero, e32, m1, tu, ma
    vmv.s.x v10, a0                    
    vsetvli a0, zero, e32, m2, ta, ma  
    vmv.v.i v8, 0                      

    [32 lines not shown]
DeltaFile
+6-12llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
+7-4llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+4-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+17-173 files

LLVM/project e418c93libcxx/test/libcxx-03/containers/associative/map abi.compile.pass.cpp, libcxx/test/libcxx-03/containers/associative/set abi.compile.pass.cpp

[libc++][C++03] Cherry-pick tests from #154559 (#198736)
DeltaFile
+186-0libcxx/test/libcxx-03/containers/associative/map/abi.compile.pass.cpp
+168-0libcxx/test/libcxx-03/containers/associative/set/abi.compile.pass.cpp
+115-0libcxx/test/libcxx-03/containers/sequences/forwardlist/abi.compile.pass.cpp
+106-0libcxx/test/libcxx-03/strings/basic.string/abi.compile.pass.cpp
+97-7libcxx/test/libcxx-03/containers/associative/unord.map/abi.compile.pass.cpp
+48-3libcxx/test/libcxx-03/containers/associative/unord.set/abi.compile.pass.cpp
+720-104 files not shown
+884-1010 files

LLVM/project 6d102f7libcxx/include/__cxx03 locale, libcxx/include/__cxx03/__random piecewise_constant_distribution.h piecewise_linear_distribution.h

[libc++][C++03] Cherry-pick #161049 (#198735)
DeltaFile
+7-11libcxx/include/__cxx03/locale
+3-2libcxx/include/__cxx03/__random/piecewise_constant_distribution.h
+3-2libcxx/include/__cxx03/__random/piecewise_linear_distribution.h
+0-2libcxx/test/std/localization/locale.categories/category.numeric/locale.nm.put/facet.num.put.members/put_pointer.pass.cpp
+0-2libcxx/test/std/localization/locale.categories/category.numeric/locale.nm.put/facet.num.put.members/put_unsigned_long.pass.cpp
+0-2libcxx/test/std/localization/locale.categories/category.numeric/locale.nm.put/facet.num.put.members/put_unsigned_long_long.pass.cpp
+13-2122 files not shown
+13-5428 files

LLVM/project 3a70807llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange ninf.ll reduction2mem.ll

[LoopInterchange] Drop ninf from instructions involved in interchange (#197923)

Applying loop-interchange can alter the order of operations in reduction
calculations. If these operations involve floating‑point arithmetic, the
results may change as well. If an instruction in the chain has the
`ninf` flag, it means that reordering can produce a poison value, which
may lead to undefined behavior even though the original program is not.
This patch addresses this issue by dropping `ninf` flags from the
instructions involved in the transformation, as discussed in #148851.

Fixes #148851.
DeltaFile
+33-11llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+1-1llvm/test/Transforms/LoopInterchange/ninf.ll
+1-1llvm/test/Transforms/LoopInterchange/reduction2mem.ll
+35-133 files

LLVM/project 6a4708dlibcxx/include/__cxx03 string_view string, libcxx/include/__cxx03/__iterator aliasing_iterator.h

[libc++][C++03] Cherry-pick #130573 (#198734)
DeltaFile
+6-2libcxx/include/__cxx03/string_view
+5-2libcxx/include/__cxx03/string
+4-2libcxx/include/__cxx03/__type_traits/is_char_like_type.h
+4-2libcxx/include/__cxx03/__iterator/aliasing_iterator.h
+0-2libcxx/test/std/strings/basic.string/char.bad.verify.cpp
+19-105 files

LLVM/project 57c6538libcxx/include/__cxx03 __config mutex, libcxx/include/__cxx03/__mutex lock_guard.h mutex.h

[libc++][C++03] Cherry-pick #117497 and #154078 (#198731)
DeltaFile
+55-19libcxx/include/__cxx03/__config
+4-6libcxx/include/__cxx03/__mutex/lock_guard.h
+4-4libcxx/include/__cxx03/__mutex/mutex.h
+3-2libcxx/include/__cxx03/mutex
+0-2libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_lock_guard.pass.cpp
+0-2libcxx/test/extensions/clang/thread/thread.mutex/thread_safety_lock_unlock.pass.cpp
+66-353 files not shown
+66-419 files

LLVM/project 6914853mlir/lib/Conversion/MathToSPIRV MathToSPIRV.cpp, mlir/test/Conversion/MathToSPIRV math-to-fpclassify-spirv.mlir

[mlir][SPIR-V] Convert math.isnormal to spirv.IsNormal (#198607)
DeltaFile
+5-0mlir/test/Conversion/MathToSPIRV/math-to-fpclassify-spirv.mlir
+2-1mlir/lib/Conversion/MathToSPIRV/MathToSPIRV.cpp
+7-12 files

LLVM/project fb826a1mlir/include/mlir/Dialect/SPIRV/IR SPIRVArithmeticOps.td, mlir/lib/Dialect/SPIRV/IR SPIRVCanonicalization.cpp

[mlir][SPIR-V] Add ISubBorrow canonicalization patterns (#198637)

Mirror the IAddCarry folder, rewrite isubborrow(x, 0) to <x, 0> via
CompositeConstruct, and fold the all-constant case into a single
spirv.Constant struct
DeltaFile
+27-27mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
+44-0mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
+2-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
+73-273 files

LLVM/project 4813043lldb/test/API/functionalities/breakpoint/delayed_breakpoints TestDelayedBreakpoint.py

[lldb] Update TestDelayedBreakpoint test to use the right setting (#198751)

This test should regardless of which setting is the default for delayed
breakpoints.
DeltaFile
+2-0lldb/test/API/functionalities/breakpoint/delayed_breakpoints/TestDelayedBreakpoint.py
+2-01 files

LLVM/project 7097038libc/include unistd.yaml, llvm/lib/Transforms/Scalar LoopInterchange.cpp

Merge branch 'main' into users/kasuga-fj/loop-interchange-drop-ninf
DeltaFile
+48-48libc/include/unistd.yaml
+53-0llvm/test/Transforms/LoopInterchange/non-lcssa-phi-in-inner-exit.ll
+20-9llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+121-573 files

LLVM/project 0d0f43allvm/lib/Transforms/Scalar LoopInterchange.cpp

address review comments
DeltaFile
+5-4llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+5-41 files

LLVM/project 4a54617llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange non-lcssa-phi-in-inner-exit.ll

[LoopInterchange] Detect unsupported PHIs in inner loop exit block correctly (#194323)

In the legality check phase, `areInnerLoopExitPHIsSupported` inspects
the PHI nodes in the exit block of the inner loop and bail out if
certain unsupported PHI node is found. This functions had several
issues:

- Conflating with the inner loop and the outer loop
- Unnecessarily conservative when LCSSA-chains exist, which will be
handled by `simplifyLCSSA` function

This patch fixes the above issues to detect unsupported PHIs correctly.

Fix #193746
DeltaFile
+53-0llvm/test/Transforms/LoopInterchange/non-lcssa-phi-in-inner-exit.ll
+20-9llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+73-92 files