LLVM/project 61f4618llvm/lib/Target/X86/GISel X86LegalizerInfo.cpp, llvm/test/CodeGen/X86 isel-invoke.ll

[X86][GlobalISel] Explicitly legalize G_INVOKE_REGION_START (#203503)

Removing dependency on the legacy ruleset similarly to #197374

The missing testing coverage was found during LegacyLegalizerInfo
removal in #197308
DeltaFile
+106-0llvm/test/CodeGen/X86/isel-invoke.ll
+1-0llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+107-02 files

LLVM/project 4397de2llvm/docs LangRef.rst, llvm/include/llvm/IR Instructions.h

[IR] Add elementwise modifier to atomic loads
DeltaFile
+33-0llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
+18-4llvm/lib/IR/Verifier.cpp
+15-6llvm/docs/LangRef.rst
+14-3llvm/include/llvm/IR/Instructions.h
+14-2llvm/lib/AsmParser/LLParser.cpp
+16-0llvm/test/Bitcode/atomic-load-store-elementwise.ll
+110-156 files not shown
+140-2112 files

LLVM/project d65d7a1clang/lib/Analysis/LifetimeSafety LoanPropagation.cpp, clang/test/Sema/LifetimeSafety dangling-global.cpp dangling-field.cpp

[LifetimeSafety] Count escape facts when classifying persistent origins (#204485)

computePersistentOrigins marks an origin persistent (kept across CFG
blocks)
only if it appears in more than one block, but it omitted
OriginEscapesFact.
A global is not seeded at function entry, so a global assigned a stack
address
on a conditional or loop path had its origin appear only in the storing
block;
misclassified as block-local, its loan was dropped at the join before
the
escape check, a silently missed dangling-global
(stack-use-after-return).
Count the escaped origin as a cross-block appearance.

Assisted-by: Claude Opus 4.8

Co-authored-by: Gabor Horvath <gaborh at apple.com>
DeltaFile
+23-1clang/test/Sema/LifetimeSafety/dangling-global.cpp
+19-0clang/test/Sema/LifetimeSafety/dangling-field.cpp
+5-1clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
+47-23 files

LLVM/project 12aefe2clang/include/clang/Options Options.td, clang/lib/Driver/ToolChains Flang.cpp

[Flang][Driver] Support for -fsplit-lto-unit option in flang driver (#202858)

When mixing Fortran objects from Flang with C/C++ objects compiled by
Clang during a combined LTO build, it is necessary to ensure that all
files use the same setting for split-lto-unit. This requires the support
for -fsplit-lto-unit option in the flang driver. This support is added
as part of this commit.

 Co-authored-by: Shivarama Rao <shivarama.rao at amd.com>
DeltaFile
+23-0flang/test/Driver/split-lto-unit.f90
+23-0flang/test/Integration/split-lto-unit-2.f90
+11-4flang/lib/Frontend/FrontendActions.cpp
+5-0clang/lib/Driver/ToolChains/Flang.cpp
+2-2clang/include/clang/Options/Options.td
+4-0flang/lib/Frontend/CompilerInvocation.cpp
+68-61 files not shown
+69-67 files

LLVM/project f310904clang/lib/Driver/ToolChains AMDGPU.cpp, llvm/include/llvm/TargetParser AMDGPUTargetParser.def

AMDGPU: Add subtarget feature for controllable xnack modes

This replaces the previously removed xnack-any-only feature,
with the inversion xnack-on-off-modes. All pre-gfx12.5 xnack
targets support the controllable mode. Ignore explicitly
set xnack settings the same way as is done for xnack requests
on other unsupported targets.
DeltaFile
+22-22llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
+13-11llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+22-0llvm/test/CodeGen/AMDGPU/target-id-xnack-always-on.ll
+14-6llvm/lib/Target/AMDGPU/AMDGPU.td
+2-8llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
+4-3clang/lib/Driver/ToolChains/AMDGPU.cpp
+77-503 files not shown
+81-579 files

LLVM/project 08b557bclang/test/Driver hip-sanitize-options.hip, clang/test/Driver/Inputs/rocm/amdgcn/bitcode oclc_isa_version_12-5-generic.bc

AMDGPU: Remove xnack-any-only subtarget feature and handling (#204514)

This reverts commit f4caa0a172d96597c375e6b6b2192c289723a6b9.

This feature was added to gfx12-5-generic only, which does not make
sense given that both gxf1250 and gfx1251 have the same unconditional
xnack handling. It also does not make sense to diagnose trying to use
a specific xnack mode on the generic target only, and only from the
backend.

The current feature management is a confusing mess, given that we have
2 parallel feature systems. AMDGPUTargetParser has a table containing
a bitmask of features, which already contained FEATURE_XNACK_ALWAYS
for gfx1250/gfx1251, but not gfx12-5-generic. Add this handling there
so the sanitizer detection is consistent on the generic target.

These 2 feature tables probably should be unified in some way. We also
probably should have a subtarget feature for the xnack handling, but it
should be inverted. xnack-any-only is an antifeature, in that it removes
functionality from the base target. It would be better to invert this,
so all of the older targets support configurable xnack modes.
DeltaFile
+0-9llvm/test/CodeGen/AMDGPU/gfx12-5-generic-no-xnack.ll
+5-0clang/test/Driver/hip-sanitize-options.hip
+0-5llvm/lib/Target/AMDGPU/AMDGPU.td
+0-4llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+1-1llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
+0-0clang/test/Driver/Inputs/rocm/amdgcn/bitcode/oclc_isa_version_12-5-generic.bc
+6-196 files

LLVM/project 567eeecllvm/lib/Target/AMDGPU AMDGPUMCResourceInfo.cpp, llvm/test/CodeGen/AMDGPU indirect-call-agpr-cap.ll indirect-call-vgpr-cap.ll

[AMDGPU] Capping max number of registers to function's occupancy budget for indirect calls (#199765)

Depends on https://github.com/llvm/llvm-project/pull/199746

Changed the SetMaxReg Lambda function to cap at
ST.getMaxNumVectorRegs(F) for VGPRs and AGPRs and ST.getMaxNumSGPRs(F)
for SGPR. ST.getMaxNumVectorRegs(F) and ST.getMaxNumSGPRs(F) returns the
budget for the given function F and is mainly determined by the
occupancy of the function.

This cap is needed since the module's max could overestimate register
usage because it includes functions that earlier in the compiler was
determined inaccessible by that indirect call. ST.getMaxNumVectorRegs(F)
and ST.getMaxNumSGPRs(F) were calculated according to an more accurate
call graph.

This fixes an issue of overinflated number of VGPR/AGPR for kernels that
have indirect function calls. This inflation has led to some kernels
with indirect calls to go over the limit for VGPR/AGPR and crash.

    [5 lines not shown]
DeltaFile
+57-0llvm/test/CodeGen/AMDGPU/indirect-call-agpr-cap.ll
+54-0llvm/test/CodeGen/AMDGPU/indirect-call-vgpr-cap.ll
+22-22llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
+21-21llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
+35-0llvm/test/CodeGen/AMDGPU/indirect-call-sgpr-cap.ll
+29-4llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
+218-478 files not shown
+270-9314 files

LLVM/project b3c6fbcllvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/include/llvm/Target CGPassBuilderOption.h

[CommandLine] Make cl::boolOrDefault a scoped enum

Prevents implicit conversion to bool/int, where BOU_FALSE wrongly
evaluated as true. All uses qualified as cl::boolOrDefault::BOU_*.

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <noreply at anthropic.com>
DeltaFile
+15-13llvm/lib/CodeGen/TargetPassConfig.cpp
+10-8llvm/include/llvm/Passes/CodeGenPassBuilder.h
+10-5llvm/lib/CodeGen/BranchFolding.cpp
+7-7llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+6-6llvm/include/llvm/Target/CGPassBuilderOption.h
+10-1llvm/lib/Support/CommandLine.cpp
+58-4024 files not shown
+129-10130 files

LLVM/project c70f3aellvm/docs LangRef.rst, llvm/include/llvm/IR Instructions.h

[IR] Add elementwise modifier to atomic loads
DeltaFile
+33-0llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
+18-4llvm/lib/IR/Verifier.cpp
+15-6llvm/docs/LangRef.rst
+14-2llvm/lib/AsmParser/LLParser.cpp
+16-0llvm/test/Bitcode/atomic-load-store-elementwise.ll
+12-1llvm/include/llvm/IR/Instructions.h
+108-136 files not shown
+137-1912 files

LLVM/project b636f43llvm/lib/Target/AMDGPU SIInstrInfo.h SIDefines.h, llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUInstPrinter.cpp

[NFC][AMDGPU] Introduce SIInstrFlags predicates for TSFlags access (#201512)

Add inline predicate templates to SIDefines.h for each TSFlags bit
(isSALU, isVOP3, isFLAT, isMaybeAtomic, hasFPClamp, ...) plus compound
predicates (isAtomic, isSegmentSpecificFLAT, isImage, isVMEM).

Route all SIInstrInfo.h thin wrapper bodies through the new predicates
instead of reading TSFlags bits directly. 
---------
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+122-144llvm/lib/Target/AMDGPU/SIInstrInfo.h
+210-0llvm/lib/Target/AMDGPU/SIDefines.h
+2-3llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+2-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+336-1494 files

LLVM/project 2563af1clang/test/Driver aarch64-mcpu.c, clang/test/Driver/print-enabled-extensions aarch64-neoverse-v3ae.c

[AArch64] Add armagicpu CPU (#202557)
DeltaFile
+2-1llvm/unittests/TargetParser/TargetParserTest.cpp
+1-1clang/test/Misc/target-invalid-cpu-note/aarch64.c
+2-0clang/test/Driver/aarch64-mcpu.c
+1-0clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
+1-0llvm/lib/Target/AArch64/AArch64Processors.td
+7-25 files

LLVM/project 4d81237llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanUtils.cpp, llvm/unittests/Transforms/Vectorize VPlanUncountableExitTest.cpp VPlanTestBase.h

[LV] Follow up to uncountable exit with side effects vectorization (#201589)

Addressing post-commit comments on #178454.
DeltaFile
+193-55llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-166llvm/unittests/Transforms/Vectorize/VPlanUncountableExitTest.cpp
+0-109llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+0-12llvm/lib/Transforms/Vectorize/VPlanUtils.h
+1-10llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+0-11llvm/unittests/Transforms/Vectorize/VPlanTestBase.h
+194-3638 files not shown
+212-38214 files

LLVM/project f5a52c9llvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/include/llvm/Target CGPassBuilderOption.h

CodeGenPassBuilder: Use cl::boolOrDefault directly in CGPassBuilderOption

Current implementation that uses std::optional<bool> captures cl::BOU_FALSE,
for example -global-isel=0, as true. Explictly setting option to 0 should be
false, forced option not set.
This could be fixed but I find it cleaner to use boolOrDefault directly and
use same logic as in TargetPassConfig.
Options EnableIPRA and EnableGlobalISelAbort are left as optional since for
them it is explictly checked if they are set using getNumOccurrences.
boolOrDefault has encoded unset option.
DeltaFile
+26-26llvm/lib/CodeGen/TargetPassConfig.cpp
+10-10llvm/include/llvm/Passes/CodeGenPassBuilder.h
+6-6llvm/include/llvm/Target/CGPassBuilderOption.h
+2-2llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+2-1llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+48-471 files not shown
+49-487 files

LLVM/project 7c05d28llvm/lib/Transforms/Scalar SimpleLoopUnswitch.cpp, llvm/test/Transforms/PhaseOrdering unswitch-nontrivial-cold-func.ll

Revert "[SimpleLoopUnswitch] Generalize the notion of trivial unswitching" (#204538)

Reverts llvm/llvm-project#193989.

That change caused failed assertions, see that PR for examples.
DeltaFile
+0-1,031llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-loop-guard.ll
+0-114llvm/test/Transforms/PhaseOrdering/unswitch-nontrivial-cold-func.ll
+31-31llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
+29-29llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
+3-48llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
+29-18llvm/test/Transforms/SimpleLoopUnswitch/PGO-nontrivial-unswitch2.ll
+92-1,2715 files not shown
+132-1,31411 files

LLVM/project d85766eclang/lib/AST/ByteCode Compiler.cpp Compiler.h, clang/test/AST/ByteCode literals.cpp

[clang][bytecode] Diagnose jumps to case labels in StmtExprs (#204539)

We need another bit of state to save if the switch was also in the
StmtExpr or not.
DeltaFile
+15-0clang/test/AST/ByteCode/literals.cpp
+9-0clang/lib/AST/ByteCode/Compiler.cpp
+1-0clang/lib/AST/ByteCode/Compiler.h
+25-03 files

LLVM/project c372480clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp, clang/lib/Sema SemaLifetimeSafety.h AnalysisBasedWarnings.cpp

Reapply "[LifetimeSafety] Support C Language in LifetimeSafety" (#204536)

There are a few constraints that make supporting C a bit cumbersome:

* C assignment expressions are rvalues, unlike C++ assignment
expressions. The analysis has to account for the different origin shape
of the assignment result by stripping an origin from `LHSExpr`.
* Function addresses in C do not need lifetime tracking. Taking `&f`
should not create origins because functions do not have local object
lifetime (unlike in C++).
* GNU C permits `void*` subscripting/pointer arithmetic. Expressions
like `bytes[0]` (where `bytes` is `void*`) have type `void` and do not
produce an addressable object with origins, even though `void*` itself
can carry pointer origins.
* Some C subscripts, such as vector subscripts, are not GLValues, so
they do not have storage origins to track.
* `va_arg(ap, array_type)` is undefined behavior, so we skip it instead
of trying to model origins for it.
* C does not have a spelling for `[[gsl::Owner]]` / `[[gsl::Pointer]]`,

    [24 lines not shown]
DeltaFile
+181-0clang/test/Sema/LifetimeSafety/safety-c.c
+28-0clang/test/Sema/attr-lifetime-capture-by.c
+23-1clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+21-0clang/test/Sema/attr-lifetimebound.c
+19-0clang/lib/Sema/SemaLifetimeSafety.h
+3-6clang/lib/Sema/AnalysisBasedWarnings.cpp
+275-74 files not shown
+290-1010 files

LLVM/project 8797861llvm/cmake/modules HandleLLVMOptions.cmake

[llvm] Fix typo UNSPPORTED -> UNSUPPORTED (#138628)

This word was misspelled in c63f2581f.
DeltaFile
+1-1llvm/cmake/modules/HandleLLVMOptions.cmake
+1-11 files

LLVM/project 09a3fffllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp AMDGPUHWEvents.cpp

[AMDGPU][HWEvents] Refactor VMEM_ACCESS as VMEM_READ_ACCESS

Instead of having an HWEvent that can be either a read or a write
depending on the target, keep the events as straightforward as
possible and let InsertWaitCnt interpret it. Rename VMEM_ACCESS
to VMEM_READ_ACCESS and set VMEM_STORE_ACCESS & similar events
even if the target does not have a VSCnt.

I think this conceptually makes more sense.
This separates concerns better so that HWEvents nodels events
objectively, and InsertWaitCnt handles them as necessary for the task
it is trying to achieve (insert wait instructions).
DeltaFile
+23-13llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+5-4llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
+1-3llvm/lib/Target/AMDGPU/AMDGPUHWEvents.def
+29-203 files

LLVM/project 4b4b771amd/comgr/test-unit CMakeLists.txt

[Comgr] Add missing dependencies to hotswap unit-tests

Would lead to undefined reference errors with BUILD_SHARED_LIBS_ON.
DeltaFile
+2-1amd/comgr/test-unit/CMakeLists.txt
+2-11 files

LLVM/project 69c9c02clang/lib/AST/ByteCode Compiler.cpp

[clang][bytecode][NFC] Remove StmtExprScope (#204530)

We can use a simple llvm::SaveAndRestore instead.
DeltaFile
+1-14clang/lib/AST/ByteCode/Compiler.cpp
+1-141 files

LLVM/project 4e9609bllvm/lib/Analysis Delinearization.cpp

[Delinearization] Fix indentation (NFC) (#204531)
DeltaFile
+17-17llvm/lib/Analysis/Delinearization.cpp
+17-171 files

LLVM/project 7d2db10llvm/lib/Transforms/Scalar SimpleLoopUnswitch.cpp, llvm/test/Transforms/PhaseOrdering unswitch-nontrivial-cold-func.ll

Revert "[SimpleLoopUnswitch] Generalize the notion of trivial unswitching (#1…"

This reverts commit 5a5d0fb1e471b3a1e842aee1f993e885c8d19713.
DeltaFile
+0-1,031llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-loop-guard.ll
+0-114llvm/test/Transforms/PhaseOrdering/unswitch-nontrivial-cold-func.ll
+31-31llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
+29-29llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
+3-48llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
+29-18llvm/test/Transforms/SimpleLoopUnswitch/PGO-nontrivial-unswitch2.ll
+92-1,2715 files not shown
+132-1,31411 files

LLVM/project 3d37689llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[AMDGPU] Make SGPR occupancy the exact inverse of getMaxNumSGPRs (#201342)

The SGPR->occupancy table ignored the allocation granule and the
trap-handler reservation, so it disagreed with getMaxNumSGPRs() (e.g. 80
and 81 SGPRs reported the same occupancy and hid the cliff). Compute
occupancy by inverting the per-wave SGPR budget instead, sharing one
helper (getSGPRBudgetPerWave) with getMaxNumSGPRs()/getMinNumSGPRs() so
the budget and its inverse cannot drift apart. Thread that budget
(total/granule/trap reserve) through the occupancy MCExpr because the
asm printer's MCSubtargetInfo does not carry the implicit amdhsa
+trap-handler feature.

This aligns the SGPR-limited occupancy heuristic with the register
budget for all pre-GFX10 targets (including non-trap), which accounts
for the codegen test updates.

Assisted-by: Claude Opus

---------

Co-authored-by: mselehov <mselehov at amd.com>
DeltaFile
+6,940-6,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,276-1,243llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+716-711llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+461-484llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+437-434llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+237-246llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
+10,067-9,90021 files not shown
+10,571-10,23727 files

LLVM/project b8def50llvm/test/tools/llvm-pdbutil dxcontainer-export.test, llvm/tools/llvm-pdbutil llvm-pdbutil.cpp llvm-pdbutil.h

[llvm-pdbutil] Add `--dxcontainer` option to `llvm-pdbutil export` (#200486)

Adds a `--dxcontainer` option to export a `DXContainer` from a PDB file.
It basically serves as an alias to `--stream=5`, and is clearly seen in
`--help`.
DeltaFile
+112-0llvm/test/tools/llvm-pdbutil/dxcontainer-export.test
+43-18llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
+1-0llvm/tools/llvm-pdbutil/llvm-pdbutil.h
+156-183 files

LLVM/project 2c57640llvm/lib/Target/AMDGPU AMDGPUHWEvents.cpp SIInsertWaitcnts.cpp

[AMDGPU][InsertWaitCnts] Move TENSOR/ASYNC event detection to separate header

I forgot to move those out of the way as they were not grouped with the other.
Now `getEventsFor` does all the work.
DeltaFile
+7-0llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
+0-5llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+7-52 files

LLVM/project f999ca3llvm/include/llvm/Bitcode BitcodeReader.h, llvm/lib/Bitcode/Reader BitcodeReader.cpp

[Bitcode] Add SkipDebugIntrinsicUpgrade hook to ParserCallbacks (#201456)

Expose CanUpgradeDebugIntrinsicsToRecords (already an opt-in parameter
on UpgradeIntrinsicFunction) through ParserCallbacks. When set, the
bitcode reader's globalCleanup() no longer auto-upgrades debug intrinsic
calls (llvm.dbg.\*) to non-instruction debug records; the caller is then
responsible for performing the upgrade manually (e.g. via
Module::convertToNewDbgValues()) after any custom processing of the
intrinsic-form IR.

This is useful for out-of-tree consumers that run passes operating on
intrinsic-form debug metadata before opting into the new debug records
format.
DeltaFile
+252-0llvm/unittests/Bitcode/BitReaderTest.cpp
+10-1llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+8-0llvm/include/llvm/Bitcode/BitcodeReader.h
+270-13 files

LLVM/project 2b14949llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp AMDGPUHWEvents.h

Comments + fix build + small improvements
DeltaFile
+8-8llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+13-0llvm/lib/Target/AMDGPU/AMDGPUHWEvents.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
+22-93 files

LLVM/project 166d2e4llvm/lib/Transforms/Scalar Reassociate.cpp, llvm/test/CodeGen/AMDGPU reassoc-scalar.ll

review
DeltaFile
+16-17llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
+0-1llvm/lib/Transforms/Scalar/Reassociate.cpp
+16-182 files

LLVM/project baad7c3clang/include/clang/AST Expr.h, clang/lib/AST ExprConstant.cpp Decl.cpp

[clang][ExprConst] Add `EvalStatus::DiagEmitted` flag (#203838)

There are some instances where we want to know _if_ a diagnostic has
been emitted, but we're not interested in the actual diagnostic.
Emitting the diagnostics can be rather costly, especially because we add
the callstack as notes.
DeltaFile
+13-16clang/lib/AST/ExprConstant.cpp
+9-7clang/lib/AST/Decl.cpp
+6-3clang/include/clang/AST/Expr.h
+2-4clang/lib/AST/ByteCode/Compiler.cpp
+2-4clang/lib/AST/ComputeDependence.cpp
+1-3clang/lib/Sema/SemaExpr.cpp
+33-374 files not shown
+40-3810 files

LLVM/project 12ecfc7llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine assume.ll assume-i32.ll

[InstCombine] Drop redundant alignment assumptions with offsets (#204321)
DeltaFile
+25-0llvm/test/Transforms/InstCombine/assume.ll
+9-6llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+13-0llvm/test/Transforms/InstCombine/assume-i32.ll
+47-63 files