LLVM/project 13cee9bcompiler-rt/lib/sanitizer_common sanitizer_posix.cpp

[sanitizer] Fix race condition in GetNamedMappingFd with decorate_pro… (#190981)

…c_maps=1

Multi-threaded programs crash randomly when
ASAN_OPTIONS=decorate_proc_maps=1 is enabled due to filename collision
in /dev/shm.

Root Cause:
All threads use the same filename format '/dev/shm/<PID> [name]',
causing race conditions where one thread deletes a file created by
another thread, resulting in ENOENT errors.

Solution:
Add thread ID (TID) to the filename to ensure uniqueness:
- Old format: /dev/shm/<PID> [name]
- New format: /dev/shm/<PID>.<TID> [name]

This ensures each thread has a unique filename, eliminating the race

    [6 lines not shown]
DeltaFile
+3-3compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
+3-31 files

LLVM/project 4ef52felibcxx/utils/ci run-buildbot

[libcxx] Remove package installation for generic-llvm-libc (#194259)

Now that these packages are installed by default in the container image,
we no longer need to install them each time we do a build.
DeltaFile
+0-10libcxx/utils/ci/run-buildbot
+0-101 files

LLVM/project 28c4c25compiler-rt/lib/sanitizer_common sanitizer_allocator_dlsym.h

[Asan]Add align argument to Realloc() (#194255)

Add align argument to the function Realloc() to ensure original
allocation alignment through realloc
DeltaFile
+3-3compiler-rt/lib/sanitizer_common/sanitizer_allocator_dlsym.h
+3-31 files

LLVM/project 544d003llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/VPlan vplan-print-after-all.ll

[VPlan] Use RUN_VPLAN_PASS for later VPlan transforms. (#194261)

Convert a number of later VPlan transform invocations to use
RUN_VPLAN_PASS. Enables more accurate transform printing, as well as
extra verification.

This should migrate all remaining transforms that can be moved without
changes.
DeltaFile
+35-31llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+11-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
+46-312 files

LLVM/project 3b20615llvm/test/Transforms/LoopVectorize/VPlan widen-canonical-iv-register-pressure.ll, llvm/test/Transforms/LoopVectorize/X86 widen-canonical-iv-register-pressure.ll

[LV] Add test cases where wide IV can cause spills. (#194260)

Add test cases showing cases where replacing VPWidenCanonicalIVRecipe
with VPWidenIntOrFPinductionPHIRecipe is profitable/not profitable due
to introducing spills.
DeltaFile
+338-0llvm/test/Transforms/LoopVectorize/X86/widen-canonical-iv-register-pressure.ll
+132-0llvm/test/Transforms/LoopVectorize/VPlan/widen-canonical-iv-register-pressure.ll
+470-02 files

LLVM/project 8f65ad5llvm/lib/Analysis ConstantFolding.cpp, llvm/test/Transforms/InstSimplify load.ll

[ConstantFolding] Fold byte loads from constant globals (#194074)

Handle byte types in `FoldReinterpretLoadFromConst` and
`ConstantFoldLoadFromUniformValue` so loads from constant globals fold.
DeltaFile
+103-0llvm/test/Transforms/InstSimplify/load.ll
+23-11llvm/lib/Analysis/ConstantFolding.cpp
+126-112 files

LLVM/project a562a10lldb/tools/lldb-dap DAP.cpp DAPSessionManager.cpp

lldb-dap: Fix race condition in event threads creation (#194012)

Move the registration of the SBListener to before
the event threads (`ProgressEventThread` and `EventThread`) start

This prevents a race condition where a stop event
could be missed if it was sent immediately after thread creation, which
would lead to a deadlock. It is most likely to happen under heavy CPU
load with test that fails early like
TestDAP_commands::test_command_directive_abort_on_error_init_commands.

Relevant logs.
```sh
# Event thread deadlock.
0x00007348BC000BE0 Listener('lldb-dap.progress.listener')::GetEventInternal, timeout = 1000000 us, event_mask = 0
0x00005b72419d1640 Broadcaster("lldb-dap")::BroadcastEvent (event_sp = 0x5b7241eebb60 Event: broadcaster = 0x5b72418e0df0 (lldb-dap), type = 0x00000001, data = <NULL>, unique=false) hijack = 0x0000000000000000
0x00005B7241898440 Listener('lldb.Debugger')::GetEventInternal, timeout = 1000000 us, event_mask = 0
0x7348bc000be0     Listener::GetEventInternal() timed out for lldb-dap.progress.listener
0x00007348BC000BE0 Listener('lldb-dap.progress.listener')::GetEventInternal, timeout = 1000000 us, event_mask = 0

    [9 lines not shown]
DeltaFile
+14-7lldb/tools/lldb-dap/DAP.cpp
+15-0lldb/tools/lldb-dap/DAPSessionManager.cpp
+2-9lldb/tools/lldb-dap/EventHelper.cpp
+1-1lldb/tools/lldb-dap/DAP.h
+32-174 files

LLVM/project 4e6d01d.github/workflows libcxx-build-and-test.yaml

[libcxx][Github] Bump libcxx runners to the next runner set (#194212)

To pick up some recent container changes that add additional tools for
the LLVM libc build.
DeltaFile
+3-3.github/workflows/libcxx-build-and-test.yaml
+3-31 files

LLVM/project 694f1b4.github/workflows libcxx-build-and-test.yaml

Remove GitHub Action seanmiddleditch/gha-setup-ninja (#194218)

From the GitHubAction
[README](https://github.com/seanmiddleditch/gha-setup-ninja/blob/master/README.md):
"This action is no longer necessary, as ninja is now
included on all default GitHub runner instances."
DeltaFile
+0-1.github/workflows/libcxx-build-and-test.yaml
+0-11 files

LLVM/project fbac55bllvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelDAGToDAG.cpp, llvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp

[AArch64] Optimize vector fmul(sitofp/uitofp, 1/2^N) -> scvtf/ucvtf (#141480)

When a vector integer-to-float conversion is followed by a multiply with a
reciprocal power-of-two constant, we can fold both operations into a single
SCVTF or UCVTF instruction with a fixed-point shift operand.

For example, `fmul(sitofp(v2i32 x), <0.5, 0.5>)` becomes `scvtf.2s v0, v0, #1`.

This is a reworked version with several improvements over the original
submission:
- Rewrite the C++ operand matcher to share implementation with the existing
    `SelectCVTFixedPointVec` (MOVIshift, FMOV, and DUP handling with correct
    truncation for f16)
- Add `uitofp`/`ucvtf` patterns via a `CVTFRecipPat` multiclass
- Add full GlobalISel support (`GIComplexOperandMatcher` + renderer)

Supported vector types: `v2f32`, `v4f32`, `v2f64`, `v4f16`, `v8f16`.

Fixes #94909
DeltaFile
+474-0llvm/test/CodeGen/AArch64/scvtf-div-mul-combine.ll
+57-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+34-10llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+26-6llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+591-164 files

LLVM/project 7b43dcdllvm/test/CodeGen/AArch64 neon-rshrn.ll

[AArch64] Add disjoint or tests for rshrn and raddhn. NFC (#194252)

These should already be OK, as the os disjoint or connot round up.
DeltaFile
+76-0llvm/test/CodeGen/AArch64/neon-rshrn.ll
+76-01 files

LLVM/project bb4aebbllvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Small improvements

Created using spr 1.3.7
DeltaFile
+15-8llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+15-81 files

LLVM/project 0e141adllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AMDGPU notriviallyvectorizableintrinsicoperands.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+237-9llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+105-54llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
+61-98llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
+34-47llvm/test/Transforms/SLPVectorizer/X86/non-vectorizable-inst-operand.ll
+30-42llvm/test/Transforms/SLPVectorizer/X86/parent-node-non-schedulable.ll
+11-15llvm/test/Transforms/SLPVectorizer/X86/split-node-marked-to-gather.ll
+478-26515 files not shown
+554-34921 files

LLVM/project 8efcfc2llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer revec.ll

[SLP] Reuse diamond-matched gather across asymmetric reorder/reuse

processBuildVector's perfect-diamond match used Entries.front()->isSame(
E->Scalars) only, missing matches where E carries the reorder/reuse and
the entry is canonical. Two TreeEntries with the same effective scalar
layout but different raw orderings then build independent gathers; one
emits a fill-in shufflevector for reused lanes while the other leaves
poison there.

Fixes #194191.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194247
DeltaFile
+10-5llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1-2llvm/test/Transforms/SLPVectorizer/X86/shrink_after_reorder.ll
+1-2llvm/test/Transforms/SLPVectorizer/revec.ll
+1-1llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
+13-104 files

LLVM/project 91805dcllvm/test/Transforms/SLPVectorizer/X86 select-copyable-cmp-poison.ll

[SLP][NFC]Add a test with the incorrect vectorization for fully matched, but reordered, node, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194244
DeltaFile
+203-0llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
+203-01 files

LLVM/project 72c8f98flang/include/flang/Parser parse-tree.h, flang/lib/Lower/OpenMP OpenMP.cpp

[flang][OpenMP] Rename "declare constructs" to directives, NFC (#194240)

Only executable directives are constructs in OpenMP, so, for example,
"declare mapper" is not a construct.

Apply

find flang/ \( -name '*.cpp' -o -name '*.h' -o -name '*.f90' \) -exec sed \
-i -E -e 's/OpenMP(Declare[A-Za-z]*)Construct\b/Omp\1Directive/g' {} \;

plus local formatting updates as needed.
DeltaFile
+16-15flang/lib/Lower/OpenMP/OpenMP.cpp
+11-12flang/lib/Semantics/resolve-directives.cpp
+10-11flang/include/flang/Parser/parse-tree.h
+9-9flang/test/Parser/OpenMP/declare_target-device_type.f90
+8-10flang/lib/Semantics/check-omp-structure.cpp
+8-8flang/lib/Semantics/check-omp-structure.h
+62-6520 files not shown
+118-12226 files

LLVM/project be59278flang/include/flang/Parser parse-tree.h, flang/lib/Lower/OpenMP OpenMP.cpp

[flang][OpenMP] Rename "declare constructs" to directives, NFC

Only executable directives are constructs in OpenMP, so, for example,
"declare mapper" is not a construct.

Apply

find flang/ \( -name '*.cpp' -o -name '*.h' -o -name '*.f90' \) -exec sed \
  -i -E -e 's/OpenMP(Declare[A-Za-z]*)Construct\b/Omp\1Directive/g' {} \;

plus local formatting updates as needed.
DeltaFile
+16-15flang/lib/Lower/OpenMP/OpenMP.cpp
+11-12flang/lib/Semantics/resolve-directives.cpp
+10-11flang/include/flang/Parser/parse-tree.h
+9-9flang/test/Parser/OpenMP/declare_target-device_type.f90
+8-10flang/lib/Semantics/check-omp-structure.cpp
+8-8flang/lib/Semantics/check-omp-structure.h
+62-6520 files not shown
+118-12226 files

LLVM/project c65bcf2llvm/lib/Analysis ValueTracking.cpp, llvm/lib/Transforms/InstCombine InstCombineAddSub.cpp InstCombineInternal.h

[InstCombine] Div ceil optimizations  (#190175)

Relates: https://github.com/llvm/llvm-project/issues/187838

This PR improves handling of `div_ceil` from rust (which emits a div +
rem).

Currently, these three rust functions:
```rust
use std::hint::assert_unchecked;

#[unsafe(no_mangle)]
pub fn div_ceil_without_assume(x: u32) -> u32 {
    x.div_ceil(7)
}

#[unsafe(no_mangle)]
pub fn div_ceil_with_assume(x: u32) -> u32 {
    unsafe {

    [313 lines not shown]
DeltaFile
+210-0llvm/test/Transforms/InstCombine/divceil.ll
+43-0llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+6-0llvm/lib/Transforms/InstCombine/InstCombineInternal.h
+4-0llvm/lib/Analysis/ValueTracking.cpp
+1-1llvm/test/Transforms/InstCombine/fls.ll
+264-15 files

LLVM/project 2d789ffllvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanConstruction.cpp, llvm/test/Transforms/LoopVectorize induction.ll

[VPlan] Verify and handle FOR legality during header phi creation (NFC). (#191298)

Move the logic to validate FOR users and introduce the split directly to
header phi creation. It makes sense to introduce the header phi and the
splice together.

It also means sinking only needs to be done once, instead for each
VPlan.

Depends on https://github.com/llvm/llvm-project/pull/190681.

PR: https://github.com/llvm/llvm-project/pull/191298
DeltaFile
+36-257llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+201-3llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+15-16llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+10-17llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+8-8llvm/test/Transforms/LoopVectorize/induction.ll
+15-0llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+285-3014 files not shown
+295-30810 files

LLVM/project c23a089llvm/include/llvm/ProfileData SampleProf.h, llvm/test/tools/llvm-profgen filter-build-id-unsymbolized.test

format, update test

Created using spr 1.3.4
DeltaFile
+9-16llvm/test/tools/llvm-profgen/filter-build-id-unsymbolized.test
+3-4llvm/include/llvm/ProfileData/SampleProf.h
+1-2llvm/tools/llvm-profgen/PerfReader.cpp
+13-223 files

LLVM/project 8c554c4llvm/lib/Target/LoongArch LoongArchLASXInstrInfo.td LoongArchLSXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction sub.ll add.ll

[LoongArch] Add support for vector add/sub on vNi128 types

Legalize ADD/SUB for v1i128 and v2i128 and extend LSX/LASX instruction
selection patterns to support the Q element size. Update register classes
to include vNi128 types and add codegen tests to verify lowering to
VADD.Q/XVADD.Q and VSUB.Q/XVSUB.Q.
DeltaFile
+6-102llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+6-93llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+6-43llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+6-42llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+17-4llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+17-4llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+58-2882 files not shown
+66-2928 files

LLVM/project d9d210dllvm/test/CodeGen/LoongArch/lasx/ir-instruction sub.ll add.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction add.ll sub.ll

[LoongArch][NFC] Add tests for vector add on vNi128
DeltaFile
+108-2llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+99-2llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+49-2llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+48-2llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+304-84 files

LLVM/project 4dafdf6llvm/include/llvm/CodeGen ValueTypes.td, llvm/test/Analysis/CostModel/ARM arith-overflow.ll

[CodeGen] Add <2 x i128> value type (#193910)
DeltaFile
+6-6llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
+2-2llvm/test/TableGen/CPtrWildcard.td
+1-0llvm/include/llvm/CodeGen/ValueTypes.td
+9-83 files

LLVM/project 6439bbellvm/lib/Target/ARM ARMISelLowering.cpp, llvm/test/CodeGen/ARM hoist-and-by-const-from-shl-in-eqcmp-zero.ll hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

Revert "[ARM] Fold SELECT (AND(X,1) == 0), C1, C2 -> XOR(C1,AND(NEG(AND(X,1)),XOR(C1,C2)) in Thumb1 (#185898)" (#194230)

This reverts commit 1823355d06b854854701a8ba430aa1f6be9994f4 due to
performance
regressions in benchmarks.
DeltaFile
+103-92llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+97-88llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+1-49llvm/lib/Target/ARM/ARMISelLowering.cpp
+201-2293 files

LLVM/project aa3de78llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 spillcost-call-between-operands.ll spillcost-loop-backedge.ll

[SLP] Fix spill-cost cache lookup and predecessor scan

A cached intra-block scan that stopped at a call or budget limit only
proves the sub-range below the stop point is call-free; do not reuse
the cached bit for queries whose First lies above it. Also switch the
cross-block predecessor scan to "exists a call-free backward path"
semantics, skip blocks strictly dominated by Root, and memoize only
the (Root, OpParent) key. Fixes a false-positive spill cost that was
blocking profitable vectorization.

Reviewers: RKSimon, hiraditya, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/192709
DeltaFile
+104-26llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4-11llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-call-between-operands.ll
+0-5llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll
+108-423 files

LLVM/project d593279llvm/lib/Target/NVPTX NVPTXISelLowering.cpp NVPTXISelLowering.h, llvm/test/CodeGen/NVPTX fp-contract-f32x2.ll

[NVPTX] Scalarize `contract FMUL v2f32` to enable FMA fusion (#192815)

SM100+ legalizes `FMUL v2f32`, blocking the scalar FADD->FMA combiner.
Scalarize it when `contract` (or `allowFMA()`) is set and every lane
feeds a single `contract` FADD.
DeltaFile
+62-24llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+29-0llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
+10-0llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+101-243 files

LLVM/project ab57f94libcxx/utils/ci/images libcxx_next_runners.txt

[libcxx] Bump next runner set (#194211)

So that we can pick up changes in
49b0451ec690dfc76690c19032bdc97c2889000b.
DeltaFile
+1-1libcxx/utils/ci/images/libcxx_next_runners.txt
+1-11 files

LLVM/project a0e42c2clang/lib/AST/ByteCode Integral.h Interp.h, clang/test/AST/ByteCode functions.cpp

[clang][bytecode] Add new IntegralType for function addresses (#194206)

We used to use just `::Address` for functions, which later caused
problems because we casted the pointer to `ValueDecl*` and passed it to
`Program::getOrCreateGlobal()`, which doesn't work of course.
DeltaFile
+9-0clang/lib/AST/ByteCode/Integral.h
+9-0clang/test/AST/ByteCode/functions.cpp
+5-1clang/lib/AST/ByteCode/Interp.h
+2-0clang/lib/AST/ByteCode/Primitives.h
+25-14 files

LLVM/project 49b0451libcxx/utils/ci/docker docker-compose.yml

[libcxx] Bump base image version to most recent (#194209)

To pull in the changes from bd75c10199a159a20720f8ee5c00afebb033f46e.
DeltaFile
+2-2libcxx/utils/ci/docker/docker-compose.yml
+2-21 files

LLVM/project 32a9f63clang/lib/AST/ByteCode Interp.cpp Interp.h, clang/test/Sema static-init.c

[clang][bytecode] Fix some problems with ptr-to-int casts (#193988)

1) When doing integral casts on a pointer-casted-to-integral, check the
bitwidth we're casting _to_, not the one we're casting _from_.
2) When the pointer we're casting to an integral is a dummy pointer,
don't forget to check the bitwidth.
DeltaFile
+5-3clang/lib/AST/ByteCode/Interp.cpp
+1-1clang/lib/AST/ByteCode/Interp.h
+1-0clang/test/Sema/static-init.c
+7-43 files