LLVM/project 3da80f8clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp, clang/test/Sema warn-lifetime-safety-invalidations.cpp

Improve liveness to detect more invaldiations
DeltaFile
+5-3clang/test/Sema/warn-lifetime-safety-invalidations.cpp
+6-0clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+11-32 files

LLVM/project 769b734llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVISelDAGToDAG.cpp, llvm/test/CodeGen/RISCV rv32p.ll

[RISCV] Combine ADDD with UMUL_LOHI/SMUL_LOHI into WMACCU/WMACC (#180383)

Combine the pattern:
  ADDD(addlo, addhi, UMUL_LOHI(x, y).0, UMUL_LOHI(x, y).1)
into:
  WMACCU(x, y, addlo, addhi)

And similarly for SMUL_LOHI -> WMACC.


This patch was written with AI, but I reviewed it carefully.
DeltaFile
+76-0llvm/test/CodeGen/RISCV/rv32p.ll
+60-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+37-0llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+12-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+185-04 files

LLVM/project 5c826f5llvm/lib/Target/RISCV RISCVISelLowering.cpp

[RISCV] Emit MULHU/MULHS/UMUL_LOHI/SMUL_LOHI from our custom XLen*2 expansion. (#180379)

We already do all the checks necessary in order to prioritize
MULHU/MULHS/UMUL_LOHI/SMUL_LOHI over MULHSU/WMULSU. We might as
well just emit the nodes instead of letting generic type legalization
redo the checks.

This is slightly different than the default legalization because we
don't have access to ExpandInteger so we have to emit TRUNCATES and
BUILD_PAIR. Not sure if this will result in any differences in practice.
DeltaFile
+33-24llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+33-241 files

LLVM/project c25018bllvm/docs LangRef.rst

[Docs][Intrisics] Fix the name of llvm.memset.inline in the documentation (#180373)

LLVM intrinsic `llvm.memset.inline` indicates in its name the types of
the destination pointer and the size. There is no second pointer.

Moreover, the tests are already verifying that generated code uses
`@llvm.memset.inline.p0.i32` and `@llvm.memset.inline.p0.i64`. So make
the documentation reference these names as well.

Fixes: https://github.com/llvm/llvm-project/issues/163454
DeltaFile
+4-4llvm/docs/LangRef.rst
+4-41 files

LLVM/project a563e6bllvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVISelDAGToDAG.cpp, llvm/test/CodeGen/RISCV rv32p.ll

[RISCV] Add support for forming WMULSU during type legalization. (#180331)

Add a DAG combine to turn it into MULHSU if the lower half result
is unused.
DeltaFile
+27-2llvm/test/CodeGen/RISCV/rv32p.ll
+18-2llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+17-3llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+2-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+64-74 files

LLVM/project 6324ee3llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize lcssa-crashes.ll

[VPlan] Use PredBB's terminator as insert point for VPIRPhi extracts.

Use PredBB's terminator as insert point in VPIRPhi::execute to make sure
the extracts are placed after any possibly sunk instructions.

Fixes https://github.com/llvm/llvm-project/issues/180363.
DeltaFile
+57-0llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
+1-1llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+58-12 files

LLVM/project 862663allvm/test/CodeGen/AArch64 atomic-ops-lse.ll trampoline.ll

[AArch64] Consider MOVaddr* as cheap if fuse-adrp-add

These pseudo-instructions usually translate into a pair of adrp+add and
have a single cycle latency on some micro-architectures.
DeltaFile
+88-88llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+43-34llvm/test/CodeGen/AArch64/trampoline.ll
+55-0llvm/test/CodeGen/AArch64/cheap-as-a-move-MOVaddr.ll
+34-19llvm/test/CodeGen/AArch64/machine-outliner-loh.ll
+14-12llvm/test/CodeGen/AArch64/cfguard-checks.ll
+12-10llvm/test/CodeGen/AArch64/atomic-ops.ll
+246-16310 files not shown
+294-19416 files

LLVM/project ac89dbfclang/include/clang/Analysis/Analyses/LifetimeSafety Loans.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp Checker.cpp

Field and interior paths
DeltaFile
+172-100clang/unittests/Analysis/LifetimeSafetyTest.cpp
+147-98clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h
+110-46clang/test/Sema/warn-lifetime-safety-invalidations.cpp
+46-42clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+30-47clang/lib/Analysis/LifetimeSafety/Checker.cpp
+58-9clang/lib/Analysis/LifetimeSafety/Loans.cpp
+563-3426 files not shown
+611-36712 files

LLVM/project 60ed0callvm/lib/Analysis InlineCost.cpp, llvm/test/Transforms/Inline inline-all-viable-calls.ll

Revert "[Inliner] Add option (default off) to inline all calls regardless of …"

This reverts commit 58de8f2c25291549dc1cabe364d399e564bca042.
DeltaFile
+0-114llvm/test/Transforms/Inline/inline-all-viable-calls.ll
+0-8llvm/lib/Analysis/InlineCost.cpp
+0-1222 files

LLVM/project 7509cadllvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlan.h

[VPlan] Support masked VPInsts, use for predication (NFC) (#142285)

Add support for mask operands to most VPInstructions, using
getNumOperandsForOpcode.

This allows VPlan predication to predicate VPInstructions directly. The
mask will then be dropped or handled when creating wide recipes.

Depends on https://github.com/llvm/llvm-project/pull/142284.
Depends on https://github.com/llvm/llvm-project/pull/168784.

PR: https://github.com/llvm/llvm-project/pull/142285
DeltaFile
+28-42llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+54-4llvm/lib/Transforms/Vectorize/VPlan.h
+2-48llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+42-0llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+18-14llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
+17-11llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+161-1196 files not shown
+196-16512 files

LLVM/project 4d5d2ffllvm/lib/CodeGen PreISelIntrinsicLowering.cpp, llvm/test/Transforms/PreISelIntrinsicLowering cond-loop.ll

[ProfCheck] Add prof data for lowering of @llvm.cond.loop

When there is no target-specific lowering of @llvm.cond.loop, it is
lowered into a simple loop by PreISelIntrinsicLowering. Mark the branch
weights into the no-return loop as unknown given we do not have value
metadata to fix the profcheck test for this feature.

Reviewers: mtrofin, alanzhao1, snehasish, pcc

Pull Request: https://github.com/llvm/llvm-project/pull/180390
DeltaFile
+12-4llvm/test/Transforms/PreISelIntrinsicLowering/cond-loop.ll
+6-1llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+0-1llvm/utils/profcheck-xfail.txt
+18-63 files

LLVM/project 33291ddllvm/include/llvm/IR ProfDataUtils.h, llvm/lib/IR ProfDataUtils.cpp

[ProfCheck] Add utility to get a MDNode for unknown branch weights

There are some cases where it is non-trivial to get access to a
branch/select instruction and the helper function that creates the
branch/select of interest takes in a MDNode for branch weights. Add a
helper to create a MDNode for unknown branch weights if the function is
profiled to handle this case.

Reviewers: mtrofin, snehasish, alanzhao1

Pull Request: https://github.com/llvm/llvm-project/pull/180389
DeltaFile
+12-0llvm/lib/IR/ProfDataUtils.cpp
+5-0llvm/include/llvm/IR/ProfDataUtils.h
+17-02 files

LLVM/project ed9c186llvm/test/CodeGen/Mips musttail.ll

[MIPS] musttail.ll - regenerate test checks (#180423)

DeltaFile
+38-0llvm/test/CodeGen/Mips/musttail.ll
+38-01 files

LLVM/project 1b0f139llvm/include/llvm/CodeGen LiveStacks.h, llvm/lib/CodeGen LiveStacks.cpp StackSlotColoring.cpp

Revert "[NFC][LiveStacks] Use vectors instead of map and unordred_map" (#180421)

Reverts llvm/llvm-project#165477

Break https://lab.llvm.org/buildbot/#/builders/52/builds/14874
DeltaFile
+25-19llvm/include/llvm/CodeGen/LiveStacks.h
+19-22llvm/lib/CodeGen/LiveStacks.cpp
+15-5llvm/lib/CodeGen/StackSlotColoring.cpp
+3-3llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp
+2-3llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+64-525 files

LLVM/project 8b1c6bfclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp

Address comments from Henrich
DeltaFile
+6-7clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+6-71 files

LLVM/project d7620e8llvm/include/llvm/CodeGen LiveStacks.h, llvm/lib/CodeGen LiveStacks.cpp StackSlotColoring.cpp

Revert "[NFC][LiveStacks] Use vectors instead of map and unordred_map (#165477)"

This reverts commit 1acc200d88cea309b47ab24366f12ee82f00d4d4.
DeltaFile
+25-19llvm/include/llvm/CodeGen/LiveStacks.h
+19-22llvm/lib/CodeGen/LiveStacks.cpp
+15-5llvm/lib/CodeGen/StackSlotColoring.cpp
+3-3llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp
+2-3llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+64-525 files

LLVM/project 3c5b054llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/SystemZ load-store-scalarization-cost.ll

[VPlan] Pass underlying instr to getMemoryOpCost in ::computeCost.

Pass underlying instruction to getMemoryOpCost in
VPReplicateRecipe::computeCost if UsedByLoadStoreAddress is true.
Some targets use the underlying instruction to improve costs,
and this is needed to match the legacy cost model.

Fixes https://github.com/llvm/llvm-project/issues/177780.
Fixes https://github.com/llvm/llvm-project/issues/177772.
DeltaFile
+47-7llvm/test/Transforms/LoopVectorize/SystemZ/load-store-scalarization-cost.ll
+5-4llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+52-112 files

LLVM/project a3cabfdlibcxx/include/__atomic/support gcc.h

address review comments: use builtin if possible
DeltaFile
+16-0libcxx/include/__atomic/support/gcc.h
+16-01 files

LLVM/project 3192fe2llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/X86 predicated-instruction-cost.ll

[VPlan] Fall back to legacy cost model if PtrSCEV is nullptr.

There are some cases when PtrSCEV can be nullptr. Fall back to legacy
cost model, to not call isLoopInvariant with nullptr.

Fixes a crash after 0c4f8094939d2.
DeltaFile
+54-0llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
+1-1llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+55-12 files

LLVM/project dfce3c7libcxx/include/__atomic atomic_ref.h

address review comments: use builtin if possible
DeltaFile
+8-0libcxx/include/__atomic/atomic_ref.h
+8-01 files

LLVM/project 5753661llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/AArch64 fold-reduce-add-cmp-zero.ll

Address comments 1
DeltaFile
+72-46llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+66-20llvm/test/Transforms/VectorCombine/AArch64/fold-reduce-add-cmp-zero.ll
+9-27llvm/test/Transforms/VectorCombine/RISCV/fold-reduce-add-cmp-zero.ll
+9-9llvm/test/Transforms/VectorCombine/RISCV/icmp-vector-reduce.ll
+2-2llvm/test/Transforms/VectorCombine/RISCV/fold-signbit-reduction-cmp.ll
+158-1045 files

LLVM/project b2f8a0fclang/docs ReleaseNotes.rst, clang/include/clang/AST JSONNodeDumper.h

[clang] ast-dump: dump `AvailabilityAttr` fields to JSON (#179281)

This adds `AvailabilityAttr` fields for the JSON dumper
DeltaFile
+158-0clang/test/AST/ast-dump-attr-json.cpp
+21-0clang/lib/AST/JSONNodeDumper.cpp
+16-0clang/test/AST/HLSL/ast-dump-availability-attr.hlsl
+5-0clang/docs/ReleaseNotes.rst
+1-0clang/include/clang/AST/JSONNodeDumper.h
+201-05 files

LLVM/project 0d94148llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 masked_store_trunc_ssat.ll masked_store_trunc_usat.ll

[X86] optimize 512-bit masked truncated saturating stores (#179130)

an oversight in https://github.com/llvm/llvm-project/pull/169827, for
the 512-bit version the `vl` target feature is not needed.


https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi16_storeu_epi8&expand=1811&ig_expand=2150,2151
DeltaFile
+22-24llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
+21-18llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
+2-1llvm/lib/Target/X86/X86ISelLowering.cpp
+45-433 files

LLVM/project de93668mlir/include/mlir/Bindings/Python IRAttributes.h, mlir/lib/Bindings/Python IRAttributes.cpp

[mlir][IR] `DenseElementsAttr`: Remove `i1` dense packing special case
DeltaFile
+6-92mlir/lib/Bindings/Python/IRAttributes.cpp
+6-54mlir/lib/IR/BuiltinAttributes.cpp
+1-51mlir/lib/IR/AttributeDetail.h
+0-14mlir/unittests/IR/AttributeTest.cpp
+0-12mlir/include/mlir/Bindings/Python/IRAttributes.h
+0-10mlir/test/IR/attribute-roundtrip.mlir
+13-2332 files not shown
+20-2418 files

LLVM/project a222d85mlir/include/mlir/Bindings/Python IRAttributes.h, mlir/lib/Bindings/Python IRAttributes.cpp

[mlir][IR] `DenseElementsAttr`: Remove `i1` dense packing special case
DeltaFile
+6-92mlir/lib/Bindings/Python/IRAttributes.cpp
+6-54mlir/lib/IR/BuiltinAttributes.cpp
+1-51mlir/lib/IR/AttributeDetail.h
+0-14mlir/unittests/IR/AttributeTest.cpp
+0-12mlir/include/mlir/Bindings/Python/IRAttributes.h
+0-10mlir/test/IR/attribute-roundtrip.mlir
+13-2332 files not shown
+19-2428 files

LLVM/project aff5afcclang-tools-extra/clang-tidy/bugprone StringConstructorCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix bugprone-string-constructor FN with allocators. (#180337)

Fixes https://github.com/llvm/llvm-project/issues/180324.
DeltaFile
+48-3clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor.cpp
+8-3clang-tools-extra/clang-tidy/bugprone/StringConstructorCheck.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+61-63 files

LLVM/project 706cc8blibcxx/test/std/atomics/atomics.ref address.pass.cpp assign.pass.cpp

[libc++][NFC] Fix license header in test for `atomic_ref` (#180395)

DeltaFile
+1-0libcxx/test/std/atomics/atomics.ref/address.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/assign.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/bitwise_and_assign.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/bitwise_or_assign.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/bitwise_xor_assign.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/compare_exchange_strong.pass.cpp
+6-018 files not shown
+24-024 files

LLVM/project 907f66dmlir/lib/IR BuiltinAttributes.cpp AttributeDetail.h, mlir/test/IR attribute-roundtrip.mlir parse-literal.mlir

[mlir][IR] `DenseElementsAttr`: Remove `i1` dense packing special case
DeltaFile
+6-54mlir/lib/IR/BuiltinAttributes.cpp
+1-51mlir/lib/IR/AttributeDetail.h
+0-14mlir/unittests/IR/AttributeTest.cpp
+0-10mlir/test/IR/attribute-roundtrip.mlir
+4-4mlir/test/IR/parse-literal.mlir
+11-1335 files

LLVM/project a5aa4fflibcxx/test/std/atomics/atomics.ref address.pass.cpp assign.pass.cpp

fix license header
DeltaFile
+1-0libcxx/test/std/atomics/atomics.ref/address.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/assign.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/bitwise_and_assign.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/bitwise_or_assign.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/bitwise_xor_assign.pass.cpp
+1-0libcxx/test/std/atomics/atomics.ref/compare_exchange_strong.pass.cpp
+6-018 files not shown
+24-024 files

LLVM/project 9139421llvm/test/Transforms/PreISelIntrinsicLowering cond-loop.ll

feedback

Created using spr 1.3.7
DeltaFile
+1-5llvm/test/Transforms/PreISelIntrinsicLowering/cond-loop.ll
+1-51 files