1,064,612 commits found in 103 milliseconds
[LifetimeSafety] Make `strict` a superset of `permissive` (#195068) [mlir][SPIR-V] Rename SPV_INTEL_long_constant_composite to SPV_INTEL_long_composites (#195062) LLVM /project 8dfe85b — flang/lib/Optimizer/CodeGen CodeGen.cpp, flang/test/Fir convert-memref-codegen.mlir [flang][fir] Support memref to memref fir.convert (#194954)
fir.convert of memref to memref can potentially arise due to a chain of
fir.convert between fir pointer types which get collapsed into a memref
to memref cast. Handle this as if we first convert to a pointer and then
convert the pointer to a memref. LLVM /project aae871b — llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 cgp-usubo.ll [DAGCombiner] Reconstruct borrow chain from icmp pattern for USUBO_CARRY (#193707)
DAG-level alternative to #189018 (CGP): match the canonical icmp form
carry_out = or(icmp ult A, B, and(icmp eq A, B, carry_in))
in visitOR and rewrite to USUBO_CARRY so the backend can chain the
borrow through sbb/sbcs.
Gated on USUBO_CARRY being legal/custom at the type the integer
legalizes to, so targets without hardware carry-flag support are
unaffected. For oversize integers (e.g. i128 on x86_64/aarch64) type
legalization then expands one USUBO_CARRY into a chain of
register-width USUBO_CARRYs, which gives strictly better code than the
CGP-level reconstruction.
Fixes #106118. LLVM /project cf96c9a — clang/include/clang/AST OpenMPClause.h, clang/lib/CodeGen CGOpenMPRuntime.cpp [𝘀𝗽𝗿] initial version
Created using spr 1.3.5
LLVM /project a823dc8 — clang/include/clang/AST OpenMPClause.h, clang/lib/CodeGen CGOpenMPRuntime.cpp [𝘀𝗽𝗿] changes to main this commit is based on
Created using spr 1.3.5
[skip ci]
LLVM /project 8b14e42 — clang/include/clang/AST OpenMPClause.h, clang/lib/CodeGen CGOpenMPRuntime.cpp [𝘀𝗽𝗿] changes to main this commit is based on
Created using spr 1.3.5
[skip ci]
LLVM /project 2587dd2 — clang/include/clang/AST OpenMPClause.h, clang/lib/CodeGen CGOpenMPRuntime.cpp [𝘀𝗽𝗿] initial version
Created using spr 1.3.5
LLVM /project c5a881e — clang/include/clang/AST OpenMPClause.h, clang/lib/CodeGen CGOpenMPRuntime.cpp [𝘀𝗽𝗿] changes to main this commit is based on
Created using spr 1.3.5
[skip ci]
LLVM /project 19a9232 — clang/include/clang/AST OpenMPClause.h, clang/lib/CodeGen CGOpenMPRuntime.cpp [𝘀𝗽𝗿] initial version
Created using spr 1.3.5
LLVM /project 0e998bb — clang/include/clang/AST OpenMPClause.h, clang/lib/CodeGen CGOpenMPRuntime.cpp [𝘀𝗽𝗿] changes to main this commit is based on
Created using spr 1.3.5
[skip ci]
LLVM /project 63e1d6f — clang/include/clang/AST OpenMPClause.h, clang/lib/CodeGen CGOpenMPRuntime.cpp [𝘀𝗽𝗿] initial version
Created using spr 1.3.5
LLVM /project 75e8549 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll rebase
Created using spr 1.3.5
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,562 -46,611 2,477 files
LLVM /project b46caf1 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5
[skip ci]
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,562 -46,611 2,477 files
LLVM /project 93be9c0 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll rebase
Created using spr 1.3.5
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,562 -46,611 2,477 files
LLVM /project 8242839 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5
[skip ci]
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,562 -46,611 2,477 files
LLVM /project b7b7969 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll rebase
Created using spr 1.3.5
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,562 -46,611 2,477 files
LLVM /project fe780b3 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5
[skip ci]
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,562 -46,611 2,477 files
LLVM /project bbdc7b8 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll rebase
Created using spr 1.3.5
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,562 -46,611 2,477 files
LLVM /project 8aa307d — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5
[skip ci]
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,562 -46,611 2,477 files
LLVM /project 33882f6 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll rebase
Created using spr 1.3.5
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,562 -46,611 2,477 files
LLVM /project 1f3057f — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5
[skip ci]
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,560 -46,608 2,477 files
LLVM /project 352f983 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll rebase
Created using spr 1.3.5
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,560 -46,608 2,477 files
LLVM /project cb280a4 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5
[skip ci]
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,560 -46,608 2,477 files
LLVM /project 4d1bfaa — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll rebase
Created using spr 1.3.5
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,559 -46,603 2,477 files
LLVM /project 9a50256 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5
[skip ci]
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,559 -46,603 2,477 files
LLVM /project c31c0e3 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll rebase
Created using spr 1.3.5
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,559 -46,603 2,477 files
LLVM /project 75b8417 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5
[skip ci]
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,559 -46,603 2,477 files
LLVM /project f1d2763 — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll rebase
Created using spr 1.3.5
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,559 -46,603 2,477 files
LLVM /project 2f3dedc — llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-ext-rv64.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.5
[skip ci]
Delta File +5,061 -4,162 llvm/test/CodeGen/Thumb2/mve-clmul.ll +4,652 -0 llvm/test/CodeGen/RISCV/rvp-simd-64.ll +1,519 -1,501 llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll +2,870 -0 llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll +1,433 -1,387 llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +0 -2,727 llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +15,535 -9,777 2,471 files not shown +100,559 -46,603 2,477 files