[TableGen] Merge EmitIntegerMatcher and EmitStringIntegerMatcher. NFC (#173940)
Allow an EmitIntegerMatcher to have an optional string value to make
it equivalent to EmitStringIntegerMatcher.
[mlir][Pass] Fix textual pipeline specification when generating a crashless reproducer (#173750)
Crashless reproducers currently emit an extra anchor op in the pipeline
they print out, because one gets added by `appendReproducer`. Fix this
by always adding the anchor op in the caller of `appendReproducer`.
In addition, `mlir-opt` always uses `any` as the anchor op, instead of
getting the anchor op from the `PassManager`, fix that as well so we can
test that the pipeline is reproduced as it was passed in.
[flang] Fixed hoisting order in fir.do_concurrent simplification. (#174044)
The order has to be fixed after #173502. This results in
reversing the order of `fir.alloca`, but that should be
insignificant.
[flang] Remove REQUIRES: shell lines form tests (#173339)
The shell feature only implies that we are not running on Windows now
that the internal shell feature is available everywhere. Replace it with
UNSUPPORTED: system-windows on non-portable tests so we can eventually
get rid of the feature.
[TableGen] Remove unused pattern rewriting functionality from CodeGenDAGPatterns. NFC (#174032)
This was originally added for GlobalISel and has been unused since
f84bc3793e9d1ba170a35b1909dd1057b63c2f15, 7.5 years ago.
InstCombine: Rudimentary support of shufflevector in SimplifyDemandedFPClass
This should look more like the computeKnownFPClass handling, with knowledge
of demanded vector elements.
InstCombine: Fix defining undef constant vector elts in SimplifyDemandedFPClass
Fold constants of known single class to the original constant instead of
a new constant. This avoids overdefining vector elements that were originally
undefined with the splat constant.
[SelectionDAG] Remove OPC_EmitStringInteger from isel. (#173936)
Instead emit this as an OPC_EmitInteger, but print the string
when the value is known to be 0..63 (when we don't need a VBR).
Also print the string into a comment when comments are not omitted
so it isn't lost when a VBR is needed.
[SLP]Mark and incompatible for 'xor %a, 0' operations
Xor with 0 is incompatible with and, which resulst in all zero instead
of %a
https://alive2.llvm.org/ce/z/oEVETS
Fixes #174041
InstCombine: Rudimentary support of shufflevector in SimplifyDemandedFPClass
This should look more like the computeKnownFPClass handling, with knowledge
of demanded vector elements.
Revert -mcpu fix (#174093)
Reverts #173399 and #174004.
#173399 moved MemoryBuffer::getFileOrSTDIN below the -mcpu validation to
fix the `-mcpu=help` flag , but on cross builds the first CPU is
rejected before the “file not found” diagnostic is printed. This failed
lit tests. #174004 introduced a host CPU fallback to fix the cross
compilation issue, but this still fails on NVPTX builders.
This can be revisited when a fix is found that works with the NVPTX
builders.
InstCombine: Fix defining undef constant vector elts in SimplifyDemandedFPClass
Fold constants of known single class to the original constant instead of
a new constant. This avoids overdefining vector elements that were originally
undefined with the splat constant.
InstCombine: Handle extractelement in SimplifyDemandedFPClass (#174081)
A lot of boilerplate changes are necessary to do proper elementwise
tracking like SimplifyDemandedBits
[mlir][int-range] `IntRangeNarrowingPass` was missing `SparseConstantPropagation` analysis (#174088)
This was causing it to skip nested scf ops in some cases (see `scf.for`
test). Use convenience `loadBaselineAnalyses` func.
[X86][AMX-AVX512] Add *i intrinsics for immediate variants (#173545)
The immediate variants use the low 6-bit as row index, while register
variants use low 16-bit. We cannot select the immediate variants using
the same intrinsic. So let's add new intrinsics for them.
