LLVM/project 4d3e667 — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/X86 vector-deinterleave7-i8.ll vector-interleave7-i32.ll

Merge remote-tracking branch 'upstream/main' into users/NeKon69/issue-213435-support-allocating-freeing-functions
DeltaFile
+89,147-91,827llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,378-26,402llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+29,293-0llvm/test/CodeGen/X86/vector-interleave7-i16.ll
+29,228-0llvm/test/CodeGen/X86/vector-interleaved7-i8.ll
+27,225-0llvm/test/CodeGen/X86/vector-interleave7-i32.ll
+26,140-0llvm/test/CodeGen/X86/vector-deinterleave7-i8.ll
+226,411-118,22918,358 files not shown
+1,967,511-634,73618,364 files

LLVM/project a45b8b8 — mlir/include/mlir/Dialect/GPU/IR GPUOps.td, mlir/lib/Dialect/GPU/IR InferIntRangeInterfaceImpls.cpp

[mlir][GPU] Infer ranges for launch cluster arguments (#238775)

Propagate ranges from input cluster dims to block id/dim values.
DeltaFile
+62-0mlir/test/Dialect/GPU/int-range-launch-clusters.mlir
+25-0mlir/lib/Dialect/GPU/IR/InferIntRangeInterfaceImpls.cpp
+2-2mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
+89-23 files

LLVM/project b92b309 — llvm/unittests/Passes/PassBuilderBindings PassBuilderBindingsTest.cpp, llvm/unittests/Target TargetMachineOptionsTest.cpp

[unittests] Skip target tests when the default triple is not built (#231723)

PassBuilder and TargetMachine C API tests fail when LLVM_TARGETS_TO_BUILD
does not include the default target triple. Skip them instead, and
null-initialize the PassBuilder fixture so TearDown does not dispose
uninitialized handles after a skipped SetUp.
DeltaFile
+8-8llvm/unittests/Passes/PassBuilderBindings/PassBuilderBindingsTest.cpp
+5-3llvm/unittests/Target/TargetMachineOptionsTest.cpp
+13-112 files

LLVM/project a3b0d32 — llvm/test/CodeGen/AArch64 sve-intrinsics-fp-arith-imm.ll

Fixups
DeltaFile
+3-6llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-imm.ll
+3-61 files

LLVM/project e93df83 — offload/include PluginManager.h, offload/libompaccsupport PluginManager.cpp

[Offload][Omp] Ensure correct teardown order

Use the new Offload API to ensure a proper libomptarget teardown
in case the process exits before reaching its `deinit` method.

Depending on different circumstances whether the shutdown happens
through `deinit` or through the liboffload `callback` everything
must be properly protected and allowed to be called safely multiple
times.

Assisted by Claude.
DeltaFile
+60-15offload/libomptarget/OffloadRTL.cpp
+38-0offload/test/api/runtime_teardown_shared_lib.c
+22-0offload/test/api/runtime_teardown_offload_disabled.c
+21-0offload/test/api/runtime_teardown.c
+12-3offload/libompaccsupport/PluginManager.cpp
+6-0offload/include/PluginManager.h
+159-186 files

LLVM/project 8763333 — llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp DAGCombiner.cpp, llvm/test/CodeGen/AArch64 fold-vector-lane-flags.ll

[DAG] Preserve scalar flags when folding vector constants

When a scalar operation has the same opcode and operands as a
(potentially unrelated) vector operation, the scalar operation's
flags get dropped. This patch preserves these lost flags.
DeltaFile
+41-67llvm/test/CodeGen/X86/fold-vector-lane-flags.ll
+58-30llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+1-4llvm/test/CodeGen/AArch64/fold-vector-lane-flags.ll
+2-3llvm/test/CodeGen/LoongArch/fold-vector-lane-flags.ll
+1-1llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+103-1055 files

LLVM/project f784c61 — llvm/test/CodeGen/AArch64 sve-intrinsics-fp-reduce.ll sve-intrinsics-bfloat-streaming-compatible.ll

Fixups
DeltaFile
+4-1,691llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll
+1,690-0llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-streaming-compatible.ll
+5-281llvm/test/CodeGen/AArch64/sve-intrinsics-bfloat.ll
+286-0llvm/test/CodeGen/AArch64/sve-intrinsics-fp-reduce-streaming-compatible.ll
+281-0llvm/test/CodeGen/AArch64/sve-intrinsics-bfloat-streaming-compatible.ll
+12-198llvm/test/CodeGen/AArch64/sve-intrinsics-fp-reduce.ll
+2,278-2,17066 files not shown
+3,002-2,57272 files

LLVM/project abb4497 — llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 masked_expandload.ll masked_compressstore.ll

[X86] Fix assertion for vXi8/vXi16 CompressStore/ExpandLoad for VBMI2 targets without VLX (#239606)

Prep work for #214628
DeltaFile
+207-81llvm/test/CodeGen/X86/masked_compressstore.ll
+197-0llvm/test/CodeGen/X86/masked_expandload.ll
+8-4llvm/lib/Target/X86/X86ISelLowering.cpp
+412-853 files

LLVM/project 541cafd — llvm/lib/Transforms/Vectorize VPlanConstruction.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize fold-epilogue-tail.ll

[LV] Support tail-folded epilogue loops (#208764)

Add support for tail-folding the vector epilogue loop.

The main and epilogue loops can require different vectorization
decisions, so introduce a separate cost model for the tail-folded
epilogue and allow VPlan construction and costing to operate with the
appropriate CM.

This patch enables emitting a tail-folded vector epilogue loop alongside
a non-tail-folded vector main loop.
For now, this feature requires both the main VF and epilogue VF to be
explicitly forced.
DeltaFile
+919-0llvm/test/Transforms/LoopVectorize/AArch64/fold-epilogue-tail.ll
+273-0llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
+164-39llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+58-0llvm/test/Transforms/LoopVectorize/AArch64/fold-epilogue-tail-remarks.ll
+14-9llvm/test/Transforms/LoopVectorize/fold-epilogue-tail.ll
+15-3llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+1,443-511 files not shown
+1,453-537 files

LLVM/project 873087a — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/X86 vector-deinterleave7-i8.ll vector-interleave7-i32.ll

Merge remote-tracking branch 'upstream/main' into users/NeKon69/issue-213435-support-allocating-freeing-functions
DeltaFile
+89,147-91,827llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,378-26,402llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+29,293-0llvm/test/CodeGen/X86/vector-interleave7-i16.ll
+29,228-0llvm/test/CodeGen/X86/vector-interleaved7-i8.ll
+27,225-0llvm/test/CodeGen/X86/vector-interleave7-i32.ll
+26,140-0llvm/test/CodeGen/X86/vector-deinterleave7-i8.ll
+226,411-118,22918,357 files not shown
+1,967,481-634,72018,363 files

LLVM/project f7e15cd — llvm/lib/Target/AArch64 AArch64InstrInfo.cpp, llvm/test/CodeGen/AArch64 machine-outliner-compatible-candidates.mir machine-outliner-regsave.mir

Determine what CFI to emit by looking at the existing CFI instructions
DeltaFile
+233-27llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+146-20llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir
+7-2llvm/test/CodeGen/AArch64/machine-outliner-compatible-candidates.mir
+386-493 files

LLVM/project 233b03f — offload/include RecordReplay.h, offload/libompaccsupport device.cpp Program.cpp

[Offload][Omp] Finish removing Plugin Interface from libomptarget (#239525)

This PR is mostly NFC and removes all remaining usages of the Plugin
Interface from libomptarget:

* Headers from the Plugin Interface are removed
* Remaining Plugin::Error usages were substituted by createError
* RecordReplay files were moved out of the plugins common directory
* Removed GenericPlugin from PluginManager and DeviceTy
* Changed usages of RTLDeviceID to use the OpenMP DeviceID. This is the
only change in behavior, but the previous value was probably not correct
if there were more than one plugin.
* Removed helpers to get GenericPlugin and RTLDeviceID. We still have 3
helpers remaining to transition.

Assisted by Claude.
DeltaFile
+0-468offload/plugins-nextgen/common/src/RecordReplay.cpp
+468-0offload/libompaccsupport/RecordReplay.cpp
+0-343offload/plugins-nextgen/common/include/RecordReplay.h
+343-0offload/include/RecordReplay.h
+36-35offload/libompaccsupport/Program.cpp
+4-9offload/libompaccsupport/device.cpp
+851-8559 files not shown
+857-89815 files

LLVM/project 8751432 — llvm/test/CodeGen/X86/apx reloc-opt.ll

[X86][APX] Test the relocation of an NF add

test_regclass_not_updated_by_regalloc_2 only produced an NDD/NF add
with a GOT operand because the allocator happened to give the add a
destination different from its source. With SlotIndexes compaction it
picks the same register, so the add is compressed to the legacy form
and the CODE_6 TODO lost its test.

Add a function whose add keeps its source live, so it stays NDD and
becomes NF under any allocation.
DeltaFile
+20-1llvm/test/CodeGen/X86/apx/reloc-opt.ll
+20-11 files

LLVM/project 4e2a2db — llvm/test/CodeGen/X86 vector-interleaved-load-i32-stride-8.ll vector-interleaved-load-i16-stride-7.ll

[X86] Enable SlotIndexes compaction by default

Compacting SlotIndexes before greedy allocation drops the entries of
erased instructions, so live range sizes and instruction distances
reflect the code being allocated rather than how much was erased
before it. AMDGPU has done this since #235806; do the same for X86.

Codegen changes only through allocation: no new crashes, verifier
errors or allocation failures in the lit suites, including
EXPENSIVE_CHECKS, and a stage-2 build of LLVM, clang and lld with
-verify-machineinstrs passes its own tests. On llvm-test-suite at -O3,
spills drop 0.3% and .text 0.06%, with compile time unchanged.

Most test updates are regenerated checks. misched-matmul now inserts
20 spills instead of 24. live-debug-vars-stale-slotindexes.mir gets
one more use of %27 so that accumulate_fit still reaches the stale
index path it was written for.
DeltaFile
+15,403-15,465llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+13,329-13,243llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+13,199-13,231llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
+12,788-12,826llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
+11,796-11,778llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
+11,057-11,064llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
+77,572-77,607447 files not shown
+344,092-345,738453 files

LLVM/project ee60ffd — llvm/include/llvm/Analysis LoopAccessAnalysis.h, llvm/lib/Analysis LoopAccessAnalysis.cpp

[LAA] Fix missing RT checks for unknown deps via non-header phis. (#230292)

Keep track of MemAccesses so we can map dependence source/sink directly
to them, instead of going through the pointers of the source and dest
instructions.

This allows correctly removing dependences.

Previously, pointers to non-header phis were not handled correctly: the
MemAccess in the map would refer to the translated pointer, which is
different to the pointer phi.
DeltaFile
+9-4llvm/test/Analysis/LoopAccessAnalysis/retry-runtime-checks-after-dependence-analysis.ll
+9-4llvm/lib/Analysis/LoopAccessAnalysis.cpp
+6-0llvm/include/llvm/Analysis/LoopAccessAnalysis.h
+24-83 files

LLVM/project 4a4d1be — lldb/source/Plugins/Process/gdb-remote GDBRemoteCommunication.cpp GDBRemoteCommunication.h

[LLDB] Clarify packet search state comments (#239415)

Document the buffer size recorded with the packet search cursor and
clarify that compression causes the search to restart. Address the
comment nits from the review of #238530.
DeltaFile
+1-1lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
+2-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.h
+3-12 files

LLVM/project 80a5c4d — clang/lib/AST ItaniumMangle.cpp, clang/test/CodeGenCXX mangle-exprs.cpp

[Clang] Fix new initializer list mangling (#232629)

Clang was adding the initializer-list marker twice when mangling an
expression such as `new std::initializer_list<int>{1}`.

Unwraped the compiler created init list expression and mangled its
elements only once.

Fixes #232531
DeltaFile
+19-1clang/test/CodeGenCXX/mangle-exprs.cpp
+2-0clang/lib/AST/ItaniumMangle.cpp
+21-12 files

LLVM/project 933cf18 — llvm/test/CodeGen/AArch64 fold-vector-lane-flags.ll, llvm/test/CodeGen/LoongArch fold-vector-lane-flags.ll

[NFC][DAG] Precommit tests that drop flags from vector ops
DeltaFile
+503-0llvm/test/CodeGen/X86/fold-vector-lane-flags.ll
+87-0llvm/test/CodeGen/AArch64/fold-vector-lane-flags.ll
+21-0llvm/test/CodeGen/LoongArch/fold-vector-lane-flags.ll
+611-03 files

LLVM/project 96bba6a — clang/include/clang/Analysis/Analyses/LifetimeSafety Loans.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

cleanup code, add edge case
DeltaFile
+36-6clang/test/Sema/LifetimeSafety/safety.cpp
+3-8clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+6-5clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h
+1-4clang/lib/Sema/SemaLifetimeSafety.h
+46-234 files

LLVM/project 6d325a5 — clang/docs ReleaseNotes.md, clang/include/clang/AST DeclBase.h DeclCXX.h

Increase the limit for ctor initializers (#239011)

The below bug reports that we 'assert'/silently fail when given too many
initializers. Also, that the limit of 2^^16 was too small in some
generated code.

This patch promotes the 'constructor initializer' limit from a bitfield
to a member of the
CXXConstructorDecl, providing 32 bits for storage.

Additionally, it moves the DeductionCandidateKind into the decl type
itself, which adds
an additional couple of bits to the available list for FunctionDecl and
its derivatives (since it
was easy, and was harder to remove from this patch after a large
refactor).

Fixes: #219366


    [2 lines not shown]
DeltaFile
+24-16clang/include/clang/AST/DeclCXX.h
+5-18clang/include/clang/AST/DeclBase.h
+3-3clang/lib/Serialization/ASTWriterDecl.cpp
+0-2clang/lib/AST/Decl.cpp
+1-1clang/lib/Serialization/ASTReaderDecl.cpp
+2-0clang/docs/ReleaseNotes.md
+35-406 files

LLVM/project ad62c8c — llvm/test/CodeGen/X86 masked_compressstore_bf16.ll masked_compressstore_f16.ll

[X86] Add f16/bf16 expandload/compressstore test coverage for #214628 (#239592)
DeltaFile
+3,007-0llvm/test/CodeGen/X86/masked_expandload_f16.ll
+2,835-0llvm/test/CodeGen/X86/masked_expandload_bf16.ll
+2,656-0llvm/test/CodeGen/X86/masked_compressstore_f16.ll
+2,371-0llvm/test/CodeGen/X86/masked_compressstore_bf16.ll
+10,869-04 files

LLVM/project a096a2b — llvm/test/CodeGen/AArch64/GlobalISel invoke-result-phi.ll

[GlobalISel][AArch64][NFC] address review comments (#239558)

Address comments from from #234603.
DeltaFile
+1-2llvm/test/CodeGen/AArch64/GlobalISel/invoke-result-phi.ll
+1-21 files

LLVM/project 8dc7f75 — clang/lib/AST/ByteCode Descriptor.cpp Pointer.h, clang/test/SemaCXX ext-int-vector.cpp

[clang][bytecode] Always check the source pointer in `Memcpy()` (#239563)

Loading from an uninitialized pointer will otherwise cause us problems
later.
Make empty record fields be initialized by default, so we don't diagnose
those. Also add the initialization state to `Pointer::operator<<`.

This fixes `SemaCXX/ext-int-vector.cpp`.
DeltaFile
+2-6clang/lib/AST/ByteCode/Interp.cpp
+4-1clang/lib/AST/ByteCode/Record.h
+4-0clang/lib/AST/ByteCode/Pointer.h
+2-1clang/lib/AST/ByteCode/Descriptor.cpp
+1-0clang/test/SemaCXX/ext-int-vector.cpp
+13-85 files

LLVM/project 3f7ff71 — mlir/include/mlir/Dialect/Vector/IR VectorOps.td, mlir/lib/Dialect/Vector/IR VectorOps.cpp

[mlir][vector] Consistently name Vector op results (#238070)

This continues the cleanup tracked in #131602.

Use result consistently in Vector op definitions, replacing names such
as dest and res. For DeinterleaveOp, rename res1 and res2 to resultEven
and resultOdd, respectively, to reflect their contents.
DeltaFile
+28-28mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
+12-12mlir/test/Dialect/Vector/CPU/ArmSVE/vector-smmla.mlir
+11-11mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+6-6mlir/test/Dialect/Vector/CPU/ArmSVE/vector-usmmla.mlir
+6-6mlir/test/Dialect/Vector/CPU/ArmSVE/vector-ummla.mlir
+6-6mlir/test/Dialect/Vector/CPU/ArmSVE/vector-bfmmla.mlir
+69-6911 files not shown
+93-9317 files

LLVM/project c53809f — llvm/test/CodeGen/AMDGPU async-barrier-replay-inline-asm.ll

[AMDGPU] Exercise replay warning across inline asm blocks

Use the recognized EXEC-zero B8 workaround in the later block so the
fixture distinguishes per-block recognition from a combined sequence.
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/async-barrier-replay-inline-asm.ll
+1-11 files

LLVM/project 703cb5b — clang/test/Interpreter/CUDA emit-llvm.cu

[clang-repl] Accept the 32-bit NVPTX triple in the CUDA emit-llvm test (#239329)

The CUDA device triple is nvptx-nvidia-cuda on 32-bit host. emit-llvm.cu
currently fails on its check for nvptx64-nvidia-cuda. Accept both
triples, as done in clang/test/Driver/cl-options.cu.
DeltaFile
+1-1clang/test/Interpreter/CUDA/emit-llvm.cu
+1-11 files

LLVM/project b74d59f — llvm/utils/gn/secondary/libcxx/include BUILD.gn, llvm/utils/gn/secondary/libcxx/src BUILD.gn

[gn] port fed3c60941ab (#239595)
DeltaFile
+0-4llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+1-3llvm/utils/gn/secondary/libcxx/src/BUILD.gn
+1-72 files

LLVM/project 679b0e1 — offload/liboffload/API Common.td, offload/liboffload/src OffloadImpl.cpp

[Offload] Add shutdown callbacks to liboffload

When Platforms are initialized liboffload sets an atexit handler that
ensures that is deinitialized before deinitialazing platforms.
Because this happens lazily, a library using offload that wants to
run some of its shutdown needs to properly setup its atexit handler
after the liboffload one (because they're called in reverse order).

This requires to know precisely the internal implementation of liboffload.

Instead of requiring that, this PR adds an API that allows the users
of liboffload to register their own deinit code and be assured that it will
be called before liboffload shutdowns independently of when platforms
are initialized.

Assisted by Claude.
DeltaFile
+211-0offload/unittests/OffloadAPI/init/olInit.cpp
+33-1offload/liboffload/src/OffloadImpl.cpp
+31-0offload/liboffload/API/Common.td
+275-13 files

LLVM/project ed282c8 — llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU BUILD.gn

[gn] port 0bd6ddc92cf4 (#239596)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
+1-01 files

LLVM/project 58f0108 — llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV/pointers phi-select-retyped-null-operand.ll

[SPIR-V] Revalidate PHI and select operands after retyping them (#239343)
DeltaFile
+85-0llvm/test/CodeGen/SPIRV/pointers/phi-select-retyped-null-operand.ll
+21-0llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+106-02 files