LLVM/project 37aca9dllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 vector-interleave-build-vector.ll

[AArch64] Fold interleave of build_vector (#214403)
DeltaFile
+214-0llvm/test/CodeGen/AArch64/vector-interleave-build-vector.ll
+27-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+241-02 files

LLVM/project 271eee9llvm/utils/lit/lit TestRunner.py, llvm/utils/lit/tests/Inputs/shtest-env-positive env-u.txt mixed.txt

[lit] Stop bare env from short-circuiting the pipeline (#214512)

env with no trailing subcommand returns early from _executeShCmd,
skipping the rest of the pipeline. A RUN line like env | FileCheck never
runs FileCheck.

Runs it as an in-process pipeline stage instead, reusing the existing
InProcessPipe implementation.

Fixes #115578.

Also fixes six Inputs/shtest-env-positive fixtures that could never have
passed once FileCheck actually ran. Five expected KEY = VALUE from
FileCheck while env has always printed KEY=VALUE. Two RUN lines used a
check-prefix that matched no CHECK line in the file. One needed
--allow-empty since env -i produces no output at all.
DeltaFile
+81-49llvm/utils/lit/lit/TestRunner.py
+7-7llvm/utils/lit/tests/Inputs/shtest-env-positive/env-calls-env.txt
+5-5llvm/utils/lit/tests/Inputs/shtest-env-positive/env-i.txt
+4-4llvm/utils/lit/tests/Inputs/shtest-env-positive/mixed.txt
+4-4llvm/utils/lit/tests/Inputs/shtest-env-positive/env.txt
+3-3llvm/utils/lit/tests/Inputs/shtest-env-positive/env-u.txt
+104-721 files not shown
+105-747 files

LLVM/project 7977cb0clang/lib/Sema SemaModule.cpp, clang/test/Modules GH204633.cppm

[C++20] [Modules] Diagnose invalid module interface for implementation unit (#215448)
DeltaFile
+4-4clang/test/Modules/GH204633.cppm
+3-1clang/lib/Sema/SemaModule.cpp
+7-52 files

LLVM/project 804a213llvm/include/llvm/ExecutionEngine/Orc EPCGenericDylibManager.h, llvm/include/llvm/ExecutionEngine/Orc/Shared OrcRTBridge.h

[ORC] Standardize dylib manager on NativeDylibManager names (#215441)

The in-tree SimpleExecutorDylibManager now publishes a single controller
interface -- the ORC runtime's NativeDylibManager symbol names -- which
EPCGenericDylibManager targets, dropping the parallel LLVM-style
SimpleExecutorDylibManager_* names and the Create path that used them.
Follow-up to the EPCGenericDylibManager proxy refactor, which already
routed both name sets through the same code.

Details:

* Remove EPCGenericDylibManager::CreateWithDefaultBootstrapSymbols.
SimpleRemoteEPC and lli now construct via Create(ExecutionSession&),
which resolves the NativeDylibManager names in the session's bootstrap
JITDylib.

* Remove the SimpleExecutorDylibManager{Instance,Open,Resolve}
bootstrap-name constants from OrcRTBridge. SimpleExecutorDylibManager
previously published both name sets and now publishes only the

    [4 lines not shown]
DeltaFile
+0-23llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp
+9-14llvm/tools/lli/ForwardingMemoryManager.h
+4-12llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.cpp
+0-7llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
+0-5llvm/include/llvm/ExecutionEngine/Orc/EPCGenericDylibManager.h
+0-4llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
+13-651 files not shown
+14-667 files

LLVM/project 5af96c6llvm/test/CodeGen/AMDGPU flat-saddr-atomics.ll llvm.amdgcn.wmma.imm.gfx1250.w32.ll

[AMDGPU] Use another sequence for initial unclaused vmem
DeltaFile
+500-250llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+464-232llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+392-196llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+366-183llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+348-174llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+332-166llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+2,402-1,201205 files not shown
+12,910-6,461211 files

LLVM/project 6ef7561llvm/lib/DWARFCFIChecker DWARFCFIAnalysis.cpp, llvm/test/DWARFCFIChecker/X86 single-func.s single-func-cfa-mistake.s

[DWARFCFIChecker] Changing register initial status as undefined  (#209032)

As per DWARF spec 6.4.1. Users can overwrite this default assumption inside the prologue.
DeltaFile
+7-17llvm/lib/DWARFCFIChecker/DWARFCFIAnalysis.cpp
+3-4llvm/test/DWARFCFIChecker/X86/nested-frames.s
+0-4llvm/test/DWARFCFIChecker/X86/single-func.s
+0-4llvm/test/DWARFCFIChecker/X86/single-func-cfa-mistake.s
+0-4llvm/test/DWARFCFIChecker/X86/cfa-corner-cases.s
+2-2llvm/test/DWARFCFIChecker/X86/single-func-missed-cfi-directive.s
+12-356 files

LLVM/project b1c8447mlir/lib/Conversion/IndexToSPIRV IndexToSPIRV.cpp, mlir/test/Conversion/IndexToSPIRV index-to-spirv.mlir

[mlir][SPIR-V] Fix swapped select operands in index.floordivs lowering (#214770)

Fix ConvertIndexFloorDivSPattern to select `negRes` when `cmp` is true

Previously operands were reversed, producing the wrong sign for the
floordiv result whenever the negative result branch should've been taken
DeltaFile
+1-1mlir/test/Conversion/IndexToSPIRV/index-to-spirv.mlir
+1-1mlir/lib/Conversion/IndexToSPIRV/IndexToSPIRV.cpp
+2-22 files

LLVM/project dce785dclang/test/CIR/CodeGen call-conv-lowering-x86_64-member-ptr.cpp call-conv-lowering-x86_64-abi-compat.c

[CIR] Drop the call-conv lowering flag from the new CodeGen tests

The two CodeGen tests this branch adds ask for the pass with
`-clangir-enable-call-conv-lowering`, which no longer exists.  The pass
now runs by default, so the RUN lines do not need a flag at all and get
the same lowering without one.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+2-2clang/test/CIR/CodeGen/call-conv-lowering-x86_64-member-ptr.cpp
+2-2clang/test/CIR/CodeGen/call-conv-lowering-x86_64-abi-compat.c
+4-42 files

LLVM/project 2b68cf5clang/test/CodeGen/LoongArch/lasx builtin.c builtin-alias.c, llvm/lib/Target/AArch64 AArch64SchedHIP12.td

Merge branch 'main' into users/adams381/cir-callconv-x86_64-leaf-floats
DeltaFile
+6,869-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-sve-instructions.s
+2,728-2,728clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+2,724-2,724clang/test/CodeGen/LoongArch/lasx/builtin.c
+5,269-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-writeback.s
+3,354-0llvm/lib/Target/AArch64/AArch64SchedHIP12.td
+3,159-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-neon-instructions.s
+24,103-5,4521,635 files not shown
+86,558-35,0841,641 files

LLVM/project 2bab21fclang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp

address review
DeltaFile
+3-1clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+3-11 files

LLVM/project cb9c454.github/workflows libcxx-benchmark-cron.yml

[libc++][NFC] Rename job in benchmark cron (#215442)

To avoid appearing as if the job is running the actual benchmarks.
DeltaFile
+1-1.github/workflows/libcxx-benchmark-cron.yml
+1-11 files

LLVM/project 84afdb7clang/test/CIR/CodeGen pointer-to-member-func-cmp.cpp enum-bool.cpp

[CIR] Enable x86_64 calling-convention lowering by default (#215026)

x86_64 calling-convention lowering has been opt-in behind
`-clangir-enable-call-conv-lowering` since it landed, so nothing reaches
the pass unless a test asks for it. The ClangIR default path therefore
emits high-level signatures that do not match SysV: a 32-byte struct
return stays first-class instead of going out through `sret`, and a
one-eightbyte struct argument is passed as a record instead of being
coerced to `i64`.

This change turns the pass on by default for x86_64 and renames the flag
to a `BoolFOption` pair, `-fclangir-call-conv-lowering` and
`-fno-clangir-call-conv-lowering`. The last flag on the command line
wins, so a build can disable the pass globally and re-enable it for one
translation unit.

Flipping the default breaks 147 of 949 CIR tests. 37 tests are CHECK
regenerations where lowering moved toward classic CodeGen. 110 tests are
quarantined by adding the disable flag to the RUN lines that turn the

    [12 lines not shown]
DeltaFile
+45-38clang/test/CIR/CodeGen/pointer-to-member-func-cast.cpp
+51-18clang/test/CIR/CodeGen/call.c
+37-19clang/test/CIR/CodeGen/lambda.cpp
+34-8clang/test/CIR/CodeGen/call.cpp
+13-24clang/test/CIR/CodeGen/enum-bool.cpp
+24-12clang/test/CIR/CodeGen/pointer-to-member-func-cmp.cpp
+204-119152 files not shown
+975-568158 files

LLVM/project d95ab96llvm/lib/Transforms/Utils SimplifyLibCalls.cpp, llvm/test/Transforms/InstCombine sincos-double-float-shrink.ll

[SimplifyLibCalls] Shrink llvm.sincos.f64 to llvm.sincos.f32 (#211218)

The double -> float shrink in LibCallSimplifier::optimizeCall only knows
about Intrinsic::sin and Intrinsic::cos, so once InstCombine combines a
sin/cos pair into llvm.sincos the fpext/fptrunc pair is left in place
and the work is done at double precision.

Handle Intrinsic::sincos too, behind the same UnsafeFPShrink gate. It
needs its own helper rather than optimizeDoubleFP because sincos returns
a struct: the results are read back through extractvalue instead of
being used directly, and the narrowed call has to be rebuilt as a
struct. InstCombine folds the resulting extractvalue/insertvalue pairs
away, so the sin/cos pair in the reported case now ends up as a single
llvm.sincos.f32 call.

NOTE: reported as a 2-2.5% regression on SPEC17 526.blender with -flto
-ffast-math on neoverse-v2 in #194616.

Assisted-by: Opus 4.8
DeltaFile
+190-0llvm/test/Transforms/InstCombine/sincos-double-float-shrink.ll
+45-0llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
+235-02 files

LLVM/project 0d75e83.github/workflows libcxx-pr-benchmark.yml libcxx-benchmark-commit.yml, libcxx/utils/ci/lnt README.md machines.json

[libc++][CI] Add a cron job to trigger benchmarking jobs (#212859)

This patch introduces a GitHub workflow that runs on a schedule and
determines which benchmarking jobs to trigger to fill the LNT instances
with performance data.

As a drive-by, it also consolidates the information describing libc++
LNT machines into a single JSON file.

The added cron workflow will run every hour, but since the benchmarks
typically take more than an hour to run, it is expected that some of
those triggers will not actually trigger new jobs.
DeltaFile
+138-0.github/workflows/libcxx-benchmark-cron.yml
+13-23.github/workflows/libcxx-benchmark-commit.yml
+31-0libcxx/utils/ci/lnt/machines.json
+17-13.github/workflows/libcxx-pr-benchmark.yml
+10-0libcxx/utils/ci/lnt/README.md
+209-365 files

LLVM/project b5babd1llvm/lib/Target/NVPTX NVPTXPassRegistry.def NVPTXTargetMachine.cpp

[NVPTX] Add NewPM boilerplate to NVPTXLowerAlloca (#215323)
DeltaFile
+29-22llvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp
+8-2llvm/lib/Target/NVPTX/NVPTX.h
+3-3llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+1-0llvm/lib/Target/NVPTX/NVPTXPassRegistry.def
+41-274 files

LLVM/project f127b4cutils/bazel/llvm-project-overlay/clang BUILD.bazel

[Bazel] Fixes 3fe75b6 (#215433)

This fixes 3fe75b62c3a9773c121b2f933e04ef594ea7821e (#199297).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=3fe75b62c3a9773c121b2f933e04ef594ea7821e

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+2-0utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+2-01 files

LLVM/project 1f105fbllvm/unittests/CAS CMakeLists.txt PluginCASTest.cpp

[Test][CAS] Fix PluginCASTest DLL discovery on Windows multi-config generators and MinGW config (#215099)

The test was computing the plugin path by walking up 3 directory levels
from the test executable to reach the build root, then appending
bin/CASPluginTest.dll. This fails on MSVC multi-config builds where an
extra Release/ subdirectory exists. Place the plugin library next to
the test executable instead, matching the pattern used by the Passes
plugin tests.

Also fix MinGW config, in mingw build configurations, the plugin is
named libCASTestPlugin.dll, while it resides in the bin directory.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply at anthropic.com>

---------

Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
DeltaFile
+4-7llvm/unittests/CAS/PluginCASTest.cpp
+7-0llvm/unittests/CAS/CMakeLists.txt
+11-72 files

LLVM/project e223260llvm/include/llvm/ExecutionEngine/Orc EPCGenericDylibManager.h, llvm/include/llvm/ExecutionEngine/Orc/Shared OrcRTBridge.h

[ORC] Reimplement EPCGenericDylibManager on RTBridge proxies (#215256)

Reimplement EPCGenericDylibManager's open/resolve operations using
rt::Proxy objects rather than direct
ExecutorProcessControl::callSPSWrapper* calls, bringing it in line with
the other RTBridge-based executor accessors. Behavior is unchanged; the
public open/lookup surface is the same aside from the removals noted
below.

Implementation details:

* The SymbolAddrs struct (three ExecutorAddrs) becomes Bindings: the
manager instance address plus rt::Proxy handles for open and resolve.
Bindings members are protocol-agnostic, so a client can build their own
for another protocol and pass them to the constructor; Create resolves
them via buildProxies against a JITDylib / the bootstrap JITDylib.

* open/resolve return SPSExpected, so this relies on the proxy layer's
Error/Expected support to deliver a single flattened Expected, replacing

    [14 lines not shown]
DeltaFile
+51-60llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp
+36-35llvm/include/llvm/ExecutionEngine/Orc/EPCGenericDylibManager.h
+17-9llvm/tools/lli/ForwardingMemoryManager.h
+11-12llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.cpp
+7-12llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
+4-6llvm/unittests/ExecutionEngine/Orc/EPCGenericDylibManagerTest.cpp
+126-1342 files not shown
+131-1468 files

LLVM/project 0750948clang/test/CodeGen/LoongArch/lasx builtin.c builtin-alias.c, llvm/lib/Target/AArch64 AArch64SchedHIP12.td

add test

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+6,869-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-sve-instructions.s
+2,728-2,728clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+2,724-2,724clang/test/CodeGen/LoongArch/lasx/builtin.c
+5,269-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-writeback.s
+3,354-0llvm/lib/Target/AArch64/AArch64SchedHIP12.td
+3,159-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-neon-instructions.s
+24,103-5,4521,372 files not shown
+81,010-30,0701,378 files

LLVM/project 5f7b217clang/test/CodeGen/LoongArch/lasx builtin.c builtin-alias.c, llvm/lib/Target/AArch64 AArch64SchedHIP12.td

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1-arichardson

[skip ci]
DeltaFile
+6,869-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-sve-instructions.s
+2,728-2,728clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+2,724-2,724clang/test/CodeGen/LoongArch/lasx/builtin.c
+5,269-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-writeback.s
+3,354-0llvm/lib/Target/AArch64/AArch64SchedHIP12.td
+3,159-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-neon-instructions.s
+24,103-5,4521,371 files not shown
+80,986-30,0701,377 files

LLVM/project 8a75be2llvm/lib/Target/Hexagon HexagonConstExtenders.cpp, llvm/test/CodeGen/Hexagon cext-cmovei-32bit.mir

[Hexagon] Fix reg class for C2_cmoveit/cmoveif cext lowering (#212911)

HexagonConstExtenders::getDirectRegReplacement mapped C2_cmoveit and
C2_cmoveif (32-bit predicated immediate moves into IntRegs) to A2_tfrpt
/ A2_tfrpf - the 64-bit DoubleRegs predicated transfers. When the
const-extender pass found a shared extended immediate profitable to
hoist into a register, it rewrote

    %d:intregs = C2_cmoveit %p:predregs, #imm

into

    %d:intregs = A2_tfrpt %p:predregs, %hoisted:intregs   (BAD)

producing a paired-register transfer with IntRegs operands and tripping
the machine verifier:

    Bad machine code: Illegal virtual register for instruction
    Expected a DoubleRegs register, but got a IntRegs register

    [9 lines not shown]
DeltaFile
+45-0llvm/test/CodeGen/Hexagon/cext-cmovei-32bit.mir
+4-2llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+49-22 files

LLVM/project 60a894ellvm/include/llvm/SandboxIR Utils.h, llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer SeedCollector.h

[SandboxVec][SeedCollector] Fix seed insert if can't determine mem access distance (#213807)

Up until now we would insert a memory instruction in a MemSeedBundle
even if we could not determine the access distance against the existing
bundle instructionss. This was causing a crash in the invocation of
upper_bound() as the vector could no longer be partitioned.

The fix is to extend the functions that check the memory access ordering
to return nullopt when the access difference can't be determined.
DeltaFile
+64-4llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SeedCollectorTest.cpp
+15-5llvm/unittests/SandboxIR/UtilsTest.cpp
+13-6llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/SeedCollector.h
+8-7llvm/include/llvm/SandboxIR/Utils.h
+14-0llvm/test/Transforms/SandboxVectorizer/Passes/SeedCollection/seed_collection.ll
+1-1llvm/lib/Transforms/Vectorize/SandboxVectorizer/SeedCollector.cpp
+115-236 files

LLVM/project 3fd375flldb/include/lldb/Utility Listener.h, lldb/source/Core Debugger.cpp

[lldb] Use StringRef when creating Listeners (#214863)

This is primarily motivated to remove the last ConstString from
Debugger.cpp. It would have been possible to write this change without
changing Listener, but then I noticed a few places where we would have
benefitted from changing the interface.
DeltaFile
+4-5lldb/source/Core/Debugger.cpp
+4-4lldb/source/Target/Target.cpp
+3-3lldb/source/Utility/Listener.cpp
+2-2lldb/include/lldb/Utility/Listener.h
+1-1lldb/source/Target/Process.cpp
+14-155 files

LLVM/project 11cffdallvm/docs Telemetry.md CMakePrimer.md, llvm/docs/RISCV RISCVVectorExtension.md

[docs] Finish MyST migration for selected LLVM docs (#214618)

Tracking issue: #201242
See the [migration guide] for more information. 

[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is a stacked PR based on #214616 , which will be a standalone
commit that
renames *.rst -> *.md before this PR lands for history preservation
purposes.

This was prepared with rst2myst plus LLM-assisted cleanup. I paged
through all the generated HTML looking for migration artifacts, and all
of the differences I could find appear to be formatting error
corrections.
DeltaFile
+557-483llvm/docs/RISCVUsage.md
+501-452llvm/docs/LFI.md
+256-258llvm/docs/yaml2obj.md
+214-235llvm/docs/CMakePrimer.md
+200-230llvm/docs/RISCV/RISCVVectorExtension.md
+174-182llvm/docs/Telemetry.md
+1,902-1,84014 files not shown
+3,032-3,05020 files

LLVM/project ebdda1ellvm/docs SymbolizerMarkupFormat.rst SymbolizerMarkupFormat.md

[docs] Rename selected LLVM docs to Markdown (#214616)

Tracking issue: #201242
See the [migration guide] for more information. 

[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines

This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
DeltaFile
+0-721llvm/docs/RISCVUsage.rst
+721-0llvm/docs/RISCVUsage.md
+0-672llvm/docs/LFI.rst
+672-0llvm/docs/LFI.md
+0-439llvm/docs/SymbolizerMarkupFormat.rst
+439-0llvm/docs/SymbolizerMarkupFormat.md
+1,832-1,83234 files not shown
+5,153-5,15340 files

LLVM/project debe28dclang/test/CodeGen/LoongArch/lasx builtin.c builtin-alias.c, llvm/lib/Target/AArch64 AArch64SchedHIP12.td

rebase now that dependency has landed

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+6,869-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-sve-instructions.s
+2,728-2,728clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+2,724-2,724clang/test/CodeGen/LoongArch/lasx/builtin.c
+5,269-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-writeback.s
+3,354-0llvm/lib/Target/AArch64/AArch64SchedHIP12.td
+3,159-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-neon-instructions.s
+24,103-5,4521,367 files not shown
+80,852-29,9881,373 files

LLVM/project f308e0cclang/test/CodeGen/LoongArch/lasx builtin.c builtin-alias.c, llvm/lib/Target/AArch64 AArch64SchedHIP12.td

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1-arichardson

[skip ci]
DeltaFile
+6,869-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-sve-instructions.s
+2,728-2,728clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+2,724-2,724clang/test/CodeGen/LoongArch/lasx/builtin.c
+5,269-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-writeback.s
+3,354-0llvm/lib/Target/AArch64/AArch64SchedHIP12.td
+3,159-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-neon-instructions.s
+24,103-5,4521,367 files not shown
+80,852-29,9881,373 files

LLVM/project 3fe75b6clang/include/clang/Basic DiagnosticCodeGenKinds.td, clang/lib/CIR/FrontendAction CIRGenAction.cpp CIRDiagnosticHandler.h

[CIR] Route MLIR diagnostics through clang::DiagnosticsEngine (#199297)

Install a scoped MLIR diagnostic handler on the CIRGenerator's
MLIRContext that translates mlir::Diagnostic severity and location to
clang diag IDs and SourceLocation, so CIR pass / verifier / lowering
errors surface in clang's standard format and respect -W/-R flags.

Disable MLIR multithreading on that context (DiagnosticsEngine is not
thread-safe). Gate the generic CIR-to-CIR fallback errors on
hasErrorOccurred() to avoid double-printing alongside specific routed
diagnostics.
DeltaFile
+245-0clang/unittests/CIR/CIRDiagnosticHandlerTest.cpp
+100-0clang/lib/CIR/FrontendAction/CIRDiagnosticHandler.cpp
+53-0clang/lib/CIR/FrontendAction/CIRDiagnosticHandler.h
+34-0clang/include/clang/Basic/DiagnosticCodeGenKinds.td
+18-4clang/lib/CIR/FrontendAction/CIRGenAction.cpp
+20-0clang/test/CIR/Diagnostics/mlir-error-routing.cu
+470-412 files not shown
+506-1318 files

LLVM/project e88a743llvm/docs SymbolizerMarkupFormat.rst SymbolizerMarkupFormat.md

[docs] Rename selected LLVM docs to Markdown
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+0-721llvm/docs/RISCVUsage.rst
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