[DAGCombiner] Narrow the integer source of sint_to_fp
Truncate the source of a `sint_to_fp` when it is known to fit in a narrower
type the target can convert from directly.
For example:
```
sitofp (sext i32 %x to i64) to float
```
On AMDGPU this becomes a single `v_cvt_f32_i32` instead of the generic
i64 to f32 expansion.
Note: X86 marks i16 sint_to_fp as Custom, but SSE only supports conversion from
i32, so the custom lowering sign-extends i16 back to i32. Mark i16 as
undesirable to avoid a redundant movswl.
[CIR] Reject language address spaces in DirectToLLVM pointer conversion
Reject unlowered language address spaces in pointer types when bypassing TargetLowering. Guard pointer-producing lowerings, including generated patterns, so failed conversions report legalization failures instead of silently selecting address space zero or constructing invalid LLVM operations.
Assisted-by: Codex / GPT-6
[ORC] Move Mangler functions into header. (#224209)
Move Mangler functions into Mangler.h so that they can be used from
OrcTargetProcess without introducing a dependence on OrcJIT.
This is a temporary fix to enable use of SymbolNameSpec in
OrcTargetProcess (see https://github.com/llvm/llvm-project/pull/224188).
Future work will reorganize these libraries and should allow this code
to sink back down into a .cpp file.
[CIR] Propagate initializer type adjustment failures
Reject initializers whose active members have no LLVM representation, including when an enclosing union's storage type is convertible. Propagate recursive adjustment failures before querying data layout or constructing LLVM operations.
Assisted-by: Codex / GPT-6
[CIR] Propagate type conversion failures in DirectToLLVM
Propagate failed type and constant conversions through DirectToLLVM so unsupported types produce legalization failures instead of invalid LLVM operations or a void function result.
Assisted-by: Codex / GPT-6
[SCEV] Look thru more expressions in isKnownMultipleOf (#219951)
Generalize the existing logic to look through AddRecs to look through
Add, Mul, and MinMax expressions in isKnownMultipleOf, noting that this
simply increases precision of added predicates, allowing us to add more
fine-grained predicates. It also fixes an underlying bug in the case the
AddRec wraps. The patch has no optimization impact at the moment, and
only serves to have higher precision in its sole user,
DependenceAnalysis.
Proof: https://alive2.llvm.org/ce/z/JLCqGJ
[llvm] Updates case folding rules to Unicode 18 (#223716)
This PR updates other Unicode tables started by
https://github.com/llvm/llvm-project/pull/198255
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
[LLD][ELF] Reduce memory and file size of overlay thunk tests (#222565)
Add AT(address) to linker script to force generation of a program header
for each address. Without AT we get a single large program header that
takes up a large amount of memory and causes a large file to be
generated. This may prevent the test from running on a 32-bit machine
without a lot of memory. See comment on #200415
Also removed a superfluous --print-map from
aarch64-thunk-bit-overlay-reuse.s. This was used when constructing the
test but it is not needed.
[Flang][Driver]Implemented the support for option -f[no-]optimize-sibling-calls in Flang (#216650)
Added support for -foptimize-sibling-calls and
-fno-optimize-sibling-calls in Flang.
- Sibling call optimization is on by default and the driver pass the
option `-f[no-]optimize-sibling-calls` to flang -fc1.
- When `-fno-optimize-sibling-calls` flag is passed, it sets boolen
`DisableTailCalls` and this results in adding the LLVM IR attribute
`"disable-tail-calls"="true"` which disables sibling call optimization.
[AMDGPU] Set Format/FormatModifier directly instead of per-flag bits, NFC.
Remove the now-redundant individual InstSI format flag fields (SOP1/2/C/K/P,
VOP1/2/C/VOP3/VINTRP/VOPD3/LDSDIR, the memory formats, Spill, and DPP/SDWA) and
have instruction classes set the Format / FormatModifier enum fields directly.
The enum fields are packed into TSFlags exactly as before, so this is NFC (the
full instruction table is byte-identical).
Real instructions copy Format/FormatModifier from their pseudo in the base real
classes (kept next to the existing TSFlags copy), so the Format field is now
correct on real instructions too.
Two derived helper bits (IsVOP3Encoding, VOPD3) are computed from Format for the
getVOPe32/getVOPe64 relation maps and the VOPDPairs searchable table; they are
not part of TSFlags.
Co-Authored-By: Claude <noreply at anthropic.com>
[AMDGPU] Decouple isVOP3P/isVINTERP from isVOP3 (#223448)
VOP3P and VINTERP instructions also set the VOP3 TSFlags bit, so isVOP3()
returned true for them. This overloaded isVOP3() to mean both "the VOP3
encoding" and "uses VOP3-style operand rules" (modifiers, constant bus,
literal legality).
Make VOP3P and VINTERP their own instruction-format enum values so
isVOP3() is strict (Format == VOP3). Callers that need "any VOP3-family
operand encoding" now use isVOP3Like() (VOP3 | VOP3P | VINTERP), added as
a SIInstrInfo wrapper. Redundant "isVOP3() && !isVOP3P()" tests are
simplified to isVOP3().
Resolves llvm/llvm-project#223448.
Co-Authored-By: Claude <noreply at anthropic.com>
[AMDGPU] Pack instruction format and modifier TSFlags bits into enums, NFC.
The instruction-format bits in TSFlags are mutually exclusive, so
collapse them into a single 5-bit Format enum and likewise FormatModifier
enum for DPP/SDWA. This frees 18 TSFlags bits.
For now Format is derived from individual TableGen bitfields to minimize
the patch, but next commit will remove those.
All raw format-bit tests already go through the SIInstrFlags predicates,
so no call sites change.
Co-Authored-By: Claude <noreply at anthropic.com>
WebAssembly: Drive Emscripten EH from the exception model, drop the cl::opt (#223972)
Remove the deprecated -enable-emscripten-cxx-exceptions flag. This
should now be driven by the generic exception-model mechanisms. There
was also some special case handling of the -mllvm flag in the clang driver
which also needed removal.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[libc] Make it possible to join the main thread (#221177)
Joining the main thread currently crashes because its ThreadAttributes
has a null platform_data pointer, causing Thread::wait() to dereference
a null futex.
While this is not a frequently used feature, it is supported by other
implementations, and I believe it is required by POSIX (the exec page
says that the main thread is created in a joinable state, and neither
pthread_join nor pthread_exit mention them not working on the main
thread).
This patch sets up the main thread attributes during startup:
- allocate a static futex for the main thread's clear_tid and point
platform_data to it
- invoke set_tid_address to have the kernel clear the futex and wake
waiters on thread termination
- mark the main thread as joinable (it was previously defaulting to
detached)
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[SROA] Avoid unnecessary stack realignment when rewriting allocas (#222967)
SROA can introduce dynamic stack realignment when rewriting an aggregate
alloca as a vector. On SystemZ (`S64`), a five-pointer structure with
alignment 8 becomes `<5 x ptr>` with alignment 64, adding an alignment
mask and extra stack-frame setup instructions.
Create replacement allocas with the alignment inherited from the
original alloca and partition offset, then use `tryEnforceAlignment` to
request the preferred type alignment. This reuses the existing
stack-alignment check: when a natural stack alignment is specified,
promotions beyond it are rejected. Stronger inherited alignments are
preserved.
Add SROA-only regression coverage for `S64`, `S128`, unspecified natural
stack alignment, and explicit stronger alignments. Existing SROA,
debug-info, and NVPTX tests retain their original RUN lines and checks,
including the NVPTX vector stores.
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[DenseMap] memcpy buckets with trivial copy constructor and destructor. NFC (#224193)
std::pair has a user-provided copy assignment operator, so
std::is_trivially_copyable is false. Define is weaker
isRelocatableBucket instead.
This optimizes some DenseMap instantiations within lld (e.g.
lld/ELF/SyntheticSections.cpp)
[compiler-rt][ARM] Make ARMv4T assembly builtins interwork (#221725)
ARMv4T can't switch instruction state when a saved return address is
loaded directly into the pc. Several builtins did exactly that, so a
call from Thumb could call into Arm state and return without switching.
To mitigate that, this patch amends POP_PC and adds
POP_PC_WITH_REGS, which expand to sensible code depending on
what arch they are compiled for. ARMv5 and later keep direct pop-to-pc
forms. v4T returns through ip and bx.
[mlir][affine] Avoid folding out-of-bounds constant loads (#224076)
`AffineLoadOp::fold` could crash when folding a constant load with
out-of-bounds indices, including loads from zero-sized constant memrefs.
Check `ElementsAttr::isValidIndex` before indexing the constant
attribute and skip folding when the access is invalid.
Adds a regression test for `memref<0xi8>`.
Fixes #223949
Co-authored-by: Purnima Shrivastava <purnimashrivastava05@.com>
[CIR] Support bitfields when unaligned access is expensive (#223748)
This basically ports OGCG codepath to enable bitfields on AMDGPU.
Assisted by claude in test checks generation.
[libc] Implement mkostemp (#224112)
Added the POSIX mkostemp entrypoint for Linux targets (aarch64, riscv,
x86_64) following the shared mktemp_core helper pattern from commit
1b48a14a3608.
Validated open flags against the supported POSIX Issue 8 set (O_APPEND,
O_CLOEXEC, O_DSYNC, O_SYNC) before invoking internal::mktemp_core.
Added unit tests in mkostemp_test.cpp covering flag combinations, append
semantics, template modification, and error conditions.
Assisted-by: Automated tooling, human reviewed.
[DAG] Optimize masked store of constant lane mask to standard store (#223665)
A masked store with a constant mask enabling the first n lanes can be
lowered to a standard store of size n.
For example a masked store with masks `<1, 1, 0, 0>` or a scalable store
with mask `llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 2)`
[CIR][AMDGPU][OpenCL] Classify __hip_atomic_*/__opencl_atomic_* operations (#220856)
load, store, exchange, compare_exchange_strong/weak, and every fetch op
were missing from the operand-classification switches, so they fell to
the default and reported an unimplemented atomic. They take the same
operands as their __c11_atomic_*/__atomic_* counterparts, so they belong
with them.
This is the ground work for implementing more AMDGPU atomics.
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
[clang][clangd] Resolve decltype when printing types for display (#223950)
`decltype(x)` is rarely what a reader wants to see in a display context:
a code completion offering `set_x(decltype(x) val)` conveys much less
than `set_x(int val)`.
clangd already worked around this for hover, by stripping decltypes off
the type before printing it, with a FIXME noting that this belongs in a
printing policy and that it does not handle composite types.
`HoverTests.cpp` carries a matching FIXME on one of the cases it misses.
Add such a policy flag, honour it in `TypePrinter`, and set it both for
code completion and for the types clangd displays on hover.
Applying it in the printer rather than at the call site also covers the
cases the workaround could not reach:
```c++
const decltype(a) b; // was `int`, now `const int`
void f(decltype(lamb) &bar); // was `decltype(lamb) &`, now `(lambda) &`
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[IR] Make Instruction::DebugMarker private behind getDbgMarker(). NFC (#224190)
Make it private and add getDbgMarker(); only BasicBlock and DbgMarker,
which maintain the marker links, write it. This enables experiments to
change the data representation.
Aided by Opus 5
