LLVM/project 9cbf724llvm/lib/TargetParser TargetDataLayout.cpp

clang-format

Created using spr 1.3.8-beta.1
DeltaFile
+2-1llvm/lib/TargetParser/TargetDataLayout.cpp
+2-11 files

LLVM/project 04031a9llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

only look at ABI

Created using spr 1.3.8-beta.1
DeltaFile
+160,853-171,875llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+54,567-55,132llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+92,827-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+31,320-33,737llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+759,347-260,74429,181 files not shown
+4,174,883-1,618,10929,187 files

LLVM/project 2d9efd2llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+160,853-171,875llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+54,567-55,132llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+92,827-0llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+31,320-33,737llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+759,347-260,74429,180 files not shown
+4,174,851-1,618,08029,186 files

LLVM/project 41236fbllvm/lib/Transforms/Scalar GVN.cpp, llvm/test/Transforms/GVN tbaa.ll

[GVN] Propagate isMemorySSAEnabled() into ValueTable (#193938)

`GVNPass::runImpl()` calls `VN.setMemorySSA(MSSA)` with a single
argument. The second parameter of `ValueTable::setMemorySSA()`,
`MSSAEnabled`, defaults to `false`, so `ValueTable::IsMSSAEnabled`
remains false even when the pass is configured with
`-enable-gvn-memoryssa=1` or `-passes='gvn<memoryssa>'`.

The MemorySSA-backed value-numbering paths in
`ValueTable::lookupOrAddCall()` and `ValueTable::computeLoadStoreVN()`
are gated on `IsMSSAEnabled`, making them unreachable from runImpl() on
main today.

This patch forwards isMemorySSAEnabled() as the second argument to
setMemorySSA(), so selecting the MemorySSA backend actually enables
MemorySSA-aware value numbering.
DeltaFile
+36-90llvm/test/Transforms/GVN/tbaa.ll
+4-1llvm/lib/Transforms/Scalar/GVN.cpp
+40-912 files

LLVM/project 87e285c. pyproject.toml

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+10-0pyproject.toml
+10-01 files

LLVM/project ab6582bclang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded vfncvtbf16.c, llvm/test/CodeGen/RISCV/rvv setcc-int-vp.ll

update switch

Created using spr 1.3.8-beta.1
DeltaFile
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+704-882llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+980-230mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
+1,024-0llvm/test/Transforms/LoopUnroll/debug-and-remarks.ll
+0-987mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+472-472clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
+6,410-3,027759 files not shown
+31,136-15,914765 files

LLVM/project 161e56bclang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded vfncvtbf16.c, llvm/test/CodeGen/RISCV/rvv setcc-int-vp.ll fixed-vectors-setcc-int-vp.ll

Merge branch 'main' into users/ylzsx/v2f32-load-legalize
DeltaFile
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+704-882llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+980-230mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
+0-987mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+472-472clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
+345-558llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
+5,731-3,585576 files not shown
+25,323-14,291582 files

LLVM/project db57208llvm/test/CodeGen/X86 machine-block-hash.mir

[X86] Mark machine-block-hash.mir as XFAIL on big-endian hosts (#194279)

Test introduced in #193107 assumes `stable_hash_combine` is stable,
but it turns out it's not true.
DeltaFile
+3-0llvm/test/CodeGen/X86/machine-block-hash.mir
+3-01 files

LLVM/project e042f67llvm/lib/Target/LoongArch LoongArchInstrInfo.cpp LoongArchInstrInfo.h, llvm/test/CodeGen/LoongArch stackslot.mir

[LoongArch] Override `isLoadFromStackSlot/isStoreToStackSlot` to expose more optimizations (#164561)
DeltaFile
+245-0llvm/test/CodeGen/LoongArch/stackslot.mir
+76-0llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+9-0llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
+330-03 files

LLVM/project 0d704c3llvm/test/CodeGen/X86 machine-block-hash.mir

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+3-0llvm/test/CodeGen/X86/machine-block-hash.mir
+3-01 files

LLVM/project a881a30llvm/lib/Target/AMDGPU SIWholeQuadMode.cpp

Apply suggestion from @ruiling
DeltaFile
+0-1llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+0-11 files

LLVM/project 37ac1efllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-fp-setcc.ll fixed-vectors-setcc-fp-vp.ll

Merge branch 'main' into users/ruiling/wqm-prop-sideeffect
DeltaFile
+4,811-4,818llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+1,872-1,883llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+565-2,727llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,117-1,613llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+11,921-16,1233,545 files not shown
+154,376-91,2463,551 files

LLVM/project ef09defllvm/test/CodeGen/AMDGPU wqm-propagate-for-execz-side-effect.mir

[test][AMDGPU] Precommit test for Back-propagate wqm for sources of side-effect instruction (#193394)
DeltaFile
+238-0llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
+238-01 files

LLVM/project b111f60llvm/test/CodeGen/X86 machine-block-hash.mir

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+0-1llvm/test/CodeGen/X86/machine-block-hash.mir
+0-11 files

LLVM/project 3114d30llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-fp-setcc.ll fixed-vectors-setcc-fp-vp.ll

Merge branch 'main' into users/ruiling/add-wqm-test
DeltaFile
+4,811-4,818llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+1,872-1,883llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+565-2,727llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,117-1,613llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+11,921-16,1233,545 files not shown
+154,376-91,2463,551 files

LLVM/project 09306f7llvm/test/CodeGen/RISCV/rvv fixed-vectors-vnmsac-vp.ll fixed-vectors-vmacc-vp.ll

[RISCV] Remove codegen for vp_add, vp_mul, vp_sub (#194173)

Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999

This splits off 3 intrinsics from #179622. These are expanded and
removed in lockstep so we don't break the multiply-accumulate patterns.
DeltaFile
+438-234llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
+438-234llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
+241-326llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
+201-265llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
+175-179llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
+141-166llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
+1,634-1,40421 files not shown
+2,244-2,04627 files

LLVM/project 652700bcompiler-rt/lib/sanitizer_common sanitizer_posix.cpp

Reland "[sanitizer] Fix race condition in GetNamedMappingFd with decorate_pro…"" (#194273)

Reverts llvm/llvm-project#194271

Relands llvm/llvm-project#190981.

ThreadID is u64, format must be `%llu`.
DeltaFile
+4-3compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
+4-31 files

LLVM/project d0efc78compiler-rt/lib/sanitizer_common sanitizer_posix.cpp

Fix formatting of shmname initialization
DeltaFile
+3-2compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
+3-21 files

LLVM/project 680e7efcompiler-rt/lib/sanitizer_common sanitizer_posix.cpp

Fix format specifier for GetNamedMappingFd
DeltaFile
+1-1compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
+1-11 files

LLVM/project f044508compiler-rt/lib/sanitizer_common sanitizer_posix.cpp

Revert "Revert "[sanitizer] Fix race condition in GetNamedMappingFd with deco…"

This reverts commit 57494cc7b4e8b59714ee9e312812d8421f41d27c.
DeltaFile
+3-3compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
+3-31 files

LLVM/project 7ac35e6

Revert "[sanitizer] Fix race condition in GetNamedMappingFd with decorate_pro…"

This reverts commit 13cee9be088057f198e08ee7217ed2af08cfd825.
DeltaFile
+0-00 files

LLVM/project 57494cccompiler-rt/lib/sanitizer_common sanitizer_posix.cpp

Revert "[sanitizer] Fix race condition in GetNamedMappingFd with decorate_pro…" (#194271)

Reverts llvm/llvm-project#190981 due to buildbot failure
(https://lab.llvm.org/buildbot/#/builders/66/builds/29993):
```
  SanitizerCommon-asan-i386-Linux :: Linux/decorate_proc_maps.cpp
```
DeltaFile
+3-3compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
+3-31 files

LLVM/project 1b381a1llvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.cpp RISCVBaseInfo.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+7-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+7-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+14-02 files

LLVM/project 13cee9bcompiler-rt/lib/sanitizer_common sanitizer_posix.cpp

[sanitizer] Fix race condition in GetNamedMappingFd with decorate_pro… (#190981)

…c_maps=1

Multi-threaded programs crash randomly when
ASAN_OPTIONS=decorate_proc_maps=1 is enabled due to filename collision
in /dev/shm.

Root Cause:
All threads use the same filename format '/dev/shm/<PID> [name]',
causing race conditions where one thread deletes a file created by
another thread, resulting in ENOENT errors.

Solution:
Add thread ID (TID) to the filename to ensure uniqueness:
- Old format: /dev/shm/<PID> [name]
- New format: /dev/shm/<PID>.<TID> [name]

This ensures each thread has a unique filename, eliminating the race

    [6 lines not shown]
DeltaFile
+3-3compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
+3-31 files

LLVM/project 4ef52felibcxx/utils/ci run-buildbot

[libcxx] Remove package installation for generic-llvm-libc (#194259)

Now that these packages are installed by default in the container image,
we no longer need to install them each time we do a build.
DeltaFile
+0-10libcxx/utils/ci/run-buildbot
+0-101 files

LLVM/project 28c4c25compiler-rt/lib/sanitizer_common sanitizer_allocator_dlsym.h

[Asan]Add align argument to Realloc() (#194255)

Add align argument to the function Realloc() to ensure original
allocation alignment through realloc
DeltaFile
+3-3compiler-rt/lib/sanitizer_common/sanitizer_allocator_dlsym.h
+3-31 files

LLVM/project 544d003llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/VPlan vplan-print-after-all.ll

[VPlan] Use RUN_VPLAN_PASS for later VPlan transforms. (#194261)

Convert a number of later VPlan transform invocations to use
RUN_VPLAN_PASS. Enables more accurate transform printing, as well as
extra verification.

This should migrate all remaining transforms that can be moved without
changes.
DeltaFile
+35-31llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+11-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
+46-312 files

LLVM/project 3b20615llvm/test/Transforms/LoopVectorize/VPlan widen-canonical-iv-register-pressure.ll, llvm/test/Transforms/LoopVectorize/X86 widen-canonical-iv-register-pressure.ll

[LV] Add test cases where wide IV can cause spills. (#194260)

Add test cases showing cases where replacing VPWidenCanonicalIVRecipe
with VPWidenIntOrFPinductionPHIRecipe is profitable/not profitable due
to introducing spills.
DeltaFile
+338-0llvm/test/Transforms/LoopVectorize/X86/widen-canonical-iv-register-pressure.ll
+132-0llvm/test/Transforms/LoopVectorize/VPlan/widen-canonical-iv-register-pressure.ll
+470-02 files

LLVM/project 8f65ad5llvm/lib/Analysis ConstantFolding.cpp, llvm/test/Transforms/InstSimplify load.ll

[ConstantFolding] Fold byte loads from constant globals (#194074)

Handle byte types in `FoldReinterpretLoadFromConst` and
`ConstantFoldLoadFromUniformValue` so loads from constant globals fold.
DeltaFile
+103-0llvm/test/Transforms/InstSimplify/load.ll
+23-11llvm/lib/Analysis/ConstantFolding.cpp
+126-112 files

LLVM/project a562a10lldb/tools/lldb-dap DAP.cpp DAPSessionManager.cpp

lldb-dap: Fix race condition in event threads creation (#194012)

Move the registration of the SBListener to before
the event threads (`ProgressEventThread` and `EventThread`) start

This prevents a race condition where a stop event
could be missed if it was sent immediately after thread creation, which
would lead to a deadlock. It is most likely to happen under heavy CPU
load with test that fails early like
TestDAP_commands::test_command_directive_abort_on_error_init_commands.

Relevant logs.
```sh
# Event thread deadlock.
0x00007348BC000BE0 Listener('lldb-dap.progress.listener')::GetEventInternal, timeout = 1000000 us, event_mask = 0
0x00005b72419d1640 Broadcaster("lldb-dap")::BroadcastEvent (event_sp = 0x5b7241eebb60 Event: broadcaster = 0x5b72418e0df0 (lldb-dap), type = 0x00000001, data = <NULL>, unique=false) hijack = 0x0000000000000000
0x00005B7241898440 Listener('lldb.Debugger')::GetEventInternal, timeout = 1000000 us, event_mask = 0
0x7348bc000be0     Listener::GetEventInternal() timed out for lldb-dap.progress.listener
0x00007348BC000BE0 Listener('lldb-dap.progress.listener')::GetEventInternal, timeout = 1000000 us, event_mask = 0

    [9 lines not shown]
DeltaFile
+14-7lldb/tools/lldb-dap/DAP.cpp
+15-0lldb/tools/lldb-dap/DAPSessionManager.cpp
+2-9lldb/tools/lldb-dap/EventHelper.cpp
+1-1lldb/tools/lldb-dap/DAP.h
+32-174 files