[CIR] Implement shouldCreateMemCpyFromGlobal in LoweringPrepare (#181276)
CIRGen emits cir.const + cir.store for aggregate initialization, keeping
closer to source-level semantics. LoweringPrepare transforms stores of
constant aggregates (arrays, records) into cir.global + cir.get_global +
cir.copy, matching OG codegen's shouldCreateMemCpyFromGlobal
optimization.
The transform only applies to stores targeting cir.alloca (local
variables inside cir.func). Stores in other contexts (e.g. OpenACC
reduction recipe init blocks, base class initialization) are left as
cir.const + cir.store.
Also fixes CopyOp lowering to use i64 for the memcpy length instead of
i32, matching OG codegen behavior.
[LLVM][Utils] Fix automerge in git-llvm-push (#181766)
Enabling automerge can only be done using the GraphQL API. Add in some
basic GraphQL infrastructure and update the enable_automerge method to
call the GraphQL API to enable automerge for a PR.
Tested locally on #181762.
Closes #181634.
[AArch64][llvm] Remove `+xs` gating for `tlbip *nxs` instructions
A recent specification update has removed FEAT_XS gating for `tlbip *nxs`
instructions. It remains gated on FEAT_XS for `tlbi *nxs` instructions.
[AArch64][llvm] Gate some `tlbip` insns with +tlbid or +d128
Change the gating of `tlbip` instructions containing `*E1IS*`, `*E1OS*`,
`*E2IS*` or `*E2OS*` to be used with `+tlbid` or `+d128`. This is because
the 2025 Armv9.7-A MemSys specification says:
```
All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions
that are currently dependent on FEAT_D128 are updated to be dependent
on FEAT_D128 or FEAT_TLBID
```
[lldb] Revert scripted symbol locator (#181945)
This revert #181334 and its follow-up PRs (including #181488, #181492,
#181493, #181494 and #181498) as well as Ismail's documentation changes
(#181594, #181717). The original commit causes a test failure in CI
(https://github.com/llvm/llvm-project/issues/181938) but the more I look
at the patch, the more I'm convinced it was not ready to land. It will
be easier to iterate on the feedback by re-landing this than by using
post-commit review.
[RISCV] Check the error location in xsfvcp-invalid.s. NFC (#181929)
Check that the error location points to the destination operand.
I'm planning to rewrite the code that generates that error, and I want
to make sure I get the location right.
[TableGen] Rename TheMatcher->TheMatcherList. NFC (#181942)
After 8d971c0360f91729cc5120ffd361f7b55e97f2ab, there is a linked list
container object called MatcherList. We no long hold a pointer directly
to the first Matcher in the list.
Rename the variables to make this clearer.
[CIR] Add verifier for CIR try op (#181419)
This adds a verifier to enforce the requirement that every catch handler
in a cir.try operation must begin with a cir.catch_param operation.
[CIR][NFC] Upstream support for FP environments and RAII options (#179121)
This adds support for FP environment descriptions and RAII options for
FP operations, i.e.,`CIRGenFPOptionsRAII`).
[OpenACC] add acc.reduction_combine operation (#181853)
To facilitate codegen decisions, we need to create an operation that can
abstract the final update of the original and partial sum from a
reduction. This is represented within the combiner recipes. Having an
operator allows future lowering to clearly identify how to handle the
final accumulation. This is currently an NFC.
The format of this operation is:
```
acc.reduction_combine %srcMemref into %destMemref <reductionOperator> : type
```
[NFC][CodeGen] Minor cleanup in MachineInstr operand printing (#181892)
- Rename `getTiedOperandIdx` to `GetTiedOperandIdx` per LLVM CS.
- Do not compute tied operand index for defs, since tied operands are
printed only on uses.
- Restructure the `if` in the later operand printing loop to not compute
tied operand index/type for subreg-index imm operands.
[mlir][gpu] Harden verification constraints in `transform.gpu.map_nested_forall_to_threads` (#170282)
Harden `transform.gpu.map_nested_forall_to_threads` to reject
non-positive block/grid sizes and handle zero-iteration dimensions
gracefully, preventing assertion failures in `computeProduct`.
Fix `getConstantIntValues` to return `std::nullopt` if any element is
non-constant, avoiding invalid zero placeholders.
Fixes: https://github.com/llvm/llvm-project/issues/73562
[NFC][CodeGen] Rename CallBrPrepare pass to InlineAsmPrepare (#181547)
This is an NFC change to make room for a more generalized "prepare" pass
for inline assembly beyond CallBrInsts. In particular, changing how we
generate code for inline assembly with "rm" constraints.
[lldb] cast char8_t* to char* to allow std::string construction under C++20 (#181928)
After 5d5301dc0c, lldb fails to compile under C++20 with:
```
llvm-project/lldb/source/Target/StackFrameList.cpp:975:12: error: no viable conversion from returned value of type 'const char8_t *' to function return type 'std::string' (aka 'basic_string<char>')
975 | return show_unicode_marker ? u8" * " : u8"* ";
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```
This PR reinterpret casts the unicode characters returned by
`GetFrameMarker` to `const char*`.
[AArch64][llvm] Remove `+d128` gating on `sysp`, `msrr` and `mrrs` instructions
Remove `+d128` gating on `sysp`, `msrr` and `mrrs` instructions.
We removed gating for `sys`, `mrs` and `mrs` instructions previously,
on the basis that it doesn't add value, as it doesn't indicate that
any particular system registers or system instructions are available.
Therefore, remove `+d128` gating for these too.
(In an upcoming change, some `tlbip` instructions, which are `sysp` aliases
are allowed to be used with either `+d128` or `tlbid`. If we don't remove
this gating, then it would require some ugly work-arounds in the code to
support the relaxation mandated by the 2025 MemSys specification.
In this change, retain `+d128` gating for all `tlbip` instructions, which
will then be loosened to either `+d128` or `+tlbid` in a subsequent change)
