LLVM/project 0b4fbc5llvm/test/Transforms/SLPVectorizer/X86 shl-compatible-with-add.ll

[SLP][NFC]Add a test to check modeling shl x, 1 as add x,x, NFC
DeltaFile
+64-0llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll
+64-01 files

LLVM/project 2f09bd2lld/test/ELF relocation-nocopy.s hidden-shared-err.s

[ELF,test] Improve error/warning message checks

Update tests to include proper `error:` or `warning:` prefixes and
file/section information in CHECK patterns. Add
--implicit-check-not=error: to ensure no unexpected errors are produced.
DeltaFile
+6-6lld/test/ELF/relocation-nocopy.s
+5-5lld/test/ELF/hidden-shared-err.s
+5-5lld/test/ELF/aarch64-lo12-alignment.s
+5-5lld/test/ELF/arm-adr-err-long.s
+4-4lld/test/ELF/arm-adr-err.s
+4-4lld/test/ELF/relocation-past-merge-end.s
+29-2942 files not shown
+117-11448 files

LLVM/project adaa3e7libc/src/__support/math sincosf_utils.h sincosf_float_eval.h

[libc] Address sincosf size bloat (#179004)

The recent refactoring in #177523 marked some functions as static which
increased the size of sinf/cosf functions. Removing the static storage
for these functions to remove the bloat which is especially problematic
in size constrained baremetal target builds.
DeltaFile
+8-9libc/src/__support/math/sincosf_utils.h
+3-3libc/src/__support/math/sincosf_float_eval.h
+1-1libc/src/__support/math/sincosf.h
+12-133 files

LLVM/project 9065730lld/test/ELF aarch64-movw-error.s arm-tag-vfp-args-errs.s

[ELF,test] Improve error message checks with proper format

Update tests to use the canonical error message format with `error:`
prefix and file:section information. Add `--implicit-check-not=error:`
to ensure no unexpected errors are produced.

This commit focuses on "out of range" and "not aligned" errors.
DeltaFile
+19-19lld/test/ELF/aarch64-movw-error.s
+15-17lld/test/ELF/arm-tag-vfp-args-errs.s
+3-3lld/test/ELF/ppc64-error-missaligned-dq.s
+3-3lld/test/ELF/ppc64-error-missaligned-ds.s
+3-3lld/test/ELF/ppc64-reloc-pcrel34-overflow.s
+2-2lld/test/ELF/aarch64-load-alignment.s
+45-473 files not shown
+50-529 files

LLVM/project e1076a8mlir/include/mlir/IR BuiltinTypeInterfaces.td, mlir/lib/AsmParser AttributeParser.cpp

[mlir][WIP] `DenseElementsAttr` generalized
DeltaFile
+155-1mlir/lib/AsmParser/AttributeParser.cpp
+76-0mlir/include/mlir/IR/BuiltinTypeInterfaces.td
+57-15mlir/lib/IR/AsmPrinter.cpp
+28-0mlir/test/lib/Dialect/Test/TestTypes.cpp
+28-0mlir/test/IR/dense-elements-type-interface.mlir
+16-0mlir/test/lib/Dialect/Test/TestTypeDefs.td
+360-165 files not shown
+379-1611 files

LLVM/project 7274ae9llvm/lib/Target/AMDGPU GCNSchedStrategy.cpp GCNSchedStrategy.h, llvm/test/CodeGen/AMDGPU debug-value-scheduler.mir sema-v-unsched-bundle.ll

[AMDGPU][Scheduler] Simplify scheduling revert logic (#177203)

When scheduling must be reverted for a region, the current
implementation re-orders non-debug instructions and debug instructions
separately; the former in a first pass and the latter in a second pass
handled by a generic machine scheduler helper whose state is tied to the
current region being scheduled, in turns limiting the revert logic to
only work on the active scheduling region.

This makes the revert logic work in a single pass for all MIs, and
removes the restriction that it works exclusively on the active
scheduling region. The latter enables future use cases such as reverting
scheduling of multiple regions at once.
DeltaFile
+44-51llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+6-2llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+2-2llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
+1-1llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
+53-564 files

LLVM/project 90b3712llvm/lib/Transforms/Vectorize VPlanTransforms.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/X86 reduction-crash.ll

Reapply "[VPlan] Detect and create partial reductions in VPlan. (NFCI) (#167851)"

This reverts commit d1e477b00b49c63ff4dd513eeb14a5b18bc055d7.

Recommit with a extra checks making sure extends are VPWidenCastRecipes,
rejecting VPReplicateRecipes.

Original message:
As a first step, move the existing partial reduction detection logic to
VPlan, trying to preserve the existing code structure & behavior as
closely as possible.

With this, partial reductions are detected and created together in a
single step.

This allows forming partial reductions and bundling them up if
profitable together in a follow-up.

PR: https://github.com/llvm/llvm-project/pull/167851
DeltaFile
+362-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+7-267llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-62llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+47-0llvm/test/Transforms/LoopVectorize/X86/reduction-crash.ll
+7-35llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+20-0llvm/lib/Transforms/Vectorize/VPlanUtils.h
+446-3665 files not shown
+493-36811 files

LLVM/project 1818b23llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp SelectionDAG.cpp, llvm/test/CodeGen/AArch64 sve-bf16-combines.ll

[SDAG] Check for `nsz` in DAG.canIgnoreSignBitOfZero() (#178905)

Follow up to #174423
DeltaFile
+16-18llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
+9-13llvm/test/CodeGen/RISCV/fma-combine.ll
+8-8llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
+5-9llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+4-6llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+5-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+47-542 files not shown
+50-578 files

LLVM/project 7c738camlir/include/mlir/Interfaces ExecutionProgressOpInterface.h, mlir/lib/Interfaces ExecutionProgressOpInterface.cpp

address comments
DeltaFile
+4-2mlir/include/mlir/Interfaces/ExecutionProgressOpInterface.h
+1-1mlir/lib/Interfaces/ExecutionProgressOpInterface.cpp
+5-32 files

LLVM/project 0280450llvm/test/tools/llvm-lipo create-archive-input.test, llvm/tools/llvm-lipo llvm-lipo.cpp

[llvm-lipo] Fix handling of archives in universal binaries (#176448)

When extracting slices from a universal binary, llvm-lipo was not
handling the case where the slice is an archive.

Fixes #90156
DeltaFile
+21-7llvm/tools/llvm-lipo/llvm-lipo.cpp
+9-0llvm/test/tools/llvm-lipo/create-archive-input.test
+30-72 files

LLVM/project 59f815bclang/bindings/python/clang cindex.py, clang/bindings/python/tests/cindex test_code_completion.py

[libclang/python] Deprecate CodeCompletionResults.results (#177764)

This partially addresses point 5 from
https://github.com/llvm/llvm-project/issues/156680.
DeltaFile
+18-0clang/bindings/python/clang/cindex.py
+10-1clang/bindings/python/tests/cindex/test_code_completion.py
+6-0clang/docs/ReleaseNotes.rst
+34-13 files

LLVM/project 49d2323llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 avx512-intrinsics.ll

[X86] getScalarMaskingNode - FIXUPIMM scalar ops take upper elements from second operand (#179101)

FIXUPIMMSS/SD instructions passthrough the SECOND operand upper elements, and not the first like most (2-op) instructions

Fixes #179057
DeltaFile
+6-4llvm/test/CodeGen/X86/avx512-intrinsics.ll
+6-4llvm/lib/Target/X86/X86ISelLowering.cpp
+12-82 files

LLVM/project 603b625llvm/include/llvm/CodeGen BasicTTIImpl.h, llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp

[Analysis] Add Intrinsics::CLMUL case to cost calculations to getIntrinsicInstrCost / getTypeBasedIntrinsicInstrCost (#176552)

This patch adds a case in getIntrinsicInstrCost and
getTypeBasedIntrinsicInstrCost in
llvm/include/llvm/CodeGen/BasicTTIImpl.h for Intrinsic::clmul. This
patch uses TLI->isOperationLegalOrCustom to check if the instruction is
cheap. If not cheap, it sums up the cost of the arithmetic operations
(AND, SHIFT, XOR) multiplied by the bit width.

Fixes #176354
DeltaFile
+26-0llvm/test/Analysis/CostModel/X86/clmul.ll
+17-0llvm/test/Analysis/CostModel/AArch64/clmul.ll
+12-0llvm/include/llvm/CodeGen/BasicTTIImpl.h
+3-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+58-04 files

LLVM/project d1e477bllvm/lib/Transforms/Vectorize VPlanTransforms.cpp LoopVectorize.cpp

Revert "[VPlan] Detect and create partial reductions in VPlan. (NFCI) (#167851)"

This reverts commit f4e8cc1a2229dca76d21c8d37439c4c194b06b86.

This change wasn't NFC; it causes failed asserts when building
ffmpeg for i686 windows, see
https://github.com/llvm/llvm-project/pull/167851 for details.
DeltaFile
+2-358llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+267-7llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+62-3llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+35-7llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+0-20llvm/lib/Transforms/Vectorize/VPlanUtils.h
+0-17llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+366-4124 files not shown
+368-44210 files

LLVM/project d5711ddmlir/include/mlir/Dialect/UB/IR UBOps.td, mlir/lib/Dialect/UB/IR UBOps.cpp

[mlir][UB] Erase ops that precede `ub.unreachable`
DeltaFile
+37-0mlir/lib/Dialect/UB/IR/UBOps.cpp
+25-0mlir/test/Dialect/UB/canonicalize.mlir
+1-0mlir/include/mlir/Dialect/UB/IR/UBOps.td
+63-03 files

LLVM/project cf9912emlir/include/mlir/Dialect/SCF/IR SCFOps.td, mlir/include/mlir/Dialect/UB/IR UBOps.h

address comments
DeltaFile
+48-0mlir/include/mlir/Interfaces/ExecutionProgressOpInterface.td
+23-0mlir/lib/Interfaces/ExecutionProgressOpInterface.cpp
+23-0mlir/include/mlir/Interfaces/ExecutionProgressOpInterface.h
+0-12mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+3-5mlir/include/mlir/Dialect/UB/IR/UBOps.h
+6-2mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
+103-196 files not shown
+111-2012 files

LLVM/project 8e7a2d8clang/lib/AST ExprConstant.cpp, clang/lib/AST/ByteCode InterpBuiltin.cpp Context.cpp

Revert "[clang][bytecode] Use in `Expr::tryEvaluateObjectSize` (#1790… (#179099)

…33)"

This reverts commit 756c321c33af2be0bd40707948aae3c06163a0a6.

Test failure in clang/test/AST/ByteCode/builtins.c in CI build

CC @tbaederr
DeltaFile
+31-37clang/lib/AST/ByteCode/InterpBuiltin.cpp
+0-29clang/lib/AST/ByteCode/Context.cpp
+0-13clang/lib/AST/ByteCode/Context.h
+0-4clang/lib/AST/ExprConstant.cpp
+4-0clang/test/Sema/warn-fortify-source.c
+0-3clang/lib/AST/ByteCode/InterpHelpers.h
+35-8612 files not shown
+35-9818 files

LLVM/project a34bfacllvm/include/llvm/ADT APInt.h, llvm/unittests/ADT APIntTest.cpp

[APInt] Extend isSameValue to also do signed-compares (#178854)

Introduce a SignedCompare parameter of isSameValue to use sext instead
of zext.
DeltaFile
+22-1llvm/unittests/ADT/APIntTest.cpp
+12-6llvm/include/llvm/ADT/APInt.h
+34-72 files

LLVM/project a19cbc4llvm/lib/Transforms/Vectorize VPlan.h VPlanRecipes.cpp

[VPlan] Rename VectorEndPointer's IndexedTy to SourceElementTy (NFC) (#178856)

For consistency with IR terminology.
DeltaFile
+9-8llvm/lib/Transforms/Vectorize/VPlan.h
+3-3llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+12-112 files

LLVM/project 618d71dllvm/test/CodeGen/X86 avx512-intrinsics.ll

[X86] Add test coverage for #179057 (#179092)

Incorrect folding of fixupimm scalar intrinsics passthrough when the
mask is known zero
DeltaFile
+36-0llvm/test/CodeGen/X86/avx512-intrinsics.ll
+36-01 files

LLVM/project 7f967a9mlir/lib/AsmParser AttributeParser.cpp, mlir/test/IR invalid-dense-array-attr.mlir

[mlir][IR] Diagnose index element type in DenseArrayAttr (#179075)

DeltaFile
+22-0mlir/test/IR/invalid-dense-array-attr.mlir
+2-2mlir/lib/AsmParser/AttributeParser.cpp
+24-22 files

LLVM/project 584bd38llvm/docs/tutorial/MyFirstLanguageFrontend LangImpl03.rst

[docs] fix output question (#177842)

See the code:
<img width="2631" height="1090" alt="image"
src="https://github.com/user-attachments/assets/dfe949b3-fbc6-4cd3-9e8d-5c0adbfcc67a"
/>
<img width="1751" height="577" alt="image"
src="https://github.com/user-attachments/assets/e3b78596-24b9-4bd5-b40d-a4154b2e6bb2"
/>


So the output is not the number, is the text "__anon_expr".
DeltaFile
+2-2llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rst
+2-21 files

LLVM/project 756c321clang/lib/AST ExprConstant.cpp, clang/lib/AST/ByteCode InterpBuiltin.cpp Context.cpp

[clang][bytecode] Use in `Expr::tryEvaluateObjectSize` (#179033)

Fixes #138474

Use new bytecode intepreter in `Expr::tryEvaluateObjectSize`. Reuses the
already existing implementation for `__builtin_object_size` in of the
intepreter.

---------

Co-authored-by: Timm Baeder <tbaeder at redhat.com>
DeltaFile
+37-31clang/lib/AST/ByteCode/InterpBuiltin.cpp
+29-0clang/lib/AST/ByteCode/Context.cpp
+13-0clang/lib/AST/ByteCode/Context.h
+0-4clang/test/Sema/warn-fortify-source.c
+4-0clang/lib/AST/ExprConstant.cpp
+3-0clang/lib/AST/ByteCode/InterpHelpers.h
+86-3512 files not shown
+98-3518 files

LLVM/project 6885042clang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode invalid.cpp

[clang][bytecode] Reject CK_BitCast nodes with errors early (#179087)

Fixes https://github.com/llvm/llvm-project/issues/179020
DeltaFile
+5-0clang/test/AST/ByteCode/invalid.cpp
+2-0clang/lib/AST/ByteCode/Compiler.cpp
+7-02 files

LLVM/project 487de1alibc/test/src/time mktime_test.cpp gmtime_test.cpp

[libc][test] Fix TmMatcher and correct tm_yday/tm_wday test values (#179029)

The TmMatcher was using || instead of && to compare tm struct fields,
causing it to match if ANY field was equal rather than ALL fields. This
masked incorrect expected values in the time tests.

Happily, only the tests needed fixing.  The code was correct.

Fixed the matcher and corrected all tm_yday and tm_wday values to match
glibc's gmtime_r output.
DeltaFile
+20-20libc/test/src/time/mktime_test.cpp
+12-12libc/test/src/time/gmtime_test.cpp
+8-8libc/test/src/time/TmMatcher.h
+2-2libc/test/src/time/gmtime_r_test.cpp
+42-424 files

LLVM/project b6e5e8elldb/source/Plugins/Process/FreeBSDKernel ThreadFreeBSDKernel.cpp ProcessFreeBSDKernel.cpp

[lldb] [Process/FreeBSDKernel] Select paniced thread automatically (#178069)

Kernel panic is a special case, and there is no signal or exception for
that so we need to rely on special workaround called `dumptid`.
FreeBSDKernel plugin is supposed to find this thread and set it manually
through `SetStopInfo()` in `CalculateStopInfo()` like Mach core plugin
does.

Before (We had to find and select crashed thread list otherwise thread 1
was selected by default):
```
➜ sudo lldb /boot/panic/kernel -c /var/crash/vmcore.last
(lldb) target create "/boot/panic/kernel" --core "/var/crash/vmcore.last"
Core file '/var/crash/vmcore.last' (x86_64) was loaded.
(lldb) bt
* thread #1, name = '(pid 12991) dtrace'
  * frame #0: 0xffffffff80bf9322 kernel`sched_switch(td=0xfffff8015882f780, flags=259) at sched_ule.c:2448:26
    frame #1: 0xffffffff80bd38d2 kernel`mi_switch(flags=259) at kern_synch.c:530:2
    frame #2: 0xffffffff80c29799 kernel`sleepq_switch(wchan=0xfffff8014edff300, pri=0) at subr_sleepqueue.c:608:2

    [38 lines not shown]
DeltaFile
+10-1lldb/source/Plugins/Process/FreeBSDKernel/ThreadFreeBSDKernel.cpp
+7-3lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp
+3-0lldb/source/Plugins/Process/FreeBSDKernel/ThreadFreeBSDKernel.h
+20-43 files

LLVM/project a51d3a2clang/lib/CIR/CodeGen TargetInfo.cpp, clang/lib/CIR/Dialect/Transforms/TargetLowering LowerModule.cpp

[CIR][AMDGPU] Lower Language specific address spaces and implement AMDGPU target
DeltaFile
+48-9clang/test/CIR/Lowering/global-address-space.cir
+51-0clang/test/CIR/CodeGen/amdgpu-address-spaces.cpp
+47-0clang/lib/CIR/Dialect/Transforms/TargetLowering/Targets/AMDGPU.cpp
+46-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+17-8clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+9-2clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
+218-194 files not shown
+234-1910 files

LLVM/project d6d3754clang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenExpr.cpp, clang/test/CIR/Lowering global-address-space.cir

preserve AS for getGlobal op
DeltaFile
+31-0clang/test/CIR/Lowering/global-address-space.cir
+3-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-2clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+36-53 files

LLVM/project 9b1cff9clang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenModule.h, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Address Space support for GlobalOps
DeltaFile
+48-9clang/lib/CIR/CodeGen/CIRGenModule.cpp
+19-20clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+30-0clang/test/CIR/IR/address-space.cir
+21-2clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+16-4clang/lib/CIR/CodeGen/CIRGenModule.h
+20-0clang/test/CIR/IR/invalid-addrspace.cir
+154-357 files not shown
+216-4313 files

LLVM/project e465147clang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenModule.h, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Address Space support for GlobalOps
DeltaFile
+48-9clang/lib/CIR/CodeGen/CIRGenModule.cpp
+19-20clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+30-0clang/test/CIR/IR/address-space.cir
+21-2clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+16-4clang/lib/CIR/CodeGen/CIRGenModule.h
+20-0clang/test/CIR/IR/invalid-addrspace.cir
+154-357 files not shown
+212-3913 files