[AArch64] Add vector expansion support for ISD::FCBRT when using ArmPL (#183750)
This patch teaches the backend how to lower the FCBRT DAG node to the
vector math library function when using ArmPL. This is similar to what
we already do for llvm.pow/FPOW, however the only way to expose this is
via a DAG combine that converts
FPOW(<2 x double> %x, <2 x double> <double 1.0/3.0, double 1.0/3.0>)
into
FCBRT(<2 x double> %x)
when the appropriate fast math flags are present on the node. I've
updated the DAG combine to handle vector types and only perform the
transformation if there exists a vector library variant of cbrt.
[DAG] isKnownNeverZero - add ISD::UADDSAT/UMAX/UMIN DemandedElts handling and tests (#183992)
Fixes #183038
Adds `isKnownNeverZero` support for `UADDSAT`, `UMAX`, and `UMIN`. This
allows the compiler to prove a vector result is _non-zero_ by analyzing
only the demanded lanes of its operands.
[mlir][llvm] Fix crash in LLVM inliner when callee has no recognized terminator (#183949)
When the callee of an llvm.call has a body block ending with an
unregistered op (rather than a recognized LLVM terminator like
llvm.return), the LLVM inliner's handleTerminator method was called with
that unregistered op and crashed via a cast<LLVM::ReturnOp>() assertion
or use-after-erase due to unresolved call result uses.
The root cause is that the generic MLIR verifier conservatively treats
unregistered ops as potential terminators (using mightHaveTrait), so
malformed IR of this shape passes verification. The inliner, however,
assumes that the callee's terminator is a recognized LLVM op.
Fix by adding a guard in LLVMInlinerInterface::isLegalToInline() that
refuses to inline a callee containing any block whose last operation
does not have the IsTerminator trait. This prevents the crash and leaves
the call site intact without any IR mutation.
Fixes #108363
Fixes #118766
[lldb] Don't link TestingSupport as a component (#184310)
This doesn't work with dylib builds, because TestingSupport is not part
of the dylib. Instead, we should link it via LINK_LIBS, like other tests
already do.
[lldb] Use AppendMessageWithFormatv in ComandObjectWatchpoint (#184128)
All of the AppendMessage... methods of CommandReturnObject automatically
add a newline, apart from AppendMessageWithFormat. This gets very
confusing when reviewing changes to commands.
While there are use cases for building a message as you go, controlling
when the newline is emitted, a lot of calls to AppendMessageWithFormat
include a newline at the end of the format string.
Such as in the watchpoint commands. So I've converted them to equivalent
AppendMessageWithFormatv calls so that:
* They have the less surprising behaviour re. newlines.
* They are in many cases more readable than the printf style notation.
Support unnamed functions in MIR parser (#183018)
In this PR, unnamed machine functions in an MIR file are associated with
anonymous functions in the embedded LLVM IR according to the order in
which they are specified. If there are more unnamed machine functions
then there are LLVM IR functions, the parsing will fail by reporting the
original error message of `function ‘’ isn’t defined in the provided
LLVM IR`.
Closes #36511
[LangRef] Mention allocation elision (#177592)
allockind / alloc-family enable allocation elision, but this was not
previously mentioned by LangRef.
Related discussion:
https://discourse.llvm.org/t/rfc-clarifying-semantic-assumptions-for-custom-allocators/89469
The semantics here are specified in terms of allowed transforms.
Making the semantics operational is tracked in #184102.
[AMDGPU] IGroupLP: Avoid repeating reachability checks in greedy algorithm (#182463)
In the greedy pipeline solver, the group cost is found using the
addEdges function and the edges must be removed from the DAG after
processing each group. The best group edges are then reinserted using
the same function. This repeats the costly reachability checks inside
the function which become problematic for pipelines with many
SchedGroups.
The algorithm is changed to remember the best group edges instead of
recomputing them. Additionally, SchedGroup::tryAddEdge is refactored to
avoid a redundant cycle check which is already performed by DAG->addEdge.
[AArch64][GlobalISel] Limit srem by const of small sizes. (#184066)
The code in SignedDivisionByConstantInfo::get can only handle bitwidths
>= 3. This adds a check for bitwidth==1 for urem too, although it will
already have been simplified.
[libc] Reland add getc, ungetc, fflush to enable libc++ iostream on baremetal (#183556)
After https://github.com/llvm/llvm-project/pull/168931 landed getc,
ungetc and fflush are still missing at link time while trying to make
libc++ std::cout work with LLVM libc on baremetal.
ungetc implementation is very minimal only to cover the current standard
streams implementation from the patch above.
The original PR https://github.com/llvm/llvm-project/pull/175530 caused
build failure on Windows because of too long command line in the
generated *.bat file which was fixed by
https://github.com/llvm/llvm-project/issues/182374
[AMDGPU] IGroupLP: Refactor SchedGroup::initSchedGroup (NFC) (#184122)
There are three overloaded SchedGroup::initSchedGroup functions, two of
which are only used for specific types of SchedGroups, namely
SCHED_BARRIER and SCHED_GROUP_BARRIER. This seems to have a led to some
confusion since the different functions perform checks which are not
needed for their intended restricted use cases. Furthermore, there are
several wrong comments surrounding those functions.
Simplify the functions and inline the actual initialization parts of the
SCHED_BARRIER and SCHED_GROUP_BARRIER variants at their only call sites.
Extract a function that finds the candidate SUnits for a given
SchedGroup and use this instead of initSchedGroup. Fix comments.
[IR] Mark reduction intrinsics as nocreateundeforpoison (#184173)
In investigating #156233, it came up that select folds like here:
https://alive2.llvm.org/ce/z/Y6jzj6 cannot be carried out, or easily
fixed for now, because integer reductions do not propagate noundef, even
if their arguments are noundef. This patch adds this propagation.
[lldb][RISCV] Support RVV register access
Support RISC-V vector register context (2/3)
Add support for reading and writing RISC-V vector (RVV) registers
through the native register context on Linux. This enables LLDB to
access all 32 vector registers (v0–v31) and the vector CSR registers
during debugging sessions.
[lldb][RISCV] Add vector VCSR register definitions
Support RISC-V vector register context (1/3)
Add definitions for RISC-V vector CSRs to support RVV debugging.
This includes the vstart, vl, vtype, vcsr, and vlenb registers,
which control the vector operation state and behavior.
[clang][Sema] Fix initialization of GRO when GRO-return type mismatches (CWG2563) (#179156)
This patch implements one piece of proposed solution to
[CWG2563](https://cplusplus.github.io/CWG/issues/2563.html):
> get-return-object-invocation is as follows:
> ...
> otherwise, get-return-object-invocation initializes a variable with
the exposition-only name gro as if by
> decltype(auto) gro = promise.get_return_object();
Close #98744
[Clang][NFCI] Make unchanged global state const (#183478)
To avoid modifications to global state that does not currently need to
be modified, this patch makes a selection of trivial cases const. This
aims to help preserve the intention of these variables and reduce the
potential mutable global state surface of clang.
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
[Clang][NFCI] Initialize PredefinedNames immediately (#183295)
In isPredefinedUnsafeLibcFunc the set of predefined names is initialized
lazily. However, this pattern is redundant as function-scope static
variables are initialized on first pass through the control flow. This
commit makes the variable constant, makes it a non-heap object, and
initializes it immediately. This has the following benefits:
- The initialization pattern cleaner and potentially easier for the
compiler to optimize.
- Making the variable const avoids it being used as mutable global
state.
- Having immediate initialization removes a potential race condition.
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
[mlir][spirv] Expand verifier testing for spirv.Tosa ops (#184112)
Also keep test order aligned with op definition order.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
