[VectorCombine] Fix foldBitcastOfVPLoad reordering loads (#218336)
We were inserting the new vp.load where the bitcast was, which would
reorder loads. This should hopefully fix RISC-V buildbot failures that
were exposed after 93ac788df8ff
RISCV: Fix VectorPeephole null dereference on an undef vmerge true operand (#218328)
Also since this is an SSA pass, switch to using getVRegDef instead of
getUniqueVRegDef
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
[mlir][vector] Verify multi_reduction reduction dimensions (#216854)
`vector.multi_reduction` does not bounds-check `reduction_dims`.
Out-of-range
entries verify cleanly and then crash the canonicalizer:
```mlir
%0 = vector.multi_reduction <add>, %a, %b [1, 2] : vector<1x4xf16> to vector<1xf16>
```
`getReductionMask()` builds `SmallVector<bool> res(sourceRank)` and
executes
`res[2] = true`. The `[1, -1]` variant indexes `res[(size_t)-1]`.
Reject out-of-range and duplicate dims in the verifier, following
`TransposeOp::verify`. The mask is reused by the shape-inference loop
below.
One existing test is itself the repro: `propagate-layout.mlir` uses `[1,
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RISCV: Fix VLOptimizer null dereference on an undef slide amount (#218329)
Also since this is an SSA pass, switch from getUniqueVRegDef
to regular getVRegDef.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
Reapply [Clang] Mark new as inaccessiblememonly if sane (#217652)
Reapply https://github.com/llvm/llvm-project/pull/197199 without changes
after https://github.com/llvm/llvm-project/pull/201375 improved our
errno TBAA reasoning.
-----
If `-fassume-sane-operator-new` (the default), assume that `operator
new` does not read or write accessible memory.
Currently, this assumption already exists due to special treatment in
BasicAA. I'd like to remove this special treatment (see
https://github.com/llvm/llvm-project/pull/197180), and instead rely only
on the `memory` attribute.
It's worth noting that this is consistent with GCC's interpretation of
the flag (where it is also enabled by default):
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[lldb] Keep DW_OP_call_frame_cfa address-sized (#216684)
`DW_OP_call_frame_cfa` currently constructs a `Scalar` directly from
`lldb::addr_t`. Since `addr_t` is a 64-bit carrier, the result remains
64 bits
when evaluating an expression for a 32-bit target, and subsequent
address
arithmetic does not wrap at the target address width.
Normalize the CFA with the evaluator's existing `to_generic` helper
after it
is pushed. This preserves the existing frame lookup, error handling, and
`LoadAddress` value type while making the scalar use the target address
width.
Add an i386 unit test that verifies both 32-bit address arithmetic and
the
resulting `APSInt` bit width.
Fixes #210980
Fix AppVerifier GetThreadId(NULL) error in llvm::thread (#216941)
A recent change (64be34c562a23761dcb48a0a6a0b3ef0576c14c4) brought up a
behaviour change to the way llvm::thread checks if it is joinable. Prior
to the patch, a thread handle is checked if it's valid. The new
behaviour is to query a thread id and check if it's non-zero.
On Windows, the new behaviour means calling GetThreadId(handle) to
retrieve the thread id. This, however, results in errors when the thread
handle is not pointing to any active thread (NULL) and when running
applications under AppVerifier as it reports that a "system function is
called with a NULL handle". For applications using LLVM infrastructure
(in our case it is a MLIR-based compiler), the call stack looks like:
```
vrfcore!VerifierStopMessageEx+0x858
vfbasics!AVrfpHandleSanityChecks+0x3c
vfbasics!AVrfpNtQueryInformationThread+0x46
KERNELBASE!GetThreadId+0x33
my_app!llvm::llvm_thread_get_id_impl
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[Mips] Use ELF binding when expanding PIC la (#217566)
A symbol already assigned to a section is not necessarily local. Use ELF
symbol binding when expanding PIC `la`, retaining the existing
section-based fallback for non-ELF targets, so defined default-visible
globals use the correct global GOT form.
Adds `llvm/test/MC/Mips/macro-la-pic-defined-global.s` covering global,
local, and `$25` call-register expansions.
Fixes #217371
[docs] Document `-mtriple` option in opt command guide (NFC) (#213942)
`-mtriple` option has been supported for a long time, but previously
lacked documentation.
[BasicAA][TLI] Treat local-linkage globals or known environments as not aliasing errno (#170290)
Errno cannot alias global variables with internal/private-linkage,
neither can it aliases globals on known environments, where errno is
known to be defined as a function call – unless targeting
freestanding/baremetal environments.
[Support] Remove deprecated CTLog2 from MathExtras.h (#218274)
CTLog2 was deprecated in favor of ConstantLog2 and has no remaining
in-tree users, so drop it.
Co-authored-by: Claude <noreply at anthropic.com>
ModuloSchedule: Fix using getVRegDef/getUniqueVRegDef on physregs (#216795)
These should be invalid to use on physical registers, but are currently
permissive. Avoid calling them so in the future they can assert.
Also this pass seems to run in SSA, so shouldn't really be using
getUniqueVRegDef.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[X86] Widen non-power-of-two vector div/rem under strictfp (#217572)
Non power of two vectors bail out of the FP divide fold under strictfp
and scalarize. The SAE forms are 512-bit only so operands widen into a
zmm, and a non power of two lane count has no machine type to widen
through.
This widens to the next power of two first but only while the result
still fits one divide. Past that it splits into two chains and a scalar
divide on the odd lane is cheaper so a shape like v9i32 is unchanged.
Fixes #217558
RISCV: Fix VectorPeephole null dereference on an undef vmerge true operand
Also since this is an SSA pass, switch to using getVRegDef instead of
getUniqueVRegDef
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
RISCV: Fix VLOptimizer null dereference on an undef slide amount
Also since this is an SSA pass, switch from getUniqueVRegDef
to regular getVRegDef.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
[AMDGPU] Model ordered XDL writes in expert scheduling
Treat qualifying XDL WMMA as VA_VDST fences so expert scheduling can use
nonzero waits after out-of-order event mixes.
An XDL instruction with a destination register of 8 or more VGPRs decrements
VA_VDST after all instructions that were issued earlier.
This offers a significant benefit in compute bound kernels since we are not
required to pessimistically wait for WMMAs to write their results when
interleaving LDS.
```
VALU def r0
TRANS
VALU
TRANS
WMMA
va_vdst(1) # previously this would require va_vdst(0)
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[libcxx][FreeBSD] Add comments for unsupported xopen_source.gen.py test (#216002)
FreeBSD _XOPEN_SOURCE == 500 does not satisfy some requirements in
libcxx. As a result, tests fail when trying to find the declarations of
these functions.
[SPARC][IAS] Adjust bounds check in %rX name parsing (#218301)
Fix an off-by-one error that results in %r31 being incorrectly rejected.
This was reported by the folks at OpenBSD.
[BOLT] Add option --merge-text-sections (#217732)
With BOLT optimization enabled the output carries the new hot code in
.text and the cold code in .text.cold, allocated back to back in the
same segment. Some consumers may prefer a single .text covering both.
The two text sections are already in one contiguous address range, so
only the section header table separates them. Under this new option
"--merge-text-sections" the lowest addressed code section keeps the
header, reports the extent of the whole run under the name .text, and
the rest are marked anonymous so no header is written for them. Their
contents and addresses are untouched, which keeps the emitted code byte
for byte identical to the one built without the option.
Symbols defined in a folded section, such as cold fragments, take the
index of the merged section so they won't end up referencing SHN_UNDEF.
Each folded section also gets a local marker symbol, named as
".bolt.pre_merge<original_section_name>", recording the name and start
address it had before the merge, so the previous layout stays
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[VectorCombine] Support simplification to scalar store for multiple insertelt (#132820)
VectorCombine already folds a load–insertelement–store sequence
containing
a single insertion into a scalar store. Extend this fold to chains of
insertelement instructions:
V0 = load vector from p
V1 = insertelement V0, x1, i1
...
Vn = insertelement V(n-1), xn, in
store Vn to p
=>
store x1 to element i1 of the vector at p
...
store xn to element in of the vector at p
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[flang] Do not branch to a FORMAT statement from an assigned GO TO
Label analysis already classifies which labeled statements may be named by
a statement that branches. Record the positions of those statements in the
semantics context and consult it when lowering records the targets of an
assigned GO TO, so that a FORMAT statement is not given a target block.
A GO TO whose variable holds only a format label now reaches the run-time
error instead of branching into the FORMAT statement.
The label analysis is built once and shared: AnalyzeLabels() runs the
constraint checks first and records the branch targets only if they pass,
since a program with fatal errors is not lowered.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
[flang] Record the position of a labeled program-unit END statement (#217842)
The END statement of a program unit is visited in advance, before the
statement visitor has moved its current position onto it, so the
position recorded for a label on that statement was whatever statement
came last -- a null source position for the first program unit in a
file, and the preceding unit's position for the others. Pass the
statement position to AddTargetLabelDefinition explicitly instead of
reading it from the visitor.
A diagnostic anchored on such a label had no location to report:
```fortran
subroutine s(j)
integer :: j
write(*,fmt=40)
go to j
40 end subroutine
```
before:
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[PM] Move PassInfoMixin to detail namespace
To follow up on the TODO and to prevent backslide (which we have had
quite a bit of).
Reviewers: arsenm, nikic, aengelke, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/218198
