LLVM/project 787c4f7 — llvm/include/llvm/Transforms/IPO Instrumentor.h, llvm/lib/Transforms/IPO InstrumentorConfigFile.cpp Instrumentor.cpp

[Instrumentor] Support multiple runtime bitcodes (#216333)

Replace the runtime_bitcode string option with runtime_bitcodes, an
ordered list of runtime bitcode files. Each file is parsed and linked
into the instrumented module in list order, so a runtime can be split
into separate modules, e.g., shared state and callbacks, without merging
them into one file first.

---------

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+43-26llvm/lib/Transforms/IPO/Instrumentor.cpp
+35-0llvm/lib/Transforms/IPO/InstrumentorConfigFile.cpp
+27-3llvm/include/llvm/Transforms/IPO/Instrumentor.h
+18-0llvm/test/Instrumentation/Instrumentor/runtime_bitcodes.ll
+17-0llvm/test/Instrumentation/Instrumentor/runtime_bitcodes_config.json
+16-0llvm/test/Instrumentation/Instrumentor/runtime_bitcodes_preserved_analyses.ll
+156-294 files not shown
+172-3310 files

LLVM/project 509e09a — libc .clang-tidy, libc/src .clang-tidy

[libc] Establish clean baseline for implementation-in-namespace (#231639)

Scope libc/src/.clang-tidy down to llvmlibc-implementation-in-namespace
with WarningsAsErrors to establish a 100% green baseline.

Add NOLINT comments to replaceable global allocation functions in
new.cpp which must reside in the global namespace. Disable default
clang-analyzer checks in libc/.clang-tidy with a leading '-*'.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+9-1libc/src/__support/CPP/new.cpp
+2-5libc/src/.clang-tidy
+1-1libc/.clang-tidy
+12-73 files

LLVM/project 3b6b7cb — llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer VecUtils.cpp

[SandboxVec][LoadStoreVec] Support constant vectors of mixed types
DeltaFile
+400-4llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_mixed_types.ll
+118-26llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+53-0llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
+23-23llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
+6-28llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+10-12llvm/unittests/Passes/PassBuilderBindings/PassBuilderBindingsTest.cpp
+610-937 files not shown
+657-9713 files

LLVM/project 8f0a6c6 — llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU AMDGPUSearchableTables.td

Identify async intrinsics with marker class
DeltaFile
+8-91llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+56-21llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+4-26llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+68-1383 files

LLVM/project 2604e32 — llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp SIISelLowering.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

[NFC][AMDGPU] Create tables for async-related intrinsics
DeltaFile
+101-0llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+37-31llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+4-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-15llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+3-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+147-635 files

LLVM/project 997d36e — llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU AMDGPUSearchableTables.td AMDGPUInstructionSelector.cpp

Narrow marker class to LDSDMA intrinsics
DeltaFile
+29-59llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+17-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5-13llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+4-13llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+15-2llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+0-3llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+70-946 files

LLVM/project b07ab20 — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp

Update attributor name
DeltaFile
+4-4llvm/docs/AMDGPUUsage.rst
+1-1llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+5-52 files

LLVM/project 4614b0c — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUSubtarget.cpp AMDGPULowerIntrinsics.cpp

Re-apply demotion logic

This reverts commit 992e6130ed441b82490f9a6cf01f5bba38293e4e.
DeltaFile
+1,321-821llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
+29-24llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll
+20-7llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+10-0llvm/docs/AMDGPUUsage.rst
+2-4llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+4-0llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+1,386-8562 files not shown
+1,390-8588 files

LLVM/project 3514c68 — llvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Transforms/IndVarSimplify ult-nonneg-bound-implies-nonneg.ll

[SCEV] Derive x >=s 0 from x <u y when y is non-negative

If x <u y and y <=u 2^(n-1) (e.g. y >=s 0), then x >=s 0.

Prove this in SCEV's isImpliedCondBalancedTypes so a guard
like "start <u len" proves start >=s 0. This also covers
x <=u y with y up to INT_MAX, which reaches the implication
code canonicalized as x <u y + 1.

The query is proven from the derived fact via
isImpliedCondOperands, so weaker bounds (x >=s c, c <= 0) follow
too.

y is checked via ranges only, to keep compile time low.

Co-Authored-By: Claude Sonnet 5.5 <noreply at anthropic.com>
DeltaFile
+15-19llvm/unittests/Analysis/ScalarEvolutionTest.cpp
+19-0llvm/lib/Analysis/ScalarEvolution.cpp
+4-10llvm/test/Transforms/IndVarSimplify/ult-nonneg-bound-implies-nonneg.ll
+38-293 files

LLVM/project 40d9fbf — llvm/test/Transforms/IndVarSimplify ult-nonneg-bound-implies-nonneg.ll, llvm/unittests/Analysis ScalarEvolutionTest.cpp

[SCEV][NFC] Precommit tests for x <u y && y >=s 0 implying x >=s 0

SCEV derives x <s y from x <u y && y >=s 0, but not x >=s 0, so a loop
guarded by "start <u len" with a non-negative len does not prove
start >=s 0.

Add unit tests for isImpliedCond and the end-to-end guard queries, and
an IndVars lit test.
Checks SCEV cannot prove yet are marked FIXME.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+340-0llvm/test/Transforms/IndVarSimplify/ult-nonneg-bound-implies-nonneg.ll
+209-0llvm/unittests/Analysis/ScalarEvolutionTest.cpp
+549-02 files

LLVM/project 33f9999 — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULowerIntrinsics.cpp SIMemoryLegalizer.cpp

Split demotion logic out
DeltaFile
+7-20llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+0-10llvm/docs/AMDGPUUsage.rst
+3-4llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll
+3-3llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
+4-2llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+2-3llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma-async.ll
+19-422 files not shown
+19-508 files

LLVM/project 4f58f66 — llvm/test/CodeGen/AMDGPU amdgpu-attributor-no-lds-dma.ll

Clean up lit tests
DeltaFile
+22-23llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-lds-dma.ll
+22-231 files

LLVM/project f0c5a19 — llvm/lib/Target/AMDGPU AMDGPUAttributor.cpp, llvm/test/CodeGen/AMDGPU annotate-kernel-features-hsa.ll annotate-kernel-features-hsa-call.ll

Rename attribute and clean up qualifying set of instructions

"no-async" was based on an imprecise use of the word "async", which also
confused me during its implementation, so I also removed
unintentionally-added intrinsics from the set of intrinsics this
attribute checks for.
DeltaFile
+0-286llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-async.ll
+241-0llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-lds-dma.ll
+21-21llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
+21-21llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+16-16llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
+13-13llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
+312-35733 files not shown
+414-46439 files

LLVM/project c86db7c — llvm/test/CodeGen/AMDGPU memory-legalizer-single-wave-workgroup-lds-dma-async.ll memory-legalizer-single-wave-workgroup-memops.ll

Bring attributor changes to this PR in the stack
DeltaFile
+4-3llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll
+3-3llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-memops.ll
+3-2llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma-async.ll
+10-83 files

LLVM/project faef630 — llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp

Remove unnecessary condition on ordering strength
DeltaFile
+1-8llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+1-81 files

LLVM/project 1b50303 — llvm/docs AMDGPUUsage.rst

Remove unnecessary paragraph
DeltaFile
+0-5llvm/docs/AMDGPUUsage.rst
+0-51 files

LLVM/project 0a872cf — llvm/docs AMDGPUUsage.rst

Link to `amdgpu-async-operations`
DeltaFile
+2-2llvm/docs/AMDGPUUsage.rst
+2-21 files

LLVM/project a0ac0c7 — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp

Prohibit demotion if function contains LDSDMA
DeltaFile
+15-5llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+11-8llvm/docs/AMDGPUUsage.rst
+5-2llvm/test/CodeGen/AMDGPU/lds-dma-war.ll
+4-2llvm/test/CodeGen/AMDGPU/lds-dma-war-async.ll
+35-174 files

LLVM/project 5671542 — llvm/lib/Target/AMDGPU AMDGPUAttributor.cpp, llvm/test/CodeGen/AMDGPU annotate-kernel-features-hsa-call.ll amdgpu-attributor-min-agpr-alloc.ll

Check for async operations through attributor
DeltaFile
+496-176llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
+286-0llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-async.ll
+112-80llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+90-88llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll
+97-1llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+31-30llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
+1,112-37535 files not shown
+1,311-53141 files

LLVM/project e6d9dc3 — llvm/lib/Target/AMDGPU AMDGPUAttributor.cpp

Convert `if` with unreachable `else` to an assert
DeltaFile
+3-3llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+3-31 files

LLVM/project a047ff5 — llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULowerIntrinsics.cpp SIMemoryLegalizer.cpp

Reapply "[AMDGPU] Use wavefront scope for single-wave workgroup synchronization (#187673)"
DeltaFile
+176-496llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
+80-112llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+25-7llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+12-0llvm/docs/AMDGPUUsage.rst
+2-5llvm/test/CodeGen/AMDGPU/lds-dma-war.ll
+2-4llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+297-6243 files not shown
+307-6289 files

LLVM/project bf80cbc — llvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Transforms/IndVarSimplify ult-nonneg-bound-implies-nonneg.ll

[SCEV] Derive x >=s 0 from x <u y when y is non-negative

If x <u y and y <=u 2^(n-1) (e.g. y >=s 0), then x >=s 0.

Prove this in SCEV's isImpliedCondBalancedTypes so a guard
like "start <u len" proves start >=s 0. This also covers
x <=u y with y up to INT_MAX, which reaches the implication
code canonicalized as x <u y + 1.

The query is proven from the derived fact via
isImpliedCondOperands, so weaker bounds (x >=s c, c <= 0) follow
too.

y is checked via ranges only, to keep compile time low.

Co-Authored-By: Claude Sonnet 5.5 <noreply at anthropic.com>
DeltaFile
+15-19llvm/unittests/Analysis/ScalarEvolutionTest.cpp
+18-0llvm/lib/Analysis/ScalarEvolution.cpp
+3-8llvm/test/Transforms/IndVarSimplify/ult-nonneg-bound-implies-nonneg.ll
+36-273 files

LLVM/project 4d2bc2c — clang/test/Analysis/Scalable/ssaf-orchestrator-make library-only.test link-unit-selection.test, clang/tools/clang-ssaf-orchestrator-make/lib/clang_ssaf_orchestrator_make/shims ar.py

[clang][ssaf] Interpose ar in clang-ssaf-orchestrator-make (#231618)

Add an ar shim so that static libraries built by the project take part
in the analysis. It records the members of each archive it writes and
links their summaries with clang-ssaf-linker static-library create. In
the transformation pass it merges their edits, as the ld shim does for a
link.

The ld shim now takes archives as inputs, so a program linked against an
in-project library includes the translation units behind it.
DeltaFile
+148-0clang/tools/clang-ssaf-orchestrator-make/tests/test_ar_shim.py
+102-0clang/tools/clang-ssaf-orchestrator-make/lib/clang_ssaf_orchestrator_make/shims/ar.py
+54-0clang/test/Analysis/Scalable/ssaf-orchestrator-make/link-units.test
+44-0clang/test/Analysis/Scalable/ssaf-orchestrator-make/prebuilt-archive.test
+36-1clang/test/Analysis/Scalable/ssaf-orchestrator-make/link-unit-selection.test
+35-0clang/test/Analysis/Scalable/ssaf-orchestrator-make/library-only.test
+419-111 files not shown
+484-2717 files

LLVM/project 7619ee7 — llvm/lib/Transforms/IPO AttributorAttributes.cpp, llvm/test/Transforms/Attributor memory-behavior-instruction-value.ll

Attributor: Only use anchor instruction effects for call site positions

AAMemoryBehavior initialized the known state of a position from the
mayReadFromMemory/mayWriteToMemory of its anchor instruction. This is
only correct when the anchor is the call. For a floating pointer value
defined by a load, the load does not write, but the pointer may still be
written through. AAInvariantLoadPointer then marked loads as invariant
that were clobbered in the same function, which miscompiled sqlite3 with
-attributor-enable=full.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+43-0llvm/test/Transforms/Attributor/memory-behavior-instruction-value.ll
+12-5llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+1-1llvm/test/Transforms/OpenMP/parallel_deletion.ll
+56-63 files

LLVM/project e187ac6 — llvm/test/CodeGen/AMDGPU memory-legalizer-single-wave-workgroup-lds-dma-async.ll

Add asyncmarks
DeltaFile
+5-0llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma-async.ll
+5-01 files

LLVM/project 2df2d3d — clang/include/clang/CIR/Dialect/IR CIRAttrs.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Emit the frame-pointer function attribute and module flag (#230697)

CIR now honors -mframe-pointer= for the functions CIRGen emits, the way
classic CodeGen does. Functions and the module carry a new
#cir.frame_pointer attribute. On a function it lowers to the
"frame-pointer" function attribute, and on the module LowerToLLVM turns
it into the "frame-pointer" module flag, which LLVM gives to the
functions it creates later.

Assisted-by: Cursor / claude-opus-5.5

---------

Co-authored-by: Henrich Lauko <xlauko at mail.muni.cz>
DeltaFile
+102-0clang/test/CIR/Lowering/frame-pointer.cir
+93-0clang/test/CIR/CodeGen/frame-pointer.cpp
+60-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+49-0clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+34-13clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+31-0clang/test/CIR/IR/func-attrs.cir
+369-138 files not shown
+445-1514 files

LLVM/project 6f7e316 — llvm/cmake/modules GetHostTriple.cmake, llvm/test lit.site.cfg.py.in

[CMake] Special-case HarmonyOS hosts in get_host_triple() (#219882)
DeltaFile
+39-1llvm/cmake/modules/GetHostTriple.cmake
+28-0llvm/test/CMake/get-host-triple.test
+25-0llvm/test/CMake/Inputs/get-host-triple.cmake
+1-0llvm/test/lit.site.cfg.py.in
+1-0llvm/test/CMake/lit.local.cfg
+94-15 files

LLVM/project 9544b29 — mlir/python/mlir/runtime np_to_memref.py, mlir/test/python execution_engine.py

[mlir][python] Handle rank-zero MemRefs in NumPy conversion (#231403)

I found this while testing MLIR's NumPy MemRef helpers in wasm32 and
wasm64 xeus-python kernels.(Basically while working on my RFC :
https://discourse.llvm.org/t/rfc-bringing-interactive-mlir-compilation-and-execution-to-webassembly/91566/3)

Rank-zero descriptors have no `shape` or `strides`, but
`ranked_memref_to_numpy()` accesses those fields and raises
`AttributeError`. Handle them as scalar NumPy views, preserving the
offset and shared storage.

The regression covers float32, float16 and complex64, including nonzero
offsets. Added a new file. Can club with the execution_engine.py tests
too if required.
DeltaFile
+32-0mlir/test/python/execution_engine.py
+2-0mlir/python/mlir/runtime/np_to_memref.py
+34-02 files

LLVM/project 7f70bc7 — llvm/lib/Target/NVPTX NVPTXISelLowering.cpp, llvm/test/CodeGen/NVPTX atomicrmw.py atomicrmw-sm90.ll

[NVPTX] Set default value of nvptx-allow-ftz-atomics to false

This restores the strict FTZ default originally introduced in #200732
and temporarily relaxed in #206154.

Frontends can now explicitly opt in to native FTZ-mismatched atomics on a
per-instruction basis using !atomic.ignore.denormal.mode metadata (#217585,
#217586), which is supported in Clang, MLIR, and XLA. Users who need the
previous behavior globally can still pass -nvptx-allow-ftz-atomics=true.

Update test cases to verify the new default disallow behavior.
DeltaFile
+36-37llvm/test/CodeGen/NVPTX/atomicrmw-ignore-denormal-mode.ll
+6-5llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+4-4llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
+2-2llvm/test/CodeGen/NVPTX/atomicrmw.py
+2-2llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+2-2llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+52-522 files not shown
+55-558 files

LLVM/project f20249c — llvm/lib/Transforms/IPO AttributorAttributes.cpp Attributor.cpp, llvm/test/Transforms/Attributor callsite-returned-type-mismatch.ll

Attributor: Don't use callee return attributes for mismatched call types

A call site returned position took the state and attributes of the
callee's returned position, even if the call uses a different return type
than the callee, e.g. calling a void function as returning ptr. This
asserted in AANonNull::isImpliedByIR on the non-pointer callee return
type, and put the callee's nofpclass on calls returning another FP type.
Ignore the callee's returned position, and its returned arguments, if the
types differ.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>



DeltaFile
+118-0llvm/test/Transforms/Attributor/callsite-returned-type-mismatch.ll
+6-2llvm/lib/Transforms/IPO/Attributor.cpp
+5-0llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+129-23 files