LLVM/project 3c355d1 — offload/libompaccsupport device.cpp, offload/test/offloading/fortran target-no-loop.f90

[OpenMP][offload] Apply the low-trip rule to no-loop kernels (#234660)

Use the same low-trip logic for no-loop that we're also using for
regular SPMD loops.
That means in particular that we try to use the preferred number of
blocks and trade threads for blocks if there are not enough loop
iterations.
The default #blocks for an MI200 would be 4*#CUs, aka 416. If we have a
loop with 256 threads/block but only a tripcount of 512, we use the
minimal #threads/block, aka 32 and then choose #blocks accordingly.

This is an upstream port of the corresponding downstream.

Claude assisted with this patch.
DeltaFile
+68-45offload/libompaccsupport/device.cpp
+7-0offload/test/offloading/fortran/target-no-loop.f90
+75-452 files

LLVM/project 2198ea8 — llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU BUILD.gn

[gn build] Port cfc479d87d4ec (#238308)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
+1-01 files

LLVM/project c76687d — llvm/utils/gn/secondary/llvm/lib/ABI BUILD.gn, llvm/utils/gn/secondary/llvm/unittests/ABI BUILD.gn

[gn build] Port 12e5222ba3478 (#238307)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/unittests/ABI/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/lib/ABI/BUILD.gn
+2-02 files

LLVM/project a2ded84 — llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/test/CodeGen/AMDGPU unsupported-image-sample.ll llvm.amdgcn.image-insts.err.ll

[AMDGPU] Guard image intrinsics with image-insts feature. (#238123)

The llvm.amdgcn.image.* intrinsics, other than the already guarded BVH
ones, did not require any target feature. On subtargets without image
instructions, such as gfx942, gfx950, gfx1250, gfx1251 and the generic
targets, they reached instruction selection and either asserted, failed
with a fatal "cannot select" error, or silently produced image
instructions that the assembler rejects for that subtarget.

Require image-insts so that both SelectionDAG and GlobalISel diagnose
them instead. This also rejects zero-dmask image intrinsics that
instruction selection would otherwise drop as no-ops.

Assisted by: Opus 5.5
DeltaFile
+47-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image-insts.err.ll
+2-2llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
+1-0llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+50-23 files

LLVM/project 129c78a — llvm/lib/Transforms/Vectorize VPlan.h

[VPlan] Strip bad TODO for VPI::execute (NFC) (#237928)

The TODO does not make sense, as unrolled parts for all recipes are
uniformly handled by VPlanUnroll. The remaining comment for VPI::execute
doesn't add value either.
DeltaFile
+0-3llvm/lib/Transforms/Vectorize/VPlan.h
+0-31 files

LLVM/project d2fc6dc — libc/src/__support/OSUtil/linux/syscall_wrappers CMakeLists.txt rt_sigsuspend.h, libc/src/signal sigsuspend.h

[libc] Implement sigsuspend in signal (#237223)

Add the standard POSIX function sigsuspend to <signal.h>:
- Add low-level rt_sigsuspend system call wrapper in
libc/src/__support/OSUtil/linux/syscall_wrappers/rt_sigsuspend.h.
- Add public header declaration in libc/src/signal/sigsuspend.h.
- Implement sigsuspend entrypoint in
libc/src/signal/linux/sigsuspend.cpp.
- Declare sigsuspend in libc/include/signal.yaml.
- Register entrypoint for Linux (x86_64, aarch64, riscv) in architecture
config files.
- Update CMakeLists.txt files across syscall wrappers, signal sources,
and tests.
- Add unit tests in libc/test/src/signal/sigsuspend_test.cpp.

Part of #236167
DeltaFile
+79-0libc/test/src/signal/sigsuspend_test.cpp
+34-0libc/src/__support/OSUtil/linux/syscall_wrappers/rt_sigsuspend.h
+33-0libc/src/signal/linux/sigsuspend.cpp
+26-0libc/src/signal/sigsuspend.h
+21-0libc/test/src/signal/CMakeLists.txt
+13-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+206-06 files not shown
+234-012 files

LLVM/project c00d7f7 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.raw.buffer.load.format.d16.ll llvm.amdgcn.struct.buffer.load.format.d16.ll

[AMDGPU] llvm.amdgcn.*.buffer.load.format.d16.ll - regenerate checks (#238285)

Clean up work for the topological sorting patch to make codegen diffs
more obvious
DeltaFile
+77-26llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
+56-23llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
+133-492 files

LLVM/project daeda2d — llvm/docs AMDGPUUsage.md AMDGPUUsage.rst, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.896bit.ll amdgcn.bitcast.960bit.ll

Merge branch 'main' into users/huntergr-arm/vector-lsr-data
DeltaFile
+88,705-91,244llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,383-26,405llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+0-22,228llvm/docs/AMDGPUUsage.rst
+9,311-9,381llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,998-9,209llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+18,116-0llvm/docs/AMDGPUUsage.md
+150,513-158,46710,856 files not shown
+691,045-463,36710,862 files

LLVM/project 436dfdc — mlir/lib/Dialect/Affine/Transforms RaiseMemrefDialect.cpp, mlir/test/Dialect/Affine raise-memref.mlir

[mlir][affine] Add arith.subi support to memref to affine raise (#222880)

This PR adds support for `arith.subi` to `toAffineExpr` to e.g. allow
matching expressions like `i-1` which appear with one-indexed arrays.
DeltaFile
+59-1mlir/test/Dialect/Affine/raise-memref.mlir
+9-6mlir/lib/Dialect/Affine/Transforms/RaiseMemrefDialect.cpp
+68-72 files

LLVM/project 7fa2a58 — clang/docs ReleaseNotes.md, clang/lib/Sema SemaDeclCXX.cpp

[clang] Fix extra error message (#235427)

When auto* is used in a structured binding, Clang reports an error
because this declaration is not allowed. However, it also reports
another error about the initializer type, which is unnecessary.

This change removes the invalid pointer from the declarator instead of
marking the declaration as invalid, allowing Clang to continue type
deduction and keep the structured bindings usable in subsequent code.

Added test cases for different invalid auto declarations.

Used LLM to identify the issue and understand the code.

Fixes #222605
DeltaFile
+56-0clang/test/SemaCXX/GH222605.cpp
+13-2clang/lib/Sema/SemaDeclCXX.cpp
+5-0clang/docs/ReleaseNotes.md
+1-1clang/test/Parser/cxx1z-decomposition.cpp
+75-34 files

LLVM/project abfd903 — llvm/include/llvm/Analysis ScalarEvolution.h, llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Don't recurse into isKnownPredicate from IsKnownPredicateViaAddRecStart

isKnownViaNonRecursiveReasoning is meant to use non-recursive checks, but
one of them, IsKnownPredicateViaAddRecStart, proves a predicate on two
AddRecs by calling isKnownPredicate on the AddRecs start values.

The start values may themselves be AddRecs of another loop.
For example, when a loop's IV starts at the exit value of the previous loop's IV.

Then that query recurses into every loop of such a chain, and each level
tries several proofs, so the number of queries grows exponentially with
the length of the chain.

Now prove the predicate on the start values with
isKnownViaNonRecursiveReasoning too, instead of isKnownPredicate.

This is less precise.
Before, isKnownPredicate could also prove the query by splitting the predicate,
and by induction.

    [3 lines not shown]
DeltaFile
+329-0llvm/test/Transforms/IndVarSimplify/addrec-start-chain.ll
+7-5llvm/lib/Analysis/ScalarEvolution.cpp
+8-2llvm/test/Transforms/IndVarSimplify/addrec-start-outer-induction.ll
+8-0llvm/include/llvm/Analysis/ScalarEvolution.h
+352-74 files

LLVM/project c6e2adc — llvm/lib/CodeGen CodeGenPrepare.cpp, llvm/test/Transforms/CodeGenPrepare/AArch64 strength-reduce-vector-as-data.ll

Address comments
DeltaFile
+31-28llvm/lib/CodeGen/CodeGenPrepare.cpp
+0-6llvm/test/Transforms/CodeGenPrepare/AArch64/strength-reduce-vector-as-data.ll
+31-342 files

LLVM/project 02c227b — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/ARM extracted-subfields-cost.ll

[SLP]Credit single-use operand chains of extracted sub-fields

Shifts and truncations that feed only the extracted fields die with
them, so their scalar cost is credited back as well.

Assisted-by: Cursor

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/238293
DeltaFile
+31-18llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1-1llvm/test/Transforms/SLPVectorizer/ARM/extracted-subfields-cost.ll
+32-192 files

LLVM/project 4929b7d — clang/lib/CIR/CodeGen CIRGenExprScalar.cpp, clang/test/CIR/CodeGenOpenCL vector.cl

[CIR][OpenCL] Fix vector ternary with unsigned condition or operands (#237750)

Use a signed MSB test and bitcast operands to match its type
DeltaFile
+31-0clang/test/CIR/CodeGenOpenCL/vector.cl
+6-4clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+37-42 files

LLVM/project 3651777 — llvm/include/llvm/Transforms/Utils LoopPeel.h, llvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopPeel] Peel last iteration to enable load widening

In loops that contain multiple consecutive small loads (e.g., 3 bytes
loading i8's), peeling the last iteration makes it safe to read beyond
the accessed region, enabling the use of a wider load (e.g., b32) for
all other N-1 iterations.

Patterns such as:
```
  %a = load i8, ptr %p
  %b = load i8, ptr %p+1
  %c = load i8, ptr %p+2
  ...
  %p.next = getelementptr i8, ptr %p, 3
```

Can be transformed to:
```
  %wide = load b32, ptr %p     ; Read 4 bytes

    [19 lines not shown]
DeltaFile
+652-131llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening.ll
+324-10llvm/lib/Transforms/Utils/LoopPeel.cpp
+51-16llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening-be.ll
+55-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening-disabled.ll
+6-0llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+6-0llvm/include/llvm/Transforms/Utils/LoopPeel.h
+1,094-1571 files not shown
+1,098-1577 files

LLVM/project 5fd4333 — llvm/test/Transforms/LoopUnroll/AArch64 peel-last-iteration-load-widening-be.ll peel-last-iteration-load-widening.ll

[NFC][LoopPeel] Add tests for load widening
DeltaFile
+1,717-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening.ll
+87-0llvm/test/Transforms/LoopUnroll/AArch64/peel-last-iteration-load-widening-be.ll
+1,804-02 files

LLVM/project b15ec3d — utils/bazel/llvm-project-overlay/llvm BUILD.bazel

Fix bazel build for #238017 (#238290)

Fix bazel build for #238017.
DeltaFile
+2-2utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+2-21 files

LLVM/project c444d8c — flang/lib/Lower/Support ReductionProcessor.cpp

[flang] Fix build on MacOS (#238284)

```
flang/lib/Lower/Support/ReductionProcessor.cpp:1134:31: error: use 'template' keyword to treat 'lookupSymbol' as a dependent template name
01:06:39    1134 |           builder.getModule().lookupSymbol<OpType>(reductionName)) {
01:06:39         |                               ^
01:06:39         |                               template
01:06:39   1 error generated.
```

I instead split the expression to match other code in the file.
DeltaFile
+2-2flang/lib/Lower/Support/ReductionProcessor.cpp
+2-21 files

LLVM/project 7ec8850 — llvm/include/llvm/Analysis ScalarEvolution.h, llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Don't recurse into isKnownPredicate from IsKnownPredicateViaAddRecStart

isKnownViaNonRecursiveReasoning is meant to use non-recursive checks, but
one of them, IsKnownPredicateViaAddRecStart, proves a predicate on two
AddRecs by calling isKnownPredicate on the AddRecs start values.

The start values may themselves be AddRecs of another loop.
For example, when a loop's IV starts at the exit value of the previous loop's IV.

Then that query recurses into every loop of such a chain, and each level
tries several proofs, so the number of queries grows exponentially with
the length of the chain.

Now prove the predicate on the start values with
isKnownViaNonRecursiveReasoning too, instead of isKnownPredicate.

This is less precise.
Before, isKnownPredicate could also prove the query by splitting the predicate,
and by induction.

    [3 lines not shown]
DeltaFile
+322-0llvm/test/Transforms/IndVarSimplify/addrec-start-chain.ll
+7-5llvm/lib/Analysis/ScalarEvolution.cpp
+9-2llvm/test/Transforms/IndVarSimplify/addrec-start-outer-induction.ll
+6-0llvm/include/llvm/Analysis/ScalarEvolution.h
+344-74 files

LLVM/project 6e5a44f — llvm/lib/CodeGen/GlobalISel CombinerHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel udiv.i32.ll srem.i64.ll

[GlobalISel] Combine shifted power-of-two division and nonnegative signed div/rem (#236601)

Fold unsigned division by a shifted power-of-two constant into a logical
right shift. Convert signed division and remainder to unsigned
operations when both operands are known nonnegative.

Add MIR regression coverage and update AMDGPU assembly checks.

Fixes #236481

Assisted by: Claude Opus 5.5
DeltaFile
+532-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-intdiv.mir
+42-393llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
+157-161llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+150-156llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+6-60llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
+47-0llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+934-7704 files not shown
+977-79510 files

LLVM/project e6fbe04 — clang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp, clang/test/CIR/CodeGen complex-div-promoted-long-double.c

[CIR] Fix complex promoted division for double (#234289)

While working on long double format attribute, I wanted to make sure CIR
passes pick up and use the info correctly, however the possible affected
place where we figure out long double type on the fly was always
hardcoded to use `long_double<double>` type. It should use targetinfo's
long double instead, taking `-mlong-double` options into account.

Assisted-by: claude
DeltaFile
+53-0clang/test/CIR/CodeGen/complex-div-promoted-long-double.c
+15-3clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+68-32 files

LLVM/project dcf2789 — llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 kshift.ll

[X86] combineKSHIFT - move kshiftr(extract_subvector(X,C1),C2) handling to SimplifyDemandedVectorElts (#237324)

The combineKSHIFT fold didn't ensure that we retain zero in the
upper/shifted elements - we're better off handling this in
SimplifyDemandedVectorElts where we can still fold if we don't need the
zero'd elements

Fixes #235657
DeltaFile
+18-6llvm/lib/Target/X86/X86ISelLowering.cpp
+1-1llvm/test/CodeGen/X86/kshift.ll
+19-72 files

LLVM/project 5f967fa — utils/bazel/llvm-project-overlay/flang/unittests BUILD.bazel

Fix for #216960 (#238286)

Fix for #216960.
DeltaFile
+8-4utils/bazel/llvm-project-overlay/flang/unittests/BUILD.bazel
+8-41 files

LLVM/project eeb1dbf — llvm/test/CodeGen/AArch64 fixed-length-masked-stores.ll fixed_masked_interleaved_stores.ll, llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64 expand-masked-store.ll expand-masked-load.ll

[AArch64] Make all fixed-width masked loads/stores legal on SVE targets (#232757)

The loop vectoriser already generates calls to illegal fixed-width
masked loads and stores regardless of whether the TTI hook says
they are legal or not. Presumably it's because this is preferrable
to manually scalarising the operation at the IR level by introducing
blocks and control flow. However, it does mean that when SVE is
available the code quality is poor, particularly for wider-than-legal
types such as <32 x i8>. This patch returns true from the TTI hook
for all fixed-width types to prevent the ScalarizeMaskedMemIntrin
pass prematurely scalarising the masked operations when we can
use SVE instead.

This PR also makes it easier for us to use SVE in future for
wide masked loads with deinterleaving or wide masked stores with
interleaving. In such cases we should be able to lower the IR to
the SVE masked ld2/st2/etc instructions.
DeltaFile
+508-437llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
+96-812llvm/test/CodeGen/AArch64/fixed-length-masked-loads.ll
+472-429llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
+98-723llvm/test/CodeGen/AArch64/fixed-length-masked-stores.ll
+56-3llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/expand-masked-load.ll
+52-1llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/expand-masked-store.ll
+1,282-2,4051 files not shown
+1,282-2,4117 files

LLVM/project 5594e34 — llvm/test/CodeGen/X86 vector-shuffle-sse4a.ll

[X86] vector-shuffle-sse4a.ll - add AVX2 test coverage (#238265)
DeltaFile
+86-115llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll
+86-1151 files

LLVM/project 7ff63a4 — llvm/test/Transforms/IndVarSimplify addrec-start-outer-induction.ll

[IndVarSimplify][NFC] Add a test for a predicate on AddRec starts

Add a test where a predicate on two AddRecs of an inner loop
is implied from the predicate on their start values,
which are IVs of the outer loop, and that predicate can
be proven by induction over the outer loop.

Assisted-By: Claude
DeltaFile
+65-0llvm/test/Transforms/IndVarSimplify/addrec-start-outer-induction.ll
+65-01 files

LLVM/project 42c86f8 — llvm/lib/Target/SPIRV SPIRVCallLowering.cpp, llvm/test/CodeGen/SPIRV spirv_param_decorations.ll

[SPIR-V] Emit ID decorations on function parameters as OpDecorateId (#229089)

Reuse the global decoration path so parameters get `<id>` operands too

Depends on #229056 and #229058
DeltaFile
+3-18llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+11-1llvm/test/CodeGen/SPIRV/spirv_param_decorations.ll
+14-192 files

LLVM/project b8e25fc — offload/libompaccsupport device.cpp, offload/test/offloading get_num_devices_device.c

[Offload][Omp] Use libomptarget values to initialize the Device Environment (#238271)

Use the values for total devices and device id from the libomptarget
side instead of the Plugin Interface.

With this not only we remove another usange of the Plugin Interface, but
make it more correct. As those values were only correct if only one RTL
was being used (probably 99.9% of the cases). This is a likely a
leftover of when it was initialized on the
Plugin side.

New test created by Claude.
DeltaFile
+37-0offload/test/offloading/get_num_devices_device.c
+2-3offload/libompaccsupport/device.cpp
+39-32 files

LLVM/project f6a1d4d — llvm/lib/Transforms/Scalar DeadStoreElimination.cpp, llvm/test/Transforms/DeadStoreElimination multiblock-unreachable.ll

[DSE] Add `@llvm.coro.end.*` calls as roots for CFG walk (#238017)
DeltaFile
+37-3llvm/test/Transforms/DeadStoreElimination/multiblock-unreachable.ll
+14-2llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+51-52 files

LLVM/project d7328f1 — offload/include PluginManager.h Platform.h, offload/libompaccsupport CMakeLists.txt PluginManager.cpp

[Offload][Omp] Replace usages of Plugin getName (#237269)

Create a new class `PlatformTy` to add liboffload platform related
operations. Add a new `getName` method and use it substitute lingering
and already substituted `GenericPluginTy::getName` usages.

The new method also fixes a bug where we were printing an extra `NULL`
character with the platform name.

Assisted by Claude.
DeltaFile
+45-0offload/include/Platform.h
+28-0offload/libompaccsupport/Platform.cpp
+10-16offload/libompaccsupport/PluginManager.cpp
+11-0offload/include/PluginManager.h
+1-0offload/libompaccsupport/CMakeLists.txt
+95-165 files