LLVM/project d3b93dbclang/lib/CodeGen QualTypeMapper.cpp, llvm/include/llvm/ABI Types.h

Revert "[LLVMABI][NFC] Align base class handling with Clang's AST (#218545)" (#220353)

This reverts commit 0260138561bdadca6685e1873d578b892fddf736.

The extra tracking for direct virtual base classes appears not to be
needed.
DeltaFile
+7-14clang/lib/CodeGen/QualTypeMapper.cpp
+2-12llvm/include/llvm/ABI/Types.h
+0-6llvm/lib/ABI/Targets/X86.cpp
+0-4llvm/lib/ABI/Types.cpp
+9-364 files

LLVM/project ae1c3a3llvm/lib/IR AsmWriter.cpp, llvm/lib/Target/AArch64/MCTargetDesc AArch64MCLFIRewriter.cpp

Merge branch 'main' into users/rampitec/monitor-sleep-forever
DeltaFile
+178-236llvm/lib/IR/AsmWriter.cpp
+217-15llvm/test/CodeGen/NVPTX/cache-hint-sm-version.ll
+80-110llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp
+100-60llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+0-124llvm/unittests/IR/AsmWriterTest.cpp
+76-38llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+651-583140 files not shown
+2,252-1,585146 files

LLVM/project 4c791a6clang/docs HardwareAssistedAddressSanitizerDesign.md

[docs] Fix capitalisation of "HWASan" (#220355)
DeltaFile
+1-1clang/docs/HardwareAssistedAddressSanitizerDesign.md
+1-11 files

LLVM/project 9fa1dbflld/ELF Relocations.cpp, lld/test/ELF gcc-except-table-znotext.s

[ELF] Don't emit dynamic relocations into .gcc_except_table with -z notext

The -z notext rule already treats .eh_frame as non-writable, so that a symbolic
relocation there is resolved at link time -- with a copy relocation where one is
needed -- rather than deferred to the loader. The in-tree rationale is that GNU
ld does not produce dynamic relocations in .eh_frame.

The same holds for .gcc_except_table, but it was not covered. Linking a non-PIE
executable whose LSDA type table uses DW_EH_PE_absptr entries naming typeinfos
from a shared library, with -z notext:

  linker   dyn relocs in .gcc_except_table   R_X86_64_COPY
  GNU ld   0                                 3
  gold     0                                 3
  lld      3                                 0

Extend the existing carve-out to .gcc_except_table, including the per-function
sections -ffunction-sections creates, so lld matches GNU ld and gold.
DeltaFile
+47-0lld/test/ELF/gcc-except-table-znotext.s
+9-5lld/ELF/Relocations.cpp
+56-52 files

LLVM/project 238ef87llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp

[AMDGPU] Add `getVGPRAllocGranule` to TargetParser (#220065)

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+28-0llvm/unittests/TargetParser/TargetParserTest.cpp
+16-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+8-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+52-03 files

LLVM/project 7c44c50clang/include/clang/AST DeclBase.h, clang/lib/Sema SemaCoroutine.cpp SemaDeclCXX.cpp

Revert "[Clang] Fix a number of issues involving expansion statements" (#220375)

Reverts llvm/llvm-project#217110

This caused a CI failure in one of the expansion statements tests; I’ll
revert this for now and investigate.
DeltaFile
+0-200clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
+6-24clang/lib/Sema/SemaDeclCXX.cpp
+0-26clang/include/clang/AST/DeclBase.h
+0-16clang/test/SemaCXX/cxx2c-expansion-stmts-warnings.cpp
+9-7clang/lib/Sema/SemaCoroutine.cpp
+8-4clang/test/SemaCXX/expansion-statements-local-extern-decls.cpp
+23-2776 files not shown
+33-28812 files

LLVM/project de1b178llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Support KnownFPClass.cpp

[KnownFPClass] Remove `propagateNonNan` `PreserveSign` parameter (#219841)

`void propagateNonNaN(const KnownFPClass &Src, bool PreserveSign =
false)`
Things work as you would expect if `PreserveSign` is `false`. But when
`PreserveSign` is `true`, it does not do what you would expect (I
thought it would copy the signbit of `NaN`). If `PreserveSign` is
`true`, it will copy `Src.SignBit` if and only if `Src` is never `NaN`,
which is counterintuitive. It also does not properly update
`KnownFPClasses`, and allows for potentially erroneous states to be
generated. Such as `fcNegZero` having a positive sign bit.

I have removed `void propagateNonNaN(const KnownFPClass &Src, bool
PreserveSign = false)` and replaced it with just `void
propagateNonNaN(const KnownFPClass &Src)`.

This fixes https://github.com/llvm/llvm-project/issues/217127

I discovered this while working on
https://github.com/llvm/llvm-project/pull/218514
DeltaFile
+4-4llvm/lib/Support/KnownFPClass.cpp
+2-5llvm/include/llvm/Support/KnownFPClass.h
+2-2llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
+8-113 files

LLVM/project 071b3c2libc/hdr/types char8_t.h, libc/include/llvm-libc-types char8_t.h

[libc] Fix char8_t public and proxy headers. (#220352)
DeltaFile
+17-0libc/hdr/types/char8_t.h
+2-2libc/include/llvm-libc-types/char8_t.h
+19-22 files

LLVM/project 51858dfclang/test/CodeGen link-builtin-bitcode.c, llvm/lib/Target/AMDGPU AMDGPU.td

[AMDGPU] Expose addressable LDS size features to the frontend

Add the FeatureAddressableLocalMemorySize* subtarget features to
AMDGPUFrontendVisibleFeatures so TargetParser carries them in its
per-GPU feature bitset and clang emits them as target features.

A "gfxN-generic" target carries the worst case of the GPUs it covers,
which for a numeric feature is the smallest value: gfx9-4-generic keeps
the 64k size while covering gfx950's 160k. The generic validation in the
-gen-amdgpu-target-def backend rejected that, since it required every
frontend-visible feature of a generic to appear verbatim on each covered
GPU. Numeric features are now compared by value instead, and only an
increase is an error.

Change-Id: Ic442a8ce123e12a14ba956ca5796bbef5b65a942
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+56-39llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+36-0llvm/test/TableGen/AMDGPUTargetDefErrors.td
+10-0llvm/unittests/TargetParser/TargetParserTest.cpp
+3-3clang/test/CodeGen/link-builtin-bitcode.c
+5-0llvm/lib/Target/AMDGPU/AMDGPU.td
+110-425 files

LLVM/project 8d529bbllvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp LegalizeVectorTypes.cpp, llvm/test/CodeGen/NVPTX cache-hint-intrinsics.ll

[SelectionDAG][NVPTX] Support cache hints on masked loads and stores (#215307)

Masked loads/stores support all the same cache hints. When splitting
masked loads/stores during legalization, I duplicate the hints. I think
this makes sense for the eviction hints, but not for prefetching. For
prefetching, it probably makes sense to only preserve the hint on the
first load.

For now, I duplicate the hints no matter what. If we want to support
selectively dropping hints during splitting, we will probably need a
target hook.

AI assisted.
DeltaFile
+84-16llvm/test/CodeGen/NVPTX/cache-hint-intrinsics.ll
+7-4llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+5-2llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+96-223 files

LLVM/project f4689e4llvm/lib/Target/X86 X86CallFrameOptimization.cpp, llvm/test/CodeGen/X86 callframe-opt-undef-push.mir

X86: Handle undef push operands in call frame optimization

Avoid unchecked getVRegDef call, which will fail for undef
operands. The register-push fallback also dropped the undef flag when
rebuilding the store as a PUSH.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+39-0llvm/test/CodeGen/X86/callframe-opt-undef-push.mir
+11-7llvm/lib/Target/X86/X86CallFrameOptimization.cpp
+50-72 files

LLVM/project 69ac946clang/test/SemaCXX cxx2c-expansion-stmts.cpp, llvm/lib/IR AsmWriter.cpp

Merge branch 'main' into users/ziqingluo/PR-post-185840466
DeltaFile
+178-236llvm/lib/IR/AsmWriter.cpp
+217-15llvm/test/CodeGen/NVPTX/cache-hint-sm-version.ll
+200-0clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
+80-110llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp
+100-60llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+0-124llvm/unittests/IR/AsmWriterTest.cpp
+775-545151 files not shown
+2,515-1,610157 files

LLVM/project 07e310cclang/lib/Sema HLSLExternalSemaSource.cpp, clang/test/CodeGenHLSL/resources Textures-Mips.hlsl

[HLSL] Fix initialization of mips' copy of the resource handle (#220349)

This is a fixup to https://github.com/llvm/llvm-project/pull/219561
which left the `mips` member's copy of the resource handle uninitialized
due to reordering of `addCopyConstructor`, `addCopyAssignmentOperator`
and `addStaticInitializationFunctions` to before the optional methods.

This PR particularly fixes the following offload test failures:
```
  OffloadTest-clang-d3d12 :: Feature/Textures/Array.mips.OperatorIndex.test
  OffloadTest-clang-d3d12 :: Feature/Textures/mips.OperatorIndex.test
  OffloadTest-clang-d3d12 :: Tools/Offloader/TextureMipLevelValidation.test
  OffloadTest-clang-vk :: Feature/Textures/Array.mips.OperatorIndex.test
  OffloadTest-clang-vk :: Feature/Textures/mips.OperatorIndex.test
```

Assisted by: Claude Opus 5
DeltaFile
+10-4clang/lib/Sema/HLSLExternalSemaSource.cpp
+13-0clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
+23-42 files

LLVM/project 1e5ad01compiler-rt/lib/ubsan_minimal ubsan_minimal_handlers.cpp

[compiler-rt] Fix undefined abort for ubsan_minimal GPU targets (#220314)

Summary:
When compiling with debug enabled this would call `abort()`. The minimal
UBSan for GPUs is intentionally written to just depend on `printf`
which most vendors support and aborting is done through hardware traps.
I neglected to update this part because I had not done it with debugging
enabled, just wrap this into a helper function.
DeltaFile
+11-7compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+11-71 files

LLVM/project 9c6f8dellvm/lib/Target/AMDGPU AMDGPU.td AMDGPULowerIntrinsics.cpp, llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp

[AMDGPU] s_monitor_sleep shall not use sleep_forever on gfx1250

Fixes: SWDEV-542848
DeltaFile
+32-31llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
+23-0llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+21-0llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+6-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.monitor.sleep.ll
+7-0llvm/lib/Target/AMDGPU/AMDGPU.td
+3-0llvm/test/MC/AMDGPU/gfx1250_asm_sopp_err.s
+92-346 files

LLVM/project 1b4fc7bllvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/lib/Target/NVPTX NVPTXIntrinsics.td NVPTXISelDAGToDAG.cpp

[SDAG][NVPTX] Support cache hints on atomic operations (#214918)

Support cache hints on atomic loads/stores, these have the same support
as normal loads/stores.
Support cache hints on atomicrmw. These will drop everything except for
.level::cache_hint.
Cmpxchg doesn't support cache hints, should drop all.

AI assisted
DeltaFile
+217-15llvm/test/CodeGen/NVPTX/cache-hint-sm-version.ll
+100-60llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+76-38llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+45-15llvm/test/CodeGen/NVPTX/cache-hint-atomics.ll
+30-0llvm/test/CodeGen/NVPTX/cache-hint-invalid.ll
+13-4llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+481-1326 files

LLVM/project 835747fllvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/Target/AMDGPU AMDGPULowerKernelAttributes.cpp R600Subtarget.h

AMDGPU: Move flat work group size constants to AMDGPUTargetParser (#220346)

getMinFlatWorkGroupSize and getMaxFlatWorkGroupSize are constants that
do not depend on the subtarget. Move them from IsaInfo to
AMDGPUTargetParser so they can be queried without an MCSubtargetInfo.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+0-9llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+9-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+2-2llvm/tools/llvm-calc-occupancy/llvm-calc-occupancy.cpp
+2-2llvm/lib/Target/AMDGPU/R600Subtarget.h
+2-2llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
+16-161 files not shown
+16-187 files

LLVM/project be44dfeutils/bazel/llvm-project-overlay/lld/test BUILD.bazel, utils/bazel/llvm-project-overlay/lld/test/COFF BUILD.bazel

[bazel] Add support for lld tests (#220311)
DeltaFile
+94-0utils/bazel/llvm-project-overlay/lld/test/BUILD.bazel
+38-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+29-0utils/bazel/llvm-project-overlay/lld/test/MachO/BUILD.bazel
+23-0utils/bazel/llvm-project-overlay/lld/test/COFF/BUILD.bazel
+23-0utils/bazel/llvm-project-overlay/lld/test/ELF/BUILD.bazel
+23-0utils/bazel/llvm-project-overlay/lld/test/wasm/BUILD.bazel
+230-01 files not shown
+245-07 files

LLVM/project 87d1135llvm/lib/CodeGen MachineModuleSlotTracker.cpp, llvm/lib/IR AsmWriter.cpp

Revert "[IR] Use persistent metadata IDs for printing" (#220334)

This reverts commit 85e903099313aa5ea98d175698aaa40e27a0d743.

The change breaks MSVC builds because an inline SmallPtrSet operation
requires a complete DILocation type. It also causes expensive-check
builds to report that the DXIL pretty-printer modifies its input
without reporting it.

Revert while fixes and test coverage are prepared.

Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/2/builds/60795
Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/187/builds/23268
DeltaFile
+178-236llvm/lib/IR/AsmWriter.cpp
+0-124llvm/unittests/IR/AsmWriterTest.cpp
+56-57llvm/lib/CodeGen/MachineModuleSlotTracker.cpp
+29-78llvm/unittests/MIR/MachineMetadata.cpp
+14-92llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
+0-94llvm/test/Other/print-persistent-metadata-ids.ll
+277-68169 files not shown
+506-1,23875 files

LLVM/project ff7e21dlldb/docs/resources lldbgdbremote.md, lldb/source/Plugins/Process/wasm ProcessWasm.cpp

[lldb] Drop the trailing separator from the qWasmGlobal instance suffix (#220338)

The instance suffix was spelled ";instance:<id>;", which ends a packet
with a separator that separates nothing. Spell it ";instance:<id>" and
avoid the redundant semicolon.
DeltaFile
+3-3lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
+2-2lldb/docs/resources/lldbgdbremote.md
+1-1lldb/source/Plugins/Process/wasm/ProcessWasm.cpp
+6-63 files

LLVM/project 137ffadllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

clang-format
DeltaFile
+8-8llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+8-81 files

LLVM/project 2ca9363llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes BundleVec.cpp

[SandboxVectorizer] Hoist getInsertPointAfterInstrs into VecUtils

Move BottomUpVec.cpp's file-local getInsertPointAfterInstrs() into
VecUtils, next to the getLowest()/getLastPHIOrSelf() primitives it's
built from. It has no BottomUpVec-specific state; the next commit adds a
second caller in LoadStoreVec.

Not hoisting BottomUpVec::createPack() itself here: it asserts a single
common scalar type (VecUtils::getCommonScalarType), which doesn't fit
LoadStoreVec's mixed-type ("enable-diff-types") requirement. That needs
its own extended packer, kept local to LoadStoreVec.cpp rather than
force-fitting the shared version.

No functional change: check-llvm Transforms/SandboxVectorizer passes
(28/28).

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+87-0llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
+6-18llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BundleVec.cpp
+13-0llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+106-183 files

LLVM/project f204c0dclang/include/clang/AST DeclBase.h, clang/lib/Sema SemaCoroutine.cpp SemaDeclCXX.cpp

[Clang] Fix a number of issues involving expansion statements (#217110)

This fixes a number of problems around expansion statements, most of
which arise from the fact that we check if `CurContext` is a
`FunctionDecl` (which it isn't inside of an expansion statement) and
then complain that we're not inside a function (even though we are).

I also updated `DeclContext::isFunctionOrMethod()` to return true for
`CXXExpansionStmtDecl`. That helper already does this for other
`DeclContext`s that aren’t functions or Objective-C methods, but which
to my understanding can only occur in one (e.g. `CapturedDecl` is an
example of this I believe).
DeltaFile
+200-0clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
+24-6clang/lib/Sema/SemaDeclCXX.cpp
+26-0clang/include/clang/AST/DeclBase.h
+7-9clang/lib/Sema/SemaCoroutine.cpp
+16-0clang/test/SemaCXX/cxx2c-expansion-stmts-warnings.cpp
+4-8clang/test/SemaCXX/expansion-statements-local-extern-decls.cpp
+277-236 files not shown
+288-3312 files

LLVM/project 8d1b38fllvm/lib/Target/PowerPC PPCISelLowering.cpp, llvm/test/CodeGen/PowerPC ppc32-f128-abi.ll

Fix `fp128` reaching `llvm_unreachable` on 32-bit PowerPC (#216613)

`fp128` is a legal type that is passed in vector registers when `vsx` is
enabled on 32-bit PowerPC: the switch statement didn't account for that,
causing an LLVM assertion.

Fixes #213355

cc @folkertdev
DeltaFile
+9-0llvm/test/CodeGen/PowerPC/ppc32-f128-abi.ll
+1-4llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+10-42 files

LLVM/project 107f244libcxx/include/__memory assume_aligned.h, lld/test/MachO U-dynamic-lookup.s

Merge branch 'main' into users/hidekisaito/vopd-same-parity-drain
DeltaFile
+80-110llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp
+9-0llvm/docs/LangRef.md
+4-4lld/test/MachO/U-dynamic-lookup.s
+6-0llvm/test/Bitcode/attributes.ll
+2-1libcxx/include/__memory/assume_aligned.h
+2-0llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+103-1156 files

LLVM/project 7a3c125llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU buffer-fat-pointer-atomicrmw-fmin.ll buffer-fat-pointer-atomicrmw-fmax.ll

[AMDGPU][SIInsertWaitcnts] Fix soft wait removal with loop-carried deps

The code that checked if a soft waitcnt (such as the one insterted by
a release fence on LDS) was redundant didn't correctly account for the
fact that that, for example, the previous iteration of a loop could
have introduced memory traffic that needs to be waited on. This bug
appeared to be fairly rare in practice (probably due to the
instruction scheduler shuffling around code in t bad form) but it can
happen.

The fix is that, instad of immediately erasing "redundant" waits, we
add them to a set of waits to be erased, and then remove them from the
set if they prove to be truly redundant.

This has the side effect of fixing a correctness issue around the CAS
loops we emit on gfx1250 - the global_inv we emit after the
`s_loadcnt 0x0` is itself a `loadcnt`-able event, and so needs to be
forced to completion before the next iteration of the CAS loop.


    [5 lines not shown]
DeltaFile
+43-11llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+41-0llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+31-0llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+31-0llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+20-8llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+20-8llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+186-278 files not shown
+229-3114 files

LLVM/project 81dc060llvm/docs LangRef.md

[LangRef] Add hybrid_patchable attribute description (#219806)
DeltaFile
+9-0llvm/docs/LangRef.md
+9-01 files

LLVM/project 91bd18ellvm/lib/Bitcode/Reader BitcodeReader.cpp, llvm/test/Bitcode attributes.ll

[IR] Support hybrid_patchable attribute in bitcode reader (#219804)

Missing in #92965.
DeltaFile
+6-0llvm/test/Bitcode/attributes.ll
+2-0llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+8-02 files

LLVM/project 5f3e8f3libcxx/include/__memory assume_aligned.h

[libc++] Add _LIBCPP_NO_SANITIZE for std::__assume_aligned (#220296)

std::assume_aligned takes void* from __builtin_assume_aligned and
converts it _Tp* that causes cfi-unrelated-cast to consider it a
downcast leading to CFI checks. Since std::find_if calls
std::assume_aligned on __last, it will lead to a CFI check that
dereferences __last causing a failure. Based on discussion, we can just
add _LIBCPP_NO_SANITIZE for cfi-unrelated-cast because the check rejects
well-defined behavior.

Fix: https://github.com/llvm/llvm-project/issues/219306
DeltaFile
+2-1libcxx/include/__memory/assume_aligned.h
+2-11 files

LLVM/project 4004b0bllvm/test/CodeGen/AMDGPU waitcnt-loop-carried-fence-drain.mir waitcnt-loop-carried-fence-drain-gfx12.mir

[AMDGPU] Pre-commit tests for loop-carried memory waits

SIInsertWaitcnts is currently dropping waits in a
(fence; read; write; branch) loop in some cases. Pre-commit tests to
show the problem.

AI disclosure: test generated by AI, but I poked them into not being terrible.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
DeltaFile
+57-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-carried-fence-drain-gfx12.mir
+53-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-carried-fence-drain.mir
+110-02 files