LLVM/project c9b1787mlir/include/mlir/Dialect/Tosa/Utils ConversionUtils.h, mlir/lib/Conversion/TosaToLinalg TosaToLinalg.cpp

[mlir][Tosa] Use split discardable/inherent attribute APIs (#218912)

Use typed operation accessors and explicit discardable attribute APIs in
the Tosa dialect, conversions, target handling, and validation.

Assisted-by: Codex
DeltaFile
+14-9mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+7-7mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
+7-6mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
+4-4mlir/include/mlir/Dialect/Tosa/Utils/ConversionUtils.h
+6-2mlir/lib/Dialect/Tosa/Transforms/TosaNarrowTypes.cpp
+5-1mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+43-295 files not shown
+52-3711 files

LLVM/project 7e329dellvm/test/Analysis/ScalarEvolution ptrtoint.ll

[SCEV] Fix dead CHECK lines in ptrtoint.ll (NFC) (#218932)

There is no CHECK prefix; remove and regenerate with X32/X86 check
lines.

As suggested in https://github.com/llvm/llvm-project/pull/217378.
DeltaFile
+56-27llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
+56-271 files

LLVM/project d1e3942llvm/test/Transforms/LoopVectorize vplan-based-stride-mv.ll, llvm/test/Transforms/LoopVectorize/VPlan vplan-based-stride-mv.ll

Merge branch 'vplan-based-stride-mv-tests' into vplan-based-stride-mv-rt-guard
DeltaFile
+1-2llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+1-2llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+2-42 files

LLVM/project e5bfadfllvm/test/Transforms/LoopVectorize vplan-based-stride-mv.ll, llvm/test/Transforms/LoopVectorize/VPlan vplan-based-stride-mv.ll

Fix formatting
DeltaFile
+1-2llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+1-2llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+2-42 files

LLVM/project c862266llvm/docs MergeFunctions.md, llvm/lib/Transforms/Utils FunctionComparator.cpp

[MergeFunctions] Fix merging functions with different KCFI type identifiers (#217665)

MergeFunctions currently merges functions with identical bodies even
when
their function-level !kcfi_type metadata contains different type
identifiers.

This can redirect calls or function pointers to a function with a
mismatched
KCFI type identifier, potentially causing KCFI checks to fail at
runtime.

Compare function-level !kcfi_type metadata in FunctionComparator so that
functions with different KCFI type identifiers are not merged.

Add a minimal regression test covering two identical functions with
different
KCFI type identifiers.

Fixes #217629
DeltaFile
+112-0llvm/test/Transforms/MergeFunc/kcfi-function-merging.ll
+4-0llvm/lib/Transforms/Utils/FunctionComparator.cpp
+2-0llvm/docs/MergeFunctions.md
+118-03 files

LLVM/project b3a1838llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 pr72777.ll u128-square.ll

[AArch64] Suboptimal assembly for u128 x * x (#214796)

This PR optimizes the AArch64 backend for 128-bit integer squaring
(`u128 x * x`).

It updates the instruction selection logic to combine `(A + B) + B` into
`A + (B << 1)`. This allows the compiler to emit a single, optimal `add
... lsl #1` instruction instead of multiple separate `add` instructions.

A baseline test was added in the first commit, and the optimization is
provided in the second commit to clearly highlight the codegen
improvements.

Fixes #213775
DeltaFile
+30-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+13-6llvm/test/CodeGen/AArch64/reassocmls.ll
+15-0llvm/test/CodeGen/AArch64/u128-square.ll
+2-3llvm/test/CodeGen/AArch64/pr72777.ll
+60-94 files

LLVM/project 6160b5amlir/lib/Dialect/X86/Utils X86Utils.cpp, mlir/test/Dialect/X86 vector-contract-to-packed-type-dotproduct.mlir vector-contract-bf16-to-fma.mlir

[MLIR][X86] Track shuffled write operand updates (#218936)

Notify pattern rewrite listeners while replacing the operands of both
write-like users after accumulator shuffling.

Add focused coverage that does not depend on the separate accumulator
rewrite.

Assisted-by: Codex
DeltaFile
+148-0mlir/test/Dialect/X86/shuffle-before-write.mlir
+6-3mlir/lib/Dialect/X86/Utils/X86Utils.cpp
+0-2mlir/test/Dialect/X86/vector-contract-to-packed-type-dotproduct.mlir
+0-2mlir/test/Dialect/X86/vector-contract-bf16-to-fma.mlir
+154-74 files

LLVM/project 55dd65fllvm/lib/Target/SPIRV SPIRVBuiltins.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product SPV_KHR_integer_dot_product_OCLtoSPIRV_int.ll

[SPIR-V] Diagnose integer dot builtins without SPV_KHR_integer_dot_product (#218599)
DeltaFile
+7-3llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+3-0llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_integer_dot_product/SPV_KHR_integer_dot_product_OCLtoSPIRV_int.ll
+10-32 files

LLVM/project a82267cclang/test/CodeGen/AArch64/neon load.c, llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp

Merge branch 'main' into users/adams381/cir-callconv-union-empty-member
DeltaFile
+1,217-1,125llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+2,240-0clang/test/CodeGen/AArch64/neon/load.c
+853-1,375llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
+815-788llvm/test/CodeGen/AMDGPU/bypass-div.ll
+753-757llvm/test/CodeGen/AMDGPU/memmove-var-size.ll
+17-1,275llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+5,895-5,3201,182 files not shown
+50,808-30,5931,188 files

LLVM/project 169e016clang/test/CodeGen arm-neon-vld.c, clang/test/CodeGen/AArch64 neon-intrinsics.c

Merge branch 'main' into users/adams381/cir-callconv-optout-regen-15
DeltaFile
+2,240-0clang/test/CodeGen/AArch64/neon/load.c
+365-576clang/test/CodeGen/arm-neon-vld.c
+898-0llvm/test/Transforms/ExpandMemCmp/BPF/memcmp.ll
+0-826orc-rt/include/orc-rt/SimplePackedSerialization.h
+826-0orc-rt/include/orc-rt/bedrock/SimplePackedSerialization.h
+0-772clang/test/CodeGen/AArch64/neon-intrinsics.c
+4,329-2,174895 files not shown
+34,369-17,323901 files

LLVM/project d19c232clang/test/CIR/CodeGenOpenACC declare-copyout.cpp declare-copy.cpp

[CIR] Fix tests post 3e3927f (Commit) / #217589 (PR) (#218925)
DeltaFile
+39-40clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
+39-39clang/test/CIR/CodeGenOpenACC/declare-create.cpp
+32-32clang/test/CIR/CodeGenOpenACC/compute-copyin-copyout-create.c
+32-32clang/test/CIR/CodeGenOpenACC/combined-copyin-copyout-create.c
+30-31clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
+30-31clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
+202-2055 files not shown
+280-28311 files

LLVM/project 5d3a3b5flang/test/Analysis/AliasAnalysis alias-analysis-acc.mlir, mlir/include/mlir/Dialect/OpenMP OpenMPOpsInterfaces.td

[mlir][OpenACC][OpenMP] Migrate to use explicit discardable/inherent attribute APIs (#218901)

Use discardable attribute APIs and typed operation accessors throughout
the OpenACC and OpenMP dialects, conversions, translation, utilities,
and tests.

Keep ComputeRegionOp inherent properties in the property dictionary and
discardable attributes in the attribute dictionary.

Assisted-by: Codex
DeltaFile
+47-18mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
+41-20mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
+42-11mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
+18-18mlir/test/Dialect/OpenACC/ops-cg.mlir
+16-16mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array.mlir
+14-14flang/test/Analysis/AliasAnalysis/alias-analysis-acc.mlir
+178-9764 files not shown
+417-28470 files

LLVM/project ae4bae2llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/test/CodeGen/AArch64 sve-load-store-legalisation.ll

[SelectionDAG] Legalize non-divisible scalable vector widening (#218777)

Enable DAGTypeLegalizer::ModifyToType to widen scalable vectors whose
element counts are not integer multiples. Split the source and
destination into their largest common scalable subvector type, extract
the source parts, append poison or zero fill parts, and concatenate
them.
DeltaFile
+132-0llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
+24-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+156-02 files

LLVM/project 3297d6eclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen/AArch64/sme2-intrinsics acle_sme2_reinterpret_svcount_svbool.c

[LLVM][SVE] Add dedicated intrinsics to cast between svcount_t and svbool_t. (#218667)

This makes the casting behaviour more explicit:
> to/from_svbool  : lane-count changing casts
> to/from_svcount : reinterpretation casts
DeltaFile
+2-21llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
+22-0llvm/lib/IR/AutoUpgrade.cpp
+18-0llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
+10-6llvm/include/llvm/IR/IntrinsicsAArch64.td
+2-6clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4-4clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
+58-371 files not shown
+61-417 files

LLVM/project 78a4e95llvm/lib/Transforms/Utils Local.cpp PromoteMemoryToRegister.cpp, llvm/test/Transforms/PhaseOrdering always-inline-alloca-promotion.ll

Revert "Revert "[PromoteMemToReg] Insert store undef when removing lifetime m…"

This reverts commit a4c562fc2bf99462d06f8714eb2a8dd8b1824313.
DeltaFile
+190-0llvm/test/Transforms/SROA/lifetime-aware-phi.ll
+32-3llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
+7-7llvm/test/Transforms/PhaseOrdering/ARM/arm_var_q31.ll
+2-4llvm/test/Transforms/PhaseOrdering/always-inline-alloca-promotion.ll
+3-0llvm/lib/Transforms/Utils/Local.cpp
+1-1llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
+235-156 files

LLVM/project 5ec690clibc/config/baremetal config.json, libc/test/UnitTest CMakeLists.txt ArmBaremetalTestUtils.cpp

[libc] Enable bare-metal hermetic tests on Arm (#207361)

This provides missing components required to run LLVM libc hermetic
tests, for example, with QEMU:
- Redirect of output, time and exit to semihosting.
- Linker script.
- Extra LIBC_MATH_ASSUME_ROUND_NEAREST_ONLY setting for
LIBC_CONF_MATH_OPTIMIZATIONS to make hardfp tests pass.
DeltaFile
+120-0libc/test/UnitTest/llvm-libc-baremetal.ld
+119-0libc/test/UnitTest/ArmBaremetalTestUtils.cpp
+9-1libc/test/UnitTest/CMakeLists.txt
+1-1libc/config/baremetal/config.json
+249-24 files

LLVM/project 5ae09b3clang/test/CIR/CodeGen record-type-metadata.cpp vtable-linkage-explicit-instantiation.cpp, clang/test/CIR/CodeGenCXX typeid-most-derived.cpp

[CIR] Drop the callconv opt-out from 4 more CIR tests (#218785)

These four CIR tests now compile and check clean with x86_64
calling-convention lowering on, unblocked by the packed-record (#218505)
and vptr-record (#218457) work. Stripping the flag moved zero CHECK
lines: the output the pass produces for these four is exactly what was
already pinned.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+2-4clang/test/CIR/CodeGenCXX/typeid-most-derived.cpp
+2-4clang/test/CIR/CodeGen/vtable-linkage-explicit-instantiation.cpp
+2-4clang/test/CIR/CodeGen/trivial-abi.cpp
+1-4clang/test/CIR/CodeGen/record-type-metadata.cpp
+7-164 files

LLVM/project 9b160a2llvm/include module.modulemap

[modulemap] Add OMPDescriptors.h.inc to modulemap of the OpenMP module
DeltaFile
+3-0llvm/include/module.modulemap
+3-01 files

LLVM/project c7fb9a1llvm/lib/CodeGen MachinePipeliner.cpp, llvm/test/CodeGen/AMDGPU swp-amdgpu-pipeline-max-mii.ll

[MachinePipeliner] Increase the default maximum MII to 256

The pipeliner rejects a loop whose minimum initiation interval exceeds
-pipeliner-max-mii. Its default of 27 suits targets with short instruction
latencies, but is too small for others: on AMDGPU a couple of MFMA
instructions already push the MII past it, so the loop never pipelines.

Increase the default limit from 27 to 256. An explicit -pipeliner-max-mii
still overrides the default.
DeltaFile
+5-5llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-max-mii.ll
+2-2llvm/lib/CodeGen/MachinePipeliner.cpp
+7-72 files

LLVM/project 538411cllvm/lib/Target/AMDGPU GCNSubtarget.h GCNSubtarget.cpp, llvm/test/CodeGen/AMDGPU swp-amdgpu-pipeline-regpressure-retry.mir

[AMDGPU] Configure the software pipeliner policy (#212539)

```
    [AMDGPU] Configure the software pipeliner policy
    
    Set the pipeliner policy in overridePipelinerPolicy() to opt into the generic
    register-pressure detector.
    
    Schedules exceeding the target-provided pressure-set limits are rejected and
    retried at a higher II.
```
DeltaFile
+181-0llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-regpressure-retry.mir
+6-0llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+2-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+189-03 files

LLVM/project fee7e4elibcxx/src/support new.ipp

[libc++][NFC] Refactor new.ipp so the _impl functions take a failure mode argument (#218648)

This avoids duplicating the failure path everywhere we use these
functions. It also makes it more explicit what the intended failure path
is.
DeltaFile
+17-12libcxx/src/support/new.ipp
+17-121 files

LLVM/project daed480clang/test/CIR/CodeGen partial-array-cleanup.cpp array-ctor.cpp, clang/test/CIR/CodeGenOpenACC atomic-write.cpp

[CIR] Regenerate CHECK lines for 8 more callconv opt-out tests

These 8 CIR tests compile clean with x86_64 calling-convention lowering
on, but their CHECK lines still pinned the pre-coercion CIR: raw record
types in signatures, plain by-value loads for temporaries with a
non-trivial destructor, and matching store/load pairs for empty
records.  The pass now emits the ABI-correct shape instead: sret return
parameters, a dropped or byref-marked argument for records that carry
no data or that need pass-by-reference, and a `#cir.poison` placeholder
where a value the pass ignores used to be stored.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+14-28clang/test/CIR/CodeGen/cleanup-conditional-with-wrapper.cpp
+14-28clang/test/CIR/CodeGen/cleanup-conditional-with-wrapper-eh.cpp
+7-13clang/test/CIR/CodeGen/array-ctor.cpp
+8-12clang/test/CIR/CodeGen/paren-list-agg-init.cpp
+5-9clang/test/CIR/CodeGen/partial-array-cleanup.cpp
+5-6clang/test/CIR/CodeGenOpenACC/atomic-write.cpp
+53-962 files not shown
+61-1068 files

LLVM/project 9087b13llvm/test/CodeGen/AMDGPU sdwa-peephole-movrels.mir

[AMDGPU] Regenerate CHECK lines for sdwa-peephole-movrels.mir (NFC) (#218888)

Address post-merge comment from
https://github.com/llvm/llvm-project/pull/218592
DeltaFile
+14-3llvm/test/CodeGen/AMDGPU/sdwa-peephole-movrels.mir
+14-31 files

LLVM/project 0877565llvm/lib/Target/AMDGPU AMDGPULowerModuleLDSPass.cpp, llvm/test/CodeGen/AMDGPU lds-run-twice.ll

[AMDGPU] Make LowerModuleLDS a noop on an already lowered module (#217075)

Full LTO reruns the pass on each codegen partition, where it matched its
own lowered structs and re-expanded their constexpr uses
DeltaFile
+38-2llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
+11-5llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+49-72 files

LLVM/project fa1d193libc/shared rpc.h

[libc] Slight optimization for small send_n / recv_n buffers (#218551)

Summary:
Adds a convergent short-circuit condition that lets the compiler
optimize out this loop better in cases where the size is known. Without
this sometimes the compiler could not figure out that a constant size
did not need the extra loop and the backedges would remain.
DeltaFile
+16-16libc/shared/rpc.h
+16-161 files

LLVM/project aff169fclang/docs/analyzer checkers.md

Address review comments
DeltaFile
+21-8clang/docs/analyzer/checkers.md
+21-81 files

LLVM/project 677fc71clang/docs LanguageExtensions.md, clang/lib/Frontend CompilerInvocation.cpp

[Clang][AIX] Error on -mloadtime-comment-vars in cc1 for non-AIX targets

The driver continues to warn and drop the option for unsupported targets;
cc1, reachable directly or via -Xclang, now rejects it with
err_drv_unsupported_opt_for_target, mirroring the -mabi=quadword-atomics
and -mxcoff-roptr checks.
DeltaFile
+4-19clang/test/CodeGen/PowerPC/loadtime-comment-vars.c
+6-6clang/test/Sema/loadtime-comment-vars.c
+6-0clang/lib/Frontend/CompilerInvocation.cpp
+0-5clang/lib/Sema/SemaDecl.cpp
+0-1clang/docs/LanguageExtensions.md
+16-315 files

LLVM/project 37bb2c5llvm/lib/TargetParser Triple.cpp, llvm/test/CodeGen/AMDGPU validate-subtarget-subarch.ll

AMDGPU: Touch up gfx1250-strict definition details

Rename the subarch triple enum for consistency, and place
it next to 1250. Add expanded test coverage.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+38-4llvm/unittests/TargetParser/TargetParserTest.cpp
+12-0llvm/test/CodeGen/AMDGPU/validate-subtarget-subarch.ll
+4-3llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+7-0llvm/unittests/TargetParser/TripleTest.cpp
+3-3llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
+1-1llvm/lib/TargetParser/Triple.cpp
+65-113 files not shown
+68-149 files

LLVM/project 0e1d76allvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Strip unused Ty arg in getPreStartForExtend (NFC) (#218918)

To avoid confusion.
DeltaFile
+2-2llvm/lib/Analysis/ScalarEvolution.cpp
+2-21 files

LLVM/project 0df60d6llvm/lib/CodeGen MachineLICM.cpp, llvm/test/CodeGen/X86 machinelicm-hoist-before-succ-args.mir

MachineLICM: Fix preheader insertion point with SUCC_ARGS

Hoist loop-invariant instructions to getBlockEndInsertPt() instead of
getFirstTerminator(), so they land before the SUCC_ARGS cluster rather
than inside it.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+48-0llvm/test/CodeGen/X86/machinelicm-hoist-before-succ-args.mir
+2-2llvm/lib/CodeGen/MachineLICM.cpp
+50-22 files