LLVM/project 43510f4 — clang-tools-extra/docs/clang-tidy/checks/altera single-work-item-barrier.md struct-pack-align.md, clang-tools-extra/docs/clang-tidy/checks/boost use-ranges.md

by Zeyi Xu on ⎇
[clang-tidy][docs] Rewrite check docs in six modules to Markdown
DeltaFile
+187-188clang-tools-extra/docs/clang-tidy/checks/cert/err33-c.md
+154-155clang-tools-extra/docs/clang-tidy/checks/boost/use-ranges.md
+71-73clang-tools-extra/docs/clang-tidy/checks/altera/unroll-loops.md
+38-39clang-tools-extra/docs/clang-tidy/checks/altera/struct-pack-align.md
+34-36clang-tools-extra/docs/clang-tidy/checks/altera/single-work-item-barrier.md
+31-33clang-tools-extra/docs/clang-tidy/checks/concurrency/mt-unsafe.md
+515-5244 files not shown
+620-63310 files

LLVM/project f6ea145 — llvm/include/llvm/CodeGen AsmPrinter.h, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

by Owen Anderson via GitHub on ⎇
[CHERI][RISCV][MC] Add shared support for aligning globals to an "alignment granule", which is applied to both the alignment and the allocated size. (#203872)

On CHERI targets, bounds are generally stored in a compressed format
which imposes alignment requirements based on allocation size. When
emitting globals, we need to align and tail-pad them as appropriate to
ensure that the pointer to the global will have bounds that are precise,
i.e. not covering any non-padding bytes that either precede or follow

While this patch adds the plumbing necessary to support this feature on
arbitrary targets, it only concretely implements it for RISCV Y-base and
XCheriot. Support for other targets (such as AArch64/MTE and
AArch64/Morello) is left as future work here.

Based on https://github.com/llvm/llvm-project/pull/121957

Co-authored-by: Florian Mayer <fmayer at google.com>

Co-authored-by: Florian Mayer <fmayer at google.com>
DeltaFile
+26-0llvm/test/CodeGen/RISCV/cheri-global-bounds.ll
+21-0llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+19-1llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+14-0llvm/include/llvm/CodeGen/AsmPrinter.h
+80-14 files

LLVM/project df9f345 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.struct.buffer.load.format.ll llvm.amdgcn.intersect_ray.ll, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.struct.buffer.load.tfe.ll llvm.amdgcn.raw.buffer.load.tfe.ll

by Anshil Gandhi on ⎇
[AMDGPU][GlobalISel] Fold redundant uniform G_AMDGPU_READANYLANE in RegBankCombiner
DeltaFile
+124-264llvm/test/CodeGen/AMDGPU/packed-fp32.ll
+69-144llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+80-97llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+36-108llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
+36-108llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
+32-83llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
+377-80412 files not shown
+561-91418 files

LLVM/project 44bfe98 — clang/test/Analysis/Scalable/source-edit-generation/Plugins/TestTransformationPlugin CMakeLists.txt

by Ziqing Luo on ⎇
remove duplicates
DeltaFile
+0-3clang/test/Analysis/Scalable/source-edit-generation/Plugins/TestTransformationPlugin/CMakeLists.txt
+0-31 files

LLVM/project bd439d5 — llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/test/Transforms/LoopVectorize/RISCV interleaved-cost.ll

by Luke Lau via GitHub on ⎇
[RISCV] Don't overcost wide load in optimized segment load/store (#207146)

With the +optimized-nfX-segment-load-store tuning flag, we cost a
segmented store as a single wide load + some shuffle ops.

However for e.g. a `<vscale x 5 x i64>` Factor=5 segmented load, a wide
`<vscale x 5 x i64>` load gets costed as a full LMUL 8 load.

From what I can see on
https://camel-cdr.github.io/rvv-bench-results/spacemit_x100/index.html
and on my own measurements on the spacemit-x60, uarchs likely don't do a
full LMUL 8 load under the hood and instead dispatch the minimum number
of DLEN sized ops needed for the full segment.

This changes the wide load cost to be divideCeil(vector size, DLEN) ops
so we don't overcost it.

Whilst we're here, this also removes the LT.first legalization
multiplier. We're computing the cost in terms of the unlegalized type so
we shouldn't be scaling it by the legalization cost.
DeltaFile
+28-28llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll
+9-5llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+37-332 files

LLVM/project 806e8ad — orc-rt/include CMakeLists.txt, orc-rt/include/orc-rt Proxy.h

by Lang Hames via GitHub on ⎇
[orc-rt] Add Proxy, a protocol-agnostic controller-call handle (#217792)

Introduce Proxy<RetT(ArgTs...)>, a typed handle for invoking a
controller-side operation from the executor. A Proxy abstracts over how
a call reaches the controller: it holds an opaque callee tag and a
dispatch function (supplied by a per-protocol spec) and forwards calls
through the Session.

This is a cut-down port of llvm/ExecutionEngine/Orc/Proxy.h, with two
deliberate differences:

- The callee is identified by an opaque tag (const void *, typically the
address of a controller-side global) rather than an ExecutorAddr, since
the executor->controller direction dispatches by tag.

- Only the asynchronous (OnComplete) call operator is provided. The
blocking convenience operator is omitted: the executor may be
single-threaded or freestanding and cannot rely on std::promise/future
or on blocking a dispatch thread.

    [2 lines not shown]
DeltaFile
+98-0orc-rt/include/orc-rt/Proxy.h
+94-0orc-rt/test/unit/ProxyTest.cpp
+1-0orc-rt/test/unit/CMakeLists.txt
+1-0orc-rt/include/CMakeLists.txt
+194-04 files

LLVM/project 8c78d4b — clang/test/Analysis/Scalable/source-edit-generation/Plugins/TestTransformationPlugin TestTransformation.cpp CMakeLists.txt

by Ziqing Luo on ⎇
[SSAF] Fix a stage2 test failure with ASan-instrumented clang - continued

The previous effort in PR#211432 that disables ASan for one static
global is not sufficient. This commit disables ASan for the whole test
plugin.

rdar://182623740
DeltaFile
+13-0clang/test/Analysis/Scalable/source-edit-generation/Plugins/TestTransformationPlugin/CMakeLists.txt
+0-3clang/test/Analysis/Scalable/source-edit-generation/Plugins/TestTransformationPlugin/TestTransformation.cpp
+13-32 files

LLVM/project 155dade — utils/bazel/llvm-project-overlay/llvm BUILD.bazel

by Corentin Kerisit via GitHub on ⎇
[bazel] Select Windows GNU BLAKE3 assembly for clang-cl (#217695)

## Motivation

This PR is motivated by ongoing work of providing a fully hermetic
clang-cl bazel toolchain built for windows with the MSVC runtime.

The LLVM Bazel overlay does not select a Windows-compatible BLAKE3
assembly source set for an x86_64 Windows target compiled with the
rules_cc `clang-cl` compiler dialect.

The `windows_gnu.S` name can be misleading here. "GNU" describes the
assembly syntax accepted by GNU-style assemblers and Clang's integrated
assembler; it does **not** mean that the implementation uses the MinGW
ABI or runtime. These files implement the Microsoft x64 calling
convention and are intended to produce Windows COFF objects.

A hermetic clang-cl toolchain can therefore assemble the GNU-syntax
Windows sources directly. Selecting the MASM-syntax `windows_msvc.asm`

    [25 lines not shown]
DeltaFile
+13-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+13-01 files

LLVM/project 89920d6 — llvm/lib/Target/RISCV RISCVZacasABIFix.cpp RISCVTargetMachine.cpp

by Sam Elliott via GitHub on ⎇
[RISCV][NFC] Rename create*LegacyPass functions (#217761)

This is to clarify which functions are creating legacy passes rather
than NewPM passes.
DeltaFile
+3-3llvm/lib/Target/RISCV/RISCV.h
+2-2llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-2llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+1-1llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+8-84 files

LLVM/project 7af8a5f — clang/test/Analysis/Scalable/source-edit-generation/Plugins/TestTransformationPlugin TestTransformation.cpp CMakeLists.txt

by Ziqing Luo on ⎇
tmp
DeltaFile
+13-0clang/test/Analysis/Scalable/source-edit-generation/Plugins/TestTransformationPlugin/CMakeLists.txt
+0-3clang/test/Analysis/Scalable/source-edit-generation/Plugins/TestTransformationPlugin/TestTransformation.cpp
+13-32 files

LLVM/project eaeafbe — llvm/lib/Target/AMDGPU SIRegisterInfo.cpp AMDGPUCallingConv.td

by kpyzhov_amdeng on ⎇
[AMDGPU] Set "preserved" bits in register bitmask for all VGPRs and SGPRs for amdgpu_cs_chain and amdgpu_cs_chain_preserve calling conventions.
DeltaFile
+4-0llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
+1-1llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+5-12 files

LLVM/project 984644f — llvm/docs HowToCrossCompileLLVM.md

by Shubh via GitHub on ⎇
[docs] Fix CMAKE_CROSSCOMPILING spelling in HowToCrossCompileLLVM (#217623)

## Summary

The HowToCrossCompileLLVM option list spelled the CMake variable as
`CMAKE_CROSSCOMPIILING` (extra I). The linked CMake docs use
`CMAKE_CROSSCOMPILING`.

Assisted-by: Grok (xAI)
DeltaFile
+1-1llvm/docs/HowToCrossCompileLLVM.md
+1-11 files

LLVM/project efd61aa — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVOptWInstrs.cpp

by Sam Elliott on ⎇
Header to RISCV.h, rename to createRISCVOptWInstrsLegacyPass
DeltaFile
+0-35llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+8-2llvm/lib/Target/RISCV/RISCV.h
+2-2llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+1-2llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+11-414 files

LLVM/project 0ab88bd — llvm/lib/Target/RISCV RISCVCodeGenPassBuilder.cpp RISCVOptWInstrs.h, llvm/test/CodeGen/RISCV O3-newpm-pipeline.ll O1-newpm-pipeline.ll

by Sam Elliott on ⎇
[RISCV] Port Opt W Instrs to NewPM

Assisted-by: AI
DeltaFile
+44-22llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+35-0llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+2-3llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+2-1llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+2-1llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+89-276 files not shown
+96-2812 files

LLVM/project c717856 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVFoldMemOffset.cpp

by Sam Elliott on ⎇
Header to RISCV.h, rename to createRISCVFoldMemOffsetLegacyPass
DeltaFile
+0-36llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+10-0llvm/lib/Target/RISCV/RISCV.h
+2-2llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+1-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+13-394 files

LLVM/project 9394d7c — llvm/lib/Target/RISCV RISCVFoldMemOffset.cpp

by Sam Elliott on ⎇
Preserve MachineRegisterClassAnalysis
DeltaFile
+1-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+1-01 files

LLVM/project e1ed7c4 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp, llvm/test/CodeGen/RISCV fold-mem-offset.mir

by Sam Elliott on ⎇
[RISCV] Port Fold Memory Offset Pass to NewPM

Assisted-by: AI
DeltaFile
+37-16llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+36-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/fold-mem-offset.mir
+76-213 files not shown
+79-219 files

LLVM/project 370e618 — llvm/lib/Target/RISCV RISCVCodeGenPassBuilder.cpp RISCVVectorPeephole.cpp

by Sam Elliott on ⎇
Header to RISCV.h, rename to createRISCVVectorPeepholeLegacyPass
DeltaFile
+0-39llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+12-2llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+0-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+13-434 files

LLVM/project 8f2bd1f — llvm/lib/Target/RISCV RISCVVectorPeephole.cpp

by Sam Elliott on ⎇
Preserve MachineRegisterClassAnalysis
DeltaFile
+1-0llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+1-01 files

LLVM/project 9c30947 — llvm/lib/Target/RISCV RISCVCodeGenPassBuilder.cpp RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.mir rvv-peephole-vmerge-to-vmv.mir

by Sam Elliott on ⎇
[RISCV] Port Vector Peephole to NewPM

Assisted-by: AI
DeltaFile
+67-45llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+39-0llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+2-2llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+2-0llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
+114-486 files not shown
+120-4812 files

LLVM/project a2c7603 — utils/bazel/llvm-project-overlay/compiler-rt compiler-rt.bzl BUILD.bazel

by Chandler Carruth via GitHub on ⎇
Improve compiler-rt build structure and export compilation info (#190088)

This first improves the structure of the compiler-rt BUILD.bazel, fixing
bugs and exposing more carefully arranged source files.

It also exposes compilation info for builtins and CRT files for use in
compiling these source files.
DeltaFile
+228-61utils/bazel/llvm-project-overlay/compiler-rt/BUILD.bazel
+155-0utils/bazel/llvm-project-overlay/compiler-rt/compiler-rt.bzl
+383-612 files

LLVM/project e3a1704 — mlir/lib/Dialect/OpenACC/Transforms ACCCGToGPU.cpp, mlir/test/Dialect/OpenACC acc-cg-to-gpu-reduction-array.mlir

by Matsu via GitHub on ⎇
[mlir][acc] Keep worker-only launches unaligned in ACCCGToGPU (#217382)

Example:
```fortran
!$acc parallel loop worker reduction(+:s) num_workers(16) vector_length(8)
```

In this code, a ThreadY reduction forced blockDim.x to a warp, and
blockDim.y
was divided by the same factor to hold the thread count, so the launch
ran as
(32, 4, 1): 4 workers instead of 16, with the folded-away workers turned
into
ThreadX lanes redoing each other's work.

Fix: skip the alignment when only the workers ask for it and the row
width
divides the subgroup size. Worker reductions combine their partials in
the

    [6 lines not shown]
DeltaFile
+143-66mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+85-4mlir/test/Dialect/OpenACC/acc-cg-to-gpu-reduction-array.mlir
+228-702 files

LLVM/project 9f5034d — llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize reduction-with-invariant-store.ll

by Luke Lau via GitHub on ⎇
[VPlan] Fix replaceWithFinalIfReductionStore assert with multiple reductions (#217316)

A reductions final value can be simplified away to a constant, which
https://github.com/llvm/llvm-project/pull/201023 handled in
replaceWithFinalIfReductionStore.
However constant live ins can have other users, e.g. a different
reductions start value, in which case the assertion will fail because
we're comparing the backedge value of a different reduction entirely.
Relax the assertion to allow any VPIRValue instead

This an alternative to https://github.com/llvm/llvm-project/pull/217306
that fixes #215071
DeltaFile
+39-0llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+40-12 files

LLVM/project ef55c1e — clang/lib/Driver/ToolChains Clang.cpp, clang/test/CodeGenCUDA offload_via_llvm_math.cu

by Sophia Herrmann on ⎇
add math functions
DeltaFile
+252-0clang/test/CodeGenCUDA/offload_via_llvm_math.cu
+137-0offload/languages/include/kernel/LanguageMath.h
+71-36clang/lib/Driver/ToolChains/Clang.cpp
+107-0offload/test/offloading/language/math.cpp
+12-0clang/test/Driver/gpu-libc.c
+3-0offload/languages/include/hip/hip_runtime.h
+582-363 files not shown
+587-369 files

LLVM/project 80e627c — clang/test/CIR/CodeGen static-members.cpp static-local.cpp, clang/test/CIR/CodeGenCXX global-refs.cpp

by Andy Kaylor via GitHub on ⎇
[CIR] Use CIR type for __dso_handle (#217790)

When CIR's LoweringPrepare pass created the runtime variable for
`__dso_handle` while emitting a guarded dtor region, it was creating the
handle using the builtin `i8` type rather than the CIR equivalent. This
caused the `__cxa_atexit` function to be created with a pointer to that
type, which causes problems for the CIR calling convention lowering
pass.

This change updates the pass to use the CIR type.
DeltaFile
+6-6clang/test/CIR/CodeGen/thread-local-in-func.cpp
+6-6clang/test/CIR/CodeGen/global-tls-dyn-init.cpp
+6-6clang/test/CIR/CodeGen/global-init.cpp
+4-4clang/test/CIR/CodeGen/static-local.cpp
+3-3clang/test/CIR/CodeGen/static-members.cpp
+2-2clang/test/CIR/CodeGenCXX/global-refs.cpp
+27-274 files not shown
+34-3410 files

LLVM/project c3a7864 — llvm/lib/Target/Mips Mips64InstrInfo.td, llvm/test/CodeGen/Mips madd-msub.ll sll64_64-is-not-a-copy.mir

by Daniel Lehmann via GitHub on ⎇
[MIPS] Don't mark SLL64_64 as isMoveReg (#214060)

I was running into a Rust miscompilation using pretty standard code (see
bugreport). I had Claude rootcause this to an LLVM bug, where SLL (on 64
bit) is marked as "move", even though it isn't - for full 64-bit values
(with arbitrary upper 32 bits), SLL is not a move as the upper bits get
just sign extended.

The fix itself is tiny and makes sense to me (I know MIPS very well, but
have little LLVM expertise myself). The test for this however is pretty
convoluted as it is quite hard to trigger this bug reliably - it needs
quite some register pressure to actually happen.

On the llvm/test/CodeGen/Mips/madd-msub.ll change: Register indices
changed here as the is the register allocator is now picking a new
independent register instead of reusing an existing one (`sll $4, $4, 0`
changes to `sll $1, $4, 0`). In this particular example that causes
instruction counts to be the same, though in other examples a small
increase is possible (cost of correctness).

    [3 lines not shown]
DeltaFile
+134-0llvm/test/CodeGen/Mips/sll64_64-is-not-a-copy.mir
+42-42llvm/test/CodeGen/Mips/madd-msub.ll
+7-6llvm/lib/Target/Mips/Mips64InstrInfo.td
+183-483 files

LLVM/project d106925 — llvm/lib/IR DebugInfo.cpp, llvm/test/Transforms/Util strip-nonlinetable-debuginfo-linkagename.ll

by Haohai Wen via GitHub on ⎇
[DebugInfo] Preserve linkage names for profiling (#217536)

Keep DISubprogram linkage names when stripping non-line-table debug
info if the compile unit has debugInfoForProfiling set. This mirrors
-gline-tables-only, which keeps linkage names when
-fdebug-info-for-profiling is enabled.
DeltaFile
+39-0llvm/test/Transforms/Util/strip-nonlinetable-debuginfo-linkagename.ll
+4-1llvm/lib/IR/DebugInfo.cpp
+43-12 files

LLVM/project 98b36be — clang/lib/Driver/ToolChains SPIRV.cpp, clang/test/Driver sycl-link-spirv-target.cpp

by Yury Plyakhin via GitHub on ⎇
[clang][SYCL] Derive -triple=/-arch= for clang-sycl-linker in the driver (#217492)

A direct `clang --target=spirv64-unknown-unknown --sycl-link a.bc` does
not tell clang-sycl-linker which device it is finalizing for.
Derive the triple from the target the driver was given, and the
architecture from -march=, and pass them as -triple=/-arch=.

An absent -march= means no specific device was requested. That is
spelled as an absent -arch=, matching how clang-linker-wrapper renders
an offload image that names no device.

A caller may also name these via -Xlinker/-Wl, or (through
clang-linker-wrapper) via -Xoffload-linker. clang-sycl-linker keeps the
last value of each, so derived values are added before an explicitly
given values.

With the driver deriving both values, the SYCL-specific forwarding in
clang-linker-wrapper becomes redundant - it spelled the triple and the
architecture out through -Xlinker after having already passed the very

    [2 lines not shown]
DeltaFile
+13-0clang/test/Driver/sycl-link-spirv-target.cpp
+13-0clang/lib/Driver/ToolChains/SPIRV.cpp
+2-7clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+2-2clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
+1-1clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-verbose.c
+31-105 files

LLVM/project 1574432 — clang/include/clang/Basic HLSLIntrinsics.td, clang/test/CodeGenHLSL/builtins fma.hlsl f32tof16.hlsl

by Farzon Lotfi via GitHub on ⎇
[HLSL][LongVec] enable support for all elementwise apis (#216905)

resolves #216103

This change turns on VaryingLongVector for all HLSL intrinsics that map
to an elementwise builtin.

assisted by  GPT 5.6-Sol via Copilot
DeltaFile
+42-0clang/include/clang/Basic/HLSLIntrinsics.td
+24-6clang/test/CodeGenHLSL/builtins/clip.hlsl
+10-0clang/test/CodeGenHLSL/builtins/f32tof16.hlsl
+10-0clang/test/CodeGenHLSL/builtins/f16tof32.hlsl
+0-8clang/test/SemaHLSL/BuiltIns/clamp-errors.hlsl
+8-0clang/test/CodeGenHLSL/builtins/fma.hlsl
+94-1440 files not shown
+305-1446 files

LLVM/project b14c84c — mlir/include/mlir/Dialect/LLVMIR LLVMAttrDefs.td, mlir/lib/CAPI/Dialect LLVM.cpp

by Gibran Essa via GitHub on ⎇
[MLIR][LLVM] Support DWARF v6 source language names in DICompileUnitAttr (#217432)

Adds support to the LLVM dialect `DICompileUnitAttr` for DWARF v6 source
language name and version .

`DICompileUnitAttr`'s `sourceLanugage` field now points to a
`DISourceLanguageNameAttr`, which contains all source language
information, including dialect, name, and version. This is done to map
as closely as possible to `llvm::DISourceLanguageName`.

`DISourceLanguageNameAttr` has parameters for:
- An DW_LANG_* language.
- A DWARF v6 DW_LNAME_* name, which can only be set if the language is
not.
- An optional language-dependent version.
- An optional target-specific language dialect.

Parsers and printers are added so if only a language is passed, it is
parsed and printed in as before this change.

Assistance from codex was used in this PR.
DeltaFile
+85-5mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
+64-5mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+31-0mlir/test/Dialect/LLVMIR/invalid-di-compile-unit-source-language.mlir
+29-1mlir/lib/CAPI/Dialect/LLVM.cpp
+24-2mlir/test/Target/LLVMIR/llvmir-debug.mlir
+24-0mlir/test/Dialect/LLVMIR/di-compile-unit-source-language.mlir
+257-138 files not shown
+355-3314 files