LLVM/project 3718ab2llvm/utils/gn/secondary/llvm/lib/Support BUILD.gn

[gn build] Port c437052c (#199709)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
+1-01 files

LLVM/project 49cecfbllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV vec3-base.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+24-15llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
+16-10llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
+4-8llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
+6-4llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+50-374 files

LLVM/project b344380clang/test/CodeGen scoped-atomic-ops.c, clang/test/CodeGenCUDA atomic-options.hip amdgpu-kernel-arg-pointer-type.cu

Revert "[clang] remove lots of "innocuous" addrspacecasts (#197745)"

This reverts commit 2825dfa027e62693753593a8e80511ea88fea6c1.
DeltaFile
+852-568clang/test/CodeGen/scoped-atomic-ops.c
+216-144clang/test/CodeGenCUDA/atomic-options.hip
+103-95clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
+41-60clang/test/CodeGenCXX/amdgcn-func-arg.cpp
+54-36clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
+42-32clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp
+1,308-93534 files not shown
+1,560-1,15640 files

LLVM/project 1bada04clang/include/clang/Basic DiagnosticParseKinds.td, clang/lib/Parse ParseExprCXX.cpp

address review comments
DeltaFile
+5-13clang/lib/Parse/ParseExprCXX.cpp
+2-2clang/test/C/C2y/n3267.c
+0-3clang/include/clang/Basic/DiagnosticParseKinds.td
+7-183 files

LLVM/project c927d44utils/bazel/llvm-project-overlay/libc BUILD.bazel, utils/bazel/llvm-project-overlay/llvm BUILD.bazel

Revert "Revert "[libc] Port 2b2a63819f9f26d661bad5c269a03077d22ff6b4"" (#199681)

Reverts llvm/llvm-project#197857.
Original change relanded as #199570
DeltaFile
+507-1utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+508-12 files

LLVM/project fe4c2bbmlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp XeGPUSgToLaneDistribute.cpp, mlir/test/Dialect/XeGPU sg-to-lane-distribute-unit.mlir sg-to-wi-experimental-unit.mlir

[mlir][xegpu] Deprecate XeGPUSubgroupDistribute and rename XeGPUSgToWiDistributeExperimental to XeGPUSgToLaneDistribute (#198027)

The XeGPUSubgroupDistribute pass is now fully superseded by the newer
subgroup-to-lane distribution flow, so this PR removes its
implementation & all associated tests.
The replacement pass XeGPUSgToWiDistributeExperimental is renamed to
XeGPUSgToLaneDistribute.
DeltaFile
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+1,932-0mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
+0-1,929mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
+1,322-0mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
+0-1,322mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+0-1,271mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
+3,254-6,80211 files not shown
+3,772-7,94517 files

LLVM/project 6b17cf8llvm/lib/Target/RISCV RISCVInstrInfoP.td RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll rvp-simd-32.ll

[RISCV][P-ext] Support packed SSHLSAT with non-constant splat shift amount. (#198937)

We can use the pssha instructions. These instructions look at the lower
8-bits of the shift amount and treat positive values as a left shift and
a negative value as a right shift.

Since out of bound shift amounts for SSHLSAT are poison, we can directly
pass the shift amount to the instruction.
DeltaFile
+4-35llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+22-5llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+5-14llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1-10llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+32-644 files

LLVM/project 52aac75llvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.cpp

[RISCV][GISel] Use sXLen member variable instead of creating it locally. NFC (#199594)
DeltaFile
+9-10llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+9-101 files

LLVM/project bd9ce0aclang/include/clang/StaticAnalyzer/Checkers Checkers.td

[clang][analyzer] Make CallAndMessage:ArgPointeeInitializedness released (NFC) (#199184)

The option was in `InAlpha` state but should be `Released` instead. It
was improved in changes #164600 and #173854.
DeltaFile
+1-1clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
+1-11 files

LLVM/project 4af6b1ellvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU global-saddr-load.ll

PR feedback, fix tests
DeltaFile
+24-90llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+12-14llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+36-1042 files

LLVM/project 088dd28llvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel load-d16.ll

[AMDGPU][True16] Add regbank combiner cases to fix regression around G_SEXTLOAD
DeltaFile
+63-165llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
+17-2llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+80-1672 files

LLVM/project 27c6a86llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp

Refactor comment, make explicit legalizer rules for True16
DeltaFile
+18-18llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+18-181 files

LLVM/project 6aaebe6llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp

Update comment around destination reg size for clarity
DeltaFile
+5-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+5-11 files

LLVM/project ab1b590llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU global-saddr-load.ll

Add legalize rules and fix tests
DeltaFile
+165-63llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
+90-24llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+6-9llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-s16-true16.mir
+7-2llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+268-984 files

LLVM/project 00f190cllvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU flat-saddr-load.ll

[AMDGPU][True16] Legalize extloads into 16-bit registers

Signed-off-by: Domenic Nutile <domenic.nutile at gmail.com>
DeltaFile
+80-38llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+2-2llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+82-402 files

LLVM/project 08d72a0llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp

AMDGPU/GlobalISel: Move executeInWaterfallLoop call from lower

WFI is an argument to applyMappingSrc and lower,
move executeInWaterfallLoop after these two return.
Also set insert point in executeInWaterfallLoop to
avoid need to set insert point before calling it.
DeltaFile
+6-5llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+6-51 files

LLVM/project c420a22llvm/include/llvm/Analysis TargetTransformInfo.h TargetTransformInfoImpl.h, llvm/lib/Analysis TargetTransformInfo.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+32-22llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
+9-0llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+6-0llvm/include/llvm/Analysis/TargetTransformInfo.h
+4-0llvm/lib/Analysis/TargetTransformInfo.cpp
+2-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-0llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+55-231 files not shown
+56-237 files

LLVM/project 721cddfllvm/test/Transforms/SLPVectorizer/AMDGPU inst-count-heuristic.ll

[SLP][NFC]Add a test with inst count heuristic for AMDHSA, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/199693
DeltaFile
+144-0llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
+144-01 files

LLVM/project e8d5037clang/test/ASTMerge/class-template-spec test.cpp, clang/test/ASTMerge/class-template-spec/Inputs class-template-spec.cpp

[clang] NFC: readd test cases reverted in 79f4d8f014 (#199676)

This adds back the test cases reverted in 79f4d8f014

We need some sort of process to stop losing regression tests due to
reverts...
DeltaFile
+110-0clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
+47-0clang/test/ASTMerge/class-template-spec/Inputs/class-template-spec.cpp
+8-0clang/test/ASTMerge/class-template-spec/test.cpp
+165-03 files

LLVM/project 3a25f7bclang/lib/AST Decl.cpp DeclCXX.cpp, clang/lib/Sema SemaLookup.cpp

[clang] preserve exact redeclaration for getTemplateInstantiationPattern (#199473)

This makes these functions not always return the definition if any. The
few users which depend on this are updated to fetch the definition
themselves.

Also fixes the VarDecl variant returning the queried declaration itself.
DeltaFile
+7-28clang/lib/AST/Decl.cpp
+9-10clang/test/AST/ast-dump-templates-pattern.cpp
+3-10clang/lib/AST/DeclCXX.cpp
+6-6clang/test/AST/ast-dump-decl.cpp
+6-4clang/lib/Sema/SemaLookup.cpp
+1-1clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
+32-592 files not shown
+34-618 files

LLVM/project 977b460mlir/include/mlir/IR BuiltinOps.td

drop unrealized_conversion_cast change
DeltaFile
+3-3mlir/include/mlir/IR/BuiltinOps.td
+3-31 files

LLVM/project 1f644aamlir/docs Tokens.md LangRef.md

address comments: symbols / IsolatedFromAbove
DeltaFile
+6-1mlir/docs/Tokens.md
+1-2mlir/docs/LangRef.md
+7-32 files

LLVM/project d510483mlir/docs Tokens.md LangRef.md

move structural contract to LangRef
DeltaFile
+20-40mlir/docs/Tokens.md
+27-6mlir/docs/LangRef.md
+47-462 files

LLVM/project 4b84c10mlir/docs Tokens.md

Update mlir/docs/Tokens.md

Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
DeltaFile
+2-1mlir/docs/Tokens.md
+2-11 files

LLVM/project 8f218f9mlir/docs Tokens.md, mlir/docs/Traits _index.md

[mlir][IR] Require token producer and consumer traits

Add marker traits for operations that intentionally produce or consume the
builtin token type. The verifier now rejects token results without
TokenProducerTrait, token operands without TokenConsumerTrait, token entry
block arguments whose parent op does not produce tokens, and token block
arguments outside entry blocks.

Extend the Test dialect token ops to cover valid opt-in cases and each
verifier rejection path.

Assisted-by: Codex
DeltaFile
+100-2mlir/test/IR/token-type.mlir
+93-3mlir/lib/IR/Verifier.cpp
+28-3mlir/test/lib/Dialect/Test/TestOps.td
+14-7mlir/docs/Tokens.md
+14-0mlir/docs/Traits/_index.md
+12-0mlir/include/mlir/IR/OpDefinition.h
+261-152 files not shown
+268-168 files

LLVM/project b917cfdmlir/docs Tokens.md

address comments
DeltaFile
+2-3mlir/docs/Tokens.md
+2-31 files

LLVM/project 63fea96mlir/test/Dialect/Builtin/Bytecode builtin_fixed_0.mlirbc

regenerate bytecode
DeltaFile
+0-0mlir/test/Dialect/Builtin/Bytecode/builtin_fixed_0.mlirbc
+0-01 files

LLVM/project 3f01feamlir/include/mlir/Dialect/LLVMIR LLVMIntrinsicOps.td LLVMOps.td, mlir/lib/Dialect/LLVMIR/IR LLVMTypeSyntax.cpp LLVMTypes.cpp

remove LLVM token type
DeltaFile
+23-37mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
+15-10mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
+11-11mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
+9-9mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+7-7mlir/test/Target/LLVMIR/Import/intrinsic.ll
+6-7mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+71-8112 files not shown
+94-10918 files

LLVM/project 2f3be65mlir/docs/Dialects LLVM.md, mlir/lib/IR Verifier.cpp

address comments
DeltaFile
+5-9mlir/lib/IR/Verifier.cpp
+1-2mlir/docs/Dialects/LLVM.md
+6-112 files

LLVM/project 9e80f60mlir/docs Tokens.md

call out IsolatedFromAbove restriction
DeltaFile
+4-0mlir/docs/Tokens.md
+4-01 files