LLVM/project 627d682mlir/include/mlir/Interfaces ControlFlowInterfaces.td, mlir/lib/Dialect/SCF/IR SCF.cpp

[mlir][draft] Consolidate patterns into RegionBranchOpInterface patterns

fix some tests
DeltaFile
+267-927mlir/lib/Dialect/SCF/IR/SCF.cpp
+39-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+17-17mlir/test/Dialect/SparseTensor/sparse_out.mlir
+11-13mlir/test/Dialect/SCF/canonicalize.mlir
+8-8mlir/test/Dialect/SparseTensor/sparse_kernels.mlir
+9-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+351-9654 files not shown
+364-97510 files

LLVM/project d75889bllvm/test/CodeGen/AArch64 sme-framelower-use-bp.ll, llvm/test/CodeGen/X86 pr162812.ll

rebase

Created using spr 1.3.7
DeltaFile
+28-742llvm/test/CodeGen/AArch64/sme-framelower-use-bp.ll
+755-5llvm/test/CodeGen/X86/pr162812.ll
+315-314llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+547-0llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-matmul.ll
+510-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll
+503-0llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll
+2,658-1,061487 files not shown
+14,499-4,665493 files

LLVM/project 1415e2bllvm/utils/TableGen DAGISelMatcherEmitter.cpp DAGISelMatcherGen.cpp, llvm/utils/TableGen/Common DAGISelMatcher.h DAGISelMatcher.cpp

[TableGen] Merge EmitIntegerMatcher and EmitStringIntegerMatcher. NFC (#173940)

Allow an EmitIntegerMatcher to have an optional string value to make
it equivalent to EmitStringIntegerMatcher.
DeltaFile
+14-33llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+8-34llvm/utils/TableGen/Common/DAGISelMatcher.h
+4-4llvm/utils/TableGen/DAGISelMatcherGen.cpp
+0-5llvm/utils/TableGen/Common/DAGISelMatcher.cpp
+26-764 files

LLVM/project cb6c195mlir/lib/Pass PassCrashRecovery.cpp, mlir/lib/Tools/mlir-opt MlirOptMain.cpp

[mlir][Pass] Fix textual pipeline specification when generating a crashless reproducer (#173750)

Crashless reproducers currently emit an extra anchor op in the pipeline
they print out, because one gets added by `appendReproducer`. Fix this
by always adding the anchor op in the caller of `appendReproducer`.

In addition, `mlir-opt` always uses `any` as the anchor op, instead of
getting the anchor op from the `PassManager`, fix that as well so we can
test that the pipeline is reproduced as it was passed in.
DeltaFile
+7-6mlir/lib/Pass/PassCrashRecovery.cpp
+1-1mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
+1-1mlir/test/Pass/crashless-reproducer.mlir
+9-83 files

LLVM/project fe0f366flang/lib/Optimizer/Transforms SimplifyFIROperations.cpp, flang/test/Transforms do_concurrent-to-do_loop-unodered.fir

[flang] Fixed hoisting order in fir.do_concurrent simplification. (#174044)

The order has to be fixed after #173502. This results in
reversing the order of `fir.alloca`, but that should be
insignificant.
DeltaFile
+43-2flang/test/Transforms/do_concurrent-to-do_loop-unodered.fir
+1-1flang/lib/Optimizer/Transforms/SimplifyFIROperations.cpp
+44-32 files

LLVM/project f0408c7.github/workflows llvm-abi-tests.yml libclang-abi-tests.yml, .github/workflows/upload-release-artifact action.yml

[Github] Update GitHub Artifact Actions (major) (#173805)

This PR contains the following updates:

| Package | Type | Update | Change |
|---|---|---|---|
|
[actions/download-artifact](https://redirect.github.com/actions/download-artifact)
| action | major | `v6.0.0` → `v7.0.0` |
|
[actions/upload-artifact](https://redirect.github.com/actions/upload-artifact)
| action | major | `v5.0.0` → `v6.0.0` |
|
[actions/upload-artifact](https://redirect.github.com/actions/upload-artifact)
| action | major | `5.0.0` → `6.0.0` |
DeltaFile
+6-6.github/workflows/llvm-abi-tests.yml
+4-4.github/workflows/libclang-abi-tests.yml
+4-4.github/workflows/premerge.yaml
+4-4.github/workflows/libcxx-build-and-test.yaml
+2-2.github/workflows/upload-release-artifact/action.yml
+2-2.github/workflows/build-ci-container-windows.yml
+22-2214 files not shown
+37-3720 files

LLVM/project 23bf786flang/test/Driver pass-plugin-not-found.f90 pass-plugin.f90, flang/test/Examples feature-list-class.f90 feature-list-functions.f90

[flang] Remove REQUIRES: shell lines form tests (#173339)

The shell feature only implies that we are not running on Windows now
that the internal shell feature is available everywhere. Replace it with
UNSUPPORTED: system-windows on non-portable tests so we can eventually
get rid of the feature.
DeltaFile
+1-1flang/test/Driver/pass-plugin-not-found.f90
+1-1flang/test/Driver/pass-plugin.f90
+1-1flang/test/Driver/plugin-invalid-name.f90
+1-1flang/test/Examples/feature-list-class.f90
+1-1flang/test/Examples/feature-list-functions.f90
+1-1flang/test/Examples/omp-atomic.f90
+6-69 files not shown
+15-1515 files

LLVM/project 3eef4f5llvm/utils/TableGen/Common CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h

[TableGen] Remove unused pattern rewriting functionality from CodeGenDAGPatterns. NFC (#174032)

This was originally added for GlobalISel and has been unused since
f84bc3793e9d1ba170a35b1909dd1057b63c2f15, 7.5 years ago.
DeltaFile
+2-7llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+1-7llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+3-142 files

LLVM/project 95656f0llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-shufflevector.ll

InstCombine: Rudimentary support of shufflevector in SimplifyDemandedFPClass

This should look more like the computeKnownFPClass handling, with knowledge
of demanded vector elements.
DeltaFile
+269-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-shufflevector.ll
+11-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+280-02 files

LLVM/project 7050ca2llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-insertelement.ll

InstCombine: Basic insertelement support for SimplifyDemandedFPClass

Eventually this should pull up the known elements logic from
computeKnownFPClass.
DeltaFile
+187-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-insertelement.ll
+10-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+197-02 files

LLVM/project 984582ellvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Fix defining undef constant vector elts in SimplifyDemandedFPClass

Fold constants of known single class to the original constant instead of
a new constant. This avoids overdefining vector elements that were originally
undefined with the splat constant.
DeltaFile
+29-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+12-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+41-22 files

LLVM/project 775251allvm/include/llvm/CodeGen SelectionDAGISel.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGISel.cpp

[SelectionDAG] Remove OPC_EmitStringInteger from isel. (#173936)

Instead emit this as an OPC_EmitInteger, but print the string
when the value is known to be 0..63 (when we don't need a VBR).
Also print the string into a comment when comments are not omitted
so it isn't lost when a VBR is needed.
DeltaFile
+7-22llvm/utils/TableGen/DAGISelMatcherGen.cpp
+17-11llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+4-13llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+8-4llvm/utils/TableGen/Common/DAGISelMatcher.h
+2-2llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+0-3llvm/include/llvm/CodeGen/SelectionDAGISel.h
+38-551 files not shown
+39-567 files

LLVM/project 2541b18llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 xor-with-zero-and-incompat.ll

[SLP]Mark and incompatible for 'xor %a, 0' operations

Xor with 0 is incompatible with and, which resulst in all zero instead
of %a

https://alive2.llvm.org/ce/z/oEVETS

Fixes #174041
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1-1llvm/test/Transforms/SLPVectorizer/X86/xor-with-zero-and-incompat.ll
+2-22 files

LLVM/project 2c32613mlir/include/mlir/Dialect/SparseTensor/IR SparseTensorOps.td, mlir/test/Dialect/SparseTensor sparse_out.mlir sparse_kernels.mlir

fix some tests
DeltaFile
+17-17mlir/test/Dialect/SparseTensor/sparse_out.mlir
+8-8mlir/test/Dialect/SparseTensor/sparse_kernels.mlir
+4-4mlir/test/Transforms/remove-dead-values.mlir
+4-3mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
+3-3mlir/test/Dialect/Vector/vector-warp-distribute.mlir
+36-355 files

LLVM/project a53dbe2mlir/lib/Dialect/MemRef/IR MemRefOps.cpp, mlir/test/Dialect/MemRef canonicalize.mlir

[mlir] Fold memref.cast static-to-dynamic to memref.expand_shape (#170037)

memref.expand_shape didn't have memref.cast op folder. Added
canonicalization pattern to allow folding of memref.cast from static to
dynamic.

Example:

```mlir
  %0 = memref.cast %arg0 : memref<8x4xf32> to memref<?x4xf32>
  %c0 = arith.constant 0 : index
  %dim0 = memref.dim %0, %c0 : memref<?x4xf32>
  %1 = memref.expand_shape %0 [[0, 1], [2]] output_shape [%dim0, 1, 4]  : memref<?x4xf32> into memref<?x1x4xf32>
```

is converted to:

```mlir
  %expand_shape = memref.expand_shape %arg0 [[0, 1], [2]] output_shape [8, 1, 4] : memref<8x4xf32> into memref<8x1x4xf32>

    [2 lines not shown]
DeltaFile
+138-0mlir/test/Dialect/MemRef/canonicalize.mlir
+67-1mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
+205-12 files

LLVM/project a980baallvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-shufflevector.ll

InstCombine: Rudimentary support of shufflevector in SimplifyDemandedFPClass

This should look more like the computeKnownFPClass handling, with knowledge
of demanded vector elements.
DeltaFile
+269-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-shufflevector.ll
+11-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+280-02 files

LLVM/project e70906cmlir/include/mlir/Dialect/SparseTensor/IR SparseTensorOps.td, mlir/test/Dialect/Vector vector-warp-distribute.mlir

fix some tests
DeltaFile
+4-4mlir/test/Transforms/remove-dead-values.mlir
+4-3mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
+3-3mlir/test/Dialect/Vector/vector-warp-distribute.mlir
+11-103 files

LLVM/project 447cademlir/include/mlir/Dialect/SparseTensor/IR SparseTensorOps.td, mlir/test/Dialect/Vector vector-warp-distribute.mlir

fix some tests
DeltaFile
+4-3mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
+3-3mlir/test/Dialect/Vector/vector-warp-distribute.mlir
+7-62 files

LLVM/project fd1d31dllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-insertelement.ll

InstCombine: Basic insertelement support for SimplifyDemandedFPClass

Eventually this should pull up the known elements logic from
computeKnownFPClass.
DeltaFile
+187-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-insertelement.ll
+11-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+198-02 files

LLVM/project 3e93d9allvm/test/tools/llvm-mca/AArch64 mcpu-help.test, llvm/tools/llvm-mca llvm-mca.cpp

Revert -mcpu fix (#174093)

Reverts #173399 and #174004.

#173399 moved MemoryBuffer::getFileOrSTDIN below the -mcpu validation to
fix the `-mcpu=help` flag , but on cross builds the first CPU is
rejected before the “file not found” diagnostic is printed. This failed
lit tests. #174004 introduced a host CPU fallback to fix the cross
compilation issue, but this still fails on NVPTX builders.

This can be revisited when a fix is found that works with the NVPTX
builders.
DeltaFile
+15-46llvm/tools/llvm-mca/llvm-mca.cpp
+0-11llvm/test/tools/llvm-mca/AArch64/mcpu-help.test
+15-572 files

LLVM/project 3dbfd13llvm/test/Transforms/SLPVectorizer/X86 xor-with-zero-and-incompat.ll

[SLP][NFC]Add a test with the incorrect xor to and transformation
DeltaFile
+19-0llvm/test/Transforms/SLPVectorizer/X86/xor-with-zero-and-incompat.ll
+19-01 files

LLVM/project bc128f3clang/test/Headers __clang_hip_math.hip, llvm/lib/IR Instructions.cpp

drop reapplying ir change

This reverts commit e4a0e0a13593d1cc0f79900c5e61a1848a1a0ee8.
DeltaFile
+88-81llvm/test/Transforms/DFAJumpThreading/dfa-unfold-select.ll
+22-22clang/test/Headers/__clang_hip_math.hip
+24-17llvm/lib/IR/Instructions.cpp
+18-18llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
+17-15llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
+12-12llvm/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
+181-16567 files not shown
+343-31673 files

LLVM/project a3fec0ellvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Fix defining undef constant vector elts in SimplifyDemandedFPClass

Fold constants of known single class to the original constant instead of
a new constant. This avoids overdefining vector elements that were originally
undefined with the splat constant.
DeltaFile
+29-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+12-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+41-22 files

LLVM/project 96df108llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-extractelement.ll

InstCombine: Handle extractelement in SimplifyDemandedFPClass (#174081)

A lot of boilerplate changes are necessary to do proper elementwise
tracking like SimplifyDemandedBits
DeltaFile
+120-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-extractelement.ll
+6-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+126-02 files

LLVM/project ff2d758llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-exp.ll

InstCombine: Preserve flags when simplifying exp (#174078)

DeltaFile
+21-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll
+12-7llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+33-72 files

LLVM/project 8031481mlir/lib/Dialect/Arith/Transforms IntRangeOptimizations.cpp, mlir/test/Dialect/Arith int-range-narrowing.mlir

[mlir][int-range] `IntRangeNarrowingPass` was missing `SparseConstantPropagation` analysis (#174088)

This was causing it to skip nested scf ops in some cases (see `scf.for`
test). Use convenience `loadBaselineAnalyses` func.
DeltaFile
+30-0mlir/test/Dialect/Arith/int-range-narrowing.mlir
+3-3mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
+33-32 files

LLVM/project 22f2ae1llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[AMDGPU][NPM] Complete fast regalloc pipeline
DeltaFile
+38-0llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-1llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+39-12 files

LLVM/project da0a853mlir/include/mlir/Interfaces ControlFlowInterfaces.td ControlFlowInterfaces.h, mlir/lib/Dialect/SCF/IR SCF.cpp

[mlir][draft] Consolidate patterns into RegionBranchOpInterface patterns
DeltaFile
+195-727mlir/lib/Dialect/SCF/IR/SCF.cpp
+39-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+5-7mlir/test/Dialect/SCF/canonicalize.mlir
+9-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+2-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+250-7345 files

LLVM/project 28a5690clang/lib/Headers amxavx512intrin.h, clang/test/CodeGen/X86 amxavx512-builtins.c

[X86][AMX-AVX512] Add *i intrinsics for immediate variants (#173545)

The immediate variants use the low 6-bit as row index, while register
variants use low 16-bit. We cannot select the immediate variants using
the same intrinsic. So let's add new intrinsics for them.
DeltaFile
+214-0clang/lib/Headers/amxavx512intrin.h
+36-0clang/test/CodeGen/X86/amxavx512-builtins.c
+9-9llvm/lib/Target/X86/X86InstrAMX.td
+18-0llvm/include/llvm/IR/IntrinsicsX86.td
+16-0llvm/lib/Target/X86/X86InstrOperands.td
+15-0llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+308-96 files not shown
+353-1512 files

LLVM/project 5c2a811clang/docs ReleaseNotes.rst, clang/lib/Sema SemaDecl.cpp

[clang] Preserve the initializer when variable declaration deduction fails (#173546)

Fix https://github.com/clangd/clangd/issues/2572.
DeltaFile
+8-1clang/lib/Sema/SemaDecl.cpp
+8-0clang/test/AST/ast-dump-recovery.cpp
+1-0clang/docs/ReleaseNotes.rst
+17-13 files