[AArch64][PAC] Reset `killed` operand flags in outlined functions
Presently, MachineOutliner does not take `killed` operand flags into
account when merging instruction sequences. While it sounds perfectly
reasonable not to inhibit merging of the instruction sequences that
only differ in `killed` flags (for N flags there is technically 2^N
valid ways to drop some subset of them), copying these flags from
an arbitrarily chosen representative instruction may result in
incorrect codegen of PAuth-related pseudo instructions on AArch64.
To keep `killed` flags conservatively correct as if `OUTLINED_FUNCTION`s
are virtually re-inserted at every call site, this patch takes the
simplest approach of resetting every `killed` flag inside the
outlined functions.
[ConstantFolding] Use getGetElementPtr() overload accepting DataLayout (#226104)
To directly create the constant GEP in canonical form. The practical
effect is that we a) canonicalize vector GEPs and b) decline to
create a GEP which can't be represented in ptradd form (in the
constant_fold_custom_dl test due to a non-canonical index type).
CodeGen: Move Generic sjlj test to Transforms
Test the IR-only SjLjEHPrepare pass in the dedicated pass test
directory. Also add the module flag so it is really triple
independent.
[flang][cuda] Share the managed companion pointer across translation units (#225710)
A non-allocatable managed module variable is accessed through a
companion pointer in the `__nv_managed_data__` section, which the CUDA
runtime fills in with the unified memory address at module
initialization. Every translation unit referencing the variable emitted
its own internal pointer and registered it. The runtime populates only
the registration performed first for a given variable name (*), so every
other unit was left loading through a null pointer and crashed at run
time.
Emit a single pointer with external linkage instead. The unit defining
the variable emits the definition, zero-initialized and in
`__nv_managed_data__`, and registers it; a unit that only USEs the
variable emits a declaration and no registration, resolving to that
definition at link time.
(*) I verified this using the following reproducer:
[31 lines not shown]
[X86] Prepare bdver tests for TuningPrefer128Bit (#226103)
Ensure the check prefixes correctly handle XOP targets independently,
I've also reordered some of the tests so we can cleanly order the
eventual AVX128/AVX256/AVX512 checks
Help reduce the diff for #225838
[RISCV] Remove getMaxLMULForFixedLengthVectors. NFC
The value can no longer be overridden after https://github.com/llvm/llvm-project/pull/207312. Now there's nothing specific about it to fixed vectors, so just inline it.
[clang][AArch64] Consolidate codegen tests for SVE's DUP intrinsics (#223933)
This patch completes the migration of the tests from:
* clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dup.c
to:
* clang/test/CodeGen/AArch64/sve/dup.c
`dup.c` covers all the cases previously tested by `acle_sve_dup.c`.
However, unlike `acle_sve_dup.c`, it was only tested as C. Add `-x c++`
RUN lines to provide the equivalent C++ coverage, including lowering
via CIR.
AMDGPU: Invalidate VCC live ranges when lowering kill instructions (#226040)
lowerKillInstr replaces the kill pseudo with a v_cmp defining VCC plus
two instructions reading it, but left any previously computed VCC
regunit ranges alone. If something had already materialized them, the
new uses have no live segment:
*** Bad machine code: No live segment at use ***
- instruction: $exec = S_ANDN2_B64_term $exec, $vcc, implicit-def $scc
Drop the ranges so they are recomputed on demand, as is already done for
EXEC and SCC.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
[SanitizerCoverage] Directly create ptradd constant expression (NFC) (#226107)
Don't go through an IRBuilder without insertion point for a case
that always creates a constant expression.
CodeGen: Derive ARM EH pointer/selector registers from MCAsmInfo
Whether the exception pointer and selector are delivered in registers is an
object-format property, not a program-state one. ARM was the only target to
consult the exception model here, to test for SjLj EH, and that is a constant
for the triple already recorded in MCAsmInfo. Read it from there and drop the
ExceptionHandling argument that was threaded through
getExceptionPointerRegister and getExceptionSelectorRegister.
This is the effective revert of fdc178994aa7.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[llvm] Update tests to use struct path TBAA (#226051)
The new format was introduced more than a decade ago, so make sure it's
used in tests. The tests currently get away with it due to a TBAA
upgrade applied in the IR parser.
Disclosure: AI-generated change.
[AArch64][GlobalISel] Improve fixed-point int-to-fp selection (#224055)
Select scalar fixed-point integer-to-float conversions directly in
GlobalISel when their integer operand is already in the FPR bank. Teach
the fixed-point immediate matcher about reciprocal constants. Refine
register-bank selection for scalar conversion intrinsics.
[mlir][ODS] Share parser operand storage cleanup (NFC) (#226094)
Group variable-length operand vectors in generated parsers and move
their construction and cleanup into a shared storage template. This
reduces repeated cleanup code in parsers with many optional operand
groups.
Assisted-by: Codex
[flang][cuda] Share the managed companion pointer across translation units
A non-allocatable managed module variable is accessed through a companion
pointer in the `__nv_managed_data__` section, which the CUDA runtime fills in
with the unified memory address at module initialization. Every translation
unit referencing the variable emitted its own internal pointer and registered
it. The runtime populates only the registration performed first for a given
variable name (*), so every other unit was left loading through a null pointer and
crashed at run time.
Emit a single pointer with external linkage instead. The unit defining the
variable emits the definition, zero-initialized and in __nv_managed_data__,
and registers it; a unit that only USEs the variable emits a declaration and
no registration, resolving to that definition at link time.
(*) I verified this using the following reproducer:
`exp_mod.f90`:
```fortran
[31 lines not shown]
[orc-rt] Add DWARFEHFrameRegistrar for .eh_frame registration. (#226093)
Adds sys::posix::DWARFEHFrameRegistrar, which registers JIT'd .eh_frame
sections, and expose it to controllers via the
orc_rt_ci_aa_sps_DWARFEHFrameRegistrar_registerSection and
orc_rt_ci_aa_sps_DWARFEHFrameRegistrar_deregisterSection allocation
actions.
The interface is added to the controller interface on Linux only; on
Darwin, StandaloneMachOUnwindInfoRegistrar is preferred.
[TableGen][AMDGPU] Introduce register sequences
The overwhelming majority of AMDGPU's registers are synthesized
tuples, and all of them are sequences of adjacent registers of
certain widths. We currently have no adequate representation of
them in TableGen: every such tuple is emitted as a descriptor
carrying its own name string and its own sub- and super-register
lists, so the generated register tables run to well over a
hundred megabytes for this one target. The names spell out every
member, so a four-register tuple is SGPR0_SGPR1_SGPR2_SGPR3.
Describing such tuples by their first and last registers alone
would address these issues. What stands in the way is that
TableGen has no notion of one register following another in a
sequence.
This patch adds such a notion using RegisterSequence instances:
def : RegisterSequence<[R0, R1, R2, R3]>;
[29 lines not shown]
[CIR][OpenMP] Implement lowering for the 'if' clause for 'parallel' d… (#204999)
Implementing the lowering of the `if` clause for the `#pragma omp
parallel` directive. The clause simply accepts the condition from
`OMPIfClause` and lowers it to an `I1` to allow for emission.
Followed the same approach as the one in my other PR #202466 and based
myself off of PR #172501 that implements the lowering for the
`proc_bind` clause.
### Evidence:
Output of: `python3 build/bin/llvm-lit -sv
clang/test/CIR/CodeGenOpenMP/parallel.c`
```
llvm-lit: /home/pedro/dev/projects/my-llvm-project/llvm/utils/lit/lit/llvm/config.py:569: note: using clang: /home/pedro/dev/projects/my-llvm-project/build/bin/clang
Testing Time: 0.10s
[2 lines not shown]
Revert "[LLDB] Simplify Makefile for TestBundleWithDotInFilename" (#226092)
Reverts llvm/llvm-project#225930
This breaks the Green Dragon bot. Reverting for now.
M68k: Use data register classes for the 16->32 extending move pseudos
MOVSXd32d16 and MOVZXd32d16 declared both operands with the XR32/XR16
classes, which include the address registers. The post-RA expansion of
these pseudos emits AND32di, MOV16dd and EXT32, all of which require a
data register, so allocating an address register produces invalid code:
$a6 = AND32di $a6(tied-def 0), 65535, implicit-def $ccr
Every pattern selecting these pseudos already restricts the source to
MxDRD16, so constrain the pseudos to the data register classes.
This fixes machine verifier errors in the touched test.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
[Mips][GlobalISel] Fix Big Endian lowering (#225972)
Flip on the big-endian switch in Mips call lowering. Fix split memory
piece placement, short-load bit extraction, and unaligned left/right
instruction offsets for big-endian targets.
Add BE/LE test coverage.
[flang] Lower loops whose branching is confined to their body structurally
Such a loop was classified separately by a previous change but still
lowered as a raw CFG, so its structured form was lost.
Lower it structurally instead, with its body folded into a region that can
hold the branching. The loop keeps its bounds on the op, so it remains
available to whatever transforms or parallelizes it. Only the body is
folded: the loop control statements are emitted as they are for any
structured loop, since a branch from outside may target either of them.
Loops an OpenACC or OpenMP directive owns are lowered the same way, so
they keep their form too.
[flang] Resolve an assigned GO TO's targets from the completed assign map
An assigned GO TO reaches any label ASSIGNed to its variable, and a label
list does not bound that: lowering allows a branch to any ASSIGNed label
whether or not the list names it. Branch analysis only sees the ASSIGNs
preceding the GO TO in program order, so the successors it records, and the
incoming branches derived from them, can be incomplete.
The symbol-to-labels map is complete once branch analysis has finished,
which is when the classification runs. Ask it for the full target set
instead of trusting the recorded successors, so a loop whose assigned GO TO
stays within its body is still recognised.
[AMDGPU] Simplify true16 SGPR folding (#226082)
Rewrite part of the SGPR folding "hack" from #128929 using
getChannelFromSubReg to avoid relying on the exact numbering of subreg
indices.
This also fixes a potential bug when folding a copy with no subreg on
the source operand like `%1:sgpr_lo16 = COPY %0:sgpr_lo16`. The old
implementation would have generated `%0.sub0:sgpr_lo16` which fails
machine verification.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
