LLVM/project b27d9d2llvm/tools/llvm-jitlink/llvm-jitlink-executor llvm-jitlink-executor.cpp

[llvm-jitlink] Fix a memory leak in llvm-jitlink-executor. (#223904)

In openListener, use a scope_exit to call freeaddrinfo on the struct
allocated by getaddrinfo.

No testcase: We have no in-tree tests for llvm-jitlink-executor. This
bug was found by inspection.
DeltaFile
+2-0llvm/tools/llvm-jitlink/llvm-jitlink-executor/llvm-jitlink-executor.cpp
+2-01 files

LLVM/project 78bbf22lldb/include/lldb/Host HostInfo.h, lldb/include/lldb/Host/emscripten HostInfoEmscripten.h

[lldb] Add HostInfoEmscripten (#223169)

Emscripten currently selects `HostInfoLinux`. That was useful as an initial bootstrap, but it also introduces Linux-specific assumptions such as `/proc/self/exe`, invoking `lsb_releas`e through `popen`, and
Linux-specific architecture handling.

This patch introduces a small `HostInfoEmscripten` implementation derived from `HostInfoPosix` and selects it when LLDB is built with Emscripten.

The implementation intentionally remains minimal. A browser-hosted LLDB process does not currently have a meaningful native executable path, so `GetProgramFileSpec()` returns an empty FileSpec.

A dedicated PlatformEmscripten and browser-specific process behavior will be handled separately so this change remains atomic !
DeltaFile
+29-0lldb/include/lldb/Host/emscripten/HostInfoEmscripten.h
+17-0lldb/source/Host/emscripten/HostInfoEmscripten.cpp
+4-2lldb/source/Host/CMakeLists.txt
+4-1lldb/include/lldb/Host/HostInfo.h
+54-34 files

LLVM/project df997d2llvm/lib/Target/RISCV RISCVRegisterInfo.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Add DecodeSingleRegister template class to replace DecodeSPRegisterClass and similar. (#223889)

This can avoid adding more explicitly written decode functions for
https://github.com/llvm/llvm-project/pull/177073
DeltaFile
+16-30llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+3-0llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+19-302 files

LLVM/project af0b251llvm/test/Transforms/LoopVectorize/AArch64 early_exit_costs.ll

Fix early_exit_costs.ll test
DeltaFile
+2-2llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
+2-21 files

LLVM/project 7694dc0llvm/test/Transforms/LoopVectorize predicated-early-exits-interleave.ll predicated-multiple-exits.ll

[VPlan] Use frozen combined condition in early exit first-active-lane

Combined is used both to compute if an early exit was taken via VPInstruction::AnyOf, as well as the index of the early-exited lane in VPInstruction::FirstActiveLane.

Combined can have poison lanes past the exited lane, so the AnyOf uses freeze to prevent branching on poison. However FirstActiveLane on a vector with a poison lane is poison, so we need to also use the frozen version of Combined to prevent poison there.
DeltaFile
+32-32llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
+24-24llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
+14-14llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
+12-12llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
+10-10llvm/test/Transforms/LoopVectorize/predicated-multiple-exits.ll
+6-6llvm/test/Transforms/LoopVectorize/predicated-early-exits-interleave.ll
+98-9817 files not shown
+144-14223 files

LLVM/project e5ef5dbllvm/lib/Transforms/Vectorize VPlanConstruction.cpp, llvm/test/Transforms/LoopVectorize single-early-exit-anyof-fold.ll

Remove FIXME
DeltaFile
+3-6llvm/test/Transforms/LoopVectorize/single-early-exit-anyof-fold.ll
+1-1llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+4-72 files

LLVM/project 1a2c10dllvm/test/Transforms/LoopVectorize fmin-without-fast-math-flags.ll epilog-vectorization-fmaxnum-reductions.ll, llvm/test/Transforms/LoopVectorize/AArch64 fmax-without-fast-math-flags.ll

Remove VPInstruction::usesFirstLaneOnly change

InstCombine will canonicalize this anyway https://godbolt.org/z/r7PsGxh6G
DeltaFile
+66-29llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
+51-24llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
+43-20llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
+42-20llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
+33-15llvm/test/Transforms/LoopVectorize/epilog-vectorization-fmaxnum-reductions.ll
+22-10llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
+257-1183 files not shown
+290-1409 files

LLVM/project f7a2602llvm/test/Transforms/LoopVectorize single-early-exit-anyof-fold.ll

Precommit test
DeltaFile
+54-0llvm/test/Transforms/LoopVectorize/single-early-exit-anyof-fold.ll
+54-01 files

LLVM/project c6daf9dllvm/lib/Transforms/Vectorize VPlan.h VPlanTransforms.cpp

Update comments
DeltaFile
+2-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-1llvm/lib/Transforms/Vectorize/VPlan.h
+3-22 files

LLVM/project 416183cllvm/test/Transforms/LoopVectorize fcmp-uno-fold-interleave.ll, llvm/test/Transforms/LoopVectorize/AArch64 fmax-without-fast-math-flags.ll cmp_cost.ll

[VPlan] Fix VPInstruction::AnyOf combine undoing freeze

There is an any-of combine for unrolled VPlans which does:

    any-of (fcmp uno A, A), (fcmp uno B, B), ...-> any-of (fcmp uno A, B)

However any-of implicitly freezes each individual operand and this means we go from `freeze (fcmp uno A, A)` to `freeze (fcmp uno A, B)` which isn't sound: alive2.llvm.org/ce/z/UdQM7C

This causes miscompiles today with early exit loops, see the attached test case in single-early-exit-anyof-fold.ll.

This fixes it by explicitly modelling the freeze in VPlan. There are three places where we use AnyOf:

1) early exit loops: the freeze needs to be applied per-lane, so apply it to `(any-of (freeze (combined-conds-to-exit)))`
2) handleMaxMinNumReductions: If any lane of the reduction was poison in the scalar loop, the final result will be poison. We only need to freeze the result of AnyOf to prevent immediate UB when branching. Freezing individual operands blocks the any-of combine otherwise.
3) handleFindLastReductions: we need to freeze Cond itself since it's got multiple uses, but I plan on fixing this in a separate PR
DeltaFile
+51-48llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
+32-36llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
+35-31llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
+28-32llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
+31-27llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
+30-27llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+207-20120 files not shown
+380-35426 files

LLVM/project f33740cllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize tail_fold_uncountable_exits.ll early_exit_with_stores.ll

Don't unwrap the freeze, copy it over in side effect early exit loops
DeltaFile
+27-27llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+12-12llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
+8-8llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
+8-8llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
+6-6llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-2llvm/test/Transforms/LoopVectorize/tail_fold_uncountable_exits.ll
+63-632 files not shown
+67-678 files

LLVM/project bf89dd2llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanUtils.cpp

[VPlan] Rename createScalarFreeze -> createFreeze. NFC (#223648)

It works for vector operands too. We can also use it in
preparePlanForMainVectorLoop
DeltaFile
+3-3llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+2-2llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+2-2llvm/lib/Transforms/Vectorize/VPlanLowering.cpp
+1-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+8-94 files

LLVM/project 83066e0llvm/docs NVPTXUsage.md, llvm/include/llvm/IR IntrinsicsNVVM.td

[LLVM][NVPTX] Add async bulk copy global to shared extensions (#222323)

This change adds following things to bulk copy intrinsics.
1. Relaxed memory ordering semantics with a scope argument.
2. Data-validity reporting patterns (introduced in Rubin).
3. 32-bit multicast mask for global to shared::cluster variants
(introduced in Rubin).
4. Ignore out of bound checks for global to shared::cta variants.

Note: MLIR lowering is updated to emit the new intrinsic signatures.
Support for the new features in MLIR will be done in a separate change.
DeltaFile
+166-71llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+169-49llvm/docs/NVPTXUsage.md
+108-108mlir/test/Target/LLVMIR/nvvm/tma_load_cluster_im2col.mlir
+72-72mlir/test/Target/LLVMIR/nvvm/tma_load_cluster_tile.mlir
+112-10llvm/lib/IR/AutoUpgrade.cpp
+73-19llvm/include/llvm/IR/IntrinsicsNVVM.td
+700-32923 files not shown
+1,269-41329 files

LLVM/project c7ddefdllvm/lib/Target/RISCV RISCVFeatures.td, llvm/test/MC/RISCV attribute-arch.s

[MC][RISCV] Make Zve32x a dependency of Zvabd (#223901)

The Zvabd specification defines Zve32x as a dependency. This commit
fixes the dependency problem in MC's implementation.

See:
https://github.com/riscv/integer-vector-absolute-difference/blob/0092c8451bb24b957d8358f261c0535ece88defb/src/unpriv/zvabd.adoc#L26
DeltaFile
+2-1llvm/lib/Target/RISCV/RISCVFeatures.td
+3-0llvm/test/MC/RISCV/attribute-arch.s
+5-12 files

LLVM/project 00fbc3fllvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

Precommit test
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163-01 files

LLVM/project 2443554llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Remove (X && Y) | (X && !Y) -> X combine. NFC

We have smaller combines that can take care of this now that we process recipes in a worklist
DeltaFile
+1-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-81 files

LLVM/project 2595cb9llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]
DeltaFile
+26-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+5-7llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+42-193 files

LLVM/project 6c1d20cllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize iv_outside_user.ll dont-fold-tail-for-divisible-TC.ll

[VPlan] Process combineRecipes in a worklist (#213899)

This brings combineRecipes further in line with InstCombine, and asides
from unlocking more simplifications it also helps avoid test churn
whenever passes are moved around combineRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification
order as before.
DeltaFile
+74-90llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
+57-0llvm/test/Transforms/LoopVectorize/blend-i1.ll
+25-13llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-8llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+1-2llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+161-1135 files

LLVM/project 8a512d6clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp

[CIR][ABI] Honor abi::ArgInfo::CanBeFlattened in the call-conv lowering
DeltaFile
+8-4clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+8-41 files

LLVM/project 8b66604llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp, llvm/test/MC/RISCV zicfiss-valid.s

[RISCV] Remap mop.rr.7 and mop.r.28 to sspush/sspopchk/ssrdp in the assembler. (#223894)

This makes llvm-mc output match llvm-objdump. And is more consistent
with the InstAliases we use c.mop.
DeltaFile
+30-0llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+9-15llvm/test/MC/RISCV/zicfiss-valid.s
+39-152 files

LLVM/project 262cf39llvm/lib/MC/MCParser MCAsmParser.cpp, llvm/test/MC/AsmParser macro-max-depth.s

[MC] Increase asm-macro-max-nesting-depth default to 100 (#218455)

GNU as accepts assembly we reject at the current default of 20, e.g.
glibc's
`sysdeps/unix/sysv/linux/alpha/rt_sigaction.S`, which nests 31 deep.
Raise the
default to 100, matching GNU as.

Assisted-by: Claude Code
DeltaFile
+13-13llvm/test/MC/AsmParser/macro-max-depth.s
+1-1llvm/lib/MC/MCParser/MCAsmParser.cpp
+14-142 files

LLVM/project 9302119mlir/python/mlir/dialects/linalg __init__.py, mlir/test/python/dialects/linalg ops.py

[mlir][python] Register linalg.ElementwiseOp wrapper as op view

The hand-written ElementwiseOp wrapper subclassed the generated OpView but
was not registered in the op-view registry, so ops reconstructed from the
registry (e.g. Operation.opview) were instances of the generated base class
rather than the publicly exported subclass. This made
isinstance(op.opview, linalg.ElementwiseOp) and match/case dispatch return
False for real linalg.elementwise ops.

Register the wrapper with replace=True (as pdl.py does) so the exported
class is the one the registry instantiates.

Fixes #223673
DeltaFile
+21-0mlir/test/python/dialects/linalg/ops.py
+3-4mlir/python/mlir/dialects/linalg/__init__.py
+24-42 files

LLVM/project 2d7343amlir/test/python/dialects/linalg ops.py

Remove comment per review
DeltaFile
+0-2mlir/test/python/dialects/linalg/ops.py
+0-21 files

LLVM/project c20428cmlir/lib/Dialect/LLVMIR/IR NVVMDialect.cpp, mlir/test/Target/LLVMIR/nvvm mbar_arrive_drop.mlir

[MLIR][NVVM] Fix the lowering of legacy mbar.arrive_drop (#222916)

`nvvm.mbarrier.arrive_drop` fails to compile for sm_80:

LLVM ERROR: Cannot select: intrinsic
%llvm.nvvm.mbarrier.arrive.drop.scope.cta.space.cta

The op always lowers to the `scope.*.space.*` intrinsics, which need
sm_90. The legacy `llvm.nvvm.mbarrier.arrive.drop{,.shared}` intrinsics
work from sm_80 but are never used.

This uses the legacy intrinsic for the basic case only, space=cta,
scope=cta, no relaxed, no explicit count, the same fix as #172476 for
`mbarrier.arrive`. The count forms need sm_90, so they are unchanged.

Assisted-by: Claude
DeltaFile
+15-2mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir
+8-2mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+23-42 files

LLVM/project 4ee9dafllvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Use DecodeFilteredRegisterClass for DecodeGPRX1X5RegisterClass. (#223878)
DeltaFile
+3-11llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+3-111 files

LLVM/project dec17c4flang/lib/Semantics expression.cpp

[flang][cuda] Fix matching distance for use_device and none (#223849)

https://docs.nvidia.com/hpc-sdk/compilers/cuda-fortran-prog-guide/#unified-data
the table set the matching distance for actual `use_device` and dummy
argument `none` to 1 but the implementation set it to 3.

@wangzpgi Was there a specific reason to set 3 instead of 1?
DeltaFile
+2-2flang/lib/Semantics/expression.cpp
+2-21 files

LLVM/project 0454184llvm/test/Transforms/LoopVectorize uniform_across_vf_induction1.ll

Update uniform_across_vf_induction1.ll
DeltaFile
+74-90llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
+74-901 files

LLVM/project fa72130llvm/test/CodeGen/AMDGPU coexec-sched-ds-fifo.mir coexec-scheduler.ll

Fix lit

Change-Id: Id8c3f63acdce212f1030e5dfc7d9273c56945958
DeltaFile
+11-3llvm/test/CodeGen/AMDGPU/ds-latency-mode-flag.mir
+3-3llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
+0-4llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+2-2llvm/test/CodeGen/AMDGPU/coexec-sched-agpr-excess.mir
+1-1llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
+17-135 files

LLVM/project 4150e90llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Call DecodeGPRPairRegisterClass from DecodeGPRPairCRegisterClass. NFC (#223882)

GPRPairC is a subset of GPRPair. We just need to do the range check and
let DecodeGPRPairRegisterClass do the rest of the work.
DeltaFile
+1-8llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+1-81 files

LLVM/project 46f08d7llvm/lib/Target/RISCV RISCVInstrInfoZicfiss.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV] Remove Zicfiss DecoderNamespace. NFC (#223891)

This used to be needed to prioritize c.sspopchk and c.sspush over
c.mop.1 and c.mop.5, but those are treated as InstAliases now.
DeltaFile
+1-2llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+0-2llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+1-42 files