LLVM/project 3383004clang-tools-extra/clang-tidy ClangTidyOptions.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Support comments in WarningsAsErrors (#171816)

Closes #171792

---------

Co-authored-by: Victor Chernyakin <chernyakin.victor.j at outlook.com>
DeltaFile
+31-0clang-tools-extra/unittests/clang-tidy/ClangTidyOptionsTest.cpp
+14-12clang-tools-extra/clang-tidy/ClangTidyOptions.cpp
+3-0clang-tools-extra/docs/ReleaseNotes.rst
+48-123 files

LLVM/project c05a3aclibcxx/include/__filesystem operations.h path.h, libcxx/test/libcxx/diagnostics filesystem.nodiscard.verify.cpp

[libc++][filesystem] Applied `[[nodiscard]]` (#171085)

`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.

- https://libcxx.llvm.org/CodingGuidelines.html
DeltaFile
+440-4libcxx/test/libcxx/diagnostics/filesystem.nodiscard.verify.cpp
+97-62libcxx/include/__filesystem/operations.h
+61-55libcxx/include/__filesystem/path.h
+37-29libcxx/include/__filesystem/directory_entry.h
+7-7libcxx/include/__filesystem/copy_options.h
+7-6libcxx/include/__filesystem/recursive_directory_iterator.h
+649-1639 files not shown
+684-19015 files

LLVM/project 2ca79b2llvm/lib/Support/rpmalloc rpmalloc.c, llvm/test/CodeGen/X86 bitcnt-big-integer.ll shift-i512.ll

fix incorrect output (now tested)

Created using spr 1.3.8-beta.1
DeltaFile
+3,996-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+3,051-413llvm/test/CodeGen/X86/bitcnt-big-integer.ll
+2,852-185llvm/test/CodeGen/X86/shift-i512.ll
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s
+12,239-8,6352,463 files not shown
+81,010-54,4482,469 files

LLVM/project 0d0cd3ellvm/lib/Support/rpmalloc rpmalloc.c, llvm/test/CodeGen/X86 bitcnt-big-integer.ll shift-i512.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+3,996-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+3,051-413llvm/test/CodeGen/X86/bitcnt-big-integer.ll
+2,852-185llvm/test/CodeGen/X86/shift-i512.ll
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
+780-1,347llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s
+12,239-8,6352,461 files not shown
+80,993-54,4392,467 files

LLVM/project 7275817llvm/test/TableGen RegClassByHwMode.td, llvm/utils/TableGen InstrInfoEmitter.cpp AsmMatcherEmitter.cpp

[TableGen] Improve generated comments for RegClassByHwMode tables

Adding a comment for which RegClassByHwMode the entry refers to is
helpful when staring at this generated table.

Pull Request: https://github.com/llvm/llvm-project/pull/171716
DeltaFile
+24-24llvm/test/TableGen/RegClassByHwMode.td
+4-2llvm/utils/TableGen/InstrInfoEmitter.cpp
+3-2llvm/utils/TableGen/AsmMatcherEmitter.cpp
+31-283 files

LLVM/project f0bec9ellvm/lib/Target/RISCV RISCVInstrInfoXCV.td

[RISCV] Use OPERAND_MEMORY as the OperandType for CVrr. NFC (#171967)

DeltaFile
+1-0llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+1-01 files

LLVM/project 618b874llvm/lib/Target/RISCV RISCVInstrInfoXSf.td

[RISCV] Add OperandType to tsimm5 used by Xsfvcp. (#171964)

DeltaFile
+2-1llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+2-11 files

LLVM/project 63ea393libcxx/include optional, libcxx/test/libcxx/utilities/optional nodiscard.verify.cpp

[libc++][optional] Applied `[[nodiscard]]` (#170045)

`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.

- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/optional

---------

Co-authored-by: William Tran-Viet <wtranviet at proton.me>
DeltaFile
+138-0libcxx/test/libcxx/utilities/optional/nodiscard.verify.cpp
+35-34libcxx/include/optional
+10-10libcxx/test/std/utilities/optional/optional.monadic/transform.pass.cpp
+8-8libcxx/test/std/utilities/optional/optional.monadic/and_then.pass.cpp
+4-4libcxx/test/std/utilities/optional/optional.monadic/or_else.pass.cpp
+195-565 files

LLVM/project c3e7a1allvm/test/CodeGen/PowerPC optimize-vector-not-equal.ll

[NFC][PowerPC] Optimize vector compares for not equal to non zero vectors (#171635)

Lockdown instructions for vector compares `not equal to non-zero (Ex:
vec[i]!=7)`. Current implementation can be made better by removing the
negation and using the identity ``` 0XFFFF + 1 = 0 and 0 + 1 = 0 ```

Co-authored-by: himadhith <himadhith.v at ibm.com>
DeltaFile
+74-0llvm/test/CodeGen/PowerPC/optimize-vector-not-equal.ll
+74-01 files

LLVM/project cdfdb06compiler-rt/lib/tsan/go test.c, compiler-rt/lib/tsan/rtl tsan_trace.h

[TSan] Zero-initialize Trace.local_head

Trace.local_head is currently uninitialized when Trace is created. It is
first initialized when the first event is added to the trace, via the
first call to TraceSwitchPartImpl.

However, ThreadContext::OnFinished uses local_head, assuming that it is
initialized. If it has not been initialized, we have undefined behavior,
likely crashing if the contents are garbage. The allocator (Alloc)
reuses previously allocations, so the contents of the uninitialized
memory are arbitrary.

In a C/C++ TSAN binary it is likely very difficult for a thread to start
and exit without a single event inbetween. For Go programs, code running
in the Go runtime itself is not TSan-instrumented, so goroutines that
exclusively run runtime code (such as GC workers) can quite reasonably
have no TSan events.

The addition of such a goroutine to the Go test.c is sufficient to

    [20 lines not shown]
DeltaFile
+4-0compiler-rt/lib/tsan/go/test.c
+1-1compiler-rt/lib/tsan/rtl/tsan_trace.h
+5-12 files

LLVM/project c7ca704flang/docs index.md

[flang][docs] Reorganize the table of contents (#171240)

This patch creates a section for user guidance.
DeltaFile
+16-8flang/docs/index.md
+16-81 files

LLVM/project 1335a05mlir/python/mlir/dialects affine.py, mlir/test/python/dialects affine.py

[MLIR][Python] Fix AffineIfOp insertion point (#171957)

This bug was introduced by #108323, where the loc and ip were not
properly set. It may lead to errors when the operations are not linearly
asserted to the IR.
DeltaFile
+28-0mlir/test/python/dialects/affine.py
+1-1mlir/python/mlir/dialects/affine.py
+29-12 files

LLVM/project ecaf673libcxx/include/__format format_context.h format_parse_context.h, libcxx/test/libcxx/diagnostics format.nodiscard.verify.cpp

[libc++][format] Applied `[[nodiscard]]` to more classes (#170808)

`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.

- https://libcxx.llvm.org/CodingGuidelines.html

Some classes in `<format>` were already annotated. This patch completes
the remaining.
DeltaFile
+23-0libcxx/test/libcxx/diagnostics/format.nodiscard.verify.cpp
+3-3libcxx/include/__format/format_context.h
+2-2libcxx/include/__format/format_parse_context.h
+1-1libcxx/include/__format/format_args.h
+29-64 files

LLVM/project cea9813llvm/lib/Target/RISCV RISCVAsmPrinter.cpp RISCVInstrInfoV.td, llvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.h

[RISCV] Add an OperandType to VMaskOp. NFC (#171926)

Use that instead of register class to detect the mask operand in
lowerRISCVVMachineInstrToMCInst.

There are other instructions like vmerge and vadc that have a VMV0
operand that isn't optional and do not reach this code. Having a
dedicated marker for the optional mask is more precise.
DeltaFile
+2-2llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+2-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+2-0llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+6-23 files

LLVM/project 8deb422llvm/lib/Target/RISCV RISCVInstrInfoVPseudos.td RISCVInstrInfoXAndes.td

[RISCV] Use VMV0 instead of VMaskOp in masked vector pseudoinstructions. NFC (#171924)

VMaskOp primarily exists for parsing/printing in the MC layer where the
mask is optional. The vector pseudos are split into mask and unmasked
versions. The mask is always rquired for the mask version.
DeltaFile
+26-26llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
+27-272 files

LLVM/project 673383allvm/lib/CodeGen WinEHPrepare.cpp

Merge remote-tracking branch 'upstream/users/Enna1/WinEH-removeIncomingValueIf' into users/Enna1/Opt-Phi-removeIncomingValue
DeltaFile
+5-7llvm/lib/CodeGen/WinEHPrepare.cpp
+5-71 files

LLVM/project b8491afllvm/lib/Target/ARM MVEGatherScatterLowering.cpp

Merge remote-tracking branch 'upstream/users/Enna1/MVE-Phi-removeIncomingValue' into users/Enna1/Opt-Phi-removeIncomingValue
DeltaFile
+19-16llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
+19-161 files

LLVM/project 8df0265llvm/lib/Transforms/Utils LoopRotationUtils.cpp

Merge remote-tracking branch 'zjt/remove_incomming_value_loop_rotation' into users/Enna1/Opt-Phi-removeIncomingValue
DeltaFile
+1-1llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
+1-11 files

LLVM/project a7784c4llvm/lib/Transforms/Utils CodeExtractor.cpp

Merge remote-tracking branch 'zjt/remove_incomming_value_code_extractor' into users/Enna1/Opt-Phi-removeIncomingValue
DeltaFile
+1-1llvm/lib/Transforms/Utils/CodeExtractor.cpp
+1-11 files

LLVM/project d7f9dd0llvm/lib/Transforms/Utils CloneFunction.cpp

Merge remote-tracking branch 'zjt/remove_incomming_value_clone_function' into users/Enna1/Opt-Phi-removeIncomingValue
DeltaFile
+4-5llvm/lib/Transforms/Utils/CloneFunction.cpp
+4-51 files

LLVM/project deb8969llvm/test/Transforms/DFAJumpThreading dfa-jump-threading-transform.ll

update llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
DeltaFile
+8-10llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
+8-101 files

LLVM/project 1d5fa2bllvm/lib/IR Instructions.cpp, llvm/test/Transforms/LoopUnroll runtime-loop-multiple-exits.ll

[IR] Optimzie `PHINode::removeIncomingValue()` by swapping with the last of incoming value.

Add an optional argument `KeepIncomingOrder` defaults true, when `KeepIncomingOrder` is true,
the new implementation simply moves the last incoming value and block into the position of the element being removed.

This improve compile-time for PHI nodes with many predecessors.
DeltaFile
+18-18llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
+12-12llvm/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
+13-9llvm/lib/IR/Instructions.cpp
+11-11llvm/test/Transforms/PGOProfile/chr.ll
+10-10llvm/test/Transforms/SimpleLoopUnswitch/inject-invariant-conditions.ll
+10-10llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
+74-7057 files not shown
+173-16663 files

LLVM/project 5dfa72fllvm/test/Transforms/DFAJumpThreading dfa-unfold-select.ll

update llvm/test/Transforms/DFAJumpThreading/dfa-unfold-select.ll
DeltaFile
+77-84llvm/test/Transforms/DFAJumpThreading/dfa-unfold-select.ll
+77-841 files

LLVM/project 88ef263llvm/lib/Transforms/Utils CloneFunction.cpp

clang format
DeltaFile
+1-1llvm/lib/Transforms/Utils/CloneFunction.cpp
+1-11 files

LLVM/project 853327allvm/lib/IR Instructions.cpp

[IR] Optimize PHINode::removeIncomingValueIf() using two-pointer
DeltaFile
+15-16llvm/lib/IR/Instructions.cpp
+15-161 files

LLVM/project 85f8b76llvm/lib/Transforms/Utils LoopRotationUtils.cpp

[LoopRotate] Simplify PHINode::removeIncomingValue usage
DeltaFile
+1-1llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
+1-11 files

LLVM/project 50d833allvm/lib/Transforms/Utils CodeExtractor.cpp

[CodeExtractor] Optimize PHI incoming value removal using reverse iteration
DeltaFile
+1-1llvm/lib/Transforms/Utils/CodeExtractor.cpp
+1-11 files

LLVM/project 4bd036amlir/include/mlir/Bindings/Python IRCore.h, mlir/lib/Bindings/Python IRAttributes.cpp MainModule.cpp

rebase
DeltaFile
+7-7mlir/include/mlir/Bindings/Python/IRCore.h
+4-5mlir/python/CMakeLists.txt
+0-8mlir/lib/Bindings/Python/IRAttributes.cpp
+8-0mlir/lib/Bindings/Python/MainModule.cpp
+19-204 files

LLVM/project 238a970llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU waitcnt-loop-ds-opt-same-iter-overwrite.mir waitcnt-loop-ds-opt-no-improvement.mir

[AMDGPU] DS loop wait relaxation -- more test cases and improvements to handle them (4/4)

Add handling for same-iteration use/overwrite of DS load results:
- Track DS load destinations and detect when results are used or
  overwritten within the same iteration
- Compute FloorWaitCount for WMMAs that only use flushed loads
Add bailout for tensor_load_to_lds and LDS DMA writes after barrier
Add negative test based on profitability criteria

Assisted-by: Cursor / claude-4.5-opus-high
DeltaFile
+111-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-opt-same-iter-overwrite.mir
+109-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-opt-no-improvement.mir
+107-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-opt-same-iter-use.mir
+93-6llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+97-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-opt-tensor-load.mir
+1-1llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-opt-eligible.mir
+518-76 files

LLVM/project 70826b7llvm/lib/Transforms/Utils CloneFunction.cpp

[CloneFunciton] Optimize PHI incoming value removal using reverse iteration
DeltaFile
+4-5llvm/lib/Transforms/Utils/CloneFunction.cpp
+4-51 files