LLVM/project 44d4197llvm/lib/Target/RISCV RISCVIndirectBranchTracking.cpp, llvm/test/CodeGen/RISCV lpad.ll

[RISCV] Emit lpad for function with returns-twice attribute (#170520)

Insert the landing pad after the functions with attribute "returns-twice"
as such function could return from a indirect branch (e.g. `setcontext`,
`swapcontext`, `setjmp`), so that they could use a normal indirect branch
which is safer than a software-guarded branch.
DeltaFile
+71-0llvm/test/CodeGen/RISCV/lpad.ll
+30-4llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+101-42 files

LLVM/project 9a71effllvm/test/CodeGen/RISCV/rvv sifive_sf_vlte32.ll sifive_sf_vlte64.ll

[RISCV] Remove zvfh and experimental-zvfbfmin from the tests for xsfmm. (#170589)

Those testcases don't need zvfh and experimental-zvfbfmin.
DeltaFile
+4-5llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll
+4-5llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll
+4-5llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll
+4-5llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll
+4-5llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll
+4-5llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll
+24-307 files not shown
+52-6513 files

LLVM/project 46ef57amlir/include/mlir/Dialect/LLVMIR NVVMOps.td, mlir/lib/Dialect/LLVMIR/IR NVVMDialect.cpp

[MLIR][NVVM] Add mbarrier.try_wait Op (#170285)

This patch adds an Op for mbarrier.try_wait operation which lowers
to the corresponding intrinsics. This Op has support for an optional
time-limit, state-or-phase as well as relaxed memory semantics,
completing the features on this Op up to Blackwell.

Unlike the existing `nvvm.mbarrier.try_wait.parity` Op, this Op
does not provide a _blocking_ implementation. We intend to
add looping around this at NVGPU in a subsequent PR
(and deprecate the inline-asm based Op here).

lit tests are added to verify the lowering to the intrinsics.

Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
DeltaFile
+147-0mlir/test/Target/LLVMIR/nvvm/mbar_try_wait.mlir
+54-0mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+41-0mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+16-0mlir/test/Target/LLVMIR/nvvm/mbar_invalid.mlir
+258-04 files

LLVM/project cb5ccabllvm/lib/Target/RISCV RISCVInstrInfoXqci.td RISCVISelDAGToDAG.cpp

[RISCV][NFC] Simplify Imm range checks (#170497)

DeltaFile
+4-4llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+3-5llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+3-3llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+3-3llvm/lib/Target/RISCV/RISCVGISel.td
+2-2llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+1-1llvm/lib/Target/RISCV/RISCVInstrInfo.td
+16-186 files

LLVM/project 896288dllvm/test/tools/llvm-exegesis/RISCV latency-by-extension-C.s, llvm/tools/llvm-exegesis/lib SerialSnippetGenerator.cpp

[Exegesis][RISCV] Support C_LDSP for llvm-exegesis (#169660)

Fix error:
```
*** Bad machine code: Illegal physical register for instruction ***
- function:    foo
- basic block: %bb.0  (0x5e2262bd3f20)
- instruction: $x10 = C_LDSP $x10, 0
- operand 1:   $x10
$x10 is not a SP register.
llvm-exegesis error: The machine function failed verification.
```
DeltaFile
+9-0llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s
+9-0llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+6-1llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
+24-13 files

LLVM/project d5b1afbutils/bazel/third_party_build BUILD.bazel BUILD

[bazel][NFC] Rename third_party_build/BUILD -> BUILD.bazel (#169709)

All other build files are named BUILD.bazel, not sure why this one is
different.
DeltaFile
+5-0utils/bazel/third_party_build/BUILD.bazel
+0-5utils/bazel/third_party_build/BUILD
+5-52 files

LLVM/project c08f49bllvm/include/llvm/Analysis Delinearization.h, llvm/lib/Analysis Delinearization.cpp DependenceAnalysis.cpp

[delinearize] use SCEV exprs in getIndexExpressionsFromGEP (#162888)

clean up interface of getIndexExpressionsFromGEP to get SCEV expressions
instead of int for Sizes of the arrays.
This intends to simplify the code in #156342 by avoiding conversions
from SCEV to int and back to SCEV.
DeltaFile
+6-6llvm/include/llvm/Analysis/Delinearization.h
+3-7polly/lib/Analysis/ScopBuilder.cpp
+3-2llvm/lib/Analysis/Delinearization.cpp
+1-1llvm/lib/Analysis/DependenceAnalysis.cpp
+13-164 files

LLVM/project c44b9ecutils/bazel/llvm-project-overlay/clang BUILD.bazel, utils/bazel/llvm-project-overlay/clang/unittests BUILD.bazel

[bazel][clang][DependencyScanning] Port #169962: clang dependency scanner deps (#170600)

DeltaFile
+5-6utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+1-1utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
+6-72 files

LLVM/project e891ff3llvm/lib/Transforms/Utils ModuleUtils.cpp

[KCFI][NFC] Remove unused header (#170599)

In addition to being unused, this forms a layering violation between
Transforms/Utils and Transforms/Instrumentation
DeltaFile
+0-1llvm/lib/Transforms/Utils/ModuleUtils.cpp
+0-11 files

LLVM/project 2222cfellvm/include/llvm-c OrcEE.h, llvm/lib/ExecutionEngine/Orc OrcV2CBindings.cpp

[C-API] LLVMOrcCreateObjectLinkingLayerWithInProcessMemoryManager (#169862)

Allow C programs to use JITLink with trivial new C-API wrapper. Modeled
on `LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager`
except that it has to deal with failure of
`jitlink::InProcessMemoryManager::Create()`. Function name suggested by
@lhames in https://github.com/llvm/llvm-project/issues/106203.

I suppose failure of underlying platform-specific things like
`sysconf(_SC_PAGESIZE)` shouldn't really happen. An alternative error
reporting style might be to follow
`LLVMOrcCreateDynamicLibrarySearchGeneratorForProcess` and return
`LLVMErrorRef` with an output parameter for the `LLVMOrcObjectLayerRef`,
but then it wouldn't be a drop-in replacement for
`LLVMOrcCreateRTDyldObjectLinkingLayerWithSectionMemoryManager`.
Thoughts?

This is wanted by PostgreSQL (branch using this API:
https://github.com/macdice/postgres/tree/llvm-22-proposed-c-api). (We're

    [4 lines not shown]
DeltaFile
+13-0llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
+8-0llvm/include/llvm-c/OrcEE.h
+21-02 files

LLVM/project 03a4738mlir/include/mlir/Dialect/XeGPU/IR XeGPUAttrs.td, mlir/lib/Dialect/XeGPU/IR XeGPUDialect.cpp

address feedback
DeltaFile
+23-19mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+8-9mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+4-7mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+3-3mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+38-384 files

LLVM/project f99aad3llvm/include/llvm/Transforms/Utils ProfileVerify.h, llvm/lib/Passes PassRegistry.def

[profcheck] Don't verify global ctors
DeltaFile
+34-0llvm/lib/Transforms/Utils/ProfileVerify.cpp
+13-0llvm/test/Transforms/PGOProfile/profcheck-llvm.global_ctors.ll
+0-8llvm/utils/profcheck-xfail.txt
+5-1llvm/include/llvm/Transforms/Utils/ProfileVerify.h
+1-1llvm/lib/Passes/PassRegistry.def
+1-1llvm/test/Transforms/PGOProfile/prof-verify-known-cold.ll
+54-112 files not shown
+56-138 files

LLVM/project a82b97cllvm/lib/CodeGen BasicBlockSections.cpp, llvm/test/CodeGen/Generic machine-function-splitter.ll

[CodeGen] Fix lpad padding at section start after empty block (#112595)

If a landing pad is at the very start of a split section, it has to be
padded by a nop instruction. Otherwise its offset is marked as zero in
the LSDA, which means no landing pad (leading it to be skipped).

LLVM already handles this. If a landing pad is the first machine block
in a section, a nop is inserted to ensure a non-zero offset. However, if
the landing pad is preceeded by an empty block, the nop would be
omitted.

To fix this, this patch adds a field to machine blocks indicating
whether this block contains the first instruction in its section. This
variable is then used to determine whether to emit the padding.

Co-authored-by: Jinjie Huang <huangjinjie at bytedance.com>
DeltaFile
+30-0llvm/test/CodeGen/Generic/machine-function-splitter.ll
+9-1llvm/lib/CodeGen/BasicBlockSections.cpp
+39-12 files

LLVM/project 5b30750llvm/test/CodeGen/AMDGPU waitcnt-debug.mir

[AMDGPU] Readd assertions requirement to test after #170468

This was removed in #170468 now that debug counters are enabled by
default rather than requiring asserts. This AMDGPU test exercises
functionality in SIInsertWaitcnts.cpp that is fully wrapped in NDEBUG
though, so this test still needs an assertions requirement to pass.
DeltaFile
+1-0llvm/test/CodeGen/AMDGPU/waitcnt-debug.mir
+1-01 files

LLVM/project e5c3a53llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/Mips fp-maximumnum-minimumnum.ll

expandFMINIMUMNUM_FMAXIMUMNUM: Improve compare between zeros (#140193)

1. On GPR32 platform, expandIS_FPCLASS may fail due to ISD::BITCAST
double to int64 may fail. Let's FP_ROUND double to float first.
Since we use it if MinMax is zero only, so the flushing won't
break anything.
    
2. Only one IS_FPCLASS is needed. MinMax will always be RHS if equal.
So we can select between LHS and MinMax.
It will even safe if FP_ROUND flush a small LHS, as if LHS is not zero
then, MinMax won't be Zero, so we will always use MinMax.

---------

Co-authored-by: Nikita Popov <github at npopov.com>
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
DeltaFile
+8,857-10,952llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,840-10,957llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+430-594llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+424-588llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+724-39llvm/test/CodeGen/Mips/fp-maximumnum-minimumnum.ll
+382-0llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+19,657-23,1302 files not shown
+19,794-23,1368 files

LLVM/project a29b29cllvm/lib/DWP DWP.cpp, llvm/test/tools/llvm-dwp/X86 soft_stop.test

[llvm-dwp] Fix FoundCUUnit problem on soft-stop with DWARF5 (#169783)

Currently, when a 'soft-stop' is triggered due to debug_info overflow,
there is an additional check for Dwarf5 to verify if the dwo contains a
split_compile unit (CU). However, since split_type units (TUs) are
typically placed before CUs in debug_info for Dwarf5, if an overflow is
detected within a TU causing an early break, the logic incorrectly
assumes this DWO lacks a CU and triggers an error.

Since the overflowing DWO will be discarded anyway, this validation is
redundant. This patch tries to fix this by removing the CU check during
a soft-stop.

Before this patch:
```
llvm-dwp main.dwo -continue-on-cu-index-overflow=soft-stop -o main.dwp
warning: debug_info Section Contribution Offset overflow 4G. Previous Offset 4294967271, After overflow offset 38.
error: no compile unit found in file: main.dwo
```

    [4 lines not shown]
DeltaFile
+457-0llvm/test/tools/llvm-dwp/X86/soft_stop.test
+1-3llvm/lib/DWP/DWP.cpp
+458-32 files

LLVM/project dc0fa08mlir/include/mlir/Analysis/Presburger IntegerRelation.h, mlir/lib/Analysis/Presburger IntegerRelation.cpp

[MLIR][Presburger] optimize bound computation by pruning orthogonal constraints (#164199)

IntegerRelation uses Fourier-Motzkin elimination and Gaussian
elimination to simplify constraints. These methods may repeatedly
perform calculations and elimination on irrelevant variables.
Preemptively eliminating irrelevant variables and their associated
constraints can speed up up the calculation process.
DeltaFile
+61-0mlir/lib/Analysis/Presburger/IntegerRelation.cpp
+33-4mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
+94-42 files

LLVM/project 2b226c8utils/bazel/llvm-project-overlay/clang BUILD.bazel, utils/bazel/llvm-project-overlay/llvm BUILD.bazel

Fix bazel build for 6e479668ba746ee3778b7ab59b7c415976719c93
DeltaFile
+15-1utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+16-12 files

LLVM/project e60d62bllvm/lib/Transforms/InstCombine InstCombinePHI.cpp, llvm/lib/Transforms/Utils Local.cpp

Utils: Inhibit load/store folding through phis for llvm.protected.field.ptr.

Protected pointer field loads/stores should be paired with the intrinsic
to avoid unnecessary address escapes.

Reviewers: nikic

Reviewed By: nikic

Pull Request: https://github.com/llvm/llvm-project/pull/151649
DeltaFile
+38-0llvm/test/Transforms/PhaseOrdering/phi-protected-field-ptr.ll
+2-4llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
+6-0llvm/lib/Transforms/Utils/Local.cpp
+46-43 files

LLVM/project 4afc256llvm/docs LangRef.rst, llvm/include/llvm/IR Intrinsics.td

Add llvm.protected.field.ptr intrinsic and pre-ISel lowering.

This intrinsic is used to implement pointer field protection.
For more information, see the included LangRef update and the RFC:
https://discourse.llvm.org/t/rfc-structure-protection-a-family-of-uaf-mitigation-techniques/85555

Reviewers: nikic, fmayer, ahmedbougacha

Reviewed By: nikic, fmayer

Pull Request: https://github.com/llvm/llvm-project/pull/151647
DeltaFile
+143-0llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+111-0llvm/test/Transforms/PreISelIntrinsicLowering/protected-field-pointer.ll
+111-0llvm/test/Transforms/PreISelIntrinsicLowering/protected-field-pointer-addrspace1.ll
+52-0llvm/docs/LangRef.rst
+7-0llvm/include/llvm/IR/Intrinsics.td
+424-05 files

LLVM/project c2409b4llvm/include/llvm/Analysis TargetTransformInfoImpl.h, llvm/include/llvm/CodeGen BasicTTIImpl.h

[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl (#169885)

Following #165532, this patch moves scalarization‑cost computation into
BaseT::getMemIntrinsicCost and lets backends override it via their
getMemIntrinsicCost.
It also removes the masked/gather‑scatter/strided/expand‑compress
costing interfaces from TTIImpl.
Targets may keep them locally if needed.

Stacked on #170426 and #170436.
DeltaFile
+42-66llvm/include/llvm/CodeGen/BasicTTIImpl.h
+13-25llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+21-5llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+16-2llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+16-2llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+7-10llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+115-1104 files not shown
+150-12610 files

LLVM/project b8a5888libclc/opencl/include/clc/opencl/synchronization utils.h

[libclc] Fix memory fence scope mapping for OpenCL (#170542)

The function `__opencl_get_memory_scope` incorrectly assumed that the
Clang built-in `__MEMORY_SCOPE_*` macros defined as bitmasks, while they
are actually defined as distinct integer values. This led to incorrect
mapping of OpenCL memory fence flags to LLVM memory scopes, causing
issues in generated code.

The fix involves updating the `__opencl_get_memory_scope` function to
return the correct `__MEMORY_SCOPE_*` values based on the provided
`cl_mem_fence_flags`. Additionally, the `__opencl_get_memory_semantics`
and the `__opencl_get_memory_scope` functions are marked as `static`
to avoid potential multiple definition issues during linking.
DeltaFile
+5-6libclc/opencl/include/clc/opencl/synchronization/utils.h
+5-61 files

LLVM/project e60a69aclang/include/clang/Frontend CompilerInvocation.h, clang/lib/Driver/ToolChains CommonArgs.cpp

[Clang] Reuse the function getOptimizationLevel in tools::addLTOOptions. (#169762)

DeltaFile
+8-20clang/lib/Driver/ToolChains/CommonArgs.cpp
+2-2clang/include/clang/Frontend/CompilerInvocation.h
+2-2clang/lib/Frontend/CompilerInvocation.cpp
+12-243 files

LLVM/project 1952c1cutils/bazel/llvm-project-overlay/clang BUILD.bazel, utils/bazel/llvm-project-overlay/llvm BUILD.bazel

Fix bazel build for 6e479668ba746ee3778b7ab59b7c415976719c93
DeltaFile
+12-1utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+13-12 files

LLVM/project bf139dallvm/include/llvm/CodeGen SelectionDAG.h, llvm/lib/CodeGen/SelectionDAG LegalizeDAG.cpp TargetLowering.cpp

DAG: Add overload of getExternalSymbol using RTLIB::LibcallImpl
DeltaFile
+7-8llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+4-4llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+5-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+1-2llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+1-0llvm/include/llvm/CodeGen/SelectionDAG.h
+18-145 files

LLVM/project 8d43197mlir/test/Dialect/XeGPU xegpu-wg-to-sg-unify-ops.mlir

[MLIR][XeGPU] Change index arithmetic ops to arith op (#170581)

This PR fixes the failure caused in the post-merge of PR #169571
DeltaFile
+10-10mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+10-101 files

LLVM/project ba5d29eclang/test/CodeGenCXX aggregate-lifetime-invoke.cpp

Update invoke test for tighter lifetimes
DeltaFile
+12-15clang/test/CodeGenCXX/aggregate-lifetime-invoke.cpp
+12-151 files

LLVM/project efbbca6llvm/include/llvm/IR DebugInfoMetadata.h, llvm/lib/CodeGen/AsmPrinter DwarfUnit.cpp

[llvm][DebugInfo] Allow DIDerivedType as a bound in DISubrangeType (#165880)

Consider this Ada type:

```
   type Array_Type is array (Natural range <>) of Integer;
   type Record_Type (L1, L2 : Natural) is record
      I1 : Integer;
      A1 : Array_Type (1 .. L1);
      I2 : Integer;
      A2 : Array_Type (1 .. L2);
      I3 : Integer;
   end record;
```

Here, the array fields have lengths that depend on the discriminants of
the record type. However, in this case the array lengths cannot be
expressed as DWARF location expressions, with the issue being that "A2"
has a non-constant offset, but an expression involving

    [24 lines not shown]
DeltaFile
+88-0llvm/test/DebugInfo/X86/derived-in-subrange.ll
+8-4llvm/lib/IR/Verifier.cpp
+4-1llvm/lib/IR/DebugInfoMetadata.cpp
+3-1llvm/include/llvm/IR/DebugInfoMetadata.h
+3-0llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+106-65 files

LLVM/project 5a47ed2llvm/lib/CodeGen/SelectionDAG LegalizeIntegerTypes.cpp

DAG: Avoid asserting on libcall action if function is unavailable

Eventually the set of available functions will be a program
dependent property, which could diverge from the static table of
functions for the subtarget. In that case, fall back to the usual
expansion.
DeltaFile
+13-7llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+13-71 files

LLVM/project 1142c93llvm/test/CodeGen/PowerPC amo-enable.ll

Remove redundant tests from amo-enable.ll
DeltaFile
+0-40llvm/test/CodeGen/PowerPC/amo-enable.ll
+0-401 files