LLVM/project 91ad9f0llvm/test/CodeGen/AMDGPU llvm.amdgcn.permlane.ll llvm.is.fpclass.f16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Handle G_BITCAST for 16 bit extendedLLTs (#208750)

Handle bitcast between i16 and f16/bf16.
For true16 this was already legal, make it legal in regbanklegalize as well.
For non-true16 widen it using G_ANYEXT to i32 and G_TRUNC to dst.
The "i32 G_ANYEXT f16/bf16" and "f16/bf16 G_TRUNC i32" are already legal,
for example these are generated by common CallLowering argument lowering.
DeltaFile
+3,572-3,745llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+3,314-3,041llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+3,245-2,737llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1,670-1,373llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+1,239-552llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+656-996llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+13,696-12,444180 files not shown
+24,994-20,597186 files

LLVM/project 3c4c850llvm/test/CodeGen/AMDGPU div_i128.ll div_v2i128.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

GlobalISel: Use extended LLTs in lshr narrow combine
DeltaFile
+3,024-2,355llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+3,080-2,174llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1,894-2,067llvm/test/CodeGen/AMDGPU/div_i128.ll
+1,365-1,378llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+1,625-788llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+218-153llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+11,206-8,91510 files not shown
+12,049-9,47316 files

LLVM/project a6e889bllvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU global-saddr-load.ll

AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for applyD16Load
DeltaFile
+14-1llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+2-2llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+16-32 files

LLVM/project bcf3b81llvm/test/CodeGen/AMDGPU llvm.log10.ll llvm.log.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fpow.ll

AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper

Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
DeltaFile
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log.ll
+2,760-1,251llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+912-86llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+536-218llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+290-131llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+11,694-4,8624 files not shown
+12,158-5,07110 files

LLVM/project c5de96fllvm/lib/Target/AMDGPU AMDGPUPreLegalizerCombiner.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-short-clamp.ll

AMDGPU/GlobalISel: Use integers for clamp i64 to i16 prelegalizer combine
DeltaFile
+26-46llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+6-6llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+32-522 files

LLVM/project 37aca7fllvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU codegen-prepare-addrspacecast-non-null.ll

GlobalISel: Use extended LLTs in extract lowering
DeltaFile
+60-29llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+1-1llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+79-485 files

LLVM/project 9f3cf8ellvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU fptrunc.f16.ll fptrunc.ll

GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering
DeltaFile
+1,282-1,453llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+264-432llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+364-243llvm/test/CodeGen/AMDGPU/fptrunc.ll
+238-239llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
+176-91llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+47-47llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+2,371-2,5056 files

LLVM/project b36e672llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.prefetch.inst.ll llvm.amdgcn.s.prefetch.data.ll, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-load.mir regbankselect-waterfall-call.mir

AMDGPU/GlobalISel: Use integers for read-any-lane split type
DeltaFile
+150-72llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
+106-106llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+33-17llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
+24-24llvm/test/CodeGen/AMDGPU/indirect-call.ll
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+341-2476 files not shown
+364-27212 files

LLVM/project a4ddf80llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel zextload.ll

AMDGPU/GlobalISel: Fix extending load narrow scalar

isAnyScalar is explicit LLT::scalar check but we want to narrow scalar
integer types as well.
DeltaFile
+6-7llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+7-82 files

LLVM/project c415b20llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-constant.mir

AMDGPU/GlobalISel: Use integer as MMO type for loads and stores lowering

We could get away with just the type from MMO in most cases, but MMO splitting
creates MMO with LLT::scalar and we prefer integer.
DeltaFile
+1,622-1,442llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,064-944llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+828-738llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+842-722llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+250-220llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+121-121llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+4,727-4,1878 files not shown
+4,995-4,28614 files

LLVM/project e1a1422llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

AMDGPU/GlobalISel: Explicitly widen scalar to i32 for load and store

Affects f16 and bf16. Earlier, they were widened to f32 and s32 respectively.
The actual error was the artifact combiner creating a copy between f32/i32
which fails in the machine verifier. Maybe we could create a bitcast there.
However i32 is more efficient for us and matches well with how argument
lowering keeps f16 and bf16 in i32 copies to/from physical registers.
Also starting from f16 store, G_STORE %0(f16), %1(p1) :: (store (f16),
and doing widen scalar to 32 bit type, i32 makes more sense since store
will store 16 least significant bits G_STORE %0(i32), %1(p1) :: (store (f16)
compared to G_STORE %0(f32), %1(p1) :: (store (f16), which looks incorrect if
we assume input was really in f32 format.
DeltaFile
+2,008-2,008llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,164-1,164llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+963-963llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+556-556llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+486-486llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+108-108llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+5,285-5,28515 files not shown
+5,362-5,36821 files

LLVM/project f8ba8c7llvm/test/CodeGen/AMDGPU vector-reduce-smin.ll vector-reduce-smax.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.i16.ll insertelement.i8.ll

AMDGPU/GlobalISel: Fix legalizer lowering for G_EXTRACT/INSERT_VECTOR_ELT

Use LLT::integer in bit twiddling lowering for extract/insert vector element.
DeltaFile
+2,741-4,467llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+1,627-4,750llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+990-990llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+975-439llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+8,357-11,51426 files not shown
+13,363-14,10532 files

LLVM/project 66f11acllvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Stop using changeTo in legaizer actions

Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
DeltaFile
+855-425llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+783-389llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+759-377llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+253-160llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+232-138llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+58-80llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+2,940-1,56911 files not shown
+3,066-1,65117 files

LLVM/project 8e03e3allvm/test/CodeGen/AMDGPU memset-param-combinations.ll shrink-add-sub-constant.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll saddsat.ll

AMDGPU/GlobalISel: Fix G_MERGE_VALUES lowering for extended LLTs

Use integer type for bit twiddling instead of scalar.
DeltaFile
+1,801-1,013llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
+1,584-1,032llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+1,583-1,004llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+1,449-654llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+1,314-625llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+989-704llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+8,720-5,032186 files not shown
+29,005-19,793192 files

LLVM/project 87f6863llvm/test/CodeGen/AMDGPU freeze.ll vector-reduce-fmin.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f16.ll

AMDGPU/GlobalISel: Fix G_UNMERGE_VALUES lowering for extended LLTs

Use integer type for bit twiddling instead of scalar.
DeltaFile
+1,623-486llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+1,155-361llvm/test/CodeGen/AMDGPU/freeze.ll
+663-347llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+663-347llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+590-290llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+545-261llvm/test/CodeGen/AMDGPU/mad-mix.ll
+5,239-2,092150 files not shown
+15,641-10,429156 files

LLVM/project ae9e2d8llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

AMDGPU/GlobalISel: Switch legalizer intrinsic lowering to extended LLTs

Affects various buffer intrinsics.
DeltaFile
+5,162-5,142llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+4,767-4,791llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+4,321-4,345llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+2,172-2,164llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+2,119-2,107llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+965-965llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+19,506-19,51462 files not shown
+24,540-23,91268 files

LLVM/project 02d2001llvm/test/CodeGen/AMDGPU llvm.amdgcn.permlane.ll llvm.is.fpclass.f16.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Handle G_BITCAST for 16 bit extendedLLTs

Handle bitcast between i16 and f16/bf16.
For true16 this was already legal, make it legal in regbanklegalize as well.
For non-true16 widen it using G_ANYEXT to i32 and G_TRUNC to dst.
The "i32 G_ANYEXT f16/bf16" and "f16/bf16 G_TRUNC i32" are already legal,
for example these are generated by common CallLowering argument lowering.
DeltaFile
+3,572-3,745llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+3,314-3,041llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+3,245-2,737llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1,670-1,373llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+1,239-552llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+656-996llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+13,696-12,444180 files not shown
+24,994-20,597186 files

LLVM/project b438322flang/lib/Lower Bridge.cpp, flang/test/Lower if_construct_execute_region_wrap.f90

[flang][PFT-to-MLIR] reset Evaluation blocks between entry-point passes

A subprogram with an alternate ENTRY is lowered by walking the shared
PFT once per entry.  Evaluation::block is populated during each walk
(top-level createEmptyBlocks and inside wrapUnstructuredConstruct's own
createEmptyBlocks), but the second pass previously inherited stale
pointers into the first entry's function/wrap regions.  For a wrappable
IfConstruct nested inside a structured container, the entry block that
genFIR(IfConstruct) starts before creating its scf.execute_region then
sent the builder into the previous entry's region, and the wrap plus
its inner load ended up in the wrong func:

    subroutine foo(a)
      integer a
    entry bar(a)
      if (a .eq. 1) then
        if (a .ne. 3) stop
      end if
    end subroutine

    [9 lines not shown]
DeltaFile
+37-0flang/test/Lower/if_construct_execute_region_wrap.f90
+24-1flang/lib/Lower/Bridge.cpp
+61-12 files

LLVM/project 195df3dmlir/lib/Dialect/OpenACC/Utils OpenACCUtilsCG.cpp, mlir/test/Dialect/OpenACC acc-cg-to-gpu-worker-reduction-private.mlir

[mlir][OpenACC] Privatize worker reduction accumulators per worker (#210456)

Example:
```fortran
!$acc parallel
!$acc loop gang reduction(+:sum)
do k = 1, p
  !$acc loop worker reduction(+:sum)
  do j = 1, n
    !$acc loop vector reduction(+:sum)
    do i = 1, m
      sum = sum + a(i,j,k)
    end do
  end do
end do
```

In this code, the worker accumulator is both gang- and worker-scoped.
Shared

    [4 lines not shown]
DeltaFile
+47-3mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
+41-0mlir/test/Dialect/OpenACC/acc-cg-to-gpu-worker-reduction-private.mlir
+6-9mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
+94-123 files

LLVM/project fdecb09llvm/include/llvm/IR RuntimeLibcalls.td RuntimeLibcallsImpl.td, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Migrate to dag libcall predicates

Switch to using dag predicates instead of free-form code predicates.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+237-112llvm/include/llvm/IR/RuntimeLibcalls.td
+21-10llvm/test/TableGen/RuntimeLibcallEmitter.td
+8-20llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+0-26llvm/include/llvm/IR/RuntimeLibcalls.h
+11-6llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td
+0-17llvm/lib/IR/RuntimeLibcalls.cpp
+277-1917 files not shown
+314-21513 files

LLVM/project 35c8e92llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp SIDefines.h, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[NFC][AMDGPU] Use SIInstrFlags predicates in SIMemoryLegalizer and AMDGPUBaseInfo. (#209821)

Part of a series following the introduction of SIInstrFlags predicates.
DeltaFile
+16-20llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+6-6llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+3-0llvm/lib/Target/AMDGPU/SIDefines.h
+25-263 files

LLVM/project 6d76d69llvm/docs LangRef.md, llvm/lib/AsmParser LLParser.cpp

[IR] Add elementwise modifier to atomic stores
DeltaFile
+111-0llvm/unittests/IR/VerifierTest.cpp
+56-0llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
+26-4llvm/lib/AsmParser/LLParser.cpp
+19-10llvm/docs/LangRef.md
+21-4llvm/lib/IR/Verifier.cpp
+12-8llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+245-269 files not shown
+305-3715 files

LLVM/project 4caba63lldb/test/API/commands/gui/spawn-threads TestGuiSpawnThreads.py

[lldb][test] Double the timeout for TestGuiSpawnThreads.py (#210043)

If the host machine is overloaded, spawning threads may be delayed due
to lack of resources. I'm pretty sure this is the cause of failures in
GitHub CI reported in
https://github.com/llvm/llvm-project/issues/209874.

For what the test is doing, we unfortunately cannot get around needing
to wait on the test program.

We could perhaps come up with a lit mode that runs some tests in serial,
but this is a larger project than I want to get into now.

For now, let's try doubling the timeout. This test is unlikely to fail
for real, so if it's taking a long time, it'll be due to system
resources. In 99% of cases, it'll pass in a few seconds still.
DeltaFile
+4-0lldb/test/API/commands/gui/spawn-threads/TestGuiSpawnThreads.py
+4-01 files

LLVM/project ded79d9llvm/lib/Target/SPIRV SPIRVGlobalRegistry.cpp, llvm/test/CodeGen/SPIRV/constant fp128-unsupported.ll

[SPIR-V] Reject fp128 and ppc_fp128 types with a diagnostic (#208397)

Introduced as a part of discussion in
https://github.com/llvm/llvm-project/pull/208219
DeltaFile
+10-0llvm/test/CodeGen/SPIRV/constant/fp128-unsupported.ll
+2-0llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+12-02 files

LLVM/project ec1e524llvm/docs LangRef.md, llvm/lib/AsmParser LLParser.cpp

[IR] Add elementwise modifier to atomic stores
DeltaFile
+111-0llvm/unittests/IR/VerifierTest.cpp
+56-0llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
+26-4llvm/lib/AsmParser/LLParser.cpp
+19-10llvm/docs/LangRef.md
+21-4llvm/lib/IR/Verifier.cpp
+12-8llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+245-269 files not shown
+305-3715 files

LLVM/project e1db2c0llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ISelLowering.h

Address comments
DeltaFile
+23-16llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/lib/Target/AArch64/AArch64ISelLowering.h
+24-182 files

LLVM/project c340737llvm/docs LangRef.md, llvm/lib/AsmParser LLParser.cpp

[IR] Add elementwise modifier to atomic stores
DeltaFile
+111-0llvm/unittests/IR/VerifierTest.cpp
+56-0llvm/test/Assembler/invalid-load-store-atomic-elementwise.ll
+26-4llvm/lib/AsmParser/LLParser.cpp
+19-10llvm/docs/LangRef.md
+21-4llvm/lib/IR/Verifier.cpp
+12-8llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+245-269 files not shown
+302-3515 files

LLVM/project 9cb6db4llvm/include/llvm/Transforms/Scalar GVN.h, llvm/lib/Transforms/Scalar GVN.cpp

Revert "[GVN] Remove the "private" `llvm::gvn` namespace (NFC)" (#210666)

Reverts llvm/llvm-project#210323

FAILED: lib/Transforms/Scalar/CMakeFiles/LLVMScalarOpts.dir/GVN.cpp.o 


/var/llvm-compile-time-tracker/llvm-project/llvm/lib/Transforms/Scalar/GVN.cpp:4001:27:
error: qualified name does not name a class before ‘:’ token
 4001 | class llvm::GVNLegacyPass : public FunctionPass {
DeltaFile
+13-6llvm/include/llvm/Transforms/Scalar/GVN.h
+4-6llvm/lib/Transforms/Scalar/GVN.cpp
+17-122 files

LLVM/project 39a2c6alibcxx/test/libcxx/atomics builtin_clear_padding.pass.cpp, libcxx/test/std/numerics/numeric.ops/numeric.ops.sat saturating.bitint.pass.cpp

[libc++][test][NFC] Removed unsupported compilers from tests (#210413)
DeltaFile
+2-4libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating.bitint.pass.cpp
+1-1libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
+3-52 files

LLVM/project eec2f09libcxx/include/__configuration availability.h

[libc++][NFC] Removed duplicated `_LIBCPP_INTRODUCED_IN_LLVM_23` macros (#210602)

Removed the redundant macros, which apparently were added by two
different patches.
DeltaFile
+0-2libcxx/include/__configuration/availability.h
+0-21 files