LLVM - FreshBSD

LLVM/project b27d9d2 — llvm/tools/llvm-jitlink/llvm-jitlink-executor llvm-jitlink-executor.cpp

2026-09-16 05:32:53 UTC by Lang Hames via GitHub on ⎇

main

[llvm-jitlink] Fix a memory leak in llvm-jitlink-executor. (#223904)

In openListener, use a scope_exit to call freeaddrinfo on the struct
allocated by getaddrinfo.

No testcase: We have no in-tree tests for llvm-jitlink-executor. This
bug was found by inspection.

Delta		File
+2	-0	llvm/tools/llvm-jitlink/llvm-jitlink-executor/llvm-jitlink-executor.cpp
+2	-0	1 files

LLVM/project 78bbf22 — lldb/include/lldb/Host HostInfo.h, lldb/include/lldb/Host/emscripten HostInfoEmscripten.h

2026-09-16 05:29:44 UTC by Anutosh Bhat via GitHub on ⎇

main

[lldb] Add HostInfoEmscripten (#223169)

Emscripten currently selects `HostInfoLinux`. That was useful as an initial bootstrap, but it also introduces Linux-specific assumptions such as `/proc/self/exe`, invoking `lsb_releas`e through `popen`, and
Linux-specific architecture handling.

This patch introduces a small `HostInfoEmscripten` implementation derived from `HostInfoPosix` and selects it when LLDB is built with Emscripten.

The implementation intentionally remains minimal. A browser-hosted LLDB process does not currently have a meaningful native executable path, so `GetProgramFileSpec()` returns an empty FileSpec.

A dedicated PlatformEmscripten and browser-specific process behavior will be handled separately so this change remains atomic !

Delta		File
+29	-0	lldb/include/lldb/Host/emscripten/HostInfoEmscripten.h
+17	-0	lldb/source/Host/emscripten/HostInfoEmscripten.cpp
+4	-2	lldb/source/Host/CMakeLists.txt
+4	-1	lldb/include/lldb/Host/HostInfo.h
+54	-3	4 files

LLVM/project df997d2 — llvm/lib/Target/RISCV RISCVRegisterInfo.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

2026-09-16 05:23:39 UTC by Craig Topper via GitHub on ⎇

main

[RISCV] Add DecodeSingleRegister template class to replace DecodeSPRegisterClass and similar. (#223889)

This can avoid adding more explicitly written decode functions for
https://github.com/llvm/llvm-project/pull/177073

Delta		File
+16	-30	llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+3	-0	llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+19	-30	2 files

LLVM/project af0b251 — llvm/test/Transforms/LoopVectorize/AArch64 early_exit_costs.ll

2026-09-16 05:19:35 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/early-exit-fal-freeze

Fix early_exit_costs.ll test

Delta		File
+2	-2	llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
+2	-2	1 files

LLVM/project 7694dc0 — llvm/test/Transforms/LoopVectorize predicated-early-exits-interleave.ll predicated-multiple-exits.ll

2026-09-16 05:19:35 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/early-exit-fal-freeze

[VPlan] Use frozen combined condition in early exit first-active-lane

Combined is used both to compute if an early exit was taken via VPInstruction::AnyOf, as well as the index of the early-exited lane in VPInstruction::FirstActiveLane.

Combined can have poison lanes past the exited lane, so the AnyOf uses freeze to prevent branching on poison. However FirstActiveLane on a vector with a poison lane is poison, so we need to also use the frozen version of Combined to prevent poison there.

Delta		File
+32	-32	llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
+24	-24	llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
+14	-14	llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
+12	-12	llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
+10	-10	llvm/test/Transforms/LoopVectorize/predicated-multiple-exits.ll
+6	-6	llvm/test/Transforms/LoopVectorize/predicated-early-exits-interleave.ll
+98	-98	17 files not shown
+144	-142	23 files

LLVM/project e5ef5db — llvm/lib/Transforms/Vectorize VPlanConstruction.cpp, llvm/test/Transforms/LoopVectorize single-early-exit-anyof-fold.ll

2026-09-16 05:19:34 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/any-of-freeze

Remove FIXME

Delta		File
+3	-6	llvm/test/Transforms/LoopVectorize/single-early-exit-anyof-fold.ll
+1	-1	llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+4	-7	2 files

LLVM/project 1a2c10d — llvm/test/Transforms/LoopVectorize fmin-without-fast-math-flags.ll epilog-vectorization-fmaxnum-reductions.ll, llvm/test/Transforms/LoopVectorize/AArch64 fmax-without-fast-math-flags.ll

2026-09-16 05:19:34 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/any-of-freeze

Remove VPInstruction::usesFirstLaneOnly change

InstCombine will canonicalize this anyway https://godbolt.org/z/r7PsGxh6G

Delta		File
+66	-29	llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
+51	-24	llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
+43	-20	llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
+42	-20	llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
+33	-15	llvm/test/Transforms/LoopVectorize/epilog-vectorization-fmaxnum-reductions.ll
+22	-10	llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
+257	-118	3 files not shown
+290	-140	9 files

LLVM/project f7a2602 — llvm/test/Transforms/LoopVectorize single-early-exit-anyof-fold.ll

2026-09-16 05:19:34 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/any-of-freeze

Precommit test

Delta		File
+54	-0	llvm/test/Transforms/LoopVectorize/single-early-exit-anyof-fold.ll
+54	-0	1 files

LLVM/project c6daf9d — llvm/lib/Transforms/Vectorize VPlan.h VPlanTransforms.cpp

2026-09-16 05:19:34 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/any-of-freeze

Update comments

Delta		File
+2	-1	llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1	-1	llvm/lib/Transforms/Vectorize/VPlan.h
+3	-2	2 files

LLVM/project 416183c — llvm/test/Transforms/LoopVectorize fcmp-uno-fold-interleave.ll, llvm/test/Transforms/LoopVectorize/AArch64 fmax-without-fast-math-flags.ll cmp_cost.ll

2026-09-16 05:19:34 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/any-of-freeze

[VPlan] Fix VPInstruction::AnyOf combine undoing freeze

There is an any-of combine for unrolled VPlans which does:

    any-of (fcmp uno A, A), (fcmp uno B, B), ...-> any-of (fcmp uno A, B)

However any-of implicitly freezes each individual operand and this means we go from `freeze (fcmp uno A, A)` to `freeze (fcmp uno A, B)` which isn't sound: alive2.llvm.org/ce/z/UdQM7C

This causes miscompiles today with early exit loops, see the attached test case in single-early-exit-anyof-fold.ll.

This fixes it by explicitly modelling the freeze in VPlan. There are three places where we use AnyOf:

1) early exit loops: the freeze needs to be applied per-lane, so apply it to `(any-of (freeze (combined-conds-to-exit)))`
2) handleMaxMinNumReductions: If any lane of the reduction was poison in the scalar loop, the final result will be poison. We only need to freeze the result of AnyOf to prevent immediate UB when branching. Freezing individual operands blocks the any-of combine otherwise.
3) handleFindLastReductions: we need to freeze Cond itself since it's got multiple uses, but I plan on fixing this in a separate PR

Delta		File
+51	-48	llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
+32	-36	llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
+35	-31	llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
+28	-32	llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
+31	-27	llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
+30	-27	llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+207	-201	20 files not shown
+380	-354	26 files

LLVM/project f33740c — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize tail_fold_uncountable_exits.ll early_exit_with_stores.ll

2026-09-16 05:19:34 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/any-of-freeze

Don't unwrap the freeze, copy it over in side effect early exit loops

Delta		File
+27	-27	llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+12	-12	llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
+8	-8	llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
+8	-8	llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
+6	-6	llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2	-2	llvm/test/Transforms/LoopVectorize/tail_fold_uncountable_exits.ll
+63	-63	2 files not shown
+67	-67	8 files

LLVM/project bf89dd2 — llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanUtils.cpp

2026-09-16 05:19:29 UTC by Luke Lau via GitHub on ⎇

main

[VPlan] Rename createScalarFreeze -> createFreeze. NFC (#223648)

It works for vector operands too. We can also use it in
preparePlanForMainVectorLoop

Delta		File
+3	-3	llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+2	-2	llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+2	-2	llvm/lib/Transforms/Vectorize/VPlanLowering.cpp
+1	-2	llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+8	-9	4 files

LLVM/project 83066e0 — llvm/docs NVPTXUsage.md, llvm/include/llvm/IR IntrinsicsNVVM.td

2026-09-16 05:16:13 UTC by Rajat Bajpai via GitHub on ⎇

main

[LLVM][NVPTX] Add async bulk copy global to shared extensions (#222323)

This change adds following things to bulk copy intrinsics.
1. Relaxed memory ordering semantics with a scope argument.
2. Data-validity reporting patterns (introduced in Rubin).
3. 32-bit multicast mask for global to shared::cluster variants
(introduced in Rubin).
4. Ignore out of bound checks for global to shared::cta variants.

Note: MLIR lowering is updated to emit the new intrinsic signatures.
Support for the new features in MLIR will be done in a separate change.

Delta		File
+166	-71	llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+169	-49	llvm/docs/NVPTXUsage.md
+108	-108	mlir/test/Target/LLVMIR/nvvm/tma_load_cluster_im2col.mlir
+72	-72	mlir/test/Target/LLVMIR/nvvm/tma_load_cluster_tile.mlir
+112	-10	llvm/lib/IR/AutoUpgrade.cpp
+73	-19	llvm/include/llvm/IR/IntrinsicsNVVM.td
+700	-329	23 files not shown
+1,269	-413	29 files

LLVM/project c7ddefd — llvm/lib/Target/RISCV RISCVFeatures.td, llvm/test/MC/RISCV attribute-arch.s

2026-09-16 05:11:25 UTC by Zeyi Xu via GitHub on ⎇

main

[MC][RISCV] Make Zve32x a dependency of Zvabd (#223901)

The Zvabd specification defines Zve32x as a dependency. This commit
fixes the dependency problem in MC's implementation.

See:
https://github.com/riscv/integer-vector-absolute-difference/blob/0092c8451bb24b957d8358f261c0535ece88defb/src/unpriv/zvabd.adoc#L26

Delta		File
+2	-1	llvm/lib/Target/RISCV/RISCVFeatures.td
+3	-0	llvm/test/MC/RISCV/attribute-arch.s
+5	-1	2 files

LLVM/project 00fbc3f — llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

2026-09-16 05:07:33 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/simplifyRecipes-worklist-inserter

Precommit test

Delta		File
+163	-0	llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163	-0	1 files

LLVM/project 2443554 — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

2026-09-16 05:07:33 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/simplifyRecipes-logical-recipe

[VPlan] Remove (X && Y) | (X && !Y) -> X combine. NFC

We have smaller combines that can take care of this now that we process recipes in a worklist

Delta		File
+1	-8	llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1	-8	1 files

LLVM/project 2595cb9 — llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

2026-09-16 05:07:33 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/simplifyRecipes-worklist-inserter

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]

Delta		File
+26	-8	llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11	-4	llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+5	-7	llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+42	-19	3 files

LLVM/project 6c1d20c — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize iv_outside_user.ll dont-fold-tail-for-divisible-TC.ll

2026-09-16 05:07:29 UTC by Luke Lau via GitHub on ⎇

users/lukel97/loop-vectorize/simplifyRecipes-worklist-inserter

[VPlan] Process combineRecipes in a worklist (#213899)

This brings combineRecipes further in line with InstCombine, and asides
from unlocking more simplifications it also helps avoid test churn
whenever passes are moved around combineRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification
order as before.

Delta		File
+74	-90	llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
+57	-0	llvm/test/Transforms/LoopVectorize/blend-i1.ll
+25	-13	llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4	-8	llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+1	-2	llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+161	-113	5 files

LLVM/project 8a512d6 — clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp

2026-09-16 05:03:24 UTC by skc7 on ⎇

users/skc7/cir/abi_canbefalttened

[CIR][ABI] Honor abi::ArgInfo::CanBeFlattened in the call-conv lowering

Delta		File
+8	-4	clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+8	-4	1 files

LLVM/project 8b66604 — llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp, llvm/test/MC/RISCV zicfiss-valid.s

2026-09-16 05:00:50 UTC by Craig Topper via GitHub on ⎇

main

[RISCV] Remap mop.rr.7 and mop.r.28 to sspush/sspopchk/ssrdp in the assembler. (#223894)

This makes llvm-mc output match llvm-objdump. And is more consistent
with the InstAliases we use c.mop.

Delta		File
+30	-0	llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+9	-15	llvm/test/MC/RISCV/zicfiss-valid.s
+39	-15	2 files

LLVM/project 262cf39 — llvm/lib/MC/MCParser MCAsmParser.cpp, llvm/test/MC/AsmParser macro-max-depth.s

2026-09-16 04:50:44 UTC by Matt Turner via GitHub on ⎇

main

[MC] Increase asm-macro-max-nesting-depth default to 100 (#218455)

GNU as accepts assembly we reject at the current default of 20, e.g.
glibc's
`sysdeps/unix/sysv/linux/alpha/rt_sigaction.S`, which nests 31 deep.
Raise the
default to 100, matching GNU as.

Assisted-by: Claude Code

Delta		File
+13	-13	llvm/test/MC/AsmParser/macro-max-depth.s
+1	-1	llvm/lib/MC/MCParser/MCAsmParser.cpp
+14	-14	2 files

LLVM/project 9302119 — mlir/python/mlir/dialects/linalg init.py, mlir/test/python/dialects/linalg ops.py

2026-09-16 04:48:37 UTC by makslevental via Maksim Levental on ⎇

users/makslevental/fix-linalg-elemwise

[mlir][python] Register linalg.ElementwiseOp wrapper as op view

The hand-written ElementwiseOp wrapper subclassed the generated OpView but
was not registered in the op-view registry, so ops reconstructed from the
registry (e.g. Operation.opview) were instances of the generated base class
rather than the publicly exported subclass. This made
isinstance(op.opview, linalg.ElementwiseOp) and match/case dispatch return
False for real linalg.elementwise ops.

Register the wrapper with replace=True (as pdl.py does) so the exported
class is the one the registry instantiates.

Fixes #223673

Delta		File
+21	-0	mlir/test/python/dialects/linalg/ops.py
+3	-4	mlir/python/mlir/dialects/linalg/__init__.py
+24	-4	2 files

LLVM/project 2d7343a — mlir/test/python/dialects/linalg ops.py

2026-09-16 04:48:37 UTC by makslevental via Maksim Levental on ⎇

users/makslevental/fix-linalg-elemwise

Remove comment per review

Delta		File
+0	-2	mlir/test/python/dialects/linalg/ops.py
+0	-2	1 files

LLVM/project c20428c — mlir/lib/Dialect/LLVMIR/IR NVVMDialect.cpp, mlir/test/Target/LLVMIR/nvvm mbar_arrive_drop.mlir

2026-09-16 04:26:04 UTC by Dhairyashil R G via GitHub on ⎇

main

[MLIR][NVVM] Fix the lowering of legacy mbar.arrive_drop (#222916)

`nvvm.mbarrier.arrive_drop` fails to compile for sm_80:

LLVM ERROR: Cannot select: intrinsic
%llvm.nvvm.mbarrier.arrive.drop.scope.cta.space.cta

The op always lowers to the `scope.*.space.*` intrinsics, which need
sm_90. The legacy `llvm.nvvm.mbarrier.arrive.drop{,.shared}` intrinsics
work from sm_80 but are never used.

This uses the legacy intrinsic for the basic case only, space=cta,
scope=cta, no relaxed, no explicit count, the same fix as #172476 for
`mbarrier.arrive`. The count forms need sm_90, so they are unchanged.

Assisted-by: Claude

Delta		File
+15	-2	mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir
+8	-2	mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+23	-4	2 files

LLVM/project 4ee9daf — llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

2026-09-16 04:13:05 UTC by Craig Topper via GitHub on ⎇

main

[RISCV] Use DecodeFilteredRegisterClass for DecodeGPRX1X5RegisterClass. (#223878)

Delta		File
+3	-11	llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+3	-11	1 files

LLVM/project dec17c4 — flang/lib/Semantics expression.cpp

2026-09-16 03:55:12 UTC by Valentin Clement (バレンタインクレメン) via GitHub on ⎇

main

[flang][cuda] Fix matching distance for use_device and none (#223849)

https://docs.nvidia.com/hpc-sdk/compilers/cuda-fortran-prog-guide/#unified-data
the table set the matching distance for actual `use_device` and dummy
argument `none` to 1 but the implementation set it to 3.

@wangzpgi Was there a specific reason to set 3 instead of 1?

Delta		File
+2	-2	flang/lib/Semantics/expression.cpp
+2	-2	1 files

LLVM/project 0454184 — llvm/test/Transforms/LoopVectorize uniform_across_vf_induction1.ll

2026-09-16 03:47:48 UTC by Luke Lau on ⎇

users/lukel97/loop-vectorize/simplifyRecipes-worklist

Update uniform_across_vf_induction1.ll

Delta		File
+74	-90	llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
+74	-90	1 files

LLVM/project fa72130 — llvm/test/CodeGen/AMDGPU coexec-sched-ds-fifo.mir coexec-scheduler.ll

2026-09-16 03:31:23 UTC by Jeffrey Byrnes on ⎇

users/jebyrnes/DSLatencyModeRebase0

Fix lit

Change-Id: Id8c3f63acdce212f1030e5dfc7d9273c56945958

Delta		File
+11	-3	llvm/test/CodeGen/AMDGPU/ds-latency-mode-flag.mir
+3	-3	llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
+0	-4	llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+2	-2	llvm/test/CodeGen/AMDGPU/coexec-sched-agpr-excess.mir
+1	-1	llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
+17	-13	5 files

LLVM/project 4150e90 — llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

2026-09-16 03:30:25 UTC by Craig Topper via GitHub on ⎇

main

[RISCV] Call DecodeGPRPairRegisterClass from DecodeGPRPairCRegisterClass. NFC (#223882)

GPRPairC is a subset of GPRPair. We just need to do the range check and
let DecodeGPRPairRegisterClass do the rest of the work.

Delta		File
+1	-8	llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+1	-8	1 files

LLVM/project 46f08d7 — llvm/lib/Target/RISCV RISCVInstrInfoZicfiss.td, llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

2026-09-16 03:28:33 UTC by Craig Topper via GitHub on ⎇

main

[RISCV] Remove Zicfiss DecoderNamespace. NFC (#223891)

This used to be needed to prioritize c.sspopchk and c.sspush over
c.mop.1 and c.mop.5, but those are treated as InstAliases now.

Delta		File
+1	-2	llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td
+0	-2	llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+1	-4	2 files