[analyzer] Chain checkers in runCheckersForEndFunction (#220970)
The function `runCheckersForEndFunction` had an unusual behavior that it
invoked the callbacks in parallel (introducing a new execution path for
each checker callback that produced a transition), unlike all other
analogous functions, which "chained" the checkers, executing them after
each other.
This behavior was introduced before 2011, when this callback was called
`check::EndPath`, to ensure that the `EndPath` callbacks are _final_ and
nodes created by them end up at the end of the execution path. When
interprocedural analysis (inlining functions) was introduced in 2013,
the callback was renamed to `EndFunction` (to reflect that it also
activates at the end of inlined functions), but the unusual behavior was
preserved.
There were 8 "real" checkers with `check::EndFunction` callbacks, but
most of them only created error nodes or did "nice to have" cleanup, so
the irregular behavior of this callback did not cause visible trouble.
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[ORC] Carry out-of-band errors in SimpleRemoteEPC results (#223378)
ORC Wrapper functions may produce out-of-band error results (e.g. due to
serialization errors), but SimpleRemoteEPC / SimpleRemoteEPCServer never
handled these cases (they incorrectly asserted that they never
appeared).
Update the SimpleRemote protocol to use the TagAddr field (previously
unused for result messages) to encode Result message kinds: either a
Value, or an OutOfBandError. This allows out-of-band errors to flow
across the wire and be passed as results to their callers.
encodeResultMessage and decodeResultMessage implement the format /
handling: out-of-band errors (or failures to deserialize out-of-band
errors) are now passed to handlers as out-of-band error results. An
invalid Result message kind in the TagAddr field results in an
llvm::Error, ending the session.
SimpleRemoteEPCUtilsTest covers both kinds' round-trips, an unrecognized
kind, and a malformed out-of-band payload.
[CIR][AMDGPU] Add support for AMDGCN permlane builtins (#223161)
Adds codegen for the following AMDGCN permlane builtins:
- __builtin_amdgcn_permlane_bcast
- __builtin_amdgcn_permlane_up
- __builtin_amdgcn_permlane_down
- __builtin_amdgcn_permlane_xor
These are lowered to the corresponding `llvm.amdgcn.permlane.*`
intrinsics.
Assisted by: Claude Opus 5
[X86][CodeGen] Support partial-reduce dot products (#205373)
Part of #187779
Lower the llvm.vector.partial.reduce dot product shapes onto the X86 dot
product instructions:
i8 x i8 -> i32: vpdpbusd (AVX512-VNNI, AVX-VNNI)
vpdpbssd / vpdpbuud (AVX-VNNI-INT8, AVX10.2)
i16 x i16 -> i32: vpdpwssd (AVX512-VNNI, AVX-VNNI)
vpdpwsud / vpdpwuud (AVX-VNNI-INT16, AVX10.2)
bf16 x bf16 -> f32: vdpbf16ps (AVX512-BF16)
f16 x f16 -> f32: vdpphps (AVX10.2)
The 128/256-bit shapes, and the 512-bit shapes on targets using 512-bit
registers, are registered as Custom. 512-bit shapes for which only the
VEX
encoding exists are split into two 256-bit dot products, and the
128/256-bit
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[ORC] Use lookupAndApply for EPCGenericRTDyldMemoryManager (#223377)
EPCGenericRTDyldMemoryManager::CreateWithDefaultBootstrapSymbols
resolved its memory-manager and EH-frame symbol addresses with
EPC.getBootstrapSymbols. For consistency, switch to
lookupAndApply/recordAddr on the bootstrap JITDylib instead.
[BOLT][RISCV] Add basic RISC-V initialization support for unit tests (#222883)
This change addresses the uninstantiated test suite failures in
RISC-V-only builds discussed in #217604. That PR proposed a temporary
workaround using GTEST_ALLOW_UNINSTANTIATED_PARAMETERIZED_TEST.
Add the basic setup needed to instantiate and initialize the existing
test suites for riscv64, including the correct ELF machine type and
subtarget features, and remove the temporary allowances.
[Flang][OpenMP] Fix use_device_addr descriptor types (#222961)
Fix invalid FIR for assumed-shape arrays in use_device_addr by using
matching descriptor-reference types and loading the descriptor inside
the region. Added tests.
Co-authored-by: Codex <codex at openai.com>
[libc][Bazel] Add missing F16 math targets (#222937)
Addresses #221799 by adding all existing F16 tests that were missing
Bazel targets.
Validated by running all 184 F16 tests with bazel test.
WebAssembly: Introduce ExceptionHandling::EmscriptenEH model
Add a dedicated EmscriptenEH exception model so the control uses
the standard exception model control, instead of relying on a backend
specific cl::opt. This will later migrate to a module flag and
remove -enable-emscripten-cxx-exceptions
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[RISCV] Don't use VL node when lowering scalable mask reductions
Using ISD::XOR gives us the generic not (setcc cc) -> setcc inverse-cc combine.
Restricted to just scalable vectors since some fixed vector patterns break without the VL node.
The VP test doesn't improve because
1) VP reductions get legalized during regular op legalization, not vector legalization
2) so generic DAGCombines don't get a chance to run before the (splat_vector 1) is legalized to vmset_vl.
We can fix this by keeping the (splat_vector 1) legal, but this is left to another PR.
ARM: Track CPSR liveness in Thumb2SizeReduction without kill flags
Thumb2SizeReduction narrows a 32-bit instruction to its flag-setting
16-bit form only when CPSR is dead afterwards. It determined this from
kill flags on CPSR operands. Kill flags have been semi-deprecated
for over a decade, so avoid relying on them. Liveness should be evaluated
as a reverse walk over a block.
The existing forward walk over the block is still necessary as a separate
step for the different A9 avoidCPSRPartialUpdate optimization.
Co-Authored-By: Claude claude-opus-4.8 <noreply at anthropic.com>
[CIR][X86] Emit cir.clz/cir.ctz for lzcnt/tzcnt builtins (#222669)
These x86 builtins were lowered through cir.call_llvm_intrinsic even
though dedicated CIR bit-count ops already exist.
Assisted-by: grok-4.6
Signed-off-by: Letu Ren <fantasquex at gmail.com>
[clang][bytecode] Improve array index and offset add/sub bounds checks wrt. opaque pointers (#223353)
We were previously causing an assertion since the index had more than 64
bits.
[mlir][dataflow] Deduplicate data-flow solver worklist items (#221983)
The solver enqueues a work item every time a state it depends on
changes, so the same item can appear in the worklist many times.
A duplicate work item is re-processed even though its inputs have not
changed since the previous processing. For example, a dense analysis can
visit a join point with N predecessors up to N times in a row.
To deduplicate the worklist, pending items are tracked using a
`DenseSet`, and an item that is already pending is not pushed again.
Items are removed from the set when dequeued, before being visited, so
an analysis can still re-enqueue the point it is currently visiting.
Since analyses already have to be monotone to reach a fixed point, this
change does not affect analysis results, only the number of visits until
convergence. The test `FooState` used XOR for the join operation, which
is not monotone; the join operation was switched to OR and dependent
tests were updated.
A test that counts how many times a join block with several predecessors
is visited was added to check the deduplication.
[BOLT][RISCV] Support reading RV64 RELR relocations (#222265)
Clang linked with packed relative dynamic relocations aborts when the
RELR reader requests the target relative relocation type. Return
`R_RISCV_RELATIVE` for RV64, preserving the RV32 restriction and other
targets.
Assisted by GPT-6.
[mlir][NVVM] Add packed EX2 operations (#220501)
Add NVVM dialect operations for the public packed EX2 PTX instructions:
* `nvvm.ex2.f16x2` lowers to `ex2.approx.f16x2`
* `nvvm.ex2.bf16x2` lowers to `ex2.approx.ftz.bf16x2`
The existing scalar `nvvm.ex2` operation is unchanged. Includes LLVM IR
translation tests for both overloads.
