LLVM/project db6b186utils/bazel/llvm-project-overlay/mlir BUILD.bazel, utils/bazel/llvm-project-overlay/mlir/test BUILD.bazel

[bazel][[mlir][xegpu] Fix build for #177492 (#178728)

Fix d9c65f94b11f2fed7b78af3a8e7bec6c84bdf219.
DeltaFile
+4-0utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+5-02 files

LLVM/project f951f63flang/include/flang/Optimizer/OpenACC Passes.td, flang/lib/Optimizer/OpenACC/Support FIROpenACCTypeInterfaces.cpp FIROpenACCUtils.cpp

[flang][acc] Add ACCOptimizeFirstprivateMap pass (#178546)

This pass optimizes acc.firstprivate_map operations generated during
OpenACC recipe materialization when acc.firstprivate is materialized
into the mapping and a private allocation inside region. The
optimization applies to scalar variables of trivial types (integers,
reals, logicals) as long as they are not optional.

The pass hoists loads from the firstprivate variable to before the
compute region, converting the firstprivate copy to a pass-by-value
pattern. This eliminates the need for runtime copying the firstprivate
variable since only its value is needed for initializing private copies.
DeltaFile
+241-0flang/test/Transforms/OpenACC/acc-optimize-firstprivate-map.fir
+193-0flang/lib/Optimizer/OpenACC/Transforms/ACCOptimizeFirstprivateMap.cpp
+4-37flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
+35-0flang/lib/Optimizer/OpenACC/Support/FIROpenACCUtils.cpp
+12-0flang/include/flang/Optimizer/OpenACC/Passes.td
+8-0mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
+493-375 files not shown
+515-4011 files

LLVM/project c31e13allvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.groupstaticsize.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for groupstaticsize (#178618)

DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
+1-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+6-53 files

LLVM/project fc2b1e4mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[OpenMP][MLIR] Modify lowering OpenMP Dialect lowering to support attach mapping

This PR adjusts the LLVM-IR lowering to support the new attach map type that the runtime
uses to link data and pointer together, this swaps the mapping from the older
OMP_MAP_PTR_AND_OBJ map type in most cases and allows slightly more complicated ref_ptr/ptee
and attach semantics.
DeltaFile
+292-220mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+292-2201 files

LLVM/project 312d798llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.global.load.tr-w64.ll llvm.amdgcn.global.load.tr-w32.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for global_load_tr_b* (#178545)

DeltaFile
+8-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+2-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
+1-1llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
+12-34 files

LLVM/project ddaf107clang/test/CodeGenHLSL/builtins exp2-overloads.hlsl sinh-overloads.hlsl

[HLSL] Make log10, exp2, sinh overload tests stricter NFC (#177495)

This patch updates log10, exp2, sinh overload tests to use -O1 instead
of -disable-llvm-passes; also, the checks are updated to match the
change accordingly.

This work is part of https://github.com/llvm/llvm-project/issues/138016.
DeltaFile
+104-62clang/test/CodeGenHLSL/builtins/exp2-overloads.hlsl
+105-43clang/test/CodeGenHLSL/builtins/sinh-overloads.hlsl
+104-42clang/test/CodeGenHLSL/builtins/log10-overloads.hlsl
+313-1473 files

LLVM/project eb33585mlir/lib/Dialect/XeGPU/Transforms XeGPUSgToWiDistributeExperimental.cpp

[mlir][xegpu] Remove unused headers added in #177492 (#178719)

Remove unused headers added in #177492
DeltaFile
+0-3mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
+0-31 files

LLVM/project 9eb797ellvm/lib/CodeGen TargetPassConfig.cpp

[CodeGen] Remove -gc-empty-basic-blocks alias flag (#178716)

This was deprecated earlier and switched to an alias so we would have
some time to update things through our internal compiler release
process. That has completed, so we can now remove the flag upstream.
DeltaFile
+0-7llvm/lib/CodeGen/TargetPassConfig.cpp
+0-71 files

LLVM/project cba7dcdllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-amdgcn.struct.ptr.buffer.store.ll regbankselect-amdgcn.struct.buffer.store.ll

[AMDGPU][GlobalISel] Add RegBankLegalize rules for buffer store variants (#178488)

Add rules for G_AMDGPU_BUFFER_STORE, G_AMDGPU_BUFFER_STORE_FORMAT,
G_AMDGPU_BUFFER_STORE_FORMAT_D16, and G_AMDGPU_TBUFFER_STORE_FORMAT.
DeltaFile
+27-31llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
+27-31llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
+27-13llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
+23-12llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
+14-2llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+10-5llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+128-9420 files not shown
+164-12926 files

LLVM/project ea25166llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/test/CodeGen/X86 masked_expandload_isel.ll

[CodeGen] Fix MachineMemOperand Size of MaskedLoad (#156398)

Fix MIR printing unknown-size issue of MaskedLoad.
DeltaFile
+2-2llvm/test/CodeGen/X86/masked_expandload_isel.ll
+1-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+3-32 files

LLVM/project 8302362offload/cmake/caches FlangOffload.cmake, openmp/docs Building.md

[Offload] Provide a cache file for building OpenMP w/ Flang offloading (#178472)

Summary:
This build is more annoying, enables everything required for this
version of the runtime.
DeltaFile
+13-0offload/cmake/caches/FlangOffload.cmake
+2-0openmp/docs/Building.md
+15-02 files

LLVM/project 8513cadllvm/utils profcheck-xfail.txt

[ProfCheck] Add ExpandIRInsts test to profcheck-xfail.txt

There are in-flight patches to fix the remaining ExpandIRInsts failures
that should fix this. Disable for now to get the bot back to green.
DeltaFile
+1-0llvm/utils/profcheck-xfail.txt
+1-01 files

LLVM/project 73dc25clibc/include pthread.yaml, libc/src/pthread pthread_getattr_np.h

[libc] Add pthread_getattr_np declaration (#178549)

Add header declaration and implementation header for the GNU
extension function pthread_getattr_np.  An actual implementation
can come later.
DeltaFile
+21-0libc/src/pthread/pthread_getattr_np.h
+6-0libc/include/pthread.yaml
+27-02 files

LLVM/project 6d27fa7llvm/utils update_analyze_test_checks.py

[NFC][UTC] Avoid copy-paste in `update_analyze_test_checks.py` (#178456)

I'm going to extend it to support VPlan dump tests soon and this cleanup
avoids future growth of the `if/elif/elif` chain.
DeltaFile
+11-19llvm/utils/update_analyze_test_checks.py
+11-191 files

LLVM/project a2fbf87lldb/source/Commands CommandObjectDWIMPrint.cpp

[lldb] Make `print` delegate to synthetic frames.

This patch is more of a proposal in that it's a pretty dramatic change to the way that `print` works. It completely delegates getting values to the frame if the frame is synthetic, and does not redirect at all if the frame fails.

For this patch, the main goal was to allow the synthetic frame to bubble up its own errors in expression evaluation, rather than having errors come back with an extra "could not find identifier <blah>" or worse, simply get swallowed. If there's a better way to handle this, I'm more than happy to change this as long as the core goals of 'delegate variable/value extraction to the synthetic frame', and 'allow the synthetic frame to give back errors that are displayed to the user' can be met.

stack-info: PR: https://github.com/llvm/llvm-project/pull/178602, branch: users/bzcheeseman/stack/7
DeltaFile
+23-2lldb/source/Commands/CommandObjectDWIMPrint.cpp
+23-21 files

LLVM/project 198a272lldb/include/lldb/Interpreter/Interfaces ScriptedFrameInterface.h, lldb/source/Plugins/Process/scripted ScriptedFrame.cpp ScriptedFrame.h

[lldb] Add support for ScriptedFrame to provide values/variables.

This patch adds plumbing to support the implementations of StackFrame::Get{*}Variable{*} on ScriptedFrame. The major pieces required are:
- A modification to ScriptedFrameInterface, so that we can actually call the python methods.
- A corresponding update to the python implementation to call the python methods.
- An implementation in ScriptedFrame that can get the variable list on construction inside ScriptedFrame::Create, and pass that list into the ScriptedFrame so it can get those values on request.

There is a major caveat, which is that if the values from the python side don't have variables attached, right now, they won't be passed into the scripted frame to be stored in the variable list. Future discussions around adding support for 'extended variables' when printing frame variables may create a reason to change the VariableListSP into a ValueObjectListSP, and generate the VariableListSP on the fly, but that should be addressed at a later time.

This patch also adds tests to the frame provider test suite to prove these changes all plumb together correctly.

stack-info: PR: https://github.com/llvm/llvm-project/pull/178575, branch: users/bzcheeseman/stack/6
DeltaFile
+82-0lldb/test/API/functionalities/scripted_frame_provider/test_frame_providers.py
+72-5lldb/source/Plugins/Process/scripted/ScriptedFrame.cpp
+53-0lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py
+29-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedFramePythonInterface.cpp
+20-1lldb/source/Plugins/Process/scripted/ScriptedFrame.h
+11-0lldb/include/lldb/Interpreter/Interfaces/ScriptedFrameInterface.h
+267-62 files not shown
+277-68 files

LLVM/project 116ba6alldb/bindings/python python-wrapper.swig, lldb/include/lldb/API SBValue.h

[lldb] Add conversions for SBValueList and SBValue to the python bridge.

This patch adds support for:
- PyObject -> SBValueList (which was surprisingly not there before!)
- PyObject -> SBValue
- SBValue -> ValueObjectSP using the ScriptInterpreter

These three are the main remaining plumbing changes necessary before we can get to the meat of actually using ScriptedFrame to provide values to the printer/etc. Future patches build off this change in order to allow ScriptedFrames to provide variables and get values for variable expressions.

stack-info: PR: https://github.com/llvm/llvm-project/pull/178574, branch: users/bzcheeseman/stack/5
DeltaFile
+38-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.cpp
+14-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
+12-0lldb/bindings/python/python-wrapper.swig
+10-0lldb/source/Interpreter/ScriptInterpreter.cpp
+3-0lldb/include/lldb/Interpreter/ScriptInterpreter.h
+3-0lldb/include/lldb/API/SBValue.h
+80-01 files not shown
+81-07 files

LLVM/project bb7fed1lldb/include/lldb/API SBValue.h, lldb/include/lldb/ValueObject ValueObject.h

[lldb] Move ValueImpl and ValueLocker to ValueObject, NFC.

This patch moves ValueImpl and ValueLocker to ValueObject.{h,cpp}. This follows the example set in TypeImpl/SBType, where we have something that SBType uses internally that needs to be exposed in the layer below. In this case, SBValue uses ValueImpl, which wraps ValueObject. The wrapper helps avoid bugs, so we want to keep it, but the script interpreter needs to use it and said interpreter is conceptually *below* the SB layer...which means we can't use methods on SBValue.

This patch is purely the code motion part of that, future patches will actually make use of this moved code.

stack-info: PR: https://github.com/llvm/llvm-project/pull/178573, branch: users/bzcheeseman/stack/4
DeltaFile
+0-166lldb/source/API/SBValue.cpp
+91-0lldb/source/ValueObject/ValueObject.cpp
+78-0lldb/include/lldb/ValueObject/ValueObject.h
+3-4lldb/include/lldb/API/SBValue.h
+172-1704 files

LLVM/project d8d4096llvm/include/llvm/CodeGen/GlobalISel CombinerHelper.h, llvm/include/llvm/Target/GlobalISel Combine.td

[GlobalISel] Rewrite binop_left_to_zero using MIR Patterns (#177924)

Following 2d87319f06ef936233ba6aaa612da9586c427d68, this PR rewrites the
`binop_left_to_zero` rule using MIR Patterns.

The new pattern uses `GIReplaceReg` in the apply clause. According to
[MIRPatterns.rst](https://github.com/llvm/llvm-project/blob/5b4a5cf51f37cb42c5e0bdb22b43acde137281c8/llvm/docs/GlobalISel/MIRPatterns.rst?plain=1#L222),
`GIReplaceReg` checks `canReplaceReg`, so the new apply pattern is
equivalent to the old `matchOperandIsZero` implementation.

Added tests for all the opcodes covered by this rule `(G_SHL, G_LSHR,
G_ASHR, G_SDIV, G_UDIV, G_SREM, G_UREM, G_MUL)`.
DeltaFile
+119-0llvm/test/CodeGen/RISCV/GlobalISel/combine.mir
+37-40llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
+8-8llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
+9-5llvm/include/llvm/Target/GlobalISel/Combine.td
+0-7llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+0-3llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+173-636 files

LLVM/project 84c66f4mlir/include/mlir/Dialect/Vector/Transforms VectorRewritePatterns.h, mlir/lib/Dialect/Vector/Transforms VectorEmulateNarrowType.cpp

[mlir][vector] Add assumeAligned mode to vector.store narrow type emulation (#178565)

The revision adds a new `assumeAligned` mode to the emulation, so
downstream projects can use simple path when it meets the requirements.
E.g., if the offset is always aligned with container's element type, we
can skip the check of front padding sizes.

---------

Signed-off-by: hanhanW <hanhan0912 at gmail.com>
DeltaFile
+55-0mlir/test/Dialect/Vector/vector-emulate-narrow-type-aligned-store-only.mlir
+45-4mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
+8-2mlir/test/lib/Dialect/MemRef/TestEmulateNarrowType.cpp
+7-2mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h
+115-84 files

LLVM/project 696ea11llvm/lib/ExecutionEngine/Orc/Debugging ELFDebugObjectPlugin.cpp, llvm/test/ExecutionEngine/JITLink/x86-64 ELF_no_debug_info.s

[ELFDebugObjectPlugin] Do not wait for std::future in post-fixup phase in the absent of debug info (#178541)

If there is no debug information, we wouldn't call
`DebugObject::collectTargetAlloc` in the post-allocation phase.
Therefore, when it's in the post-fixup phase,
`DebugObject::awaitTargetMem` will fail with _"std::future_error: No
associated state"_ because the std::future was not even populated.
DeltaFile
+20-0llvm/test/ExecutionEngine/JITLink/x86-64/ELF_no_debug_info.s
+14-1llvm/lib/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.cpp
+34-12 files

LLVM/project 3222670libcxx/include __split_buffer

[libc++] Fix `__split_buffer_size_layout` bugs (#178341)

As `__split_buffer` doesn't have any unit tests, and because #139632
disassociated adding `__split_buffer` support for both pointer-based and
size-based layouts from its `vector` counterpart, libc++ had no way to
expose `__split_buffer_size_layout` bugs until the size-based vector
patch integrated #139632. This commit fixes the two problems that were
identified while working on #155330.
DeltaFile
+6-16libcxx/include/__split_buffer
+6-161 files

LLVM/project f04b661.github/workflows prune-unused-branches.py prune-branches.yml

[Github] Make prune branches workflow save branch patches

This patch makes the prune branches workflow create patches for the
branches that it is about to prune containing all their changes. These
are then uploaded as a Github artifact with a 90 day experiation just in
case there was something in a branch that someone will later need and is
not available elsewhere.

Reviewers: petrhosek, vbvictor, cmtice

Pull Request: https://github.com/llvm/llvm-project/pull/178539
DeltaFile
+34-1.github/workflows/prune-unused-branches.py
+8-1.github/workflows/prune-branches.yml
+42-22 files

LLVM/project 1f95411llvm/test/CodeGen/SPIRV event-zero-const-64.ll event-zero-const.ll, llvm/test/CodeGen/SPIRV/transcoding spirv-event-null.ll spirv-event-null-64.ll

[SPIRV] Split async copy tests and fix invalid tests

After a spirv-val update, tests that mix spirv32 and spirv64 targets with
the same LLVM IR are now correctly flagged as invalid. The SPIR-V
specification requires that NumElements and Stride operands in
OpGroupAsyncCopy must be 32-bit integers when the addressing model is
Physical32, and 64-bit integers for Physical64.
DeltaFile
+55-52llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
+101-0llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null-64.ll
+38-0llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided-64.ll
+16-15llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided.ll
+27-0llvm/test/CodeGen/SPIRV/event-zero-const-64.ll
+6-6llvm/test/CodeGen/SPIRV/event-zero-const.ll
+243-736 files

LLVM/project 40006a7llvm/utils/gn/secondary/clang/lib/Analysis/Scalable BUILD.gn

[gn build] Port 69c0f929e065
DeltaFile
+1-0llvm/utils/gn/secondary/clang/lib/Analysis/Scalable/BUILD.gn
+1-01 files

LLVM/project d9c65f9mlir/lib/Dialect/XeGPU/Transforms XeGPUSgToWiDistributeExperimental.cpp XeGPUSubgroupDistribute.cpp, mlir/lib/Dialect/XeGPU/Utils XeGPUUtils.cpp

[mlir][xegpu] Add `XeGPUSgToWiDistributeExperimental` pass.  (#177492)

Currently XeGPU lowering pipeline uses `XeGPUSubgroupDistribute` pass to
subgroup to work item distribution of ops. This pass is well established
and relies on vector distribution's `WarpOp` based distribution
mechanism. However, recent experiments with larger kernels have shown
that this pass is very expensive in terms of compile time (see below).

This prompted us to create a new pass that does not rely on `WarpOp`
based distribution. This PR adds the initial infra to move away from the
old way and align Wg To WI distribution with Wg to Sg distribution. New
pass also uses context-aware type conversion based on XeGPU layouts to
distributed vector types from SG to WI.

This PR adds the following changes:
* SG to WI distribution pass based on context-aware type conversions
using `OpConversionPatterns`
* Test pass for testing individual patterns
(`TestXeGPUSgToWiDistributeExperimental`)

    [32 lines not shown]
DeltaFile
+561-0mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
+219-0mlir/test/Dialect/XeGPU/sg-to-wi-experimental.mlir
+152-0mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+3-73mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+59-0mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
+56-1mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
+1,050-744 files not shown
+1,099-7410 files

LLVM/project 243f011mlir/docs ReleaseNotes.md, mlir/include/mlir/Dialect/GPU/Pipelines Passes.h

[mlir][GPU|NVVM] Update the default SM to 7.5  (#177469)

Update MLIR's default SM to `sm_75`. This matches the behavior of
offline compilation tools in the CUDA Toolkit (`nvcc`, `ptxas`, ...) and
follows suit with 9fc5fd0ad689eed94f65b1d6d10f9c5642935e68.

Additionally, `sm_75` is the oldest GPU variant compatible with the
widest range of recent major CUDA Toolkit versions (11/12/13).
DeltaFile
+9-0mlir/docs/ReleaseNotes.md
+2-2mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+1-1mlir/include/mlir/Dialect/GPU/Pipelines/Passes.h
+1-1mlir/include/mlir/Dialect/GPU/Transforms/Passes.td
+13-44 files

LLVM/project caae29cmlir/include/mlir/IR OpAsmDialectInterface.td OpImplementation.h, mlir/lib/TableGen Interfaces.cpp

[MLIR] convert OpAsmDialectInterface using ODS (#171488)

This PR converts OpAsmDialectInterface using ODS.

It also introduces a new Interface Method class `InterfaceMethodDeclaration` which will declare the function without definition.
DeltaFile
+80-0mlir/include/mlir/IR/OpAsmDialectInterface.td
+7-58mlir/include/mlir/IR/OpImplementation.h
+37-27mlir/test/mlir-tblgen/dialect-interface.td
+26-8mlir/tools/mlir-tblgen/DialectInterfacesGen.cpp
+11-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+6-0mlir/lib/TableGen/Interfaces.cpp
+167-934 files not shown
+181-9310 files

LLVM/project f3ecf49.github new-prs-labeler.yml

[GitHub] add MemoryTaggingSupport.cpp in sanitizer (#178705)

DeltaFile
+2-1.github/new-prs-labeler.yml
+2-11 files

LLVM/project 9377c1dmlir/include/mlir/Dialect/SPIRV/IR SPIRVBase.td SPIRVNonUniformOps.td, mlir/test/Dialect/SPIRV/IR non-uniform-ops.mlir

[mlir][spirv] Enforce `GroupNonUniformQuadSwap` direction values using an attribute (#178684)

The direction can only take one of the three values {0, 1, 2} so we use
a SPIR-V attribute to enforce it. This property cannot be enforced when
the direction is a constant value as the verifier cannot test for
non-local properties.
DeltaFile
+13-13mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
+4-6mlir/test/Target/SPIRV/non-uniform-ops.mlir
+9-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+4-4mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td
+1-0mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
+31-235 files