LLVM/project 77208d8clang/test/OpenMP parallel_for_codegen.cpp, libc/utils cmake_format.py

Rebase

Created using spr 1.3.7
DeltaFile
+1,004-1,744llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
+1,049-1,049clang/test/OpenMP/parallel_for_codegen.cpp
+892-872llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
+889-668llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1,534-0libc/utils/cmake_format.py
+642-878llvm/test/CodeGen/X86/clmul-vector.ll
+6,010-5,2111,218 files not shown
+51,212-30,5001,224 files

LLVM/project cc4c418clang/test/OpenMP interchange_codegen.cpp, llvm/lib/Target/Hexagon HexagonDepMask.h

Rebase

Created using spr 1.3.7
DeltaFile
+17,282-3,458llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-sve-instructions.s
+7,983-1,591llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-neon-instructions.s
+1,750-2,445clang/test/OpenMP/interchange_codegen.cpp
+3,312-825llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+2,226-1,164llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+0-2,819llvm/lib/Target/Hexagon/HexagonDepMask.h
+32,553-12,3023,830 files not shown
+203,703-95,7613,836 files

LLVM/project 3e149a5llvm/test/CodeGen/AMDGPU/GlobalISel regbankcombiner-merge-readanylane.mir regbankcombiner-smed3.mir

comments
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir
+5-53 files

LLVM/project 54b2840llvm/lib/Target/AMDGPU AMDGPUPassRegistry.def AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankcombiner-smed3.mir regbankcombiner-clamp-fmed3-const.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankCombiner" to NPM
DeltaFile
+81-32llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+13-2llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-2llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+2-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
+2-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
+101-381 files not shown
+102-387 files

LLVM/project f98f858llvm/lib/Target/AMDGPU AMDGPUPassRegistry.def AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-mui.mir regbankselect-load.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankLegalize" to NPM
DeltaFile
+50-17llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+21-3llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+3-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+1-1llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+1-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+78-231 files not shown
+79-237 files

LLVM/project 809dee0llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPU.h

comments
DeltaFile
+18-25llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+3-3llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+23-303 files

LLVM/project 69abec4clang/test/OpenMP interchange_codegen.cpp, llvm/lib/Target/Hexagon HexagonDepMask.h

Rebase

Created using spr 1.3.7
DeltaFile
+17,282-3,458llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-sve-instructions.s
+7,983-1,591llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-neon-instructions.s
+1,750-2,445clang/test/OpenMP/interchange_codegen.cpp
+3,312-825llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+2,226-1,164llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+0-2,819llvm/lib/Target/Hexagon/HexagonDepMask.h
+32,553-12,3023,573 files not shown
+193,950-93,7293,579 files

LLVM/project 271af38llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPUPassRegistry.def, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-mui-regbankselect.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankSelect" to NPM (#217321)

Assisted-by: Opus-4.8
DeltaFile
+43-15llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
+18-3llvm/lib/Target/AMDGPU/AMDGPU.h
+3-2llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
+67-225 files

LLVM/project b1a72e3utils/bazel/llvm-project-overlay/libc BUILD.bazel

[Bazel] Fixes e92c19a (#221761)

This fixes e92c19abae25beb03234bfbf6cfa1a431c6d380a (#221236).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=e92c19abae25beb03234bfbf6cfa1a431c6d380a

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+5-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+5-01 files

LLVM/project c5fc983llvm/test/CodeGen/X86 pr1505b.ll

[X86] pr1505b.ll - regenerate test checks (#221774)
DeltaFile
+39-17llvm/test/CodeGen/X86/pr1505b.ll
+39-171 files

LLVM/project ead188allvm/lib/Target/AArch64 AArch64.td AArch64ValidateRetiredNames.td, llvm/test/TableGen aarch64-retired-names.td

[AArch64] Prevent reuse of retired architecture names

Add explicit lists of retired AArch64 feature and system register names,
with TableGen validation preventing future definitions from reusing them.

This preserves names previously exposed by LLVM after their architectural
features or registers have been withdrawn or removed. Add coverage for
target features, architecture extension names and aliases, architectural
FEAT_* names, and system registers.
DeltaFile
+43-0llvm/test/TableGen/aarch64-retired-names.td
+37-0llvm/lib/Target/AArch64/AArch64ValidateRetiredNames.td
+12-0llvm/lib/Target/AArch64/AArch64.td
+92-03 files

LLVM/project 1afead7llvm/lib/CodeGen RegAllocPBQP.cpp, llvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp

Revert "[CodeGen] Use RegisterClassInfo for remaining allocation-order users" (#221749)

Reverts llvm/llvm-project#216510

breaks tests MIOpen/CK shard 1-4 in CI

queueing this up in case we want to save a bit of time
DeltaFile
+23-20llvm/lib/CodeGen/RegAllocPBQP.cpp
+16-19llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+8-10llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+47-493 files

LLVM/project ce27ca4llvm/test/Analysis/ScalarEvolution incorrect-nsw.ll ext-addrec-wrap-flags.ll

[SCEV] Add test coverage for ext-nusw/nsuw inference (#218943)

Complete the existing incorrect-nsw test, showing that zext-addrec nusw
is not implied by nw on the pre-inc AR, and that sext-addrec nsuw is not
implied by nw on the pre-inc AR. See also: #217405 and #217362.

Assisted-by: AI
DeltaFile
+389-0llvm/test/Analysis/ScalarEvolution/ext-addrec-wrap-flags.ll
+0-26llvm/test/Analysis/ScalarEvolution/incorrect-nsw.ll
+389-262 files

LLVM/project fd4549aoffload/libomptarget omptarget.cpp, offload/plugins-nextgen/common/include PluginInterface.h

[offload][omp] Remove data_fence

All supported backends execute enqueued work on a given queue in
submission order (CUDA, AMDGPU, and Host queues are always in-order;
Level Zero's default and non-default in-order/synchronous command
modes are as well), so the explicit data-fence used to order a
pointer-attachment after prior data transfers is unnecessary. Remove
the DeviceTy/GenericDeviceTy/GenericPluginTy dataFence chain and the
now-unused olQueueBarrier liboffload API added to support it.
DeltaFile
+4-17offload/libomptarget/omptarget.cpp
+0-12offload/plugins-nextgen/common/src/PluginInterface.cpp
+0-8offload/plugins-nextgen/level_zero/src/L0Device.cpp
+0-8offload/plugins-nextgen/common/include/PluginInterface.h
+0-7offload/plugins-nextgen/host/src/rtl.cpp
+0-7offload/plugins-nextgen/cuda/src/rtl.cpp
+4-595 files not shown
+4-7611 files

LLVM/project 1ce91bbllvm/lib/Transforms/Utils SimplifyCFG.cpp, llvm/test/Transforms/SimplifyCFG preserve-unpredictable-switch-create.ll

[SimplifyCFG] Preserve !unpredictable when forming a switch (#221580)

SimplifyCFG turns a chain of equality comparisons into a switch in two
places, performValueComparisonIntoPredecessorFolding() and
simplifyBranchOnICmpChain(), and neither propagated !unpredictable. The
hint was therefore dropped even though it is valid on a switch and the
reverse transform, simplifySwitchOfCmpIntrinsic(), already preserves it.

Propagate the metadata in both. Folding a comparison into a predecessor
merges two decisions into a single switch, so the result is only marked
unpredictable when both of the folded comparisons were. That also makes
chains longer than two blocks work: the fold runs once per predecessor
and reads the metadata back off the switch it built on the previous
iteration.

simplifyBranchOnICmpChain() also emits a range check instead of a switch
when the case values are contiguous. That branch is an exact replacement
for the original one, so it inherits the metadata unconditionally, and
the flag now survives into the machine IR.

Fixes #42658.
DeltaFile
+180-0llvm/test/Transforms/SimplifyCFG/preserve-unpredictable-switch-create.ll
+10-0llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+190-02 files

LLVM/project 068a7cfoffload/liboffload exports, offload/liboffload/API Queue.td

[offload][omp] Manage data fence through liboffload
DeltaFile
+14-0offload/liboffload/API/Queue.td
+0-12offload/plugins-nextgen/common/src/PluginInterface.cpp
+8-0offload/liboffload/src/OffloadImpl.cpp
+5-1offload/libompaccsupport/device.cpp
+0-4offload/plugins-nextgen/common/include/PluginInterface.h
+0-1offload/liboffload/exports
+27-186 files

LLVM/project 01f5d4eoffload/include device.h, offload/liboffload exports

[offload][omp] Manage events through liboffload
DeltaFile
+0-73offload/plugins-nextgen/common/src/PluginInterface.cpp
+35-18offload/libompaccsupport/device.cpp
+0-21offload/plugins-nextgen/common/include/PluginInterface.h
+4-5offload/include/device.h
+0-5offload/liboffload/exports
+39-1225 files

LLVM/project f17a6bcllvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h

[SPIRV] Preserve DebugGlobalVariable emission order.

Iterate GlobalVariableDebugInfoMap with MapVector so OpString and
DebugGlobalVariable follow insertion order.
DeltaFile
+1-1llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+1-11 files

LLVM/project 10a3788llvm/lib/Target/RISCV RISCVInstrInfoZvdot4a8i.td RISCVInstrInfoVVLPatterns.td

[RISCV] Add VPatBinaryVL_R_VX to share between VRSUB.VX and VDOT4AUS.VX. NFC (#221284)

Assisted-by: Claude
DeltaFile
+27-8llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+1-11llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td
+28-192 files

LLVM/project ca03587llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h

Add missing comment.
DeltaFile
+4-0llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+4-01 files

LLVM/project 0dce2e9llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h SPIRVNonSemanticDebugHandler.cpp, llvm/test/CodeGen/SPIRV/debug-info debug-scope-no-scope-block.ll

[reviews] Simplify code and add new test to prevent future regressions.
DeltaFile
+62-0llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope-block.ll
+12-8llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+0-1llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+74-93 files

LLVM/project 35b967coffload/libompaccsupport PluginManager.cpp device.cpp, offload/libomptarget omptarget.cpp

[offload][omp] memory operations through liboffload
DeltaFile
+0-90offload/plugins-nextgen/common/src/PluginInterface.cpp
+68-16offload/libompaccsupport/device.cpp
+43-4offload/libompaccsupport/PluginManager.cpp
+12-24offload/libomptarget/OpenMP/API.cpp
+0-31offload/plugins-nextgen/common/include/PluginInterface.h
+25-4offload/libomptarget/omptarget.cpp
+148-1696 files not shown
+181-18512 files

LLVM/project 40e054doffload/include PluginManager.h, offload/liboffload exports

[offload][omp] Use olIterateCompatibleDevices for device init and image registration
DeltaFile
+119-109offload/libompaccsupport/PluginManager.cpp
+9-8offload/libompaccsupport/device.cpp
+0-15offload/plugins-nextgen/common/src/PluginInterface.cpp
+5-8offload/include/PluginManager.h
+0-6offload/plugins-nextgen/common/include/PluginInterface.h
+1-4offload/liboffload/exports
+134-1502 files not shown
+142-1518 files

LLVM/project 9313f07offload/liboffload/API Program.td, offload/liboffload/src OffloadImpl.cpp

[OFFLOAD] Add olIterateCompatibleDevices API
DeltaFile
+73-0offload/unittests/OffloadAPI/program/olIterateCompatibleDevices.cpp
+26-0offload/liboffload/src/OffloadImpl.cpp
+15-0offload/liboffload/API/Program.td
+1-0offload/unittests/OffloadAPI/CMakeLists.txt
+115-04 files

LLVM/project 08881a0offload/include PluginManager.h, offload/liboffload exports

[offload][omp] Load plugins through liboffload
DeltaFile
+15-11offload/libompaccsupport/PluginManager.cpp
+5-0offload/liboffload/src/OffloadImpl.cpp
+2-1offload/include/PluginManager.h
+1-1offload/liboffload/exports
+23-134 files

LLVM/project d97f21boffload/liboffload/src OffloadImpl.cpp

[offload] lazily load liboffload
DeltaFile
+242-90offload/liboffload/src/OffloadImpl.cpp
+242-901 files

LLVM/project 8bc2b2foffload/liboffload/API Platform.td, offload/liboffload/src OffloadImpl.cpp

[OFFLOAD] add olIteratePlatforms
DeltaFile
+45-0offload/unittests/OffloadAPI/platform/olIteratePlatforms.cpp
+23-0offload/liboffload/API/Platform.td
+11-0offload/liboffload/src/OffloadImpl.cpp
+79-03 files

LLVM/project 72d6236offload/liboffload exports, offload/liboffload/src OffloadImpl.cpp

[offload][omp] link libomptarget against liboffload
DeltaFile
+58-0offload/liboffload/exports
+9-3offload/liboffload/src/OffloadImpl.cpp
+5-5offload/libomptarget/CMakeLists.txt
+6-0offload/libomptarget/exports
+3-0offload/libomptarget/interface.cpp
+81-85 files

LLVM/project dd3fe03llvm/lib/Target/AMDGPU AMDGPUAnnotateUniformValues.cpp, llvm/test/CodeGen/AMDGPU move-to-valu-pseudo-scalar-trans.ll move-to-valu-pseudo-scalar-trans-f16-true16.ll

Don't infer noclobber for volatile accesses.
DeltaFile
+9-9llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
+7-7llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
+5-5llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
+5-5llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
+5-5llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
+4-4llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
+35-351 files not shown
+36-367 files

LLVM/project e92c19alibc/src/__support/CPP algorithm.h, libc/src/__support/CPP/utility swap.h

[libc] Add cpp::swap and cpp::clamp utilities (#221236)

Added cpp::swap to src/__support/CPP/utility/swap.h with move semantics
and array support, and cpp::clamp to src/__support/CPP/algorithm.h with
comparator support.

Included unit tests in swap_test.cpp and algorithm_test.cpp.

Adopted the new utilities in initial callsites:
* stdlib: Used cpp::swap in qsort_data.h
* wctype: Used cpp::swap in perfect_hash_map.h
* math: Used cpp::clamp in powf.h
* scanf_core: Used cpp::min and cpp::max in parser.h

Also fixed sign extension when parsing scanset specifiers in parser.h:
signed characters greater than or equal to 128 produced negative values,
inverting comparisons and causing out-of-bounds writes in the bitset.
Scanset characters are now cast through uint8_t, and non-ASCII tests
were added to parser_test.cpp.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+117-0libc/test/src/__support/CPP/swap_test.cpp
+50-1libc/test/src/stdio/scanf_core/parser_test.cpp
+45-1libc/test/src/__support/CPP/algorithm_test.cpp
+39-0libc/src/__support/CPP/utility/swap.h
+13-8libc/src/stdio/scanf_core/parser.h
+16-3libc/src/__support/CPP/algorithm.h
+280-1310 files not shown
+332-3016 files