LLVM/project 899c261.github/workflows build-ci-container-tooling.yml

[Github] Rename CI Tooling Containers to 26.04 (#224447)

697570d3ca9f99cc30662fc80fd0beb1b715e478 made them actually use Ubuntu
26.04, but I forgot to rename them. Do that in this commit. Everything
is hash pinned so nothing should break even if there are real issues.
DeltaFile
+1-1.github/workflows/build-ci-container-tooling.yml
+1-11 files

LLVM/project 797dfd0llvm/include/llvm/Analysis TargetTransformInfoImpl.h TargetTransformInfo.h, llvm/lib/Analysis TargetTransformInfo.cpp

Revert "[SLP] More accurately cost RISCV scalar splats" (#224426)

Reverts llvm/llvm-project#213104
DeltaFile
+55-133llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+6-42llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+31-11llvm/test/Transforms/SLPVectorizer/RISCV/check-node-without-vector-user.ll
+2-29llvm/include/llvm/Analysis/TargetTransformInfo.h
+3-18llvm/lib/Analysis/TargetTransformInfo.cpp
+5-14llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+102-24723 files not shown
+176-34029 files

LLVM/project 36620f3clang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareExchangeFloatBitwise builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project 87e7118clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareExchangeFloatBitwise coverage to the texture test
DeltaFile
+5-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+5-01 files

LLVM/project d678dc0clang/test/CodeGenHLSL/builtins RWBuffer-Interlocked.hlsl RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl, clang/test/SemaHLSL/BuiltIns ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl InterlockedCompareExchangeFloatBitwise-errors.hlsl

First attempt implementing InterlockedCompareExchangeFloatBitwise



DeltaFile
+119-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchangeFloatBitwise-errors.hlsl
+43-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchangeFloatBitwise.hlsl
+42-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl
+32-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+25-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+10-0clang/test/CodeGenHLSL/builtins/RWBuffer-Interlocked.hlsl
+271-05 files not shown
+298-311 files

LLVM/project a610a1dclang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareStoreFloatBitwise builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project f648f6cclang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareStoreFloatBitwise coverage to the texture test
DeltaFile
+7-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+7-01 files

LLVM/project fc74b2bclang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl InterlockedCompareStoreFloatBitwise.hlsl

First attempt implementing InterlockedCompareStoreFloatBitwise



DeltaFile
+100-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
+39-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
+35-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
+30-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
+27-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
+16-6clang/lib/Sema/SemaHLSL.cpp
+247-66 files not shown
+311-1012 files

LLVM/project 77d897fclang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareExchange builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project b1b2653clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareExchange coverage to the texture test
DeltaFile
+5-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+5-01 files

LLVM/project 81f5cc4clang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareStore builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project 4e70187clang/lib/Sema HLSLExternalSemaSource.cpp SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl RWByteAddressBuffer-InterlockedCompareExchange.hlsl

First attempt implementing InterlockedCompareExchange



DeltaFile
+93-81clang/lib/Sema/SemaHLSL.cpp
+113-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchange-errors.hlsl
+70-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchange.hlsl
+41-24clang/lib/Sema/HLSLExternalSemaSource.cpp
+44-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchange.hlsl
+35-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchange.hlsl
+396-1056 files not shown
+480-12212 files

LLVM/project 65d1a5cflang/lib/Optimizer/OpenACC/Support FIROpenACCUtils.cpp, flang/test/Transforms/OpenACC acc-implicit-routine.fir

[mlir][OpenACC] Error on external calls without acc routine info (#223815)

Implicit routine can only be applied to procedures defined in the
current compilation unit. Diagnose external callees in compute regions
and existing routines, and treat Fortran intrinsics and `BIND(C)`
procedures as valid device symbols.
DeltaFile
+149-0flang/test/Transforms/OpenACC/acc-implicit-routine.fir
+44-10mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitRoutine.cpp
+45-1mlir/test/Dialect/OpenACC/acc-implicit-routine.mlir
+7-0flang/lib/Optimizer/OpenACC/Support/FIROpenACCUtils.cpp
+245-114 files

LLVM/project 08c8722clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Sema HLSLExternalSemaSource.cpp

First attempt implementing InterlockedCompareStore
DeltaFile
+88-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStore-errors.hlsl
+54-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStore.hlsl
+45-7clang/lib/Sema/HLSLExternalSemaSource.cpp
+29-7clang/lib/CodeGen/CGHLSLBuiltins.cpp
+36-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStore.hlsl
+33-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStore.ll
+285-147 files not shown
+393-1613 files

LLVM/project 77e6345clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareStore coverage to the texture test
DeltaFile
+13-8clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+13-81 files

LLVM/project 2d2a68fclang/include/clang/Basic Builtins.td, clang/lib/Sema HLSLBuiltinTypeDeclBuilder.cpp

Remove comments on the float InterlockedExchange declarations
DeltaFile
+0-3clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+0-1clang/include/clang/Basic/Builtins.td
+0-42 files

LLVM/project 40762f3llvm/lib/Object GOFFObjectFile.cpp

Revert "[GOFFObjectFile] replace snprintf with formatv (#224435)" (#224444)

This reverts commit c60745d126c6d521f76e1a6d81a732d53f4b5ad2.
DeltaFile
+3-2llvm/lib/Object/GOFFObjectFile.cpp
+3-21 files

LLVM/project a883d10llvm/lib/Object GOFFObjectFile.cpp

[GOFF] Add missing include (#224441)

Caused by #224435
DeltaFile
+1-0llvm/lib/Object/GOFFObjectFile.cpp
+1-01 files

LLVM/project 3d88c0elldb/examples/python formatter_bytecode.py, lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode RigidArrayLLDBFormatterSwift.txt RigidArrayLLDBFormatterC.txt

[lldb] Add APSInt literal support to formatter_bytecode.py (#223805)

Follow up to #220665.
DeltaFile
+13-4lldb/examples/python/formatter_bytecode.py
+3-3lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterSwift.txt
+3-3lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterC.txt
+19-103 files

LLVM/project 697570d.github/workflows/containers/github-action-ci-tooling Dockerfile, llvm/utils/git requirements_linting.txt

[Github] Bump tooling containers to 26.04 (#224052)

Mainly to pull in a new CMake version.
DeltaFile
+478-308llvm/utils/git/requirements_linting.txt
+6-6.github/workflows/containers/github-action-ci-tooling/Dockerfile
+484-3142 files

LLVM/project 901629dclang/include/clang/CIR/Dialect/IR CIRDialect.td

[CIR][NFC] Keep getMemoryEffectsAttrName on one line

Assisted-by: Cursor / claude-opus-5
DeltaFile
+1-3clang/include/clang/CIR/Dialect/IR/CIRDialect.td
+1-31 files

LLVM/project cd02433llvm/lib/Target/RISCV RISCVInstrInfo.cpp

[RISCV] Add OPERAND_UIMM4_PLUS1 to RISCVInstrInfo::verifyInstruction (#224423)
DeltaFile
+3-0llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+3-01 files

LLVM/project fcb28f9llvm/lib/Target/AMDGPU AMDGPUAttributor.cpp, llvm/test/CodeGen/AMDGPU annotate-kernel-features-hsa-call.ll amdgpu-attributor-min-agpr-alloc.ll

Check for async operations through attributor
DeltaFile
+496-176llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
+286-0llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-async.ll
+112-80llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+90-88llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll
+97-1llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+31-30llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
+1,112-37535 files not shown
+1,311-53141 files

LLVM/project c60745dllvm/lib/Object GOFFObjectFile.cpp

[GOFFObjectFile] replace snprintf with formatv (#224435)

Use formatv instead of snprintf
DeltaFile
+2-3llvm/lib/Object/GOFFObjectFile.cpp
+2-31 files

LLVM/project c7f362allvm/lib/Target/AMDGPU AMDGPUTargetParser.td, llvm/test/TableGen AMDGPUTargetDefErrors.td AMDGPUTargetDefGenericFeatures.td

[AMDGPU][NFC] Allow selected generic features on any covered GPU

Add AMDGPUGenericAnyFeature so individual feature classes can require
support from at least one covered GPU. Check explicitly marked features
even when they are not frontend-visible, while retaining the all-member
check for ordinary frontend-visible features.

Follow implied features using their own validation rules. Require named
generic targets to cover at least one concrete AMDGPU GPU, rejecting self
references, other generic targets, pseudo targets, and invalid members.

Cover partial support, missing support, exact numeric-feature membership,
backend-only features, implications, and malformed coverage lists with
TableGen tests. Generated target definitions remain unchanged.

Change-Id: Id6ff521e92750a953be54dcc89d98e1b94eb16e2
DeltaFile
+166-0llvm/test/TableGen/AMDGPUTargetDefGenericFeatures.td
+38-17llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+14-5llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
+1-1llvm/test/TableGen/AMDGPUTargetDefErrors.td
+219-234 files

LLVM/project ec6255dllvm/lib/Target/AMDGPU GCNHazardRecognizer.h GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU vperm-pk16-postmisched-hazard.mir vperm-pk16-sched-softcost.mir

[AMDGPU] Prefer a safe V_PERM_PK16 follower in the scheduler (gfx1250)

Stacked on the post-RA V_PERM_PK16 hazard fixup. V_PERM_PK16 must be
immediately followed by a "safe" instruction (see
SIInstrInfo::isVPermPk16SafeInstr) or the post-RA fixup has to insert a
forced-EXEC V_NOP. Teach GCNHazardRecognizer to bias a safe follower into
the slot right after a V_PERM_PK16 so that V_NOP can be avoided.

Assisted-by: Opus 4.8 Medium
DeltaFile
+56-0llvm/test/CodeGen/AMDGPU/vperm-pk16-sched-softcost.mir
+46-3llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+33-0llvm/test/CodeGen/AMDGPU/vperm-pk16-postmisched-hazard.mir
+21-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+156-34 files

LLVM/project a7ecfe5llvm/include/llvm/Analysis TargetTransformInfoImpl.h TargetTransformInfo.h, llvm/lib/Analysis TargetTransformInfo.cpp

Revert "[SLP] More accurately cost RISCV scalar splats (#213104)"

This reverts commit bb9a57a70d35e36d4c8258cc9a15e5c29041d0d7.
DeltaFile
+55-133llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+6-42llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+31-11llvm/test/Transforms/SLPVectorizer/RISCV/check-node-without-vector-user.ll
+2-29llvm/include/llvm/Analysis/TargetTransformInfo.h
+3-18llvm/lib/Analysis/TargetTransformInfo.cpp
+5-14llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+102-24723 files not shown
+176-34029 files

LLVM/project 877ee5fllvm/lib/Target/DirectX DXILIntrinsicExpansion.cpp, llvm/test/CodeGen/DirectX RawBufferStoreDouble.ll

[DirectX] Fix DXIL expansion of 64-bit ByteAddressBuffer stores (#224136)

Fixes #223558

In llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp we were not doing
Create add with the byte index offsets because were were looking at the
wrong argument.

- Fixes DXIL expansion of 64-bit ByteAddressBuffer stores by advancing
the byte index instead of the poison offset.
- Adds regression coverage for wide double stores with offsets confirmed
as 0, 16, 32, 48.
DeltaFile
+26-0llvm/test/CodeGen/DirectX/RawBufferStoreDouble.ll
+22-0llvm/test/CodeGen/DirectX/ResourceAccess/store-rawbuffer-wide-double.ll
+5-1llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
+53-13 files

LLVM/project 953f86dclang/test/SemaHLSL/BuiltIns InterlockedExchange-errors.hlsl ByteAddressBuffer-InterlockedExchangeFloat-sm60.hlsl, llvm/lib/Target/DirectX DXILResourceAccess.cpp DXILLegalizePass.cpp

First attempt implementing float InterlockedExchange
DeltaFile
+40-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedExchangeFloat-sm60.hlsl
+39-0llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat.ll
+38-0llvm/test/CodeGen/DirectX/ResourceAtomicExchangeFloat.ll
+21-14clang/test/SemaHLSL/BuiltIns/InterlockedExchange-errors.hlsl
+29-0llvm/lib/Target/DirectX/DXILLegalizePass.cpp
+17-3llvm/lib/Target/DirectX/DXILResourceAccess.cpp
+184-178 files not shown
+246-2814 files

LLVM/project f721d81clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add float InterlockedExchange coverage to the texture test
DeltaFile
+7-1clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+7-11 files