LLVM/project f417676llvm/test/CodeGen/AMDGPU llvm.amdgcn.raw.atomic.buffer.load.ll llvm.amdgcn.raw.ptr.atomic.buffer.load.ll, llvm/test/CodeGen/AMDGPU/GlobalISel icmp.ll fcmp.ll

[AMDGPU] Add regbankselect rules for G_ICMP/G_FCMP (#172048)

- Legalize G_ICMP for S16, S32, S64, Ptr32 and Ptr64 operands.
- Legalize G_FCMP for S16, S32 and S64 operands.
DeltaFile
+1,516-0llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
+1,241-0llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
+312-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
+312-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
+63-24llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
+63-24llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
+3,507-482 files not shown
+3,594-958 files

LLVM/project b931e9cllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

Address comments
DeltaFile
+5-5llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+5-51 files

LLVM/project 8e00be6llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

Update for inferFastMathValueFlagsBinOp removal
DeltaFile
+1-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+1-11 files

LLVM/project f3a8554llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-fma.ll

InstCombine: Implement SimplifyDemandedFPClass for fma

This can't do much filtering on the sources, except for nans.
We can also attempt to introduce ninf/nnan.
DeltaFile
+65-14llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+16-31llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll
+81-452 files

LLVM/project ffe0e46llvm/test/Transforms/InstCombine simplify-demanded-fpclass-fma.ll

InstCombine: Add baseline fma tests for SimplifyDemandedFPClass
DeltaFile
+316-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll
+316-01 files

LLVM/project ef48383llvm/lib/Support KnownFPClass.cpp, llvm/test/Transforms/Attributor nofpclass-fma.ll

Can't prove -0 for fma
DeltaFile
+24-24llvm/test/Transforms/Attributor/nofpclass-fma.ll
+21-6llvm/lib/Support/KnownFPClass.cpp
+45-302 files

LLVM/project f980e41llvm/lib/Analysis ValueTracking.cpp, llvm/lib/Support KnownFPClass.cpp

ValueTracking: Improve nan tracking for fma square special case

In the square multiply case, we can infer if the add of opposite
sign infinities can occur.
DeltaFile
+11-1llvm/lib/Support/KnownFPClass.cpp
+4-0llvm/lib/Analysis/ValueTracking.cpp
+2-2llvm/test/Transforms/Attributor/nofpclass-fma.ll
+17-33 files

LLVM/project 2f3996bllvm/lib/Analysis ValueTracking.cpp

Fix regression
DeltaFile
+1-5llvm/lib/Analysis/ValueTracking.cpp
+1-51 files

LLVM/project 675078ellvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

ValueTracking: Improve handling for fma/fmuladd

The handling for fma was very basic and only handled the
repeated input case. Re-use the fmul and fadd handling for more
accurate sign bit and nan handling.
DeltaFile
+40-40llvm/test/Transforms/Attributor/nofpclass-fma.ll
+34-12llvm/lib/Analysis/ValueTracking.cpp
+13-0llvm/lib/Support/KnownFPClass.cpp
+11-0llvm/include/llvm/Support/KnownFPClass.h
+98-524 files

LLVM/project 615f5e8llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-maximum.ll simplify-demanded-fpclass-maximumnum.ll

InstCombine: Handle multiple uses for min/max in SimplifyDemandedFPClass
DeltaFile
+127-91llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+4-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+4-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+4-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+4-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+143-1075 files

LLVM/project 86ca793llvm/test/Transforms/Attributor nofpclass-fma.ll

ValueTracking: Add baseline tests for improved fma handling

Improved signbit and not-nan tracking.
DeltaFile
+388-0llvm/test/Transforms/Attributor/nofpclass-fma.ll
+388-01 files

LLVM/project 4bff3e7llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-minimum.ll simplify-demanded-fpclass-minimumnum.ll

InstCombine: Improve SimplifyDemandedFPClass min/max handling

Refine handling of minimum/maximum and minimumnum/maximumnum. The
previous folds to input were based on sign bit checks. This was too
conservative with 0s. This can now consider -0 as less than or equal
to +0 as appropriate, account for nsz. It additionally can handle
cases like one half is known positive normal and the other subnormal.
DeltaFile
+32-61llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+23-58llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+22-52llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+23-46llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+22-44llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+122-2615 files

LLVM/project c55f690llvm/test/Transforms/InstCombine simplify-demanded-fpclass-maximum.ll simplify-demanded-fpclass-minimum.ll

InstCombine: Add more tests for min/max SimplifyDemandedFPClass (#175381)

Test some more refined cases, such as ordering with 0s and within
known positive and known negative cases.
DeltaFile
+490-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+489-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+488-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+488-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+1,955-04 files

LLVM/project 805d7b8llvm/lib/Transforms/Scalar DeadStoreElimination.cpp, llvm/test/Transforms/DeadStoreElimination simple.ll

feedback

Created using spr 1.3.7
DeltaFile
+29-2llvm/test/Transforms/DeadStoreElimination/simple.ll
+17-10llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+46-122 files

LLVM/project 2166cebclang/include/clang/Basic OpenCLExtensions.def, clang/lib/Headers opencl-c.h opencl-c-base.h

Revert "[OpenCL] Set KHR extensions minimum version to OpenCL 1.0 (#175120)"

This reverts commit 386d9399731d28532e38b9820f3a44a9cfbead77.
DeltaFile
+85-134clang/lib/Headers/opencl-c.h
+13-177clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl
+51-101clang/test/Headers/opencl-c-header.cl
+21-19clang/include/clang/Basic/OpenCLExtensions.def
+20-20clang/test/SemaOpenCL/extension-version.cl
+0-7clang/lib/Headers/opencl-c-base.h
+190-4582 files not shown
+193-4618 files

LLVM/project 1547ee6llvm/utils/gn/secondary/llvm/lib/Target/AArch64 BUILD.gn

[gn build] Port 91f5d73b311f
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
+1-01 files

LLVM/project 804c034flang/lib/Semantics check-omp-loop.cpp, flang/test/Semantics/OpenMP linear-clause01.f90 clause-validity01.f90

[flang][OpenMP] Fix LINEAR clause validation to report all errors (#175938)

Fixes #175688 

After #175383 was merged, test failures occurred because removing the
early return exposed additional errors that tests weren't expecting.

This PR comprehensively fixes the issue by:

1. **Removes the early return** in check-omp-loop.cpp (line 767) after
detecting a modifier error on DO/SIMD directives. Previously, when a
modifier error was found, the function would return immediately without
checking other restrictions like the scalar requirement. Now all
applicable errors are reported, improving diagnostics.

2. **Updates linear-clause01.f90** to expect both the modifier error AND
the scalar error for Case 1 and Case 2, where arrays are used
incorrectly in LINEAR clauses.


    [8 lines not shown]
DeltaFile
+3-5flang/test/Semantics/OpenMP/linear-clause01.f90
+2-2flang/test/Semantics/OpenMP/clause-validity01.f90
+1-1flang/lib/Semantics/check-omp-loop.cpp
+6-83 files

LLVM/project bc9fce7mlir/lib/Dialect/Vector/IR VectorOps.cpp, mlir/test/Dialect/Vector canonicalize.mlir

[MLIR][Vector] Add a pattern that folds consecutive extract_strided_strided_slice ops (#175738)

A slice of a slice is just a slice.
DeltaFile
+66-3mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+42-0mlir/test/Dialect/Vector/canonicalize.mlir
+108-32 files

LLVM/project 802ca04flang/test/Lower array-user-def-assignments.f90 array-temp.f90

[flang][NFC] Converted five tests from old lowering to new lowering (part 6) (#175485)

Modified the following tests: array-elemental-calls-2.f90,
array-expression-assumed-size.f90, array-temp.f90,
array-user-def-assignments.f90, array.f90
DeltaFile
+165-644flang/test/Lower/array-user-def-assignments.f90
+76-353flang/test/Lower/array-temp.f90
+73-286flang/test/Lower/array-expression-assumed-size.f90
+216-105flang/test/Lower/array-elemental-calls-2.f90
+80-67flang/test/Lower/array.f90
+610-1,4555 files

LLVM/project 1f2d10ellvm/include/llvm/IR IRBuilder.h

[NFC][IRBuilder] Reuse CreateGEP for helpers (#175979)

Many helper functions for single index GEP exist, but each implement the
same logic to then create the GetElementPtrInst. Refactoring to call a
single function.
This is some groundwork to prepare the SGEP implementation.
DeltaFile
+8-40llvm/include/llvm/IR/IRBuilder.h
+8-401 files

LLVM/project 43e46f2llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-minimumnum.ll simplify-demanded-fpclass-maximumnum.ll

InstCombine: Handle multiple uses for min/max in SimplifyDemandedFPClass
DeltaFile
+127-91llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+4-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+4-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+4-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+4-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+143-1075 files

LLVM/project cd0df23llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-minimum.ll simplify-demanded-fpclass-minimumnum.ll

InstCombine: Improve SimplifyDemandedFPClass min/max handling

Refine handling of minimum/maximum and minimumnum/maximumnum. The
previous folds to input were based on sign bit checks. This was too
conservative with 0s. This can now consider -0 as less than or equal
to +0 as appropriate, account for nsz. It additionally can handle
cases like one half is known positive normal and the other subnormal.
DeltaFile
+32-61llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+23-58llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+22-52llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+23-46llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+22-44llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+122-2615 files

LLVM/project 541734dllvm/test/Transforms/InstCombine simplify-demanded-fpclass-maximum.ll simplify-demanded-fpclass-minimum.ll

InstCombine: Add more tests for min/max SimplifyDemandedFPClass

Test some more refined cases, such as ordering with 0s and within
known positive and known negative cases.
DeltaFile
+490-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+489-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+488-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
+488-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+1,955-04 files

LLVM/project c5e95afclang/docs index.rst, clang/docs/ScalableStaticAnalysisFramework SummaryExtraction.rst Framework.rst

[clang][ssaf][docs] Document the Summary Extraction pipeline (#172876)

This patch adds some documentation about the design of the Scalable
Static Analysis Framework (SSAF) Summary Extraction part.

This mainly focuses on how the custom FrontendAction would load
different analyses (their extraction part), and the different formats it
should export into.
Each FrontendAction call would process a single TU by extracting
summaries from them and serializing the results into a file in the
desired format.

The details are not polished yet, but I think it's still beneficial to
have some guidance on how the upcoming components would fit together,
hence this document.
I'll come back to this document to keep it up-to-date as we proceed with
the upstreaming.
DeltaFile
+81-0clang/docs/ScalableStaticAnalysisFramework/SummaryExtraction.rst
+13-0clang/docs/ScalableStaticAnalysisFramework/Framework.rst
+1-0clang/docs/index.rst
+95-03 files

LLVM/project cfefd3ellvm/test/CodeGen/PowerPC milicode64.ll milicode32.ll

[NFC][PowerPC] add  test cases for milicode (#175559)

In this PR, we do the following:

1. Simplify the test case for the millicode function  `___memmove`.
2. Add test cases for the millicode functions `___memcpy` ,
`____memset`, `____memmove` which are supported in the patch
https://reviews.llvm.org/D143997.
3. Add pre-commit test cases for the functions `___strstr`,
`___memccpy`, `___strcmp`
DeltaFile
+257-42llvm/test/CodeGen/PowerPC/milicode64.ll
+179-33llvm/test/CodeGen/PowerPC/milicode32.ll
+436-752 files

LLVM/project 58a9dc0clang/lib/CodeGen CGExpr.cpp CGExprScalar.cpp, clang/test/CodeGenHLSL/BasicFeatures MatrixSingleSubscriptGetter.hlsl MatrixSingleSubscriptSetter.hlsl

[HLSL][Matrix] Add type conversions to support bool matrix single subscript operators (#175633)

Fixes #172711

Fixes the type mismatch issues preventing single matrix subscript
getters and setters from working with boolean matrices.

The changes from this PR also happens to make matrix splats work for
boolean matrices, but adding tests for that and (re)introducing
boolean-matrix-specific sema will be relegated to its own PR.
DeltaFile
+65-0clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptGetter.hlsl
+63-0clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptSetter.hlsl
+14-0clang/lib/CodeGen/CGExpr.cpp
+2-2clang/lib/CodeGen/CGExprScalar.cpp
+144-24 files

LLVM/project ada4d3allvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Handle fdiv in SimplifyDemandedFPClass
DeltaFile
+127-148llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
+130-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+46-0llvm/lib/Support/KnownFPClass.cpp
+3-33llvm/lib/Analysis/ValueTracking.cpp
+10-0llvm/include/llvm/Support/KnownFPClass.h
+316-1825 files

LLVM/project 7ac1f11llvm/test/Transforms/InstCombine simplify-demanded-fpclass-fdiv.ll

InstCombine: Add baseline fdiv SimplifyDemandedFPClass tests
DeltaFile
+2,321-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
+2,321-01 files

LLVM/project 0431b71llvm/lib/Target/SPIRV SPIRVLegalizePointerCast.cpp, llvm/test/CodeGen/SPIRV/pointers store-to-array-first-element.ll

[SPIR-V] Fix store to first element array (#175546)

The IR can store to the first element of an array the same way it stores
to the first element of a struct by specifying the base pointer. This
commit fixes the pointercast legalization pass to support this.
DeltaFile
+20-0llvm/test/CodeGen/SPIRV/pointers/store-to-array-first-element.ll
+2-3llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
+22-32 files

LLVM/project 91f5d73llvm/lib/Target/AArch64 AArch64SRLTDefineSuperRegs.cpp, llvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-int-shifts.ll sve-streaming-mode-fixed-length-int-extends.ll

[AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188)

When SubRegister Liveness Tracking (SRLT) is enabled, this pass adds
extra implicit-def's to instructions that define the low N bits of a
GPR/FPR register to represent that the top bits are written, because all
AArch64 instructions that write the low bits of a GPR/FPR also
implicitly zero the top bits.

These semantics are originally represented in the MIR using
`SUBREG_TO_REG`, but during register coalescing this information is lost
and when rewriting virtual -> physical registers the implicit-defs are
not added to represent the the top bits are written.

There have been several attempts to fix this in the coalescer (#168353),
but each iteration has exposed new bugs and the patch had to be
reverted. Additionally, the concept of adding 'implicit-def' of a
virtual register during the register allocation process is particularly
fragile and many places don't expect it (for example in
`X86::commuteInstructionImpl` the code only looks at specific operands

    [9 lines not shown]
DeltaFile
+6-318llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
+102-165llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
+248-0llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
+40-90llvm/test/CodeGen/AArch64/arm64-addrmode.ll
+107-0llvm/test/CodeGen/AArch64/subreg-liveness-fix-subreg-to-reg-implicit-def.mir
+14-42llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
+517-61530 files not shown
+584-73436 files