LLVM/project 72aeee3orc-rt/test/regression check-rt-process-info.test

[orc-rt] Reconcile check-rt-process-info changes. (#225592)

3648582c0a41 was supposed to make this test more generic, but
accidentally removed it instead.

Reconcile the dropped changes with 3648582c0a41, which added page-size
checking.
DeltaFile
+3-2orc-rt/test/regression/check-rt-process-info.test
+3-21 files

LLVM/project a9191d3flang/lib/Optimizer/OpenMP LowerWorkdistribute.cpp, flang/test/Transforms/OpenMP lower-workdistribute-runtime-assign-array.mlir

[flang][OpenMP] Lower array-section workdistribute assign to element loop
DeltaFile
+111-11flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
+69-0flang/test/Transforms/OpenMP/lower-workdistribute-runtime-assign-array.mlir
+180-112 files

LLVM/project fa43610llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV bfloat-imm.ll float-imm.ll

[RISCV] Expand scalar FP undef/poison to 0.0 with F extension. (#225567)

This ensures the undef/poison value is always nan-boxed. This is
important if the value ends up being used by a freeze. If the value
isn't properly nan-boxed, it will be treated as a nan in FP contexts
regardless of its lower bits. If the freeze is also cast to an integer,
the lack of nan-boxing will be noticed and the integer will see the real
value of the lower bits.

Fixes #225455.
DeltaFile
+42-0llvm/test/CodeGen/RISCV/half-imm.ll
+42-0llvm/test/CodeGen/RISCV/double-imm.ll
+24-0llvm/test/CodeGen/RISCV/float-imm.ll
+16-0llvm/test/CodeGen/RISCV/bfloat-imm.ll
+7-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+131-05 files

LLVM/project 3648582orc-rt/lib/bedrock CMakeLists.txt, orc-rt/lib/bedrock/sys/windows Memory.cpp PageSize.cpp

[orc-rt] Add Windows page size detection (#224520)

Adds Windows page size detection for ORC-RT using GetSystemInfo.

Also updates the process-info regression coverage into a single test
DeltaFile
+21-0orc-rt/lib/bedrock/sys/windows/PageSize.cpp
+1-13orc-rt/test/unit/bedrock/ExecutorProcessInfoTest.cpp
+6-0orc-rt/test/regression/check-rt-process-info.test
+0-5orc-rt/test/regression/linux/check-rt-process-info.test
+0-4orc-rt/lib/bedrock/sys/windows/Memory.cpp
+1-0orc-rt/lib/bedrock/CMakeLists.txt
+29-226 files

LLVM/project 8273202llvm/include/llvm/IR Intrinsics.h, llvm/lib/IR AutoUpgrade.cpp Intrinsics.cpp

[LLVM][AutoUpgrade] Support default args on overloaded intrinsics (#217859)

This patch extends intrinsic `DefaultValue` auto-upgrade to overloaded
intrinsics.

---------

Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
DeltaFile
+33-5llvm/lib/IR/Intrinsics.cpp
+21-4llvm/test/TableGen/intrinsic-default-args.td
+12-7llvm/lib/IR/AutoUpgrade.cpp
+0-8llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
+8-0llvm/include/llvm/IR/Intrinsics.h
+74-245 files

LLVM/project 20e7308llvm/test/CodeGen/AMDGPU atomic_optimizations_global_pointer.ll atomic_optimizations_local_pointer.ll

[AMDGPU] Port Atomic-Optimizer to use Wave Reduction Intrinsics (#211757)

Currently the atomic optimizer creates reductions via intrinsics,
and introduces new control flows.
Replace this sub-target dependent logic with the existing
wave reduction intrinsics, which get lowered in the backend.
This patch ports the uniform-value and divergent-no-return-value cases.
To port the divergent-with-return-value cases, additional scan intrinsics
will need to be added.
DeltaFile
+4,817-5,217llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
+4,559-5,003llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
+1,783-2,031llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
+1,783-2,031llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
+1,574-1,388llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+1,328-1,223llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+15,844-16,89322 files not shown
+19,285-20,64128 files

LLVM/project 7f8640blld/ELF Config.h Relocations.cpp, lld/test/ELF x86-64-plt.s

[lld] Add -z mark-plt support for X86_64 (#206002)

Add option [no]mark-plt to enable it. Dynamic linker can change PLT
entries with JMPABS instruction on supported targets.

Ref.:
https://maskray.me/blog/2021-09-19-all-about-procedure-linkage-table#x86-plt-rewriting

Assisted-by: Claude Sonnet 4.6

---------

Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
DeltaFile
+44-0lld/test/ELF/x86-64-plt.s
+12-0lld/ELF/Driver.cpp
+6-0lld/ELF/SyntheticSections.cpp
+5-0lld/ELF/OutputSections.cpp
+2-0lld/ELF/Relocations.cpp
+1-0lld/ELF/Config.h
+70-06 files

LLVM/project 1bfe989libcxx/test/benchmarks lit.local.cfg CMakeLists.txt, libcxx/utils/libcxx/test config.py format.py

[libc++] Build GoogleBenchmark directly from Lit (#224192)

Previously, we would build GoogleBenchmark against the just-built
library, not against the library being tested. When testing historical
versions of libc++ or other standard libraries, this breaks. So instead
of building Google Benchmark against the just-built library in CMake, do
it from Lit as part of the test suite's configuration.

I'm not a huge fan of using Lit as a poor man's build system and we
should make the CMake test suite self-contained, however this is a step
in the right direction and it removes a major coupling between the test
suite and the regular libc++ build.
DeltaFile
+223-0libcxx/utils/libcxx/test/googlebenchmark.py
+0-48libcxx/test/benchmarks/CMakeLists.txt
+8-5libcxx/utils/libcxx/test/format.py
+11-0libcxx/test/benchmarks/lit.local.cfg
+1-1libcxx/utils/libcxx/test/config.py
+0-1libunwind/test/configs/cmake-bridge.cfg.in
+243-553 files not shown
+243-589 files

LLVM/project 9328848libcxx/test/benchmarks/containers string.bench.cpp

[libc++] Add missing <cstring> include in the string benchmark (#225501)

The benchmark uses std::strlen but never includes <cstring>.
DeltaFile
+1-0libcxx/test/benchmarks/containers/string.bench.cpp
+1-01 files

LLVM/project 7e25a95.github/workflows libcxx-pr-conformance-tests.yaml

[libc++] Pin down the OS version of macOS runners (#225536)

Otherwise, we sometimes end up using runners that don't have Xcode 26.5
on them. Pinning this allows bumping the version explicitly when we are
ready to.
DeltaFile
+1-1.github/workflows/libcxx-pr-conformance-tests.yaml
+1-11 files

LLVM/project b011bcellvm/lib/Target/RISCV RISCVInstrInfoXTHead.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[RISCV] Reject XTHeadMemIdx load-update with rd == rs1 (#225271)

In spec: "The encoding of this instruction with equal _rd_ and _rs1_ is
reserved."

This commit fixes the problem in Assembler, Codegen is already correct.

Link:
-
[th.lbia](https://github.com/XUANTIE-RV/thead-extension-spec/blob/d16533b5a9cd790c369d849ddf9a48159a5a235c/xtheadmemidx/lbia.adoc#L28)
-
[th.lbib](https://github.com/XUANTIE-RV/thead-extension-spec/blob/d16533b5a9cd790c369d849ddf9a48159a5a235c/xtheadmemidx/lbib.adoc#L28)
-
[th.lbuia](https://github.com/XUANTIE-RV/thead-extension-spec/blob/d16533b5a9cd790c369d849ddf9a48159a5a235c/xtheadmemidx/lbuia.adoc#L28)
-
[th.lbuib](https://github.com/XUANTIE-RV/thead-extension-spec/blob/d16533b5a9cd790c369d849ddf9a48159a5a235c/xtheadmemidx/lbuib.adoc#L28)
-
[th.lhia](https://github.com/XUANTIE-RV/thead-extension-spec/blob/d16533b5a9cd790c369d849ddf9a48159a5a235c/xtheadmemidx/lhia.adoc#L28)
-

    [24 lines not shown]
DeltaFile
+72-0llvm/test/MC/Disassembler/RISCV/xthead-invalid-overlap.txt
+49-0llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
+27-3llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+29-0llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+12-2llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+189-55 files

LLVM/project 3092b46llvm/lib/Target/RISCV RISCVInstrInfoXCV.td

[RISCV][MC] Mark the cv.insert is2 decoder as incomplete (#225574)

This commit addresses the post-commit review of
https://github.com/llvm/llvm-project/pull/225269
DeltaFile
+1-0llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+1-01 files

LLVM/project 6c95a92llvm/lib/Transforms/Vectorize VPRecipeBuilder.h VPlanTransforms.h, llvm/test/Transforms/LoopVectorize cast-induction.ll

[LV] Narrow truncated inductions in a VPlan transform (#220730)

VPRecipeBuilder::tryToOptimizeInductionTruncate matched a truncate of an
induction phi on the underlying IR, and it built the narrowed
VPWidenIntOrFpInductionRecipe from the recipe behind the truncate's
operand.
VPlanTransforms already answers the same question on VPValues in
getOptimizableIVOf, which returns the header IV whether the operand is
the IV
itself or an add of the IV and its step.

Add VPlanTransforms::narrowInductionTruncates and do the match there,
reusing
getOptimizableIVOf and restricting it to the phi for now. The pass runs
right
after makeCallWideningDecisions, which preserves the ordering against
makeScalarizationDecisions that the recipe builder relied on. Building
the
recipe in the transform also removes the need for the conversion loop to

    [3 lines not shown]
DeltaFile
+63-0llvm/test/Transforms/LoopVectorize/cast-induction.ll
+61-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+6-49llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+9-0llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+0-5llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+1-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-before-after-all.ll
+140-546 files

LLVM/project 0eccf17clang/lib/Headers avx10v2auxintrin.h, clang/test/CodeGen/AArch64 neon-ldst-one.c

Merge branch 'main' into users/himadhith/refactor_strToNum_funcs
DeltaFile
+4,372-0clang/test/OpenMP/structured-bindings-codegen.cpp
+1,413-1,413clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+1,403-1,403clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+1,403-1,403clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
+0-2,567clang/test/CodeGen/AArch64/neon-ldst-one.c
+2,403-0clang/lib/Headers/avx10v2auxintrin.h
+10,994-6,7861,931 files not shown
+109,353-52,3141,937 files

LLVM/project 29cd2c5llvm/lib/ProfileData InstrProf.cpp, llvm/lib/Transforms/Instrumentation InstrProfiling.cpp

[PGO] Add GPU wave counters

Lane counts do not show how often a GPU wave reaches an instrumentation
point. A divergent wave can execute both paths even when few lanes take
one path.

Extend the GPU profiling helper to collect a wave count alongside each
existing lane counter. The first active lane increments the wave counter
once, using the same workgroup sampling decision as the lane counters.
Collect both channels together so shared functions use a consistent
counter layout across translation units. Workgroup sampling controls
profiling overhead.

Carry wave counts through raw and indexed profiles and weighted merging
as a separate channel. Preserve ordinary lane-flow counts and leave
blocks without instrumentation unmeasured.
DeltaFile
+39-43llvm/lib/ProfileData/InstrProf.cpp
+49-19llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
+60-0llvm/unittests/ProfileData/InstrProfTest.cpp
+51-0llvm/test/Instrumentation/InstrProfiling/gpu-wave-link.ll
+50-0llvm/test/tools/llvm-profdata/gpu-wave-counts.test
+38-0llvm/test/Instrumentation/InstrProfiling/gpu-wave-counts.ll
+287-6239 files not shown
+577-15745 files

LLVM/project b47a631libc/fuzzing/__support CMakeLists.txt, libc/src/__support freestore.h block.h

[libc] Implement dual freestore rotation for baremetal heap (#209811)

Implement dual FreeStore rotation in FreeListHeap under
LIBC_COPT_BAREMETAL_HEAP_ENABLE_FREESTORE_ROTATION option for baremetal
targets.

- Allocations pull from active store; free() quarantines blocks into
non-active store (1 - active).
- On allocation failure in active store, rotate() flips active index and
migrates/coalesces quarantined blocks into the new active store.
- Added 2-bit prev_free tracking in BlockRef metadata to distinguish
freestore indices.
- Added unit smoke tests and updated fuzzer for dual freestore rotation.

Assisted-by: Gemini and Claude based automation tool (human-in-the-loop)

---------

Co-authored-by: Yifan Zhu <yfzhu at google.com>
Co-authored-by: Claude Fable 5.1 <noreply at anthropic.com>
DeltaFile
+108-39libc/src/__support/freelist_heap.h
+117-4libc/test/src/__support/freelist_heap_test.cpp
+48-15libc/src/__support/block.h
+38-4libc/src/__support/freestore.h
+18-0libc/test/src/__support/CMakeLists.txt
+14-0libc/fuzzing/__support/CMakeLists.txt
+343-626 files not shown
+373-6212 files

LLVM/project ffeffcelldb/include/lldb/Target Process.h Target.h, lldb/include/lldb/Utility DataExtractor.h ConstString.h

[lldb] Consistently use "null-terminated" across LLDB (NFC) (#224801)

It appears that both spellings are correct, but "null terminator" is far
more common, while "NUL terminator" is technically precise regarding the
ASCII character name. Most common in LLDB was "NULL terminated" which is
the worst of both worlds. This rallies around "null-terminated".

- Adjective -> null-terminated
- Verb -> null-terminate
- Nouns left unhyphenated but lowercased: null terminator, null
termination
DeltaFile
+8-8lldb/unittests/Utility/DataEncoderTest.cpp
+8-8lldb/include/lldb/Utility/ConstString.h
+7-7lldb/include/lldb/Utility/DataExtractor.h
+6-7lldb/include/lldb/Target/Target.h
+6-6lldb/include/lldb/Target/Process.h
+5-5lldb/source/Utility/Stream.cpp
+40-4153 files not shown
+121-12359 files

LLVM/project 1f01cb4llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 narrowed-reduction-leaves-known-bits.ll

[SLP]Fix crash in bool bitmask reduction match after tree vectorization

The known bits of the narrowed reduction leaves were computed after the
tree vectorization, which drops the operands of the vectorized scalars,
so the analysis dereferenced null operands. Match the bitmask form before
the vectorization and pass the result to the emission.

Fixes #225538

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/225568
DeltaFile
+60-0llvm/test/Transforms/SLPVectorizer/X86/narrowed-reduction-leaves-known-bits.ll
+10-4llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+70-42 files

LLVM/project 182181cmlir/include/mlir/IR BuiltinTypeInterfaces.td

[mlir][NFC] Improve `ShapedTypeInterface` documentation (#225282)

Document that each dimension size must be not larger than "signed int64
max".

Related discussion:
https://discourse.llvm.org/t/rfc-vector-should-vector-transfer-read-transfer-write-indices-be-treated-as-unsigned-non-negative/91869/6
DeltaFile
+6-5mlir/include/mlir/IR/BuiltinTypeInterfaces.td
+6-51 files

LLVM/project febece3mlir/lib/Dialect/MemRef/IR MemRefOps.cpp, mlir/test/Dialect/MemRef invalid.mlir

[mlir][memref] Reject empty collapse_shape and expand_shape reassociation groups (#225348)

`memref.collapse_shape` and `memref.expand_shape` both accept an empty
reassociation group, which is not a valid reassociation: every group
must be a
non-empty, contiguous segment of dimensions.

* `memref.collapse_shape` with an empty group aborts the compiler for a
  non-identity source layout. `CollapseShapeOp::verify` forwards the
reassociation to `computeCollapsedLayoutMap`, which calls
`ArrayRef::back()`
  on each group and asserts on the empty one:

      mlir-opt: llvm/include/llvm/ADT/ArrayRef.h:151:
      const T& llvm::ArrayRef<T>::back() const [with T = long int]:
      Assertion `!empty()' failed.

  With an identity source layout the op is instead silently accepted.


    [18 lines not shown]
DeltaFile
+31-0mlir/test/Dialect/MemRef/invalid.mlir
+17-0mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
+48-02 files

LLVM/project 82ea1d2llvm/test/CodeGen/X86 no-split-size.ll 2008-04-16-ReMatBug.ll, llvm/test/CodeGen/X86/AMX amx-spill-merge.ll

[RegAlloc] [X86] Enable callee saved register optimization for x86 (#220090)

Enable callee saved register optimization implemented in
RAGreedy::tryAssignCSRFirstTime() for x86. It can replace save/restore
instructions in prologue/epilogue with register spill/reload in cold
blocks or register splits.

Spec cpu 2006 int result with fdo on skylake.
```
regalloc-csr-cost-scale                                 0     30

400.perlbench                                          42.0  42.7   
401.bzip2                                              25.5  26.3   
403.gcc                                                42.1  41.4   
429.mcf                                                45.0  44.4   
456.hmmer                                              38.2  38.2   
458.sjeng                                              32.3  32.0   
462.libquantum                                         68.0  68.9   
471.omnetpp                                            26.9  27.3   

    [5 lines not shown]
DeltaFile
+68-68llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
+61-72llvm/test/CodeGen/X86/speculative-load-hardening.ll
+48-42llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
+39-31llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
+29-38llvm/test/CodeGen/X86/no-split-size.ll
+34-32llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
+279-28322 files not shown
+512-51928 files

LLVM/project 71122e7llvm/lib/CodeGen/SelectionDAG SelectionDAGDumper.cpp

[SelectionDAG] Add ISD::ARITH_FENCE to SelectionDAGDumper. (#225485)

We seem to have no consistency on CamelCase or snake_case in node
naming. I've gone with CamelCase to match the nearby nodes, but happy to
change.
DeltaFile
+1-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+1-01 files

LLVM/project 838c705clang/docs ReleaseNotes.md, clang/lib/AST ExprConstant.cpp

[clang] Return early if a value dependent recovery init appeared in constant evaluation context in legacy constant evaluator (#225027)

A recovery default member initializer can be value-dependent even when
the expression referring to the variable is not. Clang should return
early to avoid crash.

This fix the issue found in
https://github.com/llvm/llvm-project/issues/185874#issuecomment-4058045596.

---------

Signed-off-by: yronglin <yronglin777 at gmail.com>
DeltaFile
+25-2clang/test/SemaCXX/recovery-expr-type.cpp
+15-7clang/lib/AST/ExprConstant.cpp
+3-0clang/docs/ReleaseNotes.md
+43-93 files

LLVM/project a3cba3cbolt/lib/Core DebugNames.cpp

Close a loose end for synthesized debug (anonymous namespace) strings that happen to be already in the main CU debug_str section.
DeltaFile
+4-7bolt/lib/Core/DebugNames.cpp
+4-71 files

LLVM/project c2b3813orc-rt/include/orc-rt/support bit.h

[orc-rt] Simplify bit.h countl_zero and bit_width (#225547)

The old countl_zero algorithm wasn't recognized / optimized by clang on
arm64 or x86-64. Switch to a simpler loop that clang recognizes and
rewrite bit_width in terms of countl_zero. NFCI.
DeltaFile
+8-19orc-rt/include/orc-rt/support/bit.h
+8-191 files

LLVM/project 1adcce1clang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/Driver sanitize-trap-loop.c

[Driver] Link ubsan_loop_detect with --whole-archive (#225498)

`addSanitizerRuntimes` places sanitizer archives before user object
files on the linker command line.

Because `ubsan_loop_detect` was in `NonWholeStaticRuntimes` without `-u`
symbols, single-pass linkers like GNU `ld.bfd` discarded
`libclang_rt.ubsan_loop_detect.a` before seeing references to
`__ubsan_install_trap_loop_detection` or `__ubsan_is_trap_loop`. Move
`ubsan_loop_detect` to `StaticRuntimes` so it is linked with
`--whole-archive`.
DeltaFile
+1-1clang/test/Driver/sanitize-trap-loop.c
+1-1clang/lib/Driver/ToolChains/CommonArgs.cpp
+2-22 files

LLVM/project e02ef74llvm/lib/Target/RISCV RISCVISelLowering.cpp

fixup! Typo
DeltaFile
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1-11 files

LLVM/project 429bc4eclang/lib/CIR/CodeGen CIRGenCleanup.cpp CIRGenExprScalar.cpp, clang/test/CIR/CodeGen cleanup-conditional.cpp dtors.cpp

[CIR] Use cleanup active flag with logical operators (#225554)

When temporary expressions are created within a logical binary
operation, we need to use a "cleanup active" flag to guard any cleanups
that are created in the right-hand side of the expression because the
expression may short-circuit and not evaluate the RHS. Failure to do so
had been leading to destructors being called for objects that had never
been constructed.

This fix introduces a regression in destructor call ordering when both
sides of a logical operation create temporaries that require cleanup.
This is a known ordering bug that preceeded this PR but was incidentally
avoided by the previous incorrect handling. The orderig bug will be
fixed in a follow-up change.

Assisted-by: Cursor / various models
DeltaFile
+107-105clang/test/CIR/CodeGen/dtors.cpp
+86-0clang/test/CIR/CodeGen/cleanup-conditional.cpp
+8-2clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+8-0clang/lib/CIR/CodeGen/CIRGenCleanup.cpp
+209-1074 files

LLVM/project 0ff5abdclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp, clang/test/CIR/Lowering not.cir

[CIR] Fix 'cir.not' lowering behavior for >64 bit size (#225541)

We were only inverting the lower 64 bits because we used the
int64_t/uint64_t overload, which only filled in 64 bits. This patch
replaces that with a 'getAllOnes' of the right size.
DeltaFile
+33-0clang/test/CIR/Lowering/not.cir
+3-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+36-12 files

LLVM/project 4c320dcclang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp, clang/test/CIR/CodeGen nobuiltin-replaceable-allocation.cpp

[CIR] Lower nobuiltin attribute (#225545)

This causes a problem in tests for global allocation functions, but we
are not currently lowering the 'nobuiltin' attribute to LLVM-IR. This
patch adds the lowering.
DeltaFile
+25-0clang/test/CIR/CodeGen/nobuiltin-replaceable-allocation.cpp
+3-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+28-12 files