[GlobalISel] Fix dominance when legalizing PHI for results of invoke (#234603)
PHI legalization inserts type conversions before the first terminator so that
they execute on unwind edges. However, an invoke result is defined after
G_INVOKE_REGION_START (which can be the first terminator). Therefore conversions
of these results are inserted before the defs, causing a use before def.
Keep the existing insertion point for values available before the invoke. For
anything that is defined later, move the conversion point to after the def.
Assisted-by: Codex
[AArch64] Don't fold expandloads/compressstores into (de)interleave ops (#239160)
Previously, `performVector(De)interleaveCombine` would miscompile by
combining expandloads and compressstores with deinterleaves and
interleaves respectively.
This is fixed by updating `ISD::isNormalMaskedLoad()` and
`ISD::isNormalMaskedStore()` to exclude isExpandingLoad() and
isCompressingStore().
[mlir][ODS] Allow a space-only separator for bit enums
Bit enums required a separator containing '|' or ',', so a flag set
could not use the bare keyword syntax of LLVM IR, e.g. `nuw nsw`.
Dialects that want it, such as ClangIR's overflow flags, had to hand-write
a parser and printer for an EnumProp.
Allow `separator = " "` on new-style BitEnums. The generated FieldParser
then reads case keywords until the next token is not one, symbolize
splits on spaces, and the op-format `enum` directive parses the same
way. Like the existing check for a separator literal, the format
verifier rejects a case literal right after such an enum. The separator
must now be '|', ',', or a space ' ', where '|' and ',' may still be
surrounded by spaces, so strings such as "||" are rejected. Legacy
BitEnumAttr keeps requiring '|' or ','.
Assisted-by: Claude Code (Claude Opus 5.5).
AMDGPUCodeGenPrepare.cpp - fix MSVC "warning C4018: '<=': signed/unsigned mismatch" warnings. NFC. (#239168)
A possibly futile attempt to get /WX builds working again
[MLIR] Add TableGen "variant" of MLIRSupport (#239165)
mlir-src-sharder currently depends on MLIRSupport. In a dylib build,
this brings in a dependency on an LLVM shared library. Since
mlir-src-sharder is a TableGen tool, it links statically against
LLVMSupport, which introduces an ODR violation caught at link-time on
Windows in an LLVM dylib build.
To work around this issue, this PR introduces MLIRSupport_tablegen, to
be used by mlir-src-sharder and other MLIR TableGen tools. This always
links against a static LLVMSupport and prevents ODR violations.
This approach follows the precedent set by clangSupport_tablegen.
The effort to build LLVM as a dylib is tracked in #109483.
[IndVarSimplify] Use context to prove a narrow IV def non-negative
When IndVars widens an IV, it checks for each narrow def
(the IV and values computed from it) whether it is
non-negative on every iteration.
If it is, zext and sext of it are equal. Then when IndVars
idens the def's users, they can choose to use either
the sext or zext of the def.
Previously, we didn't use context to prove the non-negativity of def.
Now ask SCEV about the def non-negativity at its context -
the def instruction itself.
This allows SCEV to infer facts from the dominating guards and assumes.
This in turn allows eliminating unnecessary truncs/zexts. E.g. in
if (m > 0)
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[IndVarSimplify][SCEV][NFC] Add tests for LFTR losing the constant max trip count
When LFTR of IndVars rewrites a loop exit like i >s C
to i + 1 == smax(start, C + 1),
SCEV's constant max backedge-taken count of the loop gets worse.
Add tests showing it.
Assisted-By: Claude
[LoopVectorize][NFC] Add tests for runtime checks with a widened IV index
In
if (start <u len && start - 32 <u len) // len >=s 0
for (int32_t i = start; i < n; i++) a[i] = a[i - 32];
i - 32 >=s 0, so the distance between a[i] and a[i - 32] is always 32.
If the loop has an i64 IV and i - 32 is computed in i64, it is
vectorized without runtime checks.
If i - 32 is computed in i32 and zero-extended, the vectorizer
emits an overflow check and an alias check.
Add tests for both forms.
Assisted-By: Claude
[IndVarSimplify][NFC] Add a negative test for zext elimination
Add a test for a zext of an nsw add of a sign-extended IV, where the
add may be negative.
Also rewrite a stale comment of an existing test.
Assisted-By: Claude
[Flang][NFC] Remove FOR_EACH_*_KIND macros (#238748)
Third cleanup after #216960
The `FOR_EACH_*_KIND` macros only expand to a single item. In cases
where this was already the case before #216960, such as `SomeDerived`,
it was spelled out without a macro. Do the same for `FOR_EACH_*_KIND` .
[mlir][ToLLVM] Fix dead FileCheck in func-to-llvm-datalayout.mlir (NFC) (#238964)
The RUN line did not pipe into FileCheck, so none of the CHECK lines
were evaluated. Add the missing FileCheck and update the CHECK lines to
the current printer output (compact `dl_spec` syntax, no argument names
for private function declarations).
Found while looking into the static mode of `convert-to-llvm`, which
ignores `dlti.dl_spec`. Its test coverage is intentionally not extended
here: per the discussion in #156557, the static mode is a candidate for
removal rather than a fix. The open question is whether `dynamic=true`
should become the default.
Co-authored-by: Sven Lukas <sven.lukas at gmail.com>
[bazel][lldb] Port eeb24ee48aa2: Add PluginRegisterCore (#239177)
Fixes the Bazel build after eeb24ee48aa2 ([lldb] Extract reusable core
register contexts (#237442)), which moved the core register contexts to
lldb/source/Plugins/Register/Core.
[DebugInfo] Escape strings echoed into .debug_str comments (#223384)
Since 1a23bca645dc, `DwarfStringPool::emit` echoes each string into the
assembler comment next to its bytes. Strings can contain arbitrary
bytes, e.g. non-ASCII identifiers, and some assemblers reject those even
inside comments: `ptxas` (before CUDA 13.1) aborts with "Unexpected
non-ASCII character encountered" (JuliaGPU/CUDA.jl#3274). Escape the
string, as is already done when it is emitted as a quoted `.asciz`
directive.
Building the escaped comment is no longer free like the lazy `Twine` it
replaces, so only do it for verbose assembly output.
Get RegisterClassInfo from MachineRegisterClassInfoWrapperPass
Use the shared analysis instead of computing a private RegisterClassInfo, and
update its reserved registers after freezeReservedRegs(), as RegAllocBase does.
Assisted-by: Claude Opus 5.5
[libc++] Allow the compiler to reorder computation in reduction loops (#237918)
This PR allows Clang to vectorize and interleave loops in the reduction
algorithms: `std::reduce` and `std::transform_reduce`.
This is permitted by
https://eel.is/c++draft/numerics.defns#lib:GENERALIZED_SUM.
Currently it's enabled only for Clang, it's unclear if GCC has a direct
equivalent.
A new macro `_LIBCPP_ENABLE_LOOP_VECTORIZATION` is tentatively placed in
`__configuration/attributes.h`, though it's not an attribute per-se.
Ideally we might want to refactor `__configuration/pstl.h` to be less
PSTL-specific and put the new macro there instead.
Part of #234887
[mlir][NFC] Remove includes provided by generated declarations and definitions (#238848)
#236155 and #238735 made the generated declarations and definitions of
ops, attributes, types and interfaces include the core MLIR headers they
require. Includes that headers and source files only had for the
generated code are therefore redundant. This removes them in MLIR, Flang
and ClangIR.
Includes of headers that the hand-written code uses directly are kept,
even when the generated code includes them as well.
---------
Co-authored-by: Claude <noreply at anthropic.com>
