[TableGen] Fix inferring missing sub-classes for various subreg indices (#185638)
We should not imply artificial registers have sub-registers for a given
index even if the class is known to 'fully support' that index.
Fixes crashes reported in
https://github.com/llvm/llvm-project/pull/183371#discussion_r2905495313
[AMDGPU] Fix GFX1250 hazard: S_SET_VGPR_MSB dropped (#184904)
[AMDGPU] Fix GFX1250 hazard: S_SET_VGPR_MSB dropped after
S_SETREG_IMM32_B32 (MODE)
On GFX1250, S_SET_VGPR_MSB immediately after S_SETREG_IMM32_B32
targeting
the MODE register is silently dropped by hardware.
AMDGPULowerVGPREncoding may insert S_SET_VGPR_MSB after a setreg(MODE)
in
Case 2 (size > 12) when imm32[12:19] doesn't match current VGPR MSBs, or
when the next VALU instruction needs different MSBs. Fix by inserting
S_NOP
between the setreg and S_SET_VGPR_MSB to prevent the hazard.
The fix handles two scenarios:
- Case 2 mismatch: S_NOP is inserted directly before S_SET_VGPR_MSB in
handleSetregMode.
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[HLSL] Add parsing for the resource dimension attribute. (#185039)
The resource attribute was added, but the code to be able to parse it
as we do with other resource attributes was missing. This means we are
not able to test the attribute in isolation.
This change adds the parsing for the attribute, and adds more testing
for it.
Assisted-by: Gemini
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fix gh185270 consteval crash (#185511)
replace `cast<VarDecl>` with `dyn_cast_or_null<VarDecl>` in
`HandleImmediateInvocations` to avoid the crash when
`ManglingContextDecl` is a `FunctionDecl` instead of a `VarDecl`.
fixes #185270
[ORC] Flush streams in WaitingOnGraphOpStreamRecorder record ops.
Allows us to get useful recordings out of JIT sessions that crash, or are kept
alive indefinitely. (Note that an 'end' operation will have to be appended to
the output in these cases).
[MLIR][Func] Return nullptr for empty ResultAttrs (#185219)
Fixes #185156
When an empty res_attrs is passed manually, we should still return
nullptr to indicate that no results have attributes.
[OpenMP] Add definitions of FLATTEN and SPLIT to OMP.td
Add the definitions of the "flatten" and the "split" constructs
to the OMP.td file. This will allow the implementation efforts
in clang and flang to proceed independently.
There is no other functionality added in this patch.
[clang-tidy] Fix false negative in `readability-simplify-subscript-expr` when subscripting substituted types (#185570)
This check's bespoke method of avoiding matching
in template instantations is overeager. This commit
changes it to just rely on IgnoreUnlessSpelledInSource
traversal instead. This is the same problem
as in #185559.
[mlir][OpenMP] Allow tile composition (#185380)
The verifier of the TileOp did not allow composition of multiple
transformations out of precaution. However, composition works, therefore
remove the "currently only supports omp.canonical_loop as applyee" check
and add regression tests.
[CIR][AArch64] Add support for the remaining `vceqz` builtins (#185440)
Implement the remaining CIR lowerings for the AdvSIMD (Neon)
`vceqz` intrinsic group (bitwise equal to zero).
Most variants of `vceqz` variant were already supported; this patch
completes the rest of the group [1] that was left as a TODO.
Tests for these intrinsics are moved from:
* test/CodeGen/AArch64/neon_intrinsics.c
* test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
to:
* test/CodeGen/AArch64/neon/intrinsics.c
* test/CodeGen/AArch64/neon/fullfp16,
respectively.
The implementation largely mirrors the existing lowering in
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[TableGen] Do not order register classes based on heap addresses
Compare registers using their enum values instead, which I
suspect was the intention in the first place, since we already
have lexicographical ordering defined for CodeGenRegisters.
This does not cause any changes in .inc files and is likely
NFC, but it's still best to have it be deterministic.
[libclc][CMake] Append target_name to external-funcs test target name (#185639)
Avoid name conflicts when multiple libararies use the same target
triple.
Reapply "Reapply "[clang][ssaf] Add --ssaf-extract-summaries= and --ssaf-tu-summary-file= options"" (#185616)
This reverts commit 9a1c63230b8ad3f19cb624f0d283f7df10957ab7.
1st attempt: #184421
2nd attempt: #185414
Third time the charm!
rdar://172173836
[SPIRV] Add support for emitting DebugFunction debug info instructions
This commit adds support for emitting SPIRV DebugFunction and
DebugFunctionDefinition instructions for function definitions.
[TableGen] Fix inferring missing sub-classes for various subreg indices
We should not imply artificial registers have sub-registers for a given
index even if the class is known to 'fully support' that index.
Fixes crashes reported in
https://github.com/llvm/llvm-project/pull/183371#discussion_r2905495313
[NFC][SPIRV] Extract helper functions in SPIRVEmitNonSemanticDI
This commit extracts reusable helper functions to improve code
organization and reduce duplication. This is a pure refactoring
that does not change behavior.
These helpers will be used in subsequent commits to refactor
emitGlobalDI and add function-level debug info emission.
[SPIRV] Refactor NonSemantic debug info placement logic.
Refactor the logic for determining which NonSemantic.Shader.DebugInfo.100
instructions should be placed in the global section from a whitelist
to a blacklist approach.
[PowerPC][NFC] Clean up code in RegisterInfo.td (#185520)
Just some cleanup work. Moving non register related operands to
PPCOperands.td and PatLeaf def to PPCInstrInfo.td.
