[lldb] Restore autosense for expedited memory-cache address parsing (#211846)
PR #211495 changed the expedited "memory:<addr>=<bytes>" address parse
in SetThreadStopInfo from autosense (radix 0) to explicit base 16.
debugserver sends this address with a "0x" prefix, and
StringRef::getAsInteger only strips that prefix in autosense mode. With
an explicit base 16 the parse stops at the 'x' and fails, so the
expedited stack bytes are never seeded into the L1 memory cache.
Restore BASE_AUTOSENSE here, matching the documented format for this key
(0x hex, 0 octal, otherwise decimal). Fixes TestExpeditedStackMemory.py.
[flang][OpenMP] Check DEFAULT(NONE) on metadirective loop variants (#210172)
Flang does not enforce `DEFAULT(NONE)` for variables referenced in a
loop
associated with a standalone METADIRECTIVE. Consequently, it accepts
invalid
programs when a potentially selectable loop variant specifies
DEFAULT(NONE) but
omits a referenced variable from its data-sharing clauses. This change
checks the
associated loop for each potentially selectable `DEFAULT(NONE)` variant
and
diagnoses missing data-sharing attributes as it does for ordinary OpenMP
loop
constructs.
Standalone metadirectives and their associated loops are separate
parse-tree
nodes. For example:
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clang/AMDGPU: Migrate cc1 tests to subarch triples (3) (#211825)
Rewrite CodeGenHIP cc1 test RUN lines to the new subarch triple form,
dropping the redundant -target-cpu, and regenerate autogenerated CHECK
lines. Tests whose behavior depends on the implicit wave32 default
(which is not enabled by a bare subarch triple) are left for a later change.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[VectorCombine] Fold binop(shuffle(V1, Mask), shuffle(V2, Mask)) -> shuffle(binop(V1, V2), Mask) (#211530)
This is a general, cost driven version of the InstCombine fold (which
was limited to non-length changing cases in #211115), and also permits
folds with multiuse shuffles.
Fixes #210948
clang/AMDGPU: Migrate cc1 tests to subarch triples (2) (#211823)
Rewrite CodeGenCUDA cc1 test RUN lines from `-triple amdgcn...
-target-cpu gfxNNN` to the new subarch triple form, dropping the redundant
-target-cpu.
Autogenerated CHECK lines are regenerated. Tests that intentionally
assert the "target-cpu" function attribute are left unchanged.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Reland "[SimplifyCFG] Simplify switch default branch when branch proves operand value" (#211427)
Original PR: https://github.com/llvm/llvm-project/pull/206597
Revert PR: https://github.com/llvm/llvm-project/pull/211341
Relands abe757b. It was reverted due to my PR failing to update PHINode
entries in the default block, causing invalid IR in certain
circumstances. Original reproducer can be found
[here](https://github.com/llvm/llvm-project/pull/206597#issuecomment-5049789740).
We will now properly remove a PHINode entry if we remove a path from the
switch's block to the default block.
-------------------------------------------------------
If the default branch of a switch proves that there is only one value
that can be sent to the default branch, we can transform the default
branch into an explicit case of the switch. This can assist in further
simplification of the CFG during the simplification loop.
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[IR][NFC] Remove vtables from AnalysisResultConcept (#211810)
Similar to #209414 but for AnalysisResultConcept. This avoids vtables
for every analysis result type.
As a side effect, this improves the build times of PassBuilder.cpp by
~8% due to substantially fewer unique_ptr instantiations (instantiating
unique_ptr is expensive, at least with libstdc++).
clang/AMDGPU: Migrate cc1 tests to subarch triples (1) (#211822)
Mechanically rewrite cc1 test RUN lines from the old
`-triple amdgcn... -target-cpu gfxNNN` form to the new subarch triple
form (e.g. `-triple amdgpu9.00-amd-amdhsa`), dropping the now-redundant
-target-cpu. The subarch encodes the exact target, so the emitted IR no
longer carries a "target-cpu" function attribute; autogenerated CHECK
lines are regenerated accordingly.
This batch covers the small CodeGen, Frontend, Layout, and Preprocessor
test directories.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[flang][cuda] Emit data transfers for whole-array and function-result managed assignments (#211640)
Assignments that read or write device/managed/unified data are
synchronous data transfers on stream 0 that wait for previously launched
kernels. Previously, whole-array managed = managed / host = managed
assignments, and assignments consuming a managed/unified/device function
result, were lowered as host copies (hlfir.assign), which can race an
asynchronous kernel that produced the data.
Emit cuf.data_transfer for these cases. Element-wise (scalar) accesses
and right-hand-side expressions involving managed data remain host
operations (the latter avoids materializing a temporary), and a
whole-allocatable left-hand side keeps reallocation semantics.
[analyzer] Fix false positive in strchr/strrchr with constant args (#210154)
When both the source string and the search target are compile-time
constants, determine the outcome precisely and only emit the feasible
branch (found or not-found).
Handles strchr, strrchr, strchrnul, memchr, strstr, and strpbrk.
Fixes #209905
Assisted by: Kiro-cli
---------
Co-authored-by: Vladislav Aranov <vladislav.aranov at ericsson.com>
[flang] Set nsw on FIRToSCF loop induction increments (#211796)
Example:
```fortran
subroutine sum_loop(a, n)
integer :: a(n), i
do i = 1, n
a(i) = i
end do
end
```
In this code, the DO induction variable `i` is stepped each iteration.
`FIRToSCF` lowered that increment to a plain `arith.addi` with no
overflow flag — unlike the CFG-conversion path (`ControlFlowConverter`),
which marks it `overflow<nsw>` — so LLVM must assume the IV may wrap and
cannot form an affine recurrence, blocking analysis/vectorization of
loops lowered via `fir-to-scf`.
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[SystemZ][z/OS] Add text flag when parsing json (#211805)
This patch adds the text flag when we are opening json files to parse.
This fixes two lit failures on z/OS
[NFC][VPlan][Tests] Some CHECKs cleanup (#211425)
* Fix RUN-line in `VPlan/AArch64/call-decisions.ll` to work with UTC
"; -RUN" was resulting in
```
Error: Failed to update test <...>/call-decisions.ll
Traceback (most recent call last):
File "<...>/update_analyze_test_checks.py", line 228, in main
update_test(opt_basename, ti)
File "<...>/update_analyze_test_checks.py", line 131, in update_test
check_label_prefix = "VPlan for loop in " if regex == common.VPLAN_RE else ""
UnboundLocalError: local variable 'regex' referenced before assignment
```
* Regenerate CHECKs in VPlan/X86/vplan-vp-intrinsics.ll with UTC
* Split VPlan/interleave-and-scalarize-only.ll in two (VPlan/LLVM dumps)
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[Flang][Lower] Flatten signed real sum terms
Second part of generalisations requested in #207377.
Extend real sum reassociation to flatten unparenthesized addition and
subtraction into signed terms. Rebuild split groups with addition and
subtraction while preserving parenthesized subtrees as opaque values.
I did not observe any benchmark result changes as a result of this
patch.
Assisted-by: Codex
AMDGPU: Validate processor is consistent with subarch in TargetID parsing
TargetID::parse checked that a named processor was a recognized GPU, but
not that it was consistent with the triple's subarch. A target id like
"amdgpu9.00-amd-amdhsa--gfx803" was accepted even though gfx803 does not
belong to the amdgpu9.00 subarch, silently taking the processor and
ignoring the mismatched subarch.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
AMDGPU: Handle ISD::POISON in fp16SrcZerosHighBits and isCanonicalized
We can choose to interpret poison however we choose at any point, so just
assume it's a free 0. This defends against regressions when poison is made
legal; it's not yet, so this should not yet have a practically observable
change.
Co-authored-by: Claude (Claude-Opus-4.8)
[VPlan] Drop redundant member LLVM_ABI annotations (#205767)
Classes that are annotated with `LLVM_ABI[_FOR_TEST]` should not have
individual member annotations. This PR drops the redundant member
annotations.
The effort to build LLVM as a dylib is tracked in #109483.
clang/AMDGPU: Migrate cc1 tests to subarch triples (5)
Rewrite OpenMP cc1 test RUN lines to the new subarch triple form,
dropping the redundant -target-cpu, and regenerate autogenerated CHECK
lines. Tests that intentionally assert the "target-cpu" attribute are
left unchanged.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
clang/AMDGPU: Migrate cc1 tests to subarch triples (3)
Rewrite CodeGenHIP cc1 test RUN lines to the new subarch triple form,
dropping the redundant -target-cpu, and regenerate autogenerated CHECK
lines. Tests whose behavior depends on the implicit wave32 default (which
is not enabled by a bare subarch triple) are left for a later change.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
