BSD Commit Log Search

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c

[AMDGPU] Use register pair for PC spill

Change-Id: Ibedeef926f7ff235a06de65a83087c151f66a416

[Clang] Default to async unwind tables for amdgcn

To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.

There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.

Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a

[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU

While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).

Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0

[AMDGPU] Implement CFI for non-kernel functions

This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.

Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>

[AMDGPU] Emit entry function Dwarf CFI

Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.

Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>

[MIR] Error on signed integer in getUnsigned

Previously we effectively took the absolute value of the APSInt, instead
diagnose the unexpected negative value.

Change-Id: I4efe961e7b29fdf1d5f97df12f8139aac12c9219

[Clang] fix crash parsing forbidden attribute args in pragma attributes (#182362)

Fixes #182122

--- 

This patch resolves a crash when parsing `#pragma clang attribute`
arguments for attributes that forbid arguments. The root cause is that
the `#pragma` attribute path doesn't pass `EndLoc` to


https://github.com/llvm/llvm-project/blob/413cafa4624eb37e586e266f44abd64896e1c598/clang/lib/Parse/ParsePragma.cpp#L1982-L1985

unlike the normal attribute parsing flow


https://github.com/llvm/llvm-project/blob/413cafa4624eb37e586e266f44abd64896e1c598/clang/lib/Parse/ParseDeclCXX.cpp#L4706

Without `EndLoc`, argument parsing cannot update the parsed end token

    [11 lines not shown]

Refactor and support multiple affinity register for a task

- Support multiple affinity register for a task
- Move iterator loop generate logic to OMPIRBuilder
- Extract iterator loop body convertion logic
- Refactor buildAffinityData by hoisting the creation of affinity_list
- IteratorsOp -> IteratorOp
- Add mlir to llvmir test

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>

[cmake] Don't use PCH when clang-cache launcher is used (#183620)

Fix incremental build failure when using PCH build and clang-cache
together.

[MLIR][XeGPU] Add distribution pattern for xegpu.load & store for sg to wi pass (#181917)

This PR adds distribution pattern for xegpu.load & store ops for the new
sg-to-wi pass

Update test case to account for ALIAS syntax change.

[SystemZ] Emit external aliases for indirect function descriptors in the ADA section

This is the last of the three patches aimed to support indirect symbol handling for
the SystemZ backend.

An external alias is emitted for indirect function descriptors within the ADA
section, rather than a temporary alias, while also setting all of the appropriate
symbol attributes that are needed for the HLASM streamer to emit the correct XATTR
and ALIAS instructions for the indirect symbols.

Moreover, this patch updates the `CodeGen/SystemZ/zos-ada-relocations.ll` test
as the ADA section is currently the only user of indirect symbols on z/OS.

Fix clang-format.

[Hexagon] Fix assert on sign-bit CONST32 immediates (#182118)

This patch fixes a HexagonConstPropagation assert when evaluating
sign-bit CONST32/CONST64 immediates (e.g. 0x80000000) after ConstantInt
stopped implicitly truncating, by allowing truncation for that signed
case.

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c

[AMDGPU] Implement CFI for CSR spills

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>

[AMDGPU] Use register pair for PC spill

Change-Id: Ibedeef926f7ff235a06de65a83087c151f66a416

[AMDGPU] Implement CFI for non-kernel functions

This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.

Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>

[CIR][AArch64] Add lowering for vaba_* and vabd_* builtins (1/N)

Add CIR lowering for the following AdvSIMD (NEON) intrinsic families:

* vabd_*  – Absolute difference
  https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#absolute-difference

* vaba_*  – Absolute difference and accumulate
  https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#absolute-difference-and-accumulate

Tests for these intrinsics were split out from:
  test/CodeGen/AArch64/neon-intrinsics.c

and moved to:
  test/CodeGen/AArch64/neon/intrinsics.c

The following helper hooks were adapted from the ClangIR project:
  * getNeonType, emitNeonCall, emitNeonCallToOp.


    [4 lines not shown]

!fixup address latest comments, thanks

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[clang][ssaf] Improve serialization for Model types and error messages in `JSONFormat`

This changes fixes the diagnostic infrastructure in `JSONFormat`
implementation to pass model objects (`EntityId`, `EntityLinkage`,
`BuildNamespace`, `NestedBuildNamespace`, `SummaryName`) directly to
`ErrorBuilder` instead of manually extracting their components. This
relies on existing `llvm::format_provider` specializations for these
objects.

To support consistent string conversion for `BuildNamespaceKind` and
`EntityLinkageType`, across both serialization and `operator<<`,
`toString`/`fromString` functions have been introduced in an internal
header `ModelStringConversions.h`.

`EntityLinkage::LinkageType` is promoted to a standalone enum class
`EntityLinkageType` at namespace scope, following the same pattern as
`BuildNamespaceKind`.

Tests have been added for `operator<<` and `format_provider` for all

    [2 lines not shown]

[OpenMP] Remove NVPTX local addrspace on parameters (#183195)

In CGOpenMPRuntimeGPU::translateParameter, reference-type captured
variables were translated to pointer parameters with two address-space
annotations:

1. LangAS::opencl_global on the pointee (for map'd variables), which
correctly produces ptr addrspace(1) in NVPTX IR.
2. getLangASFromTargetAS(NVPTX_local_addr=5) on the pointer itself,
annotating the parameter as living in NVPTX local (stack) memory.

The second annotation is incorrect at the Clang type-system level:
EmitParmDecl only supports parameters to be in LangAS::Default (or the
special cases for OpenCL).

Temporarily add an assert in EmitParmDecl that catches parameters with
non-default address spaces in non-OpenCL compilations, and fix the
violation by dropping the NVPTX_local_addr addAddressSpace call.


    [8 lines not shown]