[msan] Correctly handle llvm::fake_use (as a no-op) (#229591)
The fake_use intrinsic (used by -fextend-variable-liveness) was being
strictly handled (i.e., check that the parameter is fully initialized),
which led to false positives
(https://github.com/llvm/llvm-project/issues/225425). This patch solves
the issue by silently not instrumenting fake_use, since they are, by
definition, not real uses and therefore cannot lead to
use-of-uninitialized-memory.
Fixes: #225425
[libc][math] Improve accuracy for exp*f float-only implementations. (#227881)
Pure Estrin's scheme pushes the rounding errors a bit more than 1 ULP on
non-FMA targets for these functions.
[SelectionDAG] Add ATOMIC_LOAD_FMAXIMUMNUM/FMINIMUMNUM to SDNode::getOperationName. (#229566)
Reorder the other FP min/max nodes to locally match the order in
ISDOpcodes.h.
[SelectionDAG] Add static_assert for ISD::BUILTIN_OP_END to SDNode::getOperationName to encourage updating when opcodes are added. (#229573)
Also add missing case for DEACTIVATION_SYMBOL.
GlobalISel: Use integer types when splitting loads in lowerLoad (#229544)
lowerLoad built the split pieces using the destination type with the
element size changed, which preserved floating-point types. An
unaligned f64 load was decomposed into G_ZEXTLOAD, G_SHL and G_OR on
f32 and f64, which then crashed in AMDGPU RegBankLegalize. Build the
pieces as integers and bitcast to a non-integer result type, as
lowerStore already does.
The pieces are now consistently integer typed, which allows more
constants to be CSEd in the existing tests.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[CIR] Implement ctor-try-body rethrow (#229436)
This came up in a test suite, but we weren't properly re-throwing
exceptions when they were in the body of a constructor's try-body. This
patch mirrors classic-codegen's behavior reasonably well, implementing
this behavior properly.
Side note: this mirrors classic codegen's behavior of including
dtor-try-bodies too, but that isn't implemented yet, so those will just
be an NYI for now.
[Bazel][mlir] Fixes build failures (#229605)
Fixes build failures following commit 4c520f2ae12f and commit
155462f440ff where ROCDLTargetInfo was introduced and referenced across
ROCDL/AMDGPU passes.
[lldb] Add LanguageRuntime::FixupVariableLocation (NFC) (#229602)
Some languages store a variable in a location whose indirection level is
only known at runtime. Swift, for example, emits resilient globals into
a fixed-size buffer; a value that doesn't fit is boxed on the heap and
the buffer holds a pointer to the box. Whether the value fits depends on
the runtime layout of a type, so the compiler can't encode it in the
DWARF location expression.
This patch adds a LanguageRuntime hook that ValueObjectVariable calls
after evaluating a variable's location, so the runtime can adjust it.
The default implementation does nothing.
Assisted-by: Claude
[Bazel] Add Support dependency to amdgpu_tests (#229597)
Fixes amdgpu_tests bazel layering failure introduced in commit
45ebdb6a55db, where AMDGPUUtilsTest.cpp includes
llvm/Support/Compiler.h.
[Bazel][libc] Update platform_file to depend on dup3 (#229595)
Fixes bazel build failure introduced in commit 64d83dcba1cb, where
file.cpp switched from using dup2 to dup3.
AMDGPU/GlobalISel: Use integer types when narrowing loads and stores
The narrowScalar mutation for loads and stores produced untyped scalars.
For FP-typed values this resulted in an untyped G_OR in the lowerLoad
expansion for unaligned private accesses, which failed to select.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Fix true16 losing 16-bit subreg operands
Folding a true16 v2s copy such as %2:sreg_32 = COPY %1.lo16 rewrites
its users to read %1.lo16 and relies on legalizeOperandsVALUt16 to
legalize the narrower operand. PHI and REG_SEQUENCE operands have no
register class, so it skipped them, leaving a 16-bit input in a VGPR_32
PHI or a 32-bit REG_SEQUENCE slot. DetectDeadLanes then marked the PHI
input undef and the defining load was deleted.
Widen such operands with a REG_SEQUENCE in legalizeOperandsVALUt16,
which runs both when the copy is folded and when the user is moved to
the VALU. This miscompiled uniform i16 loads feeding PHIs on gfx1250.
Change-Id: I9ddee5b11ff8503f4b2b1d1c4c776a12b270d968
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
[RISCV] Fold (sub 0, (srl (and X, (1 << ShAmt)), ShAmt)) -> (sra (shl X, ShAmt2), bits-1) (#229509)
Improves codegen of is.fpclass+select. The AND to test bits of
is.fpclass may get turned into and+srl while the select emits a
neg. Isel will turn the and+srl into shl+srl but it's too late to
fold the neg.
Assisted-by: Claude
AMDGPU/GlobalISel: Use integer types when narrowing loads and stores
The narrowScalar mutation for loads and stores produced untyped scalars.
For FP-typed values this resulted in an untyped G_OR in the lowerLoad
expansion for unaligned private accesses, which failed to select.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
GlobalISel: Use integer types when splitting loads in lowerLoad
lowerLoad built the split pieces using the destination type with the
element size changed, which preserved floating-point types. An
unaligned f64 load was decomposed into G_ZEXTLOAD, G_SHL and G_OR on
f32 and f64, which then crashed in AMDGPU RegBankLegalize. Build the
pieces as integers and bitcast to a non-integer result type, as
lowerStore already does.
The pieces are now consistently integer typed, which allows more
constants to be CSEd in the existing tests.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[LV] Use frozen start values from the main plan directly (NFC). (#229571)
Only freeze possibly-poison start values of FindIV reductions in the
main plan. When preparing the epilogue plan, set the start operand of
its FindIV reduction results directly to the value frozen for the main
plan, instead of creating Freeze recipes in the epilogue plan and
replacing them later via a map. This leaves only VPExpandSCEVRecipes to
replace in the epilogue plan's entry.
[CIR] Fix use-after-free in BrOp::canonicalize (#229191)
BrOp::canonicalize took the branch's destination operands as an
OperandRange, erased the branch, and then passed the range to
mergeBlocks. The range points into the branch's operand storage, which
eraseOp frees, so mergeBlocks read freed memory whenever the merged
block had arguments. Valgrind reports it on the new test:
```
Invalid read of size 8
at mlir::ValueRange::dereference_iterator
by mlir::RewriterBase::inlineBlockBefore
by cir::BrOp::canonicalize
Address ... is 136 bytes inside a block of size 144 free'd
by mlir::RewriterBase::eraseOp
by cir::BrOp::canonicalize
```
It goes unnoticed with glibc malloc, which usually leaves the freed
operands intact. Copy the operands before erasing the branch.
[msan][test] Add MSan case to clang/test/CodeGen/fake-use-sanitizer.cpp (#229564)
Regression test for https://github.com/llvm/llvm-project/issues/225425,
showing that MSan incorrectly strictly handles fake_use.
[mlir] Migrate AMDGPU/ROCDL to targets, not chipset versions (#223563)
**migration tl;dr:** Replace usages of `amdgpu::Chipset` with
`ROCDL::TargetInfo`, ideally move from `chipset=` to `arch=`. If you
don't use upstream pipelines, call
'TargetInfo::migrateArchFeaturesToModuleFlags` at the appropriate
location.
Further note: if you've got a build pipeline that's getting a `gfxXXX`
name from something like `rocm_agent_enumerator`, using a full triple
name like the ones you get from `rocminfo` is preferred.
`amdgpu::Chipset` was an awkward hack that was hard to keep up to date
with changes in the compiler/new architectures, and didn't properly
support generic targets (and has been strongly disfavored by the
compiler team).
This PR replaces `amdgpu::Chipset` with `ROCDL::TargetInfo`, a
structure that uses LLVM's TargetParser and the underlying LLVM
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[Bazel] Add FlowSensitive/Models headers to clang:analysis (#229578)
Fixes bazel build failure introduced in commits e03123a63162 and
f0d6540d5307, where GtestModelHelpers.h was added to
lib/Analysis/FlowSensitive/Models and included in Models/*.cpp.
Take a different approach
HLASM derives the AMODE from the RMODE if no AMODE is explicitly
given. The same can be done in the GOFF writer, simplifying the
coding a lot.
[CodeGen] Drop dead SlotIndexes before allocation
SlotIndexes keeps the index list entry of an erased instruction and only
clears its instruction pointer. Live range sizes are measured in slot
indexes and greedy ranks ranges by size, so the leftovers inflate some
ranges more than others and reorder allocation, spilling heavily on
register-starved functions.
Add SlotIndexes::compactIndexes() to erase them. Erased entries are
unlinked, so LiveIntervals first reports the indexes it holds via
appendReferencedIndexes().
Off by default behind -greedy-compact-slot-indexes, since it changes
allocation across much of the test suite.
