[BranchFolding] Ignore debug instructions in singleton cond branch check (#228715)
DBG_VALUE was counted when checking for a single-branch block, so the
duplicate branch was kept only under -g.
Fixes #228713
Assisted-by: Claude Opus 5.5
[mlir][RemoveDeadValues] Replace dead function argument uses with poison (#208881)
Dropping all uses of a dead function argument can leave null operands in
surviving side-effecting operations in unreachable code.
Subsequent canonicalization may then crash while folding the invalid
operation.
This PR replaces the remaining uses with `ub.poison` before erasing the
argument and add a regression test.
Fixes #206920, fixes #203226
[MLIR] Guard against overflow when simplifying affine expressions. (#228010)
Fixes https://github.com/llvm/llvm-project/issues/224577.
Current canonicalizer may lead to signed integer overflow while
simplifying affine expressions. This change adds overflow checks and
returns `failure()` when an overflow is detected.
[test][llvm-ar] Restore file permissions in error-opening-permission.test (#230361)
error-opening-permission.test sets chmod 100 on %t/permission.b to test
EACCES handling, leaving an unreadable file in the build directory after
the test finishes. This causes permission errors for tools like rsync
when copying the build directory.
Restore permissions with chmod 700 at the end of the test, matching
llvm/test/tools/llvm-ranlib/error-opening-permission.test.
Assisted-by: Gemini
[clang][CIR] Add tests for SVE ORV intrinsics (#230082)
adds CIR tests for svorv (plain SVE) intrinsics.
Moves and adapts sve-intrinsics/acle_sve_orv.c to sve/orv.c.
Part of #223963
[VPlan] Build packs from lane values in replicateByVF (NFC). (#231040)
Previously materializePacksAndUnpacks created single-operand
BuildVectors for all per-lane definitions with vector users or users
inside replicate regions, which replicateByVF later extended with the
per-lane values. Recipes in replicate regions then accessed their lanes
via extractelement(BuildVector, Lane), which had to be folded by several
BuildVector look-throughs.
Instead, create the BuildVectors directly in replicateByVF from the
per-lane definitions, only for users that need a vector. Users inside
replicate regions keep using the original definition until the replicate
regions are dissolved; the resulting lane extracts are then replaced by
the corresponding per-lane definitions before the original definition is
removed. As BuildVectors are only created with all lanes, they now
always use only the first lane of their operands.
This removes a number of indirections and folds, and simplifies the
code.
[orc-rt] Add Session instance symbols, SPS CI to look them up (#231043)
Objects created at runtime (e.g. service instances) have no symbols
under the standard object models, so the controller has no way to find
them by name. Instance symbols fill that gap:
Session::addInstanceSymbols registers (name, address) pairs for such
objects, and Session::lookupInstanceSymbols resolves a SymbolLookupSet
against them, with the same missing-symbol semantics as
SimpleSymbolTable::lookup. Duplicate handling follows
SimpleSymbolTable::addUnique: a batch containing a conflicting
definition is rejected as a whole.
The new orc_rt_ci_sps_Session_lookupInstanceSymbols wrapper exposes the
lookup to the controller. It is registered by sps_ci::addSession, which
sps_ci::addAll now includes.
TableGen: Cache resolved class instantiations
The same class instantiation is often referenced many times in one
record, and each reference was resolved again from scratch along with
everything nested in its arguments. Cache the results in MapResolver and
RecordResolver. The cache is cleared when the mappings change, and is
bypassed while a mapped variable is being resolved.
Nested instantiations are resolved through a TrackUnresolvedResolver,
which does not change the result. These share the cache of the
underlying resolver, which also records whether any references were left
unresolved so the trackers can be updated on a hit.
Gigainstructions executed by llvm-tblgen --null-backend
before after
AMDGPU.td 71.75 18.22 -74.6%
X86.td 6.10 6.15 +0.8%
AArch64.td 3.28 3.32 +1.3%
[3 lines not shown]
TableGen: Skip resolving values that cannot change
Lists, dags, bits and arguments made only of leaf values always resolve
to themselves, but resolving them still walked every element. Record
this when they are created and return early.
Gigainstructions executed by llvm-tblgen --null-backend
before after
AMDGPU.td 79.12 71.73 -9.3%
X86.td 6.25 6.12 -2.1%
AArch64.td 3.40 3.28 -3.7%
RISCV.td 8.34 8.19 -1.8%
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Use DenseMap for the IntInit pool
Gigainstructions executed by llvm-tblgen --null-backend
before after
AMDGPU.td 79.34 79.13 -0.3%
X86.td 6.30 6.25 -0.7%
AArch64.td 3.43 3.41 -0.6%
RISCV.td 8.40 8.34 -0.7%
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[VPlan] Use getFastMathFlagsOrNone in VPIRFlags::applyFlags (NFC) (#231036)
applyFlags hand-rolled the same field-by-field FastMathFlagsTy to
FastMathFlags conversion as getFastMathFlagsOrNone. Use the latter
together with copyFastMathFlags.
AMDGPU: Use TargetSubtarget.td in TargetDef tablegen tests (#231018)
The -gen-amdgpu-target-def tests only need the subtarget and processor
classes. Include TargetSubtarget.td instead of Target.td, which also
checks that it works standalone, and drop the unneeded dummy Target.
The 14 llvm-tblgen RUN lines each parsed Target.td, which costs 1.29 G
instructions:u (Release+asserts); TargetSubtarget.td costs 0.005 G.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[gn] port c90b6414e607 (mlgo EmitC models) (#231035)
Ports ab547095ead5 since it's needed unconditionally after c90b6414e607.
Register only the checked-in, pre-lowered _test_inc test model.
Lowering .mlir models is still not implemented in the GN build.
[gn] make write_file.py replace literal \n with newlines (#231034)
Like write_cmake_config.py. This makes it possible to write multi-line
generated headers from an action(), which is needed for the next commit.
As demo, update the only current existing caller to write a
trailing newline. This matches the CMake build.
[AMDGPU] Limit the fmul fusion discount to a matching context type
The fmul is free when its context instruction feeds a fusable fadd or
fsub. A vector fmul priced with a scalar lane as the context inherits
that fusion only when it is emitted lane by lane. On a packed type the
scalar user does not show that the vector fmul feeds a vector fadd, and
products extracted into a scalar fadd chain keep the packed fmul while
the fma is lost.
[llubi] Use the correct poison representation for byte values (#231028)
We always use `ByteValue` to represent `bN poison`.
The test is generated by DeepSeek-V4.1-Flash. Looks like there is no
other bug like this.
RegAllocGreedy: Avoid unused block frequency lookups in hint recoloring (#231027)
collectHintInfo looked up the block frequency of every copy, but the
frequencies are only used for the profitability check when the register
would be recolored. Most visited registers are already assigned the
target register, so record the block and look the frequency up only
when it is needed. Also use a SmallDenseSet for the visited set, which
otherwise falls back to a std::set on anything but tiny components.
On a stress test with 4000 critical edges into a block with 4 PHIs,
this roughly halves the time in Greedy.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[RISCV][P-ext] Change RISCVISD::SATI to use [1,bitwidth] for the immediate. (#230377)
This matches the intrinsics and assembly syntax for the instruction.
Assisted-by: Claude
AMDGPU: Use TargetSubtarget.td in TargetDef tablegen tests
The -gen-amdgpu-target-def tests only need the subtarget and processor
classes. Include TargetSubtarget.td instead of Target.td, which also
checks that it works standalone, and drop the unneeded dummy Target.
The 14 llvm-tblgen RUN lines each parsed Target.td, which costs 1.29 G
instructions:u (Release+asserts); TargetSubtarget.td costs 0.005 G.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
