CodeGen: Track shrinkToUses live-out blocks by block number
extendSegmentsToUses created a SmallPtrSet to track which predecessors
were already queued as live-out. On large functions it outgrows the
inline storage and rehashes each time. Keep a per-block-number tag
array in LiveIntervals and bump the current tag on each call, so a
lookup is a direct index and resetting the set is free.
Instructions for llc -O3 -filetype=null over 40 CTMark x86_64 bitcode files:
total -0.21%
consumer-typeset z06 -1.79%
ClamAV mspack -0.43%
tramp3d-v4 -0.38%
kimwitu++ kimwy -0.35%
SPASS rules-red -0.29%
lencod mbuffer -0.27%
SPASS rules-inf -0.22%
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[MLIR][Python] Don't terminate when a from_cpp type caster raises (#237010)
The `type_caster<Mlir*>::from_cpp` functions in `NanobindAdaptors.h` are `noexcept`, but they call into Python. So wrap their bodies in a small helper. The helper catches `nanobind::python_error`, restores it as the Python error indicator and returns an invalid handle.
Assisted by: Claude
[LoongArch] Fix the cost of loading and storing sub-128-bit vectors (#234458)
On LA64, vectors narrower than 128 bits are widened, and a load or store
of one is a single instruction: FLD.{S/D} or VLDREPL.{B/H} for loads and
VSTELM.{B/H/W/D} for stores. The generic model costs them as scalarized,
e.g. 5 for <4 x i16> and 9 for <8 x i8>, which makes narrow VFs look
much more expensive than they are.
This matters once the vectorizer considers VFs past the widest type. For
example, the GSM Autocorrelation loop (9 x i64 multiply-accumulate over
i16 taps) would otherwise pick VF8 on LSX, which needs more vector
registers than available and spills every iteration, instead of VF4. On
LA664:
VF8: 1.081s
VF4: 0.856s
LA32 is left unchanged, as it splits 64-bit loads and doesn't use
VSTELM.{W/D} for stores.
[VPlan] Drop poison generating flags from replicated clones (#234901)
Only noticed this after already reviewing #234613, we also need to drop
the flags for much the same reason.
[CIR] Add the cir-offload-merge tool
Add a standalone tool that moves CIR modules into and out of an offload
container:
* `-combine` takes a host CIR module and one or more device CIR modules,
each paired with its offload bundle ID through `-targets`, and nests them
in a module marked `cir.offload.container`. The host module goes first, as
the container verifier requires. Each nested module is tagged with
`cir.offload.kind` and `cir.offload.bundle_id`.
* `-split` takes a container and writes each requested target's module to
its own file. Modules are matched to the requested targets by their
bundle ID, using clang-offload-bundler's target ID compatibility rules.
Each split module is printed as a top-level module, so its type aliases
are kept.
The tool runs no passes on the container. It is driven by hand for now:
driver integration and the passes that work on the container are left to
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[CIR] Add cir.offload.bundle_id attribute
A follow-up tool combines per-target CIR modules into an offload container
and splits them back out. Splitting needs to know which compilation each
nested module came from, and `cir.offload.kind` only says host or device.
The target triple is not enough either: a multi-arch HIP build produces
several device modules with the same triple that only differ in their
target ID, e.g. `gfx90a:xnack+` and `gfx90a:xnack-`.
Add `cir.offload.bundle_id`, a string attribute carrying the module's
offload bundle ID in the format clang-offload-bundler uses
(`<offload kind>-<target triple>[-<target ID>]`).
The verifier checks that the attribute is a non-empty string attached to
a `builtin.module`, and that bundle IDs are unique within an offload
container. The attribute is optional, so existing containers stay valid.
[Verifier][RISCV] Reject i64 vsetvli intrinsics on rv32
The scalar types need to fit in XLEN. i32 intrinsics on rv64 seem to work fine.
Fixes #237048.
Assisted-by: Claude Opus 5.5
[mlir][scf] Revisit affected loops during range folding (#230961)
Folding an outer loop can expose a range-folding opportunity in an inner
loop that has already been visited. Convert loop-range folding to an
`OpRewritePattern<scf::ForOp>` and use `applyPatternsGreedily` on the
pass root so the greedy driver revisits affected loops within one pass
invocation.
Fixes #228463
[LLDB] Use `-fastproxy` when building swig bridge without limited python API (Reland) (#236247)
Per [swig
docs](https://www.swig.org/Doc4.4/Python.html#Python_fastproxy).
Additionally, the `-olddefs` option is included so that the doc comments
still function. The latter change makes importing the LLDB module a bit
slower, but makes every method call a good bit faster.
Depends on: #235909
Co-authored-by: Walnut <walnut356dev at gmail.com>
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
[llvm-ir2vec] Parse library options into LLVMContext (#237056)
Migrate away from the to-be-deprecated ParseCommandLineOptions, which
sets the global values.
[lld-macho] Build the export trie by edges, not bytes (#236626)
Emit singleton suffixes directly and scan common prefixes in one pass,
avoiding repeated byte-wise partitioning. This speeds up builds that
emit large export tries.
Reland of #234857, which was accidentally merged into a stale stack
branch instead of main. Same diff, already reviewed there.
🤖 Generated with [Claude Code](https://claude.com/claude-code)
[LoongArch] Use XVPERMI.Q for lane-crossing LASX shuffles (#232209)
Introduce XVPERMI.Q ISD node in TableGen for add lowering for 256-bit
lane shuffle.
Also extend lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle to support dual
input permute and shuffle, so that splice like this:
```
%2 = shufflevector <8 x i32> %0, <8 x i32> %1,
<8 x i32> <i32 7, i32 8, i32 9, i32 10,
i32 11, i32 12, i32 13, i32 14>
```
could be lowered to:
```
(XVBSLL_V $xr2, $xr1, 4)
(XVPERMI_Q $xr1, $xr0, 33)
(XVBSRL_V $xr0, $xr1, 12)
(XVOR_V $xr0, $xr2, $xr0)
```
All permute that destination lane comes from maximum of two source lanes
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CodeGen: Replace TargetOptions::DebuggerTuning with module flag
Read the debugger tuning from the module's "debugger-tuning" flag instead of
TargetOptions. Delete the now-dead -debugger-tune= cl::opt and the
TargetOptions::DebuggerTuning field.
Update the tests relying on it to directly use the module flag. The cases
that exercise multiple values do a text substitution to swap the value.
Alternatively this could be changed to synthesize the module flag in the
llc flag like some of the other widely used module flags do.
Co-authored-by: Claude Sonnet 5 <noreply at anthropic.com>
[docs] Add AI policy to HowToSubmitABug (#236946)
We've been getting a lot of AI-generated bug reports lately; we should
have a clear description of expectations for anyone submitting such
reports.
This reflects the current version of the policy, not the one proposed in
the "Forbid AI-generated communication" RFC. We can adjust the text when
that is approved.
[ASan][test] Disable StrArgsOverlapTest on Android AArch64 (#237043)
Temporarily disable `AddressSanitizer.StrArgsOverlapTest` on Android
AArch64 while waiting for #237000.
On Android 17 (API 37) AArch64, Bionic's `strcat` calls `strcpy at plt(dst
+ strlen(dst), src)`, so `strcat(str, str + 10)` in `StrArgsOverlapTest`
re-enters `INTERCEPTOR(strcpy)` with `to == from` and fails with
`strcpy-param-overlap` on
https://lab.llvm.org/staging/#/builders/sanitizer-x86_64-linux-android.
Assisted-by: Gemini
[MachineVerifier] Track defs inside bundles
Reuse LivePhysDefs instead of rescanning the bundle, and skip the
undefined-register check on BUNDLE header uses.
[KnownFPClass][NFC] Remove isKnownNeverZero helper to encourage proper denormal handling (#236625)
Removes `isKnownNeverZero()`, `isKnownNeverPosZero()`, and
`isKnownNeverNegZero()` which only compare against the literal `+-0.0`,
`+0.0`, and `-0.0` respectively. This encourages the use of
`isKnownNeverLogicalZero(Mode)` and friends which properly account for
the input denormal mode.
If input denormals are properly handled, you can still compare against
`+-0.0` literals via the generic `isKnownNever(fcZero)`.
AMDGPU: Fold global address into subregister use with lo/hi relocation
Split 64-bit relocations into the 32-bit halves when applying a
subregister extract, similar to how immediates are modified when
folding. The same split is applied when 64-bit mov pseudos are
expanded.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[lldb] Copy valid breakpoint overrides from the dummy target (#235834)
`Target::PrimeFromDummyTarget` copied a breakpoint override into a new target only when `Validate` failed, because an `llvm::Error` converts to true on failure. Overrides registered on the dummy target therefore never reached later targets. Copy the overrides that validate, and log the error of those that don't.
Rename `Validate` to `HasErrors`, still returning an `llvm::Error`, so call sites read the right way round. It now also checks that the override's class exists, so adding an override with a missing class fails with a useful error instead of failing on every matching breakpoint.
Test both: an override on the dummy target applies to targets created later, and `test_bad_values` now covers a missing class.
