LLVM/project ccbcda5llvm/unittests/CAS OnDiskKeyValueDBTest.cpp OnDiskGraphDBTest.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+3-3llvm/unittests/CAS/OnDiskKeyValueDBTest.cpp
+1-1llvm/unittests/CAS/OnDiskGraphDBTest.cpp
+4-42 files

LLVM/project 70f7039llvm/lib/Target/RISCV RISCVExpandAtomicPseudoInsts.cpp RISCVInstrInfoA.td, llvm/test/CodeGen/RISCV atomic-rmw.ll atomic-signext.ll

[RISCV][LLVM] Enable atomics for 'Zalrsc' (#163672)

The 'A' atomics extension is composed of two subextensions, 'Zaamo'
which has atomic memory operation instructions, and 'Zalrsc' which has
load-reserve / store-conditional instructions.
    
For machines where 'Zalrsc' is present, but 'Zaamo' is not, implement
and enable atomics memory operations through pseudo expansion. Updates the
predication and lowering control to be more precise about which 'Zaamo'/'Zalrsc'
feature was truly requisite.
    
There will be no functional change to subtargets supporting 'A', while
allowing 'Zalrsc' only subtargets to utilize atomics at an increased code
footprint.
DeltaFile
+9,014-0llvm/test/CodeGen/RISCV/atomic-rmw.ll
+2,644-0llvm/test/CodeGen/RISCV/atomic-signext.ll
+406-0llvm/test/CodeGen/RISCV/atomic-load-store.ll
+204-31llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+102-0llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll
+69-11llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+12,439-429 files not shown
+12,520-5015 files

LLVM/project 311a199llvm/test/CodeGen/X86 bitcnt-big-integer.ll

[X86] Add ctpop/ctlz/cttz test coverage for very large integers (#164450)

Inspired by #164275
DeltaFile
+3,021-0llvm/test/CodeGen/X86/bitcnt-big-integer.ll
+3,021-01 files

LLVM/project 3155b05clang/lib/CIR/CodeGen CIRGenFunction.cpp CIRGenExpr.cpp, clang/test/CIR/CodeGen builtin_inline.c

[CIR] Implement inline builtin functions (#163911)

This patch implements the handling of inline builtin functions in CIR.
There is a known limitation in CIR where direct calls to shadowed inline
builtin functions are generated instead of the intrinsic. This is
expected to be fixed by the introduction of the nobuiltin attribute in a
future patch.
DeltaFile
+91-0clang/test/CIR/CodeGen/builtin_inline.c
+43-0clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+19-1clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+11-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+164-14 files

LLVM/project b1322c4compiler-rt/cmake builtin-config-ix.cmake config-ix.cmake

[compiler-rt] [CMake] Skip find_darwin_sdk_dir on disabled platforms (#163591)

find_darwin_sdk_dir can be slow, especially if xcrun does not
immediately find the corresponding SDK (i.e. because it is missing).

This skips those checks if the user has already set the corresponding
CMake variable to disable the platform anyway.
DeltaFile
+16-8compiler-rt/cmake/builtin-config-ix.cmake
+12-6compiler-rt/cmake/config-ix.cmake
+28-142 files

LLVM/project 55f77fcllvm/utils update_mc_test_checks.py

[Utils][NFC] Clean up update_mc_test_checks.py.

Refine the code a bit to make it easier to comprehend the logic.
DeltaFile
+21-37llvm/utils/update_mc_test_checks.py
+21-371 files

LLVM/project fb870cbllvm/unittests/ExecutionEngine/Orc WaitingOnGraphTest.cpp

[ORC] Fix unused variable warning (#164444)

This fixes a potentially unused variable that's only used in an assert.

This is a fix for #164340.
DeltaFile
+2-0llvm/unittests/ExecutionEngine/Orc/WaitingOnGraphTest.cpp
+2-01 files

LLVM/project 0c0ad11flang/lib/Lower OpenACC.cpp, flang/test/Lower/OpenACC acc-declare-common-in-function.f90

[acc][flang] lowering of acc declare on COMMON variables (#163676)

COMMON variables are treated as locals and lowered to structured
declares currently. This is incorrect because variables that are COMMON
should be treated as globals. Added implementation to treat these
variables differently.
DeltaFile
+178-51flang/lib/Lower/OpenACC.cpp
+40-0flang/test/Lower/OpenACC/acc-declare-common-in-function.f90
+218-512 files

LLVM/project 3161e16clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenAtomic.cpp

[CIR] Atomic fetch operation (#161631)

This patch adds CIR support for atomic fetch-and-update operations,
including the intrinsic functions `__atomic_fetch_<binop>`,
`__atomic_<binop>_fetch`, and `__c11_atomic_fetch_<binop>`, where
`<binop>` could be `add`, `sub`, `max`, `min`, `and`, `or`, `xor`, and
`nand`.
DeltaFile
+523-0clang/test/CIR/CodeGen/atomic.c
+119-24clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
+141-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+73-0clang/include/clang/CIR/Dialect/IR/CIROps.td
+15-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+7-0clang/test/CIR/IR/invalid-atomic.cir
+878-246 files

LLVM/project 6d5dea6llvm/lib/CodeGen/SelectionDAG LegalizeFloatTypes.cpp, llvm/lib/Target/ARM ARMISelLowering.cpp

[ARM][SDAG] Add llvm.lround half promotion. (#164235)

Similar to #161088, add llvm.lround and llvm.llround promotion.
DeltaFile
+33-10llvm/test/CodeGen/ARM/lround-conv.ll
+9-0llvm/test/CodeGen/ARM/llround-conv.ll
+2-0llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+1-0llvm/lib/Target/ARM/ARMISelLowering.cpp
+45-104 files

LLVM/project 23339c4llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/hlsl-resources TypedBufferLoad.ll

[SPIR-V] Use `OpImageFetch` instead of `OpImageRead` when loading from read-only `Buffer` resource. (#163626)

Currently, the spir-v validator fails if `OpImageRead` instruction is
used when loading from read-only `Buffer`.
### Unit Test
```hlsl
RWBuffer<uint> rwbuff;
Buffer<uint>  buff;

[numthreads(1,1,1)]
void main() {
    rwbuff[99] = buff[98];
    rwbuff[97] = rwbuff[96];
}
```
This also unblocks adding a test case that adds a special capability
when using a non-uniform index on `Buffer` arrays.
(https://github.com/llvm/llvm-project/pull/162540).

Resolves https://github.com/llvm/llvm-project/issues/162891
DeltaFile
+29-21llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+43-0llvm/test/CodeGen/SPIRV/hlsl-resources/TypedBufferLoad.ll
+72-212 files

LLVM/project 5b3416clibc/include/arpa inet.yaml, libc/src/arpa/inet inet_aton.cpp inet_aton.h

[libc] implement `inet_aton` (#162651)

This patch adds the implementation for `inet_aton` function. Since this
function is not explicitly included in POSIX, I have marked it with
`llvm_libc_ext`. It is widely available and commonly used, and can also
be used to implement `inet_addr`, which is included in POSIX.
DeltaFile
+92-0libc/test/src/arpa/inet/inet_aton_test.cpp
+57-0libc/src/arpa/inet/inet_aton.cpp
+21-0libc/src/arpa/inet/inet_aton.h
+13-0libc/src/arpa/inet/CMakeLists.txt
+11-0libc/test/src/arpa/inet/CMakeLists.txt
+9-1libc/include/arpa/inet.yaml
+203-14 files not shown
+213-110 files

LLVM/project 554ea40clang/include/clang/Sema SemaBase.h Sema.h, clang/lib/Sema SemaBase.cpp SemaRISCV.cpp

[NFC][Clang][Diagnostics] Remove the DeferHint parameter of Diags(...) in favour of DeferHintRAII (#161517)

The `DeferHint` was misused at several callsites, where a `Decl*` was
implicitly casted to `bool`.

This patch proposes removing the `DeferHint` parameter and relying on
`DeferDiagsRAII` to set if Clang should defer the diagnostics.
DeltaFile
+7-10clang/lib/Sema/SemaBase.cpp
+8-8clang/lib/Sema/SemaRISCV.cpp
+8-5clang/lib/Sema/SemaOverload.cpp
+5-6clang/lib/Sema/Sema.cpp
+3-6clang/include/clang/Sema/SemaBase.h
+1-1clang/include/clang/Sema/Sema.h
+32-366 files

LLVM/project 2ec01e4llvm/lib/Transforms/Vectorize VPlanUtils.cpp VPlan.cpp

[VPlan] Move two VPBlockUtils members (NFC) (#162507)

DeltaFile
+27-0llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+0-26llvm/lib/Transforms/Vectorize/VPlan.cpp
+27-262 files

LLVM/project 98b88dcllvm/lib/Target/X86 X86InstrCompiler.td, llvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Remove extra MOV after widening atomic load

This change adds patterns to optimize out an extra MOV
present after widening the atomic load.
DeltaFile
+28-164llvm/test/CodeGen/X86/atomic-load-store.ll
+16-0llvm/lib/Target/X86/X86InstrCompiler.td
+44-1642 files

LLVM/project b3f7d0bllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Manage atomic load of fp -> int promotion in DAG

When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.
DeltaFile
+117-0llvm/test/CodeGen/X86/atomic-load-store.ll
+4-0llvm/lib/Target/X86/X86ISelLowering.cpp
+121-02 files

LLVM/project db5d7f6llvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/CodeGen AtomicExpandPass.cpp

[AtomicExpand] Add bitcasts when expanding load atomic vector

AtomicExpand fails for aligned `load atomic <n x T>` because it
does not find a compatible library call. This change adds appropriate
bitcasts so that the call can be lowered. It also adds support for
128 bit lowering in tablegen to support SSE/AVX.
DeltaFile
+92-0llvm/test/CodeGen/X86/atomic-load-store.ll
+66-0llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+51-0llvm/test/CodeGen/ARM/atomic-load-store.ll
+12-3llvm/lib/CodeGen/AtomicExpandPass.cpp
+14-0llvm/include/llvm/Target/TargetSelectionDAG.td
+5-0llvm/lib/Target/X86/X86InstrCompiler.td
+240-36 files

LLVM/project e7a4522llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Widen <2 x T> vector types for atomic load

Vector types of 2 elements must be widened. This change does this
for vector types of atomic load in SelectionDAG
so that it can translate aligned vectors of >1 size.
DeltaFile
+286-0llvm/test/CodeGen/X86/atomic-load-store.ll
+74-23llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+361-233 files

LLVM/project bd49d91llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Legalize <1 x T> vector types for atomic load

`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.
DeltaFile
+241-9llvm/test/CodeGen/X86/atomic-load-store.ll
+15-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+257-93 files

LLVM/project 61a2c59llvm/docs LangRef.rst ReleaseNotes.md, llvm/lib/IR Verifier.cpp

IR/Verifier: Allow vector type in atomic load and store

Vector types on atomics are assumed to be invalid by the verifier. However,
this type can be valid if it is lowered by codegen.
DeltaFile
+19-0llvm/test/Assembler/atomic.ll
+9-6llvm/lib/IR/Verifier.cpp
+8-7llvm/test/Verifier/atomics.ll
+6-6llvm/docs/LangRef.rst
+1-0llvm/docs/ReleaseNotes.md
+43-195 files

LLVM/project cce2b9dllvm/lib/Target/X86 X86ISelLowering.cpp X86ISelLowering.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Cast atomic vectors in IR to support floats

This commit casts floats to ints in an atomic load during AtomicExpand to support
floating point types. It also is required to support 128 bit vectors in SSE/AVX.
DeltaFile
+163-18llvm/test/CodeGen/X86/atomic-load-store.ll
+7-0llvm/lib/Target/X86/X86ISelLowering.cpp
+2-0llvm/lib/Target/X86/X86ISelLowering.h
+172-183 files

LLVM/project 1ed917fllvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Add atomic vector tests for unaligned >1 sizes.

Unaligned atomic vectors with size >1 are lowered to calls.
Adding their tests separately here.
DeltaFile
+588-0llvm/test/CodeGen/X86/atomic-load-store.ll
+588-01 files

LLVM/project 9e7209cclang/lib/AST/ByteCode Compiler.cpp

[clang][bytecode][NFC] Clean up variable creation (#164415)

DeltaFile
+50-56clang/lib/AST/ByteCode/Compiler.cpp
+50-561 files

LLVM/project f1dc6ebllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

address comments and rebase

Created using spr 1.3.8-beta.1
DeltaFile
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LLVM/project 3a6e112llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
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LLVM/project 2fc36e3llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

address comments and rebase

Created using spr 1.3.8-beta.1
DeltaFile
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LLVM/project e1fccd7llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
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LLVM/project a065244llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

address comments and rebase

Created using spr 1.3.8-beta.1
DeltaFile
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LLVM/project 990d7c0llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
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LLVM/project cefaf51llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

address comments and rebase

Created using spr 1.3.8-beta.1
DeltaFile
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