[clang][lit] Add option to skip clang-repl checks (#199255)
Whenever lit or llvm-lit is invoked to run clang tests, clang-repl is
run at least once to check for host jit capabilities, and possibly
several more times to probe related capabilities. This adds a noticeable
delay before testing starts, especially for debug builds.
This change adds a lit parameter (clang_skip_clang_repl_checks) and an
environment variable check (CLANG_LIT_SKIP_CLANG_REPL_CHECKS) to allow
the clang-repl probes to be skipped. When this option is used, any tests
that rely on jit execution will be reported as unsupported.
This option is intended only to allow quicker targeted testing during
development. It should not be used for comprehensive verification before
submitting a patch.
On my local test system, executing `ninja check-clang-cir-codegen` with
a previously completed debug build took 18 seconds to run 354 tests with
this option and 53 seconds without it. This is the sort of use case I am
targeting -- lit test runs when the clang-repl overhead will constitute
a significant portion of the total time to execute the tests.
[SandboxVec][SeedCollection] Iterate over all seeds (#195964)
Even though load seeds can already be collected by the seed collector,
the seed collection pass was not iterating over them. This patch fixes
this, we are now iterating over both store and load seeds.
[bzl] Reduce the `deps` size of libc's shared_math_header library. (#200006)
There were ~500 of them, which can cause build analysis/metric issues.
Glob the private headers in use, retaining only the support libraries
that have source code.
Make it a cc_library instead of a libc_header_library. Rename it
"apfloat_shared_math_headers" to clarify its limited use case.
[CIR] Handle the 'before case' block of a switch statement. (#199752)
Before this patch, we would fail any time there was a block with
entry/exit (in this case, one with successors thanks to a label) with a
verification error. This patch adds special handling for that first
block.
This patch DOES choose to not trim them however. Unless there is a label
inside of the block, there isn't any way to get there, and it is dead
code. I've opted to NOT do that optimization, as I suspect that might be
valuable to future passes/something we may wish to warn about in some
sort of CFG analysis.
Additionally, there is some minor changes to FlattenCFG, first to make
sure we skip the switch ONLY if it is truly empty, and second to make
sure we transform any 'break' in the pre-case region.
[AMDGPU] Use shorter form for i16 operands (#198005)
For 16-bit operands an inline constant is zero extended
which in particular allows to use FP constants. These
will have 16 bits of zeroes in the high half and FP16
value in the low 16 bits.
The patch changes semantics of the FP literal argument
used in i16 context in the asm parser to fp16.
Reapply "[clang] Use FileError in FileManager::getFileRef, getDirectoryRef" (#199759)
Most callers are unchanged, since they either ignore the specific error
or have their own formatting of the error that includes both the path
and the errorToErrorCode-unwrapped value. However, for clients that just
forward the error it's helpful to ensure we do not lose track of the
filename that the error is associated with, so use FileError.
To reduce the overhead of using FileError, keep it only in the public
getFileRef and getDirectoryRef themselves, and use ErrorOr in the
implementation. For callers of getOptional* this should avoid
allocations for errors entirely, and for callers of getFileRef and
getDirectoryRef it makes the error allocation inlinable, which may (in
theory, not tested) let us optimize it away if the Error is immediately
unwrapped back to an error code, for example.
Incidentally clean up some callers to use getOptionalFileRef where they
throw away the error immediately.
[Driver][MSVC] Loosen regex for binary name in test (#200015)
`lld-link` will often be installed as `lld-link.exe` on windows. We need
to make sure this test passes either way.
[AMDGPU] Add regression test for wave.reduce constant folding. (#198673)
Ensure wave.reduce.xor, wave.reduce.add, and wave.reduce.sub with
constant operands are not folded to the input value, since their results
depend on the number of active lanes at runtime.
Assisted-by: Cursor (Claude)
[flang][PPC] Improve vector type names in expression diagnostics (NFC) (#199383)
Continuation of #197821
The change only affects vector types; all other types preserve their
existing formatting behavior.
Co-authored-by: virsworld <virpatel at mac.home>
[CIR] Report NYI for STDC FENV_ACCESS under -fclangir
Functions that enable IEEE floating-point intrinsics via `#pragma STDC
FENV_ACCESS ON` or `__attribute__((strict_fp))` set `UsesFPIntrin()` /
`StrictFPAttr` on the `FunctionDecl`. CIR doesn't support the
FP-constrained dialect ops needed to lower such functions correctly, so
`generateCode` now reports `errorNYI` and returns early when either flag
is set, preventing silent miscompilation.
---------
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
[CodeGen] Compare MMO atomic ordering and syncscope. (#199892)
MachineMemOperand::operator== compared the address, flags, AA metadata,
range, alignment, and address space, but not atomic success ordering,
failure ordering, or syncscope. Users such as
MachineInstr::cloneMergedMemRefs could therefore treat atomic and
non-atomic MMOs, or atomics with different syncscopes, as identical.
This bug was found by a large run of Opus 4.7 looking for bugs in LLVM.
[bazel] Add config for hermetic clang toolchain (#192528)
This config uses the https://github.com/hermeticbuild/hermetic-llvm
toolchain to avoid any dependency on the host compiler. This makes it
trivial to test with remote execution and also supports cross
compilation.
[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs
These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.
Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
[AMDGPU] Implement CFI for CSR spills
Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.
Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.
Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[Clang] Default to async unwind tables for amdgcn
To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.
There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.
Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
[AMDGPU] Implement CFI for non-kernel functions
This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.
Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Emit entry function Dwarf CFI
Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.
Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU
While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).
Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
[MIR] Error on signed integer in getUnsigned
Previously we effectively took the absolute value of the APSInt, instead
diagnose the unexpected negative value.
Change-Id: I4efe961e7b29fdf1d5f97df12f8139aac12c9219
[lldb-dap] Use MainLoop instead of a background thread in OutputRedirector. (#199970)
Replace the background thread in OutputRedirector with LLDB's MainLoop
event loop. This reduces the number of threads created and ensures file
descriptors are properly closed when no longer needed.
Since debugger's output is not I/O intensive, there is no risk of
hitting the pipe buffer limit with this approach.
[mlir][SliceAnalysis] Fix visited set to avoid infinite recursion (#200008)
Fixes #139694, which introduced use-def cycle detection during slice
analysis, but some cycles were still not detected, potentially leading
to infinite recursion.
This PR fixes the handling of the visited set, which tracks the current
DFS path during recursion. Previously, the set could fail to detect
double cycles because entries were erased even when no recursive call
was made. The insert/erase operations are now only performed when
recursion actually occurs, ensuring that cycle detection correctly
reflects the active DFS path.
[AArch64][GlobalISel] Add BF16 fabs and fneg (#198655)
These should be very simple as they are just legal or expanded based on
whether fullfp16 is available, as the FP16 FNEG and FABS instructions can
be used equally for BF16.
[flang-rt][cuda] Use a thinner I/O in CUDA build (#199769)
Reduce the footprint of IO in the CUDA build. This helps including IO
when using non relocatable device code mode.
[AtomicExpand] Preserve volatile in widenPartwordAtomicRMW. (#199722)
widenPartwordAtomicRMW widens a sub-word atomicrmw to the target's
minimum cmpxchg size by calling CreateAtomicRMW, which has no
IsVolatile parameter, and didn't copy isVolatile() from the original.
Every other expansion path in this file already does. Affects targets
whose MinCmpXchgSizeInBits exceeds the value width (RISC-V without
Zabha, LoongArch base, SPARC, AMDGPU, etc.).
This bug was found by a large run of Opus 4.7 looking for bugs in LLVM.
