[SPIRV][NewPM] Port SPIRVPostLegalizer
Standard NewPM pass porting. Most of the implementation was already in
static functions so this was pretty simple.
Reviewers: Keenuts, aeubanks, VyacheslavLevytskyy
Pull Request: https://github.com/llvm/llvm-project/pull/219109
[SPIRV][NewPM] Port SPIRVPreLegalizerCombiner
Standard NewPM pass porting. We do need to move the rule config parsing
into being per MF, but this should not be a noticeable regression.
Reviewers: aeubanks, Keenuts, VyacheslavLevytskyy
Pull Request: https://github.com/llvm/llvm-project/pull/219108
[SPIRV][NewPM] Port SPIRVPreLegalizer
Standard NewPM pass porting. The pass does not use any analyses and was
already largely implemented as static functions so this is mostly just
adding the NewPM boilerplate.
Reviewers: aeubanks, Keenuts, VyacheslavLevytskyy
Pull Request: https://github.com/llvm/llvm-project/pull/219104
[PGOProfile] Use .proftext in test to avoid binary blob (#219055)
Use `.proftext` in `thinlto_indirect_call_promotion.ll` to avoid
checking in the binary file `thinlto_indirect_call_promotion.profraw`
(and `update_thinlto_indirect_call_promotion_inputs.sh` that generates
the profile).
I ran `llvm-profdata show --text` to convert the `.profdata` file into a
`.proftext` file that could be inlined into the test. I actually had to
regenerate the `.profraw` file because of a version mismatch. I suspect
that the `REQUIRES: zlib` in the test was actually making this test not
run at all, because it was failing on my machine before this.
Also delete
`llvm/test/tools/llvm-profdata/Inputs/thinlto_indirect_call_promotion.profraw`
which seems to be completely unused.
[InstrProf] Remove pgotestir.profraw test file (#219068)
Remove `pgotestir.profraw` which is actually the same as
`pgotestir.proftext`. Also rename `pgotestclang.profraw` to
`pgotestclang.proftext` since it is actually just a test file, not a
binary blob. Update the test to reflect these changes.
[Reassociate] Improve handling of fadd/fmul pairs (#218675)
Currently fadd/fmul pairs are treated as leaf nodes in order to preserve
pairs of instructions likely to result in FMA generation. However, doing
this unconditionally can prevent reassociation of deeper expression
trees. This commit fixes that by preserving an fadd/fmul pair as a leaf
only when the other operand of the fadd is not itself a reassociable
fadd expression.
[GlobalISel] Drop nuw/nsw/disjoint when widening a result with G_ANYEXT (#218558)
nuw/nsw/disjoint flags are only true at the original width. G_ANYEXT
leaves the new high bits unconstrained, so they must be dropped.
[SLSR] Skip candidate-basis differences when `SCEVUnknown`s differ (NFC) (#217451)
After SLSR finds a non-constant delta for a candidate, it will continue
searching for a constant delta. However, when the set of `SCEVUnknown`s
differs between a candidate and a basis, the offset cannot be constant.
Thus, prune that candidate and avoid an expensive, fruitless call to
`getSCEVMinus()`.
[AMDGPU][GlobalISel] Fix i64-to-i16 clamp combine on inverted bounds (#216306)
`abs(Cmp2 - Cmp1)` check couldn't tell inverted bounds `(Lo > Hi)` from
valid ones, letting the combine build a med3 that clamped to the wrong
range instead of the constant smin/smax result
[CIR] Implement missing __sync_* atomic builtins (#214606)
Add CIR codegen support for five legacy __sync_* builtins that
previously emitted "Not Yet Implemented" errors:
__sync_val_compare_and_swap -> cir.atomic.cmpxchg (seq_cst)
__sync_bool_compare_and_swap -> cir.atomic.cmpxchg + cmp (seq_cst)
__sync_swap -> cir.atomic.xchg (seq_cst)
__sync_lock_test_and_set -> cir.atomic.xchg (seq_cst)
__sync_lock_release -> cir.store 0 (release)
Size-suffixed forms (_1, _2, _4, _8) are handled, covering 20 builtin
variants in total; the unsuffixed forms are rewritten by Sema and the
_16 variants fall back to errorBuiltinNYI.
The existing emitBinaryAtomic / emitBinaryAtomicPost infrastructure
already handled the arithmetic __sync_* family (fetch_and_add, etc.).
This patch adds the remaining compare-and-swap, exchange, and
lock-release helpers: emitAtomicCmpXchgValue, emitAtomicCmpXchgBool,
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Restrict intrinsic to fixed->scalable with same min EC
This simplifies a lot of the legalisation code. The codegen regressions
for 64b -> scalable 128b can be addressed with a DAG combiner in a
follow-up.
[analyzer] Move the lifetime checkers from alpha.cplusplus to alpha.core (#216739)
This PR moves the lifetime checkers from `alpha.cplusplus` to
`alpha.core`. This PR is the beginning of future PRs that will bring the
lifetime checkers from `alpha` to `core`. To meet the requirements of a
`core` checker there are still missing works for these checkers that is
the reason this PR only moves them from `alpha.cplusplus` to
`alpha.core`.
[mlir][LLVM] Use a disjoint scope domain when inlining noalias
This matches recent changes to the LLVM inliner.
AI disclosure: Claude wrote the code, I wrote the commit message and
have done initial review.
