LLVM/project 5c72b10mlir/lib/Dialect/AMDGPU/Transforms VectorReductionToDot.cpp, mlir/test/Dialect/AMDGPU vector-reduction-to-dot.mlir

test

Signed-off-by: Eric Feng <Eric.Feng at amd.com>
DeltaFile
+7-66mlir/test/Dialect/AMDGPU/vector-reduction-to-dot.mlir
+0-16mlir/lib/Dialect/AMDGPU/Transforms/VectorReductionToDot.cpp
+7-822 files

LLVM/project c507e20llvm/include/llvm/Transforms/IPO InstrumentorStubPrinter.h Instrumentor.h, llvm/lib/Transforms/IPO InstrumentorStubPrinter.cpp

[Instrumentor] Allow printing a runtime stub (#138978)

This commit extends the Instrumentor with the option
`configuration.runtime_stubs_file` to generate a runtime stub file with
the configured instrumentation. The stub prints all parameters passed to
each enabled instrumentation function.
DeltaFile
+212-0llvm/lib/Transforms/IPO/InstrumentorStubPrinter.cpp
+105-0llvm/test/Instrumentation/Instrumentor/rt_config.json
+105-0llvm/test/Instrumentation/Instrumentor/bad_rt_config.json
+37-0llvm/test/Instrumentation/Instrumentor/default_rt
+32-0llvm/include/llvm/Transforms/IPO/InstrumentorStubPrinter.h
+16-0llvm/include/llvm/Transforms/IPO/Instrumentor.h
+507-07 files not shown
+520-213 files

LLVM/project 54e1afcllvm/lib/Target/AArch64 AArch64SLSHardening.cpp AArch64.h

[NewPM] Port for AArch64SLSHardening (#196378)

AArch64.h: Declared the AArch64SLSHardeningPass class.
AArch64PassRegistry.def: Registered the pass under the name
aarch64-sls-hardening.
AArch64SLSHardening.cpp: Implemented the run method to bridge the NewPM
with the existing pass logic, ensuring MachineModuleAnalysis is
correctly retrieved.
DeltaFile
+28-6llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+8-2llvm/lib/Target/AArch64/AArch64.h
+2-2llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+1-0llvm/lib/Target/AArch64/AArch64PassRegistry.def
+39-104 files

LLVM/project 119f338clang/lib/Basic Targets.cpp, clang/lib/Basic/Targets OSTargets.h

[clang][RISCV] Remove some of the bits added with RISC-V big endian support (#192903)

- FreeBSD will not have any new 32-bit archs
- *BSD's are unlikely to touch BE RISC-V
- Keep the BE and LE targets separate
DeltaFile
+16-2clang/lib/Basic/Targets.cpp
+0-8clang/lib/Driver/ToolChains/FreeBSD.cpp
+3-0clang/test/Driver/freebsd.c
+0-2clang/lib/Basic/Targets/OSTargets.h
+19-124 files

LLVM/project a2e0ee2bolt/docs BinaryAnalysis.md, llvm/docs/AMDGPU AMDGPUAsmGFX950.rst

Merge branch 'main' into users/s-perron/constantbuffer-type-trait
DeltaFile
+5,910-880llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+3,306-504llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
+581-920llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
+1,287-0llvm/test/tools/dsymutil/AArch64/typedef-different-types.test
+0-775llvm/utils/Reviewing/find_interesting_reviews.py
+672-100bolt/docs/BinaryAnalysis.md
+11,756-3,1791,890 files not shown
+42,586-17,1011,896 files

LLVM/project d279247llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/test/MC/AMDGPU gfx1250_asm_vop3_err.s

[AMDGPU] Also disable lit64() from VOP3 and inline constant
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+5-0llvm/test/MC/AMDGPU/gfx1250_asm_vop3_err.s
+10-32 files

LLVM/project cc79831clang/include/clang/CIR/Interfaces CIROpInterfaces.td, clang/lib/CIR/CodeGen CIRGenModule.cpp

[CIR] Implement weak ref and alias attribute handling (#195972)

This adds handling for globals with the WeakRefAttr (not emitted) or
AliasAttr attributes set. CIR already had support for function aliases,
but we weren't handling the explicit alias attribute, and we didn't have
any support for global variable aliases. This change adds the global
variable alias support and adds the code to handle the explicit
attribute for variables and functions.

Assisted-by: Cursor / claude-opus-4.7-thinking-xhigh
DeltaFile
+91-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+79-0clang/test/CIR/CodeGen/attr-alias.c
+32-22clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+42-0clang/test/CIR/IR/invalid-global.cir
+26-0clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
+26-0clang/test/CIR/CodeGen/attr-weakref.c
+296-254 files not shown
+324-2610 files

LLVM/project 93c6562clang/lib/Sema SemaHLSL.cpp HLSLBuiltinTypeDeclBuilder.cpp, clang/test/AST/HLSL ConstantBuffers-AST.hlsl

[HLSL] Add ConstantBuffer<T> (#195153)

The ConstantBuffer<T> is a standard resource type in HLSL. This commit
is following the design in wg-hlsl proposal
[0046](https://github.com/llvm/wg-hlsl/blob/main/proposals/0046-constantbuffer-t.md).

The type constraints will be left to a follow up pr.

Assisted-by: Gemini

<!-- branch-stack-start -->

-------------------------
- main
  - https://github.com/llvm/llvm-project/pull/195151
    - https://github.com/llvm/llvm-project/pull/195152
      - users/s-perron/constantbuffer-constantbuffer-t :point_left:
        - https://github.com/llvm/llvm-project/pull/195154


    [3 lines not shown]
DeltaFile
+120-0clang/test/AST/HLSL/ConstantBuffers-AST.hlsl
+68-0clang/test/CodeGenHLSL/builtins/ConstantBuffer-layout.hlsl
+65-0clang/test/CodeGenHLSL/builtins/ConstantBuffer.hlsl
+47-0clang/lib/Sema/SemaHLSL.cpp
+35-0clang/test/SemaHLSL/BuiltIns/ConstantBuffers.hlsl
+29-2clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+364-27 files not shown
+478-313 files

LLVM/project 0387b87clang/test/C/C2y n3364.c

Fix PowerPC test failure from [AsmWriter] Change the output syntax of floating-point literals. (#196407)

The root cause of the failure is that the output syntax only outputs the
+/-snan syntax for ppc_fp128 if the trailing double is 0. The clang test
here is triggering -LDBL_SNAN, which is actually an fneg(snan constant),
and the fneg causes the signs of both doubles in the ppc_fp128 to flip.
As a result, only the ppc_fp128 form is output in the hexadecimal format
rather than the -snan format, necessitating a change to the test output.
DeltaFile
+1-1clang/test/C/C2y/n3364.c
+1-11 files

LLVM/project 3c9f41futils/bazel/llvm-project-overlay/llvm BUILD.bazel driver.bzl

[Bazel] Fixes dbf927a (#196414)

This fixes dbf927a6e3ff4b076b3ead608c57e16ebee9ed66.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+17-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+1-1utils/bazel/llvm-project-overlay/llvm/driver.bzl
+18-12 files

LLVM/project f486c65llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanTransforms.h, llvm/test/Transforms/LoopVectorize load-of-struct-deref-pred.ll dereferenceable-info-from-assumption-variable-size.ll

[VPlan] Directly use masks on recipes in dropPoisonGen (#193978)

dropPoisonGeneratingRecipes currently uses a convoluted and incorrect
logic to determine whether a recipe is masked. Use the masks that are
set on the recipes directly instead.
DeltaFile
+16-16llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
+11-16llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-9llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+4-4llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll
+3-3llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-variable-size.ll
+1-5llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+37-539 files not shown
+52-6715 files

LLVM/project e0039cbclang/test/SemaHLSL/BuiltIns ConstantBuffers.hlsl, clang/test/SemaHLSL/Resources ConstantBuffers.hlsl

Move test file, and add new test.
DeltaFile
+74-0clang/test/SemaHLSL/Resources/ConstantBuffers.hlsl
+0-68clang/test/SemaHLSL/BuiltIns/ConstantBuffers.hlsl
+74-682 files

LLVM/project 3c2569bllvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU udivrem24.ll udiv.ll

[AMDGPU] Fix LowerDIVREM24 lowering for the unsigned case

The code was not properly checking that the operands were
24-bit integers for the unsigned case.
DeltaFile
+70-78llvm/test/CodeGen/AMDGPU/udivrem24.ll
+19-22llvm/test/CodeGen/AMDGPU/udiv.ll
+34-0llvm/test/CodeGen/AMDGPU/udiv-miscompilation.ll
+14-6llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+137-1064 files

LLVM/project 9f47d4cllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize first-order-recurrence-tail-folding.ll

[VPlan] Fold removeRedundantCanonicalIVs into replaceWideCanIVs. (#195545)

Unify logic to replace VPWidenCanonicalIVRecipes with scalar-steps or
VPWidenIntOrFpInductionRecipe in replaceWideCanonicalIVWithWideIV. This
reduces the code a bit and running later has the benefit that we do the
replacement after the wide mask compare has been replaced by
active-lane-mask/EVL. This means we do not need to drop wrap flags in
some cases, as the wide IV is not used for the mask.

PR: https://github.com/llvm/llvm-project/pull/195545
DeltaFile
+77-70llvm/test/Transforms/LoopVectorize/VPlan/vplan-sink-scalars-and-merge.ll
+36-61llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+38-37llvm/test/Transforms/LoopVectorize/VPlan/first-order-recurrence-sink-replicate-region.ll
+10-10llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
+9-9llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
+6-6llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
+176-19312 files not shown
+201-21818 files

LLVM/project dbf927allvm/docs/CommandGuide llvm-extract-bundle-entry.rst, llvm/lib/Object OffloadBundle.cpp

Add llvm-extract-bundle-entry to extend llvm-objcopy (#169386)

This commit creates llvm-extract-bundle-entry as a wrapper to
llvm-objcopy,
  to allow extracting HIP offload fatbin bundles given a URI argument.

---------

Co-authored-by: dsalinas_amdeng <david.salinas at amd.com>
DeltaFile
+92-1llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
+78-0llvm/test/tools/llvm-objcopy/extract-bundle-entry.test
+59-0llvm/docs/CommandGuide/llvm-extract-bundle-entry.rst
+36-0llvm/tools/llvm-objcopy/ExtractBundleEntryOpts.td
+20-5llvm/lib/Object/OffloadBundle.cpp
+12-0llvm/tools/llvm-objcopy/llvm-objcopy.cpp
+297-68 files not shown
+329-814 files

LLVM/project ad5664bclang/include/clang/Basic TokenKinds.def, clang/include/clang/Sema SemaHLSL.h

[HLSL] Add type traits for ConstantBuffers templates

This commit adds the type traits to restrict the template type in a
ConstantBuffer to structs or classes that do not contain a resource
type.

Assisted-by: Gemini
DeltaFile
+44-6clang/lib/Sema/HLSLExternalSemaSource.cpp
+33-0clang/test/SemaHLSL/BuiltIns/ConstantBuffers.hlsl
+13-0clang/lib/Sema/SemaHLSL.cpp
+9-0clang/lib/Sema/SemaTypeTraits.cpp
+1-0clang/include/clang/Sema/SemaHLSL.h
+1-0clang/include/clang/Basic/TokenKinds.def
+101-66 files

LLVM/project c0262e7llvm/lib/Target/SystemZ SystemZISelLowering.cpp, llvm/test/CodeGen/SystemZ args-23.ll

[SystemZ] Fix internal error with single-element vector types (#196127)

The special treatment of single-element 128-bit vector types in
SystemZTargetLowering::getRegisterTypeForCallingConv is not appropriate
if vector types are not supported, and can lead to internal compiler
errors.

Fixes: https://github.com/llvm/llvm-project/issues/194256
(cherry picked from commit 48346f2352eaf25373e1a6204c0c7f9fdce92a85)
DeltaFile
+464-0llvm/test/CodeGen/SystemZ/args-23.ll
+1-1llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+465-12 files

LLVM/project cbb1eb5lldb/test/API/tools/lldb-dap/source TestDAP_source.py, lldb/tools/lldb-dap/Handler SourceRequestHandler.cpp

[lldb-dap] Fix crash in source request handler (#195847)

Check optional argument source has a value before getting the source
reference.

(cherry picked from commit fa8724beccad53be2d39d065be5db11917f94bac)
DeltaFile
+6-0lldb/test/API/tools/lldb-dap/source/TestDAP_source.py
+3-2lldb/tools/lldb-dap/Handler/SourceRequestHandler.cpp
+9-22 files

LLVM/project b3793a0bolt/include/bolt/Profile DataReader.h, bolt/lib/Profile DataReader.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.4
DeltaFile
+23-18bolt/lib/Profile/DataReader.cpp
+3-6bolt/include/bolt/Profile/DataReader.h
+26-242 files

LLVM/project 62a94f0llvm/lib/Transforms/IPO InstrumentorStubPrinter.cpp

Fix comment
DeltaFile
+2-0llvm/lib/Transforms/IPO/InstrumentorStubPrinter.cpp
+2-01 files

LLVM/project 36cfc59clang/lib/CIR/Dialect/Transforms EHABILowering.cpp CIRTransformUtils.cpp, clang/test/CIR/IR invalid-construct-catch-param.cir

[CIR] Lower cir.construct_catch_param on Itanium (#195904)

Implement Itanium-ABI lowering of the `cir.construct_catch_param`
operation. This operation encapsulates the target-specific work that
must happen before `__cxa_begin_catch` to bind an in-flight exception
object to a non-trivially-copyable catch parameter

In order to allow the full copy-constructor call generation handling,
including call site attribute generation, to be reused during codegen,
we will be generating a thunk function to perform the copy construction
when it is needed. This function gets inlined during EHABI lowering.
This allows us to generate a target-independent representation during
the initial CIR code generation without having to duplicate the copy
construction logic in the EHABI lowering pass.

The actual generation of the thunk function and the
construct_catch_param operation will be added in a follow-up change.

Assisted-by: Cursor / claude-opus-4.7-thinking-xhigh
DeltaFile
+218-0clang/test/CIR/Transforms/eh-abi-lowering-construct-catch.cir
+185-18clang/lib/CIR/Dialect/Transforms/EHABILowering.cpp
+175-0clang/test/CIR/Transforms/eh-abi-lowering-construct-catch-invalid.cir
+72-0clang/lib/CIR/Dialect/Transforms/CIRTransformUtils.cpp
+1-64clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
+40-1clang/test/CIR/IR/invalid-construct-catch-param.cir
+691-835 files not shown
+735-8411 files

LLVM/project 143aa41llvm/docs SecurityTransparencyReports.rst

2025 Security Response Group Transparency Report (#194066)

Add the Security Response Group's Transparency Report for 2025.
DeltaFile
+129-0llvm/docs/SecurityTransparencyReports.rst
+129-01 files

LLVM/project 3983572llvm/include/llvm/CodeGen SelectionDAG.h TargetLowering.h, llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp TargetLowering.cpp

[DAG] Use UndefPoisonKind enum in isGuaranteedNotToBeUndefOrPoison/canCreateUndefOrPoison/getFreeze (#196145)

Replace the PoisonOnly flag and allow discrimination between
undef/poison values - to more closely match ValueTracking / GISel
implementations.

This patch is mainly a drop in replacement for the PoisonOnly logic, and
hasn't added anything to match UndefOnly logic (e.g. for SelfMultiply
patterns) - we can improve upon this later on with proper test coverage.

Fixes #194818
DeltaFile
+43-43llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+26-22llvm/include/llvm/CodeGen/SelectionDAG.h
+9-9llvm/lib/Target/X86/X86ISelLowering.cpp
+6-8llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+6-7llvm/include/llvm/CodeGen/TargetLowering.h
+7-4llvm/lib/Target/X86/X86ISelLowering.h
+97-9311 files not shown
+132-13017 files

LLVM/project e297b9bllvm/test/Instrumentation/Instrumentor generate_rt.ll

[Instrumentor] Fix test for Windows
DeltaFile
+1-1llvm/test/Instrumentation/Instrumentor/generate_rt.ll
+1-11 files

LLVM/project 8c2ac3dllvm/test/Instrumentation/Instrumentor generate_bad_rt.ll

Fix test for windows
DeltaFile
+1-1llvm/test/Instrumentation/Instrumentor/generate_bad_rt.ll
+1-11 files

LLVM/project c527010llvm/include/llvm/Transforms/IPO InstrumentorStubPrinter.h Instrumentor.h, llvm/lib/Transforms/IPO InstrumentorStubPrinter.cpp

[Instrumentor] Allow printing a runtime stub
DeltaFile
+210-0llvm/lib/Transforms/IPO/InstrumentorStubPrinter.cpp
+105-0llvm/test/Instrumentation/Instrumentor/rt_config.json
+105-0llvm/test/Instrumentation/Instrumentor/bad_rt_config.json
+37-0llvm/test/Instrumentation/Instrumentor/default_rt
+32-0llvm/include/llvm/Transforms/IPO/InstrumentorStubPrinter.h
+16-0llvm/include/llvm/Transforms/IPO/Instrumentor.h
+505-07 files not shown
+518-213 files

LLVM/project d41ee9allvm/test/Instrumentation/Instrumentor generate_rt.ll

[Instrumentor] Fix test for Windows
DeltaFile
+1-1llvm/test/Instrumentation/Instrumentor/generate_rt.ll
+1-11 files

LLVM/project 9d2b478clang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp, clang/test/CIR/CodeGen static-local-arm-guard.cpp

[CIR] Implement ARM-style static guard lowering (#196394)

This adds the ARM-specific handling in LoweringPrepare to emit guard
variables for static local initialization.
DeltaFile
+100-0clang/test/CIR/CodeGen/static-local-arm-guard.cpp
+11-6clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+111-62 files

LLVM/project 122f6f0flang/include/flang/Optimizer/Analysis AliasAnalysis.h, flang/lib/Optimizer/Analysis AliasAnalysis.cpp

[flang] Add initial support for RegionBranchOpInterface to AA (#196132)

This PR introduces initial support for being able to disambiguate values
through operations that implement RegionBranchOpInterface (eg fir.if).
The initial approach implements a localized approach which instead of an
invasive update to the current algorithm so that a single underlying
origin to be replaced with multiple, it still leaves the single origin
concept. It does so through a conservative merge of all input sources.

The main initial goal is to allow disambiguating OPTIONAL pattern where
we have an allocate on one branch and an absent on the other.
Additionally, it is able to properly merge sources if the sources have
same properties.
DeltaFile
+286-0flang/test/Analysis/AliasAnalysis/alias-analysis-regionbranch.mlir
+181-0flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
+5-0flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
+472-03 files

LLVM/project 2f9efaemlir/include/mlir/Dialect/SPIRV/IR SPIRVControlFlowOps.td SPIRVGraphOps.td, mlir/test/Dialect/SPIRV/IR tosa-ops-verification.mlir control-flow-ops.mlir

[MLIR][SPIRV] Enable strict property assembly format

Enable strict property assembly format mode for the SPIR-V dialect. Bind
FunctionCall arg/result attributes and GraphConstant IDs directly in
declarative assembly formats so strict parsing does not rely on fallback
handling.

Update SPIR-V dialect and target tests to use the direct property spelling.

Assisted-by: Codex
DeltaFile
+6-6mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
+6-1mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir
+3-3mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
+4-1mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
+2-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
+2-2mlir/test/Target/SPIRV/graph-ops.mlir
+23-152 files not shown
+25-178 files