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[LV] Use VPReductionRecipe for partial reductions (#147513)

Partial reductions can easily be represented by the VPReductionRecipe
class by setting their scale factor to something greater than 1. This PR
merges the two together and gives VPReductionRecipe a VFScaleFactor so
that it can choose to generate the partial reduction intrinsic at
execute time.

Stacked PRs:
1. https://github.com/llvm/llvm-project/pull/147026
2. https://github.com/llvm/llvm-project/pull/147255
3. https://github.com/llvm/llvm-project/pull/156976
4. https://github.com/llvm/llvm-project/pull/160154
5. https://github.com/llvm/llvm-project/pull/147302
6. https://github.com/llvm/llvm-project/pull/162503
7. -> https://github.com/llvm/llvm-project/pull/147513

Replaces https://github.com/llvm/llvm-project/pull/146073 .

[MC][RISCV] Add missing Predicates for NDS_FMV_BF16_X (#169662)

run 
```shell
build/bin/llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-index=-1
```

error:
```
---
mode:            latency
key:
  instructions:
    - 'NDS_FMV_BF16_X F2_H X11'
    - 'NDS_FMV_X_BF16 X26 F2_H'
  config:          ''
  register_initial_values:
    - 'X11=0x0'
cpu_name:        generic

    [8 lines not shown]

[mlir][xegpu] Add layout based SIMT distribution support for `vector.extract/insert_strided_slice` (#168626)

This PR adds general SIMT distribution support for
`vector.extract/insert_strided_slice`. Currently vector distribution
already have support for these operations but have restrictions to avoid
requiring layouts during distribution logic. For example,
`extract_stride_slice` require that distributed dimension is fully
extracted. However, more complex cases may require extracting partially
from distributed dimension (eg. 8x16xf16 extraction from 8x32xf16).
These types of cases need the layouts to reason about how the data is
spread across SIMT lanes.

Currently, we don't have layout access in vector distribution so these
new patterns are place in XeGPU side. They have higher pattern benefit
so that they will be tried first before trying regular vector
distribution based patterns.

rework

Created using spr 1.3.8-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]

rework

Created using spr 1.3.8-beta.1

fix dominance issue and comment

[ReplaceConstant] Don't create instructions for the same constant multiple times in the same basic block

Fixes #167500.

[scudo] Add scudo_standalone support for SystemZ (#166187)

Add Support for scudo_standalone for SystemZ without enabling gwp_asan.

Co-authored-by: anoopkg6 <anoopkg6 at github.com>

[tysan] Type Sanitizer support for SystemZ (#162396)

Type Sanitizer support for SystemZ.

Co-authored-by: anoopkg6 <anoopkg6 at github.com>

PowerPC: Add vec_malloc functions to AIX in RuntimeLibcalls

XCore: Add iprintf to RuntimeLibcalls system library

RuntimeLibcalls: Add macos unlocked IO functions to systems

This is another of the easier to understand conditions from
TargetLibraryInfo

RuntimeLibcalls: Add small_printf functions to emscripten

RuntimeLibcalls: Add memset_pattern* calls to darwin systems (#167083)

This is one of the easier cases to comprehend in TargetLibraryInfo's
setup.

Multi-origin changes

RuntimeLibcalls: Add more function entries from TargetLibraryInfo (#167082)

Script scraped dump of most functions in TargetLibraryInfo.def,
with existing entries and a few special cases removed. This only
adds the definitions, and doesn't add them to any system yet.

Adding them in the correct places is the hard part, since it's
all written as opt-out with manually written exemptions in
TargetLibraryInfo.

RuntimeLibcalls: Add malloc and free entries (#167081)

Calloc was already here, but not the others. Also add
manual type information.

[BOLT][BTI] Disassemble PLT entries when processing BTI binaries

PLT entries are PseudoFunctions, and are not disassembled or emitted.
For BTI, we need to check the first MCInst of PLT entries, to see
if indirectly calling them is safe or not.

This patch disassembles PLTs for binaries using BTI, while not changing
the behaviour for binaries without BTI.

The PLTs are only disassembled, not emitted.

CodeGen: Remove PointerLikeRegClass handling from codegen (#159883)

All uses have been migrated to RegClassByHwMode. This is now
an implementation detail of InstrInfoEmitter for pseudoinstructions.

CodeGen: Make target overrides of PointerLikeRegClass mandatory (#159882)

Most targets should now use the convenience multiclass to fixup
the operand definitions of pointer-using pseudoinstructions:

defm : RemapAllTargetPseudoPointerOperands<target_ptr_regclass>;

[SPIRV] Use OpCopyMemory for logical SPIRV memcpy (#169348)

This commit modifies the SPIRV instruction selector to emit
`OpCopyMemory`
instead of `OpCopyMemorySized` when generating SPIRV for logical
addressing.

Previously, `G_MEMCPY` was translated to `OpCopyMemorySized`, which
requires an
explicit size operand. However, for logical SPIRV, the size of the
pointee type
is implicitly known. This change ensures that `OpCopyMemory` is used,
which is
more appropriate for logical SPIRV and aligns with the SPIR-V
specification for
logical addressing.

[BOLT][BTI] Disassemble PLT entries when processing BTI binaries

PLT entries are PseudoFunctions, and are not disassembled or emitted.
For BTI, we need to check the first MCInst of PLT entries, to see
if indirectly calling them is safe or not.

This patch disassembles PLTs for binaries using BTI, while not changing
the behaviour for binaries without BTI.

The PLTs are only disassembled, not emitted.

[SPIRV] Support Peeled Array Layouts for HLSL CBuffers (#169078)

This commit adds support for 'peeled arrays' in HLSL constant buffers.
HLSL CBuffers may have padding between array elements but not after the
last element. This is represented in LLVM IR as {[N-1 x {T, pad}], T}.

Changes include:
- Recognition of the peeled array pattern.
- Logic to reconstitute these into SPIR-V compatible arrays.
- Support for spirv.Padding type in GlobalRegistry and Builtins.
- Updates to SPIRVCBufferAccess to correctly calculate member offsets
  in these padded structures.

Depends on https://github.com/llvm/llvm-project/pull/169076

CodeGen: Make all targets override pseudos with pointers (#159881)

This eliminates the need to have PointerLikeRegClass handling in
codegen.

fix test

address review

[SPIRV] Enable DCE in instruction selection and update tests (#168428)

The instruction selection pass for SPIR-V now performs dead code
elimination (DCE).
This change removes unused instructions, leading to more optimized
SPIR-V output.

As a consequence of this, several tests were updated to ensure their
continued
correctness and to prevent previously tested code from being optimized
away.
Specifically:
- Many tests now store computed values into global variables to ensure
they are
  not eliminated by DCE, allowing their code generation to be verified.
- The test `keep-tracked-const.ll` was removed because it no longer
tested
its original intent. The check statements in this test were for
constants

    [12 lines not shown]

opt: Try to respect target-abi command line option (#169604)

Mips seems kind of broken with these options. n32 seems to
override the 64-bit arch with 32-bit pointers, and trying
to use any 32-bit mips triple also just errors with any
options.

address review