[KnownFPClass][NFC] Remove isKnownNeverZero helper to encourage proper denormal handling (#236625)
Removes `isKnownNeverZero()`, `isKnownNeverPosZero()`, and
`isKnownNeverNegZero()` which only compare against the literal `+-0.0`,
`+0.0`, and `-0.0` respectively. This encourages the use of
`isKnownNeverLogicalZero(Mode)` and friends which properly account for
the input denormal mode.
If input denormals are properly handled, you can still compare against
`+-0.0` literals via the generic `isKnownNever(fcZero)`.
AMDGPU: Fold global address into subregister use with lo/hi relocation
Split 64-bit relocations into the 32-bit halves when applying a
subregister extract, similar to how immediates are modified when
folding. The same split is applied when 64-bit mov pseudos are
expanded.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[lldb] Copy valid breakpoint overrides from the dummy target (#235834)
`Target::PrimeFromDummyTarget` copied a breakpoint override into a new target only when `Validate` failed, because an `llvm::Error` converts to true on failure. Overrides registered on the dummy target therefore never reached later targets. Copy the overrides that validate, and log the error of those that don't.
Rename `Validate` to `HasErrors`, still returning an `llvm::Error`, so call sites read the right way round. It now also checks that the override's class exists, so adding an override with a missing class fails with a useful error instead of failing on every matching breakpoint.
Test both: an override on the dummy target applies to targets created later, and `test_bad_values` now covers a missing class.
AMDGPU: Fix folding 64-bit move imm into subreg use in SIShrinkInstructions
foldImmediates folded the full 64-bit immediate of a move into a
subregister use, rather than the value of the used half. Extract the
immediate value of the used subregister. Global addresses were similarly
broken.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[libc++] Produce LNT v5 reports from the A/B benchmark job (#237001)
This patch lifts the LNT v5 report creation into a command-line tool so
that we can call it from the A/B benchmarking job, and upload it as an
artifact. In future PRs we can actually submit those results to LNT.
Assisted by Claude
[SandboxVec][LoadStoreVec] Update test checks and rename tests (NFC) (#236947)
load_store_vec_load_seeds.ll primarily checks tge LSV starting from
loads, but we are currently using both loads and stores as seeds in the
RUN line. This patch replaces the single RUN line with two RUN lines,
one for loads and one for stores. Also rename it to load_seeds.ll since
load_store_vec is implied by the parent directory.
Also specify the default store seed in load_store_vec.ll RUN line and
rename it to store_seeds.ll.
IR: Introduce "debugger-tuning" module flag (#235049)
Prepare to replace TargetOptions::DebuggerTuning with a module flag. Unlike
other TargetOptions recently moved to module flags, debugger tuning is not a
firm ABI property. Mismatches and unrecognized names are tolerated.
Co-authored-by: Claude Sonnet 5 <noreply at anthropic.com>
[CodeGen] Ignore debug instructions in ImplicitNullChecks scan (#232158)
A debug record at the start of the non-null block can consume the
ImplicitNullChecks scan budget and leave an explicit test and branch.
Iterate over top-level non-debug instructions while keeping pseudo
probes in the scan. The regression test uses a scan limit of one to
exercise the boundary with a single `#dbg_value`.
[lldb] Keep provider frames out of the base unwinder frame list (#235909)
When a scripted frame provider is loaded, Thread::ClearStackFrames saves
the provider-augmented frame list in m_prev_frames_sp, and the next base
unwinder frame list (ID 0) is created with it as its previous frames.
Once the unwinder list has fetched all its frames, it merges with the
previous list and adopts every previous frame whose StackID matches.
Scripted frames that mirror the CFA and PC of the frames they wrap have
matching StackIDs, so they replace the unwound frames in the unwinder
list. That means the unwinder backtrace shows the scripted frames
instead of the newly unwound ones:
```
(lldb) bt --provider 0
=== Provider 0: Base Unwinder ===
frame #0: a.out`main at main.c:23:3 [synthetic]
frame #1: dyld`start + 6652 [synthetic]
```
[23 lines not shown]
[InstCombine] Fix demanded classes for sqrt (#231316)
Fixes https://github.com/llvm/llvm-project/issues/229988
Correctly sets `DemandedSrcMask` for `sqrt` in
`SimplifyDemandedUseFPClass` while taking the denormal mode into
account. Previously a subnormal source that flushes to a demanded zero
result was not demanded, so the source could be dropped.
Also stops inferring that the source cannot be negative for classes that
were demanded. This is a separate pre-existing bug that returned
`poison` where a `-0.0` or `+0.0` result was demanded.
I also made sure `computeKnownFPClass(fcZero)` would add `fcSubnormal`
to `InterestedSrcs` for `sqrt` in `ValueTracking.cpp` and
`GISelValueTracking.cpp`.
AI Disclosure:
I used Claude Opus 5 to help implement the changes and write the tests.
[GlobalISel] Auto-commute combine patterns
Emit both operand orders for constrained commutative generic match
patterns, including each use of a PatFrag. Skip redundant permutations
and enforce MaxPermutations before allocating expanded alternatives.
Give each permutation its own operand expansions so operand indices
cannot leak between alternatives.
Keep commuted immediate patterns available with constant-to-RHS
canonicalization, and consolidate AMDGPU carry rules while preserving
zero-addend and RHS-first matching.
Make the integer and AMDGPU multiply/select helpers accept either operand
order.
Add emitter documentation and TableGen, MIR, and codegen regressions.
[KnownFPClass] Add getEmpty() and use KnownFPClass(APFloat) for FP constants (#236622)
Replaces `Known.setKnownFPClasses(fcNone)` with `Known =
KnownFPClass::getEmpty()`.
Also replaces some uses of `Known |= APFloat.classify()` with `Known |=
KnownFPClass(APFloat)`. This preserves information that is lost in the
conversion to `FPClassTest` (Such as the sign bit).
I plan on removing `void KnownFPClass::setSignBit(std::optional<bool>
SignBit)` since it has poorly defined semantics, and should be replaced
by `signBitMustBeOne`/`signBitMustBeZero` or `copysign` instead.
Follow-up to https://github.com/llvm/llvm-project/pull/236319
AI Disclosure:
I used Claude Opus 5 to help write the changes.
[asan][test] Guard throw_call_test.cpp on shared_cxxabi, Solaris, and NetBSD (#237024)
After #236664 added explicit `-fsanitize-address-use-after-return=never`
and `-fno-sanitize-address-use-after-scope` runs, `throw_call_test.cpp`
started failing on:
* Toolchains built with static `libc++abi.a` (`!shared_cxxabi`, e.g.
`Fuchsia-stage2.cmake`), where strong `__cxa_throw` and
`_Unwind_RaiseException` override ASan's weak interceptors.
* Solaris (#42048) and NetBSD, where `asan_interceptors.h` disables
`__cxa_throw` interception.
Add `REQUIRES: shared_cxxabi` and `XFAIL` Solaris and NetBSD, matching
`TestCases/intercept-rethrow-exception.cpp`, and update the Solaris
`FIXME` comment in both tests to link #42048.
Assisted-by: Gemini
[SandboxVec][LoadStoreVec] Support mixed-type store vectorization of arbitrary values
vectorizeStores() only handled chains whose stored values were all
consecutive loads or all constants. Any other chain, e.g., storing
function arguments or computed values, was left alone.
Pack such values into a vector with createPack(). For a chain of mixed
types the vector has integer lanes, so each value is first
reinterpreted (bitcast / ptrtoint) as the lanes it occupies with
Reinterpret::reinterpretValue(), and a value spanning several lanes is
inserted lane by lane. The pack is placed right before the vector
store, where every stored value is available. Whether this pays off is
left to the existing cost check in acceptOrRevert().
Chains storing a non-integral pointer are left alone.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Support mixed-type load vectorization
Remove the restriction that every load in a top-level load chain must
have the vector's element type. A chain of mixed types such as
{i32, float} or {double, i32, i32} is loaded as a vector of integers
(as chosen by VecUtils::getCombinedVectorTypeFor()), each original load
is unpacked from the lanes it occupies, and then reinterpreted back to
its own type with Reinterpret::reinterpretValue().
Chains involving a non-integral pointer are left alone, since such a
pointer cannot be recovered from an integer lane.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec][LoadStoreVec] Vectorize store chains whose loads have external uses
vectorizeStores() used to give up on a load-store chain if any of the
loads had a user other than its store. Now that loads of mixed types
can be unpacked from a vector load, vectorize such chains as well: the
loads become a single vector load, and the external users are fed from
the lanes each load occupies, cast back to the load's type if needed.
The unpacking loop of vectorizeLoads() is factored out into
unpackLoads() (along with the canUnpackLoads() check) and shared by
both paths. Chains with a non-integral pointer load that has external
users are still left alone.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[HLSL] Complete SV_Target support
Implement the remaining SV_Target rules from the HLSL semantics overview
(wg-hlsl proposal 0040). SV_Target is a pixel shader output of up to 8
render targets, each a scalar or vector of up to four 16- or 32-bit floats,
where arrays are allowed and the semantic index must match the signature
row.
- In SPIR-V, the location of an SV_Target output is its semantic index, as in
DXC, rather than the next free output location. An array covers the
consecutive locations of its elements.
- DXIL pixel shader outputs are not indexable, and each render target must be
in the row of its semantic index. An SV_Target array is therefore split into
one single-row signature element per render target. This previously hit an
assertion during signature packing.
- The DirectX backend validates that SV_Target elements use 16- or 32-bit
floating-point components.
Signature elements now also take their semantic kind from the interpretation
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[mlir][arith] Add overflow<zero> to arith.remsi
Define INT_MIN % -1 as zero when overflow<zero> is set, while keeping
this case undefined by default with no additional LLVM runtime checks.
Guard flagged remainders in LLVM and EmitC lowering. Preserve the
zero result through integer narrowing and WebAssembly raising, and
update folding, speculation, operation documentation, and tests.
Tested: 12 affected lit test files.
[mlir][ptr] Use allocation size for type offsets (#236864)
Return the allocation stride from `ptr::TypeOffsetOp::getTypeSize()` so
the C++ query agrees with the operation's element-offset semantics and
its GEP-based lowering. For example, `i24` occupies 3 storage bytes but
has a 4-byte allocation stride under the default data layout.
Assisted-by: Codex / GPT-6
[MLIR][Python] Fix stale multithreaded_tests.py
This test only runs on free-threaded CPython, so it rotted unnoticed. On
3.14t it failed every test and then aborted. Fix it:
- Drop calls to live-operation APIs removed in #155114.
- Compare live contexts against a pre-test baseline, not 0.
- Restore the builtin RankedTensorType caster after binding
TestIntegerRankedTensorType, which hijacked it and caused the abort
(the abort itself is fixed in #237010).
- Only collect test functions defined in each module.
- Skip testMatchInterfaceEnumReplaceAttributeBuilder, which replaces a
global attribute builder used by testMatchInterfaceEnum.
- Without TSAN, skip the xfail list and the np_to_memref tests, which hit
a ctypes race (python/cpython#127945) nondeterministically.
[GlobalISel] Canonicalize more constants
Move scalar constants behind casts and copies, and vector splats, to
the RHS of commutative operations. Keep two constant operands in their
existing order.
Retain commuted identity coverage for casts and splats that constant
folding cannot simplify, and update affected AArch64 and AMDGPU output.
[GlobalISel] Fixup commuted combine matching
Match the subtraction on either side of (A-C1)+C2. Check constants and
use counts through the matched operands.
Look through single-use copies when unmerging constants to avoid extra
AMDGPU materializations. Preserve shared constants and copies, physical
register copies, and constant-fold barriers.
Cover commuted subtraction and copied constants in MIR tests, and update
affected AMDGPU assembly checks.
[GlobalISel] Auto-commute combine patterns
Emit both operand orders for constrained commutative generic match
patterns, including each use of a PatFrag. Skip redundant permutations
and enforce MaxPermutations before allocating expanded alternatives.
Give each permutation its own operand expansions so operand indices
cannot leak between alternatives.
Keep commuted immediate patterns available with constant-to-RHS
canonicalization, and consolidate AMDGPU carry rules while preserving
zero-addend and RHS-first matching.
Make the integer and AMDGPU multiply/select helpers accept either operand
order.
Add emitter documentation and TableGen, MIR, and codegen regressions.
[mlir][arith] Add overflow<zero> to arith.remsi
Define INT_MIN % -1 as zero when overflow<zero> is set, while keeping
this case undefined by default with no additional LLVM runtime checks.
Guard flagged remainders in LLVM and EmitC lowering. Preserve the
zero result through integer narrowing and WebAssembly raising, and
update folding, speculation, operation documentation, and tests.
Tested: 15 affected lit test files.
