RuntimeLibcalls: Use correct type for LDbl
Use the Module / Triple's correct long double type. Previously this
was hardcoded to assume double.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[CIR][SPIR-V] Use the program address space for function aliases (#233720)
Alias initializer pointer was hardcoded to address space 0, which trips
an assertion on spirv64-amd-amdhsa where functions live in space 4
RegAlloc: Fix dead flags of defs after failed allocation
After an allocation failure, the error register may be assigned to
multiple defs of the same instruction. If one of these is dead and
another live, the instruction fails the verifier check added in #233110.
In RegAllocBase, add the failed defs to the error register's regunit
live ranges so a later assignment cannot also def it, and make the dead
flags of the error defs agree with any def already assigned the
register. In RegAllocFast, clear the dead flags of registers with a
live def on instructions using an error assignment.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[lldb][Fortran] Added support for base types to DWARFASTParserFortran (#223406)
This PR adds support for base types to DWARFASTParserFortran, introduces
a method to retrieve the parser from TypeSystemFortran, and adds unit
tests for type parsing.
Changes:
- Added DW_TAG_base_type handling to ParseType.
- Added scope resolution for parsed types.
- Added a method to return the parser from TypeSystemFortran.
- Added unit tests to verify that base types are parsed correctly.
Relates to #109119.
[SLP]Limit rejected tree size for reductions
The overlapping windows of the same reduction rebuild almost the same
trees. Long reductions, like the runtime check chains, spend most of
the time on the rejected wide windows. Like the scheduling region, the
size of the next tree, estimated by the last rejected one, is limited
by -slp-reduction-budget (default is 65536 scalars), reduced by the
sizes of the rejected trees, but not below 2048 scalars, so the
smaller trees are still analyzed. The non-power-of-2 widths get only
2048 scalars for the rejected trees. The budget limits only the series
of the rejected trees, the vectorized tree starts a new series.
Fixes #229372
Assisted-by: Cursor
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/232884
[SLP]Treat trunc X to i1 as bit test (and X, 1) != 0
InstCombine canonicalizes icmp ne (and X, 1), 0 to trunc X to i1,
which blocked bundling it with the other bit tests. Model it as icmp
eq/ne.
Fixes #230768
Assisted-by: Cursor
Reviewers: bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/233124
[lldb][Fortran] Added support for base types to DWARFASTParserFortran, tests for DWARFASTParserFortran and a method to get the parser from TypeSystemFortran
[lldb][Fortran] Added support for basic types in TypeSystemFortran (#223380)
This PR adds support for Base Types (INTEGER, LOGICAL, COMPLEX, REAL).
Changes:
- Adds methods to create types through the FortranType class.
- Manages type lifetimes using a SmallVector.
- Prevents duplicates using a FoldingSet.
- Allows retrieving information about the size, name, and kind of base
type.
Testing is done through TestTypeSystemFortran, which will have all tests
relating to the Type System.
Part of the Add Fortran support to LLDB GSoC 2026 project.
Relates to #109119.
[LiveDebugVariables] Add tests for canonicalizeIndexes (#225375)
Test various paths that leave stale SlotIndexes that reach
canonicalizeIndexes.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
[clang][OpenMP] Extend no-loop promotion to the split teams loop
Widen the no-loop promotion to apply not only to the fused target teams
distribute parallel for but include the same region written as separate
directives, other directives promotable to parallel for, and regions
carrying a schedule clause that asks for a mapping a no-loop kernel
already provides.
Use the SPMD_NO_LOOP kernel tag to carry the promotion decision, based
on whether the kernel can get fully promoted to a no-loop kernel. This
eliminates the previous discrepancy where a clause got the tag but not
the promotion.
[CodeGen] Allow inserting a block that starts with debug instructions in SlotIndexes (#233453)
SlotIndexes::insertMBBInMaps used the index of the new block's first
instruction to decide where to insert the block's start entry. Debug and
pseudo probe instructions have no index, so splitting a block with
LiveIntervals available crashed if the new block started with one. For
example, SIWholeQuadMode splits a block after a lowered demote, and a
DBG_VALUE following the demote made llc crash with -g.
Use the first instruction that has an index instead, or the end of the
previous block if there is none.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[libc++] Mark xopen_source test unsupported on OpenBSD (#233710)
OpenBSD's headers strictly honor _XOPEN_SOURCE. With 500 and 600 the
POSIX.1-2008 locale API (locale_t, uselocale(), LC_*_MASK) is hidden,
and with any value below 800 asprintf() is hidden since it is only
exposed for POSIX.1-2024 or the BSD namespace. libc++'s OpenBSD locale
support relies on these from public headers, so every generated test
fails.
Mark the test unsupported on OpenBSD targets, as is already done for
FreeBSD.
[AMDGPU] Restrict VI VOP3P reals to GFX9. NFCI. (#232069)
VOP3P_Real_vi used HasVOP3PInsts as its AssemblerPredicate, which was
equivalent to GFX9 when VOP3P was introduced, but GFX10+ also have
FeatureVOP3PInsts. This meant that on GFX10+ the asm matcher could
match both the VI real and the real for the current generation, which
have different encodings. It only selected the right one because the VI
reals are defined later.
Use isGFX9Only instead. All GFX9 targets have FeatureVOP3PInsts, and
GFX8 does not have FeatureGFX9Insts, so this does not change which
targets the VI reals are available on, apart from excluding GFX10+.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
Co-Authored-By: Ivan Kosarev <ivan.kosarev at amd.com>
[CostModel] Generic equal type cost model partial reduce (#229426)
When trying to enable partial reductions as a default reduction step in
#228481, a regression was found where a loop that would have been
unrolled if the steps were plain add instructions no longer unrolled.
This is due to inaccurate costs in the default path, especially for code
size.
This updates the basic TTI cost functions to return the cost of the
equivalent arithmetic instruction in the case the input and accumulator
types are the same, otherwise falls back to querying the backend with an
ISD opcode.
[mlir] Fix false positive loops in RegionBranchOpInterface::hasLoop
hasLoop traversed the region graph from each entry region and reported
a loop as soon as it popped an already visited region. The worklist
gets one entry per successor of each terminator, so a region reached
along two paths was popped twice even without a cycle, e.g. when a
region has two terminators that both branch to the same successor
region. hasLoop now reports a loop only if some region reachable from
the parent op can reach itself, using the same check as
isRepetitiveRegion. The visited argument of the traversal stop
condition is no longer used and is removed.
Assisted-by: Claude Code (Claude Opus 5.5)
[lldb][test] Accept legacy register index overflow diagnostic (#233764)
[ARM builder was failing
](https://lab.llvm.org/buildbot/#/builders/18/builds/27896)after I
merged https://github.com/llvm/llvm-project/pull/224147
because `TestXMLRegisterUnion.py` expected the legacy expression parser
to report oversized vector indexes with array index, but on 32-bit ARM
the index `4294967296` overflows long during parsing first, so LLDB
reports invalid index expression `""` instead. The command still fails
correctly; only the test’s expected diagnostic was too specific.
Co-authored-by: Bar Soloveychik <barsolo at fb.com>
[clang][OpenMP] Emit lastprivate final copies in no-loop kernels
Promotion rejected lastprivate because the no-loop branch leaves the
worksharing path before it privatizes or copies out, so the clause would
have been silently dropped.
Privatize the non-counter variables in the parallel region and copy them
out under the last iteration that applyWorkshareLoop publishes, forcing
the exit barrier the copy reads through. Loop counters stay at the
distribute level and reach EmitOMPSimdFinal.
[NFC][AArch64][FrameLowering] Refactor handling of Callee-Saved spill pairs (#233405)
This PR is preparation for a subsequent PR that will enable quad spills.
The main refactor is adding functions to RegGroupInfo that are dynamic
to the number of registers in a RegGroup.
The subsequent PR will expand these functions for Quad ZPR spills.
A test was also added to show the before/after of this refactor and to
catch any errors in MIR after frame lowering.
