LLVM/project 231c432 — clang/include/clang/AST Expr.h, clang/lib/Sema SemaOverload.cpp SemaInit.cpp

by Akash Manna via GitHub on ⎇
[clang][Sema] Expand `#embed` in braced lists that initialize non-aggregates (#231938)

Fixes #222796

A multi-byte `#embed` inside braces is one `EmbedExpr`, and only
aggregate initialization slices it. Every other consumer of the braced
list counted it as a single element, so `X x = { #embed ... }` called
the constructor with the first byte only, and a reference or fixed enum
silently took the first byte instead of being rejected.

`Sema::getInitsWithEmbedExpanded()` hands those consumers the list with
each multi-element `EmbedExpr` split into one single-element `EmbedExpr`
per byte, the same slices aggregate initialization already builds.
Constructor selection, braced-argument overload resolution and CTAD use
it; the single-element and excess-element checks go through the new
`InitListExpr::hasZeroInits()` / `hasOneInit()`. Aggregates still keep
the whole `EmbedExpr`.

For more reference, see https://github.com/llvm/llvm-project/pull/218262

    [2 lines not shown]
DeltaFile
+157-1clang/test/SemaCXX/embed-init-list.cpp
+63-19clang/lib/Sema/SemaInit.cpp
+27-0clang/test/Preprocessor/embed_constexpr.cpp
+13-13clang/lib/Sema/SemaOverload.cpp
+11-0clang/test/Preprocessor/embed_codegen.cpp
+11-0clang/include/clang/AST/Expr.h
+282-334 files not shown
+300-3310 files

LLVM/project 33bb824 — mlir/include/mlir/Dialect/XeGPU/Transforms XeGPULayoutImpl.h, mlir/lib/Dialect/XeGPU/Transforms XeGPUPropagateLayout.cpp XeGPULayoutImpl.cpp

by Nishant Patel via GitHub on ⎇
[MLIR][XeGPU] Rematerialize layout conversion sources after conflict resolution (#230669)

This PR separates layout conflict resolution from rematerialization. The
resolver now inserts xegpu.convert_layout for conflicts ....a following
step clones eligible, cheap vector producer chains in the target layout
and replaces those conversions. This avoids SLM round trips.
DeltaFile
+204-0mlir/test/Dialect/XeGPU/rematerialize-conversion-sources.mlir
+75-13mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
+37-24mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+15-41mlir/test/Dialect/XeGPU/resolve-layout-conflicts.mlir
+32-0mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
+12-7mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h
+375-856 files

LLVM/project 6354b57 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVLandingPadSetup.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+35-8llvm/lib/Target/RISCV/RISCV.h
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+22-7llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+8-8llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+162-621 files not shown
+167-627 files

LLVM/project 234ee35 — llvm/lib/Target/RISCV RISCVLandingPadSetup.cpp RISCVMakeCompressible.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+43-10llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+32-8llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+22-7llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+194-642 files not shown
+210-748 files

LLVM/project bbbc1cb — llvm/lib/Target/RISCV RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rvp-scalar.ll

by Hank Chang via GitHub on ⎇
[RISCV][P-ext] Add isel patterns for mul.h01/mul.h11 and macc.h01/macc.h11 (#234976)

`mul.h01` multiplies the lower half word of rs1 by the upper half word
of rs2, and `mul.h11` multiplies the upper half words of both.
`macc.h01/h11` add the product to rd.

Previously, (sra X, 16) was selected as a separate srai feeding
`mul/macc.h00`. Match it directly so the shift is folded. As with
`macc.h00`, the macc patterns require the multiply to have a single use.
DeltaFile
+222-0llvm/test/CodeGen/RISCV/rvp-scalar.ll
+15-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+237-02 files

LLVM/project 8bd62b1 — llvm/lib/Target/RISCV RISCVPassRegistry.def RISCVTargetMachine.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+27-6llvm/lib/Target/RISCV/RISCV.h
+22-7llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+6-6llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+4-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+128-406 files

LLVM/project e22cd33 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVLandingPadSetup.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+35-8llvm/lib/Target/RISCV/RISCV.h
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+22-7llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+8-8llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+162-621 files not shown
+167-627 files

LLVM/project 342dcd8 — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize interleave_uncountable_exits.ll

by Luke Lau on ⎇
[VPlan] Move extract-lane(0, canWideIV) combine before unrolling

Some extract-lane combines can't be performed before unrolling, e.g. the one that combines it to Instruction::ExtractElement can end up extracting from a different part. But the extract-lane(0, canWideIV) can because at index 0 you're always extracting from the first part. Do this before unrolling, which improves codegen of unrolled code.
DeltaFile
+5-80llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
+16-24llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+6-6llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-8llvm/test/Transforms/PhaseOrdering/AArch64/countable-and-uncountable-exits-combined.ll
+1-7llvm/test/Transforms/LoopVectorize/interleave_uncountable_exits.ll
+29-1255 files

LLVM/project 0fd85a4 — llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanUnroll.cpp, llvm/test/Transforms/LoopVectorize interleave_uncountable_exits.ll

by Luke Lau on ⎇
[VPlan] Support interleaving early exit loops with side effects

We couldn't do this on main previously because the exit mask `active-lane-mask(0, FirstActiveLane(Cond))` doesn't get unrolled properly across parts. Now that we use mask.beforefirst we can unroll it properly in a chain. The unrolled form is:

    unroll(mask.beforefirst, P) = mask.beforefirst(cond[P] | broadcast(anyof(not(unroll(mask.beforefirst, P-1)))))

On AArch64 this can be combined to brkpb in another patch.
DeltaFile
+216-15llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
+35-4llvm/test/Transforms/PhaseOrdering/AArch64/countable-and-uncountable-exits-combined.ll
+31-7llvm/test/Transforms/LoopVectorize/interleave_uncountable_exits.ll
+11-0llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
+0-9llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+293-355 files

LLVM/project 91884de — llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize early_exit_combined_exits.ll early_exit_with_stores.ll

by Luke Lau on ⎇
[VPlan] Use llvm.mask.beforefirst for computing early exit mask

This makes the cost more accurate and improves codegen for RISC-V. The codegen for an early exit loop with side effects then goes from:

    .LBB0_3:                                # %vector.body
                                            # =>This Inner Loop Header: Depth=1
        vl1r.v  v16, (a3)
        vsetvli zero, zero, e8, m1, ta, ma
        vmseq.vi        v16, v16, 0
        vfirst.m        a7, v16
        srli    t0, a7, 63
        czero.nez       a7, a7, t0
        czero.eqz       t0, a1, t0
        or      a7, t0, a7
        vsetvli zero, zero, e64, m8, ta, ma
        vmsltu.vx       v0, v8, a7
        vle8.v  v17, (a5), v0.t
        vcpop.m t1, v16
        vsetvli zero, zero, e8, m1, ta, ma

    [22 lines not shown]
DeltaFile
+50-50llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
+40-40llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+18-18llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
+21-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+10-10llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
+8-8llvm/test/Transforms/LoopVectorize/early_exit_combined_exits.ll
+147-1267 files not shown
+166-14413 files

LLVM/project 3df1a2e — clang/lib/CIR/CodeGen CMakeLists.txt

by Jinsong Ji via GitHub on ⎇
[CIR][CMake] Fix MSVC PCH ambiguity after 0173f46b7d9d (#235058)

0173f46b7d9d added a PCH for clangCIR that includes
CIRGenFunction.h, which forward-declares ScalarExprEmitter in an
anonymous namespace. MSVC treats the anonymous namespace from the PCH
as distinct from the one in CIRGenExprScalar.cpp, causing error C2872
('ScalarExprEmitter': ambiguous symbol). Skip the PCH for that file on
MSVC.

Assisted-By: Claude Opus 5.5
DeltaFile
+8-0clang/lib/CIR/CodeGen/CMakeLists.txt
+8-01 files

LLVM/project 6c3fca3 — llvm/lib/Target/RISCV RISCVPassRegistry.def RISCVTargetMachine.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+27-6llvm/lib/Target/RISCV/RISCV.h
+22-7llvm/lib/Target/RISCV/RISCVLandingPadSetup.cpp
+6-6llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+4-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+128-406 files

LLVM/project 15be7ab — llvm/lib/Target/RISCV RISCVPassRegistry.def RISCVTargetMachine.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+19-4llvm/lib/Target/RISCV/RISCV.h
+5-5llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+3-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+96-305 files

LLVM/project 9758586 — llvm/include/llvm/CodeGen SlotIndexes.h, llvm/lib/CodeGen LiveIntervals.cpp SlotIndexes.cpp

by Petar Jovanovic on ⎇
[CodeGen] Drop dead SlotIndexes before allocation

SlotIndexes keeps the index list entry of an erased instruction and only
clears its instruction pointer. Live range sizes are measured in slot
indexes and greedy ranks ranges by size, so the leftovers inflate some
ranges more than others and reorder allocation, spilling heavily on
register-starved functions.

Add SlotIndexes::compactIndexes() to erase them. Erased entries are
unlinked, so holding an index to one is now a bug; linkedEntry() asserts
on it. The one analysis that did was LiveIntervals, so add
removeUnreferencedIntervals() to retire the intervals responsible.

Off by default behind -greedy-compact-slot-indexes, since it changes
allocation across much of the test suite.

The test file greedy-compact-slot-indexes-priority.mir by Q. Colombet.
DeltaFile
+288-0llvm/unittests/CodeGen/SlotIndexesTest.cpp
+82-0llvm/test/CodeGen/AMDGPU/greedy-compact-slot-indexes-priority.mir
+43-0llvm/lib/CodeGen/SlotIndexes.cpp
+35-0llvm/test/CodeGen/AMDGPU/greedy-compact-slot-indexes.ll
+23-6llvm/include/llvm/CodeGen/SlotIndexes.h
+17-0llvm/lib/CodeGen/LiveIntervals.cpp
+488-62 files not shown
+504-78 files

LLVM/project a7a659b — llvm/test/CodeGen/X86 greedy-inline-asm-fold.mir

by Bill Wendling on ⎇
[TargetInstrInfo] Address review: write the two-register flag symbolically

Now that the operand count of an inline asm flag can be written in MIR, use
"reguse:GR64 foldable ops:2" instead of an immediate whose register class ID
changes whenever a register class is added. Regenerate the checks, which
now print the five operands of each x86 memory reference as "ops:5".

Assisted-by: Claude Opus 5.5
DeltaFile
+10-12llvm/test/CodeGen/X86/greedy-inline-asm-fold.mir
+10-121 files

LLVM/project 0c290fc — llvm/docs AMDGPUUsage.rst, llvm/test/CodeGen/NVPTX store-sm60.ll load-sm70.ll

by Bill Wendling on ⎇
Merge branch 'users/void/mir-inline-asm-operand-count' into users/void/asm-rm-2-fold-tied-operands
DeltaFile
+22,584-0llvm/test/CodeGen/NVPTX/load-sm90.ll
+0-22,223llvm/docs/AMDGPUUsage.rst
+21,644-0llvm/test/CodeGen/NVPTX/store-sm90.ll
+20,068-0llvm/test/CodeGen/NVPTX/load-sm60.ll
+19,684-0llvm/test/CodeGen/NVPTX/load-sm70.ll
+19,088-0llvm/test/CodeGen/NVPTX/store-sm60.ll
+103,068-22,2236,067 files not shown
+483,430-170,5116,073 files

LLVM/project 65eac67 — llvm/lib/Target/RISCV RISCVPassRegistry.def RISCVTargetMachine.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+11-2llvm/lib/Target/RISCV/RISCV.h
+3-3llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+53-164 files

LLVM/project c8afd1a — llvm/lib/Target/RISCV RISCVPassRegistry.def RISCVTargetMachine.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+19-4llvm/lib/Target/RISCV/RISCV.h
+5-5llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+3-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+96-305 files

LLVM/project 3cb7199 — llvm/include/llvm/IR InlineAsm.h, llvm/lib/CodeGen/MIRParser MIParser.cpp

by Bill Wendling on ⎇
[MIR] Serialize the operand count of inline asm operand flags

An inline asm operand flag is followed by the number of operands that it
says: e.g. two registers for an i128 or an i386 "A" output, or the five
operands of an x86 memory reference. The symbolic flag syntax had no way to
write that count, so the printer dropped it and the parser assumed one.
Printed MIR with such a flag didn't parse back correctly: the operands
after the first were read as further flags or as stray operands, which the
machine verifier rejects. Tests had to write such a flag as an immediate,
whose register class ID changes whenever a register class is added.

Print the count as "ops:N" at the end of the flag when it isn't 1, and
parse it back, e.g.:

  INLINEASM &"", attdialect, mem:m ops:5, %stack.0, 1, $noreg, 0, $noreg
  INLINEASM &"", attdialect, reguse:GR64 foldable ops:2, %0, %1

A count of 0 is accepted, since the printer emits whatever count the flag
holds; peephole-copy.mir writes "1 /* clobber */", which is a reguse flag

    [3 lines not shown]
DeltaFile
+31-0llvm/lib/CodeGen/MIRParser/MIParser.cpp
+29-0llvm/test/CodeGen/MIR/X86/inline-asm-operand-count.mir
+13-0llvm/include/llvm/IR/InlineAsm.h
+11-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-count.mir
+11-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-missing-colon.mir
+11-0llvm/test/CodeGen/MIR/Generic/inline-asm-ops-too-large.mir
+106-07 files not shown
+121-913 files

LLVM/project 468782c — clang/lib/CIR/Dialect/Transforms CIRCanonicalize.cpp CIRSimplify.cpp

by Bruno Cardoso Lopes via GitHub on ⎇
[CIR] Scope Canonicalize/Simplify greedy rewrites to the body region (#234810)

Pass a GreedyRewriteConfig scoped to the body region at the three
greedy-rewrite call sites (CIRCanonicalize, CIRSimplify twice) instead
of letting the driver search for the common ancestor of the collected
ops. The body region encloses the ancestor the driver would find, so
this only skips the search.

The wider scope can additionally simplify region ancestors the narrow
one would not reach, but every rewrite stays semantics-preserving.
Measured on the investigation branch: TosaProfileCompliance -fclangir
end to end drops from 118.3s to about 109s.
DeltaFile
+10-3clang/lib/CIR/Dialect/Transforms/CIRSimplify.cpp
+5-2clang/lib/CIR/Dialect/Transforms/CIRCanonicalize.cpp
+15-52 files

LLVM/project 37503a5 — libc/src/__support/math CMakeLists.txt cosh.h, libc/test/src/math cosh_test.cpp

by Tue Ly on ⎇
[libc][math] Implement double precision cosh correctly rounded to all rounding modes.

Use shared exp(x) +- exp(-x) evaluations with sinh from https://github.com/llvm/llvm-project/pull/235097.

Assisted-by: Gemini for analysis and refactoring.
DeltaFile
+187-0libc/test/src/math/cosh_test.cpp
+125-0libc/test/src/math/smoke/cosh_test.cpp
+94-0libc/src/__support/math/cosh_double_eval.h
+34-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+34-0libc/src/__support/math/cosh.h
+29-0libc/src/__support/math/CMakeLists.txt
+503-024 files not shown
+631-130 files

LLVM/project 9e860ba — llvm/include/llvm/CodeGen MachineInstr.h, llvm/lib/CodeGen MachineInstr.cpp

by Bill Wendling on ⎇
[TargetInstrInfo] Address review: don't fold a subregister that isn't at the start of the slot

A folded operand refers to the start of the stack slot, which holds the
whole register, so a subregister is only there if it's at bit offset 0 on a
little-endian target. Folding x86's sub_8bit_hi read byte 0 instead of byte
1. Folding several operands at once made this worse: two operands holding
different subregisters of one value (e.g. "Qm"(lo), "Qm"(hi)) both read
byte 0.

Check the subregister in mayFoldInlineAsmRegOp, so the spill weights agree
with what folds. A tied def is covered too, since its tied use has the same
subregister.

Assisted-by: Claude Opus 5.5
DeltaFile
+112-0llvm/test/CodeGen/X86/greedy-inline-asm-fold.mir
+11-0llvm/lib/CodeGen/MachineInstr.cpp
+2-1llvm/include/llvm/CodeGen/MachineInstr.h
+125-13 files

LLVM/project b0e5493 — llvm/lib/CodeGen TargetInstrInfo.cpp MachineInstr.cpp

by Bill Wendling on ⎇
Move folding register checks into mayFoldInlineAsmRegOp so that it's available everywhere.
DeltaFile
+9-0llvm/lib/CodeGen/MachineInstr.cpp
+1-7llvm/lib/CodeGen/TargetInstrInfo.cpp
+10-72 files

LLVM/project 16dde0d — llvm/lib/Target/SystemZ SystemZISelLowering.cpp

by Aiden Grossman via GitHub on ⎇
[SystemZ] Fix -Wunused-variable in bcb301d (#235171)

Variable ends up only being used in assertions afterwards which fires
-Wunused-variable in release builds.
DeltaFile
+1-1llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+1-11 files

LLVM/project a57c6df — llvm/test/tools/llvm-exegesis/X86 snippet-generator-seed.test, llvm/tools/llvm-exegesis/lib SnippetGenerator.cpp

by Chandler Carruth via GitHub on ⎇
[llvm-exegesis] Avoid instability from `std::uniform_int_distribution` (#234516)

The standard doesn't require a stable order, and we see active variation
between libstdc++ and libc++ when using this. Follow the pattern of
`llvm::shuffle` and manually clamp with `%` instead.

Also removes an unnecessary `REQUIRES` that gets this to run in
pre-merge CI.

Assisted-by: Antigravity with Gemini
DeltaFile
+8-2llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+3-5llvm/test/tools/llvm-exegesis/X86/snippet-generator-seed.test
+11-72 files

LLVM/project d232ab8 — llvm/lib/CodeGen TargetInstrInfo.cpp

by Bill Wendling via GitHub on ⎇
Update llvm/lib/CodeGen/TargetInstrInfo.cpp

Co-authored-by: Nick Desaulniers <ndesaulniers at google.com>
DeltaFile
+1-1llvm/lib/CodeGen/TargetInstrInfo.cpp
+1-11 files

LLVM/project cebe3e9 — flang/lib/Evaluate int-power.h

by Michael Kruse on ⎇
IntPower: safety condition
DeltaFile
+3-23flang/lib/Evaluate/int-power.h
+3-231 files

LLVM/project b344a11 — flang/lib/Evaluate int-power.h

by Michael Kruse on ⎇
Post-merge fix: avoid two different algorithms
DeltaFile
+13-1flang/lib/Evaluate/int-power.h
+13-11 files

LLVM/project e9d8621 — mlir/lib/Dialect/SCF/Transforms LoopSpecialization.cpp, mlir/test/Dialect/SCF for-loop-peeling.mlir

by Prashanth via GitHub on ⎇
[mlir][scf] add support for unsigned loop for back peeling (#234435)

- add support for unsigned loop for back peeling
- fix sub overflow bug in the signed path
- remove unsigned operation check in dispatcher
- return early if unsigned in `peelForLoopAndSimplifyBounds` since
affine.min/max does not hold for unsigned loops
- add tests for edge cases in unsigned, sub overflow and no bound
simplification for unsigned

from https://github.com/llvm/llvm-project/pull/231100

claude helped me with the tests and correctness.
DeltaFile
+166-0mlir/test/Dialect/SCF/for-loop-peeling.mlir
+82-46mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
+248-462 files

LLVM/project b67e7bb — clang/include/clang/Basic MSP430Target.def, clang/include/clang/Basic/Target/MSP430 gen-msp430-def.py

by Robin Mueller via GitHub on ⎇
[MSP430] Update msp430 generator (#228006)

- gen-msp430-def.py was updated to include the CPU type. Current CPU types are msp430, msp430x and msp430xv2. This is useful information for determining whether extended instructions are valid on a given target.
- Adds a new hwmult variant called f5series. The script now maps the HWMPY value of 8 to this variant. This is important because the f5series hardware multiplier has a different base address compared to older MPY32 support.
- Also added new tests with a newer target containing a f5series hardware multiplier. The auto mode will now also correctly map to include f5series support if the MCU supports this.

Based on https://reviews.llvm.org/D108301 by Jozef Lawrynowicz.

Co-authored-by: Jozef Lawrynowicz <jozefl.opensrc at gmail.com>
Assisted-by: Claude Code (Claude Opus 5.5)
DeltaFile
+651-639clang/include/clang/Basic/MSP430Target.def
+66-34clang/include/clang/Basic/Target/MSP430/gen-msp430-def.py
+2-2clang/lib/Driver/ToolChains/MSP430.cpp
+4-0clang/test/Driver/msp430-toolchain.c
+2-0clang/test/Driver/msp430-hwmult.c
+725-6755 files