[AMDGPU] Canonicalize num_records to its actual width in InstCombine
llvm.amdgcn.make.buffer.rsrc is overloaded on the type of its
num_records argument, but the hardware field it ends up in has a fixed
width (32 bits, or 45 bits on gfx1250 and up). Rewrite the intrinsic to
use that width, zero-extending or truncating num_records as needed, so
that IR-level optimizations can see that the extra bits of, for example,
the i64 that Clang emits are not demanded.
Targets that aren't concrete enough for the buffer resource layout to be
known are left alone.
AI disclosure: This was my idea but Claude wrote the code (and I've
tried to tighten up the comments)
[AMDGPU] Pre-commit tests for num_records canonicalization
Add tests for having InstCombine canonicalize the num_records argument
of llvm.amdgcn.make.buffer.rsrc to the width it will ultimately have,
which lets later passes see that, for example, the high bits of the i64
that Clang emits aren't used.
AI disclosure: Claude generated these and I've looked at them
[AMDGPU] Use real num_records width in LowerBufferFatPointers
Fix the following edge cases in reasoning about whether a value can be
The out-of-bounds analysis in LowerBufferFatPointers took the
num_records operand of llvm.amdgcn.make.buffer.rsrc at face value, which
went wrong in three ways.
1. The pass would crash if num_records was narrower than the
underlying hardware width.
2. A 45-bit num_records with its high bit set made all offsets look
negative, which, among other things, broke the `(1 << 45) - 1` "no
bounds checking" value.
3. The test for all-1 num_records wasn't accounting for hardware
width, leading to false positives if the num_records field was
narrower tan the underlying field.
4. Don't try to do reasoning about num_records when its width isn't
known.
AI disclosure: Claude found and took a try at fixing these, I've
reviewed
[mlir][AMDGPU] Emit num_records at the buffer resource's actual width
makeBufferRsrc() zero-extended num_records to i64 on targets whose
buffer resource has a 45-bit num_records field, leaving 19 bits that the
hardware will never look at. Emit an i45 instead, which is what
rocdl.make.buffer.rsrc will end up putting in the descriptor anyway, so
that downstream consumers can see that those bits aren't demanded.
While here, factor the i32 and i64 conversion helpers into a shared
convertUnsignedToInt() that takes the target width.
AI disclosure: Claude made this, I looked at and poked the design into
shape.
[AMDGPU] Pre-commit num_records of arbitrary width tests for LowerBufferFatPointers
Add tests to ensure that the reasoning for whether an access can be
partially out of bounds and needs to be scalarized work correctly when
num_records has a width different from the hardware width.
AI disclosure: Claude generated these and I've looked at them
[AMDGPU] Track buffer resource num_records width in a subtarget field
Replace the boolean 45-bit-num-records-buffer-resource subtarget
feature's `Has45BitNumRecordsBufferResource` flag with a numeric
`BufferResourceNumRecordsWidth` field.
AI disclosure: Code by Claude, comments and wordings by me
[SelectionDAG] Preserve CTTZ_ELTS lane count during expansion (#217982)
Fixes #216649
`expandCttzElts` derives `VL` from its legalized auxiliary step vector.
When that helper vector is widened for target legality, its lane count
may differ from the logical lane count of the `CTTZ_ELTS` operand.
On X86 with AVX512F, the step vector for a semantic `<4 x i1>` mask is
widened from `v4i8` to `v16i8`. As a result, an all-zero
`llvm.experimental.cttz.elts` input returns 16 instead of the required
result of 4.
Preserve the `ElementCount` from the `CTTZ_ELTS` operand and use it when
materializing `VL`. Auxiliary step-vector legalization can still widen
its representation without changing the logical lane domain of the
operation.
Add AVX512F regression coverage for the affected `v4i1` and `v8i1`
cases.
[LLVMABI] Skip data-free members when reducing a union (#218532)
While implementing union support for ClangIR, I found that
`reduceUnionForX8664` can choose a member holding no data as the type
representing the union. It chooses by alignment and then by size, and an
over-aligned empty class or an array of empty records wins either
comparison, so the coercion comes out wider than Clang's.
Clang does not need this skip because it compares lowered types, where
an empty class is a byte array it can narrow the coercion through. A
record reaching this library has no fields, so there is nothing to
narrow through.
This change skips members holding no data, using `bitsContainNoUserData`
to identify them.
Assisted-by: Cursor / claude-opus-5
[CIR] Update CHECK lines for the nofreeobj rename
#218404 renamed classic's indirect-argument attribute from nofree to
nofreeobj. Five OGCG lines across two tests still pinned the
old spelling.
Assisted-by: Cursor / claude-opus-5
[mlir][transform] Add ApplySwapExtractSliceWithFillPatternsOp transform op (#213907)
Adds transform op for the existing linalg `SwapExtractSliceOfFill`
pattern as `apply_patterns.linalg.swap_extract_slice_with_fill`.
Assisted-by: GPT-5.3-Codex
Fix wasm test target requirement (#218686)
The new wasm tests need an extra `REQUIRES
webassembly-registered-target` guard to prevent build failures:
#215562
[X86] fix `va_arg` alignment of `f128` (#218017)
fixes https://github.com/llvm/llvm-project/issues/217747
In a c-variadic call, an `f128` argument is passed with an alignment of
16, but was read with an alignment of only 4, often at the wrong offset
in the `va_list`.
Some types this does not cover:
- `__int128` (needs `-fforce-enable-int128` for i386)
- `_Complex __float128`
Those still get an alignment of 4.
[compiler-rt] Add version info to Windows runtime DLLs (#216408)
Windows runtime DLLs built by compiler-rt currently do not include
VERSIONINFO metadata. This leaves fields such as FileVersion,
ProductName, and ProductVersion empty in Windows file properties.
LLVM and Clang already use windows_version_resource.rc to add this
metadata to Windows executables and shared libraries. compiler-rt uses a
separate CMake helper for runtime libraries, so its DLLs do not inherit
that support.
Add compiler-rt support for attaching the shared LLVM Windows version
resource to MSVC shared runtime targets. The resource file is copied to
a target-specific file before being added as a source, so each DLL can
use its own source properties.
Use LLVMVersion.cmake to fill in the version fields. This gives runtime
DLLs such as clang_rt.asan_dynamic-x86_64.dll FileVersion and
ProductVersion values matching the LLVM version.
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[Transforms] Infer attributes for posix_memalign
posix_memalign writes the allocated pointer through its first argument but does not retain the address of that output slot. Model the contract with noundef, nounwind, willreturn, captures(none), writeonly, and arg/inaccessible/errno memory effects.
The missing capture information caused Attributor to treat an alloca passed to posix_memalign as escaped, preventing noalias inference at a later callback call site. Test both the inferred declaration attributes and the OpenMP callback-lifetime case that exposed the missing model.
[OpenMP] Seed noalias for host callback captures
The generic Attributor can derive noalias and the related lifetime facts for callback-mapped capture arguments, but OpenMPOpt does not seed AANoAlias in its restricted host run. Consequently capture-container loads remain in loops under dereferenceable-at-point semantics.
Seed AANoAlias for pointer arguments mapped to broker operands by callback metadata. Existing call-site reasoning checks every callback and direct call site and rejects escaped or aliased slots. LICM can then hoist immutable capture-container loads without changing the callback ABI or adding an OpenMP-specific hoisting transform.
Add LLVM, Clang, and Flang coverage for pointer, scalar, and aggregate captures together with escaped, duplicated, unmapped, and unknown-use negatives.
[Attributor] Check callback broker argument aliases correctly
AbstractCallSite uses separate callback argument and broker operand numbers. AANoAliasCallSiteArgument currently skips the callback argument number while iterating broker operands, which can skip an unrelated operand and incorrectly infer noalias for aliased callback arguments.
Skip the mapped call-site operand instead. Add a duplicated-operand regression where the callback and broker argument numbers differ.
[lldb][NativePDB] Build parent map on demand (#216821)
Currently, the PDB plugin builds a map from nested structs to parents,
because such a mapping is not available in the TPI stream. To do this,
we're walking the entire TPI stream. If that stream is large, this can
take time. We've been doing this in `InitializeObject`, so it
immediately ran. Inside the same function, we're also scanning the
basenames of types for `FindTypes`.
When the debugger starts, we usually don't need this information, as we
don't create/query any types at that point. Thus, I made this lazy.
Running `build-rel/bin/lldb build-dbg/bin/lldb -o r -o q -- -o q` goes
from 8.8s to 7.6s. The majority of time is still spent in
`Symtab::InitNameIndexes` preloading symbols. We could try to
parallelize that if we have some worker threads to spare. Which, in this
case, we do.
[PowerPC][Clang] fix IEEE f128 complex div/mul use IBM f128 libcalls on powerpc (#218151)
fixes https://github.com/llvm/llvm-project/issues/216820
Previously the IBM f128 libcall was used also for IEEE f128 complex
mul/div.
[clang][bytecode] Add `StringPointer` (#216736)
This is a new pointer type that points to a string literal. We do not
allocate any memory for it but we _can_ read from it.
A `StringPointer` only consists of a `StringLiteral` (or rather a
"Base", which can also be a `PredefinedExpr`), and an ID which is only
increased on `GetStringPtr` ops. This way we can know whether two
literals have been created via the same evaluation. This is needed for
the "overlapping string literals" diagnostics, particularly in the loop
case:
```c++
constexpr bool different_in_loop(bool b = false) {
if (b) return false;
const char *p[2] = {};
for (const char *&r : p)
r = "hello";
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[AArch64][GISel] Allow import of DAG FCVT/CVTF patterns using fixedpoint immediate (#215812)
Currently, fp_to_int(fmul) patterns only work for DAG, this is due to
the use of fixedpoint immediate type which GISel could not import.
Add GlobalISel matchers for fixed-point immediates, allowing these
patterns to be imported and used during instruction selection.
I originally added these to allow fp_to_int(fmul) fold DAG patterns from
this [PR](https://github.com/llvm/llvm-project/pull/210987) to import,
but this also enables fdiv(int_to_fmul) folds to work in GISel
[AArch64] Reject non-scalable types in named Z-register constraints (#217551)
LLVM currently handles typed named Z-register constraints
inconsistently. Depending on the operand type and whether SVE is
available, compilation may succeed, crash, or trigger an assertion.
Reject typed Z-register operands when SVE or streaming SVE is
unavailable, and reject non-scalable operand types. Preserve the
existing behavior for untyped Z-register clobbers.
Fixes #169027
[AArch64][Atomics] Add test file for testing <1xTy> store atomics (#216028)
Currently, there exists no testing for <1xTy> store atomic.
These used to throw a widening legalization error but was fixed due to
this [PR](https://github.com/llvm/llvm-project/pull/197618)
Add these tests for AArch64 to ensure regression does not occur.
Note: Currently <1xi64> has a instruction selection issue and this is
why it has not been added.
A future patch will fix this case.
