LLVM/project 6b98f6f — llvm/lib/Target/RISCV RISCVLateBranchOpt.cpp RISCVDeadRegisterDefinitions.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+96-21llvm/lib/Target/RISCV/RISCV.h
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+345-1859 files not shown
+520-25215 files

LLVM/project 335d950 — llvm/lib/Target/RISCV RISCVInsertReadWriteCSR.cpp RISCVDeadRegisterDefinitions.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+105-23llvm/lib/Target/RISCV/RISCV.h
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+30-18llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
+356-18710 files not shown
+564-27516 files

LLVM/project f17204b — llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

by Eric Ross via GitHub on ⎇
[KnownFPClass] Combine fpext and fptrunc into a shared routine (#225188)

Implements https://github.com/llvm/llvm-project/issues/219847
Partially addresses https://github.com/llvm/llvm-project/issues/219300
Fixes:
- `DenormalMode` handling by `fptrunc`/`fpext`
- `fpext` no longer rules out `qNaN` if the input could be `sNaN`.

Changes:
- `fptrunc` now takes the input/output types.
- `fpext`/`fptrunc` take the `DenormalMode` of the source/destination
types.

I completely rewrote `fpext` and `fptrunc` to use a shared `fpconvert`
routine. Using an approach of starting from `fcAllFlags` and removing
classes instead of starting from `KnownSrc` and adding classes. This
rewrite also improves some deductions for `fptrunc`.

The internal `fpconvert` routine I added should also be able to handle

    [13 lines not shown]
DeltaFile
+227-3llvm/test/Transforms/Attributor/nofpclass-fpext.ll
+207-17llvm/test/Transforms/Attributor/nofpclass-fptrunc.ll
+122-29llvm/lib/Support/KnownFPClass.cpp
+21-2llvm/lib/Analysis/ValueTracking.cpp
+17-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+12-6llvm/include/llvm/Support/KnownFPClass.h
+606-594 files not shown
+630-7510 files

LLVM/project f90ebb2 — llvm/lib/Target/RISCV RISCVQCRelaxMarking.cpp RISCVLateBranchOpt.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+86-18llvm/lib/Target/RISCV/RISCV.h
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+288-1477 files not shown
+427-19913 files

LLVM/project 97298f7 — llvm/lib/Target/RISCV RISCVLateBranchOpt.cpp RISCVDeadRegisterDefinitions.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+78-46llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+96-21llvm/lib/Target/RISCV/RISCV.h
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+345-1859 files not shown
+520-25215 files

LLVM/project 2a0a572 — llvm/lib/Target/RISCV RISCVIndirectBranchTracking.cpp RISCVQCRelaxMarking.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+74-16llvm/lib/Target/RISCV/RISCV.h
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+31-10llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+263-1245 files not shown
+366-16311 files

LLVM/project 4a62511 — llvm/lib/Target/RISCV RISCVQCRelaxMarking.cpp RISCVLateBranchOpt.cpp

by Aiden Grossman on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+61-58llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+86-18llvm/lib/Target/RISCV/RISCV.h
+44-31llvm/lib/Target/RISCV/RISCVPromoteConstant.cpp
+38-11llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+28-18llvm/lib/Target/RISCV/RISCVLateBranchOpt.cpp
+31-11llvm/lib/Target/RISCV/RISCVQCRelaxMarking.cpp
+288-1477 files not shown
+427-19913 files

LLVM/project 3e00dc0 — libc/src/__support/math tanpif16.h tanpif.h

by c8ef on ⎇
address review comments
DeltaFile
+7-6libc/src/__support/math/tanpif16.h
+7-6libc/src/__support/math/tanpif.h
+14-122 files

LLVM/project 35c7d63 — llvm/lib/Target/X86 X86InstrInfo.cpp, llvm/test/CodeGen/X86 pr234931.ll expand-post-ra-pseudo.mir

by Matt Arsenault on ⎇
X86: Fix inconsistent dead flags when expanding MOV32ri64

The expansion added a live implicit-def of the 64-bit register and
kept the original dead flag on the 32-bit def. The implicit-def is
unnecessary since the 32-bit def covers the same register units.
Drop it, and only mark the 32-bit def dead if the instruction has no
other live def of it, matching what LiveVariables would produce.

Fixes #234931

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+40-0llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir
+20-0llvm/test/CodeGen/X86/pr234931.ll
+6-4llvm/lib/Target/X86/X86InstrInfo.cpp
+66-43 files

LLVM/project 458d7b5 — llvm/lib/Target/X86 X86InstrInfo.cpp, llvm/test/CodeGen/X86/apx compress-evex-shld-shrd-commute.mir two-address-shld-shrd-commute.mir

by Feng Zou via GitHub on ⎇
[X86][APX] Fix commuting SHLD/SHRD NF, NF_ND and EVEX variants (#233873)

All SHLD/SHRD rri8 variants are marked commutable, but
commuteInstructionImpl only rewrote the legacy and _ND opcodes as SHLD
B, C, I <-> SHRD C, B, (BitWidth - I). The _NF, _NF_ND and _EVEX
variants fell through to the generic commute, which only swaps the
sources and changes the result.

This is reachable when optimizeCompareInstr converts an EFLAGS clobber
to its NF form (e.g. SHLD16rri8_ND -> SHLD16rri8_NF_ND) and RA assigns
the destination to the second source: X86CompressEVEX commutes it to
drop the redundant NDD destination and emits the wrong shift. The
TwoAddressInstruction pass can hit the same bug when commuting the
non-NDD _NF and _EVEX forms.

Assisted-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+422-0llvm/test/CodeGen/X86/apx/two-address-shld-shrd-commute.mir
+189-0llvm/test/CodeGen/X86/apx/compress-evex-shld-shrd-commute.mir
+30-20llvm/lib/Target/X86/X86InstrInfo.cpp
+641-203 files

LLVM/project 0a510fc — lld/ELF SyntheticSections.cpp

by Fangrui Song via GitHub on ⎇
[ELF] Parallelize .eh_frame writing. NFC (#235391)

EhFrameSection::writeTo copies CIE/FDE and applies relocations on one
thread, leaving a long single-threaded tail in "Write sections".
Parallelize them, saving ~24ms when linking chromium x86-64.
DeltaFile
+5-4lld/ELF/SyntheticSections.cpp
+5-41 files

LLVM/project 6c2f1e5 — lld/ELF Relocations.cpp

by Fangrui Song via GitHub on ⎇
[ELF] Scan .eh_frame relocations first. NFC (#235389)

.eh_frame is usually the largest item, so one thread scans it while the
others are idle. Hand it out first.
DeltaFile
+5-4lld/ELF/Relocations.cpp
+5-41 files

LLVM/project a4b66d6 — lldb/source/Symbol Symbol.cpp, lldb/unittests/Target ReExportedSymbolTest.cpp

by ShengYi Hung (aokblast) on ⎇
[LLDB] Skip Undef Symbol when resolving ReExportedSymbol

An undef symbol cannot be resolved. Skip it so that a symbol needs no
Resolve can pass. Without this, a symbol that needs no ReExport resolver
can choose the undef symbol incorrectly.

Assisted-by:    Claude # Test
DeltaFile
+56-0lldb/unittests/Target/ReExportedSymbolTest.cpp
+2-0lldb/source/Symbol/Symbol.cpp
+58-02 files

LLVM/project 0b6b6ed — llvm/include/llvm/Support Allocator.h

by Fangrui Song via GitHub on ⎇
[Allocator] Cap MinAlign at alignof(max_align_t) (#235373)

alignof(std::max_align_t) is 4 on NetBSD/i386, whose <stddef.h> defines
max_align_t as a union of void *, long double, and long long.

Fix #230782
DeltaFile
+1-1llvm/include/llvm/Support/Allocator.h
+1-11 files

LLVM/project 9460110 — llvm/lib/Target/RISCV RISCVISelLowering.h RISCVISelLowering.cpp, llvm/test/Transforms/CodeGenPrepare/RISCV dont-sink-vector-compare.ll

by Luke Lau via GitHub on ⎇
[RISCV] Return true for vector registers in hasMultipleConditionRegisters (#234876)
DeltaFile
+59-0llvm/test/Transforms/CodeGenPrepare/RISCV/dont-sink-vector-compare.ll
+4-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-0llvm/lib/Target/RISCV/RISCVISelLowering.h
+65-03 files

LLVM/project 6636b41 — llvm/lib/Target/BPF BPFMISimplifyPatchable.cpp BTFDebug.cpp, llvm/test/CodeGen/BPF/CORE reloc-carrier-punctuation.ll offset-reloc-subarray.ll

by Tamir Duberstein via GitHub on ⎇
[BPF] Disambiguate CO-RE relocation globals (#234252)

The BPF backend encodes the relocation kind, local value and access path
in a global name. Type names such as `S<ns::Arg$>` can contain both
delimiters. Decode the fixed suffix from the right in instruction
folding and BTF emission. This fixes the compiler crash reported in
#233947.

Within a module, different debug types can produce the same name. A
pointer access and a 32-bit field-offset query can also have the same
name with different load types. Reuse an external relocation global only
when its debug root and load type match. Put any discriminator before
the suffix so both consumers read the original relocation.

Assisted-by: OpenAI Codex
DeltaFile
+185-225llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
+72-0llvm/test/CodeGen/BPF/CORE/reloc-carrier-identity.ll
+48-0llvm/test/CodeGen/BPF/CORE/offset-reloc-subarray.ll
+40-0llvm/test/CodeGen/BPF/CORE/reloc-carrier-punctuation.ll
+5-15llvm/lib/Target/BPF/BTFDebug.cpp
+2-8llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
+352-2481 files not shown
+361-2487 files

LLVM/project fd41135 — libunwind/src UnwindRegistersSave.S UnwindRegistersRestore.S, libunwind/test x86_64_getcontext_preserves_rbx.pass.cpp x86_64_resume_extended_registers.pass.cpp

by Minsoo Choo via GitHub on ⎇
[libunwind] Support extended amd64 segment registers (#229176)

Raise the amd64 DWARF register limit to 59 and add RFLAGS, all six
segment selectors, FS.base, and GS.base to the register model. Capture
the extended state and restore it when resuming, using sigreturn() on
FreeBSD to restore selectors and bases together. Pack the state into the
existing context buffers without changing their public sizes or the
Windows XMM offsets.

Add tests for register access, signal-frame CFI recovery, register
bounds, and resume behavior.

Assisted-by: GPT
DeltaFile
+163-0libunwind/test/x86_64_extended_registers.pass.cpp
+150-0libunwind/test/x86_64_resume_extended_registers.pass.cpp
+92-7libunwind/src/Registers.hpp
+80-0libunwind/test/x86_64_getcontext_preserves_rbx.pass.cpp
+62-7libunwind/src/UnwindRegistersRestore.S
+57-5libunwind/src/UnwindRegistersSave.S
+604-197 files not shown
+772-2213 files

LLVM/project c8b043a — utils/bazel/llvm-project-overlay/lldb/source/Plugins plugin_config.bzl BUILD.bazel

by Lexi Bromfield via GitHub on ⎇
[lldb][bazel] Add targets for the remaining unconditional plugins (#235325)

CMake builds these plugins on every host, but the Bazel overlay had no
targets for them:

- PluginABILoongArch
- PluginDynamicLoaderFreeBSDKernel
- PluginPlatformAIX
- PluginPlatformFreeBSD
- PluginPlatformNetBSD
- PluginPlatformOpenBSD
- PluginTypeSystemClike

I also added these to the DEFAULT_PLUGINS list.

For now, I'm still leaving out plugins that CMake only builds with an
optional dependency or on a specific host:

- ProcessFreeBSDKernelCore (FreeBSD hosts, libkvm)

    [8 lines not shown]
DeltaFile
+124-0utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
+7-0utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl
+131-02 files

LLVM/project 5e767e5 — clang/www c_dr_status.html, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-llvm.amdgcn.image.sample.a16.ll legalize-llvm.amdgcn.image.dim.a16.ll

by Luke Lau via GitHub on ⎇
Merge branch 'main' into users/lukel97/riscv/dont-sink-vector-compares
DeltaFile
+2,112-452llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+1,740-729llvm/test/CodeGen/X86/bfloat.ll
+1,222-1,222llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+1,060-1,060llvm/test/Transforms/Util/DeclareRuntimeLibcalls/aarch64.ll
+1,572-467clang/www/c_dr_status.html
+945-983llvm/test/CodeGen/X86/atomic-load-store.ll
+8,651-4,9131,488 files not shown
+71,839-35,1291,494 files

LLVM/project 57f5cdf — llvm/lib/Target/AMDGPU GCNFeatures.td AMDGPUFeatures.td, llvm/test/CodeGen/AMDGPU lds-size-gfx9-4-generic.ll

by Chinmay Deshpande via GitHub on ⎇
[AMDGPU] Fix gfx9-4-generic LDS allocation granule (#235163)

`gfx9-4-generic` paired gfx950's 1280-byte allocation granule with
gfx942's 64 KiB LDS capacity.

Use gfx942's 512-byte granule, which matches the capacity. 

Refer to ISA Doc Section 3.6.5

Fixes LCOMPILER-3031.
DeltaFile
+16-4llvm/test/CodeGen/AMDGPU/lds-size-gfx9-4-generic.ll
+1-5llvm/unittests/TargetParser/TargetParserTest.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
+1-1llvm/lib/Target/AMDGPU/GCNFeatures.td
+20-124 files

LLVM/project 3e2f99b — llvm/include/llvm/Analysis MemorySSA.h, llvm/lib/Analysis MemorySSA.cpp

by Florian Hahn via GitHub on ⎇
[MemorySSA] Remove unused functions (NFC) (#235374)

Remove MemoryPhi::unorderedDeleteIncomingValue, upward_defs and
ClobberWalker::const_def_path, which have no callers, together with the
const_def_path_iterator alias only used by const_def_path.
DeltaFile
+0-12llvm/include/llvm/Analysis/MemorySSA.h
+0-7llvm/lib/Analysis/MemorySSA.cpp
+0-192 files

LLVM/project 301640d — llvm/lib/Analysis LoopAccessAnalysis.cpp, llvm/test/Analysis/LoopAccessAnalysis zero-sized-access-type.ll

by Florian Hahn via GitHub on ⎇
[LAA] Avoid division by zero for zero-sized access types. (#235372)

Zero-sized access types lead to divide-by-zero in getStrideFromAddRec.

Bail out if that would be the case.
DeltaFile
+47-0llvm/test/Analysis/LoopAccessAnalysis/zero-sized-access-type.ll
+3-0llvm/lib/Analysis/LoopAccessAnalysis.cpp
+50-02 files

LLVM/project 4d7292e — libunwind/include __libunwind_config.h, libunwind/src UnwindCursor.hpp

by Minsoo Choo via GitHub on ⎇
[libunwind] Unwind through AArch64 FreeBSD signal trampolines (#235065)

Retried from https://reviews.llvm.org/D155066.

Recognize signal trampolines using KERN_PROC_SIGTRAMP when unwind
metadata is unavailable. Restore the interrupted PC, LR, SP, general
registers, and valid floating-point registers.

Add coverage for unwinding out of an interrupted leaf function on both
regular and alternate signal stacks.

Assisted-by: GPT
DeltaFile
+103-0libunwind/test/aarch64_freebsd_signal_unwind.pass.cpp
+76-1libunwind/src/UnwindCursor.hpp
+3-0libunwind/include/__libunwind_config.h
+2-0libunwind/test/aarch64_za_unwind.pass.cpp
+184-14 files

LLVM/project 36985ee — libc/test/src/math/exhaustive cos.wc sin.wc, llvm/lib/Support UnicodeNameToCodepointGenerated.cpp

by hulxv via GitHub on ⎇
Merge branch 'main' into users/hulxv/ci/compiler-rt/check-libc-freestanding
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+98,508-116,745llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+30,284-36,334llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+32,750-17,381llvm/test/CodeGen/AMDGPU/frem.ll
+23,347-23,371llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+2,366,152-193,83136,260 files not shown
+5,365,981-1,645,05936,266 files

LLVM/project 7e2f1c5 — llvm/test/Analysis/CostModel/RISCV arith-int.ll clmul.ll, llvm/test/Transforms/LoopVectorize/RISCV early-exit-live-out.ll

by Aiden Grossman via GitHub on ⎇
[RISCV][TTI] Multiplication is high-cost without M extension (#235363)

This fixes a regression exposed in a future patch that came up when
working on LSR where suddenly we were emitting a multiplication libcall
in a test that didn't specify having the M extension because LSR thought
it was cheap.

I don't think lacking an M extension is common, but this is a pretty
small change and probably helps people compiling code to RISCV on really
small/cheap cores.

Assisted-by: LLM
DeltaFile
+96-96llvm/test/Analysis/CostModel/RISCV/mulh.ll
+13-15llvm/test/Transforms/SLPVectorizer/RISCV/long-gep-chains.ll
+5-8llvm/test/Transforms/SLPVectorizer/RISCV/gep-mixed-index-types.ll
+5-5llvm/test/Analysis/CostModel/RISCV/clmul.ll
+3-3llvm/test/Analysis/CostModel/RISCV/arith-int.ll
+4-2llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
+126-1293 files not shown
+133-1339 files

LLVM/project 301aae6 — lldb/unittests CMakeLists.txt

by aokblast (aokblast) via GitHub on ⎇
[LLDB] Exclude exposed exe symbols from tests (#228645)

Same as what we have for normal lldb installation. A executable may
creates a copy of a symbol if it links to the archive. Exclude archive
symbols out from the exe itself.
DeltaFile
+4-0lldb/unittests/CMakeLists.txt
+4-01 files

LLVM/project 356b4eb — lldb/source/Host/freebsd Host.cpp

by aokblast (aokblast) via GitHub on ⎇
[LLDB][FreeBSD] Fix file not exists detection (#235358)

A process can outlive the exact running binary inside. As a result, a
file fails to query should set unknow by default.
DeltaFile
+7-10lldb/source/Host/freebsd/Host.cpp
+7-101 files

LLVM/project 95b1868 — llvm/lib/CodeGen/SelectionDAG SDNodeInfo.cpp, llvm/lib/Target/M68k M68kSelectionDAGInfo.cpp

by Craig Topper via GitHub on ⎇
Reapply "[SelectionDAG] Implement SDTCisSameAs in verifyNode." (#235357)

This relands a98c5c2b79b6afe17e831f4962f7f1fa27e9ad86 with a waiver for
M68k
DeltaFile
+10-1llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp
+3-0llvm/lib/Target/M68k/M68kSelectionDAGInfo.cpp
+13-12 files

LLVM/project 8c67eee — llvm/lib/Target/M68k M68kISelDAGToDAG.cpp M68kInstrArithmetic.td

by Craig Topper on ⎇
[M68k] Remove dead ADDC/ADDE/SUBC/SUBE isel patterns. NFC

These nodes are custom lowered and can't make it to isel.

Assisted-by: Claude
DeltaFile
+94-120llvm/lib/Target/M68k/M68kInstrArithmetic.td
+0-1llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+94-1212 files

LLVM/project b6977b2 — llvm/lib/Target/AVR AVRExpandPseudoInsts.cpp, llvm/test/CodeGen/AVR std-ldd-tiny.ll

by Petar Jovanovic on ⎇
[AVR] Fix byte spills and stack args on AVRTiny

AVRTiny cores have no load/store with displacement, yet 8-bit spills,
reloads and stack arguments in functions without a reserved call frame
were still emitted as STDPtrQRr/LDDRdPtrQ. llc then aborted in the
AsmPrinter, so any function that spilled a byte failed to compile, also
with the default register allocator and at -O0, and builds without
assertions silently emitted std/ldd instead.

Expand both instructions on AVRTiny the same way as their 16-bit
counterparts: a plain st/ld when the displacement is zero, as it always
is for spill slots, and pointer adjustments around it otherwise.
DeltaFile
+222-0llvm/test/CodeGen/AVR/std-ldd-tiny.ll
+74-0llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+44-0llvm/test/CodeGen/AVR/pseudo/STDPtrQRr.mir
+41-0llvm/test/CodeGen/AVR/pseudo/LDDRdPtrQ.mir
+381-04 files