LLVM/project c94c7ccflang/lib/Optimizer/OpenMP MapInfoFinalization.cpp, flang/test/Lower/OpenMP defaultmap.f90

[Flang][OpenMP] Remove present modifier application on descriptor (#211856)

This was a minor change upstreamed in the original PR:
https://github.com/llvm/llvm-project/pull/208133

However, it is a modification that needs a little more thought from a
specification perspective before it is rolled out, there's a number of
code bases that depend on the presence modifier being applied only to
the underlying data. However, this leads to inconsistencies when a user
makes use of any reference semantic modifiers when mapping as they
SHOULD be allowed to specify present applying to the descriptor. So, we
need to work out what the correct defualt behaviour is, and regardless
of the default support a user intentionally specifying presence
application on a descriptor via reference semantics.

For now, we will revert to previous state.
DeltaFile
+1-2flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
+1-1flang/test/Lower/OpenMP/defaultmap.f90
+2-32 files

LLVM/project 693d0a9llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/lib/Transforms/Vectorize/SLPVectorizer SLPCompatibilityAnalysis.h SLPCompatibilityAnalysis.cpp

[SLP][modularisation][NFC] Extract InstructionsState (2/3) (#211461)

Move the InstructionsState class out of SLPVectorizer.cpp into the
existing private module SLPVectorizer/SLPCompatibilityAnalysis.{h,cpp}.
The class declaration (with trivial accessors) lives in the header; the
non-trivial method bodies are defined out-of-line in the .cpp:

  isSameOperation
  getMatchingMainOpOrAltOp
  isMulDivLikeOp
  isAddSubLikeOp
  isCopyableElement
  isExpandedBinOp
  isExpandedOperand
  isNonSchedulable

Part of the effort to modularize SLPVectorizer.cpp. See the RFC:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
DeltaFile
+0-251llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+157-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.cpp
+116-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.h
+273-2513 files

LLVM/project 7ded638libcxx/include optional, libcxx/include/__optional make_optional.h common.h

[libc++] Granularize `<optional>` (#206644)

Certain headers require `optional<T&>`, so it may be beneficial to split
out `optional<T>` and `optional<T&>`. This can allow consumers to only
bring in the `optional` flavour it needs..

- Parcel out the respective pieces into their own header.
- Certain sources rely on transitive includes brought in by
`<optional>`, so they're kept there for now, and only tests have been
fixed.

---------

Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
DeltaFile
+13-1,479libcxx/include/optional
+757-0libcxx/include/__optional/optional.h
+357-0libcxx/include/__optional/optional_ref.h
+349-0libcxx/include/__optional/comparison.h
+97-0libcxx/include/__optional/common.h
+91-0libcxx/include/__optional/make_optional.h
+1,664-1,47912 files not shown
+1,903-1,50518 files

LLVM/project a01f8c8libcxx/include variant

Speed up compilation of typical invocations of std::visit(std::variant<...>) for up to 11 types (#164196)

Similar to https://reviews.llvm.org/D90168 which was reverted (https://github.com/llvm/llvm-project/issues/62648#issuecomment-1832315651), but uses `switch` statements rather than function pointer tables.
DeltaFile
+94-7libcxx/include/variant
+94-71 files

LLVM/project bdddd3ellvm/lib/Target/X86/AsmParser X86AsmParser.cpp, llvm/test/MC/X86 intel-syntax-data32-16.s

[X86] Apply the data32 mode switch in the Intel matcher (#212417)

In .code16, `data32 push 8` in Intel syntax assembled as `pushw $8` with
the 66 prefix dropped, and `data32 push 0x1234` truncated the immediate
to 16 bits. AT&T syntax gets both right.

`ForcedDataPrefix` is set while parsing either syntax, but only
`matchAndEmitATTInstruction` switched mode on it, so the Intel path took
the operand size from the mode and never saw the prefix.

Do the same switch in `matchAndEmitIntelInstruction`. The mode has to go
back to 16-bit before the instruction is emitted, otherwise the 32-bit
form is emitted without its 66 prefix. That function has several error
returns partway through matching, so a scope guard covers those.

Encodings after the change match both AT&T syntax and GNU as:

```
data32 push 8       [0x6a,0x08]      -> [0x66,0x6a,0x08]

    [3 lines not shown]
DeltaFile
+40-0llvm/test/MC/X86/intel-syntax-data32-16.s
+16-0llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+56-02 files

LLVM/project af1dbbbllvm/lib/Transforms/Vectorize/SandboxVectorizer DependencyGraph.cpp, llvm/unittests/Transforms/Vectorize/SandboxVectorizer DependencyGraphTest.cpp

[SandboxIR] Fix notifyEraseInstr to skip scheduled neighbors

Guard both loops with !PredN->scheduled() / !SuccN->scheduled() so
scheduled neighbors are left untouched, and add a unit test that erases
a node with one scheduled and one unscheduled predecessor to cover the
fix.
DeltaFile
+43-0llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
+4-2llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
+47-22 files

LLVM/project dc57785clang/lib/CIR/CodeGen CIRGenBuiltinRISCV.cpp, clang/test/CIR/CodeGenBuiltins/RISCV riscv-xandesperf-rv32.c riscv-xandesperf-rv64.c

[CIR][RISCV] Support XAndesPerf builtins (#211490)
DeltaFile
+43-0clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv32.c
+43-0clang/test/CIR/CodeGenBuiltins/RISCV/riscv-xandesperf-rv64.c
+16-4clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+102-43 files

LLVM/project e77eb2aclang/docs LanguageExtensions.md, clang/lib/Sema SemaDecl.cpp

[Clang][AIX] Restrict -mloadtime-comment-vars to file/namespace scope

Support only file- and namespace-scope variables. Name-matched static
data members, variable template specializations (explicit ones
included), and function-local statics are now diagnosed with
-Wloadtime-comment-var instead of being silently ignored. Implicit
instantiations are diagnosed via the template-instantiation path, once
per instantiating TU. Automatic locals have no symbol to match and
remain out of scope.
DeltaFile
+0-270clang/test/CodeGen/PowerPC/loadtime-comment-vars-cxx.cpp
+234-0clang/test/CodeGen/PowerPC/loadtime-comment-vars.cpp
+117-0clang/test/Sema/loadtime-comment-vars.cpp
+79-26clang/test/CodeGen/PowerPC/loadtime-comment-vars.c
+50-20clang/lib/Sema/SemaDecl.cpp
+30-14clang/docs/LanguageExtensions.md
+510-3307 files not shown
+584-34613 files

LLVM/project 44a1133lldb/examples/python/templates scripted_string_summary.py, lldb/include/lldb/DataFormatters TypeSummary.h

[lldb/script] Add class-based summary providers via ScriptedStringSummaryInterface (#210469)
DeltaFile
+75-0lldb/source/DataFormatters/TypeSummary.cpp
+66-6lldb/source/Commands/CommandObjectType.cpp
+61-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStringSummaryPythonInterface.cpp
+53-1lldb/include/lldb/DataFormatters/TypeSummary.h
+48-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStringSummaryPythonInterface.h
+40-0lldb/examples/python/templates/scripted_string_summary.py
+343-715 files not shown
+442-821 files

LLVM/project 1a5fc1cmlir/include/mlir/Dialect/Linalg Passes.td, mlir/lib/Dialect/Linalg/Transforms FoldIntoElementwise.cpp

[mlir] [linalg] Fold broadcast/transpose into linalg.generic (#212415)

Currently we are able to fold broadcast/transpose into
linalg.elementwise. This patch extends the ability to fold
broadcast/transpose into linalg.generic.

For example,

```
  %empty = tensor.empty() : tensor<8x16xf32>
  %broadcasted = linalg.broadcast ins(%A : tensor<8xf32>) outs(%empty : tensor<8x16xf32>) dimensions = [1]
  %result = linalg.generic {
    indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
                     affine_map<(d0, d1) -> (d0, d1)>],
    iterator_types = ["parallel", "parallel"]
  } ins(%broadcasted : tensor<8x16xf32>) outs(%B : tensor<8x16xf32>) {
  ^bb0(%in: f32, %out: f32):
    %v = arith.addf %in, %in : f32
    linalg.yield %v : f32

    [19 lines not shown]
DeltaFile
+165-0mlir/test/Dialect/Linalg/elementwise/fold.mlir
+28-10mlir/lib/Dialect/Linalg/Transforms/FoldIntoElementwise.cpp
+6-6mlir/include/mlir/Dialect/Linalg/Passes.td
+199-163 files

LLVM/project 5857e09llvm/unittests/Frontend HLSLSemanticSignatureMetadataTest.cpp

[NFC][HLSL] Fix msan errors in tests (#212901)

Some of the tests were not initializing all the fields prior to
generating metadata, this caused a read of uninitialized memory and
caused the sanitizer to fail.

Assisted by: Claude Opus 5

Caught here: https://lab.llvm.org/buildbot/#/builders/94/builds/19767
DeltaFile
+8-0llvm/unittests/Frontend/HLSLSemanticSignatureMetadataTest.cpp
+8-01 files

LLVM/project e7b04c1libc/include dirent.yaml, libc/include/llvm-libc-macros dirent-macros.h

[libc] Modernize and extend dirent.h header. (#212902)

Extend the `<dirent.h>` header with macro and types specified in recent
POSIX.1-2024:
* Add `posix_dent` structure, which has more fields than `dirent`, that
are actually used in practice. This struct would be identical to
`dirent` that we have on Linux
* Add `reclen_t` type for `d_reclen` field.
* Add macro `DT_BLK` and friends

Also, extend the tests to verify the values of `d_type` field, now that
we have the proper macro defined.

Assisted by: Gemini, human-verified
DeltaFile
+35-0libc/include/llvm-libc-types/struct_posix_dent.h
+26-0libc/include/llvm-libc-macros/linux/dirent-macros.h
+21-0libc/include/dirent.yaml
+21-0libc/include/llvm-libc-macros/dirent-macros.h
+19-0libc/include/llvm-libc-types/reclen_t.h
+12-4libc/test/src/dirent/dirent_test.cpp
+134-45 files not shown
+156-611 files

LLVM/project 3889cccllvm/lib/MC/MCParser MasmParser.cpp, llvm/test/tools/llvm-ml textequ_expansion.asm

[llvm-ml] make TEXTEQU directive not to eagerly expand macros in arguments (#209526)

We observed a crash in `TEXTEQU` that pastes two macros into one.

```masm
.data
part1 TEXTEQU <1>
part2 TEXTEQU <0>
joined TEXTEQU part1, part2 ; crash
```

`part1` is immediately rewritten into `1` as integer, which is rejected
by `TEXTEQU` parser. We need to keep `part1` as identifier for `TEXTEQU`
to pick up later.
DeltaFile
+71-73llvm/lib/MC/MCParser/MasmParser.cpp
+92-0llvm/test/tools/llvm-ml/textequ_expansion.asm
+163-732 files

LLVM/project e82a934llvm/docs/_static custom.css

[docs] de-highlight code snippet errors in dark mode (#212894)

Apply https://github.com/llvm/llvm-project/pull/212698 to dark mode as
well as light mode.
DeltaFile
+1-0llvm/docs/_static/custom.css
+1-01 files

LLVM/project 5e0a2aallvm/test/CodeGen/X86 win64-eh-unwindv2-errors.mir

[X86] Make WinEH crash test reliable under ASan (#212820)

The WinEH unwind `v2 error` test uses `not --crash` for malformed MIR
inputs.
In AddressSanitizer builds, the default `abort_on_error=0` can prevent
the
expected fatal error from being reported as a crash, causing FileCheck
to
  receive no diagnostic output.

Set `ASAN_OPTIONS=abort_on_error=1` for the expected-crash invocations
in
  `win64-eh-unwindv2-errors.mir`.

  ## Testing

  - ASan build focused test passes.
  - Non-ASan build focused test passes.
  - Five additional serial ASan reruns pass.

    [4 lines not shown]
DeltaFile
+28-28llvm/test/CodeGen/X86/win64-eh-unwindv2-errors.mir
+28-281 files

LLVM/project 9c8bba8llvm/lib/Transforms/Vectorize VPRecipeBuilder.h

Revert remaining change in VPRecipeBuilder.h
DeltaFile
+5-5llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+5-51 files

LLVM/project 3ca8b6eclang/lib/CIR/CodeGen CIRGenBuiltinNVPTX.cpp, clang/test/CIR/CodeGenCUDA builtins-nvvm-atomic.cu

[CIR][CUDA] Add support for NVVM xchg builtins (#211815)

Adds codegen support for the scoped and unscoped NVVM atomic exchange
builtins:
`atom_xchg,` `atom_cta_xchg,` and `atom_sys_xchg.`

These are lowered to the corresponding CIR `cir.atomic.xchg` operations
and subsequently lowered to LLVM `atomicrmw xchg` instructions.
DeltaFile
+72-0clang/test/CIR/CodeGenCUDA/builtins-nvvm-atomic.cu
+16-12clang/lib/CIR/CodeGen/CIRGenBuiltinNVPTX.cpp
+88-122 files

LLVM/project d998634clang/lib/Driver/ToolChains Linux.cpp, clang/test/Driver aarch64-ptrauth.c

[PAC][clang] Enable `-fptrauth-elf-got` as part of pauthtest (#212446)
DeltaFile
+3-3clang/test/Driver/aarch64-ptrauth.c
+4-0clang/lib/Driver/ToolChains/Linux.cpp
+7-32 files

LLVM/project 397743fclang/lib/CIR/CodeGen CIRGenStmt.cpp, clang/test/CIR/CodeGen complex.cpp

[CIR] Implement complex rvalues NYI (#211645)

emitReturnOfRValue had an NYI for _Complex types, so returning one as an
Rvalue (see example of a lambda invoker) would NYI. Since the logic to
the store is already handled in the lower-to-LLVM, this ended up being a
pretty trivial patch.

Note; There are some differences in how this lowers, because our calling
convention for the ret is different here, and we maintain the 'complex'
type differently even through LLVM-IR. However, the IR looks to be
equivilent.
DeltaFile
+35-0clang/test/CIR/CodeGen/complex.cpp
+2-1clang/lib/CIR/CodeGen/CIRGenStmt.cpp
+37-12 files

LLVM/project c56ea6dllvm/include/llvm/CodeGen MacroFusion.h, llvm/lib/CodeGen MacroFusion.cpp

[MacroFusion] Add SDep param to predicates(NFC) (#212255)

This patch aims to extend the API for macro fusion predicates with an
additional SDep param which allows each predicate to individually decide
wether a pair should be macro fused based on the kind of dependency
between the 2 instructions.
    
A followup patch https://github.com/llvm/llvm-project/pull/212603
introduces a real user in AArch64.
DeltaFile
+28-14llvm/test/TableGen/MacroFusion.td
+10-9llvm/lib/CodeGen/MacroFusion.cpp
+12-4llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
+9-3llvm/include/llvm/CodeGen/MacroFusion.h
+4-3llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+4-1llvm/lib/Target/X86/X86MacroFusion.cpp
+67-346 files not shown
+88-3912 files

LLVM/project 2815f29clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaHLSL.cpp

[HLSL] Add sema for use of samplers and gathers on textures of doubles and ints (#212613)

Fixes https://github.com/llvm/llvm-project/issues/198882 and
https://github.com/llvm/llvm-project/issues/198883

This PR:
- Implements sema checks to reject the use of samplers and gathers on
textures of doubles.
- Implements sema checks to reject use of samplers on textures of
integers before shader model 6.7

Assisted by: Claude Opus 5
DeltaFile
+102-0clang/lib/Sema/SemaHLSL.cpp
+69-0clang/test/SemaHLSL/Resources/Textures-double-element-type-errors.hlsl
+61-0clang/test/SemaHLSL/Resources/Textures-integer-element-type.hlsl
+5-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+237-04 files

LLVM/project c4dbdfcllvm/utils/gn/secondary/llvm/lib/Frontend/HLSL BUILD.gn, llvm/utils/gn/secondary/llvm/unittests/Frontend BUILD.gn

[gn build] Port 8e564ec0a221 (#212897)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/lib/Frontend/HLSL/BUILD.gn
+2-02 files

LLVM/project cd1db26llvm/utils/gn/secondary/clang/unittests/CIR BUILD.gn

[gn build] Port 13834ee4dc48 (#212896)
DeltaFile
+1-0llvm/utils/gn/secondary/clang/unittests/CIR/BUILD.gn
+1-01 files

LLVM/project a934934flang/include/flang/Optimizer/Dialect/CUF CUFOps.td, flang/lib/Optimizer/Transforms/CUDA CUFAddConstructor.cpp

[flang][cuda] Unify registration under -gpu=mem:unified (#212871)

Always use the cuf operation under -gpu=unified as registration might be
differed to the backend. Add a UnitAttr to distinguish device resident
variable that will not use cudaRegisterHostVar but cudaRegisterVar.
DeltaFile
+34-22flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
+24-22flang/test/Fir/CUDA/cuda-constructor-2.f90
+6-5flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
+64-493 files

LLVM/project 76403adflang/include/flang/Evaluate tools.h, flang/test/Lower/CUDA cuda-managed-assign.cuf

[flang][cuda] Keep data transfers for allocatable assignments with device data (#212855)

An assignment to a whole allocatable was lowered as a host assignment to
keep reallocation semantics, without checking the memory kind, so a
device allocatable assigned from a managed array wrote device memory
from the host and segfaulted.

Keep the transfer when either side is device or constant data. CUDA
Fortran Programming Guide 3.4.1 makes an assignment between managed and
device data a copy in both directions, with no exception for an
allocatable left-hand side.
DeltaFile
+39-22flang/include/flang/Evaluate/tools.h
+17-0flang/test/Lower/CUDA/cuda-managed-assign.cuf
+56-222 files

LLVM/project 0d1c3c0clang/include/clang/CIR/Dialect/IR CIRTypeConstraints.td CIROps.td, clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

[CIR] Allow boolean operands in cir.cmp (#206846)

GROMACS uses scoped enums with a boolean underlying type as type-safe
flags (`enum class EmulateGpuNonbonded : bool`), and compares them with
`==` / `!=` / `<`. A scoped enum is not integer-promoted before the
comparison, so the operand reaches `cir.cmp` as a `!cir.bool` (CIR
already
represents a boolean-underlying enum with `!cir.bool`). The `cir.cmp`
operand constraint `CIR_ComparableType` does not list bool, so module
verification fails before the CIR-to-CIR passes with:

```
'cir.cmp' op operand #0 must be comparable type, but got '!cir.bool'
```

Add bool to `CIR_ComparableType` and let the comparison lowering compare
`!cir.bool` the same way it already compares pointers, as an unsigned
`icmp` (`ult` for `<`), which is what classic CodeGen does with these as
`i1`. Plain `bool` comparisons are unchanged, since they still carry the

    [13 lines not shown]
DeltaFile
+95-5clang/test/CIR/CodeGen/enum-bool.cpp
+68-0clang/test/CIR/IR/cmp.cir
+5-12clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+3-2clang/include/clang/CIR/Dialect/IR/CIROps.td
+2-2clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
+173-215 files

LLVM/project b0541c3clang/include/clang/StaticAnalyzer/Core/PathSensitive CoreEngine.h ExprEngine.h, clang/lib/StaticAnalyzer/Checkers AnalyzerStatsChecker.cpp

[NFC][analyzer] Remove BlockEdge parameter of processCFGBlockEntrance (#212804)

As a side effect of my previous refactoring efforts, the method
`ExprEngine::processCFGBlockEntrance` had two very similar parameters: a
`BlockEdge` and a `BlockEntrance` instance.

These are both subclasses of `ProgramPoint`, stored the same data (the
`BlockEntrance` was initialized with data taken from the `BlockEdge`
just before the call) and the `BlockEdge` was almost completely unused
within `processCFGBlockEntrance`.

The only reason for having the `BlockEdge` was that it was stored in the
debug statistic table `blocksExhausted`; so this commit transitions that
simple debug code to use `BlockEntrance` instances instead (which is
also perfectly sufficient for its goals). This allows the removal of the
redundant argument of `processCFGBlockEntrance`.

This prepares the ground for further cleanup in this method.
DeltaFile
+2-6clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+2-2clang/lib/StaticAnalyzer/Checkers/AnalyzerStatsChecker.cpp
+2-2clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
+1-1clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
+1-1clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h
+8-125 files

LLVM/project 64dfcdbclang/include/clang/CIR/Dialect/IR CIROps.td, clang/test/CIR/IR fenv.cir

[CIR] Add fenv attribute to more builtins (#212880)

This adds the #cir.fenv attribute to the CIR_UnaryFPToIntBuiltinOp and
CIR_TernaryFPToFPBuiltinOp base classes, and through them to the
cir.lround, cir.llround, cir.lrint, cir.llrint, and cir.fma operations.

This attribute is still missing from various cast and compare
operations. Those will be added in a follow-up change.

Assisted-by: Cursor / various models
DeltaFile
+22-6clang/include/clang/CIR/Dialect/IR/CIROps.td
+24-0clang/test/CIR/IR/fenv.cir
+20-1clang/unittests/CIR/FenvOpTest.cpp
+66-73 files

LLVM/project ade1287llvm/lib/DWARFLinker/Classic DWARFLinker.cpp, llvm/test/tools/dsymutil/X86 keep-enumerators.test

[DWARFLinker] Keep DW_TAG_enumerator children of a live enumeration_type (#212849)

Swift allows functions inside enums:

  enum Foo: Int {
    case bar = 0

    func baz() { ... }
    }

  DW_TAG_enumeration_type  "Foo"
    DW_TAG_enumerator        "bar"
    DW_TAG_subprogram        "baz"  DW_AT_declaration
  ...
  DW_TAG_subprogram  DW_AT_low_pc(...)  DW_AT_specification -> "baz"

dieNeedsChildrenToBeMeaningful() did not list DW_TAG_enumeration_type,
so the parent walk skipped the enum's children.


    [2 lines not shown]
DeltaFile
+160-0llvm/test/tools/dsymutil/X86/keep-enumerators.test
+1-0llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
+161-02 files

LLVM/project 99340f9llvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp

[AMDGPU] Rename packed 64-bit features to include SingleSGPR. NFCI.
DeltaFile
+9-9llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+12-6llvm/lib/Target/AMDGPU/AMDGPU.td
+8-8llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+4-4llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+2-2llvm/lib/Target/AMDGPU/SIInstructions.td
+2-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+37-313 files not shown
+43-339 files