LLVM/project e0e0b57llvm/include/llvm/CodeGen ValueTypes.h, llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp

Revert "[Codegen] Replace any_of with is_contained. NFC (#212289)" (#212794)

This reverts commit 52f6c88c2c1b6f0c10b9c8fb09ec35e147c593e3 due to
errors in the C++20 builder.

It does not revert the followup from #212711.
DeltaFile
+7-6llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+0-2llvm/include/llvm/CodeGen/ValueTypes.h
+1-1llvm/lib/Transforms/Utils/LoopUnroll.cpp
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+1-1llvm/lib/Target/NVPTX/NVPTXUtilities.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+11-126 files

LLVM/project 421d2e8llvm/include/llvm/Frontend/OpenMP ConstructDecompositionT.h

[OpenMP] Fix ambiguous namespace lookup with delayed template parsing (#212720)

Running `check-llvm` on Windows fails while compiling LLVMFrontendTests
with the following error:

  error: reference to 'detail' is ambiguous

Clang enables delayed template parsing by default when targeting the
MSVC ABI on Windows. When ConstructDecompositionT is instantiated after
a using-directive for `llvm::omp`, both `::detail` and
`llvm::omp::detail` are
visible, making `detail::find_unique` ambiguous.

Explicitly qualify find_unique with the global namespace. This fixes
check-llvm on Windows and other environments using
-fdelayed-template-parsing, without changing behavior.
DeltaFile
+1-1llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
+1-11 files

LLVM/project 264f240llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 fmuladd-copyable-mul-part.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+29-27llvm/test/Transforms/SLPVectorizer/X86/fmuladd-copyable-mul-part.ll
+37-9llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+66-362 files

LLVM/project 8d445c6llvm/test/CodeGen/AMDGPU bitop3-shared-operand.ll

[AMDGPU][NFC] Add previously failing bitop3 tests. (#212335)

The following two expressions used to return the wrong truth table for
v_bitop3:

; ((b & T) | T) & ~T, where T = a & c

; U ^ (~U | T), where T = c ^ b and U = (T | a) & T

The fix was implemented in:
https://github.com/llvm/llvm-project/pull/198556

Assisted-by: Cursor (Claude)
DeltaFile
+56-0llvm/test/CodeGen/AMDGPU/bitop3-shared-operand.ll
+56-01 files

LLVM/project f24da9dllvm/lib/Target/RISCV RISCVFrameLowering.cpp, llvm/test/CodeGen/RISCV epilog-crash.ll

[RISC-V] Fix assert after 255162a (#212791)

The iterator passed-in may point to the end of the block which causes an
assertion failure when attempting to inspect the MI it points to. Guard
against this.
DeltaFile
+37-0llvm/test/CodeGen/RISCV/epilog-crash.ll
+2-1llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+39-12 files

LLVM/project 7140530llvm/test/Transforms/SLPVectorizer/X86 fmuladd-copyable-mul-part.ll

[SLP][NFC]Add a test with nother candidate for fmuladd copyables, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/212802
DeltaFile
+155-0llvm/test/Transforms/SLPVectorizer/X86/fmuladd-copyable-mul-part.ll
+155-01 files

LLVM/project 45ef27allvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU pack-half-to-lshl-or.ll

[AMDGPU] Handle True16 high-half 16-bit packing idiom with uniform operand (#211102)

With True16 instructions, the high-half packing idiom from #206058 tries
to `OR` a 16-bit VGPR operand into the high half of the other operand,
but this causes a crash if the other operand is uniform, as this
generates an invalid `$sgpr = COPY $sgpr_hi16`.
DeltaFile
+173-0llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
+2-2llvm/lib/Target/AMDGPU/SIInstructions.td
+175-22 files

LLVM/project e3f24d8llvm/lib/Transforms/Scalar LoopIdiomRecognize.cpp, llvm/test/Transforms/LoopIdiom memmove-ext.ll

[LoopIdiom] Use SCEV for deciding memmove validity (#211274)

When the loop index variable is smaller than the GEP offset size, and is
thus sign or zero extended before being used, then the IR that is
expanded from the SCEV expressions for the load and store locations will
be in a form that means GetPointerBaseWithConstantOffset can't deduce
the base and offset, meaning we can't generate memmove.

Solve this by deciding memmove validity based on the SCEV expressions
instead of the IR that is expanded from them. This means we also need to
insert a check to handle a null base pointer, as that was previously
handled implicitly due to how SCEVExpander expands expressions involving
null pointers.
DeltaFile
+341-0llvm/test/Transforms/LoopIdiom/memmove-ext.ll
+29-25llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
+370-252 files

LLVM/project 312aa8clldb/packages/Python/lldbsuite/test lldbtest.py dotest.py, lldb/packages/Python/lldbsuite/test/builders builder.py

[LLDB] Remove Xcode sdk guessing from Makefile.rules (NFC) (#212378)

This cleanup patch pushes the auto-detection of the `macosx` SDK from
Makefile.rules up into `dotest.py` and unifies it with the existing SDK
handling for other Apple platforms.

Assisted-by: claude
DeltaFile
+0-10lldb/packages/Python/lldbsuite/test/builders/builder.py
+4-4lldb/packages/Python/lldbsuite/test/dotest.py
+4-1lldb/packages/Python/lldbsuite/test/lldbtest.py
+1-2lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+9-174 files

LLVM/project 4fabb43llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AArch64 sve-vls-reduce-bfp.ll sve-vls-reduce-fp.ll

[AArch64][CostModel] Lower wide fixed-length vector reductions cost (#211824)

When vscale is known > 1, SVE will be used to perform most reductions.
This should be reflected in the cost model.
DeltaFile
+290-0llvm/test/Analysis/CostModel/AArch64/sve-vls-reduce-int.ll
+154-0llvm/test/Analysis/CostModel/AArch64/sve-vls-reduce-fp.ll
+116-0llvm/test/Analysis/CostModel/AArch64/sve-vls-reduce-bfp.ll
+4-3llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+564-34 files

LLVM/project be76618lldb/source/Core IOHandler.cpp

[lldb][Windows] Check for EOF before the ctrl-c retry in GetLine (#212745)

On Windows `lldb --repl` can hang forever instead of exiting at EOF.

`IOHandlerEditline::GetLine` checks `GetLastError() ==
ERROR_OPERATION_ABORTED` and does a `continue` before checking `feof`.
However `fgets` is a CRT function and does not set the Win32 last error
value, so the `GetLastError` read is not the expected error. When it
happens to be `ERROR_OPERATION_ABORTED` (995) the loop never reaches the
EOF check.

This reorders the checks so EOF wins unconditionally, and adds
`clearerr` before the ctrl-c retry (a real interrupt leaves the error
flag set, which would fail the next `fgets`). ctrl-c handling is
otherwise unchanged.

rdar://183335061
DeltaFile
+16-15lldb/source/Core/IOHandler.cpp
+16-151 files

LLVM/project 9aae5cfllvm/lib/Target/AMDGPU AMDGPU.td, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

AMDGPU: Remove xnack and sramecc subtarget features

Now that these are controlled by module flags, the subtarget
features were just used for assembler and disassembler controls.
Now that the assembler and disassembler can infer these from
the e_flags and target directives, they are no longer necessary.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+26-70llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+38-24llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
+44-14llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
+29-8llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+16-12llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
+2-24llvm/lib/Target/AMDGPU/AMDGPU.td
+155-15221 files not shown
+257-22427 files

LLVM/project 705aa2allvm/lib/Transforms/Scalar JumpThreading.cpp, llvm/test/Transforms/JumpThreading phi-copy-to-pred.ll dup-cond-br-recursive-phi.ll

[JumpThreading] Materialize PHIs in duplicateCondBranchOnPHIIntoPred (#204859)

In duplicateCondBranchOnPHIIntoPred, updateSSA iteratively updates the
uses of
the instructions of BB (the duplicated block) according to ValueMapping.
For
PHIs, however, the mapping is inconsistent: the keys refer to the values
before
the parallel assignment of the PHIs, while the mapped-to values refer to
the
values after it. E.g.

  BB:
    %arr  = phi [ %ov.0, %PredBB ], ...
    %ov.0 = phi [ %ov.sel, %PredBB ], ...
  --->
    %arr  => %ov.0
    %ov.0 => %ov.sel


    [24 lines not shown]
DeltaFile
+19-10llvm/lib/Transforms/Scalar/JumpThreading.cpp
+29-0llvm/test/Transforms/JumpThreading/dup-cond-br-recursive-phi.ll
+23-0llvm/test/Transforms/JumpThreading/phi-copy-to-pred.ll
+71-103 files

LLVM/project 1c1a067llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-merge-values.mir fp-int-conversions.ll

GlobalISel: Fix lowerMergeValues when dst type is float

Lowering is done in the integer domain. Similar to the type
mismatch when dst is a pointer, make a bitcast when dst is float.
DeltaFile
+37-0llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
+28-0llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
+2-0llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+67-03 files

LLVM/project 196b4b6libcxx/include/__algorithm pstl.h, libcxx/include/__pstl backend_fwd.h

[libc++][pstl] Implementation of a parallel std::adjacent_find() based on std::mismatch() (#210604)

This PR implements a parallel `std::adjacent_find()` based on parallel
`std::mismatch`. The implementation reshapes the input range as two ranges
offset by 1 element and asks `std::mismatch` to find the first equal pair.

Part of #99938.
DeltaFile
+134-0libcxx/test/std/algorithms/alg.nonmodifying/alg.adjacent.find/pstl.adjacent_find_pred.pass.cpp
+126-0libcxx/test/std/algorithms/alg.nonmodifying/alg.adjacent.find/pstl.adjacent_find.pass.cpp
+45-0libcxx/include/__pstl/backends/default.h
+25-0libcxx/include/__algorithm/pstl.h
+12-0libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
+7-0libcxx/include/__pstl/backend_fwd.h
+349-02 files not shown
+359-08 files

LLVM/project b60f5e3llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

AMDGPU: Remove xnack and sramecc subtarget features

Now that these are controlled by module flags, the subtarget
features were just used for assembler and disassembler controls.
Now that the assembler and disassembler can infer these from
the e_flags and target directives, they are no longer necessary.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+26-70llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+38-24llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
+44-14llvm/test/MC/AMDGPU/amdgcn_target_directive_from_eflags.s
+29-8llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+16-12llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
+20-6llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+173-13421 files not shown
+259-22527 files

LLVM/project b982bfellvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.h AMDGPUDisassembler.cpp, llvm/test/tools/llvm-objdump/ELF/AMDGPU kd-gfx12.s kd-gfx11.s

AMDGPU: Only disassemble .amdhsa_reserve_xnack_mask on xnack targets

The disassembler unconditionally printed .amdhsa_reserve_xnack_mask when
emitting a kernel descriptor. Targets that do not support xnack have no
xnack mask to reserve, and the assembler streamer already only emits the
directive when the subtarget supports xnack. Match that behavior in the
disassembler so the round-trip is consistent and gfx11/gfx12 descriptors
no longer carry a spurious directive.

As a guard against a malformed binary, if the object's ELF e_flags
erroneously select xnack "on" for a target that does not support xnack,
still print the directive so the invalid state remains visible in the
disassembly rather than being silently dropped.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+55-0llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-xnack-unsupported-eflags.yaml
+10-4llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+0-4llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
+3-0llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+0-2llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx12.s
+68-105 files

LLVM/project 689c9eellvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.h AMDGPUDisassembler.cpp, llvm/test/tools/llvm-objdump/ELF/AMDGPU kd-gfx12.s kd-gfx11.s

AMDGPU: Only disassemble .amdhsa_reserve_xnack_mask on xnack targets

The disassembler unconditionally printed .amdhsa_reserve_xnack_mask when
emitting a kernel descriptor. Targets that do not support xnack have no
xnack mask to reserve, and the assembler streamer already only emits the
directive when the subtarget supports xnack. Match that behavior in the
disassembler so the round-trip is consistent and gfx11/gfx12 descriptors
no longer carry a spurious directive.

As a guard against a malformed binary, if the object's ELF e_flags
erroneously select xnack "on" for a target that does not support xnack,
still print the directive so the invalid state remains visible in the
disassembly rather than being silently dropped.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+55-0llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-xnack-unsupported-eflags.yaml
+10-4llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+0-4llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
+3-0llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+0-2llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx12.s
+68-105 files

LLVM/project 82a4cd7clang/test/OpenMP loop_transform_final_iv.c interchange_codegen.cpp

[OpenMP] Restore loop variable values after loop-tranformation constructs. (#208533)

This patch fixes loop variable finalization for OpenMP 6.0
loop-transformations constructs: `tile`, `stripe`, `reverse`,
`interchange` and `fuse` to comply with spec requirement page 371, lines
19-21. The spec requires that "After the execution of the
loop-transforming construct, the loop-iteration variables of any of its
transformation-affected loops have the values that they would have
without the loop-transforming directive".
DeltaFile
+224-110clang/test/OpenMP/tile_codegen.cpp
+224-110clang/test/OpenMP/stripe_codegen.cpp
+216-66clang/test/OpenMP/fuse_codegen.cpp
+180-85clang/test/OpenMP/reverse_codegen.cpp
+134-45clang/test/OpenMP/interchange_codegen.cpp
+129-0clang/test/OpenMP/loop_transform_final_iv.c
+1,107-4164 files not shown
+1,265-47910 files

LLVM/project e854fb7llvm/utils/gn/secondary/llvm/lib/Transforms/Instrumentation BUILD.gn

[gn build] Port 2f910f66e7e1 (#212782)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Transforms/Instrumentation/BUILD.gn
+1-01 files

LLVM/project 0189195clang/docs ReleaseNotes.md, clang/lib/Parse ParseOpenMP.cpp

[Clang][OpenMP] Fixed an assertion on omp taskloop transparent (#200663)

In
https://github.com/llvm/llvm-project/blob/15bb4a97a798ed43b3966c99d37585651b965e5e/clang/lib/Parse/ParseOpenMP.cpp#L3289-L3295
We missed a check for `WrongDirective` before calling
`ActOnOpenMPTransparentClause`.

This patch adds the missing check.
fix #197162
DeltaFile
+6-0clang/test/SemaOpenMP/gh197162.c
+3-2clang/lib/Parse/ParseOpenMP.cpp
+1-0clang/docs/ReleaseNotes.md
+10-23 files

LLVM/project 2b06cb5llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AMDGPU amdgpu-codegenprepare-idiv.ll neg_ashr64_reduce.ll

[DAGCombine] Freeze after load is scalarized. (#212587)

fixes #211567
DeltaFile
+58-52llvm/test/CodeGen/AMDGPU/sra.ll
+57-0llvm/test/CodeGen/AMDGPU/freeze-scalar-load.ll
+22-20llvm/test/CodeGen/AMDGPU/mul_int24.ll
+4-7llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
+5-5llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+8-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+154-846 files

LLVM/project f2453afllvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp, llvm/test/CodeGen/AMDGPU global_smrd_cfg.ll move-to-valu-addsubu64.ll

[AMDGPU] Improve MemorySSA walking in isClobberedInFunction (#211817)

Consistently call the two argument overload
`MemorySSAWalker::getClobberingMemoryAccess(MemoryAccess,
MemoryLocation)` to get a clobbering def (according to the AliasAnalysis
used by MSSA) before applying the special cases in `isReallyAClobber`.

This has the effect of marking more loads as `amdgpu-noclobber` and
selecting SMEM load instructions for them.

Fixes: ROCM-28492
DeltaFile
+280-288llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+52-9llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+6-3llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+2-2llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
+1-2llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll
+341-3045 files

LLVM/project 82c7b9aclang/docs ClangFormatStyleOptions.rst, clang/include/clang/Format Format.h

[clang-format] Add Natural option for SortIncludes (#210788)

`SortIncludes` currently orders includes lexicographically with the
option to ignore case or extension. This adds another option, `Natural`,
that compares embedded runs of digits as numbers rather than sequences
of characters, matching the "natural sort" behaviour found in most file
managers and tools like `sort` when called with the `-V` option.

**Disclaimer**

AI assistance was used in initial exploration and review but the code is
"hand generated".
DeltaFile
+52-15clang/lib/Format/Format.cpp
+34-0clang/unittests/Format/SortIncludesTest.cpp
+16-12clang/unittests/Format/ConfigParseTest.cpp
+10-1clang/include/clang/Format/Format.h
+10-0clang/docs/ClangFormatStyleOptions.rst
+122-285 files

LLVM/project a463071llvm/lib/LTO LTOModule.cpp, llvm/test/LTO/X86 ifunc.ll

[LTO] Handle GlobalIFunc in LTOModule::parseSymbols (#212515)

Avoids the assert immediately below.

Fixes #45694

rdar://182744700
DeltaFile
+18-0llvm/test/LTO/X86/ifunc.ll
+1-1llvm/lib/LTO/LTOModule.cpp
+19-12 files

LLVM/project 2faa90allvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU fix-sgpr-copies-f16-true16.mir

[AMDGPU] Retain subreg when legalising generic operand (#212636)

When building a `COPY` to legalise a generic operand whose register
class does not match what is expected, the subregister is not retained
in the copy, and is not dropped from the newly created virtual
destination register.
DeltaFile
+35-0llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+3-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+38-22 files

LLVM/project e61b2abllvm/lib/CodeGen/GlobalISel InlineAsmLowering.cpp, llvm/lib/Target/AArch64 AArch64RegisterInfo.cpp AArch64RegisterInfo.td

[AArch64] Remove GPR64arg register class (#212457)

GPR64arg was added in fcbec02ea6fb to describe X0-X7 for the reserved
argument-register check. It is an ABI register set rather than an
allocation constraint and should not be used for register allocation.
Given it has a single use that only cares about the number of registers,
a register class isn't necessary.

This exposes that GlobalISel recomputes the minimal register class when
a matching inline asm input is tied to a fixed physical-register output.
For X2 that class was GPR64arg, getRegistersForValue already asks the
target which class implements the output constraint. Retain that class
and reuse it for the matching input.

Assisted-by: codex
DeltaFile
+9-5llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+3-3llvm/test/TableGen/aarch64-register-info-stats.td
+0-3llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+1-1llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
+1-1llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+14-135 files

LLVM/project 7e1aba7llvm/lib/Target/PowerPC PPCISelLowering.cpp, llvm/test/CodeGen/PowerPC fp-classify-nan.ll

Reland [PowerPC] improve performance on the isNan and !isNan function in case of -ffp-model=strict (#212565)

1. reland the patch https://github.com/llvm/llvm-project/pull/204170
2. and fix the regression caused by above patch.
DeltaFile
+126-0llvm/test/CodeGen/PowerPC/fp-classify-nan.ll
+66-6llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+192-62 files

LLVM/project 7f0e5f9clang/include/clang/Basic Diagnostic.h, clang/include/clang/Sema AnalysisBasedWarnings.h

[clang] Cache the analysis-based warning policy in effect (#212213)

While benchmarking with warnings enabled, I found that
`AnalysisBasedWarnings::getPolicyInEffectAt` runs at the end of every
function body, performing six location-sensitive `isIgnored()` queries.
This overhead comes from #136323 ([compile-time
impact](https://llvm-compile-time-tracker.com/compare.php?from=2a9f77f6bd48d757b2d45aadcb6cf76ef4b4ef32&to=71ce9e26aec00e4af27a69ccfab8ca1773ed7018&stat=instructions:u)).

Since these six diagnostics only depend on the diagnostic state at the
query location and whether it is in a system header or macro, we can
cache the computed policy rather than recomputing it for every function.

The cache flushes when a `#pragma clang diagnostic` changes severities,
and it bypasses active diagnostic suppression mappings.

Compile-time results for this pr:

https://llvm-compile-time-tracker.com/compare.php?from=49de424f45389cb757c3cc8c50daf38d024e2314&to=a61503b54e9568254885777cf89f5ca1586ec99f&stat=instructions%3Au
DeltaFile
+39-5clang/lib/Sema/AnalysisBasedWarnings.cpp
+11-0clang/include/clang/Basic/Diagnostic.h
+7-0clang/include/clang/Sema/AnalysisBasedWarnings.h
+4-0clang/lib/Sema/Sema.cpp
+61-54 files

LLVM/project 13a6fc2third-party/benchmark/src sysinfo.cc

[benchmark] Back port 2b0bff7 from upstream (#212278)

Fix compile error with clang -Werror -Wunused-template
(cherry picked from commit 2b0bff7444a8df460daab2e5af18bce45ca00657)
DeltaFile
+3-2third-party/benchmark/src/sysinfo.cc
+3-21 files