LLVM/project 2ff7096 — offload/libompaccsupport RecordReplay.cpp

[offload] Remove unused variabled confusing CI bot with -Werror
DeltaFile
+0-1offload/libompaccsupport/RecordReplay.cpp
+0-11 files

LLVM/project 813ee29 — openmp/libompd/src omp-icv.cpp, openmp/libompd/test/api_tests test_ompd_get_icv_from_scope.c

[OpenMP][ompd] Fix compare wraparound and improve test

The test checks for an "incomplete" return value, which can only happen
for a thread list, not a single value. This used to work because of the
unsigned int wraparound in the corresponding code check, which
incorrectly yielded the "incomplete" return value.
DeltaFile
+2-2openmp/libompd/src/omp-icv.cpp
+2-1openmp/libompd/test/api_tests/test_ompd_get_icv_from_scope.c
+4-32 files

LLVM/project 90028b8 — llvm/include/llvm/IR LLVMRemarkStreamer.h, llvm/lib/IR LLVMRemarkStreamer.cpp

[LTO] Keep the remarks of every partition with parallel codegen

With ParallelCodeGenParallelismLevel > 1, splitCodeGen compiles each
partition in a fresh LTOLLVMContext. Those contexts have no remark
streamer, so code generation remarks (asm-printer, prolog-epilog,
regalloc, ...) never reach the -pass-remarks-output file.

Add LLVMRemarkBuffer, which streams the remarks of one context into an
in-memory bitstream buffer and later emits them through the serializer
of another context's remark file. splitCodeGen gives each partition a
buffer with the remark settings from lto::Config and, once all
partitions are done, emits them in partition order, so the file does
not depend on thread scheduling. Remarks are copied as they are;
RemarkLinker would sort and deduplicate them and drop the ones without
a debug location.

LTOCodeGenerator now stores its -lto-pass-remarks-* options in its
Config, so llvm-lto -j gets the partition remarks too.


    [4 lines not shown]
DeltaFile
+50-0llvm/test/LTO/Resolution/X86/parallel-codegen-remarks.ll
+34-8llvm/lib/LTO/LTOBackend.cpp
+42-0llvm/lib/IR/LLVMRemarkStreamer.cpp
+32-1llvm/include/llvm/IR/LLVMRemarkStreamer.h
+9-3llvm/tools/llvm-lto2/llvm-lto2.cpp
+9-2llvm/lib/LTO/LTOCodeGenerator.cpp
+176-146 files

LLVM/project 73bebd1 — llvm/lib/Target/AArch64 AArch64InstrInfo.cpp, llvm/test/CodeGen/AArch64 arm64-indexed-vector-ldst.ll sink-and-fold-fp32.mir

[AArch64] Add FP32 loads/stores to address folding tables. (#236457)

These were missing (unlike B/H/D/Q forms, which are already present).
DeltaFile
+194-0llvm/test/CodeGen/AArch64/sink-and-fold-fp32.mir
+34-0llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+3-4llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
+231-43 files

LLVM/project 6b40c28 — llvm/test/CodeGen/AArch64 build-vector-extract.ll aarch64-neon-vector-insert-uaddlv.ll

Update Test Checks
DeltaFile
+644-665llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+169-90llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
+13-17llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
+1-3llvm/test/CodeGen/AArch64/build-vector-extract.ll
+827-7754 files

LLVM/project 9a5c174 — clang/docs/analyzer checkers.md, clang/lib/StaticAnalyzer/Checkers SimpleStreamChecker.cpp

[analyzer] Remove the SimpleStream demo checker from the CSA checkers (#238415)

The `SimpleStreamChecker` is a demo checker that was implemented for the
2012 LLVM Developers' Meeting talk. The checker served as an educational
checker for newcomers, students, etc. to the Clang Static Analyzer.
Since then there has been a lots of improvements within CSA and the
`SimpleStreamChecker` lost its purpose because there are other more
modern checkers that are great source for newcomers to learn the
fundamentals. By removing the checker users do not lose anything since
the `StreamChecker` already covers what `SimpleStreamChecker` has
covered.

Discussion about the removal of this checker started in
https://github.com/llvm/llvm-project/pull/230288
DeltaFile
+0-223clang/lib/StaticAnalyzer/Checkers/SimpleStreamChecker.cpp
+0-96clang/test/Analysis/simple-stream-checks.c
+0-24clang/docs/analyzer/checkers.md
+19-0clang/test/Analysis/stream.c
+5-2clang/www/analyzer/checker_dev_manual.html
+6-0clang/test/Analysis/Inputs/system-header-simulator.h
+30-3455 files not shown
+30-35311 files

LLVM/project a19f976 — llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 shuffle-insert-zero.ll

[AArch64][DAG] Improve codegen for clearing upper vector lanes

Add patterns that use scalar fmov instruction to clear the upper lanes of a vector
DeltaFile
+305-16llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll
+69-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+374-162 files

LLVM/project c01c092 — clang/test/CodeGen/RISCV rvp-intrinsics.c, llvm/lib/Target/RISCV RISCVISelLowering.cpp

Fix riscv intrinsic regression
DeltaFile
+10-10clang/test/CodeGen/RISCV/rvp-intrinsics.c
+3-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1-1llvm/test/CodeGen/RISCV/rvp-widening-convert.ll
+14-123 files

LLVM/project ec906c0 — llvm/test/Analysis/ValueTracking knownbits-x86-hadd-hsub.ll, llvm/test/Transforms/InstCombine vec_shuffle-inseltpoison.ll insert-element-shuffle-vector-debugloc.ll

Update test checks
DeltaFile
+6-6llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
+4-4llvm/test/Transforms/InstCombine/vec_shuffle.ll
+2-2llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
+1-1llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
+1-1llvm/test/Transforms/InstCombine/insert-element-shuffle-vector-debugloc.ll
+1-1llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
+15-156 files

LLVM/project c72f6af — llvm/lib/Transforms/InstCombine InstCombineVectorOps.cpp, llvm/test/Transforms/InstCombine vec_shuffle.ll

[InstCombine] Canonicalise Vector Shuffle that clears upper bits

Currently, shuffle vectors that are equivalent to preserving lane 0 and clearing the uppers lanes of a vector result in different shuffle vectors and masks

Recognise and canonicalise the shuffleVectors to the same form allowing for easier recognition in the backend
DeltaFile
+38-0llvm/test/Transforms/InstCombine/vec_shuffle.ll
+10-2llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
+48-22 files

LLVM/project 842fb41 — llvm/include/llvm/IR LLVMRemarkStreamer.h, llvm/lib/IR LLVMRemarkStreamer.cpp

[LTO] Keep the remarks of every partition with parallel codegen

With ParallelCodeGenParallelismLevel > 1, splitCodeGen compiles each
partition in a fresh LTOLLVMContext. Those contexts have no remark
streamer, so code generation remarks (asm-printer, prolog-epilog,
regalloc, ...) never reach the -pass-remarks-output file.

Add LLVMRemarkBuffer, which streams the remarks of one context into an
in-memory bitstream buffer and later emits them through the serializer
of another context's remark file. splitCodeGen gives each partition a
buffer and, once all partitions are done, emits them in partition order,
so the file does not depend on thread scheduling. Remarks are copied as
they are; RemarkLinker would sort and deduplicate them and drop the ones
without a debug location.

Add -lto-partitions to llvm-lto2, the counterpart of lld's
--lto-partitions, so the parallel path can be tested.

Assisted-by: Claude Code (Claude Opus 5.5)
DeltaFile
+43-0llvm/test/LTO/Resolution/X86/parallel-codegen-remarks.ll
+42-0llvm/lib/IR/LLVMRemarkStreamer.cpp
+32-8llvm/lib/LTO/LTOBackend.cpp
+32-1llvm/include/llvm/IR/LLVMRemarkStreamer.h
+9-3llvm/tools/llvm-lto2/llvm-lto2.cpp
+158-125 files

LLVM/project d5a665b — clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/test/CIR/CodeGenCUDA host-used-device-var.cu

[CIR][CUDA] Emit device variables referenced only by host code (#236392)

CIR can omit static CUDA/HIP device and constant variables when they are
referenced only by host code. For example, a host function may pass a
device variable’s address to a device-symbol lookup API even though no
device function uses it. CIR skips host function bodies during device
compilation, so those references do not cause the variables to be
emitted.

Add these variables to the list that CIR emits at the end of
compilation, matching classic Clang code generation. Preserve the
recorded host references so the compiler can make the variables
accessible to host code and prevent them from being removed as unused.

Add a test checking that the device variables are emitted, the host-only
function remains absent, and a variable referenced only through `sizeof`
remains absent.

---------

Co-authored-by: Steffen Larsen <sholstla at amd.com>
DeltaFile
+29-0clang/test/CIR/CodeGenCUDA/host-used-device-var.cu
+6-1clang/lib/CIR/CodeGen/CIRGenModule.cpp
+35-12 files

LLVM/project d3c06e7 — offload/test/sanitizer kernel_crash_async.c

[Offload][test] Fix flaky kernel_crash_async.c

The three nowait target regions can launch in any order. Since only the
last one fails, we can only be sure to see its log record. The other
kernels might never run due to the crash.

Claude assisted with this patch.
DeltaFile
+1-1offload/test/sanitizer/kernel_crash_async.c
+1-11 files

LLVM/project dffed5d — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU load.ll

fix inf loop
DeltaFile
+47-0llvm/test/Analysis/CostModel/AMDGPU/load.ll
+10-3llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+57-32 files

LLVM/project a0409e5 — orc-rt/include/orc-rt/bedrock/sps LookupInJITDylibSPS.h, orc-rt/include/orc-rt/support JITDylibLookupFlags.h

[orc-rt] Add JITDylibLookupFlags argument to lookupInJITDylib (#240336)

sps::lookupInJITDylib had no way to say whether the lookup should match
all of a JITDylib's symbols, or only its exported symbols.

This commit adds a JITDylibLookupFlags enum (mirroring LLVM ORC's enum
of the same name) and a JITDylibLookupFlags parameter to
lookupInJITDylib. The flags are sent to the controller as a new argument
between the JITDylib key and the lookup set, using a new
SPSJITDylibLookupFlags tag that serializes as a bool: MatchAllSymbols as
true, MatchExportedSymbolsOnly as false.
DeltaFile
+49-0orc-rt/include/orc-rt/support/sps/SPSJITDylibLookupFlags.h
+34-11orc-rt/test/unit/bedrock/sps/LookupInJITDylibSPSTest.cpp
+26-0orc-rt/test/unit/support/sps/SPSJITDylibLookupFlagsTest.cpp
+26-0orc-rt/include/orc-rt/support/JITDylibLookupFlags.h
+5-4orc-rt/lib/bedrock/sps/LookupInJITDylibSPS.cpp
+5-1orc-rt/include/orc-rt/bedrock/sps/LookupInJITDylibSPS.h
+145-162 files not shown
+148-168 files

LLVM/project 509b485 — clang/lib/CodeGen CodeGenModule.h CodeGenModule.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+18-3clang/lib/CodeGen/CodeGenModule.cpp
+2-0clang/lib/CodeGen/CodeGenModule.h
+20-32 files

LLVM/project 2a57823 — clang/lib/CodeGen CodeGenModule.h CodeGenModule.cpp, llvm/lib/Target/RISCV RISCVTargetMachine.h RISCVTargetMachine.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+18-3clang/lib/CodeGen/CodeGenModule.cpp
+12-7llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+3-0llvm/lib/Target/RISCV/RISCVTargetMachine.h
+2-0clang/lib/CodeGen/CodeGenModule.h
+35-104 files

LLVM/project 221cc58 — clang/lib/CodeGen CodeGenModule.h CodeGenModule.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+18-3clang/lib/CodeGen/CodeGenModule.cpp
+2-0clang/lib/CodeGen/CodeGenModule.h
+20-32 files

LLVM/project dfc2e54 — llvm/lib/Support APFloat.cpp, llvm/test/CodeGen/ARM/GlobalISel arm-irtranslator.ll arm-legalize-fp.mir

Merge branch 'main' into users/lukel97/codegenprepare-lsr-constantint-fix
DeltaFile
+5,423-1,527llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+534-327llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+739-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mulwev_od.ll
+350-308llvm/lib/Support/APFloat.cpp
+643-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mulwev_od.ll
+596-0llvm/test/CodeGen/X86/vector-shuffle-var-legalize.ll
+8,285-2,162838 files not shown
+31,127-11,277844 files

LLVM/project 857e456 — lld/ELF Driver.cpp, lld/test/ELF format-binary.test

[lld][ELF] Fix .note.gnu.property values in ld -b binary invocations (#238541)

fixes: #237529

ld.lld -b binary generated bogus .note.gnu.property values because in
such invocations there are no ELF object files to AND the `-1` initial
value with. Use `0` as a starting value in that case.
DeltaFile
+8-2lld/ELF/Driver.cpp
+3-3lld/test/ELF/format-binary.test
+11-52 files

LLVM/project 22d766e — mlir/lib/Dialect/Vector/Transforms VectorUnroll.cpp, mlir/test/Dialect/Vector vector-unroll-options.mlir

[mlir][vector] Add comments and unify tests post #234448 (#240320)

Minor tweaks post https://github.com/llvm/llvm-project/pull/234448:
* Simplifies the comment in the implementation file.
* Adds comments in the test file.
* Unifies the tests to use <16x16> and <2x8x8>, as oppoed to <16x16> and
  <1x8x8x>.
DeltaFile
+28-8mlir/test/Dialect/Vector/vector-unroll-options.mlir
+3-4mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
+31-122 files

LLVM/project 188a956 — mlir/lib/Conversion/VectorToSCF VectorToSCF.cpp, mlir/test/Conversion/VectorToSCF vector-to-scf.mlir

[mlir][VectorToSCF] Decline transfer ops masked by vector.mask (#221307)

The transfer op patterns in `convert-vector-to-scf` unpack a
`vector.transfer_read`/`vector.transfer_write` into a loop, a buffer and
lower-rank transfer ops, but never check whether the op sits inside a
`vector.mask`. In that case all of it lands in the mask region and the
pass fails:

```mlir
func.func @w(%v: vector<4x8xf32>, %m: vector<4x8xi1>, %mem: memref<?x?xf32>) {
  %c0 = arith.constant 0 : index
  vector.mask %m { vector.transfer_write %v, %mem[%c0, %c0] : vector<4x8xf32>, memref<?x?xf32> } : vector<4x8xi1>
  return
}
```

```
error: 'vector.mask' op expects only one operation to mask
```

    [20 lines not shown]
DeltaFile
+83-0mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
+15-0mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
+98-02 files

LLVM/project 8ce83f5 — libc/src/__support/OSUtil/linux/syscall_wrappers CMakeLists.txt setsid.h, libc/src/unistd/linux CMakeLists.txt setsid.cpp

[libc] Use a syscall wrapper for setsid

This PR move setsid behind the centralized syscall wrappers, following libc/docs/dev/syscall_wrapper_refactor.md.
DeltaFile
+34-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+34-0libc/src/__support/OSUtil/linux/syscall_wrappers/setsid.h
+11-8libc/src/unistd/linux/setsid.cpp
+13-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+5-2libc/src/unistd/linux/CMakeLists.txt
+97-105 files

LLVM/project a66a121 — libc/src/__support/OSUtil/linux/syscall_wrappers CMakeLists.txt pwrite.h, libc/src/unistd/linux CMakeLists.txt pwrite.cpp

[libc] Use a syscall wrapper for pwrite

This PR move pwrite behind the centralized syscall wrappers, following libc/docs/dev/syscall_wrapper_refactor.md.
DeltaFile
+51-0libc/src/__support/OSUtil/linux/syscall_wrappers/pwrite.h
+11-24libc/src/unistd/linux/pwrite.cpp
+21-2utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+17-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+5-5libc/src/unistd/linux/CMakeLists.txt
+105-315 files

LLVM/project 36b725f — libc/src/__support/OSUtil/linux/syscall_wrappers CMakeLists.txt pread.h, libc/src/unistd/linux CMakeLists.txt pread.cpp

[libc] Use a syscall wrapper for pread

This PR move pread behind the centralized syscall wrappers, following libc/docs/dev/syscall_wrapper_refactor.md.
DeltaFile
+51-0libc/src/__support/OSUtil/linux/syscall_wrappers/pread.h
+11-22libc/src/unistd/linux/pread.cpp
+21-2utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+17-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+5-5libc/src/unistd/linux/CMakeLists.txt
+105-295 files

LLVM/project 8bec685 — libc/src/__support/OSUtil/linux/syscall_wrappers CMakeLists.txt pipe.h, libc/src/unistd/linux CMakeLists.txt pipe.cpp

[libc] Use a syscall wrapper for pipe

This PR move pipe behind the centralized syscall wrappers, following libc/docs/dev/syscall_wrapper_refactor.md.
DeltaFile
+39-0libc/src/__support/OSUtil/linux/syscall_wrappers/pipe.h
+11-13libc/src/unistd/linux/pipe.cpp
+16-1utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+12-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+5-3libc/src/unistd/linux/CMakeLists.txt
+83-175 files

LLVM/project 3617a14 — libsycl/test lit.site.cfg.py.in lit.cfg.py

[libsycl][lit] Fix PATH setup on Windows (#238826)

On Windows, `LLVMOffload.dll` is in `libsycl_libs_dir`, so append that
to the path in test setup.

Also, fix the `libsycl_libs_dir` logic to not be hardcoded for linux.

This fixes two issues when building on Windows, and the tests run and
all pass after this change.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>

Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
DeltaFile
+5-0libsycl/test/lit.cfg.py
+1-1libsycl/test/lit.site.cfg.py.in
+6-12 files

LLVM/project a771108 — llvm/lib/Target/AArch64 AArch64SVEInstrInfo.td

fixup! [AArch64] Add patterns to combine SVE AND and XOR to BIC

Use proper naming conventions for the newly added multiclasses.
DeltaFile
+20-20llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+20-201 files

LLVM/project bd48c7b — mlir/include/mlir/Dialect/SCF/IR SCFOps.td

[mlir][scf][NFC] Improve scf.forall doc examples (#240158)

Update the `scf.forall` IR examples to match the current syntax ,and fix
some typos.
DeltaFile
+13-11mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
+13-111 files

LLVM/project b1750fe — clang/lib/CodeGen CodeGenModule.h CodeGenModule.cpp, llvm/lib/Target/RISCV RISCVTargetMachine.h RISCVTargetMachine.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+18-3clang/lib/CodeGen/CodeGenModule.cpp
+12-7llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+3-0llvm/lib/Target/RISCV/RISCVTargetMachine.h
+2-0clang/lib/CodeGen/CodeGenModule.h
+35-104 files