LLVM/project 6129e1fllvm/lib/Transforms/Utils CloneFunction.cpp

[Utils] Hoist ValueMapper out of per-instruction remap loops in CloneFunction (#216014)

Remapping heap-allocates a ~500-byte Mapper per call and the clone paths
call these once per instruction. Since every public ValueMapper method
flushes on exit, a single instance of ValueMapper is used per loop
reducing allocations from 500*N to 500 per loop.

This change was developed with AI assistance. I have reviewed, tested,
and understand it and take ownership of it.
DeltaFile
+19-24llvm/lib/Transforms/Utils/CloneFunction.cpp
+19-241 files

LLVM/project bb2c2f0llvm/lib/Analysis ValueTracking.cpp, llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp

[KnownFPClass] Infer signs of finite nonzero fdiv results (#214912)

The only time a non-zero finite result can be generated from `x / y` is
if both `x` and `y` are either normal or subnormal. I used this
information to rule out sign information in some cases, such as
`sqrt(x)`, which can either be `-0.0` or `positive`. This is useful for
`1.0 / sqrt(x)` since `1.0 / -0.0` will never generate a negative normal
or negative subnormal.

AI disclosure:
I used OpenAI Codex (ChatGPT 5.6 sol) to write update the test cases,
implement the changes, and enable the additional analysis passes for the
FDIV intrinsic

***

Background: 

I discovered that `1.0 / sqrt(x)` was not able to rule out the result

    [7 lines not shown]
DeltaFile
+82-0llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
+79-0llvm/test/Transforms/Attributor/nofpclass-inv-sqrt.ll
+17-10llvm/lib/Analysis/ValueTracking.cpp
+23-4llvm/test/Transforms/InstCombine/fptoui-of-fdiv.ll
+16-9llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+11-11llvm/test/Transforms/Attributor/nofpclass-fdiv.ll
+228-341 files not shown
+240-347 files

LLVM/project be9f102llvm/lib/Target/AArch64 AArch64SMEAttributes.h AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sme-dynamic-tls.ll

[AArch64] Save more ZA state around TLS-descriptor calls (#216293)

Save agnostic ZA state and ZT0 state.
DeltaFile
+56-1llvm/test/CodeGen/AArch64/sme-dynamic-tls.ll
+20-15llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+4-0llvm/lib/Target/AArch64/AArch64SMEAttributes.h
+80-163 files

LLVM/project 99cc412llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-shift-trunc-combine.ll

[AArch64] Combine shift and truncate into deinterleave. (#216060)

This is an alternative approach to #213252, from which I've taken some
of the tests.

Co-authored-by: Jacob Crawley <jacob.crawley at arm.com>
DeltaFile
+162-0llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
+21-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+183-02 files

LLVM/project 962c55flldb/include/lldb/Target Process.h, lldb/unittests/ValueObject GetPointeeDataTest.cpp

[lldb][NFC] Fix GetPointeeDataTest after the ProcessAddress migration (#216978)

One unit-test override was missed when `Process::DoReadMemory` was
changed to accept `const ProcessAddress &`. `SentinelProcess` in
`GetPointeeDataTest.cpp` still uses `lldb::addr_t`, so the override does
not match, the mock remains abstract, and `check-lldb` fails to build.

Update the parameter type and the remaining stale `Process.h`
documentation. This is a quick NFC fix for the broken build.

## Testing

`check-lldb` builds successfully.
DeltaFile
+2-2lldb/include/lldb/Target/Process.h
+2-1lldb/unittests/ValueObject/GetPointeeDataTest.cpp
+4-32 files

LLVM/project 511757dllvm/lib/Target/SPIRV SPIRVPrepareFunctions.cpp, llvm/test/CodeGen/SPIRV/passes SPIRVPrepareFunctions.ll

[SPIR-V] Fix crash when a function pointer global is a use of a cloned function (#216638)

GlobalValue operands must be updated via replaceUsesOfWith, not
Constant::handleOperandChange, which doesn't support them

Fixes LCOMPILER-2616
DeltaFile
+24-0llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareFunctions.ll
+4-7llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+28-72 files

LLVM/project b13bb17llvm/test/CodeGen/AMDGPU amdgcn.bitcast.320bit.ll amdgcn.bitcast.768bit.ll

[AMDGPU][NFC] Add GFX13 run lines to bitcast tests
DeltaFile
+37,371-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,251-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+9,658-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+9,084-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+8,503-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+8,459-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+83,326-018 files not shown
+138,223-824 files

LLVM/project 9fbfaa1llvm/include/llvm/IR RuntimeLibcalls.td, llvm/test/CodeGen/X86 ldexp-avx512.ll fp80-math-no-libcall-error.ll

RuntimeLibcalls: Fix wrongly typed x87/fp128 long double libcalls on x86

The x86 and default libcall sets gated the l-suffixed long double libm
functions on OS conditions rather than the long double format. This
incorrectly provided the f80 libcalls on targets whose long double is not x87
(Windows-MSVC, UEFI, x86_64 Android), double-provided frexpl/ldexpl on musl,
and provided the fp128 sincosl on targets using double as long double (m68k).

Gate the l-suffixed libm math on the long double format, mirroring the earlier
AArch64 fix: x87 targets get the _f80 calls, fp128 targets the _f128 calls, and
double targets neither. The compiler-rt f80 helpers (__extendxftf2, __fixxfti,
__powixf2, ...) are keyed to the x86_fp80 IR type, not the long double format,
so they stay unconditional on x86.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+374-0llvm/test/CodeGen/X86/fp80-math-libcalls.ll
+0-359llvm/test/CodeGen/X86/finite-libcalls.ll
+146-0llvm/test/CodeGen/X86/fp80-conv-libcalls.ll
+92-0llvm/test/CodeGen/X86/fp80-math-no-libcall-error.ll
+44-17llvm/include/llvm/IR/RuntimeLibcalls.td
+11-6llvm/test/CodeGen/X86/ldexp-avx512.ll
+667-3822 files not shown
+681-3848 files

LLVM/project b900a75llvm/test/Transforms/LoopVectorize scalable-lifetime.ll, llvm/test/Transforms/LoopVectorize/AArch64 type-shrinkage-zext-costs.ll sve-interleaved-masked-accesses.ll

[LV][NFC] Regenerate CHECK lines in some tests (#216728)
DeltaFile
+294-294llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
+141-141llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
+85-85llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
+61-61llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
+52-52llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll
+633-6335 files

LLVM/project 2d10fedllvm/lib/Target/RISCV/GISel RISCVPostLegalizerCombiner.cpp RISCVInstructionSelector.cpp

RISCV/GlobalISel: Use mi_match for constant checks (#216954)

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+5-7llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+3-6llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
+8-132 files

LLVM/project c7ff5c3llvm/lib/CodeGen/SelectionDAG LegalizeTypes.h LegalizeFloatTypes.cpp, llvm/test/CodeGen/Mips/msa f16vec.ll

[SelectionDAG] Fix soft-promotion of f16 BUILD_VECTOR for MSA targets (#210515)

When compiling for MIPS with +msa and f16 vectors (v8f16, v4f16, v2f16),
LLVM would crash with "Do not know how to soft promote this operator's
operand!" because BUILD_VECTOR was missing from the
SoftPromoteHalfOperand switch statement in LegalizeFloatTypes.cpp.

On MIPS, f16 is not natively supported by default, so LLVM soft-promotes
it: stores as i16, computes as f32.

Building f16 vectors requires handling BUILD_VECTOR with soft-promoted
i16 operands.

This patch adds the missing BUILD_VECTOR case and implements
SoftPromoteHalfOp_BUILD_VECTOR, which:
(1) retrieves soft-promoted i16 operands via GetSoftPromotedHalf,
(2) builds a v{N}i16 integer vector,
(3) bitcasts to the original v{N}f16 type.


    [11 lines not shown]
DeltaFile
+135-0llvm/test/CodeGen/Mips/msa/f16vec.ll
+16-0llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+152-03 files

LLVM/project e714127llvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.cpp

AArch64: Use mi_match for G_CONSTANT operand check in RegisterBankInfo (#216955)

Replace the getVRegDef + G_CONSTANT opcode check in the build_vector
all-constant-operands test with an m_ICst match. NFC.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+4-2llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+4-21 files

LLVM/project f215bddllvm/test/CodeGen/AMDGPU amdgcn.bitcast.320bit.ll amdgcn.bitcast.768bit.ll

[AMDGPU][NFC] Add GFX13 run lines to bitcast tests
DeltaFile
+37,371-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+10,251-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+9,658-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+9,084-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+8,503-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+8,459-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+83,326-018 files not shown
+138,240-824 files

LLVM/project b5e18baflang/lib/Lower HlfirIntrinsics.cpp, flang/lib/Optimizer/HLFIR/IR HLFIROps.cpp

[Flang][HLFIR] Lower PACK(array, .TRUE.) to hlfir.reshape (#213603)

When the PACK mask is the compile-time scalar .TRUE., the result is
equivalent to RESHAPE(array, [SIZE(array)]). Detect this case during
HLFIR intrinsic lowering and emit hlfir.reshape, reusing the same
operation as the RESHAPE intrinsic rather than calling _FortranAPack.

This allows later optimization passes to handle the operation as a
reshape instead of going through the general PACK runtime. Variable or
array masks, VECTOR, and non-trivial or polymorphic operands continue to
use the existing runtime PACK path.

Assisted by: Claude
DeltaFile
+109-0flang/test/HLFIR/simplify-hlfir-intrinsics-pack.fir
+67-0flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
+41-8flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
+48-0flang/test/Lower/HLFIR/pack_scalar_true.f90
+29-1flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+25-0flang/lib/Lower/HlfirIntrinsics.cpp
+319-94 files not shown
+358-3510 files

LLVM/project fec2cballvm/lib/Transforms/InstCombine InstCombineSelect.cpp, llvm/test/Transforms/InstCombine select-masked_load.ll

[InstCombine] Fix miscompile when folding a select into a masked load (#216730)

`visitSelectInst` folds:

    select(mask, masked.load(ptr, mask, PT), FV)

into:

    masked.load(ptr, mask, FV)

The replacement load was previously created at the select, effectively
moving the memory access past any intervening instructions. If one of
them writes the loaded memory, the replacement load reads the updated
value instead of the original one. This was also observed downstream in
[ispc/ispc#3891](https://github.com/ispc/ispc/issues/3891).

The fold was added in `eb8589987267`. The issue is labelled
`regression:22`, so it affects LLVM 22.1 as well as current trunk.


    [12 lines not shown]
DeltaFile
+41-0llvm/test/Transforms/InstCombine/select-masked_load.ll
+10-5llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+51-52 files

LLVM/project fff6637flang/lib/Lower PFTBuilder.cpp, flang/test/Lower assigned-goto-format-target.f90

[flang][PFT] do not record a FORMAT statement as an assigned GO TO target

A FORMAT statement is not a branch target, so a program that assigns its
label to a variable and then branches to that variable is not conforming
and is meant to reach a run-time error.

Skip FORMAT statements when recording the targets, the same way the
AssignStmt case already does.

Only the `go to v` form needs this: in `go to v, (l1, l2, ...)` a
FORMAT label is rejected during semantic checking, so it never reaches
the PFT. assign07.f90 is extended to test this semantic check.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+48-0flang/test/Lower/assigned-goto-format-target.f90
+16-2flang/lib/Lower/PFTBuilder.cpp
+6-0flang/test/Semantics/assign07.f90
+70-23 files

LLVM/project 796a186llvm/lib/Target/AArch64 AArch64ConditionOptimizer.cpp, llvm/test/CodeGen/AArch64 aarch64-condopt-cross-block-select.mir

[AArch64] Extend optimizeCrossBlock() to handle select-family instructions (#208369)

* The cross-block condition optimizer previously only handled blocks
ending with a Bcc terminator. This patch extends optimizeCrossBlock() to
also recognize CSEL, CSET, CSINC, CSINV, and CSNEG as conditional
consumers by introducing findCondConsumer(), which unifies consumer
discovery for both block roles: trying a Bcc terminator first and
falling back to a reverse scan for the sole NZCV-consuming select-family
instruction if no Bcc is present.

* This enables CMP adjustment and CSE elimination across all four
head/true-successor combinations: Bcc+Bcc (original), Select+Bcc,
Bcc+Select, and Select+Select.

* Tests are added in aarch64-condopt-cross-block-select.mir covering all
three new combinations along with negative cases for NZCV liveness and
mismatched registers.

Assisted by: Claude for mir test cases
DeltaFile
+567-0llvm/test/CodeGen/AArch64/aarch64-condopt-cross-block-select.mir
+108-21llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+675-212 files

LLVM/project 94d4607llvm/lib/Transforms/Scalar LoopInterchange.cpp

address review
DeltaFile
+3-1llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+3-11 files

LLVM/project d37fa5allvm/include/llvm/ADT FoldingSet.h

Revert "[ADT] Remove CRTP from FoldingSet and ContextualFoldingSet (NFC)" (#216957)

Reverts llvm/llvm-project#216830 due to breakage on msvc builds
DeltaFile
+104-59llvm/include/llvm/ADT/FoldingSet.h
+104-591 files

LLVM/project 6bba49autils/bazel/llvm-project-overlay/libc BUILD.bazel, utils/bazel/llvm-project-overlay/libc/test/src/math/smoke BUILD.bazel

[Bazel] Fixes de7cacd (#216949)

This fixes de7cacd2406aa805a463f26563b4f55811842ba0 (#216552).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=de7cacd2406aa805a463f26563b4f55811842ba0

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+3-0utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
+3-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+6-02 files

LLVM/project e61de01llvm/lib/Transforms/Vectorize VPlan.cpp

[VPlan] Check enclosing region first (NFC). (#216676)

Check cheaper getEnclosingLoopRegion() first; it only walks the parent
chain, while getVectorLoopRegion() traverses the plan's top-level
blocks.
DeltaFile
+2-2llvm/lib/Transforms/Vectorize/VPlan.cpp
+2-21 files

LLVM/project 533f447llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange inner-latch-defs-iv.ll

[LoopInterchange] Bail out if a PHI would be cloned into the new latch
DeltaFile
+58-0llvm/test/Transforms/LoopInterchange/inner-latch-defs-iv.ll
+26-30llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+84-302 files

LLVM/project aeee8b8llvm/include/llvm InitializePasses.h, llvm/include/llvm/CodeGen ImplicitNullChecks.h

[NewPM] Port ImplicitNullChecks to the new pass manager

Adds a newPM pass for ImplicitNullChecks.

- Refactors base logic into an ImplicitNullChecks class
- Renames old pass with the "Legacy" suffix
- Adds the new pass manager pass ImplicitNullChecksPass
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder
- Updated existing .mir tests to also test with the New Pass Manager

TAG=agy
CONV=f54ff826-1008-4e8c-9be5-0364adbe3923
DeltaFile
+37-12llvm/lib/CodeGen/ImplicitNullChecks.cpp
+28-0llvm/include/llvm/CodeGen/ImplicitNullChecks.h
+1-1llvm/lib/CodeGen/CodeGen.cpp
+1-1llvm/include/llvm/Passes/MachinePassRegistry.def
+1-1llvm/include/llvm/InitializePasses.h
+1-0llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
+69-153 files not shown
+72-159 files

LLVM/project c9fdb59llvm/lib/Target/SPIRV SPIRVCombinerHelper.cpp

SPIRV: Use mi_match in combiner match functions

Convert some simple cases away from getVRegDef + opcode
checks which don't require new matchers.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+4-9llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
+4-91 files

LLVM/project 326d86dllvm/include/llvm/ADT FoldingSet.h

Revert "[ADT] Remove CRTP from FoldingSet and ContextualFoldingSet (NFC) (#21…"

This reverts commit 703f0ae7e68f3cbb3679aef3ac4079d9d4ca3e52.
DeltaFile
+104-59llvm/include/llvm/ADT/FoldingSet.h
+104-591 files

LLVM/project c49ed73llvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.cpp

AArch64: Use mi_match for G_CONSTANT operand check in RegisterBankInfo

Replace the getVRegDef + G_CONSTANT opcode check in the build_vector
all-constant-operands test with an m_ICst match. NFC.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+4-2llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+4-21 files

LLVM/project 84a25f6llvm/lib/Target/RISCV/GISel RISCVPostLegalizerCombiner.cpp RISCVInstructionSelector.cpp

RISCV/GlobalISel: Use mi_match for constant checks

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+5-7llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+3-6llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
+8-132 files

LLVM/project da1fb5cllvm/test/tools/llvm-readobj/ELF linker-options.test bb-addr-map.test, llvm/tools/llvm-readobj ELFDumper.cpp

[llvm-readobj] Improve unsupported option messages (#216488)

Improve the messages for unsupported options when using GNU output
style.
Fixes #51294.
DeltaFile
+3-3llvm/tools/llvm-readobj/ELFDumper.cpp
+2-2llvm/test/tools/llvm-readobj/ELF/call-graph-profile.test
+1-1llvm/test/tools/llvm-readobj/ELF/linker-options.test
+1-1llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test
+1-1llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
+8-85 files

LLVM/project 55feb0aclang/lib/Frontend SerializedDiagnosticPrinter.cpp, clang/test/Misc serialized-diags-large-fixit.m

[Clang][Frontend] Fix fix-it size overflow in emitted .dia (#216075)

When fix-its are emitted into a .dia, we previously stored the fix-it
text in a blob of arbitrary size, but the size of the text was stored in
a separate 16 bit field. For really large fix-its, the size won't fit it
those 16 bits, and the compiler crashes.

Switch to a variable length encoding of the fit-it size. This is similar
to this issue:
https://github.com/llvm/llvm-project/commit/e26aea5b290165f3bccffab662a706d4a56f7540

We also remove a hard coded check in the clang library used to load .dia
files that failed for fix-its whose size doesn't fit in 16 bits.

Generated with codex

Co-authored-by: Nuri Amari <nuriamari at fb.com>
(cherry picked from commit bb123b2208060bf3ec8a5f22f2111bd194c4ad4d)
DeltaFile
+45-0clang/test/Misc/serialized-diags-large-fixit.m
+0-3clang/tools/libclang/CXLoadedDiagnostic.cpp
+1-1clang/lib/Frontend/SerializedDiagnosticPrinter.cpp
+46-43 files

LLVM/project fc5861dcompiler-rt/lib/msan/tests msan_test.cpp, compiler-rt/test/fuzzer reload.test

[sanitizer] Skip hanging tests on NetBSD (#216712)

Several sanitizer tests hang indefinitely on NetBSD:

```
MemorySanitizer-Unit :: ./Msan-x86_64-Test
MemorySanitizer-Unit :: ./Msan-x86_64-with-call-Test
MemorySanitizer-X86_64 :: zero_alloc.cpp
ThreadSanitizer-x86_64 :: signal_cond.cpp
libFuzzer-x86_64-default-NetBSD :: reload.test
```

All of them loop and don't time out, so they need to be terminated
manually for `ninja check-all` to complete. To avoid this, this patch
skips the affected tests or subtests. Unfortunately, the Msan unit tests
still hang on exit in `__cxa_finalize` even if all subtests are skipped
with `llvm-lit -gtest_filter=-*`.

Tested on `x86_64-pc-netbsd11.0`, `x86_64-pc-freebsd15.1`, and

    [3 lines not shown]
DeltaFile
+4-0compiler-rt/lib/msan/tests/msan_test.cpp
+2-0compiler-rt/test/tsan/signal_cond.cpp
+2-0compiler-rt/test/msan/zero_alloc.cpp
+1-0compiler-rt/test/fuzzer/reload.test
+9-04 files