LLVM/project 60a2e2bclang/include/clang/Driver Options.td, clang/include/clang/Lex LiteralConverter.h

address comments
DeltaFile
+30-23clang/lib/Lex/LiteralConverter.cpp
+31-13clang/lib/Lex/LiteralSupport.cpp
+15-11clang/lib/Driver/ToolChains/Clang.cpp
+11-6clang/include/clang/Lex/LiteralConverter.h
+9-7clang/test/Driver/clang_f_opts.c
+9-4clang/include/clang/Driver/Options.td
+105-6411 files not shown
+130-7617 files

LLVM/project 6988ba2clang/lib/Frontend FrontendAction.cpp, clang/lib/Lex PPDirectives.cpp

do not translate line/digit directives, do not translate filename
DeltaFile
+4-2clang/lib/Lex/PPDirectives.cpp
+3-1clang/lib/Frontend/FrontendAction.cpp
+7-32 files

LLVM/project f39e2a0llvm/lib/Transforms/Vectorize LoopVectorize.cpp

[LoopVectorize][NFC] Refactor widening decision logic
DeltaFile
+24-28llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+24-281 files

LLVM/project 482b715mlir/lib/Bindings/Python IRCore.cpp

Update mlir/lib/Bindings/Python/IRCore.cpp

Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
DeltaFile
+1-1mlir/lib/Bindings/Python/IRCore.cpp
+1-11 files

LLVM/project b08f1f8llvm/unittests/Analysis IVDescriptorsTest.cpp

[IVDescriptors] Add unit tests for MonotonicDescriptor
DeltaFile
+131-0llvm/unittests/Analysis/IVDescriptorsTest.cpp
+131-01 files

LLVM/project bba40abmlir/include/mlir/Dialect/XeGPU/IR XeGPUAttrs.td, mlir/include/mlir/Dialect/XeGPU/Transforms Passes.td

[MLIR][XeGPU] Decouple `inst_data` and `lane_layout` in propagation (#166941)

DeltaFile
+124-70mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+21-21mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
+11-0mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+8-1mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
+1-1mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
+1-1mlir/test/Dialect/XeGPU/propagate-layout.mlir
+166-946 files

LLVM/project c08f8babolt/lib/Passes PointerAuthCFIAnalyzer.cpp, bolt/test/AArch64 negate-ra-state-incorrect.s

[BOLT] Use opts::Verbosity in PointerAuthCFIAnalyzer
DeltaFile
+17-10bolt/lib/Passes/PointerAuthCFIAnalyzer.cpp
+1-1bolt/test/AArch64/negate-ra-state-incorrect.s
+18-112 files

LLVM/project 18993b2bolt/unittests/Passes InsertNegateRAState.cpp

[BOLT] Test fillUnknownStubs
DeltaFile
+61-0bolt/unittests/Passes/InsertNegateRAState.cpp
+61-01 files

LLVM/project 4745d5dbolt/lib/Passes InsertNegateRAStatePass.cpp PointerAuthCFIFixup.cpp, bolt/unittests/Passes PointerAuthCFIFixup.cpp InsertNegateRAState.cpp

[BOLT][NFC] Rename Pointer Auth DWARF rewriter passes

Original names were "working titles". After initial patches are merged,
I'd like to rename these passes to names that reflect their intent
better and show their relationship to each other:

InsertNegateRAStatePass renamed to PointerAuthCFIFixup,
MarkRAStates renamed to PointerAuthCFIAnalyzer.
DeltaFile
+0-350bolt/lib/Passes/InsertNegateRAStatePass.cpp
+350-0bolt/lib/Passes/PointerAuthCFIFixup.cpp
+288-0bolt/unittests/Passes/PointerAuthCFIFixup.cpp
+0-288bolt/unittests/Passes/InsertNegateRAState.cpp
+0-145bolt/lib/Passes/MarkRAStates.cpp
+145-0bolt/lib/Passes/PointerAuthCFIAnalyzer.cpp
+783-78313 files not shown
+929-92819 files

LLVM/project 1697336bolt/lib/Passes PointerAuthCFIAnalyzer.cpp, bolt/test/runtime/AArch64 pacret-synchronous-unwind.cpp

[BOLT][PAC] Warn about synchronous unwind tables

BOLT currently ignores functions with synchronous PAuth DWARF info.
When more than 10% of functions get ignored for inconsistencies, we
should emit a warning to only use asynchronous unwind tables.

See also: #165215
DeltaFile
+33-0bolt/test/runtime/AArch64/pacret-synchronous-unwind.cpp
+8-1bolt/lib/Passes/PointerAuthCFIAnalyzer.cpp
+41-12 files

LLVM/project ca5f677bolt/docs PacRetDesign.md

Update bolt/docs/PacRetDesign.md

Co-authored-by: Paschalis Mpeis <paschalis.mpeis at arm.com>
DeltaFile
+1-1bolt/docs/PacRetDesign.md
+1-11 files

LLVM/project 291486abolt/docs PacRetDesign.md

Update PacRetDesign.md
DeltaFile
+1-1bolt/docs/PacRetDesign.md
+1-11 files

LLVM/project de568ecbolt/unittests/Passes InsertNegateRAState.cpp

[BOLT] Test fillUnknownRAStateInBB
DeltaFile
+63-0bolt/unittests/Passes/InsertNegateRAState.cpp
+63-01 files

LLVM/project 6219f74bolt/docs PacRetDesign.md, bolt/include/bolt/Passes InsertNegateRAStatePass.h

[BOLT] Improve InsertNegateRAStatePass::inferUnknownStates

Previous implementation used a simple heuristic. This can be improved in
several ways:
- If a BasicBlock has instruction both with known RAState and unknown RAState,
  use the known states to work out the unknown ones.
- If a BasicBlock only consists of instructions with unknown RAState,
  use the last known RAState from its predecessors, or the first known
  from its successors to set the RAStates in the BasicBlock. This includes
  error checking: all predecessors/successors should have the same RAState.
- Some BasicBlocks may only contain instructions with unknown RAState,
  and have no CFG neighbors. These already have incorrect unwind info.
  For these, we copy the last known RAState based on the layout order.

Updated bolt/docs/PacRetDesign.md to reflect changes.
DeltaFile
+203-20bolt/lib/Passes/InsertNegateRAStatePass.cpp
+32-2bolt/include/bolt/Passes/InsertNegateRAStatePass.h
+18-5bolt/docs/PacRetDesign.md
+253-273 files

LLVM/project 56b26babolt/unittests CMakeLists.txt, bolt/unittests/Passes InsertNegateRAState.cpp CMakeLists.txt

[BOLT] Single-pass unittest for InsertNegateRAState

This commit creates a new directory: bolt/unittests/Passes, to be used
by unittests that need to register and run passes with the
BinaryFunctionPassManager.

An example test is created for InsertNegateRAState pass. Actual tests
will be added in followup commits.
DeltaFile
+164-0bolt/unittests/Passes/InsertNegateRAState.cpp
+30-0bolt/unittests/Passes/CMakeLists.txt
+1-0bolt/unittests/CMakeLists.txt
+195-03 files

LLVM/project d1f66f7bolt/lib/Passes InsertNegateRAStatePass.cpp

[BOLT] Bugfix: use getFirstNonPseudo() instead of begin()

RA states are only assigned to non-pseudo instructions. Because of this,
CFI instructions are skipped.
Here, I incorrectly used begin(), not skipping CFIs.
DeltaFile
+3-2bolt/lib/Passes/InsertNegateRAStatePass.cpp
+3-21 files

LLVM/project a873e78bolt/lib/Passes InsertNegateRAStatePass.cpp

[BOLT] Review changes

- remove unused PrevInst
- add a static PassFailed, and createFatalBOLTError() if the pass failed
  on any of the threads executed in parallel. This is the same way
  ADRRelaxationPass handles errors in threads.
DeltaFile
+10-2bolt/lib/Passes/InsertNegateRAStatePass.cpp
+10-21 files

LLVM/project 7be06ccbolt/include/bolt/Core MCPlusBuilder.h, bolt/lib/Core MCPlusBuilder.cpp

[BOLT] Change RAState helpers (NFCI)

- unify isRAStateSigned and isRAStateUnsigned to a common getRAState,
- unify setRASigned and setRAUnsigned into setRAState(MCInst, bool),
- update users of these to match the new implementations.
DeltaFile
+27-11bolt/lib/Passes/InsertNegateRAStatePass.cpp
+11-16bolt/lib/Core/MCPlusBuilder.cpp
+6-13bolt/include/bolt/Core/MCPlusBuilder.h
+2-10bolt/lib/Passes/MarkRAStates.cpp
+46-504 files

LLVM/project 820b9c3llvm/lib/Target/AMDGPU SIFrameLowering.cpp, llvm/test/CodeGen/AMDGPU amdgpu-cs-chain-frame-pointer.ll

Added test case to verify no FP setup occurs with "frame-pointer"="all".
DeltaFile
+15-0llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-frame-pointer.ll
+7-7llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+22-72 files

LLVM/project f67737bllvm/test/CodeGen/AMDGPU cc-entry.ll

Add test
DeltaFile
+8-0llvm/test/CodeGen/AMDGPU/cc-entry.ll
+8-01 files

LLVM/project 03c691dllvm/test/CodeGen/AMDGPU cc-entry.ll

Use autogenerate, use stdout, add call to entry from another fn
DeltaFile
+63-2llvm/test/CodeGen/AMDGPU/cc-entry.ll
+63-21 files

LLVM/project b863f78llvm/lib/Target/AMDGPU AMDGPUResourceUsageAnalysis.cpp

[AMDGPU] Remove calling conv check on entry function

It is undefined behavior to call a function with a
mismatched calling convention. Rather than crash on
this behavior, it should compile.
DeltaFile
+0-7llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
+0-71 files

LLVM/project be84705llvm/test/CodeGen/SPIRV/opencl unpackhalf2x16-error.ll

[HLSL][SPIRV] Add error test for unpackhalf2x16 (#166969)

Add an error test to check that a suitable error diagnostic is generated
for the use of the GL::unpackhalf2x16 operation in
 invalid contexts.

Fixes #166965

Co-authored-by: Tim Corringham <tcorring at amd.com>
DeltaFile
+11-0llvm/test/CodeGen/SPIRV/opencl/unpackhalf2x16-error.ll
+11-01 files

LLVM/project f22d588mlir/lib/Transforms/Utils DialectConversion.cpp

[mlir] Dialect Conversion: Fix expensive pattern check in no-rollback mode (#166576)

Fixes a bug causing every conversion to fail fatally with "expected
pattern to replace the root operation or modify it in place" when
`MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS` is enabled and pattern
rollback is disabled.

When `allowPatternRollback` is disabled, the rewriter does not keep
track of the rewrites it performs and can therefore not use that list to
check whether the root op was replaced or updated in place.
DeltaFile
+13-11mlir/lib/Transforms/Utils/DialectConversion.cpp
+13-111 files

LLVM/project 342e28fclang/lib/CodeGen CGCall.cpp CGDebugInfo.h, clang/test/DebugInfo/CXX decl-member-call.cpp

[clang][DebugInfo] Attach `DISubprogram` to additional call variants (#166202)

`DISubprogram`s are attached to call sites to support various debug info
features, including entry values and tail calls. Clang 9.0
(0f6516856670a435461f56a9faeb4aa8a35a6679) was the first version to
include this kind of call site `DISubprogram` attachment.

This earlier work appears to visit only some call site variants,
however. The call site attachment was added to a higher-level `EmitCall`
path in Clang's code gen that is only used by some call variants. In
particular, some C++ member calls use a different code gen path, which
did not include this call site attachment step, and thus the debug info
it triggers (e.g. call site entries) was not emitted for such calls.

This moves `DISubprogram` attachment to a lower-level call emission path
that is used by all call variants.

Fixes https://github.com/llvm/llvm-project/issues/161962
DeltaFile
+25-0clang/test/DebugInfo/CXX/decl-member-call.cpp
+19-0clang/lib/CodeGen/CGCall.cpp
+5-6clang/lib/CodeGen/CGDebugInfo.h
+0-9clang/lib/CodeGen/CGExpr.cpp
+6-2clang/lib/CodeGen/CGDebugInfo.cpp
+55-175 files

LLVM/project 309729eclang/test/C/C2y n3348.c, clang/www c_status.html

[C2y] Claim nonconformance to WG14 N3348 (#166966)

This paper allows use of * in a multidimensional array extent within a
_Generic selection association, as a wildcard for any array extent.

Clang does not currently support this feature, so this is just some
initial test coverage along with an update to the conformance site.
DeltaFile
+44-0clang/test/C/C2y/n3348.c
+1-1clang/www/c_status.html
+45-12 files

LLVM/project 7886359llvm/test/CodeGen/AMDGPU cc-entry.ll

Use autogenerate, use stdout, add call to entry from another fn
DeltaFile
+63-2llvm/test/CodeGen/AMDGPU/cc-entry.ll
+63-21 files

LLVM/project 2705951llvm/test/CodeGen/X86 2012-01-10-UndefExceptionEdge.ll

[X86] 2012-01-10-UndefExceptionEdge.ll - regenerate test checks (#167307)

DeltaFile
+10-10llvm/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll
+10-101 files

LLVM/project d4eecd0llvm/lib/Target/AMDGPU SIFrameLowering.cpp SIMachineFunctionInfo.cpp, llvm/test/CodeGen/AMDGPU amdgpu-cs-chain-frame-pointer.ll

For emitEpilogue, emitCSRSpillRestores' argument in FPSaved case to handle chain functions in same way as non-FPSaved case, an offset. Remove prior hardcode to s33 and do not restore FP for chain functions.
DeltaFile
+8-3llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-frame-pointer.ll
+3-2llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+0-1llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+11-63 files

LLVM/project 4c9ae7cllvm/lib/Target/AMDGPU SIMachineFunctionInfo.cpp, llvm/test/CodeGen/AMDGPU amdgpu-cs-chain-frame-pointer.ll

[AMDGPU] Initialize FrameOffsetReg for amdgpu_cs_chain functions

Functions with the amdgpu_cs_chain calling convention were not
initializing FrameOffsetReg, leaving it as FP_REG.
This caused machine code verification failures
as SCRATCH_STORE_DWORD_SADDR instructions require the saddr
operand to be in the SReg_32_XEXEC_HI register class.

This LLVM defect was identified via the AMD Fuzzing project.
DeltaFile
+64-0llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-frame-pointer.ll
+1-0llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+65-02 files