[Delinearization] Precommit global decl test. NFC. (#175173)
This precommits a test that should demonstrate that Delinearization can
succeed when we analyse the size of the global variable definition.
[SPIRV] Added Support for the SPV_ALTERA_arbitrary_precision_floating_point Extension (#160054)
Added support for the SPV_ALTERA_arbitrary_precision_floating_point
extension, enabling all the arbitrary precision floating-point
operations with instruction definitions and test files.
[SPIRV] Added support for the constrained arithmetic(Fmuladd) intrinsic (#170270)
Added SPIR-V support for constrained arithmetic intrinsic fmuladd,
lowered as a sequence of OpFMul and OpFAdd with roundingmode, consistent
with the SPIR-V translator.
[llvm][LoongArch] Add PC-relative address materialization using pcadd instructions (#175358)
This patch adds support for PC-relative address materialization using
pcadd-class relocations, covering the HI20/LO12 pair and their GOT and
TLS variants (IE, LD, GD, and DESC).
Link:
https://gcc.gnu.org/pipermail/gcc-patches/2025-December/703312.html
[InferAddressSpaces] Handle unconverted ptrmask (#140802)
In case a ptrmask cannot be converted to the new address space due to an
unknown mask value, this needs to be detcted and an addrspacecast is
needed to not hinder a future use of the unconverted return value of
ptrmask. Otherwise, users of this value will become invalid by receiving
a nullptr as an operand.
This LLVM defect was identified via the AMD Fuzzing project.
(See https://reviews.llvm.org/D80129 for an explanation of why some
ptrmasks are impossible to convert to other addrspaces.)
[clang][ExprConst] Diagnose out-of-lifetime access consistently (#175562)
Previously, we had two very similar diagnostics, "read of object outside
its lifetime" and "read of variable whose lifetime has ended".
The difference, as far as I can tell, is that the latter was used when
the variable was created in a function frame that has since vanished,
i.e. in this case:
```c++
constexpr const int& return_local() { return 5; }
static_assert(return_local() == 5);
```
so the output used to be:
```console
array.cpp:602:15: error: static assertion expression is not an integral constant expression
602 | static_assert(return_local() == 5);
| ^~~~~~~~~~~~~~~~~~~
array.cpp:602:15: note: read of temporary whose lifetime has ended
array.cpp:601:46: note: temporary created here
601 | constexpr const int& return_local() { return 5; }
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[VPlan] Replace PhiR operand of ComputeRdxResult with VPIRFlags. (#174026)
Remove the artificial PhiR operand of ComputeReductionResult, which was
only used to look up recurrence kind, in-loop and ordered properties.
Instead, encode them as VPIRFlags as suggested by @ayalz in
https://github.com/llvm/llvm-project/pull/170223.
This addresses a TODO to make codegen for ComputeReductionResult
independent of looking up information from other recipes.
This is NFC w.r.t. codegen, the printing has been improved to include
the reduction type, and whether it is in-loop/ordered.
PR: https://github.com/llvm/llvm-project/pull/174026
[IndirectCallPromotion] Proper canonicalize coroutine function (#175606)
Fix an issue where coroutine function and its await suspend wrappers are
all canonicalized to the same name. This creates duplicate entries in
`MD5FuncMap` (a sorted vector) and may return an incorrect GUID that
mismatches the one from prof metadata and miss ICP. For example, coro
function `foo` and its wrappers `foo.__await_suspend_wrapper__init`,
`foo.__await_suspend_wrapper__final` are all canonicalized to `foo`.
During GUID lookup, any of them can be returned due to unstable sort.
This is more of the reliability issue (the indeterminism) than a
performance issue because hot indirect calls should've been promoted in
sample loader pass.
This also fixes the same naming issue in `CGProfile` where symtab is
created. By the time the pass is run, wrapper functions should already
be inlined but naming collision can happen to the coro function and its
post-split clones (`foo.resume`, `foo.cleanup`).
This change
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[VPlan] Split out optimizeEVLMasks. NFC (#174925)
Addresses part of #153144 and splits off part of #166164
There are two parts to the EVL transform:
1) Convert the loop so the number of elements processed each iteration
is EVL, not VF. The IV and header mask are replaced with EVL-based
variants.
2) Optimize users of the EVL based header mask to VP intrinsic based
recipes.
(1) changes the semantics of the vector loop region, whereas (2) needs
to preserve them. This splits (2) out so we don't mix the two up, and
allows us to move (1) earlier in the pipeline in a future PR.
[NFC][Linalg] Add `matchConvolutionOpOfType` API and make `isaConvolutionOpOfType` API a wrapper (#174722)
-- This commit involves the following updates pertaining to
`isaConvolutionOpOfType` API :-
1. We don't want dilations/strides of convolution op to be returned as
pointer arguments to the API function - to tackle this we create a new
API `matchConvolutionOpOfType` which would return an optional struct of
dilations/stride.
2. To not break the original API's use case as a simple querying
functionality with true/false return - we keep `isaConvolutionOpOfType`
as a wrapper API which will invoke `matchConvolutionOpOfType` API and
return true/false depending on whether `matchConvolutionOpOfType` API
returned any value or not.
3. Dilations/strides of named convolution op are also populated now (it
was missed in the previous PRs while creating `isaConvolutionOpOfType`).
4. [Max/Min]UnsignedPool ops' body matcher now only matches unsigned int
ops (refer: https://github.com/llvm/llvm-project/pull/166070)
-- No tests are being added as all the above are NFC changes around the
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[MLIR][Bufferization] Fold LoadOp only when the buffer is read only (#172595)
When we `memref.load` from a buffer, it folded to `tensor.extract` even
when the buffer was writable, causing unexpected results. For example:
```mlir
func.func @load_after_write_from_buffer_cast(%arg0: index, %arg1: index,
%arg2: tensor<?x?xf32>) -> f32 {
%0 = bufferization.to_buffer %arg2 : tensor<?x?xf32> to memref<?x?xf32>
linalg.ceil ins(%0 : memref<?x?xf32>) outs(%0 : memref<?x?xf32>)
%1 = memref.load %0[%arg0, %arg1] : memref<?x?xf32>
return %1 : f32
}
```
would fold into
```mlir
module {
func.func @load_after_write_from_buffer_cast(%arg0: index, %arg1: index, %arg2: tensor<?x?xf32>) -> f32 {
%0 = bufferization.to_buffer %arg2 : tensor<?x?xf32> to memref<?x?xf32>
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[clang-repl] Use more precise search to find the orc runtime. (#175805)
The new mechanism relies on the path in the toolchain which should be
the autoritative answer. This patch tweaks the discovery of the orc
runtime from unittests where the resource directory is hard to deduce.
Should address the issue raised in #175435 and #175322
[RISCV][llvm] Support select codegen for P extension (#175741)
This is scalar condition with fixed vector true/false value, we can just
handle it same as scalars.
[RISCV][llvm] Support vselect codegen for P extension (#175744)
The only difference between vselect vs. select is condition value(a.k.a.
mask), we can select by using bitwise operation:
vselect(mask, true, false) = (mask & true) | (~mask & false)
[CodeGen][NPM] Add support for -print-regusage in New Pass Manager (#169761)
Support `-print-regusage` flag in NPM for printing register usage information
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_S_MUL_*
Patch 3 of 4 patches to implement full G_MUL support in regbanklegalize.
Current mul.ll test is only partially updated and expected to fail.
It will be updated in the fourth patch.
[AMDGPU] Fix the encoding of VOP3PX2 instructions
ISA spec says `SCALE_OPSEL[0:1]` determines which parts of S3 and S4 are used, and `SCALE_OPSEL_HI[0:1]` should be zero.
