[InferAS][NFC] Improve documentation for getAddrSpaceCastPreservedPtrMask (#185239)
Clarify the description of the preserved pointer bit mask and its
purpose in address space inference. Reformat the example for better
readability.
Co-authored-by: Yuanke Luo <ykluo at birentech.com>
[DA] Fix test case for the Weak Zero SIV tests (NFC) (#185555)
The IR does not match the pseudo code. The pseudo code is intentional,
so update the IR accordingly.
[clang] Adjust -pedantic-errors -WX/-Wno-error=X interaction (#184756)
While -Wno-long-long suppresses -pedantic-errors diagnostics in both GCC
and Clang, GCC -Wno-error=long-long emits warnings while Clang still
emits errors.
```
% echo 'long long x = 0;' | gcc -std=c89 -pedantic-errors -Wno-error=long-long -x c -fsyntax-only -
<stdin>:1:6: warning: ISO C90 does not support 'long long' [-Wlong-long]
% echo 'long long x = 0;' | clang -std=c89 -pedantic-errors -Wno-error=long-long -x c -fsyntax-only -
<stdin>:1:1: error: 'long long' is an extension when C99 mode is not enabled [-Werror,-Wlong-long]
1 | long long x = 0;
| ^
1 error generated.
```
The order of -pedantic-errors and -Wno-error=long-long does not matter.
Two fixes to how extension diagnostics interact with -pedantic-errors
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[HLSL] Add support for groupshared args (#181886)
Add support for groupshared args to HLSL.
Some support for template errors and warnings still needs to be added in
a follow up (tracked by #182535)
Closes #174472
[libunwind][PAC] Defang ptrauth's PC in valid CFI range abort
It turns out making the CFI check a release mode abort causes many,
if not the majority, of JITs to fail during unwinding as they do not
set up CFI sections for their generated code. As a result any JITs
that do nominally support unwinding (and catching) through their JIT
or assembly frames trip this abort.
rdar://170862047
[Clang] Track alloca element types to avoid getAllocatedType() calls (#181740)
Store alloca element types alongside alloca pointers in Clang's CodeGen,
eliminating the need to query getAllocatedType() later.
Changes:
- CodeGenFunction.h: Modified DominatingLLVMValue::saved_type to track
type Uses Type==nullptr as sentinel for "not saved" instead of separate
bool. Fixes a bug where it previously tried to use the addrspacecasted
value constructor and later cast it to an alloca.
- CGHLSLRuntime.cpp: Changed OutputSemantic map to store (Value*, Type*)
pairs to trivially remove getAllocatedType calls.
Co-authored-by: Claude Sonnet 4.5 <noreply at anthropic.com>
[DA] Fix overflows when calculating Delta in the Weak Zero SIV tests (#184997)
Add overflow checks when computing `Delta` in the Weak Zero SIV tests.
The tests bail out if we cannot prove that the `Delta` computation does
not overflow. These calculations are also moved later so that some
analyses that do not require these checks can run first.
Fix part of the test cases added in #164246.
Revert "AMDGPU: Annotate group size ABI loads with range metadata (#185420)" (#185521)
This reverts commit 76daf31b4000623d5c9548348a859ea3ed8712e1.
Bot failure.
[lld][MachO] Deduplicate branch-extension thunks for ICF-folded symbols (#185396)
After ICF, multiple symbols may resolve to the same address but remain
as distinct Symbol pointers. When used as keys in thunkMap, this caused
redundant branch-extension thunks to be created for the same target. Fix
this by providing a custom DenseMapInfo for thunkMap that hashes and
compares Defined symbols by (isec, value) instead of pointer identity.
[HLSL] Fix interleaved vector and matrix return types in AST dump (#184888)
HLSL vector and matrix types were previously printed with their closing
syntax (', N>') in 'printAfter', causing them to interleave with
function
parameters when used as return types (e.g., 'vector<float (args), 4>').
This change moves the HLSL vector and matrix closing syntax into
'printBefore' when 'UseHLSLTypes' is enabled, ensuring the type is
printed completely before the parameter list.
Note that address space qualifiers are now printed after the type
(e.g., 'vector<float, 4>hlsl_device'). This is because
'canPrefixQualifiers' in 'TypePrinter.cpp' returns false for these
types.
We cannot easily change this to check 'UseHLSLTypes' because
'canPrefixQualifiers' is a static method and does not have access to the
PrintingPolicy at that point.
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[NFC] Migrate NVPTX specific debug info code to separate class
This refactors the dwarf emission code to pull out the rest of the NVPTX specific code into it's own subclass for debug info handling and architecture specific differences.
Tested with ninja check-all on OSX.
[SPIR] Do not warn on 64-bit atomics (#185502)
Summary:
SPIR-V's Int64Atomics capability is not dependent on its addressing mode
as far as I am aware. These 32-bit SPIR targets already claim to support
the cl_khr_int64 atomics and we already emit 64-bit atomics in the
backend. Additionally, this is already accepted as a hack due to the
fact that the host will increase it in offloading usage. I do not see a
reason to keep these at 32, which causes numerous warnings inside of the
`libclc` build.
[libclc] Replace last of `opencl` atomics with `__scoped_` versions (#185515)
Summary:
These were the only uses of the old atomics. The old definition guards
stay as those prevent us from compiling the unsupported uintptr_t atomic
type on nvptx which does not define it. Could probably be improved
later.
[SelectionDAG] Use ExpandIntRes_CLMUL to expand vector CLMUL via narrower legal types (#184468)
Reuse the ExpandIntRes_CLMUL identity to expand vector
CLMUL/CLMULR/CLMULH on wider element types (vXi16, vXi32, vXi64) by
decomposing into half-element-width operations that eventually reach a
legal CLMUL type.
Three generic strategies in expandCLMUL:
1. Halve: halve element width (e.g. v8i16 -> v8i8 on AArch64)
2. promote to double : zext to wider type if CLMUL is legal there (e.g.
x86)
3. Count widen: pad with undef to double element count (e.g. v4i16 ->
v8i16)
A helper canNarrowCLMULToLegal() guides strategy selection and prevents
circular expansion in the CLMULH bitreverse path.
Also add Custom BITREVERSE lowering for v4i16/v8i16 on AArch64 using
REV16+RBIT, which the CLMULH expansion relies on.
Fixes #183768
[WebAssembly] Fold any/alltrue SIMD boolean reductions with eqz (#184704)
Existing ISel patterns match setne/seteq following SIMD boolean reductions
any_true and all_true, and drop the ones that are redundant (because the
reductions always return 1 or 0). This adds patterns to also produce eqz
instructions instead of a comparison with a const.
[flang-rt] Need to pad the output of execute_command_line(..., CMDMSG) (#185509)
Previously the error message was copied, but not padded for cases where
the message was shorter than the passed CMDMSG string. Add the padding
and also change the test case to test padding on all platforms.
