[ELF,SPARC] Handle TLS IE relocations (#213500)
An initial-exec reference loads the symbol's TP-relative offset from the
GOT and adds the thread pointer:
```
sethi %tie_hi22(sym), %o0 # R_SPARC_TLS_IE_HI22
add %o0, %tie_lo10(sym), %o0 # R_SPARC_TLS_IE_LO10
ldx [%l7 + %o0], %o0, %tie_ldx(sym) # R_SPARC_TLS_IE_LDX
add %g7, %o0, %o0, %tie_add(sym) # R_SPARC_TLS_IE_ADD
```
The sethi and add form the GOT offset. In an executable a
non-preemptible symbol is optimized to Local Exec, as GNU ld does: the
sethi holds the complement, the add becomes an xor, and the load becomes
a register move, or a nop when source and destination are the same. The
thread pointer add is unchanged.
Co-authored-by: Kirill A. Korinsky <kirill at korins.ky>
Co-authored-by: LemonBoy <thatlemon at gmail.com>
Co-authored-by: Alex Rønne Petersen <alex at alexrp.com>
[mlir][x86] Decouple Accumulator from ADD-Based Vector Contractions (over loops) (#204327)
This path transforms `vector.contract(A, B, Acc)` into
`vector.contract(A, B, 0) + Acc` to decouple the contraction computation
from the accumulator update for contractions over the loop.
[ELF,SPARC] Handle GOTDATA relocations (#213497)
A PIC data reference forms the symbol's GOT offset with
R_SPARC_GOTDATA_OP_HIX22 and R_SPARC_GOTDATA_OP_LOX10 and loads through
it, with R_SPARC_GOTDATA_OP marking the load:
```
sethi %gdop_hix22(sym), %g1
xor %g1, %gdop_lox10(sym), %g1
ldx [%l7 + %g1], %g1, %gdop(sym)
```
When the symbol is neither preemptible nor absolute, optimize the load
to `add %l7, %g1, %g1` over the symbol's GOT-relative address. An
absolute symbol keeps the GOT load, as it can be arbitrarily far from
.got and we don't want the X86_64::relaxOpt complexity.
Co-authored-by: Kirill A. Korinsky <kirill at korins.ky>
Co-authored-by: LemonBoy <thatlemon at gmail.com>
Co-authored-by: Alex Rønne Petersen <alex at alexrp.com>
[JITLink] Remove LTmp workaround now that LLVM requires C++17 (#213428)
C++17 guarantees the postfix-expression naming the called function is
sequenced before evaluation of its arguments, so
L->linkPhase1(std::move(L)) is well-formed without the LTmp indirection.
This should also be implemented by MSVC now. See here (P0145R3 and
P0400R0):
https://learn.microsoft.com/ar-sa/cpp/overview/visual-cpp-language-conformance?view=msvc-170
Disclaimer: As I have no LLVM Windows machine with MSVC at hand, I was
not able to test it myself.
Co-authored-by: Claude <noreply at anthropic.com>
[lldb] Reimplement PythonCallable::GetArgInfo without executing Python code (#213378)
`b05a5d0a` added an arity-trimming step to the shared
`ScriptedPythonInterface::Dispatch`: extensions are now allowed to
define methods with trailing parameters as optional
(`num_children(self)` vs. `num_children(self, max_count)`), so before
calling into a method, `Dispatch` needs to know how many positional
arguments it actually accepts and drop any trailing ones we'd otherwise
pass.
That check calls `PythonCallable::GetArgInfo`, which ran a whole
embedded Python script through `inspect.signature` on every call, since
every scripted-extension dispatch goes through it.
For the common case `GetArgInfo()` actually needs to handle fast (plain
Python functions/methods, classes used as constructors, and callable
instances defining `__call__`, i.e. everything `Dispatch<T>()` and
`CreatePluginObject()` ever pass it), the answer is available as plain
data attributes, with no Python bytecode execution required:
[15 lines not shown]
[AMDGPU] Support partial and empty WWM pools for SGPR spills
SGPR lane spilling currently treats the WWM VGPR pool as all-or-nothing. This
can fail compilation when the requested pool cannot be formed, even though
scratch spilling or a smaller spillable pool could make progress.
This PR lets ordinary SGPR spills fall back to scratch when the pool is empty
and lets WWM register allocation use a nonempty partial pool. It keeps the
full-pool requirement for strict WWM/WQM and explicit spill-carrier
preallocation.
The no-pool fallback is recorded in SIMachineFunctionInfo so frame lowering can
provide enough emergency scavenging slots. The state is also serialized to
preserve the behavior across MIR round trips.
[mlir-c] Add structural operation equivalence (#206537)
Exposes `OperationEquivalence` through the MLIR C API so callers can compare operations structurally rather than by handle identity.
Assisted by: Claude
[lld][MachO] Avoid quadratic iteration over already-folded symbols during ICF (#213339)
`ConcatInputSection::foldIdentical()` clears the folded functions
`originalUnwindEntry`.
However, it cleared every symbol: with N members, the repeated clearing
is **O(N²)**.
This is redundant: we should only remove the incoming `copy->symbols`.
This patch moves the removing loop ahead and adds more clear comments on
why we need to skip the first element.
Also added a new `lld/test/MachO/icf-scale-same-class.s` with 500K
identical functions as a stress test, which would've taken minutes to
link, and less than a second with the patch.
Testing on real-world app (IRPGO instrumentation + ICF) find that we
achieved a 19x speed up (1:14:42 -> 3:55)
clang/AMDGPU: Require 16-bit-insts for half typed image builtins
Typed image load/store operations with 16-bit elements require d16
support which was introduced in gfx8. They were previously gated only
on image-insts, so they were wrongly accepted on targets that have
images but lack 16-bit support (e.g. gfx700), where the backend then
fails to select.
Co-Authored-By: Claude (Opus 4.8) <noreply at anthropic.com>
clang/AMDGPU: Require 16-bit-insts for half typed buffer format builtins
Typed buffer format load/store operations with 16-bit elements require
d16 support which was introduced in gfx8. These builtins previously had
no required features at all, so they were accepted (and then crashed the
backend) on targets without 16-bit support.
Diagnose these in Sema, parallel to the image builtins. The manual
verification here suprised me. The automatic builtin feature verification
is enforced in codegen, which seems like a layering violation which
should be fixed.
Co-Authored-By: Claude (Opus 4.8) <noreply at anthropic.com>
clang: Replace Is*OffloadArch free functions with OffloadArch methods
Drop the IsNVIDIAOffloadArch/IsAMDOffloadArch/IsIntel*OffloadArch free
functions in favor of the OffloadArch member predicate functions.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[InstSimplify] Defer to ConstantFold in simplifyInstrinsic (#205061)
Defer to ConstantFolding on all-constant operands, in
llvm::simplifyIntrinsic. The patch adds a context-function argument to
ConstantFoldIntrinsic for strictfp information, which is used by a new
canConstantFoldIntrinsic under canConstantFoldCallTo: it was
necessitated by exposing the constant-folder via
llvm::simplifyIntrinsic. The patch only has impact on passes that use
simplifyIntrinsic via InstSimplifyFolder, other than InstCombine, which
already constant-folds intrinsics.
[libc] Fix LLVM_LIBC_FUNCTION on 32-bit x86 Windows (#213456)
Previously, trying to compile libm with LIBC_COPT_PUBLIC_PACKAGING
defined failed on 32-bit Windows with
error: alias must point to a defined variable or function
This is because 32-bit Windows adds a leading underscore to __cdecl C
functions, making the alias declaration not find its target symbol name.
The same problem exists on Apple platforms, which as solution don't emit
the alias for the C++ LIBC_NAMESPACE:: symbol.
Do the same on 32-bit Windows as on Apple platforms: Emit only
the underscore-prefixed symbol, not the LIBC_NAMESPACE:: alias.
[mlir][xegpu] Add xegpu.lane_shuffle op (#210777)
Add a lane-level XeGPU operation that re-distributes a subgroup's
fragments across its lanes without changing the element type.
The op takes a 1D vector — the fragment held by one lane — and returns a
fragment of the same type. A pack/unpack mode selects the direction:
viewing the subgroup as an S x N element grid (S = subgroup size, N =
elements per lane), pack moves element j of lane i from logical position
j*S + i to i*N + j, so a lane's elements end up at consecutive
positions; unpack is the reverse.
This implements xegpu.convert_layout semantics at the lane level when
lane_layout is unchanged but lane_data differs.
assisted-by-claude
---------
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
[IR] Truncate struct field offsets exceeding the pointer index width. (#213436)
Update accumulateConstantOffset and collectOffset to implicitly truncate
struct field offsets. This fixes crashes in the new tests, where the
field offset does not fit in the index width.
PR: https://github.com/llvm/llvm-project/pull/213436
