LLVM/project 83ff96dllvm/lib/Transforms/IPO Instrumentor.cpp, llvm/test/CodeGen/X86 atomic-load-store.ll

Merge branch 'main' into users/amara/fix-modulemap
DeltaFile
+996-0llvm/test/CodeGen/X86/atomic-load-store.ll
+280-0llvm/test/Instrumentation/Instrumentor/numeric.ll
+0-280llvm/test/Instrumentation/Instrumentor/operations.ll
+61-1llvm/lib/Transforms/IPO/Instrumentor.cpp
+23-21mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
+30-0llvm/test/Instrumentation/Instrumentor/numeric_config.json
+1,390-3024 files not shown
+1,410-34210 files

LLVM/project e7aff7bllvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Add aligned atomic vector store tests wider than 128 bits (NFC) (#202537)

These >128-bit stores are expanded to __atomic_store libcalls regardless
of alignment, since x86 caps atomic ops at 128 bits.
DeltaFile
+996-0llvm/test/CodeGen/X86/atomic-load-store.ll
+996-01 files

LLVM/project 3584126mlir/tools/mlir-tblgen AttrOrTypeFormatGen.cpp

[MLIR][ODS] Do not emit code when printing empty lists in Type/Attr assembly printer (NFC) (#201174)

In TableGen's code generator, `DefFormat::genCommaSeparatedPrinter` can
emit code like
```
void FooType::print(::mlir::AsmPrinter &odsPrinter) const {
  ::mlir::Builder odsBuilder(getContext());
  odsPrinter << "<";
  {
    bool _firstPrinted = true;
  }
  odsPrinter << ">";
}
```

This results in unused variable warnings for `_firstPrinted` when
compiling the table-gen'd code:
```
warning: unused variable '_firstPrinted' [-Wunused-variable]

    [7 lines not shown]
DeltaFile
+23-21mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
+23-211 files

LLVM/project bf4da3dllvm/include module.modulemap

[IR] Add BundleAttributes.def to modulemap as textual header

Fixes stage 2 builds broken by 88bd366041fd539d2e8d75f2b2ae081940922f8e
DeltaFile
+1-0llvm/include/module.modulemap
+1-01 files

LLVM/project 6a05e9bllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 vector-interleaved-store-i64-stride-6.ll vector-interleaved-store-i16-stride-6.ll

[SelectionDAG] Fold extracts of subvector inserts

Fold extract_subvector(insert_subvector(...)) when the extraction is
outside the inserted subvector or the inserted subvector only amends
the extracted

In particular,
1. vA extract_subvector (vB insert_subvector(vB X, vC Y, C1), C2) =>
vA extract_subvector(X, C2) when [C2, C2 + A) intersect [C1, C1 + C)
is the empty set
2. ... => extract_subvector(Y, C2 - C1) if [C2, C2 + Y) is a subset of
[C1, C1 + C) - an existing simplification
3. ... => vA insert_subvector(vA extract_subvector(vB X, C2), vC Y, C1 - C2)
if [C1, C1 + C) is a subset of [C2, C2 + A) - that is, if you're only
updating the extracted sub-part.

Adds a regresssion tests for an infinite SelectionDAG cycle that is
fixed by a stack of commits that ends with this one.


    [3 lines not shown]
DeltaFile
+72-56llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+44-48llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+27-7llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+15-17llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
+4-8llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
+4-8llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
+166-1446 files

LLVM/project 47ca5e8llvm/include/llvm/Transforms/IPO Instrumentor.h, llvm/lib/Transforms/IPO Instrumentor.cpp

[Instrumentor] Add instruction flags to NumericIO (#200709)
DeltaFile
+280-0llvm/test/Instrumentation/Instrumentor/numeric.ll
+0-280llvm/test/Instrumentation/Instrumentor/operations.ll
+61-1llvm/lib/Transforms/IPO/Instrumentor.cpp
+30-0llvm/test/Instrumentation/Instrumentor/numeric_config.json
+0-28llvm/test/Instrumentation/Instrumentor/operations.json
+12-8llvm/include/llvm/Transforms/IPO/Instrumentor.h
+383-3172 files not shown
+391-3218 files

LLVM/project f5c08d6utils/bazel/llvm-project-overlay/flang BUILD.bazel, utils/bazel/llvm-project-overlay/flang/include/flang/Optimizer/Dialect BUILD.bazel

[bazel] Added targets for flang, flang-rt, and openmp (#202791)

This change adds the necessary targets for a fortran toolchain. `flang`
for the compiler itself, `flang-rt` for executable support, and `openmp`
for `!$omp` directives within fortran code.
DeltaFile
+375-0utils/bazel/llvm-project-overlay/openmp/runtime/src/BUILD.bazel
+324-0utils/bazel/llvm-project-overlay/flang/unittests/BUILD.bazel
+268-0utils/bazel/llvm-project-overlay/flang/BUILD.bazel
+200-0utils/bazel/llvm-project-overlay/flang/include/flang/Optimizer/Dialect/BUILD.bazel
+114-0utils/bazel/llvm-project-overlay/flang/include/flang/Optimizer/HLFIR/BUILD.bazel
+108-0utils/bazel/llvm-project-overlay/flang/lib/Frontend/BUILD.bazel
+1,389-048 files not shown
+3,710-054 files

LLVM/project a80b840llvm/lib/Demangle DLangDemangle.cpp, llvm/unittests/Demangle DLangDemangleTest.cpp

[Demangle] Implement type D demangling and add all D basic type encodings (#202834)

This patch adds type name output to D demangler `parseType` and adds all
D basic type encodings to it.
DeltaFile
+138-10llvm/lib/Demangle/DLangDemangle.cpp
+37-12llvm/unittests/Demangle/DLangDemangleTest.cpp
+175-222 files

LLVM/project 662d9a8llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[AMDGPU] Validate WMMA scale/format combination

Only some combinations are listed as supported.

Fixes: https://github.com/ROCm/llvm-project/issues/2634
DeltaFile
+27-7llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+16-16llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
+16-16llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
+31-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+20-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
+122-513 files not shown
+152-519 files

LLVM/project 607250allvm/lib/Target/AMDGPU SIISelLowering.cpp

use decimal number rather than hex
DeltaFile
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-11 files

LLVM/project f0c60f5llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmin.ll llvm.amdgcn.reduce.fmax.ll

[AMDGPU] Support Wave Reduction intrinsics for half types

Supported Ops: `fmin`, `fmax`, `fadd`, `fsub`.
DeltaFile
+941-264llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+941-264llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+902-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+899-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+18-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+15-3llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+3,716-8566 files

LLVM/project 55611ddllvm/lib/Target/X86 X86ISelLoweringCall.cpp, llvm/test/CodeGen/X86 sibcall.ll musttail-tailcc.ll

[X86] Fix musttail miscompilation when arguments are passed on the stack (#199691)

After commit 782bf6a, a musttail call with matching CC was always
treated as a sibcall, which skips the stores of outgoing stack
arguments. Any non-forwarded stack argument was silently dropped.

Only treat musttail as a sibcall when every argument is in a register;
otherwise fall back to full tail-call lowering.

Fix #199224

---------

Co-authored-by: Reid Kleckner <rkleckner at nvidia.com>
DeltaFile
+78-0llvm/test/CodeGen/X86/sibcall.ll
+60-0llvm/test/CodeGen/X86/musttail-tailcc.ll
+11-13llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+6-8llvm/test/CodeGen/X86/hipe-cc64.ll
+3-0llvm/test/CodeGen/X86/swifttailcc-store-ret-address-aliasing-stack-slot.ll
+158-215 files

LLVM/project 1b4d60dlldb/include/lldb/Target StackFrameRecognizer.h

[lldb] Remove ValueObjectRecognizerSynthesizedValue::IsSynthetic override (#199117)

Removes the `IsSynthetic` override on
`ValueObjectRecognizerSynthesizedValue`. This class does not also
override `GetNonSyntheticValue`.

There was a bug in which code assumed that when `IsSynthetic()` returned
true, that `GetNonSyntheticValue` would produce a different value
object. However the default behavior of `GetNonSyntheticValue` is to
return itself.

It seems to me that either:
1. `ValueObjectSynthetic` should be the only class to override
`IsSynthetic` to true
2. or, that classes which override `IsSynthetic` should also override
`GetNonSyntheticValue`

In either case, I think it's best to remove this `IsSynthetic` on
`ValueObjectRecognizerSynthesizedValue`.
DeltaFile
+0-1lldb/include/lldb/Target/StackFrameRecognizer.h
+0-11 files

LLVM/project 3db1c77llvm/lib/Support SpecialCaseList.cpp

rebase

Created using spr 1.3.7
DeltaFile
+1-1llvm/lib/Support/SpecialCaseList.cpp
+1-11 files

LLVM/project 4098438llvm/lib/Support SpecialCaseList.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+1-1llvm/lib/Support/SpecialCaseList.cpp
+1-11 files

LLVM/project f29fbafllvm/lib/Support SpecialCaseList.cpp

rebase

Created using spr 1.3.7
DeltaFile
+1-1llvm/lib/Support/SpecialCaseList.cpp
+1-11 files

LLVM/project 4bd388allvm/lib/Support SpecialCaseList.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+1-1llvm/lib/Support/SpecialCaseList.cpp
+1-11 files

LLVM/project c5da536llvm/lib/Support SpecialCaseList.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+19-12llvm/lib/Support/SpecialCaseList.cpp
+19-121 files

LLVM/project 136a1b0llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

Remove redundant test
DeltaFile
+1-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+1-21 files

LLVM/project e664b2fllvm/include/llvm/Support circular_raw_ostream.h, llvm/test/CodeGen/AMDGPU sdiv64.ll srem64.ll

rebase

Created using spr 1.3.7
DeltaFile
+534-280llvm/test/CodeGen/AMDGPU/sdiv64.ll
+413-292llvm/test/CodeGen/AMDGPU/srem64.ll
+218-56llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+249-11mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+235-0mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
+113-115llvm/include/llvm/Support/circular_raw_ostream.h
+1,762-75473 files not shown
+3,343-1,45679 files

LLVM/project eb27cc6llvm/include/llvm/Support circular_raw_ostream.h, llvm/test/CodeGen/AMDGPU sdiv64.ll srem64.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+534-280llvm/test/CodeGen/AMDGPU/sdiv64.ll
+413-292llvm/test/CodeGen/AMDGPU/srem64.ll
+218-56llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+249-11mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+235-0mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
+113-115llvm/include/llvm/Support/circular_raw_ostream.h
+1,762-75473 files not shown
+3,360-1,46379 files

LLVM/project 178831bllvm/lib/Support SpecialCaseList.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+26-14llvm/lib/Support/SpecialCaseList.cpp
+26-141 files

LLVM/project 0ab940dllvm/lib/Support SpecialCaseList.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+19-12llvm/lib/Support/SpecialCaseList.cpp
+19-121 files

LLVM/project a125f09llvm/lib/Support SpecialCaseList.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+19-12llvm/lib/Support/SpecialCaseList.cpp
+19-121 files

LLVM/project 07046d7llvm/lib/Target/AArch64/MCTargetDesc AArch64MCLFIRewriter.cpp, llvm/test/CodeGen/AMDGPU bf16.ll sdiv64.ll

Merge branch 'main' into users/krzysz00/insert-concat-dagcombine
DeltaFile
+992-904llvm/test/CodeGen/AMDGPU/bf16.ll
+742-742llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+534-280llvm/test/CodeGen/AMDGPU/sdiv64.ll
+413-292llvm/test/CodeGen/AMDGPU/srem64.ll
+650-0llvm/test/MC/AArch64/LFI/simd.s
+542-1llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCLFIRewriter.cpp
+3,873-2,21995 files not shown
+9,117-4,372101 files

LLVM/project 0e8cdadllvm/test/CodeGen/AArch64 sve-fixed-vector-lrint.ll sve-fixed-vector-llrint.ll, llvm/test/CodeGen/AMDGPU bf16.ll

[SelectionDAG] Fold extracts spanning concat operands (#200936)

Factor the extract_subvector-of-CONCAT_VECTORS logic and handle
extracts that cover multiple whole concat operands by rebuilding a
smaller concat directly.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>

---------

Co-authored-by: OpenAI Codex <codex at openai.com>
DeltaFile
+992-904llvm/test/CodeGen/AMDGPU/bf16.ll
+742-742llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+187-229llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+187-229llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+196-176llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
+142-140llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+2,446-2,42013 files not shown
+2,940-3,03919 files

LLVM/project 1579432llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine copysign.ll

[InstCombine] Fold copysign(floor(fabs(X)), X) to trunc(X) (#200836)

Fixes #200519.

Adds an InstCombine fold for the pattern `copysign(floor(fabs(X)), X)
--> trunc(X)`.
DeltaFile
+119-0llvm/test/Transforms/InstCombine/copysign.ll
+12-0llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+131-02 files

LLVM/project 5dccbf9llvm/test/CodeGen/RISCV clmul.ll clmulr.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll clmul-sdnode.ll

Merge branch 'main' into users/krzysz00/insert-concat-dagcombine
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+10,281-12,374llvm/test/CodeGen/RISCV/clmulh.ll
+8,361-8,920llvm/test/CodeGen/RISCV/rvv/expandload.ll
+109,084-164,3692,340 files not shown
+298,552-310,2652,346 files

LLVM/project 72afc58llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Strip LogicalAnd from live-in-folder (NFC) (#202934)

The various simplifications performed in simplifyRecipe subsume it.
DeltaFile
+0-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-31 files

LLVM/project ab602d3llvm/test/MC/RISCV rv32c-invalid.s xqcibm-invalid.s

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+112-57llvm/test/MC/RISCV/rv32c-invalid.s
+44-23llvm/test/MC/RISCV/xqcibm-invalid.s
+36-19llvm/test/MC/RISCV/rv64c-invalid.s
+20-11llvm/test/MC/RISCV/rvc-hints-invalid.s
+212-1104 files