[mlir][func] Fix a crash in DuplicateFunctionEliminationPass (#209667)
Previously, we used `SymbolUserMap::replaceAllUsesWith` to replace
symbols, but this could not update the symbol table cached by
`SymbolUserMap` during traversal, leading to a crash. This PR switches
to `SymbolTable::replaceAllSymbolUses`, which always operates on the
latest symbol table and avoids the crash. Fixes #209648.
[libc][cmake] Enable assertions and Werror for baremetal builds (#214093)
Enable LLVM_ENABLE_ASSERTIONS and LLVM_ENABLE_WERROR in
baremetal_common.cmake
to ensure pre-merge checks catch assertion failures and compiler
warnings for
baremetal targets.
Assisted-by: Gemini
Add PISA register file, instruction set, and MC layer
Add the PISA register file and register-bank descriptions, the instruction
formats and definitions, and the MC/assembly layer (instruction printer,
register and code encoders, target streamer, MC target description and the
supporting enums), replacing the stub descriptions from
the initial target skeleton.
This provides the instruction-set description and assembly-emission
foundation. The GlobalISel lowering and instruction selection that consume it
are added in the following changes.
[clang][StaticAnalyzer] Add support for variables and fields in GetEnclosingDeclContextSignature
Function `getIssueHash` relies on the name of the enclosing
declaration of the issue Decl for hashing. But the underlying
function `GetEnclosingDeclContextSignature` does not compute the
enclosing declaration for variables or fields, causing missing HTML
reports despite text warnings being printed.
The added
`clang/test/Analysis/Checkers/WebKit/html-diag-dedup-members.cpp`
example is a reproducer of this kind of issue we observed in WebKit.
Also, `RawPtrRefLocalVarsChecker` and `RawPtrRefMemberChecker` never
called `Report->setDeclWithIssue()`. This commit fixes it.
rdar://183700416
Assisted-by: Claude sonnet
[CIR] Change previous coroutine builtins to have their own coro intrinsic ops (#211699)
This PR introduces dedicated CIR operations for the coroutine intrinsics
(`coro.intrinsic.id`, `coro.intrinsic.alloc`, `coro.intrinsic.begin`,
`coro.intrinsic.free`, `coro.intrinsic.end`, `coro.intrinsic.size`)
instead of emitting them as calls to hand-created builtin functions.
LLVM IR already has its own dedicated ops for these cases, so this
follows the same pattern at CIR.
Along the way this also changes how coroutine builtins are handled in
`CIRGenBuiltin`: previously the intrinsics emitted automatically as part
of lowering `EmitCoroutineBody` and the ones triggered by an explicit
`__builtin_coro_*` call written in user source code were going through
the same path. This PR separates the two, since they're conceptually
different emission points.
New tests covering these builtins are included as well.
Also added explicit `errorNYI` messages for the remaining
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[AMDGPU][GlobalISel] Use single B32 rule for permlane16
B32 already covers s32, <2 x s16> and 32-bit pointers, so one StandardB
fast rule replaces the separate S32, V2S16 and DivPtr32 rules. This
matches permlane_bcast/up/down/xor and permlane64, which have the same
overloaded intrinsic shape.
Change-Id: I770a93d5e75e68df704e84d7ad165fdd2cf2fc53
Add PISA target registration and backend stub
Register the Intel GPU portable ISA (PISA) target. Add the pisa Triple
arch, data layout, and a minimal MC/TargetMachine skeleton.
[RISCV] coalesce between VSETVLI and SF_VSETTNT (#203438)
When twiden != 0, LMUL, tail policy, and mask policy from the user are
ignored. The tail policy and mask policy are always treated as agnostic.
The normal RVV instruction will ignore the twiden parameter. This
observation could allow the RVV instruction and xsfmm instruction to
share the same configuration instruction.
We need to make sure the AVL, SEW, and AltFmt is same between VSETVL and
VSETVLTN.
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
[lldb] Step past a prologue the pc is inside (#213555)
A step into a function ran past its prologue only when the pc was
exactly the function's first address. A target whose entry point is not
a function's first address (such as WebAssembly) is entered past it.
This means that the check took every such call for one whose prologue
had already run, and the step stopped on the opening brace instead of
the first statement.
What says the prologue has yet to run is the pc being inside it, which
for a target that does enter at the first address is the condition that
was there before.
[AArch64][GlobalISel] Use a concrete type for store merging. (#213740)
This is just to reduce the number of scalar types in the MIR, as the
value is between a constant and a store it should have little effect.
[CIR] Move array-ctor cleanup to properly cleanup temporaries (#213993)
This patch came out of self-build, any constructor temporary called
during the construction of an array element was being improperly cleaned
up (actually, no terminator?). This patch moves the RunCleanups RAII to
do so immediately in the body.
The OGCG/LLVM check lines are effectively equal, except OGCG uses a PHI
and we are doing so with an iterator loop, but the 'dtor called
immediately' is still correct.
[CIR] Reject a global carrying a function type (#214065)
The verifier was accepting a `cir.global` whose `sym_type` is a
function. The LLVM dialect global takes one too, so it survives to LLVM
IR translation and crashes instead of reporting an error.
`GlobalOp::verify()` now rejects it.
[AMDGPU] Skip s_delay_alu for gfx1250 WMMA C-reuse chains
Consecutive gfx1250 WMMA/SWMMAC ops accumulating into the same matrix C
register reuse the accumulator in place, so the tied srcC read is
omitted and no delay is needed. AMDGPUInsertDelayAlu did not model this
and emitted an s_delay_alu that stalls the reuse chain.
Detect a C-reuse edge (tied srcC overlaps the previous XDL WMMA's dest,
with no intervening instruction) and skip the delay for that operand.
The change is state-neutral and safe, since GFX12+ interlocks the
matrix C hazard in hardware.
[SelectionDAG] Split masked div/rem operands with illegal masks (#214058)
PR description written by Codex
Split masked signed and unsigned division/remainder alongside illegal
vector masks to fix NVPTX SelectionDAG crashes. Covers all four
intrinsics and the original eight-lane reproducer; five focused LLVM
tests pass.
[OpenMP] Propagate PRESENT to pointee entries in mapper codegen (#210214)
For cases like:
```c
#pragma omp declare_mapper (default: S s) map(s.x, s.p[0:10])
S s1;
...
#pragma omp target_enter_data map(present, alloc: s1)
```
After "mapper-expansion", the behavior of the above should be equivalent
to:
```
#pragma omp target_enter_data map(present, alloc: s1.x) map(present, alloc: s.p[0:10])
```
i.e. The `present` map-type needs to be propagated to the map for the
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[NFC][BoundsSafety] Give `counted_by_or_null`, `sized_by`, and `sized_by_or_null` their own documentation (#212877)
Previously the `counted_by`, `counted_by_or_null`, `sized_by`, and
`sized_by_or_null` attributes all pointed at a single `Documentation`
object (`CountedByDocs`). The generated `AttributeReference.rst`
therefore folded all four into one entry whose text described only
`counted_by` used on a C99 flexible array member.
This was misleading because the attributes differ in important ways that
went undocumented:
* `counted_by` counts *elements* whereas `sized_by` counts *bytes*.
* `counted_by` and `sized_by` require a null pointer to have a zero
count/size, while the `_or_null` variants allow a null pointer
regardless of the count or size.
* `counted_by` may be applied to a flexible array member, but
`sized_by`, `counted_by_or_null`, and `sized_by_or_null` apply to
pointers only.
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