LLVM/project 6e94aea — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

[RISCV][P-ext] Use nsrl to for 64-bit extract_vector_elt with variable index on RV32.
DeltaFile
+6-30llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+21-6llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+27-362 files

LLVM/project 6f6aae5 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

[RISCV][P-ext] Fix crash on v2i32 extract_vector_elt with a variable index on RV32.

Assisted-by: Claude
DeltaFile
+63-39llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+6-3llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+69-422 files

LLVM/project d18f304 — llvm/test/CodeGen/RISCV rvp-simd-32.ll rvp-simd-64.ll

[RISCV][P-ext] Add tests for extractelement with a variable index. NFC

Assisted-by: Claude
DeltaFile
+109-61llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+36-4llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+145-652 files

LLVM/project 0a88893 — llvm/lib/Target/RISCV RISCVInstrInfoP.td RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

[RISCV][P-ext] Make v2i32 insert_vector_elt with constant indices legal for RV32.

We can select to an insert_subreg.

The default lowering created a store+load to stack that got folded,
but left behind the stack slot allocation.

Assisted-by: Claude
DeltaFile
+73-47llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+6-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+5-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+84-473 files

LLVM/project 4847ba4 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-32.ll rvp-simd-64.ll

[RISCV][P-ext] Lower 2 element insert_vector_elt to scalar_to_vec+ppaire/ppaireo.

This avoids needing to match the srl+build_vec later which we only
do on RV64.
DeltaFile
+9-14llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-4llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+1-2llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+12-203 files

LLVM/project 25b1d2f — cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

fixup! Update test expectation
DeltaFile
+1-1cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+1-11 files

LLVM/project c628d63 — llvm/lib/Target/RISCV RISCVInstrInfoXSpacemiT.td

[RISCV] Add SMT_ prefix to SpacemiT instruction enum names. (#241053)

Add "vtype" to end of names that become ambiguous. This represents the
additional operand the VMADOT II instructions have.
DeltaFile
+14-14llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td
+14-141 files

LLVM/project c01e243 — llvm/test/CodeGen/BPF adjust-opt-icmp7.ll

[BPF] Regenerate adjust-opt-icmp7.ll checks after #237690 (#241074)

#231257 added this test with checks generated before #237690 started
marking global functions noipa, so it fails on main.

cc @eaeltsin

Assisted-by: Claude Opus 5.5
DeltaFile
+1-1llvm/test/CodeGen/BPF/adjust-opt-icmp7.ll
+1-11 files

LLVM/project 9485b09 — clang/include/clang/CIR/Dialect/IR CIRAttrs.td, clang/test/CIR/CodeGenSYCL sycl-kernel-entry-point-exceptions.cpp

Merge branch 'main' into revert-238985-amdgpu-exec-copy-clobber
DeltaFile
+482-0llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ve.ll
+222-0llvm/test/Transforms/SLPVectorizer/AMDGPU/latency-bound-data-movement.ll
+158-0clang/test/CIR/CodeGenSYCL/sycl-kernel-entry-point-exceptions.cpp
+15-13clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+27-0llvm/test/Transforms/InstCombine/VE/libcall-arg-exts.ll
+10-2libc/test/UnitTest/FPMatcher.h
+914-1517 files not shown
+965-4123 files

LLVM/project 2c4a14f — llvm/test/CodeGen/X86/apx reloc-opt.ll

[X86][APX] Test the relocation of an NF add

test_regclass_not_updated_by_regalloc_2 only produced an NDD/NF add
with a GOT operand because the allocator happened to give the add a
destination different from its source. With SlotIndexes compaction it
picks the same register, so the add is compressed to the legacy form
and the CODE_6 TODO lost its test.

Add a function whose add keeps its source live, so it stays NDD and
becomes NF under any allocation.
DeltaFile
+20-1llvm/test/CodeGen/X86/apx/reloc-opt.ll
+20-11 files

LLVM/project 4553b4f — llvm/test/CodeGen/X86 vector-interleaved-store-i64-stride-7.ll vector-deinterleave8-i64.ll

[X86] Enable SlotIndexes compaction by default

Compacting SlotIndexes before greedy allocation drops the entries of
erased instructions, so live range sizes and instruction distances
reflect the code being allocated rather than how much was erased
before it. AMDGPU has done this since #235806; do the same for X86.

Codegen changes only through allocation: no new crashes, verifier
errors or allocation failures in the lit suites, including
EXPENSIVE_CHECKS, and a stage-2 build of LLVM, clang and lld with
-verify-machineinstrs passes its own tests. On llvm-test-suite at -O3,
spills drop 0.3% and .text 0.06%, with compile time unchanged.

Most test updates are regenerated checks. misched-matmul now inserts
20 spills instead of 24. live-debug-vars-stale-slotindexes.mir gets
one more use of %27 so that accumulate_fit still reaches the stale
index path it was written for.
DeltaFile
+20,796-20,889llvm/test/CodeGen/X86/vector-interleave7-i16.ll
+17,854-17,989llvm/test/CodeGen/X86/vector-interleave7-i32.ll
+17,166-17,229llvm/test/CodeGen/X86/vector-interleave6-i16.ll
+15,403-15,465llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+13,897-13,898llvm/test/CodeGen/X86/vector-deinterleave8-i64.ll
+13,329-13,243llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+98,445-98,713503 files not shown
+675,135-677,689509 files

LLVM/project 69ba8a3 — clang/include/clang/CIR/Dialect/IR CIRAttrs.td, clang/test/CIR/CodeGenSYCL sycl-lowering-lang-options.cpp

[CIR][SYCL] Emit sycl_in_device field to the for cir.lowering_options (#238117)

Add sycl_is_device field to the `cir.lowering_options`. This is
populated during CIRGen time from `langOpts.SYCLIsDevice`.
DeltaFile
+15-13clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+12-0clang/test/CIR/CodeGenSYCL/sycl-lowering-lang-options.cpp
+4-4clang/test/CIR/Transforms/abi-lowering/indirect-aliased.cir
+4-4clang/test/CIR/Transforms/abi-lowering/amdgpu-kernel-hip-ptr.cir
+4-4clang/test/CIR/Lowering/no-trapping-math-ssp-buffer-size.cir
+4-2clang/test/CIR/IR/lowering-lang-options.cir
+43-274 files not shown
+48-2910 files

LLVM/project ad36cf3 — clang/test/CIR/CodeGenSYCL sycl-kernel-entry-point-exceptions.cpp, clang/test/CodeGenSYCL address-space-mangling.cpp function-attrs.cpp

[CIR][SYCL][NFC] Port some CodeGenSYCL tests from clang to CIR CodeGen (#236512)

Ports some SYCL CodeGen tests from clang to CIR CodeGen.
DeltaFile
+158-0clang/test/CIR/CodeGenSYCL/sycl-kernel-entry-point-exceptions.cpp
+2-7clang/test/CodeGenSYCL/function-attrs.cpp
+4-0clang/test/CodeGenSYCL/address-space-mangling.cpp
+164-73 files

LLVM/project 9345ffc — lld/Common Utils.cpp

[lld] Add a fast path to lld::utils::getRootSymbol() (#240407)

StringRef::rsplit() calls StringRef::rfind(), which calls
string_view::rfind(), which is a naive reverse loop at least in libc++.

Most symbols don't contain `.` characters, so quickly check for that
(which uses an optimzied string search, which is much faster).

(We could instead revert 2f851f26ead0ea and move StringRef::rfind() back
to its own impl and then do something like 4d681d7dc49 / 233edd20a774bbc
to make it faster, but it seems there's a desire to make StringRef
*more* like string_view over time. And also, using that all args we pass
to it here contain a `.` is a real higher-level optimization.)

This code is hot in ld64.lld when using -order_file.

Reduces link time of a release static symbol_level=1 aarch64 Chromium
Framework link from 4.533 s ± 0.017 s to 4.252 s ± 0.045 s, a ~6%
reduction.

    [3 lines not shown]
DeltaFile
+3-0lld/Common/Utils.cpp
+3-01 files

LLVM/project 6fe51fa — llvm/test/Transforms/SLPVectorizer/AMDGPU latency-bound-data-movement.ll

[SLP][AMDGPU][NFC] Add a test of FP chains in short blocks (#241014)

Chained complex multiplies in a short block, in a loop, after a loop and
across a branch, on gfx942. SLP keeps all of them scalar today.
DeltaFile
+222-0llvm/test/Transforms/SLPVectorizer/AMDGPU/latency-bound-data-movement.ll
+222-01 files

LLVM/project 2012a84 — libc/test/UnitTest ErrnoSetterMatcher.h FPMatcher.h, libc/test/src/stdio CMakeLists.txt snprintf_test.cpp

[libc][test] Guard custom matchers with LIBC_TEST_HAS_MATCHERS() (#241062)

Commit 528affb94ef8 (#240616) updated ErrnoSetterMatcher and FPMatcher
to
inherit from Matcher<T> and accept MatchResultListener * without
guarding
the matcher definitions on LIBC_TEST_HAS_MATCHERS(). Downstream test
frameworks that do not support matchers (such as Fuchsia's zxtest and
Pigweed's light pw_unit_test) fail to compile headers that transitively
include FPMatcher.h for FPTest or DECLARE_SPECIAL_CONSTANTS (e.g.
stdfix/ExpTest.h) or include ErrnoSetterMatcher.h.

Guard the matcher classes, factory helpers, and EXPECT_THAT/ASSERT_THAT
macros in ErrnoSetterMatcher.h and FPMatcher.h with
LIBC_TEST_HAS_MATCHERS(), keeping FPTest, DECLARE_SPECIAL_CONSTANTS, and
non-matcher rounding helpers unconditionally available, and replace the
unused ErrnoSetterMatcher.h include in snprintf_test.cpp with direct
CPP/limits.h.


    [2 lines not shown]
DeltaFile
+10-2libc/test/UnitTest/FPMatcher.h
+4-0libc/test/UnitTest/ErrnoSetterMatcher.h
+1-1libc/test/src/stdio/snprintf_test.cpp
+1-0utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
+1-0libc/test/src/stdio/CMakeLists.txt
+17-35 files

LLVM/project bf649b5 — llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination sadd-with-overflow.ll minmax.ll

[ConstraintElim] Split signed min/max across their operands when checking a compare

The existing constraint systems only record the bounds that hold for both
operands of a min/max (smax(a, b) >= a and >= b, smin(a, b) <= a and <= b). The
other direction is a disjunction, which cannot be recorded as a fact. When a
compare of signed decompositions involves a min/max result, split it into its
operands: the decomposition is monotonic in that result, so it is the max or min
of its values on each side, and the relation holds for all or for either side
respectively.

https://alive2.llvm.org/ce/z/zsGkJ-
DeltaFile
+366-3llvm/test/Transforms/ConstraintElimination/minmax.ll
+111-0llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+4-8llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+481-113 files

LLVM/project ff17097 — llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination ssub-with-overflow.ll sadd-with-overflow.ll

[ConstraintElim] Prove sadd/ssub.with.overflow cannot overflow from the exact sum

Decompose the operands and show that the sum lies in the range of the type. This
handles patterns like A + (B - A), as well as sums involving signed min/max
results, which are split across their respective operands using monotonicity
(for example start + smax(end - start - 1, 0) <= end).

https://alive2.llvm.org/ce/z/ze8LCk
DeltaFile
+634-0llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+159-3llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+100-0llvm/test/Transforms/ConstraintElimination/ssub-with-overflow.ll
+893-33 files

LLVM/project 1a00cfc — llvm/lib/Transforms/Scalar ConstraintElimination.cpp

cache known bits for opposite signs check
DeltaFile
+13-10llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+13-101 files

LLVM/project 705a74f — llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination add-nsw.ll sadd-with-overflow.ll

[ConstraintElim] A signed sum of operands with opposite signs cannot wrap

If one operand is known non-negative and the other non-positive, the signed
sum is between them, so it cannot overflow.

https://alive2.llvm.org/ce/z/ZF5Yqr
DeltaFile
+62-0llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+19-0llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+3-6llvm/test/Transforms/ConstraintElimination/add-nsw.ll
+84-63 files

LLVM/project e14a09a — llvm/lib/IR RuntimeLibcalls.cpp, llvm/test/Transforms/InstCombine/VE libcall-arg-exts.ll

[RuntimeLibcalls] Extend i32 libcall arguments and returns on VE (#240638)

clang adds `sign-/zeroext` attributes to `int`/`unsigned` for VE.
Libcalls synthesized by the compiler lacked the those attributes.

Assisted-by: Claude
DeltaFile
+482-0llvm/test/Transforms/Util/DeclareRuntimeLibcalls/ve.ll
+27-0llvm/test/Transforms/InstCombine/VE/libcall-arg-exts.ll
+2-2llvm/lib/IR/RuntimeLibcalls.cpp
+511-23 files

LLVM/project 9ab58bd — llvm/lib/Target/AMDGPU SIOptimizeExecMaskingPreRA.cpp, llvm/test/CodeGen/AMDGPU wqm.ll optimize-exec-mask-pre-ra-exec-clobber.mir

Revert "[AMDGPU] Preserve exec copies across intervening EXEC writes (#238985)"

This reverts commit 31b9c42ab4beceeba5dfd44e30f94e805f33d6df.
DeltaFile
+0-44llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-exec-clobber.mir
+1-19llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+2-4llvm/test/CodeGen/AMDGPU/wqm.ll
+3-673 files

LLVM/project db0a0e8 — llvm/lib/Target/Hexagon HexagonDepMappings.td, llvm/test/MC/Hexagon LX_mux_h_alt.s

[Hexagon] Add assembly mapping for LX_mux_h_alt (#241036)

Map the alternate conditional syntax to LX_mux_h while preserving the
operand order.

Co-authored-by: Alexey Karyakin <akaryaki at quicinc.com>
DeltaFile
+8-0llvm/test/MC/Hexagon/LX_mux_h_alt.s
+1-0llvm/lib/Target/Hexagon/HexagonDepMappings.td
+9-02 files

LLVM/project fa9cded — clang/docs ReleaseNotes.md, clang/lib/Basic/Targets MSP430.h

[MSP430] Fix the underlying type of wint_t (#240972)

This is a minor ABI change since the behavior can only be observed when
extending `wint_t` to a wider type.
DeltaFile
+2-2clang/test/Preprocessor/stdint.c
+1-1clang/test/Preprocessor/init.c
+2-0clang/docs/ReleaseNotes.md
+1-0clang/lib/Basic/Targets/MSP430.h
+6-34 files

LLVM/project 6fd18a3 — llvm/lib/Target/Xtensa/AsmParser XtensaAsmParser.cpp, llvm/test/MC/Xtensa xtensa-esp32s3-invalid.s xtensa-esp32s3-valid.s

[Xtensa] Fix upper bound for ESP32-S3 select immediate (#235130)

Fix off-by-one in the isSelect_16() so it only accepts [0, 15]
DeltaFile
+4-0llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s
+3-0llvm/test/MC/Xtensa/xtensa-esp32s3-invalid.s
+1-1llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
+8-13 files

LLVM/project a349e7a — llvm/lib/Target/Xtensa XtensaOperands.td

[Xtensa][NFC] Fix immediate operand predicates (#235122)

Correct operator precedence in alignment checks and add the missing
four-byte alignment constraint to imm64n_4n.

These don't seem to be currently used by any selection pattern, so there
is no functional change.
DeltaFile
+13-11llvm/lib/Target/Xtensa/XtensaOperands.td
+13-111 files

LLVM/project 4a444cb — clang/lib/Sema SemaTemplateDeductionGuide.cpp, clang/test/SemaCXX cxx20-ctad-type-alias.cpp

[Clang] Fix nullptr dereference in getRHSTemplateDeclAndArgs (#240754)

The RHS could be a non-dependent type alias, and thus they are not
always TemplateSpecializationType.

This addresses
https://github.com/llvm/llvm-project/pull/147675#discussion_r4487870799
DeltaFile
+34-0clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
+3-2clang/lib/Sema/SemaTemplateDeductionGuide.cpp
+37-22 files

LLVM/project 6ec24b3 — llvm/lib/Target/DirectX DXIL.td, llvm/test/CodeGen/DirectX debugbreak.ll

[DirectX] Add dx.op.debugBreakLower llvm.debugtrap to dx.op.debugBreak

Fixes #231271
DeltaFile
+18-0llvm/test/CodeGen/DirectX/debugbreak.ll
+10-1llvm/lib/Target/DirectX/DXIL.td
+28-12 files

LLVM/project 399e993 — llvm/include/llvm/IR RuntimeLibcallsImpl.td RuntimeLibcalls.td, llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Move sqrt attributes to TableGen (#240726)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-20llvm/lib/IR/RuntimeLibcalls.cpp
+11-1llvm/include/llvm/IR/RuntimeLibcalls.td
+7-2llvm/include/llvm/IR/RuntimeLibcallsImpl.td
+4-4llvm/test/Transforms/Util/DeclareRuntimeLibcalls/hexagon.ll
+3-3llvm/test/Transforms/Util/DeclareRuntimeLibcalls/systemz.ll
+3-2llvm/test/Transforms/Util/DeclareRuntimeLibcalls/arm64ec.ll
+28-326 files

LLVM/project c5fd86d — clang/lib/Driver/ToolChains HLSL.cpp, clang/unittests/Driver DXCModeTest.cpp

[HLSL] Add Shader Model 6.10 and DXIL version 1.10 to the target triple
DeltaFile
+13-0llvm/unittests/TargetParser/TripleTest.cpp
+7-2llvm/lib/TargetParser/Triple.cpp
+5-1clang/unittests/Driver/DXCModeTest.cpp
+2-1llvm/include/llvm/TargetParser/Triple.h
+3-0clang/lib/Driver/ToolChains/HLSL.cpp
+30-45 files