Revert "[Codegen] Replace any_of with is_contained. NFC (#212289)" (#212794)
This reverts commit 52f6c88c2c1b6f0c10b9c8fb09ec35e147c593e3 due to
errors in the C++20 builder.
It does not revert the followup from #212711.
[OpenMP] Fix ambiguous namespace lookup with delayed template parsing (#212720)
Running `check-llvm` on Windows fails while compiling LLVMFrontendTests
with the following error:
error: reference to 'detail' is ambiguous
Clang enables delayed template parsing by default when targeting the
MSVC ABI on Windows. When ConstructDecompositionT is instantiated after
a using-directive for `llvm::omp`, both `::detail` and
`llvm::omp::detail` are
visible, making `detail::find_unique` ambiguous.
Explicitly qualify find_unique with the global namespace. This fixes
check-llvm on Windows and other environments using
-fdelayed-template-parsing, without changing behavior.
[AMDGPU][NFC] Add previously failing bitop3 tests. (#212335)
The following two expressions used to return the wrong truth table for
v_bitop3:
; ((b & T) | T) & ~T, where T = a & c
; U ^ (~U | T), where T = c ^ b and U = (T | a) & T
The fix was implemented in:
https://github.com/llvm/llvm-project/pull/198556
Assisted-by: Cursor (Claude)
[RISC-V] Fix assert after 255162a (#212791)
The iterator passed-in may point to the end of the block which causes an
assertion failure when attempting to inspect the MI it points to. Guard
against this.
[AMDGPU] Handle True16 high-half 16-bit packing idiom with uniform operand (#211102)
With True16 instructions, the high-half packing idiom from #206058 tries
to `OR` a 16-bit VGPR operand into the high half of the other operand,
but this causes a crash if the other operand is uniform, as this
generates an invalid `$sgpr = COPY $sgpr_hi16`.
[LoopIdiom] Use SCEV for deciding memmove validity (#211274)
When the loop index variable is smaller than the GEP offset size, and is
thus sign or zero extended before being used, then the IR that is
expanded from the SCEV expressions for the load and store locations will
be in a form that means GetPointerBaseWithConstantOffset can't deduce
the base and offset, meaning we can't generate memmove.
Solve this by deciding memmove validity based on the SCEV expressions
instead of the IR that is expanded from them. This means we also need to
insert a check to handle a null base pointer, as that was previously
handled implicitly due to how SCEVExpander expands expressions involving
null pointers.
[LLDB] Remove Xcode sdk guessing from Makefile.rules (NFC) (#212378)
This cleanup patch pushes the auto-detection of the `macosx` SDK from
Makefile.rules up into `dotest.py` and unifies it with the existing SDK
handling for other Apple platforms.
Assisted-by: claude
[AArch64][CostModel] Lower wide fixed-length vector reductions cost (#211824)
When vscale is known > 1, SVE will be used to perform most reductions.
This should be reflected in the cost model.
[lldb][Windows] Check for EOF before the ctrl-c retry in GetLine (#212745)
On Windows `lldb --repl` can hang forever instead of exiting at EOF.
`IOHandlerEditline::GetLine` checks `GetLastError() ==
ERROR_OPERATION_ABORTED` and does a `continue` before checking `feof`.
However `fgets` is a CRT function and does not set the Win32 last error
value, so the `GetLastError` read is not the expected error. When it
happens to be `ERROR_OPERATION_ABORTED` (995) the loop never reaches the
EOF check.
This reorders the checks so EOF wins unconditionally, and adds
`clearerr` before the ctrl-c retry (a real interrupt leaves the error
flag set, which would fail the next `fgets`). ctrl-c handling is
otherwise unchanged.
rdar://183335061
AMDGPU: Remove xnack and sramecc subtarget features
Now that these are controlled by module flags, the subtarget
features were just used for assembler and disassembler controls.
Now that the assembler and disassembler can infer these from
the e_flags and target directives, they are no longer necessary.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[JumpThreading] Materialize PHIs in duplicateCondBranchOnPHIIntoPred (#204859)
In duplicateCondBranchOnPHIIntoPred, updateSSA iteratively updates the
uses of
the instructions of BB (the duplicated block) according to ValueMapping.
For
PHIs, however, the mapping is inconsistent: the keys refer to the values
before
the parallel assignment of the PHIs, while the mapped-to values refer to
the
values after it. E.g.
BB:
%arr = phi [ %ov.0, %PredBB ], ...
%ov.0 = phi [ %ov.sel, %PredBB ], ...
--->
%arr => %ov.0
%ov.0 => %ov.sel
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GlobalISel: Fix lowerMergeValues when dst type is float
Lowering is done in the integer domain. Similar to the type
mismatch when dst is a pointer, make a bitcast when dst is float.
[libc++][pstl] Implementation of a parallel std::adjacent_find() based on std::mismatch() (#210604)
This PR implements a parallel `std::adjacent_find()` based on parallel
`std::mismatch`. The implementation reshapes the input range as two ranges
offset by 1 element and asks `std::mismatch` to find the first equal pair.
Part of #99938.
AMDGPU: Remove xnack and sramecc subtarget features
Now that these are controlled by module flags, the subtarget
features were just used for assembler and disassembler controls.
Now that the assembler and disassembler can infer these from
the e_flags and target directives, they are no longer necessary.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
AMDGPU: Only disassemble .amdhsa_reserve_xnack_mask on xnack targets
The disassembler unconditionally printed .amdhsa_reserve_xnack_mask when
emitting a kernel descriptor. Targets that do not support xnack have no
xnack mask to reserve, and the assembler streamer already only emits the
directive when the subtarget supports xnack. Match that behavior in the
disassembler so the round-trip is consistent and gfx11/gfx12 descriptors
no longer carry a spurious directive.
As a guard against a malformed binary, if the object's ELF e_flags
erroneously select xnack "on" for a target that does not support xnack,
still print the directive so the invalid state remains visible in the
disassembly rather than being silently dropped.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
AMDGPU: Only disassemble .amdhsa_reserve_xnack_mask on xnack targets
The disassembler unconditionally printed .amdhsa_reserve_xnack_mask when
emitting a kernel descriptor. Targets that do not support xnack have no
xnack mask to reserve, and the assembler streamer already only emits the
directive when the subtarget supports xnack. Match that behavior in the
disassembler so the round-trip is consistent and gfx11/gfx12 descriptors
no longer carry a spurious directive.
As a guard against a malformed binary, if the object's ELF e_flags
erroneously select xnack "on" for a target that does not support xnack,
still print the directive so the invalid state remains visible in the
disassembly rather than being silently dropped.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[OpenMP] Restore loop variable values after loop-tranformation constructs. (#208533)
This patch fixes loop variable finalization for OpenMP 6.0
loop-transformations constructs: `tile`, `stripe`, `reverse`,
`interchange` and `fuse` to comply with spec requirement page 371, lines
19-21. The spec requires that "After the execution of the
loop-transforming construct, the loop-iteration variables of any of its
transformation-affected loops have the values that they would have
without the loop-transforming directive".
[AMDGPU] Improve MemorySSA walking in isClobberedInFunction (#211817)
Consistently call the two argument overload
`MemorySSAWalker::getClobberingMemoryAccess(MemoryAccess,
MemoryLocation)` to get a clobbering def (according to the AliasAnalysis
used by MSSA) before applying the special cases in `isReallyAClobber`.
This has the effect of marking more loads as `amdgpu-noclobber` and
selecting SMEM load instructions for them.
Fixes: ROCM-28492
[clang-format] Add Natural option for SortIncludes (#210788)
`SortIncludes` currently orders includes lexicographically with the
option to ignore case or extension. This adds another option, `Natural`,
that compares embedded runs of digits as numbers rather than sequences
of characters, matching the "natural sort" behaviour found in most file
managers and tools like `sort` when called with the `-V` option.
**Disclaimer**
AI assistance was used in initial exploration and review but the code is
"hand generated".
[AMDGPU] Retain subreg when legalising generic operand (#212636)
When building a `COPY` to legalise a generic operand whose register
class does not match what is expected, the subregister is not retained
in the copy, and is not dropped from the newly created virtual
destination register.
[AArch64] Remove GPR64arg register class (#212457)
GPR64arg was added in fcbec02ea6fb to describe X0-X7 for the reserved
argument-register check. It is an ABI register set rather than an
allocation constraint and should not be used for register allocation.
Given it has a single use that only cares about the number of registers,
a register class isn't necessary.
This exposes that GlobalISel recomputes the minimal register class when
a matching inline asm input is tied to a fixed physical-register output.
For X2 that class was GPR64arg, getRegistersForValue already asks the
target which class implements the output constraint. Retain that class
and reuse it for the matching input.
Assisted-by: codex
Reland [PowerPC] improve performance on the isNan and !isNan function in case of -ffp-model=strict (#212565)
1. reland the patch https://github.com/llvm/llvm-project/pull/204170
2. and fix the regression caused by above patch.
