ModuloSchedule: Use use_instructions instead of use_operands + getParent (#219297)
The use list only inspected the user, so directly loop over the users.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Rematerializer: Use def_instructions instead of def_operands + getParent (#219298)
Directly iterate the user instructions instead of querying the same
parent for each use.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[ADT] Remove ComputeNodeHash and Trait::ComputeHash (NFC) (#219029)
With the switch to open addressing (commit b3411b89c3af),
FoldingSetNode stores its hash in the node itself. Table growth
rehashes nodes by calling getFoldingSetHash(), leaving ComputeNodeHash
and Trait::ComputeHash unused.
[mlir][IR][NFC] Disambiguate `SymbolTable::Visibility` references (#219301)
As a follow-up to 979b722, address MSVC's confusion when it's trying to
resolve the underqualified enum name:
```
error C2955: 'mlir::OpTrait::SymbolTable': use of class template requires template argument list
```
Assisted-by: OpenAI Codex
Signed-off-by: Artem Gindinson <gindinson at roofline.ai>
Hexagon: Use use_instructions in BitSimplify use scans
This only inspects the parent instruction, so use use_instructions
instead.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[scudo] Track maximum resident memory in cache (#219036)
Add tracking for the resident memory in MapAllocatorCache. Unreleased
cache entries where Time != 0 are assumed to be resident, while entries
that have passed through releaseOlderThan where Time == 0 have had their
physical pages discarded.
Tracking is performed by updating CurrentResidentBytes on store, remove,
and release operations, recoding the peak in maxResidentBytes and
reporting it in getStats.
GlobalISel: Replace MachineOperand based register constraint API
Replace MachineOperand reference in getConstrainedRegClassForOperand with
a Register. It is only valid to call this on a generic vreg operand, which
must be a Register so there's no point in using an operand reference.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[Clang] Rename OffloadArch::TargetArch::SPIRV to AMDGCNSPIRV to avoid confusion (#218502)
Following up to
https://github.com/llvm/llvm-project/pull/213362/changes#r3745729994,
the `TargetArch::SPIRV` introduced by #213362 actually corresponds to
`amdgcnspirv`, which is not the same as standard SPIRV: This could prove
rather confusing in the future. Renaming to `TargetArch::AMDGCNSPIRV`
also decouples "`TargetArch::SPIRV`" from AMD-specific SPIRV support, as
SPIRV is used by other vendors as well.
[CIR] Classify a named bit-field access unit as a bit-field on x86_64
mapCIRType built the ABI FieldInfo for a bit-field access unit with IsBitField
set only for an unnamed one, so a named unit reached the classifier as an
ordinary field. We now pass IsBitField with the unit's width to be able to
lower named bit-fields correctly.
Assisted-by: Cursor / claude-opus-5
[KnownFPClass] Add `KnownFPClass::frem` [NFC] (#218949)
Follow up to https://github.com/llvm/llvm-project/pull/218726
Moves `frem` deduction logic from `Analysis/ValueTracking.cpp` and
`CodeGen/GlobalISel/GISelValueTracking.cpp` to `KnownFPClass::frem`.
[MLIR][XeGPU] Update array-length users atomically (#217478)
Preflight load and slice users before changing tensor descriptor types,
then update their dependent types and offsets in one pattern
application.
Assisted-by: Codex
[AMDGPU] Ignore CU mode on targets without WGP mode
isFullSIMDMode() treated +cumode as meaningful on every generation, so on
pre-gfx10 targets it halved both the physical and the addressable LDS size
and dropped getNumWorkGroupSIMDs() from 4 to 2. Before the LDS size rework
the CU/WGP adjustment was gated on isGFX10Plus(), and +cumode was simply
ignored elsewhere.
rocFFT passes -mcumode to hipRTC unconditionally, so its Bluestein kernels
started failing to compile on gfx942 with "local memory (65536) exceeds
limit (32768)".
Change-Id: I0b440751aedd8f8b5d334ee62b68ffdc449d53f8
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
Rematerializer: Use def_instructions instead of def_operands + getParent
Directly iterate the user instructions instead of querying the same
parent for each use.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
ModuloSchedule: Use use_instructions instead of use_operands + getParent
The use list only inspected the user, so directly loop over the users.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[SCEV] Remove unreachable visitMulExpr in SCEVCastSinkingRewriter (NFC) (#219279)
SCEVCastSinkingRewriter::visit() returns S unchanged unless S->getType()
is a pointer type. So visitMulExpr can never be entered.
[CIR] Drop the isX86 gate on the incomplete-record skip
Eli asked why the incomplete-record skip only applied to the x86_64
driver. The reasoning behind it, that only a declaration can carry
this shape and no translation unit can ever call or define it, is a
language rule, not a target one, so the gate had no real reason to
be there.
Added a case to declaration-rewrite.cir that injects an "ignore"
classification for an incomplete-by-value parameter and checks the
argument survives anyway.
Assisted-by: Cursor / claude-opus-5
[mlir][OpenACC] Lower constant sized loop clauses (#219043)
Add support for sized loop clauses (`acc.loop
vector(n)/worker(n)/gang(num:n)`) in kernels constructs. Collect
constant sizes from kernels loops before conversion and add them to the
launch arguments. Treat the parallelism levels associated with sized
clauses as regular levels when assigning par_dims to loops. Non-constant
sizes remain NYI.
[MLIR][XeGPU][NFC] Fix WG integration tests for strict property assembly format (#219256)
b73a8b8d8c17 ("[MLIR][XeGPU] Enable strict property assembly format",
#217281) made inherent attributes stored as properties unparseable from
the trailing attr-dict, but two XeGPU workgroup integration tests still
write `layout` that way, so they fail to parse.
Move the affected `layout`/`layout_a`/`layout_b`/`layout_cd` operands
into the prop-dict position, `{...}` -> `<{...}>`, for
xegpu.load_matrix, store_matrix, load_nd, store_nd and dpas.
These tests only run when the Level Zero or SYCL runner is enabled
(MLIR_ENABLE_LEVELZERO_RUNNER / MLIR_ENABLE_SYCL_RUNNER), which is why
the breakage was not caught by the default CI configuration.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
[CIR] Pin x86_64 in the OpenACC declare tests
The six OpenACC declare tests dropped their CallConvLowering opt-out
without pinning a target, so `%clang_cc1` fell back to the build's
default triple. That was harmless while the opt-out flag kept
CallConvLowering from running, but the pass's byref classification for
`HasSideEffects` is target-dependent, and the Linux AArch64 CI leg
defaults to `aarch64-unknown-linux-gnu`, not x86_64. Pin
`-triple x86_64-unknown-linux-gnu`, matching the other CIR test in this
directory that already exercises CallConvLowering deliberately.
Assisted-by: Cursor / claude-opus-5
GlobalISel: Replace MachineOperand based register constraint API
Replace MachineOperand reference in getConstrainedRegClassForOperand with
a Register. It is only valid to call this on a generic vreg operand, which
must be a Register so there's no point in using an operand reference.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
