LLVM/project fd46e40llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] detectZextAbsDiff - use m_SpecificVectorElementVT matcher. NFC. (#146498)

DeltaFile
+5-6llvm/lib/Target/X86/X86ISelLowering.cpp
+5-61 files

LLVM/project 37d30d9mlir/test/mlir-tblgen op-format-spec.td

[mlir][tblgen] Fix test definition names to reflect expected valid results (NFC) (#146243)

DeltaFile
+3-3mlir/test/mlir-tblgen/op-format-spec.td
+3-31 files

LLVM/project c1122c6llvm/lib/CodeGen PHIElimination.cpp, llvm/test/CodeGen/AArch64 PHIElimination-reuse-copy.mir tbl-loops.ll

[PHIElimination] Verify COPY has similar register class, update LiveVars
DeltaFile
+88-14llvm/test/CodeGen/AArch64/PHIElimination-reuse-copy.mir
+8-8llvm/test/CodeGen/AArch64/tbl-loops.ll
+5-1llvm/lib/CodeGen/PHIElimination.cpp
+101-233 files

LLVM/project 6d6b364clang/include/clang/Basic arm_neon.td

[Clang][AArch64] Move definitions of FP8 Neon loads & stores (#146352)

Moves the definitions of FP8 loads & stores so that they are guarded
by `ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)"`
DeltaFile
+52-52clang/include/clang/Basic/arm_neon.td
+52-521 files

LLVM/project f581ef5mlir/include/mlir/Dialect/GPU/IR GPUOps.td, mlir/lib/Conversion/GPUToSPIRV GPUToSPIRV.cpp

[mlir][gpu] Add gpu.rotate operation (#142796)

Add gpu.rotate operation and a pattern to convert gpu.rotate to SPIR-V
OpGroupNonUniformRotateKHR.
DeltaFile
+102-0mlir/test/Conversion/GPUToSPIRV/rotate.mlir
+78-0mlir/test/Dialect/GPU/invalid.mlir
+50-2mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
+46-1mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
+43-0mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
+4-0mlir/test/Dialect/GPU/ops.mlir
+323-36 files

LLVM/project a97826allvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

[DAG] canCreateUndefOrPoison - explicitly state the AssertSext/Zext/Align/NoFPClass can create poison. NFC. (#146493)

This keeps getting forgotten (e.g. #66603) - so make a point of adding
it here to make it clear instead of relying on the implicit default of
returning true.
DeltaFile
+7-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+7-01 files

LLVM/project 43d2486mlir/test/lib/Dialect/Test TestFormatUtils.cpp TestFormatUtils.h, mlir/test/mlir-tblgen op-format.td op-format-spec.td

[mlir][tblgen] Fix region and successor references in custom directives (#146242)

Previously, references to regions and successors were incorrectly disallowed outside the top-level assembly form. This change enables the use of bound regions and successors as variables in custom directives.
DeltaFile
+23-0mlir/test/lib/Dialect/Test/TestFormatUtils.cpp
+12-8mlir/tools/mlir-tblgen/OpFormatGen.cpp
+20-0mlir/test/mlir-tblgen/op-format.td
+18-0mlir/test/lib/Dialect/Test/TestFormatUtils.h
+18-0mlir/test/lib/Dialect/Test/TestOps.td
+13-0mlir/test/mlir-tblgen/op-format-spec.td
+104-81 files not shown
+111-87 files

LLVM/project 4e30f81llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[DAG] visitFREEZE - remove isGuaranteedNotToBeUndefOrPoison assertion (#146490)

Although nice to have to prove the freeze can be moved, this can fail
immediately after freeze(op(...)) -> op(freeze(),freeze(),...) creation
if any of the new freeze nodes now prevents value tracking from seeing
through to the source values (e.g. shift amounts/element indices are in
bounds etc.).

This will allow us to remove the isGuaranteedNotToBeUndefOrPoison checks
inside canCreateUndefOrPoison that were discussed on #146361
DeltaFile
+19-22llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+19-221 files

LLVM/project 2ee884aclang-tools-extra/clang-doc Serialize.cpp

[clang-doc] Remove the unused clangd header.

This header seems to be included unintentionally.
DeltaFile
+0-1clang-tools-extra/clang-doc/Serialize.cpp
+0-11 files

LLVM/project 8fe25f3llvm Maintainers.md

[PowerPC] Remove chenzheng1030 from active maintainers (#145519)

chenzheng1030 has left IBM and no longer works on the PowerPC
backend. Move them from active to former maintainers.
DeltaFile
+2-3llvm/Maintainers.md
+2-31 files

LLVM/project cd60247llvm/docs DeveloperPolicy.rst

[llvm][docs] Document how to ask for things other than commit access (#146340)

This is the implicit process but useful to spell it out I think. To give
folks more confidence in asking.

Inspired by
https://discourse.llvm.org/t/request-github-issue-triage-permission-for-labeling-clang-issues/87126/1
DeltaFile
+11-0llvm/docs/DeveloperPolicy.rst
+11-01 files

LLVM/project 2199054llvm/lib/CodeGen PHIElimination.cpp, llvm/test/CodeGen/AArch64 PHIElimination-reuse-copy.mir tbl-loops.ll

[PHIElimination] Verify COPY has similar register class, update LiveVars
DeltaFile
+65-14llvm/test/CodeGen/AArch64/PHIElimination-reuse-copy.mir
+8-8llvm/test/CodeGen/AArch64/tbl-loops.ll
+5-1llvm/lib/CodeGen/PHIElimination.cpp
+78-233 files

LLVM/project 5c08aeaclang/include/clang/AST DeclarationName.h

[clang] Don't use raw source location in DeclarationName, NFC (#146412)

Converting back and forth for the source location raw encoding is
unnecessary.
DeltaFile
+9-9clang/include/clang/AST/DeclarationName.h
+9-91 files

LLVM/project 6a5a4a5llvm/lib/Target/AMDGPU AMDGPUCombine.td

Remove duplicate combines
DeltaFile
+3-4llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+3-41 files

LLVM/project 129c674llvm/test/CodeGen/AMDGPU div_i128.ll lround.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll saddsat.ll

[AMDGPU] Add KnownBits simplification combines to RegBankCombiner
DeltaFile
+22-41llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+21-40llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+30-29llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+13-17llvm/test/CodeGen/AMDGPU/div_i128.ll
+9-9llvm/test/CodeGen/AMDGPU/lround.ll
+2-14llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+97-1502 files not shown
+104-1578 files

LLVM/project e53e75allvm/lib/CodeGen/GlobalISel CombinerHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

[AMDGPU] Add BFX Formation Combines to RegBankCombiner

They're relatively safe to use there I believe. The only new registers
they may create are the constants for the BFX. For those, borrow the
RC from the source register.

Fixes #140040
DeltaFile
+484-541llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+461-509llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+173-183llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+131-141llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+56-63llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+29-0llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+1,334-1,4373 files not shown
+1,356-1,4629 files

LLVM/project 9927a43llvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankcombiner-lower-bfx.mir

comments
DeltaFile
+107-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-lower-bfx.mir
+4-3llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+111-32 files

LLVM/project d906a97llvm/lib/Target/AMDGPU AMDGPURegisterBankInfo.cpp AMDGPURegBankCombiner.cpp

[AMDGPU] Move S_BFE lowering into RegBankCombiner
DeltaFile
+55-70llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+51-0llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+13-1llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+119-713 files

LLVM/project b1c8465llvm/lib/Target/AMDGPU SIISelLowering.cpp

add assert
DeltaFile
+5-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5-01 files

LLVM/project ae15e5bllvm/lib/Target/AMDGPU SIISelLowering.cpp

Propagate depth correctly
DeltaFile
+7-6llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+7-61 files

LLVM/project f5a5891llvm/lib/Target/AMDGPU SIISelLowering.cpp

Change assert
DeltaFile
+1-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-31 files

LLVM/project 15b6ef2llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel known-bits-sbfe.mir

Fixes + add tests
DeltaFile
+139-0llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir
+7-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+146-52 files

LLVM/project 1fadb4ellvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp

style change
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+1-11 files

LLVM/project f5f905dllvm/lib/Target/AMDGPU SIISelLowering.cpp

comment
DeltaFile
+1-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-41 files

LLVM/project 74b1ed3llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel known-bits-sbfe.mir

Address comment and add more tests
DeltaFile
+115-1llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir
+9-6llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+124-72 files

LLVM/project 2589905llvm/lib/Target/AMDGPU SIISelLowering.cpp

[AMDGPU] Compute GISel KnownBits for S_BFE instructions
DeltaFile
+45-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+45-01 files

LLVM/project 698ec8cmlir/include/mlir/Dialect/Tosa/Transforms Passes.td, mlir/lib/Dialect/Tosa/Transforms TosaConvertIntegerTypeToSignless.cpp TosaValidation.cpp

[mlir][tosa] Require signless types in validation and add corresponding conversion pass (#144367)

Firstly, this commit requires that all types are signless in the strict
mode of the validation pass. This is because signless types on
operations are required by the TOSA specification. The "strict" mode in
the validation pass is the final check for TOSA conformance to the
specification, which can often be used for conversion to other formats.

In addition, a conversion pass `--tosa-convert-integer-type-to-signless`
is provided to allow a user to convert all integer types to signless.
The intention is that this pass can be run before the validation pass.
Following use of this pass, input/output information should be carried
independently by the user.
DeltaFile
+139-0mlir/lib/Dialect/Tosa/Transforms/TosaConvertIntegerTypeToSignless.cpp
+73-0mlir/test/Dialect/Tosa/tosa-convert-integer-type-to-signless.mlir
+31-0mlir/test/Dialect/Tosa/tosa-validation-valid.mlir
+14-0mlir/include/mlir/Dialect/Tosa/Transforms/Passes.td
+5-4mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+2-0mlir/test/Dialect/Tosa/invalid.mlir
+264-41 files not shown
+265-47 files

LLVM/project cd10dedclang/lib/Basic/Targets AArch64.cpp AArch64.h, clang/test/Preprocessor arm-target-features.c

[Clang] Remove AArch64TargetInfo::setArchFeatures (#146107)

When compiling with `-march=armv9-a+nosve` we found that Clang still
defines the `__ARM_FEATURE_SVE2` macro, which is explicitly set in
`setArchFeatures` when compiling for armv9-a.

After some experimenting, I found out that the list of features passed
into `AArch64TargetInfo::handleTargetFeatures` has already been expanded
and takes into account `+no[feature]` and has already expanded features
like `armv9-a`.

From that I conclude that `setArchFeatures` is no longer required.
DeltaFile
+0-74clang/lib/Basic/Targets/AArch64.cpp
+5-0clang/test/Preprocessor/arm-target-features.c
+0-2clang/lib/Basic/Targets/AArch64.h
+5-763 files

LLVM/project 768227bbolt/utils nfc-check-setup.py

Addressing reviewers
DeltaFile
+0-1bolt/utils/nfc-check-setup.py
+0-11 files

LLVM/project c853236llvm/include/llvm/CodeGen/GlobalISel CombinerHelper.h, llvm/include/llvm/Target/GlobalISel Combine.td

[GISel] Combine compare of bitfield extracts or'd together.

Equivalent of the previous DAG patch for GISel.
The shifts are BFXs in GISel, so the canonical form of the entire expression
is different than in the DAG. The mask is not at the root of the expression, it
remains on the leaves instead.

See #136727
DeltaFile
+326-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-cmp-merged-bfx.mir
+56-138llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
+89-0llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp
+10-1llvm/include/llvm/Target/GlobalISel/Combine.td
+2-0llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+483-1395 files