LLVM/project dc43062llvm/test/Transforms/LoopVectorize multiple-early-exits.ll

[LV] Add tests with multiple early exits. (NFC)

Adds test coverage with vectorizable loops with early exits.
DeltaFile
+1,180-0llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
+1,180-01 files

LLVM/project fd0bf4aclang-tools-extra/clang-tidy ClangTidyDiagnosticConsumer.cpp

[clang-tidy] Speed up deduplicating warnings from alias checks (#174237)

Right now, the deduplication algorithm runs in O(n²) time, because it
goes warning-by-warning (an O(n) operation), removing duplicates using
`std::vector::erase` (another O(n) operation). This starts taking up a
noticeable amount of time as you start getting a lot of warnings. For
example, running all checks over `clang/lib/Sema/Sema.cpp` and the
headers it includes:

```sh
time ./build/release/bin/clang-tidy -p build/debug --checks=* clang/lib/Sema/Sema.cpp -header-filter=.* > /dev/null
```

...takes 2m9s on my system before this change and 1m52s after. Now, this
scenario *is* a bit artificial; I imagine runs with so many warnings are
uncommon in practice. On the other hand, the change is quite small,
so we're not really going out of our way to improve it.
DeltaFile
+27-31clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
+27-311 files

LLVM/project e9ac1d1clang-tools-extra/docs ReleaseNotes.rst

Change chrono -> ranges in release notes
DeltaFile
+1-1clang-tools-extra/docs/ReleaseNotes.rst
+1-11 files

LLVM/project 39ae1callvm/lib/Target/X86 X86FastPreTileConfig.cpp X86.h, llvm/test/CodeGen/X86/AMX amx-fastconfig-phi2.mir amx-fastconfig-phi.mir

[X86][NewPM] Port x86-fast-pre-tile-config (#174323)

DeltaFile
+47-22llvm/lib/Target/X86/X86FastPreTileConfig.cpp
+10-2llvm/lib/Target/X86/X86.h
+2-2llvm/lib/Target/X86/X86TargetMachine.cpp
+2-1llvm/test/CodeGen/X86/AMX/amx-fastconfig-phi2.mir
+2-1llvm/test/CodeGen/X86/AMX/amx-fastconfig-phi.mir
+2-1llvm/test/CodeGen/X86/AMX/amx-fastconfig.mir
+65-295 files not shown
+73-3411 files

LLVM/project a73de98lldb/source/Core SourceManager.cpp

[lldb] Handle not being able to read a file in the SourceManager (#174346)

Even if a file has a valid modification time, it's possible that reading
the data fails. The SourceManager wasn't accounting for that, which
would result in a crash due to an unchecked read from a null `data_sp`.

We were seeing the issue when trying to read from a buggy virtual file
system, but presumably the same thing can happen with a poorly timed
unmount of a drive.

rdar://166414707
DeltaFile
+11-2lldb/source/Core/SourceManager.cpp
+11-21 files

LLVM/project 58822a6llvm/lib/Transforms/InstCombine InstructionCombining.cpp InstCombineAndOrXor.cpp, llvm/test/Transforms/InstCombine binop-select.ll

[InstCombine] Fold `(select C, (x bin_op a), x) bin_op b` into `x bin_op select C, (a bin_op b), b` (#173511)

Fixes #154246.

The original pattern in the issue was the following:
```llvm
define i8 @src(i8 %arg0, i8 %arg1) {
  %v0 = icmp eq i8 %arg1, -1
  %v1 = or i8 %arg0, 4
  %v2 = select i1 %v0, i8 %v1, i8 %arg0
  %v3 = or i8 %v2, 1
  ret i8 %v3
}
```
to
```llvm
define i8 @tgt(i8 %arg0, i8 %arg1) {
  %v0 = icmp eq i8 %arg1, -1
  %v3.v = select i1 %v0, i8 5, i8 1

    [6 lines not shown]
DeltaFile
+776-0llvm/test/Transforms/InstCombine/binop-select.ll
+44-0llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+6-0llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+3-0llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+3-0llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+2-0llvm/lib/Transforms/InstCombine/InstCombineInternal.h
+834-06 files

LLVM/project ac300dd

Merge branch 'users/chapuni/mcdc/nest/lnot' into users/chapuni/mcdc/nest/trunk
DeltaFile
+0-00 files

LLVM/project 6de643e

Merge branch 'users/chapuni/mcdc/nest/expect' into users/chapuni/mcdc/nest/trunk
DeltaFile
+0-00 files

LLVM/project 93ca3d5llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/PowerPC vector-popcnt-128-ult-ugt.ll

Merge branch 'users/chapuni/mcdc/nest/nest' into users/chapuni/mcdc/nest/trunk
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+22,442-22,606llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+508,892-22,60662,984 files not shown
+7,272,157-2,626,23762,990 files

LLVM/project 2b9ab09clang/include/clang/Basic DiagnosticFrontendKinds.td

Prune warn_pgo_nested_boolean_expr
DeltaFile
+0-5clang/include/clang/Basic/DiagnosticFrontendKinds.td
+0-51 files

LLVM/project 6648a46llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/nest-base' into users/chapuni/mcdc/nest/nest

Conflicts:
        clang/lib/CodeGen/CodeGenPGO.cpp (#172557)
        clang/test/Frontend/custom-diag-werror-interaction.c
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+65,599-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+552,049-067,059 files not shown
+8,075,972-3,085,89167,065 files

LLVM/project 09e881ellvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/PowerPC vector-popcnt-128-ult-ugt.ll

Merge commit '64cbe975bf1a9425a5bfad0e03f9e0ea26769979' into users/chapuni/mcdc/nest/nest-base
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+22,442-22,606llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+508,892-22,60662,984 files not shown
+7,272,163-2,626,24362,990 files

LLVM/project 64cbe97clang/lib/CodeGen CoverageMappingGen.cpp CodeGenPGO.cpp, clang/test/Profile c-mcdc-logicalop-ternary.c

Merge branches 'users/chapuni/mcdc/nest/covmapdesc', 'users/chapuni/mcdc/nest/covgen', 'users/chapuni/mcdc/nest/logopstack' and 'users/chapuni/mcdc/nest/bitmapaddr' into HEAD
DeltaFile
+142-175llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
+189-126clang/lib/CodeGen/CoverageMappingGen.cpp
+51-11clang/lib/CodeGen/CodeGenPGO.cpp
+14-26clang/lib/CodeGen/CGExprScalar.cpp
+17-5clang/lib/CodeGen/CodeGenPGO.h
+10-8clang/test/Profile/c-mcdc-logicalop-ternary.c
+423-3518 files not shown
+476-39214 files

LLVM/project bd784b6clang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode typeid.cpp

[clang][bytecode] Fix typeid test under msan (#174317)

The original problem description sounded sane but it was lacking a bit.
What happens where is that the global block is ultimately not
initialized simply because it was already created before and its
initializer failed, causing us to call invokeDtor() in a previous
evaluation.

Check for the initialion state earlier and abort there instead of
accessing the (now uninitialized) data of the block, causing msan
failures.

See the failed msan build at
https://lab.llvm.org/buildbot/#/builders/164/builds/17206
DeltaFile
+11-0clang/test/AST/ByteCode/typeid.cpp
+4-1clang/lib/AST/ByteCode/Compiler.cpp
+15-12 files

LLVM/project eeee678llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/PowerPC vector-popcnt-128-ult-ugt.ll

Merge branch 'users/chapuni/mcdc/nest/mcdcstate' into users/chapuni/mcdc/nest/bitmapaddr

Conflicts:
        clang/lib/CodeGen/CodeGenFunction.h (#142155)
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+22,442-22,606llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+508,892-22,60662,983 files not shown
+7,272,006-2,626,05762,989 files

LLVM/project 76b00fcflang/lib/Semantics check-call.cpp, flang/test/Semantics cuf23.cuf

[flang][cuda] Skip sizeof intrinsic in check (#174339)

#174025 introduced a new semantic check for host intrinsic with device
variable.`sizeof` intrinsic extension should be skipped for this check.
DeltaFile
+1-1flang/lib/Semantics/check-call.cpp
+1-0flang/test/Semantics/cuf23.cuf
+2-12 files

LLVM/project 545c684llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/mcdcstate' into users/chapuni/mcdc/nest/covgen

Conflicts:
        clang/lib/CodeGen/CoverageMappingGen.cpp (#172557)
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+65,599-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+552,049-067,059 files not shown
+8,075,845-3,085,61667,065 files

LLVM/project ba73eb8clang/lib/CodeGen CodeGenPGO.cpp CodeGenFunction.h

clangCodeGen: Follow #142155
DeltaFile
+6-0clang/lib/CodeGen/CodeGenPGO.cpp
+2-4clang/lib/CodeGen/CodeGenFunction.h
+8-42 files

LLVM/project 7a5760fllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'users/chapuni/mcdc/nest/mcdcstate' into users/chapuni/mcdc/nest/logopstack
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+65,599-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+552,049-067,059 files not shown
+8,075,845-3,085,61667,065 files

LLVM/project 2702f3dllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/PowerPC vector-popcnt-128-ult-ugt.ll

Merge branch 'main' into users/chapuni/mcdc/nest/mcdcstate
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+22,442-22,606llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+508,892-22,60662,983 files not shown
+7,272,001-2,626,05362,989 files

LLVM/project b65f6bfllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites long-spec-const-composite.ll

Merge branch 'main' into users/chapuni/mcdc/nest/covmapdesc
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+65,599-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-spec-const-composite.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+552,049-067,058 files not shown
+8,075,844-3,085,61567,064 files

LLVM/project 7a95385llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/PowerPC vector-popcnt-128-ult-ugt.ll

Merge branch 'main' into users/chapuni/mcdc/nest/lnot
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+22,442-22,606llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+508,892-22,60662,983 files not shown
+7,272,001-2,626,05362,989 files

LLVM/project e93fb04llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/PowerPC vector-popcnt-128-ult-ugt.ll

Merge branch 'main' into users/chapuni/mcdc/nest/expect
DeltaFile
+241,284-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+95,651-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+53,948-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+49,842-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+45,725-0llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+22,442-22,606llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+508,892-22,60662,983 files not shown
+7,272,001-2,626,05362,989 files

LLVM/project 0c71423mlir/cmake/modules MLIRDetectPythonEnv.cmake

[Python] Bump MLIR Python minimum version to 3.10
DeltaFile
+4-3mlir/cmake/modules/MLIRDetectPythonEnv.cmake
+4-31 files

LLVM/project 19a1c40llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] LowerMINMAX - use valuetracking to attempt to find a smaller type that can efficiently lower min/max ops (#174294)

We currently use the generic expansions to custom lower integer min/max
instructions, but if we have sufficient leading bits, SSE/AVX is always
better off handling it directly with smaller types.

vXi64 cmp/min/max is particularly weak, and as we narrow the types the
better legality we have - this approach seems to work well for x86, but
I'm not sure if its valid enough to try generically in this manner.

However, I added the signed/unsigned generic flip fold to
expandIntMINMAX to further improve SSE2 codegen, similar to what we
already attempt in DAGCombiner (which with a bit more work we might be
able to remove now).

All thats missing is better ComputeNumSignBits handling for vXi64 ashr
expansion, which still misses a lot of cases when split across vXi32
types and shuffles.

Fixes #174169
DeltaFile
+26-67llvm/test/CodeGen/X86/vector-umin-range.ll
+24-67llvm/test/CodeGen/X86/vector-umax-range.ll
+32-0llvm/lib/Target/X86/X86ISelLowering.cpp
+10-16llvm/test/CodeGen/X86/vector-pcmp.ll
+22-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+2-10llvm/test/CodeGen/X86/vector-smin-range.ll
+116-1601 files not shown
+118-1707 files

LLVM/project 30bb38bllvm/lib/AsmParser LLParser.cpp, llvm/test/Assembler denormal_fpenv.ll invalid_denormal_fpenv.ll

IR: Promote "denormal-fp-math" to a first class attribute

Convert "denormal-fp-math" and "denormal-fp-math-f32" into a first
class denormal_fpenv attribute. Previously the query for the effective
deormal mode involved two string attribute queries with parsing. I'm
introducing more uses of this, so it makes sense to convert this
to a more efficient encoding. The old representation was also awkward
since it was split across two separate attributes. The new encoding
just stores the default and float modes as bitfields, largely avoiding
the need to consider if the other mode is set.

The syntax in the common cases looks like this:
  `denormal_fpenv(preservesign,preservesign)`
  `denormal_fpenv(float: preservesign,preservesign)`
  `denormal_fpenv(dynamic,dynamic float: preservesign,preservesign)`

I wasn't sure about reusing the float type name instead of adding a
new keyword. It's parsed as a type but only accepts float. I'm also
debating switching the name to subnormal to match the current

    [18 lines not shown]
DeltaFile
+374-0llvm/test/Bitcode/auto_upgrade_denormal_fp_math.ll
+297-0llvm/test/Assembler/denormal_fpenv.ll
+228-2llvm/test/Bitcode/compatibility.ll
+187-0llvm/test/Assembler/invalid_denormal_fpenv.ll
+57-57llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
+101-0llvm/lib/AsmParser/LLParser.cpp
+1,244-59215 files not shown
+2,367-936221 files

LLVM/project 621a533llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

vector leading to store
DeltaFile
+261-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+261-01 files

LLVM/project a2f3139llvm/include/llvm/Target TargetOptions.h, llvm/lib/CodeGen CommandFlags.cpp

CodeGen: Remove denormal mode from TargetOptions (#174285)

This doesn't appear to be used anywhere, and is a
per-function property.
DeltaFile
+1-20llvm/include/llvm/Target/TargetOptions.h
+0-5llvm/lib/CodeGen/CommandFlags.cpp
+1-252 files

LLVM/project 2ea6c18clang/lib/CIR/CodeGen CIRGenFunction.h

[CIR][NFC] Fix incorrect function names in assert messages (#174334)

DeltaFile
+2-3clang/lib/CIR/CodeGen/CIRGenFunction.h
+2-31 files

LLVM/project c03b6f3llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor nofpclass.ll

Partially reapply "ValueTracking: Improve handling of fadd in computeKnownFPClass." (#174290) (#174332)

This partially reverts commit 108a22ed5fa1836b4cfcd05e9d96f98a533068d5.

Restore the sign-bit tracking for both inputs known-negative case,
and leave the 0 handling for later. There is a libc test improperly
relying on running code compiled for IEEE behavior that changed
the output denormal mode.
DeltaFile
+15-15llvm/test/Transforms/Attributor/nofpclass.ll
+18-4llvm/lib/Analysis/ValueTracking.cpp
+33-192 files