LLVM/project 583f294llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 copyable_reorder.ll

[SLP] Normalize copyable operand order to group loads for better vectorization

When building operands for entries with copyable elements, non-copyable
lanes may have inconsistent operand order (e.g., some lanes have
load,add while others have add,load for commutative ops). This prevents
VLOperands::reorder() from grouping consecutive loads on one side,
degrading downstream vectorization.
Normalize in two steps during buildOperands:
1) Majority voting: swap lanes that are the exact inverse of the
   majority operand-type pattern.
2) Load preference: if the majority pattern has loads at OpIdx 1
   (strict majority), swap to put loads at OpIdx 0, enabling
   vector load + copyable patterns.

Recommit after revert at c2139f13606f0be8d09fa82a28e85dba4c3478dd, added
a check for commutative operations for reorder.

Original Pull Request: https://github.com/llvm/llvm-project/pull/189181


    [2 lines not shown]
DeltaFile
+78-49llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+12-26llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
+90-752 files

LLVM/project e4afaa1llvm/lib/Target/RISCV RISCVCodeGenPrepare.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-reduction-int.ll

[RISCV] Further improved exact VLEN lowering for mul reductions (#192688)

This is a follow up to 973a05ed. When we have a horizontal multiply
reduction at high LMUL and we have exact knowledge of VLEN, we can
extract the individual m1 sub-vectors and perform the entire reduction
tree at m1. This reduces the work performed (by not performing high LMUL
operations on a vectors with empty tails), and decreases register
pressure. Interestingly, we don't even increase dynamic instruction
count as the register alignment of the original LMUL forced the use of
whole register moves in the tree reduction anyways. (In the non-exact
case, these are vslidedown instructions, and are required.)

Originally written by Claude Code, heavily revised by me.
DeltaFile
+82-26llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
+37-15llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+119-412 files

LLVM/project d841a93llvm/lib/Target/SPIRV SPIRVCallLowering.cpp SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV/hlsl-intrinsics gep-i8-ptr-param-struct.ll

[SPIR-V] Deduce argument types before doing GEP (#193046)

In SPIRVEmitIntrinsics, we try to get the type for a GEP by looking at
the type of the input pointer, and deducing the output pointer type from
it. If the input pointer is a function parameter, we do not have the
type
available yet because we deduce the type of the parameters after
processing the GEPs.

There is no reason to have that order. Moving the parameter passes
earlier so the GEP type deduction works.

The same test exposed a problem with function parameter attributes. They
require Kernel, so we no longer emit them when creating a shader.


<!-- branch-stack-start -->

<!-- branch-stack-end -->
DeltaFile
+52-50llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+35-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/gep-i8-ptr-param-struct.ll
+2-2llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+89-523 files

LLVM/project 6a6f3b0llvm/test/Transforms/SLPVectorizer/X86 copyable_reorder.ll

[SLP][NFC]Add a test with non-reordable operands of non-commutative copyables, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/193226
DeltaFile
+43-0llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
+43-01 files

LLVM/project 216bccbllvm/lib/Target/SPIRV SPIRVPushConstantAccess.cpp, llvm/test/CodeGen/SPIRV vk-pushconstant-gep-constant-expr.ll

[SPIR-V] Handle constant expression uses of PushConstant globals (#193005)

When lowering  globals, users that are constant
expressions cannot be rewritten by the push constant access path
because a simple replacement with the result of a call to an intrinsic
will no longer be a constant. The uses of the GV that are constant
expression must be replaced with instruction before trying to rewrite
them.
DeltaFile
+27-0llvm/test/CodeGen/SPIRV/vk-pushconstant-gep-constant-expr.ll
+3-1llvm/lib/Target/SPIRV/SPIRVPushConstantAccess.cpp
+30-12 files

LLVM/project 1a02697clang/test/ClangScanDeps optimize-vfs-pch.m modules-pch-common-stale.c

[LIT] Add -nostdinc so system headers aren't searched with implicit module maps (#192125)

These lit tests are implicitly loading the module maps found in the
directories found in the search path. On z/OS this ends up trying to
load an invalid module map that is never used with the actual clang
compilation. Add `-nostdinc` to avoid searching dirs outside of the ones
being tested.
DeltaFile
+4-4clang/test/ClangScanDeps/optimize-vfs-pch.m
+4-4clang/test/ClangScanDeps/modules-pch-common-stale.c
+2-2clang/test/ClangScanDeps/modules-pch-imports.c
+1-1clang/test/ClangScanDeps/modules-full-by-mult-mod-names-diagnostics.c
+11-114 files

LLVM/project 4ebf27bllvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

Merge branch 'main' into users/bassiounix/clang/deduction-guides
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,805-4,811llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,871-1,882llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+764-1,425llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
+39,728-9,6851,540 files not shown
+91,982-39,2751,546 files

LLVM/project df7eb62clang/www cxx_status.html

increase clang support version
DeltaFile
+1-1clang/www/cxx_status.html
+1-11 files

LLVM/project 971ce4bclang/lib/Frontend InitPreprocessor.cpp, clang/test/Lexer cxx-features.cpp

enable ctad for both c++17 and c++20
DeltaFile
+1-1clang/test/Lexer/cxx-features.cpp
+1-0clang/lib/Frontend/InitPreprocessor.cpp
+2-12 files

LLVM/project a2011b1llvm/test/Transforms/LoopVectorize/RISCV strided-accesses.ll

[LV][RISCV][NFC] Update strided-accesses.ll to UTC version 6 (#193211)
DeltaFile
+570-540llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+570-5401 files

LLVM/project e5925fbllvm/test/tools/llvm-objdump/MachO compact-unwind-i386.test compact-unwind-x86_64.test

[NFC][llvm-objdump] Use CHECK-NEXT in MachO tests (#192696)

[NFC][llvm-objdump] Use CHECK-NEXT in MachO tests
DeltaFile
+25-25llvm/test/tools/llvm-objdump/MachO/compact-unwind-i386.test
+25-25llvm/test/tools/llvm-objdump/MachO/compact-unwind-x86_64.test
+21-21llvm/test/tools/llvm-objdump/MachO/dis-no-leading-addr.test
+18-18llvm/test/tools/llvm-objdump/MachO/archive-headers.test
+16-16llvm/test/tools/llvm-objdump/MachO/dis-symname.test
+15-15llvm/test/tools/llvm-objdump/MachO/section-contents.test
+120-1207 files not shown
+156-15613 files

LLVM/project dc73cabllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 bfloat-int-cvt.ll

[X86][AVX10.2] Skip FP2I/I2FP customizations for bf16 (#193137)

Because AVX10.2 doesn't provide native BF16 FP2I/I2FP conversion
instructions.
DeltaFile
+849-0llvm/test/CodeGen/X86/bfloat-int-cvt.ll
+11-5llvm/lib/Target/X86/X86ISelLowering.cpp
+860-52 files

LLVM/project 8abcce0llvm/test/Transforms/LoopVectorize/AArch64 Oz-and-forced-vectorize.ll, llvm/test/Transforms/PhaseOrdering/AArch64 Oz-and-forced-vectorize.ll

[LoopVectorize] Generate test checks (NFC) (#193216)

Also move the test to PhaseOrdering, as it tests the full pipeline.
DeltaFile
+89-0llvm/test/Transforms/PhaseOrdering/AArch64/Oz-and-forced-vectorize.ll
+0-37llvm/test/Transforms/LoopVectorize/AArch64/Oz-and-forced-vectorize.ll
+89-372 files

LLVM/project 941e8efmlir/include/mlir/Dialect/Arith/Transforms Passes.h Passes.td, mlir/lib/Dialect/Arith/Transforms ExpandOps.cpp

[mlir][arith] Add support for `arith.flush_denormals` emulation (#192660)

Add lowering pattern and a new pass `arith-expand-flush-denormals` that
rewrites `arith.flush_denormals` ops with integer arithmetics. This
lowering is useful for target architectures that cannot pattern-match
`arith.flush_denormals` + other FP arithmetics into special instructions
with FTZ semantics.

Assisted-by: claude-opus-4.7-thinking-high

Depends on #192641.
DeltaFile
+105-0mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
+96-0mlir/test/Dialect/Arith/expand-flush-denormals.mlir
+5-0mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
+4-0mlir/include/mlir/Dialect/Arith/Transforms/Passes.td
+210-04 files

LLVM/project 1566b63clang/lib/Driver/ToolChains Clang.cpp, clang/lib/Driver/ToolChains/Arch X86.cpp

[X86][clang-cl] Make AVX10.2 map to the same target-cpu as AVX10.1 (#193147)

Diamondrapids contains a large feature set APX, which should not be
enabled by AVX10.2
DeltaFile
+6-4clang/test/Driver/cl-x86-flags.c
+8-1clang/lib/Driver/ToolChains/Clang.cpp
+1-1clang/lib/Driver/ToolChains/Arch/X86.cpp
+15-63 files

LLVM/project 9c2d944llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 dag-ReplaceAllUsesOfValuesWith.ll

[DAG] Reassociate (add (add X, Y), X) --> add(add(X, X), Y) (#162242)

Attempt to bring together self-additions, to help with folding to shift/mul/address patterns
DeltaFile
+39-37llvm/test/CodeGen/AMDGPU/idot2.ll
+14-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+6-6llvm/test/CodeGen/X86/avx-vinsertf128.ll
+1-4llvm/test/CodeGen/AArch64/dag-ReplaceAllUsesOfValuesWith.ll
+1-2llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll
+61-495 files

LLVM/project 1697b96runtimes/cmake config-Fortran.cmake

[runtimes] Protect use of undefined CMAKE_Fortran_COMPILER (#193210)

Unlike everything else in CMake, cmake_path does not assume a default
value for undefined variables, but instead throws an error:
```
CMake Error at cmake/config-Fortran.cmake:77 (cmake_path):
  cmake_path undefined variable for input path.
Call Stack (most recent call first):
  CMakeLists.txt:284 (include)
```
Protect the use of cmake_path to not trigger this error when
CMAKE_Fortran_COMPILER is undefined.

Fixes the flang-aarch64-out-of-tree buildbot after #171610.
DeltaFile
+38-36runtimes/cmake/config-Fortran.cmake
+38-361 files

LLVM/project d629a22polly/unittests CMakeLists.txt

[Polly] Disable PCH reuse for unit tests (#193209)

Polly library targets already disable PCH reuse because Polly
unconditionally builds with -fno-rtti and -fno-exceptions. Reusing LLVM
PCHs that were built with RTTI or exceptions enabled is incompatible
with Clang when compiling Polly targets under those flags.

After 47eb8b43c990 enabled PCH reuse for unit tests, Polly unit tests
can hit the same mismatch as the library targets. Pass DISABLE_PCH_REUSE
through the shared add_polly_unittest wrapper so all Polly unit tests
follow the existing Polly target policy.

cc @aengelke -- a minor fix for polly.
DeltaFile
+4-1polly/unittests/CMakeLists.txt
+4-11 files

LLVM/project 300285eclang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenModule.h

[CIR][NFCI] Remove 'isConstant' from getCIRLinkageForX (#193100)

This variable has since disappeared from classic compiler, and we
weren't using it anywhere anyway. This patch gets us back in sync with
the classic codegen for these interfaces.
DeltaFile
+9-14clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-4clang/lib/CIR/CodeGen/CIRGenModule.h
+1-2clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+1-2clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp
+1-2clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+1-1clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+15-256 files

LLVM/project f6f39c6llvm/test/Transforms/LoopVectorize/RISCV strided-accesses.ll

[LV] Add test for interaction between interleaved and strided load. nfc (#192990)

For #147297

Co-authored-by: Luke Lau <luke at igalia.com>
DeltaFile
+126-0llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+126-01 files

LLVM/project a976a72llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU vgpr-spill.mir

[AMDGPU] Multi dword spilling for unaligned tuples (#183701)

While spilling unaligned tuples, rather than breaking the
spill into 32-bit accesses, spill the first register as a single
32-bit spill, and spill the remainder of the tuple as an aligned tuple.
Some additional bookkeeping is required in the spilling
loop to manage the state.

References: https://github.com/llvm/llvm-project/pull/177317
DeltaFile
+21-37llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
+34-10llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+55-472 files

LLVM/project b7cfcfellvm/lib/ProfileData/Coverage CoverageMapping.cpp

[llvm-cov] Fix error propagation in CoverageMapping::load() (#193197)

Fix a subtle issue on the error path: if loadFromFile() fails there is no error to consume.
DeltaFile
+11-7llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
+11-71 files

LLVM/project 58063ffmlir/include/mlir/Dialect/Arith/Transforms Passes.td, mlir/lib/Dialect/Arith/Transforms ExpandOps.cpp

address comments
DeltaFile
+30-46mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
+16-28mlir/test/Dialect/Arith/expand-flush-denormals.mlir
+4-15mlir/include/mlir/Dialect/Arith/Transforms/Passes.td
+50-893 files

LLVM/project 037a48allvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine fcmp.ll

[InstCombine] fold fabs(uitofp(i16 a) - uitofp(i16 b)) < 1.0 to a == b (#191378)

Fixes: https://github.com/llvm/llvm-project/issues/187088

When a and b are types with bitwidth (16 bits) smaller than the mantissa
for float32 (24 bits), they will be exact and their absolute difference
would be integral ±1 or greater if a != b. On the corollary, if their
difference is < 1.0, this implies that a = b.

This patch exploits this fact to fold the expression to just a single
icmp.
DeltaFile
+259-5llvm/test/Transforms/InstCombine/fcmp.ll
+70-0llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+329-52 files

LLVM/project 7134ce5clang-tools-extra/clang-tidy/readability IdentifierLengthCheck.cpp

Revert "[clang-tidy][NFC] add numeric include for transform_reduce" (#193200)

After experiment, this didn't fix the build failure. So revert this to
keep the trunk clean.

Reverts llvm/llvm-project#193165
DeltaFile
+0-1clang-tools-extra/clang-tidy/readability/IdentifierLengthCheck.cpp
+0-11 files

LLVM/project 2196957mlir/lib/Dialect/Arith/Transforms ExpandOps.cpp, mlir/test/Dialect/Arith expand-flush-denormals.mlir

address comments
DeltaFile
+16-31mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
+15-27mlir/test/Dialect/Arith/expand-flush-denormals.mlir
+31-582 files

LLVM/project 649143cmlir/include/mlir/Dialect/Arith/Transforms Passes.td Passes.h, mlir/lib/Dialect/Arith/Transforms ExpandOps.cpp

[mlir][arith] Add support for `arith.flush_denormals` emulation
DeltaFile
+121-0mlir/lib/Dialect/Arith/Transforms/ExpandOps.cpp
+108-0mlir/test/Dialect/Arith/expand-flush-denormals.mlir
+15-0mlir/include/mlir/Dialect/Arith/Transforms/Passes.td
+5-0mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
+249-04 files

LLVM/project 744279bmlir/include/mlir/Dialect/Arith/IR ArithOps.td, mlir/lib/Conversion/ArithAndMathToAPFloat ArithToAPFloat.cpp

[mlir][arith] Add `arith.flush_denormals` operation (#192641)

Add a new `arith.flush_denormals` operation. The operation takes a
floating-point value as input and returns zero if the value is denormal.
If the input is not denormal, the operation passes through the input.
This commit also adds support to the `ArithToAPFloat` infrastructure.

Running example:
```mlir
%flush_a = arith.flush_denormals %a : f32
%flush_b = arith.flush_denormals %b : f32
%res = arith.addf %flush_a, %flush_b : f32
%flush_res = arith.flush_denormals %res : f32
```

The exact lowering path depends on the backend and is not implemented as
part of this PR:
- Per-instruction mode. E.g., on NVIDIA architectures, the above example
can lower to `add.ftz.f32 dest, a, b`.

    [11 lines not shown]
DeltaFile
+39-0mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+23-13mlir/lib/Conversion/ArithAndMathToAPFloat/ArithToAPFloat.cpp
+32-0mlir/test/Dialect/Arith/ops.mlir
+26-0mlir/test/Conversion/ArithAndMathToAPFloat/arith-to-apfloat.mlir
+23-0mlir/test/Dialect/Arith/canonicalize.mlir
+22-0mlir/lib/Dialect/Arith/IR/ArithOps.cpp
+165-132 files not shown
+195-138 files

LLVM/project 95c5836llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU minimumnum.ll maximumnum.ll

[AMDGPU] Add legalizer rule support for AMDGPU's regbank fminimumnum and fmaximumnum (#192719)

Part of #192497
DeltaFile
+51-24llvm/test/CodeGen/AMDGPU/minimumnum.ll
+51-24llvm/test/CodeGen/AMDGPU/maximumnum.ll
+2-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+104-493 files

LLVM/project 60af5a9libsycl/include/sycl/__impl queue.hpp, libsycl/include/sycl/__impl/detail arg_wrapper.hpp

fix merge errors

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+0-135libsycl/include/sycl/__impl/detail/arg_wrapper.hpp
+0-43libsycl/include/sycl/__impl/queue.hpp
+0-1782 files