[Mips] Legalize vector UNDEF instead of expanding to zero BUILD_VECTOR (#211503)
Currently, MIPS MSA expands ISD::UNDEF into a BUILD_VECTOR of all zeros
during legalization. This creates an infinite loop in DAGCombiner when
the following occurs:
1.Mips lower BUILD_VECTOR expands non-splat vectors into
INSERT_VECTOR_ELT with creating undef node
2.Then legalization expands UNDEF back to BUILD_VECTOR zero
3.Mips lower BUILD_VECTOR converts zero vector to BITCAST
4.DAGCombiner optimizes BITCAST(zero) to UNDEF
5.Back to step 2, infinite loop
Fix #210229.
[Mips] Fix getInstSizeInBytes for instructions with delay slots (#216665)
MIPS branch/jump instructions (B, BEQ, JALR64Pseudo, PseudoReturn64,
etc.) have a delay slot. The actual encoded size is 8 bytes (instr +
NOP). This fixes "out of range PC16 fixup" errors on large functions.
This issue was exposed in llvm 23 by commit pr #191460 which changed
MipsBranchExpansion to use MBB::iterator instead of instr_iterator,
making the MBB size calculation more accurate and revealing the
pre-existing bug.
Thanks for the pr #187703 `AllowOverEstimate` to help find instr which
actual size mismatch expected size .
Fix #112010.
[BOLT] Fix overflow issue when using absolute addressing in LSDA (#216654)
Currently, in the emitLSDA() flow, signed data is used when using
absolute addresses to update the LSDA for non PIE/DSO. But when the PC
is higher than 0x7fffffff(2GB), this will be sign-extended into an
invalid 64-bit address. Especially when the output binary is large,
silent errors can easily occur (we have met this problem in real
scenarios).
So this patch changes the signed data to unsigned data, thereby fixing
the incorrect address extension like this:
```
.gcc_except_table
LSDA:
LPStartEncoding: DW_EH_PE_omit // No LPStart
CallSiteEncoding: DW_EH_PE_sdata4 -> udata4 // Changed from sdata4 to udata4
call-site table:
call-site 1:
start = ...
[4 lines not shown]
[IR] Autoupgrade trivial VP intrinsics to their non-VP counterparts (#212490)
As a first step towards removing trivial VP intrinsics, autoupgrade them
to their non-VP counterparts for backwards compatibility. Subsequent PRs
can then remove the intrinsics themselves.
Since trivial VP intrinsics only set lanes to poison, it's safe to
replace them with non predicated versions.
RFC: https://discourse.llvm.org/t/rfc-remove-trivial-vp-intrinsics/90972
[CIR] Destroy a static local's extended temporary in its cir.local_init (#216210)
A temporary lifetime-extended by a function-local static had its
destructor hung off the cir.global, which the verifier rejects: a static
local is initialized and destroyed in-function under its guard, via
cir.local_init. Thread the region emitCXXSpecialVarDeclInit already
picks down to pushTemporaryCleanup, which registers into it in reverse
construction order.
Fixes SPEC2026: yaml-cpp's IsValidPlainScalar (736.ocio_r,
772/872.marian).
[SLP]Add extractelement as a main opcode for copyables
Model a bundle of extractelements from a common vector plus a foreign scalar
as a copyable node: matching lanes reuse the source vector and copyable lanes
are inserted into it. Limited to the identity extract order without a reuse
shuffle, other cases fall back to gather.
Fixes #192849
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/216503
[AMDGPU] Optimize SGPR splat reg sequences for packed 64-bit instructions (#217182)
This work optimizes SGPR register sequences for packed 64-bit instructions by eliminating
redundant register copies when a scalar value is splatted across multiple lanes.
The optimization is implemented in SIFoldOperands::tryFoldSGPRSplatRegSequence, which:
1. Detects SGPR register sequences where all elements are identical
2. Verifies all uses are packed 64-bit instructions supporting single
SGPR read
3. Replaces redundant elements with undef to allow copy elimination
This reduces SGPR register pressure and eliminates unnecessary copies in
kernels using packed operations with splat scalars.
[SLP]Fix unscheduled-deps assertion for cmp with identical operands
Same-operands cmps (icmp sge %x, %x) took the reordered dependency
counting path, which undercounts the second use while scheduling
releases one dep per operand column. Treat them as non-commutative so
each use is checked against its own edge.
Fixes #217408
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/217495
Reject CHARACTER types in AssignSimple and add death tests
AssignSimple is only intended for trivial intrinsic types (integer, real,
complex, logical). Add a guard that crashes on CHARACTER type input,
matching the existing derived-type guard.
Add death tests covering all five crash paths in AssignSimple: rank
mismatch, element-bytes mismatch, derived type, character type, and
non-allocatable element count mismatch.
Co-Authored-By: Claude Opus 4 (1M context) <noreply at anthropic.com>
[NewPM] Port CFIInstrInserter to the new pass manager
Adds a newPM pass for CFIInstrInserter (cfi-instr-inserter).
- Extracts the pass's working state (MBBVector, CSRLocMap) and logic
into a CFIInstrInserterImpl class with a run method, called by both
the legacy pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass CFIInstrInserterPass, using
RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
calls skipFunction, so it always runs unconditionally and should not
be skippable in the new PM either. run() unconditionally returns
PreservedAnalyses::all(), matching the legacy pass's own
AU.setPreservesAll() declaration -- the same shape CFIFixupPass (an
already-ported sibling CFI pass) already uses.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder.
- Wires the pass into X86's and RISC-V's newPM pipelines, matching
their existing legacy-PM gating conditions:
- X86 replaces an existing TODO inside an already-correct
[13 lines not shown]
[NewPM] Port FuncletLayout to the new pass manager (#217490)
Adds a newPM pass for FuncletLayout (funclet-layout).
- Extracts the pass's logic (which has no per-instance state) into a
shared runFuncletLayout free function, called by both the legacy pass
and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass FuncletLayoutPass, using
RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
calls skipFunction, so it always runs unconditionally and should not be
skippable in the new PM either.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder
-- FuncletLayoutPass was already unconditionally invoked from
CodeGenPassBuilder.h via a DUMMY_MACHINE_FUNCTION_PASS stub, so no
separate enablement change was needed.
- Fixes four pipeline-dump tests (X86, RISC-V x2, Lanai) whose CHECK
lines expected the stub's class-name fallback ("FuncletLayoutPass")
rather than the real pass's registered pipeline name ("funclet-layout").
[4 lines not shown]
[NewPM] Port CFIInstrInserter to the new pass manager
Adds a newPM pass for CFIInstrInserter (cfi-instr-inserter).
- Extracts the pass's working state (MBBVector, CSRLocMap) and logic
into a CFIInstrInserterImpl class with a run method, called by both
the legacy pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass CFIInstrInserterPass, using
RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
calls skipFunction, so it always runs unconditionally and should not
be skippable in the new PM either. run() unconditionally returns
PreservedAnalyses::all(), matching the legacy pass's own
AU.setPreservesAll() declaration -- the same shape CFIFixupPass (an
already-ported sibling CFI pass) already uses.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder.
- Wires the pass into X86's and RISC-V's newPM pipelines, matching
their existing legacy-PM gating conditions:
- X86 replaces an existing TODO inside an already-correct
[13 lines not shown]
[NewPM] Port FuncletLayout to the new pass manager
Adds a newPM pass for FuncletLayout (funclet-layout).
- Extracts the pass's logic (which has no per-instance state) into a
shared runFuncletLayout free function, called by both the legacy
pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass FuncletLayoutPass, using
RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
calls skipFunction, so it always runs unconditionally and should not
be skippable in the new PM either.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder
-- FuncletLayoutPass was already unconditionally invoked from
CodeGenPassBuilder.h via a DUMMY_MACHINE_FUNCTION_PASS stub, so no
separate enablement change was needed.
- Fixes four pipeline-dump tests (X86, RISC-V x2, Lanai) whose CHECK
lines expected the stub's class-name fallback ("FuncletLayoutPass")
rather than the real pass's registered pipeline name
[6 lines not shown]
[NewPM] Port FuncletLayout to the new pass manager
Adds a newPM pass for FuncletLayout (funclet-layout).
- Extracts the pass's logic (which has no per-instance state) into a
shared runFuncletLayout free function, called by both the legacy
pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass FuncletLayoutPass, using
RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
calls skipFunction, so it always runs unconditionally and should not
be skippable in the new PM either.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder
-- FuncletLayoutPass was already unconditionally invoked from
CodeGenPassBuilder.h via a DUMMY_MACHINE_FUNCTION_PASS stub, so no
separate enablement change was needed.
- Fixes four pipeline-dump tests (X86, RISC-V x2, Lanai) whose CHECK
lines expected the stub's class-name fallback ("FuncletLayoutPass")
rather than the real pass's registered pipeline name
[6 lines not shown]
[AMDGPU] Remove more redundant ANDs (#216900)
Remove more redundant AND X, IMM instructions by allowing:
1. s_and_b32 operations to be processed.
2. IMM can have values beside 0xffff.
3. The instruction defining X can be another AND instruction.
4. IMM can be either source operand.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
