LLVM/project dc9d64alld/COFF InputFiles.cpp, lld/test/COFF embed-bitcode.test

[lld][COFF] Restore `lto-embed-bitcode` and `-fembed-bitcode` Bitcode Embedding Features (#188398)

Removes the patches introduced by #150897 which broke LTO embed
documented features for creating whole-program-bitcode representations
of executables, used in production analysis/rewriting toolsets. This was
a documented feature available up until 21.1.8 broken by 22.x release.

This previously allowed the users to have a whole-program-bitcode
section `.llvmbc` embedded inside of the final executable.

(cherry picked from commit 1e99c9e4c7e82c8417e4bdb0d1cb3b86e6640c6c)
DeltaFile
+0-30lld/test/COFF/embed-bitcode.test
+0-5lld/COFF/InputFiles.cpp
+0-352 files

LLVM/project 199e5b7. lib.out tmp.exe

[NFC] Remove stray files from top level directory (#189563)

Added untracked files into the top level directory by mistake, reverting
the change in this PR.

Co-authored-by: himadhith <himadhith.v at ibm.com>
DeltaFile
+0-38lib.out
+0-0tmp.exe
+0-382 files

LLVM/project 8fef0fbclang/lib/Interpreter Interpreter.cpp, clang/test/Interpreter pretty-print.c

[clang-repl] Fix C89 incompatible keywords (#189432)

Restrict and inline keywords are removed for C89 interpreter since these
keywords caused fail at runtime preamble.

Fixes #189088

(cherry picked from commit 8bd83048084c27615e9536227fbb2545472915e7)
DeltaFile
+9-2clang/lib/Interpreter/Interpreter.cpp
+1-0clang/test/Interpreter/pretty-print.c
+10-22 files

LLVM/project f500b8dclang-tools-extra/test/clang-doc enum.cpp, llvm/test/Analysis/CostModel/AMDGPU log10.ll log.ll

Merge branch 'main' into users/cabbaken/03-31-_da_check_nsw_flags_for_addrecs_in_the_exact_rdiv_test
DeltaFile
+464-226clang-tools-extra/test/clang-doc/enum.cpp
+328-349llvm/test/CodeGen/AMDGPU/fract-match.ll
+380-248llvm/test/Analysis/CostModel/AMDGPU/log10.ll
+380-248llvm/test/Analysis/CostModel/AMDGPU/log.ll
+606-0llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+296-190llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+2,454-1,261694 files not shown
+22,407-6,946700 files

LLVM/project 0c2c3f0clang/test/Analysis bstring.cpp

[analyzer][NFC] Reorganize bstring.cpp tests (#188709)

This change eliminates preprocessor-based suppression of test cases by
introducing multi-prefix verify options to run-lines. This slightly
increases coverage.
DeltaFile
+62-59clang/test/Analysis/bstring.cpp
+62-591 files

LLVM/project 0f75ecflldb/include/lldb/Target Target.h, lldb/source/Target Target.cpp

[lldb] Only create RegisterTypeBuilderClang plugin once (#189393)

This plugin creates types based on information from target XML, which is
parsed only once per session. It has internal logic to reuse created
types, but the plugin itself was being remade every time a type was
requested.
DeltaFile
+4-3lldb/source/Target/Target.cpp
+2-0lldb/include/lldb/Target/Target.h
+6-32 files

LLVM/project 7b6514ccompiler-rt/lib/sanitizer_common sanitizer_procmaps_mac.cpp weak_symbols.txt, compiler-rt/lib/tsan/go buildgo.sh

[sanitizer_common] [Darwin] Adopt _dyld_get_dyld_header (#182943)

(cherry picked from commit 2e7d07a33725a82ecfc514e27f047ece3ff13d4c)
DeltaFile
+6-2compiler-rt/lib/sanitizer_common/sanitizer_procmaps_mac.cpp
+1-1compiler-rt/lib/tsan/go/buildgo.sh
+1-0compiler-rt/lib/sanitizer_common/weak_symbols.txt
+8-33 files

LLVM/project b2660a9clang/lib/CodeGen CGOpenMPRuntimeGPU.cpp

OpenMP: Reimplement getOffloadArch

This function made no sense at all. It was scanning through
the feature map looking for something that parsed as an OffloadArch.
Directly compute the arch from the target device.

I don't know why there isn't just an OffloadArch in TargetOpts,
this shouldn't really require parsing.
DeltaFile
+3-12clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+3-121 files

LLVM/project 6e2e06fllvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Refactor the signature of the Exact RDIV test (NFCI) (#189535)
DeltaFile
+10-20llvm/lib/Analysis/DependenceAnalysis.cpp
+1-3llvm/include/llvm/Analysis/DependenceAnalysis.h
+11-232 files

LLVM/project 538ce9eclang/lib/AST DeclTemplate.cpp, clang/test/SemaTemplate GH188759.cpp

[clang] fix getReplacedTemplateParameter for function template specializaions

This fixes the transformation of substituted constant template parameters by
providing the instantiated parameter type for the function template
specialization case.

This fixes a regression introduced in #161029 which will be backported to llvm-22, so there are no release notes.

Fixes #188759
DeltaFile
+13-0clang/test/SemaTemplate/GH188759.cpp
+6-4clang/lib/AST/DeclTemplate.cpp
+19-42 files

LLVM/project 7365bfbllvm/lib/Target/X86/GISel X86InstructionSelector.cpp, llvm/test/CodeGen/X86/GlobalISel select-insert-vec256.mir select-insert-vec512.mir

[X86][GISel] Avoid creating subreg def operands in emitInsertSubreg (#189408)

emitInsertSubreg builds a COPY with a subregister def operand, but these
probably should not be allowed in SSA MIR. Change it to build an
equivalent use of INSERT_SUBREG instead.
DeltaFile
+71-44llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
+56-38llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
+12-10llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
+11-8llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
+9-3llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+159-1035 files

LLVM/project dbad8a1llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp WebAssemblyMachineFunctionInfo.cpp, llvm/test/CodeGen/WebAssembly swifttailcc.ll swiftasync-coroutine.ll

Wasm: add support for `swifttailcc` calling convention (#188296)

Wasm backend already supports tail calls where available, we only need
to enable corresponding branches for this calling convention.
DeltaFile
+148-0llvm/test/CodeGen/WebAssembly/swifttailcc.ll
+41-0llvm/test/CodeGen/WebAssembly/swiftasync-coroutine.ll
+27-11llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+19-0llvm/test/CodeGen/WebAssembly/swifttailcc-no-tailcall.ll
+12-6llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
+10-0llvm/test/CodeGen/WebAssembly/swifttailcc-musttail-no-tailcall.ll
+257-171 files not shown
+262-207 files

LLVM/project 14bf1cdllvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp SIInstrInfo.h

[AMDGPU][SIMemoryLegalizer] Consider scratch operations as NV=1 if GAS is disabled

- Clarify that `thread-private` MMO flag is still useful.
- If GAS is not enabled (which is the default as of last patch), consider an op as `NV=1` if it's a `scratch_` opcode, or if the MMO is in the private AS.
- Add tests for the new cases.
- Update AMDGPUUsage GFX12.5 memory model
DeltaFile
+181-0llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.mir
+75-36llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
+13-6llvm/docs/AMDGPUUsage.rst
+14-3llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+3-1llvm/lib/Target/AMDGPU/SIInstrInfo.h
+286-465 files

LLVM/project d5d8b47llvm/include/llvm/IR GlobalObject.h Instruction.h, llvm/lib/IR Metadata.cpp LLVMContextImpl.h

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+105-114llvm/lib/IR/Metadata.cpp
+9-51llvm/lib/IR/LLVMContextImpl.h
+5-0llvm/include/llvm/IR/GlobalObject.h
+5-0llvm/include/llvm/IR/Instruction.h
+5-0llvm/include/llvm/IR/Value.h
+3-2llvm/lib/IR/Globals.cpp
+132-1671 files not shown
+134-1707 files

LLVM/project fa136dfllvm/lib/Object RelocationResolver.cpp, llvm/test/DebugInfo/AArch64 tls-at-location.ll

[llvm-dwarfdump] Support R_AARCH64_TLS_DTPREL64 in Object/RelocationResolver.cpp (#187649)

In patch https://github.com/llvm/llvm-project/pull/146572 we have plan
to emit R_AARCH64_TLS_DTPREL64. This give us the warning while using
llvm-dwarfdump for the object file which has tls variables -

warning: failed to compute relocation: R_AARCH64_TLS_DTPREL64, Invalid
data was encountered while parsing the file

To fix this warning we have mark the relocation as supported however
final absolute address of a TLS variable is determined at runtime,
resolving to the symbol's section-relative offset in the object file is
mitigate the warning.
DeltaFile
+2-0llvm/lib/Object/RelocationResolver.cpp
+1-1llvm/test/DebugInfo/AArch64/tls-at-location.ll
+3-12 files

LLVM/project 0430ca0clang/test/CodeGenHIP incorrect-atomic-scope.hip, clang/test/CodeGenOpenCL incorrect-atomic-scope.cl

add a builtin that becomes an intrinsic with metadata scope
DeltaFile
+22-3clang/test/CodeGenOpenCL/incorrect-atomic-scope.cl
+18-2clang/test/CodeGenHIP/incorrect-atomic-scope.hip
+40-52 files

LLVM/project b4485bdclang-tools-extra/test/clang-doc enum.cpp, llvm/test/Analysis/CostModel/AMDGPU log.ll log10.ll

Merge branch 'main' into users/cabbaken/03-31-_da_refactor_the_signature_of_the_exact_rdiv_test_nfci_
DeltaFile
+464-226clang-tools-extra/test/clang-doc/enum.cpp
+328-349llvm/test/CodeGen/AMDGPU/fract-match.ll
+380-248llvm/test/Analysis/CostModel/AMDGPU/log.ll
+380-248llvm/test/Analysis/CostModel/AMDGPU/log10.ll
+606-0llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+296-190llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+2,454-1,261680 files not shown
+21,913-6,755686 files

LLVM/project e07cfeellvm/include/llvm/MC MCAssembler.h, llvm/lib/MC MCAssembler.cpp

Revert "[MC] Fuse relaxation and layout into a single forward pass (#184544)"

This reverts commit debb2514ea7f062a29e5e4740f9d6ee4cea3b978.
DeltaFile
+42-60llvm/lib/MC/MCAssembler.cpp
+0-37llvm/test/MC/X86/align-branch-convergence.s
+8-6llvm/test/MC/ELF/relax-branch-align.s
+1-6llvm/include/llvm/MC/MCAssembler.h
+51-1094 files

LLVM/project 598f353llvm/test/CodeGen/AArch64 sve-mask-partition.ll intrinsic-cttz-elts-sve.ll, llvm/test/CodeGen/PowerPC cttz-elts.ll

[SelectionDAG] Expand CTTZ_ELTS[_ZERO_POISON] and handle legalization (#188691)

This is a second attempt at "[SelectionDAG] Expand
CTTZ_ELTS[_ZERO_POISON] and handle splitting" (#188220)

That PR had to be reverted in 7d39664a6ae8daaf186b65578492244d96a50bf2
because we had crashes on AMDGPU since we didn't have scalarization
support, and other crashes on PowerPC because we didn't handle the case
when a vector needed widened. Tests for these are added in
AMDGPU/cttz-elts.ll, RISCV/rvv/cttz-elts-scalarize.ll and
PowerPC/cttz-elts.ll.

The former crash has been fixed by adding
DAGTypeLegalizer::ScalarizeVecOp_CTTZ_ELTS.

The second crash has been fixed by reworking
TargetLowering::expandCttzElts. The expansion for CTTZ_ELTS is nearly
identical to VECTOR_FIND_LAST_ACTIVE, except it uses a reverse step
vector and subtracts the result from VF. The easiest way to fix these

    [6 lines not shown]
DeltaFile
+412-24llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-elts.ll
+261-0llvm/test/CodeGen/RISCV/rvv/cttz-elts-scalarize.ll
+53-203llvm/test/CodeGen/AArch64/sve-mask-partition.ll
+73-79llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll
+33-98llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
+120-0llvm/test/CodeGen/PowerPC/cttz-elts.ll
+952-40414 files not shown
+1,174-56520 files

LLVM/project 40f53d2clang/test/CIR/CodeGen keep-persistent-storage-variables.cpp keep-static-consts.cpp

add tests persistent-storage-variables and keep-static-consts
DeltaFile
+20-0clang/test/CIR/CodeGen/keep-persistent-storage-variables.cpp
+11-0clang/test/CIR/CodeGen/keep-static-consts.cpp
+31-02 files

LLVM/project 45a12c8llvm/lib/Analysis DependenceAnalysis.cpp

Update
DeltaFile
+3-6llvm/lib/Analysis/DependenceAnalysis.cpp
+3-61 files

LLVM/project 0aa937fllvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU fract-match.ll

AMDGPU: Match fract from compare and select and minimum

Implementing this with any of the minnum variants is overconstraining
for the actual use. Existing patterns use fmin, then have to manually
clamp nan inputs to get nan propagating behavior. It's cleaner to express
this with a nan propagating operation to start with.
DeltaFile
+197-264llvm/test/CodeGen/AMDGPU/fract-match.ll
+124-85llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+321-3492 files

LLVM/project 32ad662llvm/lib/Analysis DependenceAnalysis.cpp

Update
DeltaFile
+2-6llvm/lib/Analysis/DependenceAnalysis.cpp
+2-61 files

LLVM/project f48425ellvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU fract-match.ll

AMDGPU: Match fract pattern with swapped edge case check (#189081)

A fract implementation can equivalently be written as
  r = fmin(x - floor(x))
  r = isnan(x) ? x : r;
  r = isinf(x) ? 0.0 : r;

or:
  r = fmin(x - floor(x));
  r = isinf(x) ? 0.0 : r;
  r = isnan(x) ? x : r;

Previously this only matched the previous form. Match
the case where the isinf check is the inner clamp. There are
a few more ways to write this pattern (e.g., move the clamp of
infinity to the input) but I haven't encountered that in the wild.

The existing code seems to be trying too hard to match noncanonical
variants of the pattern. Only handles the result that all 4 permutations
of compare and select produce out of instcombine.
DeltaFile
+328-349llvm/test/CodeGen/AMDGPU/fract-match.ll
+47-17llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+375-3662 files

LLVM/project 5b2363a. lib.out tmp.exe, libcxx/test/std/thread/futures/futures.async thread_create_failure.pass.cpp

[libc++][AIX] Fix force_thread_creation_failure by using RLIMIT_THREADS (#188787)

This patch fixes the test `force_thread_creation_failure.cpp` on AIX by
using platform specific `RLIMIT_THREADS` which helps in restricting the
thread creation as `RLIMIT_NPROC` on AIX restricts processes and not
threads.

---------

Co-authored-by: himadhith <himadhith.v at ibm.com>
DeltaFile
+38-0lib.out
+9-7libcxx/test/std/thread/futures/futures.async/thread_create_failure.pass.cpp
+0-0tmp.exe
+47-73 files

LLVM/project f918f84clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen CIRGenModule.cpp

add opGlobalPragmaClangSection missing feature
DeltaFile
+4-0clang/test/CIR/CodeGen/global-section.c
+1-1clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+1-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+1-0clang/include/clang/CIR/MissingFeatures.h
+7-14 files

LLVM/project 035ae02llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[RISCV] Fix discarded return value in RISCVOperand::print for FRM (#189530)

The roundingModeToString() return value was not being written to the
output stream, causing FRM operands to print as "<frm: >" with no
rounding mode name in debug output.

Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
DeltaFile
+1-1llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+1-11 files

LLVM/project 2f671faclang/test/CodeGenHIP incorrect-atomic-scope.hip, clang/test/CodeGenOpenCL incorrect-atomic-scope.cl

add an example of scoped atomics
DeltaFile
+9-3clang/test/CodeGenOpenCL/incorrect-atomic-scope.cl
+8-2clang/test/CodeGenHIP/incorrect-atomic-scope.hip
+17-52 files

LLVM/project 8037908clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenModule.cpp

[CIR] Add calling_conv attribute to FuncOp with lowering support
DeltaFile
+38-0clang/test/CIR/IR/calling-conv.cir
+34-0clang/test/CIR/Lowering/calling-conv.cir
+23-5clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+24-1clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+16-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+5-6clang/lib/CIR/CodeGen/CIRGenModule.cpp
+140-133 files not shown
+143-219 files

LLVM/project 7aa5fd5clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR] Add calling convention values to CIR_CallingConv
DeltaFile
+8-3clang/include/clang/CIR/Dialect/IR/CIROps.td
+8-31 files