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[AMDGPU] Add s_wakeup_barrier instruction for gfx1250 (#170501)

[DAG] Recognise AVGFLOOR (((A >> 1) + (B >> 1)) + (A & B & 1)) patterns (#169644)

Recognise 'LSB' style AVGFLOOR patterns.

Alive2:
[https://alive2.llvm.org/ce/z/nfSSk_](https://alive2.llvm.org/ce/z/nfSSk_)

Fixes #53648

[LoongArch] Custom lowering for vector logical right shifts of integers (#171097)

After PR #169491, the DAG combiner can still recreate vector UDIV in an
illegal type even after type legalization, which is the root cause of
issue #170976.

The optimization introduced in PR #169491 is still desirable, so this
patch adds custom lowering for vector integer logical right shifts to
prevent the DAG from producing nodes with illegal types.

Fixes #170976

Merge branch 'main' into users/rovka/alloc-vgpr-intrinsic

Merge branch 'main' into users/rovka/relax-callers-for-chain-funcs

[compiler-rt][sanitizer] fix i386 build for Haiku (#171075)

r13 does not provide the trap err.

Co-authored-by: Jerome Duval <jerome.duval at gmail.com>

[RISCV][GISel] Legalize the G_FCANONICALIZE instruction (#166162)

use dims modifer in main num_teams clause itself instead of creating new clause

[AMDGPU] Removal of language sensitive option for _Float16 and half('e') handling (#170443)

Removing the 'e' handling for the amdgcn builtins as we decided to use
_Float16 for both HIP/C++ and OpenCL

[mlir][py] avoid crashing on None contexts in custom `get`s (#171140)

Following a series of refactorings, MLIR Python bindings would crash if
a
dialect object requiring a context defined using
mlir_attribute/type_subclass
was constructed outside of the `ir.Context` context manager. The type
caster
for `MlirContext` would try using `ir.Context.current` when the default
`None`
value was provided to the `get`, which would also just return `None`.
The
caster would then attempt to obtain the MLIR capsule for that `None`,
fail,
but access it anyway without checking, leading to a C++ assertion
failure or
segfault.

Guard against this case in nanobind adaptors. Also emit a warning to the

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Address weining's comments

[MC] Reorder TARGETInstrTable to shrink MCInstrDesc::ImplicitOffset (#171199)

Put ImplicitOps[] before OperandInfo[] in the generated
TARGETInstrTable. This means that offsets to entries into the (small)
ImplicitOps table do not need to skip over the (large) OperandInfo
table.

This allows shrinking ImplicitOffset from 32 bits to 16 bits
(effectively reverting #138127) which will allow expanding Opcode
instead without increasing the size of MCInstrDesc.

[mlir][py] avoid crashing on None contexts in custom `get`s

Following a series of refactorings, MLIR Python bindings would crash if a
dialect object requiring a context defined using mlir_attribute/type_subclass
was constructed outside of the `ir.Context` context manager. The type caster
for `MlirContext` would try using `ir.Context.current` when the default `None`
value was provided to the `get`, which would also just return `None`. The
caster would then attempt to obtain the MLIR capsule for that `None`, fail,
but access it anyway without checking, leading to a C++ assertion failure or
segfault.

Guard against this case in nanobind adaptors. Also emit a warning to the user
to clarify expectations, as the default message confusingly says that `None` is
accepted as context and then fails with a type error. Using Python C API is
currently recommended by nanobind in this case since the surrounding function
must be marked `noexcept`.

The corresponding test is in the PDL dialect since it is where I first observed
the behavior. Core types are not using the `mlir_type_subclass` mechanism and
are immune to the problem, so cannot be used for checking.

[VPlan] Combine LiveIns fields into MapVector (NFC) (#170220)

Combine Value2VPValue and VPLiveIns into a single MapVector LiveIns
field, simplifying users.

[Flang-rt] Implement same behavior as -O3 for zero-length arrays (#171480)

[MLIR][LLVMIR] Fix LLVM IR import of ZeroInitializers to constant zero (#171107)

Constant zero aggregate structures are imported to from llvm IR as
undef.
This includes for example LandingPad Instructions which have zero value
filters, structs.

This fixes the import to use the zeroOp to materialize a
zero-initialized constant.

ELF: Remove stray ;. NFC

[AMDGPU] Add builtins for wave reduction intrinsics

[AMDGPU] Add wave reduce intrinsics for double types - 2

Supported Ops: `add`, `sub`

[LV] Use branch_weights metadata in getPredBlockCostDivisor test. NFC (#171299)

This is more reliable in the event that the trivial fcmp gets folded
away.

[RISCVInsertVSETVLI] Don't allow getSEW/getLMUL to be called for hasSEWLMULRatioOnly(). NFC (#171554)

Refactor some logic in transferBefore to handle hasSEWLMULRatioOnly()
before calling getSEW/getLMUL.

Update adjustIncoming to use getSEWLMULRatio(). Update the interface of
RISCVVType::getSameRatioLMUL to take the ratio instead of SEW and LMUL.
Update the few other callers to call RISCVVType::getSEWLMULRatio first.

[RISCV] Use frmarg instead of ixlenimm in PseudoFROUND. NFC (#171563)

This is expanded with a custom inserter and this immediate will be
copied to the frm operand of a non-pseudo instruction.

[RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 (#171562)

There is no difference of functionality and I believe this is a
copy-paste mistake. :-)

[AArch64][SVE] Add SubtargetFeature to disable lowering unpredicated loads/stores as LDR/STR (#170256)

PR #127837 changed the lowering for unpredicated loads/stores to use LDR/STR instead of LD1/ST1.
However, on some CPUs, such as A64FX, there is a performance difference between LD1/ST1 and LDR/STR.
As a result, the lowering introduced in #127837 can cause a performance regression on these targets.
This patch adds a SubtargetFeature `disable-unpredicated-ld-st-lower` to disable this lowering.
It is enabled for the A64FX target.

[AMDGPU] Make SIShrinkInstructions pass return valid changed state

clang-format

[NPM] Schedule PhysicalRegisterUsageAnalysis before RegUsageInfoCollectorPass (#168832)

RegUsageInfoCollectorPass requires PhysicalRegisterUsageAnalysis to be valid. this change is required since its a module analysis.

[scudo] Add last release time info to getStats (#170902)

Knowing when the last page release happened can help us figure out if
the page release is skipped or not.

[RISCV] Add fractional LMUL register classes for inline assembly. (#171278)

Inline assembly uses the first type from the register class to
connect to the rest of SelectionDAG. By adding fractional LMUL
register classes, we can ensure that this type is the size of the
types we use for fractional LMUL in the rest of SelectionDAG.

This allows us to remove some of the handling we had in
splitValueIntoRegisterParts/joinRegisterPartsIntoValue. This code
was incorrectly handling v16i4 arguments/returns which should be
any_extend to v16i8 to match type legalization. Instead we widened
v16i4 -> v32i4 then bitcasted to v16i8. This merged pairs of i4
elements into an i8 element instead of keeping them as separate
elements that have been extended to i8.

This is an alternative to #171243.
    
Fixes #171141.

[AMDGPU] Removal of language sensitive option for _Float16 and half( 'e') handling