[RelLookupTableConverter][NFC] Fix typo GlovalVarOp -> GlobalVarOp (#223555)
Fixes the misspelling of GlovalVarOp with a 'v' in
shouldConvertToRelLookupTable.
[Clang] Reject overflow behavior types on _Atomic (#222179)
atomic read-modify-write operations aren't instrumented for overflow. `counter++` on an `_Atomic` object lowers to a single `atomicrmw`, and this is true for plain atomic types under `-fsanitize=signed-integer-overflow` too.
That's a problem for `__ob_trap`, which is supposed to be checked no matter what the global flags say:
```c
typedef int __ob_trap trapping_int;
_Atomic trapping_int counter;
int x = counter + 1; // checked
counter++; // not checked
```
A guarantee that only holds for some expressions is worse than none, so reject the combination outriht. Let's also reject `__ob_wrap` too so the rule doesn't depend on the behavior kind... wrap has minimal use here anyways.
Applying an OBT specifier over an atomic type was already an error, though it unhelpfully reported `_Atomic(int)` as a non-integer type even though it is. Applying `_Atomic` over an existing OBT was accepted, which is where the unchecked read-modify-write came from... this was a bug that is now fixed because we are no longer trying to apply OBT on top of `_Atomic`. This is all made more clear by better diagnostics too :)
We can relax this later if someone needs it. I think instrumenting checked atomic rmws would mean lowering to a cmpxchg/CAS loop.
Assisted-by: claude
Signed-off-by: Justin Stitt <justinstitt at google.com>
[Clang][ABI] Classify floating-point matrix types as homogeneous aggregates (#222429)
The `ABIInfo::isHomogeneousAggregate()` function did not have explicit
handling for `ConstantMatrixType` and so, by default, these types were
rejected as potential homogeneous aggregates.
This change adds handling for `ConstantMatrixType` and classifies such
matrix types depending on whether they otherwise meet the criteria.
Fixes: https://github.com/llvm/llvm-project/issues/222417
Assisted-by: Cursor / Grok 4.6
Reland "[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors" (#221058)
This relands #217055
The original commit revealed a latent issue in eliminateFrameIndex in
SIRegisterInfo where SCC can be clobbered before reading it on
gfx900/gfx90a. This change itself has no known issues.
[CIR][CodeGen] Implement target-features checking(CodeGenUtils!) (#223056)
This DOES move checking functions out of CodeGen and into CodeGenUtils
so both can use it.
This is a diagnostic for builtins/etc that is built in to classic
codegen. We have to implement it, because otherwise autoconfig thinks
that we support AVX without a flag, and thus causes us to fail builds
later on that now expect __AVX__/etc to be defined without enabling
them.
[mlir][emitc] Add a ConvertToEmitCPatternInterface for the math dialect (#223666)
MathToEmitC wasn't registered for `--convert-to-emitc`. This registers
an interface matching the other *ToEmitC interfaces.
[KnownFPClass] Add sign preserving deductions to `atan2(y, x)` (#223176)
`atan2(y, x)` should return the same sign as `y` (up to the denormal
mode):
- If `y >= +0.0`, then `atan2(y, x) >= +0.0`
- If `y <= -0.0`, then `atan2(y, x) <= -0.0`
AI Disclosure:
I used ChatGPT Codex (5.6 sol) to help write the tests.
[KnownFPClass] Propagate non-`sNaN` for `fadd`/`fsub`, `fmul`, `fdiv`, and `fma` (#221876)
`fadd`, `fsub`, `fmul`, `fdiv`, and `fma` can only return `sNaN` if at
least one of their inputs are `sNaN`. This means that we can rule out
`sNaN` from the result if all of the arguments are known to never be
`sNaN`.
`sNaN` propagation for `frem` is handled in this PR:
https://github.com/llvm/llvm-project/pull/219303
[flang][test][NFC] Add OpenMP test for mismatched loop bound types (#221097)
Adds a regression test that lowering succeeds when an OpenMP loop mixes
bound types: the loop trip count comes from an integer(kind=INT64)
module
variable while the lower bound and step are i32 literals, so both are
converted to i64 before being passed through host_eval.
[AMDGPU] Prevent SCC clobber in frame index lowering in scaling path
eliminateFrameIndex has two lowering strategies, but only one has the proper handling for checking SCC-liveness to prevent clobbering. Unify them with a helper function to ensure both paths handle the same
[NVPTX] Honor !atomic.ignore.denormal.mode on atomicrmw fadd
PTX atom.add has a fixed denormal behavior that the program cannot
control: atom.add.f32 flushes denormals on global memory but not on
shared, and atom.add.f16 never flushes. When that disagrees with the
function's denormal mode, the backend expands the atomic into a CAS loop
so the denormal behavior is preserved.
!atomic.ignore.denormal.mode says the denormal behavior of this
particular atomic does not matter, so use the native instruction even
when it disagrees. This is the same thing -nvptx-allow-ftz-atomics does,
except per-instruction instead of per-compilation, which lets a frontend
opt in only the operations it knows about -- notably CUDA's atomicAdd(),
which is defined in terms of atom.add.
Note that -nvptx-allow-ftz-atomics defaults to true, so the new behavior
is only observable with -nvptx-allow-ftz-atomics=false.
Co-authored-by: Artem Belevich <tra at google.com>
[clang][NVPTX] Emit !atomic.ignore.denormal.mode for CUDA atomics
CUDA's atomicAdd() family is defined in terms of PTX atom.add, whose
denormal behavior is fixed by the hardware. Without any annotation the
backend has to assume the function's denormal mode must be honored and
expands these into CAS loops whenever the two disagree. Mark them with
!atomic.ignore.denormal.mode so the native instruction is used.
That covers the __nvvm_atom_*_add_gen_f builtins that atomicAdd(),
atomicAdd_block() and atomicAdd_system() are written in terms of, plus
C11/C++11 atomics under -fatomic-ignore-denormal-mode and the
[[clang::atomic(ignore_denormal_mode)]] attribute, which requires
teaching the NVPTX target about AtomicOptions.
The condition for when the metadata is meaningful is now shared with the
AMDGPU and SPIR-V targets in addAtomicIgnoreDenormalModeMetadata(). It
takes an AllowHalf flag because whether f16 denormals are observable is
target specific: PTX exposes no FTZ control for f16 operations, so
atom.add.f16 never flushes and the opt-in is meaningful there, whereas
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[Flang] Keep -fkeep-inline-functions as an ignored option (#223733)
55221f7 removed the warning check for -fkeep-inline-functions and
-fno-keep-inline-functions from flang-f-opts.f90 after the test started
failing when the option was implemented for Clang in 28efe19.
The options are currently only supported by Clang, so keep
-fkeep-inline-functions and -fno-keep-inline-functions as unsupported
options for Flang and emit the appropriate warnings.
[IR] Generalize !amdgpu.ignore.denormal.mode into !atomic.ignore.denormal.mode (#217585)
The !amdgpu.ignore.denormal.mode metadata tells the backend that an
atomicrmw fadd need not honor the function's denormal mode, so a native
atomic instruction whose denormal behavior is fixed in hardware may be
used instead of a CAS loop. Nothing about that is AMDGPU specific: NVPTX
has exactly the same problem with atom.add, whose FTZ behavior depends
on
the address space and cannot be controlled.
Promote it to a target independent fixed metadata kind,
!atomic.ignore.denormal.mode, and switch the AMDGPU, SPIR-V and OpenMP
producers and consumers over to it. Document it in LangRef, and point
AMDGPUUsage at that description rather than duplicating it.
Existing IR keeps working: AutoUpgrade renames the metadata on atomicrmw
instructions when parsing textual IR and when materializing bitcode. The
upgrade is deliberately scoped to atomicrmw rather than being applied to
every attachment of that name, since that is the only place the metadata
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[lldb] [Windows] Add a missing include. NFC. (#223727)
_open_osfhandle is defined in io.h, which wasn't explicitly included
before.
This built fine in practice with both WinSDK and recent mingw-w64
headers, but failed with older versions of mingw-w64 (older than August
2026).
Also change an accidental #if into #ifdef.
This fixes regressions from 1ca6698be7708121f987d0acf896c7dc4cf63a51 and
ba1687b72476eb368641b9a9f565a38cf41b7393.
[AMDGPU] Set Format/FormatModifier directly instead of per-flag bits, NFC.
Remove the now-redundant individual InstSI format flag fields (SOP1/2/C/K/P,
VOP1/2/C/VOP3/VINTRP/VOPD3/LDSDIR, the memory formats, Spill, and DPP/SDWA) and
have instruction classes set the Format / FormatModifier enum fields directly.
The enum fields are packed into TSFlags exactly as before, so this is NFC (the
full instruction table is byte-identical).
Real instructions copy Format/FormatModifier from their pseudo in the base real
classes (kept next to the existing TSFlags copy), so the Format field is now
correct on real instructions too.
Two derived helper bits (IsVOP3Encoding, VOPD3) are computed from Format for the
getVOPe32/getVOPe64 relation maps and the VOPDPairs searchable table; they are
not part of TSFlags.
Co-Authored-By: Claude <noreply at anthropic.com>
[AMDGPU] Decouple isVOP3P/isVINTERP from isVOP3 (#223448)
VOP3P and VINTERP instructions also set the VOP3 TSFlags bit, so isVOP3()
returned true for them. This overloaded isVOP3() to mean both "the VOP3
encoding" and "uses VOP3-style operand rules" (modifiers, constant bus,
literal legality).
Make VOP3P and VINTERP their own instruction-format enum values so
isVOP3() is strict (Format == VOP3). Callers that need "any VOP3-family
operand encoding" now use isVOP3Like() (VOP3 | VOP3P | VINTERP), added as
a SIInstrInfo wrapper. Redundant "isVOP3() && !isVOP3P()" tests are
simplified to isVOP3().
Resolves llvm/llvm-project#223448.
Co-Authored-By: Claude <noreply at anthropic.com>
[AMDGPU] Pack instruction format and modifier TSFlags bits into enums, NFC.
The instruction-format bits in TSFlags are mutually exclusive, so
collapse them into a single 5-bit Format enum and likewise FormatModifier
enum for DPP/SDWA. This frees 18 TSFlags bits.
For now Format is derived from individual TableGen bitfields to minimize
the patch, but next commit will remove those.
All raw format-bit tests already go through the SIInstrFlags predicates,
so no call sites change.
Co-Authored-By: Claude <noreply at anthropic.com>
[NewPM] Add helper function to skip for opt-bisect
With the introduction of CodeGen passes to the NewPM infrastructure, we
get the concept of required passes that perform optimizations and want
to skip them when running under opt bisect. This occurs for passes like
SelectionDAG and StackColoring. Add a helper function to make it easy to
query, although make it specific to opt bisect unlike the LegacyPM
skipFunction. A helper function is slightly more convenient (i.e., no
need to forward the pass name explicitly).
Reviewers: nikic, arsenm, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/223486
[CHERI][RISCV][AsmPrinter] Use pointer index size rather than pointer size in AsmPrinter constant lowering. (#220100)
This prevents a crash due to APInt width mismatches during
accumulateConstantOffset for CHERI targets.
clang: Fix exception model flag tests if webassembly isn't build (#223770)
The wasm and emscripten RUN lines require the WebAssembly backend due to
the use of -mllvm -wasm-enable-eh, until that flag is fully replaced with
the new exception model flag.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[flang][cuda][NFC] Move CUFDeviceIsActive function to the right place (#223453)
The definition and declaration were done in different files (descriptor
and allocator). Move all to allocatable as this check is used for the
automatic deallocation.
[[mlir][linalg] Infer reduction-neutral padding values in rewriteAsPaddedOp (#216517)
**Problem**:
with no explicit options.paddingValues, rewriteAsPaddedOp padded every
operand with zero — silently corrupting reductions (a padded
maximumf/mulf element gets combined).
**Change**:
Added a new public linalg::inferPaddingValues(builder, toPad) to pick a
semantics-preserving value per operand:
- no reduction dim → zero;
- contraction → zero (0 annihilates through the multiply);
- other reductions → the combiner's neutral (-inf for maximumf, 1 for
mulf, …), found via matchReduction so the real accumulator combiner is
used.
rewriteAsPaddedOp calls it when options.paddingValues is empty. If no
value can be inferred, it returns failure() with the error "could not
infer a padding value"; the caller is then expected to determine the
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[docs] Prefer portable Markdown documentation links
Document and enforce source-relative Markdown links for documents and
generated heading anchors. Diagnose nonportable project: and generated HTML
links, and convert the existing LLVM Markdown links to the preferred form.
[UTC] Strip only standalone positional %s in update_test_checks.py (#221153)
Previously, update_test_checks.py used tool_cmd_args.replace("%s", "")
to strip the input file when passing the IR via stdin. However, this
blindly removed "%s" from any option argument, leaving an empty value
(e.g., -lowertypetests-read-summary=).
Update the argument stripping to only remove standalone positional
"< %s" or "%s", preserving option arguments with "%s" values so they can
be expanded via common substitutions.
This enables update_test_checks.py to work for tests such as
llvm/test/Transforms/LowerTypeTests/cfi-jumptable-hotness-summary.ll,
which passes -lowertypetests-read-summary=%s on the RUN line.
Assisted-by: Gemini
