[SPIR-V] Reject OpSelect with scalar result and vector condition (#193745)
Per SPIR-V spec, scalar Result Type requires a scalar bool condition.
So, vector cond branches under a scalar result are unreachable
[VPlan] Avoid erroneously marking PredPHI as using scalars (#195511)
PredInstPHIRecipe can use wide values, and indeed, we have several tests
demonstrating this behavior. Strip the erroenous always-true usesScalars
member, falling back to usesFirstLaneOnly as usual.
[CIR][AArch64] Lower vfmaq_v f32/f64 (#195602)
Lower `BI__builtin_neon_vfmaq_v` in CIR for the `vfmaq_f32` and
`vfmaq_f64` ACLE wrappers.
This is split out from the broader fused multiply-accumulate work and
only covers `BI__builtin_neon_vfmaq_v`. The related `vfma_v`,
`vfmaq_f16`, lane, laneq, and scalar forms remain outside this PR.
Tests move the existing `vfmaq_f32` and `vfmaq_f64` coverage from
`neon-intrinsics.c` into `neon/vfmaq.c`, preserve the original LLVM
checks, and add ClangIR coverage.
Validation: rebuilt `clang` and ran the focused `vfmaq.c` lit test.
Part of #185382
Split from feedback on #188190
[llvm][tools][llvm-objdump] Fix nested-offload-binary.test (#196912)
In little endian systems the embedded image hex is incorrect and the
test fails on Solaris/sparcv9.
Switching to generate the inner image on the fly and patch the outer
image CONTENT field.
DAGCombiner: (srl/sra (add nuw/nsw X, c), d) --> (add nuw/nsw (srl/sra X, d), c >> d)
Additional precondition:
* The LSBs of c are 0; equivalently: c >> d is exact
Alive2 for
* unsigned case: https://alive2.llvm.org/ce/z/YcJ8qA
* signed case: https://alive2.llvm.org/ce/z/fgpvyE
We already canonicalize (shl (add ...) ...) to (add (shl ...) ...).
Restrict this combine to the single-use case to minimize risk for now.
The main target of this combine is a fan-out tree of `add`s that all end
up being shifted by the same amount at the leaves. This change happens to
improve a bunch of existing CodeGen tests in AMDGPU.
v2:
- remove a redundant check on the shift amount -- large shift amounts
results in poison anyway
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[libc] Fix BigInt shift on big-endian platforms (#196957)
BigInt<128> stores the value in two separate word sized array slots
with the low 64 bits being stored in val[0] and high 64 bits in val[1].
This can't be reinterpreted as a 128 bit value on big-endian platforms
because the values are reversed.
This has caused test failures on s390x builds of V8:
https://issues.chromium.org/issues/511831894
---------
Co-authored-by: Guillaume Chatelet <gchatelet at google.com>
[flang][FIRToMemRef] [flang][fir-to-memref] Lower complex projected slices via memref<...x2xT> reinterpretation (#196123)
At the `fir.array_coor` site, reinterpret the
`memref<d0×...×complex<T>>` as `memref<d0×...×2×T>` via `fir.convert`,
then append the component index (0=re, 1=im) as the final memref index.
Loads and stores then operate directly on a scalar `T`-sized location.
[lldb] Handle SIGINT via the MainLoop signal thread (on POSIX) (#196687)
The driver's async SIGINT handler called
SBDebugger::DispatchInputInterrupt directly. That is not
async-signal-safe and can lead to a crash.
Register SIGINT with the existing signal-thread MainLoop instead so
DispatchInputInterrupt runs in normal thread context. The Windows path
is unchanged and keeps the legacy async handler.
While DispatchInputInterrupt runs, the callback temporarily installs
SIG_DFL so a second Ctrl-C still hard-terminates the process, preserving
the escape hatch users rely on when the debugger is unresponsive.
Moving SIGINT off the main thread means a Ctrl-C no longer interrupts
blocking syscalls there (e.g. a Python REPL waiting on input or
sleeping), so Python never observes the queued interrupt and
KeyboardInterrupt is not raised. To restore that behavior, after
dispatching the interrupt the callback re-raises SIGINT on the main
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