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[CIR] Implement function target/tune attrs and FMV metadata.

[MLIR] Fix offload map metadata order (#195346)

This fixes one part of
https://github.com/llvm/llvm-project/issues/195333.

There are two different semicolon-field orders in
offload/include/Shared/SourceInfo.h:

1. Per-map strings (`map_var_info_t`): first field is the mapped name,
second
is the file path:
```
/// Type alias for source location information for variable mappings with
/// data layout ";name;filename;row;col;;\0" from clang.
using map_var_info_t = void *;
```

2. `ident_t` region strings: first field is the file path, second is the
function name:

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[mlir][SPIR-V][NFC] Add pushCaps/pushExts helpers to type visitors (#195796)

Discussed in
https://github.com/llvm/llvm-project/pull/195060#discussion_r3183984853

[NFC][clang] InterpBuiltin.cpp - use consistent ia32 naming convention for all x86 builtin expansions (#195699)

Also, add IsAdd argument to interp__builtin_ia32_addcarry_subborrow instead of repeated builtinid comparisons

Sigh formatting is the bane of my existence

[AssumeBuilder] Fix incorrect nonnull optimization (#195676)

We can only optimize nonnull assumes to refer to the base of a GEP if
the GEP is inbounds.

From #195650.

Clean up some of the logic

[libc++][mdspan] Fix `mdspan::operator[]` bounds checking and implement LWG4020 (#192269)

This example fails to compile with libc++ in hardened mode without this
fix.
```c++
#include <mdspan>

struct RValueInt {
  constexpr operator int() && noexcept { return 0; }
};

int main() {
  int data[1] = {42};
  std::mdspan m(data, std::extents<int, 1>{1});

  m[RValueInt{}];
}
```

Fixes: #171311

[LV] Use isLegalMaskedLoadOrStore for interleaved accesses too (NFC)

isLegalMaskedLoadOrStore is now the central place for querying target
capabilities for masked accesses. Access pattern legality checks are
hoisted outside of it.

[clang][AST][NFC] const-correctness improvements for member functions returing `ArrayRef` (#195784)

- Add const qualifiers to member functions.
- Drop non-const-qualified member functions whose const-qualified
versions return same thing.

[LV] Introduce isLegalMaskedLoadOrStore (NFC) (#195242)

This simplifies legality checks, and eventually will become the single
point querying TTI hooks for masked ld/st. Currently, legality checks
for interleaved accesses still query TTI directly.

[AArch64][GlobalISel] Match G_DUP with undef elements (#195237)

This helps us match more vector splats that contain undef elements,
matching build vectors that contain undef so long as they contain at
least 2 duplicate entries.

[CIR][CUDA] Fix typed StringAttr on globals and Add CIR-to-LLVM lowering checks for existing registration support (#195002)

[AArch64][GlobalISel] Add gisel test coverage for addp-shuffles.ll. NFC (#195803)

[mlir][NFC] Fix typo (flattend => flattened) (#195780)

Merge branch 'main' into users/vitalybuka/spr/lit-use-dbg-instead-of-note-for-tool-detection

[clang][P2719] Relax requirements for matching operator new and delete

The most recent revision of P2719 introduced very strict rules about
matching parameter sets between type aware operators new and delete.

The intention was to resolve the classic "no matching operator delete
has been found so the object will silently leak" problem. The strict
rules however made deleting objects that had a placement new
"impossible".

I missed this however as all of our large scale tests involved
projects that were already using manually implemented allocators
(often trying to support type isolation). The problem with this from
a validation point of view is simple: all of these projects had
existing class scoped operators, and the untyped delete was silently
selected, avoiding the need for a non-placement type-aware delete
that would conflict with the placement cleanup delete.

The next revision of P2719 resolves this by removing the exact type

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[GlobalISel] Fast-path single reg loads and stores in IRTranslator (#195245)

IRTranslator::translateLoad is hot in compile-time profiles of sqlite on
aarch64-O0-g. Aggregates are flattened into multiple vregs with offsets.
Most loads and stores lower to a single register so this offset
materialization can be avoided.

Small -0.07% geomean improvement on aarch64-O0-g with -0.24% for sqlite.

https://llvm-compile-time-tracker.com/compare.php?from=a7a2dc59616a8cb1198d933bcdf55ebdbd78894c&to=e535e96fd0952cfa646d48ef84cf5948c0a8a2ab&stat=instructions%3Au

[GlobalISel] Fast-path single vreg values in getOrCreateVRegs (#195244)

IRTranslator::translateLoad is hot in compile-time profiles of sqlite on
aarch64-O0-g. Aggregates are flattened into multiple vregs with offsets.
Avoiding this path for single vregs is a small -0.11% compile-time win.

https://llvm-compile-time-tracker.com/compare.php?from=a7a2dc59616a8cb1198d933bcdf55ebdbd78894c&to=96fcfe733947db64effd5e1d1413697981cbe357&stat=instructions%3Au

[mlir][SPIR-V] Add Weak linkage type and SPV_AMD_weak_linkage extension (#195660)

- add 'Weak' linkage type (SPV_AMD_weak_linkage)
- deduce the Linkage capability and linkage-type extension from
linkage_attributes in UpdateVCE pass

---------

Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>

support device_type groupprivate lowering

[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features (#192142)

Profile-driven indirect call promotion was promoting indirect calls to
functions requiring advanced CPU features (e.g., AVX512) even when the
caller function did not support those features. When these promoted
calls were subsequently inlined, it could lead to invalid IR and
backend crashes during instruction selection because the target CPU
could not handle the advanced instructions.

This patch addresses the issue by adding a target feature
compatibility check to `llvm::isLegalToPromote` in
`CallPromotionUtils.cpp`. If the callee requires target features
(prefixed with `+`) that are not present in the caller's target
features, the promotion is skipped.  By centralizing this check in
`isLegalToPromote`, we protect all passes relying on this utility
(such as `SampleProfileLoader` and `IndirectCallPromotion`) from
promoting to incompatible targets. This also prevents incorrect
inlining of `always_inline` functions that would otherwise be promoted
via indirect calls and then inlined.

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[CIR][NFC] Rename SignBitOp to CIR_SignBitOp (#195477)

Align with the CIR_ prefix naming convention used by other op
definitions in CIROps.td.

[MLIR] Add HasAncestor op trait (#195447)

Add HasAncestor/AncestorOneOf traits that verify an operation has a
specific ancestor anywhere in the parent chain, unlike HasParent which
only checks the immediate parent.

fix libMLIRCAPIInterfaces after #195505 (#195789)

https://github.com/llvm/llvm-project/pull/195505 missed
`MLIRSideEffectInterfaces` in the CMakeLists.txt.

[orc-rt] Change SPS controller-interface naming conventions. (#195614)

This commit makes two changes to the naming conventions for SPS CI
symbols:

1. The orc_rt_sps_ci_ prefix is replaced with orc_rt_ci_sps_ (for SPS
wrapper functions) and orc_rt_ci_ (without the "sps_" suffix) for data
symbols.

2. The _sps_wrapper suffix is dropped from wrapper functions, since the
prefix now distinguishes between SPS-wrappers and data symbols.

Enable -print-file-name for flang

Rebase

Created using spr 1.3.6-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Address review comments

Created using spr 1.3.6-beta.1