LLVM/project 2d4acb0lldb/packages/Python/lldbsuite/test/make Makefile.rules, lldb/source/Plugins/SymbolFile/DWARF SymbolFileDWARF.cpp

LLDB Debuginfod tests and a fix or two (#90622)

I'm taking yet another swing at getting these tests going, on the
hypothesis that the problems with buildbots & whatnot are because
they're not configured with CURL support, which I've confirmed would
cause the previous tests to fail. (I have no access to an ARM64 linux
system, but I did repro the failure on MacOS configured without CURL
support)

So, the only difference between this diff and
[previous](https://github.com/llvm/llvm-project/pull/85693)
[diffs](https://github.com/llvm/llvm-project/pull/87676) that have
already been approved is that I've added a condition to the tests to
only run if Debuginfod capabilities should be built into the binary. I
had done this for these tests when they were [Shell
tests](https://github.com/llvm/llvm-project/pull/79181) and not API
tests, but I couldn't find a direct analog in any API test, so I used
the "plugins" model used by the intel-pt tests as well.


    [2 lines not shown]
DeltaFile
+192-0lldb/test/API/debuginfod/SplitDWARF/TestDebuginfodDWP.py
+183-0lldb/test/API/debuginfod/Normal/TestDebuginfod.py
+25-13lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+27-2lldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp
+25-1lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+23-0lldb/test/API/debuginfod/SplitDWARF/Makefile
+475-166 files not shown
+519-1712 files

LLVM/project e4bb663llvm/test/Transforms/SLPVectorizer/X86 arith-fp-call.ll

[SLP][X86] Add test coverage for rint/lrint/llrint fp calls
DeltaFile
+394-0llvm/test/Transforms/SLPVectorizer/X86/arith-fp-call.ll
+394-01 files

LLVM/project 49bac13llvm/test/Analysis/CostModel/X86 arith-fp.ll arith-fp-latency.ll

[CostModel][X86] Add test coverage for rint/lrint/llrint fp calls
DeltaFile
+273-0llvm/test/Analysis/CostModel/X86/arith-fp.ll
+273-0llvm/test/Analysis/CostModel/X86/arith-fp-latency.ll
+273-0llvm/test/Analysis/CostModel/X86/arith-fp-sizelatency.ll
+141-0llvm/test/Analysis/CostModel/X86/arith-fp-codesize.ll
+960-04 files

LLVM/project aa5ff68clang/lib/Sema SemaOverload.cpp, clang/test/SemaHLSL ScalarOverloadResolution.hlsl VectorElementOverloadResolution.hlsl

[HLSL] Shore up floating point conversions (#90222)

This PR fixes bugs in HLSL floating conversions. HLSL always has `half`,
`float` and `double` types, which promote in the order:

`half`->`float`->`double`

and convert in the order:

`double`->`float`->`half`

As with other conversions in C++, promotions are preferred over
conversions.

We do have floating conversions documented in the draft language
specification (https://microsoft.github.io/hlsl-specs/specs/hlsl.pdf
[Conv.rank.float]) although the exact language is still in flux
(https://github.com/microsoft/hlsl-specs/pull/206).

Resolves #81047
DeltaFile
+229-0clang/test/SemaHLSL/ScalarOverloadResolution.hlsl
+228-0clang/test/SemaHLSL/VectorElementOverloadResolution.hlsl
+42-1clang/lib/Sema/SemaOverload.cpp
+8-18clang/test/SemaHLSL/OverloadResolutionBugs.hlsl
+507-194 files

LLVM/project e06d6edllvm/lib/Transforms/IPO SampleProfileMatcher.cpp, llvm/test/Transforms/SampleProfile non-probe-stale-profile-matching.ll

[SamplePGO] Handle FS discriminators in SampleProfileMatcher (#90858)

Currently the code uses FunctionSamples::getCallSiteIdentifier which
will sometimes incorrectly guess that FSAFDO discriminators are probe
based and will convert them incorrectly.

This change doesn't affect builds which don't use FSAFDO, it only fixes
sample profile matching with FS discriminators.

The test for this is manually updated to use discriminator value 15,
which is a perfectly valid base discriminator in the FS world, but
satisfies `isPseudoProbeDiscriminator`, so
`getBaseDiscriminatorFromDiscriminator` will incorrectly extract the
probe index from it.

Note: this change only affects how the base discriminators will be
extracted when doing stale profile matching in the IR-level sample
profile loader. It doesn't add stale profile matching to the MIR-level
FS profile loader pass.
DeltaFile
+4-4llvm/test/Transforms/SampleProfile/non-probe-stale-profile-matching.ll
+4-2llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
+2-2llvm/test/Transforms/SampleProfile/Inputs/non-probe-stale-profile-matching.prof
+10-83 files

LLVM/project 5445a35llvm/lib/TargetParser RISCVISAInfo.cpp, llvm/unittests/TargetParser RISCVISAInfoTest.cpp

[RISCV] Detect empty extension name after parsing MajorVersion in parseNormalizedArchString. (#90790)

If the string is just a version, we will end up adding an empty string
as an extension which crashes in the compare function for the std::map.
DeltaFile
+8-0llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+4-0llvm/lib/TargetParser/RISCVISAInfo.cpp
+12-02 files

LLVM/project 1aeb64cclang/lib/AST/Interp Interp.h Program.cpp, clang/test/AST/Interp builtin-align-cxx.cpp c.c

Reapply "[clang][Interp] Create full type info for dummy pointers"

This reverts commit 6195e228eb2a7085fac53603f534d2401ab1ac39.
DeltaFile
+14-22clang/lib/AST/Interp/Interp.h
+12-9clang/lib/AST/Interp/Program.cpp
+1-14clang/test/AST/Interp/builtin-align-cxx.cpp
+0-8clang/lib/AST/Interp/Descriptor.cpp
+3-3clang/lib/AST/Interp/Descriptor.h
+3-0clang/test/AST/Interp/c.c
+33-566 files

LLVM/project 62c2959clang/www cxx_status.html

[clang] NFC: cxx_status mark P0522R0 as unreleased

Addressing post-commit review on #89807
DeltaFile
+2-2clang/www/cxx_status.html
+2-21 files

LLVM/project 4fd319allvm/lib/AsmParser LLParser.cpp, llvm/unittests/Analysis IRSimilarityIdentifierTest.cpp

Revert#2 "[RemoveDIs] Load into new debug info format by default in LLVM (#89799)"

Reverted following probably-causing failures on some clang buildbots:
  https://lab.llvm.org/buildbot/#/builders/245/builds/24037

This reverts commit a12622543de15df45fb9ad64e8ab723289d55169.
DeltaFile
+32-41llvm/unittests/IR/DebugInfoTest.cpp
+68-0llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
+4-56llvm/unittests/Transforms/Utils/LocalTest.cpp
+18-16llvm/lib/AsmParser/LLParser.cpp
+0-32llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
+6-6llvm/unittests/IR/IRBuilderTest.cpp
+128-15113 files not shown
+154-18619 files

LLVM/project 1c80d32clang/include/clang/Driver Options.td, clang/lib/Basic/Targets WebAssembly.cpp

[WebAssembly] Sort target features (NFC) (#90777)

DeltaFile
+84-84clang/lib/Basic/Targets/WebAssembly.cpp
+64-64clang/test/Driver/wasm-features.c
+41-39llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
+32-32llvm/lib/Target/WebAssembly/WebAssembly.td
+20-20clang/include/clang/Driver/Options.td
+16-16llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
+257-2551 files not shown
+266-2647 files

LLVM/project d7b4271libcxx/include/__chrono exception.h, libcxx/test/libcxx/time/time.zone/time.zone.exception/time.zone.exception.ambig assert.ctor.pass.cpp

[libc++][TZDB] Implements time_zone::to_sys.

This implements the throwing overload and the exception classes throw by
this overload.

Implements parts of:
- P0355 Extending chrono to Calendars and Time Zones
DeltaFile
+237-0libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/to_sys.pass.cpp
+172-0libcxx/test/std/time/time.zone/time.zone.exception/time.zone.exception.nonexist/ctor.pass.cpp
+171-0libcxx/test/std/time/time.zone/time.zone.exception/time.zone.exception.ambig/ctor.pass.cpp
+129-0libcxx/include/__chrono/exception.h
+53-0libcxx/test/libcxx/time/time.zone/time.zone.exception/time.zone.exception.nonexist/assert.ctor.pass.cpp
+53-0libcxx/test/libcxx/time/time.zone/time.zone.exception/time.zone.exception.ambig/assert.ctor.pass.cpp
+815-017 files not shown
+987-4423 files

LLVM/project 941eab1llvm/lib/TargetParser RISCVISAInfo.cpp, llvm/unittests/TargetParser RISCVISAInfoTest.cpp

[RISCV] Make parseNormalizedArchString only accept [a-z0-9_]. (#90815)

Previously we only rejected upper case characters. We should instead
reject anything except lower case, numbers, and underscore. Other
characters will likely confuse the extension sorting.
DeltaFile
+6-5llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+4-2llvm/lib/TargetParser/RISCVISAInfo.cpp
+10-72 files

LLVM/project eb82363llvm/lib/Target/AMDGPU AMDGPUInsertSingleUseVDST.cpp, llvm/test/CodeGen/AMDGPU insert-singleuse-vdst.mir

[AMDGPU] Group multiple single use producers under one single use instruction. (#90713)

Previously each single use producer would be marked with a
"S_SINGLEUSE_VDST 1" instruction. This patch adds support for
larger immediates that encode multiple single use producers into
one S_SINGLEUSE_VDST instruction.
DeltaFile
+526-14llvm/test/CodeGen/AMDGPU/insert-singleuse-vdst.mir
+113-11llvm/lib/Target/AMDGPU/AMDGPUInsertSingleUseVDST.cpp
+639-252 files

LLVM/project e71eaccmlir/lib/Dialect/SparseTensor/IR SparseTensorDialect.cpp CMakeLists.txt, mlir/lib/Dialect/SparseTensor/Transforms/Utils CodegenUtils.h

[mlir][sparse] Support explicit/implicit value for complex type (#90771)

DeltaFile
+14-6mlir/test/Dialect/SparseTensor/sparse_matmul_one.mlir
+15-0mlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir
+6-3mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.h
+5-0mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
+1-0mlir/lib/Dialect/SparseTensor/IR/CMakeLists.txt
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+42-96 files

LLVM/project e7d6f33lld/ELF/Arch RISCV.cpp

Rebase

Created using spr 1.3.4
DeltaFile
+4-4lld/ELF/Arch/RISCV.cpp
+4-41 files

LLVM/project 2e1b3c8lld/ELF/Arch RISCV.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+4-4lld/ELF/Arch/RISCV.cpp
+4-41 files

LLVM/project 0708500clang/lib/AST ASTContext.cpp

[Clang] Remove bogus assert in are[Lax]CompatibleSveTypes()

This caused an assertion failure for the following input:

  __SVInt32_t bar(__SVInt32_t x);

  void foo(__SVInt32_t x) {
    return bar(x);
  }
DeltaFile
+0-10clang/lib/AST/ASTContext.cpp
+0-101 files

LLVM/project 907f6f0lld/ELF/Arch RISCV.cpp

git clang-format

Created using spr 1.3.4
DeltaFile
+4-4lld/ELF/Arch/RISCV.cpp
+4-41 files

LLVM/project 4464599clang/test/Preprocessor riscv-target-features.c, llvm/docs RISCVUsage.rst

[RISCV] Add smstateen extension (#90818)

DeltaFile
+9-0clang/test/Preprocessor/riscv-target-features.c
+4-0llvm/test/CodeGen/RISCV/attributes.ll
+3-0llvm/lib/Target/RISCV/RISCVFeatures.td
+3-0llvm/test/MC/RISCV/attribute-arch.s
+1-0llvm/docs/RISCVUsage.rst
+1-0llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+21-01 files not shown
+22-07 files

LLVM/project a6e722flld/ELF/Arch RISCV.cpp, lld/test/ELF riscv-attributes.s

Rebase

Created using spr 1.3.4
DeltaFile
+4-5lld/ELF/Arch/RISCV.cpp
+1-2lld/test/ELF/riscv-attributes.s
+5-72 files

LLVM/project c33acealld/ELF/Arch RISCV.cpp, lld/test/ELF riscv-attributes.s

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+4-5lld/ELF/Arch/RISCV.cpp
+1-2lld/test/ELF/riscv-attributes.s
+5-72 files

LLVM/project 849a8belld/ELF/Arch RISCV.cpp, lld/test/ELF riscv-attributes.s

Remove braces and clean up LLD test

Created using spr 1.3.4
DeltaFile
+4-5lld/ELF/Arch/RISCV.cpp
+1-2lld/test/ELF/riscv-attributes.s
+5-72 files

LLVM/project a131525flang/lib/Semantics expression.cpp, flang/test/Semantics cuf13.cuf

[flang][cuda] Compute matching distance in generic resolution (#90774)

Implement the matching distance as described here:
https://docs.nvidia.com/hpc-sdk/archive/24.3/compilers/cuda-fortran-prog-guide/index.html#cfref-var-attr-unified-data

Generic resolved to the smallest distance.
DeltaFile
+103-6flang/lib/Semantics/expression.cpp
+22-8flang/test/Semantics/cuf13.cuf
+125-142 files

LLVM/project 520cccallvm/lib/Target/PowerPC PPCISelDAGToDAG.cpp, llvm/lib/Target/PowerPC/MCTargetDesc PPCMCTargetDesc.cpp

NFC: fix clang format spacing and documentation (#90775)

Some minor fixes to clean up tabs and language in code documentation.
DeltaFile
+19-19llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
+8-9llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+27-282 files

LLVM/project 0638e22llvm/include/llvm/CodeGen SDPatternMatch.h, llvm/unittests/CodeGen SelectionDAGPatternMatchTest.cpp

[SDPatternMatch] Add m_CondCode, m_NoneOf, and some SExt improvements (#90762)

  - Add m_CondCode to match the ISD::CondCode value from CondCodeSDNode
  - Add m_NoneOf combinator
  - m_SExt now recognizes sext_inreg
DeltaFile
+63-10llvm/include/llvm/CodeGen/SDPatternMatch.h
+13-0llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+76-102 files

LLVM/project fbaba78lldb/test/API/functionalities/gdb_remote_client TestGDBRemoteLoad.py

[lldb][test][FreeBSD] Remove xfails from TestGDBRemoteLoad (#84026)

Fixes #48758

These are now passing on AArch64 FreeBSD 14.
DeltaFile
+0-9lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteLoad.py
+0-91 files

LLVM/project d11afe1llvm/lib/Target/SystemZ SystemZInstrInfo.cpp, llvm/test/CodeGen/SystemZ copy-phys-reg-gr128-to-fp128.mir

SystemZ: Handle gr128 to fp128 copies in copyPhysReg (#90861)

DeltaFile
+49-0llvm/test/CodeGen/SystemZ/copy-phys-reg-gr128-to-fp128.mir
+16-0llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+65-02 files

LLVM/project eb3a671llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-ld2-alloca.ll sve-streaming-mode-fixed-length-shuffle.ll

[AArch64] Avoid vector interleave instructions when NEON and SVE are unavailable (#90723)

As the summary suggests, the code incorrectly assumes that it can use
NEON or SVE instructions to implement an interleaved load/store
operation, even when both features are unavailable in the selected
runtime mode.
DeltaFile
+84-20llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
+29-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
+14-13llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+127-333 files

LLVM/project a126225llvm/lib/AsmParser LLParser.cpp, llvm/unittests/Analysis IRSimilarityIdentifierTest.cpp

Reapply "[RemoveDIs] Load into new debug info format by default in LLVM (#89799)"

Fixes the broken tests in the original commit:
  2f01fd99eb8c8ab3db9aba72c4f00e31e9e60a05

This will probably break some downstream tools that don't already handle
debug records. If your downstream code breaks as a result of this
change, the simplest fix is to convert the module in question to the old
debug format before you process it, using
`Module::convertFromNewDbgValues()`. For more information about how to
handle debug records or about what has changed, see the migration
document:
  https://llvm.org/docs/RemoveDIsDebugInfo.html

This reverts commit 00821fed09969305b0003d3313c44d1e761a7131.
DeltaFile
+41-32llvm/unittests/IR/DebugInfoTest.cpp
+0-68llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
+56-4llvm/unittests/Transforms/Utils/LocalTest.cpp
+16-18llvm/lib/AsmParser/LLParser.cpp
+32-0llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
+6-6llvm/unittests/IR/IRBuilderTest.cpp
+151-12813 files not shown
+186-15419 files

LLVM/project f5b4e20llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

[llvm][AArch64] Fix Arm 32 bit build warnings (#90862)

https://github.com/llvm/llvm-project/pull/84173 added uses of std::labs
on an int64_t which leads to this warning on Arm 32 bit:
```
/home/david.spickett/llvm-project/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16655:12: warning: absolute value function 'labs' given an argument of type 'long long' but has parameter of type 'long' which may cause truncation of value [-Wabsolute-value]
    return std::labs(Imm / 4) <= 16;
           ^
/home/david.spickett/llvm-project/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16655:12: note: use function 'std::abs' instead
    return std::labs(Imm / 4) <= 16;
           ^~~~~~~~~
           std::abs
```

Since int64_t is "long long" on Arm, not "long".

Use std::abs instead since it has versions for "long" and "long long",
we'll pick up the right one at compile time
(https://en.cppreference.com/w/cpp/numeric/math/abs).
DeltaFile
+3-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+3-31 files