LLVM / project - FreshBSD

LLVM/project d8faf7f — llvm/include/llvm/Support GenericDomTreeConstruction.h, llvm/unittests/Support GenericDomTreeTest.cpp

2026-07-25 08:38:29 UTC by Alexis Engelke on ⎇

users/aengelke/spr/domtreeconstrnfc-resize-nodeinfos-once-on-construction

[spr] initial version

Created using spr 1.3.8-wip

Delta		File
+18	-17	llvm/include/llvm/Support/GenericDomTreeConstruction.h
+0	-5	llvm/unittests/Support/GenericDomTreeTest.cpp
+18	-22	2 files

LLVM/project 068ec1a — clang/lib/CodeGen CGBuiltin.cpp, clang/test/CodeGen builtin-clear-padding-codegen.c

2026-07-25 08:35:45 UTC by Hui via GitHub on ⎇

main

[clang] fix __builtin_clear_padding not working with virtual base pointers on Windows (#211355)

Fixes https://github.com/llvm/llvm-project/issues/209787
It was an oversight that the builtin only takes care of the virtual
function table pointer but not the virtual base pointer. On Itanium
there is one pointer so it wasn't a problem but on windows msvc , this
is a problem. And the runtime test in libcxx CI was disabled in llvm 23
because we don't use trunk clang in our libcxx CI in general. and after
we flipped to llvm 24, the test started to fail on downstream (chromium)
where they use trunk clang with trunk libc++ on Windows.

We do have FileCheck test in clang test which covers this virtual case.
However, the target triple in the FileCheck under test were
`x86_64-linux-gnu` and `x86_64-windows-gnu` , which does not cover the
Windows msvc ABI. I updated the test to test `x86_64-pc-windows-msvc` in
this PR to cover that ABI.

Delta		File
+598	-627	clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+317	-471	clang/test/CodeGen/builtin-clear-padding-codegen.c
+7	-0	clang/lib/CodeGen/CGBuiltin.cpp
+922	-1,098	3 files

LLVM/project ddc72e6 — llvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine cast_ptr.ll

2026-07-25 08:34:40 UTC by Alexis Engelke on ⎇

users/aengelke/spr/instcombine-fold-icmp-ptrtoaddr-x-ptrtoaddr-y-icmp-x-y

more tests

Created using spr 1.3.8-wip

Delta		File
+57	-0	llvm/test/Transforms/InstCombine/cast_ptr.ll
+2	-0	llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+59	-0	2 files

LLVM/project b9c05ca — llvm/lib/Analysis ScalarEvolution.cpp

2026-07-25 08:23:02 UTC by Vitaly Buka via GitHub on ⎇

main

[SCEV] Fix MSan uninitialized value in createSCEV (#211996)

In #180244 (8e76c3f0d29a), handling of Instruction::Sub in
createSCEV declared PtrLHS and PtrRHS as uninitialized local variables.
When only one side matched m_PtrToInt, the other variable remained
uninitialized. Passing it by value to GetOp copied uninitialized shadow
bytes, causing MemorySanitizer to report use-of-uninitialized-value.

Initialize PtrLHS and PtrRHS to nullptr upon declaration.

Assisted-by: Gemini

Delta		File
+1	-1	llvm/lib/Analysis/ScalarEvolution.cpp
+1	-1	1 files

LLVM/project f539edf — llvm/include/llvm/LTO/legacy ThinLTOCodeGenerator.h, llvm/lib/LTO ThinLTOCodeGenerator.cpp

2026-07-25 08:01:24 UTC by Xiaoyang Gong via GitHub on ⎇

main

[LTO] Include debug options in legacy ThinLTO cache keys (#211474)

Legacy ThinLTO omits -mllvm options from cache keys, which can cause it
to reuse objects built with different code-generation settings.

Include these options in cache keys, matching modern ThinLTO behavior.

Delta		File
+43	-0	llvm/test/tools/lto/legacy-thinlto-cache-key.ll
+8	-0	llvm/include/llvm/LTO/legacy/ThinLTOCodeGenerator.h
+6	-1	llvm/tools/lto/lto.cpp
+4	-2	llvm/lib/LTO/ThinLTOCodeGenerator.cpp
+61	-3	4 files

LLVM/project 43da8ef — llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/PhaseOrdering/X86 fmaddsub.ll

2026-07-25 07:49:29 UTC by Simon Pilgrim via GitHub on ⎇

main

Revert "[VectorCombine] Fold binop(shuffle(V1, Mask), shuffle(V2, Mask)) -> shuffle(binop(V1, V2), Mask)" (#211994)

Reverts llvm/llvm-project#211530 while I investigate some compilation timeouts

Delta		File
+64	-27	llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
+0	-69	llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+9	-8	llvm/test/Transforms/VectorCombine/X86/shuffletoidentity-bitcast.ll
+4	-3	llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
+4	-2	llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll
+3	-2	llvm/test/Transforms/VectorCombine/pr197910.ll
+84	-111	6 files

LLVM/project e50a4d2 — llvm/lib/Analysis ScalarEvolution.cpp

2026-07-25 07:45:22 UTC by Vitaly Buka on ⎇

users/vitalybuka/spr/scev-fix-msan-uninitialized-value-in-createscev

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

Delta		File
+1	-1	llvm/lib/Analysis/ScalarEvolution.cpp
+1	-1	1 files

LLVM/project 3055342 — clang/test/SemaOpenCL builtins-amdgcn-error-gfx12.cl builtins-amdgcn-global-load-store-target-error.cl

2026-07-25 07:30:57 UTC by Matt Arsenault via GitHub on ⎇

main

clang/AMDGPU: Migrate cc1 tests to subarch triples (9) (#211954)

Delta		File
+8	-8	clang/test/SemaOpenCL/builtins-amdgcn-error-gfx12.cl
+6	-6	clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-target-error.cl
+5	-5	clang/test/SemaOpenCL/builtins-amdgcn-raw-ptr-buffer-load-lds-target-error.cl
+5	-5	clang/test/SemaOpenCL/builtins-amdgcn-error-gfx10.cl
+5	-5	clang/test/SemaOpenCL/builtins-amdgcn-cmp-deprecated.cl
+4	-4	clang/test/SemaOpenCL/builtins-amdgcn-wave32-func-attr.cl
+33	-33	42 files not shown
+93	-91	48 files

LLVM/project 0818e7f — llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/PhaseOrdering/X86 fmaddsub.ll

2026-07-25 07:15:10 UTC by Simon Pilgrim via GitHub on ⎇

revert-211530-vectorcombine-binop-of-shuffles

Revert "[VectorCombine] Fold binop(shuffle(V1, Mask), shuffle(V2, Mask)) -> s…"

This reverts commit b7fa8b21227c7c6a1c625db9ceab4acb485c2e6b.

Delta		File
+64	-27	llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
+0	-69	llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+9	-8	llvm/test/Transforms/VectorCombine/X86/shuffletoidentity-bitcast.ll
+4	-3	llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
+4	-2	llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll
+3	-2	llvm/test/Transforms/VectorCombine/pr197910.ll
+84	-111	6 files

LLVM/project a6d9e7e — llvm/test/TableGen ProcessorAlias.td, llvm/utils/TableGen SubtargetEmitter.cpp

2026-07-25 06:25:26 UTC by Matt Arsenault on ⎇

users/arsenm/mc-cpu-alias-compact-table

sort

Delta		File
+10	-3	llvm/utils/TableGen/SubtargetEmitter.cpp
+2	-1	llvm/test/TableGen/ProcessorAlias.td
+12	-4	2 files

LLVM/project db06c0e — llvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine cast_ptr.ll

2026-07-25 06:21:11 UTC by Alexis Engelke on ⎇

users/aengelke/spr/instcombine-fold-icmp-ptrtoaddr-x-ptrtoaddr-y-icmp-x-y

[spr] initial version

Created using spr 1.3.8-wip

Delta		File
+57	-0	llvm/test/Transforms/InstCombine/cast_ptr.ll
+6	-1	llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+63	-1	2 files

LLVM/project 943d649 — clang/test/SemaHIP builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip amdgpu-feature-builtins-return-type-deduction.hip

2026-07-25 06:20:47 UTC by Matt Arsenault via GitHub on ⎇

main

clang/AMDGPU: Migrate cc1 tests to subarch triples (8) (#211870)

Rewrite SemaHIP cc1 test RUN lines to the new subarch triple form,
dropping the redundant -target-cpu.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

Delta		File
+2	-2	clang/test/SemaHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
+2	-2	clang/test/SemaHIP/amdgpu-feature-builtins-return-type-deduction.hip
+2	-2	clang/test/SemaHIP/amdgpu-builtin-in-lambda.hip
+2	-2	clang/test/SemaHIP/amdgpu-builtin-in-lambda-with-unsupported-attribute.hip
+1	-1	clang/test/SemaHIP/builtins-amdgcn-raw-buffer-atomic-add.hip
+1	-1	clang/test/SemaHIP/builtins-amdgcn-raw-buffer-atomic-fmin-max.hip
+10	-10	15 files not shown
+25	-25	21 files

LLVM/project 38f619c — llvm/include/llvm/MC MCSubtargetInfo.h, llvm/lib/CodeGen TargetSubtargetInfo.cpp

2026-07-25 06:18:22 UTC by Matt Arsenault on ⎇

users/arsenm/mc-cpu-alias-compact-table

TableGen: Use a compact table for CPU aliases

Previously each ProcessorAlias was emitted as a full SubtargetSubTypeKV
entry in the processor subtype table, duplicating the canonical
processor's feature masks and scheduling model index. At 104 bytes per
entry: AArch64's 18 aliases added ~1.8KB, and X86 will add more as aliases
are introduced.

Emit aliases into a separate SubtargetSubTypeAliasKV table instead. Each
alias is just a name string offset plus the index of the canonical
processor it resolves to.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+88	-46	llvm/utils/TableGen/SubtargetEmitter.cpp
+29	-6	llvm/include/llvm/MC/MCSubtargetInfo.h
+21	-9	llvm/lib/MC/MCSubtargetInfo.cpp
+18	-11	llvm/test/TableGen/ProcessorAlias.td
+6	-6	llvm/lib/CodeGen/TargetSubtargetInfo.cpp
+3	-3	llvm/unittests/CodeGen/MFCommon.inc
+165	-81	4 files not shown
+172	-87	10 files

LLVM/project 5fb4910 — llvm/lib/Target/X86 X86.td

2026-07-25 06:17:45 UTC by Matt Arsenault on ⎇

users/arsenm/x86/use-ProcessorAlias

X86: Use ProcessorAlias for duplicated processor names

Many X86 processors were defined multiple times under different names,
emitting an identical ProcessorModel for each spelling and duplicating
the feature masks, tune features, and scheduling model index in the subtype
table.

Define each processor once under its canonical name and express the
alternate spellings with ProcessorAlias, using the tablegen alias
mechanism. This deduplicates the redundant subtype table entries and saves
about 4.6k with the new alias table.

Co-Authored-By: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+116	-131	llvm/lib/Target/X86/X86.td
+116	-131	1 files

LLVM/project 58651fb — llvm/lib/Target/AMDGPU GCNProcessors.td

2026-07-25 06:17:45 UTC by Matt Arsenault on ⎇

users/arsenm/amdgpu/use-ProcessorAlias

AMDGPU: Use ProcessorAlias for legacy arch names

Older targets have aliasing names which were previously implemented
by defining a second copy of the processor, identical except for the name
Use the recently improved tablegen mechanism for defining name-only aliases.
This dedupliates some redundant table entries, like the sched model.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+18	-60	llvm/lib/Target/AMDGPU/GCNProcessors.td
+18	-60	1 files

LLVM/project 790c44c — llvm/lib/Target/X86 X86.td

2026-07-25 06:17:45 UTC by Matt Arsenault on ⎇

users/arsenm/x86/use-ProcessorAlias

pentium alias

Delta		File
+2	-2	llvm/lib/Target/X86/X86.td
+2	-2	1 files

LLVM/project 4792e54 — llvm/include/llvm/MC MCSubtargetInfo.h, llvm/include/llvm/Target Target.td

2026-07-25 06:17:42 UTC by Matt Arsenault on ⎇

users/arsenm/mc/tablegen-support-cpu-aliases

TableGen: Add first class support for processor aliases

Previously isCPUStringValid was virtual so TableGen could emit an
AArch64 specific hack for recognizing cpu aliases. Teach tablegen
about aliases, and insert each alias into the CPU subtype table as its
own entry (sorted by name, carrying the canonical processor's features
and scheduling model).

There is further opportunity for code sharing improvements. AArch64's
aliases are consumed by ARMTargetDefEmitter to emit a custom inc file
in TargetParser which should be universalized.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+44	-43	llvm/utils/TableGen/SubtargetEmitter.cpp
+34	-0	llvm/test/TableGen/ProcessorAliasErrors.td
+24	-0	llvm/test/TableGen/ProcessorAlias.td
+7	-0	llvm/include/llvm/Target/Target.td
+0	-6	llvm/lib/Target/AArch64/AArch64Processors.td
+1	-1	llvm/include/llvm/MC/MCSubtargetInfo.h
+110	-50	6 files

LLVM/project 9184bb0 — llvm/include/llvm/IR PassManagerInternal.h PassManager.h

2026-07-25 06:03:35 UTC by Alexis Engelke via GitHub on ⎇

main

[IR][NFC] Remove vtables from analysis passes (#211864)

Similar to #209414 but for AnalysisPassConcept. This avoids vtables for
every analysis pass.

Delta		File
+57	-38	llvm/include/llvm/IR/PassManagerInternal.h
+2	-2	llvm/include/llvm/IR/PassManager.h
+2	-1	llvm/include/llvm/IR/PassManagerImpl.h
+61	-41	3 files

LLVM/project 6436ba9 — llvm/lib/Transforms/Instrumentation AddressSanitizer.cpp, llvm/test/Instrumentation/AddressSanitizer asan-detect-invalid-pointer-pair.ll

2026-07-25 05:49:55 UTC by Alexis Engelke on ⎇

users/aengelke/spr/asan-instrument-ptrtoaddr-as-pointer-difference

[spr] initial version

Created using spr 1.3.8-wip

Delta		File
+13	-0	llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll
+1	-1	llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+14	-1	2 files

LLVM/project 678ee28 — llvm/lib/Target/AArch64 SVEShuffleOpts.cpp AArch64.h

2026-07-25 05:43:49 UTC by Aiden Grossman on ⎇

users/boomanaiden154/main.thinlto-mark-assignguidpass-as-requiredpassinfomixin

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]

Delta		File
+3	-3	llvm/lib/Target/AArch64/SVEShuffleOpts.cpp
+3	-2	llvm/lib/Target/AArch64/AArch64.h
+3	-1	llvm/lib/Target/AArch64/AArch64PassRegistry.def
+9	-6	3 files

LLVM/project 217af2f — llvm/include/llvm/Transforms/Utils AssignGUID.h, llvm/lib/Target/AArch64 SVEShuffleOpts.cpp AArch64.h

2026-07-25 05:43:49 UTC by Aiden Grossman on ⎇

users/boomanaiden154/thinlto-mark-assignguidpass-as-requiredpassinfomixin

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

Delta		File
+3	-3	llvm/lib/Target/AArch64/SVEShuffleOpts.cpp
+3	-2	llvm/lib/Target/AArch64/AArch64.h
+1	-3	llvm/include/llvm/Transforms/Utils/AssignGUID.h
+3	-1	llvm/lib/Target/AArch64/AArch64PassRegistry.def
+10	-9	4 files

LLVM/project 02fa1be — llvm/include/llvm/CodeGen MachineCheckDebugify.h, llvm/include/llvm/Transforms/Scalar AlignmentFromAssumptions.h LogicalSROA.h

2026-07-25 05:41:25 UTC by Aiden Grossman via GitHub on ⎇

main

[Passes] Replace PassInfoMixin with {Optional,Required}PassInfoMixin

There were a couple passes that landed after the mass migration that
need to be updated to eventually make PassInfoMixin private. For backend
passes I looked at whether LegacyPM passes called skipFunction rather
than whether or not they should be enabled to try and preserve existing
behavior where possible.

We still need to wait a bit in order to avoid PassInfoMixin to a detail
namespace and fully remove isRequired from PassInfoMixin given there are
a lot of out-of-tree passes that have not yet been moved over. I'm
hoping to have patches out within a week.

Reviewers: arsenm, aeubanks

Pull Request: https://github.com/llvm/llvm-project/pull/211874

Delta		File
+6	-4	llvm/lib/Target/AArch64/AArch64.h
+3	-2	llvm/lib/Target/Lanai/Lanai.h
+2	-1	llvm/lib/Target/MSP430/MSP430.h
+1	-1	llvm/include/llvm/CodeGen/MachineCheckDebugify.h
+1	-1	llvm/include/llvm/Transforms/Scalar/AlignmentFromAssumptions.h
+1	-1	llvm/include/llvm/Transforms/Scalar/LogicalSROA.h
+14	-10	3 files not shown
+17	-13	9 files

LLVM/project ac0fbaa — flang/lib/Lower ConvertExpr.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll maximumnum.ll

2026-07-25 05:39:39 UTC by Alexis Engelke on ⎇

users/aengelke/spr/clangcodegen-use-ptrtoaddr-for-pointer-diff

rebase + fwrapv-pointer

Created using spr 1.3.8-wip

Delta		File
+13,068	-0	llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+6,560	-6,119	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,575	-5,393	llvm/test/CodeGen/AMDGPU/maximumnum.ll
+5,454	-5,259	llvm/test/CodeGen/AMDGPU/minimumnum.ll
+4,728	-4,968	llvm/test/CodeGen/AMDGPU/bf16.ll
+0	-7,750	flang/lib/Lower/ConvertExpr.cpp
+35,385	-29,489	6,099 files not shown
+231,076	-190,446	6,105 files

LLVM/project bcd5798 — clang/lib/StaticAnalyzer/Checkers/RetainCountChecker RetainCountDiagnostics.cpp

2026-07-25 05:21:07 UTC by Hardik Kumar via GitHub on ⎇

main

[clang][NFC]Remove unused variable (#211983)

The patch resolves the following warning.
```bash
clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/RetainCountDiagnostics.cpp:504:16: warning: variable ‘i’ set but not used [-Wunused-but-set-variable=]
  504 |       unsigned i = 0;
      |                ^
```

A count variable was set and incremented inside of a for loop but never
actually used inside of the loop or anywhere else in its scope.

Delta		File
+1	-3	clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/RetainCountDiagnostics.cpp
+1	-3	1 files

LLVM/project 9881786 — llvm/lib/Target/AArch64 AArch64InstrInfo.cpp SVEInstrFormats.td, llvm/lib/Target/AArch64/MCTargetDesc AArch64MCTargetDesc.h

2026-07-25 05:20:16 UTC by David Green via GitHub on ⎇

main

[AArch64] Add a OPERAND_IMM_UINT1 operand type (#211986)

Delta		File
+6	-0	llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+3	-0	llvm/test/CodeGen/AArch64/verify-imm.mir
+3	-0	llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+2	-0	llvm/lib/Target/AArch64/SVEInstrFormats.td
+1	-0	llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
+15	-0	5 files

LLVM/project d7f6d6b — llvm/include/llvm/IR PassManagerInternal.h

2026-07-25 05:16:24 UTC by Alexis Engelke on ⎇

users/aengelke/spr/irnfc-remove-vtables-from-analysis-passes

remove private

Created using spr 1.3.8-wip

Delta		File
+0	-1	llvm/include/llvm/IR/PassManagerInternal.h
+0	-1	1 files

LLVM/project bf7b5a0 — clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenAtomic.cpp

2026-07-25 04:22:52 UTC by Sirui Mu via GitHub on ⎇

main

[CIR] Add support for atomic fmaximum/fminimum/fmaximumnum/fminimumnum (#211845)

This patch adds CIR support for the following atomic builtin functions:

- `__atomic_fetch_fmaximum`
- `__atomic_fetch_fminimum`
- `__atomic_fetch_fmaximumnum`
- `__atomic_fetch_fminimumnum`

The scoped versions of these atomic builtin functions are supported as
well.

Specifically, this patch contains the following changes:

- It updates the `cir.atomic.fetch` operation and adds new fetch
operators including `maximum`, `minimum`, `maximumnum`, and
`minimumnum`. These operators accept floating-point inputs only.
- It updates the LLVM lowering of the `cir.atomic.fetch` operation. The
LLVM lowering now will lower `maximum`, `minimum`, `maximumnum`, and

    [6 lines not shown]

Delta		File
+84	-0	clang/test/CIR/CodeGen/atomic-scoped.c
+60	-0	clang/test/CIR/CodeGen/atomic.c
+36	-9	clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
+24	-2	clang/include/clang/CIR/Dialect/IR/CIROps.td
+16	-2	clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+14	-1	clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+234	-14	1 files not shown
+243	-15	7 files

LLVM/project cd7d586 — llvm/docs LangRef.md

2026-07-25 03:55:03 UTC by Harrison Hao on ⎇

users/harrisonGPU/store-atomic-elementwise

Update doc

Delta		File
+5	-5	llvm/docs/LangRef.md
+5	-5	1 files

LLVM/project 339792f — mlir/include/mlir-c ExtensibleDialect.h, mlir/include/mlir/Bindings/Python IRCore.h

2026-07-25 03:42:02 UTC by Twice via GitHub on ⎇

main

[MLIR][Python] Support IsIsolatedFromAbove trait for python-defined operations (#211849)

This PR adds dynamic `IsIsolatedFromAbove` trait support and exposes it
to Python as `IsIsolatedFromAboveTrait`.

The test verifies that a region with the trait cannot capture an SSA
value from above, while a region without the trait can.

Assisted by Codex/GPT 5.6 Sol (for writing test cases).

Delta		File
+63	-0	mlir/test/python/dialects/ext.py
+23	-0	mlir/lib/Bindings/Python/IRCore.cpp
+9	-0	mlir/include/mlir-c/ExtensibleDialect.h
+8	-0	mlir/lib/CAPI/IR/ExtensibleDialect.cpp
+8	-0	mlir/include/mlir/IR/ExtensibleDialect.h
+6	-0	mlir/include/mlir/Bindings/Python/IRCore.h
+117	-0	6 files

LLVM/project c64a5b0 — clang/bindings/python/clang cindex.py, clang/bindings/python/tests/cindex test_code_completion.py test_enums.py

2026-07-25 03:38:13 UTC by Jannick Kremer via GitHub on ⎇

main

[libclang/python] Remove CompletionString.AvailabilityKindCompat (#210682)

This completes the fourth step of
https://github.com/llvm/llvm-project/pull/156680
This change is a follow-up to
https://github.com/llvm/llvm-project/pull/160296, following the release
branching, to ensure a one release-cycle deprecation period.

---------

Co-authored-by: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>

Delta		File
+16	-72	clang/bindings/python/tests/cindex/test_code_completion.py
+2	-48	clang/bindings/python/clang/cindex.py
+4	-0	clang/docs/ReleaseNotes.md
+0	-1	clang/bindings/python/tests/cindex/test_enums.py
+22	-121	4 files