[llvm][RISCV] Revise xsfmm intrinsic interface. (#201527)
This patch does 2 things:
1. Change matmul interface to use newly defined OFP8 RVV types.
2. change all of matmul overloaded interfaces to only keep only widen
information and eliminate types information.
[clang][RISCV] Handle VLS CC on unsupported primitive type in aggregate type (#203898)
We handled this for pure vector type before but missed the aggregate
types, this patch try to apply same mechanism on them where unsupported
vector types are converted to same size i8 vector types.
[lld-macho] Relax safe ICF's keepUnique for ld64-coalesced data sections (#193125)
#188400 regressed data-section folding under --icf=safe{,_thunks}:
no-addrsig fallback, and over-broad compiler-emitted addrsig entries
covering data symbols, both caused markSymAsAddrSig to set keepUnique on
data sections, after which foldIdenticalSections refused to fold them.
ld64 coalesces __cfstring, __objc_classrefs and __objc_selrefs
unconditionally regardless of addrsig, so ignore keepUnique for them as
a workaround for the imprecise addrsig payload.
[orc-rt]R Align scope-exit with LLVM (rename to scope_exit, use CTAD) (#205020)
This renames the orc_rt::detail::ScopeExitRunner class to
orc_rt::scope_exit and adds a class template argument deduction guide.
[AtomicExpand] Add bitcasts when expanding store atomic vector (#197862)
AtomicExpand fails for aligned `store atomic <n x T>` because it
does not find a compatible library call. This change adds appropriate
ptrtoint + bitcast so that the call can be lowered, mirroring the
load-side handling.
Store-side counterpart to #148900. Stacked on top of
https://github.com/llvm/llvm-project/pull/201566.
[orc-rt] Add InProcessControllerAccess class. (#204976)
Adds a Session::ControllerAccess implementation for in-process JIT
setups, where the controller (LLVM-side) and the executor (orc-rt) live
in the same address space.
The two sides communicate through a refcounted C-ABI struct (Connection)
of function pointers. The C-only interface avoids assuming a common C++
ABI between the two sides and supports symmetric, graceful disconnect:
when either side calls Connection::Disconnect, in-flight cross-calls are
drained and pending continuations are surfaced as out-of-band errors,
after which further cross-calls fail cleanly.
This is intended to be paired with a new ExecutorProcessControl
implementation (llvm::orc::InProcessEPC) on the LLVM side, landing in a
follow-up commit. Unit tests are included covering construction without
connect, attach via Session, OnConnect-failure detach, successful and
out-of-band-error call cases, and the disconnect-drains-pending
behavior.
[libc][math] Extend iscanonical macro to _Float16 and float128
iscanonical is a C23 type-generic macro, so the f16/f128 variants are
surfaced through it rather than as functions in the generated math.h.
float128 is only listed when distinct from long double (LDBL_MANT_DIG !=
113) to avoid two _Generic associations with compatible types.
[libc][math] Fix aarch64 Darwin fenv implementation for full builds
A full build replaces the system (Apple) <fenv.h> with libc's headers, so
fenv_darwin_impl.h no longer found an 8-byte fenv_t, FE_FLUSHTOZERO, or the
__fpcr_* masks it relied on. Size FPState to the fenv_t in scope, alias
FE_FLUSHTOZERO to FE_DENORM, and define the FPCR trap masks locally.
[VPlan] Use pattern matching in isUsedByLoadStoreAddress (NFC) (#205008)
Replace the hand-written check for a VPReplicateRecipe load/store using
the value as its address with VPlan pattern matching via
m_Unary/m_Binary, which also handle masked recipes uniformly.
[VPlan] Add VPReplicateRecipe::getNumOperandsWithoutMask (NFC) (#205004)
Add a getNumOperandsWithoutMask helper to VPReplicateRecipe, mirroring
the existing VPInstruction::getNumOperandsWithoutMask, and use it to
replace some hand-rolled code.
[libc][math] Extend iscanonical macro to _Float16 and float128
iscanonical is a C23 type-generic macro, so the f16/f128 variants are
surfaced through it rather than as functions in the generated math.h.
float128 is only listed when distinct from long double (LDBL_MANT_DIG !=
113) to avoid two _Generic associations with compatible types.
[flang][OpenMP] Move unique clauses to allowedOnceClauses in OMP.td
Many unique clauses were listed in "allowedClauses", which turned off
the single-occurrence check in flang. Move these clauses to the right
category to enable this check.
One exception to this is the IF clause: the IF clause is unique for
all non-compound directives, but is repeatable on compound ones with
the restriction that at most one IF clause can apply to any of the
constituents. This restriction is currently not enforced correctly
in flang, and so the IF clause was left unchanged.
Although this change is applied to a file shared between flang and
clang, clang does not use these categories for its checks, and hence
is not affected by this patch.
Revert "[Legalizer] Add support for promoting integers for s/ucmp (#198554) (#204978)
This reverts commit 91edd87a801fc5c9d12c7f5c6863edd50327cef8.
It was causing CI failures for Linux.
[ARM] Use lo tCMPr opcode when expanding CMP_SWAP (#204567)
We were always generating the tCMPhir even when the registers were both
low, which is an unpredictable instruction. Generating tCMPr instead
when both the registers are low.
Fixes #204519.
Use BRIGHT_BLACK instead of SAVEDCOLOR for input lines and ellipses
`BRIGHT_BLACK` is a grayish color that is (1) clearly visible on the
light and dark terminal themes I have tried and (2) typically distinct
from the default color (`SAVED_COLOR`) used for input text.
[VPlan] Allow plain active lane mask in LastActiveLane verifier. (#204982)
Active lane masks are prefix masks. After simplifying the backedge, we
may end up with an active-lane-mask operand of LastActiveLane that does
not match the header mask predicate.
This fixes a verifier failure for the new test.
[Xtensa] Call isUInt<8> in range-check asserts (#204731)
`printOffset8m8_AsmOperand` and `getSelect_256OpValue` assert on
`isUInt<8>` without calling it, so the expression takes the function's
address and the range check never runs. This also trips
`-Werror,-Wpointer-bool-conversion` in builds with assertions enabled.
Pass the operand value so the bound is actually checked.
[RFC][CodeGen] Add generic target feature checks for intrinsics
This PR adds target-independent infrastructure for annotating LLVM intrinsics
with required subtarget feature expressions.
It introduces a TargetFeatures string field to intrinsic TableGen records.
TableGen emits an intrinsic-to-feature mapping table.
Both SelectionDAG and GlobalISel now perform this check before lowering target
intrinsics. This allows targets to opt in by annotating intrinsic definitions
directly, rather than adding custom checks during lowering, legalization, or
instruction selection.
This PR uses one AMDGPU intrinsic as an example.
[RFC][IR] Extract AMDGPU-specific verification logic into `VerifierAMDGPU.cpp`
`Verifier.cpp` is large and already mixes generic IR verification with
target-specific checks. We also have a growing amount of AMDGPU verifier logic
downstream, which would all end up in the same file if we don't address this,
and that is not ideal.
This patch extracts AMDGPU-specific verification logic into a separate
`VerifierAMDGPU.cpp` file, with shared infrastructure (`VerifierSupport`) moved
into `VerifierInternal.h`.
This is purely a code organization change, not a target-dependent IR verifier.
All checks remain compiled and linked into `LLVMCore` regardless of the target
triple. The extracted functions are called unconditionally at well-defined
extension points in `Verifier.cpp`, and each function internally gates on
target-specific conditions (for example, triple checks or intrinsic IDs) as
needed. The file is strictly limited to AMDGPU-specific IR constructs (amdgcn
intrinsics, AMDGPU module flags, etc.), and does not contain generic IR rules
that vary by target.
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[clang][x86] Add constexpr support for VNNI intrinsics (#190549)
Fixes #161340.
It adds constexpr support for VNNI
intrinsics by modifying their header files, their TableGen definitions,
how they're interpreted in InterpBuiltin.cpp and ExprConstant.cpp, and
adds unit tests in the headers' corresponding unit test files.
[orc-rt] Replace TaskDispatcher with Session-supplied wrapper-runner. (#204965)
TaskDispatcher was only used to run wrapper-function calls that
originated from the controller. Replace it with a callable type:
Session::RunWrapperCall = move_only_function<void(
orc_rt_SessionRef, uint64_t, orc_rt_WrapperFunctionReturn,
orc_rt_WrapperFunction, WrapperFunctionBuffer)>
Each call carries an outstanding ManagedCodeTaskGroup token; the runner
must eventually invoke Fn (which calls Return) or call Return directly
to bail out, otherwise Session shutdown blocks indefinitely.
Clients can supply any callable that satisfies the contract above. The
new QueueingRunner and ThreadPoolRunner classes (replacing
QueueingTaskDispatcher and ThreadPoolTaskDispatcher, respectively) are
provided as off-the-shelf options.
