1,049,299 commits found in 6 milliseconds
[flang] Added minutes from the 2-25-2026 Flang Community Call (#183389)
LLVM /project dff87d3 — lldb/test/API/lang/objc/failing-description TestObjCFailingDescription.py, lldb/test/API/lang/objc/struct-description TestObjCStructDescription.py Revert "[lldb/test] Fix tests reading log from remote platform instead of hos…"
This reverts commit b3ec476c702a1cd8ada8686a2be4fed7cccf81ef .
[lld][WebAssembly] Remove comment about wasm-ld being WIP. NFC (#183410)
wasm-ld has been feature complete for a while now. LLVM /project b3ec476 — lldb/test/API/lang/objc/failing-description TestObjCFailingDescription.py, lldb/test/API/lang/objc/struct-description TestObjCStructDescription.py [lldb/test] Fix tests reading log from remote platform instead of host (#183413)
Some tests are using logs to validate that a test behaves correctly
however they used `platform shell cat {log}` to read the logfile.
This doesn't work when running the testsuite against a remote platform
since the logs are saved on the host's filesystem.
This patch addresses those failures by making sure we read the log file
from the host platform.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma> [libc++] Try using job.check_run_id instead of github.job
According to https://github.com/orgs/community/discussions/8945,
it seems I'm not the only one who is confused by the documentation.
LLVM /project 2370063 — mlir/include/mlir/Dialect/OpenACC OpenACCUtilsLoop.h, mlir/lib/Dialect/OpenACC/Utils OpenACCUtilsLoop.cpp [openacc] Change function wrapMultiBlockRegionWithSCFExecuteRegion to non-static (#183409)
This change updates function `wrapMultiBlockRegionWithSCFExecuteRegion`
to be non-static. LLVM /project 2acb24e — llvm/lib/Target/ARM ARMISelLowering.cpp, llvm/test/CodeGen/ARM shift-combine.ll [ARM] optimize to `vsri`/`vsli` (#182051)
fixes https://github.com/llvm/llvm-project/issues/181495 LLVM /project 122e79c — llvm/lib/CodeGen MachineScheduler.cpp, llvm/test/CodeGen/AMDGPU a-v-flat-atomicrmw.ll freeze.ll [MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)
There are three calls to bumpCycle in bumpNode. Prior to the first call,
we calculate NextCycle as the next cycle in which all of a given
instruction's required hardware resources (as defined by the SchedModel)
are available. Any gap between this calculated NextCycle and CurrCycle
measures stalls that must occur before we can schedule the given
instruction.
The second and third call handle adjustments that occur during or after
issuing of the instruction (e.g. if the number of microops exceeds the
issue width).
According to the documentation of HazardRec->EmitInstruction, we should
call this method when an instruction is emitted: "This callback is
invoked when an instruction is emitted, to advance the hazard state."
In the context of bumpNode, this implies that it should be called after
we bumpCycle for stalls that must occur before issue of the
[18 lines not shown ] LLVM /project 6079e39 — libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp Rebase
Created using spr 1.3.6-beta.1
LLVM /project f454b5e — libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
LLVM /project 2037a50 — libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp Rebase
Created using spr 1.3.6-beta.1
LLVM /project 6e4ddb5 — libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
LLVM /project 6d32c36 — libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp Rebase
Created using spr 1.3.6-beta.1
LLVM /project b732d7f — libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
LLVM /project 576932b — libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp Whitespace change
Created using spr 1.3.6-beta.1
[libc++] Use the Github context instead of env to access the run ID & friends
[RISCV] Add missing immediates to check lines in rv32p-valid.s and rv64p-valid.s. NFC (#183238)
[MC] Consistent use of inline field initializers in MCAsmInfo (#183343)
LLVM /project a5f52b0 — llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll Rebase
Created using spr 1.3.6-beta.1
Delta File +25,051 -14,920 llvm/test/CodeGen/RISCV/clmul.ll +16,004 -0 llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s +13,198 -0 llvm/test/CodeGen/RISCV/clmulr.ll +12,863 -0 llvm/test/CodeGen/RISCV/clmulh.ll +8,874 -0 llvm/test/CodeGen/PowerPC/clmul-vector.ll +3,298 -3,437 llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll +79,288 -18,357 5,976 files not shown +394,965 -143,055 5,982 files
LLVM /project b2430bb — llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +25,051 -14,920 llvm/test/CodeGen/RISCV/clmul.ll +16,004 -0 llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s +13,198 -0 llvm/test/CodeGen/RISCV/clmulr.ll +12,863 -0 llvm/test/CodeGen/RISCV/clmulh.ll +8,874 -0 llvm/test/CodeGen/PowerPC/clmul-vector.ll +3,298 -3,437 llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll +79,288 -18,357 5,976 files not shown +394,965 -143,055 5,982 files
LLVM /project c7103a4 — llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll Rebase
Created using spr 1.3.6-beta.1
Delta File +25,051 -14,920 llvm/test/CodeGen/RISCV/clmul.ll +16,004 -0 llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s +13,198 -0 llvm/test/CodeGen/RISCV/clmulr.ll +12,863 -0 llvm/test/CodeGen/RISCV/clmulh.ll +8,874 -0 llvm/test/CodeGen/PowerPC/clmul-vector.ll +3,298 -3,437 llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll +79,288 -18,357 5,976 files not shown +394,965 -143,055 5,982 files
LLVM /project 85a73a6 — llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +25,051 -14,920 llvm/test/CodeGen/RISCV/clmul.ll +16,004 -0 llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s +13,198 -0 llvm/test/CodeGen/RISCV/clmulr.ll +12,863 -0 llvm/test/CodeGen/RISCV/clmulh.ll +8,874 -0 llvm/test/CodeGen/PowerPC/clmul-vector.ll +3,298 -3,437 llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll +79,288 -18,357 5,976 files not shown +394,965 -143,055 5,982 files
LLVM /project 812a378 — llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll Rebase
Created using spr 1.3.6-beta.1
Delta File +25,051 -14,920 llvm/test/CodeGen/RISCV/clmul.ll +16,004 -0 llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s +13,198 -0 llvm/test/CodeGen/RISCV/clmulr.ll +12,863 -0 llvm/test/CodeGen/RISCV/clmulh.ll +8,874 -0 llvm/test/CodeGen/PowerPC/clmul-vector.ll +3,298 -3,437 llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll +79,288 -18,357 5,995 files not shown +395,998 -143,089 6,001 files
LLVM /project ac0d3e6 — llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +25,051 -14,920 llvm/test/CodeGen/RISCV/clmul.ll +16,004 -0 llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s +13,198 -0 llvm/test/CodeGen/RISCV/clmulr.ll +12,863 -0 llvm/test/CodeGen/RISCV/clmulh.ll +8,874 -0 llvm/test/CodeGen/PowerPC/clmul-vector.ll +3,298 -3,437 llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll +79,288 -18,357 5,995 files not shown +395,998 -143,089 6,001 files
LLVM /project 90bbc06 — clang/docs ClangIRCleanupAndEHDesign.md, clang/lib/CIR/Dialect/Transforms IdiomRecognizer.cpp Rebase
Created using spr 1.3.6-beta.1
LLVM /project 33ae573 — clang/docs ClangIRCleanupAndEHDesign.md, clang/lib/CIR/Dialect/Transforms IdiomRecognizer.cpp [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
LLVM /project ee3bb59 — llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll Rebase, use correct macro name
Created using spr 1.3.6-beta.1
Delta File +25,051 -14,920 llvm/test/CodeGen/RISCV/clmul.ll +16,004 -0 llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s +13,198 -0 llvm/test/CodeGen/RISCV/clmulr.ll +12,863 -0 llvm/test/CodeGen/RISCV/clmulh.ll +8,874 -0 llvm/test/CodeGen/PowerPC/clmul-vector.ll +3,298 -3,437 llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll +79,288 -18,357 5,992 files not shown +395,957 -143,078 5,998 files
LLVM /project 0de8ae1 — llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Delta File +25,051 -14,920 llvm/test/CodeGen/RISCV/clmul.ll +16,004 -0 llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s +13,198 -0 llvm/test/CodeGen/RISCV/clmulr.ll +12,863 -0 llvm/test/CodeGen/RISCV/clmulh.ll +8,874 -0 llvm/test/CodeGen/PowerPC/clmul-vector.ll +3,298 -3,437 llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll +79,288 -18,357 5,991 files not shown +395,954 -143,076 5,997 files
LLVM /project fa3b86b — llvm/lib/Target/RISCV RISCVMoveMerger.cpp, llvm/test/CodeGen/RISCV rv32-move-merge.ll double-round-conv-sat.ll [RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)
Extends RISCVMoveMerger to identify adjacent 32-bit moves that can be
combined into a single 64-bit move instruction. In particular, this
patch adds support for extension zdinx (`fmv.d`) and p(`padd.dw`).
Fixes #180831 LLVM /project 5a629e6 — llvm/lib/Target/ARM/MCTargetDesc ARMMCAsmInfo.cpp, llvm/lib/Target/LoongArch/MCTargetDesc LoongArchMCAsmInfo.cpp [MC] Remove redundant setting of AllowDollarAtStartOfIdentifier. NFC (#183339)
This setting defaults to false so there is no need to set it unless we
want it to be true.
This makes it easy to see at a glace which backends support this, and
matches the existing behaviour of other fields such as
`AllowAtAtStartOfIdentifier`, `AllowQuestionAtStartOfIdentifier`,
`UseAssignmentForEHBegin` and `AllowAtInName`. These are all only ever
set to true in subclasses, never false. 