[LoopVectorize] Clear stale CycleAnalysis after vectorizing a loop (#215237)
After a6af12620778, LoopVectorizePass crashes when processing functions
with multiple loops. After vectorizing a loop, locks may be deleted, but
the cached CycleAnalysis still holds pointers to those blocks. If BFI is
later requested for a subsequent loop, it uses the stale CycleInfo and
crashes. Clear the cached CycleAnalysis after each loop vectorization so
that BlockFrequencyAnalysis recomputes it fresh if needed.
Fixes #215236
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Co-authored-by: Florian Hahn <flo at fhahn.com>
CodeGen: Add getDefBlock helper (#216182)
A reasonable number of places check getVRegDef just to
return the parent block, so introduce a helper for it.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DAG: Gracefully diagnose missing FP conversion libcalls when softening (#215765)
Diagnose the missing libcall and return poison instead.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[mlir][ArmSME] Enable native ArmSME integration testing on Darwin (#215296)
`MLIR_RUN_ARM_SME_TESTS=ON` could not exercise ArmSME integration tests
on real Apple Silicon SME hardware:
1. `check_hwcap` only detects CPU features via Linux's
`getauxval()`/`hwcap.h`, so it always required an emulator on Darwin,
even with real SME hardware present.
2. With `+sve` enabled, LLVM lowers `vector.vscale` to a bare
`cntd`/`cntb`, illegal outside streaming mode. Apple Silicon doesn't
expose base (non-streaming) SVE at EL0, so this traps (see #204853).
3. Some functions computing `vector.vscale` directly had no (or an
incorrectly unprefixed) streaming attribute, which is required for legal
`vscale` codegen and is silently dropped during `func.func` to
`llvm.func` conversion unless `llvm.`-prefixed (see #190864).
4. 6 tests force a specific streaming vector length via
`setArmSVLBits`/`setArmVLBits`, which isn't possible on real hardware
(SVL is fixed per core).
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[LoongArch] Add late branch optimization pass
The patch adds a late optimization pass that replaces conditional
branches that can be statically evaluated with an unconditinal branch.
This pass is inspired by RISC-V's RISCVLateBranchOpt pass.
[LoongArch] Fix selection of BRCOND with constant conditions (#216027)
LoongArch DAG instruction selection could fail to select
`LoongArchISD::BRCOND` when its condition was a constant integer. Add
patterns to lower constant zero and one conditions to `BEQZ` and `BNEZ`.
Co-authored-by: wanglei <wanglei at loongson.cn>
Fixes: https://github.com/llvm/llvm-project/issues/215935
[PassInstrumentation] Replace llvm::Any with a tagged IRUnitRef. (NFC) (#215341)
llvm::Any currently requires heap allocations on every construction,
which is quite expensive for the use in PassInstrumentation.
Replace llvm::Any with a hand-rolled IRUnitRef wrapper that uses
PointerIntPair on platforms with 64 bit (or larger) pointers or a pair
of Kind/pointer on other platforms.
Unfortunately I don't think alignas(8) would work for Function (or any
Value*), as it uses `HungOffOperandsAllocMarker`.
Follow-up to https://github.com/llvm/llvm-project/pull/215120.
It further improves compile-time:
* stage1-O3: -0.09%
* stage1-ReleaseThinLTO: -0.09%
* stage1-ReleaseLTO-g: -0.08%
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[RISCV] Don't fold vector (fp_to_sint (ceil/floor/round/etc X)) if the inner op has multiple uses. (#216137)
If the inner operation needs to write FRM and the folded operation
does too, combining them may require another pair of FRM writes
unless we can get rid of the inner operation.
This may be expensive on CPUs without FRM renaming support.
Assisted-by: Claude
[DWARFLinker] Constrain a function's high_pc to its own symbol
Mach-O objects built with .subsections_via_symbols make every symbol an
independently placeable atom, and the linker packs atoms without
preserving the spacing they had in the object file.
I have an example where the compiler describes such a subprogram as
extending past its own atom. While it's debatable whether that's a good
idea, it's not invalid in the object file. However, once linked, it is
invalid.
We can make dsymutil resilient against this by looking at the size of
the symbol in the debug map and adjusting the end_pc. I'm doing so
conservatively so that only a collision is repaired. Already
overlapping/invalid ranges remain untouched.
rdar://184768778
[lldb] Search for a corefile's images before loading any of them
A userland or kernel corefile can list hundreds of images, and searching for
one can shell out to a symbol server or fetch over the network. Searching for
them one at a time is where loading such a corefile spends its time.
Add a batch form of SymbolLocator::Locate that runs the searches on the
debugger's thread pool, gated on target.parallel-module-load. Results come
back in the order the requests were given, since that order decides the
Target's module order. Only the results are ordered, and anything a search
reports to the user arrives in whatever order the searches finish in.
Only the plugin searches run concurrently, so a platform hook does not have to
be thread safe to take part, and reading a binary's UUID out of memory stays
on the calling thread.
Setting up a platform binary can replace the Target's platform and dynamic
loader, and now happens for every image before any of them is searched for, so
the platform a corefile asks for is the one all of its images are searched
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[ORC] Drop SimpleExecutorMemoryManagerSymbolNames struct (#216231)
Remove the SimpleExecutorMemoryManagerSymbolNames struct and the
orc_rt_SimpleNativeMemoryMapSPSSymbols global. The sps::MemMgr*CIName
constants in GenericMemoryManagerProxySpecs.h are now the single source
of truth for the SimpleNativeMemoryMap controller-interface names, used
by both the controller-side proxies and the executor-side
SimpleExecutorMemoryManager bootstrap registration (as
OrcRTBootstrap.cpp already does for the memory-access wrappers).
No functional change: the name strings are identical to those previously
held in orc_rt_SimpleNativeMemoryMapSPSSymbols.
[ProfileData] Avoid magic layout indices in SampleProfileWriter (NFC) (#215981)
This patch removes hardcoded section layout indices in
SampleProfileWriterExtBinary in favor of finding the first unwritten
matching entry in SectionHdrLayout.
Previously, writeDefaultLayout and writeCtxSplitLayout passed magic
integer indices to writeOneSection to specify the position of each
section in SectionHdrLayout.
This patch introduces findUnwrittenEntry to dynamically look up the
matching unwritten section entry in SectionHdrLayout and determine its
ordinal among sections of the same type. This allows
writeDefaultLayout and writeCtxSplitLayout to iterate over declarative
arrays of sections without magic indices, and allows removing the
index-based addSectionFlag overload.
Assisted-by: Antigravity
[ProfileData] Remove SampleSorter (NFC) (#215941)
This patch removes SampleSorter in favor of direct iteration over
BodySamples and CallsiteSamples.
Originally, BodySamples and CallsiteSamples used DenseMap. Because
DenseMap does not guarantee iteration order, SampleSorter was
introduced to sort samples by LineLocation on demand when printing or
writing text profiles.
In December 2015, commit 10cf124bb920 switched BodySamples and
CallsiteSamples from DenseMap to std::map to reduce memory usage, but
SampleSorter was retained. Since std::map is already ordered by
LineLocation, SampleSorter is redundant.
Assisted-by: Antigravity
Reland "[Profile] Add a more descriptive message to the bad_header error" (#216230)
At the moment, the raw profile reader diagnoses different problem with
the same error message "invalid instrumentation profile data (file
header is corrupt)". On AIX, we had users report such problems thinking
it's a compiler bug, while the real problem was truncated profiles. The
particular case they hit was the condition
[here](https://github.com/llvm/llvm-project/blob/668803fa73bdf2f8d095162a1f81c000d18458c9/llvm/lib/ProfileData/InstrProfReader.cpp#L652):
```
Error RawInstrProfReader<IntPtrT>::readHeader(...) {
...
if (Start + ValueDataOffset > DataBuffer->getBufferEnd())
return error(instrprof_error::bad_header);
```
This could indicate a corrupted header (large garbage values for some
sections) or a truncated file.
I figured if we print the values and sizes we read in the header, it
will give the user more info.
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[BOLT][RISCV][NFC] Add a test for GOT references with a non-adjacent load (#215991)
The RISC-V psABI pairs the two halves of a PC-relative address through
the label that the %pcrel_lo relocation refers to, so the load holding
the low part does not have to follow the AUIPC directly.
Pin down the current behavior in that case. All three references name
the same symbol and should therefore resolve to the same GOT entry, but
only the first one does, because BOLT takes the low part from whatever
instruction follows the AUIPC: an unrelated ADDI in the second case, and
the terminator of the basic block in the third. The next commit fixes
this and updates the checks.
[DebugInfo][NFC] Document debug record salvage (#215907)
Document the order salvageDebugInfoForDbgValues works in: a dbg.assign
address before its variable location, stop once a variable location
can't be salvaged, and kill every supplied record when none of them were
processed.
salvageDebugInfo is documented on both its declaration and its
definition, keep the header copy and update it.
No regressions on check-llvm.
[ORC] Realign EPCGenericJITLinkMemoryManager Create API (#216216)
Bring EPCGenericJITLinkMemoryManager into alignment with
EPCGenericMemoryAccess and EPCGenericDylibManager: a Bindings
constructor plus static Create methods that build the bindings from the
ProxySpecs using the default controller-interface names.
Create(JITDylib&) resolves the SimpleNativeMemoryMap symbols in the
given JITDylib; Create(ExecutionSession&) uses the bootstrap JITDylib.
Clients targeting a different protocol can construct their own Bindings
directly.
This replaces the previous scheme where Create took a
SimpleExecutorMemoryManagerSymbolNames override.
[libc][Semaphore] Fix tests - remove APPEND_LIBC_TEST macro uses. (#216219)
APPEND_LIBC_TEST was removed in abeb492322c12860a4533426208d6d26155cd0bc
, remove it from the newly added semaphore tests as well.
[CIR][CodeGen] Emit cir.fmuladd for FP-contracted mul+add/sub (#215382)
Ports the FP-contraction fusion from classic CodeGen (`tryEmitFMulAdd` /
`buildFMulAdd`) to CIRGen. Under `-ffp-contract=on / fast`, `a * b + c`
and `a * b - c` fuse into `cir.fmuladd` (with the addend negated for the sub
form) instead of separate `cir.fmul` + `cir.fadd/fsub`.
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Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
[mlir][xegpu] Lower lane_data repack convert_layout to lane_shuffle (#210837)
Extend the SgToLaneConvertLayout pattern to lower a convert_layout that
only repacks lane_data between round-robin and contiguous form (keeping
lane_layout and order unchanged) into xegpu.lane_shuffle. Each lane
keeps the same elements and total bits along the repacked dimension, but
their assignment to lanes changes, so the data is moved across lanes
with a bit-preserving bitcast_shuffle.
assisted-by-claude
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
