LLVM/project 0e4d82c — lld/MachO Writer.cpp SyntheticSections.cpp, lld/test/MachO chained-fixups-alignment.s

[lld-macho] Don't write chained fixups through misaligned pointers (#238485)

`DYLD_CHAINED_PTR_64` fixups only need to be 4-byte aligned, but later
patched their `next` fields, through pointers to
`dyld_chained_ptr_64_rebase` and `dyld_chained_ptr_64_bind`, which need
8-byte alignment. UBSan has flagged this since #234006 added a
4-byte-aligned fixup to chained-fixups-alignment.s.

Now we build them in locals and memcpy them in and out. arm64e fixups
have to be 8-byte aligned, so those writes are fine as they are. The
test now also has a bind and a `next` field at 4 mod 8, and checks that
the chain still decodes.

Fixes the sanitizer-x86_64-linux-fast failure after #234006:
https://lab.llvm.org/buildbot/#/builders/169/builds/28168

Assisted-by: Claude
DeltaFile
+18-13lld/MachO/SyntheticSections.cpp
+13-2lld/test/MachO/chained-fixups-alignment.s
+5-2lld/MachO/Writer.cpp
+36-173 files

LLVM/project 4e68ddd — llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/lib/Target/RISCV RISCVISelLowering.cpp

Reapply "[SelectionDAG] Narrow (shr (sub A, B), 1) to AVGSUBFLOOR" (#238249) (#238408)

Needed to regenerate 2 tests to remove pzext.h.b.

Original message:

Add combineShiftToAVGSUB, which forms AVGSUBFLOORS/AVGSUBFLOORU on a
narrower type when both operands are known to be extended from it, so
the subtract can't overflow. This is similar to combineShiftToAVG.

The node is only formed if it is legal or custom on the narrow type or
the original type after type legalization. As long as type legalization
won't change the element type. This covers WidenVector, SplitVector and
ScalarizeVector. This can be relaxed in the future.

Remove the RISC-V P extension truncate combine for (P)ASUB(U) since this
is now handled by the generic combine.
DeltaFile
+196-0llvm/test/CodeGen/RISCV/rvp-avgsub.ll
+113-6llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+0-11llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+309-173 files

LLVM/project 4b3c37b — llvm/lib/Target/AMDGPU AMDGPULowerIntrinsics.cpp, llvm/test/CodeGen/AMDGPU lds-dma-war-async.ll llvm.amdgcn.tensor.load.store.ll

[AMDGPU] Clamp full multicast masks to 0x7fff, skip small clusters
DeltaFile
+177-117llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
+150-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
+37-56llvm/test/CodeGen/AMDGPU/lower-intrinsics-mcast-full-mask.ll
+49-34llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
+34-26llvm/test/CodeGen/AMDGPU/lds-dma-war-async.ll
+20-8llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+467-3492 files not shown
+481-3608 files

LLVM/project d70935d — libc/src/__support/math scalbnf128.h scalblnf128.h, libc/test/src/math ldexpf128_test.cpp scalblnf128_test.cpp

[libc] Make ldexpf128/scalbnf128/scalblnf128 use emulated Float128 (#220295)

This makes the three exponent scaling functions ldexpf128, scalbnf128
and scalblnf128 work with the emulated Float128 type, so they can be
used on platforms without native __float128.

Fixes #219759 (part of #216576).
DeltaFile
+33-0libc/test/src/math/CMakeLists.txt
+29-0libc/test/src/math/scalblnf128_test.cpp
+23-0libc/test/src/math/ldexpf128_test.cpp
+10-11libc/src/__support/math/ldexpf128.h
+10-8libc/src/__support/math/scalbnf128.h
+10-8libc/src/__support/math/scalblnf128.h
+115-2735 files not shown
+331-11741 files

LLVM/project 0cbf3ec — llvm/test/CodeGen/AMDGPU/GlobalISel postlegalizer-combiner-carry-zero.mir combine-fmul-select-copy.mir, llvm/test/CodeGen/RISCV/GlobalISel double-intrinsics.ll

[GlobalISel] Auto-commute combine patterns

Emit both operand orders for constrained commutative generic match
patterns, including each use of a PatFrag. Skip redundant permutations
and enforce MaxPermutations before allocating expanded alternatives.

Give each permutation its own operand expansions so operand indices
cannot leak between alternatives.

Keep commuted immediate patterns available with constant-to-RHS
canonicalization, and consolidate AMDGPU carry rules while preserving
zero-addend and RHS-first matching.

Make the integer and AMDGPU multiply/select helpers accept either operand
order.

Add emitter documentation and TableGen, MIR, and codegen regressions.
DeltaFile
+114-122llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
+203-18llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+205-0llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-commute.td
+119-15llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td
+132-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fmul-select-copy.mir
+118-0llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-carry-zero.mir
+891-15523 files not shown
+1,630-40129 files

LLVM/project 1e10bee — llvm/test/CodeGen/AMDGPU rem_i128.ll

Apply suggestion from @chinmaydd
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/rem_i128.ll
+2-21 files

LLVM/project c85eea0 — mlir/include/mlir/Dialect/LLVMIR ROCDLOps.td

[MLIR][ROCDL] Note the deprecation of the <4 x i32> buffer ops

While we don't have a way to flag a MLIR op as deprecated yet, go
ahead and add a note to the old `<4 x i32>` intriinsic ops that
they're actively deprecated.

AI disclosure: Claude made this edit, though I checked the wording and
wrote up this message.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+24-0mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+24-01 files

LLVM/project 096753f — llvm/docs AMDGPUUsage.md ReleaseNotes.md

[AMDGPU][docs] Document the <4 x i32> buffer intrinsic deprecation (#231302)

Flag the deprecation of <4 x i32> buffer intrinsics in the release
notes, flagging the migration path and the s.buffer.load subtleties.

AI disclosure: Claude did draft some of this, but I deleted basically
all of it and the words are mine.

---------

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+28-0llvm/docs/ReleaseNotes.md
+26-1llvm/docs/AMDGPUUsage.md
+54-12 files

LLVM/project fad7319 — llvm/test/CodeGen/AMDGPU vector-reduce-fmaximum.ll llvm.amdgcn.mfma.ll

[AMDGPU][NFC] Clean up pre-gfx125x test RUN lines

Drop flags that match defaults: -verify-machineinstrs in .ll tests,
-global-isel=0 in tests without a GlobalISel run, and redundant
-global-isel-abort. Use subarch triples instead of amdgcn plus -mcpu.
Error-only MC runs use -filetype=null.

Change-Id: Ic8e2469780e32dbe204a032fcf9d91a1e8b737d2
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+11-11llvm/test/CodeGen/AMDGPU/minimumnum.ll
+11-11llvm/test/CodeGen/AMDGPU/maximumnum.ll
+10-10llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+10-10llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
+10-10llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+10-10llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+62-6280 files not shown
+203-20386 files

LLVM/project 8e98546 — llvm/test/CodeGen/AMDGPU trans-bf16-omod.ll s-wakeup-barrier.ll, llvm/test/MC/AMDGPU gfx1251_asm_wmma_w32.s

[AMDGPU][NFC] Clean up gfx125x test RUN lines (#238105)

Drop flags that match defaults: `-verify-machineinstrs` in `.ll` tests,
`-global-isel=0` in tests without a GlobalISel run, and redundant
`-global-isel-abort`.

Use subarch triples instead of amdgcn plus `-mcpu`. 

Error-only MC runs use `-filetype=null`.
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
+3-3llvm/test/CodeGen/AMDGPU/coexec-sched-barrier-latency.mir
+2-2llvm/test/Verifier/AMDGPU/llvm.amdgcn.cooperative.atomic.ll
+2-2llvm/test/MC/AMDGPU/gfx1251_asm_wmma_w32.s
+2-2llvm/test/CodeGen/AMDGPU/trans-bf16-omod.ll
+2-2llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
+14-1422 files not shown
+46-4628 files

LLVM/project 921fdd3 — clang/lib/Driver Driver.cpp, clang/test/Driver sycl-offload-arch-igca.cpp sycl-offload-jit.cpp

[Clang][SYCL] Reject an NVIDIA offload target for SYCL (#229937)

Reject an NVIDIA offload target for SYCL.

Previously, `clang++ -fsycl --offload-arch=sm_80`, or
`--offload-targets=nvptx64-nvidia-cuda`, hit an assertion in the CUDA
toolchain, which supports only CUDA and OpenMP. Clang does not support
SYCL offloading to NVIDIA GPUs without `-foffload-via-llvm`, so the
driver now reports "invalid or unsupported offload target" instead. With
`-foffload-via-llvm`, SYCL offloading to an NVIDIA GPU is unchanged.
DeltaFile
+15-0clang/test/Driver/sycl-offload-jit.cpp
+10-0clang/lib/Driver/Driver.cpp
+4-3clang/test/Driver/sycl-offload-arch-igca.cpp
+29-33 files

LLVM/project 1f82333 — llvm/lib/Analysis InlineCost.cpp

Refine the comment a bit (NFC)

Co-authored-by: Florian Hahn <flo at fhahn.com>
DeltaFile
+1-1llvm/lib/Analysis/InlineCost.cpp
+1-11 files

LLVM/project 97b7b48 — llvm/test/CodeGen/AMDGPU lower-intrinsics-mcast-full-mask.ll

[AMDGPU] Add cluster size tests for full multicast load masks (NFC)

Add tests for a cluster load with a full workgroup mask in functions with
no cluster, a fixed cluster of 8 or 16 workgroups, and a cluster size only
known at run time. The checks show the current lowering, which clamps the
mask in all of them.
DeltaFile
+90-0llvm/test/CodeGen/AMDGPU/lower-intrinsics-mcast-full-mask.ll
+90-01 files

LLVM/project eaf6ec1 — llvm/lib/Target/X86 X86PassRegistry.def X86CodeGenPassBuilder.cpp, llvm/test/CodeGen/X86 llc-pipeline-npm.ll

finish

Created using spr 1.3.7
DeltaFile
+4-0llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1-2llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+1-0llvm/lib/Target/X86/X86PassRegistry.def
+6-23 files

LLVM/project cd7a203 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AMDGPU bitcast-int-fp.ll

[AMDGPU] Treat a bitcast between legal types as free

The generic cost model treats a bitcast as free only when both types
are integer types or both are not. AMDGPU keeps integer and
floating-point values in the same registers, so a bitcast between two
legal types is a no-op. A scalar bitcast from i32 to float cost 1, but
the vector bitcast from <2 x i32> to <2 x float> cost 0. The SLP
vectorizer counted this difference as a saving.

A bitcast that involves a type the target legalizes, such as a vector
of i8, keeps its cost, because the lanes may need repacking.

Assisted-by: Claude Opus
DeltaFile
+35-35llvm/test/Analysis/CostModel/AMDGPU/bitcast-int-fp.ll
+4-3llvm/test/Transforms/SLPVectorizer/AMDGPU/bitcast-int-fp.ll
+6-0llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+45-383 files

LLVM/project c71423e — llvm/lib/Target/SystemZ SystemZTargetMachine.cpp, llvm/test/CodeGen/SystemZ zos-section-readonlywithrel.ll

[SystemZ][z/OS] Unconditionally use DynamicNoPIC relocation model (#238087)

On z/OS, generated code is always position-independent, so -fpic and
-fno-pic have no effect. Previously, getEffectiveRelocModel() returned
the requested relocation model if one was provided. When -fpic was
passed, TargetMachine:: isPositionIndependent() returned true, enabling
optimizations such as relative lookup tables that generate 32-bit
relative offsets between globals. These are incompatible with the GOFF
binder's requirement for 8-byte relocations in C_WSA64.

This change forces getEffectiveRelocModel() to always return
Reloc::DynamicNoPIC on z/OS, regardless of what the frontend requests.

Assisted-by: IBM Bob
DeltaFile
+11-6llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+4-0llvm/test/CodeGen/SystemZ/zos-section-readonlywithrel.ll
+15-62 files

LLVM/project ac479cc — llvm/test/Analysis/CostModel/AMDGPU bitcast-int-fp.ll

[AMDGPU][NFC] Add bitcast cost tests for legalized types and pointers

Add bitcasts that involve types the target legalizes, such as vectors
of i8, i24 and <2 x i24>, and bitcasts of pointers. Add a gfx7 RUN
line, where i16 and <2 x i16> are not legal.

Assisted-by: Claude Opus
DeltaFile
+134-2llvm/test/Analysis/CostModel/AMDGPU/bitcast-int-fp.ll
+134-21 files

LLVM/project cdf67f8 — lldb/source/Plugins/Process/Windows/Common DebuggerThread.h DebuggerThread.cpp

[lldb][Windows] Lock DebuggerThread::m_process against the debug loop (#236560)

When the inferior exits before its initial stop, the debug loop resets
`DebuggerThread::m_process` but the launching thread copies it. Both
threads touch the same `shared_ptr`, which corrupts the heap, and
lldb-server dies with `0xC0000374`.

This causes `TestMissingDll.py` to fail with `"Sending vRun packet
failed"`.

This patch guards `m_process` with a mutex.

Tested on Windows with the race window widened: 21 of 800 launches
crashed before, 0 of 4800 after. `TestMissingDll.py` passed 1600 of 1600
runs.

rdar://191149207
DeltaFile
+28-26lldb/source/Plugins/Process/Windows/Common/DebuggerThread.cpp
+3-2lldb/source/Plugins/Process/Windows/Common/DebuggerThread.h
+31-282 files

LLVM/project a23f991 — clang/include/clang/Parse Parser.h, clang/include/clang/Sema DeclSpec.h

[BoundsSafety][NFC] Add late-parsed type attribute lists to declarators (#224559)

This is groundwork for late-parsing type attributes in every type
position where an ordinary type attribute can appear, following the
direction set in https://github.com/llvm/llvm-project/pull/223267, which
allows a CountAttributedType's count to be filled in later.

Ordinary type attributes are kept on the DeclSpec, on each
DeclaratorChunk and on the
Declarator. Give late-parsed type attributes the same three homes, with
nothing producing or consuming them yet.

No functional change: no caller passes a list yet, so the lists stay
empty. The next commit populates them.

Assisted-by: Opus 5.5

<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
DeltaFile
+84-53clang/include/clang/Sema/DeclSpec.h
+14-9clang/include/clang/Parse/Parser.h
+10-4clang/lib/Parse/ParseDecl.cpp
+108-663 files

LLVM/project 9f251f9 — lldb/source/Plugins/SymbolFile/DWARF DWARFASTParserFortran.cpp

Clarified Mangled comment, got rid of unnecessary switch, removed redundant comment and shortened variable names for parameter name and type vector
DeltaFile
+21-29lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserFortran.cpp
+21-291 files

LLVM/project c99848c — llvm/lib/Target/AArch64 AArch64.h AArch64SLSHardening.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+14-5llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+7-0llvm/lib/Target/AArch64/AArch64.h
+21-52 files

LLVM/project aea7325 — llvm/lib/Target/AArch64 AArch64.h AArch64SLSHardening.cpp, llvm/lib/Target/X86 X86TargetMachine.cpp X86.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+39-6llvm/lib/Target/X86/X86IndirectThunks.cpp
+14-5llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+18-1llvm/lib/Target/X86/X86.h
+7-0llvm/lib/Target/AArch64/AArch64.h
+1-1llvm/lib/Target/X86/X86TargetMachine.cpp
+79-135 files

LLVM/project e1c2111 — lldb/include/lldb/API SBCommandInterpreter.h, lldb/include/lldb/Interpreter CommandInterpreter.h

[lldb] Add eBroadcastBitReadyForInput to SBCommandInterpreter

Add eBroadcastBitReadyForInput to CommandInterpreter and
SBCommandInterpreter, and emit it from IOHandlerEditline::GetLine and
embedded_interpreter.py when waiting for input on the debugger input
stream. Also flush stderr before prompting in embedded_interpreter.py's
readfunc_stdio.

Add SBCommandInterpreterTest unit tests covering pipe input, sourced
files, multiline sub-IOHandlers, PTY editline input, and the interactive
embedded Python interpreter.
DeltaFile
+432-0lldb/unittests/API/SBCommandInterpreterTest.cpp
+10-0lldb/source/Interpreter/embedded_interpreter.py
+7-0lldb/source/Core/IOHandler.cpp
+4-0lldb/unittests/API/CMakeLists.txt
+2-1lldb/include/lldb/Interpreter/CommandInterpreter.h
+2-1lldb/include/lldb/API/SBCommandInterpreter.h
+457-21 files not shown
+458-27 files

LLVM/project e5a911f — llvm/lib/Target/SPIRV SPIRVAPI.cpp, llvm/unittests/Target/SPIRV SPIRVAPITest.cpp

[SPIR-V][NewPM] Use runCodeGenPipeline in SPIRVTranslate (#238451)

SPIRVTranslate will be able to pick NewPM once SPIR-V defaults to it
DeltaFile
+18-0llvm/unittests/Target/SPIRV/SPIRVAPITest.cpp
+4-12llvm/lib/Target/SPIRV/SPIRVAPI.cpp
+22-122 files

LLVM/project 8469104 — llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.896bit.ll amdgcn.bitcast.960bit.ll

Merge branch 'main' into users/DavidTruby/lld-coff-per-target
DeltaFile
+108,333-130,089llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+35,435-42,258llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+32,719-17,350llvm/test/CodeGen/AMDGPU/frem.ll
+23,347-23,371llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+19,306-23,044llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+18,036-21,726llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+237,176-257,83826,085 files not shown
+2,111,953-1,155,41026,091 files

LLVM/project 5db9b2b — libc/src/__support str_to_float.h, libc/test/src/__support str_to_float_test.cpp str_to_double_test.cpp

[libc] Bound the decimal point check in simple_decimal_conversion (#238179)

HighPrecisionDecimal clamps the decimal point to 1 << 30, but
exp10_to_exp2
is only valid for inputs below 646456636. For larger decimal points the
result wrapped to a negative value, so the "too large" and "too small"
checks did not trigger and the shift loops ran tens of millions of
iterations until exp_2 overflowed (signed integer overflow).

Treat decimal points at or beyond the valid range of exp10_to_exp2 as
out of
range, and use add_overflow/sub_overflow for exp_2 in the shift loops so
that they stay well defined.

Assisted-by: Claude (Anthropic)
DeltaFile
+24-5libc/src/__support/str_to_float.h
+15-0libc/test/src/__support/str_to_double_test.cpp
+10-0libc/test/src/__support/str_to_float_test.cpp
+49-53 files

LLVM/project bfaf4cb — llvm/lib/IR RuntimeLibcalls.cpp

RuntimeLibcalls: Only apply vector math attributes to floating point vectors

i128 is now <2 x i64> on Win64, which made the vector type checks treat
integer helpers like __atomic_load_16 as vector math functions and mark
them nosync and nofree. Check for a floating point vector argument.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
DeltaFile
+6-2llvm/lib/IR/RuntimeLibcalls.cpp
+6-21 files

LLVM/project e71256a — utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[Bazel] Fixes d1acd0e (#238460)

This fixes d1acd0ef6ff890d73593dbbd8caf2e2dc7f64169 (#237605).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=d1acd0ef6ff890d73593dbbd8caf2e2dc7f64169

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+2-1utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+2-11 files

LLVM/project 4025c5a — llvm/lib/Target/AArch64 AArch64.h AArch64SLSHardening.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+14-5llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+7-0llvm/lib/Target/AArch64/AArch64.h
+21-52 files

LLVM/project ba12fde — llvm/lib/CodeGen/SelectionDAG LegalizeDAG.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

SelectionDAG: Use the memory type for atomic libcall actions

The atomic libcall selection is driven by the memory type, not the
legalized value type. Convert targets to use the LibCall action
instead of Expand.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+18-11llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+6-12llvm/lib/Target/Mips/Mips16ISelLowering.cpp
+6-12llvm/lib/Target/ARM/ARMISelLowering.cpp
+16-0llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+9-6llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+7-7llvm/lib/Target/AVR/AVRISelLowering.cpp
+62-484 files not shown
+76-5110 files