LLVM/project 06ef301flang/lib/Semantics check-omp-loop.cpp check-omp-structure.h, flang/test/Semantics/OpenMP do10.f90

[flang][OpenMP] Use LoopRange to implement loop var type checking, NFC (#181797)

DeltaFile
+12-18flang/lib/Semantics/check-omp-loop.cpp
+7-7flang/test/Semantics/OpenMP/do10.f90
+1-1flang/lib/Semantics/check-omp-structure.h
+20-263 files

LLVM/project e07b9d1clang/cmake/caches VectorEngine.cmake, openmp CMakeLists.txt

Revert "[OpenMP] Remove standalone build mode (#149878)"

Downstream builds are note sufficiently prepared.

This reverts commit 176928cc1371c23d499b474fa95e076b61f776c4.
DeltaFile
+134-39openmp/cmake/OpenMPTesting.cmake
+90-46openmp/runtime/CMakeLists.txt
+73-40openmp/CMakeLists.txt
+20-1openmp/runtime/unittests/CMakeLists.txt
+5-3openmp/runtime/src/CMakeLists.txt
+8-0clang/cmake/caches/VectorEngine.cmake
+330-1294 files not shown
+333-13310 files

LLVM/project 9a55899llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] combineSETCC - merge inner isScalarInteger() condition. NFC. (#182004)

All folds in the outer if() require this - inc combineVectorSizedSetCCEquality
DeltaFile
+95-98llvm/lib/Target/X86/X86ISelLowering.cpp
+95-981 files

LLVM/project 2dfa047flang/lib/Semantics check-omp-loop.cpp check-omp-structure.h

[flang][OpenMP] Include check for fully unrolled loops into nest check, NFC (#181729)

It's naturally a part of the verification of constructs nested in loop
constructs, so perform that check there instead of having it in a
separate function.
DeltaFile
+15-24flang/lib/Semantics/check-omp-loop.cpp
+0-1flang/lib/Semantics/check-omp-structure.h
+15-252 files

LLVM/project d154ec7llvm/lib/Transforms/Vectorize VPlanConstruction.cpp, llvm/test/Transforms/LoopVectorize pointer-induction.ll

[VPlan] Use ExitingIVValue for pointer inductions as well. (#180925)

Use ExitingIVValue from https://github.com/llvm/llvm-project/pull/175651
also for pointer inductions.

PR: https://github.com/llvm/llvm-project/pull/180925
DeltaFile
+34-27llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+1-12llvm/test/Transforms/LoopVectorize/pointer-induction.ll
+35-392 files

LLVM/project e1e0e86offload/plugins-nextgen/common/include PluginInterface.h

[Offload] Always check/consume Error (#182008)

This fixes an issue introduced in
https://github.com/llvm/llvm-project/pull/172226 where an llvm::Error is
not checked in the "good" code path.
DeltaFile
+3-1offload/plugins-nextgen/common/include/PluginInterface.h
+3-11 files

LLVM/project f8f799cllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/NVPTX i1-ext-load.ll

[DAG] Fold  (X +/- Y) & Y --> ~X & Y when Y is a power of 2 (or zero). (#181677)

Same as InstCombinerImpl::visitAnd

To prevent RISCV falling back to a mul call in known-never-zero.ll I've
had to tweak the (sub X, (vscale * C)) to (add X, (vscale * -C)) fold to
not occur if C is power-of-2 and the target has poor mul support.

Alive2: https://alive2.llvm.org/ce/z/Khvs5H
DeltaFile
+19-21llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
+11-11llvm/test/CodeGen/RISCV/idiv_large.ll
+8-12llvm/test/CodeGen/X86/known-pow2.ll
+11-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+3-4llvm/test/CodeGen/NVPTX/i1-ext-load.ll
+52-495 files

LLVM/project 9a4a38fllvm/test/CodeGen/AMDGPU llvm.amdgcn.image.sample.g16.a16.dim.ll, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.image.atomic.dim.a16.ll llvm.amdgcn.image.load.3d.a16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for INTRIN_IMAGE

Regbanklegalize rules for INTRIN_IMAGE loads and stores.
Because of very large number of different type signatures, rule specifies
only function for lowering (waterfall lowering of RsrcIdx operand if needed)
and this function also applies register banks.
DeltaFile
+268-52llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
+128-112llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
+114-50llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
+78-84llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
+58-70llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
+86-36llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
+732-40429 files not shown
+1,082-53235 files

LLVM/project 17b4a72llvm/test/tools/llvm-reduce unconditional-br-phi.ll unconditional-br.ll, llvm/tools/llvm-reduce DeltaPasses.def

[llvm-reduce] Add a pass to replace unconditional branches with returns (#180993)

Unconditional branches could end up in infinite loops in the reduced
code, while the code could have been reduce further.

This patch implements a simple pass that replaces unconditional branches
with returns.
DeltaFile
+89-0llvm/test/tools/llvm-reduce/unconditional-br-phi.ll
+40-0llvm/test/tools/llvm-reduce/unconditional-br.ll
+37-0llvm/tools/llvm-reduce/deltas/ReduceUsingSimplifyCFG.cpp
+2-2llvm/test/tools/llvm-reduce/reduce-invoke.ll
+2-0llvm/tools/llvm-reduce/DeltaPasses.def
+1-0llvm/tools/llvm-reduce/deltas/ReduceUsingSimplifyCFG.h
+171-26 files

LLVM/project ead7563llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 store-float-conversion.ll tbl-loops.ll

[AArch64] Improve post-inc stores of SIMD/FP values

Add patterns to match post-increment truncating stores from lane 0 of
wide integer vectors (v4i32/v2i64) to narrower types (i8/i16/i32).
This avoids transferring the value through a GPR when storing.

Also remove the pre-legalization early-exit in combineStoreValueFPToInt
as it prevented the optimization from applying in some cases.
DeltaFile
+260-0llvm/test/CodeGen/AArch64/store-float-conversion.ll
+7-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-2llvm/test/CodeGen/AArch64/tbl-loops.ll
+268-54 files

LLVM/project a210b35llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU fptoi.i128.ll global-saddr-load.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_PHI

Move G_PHI handling to AMDGPURegBankLegalizeRules.cpp.
Support all legal types.
DeltaFile
+183-157llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
+130-114llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
+70-65llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+45-48llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
+38-50llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+37-43llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+503-4779 files not shown
+580-53015 files

LLVM/project 48002eblldb/packages/Python/lldbsuite/test/tools/lldb-dap dap_server.py lldbdap_testcase.py, lldb/tools/lldb-dap JSONUtils.h JSONUtils.cpp

[lldb-dap] Remove dead code. (#181947)

It seems we have dead from the raw json days.
DeltaFile
+0-129lldb/unittests/DAP/JSONUtilsTest.cpp
+0-129lldb/tools/lldb-dap/JSONUtils.h
+2-105lldb/tools/lldb-dap/JSONUtils.cpp
+0-42lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
+0-35lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
+0-25lldb/tools/lldb-dap/LLDBUtils.cpp
+2-4653 files not shown
+2-5089 files

LLVM/project 4506982llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp, llvm/test/CodeGen/AArch64 rem.ll arm64-neon-mul-div.ll

[GlobalISel] Add G_UDIV/G_SDIV computeKnownBits (#181307)

Code ported from `SelectionDAG::computeKnownBits`.

Related: #150515
DeltaFile
+362-364llvm/test/CodeGen/AArch64/rem.ll
+154-150llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
+67-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-sdiv.mir
+55-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-udiv.mir
+18-0llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+2-2llvm/test/CodeGen/AArch64/funnel-shift.ll
+658-5166 files

LLVM/project b26ee7bllvm/test/Transforms/LoopInterchange phi-ordering.ll

[LoopInterchange] Fix test phi-ordering.ll (NFC)
DeltaFile
+37-32llvm/test/Transforms/LoopInterchange/phi-ordering.ll
+37-321 files

LLVM/project 2f708a9llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-instorder.ll interchangeable-outerloop-multiple-indvars.ll

[LoopInterchange] Fix instorder profitability check
DeltaFile
+50-41llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+40-30llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+1-1llvm/test/Transforms/LoopInterchange/interchangeable-outerloop-multiple-indvars.ll
+91-723 files

LLVM/project 9d7ca79llvm/test/Transforms/LoopInterchange profitability-instorder.ll

[LoopInterchange] Add a test for simple profitable case (NFC)
DeltaFile
+180-0llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+180-01 files

LLVM/project 10ccf11llvm/test/TableGen regunit-intervals.td, llvm/utils/TableGen RegisterInfoEmitter.cpp

[Tablegen] Patch RegUnitIntervals Initialization (#181173)

There were a few places it was missing some code-generation to properly
initialize it if enabled, and also it was missing the sentinel value.
DeltaFile
+13-2llvm/utils/TableGen/RegisterInfoEmitter.cpp
+3-0llvm/test/TableGen/regunit-intervals.td
+16-22 files

LLVM/project a13e04allvm/test/Transforms/LoopInterchange pr57148.ll lcssa-preheader.ll

[LoopInterchange] Update UTC version (NFC) (#181988)

This is a follow-up PR to #181804. While working on the stacked PRs, I
encountered some noisy diffs in the CHECK lines that don't change the
meaning of the tests. To avoid such changes and make the review easier,
this patch updates the UTC version. It also renames some BBs to suppress
warnings emitted by UTC.
DeltaFile
+99-99llvm/test/Transforms/LoopInterchange/pr57148.ll
+89-85llvm/test/Transforms/LoopInterchange/lcssa-preheader.ll
+82-82llvm/test/Transforms/LoopInterchange/interchangeable-outerloop-multiple-indvars.ll
+82-82llvm/test/Transforms/LoopInterchange/interchangeable-innerloop-multiple-indvars.ll
+69-67llvm/test/Transforms/LoopInterchange/update-condbranch-duplicate-successors.ll
+65-63llvm/test/Transforms/LoopInterchange/interchangeable.ll
+486-4784 files not shown
+639-62610 files

LLVM/project 6012aa1llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp

[AMDGPU] Fix opcode comparison logic for G_INTRINSIC (#156008)

The check `(Opc < TargetOpcode::GENERIC_OP_END)` incorrectly
includes `G_INTRINSIC` (129), which is less than
`GENERIC_OP_END` (313), leading to logically dead code.

This patch reorders the conditionals to first check for `G_INTRINSIC`,
ensuring
correct handling of the `amdgcn_fdot2` intrinsic.
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+4-41 files

LLVM/project e6cff75llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] combineMOVMSK - pull out repeated SDLoc (#181986)

DeltaFile
+3-6llvm/lib/Target/X86/X86ISelLowering.cpp
+3-61 files

LLVM/project 176928cclang/cmake/caches VectorEngine.cmake, openmp CMakeLists.txt

[OpenMP] Remove standalone build mode (#149878)

Remove all the CMake code for openmp standalone builds. Standalone
builds have been superseded by the runtimes default build (also
sometimes called the standalone runtimes build). The runtimes default
build can be thought of a standalone build with the standalone
boilerplate contained in <llvm-project>/runtimes/CMakeLists.txt. There
is no need for each runtime to contain the same boilerplate code again.

Builds still using the standalone build via
```sh
cmake -S <llvm-project>/openmp ...
```
can switch over to the runtimes default build using
```sh
cmake -S <llvm-project>/runtimes -DLLVM_ENABLE_RUNTIMES=openmp ...
```
Options that were valid for the standalone build are also valid for
default runtimes build, unless handled only in

    [8 lines not shown]
DeltaFile
+39-134openmp/cmake/OpenMPTesting.cmake
+46-90openmp/runtime/CMakeLists.txt
+43-76openmp/CMakeLists.txt
+1-20openmp/runtime/unittests/CMakeLists.txt
+3-5openmp/runtime/src/CMakeLists.txt
+0-8clang/cmake/caches/VectorEngine.cmake
+132-3334 files not shown
+136-33610 files

LLVM/project 3d3ad01clang/lib/Driver/ToolChains Clang.cpp, clang/lib/Driver/ToolChains/Arch AArch64.cpp AArch64.h

[Clang][AArch64] set default mtune for macOS (#179136)

This patch sets a default tune-cpu on macOS targets to `apple-m5`.

The implementation adds a helper in
`clang/lib/Driver/ToolChains/Arch/AArch64.h` called by
`clang/lib/Driver/ToolChains/Clang.cpp`. It doesnt follow a "check then
get" flow because its very concise, and returns an optional instead. It
adds a missing test file for mtune on Apple macOS targets, including the
new logic.
DeltaFile
+43-3clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+28-0clang/test/Driver/aarch64-mtune-apple-macos.c
+3-5clang/lib/Driver/ToolChains/Clang.cpp
+5-0clang/lib/Driver/ToolChains/Arch/AArch64.h
+79-84 files

LLVM/project c0c2ac0clang/lib/Headers amdhsa_abi.h CMakeLists.txt, clang/test/Headers amdhsa_abi.cl

clang: Add builtin header for amdhsa abi

This is place to put definitions for various ABI structs.
Currently device libs is just hardcoding magic numbers and casting
and it's incomprehensible.
DeltaFile
+166-0clang/test/Headers/amdhsa_abi.cl
+80-0clang/lib/Headers/amdhsa_abi.h
+1-0clang/lib/Headers/CMakeLists.txt
+247-03 files

LLVM/project 9057af9llvm/test/CodeGen/X86 known-pow2.ll

[X86] Add additional test coverage for #147216 (#181980)

DeltaFile
+57-0llvm/test/CodeGen/X86/known-pow2.ll
+57-01 files

LLVM/project 5a4d15ellvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange profitability-instorder.ll interchangeable-outerloop-multiple-indvars.ll

[LoopInterchange] Fix instorder profitability check
DeltaFile
+50-41llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+40-30llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+1-1llvm/test/Transforms/LoopInterchange/interchangeable-outerloop-multiple-indvars.ll
+91-723 files

LLVM/project 3478cdcllvm/test/Transforms/LoopInterchange profitability-instorder.ll

[LoopInterchange] Add a test for simple profitable case (NFC)
DeltaFile
+180-0llvm/test/Transforms/LoopInterchange/profitability-instorder.ll
+180-01 files

LLVM/project 97c34e3llvm/test/Transforms/LoopInterchange phi-ordering.ll

[LoopInterchange] Fix test phi-ordering.ll (NFC)
DeltaFile
+37-32llvm/test/Transforms/LoopInterchange/phi-ordering.ll
+37-321 files

LLVM/project 776ae18llvm/test/Transforms/LoopInterchange pr57148.ll lcssa-preheader.ll

[LoopInterchange] Update UTC version (NFC)
DeltaFile
+99-99llvm/test/Transforms/LoopInterchange/pr57148.ll
+89-85llvm/test/Transforms/LoopInterchange/lcssa-preheader.ll
+82-82llvm/test/Transforms/LoopInterchange/interchangeable-innerloop-multiple-indvars.ll
+82-82llvm/test/Transforms/LoopInterchange/interchangeable-outerloop-multiple-indvars.ll
+69-67llvm/test/Transforms/LoopInterchange/update-condbranch-duplicate-successors.ll
+65-63llvm/test/Transforms/LoopInterchange/interchangeable.ll
+486-4784 files not shown
+639-62610 files

LLVM/project 07931d4llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

Fixups
DeltaFile
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-11 files

LLVM/project 051d125llvm/lib/Target/X86 X86ISelLowering.cpp

Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC. (#181979)

DeltaFile
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+1-11 files