LLVM/project 9673aaeflang/lib/Lower PFTBuilder.cpp, flang/test/Lower/OpenACC acc-declare-interface-body.f90

[flang][OpenACC] Don't hoist declare directive out of interface bodies (#202806)

Example:
```fortran
program main
  real :: a(10, 60)
  interface
    subroutine compute(a)
      real :: a(10, 60)
!$acc declare present(a)
    end subroutine
  end interface
  call compute(a)
end program
```

In this code, the `!$acc declare` inside the interface body is hoisted
into the
host program unit and lowered there, where its operand (the interface

    [12 lines not shown]
DeltaFile
+43-0flang/test/Lower/OpenACC/acc-declare-interface-body.f90
+15-0flang/lib/Lower/PFTBuilder.cpp
+58-02 files

LLVM/project 4b3deaellvm/unittests/DebugInfo/PDB CMakeLists.txt

Fix DebugInfo unittests shared library build (#202943)

Fixes: `PublicsStreamTest.cpp.o: undefined reference to symbol
'_ZN4llvm6object18GenericBinaryErrorC1ERKNS_5TwineENS0_12object_errorE'`
under `BUILD_SHARED_LIBS=1`.
DeltaFile
+1-0llvm/unittests/DebugInfo/PDB/CMakeLists.txt
+1-01 files

LLVM/project 0cce782llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV select-aggregate.ll select-composite-constant.ll

[SPIR-V] Lower `select` instructions with aggregate operands (#201417)

Context: `SPIRVEmitIntrinsics` represents aggregate (array/struct) SSA
values as i32 value-ids, keeping the real type on the side for SPIR-V
emission. `preprocessCompositeConstants()` rewrites composite constant
operands into those value-ids.

A `select` takes its result type from its operands, so rewriting one arm
leaves the select with an aggregate result type but an i32 operand,
which is invalid. The exact failure mode depends: a composite-constant
arm tripped the verifier ("Select values must have same type as select
instruction"), while a non-constant arm (say a load) only became a
value-id later, in the visitor pass, at which point
`replaceMemInstrUses()` found a `select` among its users and hit an
unreachable.

I pushed two commits fixing this, one limited to my use case, another
more general:


    [20 lines not shown]
DeltaFile
+80-0llvm/test/CodeGen/SPIRV/select-aggregate.ll
+23-33llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+41-0llvm/test/CodeGen/SPIRV/select-composite-constant.ll
+144-333 files

LLVM/project 8210a58libcxxabi/src/demangle Utility.h, llvm/include/llvm/Demangle DemangleConfig.h Utility.h

[Demangle] Guard DEMANGLE_ABI and add missing annotation (#202920)

This updates the DEMANGLE_ABI annotation to only be defined if it is not
already defined. This is required to parse the Demangle headers with the
ids-check script.
In addition, this adds one missing DEMANGLE_ABI annotation.

This effort is tracked in #109483.
DeltaFile
+22-17llvm/include/llvm/Demangle/DemangleConfig.h
+1-1llvm/include/llvm/Demangle/Utility.h
+1-1libcxxabi/src/demangle/Utility.h
+24-193 files

LLVM/project dd07243flang/lib/Lower/OpenMP OpenMP.cpp, flang/test/Lower/OpenMP target-inreduction.f90

[flang][OpenMP] Model target in_reduction through map entries

Model omp.target in_reduction so the target body uses the mapped
map_entries block argument instead of a separate in_reduction entry
block argument.

The in_reduction operands remain on the op for host-side translation.
For the host-fallback path, the matching map block argument is redirected
to the pointer returned by __kmpc_task_reduction_get_th_data, so the
target body accumulates into the task reduction-private storage.

Flang lowering now relies on the implicit address-preserving map for the
target body binding, while task and taskloop keep their existing
in_reduction block-argument behavior.

Offload/device compilation is still diagnosed as not yet implemented, and
each target in_reduction variable must have a matching map_entries entry.
DeltaFile
+67-31mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+40-26mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+17-8flang/lib/Lower/OpenMP/OpenMP.cpp
+11-9mlir/test/Target/LLVMIR/openmp-target-in-reduction.mlir
+8-6flang/test/Lower/OpenMP/target-inreduction.f90
+9-0mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
+152-804 files not shown
+161-8910 files

LLVM/project 35ac9a4flang/lib/Lower/OpenMP OpenMP.cpp, flang/test/Lower/OpenMP target-inreduction.f90

[flang][OpenMP] Lower target in_reduction for host fallback

Teach Flang lowering and MLIR OpenMP translation to carry
in_reduction through omp.target for the host-fallback path.

The translation looks up task reduction-private storage with
__kmpc_task_reduction_get_th_data and binds the target region's
in_reduction block argument to that private pointer, so uses inside the
region do not keep referring to the original variable.

The patch also preserves in_reduction operands in the TargetOp builder
path and ensures target in_reduction list items are mapped into the
target region when needed.

The device/offload-entry path remains diagnosed as not yet implemented.
DeltaFile
+112-12mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+83-3mlir/test/Target/LLVMIR/openmp-todo.mlir
+62-18flang/lib/Lower/OpenMP/OpenMP.cpp
+60-0mlir/test/Dialect/OpenMP/invalid.mlir
+50-0mlir/test/Target/LLVMIR/openmp-target-in-reduction.mlir
+28-0flang/test/Lower/OpenMP/target-inreduction.f90
+395-333 files not shown
+432-539 files

LLVM/project b836063llvm/lib/Transforms/Scalar LoopFuse.cpp

[LoopFusion] Drop duplicate write-write dependence check (NFC) (#203173)

`dependencesAllowFusion()` re-tested every FC0-write vs FC1-write pair
in the second loop nest, duplicating the checks already done in the
first. Iterate only the remaining FC0-read vs FC1-write pairs; the set
of checked dependences (W0xW1, W0xR1, R0xW1) is unchanged.
DeltaFile
+4-7llvm/lib/Transforms/Scalar/LoopFuse.cpp
+4-71 files

LLVM/project 5e7ab8fflang/lib/Lower OpenACC.cpp, flang/test/Lower/OpenACC acc-unstructured.f90 acc-cache.f90

[OpenACC][flang] Emit NYI when unstructured loops are associated with OpenACC directives

When an unstructured loop is associated with a loop or a combined
directive, we emit an unstructured CFG for the loop's logic nested
within the OpenACC op. This effectively serializes the nested loop on
the device which is not desirable. For now, emit NYI's while working on
a longer-term solution.

The NYI is restricted to the cases where the loop will be lowered with
`independent` parallelism semantics for the default device_type -- i.e.,
the user has explicitly promised the loop is parallel. This covers:
- combined `acc parallel loop`,
- standalone `acc loop` inside `acc parallel`,
- orphan `acc loop` inside a non-`seq` acc routine,
- explicit `independent` clause.

For `auto` (`acc kernels loop` and `acc loop` inside `acc kernels`) and
for `seq` (`acc serial loop`, `acc loop` inside `acc serial`, explicit
`seq`, or orphan inside a `seq` routine), the user has not made a

    [4 lines not shown]
DeltaFile
+88-151flang/test/Lower/OpenACC/acc-unstructured.f90
+123-16flang/lib/Lower/OpenACC.cpp
+120-0flang/test/Lower/OpenACC/Todo/acc-unstructured-loop-construct.f90
+3-116flang/test/Lower/OpenACC/acc-cache.f90
+69-0flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
+0-41flang/test/Lower/OpenACC/acc-loop-exit.f90
+403-3246 files

LLVM/project 700ff25libcxx/include thread

[libc++] Hoist <compare> outside the threads guard in <thread> (#202535)

The standard mandates [thread.syn] include <compare> as part of
<thread>'s synopsis. This is a standards-mandated dependency, not a
thread-feature dependency, so it should be visible regardless of
_LIBCPP_HAS_THREADS.

This matches how we handle standard-mandated includes elsewhere, see for
example #134877.
DeltaFile
+5-5libcxx/include/thread
+5-51 files

LLVM/project 9081432mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp, mlir/test/Target/LLVMIR openmp-taskloop-reduction.mlir openmp-todo.mlir

[mlir][OpenMP] Translate reductions on taskloop

Add LLVM IR translation for reduction and in_reduction clauses on omp.taskloop.context.

For taskloop reduction, emit the implicit taskgroup reduction setup and map each generated task to runtime-provided private reduction storage through __kmpc_task_reduction_get_th_data. For in_reduction, use the same runtime lookup path with a null descriptor to join an enclosing task reduction context.

Unsupported byref, cleanup, and two-argument initializer forms remain diagnosed.

Add MLIR translation tests for the supported taskloop reduction and in_reduction cases.
DeltaFile
+245-0mlir/test/Target/LLVMIR/openmp-taskloop-reduction.mlir
+221-22mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+92-10mlir/test/Target/LLVMIR/openmp-todo.mlir
+558-323 files

LLVM/project 046bd54llvm/test/CodeGen/RISCV xqccmp-push-pop-popret.ll qci-interrupt-attr.ll, llvm/test/CodeGen/RISCV/rvv nontemporal-vp-scalable.ll

[RISCV] Set CostPerUse to 1 only when optimizing for size (#201501)

We saw some regressions because of bad RAs as the cost of registers
beyond x8-x15 are bigger. This is why `DisableCostPerUse` was added
in https://github.com/llvm/llvm-project/issues/83320.

In this PR, we change it to set `CostPerUse=1` only when optimizing
for size.

Code size increases less than 0.1% in llvm-test-suite.
DeltaFile
+904-904llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+870-870llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
+632-632llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+600-600llvm/test/CodeGen/RISCV/push-pop-popret.ll
+288-288llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+244-244llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+3,538-3,53811 files not shown
+4,469-4,46617 files

LLVM/project 5e7ec28clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-misc.c v8.2a-neon-intrinsics.c

[clang][CIR][AArch64] Add lowering for conversion intrinsics (#199990)

This PR adds lowering for intrinsic from the following groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions-2

It continues the work started in #190961 and #193273. This PR implements
conversions from FP to integer types where the bit-wdith does not
change:
  * vcvt_s64_f64
  * vcvt_u64_f64
  * vcvt_s32_f32
  * vcvtq_s32_f32
  * vcvtq_s64_f64
  * vcvt_u32_f32
  * vcvtq_u32_f32
  * vcvtq_u64_f64
  * vcvt_s16_f16
  * vcvtq_s16_f16

    [10 lines not shown]
DeltaFile
+114-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+87-0clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c
+0-78clang/test/CodeGen/AArch64/neon-misc.c
+0-52clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
+0-28clang/test/CodeGen/AArch64/neon-intrinsics.c
+14-1clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+215-1596 files

LLVM/project 67d211amlir/lib/Conversion/ComplexToSPIRV ComplexToSPIRV.cpp, mlir/test/Conversion/ComplexToSPIRV complex-to-spirv.mlir

[mlir][SPIR-V] Convert complex.neg and complex.conj in ComplexToSPIRV (#202898)
DeltaFile
+36-2mlir/lib/Conversion/ComplexToSPIRV/ComplexToSPIRV.cpp
+31-0mlir/test/Conversion/ComplexToSPIRV/complex-to-spirv.mlir
+67-22 files

LLVM/project 123078cmlir/include/mlir/Conversion Passes.td, mlir/lib/Conversion/ConvertToEmitC ConvertToEmitCPass.cpp

Reland emitc lower multi return functions (#203026)

Reland #200659 reverted by #202911.

Fixed GCC 7 func-to-emitc build: Use the adaptor operand types
when creating the multi-return struct type instead of relying on an
implicit conversion from ValueRange to TypeRange.

Failed buildbot:
https://lab.llvm.org/buildbot/#/builders/116/builds/29302

Assisted-by: Copilot
DeltaFile
+236-25mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
+96-2mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
+87-1mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
+63-0mlir/test/Target/Cpp/func.mlir
+13-5mlir/lib/Conversion/ConvertToEmitC/ConvertToEmitCPass.cpp
+6-0mlir/include/mlir/Conversion/Passes.td
+501-337 files not shown
+512-3913 files

LLVM/project 0d1a5e7llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange inner-induciton-step-is-not-invariant.ll

[LoopInterchange] Reject if inner loop IV has outer-variant step
DeltaFile
+20-48llvm/test/Transforms/LoopInterchange/inner-induciton-step-is-not-invariant.ll
+7-1llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+27-492 files

LLVM/project dd8c5c2llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange reduction2mem-limitation.ll

[LoopInterchange] Consolidate induction and reduction vars check
DeltaFile
+72-95llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+4-10llvm/test/Transforms/LoopInterchange/reduction2mem-limitation.ll
+76-1052 files

LLVM/project 7e6f2b7llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.set.inactive.chain.arg.ll amdgpu-cs-chain-preserve-cc.ll

AMDGPU/GlobalISel: RegBankLegalize rules for set_inactive intrinsics (#203047)
DeltaFile
+103-119llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
+31-27llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
+25-25llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
+6-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+2-2llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
+171-1771 files not shown
+173-1797 files

LLVM/project d3d0927llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch crc.ll

[LoongArch] Propagate demanded bits for CRC[C].W.{B,H}.W

CRC byte and halfword instructions only use the low 8 or 16 bits of
their data operand. Propagate these demanded-bit requirements through
SimplifyDemandedBitsForTargetNode() so redundant masking operations can
be removed during DAG combining.
DeltaFile
+21-4llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+0-4llvm/test/CodeGen/LoongArch/crc.ll
+21-82 files

LLVM/project 9ebbc1ellvm/docs ReleaseNotes.md, llvm/include/llvm/ADT APInt.h

[APInt] Provide sqrtFloor (floor of square root) instead of sqrt (rounded) (#197406)

This simplifies both the implementation and the only in-tree user.

I changed the name to avoid silently changing the behavour of an
existing function that might have out-of-tree users.
DeltaFile
+12-33llvm/lib/Support/APInt.cpp
+20-6llvm/unittests/ADT/APIntTest.cpp
+2-2llvm/include/llvm/ADT/APInt.h
+3-0llvm/docs/ReleaseNotes.md
+37-414 files

LLVM/project 34a321allvm/test/Transforms/LoopVectorize/ARM mve-reductions.ll mve-reduction-predselect.ll

[LV][NFC] Remove instcombine pass from RUN lines in ARM tests (#202913)

Following on from PR #197448 I've now removed the instcombine pass from
RUN lines in the ARM test directory, which exposes some potential
missing optimisations in vplan:

1. We could be folding IR into saturating math intrinsic calls to better
reflect the cost.
2. Masked load + select -> masked load with different passthru.
3. icmp + select -> smin/smax.

Some of these were already observed in #197448
DeltaFile
+141-107llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
+56-46llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
+51-45llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll
+34-19llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
+14-12llvm/test/Transforms/LoopVectorize/ARM/mve-reductions-interleave.ll
+13-8llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
+309-2372 files not shown
+321-2478 files

LLVM/project 64fbde5llvm/test/CodeGen/LoongArch crc.ll

[LoongArch][NFC] Add demanded bits tests for CRC[C].W.{B,H}.W
DeltaFile
+50-0llvm/test/CodeGen/LoongArch/crc.ll
+50-01 files

LLVM/project 9347582llvm/include/llvm/Target/GlobalISel SelectionDAGCompat.td, llvm/lib/Target/AArch64 AArch64InstrInfo.td

[GlobalISel] Remove `fp_to_[s/u]int_sat_gi` node (#202908)

Instead of having a separate node reuse `fp_to_[s/u]int_sat`
but drop the saturation width from it.

Assisted-by: Claude Code
DeltaFile
+43-120llvm/lib/Target/AArch64/AArch64InstrInfo.td
+19-0llvm/utils/TableGen/GlobalISelEmitter.cpp
+0-14llvm/lib/Target/AMDGPU/VOP1Instructions.td
+7-0llvm/test/TableGen/GlobalISelEmitter/SkippedPatterns.td
+0-5llvm/lib/Target/AMDGPU/SOPInstructions.td
+2-2llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+71-1411 files not shown
+71-1437 files

LLVM/project e1e5b37llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange inner-induciton-step-is-not-invariant.ll

[LoopInterchange] Reject if inner loop IV has outer-variant step
DeltaFile
+20-48llvm/test/Transforms/LoopInterchange/inner-induciton-step-is-not-invariant.ll
+7-1llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+27-492 files

LLVM/project 4b445c6llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange reduction2mem-limitation.ll

[LoopInterchange] Consolidate induction and reduction vars check
DeltaFile
+78-93llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+0-6llvm/test/Transforms/LoopInterchange/reduction2mem-limitation.ll
+78-992 files

LLVM/project b65e7e4llvm/lib/Target/Xtensa XtensaAsmPrinter.cpp, llvm/lib/Target/Xtensa/AsmParser XtensaAsmParser.cpp

[Xtensa] Fix code generation for TLS variables. (#202822)

This MR fixes https://github.com/llvm/llvm-project/issues/190202
DeltaFile
+50-0llvm/test/MC/Xtensa/tls.s
+30-0llvm/test/CodeGen/Xtensa/tls.ll
+7-1llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
+0-7llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
+1-5llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
+4-0llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp
+92-136 files

LLVM/project c1e628allvm/test/Transforms/LoopInterchange inner-induciton-step-is-not-invariant.ll

[LoopInterchange] Add tests for outer-variant inner IV step (NFC)
DeltaFile
+147-0llvm/test/Transforms/LoopInterchange/inner-induciton-step-is-not-invariant.ll
+147-01 files

LLVM/project d6abc8fllvm/test/Transforms/LoopInterchange fp-reductions.ll reductions-across-inner-and-outer-loop.ll

[LoopInterchange] Use UTC as much as possible (NFC) (#202096)

Historically, the loop-interchange tests have relied heavily on checks
via pass remarks. This is because pass remarks are more human-readable
than the CHECK directives generated by UTC. However, during recent
development, I found some downsides:

- Updating them manually is a bit tedious.
- We need to carefully keep the remarks and the code consistent with
each other. In other words, we don't have any way to verify whether the
remarks themselves are reasonable.

For these reasons, I now think it makes more sense to rely on UTC as
much as possible, and this patch does that. Some tests are left as-is,
e.g., the test for checking remarks.

Disclosure: This patch is assisted-by Claude Code.
DeltaFile
+364-49llvm/test/Transforms/LoopInterchange/fp-reductions.ll
+209-117llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
+277-43llvm/test/Transforms/LoopInterchange/reductions-non-wrapped-operations.ll
+188-40llvm/test/Transforms/LoopInterchange/legality-for-scalar-deps.ll
+148-33llvm/test/Transforms/LoopInterchange/profitability-vectorization-heuristic.ll
+97-45llvm/test/Transforms/LoopInterchange/currentLimitation.ll
+1,283-32716 files not shown
+2,089-56822 files

LLVM/project 86154e8llvm/include/llvm/CodeGen/GlobalISel LegalizerHelper.h Utils.h, llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp Utils.cpp

Reapply "[GlobalISel] Add a shared matcher for memcpy-family instructions (NFC)" (#202275) (#202298)

sanitizer-aarch64-linux-bootstrap-ubsan broke after #201766:
lab.llvm.org/buildbot/#/builders/85/builds/22356

  failed tests:
    LLVM :: CodeGen/AArch64/aarch64-mops.ll
    LLVM :: CodeGen/AArch64/memsize-remarks.ll

The culprit is canLowerMemCpyFamily returning true for zero-length ops
before initializing IsVolatile. The memcpy-family lowering helpers don't
use IsVolatile, it's only needed while building the lowering plan with
findGISelOptimalMemOpLowering and shouldn't have been forwarded.

I've also check the other arguments and simplified alignment too.

This reverts commit 2de2edb943fe1b83d79bdffa03606eb8c5452e9b.
DeltaFile
+31-186llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+179-0llvm/lib/CodeGen/GlobalISel/Utils.cpp
+10-5llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+13-0llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+233-1914 files

LLVM/project 63e33c6llvm/include/llvm/Support GlobPattern.h, llvm/lib/Support GlobPattern.cpp

[NFC][Support] Implement slash-agnostic path matching in GlobPattern (#202854)

Add a SlashAgnostic option to GlobPattern to allow matching path
separators
(both forward slashes and backslashes) agnostically.

When enabled:
- We conservatively reduce the plain prefix and suffix by treating path
  separators as metacharacters. This ensures that path separators are
  matched via the slash-agnostic state machine rather than plain string
  comparison.
- Brackets containing slashes are adjusted to match both separators.
- Character comparisons in the state machine (matchChar) treat '/' and
  '\' as equivalent.

For #149886.

Co-authored-by: Devon Loehr <DKLoehr at users.noreply.github.com>

Assisted-by: Gemini
DeltaFile
+62-0llvm/unittests/Support/GlobPatternTest.cpp
+37-14llvm/lib/Support/GlobPattern.cpp
+6-3llvm/include/llvm/Support/GlobPattern.h
+105-173 files

LLVM/project dcf3585llvm/test/CodeGen/RISCV clmul.ll clmulr.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll clmul-sdnode.ll

Merge branch 'main' into users/kasuga-fj/loop-interchage-use-utc
DeltaFile
+38,494-84,026llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+22,388-22,086llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+19,087-24,391llvm/test/CodeGen/RISCV/clmul.ll
+10,473-12,572llvm/test/CodeGen/RISCV/clmulr.ll
+10,281-12,374llvm/test/CodeGen/RISCV/clmulh.ll
+8,361-8,920llvm/test/CodeGen/RISCV/rvv/expandload.ll
+109,084-164,3693,893 files not shown
+434,153-338,7713,899 files