1,035,354 commits found in 80 milliseconds
LLVM /project 609c955 — mlir/include/mlir/Bindings/Python IRCore.h, mlir/lib/Bindings/Python MainModule.cpp IRTypes.cpp works
LLVM /project 10d6a02 — libc/include pthread.yaml, libc/src/pthread pthread_attr_getschedparam.cpp pthread_attr_setschedparam.cpp [libc] Add stub pthread_attr_getschedparam / pthread_attr_setschedparam (#173440)
Add the boilerplate for declaring these POSIX functions and
providing implementations. So far the only implementations are
just stubs that fail with ENOTSUP, and they are neither tested
nor included in any CMake entrypoints lists. More work is still
required to add the actual fields to the pthread_attr_t and
implement the support in the Linux pthread_create et al, but that
is not done here. It's not an especially large amount of work,
but more than just trivial.
The scaffolding here paves the way for that later work, but is
also immediately useful for filling out the subset of POSIX
pthread_attr_* functions that Fuchsia's libc already supports. LLVM /project c7cce95 — llvm/lib/Target/RISCV RISCVInsertVSETVLI.cpp RISCVVSETVLIInfoAnalysis.h Remove braces
Created using spr 1.3.6-beta.1
LLVM /project 49b5358 — llvm/lib/Target/RISCV RISCVInsertVSETVLI.cpp RISCVVSETVLIInfoAnalysis.h [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
LLVM /project 5e69a7f — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV atomic-rmw.ll rebase
Created using spr 1.3.4
Delta File +53,434 -51,436 llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll +17,545 -20,831 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +18,291 -16,006 llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll +19,255 -3,889 llvm/test/CodeGen/RISCV/atomic-rmw.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +126,504 -114,353 24,755 files not shown +2,051,833 -870,554 24,761 files
LLVM /project 3742d59 — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV atomic-rmw.ll [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Delta File +53,434 -51,436 llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll +17,545 -20,831 llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll +18,291 -16,006 llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll +19,255 -3,889 llvm/test/CodeGen/RISCV/atomic-rmw.ll +8,998 -11,093 llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll +8,981 -11,098 llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll +126,504 -114,353 24,755 files not shown +2,051,833 -870,554 24,761 files
LLVM /project 4b65538 — llvm/lib/IR Instructions.cpp, llvm/test/Transforms/DFAJumpThreading dfa-unfold-select.ll [IR] Change PHINode::removeIncomingValueIf() to loop incoming values backwards
[llvm][RISCV] Support Zvfofp8min llvm intrinsics and codegen (#172585)
This is follow up patch for
https://github.com/llvm/llvm-project/pull/157014
to support llvm intrinsics and codegen. [flang][NFC] Fixed a merge artifact in Intrinsics.md (#173443)
Removed "HEAD" line from some past merge. LLVM /project 5aa8882 — mlir/examples/standalone/test/python smoketest.py, mlir/include/mlir/Bindings/Python IRCore.h kind of works
[BOLT][NFC] Split up StaleProfileMatching::matchWeights (#165492)
Simplify matchWeights in preparation for pseudo probe matching
(#100446).
Test Plan: NFC Fix bazel build for 51253b3 (#173437)
Co-authored-by: Pranav Kant <prka at google.com> LLVM /project c91cfd4 — clang/lib/AST/ByteCode Context.cpp, clang/test/AST/ByteCode char-buffer-arithmetic.c Finally worked out how to test the string size computation
[RISCV] Pre-commit RVV instructions to the Ands45 scheduling model and tests (#171954)
This is like what spacemit x60 did in
https://github.com/llvm/llvm-project/commit/c4d4e761ef27d6dd27323cf3efa506db5e9e3457. LLVM /project 520ba7d — clang/test/Driver print-supported-extensions-riscv.c, llvm/docs RISCVUsage.rst [RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental (#173331)
Version 0.13 of the Xqci Qualcomm uC Vendor Extension has been marked as
frozen. We've had assembler support for this since LLVM20 and code
generation support since LLVM21. I think we have enough coverage in the
code base to mark the extension as non-experimental. LLVM /project f0597e1 — llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fmed3.ll [AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_FMED3 (#173085)
LLVM /project 935da9d — mlir/include/mlir/Bindings/Python IRCore.h, mlir/lib/Bindings/Python MainModule.cpp Pass.cpp kind of works
LLVM /project 389e5a9 — mlir/include/mlir/Bindings/Python IRCore.h, mlir/lib/Bindings/Python MainModule.cpp Pass.cpp kind of works
[lldb] Add Python 3.8 compatibility for lldbtest.py (#173392)
follow up from 9892870687e0af00e798474aa5cecfd4647071e1 as we recently
added type hints to this file LLVM /project 9b020dd — lld/test/wasm/lto stub-library.s stub-library-libcall.s, lld/test/wasm/lto/Inputs funcs.ll foo.ll [lld][WebAssembly] Don't export deps for unused stub symbols (#173422)
When a stub .so file contains
```
A: B
```
And `A` is defined in bitcode that's pulled in for LTO, but both `A` and
`B` are removed in `LTO::linkRegularLTO` due to not being dead:
https://github.com/llvm/llvm-project/blob/24297bea9672722d8fbaaff137b301b0becaae9c/llvm/lib/LTO/LTO.cpp#L1042-L1054
Then the symbol `A` becomes undefined after LTO, `processStubLibraries`
tries to import `A` from JS, and tries to export its dependency `B`:
https://github.com/llvm/llvm-project/blob/24297bea9672722d8fbaaff137b301b0becaae9c/lld/wasm/Driver.cpp#L1108-L1109
But `B` is gone, causing this error:
```console
wasm-ld: error: ....: undefined symbol: B. Required by A
```
This PR checks if the symbol is used in regular objects before trying to
exporrt its dependences, ensuring the case above doesn't crash the
linker. LLVM /project 82d0ec9 — flang-rt/lib/runtime command.cpp environment.cpp, flang/include/flang/Common windows-include.h [flang] improve compatibility with mingw headers (#172041)
The mingw headers declare `__environ` already, leading to warnings due
to missing dllimport here. Similarly with _WIN32_WINNT may be already
defined from a header leading to nuisance warnings. And the getpid is
not defined in the current header set (it is in process.h), so that
needs to be defined, just like MSVC (this replaces
https://github.com/msys2/MINGW-packages/blob/576fc4bbfa9bff4d5ab81779a706723b5214fd7d/mingw-w64-flang/0103-fix-build-on-mingw.patch ). LLVM /project f7e19f1 — clang-tools-extra/clang-doc JSONGenerator.cpp Serialize.cpp, clang-tools-extra/clang-doc/assets clang-doc-mustache.css [clang-doc] Add navigation via namespaces
LLVM /project 5ae6964 — llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp Make KnownFPClass::exp not side-effecting
LLVM /project df6a4ca — llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp InstCombine: Handle exp/exp2/exp10 in SimplifyDemandedFPClass
I'm working on optimizing out the tail sequences in the
implementations of the 4 different flavors of pow. These
include chains of selects on the various edge cases.
Related to #64870
InstCombine: Add baseline tests for exp SimplifyDemandedFPClass
LLVM /project 9435649 — llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor nofpclass-exp.ll ValueTracking: Improve handling of exp intrinsic for overflow
Teach exp handling that positive inputs cannot introduce overflow,
and negative inputs cannot introduce underflow.
ValueTracking: Add baseline tests for computeKnownFPClass exp
This is already handled, but misses opportunities. Test cases
where the input is known positive or negative.
LLVM /project 24bbda9 — llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp Make KnownFPClass::canonicalize not side-effecting
LLVM /project fdeaf6f — llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp InstCombine: Handle canonicalize in SimplifyDemandedFPClass
Doesn't try to handle PositiveZero flushing mode, but I
don't believe it is incorrect with it.
LLVM /project a45ca44 — mlir/include/mlir/Dialect/XeGPU/IR XeGPUAttrs.td, mlir/include/mlir/Dialect/XeGPU/Utils XeGPULayoutUtils.h add layout set up rule for reduction
