LLVM/project 5c9c034libcxx/docs VendorDocumentation.rst, libcxx/include/__configuration availability.h

[libc++] Move the documentation for availability to our RST docs (#169371)

We have quite a bit of documentation inside <__configuration/availability.h>
about the availability markups. This documentation would be better to have as
part of our general documentation to improve discoverability. A link to the
new location is added to <__configuration/availability.h> as well.
DeltaFile
+4-49libcxx/include/__configuration/availability.h
+42-0libcxx/docs/VendorDocumentation.rst
+46-492 files

LLVM/project 220f25fclang/lib/Analysis ThreadSafety.cpp

s/callee/caller
DeltaFile
+1-1clang/lib/Analysis/ThreadSafety.cpp
+1-11 files

LLVM/project c7adcb4clang/test/SemaCXX warn-thread-safety-analysis.cpp

fix typo in test
DeltaFile
+1-1clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+1-11 files

LLVM/project 0a65849llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] EltsFromConsecutiveLoads - only attempt to recognise reverse patterns from all load element patterns (#170852)

Noticed while investigating a regression reported after #168706 - don't
attempt this if any elements are zero/undef - there is a potential issue
with reverse(insert_subvector(undef,load(),0)) patterns - but I haven't
managed to create a fail case.
DeltaFile
+2-1llvm/lib/Target/X86/X86ISelLowering.cpp
+2-11 files

LLVM/project 1df7b51clang/lib/Sema SemaChecking.cpp, clang/test/Sema format-attr-missing.c format-strings.c

[Sema] Suggest missing format attributes (#166738)

Implements the `-Wmissing-format-attribute` diagnostic as a subgroup of
`-Wformat-nonliteral`. It suggests adding format attributes to function
declarations that call other format functions and pass the format string
to them.

This is an updated implementation of #105479.

---------

Co-authored-by: Budimir Arandjelovic <budimir.arandjelovic at htecgroup.com>
DeltaFile
+228-0clang/test/Sema/format-attr-missing.c
+182-33clang/lib/Sema/SemaChecking.cpp
+94-15clang/test/Sema/format-strings.c
+68-0clang/test/Sema/format-attr-missing.m
+68-0clang/test/Sema/format-attr-missing.cpp
+55-0clang/test/Sema/format-attr-missing-gnu.c
+695-488 files not shown
+717-6014 files

LLVM/project 1e04c49clang/lib/Analysis ThreadSafety.cpp, clang/test/SemaCXX warn-thread-safety-analysis.cpp

fix comment
DeltaFile
+14-0clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+4-2clang/lib/Analysis/ThreadSafety.cpp
+18-22 files

LLVM/project 6b040b4lldb/source/Plugins/Process/gdb-remote ProcessGDBRemote.cpp

[lldb] Issue a warning when Target XML should have been used but we do not have libxml2 (#170663)

If you connect lldb without libxml2 enabled, to a debug stub,
that server may offer Target XML but lldb will not use it. This
often causes incorrect or missing registers.

So much so that I think users should be made aware of this so
they can find an lldb with libxml2 enabled.

This warning will only be printed when:
* The debug server offered us Target XML but lldb does not have libxml2,
and -
* qRegisterInfo was not supported by the debug server.

This means that (lldb without libxml2) -> (lldb-server or debugserver)
will not warn as we'll fall back to qRegisterInfo. All that's
potentially
missing is advanced register formatting information, which most people
won't notice is missing anyway. If they do, the logs contain information

    [34 lines not shown]
DeltaFile
+17-1lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+17-11 files

LLVM/project b01b273llvm/lib/Support CachePruning.cpp, llvm/lib/Support/Windows Path.inc

[Support][Windows] disk_space handle unicode paths (#170716)

replaces GetDiskFreeSpaceExA with GetDiskFreeSpaceExW to handle user
paths with Unicode characters

fixes: https://github.com/llvm/llvm-project/issues/170571

I’m not entirely sure the fix is correct, so I’d appreciate it if
someone more familiar with the code could review it. Thanks!
DeltaFile
+11-6llvm/lib/Support/Windows/Path.inc
+3-1llvm/lib/Support/CachePruning.cpp
+14-72 files

LLVM/project 17e0bacllvm/utils/gn/secondary/clang/lib/DependencyScanning BUILD.gn, llvm/utils/gn/secondary/clang/lib/Tooling BUILD.gn

[gn] port b70be3dc14c1f54 (clang/lib/DependencyScanning)
DeltaFile
+0-29llvm/utils/gn/secondary/clang/lib/Tooling/DependencyScanning/BUILD.gn
+25-0llvm/utils/gn/secondary/clang/lib/DependencyScanning/BUILD.gn
+15-0llvm/utils/gn/secondary/clang/unittests/DependencyScanning/BUILD.gn
+2-3llvm/utils/gn/secondary/clang/unittests/Tooling/BUILD.gn
+2-0llvm/utils/gn/secondary/clang/lib/Tooling/BUILD.gn
+1-1llvm/utils/gn/secondary/clang/tools/clang-scan-deps/BUILD.gn
+45-332 files not shown
+47-348 files

LLVM/project 39429ddclang-tools-extra/clang-tidy/tool check_alphabetical_order.py check_alphabetical_order_test.py, clang-tools-extra/test lit.cfg.py

[clang-tidy] Implement alphabetical order check (#166072)

The patch implements `clang-tidy-alphabetical-order-check.py`, a small
Python tool to normalize clang-tidy docs with deterministic ordering.

It currently checks these two files:
-
https://github.com/llvm/llvm-project/blob/main/clang-tools-extra/docs/clang-tidy/checks/list.rst?plain=1
-
https://github.com/llvm/llvm-project/blob/main/clang-tools-extra/docs/ReleaseNotes.rst?plain=1

Closes #166021

---------

Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
DeltaFile
+412-0clang-tools-extra/clang-tidy/tool/check_alphabetical_order.py
+394-0clang-tools-extra/clang-tidy/tool/check_alphabetical_order_test.py
+5-0clang-tools-extra/test/clang-tidy/infrastructure/alphabetical-order.test
+1-0clang-tools-extra/test/lit.cfg.py
+812-04 files

LLVM/project 691893emlir/lib/Dialect/ArmSME/Transforms OuterProductFusion.cpp

[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in OuterProductFusion.cpp (NFC)
DeltaFile
+3-3mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp
+3-31 files

LLVM/project e6d1deamlir/lib/Bindings/Python NanobindUtils.h, mlir/test/python/ir operation.py

[MLIR][Python] make Sliceable inherit from Sequence (#170551)

Generates type stubs like

```python
class RegionSequence(Sequence[Region]):
    def __add__(self, arg: RegionSequence, /) -> list[Region]: ...

    def __iter__(self) -> RegionIterator:
        """Returns an iterator over the regions in the sequence."""
```
DeltaFile
+11-1mlir/lib/Bindings/Python/NanobindUtils.h
+4-0mlir/test/python/ir/operation.py
+15-12 files

LLVM/project 0ecac6dllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

[AMDGPU] Inherit constructors from WaitcntGenerator. NFC. (#170845)

DeltaFile
+3-8llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+3-81 files

LLVM/project 90a14d2llvm/test/CodeGen/SPARC optcompare.ll

[SPARC][NFC] Update optcompare test that always returns false (#170025)

DeltaFile
+5-5llvm/test/CodeGen/SPARC/optcompare.ll
+5-51 files

LLVM/project 0f9ea8aclang/lib/Analysis ThreadSafety.cpp, clang/test/SemaCXX warn-thread-safety-analysis.cpp

move test to test_scoped_lockable
DeltaFile
+23-23clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+2-1clang/lib/Analysis/ThreadSafety.cpp
+25-242 files

LLVM/project 4ada42emlir/lib/Conversion/XeVMToLLVM XeVMToLLVM.cpp

[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in XeVMToLLVM.cpp (NFC)
DeltaFile
+1-1mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
+1-11 files

LLVM/project 64e3bcdllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

[AMDGPU] Add an assertion. NFCI.
DeltaFile
+1-0llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+1-01 files

LLVM/project fc7b7bbbolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp, bolt/unittests/Core MCPlusBuilder.cpp

[BOLT] Add assert wehn calling insertBTI on empty BBs

BOLT may generate empty BBs, e.g. around function splitting, to hold
temporary labels. If they are the target of a new indirect branch, the
BTI should be inserted into the first "real" BasicBlock.
DeltaFile
+14-0bolt/unittests/Core/MCPlusBuilder.cpp
+4-0bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+18-02 files

LLVM/project f827e4dlldb/tools/lldb-dap DAPLog.cpp

[lldb-dap] show a useful timestamp in log messages (#170737)

It becomes easier to see the time difference between requests and
responses
DeltaFile
+3-3lldb/tools/lldb-dap/DAPLog.cpp
+3-31 files

LLVM/project b36f89fllvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU rotr.ll rotl.ll

[AMDGPU] Make rotr illegal (#166558)

fshr is already legal and is strictly more powerful than rotr, so we
should only need selection patterns for fshr.
DeltaFile
+281-107llvm/test/CodeGen/AMDGPU/rotr.ll
+153-72llvm/test/CodeGen/AMDGPU/rotl.ll
+16-22llvm/test/CodeGen/AMDGPU/packetizer.ll
+0-27llvm/lib/Target/AMDGPU/SIInstructions.td
+7-8llvm/test/CodeGen/AMDGPU/shl.ll
+6-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+463-2364 files not shown
+465-24810 files

LLVM/project 740a3adllvm/test/CodeGen/AMDGPU atomicrmw_usub_sat.ll atomicrmw_usub_cond.ll, llvm/test/Transforms/AtomicExpand/AMDGPU expand-atomic-i32-agent.ll expand-atomic-i16.ll

AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)

Split off from https://github.com/llvm/llvm-project/pull/105553 as per
discussion there.
DeltaFile
+4,091-0llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
+1,315-0llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
+956-40llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
+614-284llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
+779-6llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
+686-9llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-system.ll
+8,441-33930 files not shown
+10,340-44536 files

LLVM/project 9e31e81clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/Sema SemaExpr.cpp

Adding compatibility tests for vector half to _Float16
DeltaFile
+75-0clang/test/SemaOpenCL/half-float16-vector-compatibility.cl
+30-30clang/include/clang/Basic/BuiltinsAMDGPU.def
+36-0clang/test/CodeGen/half-float16-vector-compatibility.cl
+6-0clang/lib/Sema/SemaExpr.cpp
+147-304 files

LLVM/project 89e9b4aclang/lib/CodeGen BackendUtil.cpp, llvm/include/llvm/Passes PassPlugin.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.5-bogner
DeltaFile
+23-10clang/lib/CodeGen/BackendUtil.cpp
+26-5llvm/include/llvm/Passes/PassPlugin.h
+0-5llvm/lib/Passes/PassPlugin.cpp
+49-203 files

LLVM/project db84960clang/test/CodeGen/AArch64/sme2-intrinsics acle_sme2_bfscale.c acle_sme2_bfmul.c, llvm/include/llvm/IR IntrinsicsAArch64.td

[AArch64] Add intrinsics for multi-vector FEAT_SVE_BFSCALE instructions (#163536)

These are the intrinsics prototype implemented, according to [1]
//BFMUL:
svbfloat16x2_t svmul[_bf16_x2](svbfloat16x2_t zd, svbfloat16x2_t zm) __arm_streaming;
svbfloat16x2_t svmul[_single_bf16_x2](svbfloat16x2_t zd, svbfloat16_t zm) __arm_streaming;
svbfloat16x4_t svmul[_bf16_x4](svbfloat16x4_t zd, svbfloat16x4_t zm) __arm_streaming;
svbfloat16x4_t svmul[_single_bf16_x4](svbfloat16x4_t zd, svbfloat16_t zm) __arm_streaming;

//BFSCALE
svbfloat16x2_t svscale[_bf16_x2](svbfloat16x2_t zdn, svint16x2_t zm) __arm_streaming;
svbfloat16x2_t svscale[_single_bf16_x2](svbfloat16x2_t zn, svint16_t zm) __arm_streaming;
svbfloat16x4_t svscale[_bf16_x4](svbfloat16x4_t zdn, svint16x4_t zm) __arm_streaming;
svbfloat16x4_t svscale[_single_bf16_x4](svbfloat16x4_t zn, svint16_t zm) __arm_streaming;
[1]ARM-software/acle#410
DeltaFile
+76-0clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
+76-0clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
+56-0llvm/test/CodeGen/AArch64/sme2-intrinsics-bfmul.ll
+56-0llvm/test/CodeGen/AArch64/sme2-intrinsics-bfscale.ll
+41-2llvm/include/llvm/IR/IntrinsicsAArch64.td
+24-0llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+329-21 files not shown
+340-27 files

LLVM/project bb5e556bolt/include/bolt/Core MCPlusBuilder.h, bolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp

[BOLT][BTI] rename addBTItoBBStart to insertBTI
DeltaFile
+14-14bolt/unittests/Core/MCPlusBuilder.cpp
+3-3bolt/include/bolt/Core/MCPlusBuilder.h
+1-1bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+18-183 files

LLVM/project ac7fddbclang/lib/Analysis ThreadSafety.cpp, clang/test/SemaCXX warn-thread-safety-analysis.cpp

Add more tests
DeltaFile
+13-6clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+1-4clang/lib/Analysis/ThreadSafety.cpp
+14-102 files

LLVM/project 533b502clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/Sema SemaExpr.cpp

Adding compatibility tests for vector half to _Float16
DeltaFile
+75-0clang/test/SemaOpenCL/half-float16-vector-compatibility.cl
+30-30clang/include/clang/Basic/BuiltinsAMDGPU.def
+36-0clang/test/CodeGen/half-float16-vector-compatibility.cl
+5-0clang/lib/Sema/SemaExpr.cpp
+146-304 files

LLVM/project cf53228clang/lib/Analysis ThreadSafety.cpp, clang/test/SemaCXX warn-thread-safety-analysis.cpp

false-posiitve thread-safety
DeltaFile
+16-0clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+7-0clang/lib/Analysis/ThreadSafety.cpp
+23-02 files

LLVM/project d17284amlir/python/mlir ir.py, mlir/test/python/ir auto_location.py

[python] Fix loc_tracebacks() (#170831)

There were two bugs lurking in mlir.ir.loc_tracebacks():
  1) The default None parameter was not handled correctly (passed to a
     C++ function that expects ints.
  2) The `yield` was incorrectly indented meaning loc_tracebacks()
     could not be nested (a "generator didn't yield" exception would be
     raised).

Added testing of loc_tracebacks by replacing the custom contextmanager
in the auto_location.py test with the loc_tracebacks() API.

Had to harden the test to line number differences.

---------

Co-authored-by: James Molloy <jmolloy at google.com>
DeltaFile
+13-18mlir/test/python/ir/auto_location.py
+2-1mlir/python/mlir/ir.py
+15-192 files

LLVM/project 77b1d7fllvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp

Fixed formatting
DeltaFile
+48-32llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+48-321 files