[AArch64] - Improve costing for Identity shuffles for SVE targets. (#165375)
Identity masks can be treated as free when scalable vectorization is
possible making the check agnostic of the vectorization policy
fixed/scalable, This allows for aggressive vector combines for identity
shuffle masks.
[AMDGPU] Don't fold an i64 immediate value if it can't be replicated from its lower 32-bit
On some targets, a packed f32 instruction can only read 32 bits from a scalar operand (SGPR or literal) and replicates the bits to both channels. In this case, we should not fold an immediate value if it can't be replicated from its lower 32-bit.
[RISCV] Make XFAIL test UNSUPPORTED. (#168525)
Currently the test cfi-multiple-location.mir is marked as XFAIL. This
causes failures on some build bots because the test unexpectedly passes.
Mark this test as UNSUPPORTED for now. Later I plan to merge an MR which
fixes an issue in CFIInstrInserter and this test will be enabled.
[DebugInfo][IR] Verifier checks for the extraData (#167971)
LLVM IR verifier checks for `extraData` in debug info metadata.
This is a follow-up PR based on discussions in #165023
Modify llvm-dwp to be able to emit string tables over 4GB without losing data (#167457)
We can change llvm-dwp to emit DWARF64 version of the .debug_str_offsets
tables for .dwo files in a .dwp file. This allows the string table to
exceed 4GB without truncating string offsets into the .debug_str section
and losing data. llvm-dwp will append all strings to the .debug_str
section for a .dwo file, and if any of the new string offsets exceed
UINT32_MAX, it will upgrade the .debug_str_offsets table to a DWARF64
header and then each string offset in that table can now have a 64 bit
offset.
Fixed LLDB to be able to successfully load the 64 bit string tables in
.dwp files.
Fixed llvm-dwarfdump and LLVM DWARF parsing code to do the right thing
with DWARF64 string table headers.
[dsymutil] Specify that -flat is for testing in the help output (#168590)
Gently discourage users from relying on -flat by specifying in the help
output that it's meant for testing.
Reland instr-ref-target-hooks-sp-clobber.mir (#168136)
This test was failing on chromium builds with error:
```
/Volumes/Work/s/w/ir/x/w/llvm_build/bin/llc -o - /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir -run-pass=livedebugvalues | /Volumes/Work/s/w/ir/x/w/llvm_build/bin/FileCheck /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir # RUN: at line 8
+ /Volumes/Work/s/w/ir/x/w/llvm_build/bin/llc -o - /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir -run-pass=livedebugvalues
+ /Volumes/Work/s/w/ir/x/w/llvm_build/bin/FileCheck /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir
error: YAML:121:3: unknown key 'stackSizePPR'
stackSizePPR: 0
^~~~~~~~~~~~
FileCheck error: '<stdin>' is empty.
FileCheck command line: /Volumes/Work/s/w/ir/x/w/llvm_build/bin/FileCheck /Volumes/Work/s/w/ir/x/w/llvm-llvm-project/llvm/test/DebugInfo/AArch64/instr-ref-target-hooks-sp-clobber.mir
```
This is an attempt to reland the failing test
Mips: Remove manual libcall name search and table
This should really check if the libcall is known supported.
For now mips doesn't configure its RuntimeLibcallsInfo
correctly, and does not have any of the mips16 calls in it.
For now there isn't a way to add them without triggering conflicting
cases in tablegen, so keep parsing the raw name as it was before.
[RISCV] Legalize misaligned unmasked vp.load/vp.store to vle8/vse8. (#167745)
If vector-unaligned-mem support is not enabled, we should not generate
loads/stores that are not aligned to their element size.
We already do this for non-VP vector loads/stores.
This code has been in our downstream for about a year and a half after
finding the vectorizer generating misaligned loads/stores. I don't think
that is unique to our downstream.
Doing this for masked vp.load/store requires widening the mask as well
which is harder to do.
NOTE: Because we have to scale the VL, this will introduce additional
vsetvli and the VL optimizer will not be effective at optimizing any
arithmetic that is consumed by the store.
[NFC][TableGen] Remove `close` member from various CodeGenHelpers (#167904)
Always rely on local scopes to enforce the lifetime of these helper
objects and by extension where the "closing" of various C++ code
constructs happens.
[clang][DependencyScanning] Add Test Coverage of `StabeDirs` during By-Name Lookups (#168143)
This PR adds some test coverage for `StableDirs` during by-name lookups.
[LLDB] Add log channel for InstrumentationRuntime plugins (#168508)
This patch adds `LLDBLog::InstrumentationRuntime` as a log channel to
provide an appropriate channel for instrumentation runtime plugins as
previously one did not exist.
A small use of the channel is added to illustrate its use. The logging
added is not intended to be comprehensive.
This is primarily motivated by an `-fbounds-safety` instrumentation
plugin (https://github.com/swiftlang/llvm-project/pull/11835).
rdar://164920875
[GISel][RISCV] Compute CTPOP of small odd-sized integer correctly (#168559)
Fixes the assertion in #168523
This patch lifts the small, odd-sized integer to 8 bits, ensuring that
the following lowering code behaves correctly.
[ARM] TableGen-erate node descriptions (#168212)
This allows SDNodes to be validated against their expected type profiles
and reduces the number of changes required to add a new node.
Some nodes fail validation, those are enumerated in
`ARMSelectionDAGInfo::verifyTargetNode()`. Some of the bugs are easy to
fix, but probably they should be fixed separately, this patch is already big.
Part of #119709.
Pull Request: https://github.com/llvm/llvm-project/pull/168212
[CI] Skip Running Premerge Advisor on AArch64 (#168404)
They were still running because the conditional was not correct. This
patch fixes that so they do not interefere with the results of the job.
[X86] Add test examples of build vectors of reversed scalar loads that could be converted to vector loads plus shuffles (#168571)
This is turning up in some legalisation code when shuffling vectors bitcast from illegal loads.
Ideally we'd handle more complex shuffles, but reverse is a start.
