LLVM/project 851ce84llvm/lib/CodeGen ModuloSchedule.cpp

ModuloSchedule: Use use_instructions instead of use_operands + getParent (#219297)

The use list only inspected the user, so directly loop over the users.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+6-7llvm/lib/CodeGen/ModuloSchedule.cpp
+6-71 files

LLVM/project b8cbca3llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

Update supportsWGP to use feature bits instead

Change-Id: Ie1ecc691fac766dc2f32ff4edcb41ccf2483a71c
DeltaFile
+1-3llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+1-31 files

LLVM/project 6a5367allvm/lib/CodeGen Rematerializer.cpp

Rematerializer: Use def_instructions instead of def_operands + getParent (#219298)

Directly iterate the user instructions instead of querying the same
parent for each use.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-4llvm/lib/CodeGen/Rematerializer.cpp
+2-41 files

LLVM/project c59f418llvm/include/llvm/ADT FoldingSet.h, llvm/include/llvm/Analysis ScalarEvolution.h

[ADT] Remove ComputeNodeHash and Trait::ComputeHash (NFC) (#219029)

With the switch to open addressing (commit b3411b89c3af),
FoldingSetNode stores its hash in the node itself.  Table growth
rehashes nodes by calling getFoldingSetHash(), leaving ComputeNodeHash
and Trait::ComputeHash unused.
DeltaFile
+0-36llvm/include/llvm/ADT/FoldingSet.h
+3-14llvm/include/llvm/CodeGen/SelectionDAG.h
+0-9llvm/include/llvm/Analysis/ScalarEvolution.h
+3-593 files

LLVM/project 9ebb067mlir/include/mlir/IR SymbolTable.h

[mlir][IR][NFC] Disambiguate `SymbolTable::Visibility` references (#219301)

As a follow-up to 979b722, address MSVC's confusion when it's trying to
resolve the underqualified enum name:
```
error C2955: 'mlir::OpTrait::SymbolTable': use of class template requires template argument list
```

Assisted-by: OpenAI Codex

Signed-off-by: Artem Gindinson <gindinson at roofline.ai>
DeltaFile
+11-10mlir/include/mlir/IR/SymbolTable.h
+11-101 files

LLVM/project 747588allvm/lib/Target/Hexagon HexagonBitSimplify.cpp

Hexagon: Use use_instructions in BitSimplify use scans

This only inspects the parent instruction, so use use_instructions
instead.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+8-10llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+8-101 files

LLVM/project 5964066compiler-rt/lib/scudo/standalone secondary.h, compiler-rt/lib/scudo/standalone/tests secondary_test.cpp

[scudo] Track maximum resident memory in cache (#219036)

Add tracking for the resident memory in MapAllocatorCache. Unreleased
cache entries where Time != 0 are assumed to be resident, while entries
that have passed through releaseOlderThan where Time == 0 have had their
physical pages discarded.

Tracking is performed by updating CurrentResidentBytes on store, remove,
and release operations, recoding the peak in maxResidentBytes and
reporting it in getStats.
DeltaFile
+44-0compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
+35-2compiler-rt/lib/scudo/standalone/secondary.h
+79-22 files

LLVM/project cd17483llvm/test/CodeGen/AArch64 vector-ldst-offset.ll vector-ldst-align.ll, llvm/test/CodeGen/AMDGPU/NextUseAnalysis test_ers_emit_restore_in_loop_preheader2.mir test_ers_nested_loops.mir

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+9,921-0llvm/test/CodeGen/AArch64/vector-ldst-align-float.ll
+8,227-0llvm/test/CodeGen/AArch64/vector-ldst-align.ll
+0-6,246llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
+0-4,877llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
+3,448-2llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
+2,421-285llvm/test/tools/llvm-mca/AArch64/Cortex/A57-forwarding.s
+24,017-11,4103,448 files not shown
+186,009-80,4233,454 files

LLVM/project 3aff3f8llvm/lib/Target/AMDGPU SIRegisterInfo.cpp AMDGPUInstructionSelector.cpp, llvm/lib/Target/RISCV RISCVRegisterInfo.h RISCVRegisterInfo.cpp

GlobalISel: Replace MachineOperand based register constraint API

Replace MachineOperand reference in getConstrainedRegClassForOperand with
a Register. It is only valid to call this on a generic vreg operand, which
must be a Register so there's no point in using an operand reference.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+31-33llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+6-6llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
+4-5llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+4-5llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-6llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
+3-2llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+50-575 files not shown
+59-6611 files

LLVM/project 367293aclang/include/clang/Basic OffloadArch.h, clang/lib/Basic Cuda.cpp OffloadArch.cpp

[Clang] Rename OffloadArch::TargetArch::SPIRV to AMDGCNSPIRV to avoid confusion (#218502)

Following up to
https://github.com/llvm/llvm-project/pull/213362/changes#r3745729994,
the `TargetArch::SPIRV` introduced by #213362 actually corresponds to
`amdgcnspirv`, which is not the same as standard SPIRV: This could prove
rather confusing in the future. Renaming to `TargetArch::AMDGCNSPIRV`
also decouples "`TargetArch::SPIRV`" from AMD-specific SPIRV support, as
SPIRV is used by other vendors as well.
DeltaFile
+12-10clang/include/clang/Basic/OffloadArch.h
+6-6clang/unittests/Basic/OffloadArchTest.cpp
+4-4clang/lib/Basic/OffloadArch.cpp
+3-3clang/lib/Driver/Driver.cpp
+2-2clang/lib/Basic/Cuda.cpp
+27-255 files

LLVM/project e192df0clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/test/CIR/CodeGen call-conv-lowering-x86_64-packed.c

[CIR] Classify a named bit-field access unit as a bit-field on x86_64

mapCIRType built the ABI FieldInfo for a bit-field access unit with IsBitField
set only for an unnamed one, so a named unit reached the classifier as an
ordinary field.  We now pass IsBitField with the unit's width to be able to
lower named bit-fields correctly.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+33-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-packed.c
+6-1clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+39-12 files

LLVM/project 41c2ec5llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

[KnownFPClass] Add `KnownFPClass::frem` [NFC] (#218949)

Follow up to https://github.com/llvm/llvm-project/pull/218726

Moves `frem` deduction logic from `Analysis/ValueTracking.cpp` and
`CodeGen/GlobalISel/GISelValueTracking.cpp` to `KnownFPClass::frem`.
DeltaFile
+30-0llvm/lib/Support/KnownFPClass.cpp
+1-18llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+1-18llvm/lib/Analysis/ValueTracking.cpp
+5-0llvm/include/llvm/Support/KnownFPClass.h
+37-364 files

LLVM/project a58e481mlir/lib/Dialect/XeGPU/Transforms XeGPUArrayLengthOptimization.cpp, mlir/test/Dialect/XeGPU array-len-op-unit.mlir

[MLIR][XeGPU] Update array-length users atomically (#217478)

Preflight load and slice users before changing tensor descriptor types,
then update their dependent types and offsets in one pattern
application.

Assisted-by: Codex
DeltaFile
+88-147mlir/lib/Dialect/XeGPU/Transforms/XeGPUArrayLengthOptimization.cpp
+198-2mlir/test/Dialect/XeGPU/array-len-op-unit.mlir
+286-1492 files

LLVM/project d97960dllvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp, llvm/test/CodeGen/AMDGPU lds-limit-diagnostics.ll

[AMDGPU] Ignore CU mode on targets without WGP mode

isFullSIMDMode() treated +cumode as meaningful on every generation, so on
pre-gfx10 targets it halved both the physical and the addressable LDS size
and dropped getNumWorkGroupSIMDs() from 4 to 2. Before the LDS size rework
the CU/WGP adjustment was gated on isGFX10Plus(), and +cumode was simply
ignored elsewhere.

rocFFT passes -mcumode to hipRTC unconditionally, so its Bluestein kernels
started failing to compile on gfx942 with "local memory (65536) exceeds
limit (32768)".

Change-Id: I0b440751aedd8f8b5d334ee62b68ffdc449d53f8
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+5-0llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
+3-1llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+8-12 files

LLVM/project 6560cd0llvm/lib/CodeGen Rematerializer.cpp

Rematerializer: Use def_instructions instead of def_operands + getParent

Directly iterate the user instructions instead of querying the same
parent for each use.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-4llvm/lib/CodeGen/Rematerializer.cpp
+2-41 files

LLVM/project 948eff3llvm/lib/CodeGen ModuloSchedule.cpp

ModuloSchedule: Use use_instructions instead of use_operands + getParent

The use list only inspected the user, so directly loop over the users.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+6-7llvm/lib/CodeGen/ModuloSchedule.cpp
+6-71 files

LLVM/project 0fd16c5llvm/lib/ProfileData InstrProf.cpp, llvm/test/tools/llvm-profdata merge-incompatible.test

[llvm-profdata] Clarify incompatible counter profile error (#219280)

Fix based on the comment on
https://github.com/llvm/llvm-project/pull/213177#pullrequestreview-5011647833
DeltaFile
+1-2llvm/lib/ProfileData/InstrProf.cpp
+1-1llvm/test/tools/llvm-profdata/merge-incompatible.test
+2-32 files

LLVM/project 6b1075cclang/test/CodeGen/AArch64/neon load.c, llvm/test/CodeGen/AMDGPU atomic_optimizations_global_pointer.ll

Merge branch 'users/adams381/cir-callconv-incomplete-record-decl' of https://github.com/llvm/llvm-project into cir-callconv-incomplete-record-decl
DeltaFile
+0-6,246llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
+0-4,877llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
+2,428-0llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-0.ll
+2,426-0llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-1.ll
+1,217-1,125llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+2,240-0clang/test/CodeGen/AArch64/neon/load.c
+8,311-12,2482,226 files not shown
+106,120-52,3252,232 files

LLVM/project a4d5d5fllvm/test/Transforms/SLPVectorizer/X86 splat-gather-operands.ll

[SLP][NFC]Add extra tests for gathered splats, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/219291
DeltaFile
+91-0llvm/test/Transforms/SLPVectorizer/X86/splat-gather-operands.ll
+91-01 files

LLVM/project 5d05e04offload/languages/include/kernel DefineLanguageNames.inc UndefineLanguageNames.inc, offload/languages/kernel/src LanguageRuntime.cpp

add StreamCreateWithFlags
DeltaFile
+26-1offload/languages/kernel/src/LanguageRuntime.cpp
+27-0offload/test/offloading/CUDA/stream_api.cu
+26-0offload/test/offloading/HIP/stream_api.hip
+10-1offload/languages/include/kernel/LanguageRuntime.h
+3-1offload/languages/include/kernel/UndefineLanguageNames.inc
+3-0offload/languages/include/kernel/DefineLanguageNames.inc
+95-36 files

LLVM/project 93bd9f4llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Remove unreachable visitMulExpr in SCEVCastSinkingRewriter (NFC) (#219279)

SCEVCastSinkingRewriter::visit() returns S unchanged unless S->getType()
is a pointer type. So visitMulExpr can never be entered.
DeltaFile
+0-10llvm/lib/Analysis/ScalarEvolution.cpp
+0-101 files

LLVM/project 18bd92aclang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/Driver cuda-via-liboffload.cu

add PerThreadDefaultStream
DeltaFile
+28-0offload/languages/kernel/CMakeLists.txt
+14-0clang/test/Driver/cuda-via-liboffload.cu
+12-0offload/languages/kernel/src/PerThreadDefaultStream.cpp
+6-3offload/languages/kernel/src/State.cpp
+5-0clang/lib/Driver/ToolChains/CommonArgs.cpp
+1-0offload/languages/kernel/exports
+66-36 files

LLVM/project bd63550offload/languages/kernel/include OffloadErrors.h State.h, offload/languages/kernel/src LanguageRuntime.cpp State.cpp

add interal StreamTy
DeltaFile
+246-89offload/languages/kernel/src/State.cpp
+78-37offload/languages/kernel/include/State.h
+32-26offload/languages/kernel/src/LanguageRuntime.cpp
+31-9offload/test/offloading/CUDA/stream_api.cu
+30-8offload/test/offloading/HIP/stream_api.hip
+38-0offload/languages/kernel/include/OffloadErrors.h
+455-1695 files not shown
+539-20111 files

LLVM/project aea3906clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/test/CIR/Transforms/abi-lowering declaration-rewrite.cir

[CIR] Drop the isX86 gate on the incomplete-record skip

Eli asked why the incomplete-record skip only applied to the x86_64
driver.  The reasoning behind it, that only a declaration can carry
this shape and no translation unit can ever call or define it, is a
language rule, not a target one, so the gate had no real reason to
be there.

Added a case to declaration-rewrite.cir that injects an "ignore"
classification for an incomplete-by-value parameter and checks the
argument survives anyway.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+12-0clang/test/CIR/Transforms/abi-lowering/declaration-rewrite.cir
+1-1clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+13-12 files

LLVM/project d2c003cmlir/lib/Dialect/OpenACC/Transforms ACCComputeLowering.cpp, mlir/test/Dialect/OpenACC acc-compute-lowering-compute.mlir

[mlir][OpenACC] Lower constant sized loop clauses (#219043)

Add support for sized loop clauses (`acc.loop
vector(n)/worker(n)/gang(num:n)`) in kernels constructs. Collect
constant sizes from kernels loops before conversion and add them to the
launch arguments. Treat the parallelism levels associated with sized
clauses as regular levels when assigning par_dims to loops. Non-constant
sizes remain NYI.
DeltaFile
+91-13mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
+31-0mlir/test/Dialect/OpenACC/acc-compute-lowering-compute.mlir
+122-132 files

LLVM/project e947b0cclang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded vabd.c vabdu.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded vabdu.c

Merge branch 'main' into users/adams381/cir-callconv-optout-openacc-declare
DeltaFile
+2,428-0llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-0.ll
+2,426-0llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-1.ll
+2,058-2libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
+1,449-52clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
+1,449-52clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
+1,419-52clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
+11,229-158971 files not shown
+49,798-9,531977 files

LLVM/project dd1e73emlir/test/Integration/Dialect/XeGPU/WG load_store_matrix.mlir simple_mxfp_gemm_dequantizeB_F4.mlir

[MLIR][XeGPU][NFC]  Fix WG integration tests for strict property assembly format (#219256)

b73a8b8d8c17 ("[MLIR][XeGPU] Enable strict property assembly format",
#217281) made inherent attributes stored as properties unparseable from
the trailing attr-dict, but two XeGPU workgroup integration tests still
write `layout` that way, so they fail to parse.

Move the affected `layout`/`layout_a`/`layout_b`/`layout_cd` operands
into the prop-dict position, `{...}` -> `<{...}>`, for
xegpu.load_matrix, store_matrix, load_nd, store_nd and dpas.

These tests only run when the Level Zero or SYCL runner is enabled
(MLIR_ENABLE_LEVELZERO_RUNNER / MLIR_ENABLE_SYCL_RUNNER), which is why
the breakage was not caught by the default CI configuration.

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+7-7mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F4.mlir
+4-4mlir/test/Integration/Dialect/XeGPU/WG/load_store_matrix.mlir
+11-112 files

LLVM/project a6be255llvm/include/llvm/Analysis TargetTransformInfo.h, llvm/lib/Transforms/Scalar LowerMatrixIntrinsics.cpp

[NFC][TTI] Remove default CostKind from TTI::getMemoryOpCost() (#219070)

Addresses #135598.
DeltaFile
+10-8llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
+5-5llvm/include/llvm/Analysis/TargetTransformInfo.h
+15-132 files

LLVM/project 8dc9a50clang/test/CIR/CodeGenOpenACC declare-deviceresident.cpp declare-create.cpp

[CIR] Pin x86_64 in the OpenACC declare tests

The six OpenACC declare tests dropped their CallConvLowering opt-out
without pinning a target, so `%clang_cc1` fell back to the build's
default triple.  That was harmless while the opt-out flag kept
CallConvLowering from running, but the pass's byref classification for
`HasSideEffects` is target-dependent, and the Linux AArch64 CI leg
defaults to `aarch64-unknown-linux-gnu`, not x86_64.  Pin
`-triple x86_64-unknown-linux-gnu`, matching the other CIR test in this
directory that already exercises CallConvLowering deliberately.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+2-2clang/test/CIR/CodeGenOpenACC/declare-present.cpp
+1-1clang/test/CIR/CodeGenOpenACC/declare-deviceresident.cpp
+1-1clang/test/CIR/CodeGenOpenACC/declare-create.cpp
+1-1clang/test/CIR/CodeGenOpenACC/declare-copyout.cpp
+1-1clang/test/CIR/CodeGenOpenACC/declare-copyin.cpp
+1-1clang/test/CIR/CodeGenOpenACC/declare-copy.cpp
+7-76 files

LLVM/project 9ada7c3llvm/lib/Target/AMDGPU SIRegisterInfo.cpp AMDGPUInstructionSelector.cpp, llvm/lib/Target/RISCV RISCVRegisterInfo.cpp

GlobalISel: Replace MachineOperand based register constraint API

Replace MachineOperand reference in getConstrainedRegClassForOperand with
a Register. It is only valid to call this on a generic vreg operand, which
must be a Register so there's no point in using an operand reference.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+23-22llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+4-5llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+4-5llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-6llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
+3-3llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
+3-2llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
+39-435 files not shown
+48-5211 files