LLVM/project 0256ff9clang/test lit.cfg.py

[clang][test][AIX] Set OBJECT_MODE=any for all clang test (#209531)

This patch sets OBJECT_MODE=any to have tools able to handle 32-bit or
64-bit objects.
DeltaFile
+1-4clang/test/lit.cfg.py
+1-41 files

LLVM/project 2dac2abutils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel][mlir] Port b8ba3c2b72cb53268129bbecfeb4ba7ec5b8d831 (#209854)

Add SCFToAffine target + deps
DeltaFile
+21-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+21-01 files

LLVM/project 889b2d6clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins QuadReadAcrossDiagonal.hlsl QuadReadAcrossX.hlsl

[HLSL] Adds diagnostics for missing/ambiguous shader entry function. (#184892)

Addresses #119260.
DeltaFile
+24-24clang/test/SemaHLSL/BuiltIns/unary-compat-overload-warnings.hlsl
+27-3clang/test/SemaHLSL/entry_shader.hlsl
+22-0clang/lib/Sema/SemaHLSL.cpp
+16-3clang/test/SemaHLSL/num_threads.hlsl
+4-4clang/test/CodeGenHLSL/builtins/QuadReadAcrossDiagonal.hlsl
+4-4clang/test/CodeGenHLSL/builtins/QuadReadAcrossX.hlsl
+97-38150 files not shown
+336-266156 files

LLVM/project be1b1a7llvm/lib/LineEditor LineEditor.cpp

Turn signal handling on in LineEditor (#203616)

This PR was created to address
https://github.com/jank-lang/jank/issues/801.

Without signal handling, `CLRL+C` / `CTRL+Z` leaves the terminal in an
awkward state, breaking other command line tasks and forcing the user to
open a new/clean terminal window.

cc: @jeaye 

### Edit

#### AI

Per the contribution policies and review practices, AI was used to
locate the root cause of the issue I was seeing. From there, I
personally wrote the code and manually tested the build to verify that
the change fixed the problem I was seeing.

    [6 lines not shown]
DeltaFile
+1-0llvm/lib/LineEditor/LineEditor.cpp
+1-01 files

LLVM/project 2732991llvm/lib/Target/AMDGPU AMDGPU.td

[AMDGPU] Limit unclaused VMEM w/a to specific targets (#209843)

Fixes: LCOMPILER-2448
DeltaFile
+9-4llvm/lib/Target/AMDGPU/AMDGPU.td
+9-41 files

LLVM/project c4c4f20libc/src/__support freelist.cpp

[libc][baremetal][NFC] cache away redundant freelist memory access during push and pop (#208282)

By explicitly caching Node *next = node->next; and Node *prev =
node->prev; at function entry:
#### Before (Original):
```llvm                                                                                                                                                                                                             
    13:                                               ; preds = %6                                                                                                                                               
      %14 = load ptr, ptr %1, align 8                 ; Load node->prev                                                                                                                                          
      %15 = getelementptr inbounds nuw i8, ptr %14, i64 8                                                                                                                                                        
      store ptr %8, ptr %15, align 8                  ; Store next to prev->next                                                                                                                                 
      %16 = load ptr, ptr %7, align 8                 ; <--- REDUNDANT LOAD of node->next                                                                                                                        
      store ptr %14, ptr %16, align 8                 ; Store prev to next->prev                                                                                                                                 
      %17 = icmp eq ptr %3, %1                                                                                                                                                                                   
      br i1 %17, label %18, label %20                                                                                                                                                                            
  
    18:                                               ; preds = %13, %10
      %19 = phi ptr [ null, %10 ], [ %16, %13 ]
      store ptr %19, ptr %0, align 8
```

    [27 lines not shown]
DeltaFile
+6-4libc/src/__support/freelist.cpp
+6-41 files

LLVM/project 09a947elldb/packages/Python/lldbsuite/test lldbutil.py lldbtest.py, lldb/test/API/driver/longpath TestLongPathDriver.py

[lldb][Windows] Use extended path prefix for rmtree (#209409)

The test suite previously only warned when a test build directory or
artifact path exceeded Windows' `MAX_PATH (260)` limit, and
`shutil.rmtree` could fail to clean up such directories. This replaces
the warnings with actual long-path support.

This is a recurring problem in Swiftlang.
DeltaFile
+108-0lldb/packages/Python/lldbsuite/test/lldbutil.py
+4-33lldb/packages/Python/lldbsuite/test/lldbtest.py
+0-7lldb/test/Shell/helper/toolchain.py
+2-1lldb/test/API/tools/lldb-dap/longpath/TestDAP_launch_longPath.py
+2-1lldb/test/API/driver/longpath/TestLongPathDriver.py
+1-1lldb/test/API/functionalities/longpath/TestLongPath.py
+117-436 files

LLVM/project 378629bflang/lib/Optimizer/CodeGen TargetRewrite.cpp

[flang] Derive target-specific data layout from triple in TargetRewrite (#209649)

When target-rewrite runs without an explicit llvm.data_layout attribute,
it falls back to hardcoded generic default in MLIR (kDefaultDataLayout)
which specifies f128 ABI alignment as 16 bytes. This is incorrect for
targets where f128 ABI alignment differs from its size, such as SystemZ
which requires 8 bytes per the ELF ABI.

The target triple is available in the target-rewrite pass. Fix by
deriving the data layout from the target triple using
triple.computeDataLayout() before falling back to the generic default,
ensuring target-specific alignments are correctly reflected in
dlti.dl_spec.

@uweigand @dominik-steenken

---------

Co-authored-by: anoop.kumar6 at ibm.com <anoopk at b35lp63.lnxne.boe>
DeltaFile
+11-0flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
+11-01 files

LLVM/project ea61254polly/lib/CodeGen IslNodeBuilder.cpp BlockGenerators.cpp, polly/test/CodeGen issue205732.ll

[Polly] Fix codegen assertions to account for DefinedBehaviorContext (#209188)

DeLICM may produce new read access relations whose domain is restricted
to the DefinedBehaviorContext (e.g., only valid when a parameter ensures
no UB). The validation in setNewAccessRelation already accounts for
this, but the debug assertions in createNewAccesses and
generateScalarLoads did not, causing false assertion failures during
code generation.

Intersect the checked domains with getBestKnownDefinedBehaviorContext()
to match the contract that DeLICM relies on.

Fixes #205732
DeltaFile
+40-0polly/test/CodeGen/issue205732.ll
+10-2polly/lib/CodeGen/IslNodeBuilder.cpp
+5-0polly/lib/CodeGen/BlockGenerators.cpp
+55-23 files

LLVM/project ce6af70clang/lib/Sema SemaDecl.cpp, clang/test/SemaTemplate class-template-spec.cpp

Create a Template member to be the MemberSpec of a failed TemplVarDecl (#209604)

Patch #200092 changed to no longer check the previous var template when
setting whether the current one is a member specialization. However, if
the previous one was actually an error case (see the example here and in
the report), we ended up trying to do that anyway, which caused an
assertion.

This patch puts in a 'fake' declaration for the not-found declaration after we
emit the 'not found' error for the purposes of allowing our diagnostics to
continue evaluating these without causing problems.

Fixes: #209432
(cherry picked from commit 2c2e43675910603bab1b163655786e4850569d74)
DeltaFile
+21-0clang/test/SemaTemplate/class-template-spec.cpp
+15-0clang/lib/Sema/SemaDecl.cpp
+36-02 files

LLVM/project b8ba3c2mlir/include/mlir/Conversion Passes.td Passes.h, mlir/include/mlir/Conversion/SCFToAffine SCFToAffine.h

[mlir][SCFToAffine] Raise scf.for to affine.for (#200851)

Add a pass `-raise-scf-to-affine` that rewrites `scf.for` into
`affine.for` when the bounds and step are valid affine quantities. It
handles constant and dynamic steps, and integer-typed loops (by a
lossless cast of the bounds to `index`).

This is a first step; raising further scf ops to affine will follow.

Assisted-by: Claude Code (Anthropic)
Co-authored-by: Ming Yan <nexming7 at gmail.com>
Co-authored-by: Julian Farnsteiner <jcf96 at proton.me>
DeltaFile
+368-0mlir/lib/Conversion/SCFToAffine/SCFToAffine.cpp
+330-0mlir/test/Conversion/SCFToAffine/scf-to-affine.mlir
+37-0mlir/include/mlir/Conversion/Passes.td
+26-0mlir/include/mlir/Conversion/SCFToAffine/SCFToAffine.h
+15-0mlir/lib/Conversion/SCFToAffine/CMakeLists.txt
+1-0mlir/include/mlir/Conversion/Passes.h
+777-01 files not shown
+778-07 files

LLVM/project fc48c7ellvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV strided-accesses.ll strided-accesses-unroll.ll

[VPlan] Fix nowrap flags for strided access pointers from SCEV (#209453)

This patch addresses two things. First, the offset calculation
(canonical IV * stride) should not reuse the NSW flag of the add
recurrence. The NSW property from SCEV for the original scalar
recurrence does not necessarily hold for the reconstructed
multiplication using the vector canonical IV. The NUW flag, however, can
still be safely propagated.
Second, because vputils::getGEPFlagsForPtr currently doesn't support
recipes other than VPInstruction, and to avoid relying on LLVM IR
function (like calling stripPointerCasts()), we change
VPVectorPointerRecipe's GEP flags to use the add recurrence's flags to
prevent propagating unprovable GEP flags like inbounds.

(cherry picked from commit 1d4148821bf96bef23ea77952031e3e7bec26d3a)
DeltaFile
+7-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+5-5llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+1-3llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-unroll.ll
+13-153 files

LLVM/project ed33424clang/test/Driver/print-enabled-extensions aarch64-cortex-a320.c, llvm/lib/Target/AArch64 AArch64Processors.td AArch64Features.td

[AArch64] Remove HCX feature flag from backend (#209477)

This patch removes +hcx option from the llvm and removes guarding of
HCRX_EL2 system register on it.

(cherry picked from commit f48200029bf6277d4fe3915b480a5c87c8f172c9)
DeltaFile
+4-6llvm/lib/Target/AArch64/AArch64Processors.td
+1-6llvm/test/MC/AArch64/armv8.7a-hcx.s
+1-5llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt
+1-4llvm/lib/Target/AArch64/AArch64Features.td
+1-3llvm/lib/Target/AArch64/AArch64SystemOperands.td
+0-2clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c
+8-2632 files not shown
+8-5838 files

LLVM/project a431e97llvm/lib/Target/X86 X86LowerTileCopy.cpp, llvm/test/CodeGen/X86/AMX pr209512.ll

[X86] Skip debug instructions in tile copy lowering (#209640)

X86LowerTileCopy iterates over instructions in reverse to track live
registers, calling LiveRegUnits::stepBackward on every instruction
unconditionally. Since commit 16b2ef32 added an assertion that
stepBackward must not receive debug instructions, functions containing
debug info hit the assertion during tile copy lowering.
This patch skips debug instructions early in the loop, matching the
guard pattern used in RegisterScavenging.cpp and X86FixupBWInsts.cpp.

Fixes #209512

(cherry picked from commit 3e4160fdc3d5bb0ed86480604bdfcd3130e7dd37)
DeltaFile
+28-0llvm/test/CodeGen/X86/AMX/pr209512.ll
+2-0llvm/lib/Target/X86/X86LowerTileCopy.cpp
+30-02 files

LLVM/project 8cc33c0clang/test/CodeGen memcmp-inline-builtin-to-asm.c memcpy-inline-builtin.c

[Clang] Require x86 target for some tests (#209532)

These tests assert behavior about the always-inliner which now requires
a target to be present to check function attribute compatibility for
inlining.

Fix forward for 37b8e765ce4837a7577e6f762bcdffe4b232759c.

(cherry picked from commit 97f76580cdb0893d0b4edc7adf703162a23c0a67)
DeltaFile
+2-0clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
+2-0clang/test/CodeGen/memcpy-inline-builtin.c
+2-0clang/test/CodeGen/pr9614.c
+6-03 files

LLVM/project 5979f7cclang/lib/CIR/CodeGen CIRGenBuiltin.cpp, clang/test/CIR/CodeGenBuiltins builtins-elementwise.c

[CIR][NFC] Update stale elementwise handler (#207530)

A follow up of https://github.com/llvm/llvm-project/pull/204974
Clean up stale code of https://github.com/llvm/llvm-project/pull/169424
Add two missing CIR elementwise tests
Add three missing elementwise builtins as NYI
Assisted-by: Codex
DeltaFile
+16-61clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+44-0clang/test/CIR/CodeGenBuiltins/builtins-elementwise.c
+60-612 files

LLVM/project da003dfclang/test/Driver amdgpu-xnack-sramecc-flags.c, llvm/lib/Target/AMDGPU AMDGPUAsmPrinter.cpp

AMDGPU: Use module flags to control xnack and sramecc

This ensures these ABI details are encoded in the IR module
rather than depending on external state from command-line flags.
Previously, these were encoded as function-level subtarget features.
The code object output was a single target ID directive implied
by the global subtarget. The backend would previously check if a
function's subtarget feature mismatched the global subtarget. This
is avoided by making xnack and sramecc module-level properties from
the start. This also provides proper linker compatibility
enforcement, moving the error point earlier.

The old encoding was also an abuse of the subtarget feature system.
Subtarget features are a bitvector, and later features in the string
can override earlier ones. The old handling added a special case
where explicit settings were preserved: ordinarily +feature,-feature
should result in the feature being disabled, but +xnack,-xnack would
preserve the explicit "-xnack" state, which differs from the absence
of any xnack setting.

    [25 lines not shown]
DeltaFile
+52-52llvm/test/CodeGen/AMDGPU/directive-amdgcn-target-legacy-triples.ll
+30-46llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+75-0llvm/test/CodeGen/AMDGPU/module-flag-xnack.ll
+36-33clang/test/Driver/amdgpu-xnack-sramecc-flags.c
+66-0llvm/test/CodeGen/AMDGPU/module-flag-sramecc.ll
+54-0llvm/test/CodeGen/AMDGPU/module-flag-xnack-no-on-off-modes.ll
+313-13193 files not shown
+1,154-36299 files

LLVM/project 3a10c3aclang/include/clang/Frontend SSAFOptions.h, clang/include/clang/Options Options.td

[clang][SSAF] Optionally skip system-header contributors (#205446)

A new —ssaf-no-extract-from-system-headers switch that gates the
contributor finder so contributors located inside system headers are
dropped from the per-TU summary.
rdar://179151040

---------

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
DeltaFile
+66-0clang/unittests/ScalableStaticAnalysis/Analyses/PointerFlow/PointerFlowTest.cpp
+42-0clang/test/Analysis/Scalable/PointerFlow/system-header-opt-out.cpp
+26-8clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.cpp
+7-0clang/include/clang/Frontend/SSAFOptions.h
+7-0clang/include/clang/Options/Options.td
+5-2clang/lib/ScalableStaticAnalysis/Analyses/SSAFAnalysesCommon.h
+153-104 files not shown
+158-1010 files

LLVM/project 4758a7fllvm/test/DebugInfo/AMDGPU dwarfdump-relocs.ll pointer-address-space.ll

AMDGPU: Migrate DebugInfo tests to new subarch triples (58)

Mostly mechanical by script

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+2-2llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
+2-2llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
+2-2llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
+2-2llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll
+2-2llvm/test/DebugInfo/AMDGPU/variable-locations.ll
+1-1llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-cfi-directives.s
+11-115 files not shown
+16-1611 files

LLVM/project fc2126ellvm/test/CodeGen/MIR/AMDGPU s_waitcnt-errors.mir s_wait_loadcnt_dscnt-errors.mir

AMDGPU: Migrate MIR parser tests to new subarch triples (59)

Mechanical migration by script.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+16-16llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt-errors.mir
+12-12llvm/test/CodeGen/MIR/AMDGPU/s_wait_loadcnt_dscnt-errors.mir
+8-8llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_soft.mir
+8-8llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt.mir
+6-6llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu-errors.mir
+3-3llvm/test/CodeGen/MIR/AMDGPU/instr-mmra-error.mir
+53-5328 files not shown
+86-8634 files

LLVM/project 5587d53llvm/test/CodeGen/AMDGPU promote-constOffset-to-imm.ll call-encoding.ll

AMDGPU: Migrate more tests to using subarch triple commands (57)

Mostly mechanical updates with some light cleanups manually
applied.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+6-6llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
+5-5llvm/test/CodeGen/AMDGPU/call-encoding.ll
+4-4llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
+3-3llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
+2-2llvm/test/CodeGen/AMDGPU/inline-calls.ll
+2-2llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
+22-2219 files not shown
+41-4125 files

LLVM/project 79624adllvm/test/CodeGen/AMDGPU ran-out-of-registers-errors.ll machine-sink-temporal-divergence-swdev407790.ll

AMDGPU: Migrate uniform target-cpu attribute tests to subarch triple (55)

For tests that set the subtarget via a single uniform "target-cpu" IR function attribute, fold the cpu into the amdgpu subarch triple on the RUN lines, drop the redundant -mcpu, and remove the "target-cpu" attribute (deleting now-empty attribute groups and their references). The subtarget is unchanged, so codegen output is preserved.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+9-10llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
+4-4llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
+3-3llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
+2-3llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
+2-2llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
+2-2llvm/test/CodeGen/AMDGPU/debug-value.ll
+22-245 files not shown
+32-3411 files

LLVM/project 3bc3315llvm/test/CodeGen/AMDGPU amdgpu-attributor-min-agpr-alloc.ll attributor-flatscratchinit.ll

AMDGPU: Fold -mcpu into subarch triple for attributor tests (56)

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+97-100llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll
+24-34llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
+19-24llvm/test/CodeGen/AMDGPU/propagate-amdgpu-cluster-dims.ll
+7-10llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
+8-8llvm/test/CodeGen/AMDGPU/amdgpu-attributor-nocallback-intrinsics.ll
+6-6llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
+161-1825 files not shown
+178-20111 files

LLVM/project e41d57allvm/test/Transforms/AtomicExpand/AMDGPU expand-atomic-f32-agent.ll expand-atomic-f32-system.ll

AMDGPU: Migrate tests with regenerated checks to amdgpu subarch triple (54)

Fold the explicit -mcpu subtarget into the amdgpu subarch triple on autogenerated tests where the folded triple changes output relative to the previous default subtarget (e.g. cost-model BASE lines, scheduling). CHECK lines were regenerated with the update_*_test_checks.py scripts.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
DeltaFile
+803-803llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-agent.ll
+284-284llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f32-system.ll
+244-244llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-agent.ll
+202-202llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-f64-system.ll
+194-194llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
+149-141llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-flat-noalias-addrspace.ll
+1,876-1,86865 files not shown
+3,800-3,82171 files

LLVM/project 693ded3llvm/runtimes CMakeLists.txt

[LLVM] Fix not passing CMAKE_CROSSCOMPILING_EMULATOR for amdgpu (#209828)

Summary:
This only matches on amdgcn, just add amdgpu
DeltaFile
+1-1llvm/runtimes/CMakeLists.txt
+1-11 files

LLVM/project d3d8264clang/include/clang/Basic TargetID.h, clang/lib/Basic TargetID.cpp

clang: Use TargetID parsing from AMDGPUTargetParser

We had grown 2 parallel parsing implementations for
triple+gpu name+feature flag target ID strings. Mostly
eliminate the redundant clang version.

Co-authored-by: Claude (Opus 4.8)
DeltaFile
+29-165clang/lib/Basic/TargetID.cpp
+49-51clang/lib/Driver/ToolChains/AMDGPU.cpp
+27-41clang/lib/Driver/OffloadBundler.cpp
+7-33clang/include/clang/Basic/TargetID.h
+18-14clang/lib/Basic/Targets/AMDGPU.h
+17-14clang/lib/Basic/Targets/AMDGPU.cpp
+147-3185 files not shown
+172-34211 files

LLVM/project e6782a9llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: Add TargetID::printCanonicalTargetIDString

Factor the canonical feature-string formatting into a raw_ostream print
method so callers can stream directly without a temporary std::string.
getCanonicalFeatureString now delegates to it.
DeltaFile
+6-2llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+5-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+11-22 files

LLVM/project 11725b1clang/include/clang/Basic TargetID.h, clang/lib/Basic TargetID.cpp

Fix offload bundler usage of getConflictTargetIDCombination
DeltaFile
+14-9clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
+11-9clang/include/clang/Basic/TargetID.h
+12-2clang/lib/Driver/OffloadBundler.cpp
+9-4clang/lib/Driver/Driver.cpp
+2-3clang/lib/Basic/TargetID.cpp
+48-275 files

LLVM/project 4a72f64llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

comment
DeltaFile
+2-1llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+2-11 files

LLVM/project dcb7fe4llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: Remove now-unused splitTargetID

splitTargetID was a syntactic-only target-ID splitter used solely by
clang's getConflictTargetIDCombination, which now parses through the
canonical llvm::AMDGPU::TargetID::parse instead. With that last user
gone, drop the function, its declaration, and its unit test.
DeltaFile
+0-40llvm/unittests/TargetParser/TargetParserTest.cpp
+0-20llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+0-6llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+0-663 files