[CodeGen] Always emit CodeView compiler info for UEFI targets (#188383)
UEFI is based on the MSVC toolchain conventions. PR #142970 made Windows
targets always emit minimal CodeView compiler information (`S_OBJNAME`
and `S_COMPILE3`) even when debug info is otherwise disabled, matching
MSVC. Make UEFI targets behave the same way.
[llvm] Adjust LLVM_ABI annotations for ELF/Mach-O (#232393)
Some annotations were not at the right level (class or method) for some
use cases. These ensure that the dylib build with default visibility set
to hidden properly works for macOS and Linux with tests.
The effort to build LLVM as a dylib is tracked in #109483.
Attributor: Reach fixpoint in AACallEdges if there are only direct calls
The callees when there are only direct, live calls will not change.
No other attributes matter, but this ran the update a second time to
find out.
Instructions spent in amdgpu-attributor:
rocPRIM test_device_scan, gfx942: 1265M -> 1263M (-0.2%)
Blender Cycles HIP kernel, gfx1100: 488M -> 487M (-0.2%)
rocPRIM 16 tests, full LTO, closed world: 4381M -> 4359M (-0.5%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Attributor: Don't create call site AACallEdges for direct calls
AACallEdgesFunction created an AACallEdges for every call-like
instruction in the function including intrinsics. For a direct call
without callback metadata, the call site attribute only ever adds the
callee, so add it directly.
Instructions spent in amdgpu-attributor:
rocPRIM test_device_scan, gfx942: 1963M -> 1768M (-9.9%)
Blender Cycles HIP kernel, gfx1100: 636M -> 622M (-2.2%)
rocPRIM 16 tests, full LTO, closed world: 7415M -> 6511M (-12.2%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Share the xforms for FP immediate bits (#232492)
AArch64 and AMDGPU defined identical bitcast_fpimm_to_iN xforms, and
Hexagon defined an equivalent ftoi. Define them once in
TargetSelectionDAG.td.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[libc] Add <libintl.h> and textdomain stub (#232351)
POSIX.1-2024 standardises the <libintl.h> message translation
interfaces. Because LLVM-libc currently supports only the "C" locale,
message catalog functions can be satisfied with stateless stubs that do
not access the filesystem.
Added the <libintl.h> header generation specification and the textdomain
entrypoint behind LLVM_LIBC_ENABLE_EXPERIMENTAL_ENTRYPOINTS, returning
"messages" when querying or resetting the domain and returning the input
domain name otherwise.
Assisted-by: Automated tooling, human reviewed.
[RISCV][P-ext] Add scalar mulq(r) intrinsics (#232316)
Add the scalar "Q-format" Multiplication intrinsics:
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#q-format-multiplication
- `__riscv_mulq_i32`
- `__riscv_mulqr_i32`
RV32 selects `mulq`/`mulqr` directly. RV64 has no scalar forms, so the
intrinsics use `pmulq.w`/`pmulqr.w` on the low words, the same way as
the scalar `aadd`/`asub` intrinsics (#230710).
[libc] Use a syscall wrapper for `sched_getscheduler` (#232597)
This PR move `sched_getscheduler` behind the centralized syscall
wrappers, following `libc/docs/dev/syscall_wrapper_refactor.md`.
[flang] Fail fir.global conversion when the type has no LLVM equivalent
GlobalOpConversion passed the result of convertType straight to
LLVM::GlobalOp::create. For a global whose type the FIR type converter
cannot lower, such as tensor<10xi32>, that result is null and
TypeAttr::get segfaults. Return a match failure instead so the
conversion reports that fir.global could not be legalized.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
[clang-repl] Add OffloadType enum and HIP device parser skeleton (#231391)
This PR adds an OffloadType enum (Detect, CUDA, HIP) and
Interpreter::createWithDevice(), so device setup can be chosen in one
place. createWithCUDA() now forwards to it, so CUDA behaviour and
existing callers are unchanged. Detect and the HIP binary generation
return "unsupported" errors for now.
It also adds the IncrementalHIPDeviceParser class. Its constructor
checks that the device target triple is an AMDGPU one.
GenerateOffloadBinary() is a stub that will be implemented later.
Assisted by Claude Sonnet 5.5
Revert "[SLP][NFC]Add extra bitpack tests, NFC" (#232593)
Reverts llvm/llvm-project#232554
Reverting as the patch broke the CI builders across the board. I see the
original owner is not available to address the failure so reverting to
turn ToT green.
[OpenMP] Preserve host capture lifetimes in frontend lowering
Mark captured alloca/global storage nofreeobj when Clang emits a synchronous
host parallel call. This preserves lifetime across outlining without claiming
that escaped capture slots are noalias or immutable, and without extending the
lifetime guarantee to pointers loaded from those slots.
Mark OpenMPIRBuilder's fresh host capture aggregate noalias and nofreeobj.
This covers the lowering path used by Flang and Clang's IRBuilder mode.
Replace callback Attributor seeding with frontend and translation tests,
including escaped captures, heap references, firstprivate pointers, debug
wrappers, serialized regions, and optimized load hoisting with OpenMPOpt
disabled. Refresh the affected parameter-attribute checks.
[CodeGen] Address review: error for "=m|r" direct outputs too
A direct output whose chosen alternative is memory, e.g. "=m|r", still
crashed SelectionDAG, which exempted multiple-alternative operands from the
check and then asked for the address of an output with no value. Drop the
exemption and test "=m|r" with both instruction selectors. Name the
selector explicitly in the RUN lines rather than relying on -O levels,
since X86 GlobalISel can't lower inline asm and both X86 lines ran
SelectionDAG anyway. Drop "yet" from the error: Clang never emits a
direct memory output, so there are no plans to support one.
Assisted-by: Claude Opus 5.5
[CodeGen] Report an error for a direct inline asm output in memory
An inline asm output returned by value has no memory to write to, yet a
constraint such as "=rm" picks memory, the most general constraint, as
does "=m". SelectionDAG asserted on that ("Can only indirectify direct
input operands!"), and GlobalISel dereferenced a null pointer. Clang
never emits such an output, since it passes the address of a memory
output, but other IR can. Report "cannot handle direct memory outputs
yet for constraint 'm'" instead, like the other inline asm errors there.
Assisted-by: Claude Opus 5.5
[TargetInstrInfo] Address review: autogenerate greedy-inline-asm-fold.mir checks
Generate the checks with update_mir_test_checks.py so that the spills and
reloads around each folded inline asm are verified, not just the INLINEASM
itself. Fix the "=r" comment to describe the C "+r" operand, note that which
"+rm" pair greedy folds is its own choice, and add a "+&rm" case on an
uninitialized value showing that folding a pair whose tied use is undef
stores to the slot without loading from it.
Assisted-by: Claude Opus 5.5
[TargetInstrInfo] Fix folding inline asm operands next to tied operands
foldInlineAsmMemOperand() swapped a register operand for the target's
memory operands with MachineInstr::removeOperand(), which asserts when a
later operand is tied, because moving it would break the tie. Inline asm
lists every input after every output, so folding any operand that comes
before another tied pair asserted, e.g. an "rm" input followed by the
input of a "+r" operand, or one of two "+rm" operands. Without
assertions, the moved operands kept stale tie indices. Untie the
operands, rebuild the operand list, and re-tie the remaining pairs at
their new positions.
It also gave up when the register appears in more than one operand, e.g.
one value passed to two "rm" operands, which left the greedy allocator
unable to spill that value at all. Fold every such operand into the
stack slot.
Finally, take MayLoad from the folded operands rather than from every
read of the register: a folded def whose tied use is another virtual
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[flang-rt][cuda] Remove deprecated usage of cudaGetDriverEntryPoint (#232485)
deviceContextTornDown() resolves cuDevicePrimaryCtxGetState through
cudaGetDriverEntryPointByVersion, using the installed driver version,
and fell back to the unversioned cudaGetDriverEntryPoint when that
failed. The unversioned entry point is deprecated since CUDA 12.5 and
triggers -Wdeprecated-declarations.
The fallback adds nothing: the ByVersion call is already required to
build, and the unversioned lookup uses the runtime version, which is
the case that fails when the runtime is newer than the driver. If the
versioned lookup fails, leave the function pointer null, which already
takes the conservative "cannot prove torn down" path.
[flang] Fix NOTIFY= placement checking and folding (#231660)
F2023 C933 permits NOTIFY= only in the image selector of an intrinsic
assignment's target variable. Before this patch, semantic analysis
accepted it in other contexts.
Assignment checking reuses the analyzed assignment's classification as
intrinsic or defined. For intrinsic assignment, an existing parse-tree
helper identifies the target variable's own image selector. The new
check permits a NOTIFY= specifier only if its parse-tree node belongs to
that selector's specifier list. It rejects NOTIFY= on separate
designators nested within the target variable.
If an operand error prevents assignment analysis, the checker avoids an
extra placement diagnostic on the target's own selector. Existing
duplicate-specifier diagnostics remain unchanged.
Before this patch, FoldOperation(CoarrayRef) dropped NOTIFY= from the
rebuilt reference. The change retains and folds the notification
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[flang][NFC] Expose force-no-alias option via CommandLineOpts (#232568)
Move the force-no-alias cl::opt from a file-local static in
Pipelines.cpp
to CommandLineOpts.cpp and declare it extern in CommandLineOpts.h, so
other pipelines built on top of flang can honor the same setting without
re-registering the option.
[mlir][Diagnostics] Set parallel diagnostic order ids without a lock (#232520)
failableParallelForEach tells its ParallelDiagnosticHandler which
element each thread is processing before every element and clears it
after, so diagnostics come out in element order.
The order id now lives in a thread-local slot naming its handler by a
monotonic id (no raw pointers, so a handler destroyed with a stale slot
naming it is harmless). A thread handles one element at a time per
handler, so the slot covers every thread whose loop is not nested in
another loop on the same thread.
200K single-op func.func through per-function cse, 96 threads: sys time
22.9s to 3.8s, wall 3.4s to 3.2s. Unittest pins the nested fallback and
outer-id preservation.
[BOLT] Expand builtin_unreachable recognition heuristics (#231258)
A jump to the address right past the end of a function (the result of
__builtin_unreachable()) was replaced with a nop only when the target
was within the function's padding (MaxSize). However, there is a corner
case for the very last function in a section: MaxSize equals Size, so
BOLT would see __builtin_unreachable() instead as as an interprocedural
reference to an address outside of any section, tripping the "cannot get
section for referenced address" assertion in
processInterproceduralReferences(). Fix this.
[X86] Address review: test a tied input's untied read under -regalloc=fast
Add the case from the #229630 review, one value passed to an untied "r"
input and to the "0" input tied to an "rm" output, to show that the fast
register allocator no longer folds the output when everything fits.
Drop the -O0 RUN line from inline-asm-direct-mem-output-error.ll: it only
showed that "=rm" still picks memory at -O0, which asm-constraints-rm.ll
already tests, and there make the -O0 line name the instruction selector
and say that it tests the optimization level.
Assisted-by: Claude Opus 5.5
[TargetLowering][X86] Prefer 'r' over 'm' for foldable "rm" inline asm operands
An "rm" (register-or-memory) inline asm operand has always resolved to
'm', because getConstraintPreferences() picks the most general
constraint present, and 'm' is more general than 'r'. That's safe, since
memory can't run out, but it forces a value that could stay in a
register through a stack slot even when there's no register pressure
(https://github.com/llvm/llvm-project/issues/20571).
Prefer 'r' instead where the register allocator can fold the register
back to a stack slot when it runs out of registers, and mark the
register operand foldable (InlineAsm::Flag::setRegMayBeFolded()) so it
does. Both allocators can: the greedy allocator folds an operand when it
spills its value, and the fast allocator folds operands up front when
the asm's register operands wouldn't fit.
ParseConstraints() sets AsmOperandInfo::MayFoldRegister for an operand
whose constraint codes include 'r' and 'm' and are otherwise only
immediate codes, above -O0, on a target that opts in through the new
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