LLVM/project 388fe68llvm/lib/Target/RISCV RISCVInstrInfo.td, llvm/test/CodeGen/RISCV tlsdesc-clobber.ll

[RISCV] Add explicit defs in PseudoLA_TLSDESC (#205494)

(Separated from #205027, per this discussion thread:
https://github.com/llvm/llvm-project/pull/205027#discussion_r3464170432
and
https://github.com/llvm/llvm-project/pull/205027#issuecomment-4785382877)

Per the psABI, la.tlsdesc clobbers a0/t0. The defs are not strictly
required now because the expanding happens pre-RA, while just in case
some passes may need it or the expanding may be moved to post-RA in the
future.

Also, a test case is added as well showing the right behavior of TLSDESC
clobbering.
DeltaFile
+53-0llvm/test/CodeGen/RISCV/tlsdesc-clobber.ll
+3-1llvm/lib/Target/RISCV/RISCVInstrInfo.td
+56-12 files

LLVM/project df9bcebllvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/lib/Target/AMDGPU AMDGPU.td AMDGPUTargetTransformInfo.cpp

[TTI][Inline] Define inlining behavior in SubtargetFeature (#205348)

This allows specifying the InliningBehavior as part of SubtargetFeature.
The behavior is one of InlineDefault, InlineInverse, and InlineIgnore.

* InlineDefault: A callee with this feature enabled cannot be inlined
into a caller without it enabled.
* InlineInverse: A callee without this feature enabled cannot be inlined
into a caller with it enabled.
 * InlineIgnore: Arbitrary differences are allowed.

The default areInlineCompatible() implementation respects these now.

The intention behind this change is that it reduces the risk of
forgetting to update feature lists in TTI when adding a new feature,
e.g. when adding a new tuning flag that should be InlineIgnore.

Move X86 and AMDGPU ignored features, and the one inverse feature on
AArch64 to TableGen.

    [2 lines not shown]
DeltaFile
+136-70llvm/lib/Target/X86/X86.td
+0-76llvm/lib/Target/X86/X86TargetTransformInfo.h
+32-17llvm/lib/Target/AMDGPU/AMDGPU.td
+1-26llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+26-0llvm/utils/TableGen/SubtargetEmitter.cpp
+1-17llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+196-2068 files not shown
+258-21614 files

LLVM/project ce56a6allvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange transform-stop-partway.ll pr57148.ll

[LoopInterchange] Prevent the transformation stage from stopping partway
DeltaFile
+19-36llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+17-18llvm/test/Transforms/LoopInterchange/transform-stop-partway.ll
+18-14llvm/test/Transforms/LoopInterchange/pr57148.ll
+12-14llvm/test/Transforms/LoopInterchange/pr43326-ideal-access-pattern.ll
+11-13llvm/test/Transforms/LoopInterchange/interchanged-loop-nest-3.ll
+11-9llvm/test/Transforms/LoopInterchange/guarded-inner-loop.ll
+88-1043 files not shown
+102-1129 files

LLVM/project 3887ae1clang-tools-extra/clang-tidy/utils RenamerClangTidyCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Guard `readability-identifier-naming` recursion in dependent base lookup (#204913)

Prevent `readability-identifier-naming` from recursing indefinitely in
dependent base lookup when AggressiveDependentMemberLookup` is enabled.

In #204790, `findDeclInBases()` maps a dependent template base back to
the primary template, creating a recursive cycle that crashes
clang-tidy. Add a recursion guard to stop the crash. A more complete fix
could be explored separately.

Add a regression test covering the dependent base cycle reproducer.

Closes https://github.com/llvm/llvm-project/issues/204790.

---------

Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
DeltaFile
+16-4clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
+15-0clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-member-decl-usage.cpp
+3-0clang-tools-extra/docs/ReleaseNotes.rst
+34-43 files

LLVM/project ea05555libcxx/include/__locale_dir/support fuchsia.h llvm_libc.h, libcxx/test/libcxx/text/text_encoding environment.pass.cpp

[libc++] Add implementations of `__get_locale_encoding(...)` to Fuschia and LLVM-Libc (#205716)

- These were missed in #141312 and consequently broke the Fuschia and
AMDGPU llvm-libc build bots.
- Fuschia seems to have support for `nl_langinfo_l(...)`, so we can use
that.
- However, LLVM-libc does not implement it, so for now we can do a dummy
implementation and mark `environment()` and `encoding()` as unsupported
on LLVM libc.
DeltaFile
+5-0libcxx/include/__locale_dir/support/fuchsia.h
+2-0libcxx/include/__locale_dir/support/llvm_libc.h
+1-0libcxx/test/std/text/text_encoding/text_encoding.members/environment.pass.cpp
+1-0libcxx/test/libcxx/text/text_encoding/environment.pass.cpp
+9-04 files

LLVM/project b95d720clang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp LiveOrigins.cpp

Reapply "[LifetimeSafety] Fix liveness propagation for all origin flows (#205323)" (#205687)

This reverts commit d4cf04ba17c833cfbab5a16aa2d21f7185a0c9ae.
DeltaFile
+72-0clang/test/Sema/LifetimeSafety/safety.cpp
+23-6clang/test/Sema/LifetimeSafety/invalidations.cpp
+21-0clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+14-3clang/lib/Analysis/LifetimeSafety/LiveOrigins.cpp
+1-0clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+131-95 files

LLVM/project 11682b5. lifetime_reproduce.cpp, clang/include/clang/Analysis/Analyses/LifetimeSafety Facts.h

fix-liveness
DeltaFile
+73-20clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+13-0clang/test/Sema/LifetimeSafety/safety.cpp
+8-0lifetime_reproduce.cpp
+5-0clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h
+99-204 files

LLVM/project c50b561clang/lib/Sema SemaAMDGPU.cpp

clang/AMDGPU: Simplify cpu name checks for __builtin_amdgcn_is_processor (#205724)

Instead of trying to figure out which TargetInfo to use, skip it and
directly use the source of truth from TargetParser. This avoids
regressions in future commits where isValidCPUName will be 
conditionally filtered.
DeltaFile
+4-8clang/lib/Sema/SemaAMDGPU.cpp
+4-81 files

LLVM/project f21cd4fllvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange transform-stop-partway.ll

[LoopInterchange] Add test for IR modification stops partway
DeltaFile
+88-0llvm/test/Transforms/LoopInterchange/transform-stop-partway.ll
+4-1llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+92-12 files

LLVM/project b8be950llvm/include/llvm/ADT iterator_range.h

[ADT][NFC] Use is_constructible instead of implementing it ourselves (#205341)
DeltaFile
+5-8llvm/include/llvm/ADT/iterator_range.h
+5-81 files

LLVM/project 60977b5llvm/include/llvm/TargetParser RISCVTargetParser.h, llvm/lib/Target/RISCV RISCVAsmPrinter.cpp

[RISCV][Zicfilp] Emit .note.gnu.property section for Zicfilp CFI unlabeled scheme (#141468)

RISC-V Zicfilp-based CFI needs to let the linker/loader know if the
binary is built with the mechanism enabled to support proper
link-time/load-time management of this feature. The information is
encoded as a bit in the `.note.gnu.property` section. This patch
implements emitting the section for RISC-V targets when Zicfilp-based
CFI with the "unlabeled" label scheme is enabled.

When Clang receives the `-fcf-protection=branch` flag, which enables
forward-edge CFI protection, it adds the `cf-protection-branch`
attribute to the LLVM module. Additionally, if a branch label scheme is
needed, another attribute (`cf-branch-label-scheme`) is added to
indicate it. For RISC-V targets, the `cf-protection-branch` attribute
indicates the adoption of Zicfilp-based forward-edge CFI protection, and
the `cf-branch-label-scheme` attribute selects how the "label" operands
of the Zicfilp `lpad` insns are produced. This patch emits the proper
`.note.gnu.property` feature bit when the RISC-V backend sees that the
LLVM module has the `cf-protection-branch` attribute set to `1`, and the

    [6 lines not shown]
DeltaFile
+31-2llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+26-0llvm/test/CodeGen/RISCV/note-gnu-property-zicfilp-unlabeled.ll
+18-0llvm/include/llvm/TargetParser/RISCVTargetParser.h
+14-0llvm/test/CodeGen/RISCV/note-gnu-property-zicfilp-error.ll
+5-4llvm/test/CodeGen/RISCV/tail-calls.ll
+2-1llvm/test/CodeGen/RISCV/rv64-trampoline-cfi.ll
+96-77 files not shown
+110-1413 files

LLVM/project 44546e0libcxx/include map __tree, libcxx/include/__memory unique_ptr.h

[libc++] Enable clang-tidy in the CI again (#195047)

clang-tidy currently doesn't run in the CI because CMake doesn't find
the appropriate `ClangConfig.cmake` anymore. This adds the path so
clang-tidy is built again and fixes most issues. Some things are
disabled for now to get most checks back. They will be re-enabled later.
DeltaFile
+6-6libcxx/include/map
+0-10libcxx/test/tools/clang_tidy_checks/hide_from_abi.cpp
+6-1libcxx/utils/ci/run-buildbot
+6-1libcxx/test/libcxx/clang_tidy.gen.py
+2-2libcxx/include/__memory/unique_ptr.h
+2-2libcxx/include/__tree
+22-2210 files not shown
+37-2916 files

LLVM/project e5f8e65clang/include/clang/Basic DiagnosticSemaKinds.td, clang/test/SemaHIP amdgpu-feature-predicates-guard-use.hip

clang: Fix referring to __builtin_amdgcn_is_processor in diagnostic (#205725)

The builtin name is really __builtin_amdgcn_processor_is.
DeltaFile
+2-2clang/test/SemaHIP/amdgpu-feature-predicates-guard-use.hip
+1-1clang/include/clang/Basic/DiagnosticSemaKinds.td
+3-32 files

LLVM/project 2290eefllvm/unittests/Target/AArch64 AArch64SVESchedPseudoTest.cpp

[AArch64] Correct latency calculation in runSVEPseudoTestForCPU test. NFC (#205100)

It does not look like this caused problems in the pseudo scheduling
tests, but is accumulating the wrong latency. I added extra checks that
the NumWriteLatencyEntries were the same in both cases whilst I was here
too.
DeltaFile
+9-2llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp
+9-21 files

LLVM/project 6fca2c7llvm/include/llvm/IR FPTransformChecker.h

Fix LLVM_ABI decorations
DeltaFile
+3-3llvm/include/llvm/IR/FPTransformChecker.h
+3-31 files

LLVM/project 0f09d4bclang/test/CodeGen amdgpu-feature-builtins-invalid-use.cpp, clang/test/SemaCXX amdgpu-feature-builtins-invalid-use.cpp

clang: Move __builtin_amdgcn_processor_is diagnostic test to sema

This wasn't checking the codegen result, so move it to the right place
and use -verify instead of FileChecking stderr.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+50-0clang/test/SemaCXX/amdgpu-feature-builtins-invalid-use.cpp
+0-48clang/test/CodeGen/amdgpu-feature-builtins-invalid-use.cpp
+50-482 files

LLVM/project d77731fllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Merge branch 'main' into users/spavloff/snan
DeltaFile
+31,001-87,165llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+15,519-26,130llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+12,134-24,576llvm/test/CodeGen/RISCV/clmul.ll
+16,791-15,581llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+8,309-12,701llvm/test/CodeGen/RISCV/clmulr.ll
+7,968-12,512llvm/test/CodeGen/RISCV/clmulh.ll
+91,722-178,66515,878 files not shown
+1,233,299-796,47215,884 files

LLVM/project a6e3bf8clang/lib/AST/ByteCode Interp.cpp InterpHelpers.h

[clang][bytecode] Pass AccessKinds to Check{Constant,Mutable} (#205720)

So we can pass them on do `diagnoseNonConstVariable`.

This doesn't make a difference right now but is needed for a future
commit.
DeltaFile
+11-9clang/lib/AST/ByteCode/Interp.cpp
+5-3clang/lib/AST/ByteCode/InterpHelpers.h
+2-1clang/lib/AST/ByteCode/Interp.h
+18-133 files

LLVM/project dd499f8clang/include/clang/Options Options.td, clang/lib/Driver/ToolChains Flang.cpp

[Flang][Driver]Add support for option '-fpseudo-probe-for-profiling' in flang (#205046)

Added support for option `-fpseudo-probe-for-profiling` in flang.

- When the option `-fpseudo-probe-for-profiling` is passed, the compiler
sets the` PseudoProbeForProfiling` flag and triggers the
`SampleProfileProbePass`. This pass inserts `llvm.pseudoprobe(..)`
intrinsic calls and `!llvm.pseudo_probe_desc` metadata into the IR.
DeltaFile
+33-0flang/test/Integration/pseudo-probe-for-profiling.f90
+15-7flang/lib/Frontend/FrontendActions.cpp
+15-0flang/test/Driver/fpseudo-probe-for-profiling.f90
+5-0clang/lib/Driver/ToolChains/Flang.cpp
+5-0flang/lib/Frontend/CompilerInvocation.cpp
+1-1clang/include/clang/Options/Options.td
+74-81 files not shown
+75-87 files

LLVM/project 101b2cdflang/lib/Semantics check-omp-structure.cpp, flang/test/Semantics/OpenMP declare-reduction-use-reexport-remerge.f90 declare-reduction-use-reexport-merged.f90

[flang][OpenMP] Fix declare reduction lookup for USE...ONLY imports

CheckSymbolSupportsType walked every module in the global scope to find
declare-reduction declarations. That accepted reductions from modules
that were never USE'd, or were excluded via USE...ONLY, and it still
rejected some valid imports such as a renamed operator.

Replace the global scan with FindUserReduction(), which resolves the
reduction the way name resolution resolves the operator. It checks a
directly visible reduction first, then follows the operator's USE
associations and merged-generic sources to the declaring modules,
re-deriving the source module's mangled name for renamed operators. The
search recurses through re-exporting (facade) modules and is type-aware,
so an operator that carries reductions for several types resolves to the
one supporting the requested type. A locally declared reduction is
authoritative and shadows reductions reachable through the operator.

Consolidate the duplicated GetReductionFortranId() (formerly static in
both resolve-names.cpp and mod-file.cpp) into a shared utility, fixing a

    [11 lines not shown]
DeltaFile
+131-30flang/lib/Semantics/check-omp-structure.cpp
+93-0flang/test/Semantics/OpenMP/declare-reduction-use-reexport-remerge.f90
+63-0flang/test/Semantics/OpenMP/declare-reduction-use-reexport-merged.f90
+61-0flang/test/Semantics/OpenMP/declare-reduction-use-mixed-merged.f90
+60-0flang/test/Semantics/OpenMP/declare-reduction-use-only-merged.f90
+59-0flang/test/Semantics/OpenMP/declare-reduction-use-shadow-merged.f90
+467-309 files not shown
+687-9015 files

LLVM/project f722c3fclang/include/clang/Basic DiagnosticSemaKinds.td, clang/test/SemaHIP amdgpu-feature-predicates-guard-use.hip

clang: Fix referring to __builtin_amdgcn_is_processor in diagnostic

The builtin name is really __builtin_amdgcn_processor_is.
DeltaFile
+2-2clang/test/SemaHIP/amdgpu-feature-predicates-guard-use.hip
+1-1clang/include/clang/Basic/DiagnosticSemaKinds.td
+3-32 files

LLVM/project 67349c5clang/lib/Sema SemaAMDGPU.cpp

clang/AMDGPU: Simplify cpu name checks for __builtin_amdgcn_is_processor

Instead of trying to figure out which TargetInfo to use, skip it and
directly use the source of truth from TargetParser. This avoids regressions
in future commits where isValidCPUName will be conditionally filtered.
DeltaFile
+4-8clang/lib/Sema/SemaAMDGPU.cpp
+4-81 files

LLVM/project 1ece64cclang/test/CodeGen/WebAssembly wasm-funcref-to-ptr-error.c

Fix test from #203165 when no wasm target is configured (#205722)

Fix test from #203165 when no wasm target is configured
DeltaFile
+1-0clang/test/CodeGen/WebAssembly/wasm-funcref-to-ptr-error.c
+1-01 files

LLVM/project 374df9fllvm/lib/Target/AArch64 AArch64SRLTDefineSuperRegs.cpp AArch64.h, llvm/test/CodeGen/AArch64 subreg-liveness-fix-subreg-to-reg-implicit-def.mir

[NewPM][AArch64] Port AArch64SRLTDefineSuperRegs pass to NewPassManager (#202803)

Standard port for the AArch64SRLTDefineSuperRegs pass.

Assisted by Gemini
DeltaFile
+38-17llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp
+9-2llvm/lib/Target/AArch64/AArch64.h
+2-2llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+1-0llvm/lib/Target/AArch64/AArch64PassRegistry.def
+1-0llvm/test/CodeGen/AArch64/subreg-liveness-fix-subreg-to-reg-implicit-def.mir
+51-215 files

LLVM/project 765f0d1clang/test/CodeGen/WebAssembly wasm-funcref.c, llvm/lib/Target/WebAssembly WebAssemblyLowerRefTypesIntPtrConv.cpp WebAssemblyFastISel.cpp

[WebAssembly] Represent reference types as TargetExtType (#203165)

Originally #71540 by Paolo Matos, I picked it up and finished it.
Resolves https://github.com/llvm/llvm-project/issues/69894.

Model WebAssembly externref and funcref as target("wasm.externref") /
target("wasm.funcref") TargetExtTypes instead of pointers in
non-integral address spaces 10 and 20.

The entire WebAssemblyLowerRefTypesIntPtrConv can be removed.

This breaks the GlobalISel handling for reference types, I just disabled
GlobalISel handling for functions that use them.

I added intrinsics for `wasm.ptr.to_funcref` and `wasm.funcref.to_ptr`.
ptr.to_funcref does a table.get from the indirect function pointer
table. As a special case, 0 is converted to the null funcref rather than
doing table.get on 0. `wasm.funcref.to_ptr` is only handled when we call
it immediately, otherwise it will fail to lower. We could dynamically

    [13 lines not shown]
DeltaFile
+0-85llvm/lib/Target/WebAssembly/WebAssemblyLowerRefTypesIntPtrConv.cpp
+50-21clang/test/CodeGen/WebAssembly/wasm-funcref.c
+59-11llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+67-0llvm/test/CodeGen/WebAssembly/ref-null-zeroinitializer.ll
+6-50llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/call-basics.ll
+32-21llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.cpp
+214-18858 files not shown
+679-40564 files

LLVM/project c0e80b9clang-tools-extra/test/clang-doc class-partial-specialization.cpp, clang-tools-extra/test/clang-doc/json class-partial-specialization.cpp nested-pointer-qualifiers.cpp

[clang-doc] Test more language constructs (#205585)

We're missing several different language constructs in our tests. This
patch simply adds the basic tests and captures the output without trying
to fix or adjust any behavior, and can be considered a sort of precommit
test for future fixes to the various documentation components.
DeltaFile
+25-0clang-tools-extra/test/clang-doc/json/class-partial-specialization.cpp
+18-0clang-tools-extra/test/clang-doc/json/nested-pointer-qualifiers.cpp
+18-0clang-tools-extra/test/clang-doc/json/member-function-pointer-type.cpp
+18-0clang-tools-extra/test/clang-doc/json/function-pointer-type.cpp
+18-0clang-tools-extra/test/clang-doc/json/array-type.cpp
+13-0clang-tools-extra/test/clang-doc/class-partial-specialization.cpp
+110-09 files not shown
+165-015 files

LLVM/project 2fe6548flang/lib/Semantics expression.cpp check-cuda.cpp, flang/test/Semantics cuf30.cuf

[flang][cuda] Add NYI message for CUDA dynamic parallelism (#205628)
DeltaFile
+19-0flang/test/Semantics/cuf30.cuf
+10-2flang/lib/Semantics/expression.cpp
+4-0flang/lib/Semantics/check-cuda.cpp
+33-23 files

LLVM/project 53fb849clang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode evaluate-dtor-codegen.cpp

[clang][bytecode] Ignore indeterminate APValues (#205555)

They don't produce a value and for us, that means we just need to ignore
them and not initialize anything.
DeltaFile
+14-0clang/test/AST/ByteCode/evaluate-dtor-codegen.cpp
+9-0clang/lib/AST/ByteCode/Compiler.cpp
+23-02 files

LLVM/project f9953d4flang/lib/Parser executable-parsers.cpp, flang/test/Semantics cuf23.cuf

[flang][cuda] Accept cuf kernel do without scalar (#205705)

The base compiler accept `!$cuf kernel do()` instead of raising an
error. Update the parser to accept the same syntax.
`!$cuf kernel do()` is equivalent to `!$cuf kernel do`
DeltaFile
+5-0flang/test/Semantics/cuf23.cuf
+3-1flang/lib/Parser/executable-parsers.cpp
+8-12 files

LLVM/project 1827faeclang/test/Driver/print-enabled-extensions aarch64-hip12.c, llvm/lib/Target/AArch64 AArch64Processors.td

[AArch64] Add missing SubtargetFeature for hip12 core (#205246)

The initial patch for the hip12 core had omitted several subtarget
features:

  FeatureFP16FML, FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
  FeatureCCIDX, FeatureRandGen.
DeltaFile
+3-1llvm/lib/Target/AArch64/AArch64Processors.td
+3-0clang/test/Driver/print-enabled-extensions/aarch64-hip12.c
+6-12 files