LLVM/project e0f95ddmlir/lib/Target/LLVMIR ModuleImport.cpp, mlir/test/Target/LLVMIR/Import function-metadata.ll

[MLIR][LLVM] Preserve unknown function metadata on import

Import representable non-debug function metadata without a kind-specific
dialect conversion into `LLVMFuncOp` `function_metadata`. Preserve repeated
metadata kinds through the generic carrier so LLVM IR import and export can
round-trip the supported generic metadata subset.

Warn and drop attachments outside that subset while continuing to import the
function.
DeltaFile
+110-0mlir/test/Target/LLVMIR/Import/function-metadata.ll
+36-5mlir/lib/Target/LLVMIR/ModuleImport.cpp
+146-52 files

LLVM/project bcfea3dmlir/lib/Target/LLVMIR ModuleTranslation.cpp, mlir/test/Target/LLVMIR function-metadata.mlir

[MLIR][LLVM] Translate LLVMFuncOp function metadata

Materialize LLVMFuncOp function_metadata through ModuleTranslation metadata conversion. Attach function metadata after module-level symbols are mapped so metadata references to functions, globals, aliases, and ifuncs can be resolved.
DeltaFile
+156-0mlir/test/Target/LLVMIR/function-metadata.mlir
+49-5mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+205-52 files

LLVM/project 22732e6mlir/include/mlir/Dialect/LLVMIR LLVMOps.td LLVMAttrDefs.td, mlir/lib/Dialect/LLVMIR/IR LLVMAttrs.cpp

[MLIR][LLVM] Add function metadata to LLVMFuncOp

Add a generic LLVM dialect carrier for LLVM IR function metadata on LLVMFuncOp.
Represent attachments as an ordered list so repeated metadata kinds, such as
multiple type metadata attachments, can be preserved while keeping metadata names
language-agnostic.
DeltaFile
+22-0mlir/test/Dialect/LLVMIR/roundtrip.mlir
+22-0mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+20-0mlir/test/Dialect/LLVMIR/invalid.mlir
+18-0mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
+3-0mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+1-0mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+86-06 files

LLVM/project 5e2f10bmlir/include/mlir/Target/LLVMIR ModuleImport.h, mlir/lib/Target/LLVMIR ModuleImport.cpp

[MLIR][LLVM] Preserve global value metadata operands on import (#203017)

Import metadata operands that refer to an `llvm::GlobalValue` as
`#llvm.md_global_value` attributes. Resolve each reference to the MLIR
symbol assigned during module import, retaining synthesized names for
nameless globals.

Report unsupported metadata when an operand has no symbol-backed
representation in the imported module. This covers local values,
intrinsics with dedicated import conversions, and `llvm.global_ctors` or
`llvm.global_dtors`.
DeltaFile
+95-5mlir/test/Target/LLVMIR/Import/intrinsic-unregistered.ll
+41-21mlir/lib/Target/LLVMIR/ModuleImport.cpp
+58-0mlir/test/Target/LLVMIR/Import/import-failure.ll
+12-0mlir/include/mlir/Target/LLVMIR/ModuleImport.h
+206-264 files

LLVM/project 9f30358llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

[RISCV][NFC] Move RISCVCodeGenPrepare Declarations

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVCodeGenPrepare.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 50fb42bllvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

[RISCV][NFC] Move ZacasABIFix Pass Declaration

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVZacasABIFix.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project a290dafllvm/lib/Target/RISCV RISCVCodeGenPassBuilder.cpp RISCVOptWInstrs.h, llvm/test/CodeGen/RISCV O3-newpm-pipeline.ll O1-newpm-pipeline.ll

[RISCV] Port Opt W Instrs to NewPM

Assisted-by: AI
DeltaFile
+44-22llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+35-0llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+3-3llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+2-1llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+2-1llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+90-277 files not shown
+97-3113 files

LLVM/project bbaf9aellvm/lib/Target/RISCV RISCVFoldMemOffset.cpp

Preserve MachineRegisterClassAnalysis
DeltaFile
+1-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+1-01 files

LLVM/project c1a4ceeclang/lib/AST/ByteCode Program.h Compiler.cpp

[clang][bytecode][NFC] Fix some copies in for-range loops (#215544)
DeltaFile
+1-1clang/lib/AST/ByteCode/Program.h
+1-1clang/lib/AST/ByteCode/Compiler.cpp
+1-1clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
+3-33 files

LLVM/project b578cccllvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV fold-mem-offset.mir

[RISCV] Port Fold Memory Offset Pass to NewPM

Assisted-by: AI
DeltaFile
+37-16llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+36-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/fold-mem-offset.mir
+78-213 files not shown
+81-219 files

LLVM/project 2a7d49cllvm/lib/Target/RISCV RISCVVectorPeephole.cpp

Preserve MachineRegisterClassAnalysis
DeltaFile
+1-0llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+1-01 files

LLVM/project a6f8344llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.mir

[RISCV] Port Vector Peephole to NewPM

Assisted-by: AI
DeltaFile
+66-44llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+39-0llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+111-497 files not shown
+119-4913 files

LLVM/project 03ee43allvm/lib/Target/RISCV RISCVVLOptimizer.cpp

Preserve MachineRegisterClassAnalysis
DeltaFile
+1-0llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+1-01 files

LLVM/project ee6176dclang/lib/AST/ByteCode EvalEmitter.h Source.h

[clang][bytecode] Clean up SourceMapper related code (#215528)

Instead of having different `SourceMapper` implementations, just ask the
`Function` directly if we have one, and fall back to the `SourceMapper`
otherwise.

We now only have one `SourceMapper` implementation though:
`EvalEmitter`. And the only reason we have this is so we don't have a
circular dependency between `InterpState` and `EvalEmitter`.
DeltaFile
+21-9clang/lib/AST/ByteCode/InterpFrame.cpp
+6-14clang/lib/AST/ByteCode/Source.cpp
+6-7clang/lib/AST/ByteCode/InterpState.h
+5-5clang/lib/AST/ByteCode/Source.h
+3-5clang/lib/AST/ByteCode/EvalEmitter.h
+41-405 files

LLVM/project 1a4bc95llvm/include/llvm/IR DebugInfoMetadata.h, llvm/lib/CodeGen/AsmPrinter DwarfExpression.cpp

[DebugInfo][NFC] Add typed DIExpression operand views (#215682)

DIExpression users check an opcode and then read its arguments with
numbered getArg() calls. Add typed views for the operations with
repeated raw accesses and use their named accessors in those consumers.

The views reuse ExprOperand's pointer storage and LLVM's cast helpers. A
failed dyn_cast returns an empty view, so conditional matches don't need
an optional wrapper. Reading one is a bug, so getOp() and getArg() now
assert the operand is there rather than dereferencing null.

The only interesting change is that getActiveBits loses the fallthrough
from its extract case into its fragment case. The two shared one read
because both opcodes keep their size in the same argument; now each
names its own through its view and they share a lambda for
the narrowing. A unit test covers both paths.

Overall a bit more code, but quite a bit more readable IMO.


    [2 lines not shown]
DeltaFile
+183-3llvm/include/llvm/IR/DebugInfoMetadata.h
+166-0llvm/unittests/IR/MetadataTest.cpp
+85-43llvm/lib/IR/DebugInfoMetadata.cpp
+51-47llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
+8-8llvm/lib/IR/DIExpressionOptimizer.cpp
+8-6llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+501-1074 files not shown
+518-12410 files

LLVM/project 3091381clang/lib/AST/ByteCode InterpBuiltin.cpp

[clang][bytecode][NFC] Avoid an APFloat copy (#215543)
DeltaFile
+1-1clang/lib/AST/ByteCode/InterpBuiltin.cpp
+1-11 files

LLVM/project 6069eb9clang/lib/AST/ByteCode Interp.cpp

[clang][bytecode][NFC] Remove redundant isInvalidDecl() check (#215546)

This is already checked earlier in the same function.
DeltaFile
+0-4clang/lib/AST/ByteCode/Interp.cpp
+0-41 files

LLVM/project c4f449fclang/include/clang/InstallAPI FileList.h

[clang][InstallAPI] Fix doc comment weirdness (#215462)

We shouldn't be using a documentation comment here.
DeltaFile
+3-3clang/include/clang/InstallAPI/FileList.h
+3-31 files

LLVM/project 0813837llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/WebAssembly simd-extending-convert.ll

[WebAssembly][DAGCombine] Avoid scalarizing v8i8 to v8f16 conversions (#213636)

WebAssembly FP16 can convert `v8i16` to `v8f16`, but direct `v8i8` to
`v8f16` conversions were scalarized during SelectionDAG type
legalization.

This results in lane extractions, scalar conversions, calls to
`__truncsfhf2`, and reconstruction of the result vector.

We should extend `v8i8` to `v8i16` in `performVectorExtendToFPCombine`
before type legalization. This allows the existing WebAssembly combines
to select:

- `i16x8.extend_low_i8x16_{s,u}`
- `f16x8.convert_i16x8_s`
DeltaFile
+25-0llvm/test/CodeGen/WebAssembly/simd-extending-convert.ll
+6-4llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+31-42 files

LLVM/project da69184mlir/include/mlir/Bytecode BytecodeImplementation.h, mlir/include/mlir/IR AffineMap.h OpDefinition.h

[mlir][NFC] Remove internal linkage from core header function templates (#214756)

These are more of the cases fixed alongside #208001, which enabled
-Wunused-template under -Wall. Each template is `static` in a widely
included header, so clang warns in every TU that includes it without
instantiating it. Dropping `static` gives them vague linkage and
silences the warning.
DeltaFile
+8-11mlir/include/mlir/IR/PDLPatternMatch.h.inc
+6-7mlir/include/mlir/IR/OpDefinition.h
+3-3mlir/include/mlir/Pass/PassOptions.h
+2-2mlir/include/mlir/IR/AffineMap.h
+2-2mlir/include/mlir/Bytecode/BytecodeImplementation.h
+21-255 files

LLVM/project 1376072mlir/include/mlir/Dialect/Utils ReshapeOpsUtils.h

[mlir][NFC] Remove internal linkage from reshape op helper templates (#214759)

Another case of the cleanup done for #208001, which enabled
-Wunused-template under -Wall. Both helpers are `static` in
ReshapeOpsUtils.h, which reaches many TUs via Linalg.h, Tensor.h and
MemRef.h, so clang warns wherever they are not instantiated. Dropping
`static` gives them vague linkage.
DeltaFile
+4-4mlir/include/mlir/Dialect/Utils/ReshapeOpsUtils.h
+4-41 files

LLVM/project 69653c1llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

[RISCV][NFC] Move ZacasABIFix Pass Declaration

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVZacasABIFix.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 077b10dllvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

[RISCV][NFC] Move RISCVCodeGenPrepare Declarations

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVCodeGenPrepare.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 4be849cllvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV prefer-w-inst.mir

[RISCV] Port Opt W Instrs to NewPM

Assisted-by: AI
DeltaFile
+44-22llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+35-0llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+3-3llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+88-297 files not shown
+97-3113 files

LLVM/project 5236852llvm/lib/Target/RISCV RISCVPassRegistry.def RISCV.h

[RISCV] Port Fold Memory Offset Pass to NewPM

Assisted-by: AI
DeltaFile
+37-16llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+36-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+78-213 files not shown
+81-219 files

LLVM/project 8dce5c8llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.mir

[RISCV] Port Vector Peephole to NewPM

Assisted-by: AI
DeltaFile
+66-44llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+39-0llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+111-497 files not shown
+119-4913 files

LLVM/project ecaa557llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp, llvm/test/CodeGen/RISCV/rvv vl-opt.mir

[RISCV] Port VL Optimizer to NewPM

Assisted-by: AI
DeltaFile
+56-31llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+36-0llvm/lib/Target/RISCV/RISCVVLOptimizer.h
+1-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+98-363 files not shown
+101-369 files

LLVM/project f13ce96llvm/lib/Target/RISCV RISCV.h

Remove useless header
DeltaFile
+0-1llvm/lib/Target/RISCV/RISCV.h
+0-11 files

LLVM/project 64d780abolt/lib/Profile DataAggregator.cpp

[Perf2bolt] Support multi-PID filtering for multiple perf inputs (#215541)

#199324 added support for multiple perf inputs in perf2bolt. Building on
that, this patch additionally supports filtering by multiple PIDs via
--pid=pid1,pid2...
DeltaFile
+25-16bolt/lib/Profile/DataAggregator.cpp
+25-161 files

LLVM/project 035c725llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll f32x2-instructions.ll

[NVPTX] Cleanup PTX ISA subtarget features (#214623)
DeltaFile
+1,514-802llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
+654-654llvm/test/CodeGen/NVPTX/tcgen05-st.ll
+573-573llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+493-301llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
+354-298llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
+276-276llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+3,864-2,90489 files not shown
+8,229-7,04695 files