[X86] haddsub-undef.ll - rename undef functions to match equivalents in phaseordering tests (#207207)
Still some churn / regressions to address, but this is the same IR as
we're attempting in PhaseOrdering/X86/hadd.ll
Still need to update them to the vectorized IR from the middle-end
clang: Use a switch over APFloat semantics instead of if chain
Replace the chain of fltSemantics singleton address comparisons with a
switch over the APFloatBase::Semantics enum.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
clang: Remove useFP16ConversionIntrinsics target option
Follow up to #174494. Remove the remnants of the control to
use llvm.convert.to.fp16/llvm.convert.from.fp16. Prefer
directly using the IR half type, unless the value is used
in an ABI context where it needs to remain as i16.
I did the first 80% of this a long time ago, and AI finished
the last bit and handled the recent rebases and test updates.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[X86] Add AVX512BMM support for AMD Zen 6 (znver6) (#182556)
This patch adds support for AVX512BMM (Bit Matrix Multiply) instruction
set extension for AMD Zen 6 processors.
AVX512BMM includes three instructions:
- VBITREVB: Bit reverse within each byte
- VBMACOR: Bit matrix multiply with OR accumulation
- VBMACXOR: Bit matrix multiply with XOR accumulation
The following implementations for AVX512BMM are added:
- Define __AVX512BMM__ macro for znver6
- avx512bmmintrin.h, avx512bmmvlintrin.h header files
- Implement _mm_bitrev_epi8, _mm256_bitrev_epi8, _mm512_bitrev_epi8
- Implement _mm256/512_bmacor16x16x16 and bmacxor intrinsics
[clang] Check `T` and `U` operands of __reference_constructs_from_temporary are complete types (#206703)
This PR fix a bug introduce by
https://github.com/llvm/llvm-project/pull/206527.
[type.traits] Precondition : "T and U shall be complete types, cv void,
or arrays of unknown bound first.
The check for which
[#206527](https://github.com/llvm/llvm-project/pull/206527.) disables if
the first argument isn't a reference type.
---------
Signed-off-by: yronglin <yronglin777 at gmail.com>
[OpenACC] Fix reduction var equality check for member variables (#207196)
OpenACC requires we check that a variable have the same operator in all
nested constructs with a reduction. The implementation for this checks
everything I could think of, but I apparently missed member expressions.
This patch adds checks for that as well as 'this' so we should correctly
get the checks.
Fixes: #207180
[Dexter] Add ability to check float values within a range (#204161)
Adds a new node type, !float, which can be used to match debugger ouptut
as
float values rather than as strings, optionally allowing a range to be
specified for inexact matches. This new node allows a list of values to
be
given, effectively a shorthand for a list of individual !float nodes.
[X86] haddsub-2.ll - sync scalar "not" hsub tests between the middle-end and backend (#207192)
Replace the codegen scalar tests with the IR that middle-end actually generates
Help towards #143000
[AArch64] NFC: Factor out code from FP_TO_INT (SVE).
This just moves out some of the SVE lowering code from
LowerVectorFP_TO_INT into a separate function, so that we
can reuse that in LowerVectorFP_TO_INT_SAT.
[AArch64] NFCI: Simplify LowerVectorFP_TO_INT_SAT (part 2)
This simplifies the logic a bit more, such that the flow of the
lowering is as follows:
* Try to promote if necessary (fp16/bf16 types or src < dst)
* Try to handle natively (satwidth == srcwidth == dstwidth)
* Otherwise use min/max + truncate.