LLVM/project 3211ce1flang/docs/MeetingNotes/2026 2026-02-25.md

[flang] Added minutes from the 2-25-2026 Flang Community Call (#183389)

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+66-0flang/docs/MeetingNotes/2026/2026-02-25.md
+66-01 files

LLVM/project dff87d3lldb/test/API/lang/objc/failing-description TestObjCFailingDescription.py, lldb/test/API/lang/objc/struct-description TestObjCStructDescription.py

Revert "[lldb/test] Fix tests reading log from remote platform instead of hos…"

This reverts commit b3ec476c702a1cd8ada8686a2be4fed7cccf81ef.
DeltaFile
+2-4lldb/test/API/lang/objc/failing-description/TestObjCFailingDescription.py
+2-4lldb/test/API/lang/objc/struct-description/TestObjCStructDescription.py
+4-82 files

LLVM/project f38e7b1lld/docs WebAssembly.rst index.rst

[lld][WebAssembly] Remove comment about wasm-ld being WIP. NFC (#183410)

wasm-ld has been feature complete for a while now.
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+2-2lld/docs/WebAssembly.rst
+1-2lld/docs/index.rst
+3-42 files

LLVM/project b3ec476lldb/test/API/lang/objc/failing-description TestObjCFailingDescription.py, lldb/test/API/lang/objc/struct-description TestObjCStructDescription.py

[lldb/test] Fix tests reading log from remote platform instead of host (#183413)

Some tests are using logs to validate that a test behaves correctly
however they used `platform shell cat {log}` to read the logfile.

This doesn't work when running the testsuite against a remote platform
since the logs are saved on the host's filesystem.

This patch addresses those failures by making sure we read the log file
from the host platform.

Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
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+4-2lldb/test/API/lang/objc/failing-description/TestObjCFailingDescription.py
+4-2lldb/test/API/lang/objc/struct-description/TestObjCStructDescription.py
+8-42 files

LLVM/project f01f0f0.github/workflows libcxx-run-benchmarks.yml

[libc++] Try using job.check_run_id instead of github.job

According to https://github.com/orgs/community/discussions/8945,
it seems I'm not the only one who is confused by the documentation.
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+1-1.github/workflows/libcxx-run-benchmarks.yml
+1-11 files

LLVM/project 2370063mlir/include/mlir/Dialect/OpenACC OpenACCUtilsLoop.h, mlir/lib/Dialect/OpenACC/Utils OpenACCUtilsLoop.cpp

[openacc] Change function wrapMultiBlockRegionWithSCFExecuteRegion to non-static (#183409)

This change updates function `wrapMultiBlockRegionWithSCFExecuteRegion`
to be non-static.
DeltaFile
+72-0mlir/unittests/Dialect/OpenACC/OpenACCUtilsLoopTest.cpp
+18-0mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsLoop.h
+6-6mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsLoop.cpp
+96-63 files

LLVM/project 2acb24ellvm/lib/Target/ARM ARMISelLowering.cpp, llvm/test/CodeGen/ARM shift-combine.ll

[ARM] optimize to `vsri`/`vsli` (#182051)

fixes https://github.com/llvm/llvm-project/issues/181495
DeltaFile
+1,303-0llvm/test/CodeGen/ARM/shift-combine.ll
+63-3llvm/lib/Target/ARM/ARMISelLowering.cpp
+1,366-32 files

LLVM/project 122e79cllvm/lib/CodeGen MachineScheduler.cpp, llvm/test/CodeGen/AMDGPU a-v-flat-atomicrmw.ll freeze.ll

[MISched] Advance HazardRec past stalls before calling EmitInstruction (#182977)

There are three calls to bumpCycle in bumpNode. Prior to the first call,
we calculate NextCycle as the next cycle in which all of a given
instruction's required hardware resources (as defined by the SchedModel)
are available. Any gap between this calculated NextCycle and CurrCycle
measures stalls that must occur before we can schedule the given
instruction.

The second and third call handle adjustments that occur during or after
issuing of the instruction (e.g. if the number of microops exceeds the
issue width).

According to the documentation of HazardRec->EmitInstruction, we should
call this method when an instruction is emitted: "This callback is
invoked when an instruction is emitted, to advance the hazard state."

In the context of bumpNode, this implies that it should be called after
we bumpCycle for stalls that must occur before issue of the

    [18 lines not shown]
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+20-26llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+18-25llvm/test/CodeGen/AMDGPU/freeze.ll
+12-11llvm/lib/CodeGen/MachineScheduler.cpp
+12-8llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+9-10llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
+6-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
+77-8610 files not shown
+103-11716 files

LLVM/project 6079e39libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+0-1libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
+0-1libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
+0-22 files

LLVM/project f454b5elibcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+0-1libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
+0-1libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
+0-22 files

LLVM/project 2037a50libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+0-1libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
+0-1libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
+0-22 files

LLVM/project 6e4ddb5libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+0-1libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
+0-1libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
+0-22 files

LLVM/project 6d32c36libcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+0-1libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
+0-1libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
+0-22 files

LLVM/project b732d7flibcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+0-1libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
+0-1libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
+0-22 files

LLVM/project 576932blibcxx/test/extensions/gnu/hash_map non_standard_layout.pass.cpp, libcxx/test/extensions/gnu/hash_multimap non_standard_layout.pass.cpp

Whitespace change

Created using spr 1.3.6-beta.1
DeltaFile
+0-1libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
+0-1libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
+0-22 files

LLVM/project 6272d5a.github/workflows libcxx-run-benchmarks.yml

[libc++] Use the Github context instead of env to access the run ID & friends
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+1-1.github/workflows/libcxx-run-benchmarks.yml
+1-11 files

LLVM/project 25ebf5ellvm/test/MC/RISCV rv32p-valid.s rv64p-valid.s

[RISCV] Add missing immediates to check lines in rv32p-valid.s and rv64p-valid.s. NFC (#183238)

DeltaFile
+27-27llvm/test/MC/RISCV/rv32p-valid.s
+1-1llvm/test/MC/RISCV/rv64p-valid.s
+28-282 files

LLVM/project 8539dcallvm/include/llvm/MC MCAsmInfo.h, llvm/lib/MC MCAsmInfo.cpp

[MC] Consistent use of inline field initializers in MCAsmInfo (#183343)

DeltaFile
+3-3llvm/include/llvm/MC/MCAsmInfo.h
+0-4llvm/lib/MC/MCAsmInfo.cpp
+3-72 files

LLVM/project a5f52b0llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,976 files not shown
+394,965-143,0555,982 files

LLVM/project b2430bbllvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,976 files not shown
+394,965-143,0555,982 files

LLVM/project c7103a4llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,976 files not shown
+394,965-143,0555,982 files

LLVM/project 85a73a6llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,976 files not shown
+394,965-143,0555,982 files

LLVM/project 812a378llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,995 files not shown
+395,998-143,0896,001 files

LLVM/project ac0d3e6llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,995 files not shown
+395,998-143,0896,001 files

LLVM/project 90bbc06clang/docs ClangIRCleanupAndEHDesign.md, clang/lib/CIR/Dialect/Transforms IdiomRecognizer.cpp

Rebase

Created using spr 1.3.6-beta.1
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+193-0lldb/source/Plugins/ScriptInterpreter/Lua/LuaState.cpp
+0-191lldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
+102-73mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+94-55clang/docs/ClangIRCleanupAndEHDesign.md
+119-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.ll
+96-0clang/lib/CIR/Dialect/Transforms/IdiomRecognizer.cpp
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LLVM/project 33ae573clang/docs ClangIRCleanupAndEHDesign.md, clang/lib/CIR/Dialect/Transforms IdiomRecognizer.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
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+193-0lldb/source/Plugins/ScriptInterpreter/Lua/LuaState.cpp
+0-191lldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
+102-73mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+94-55clang/docs/ClangIRCleanupAndEHDesign.md
+119-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.ll
+96-0clang/lib/CIR/Dialect/Transforms/IdiomRecognizer.cpp
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LLVM/project ee3bb59llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Rebase, use correct macro name

Created using spr 1.3.6-beta.1
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+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,992 files not shown
+395,957-143,0785,998 files

LLVM/project 0de8ae1llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,991 files not shown
+395,954-143,0765,997 files

LLVM/project fa3b86bllvm/lib/Target/RISCV RISCVMoveMerger.cpp, llvm/test/CodeGen/RISCV rv32-move-merge.ll double-round-conv-sat.ll

[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)

Extends RISCVMoveMerger to identify adjacent 32-bit moves that can be
combined into a single 64-bit move instruction. In particular, this
patch adds support for extension zdinx (`fmv.d`) and p(`padd.dw`).

Fixes #180831
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+113-23llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
+46-0llvm/test/CodeGen/RISCV/rv32-move-merge.ll
+12-24llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
+10-20llvm/test/CodeGen/RISCV/double-select-icmp.ll
+26-0llvm/test/CodeGen/RISCV/rv32-merge-non-arg-reg.mir
+7-14llvm/test/CodeGen/RISCV/rv32p.ll
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LLVM/project 5a629e6llvm/lib/Target/ARM/MCTargetDesc ARMMCAsmInfo.cpp, llvm/lib/Target/LoongArch/MCTargetDesc LoongArchMCAsmInfo.cpp

[MC] Remove redundant setting of AllowDollarAtStartOfIdentifier. NFC (#183339)

This setting defaults to false so there is no need to set it unless we
want it to be true.

This makes it easy to see at a glace which backends support this, and
matches the existing behaviour of other fields such as
`AllowAtAtStartOfIdentifier`, `AllowQuestionAtStartOfIdentifier`,
`UseAssignmentForEHBegin` and `AllowAtInName`. These are all only ever
set to true in subclasses, never false.
DeltaFile
+0-5llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
+0-3llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
+0-2llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
+0-1llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCAsmInfo.cpp
+0-1llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
+0-125 files