LLVM / project - FreshBSD

LLVM/project e71f327 — clang/include/clang/Options Options.td, clang/lib/Driver/ToolChains/Arch X86.cpp

2026-03-03 22:42:49 UTC by zhouguangyuan0718 via GitHub on ⎇

main

[X86] support reserve r8~r15 on X86_64 (#180242)

Which is under discussion in
https://github.com/llvm/llvm-project/issues/179036

Add new options -ffixed_r{8-15} for clang X86 target, like option
"-ffixed_x" for RISCV/AArch64 target.
Also, add target-feature +reserve-r{8-15} for the X86 backend.

The registers which are specified reserved will not be used in
RegAlloc/CalleeSave. Then the reserved registers can be maintained by
user. It will be useful for the runtime/interpreter implementation.

Other registers are used in specific instructions or mechanism, so they
can't be reserved.

Delta		File
+114	-0	llvm/test/CodeGen/X86/reserveRreg.ll
+114	-0	clang/test/Driver/x86_64-fixed-r-register.c
+60	-0	clang/lib/Driver/ToolChains/Arch/X86.cpp
+10	-3	clang/include/clang/Options/Options.td
+12	-0	llvm/lib/Target/X86/X86ISelLowering.cpp
+11	-0	llvm/lib/Target/X86/X86RegisterInfo.cpp
+321	-3	5 files not shown
+356	-4	11 files

LLVM/project 1b633d6 — clang/docs ReleaseNotes.rst, clang/lib/Sema SemaChecking.cpp

2026-03-03 22:35:04 UTC by Joseph Huber via GitHub on ⎇

main

[Clang] Permit floating point and pointer values in most atomic ops (#183843)

Summary:
We already support floating point arguments for the standard atomic
functions. LLVM supports these in most cases as well. This PR unifies
the handling and allows this in the cases that the LLVM IR supports.

Delta		File
+16	-11	clang/lib/Sema/SemaChecking.cpp
+26	-0	clang/test/Sema/scoped-atomic-ops.c
+13	-6	clang/test/Sema/atomic-ops.c
+3	-0	clang/docs/ReleaseNotes.rst
+58	-17	4 files

LLVM/project 28638f5 — lldb/include/lldb/Core Debugger.h, lldb/include/lldb/Target Process.h

2026-03-03 22:29:15 UTC by Jonas Devlieghere via GitHub on ⎇

main

[lldb] Remove Debugger::{FindTargetWithProcessID, FindTargetWithProcess} (#184446)

In #184259, Jim noticed that Debugger::FindTargetWithProcess and
Debugger::FindTargetWithProcessID are rather poorly designed APIs as
tehy allow code running in one Debugger to mess with Targets from
another Debugger. The only use is Process::SetProcessExitStatus which
isn't actually used.

Delta		File
+0	-30	lldb/source/Target/Process.cpp
+0	-28	lldb/source/Core/Debugger.cpp
+0	-16	lldb/include/lldb/Target/Process.h
+0	-4	lldb/include/lldb/Core/Debugger.h
+0	-78	4 files

LLVM/project f4e64ce — lldb/source/Plugins/ABI/AArch64 ABIAArch64.cpp, lldb/source/Plugins/Process/Utility RegisterInfos_arm64.h RegisterInfos_arm64_sve.h

2026-03-03 22:28:00 UTC by Jason Molenda via GitHub on ⎇

main

[lldb] AArch64 register 33 is not cpsr (#183860)

I have an unwind failure where the eh_frame for a
trap handler states that the caller's return address is in eh_frame
register 33, which lldb treats as cpsr.
https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst#dwarf-register-names
Register 33 is ELR_mode, which isn't defined as a register in any of the
AArch64 register definition files in lldb today, so I'm not adding it to
the header files.

rdar://170602999

Delta		File
+17	-11	lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+5	-5	lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
+8	-2	lldb/source/Utility/ARM64_DWARF_Registers.h
+8	-2	lldb/source/Utility/ARM64_ehframe_Registers.h
+0	-4	lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
+0	-2	lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
+38	-26	1 files not shown
+39	-27	7 files

LLVM/project 685a65a — clang-tools-extra Maintainers.rst

2026-03-03 22:24:16 UTC by mitchell via GitHub on ⎇

main

[clang-tidy] Add zeyi2 as maintainer (#183883)

I've been actively contributing to `clang-tidy` for the past 4 months,
reviewing PRs, [fixing
issues](https://github.com/pulls?q=is%3Apr+author%3Azeyi2+archived%3Afalse+user%3Allvm+is%3Aclosed+label%3Aclang-tidy+sort%3Aupdated-desc),
engaging in discourse discussions and building [new testing
tools](https://github.com/clang-tidy-infra/CTIT). I'm passionate about
and project and would like to volunteer as a maintainer to continue
supporting the project's growth :)

Delta		File
+3	-0	clang-tools-extra/Maintainers.rst
+3	-0	1 files

LLVM/project 50e3cc0 — clang/lib/Sema SemaARM.cpp, clang/test/Sema/AArch64 pcdphint-atomic-store.c

2026-03-03 22:16:34 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Ensure Context.getTypeSize() is only called after checking ValType->isIntegerType()

Delta		File
+6	-0	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+3	-2	clang/lib/Sema/SemaARM.cpp
+9	-2	2 files

LLVM/project 9264159 — lldb/unittests/DAP TestBase.cpp TestBase.h

2026-03-03 22:15:39 UTC by Jonas Devlieghere via GitHub on ⎇

main

[lldb] Fix the GoogleTest teardown in the DAP unit tests (#184262)

Some of the DAP tests define a static method named `TeatUpTestSuite`
which is calling `SBDebugger::Terminate`. Besides the typo, the correct
method is `TearDownTestSuite`, which GoogleTest calls after running the
last test in the test suite.

When addressing this, I realized that currently you can't really call
Initialize and Terminate multiple times in the same process. This
depends on:

- https://github.com/llvm/llvm-project/pull/184259
- https://github.com/llvm/llvm-project/pull/184261

Delta		File
+1	-1	lldb/unittests/DAP/TestBase.cpp
+1	-1	lldb/unittests/DAP/TestBase.h
+1	-1	lldb/unittests/DAP/VariablesTest.cpp
+3	-3	3 files

LLVM/project 5b144c0 — clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-tensor-load-store.cl, llvm/lib/Target/AMDGPU MIMGInstructions.td SIInstrInfo.cpp

2026-03-03 22:10:38 UTC by Changpeng Fang via GitHub on ⎇

main

[AMDGPU] Add suffix _d4 to tensor load/store with 4 groups D#, NFC (#184176)

Rename TENSOR_LOAD_TO_LDS to TENSOR_LOAD_TO_LDS_d4;
  Rename TENSOR_STORE_FROM_LDS to TENSOR_STORE_FROM_LDS_d4;
Also rename function names in a couple of tests to reflect this change.

Delta		File
+10	-10	llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
+6	-6	llvm/lib/Target/AMDGPU/MIMGInstructions.td
+6	-6	llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+6	-6	llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
+4	-4	clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-tensor-load-store.cl
+3	-3	llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+35	-35	3 files not shown
+42	-42	9 files

LLVM/project d47c8d0 — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 pcdphint-atomic-store-diagnostic.ll

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Move tests to llvm/test/Verifier

Delta		File
+0	-54	llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+47	-0	llvm/test/Verifier/intrinsic-immarg.ll
+0	-32	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+47	-86	3 files

LLVM/project 06e352b — clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Small fixes Kerry has suggested

Delta		File
+112	-40	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+7	-11	clang/lib/Sema/SemaARM.cpp
+7	-9	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1	-1	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+127	-61	4 files

LLVM/project 62fe6f6 — clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64InstrInfo.td AArch64InstrFormats.td

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Address more helpful review comments from Kerry

Delta		File
+160	-0	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4	-4	llvm/lib/Target/AArch64/AArch64InstrInfo.td
+0	-5	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+1	-4	clang/lib/Sema/SemaARM.cpp
+165	-13	4 files

LLVM/project 95d2e67 — clang/test/CodeGen arm_acle.c builtins-arm64.c, clang/test/Sema/AArch64 pcdphint-atomic-store.c

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fix more PR comments

Delta		File
+19	-9	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+8	-6	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+10	-0	clang/test/CodeGen/arm_acle.c
+0	-9	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5	-0	clang/test/CodeGen/builtins-arm64.c
+0	-4	llvm/include/llvm/IR/IntrinsicsAArch64.td
+42	-28	2 files not shown
+44	-32	8 files

LLVM/project 7e0c35f — clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/IR Verifier.cpp

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! More small optimisations Kerry spotted

Delta		File
+7	-12	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2	-3	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+1	-2	llvm/lib/IR/Verifier.cpp
+10	-17	3 files

LLVM/project 6606f14 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Address Carol's comments and fix git clang-format issues

Delta		File
+27	-0	llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+20	-0	llvm/lib/IR/Verifier.cpp
+12	-6	clang/lib/Sema/SemaARM.cpp
+0	-11	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4	-2	clang/lib/Headers/arm_acle.h
+2	-4	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+65	-23	6 files

LLVM/project 37b40b9 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! More small fixes

Delta		File
+15	-37	clang/lib/Sema/SemaARM.cpp
+11	-0	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5	-3	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2	-2	clang/lib/Headers/arm_acle.h
+0	-1	clang/test/CodeGen/arm_acle.c
+33	-43	5 files

LLVM/project 5313224 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`

Move code to `AArch64ExpandPseudoInsts` and `getTgtMemIntrinsic`
and use tablegen pattern for intrinsic, plus other small review changes.

Delta		File
+47	-75	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+69	-32	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+42	-47	clang/lib/Sema/SemaARM.cpp
+21	-12	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+10	-12	llvm/lib/Target/AArch64/AArch64InstrInfo.td
+17	-5	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+206	-183	5 files not shown
+220	-192	11 files

LLVM/project f7f4f88 — llvm/test/CodeGen/AArch64 pcdphint-atomic-store.ll

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Sort out testcases

Delta		File
+54	-102	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+54	-102	1 files

LLVM/project 68bcea8 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fixes for Caroline

Delta		File
+27	-0	llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+1	-12	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2	-2	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+0	-3	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+30	-17	4 files

LLVM/project 98360dc — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

2026-03-03 22:08:07 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fix tests

Delta		File
+2	-0	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2	-0	1 files

LLVM/project 90a29b8 — llvm/include/llvm/IR IntrinsicsAArch64.td, llvm/lib/Target/AArch64 AArch64InstrFormats.td

2026-03-03 22:08:06 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! remove mayLoad/mayStore as suggested by Kerry

Delta		File
+0	-5	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+1	-1	llvm/include/llvm/IR/IntrinsicsAArch64.td
+1	-6	2 files

LLVM/project 8ec6f20 — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/CodeGen/AArch64 pcdphint-atomic-store.c

2026-03-03 22:08:06 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Ensure stshh always immediately precedes a store instruction

Delta		File
+82	-0	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+50	-13	clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+62	-0	llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+20	-26	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+15	-0	llvm/lib/Target/AArch64/AArch64InstrInfo.td
+8	-3	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+237	-42	3 files not shown
+248	-49	9 files

LLVM/project abe9be7 — clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

2026-03-03 22:08:06 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Improve error diagnostics, and other cleanups

Delta		File
+12	-0	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4	-2	clang/lib/Sema/SemaARM.cpp
+2	-1	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1	-1	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+1	-1	clang/include/clang/Basic/DiagnosticSemaKinds.td
+2	-0	clang/lib/Headers/arm_acle.h
+22	-5	6 files

LLVM/project 187a6fd — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/Sema/AArch64 pcdphint-atomic-store.c

2026-03-03 22:08:06 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup!

A few small tidyups

Delta		File
+7	-6	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4	-4	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+4	-0	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+15	-10	3 files

LLVM/project da20c4f — clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

2026-03-03 22:08:06 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin

Add `__arm_atomic_store_with_stshh` implementation as defined
in the ACLE. Validate that the arguments passed are correct, and
lower it to the stshh intrinsic plus an atomic store with the
allowed orderings.

Gate this on FEAT_PCDPHINT so that availability matches
hardware support for the `STSHH` instruction. Use an i64
immediate and side-effect modeling to satisfy tablegen and decoding.

Delta		File
+140	-0	clang/lib/Sema/SemaARM.cpp
+48	-0	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+31	-0	clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+29	-0	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+13	-0	llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+10	-2	llvm/lib/Target/AArch64/AArch64InstrFormats.td
+271	-2	5 files not shown
+298	-2	11 files

LLVM/project f1b2d2c — clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

2026-03-03 22:08:06 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fix Kerry's CR comments and add negative test for "must be an integer type"

Delta		File
+16	-6	llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+3	-7	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+3	-3	clang/lib/Sema/SemaARM.cpp
+5	-0	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+3	-0	clang/include/clang/Basic/DiagnosticSemaKinds.td
+1	-1	clang/lib/Headers/arm_acle.h
+31	-17	6 files

LLVM/project 9abef46 — clang/include/clang/Basic BuiltinsAArch64.def, clang/lib/CodeGen/TargetBuiltins ARM.cpp

2026-03-03 22:08:06 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup!

More small issues tidied, and remove gating.

Delta		File
+6	-2	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+2	-2	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+0	-2	clang/lib/Headers/arm_acle.h
+1	-1	clang/lib/Sema/SemaARM.cpp
+1	-1	clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+1	-1	clang/include/clang/Basic/BuiltinsAArch64.def
+11	-9	6 files

LLVM/project 284ecb4 — clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

2026-03-03 22:08:06 UTC by Jonathan Thackray on ⎇

users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh

fixup! Fix issues Kerry raised in PR

Delta		File
+10	-23	clang/lib/Sema/SemaARM.cpp
+16	-11	clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5	-12	clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1	-5	clang/include/clang/Basic/DiagnosticSemaKinds.td
+32	-51	4 files

LLVM/project 1953b87 — clang/include/clang/CIR MissingFeatures.h, clang/include/clang/CIR/Dialect/Builder CIRBaseBuilder.h

2026-03-03 22:01:49 UTC by Ayokunle Amodu via GitHub on ⎇

main

[CIR][CodeGen] Upstream support for `__builtin_isinf_sign` (#183977)

This adds CIR codegen and lowering support for `__builtin_isinf_sign`.

Delta		File
+39	-0	clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
+29	-0	clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+24	-1	clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+17	-0	clang/include/clang/CIR/Dialect/IR/CIROps.td
+5	-0	clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
+1	-0	clang/include/clang/CIR/MissingFeatures.h
+115	-1	6 files

LLVM/project 89a4bcf — clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

2026-03-03 21:34:18 UTC by Henrich Lauko via GitHub on ⎇

main

[CIR] Split cir.binop into separate per-operation binary ops (#184227)

Replace the single `cir.binop` operation (dispatched via a `BinOpKind`
enum) with nine distinct ops — `cir.add`, `cir.sub`, `cir.mul`,
`cir.div`, `cir.rem`, `cir.and`, `cir.or`, `cir.xor`, and `cir.max` —
each with precise type constraints and only the attributes it needs
(nsw/nuw/sat on add/sub via `BinaryOverflowOp`).

A new `BinaryOpInterface` provides uniform `getLhs`/`getRhs`/`getResult`
access for passes and analyses.

The monolithic switch-based CIRToLLVMBinOpLowering is replaced by per-op
patterns generated through the existing CIRLowering.inc TableGen
infrastructure, with shared dispatch factored into two helpers:
`lowerSaturatableArithOp` for add/sub and `lowerIntFPBinaryOp` for
div/rem.

Delta		File
+491	-491	clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c
+242	-56	clang/include/clang/CIR/Dialect/IR/CIROps.td
+124	-124	clang/test/CIR/CodeGen/complex-mul-div.cpp
+129	-106	clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+92	-92	clang/test/CIR/CodeGenBuiltins/X86/sse41-builtins.c
+73	-73	clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-CtorDtor.cpp
+1,151	-942	103 files not shown
+2,353	-2,106	109 files

LLVM/project c4ea6cc — lldb/source/Plugins/Process/MacOSX-Kernel ProcessKDP.cpp, lldb/source/Plugins/Process/mach-core ProcessMachCore.cpp

2026-03-03 21:17:21 UTC by Jonas Devlieghere via GitHub on ⎇

main

[lldb] Remove call_once wrappers around PluginManager::RegisterPlugin (#184273)

Remove call_once wrappers around PluginManager::RegisterPlugin. Plugins
can be registered and unregistered in Initialize and Terminate
respectively. In its current state, after having called Terminate, a
plugin can never be re-initialized.

Delta		File
+4	-11	lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
+5	-10	lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
+3	-11	lldb/source/Plugins/ScriptInterpreter/None/ScriptInterpreterNone.cpp
+3	-10	lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
+3	-8	lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
+3	-7	lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
+21	-57	7 files not shown
+38	-106	13 files