LLVM/project d6ffa06llvm/lib/IR Constants.cpp, llvm/test/Assembler aggregate-constant-values.ll

[RFC][IR] Support vector splats in `ConstantPointerNull`

This PR allows `ConstantPointerNull` to represent both scalar pointer nulls and
fixed or scalable vector splats of pointer nulls. This change first aligns with
the native splat behavior of `ConstantInt` and `ConstantFP`, and second, makes
it easier to eventually change the semantics of `ConstantPointerNull` to
represent a semantic null pointer instead of a zero value, which is what it
represents today.
DeltaFile
+31-31llvm/test/Transforms/RewriteStatepointsForGC/base-vector.ll
+30-30llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
+52-4llvm/lib/IR/Constants.cpp
+28-0llvm/unittests/IR/ConstantsTest.cpp
+18-9llvm/test/Transforms/RewriteStatepointsForGC/base-inference.ll
+24-0llvm/test/Assembler/aggregate-constant-values.ll
+183-7451 files not shown
+333-20357 files

LLVM/project 3e2eb32llvm/lib/IR Constants.cpp, llvm/test/Assembler aggregate-constant-values.ll

[RFC][IR] Support vector splats in `ConstantPointerNull`

This PR allows `ConstantPointerNull` to represent both scalar pointer nulls and
fixed or scalable vector splats of pointer nulls. This change first aligns with
the native splat behavior of `ConstantInt` and `ConstantFP`, and second, makes
it easier to eventually change the semantics of `ConstantPointerNull` to
represent a semantic null pointer instead of a zero value, which is what it
represents today.
DeltaFile
+31-31llvm/test/Transforms/RewriteStatepointsForGC/base-vector.ll
+30-30llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
+51-4llvm/lib/IR/Constants.cpp
+28-0llvm/unittests/IR/ConstantsTest.cpp
+18-9llvm/test/Transforms/RewriteStatepointsForGC/base-inference.ll
+24-0llvm/test/Assembler/aggregate-constant-values.ll
+182-7450 files not shown
+328-20356 files

LLVM/project 5bc46b1llvm/test/Transforms/LoopVectorize as_cast.ll

[LV] Modernize as_cast.ll test. (NFC) (#195481)

Update as_cast.ll to cover both loop-invariant and varying address space
casts, as well as auto-generating the checks.
DeltaFile
+93-27llvm/test/Transforms/LoopVectorize/as_cast.ll
+93-271 files

LLVM/project ecbd653llvm/lib/Transforms/Utils CodeExtractor.cpp, llvm/test/Transforms/HotColdSplit stale-funcretval-after-sever.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+32-0llvm/test/Transforms/HotColdSplit/stale-funcretval-after-sever.ll
+3-0llvm/lib/Transforms/Utils/CodeExtractor.cpp
+35-02 files

LLVM/project 1f34e4bllvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Set predecessor of DispatchVPBB early (NFC). (#195480)

This allows finding the containing plan earlier, which helps when trying
to print DispatchVPBB in a debugger.
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-11 files

LLVM/project ff94721llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp

[VPlan] Add VPBuilder methods to create (First|Last)ActiveLane (NFC). (#195479)

Add dedicaed helpers to builder to slightly simplify code a use-sites.
DeltaFile
+14-0llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+5-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-2llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+20-103 files

LLVM/project 13371e2compiler-rt/lib/ubsan ubsan_diag.cpp

[compiler-rt][UBSan][NFC] Reorder includes in ubsan_diag.cpp (#195435)
DeltaFile
+3-1compiler-rt/lib/ubsan/ubsan_diag.cpp
+3-11 files

LLVM/project 1cd649cclang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Use declarative TableGen constraints for overflow flag verification

Replace hand-written C++ verifiers with PredOpTrait-based constraints
(FlagRequiresIntType, HasAtMostOneOfAttrs). Introduce CIR_SaturatableBinaryOp
base class and use append/prepend ODS directives to compose arguments, format,
and traits across the op hierarchy. Fix HasAtMostOneOfAttrsPred to use
accessor methods instead of dollar-sign references. Add Commutative trait
to AddOp and MulOp.
DeltaFile
+49-35clang/include/clang/CIR/Dialect/IR/CIROps.td
+0-39clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+4-4clang/test/CIR/CodeGen/size-of-vla.cpp
+4-4clang/test/CIR/CodeGen/vla.c
+2-2clang/test/CIR/CodeGen/delete-array.cpp
+59-845 files

LLVM/project 3b32d6ellvm/include/llvm/CodeGen/GlobalISel GenericMachineInstrs.h, llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp

[X86][GlobalISel] Support fp80 for G_FPTRUNC and G_FPEXT (#141611)

Introduce `G_FPEXTLOAD` and `G_FPTRUNCSTORE` for extending load and
truncating store of a floating point value.

* Introduce `IfFPExtend` and `IfFPTrunc` into `GINodeEquiv` to dispatch
SDAG patterns to the newly introduced opcodes similarly to `G_SEXTLOAD`
and `G_ZEXTLOAD`.
* Added narrowing and widening for the opcodes. However they aren't used
anywhere.
* Supported lowering of `G_FPEXTLOAD` and `G_FPTRUNCSTORE` for X86 by
using X87.
* Added `lowerFPExtAndTruncMem` as default lowering for `G_FPTRUNC` and
`G_FPEXT` using memory.
* Dropped autogenerated line from `legalizer-info-validation.mir` as
scripts can't update them anymore.
* Updated `match-table-cxx.td` with regexps. This is not the first PR
that updates the whole test after opcode introduction.
DeltaFile
+259-0llvm/test/CodeGen/X86/isel-fptrunc-fpext.ll
+66-66llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
+77-3llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+27-27llvm/test/TableGen/RegClassByHwMode.td
+39-5llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+32-0llvm/test/MachineVerifier/test_g_fptruncstore.mir
+500-10119 files not shown
+688-12825 files

LLVM/project 124d442clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

[CIR] Extract CIR_ClassCastOp base class for BaseClassAddrOp and DerivedClassAddrOp

Both ops have identical structure (arguments, results, assembly format)
and differ only in mnemonic and description. Extract a shared TableGen
base class to eliminate the duplication. Also improve the assembly format
to print nonnull before the operand and place the type after the offset.
DeltaFile
+22-33clang/include/clang/CIR/Dialect/IR/CIROps.td
+18-18clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+8-8clang/test/CIR/CodeGen/vtt.cpp
+5-5clang/test/CIR/CodeGen/derived-to-base.cpp
+4-4clang/test/CIR/CodeGen/inherited-ctors.cpp
+3-3clang/test/CIR/CodeGen/base-to-derived.cpp
+60-7114 files not shown
+90-10120 files

LLVM/project c4fc27cllvm/lib/Transforms/Vectorize VPlanConstruction.cpp LoopVectorize.cpp

[VPlan] Strip pred-block check in inLoopReductions (NFC) (#194086)

A VPInstruction will only have a mask if the block needs predication.
DeltaFile
+3-8llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+1-7llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1-3llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+5-183 files

LLVM/project 8ee61adllvm/lib/Target/AMDGPU SIInstructions.td AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU fneg-fabs-v2f32.ll

[AMDGPU] Make v2f32 legal for G_FNEG and G_FABS and pattern update (#195419)

  G_FNEG and G_FABS were made legal for v2f32 when packed fp32 instructions were implemented.
For some unknown reasons, this legalization was not upstreamed yet. This work makes v2f32 legal for
G_FNEG and G_FABS, and updates a few tablegen patterns to ensure instructions can be correctly
selected.
DeltaFile
+256-0llvm/test/CodeGen/AMDGPU/fneg-fabs-v2f32.ll
+17-6llvm/lib/Target/AMDGPU/SIInstructions.td
+4-14llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
+7-5llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+284-254 files

LLVM/project 5d98710llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

[SelectionDAG] Move VSelect sign pattern check from AArch64 to general SelectionDAG (#151840)

For some reason the check is already there, but it bails out. Doing the
transform in SelDAG has no negative effect.
DeltaFile
+1,003-0llvm/test/CodeGen/X86/cmp-select-sign.ll
+0-30llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+7-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+1,010-323 files

LLVM/project d20a3c0llvm/test/tools/dsymutil/X86 module-warnings.test

[dsymutil] Update module-warnings.test to run with both linkers (#195474)

The classic linker emits a combined .debug_macinfo table and warns about
MacroLists it has to drop because no compile unit references them. The
parallel linker emits .debug_macinfo per compile unit, so unreferenced
lists are never emitted and have no corresponding warning.
DeltaFile
+11-3llvm/test/tools/dsymutil/X86/module-warnings.test
+11-31 files

LLVM/project 8a5d5d0clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Use declarative TableGen constraints for overflow flag verification

Replace hand-written C++ verifiers with PredOpTrait-based constraints
(FlagRequiresIntType, HasAtMostOneOfAttrs). Introduce CIR_SaturatableBinaryOp
base class and use append/prepend ODS directives to compose arguments, format,
and traits across the op hierarchy. Fix HasAtMostOneOfAttrsPred to use
accessor methods instead of dollar-sign references. Add Commutative trait
to AddOp and MulOp.
DeltaFile
+49-35clang/include/clang/CIR/Dialect/IR/CIROps.td
+0-39clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+49-742 files

LLVM/project c64084cclang/include/clang/CIR/Dialect/IR CIROps.td

[CIR][NFC] Rename SignBitOp to CIR_SignBitOp

Align with the CIR_ prefix naming convention used by other op
definitions in CIROps.td.
DeltaFile
+1-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+1-11 files

LLVM/project 8db17fallvm/lib/Transforms/Vectorize VPlanAnalysis.h

[VPlan] Remove unused inferScalarTypeForRecipe declaration (NFC). (#194450)

The declaration is not used, remove it.
DeltaFile
+0-2llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
+0-21 files

LLVM/project 34197a9clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Use declarative TableGen constraints for overflow flag verification

Replace hand-written C++ verifiers with PredOpTrait-based constraints
(FlagRequiresIntType, HasAtMostOneOfAttrs). Introduce CIR_SaturatableBinaryOp
base class and use append/prepend ODS directives to compose arguments, format,
and traits across the op hierarchy. Fix HasAtMostOneOfAttrsPred to use
accessor methods instead of dollar-sign references. Add Commutative trait
to AddOp and MulOp.
DeltaFile
+50-35clang/include/clang/CIR/Dialect/IR/CIROps.td
+0-39clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+50-742 files

LLVM/project ea1505allvm/include/llvm/IR Constant.h, llvm/lib/IR Constants.cpp

[NFCI][IR] Add DataLayout pointer to zero and null value related APIs

When the semantics of `ConstantPointerNull` change to represent a semantic null
pointer in the future, a null value won't necessarily be a zero value anymore.
Because of that, the entire LLVM constant infrastructure will need to change. As
a first step, this PR adds an optional data layout pointer to `isNullValue`,
`isZeroValue`, `getNullValue`, and `getZeroValue`. It isn't used yet, since a
null value is still a zero value right now.
DeltaFile
+227-0llvm/unittests/IR/ConstantsTest.cpp
+104-11llvm/lib/IR/Constants.cpp
+20-2llvm/include/llvm/IR/Constant.h
+351-133 files

LLVM/project d1a9dfellvm/include/llvm/IR Constant.h, llvm/lib/IR Constants.cpp

[NFCI][IR] Add DataLayout pointer to zero and null value related APIs

When the semantics of `ConstantPointerNull` change to represent a semantic null
pointer in the future, a null value won't necessarily be a zero value anymore.
Because of that, the entire LLVM constant infrastructure will need to change. As
a first step, this PR adds an optional data layout pointer to `isNullValue`,
`isZeroValue`, `getNullValue`, and `getZeroValue`. It isn't used yet, since a
null value is still a zero value right now.
DeltaFile
+227-0llvm/unittests/IR/ConstantsTest.cpp
+126-11llvm/lib/IR/Constants.cpp
+20-2llvm/include/llvm/IR/Constant.h
+373-133 files

LLVM/project 0555d59clang/test/CodeGen target-data.c, clang/test/CodeGenOpenCL amdgpu-env-amdgcn.cl

Revert "[AMDGPU] Update data layout string to use the new pointer spec about null pointer value" (#195460)

Reverts llvm/llvm-project#194101 since the infrastructure to use that is
not ready such that updating it right now will cause some inconsistency.
DeltaFile
+6-7llvm/lib/TargetParser/TargetDataLayout.cpp
+4-4clang/test/CodeGen/target-data.c
+3-3lld/test/ELF/lto/amdgcn-oses.ll
+1-1lld/test/ELF/lto/r600.ll
+1-1lld/test/ELF/lto/amdgcn.ll
+1-1clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
+16-176 files

LLVM/project f66331ellvm/test/tools/llubi stack_overflow.ll store_dead.ll, llvm/tools/llubi/lib Interpreter.cpp ExecutorBase.cpp

[llubi] Improve diagnostics and add stacktrace (#195449)

This PR improves UB diagnostics by making `reportImmediateUB` return a
temporary streamable object. Stacktrace on UB is also added.
DeltaFile
+40-34llvm/tools/llubi/lib/Interpreter.cpp
+50-13llvm/tools/llubi/lib/ExecutorBase.cpp
+38-21llvm/tools/llubi/lib/Library.cpp
+53-2llvm/tools/llubi/lib/ExecutorBase.h
+11-0llvm/test/tools/llubi/stack_overflow.ll
+3-1llvm/test/tools/llubi/store_dead.ll
+195-7134 files not shown
+277-8340 files

LLVM/project 267e3d3clang/test/CodeGen target-data.c, clang/test/CodeGenOpenCL amdgpu-env-amdgcn.cl

Revert "[AMDGPU] Update data layout string to use the new pointer spec about …"

This reverts commit 1a861970f2ba5a8e0bdc47423a892d5f39a25c05.
DeltaFile
+6-7llvm/lib/TargetParser/TargetDataLayout.cpp
+4-4clang/test/CodeGen/target-data.c
+3-3lld/test/ELF/lto/amdgcn-oses.ll
+1-1lld/test/ELF/lto/r600.ll
+1-1lld/test/ELF/lto/amdgcn.ll
+1-1clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
+16-176 files

LLVM/project 2ce499bllvm/include/llvm/IR Constant.h, llvm/lib/IR Constants.cpp

[NFCI][IR] Add DataLayout pointer to zero and null value related APIs

When the semantics of `ConstantPointerNull` change to represent a semantic null
pointer in the future, a null value won't necessarily be a zero value anymore.
Because of that, the entire LLVM constant infrastructure will need to change. As
a first step, this PR adds an optional data layout pointer to `isNullValue`,
`isZeroValue`, `getNullValue`, and `getZeroValue`. It isn't used yet, since a
null value is still a zero value right now.
DeltaFile
+144-0llvm/unittests/IR/ConstantsTest.cpp
+25-2llvm/include/llvm/IR/Constant.h
+15-3llvm/lib/IR/Constants.cpp
+184-53 files

LLVM/project 7d925b9libcxx/include/__random discard_block_engine.h shuffle_order_engine.h

[libc++] Make __is_seed_sequence a variable template (#195420)

This makes things a bit more readable and improves compile times a bit.
DeltaFile
+4-5libcxx/include/__random/discard_block_engine.h
+4-5libcxx/include/__random/shuffle_order_engine.h
+2-4libcxx/include/__random/is_seed_sequence.h
+2-2libcxx/include/__random/linear_congruential_engine.h
+2-2libcxx/include/__random/mersenne_twister_engine.h
+2-2libcxx/include/__random/independent_bits_engine.h
+16-201 files not shown
+18-227 files

LLVM/project fd51c78clang/lib/AST DeclTemplate.cpp, clang/lib/Sema SemaTemplateDeductionGuide.cpp SemaTemplate.cpp

[clang] fix alias ctad producing function template with no template parameters (#195303)
DeltaFile
+40-43clang/lib/Sema/SemaTemplateDeductionGuide.cpp
+18-9clang/lib/Sema/SemaTemplate.cpp
+9-0clang/lib/AST/DeclTemplate.cpp
+4-3clang/test/SemaCXX/cxx20-ctad-type-alias.cpp
+3-3clang/lib/Sema/SemaInit.cpp
+2-2clang/test/SemaTemplate/deduction-guide.cpp
+76-604 files not shown
+82-6210 files

LLVM/project b506ef0clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, llvm/lib/Analysis ValueTracking.cpp

[ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC)

The method assumes that host chars and target chars have the same width.
Add a CharWidth argument so that it can bail out if the requested char
width differs from the host char width.

Alternatively, the check could be done at call sites, but this is more
error-prone.

In the future, this method will be replaced with a different one that
allows host/target chars to have different widths. The prototype will
be the same except that StringRef is replaced with something that is
byte width agnostic. Adding CharWidth argument now reduces the future
diff.
DeltaFile
+72-31llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
+9-3llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+5-2llvm/lib/Analysis/ValueTracking.cpp
+2-2clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+2-2llvm/lib/Transforms/Utils/AMDGPUEmitPrintf.cpp
+2-2llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp
+92-424 files not shown
+96-4610 files

LLVM/project 3a59b36llvm/include/llvm/IR PatternMatch.h, llvm/lib/Analysis InstructionSimplify.cpp

[IR] Account for byte width in m_PtrAdd

The method has few uses yet, so just pass DL argument to it. The change
follows m_PtrToIntSameSize, and I don't see a better way of delivering
the byte width to the method.
DeltaFile
+19-6llvm/unittests/IR/PatternMatch.cpp
+8-5llvm/include/llvm/IR/PatternMatch.h
+4-3llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+3-2llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+1-1llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+1-1llvm/lib/Analysis/InstructionSimplify.cpp
+36-186 files

LLVM/project 68d0d2bllvm/include/llvm/IR IRBuilder.h, llvm/lib/Transforms/Instrumentation SanitizerCoverage.cpp

[IRBuilder] Add getByteTy and use it in CreatePtrAdd

The change requires DataLayout instance to be available, which, in turn,
requires insertion point to be set. In-tree tests detected only one case
when the function was called without setting an insertion point, it was
changed to create a constant expression directly.
DeltaFile
+22-0llvm/unittests/IR/IRBuilderTest.cpp
+8-2llvm/include/llvm/IR/IRBuilder.h
+2-3llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
+32-53 files

LLVM/project 6950e52clang/lib/CodeGen ItaniumCXXABI.cpp, llvm/include/llvm/IR Constants.h

Use DL in ConstantExpr::getPtrAdd() / ConstantExpr::getInBoundsPtrAdd()
DeltaFile
+9-9llvm/lib/Analysis/ScalarEvolution.cpp
+9-9llvm/include/llvm/IR/Constants.h
+9-0llvm/lib/IR/Constants.cpp
+5-3llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+2-1clang/lib/CodeGen/ItaniumCXXABI.cpp
+2-1llvm/unittests/IR/PatternMatch.cpp
+36-237 files not shown
+43-3013 files