[NFC][LFI] Reduce includes due to c-t impact (#182617)
Removes header includes that don't need to be made at the top-level by
moving transitive dependencies directly into source files and using
forward declarations. Biggest impact is that we no longer include
`MCLFIRewriter.h` in `MCStreamer.h` and `MCAsmParserExtension.h`.
[clang-tidy] Correctly handle array of pointers in misc-const-correctness (#179059)
In arrays of pointers, `misc-const-correctness` check wrongly inspects
whether the array element type was const-qualified, rather than the type
it points to, leading to redundant `const` suggestions. This patch fixes
the problem.
Closes [#178880](https://github.com/llvm/llvm-project/issues/178880)
[Clang][AMDGPU][Docs] Add builtin documentation for AMDGPU builtins
Use the documentation generation infrastructure to document the AMDGPU builtins.
This PR starts with the ABI / Special Register builtins. Documentation for the
remaining builtin categories will be added incrementally in follow-up patches.
[Clang][TableGen] Add documentation generation infrastructure for builtins (#181573)
Add a `-gen-builtin-docs` TableGen backend that generates RST
documentation from builtin definitions, modeled after the existing
attribute documentation system (`-gen-attr-docs`).
The emitter generates per-builtin RST sections grouped by category,
including
prototype rendering with optional named parameters (via `ArgNames`),
target
feature annotations, and documentation content. A mismatch between
`ArgNames`
count and prototype parameter count is a fatal error.
[Clang] Added clang diagnostic when snprintf/vsnprintf uses sizeof(dest) for the len parameter
Closes: [#162366](https://github.com/llvm/llvm-project/issues/162366)
---------
Co-authored-by: Bogdan Zunic <bzunic at cisco.com>
[Clang][AMDGPU][Docs] Add builtin documentation for AMDGPU builtins
Use the documentation generation infrastructure to document the AMDGPU builtins.
This PR starts with the ABI / Special Register builtins. Documentation for the
remaining builtin categories will be added incrementally in follow-up patches.
[Clang][TableGen] Add documentation generation infrastructure for builtins
Add a `-gen-builtin-docs` TableGen backend that generates RST
documentation from builtin definitions, modeled after the existing
attribute documentation system (`-gen-attr-docs`).
The emitter generates per-builtin RST sections grouped by category, including
prototype rendering with optional named parameters (via `ArgNames`), target
feature annotations, and documentation content. A mismatch between `ArgNames`
count and prototype parameter count is a fatal error.
[SlotIndexes] Make IndexListEntry/slot constructor private
This was made public only for some unit tests introduced in
e5e3dccd0741c2cf6e1885f0b6053fcfc6684102 that have now been removed.
Since they have been removed, make the method private to prevent misuse,
remove the warning now that misuse is prevented by visibility, and
remove the description of the destructor given it is redundant with the
code.
[flang-rt] Temporarily disable destructor call in OwningPtr::delete_ptr. (#182635)
This is causing failures in CUF testing, because the device compiler
cannot identify the static stack size for kernels.
[ThinLTO][MemProf] Support remark emission for thin link and use in MemProf (#182570)
Enable optimization remark emission during the ThinLTO thin link phase.
This is useful for global analysis passes like MemProf context
disambiguation which operate on the summary index and may need to
report diagnostics before any IR modules are available.
Key changes:
- Create a dummy function ("thinlto_remark_dummy") in a private Module
within the LTO class to provide the necessary Function context for
OptimizationRemarkEmitter.
- Update MemProfContextDisambiguation to use a callback for remark
emission, allowing it to report hinted sizes and other diagnostics
during the thin link.
- Ensure the dummy module and function are safely cleaned up at the end
of the LTO session via the LTO::cleanup mechanism.
[RISCV] Remove srl from (srl (and X, (1 << C)), C) used as czero.eqz/nez condition. (#182598)
(setne (and X, 1 << C), 0) is canonicalized to (srl (and X, (1 << C)),
C).
If this is later used as a czero.eqz/nez condition, we can remove
the srl if the and can be represented as an ANDI.
[HLSL] Enable `-Wconversion`, `-Wvector-conversion`, and `-Wmatrix-conversion` warnings for HLSL by default (#182607)
Fixes #180038 by enabling `-Wconversion`, `-Wvector-conversion`, and
`-Wmatrix-conversion` warnings for HLSL by default, both in the HLSL
clang driver and when fixing up clang invocations under HLSL in
CompilerInvocation.cpp (so that they are enabled even with clang -cc1).
This PR also updates existing tests to expect warnings that weren't
expected before, and removes the `-Wconversion` flags from existing HLSL
tests since it is now redundant due to being enabled by default.
Note that no existing HLSL tests use or exercise `-Wvector-conversion`
or `-Wmatrix-conversion`.
[AMDGPU] Use a general form of intrinsic for tensor load/store (#182334)
The intrinsic has five arguments for the tensor descriptor (D#), while the fifth one is reserved for future targets, and it will be silently ignored in codegen for gfx1250.
For tensor up to 2D, only the first two D# groups are meaningful and the rest should be zero-initialized.
[Hexagon] Handle subreg copies between DoubleRegs and IntRegs (#181360)
ISel can generate truncating COPYs from DoubleRegs to IntRegs when a
64-bit result (e.g., C2_mask) is used in a 32-bit context. Several
passes crashed on this pattern:
BitTracker asserted WD >= WS for COPY instructions. Handle the WD < WS
case by extracting the low WD bits from the source.
HexagonInstrInfo::copyPhysReg had no case for IntRegs <- DoubleRegs or
DoubleRegs <- IntRegs. Add both directions, respecting the subreg index
on the operand (isub_lo/isub_hi) when present.
HexagonTfrCleanup asserted that source and destination register sizes
match. Replace with proper subreg resolution on both operands and a
hasNoVRegs() guard since the pass runs post-RA.
HexagonGenMux asserted no subregs on physical register operands.
Preserve subreg information when building mux instructions and resolve
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