LLVM/project fddc2c0llvm/lib/Transforms/Utils SimplifyCFG.cpp, llvm/test/Transforms/SimplifyCFG dup-preds.ll switch-dup-bbs.ll

[SimplifyCFG] Simplify identical predecessors (#173022)

When >1 predecessors of BB are identical, try to merge them into ONE.


---

Here is a simplified example (`sink` and `bb*`s share the same
predecessor `entry`, hindering the existing uncond br folding to
optimize such a case):
```diff
- entry:
-   switch to %br1, %br2, %br3, %sink
- bb1:
-   br label %sink
- bb2:
-   br label %sink
- bb3:
-   br label %sink

    [25 lines not shown]
DeltaFile
+192-107llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+108-0llvm/test/Transforms/SimplifyCFG/dup-preds.ll
+4-6llvm/test/Transforms/SimplifyCFG/switch-dup-bbs.ll
+304-1133 files

LLVM/project acc2285libclc/clc/lib/generic/math clc_logb.inc clc_logb.cl

libclc: Update logb implementation (#185881)

Similar to the previous logb change, use a common
bithacking free implementation.
DeltaFile
+10-44libclc/clc/lib/generic/math/clc_logb.inc
+9-5libclc/clc/lib/generic/math/clc_logb.cl
+19-492 files

LLVM/project 3252fe7libclc/clc/lib/generic/math clc_log_base.h

libclc: Update f64 log implementations

The log implementation was originally ported from
rocm device libs way back in 44b6117dfde30d6cc292fabca8ecb0cef4657f7a.
Update this to a version derived from the latest. Leaves the float and
half cases alone.
DeltaFile
+39-112libclc/clc/lib/generic/math/clc_log_base.h
+39-1121 files

LLVM/project 3218d11libclc/clc/include/clc/math clc_ep.inc clc_ep.h, libclc/clc/lib/generic CMakeLists.txt

libclc: Add ep utility

Add utility for compensated arithmetic, which should be used
by a number of the large functions.
DeltaFile
+391-0libclc/clc/lib/generic/math/clc_ep.inc
+131-0libclc/clc/include/clc/math/clc_ep.inc
+34-0libclc/clc/lib/generic/math/clc_ep.cl
+21-0libclc/clc/include/clc/math/clc_ep.h
+1-0libclc/clc/lib/generic/CMakeLists.txt
+578-05 files

LLVM/project da1ee22libclc/clc/lib/generic/math clc_hypot.cl

libclc: Fix hypot build

Bad merge lost the new include
DeltaFile
+1-0libclc/clc/lib/generic/math/clc_hypot.cl
+1-01 files

LLVM/project 5365c57libclc/clc/lib/generic/math clc_ilogb.inc clc_ilogb.cl

libclc: Update ilogb implementation (#185877)

This was originally ported from rocm device libs in
d6d0454231ac489c50465d608ddf3f5d900e1535. Update for
more recent changes that were made there. This avoids
bithacking and improves value tracking. This also allows
using a common code path for all types.
DeltaFile
+7-69libclc/clc/lib/generic/math/clc_ilogb.inc
+9-5libclc/clc/lib/generic/math/clc_ilogb.cl
+1-1libclc/clc/lib/generic/math/clc_hypot.cl
+17-753 files

LLVM/project 77fa3d3libclc/clc/lib/generic/math clc_logb.inc clc_logb.cl

libclc: Update logb implementation

Similar to the previous logb change, use a common
bithacking free implementation.
DeltaFile
+10-44libclc/clc/lib/generic/math/clc_logb.inc
+9-5libclc/clc/lib/generic/math/clc_logb.cl
+19-492 files

LLVM/project cfbda41libclc/clc/lib/generic/math clc_ilogb.inc clc_ilogb.cl

libclc: Update ilogb implementation

This was originally ported from rocm device libs in
d6d0454231ac489c50465d608ddf3f5d900e1535. Update for
more recent changes that were made there. This avoids
bithacking and improves value tracking. This also allows
using a common code path for all types.
DeltaFile
+7-69libclc/clc/lib/generic/math/clc_ilogb.inc
+9-5libclc/clc/lib/generic/math/clc_ilogb.cl
+1-1libclc/clc/lib/generic/math/clc_hypot.cl
+17-753 files

LLVM/project 3da14eelibclc/clc/lib/generic/math clc_hypot.inc clc_hypot.cl

libclc: Update hypot implementation (#185873)

This avoids bithacking on the values and improves value
tracking.
DeltaFile
+30-67libclc/clc/lib/generic/math/clc_hypot.inc
+12-10libclc/clc/lib/generic/math/clc_hypot.cl
+42-772 files

LLVM/project 7cb3005clang/test/CodeGenCUDA amdgpu-workgroup-size.cu builtins-amdgcn.cu, clang/test/CodeGenOpenCL builtins-amdgcn-workgroup-size.cl

AMDGPU: Add dereferenceable attribute to dispatch ptr intrinsic (#185955)

Stop manually setting it on the callsite in clang.
DeltaFile
+24-24clang/test/CodeGenOpenCL/builtins-amdgcn-workgroup-size.cl
+14-8llvm/test/Assembler/amdgcn-intrinsic-attributes.ll
+5-5llvm/test/CodeGen/AMDGPU/implicit-arg-block-count.ll
+3-3clang/test/Headers/gpuintrin.c
+3-3clang/test/CodeGenCUDA/amdgpu-workgroup-size.cu
+3-3clang/test/CodeGenCUDA/builtins-amdgcn.cu
+52-465 files not shown
+58-5511 files

LLVM/project 763de90llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp, llvm/test/MC/RISCV/rvv zvlsseg-invalid.s

[RISCV] Add register group overlap checks to the assembler for vector indexed segment load (#184963)

https://github.com/llvm/llvm-project/commit/f7ca74f600cb6360b4255fc849ac21dd13a56a4c
has added basic check for register overlap.
Furthermore, we need to add extra check for register group overlap since
more registers will be occupied in segment load.
DeltaFile
+72-1llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+28-0llvm/test/MC/RISCV/rvv/zvlsseg-invalid.s
+100-12 files

LLVM/project 9ca9ca3llvm/utils/TableGen MacroFusionPredicatorEmitter.cpp

[MacroFusion] Add [[maybe_unused]] to suppress some warings (#185833)
DeltaFile
+2-2llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
+2-21 files

LLVM/project aa16859libclc/clc/lib/amdgpu/address_space clc_qualifier.inc clc_qualifier.cl

[libclc][amdgpu] Add clc qualifier functions with non-const pointer (#186015)

Fix unresolved external functions: _Z15__clc_get_fencePv,
_Z15__clc_to_globalPv, _Z14__clc_to_localPv, _Z16__clc_to_privatePv
DeltaFile
+32-0libclc/clc/lib/amdgpu/address_space/clc_qualifier.inc
+6-21libclc/clc/lib/amdgpu/address_space/clc_qualifier.cl
+38-212 files

LLVM/project 1b20c9cllvm/include/llvm/Frontend/OpenMP OMPKinds.def, offload/include/Shared Environment.h

Address review comments
DeltaFile
+15-17offload/plugins-nextgen/common/src/PluginInterface.cpp
+9-0openmp/device/src/State.cpp
+5-2offload/plugins-nextgen/amdgpu/src/rtl.cpp
+0-3offload/plugins-nextgen/common/include/PluginInterface.h
+1-1offload/include/Shared/Environment.h
+1-1llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
+31-246 files

LLVM/project 7265d89libclc/clc/include/clc/math clc_frexp_exp.h, libclc/clc/include/clc/shared unary_decl_with_int_return.inc

libclc: Add frexp_exp utility function (#185872)
DeltaFile
+22-0libclc/clc/include/clc/math/clc_frexp_exp.h
+13-0libclc/clc/lib/generic/math/clc_frexp_exp.inc
+13-0libclc/clc/lib/generic/math/clc_frexp_exp.cl
+9-0libclc/clc/include/clc/shared/unary_decl_with_int_return.inc
+1-0libclc/clc/lib/generic/CMakeLists.txt
+58-05 files

LLVM/project abd8f45clang/test/ClangScanDeps modules-symlink-dir-from-module-incremental.c

[Clang][Test] Mark modules-symlink-dir test as unsupported on AIX. (#184988)

This change marks the test
`modules-symlink-dir-from-module-incremental.c` as "unsupported" on AIX.
The test relies on the -F flag to specify framework search paths, which
is a driver feature exclusive to Darwin, and it is not supported on the
AIX target.

Co-authored-by: Aditya Chaudhary <aditya.chaudhary1 at ibm.com>
DeltaFile
+3-0clang/test/ClangScanDeps/modules-symlink-dir-from-module-incremental.c
+3-01 files

LLVM/project bd51811llvm/lib/Target/AMDGPU SIISelLowering.cpp

Add compiler warning
DeltaFile
+13-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+13-31 files

LLVM/project 2f8c731llvm/test/CodeGen/X86 sse-minmax-unsafe.ll avx512-unsafe-fp-math.ll

[X86] Remove `NoSignedZerosFPMath` uses (#163902)

Remove `NoSignedZerosFPMath` uses, one of flags in `resetTargetOptions`,
users should use `nsz` instead.
DeltaFile
+420-135llvm/test/CodeGen/X86/sse-minmax-unsafe.ll
+149-43llvm/test/CodeGen/X86/avx512-unsafe-fp-math.ll
+121-68llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll
+104-55llvm/test/CodeGen/X86/avx512fp16-unsafe-fp-math.ll
+38-38llvm/test/CodeGen/X86/machine-combiner.ll
+18-18llvm/test/CodeGen/X86/avx512fp16-machine-combiner.ll
+850-3577 files not shown
+914-42713 files

LLVM/project 65d0ef4clang/lib/CIR/CodeGen TargetInfo.cpp CIRGenModule.cpp, clang/test/CIR/CodeGenHIP simple.cpp

[CIR][AMDGPU] Add AMDGPU target support to CIR CodeGen (#185819)

This PR adds AMDGPUTargetCIRGenInfo and AMDGPUABIInfo to handle the
amdgcn triple in CIR code generation, along with a
basic HIP codegen test.
DeltaFile
+89-0clang/test/CIR/CodeGenHIP/simple.cpp
+20-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+4-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+3-0clang/lib/CIR/CodeGen/TargetInfo.h
+116-04 files

LLVM/project 24be73bclang/test/CodeGen attr-target-clones-ppc.c

test all supported CPUs
DeltaFile
+13-2clang/test/CodeGen/attr-target-clones-ppc.c
+13-21 files

LLVM/project 2cfce29clang/test/Sema attr-target-clones-ppc.c

fix test
DeltaFile
+3-1clang/test/Sema/attr-target-clones-ppc.c
+3-11 files

LLVM/project 3b7e5b9clang/lib/Sema SemaPPC.cpp

create PPCTargetInfo::isTargetClonesSupportedCPU to filter out unsupported CPUs during Sema
DeltaFile
+6-3clang/lib/Sema/SemaPPC.cpp
+6-31 files

LLVM/project 5b1eed6clang/lib/CodeGen CGException.cpp, clang/test/CodeGen windows-seh-arg-capture-crash.cpp

[WinEH] Fix crash when aligning parameters larger than ABI (#180905)

Fix #180648 caused by an unhandled `Argument` for parameters exceeding
ABI size limits. This patch explicitly emits an `alloca` for the `Argument` in 
the entry block to ensure correct address resolution.
DeltaFile
+56-0clang/test/CodeGen/windows-seh-arg-capture-crash.cpp
+27-7clang/lib/CodeGen/CGException.cpp
+83-72 files

LLVM/project 0535075llvm/lib/Target/RISCV RISCVInstrInfoP.td RISCVInstrInfo.td

[RISCV] Use PatGprImm for riscv_psslai. NFC (#185996)

Relax PatGprImm to allow any SDPatternOperator insead of ImmLeaf.
DeltaFile
+2-4llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+1-1llvm/lib/Target/RISCV/RISCVInstrInfo.td
+3-52 files

LLVM/project 0e314eflldb/tools/lldb-fuzzer/lldb-commandinterpreter-fuzzer lldb-commandinterpreter-fuzzer.cpp, lldb/tools/lldb-fuzzer/lldb-target-fuzzer lldb-target-fuzzer.cpp

[LLDB] Ensure plugins are destroyed at end of fuzz tests (#186012)
DeltaFile
+22-0lldb/tools/lldb-fuzzer/utils/SBDebuggerContextManager.h
+5-5lldb/tools/lldb-fuzzer/lldb-commandinterpreter-fuzzer/lldb-commandinterpreter-fuzzer.cpp
+3-5lldb/tools/lldb-fuzzer/lldb-target-fuzzer/lldb-target-fuzzer.cpp
+30-103 files

LLVM/project 0e45e69clang/test/Layout ms-x86-bitfields-overflow.c

[Clang][layout] Update tests after #182792 (#186019)

\#182792 makes it so that these structs have an alignment of 1. This
needs to be fixed in a recently added test (landed after the most recent
premerge run of the test).

This test update is expected behavior.
DeltaFile
+2-2clang/test/Layout/ms-x86-bitfields-overflow.c
+2-21 files

LLVM/project 3ca069cllvm/include/llvm/CodeGen BasicTTIImpl.h, llvm/test/Analysis/CostModel/AArch64 fshl.ll fshr.ll

[CodeGen][TTI] Reduce funnel shift cost for constant shift amounts (#184942)

The Sub instruction cost and the shift-by-zero handling costs (ICmp +
Select) are only needed when the shift amount is non-constant. Move them
inside the `!OpInfoZ.isConstant()` guard to avoid overestimating cost
for constant shift amounts.

The overestimated scalar cost caused SLP vectorizer to incorrectly
prefer vectorizing funnel shifts with constant shift amounts, since SLP
compares vector cost against scalar cost and a falsely high scalar cost
makes vectorization appear more profitable than it actually is.

Fixes #181308.
DeltaFile
+405-440llvm/test/Analysis/CostModel/X86/fshl.ll
+405-440llvm/test/Analysis/CostModel/X86/fshr.ll
+95-0llvm/test/Transforms/SLPVectorizer/RISCV/funnel-shift-cost.ll
+16-15llvm/include/llvm/CodeGen/BasicTTIImpl.h
+15-15llvm/test/Analysis/CostModel/AArch64/fshl.ll
+15-15llvm/test/Analysis/CostModel/AArch64/fshr.ll
+951-9251 files not shown
+961-9357 files

LLVM/project 0b332dellvm/lib/Target/RISCV RISCVSchedAndes45.td, llvm/test/tools/llvm-mca/RISCV/Andes45 rvv-permutation.s rvv-fp.s

[RISCV] Update Andes45 vector permutation scheduling info (#185591)

This PR adds latency/throughput for all RVV permutation instructions to
the andes45 series scheduling model.

We use the default cycle for permutation instructions since we are
unable to model the Latency and ReleaseAtCycles accurately now.
DeltaFile
+343-343llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s
+41-22llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+30-30llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fp.s
+414-3953 files

LLVM/project b72a812clang-tools-extra/clang-tidy/modernize UseTrailingReturnTypeCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix spurious errors from builtin macros in modernize-use-trailing-return-type (#184022)

## Summary

I hit the same issue as in #168360 when upgrading to LLVM 21 with
clang-tidy reporting cryptic:

`error: missing '(' after '__has_feature'`

Further investigation confirmed that the issue is localized to
`modernize-use-trailing-return-type` and only happens with C++20+ and llvm
21 system headers (where `__has_feature` started to be used by libc++).
Initial non-localized repro had this error firing 7k+ on LLVM 21, but
when I switched to HEAD the incidence dropped to just 5 'check()' calls
firing. The drop in incidence is likely to be related to 
https://github.com/llvm/llvm-project/pull/151035 as there are no other 
plausibly relevant changes.

However, as I was still hitting the issue with HEAD, this helped develop

    [20 lines not shown]
DeltaFile
+11-0clang-tools-extra/test/clang-tidy/checkers/modernize/use-trailing-return-type.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+1-3clang-tools-extra/clang-tidy/modernize/UseTrailingReturnTypeCheck.cpp
+17-33 files

LLVM/project da3efc7clang/lib/AST RecordLayoutBuilder.cpp, clang/test/CodeGen ms_struct-packed.c ms_struct-bitfield.c

Fix packed being ignored on ms_struct bitfields (#182792)

For ms_struct structs on Itanium layout targets, the packed attribute is
ignored on bit-fields (2014 commit
76e1818a2b1248579557de2927c135c322577c82), mismatching the GCC behavior.
Remove the `!IsMsStruct` guard to fix it.
DeltaFile
+18-0clang/test/CodeGen/ms_struct-packed.c
+2-2clang/test/CodeGen/ms_struct-bitfield.c
+1-1clang/lib/AST/RecordLayoutBuilder.cpp
+21-33 files