[AArch64] Fix miscompilation due to integer overflow in immediate offset for stack store/load instructions with preserve_all (#207026)
Fix AArch64 framelowering bug exposed by a preserve_all function that
spills 30+ callee-saved registers: paired stp/ldp offsets overflows the
signed 7-bit immediate, fixed by spilling those registers as single
str/ldr instead.
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Fixes #204564
[analyzer] Fix invalid HTML nesting for popups at end of line (#207793)
The static analyzer's HTML reports contain misnested tags whenever a
variable with a `variable_popup` is the last token on a source line.
`AddLineNumber` inserts the row-closing `</td></tr>` with `InsertTextBefore`, which
places it in front of text previously inserted at the same offset. As a result,
the popup's closing `</table></span>` tags and the arrow anchor `</span>`
tags end up outside the table row. HTML parsers (jsoup, pup) and validators
reject the file from that point on.
Before:
<span class='variable'>b</td></tr><table
class='variable_popup'>...</table></span></span></span>
<img width="786" height="414" alt="image"
src="https://github.com/user-attachments/assets/023461ad-73e4-424e-a4fb-42faf7a945f0"
/>
[28 lines not shown]
[analyzer] Prevent inlining RAII ctors/dtors (#208729)
BlockInCriticalSectionChecker registers the pre-call for the RAII ctors
and Dtors - and also the raw 'lock' and 'unlock' handlers.
However, pre-call does not prevent inlining. This means that (in the
likely case of) that the body is present, the analyzer will model the
effect of the lock twice. This happens on libc++ unique_lock.
We really should have eval-called the ctor/dtor to avoid the inlining of
those, but here we are.
rdar://175814310
[AArch64][GlobalISel] Extend handling to bf16 vecreduce. (#208684)
This alters the extension of f16 vecreduce to bf16, allowing us to
handle the non-strict fadd and fmul reductions, along with fmin and fmax
variants.
[LLDB] Support Auxiliary library in ELF format
An ELF filter library (DT_FILTER) or auxiliary filter (DT_AUXILIARY)
delegates symbol resolution to its filtee: the dynamic linker looks up
each symbol in the filtee first, falling back to the filter library's
own definition. Filter library may export placeholder smyolbs whose
addresses are not the actual function entry points.
To support this, we teach ObjectFileELF to parse the filtee and model
placeholder function definition in filter libraries as ReExported,
reusing the existing re-export machinery.
[GlobalISel] Improve bf16 converts with fast-math flags. (#200741)
This alters the lowering of bf16 G_TRUNC to exclude the check for nan if
the operation being extended is nnan. Flags are then threaded through so
that the G_FPEXT and G_FPTRUNC from promoted nodes keep the same FMF.
[StackColoring] Change TotalStackSize from unsigned to int64_t (#208671)
StackColoring tracks the total size of the stack as `unsigned int`. This
will wrap around, even on 64-bit systems, if the stack is greater than
that resulting in a wrong size. This can happen on both PPC and RISCV64.
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (12)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (13)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (9)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (10)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (11)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (8)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (7) (#208836)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (6) (#208835)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (5) (#208834)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
[clang-tidy] Support parentheses around subscript operators in readability-redundant-parentheses (#208759)
Subscript operators have the same operator procedure as function calls.
Treat overloaded `()` as built-in operators as a drive-by. I missed this
case when reviewing #192254.
Reject auto combined with type specifiers in C++ (#208552)
Follow-up of https://github.com/llvm/llvm-project/pull/166004
- Diagnose C++ declarations that combine `auto` with another type
specifier, such as `auto int` .
- Preserve C/C23 handling where `auto` can still be interpreted as a
storage-class specifier in valid combinations.
- Fix parser disambiguation so `auto Use = 0` treats `Use` as the
declarator name before type lookup, avoiding ambiguous lookup
regressions.
---------
Signed-off-by: Osama Abdelkader <osama.abdelkader at gmail.com>
[ARM] Use .reloc for weak symbols in PIC mode instead of GOT indirection (#208372)
In ARM ELF PIC mode, weak symbols referenced via the constant pool use a
PC-relative expression like `.long sym-(.LPC+8)`. The assembler eagerly
resolves this when both the symbol and reference are in the same
section, which prevents the linker from overriding a weak definition
with a strong one from another object file.
The previous approach (#198577) forced weak symbols to go through GOT
indirection to avoid this, but that adds an extra load. This patch
instead emits a `.reloc` directive alongside the local PC-relative
expression, forcing the assembler to emit a proper `R_ARM_REL32`
relocation. This lets the linker perform the override without the
runtime cost of a GOT load.
[LLDB] Detect Memory overlapping between AllocateMemory and MemoryInfo
IRMemoryMap estimates a free address range using memory information.
However, the memory returns by AllocateMemory can overlap with the
ranges reported by MemoryInfo (internally backed by PT_VM_ENTRY),
because the kernel is unaware of allocations made during the probing
process.
As a result, two allocatios may silently insert duplicate key for
different objects, leading to intermittent test failure. The issue is
nodeterministic because it depends on the underlying malloc
implementation and ASLR.
Fix this by detecting overlapping allocations after AllocateMemory. If
an overlap is found, fall back to the address-guessing path, which
perform the necessary overlap checks before committing the allocation.
Also, return and print message in IRInterpreter in unsecessful allocation.
[clang][test] Fix emulated-tls.cpp failure on LoongArch (#208886)
The LoongArch backend does not support emulated TLS, so
mark the test as unsupported to fix the LoongArch buildbot
failure.
Failure: https://lab.llvm.org/staging/#/builders/20/builds/28875
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
A TBL with out-of-range values will place zero into the respective
vector lane. Use this to generate a more efficient 1 operand TBL where
possible.
[OpenMP][Offload] Fix flang offload test (#208829)
This PR attempts to address the remaining flang offload test failure
after https://github.com/llvm/llvm-project/pull/208617. Bot:
https://lab.llvm.org/buildbot/#/builders/67/builds/8412
The problem with is test is that `foo__l8` kernel was not linked into
device image without explicitly use the amdgpu-amd-amdhsa triple in the
compilation. It only happened to this specific test.
Local test results after fix:
```
Testing Time: 146.44s
Total Discovered Tests: 3478
Skipped : 77 (2.21%)
Unsupported : 341 (9.80%)
Passed : 3055 (87.84%)
Expectedly Failed: 5 (0.14%)
```
[GlobalISel][AArch64] Improve legalization of shift amounts (#208676)
Fixes crashes when the shift amount type is already between s32 and s64,
but not s32 or s64.
The shift amount should have the same type with the shifted value for
the shift instructions, so add the same `widenScalarToNextPow2`
legalization that we apply to the shifted value, to the shift amount.
Fixes crashes in programs like:
define i8 @test(i48 %a) {
entry:
%b = lshr i48 %a, 15
%c = trunc i48 %b to i8
ret i8 %c
}
The new test crashes before this PR.
[orc-rt] Hold log level names as uppercase (#208880)
orc_rt_log_Level_getName is used primarily in text prefixes (e.g. the
upcoming printf backend's "[orc-rt:General:LEVEL]"), where uppercase is
the intended rendering. Storing the names as uppercase lets the backend
use them directly without case conversion. orc_rt_log_Level_parse
performs a case-insensitive parse, so ORC_RT_LOG=info and similar still
work.
[orc-rt] Hold log level names as uppercase.
orc_rt_log_Level_getName is expected to be primarily used in
text-prefixes (e.g. in the upcoming printf backend), where it should be
printed as uppercase. Storing as uppercase in the first place will save
us a toupper conversion on each log call.
