LLVM/project a3ab110llvm/utils/TableGen/Common CodeGenTarget.cpp

[TableGen] Silence a warning (NFC)

/llvm-project/llvm/utils/TableGen/Common/CodeGenTarget.cpp:286:12:
 error: variable 'SkippedInsts' set but not used [-Werror,-Wunused-but-set-variable]
  unsigned SkippedInsts = 0;
           ^
1 error generated.
DeltaFile
+1-1llvm/utils/TableGen/Common/CodeGenTarget.cpp
+1-11 files

LLVM/project 719c41amlir/include/mlir/Pass Pass.h, mlir/lib/Pass Pass.cpp

[mlir][Pass] Fix crash when applying a pass to an optional interface
DeltaFile
+33-1mlir/test/Dialect/Transform/test-pass-application.mlir
+8-0mlir/include/mlir/Pass/Pass.h
+3-3mlir/lib/Pass/Pass.cpp
+1-1mlir/test/Pass/pipeline-invalid.mlir
+45-54 files

LLVM/project 961940ellvm/include/llvm/Analysis TargetTransformInfo.h, llvm/include/llvm/CodeGen BasicTTIImpl.h

[TTI] Use MemIntrinsicCostAttributes for getMaskedMemoryOpCost (#168029)

- Split from #165532. This is a step toward a unified interface for
masked/gather-scatter/strided/expand-compress cost modeling.
- Replace the ad-hoc parameter list with a single attributes object.

API change:
```
- InstructionCost getMaskedMemoryOpCost(Opcode, Src, Alignment,
-                                       AddressSpace, CostKind);

+ InstructionCost getMaskedMemoryOpCost(MemIntrinsicCostAttributes,
+                                       CostKind);
```
Notes:
- NFCI intended: callers populate MemIntrinsicCostAttributes with the
same information as before.
- Follow-up: migrate gather/scatter, strided, and expand/compress cost
queries to the same attributes-based entry point.
DeltaFile
+27-1llvm/include/llvm/Analysis/TargetTransformInfo.h
+14-10llvm/include/llvm/CodeGen/BasicTTIImpl.h
+13-6llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+10-7llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+8-6llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+8-4llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+80-3411 files not shown
+107-6217 files

LLVM/project 54f9084clang/lib/CodeGen BackendUtil.cpp, llvm/include/llvm/Transforms/Instrumentation BoundsChecking.h

fmt

Created using spr 1.3.7
DeltaFile
+2-2clang/lib/CodeGen/BackendUtil.cpp
+2-1llvm/include/llvm/Transforms/Instrumentation/BoundsChecking.h
+4-32 files

LLVM/project 676ae65clang/include/clang/Basic CodeGenOptions.def, clang/include/clang/Options Options.td

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+19-0compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+6-0clang/lib/Driver/SanitizerArgs.cpp
+5-0clang/include/clang/Options/Options.td
+5-0clang/test/Driver/fsanitize.c
+2-0clang/include/clang/Basic/CodeGenOptions.def
+1-0compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
+38-01 files not shown
+39-07 files

LLVM/project f9f9aa7clang/lib/CodeGen CGExpr.cpp, clang/test/CodeGen cfi-icall-trap-recover-runtime.c

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+36-0clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
+24-0clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
+19-0compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+16-0llvm/test/Instrumentation/BoundsChecking/runtimes.ll
+10-0llvm/lib/Passes/PassBuilder.cpp
+7-0clang/lib/CodeGen/CGExpr.cpp
+112-010 files not shown
+148-316 files

LLVM/project de10972clang/include/clang/Basic CodeGenOptions.def, clang/include/clang/Driver SanitizerArgs.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+19-0compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+6-0clang/lib/Driver/SanitizerArgs.cpp
+5-0clang/test/Driver/fsanitize.c
+5-0clang/include/clang/Options/Options.td
+2-0clang/include/clang/Basic/CodeGenOptions.def
+1-0clang/include/clang/Driver/SanitizerArgs.h
+38-01 files not shown
+39-07 files

LLVM/project a5fb057compiler-rt/lib/ubsan_minimal ubsan_minimal_handlers.cpp, compiler-rt/test/ubsan_minimal/TestCases test-darwin-interface.c

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+19-0compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+1-0compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
+20-02 files

LLVM/project 6a57e2dcompiler-rt/lib/ubsan_minimal ubsan_minimal_handlers.cpp, compiler-rt/test/ubsan_minimal/TestCases test-darwin-interface.c

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+19-0compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
+1-0compiler-rt/test/ubsan_minimal/TestCases/test-darwin-interface.c
+20-02 files

LLVM/project bfb9539llvm/include/llvm/Target Target.td, llvm/test/TableGen target-specialized-pseudos.td

TableGen: Support target specialized pseudoinstructions (#159880)

Allow a target to steal the definition of a generic pseudoinstruction
and remap the operands. This works by defining a new instruction, which
will simply swap out the emitted entry in the InstrInfo table.

This is intended to eliminate the C++ half of the implementation
of PointerLikeRegClass. With RegClassByHwMode, the remaining usecase
for PointerLikeRegClass are the common codegen pseudoinstructions.
Every target maintains its own copy of the generic pseudo operand
definitions anyway, so we can stub out the register operands with
an appropriate class instead of waiting for runtime resolution.

In the future we could probably take this a bit further. For example,
there is a similar problem for ADJCALLSTACKUP/DOWN since they depend
on target register definitions for the stack pointer register.
DeltaFile
+101-0llvm/test/TableGen/target-specialized-pseudos.td
+93-0llvm/include/llvm/Target/Target.td
+37-0llvm/utils/TableGen/InstrInfoEmitter.cpp
+11-1llvm/utils/TableGen/Common/CodeGenTarget.cpp
+242-14 files

LLVM/project 522177cllvm/docs NVPTXUsage.rst, llvm/include/llvm/IR IntrinsicsNVVM.td

[NVPTX] Add a few more missing fence intrinsics (#166352)

This commit adds the below fence intrinsics:

- llvm.nvvm.fence.acquire.sync_restrict.space.cluster.scope.cluster
- llvm.nvvm.fence.release.sync_restrict.space.cta.scope.cluster
- llvm.nvvm.fence.mbarrier_init.release.cluster
-
llvm.nvvm.fence.proxy.async.generic.acquire.sync_restrict.space.cluster.scope.cluster
-
llvm.nvvm.fence.proxy.async.generic.release.sync_restrict.space.cta.scope.cluster
llvm.nvvm.fence.proxy.alias
- llvm.nvvm.fence.proxy.async
- llvm.nvvm.fence.proxy.async.global
- llvm.nvvm.fence.proxy.async.shared_cluster
- llvm.nvvm.fence.proxy.async.shared_cta

For more information, please refere the [PTX
ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-membar)
DeltaFile
+106-0llvm/docs/NVPTXUsage.rst
+45-13llvm/include/llvm/IR/IntrinsicsNVVM.td
+51-0llvm/test/CodeGen/NVPTX/fence-proxy-sm90.ll
+35-0llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+31-0llvm/test/CodeGen/NVPTX/thread-fence.ll
+27-0llvm/test/CodeGen/NVPTX/fence-proxy-sm90-ptx86.ll
+295-133 files not shown
+335-139 files

LLVM/project 9a15556mlir/include/mlir/Dialect/OpenACC/Transforms Passes.td

[OpenACC] add cl::values to ACCImplicitRoutineOptions (#168601)

Add the cl::values to the pass options so an assert is not reached when
trying to generate a reproducer e.g. "unknown data value for option"
DeltaFile
+8-1mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
+8-11 files

LLVM/project 88efd0ellvm/lib/Transforms/IPO LowerTypeTests.cpp, llvm/test/Transforms/LowerTypeTests function-weak.ll

[LTT] Mark as unkown weak function tests. (#167399)

We don't have enough information to infer the probability of a weak function pointer being nullptr or not (open question if we could propagate this from the linker)

Issue #147390
DeltaFile
+3-2llvm/test/Transforms/LowerTypeTests/function-weak.ll
+3-0llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+6-22 files

LLVM/project 232a96dllvm/include/llvm/MC MCInstrDesc.h, llvm/include/llvm/Target Target.td

CodeGen: Remove PointerLikeRegClass handling from codegen

All uses have been migrated to RegClassByHwMode. This is now
an implementation detail of InstrInfoEmitter for pseudoinstructions.
DeltaFile
+13-13llvm/include/llvm/Target/Target.td
+1-12llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+1-12llvm/include/llvm/MC/MCInstrDesc.h
+1-5llvm/utils/TableGen/InstrInfoEmitter.cpp
+0-4llvm/lib/CodeGen/TargetInstrInfo.cpp
+0-3llvm/utils/TableGen/Common/InstructionEncoding.cpp
+16-492 files not shown
+17-518 files

LLVM/project fed007cllvm/test/TableGen target-specialized-pseudos.td RegClassByHwMode.td, llvm/utils/TableGen InstrInfoEmitter.cpp

CodeGen: Make target overrides of PointerLikeRegClass mandatory

Most targets should now use the convenience multiclass to fixup
the operand definitions of pointer-using pseudoinstructions:

defm : RemapAllTargetPseudoPointerOperands<target_ptr_regclass>;
DeltaFile
+26-8llvm/test/TableGen/target-specialized-pseudos.td
+15-3llvm/utils/TableGen/InstrInfoEmitter.cpp
+14-1llvm/test/TableGen/RegClassByHwMode.td
+2-0llvm/test/TableGen/get-operand-type.td
+2-0llvm/test/TableGen/get-operand-type-no-expand.td
+2-0llvm/test/TableGen/def-multiple-operands.td
+61-122 files not shown
+64-128 files

LLVM/project ccf4a7dllvm/lib/Target/AMDGPU R600.td SIInstructions.td, llvm/lib/Target/ARM ARM.td

CodeGen: Make all targets override pseudos with pointers

This eliminates the need to have PointerLikeRegClass handling in
codegen.
DeltaFile
+12-9llvm/lib/Target/AMDGPU/R600.td
+11-0llvm/lib/Target/AMDGPU/SIInstructions.td
+10-0llvm/lib/Target/NVPTX/NVPTX.td
+8-0llvm/lib/Target/ARM/ARM.td
+8-0llvm/lib/Target/WebAssembly/WebAssembly.td
+3-1llvm/lib/Target/SystemZ/SystemZ.td
+52-1020 files not shown
+94-1026 files

LLVM/project 310569dllvm/include/llvm/Target Target.td, llvm/test/TableGen target-specialized-pseudos.td

TableGen: Support target specialized pseudoinstructions

Allow a target to steal the definition of a generic pseudoinstruction
and remap the operands. This works by defining a new instruction, which
will simply swap out the emitted entry in the InstrInfo table.

This is intended to eliminate the C++ half of the implementation
of PointerLikeRegClass. With RegClassByHwMode, the remaining usecase
for PointerLikeRegClass are the common codegen pseudoinstructions.
Every target maintains its own copy of the generic pseudo operand
definitions anyway, so we can stub out the register operands with
an appropriate class instead of waiting for runtime resolution.

In the future we could probably take this a bit further. For example,
there is a similar problem for ADJCALLSTACKUP/DOWN since they depend
on target register definitions for the stack pointer register.
DeltaFile
+101-0llvm/test/TableGen/target-specialized-pseudos.td
+93-0llvm/include/llvm/Target/Target.td
+37-0llvm/utils/TableGen/InstrInfoEmitter.cpp
+11-1llvm/utils/TableGen/Common/CodeGenTarget.cpp
+242-14 files

LLVM/project c32d2eellvm/utils/TableGen CodeGenMapTable.cpp

[NFC][TableGen] Adopt CodeGenHelpers in CodeGenMapTable (#168592)

Adopt `IfDefEmitter` and `NamespaceEmitter` in CodeGenMapTable.cpp
DeltaFile
+3-5llvm/utils/TableGen/CodeGenMapTable.cpp
+3-51 files

LLVM/project 7819071.github/workflows release-binaries.yml

workflows/release-binaries: Drop install-ninja action (#167070)

ninja is already installed by default on Linux and macOS.
DeltaFile
+0-3.github/workflows/release-binaries.yml
+0-31 files

LLVM/project 7b7cc0dllvm/lib/Target/AMDGPU SIFoldOperands.cpp GCNSubtarget.h

[NFC] Check operand type instead of opcode

A folow-up of #168458.
DeltaFile
+13-21llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+1-1llvm/lib/Target/AMDGPU/GCNSubtarget.h
+14-222 files

LLVM/project 651785autils/bazel/llvm-project-overlay/llvm BUILD.bazel

Fix #168367 (#168635)

DeltaFile
+4-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+4-01 files

LLVM/project 411c752orc-rt/lib/executor TaskDispatcher.cpp ThreadPoolTaskDispatcher.cpp

[orc-rt] Fix typos in file comments.
DeltaFile
+2-2orc-rt/lib/executor/TaskDispatcher.cpp
+2-2orc-rt/lib/executor/ThreadPoolTaskDispatcher.cpp
+4-42 files

LLVM/project 5d9b338utils/bazel/llvm-project-overlay/llvm BUILD.bazel

Fix e47e9f3b7b136f0af549e785896b0584088d0d2c
DeltaFile
+4-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+4-01 files

LLVM/project 62d556elibcxx/utils/libcxx/test/features availability.py

[NFC] [test] [libcxx] Fix invalid escape sequences

```
>>> "_target-has-llvm-21 || target={{.+}}-apple-macosx{{26.[0-9](.\d+)?}}" == r"_target-has-llvm-21 || target={{.+}}-apple-macosx{{26.[0-9](.\\
d+)?}}"
<python-input-6>:1: SyntaxWarning: invalid escape sequence '\d'
True
>>> "_target-has-llvm-20 || target={{.+}}-apple-macosx{{15.[4-9](.\d+)?}}" == r"_target-has-llvm-20 || target={{.+}}-apple-macosx{{15.[4-9](.\\
d+)?}}"
<python-input-7>:1: SyntaxWarning: invalid escape sequence '\d'
True
>>> "_target-has-llvm-19 || target={{.+}}-apple-macosx{{15.[0-3](.\d+)?}}" == r"_target-has-llvm-19 || target={{.+}}-apple-macosx{{15.[0-3](.\\
d+)?}}"
<python-input-8>:1: SyntaxWarning: invalid escape sequence '\d'
True
>>> "_target-has-llvm-18 || target={{.+}}-apple-macosx{{14.[4-9](.\d+)?}}" == r"_target-has-llvm-18 || target={{.+}}-apple-macosx{{14.[4-9](.\\
d+)?}}"
<python-input-9>:1: SyntaxWarning: invalid escape sequence '\d'
```
DeltaFile
+4-4libcxx/utils/libcxx/test/features/availability.py
+4-41 files

LLVM/project 0a96b24flang/include/flang/Optimizer/OpenACC/Support FIROpenACCOpsInterfaces.h, flang/lib/Optimizer/OpenACC/Support FIROpenACCOpsInterfaces.cpp RegisterOpenACCExtensions.cpp

[mlir][acc][flang] Introduce OpenACC interfaces for globals (#168614)

Introduce two new OpenACC operation interfaces for identifying global
variables and their address computations:

- `GlobalVariableOpInterface`: Identifies operations that define global
variables. Provides an `isConstant()` method to query whether the global
is constant.

- `AddressOfGlobalOpInterface`: Identifies operations that compute the
address of a global variable. Provides a `getSymbol()` method to
retrieve the symbol reference.

This is being done in preparation for `ACCImplicitDeclare` pass which
will automatically ensure that `acc declare` is applied to globals when
needed.

The following operations now implement these interfaces:
- `memref::GlobalOp` implements `GlobalVariableOpInterface`

    [2 lines not shown]
DeltaFile
+95-0mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
+31-0mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
+23-0mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+14-0flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
+9-0flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
+3-0flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
+175-01 files not shown
+176-07 files

LLVM/project 1262acfllvm/lib/CodeGen/AsmPrinter DwarfUnit.cpp DwarfUnit.h

Introduce DwarfUnit::addBlock helper method (#168446)

This patch is just a small cleanup that unifies the various spots that
add a DWARF expression to the output.
DeltaFile
+21-65llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+3-0llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
+24-652 files

LLVM/project 5e80358llvm/lib/Target/ARM/MCTargetDesc ARMAsmBackend.cpp, llvm/test/MC/ARM arm-movt-movw-absolute-pass.s

[llvm][ARM] Allow MOVT and MOVW on the offset between two labels (#168072)

In this case, the value is a constant, not an addend to a relocation.
So the "Relocation Not In Range" error must not be triggered.

Regression from PR #112877
Fixes #132322
DeltaFile
+9-0llvm/test/MC/ARM/arm-movt-movw-absolute-pass.s
+1-1llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+10-12 files

LLVM/project 5f66203llvm/include/llvm/CodeGen SDPatternMatch.h

DAG: Reorder SDPatternMatch combinators earlier

Split out from #168288
DeltaFile
+65-65llvm/include/llvm/CodeGen/SDPatternMatch.h
+65-651 files

LLVM/project 3e499e9clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/test/CIR/CodeGen no-common.c

[CIR] Add support for common linkage (#168613)

Add support for marking global variables with common linkage.
DeltaFile
+103-0clang/test/CIR/CodeGen/no-common.c
+12-5clang/lib/CIR/CodeGen/CIRGenModule.cpp
+115-52 files

LLVM/project 6b61559llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/test/CodeGen/AArch64 sve-extract-scalable-vector.ll

DAG: Use poison for some vector result widening
DeltaFile
+216-218llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
+137-137llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
+38-36llvm/test/CodeGen/X86/matrix-multiply.ll
+12-12llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+0-7llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
+403-4105 files