LLVM/project e59a0c6 — orc-rt/include/orc-rt/bedrock Session.h, orc-rt/lib/bedrock Session.cpp

[orc-rt] Pass the reporting Session to Session error reporters. (#226622)

Session error reporters previously received only the Error, and had to
be supplied to the Session constructor, so they had no direct way to
refer to the Session reporting the error (e.g. to include its address in
a log message).

This commit changes ErrorReporterFn to take the reporting Session along
with the Error, and adds a Session::logErrors reporter that logs errors
via ORC_RT_LOG at Error level in the Session category. logErrors is only
available when Error-level logging is compiled in
(ORC_RT_LOG_ENABLED(Error)), so that it can't silently discard errors in
configurations where logging is compiled out. The noErrors and
AccumulateErrors test helpers are updated to work as both plain and
Session error reporters.
DeltaFile
+24-6orc-rt/test/unit/bedrock/SessionTest.cpp
+24-3orc-rt/test/unit/CommonTestUtils.h
+22-2orc-rt/include/orc-rt/bedrock/Session.h
+11-0orc-rt/lib/bedrock/Session.cpp
+1-1orc-rt/tools/ogre/ogre.cpp
+1-1orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
+83-136 files

LLVM/project ab08c75 — bolt/lib/Passes BinaryPasses.cpp ReorderFunctions.cpp, bolt/lib/Profile DataAggregator.cpp

[BOLT] Remove cl::callback uses (#226359)

cl::callback will be removed to enable migration to TableGen based
representation.

https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3

LLM-aided
DeltaFile
+7-8bolt/lib/Passes/ReorderFunctions.cpp
+6-8bolt/lib/Passes/BinaryPasses.cpp
+6-6bolt/lib/Profile/DataAggregator.cpp
+19-223 files

LLVM/project 0b61b73 — clang-tools-extra/clangd/tool ClangdMain.cpp

[clangd] Report retired flags after parsing (#226360)

cl::callback will be removed to enable migration to TableGen

https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3

LLM-aided
DeltaFile
+9-5clang-tools-extra/clangd/tool/ClangdMain.cpp
+9-51 files

LLVM/project 90c150f — clang/tools/clang-format ClangFormat.cpp, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

Replace cl::bits with cl::list. NFC (#226399)

cl::bits packs enum values into an unsigned, which would block migration
to TableGen based representation. The three users only test membership.

LLM-aided
DeltaFile
+11-17llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+3-3llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
+2-2clang/tools/clang-format/ClangFormat.cpp
+16-223 files

LLVM/project 8c697f0 — clang/test/CodeGenHLSL/builtins WaveReadLaneFirst.hlsl, libcxx/test/std/algorithms/alg.modifying.operations/alg.swap pstl.swap_ranges.pass.cpp

Rebase, improvements

Created using spr 1.3.7
DeltaFile
+1,538-1,052llvm/test/CodeGen/AMDGPU/frem.ll
+733-228llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
+389-0llvm/test/Transforms/LoopFusion/guard_skip_empty_block.ll
+187-0libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
+129-15llvm/test/CodeGen/X86/llvm.frexp.ll
+120-0clang/test/CodeGenHLSL/builtins/WaveReadLaneFirst.hlsl
+3,096-1,295147 files not shown
+5,950-1,866153 files

LLVM/project f8c2918 — llvm/test/Transforms/SLPVectorizer/AArch64 ordered-reduction-of-loads.ll, llvm/test/Transforms/SLPVectorizer/RISCV ordered-reduction.ll

[SLP][NFC]Add extra test for reductions vectorization, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/226618
DeltaFile
+77-0llvm/test/Transforms/SLPVectorizer/RISCV/ordered-reduction.ll
+48-0llvm/test/Transforms/SLPVectorizer/AArch64/ordered-reduction-of-loads.ll
+125-02 files

LLVM/project 3a2787d — orc-rt/include/orc-rt-c config.h.in, orc-rt/include/orc-rt-c/support Logging.h

[orc-rt] Move ORC_RT_LOG_ENABLED into config.h. (#226617)

ORC_RT_LOG_ENABLED depends only on the logging configuration values
defined in config.h, but was defined in Logging.h, so checking whether a
log level is compiled in required pulling in the logging backend's
headers (e.g. <os/log.h>).

This commit moves ORC_RT_LOG_ENABLED (and its level-token aliases) into
config.h, so that headers can check the logging configuration without
including Logging.h.
DeltaFile
+32-0orc-rt/include/orc-rt-c/config.h.in
+2-26orc-rt/include/orc-rt-c/support/Logging.h
+34-262 files

LLVM/project 201e76d — llvm/lib/CodeGen DetectDeadLanes.cpp, llvm/test/CodeGen/AMDGPU detect-dead-lanes-reg-sequence-narrow-slot.mir true16-uniform-f16-phi-copysign.ll

[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (#226556)

isCrossCopy() returned early whenever source and destination shared a
register class, treating the transfer as lane-for-lane. That is wrong
when a REG_SEQUENCE names a subregister slot narrower than the source
operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit
vreg. Only take the early exit when the two widths match; otherwise fall
through to findCommonRegClass().

Fixes: ROCM-31212
DeltaFile
+1,538-1,052llvm/test/CodeGen/AMDGPU/frem.ll
+72-0llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
+24-0llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
+13-2llvm/lib/CodeGen/DetectDeadLanes.cpp
+1,647-1,0544 files

LLVM/project eba3a84 — llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU mai-hazards-gfx90a.mir mai-hazards-gfx942.mir

[AMDGPU] Measure MFMA overwrite hazards at each instruction

Apply previously established processing to:
 - VALU overwriting an MFMA result
 - VALU overwriting a register an MFMA took as srcC

AI-assisted.
DeltaFile
+52-54llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+58-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
+51-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
+161-543 files

LLVM/project 93d916b — llvm/lib/Target/AMDGPU GCNHazardRecognizer.h GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU rewrite-vgpr-mfma-to-agpr.ll mai-hazards-gfx942.mir

[AMDGPU] Measure MFMA read hazards at each producer

Introduce more sophisticated traversal to avoid the following traps:
 - order-dependent traversal and discarding seen BBs despite shorter path
 - mis-matching distance and window of different producers

Record the best distance per BB instead of a visited flag and sweep the
arrivals in nondecreasing distance (bucket queue). This pairs producers
with their actual distance to a consumer in one go.

Fixed scenarios:
 - MFMA reading an MFMA result as srcA, srcB or srcC
 - VALU, memory or export instruction reading an MFMA result

rewrite-vgpr-mfma-to-agpr.ll gains an s_nop 2: a 4-pass XDL write that
partially overlaps the srcC read two slots later requires five wait
states, and none were emitted because the nearest producer wrote the
register in full.

AI-assisted.
DeltaFile
+623-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
+206-76llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+78-0llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
+10-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+3-2llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
+920-785 files

LLVM/project f0cd35b — llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp

[AMDGPU][NFC] Avoid duplicate MAI hazard checks

PreEmitNoopsCommon called checkMAIVALUHazards twice whenever padding was
required.

AI-assisted.
DeltaFile
+3-4llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+3-41 files

LLVM/project a398793 — llvm/lib/Target/AMDGPU GCNHazardRecognizer.h GCNHazardRecognizer.cpp

[AMDGPU][NFC] Extract the MFMA read-window calculation

Move the wait states a consumer needs before reading an MFMA result out
of checkMAIHazards90A into getMFMAReadWaitStates, taking the producer as
an argument, so a caller can ask about a specific producer. The partial
srcC overlap half moves into getMFMAOverlappedSrcCWaitStates. The caller
passes the producer the walk recorded, so nothing changes.

AI-assisted.
DeltaFile
+145-137llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+11-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+156-1372 files

LLVM/project f739fbc — llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/AArch64 diff-checks-force-interleave-count.ll

[LV] Honor -force-vector-interleave when generating diff checks  (#225768)

We use both IC and UserIC in the checks below. However, once those
checks are done, UserIC will always override IC if it's non-zero. That
means using the max is unnecessary and can result in overly conservative
checks when UserIC < IC.
DeltaFile
+43-0llvm/test/Transforms/LoopVectorize/AArch64/diff-checks-force-interleave-count.ll
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+44-12 files

LLVM/project b5426c1 — orc-rt/include/orc-rt-c/support Logging.h, orc-rt/test/unit/support LoggingTest.cpp

[orc-rt] Add ORC_RT_LOG_ENABLED macro. (#226500)

ORC_RT_LOG_ENABLED(Level) reports whether log sites at the given level
are compiled in, taking into account both the backend and the
ORC_RT_LOG_LEVEL floor. It takes the same level token as ORC_RT_LOG and
can be used in preprocessor conditionals, allowing code that relies on
logging to surface something important (e.g. a logging error reporter)
to choose an alternative when logging is compiled out.
DeltaFile
+44-1orc-rt/test/unit/support/LoggingTest.cpp
+29-0orc-rt/include/orc-rt-c/support/Logging.h
+73-12 files

LLVM/project ce8e983 — mlir/include/mlir/Dialect/Linalg/IR LinalgInterfaces.td, mlir/include/mlir/Dialect/OpenACC OpenACCOpsInterfaces.td

[mlir][Interfaces] Share more operation interface bodies (NFC) (#226603)

Use raw operation access for methods that do not depend on the concrete
operation type. Keep typed access where operation-specific APIs are
needed.

This save a little bit of code size and improves build time.

Assisted-by: Codex
DeltaFile
+6-5mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
+4-4mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+3-3mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
+4-2mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAInterfaces.td
+2-2mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
+2-1mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorInterfaces.td
+21-176 files

LLVM/project 7fc4f27 — flang/lib/Parser openacc-parsers.cpp, flang/test/Parser acc-label-do.f90

[flang][openacc] Build full shared-label DO nests in AccNonBlockDoConstruct (#225997)

When an `!$acc loop` is associated with a labeled DO,
AccNonBlockDoConstruct
turned only that outer loop into a DoConstruct and left sibling
LabelDoStmts
that share the same terminator for later CanonicalizeDo. An inner `!$acc
loop`
then swallowed the shared terminator into its own DoConstruct, so
AnalyzeLabels (which runs before CanonicalizeDo) rejected the remaining
LabelDoStmts with "Label 'N' is not in DO loop scope".

Recurse on nested LabelDoStmts while parsing the associated loop so the
whole shared-label nest is a DoConstruct before label analysis. Add a
parser test where only the outer and innermost loops have LOOP
directives.
DeltaFile
+53-25flang/lib/Parser/openacc-parsers.cpp
+57-0flang/test/Parser/acc-label-do.f90
+110-252 files

LLVM/project 7e91ef5 — libcxx/include/__algorithm pstl.h, libcxx/include/__pstl backend_fwd.h

[libc++][pstl] Implementation of parallel std::swap_ranges() based on parallel __for_each (#224967)

This PR adds an implementation of parallel `std::swap_ranges()` based on
`__parallel_for_each_iter_pair()`.

The implementation is effectively a one-liner, but has to deal with
iterator ranges, thus is located in `cpu_algos`:
```c++
__pstl::__parallel_for_each_iter_pair<_Backend>(
    first1, last1, first2,
    [](ForwardIterator1 brick_first1, ForwardIterator1 brick_last1, ForwardIterator2 brick_first2) {
        std::swap_ranges(std::move(brick_first1), std::move(brick_last1), std::move(brick_first2));
    });
```

Part of #99938
DeltaFile
+187-0libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
+71-0libcxx/include/__pstl/cpu_algos/swap_ranges.h
+14-0libcxx/include/__algorithm/pstl.h
+10-0libcxx/include/__pstl/backends/serial.h
+7-0libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
+7-0libcxx/include/__pstl/backend_fwd.h
+296-06 files not shown
+319-012 files

LLVM/project 5aa8fcc — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv trunc-select-to-max-usat.ll

[RISCV] Support swapped select operands in combineTruncSelectToSMaxUSat. (#226584)

Handle (trunc (vselect (setugt X, 2^N-1), (sext (setgt X, 0)), X)) in
addition to the existing (trunc (vselect (setult X, 2^N), X,
(sext (setgt X, 0)))) form.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
DeltaFile
+84-0llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
+28-20llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+112-202 files

LLVM/project ea89ca0 — clang/lib/Sema HLSLExternalSemaSource.cpp

address hekota, use the float overload helper
DeltaFile
+2-2clang/lib/Sema/HLSLExternalSemaSource.cpp
+2-21 files

LLVM/project 5cab296 — llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/test/CodeGen/X86 llvm.frexp.ll

[SelectionDAG] Fix result index and vector width in unrollExpandedOp (#225886)

Fixes #224127.

In `DAGTypeLegalizer::WidenVectorResult`, `unrollExpandedOp` computes
the unroll count and widened vector type from the result being legalized
(`ResNo`) rather than unconditionally using result 0. For multi-result
nodes where result types differ (e.g. `ISD::FFREXP`), this prevents
mismatched vector widths and preserves the correct result index from
`DAG.UnrollVectorOp`.

Assisted-by: Claude

---------

Co-authored-by: Demetrios Chiuratto Agourakis <agourakis82 at gmail.com>
DeltaFile
+129-15llvm/test/CodeGen/X86/llvm.frexp.ll
+8-5llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+137-202 files

LLVM/project 7fbfd20 — lldb/include/lldb/Utility StructuredData.h, lldb/source/Commands CommandObjectVersion.cpp

[lldb] Add StructuredData::Dictionary::ForEachSorted (NFC) (#226597)

`Dictionary::Serialize`, `Dictionary::GetDescription` and the build
configuration dump in `CommandObjectVersion` each collect the
dictionary's keys and sort them before iterating, so that the output
doesn't depend on StringMap's ordering. Factor that into a new
`ForEachSorted` method.

Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
DeltaFile
+17-31lldb/source/Utility/StructuredData.cpp
+16-25lldb/source/Commands/CommandObjectVersion.cpp
+17-0lldb/include/lldb/Utility/StructuredData.h
+50-563 files

LLVM/project c4195f6 — mlir/docs Interfaces.md, mlir/include/mlir/Dialect/OpenMP OpenMPOpsInterfaces.td

[mlir][ODS] Share operation interface methods with raw-op bodies (NFC) (#226317)

Allow an operation interface method to use a shared callback when its
body only needs the raw Operation. Use it for OpenMP block-argument
indexing and slicing methods, avoiding per-operation wrappers while
preserving the existing fallback and external model paths.

Reduces the size of the OpenMP dialect text section by 1.68%.

Assisted-by: Codex
DeltaFile
+49-2mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
+31-11mlir/docs/Interfaces.md
+32-0mlir/test/mlir-tblgen/op-interface.td
+8-5mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
+120-184 files

LLVM/project 5f3a611 — utils/bazel MODULE.bazel.lock linux_uapi.bzl

[bazel] Download linux UAPI headers when no local dir is set (#216868)

This PR defines a hermetic source for `@linux_api//:linux_uapi_headers`
that will be used in CI. If no `LINUX_UAPI_INCLUDE_DIR` value is
specified, then Bazel will download the linux-libc-dev debian package
and use its headers.

I originally wanted to pull from https://github.com/torvalds/linux and
build UAPI headers from source as it gives more control, but the repo is
rather large and took ~20s to download and ~10s to build. Using the
debian package's headers is closer to what the LLVM-libc fullbuild CI
[currently
does](https://github.com/llvm/llvm-project/blob/007551bacb899a409218574908d96b0633d52018/.github/workflows/containers/libc/Dockerfile#L38)
and is very fast.
DeltaFile
+62-43utils/bazel/linux_uapi.bzl
+1-1utils/bazel/MODULE.bazel.lock
+63-442 files

LLVM/project 91d0e2e — offload/include/Shared SourceInfo.h, offload/test/offloading info.c

[Offload][OpenMP] remove SourceInfo::removePath (#226586)

This Pr is the same as https://github.com/llvm/llvm-project/pull/226283
(which was reverted in https://github.com/llvm/llvm-project/pull/226557)
This Pr is the same as https://github.com/llvm/llvm-project/pull/226283
but with an update to info.c to account for the new full path output.
DeltaFile
+12-12offload/test/offloading/info.c
+2-14offload/include/Shared/SourceInfo.h
+3-0openmp/docs/ReleaseNotes.md
+17-263 files

LLVM/project f9f5ed2 — llvm/runtimes CMakeLists.txt

[LLVM] Use complete runtime dependency list for multilibs (#226580)

Summary:
The current handling makes the multilib job depend on the base runtimes
job. This means that we will potentially depend on things that don't
necessarily need to be built to fulfil the multilibs job. Instead, just
depend on the individual targets for that multilib.
DeltaFile
+4-1llvm/runtimes/CMakeLists.txt
+4-11 files

LLVM/project b4842be — llvm/lib/CodeGen/GlobalISel CombinerHelper.cpp, llvm/test/CodeGen/AArch64/GlobalISel prelegalizercombiner-undef.mir

[GlobalISel] Preserve volatile and ordered atomic stores of undef (#226265)

Guard `erase_undef_store` with `isUnordered()`, matching InstCombine.
Ensures volatile and ordered atomic stores are preserved.

---------

Co-authored-by: Hongyu Chen <hongchen at nvidia.com>
DeltaFile
+114-0llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
+12-16llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
+6-0llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
+6-0llvm/test/CodeGen/AMDGPU/call-constant.ll
+2-1llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+140-175 files

LLVM/project 30c41cd — llvm/lib/Transforms/Scalar SROA.cpp, llvm/test/Transforms/SROA vector-conversion.ll byte-conversion.ll

[SROA] Convert byte values
DeltaFile
+92-19llvm/lib/Transforms/Scalar/SROA.cpp
+52-58llvm/test/Transforms/SROA/byte-conversion.ll
+18-21llvm/test/Transforms/SROA/vector-conversion.ll
+162-983 files

LLVM/project da01264 — llvm/test/Transforms/SROA vector-conversion.ll byte-conversion.ll

[SROA] Pre-commit tests for byte conversions
DeltaFile
+274-0llvm/test/Transforms/SROA/byte-conversion.ll
+96-0llvm/test/Transforms/SROA/vector-conversion.ll
+370-02 files

LLVM/project 4462816 — llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll bitinsert-bitextract.ll, llvm/test/CodeGen/ARM bitinsert-bitextract-fp.ll bitinsert-bitextract.ll

Rebase, address comments, improvements

Created using spr 1.3.7
DeltaFile
+4,294-0llvm/test/CodeGen/RISCV/bitinsert-bitextract.ll
+3,321-0llvm/test/CodeGen/ARM/bitinsert-bitextract.ll
+1,989-0llvm/test/CodeGen/RISCV/bitinsert-bitextract-fp.ll
+1,976-0llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
+1,552-0llvm/test/CodeGen/ARM/bitinsert-bitextract-fp.ll
+478-979llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+13,610-979398 files not shown
+28,698-4,916404 files

LLVM/project 1173687 — llvm/lib/Transforms/Vectorize VPlanHelpers.h VPlan.cpp

[VPlan] Use NeedsSingleScalar consistently for ::get (NFC). (#226494)

IsScalar/IsSingleScalar as used currently may be consfusing, as it could
be read as implying that the VPValue is a single-scalar, see
https://github.com/llvm/llvm-project/pull/226153.

But here it means that the caller only needs a single scalar. Update
wording.

PR: https://github.com/llvm/llvm-project/pull/226494
DeltaFile
+17-15llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+5-5llvm/lib/Transforms/Vectorize/VPlan.cpp
+4-3llvm/lib/Transforms/Vectorize/VPlanHelpers.h
+26-233 files