LLVM/project 418ba6eclang/lib/CodeGen CGDebugInfo.cpp, clang/test/DebugInfo/CXX callsite-edges.cpp callsite-derived.cpp

[clang][DebugInfo] Add virtuality call-site target information in DWARF. (#167666)

Given the test case:

  struct CBase {
    virtual void foo();
  };

  void bar(CBase *Base) {
    Base->foo();
  }

and using '-emit-call-site-info' with llc, the following DWARF
is produced for the indirect call 'Base->foo()':

1$: DW_TAG_structure_type "CBase"
      ...
2$:   DW_TAG_subprogram "foo"
        ...

    [18 lines not shown]
DeltaFile
+93-0clang/test/DebugInfo/CXX/callsite-edges.cpp
+71-0cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/callsite-dwarf.cpp
+58-0clang/test/DebugInfo/CXX/callsite-derived.cpp
+48-0clang/test/DebugInfo/CXX/callsite-base.cpp
+28-1llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+17-0clang/lib/CodeGen/CGDebugInfo.cpp
+315-118 files not shown
+380-2324 files

LLVM/project 1b0c975llvm/test/Transforms/InstSimplify/ConstProp vector-type-constant-folding.ll

Use named values in tests. (#182102)

Address
https://github.com/llvm/llvm-project/pull/181695#discussion_r2821774068.
DeltaFile
+5-5llvm/test/Transforms/InstSimplify/ConstProp/vector-type-constant-folding.ll
+5-51 files

LLVM/project fa84bdcmlir/include/mlir/TableGen AttrOrTypeDef.h, mlir/lib/TableGen AttrOrTypeDef.cpp Operator.cpp

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+98-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+82-0mlir/test/mlir-tblgen/attrdefs.td
+82-0mlir/test/mlir-tblgen/typedefs.td
+42-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+14-0mlir/include/mlir/TableGen/AttrOrTypeDef.h
+11-0mlir/lib/TableGen/Operator.cpp
+329-05 files not shown
+369-411 files

LLVM/project f04d3a2mlir/lib/Dialect/Transform/Interfaces TransformInterfaces.cpp

[MLIR] Apply clang-tidy fixes for performance-unnecessary-value-param in TransformInterfaces.cpp (NFC)
DeltaFile
+4-1mlir/lib/Dialect/Transform/Interfaces/TransformInterfaces.cpp
+4-11 files

LLVM/project 6ca0e29mlir/lib/Dialect/Tosa/IR TosaOps.cpp, mlir/test/Dialect/Tosa tosa-infer-shapes.mlir

[mlir][tosa] Refactor convolution infer return type (#178869)

Lots of logic was repeated for Conv2D, Conv3D and Conv2DBlockScaled ops.
This commit factors out common logic to reduce code duplication.

In doing so, a bug in calculating the bias shape was also fixed. Since
DepthwiseConv2D and TransposeConv2D were fixed independently, this
commit fixes #175765.
DeltaFile
+249-190mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+20-2mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+269-1922 files

LLVM/project df05694llvm/lib/Target/AMDGPU VOPCInstructions.td, llvm/test/MC/AMDGPU gfx12_asm_vopcx.s gfx12_asm_vopc.s

[AMDGPU] Add VOPC to gfx13
DeltaFile
+1,246-1,232llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+737-721llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
+186-181llvm/lib/Target/AMDGPU/VOPCInstructions.td
+78-50llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+68-28llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+4-25llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+2,319-2,23723 files not shown
+2,391-2,25329 files

LLVM/project 62d1536llvm/lib/Target/PowerPC PPCInstrInfo.td P10InstrResources.td, llvm/test/MC/Disassembler/PowerPC ppc64le-encoding.txt ppc64-encoding.txt

[PowerPC] Add support for MSGSNDP instruction (#180974)

Message Send Privileged X-form

`msgsndp RB`
```
opcode : 0-5 (5bits)  ===> 31    
RB     : 16-20 (5 bits) 
xo     : 21-30 (10 bits)   ==> 142  

```

---------

Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
DeltaFile
+10-1llvm/lib/Target/PowerPC/PPCInstrInfo.td
+5-0llvm/test/MC/PowerPC/ppc64-encoding.s
+3-0llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
+2-1llvm/lib/Target/PowerPC/P10InstrResources.td
+2-1llvm/lib/Target/PowerPC/P9InstrResources.td
+3-0llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+25-31 files not shown
+26-37 files

LLVM/project cc704f8llvm/test/CodeGen/SystemZ fp-sincos-01.ll patchable-function-entry.ll

[SystemZ] Fix duplicate RUN lines in tests (#182273)

DeltaFile
+0-1llvm/test/CodeGen/SystemZ/fp-sincos-01.ll
+0-1llvm/test/CodeGen/SystemZ/patchable-function-entry.ll
+0-22 files

LLVM/project 2c9ba73mlir/include/mlir/TableGen Operator.h, mlir/lib/TableGen Operator.cpp AttrOrTypeDef.cpp

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+98-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+82-0mlir/test/mlir-tblgen/typedefs.td
+82-0mlir/test/mlir-tblgen/attrdefs.td
+44-0mlir/lib/TableGen/Operator.cpp
+41-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+10-0mlir/include/mlir/TableGen/Operator.h
+357-05 files not shown
+395-411 files

LLVM/project eb88b28mlir/lib/Dialect/GPU/Transforms SubgroupIdRewriter.cpp

[MLIR] Apply clang-tidy fixes for readability-identifier-naming in SubgroupIdRewriter.cpp (NFC)
DeltaFile
+2-2mlir/lib/Dialect/GPU/Transforms/SubgroupIdRewriter.cpp
+2-21 files

LLVM/project e03a87cmlir/lib/Target/LLVMIR ModuleTranslation.cpp

[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in ModuleTranslation.cpp (NFC)
DeltaFile
+3-3mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+3-31 files

LLVM/project 6dc400eflang/lib/Lower/OpenMP Clauses.cpp, flang/lib/Parser openmp-parsers.cpp

format
DeltaFile
+1-1flang/lib/Lower/OpenMP/Clauses.cpp
+1-1flang/lib/Parser/openmp-parsers.cpp
+2-22 files

LLVM/project ff97195llvm/test/CodeGen/X86 knownbits-vpmadd52.ll

[X86] knownbits-vpmadd52.ll - replace extended unicode character with regular ascii (#182278)

Stops update_llc_test_checks.py from complaining / unnecessarily changing the file
DeltaFile
+1-1llvm/test/CodeGen/X86/knownbits-vpmadd52.ll
+1-11 files

LLVM/project 8a7413bllvm/lib/Target/AMDGPU AMDGPULibCalls.cpp

Fix MSVC "not all control paths return a value" warning. NFC. (#182262)

DeltaFile
+1-0llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+1-01 files

LLVM/project d4f9e78llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp

gisel fshl/r
DeltaFile
+31-16llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+31-161 files

LLVM/project 2a75e2dmlir/include/mlir/TableGen Operator.h, mlir/lib/TableGen Operator.cpp AttrOrTypeDef.cpp

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+101-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+82-0mlir/test/mlir-tblgen/typedefs.td
+82-0mlir/test/mlir-tblgen/attrdefs.td
+44-0mlir/lib/TableGen/Operator.cpp
+41-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+10-0mlir/include/mlir/TableGen/Operator.h
+360-05 files not shown
+398-411 files

LLVM/project 64c5676flang/lib/Lower/OpenMP Clauses.cpp, flang/test/Lower/OpenMP/Todo depth-clause.f90

[flang][OpenMP] Initial support for DEPTH clause

The semantic checks do not check any conditions on the associated loop
nest (such as actual depth or whether it is a perfect nest).
Lowering will emit a not-implemented-yet message.
DeltaFile
+38-0flang/test/Parser/OpenMP/depth-clause.f90
+18-0flang/test/Lower/OpenMP/Todo/depth-clause.f90
+17-0flang/test/Semantics/OpenMP/depth-clause.f90
+9-1llvm/include/llvm/Frontend/OpenMP/ClauseT.h
+7-1llvm/include/llvm/Frontend/OpenMP/OMP.td
+6-0flang/lib/Lower/OpenMP/Clauses.cpp
+95-24 files not shown
+105-210 files

LLVM/project 78bc9c7mlir/include/mlir/IR OpBase.td AttrTypeBase.td, mlir/include/mlir/TableGen Operator.h

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+101-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+44-0mlir/lib/TableGen/Operator.cpp
+41-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+10-0mlir/include/mlir/TableGen/Operator.h
+9-0mlir/include/mlir/IR/OpBase.td
+9-0mlir/include/mlir/IR/AttrTypeBase.td
+214-03 files not shown
+234-49 files

LLVM/project 19ce561llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp

gisel rem
DeltaFile
+16-0llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+16-01 files

LLVM/project 54ab131libclc CMakeLists.txt, libclc/opencl/lib/clspv subnormal_config.cl

[libclc] Completely remove ENABLE_RUNTIME_SUBNORMAL option (#182125)

Summary:
This isn't really used and this simplifies the code. I could go deeper
to remove this content entirely as they all return `false` but I figured
    this was an easier change to do first.

---------

Co-authored-by: Wenju He <wenju.he at intel.com>
DeltaFile
+0-21libclc/CMakeLists.txt
+0-16libclc/opencl/lib/clspv/subnormal_config.cl
+0-16libclc/opencl/lib/spirv/subnormal_config.cl
+0-16libclc/opencl/lib/generic/subnormal_helper_func.ll
+0-9libclc/opencl/lib/generic/subnormal_disable.ll
+0-9libclc/opencl/lib/generic/subnormal_use_default.ll
+0-874 files not shown
+5-9110 files

LLVM/project 15fb543llvm/lib/Target/AMDGPU VOPCInstructions.td, llvm/test/MC/AMDGPU gfx12_asm_vopc.s gfx12_asm_vopcx.s

[AMDGPU] Add VOPC to gfx13
DeltaFile
+186-181llvm/lib/Target/AMDGPU/VOPCInstructions.td
+78-50llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+68-28llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+32-16llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
+28-14llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+4-25llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+396-31423 files not shown
+468-33029 files

LLVM/project bdd0f4cllvm/lib/Target/AArch64 AArch64InstrInfo.cpp, llvm/test/CodeGen/AArch64 atomic-ops-lse.ll cheap-as-a-move-MOVaddr.ll

[AArch64] Consider MOVaddr* as cheap if fuse-adrp-add
DeltaFile
+88-88llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+55-0llvm/test/CodeGen/AArch64/cheap-as-a-move-MOVaddr.ll
+9-9llvm/test/CodeGen/AArch64/memcmp.ll
+8-8llvm/test/CodeGen/AArch64/atomic-ops.ll
+6-6llvm/test/CodeGen/AArch64/cgdata-outline-gvar.ll
+9-0llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+175-1116 files not shown
+190-12012 files

LLVM/project b0192c3mlir/lib/Target/SPIRV/Deserialization Deserializer.cpp, mlir/lib/Target/SPIRV/Serialization Serializer.cpp

[mlir][spirv] (De)serialize Offset, XfbBuffer and XfbStride decorations (#181835)

Process decorations number 35, 36 and 37 in SPIR-V deserializer and
serializer; add a simple test case.
DeltaFile
+9-0mlir/test/Target/SPIRV/decorations.mlir
+3-0mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
+3-0mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
+15-03 files

LLVM/project d98d625llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 hoist-and-by-const-from-shl-in-eqcmp-zero.ll known-pow2.ll

[X86] combineSETCC - drop unnecessary shift amount bounds check for larger-than-legal ICMP_ZERO(AND(X,SHL(1,IDX))) folds (#182021)

For i128 etc. bittest patterns, we split the pattern into a i32
extraction + i32 bittest.

But we were unnecessarily limiting this to inbounds shift amounts. I
wrote this fold at the same time as narrowBitOpRMW where we needed the
bounds check for safe memory access, which isn't necessary in
combineSETCC.

Fix 2 of 2 for #147216
DeltaFile
+62-167llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+12-17llvm/lib/Target/X86/X86ISelLowering.cpp
+8-13llvm/test/CodeGen/X86/known-pow2.ll
+82-1973 files

LLVM/project a28d89bllvm/lib/CodeGen RDFLiveness.cpp, llvm/test/CodeGen/Hexagon rdf-liveness-phi-invalidation.ll

[RDF] Fix DenseMap reference invalidation in computePhiInfo (#182144)

In Liveness::computePhiInfo, the reference `RefMap &RUM =
RealUseMap[PA.Id]` can be invalidated when the inner loop inserts into
RealUseMap via `RealUseMap[P.first][SS.Id]`. If `P.first` is a new key,
the DenseMap may rehash, invalidating the RUM reference and any
iterators into it.

Fix by making a copy of the map value instead of holding a reference.
This is detected by _GLIBCXX_DEBUG (enabled via EXPENSIVE_CHECKS) which
tracks iterator validity on std::unordered_map (RefMap).
DeltaFile
+87-0llvm/test/CodeGen/Hexagon/rdf-liveness-phi-invalidation.ll
+5-1llvm/lib/CodeGen/RDFLiveness.cpp
+92-12 files

LLVM/project 46bfd69llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[LV] NFCI: Add RecurKind to VPPartialReductionChain (#181705)

This avoids having to pass around the RecurKind or re-figure it out from
the VPReductionPHI node.

This is useful in a follow-up PR, where we need to distinguish between a
`Sub` and `AddWithSub` recurrence, which can't be deduced from the
`ReductionBinOp` field.
DeltaFile
+24-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+24-141 files

LLVM/project 85688fbmlir/include/mlir/IR OpBase.td AttrTypeBase.td, mlir/lib/TableGen AttrOrTypeDef.cpp

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+45-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+10-2mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+8-2mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
+10-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+9-0mlir/include/mlir/IR/OpBase.td
+8-0mlir/include/mlir/IR/AttrTypeBase.td
+90-43 files not shown
+110-49 files

LLVM/project 15515efmlir/test/Dialect/Tosa tosa-narrow-f64-to-f32.mlir tosa-narrow-f64-to-f32-aggressive.mlir

[mlir][tosa] Fix dense_resource data alignment in tosa-narrow-* tests (#182253)

The alignment of int64 and float64 dense resource should be 8 and not 4
DeltaFile
+1-1mlir/test/Dialect/Tosa/tosa-narrow-f64-to-f32.mlir
+1-1mlir/test/Dialect/Tosa/tosa-narrow-f64-to-f32-aggressive.mlir
+1-1mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32-aggressive.mlir
+1-1mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32.mlir
+4-44 files

LLVM/project 72344f5llvm/test/CodeGen/ARM/ParallelDSP multi-use-loads.ll, llvm/test/CodeGen/Thumb2 mve-satmul-loops.ll mve-fpclamptosat_vec.ll

[RegisterCoalescer] Prefer copy over rematerialization when smaller

When the source register has multiple uses, compare instruction sizes
before rematerializing. If the copy is smaller than the rematerialized
instruction, prefer keeping the copy to reduce code size.

Additionally, register-to-register copies are often eliminated by
register renaming on modern out-of-order CPUs, making them effectively
free at runtime.
DeltaFile
+269-258llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
+98-98llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
+62-78llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
+61-61llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+52-55llvm/test/CodeGen/Thumb2/mve-scmp.ll
+52-51llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
+594-60149 files not shown
+1,008-1,01155 files

LLVM/project b2c2df6llvm/lib/Target/AMDGPU VOPCInstructions.td, llvm/test/MC/AMDGPU gfx12_asm_vopc.s gfx12_asm_vopcx.s

[AMDGPU] Add VOPC to gfx13
DeltaFile
+1,763-1,747llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
+186-181llvm/lib/Target/AMDGPU/VOPCInstructions.td
+78-50llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+68-28llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+56-14llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+4-25llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+2,155-2,04523 files not shown
+2,227-2,06129 files