LLVM/project 70f88ebllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll

Address comments

Created using spr 1.3.7
DeltaFile
+84,419-78,498llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,751-24,782llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+23,663-20,281llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+21,867-18,577llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+19,112-16,445llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+11,541-22,066llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+186,353-180,649667 files not shown
+293,680-264,860673 files

LLVM/project e68f696.github/workflows spirv-tests.yml

[CI][SPIRV][NFC] Remove unneccessary mkdir from workflow (#184353)

The `CMake` command does the `mkdir` automatically.

Pointed out in https://github.com/llvm/llvm-project/pull/184174

Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
DeltaFile
+0-1.github/workflows/spirv-tests.yml
+0-11 files

LLVM/project 6cc42b3libc/src/__support/GPU allocator.cpp

[libc] Various GPU allocator tweaks and optimizations (#184368)

Summary:
Some low-hanging fruit tweaks. Mostly preventing redundant loads and
unnecessary widening. Some fixes as well, like nullptr handling,
incorrect rounding, and oversized bitfields.
DeltaFile
+29-38libc/src/__support/GPU/allocator.cpp
+29-381 files

LLVM/project d61b45cclang/lib/CodeGen CGAtomic.cpp, clang/test/CodeGen atomic-arm64.c atomic-ops.c

[Clang] Generate ptr and float atomics without integer casts (#183853)

Summary:
LLVM IR should support these for all cases except for compare-exchange.
Currently the code goes through an integer indirection for these cases.
This PR changes the behavior to use atomics directly to the target
memory type.
DeltaFile
+13-13clang/lib/CodeGen/CGAtomic.cpp
+4-4clang/test/CodeGen/atomic-arm64.c
+3-3clang/test/CodeGen/atomic-ops.c
+3-3clang/test/CodeGen/big-atomic-ops.c
+2-2clang/test/CodeGenOpenCL/atomic-ops.cl
+25-255 files

LLVM/project aef9627llvm/lib/Target/SPIRV SPIRVCommandLine.cpp SPIRVCommandLine.h, llvm/lib/Target/SPIRV/MCTargetDesc SPIRVBaseInfo.h

Reapply "[SPIRV][NFCI] Use unordered data structures for SPIR-V extensions (#184162)

Reapply https://github.com/llvm/llvm-project/pull/183567 with minor
changes.

Problem causing the revert was we couldn't use the enum in `DenseMap`
directly because of some `TableGen` limitations so I casted made the map
use the underlying type, but that caused some UB, so I
[fixed](https://github.com/llvm/llvm-project/pull/183769) the `TableGen`
limitation so now it just works.
DeltaFile
+160-173llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+7-12llvm/lib/Target/SPIRV/SPIRVCommandLine.h
+4-6llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
+3-5llvm/lib/Target/SPIRV/SPIRVSubtarget.h
+3-0llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.h
+1-1llvm/lib/Target/SPIRV/SPIRVAPI.cpp
+178-1971 files not shown
+179-1977 files

LLVM/project 02b2a1ellvm/lib/Target/M68k/GISel M68kCallLowering.cpp

Fix `assignValueToReg` function's argument (#184354)

Because of [PR#178198](https://github.com/llvm/llvm-project/pull/178198)
the argument changes for `assignValueToReg`.

This PR aiming at fixing M86k experimental target
DeltaFile
+4-2llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
+4-21 files

LLVM/project dd0a780llvm CMakeLists.txt, openmp/runtime CMakeLists.txt

CMake fixes
DeltaFile
+8-8openmp/runtime/cmake/arm64x.cmake
+2-2llvm/CMakeLists.txt
+1-2openmp/runtime/CMakeLists.txt
+11-123 files

LLVM/project 205a89allvm/include/llvm/CodeGen Rematerializer.h

Remove useless argument
DeltaFile
+2-2llvm/include/llvm/CodeGen/Rematerializer.h
+2-21 files

LLVM/project 938e87fclang-tools-extra/unittests/clang-tidy LexerUtilsTest.cpp, clang/test/SemaHLSL static_resources.hlsl

Address comments

Created using spr 1.3.7
DeltaFile
+216-0lldb/test/API/functionalities/gdb_remote_client/TestBatchedBreakpointStepOver.py
+204-0clang-tools-extra/unittests/clang-tidy/LexerUtilsTest.cpp
+170-1lldb/source/Target/ThreadList.cpp
+138-0clang/test/SemaHLSL/Resources/static_resources.hlsl
+0-138clang/test/SemaHLSL/static_resources.hlsl
+135-0clang/test/SemaHLSL/Resources/resource_binding_attr_error_udt.hlsl
+863-139230 files not shown
+4,932-2,698236 files

LLVM/project 358f477clang/lib/CodeGen CGStmtOpenMP.cpp, clang/test/OpenMP parallel_for_codegen.cpp for_range_loop_codegen.cpp

[Clang] Fix clang crash for fopenmp statement(for) inside lambda function (#146772)

C++ range-for statements introduce implicit variables such as `__range`,
`__begin`, and `__end`. When such a loop appears inside an OpenMP
loop-based directive (e.g. `#pragma omp for`) within a lambda, these
implicit variables were not emitted before OpenMP privatization logic
ran.

OMPLoopScope assumes that loop-related variables are already present in
LocalDeclMap and temporarily overrides their addresses. Since the
range-for implicit variables had not yet been emitted, they were treated
as newly introduced entries and later erased during restore(), leading
to missing mappings and a crash during codegen.

Fix this by emitting the range-for implicit variables before OpenMP
privatization (setVarAddr/apply), ensuring that existing mappings are
correctly overridden and restored.

This fixes #146335
DeltaFile
+1,128-1,116clang/test/OpenMP/parallel_for_codegen.cpp
+252-0clang/test/OpenMP/for_range_loop_codegen.cpp
+14-13clang/lib/CodeGen/CGStmtOpenMP.cpp
+1,394-1,1293 files

LLVM/project e10655ellvm/test/CodeGen/X86 known-never-zero.ll

[X86] known-never-zero.ll - add sdiv/udiv vector test coverage for #183047 (#184350)

DeltaFile
+146-0llvm/test/CodeGen/X86/known-never-zero.ll
+146-01 files

LLVM/project 43503c4llvm/lib/Target/AArch64 AArch64ConditionOptimizer.cpp

[NFC][AArch64] isPureCmp is a duplicate of canAdjustCmp, so remove the duplicate (#183568)

Just delete the duplicate function.
DeltaFile
+1-19llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+1-191 files

LLVM/project 81396ebllvm/lib/Target/AMDGPU SIShrinkInstructions.cpp, llvm/test/CodeGen/AMDGPU v_swap_b16.ll v_swap_b32.mir

[AMDGPU] Generate more swaps (#184164)

Generate more swaps from:

```
   mov T, X
   ...
   mov X, Y
   ...
   mov Y, X
```
by being more careful about what use/defs of X, Y, T are allowed in
intervening code and allowing flexibility where the swap is inserted.

---------

Signed-off-by: John Lu <John.Lu at amd.com>
DeltaFile
+154-0llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
+62-52llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+66-32llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
+15-29llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+2-2llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+299-1155 files

LLVM/project e570faaclang/lib/Driver/ToolChains HIPAMD.cpp, clang/test/Driver hip-toolchain-no-rdc.hip spirv-amd-toolchain.c

[SPIR-V][HIP] Disable SPV_KHR_untyped_pointers (#183530)

SPV_KHR_untyped_pointers in SPIR-V to LLVM translator is incomplete with
few known issues. Therefore we better not to rely on this extension for SPIR-V
generation.
DeltaFile
+1-1clang/lib/Driver/ToolChains/HIPAMD.cpp
+1-1clang/test/Driver/hip-toolchain-no-rdc.hip
+1-1clang/test/Driver/spirv-amd-toolchain.c
+3-33 files

LLVM/project acb8a6dllvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 neon-extractbitcast-mir.ll

[AArch64] Fix type mismatch in bitconvert + vec_extract patterns (#183549)

This patch fixes mismatch in element width during isel of bitconvert +
vec_extract nodes. This resolves issue reported on
[this](https://github.com/llvm/llvm-project/pull/172837) PR.
DeltaFile
+18-0llvm/test/CodeGen/AArch64/neon-extractbitcast-mir.ll
+2-2llvm/lib/Target/AArch64/AArch64InstrInfo.td
+20-22 files

LLVM/project c9d065allvm/test/CodeGen/X86 shift-i256.ll funnel-shift-i256.ll

[X86] Add i256 shift / funnel shift coverage to match i512 tests (#184346)

shift-i256.ll - added x86-64/x86-64-v2/x86-64-v3/x86-64-v4 coverage and retained the x86 test coverage
DeltaFile
+3,169-313llvm/test/CodeGen/X86/shift-i256.ll
+2,056-0llvm/test/CodeGen/X86/funnel-shift-i256.ll
+5,225-3132 files

LLVM/project 5b976c9libc/include/llvm-libc-macros/linux sys-ipc-macros.h, libc/include/llvm-libc-types struct_ipc_perm.h

[libc][sys] add header and functions for sys ipc (#182700)

Split from a larger change. This PR contains the base impl for sys ipc,
sys sem will come after this. @SchrodingerZhu

this PR implements for:
https://github.com/llvm/llvm-project/issues/182161

see the last PR for more detail:
https://github.com/llvm/llvm-project/pull/182683
DeltaFile
+59-0libc/test/src/sys/ipc/linux/ftok_test.cpp
+51-0libc/include/sys/ipc.yaml
+38-0libc/src/sys/ipc/linux/ftok.cpp
+34-0libc/src/sys/ipc/linux/kernel_statx.h
+34-0libc/include/llvm-libc-types/struct_ipc_perm.h
+24-0libc/include/llvm-libc-macros/linux/sys-ipc-macros.h
+240-018 files not shown
+421-024 files

LLVM/project c782e2dllvm/lib/Target/SPIRV SPIRVModuleAnalysis.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers fun-ptr-service-func.ll

[SPIRV] Don't emit service function basic block names (#184206)

Right now if a module has a service function we always emit `OpName
entry` for the service function's basic block.

The actual service function isn't emitted and no other instruction uses
the basic block `OpName` instruction, so don't emit it.

Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
DeltaFile
+6-3llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
+4-0llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+1-1llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-service-func.ll
+11-43 files

LLVM/project bbde3e3llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize if-pred-stores.ll

[VPlan] Preserve IsSingleScalar for sunken predicated stores. (#184329)

The predicated stores may be single scalar (e.g. for VF = 1). We should
preserve IsSingleScalar. As all stores access the same address,
IsSingleScalar must match across all stores in the group.

This fixes an assertion when interleaving-only with sunken stores.

Fixes https://github.com/llvm/llvm-project/issues/184317

PR: https://github.com/llvm/llvm-project/pull/184329
DeltaFile
+181-0llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
+7-5llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+188-52 files

LLVM/project 7c2c505llvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Move rollback capabilities outside of the rematerializer

The rematerializer implements support for rolling back
rematerializations by modifying MIs that should normally be deleted in
an attempt to make them "transparent" to other analyses. This involves:

1. setting their opcode to DBG_VALUE and
2. setting their read register operands to the sentinel register.

This approach has several drawbacks.

1. It forces the rematerializer to support tracking these "dead MIs".
2. It is not actually clear whether this mechanism will interact well
   with all other analyses. This is an issue since the intent of the
   rematerializer is to be usable in as many contexts as possible.
3. In practice, it has shown itself to be relatively error-prone.

This commit removes rollback support from the rematerializer and moves
those capabilties to a rematerializer listener than can be instantiated

    [5 lines not shown]
DeltaFile
+153-130llvm/lib/CodeGen/Rematerializer.cpp
+98-80llvm/include/llvm/CodeGen/Rematerializer.h
+108-23llvm/unittests/CodeGen/RematerializerTest.cpp
+359-2333 files

LLVM/project 8b1ec1cllvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Allow rematerializer to rematerialize at the end of a block

This makes the rematerializer able to rematerialize MIs at the end of a
basic block. We achive this by tracking the parent basic block of every
region inside the rematerializer and adding an explicit target region to
some of the class's methods. The latter removes the requirement that we
track the MI of every region (`Rematerializer::MIRegion`) after the
analysis phase; the class member is therefore deleted.

This new ability will be used shortly to improve the design of the
rollback mechanism.
DeltaFile
+35-25llvm/lib/CodeGen/Rematerializer.cpp
+32-27llvm/include/llvm/CodeGen/Rematerializer.h
+16-14llvm/unittests/CodeGen/RematerializerTest.cpp
+83-663 files

LLVM/project ef56bdellvm/lib/CodeGen Rematerializer.cpp

Format
DeltaFile
+1-1llvm/lib/CodeGen/Rematerializer.cpp
+1-11 files

LLVM/project d41b7fflibsycl/docs index.rst, libsycl/include/sycl/__impl queue.hpp property_list.hpp

fix comments

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+15-23libsycl/include/sycl/__impl/queue.hpp
+7-16libsycl/src/detail/queue_impl.hpp
+2-2libsycl/include/sycl/__impl/detail/default_async_handler.hpp
+1-1libsycl/include/sycl/__impl/property_list.hpp
+1-1libsycl/docs/index.rst
+1-1libsycl/include/sycl/__impl/async_handler.hpp
+27-446 files

LLVM/project 1eeb2ecclang-tools-extra/clang-tidy/bugprone StdNamespaceModificationCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Handle specialization of user-defined type in `bugprone-std-namespace-modification` (#183984)

Ignore `templateSpecializationType` based on user-define classes too.

Fixes #183752
DeltaFile
+15-0clang-tools-extra/test/clang-tidy/checkers/bugprone/std-namespace-modification.cpp
+7-4clang-tools-extra/clang-tidy/bugprone/StdNamespaceModificationCheck.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+3-0clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/system-header-simulation.h
+30-44 files

LLVM/project 33864eflld/COFF Driver.cpp, lld/wasm OutputSections.cpp

[lld] Turn misc copy-assign to move-assign (#184145)

That's an automated patch generated from clang-tidy
performance-use-std-move as a follow-up to #184136
DeltaFile
+1-1lld/COFF/Driver.cpp
+1-1lld/wasm/OutputSections.cpp
+2-22 files

LLVM/project 3b20f09clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp

Tweak NYI msgs
DeltaFile
+8-15clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+8-151 files

LLVM/project 0991e23llvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Add listener support to the rematerializer (NFC)

This change adds support for adding listeners to the
target-independent rematerializer; listeners can catch certain
rematerialization-related events to implement some additional
functionnality on top of what the rematerializer already performs.

This has no user at the moment, but the plan is to have listeners start
being responsible for secondary/optional functionnalities that are at
the moment integrated with the rematerializer itself. Two examples of
that are:
1. rollback support (currently optional), and
2. region tracking (currently mandatory, but not fundamentally necessary
   to the rematerializer).
DeltaFile
+43-0llvm/include/llvm/CodeGen/Rematerializer.h
+7-1llvm/lib/CodeGen/Rematerializer.cpp
+50-12 files

LLVM/project 534d6e8llvm/include/llvm/Analysis BlockFrequencyInfoImpl.h

[Analysis][NFC] Store CallbackVH in vector, not in map (#184323)

This avoid non-trivial move operations whenever the map grows.
DeltaFile
+31-30llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+31-301 files

LLVM/project 97043e5mlir/lib/Dialect/Vector/Transforms VectorDistribute.cpp, mlir/test/Dialect/Vector vector-warp-distribute.mlir

[mlir][Vector][GPU] Distribute expanding `shape_cast` ops (#183830)

The initial implementation of `shape_cast` distribution only focused on
scenarios with collapsing shape casts. Within downstream pipelines such
as IREE, commit 962a9a3 exposes an issue with this implementation, where
the rank-expanding cast ops (stemming from the new `vector.broadcast`
canonicalization) silently fall through to the "collapsing-or-no-op"
logic. This brings about bugs with rank mismatches and firing validation
assertions when distributing rather common reshaping sequences
encountered after CSE/ canonicalization, such as below:
```
  // Example 1: gather op
  %weight = arith.constant dense_resource<__elided__> : tensor<256xi8>
  %c0 = arith.constant 0 : index
  ...
  %expand = vector.shape_cast <...> : vector<1xindex> to vector<1x1xindex>
  %gather = vector.gather %weight[%c0] [%expand], <...>, <...> : memref<256xi8>, vector<1x1xindex>, vector<1x1xi1>, vector<1x1xi8> into vector<1x1xi8>
  %collapse_back = vector.shape_cast %gather : vector<1x1xi8> to vector<1xi8>
  // Example 2: multi-reduction

    [19 lines not shown]
DeltaFile
+68-0mlir/test/Dialect/Vector/vector-warp-distribute.mlir
+45-10mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
+113-102 files

LLVM/project 6d83be8llvm/test/CodeGen/AMDGPU select-nsz-known-values-to-fmin-fmax.ll

AMDGPU: Add more tests for fp min/max combines

There's some overlap with existing tests which
use the nnan flag. The vector cases get missed here.
DeltaFile
+956-0llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
+956-01 files