LLVM/project 0b414fb — llvm/test/CodeGen/AMDGPU va-ssrc-sdst-hazard-sched.mir

Fix test

Change-Id: I1aef9ffd0713bed2af97fe758a32a013c83c2af7
DeltaFile
+4-2llvm/test/CodeGen/AMDGPU/va-ssrc-sdst-hazard-sched.mir
+4-21 files

LLVM/project 6f41962 — libc/src/__support/OSUtil/linux/syscall_wrappers shmdt.h, libc/src/sys/shm shmdt.h

[libc][sys/shm] Implement shmdt syscall wrapper on Linux. (#239785)

`shmdt` is a POSIX function (see
[docs](https://pubs.opengroup.org/onlinepubs/9799919799/functions/shmdt.html#))
that detaches the shared memory segment from the address space of a
calling process.

On Linux, it can be implemented as a simple wrapper around SYS_shmdt
syscall.

Provide the implementation, and add a simple test case verifying it only
works correctly on addresses returned by `shmat` call.
DeltaFile
+55-0libc/test/src/sys/shm/linux/shmdt_test.cpp
+33-0libc/src/__support/OSUtil/linux/syscall_wrappers/shmdt.h
+32-0libc/src/sys/shm/linux/shmdt.cpp
+25-0libc/src/sys/shm/shmdt.h
+11-9libc/test/src/sys/shm/linux/shmat_test.cpp
+19-0libc/test/src/sys/shm/linux/CMakeLists.txt
+175-97 files not shown
+217-913 files

LLVM/project 216a14a — llvm/lib/Target/RISCV RISCVInstrInfo.cpp RISCVFeatures.td, llvm/test/CodeGen/RISCV reserved-reg-errors-alias.ll

[RISCV] Report errors for user reserving argument/return registers with Zhinx/Zfinx. (#239384)

Zhinx/Zfinx can use X10_H-X17_H or X10_W-X10_H subregisters. These were
not tracked in the bitvector in RISCVSubtarget.

The subtarget now contains a 32 element bitset for just the X registers.
The full bitset has moved to RISCVRegisterInfo where it is populated
with the aliases in the constructor.

RISCVRegisterInfo::getReservedRegs now uses the 32 element bitset. This
required moving the constant registers out of the loop and reserving
them explicitly. Alternatively, we could use the full bitset here, but
since we use markSuperRegs, we'd end up visiting registers multiple
times.

I've kept an accessor for the full bitset in RISCVSubtarget to avoid
touching all callers.

Assisted-by: Claude
DeltaFile
+22-15llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+37-0llvm/test/CodeGen/RISCV/reserved-reg-errors-alias.ll
+14-1llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+9-2llvm/lib/Target/RISCV/RISCVSubtarget.h
+1-1llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+1-1llvm/lib/Target/RISCV/RISCVFeatures.td
+84-206 files

LLVM/project 7a08f39 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIFoldOperands.cpp

AMDGPU: Remove clearKillFlags calls

Kill flags on physical registers here are either never set by the
time this code runs or are on reserved or constant registers where
they carry no information. Remove the clearKillFlags calls.

SIPeepholeSDWA was adding a kill flag on the virtual register it ties
to the preserved destination and relying on the clear to remove it.
Stop adding it.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+1-18llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+0-13llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+0-9llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-403 files

LLVM/project b44013d — llvm/lib/CodeGen MachineSink.cpp

MachineSink: Remove clearKillFlags calls

Kill flags on physical registers here are either never set by the
time this code runs or are on reserved or constant registers where
they carry no information. Remove the clearKillFlags calls.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-20llvm/lib/CodeGen/MachineSink.cpp
+0-201 files

LLVM/project ce04062 — llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU va-ssrc-sdst-hazard-sched.mir atomic_optimizations_global_pointer.ll

Widen hazard conditions to account for VCC RegClass matching + fold hazard checking

Change-Id: If1a818206d383bababe156185cec1831229e7bec
DeltaFile
+18-159llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+18-18llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
+9-9llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+2-3llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+2-2llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+1-1llvm/test/CodeGen/AMDGPU/va-ssrc-sdst-hazard-sched.mir
+50-1926 files

LLVM/project 907aa7a — llvm/lib/Target/LoongArch LoongArchOptWInstrs.cpp

LoongArch: Remove clearKillFlags calls on virtual registers

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-1llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
+0-11 files

LLVM/project fdb5365 — llvm/lib/Target/PowerPC PPCMIPeephole.cpp

PowerPC: Remove clearKillFlags calls on virtual registers

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-2llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+0-21 files

LLVM/project c69f817 — llvm/lib/Target/X86 X86OptimizeLEAs.cpp

X86: Remove clearKillFlags calls on virtual registers

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-6llvm/lib/Target/X86/X86OptimizeLEAs.cpp
+0-61 files

LLVM/project c16d477 — llvm/lib/Target/RISCV RISCVVectorPeephole.cpp RISCVOptWInstrs.cpp

RISCV: Remove clearKillFlags calls on virtual registers

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-6llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+0-1llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+0-1llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+0-83 files

LLVM/project fa61fe8 — llvm/lib/Target/RISCV RISCVZilsdOptimizer.cpp, llvm/test/CodeGen/RISCV O3-pipeline.ll

[RISCV] Drop MachineDominatorTreeWrapperPass in Zilsd optimizer (#239783)

The last use of MachineDominatorTreeWrapperPass in
RISCVZilsdOptimizer.cpp was removed on November 6, 2026 in commit
d8ce3e5f727698eacfc46687562e5c53ab7c7241.

This patch removes the unused MachineDominatorTreeWrapperPass dependency
and MachineDominators.h include from RISCVZilsdOptimizer.cpp.  Dropping
this dependency defers MachineDominator Tree Construction in the legacy
RISC-V -O3 pipeline until right before Slot index numbering.

Assisted-by: Antigravity
DeltaFile
+0-3llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+1-1llvm/test/CodeGen/RISCV/O3-pipeline.ll
+1-42 files

LLVM/project ebcde07 — llvm/lib/Target/X86 X86AvoidStoreForwardingBlocks.cpp

X86: Remove dead kill flag maintenance in X86AvoidStoreForwardingBlocks (#239777)

This pass runs before register allocation, and the verifier now
rejects kill flags on virtual registers.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-33llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
+0-331 files

LLVM/project b9c30ea — llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination sadd-with-overflow.ll minmax.ll

[ConstraintElim] Split signed min/max across their operands when checking a compare

The existing constraint systems only record the bounds that hold for both
operands of a min/max (smax(a, b) >= a and >= b, smin(a, b) <= a and <= b). The
other direction is a disjunction, which cannot be recorded as a fact. When a
compare of signed decompositions involves a min/max result, split it into its
operands: the decomposition is monotonic in that result, so it is the max or min
of its values on each side, and the relation holds for all or for either side
respectively.

https://alive2.llvm.org/ce/z/zsGkJ-
DeltaFile
+366-3llvm/test/Transforms/ConstraintElimination/minmax.ll
+111-0llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+4-8llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+481-113 files

LLVM/project d72667b — llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination add-nsw.ll sadd-with-overflow.ll

[ConstraintElim] A signed sum of operands with opposite signs cannot wrap

If one operand is known non-negative and the other non-positive, the signed
sum is between them, so it cannot overflow.

https://alive2.llvm.org/ce/z/ZF5Yqr
DeltaFile
+97-2llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+19-0llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+3-6llvm/test/Transforms/ConstraintElimination/add-nsw.ll
+119-83 files

LLVM/project c40cf3d — llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination ssub-with-overflow.ll sadd-with-overflow.ll

[ConstraintElim] Prove sadd/ssub.with.overflow cannot overflow from the exact sum

Decompose the operands and show that the sum lies in the range of the type. This
handles patterns like A + (B - A), as well as sums involving signed min/max
results, which are split across their respective operands using monotonicity
(for example start + smax(end - start - 1, 0) <= end).

https://alive2.llvm.org/ce/z/ze8LCk
DeltaFile
+539-0llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
+159-4llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+100-0llvm/test/Transforms/ConstraintElimination/ssub-with-overflow.ll
+798-43 files

LLVM/project e82d29c — llvm/lib/Transforms/Scalar ConstraintElimination.cpp

remove pair + destructuring
DeltaFile
+4-4llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+4-41 files

LLVM/project 54c4c97 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIISelLowering.cpp

AMDGPU: Remove clearKillFlags calls on virtual registers (#239780)

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-6llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
+0-6llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+0-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+0-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+0-174 files

LLVM/project 90c2c0c — llvm/lib/Target/Hexagon HexagonPeephole.cpp HexagonGenInsert.cpp

Hexagon: Remove clearKillFlags calls on virtual registers (#239781)

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-3llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+0-3llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+0-2llvm/lib/Target/Hexagon/HexagonPeephole.cpp
+0-83 files

LLVM/project 749ef4e — libc/src/string/memory_utils/generic inline_strlen.h, libc/src/string/memory_utils/x86_64 inline_strlen.h

[libc] Don't match the byte after the range in vector find_first_character (#235288)

The vectorized `find_first_character` implementations (`clang_vector`
and the x86_64 `arch_vector`) returned the position of a match that was
the first byte after the searched range. For example, `memchr("ab", 'b',
1)` returned a pointer to the `'b'` instead of `nullptr`.

The new test covers all implementations, since no configuration selects
the vectorized ones by default. On aarch64 Linux, it fails without the
fix and passes with it. The x86_64 changes were only compiled, not run.

Assisted-by: Claude Code (Claude Opus 5.5)
DeltaFile
+35-0libc/test/src/strings/wide_read_memory_test.cpp
+1-1libc/src/string/memory_utils/x86_64/inline_strlen.h
+1-1libc/src/string/memory_utils/generic/inline_strlen.h
+37-23 files

LLVM/project f1da939 — libc/src/string/memory_utils/generic inline_strlen.h, libc/src/string/memory_utils/x86_64 inline_strlen.h

[libc] Don't read memory in vector find_first_character if n is 0 (#235289)

The vectorized `find_first_character` implementations (`clang_vector`
and the x86_64 `arch_vector`) loaded the aligned block containing the
start pointer before checking the length. With a length of zero, the
pointer doesn't have to be dereferenceable, so `memchr(p, c, 0)` and
`strnlen(p, 0)` crashed if `p` was the start of an inaccessible page.

The new test covers all implementations, since no configuration selects
the vectorized ones by default. On aarch64 Linux, it segfaults without
the fix and passes with it. The x86_64 changes were only compiled, not
run.

Assisted-by: Claude Code (Claude Opus 5.5)
DeltaFile
+23-0libc/test/src/strings/wide_read_memory_test.cpp
+4-0libc/src/string/memory_utils/x86_64/inline_strlen.h
+4-0libc/src/string/memory_utils/generic/inline_strlen.h
+31-03 files

LLVM/project 4220670 — llvm/test/CodeGen/AMDGPU srem.ll amdgpu-codegenprepare-idiv.ll, llvm/test/CodeGen/RISCV half-round-conv-sat.ll half-round-conv.ll

[DAG] Fold fp_to_int(ftrunc(x)) -> fp_to_int(x) (#231060)

fp_to_[su]int already rounds toward zero, so an ftrunc in front of it
does nothing and can be dropped. fp_to_[su]int_sat is the same since it
truncates before it clamps.

x86 hits this through LowerFROUND which expands round into a copysign
add plus an ftrunc so (long)roundf(x) keeps a vroundss that the convert
makes pointless.

The AArch64 test changes are shapes its isel patterns don't cover,
mostly f16 and bf16.

On RISC-V llvm.trunc on some test cases turns into an fabs, a compare,
an fcvt round trip and an fsgnj, or a call to trunc, and all of it goes
away.

AMDGPU runs integer division through a float reciprocal. The i32 cases
each lose a v_trunc_f32. The i64 files only change register numbering

    [7 lines not shown]
DeltaFile
+408-518llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+0-462llvm/test/CodeGen/RISCV/half-round-conv.ll
+389-0llvm/test/CodeGen/X86/fp-round.ll
+44-288llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+16-168llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
+88-88llvm/test/CodeGen/AMDGPU/srem.ll
+945-1,52423 files not shown
+1,370-2,31529 files

LLVM/project aa5022f — llvm/lib/Target/X86 X86ExpandPseudo.cpp, llvm/test/CodeGen/X86 vaargs-prolog-insert.ll

[X86ExpandPseudo] Don't preserve CFG unconditionally (#239756)

As in title. CFG can't be preserved unconditionally because it is
sometimes changed. Add newpm line to affected test
DeltaFile
+7-1llvm/lib/Target/X86/X86ExpandPseudo.cpp
+1-0llvm/test/CodeGen/X86/vaargs-prolog-insert.ll
+8-12 files

LLVM/project 4e02a6e — llvm/lib/Target/PowerPC PPCISelLowering.cpp, llvm/test/CodeGen/PowerPC f128-brcc.ll

[PowerPC] Custom-lower `f128` `BR_CC` for VSX w/o P9 (#230758)

`f128` is legal in VSX registers, but actual operations are softened
prior to P9. Expanding a `BR_CC` does not soften the compare; it only
legalizes the condition code, which is already legal, so we hit the
assertion:

    assert(Legalized && "Can't legalize BR_CC with legal condition!");

`LowerBR_CC()` already handles both aspects correctly for SPE, so just
repurpose that for this case, similar to other backends.

closes https://github.com/llvm/llvm-project/issues/171869
DeltaFile
+81-0llvm/test/CodeGen/PowerPC/f128-brcc.ll
+2-4llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+83-42 files

LLVM/project 28e51ff — flang/lib/Lower OpenACC.cpp, flang/lib/Semantics resolve-directives.cpp

[flang][OpenACC] Reject real explicit acc loop bounds in semantics (#239258)

Follow-up to f8897bb9f "[flang][OpenACC] Convert real DO controls for
implicit acc.loop". That change converts a REAL DO control of an
implicit acc.loop to the induction variable's integer type. An explicit
!$acc loop must have integer bounds, but semantics did not check them,
so a REAL lower bound, upper bound, or step reached lowering. With a
REAL upper bound and no step, lowering built the default step from the
REAL type and aborted:

  error: expected integer or index type

Check the lower bound, upper bound, and step of each loop associated
with an explicit directive in CheckAssociatedLoop, including COLLAPSE
nests. A REAL expression is reported as "OpenACC loop bound expression
must have INTEGER type". Implicit acc loops are checked during lowering,
where a non-integer control is converted to the induction variable's
integer type. DO CONCURRENT does not pass its step to the semantic
check, because its step is parsed as ScalarIntExpr.

    [6 lines not shown]
DeltaFile
+71-0flang/test/Semantics/OpenACC/acc-loop-real-bounds.f90
+25-6flang/lib/Semantics/resolve-directives.cpp
+8-9flang/lib/Lower/OpenACC.cpp
+104-153 files

LLVM/project 76712e3 — flang/include/flang/Semantics symbol.h, flang/lib/Semantics resolve-directives.cpp

[flang][OpenACC] Resolve the DELETE and NO_CREATE clause operands (#239677)

A named common block in a `delete` or `no_create` clause produces an
internal error instead of being resolved:

```fortran
subroutine s
  integer :: a
  common /c/ a
  !$acc enter data create(/c/)
  a = 1
  !$acc exit data delete(/c/)
end subroutine
```

```
error: Internal: no symbol found for 'c'
  !$acc exit data delete(/c/)
                          ^

    [55 lines not shown]
DeltaFile
+64-0flang/test/Semantics/OpenACC/acc-delete-no-create-common.f90
+32-0flang/test/Lower/OpenACC/acc-delete-no-create-common.f90
+12-1flang/lib/Semantics/resolve-directives.cpp
+2-1flang/include/flang/Semantics/symbol.h
+110-24 files

LLVM/project b6bc8a1 — llvm/unittests/Target/X86 TernlogTest.cpp

X86: Keep the TargetMachine alive in TernlogTest (#239759)

The TTI callback destroyed the TargetMachine it created before the
returned TTI was used, leaving it with dangling pointers. It just
happens this test never reads from these pointers today, so no
sanitizer reports this.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+2-2llvm/unittests/Target/X86/TernlogTest.cpp
+2-21 files

LLVM/project 47a4d6a — offload/libompaccsupport device.cpp Mapping.cpp, offload/libomptarget private.h

[Offload] Add per-message INFO verbosity levels to INFO debug messages

Assisted-by: Claude Opus 5.5
DeltaFile
+137-52offload/libompaccsupport/Mapping.cpp
+136-0offload/test/offloading/info_level.c
+29-5openmp/docs/design/Runtimes.md
+20-10offload/plugins-nextgen/amdgpu/src/rtl.cpp
+14-7offload/libompaccsupport/device.cpp
+9-6offload/libomptarget/private.h
+345-805 files not shown
+362-8411 files

LLVM/project 4e3b274 — offload/include/Shared Debug.h, offload/libompaccsupport Mapping.cpp

[Offload] Add LIBOMPTARGET_INFO output to LIBOMPTARGET_DEBUG

Assisted-by: Claude Opus 5.5
DeltaFile
+80-71offload/include/Shared/Debug.h
+49-0offload/test/mapping/attach_ptr_update_to_restore_info.c
+22-0offload/test/offloading/info_category.c
+10-10offload/libompaccsupport/Mapping.cpp
+8-7offload/libomptarget/omptarget.cpp
+7-7offload/libomptarget/private.h
+176-955 files not shown
+189-10811 files

LLVM/project 8840165 — llvm/lib/Target/RISCV RISCVVectorPeephole.cpp RISCVOptWInstrs.cpp

RISCV: Remove clearKillFlags calls on virtual registers

Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+0-6llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+0-1llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+0-1llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+0-83 files

LLVM/project 7748648 — .github/workflows libc-fullbuild-tests.yml, compiler-rt/cmake/Modules AddCompilerRT.cmake

[libc][scudo] Use RUNTIMES_USE_LIBC to decide if scudo uses LLVM-libc (#239496)

`RUNTIMES_USE_LIBC` CMake flag is now responsible for defining which
libc is
used to build compiler-rt runtime libraries. In particular, it provides
`runtimes-libc-headers` interface library, which achieves three
important goals
when we're using `llvm-libc`:
* sets up proper include directories to use LLVM-libc headers;
* ensures that LLVM-libc generated headers will be produced;
* Adds `-nostdlibinc` and propagates Linux kernel headers inclusion
paths so that
  they match what LLVM-libc itself is using.

Instead of using ad-hoc flag
`COMPILER_RT_BUILD_SCUDO_STANDALONE_WITH_LLVM_LIBC`
just rely on the value of `RUNTIMES_USE_LIBC=llvm-libc` when we're
building Scudo
allocator for use with LLVM-libc. Importantly, this fixes the

    [19 lines not shown]
DeltaFile
+11-10compiler-rt/lib/scudo/standalone/CMakeLists.txt
+5-1compiler-rt/cmake/Modules/AddCompilerRT.cmake
+2-2libc/docs/full_host_build.md
+1-1libc/docs/getting_started.md
+1-1libc/docs/build_and_test.md
+1-0.github/workflows/libc-fullbuild-tests.yml
+21-156 files