[clang] fix __builtin_clear_padding not working with virtual base pointers on Windows (#211355)
Fixes https://github.com/llvm/llvm-project/issues/209787
It was an oversight that the builtin only takes care of the virtual
function table pointer but not the virtual base pointer. On Itanium
there is one pointer so it wasn't a problem but on windows msvc , this
is a problem. And the runtime test in libcxx CI was disabled in llvm 23
because we don't use trunk clang in our libcxx CI in general. and after
we flipped to llvm 24, the test started to fail on downstream (chromium)
where they use trunk clang with trunk libc++ on Windows.
We do have FileCheck test in clang test which covers this virtual case.
However, the target triple in the FileCheck under test were
`x86_64-linux-gnu` and `x86_64-windows-gnu` , which does not cover the
Windows msvc ABI. I updated the test to test `x86_64-pc-windows-msvc` in
this PR to cover that ABI.
[SCEV] Fix MSan uninitialized value in createSCEV (#211996)
In #180244 (8e76c3f0d29a), handling of Instruction::Sub in
createSCEV declared PtrLHS and PtrRHS as uninitialized local variables.
When only one side matched m_PtrToInt, the other variable remained
uninitialized. Passing it by value to GetOp copied uninitialized shadow
bytes, causing MemorySanitizer to report use-of-uninitialized-value.
Initialize PtrLHS and PtrRHS to nullptr upon declaration.
Assisted-by: Gemini
[LTO] Include debug options in legacy ThinLTO cache keys (#211474)
Legacy ThinLTO omits -mllvm options from cache keys, which can cause it
to reuse objects built with different code-generation settings.
Include these options in cache keys, matching modern ThinLTO behavior.
clang/AMDGPU: Migrate cc1 tests to subarch triples (8) (#211870)
Rewrite SemaHIP cc1 test RUN lines to the new subarch triple form,
dropping the redundant -target-cpu.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
TableGen: Use a compact table for CPU aliases
Previously each ProcessorAlias was emitted as a full SubtargetSubTypeKV
entry in the processor subtype table, duplicating the canonical
processor's feature masks and scheduling model index. At 104 bytes per
entry: AArch64's 18 aliases added ~1.8KB, and X86 will add more as aliases
are introduced.
Emit aliases into a separate SubtargetSubTypeAliasKV table instead. Each
alias is just a name string offset plus the index of the canonical
processor it resolves to.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
X86: Use ProcessorAlias for duplicated processor names
Many X86 processors were defined multiple times under different names,
emitting an identical ProcessorModel for each spelling and duplicating
the feature masks, tune features, and scheduling model index in the subtype
table.
Define each processor once under its canonical name and express the
alternate spellings with ProcessorAlias, using the tablegen alias
mechanism. This deduplicates the redundant subtype table entries and saves
about 4.6k with the new alias table.
Co-Authored-By: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
AMDGPU: Use ProcessorAlias for legacy arch names
Older targets have aliasing names which were previously implemented
by defining a second copy of the processor, identical except for the name
Use the recently improved tablegen mechanism for defining name-only aliases.
This dedupliates some redundant table entries, like the sched model.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
TableGen: Add first class support for processor aliases
Previously isCPUStringValid was virtual so TableGen could emit an
AArch64 specific hack for recognizing cpu aliases. Teach tablegen
about aliases, and insert each alias into the CPU subtype table as its
own entry (sorted by name, carrying the canonical processor's features
and scheduling model).
There is further opportunity for code sharing improvements. AArch64's
aliases are consumed by ARMTargetDefEmitter to emit a custom inc file
in TargetParser which should be universalized.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[Passes] Replace PassInfoMixin with {Optional,Required}PassInfoMixin
There were a couple passes that landed after the mass migration that
need to be updated to eventually make PassInfoMixin private. For backend
passes I looked at whether LegacyPM passes called skipFunction rather
than whether or not they should be enabled to try and preserve existing
behavior where possible.
We still need to wait a bit in order to avoid PassInfoMixin to a detail
namespace and fully remove isRequired from PassInfoMixin given there are
a lot of out-of-tree passes that have not yet been moved over. I'm
hoping to have patches out within a week.
Reviewers: arsenm, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/211874
[clang][NFC]Remove unused variable (#211983)
The patch resolves the following warning.
```bash
clang/lib/StaticAnalyzer/Checkers/RetainCountChecker/RetainCountDiagnostics.cpp:504:16: warning: variable ‘i’ set but not used [-Wunused-but-set-variable=]
504 | unsigned i = 0;
| ^
```
A count variable was set and incremented inside of a for loop but never
actually used inside of the loop or anywhere else in its scope.
[CIR] Add support for atomic fmaximum/fminimum/fmaximumnum/fminimumnum (#211845)
This patch adds CIR support for the following atomic builtin functions:
- `__atomic_fetch_fmaximum`
- `__atomic_fetch_fminimum`
- `__atomic_fetch_fmaximumnum`
- `__atomic_fetch_fminimumnum`
The scoped versions of these atomic builtin functions are supported as
well.
Specifically, this patch contains the following changes:
- It updates the `cir.atomic.fetch` operation and adds new fetch
operators including `maximum`, `minimum`, `maximumnum`, and
`minimumnum`. These operators accept floating-point inputs only.
- It updates the LLVM lowering of the `cir.atomic.fetch` operation. The
LLVM lowering now will lower `maximum`, `minimum`, `maximumnum`, and
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[MLIR][Python] Support IsIsolatedFromAbove trait for python-defined operations (#211849)
This PR adds dynamic `IsIsolatedFromAbove` trait support and exposes it
to Python as `IsIsolatedFromAboveTrait`.
The test verifies that a region with the trait cannot capture an SSA
value from above, while a region without the trait can.
Assisted by Codex/GPT 5.6 Sol (for writing test cases).
[libclang/python] Remove CompletionString.AvailabilityKindCompat (#210682)
This completes the fourth step of
https://github.com/llvm/llvm-project/pull/156680
This change is a follow-up to
https://github.com/llvm/llvm-project/pull/160296, following the release
branching, to ensure a one release-cycle deprecation period.
---------
Co-authored-by: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>