[Transforms][Utils] Preserve branch weights in LoopSplitUtils (#213626)
Carry the original latch's branch weights onto the clamped latch, and
mark the newly created partition-guard branches as having unknown
weights so profile-tracking passes are not misled.
[X86] Add PSEUDO_FMIN/PSEUDO_FMAX to canCombineAsMaskOperation (#213475)
Add FP min/max opcodes to the list of operations that can be folded into
write-masked instructions. This allows commuteSelect to recognize these
operations and invert the setcc condition to enable ISel to match fused
vminps/vmaxps {%k} patterns.
[clang][AMDGPU] Widen ballot for read_exec_lo/hi to wavefront size (#212813)
GlobalISel cannot select a ballot narrower than the wavefront width,
since it can't represent one bit per lane
Widen the ballot to the wave size and narrow the result afterwards
This is a prerequisite for relanding
https://github.com/llvm/llvm-project/pull/211493 (reverted in
https://github.com/llvm/llvm-project/pull/212628 to unblock buildbot) to
prevent device libs side failures
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Reland [MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#213584)
This relands #211715 which was reverted because of some failures
in experimental targets and one AMDGPU test `diverged-entry-basic.ll`.
Below is the original commit message.
----
This recommits #119826, which taught `MachineLICM` to use
`RegisterClassInfo` when computing register pressure limits so
reserved registers are accounted for (#118787).
The original change was reverted by eeac0ff because it increased
compile time by causing repeated `RegisterClassInfo` computations.
This PR is based on #210826, in which `MachineRegisterClassInfo`
analysis pass was added. `MachineRegisterClassInfo` is required
by `MachineLICM` now, but the intervening machine passes that do
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[mlir][bufferization] Handle arith.select-based deallocs in static memory planner (#209106)
The static memory planner currently skips any allocation that doesn't
have a direct `memref.dealloc` user. This is overly conservative, after
running `ownership-based-buffer-deallocation`, it's common to see
patterns like:
`%2 = arith.select %c, %0, %1 : memref<1024xf32>`
`memref.dealloc %2 : memref<1024xf32>`
where both `%0` and `%1` get skipped with `++numSkipNoDealloc` even
though their lifetimes are well-defined.
This patch teaches `collectCandidates` to follow `arith.select` chains
when looking for potential deallocs. We traverse the use-def graph
forward from each alloc, collecting any `memref.dealloc` ops reachable
through select results.
Since a single select-based dealloc can conditionally free one of
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[TLI] Update `getWCharSize` documentation (NFC) (#213622)
`return 0` part of `getWCharSize` was added in cc603ee3d563 but then
removed in 5a88dffc40d2. Update the documentation as it no longer
returns 0 when the size is unknown (instead returns the default).
[ORC] Fix COFFAutoImportGeneratorTest on Darwin. (#213616)
Add linker-level mangling prefix for lookups on Darwin.
These should fix the build failures associated with PR203914 on Darwin,
e.g. https://lab.llvm.org/buildbot/#/builders/23/builds/21523
X86: Defend against regression from SimplifyDemandedVectorElts load support (#213611)
It doesn't appear possible to test this independently.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[mlir][SPIR-V] Restrict GroupNonUniform ops to Subgroup scope (#213087)
spirv-val now limits execution scope for GroupNonUniform* ops to
Subgroup, except OpGroupNonUniformRotateKHR which still allows Workgroup
(see https://github.com/KhronosGroup/SPIRV-Tools/pull/6811). Tighten the
ODS trait accordingly and stop lowering GPU non-uniform reductions to a
Workgroup scope op
Follow-up to #212928
[clang][LifetimeSafety] Fix unnamed TimeTraceScope in computePersistentOrigins (#213521)
The TimeTraceScope was constructed as a temporary and destroyed
immediately, so the prepass was reported as taking ~0. It actually
accounts for ~14% of LoanPropagation in some cases.
Co-authored-by: Gabor Horvath <gaborh at apple.com>
[lldb] Fix test_case_insensitivity's register value for canonical/PAC constraints (#213605)
This addresses a test failure introduced in
4f6cf2c2072ccf5780ac30bf69ebf99b788dbd52.
`0x1122334455667788` is a non-canonical address on x86_64 (fails to
write to rsp) and gets its non-addressing bits masked off on read for
pc/lr/sp/fp on Darwin AArch64, so it doesn't round-trip on either. Zero
the top 20 bits to stay clear of both.
[X86] Fix missing CFI after the Swift async context push (#202570)
The Swift async prologue pushes the context slot (pushq %r14 / $0) but
doesn't touch the CFA until the later .cfi_def_cfa_register %rbp. So the
CFA still describes the stack from before the push and stays stale all
the way through the leaq and the subq. If something unwinds in that
window (debugger, profiler, signal) it reads the wrong slot. Normal
execution is fine.
FIX: account for the push with .cfi_adjust_cfa_offset 8, then switch to
an %rbp-relative CFA (.cfi_def_cfa %rbp, 16) right after the leaq and
before the subq, so the rule is correct before rsp moves again.
Adds swift-async-cfi-prologue.ll (directives + .eh_frame rows, plus a
locals case for the subq) and updates swift-async.ll.
[AMDGPU] Add synthetic apertures and use them for barriers
Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
[RFC][AMDGPU] Add BARRIER address space
Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.
These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.
The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.
[clang][AMDGPU] Clean-up handling of named barrier type (#207687)
- Allow the type in struct/classes in very limited circumstances. The
goal is to enable creating trivial wrappers around the named barrier
variable, but ensure we can't get into situations where things would get
awkward. Currently this means we only allow the named barrier in
RecordDecls with exactly 1 field, that have no base class, and are not
inherited.
- Use a `amdgpu_barrier` LangAS for this type that currently maps to the
local AS. This allows easy switching to the barrier AS in a future
patch.
