[AArch64] Remove tryShiftAmountMod in favor of SelectShiftMask (#228753)
The earlier patches moved the shift-amount optimizations (AND mask,
ADD/SUB mod, NEG, MVN, ROTR) into the `SelectShiftMask` ComplexPattern,
so the variable shift/rotate instructions inherit them through the
`Shift` multiclass for both SelectionDAG and GlobalISel. With that in
place, `tryShiftAmountMod` is now redundant and this patch removes it
along with its two call sites.
Completing the removal needed a few additions so the ComplexPattern path
covers every case the old DAG routine did:
- `allUsesAreShiftAmounts` gates the `NEG`/`MVN` rewrite, so a multi-use
`C - x` amount (e.g. one that is also stored) is shared instead of being
recomputed as a separate `neg`/`mvn`.
- The matcher accepts the amount in an i32 or i64 register, with the
NEG/NOT opcode taken from the node's own type and the threshold/modulus
from the `ShiftWidth` template parameter.
- Peek-through patterns cover widened amounts: an i32 shift with an i64
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[clangd] Extract to function: Fix parameter declarator printing
A parameter's type and name were rendered by printing the type as a
standalone string and appending the name after it. That's wrong for
any declarator syntax that doesn't simply put the name after the type:
a function pointer parameter rendered as the uncompilable
`void (*)(int) F` instead of `void (*F)(int)`, and a parameter that's a
reference to an array rendered as the equally invalid `int[5] &arr`
instead of `int (&arr)[5]`.
Fixed by passing the name as printType()'s existing declarator
placeholder argument instead, letting clang's own type printer place it
correctly. For the reference case, this requires building the actual
reference QualType rather than just prepending "&" to the placeholder
string, since only the real type lets the printer parenthesize the
array case correctly.
Assisted-by: Claude Code
[mlir][DataLayout] Add getTypeAllocSize (#231262)
Add DataLayout::getTypeAllocSize, the type's size rounded up to its ABI
alignment, as in llvm::DataLayout. Use it for the three places that
computed this by hand: LLVM dialect arrays and structs, and the OpenMP
offload privatization pass. ClangIR's type layout hooks also need it.
Assisted-by: Cursor / Claude Opus 5.5
[clang][ssaf] Put clang-ssaf-orchestrator-make in LLVM_BINARY_DIR (#231930)
`clang-ssaf-orchestrator-make/CMakeLists.txt` puts the output binary in
`CMAKE_BINARY_DIR` rather than `LLVM_BINARY_DIR`, which means that when
LLVM is used as part of a larger cmake-based project via
`add_subdirectory` (such as Arm Toolchain), this tool ends up in the
project's top-level `bin` directory instead of the LLVM `bin` directory.
Tests will attempt to find it in the latter, so all of these tests fail.
[clang][ssaf] Add clang-ssaf-merge-conflict-report (#231731)
clang-ssaf-src-edit-merge reports the edits it drops because they
overlap, but only those of the one merge it ran. Add a tool that merges
such reports, so that the conflicts found while merging the edits of an
archive can be carried into the report of the program it is linked into.
[AArch64] Pre-commit tests for vector SQABS
Cover saturating absolute value expressed as UMIN of ABS and the signed
maximum for Neon and scalable vectors. Include commuted operands, poison,
multiple uses and negative cases.
Record the existing code generation so the SQABS combine can show its
effect as updates to these checks.
[mlir][flang][OpenMP] Select iterators per locator and allow multi-block regions (#227454)
Flang expands each iterator-dependent depend or affinity locator over
every
range in the clause, even iterators the locator doesn't use. For
example:
```
depend(iterator(i=1:2, j=3:m), in: a(i))
```
When m < 3, the unused j range is empty, so both dependences on a
disappear
and task ordering can be lost. When j isn't empty, the entries are just
repeated. Affinity has the same problem.
This patch picks the ranges for each locator from the iterator names
that
appear in its source, keeping declaration order. Doing that safely needs
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VE: Use i32 registers for 32-bit loads in the SjLj dispatch block (#231656)
Fix verifier errors in exception test. The call site index and the
PIC jump table offset were loaded with ldl.zx, which defines an i32
register, into vregs with the i64 register class.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Attributor: Rewrite function signatures in a deterministic order (#231802)
ArgumentReplacementMap was a DenseMap keyed by Function pointer, so
the order of the signature rewrites depended on pointer values, which
showed up as different value names in the output.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AMDGPU: Don't check liveness in AMDGPUAttributor (#231915)
AAIsDead is not in the set of AMDGPUAttributor enabled AAs, so the
liveness checks of the Attributor never find anything dead. They still
looked up AAIsDead for each visited instruction and use, for every
update.
The output IR is unchanged on the modules below. Instructions spent in
amdgpu-attributor (opt, parse cost subtracted, median of 3 runs):
rocPRIM test_device_scan, gfx942: 1963M -> 1442M (-26.5%)
Blender Cycles HIP kernel, gfx1100: 636M -> 497M (-21.9%)
rocPRIM 16 tests, full LTO, closed world: 7415M -> 5152M (-30.5%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Remove SI2_VI3Alias. NFC. (#231934)
This allowed v_ldexp_f32 and friends to be written without modifiers on
GFX8/GFX9 where they are VOP3-only. But the real VOP3 instructions
already accept these forms since modifiers, clamp and omod are optional.
[AArch64] Use multi-vector intrinsics for masked load/store users of predicate-as-counter (#220962)
If the user of the original wide mask is a masked load or store
intrinsic (matching the element size of the predicate-as-counter),
rewrite it directly to a masked multi-vector load/store.
This avoids materializing the vector mask and is easier to handle here
than later (e.g. in SelectionDAG), since we do not need to match the
concatenation of all `pext` segments of the predicate-as-counter.
Assisted-by: Codex
[flang][SystemZ] Fix test failures on s390x for target alignment, endianness and vectorizer remarks (#230565)
Fix Flang test failures on SystemZ.
i) SystemZ data layout specifies 2-byte aggregate alignment and 8-byte
fp128 alignment, handled via FileCheck variable substitutions
(-DAGG_ALIGN, -DF128_ALIGN).
ii) The default SystemZ CPU (z10) has no vector facility, so -march=z13
is passed on s390x in optimization-remark.f90 to enable vector remarks.
iii) s390x is big-endian, so s390x.* is added to select big-endian
checks in default-initialization-globals.f90 and data08.f90.
[AArch64][SME] NFC: Inline getCompatibilityForChangeToStreamingMode.
This removes the need for the `StreamingIncompatibility` enum and
makes the code a little simpler.
This PR also moves hasPossibleIncompatibleOps to AArch64TTIimpl,
so that we can query the costmodel in a follow-up PR.
[AMDGPU][SplitModule] Add entry points for unreachable call cycles (#230984)
A function in a call cycle always has an incoming direct call, so
`SplitGraph` never makes it an entry point. If no kernel and no other
entry point reaches the cycle, the cycle is assigned to no partition.
This can hit an assertion in `verifyGraph`.
In this PR, we visit the unreached nodes in reverse post-order of the
direct call edges, and make each node that is still unreached an entry
point. Only the outermost unreached cycles get one, so their callees are
not copied into other partitions.
[LoongArch] Avoid store forwarding blocks in small copies
Store-to-load forwarding fails when a load is wider than the store that
wrote its bytes, for GPR, FPR, LSX and LASX accesses alike. On LA664 such
a load takes 14-17 cycles instead of 7-10.
Small memcpy/memmove are lowered to ld.d/st.d, fld.d/fst.d, vld/vst or
xvld/xvst copies. Add a pass that breaks such a copy into smaller copies
when its load is likely to read data from in-flight narrower stores:
- A narrower store shortly before the load writes inside the copied bytes
through the same base register or frame index: break the copy around
the store.
- In a loop, a store of the previous iteration of at least 8 bytes may
write the same buffer, as in LZ77 back-reference copies: break the copy
into 8-byte pieces.
The pass runs at -O1 and above and can be disabled with
-loongarch-disable-avoid-sfb.
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[LoongArch][NFC] Pre-commit tests for store forwarding blocks in copies
Small copies whose load reads data from in-flight narrower stores,
including LZ77-style overlapping copy loops reduced from the rustc-perf
bufreader benchmark.
[offload][nfc] Decouple OpenMP offload policy from PluginManager (#220761)
PluginManager will be reused across OpenMP and OpenACC, This patch
removes PluginManager's dependency on the OpenMP offload policy.
