LLVM/project 35dcb5cclang/lib/CIR/CodeGen CIRGenDecl.cpp CIRGenFunction.h, clang/test/CIR/CodeGen cleanup-automatic-eh.cpp

[CIR] Add EH handling for lifetime extended cleanups (#192305)

This adds code to call pushDestroyAndDeferDeactivation from the
pushLifetimeExtendedDestroy function. This was needed to generate the
correct code for lifetime extended cleanups when exceptions are enabled.
An extended version of the cleanup with automatic storage duration is
used as a test case.

To make this work correctly, I had to add a CleanupDeactivationScope to
RunCleanupsScope and force deactivation when forceCleanup is called.
This matches the corresponding code in classic codegen.

I surveyed other places where classic codegen is using
CleanupDeactivationScope and added a MissingFeatures marker in one
location where it was not previously marked. Other places where it was
missing were already marked in this way.
DeltaFile
+62-0clang/test/CIR/CodeGen/cleanup-automatic-eh.cpp
+4-9clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+3-1clang/lib/CIR/CodeGen/CIRGenFunction.h
+1-0clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
+70-104 files

LLVM/project e540f80flang/include/flang/Optimizer/Dialect FIROps.td, flang/lib/Optimizer/Dialect FIROps.cpp

[flang] implements a rewrite pattern to constant fold fir::BoxEleSizeOp (#192320)

Implements a rewrite pattern to constant fold an `fir::BoxEleSizeOp`
when possible.
DeltaFile
+105-0flang/test/Fir/box-elesize-canonicalize.fir
+61-0flang/lib/Optimizer/Dialect/FIROps.cpp
+1-2flang/test/Lower/volatile-string.f90
+2-0flang/include/flang/Optimizer/Dialect/FIROps.td
+169-24 files

LLVM/project 89e736dflang/lib/Optimizer/Analysis AliasAnalysis.cpp, flang/test/Analysis/AliasAnalysis modref-call-memory-effects.fir

[flang][test] Experimental support of MemoryEffectOpInterface for fir.call. (#191580)

I would like to experiment with `fir.call` implementing
`MemoryEffectOpInterface`. So the main change is the fall-through
path in FIR AA. It should be NFC for Flang.
DeltaFile
+49-0flang/test/lib/Analysis/AliasAnalysis/TestAliasAnalysis.cpp
+28-0flang/test/Analysis/AliasAnalysis/modref-call-memory-effects.fir
+7-2flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
+84-23 files

LLVM/project 25ccdfaclang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.h

fix build issue
DeltaFile
+1-0clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
+1-01 files

LLVM/project 1f93b92clang/lib/Sema SemaAttr.cpp

concise findCXXNewExpr
DeltaFile
+2-3clang/lib/Sema/SemaAttr.cpp
+2-31 files

LLVM/project cdfd0b6clang/lib/Headers __clang_cuda_runtime_wrapper.h

[CUDA] Change __CUDACC__ definition to 1 (#189457)

I recently encountered an issue where `nccl` used `#if __CUDACC__` ,
assuming `__CUDACC__` is not only defined but having a #if-able value.


https://github.com/NVIDIA/nccl/blob/v2.28.3-1/src/include/nccl_device/coop.h#L18

Looking at nvcc invocation, I see that:
```
echo "" | nvcc -x cu -E -Xcompiler -dM - | grep __CUDACC__
#define __CUDACC__ 1
```

Changing __CUDACC__ to 1 to match what NVIDIA downstream code
assumptions.
DeltaFile
+5-5clang/lib/Headers/__clang_cuda_runtime_wrapper.h
+5-51 files

LLVM/project 7b24f05clang/lib/Sema SemaAttr.cpp

format
DeltaFile
+5-5clang/lib/Sema/SemaAttr.cpp
+5-51 files

LLVM/project f95a9b3clang/lib/Sema SemaAttr.cpp

add docs
DeltaFile
+4-0clang/lib/Sema/SemaAttr.cpp
+4-01 files

LLVM/project dc86abcllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484
DeltaFile
+7-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+7-01 files

LLVM/project e7db400llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

Formatting

Change-Id: I3d89fba145471141ef945b1de15330caa245e82d
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+8-72 files

LLVM/project dc80075llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Claude Code review

Change-Id: Iab06de2981b27667cc29a56931dd378ecf7a1b0c
DeltaFile
+115-109llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+16-26llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+5-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+136-1353 files

LLVM/project 66ff79fllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

clang-format

Change-Id: I534b1a979f55339a814ef3416c2492252845add5
DeltaFile
+6-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+6-31 files

LLVM/project 0a1d2e7llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Make fence heuristic work bottom-up

Change-Id: I629cbc8905b87a962e8b123287e5f60a3154df6b
DeltaFile
+19-17llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+19-171 files

LLVM/project 333b8d3llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add comment

Change-Id: I2180bba631fe4a01ed3c3fbcfa8c19cbefa84133
DeltaFile
+1-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-01 files

LLVM/project 7bd577ellvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

[AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5
DeltaFile
+323-0llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+77-23llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+18-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+418-233 files

LLVM/project 4a4e98fllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Typo

Change-Id: I8b8da8a07be84506483f474d0a5e10ad79178c15
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+1-11 files

LLVM/project de914f9llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

[AMDGPU] Add stalls for DS FIFO buffer

Change-Id: I73e56da97a931349e0655e4e20b24aeb97920647
DeltaFile
+61-54llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+41-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+41-5llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+143-653 files

LLVM/project 253d61allvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f
DeltaFile
+7-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+7-11 files

LLVM/project 646831cllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

[AMDGPU] Add block carried latency to CoExecSched

Change-Id: Ib04e40e57d38e127d6c5452d1719e32dacef2ade
DeltaFile
+880-4llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+167-67llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+0-37llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+23-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+0-4llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+1,070-1185 files

LLVM/project a21d492llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Merge conflicts

Change-Id: I33564a1e5d14f3b53577cb463ba2cb3a7993fd24
DeltaFile
+50-57llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+54-602 files

LLVM/project 508a211llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Merge conflict

Change-Id: I24f471688f9d0604b45e95a4fa4da85fb0d9ed76
DeltaFile
+23-22llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+27-4llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+50-262 files

LLVM/project 419867fllvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h

Claude Code review

Change-Id: Id4983ca59270c8bb2d261d38a6e7f2483c9d237e
DeltaFile
+15-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+16-12 files

LLVM/project f898e26llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

[AMDGPU] Address follow-up concerns from 189121

Change-Id: I7ae986ab2a22d7e8a8a04a8d3923412b6688ad99
DeltaFile
+20-21llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+6-9llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+26-302 files

LLVM/project cc5cd70clang/lib/Sema SemaTemplateInstantiateDecl.cpp, clang/test/Sema/Inputs lifetime-analysis.h

fix spaces
DeltaFile
+1-1clang/test/Sema/Inputs/lifetime-analysis.h
+0-1clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
+1-22 files

LLVM/project 9fb6c65llvm/lib/Target/PowerPC PPCISelLowering.cpp PPCInstrInfo.cpp, llvm/test/CodeGen/PowerPC amo-enable.ll

[PowerPC] Rework AMO load with Compare and Swap Not Equal to use post-RA pseudo expansion (#190698)

Replace the dummy call lowering with a PPCPostRAExpPseudo that hardcodes
X8/X9/X10 post-RA to satisfy the 3 consecutive register constraint for
lwat/ldat FC=16, addressing reviewer feedback.
DeltaFile
+106-54llvm/test/CodeGen/PowerPC/amo-enable.ll
+1-44llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+42-0llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+0-21llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+13-0llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+13-0llvm/lib/Target/PowerPC/PPCInstrInfo.td
+175-1192 files not shown
+176-1208 files

LLVM/project 887e5a0clang/lib/Sema SemaAttr.cpp, clang/test/Sema warn-lifetime-safety.cpp

infer only for reference types
DeltaFile
+8-6clang/test/Sema/warn-lifetime-safety.cpp
+5-4clang/lib/Sema/SemaAttr.cpp
+13-102 files

LLVM/project 4df814amlir/include/mlir/Dialect/XeGPU/IR XeGPUAttrs.td, mlir/lib/Dialect/XeGPU/IR XeGPUDialect.cpp XeGPUOps.cpp

[MLIR][XeGPU] Refactor isEvenlyDistributable() to Layout attribute interface (#191945)

This PR refactor isEvenlyDistributable() to layout attribute interface
isDistributable(), and used them in all anchor operations to check the
shape can be ditributed with the anchor layout.
DeltaFile
+4-84mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+61-3mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
+53-7mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+11-11mlir/test/Dialect/XeGPU/transform-ops.mlir
+8-8mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
+0-8mlir/test/Dialect/XeGPU/invalid.mlir
+137-1212 files not shown
+138-1268 files

LLVM/project 27ff651clang/lib/Basic/Targets TCE.h TCE.cpp, clang/test/CodeGen target-data.c

[OpenASIP] Update the TCE target defs for OpenASIP 2.2 (#176698)

OpenASIP (ex. TCE*) is a special target which has only a stub target
definition in the LLVM side that has resided in LLVM for over 15 years.
I'm the original contributors of this stub.

Due to needing various other patches to LLVM that were not nicely
upstreamable, the upstream TCE target defs have long been unupdated.
However, with the recent changes to the vectorization types etc. I
managed to minimize the required LLVM TCE patch to this one and with
this patch OpenASIP can be (finally!) used without a patched LLVM for
VLIW/TTA customization. RISC-V operation set customization still
requires a patch to polish and upstream (TBD).

This patch:

* Introduces a 64b variant of an OpenASIP target.
* Unifies the datalayouts of the different target variants to make it
compatible with OpenASIP v2.2 and above.

    [17 lines not shown]
DeltaFile
+50-9clang/lib/Basic/Targets/TCE.h
+28-24llvm/include/llvm/TargetParser/Triple.h
+15-1llvm/lib/TargetParser/Triple.cpp
+13-0llvm/lib/TargetParser/TargetDataLayout.cpp
+12-0clang/lib/Basic/Targets/TCE.cpp
+6-2clang/test/CodeGen/target-data.c
+124-365 files not shown
+145-3611 files

LLVM/project 646c43fclang/test/Sema warn-lifetime-safety.cpp warn-lifetime-safety-suggestions.cpp

format test. add negative test.
DeltaFile
+15-4clang/test/Sema/warn-lifetime-safety.cpp
+1-2clang/test/Sema/warn-lifetime-safety-suggestions.cpp
+16-62 files

LLVM/project 4f20676clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded vpairo.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded vpaire.c vpairo.c

Merge branch 'users/ziqingluo/PR-172429193-2-split-1' into users/ziqingluo/PR-172429193-2-split-2

 Conflicts:
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.h
        clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
DeltaFile
+6,877-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-sve-instructions.s
+5,336-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-writeback.s
+3,167-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-neon-instructions.s
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
+2,723-0clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
+23,549-0678 files not shown
+87,707-9,845684 files