569,981 commits found in 29 milliseconds
LLVM /project 3ccfbc8 — lldb/source/Core Debugger.cpp, lldb/test/API/functionalities/statusline TestStatusline.py [lldb] Make sure changing the separator takes immediate effect (#136779)
The setter is only used when changing the setting programmatically. When
using the settings command, we need to monitor SetPropertyValue. [mlir][bazel] Port e112dccc8ba49425c575a6b15325f2cbeef5c606 .
[libc][math] Skip checking for exceptional values in expm1f when LIBC_MATH_SKIP_ACCURATE_PASS is set. (#130968)
LLVM /project 141c14c — llvm/test/CodeGen/LoongArch/lasx widen-shuffle-mask.ll, llvm/test/CodeGen/LoongArch/lsx widen-shuffle-mask.ll [LoongArch] Pre-commit for widen shuffle mask (#136544)
[clang] Rework `hasBooleanRepresentation`. (#136038)
This is a follow-up of 13aac46332f607a38067b5ddd466071683b8c255 .
This commit adjusts the implementation of `hasBooleanRepresentation` to
be somewhat aligned to `hasIntegerRepresentation`.
In particular vector of booleans should be handled in
`hasBooleanRepresentation`, while `_Atomic(bool)` should not. [RISCV] Remove stale comment. NFC
[clang-format] Don't test stability if JS format test fails (#136662)
LLVM /project 037657d — clang/lib/Format TokenAnnotator.cpp, clang/unittests/Format TokenAnnotatorTest.cpp [clang-format] Correctly annotate kw_operator in using decls (#136545)
Fix #136541 LLVM /project 9efabbb — clang/lib/Format FormatTokenLexer.cpp FormatTokenLexer.h, clang/unittests/Format TokenAnnotatorTest.cpp [clang-format] Fix a bug in lexing C++ UDL ending in $ (#136476)
Fix #61612 LLVM /project 4f71655 — clang/lib/Format UnwrappedLineParser.cpp, clang/unittests/Format TokenAnnotatorTest.cpp [clang-format] Fix a bug in parsing C-style cast of lambdas (#136099)
Fix #135959 Address review comments.
Created using spr 1.3.6-beta.1
[𝘀𝗽𝗿] changes to main this commit is based on
Created using spr 1.3.6-beta.1
[skip ci]
LLVM /project b9cf383 — llvm/lib/CodeGen LiveRangeShrink.cpp, llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp [𝘀𝗽𝗿] initial version
Created using spr 1.3.6-beta.1
[𝘀𝗽𝗿] initial version
Created using spr 1.3.6-beta.1
LLVM /project 11c0913 — clang/lib/CodeGen CodeGenModule.cpp, llvm/include/llvm/IR Metadata.h Address review comments.
Created using spr 1.3.6-beta.1
LLVM /project 82f8060 — llvm/include/llvm/IR Metadata.h, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
LLVM /project 89c896b — llvm/include/llvm/IR Metadata.h, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp Rebase on parent llvm change.
Created using spr 1.3.6-beta.1
LLVM /project 7a1c8fb — llvm/include/llvm/IR Metadata.h, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp [𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
LLVM /project 80df0c0 — llvm/include/llvm/IR Metadata.h, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp Address review comments.
Created using spr 1.3.6-beta.1
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Move verifier down to parent change.
Created using spr 1.3.6-beta.1
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Rebase on parent change.
Created using spr 1.3.6-beta.1
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Verifier changes.
Created using spr 1.3.6-beta.1
gn build: Port d1cce66469d0 more
LLVM /project 2484060 — llvm/lib/Target/RISCV RISCVFoldMemOffset.cpp, llvm/test/CodeGen/RISCV fold-mem-offset.mir [RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
Any kill flags that were present for the old register are not valid for
the replacement and the replacement may have extended the live range of
the replacement register. [MLIR] [python] Fixed the signature of `_OperationBase.get_asm` (#136676)
It claimed to return an `io.StringIO` or an `io.BytesIO`, but it did in
fact return `str` or `bytes`. LLVM /project fb9ba07 — llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/Transforms/InferAddressSpaces/AMDGPU alloca-as0.ll [AMDGPU] Make `AllocaInst` return AS5 in `getAssumedAddrSpace`
LLVM /project ae09399 — llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU alloca-as0.ll assert-wrong-alloca-addrspace.ll [AMDGPU] Support alloca in AS0
This PR lowers an alloca in AS0 to an alloca in AS5 followed by an addrspacecast
back to AS0.