LLVM/project 1bfeb2fllvm/docs NVPTXUsage.rst NVPTXUsage.md, llvm/test/CodeGen/NVPTX atomicrmw-sm60.ll atomicrmw-sm70.ll

rebase

Created using spr 1.3.5-bogner
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+0-4,767llvm/docs/NVPTXUsage.rst
+2,949-1,487llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+2,871-1,461llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+4,253-0llvm/docs/NVPTXUsage.md
+3,624-0mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+1,635-849llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+15,332-8,5644,684 files not shown
+126,127-64,3784,690 files

LLVM/project b9ebe54llvm/docs NVPTXUsage.rst NVPTXUsage.md, llvm/test/CodeGen/NVPTX atomicrmw-sm60.ll atomicrmw-sm70.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5-bogner

[skip ci]
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+0-4,767llvm/docs/NVPTXUsage.rst
+2,949-1,487llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+2,871-1,461llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+4,253-0llvm/docs/NVPTXUsage.md
+3,624-0mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+1,635-849llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+15,332-8,5644,684 files not shown
+126,127-64,3784,690 files

LLVM/project 54b3fd0llvm/docs NVPTXUsage.rst NVPTXUsage.md, llvm/test/CodeGen/NVPTX atomicrmw-sm60.ll atomicrmw-sm70.ll

remove getThreadIndex()

Created using spr 1.3.5-bogner
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+0-4,767llvm/docs/NVPTXUsage.rst
+2,949-1,487llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+2,871-1,461llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+4,253-0llvm/docs/NVPTXUsage.md
+3,624-0mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+1,635-849llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+15,332-8,5644,684 files not shown
+126,127-64,3784,690 files

LLVM/project bcb4e7dllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-fdiv.ll

[InstCombine] Fix 0.0 / x -> 0 folds when the divisor may be zero (#202482)

SimplifyDemandedUseFPClass folded 0/x to a signed zero, guarded only on
the divisor being non-NaN. But when x==0, the result is is NaN, not 0!

Require the divisor to be never (logical) zero, unless a NaN result
isn't demanded.
DeltaFile
+105-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
+12-5llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+117-52 files

LLVM/project 220e827llvm/include/llvm/IR PassManagerInternal.h, llvm/unittests/IR PassManagerTest.cpp

[IR][NFC] Avoid unneccessary move of analysis results (#210540)

While benchmarking CycleAnalysis, I noticed that each analysis result is
constructed on the stack first and then moved to its final place on the
heap. This is unnecessary -- directly construct the analysis result in
its final place. Consequently, analysis results can be immovable.
DeltaFile
+12-33llvm/include/llvm/IR/PassManagerInternal.h
+5-0llvm/unittests/IR/PassManagerTest.cpp
+17-332 files

LLVM/project b0be6ecllvm/include/llvm/IR PassManagerInternal.h, llvm/unittests/IR PassManagerTest.cpp

[spr] initial version

Created using spr 1.3.8-wip
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+12-33llvm/include/llvm/IR/PassManagerInternal.h
+5-0llvm/unittests/IR/PassManagerTest.cpp
+17-332 files

LLVM/project 24c0027llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[AMDGPU] Enabled GCNTrackers in GCNMaxOccupancySchedStrategy.

https://github.com/llvm/llvm-project/pull/169616 introduced scheduling
strategy specific GCNTrackers. This PR follows that template and
enables GCNTrackers for the max-occupancy strategy.

Depends on https://github.com/llvm/llvm-project/pull/184275.

Assisted-by: Cursor/Claude Opus
DeltaFile
+73,543-73,116llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+13,031-13,122llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+3,785-3,654llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+3,696-3,670llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+3,193-3,014llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+2,690-2,887llvm/test/CodeGen/AMDGPU/load-local-i16.ll
+99,938-99,463132 files not shown
+139,455-136,476138 files

LLVM/project d89537dllvm/lib/Target/DirectX DXContainerGlobals.cpp, llvm/lib/Target/DirectX/DXILWriter DXILWriterPass.cpp

[DirectX] Fix `--dx-embed-debug` flag dependency (#210513)

This patch moves the definition of `cl::opt<std::string> PdbDebugPath`
from `DXContainerGlobals.cpp` to `DXILWriter/DXILWriterPass.cpp`,
reversing the dependency.
Fixes the layering violation in #204166.
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+5-1llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
+1-5llvm/lib/Target/DirectX/DXContainerGlobals.cpp
+6-62 files

LLVM/project 5c30a1emlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

[mlir-c] Expose hard-failure state in 1:N type conversion callback

The 1:N conversion callback returned MlirLogicalResult, which the binding
could only map to success or nullopt (try-another), leaving the C++
failure() state (fail without trying another conversion) unreachable.

Return a MlirTypeConverterConversionStatus enum instead, with Success,
Failure, and Declined states mapped to success(), failure(), and
std::nullopt respectively. Add a test covering the hard-failure path.
DeltaFile
+99-12mlir/test/CAPI/rewrite.c
+18-6mlir/include/mlir-c/Rewrite.h
+12-3mlir/lib/CAPI/Transforms/Rewrite.cpp
+129-213 files

LLVM/project 2e42e0cmlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

[mlir-c] Expose hard-failure state in 1:N type conversion callback

The 1:N conversion callback returned MlirLogicalResult, which the binding
could only map to success or nullopt (try-another), leaving the C++
failure() state (fail without trying another conversion) unreachable.

Return a MlirTypeConverterConversionStatus enum instead, with Success,
Failure, and Declined states mapped to success(), failure(), and
std::nullopt respectively. Add a test covering the hard-failure path.
DeltaFile
+99-12mlir/test/CAPI/rewrite.c
+11-6mlir/include/mlir-c/Rewrite.h
+12-3mlir/lib/CAPI/Transforms/Rewrite.cpp
+122-213 files

LLVM/project 785b595mlir/test/CAPI rewrite.c

pre-increment
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+6-6mlir/test/CAPI/rewrite.c
+6-61 files

LLVM/project 56262f3mlir/lib/Bindings/Python Rewrite.cpp

[mlir-c] Value-initialize MlirConversionPatternCallbacks in Python bindings

The Python conversion-pattern binding left the struct default-initialized,
so the newly-added optional matchAndRewrite1ToN field held an indeterminate
pointer. The driver's null check then read garbage and jumped into it,
segfaulting mlir/test/python/rewrite.py. Value-initialize the struct so
optional callbacks default to null.
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+3-1mlir/lib/Bindings/Python/Rewrite.cpp
+3-11 files

LLVM/project abb0b4emlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

[mlir-c] Add 1:N TypeConverter conversion and materialization bindings

Builds on the source/target materialization C bindings:

- Target materialization callbacks now receive `originalType` (split from the
  previously-shared source/target callback typedef), exposing a documented C++
  capability that was otherwise unreachable from C.
- 1:N type conversion: `mlirTypeConverterAdd1ToNConversion` plus an opaque
  results accumulator (`MlirTypeConverterConversionResults` /
  `mlirTypeConverterConversionResultsAppend`). A declining callback's appended
  types are rolled back so the driver's "try the next conversion" invariant
  holds.
- 1:N target materialization: `mlirTypeConverterAdd1ToNTargetMaterialization`,
  whose callback fills a caller-allocated `outputs` buffer. A success that
  leaves any output null is treated as a decline rather than handing the driver
  a null-containing result.
- `mlirConversionPatternRewriterReplaceOpWithMultiple` for 1:N value
  replacement, which can drive a source materialization with nInputs > 1.
- An optional `matchAndRewrite1ToN` callback on `MlirConversionPatternCallbacks`

    [9 lines not shown]
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+731-2mlir/test/CAPI/rewrite.c
+153-14mlir/lib/CAPI/Transforms/Rewrite.cpp
+103-5mlir/include/mlir-c/Rewrite.h
+987-213 files

LLVM/project 0f794b4mlir/test/CAPI rewrite.c

[mlir-c] Fix -Wmissing-field-initializers in rewrite.c test

The new matchAndRewrite1ToN field left three existing
MlirConversionPatternCallbacks initializers under-initialized, which
fails the CI build under -Werror=-Wmissing-field-initializers.
DeltaFile
+4-3mlir/test/CAPI/rewrite.c
+4-31 files

LLVM/project 97d9dbemlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

cleanup comments
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+2-18mlir/include/mlir-c/Rewrite.h
+0-12mlir/lib/CAPI/Transforms/Rewrite.cpp
+2-302 files

LLVM/project d88556dmlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

[mlir-c] Use a status enum for the type conversion callback

The 1:1 conversion callback returned MlirLogicalResult and encoded the
three C++ conversion states implicitly: returning failure meant "try
another conversion", while returning success with a null out-parameter
meant a hard failure. This dual encoding was easy to misuse and the doc
comment conflated the two.

Return a MlirTypeConverterConversionStatus enum with explicit Success,
Failure (do not try another), and Declined (try another) states, and add
a test covering the decline-fallback and hard-failure paths.
DeltaFile
+72-5mlir/test/CAPI/rewrite.c
+20-5mlir/include/mlir-c/Rewrite.h
+13-5mlir/lib/CAPI/Transforms/Rewrite.cpp
+105-153 files

LLVM/project 6d70017. .mailmap

mailmap: Add entries for Peter Collingbourne. (#210526)

I am no longer at Google.
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+2-0.mailmap
+2-01 files

LLVM/project 4812a67clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn.hip builtins-amdgcn-vi-f16.hip

[CIR][AMDGPU] Add support for AMDGCN frexp_mant builtins (#198121)

Adds codegen for the following AMDGCN frexp mantissa builtins:

- __builtin_amdgcn_frexp_mant (double)
- __builtin_amdgcn_frexp_mantf (float)
- __builtin_amdgcn_frexp_manth (half)

These are lowered to the corresponding `llvm.amdgcn.frexp.mant`
intrinsic.
DeltaFile
+16-0clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+8-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
+2-4clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+26-43 files

LLVM/project acd3fcfclang/lib/CodeGen CodeGenModule.cpp, clang/test/CodeGen call-graph-section.cpp call-graph-section-templates.cpp

[clang] Emit call graph type metadata for internal linkage symbols (#210194)
DeltaFile
+18-18clang/test/CodeGen/call-graph-section.cpp
+18-16clang/lib/CodeGen/CodeGenModule.cpp
+13-13clang/test/CodeGen/call-graph-section-templates.cpp
+9-9llvm/test/CodeGen/ARM/call-graph-section-assembly.ll
+8-8llvm/test/CodeGen/X86/call-graph-section-tailcall.ll
+8-8clang/test/CodeGen/call-graph-section.c
+74-7214 files not shown
+135-13720 files

LLVM/project f9b7acblld/ELF Relocations.h

[NFC][ELF] Remove unused R_TLS*_HINT RelExprs (#210519)

As of 5e87f8147d68 ("[ELF] Add target-specific relocation scanning for
PPC32 (#181517)") these are never generated, and as of 46d29d43ba8e
("[ELF] Remove unused handleTlsRelocation (#184951)") these are not even
handled anywhere.
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+0-2lld/ELF/Relocations.h
+0-21 files

LLVM/project 2144ee4lld/ELF Relocations.h

[NFC][ELF] Remove unused R_TLSDESC_CALL RelExpr (#210518)

As of 4ea72c1e8cbd ("[ELF] Add target-specific relocation scanning for
RISC-V (#181332)") this is never generated, and as of 46d29d43ba8e
("[ELF] Remove unused handleTlsRelocation (#184951)") this is not even
handled anywhere.
DeltaFile
+0-1lld/ELF/Relocations.h
+0-11 files

LLVM/project 0b5073alld/ELF InputSection.cpp Relocations.h

[NFC][ELF] Remove unused R_RELAX_TLS_* RelExprs (#210517)

As of 46d29d43ba8e ("[ELF] Remove unused handleTlsRelocation (#184951)")
these are never generated.
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+0-7lld/ELF/InputSection.cpp
+0-7lld/ELF/Relocations.h
+0-142 files

LLVM/project 6e4eadcflang/lib/Parser openmp-parsers.cpp, llvm/include/llvm/Frontend/OpenMP OMP.h

[OpenMP] Add constexpr enum ranges for all clauses and all directives
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+9-0llvm/include/llvm/Frontend/OpenMP/OMP.h
+2-5flang/lib/Parser/openmp-parsers.cpp
+2-4llvm/lib/Frontend/OpenMP/OMP.cpp
+2-4llvm/unittests/Frontend/OpenMPDirectiveNameParserTest.cpp
+15-134 files

LLVM/project c739ce6llvm/test/TableGen subreg-index-overflow-allowed.td subreg-index-overflow.td, llvm/utils/TableGen/Common CodeGenRegisters.cpp CodeGenRegisters.h

[TableGen] Diagnose sub-register indices that overflow their register (#206346)
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+79-0llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+37-0llvm/test/TableGen/subreg-index-overflow-allowed.td
+29-0llvm/test/TableGen/subreg-index-overflow.td
+5-0llvm/utils/TableGen/Common/CodeGenRegisters.h
+150-04 files

LLVM/project 53096b7llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86/apx sub.ll

[X86][APX] Optimize usub.sat(X,1) to cmp+adc with NDD (#208475)

When NDD is available, usub.sat(X, 1) is lowered from xor+sub+cmov (3
insns) to cmp+adc (2 insns).

All X86 tests pass.

Fixes #207888

Co-authored-by: AntonyCJ30 <cj6186609 at gmail@gmail.com>
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+24-2llvm/lib/Target/X86/X86ISelLowering.cpp
+212-1972 files

LLVM/project be68a88llvm/include/llvm/ADT Sequence.h

[ADT] Fix non-assertion build after 36c812f771 (#210511)

E.g. https://lab.llvm.org/buildbot/#/builders/228/builds/5253
DeltaFile
+7-2llvm/include/llvm/ADT/Sequence.h
+7-21 files

LLVM/project f6d9ec4clang/lib/Headers riscv_packed_simd.h, clang/test/CodeGen/RISCV rvp-intrinsics.c

[RISCV] Add packed narrowing convert intrinsics (#210389)

Add RISC-V P-extension packed narrowing convert header APIs for `pncvt`
and `pncvth`.

The new APIs lower through generic IR: RV32 uses truncate / logical
shift plus truncate forms, while RV64 uses existing packed unzip shuffle
forms. This reuses the existing backend lowering and TableGen aliases
rather than adding intrinsic-specific lowering.

Tests cover Clang IR generation and cross-project header assembly checks
for RV32/RV64 spec-listed mnemonics.
DeltaFile
+158-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+50-0clang/lib/Headers/riscv_packed_simd.h
+42-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+250-03 files

LLVM/project 94b08b5llvm/lib/Support/Unix Signals.inc

[Support] Improve the logic for re-raising signals (#177864)

On most systems, checking `si_pid` is not actually valid unless
`si_code` equals one of the relevant signal codes (`SI_USER`,
`SI_QUEUE`, and on some OSs, `SI_LWP`), or the signal is `SIGCHLD`. So
on e.g. NetBSD, we would misinterpret the `SIGSEGV` fault address as the
sending PID and incorrectly conclude that the signal came from a
different process.

But as far as I can tell, there's not even a valid reason for us to be
checking `si_pid != getpid()`, because the signal could very well have
been explicitly sent by another thread in the current process. So we
really just need to check `si_code` for the aforementioned signal codes.

Darwin is the exception because it just doesn't set `si_code` at all in
the case of the `SI_*` signal codes. So keep the old logic there, even
though it misses the corner case of signals sent by a thread in the
current process.


    [4 lines not shown]
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+33-12llvm/lib/Support/Unix/Signals.inc
+33-121 files

LLVM/project af0c933llvm/test/CodeGen/PowerPC ppcf128-constrained-fp-intrinsics.ll, llvm/test/Transforms/EarlyCSE replace-calls-def-attrs.ll

[IR] Make semantics of strictfp consistent (#209465)

Although the section on constrainedfp in the LangRef clearly states "All
function definitions that use constrained floating point intrinsics must
have the strictfp attribute", indicating that a function with strictfp
calls must be marked with strictfp, the general description of strictfp
does not specify this. Refine its semantics and make it so, eliminating
the inconsistency.
DeltaFile
+35-32llvm/test/Transforms/EarlyCSE/replace-calls-def-attrs.ll
+25-25mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+22-18llvm/test/Transforms/InstCombine/erf.ll
+16-14llvm/test/Transforms/SimplifyCFG/X86/merge-compatible-invokes-of-landingpad.ll
+24-0llvm/unittests/IR/VerifierTest.cpp
+2-14llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
+124-10317 files not shown
+169-13623 files

LLVM/project 2b90a32llvm/include/llvm/ADT Sequence.h

format
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+2-2llvm/include/llvm/ADT/Sequence.h
+2-21 files