LLVM/project 765b64butils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy BUILD.bazel

[bazel] Port 92f16356340d230f04e67d9d7b8f3d91b9f0513b
DeltaFile
+1-0utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy/BUILD.bazel
+1-01 files

LLVM/project 222dcb3mlir/include/mlir/Dialect/SparseTensor/IR SparseTensorOps.td, mlir/include/mlir/Interfaces ControlFlowInterfaces.h

reorganize code
DeltaFile
+11-275mlir/lib/Dialect/SCF/IR/SCF.cpp
+282-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+17-17mlir/test/Dialect/SparseTensor/sparse_out.mlir
+8-8mlir/test/Dialect/SparseTensor/sparse_kernels.mlir
+7-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+3-4mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
+328-3041 files not shown
+331-3077 files

LLVM/project 75522acmlir/include/mlir/Interfaces ControlFlowInterfaces.h, mlir/lib/Dialect/SCF/IR SCF.cpp

reorganize code
DeltaFile
+11-275mlir/lib/Dialect/SCF/IR/SCF.cpp
+281-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+17-17mlir/test/Dialect/SparseTensor/sparse_out.mlir
+8-8mlir/test/Dialect/SparseTensor/sparse_kernels.mlir
+7-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+3-3mlir/test/Dialect/Vector/vector-warp-distribute.mlir
+327-3036 files

LLVM/project 8b2bcb7mlir/include/mlir/Interfaces ControlFlowInterfaces.td, mlir/lib/Dialect/SCF/IR SCF.cpp

[mlir][draft] Consolidate patterns into RegionBranchOpInterface patterns

fix some tests
DeltaFile
+280-854mlir/lib/Dialect/SCF/IR/SCF.cpp
+39-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+17-17mlir/test/Dialect/SparseTensor/sparse_out.mlir
+11-13mlir/test/Dialect/SCF/canonicalize.mlir
+8-8mlir/test/Dialect/SparseTensor/sparse_kernels.mlir
+9-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+364-8924 files not shown
+377-90210 files

LLVM/project 07adecflibcxx/docs/Status Cxx2cIssues.csv, libcxx/include optional

[libc++] Resolve LWG4370 (#174062)

Resolves #171364

- Implement [proposed resolution of LWG4370](https://wg21.link/LWG4370)
- Add corresponding compile test
DeltaFile
+36-12libcxx/include/optional
+40-0libcxx/test/std/utilities/optional/optional.relops/relops.compile.pass.cpp
+1-1libcxx/docs/Status/Cxx2cIssues.csv
+77-133 files

LLVM/project 904dbbfmlir/include/mlir/Transforms Passes.td Passes.h, mlir/lib/Transforms RemoveDeadValues.cpp

tmp commit

simple test working

draft: do not erase IR, just replace uses
DeltaFile
+184-328mlir/lib/Transforms/RemoveDeadValues.cpp
+110-45mlir/test/Transforms/remove-dead-values.mlir
+10-0mlir/include/mlir/Transforms/Passes.td
+1-0mlir/include/mlir/Transforms/Passes.h
+305-3734 files

LLVM/project 4c4344fllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-shufflevector.ll

InstCombine: Rudimentary support of shufflevector in SimplifyDemandedFPClass

This should look more like the computeKnownFPClass handling, with knowledge
of demanded vector elements.
DeltaFile
+269-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-shufflevector.ll
+11-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+280-02 files

LLVM/project b43927cllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-insertelement.ll

InstCombine: Basic insertelement support for SimplifyDemandedFPClass

Eventually this should pull up the known elements logic from
computeKnownFPClass.
DeltaFile
+187-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-insertelement.ll
+10-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+197-02 files

LLVM/project 78c49c5llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Fix defining undef constant vector elts in SimplifyDemandedFPClass

Fold constants of known single class to the original constant instead of
a new constant. This avoids overdefining vector elements that were originally
undefined with the splat constant.
DeltaFile
+29-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+12-2llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+41-22 files

LLVM/project 0b24580mlir/include/mlir/Interfaces ControlFlowInterfaces.td ControlFlowInterfaces.h, mlir/lib/Analysis/DataFlow SparseAnalysis.cpp

[mlir][Interfaces][NFC] Add `RegionBranchOpInterface` helper for forwarded values (#173981)

Add a helper function to compute a mapping of successor operands to
successor inputs. This mapping is computed in various places. Also add a
helper function to gather all region branch points.

This commit is in preparation of a bug fix / partial redesign of
`-remove-dead-values`. This commit also removes some duplicate code in
various places.
DeltaFile
+21-29mlir/lib/Analysis/DataFlow/SparseAnalysis.cpp
+22-23mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+44-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+6-31mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp
+9-14mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+13-0mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+115-976 files

LLVM/project 5ee82dfllvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/X86 cast-costs.ll cost-model.ll

[VPlan] Handle addrspacecast/ptrtoaddr in VPlan-based cost model.

Also handle missing PtrToAddrs and AddrSpaceCast in
getCostForRecipeWithOpcode.

This makes sure all cast opcodes are handled, fixing a crash on loops
replicating addrspacecast and ptrtoaddrs.
DeltaFile
+221-0llvm/test/Transforms/LoopVectorize/X86/cast-costs.ll
+0-99llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+6-2llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+227-1013 files

LLVM/project 33ddbfdllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

InstCombine: Fix another wrong interested mask computeKnownFPClass call (#174135)

Follow up from c436551d5283a8fc00ae880a5b76660b6f08e37b, this is another
instance of the same problem.
DeltaFile
+1-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+1-11 files

LLVM/project 92f1635clang-tools-extra/clang-tidy/google UnnamedNamespaceInHeaderCheck.cpp UnnamedNamespaceInHeaderCheck.h, clang-tools-extra/clang-tidy/misc AnonymousNamespaceInHeaderCheck.cpp AnonymousNamespaceInHeaderCheck.h

[clang-tidy] Rename google-build-namespaces to misc-anonymous-namespace-in-header (#173484)

This PR renames the check `google-build-namespaces` to
`misc-anonymous-namespace-in-header` and adds documentation on why
anonymous namespaces in headers are problematic.

Closes #170979
DeltaFile
+0-52clang-tools-extra/test/clang-tidy/checkers/google/namespaces.cpp
+52-0clang-tools-extra/test/clang-tidy/checkers/misc/anonymous-namespace-in-header.cpp
+41-0clang-tools-extra/clang-tidy/misc/AnonymousNamespaceInHeaderCheck.cpp
+0-40clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.cpp
+0-40clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.h
+39-0clang-tools-extra/clang-tidy/misc/AnonymousNamespaceInHeaderCheck.h
+132-13213 files not shown
+192-14919 files

LLVM/project deaed48llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

InstCombine: Fix another wrong interested mask computeKnownFPClass call

Follow up from c436551d5283a8fc00ae880a5b76660b6f08e37b, this is another
instance of the same problem.
DeltaFile
+1-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+1-11 files

LLVM/project e2e2c50llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[AMDGPU][NPM] Disable few non useful passes (#172796)

Matches the legacy pipeline
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+5-52 files

LLVM/project ebb1c27mlir/lib/Dialect/Linalg/IR LinalgOps.cpp, mlir/python/mlir/dialects/linalg/opdsl/lang emitter.py

[mlir][linalg] Reject unsigned pooling on non-integer element types (#166070)

Fixes: #164800 

Ensures unsigned pooling ops in Linalg stay in the integer domain: the
lowering now rejects floating/bool inputs with a clear diagnostic, new
regression tests lock in both the error path and a valid integer
example, and transform decompositions are updated to reflect the integer
typing.

Signed-off-by: Akimasa Watanuki <mencotton0410 at gmail.com>
DeltaFile
+119-0mlir/test/Dialect/Linalg/invalid.mlir
+72-0mlir/test/Dialect/Linalg/named-ops.mlir
+48-0mlir/test/python/dialects/linalg/opdsl/emit_pooling.py
+14-14mlir/test/Dialect/Linalg/transform-op-decompose.mlir
+12-6mlir/python/mlir/dialects/linalg/opdsl/lang/emitter.py
+14-4mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+279-242 files not shown
+279-388 files

LLVM/project 5d0730bllvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[CodeGen][NPM] Add "PhysicalRegisterUsageAnalysis" once
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+1-4llvm/include/llvm/Passes/CodeGenPassBuilder.h
+4-72 files

LLVM/project ac37230llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[AMDGPU][NPM] Complete fast regalloc pipeline
DeltaFile
+38-0llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-1llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+39-12 files

LLVM/project ce33105llvm/lib/CodeGen LiveIntervals.cpp

[CodeGen][NPM] dump slot index info with -debug while running LiveIntervals
DeltaFile
+4-2llvm/lib/CodeGen/LiveIntervals.cpp
+4-21 files

LLVM/project fd0d859llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp

[AMDGPU][NPM] Obey "enable-amdgpu-aa" option
DeltaFile
+2-1llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+2-11 files

LLVM/project f08174dllvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[AMDGPU][NPM] Disable few non useful passes
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+5-52 files

LLVM/project 30b5dd0llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[AMDGPU][NPM] Enable "AMDGPURewriteAGPRCopyMFMAPass"
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+2-0llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+4-22 files

LLVM/project 3428f10llvm/lib/CodeGen BranchFolding.cpp BranchRelaxation.cpp, llvm/lib/Target/AMDGPU SIPreEmitPeephole.cpp

[CodeGen][NPM] Update dominator tree and post dominator tree consistently
DeltaFile
+11-2llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+11-1llvm/lib/CodeGen/BranchFolding.cpp
+10-1llvm/lib/CodeGen/BranchRelaxation.cpp
+7-4llvm/lib/CodeGen/MachineBlockPlacement.cpp
+39-84 files

LLVM/project d0076c9llvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[NPM] Update OptimizedRegAlloc and MachineLateOptimization pipelines (#172795)

1. add the StackSlotColoringPass to default pipeline
2. Introduce MachineLateInstrsCleanupPass at the beginning of
addMachineLateOptimization (matches the legacy default pipeline)
DeltaFile
+6-3llvm/include/llvm/Passes/CodeGenPassBuilder.h
+2-2llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+8-52 files

LLVM/project 14b1d77llvm/docs NVPTXUsage.rst, llvm/lib/IR NVVMIntrinsicUtils.cpp

[NVPTX] Add intrinsics and codegen for tensormap.replace (#172458)

This change adds NVVM intrinsics and NVPTX codegen for the
`tensormap.replace` PTX instructions.
Tests are added in `tensormap_replace.ll`,
`tensormap_replace_sm_100a.ll`,
and `tensormap_replace_sm_103a.ll` and tested through `ptxas-13.0`.

PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-tensormap-replace
DeltaFile
+289-0llvm/docs/NVPTXUsage.rst
+263-0llvm/test/CodeGen/NVPTX/tensormap_replace.ll
+84-0llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+71-0llvm/lib/IR/NVVMIntrinsicUtils.cpp
+64-0llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+60-0llvm/test/CodeGen/NVPTX/tensormap_replace_sm_100a.ll
+831-05 files not shown
+1,008-011 files

LLVM/project 1e8f174llvm/utils profcheck-xfail.txt

[ProfCheck] Exclude test from e4722c6

This adds in a select that we should probably just mark with unknown
profdata. Exclude for now to get the bot back to green.
DeltaFile
+1-0llvm/utils/profcheck-xfail.txt
+1-01 files

LLVM/project f8140c3llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/CodeGen/AArch64 sme-framelower-use-bp.ll

rebase

Created using spr 1.3.7
DeltaFile
+28-742llvm/test/CodeGen/AArch64/sme-framelower-use-bp.ll
+755-5llvm/test/CodeGen/X86/pr162812.ll
+315-314llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+547-0llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-matmul.ll
+439-97llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+510-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll
+2,594-1,158802 files not shown
+21,067-6,665808 files

LLVM/project c2c787cllvm/include/llvm/ABI Types.h, llvm/lib CMakeLists.txt

[LLVMABI] Implement the ABI Typesystem (#158329)

This PR implements the first part of the LLVM ABI lowering library,
proposed in [this
RFC](https://discourse.llvm.org/t/rfc-an-abi-lowering-library-for-llvm/84495).
It is split out of https://github.com/llvm/llvm-project/pull/140112,
which demonstrates how this is going to be used.

The ABI type system is intended to represent all the type information
that is necessary to make call lowering decisions. As such, it contains
less information than Clang QualTypes, but more information than LLVM IR
types. The current type system has enough information to implement the
x86_64 SysV ABI, but some extensions will likely be needed in the future
for other targets (e.g. unadjusted alignment).

The type system expects layout information (like size, offset and
alignment) to already be computed by the frontend.

The types are constructed using TypeBuilder, which uses a
BumpPtrAllocator. The types themselves are not uniqued -- instead we
cache the QualType -> ABI type translation (in future patches).
DeltaFile
+431-0llvm/include/llvm/ABI/Types.h
+14-0llvm/lib/ABI/CMakeLists.txt
+9-0llvm/lib/ABI/Types.cpp
+1-0llvm/lib/CMakeLists.txt
+455-04 files

LLVM/project ee0ed27llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor nofpclass.ll

ValueTracking: Improve handling of fadd in computeKnownFPClass.

This already recognized that if both inputs are positive, the
result is positive. Extend this to the mirror situation with
negative inputs.

Also special case fadd x, x. Canonically, fmul x, 2 is fadd x, x.
We can tell the sign bit won't change, and 0 will propagate.
DeltaFile
+23-23llvm/test/Transforms/Attributor/nofpclass.ll
+24-4llvm/lib/Analysis/ValueTracking.cpp
+47-272 files

LLVM/project 0eddb06llvm/test/Transforms/Attributor nofpclass.ll

ValueTracking: Add more baseline tests for computeKnownPPClass of fadd

Test cases with fadd x, x. Also test cases where both inputs are known
negative.
DeltaFile
+602-106llvm/test/Transforms/Attributor/nofpclass.ll
+602-1061 files