LLVM/project b97d8b2llvm/test/Transforms/LoopVectorize/X86 libm-vector-calls-finite.ll libm-vector-calls-VF2-VF8.ll

[LoopVectorize][X86] Improve libmvec SSE/AVX/AVX-512 test coverage (#211863)

This PR updates the libmvec loop vectorization tests to use `-force-vector-width` instead of hardcoded loop metadata.

Fixes #211532
DeltaFile
+601-274llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls.ll
+0-480llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-VF2-VF8.ll
+118-60llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-finite.ll
+719-8143 files

LLVM/project 794aa0fllvm/lib/Support APFloat.cpp, llvm/unittests/ADT APFloatTest.cpp

[APFloat] Don't turn a Float8E8M0FNU NaN into an Inf on conversion (#214919)

`Float8E8M0FNU` has a precision of 1, so it stores no significand bits
and its NaN carries no payload. `IEEEFloat::convert` shifts the (empty)
significand into the target format, which leaves the NaN exponent with
an all-zero significand — and that is the encoding of an infinity in any
format that has infinities.

The `APFloat` object still reports `fcNaN`, so `isNaN()` returns true,
but `bitcastToAPInt()` hands back Inf bits. Anything that stores the bit
pattern rather than the object — `ConstantFP`, MLIR's `FloatAttr` —
therefore ends up with an infinity.

In MLIR this shows up when folding `arith.extf` on an `f8E8M0FNU`
constant. The OCP MXFP spec uses the all-ones encoding as the scale of
an invalid block, so this silently replaces "this block is invalid" with
a value that poisons everything it is multiplied into:

```mlir

    [27 lines not shown]
DeltaFile
+30-0llvm/unittests/ADT/APFloatTest.cpp
+19-0mlir/test/Dialect/Arith/canonicalize.mlir
+5-0llvm/lib/Support/APFloat.cpp
+54-03 files

LLVM/project 2938cfcclang/lib/StaticAnalyzer/Core HTMLDiagnostics.cpp, clang/test/Analysis/html_diagnostics highlight-range-mapping.cpp

[analyzer] Fix -analyzer-output=html assert on reversed and macro ranges

HTMLDiagnostics::HighlightRange guarded against a reversed range by
comparing line numbers, so a same-line reversal - which is what the piece for
an implicit copy constructor carries - reached html::HighlightRange.
Its scan walks from begin to end, ran off the end of the buffer, and asserted:
https://godbolt.org/z/sTb5qfjjd

  Invalid position to insert! (RewriteRope.h)

It also added the end token's length itself and then passed a token range to
html::HighlightRange, which measured the token again, this time from the
interior. For most tokens the two cancel, but where the tail re-lexes longer
the highlight reached past the end of the range, e.g. over a trailing ';'.

Use getExpansionRangeInFile(), which rejects reversed and cross-file ranges,
then convert once and tell html::HighlightRange the range is already
char-granular.


    [4 lines not shown]
DeltaFile
+43-0clang/test/Analysis/html_diagnostics/highlight-range-mapping.cpp
+8-27clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
+51-272 files

LLVM/project e29e70dclang/lib/StaticAnalyzer/Core SarifDiagnostics.cpp, clang/test/Analysis/diagnostics sarif-macro-expansion.c

[analyzer] Fix -analyzer-output=sarif crash on macro-expanded ranges

A path piece whose range ends inside a macro expansion aborted the whole
document: https://godbolt.org/z/61vWYcsWj

  Cannot create a physicalLocation from invalid SourceRange!

convertTokenRangeToCharRange() built the end with
Lexer::getLocForEndOfToken(), which returns an invalid location for a macro
ID that is not at the end of its expansion, and used it unchecked. The
analyzer's own test corpus hits this in nine files; text and plist output
were unaffected because both already map such ranges to the expansion.

- Use getExpansionRangeInFile(), so the region covers the macro use like the
  other two outputs.
- Fall back to a caret when the range is unusable. A thread flow needs a
  location per piece, so dropping one would truncate the reported path. This
  also stops reversed ranges producing regions with endColumn < startColumn.


    [4 lines not shown]
DeltaFile
+22-21clang/lib/StaticAnalyzer/Core/SarifDiagnostics.cpp
+35-0clang/test/Analysis/diagnostics/sarif-macro-expansion.c
+57-212 files

LLVM/project ee8dc4cclang/include/clang/Frontend DiagnosticRenderer.h, clang/lib/Frontend DiagnosticRenderer.cpp

[clang] Reject ranges getExpansionRangeInFile cannot represent

getExpansionRangeInFile was extracted verbatim and inherited two shortcomings
of the original loop, fixed here before the analyzer's SARIF and HTML consumers
depend on it:

- It mapped the end with getExpansionRange(SourceLocation), which always
  reports a token range, so a char-range input was widened by a whole token.
  Now using the getExpansionRange(CharSourceRange) overload, which keeps the flag.
- It passed reversed ranges through. Consumers walk begin->end; now returning
  nullopt for those, as Lexer::makeFileCharRange already does.

Separate from the extraction so that stays NFC, and out of the consumer fixes
because it changes the shared helper's contract rather than one output.

Both contract changes, plus the invalid- and cross-file-range guards, are
covered by a GetExpansionRangeInFile unit test in
clang/unittests/Frontend/TextDiagnosticTest.cpp.

Assisted-By: claude
DeltaFile
+89-0clang/unittests/Frontend/TextDiagnosticTest.cpp
+9-2clang/include/clang/Frontend/DiagnosticRenderer.h
+8-1clang/lib/Frontend/DiagnosticRenderer.cpp
+106-33 files

LLVM/project 550d4a4clang/include/clang/Frontend DiagnosticRenderer.h

[clang][NFC] Document getExpansionRangeInFile's nullopt cases
DeltaFile
+3-0clang/include/clang/Frontend/DiagnosticRenderer.h
+3-01 files

LLVM/project a117608clang/lib/Frontend DiagnosticRenderer.cpp

[clang][NFC] Reuse SourceManager::getExpansionRange in getExpansionRangeInFile
DeltaFile
+4-6clang/lib/Frontend/DiagnosticRenderer.cpp
+4-61 files

LLVM/project 3027f32llvm/test/Transforms/LoopVectorize pr34681.ll bounded-load.ll, llvm/test/Transforms/LoopVectorize/RISCV strided-accesses-narrow-iv.ll strided-access-wide-stride.ll

[LV] Avoid adding stray predicates in isConsecutivePtr (#213662)

If the absolute value of Stride is not unit, avoid adding stray SCEV
predicates.
DeltaFile
+117-75llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
+77-36llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
+15-73llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+58-18llvm/test/Transforms/LoopVectorize/bounded-load.ll
+48-18llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll
+2-26llvm/test/Transforms/LoopVectorize/pr34681.ll
+317-2464 files not shown
+336-29010 files

LLVM/project c6a18acllvm/lib/Target/AArch64 AArch64SchedHIP12.td, llvm/test/tools/llvm-mca/AArch64/HiSilicon hip12-forwarding.s hip12-basic-instructions.s

[AArch64] Add initial sched model for hip12 (#212935)

This patch adds initial sched model for Hisilicon's hip12 core (Kunpeng
950 processor).
DeltaFile
+6,869-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-sve-instructions.s
+5,269-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-writeback.s
+3,354-0llvm/lib/Target/AArch64/AArch64SchedHIP12.td
+3,159-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-neon-instructions.s
+2,519-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-basic-instructions.s
+1,871-0llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-forwarding.s
+23,041-013 files not shown
+23,824-219 files

LLVM/project d928627llvm/test/Transforms/LoopVectorize/AArch64 induction-costs.ll optsize_minsize.ll, llvm/test/Transforms/LoopVectorize/ARM optsize_minsize.ll

[VPlan] Cost truncated widened inductions via ::computeCost. (#212786)

Follow-up to https://github.com/llvm/llvm-project/pull/202232 to also
compute costs for truncated inductions in ::computeCost, removing the
fallback to the legacy cost model unless the loop is fully unrolled.

Note that this changes vectorization decisions in both direction, e.g.
* now vectorized `@tail_predicate_without_optsize`: legacy costs <16 x
i64>, whereas we generate a narrow IV <16 x i8>, which is much cheaper
* no longer vectorized `@second_lshr_operand_zero_via_scev()`: we
generate 2 IVs (one truncated and one not truncated), which is more
expensive than the single IV LV assumes (note that previously we would
ignore the cost of the trunc in the cost computation, because the trunc
was replaced by the wide truncated IV, which was assumed free.

Both cases are due to more accurate cost computations.

PR: https://github.com/llvm/llvm-project/pull/212786
DeltaFile
+130-17llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
+17-35llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
+24-24llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll
+18-18llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
+15-6llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
+8-8llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
+212-1083 files not shown
+221-1279 files

LLVM/project b4c970cllvm/test/CodeGen/X86 pext-vector.ll pdep-vector.ll

[X86] Add pdep/pext vector test coverage (#215231)

Baseline tests for #214508
DeltaFile
+889-0llvm/test/CodeGen/X86/pdep-vector.ll
+869-0llvm/test/CodeGen/X86/pext-vector.ll
+1,758-02 files

LLVM/project 09f5979llvm/lib/Analysis IVDescriptors.cpp, llvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlanTransforms.cpp

[LV] Vectorize down-counting floating-point argmin/argmax reductions

Extend the multi-use min/max reduction coupling so a floating-point
min/max value reduction can be paired with a down-counting (FindFirst)
index reduction, enabling argmin/argmax vectorization for loops whose
induction counts down.

Analysis (IVDescriptors):
 - Recognize select-based FP min/max recurrences, not just the
   intrinsic form.
 - For the shared-compare argmin/argmax shape (the reduction compare
   also feeds an index select), take the required NaN-free and
   signed-zero-free facts from the compare when the select itself does
   not carry them. Plain min/max reductions keep the strict
   flags-on-the-select rule.

VPlan (handleMultiUseReductions):
 - Accept a select as the value reduction's min/max operation and read
   its value operands accordingly.

    [14 lines not shown]
DeltaFile
+221-43llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+127-0llvm/test/Transforms/LoopVectorize/AArch64/select-index-decreasing.ll
+29-5llvm/lib/Analysis/IVDescriptors.cpp
+26-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+404-505 files

LLVM/project 2aa7f96llvm/include/llvm/Analysis PHITransAddr.h, llvm/lib/Analysis PHITransAddr.cpp

[GVN] Recover affine-equal select-dependent load addresses

Teach PHITransAddr to recover available select-arm addresses when a
constant GEP index adjustment is folded into a nested byte offset. This
lets GVN reuse the existing load-PRE path without depending on SCEV.
DeltaFile
+89-17llvm/lib/Analysis/PHITransAddr.cpp
+67-0llvm/test/Transforms/GVN/phitrans-gep-select-load-address.ll
+6-0llvm/include/llvm/Analysis/PHITransAddr.h
+162-173 files

LLVM/project a7fd911llvm/test/Analysis/CostModel/RISCV cttz_elts.ll

[RISCV] Change undef->poison in cttz_elts.ll test (#215218)

Since `undef` is deprecated and triggers CI-failures when changing
existing tests. Discussed in
https://github.com/llvm/llvm-project/pull/214795#discussion_r3747841496
DeltaFile
+112-112llvm/test/Analysis/CostModel/RISCV/cttz_elts.ll
+112-1121 files

LLVM/project 29726d8lldb/source/Plugins/Process/Utility RegisterTypeDetector_arm64.cpp RegisterTypeDetector_arm64.h

[lldb][AArch64] Detect type for many registers with a single function (#214734)

It was pointed out during review of
https://github.com/llvm/llvm-project/pull/214515
that the type for the 2 GCS registers will be created twice.
Each one will have the same ID so we will only emit one and
the other goes unused.

To account for this, and the possibility of not just 2 but N
registers later, I've changed the name in the register entry
to a list of names.

So for the 2 GCS registers we only do detection once, and both
of them will refer to the same instance of the type.
DeltaFile
+14-14lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.h
+2-1lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.cpp
+16-152 files

LLVM/project 47f32bdllvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine fold-shuffle-chains-to-reduce.ll

[VectorCombine] Fold reduction chains with equivalent bitcast sources (#212084)

## Description

`foldShuffleChainsToReduce` currently identifies leaf sources by SSA
value identity.
This can prevent a shuffle reduction chain from being folded when
multiple bitcast instructions represent the same vector source.

This happens when an earlier VectorCombine transform moves a bitcast
through a shuffle and creates a new bitcast of the same underlying
value.
The reduction matcher then sees the original and newly created bitcasts
as separate sources and rejects the fold.

This PR treats bitcast sources as equivalent when they have the same
result type and the same operand.
It then merges the demanded lanes of equivalent sources while preserving
duplicate-lane semantics:

    [18 lines not shown]
DeltaFile
+126-0llvm/test/Transforms/VectorCombine/fold-shuffle-chains-to-reduce.ll
+22-10llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+148-102 files

LLVM/project 364002allvm/include/llvm/Transforms/Utils LoopSplitUtils.h, llvm/lib/Transforms/Utils LoopSplitUtilsPass.cpp LoopSplitUtils.cpp

[LoopSplitUtils] Revert, removing from tree (#214577)

This reverts commits:

- 2354dce21 ([Transforms][Utils] Add LoopSplitUtils for iteration-space
loop splitting, #205995)
- 8f1efc26 ([Transforms][Utils] Preserve branch weights in
LoopSplitUtils, #213626)
- 49ace5ab ([Transforms][Utils] Test for branch weight preservation in
LoopSplitUtils, #213647)

Removing LoopSplitUtils from the tree completely, as several crashes
were uncovered after it was added. A highly reduced initial version with
much better test coverage is proposed for the re-land.
DeltaFile
+0-630llvm/lib/Transforms/Utils/LoopSplitUtils.cpp
+0-154llvm/include/llvm/Transforms/Utils/LoopSplitUtils.h
+0-148llvm/lib/Transforms/Utils/LoopSplitUtilsPass.cpp
+0-89llvm/test/Transforms/LoopSplit/constant-trip-count.ll
+0-88llvm/test/Transforms/LoopSplit/nested-loop.ll
+0-88llvm/test/Transforms/LoopSplit/four-partitions.ll
+0-1,19713 files not shown
+0-1,76119 files

LLVM/project df90dfbllvm/include/llvm/IR IntrinsicsNVVM.td, llvm/lib/Target/NVPTX NVPTXSubtarget.h NVPTXInstrInfo.td

[NVPTX] Add intrinsics for ue5m3x2 to f16x2/bf16x2 conversions (#214411)

This patch adds the following intrinsics for `ue5m3x2` to `f16x2/bf16x2`
conversions introduced in PTX 9.4:

- `cvt.rn.f16x2.ue5m3x2`
- `cvt.rn{.satfinite}{.scaled::n2::ue8m0}.bf16x2.ue5m3x2`

Tests have been verified through `ptxas-13.4`.
---------

Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
DeltaFile
+80-0llvm/test/CodeGen/NVPTX/convert-ue5m3x2.ll
+16-0llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+14-0llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+12-0llvm/include/llvm/IR/IntrinsicsNVVM.td
+5-0llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+127-05 files

LLVM/project 89a2137libcxx/include tuple, libcxx/include/__configuration namespace.h

[libc++] Remove _IsThisTuple (#213909)

We can inline it into `_EnableUTypesCtor` instead.
DeltaFile
+2-6libcxx/include/tuple
+3-1libcxx/include/__configuration/namespace.h
+5-72 files

LLVM/project 390172alldb/source/Plugins/Process/Utility RegisterTypeDetector_arm64.cpp RegisterTypeDetector_arm64.h

[lldb][AArch64] Detect type for many registers with a single function

It was pointed out during review of https://github.com/llvm/llvm-project/pull/214515
that the type for the 2 GCS registers will be created twice.
Each one will have the same ID so we will only emit one and
the other goes unused.

To account for this, and the possibility of not just 2 but N
registers later, I've changed the name in the register entry
to a list of names.

So for the 2 GCS registers we only do detection once, and both
of them will refer to the same instance of the type.
DeltaFile
+14-14lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.h
+2-1lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.cpp
+16-152 files

LLVM/project 4eda802lldb/source/Plugins/Process/Utility RegisterTypeDetector_arm64.h

[lldb][AArch64] Remove size from type detector entries (#214733)

This was passed to the constructor but goes unused.
The detector functions know the size of the type
they're creating already.
DeltaFile
+10-11lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.h
+10-111 files

LLVM/project 20b9e60llvm/lib/Analysis IVDescriptors.cpp, llvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlanTransforms.cpp

[LV] Vectorize down-counting floating-point argmin/argmax reductions

Extend the multi-use min/max reduction coupling so a floating-point
min/max value reduction can be paired with a down-counting (FindFirst)
index reduction, enabling argmin/argmax vectorization for loops whose
induction counts down.

Analysis (IVDescriptors):
 - Recognize select-based FP min/max recurrences, not just the
   intrinsic form.
 - For the shared-compare argmin/argmax shape (the reduction compare
   also feeds an index select), take the required NaN-free and
   signed-zero-free facts from the compare when the select itself does
   not carry them. Plain min/max reductions keep the strict
   flags-on-the-select rule.

VPlan (handleMultiUseReductions):
 - Accept a select as the value reduction's min/max operation and read
   its value operands accordingly.

    [14 lines not shown]
DeltaFile
+221-43llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+127-0llvm/test/Transforms/LoopVectorize/AArch64/select-index-decreasing.ll
+29-5llvm/lib/Analysis/IVDescriptors.cpp
+26-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+404-505 files

LLVM/project f0829eellvm/include/llvm/Analysis MemoryDependenceAnalysis.h, llvm/lib/Analysis MemoryDependenceAnalysis.cpp PHITransAddr.cpp

[GVN] Replace SCEV address recovery with GEP peeling

Avoid introducing ScalarEvolution into GVN by teaching PHITransAddr to
recover affine-equivalent select-arm addresses from nested GEPs.
DeltaFile
+89-17llvm/lib/Analysis/PHITransAddr.cpp
+0-81llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
+0-73llvm/test/Transforms/GVN/scev-select-load-address.ll
+67-0llvm/test/Transforms/GVN/phitrans-gep-select-load-address.ll
+0-12llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
+0-6llvm/lib/Transforms/Scalar/GVN.cpp
+156-1892 files not shown
+162-1928 files

LLVM/project 3736fe2clang-tools-extra/clang-tidy/zircon CMakeLists.txt ZirconTidyModule.cpp, clang-tools-extra/docs/clang-tidy/checks/zircon temporary-objects.md

[clang-tidy] Remove deprecated zircon module (#215063)

Follow up of https://github.com/llvm/llvm-project/pull/162012
DeltaFile
+0-37clang-tools-extra/clang-tidy/zircon/ZirconTidyModule.cpp
+0-25clang-tools-extra/clang-tidy/zircon/CMakeLists.txt
+0-18clang-tools-extra/test/clang-tidy/checkers/fuchsia/temporary-objects-deprecated-alias.cpp
+0-14llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/zircon/BUILD.gn
+0-11clang-tools-extra/docs/clang-tidy/checks/zircon/temporary-objects.md
+0-10utils/bazel/llvm-project-overlay/clang-tools-extra/clang-tidy/BUILD.bazel
+0-1158 files not shown
+8-13714 files

LLVM/project 75a45c3mlir/lib/Dialect/Vector/IR VectorOps.cpp, mlir/test/Dialect/Vector invalid.mlir

Revert "[mlir][vector] Verify non-unit strides on `masked/expand/compress` ops  (#210952)" (#215224)

This reverts commit ac646b5be0d7764a1dbeb86e4f8d54df2d4fd3eb.

The following integration tests are failing:
  * Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir
  * Integration/Dialect/Linalg/CPU/ArmSME/multi-tile-matmul-mixed-types.mlir

Failing bot:
  * https://lab.llvm.org/buildbot/#/builders/121/builds/2588
DeltaFile
+0-107mlir/test/Dialect/Vector/invalid.mlir
+0-24mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+0-1312 files

LLVM/project 2cb0587clang/lib/StaticAnalyzer/Checkers DanglingPtrDeref.cpp

[analyzer] Add aggregate lifetime source binding to DanglingPtrDeref
DeltaFile
+8-0clang/lib/StaticAnalyzer/Checkers/DanglingPtrDeref.cpp
+8-01 files

LLVM/project 354bafaclang/lib/StaticAnalyzer/Checkers LifetimeModeling.cpp, clang/test/Analysis lifetime-bound.cpp

Add getRegionsFromSVal helper and correct test function name.
DeltaFile
+10-7clang/lib/StaticAnalyzer/Checkers/LifetimeModeling.cpp
+2-2clang/test/Analysis/lifetime-bound.cpp
+12-92 files

LLVM/project b22c8a6llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination ssub-with-overflow.ll

[ConstraintElimination] Defer removal of simplified ssub.with.overflow (#215135)

replaceSubOverflowUses erased the intrinsic as soon as it became dead.
That frees the intrinsic's operand Use array, but the worklist can still
hold UseCheck entries pointing into it, storing a now invalid pointer to
a Use *.

Instead of erasing the intrinsic in place, poison its arguments and push
it onto ToRemove.

PR: https://github.com/llvm/llvm-project/pull/215135
DeltaFile
+46-0llvm/test/Transforms/ConstraintElimination/ssub-with-overflow.ll
+4-1llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+50-12 files

LLVM/project a74f304lldb/source/Plugins/Process/Utility RegisterTypeDetector_arm64.cpp RegisterTypeDetector_arm64.h

[lldb][AArch64] Detect type for many registers with a single function

It was pointed out during review of https://github.com/llvm/llvm-project/pull/214515
that the type for the 2 GCS registers will be created twice.
Each one will have the same ID so we will only emit one and
the other goes unused.

To account for this, and the possibility of not just 2 but N
registers later, I've changed the name in the register entry
to a list of names.

So for the 2 GCS registers we only do detection once, and both
of them will refer to the same instance of the type.
DeltaFile
+14-14lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.h
+2-1lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.cpp
+16-152 files

LLVM/project 43d162flldb/source/Plugins/Process/Utility RegisterTypeDetector_arm64.h

[lldb][AArch64] Remove size from type detector entries

This was passed to the constructor but goes unused.
The detector functions know the size of the type
they're creating already.
DeltaFile
+10-11lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.h
+10-111 files