[libc++] Clean up leftover std::print availability workarounds (#234379)
The availability markup for std::print was removed in 4a87db6b10a0 and
the corresponding macros were deleted entirely in 1616fbaccf82. However,
several functions in <print> were left templates to work around
https://llvm.org/PR61563, which is not necessary anymore.
Remove a few workarounds that are now unnecessary, and reword others
that are required due to format now, not print.
[Object] Bounds-check the big archive next member offset (#230781)
NextOffset comes from a 20-character decimal field in the member header,
so it can hold any 64-bit value. `getNextChildLoc()` adds it to the
start of the buffer before anything checks it, which wraps, and the
`NextLoc > getBufferEnd()` test in `getNext()` then passes because the
wrapped pointer is below the buffer rather than above it. The next
member header is read from there: with an offset of 2^64-1 the pointer
lands one byte before the archive, and llvm-ar prints that byte back in
its own diagnostic.
Check the offset against the archive's size while it is still an
integer.
The generic member header path has the same shape but its size field is
only 10 characters wide, so it cannot reach a wrap and is left alone.
Assisted-by: Claude (Anthropic)
[AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms
Replace NOT followed by merging AND with BIC for expressions such as:
return svand_u32_m(pg, a, svnot_u32_x(pg, b));
Combine when NOT is the second operand and its predicate matches the AND
predicate or is all-active.
Use predicated BIC to preserve the AND's first operand in inactive
lanes. Use unpredicated BIC when the AND predicate is all-active.
Do not commute merging AND operands, since this would change inactive
results. Leave pairs with incompatible predicates unchanged.
This applies to all integer element widths. Update the pre-commit LLVM
expectations, including cases where combining would change the
result.
fixup! [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms
Select merging AND-NOT operations with TableGen patterns instead of the C++ combine. Preserve the first operand in inactive lanes and use an unpredicated BIC when both predicates are all-active.
[AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms
Replace NOT followed by AND with BIC for expressions such as:
return svand_u32_x(svptrue_b32(), a, svnot_u32_x(svptrue_b32(), b));
Combine ordinary AND with NOT when the NOT predicate is all-active or
its inactive values are undefined.
Also combine matching-predicate SVE AND_x-NOT pairs before lowering
discards the AND predicate. AND_x ignores inactive results, so the NOT's
inactive values do not need preserving.
This applies to all integer element widths. Update the pre-commit LLVM
expectations, including cases where combining would change the
result.
fixup! Replace performSVEAndNotIntrinsicCombine() with tablegen
Move AND_U and NOT matching to TableGen, using a shared pattern fragment
for both operand orders. Retain register and immediate AND selection
for other AND_U operations.
[AArch64][llvm] Add pre-commit tests for SVE AND-NOT combining
Add LLVM tests for expressions where NOT followed by AND could
use BIC. Record the existing assembly so the following changes show the
missed optimisations being fixed.
Cover _x and _m AND forms using all-active and runtime predicates. Test
_m forms across all integer element widths. Include NOT with defined
inactive values and reversed AND operands.
Also test cases that must remain as NOT followed by AND because
combining would change the values in inactive lanes.
fixup! [AArch64][llvm] Add pre-commit tests for SVE AND-NOT combining
Add the ordinary LLVM NOT cases to the pre-commit tests, covering both AND_U operand orders. These already select BIC and guard against regressions when retaining AND_U for TableGen selection.
fixup! [AArch64][llvm] Add pre-commit tests for SVE AND-NOT combining
Add the nested AND_U constant-mask case to the pre-commit tests. This folding already works before the AND-NOT implementation change.
[flang][OpenMP] Disallow substrings as named parameter list items (#234609)
OpenMP 5.2+ explicitly disallows substrings as named parameter list
items (and therefore as members of argument lists). This patch checks
this restriction generically so that it applies everywhere.
AFFINITY and DEPEND both produced portability warnings instead of hard
errors. I decided to keep those existing extensions.
Some other clauses (e.g. privatization, reduction) have the same
restriction in earlier standard versions. This is checked separately for
those clauses.
Assisted-by: Codex
[flang] Enumeration Type: (PR 5/5) Enable (#231641)
Enable the F2023 ENUMERATION TYPE (7.6.2) by default and remove the
development gate.
- Remove `-fenumeration-type` / `-fno-enumeration-type`,
`LanguageFeature::EnumerationType` and the experimental-support warning.
- Update tests to run without the flag.
- Update ReleaseNotes.md, Extensions.md and FortranStandardsSupport.md.
New declaration checks. An enumeration type is not a derived type, so it
is not extensible and has no type parameters. Flang now diagnoses:
- `EXTENDS(enum)`, rejected early so that no parent component is created
- `CLASS(enum)`, including in a FUNCTION prefix and in IMPLICIT
- `CLASSOF(enum)`; Flang requires an extensible type here (see
Extensions.md)
- `CLASS IS (enum)` in SELECT TYPE
- `TYPE IS (enum)` unless the selector is unlimited polymorphic
- pointer assignment of an enumeration-type pointer from a `CLASS(*)`
[19 lines not shown]
[libc][cmake] Respect the configured optimization level for the Linux thread and TLS objects (#234382)
The `-O3` override on the Linux `thread` object dates from the old
approach of reading the thread arguments off the new thread's stack,
which #225384 removed; the `tls` objects copied the same pattern in
#225418. Neither needs it anymore, so drop the overrides and use the
optimization level configured by CMake.
Assisted-by: Claude
[NFC][clang-repl] Drop the private label in IncrementalCUDADeviceParser (#234600)
This is an NFC change. It moves the private members of
IncrementalCUDADeviceParser to the top of the class and drops the
`private:` specifier, to match `IncrementalHIPDeviceParser` and the rest
of the file.
[GlobalISel] Preserve dominance when legalizing invoke-result PHIs
PHI legalization inserts conversions before the first terminator so they
execute on unwind edges. An invoke result is defined after the invoke-region
marker, however, and placing its conversion before that marker creates a
use before definition.
Keep the existing insertion point for values available before the invoke,
and insert after the definition for values produced inside the region.
Use the same rule for scalar and vector PHI resizing. This also ensures
vector widening for unwind PHIs executes before a potentially throwing call.
Update the pre-committed IR and helper-level checks and enable machine
verification in the IR test.
[GlobalISel][AArch64] Pre-commit PHI legalization tests around invokes
Cover a real invoke result and a vector PHI on an unwind edge. Check scalar
narrowing and vector splitting directly in LegalizerHelper tests so artifact
combining cannot hide misplaced conversions.
Record the current conversion placement for the subsequent dominance fix.
Temporarily disable machine verification in the IR test to capture the
existing use-before-definition output.
[SCEV] Derive x >=s 0 from x <u y and y <=u 2^(n-1)
Let n be the bit width of x and y. If x <u y and y <=u 2^(n-1), then
x <u 2^(n-1), so x >=s 0. Here y <=u 2^(n-1) means y >=s 0 or
y == INT_MIN. In the same way, if x <=u y and y <u 2^(n-1), then
x >=s 0.
This lets a guard like x <u len prove x >=s 0 when len is non-negative.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][IndVars][NFC] Add tests for x >=s 0 from x <u y with swapped operands
Let n be the bit width of x and y. If x <u y and y <=u 2^(n-1), then
x >=s 0. SCEV can't prove this yet when the operands of the compare to
prove are in the opposite order to the guard, e.g. 0 <=s x with
x <u y known.
Add tests for it.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV][IndVars][NFC] Add tests for x >=s 0 from x <u y and y <=u 2^(n-1)
Let n be the bit width of x and y. If x <u y and y <=u 2^(n-1), then
x >=s 0. SCEV can't prove this yet.
Add tests for it.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SCEV] Prove signed/unsigned implications in either operand order
SCEV could prove these implications only with the operands in the same
order:
- If a <u b and a, b have the same sign, then a <s b.
- If a <s b and a, b have the same sign, then a <u b.
- If a <u b and b >=s 0, then a <s b.
- If a <s b and b <s 0, then a <u b.
For example, it proved a <s b from a <u b and b >=s 0, but not b >s a.
Now it proves them in either order.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
