[CodeGen] Move BasicBlockMatchingAndInference options to CodeGenOptions.td (#235180)
Move -propeller-match-bbid and -propeller-infer-threshold from cl::opt
in BasicBlockMatchingAndInference.cpp to CodeGenOptions.td. This avoids
exposing PropellerMatchBBID in BasicBlockMatchingAndInference.h and
including that header in TargetPassConfig.cpp.
CodeGen: Consolidate MachinePipeliner controls (#235311)
This pass followed the anti-pattern of having a cl::opt in the pass
which early returned instead of not adding the pass to the pipeline in
the first place. Additionally several targets had their own cl::opts
used from the subtarget enablement hook.
Consolidate this into one generic control with a subtarget hook to
enable the pipeliner, following the example of enable-misched /
enableMachineScheduler.
Adding the nop pass still had the side effect of running the required
analyses which exposed issues. In particular this hides failures in
PPC with the defaults. The LiveIntervals dependency would assert if
there were unreachable blocks which was possible with the point PPC
inserted the pass.
Hexagon's hardware loop passes move to the end of
addMachineSSAOptimization so they still run before the pipeliner.
[6 lines not shown]
[AMDGPU] Use addressable arch VGPR count for CFI
emitPrologueEntryCFI assumed 1024 arch VGPRs on targets with VGPR
MSBs, regardless of wave size. In wave64 only 512 are addressable, and
VGPRs above that have no DWARF number. Use
getAddressableNumArchVGPRs, as whole wave function handling already
does.
No upstream target with VGPR MSBs supports wave64. NFC.
Change-Id: Ic65c4bb284e8583395bbe98ceeccd0f46b877538
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[SandboxVec] Remove empty test directory (NFC) (#235015)
This removes `Passes/BundleVec/AMDGPU/` as there are no tests left in
this directory after https://github.com/llvm/llvm-project/pull/234432
[AMDGPU] Derive addressable VGPRs from encoding width
The addressable VGPR count is bounded by both the operand encoding
width and the register file size. Compute it as the smaller of the two
instead of listing per-target values. Wave64 on targets with VGPR MSBs
was already min(1024, 512). NFC.
Change-Id: Ia0e030a9005fb2e915ef09e4ac7fd5ded22ab9b2
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Rename 1024AddressableVGPRs to VGPRMSBs
Most users of this feature ask whether the target has VGPR MSBs:
S_SET_VGPR_MSB, VGPR encoding lowering, MSB decoding and inline asm
register classes. 1024 follows from an 8-bit operand field plus 2 MSBs.
Name the feature after the capability so VGPR counts can be derived
from the encoding width. NFC.
Change-Id: I4da9b113260bb73cc60119836918ad16c09687ba
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[runtimes][Fortran] No introspection in bootstrapping build (#234424)
In a bootstrapping build, flang is only built for the runtime's build
step, but not the configure step. That means the the result of Fortran
compiler introspection is unreliable. Don't attempt
`check_fortran_builtins_available()` in a bootstrapping configure.
One may think that any compiler introspection will just fail as intended
if flang is not even available, but
https://github.com/llvm/llvm-project/pull/209482#issuecomment-6202154199
describes how it may pass: `fakeflang` just runs the preprocessor (which
is sufficient for CMake to detect LLVMFlang), but
`check_fortran_builtins_available`'s check is intended to fail during
symbol resolution.
AMDGPU: Don't reserve the implicit buffer pointer with architected flat scratch (#235258)
Mesa shaders always had s[0:1] reserved for the implicit buffer
pointer, which is only needed to set up the scratch buffer
resource. With architected flat scratch, scratch is initialized by the
hardware and the pointer is unused. The driver stopped passing this
pointer so all user SGPRs were off by 2.
Don't reserve it on targets with architected flat scratch, so the user
SGPRs of Mesa shaders start at s0. Diagnose the use in the unsupported
contexts. This fixes many test failures on my system when running
piglit.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
RegAlloc: Only def the subregister regunits of a failed subregister def (#235307)
After an allocation failure, cleanupFailedDefs added each failed def to
the live ranges of all regunits of the assigned register. A subregister
def only writes the subregister, so the remaining units got a def from
an instruction that does not modify them, which the verifier rejects.
Fixes ran-out-of-registers-errors.ll with EXPENSIVE_CHECKS after
#233796.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[SelectionDAG][RISCV][X86] Keep jump table range checks with cf-protection-branch (#234733)
When the default of a switch is unreachable, SelectionDAGBuilder elides
the jump table range check, except when ARM branch-target-enforcement is
enabled, since an unchecked table branch can be a JOP gadget.
Extend this to the cf-protection-branch module flag used by RISC-V
Zicfilp and X86 IBT. The module flag is merged with Module::Min
behavior, so a value of 0 is treated as not enabled.
Assisted-by: Claude
[RISCV] Use vector getConstant. NFC (#235152)
It will eventually be legalized to a splat_vector and constant, but we
usually use a vector getConstant so let's be consistent.
CodeGen: Consolidate MachinePipeliner controls
This pass followed the anti-pattern of having a cl::opt in the pass
which early returned instead of not adding the pass to the pipeline in
the first place. Additionally several targets had their own cl::opts
used from the subtarget enablement hook.
Consolidate this into one generic control with a subtarget hook to
enable the pipeliner, following the example of enable-misched /
enableMachineScheduler.
Adding the nop pass still had the side effect of running the required
analyses which exposed issues. In particular this hides failures in
PPC with the defaults. The LiveIntervals dependency would assert if
there were unreachable blocks which was possible with the point PPC
inserted the pass.
Hexagon's hardware loop passes move to the end of
addMachineSSAOptimization so they still run before the pipeliner.
[7 lines not shown]
[mlir][linalg] Handle `DropPadUnitDims` when padding value is defined inside the pad body (#223712)
`DropPadUnitDims` reused the pad's padding value as-is when building the
replacement `tensor.pad`.
If that value was defined inside the original pad's own body, the new op
ended up referencing it from outside its region, and erasing the
original pad then hit an assertion.
This PR clone the defining op when the padding value lives inside the
pad body.
Fixes #203813
---------
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
[clang-tidy] Don't suggest const on `std::moved` locals in templates … (#226577)
[clang-tidy] Don't suggest const on std::moved locals in templates
Skip diagnostics in template instantiations for locals that are used as
arguments of std::move.
Reason: for some instantiations the move may be converted to copy so the
variable may look unmutated and flagged, whereas for other template
instantiations the real move semantics may apply.
Fixes: #225395
Assisted by Gemini for constructing the matcher.
---------
Co-authored-by: Zeyi Xu <zeyi2 at nekoarch.cc>
[AMDGPU][NFC] Harden sched_mfma_rewrite_copies.mir rewrite cases
The only functions in this test that are rewritten to AGPR form are
noncandidate_mfma_def_feeds_candidate_src2 and
av_mov_imm_src2_def_escapes_to_vgpr_user, added by #200972. Both are
balanced exactly on the RewriteMFMAFormStage cost threshold. Any
change that lowers the measured region pressure removes the rewrites
and the original intention of this test is lost.
The spill reduction is bounded by the number of rewrite-candidate
lanes live at the region's peak pressure. Keep more chain values live
through MFMA operands and keep the chain members rewrite candidates.
The properties under test are unchanged: the first MFMA in the first
function is still a non-candidate whose result feeds a candidate's
src2, and the AV_MOV_B64_IMM_PSEUDO in the second still escapes to a
VGPR user, so both still need bridge copies.
Co-authored-by: Cursor <cursoragent at cursor.com>
[mlir] Find the pattern dump root only when IR debugging is enabled (#233771)
Extracted from https://github.com/llvm/llvm-project/pull/231423
`PatternApplicator` debug printing was unconditionally calling
`getDumpRootOp` which walks nested ops chains. This was taking a
noticeable time in synthetic 1000-nested test. Call `getDumpRootOp` only
if printing is actually enabled.
[Test][clang-repl]Keep value names in clang-repl pragma-optimize.cpp (#235305)
The test added by aa6e40c073e6 checks for named values
(entry:, %x.addr, %x), which only appear when clang keeps value names.
That is the default in assertion builds, but non-assertion CI builds
discard them, so the CHECK-NEXT: entry: line fails. Pass
-fno-discard-value-names explicitly.
Assisted-By: Claude Opus 5.5
[SPARC] Implement TargetInstrInfo::insertIndirectBranch() (#226678)
Implement `insertIndirectBranch` so that branch relaxation pass can
insert unconditional long-range branching.
Follow an approach similar to the one used in AVR and use the CALL
instruction to get a reach of 32-bit signed offset instead of emitting
actual indirect branches.
[RISCV][P-ext] Add isel pattern match for mulu.h01/mulu.h11 (#235226)
`mulu.h01` multiplies the zero-extended lower half word of rs1 by the
zero-extended upper half word of rs2, and `mulu.h11` multiplies the
zero-extended upper half words of both.
Previously, (srl X, 16) was selected as a separate srli feeding
`mulu.h00` or `mul`. Match it directly so the shift is folded.
zexti16 also matches (srl X, 16) since its upper bits are known zero, so
the new patterns need AddedComplexity to be tried before the `mulu.h00`
pattern, and `mulu.h11` before `mulu.h01`.
[OpenMP] Add definition of task_iteration directive
This just adds the basic definitions of the directive (specifically the
definitions of the OMPD_task_iteration enum).
This isn't used or handled anywhere at the moment.
[AVR] Address review comments on AVRTiny spills
Document that STDPtrQRr and LDDRdPtrQ are only treated as pseudo
instructions on AVRTiny, and check atmega328 instead of -O0 in
std-ldd-tiny.ll so the test contrasts the two kinds of cores.
[SLP]Drop samesign of narrowed bit test compares (#235287)
The bit tests compare and L, R, which sign-extends from the narrow type
only
if both L and R do, so its sign may change after narrowing.
Fixes
https://github.com/llvm/llvm-project/pull/233124#issuecomment-6382644843
Assisted-by: Cursor
