[IR] Add ImplicitTrunc argument to ConstantInt::get() (#170865)
Add an ImplicitTrunc argument to ConstantInt::get(), which allows
controlling whether implicit truncation of the value is permitted.
This argument currently defaults to true, but will be switched to false
in the future to guard against signed/unsigned confusion, similar to
what has already happened for APInt.
The argument gives an opt-out for cases where the truncation is
intended. The patch contains one illustrative example where this
happens.
[clang-tidy][NFC] Add empty '.clang-tidy' file in tests dir to silent warnings in IDE (#171029)
When working on tests, `clangd` with option `--clang-tidy` will report
warnings from
[root](https://github.com/llvm/llvm-project/blob/main/.clang-tidy)
clang-tidy config.
I believe these warnings serve no purpose in tests, so we better disable
them to silent warnings in IDE.
[RISCV] Re-generate rvp-ext-rv32.ll after #170399. NFC
Some instructions got renamed by #170399, but new tests cases were
added after that PR was created.
[RISCV] Update P extension to the 018 version of the spec. (#170399)
Rename the PPACK* instructions to PPAIR*. Rename PDIF* to PABD*. Remove
Zba/Zbb instructions from P.
https://www.jhauser.us/RISCV/ext-P/
[CIR] Make CIR-to-LLVM a one shot conversion
This had to fix memory and conversion bugs due to now immediate
conversion patterns and no longer present original MLIR.
[RISCV] Remove last use of @llvm.experimental.vp.splat in RISCVCodeGenPrepare. NFCI (#170543)
RISCVCodeGenPrepare is the last user of the vp.splat intrinsic, where it
uses it to expand a zero strided load into a scalar load and splat.
Originally this was to avoid vl toggles inside vectorized loops, but
nowadays this shouldn't be necessary because we have RISCVVLOptimizer.
To preserve the test cases where there's no store with VL, this replaces
it with a regular splat followed by a vp_merge to set the lanes past EVL
as poison. We need to set the EVL here because RISCVISelDAGToDAG will
try and recombine it back into a zero strided load, and we want to
preserve the original VL.
PowerPC/VSX: Select FMINNUM and FMAXNUM (#135739)
In LangRef, we claim that FMINNUM and FMAXNUM should follow the minNum
and maxNum operators in IEEE754-2008.
PowerPC/VSX does have these instructions XSMINDP and XSMAXDP.
Now we use FMINNUM_IEEE and FMAXNUM_IEEE, since they are used by the
non-arch expand codes now.
In future, we may replace all FMINNUM_IEEE/FMAXNUM_IEEE with FMINNUM and
FMAXNUM.
---------
Co-authored-by: Your Name <you at example.com>
[libc++] Applied `[[nodiscard]]` to `hash<shared_ptr>`, `hash<unique_ptr>`, etc. (#170674)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
1. `hash<shared_ptr>`, `hash<unique_ptr>`, `std::integer_sequence<>`
etc.
2. Also implements fixes to
https://github.com/llvm/llvm-project/issues/169634 on the go (issues
discovered during current implementation)
---------
Co-authored-by: A. Jiang <de34 at live.cn>
Co-authored-by: Hristo Hristov <zingam at outlook.com>
[AMDGPU] Apply alignment attr for make.buffer.rsrc (#166914)
Calculating alignment for `make.buffer.rsrc` intrinsic. The logic is the
alignment on use of return value of `make.buffer.rsrc` should be capped
by the base operand's alignment of `make.buffer.rsrc`.
For example:
```ll
define float @foo(ptr addrspace(1) align X %ptr) {
%fat.ptr = call ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) %ptr, i16 0, i32 C, i32 0)
%y = load float, ptr addrspace(7) %fat.ptr, align Y
ret float %y
}
```
We hopes that `Y = min(X, Y)`
---
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[AMDGPU] Enable i8 GEP promotion for vector allocas (#166132)
This patch adds support for the pattern:
```llvm
%index = select i1 %idx_sel, i32 0, i32 4
%elt = getelementptr inbounds i8, ptr addrspace(5) %alloca, i32 %index
```
by scaling the byte offset to an element index (index >>
log2(ElemSize)),
allowing the vector element to be updated with insertelement instead of
using
scratch memory.
[RISCV] Use a switch in RISCVInstrInfo::verifyInstruction. NFC (#170961)
The immediate only operands handled with a range check and a switch
nested under the default case.
[InstCombine] Fix bail-out in `PHIsEqualValue()` (#170650)
We encountered a such case: `PHIsEqualValue()` is called with a PHI node
`PN` whose incoming values are all PHI nodes, and `NonPhiInVal` is
nullptr. When the size of `ValueEqualPHIs` reaches 16, `NonPhiInVal` is
still nullptr, then we keep scanning PHI node operands, this time the
recursion won't bail out even if we have visited too many PHI nodes.
In our case, the recursion ends with ~1700 PHI nodes visited, causes
InstCombine time-consuming.
[libcxx] Removal of narrowing conversions in `flat_[multi]{set, map}` tests for compatibility with MSVC (#170909)
Impacts files in `test/std/containers/container.adaptors/flat.xxx`. No
meaning is changed; only appropriate types are spelled out to prevent
compiler warnings.
- Replace `char`s and `short`s used in tests of `flat_[multi]{set, map}`
with `long`s to prevent warnings about narrowing conversions when
running tests. Allow increased test coverage for MSVC STL.
- Make test code robust against evil overloads of operator comma .(2
files)
- Add `[[maybe_unused]]` to some local `typedef`s that are sometimes
unused due to usage of `LIBCPP_STATIC_ASSERT`.
For discussion and suggested changes, see the LLVM Discord
https://discord.com/channels/636084430946959380/636732894974312448/1445901676400742533
