LLVM/project d2c6e4cllvm/lib/Target/Mips MipsExpandPseudo.cpp, llvm/test/CodeGen/Mips atomic-min-max-LiveVariables.ll

MIPS/expandAtomicBinOp: Remove tailing kill dead register operands (#186055)

Some trailing kill/dead register operands may added by
MachineInstr::addRegisterKilled or MachineInstr::addRegisterDead, which
uses the overlap registers same with the operand 1-4.

Let's remove them here as only 5 operands are assert existing.
DeltaFile
+131-0llvm/test/CodeGen/Mips/atomic-min-max-LiveVariables.ll
+27-0llvm/lib/Target/Mips/MipsExpandPseudo.cpp
+158-02 files

LLVM/project 77de752utils/bazel/llvm-project-overlay/mlir/test BUILD.bazel

[Bazel] Fixes 2d70dbd (#186268)

This fixes 2d70dbdb357d2b4080b30d35a105442337bc1fdd.
DeltaFile
+2-0utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
+2-01 files

LLVM/project ec93414clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenExprCXX.cpp

[CIR] Implement array delete for destructed types (#186248)

This extends the cir.delete_array lowering code to introduce a loop that
calls destructors when the array being deleted represents a destructed
type. The lowering introduces the destructors by way of a cir.array.dtor
operation, which is further expanded during LoweringPrepare. This also
required updating the cir.array.dtor operation to accept a raw pointer
to the element type and a value representing the number of elements to
be destructed.

This does not yet handle the possibility of destructors throwing
exceptions.
DeltaFile
+121-0clang/test/CIR/CodeGen/delete-array.cpp
+76-24clang/include/clang/CIR/Dialect/IR/CIROps.td
+52-15clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+22-2clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
+17-7clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
+288-485 files

LLVM/project 6121df7clang-tools-extra/clang-tidy/readability InconsistentIfElseBracesCheck.cpp BracesAroundStatementsCheck.cpp, clang-tools-extra/clang-tidy/utils BracesAroundStatement.cpp

[clang-tidy] Correctly handle attributes in readability-inconsistent-ifelse-braces (#184095)

Improved the check to correctly handle `[[likely]]` and `[[unlikely]]`
attributes placed between the if/else keyword and the opening brace.

As of AI Usage: Gemini 3 is used for pre-commit reviewing.
Closes https://github.com/llvm/llvm-project/issues/184081

(cherry picked from commit ca1eefdfc061fc062b6b9dc4149ca4a0e51bde08)
DeltaFile
+50-4clang-tools-extra/test/clang-tidy/checkers/readability/inconsistent-ifelse-braces-attributes.cpp
+14-5clang-tools-extra/clang-tidy/readability/InconsistentIfElseBracesCheck.cpp
+15-3clang-tools-extra/clang-tidy/utils/BracesAroundStatement.cpp
+1-1clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.cpp
+80-134 files

LLVM/project 8698f72lldb/source/Plugins/Process/Linux NativeRegisterContextLinux_arm64.cpp

[lldb] Wrap HWCAP defines in ifndef (NFC) (#186283)

Fixes a redefinition warning on Ubuntu 25.10 coming from `ptrace.h`
including `hwcap.h`.

```
/home/jonas/llvm/llvm-project/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:84:9: warning: ‘HWCAP2_POE’ redefined
   84 | #define HWCAP2_POE (1ULL << 63)
      |         ^~~~~~~~~~
In file included from /usr/include/aarch64-linux-gnu/asm/ptrace.h:25,
                 from /home/jonas/llvm/llvm-project/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h:19,
                 from /home/jonas/llvm/llvm-project/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:11:
/usr/include/aarch64-linux-gnu/asm/hwcap.h:141:9: note: this is the location of the previous definition
  141 | #define kkk              (1UL << 63)
      |         ^~~~~~~~~~
```
DeltaFile
+10-0lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+10-01 files

LLVM/project 6a52bb3llvm/test/CodeGen/X86 avx512-unsafe-fp-math.ll machine-combiner.ll

[X86] Remove `NoNaNsFPMath` uses (#185582)

Remove `NoNaNsFPMath` uses in X86 part. This should be the last part.
DeltaFile
+5-76llvm/test/CodeGen/X86/avx512-unsafe-fp-math.ll
+38-38llvm/test/CodeGen/X86/machine-combiner.ll
+31-31llvm/test/CodeGen/X86/sse-minmax-unsafe.ll
+24-26llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll
+18-18llvm/test/CodeGen/X86/avx512fp16-machine-combiner.ll
+9-11llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll
+125-2006 files not shown
+147-23412 files

LLVM/project 203c5c5llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU waitcnt-wcg-attributes.mir

[AMDGPU][SIInsertWaitcnts] Create a WCG instance per MF (#185916)

WaitcntGenerator state depends on MF attributes, so create a new WCG object per MF
until we have a better solution. This patch also adds a test that exercises this.

Even though we stopped creating a new WCG instance in #177689, the behavior
didn't change because SIInsertWaitcnts gets recreated on every MF
(so this patch is practically an NFC).
DeltaFile
+53-0llvm/test/CodeGen/AMDGPU/waitcnt-wcg-attributes.mir
+6-6llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+59-62 files

LLVM/project 21fc8e9lldb/tools/debugserver/source CMakeLists.txt

[lldb] Build debugserver fat for arm64 and arm64e (#186038)

Change the default of `LLDB_ENABLE_ARM64E_DEBUGSERVER` so we build
debugserver fat for arm64 and arm64e when running on macOS Tahoe (26) or
later on ptrauth-capable hardware.
DeltaFile
+32-1lldb/tools/debugserver/source/CMakeLists.txt
+32-11 files

LLVM/project 5315e0bllvm/lib/Target/SystemZ SystemZISelLowering.cpp

[SystemZ] Limit depth of findCCUse() (#185922)

The recursion here has potentially exponential complexity. Avoid this by
limiting the depth of recursion.

An alternative would be to memoize the results. I went with the simpler
depth limit on the assumption that we don't particularly care about very
deep value chains here.

Fixes https://github.com/llvm/llvm-project/issues/185905.

(cherry picked from commit 11e0d6ae4b00114d642f03168f57a007464bf5f6)
DeltaFile
+9-4llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+9-41 files

LLVM/project 81cf937llvm/lib/Target/AArch64 AArch64Arm64ECCallLowering.cpp, llvm/test/CodeGen/AArch64 arm64ec-entry-thunks.ll

[arm64ec] Fix missing sret return in Arm64EC entry thunks for large struct returns (#185452)

When an Arm64EC function returns a struct by value that is too large for
x64's `RAX` (>8 bytes), the entry thunk synthesizes a hidden sret
pointer parameter for the x64 side. However, this
parameter was never marked with the sret attribute, so ISel did not copy
its value into `x8` (the Arm64EC mapping of `RAX`) on return. This
caused the x64 caller to see a garbage pointer in `RAX` instead of the
return buffer address.

The change adds the sret attribute to the thunk's synthesized pointer
parameter, so that `LowerFormalArguments` saves it and `LowerReturn`
restores it to `x8` before the tail call to `__os_arm64x_dispatch_ret`.

Fixes #185390

(cherry picked from commit 90978e484f289f4c7036486e375166f69a587b2b)
DeltaFile
+5-0llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
+2-0llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
+7-02 files

LLVM/project 4dfb4b6llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/lib/Target/X86 X86FastISel.cpp

[FastISel] Lower call instruction with illegal type returned (#180322)

Fix issue https://github.com/llvm/llvm-project/issues/179100
When lowering the call instruction with illegal type returned, we should
bail out and transfer the lowering to DAG. Otherwise the return value is
not promoted to proper type, but DAG would assume it has been promoted.

---------

Co-authored-by: Yuanke Luo <ykluo at birentech.com>
(cherry picked from commit 41ef3d083a0925cb9c184057f76a0d42ad5680ab)
DeltaFile
+55-0llvm/test/CodeGen/X86/bf16-fast-isel.ll
+26-0llvm/test/CodeGen/X86/pr179100.ll
+1-7llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+6-0llvm/lib/Target/X86/X86FastISel.cpp
+88-74 files

LLVM/project 92a6627llvm/lib/Transforms/Utils SimplifyCFG.cpp, llvm/test/Transforms/SimplifyCFG switch-umin.ll

[SimplifyCFG] process prof data when remove case in umin (#182261)

In #164097, we introduce a optimization for umin. But it does not handle
profile data correctly.
This PR remove profile data when remove cases.
Fixed: #181837

(cherry picked from commit 31e5f86a3cdc960ef7b2f0a533c4a37cf526cacd)
DeltaFile
+43-0llvm/test/Transforms/SimplifyCFG/switch-umin.ll
+1-1llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+44-12 files

LLVM/project 318adcellvm/lib/Target/AArch64 AArch64Features.td, llvm/unittests/TargetParser TargetParserTest.cpp

[AArch64][llvm] Update Armv9.7-A dependencies (#185034)

Update Armv9.7-A dependenies:
  * `FeatureF16MM` to depend on `FeatureNEON`
  * `FeatureF16F32DOT` enabled by default for Armv9.7-A

(cherry picked from commit cba914cecec3a8194c7eb5953e82028484d50289)
DeltaFile
+4-3llvm/lib/Target/AArch64/AArch64Features.td
+3-0llvm/unittests/TargetParser/TargetParserTest.cpp
+7-32 files

LLVM/project 7a9fd4aclang/lib/CodeGen CGExprCXX.cpp, clang/test/CodeGenCXX ms-vdtors-devirtualization.cpp

[win][clang] Fix devirtualization of vector deleting destructor call (#183741)

Since vector deleting destructor performs a loop over array elements and
calls delete[], simply devirtualizing call to it produces wrong code
with memory leaks.
Before emitting virtual call to vector deleting destructor, check if it
can be devirtualized, if yes, emit normal loop over array elements
instead of a virtual call.

No release note since this is a relatively recent regression.
This aims to fix https://github.com/llvm/llvm-project/issues/183621
DeltaFile
+111-0clang/test/CodeGenCXX/ms-vdtors-devirtualization.cpp
+55-45clang/lib/CodeGen/CGExprCXX.cpp
+166-452 files

LLVM/project eb011a7llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 zero_extend_vector_inreg.ll zero_extend_vector_inreg_of_broadcast.ll

[X86] Fold BLENDI(X,Y) -> VZEXT_MOVL if the upper elements are known to be zero (#186267)

The zext_inreg test changes are interesting - we mostly get closer to
the VPBLENDW(XMM,0) pattern, but the fast-shuffle targets still fail to
recognize the upper half of the YMM is zero and don't simplify the
AND(YMM,C) as much as they could.

Helps with regression identified on #182200
DeltaFile
+296-116llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
+88-36llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
+74-30llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
+6-0llvm/lib/Target/X86/X86ISelLowering.cpp
+464-1824 files

LLVM/project d193e4fllvm/utils/gn/secondary/llvm/lib/Target/Mips BUILD.gn

[gn build] Port 472c8f8d9696
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn
+1-01 files

LLVM/project 672b37bllvm/utils/gn/secondary/clang/lib/Analysis/Scalable BUILD.gn, llvm/utils/gn/secondary/clang/unittests/Analysis/Scalable BUILD.gn

[gn build] Port 4334fed5c954
DeltaFile
+2-0llvm/utils/gn/secondary/clang/lib/Analysis/Scalable/BUILD.gn
+1-0llvm/utils/gn/secondary/clang/unittests/Analysis/Scalable/BUILD.gn
+3-02 files

LLVM/project 2e95f58llvm/utils/gn/secondary/llvm/lib/Debuginfod BUILD.gn, llvm/utils/gn/secondary/llvm/lib/Support/HTTP BUILD.gn

[gn] port 5eaf19a15129 (Support/HTTP)
DeltaFile
+11-0llvm/utils/gn/secondary/llvm/lib/Support/HTTP/BUILD.gn
+9-0llvm/utils/gn/secondary/llvm/unittests/Support/HTTP/BUILD.gn
+1-4llvm/utils/gn/secondary/llvm/unittests/Debuginfod/BUILD.gn
+1-2llvm/utils/gn/secondary/llvm/lib/Debuginfod/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/tools/llvm-debuginfod-find/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/tools/llvm-debuginfod/BUILD.gn
+24-65 files not shown
+29-611 files

LLVM/project 4376fbdclang/test/OpenMP target_teams_distribute_parallel_for_simd_schedule_codegen.cpp teams_distribute_parallel_for_simd_schedule_codegen.cpp

[OpenMP] Move OpenMP implicit argument to the end and reformat (#185989)

Summary:
We use this `dyn_ptr` argument in Clang/OpenMP to handle the
`KernelLaunchEnvironment`. This is a per-kernel argument used to share
some information. Currenetly, it's prepended to the argument list and we
generate storage for it in the runtime.

This is bad for a few reasons:
1. It changes the ABI by shifting user arguments
2. It cannot be trivially be left uninitialized if unused
3. The runtime must allocate its own memory for it

This PR changes it to be appended instead. Additionally, space for this
is always emitted. This means the OMPIRBuilder itself will provide the
storage, we simply need to populate it in the runtime if it is used.
This means that if it's unused we don't always pay the cost and it's
easier for non-OpenMP users to ignore it.


    [4 lines not shown]
DeltaFile
+5,294-4,814clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
+5,238-4,758clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
+4,350-4,098clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
+4,004-3,524clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
+4,000-3,520clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
+3,590-3,174clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
+26,476-23,888350 files not shown
+126,819-112,620356 files

LLVM/project 94819cclldb/include/lldb/ValueObject ValueObject.h, lldb/source/API SBValue.cpp

[LLDB] Modify CreateValueObjectFrom* to take an ExecutionContext (#185547)

Currently these functions take a target pointer. In Cross-language
projects this means it's down to chance what typesystem the resulting
value will be in, since the implementation returns the first scratch
type system in the target, which depends on the order of images and
their implementation language.

By passing in an execution context the selected frame is used to
determine the typesystem, which is usually the expected outcome when
using DIL.

This should be entirely NFC for Clang-only LLDBs, but is a necessity for
LLDBs with additional type system plugins such as the Swift plugin.

Assisted by Claude to patch the call sites.
DeltaFile
+32-39lldb/source/ValueObject/ValueObject.cpp
+17-16lldb/include/lldb/ValueObject/ValueObject.h
+24-7lldb/source/API/SBValue.cpp
+13-8lldb/source/ValueObject/DILEval.cpp
+3-2lldb/unittests/DataFormatter/FormatterSectionTest.cpp
+89-725 files

LLVM/project edf6dbellvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU wmma-coexecution-valu-hazards.mir

[AMDGPU] Include TRANS instructions in WMMA coexecution hazard checking
DeltaFile
+17-0llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
+2-2llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+19-22 files

LLVM/project 2d70dbdmlir/test/Transforms inlining.mlir, mlir/test/lib/Dialect/Test TestDialectInterfaces.cpp

[mlir][test] Fix UNREACHABLE in TestInlinerInterface for multi-block inlining (#186266)

When the MLIR inliner inlines a callable region that has more than one
block, it calls `handleTerminator(op, Block *newDest)` for the
terminator of every inlined block. `TestInlinerInterface` only
implemented the single-block variant (`handleTerminator(op,
ValueRange)`), so the default `llvm_unreachable` was hit when inlining a
`test.functional_region_op` whose body contained multiple blocks (e.g.
an explicit `cf.br` jump to a successor block whose terminator was
`test.return`).

Fix: add the missing `handleTerminator(op, Block *)` override to
`TestInlinerInterface`. Mirror the pattern used by
`FuncDialectInlinerExtension`: if the terminator is a `TestReturnOp`,
replace it with a `cf.br` to `newDest` carrying the return operands. Any
other terminator (e.g. `cf.br` for intra-region branches) is left
untouched — the existing `ControlFlowInlinerInterface` no-op already
handles those correctly.


    [5 lines not shown]
DeltaFile
+23-0mlir/test/Transforms/inlining.mlir
+14-0mlir/test/lib/Dialect/Test/TestDialectInterfaces.cpp
+37-02 files

LLVM/project 5775e42utils/bazel/llvm-project-overlay/mlir/test/Dialect BUILD.bazel

[bazel] fix .mlir test added in #186078. (#186265)
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/test/Dialect/BUILD.bazel
+1-01 files

LLVM/project fe2537alibc/config/windows entrypoints.txt, libc/include wctype.yaml

[libc] Add missing iswdigit to wctype.yaml and Windows entrypoints (#186023)

`iswdigit` was implemented
(https://github.com/llvm/llvm-project/pull/181635) but not declared in
the generated wctype.h (wctype.yaml) and was missing from the Windows
config entrypoints.

This pr declares iswdigit in wctype.h and enables it for the Windows
config.

also is part of https://github.com/llvm/llvm-project/issues/185136.
DeltaFile
+6-0libc/include/wctype.yaml
+1-0libc/config/windows/entrypoints.txt
+7-02 files

LLVM/project e615400llvm/include/llvm/Transforms/Utils SampleProfileLoaderBaseImpl.h, llvm/lib/Transforms/IPO SampleProfile.cpp

[SampleProfile] Skip counting mismatched weak symbols during profile loading (#185514)

Weak symbols may be overridden during linking, and this may cause
profile mismatch when compiling the weak symbols, while the profile was
created based on the overriding function. Skip counting the weak symbol
while checking the mismatched function profiles to avoid false alarm on
rejecting legit profiles.
DeltaFile
+13-0llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
+12-0llvm/test/Transforms/SampleProfile/weak-symbol-profile-mismatch.ll
+5-0llvm/test/Transforms/SampleProfile/Inputs/weak-symbol-profile-mismatch.prof
+2-1llvm/lib/Transforms/IPO/SampleProfile.cpp
+32-14 files

LLVM/project c0e1286mlir/include/mlir/Dialect/OpenACC OpenACCUtilsCG.h, mlir/include/mlir/Dialect/OpenACC/Transforms Passes.td

[acc] Introduce ACCRoutineLowering for `acc routine` specialization (#186243)

This pass handles `acc routine` directive by creating specialized
functions with appropriate parallelism information that can be used for
eventual creation of device function.

For each acc.routine that is not bound by name, the pass creates a new
function (the "device" copy) whose body is a single acc.compute_region
containing a clone of the original (host) function body. Parallelism is
expressed by one acc.par_width derived from the routine's clauses (seq,
vector, worker, gang). The device copy created is simply a staging place
for eventual move to device module level function.

---------

Co-authored-by: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
DeltaFile
+250-0mlir/lib/Dialect/OpenACC/Transforms/ACCRoutineLowering.cpp
+125-0mlir/test/Dialect/OpenACC/acc-routine-lowering.mlir
+65-0mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
+38-14mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
+25-0mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
+8-1mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
+511-151 files not shown
+512-157 files

LLVM/project 475cc4fllvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/X86 cost-any-of.ll

[VPlan] Account for any-of costs in legacy cost model

Some VPlan transforms, like vectorizing fmin without fast-math,
introduce AnyOfs, which have costs assigned in the VPlan-based cost
model, but not the legacy cost model. Account for their cost like done
for other similar VPInstrctions, like EVL.

Fixes https://github.com/llvm/llvm-project/issues/185867.
DeltaFile
+84-0llvm/test/Transforms/LoopVectorize/X86/cost-any-of.ll
+1-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+85-02 files

LLVM/project 6c35a67clang/lib/CodeGen CGExprScalar.cpp, clang/test/CodeGen ubsan-type-ignorelist-category.test

[Clang] Check sanitizer ignorelist for divrem overflow (#185721)

Instrumentation emitted for overflow by division was not checking with the sanitizer case list's type entries.

The original type-based ignorelist support (#107332) added `isTypeIgnoredBySanitizer` calls to `CanElideOverflowCheck`, which covers `+`, `-`, `*`, `++`, `--`. However, division and remainder have a separate code path in `EmitUndefinedBehaviorIntegerDivAndRemCheck` that never calls `CanElideOverflowCheck` or checks the ignorelist directly.

Add a check so that the SCL is honored for the div/rem case.
DeltaFile
+18-0clang/test/CodeGen/ubsan-type-ignorelist-category.test
+3-1clang/lib/CodeGen/CGExprScalar.cpp
+21-12 files

LLVM/project 5a369dalldb/source/Plugins/SymbolFile/DWARF DWARFCompileUnit.cpp

[lldb] Unify logging for GetAttributeAddressRanges error (#186258)

Use the same format string in DWARFCompileUnit.cpp as we do everywhere
else to report the error from GetAttributeAddressRanges. I noticed the
inconsistency when looking at our system log:

```
2026-03-12 05:36:48.600914 -0700        0x2e66: DIE has no address range information
2026-03-12 05:36:48.600950 -0700        0x2e8c: DIE has no address range information
2026-03-12 05:36:48.601068 -0700        DIE(0x1dc2): DIE has no address range information
2026-03-12 05:36:48.631000 -0700        DIE(0x80f4): DIE has no address range information
```
DeltaFile
+1-1lldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.cpp
+1-11 files

LLVM/project c7e66a6clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Headers/hlsl hlsl_alias_intrinsics.h

[HLSL] Add WaveActiveBitXor function (#185776)

This PR adds WaveActiveBitXor function to HLSL, with spirv and DXIL code
generation.
Fixes https://github.com/llvm/llvm-project/issues/99168
DeltaFile
+82-0clang/test/CodeGenHLSL/builtins/WaveActiveBitXor.hlsl
+34-0clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+32-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitXor.ll
+23-0clang/test/CodeGenHLSL/builtins/WaveActiveBitXor-errors.hlsl
+19-0llvm/test/CodeGen/DirectX/WaveActiveBitXor.ll
+12-1clang/lib/CodeGen/CGHLSLBuiltins.cpp
+202-110 files not shown
+229-216 files