LLVM / project - FreshBSD

LLVM/project e08c1c5 — llvm/test/CodeGen/RISCV/rvv vitofp-sdnode.ll vfptoi-sdnode.ll

2026-04-21 01:09:18 UTC by Brandon Wu via GitHub on ⎇

main

[RISCV][llvm] Support [s|u]int_to_fp and fp_to_[s|u]int for zvfbfa (#192287)

Delta		File
+878	-428	llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862	-426	llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+369	-109	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+201	-73	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+114	-2	llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
+114	-2	llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
+2,538	-1,040	7 files not shown
+2,743	-1,094	13 files

LLVM/project 5fa31cb — llvm/lib/Target/RISCV RISCVInstrInfoVSDPatterns.td RISCVInstrInfoVVLPatterns.td, llvm/test/CodeGen/RISCV/rvv vfwmacc-sdnode.ll fixed-vectors-vfwmacc.ll

2026-04-21 01:08:48 UTC by Brandon Wu via GitHub on ⎇

main

[llvm][RISCV] Handle miscompile of widening fma in zvfbfa codegen (#192412)

Delta		File
+40	-40	llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
+40	-40	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
+14	-10	llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+3	-2	llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+97	-92	4 files

LLVM/project 33c5aeb — llvm/test/CodeGen/RISCV/rvv fixed-vectors-vfwadd.ll fixed-vectors-vfwsub.ll

2026-04-21 01:08:25 UTC by Brandon Wu via GitHub on ⎇

main

[RISCV][llvm] Support widening fadd, fsub and fmul codegen for zvfbfa (#192414)

Delta		File
+668	-4	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
+619	-4	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
+578	-4	llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+578	-4	llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+414	-4	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
+326	-4	llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
+3,183	-24	4 files not shown
+3,266	-301	10 files

LLVM/project acc3f73 — llvm/lib/Target/X86 X86InsertVZeroUpper.cpp X86VZeroUpper.cpp, llvm/test/CodeGen/X86 llc-pipeline-npm.ll

2026-04-21 00:58:32 UTC by Kyungtak Woo via GitHub on ⎇

main

[NewPM] Port x86-insert-vzero-upper (#181597)

Had to move X86InsertVZeroUpper to its own file like in
https://github.com/llvm/llvm-project/pull/179864
No test coverage added for now as there are no MIR->MIR tests exercising
this pass and we do not have enough ported to run any end to end tests.

Redo of https://github.com/llvm/llvm-project/pull/180886

Delta		File
+366	-0	llvm/lib/Target/X86/X86InsertVZeroUpper.cpp
+0	-353	llvm/lib/Target/X86/X86VZeroUpper.cpp
+6	-1	llvm/lib/Target/X86/X86.h
+4	-0	llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1	-2	llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+1	-1	llvm/lib/Target/X86/X86PassRegistry.def
+378	-357	2 files not shown
+380	-359	8 files

LLVM/project 890c3fc — clang/lib/CodeGen CGObjCMac.cpp

2026-04-21 00:52:13 UTC by Akira Hatanaka via GitHub on ⎇

main

[CodeGen] NFC: Fix and improve comments in CGObjCMac.cpp (#193119)

Extract comment changes from #191091.

Delta		File
+37	-31	clang/lib/CodeGen/CGObjCMac.cpp
+37	-31	1 files

LLVM/project 125fa54 — llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

2026-04-21 00:45:13 UTC by Vitaly Buka on ⎇

users/vitalybuka/spr/codegen-add-constexpr-and-static_assert-to-fold64to16

rebase

Created using spr 1.3.7

Delta		File
+26,606	-0	llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078	-0	llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604	-1,567	llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0	-1,370	llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662	-662	llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291	-0	llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241	-3,599	1,092 files not shown
+63,356	-20,992	1,098 files

LLVM/project d6c5a20 — llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

2026-04-21 00:45:12 UTC by Vitaly Buka on ⎇

users/vitalybuka/spr/main.codegen-add-constexpr-and-static_assert-to-fold64to16

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]

Delta		File
+26,606	-0	llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078	-0	llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604	-1,567	llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0	-1,370	llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662	-662	llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291	-0	llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241	-3,599	1,092 files not shown
+63,356	-20,992	1,098 files

LLVM/project 2e1d160 — llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

2026-04-21 00:45:10 UTC by Vitaly Buka on ⎇

users/vitalybuka/spr/nfccodegen-rename-hash-functions-in-machineblockhashinfo-for-consistency

rebase

Created using spr 1.3.7

Delta		File
+26,606	-0	llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078	-0	llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604	-1,567	llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0	-1,370	llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662	-662	llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291	-0	llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241	-3,599	1,092 files not shown
+63,356	-20,992	1,098 files

LLVM/project 5585194 — llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

2026-04-21 00:45:06 UTC by Vitaly Buka on ⎇

users/vitalybuka/spr/main.nfccodegen-rename-hash-functions-in-machineblockhashinfo-for-consistency

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]

Delta		File
+26,606	-0	llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078	-0	llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604	-1,567	llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0	-1,370	llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662	-662	llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291	-0	llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241	-3,599	1,092 files not shown
+63,356	-20,992	1,098 files

LLVM/project df4dd38 — llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

2026-04-21 00:44:58 UTC by Vitaly Buka on ⎇

users/vitalybuka/spr/nfcmachineblockhashinfo-fork-hash_16_bytes-to-guarantee-stability

rebase

Created using spr 1.3.7

Delta		File
+26,606	-0	llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078	-0	llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604	-1,567	llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0	-1,370	llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662	-662	llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291	-0	llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241	-3,599	1,092 files not shown
+63,356	-20,992	1,098 files

LLVM/project 3afda98 — llvm/lib/Target/RISCV RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rv64p.ll rv32p.ll

2026-04-21 00:44:28 UTC by Craig Topper via GitHub on ⎇

main

[RISCV][P-ext] Remateralize pli and plui (#193110)

Test cases were written by Claude Sonnet 4.5.

Delta		File
+225	-0	llvm/test/CodeGen/RISCV/rv64p.ll
+135	-0	llvm/test/CodeGen/RISCV/rv32p.ll
+5	-1	llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+365	-1	3 files

LLVM/project 4d2df3b — llvm/utils/gn/secondary/llvm/lib/Target/AArch64 BUILD.gn

2026-04-21 00:35:36 UTC by Nico Weber via GitHub on ⎇

main

[gn] port c95a333de7108 (#193121)

Delta		File
+4	-1	llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
+4	-1	1 files

LLVM/project ad180de — clang/include/clang/AST ASTContext.h, clang/lib/AST ASTContext.cpp ItaniumMangle.cpp

2026-04-21 00:31:14 UTC by Matheus Izvekov on ⎇

users/mizvekov/fix-decltype-dependence

[clang] implement CWG2064: ignore value dependence for decltype

The 'decltype' for a value-dependent (but non-type-dependent) should be known,
so this patch makes them non-opaque instead.

This patch also implements what's neceessary to allow overloading
on pure differences in instantiation dependence, making `std::void_t`
usable for SFINAE purposes.

This also readds a few test cases from da98651, which was a previous attempt
at resolving CWG2064.

Fixes #8740
Fixes #61818
Fixes #190388

Delta		File
+906	-175	clang/lib/AST/ASTContext.cpp
+312	-12	clang/test/SemaTemplate/instantiation-dependence.cpp
+151	-93	clang/lib/AST/ItaniumMangle.cpp
+76	-68	clang/lib/AST/Type.cpp
+76	-48	clang/lib/Sema/SemaTemplate.cpp
+95	-16	clang/include/clang/AST/ASTContext.h
+1,616	-412	83 files not shown
+2,381	-777	89 files

LLVM/project 0a5870d — llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

2026-04-21 00:25:59 UTC by Ziqing Luo on ⎇

users/ziqingluo/PR-172429193-2-split-1

Merge remote-tracking branch 'origin/main' into users/ziqingluo/PR-172429193-2-split-1

 Conflicts:
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.h
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevelFormat.h
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.h
        clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
        clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp

Delta		File
+275,101	-0	llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679	-0	llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682	-0	llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844	-0	llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613	-0	llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209	-0	llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128	-0	3,037 files not shown
+986,155	-65,820	3,043 files

LLVM/project 1290b82 — clang/test/SemaCUDA float128.cu

2026-04-21 00:24:52 UTC by Pranav Kant via GitHub on ⎇

main

[test] Remove redundant typedef (#193116)

Delta		File
+0	-1	clang/test/SemaCUDA/float128.cu
+0	-1	1 files

LLVM/project 66b86af — clang/test/CodeGen/RISCV rvv-builtin-reduce-ops.c

2026-04-21 00:17:38 UTC by Philip Reames via GitHub on ⎇

main

[clang][riscv] Add tests for __builtin_reduce_X support [NFC] (#193082)

It turns out we already support use of the __builtin_reduce_ family of
builtins on the builtin RVV types, but we have no test coverage which
demonstrates this.

Note that __builtin_reduce_mul is a bit of a cornercase as currently the
clang part works just fine, but the lowering will crash since we don't
have a vredprod-esq instruction. (See
https://github.com/llvm/llvm-project/pull/193094 for the lowering fix.)

Delta		File
+156	-0	clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
+156	-0	1 files

LLVM/project 212474a — clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageTest.cpp

2026-04-20 23:59:32 UTC by Ziqing Luo on ⎇

users/ziqingluo/PR-172429193-2-split-1

address comments

Delta		File
+59	-89	clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+59	-89	1 files

LLVM/project a10aae8 — offload/tools/kernelreplay llvm-omp-kernel-replay.cpp

2026-04-20 23:47:58 UTC by Kevin Sala Penades via GitHub on ⎇

main

[offload] Remove unnecessary extra allocations in kernel replay tool (#193108)

The tool had two extra allocations holding the device memory and
globals. Apparently, the AMDGPU plugin failed in the past to transfer
data from the file memory mapping, and required these extra buffers.
After testing it on MI300A and MI250X, this issue is not present
anymore. Thus, we are removing them for now.

Delta		File
+9	-23	offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
+9	-23	1 files

LLVM/project 6c35bdb — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 copyable_reorder.ll

2026-04-20 23:43:13 UTC by Alexey Bataev via GitHub on ⎇

main

[SLP] Normalize copyable operand order to group loads for better vectorization

When building operands for entries with copyable elements, non-copyable
lanes may have inconsistent operand order (e.g., some lanes have
load,add while others have add,load for commutative ops). This prevents
VLOperands::reorder() from grouping consecutive loads on one side,
degrading downstream vectorization.
Normalize in two steps during buildOperands:
1) Majority voting: swap lanes that are the exact inverse of the
   majority operand-type pattern.
2) Load preference: if the majority pattern has loads at OpIdx 1
   (strict majority), swap to put loads at OpIdx 0, enabling
   vector load + copyable patterns.

Reviewers: hiraditya, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/189181

Delta		File
+12	-26	llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
+26	-7	llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+38	-33	2 files

LLVM/project 500e913 — llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.sat.pk.ll

2026-04-20 23:41:28 UTC by Aidan Shilling via GitHub on ⎇

main

AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_sat_pk4_i4_i8 / amdgcn_sat_pk4_u4_u8 (#193096)

Delta		File
+2	-2	llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
+4	-0	llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+6	-2	2 files

LLVM/project f46da03 — lldb/source/Plugins/Platform/WebAssembly PlatformWasm.cpp

2026-04-20 23:37:36 UTC by Jonas Devlieghere via GitHub on ⎇

main

[lldb] Don't enable ASLR for the Wasm runtime (#193115)

We're launching the Wasm runtime (a native host binary), not the target
being debugged. Clear flags that don't apply to the runtime process.

Delta		File
+3	-1	lldb/source/Plugins/Platform/WebAssembly/PlatformWasm.cpp
+3	-1	1 files

LLVM/project 9356e1e — clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageExtractor.cpp

2026-04-20 23:33:19 UTC by Ziqing Luo via GitHub on ⎇

users/ziqingluo/PR-172429193-2-split-1

Update clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>

Delta		File
+1	-1	clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
+1	-1	1 files

LLVM/project 6fe6f1b — llvm/include/llvm/CodeGen MachineBlockHashInfo.h, llvm/include/llvm/Passes MachinePassRegistry.def

2026-04-20 23:30:47 UTC by Vitaly Buka via GitHub on ⎇

main

[CodeGen] Add MachineBlockHashInfoAnalysis for the new pass manager (#193107)

This patch introduces MachineBlockHashInfoAnalysis and its corresponding
printer pass MachineBlockHashInfoPrinterPass to the new pass manager.

This allows running -passes="print<machine-block-hash>" via llc.

Can't merge before #192826, and don't want to mix test patch with
determinism fix in #192826.

This is #192911 which was accidentally merged into spr/users branch.

Delta		File
+53	-0	llvm/test/CodeGen/X86/machine-block-hash.mir
+23	-1	llvm/lib/CodeGen/MachineBlockHashInfo.cpp
+23	-0	llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
+3	-0	llvm/include/llvm/Passes/MachinePassRegistry.def
+1	-0	llvm/lib/Passes/PassBuilder.cpp
+103	-1	5 files

LLVM/project ce73ab7 — clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageTest.cpp

2026-04-20 23:28:32 UTC by Ziqing Luo via GitHub on ⎇

users/ziqingluo/PR-172429193-2-split-1

Update clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>

Delta		File
+1	-1	clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+1	-1	1 files

LLVM/project 75790bf — clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel EntityPointerLevel.h EntityPointerLevelFormat.h, clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsage.h

2026-04-20 23:27:47 UTC by Ziqing Luo via GitHub on ⎇

main

[SSAF][UnsafeBufferUsage] Add APIs to the EntityPointerLevel module for UnsafeBufferUsage (#191333)

- UnsafeBufferUsage serialization uses EntityPointerLevel's API to
serialize EntityPointerLevels.
- Add APIs to EntityPointerLevel for creating EPLs from Decls and
incrementing EPL's pointer level.
- Improve UnsafeBufferUsage serialization error messages with a test.

---------

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>

Delta		File
+103	-33	clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
+29	-8	clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.h
+35	-0	clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevelFormat.h
+9	-19	clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.cpp
+13	-5	clang/test/Analysis/Scalable/UnsafeBufferUsage/tu-summary-serialization.test
+2	-6	clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.h
+191	-71	1 files not shown
+193	-73	7 files

LLVM/project 13e18f8 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 select-logical-or-and-i1-vector.ll

2026-04-20 23:22:45 UTC by Alexey Bataev via GitHub on ⎇

main

[SLP] Improve cost model for i1 select-as-or/and patterns

Model `select i1 %c, i1 true, i1 %d` as `or` and
`select i1 %c, i1 %d, i1 false` as `and` in the SLP cost model, since
these are the operations the backend will lower them to. The previous
select cost overestimated the vector cost of these patterns, preventing
profitable vectorization of i1 condition chains.

Reviewers: hiraditya, RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/188572

Delta		File
+84	-34	llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+20	-24	llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
+104	-58	2 files

LLVM/project c758592 — llvm/docs/CommandGuide dsymutil.rst, llvm/test/tools/dsymutil codesign.test cmdline.test

2026-04-20 23:10:17 UTC by Jonas Devlieghere via GitHub on ⎇

main

[dsymutil] Add support for code signing dSYM bundles (#190676)

This PR adds support for code signing the dSYM bundle using the
`codesign` command line utility.

Delta		File
+57	-0	llvm/tools/dsymutil/dsymutil.cpp
+15	-0	llvm/test/tools/dsymutil/codesign.test
+6	-0	llvm/tools/dsymutil/Options.td
+5	-0	llvm/docs/CommandGuide/dsymutil.rst
+1	-0	llvm/test/tools/dsymutil/cmdline.test
+84	-0	5 files

LLVM/project 9adf869 — llvm/include/llvm/CodeGen MachineBlockHashInfo.h, llvm/include/llvm/Passes MachinePassRegistry.def

2026-04-20 22:59:31 UTC by Vitaly Buka on ⎇

users/vitalybuka/spr/codegen-add-machineblockhashinfoanalysis-for-the-new-pass-manager-192911

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

Delta		File
+53	-0	llvm/test/CodeGen/X86/machine-block-hash.mir
+23	-1	llvm/lib/CodeGen/MachineBlockHashInfo.cpp
+23	-0	llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
+3	-0	llvm/include/llvm/Passes/MachinePassRegistry.def
+1	-0	llvm/lib/Passes/PassBuilder.cpp
+103	-1	5 files

LLVM/project 83dfe3d — lldb/include/lldb/Target ExecutionContextScope.h

2026-04-20 22:59:22 UTC by Dave Lee via GitHub on ⎇

main

[lldb] Fix minor docstring mis-formatting (NFC) (#193106)

Delta		File
+1	-2	lldb/include/lldb/Target/ExecutionContextScope.h
+1	-2	1 files

LLVM/project 4e32f89 — lldb/include/lldb/Symbol Symtab.h, lldb/source/Symbol Symtab.cpp

2026-04-20 22:58:00 UTC by Adrian Prantl via GitHub on ⎇

users/vitalybuka/spr/codegen-add-machineblockhashinfoanalysis-for-the-new-pass-manager-192911

[LLDB] Fix potential data race in Symtab initialization (#192753)

Claude pointed out to me that Symtab::FindFunctionSymbols doesn't lock
the mutex before checking m_name_indexes_computed and recomputing it. On
top of that all the initialization flags are bitfields, which makes any
unguarded concurrent accesses UB. Changing them to bools should no
longer be necessary after introducing a lock, but several of the public
methods trust that their caller holds the lock so I'm opting to remove
this footgun just in case.

rdar://174988238

Delta		File
+105	-111	lldb/source/Symbol/Symtab.cpp
+7	-4	lldb/include/lldb/Symbol/Symtab.h
+112	-115	2 files