LLVM/project 1a772bcllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 setcc-poison.ll setcc-carry.ll

[X86] Improve FREEZE node elimination for SETCC operations (#192362)

This improves FREEZE node handling around SETCC and SETCC_CARRY
operations to enable better optimization, particularly for APX
CCMP/CTEST
pattern matching with fastmath comparisons.

Resolve https://github.com/llvm/llvm-project/issues/191716.
DeltaFile
+149-0llvm/test/CodeGen/X86/setcc-poison.ll
+112-0llvm/test/CodeGen/X86/setcc-carry.ll
+37-0llvm/test/CodeGen/X86/apx/ctest.ll
+37-0llvm/test/CodeGen/X86/apx/ccmp.ll
+10-10llvm/test/CodeGen/X86/freeze-binary.ll
+4-0llvm/lib/Target/X86/X86ISelLowering.cpp
+349-106 files

LLVM/project a1a40cblldb/packages/Python/lldbsuite/test lldbtest.py, lldb/packages/Python/lldbsuite/test/make Makefile.rules

[lldb/test] Fix shared library symlinks for remote testing (#189177)

When running tests on a remote device, framework convenience symlinks
created by test Makefiles (e.g. `$(BUILDDIR)/Framework` pointing to
`$(BUILDDIR)/Framework.framework/Framework`) cause launch failures.

`Platform::Install` recreates these as symlinks on the remote device
pointing to host build paths that don't exist, resulting in "No such
file or directory" from dyld.

This patch changes `LN_SF` in Makefile.rules to strip the common
directory prefix from the symlink source using `patsubst` so it produces
relative symlinks instead of absolute ones.

It also resolve symlinks with `os.path.realpath()` in
`registerSharedLibrariesWithTarget` before registering modules so that
`Platform::Install` sees a regular file and transfers the actual binary
content.


    [2 lines not shown]
DeltaFile
+7-1lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+1-0lldb/packages/Python/lldbsuite/test/lldbtest.py
+8-12 files

LLVM/project 0d0595bclang/lib/CodeGen/Targets SPIR.cpp, clang/test/CodeGen/AMDGPU amdgpu-atomic-float.c

[SPIR-V] Encode Atomic metadata as UserSemantic string decoration (#193019)

AMDGPU uses metadata to guide atomic related optimisations. SPIR-V was
not handling it, which led to significant and spurious performance
differences. This patch fixes this oversight by encoding the metadata as
UserSemantic string decorations applied to the atomic instructions.
DeltaFile
+304-18clang/test/CodeGenCUDA/atomic-options.hip
+194-25clang/test/CodeGenHIP/amdgpu-flat-atomic-fadd.hip
+113-16clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c
+70-9clang/test/CodeGenHIP/amdgpu-global-atomic-fadd.hip
+25-0clang/lib/CodeGen/Targets/SPIR.cpp
+22-0llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+728-683 files not shown
+751-699 files

LLVM/project 46e09c5llvm/lib/Transforms/Scalar ExpandMemCmp.cpp

[ExpandMemCmp] Pre-collect memcmp calls to improve compile time (#193415)

Avoid restarting the basic block iteration from the beginning of the
function every time a memcmp/bcmp is expanded. Instead, pre-collect all
memcmp/bcmp calls and process them in a single pass.
DeltaFile
+17-40llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
+17-401 files

LLVM/project 793bdd8libc/src/__support/threads CndVar.h CMakeLists.txt, libc/src/__support/threads/linux CndVar.cpp CMakeLists.txt

[libc][CndVar] reimplmement conditional variable with FIFO ordering (#192748)

This PR reimplements conditional variable with two different variants:
- futex-based shared condvar with atomic counter for waiters
- queue-based private condvar

Notice that thread-local queue node cannot be reliably accessed in
shared processes, so we cannot use a unified implementation in this
case.

POSIX.1-2024 (Issue 8) added atomicity conditions to conditional
variable:

- The `pthread_cond_broadcast()` function shall, **as a single atomic
operation**, determine which threads, if any, are blocked on the
specified condition variable cond and unblock all of these threads.

- The `pthread_cond_signal()` function shall, as a **single atomic
operation**, determine which threads, if any, are blocked on the

    [41 lines not shown]
DeltaFile
+324-25libc/src/__support/threads/CndVar.h
+128-0libc/test/integration/src/__support/threads/cndvar_test.cpp
+0-106libc/src/__support/threads/linux/CndVar.cpp
+16-7libc/src/__support/threads/CMakeLists.txt
+0-23libc/src/__support/threads/linux/CMakeLists.txt
+18-0libc/test/integration/src/__support/threads/CMakeLists.txt
+486-16113 files not shown
+523-18919 files

LLVM/project ccc608fllvm/lib/Target/DirectX DXILOpLowering.cpp DXILResourceAccess.cpp, llvm/test/CodeGen/DirectX TextureLoad.ll

[DirectX] Implement lowering of Texture Load and Texture .operator[] (#193343)

Fixes https://github.com/llvm/llvm-project/issues/192546 and
https://github.com/llvm/llvm-project/issues/192558

This PR defines the TextureLoad DXIL Op (opcode 66), and implements
lowering of the texture load (dx_resource_load_level) intrinsic to the
DXIL op.

This PR also implements the transformation of loads from texture
resources (via dx_resource_getpointer) into dx_resource_load_level
intrinsics.

Assisted-by: Claude Opus 4.7
DeltaFile
+223-0llvm/test/CodeGen/DirectX/TextureLoad.ll
+97-0llvm/test/CodeGen/DirectX/ResourceAccess/load_texture.ll
+57-0llvm/lib/Target/DirectX/DXILOpLowering.cpp
+46-1llvm/lib/Target/DirectX/DXILResourceAccess.cpp
+14-1llvm/lib/Target/DirectX/DXIL.td
+437-25 files

LLVM/project 417f5bccompiler-rt/test/sanitizer_common/TestCases/Posix getpw_getgr.cpp

[NFC][sanitizer_common] Fix getpw_getgr.cpp test for large groups (#193625)

On my desktop buffer needs to be about 1MB.
DeltaFile
+13-2compiler-rt/test/sanitizer_common/TestCases/Posix/getpw_getgr.cpp
+13-21 files

LLVM/project 6fa0a86compiler-rt/test/sanitizer_common/TestCases/Posix getpw_getgr.cpp

simplify

Created using spr 1.3.7
DeltaFile
+1-4compiler-rt/test/sanitizer_common/TestCases/Posix/getpw_getgr.cpp
+1-41 files

LLVM/project 50b94b6llvm/docs AMDGPUUsage.rst, llvm/include/llvm/IR IntrinsicsAMDGPU.td

[AMDGPU] Add a sched group mask for LDSDMA instructions

The existing VMEM masks are not fine-grained enough for some use cases. For
example, if users want to control async loads, using VMEM may cause the compiler
to pick instructions it shouldn't.

This PR adds a new sched group mask for LDSDMA instructions. It is a subclass of
VMEM, but only targets isLDSDMA instructions.
DeltaFile
+342-0llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
+21-21llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
+15-7llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+2-0llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+1-0llvm/docs/AMDGPUUsage.rst
+381-285 files

LLVM/project 779dfb8compiler-rt/test/sanitizer_common/TestCases/Posix getpw_getgr.cpp

format

Created using spr 1.3.7
DeltaFile
+1-1compiler-rt/test/sanitizer_common/TestCases/Posix/getpw_getgr.cpp
+1-11 files

LLVM/project 95aceabcompiler-rt/test/sanitizer_common/TestCases/Posix getpw_getgr.cpp

size

Created using spr 1.3.7
DeltaFile
+1-1compiler-rt/test/sanitizer_common/TestCases/Posix/getpw_getgr.cpp
+1-11 files

LLVM/project 79c85c8compiler-rt/test/sanitizer_common/TestCases/Posix getpw_getgr.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+16-2compiler-rt/test/sanitizer_common/TestCases/Posix/getpw_getgr.cpp
+16-21 files

LLVM/project cdbb670llvm/test/Transforms/SLPVectorizer/RISCV revec-strided-store.ll

[SLP][NFC] Precommit test for strided store revectorization (#191569)
DeltaFile
+107-0llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll
+107-01 files

LLVM/project 9020920clang/lib/CIR/CodeGen CIRGenCall.cpp

[CIR][NFC] Delete unnecessary errorNYI call in emitDelegateCallArg (#193608)

There was a call to errorNYI in `CIRGenFunction::emitDelegateCallArg`
when the parameter decl was a `CXXRecordDecl`. This was an artifact from
an older version of this function in classic codegen, which called
`ErrorUnsupported` for InAlloca arguments, but that handling was deleted
as part of https://reviews.llvm.org/D154007.
DeltaFile
+0-6clang/lib/CIR/CodeGen/CIRGenCall.cpp
+0-61 files

LLVM/project a5ce0fcllvm/include/llvm/Analysis TargetTransformInfoImpl.h, llvm/include/llvm/CodeGen BasicTTIImpl.h

[LV][RISCV] Add explicit LMUL controls via computeFeasibleMaxVF

Add components of maxVF and its support for scalable
vectorization. The default for unspecified RISCV is
LMUL=4 with this change, so some tests will have
the flag that controls max LMUL to extend to LMUL=8
when the request is made.
DeltaFile
+26-0llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+7-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+3-3llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-maxbandwidth.ll
+5-0llvm/include/llvm/CodeGen/BasicTTIImpl.h
+5-0llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+5-0llvm/lib/Analysis/TargetTransformInfo.cpp
+51-34 files not shown
+59-510 files

LLVM/project 819aabflldb/packages/Python/lldbsuite/test lldbtest.py

[lldb] Update filecheck_log to use direct input (NFC-ish) (#193618)

Pass log files as direct input to `FileCheck` via its `-input-file`
option.

I had a failing test case where the log file contains the string being
checked for, and yet `FileCheck` failed. While debugging, I noticed the
output from running `platform shell -h -- cat ...` was somehow
truncated. I have not debugged why. As soon as I saw the issue, I
figured it was best to skip all the intermediaries, and pass the log
file straight to `FileCheck`.
DeltaFile
+12-7lldb/packages/Python/lldbsuite/test/lldbtest.py
+12-71 files

LLVM/project 2ca5abellvm/lib/Target/SPIRV SPIRVPreLegalizer.cpp SPIRVPrepareFunctions.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly inline_asm.ll

[SPIR-V] Handle ASM with multiple outputs (#187128)

Inline ASM that writes to multiple registers is represented as a struct
returning call in LLVM IR. We did not handle this properly, as we
mutated the callsite, but did not correctly retrieve the type during
lowering to SPIR-V. Furthermore, IRTranslator tries to do some clever
things when lowering ASM, which are completely unhelpful to SPIR-V,
which merely wants to pass the original ASM through. This patch
correctly retains the IR type and cleans up the IRTranslator introduced
noise, matching how the SPIRV-LLVM Translator would handle such cases.
There is probably a cleaner reformulation of this to be had when we
rework the entire callsite mutation infra.

<!-- branch-stack-start -->

<!-- branch-stack-end -->

---------

Co-authored-by: Marcos Maronas <marcos.maronas at intel.com>
Co-authored-by: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
DeltaFile
+46-36llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+35-5llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+35-1llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll
+33-0llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+8-4llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+6-2llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+163-481 files not shown
+166-487 files

LLVM/project 2c7b820lldb/include/lldb/ValueObject ValueObject.h ValueObjectConstResult.h, lldb/source/Plugins/Language/CPlusPlus GenericList.cpp

Ensure that the Synthetic children of a ValueObject are managed by their parents ClusterManager (#192561)

A very common pattern in our synthetic child providers was to make the
child ValueObject using ValueObjectConstResult::Create or some form of
the static ValueObject::CreateValueObjectFrom*** methods, and store and
hand that out as the child. Doing that creates a "root" ValueObject
whose lifecycle is not linked to the lifecycle of the ValueObject it is
a child of. And that means it is possible that either the child or the
parent could have gotten destroyed when the other ValueObject gets asked
a question about it.

For the most part this doesn't happen because there are usually enough
other shared pointer references binding the two to keep both sides
alive. But we have gotten a small but steady stream of reports for years
now of crashes where a ValueObject accesses its ClusterManager but that
has already been deleted. I've never been able to find a reproducible
case of this, but one plausible cause is that we are violating the
contract that "all the children of a ValueObject have coterminous
lifespans, enforced by the ClusterManager". So it is unsurprising that

    [31 lines not shown]
DeltaFile
+106-28lldb/include/lldb/ValueObject/ValueObject.h
+58-31lldb/source/ValueObject/ValueObject.cpp
+47-39lldb/source/ValueObject/ValueObjectConstResult.cpp
+41-16lldb/include/lldb/ValueObject/ValueObjectConstResult.h
+23-19lldb/source/Plugins/Language/ObjC/NSException.cpp
+14-14lldb/source/Plugins/Language/CPlusPlus/GenericList.cpp
+289-14734 files not shown
+437-25740 files

LLVM/project c326518llvm/test/CodeGen/AArch64 hadd-combine.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+785-891llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+897-327llvm/test/CodeGen/AArch64/hadd-combine.ll
+365-365llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+292-292llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
+224-224llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
+223-223llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
+2,786-2,322276 files not shown
+7,789-5,459282 files

LLVM/project 64a3001llvm/test/CodeGen/AArch64 hadd-combine.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll

rebase

Created using spr 1.3.7
DeltaFile
+785-891llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+897-327llvm/test/CodeGen/AArch64/hadd-combine.ll
+365-365llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+292-292llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
+224-224llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
+223-223llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
+2,786-2,322276 files not shown
+7,789-5,459282 files

LLVM/project 5e12ef8llvm/test/CodeGen/AArch64 hadd-combine.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll

rebase

Created using spr 1.3.7
DeltaFile
+785-891llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+897-327llvm/test/CodeGen/AArch64/hadd-combine.ll
+365-365llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+292-292llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
+224-224llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
+223-223llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
+2,786-2,322276 files not shown
+7,789-5,459282 files

LLVM/project 3021dabllvm/test/CodeGen/AArch64 hadd-combine.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+785-891llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+897-327llvm/test/CodeGen/AArch64/hadd-combine.ll
+365-365llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+292-292llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
+224-224llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
+223-223llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
+2,786-2,322276 files not shown
+7,789-5,459282 files

LLVM/project 9f5e0aclibc/include elf.yaml

[libc] Add some more segment type macros

Missing macros from
https://refspecs.linuxfoundation.org/LSB_5.0.0/LSB-Core-generic/LSB-Core-generic/progheader.html.

We need PT_GNU_EH_FRAME for libunwind.

Reviewers: jtstogel, frobtech, vonosmas, michaelrj-google

Pull Request: https://github.com/llvm/llvm-project/pull/193604
DeltaFile
+12-0libc/include/elf.yaml
+12-01 files

LLVM/project 802de7eoffload/libomptarget interface.cpp private.h, offload/plugins-nextgen/common/include RecordReplay.h

[offload] Allow replay repetitions and report basic timing (#193388)

This commit extends the kernel replay tool to perform multiple replay
repetitions on the same process. It also prints the execution time of
the kernel replay, which includes the kernel launch and kernel
synchronization (replay I/O time is excluded). Precise kernel timing
should be obtained through the corresponding profiling tools for now.

The output report after recording has been improved as well.
DeltaFile
+55-19offload/plugins-nextgen/common/src/RecordReplay.cpp
+33-13offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
+25-0offload/plugins-nextgen/common/include/RecordReplay.h
+13-8offload/libomptarget/interface.cpp
+8-9offload/libomptarget/private.h
+10-2offload/libomptarget/omptarget.cpp
+144-512 files not shown
+155-558 files

LLVM/project e68d91allvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp

[NFC][SPIRV] Introduce function to handle 64 bits overflow (#193088)

Some intrinsics require special logic to deal with 64bits, usually
because vulkan doesn't allow 64 overloads. This patch introduces a
function that can be reused in some of those intrinsics to deal with
this specific case.

Requested here
https://github.com/llvm/llvm-project/pull/193068#discussion_r3113352858
as part of https://github.com/llvm/llvm-project/issues/192756
DeltaFile
+91-157llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+91-1571 files

LLVM/project fa0de06libc/include elf.yaml

rebase

Created using spr 1.3.7
DeltaFile
+12-0libc/include/elf.yaml
+12-01 files

LLVM/project f720315libc/include elf.yaml

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+12-0libc/include/elf.yaml
+12-01 files

LLVM/project 3be5c2elibc/include elf.yaml

rebase

Created using spr 1.3.7
DeltaFile
+12-0libc/include/elf.yaml
+12-01 files

LLVM/project 769f03clibc/include elf.yaml

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+12-0libc/include/elf.yaml
+12-01 files

LLVM/project c76e275libc/config/linux/x86_64 entrypoints.txt, libcxx/cmake/caches Generic-llvm-libc.cmake

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+0-62libcxx/cmake/caches/Generic-llvm-libc.cmake
+0-27libcxx/test/configs/llvm-libc++-llvm-libc.cfg.in
+0-27libcxxabi/test/configs/llvm-libc++abi-llvm-libc.cfg.in
+0-20libcxx/utils/ci/run-buildbot
+0-3libc/config/linux/x86_64/entrypoints.txt
+0-1395 files