LLVM/project e08c1c5llvm/test/CodeGen/RISCV/rvv vitofp-sdnode.ll vfptoi-sdnode.ll

[RISCV][llvm] Support [s|u]int_to_fp and fp_to_[s|u]int for zvfbfa (#192287)
DeltaFile
+878-428llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+862-426llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
+369-109llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+201-73llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+114-2llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll
+114-2llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll
+2,538-1,0407 files not shown
+2,743-1,09413 files

LLVM/project 5fa31cbllvm/lib/Target/RISCV RISCVInstrInfoVSDPatterns.td RISCVInstrInfoVVLPatterns.td, llvm/test/CodeGen/RISCV/rvv vfwmacc-sdnode.ll fixed-vectors-vfwmacc.ll

[llvm][RISCV] Handle miscompile of widening fma in zvfbfa codegen (#192412)
DeltaFile
+40-40llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
+40-40llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
+14-10llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+3-2llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+97-924 files

LLVM/project 33c5aebllvm/test/CodeGen/RISCV/rvv fixed-vectors-vfwadd.ll fixed-vectors-vfwsub.ll

[RISCV][llvm] Support widening fadd, fsub and fmul codegen for zvfbfa (#192414)
DeltaFile
+668-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
+619-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+578-4llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+414-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
+326-4llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
+3,183-244 files not shown
+3,266-30110 files

LLVM/project acc3f73llvm/lib/Target/X86 X86InsertVZeroUpper.cpp X86VZeroUpper.cpp, llvm/test/CodeGen/X86 llc-pipeline-npm.ll

[NewPM] Port x86-insert-vzero-upper (#181597)

Had to move X86InsertVZeroUpper to its own file like in
https://github.com/llvm/llvm-project/pull/179864
No test coverage added for now as there are no MIR->MIR tests exercising
this pass and we do not have enough ported to run any end to end tests.

Redo of https://github.com/llvm/llvm-project/pull/180886
DeltaFile
+366-0llvm/lib/Target/X86/X86InsertVZeroUpper.cpp
+0-353llvm/lib/Target/X86/X86VZeroUpper.cpp
+6-1llvm/lib/Target/X86/X86.h
+4-0llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1-2llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+1-1llvm/lib/Target/X86/X86PassRegistry.def
+378-3572 files not shown
+380-3598 files

LLVM/project 890c3fcclang/lib/CodeGen CGObjCMac.cpp

[CodeGen] NFC: Fix and improve comments in CGObjCMac.cpp (#193119)

Extract comment changes from #191091.
DeltaFile
+37-31clang/lib/CodeGen/CGObjCMac.cpp
+37-311 files

LLVM/project 125fa54llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

rebase

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project d6c5a20llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project 2e1d160llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

rebase

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project 5585194llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project df4dd38llvm/test/CodeGen/AArch64 sve-fixed-length-masked-expandloads.ll sve-streaming-mode-fixed-length-masked-expandload.ll, llvm/test/CodeGen/AArch64/GlobalISel select-with-no-legality-check.mir knownbits-vector.mir

rebase

Created using spr 1.3.7
DeltaFile
+26,606-0llvm/test/CodeGen/AArch64/sve-fixed-length-masked-expandloads.ll
+4,078-0llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-expandload.ll
+1,604-1,567llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,370llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
+662-662llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+1,291-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vector.mir
+34,241-3,5991,092 files not shown
+63,356-20,9921,098 files

LLVM/project 3afda98llvm/lib/Target/RISCV RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rv64p.ll rv32p.ll

[RISCV][P-ext] Remateralize pli and plui (#193110)

Test cases were written by Claude Sonnet 4.5.
DeltaFile
+225-0llvm/test/CodeGen/RISCV/rv64p.ll
+135-0llvm/test/CodeGen/RISCV/rv32p.ll
+5-1llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+365-13 files

LLVM/project 4d2df3bllvm/utils/gn/secondary/llvm/lib/Target/AArch64 BUILD.gn

[gn] port c95a333de7108 (#193121)
DeltaFile
+4-1llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
+4-11 files

LLVM/project ad180declang/include/clang/AST ASTContext.h, clang/lib/AST ASTContext.cpp ItaniumMangle.cpp

[clang] implement CWG2064: ignore value dependence for decltype

The 'decltype' for a value-dependent (but non-type-dependent) should be known,
so this patch makes them non-opaque instead.

This patch also implements what's neceessary to allow overloading
on pure differences in instantiation dependence, making `std::void_t`
usable for SFINAE purposes.

This also readds a few test cases from da98651, which was a previous attempt
at resolving CWG2064.

Fixes #8740
Fixes #61818
Fixes #190388
DeltaFile
+906-175clang/lib/AST/ASTContext.cpp
+312-12clang/test/SemaTemplate/instantiation-dependence.cpp
+151-93clang/lib/AST/ItaniumMangle.cpp
+76-68clang/lib/AST/Type.cpp
+76-48clang/lib/Sema/SemaTemplate.cpp
+95-16clang/include/clang/AST/ASTContext.h
+1,616-41283 files not shown
+2,381-77789 files

LLVM/project 0a5870dllvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge remote-tracking branch 'origin/main' into users/ziqingluo/PR-172429193-2-split-1

 Conflicts:
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.h
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevelFormat.h
        clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.h
        clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
        clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+41,844-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+40,613-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+37,209-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+597,128-03,037 files not shown
+986,155-65,8203,043 files

LLVM/project 1290b82clang/test/SemaCUDA float128.cu

[test] Remove redundant typedef (#193116)
DeltaFile
+0-1clang/test/SemaCUDA/float128.cu
+0-11 files

LLVM/project 66b86afclang/test/CodeGen/RISCV rvv-builtin-reduce-ops.c

[clang][riscv] Add tests for __builtin_reduce_X support [NFC] (#193082)

It turns out we already support use of the __builtin_reduce_ family of
builtins on the builtin RVV types, but we have no test coverage which
demonstrates this.

Note that __builtin_reduce_mul is a bit of a cornercase as currently the
clang part works just fine, but the lowering will crash since we don't
have a vredprod-esq instruction. (See
https://github.com/llvm/llvm-project/pull/193094 for the lowering fix.)
DeltaFile
+156-0clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
+156-01 files

LLVM/project 212474aclang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageTest.cpp

address comments
DeltaFile
+59-89clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+59-891 files

LLVM/project a10aae8offload/tools/kernelreplay llvm-omp-kernel-replay.cpp

[offload] Remove unnecessary extra allocations in kernel replay tool (#193108)

The tool had two extra allocations holding the device memory and
globals. Apparently, the AMDGPU plugin failed in the past to transfer
data from the file memory mapping, and required these extra buffers.
After testing it on MI300A and MI250X, this issue is not present
anymore. Thus, we are removing them for now.
DeltaFile
+9-23offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
+9-231 files

LLVM/project 6c35bdbllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 copyable_reorder.ll

[SLP] Normalize copyable operand order to group loads for better vectorization

When building operands for entries with copyable elements, non-copyable
lanes may have inconsistent operand order (e.g., some lanes have
load,add while others have add,load for commutative ops). This prevents
VLOperands::reorder() from grouping consecutive loads on one side,
degrading downstream vectorization.
Normalize in two steps during buildOperands:
1) Majority voting: swap lanes that are the exact inverse of the
   majority operand-type pattern.
2) Load preference: if the majority pattern has loads at OpIdx 1
   (strict majority), swap to put loads at OpIdx 0, enabling
   vector load + copyable patterns.

Reviewers: hiraditya, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/189181
DeltaFile
+12-26llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
+26-7llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+38-332 files

LLVM/project 500e913llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.sat.pk.ll

AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_sat_pk4_i4_i8 / amdgcn_sat_pk4_u4_u8 (#193096)
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+6-22 files

LLVM/project f46da03lldb/source/Plugins/Platform/WebAssembly PlatformWasm.cpp

[lldb] Don't enable ASLR for the Wasm runtime (#193115)

We're launching the Wasm runtime (a native host binary), not the target
being debugged. Clear flags that don't apply to the runtime process.
DeltaFile
+3-1lldb/source/Plugins/Platform/WebAssembly/PlatformWasm.cpp
+3-11 files

LLVM/project 9356e1eclang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageExtractor.cpp

Update clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
DeltaFile
+1-1clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
+1-11 files

LLVM/project 6fe6f1bllvm/include/llvm/CodeGen MachineBlockHashInfo.h, llvm/include/llvm/Passes MachinePassRegistry.def

[CodeGen] Add MachineBlockHashInfoAnalysis for the new pass manager (#193107)

This patch introduces MachineBlockHashInfoAnalysis and its corresponding
printer pass MachineBlockHashInfoPrinterPass to the new pass manager.

This allows running -passes="print<machine-block-hash>" via llc.

Can't merge before #192826, and don't want to mix test patch with
determinism fix in #192826.

This is #192911 which was accidentally merged into spr/users branch.
DeltaFile
+53-0llvm/test/CodeGen/X86/machine-block-hash.mir
+23-1llvm/lib/CodeGen/MachineBlockHashInfo.cpp
+23-0llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
+3-0llvm/include/llvm/Passes/MachinePassRegistry.def
+1-0llvm/lib/Passes/PassBuilder.cpp
+103-15 files

LLVM/project ce73ab7clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageTest.cpp

Update clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
DeltaFile
+1-1clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+1-11 files

LLVM/project 75790bfclang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel EntityPointerLevel.h EntityPointerLevelFormat.h, clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsage.h

[SSAF][UnsafeBufferUsage] Add APIs to the EntityPointerLevel module for UnsafeBufferUsage (#191333)

- UnsafeBufferUsage serialization uses EntityPointerLevel's API to
serialize EntityPointerLevels.
- Add APIs to EntityPointerLevel for creating EPLs from Decls and
incrementing EPL's pointer level.
- Improve UnsafeBufferUsage serialization error messages with a test.

---------

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
DeltaFile
+103-33clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
+29-8clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.h
+35-0clang/include/clang/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevelFormat.h
+9-19clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.cpp
+13-5clang/test/Analysis/Scalable/UnsafeBufferUsage/tu-summary-serialization.test
+2-6clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsage.h
+191-711 files not shown
+193-737 files

LLVM/project 13e18f8llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 select-logical-or-and-i1-vector.ll

[SLP] Improve cost model for i1 select-as-or/and patterns

Model `select i1 %c, i1 true, i1 %d` as `or` and
`select i1 %c, i1 %d, i1 false` as `and` in the SLP cost model, since
these are the operations the backend will lower them to. The previous
select cost overestimated the vector cost of these patterns, preventing
profitable vectorization of i1 condition chains.

Reviewers: hiraditya, RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/188572
DeltaFile
+84-34llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+20-24llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
+104-582 files

LLVM/project c758592llvm/docs/CommandGuide dsymutil.rst, llvm/test/tools/dsymutil codesign.test cmdline.test

[dsymutil] Add support for code signing dSYM bundles (#190676)

This PR adds support for code signing the dSYM bundle using the
`codesign` command line utility.
DeltaFile
+57-0llvm/tools/dsymutil/dsymutil.cpp
+15-0llvm/test/tools/dsymutil/codesign.test
+6-0llvm/tools/dsymutil/Options.td
+5-0llvm/docs/CommandGuide/dsymutil.rst
+1-0llvm/test/tools/dsymutil/cmdline.test
+84-05 files

LLVM/project 9adf869llvm/include/llvm/CodeGen MachineBlockHashInfo.h, llvm/include/llvm/Passes MachinePassRegistry.def

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+53-0llvm/test/CodeGen/X86/machine-block-hash.mir
+23-1llvm/lib/CodeGen/MachineBlockHashInfo.cpp
+23-0llvm/include/llvm/CodeGen/MachineBlockHashInfo.h
+3-0llvm/include/llvm/Passes/MachinePassRegistry.def
+1-0llvm/lib/Passes/PassBuilder.cpp
+103-15 files

LLVM/project 83dfe3dlldb/include/lldb/Target ExecutionContextScope.h

[lldb] Fix minor docstring mis-formatting (NFC) (#193106)
DeltaFile
+1-2lldb/include/lldb/Target/ExecutionContextScope.h
+1-21 files

LLVM/project 4e32f89lldb/include/lldb/Symbol Symtab.h, lldb/source/Symbol Symtab.cpp

[LLDB] Fix potential data race in Symtab initialization (#192753)

Claude pointed out to me that Symtab::FindFunctionSymbols doesn't lock
the mutex before checking m_name_indexes_computed and recomputing it. On
top of that all the initialization flags are bitfields, which makes any
unguarded concurrent accesses UB. Changing them to bools should no
longer be necessary after introducing a lock, but several of the public
methods trust that their caller holds the lock so I'm opting to remove
this footgun just in case.

rdar://174988238
DeltaFile
+105-111lldb/source/Symbol/Symtab.cpp
+7-4lldb/include/lldb/Symbol/Symtab.h
+112-1152 files