LLVM/project 16ab8e4 — llvm/lib/Transforms/Utils FixIrreducible.cpp

[FixIrreducible] Remove dead code (#239524)

The Entries set has been unused since it was introduced in #101386.
DeltaFile
+0-8llvm/lib/Transforms/Utils/FixIrreducible.cpp
+0-81 files

LLVM/project 7f2cda8 — llvm/lib/Target/LoongArch LoongArchInstrInfo.td LoongArchRegisterInfo.cpp, llvm/test/CodeGen/LoongArch ldptr-stptr-frame-offset.ll ldptr-anyext-constant-offset.ll

[LoongArch] Select LDPTR.W for any-extending i32 loads (#237883)

On LA64, an i32 load that does not require sign extension may be
represented as extloadi32 in SelectionDAG.

The existing LDPTR.W pattern only matches sextloadi32. This prevents
some constant-offset i32 loads from using LDPTR.W, resulting in
unnecessary address materialization and register-indexed loads.

Add an extloadi32 pattern for LDPTR.W, preserving the existing
zero-extension semantics and immediate-range constraints.

Assisted-by: Codex (cloud)
DeltaFile
+241-0llvm/test/CodeGen/LoongArch/ldptr-anyext-constant-offset.ll
+161-0llvm/test/CodeGen/LoongArch/ldptr-stptr-frame-offset.ll
+27-0llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
+4-0llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+433-04 files

LLVM/project bc3fb10 — mlir/lib/IR AffineMap.cpp, mlir/test/Dialect/Affine canonicalize.mlir

[mlir][affine] avoid folding affine expressions that overflow int64_t (#231085)

AffineExprConstantFolder used plain int64_t math for add/mul, so folding
something like (d0 + 1) with d0 = INT64_MAX overflowed. floordiv/ceildiv
of INT64_MIN by -1 had the same problem and hit an assert. Now we check
for overflow and just skip the fold when it happens.

Added tests for add, mul, and div overflow in canonicalize.mlir.

fixes #229706

---------

Co-authored-by: Mahmoud <mahmoud at Mahmouds-MacBook-Pro.local>
DeltaFile
+57-0mlir/test/Dialect/Affine/canonicalize.mlir
+17-2mlir/lib/IR/AffineMap.cpp
+74-22 files

LLVM/project 0198fcb — llvm/lib/Transforms/Vectorize VPlanConstruction.cpp VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize compress-idioms.ll

Fixups
DeltaFile
+15-15llvm/lib/Transforms/Vectorize/VPlan.h
+0-16llvm/test/Transforms/LoopVectorize/compress-idioms.ll
+9-0llvm/lib/Transforms/Vectorize/VPlanLowering.cpp
+4-2llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+2-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-1llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+31-376 files

LLVM/project aa6faec — flang/lib/Optimizer/Dialect FIRAttr.cpp, mlir/include/mlir/Dialect/OpenMP OpenMPOpsEnums.h

[mlir][ODS] Include headers required by generated enum declarations and definitions (#239223)

Generated enum declarations and definitions use C++ constructs that are
not declared by any header they include. They therefore relied on the
surrounding source file to include these headers first.

The enum declarations and definitions now include the headers declaring
these constructs, depending on the features of the enums.

The declarations still only forward declare `AsmParser` and
`FieldParser` to keep the generated headers cheap to include.

Similar to #236155 and #238735 but for the enum generator.

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+86-0mlir/test/mlir-tblgen/cpp-includes-enums.td
+61-7mlir/tools/mlir-tblgen/EnumsGen.cpp
+0-5mlir/include/mlir/Dialect/OpenMP/OpenMPOpsEnums.h
+0-3mlir/unittests/TableGen/EnumsGenTest.cpp
+0-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVEnums.h
+0-2flang/lib/Optimizer/Dialect/FIRAttr.cpp
+147-1912 files not shown
+147-3218 files

LLVM/project 47acf9b — llvm/test/Transforms/StructurizeCFG hoist-zerocost-multiple-rejections.ll

[AMDGPU][NFC] precommit test for StructurizeCFG hoist and replace else phi arm for non-diamond case (#239475)
DeltaFile
+1,664-0llvm/test/Transforms/StructurizeCFG/hoist-zerocost-multiple-rejections.ll
+1,664-01 files

LLVM/project 6ff7799 — llvm/include/llvm/Support Compiler.h

[Support] Use [[gnu::warn_unused]] for LLVM_ATTRIBUTE_WARN_UNUSED (NFC) (#239486)

This patch updates LLVM_ATTRIBUTE_WARN_UNUSED in Compiler.h to use the
C++11 attribute syntax [[gnu::warn_unused]] via LLVM_HAS_CPP_ATTRIBUTE
instead of __attribute__((warn_unused)).

GCC 12 and earlier reject:

    class __attribute__((warn_unused)) [[nodiscard]] Foo { ... };
    class [[nodiscard]] __attribute__((warn_unused)) Bar { ... };

This is exactly what happened in #237802.  Specifically, it added
LLVM_ATTRIBUTE_WARN_UNUSED to APInt, which already had [[nodiscard]],
and broke GCC 12 buildbots, leading to a revert in #239152:
https://lab.llvm.org/buildbot/#/builders/181/builds/53859

This patch drops the __attribute__((warn_unused)) fallback because an
older compiler like Clang 5.0 would select it and fail when a class
also has [[nodiscard]].  It's always safe to expand this optional

    [2 lines not shown]
DeltaFile
+2-2llvm/include/llvm/Support/Compiler.h
+2-21 files

LLVM/project f560e91 — mlir/lib/Conversion/SPIRVToLLVM SPIRVToLLVM.cpp, mlir/test/Conversion/SPIRVToLLVM cl-ops-to-llvm.mlir

[mlir][SPIR-V] Add SPIRVToLLVM conversion for CL.sincos (#237742)
DeltaFile
+28-1mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+23-0mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
+51-12 files

LLVM/project 6ecc5ce — mlir/include/mlir/Dialect/OpenMP OpenMPOpsEnums.h, mlir/include/mlir/Dialect/SPIRV/IR SPIRVEnums.h

[mlir][ODS] Include headers required by generated enum declarations and definitions

Generated enum declarations and definitions use C++ constructs that are
not declared by any header they include. They therefore relied on the
surrounding source file to include these headers first.

The enum declarations and definitions now include the headers declaring
these constructs, depending on the features of the enums.

The declarations still only forward declare `AsmParser` and `FieldParser`
to keep the generated headers cheap to include.

Similar to #236155 and #238735 but for the enum generator.

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+86-0mlir/test/mlir-tblgen/cpp-includes-enums.td
+61-7mlir/tools/mlir-tblgen/EnumsGen.cpp
+0-5mlir/include/mlir/Dialect/OpenMP/OpenMPOpsEnums.h
+0-3mlir/unittests/TableGen/EnumsGenTest.cpp
+0-2mlir/include/mlir/Dialect/Transform/IR/TransformAttrs.h
+0-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVEnums.h
+147-1912 files not shown
+147-3218 files

LLVM/project 577bf51 — llvm/lib/Transforms/Scalar DeadStoreElimination.cpp, llvm/test/Transforms/DeadStoreElimination noop-stores.ll

[DSE] Extend same ptr operand check to must-aliasing pointers in `storeIsNoop` (#238722)

We have observed a few DSE missed opportunities with a handful of CUDA
APIs that merely annotate a pointer with a cache hint and return it
(notably, `cuda::associate_access_property`). Thus, extend the existing
pointer equality check to must-aliasing pointers as well.

Co-authored-by: Alexander Krolik <akrolik at nvidia.com>
DeltaFile
+26-0llvm/test/Transforms/DeadStoreElimination/noop-stores.ll
+5-1llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+31-12 files

LLVM/project ee27f89 — mlir/lib/Dialect/SPIRV/Transforms UnifyAliasedResourcePass.cpp, mlir/test/Dialect/SPIRV/Transforms unify-aliased-resource.mlir

[mlir][SPIRV] Handle vector stores when unifying aliased resources (#232185)

I hit this while compiling JAX training code to WebGPU through IREE.

The alias-unification pass can select a smaller vector resource, but its
store conversion currently only handles scalars. Handle vector stores by
splitting them into stores of the canonical vector type, preserving
memory-access flags and alignment.

---------

Signed-off-by: anutosh491 <andersonbhat491 at gmail.com>
DeltaFile
+169-0mlir/test/Dialect/SPIRV/Transforms/unify-aliased-resource.mlir
+67-6mlir/lib/Dialect/SPIRV/Transforms/UnifyAliasedResourcePass.cpp
+236-62 files

LLVM/project 5420fce — mlir/lib/Conversion/SPIRVToLLVM SPIRVToLLVM.cpp, mlir/test/Conversion/SPIRVToLLVM cl-ops-to-llvm.mlir gl-ops-to-llvm.mlir

[mlir][SPIR-V] Add SPIRVToLLVM conversion for CL.ldexp and GL.Ldexp (#237745)

Vector exponents are not covered since llvm.intr.ldexp accepts only a
scalar integer exponent
DeltaFile
+11-0mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
+7-0mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
+2-0mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+20-03 files

LLVM/project eb85651 — llvm/lib/Target/RISCV RISCVInstrInfoV.td, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.ll

[RISCV] Set DestEEW = EEW1 for VLM_V (#239498)

Assisted-by: Claude
DeltaFile
+14-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+15-12 files

LLVM/project ebc8a1b — llvm/lib/ObjCopy/MachO MachOReader.cpp, llvm/test/tools/llvm-objcopy/MachO arm64-relocs.s

[llvm-objcopy][MachO] Handle ARM64_RELOC_ADDEND for CPU_TYPE_ARM64_32 (#238296)

`ARM64_RELOC_ADDEND` was only handled for arm64, not arm64_32. On
arm64_32 the addend was read as a section index, so `llvm-objcopy` could
crash or write a wrong addend. Handle it for arm64_32 too, and add an
arm64_32 case to `arm64-relocs.s`.

Fixes #238273
I wrote the code and verified everything myself. Claude Code helped me
identify the issue.

Assisted-by: Claude Code
DeltaFile
+4-2llvm/lib/ObjCopy/MachO/MachOReader.cpp
+5-0llvm/test/tools/llvm-objcopy/MachO/arm64-relocs.s
+9-22 files

LLVM/project db52992 — llvm/include/llvm/IR IRBuilder.h

Reapply [IRBuilder] Assert correct offset width for CreatePtrAdd (#239262)

Reapply #238806 without changes after fixing more CreatePtrAdd uses.

-----

Assert that the offset width matches the pointer index width. This is
supposed to become an IR well-formedness requirement when we switch to
ptradd, so we should start asserting it in the builder now.

Helpers like CreatePtrAddWith(Unsigned|Signed)Offset and
CreatePtrAddWith[SZ]ExtOrTrunc can be used to more conveniently create
ptradds with appropriately sized offsets.

Problematic uses of CreatePtrAdd were already adjusted in #238347.
DeltaFile
+4-2llvm/include/llvm/IR/IRBuilder.h
+4-21 files

LLVM/project f6f7322 — llvm/lib/Transforms/Instrumentation MemorySanitizer.cpp

[MemorySanitizer] Consistently use unsigned offsets (NFC) (#239193)

Helper functions for getting origin/shadow etc accepted a mix of int and
unsigned. I believe all of these offsets are non-negative, so use
unsigned everywhere to avoid confusion.
DeltaFile
+13-12llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+13-121 files

LLVM/project e0d0b97 — llvm/test/CodeGen/RISCV rvp-simd-32.ll rvp-simd-64.ll

[RISCV][P-ext] Remove line breaks from argument list of function definition in tests. NFC (#238881)

These line breaks cause the update_llc_test_checks.py script to put the
checks in the middle of the argument list.
DeltaFile
+23-44llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+8-16llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+31-602 files

LLVM/project 4c22a9f — mlir/include/mlir/Dialect/AMDGPU/IR AMDGPUDialectDecl.h, mlir/include/mlir/Dialect/Affine/IR AffineDialect.h

[mlir][ODS] Include headers required by generated dialect declarations and definitions (#239215)

Generated dialect declarations and definitions use C++ constructs that
are not declared by any header they include. They therefore relied on
the surrounding source file to include these headers first.

The dialect declarations now include the header declaring the dialect
base class, and the headers declaring `StringAttr` and `Operation` if
the dialect has discardable attributes. The dialect definitions include
`MLIRContext.h` if they load dependent dialects.

Similar to #236155 and #238735 but for the dialect generator.

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+40-0mlir/test/mlir-tblgen/cpp-includes-dialect.td
+20-0mlir/tools/mlir-tblgen/DialectGen.cpp
+0-3mlir/include/mlir/Dialect/LLVMIR/ROCDLDialectDecl.h
+0-2mlir/include/mlir/Dialect/Arith/IR/ArithDialect.h
+0-2mlir/include/mlir/Dialect/Affine/IR/AffineDialect.h
+0-2mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUDialectDecl.h
+60-952 files not shown
+61-7658 files

LLVM/project f133b97 — utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[Bazel] Fixes d1ec07e (#239493)

This fixes d1ec07e0431412a667fecd5c2708f3606b6799a4 (#238966).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=d1ec07e0431412a667fecd5c2708f3606b6799a4

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+2-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+2-01 files

LLVM/project 5c9aa46 — llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll amdgcn.bitcast.832bit.ll

[spr] update

Created using spr 2.0.0-beta.2
DeltaFile
+89,147-91,827llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,378-26,402llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,311-9,381llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,998-9,209llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+8,016-8,194llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+7,335-7,432llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+148,185-152,44513,886 files not shown
+699,970-465,39813,892 files

LLVM/project 47d998a — llvm/lib/Target/LoongArch LoongArchRegisterInfo.cpp, llvm/test/CodeGen/LoongArch/lasx xvldrepl-frame-index.ll

[LoongArch] Fix misaligned frame-index offset for vldrepl.{h,w,d}

eliminateFrameIndex did not check that the final offset is a multiple of
the access size for [X]VLDREPL_{H,W,D}, so a byte-aligned stack object
could produce an unencodable immediate. Materialize the address in a
scratch register in that case, as is already done for [X]VSTELM_*.

Assisted-by: LLM
DeltaFile
+12-0llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
+6-3llvm/test/CodeGen/LoongArch/lsx/vldrepl-frame-index.ll
+6-3llvm/test/CodeGen/LoongArch/lasx/xvldrepl-frame-index.ll
+24-63 files

LLVM/project e641369 — llvm/test/CodeGen/LoongArch/lasx xvldrepl-frame-index.ll, llvm/test/CodeGen/LoongArch/lsx vldrepl-frame-index.ll

[LoongArch] Pre-commit tests for misaligned frame-index offset on vldrepl

Assisted-by: LLM
DeltaFile
+76-0llvm/test/CodeGen/LoongArch/lasx/xvldrepl-frame-index.ll
+76-0llvm/test/CodeGen/LoongArch/lsx/vldrepl-frame-index.ll
+152-02 files

LLVM/project fa98dee — llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/X86 tl-libcalls-module-flags.ll

[TargetLowering] Use DAG.getLibcalls() in expandMultipleResultFPLibCall (#239150)

`getLibcallLoweringInfo` and the helper `getLibcallImplCallingConv`
access the `Libcalls` from TargetLoweringBase, which is constructed
without the LLVM Module being available. This affects the libcalls
available through module flags like `long-double-type`. SelectionDAG
already consults the module flags, so missing it here can lead
inconsistencies in which libcalls are available.

Fixes: #239145
DeltaFile
+34-0llvm/test/CodeGen/X86/tl-libcalls-module-flags.ll
+3-2llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+37-22 files

LLVM/project 8a8ab64 — offload/include device.h, offload/libompaccsupport device.cpp

[Offload][Omp] Decouple RecordReplay from PluginInterface (#236814)

After we broke the `GenericKernelyTy` dependence in the RecordReplay
(RR), most of it became independent from the `PluginInterface`.

This PR moves the RR logic from the `PluginInterface` to libomptarget
and changes RR to use OpenMP errors and liboffload for data transfers.
Still, the _VirtualAddress_ interfaces are not available through the
liboffload API so we use them through temporary helpers.

I purposely didn't move the RR source files from the plugin directory so
the changes in this PR would easier to review. The code will be
reorganized in a follow-up NFC PR.

It was verified by @kevinsala on NVIDIA and AMD gpus.

Assisted by Claude

---------

Co-authored-by: Kevin Sala <salapenades1 at llnl.gov>
DeltaFile
+92-18offload/libompaccsupport/device.cpp
+67-42offload/plugins-nextgen/common/src/RecordReplay.cpp
+0-37offload/plugins-nextgen/common/src/PluginInterface.cpp
+0-34offload/plugins-nextgen/common/include/PluginInterface.h
+11-11offload/plugins-nextgen/common/include/RecordReplay.h
+22-0offload/include/device.h
+192-1424 files not shown
+217-14910 files

LLVM/project 5c81f69 — llvm/include/llvm/Transforms/IPO Attributor.h, llvm/lib/Transforms/IPO Attributor.cpp

Attributor: Only check once if time trace scopes are recorded

Every initialization and update of an abstract attribute opened a
TimeTraceScope, which checks if the time profiler is enabled out of line.
Check it once per Attributor instead. NFC.

CTMark instructions:u with -attributor-enable=light changes by O3 -0.02%,
ThinLTO -0.03%. The attributor-light pass itself is 0.3-0.8% faster
(callgrind), and 0.3-1.9% faster with the other pending Attributor
compile-time changes applied.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+12-4llvm/include/llvm/Transforms/IPO/Attributor.h
+8-4llvm/lib/Transforms/IPO/Attributor.cpp
+20-82 files

LLVM/project c408850 — llvm/test/CodeGen/AArch64 arm64-dagcombiner-load-slicing.ll scalarized-store.ll

[AArch64] Regnerate arm64-dagcombiner-load-slicing.ll and add expended store tests. NFC (#239509)
DeltaFile
+900-0llvm/test/CodeGen/AArch64/scalarized-store.ll
+33-21llvm/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll
+933-212 files

LLVM/project f947707 — llvm/test/CodeGen/RISCV idiv_large.ll bitint-fp-conv-200.ll, llvm/test/CodeGen/RISCV/GlobalISel fp128.ll

[RISCV] Update the getCSRCost value
DeltaFile
+2,637-2,485llvm/test/CodeGen/RISCV/fpclamptosat.ll
+1,268-1,128llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
+804-803llvm/test/CodeGen/RISCV/idiv_large.ll
+670-670llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
+659-507llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+516-480llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
+6,554-6,07379 files not shown
+10,996-10,89485 files

LLVM/project eaaa209 — llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-stackrestore.mir

[AMDGPU][GISel] Add RegBankLegalize rule for G_STACKRESTORE
DeltaFile
+21-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-stackrestore.mir
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+23-42 files

LLVM/project 456b470 — llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-stackrestore.mir

pre-commit failing test cases
DeltaFile
+41-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-stackrestore.mir
+41-01 files

LLVM/project 2c87de2 — clang/lib/CIR/Dialect/Transforms CIRABIClassifier.cpp, clang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.h CIRABIRewriteContext.cpp

[CIR][AMDGPU] Lower Indirect arguments and sret returns in addrspace(5)
DeltaFile
+62-34clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+93-0clang/test/CIR/Transforms/abi-lowering/amdgpu-indirect.cir
+0-22clang/test/CIR/Transforms/abi-lowering/amdgpu-indirect-nyi.cir
+6-5clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
+0-3clang/lib/CIR/Dialect/Transforms/CIRABIClassifier.cpp
+161-645 files