LLVM/project c3a50a0 — llvm/include/llvm/MC MCInstPrinter.h, llvm/test/TableGen RegClassByHwModeAlias.td RegClassByHwModeErrors.td

by Alex Richardson on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+48-0llvm/test/TableGen/RegClassByHwModeAlias.td
+33-0llvm/test/TableGen/RegClassByHwModeErrors.td
+19-5llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+12-11llvm/include/llvm/MC/MCInstPrinter.h
+13-9llvm/utils/TableGen/AsmWriterEmitter.cpp
+10-6llvm/utils/TableGen/Common/InfoByHwMode.cpp
+135-315 files not shown
+159-3811 files

LLVM/project 22b3541 — llvm/include/llvm/MC MCInstPrinter.h, llvm/test/TableGen RegClassByHwModeAlias.td RegClassByHwModeErrors.td

by Alex Richardson on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+48-0llvm/test/TableGen/RegClassByHwModeAlias.td
+33-0llvm/test/TableGen/RegClassByHwModeErrors.td
+19-5llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+12-11llvm/include/llvm/MC/MCInstPrinter.h
+13-9llvm/utils/TableGen/AsmWriterEmitter.cpp
+10-6llvm/utils/TableGen/Common/InfoByHwMode.cpp
+135-312 files not shown
+147-338 files

LLVM/project 86c5539 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/Analysis/CostModel/RISCV vp-intrinsics.ll

by Luke Lau via GitHub on ⎇
[IR][RISCV] Remove @llvm.experimental.vp.splat (#171084)

@llvm.experimental.vp.splat was originally added in #98731 in order to
prevent VL toggles when optimizing a zero strided load to a scalar load
+ splat on RISC-V: #101329

However, the need to explicitly set the VL operand has been superseded
by RISCVVLOptimizer which can infer this automatically based on the
splat's users, and the use of the vp.splat intrinsic was removed in
#170543.

Now that there are no users of @llvm.experimental.vp.splat internal to
LLVM and it's unlikely we will need it in future due to
RISCVVLOptimizer, this patch removes the intrinsic. I couldn't find any
publicly available out-of-tree users of the intrinsic with a quick
search on GitHub.
DeltaFile
+0-744llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
+0-636llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
+0-151llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
+2-131llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+0-107llvm/test/CodeGen/RISCV/rvv/vp-splat-mask.ll
+5-53llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+7-1,82210 files not shown
+14-1,95316 files

LLVM/project 6f4fe69 — llvm/include/llvm/MC MCInstPrinter.h, llvm/lib/MC MCInstPrinter.cpp

by Alex Richardson on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+48-0llvm/test/TableGen/RegClassByHwModeAlias.td
+12-11llvm/include/llvm/MC/MCInstPrinter.h
+13-9llvm/utils/TableGen/AsmWriterEmitter.cpp
+8-1llvm/lib/MC/MCInstPrinter.cpp
+81-214 files

LLVM/project 48d5d8f — clang/lib/AST/ByteCode Pointer.cpp Interp.h, llvm/test/Transforms/LoopUnroll/RISCV vector.ll

by Alex Richardson on ⎇
rebase

Created using spr 1.3.8-beta.1
DeltaFile
+157-136llvm/test/Transforms/LowerTypeTests/import.ll
+129-7llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
+67-57clang/lib/AST/ByteCode/Pointer.cpp
+31-31clang/lib/AST/ByteCode/Interp.h
+38-20clang/lib/AST/ByteCode/Descriptor.cpp
+19-20clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+441-27124 files not shown
+605-34630 files

LLVM/project 0893fdb — clang/lib/AST/ByteCode Pointer.cpp Interp.h, llvm/test/Transforms/LoopUnroll/RISCV vector.ll

by Alexander Richardson via Alex Richardson on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+157-136llvm/test/Transforms/LowerTypeTests/import.ll
+129-7llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
+67-57clang/lib/AST/ByteCode/Pointer.cpp
+31-31clang/lib/AST/ByteCode/Interp.h
+38-20clang/lib/AST/ByteCode/Descriptor.cpp
+19-20clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+441-27124 files not shown
+605-34630 files

LLVM/project 5079260 — llvm/test/TableGen RegClassByHwModeErrors.td RegClassByHwMode.td, llvm/test/TableGen/Common RegClassByHwModeCommon.td

by Alexander Richardson via GitHub on ⎇
[TableGen] Slightly improve error location for a fatal error

I was hitting this error and the error location was pointing to the
register class definition instead of the incorrect InstAlias. Pass in
the InstAlias location to make it easier to debug.

Happens with `def : InstAlias<"foo", (Inst X0)>`, where `Inst` takes
a RegClassByHwMode operand that is not necessarily satisfied by
register X0. Similar problem with the CompressPat backend.

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/170790
DeltaFile
+88-0llvm/test/TableGen/RegClassByHwModeErrors.td
+7-57llvm/test/TableGen/RegClassByHwMode.td
+44-0llvm/test/TableGen/Common/RegClassByHwModeCommon.td
+12-9llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
+8-6llvm/utils/TableGen/CompressInstEmitter.cpp
+10-2llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+169-743 files not shown
+175-789 files

LLVM/project 9baf76a — llvm/test/CodeGen/Mips setcc-se.ll micromips-pseudo-mtlohi-expand.ll, llvm/test/CodeGen/Mips/llvm-ir load.ll store.ll

by Alexander Richardson via GitHub on ⎇
[MCAsmStreamer] Print register names in --show-inst mode

Passing the context to `Inst.dump_pretty()` allows printing symbolic
register names instead of `<MCOperand Reg:1234>` in the output.
I plan to use this in a future RVY test cases where we have register
class with the same name in assembly syntax, but different underlying
register enum values. Printing the name of the enum value makes it
easier to test that we selected the correct register.

Reviewed By: lenary

Pull Request: https://github.com/llvm/llvm-project/pull/171252
DeltaFile
+795-795llvm/test/CodeGen/Mips/llvm-ir/load.ll
+450-450llvm/test/CodeGen/Mips/llvm-ir/store.ll
+157-157llvm/test/CodeGen/Mips/setcc-se.ll
+148-148llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+66-66llvm/test/MC/Lanai/memory.s
+40-40llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
+1,656-1,6565 files not shown
+1,702-1,70211 files

LLVM/project b1b3629 — clang/include/clang/Basic Builtins.def, clang/lib/AST ASTContext.cpp

by ranapratap55 on ⎇
[AMDGPU] Removal of language sensitive option for _Float16 and half( 'e') handling
DeltaFile
+2-6clang/lib/AST/ASTContext.cpp
+0-1clang/include/clang/Basic/Builtins.def
+2-72 files

LLVM/project 773a6a9 — clang/lib/AST/ByteCode Pointer.cpp Interp.h

by Timm Bäder on ⎇
Revert "[clang][bytecode] Allocate InitMaps via Program/InterpState allocators (#170272)"

This reverts commit 8fe38c4c9c71c7a86ecdba476ee5bae4c02c0dfe.

This breaks the clang-armv7-2stage build bot:
https://lab.llvm.org/buildbot/#/builders/79/builds/2531
DeltaFile
+67-57clang/lib/AST/ByteCode/Pointer.cpp
+31-31clang/lib/AST/ByteCode/Interp.h
+38-20clang/lib/AST/ByteCode/Descriptor.cpp
+19-20clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+6-26clang/lib/AST/ByteCode/Descriptor.h
+9-11clang/lib/AST/ByteCode/Pointer.h
+170-1656 files not shown
+188-18512 files

LLVM/project 0df8306 — clang/include/clang/Basic BuiltinsNVPTX.td OffloadArch.h, clang/lib/Basic Cuda.cpp OffloadArch.cpp

by Rajat Bajpai via GitHub on ⎇
[Clang][CUDA] Add support for SM_88, SM_110, and SM_110a architectures (#170258)

This patch adds support for new GPU architectures introduced in CUDA
13.0 in Clang:
- SM_88: Ampere architecture variant
- SM_110/SM_110a: Blackwell architecture variants

Additionally, this patch deprecates SM_101/SM_101a support for CUDA 13.0
and later versions. The SM_101 architecture is superseded by SM_110 and
is no longer supported by CUDA 13.0+ toolchain components.
DeltaFile
+7-3clang/include/clang/Basic/BuiltinsNVPTX.td
+8-0clang/lib/Basic/Cuda.cpp
+6-0clang/lib/Basic/Targets/NVPTX.cpp
+3-0clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+3-0clang/include/clang/Basic/OffloadArch.h
+3-0clang/lib/Basic/OffloadArch.cpp
+30-32 files not shown
+34-38 files

LLVM/project a899a04 — clang/include/clang/Basic BuiltinsAMDGPU.def

by ranapratap55 on ⎇
[AMDGPU] Modifies builtin def to take _Float16('x') for both HIP/C++ and for OpenCL
DeltaFile
+17-17clang/include/clang/Basic/BuiltinsAMDGPU.def
+17-171 files

LLVM/project 93c7ad1 — llvm/lib/Transforms/IPO LowerTypeTests.cpp, llvm/test/Transforms/LowerTypeTests import.ll

by Mircea Trofin via GitHub on ⎇
[LTT] Bias branch weights as "expected" when lowering type tests with conditional (#170752)

We expect the type test to succeed.
DeltaFile
+13-10llvm/test/Transforms/LowerTypeTests/import.ll
+5-1llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+0-2llvm/utils/profcheck-xfail.txt
+18-133 files

LLVM/project 4727ca7 — clang/lib/CodeGen CGExpr.cpp CodeGenFunction.h, clang/test/CodeGen attr-counted-by.c attr-counted-by-for-pointers.c

by Bill Wendling on ⎇
[Clang][counted_by] Correct signed counted_by values

If the 'counted_by' value is signed, we will incorrectly allow accesses
when the value is negative. This has obvious bad effects as it will
allow accessing a huge swath of unallocated memory.

Also clarify and rearrange the parameters to make them more
perspicuous.

Fixes: 170987
DeltaFile
+309-274clang/test/CodeGen/attr-counted-by.c
+67-57clang/test/CodeGen/attr-counted-by-for-pointers.c
+61-36clang/lib/CodeGen/CGExpr.cpp
+35-36clang/test/DebugInfo/Generic/bounds-checking-debuginfo.c
+9-8clang/lib/CodeGen/CodeGenFunction.h
+481-4115 files

LLVM/project 82a1a33 — llvm/test/CodeGen/AArch64 arm64-homogeneous-prolog-epilog-tail-call.mir

by Mircea Trofin on ⎇
Remove cleanup of incorrect output in test dir
DeltaFile
+0-1llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir
+0-11 files

LLVM/project ce76c39 — llvm/test/CodeGen/AArch64 arm64-homogeneous-prolog-epilog-tail-call.mir

by Mircea Trofin via GitHub on ⎇
Fix test outputting to test dir (#171255)

The test introduced in #171118 has `llc` inadvertently producing an
output into the same dir as the test file itself. Most build bots don't
clean up the local git repo, which is assumed to not be written by build
+ test, and patch on top (for build performance reasons), which means
the produced output from the aforementioned PR is treated as a test from
here onwards, by all bots. Since it's missing `RUN` lines, we get
errors, for example
 https://lab.llvm.org/buildbot/#/builders/108/builds/20674

This patch fixes the `llc` line and also removes the `.s`. This avoids
all bot maintainers go restart their bots. Then, the cleanup is removed
in #171256.
DeltaFile
+2-1llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir
+2-11 files

LLVM/project ab41b50 — llvm/test/CodeGen/Mips setcc-se.ll, llvm/test/CodeGen/Mips/llvm-ir load.ll store.ll

by Alex Richardson on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+795-795llvm/test/CodeGen/Mips/llvm-ir/load.ll
+450-450llvm/test/CodeGen/Mips/llvm-ir/store.ll
+157-157llvm/test/CodeGen/Mips/setcc-se.ll
+148-148llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+66-66llvm/test/MC/Lanai/memory.s
+121-0llvm/test/TableGen/RegClassByHwModeErrors.td
+1,737-1,61617 files not shown
+1,943-1,79223 files

LLVM/project 0835d70 — llvm/test/CodeGen/Mips setcc-se.ll, llvm/test/CodeGen/Mips/llvm-ir load.ll store.ll

by Alex Richardson on ⎇
[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+795-795llvm/test/CodeGen/Mips/llvm-ir/load.ll
+450-450llvm/test/CodeGen/Mips/llvm-ir/store.ll
+157-157llvm/test/CodeGen/Mips/setcc-se.ll
+148-148llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+66-66llvm/test/MC/Lanai/memory.s
+88-0llvm/test/TableGen/RegClassByHwModeErrors.td
+1,704-1,61614 files not shown
+1,877-1,78020 files

LLVM/project ba3208e — llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

by Owen Anderson via GitHub on ⎇
[LLVM/CodeGen] Use the correct address space when building structor tables. (#171247)

No in-tree target exercises this, but it's needed for CHERI, and I
believe its correctness is verifiable by inspection.

Co-authored-by: Alex Richardson <alexrichardson at google.com>
DeltaFile
+1-1llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+1-11 files

LLVM/project a0b6638 — llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/test/Transforms/LoopUnroll/RISCV vector.ll

by Pengcheng Wang via GitHub on ⎇
[RISCV] Don't unroll vectorized loops with vector operands (#171089)

We have disabled unrolling for vectorized loops in #151525 but this
PR only checked the instruction type.

For some loops, there is no instruction with vector type but they
are still vector operations (just like the memset zero test in the
precommit test).

Here we check the operands as well to cover these cases.
DeltaFile
+17-98llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
+4-1llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+21-992 files

LLVM/project abe7ec4 — clang/test/Headers __clang_hip_math.hip, llvm/lib/Transforms/Scalar StraightLineStrengthReduce.cpp

by Alex Richardson on ⎇
fix missing newline

Created using spr 1.3.8-beta.1
DeltaFile
+2,027-185llvm/test/CodeGen/X86/shift-i512.ll
+1,563-413llvm/test/CodeGen/X86/bitcnt-big-integer.ll
+825-755clang/test/Headers/__clang_hip_math.hip
+883-273llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
+2-668llvm/test/CodeGen/RISCV/rv32p.ll
+323-320llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
+5,623-2,614984 files not shown
+18,739-13,559990 files

LLVM/project 780b0fe — clang/test/Headers __clang_hip_math.hip, llvm/lib/Transforms/Scalar StraightLineStrengthReduce.cpp

by Alex Richardson on ⎇
[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+2,027-185llvm/test/CodeGen/X86/shift-i512.ll
+1,563-413llvm/test/CodeGen/X86/bitcnt-big-integer.ll
+825-755clang/test/Headers/__clang_hip_math.hip
+883-273llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
+2-668llvm/test/CodeGen/RISCV/rv32p.ll
+323-320llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
+5,623-2,614983 files not shown
+18,734-13,554989 files

LLVM/project e5a1821 — clang/include/clang/Basic OpenCLExtensions.def, clang/test/SemaOpenCL extension-version.cl

by Wenju He via GitHub on ⎇
[OpenCL] Add missing Intel extensions to OpenCLExtensions.def (#169875)

Add following extensions:
cl_intel_bfloat16_conversion
cl_intel_subgroup_buffer_prefetch
cl_intel_subgroup_local_block_io
cl_intel_subgroups_char
cl_intel_subgroups_long

This allows targets to expose these extensions via
getSupportedOpenCLOpts and ensures macros are defined when enabled.
DeltaFile
+36-0clang/test/SemaOpenCL/extension-version.cl
+5-0clang/include/clang/Basic/OpenCLExtensions.def
+41-02 files

LLVM/project a859ff9 — llvm/test/CodeGen/AMDGPU maximumnum.bf16.ll minimumnum.bf16.ll, llvm/test/CodeGen/X86 wide-scalar-shift-by-byte-multiple-legalization.ll shift-i512.ll

by Jianhui Li on ⎇
Merge branch 'main' into broadcastpropagation
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,857-10,952llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,840-10,957llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+4,091-0llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
+1,541-1,541llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+2,027-185llvm/test/CodeGen/X86/shift-i512.ll
+42,878-44,4082,285 files not shown
+129,195-93,1652,291 files

LLVM/project bf8558e — mlir/include/mlir/Dialect/XeGPU/IR XeGPUAttrs.td, mlir/lib/Dialect/XeGPU/IR XeGPUDialect.cpp

by Jianhui Li on ⎇
add setUnitDimData/Layout interface and refactor
DeltaFile
+125-0mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+45-29mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+20-0mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+2-6mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+192-354 files

LLVM/project 621a15d — llvm/test/CodeGen/Mips setcc-se.ll micromips-pseudo-mtlohi-expand.ll, llvm/test/CodeGen/Mips/llvm-ir load.ll store.ll

by Alex Richardson on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+795-795llvm/test/CodeGen/Mips/llvm-ir/load.ll
+450-450llvm/test/CodeGen/Mips/llvm-ir/store.ll
+157-157llvm/test/CodeGen/Mips/setcc-se.ll
+148-148llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+66-66llvm/test/MC/Lanai/memory.s
+40-40llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
+1,656-1,6565 files not shown
+1,702-1,70211 files

LLVM/project 893479a — llvm/test/Transforms/LoopUnroll/RISCV vector.ll

by Pengcheng Wang on ⎇
[RISCV] Precommit test for unrolling loops with vector operands
DeltaFile
+210-7llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
+210-71 files

LLVM/project f715356 — llvm/lib/Transforms/IPO LowerTypeTests.cpp, llvm/test/Transforms/LowerTypeTests import.ll

by Mircea Trofin on ⎇
[LTT] Add `unknown` branch weights when lowering type tests with conditional
DeltaFile
+13-10llvm/test/Transforms/LowerTypeTests/import.ll
+5-1llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+0-2llvm/utils/profcheck-xfail.txt
+18-133 files

LLVM/project f2ddc7b — llvm/test/Transforms/LowerTypeTests import.ll

by Mircea Trofin via GitHub on ⎇
[NFC] Run UTC --check-globals on LowerTypeTests/import.ll (#170755)
DeltaFile
+154-136llvm/test/Transforms/LowerTypeTests/import.ll
+154-1361 files

LLVM/project 898963b — llvm/lib/Target/AArch64 AArch64LowerHomogeneousPrologEpilog.cpp, llvm/test/CodeGen/AArch64 arm64-homogeneous-prolog-epilog-tail-call.mir

by Zhaoxuan Jiang via GitHub on ⎇
[AArch64] Fix missing register definitions in homogeneous epilog lowering (#171118)

The lowering for HOM_Epilog did not transfer explicit register defs from
the pseudo-instruction to the generated helper calls. MachineVerifier
would complain if a following tail call uses one of the restored CSRs.
This scenario occurs in code generated by the Swift compiler, where X20
is used to pass swiftself.

This patch fixes the issue by adding the missing defs back to the helper
call as implicit defs.
DeltaFile
+28-0llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir
+17-10llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
+45-102 files