LLVM/project e336342llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp SIDefines.h

Round-trip VGPR-memory pointers through flat via a synthetic aperture
DeltaFile
+164-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-addrspacecast.ll
+27-7llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+25-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-0llvm/lib/Target/AMDGPU/SIDefines.h
+9-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+5-0llvm/docs/AMDGPUUsage.rst
+242-113 files not shown
+252-119 files

LLVM/project 61a8d42libcxx/test/benchmarks/locale num_put.bench.cpp num_get.bench.cpp, libcxx/test/benchmarks/text/localization num_put.bench.cpp num_get.bench.cpp

[libc++] Optimize std::swap of locales (#209760)

Currently we copy construct `locale`s whenever we swap, which is quite
expensive for locales since that does atomic increments and decrements.
We can just swap the pointers instead.
DeltaFile
+0-82libcxx/test/benchmarks/locale/ctype.bench.cpp
+82-0libcxx/test/benchmarks/text/localization/ctype.bench.cpp
+0-46libcxx/test/benchmarks/locale/num_get.bench.cpp
+46-0libcxx/test/benchmarks/text/localization/num_get.bench.cpp
+0-39libcxx/test/benchmarks/locale/num_put.bench.cpp
+39-0libcxx/test/benchmarks/text/localization/num_put.bench.cpp
+167-1674 files not shown
+240-16710 files

LLVM/project f661a4bopenmp/device/include State.h, openmp/device/src Reduction.cpp State.cpp

[offload] Add global addrspace qualifier to KLE and member pointers

Claude assisted with this patch.
DeltaFile
+5-5openmp/device/src/State.cpp
+2-1openmp/device/src/Reduction.cpp
+1-1openmp/device/include/State.h
+8-73 files

LLVM/project ee56bcb.github/workflows/upload-release-artifact action.yml

Move checkout and gate it on upload
DeltaFile
+11-10.github/workflows/upload-release-artifact/action.yml
+11-101 files

LLVM/project 4d34976clang/lib/Driver/ToolChains Clang.cpp, clang/test/Driver openmp-target-fast-flag.c

Reland "Revert "[OpenMP] target-fast implies teams/threads oversubscription"" (#213911)

Reverts llvm/llvm-project#213769
DeltaFile
+15-7clang/test/Driver/openmp-target-fast-flag.c
+2-2clang/lib/Driver/ToolChains/Clang.cpp
+17-92 files

LLVM/project 08bf9b0.github/workflows/upload-release-artifact action.yml

Fix indnetation
DeltaFile
+8-8.github/workflows/upload-release-artifact/action.yml
+8-81 files

LLVM/project 082d7bellvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp SIInstructions.td

Set up M0 for VGPR-memory accesses in finalizeLowering instead of a separate pass
DeltaFile
+0-110llvm/lib/Target/AMDGPU/AMDGPUAssignIdxToM0.cpp
+34-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-5llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+0-10llvm/lib/Target/AMDGPU/AMDGPU.h
+0-9llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+7-2llvm/lib/Target/AMDGPU/SIInstructions.td
+47-1364 files not shown
+47-14610 files

LLVM/project dcb3518llvm/lib/Target/AMDGPU AMDGPUAssignIdxToM0.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-unsupported.ll as-vgpr-optnone.ll

Address review: subarch triples, required pass mixin, legalizer predicates, redundant VALU
DeltaFile
+10-11llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+4-4llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-gpr-idx-mode.ll
+3-2llvm/lib/Target/AMDGPU/AMDGPUAssignIdxToM0.cpp
+2-2llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-unsupported.ll
+2-2llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-optnone.ll
+2-2llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-inttoptr.ll
+23-236 files not shown
+34-3512 files

LLVM/project 9df247dllvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-copy.ll

Explain the undef operands of the VGPR-memory indexed moves
DeltaFile
+224-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-copy.ll
+13-1llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+237-12 files

LLVM/project 0b8b9f4llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-divergent.ll as-vgpr-gpr-idx-mode.ll

Pin VGPR-memory indexed accesses to EXEC and mark them divergent
DeltaFile
+14-14llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-gpr-idx-mode.ll
+7-8llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-divergent.ll
+13-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+5-5llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+39-274 files

LLVM/project 98e5e68llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp AMDGPUMCInstLower.cpp

Give the VGPR-memory moves their own opcodes
DeltaFile
+10-14llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+15-0llvm/lib/Target/AMDGPU/SIInstructions.td
+7-0llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+2-1llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+34-154 files

LLVM/project 084a4f8llvm/lib/Target/AMDGPU AMDGPUAssignIdxToM0.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-gpr-idx-mode.ll

Stop miscompiling VGPR-memory accesses on subtargets without movrel
DeltaFile
+101-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-gpr-idx-mode.ll
+42-8llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+9-12llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5-8llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+4-3llvm/lib/Target/AMDGPU/SIInstructions.td
+4-0llvm/lib/Target/AMDGPU/AMDGPUAssignIdxToM0.cpp
+165-316 files

LLVM/project 205a344llvm/lib/Target/AMDGPU AMDGPUAssignIdxToM0.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-divergent.ll as-vgpr-gpr-idx-mode.ll

Declare in TableGen that the VGPR-memory pseudos write M0
DeltaFile
+14-14llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-gpr-idx-mode.ll
+0-24llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+8-7llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-divergent.ll
+0-13llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+7-6llvm/lib/Target/AMDGPU/SIInstructions.td
+3-8llvm/lib/Target/AMDGPU/AMDGPUAssignIdxToM0.cpp
+32-721 files not shown
+32-737 files

LLVM/project b68e6f9llvm/lib/Target/AMDGPU AMDGPUAssignIdxToM0.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-optnone.ll

Run AMDGPUAssignIdxToM0 for optnone functions
DeltaFile
+43-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-optnone.ll
+3-2llvm/lib/Target/AMDGPU/AMDGPUAssignIdxToM0.cpp
+46-22 files

LLVM/project 34a70f8llvm/lib/Target/AMDGPU AMDGPUAssignIdxToM0.cpp

Do not set a kill flag on the M0 index copy in AMDGPUAssignIdxToM0
DeltaFile
+2-1llvm/lib/Target/AMDGPU/AMDGPUAssignIdxToM0.cpp
+2-11 files

LLVM/project 999e93cllvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-index-demanded-bits.ll

Simplify demanded bits
DeltaFile
+51-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-index-demanded-bits.ll
+23-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-2llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+75-23 files

LLVM/project 2090b09llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp

Mask the VGPR-memory movrel base into the addressable range
DeltaFile
+10-7llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+10-71 files

LLVM/project 1ae9f69llvm/lib/Target/AMDGPU SIInstrInfo.cpp

Waterfall any non-SGPR VGPR-memory index, not just virtual
DeltaFile
+4-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+4-21 files

LLVM/project 0456d7ellvm/lib/Target/AMDGPU SIInstructions.td AMDGPUAssignIdxToM0.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-divergent.ll as-vgpr-basic.ll

Lower loads and stores for address space 13
DeltaFile
+461-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-copy.ll
+384-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-basic.ll
+130-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-divergent.ll
+117-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+108-0llvm/lib/Target/AMDGPU/AMDGPUAssignIdxToM0.cpp
+100-0llvm/lib/Target/AMDGPU/SIInstructions.td
+1,300-024 files not shown
+1,898-2430 files

LLVM/project 8aa39c9llvm/lib/Target/AMDGPU AMDGPU.h, llvm/test/CodeGen/AMDGPU attributor-noalias-addrspace.ll attributor-flatscratchinit-undefined-behavior.ll

Classify the VGPR address space correctly and give it alias rules
DeltaFile
+39-0llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
+18-11llvm/lib/Target/AMDGPU/AMDGPU.h
+10-10llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
+4-4llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
+2-2llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
+2-2llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
+75-292 files not shown
+77-318 files

LLVM/project 0343527mlir/lib/Dialect/Tosa/IR TosaCanonicalizations.cpp, mlir/test/Dialect/Tosa constant_folding.mlir

[mlir][tosa] Fold reshape of dense resource constants (#213225)

Add support for `DenseResourceElementsAttr` in TOSA reshape folding.
DeltaFile
+19-0mlir/test/Dialect/Tosa/constant_folding.mlir
+9-4mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
+28-42 files

LLVM/project 22508acllvm/test/CodeGen/X86 pr61923.ll

[X86] pr61923.ll - update IR to match middleend (#213908)

InstCombine converts vXi1 logic reductions to bitcasted scalar integer
ops - we should be testing that, not llvm.vector.reduce.and.v32i1 calls
DeltaFile
+2-1llvm/test/CodeGen/X86/pr61923.ll
+2-11 files

LLVM/project b728ce7llvm/test/CodeGen/AMDGPU occupancy-levels.ll

[AMDGPU][NFC] Add occupancy tests for GFX6/7/8
DeltaFile
+123-0llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
+123-01 files

LLVM/project dee06f0clang/lib/Driver/ToolChains Clang.cpp, clang/test/Driver openmp-target-fast-flag.c

Revert "Revert "[OpenMP] target-fast implies teams/threads oversubscription" …"

This reverts commit a5f7de0ce79e7b969cafc8684055ba5bd790397b.
DeltaFile
+15-7clang/test/Driver/openmp-target-fast-flag.c
+2-2clang/lib/Driver/ToolChains/Clang.cpp
+17-92 files

LLVM/project ebd0cbfmlir/include/mlir/IR TensorEncoding.td, mlir/lib/Dialect/Tensor/IR TensorOps.cpp

[mlir][tensor] Preserve encoding in more canonicalizers (pad, convertToStaticExpandShape) (#207241)

Fixes encoding drop in `tensor.*` canonicalizers.

Patterns that only refine a tensor's shape (never merge/combine data)
now propagate the encoding: `ConvertToStaticExpandShape`,
`PadOp::inferResultType` (and its callers `FoldSourceTensorCast`,
`FoldStaticPadding`). An encoding implementing
`VerifiableTensorEncoding` is re-verified against the refined shape and
dropped if invalid (e.g. sparse); an opaque encoding (no interface) is
propagated as-is.

Patterns that merge/combine tensors (`ConcatOp::inferResultType`,
`InferConcatOperandTypes`, `CollapseShapeOp::inferCollapsedType`) keep
the existing drop-encoding behavior - there's no static way to verify an
arbitrary encoding survives a merge or rank change when dynamic dims are
involved.

Documents this contract on `VerifiableTensorEncoding` in

    [4 lines not shown]
DeltaFile
+144-1mlir/test/Dialect/Tensor/canonicalize.mlir
+41-6mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
+28-0mlir/include/mlir/IR/TensorEncoding.td
+213-73 files

LLVM/project b5446f6llvm/test/MC/AArch64 tls-auth-relocs.s

Address review comments
DeltaFile
+2-2llvm/test/MC/AArch64/tls-auth-relocs.s
+2-21 files

LLVM/project 5156be9llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 intrinsic-vector-match-sve2.ll select-with-and-or.ll

[AArch64][ISel] Recover ADDHN from OR comparison masks (#210943)

InstCombine converts the high-half addition of vector comparison masks
into an OR. Recognise the resulting trunc(or(setcc, setcc)) DAG and
reconstruct the canonical ADDHN pattern for the supported NEON types.
DeltaFile
+60-72llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+48-38llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
+72-0llvm/test/CodeGen/AArch64/neon-addhn.ll
+19-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+8-10llvm/test/CodeGen/AArch64/select-with-and-or.ll
+5-7llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
+212-1279 files not shown
+238-14915 files

LLVM/project 53f5999llvm/lib/Transforms/InstCombine InstCombineLoadStoreAlloca.cpp, llvm/test/Transforms/InstCombine ptr-replace-alloca.ll

[InstCombine] Rebuild type-changing PHIs in PointerReplacer (#212429)

PointerReplacer mutates PHI types when replacing an alloca with a
pointer in another address space. Mutating a value type in place can
invalidate existing users whose result types or operand constraints were
formed from the original pointer type.

For example:
```
%p = phi ptr addrspace(5) [ %a, %bb0 ], [ %b, %bb1 ]
%g = getelementptr i8, ptr addrspace(5) %p, i64 1
```

Changing `%p` to `ptr addrspace(4)` leaves the existing GEP result in
`AS5` while its pointer operand is now in `AS4`. (This is what exposed
the bug). This triggered:

https://github.com/llvm/llvm-project/blob/0bcff14b1740cf32f9e0983726238dcf353c6ac8/llvm/lib/IR/Operator.cpp#L129-L131


    [9 lines not shown]
DeltaFile
+36-0llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll
+23-8llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+59-82 files

LLVM/project 256f40dorc-rt/lib/executor TargetDetails.h ExecutorProcessInfo.cpp, orc-rt/lib/executor/darwin CPUFeatures.cpp TargetTriple.cpp

Cpu features cross platform (#205447)

Also adds the place holders for other OS's as well as the structure for
cross platform code going forward.

Prefer sys calls as we can't be sure what runtime we may end up linking
with
Some features can be controlled via the kernel so this makes it easier
than relying on __cpuid for now.

The triples are now more accurate and include the os version on darwin. 

All results are a string that are passed in the default map with the key are llvm subtarget features valid strings
orc-rt.Executor.SubtargetFeatures

Adds a new process regression test as well, with a best effort
guess that the triple returned is correct.
DeltaFile
+107-6orc-rt/test/unit/ExecutorProcessInfoTest.cpp
+107-0orc-rt/lib/executor/darwin/TargetTriple.cpp
+33-29orc-rt/lib/executor/ExecutorProcessInfo.cpp
+62-0orc-rt/test/tools/orc-rt-process-info-check.cpp
+60-0orc-rt/lib/executor/darwin/CPUFeatures.cpp
+51-0orc-rt/lib/executor/TargetDetails.h
+420-3515 files not shown
+607-5421 files

LLVM/project e5c1f78libcxx/include string __split_buffer, libcxx/include/__memory unique_ptr.h

[libc++][NFC] Make __libcpp_is_trivially_relocatable a variable template (#213640)

Variable templates are a bit nicer to read and improve compile times a
bit.
DeltaFile
+90-105libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
+8-8libcxx/include/__memory/unique_ptr.h
+5-5libcxx/include/__type_traits/is_trivially_relocatable.h
+4-4libcxx/include/string
+4-4libcxx/include/__vector/vector.h
+4-4libcxx/include/__split_buffer
+115-13011 files not shown
+130-15117 files