LLVM/project a42f703llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-ctlz-zero-poison-extract-vector-elt.ll combine-ctlz-zero-poison-build-vector.ll

[GlobalISel][AMDGPU] Expand `isKnownNeverZero` for vector instructions (#211149)

A followup PR about adding some vector instruction patterns to
`isKnownNeverZero`, which firstly added in
https://github.com/llvm/llvm-project/pull/198438

The following instructions are added:
* `G_BUILD_VECTOR`
* `G_EXTRACT_VECTOR_ELT`
* `G_SHUFFLE_VECTOR`
DeltaFile
+97-0llvm/test/CodeGen/AMDGPU/GlobalISel/known-never-zero-vector.mir
+48-1llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+33-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-shuffle-vector.ll
+31-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-build-vector.ll
+24-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-zero-poison-extract-vector-elt.ll
+6-6llvm/test/tools/UpdateTestChecks/update_givaluetracking_test_checks/Inputs/const.mir.expected
+239-71 files not shown
+243-97 files

LLVM/project b6eb594llvm/test/CodeGen/AMDGPU splitkit-getsubrangeformask-phi-extend.ll memintrinsic-unroll.ll

[AMDGPU] Reschedule loads in clauses to improve throughput (#102595)

After clauses are formed their internal loads can be reordered to
facilitate some additional opportunities for overlapping computation.
This late stage rescheduling causes no change in register pressure.
DeltaFile
+2,087-1,967llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+445-403llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+449-293llvm/test/CodeGen/AMDGPU/div_i128.ll
+261-241llvm/test/CodeGen/AMDGPU/bf16.ll
+232-198llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+210-210llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
+3,684-3,31268 files not shown
+6,129-4,99474 files

LLVM/project 0fd1b98.github/workflows release-documentation.yml

Fixes plus debug
DeltaFile
+2-1.github/workflows/release-documentation.yml
+2-11 files

LLVM/project f2bfcf5llvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction extractelement.ll

[LoongArch] Use unsigned vector extract for zero extension (#214120)

Add patterns to select VPICKVE2GR_BU/HU and [X]VPICKVE2GR_WU for vector
extraction followed by zero extension, eliminating redundant masking
instructions.
DeltaFile
+16-38llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
+28-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+8-19llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
+13-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+65-574 files

LLVM/project 8d19df3llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/test/Analysis/CostModel/RISCV select-fp-zve32x.ll

[RISCV][CostModel] Fix invalid cost for vector select on targets without FP vector support (#183158)

Fixes #182047

**Issue:** Compiling floating-point vector selects (e.g., `<2 x float>`)
on RISC-V targets that only support integer vectors (like `zve32x`)
causes a compiler crash in the Loop Vectorizer (`emitInvalidCostRemarks`
unhandled `TypeSwitch`).

**Root Cause:** The Type Legalizer correctly scalarizes the unsupported
FP vector into `f32` operations. However,
`RISCVTTIImpl::getCmpSelInstrCost` attempted to cost
`Instruction::Select` natively without verifying floating-point vector
hardware support. It passed the scalarized type to
`getRISCVInstructionCost` to price a native vector merge instruction,
which returned `InstructionCost::getInvalid()`.

**Fix:** Added hardware support checks (`hasVInstructionsF16/32/64()`)
for floating-point types in the `Instruction::Select` block. If the

    [9 lines not shown]
DeltaFile
+57-0llvm/test/Analysis/CostModel/RISCV/select-fp-zve32x.ll
+1-1llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+58-12 files

LLVM/project f0c8cb2clang/docs HardwareAssistedAddressSanitizerDesign.md Block-ABI-Apple.md, clang/docs/CIR CleanupAndEHDesign.md

[docs] Finish MyST migration for selected docs
DeltaFile
+112-249clang/docs/CommandGuide/clang.md
+104-121clang/docs/ControlFlowIntegrityDesign.md
+94-98clang/docs/AutomaticReferenceCounting.md
+38-39clang/docs/CIR/CleanupAndEHDesign.md
+23-24clang/docs/HardwareAssistedAddressSanitizerDesign.md
+23-24clang/docs/Block-ABI-Apple.md
+394-5559 files not shown
+436-60615 files

LLVM/project b4c0131llvm/docs DirectXUsage.md RISCVUsage.md, llvm/docs/PDB index.md

[docs] Finish MyST migration for selected docs
DeltaFile
+391-337llvm/docs/LFI.md
+203-207llvm/docs/SymbolizerMarkupFormat.md
+192-202llvm/docs/RISCVUsage.md
+80-44llvm/docs/PDB/index.md
+20-25llvm/docs/DirectXUsage.md
+14-15llvm/docs/RISCV/RISCVVectorExtension.md
+900-8306 files not shown
+913-85912 files

LLVM/project ceaff22clang/lib/CodeGen CGExprScalar.cpp, clang/test/CodeGen constrained-math-builtins.c fp-reassoc-pragma.cpp

[Clang][CodeGen] Respect FP pragma options for fneg and calls (#212141)

Apply expression-specific floating-point options when emitting fneg and
call instructions.

This prevents these instructions from retaining fast-math flags disabled
by local FP pragmas, such as #pragma clang fp reassociate(off).

Fixes #51905
DeltaFile
+22-22clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
+22-8clang/test/CodeGen/fp-reassoc-pragma.cpp
+8-8clang/test/CodeGen/constrained-math-builtins.c
+5-1clang/lib/CodeGen/CGExprScalar.cpp
+57-394 files

LLVM/project 5ab9b3ellvm/docs AMDGPUMemoryModel.md

[Docs][AMDGPU] fully specify volatile accesses in the memory model (#214168)

A non-atomic volatile access on AMDGPU includes store-available or
load-visible
semantics at the widest scope supported by its address space:

- system scope for global/generic,
- workgroup scope for local (LDS)

An atomic volatile access has the same availability and visibility as
its atomic
non-volatile variant.

Previous Reference: 2f499b9

This fully specifies the behavior that the LLVM memory model leaves
target-dependent, matching the implementation in SIMemoryLegalizer. 

Assisted-By: Claude Opus 4.8
DeltaFile
+25-0llvm/docs/AMDGPUMemoryModel.md
+25-01 files

LLVM/project 35b6c91llvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx/ir-instruction extractelement.ll

[LoongArch] Use unsigned vector extract for zero extension

Add patterns to select VPICKVE2GR_BU/HU and [X]VPICKVE2GR_WU for vector
extraction followed by zero extension, eliminating redundant masking
instructions.
DeltaFile
+16-38llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
+28-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+8-19llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
+13-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+65-574 files

LLVM/project 22219cdllvm/docs Telemetry.md CMakePrimer.md, llvm/docs/RISCV RISCVVectorExtension.md

[docs] Convert selected rst docs with rst2myst
DeltaFile
+563-482llvm/docs/RISCVUsage.md
+282-270llvm/docs/SymbolizerMarkupFormat.md
+257-256llvm/docs/yaml2obj.md
+215-235llvm/docs/CMakePrimer.md
+200-229llvm/docs/RISCV/RISCVVectorExtension.md
+175-182llvm/docs/Telemetry.md
+1,692-1,65414 files not shown
+2,771-2,84420 files

LLVM/project 1a12786clang/docs ControlFlowIntegrityDesign.md Block-ABI-Apple.md, clang/docs/CIR ABILowering.md CleanupAndEHDesign.md

[docs] Convert selected rst docs with rst2myst
DeltaFile
+1,504-1,583clang/docs/AutomaticReferenceCounting.md
+1,110-1,139clang/docs/CIR/CleanupAndEHDesign.md
+640-663clang/docs/Block-ABI-Apple.md
+637-629clang/docs/CommandGuide/clang.md
+339-370clang/docs/CIR/ABILowering.md
+336-338clang/docs/ControlFlowIntegrityDesign.md
+4,566-4,72214 files not shown
+5,730-6,04020 files

LLVM/project 9a50892llvm/docs SymbolizerMarkupFormat.rst SymbolizerMarkupFormat.md

[docs] Rename selected LLVM docs to Markdown
DeltaFile
+0-721llvm/docs/RISCVUsage.rst
+721-0llvm/docs/RISCVUsage.md
+0-672llvm/docs/LFI.rst
+672-0llvm/docs/LFI.md
+0-439llvm/docs/SymbolizerMarkupFormat.rst
+439-0llvm/docs/SymbolizerMarkupFormat.md
+1,832-1,83234 files not shown
+5,153-5,15340 files

LLVM/project 07ae984clang/docs Block-ABI-Apple.rst Block-ABI-Apple.md, clang/docs/CIR CleanupAndEHDesign.rst CleanupAndEHDesign.md

[docs] Rename selected Clang docs to Markdown
DeltaFile
+0-2,674clang/docs/AutomaticReferenceCounting.rst
+2,674-0clang/docs/AutomaticReferenceCounting.md
+0-1,631clang/docs/CIR/CleanupAndEHDesign.rst
+1,631-0clang/docs/CIR/CleanupAndEHDesign.md
+0-944clang/docs/Block-ABI-Apple.rst
+944-0clang/docs/Block-ABI-Apple.md
+5,249-5,24935 files not shown
+10,297-10,29841 files

LLVM/project 1bfd939llvm/test/CodeGen/LoongArch/lasx/ir-instruction extractelement.ll, llvm/test/CodeGen/LoongArch/lsx/ir-instruction extractelement.ll

[LoongArch][NFC] Add tests for vector extraction with zero extension (#214119)
DeltaFile
+107-0llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
+64-0llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
+171-02 files

LLVM/project 8307b46bolt/lib/RuntimeLibs RuntimeLibrary.cpp, bolt/test CMakeLists.txt lit.cfg.py

[BOLT] Support runtime libraries built as thin archives (#214292)

In some configurations, BOLT runtime libraries may be built as thin
archive. Use the more generic `Archive::create` to handle these.
DeltaFile
+22-0bolt/test/runtime/thin-archive.c
+4-3bolt/lib/RuntimeLibs/RuntimeLibrary.cpp
+3-0bolt/test/lit.cfg.py
+1-0bolt/test/CMakeLists.txt
+30-34 files

LLVM/project c6eb5e3clang/docs ClangFormat.md ClangFormatStyleOptions.md, clang/docs/tools dump_format_help.py dump_format_style.py

[docs][clang-format] Migrate generated clang-format docs to markdown (#211398)

Tracking issue: #201242
See the [migration guide] for more information. 

This is a stacked PR based on #211397 , which will be a standalone
commit that
renames *.rst -> *.md before this PR lands for history preservation
purposes.

[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines

First, the generator was updated to generate markdown constructs, and
then the Doxygen comments in `Format.h` and `IncludeStyle.h` were also
modified to use markdown constructs. Mostly this means using single
backticks instead of double backticks, which is the Doxygen-native way
of expressing code font blocks anyway, so that's good.


    [3 lines not shown]
DeltaFile
+5,522-5,344clang/docs/ClangFormatStyleOptions.md
+404-404clang/include/clang/Format/Format.h
+241-260clang/docs/ClangFormat.md
+109-27clang/docs/tools/dump_format_style.py
+34-33clang/include/clang/Tooling/Inclusions/IncludeStyle.h
+3-11clang/docs/tools/dump_format_help.py
+6,313-6,0796 files

LLVM/project 56a654bllvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[DAG] Change `isExtractSubvectorCheap` into `getExtractSubvectorCost` (#213614)

This changes `isExtractSubvectorCheap` into `getExtractSubvectorCost`.

This is preparing for #201056 in order to remove `isNarrowingProfitable`
bail out for `narrowInsertExtractVectorBinOp`.

The reason is `isNarrowingProfitable` should be applying on scalar
variable instead of vectors.

---------

Co-authored-by: shore <shorshen at amd.com>
DeltaFile
+17-11llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+20-7llvm/include/llvm/CodeGen/TargetLowering.h
+17-9llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+15-8llvm/lib/Target/X86/X86ISelLowering.cpp
+10-4llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+8-5llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+87-4411 files not shown
+130-7717 files

LLVM/project 1b8dcb4llvm/lib/Target/NVPTX NVPTXISelLowering.cpp NVPTXInstrInfo.td

[NVPTX] Model SM architectures as subtarget features (NFC) (#214335)
DeltaFile
+170-170llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+89-121llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+93-82llvm/lib/Target/NVPTX/NVPTX.td
+64-97llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+50-78llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+38-39llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+504-5873 files not shown
+512-5949 files

LLVM/project 1c0eda0llvm/lib/Analysis ScalarEvolution.cpp, llvm/unittests/Analysis ScalarEvolutionTest.cpp

Revert "[SCEV] Speed up forgetLoop by avoiding def-use walk for loop-header PHIs" (#212485)

Reverts https://github.com/llvm/llvm-project/pull/201572
Multiple miscompilations are reported, see
https://github.com/llvm/llvm-project/issues/207744,
https://github.com/llvm/llvm-project/issues/212027

That commit made forgetLoop() rely on LoopUsers[L] and stop walking the
def-use chain of the loop-header PHIs. This is insufficient, because
some cached data is derived from the underlying IR of SCEVUnknown, it is
not reachable from LoopUsers[L].
After that commit, forgetLoop() no longer invalidated them, so stale
UnsignedRanges / SignedRanges, ConstantMultipleCache, ValuesAtScopes
cause miscompilations.
DeltaFile
+0-39llvm/unittests/Analysis/ScalarEvolutionTest.cpp
+16-6llvm/lib/Analysis/ScalarEvolution.cpp
+16-452 files

LLVM/project 7f298d7llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Update for comments
DeltaFile
+4-5llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4-51 files

LLVM/project 5be66d0llvm/lib/Target/AMDGPU SIModeRegisterDefaults.h SIISelLowering.h

[NFC][AMDGPU] Let IR level callers query the FMA/FMAD predicates (#213310)

isFMADLegal and isFMAFasterThanFMulAndFAdd read the denormal mode out of
the MachineFunction, so nothing before instruction selection can ask
them whether an fmul/fadd pair will be fused. Take an explicit
DenormalFPEnv instead, and make the existing MachineFunction /
SelectionDAG / MachineInstr entry points thin wrappers over it.

Also override the IR level isFMAFasterThanFMulAndFAdd hook. The two
views agree by construction, since SIModeRegisterDefaults copies its
denormal fields out of getDenormalFPEnv.

isFMADLegal uses VT as written and does not look through vectors, so a
vector type reports false, as in the SelectionDAG overload it was
extracted from.

The patch is preparation for querying these from getArithmeticInstrCost
and a revived isProfitableToSinkOperands.


    [2 lines not shown]
DeltaFile
+41-19llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+10-0llvm/lib/Target/AMDGPU/SIISelLowering.h
+5-0llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h
+56-193 files

LLVM/project a432964llvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/test/CodeGen/AMDGPU mad-mix-lo-bf16.ll mad-mix-lo.ll

[AMDGPU] Fix sign of zero in fpround(fmul) -> V_{MAD,FMA}_MIX{LO,HI} (#214544)

The isel patterns lowering `fptrunc (fmul float %a, %b)` to a mix
instruction passed +0.0 as the FMA addend. Under round-to-nearest fma(a,
b, +0.0) is +0.0 whenever a * b is -0.0, so the sign of zero was lost:
on gfx90a, `(half)(-1.0f * 0.0f)` returned +0.0.

Use a -0.0 addend instead, which is the correct multiplicative identity
for an FMA and is what the f32 sibling pattern in MadFmaMixFP32Pats has
always done.

Verified on gfx90a: (half)(-1.0f * 0.0f) now returns 0x8000.
DeltaFile
+76-76llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+76-76llvm/test/CodeGen/AMDGPU/llvm.log.ll
+11-11llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+4-4llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
+3-3llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+170-1705 files

LLVM/project 668134ellvm/include/llvm/DebugInfo/GSYM GsymReader.h FunctionInfo.h, llvm/lib/DebugInfo/GSYM FunctionInfo.cpp GsymReader.cpp

[gsymutil] Add `--statistics` option (#186495)

# Motiviation

Currently, if one wants to know the size of the sections in a gSYM (e.g.
to check if they exceed 4GB), they have to dump the whole gSYM in the
text form, then process that huge text to get the sizes.

# New option `--statistics[=<format>]`

This patch adds a `llvm-gsymutil --statistics[=<format>]` option to
print the size info for all sections. It supports three formats:
* `text`: Default.
* `json`: Dense JSON.
* `pretty-json`: Pretty-printed JSON.

See example output below.

# Examples

    [67 lines not shown]
DeltaFile
+397-0llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp
+204-0llvm/lib/DebugInfo/GSYM/GsymReader.cpp
+79-0llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp
+38-0llvm/include/llvm/DebugInfo/GSYM/FunctionInfo.h
+25-0llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
+18-0llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
+761-03 files not shown
+776-09 files

LLVM/project d39a398clang/docs ClangFormat.md ClangFormatStyleOptions.md, clang/docs/tools dump_format_help.py dump_format_style.py

[docs][clang-format] Migrate generated clang-format docs to markdown

The challenge here is that the documentation is generated from Doxygen
comments in headers, `Format.h` and `IncludeStyle.h`.

First, the generator was updated to generate markdown constructs, and
then the Doxygen comments were also modified to use markdown constructs.
Mostly this means using single backticks instead of double backticks,
which is the Doxygen-native way of expressing code font blocks anyway,
so that's good.

To validate, I built the Sphinx docs and the doxygen, and I confirmed
that the generator script is idempotent, meaning it doesn't change the
markdown output. When I add a new option to clang-format, it shows up in
the help text block, so it works.

Before/after validation links:
| Source file | Before HTML | After HTML |
| --- | --- | --- |

    [4 lines not shown]
DeltaFile
+5,424-5,444clang/docs/ClangFormatStyleOptions.md
+401-400clang/include/clang/Format/Format.h
+236-259clang/docs/ClangFormat.md
+87-27clang/docs/tools/dump_format_style.py
+34-33clang/include/clang/Tooling/Inclusions/IncludeStyle.h
+3-11clang/docs/tools/dump_format_help.py
+6,185-6,1746 files

LLVM/project 330f7fdclang/docs ClangFormatStyleOptions.md, clang/docs/tools dump_format_style.py

Fix dump_format_style.py blank lines and trailing whitespace, regenerate

The reindent_fenced_blocks() change in the previous commit introduced two
output issues when regenerating ClangFormatStyleOptions.md:

1. Empty lines inside code blocks got an indentation prefix added, producing
   trailing whitespace. Fix by skipping the prefix for whitespace-only lines.

2. The blank line that separates a description sentence from the following
   code fence was lost. This blank line is necessary for correct CommonMark
   loose-list rendering. Fix by inserting a blank line before any opening
   code fence (triple-backtick with a lang word, or ::: with a directive)
   that immediately follows a non-blank line.

Regenerate ClangFormatStyleOptions.md with the corrected generator.
DeltaFile
+263-64clang/docs/ClangFormatStyleOptions.md
+3-4clang/include/clang/Format/Format.h
+6-1clang/docs/tools/dump_format_style.py
+272-693 files

LLVM/project 0ce2c97clang/docs ClangFormatStyleOptions.md ClangFormat.md, clang/docs/tools dump_format_style.py

fix link word wrapping
DeltaFile
+26-9clang/docs/tools/dump_format_style.py
+9-5clang/docs/ClangFormat.md
+0-1clang/docs/ClangFormatStyleOptions.md
+35-153 files

LLVM/project 77b44ebclang/docs ClangFormat.rst ClangFormat.md, clang/lib/Format CMakeLists.txt

[docs][clang-format] Rename clang-format docs *.rst -> *.md, update refs (#211397)

Tracking issue: #201242
See the [migration guide] for more information. 

[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines

This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.

---------

Co-authored-by: owenca <owenpiano at gmail.com>
DeltaFile
+0-8,043clang/docs/ClangFormatStyleOptions.rst
+8,043-0clang/docs/ClangFormatStyleOptions.md
+0-366clang/docs/ClangFormat.rst
+366-0clang/docs/ClangFormat.md
+2-2clang/test/Format/docs_updated.test
+2-2clang/lib/Format/CMakeLists.txt
+8,413-8,4132 files not shown
+8,417-8,4178 files

LLVM/project 9219721llvm/test/CodeGen/NVPTX cache-hint-load-store.ll cache-hint-intrinsics.ll

[NVPTX] Fix broken cache hint metadata lit tests (#214600)

I just merged https://github.com/llvm/llvm-project/pull/204067 and
unfortunately forgot to locally compile all the PTX I was generating
from cache hint metadata in lit tests.

- I didn't know that .L2::cache_hint isn't valid on PTX volatile loads.
We need to drop the metadata then for volatile loads. I'll put this up
in a PR later, but for now just delete the lit test that generates the
invalid PTX. I'll add it back in the follow up.

- I forgot to provide SM version and PTX version when invoking ptxas for
the lit tests.
DeltaFile
+1-14llvm/test/CodeGen/NVPTX/cache-hint-transforms.ll
+1-1llvm/test/CodeGen/NVPTX/cache-hint-load-store.ll
+1-1llvm/test/CodeGen/NVPTX/cache-hint-intrinsics.ll
+1-1llvm/test/CodeGen/NVPTX/cache-hint-cache-policy.ll
+1-1llvm/test/CodeGen/NVPTX/cache-hint-atomics.ll
+5-185 files

LLVM/project 5200600clang-tools-extra/include-cleaner/lib WalkAST.cpp, clang-tools-extra/include-cleaner/unittests WalkASTTest.cpp

[include-cleaner] Ensure receiver headers are kept when accessing ObjC properties (#212633)

When accessing Objective-C properties via dot-notation (e.g., obj.foo),
include-cleaner was previously only recording the usage of the property
itself or its underlying getter/setter methods. This could lead to cases
where the header declaring the receiver's type (Interface or Protocol)
was incorrectly flagged as unused if no other standard methods were
invoked on it.
DeltaFile
+304-6clang-tools-extra/include-cleaner/unittests/WalkASTTest.cpp
+13-2clang-tools-extra/include-cleaner/lib/WalkAST.cpp
+317-82 files