LLVM/project ead188allvm/lib/Target/AArch64 AArch64.td AArch64ValidateRetiredNames.td, llvm/test/TableGen aarch64-retired-names.td

[AArch64] Prevent reuse of retired architecture names

Add explicit lists of retired AArch64 feature and system register names,
with TableGen validation preventing future definitions from reusing them.

This preserves names previously exposed by LLVM after their architectural
features or registers have been withdrawn or removed. Add coverage for
target features, architecture extension names and aliases, architectural
FEAT_* names, and system registers.
DeltaFile
+43-0llvm/test/TableGen/aarch64-retired-names.td
+37-0llvm/lib/Target/AArch64/AArch64ValidateRetiredNames.td
+12-0llvm/lib/Target/AArch64/AArch64.td
+92-03 files

LLVM/project 1afead7llvm/lib/CodeGen RegAllocPBQP.cpp, llvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp

Revert "[CodeGen] Use RegisterClassInfo for remaining allocation-order users" (#221749)

Reverts llvm/llvm-project#216510

breaks tests MIOpen/CK shard 1-4 in CI

queueing this up in case we want to save a bit of time
DeltaFile
+23-20llvm/lib/CodeGen/RegAllocPBQP.cpp
+16-19llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+8-10llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+47-493 files

LLVM/project ce27ca4llvm/test/Analysis/ScalarEvolution incorrect-nsw.ll ext-addrec-wrap-flags.ll

[SCEV] Add test coverage for ext-nusw/nsuw inference (#218943)

Complete the existing incorrect-nsw test, showing that zext-addrec nusw
is not implied by nw on the pre-inc AR, and that sext-addrec nsuw is not
implied by nw on the pre-inc AR. See also: #217405 and #217362.

Assisted-by: AI
DeltaFile
+389-0llvm/test/Analysis/ScalarEvolution/ext-addrec-wrap-flags.ll
+0-26llvm/test/Analysis/ScalarEvolution/incorrect-nsw.ll
+389-262 files

LLVM/project fd4549aoffload/libomptarget omptarget.cpp, offload/plugins-nextgen/common/include PluginInterface.h

[offload][omp] Remove data_fence

All supported backends execute enqueued work on a given queue in
submission order (CUDA, AMDGPU, and Host queues are always in-order;
Level Zero's default and non-default in-order/synchronous command
modes are as well), so the explicit data-fence used to order a
pointer-attachment after prior data transfers is unnecessary. Remove
the DeviceTy/GenericDeviceTy/GenericPluginTy dataFence chain and the
now-unused olQueueBarrier liboffload API added to support it.
DeltaFile
+4-17offload/libomptarget/omptarget.cpp
+0-12offload/plugins-nextgen/common/src/PluginInterface.cpp
+0-8offload/plugins-nextgen/level_zero/src/L0Device.cpp
+0-8offload/plugins-nextgen/common/include/PluginInterface.h
+0-7offload/plugins-nextgen/host/src/rtl.cpp
+0-7offload/plugins-nextgen/cuda/src/rtl.cpp
+4-595 files not shown
+4-7611 files

LLVM/project 1ce91bbllvm/lib/Transforms/Utils SimplifyCFG.cpp, llvm/test/Transforms/SimplifyCFG preserve-unpredictable-switch-create.ll

[SimplifyCFG] Preserve !unpredictable when forming a switch (#221580)

SimplifyCFG turns a chain of equality comparisons into a switch in two
places, performValueComparisonIntoPredecessorFolding() and
simplifyBranchOnICmpChain(), and neither propagated !unpredictable. The
hint was therefore dropped even though it is valid on a switch and the
reverse transform, simplifySwitchOfCmpIntrinsic(), already preserves it.

Propagate the metadata in both. Folding a comparison into a predecessor
merges two decisions into a single switch, so the result is only marked
unpredictable when both of the folded comparisons were. That also makes
chains longer than two blocks work: the fold runs once per predecessor
and reads the metadata back off the switch it built on the previous
iteration.

simplifyBranchOnICmpChain() also emits a range check instead of a switch
when the case values are contiguous. That branch is an exact replacement
for the original one, so it inherits the metadata unconditionally, and
the flag now survives into the machine IR.

Fixes #42658.
DeltaFile
+180-0llvm/test/Transforms/SimplifyCFG/preserve-unpredictable-switch-create.ll
+10-0llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+190-02 files

LLVM/project 068a7cfoffload/liboffload exports, offload/liboffload/API Queue.td

[offload][omp] Manage data fence through liboffload
DeltaFile
+14-0offload/liboffload/API/Queue.td
+0-12offload/plugins-nextgen/common/src/PluginInterface.cpp
+8-0offload/liboffload/src/OffloadImpl.cpp
+5-1offload/libompaccsupport/device.cpp
+0-4offload/plugins-nextgen/common/include/PluginInterface.h
+0-1offload/liboffload/exports
+27-186 files

LLVM/project 01f5d4eoffload/include device.h, offload/liboffload exports

[offload][omp] Manage events through liboffload
DeltaFile
+0-73offload/plugins-nextgen/common/src/PluginInterface.cpp
+35-18offload/libompaccsupport/device.cpp
+0-21offload/plugins-nextgen/common/include/PluginInterface.h
+4-5offload/include/device.h
+0-5offload/liboffload/exports
+39-1225 files

LLVM/project f17a6bcllvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h

[SPIRV] Preserve DebugGlobalVariable emission order.

Iterate GlobalVariableDebugInfoMap with MapVector so OpString and
DebugGlobalVariable follow insertion order.
DeltaFile
+1-1llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+1-11 files

LLVM/project 10a3788llvm/lib/Target/RISCV RISCVInstrInfoZvdot4a8i.td RISCVInstrInfoVVLPatterns.td

[RISCV] Add VPatBinaryVL_R_VX to share between VRSUB.VX and VDOT4AUS.VX. NFC (#221284)

Assisted-by: Claude
DeltaFile
+27-8llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+1-11llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td
+28-192 files

LLVM/project ca03587llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h

Add missing comment.
DeltaFile
+4-0llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+4-01 files

LLVM/project 0dce2e9llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h SPIRVNonSemanticDebugHandler.cpp, llvm/test/CodeGen/SPIRV/debug-info debug-scope-no-scope-block.ll

[reviews] Simplify code and add new test to prevent future regressions.
DeltaFile
+62-0llvm/test/CodeGen/SPIRV/debug-info/debug-scope-no-scope-block.ll
+12-8llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+0-1llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+74-93 files

LLVM/project 35b967coffload/libompaccsupport PluginManager.cpp device.cpp, offload/libomptarget omptarget.cpp

[offload][omp] memory operations through liboffload
DeltaFile
+0-90offload/plugins-nextgen/common/src/PluginInterface.cpp
+68-16offload/libompaccsupport/device.cpp
+43-4offload/libompaccsupport/PluginManager.cpp
+12-24offload/libomptarget/OpenMP/API.cpp
+0-31offload/plugins-nextgen/common/include/PluginInterface.h
+25-4offload/libomptarget/omptarget.cpp
+148-1696 files not shown
+181-18512 files

LLVM/project 40e054doffload/include PluginManager.h, offload/liboffload exports

[offload][omp] Use olIterateCompatibleDevices for device init and image registration
DeltaFile
+119-109offload/libompaccsupport/PluginManager.cpp
+9-8offload/libompaccsupport/device.cpp
+0-15offload/plugins-nextgen/common/src/PluginInterface.cpp
+5-8offload/include/PluginManager.h
+0-6offload/plugins-nextgen/common/include/PluginInterface.h
+1-4offload/liboffload/exports
+134-1502 files not shown
+142-1518 files

LLVM/project 9313f07offload/liboffload/API Program.td, offload/liboffload/src OffloadImpl.cpp

[OFFLOAD] Add olIterateCompatibleDevices API
DeltaFile
+73-0offload/unittests/OffloadAPI/program/olIterateCompatibleDevices.cpp
+26-0offload/liboffload/src/OffloadImpl.cpp
+15-0offload/liboffload/API/Program.td
+1-0offload/unittests/OffloadAPI/CMakeLists.txt
+115-04 files

LLVM/project 08881a0offload/include PluginManager.h, offload/liboffload exports

[offload][omp] Load plugins through liboffload
DeltaFile
+15-11offload/libompaccsupport/PluginManager.cpp
+5-0offload/liboffload/src/OffloadImpl.cpp
+2-1offload/include/PluginManager.h
+1-1offload/liboffload/exports
+23-134 files

LLVM/project d97f21boffload/liboffload/src OffloadImpl.cpp

[offload] lazily load liboffload
DeltaFile
+242-90offload/liboffload/src/OffloadImpl.cpp
+242-901 files

LLVM/project 8bc2b2foffload/liboffload/API Platform.td, offload/liboffload/src OffloadImpl.cpp

[OFFLOAD] add olIteratePlatforms
DeltaFile
+45-0offload/unittests/OffloadAPI/platform/olIteratePlatforms.cpp
+23-0offload/liboffload/API/Platform.td
+11-0offload/liboffload/src/OffloadImpl.cpp
+79-03 files

LLVM/project 72d6236offload/liboffload exports, offload/liboffload/src OffloadImpl.cpp

[offload][omp] link libomptarget against liboffload
DeltaFile
+58-0offload/liboffload/exports
+9-3offload/liboffload/src/OffloadImpl.cpp
+5-5offload/libomptarget/CMakeLists.txt
+6-0offload/libomptarget/exports
+3-0offload/libomptarget/interface.cpp
+81-85 files

LLVM/project dd3fe03llvm/lib/Target/AMDGPU AMDGPUAnnotateUniformValues.cpp, llvm/test/CodeGen/AMDGPU move-to-valu-pseudo-scalar-trans.ll move-to-valu-pseudo-scalar-trans-f16-true16.ll

Don't infer noclobber for volatile accesses.
DeltaFile
+9-9llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
+7-7llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
+5-5llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
+5-5llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
+5-5llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
+4-4llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
+35-351 files not shown
+36-367 files

LLVM/project e92c19alibc/src/__support/CPP algorithm.h, libc/src/__support/CPP/utility swap.h

[libc] Add cpp::swap and cpp::clamp utilities (#221236)

Added cpp::swap to src/__support/CPP/utility/swap.h with move semantics
and array support, and cpp::clamp to src/__support/CPP/algorithm.h with
comparator support.

Included unit tests in swap_test.cpp and algorithm_test.cpp.

Adopted the new utilities in initial callsites:
* stdlib: Used cpp::swap in qsort_data.h
* wctype: Used cpp::swap in perfect_hash_map.h
* math: Used cpp::clamp in powf.h
* scanf_core: Used cpp::min and cpp::max in parser.h

Also fixed sign extension when parsing scanset specifiers in parser.h:
signed characters greater than or equal to 128 produced negative values,
inverting comparisons and causing out-of-bounds writes in the bitset.
Scanset characters are now cast through uint8_t, and non-ASCII tests
were added to parser_test.cpp.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+117-0libc/test/src/__support/CPP/swap_test.cpp
+50-1libc/test/src/stdio/scanf_core/parser_test.cpp
+45-1libc/test/src/__support/CPP/algorithm_test.cpp
+39-0libc/src/__support/CPP/utility/swap.h
+13-8libc/src/stdio/scanf_core/parser.h
+16-3libc/src/__support/CPP/algorithm.h
+280-1310 files not shown
+332-3016 files

LLVM/project f16746allvm/lib/Target/AMDGPU SIInstrInfo.cpp AMDGPUInstrInfo.h

[AMDGPU] Remove dead D16ImageDimIntrinsic and lookupD16ImageDimIntrinsic (NFC) (#221660)

The corresponding TableGen table and callers were removed on June 21,
2018 in commit 7a9c03f484fee744b1cbcc45e77f949b4ebfcbee, leaving behind
the struct, the declaration, and the unused macro definition.

Assisted-by: Antigravity
DeltaFile
+0-6llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
+0-1llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+0-72 files

LLVM/project 07f6736lldb/source/Plugins/Language/Fortran CMakeLists.txt FortranLanguage.h, lldb/source/Target Language.cpp

[lldb][Fortran] Add Fortran language plugin to LLDB (#221301)

This PR adds the Plugin necessary for LLDB to recognise Fortran.
Subsequent PRs will add the TypeSystem and the DWARFASTParser for
Fortran.

Changes:
- Adds Fortran language Plugin.
- Adds LanguageIsFortran function to the Language class to help identify
Fortran.

Testing:
- Check if language Plugin is registered.

Part of the Add Fortran support to LLDB GSoC 2026 project.

Relates to #109119.

Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
DeltaFile
+55-0lldb/source/Plugins/Language/Fortran/FortranLanguage.cpp
+48-0lldb/source/Plugins/Language/Fortran/FortranLanguage.h
+31-0lldb/unittests/Language/Fortran/FortranLanguageTest.cpp
+14-0lldb/source/Target/Language.cpp
+12-0lldb/source/Plugins/Language/Fortran/CMakeLists.txt
+6-0lldb/unittests/Language/Fortran/CMakeLists.txt
+166-03 files not shown
+170-09 files

LLVM/project 1cfbd8fllvm/lib/CodeGen RegAllocPBQP.cpp, llvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp

Revert "[CodeGen] Use RegisterClassInfo for remaining allocation-order users …"

This reverts commit 0664fb13c0dd34fd3d041a5d2610650945518e02.
DeltaFile
+23-20llvm/lib/CodeGen/RegAllocPBQP.cpp
+16-19llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+8-10llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+47-493 files

LLVM/project 905559eclang/test/CIR/CodeGenBuiltins/AArch64 acle_sve_len.c acle_sve_dup.c, clang/test/CodeGen/AArch64/sve len.c dup.c

Rebase

Created using spr 1.3.7
DeltaFile
+824-0clang/test/CodeGen/AArch64/sve/dup.c
+0-818clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c
+177-0clang/test/CodeGen/AArch64/sve/len.c
+0-170clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_len.c
+0-108llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+98-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
+1,099-1,09626 files not shown
+1,537-1,28632 files

LLVM/project 17e32b0llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp, llvm/test/CodeGen/SPIRV/debug-info debug-local-variable-skip-type.ll debug-local-variable-dbg-value.ll

[SPIRV] Add support for NSDI DebugLocalVariable.
DeltaFile
+69-11llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+58-0llvm/test/CodeGen/SPIRV/debug-info/debug-local-variable.ll
+43-0llvm/test/CodeGen/SPIRV/debug-info/debug-local-variable-records-and-retained.ll
+41-0llvm/test/CodeGen/SPIRV/debug-info/debug-local-variable-dbg-value.ll
+41-0llvm/test/CodeGen/SPIRV/debug-info/debug-local-variable-retained-nodes.ll
+32-0llvm/test/CodeGen/SPIRV/debug-info/debug-local-variable-skip-type.ll
+284-111 files not shown
+305-117 files

LLVM/project d246c5ellvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/lib/Transforms/Vectorize/SLPVectorizer SLPUtils.h SLPUtils.cpp

[SLP][modularisation][NFC] Move order/mask helpers to SLPUtils (#221663)

Move the following BoUpSLP-independent order/mask helpers out of
SLPVectorizer.cpp into SLPVectorizer/SLPUtils.{h,cpp}:

  reorderReuses
  reorderOrder
  isReverseOrder
  isRepeatedNonIdentityClusteredMask
  combineOrders

They sit with the existing permutation helpers. Behavior is unchanged.

Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
DeltaFile
+0-108llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+98-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
+26-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
+124-1083 files

LLVM/project d03de58clang/utils/TableGen CIRLoweringEmitter.cpp

[CIR] Derive lowering attr names from cppClassName, not the def name

CIRLoweringEmitter built its CXX_ABI_ALWAYS_LEGAL_ATTRS entries with
GetOpCppClassName, which splits the TableGen def name at the first
underscore. That works only while every def is named CIR_<CppClassName>Attr.
When one is not, the emitter writes an `isa<>` for a class that does not
exist, and the failure lands as a compile error in generated code.

Attributes carry the authoritative name in cppClassName, which
GenerateAttrToValueVisitor was already reading. Factor that out as
GetAttrCppClassRef and use it for both attribute paths. GetOpCppClassName
stays for operations.

NFC, and checkable. No CIR attribute overrides cppClassName, so the generated
CIRLowering.inc is byte-identical.
DeltaFile
+16-10clang/utils/TableGen/CIRLoweringEmitter.cpp
+16-101 files

LLVM/project 95de5ebclang/include/clang/CIR/Dialect/IR CIREnumAttr.td CIROps.td

[CIR] Drop dead ceremony around the CIR enum attributes (#220890)

Five things that no longer earn their place in the CIR enum attribute
machinery.

CIR_CleanupKindAttr carried three. Its cppClassName restated the default
AttrDef already derives. Its skipDefaultBuilders plus hand-written
AttrBuilder existed only to default $value to CleanupKind::All, which no
caller relies on, so the generated builders stayed suppressed for
nothing.
And its summary and description restated the name, overriding the enum's
own
"cleanup kind" that EnumAttr would otherwise inherit. The isNormal, isEH
and
isNormalAndEH helpers stay.

CIR_TLSModelAttr's summary restated its name the same way, so only that
goes.
CIR_DefaultValuedEnumParameter has never had a user.
DeltaFile
+0-16clang/include/clang/CIR/Dialect/IR/CIROps.td
+0-5clang/include/clang/CIR/Dialect/IR/CIREnumAttr.td
+0-212 files

LLVM/project 330bb86llvm/docs LibFuzzer.md

[docs][libFuzzer] Fix formatting and collapsed definition lists (#206709)

This PR fixes broken formatting and collapsed definition lists in the
libFuzzer documentation by adding missing blank lines.

Closes #206706

Signed-off-by: Anchels <mishtitov at gmail.com>
DeltaFile
+41-0llvm/docs/LibFuzzer.md
+41-01 files

LLVM/project c84706fllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-masked-scatter.ll sve-insert-vector-to-predicate-load.ll

[AArch64][SVE] Lower extended v2i8 loads using SVE. (#217006)

Loads of v2i8 are promoted to v2i32, which requires two extend
operations; v2i8 -> v2i16, then v2i16 -> v2i32. This comes largely for
free when using SVE's extending loads.
DeltaFile
+75-0llvm/test/CodeGen/AArch64/load.ll
+5-7llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
+8-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+4-5llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
+2-4llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll
+2-3llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
+96-226 files