LLVM/project 01cb854llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

InstCombine: Handle canonicalize in SimplifyDemandedFPClass

Doesn't try to handle PositiveZero flushing mode, but I
don't believe it is incorrect with it.
DeltaFile
+26-53llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll
+73-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+6-49llvm/lib/Analysis/ValueTracking.cpp
+48-0llvm/lib/Support/KnownFPClass.cpp
+5-0llvm/include/llvm/Support/KnownFPClass.h
+158-1025 files

LLVM/project 06ef509llvm/test/Transforms/InstCombine simplify-demanded-fpclass-canonicalize.ll

InstCombine: Add baseline test for canonicalize SimplifyDemandedFPClass
DeltaFile
+609-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll
+609-01 files

LLVM/project 80887c7clang/include/clang/Basic DiagnosticFrontendKinds.td DiagnosticGroups.td, clang/lib/CodeGen CGOpenMPRuntime.cpp CodeGenModule.cpp

[clang][NFC][diagnostics] Remove most usage of `getCustomDiagID()` from CodeGen (#172557)

DeltaFile
+63-0clang/include/clang/Basic/DiagnosticFrontendKinds.td
+11-29clang/lib/CodeGen/CGOpenMPRuntime.cpp
+10-20clang/lib/CodeGen/CodeGenModule.cpp
+4-12clang/lib/CodeGen/CodeGenPGO.cpp
+2-7clang/lib/CodeGen/BackendUtil.cpp
+9-0clang/include/clang/Basic/DiagnosticGroups.td
+99-688 files not shown
+115-9214 files

LLVM/project 42b3483llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor nofpclass-canonicalize.ll

ValueTracking: Improve accuracy of 0 handling with PreserveSign (#173165)

If the source value is known not subnormal and not zero with the
same sign, we can infer the result is also not zero with the same
sign.
DeltaFile
+26-26llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
+8-0llvm/lib/Analysis/ValueTracking.cpp
+34-262 files

LLVM/project c513e6allvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor nofpclass-canonicalize.ll

ValueTracking: Improve accuracy of 0 handling with PreserveSign

If the source value is known not subnormal and not zero with the
same sign, we can infer the result is also not zero with the same
sign.
DeltaFile
+26-26llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
+8-0llvm/lib/Analysis/ValueTracking.cpp
+34-262 files

LLVM/project ffbed74llvm/test/Transforms/Attributor nofpclass-canonicalize.ll

ValueTracking: Add more tests for computeKnownFPClass canonicalize (#173164)

DeltaFile
+90-0llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
+90-01 files

LLVM/project 0d29efbllvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port fc4661aa11a0
DeltaFile
+1-0llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+1-01 files

LLVM/project fc4661alibcxx/include/__ranges adjacent_transform_view.h, libcxx/test/std/ranges/range.adaptors/range.adjacent.transform adaptor.pass.cpp end.pass.cpp

[libc++] Implement `adjacent_transform` (#168208)

This patch implements std::ranges::adjacent_transform_view. This is part
of P2321R2 tracked
by #105169.
DeltaFile
+406-0libcxx/include/__ranges/adjacent_transform_view.h
+275-0libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/adaptor.pass.cpp
+206-0libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/sentinel/eq.pass.cpp
+195-0libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/sentinel/minus.pass.cpp
+183-0libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/end.pass.cpp
+164-0libcxx/test/std/ranges/range.adaptors/range.adjacent.transform/iterator/arithmetic.pass.cpp
+1,429-026 files not shown
+3,487-532 files

LLVM/project 0952cccllvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine icmp-binop.ll

[InstCombine] Bail out on type mismatch in foldICmpBinOpWithConstantViaTruthTable (#173179)

Fixes https://github.com/llvm/llvm-project/issues/173177
The previous implementation doesn't consider cases like `<2 x i1>
icmp(binop(sel <2 x i1>, sel i1))`.
DeltaFile
+17-1llvm/test/Transforms/InstCombine/icmp-binop.ll
+1-1llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+18-22 files

LLVM/project f06f5b5llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv rvv-vmerge-to-vmv.ll

[RISCV] Use legally typed splat during vmv_v_v splat(x) -> vmv_v_x (#173154)

Fixes https://github.com/llvm/llvm-project/issues/173141
Introduced in #170539, `DAG.getSplatValue` may involve the illegal-typed
splat value if not specified. This patch fixes it.
DeltaFile
+23-0llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+24-12 files

LLVM/project 3eee451llvm/lib/Transforms/IPO MergeFunctions.cpp

Fix use-after-free bug in mergeTwoFunctions(). (#173126)

This was caught by Apple's Probabilistic Guard Malloc which detected
that OldF's memory is freed inside mergeTwoFunctions(), and then
back in insert() the now dangling pointer is dereferenced again.

rdar://163874208
DeltaFile
+7-3llvm/lib/Transforms/IPO/MergeFunctions.cpp
+7-31 files

LLVM/project 3ce0552llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV load-narrow-shift-mask-combine.ll

[RISCV] Introduce new AND combine to expose additional load narrowing opportunities (#170483)

The standard codegen pipeline sometimes ends up with a shift followed by
 a mask. If doing the mask first would have enabled load narrowing, then
 it is preferable to do so. The motivating example was seen in povray
 from SPEC where we had something like:

 ```
 lh a0, 0(a0)
 slli a0, a0, 56
 srli a0, a0, 52
 ```

 Which can be better implemented as:
 ```
 lbu a0, 0(a0)
 slli a0, a0, 4
 ```


    [3 lines not shown]
DeltaFile
+43-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+10-16llvm/test/CodeGen/RISCV/load-narrow-shift-mask-combine.ll
+1-1llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+54-183 files

LLVM/project 6b09f73llvm/test/CodeGen/RISCV load-narrow-shift-mask-combine.ll

[RISCV][test] Precommit test case showing opportunity to narrow loads for some shift then mask cases

Reviewed as part of #170483
DeltaFile
+80-0llvm/test/CodeGen/RISCV/load-narrow-shift-mask-combine.ll
+80-01 files

LLVM/project 177072amlir/python/mlir/dialects scf.py, mlir/test/python/dialects scf.py

[MLIR][Python] Update the scf.if interface to be consistent with affine.if (#173171)

This is a follow-up of #171957 that updates the argument names of
`scf.if` Python binding to be consistent with `affine.if`. Basically,
both operations should use `has_else` to determine whether the `if`
block is presented.

cc @makslevental
DeltaFile
+7-5mlir/python/mlir/dialects/scf.py
+1-1mlir/test/python/dialects/scf.py
+8-62 files

LLVM/project 4fec702clang/docs ReleaseNotes.rst, clang/lib/Sema SemaInit.cpp

[clang] Add FixItHint for designated init order (#173136)

Generate fix-it for C++20 designated initializers when the initializers
do not match the declaration order in the structure.
DeltaFile
+105-0clang/test/SemaCXX/cxx20-designated-initializer-fixits.cpp
+65-3clang/lib/Sema/SemaInit.cpp
+3-0clang/docs/ReleaseNotes.rst
+173-33 files

LLVM/project 14b9478clang-tools-extra/clang-tidy/bugprone ArgumentCommentCheck.cpp

[clang-tidy][NFC] Refactor `bugprone-argument-comment` [1/3] (#172521)

This is a necessary step to land #171757

Part of https://github.com/llvm/llvm-project/issues/170921
DeltaFile
+21-21clang-tools-extra/clang-tidy/bugprone/ArgumentCommentCheck.cpp
+21-211 files

LLVM/project b5fd757clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaSYCL.cpp SemaDecl.cpp

[Clang][SYCL][NFC] Modify err_sycl_entry_point_invalid to use %enum_select. (#173122)

The `err_sycl_entry_point_invalid` diagnostic has a selection field for
which there are already many options with more expected to be added. Use
of `%enum_select` avoids the need for magic numbers with associated
comments at source locations where the diagnostic is issued.
DeltaFile
+11-5clang/include/clang/Basic/DiagnosticSemaKinds.td
+7-7clang/lib/Sema/SemaSYCL.cpp
+4-4clang/lib/Sema/SemaDecl.cpp
+22-163 files

LLVM/project b0eb38allvm/lib/IR Constants.cpp, llvm/test/CodeGen/AMDGPU branch-folding-implicit-def-subreg.ll tuple-allocation-failure.ll

[WIP][IR][Constants] Change the semantic of `ConstantPointerNull` to represent an actual `nullptr` instead of a zero-value pointer

The value of a `nullptr` is not always `0`. For example, on AMDGPU, the `nullptr` in address spaces 3 and 5 is `0xffffffff`. Currently, there is no target-independent way to get this information, making it difficult and error-prone to handle null pointers in target-agnostic code.

We do have `ConstantPointerNull`, but it might be a little confusing and misleading. It represents a pointer with an all-zero value rather than necessarily a real `nullptr`. Therefore, to represent a real `nullptr` in address space `N`, we need to use `addrspacecast ptr null to ptr addrspace(N)` and it can't be folded.

In this PR, we change the semantic of `ConstantPointerNull` to represent an actual `nullptr` instead of a zero-value pointer. Here is the detailed changes.

* `ptr addrspace(N) null` will represent the actual `nullptr` in address space `N`.
* `ptr addrspace(N) zeroinitializer` will represent a zero-value pointer in address space `N`.

* `Constant::getNullValue` will return a _null_ value. It is same as the current semantics except for the `PointerType`, which will return a real `nullptr` pointer.
* `Constant::getZeroValue` will return a zero value constant. It is completely same as the current semantics. To represent a zero-value pointer, a `ConstantExpr` will be used (effectively `inttoptr i8 0 to ptr addrspace(N)`).
* Correspondingly, there will be both `Constant::isNullValue` and `Constant::isZeroValue`.

The RFC is https://discourse.llvm.org/t/rfc-introduce-sentinel-pointer-value-to-datalayout/85265. It is a little bit old and the title might look different, but everything eventually converges to this change. An early attempt can be found in https://github.com/llvm/llvm-project/pull/131557, which has many valuable discussion as well.

This PR is still WIP but any early feedback is welcome. I'll include as many necessary code changes as possible in this PR, but eventually this needs to be carefully split into multiple PRs, and I'll do it after the changes look good to every one.
DeltaFile
+257-257llvm/test/DebugInfo/Generic/debug-names-many-cu.ll
+115-99llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+100-94llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
+76-73llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
+96-17llvm/lib/IR/Constants.cpp
+85-26llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+729-566611 files not shown
+2,190-1,815617 files

LLVM/project 51c085bllvm/lib/Target/RISCV RISCVMakeCompressible.cpp, llvm/test/CodeGen/RISCV make-compressible-xqci.mir

[RISCV] Support Xqcilo loads/stores in RISCVMakeCompressible (#172971)

This patch adds support for converting Xqcilo loads/stores with either
large offsets or uncompressible registers into loads/stores that can be
compressed. We do this transformation only when the Xqcilia extension is
enabled in addition to the Xqcilo extension so that we can use the
QC_E_ADDI instruction to form the new base.

There might be a few cases where compressing from the 48-bit Xqcilo
load/store to a 32-bit load/store might be beneficial which this patch
does not address.
DeltaFile
+543-0llvm/test/CodeGen/RISCV/make-compressible-xqci.mir
+41-4llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+584-42 files

LLVM/project 7d0773bllvm/include/llvm/ADT Bitset.h STLExtras.h, llvm/unittests/ADT BitsetTest.cpp STLExtrasTest.cpp

Revert "Make STLExtras's (all|any|none)_of() Utility Functions Constexpr-Friendly" (#173163)

Reverts llvm/llvm-project#172536. This is causing weird assertion
failures in clang, per
https://github.com/llvm/llvm-project/pull/172536#issuecomment-3677973154.
It might be a bug in GCC, but still makes sense to revert it in the
interest of bootstrapping.

---------

Signed-off-by: Michał Górny <mgorny at gentoo.org>
DeltaFile
+0-226llvm/unittests/ADT/BitsetTest.cpp
+15-44llvm/include/llvm/ADT/Bitset.h
+8-17llvm/include/llvm/ADT/STLExtras.h
+0-19llvm/unittests/ADT/STLExtrasTest.cpp
+23-3064 files

LLVM/project 5b606bdllvm/lib/Target/LoongArch LoongArchISelLowering.cpp

[LoongArch] Use getShiftAmountConstant. NFC

This avoids an unnecessary type legalization step to fix the shift amount.
DeltaFile
+1-1llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+1-11 files

LLVM/project ec797b3mlir/cmake/modules AddMLIRPython.cmake, mlir/examples/standalone CMakeLists.txt

massage cmake
DeltaFile
+98-31mlir/cmake/modules/AddMLIRPython.cmake
+10-61mlir/python/CMakeLists.txt
+3-0mlir/examples/standalone/CMakeLists.txt
+111-923 files

LLVM/project da98be1clang/lib/CIR/CodeGen CIRGenBuiltin.cpp, clang/test/CIR/CodeGen fp-math-precision-opts.c

[CIR] Only emit FP math intrinsics when precision/errno settings allow it (#169424)

Depending on the compiler CLI options, attributes near the call site and
pragmas we might not be allowed to emit a call to an intrinsic (e.g. if
it does not set errno and we expect it to be set). This is checked by
`shouldGenerateFPMathIntrinsic` (shared with classing codegen).

This commit adds this check and additionally adds remaining cases in the
switch statement for math builtins.
DeltaFile
+390-65clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+79-0clang/test/CIR/CodeGen/fp-math-precision-opts.c
+469-652 files

LLVM/project 9f4f13allvm/lib/Target/AMDGPU AMDGPULowerKernelArguments.cpp, llvm/test/CodeGen/AMDGPU mad-combine.ll lower-noalias-kernargs.ll

[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments. (#161375)

Emit `!noalias` and `alias.scope` metadata for `noalias` kernel
arguments.

---------

Co-authored-by: Leon Clark <leoclark at amd.com>
DeltaFile
+197-251llvm/test/CodeGen/AMDGPU/mad-combine.ll
+434-0llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
+148-148llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
+101-101llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
+139-10llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
+43-35llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+1,062-5454 files not shown
+1,155-60010 files

LLVM/project f42af14llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/AArch64 select-costs.ll

Revert "[VPlan] Use predicate from VPValue VPWidenSelectR::computeCost." (#173170)

Reverts llvm/llvm-project#172915

Looks like this may be causing
https://lab.llvm.org/buildbot/#/builders/128/builds/9590 to fail. 
Revert while I confirm.
DeltaFile
+4-4llvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
+3-2llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+7-62 files

LLVM/project 21571cfclang/lib/CodeGen CGExpr.cpp CGExprScalar.cpp, clang/test/CodeGen matrix-type-indexing.c

[HLSL][Matrix] Support row and column indexing modes for MatrixSubscriptExpr (#171564)

fixes #167617

In DXC HLSL supports different indexing modes via codegen for its
equivalent of the MatrixSubscriptExpr when the /Zpr and /Zpc flags are
used see: https://godbolt.org/z/bz5Y5WG36.

This change modifies EmitMatrixSubscriptExpr to consider the
MatrixRowMajor/MatrixColMajor Layout flags before generating an index.

Similarly it introduces `createRowMajorIndex` and
`createColumnMajorIndex` in `MatrixBuilder.h` for use in
`VisitMatrixSubscriptExpr`.
DeltaFile
+60-0clang/test/CodeGen/matrix-type-indexing.c
+52-0clang/test/CodeGenHLSL/BasicFeatures/matrix-type-indexing.hlsl
+36-0clang/test/CodeGenCXX/matrix-type-indexing.cpp
+22-2llvm/include/llvm/IR/MatrixBuilder.h
+16-7clang/lib/CodeGen/CGExpr.cpp
+12-3clang/lib/CodeGen/CGExprScalar.cpp
+198-126 files

LLVM/project cb56a91clang/lib/Headers/hlsl hlsl_alias_intrinsics.h, clang/lib/Sema SemaHLSL.cpp SemaExpr.cpp

[HLSL][Matrix] Add OR and AND logical operator support for matrix (#172384)

fixes #172341

This change adds the `or` and `and` HLSL builtins with overloads for the
matrix types.

It also disables the logical operators from being used for HLSL 2021. To
keep this code from getting too complicated HLSL 2018 and lower logical
operator support was not added.
DeltaFile
+192-41clang/test/CodeGenHLSL/builtins/or.hlsl
+155-0clang/test/CodeGenHLSL/builtins/and_mat.hlsl
+67-4clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+32-1clang/lib/Sema/SemaHLSL.cpp
+32-0clang/test/SemaHLSL/BuiltIns/logical-mat-operator-errors.hlsl
+23-0clang/lib/Sema/SemaExpr.cpp
+501-464 files not shown
+539-4810 files

LLVM/project e77246dllvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/AArch64 select-costs.ll

[VPlan] Use predicate from VPValue VPWidenSelectR::computeCost. (#172915)

Instead of looking up the predicate from the VPValue condition instead
of the underlying IR.

This improves cost modeling in some cases, e.g. when we can fold
operations like negations in compares. On AArch64, this leads to
additional vectorization in a few cases in practice.

Example lowering for the modified test case:
https://llvm.godbolt.org/z/6nc6jo5eG

PR: https://github.com/llvm/llvm-project/pull/172915
DeltaFile
+4-4llvm/test/Transforms/LoopVectorize/AArch64/select-costs.ll
+2-3llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+6-72 files

LLVM/project cd13170libcxx/include flat_map flat_set, libcxx/test/std/containers/container.adaptors/flat.map/flat.map.modifiers insert_range_sorted_unique.pass.cpp

[libc++] Implement P3567R2 flat_meow fixes (#162022)

Fixes #171272

---------

Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
DeltaFile
+667-15libcxx/include/flat_map
+545-10libcxx/include/flat_set
+123-0libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.modifiers/insert_range_sorted_equivalent.pass.cpp
+121-0libcxx/test/std/containers/container.adaptors/flat.map/flat.map.modifiers/insert_range_sorted_unique.pass.cpp
+108-0libcxx/test/std/containers/container.adaptors/flat.multiset/flat.multiset.modifiers/insert_range_sorted_equivalent.pass.cpp
+108-0libcxx/test/std/containers/container.adaptors/flat.set/flat.set.modifiers/insert_range_sorted_unique.pass.cpp
+1,672-2523 files not shown
+1,833-11229 files

LLVM/project 611a271llvm/include/llvm/BinaryFormat GOFF.h, llvm/include/llvm/MC MCGOFFObjectWriter.h

[GOFF] Write out relocations in the GOFF writer (#167054)

Add support for writing relocations. Since the symbol numbering is only
available after the symbols are written, the relocations are collected
in a vector. At write time, the relocations are converted using the
symbols ids, compressed and written out. A relocation data record is
limited to 32K-1 bytes, which requires making sure that larger
relocation data is written into multiple records.
DeltaFile
+233-4llvm/lib/MC/GOFFObjectWriter.cpp
+46-1llvm/include/llvm/MC/MCGOFFObjectWriter.h
+12-12llvm/test/CodeGen/SystemZ/llvm.sincos.ll
+23-0llvm/include/llvm/BinaryFormat/GOFF.h
+18-5llvm/test/CodeGen/SystemZ/zos-section-1.ll
+21-0llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGOFFObjectWriter.cpp
+353-2210 files not shown
+412-5916 files