LLVM/project 6a99441compiler-rt/lib/sanitizer_common sanitizer_internal_defs.h

[NFCI][sanitizer_common] Realign #ifdefs in sanitizer_internal_defs.h (#186861)

Currently it is very hard to tell these nested ifdefs apart. This patch
fixes that, while trying to be as light-touch as possible.
DeltaFile
+6-6compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
+6-61 files

LLVM/project 015994bcompiler-rt/test/asan/TestCases stack_container_dynamic_lib.c

[ASan][test-only] Remove superfluous guards in stack_container_dynamic_lib.c (#188469)

As noted in https://github.com/llvm/llvm-project/pull/188406 comments,
the documentation recommends guarding only with
__has_feature(address_sanitizer). This patch updates the test to follow
the same pattern by removing the
__SANITIZER_DISABLE_CONTAINER_OVERFLOW__ checks. Having this macro
defined results in the common_interface_defs.h header defining the
contiguous container functions as no-ops anyway.

This is a followup to https://github.com/llvm/llvm-project/pull/188406.
DeltaFile
+4-8compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.c
+4-81 files

LLVM/project 07cce30llvm/test/tools/llvm-debuginfod-find headers-winhttp.test

Revert "[llvm] Attempt to re-enable llvm-debuginfod-find test on Windows bots" (#188935)

Reverts llvm/llvm-project#188810
DeltaFile
+10-1llvm/test/tools/llvm-debuginfod-find/headers-winhttp.test
+10-11 files

LLVM/project 5145d72llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp SPIRVGlobalRegistry.cpp, llvm/test/CodeGen/SPIRV/pointers PtrCast-in-OpSpecConstantOp.ll

[SPIR-V] Emit OpSpecConstantComposite for composites with spec constant operands (#188557)

- The SPIR-V spec requires that OpConstantComposite must not reference
spec constant operands. When a composite contains non-constant
constitued, OpSpecConstantComposite should be emitted instead of
OpConstantComposite
- Avoid creating function pointer types when the
SPV_INTEL_function_pointers extension is unavailable, falling back to i8
as the pointee type
- Re-enable spirv-val validation in tests that previously failed due to
this issue, and un-XFAIL the block_w_struct_return and global_block
transcoding tests

related to #60133
fixes #186756
DeltaFile
+27-2llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+11-10llvm/test/CodeGen/SPIRV/transcoding/global_block.ll
+9-10llvm/test/CodeGen/SPIRV/transcoding/block_w_struct_return.ll
+9-10llvm/test/CodeGen/SPIRV/pointers/PtrCast-in-OpSpecConstantOp.ll
+9-5llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+5-7llvm/test/CodeGen/SPIRV/transcoding/ConvertPtrInGlobalInit.ll
+70-444 files not shown
+80-6110 files

LLVM/project 8ab7b37openmp/cmake OpenMPTesting.cmake, openmp/runtime/test lit.cfg lit.site.cfg.in

[OpenMP][test] Remove %flags-use-compiler-omp-h (#188789)

With the standalone and project builds removed,
`OPENMP_TEST_COMPILER_HAS_OMP_H`/`config.test_compiler_has_omp_h` is set
to constant 1, which causes the `config.omp_header_directory` search
path NOT to be added to `%flags-use-compiler-omp-h`, causing the system
`omp.h` used, or the only test actually using it
(`omp50_taskdep_depobj.c`) failing if that one is not available.

The intention of `OPENMP_TEST_COMPILER_HAS_OMP_H` was to use gcc's
`omp.h` which declares `omp_depend_t` differently than our `omp.h`
(https://reviews.llvm.org/D108790). Using `OPENMP_TEST_C_COMPILER=gcc`
was used to test libomp's GOMP compatibility layer, but testing it is
currently unmaintained and has no buildbot (60 failing tests out of 389
with gcc-13, not including OMPD and OMPT). If updating testing for GOMP,
then gcc's own `omp.h` must be used for all tests: using the GOMP ABI
requires using GOMP's `omp.h`.

Closes: #187879
DeltaFile
+0-12openmp/runtime/test/lit.cfg
+1-1openmp/runtime/test/tasking/omp50_taskdep_depobj.c
+0-2openmp/cmake/OpenMPTesting.cmake
+0-1openmp/runtime/test/lit.site.cfg.in
+0-1openmp/runtime/test/CMakeLists.txt
+1-175 files

LLVM/project 88c5774llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/llvm-intrinsics bitreverse.ll bitreverse_small_type.ll

[SPIRV] Add bitreverse expansion for kernel (#186412)

The OpBitReverse is available when Shader or SPV_KHR_bit_instructions
extension is enabled. For targets without these capabilities, introduce
software emulation of G_BITREVERSE based on the parallel bit reversal
algorithm:
https://graphics.stanford.edu/~seander/bithacks.html#ReverseParallel

The emulation supports 8/16/32/64-bit scalars and vectors using bitwise
operations (shifts, AND, OR). A helper lambda avoids undefined behavior
when computing masks for 64-bit types.

Tests added for both emulation and native paths across all supported
types.

Assisted-by: Claude Code
DeltaFile
+395-0llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse.ll
+232-78llvm/test/CodeGen/SPIRV/llvm-intrinsics/bitreverse_small_type.ll
+81-13llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+708-913 files

LLVM/project 35781a7libclc/clc/include/clc/subgroup clc_sub_group_non_uniform_reduce_decl.inc clc_sub_group_non_uniform_reduce.h, libclc/clc/lib/amdgpu/subgroup clc_sub_group_non_uniform_reduce.cl clc_sub_group_reduce.cl

libclc: Partially implement nonuniform subgroup reduce functions (#188929)

For AMDGPU these are identical to the uniform case. Stub out the missing
cases with traps to avoid test failures from undefined symbols while
keeping the structure consistent.
DeltaFile
+384-0libclc/clc/lib/amdgpu/subgroup/clc_sub_group_non_uniform_reduce.cl
+8-134libclc/clc/lib/amdgpu/subgroup/clc_sub_group_reduce.cl
+48-0libclc/opencl/lib/generic/subgroup/sub_group_non_uniform_reduce.inc
+33-0libclc/clc/include/clc/subgroup/clc_sub_group_non_uniform_reduce_decl.inc
+30-0libclc/opencl/lib/generic/subgroup/sub_group_non_uniform_reduce.cl
+29-0libclc/clc/include/clc/subgroup/clc_sub_group_non_uniform_reduce.h
+532-1343 files not shown
+560-1349 files

LLVM/project 67b5715llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i64-stride-7.ll vector-interleaved-store-i64-stride-7.ll

Merge branch 'arm-fp-flt' into arm-fp-faddsub
DeltaFile
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,432-6,562llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+4,982-4,991llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,590-4,623llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+4,364-4,820llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+3,814-3,848llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+31,017-31,6425,677 files not shown
+289,135-131,5975,683 files

LLVM/project 45b21adllvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i64-stride-7.ll vector-interleaved-store-i64-stride-7.ll

Merge branch 'arm-fp-fix' into arm-fp-flt
DeltaFile
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,432-6,562llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+4,982-4,991llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,590-4,623llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+4,364-4,820llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+3,814-3,848llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+31,017-31,6425,677 files not shown
+289,135-131,5975,683 files

LLVM/project dce023ellvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i64-stride-7.ll vector-interleaved-store-i64-stride-7.ll

Merge branch 'arm-fp-f2d2f' into arm-fp-fix
DeltaFile
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,432-6,562llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+4,982-4,991llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,590-4,623llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+4,364-4,820llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+3,814-3,848llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+31,017-31,6425,677 files not shown
+289,135-131,5975,683 files

LLVM/project 584fe53llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i64-stride-7.ll vector-interleaved-store-i64-stride-7.ll

Merge branch 'arm-fp-fcmp' into arm-fp-f2d2f
DeltaFile
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,432-6,562llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+4,982-4,991llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,590-4,623llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+4,364-4,820llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+3,814-3,848llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+31,017-31,6425,677 files not shown
+289,135-131,5975,683 files

LLVM/project b046026llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i64-stride-7.ll vector-interleaved-store-i64-stride-7.ll

Merge branch 'arm-fp-dcmp' into arm-fp-fcmp
DeltaFile
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,432-6,562llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+4,982-4,991llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,590-4,623llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+4,364-4,820llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+3,814-3,848llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+31,017-31,6425,677 files not shown
+289,135-131,5975,683 files

LLVM/project 0f2c019llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i64-stride-7.ll vector-interleaved-store-i64-stride-7.ll

Merge branch 'arm-fp-dmuldiv' into arm-fp-dcmp
DeltaFile
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,432-6,562llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+4,982-4,991llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,590-4,623llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+4,364-4,820llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+3,814-3,848llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+31,017-31,6425,677 files not shown
+289,135-131,5975,683 files

LLVM/project b5c9babllvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i64-stride-7.ll vector-interleaved-store-i64-stride-7.ll

Merge branch 'arm-fp-daddsub' into arm-fp-dmuldiv
DeltaFile
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,432-6,562llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+4,982-4,991llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,590-4,623llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+4,364-4,820llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+3,814-3,848llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+31,017-31,6425,677 files not shown
+289,135-131,5975,683 files

LLVM/project 064877blibclc/clc/include/clc/subgroup clc_sub_group_non_uniform_reduce_decl.inc clc_sub_group_non_uniform_reduce.inc, libclc/clc/lib/amdgpu/subgroup clc_sub_group_non_uniform_reduce.inc

Address comments
DeltaFile
+0-87libclc/clc/lib/amdgpu/subgroup/clc_sub_group_non_uniform_reduce.inc
+33-0libclc/clc/include/clc/subgroup/clc_sub_group_non_uniform_reduce_decl.inc
+0-33libclc/clc/include/clc/subgroup/clc_sub_group_non_uniform_reduce.inc
+2-2libclc/clc/include/clc/subgroup/clc_sub_group_non_uniform_reduce.h
+35-1224 files

LLVM/project 9a4c6c0mlir/lib/Conversion/GPUToSPIRV GPUToSPIRV.cpp, mlir/test/Conversion/GPUToSPIRV broadcast.mlir

[mlir][spirv][gpu] Add lowering for gpu.subgroup_broadcast (#187947)

Add lowering for `gpu.subgroup_broadcast` and
`gpu.subgroup_broadcast_first` to `spirv.GroupNonUniformBroadcast` and
`spirv.GroupNonUniformBroadcastFirst`.

Fixes #157940
DeltaFile
+47-0mlir/test/Conversion/GPUToSPIRV/broadcast.mlir
+39-0mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
+86-02 files

LLVM/project 08c830aclang/lib/CIR/CodeGen CIRGenModule.cpp

remove MissingFeatures::opFuncSection
DeltaFile
+0-1clang/lib/CIR/CodeGen/CIRGenModule.cpp
+0-11 files

LLVM/project aeced07llvm/test/CodeGen/AMDGPU memintrinsic-unroll.ll, llvm/test/CodeGen/X86 vector-interleaved-load-i64-stride-7.ll vector-interleaved-store-i64-stride-7.ll

Merge remote-tracking branch 'upstream/main' into arm-fp-daddsub
DeltaFile
+6,835-6,798llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,432-6,562llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
+4,982-4,991llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
+4,590-4,623llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+4,364-4,820llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+3,814-3,848llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
+31,017-31,6425,677 files not shown
+289,135-131,5975,683 files

LLVM/project 9b44b22llvm/test/tools/llvm-debuginfod-find headers-winhttp.test

Revert "[llvm] Attempt to re-enable llvm-debuginfod-find test on Windows bots…"

This reverts commit 906912d752e5d6e53de0665df67cc40a83ca2091.
DeltaFile
+10-1llvm/test/tools/llvm-debuginfod-find/headers-winhttp.test
+10-11 files

LLVM/project 286909allvm/include/llvm/IR PatternMatch.h, llvm/unittests/IR PatternMatch.cpp

PatternMatch: Add matchers for positive or negative infinity

The existing m_Inf deceptively matches both positive and negative
infinities. Add variants that match the specific sign.
DeltaFile
+18-0llvm/include/llvm/IR/PatternMatch.h
+6-0llvm/unittests/IR/PatternMatch.cpp
+24-02 files

LLVM/project 93e475aclang-tools-extra/clang-tidy/modernize UseStdPrintCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Add missing #include insertion in macros for modernize-use-std-print (#188394)

Follow-up of: #188247

---------

Co-authored-by: Victor Chernyakin <chernyakin.victor.j at outlook.com>
DeltaFile
+12-0clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-print-macro.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+2-1clang-tools-extra/clang-tidy/modernize/UseStdPrintCheck.cpp
+19-13 files

LLVM/project eac6467llvm/lib/Transforms/Scalar NaryReassociate.cpp

review: address suggestions
DeltaFile
+21-29llvm/lib/Transforms/Scalar/NaryReassociate.cpp
+21-291 files

LLVM/project bf65765llvm/include/llvm/Transforms/Scalar NaryReassociate.h, llvm/lib/Transforms/Scalar NaryReassociate.cpp

[NaryReassociate] Make uniformity-aware to prefer grouping uniform values
DeltaFile
+96-3llvm/lib/Transforms/Scalar/NaryReassociate.cpp
+5-5llvm/test/Transforms/NaryReassociate/AMDGPU/nary-add-uniform.ll
+6-3llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+3-1llvm/include/llvm/Transforms/Scalar/NaryReassociate.h
+110-124 files

LLVM/project 4b715b3libclc/clc/include/clc/subgroup clc_sub_group_non_uniform_reduce.inc, libclc/clc/lib/amdgpu/subgroup clc_sub_group_non_uniform_reduce.cl clc_sub_group_reduce.cl

libclc: Partially implement nonuniform subgroup reduce functions

For AMDGPU these are identical to the uniform case. Stub out the missing
cases with traps to avoid test failures from undefined symbols while keeping
the structure consistent.
DeltaFile
+384-0libclc/clc/lib/amdgpu/subgroup/clc_sub_group_non_uniform_reduce.cl
+8-134libclc/clc/lib/amdgpu/subgroup/clc_sub_group_reduce.cl
+87-0libclc/clc/lib/amdgpu/subgroup/clc_sub_group_non_uniform_reduce.inc
+48-0libclc/opencl/lib/generic/subgroup/sub_group_non_uniform_reduce.inc
+33-0libclc/clc/include/clc/subgroup/clc_sub_group_non_uniform_reduce.inc
+30-0libclc/opencl/lib/generic/subgroup/sub_group_non_uniform_reduce.cl
+590-1344 files not shown
+647-13410 files

LLVM/project 40984c6llvm/test/Transforms/NaryReassociate/AMDGPU nary-add-uniform.ll

[NaryReassociate][AMDGPU] Pre-commit test for uniformity-aware reassociation (NFC)
DeltaFile
+319-0llvm/test/Transforms/NaryReassociate/AMDGPU/nary-add-uniform.ll
+319-01 files

LLVM/project 56e1510libclc/clc/include/clc clc_target_defines.h, libclc/clc/include/clc/collective clc_work_group_scan_decl.inc clc_work_group_scan.h

libclc: Add work group scan functions (#188829)
DeltaFile
+155-0libclc/clc/lib/generic/collective/clc_work_group_scan.inc
+41-0libclc/opencl/lib/generic/collective/work_group_scan.inc
+38-0libclc/clc/lib/generic/collective/clc_work_group_scan.cl
+25-0libclc/clc/include/clc/collective/clc_work_group_scan_decl.inc
+23-0libclc/clc/include/clc/clc_target_defines.h
+20-0libclc/clc/include/clc/collective/clc_work_group_scan.h
+302-03 files not shown
+319-09 files

LLVM/project 5c0c421clang/lib/Serialization ASTWriterStmt.cpp ASTReaderStmt.cpp, clang/test/ASTMerge/generic-selection-expr test-type.c

Support Serializing/Deserializing Extended Generic Selection Expressions

Clang supports using a type as the predicate for generic selection
expressions but lacked support for serializing/deserializing these
extended generic selection expressions.

Signed-off-by: Will Hawkins <hawkinsw at obs.cr>
DeltaFile
+13-5clang/lib/Serialization/ASTWriterStmt.cpp
+6-5clang/lib/Serialization/ASTReaderStmt.cpp
+4-0clang/test/ASTMerge/generic-selection-expr/Inputs/generic-type.c
+3-0clang/test/ASTMerge/generic-selection-expr/test-type.c
+26-104 files

LLVM/project 62ed3fcllvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak-zero-siv-delta-signed-min.ll

[DA] Stop negating Delta in the Weak Zero SIV test
DeltaFile
+6-6llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-delta-signed-min.ll
+0-12llvm/lib/Analysis/DependenceAnalysis.cpp
+6-182 files

LLVM/project d1b241allvm/lib/Analysis DependenceAnalysis.cpp

[DA] Remove absolute value calculations in the Weak Zero SIV tests
DeltaFile
+7-7llvm/lib/Analysis/DependenceAnalysis.cpp
+7-71 files

LLVM/project cf542a3lldb/bindings/python python-wrapper.swig

[lldb] use the Py_REFCNT() macro instead of directly accessing member (#188161)

[PyObject members are not to be accessed
directly](https://docs.python.org/3/c-api/structures.html#c.PyObject),
but rather through macros, in this case `Py_REFCNT()`.

In most, ie Global Interpreter Lock-enabled, CPython cases,
`Py_REFCNT()` expands to accessing `ob_refcnt` anyway. However, in a
free-threaded CPython, combined with disabling the limited API (since it
requires the GIL for now), the direct member does not exist, causing the
build to fail. The macro expands to the correct access method in the
free-threaded configuration.

(cherry picked from commit 2a7b0f06d2060dbab8fa38fae7689f2d9048fa9d)
DeltaFile
+1-1lldb/bindings/python/python-wrapper.swig
+1-11 files