LLVM/project 4a773b9llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp SPIRVTargetMachine.cpp, llvm/test/CodeGen/SPIRV loop-unroll-nonshader.ll llc-pipeline.ll

[SPIR-V] Emit OpLoopMerge for non-shader targets without SPV_INTEL_unstructured_loop_controls extension (#187519)

`OpLoopMerge` emission was not supported due to the fact that spirv
structurizer is not being run for non-shader targets.

After enabling support for `SPV_INTEL_unstructured_loop_controls` in
https://github.com/llvm/llvm-project/pull/178799 is started to preserve
some information about unstructured control flow. This PR is intended to
enable support for `OpLoopMerge` without extension.

Note: changes in `llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll`
and `llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll` are due to the
fact that loop layout has changed after `loop-simplify` pass enabling
DeltaFile
+169-0llvm/test/CodeGen/SPIRV/loop-unroll-nonshader.ll
+50-17llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+13-8llvm/test/CodeGen/SPIRV/pointers/phi-chain-types.ll
+9-3llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll
+6-0llvm/test/CodeGen/SPIRV/llc-pipeline.ll
+4-0llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+251-286 files

LLVM/project 25fee95mlir/lib/Target/SPIRV/Deserialization Deserializer.cpp

[MLIR] Apply clang-tidy fixes for modernize-loop-convert in Deserializer.cpp (NFC)
DeltaFile
+1-4mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
+1-41 files

LLVM/project dfc866cmlir/lib/Dialect/SparseTensor/Transforms SparseTensorRewriting.cpp

[MLIR] Apply clang-tidy fixes for bugprone-argument-comment in SparseTensorRewriting.cpp (NFC)
DeltaFile
+1-1mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp
+1-11 files

LLVM/project 1ac60cemlir/lib/Dialect/Arith/Transforms ShardingInterfaceImpl.cpp

[MLIR] Apply clang-tidy fixes for performance-unnecessary-copy-initialization in ShardingInterfaceImpl.cpp (NFC)
DeltaFile
+2-2mlir/lib/Dialect/Arith/Transforms/ShardingInterfaceImpl.cpp
+2-21 files

LLVM/project 4991abemlir/test/lib/Dialect/Shard TestReshardingPartition.cpp

[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in TestReshardingPartition.cpp (NFC)
DeltaFile
+2-2mlir/test/lib/Dialect/Shard/TestReshardingPartition.cpp
+2-21 files

LLVM/project b50d5admlir/lib/Conversion/LLVMCommon TypeConverter.cpp

[MLIR] Apply clang-tidy fixes for llvm-else-after-return in TypeConverter.cpp (NFC)
DeltaFile
+2-1mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
+2-11 files

LLVM/project 4284629llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen TargetLoweringBase.cpp

feedback

Created using spr 1.3.8-wip
DeltaFile
+4-2llvm/include/llvm/CodeGen/TargetLowering.h
+1-1llvm/lib/CodeGen/TargetLoweringBase.cpp
+5-32 files

LLVM/project 84d6359llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/test/MC/AArch64 armv9a-tlbip.s

[AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases

Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.

The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.

Update testcases accordingly.
DeltaFile
+92-61llvm/lib/Target/AArch64/AArch64SystemOperands.td
+8-9llvm/test/MC/AArch64/armv9a-tlbip.s
+100-702 files

LLVM/project f85b033llvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! Refactor TLBI tablegen
DeltaFile
+233-120llvm/lib/Target/AArch64/AArch64SystemOperands.td
+233-1201 files

LLVM/project d7b933allvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! Change tablegen as suggested
DeltaFile
+52-30llvm/lib/Target/AArch64/AArch64SystemOperands.td
+52-301 files

LLVM/project c18113allvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! More optimisations
DeltaFile
+121-133llvm/lib/Target/AArch64/AArch64SystemOperands.td
+121-1331 files

LLVM/project dc4dd5fllvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! Another tablegen optimisation
DeltaFile
+117-185llvm/lib/Target/AArch64/AArch64SystemOperands.td
+117-1851 files

LLVM/project d06dd50llvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! More tablegen fixes
DeltaFile
+31-69llvm/lib/Target/AArch64/AArch64SystemOperands.td
+31-691 files

LLVM/project 2690ac1llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/test/MC/AArch64 armv8.7a-xs.s armv9.5a-tlbiw.s

fixup! Move nxs bit into TLBIEntry rather than override
DeltaFile
+57-56llvm/test/MC/AArch64/armv8.7a-xs.s
+21-33llvm/lib/Target/AArch64/AArch64SystemOperands.td
+10-10llvm/test/MC/AArch64/armv9.5a-tlbiw.s
+88-993 files

LLVM/project 3017075llvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! One more small optimisation
DeltaFile
+4-6llvm/lib/Target/AArch64/AArch64SystemOperands.td
+4-61 files

LLVM/project 53e7f9allvm/lib/Transforms/Vectorize VPlanRecipes.cpp

[VPlan] Generalize header-phi detection in VPPhi::execute. (NFC) (#189352)

Generalize the header-phi detection in VPPhi::execute to use VPDT.

This is currently NFC, but is needed to use VPPhi also for dissolving
replicate regions (https://github.com/llvm/llvm-project/pull/186252).

Split off from approved https://github.com/llvm/llvm-project/pull/186252
as suggested.

PR: https://github.com/llvm/llvm-project/pull/189352
DeltaFile
+5-3llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+5-31 files

LLVM/project 7fb4f73polly/include/polly ScopInfo.h, polly/lib/Analysis ScopBuilder.cpp

[Polly] Avoid __builtin_assume circular context reasoning (#189350)

The conversion of SCEVs to isl::pw_aff may only be valid under
conditions that have to be confirmed via RTC. This also happens with
__builtin_assume. These user-added assumptions are then added to
ScopInfo::Context. However, the conclusion in ScopInfo::Context is then
also used to simplify ("gist") its own RTC preconditions in
ScopInfo::AssumedContext and ScopInfo::InvalidContext away.

Avoid by adding user assumptions with preconditions to
ScopInfo::DefinedBehaviourContext instead, which is not used to simplify
AssumedContext/InvalidContext.

Fixes #187922

Thanks @thapgua for the report
DeltaFile
+155-0polly/test/ScopInfo/issue187922.ll
+14-3polly/lib/Analysis/ScopBuilder.cpp
+6-4polly/test/ScopInfo/user_provided_assumptions.ll
+3-1polly/include/polly/ScopInfo.h
+178-84 files

LLVM/project bfac1d8llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen TargetLoweringBase.cpp

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+5-15llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+8-0llvm/include/llvm/CodeGen/TargetLowering.h
+7-0llvm/lib/CodeGen/TargetLoweringBase.cpp
+20-153 files

LLVM/project e901b02llvm/lib/Transforms/Utils BasicBlockUtils.cpp, llvm/unittests/Transforms/Utils BasicBlockUtilsTest.cpp

[BasicBlockUtils] Fixed LoopInfo update in UpdateAnalysisInformation() (#177147)

SplitLandingPadPredecessors() results in an irreducible loop
and makes LoopInfo invalid. Verification results in a crash:
Assertion `CB != OutsideLoopPreds[i] && "Loop has multiple entry
points!"' failed.

Created a new test with a broken LoopInfo after
SplitLandingPadPredecessors().
The test @split-lp-predecessors-test() after
SplitBlockPredecessors(catch_dest, { loop }, "", DT, LI) changes to
the following IR where the loop {%catch_dest} gets into irreducible
loop {%catch_dest.split-lp, %catch_dest}:

```
define void @split-lp-predecessors-test() personality ptr null {
entry:
  invoke void @foo()
          to label %loop unwind label %catch_dest.split-lp

    [32 lines not shown]
DeltaFile
+92-0llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp
+18-2llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+110-22 files

LLVM/project c7908d3llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP][NFC]Use passing-by-ref in the range based loop to prevent warnings/errors
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1-11 files

LLVM/project 4d3759dllvm/lib/Transforms/InstCombine InstCombineMulDivRem.cpp, llvm/test/Transforms/InstCombine fmul.ll

[InstCombine] Fold X * ldexp(1.0, Y) -> ldexp(X, Y). (#188493)

This would avoid the FMUL in sequences such as
[these](https://godbolt.org/z/xhqfe5sb1).
DeltaFile
+109-0llvm/test/Transforms/InstCombine/fmul.ll
+9-0llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+118-02 files

LLVM/project e6c89e8llvm/lib/TableGen Record.cpp, llvm/test/TableGen intrinsic-arginfo-error.td

[TableGen] Improve the error report of getElementAsRecord (#189302)
DeltaFile
+10-0llvm/test/TableGen/intrinsic-arginfo-error.td
+2-1llvm/lib/TableGen/Record.cpp
+12-12 files

LLVM/project 65cb5c3clang/include/clang/Basic BuiltinsX86.td, clang/lib/Headers emmintrin.h

[clang][x86] Fix the return type of the cvtpd2dq builtin (#189254)

The CVTPD2DQ instruction converts packed 64-bit floating-point values to
packed 32-bit signed integer values. This patch fixes the return type of
the corresponding builtin, which previously returned a vector of two
64-bit signed integers. The new behavior is in line with the return type
of the CVTTPD2DQ builtin.
DeltaFile
+1-1clang/include/clang/Basic/BuiltinsX86.td
+1-1clang/lib/Headers/emmintrin.h
+1-1clang/test/CodeGen/builtins-x86.c
+3-33 files

LLVM/project 2b41985llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp SelectionDAG.cpp

[DAG] Fix incorrect ForSigned handling in computeConstantRange calls (#188889)

Fix two places where ForSigned was incorrectly passed to
computeConstantRange, causing wrong signed/unsigned range computation.

In computeConstantRangeIncludingKnownBits (DemandedElts overload),
the call omitted ForSigned, so Depth (unsigned) was implicitly
converted to bool for the ForSigned parameter. Introduced in
a6a66a4e6915.

In visitIMINMAX, the call always passed ForSigned=false, even when
folding SMAX/SMIN which query signed bounds from the resulting range.
DeltaFile
+2-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+1-1llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+3-22 files

LLVM/project 6c8782bmlir/lib/Dialect/Vector/Transforms VectorDistribute.cpp

[MLIR][Vector] Fix direct operand.set() bypassing rewriter in WarpOpScfIfOp/ForOp (#188948)

In WarpOpScfIfOp and WarpOpScfForOp, the walk that updates users of
escaping values (after moving them to the inner WarpOp) was calling
operand.set() directly, bypassing the rewriter API. This causes the
MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS fingerprint check to fail.

Fix by wrapping the operand updates with rewriter.modifyOpInPlace().

Assisted-by: Claude Code
Fix a failure present with MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON.
DeltaFile
+20-2mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
+20-21 files

LLVM/project 0bb0c7dmlir/lib/Dialect/MPI/IR MPIOps.cpp

[MLIR][MPI] Fix direct getRefMutable().assign() bypassing rewriter in FoldCast (#188943)

The FoldCast canonicalization pattern was calling
op.getRefMutable().assign(src) directly, bypassing the rewriter. This
violates the pattern API contract and causes fingerprint change failures
when
MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS is enabled. Wrap the
modification with b.modifyOpInPlace() to properly notify the rewriter of
the changes.

Assisted-by: Claude Code
Fix a failure present with MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON.
DeltaFile
+1-1mlir/lib/Dialect/MPI/IR/MPIOps.cpp
+1-11 files

LLVM/project ccb64cbmlir/include/mlir/IR Value.h BlockSupport.h, mlir/lib/IR Value.cpp

[Value] Mark getOperandNumber as Const (#189267)
DeltaFile
+2-2mlir/lib/IR/Value.cpp
+1-1mlir/include/mlir/IR/Value.h
+1-1mlir/include/mlir/IR/BlockSupport.h
+4-43 files

LLVM/project 9e7e955llvm/lib/Target/AArch64/MCTargetDesc AArch64InstPrinter.cpp

fixup! Improve printing code for tabs and commas
DeltaFile
+5-8llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+5-81 files

LLVM/project d3f1e0dllvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp SPIRVPostLegalizer.cpp, llvm/test/CodeGen/SPIRV/instructions phi-aggregate-loop.ll

[SPIR-V] Fix aggregate PHI type mismatch in loops (#186086)
DeltaFile
+112-0llvm/test/CodeGen/SPIRV/instructions/phi-aggregate-loop.ll
+37-1llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+9-6llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+3-1llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+161-84 files

LLVM/project 53335d4llvm/test/MC/AArch64 armv9.4a-gcs.s arm64-aliases.s

fixup! Move new tests into arm64-aliases.s
DeltaFile
+0-40llvm/test/MC/AArch64/armv9.4a-gcs.s
+32-0llvm/test/MC/AArch64/arm64-aliases.s
+25-0llvm/test/MC/AArch64/armv9a-sysp-pairs.s
+2-6llvm/test/MC/AArch64/brbe.s
+0-5llvm/test/MC/AArch64/armv8.9a-debug-pmu.s
+0-5llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
+59-566 files