LLVM/project 2634a2bclang/include/clang/Frontend CompilerInstance.h, clang/lib/CodeGen BackendUtil.cpp

Revert "[LLVM][NFC] Move PassPlugin from Passes to Extensions lib" and subsequent commit

This reverts commit d87b47d3a893b849cfd1ee5309b9fec2b0aec8cd.
This reverts commit f7ed3d44a198bfe689a1aa284452e875d5bb8a55.
DeltaFile
+142-0llvm/include/llvm/Passes/PassPlugin.h
+0-142llvm/include/llvm/Extensions/PassPlugin.h
+49-0llvm/lib/Passes/PassPlugin.cpp
+0-49llvm/lib/Extensions/PassPlugin.cpp
+11-4clang/lib/CodeGen/BackendUtil.cpp
+0-12clang/include/clang/Frontend/CompilerInstance.h
+202-20734 files not shown
+225-26640 files

LLVM/project 3cfe144lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime AppleObjCClassDescriptorV2.cpp AppleObjCClassDescriptorV2.h

[lldb] Use ReadCStringsFromMemory to speed-up AppleObjCClassDescriptorV2::method_t lookup (#172031)

With this improvement, compiling a simple Objective-C program like:

```
int main() {
    @autoreleasepool {
        NSDictionary *mapping = @{ @"one": @1, @"two": @2, @"three": @3 };
        return 0; //breakhere
    }
}
```

And running `expr -O -- mapping[@"one"]`, we can observe the following
packet count for the expression evaluation:

```
Before:
  multi mem read ($MultiMemRead)        :    94

    [12 lines not shown]
DeltaFile
+24-7lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.cpp
+4-0lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.h
+28-72 files

LLVM/project 80bc071llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 arm64-cvtf-simd-intrinsics.ll

[AArch64][llvm] Add codegen for simd fpcvt intrinsics

Add tablegen patterns to provide codegen for SCVTF and UCVTF
operating purely on SIMD & FP registers, using explicit bitcasts.
DeltaFile
+30-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+10-17llvm/test/CodeGen/AArch64/arm64-cvtf-simd-intrinsics.ll
+40-172 files

LLVM/project 9c77705mlir/docs LangRef.md, mlir/docs/DefiningDialects Assembly.md

Dialect alias docs and allow disabling

Signed-off-by: Fabian Mora <fmora.dev at gmail.com>
DeltaFile
+56-0mlir/docs/DefiningDialects/Assembly.md
+35-1mlir/docs/LangRef.md
+24-1mlir/lib/IR/AsmPrinter.cpp
+10-0mlir/include/mlir/IR/OperationSupport.h
+2-0mlir/test/IR/print-attr-type-dialect-aliases.mlir
+127-25 files

LLVM/project ec18557lldb/test/API/commands/platform/launchgdbserver TestPlatformLaunchGDBServer.py

[lldb][windows] skip TestPlatformProcessLaunchGDBServer.test_launch_with_unusual_process_name (#173250)

This patch skips
TestPlatformProcessLaunchGDBServer.test_launch_with_unusual_process_name
on Windows which is flaky.

The test will be reenabled once it has been fixed.
DeltaFile
+1-0lldb/test/API/commands/platform/launchgdbserver/TestPlatformLaunchGDBServer.py
+1-01 files

LLVM/project 2c841b7llvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU rsq.f64.ll amdgpu-codegenprepare-fdiv.f64.ll

AMDGPU: Introduce f64 rsq pattern in AMDGPUCodeGenPrepare (#172053)

DeltaFile
+4,532-3,195llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+306-56llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
+131-12llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+4,969-3,2633 files

LLVM/project 9008922llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer crash_exceed_scheduling.ll extract-many-users-buildvector.ll

Revert "[SLP]Enable float point math ops as copyables elements."

This reverts commit e644f06c2ffc23b3415f3478b05c627303aef614 to fix
crashes found during internal testing
DeltaFile
+46-92llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
+102-26llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
+20-60llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+38-34llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
+26-18llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
+20-20llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
+252-25013 files not shown
+338-34119 files

LLVM/project a281656llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Revert "[SLP][NFC]Add parens to silence a warning message, NFC"

This reverts commit 366f6eb607dab74b7be28d3bd72736273329d647.
DeltaFile
+10-10llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+10-101 files

LLVM/project 37e3641flang/docs DebugGeneration.md

[Flang][Docs] Formatting change (#173257)

The flang.llvm.org page listed two entries (Testing, Resources) from the
Debug generation document in the table of contents. Change the
formatting to only include the top-level title.
DeltaFile
+2-2flang/docs/DebugGeneration.md
+2-21 files

LLVM/project 153ece5llvm/test/CodeGen/AArch64 arm64-vshift.ll

[AArch64][GlobalISel] Added test coverage for sri intrinsic

Previously, generation of sri intrinsics was tested during the ACLE -> IR stage, but not in the IR -> MIR stage. Now, correct generation of sri intrinsics is tested in both stages.
DeltaFile
+110-6llvm/test/CodeGen/AArch64/arm64-vshift.ll
+110-61 files

LLVM/project ed9b903llvm/lib/Target/AArch64 AArch64InstrGISel.td, llvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp AArch64RegisterBankInfo.cpp

[AArch64][GlobalISel] Added support for sri intrinsic
DeltaFile
+8-0llvm/lib/Target/AArch64/AArch64InstrGISel.td
+7-0llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+2-0llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+17-03 files

LLVM/project c515914llvm/lib/Target/AArch64 SVEInstrFormats.td, llvm/test/CodeGen/AArch64 sve-lrint.ll sve-llrint.ll

[AArch64][SVE] Add MOVPRFX hints for unary undef pseudos. (#173031)

Extend the hints added in #166926 to unary pseudos with undef inactive
lanes.
DeltaFile
+200-209llvm/test/CodeGen/AArch64/sve-lrint.ll
+200-209llvm/test/CodeGen/AArch64/sve-llrint.ll
+160-167llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+38-41llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+34-43llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
+34-34llvm/lib/Target/AArch64/SVEInstrFormats.td
+666-7035 files not shown
+714-75611 files

LLVM/project 945cc50llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 fma-fneg-combine-3.ll

[X86] isFNEG - add concat_vectors(fneg(x),fneg(y)) -> concat_vectors(x,y) handling (#173255)

Fixes #173172
DeltaFile
+32-68llvm/test/CodeGen/X86/fma-fneg-combine-3.ll
+13-0llvm/lib/Target/X86/X86ISelLowering.cpp
+45-682 files

LLVM/project b380116llvm/test/CodeGen/AArch64 arm64-cvtf-simd-intrinsics.ll

[AArch64][llvm] Pre-commit tests for new fpcvt codegen
DeltaFile
+90-0llvm/test/CodeGen/AArch64/arm64-cvtf-simd-intrinsics.ll
+90-01 files

LLVM/project caf649fllvm/test/CodeGen/SPIRV ga-gep.ll ga-inttoptr.ll

Replace test.
DeltaFile
+0-13llvm/test/CodeGen/SPIRV/ga-gep.ll
+11-0llvm/test/CodeGen/SPIRV/ga-inttoptr.ll
+11-132 files

LLVM/project e5551a6mlir/lib/Dialect/MemRef/IR MemRefOps.cpp, mlir/test/Dialect/MemRef canonicalize.mlir

[mlir][memref] memref.view canonicalizations fixes (#173237)

* Do not fold if offset is not zero
* Remove unnecessary alloc check
DeltaFile
+36-5mlir/test/Dialect/MemRef/canonicalize.mlir
+10-13mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
+46-182 files

LLVM/project f512576llvm/utils/gn/secondary/clang-tools-extra/clang-change-namespace BUILD.gn, llvm/utils/gn/secondary/clang/lib/Frontend BUILD.gn

[gn] fix mistake from 2815358c68ddd
DeltaFile
+0-1llvm/utils/gn/secondary/clang-tools-extra/clang-change-namespace/BUILD.gn
+1-0llvm/utils/gn/secondary/clang/lib/Frontend/BUILD.gn
+1-12 files

LLVM/project 2815358llvm/utils/gn/secondary/clang-tools-extra/clang-change-namespace BUILD.gn

[gn] port f7ed3d44a198b more

This should've been in f5472798bed718b7.
DeltaFile
+1-0llvm/utils/gn/secondary/clang-tools-extra/clang-change-namespace/BUILD.gn
+1-01 files

LLVM/project 9086571llvm/test/CodeGen/RISCV short-forward-branch-opt-load.ll short-forward-branch-opt-load-atomic-acquire-seq_cst.ll, llvm/test/tools/llvm-mca/AArch64/Olympus sve-instructions.s neon-instructions.s

rebase + make test more precise

Created using spr 1.3.5-bogner
DeltaFile
+10,680-0llvm/test/tools/llvm-mca/AArch64/Olympus/sve-instructions.s
+6,871-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-load.ll
+5,310-0llvm/test/tools/llvm-mca/AArch64/Olympus/neon-instructions.s
+3,983-0llvm/test/tools/llvm-mca/AArch64/Olympus/writeback-loads-stores.s
+3,834-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-load-atomic-acquire-seq_cst.ll
+3,801-0llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s
+34,479-02,213 files not shown
+126,286-33,9362,219 files

LLVM/project 5889beellvm/test/CodeGen/RISCV short-forward-branch-opt-load.ll short-forward-branch-opt-load-atomic-acquire-seq_cst.ll, llvm/test/tools/llvm-mca/AArch64/Olympus sve-instructions.s neon-instructions.s

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5-bogner

[skip ci]
DeltaFile
+10,680-0llvm/test/tools/llvm-mca/AArch64/Olympus/sve-instructions.s
+6,871-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-load.ll
+5,310-0llvm/test/tools/llvm-mca/AArch64/Olympus/neon-instructions.s
+3,983-0llvm/test/tools/llvm-mca/AArch64/Olympus/writeback-loads-stores.s
+3,834-0llvm/test/CodeGen/RISCV/short-forward-branch-opt-load-atomic-acquire-seq_cst.ll
+3,801-0llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s
+34,479-02,212 files not shown
+126,283-33,9332,218 files

LLVM/project 7863604llvm/utils/gn/secondary/clang/lib/CodeGen BUILD.gn, llvm/utils/gn/secondary/llvm/tools/bugpoint BUILD.gn

[gn] port 8f766e382b77 more

This should've been in ae23bd3577e8904.
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/tools/opt/BUILD.gn
+1-0llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/tools/bugpoint/BUILD.gn
+3-03 files

LLVM/project a0a637cllvm/utils/gn/secondary/llvm/lib/Extensions BUILD.gn, llvm/utils/gn/secondary/llvm/lib/Passes BUILD.gn

[gn build] Port d87b47d3a893
DeltaFile
+4-1llvm/utils/gn/secondary/llvm/lib/Extensions/BUILD.gn
+0-1llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/tools/llvm-lto2/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/unittests/Passes/Plugins/BUILD.gn
+8-21 files not shown
+9-27 files

LLVM/project f547279llvm/utils/gn/secondary/clang/test BUILD.gn

[gn] port f7ed3d44a198b
DeltaFile
+1-0llvm/utils/gn/secondary/clang/test/BUILD.gn
+1-01 files

LLVM/project e47b109lldb/include/lldb/Target Process.h, lldb/source/Target Process.cpp

[lldb] Add ReadCStrings API to Process (#172026)

This commit uses Process::ReadMemoryRanges to create an efficient method
for reading multiple strings at once. This method works like the
single-string version, reading 256 bytes at a time, but instead doing it
for _every_ string requested at the same time.
DeltaFile
+73-0lldb/unittests/Target/MemoryTest.cpp
+57-1lldb/source/Target/Process.cpp
+3-0lldb/include/lldb/Target/Process.h
+133-13 files

LLVM/project 57ea81cllvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

ValueTracking: Avoid calling computeKnownFPClass on matched constant

The fmul case already tries to match a literal value, we don't
need to match it twice.
DeltaFile
+6-4llvm/lib/Analysis/ValueTracking.cpp
+4-0llvm/include/llvm/Support/KnownFPClass.h
+4-0llvm/lib/Support/KnownFPClass.cpp
+14-43 files

LLVM/project ab51313llvm/lib/Analysis ValueTracking.cpp, llvm/test/CodeGen/AMDGPU fold-fabs.ll

ValueTracking: Improve computeKnownFPClass fmul handling

Improve known non-nan sign bit tracking. Handle cases with
a known 0 or inf input of indeterminate sign.

The tails of some library functions have sign management
for special cases.
DeltaFile
+35-35llvm/test/Transforms/Attributor/nofpclass-fmul.ll
+33-12llvm/lib/Analysis/ValueTracking.cpp
+1-3llvm/test/Transforms/InstCombine/fpcast.ll
+1-2llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
+1-1llvm/test/Transforms/Attributor/nofpclass-nan-fmul.ll
+0-1llvm/test/CodeGen/AMDGPU/fold-fabs.ll
+71-546 files

LLVM/project 20ff83ellvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU rsq.f32-safe.ll amdgpu-codegenprepare-fdiv.ll

AMDGPU: Stop requiring afn for f32 rsq formation

We were checking for afn or !fpmath attached to the sqrt. We
are not trying to replace a correctly rounded rsqrt; we're replacing
the two correctly rounded operations with the contracted operation.
It's net a better precision, so contract on both instructions should
be sufficient. Both the contracted and uncontracted sequences pass
the OpenCL conformance test, with a lower maximum error contracted.
DeltaFile
+504-1,529llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
+52-45llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
+6-25llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+562-1,5993 files

LLVM/project 59bb680llvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp

neg rsq comment
DeltaFile
+5-0llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+5-01 files

LLVM/project 2227f62llvm/test/CodeGen/AMDGPU rsq.f64.ll amdgpu-codegenprepare-fdiv.f64.ll

Regenerate checks
DeltaFile
+188-188llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+71-76llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
+259-2642 files

LLVM/project f7ce96allvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp

Commute to canonical
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+2-21 files