LLVM/project 2042987clang/lib/Driver Driver.cpp

clang: Remove extra space and braces in flang check (#208714)
DeltaFile
+1-2clang/lib/Driver/Driver.cpp
+1-21 files

LLVM/project f77162dclang/include/clang/Driver Job.h, clang/lib/Driver Compilation.cpp Driver.cpp

[Clang][Driver] Parallelize device cc1 jobs for offload arches

[Clang][Driver] Parallelize device cc1 jobs for offload arches

Large offload builds can target many device architectures. A common
ROCm build can target around ten `--offload-arch=` values. For a large
single translation unit, the offload device cc1 work before
clang-linker-wrapper can become a build-time bottleneck. Those
per-architecture jobs are independent, but the driver ran them serially,
so `--offload-jobs=` only helped the later wrapper work.

Borrow the parallel job mechanism used by clang-linker-wrapper for the
pre-wrapper device cc1 jobs. Device job construction marks eligible
compile and backend jobs with an offload parallel group. The generic
executor only consumes that opt-in metadata for adjacent device jobs
with distinct bound architectures.

The parallel path is disabled for driver-side output modes and callbacks
so existing serial output handling is preserved. This is NFC for
non-offload compilation.
DeltaFile
+154-2clang/lib/Driver/Compilation.cpp
+64-0clang/lib/Driver/Driver.cpp
+9-13clang/lib/Driver/ToolChains/Clang.cpp
+21-0clang/test/Driver/offload-parallel-device-cc1.cu
+16-0clang/lib/Driver/ToolChains/CommonArgs.cpp
+12-2clang/include/clang/Driver/Job.h
+276-171 files not shown
+289-177 files

LLVM/project b3da6d2llvm/lib/Target/AArch64 AArch64MIPeepholeOpt.cpp, llvm/test/CodeGen/AArch64 redundant-orrwrs-from-zero-extend.mir

AArch64: Fix mishandling subregister in orr peephole (#208015)

Avoids verifier failure regressions in a future change.
DeltaFile
+21-0llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir
+3-0llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+24-02 files

LLVM/project 90f9ee6llvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU packed_shl64_combine.ll

[AMDGPU] Make `(v2i32 (trunc v2i64:$a))` legal (#207761)

`performShlCombine` introduced a `v2i32 truncate x:v2i64`. This
pattern is not legal, and is normally expanded by the legalizer.

However, since the combine is done after legalization the illegal
pattern remains.

This happens on `gfx1251` since it has legal `shl v2i64` instructions
(due to `PackedU64Ops`).

This patch introduces a legal pattern for `v2i32 truncate x:v2i64`.
DeltaFile
+162-0llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
+14-0llvm/lib/Target/AMDGPU/SIInstructions.td
+176-02 files

LLVM/project 0911e6dllvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp SPIRVNonSemanticDebugHandler.h

[review] Simplify code for scope path handling.
DeltaFile
+23-8llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+10-0llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+33-82 files

LLVM/project 5b8a35dllvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel sdiv.i64.ll srem.i64.ll

AMDGPU/GlobalISel: Switch RegBankLegalize lowering to extended LLTs

Stop using LLT::scalar for lowering in AMDGPURegBankLegalizeHelper
Affects integer lowering code for RegBankLLTMappingApplyID and
custom cpp for LoweringMethodID.
DeltaFile
+2,694-1,347llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+2,478-1,239llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+2,422-1,211llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+2,186-1,321llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+2,168-1,313llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+1,874-1,554llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+13,822-7,985207 files not shown
+39,447-24,886213 files

LLVM/project a64feacllvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-sdiv.mir legalize-udiv.mir

AMDGPU/GlobalISel: Switch legalizer custom lowering to extended LLTs

Stop using LLT::scalar in custom lowering in AMDGPULegalizerInfo.
The exception is S1 since it seems to work fine.
Does not change legalizer actions. In general this is intended as a
mechanical step in amdgpu's switch to extended LLTs, just try to
avoid LLT::scalar in instructions generated after IRtranslator,
since it seems like a step in the right direction. Some tests remove
-global-isel-abort=2 since GIM_SwitchType no longer fails on
LLT::scalar. Exposes a couple of new failures with 16bit bitcast.
DeltaFile
+7,518-3,753llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+6,870-3,429llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+6,643-3,290llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+4,890-2,337llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+3,044-3,044llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
+2,912-2,912llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
+31,877-18,765260 files not shown
+89,724-60,871266 files

LLVM/project 9fbbe3ellvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp

[GlobalISel] Simplify computeNumSignBits fallback to KnownBits. NFC. (#208675)
DeltaFile
+1-14llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+1-141 files

LLVM/project 0f514d2llvm/test/CodeGen/AMDGPU/GlobalISel legalize-llvm.amdgcn.image.sample.a16.ll irtranslator-call.ll

AMDGPU/GlobalISel: Switch CallLowering to extended LLTs

Stop using LLT::scalar for argument lowering in AMDGPUCallLowering.
Mostly straightforward, worth noting that some places now require
a bitcast between integer and float.
DeltaFile
+2,670-1,990llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+927-925llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
+909-723llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
+675-766llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
+488-488llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
+470-469llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
+6,139-5,361144 files not shown
+11,007-11,784150 files

LLVM/project 34b2fbellvm/lib/Target/ARM ARMFrameLowering.cpp

Account for a KCFI check before call instructions
DeltaFile
+10-0llvm/lib/Target/ARM/ARMFrameLowering.cpp
+10-01 files

LLVM/project 5d088a1llvm/lib/Target/ARM ARMFrameLowering.cpp

Add size estimates for CMSE calls and returns
DeltaFile
+30-0llvm/lib/Target/ARM/ARMFrameLowering.cpp
+30-01 files

LLVM/project 7bb4410llvm/lib/Target/ARM ARMFrameLowering.cpp

Merge branch 'thumb1-estimation-fix' into thumb1-estimation-check
DeltaFile
+44-0llvm/lib/Target/ARM/ARMFrameLowering.cpp
+44-01 files

LLVM/project 169ab6cclang/lib/Driver Driver.cpp

clang: Remove extra space and braces in flang check
DeltaFile
+1-2clang/lib/Driver/Driver.cpp
+1-21 files

LLVM/project 375cc88llvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-llvm.amdgcn.image.sample.a16.ll legalize-store-global.mir

AMDGPU/GlobalISel: Switch to extended LLTs (#207419)

IRtranslator now translates bfloat. Switch tablegen to use extendedLLTs.
Around 300 regression tests fail to inst-select because GIM_SwitchType
does not accept LLT::scalar. Around 100 mir inst select tests had input
updated to i32/f32 and select successfully. Then there are 24 various
crashes, mostly combiner or machine-verifier, those tests are disabled.

Most problems come from mixing s32 with i32/f32 and the way operator==
works with extendedLLTs compared to GIM_SwitchType.
In general, for inst-select fixes, I think it would be best to avoid
explicit use of LLT::scalar in lowering to avoid mixing it with
LLT::integer/LLT::float See inst-select-extendedLLTs.mir and
inst-select-extendedLLTs-err.mir.
DeltaFile
+5,524-11,062llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+5,056-10,126llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+4,877-9,819llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+5,052-5,052llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+4,710-4,710llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+3,093-5,580llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+28,312-46,349685 files not shown
+170,777-238,706691 files

LLVM/project 6400792clang/lib/Driver/ToolChains AMDGPU.cpp HIPAMD.cpp

clang/AMDGPU: Merge toolchain subclasses (#204863)

Simplify the toolchain implementations by collapsing
them into one. Previously we had a confusing split. The
AMDGPUToolChain base class implemented much of the base
support. It was subclassed by ROCMToolChain, which would
have been more accurately described as the offloading subclass.

That was further subclassed into HIP and OpenMP specific subclasses.
Deleting those two is the important part of this change. There was
code duplication, and features arbitrarily handled in one but not
the other. The offload kind is passed in almost everywhere if you
really need to know the original language. However, I consider
this an antifeature, and it is really poor QoI to have the HIP
and OpenMP toolchains behave differently in any way. The platform
should be consistent and the driver behaviors should not depend
on the language.

There is additional mess in the handling of spirv, which this

    [8 lines not shown]
DeltaFile
+281-125clang/lib/Driver/ToolChains/AMDGPU.cpp
+2-211clang/lib/Driver/ToolChains/HIPAMD.cpp
+0-94clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
+53-23clang/lib/Driver/ToolChains/AMDGPU.h
+0-68clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
+1-55clang/lib/Driver/ToolChains/HIPAMD.h
+337-5764 files not shown
+362-59110 files

LLVM/project 235056bclang/docs ReleaseNotes.md, clang/lib/Lex PPMacroExpansion.cpp

[clang][Preprocessor] Fix expansion locations for feature-like builtin macros (#207130)

Fixes #196067.

This patch fixes the expansion locations of synthesized tokens produced
by
feature-like builtin macros such as `__has_builtin(...)`.

Feature-like builtin macros lex past the macro name while evaluating
their
arguments. `ExpandBuiltinMacro()` used the final `Tok` location as both
the
expansion start and end when creating the synthesized result token, so
`__has_builtin(...)` results were anchored at the closing paren rather
than the
builtin macro invocation.

Fix by saving the macro-name location before argument parsing and using
it as

    [15 lines not shown]
DeltaFile
+12-0clang/unittests/Tooling/Syntax/TokensTest.cpp
+3-0clang/docs/ReleaseNotes.md
+2-1clang/lib/Lex/PPMacroExpansion.cpp
+17-13 files

LLVM/project ba4df5fllvm/docs LangRef.md

[LangRef] State that the memory model is an axiomatic one

Currently, one could read large parts of the memory model without learning for
sure whether it is meant as an operational model that describes how individual
operations change some notion of state or if it is an axiomatic model (like the
C++ memory model) that lists constraints that a candidate execution must
satisfy to be allowed.

While the description of what a read returns sounds somewhat operational,
aspects like the definition of fence instructions, the monotonic modification
order, and the total order of sequentially consistent operations place it in
the realm of axiomatic models.

This is an attempt to make the nature of the model more explicit (and maybe a
place to discuss the nature of the model), as suggested by RalfJung in the
reviews for #204329.
DeltaFile
+2-0llvm/docs/LangRef.md
+2-01 files

LLVM/project cfb2520clang/docs ReleaseNotes.md, clang/lib/Parse ParseDecl.cpp

[Clang] Ensure correct template parameter depth for abbreviated templates (#208699)

Fixes https://github.com/llvm/llvm-project/issues/200682
DeltaFile
+37-0clang/test/SemaTemplate/concepts-lambda.cpp
+7-1clang/lib/Parse/ParseDecl.cpp
+1-0clang/docs/ReleaseNotes.md
+45-13 files

LLVM/project f114842clang/docs ReleaseNotes.md, clang/lib/Sema SemaTemplateInstantiate.cpp

[Clang] Fix a bug in parameter mapping substitution (#208663)

When building parameter mapping, both substitution and
CheckTemplateArguments were marked as ParameterMappingSubstitution,
while CheckTemplateArguments could also substitute into default
arguments eagerly such that some type constraints were transformed too
early.

It turned out that we don't have to enforce that rebuild in
SubstTypeConstraint, so this reverts that behavior.

Fixes https://github.com/llvm/llvm-project/issues/197597
DeltaFile
+58-0clang/test/SemaTemplate/concepts-no-early-substitution.cpp
+1-1clang/lib/Sema/SemaTemplateInstantiate.cpp
+1-0clang/docs/ReleaseNotes.md
+60-13 files

LLVM/project c3cb696lldb/source/Breakpoint BreakpointResolverFileLine.cpp

[lldb] Fix data race when setting a breakpoint in mulitple debuggers. (#208485)

When you have two SBDebugger with a target for the same `a.out` and you
try to add a breakpoint at the same location.

The data race happens in `CompileUnit::GetSupportFiles()` one debugger
sees the there is no support files. it sets the parsed flag and parses
the support file. The other debugger sees the parsed flag is set and
will not set the breakpoint since the support file is still parsing and
and will assume the symbol file does not have support files.
DeltaFile
+8-5lldb/source/Breakpoint/BreakpointResolverFileLine.cpp
+8-51 files

LLVM/project 0457981llvm/lib/Target/AMDGPU SIISelLowering.cpp

remove legalizer rule
DeltaFile
+0-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+0-21 files

LLVM/project 7a7c1a1llvm/lib/Target/AMDGPU SIISelLowering.cpp

Make truncate legal
DeltaFile
+4-3llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-31 files

LLVM/project a864244llvm/test/CodeGen/AMDGPU packed_shl64_combine.ll

whopsy++
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
+2-21 files

LLVM/project 231c3d8llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

whopsy
DeltaFile
+0-1llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+0-11 files

LLVM/project 4594633llvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp

[Review] Move the unroll of trunc v2i64 to v2i32 out of performShlCombine
DeltaFile
+14-0llvm/lib/Target/AMDGPU/SIInstructions.td
+3-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+0-5llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+17-73 files

LLVM/project aba078allvm/test/CodeGen/AMDGPU packed_shl64_combine.ll

[Review] Remove amdgpu_kernel and make 2 variants, inreg/normal
DeltaFile
+139-33llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
+139-331 files

LLVM/project 0217fcallvm/test/CodeGen/AMDGPU packed_shl64_combine.ll

[Review] Reduced the test and renames
DeltaFile
+111-172llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
+111-1721 files

LLVM/project c26a0f5llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

[AMDGPU] Unroll illegal vector TRUNCATE after legalization

`performShlCombine` introduced a `v2i32 truncate x:v2i64`. This
pattern is not legal, and is normally expanded by the legalizer.

However, since the combine is done after legalization the illegal
pattern remains.

This happens on gfx1251 since it has legal `shl v2i64` instructions.
DeltaFile
+8-0llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+8-01 files

LLVM/project 14c7ce3llvm/test/CodeGen/AMDGPU packed_shl64_combine.ll

[AMDGPU] Pre-commit test
DeltaFile
+117-0llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
+117-01 files

LLVM/project fe06689llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

[Review] Move the unroll to avoid generating the illegal pattern in the first place
DeltaFile
+6-8llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+6-81 files