LLVM/project 6384c2aclang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp, clang/test/CIR/Transforms/abi-lowering indirect-non-byval-nyi.cir indirect-non-byval-forward-param.cir

Merge branch 'main' into users/vitalybuka/spr/nfctransforms-add-missing-vector-include-to-sampleprofileinferenceh
DeltaFile
+655-0clang/test/CIR/Transforms/abi-lowering/indirect-non-byval-forward-param.cir
+309-0clang/test/CIR/Transforms/abi-lowering/indirect-non-byval-nyi.cir
+148-12clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+40-89flang/lib/Optimizer/Builder/FIRBuilder.cpp
+87-0flang/test/Fir/CUDA/predefined-variables.mlir
+72-0llvm/test/CodeGen/AMDGPU/shrink-dead-vcc-def.mir
+1,311-10123 files not shown
+1,905-24629 files

LLVM/project b771db4llvm/include/llvm/Transforms/Utils SampleProfileInference.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+1-0llvm/include/llvm/Transforms/Utils/SampleProfileInference.h
+1-01 files

LLVM/project 20da465llvm/include/llvm/MC MCAsmInfo.h, llvm/lib/CodeGen/SelectionDAG LegalizeDAG.cpp SelectionDAGBuilder.cpp

CodeGen: Suppress per-invoke EH labels via an MCAsmInfo object predicate

This is to avoid depending on TargetOptions::ExceptionModel in the
X86ISelLowering constructor. This was used to legalize EH_LABEL to a nop.
Legality rules cannot depend on program state, and the exception model should
be read from the IR module flag. In this instance the exception model isn't
really the relevant property. The specific personality and the target
object's EH table format are. Introduce a new MCAsmInfo predicate which is a
known constant for the triple. Also just do this during the initial label
emission instead of leaving it to legalization. This cleans up some unused
labels for wasm. This is also a minor behavior change for unknown personalities;
the labels will now be conservatively emitted.

I don't know all that much about exceptions, there's a lot of AI reverse
engineering of intent here. Another bruteforce approach would be to just
relocate the current condition to the selector which has access to the
exception model, but the MCAsmInfo check will be reusable in other contexts.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+40-0llvm/test/CodeGen/WebAssembly/eh-invoke-label-suppression.ll
+28-0llvm/test/CodeGen/X86/eh-labels-unknown-personality.ll
+15-0llvm/include/llvm/MC/MCAsmInfo.h
+11-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+0-7llvm/lib/Target/X86/X86ISelLowering.cpp
+0-1llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+94-96 files

LLVM/project b8d5014clang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp, clang/test/CIR/CodeGen call-conv-lowering-x86_64-non-byval-thunk.cpp call-conv-lowering-x86_64-non-byval-thunk-mixed.cpp

[CIR] Read a non-byval parameter back out of its spill slot (#225010)

CallConvLowering recognizes a forwarded non-byval indirect argument by
the slot its operand was loaded from. At -O1 and above cir-simplify
folds that load away when the slot is a constant alloca, which is what
CIRGen emits for a const-qualified by-value parameter. The walk that
gives each such parameter's slot the alignment the ABI promises now also
reads the record back out of the slot at the spill and points the
parameter's call-argument uses at that load, so an Expand, byval or
coerced argument reads it too.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+655-0clang/test/CIR/Transforms/abi-lowering/indirect-non-byval-forward-param.cir
+309-0clang/test/CIR/Transforms/abi-lowering/indirect-non-byval-nyi.cir
+148-12clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+70-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-non-byval-thunk-sret.cpp
+58-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-non-byval-thunk-mixed.cpp
+50-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-non-byval-thunk.cpp
+1,290-122 files not shown
+1,330-368 files

LLVM/project a26ba32flang/lib/Optimizer/Builder FIRBuilder.cpp, flang/lib/Optimizer/Transforms/CUDA CUFPredefinedVarToGPU.cpp

[flang] Fix TRANSFER into derived type with tail padding (#223814)

When assigning a derived type value whose allocated size exceeds its
declared
field size (e.g. `SEQUENCE` type `{i32, i8}` — 5 bytes of fields, 8
bytes
allocated due to ABI tail padding), the assignment path in
`genRecordAssignment` took a "simple type" fast path that called
`genComponentByComponentAssignment`. That function iterated over
declared
fields and copied them one by one via `fir.coordinate_of`/`fir.load`/
`fir.store`, silently skipping the tail-padding bytes and leaving them
**unwritten** in the destination.

This is a compatibility choice rather than a correctness fix: F2023
10.2.1.3
p15 defines derived-type intrinsic assignment component by component,
and p16
allows any means with the same effect, so padding is outside the defined

    [195 lines not shown]
DeltaFile
+40-89flang/lib/Optimizer/Builder/FIRBuilder.cpp
+87-0flang/test/Fir/CUDA/predefined-variables.mlir
+68-4flang/test/HLFIR/assign-codegen-derived.fir
+60-11flang/lib/Optimizer/Transforms/CUDA/CUFPredefinedVarToGPU.cpp
+28-0flang/test/Lower/Intrinsics/transfer.f90
+1-18flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
+284-1223 files not shown
+303-1469 files

LLVM/project 77c9104llvm/lib/Target/SPIRV SPIRVLegalizeResourceBinding.cpp

[SPIRV] Fix -Wunused-variable in #224488 (#225897)

Use [[maybe_unused]] as the operations either have side effects where we
can't inline them into the assert or the definitions/variable names
provide additional clarity.
DeltaFile
+2-2llvm/lib/Target/SPIRV/SPIRVLegalizeResourceBinding.cpp
+2-21 files

LLVM/project 1261342llvm/lib/Target/AMDGPU SIShrinkInstructions.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU fold-immediate-operand-shrink-dead-carry.mir shrink-v-cmp-wave32-dead-vcc-lo.mir

AMDGPU: Preserve carry-out dead flag in buildShrunkInst (#225798)

Shrinking from the e64 to the e32 form drops the explicit carry-out def
in favor of an implicit vcc def. If the original carry out had a dead
flag, preserve it in the shrunk instruction's implicit-def operand.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+72-0llvm/test/CodeGen/AMDGPU/shrink-dead-vcc-def.mir
+0-55llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
+44-0llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-dead-carry.mir
+10-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+0-4llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+126-595 files

LLVM/project 96f2657llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer VecUtils.h, llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes LoadStoreVec.h

[SandboxVec][LoadStoreVec] Support constant vectors of mixed types

createConstantVector() previously packed the constant store operands
as-is, which only worked when every store had the same element type.
Take the lane type from VecUtils::getCombinedVectorTypeFor() instead and
reinterpret each constant's bits as that type, going through an integer
of matching width via ptrtoint/inttoptr/bitcast. Constants wider than a
lane (e.g. an i64 in an <N x i32>) are split across several lanes in
memory order. Bail out when a constant cannot be reinterpreted, such as
a non-integral pointer or a relocatable address that needs splitting.

Also flatten vector-typed ConstantPointerNull into per-lane nulls, and
bail out on the remaining vector constants such as poison rather than
packing them into the result.

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+385-0llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/load_store_vec_mixed_types.ll
+92-12llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
+15-5llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
+18-0llvm/lib/SandboxIR/Constant.cpp
+12-3llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
+12-0llvm/unittests/SandboxIR/SandboxIRTest.cpp
+534-203 files not shown
+540-219 files

LLVM/project 1e5e53dclang/docs ReleaseNotes.md, clang/include/clang/Basic BuiltinHeaders.def Builtins.td

[Clang][Sema] Add fortify warnings for recv and recvfrom (#223520)

Add `-Wfortify-source` diagnostics for `recv` and `recvfrom` when the size argument exceeds the destination buffer size.

Part of #142230

Assisted-by: Gemini
DeltaFile
+72-0clang/test/Sema/warn-fortify-source-recv-not-builtin.c
+36-0clang/test/Sema/warn-fortify-source.c
+15-3clang/lib/Sema/SemaChecking.cpp
+17-0clang/include/clang/Basic/Builtins.td
+3-0clang/docs/ReleaseNotes.md
+1-0clang/include/clang/Basic/BuiltinHeaders.def
+144-36 files

LLVM/project 7a89432.github/workflows libcxx-pr-benchmark.yml libcxx-pr-test-tools.yml

Revert "Partially Reapply "[libcxx] Move premerge jobs to k8s mode runner set…"

This reverts commit a14634f662776d7c9f3fe15f5eb687dc6287d17c.
DeltaFile
+2-5.github/workflows/libcxx-pr-test-tools.yml
+1-0.github/workflows/libcxx-pr-benchmark.yml
+3-52 files

LLVM/project edbecccclang/lib/CodeGen CGHLSLRuntime.cpp, clang/lib/Sema SemaHLSL.cpp

[HLSL] Implement the SV_InstanceID semantic (#221091)

Fixes #212572

Adds type validation, stage restriction, and lowering for
`SV_InstanceID`.

- Type check rejects non-uint; DXIL accepts U32/U16, SPIR-V accepts U32
only (VUID-InstanceIndex-InstanceIndex-04265).
- Rejected all sigpoints but Vertex In.
- On SPIR-V, the variable is decorated with `BuiltIn InstanceIndex`
instead of a user-assigned Location.
- SPIR-V lowering loads from the `InstanceIndex` (ID 43) built-in; DXIL
lowering uses `dx.op.loadInput`.
- LIT tests for sema (wrong type, wrong stage, output direction) and
codegen (BuiltIn decoration, no Location).

@dnovillo @pow2clk

Assisted-by: LLM
DeltaFile
+38-0clang/test/SemaHLSL/Semantics/instanceid.vs.hlsl
+19-0clang/test/CodeGenHLSL/semantics/SV_InstanceID.vs.hlsl
+13-0clang/lib/Sema/SemaHLSL.cpp
+12-0clang/lib/CodeGen/CGHLSLRuntime.cpp
+11-0clang/test/SemaHLSL/Semantics/instanceid.output.hlsl
+7-0clang/test/SemaHLSL/Semantics/instanceid.ps.hlsl
+100-02 files not shown
+103-28 files

LLVM/project a4f389ecompiler-rt/lib/sanitizer_common/symbolizer/scripts global_symbols.txt

[NFC][sanitizer] Allow fread in symbolizer (#225853)

Commit 3c63fcb246f3 (#212010) introduced `fread` usage in libc++
`std_stream.h`. Because libc++ is linked into the internal symbolizer,
`fread` is now referenced in `symbolizer.o`. Add `fread U` to
`global_symbols.txt` so symbol verification succeeds.

Assisted-by: Gemini
DeltaFile
+1-0compiler-rt/lib/sanitizer_common/symbolizer/scripts/global_symbols.txt
+1-01 files

LLVM/project d4c1e0cllvm/test/CodeGen/AMDGPU amdgcn.bitcast.960bit.ll amdgcn.bitcast.256bit.ll

AMDGPU: Preserve dead carry-out when shrinking adds in SIFoldOperands (#225687)

The VOP3 form of add/sub with carry out are sometimes shrunk to the VOPC
form when the carry out is dead. Preserve this information by setting
the dead flag on the new instruction. This alleviates some implicit
dependence on LiveVariables' later recomputation of dead flags.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+4,860-4,866llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,684-1,713llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+772-790llvm/test/CodeGen/AMDGPU/scratch-simple.ll
+398-401llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+226-247llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+210-221llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,150-8,23834 files not shown
+9,629-9,94040 files

LLVM/project dfc0d74libcxx/test/benchmarks filesystem.bench.cpp

[libc++] Don't pass a path lvalue to DoNotOptimize in the filesystem benchmark (#225504)

BM_PathIterateOnceBackwards passes *I directly to DoNotOptimize.
However, libstdc++ returns a const lvalue reference to `path` from that
operation, which selects GoogleBenchmark's deprecated const-ref
overload.

Use the pattern used elsewhere in this file instead.
DeltaFile
+2-2libcxx/test/benchmarks/filesystem.bench.cpp
+2-21 files

LLVM/project be40d5bcompiler-rt/lib/csan csan_watch.h csan_report.cpp, compiler-rt/lib/csan/offload csan_offload_report.cpp csan_offload_hsa_interceptors.cpp

[compiler-rt] Add 'csan' library for the concurrency sanitizer

Summary:
Adds the runtime for the concurrency sanitizer, both CPU and GPU.
Fundamentally, this works using the following pseudocode:

```c
static u64 watchpoints[N]; // Hash-indexed, zero is empty.

// Emitted before the access, so we never trip on our own write.
void check_access(volatile void *addr, u32 size, u32 type) {
    // Every access probes. A read conflicts only with a watched write, a
    // write conflicts with either.
    if (u64 *wp = find_watchpoint(addr, size, type))
        consume(wp, this_pc()); // Hand our location to the owner.

    if (!should_sample()) // Wave-uniform, 1-in-N chance.
        return;


    [17 lines not shown]
DeltaFile
+456-0compiler-rt/lib/csan/csan_gpu.cpp
+370-0compiler-rt/lib/csan/offload/csan_offload_hsa_interceptors.cpp
+334-0compiler-rt/lib/csan/csan.cpp
+279-0compiler-rt/lib/csan/csan_report.cpp
+184-0compiler-rt/lib/csan/offload/csan_offload_report.cpp
+163-0compiler-rt/lib/csan/csan_watch.h
+1,786-050 files not shown
+3,031-556 files

LLVM/project aeea5b1llvm/test/Transforms/LoopVectorize outer-loop-gep-nowrap-flags-scev.ll outer_loop_contiguous.ll, llvm/test/Transforms/LoopVectorize/AArch64 outer_loop_prefer_scalable.ll

[LV] Add additional outer loop vectorization tests. (#225821)

Add test more test coverage for outer loop vectorization path, focusing
on various legality aspects, like supported instructions and memory
checks.
DeltaFile
+1,326-0llvm/test/Transforms/LoopVectorize/outer-loop-memory-safety.ll
+477-1llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll
+147-0llvm/test/Transforms/LoopVectorize/outer-loop-gep-nowrap-flags-scev.ll
+98-1llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
+62-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop-memchecks.ll
+2,110-25 files

LLVM/project b68692bllvm/docs/CommandGuide lit.md

[lit][docs] Document %if conditional substitution in lit CommandGuide (#225683)

`%if ... %else` conditional substitutions (implemented in
`TestRunner.py` and mentioned in `TestingGuide.md`) were missing from
the `SUBSTITUTIONS` table and `available_features` description in
`llvm/docs/CommandGuide/lit.md`. Add `%if` to the base substitutions
table and note that `available_features` can be used in `%if`
conditions.

Signed-off-by: Ingo Müller <ingomueller at google.com>
DeltaFile
+2-1llvm/docs/CommandGuide/lit.md
+2-11 files

LLVM/project 2aaf32aclang/docs ConcurrencySanitizer.md, clang/lib/CodeGen CodeGenFunction.cpp

[Clang] Add support for the `-fsanitize=concurrency` runtime

Summary:
Add the frontend sanitizer kind, function attributes, pass pipeline
integration, predefined macro, driver handling, and documentation for
ConcurrencySanitizer.
DeltaFile
+207-0clang/docs/ConcurrencySanitizer.md
+73-0clang/test/CodeGen/sanitize-concurrency.c
+31-7clang/lib/Driver/ToolChains/CommonArgs.cpp
+15-0clang/test/Driver/fsanitize.c
+10-4clang/lib/Driver/SanitizerArgs.cpp
+10-3clang/lib/CodeGen/CodeGenFunction.cpp
+346-1410 files not shown
+374-1516 files

LLVM/project fa93974llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 fsub-chain-reduction-unpaired-signs.ll

[SLP]Pair small sign-aware reduction groups only if both signs have one

The small-group check of the flattened fsub/fneg fadd reductions
used whenever any leaf was negated, vectorizing 2-wide parts that
have no opposite-sign part to combine with via the vector fsub.
Allow it only if both signs have a group of at least 2 values.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/225881
DeltaFile
+13-15llvm/test/Transforms/SLPVectorizer/AArch64/fsub-chain-reduction-unpaired-signs.ll
+12-3llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+25-182 files

LLVM/project 2cd14dfclang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareExchangeFloatBitwise coverage to the texture test
DeltaFile
+5-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+5-01 files

LLVM/project cc24f8bclang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareExchangeFloatBitwise builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project ce18585clang/test/CodeGenHLSL/builtins RWBuffer-Interlocked.hlsl RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl, clang/test/SemaHLSL/BuiltIns ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl InterlockedCompareExchangeFloatBitwise-errors.hlsl

First attempt implementing InterlockedCompareExchangeFloatBitwise



DeltaFile
+119-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareExchangeFloatBitwise-errors.hlsl
+43-0clang/test/CodeGenHLSL/builtins/InterlockedCompareExchangeFloatBitwise.hlsl
+42-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareExchangeFloatBitwise-sm60.hlsl
+32-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+25-0clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareExchangeFloatBitwise.hlsl
+10-0clang/test/CodeGenHLSL/builtins/RWBuffer-Interlocked.hlsl
+271-05 files not shown
+298-311 files

LLVM/project 6bf89baclang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareExchange coverage to the texture test
DeltaFile
+5-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+5-01 files

LLVM/project 07ecb07clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareStoreFloatBitwise coverage to the texture test
DeltaFile
+7-0clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+7-01 files

LLVM/project 6f23ed3clang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareExchange builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project a91df9fclang/include/clang/Basic Builtins.td

Remove the comment on the InterlockedCompareStoreFloatBitwise builtin
DeltaFile
+0-1clang/include/clang/Basic/Builtins.td
+0-11 files

LLVM/project acb0146clang/lib/Sema SemaHLSL.cpp, clang/test/CodeGenHLSL/builtins RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl InterlockedCompareStoreFloatBitwise.hlsl

First attempt implementing InterlockedCompareStoreFloatBitwise



DeltaFile
+100-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
+39-0clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
+35-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
+30-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
+27-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
+16-6clang/lib/Sema/SemaHLSL.cpp
+247-66 files not shown
+311-1012 files

LLVM/project 80e031eclang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Sema HLSLExternalSemaSource.cpp

First attempt implementing InterlockedCompareStore
DeltaFile
+88-0clang/test/SemaHLSL/BuiltIns/InterlockedCompareStore-errors.hlsl
+54-0clang/test/CodeGenHLSL/builtins/InterlockedCompareStore.hlsl
+44-8clang/lib/Sema/HLSLExternalSemaSource.cpp
+29-7clang/lib/CodeGen/CGHLSLBuiltins.cpp
+36-0clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStore.hlsl
+33-0llvm/test/CodeGen/DirectX/ResourceAtomicCompareStore.ll
+284-157 files not shown
+392-1713 files

LLVM/project 5bfa2d2llvm/lib/Target/DirectX DXILResourceAccess.cpp, llvm/test/CodeGen/DirectX ResourceAtomicBinOp-texture-nonscalar.ll ResourceAtomicExchangeFloat.ll

Lower atomicrmw on scalar float texture resources
DeltaFile
+18-0llvm/test/CodeGen/DirectX/ResourceAtomicExchangeFloat.ll
+4-4llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
+5-2llvm/lib/Target/DirectX/DXILResourceAccess.cpp
+27-63 files

LLVM/project bf93125clang/test/CodeGenHLSL/builtins RWTexture-Interlocked.hlsl

Add InterlockedCompareStore coverage to the texture test
DeltaFile
+13-8clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
+13-81 files