LLVM/project ba5bccf — libcxx/test/benchmarks/containers/associative map.bench.cpp unordered_map.bench.cpp, libcxx/test/benchmarks/format formatter_float.bench.cpp write_int_comparison.bench.cpp

by Louis Dionne via GitHub on ⎇
[libc++] Fix duplicate names in benchmarks (#215676)

A few benchmarks were using names that were reused elsewhere in the test
suite. All benchmarks must have a unique name, otherwise we can't
distinguish them in LNT.
DeltaFile
+17-11libcxx/test/benchmarks/format/write_int_comparison.bench.cpp
+17-11libcxx/test/benchmarks/format/write_double_comparison.bench.cpp
+4-1libcxx/test/benchmarks/format/formatter_float.bench.cpp
+2-1libcxx/test/benchmarks/containers/associative/unordered_map.bench.cpp
+1-1libcxx/test/benchmarks/containers/associative/map.bench.cpp
+41-255 files

LLVM/project f75f03b — libc/src/__support/FPUtil dyadic_float.h, libc/src/__support/builtins CMakeLists.txt truncxfbf2.h

by hulxv on ⎇
[compiler-rt][builtins] libc-backed float80-bfloat16/float16 conversion builtins
DeltaFile
+78-17libc/src/__support/builtins/fpconvert_helper.h
+38-24libc/src/__support/FPUtil/dyadic_float.h
+41-0libc/src/__support/builtins/extendhfxf2.h
+40-0libc/src/__support/builtins/truncxfhf2.h
+39-0libc/src/__support/builtins/truncxfbf2.h
+37-0libc/src/__support/builtins/CMakeLists.txt
+273-4111 files not shown
+475-4117 files

LLVM/project 57a9c4f — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.sqrt.bf16.ll llvm.amdgcn.sin.bf16.ll

by Stanislav Mekhanoshin via GitHub on ⎇
[AMDGPU] VOP1 bf16 instructions read high 16 bit of an inline (#215688)

VOP1 cannot be used in this case and VOP3 shall use OPSEL.
DeltaFile
+18-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+20-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+8-8llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
+54-184 files not shown
+62-2610 files

LLVM/project 5d27e3a — clang/lib/Driver/ToolChains Flang.cpp, flang/test/Driver fast-math.f90

by Shunsuke Watanabe via GitHub on ⎇
[Flang][Driver] Override -ffast-math floating point contraction with -ffp-contract= (#213574)

This patch allows overriding the floating point contract settings
implied by -ffast-math by explicitly specifying -ffp-contract=. The
final floating point contract mode follows the usual last-flag-wins
behavior. In addition, -fno-fast-math only cancels the effects of
-ffast-math and preserves any explicitly specified -ffp-contract=
setting.

A warning is emitted when an explicit -ffp-contract= option overrides
the floating point contract mode implied by -ffast-math.

This behavior is consistent with Clang.
DeltaFile
+51-10flang/test/Driver/fast-math.f90
+39-20clang/lib/Driver/ToolChains/Flang.cpp
+90-302 files

LLVM/project 486b922 — llvm/lib/Target/AMDGPU VOP1Instructions.td, llvm/test/MC/AMDGPU gfx1250_asm_vop3_from_vop1-fake16.s

by Stanislav Mekhanoshin via GitHub on ⎇
[AMDGPU] Allow OPSEL in bf16 trans instructions in fake16 (#215687)
DeltaFile
+24-0llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
+2-0llvm/lib/Target/AMDGPU/VOP1Instructions.td
+50-245 files

LLVM/project 661cffb — clang/lib/CIR/CodeGen CIRGenCall.cpp CIRGenModule.cpp, clang/test/CIR/CodeGen asm-label-redirect.c alloc-size.c

by Adam Smith via GitHub on ⎇
[CIR] Record target-cpu and target-features on function declarations (#214986)

A function declaration carried no CPU or feature attributes. CIRGen set
them from `setNonAliasAttributes`, which runs only for a definition,
where classic CodeGen sets them from `ConstructAttributeList` for a
declaration too. We now set them properly in `constructAttributeList`
alongside the other non-call-site attributes.

Recording them on a declaration exposes a second bug. When a function is
declared first and defined later with a `target` attribute,
`setNonAliasAttributes` wrote the definition's values over the
declaration's rather than replacing them, so a `tune-cpu` that the
`target` attribute suppresses survived. It now clears the three
attributes before writing, which is safe because
`getCPUAndFeaturesAttributes` resolves the most recent declaration, so
its result supersedes anything an earlier one wrote.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+29-0clang/test/CIR/CodeGen/attr-target-x86.c
+15-6clang/lib/CIR/CodeGen/CIRGenModule.cpp
+8-1clang/lib/CIR/CodeGen/CIRGenCall.cpp
+2-2clang/test/CIR/CodeGen/asm-label-redirect.c
+2-2clang/test/CIR/CodeGen/alloc-size.c
+3-1clang/test/CIR/CodeGen/global-init.cpp
+59-121 files not shown
+62-127 files

LLVM/project fbcf554 — llvm/utils/lit/lit reports.py

by NAKAMURA Takumi via GitHub on ⎇
lit/reports.py: Make Py3.8-compatible (for #211066) (#215554)

I know py3.8 is slightly old. That said;

- llvm/CMakeLists.txt restricts the bottom version as 3.8
- This is not a functionally-critical change

I won't object further discussions if version upgrade would be required.
DeltaFile
+2-1llvm/utils/lit/lit/reports.py
+2-11 files

LLVM/project 1c33a0f — llvm/unittests/IR ConstantFPRangeTest.cpp

by NAKAMURA Takumi via GitHub on ⎇
ConstantFPRangeTest.cpp: Hide templates conditionally. [-Wunused-template] (#215559)

Introduced in #86483. They are referred in `EXPENSIVE_CHECKS`.
DeltaFile
+4-0llvm/unittests/IR/ConstantFPRangeTest.cpp
+4-01 files

LLVM/project f073261 — llvm/test/CodeGen/RISCV pr148084.ll

by Craig Topper via GitHub on ⎇
[RISCV] Prevent dead code in pr148084.ll. NFC (#215646)
DeltaFile
+80-60llvm/test/CodeGen/RISCV/pr148084.ll
+80-601 files

LLVM/project e91447a — llvm/docs LangRef.md LangRef.rst, llvm/lib/Support UnicodeNameToCodepointGenerated.cpp

by Johannes Doerfert via GitHub on ⎇
Merge branch 'main' into users/jdoerfert/openmp_kernel_name
DeltaFile
+45,574-45,285llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+24,053-23,916llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+0-33,097llvm/docs/LangRef.rst
+15,740-14,892llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+30,488-0llvm/docs/LangRef.md
+28,897-12llvm/test/CodeGen/RISCV/clmul.ll
+144,752-117,20230,970 files not shown
+2,010,856-1,170,24130,976 files

LLVM/project 022d936 — clang/lib/CIR/Dialect/IR CIRDialect.cpp, clang/test/CIR/Transforms canonicalize.cir

by Kunal Dubey via GitHub on ⎇
[CIR] Avoid folding non-integer constants as integer casts (#214551)

CIRGen may produce undef constants while recovering from NYI builtin
lowering. When such a value feeds an implicit integral cast,
CastOp::fold currently treats the source as an integer constant solely
because it is a cir.constant, then calls getIntValue() and crashes.

Added a check for the constant to see if the payload is actually an
IntAttr before folding the cast. If it is not, return the cast unfolded.

Added a regression test covering an unimplemented __builtin_stdc_* call
whose undef result was implicitly being cast to integer by CastOp::fold.

Part of issue #214443
DeltaFile
+12-4clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+9-0clang/test/CIR/Transforms/canonicalize.cir
+21-42 files

LLVM/project 578aefa — orc-rt/include/orc-rt SimplePackedSerialization.h, orc-rt/test/unit SimplePackedSerializationTest.cpp

by Lang Hames via GitHub on ⎇
[orc-rt] SPS serialization: SPSExecutorAddrRange <-> span<T> (#215693)

Allows a memory range to be sent as an SPSExecutorAddrRange by the
controller and received as a span<T> by the executor, so handlers can
take a span directly rather than converting from an ExecutorAddrRange
themselves.

The wire format is identical to the existing ExecutorAddrRange
serialization -- a (Start, End) address pair -- so the two are
interchangeable in either direction.

Note that this transmits the span's bounds, not its contents; that
distinguishes it from the existing SPSSequence<char> / span<const char>
serialization, which copies the bytes.

Since the address pair arrives as untrusted wire data, deserialization
rejects inverted ranges, addresses that don't fit in uintptr_t, and
lengths that aren't a whole number of elements, rather than constructing
an out-of-bounds span.
DeltaFile
+99-0orc-rt/test/unit/SimplePackedSerializationTest.cpp
+36-1orc-rt/include/orc-rt/SimplePackedSerialization.h
+135-12 files

LLVM/project 51c9b9b — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

by Sam Elliott on ⎇
[RISCV][NFC] Move ZacasABIFix Pass Declaration

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVZacasABIFix.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project d002b95 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

by Sam Elliott on ⎇
[RISCV][NFC] Move RISCVCodeGenPrepare Declarations

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVCodeGenPrepare.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 20538ab — llvm/lib/Target/RISCV RISCVCodeGenPassBuilder.cpp RISCVOptWInstrs.h, llvm/test/CodeGen/RISCV O3-newpm-pipeline.ll O1-newpm-pipeline.ll

by Sam Elliott on ⎇
[RISCV] Port Opt W Instrs to NewPM

Assisted-by: AI
DeltaFile
+44-22llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+35-0llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+3-3llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+2-1llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+2-1llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+90-277 files not shown
+97-3113 files

LLVM/project 06c22c2 — llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV fold-mem-offset.mir

by Sam Elliott on ⎇
[RISCV] Port Fold Memory Offset Pass to NewPM

Assisted-by: AI
DeltaFile
+37-16llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+36-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/fold-mem-offset.mir
+78-213 files not shown
+81-219 files

LLVM/project f6271e6 — llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.mir

by Sam Elliott on ⎇
[RISCV] Port Vector Peephole to NewPM

Assisted-by: AI
DeltaFile
+66-44llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+39-0llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+111-497 files not shown
+119-4913 files

LLVM/project 7c9cde3 — llvm/lib/Target/RISCV RISCV.h

by Sam Elliott on ⎇
Remove useless header
DeltaFile
+0-1llvm/lib/Target/RISCV/RISCV.h
+0-11 files

LLVM/project e16b5cc — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp, llvm/test/CodeGen/RISCV/rvv vl-opt.mir

by Sam Elliott on ⎇
[RISCV] Port VL Optimizer to NewPM

Assisted-by: AI
DeltaFile
+56-31llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+36-0llvm/lib/Target/RISCV/RISCVVLOptimizer.h
+1-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+98-363 files not shown
+101-369 files

LLVM/project df96bb3 — llvm/lib/Target/RISCV RISCVGatherScatterLowering.cpp

by Sam Elliott on ⎇
Move subtarget checks into Impl object
DeltaFile
+5-7llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
+5-71 files

LLVM/project d4cf759 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

by Sam Elliott on ⎇
[RISCV][NFC] Move ZacasABIFix Pass Declaration

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVZacasABIFix.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 6d0f1fd — llvm/lib/Target/RISCV RISCVCodeGenPassBuilder.cpp RISCVOptWInstrs.h, llvm/test/CodeGen/RISCV O3-newpm-pipeline.ll O1-newpm-pipeline.ll

by Sam Elliott on ⎇
[RISCV] Port Opt W Instrs to NewPM

Assisted-by: AI
DeltaFile
+44-22llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+35-0llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+3-3llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+2-1llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+2-1llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+90-277 files not shown
+97-3113 files

LLVM/project 040ebf2 — llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

by Sam Elliott on ⎇
[RISCV][NFC] Move RISCVCodeGenPrepare Declarations

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVCodeGenPrepare.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 0024ef0 — llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV fold-mem-offset.mir

by Sam Elliott on ⎇
[RISCV] Port Fold Memory Offset Pass to NewPM

Assisted-by: AI
DeltaFile
+37-16llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+36-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/fold-mem-offset.mir
+78-213 files not shown
+81-219 files

LLVM/project bc707b8 — llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.mir

by Sam Elliott on ⎇
[RISCV] Port Vector Peephole to NewPM

Assisted-by: AI
DeltaFile
+66-44llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+39-0llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+111-497 files not shown
+119-4913 files

LLVM/project 0d16817 — llvm/lib/Target/RISCV RISCV.h

by Sam Elliott on ⎇
Remove useless header
DeltaFile
+0-1llvm/lib/Target/RISCV/RISCV.h
+0-11 files

LLVM/project 6340660 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.sqrt.bf16.ll llvm.amdgcn.sin.bf16.ll

by Stanislav Mekhanoshin on ⎇
[AMDGPU] VOP1 bf16 instructions read high 16 bit of an inline

VOP1 cannot be used in this case and VOP3 shall use OPSEL.
DeltaFile
+18-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+20-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+8-8llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
+54-184 files not shown
+62-2610 files

LLVM/project 03a8db1 — llvm/include/llvm/CodeGen TargetLoweringObjectFileImpl.h, llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp

by Arthur Eubanks via GitHub on ⎇
[MC][x86-64] Decide if each individual mergeable constants is small or large (#209881)

Rather than only relying on the code model. Otherwise we can end up with
the IR and MC disagreeing about which ones are small/large.

Don't use MergeableConst*Section in
TargetLoweringObjectFileELF::getSectionForConstant(), decide which
section dynamically. Other binary formats still use those though.

This resolves some relocation overflows from mixed small/medium code
model code.

Followup to #190903.

Assisted-by: Gemini
DeltaFile
+59-44llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+58-0llvm/test/CodeGen/X86/code-model-elf-strings.ll
+18-1llvm/test/CodeGen/X86/code-model-elf-constpool-large.ll
+14-2llvm/lib/Target/TargetMachine.cpp
+4-11llvm/lib/MC/MCObjectFileInfo.cpp
+5-0llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
+158-583 files not shown
+161-609 files

LLVM/project e15d649 — clang/docs ReleaseNotes.md, clang/lib/Sema SemaTemplateInstantiate.cpp SemaExpr.cpp

by Eli Friedman via GitHub on ⎇
[clang] Don't mark a field invalid for unparsed in-class member initializer. (#215423)

We delay parsing of in-class member initializers until the end of the
outermost class declaration. It is an error for code to try to use that
initializer before it's parsed. However, sometimes that error can be
suppressed by an SFINAE context. Since we aren't sure a user-visible
error will be emitted, don't mark the field invalid.

Fixes https://github.com/llvm/llvm-project/issues/215166 .
DeltaFile
+14-0clang/test/SemaCXX/cxx11-default-member-initializers.cpp
+5-0clang/docs/ReleaseNotes.md
+0-1clang/lib/Sema/SemaTemplateInstantiate.cpp
+0-1clang/lib/Sema/SemaExpr.cpp
+19-24 files

LLVM/project 6ab70d7 — llvm/lib/Target/AMDGPU VOP1Instructions.td, llvm/test/MC/AMDGPU gfx1250_asm_vop3_from_vop1-fake16.s

by Stanislav Mekhanoshin on ⎇
[AMDGPU] Allow OPSEL in bf16 trans instructions in fake16
DeltaFile
+24-0llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
+2-0llvm/lib/Target/AMDGPU/VOP1Instructions.td
+50-245 files