[clang][CFG] Fix lambda capture evaluation order (#211877)
Previously, the captures were emitted in their spelling order - but in
the CFG that gets translared in a reversed order.
Because of this, we need to emit them in reversed order to get them
appear in their natural order.
Fixes rdar://183140177
[docs] Remove release notes for backported changes (#212069)
Commit 68f703f3e58a52c41b39dfc654a675560b6c5614 added these release
notes, but this commit was backported to the 23.x release branch in
47e2df730a099583f16fc6fe64f0d2ffc5b7a16a (included in the 23.1.0 RC 1
tag).
Therefore, remove these release notes from the main branch (where they
would have been included in the 24.x release notes).
[clang] [test] Fix a new test on mingw (#212064)
This fixes running a new test that was added in
4b66bacd1fdf02803509b744034f3ab09945157c, in mingw environments.
The quirks that warranted adding the `!defined(_WIN32)` condition in the
test aren't actually specific to Windows in general, but specific to
MSVC environments - mingw environments behave just like other platforms.
Ideally we'd use `!defined(_MSC_VER)`, however in -cc1 mode, Clang
doesn't automatically define `_MSC_VER`; defining it requires setting a
command line option that the driver normally passes in MSVC mode.
Therefore, qualify the condition as `!defined(_MSC_VER) ||
defined(__MINGW32__)`.
DAG: Canonicalize undef shuffle operands and results to poison
getVectorShuffle canonicalizes fully-undefined results and unused operands.
Make sure these use poison to avoid degrading poison to undef, defending against
future regressions.
Co-Authored-By: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[libc][test][NFC] Fix pthread_setschedparam_test flakiness (#212067)
Synchronised child thread execution in pthread_setschedparam_test using
a mutex lock. This prevents race conditions where the child thread
exited before scheduling parameter assertions ran on multi-core
platforms such as aarch64.
Added missing pthread target dependencies to CMakeLists.txt.
Assisted-by: Automated tooling, human reviewed.
[AMDGPU][GISel] Remove redundant AND on scalar shift amounts
A scalar shift only consumes the low log2(bitwidth) bits of its amount,
so an explicit (and amt, mask) feeding the amount is redundant whenever
mask has all of those low bits set. SelectionDAG already achieves this
via SimplifyDemandedBits on the shift-amount operand; this adds the
equivalent to the post-RegBankSelect combiner for G_SHL/G_LSHR/G_ASHR.
Co-authored-by: Cursor <cursoragent at cursor.com>
[LoopInfo] Identify loops with a single-pass DFS algorithm. NFC (#212000)
analyze() numbers the dominator tree, scans it in reverse preorder for
header candidates, floods backward through the CFG from each header's
latches, then walks the CFG again to order the blocks.
Do all of it in one forward DFS, with the algorithm of Wei et al.,
"A New Algorithm for Identifying Loops in Decompilation", which
GenericCycleInfo already implements.
On an irreducible CFG that algorithm may return an irreducible superset
of the natural loop subset `discoverAndMapSubloop` would return.
(Depending on the successor visiting order, the algorithm may report a
reducible loop nested in an irreducible loop, where the reducible one
exactly matches `discoverAndMapSubloop`.)
To satisfy verifyLoop and LoopSimplify, reduce each such ireducible loop
to the natural loop of its header's backedges instead: the latches the
header dominates, and the blocks reaching them without passing the
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[clang][bytecode] Don't check global variable init size (#212092)
The current interpreter doesn't do this either. If we do, the clang
build fails because AMDGPUGenGlobalISel.inc: contains a global constexpr
array called MatchTable0 with 1'926'005 elements.
[clang][bytecode] Only override constant-context state if we have an EvalEmitter (#211475)
This does not make sense when emitting bytecode, as the bytecode would
just contain a `PushCC`/`PopCC` pair with nothing in between.
[AArch64] Add CAS instructions to NeoverseN2 schedule model (#211195)
CAS instructions (B, H, W, X variants) are not described in the ARM
Neoverse N2 Software Optimization Guide. There used to be no schedule
model for them, so `llvm-mca` was unable to analyze code containing
these instructions:
llvm-mca -mtriple=aarch64 -mcpu=cortex-a78 -mattr=+lse casb.s
error: found an unsupported instruction in the input assembly
sequence, use -skip-unsupported-instructions=lack-sched to ignore
these on the input.
note: instruction: casb w0, w1, [sp]
The patch adds a basic schedule model of 14 cycles (as measured on
Cortex-A78 with llvm-exegesis) and L/S utilized pipelines (this is a
guess, the reality is likely more complicated).
[Github] Add myself and lforg37 as mlir wasmssa codeowners (#212079)
Adding @flemairen6 and @lforg37 as codeowners of WasmSSA
Co-authored-by: Ferdinand Lemaire <flemairen6 at gmail.com>
[MLIR][WasmSSA] Add global_set and select ops (#196613)
Adds two missing ops to the WasmSSA dialect.
- `wasmssa.global_set`
- `wasmssa.select`
---------
Co-authored-by: Ferdinand Lemaire <flscminecraft at gmail.com>
[ELF] Retain .got for revertible no-PIC GOTPCRELX optimization (#212077)
Commit 9d6ec280fc537b55ef8641ea85d3522426bc5766 (2023) sets
GotSection::hasGotOffRel when adjustGotPcExpr returns R_RELAX_GOT_PC,
keeping .got alive for an optimization that X86_64::relaxOnce may
revert.
R_RELAX_GOT_PC_NOPIC (e.g. `addq`) in -no-pie mode has the same issue.
[mlir][tosa] Fix mul/intdiv folds crashing on dynamic-shaped results (#212073)
`tosa.mul` and `tosa.intdiv` fold constant splat operands by building a
`DenseElementsAttr` of the result type, which asserts when that type has
a dynamic shape. When the operands are constants but the result type is
dynamic, folding aborted. Guard `mulBinaryFolder` and the `IntDivOp`
splat path on a static result shape, matching the other fold paths in
these ops.
Signed-off-by: Víctor Pérez Carrasco <victor.pc.upm at gmail.com>
[LV] Extract fixupHeaderPhiBackedges from VPlan::execute (NFC) (#212063)
Hoist the header-phi backedge fixup loop at the end of VPlan::execute
into a helper VPTransformState::fixupHeaderPhiBackedges.
clang/AMDGPU: Rename amdgcn triples to amdgpu in cc1 tests (14)
Replace the legacy amdgcn architecture name with amdgpu in various
test triples. This set of updates covers cases that did not have
a set -target-cpu.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
