LLVM/project 027bcccllvm/include/llvm/IR GlobalObject.h, llvm/lib/CodeGen CodeGenPrepare.cpp StaticDataAnnotator.cpp

[NFCI][Globals] In GlobalObjects::setSectionPrefix, do conditional update if existing prefix is not equivalent to the new one. Returns whether prefix changed. (#158460)

Before this change, `setSectionPrefix` overwrites existing section
prefix with new one unconditionally.

After this change, `setSectionPrefix` checks for equivalences, updates
conditionally and returns whether an update happens.

Update the existing callers to make use of the return value. [PR
155337](https://github.com/llvm/llvm-project/pull/155337/files#diff-cc0c67ac89807f4453f0cfea9164944a4650cd6873a468a0f907e7158818eae9)
is a motivating use case whether the 'update' semantic is needed.
DeltaFile
+80-0llvm/unittests/IR/GlobalObjectTest.cpp
+13-1llvm/lib/IR/Globals.cpp
+4-4llvm/lib/CodeGen/CodeGenPrepare.cpp
+4-2llvm/include/llvm/IR/GlobalObject.h
+2-3llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
+1-2llvm/lib/CodeGen/StaticDataAnnotator.cpp
+104-121 files not shown
+105-127 files

LLVM/project 763b167llvm/include/llvm/Analysis IR2Vec.h, llvm/lib/Analysis IR2Vec.cpp InlineAdvisor.cpp

VocabStorage
DeltaFile
+255-37llvm/unittests/Analysis/IR2VecTest.cpp
+160-57llvm/lib/Analysis/IR2Vec.cpp
+114-31llvm/include/llvm/Analysis/IR2Vec.h
+8-5llvm/unittests/Analysis/FunctionPropertiesAnalysisTest.cpp
+3-3llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp
+1-1llvm/lib/Analysis/InlineAdvisor.cpp
+541-1346 files

LLVM/project 95388b2mlir/lib/Dialect/OpenACC/IR OpenACC.cpp, mlir/test/Dialect/OpenACC invalid.mlir

[OpenACC] verify acc:DataOp operand not BlockArgument (#159148)

Similar to #158095, check that the operand of acc::DataOp is not a
BlockArgument before trying to get its defining operation so it will not
segfault and instead produce a clean error.
DeltaFile
+8-0mlir/test/Dialect/OpenACC/invalid.mlir
+2-1mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+10-12 files

LLVM/project 028ddb1llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.gfx942.ll llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll, llvm/test/CodeGen/RISCV rv32zbb.ll

Merge branch 'main' into users/kasuga-fj/da-fix-exact-siv-ovfl-2
DeltaFile
+1,794-1,900llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
+302-264llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+144-252llvm/test/CodeGen/RISCV/rv32zbb.ll
+121-242llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
+121-237llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
+157-157llvm/test/CodeGen/X86/fma_patterns.ll
+2,639-3,052294 files not shown
+8,314-7,146300 files

LLVM/project 7779882llvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis ExactSIV.ll

[DA] Add option to run only SIV routines (#157084)

This patch introduces a new option, `da-run-siv-routines-only`, which
runs only the SIV family routines in the DA. This is useful for testing
(regression tests, not dependence tests) as it helps detect behavioral
changes in the SIV routines. Actually, regarding the test cases added in
#157085, fixing the incorrect result requires changes across multiple
functions (at a minimum, `exactSIVtest`, `gcdMIVtest` and
`symbolicRDIVtest`). It is difficult to address all of them at once.

This patch also generates the CHECK directives using the new option for
`ExactSIV.ll` as it is necessary for subsequent patches. However, I
believe it will also be useful for other `xxSIV.ll` tests. Notably, the
SIV family routines tend to be affected by other routines, as they are
typically invoked at the beginning of the overall analysis.
DeltaFile
+198-0llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll
+14-0llvm/lib/Analysis/DependenceAnalysis.cpp
+212-02 files

LLVM/project f74583foffload/plugins-nextgen/common/src PluginInterface.cpp

[offload] Fix build with debug libomptarget (#159144)

Currently get this error
```
offload/plugins-nextgen/common/src/PluginInterface.cpp:859:63: error: member reference type 'StringRef' is not a pointer; did you mean to use '.'?
```

We pass the full image binary now so we can't really print anything
useful here.

Seems introduced in https://github.com/llvm/llvm-project/pull/158748.

---------

Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Co-authored-by: Joseph Huber <huberjn at outlook.com>
DeltaFile
+1-1offload/plugins-nextgen/common/src/PluginInterface.cpp
+1-11 files

LLVM/project e24f901clang/lib/Driver/ToolChains FreeBSD.h, clang/test/Driver aarch64-features.c

[Driver] Enable outline atomics for FreeBSD/aarch64 (#156089)

DeltaFile
+5-0clang/lib/Driver/ToolChains/FreeBSD.h
+3-0clang/test/Driver/aarch64-features.c
+8-02 files

LLVM/project dd56becllvm/lib/CAS MappedFileRegionArena.cpp

[CAS] Fix alignment error from MappedFileRegionArena (#159128)

Fix a bug that when an alignment error can happen when reading a slice
of file from existing MappedFileRegionArena.
DeltaFile
+6-5llvm/lib/CAS/MappedFileRegionArena.cpp
+6-51 files

LLVM/project bdf18b6llvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU flat-saddr-atomics.ll llvm.amdgcn.is.private.ll

[AMDGPU] Fold copies of constant physical registers into their uses

Co-authored-by: Jay Foad <Jay.Foad at amd.com>
DeltaFile
+384-386llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+69-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
+13-14llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
+6-7llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
+9-3llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+481-4105 files

LLVM/project 90d96b3lldb/tools/lldb-dap/Protocol ProtocolEvents.cpp ProtocolEvents.h, lldb/unittests/DAP ProtocolTypesTest.cpp

[NFC][lldb-dap] Fix typo in invalidated event (#158338)

Fixed a typo in the `invalidated` event according to
[DAP](https://microsoft.github.io/debug-adapter-protocol/specification#Events_Invalidated)
specification. While the field is `frameId` elsewhere, it must be
`stackFrameId` in this event.
DeltaFile
+2-2lldb/tools/lldb-dap/Protocol/ProtocolEvents.cpp
+2-2lldb/unittests/DAP/ProtocolTypesTest.cpp
+1-1lldb/tools/lldb-dap/Protocol/ProtocolEvents.h
+5-53 files

LLVM/project fd59fd5llvm/test/CodeGen/AMDGPU coalesce-copy-to-agpr-to-av-registers.mir rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir

[AMDGPU] Add aperture classes to VS_64 (#158823)

Should not do anything.
DeltaFile
+115-115llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
+14-14llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
+12-12llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
+8-8llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
+6-6llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
+6-6llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
+161-1615 files not shown
+174-17211 files

LLVM/project 381d31dllvm/include/llvm/IR GlobalObject.h

fix typo
DeltaFile
+3-3llvm/include/llvm/IR/GlobalObject.h
+3-31 files

LLVM/project 46fd8d0compiler-rt/lib/dfsan dfsan.cpp, compiler-rt/lib/fuzzer FuzzerLoop.cpp FuzzerDriver.cpp

Reapply "[NFC] Fix CodeQL violations in compiler-rt. (#157793)" (#157913) (#159097)

Fix below buildbot failure.

```
/var/lib/buildbot/fuchsia-x86_64-linux/llvm-project/compiler-rt/lib/fuzzer/FuzzerDriver.cpp:172:42: error: use of undeclared identifier 'uint'
  172 |           Printf("Flag: %s %u\n", Name, (uint)Val);
```

Replace uint with uint32_t cast.

This reverts commit 8062b166762b51f1c3a9168e7031babde3e330a8.
DeltaFile
+9-9compiler-rt/lib/hwasan/hwasan_report.cpp
+5-4compiler-rt/lib/dfsan/dfsan.cpp
+3-3compiler-rt/lib/fuzzer/FuzzerLoop.cpp
+2-2compiler-rt/lib/fuzzer/FuzzerDriver.cpp
+2-1compiler-rt/lib/fuzzer/FuzzerCorpus.h
+21-195 files

LLVM/project f854009mlir/lib/Dialect/Arith/IR ArithOps.cpp ArithCanonicalization.td

[mlir][arith][NFC] Minor Revisions to Comments (#158757)

This is a minor nitpick PR to fix a few comments.
DeltaFile
+1-1mlir/lib/Dialect/Arith/IR/ArithOps.cpp
+1-1mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
+2-22 files

LLVM/project 1819798lldb/packages/Python/lldbsuite/test/tools/lldb-dap dap_server.py, lldb/test/API/tools/lldb-dap/launch TestDAP_launch.py

[lldb-dap] Add stdio redirection (#158609)

As far as I understand, lldb-dap does not currently support stdio
redirection. I have added support for this via a new field in the launch
configuration named `stdio`. It was inspired by the same named field in
[CodeLLDB](https://github.com/vadimcn/codelldb/blob/master/MANUAL.md#stdio-redirection).
DeltaFile
+30-0lldb/tools/lldb-dap/Handler/RequestHandler.cpp
+29-0lldb/tools/lldb-dap/README.md
+16-0lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
+8-0lldb/tools/lldb-dap/package.json
+2-1lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
+3-0lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
+88-11 files not shown
+90-17 files

LLVM/project 3c4ab4fmlir/lib/Dialect/Tosa/Transforms TosaConvertIntegerTypeToSignless.cpp, mlir/test/Dialect/Tosa tosa-convert-integer-type-to-signless.mlir

[mlir][tosa] Handle unsigned constants in `TosaConvertIntegerTypeToSignless` (#156483)

This commit fixes handling of unsigned constant data in the
`TosaConvertIntegerTypeToSignless` pass. Previously, the type of the
"values" attribute would remain unsigned, which caused an error in the
const ops verifier:
```
error: 'tosa.const' op expected same attr/result element types
  %input_zp = "tosa.const"() {values = dense<17> : tensor<1xui8>} : () -> tensor<1xui8>
              ^
note: see current operation: %0 = "tosa.const"() <{values = dense<17> : tensor<1xui8>}> : () -> tensor<1xi8>
```
Now the constant data in "values" is transformed to signless as well.
DeltaFile
+31-0mlir/lib/Dialect/Tosa/Transforms/TosaConvertIntegerTypeToSignless.cpp
+24-0mlir/test/Dialect/Tosa/tosa-convert-integer-type-to-signless.mlir
+55-02 files

LLVM/project 1df1bf5llvm/include/llvm/IR GlobalObject.h, llvm/lib/CodeGen CodeGenPrepare.cpp StaticDataAnnotator.cpp

merge update inside set, and update callsites to make use of return value
DeltaFile
+10-14llvm/lib/IR/Globals.cpp
+9-10llvm/unittests/IR/GlobalObjectTest.cpp
+4-8llvm/include/llvm/IR/GlobalObject.h
+4-4llvm/lib/CodeGen/CodeGenPrepare.cpp
+2-3llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
+1-2llvm/lib/CodeGen/StaticDataAnnotator.cpp
+30-416 files

LLVM/project 9e9edb5llvm/lib/CAS OnDiskCommon.cpp

[CAS] Fix build for older macOS SDK (before 13.0) (#159133)

Fix a build failure and back-deployment problem for macOS before 13.0.
DeltaFile
+7-1llvm/lib/CAS/OnDiskCommon.cpp
+7-11 files

LLVM/project 0648c51llvm/test/CodeGen/AMDGPU local-stack-alloc-add-references.gfx8.mir local-stack-alloc-add-references.gfx9.mir

AMDGPU: Fix some broken regclass numbers in mir tests (#159102)

DeltaFile
+156-156llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
+90-90llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
+15-15llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
+12-12llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
+12-12llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
+8-8llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
+293-2937 files not shown
+313-31313 files

LLVM/project b76dc2blibc/src/__support/CPP simd.h, libc/src/__support/CPP/type_traits is_unsigned.h

[libc] Clean up mask helpers after allowing implicit conversions (#158681)

Summary:
I landed a change in clang that allows integral vectors to implicitly
convert to boolean ones. This means I can simplify the interface and
remove the need to cast to bool on every use. Also do some other
cleanups of the traits.
DeltaFile
+64-57libc/src/__support/CPP/simd.h
+8-6libc/test/src/__support/CPP/simd_test.cpp
+6-0libc/src/__support/CPP/type_traits/is_unsigned.h
+2-2libc/src/string/memory_utils/generic/inline_strlen.h
+80-654 files

LLVM/project b8efe1cclang/test/Driver clang_f_opts.c

[clang][nfc] Fix tests to avoid writing output to unreachable location (#159138)

Note: this was originally done in (#158698) but was reverted in the
pr/158844 (which re-applied the original rev)
DeltaFile
+3-3clang/test/Driver/clang_f_opts.c
+3-31 files

LLVM/project 198ea23llvm CMakeLists.txt

[CAS] Disable OnDiskCAS build on Solaris (#159122)

OnDiskCAS implementation receives error `No record locks available`
on Solaris. Disable building on Solaris for now to fix buildbot failure.
DeltaFile
+4-4llvm/CMakeLists.txt
+4-41 files

LLVM/project f209d63llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp, llvm/test/CodeGen/PowerPC build-vector-tests.ll mma-intrinsics.ll

[SelectionDAGBuilder][PPC] Use getShiftAmountConstant. (#158400)

The PowerPC changes are caused by shifts created by different IR
operations being CSEd now. This allows consecutive loads to be turned
into vectors earlier. This has effects on the ordering of other combines
and legalizations. This leads to some improvements and some regressions.
DeltaFile
+16-22llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+18-18llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+11-16llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+45-563 files

LLVM/project 40f2da5llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVSubtarget.h

[RISCV] Add hasREV8Like helper to RISCVSubtarget. NFC (#158775)

DeltaFile
+1-6llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+3-0llvm/lib/Target/RISCV/RISCVSubtarget.h
+4-62 files

LLVM/project be591e5.github CODEOWNERS

Add moxinilian to IRDL CODEOWNERS

This is so I get notified when an IRDL file is updated.
DeltaFile
+3-0.github/CODEOWNERS
+3-01 files

LLVM/project 2d86feallvm/lib/CAS OnDiskCommon.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6
DeltaFile
+7-1llvm/lib/CAS/OnDiskCommon.cpp
+7-11 files

LLVM/project 7bc91f3clang/test/Driver/DTLTO dtlto.c ps5-dtlto.c

[DTLTO][TEST] XFAIL Clang driver tests for Multicall toolchains (#159129)

Previously I masked issues with Multicall + DTLTO (see #148908) due to
an incomplete understanding of how the Multicall toolchain works.

This patch reverts those incorrect changes and instead marks the
affected tests XFAIL when running under Multicall.

Issue #159125 tracks fixing DTLTO with Multicall.
DeltaFile
+4-1clang/test/Driver/DTLTO/dtlto.c
+4-1clang/test/Driver/DTLTO/ps5-dtlto.c
+8-22 files

LLVM/project ff30941llvm/test/CodeGen/AMDGPU local-stack-alloc-add-references.gfx8.mir local-stack-alloc-add-references.gfx9.mir

AMDGPU: Fix some broken regclass numbers in mir tests
DeltaFile
+156-156llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
+90-90llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
+15-15llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
+12-12llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
+12-12llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
+8-8llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
+293-2937 files not shown
+313-31313 files

LLVM/project 55e6b32llvm/utils/gn/secondary/llvm/lib/Target/BPF BUILD.gn

[gn build] Port c3fb2e1cee95
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
+1-01 files

LLVM/project d0c0986mlir/test/python CMakeLists.txt

[MLIR][Python] add `not` to `MLIR_PYTHON_TEST_DEPENDS` (#159124)

[lit complains if these aren't
found](https://github.com/llvm/llvm-project/blob/95fc948c0a07953ae9d0973854336e197e36d349/llvm/utils/lit/lit/llvm/config.py#L466-L482)
(even if they're not used by a test...) so make sure to include all of
them in `MLIR_PYTHON_TEST_DEPENDS`.
DeltaFile
+1-1mlir/test/python/CMakeLists.txt
+1-11 files