LLVM/project 3a1079fllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll spill-scavenge-offset.ll, llvm/test/CodeGen/X86 2008-04-17-CoalescerBug.ll

Revert "[RegAlloc] Relax the split constrain on MBB prolog" (#169990)

Reverts llvm/llvm-project#168259

breaks hip buildot
DeltaFile
+2,852-2,897llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+283-284llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+152-159llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+95-92llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+0-167llvm/test/CodeGen/AMDGPU/spill-before-exec2.mir
+38-40llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
+3,420-3,6395 files not shown
+3,458-3,73311 files

LLVM/project d3762edllvm/docs Telemetry.rst InstCombineContributorGuide.md

[docs] Fix typos and remove redundant whitespace (#169981)

As the title says, I fixed some spelling mistakes I found in the docs.
DeltaFile
+24-24llvm/docs/Telemetry.rst
+1-1llvm/docs/InstCombineContributorGuide.md
+1-1llvm/docs/KeyInstructionsDebugInfo.md
+26-263 files

LLVM/project 66d33cellvm/test/Transforms/LoopVectorize pr58811-scev-expansion.ll

[LV] Extend test coverage for inductions depending on complex SCEVs.

Re-generate check lines, add test with complex SCEV as induction start
value and add stores to existing loops to make them not trivial.
DeltaFile
+458-109llvm/test/Transforms/LoopVectorize/pr58811-scev-expansion.ll
+458-1091 files

LLVM/project 33e5eecllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll spill-scavenge-offset.ll, llvm/test/CodeGen/X86 2008-04-17-CoalescerBug.ll

Revert "[RegAlloc] Relax the split constrain on MBB prolog (#168259)"

This reverts commit 9bae84b01718e53495abf50958abc86ea45f16bb.
DeltaFile
+2,852-2,897llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+283-284llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+152-159llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+95-92llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+0-167llvm/test/CodeGen/AMDGPU/spill-before-exec2.mir
+38-40llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
+3,420-3,6395 files not shown
+3,458-3,73311 files

LLVM/project f5742c4llvm/include/llvm/IR IntrinsicsRISCVXCV.td, llvm/lib/Target/RISCV RISCVInstrInfoXCV.td

[RISCV] Intrinsic Support for XCVelw (#129168)

DeltaFile
+27-0llvm/test/CodeGen/RISCV/xcvelw.ll
+11-0llvm/test/MC/RISCV/corev/XCVelw-pseudo.s
+8-1llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+4-0llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
+3-0llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+53-15 files

LLVM/project 5fccb47clang-tools-extra/clang-tidy/utils FormatStringConverter.cpp, clang-tools-extra/docs ReleaseNotes.rst

Revert "[clang-tidy] Fix OOB access in `FormatStringConverter` with signed ch…"

This reverts commit 5dd2b06d60d3eb9b07c7513358ad8b04386f79bc.
DeltaFile
+0-12clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-print.cpp
+3-4clang-tools-extra/clang-tidy/utils/FormatStringConverter.cpp
+3-4clang-tools-extra/docs/ReleaseNotes.rst
+0-2clang-tools-extra/test/clang-tidy/check_clang_tidy.py
+6-224 files

LLVM/project 5dd2b06clang-tools-extra/clang-tidy/utils FormatStringConverter.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix OOB access in `FormatStringConverter` with signed chars (#169215)

`FormatStringConverter::appendFormatText` incorrectly treated non-ASCII
characters (e.g. UTF-8) as negative values when using signed chars. This
caused them to pass the `< 32` check for control characters.

The negative values were passed to `llvm::hexdigit`, resulting in an OOB
access and a crash.

This closes
[#169198](https://github.com/llvm/llvm-project/issues/169198)
DeltaFile
+12-0clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-print.cpp
+4-3clang-tools-extra/docs/ReleaseNotes.rst
+4-3clang-tools-extra/clang-tidy/utils/FormatStringConverter.cpp
+2-0clang-tools-extra/test/clang-tidy/check_clang_tidy.py
+22-64 files

LLVM/project b1dfd8cllvm/lib/Target/SystemZ/MCTargetDesc SystemZMCAsmInfo.cpp SystemZHLASMAsmStreamer.cpp, llvm/test/CodeGen/SystemZ llvm.sincos.ll zos-intrinsics.ll

Use correct type extension for relocations

D means 8 byte.
DeltaFile
+12-12llvm/test/CodeGen/SystemZ/llvm.sincos.ll
+11-10llvm/test/CodeGen/SystemZ/zos-intrinsics.ll
+9-9llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll
+7-7llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
+4-4llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
+2-2llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+45-446 files

LLVM/project 58a8e1eclang-tools-extra/clang-doc JSONGenerator.cpp, clang-tools-extra/test/clang-doc basic-project.mustache.test

Address review feedback, handle extraction better
DeltaFile
+0-97clang-tools-extra/test/clang-doc/basic-project.mustache.test
+44-3clang-tools-extra/clang-doc/JSONGenerator.cpp
+0-3clang-tools-extra/test/clang-doc/json/class.cpp
+44-1033 files

LLVM/project 9bae84bllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll spill-scavenge-offset.ll, llvm/test/CodeGen/X86 2008-04-17-CoalescerBug.ll

[RegAlloc] Relax the split constrain on MBB prolog (#168259)

https://reviews.llvm.org/D52052 is to prevent register split on the MBB
which have prolog instructions defining the exec register (or mask register
that activate the threads of a warp in GPU). The constrain seems too
strict, because 1) If the split is allowed, it may fit the free live range
of a physical register, and no spill will happen; 2) The register class of
register that is under splitting may not be the same to the register that
is defined in prolog, so there is no interference with the register being
defined in prolog. 
The current code has another small issue. The MBB->getFirstNonDebugInstr()
just skip debug instructions, but SA->getFirstSplitPoint(Number) would skip
label and phi instructions. This cause some MBB with label instruction
being taken as prolog.
This patch is to relax the split constrain on MMB with prolog by checking
if the register defined in prolog has the common register class with the
register being split. It allow the split if the register defined in prolog
is physical register or there is no common register class.


    [2 lines not shown]
DeltaFile
+2,867-2,822llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+282-281llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+159-152llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+99-102llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+167-0llvm/test/CodeGen/AMDGPU/spill-before-exec2.mir
+40-38llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
+3,614-3,3955 files not shown
+3,708-3,43311 files

LLVM/project b634514llvm/lib/Target/SystemZ/MCTargetDesc SystemZMCAsmInfo.h

Fix formatting.
DeltaFile
+3-3llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h
+3-31 files

LLVM/project a112e7bllvm/lib/Target/SystemZ/MCTargetDesc SystemZHLASMAsmStreamer.cpp, llvm/test/CodeGen/SystemZ zos-hlasm-out.ll

Also test relocations
DeltaFile
+8-0llvm/test/CodeGen/SystemZ/zos-hlasm-out.ll
+3-0llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+11-02 files

LLVM/project 99addbfllvm/lib/Transforms/Vectorize VPlanConstruction.cpp, llvm/test/Transforms/LoopVectorize select-index-interleaving.ll select-umin-last-index.ll

[LV] Vectorize selecting last IV of min/max element. (#141431)

Add support for vectorizing loops that select the index of the minimum
or maximum element. The patch implements vectorizing those patterns by
combining Min/Max and FindFirstIV reductions.

It extends matching Min/Max reductions to allow in-loop users that are
FindLastIV reductions. It records a flag indicating that the Min/Max
reduction is used by another reduction. The extra user is then check as
part of the new `handleMultiUseReductions` VPlan transformation.

It processes any reduction that has other reduction users. The reduction
using the min/max reduction currently must be a FindLastIV reduction,
which needs adjusting to compute the correct result:
 1. We need to find the last IV for which the condition based on the
     min/max reduction is true,
 2. Compare the partial min/max reduction result to its final value and,
 3. Select the lanes of the partial FindLastIV reductions which
     correspond to the lanes matching the min/max reduction result.

    [3 lines not shown]
DeltaFile
+267-30llvm/test/Transforms/LoopVectorize/AArch64/select-index.ll
+208-20llvm/test/Transforms/LoopVectorize/select-index-interleaving.ll
+160-20llvm/test/Transforms/LoopVectorize/select-umin-last-index.ll
+166-10llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+120-15llvm/test/Transforms/LoopVectorize/select-umax-last-index.ll
+120-15llvm/test/Transforms/LoopVectorize/select-smin-last-index.ll
+1,041-1109 files not shown
+1,283-13415 files

LLVM/project 57486fb

Merge branch 'users/meinersbur/openmp_hoist-module' into users/meinersbur/flang_builtin-mods_2
DeltaFile
+0-00 files

LLVM/project 4e12b6cllvm/include/llvm/MC MCGOFFObjectWriter.h, llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp

Remove use of S_PLT
DeltaFile
+5-5llvm/include/llvm/MC/MCGOFFObjectWriter.h
+3-3llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h
+1-3llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGOFFObjectWriter.cpp
+2-2llvm/test/CodeGen/SystemZ/call-zos-02.ll
+3-0llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
+1-1llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+15-142 files not shown
+17-168 files

LLVM/project 6e9cf96llvm/include/llvm/BinaryFormat GOFF.h

Fix formatting.
DeltaFile
+1-4llvm/include/llvm/BinaryFormat/GOFF.h
+1-41 files

LLVM/project 87dd5fallvm/include/llvm/MC MCGOFFObjectWriter.h, llvm/lib/MC GOFFObjectWriter.cpp

Use only one vector to store the relocations.
DeltaFile
+61-89llvm/lib/MC/GOFFObjectWriter.cpp
+26-15llvm/include/llvm/MC/MCGOFFObjectWriter.h
+87-1042 files

LLVM/project 511ce34llvm/include/llvm/MC MCGOFFObjectWriter.h, llvm/lib/MC GOFFObjectWriter.cpp

Remove `IsPCRel` parameter

Information can be retrieved from `Fixup`.
DeltaFile
+5-6llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGOFFObjectWriter.cpp
+2-2llvm/include/llvm/MC/MCGOFFObjectWriter.h
+1-2llvm/lib/MC/GOFFObjectWriter.cpp
+8-103 files

LLVM/project 0d1109allvm/include/llvm/BinaryFormat GOFF.h, llvm/include/llvm/MC MCGOFFObjectWriter.h

[GOFF] Write out relocations in the GOFF writer

Add support for writing relocations. Since the symbol numbering is only
available after the symbols are written, the relocations are collected
in a vector. At write time, the relocations are converted using the
symbols ids, compressed and written out. A relocation data record is
limited to 32K-1 bytes, which requires making sure that larger relocation
data is written into multiple records.
DeltaFile
+262-4llvm/lib/MC/GOFFObjectWriter.cpp
+35-1llvm/include/llvm/MC/MCGOFFObjectWriter.h
+26-0llvm/include/llvm/BinaryFormat/GOFF.h
+24-0llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGOFFObjectWriter.cpp
+18-5llvm/test/CodeGen/SystemZ/zos-section-1.ll
+11-5llvm/test/CodeGen/SystemZ/zos-section-2.ll
+376-151 files not shown
+377-157 files

LLVM/project 126ad82llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp, llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp

Move loop to AsmPrinter
DeltaFile
+15-0llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+0-12llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+15-122 files

LLVM/project e99d8adllvm/lib/MC MCWin64EH.cpp

[MC] [Win64EH] Fix the operator ordering for UOP_SaveFPLRX. NFC.

The encoded offset should be (OffsetInBytes/8)-1 due to an
implicit offset of 1. Previously the operator ordering was
inverted. As the offset is a multiple of 8, the incorrect
operator ordering did produce the right result in all cases
anyway.
DeltaFile
+1-1llvm/lib/MC/MCWin64EH.cpp
+1-11 files

LLVM/project 8a2965dllvm/tools/llvm-readobj ARMWinEHPrinter.cpp

[llvm-readobj] Remove a leftover comment from 6ad4fdacaeea4777e98a3ab41512c49d3d1b6151. NFC.

This case did get documented upstream, in
https://github.com/MicrosoftDocs/cpp-docs/pull/4202, and the
way that llvm-readobj prints it, implemented in that commit, is
correct.
DeltaFile
+0-3llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
+0-31 files

LLVM/project c110f78llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/tools/llvm-dwarfdump/X86 simplified-template-names.s

Rebase

Created using spr 1.3.7
DeltaFile
+41,820-45,029llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+11,644-10,635llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,981-8,885llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+5,981-8,885llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+7,387-7,087llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+3,868-6,624llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v3p0.ll
+76,681-87,1459,824 files not shown
+541,993-498,4529,830 files

LLVM/project f07556allvm/lib/Target/SystemZ SystemZAsmPrinter.cpp, llvm/lib/Target/SystemZ/MCTargetDesc SystemZHLASMAsmStreamer.cpp SystemZTargetStreamer.cpp

Simplify the implementation by moving some code into finishImpl()
DeltaFile
+5-6llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+0-6llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.cpp
+0-5llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h
+0-4llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+1-2llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h
+2-1llvm/test/CodeGen/SystemZ/zos-symbol-1.ll
+8-246 files

LLVM/project 6537834llvm/lib/Target/SystemZ SystemZAsmPrinter.cpp

Remove left-over popSection()
DeltaFile
+0-1llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+0-11 files

LLVM/project 7fa4651llvm/include/llvm/MC MCSymbolGOFF.h, llvm/lib/MC MCSymbolGOFF.cpp GOFFObjectWriter.cpp

Completely remove attributes from MCSymbolGOFF
DeltaFile
+6-28llvm/lib/MC/MCSymbolGOFF.cpp
+13-2llvm/lib/MC/GOFFObjectWriter.cpp
+5-10llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+2-2llvm/include/llvm/MC/MCSymbolGOFF.h
+26-424 files

LLVM/project 4dc29b8llvm/test/Transforms/LoopVectorize select-fmin-last-index.ll select-fmax-last-index.ll, llvm/test/Transforms/LoopVectorize/AArch64 select-index.ll

[LV] Add additional argmin/argmax tests for #141431.

Apply suggestions for tests from
https://github.com/llvm/llvm-project/pull/141431 and add additional
missing coverage.
DeltaFile
+135-40llvm/test/Transforms/LoopVectorize/AArch64/select-index.ll
+128-0llvm/test/Transforms/LoopVectorize/select-fmin-last-index.ll
+128-0llvm/test/Transforms/LoopVectorize/select-fmax-last-index.ll
+82-38llvm/test/Transforms/LoopVectorize/select-umin-last-index.ll
+28-28llvm/test/Transforms/LoopVectorize/select-smax-last-index.ll
+28-28llvm/test/Transforms/LoopVectorize/select-umax-last-index.ll
+529-1343 files not shown
+568-1739 files

LLVM/project 1948989runtimes CMakeLists.txt

Exact CMake version
DeltaFile
+2-2runtimes/CMakeLists.txt
+2-21 files

LLVM/project dee0b90llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/tools/llvm-dwarfdump/X86 simplified-template-names.s

Rebase

Created using spr 1.3.7
DeltaFile
+45,267-48,746llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+11,954-11,000llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,981-8,885llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+5,981-8,885llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+7,387-7,087llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
+5,060-5,874llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+81,630-90,47716,739 files not shown
+1,216,730-593,34616,745 files

LLVM/project 063b271llvm/include/llvm/MC MCGOFFStreamer.h, llvm/lib/MC MCGOFFStreamer.cpp

Remove unused emitExterns()
DeltaFile
+0-4llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.cpp
+0-2llvm/include/llvm/MC/MCGOFFStreamer.h
+0-2llvm/lib/MC/MCGOFFStreamer.cpp
+0-1llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h
+0-94 files