[Clang][C2y] Make the 'if' declaration extension warning on by default
Declarations in the condition of 'if' and 'switch' statements (N3356)
were previously only diagnosed in pre-C2y modes under -pedantic, since
the C compatibility warnings default to Extension. Promote the
diagnostic to an ExtWarn so users on older language modes are told
they are relying on a C2y extension; -Wno-c2y-extensions silences it.
Co-Authored-By: Claude Fable 5.1 <noreply at anthropic.com>
[Clang][C2y] Simplify condition-declaration diagnostics in C
Key the diagnostics on whether a declaration is permitted as the
condition (only as the sole clause of an 'if' or 'switch'), so the two
"expected expression" emissions collapse into one and the first-clause
check is no longer nested inside the branching. No functional change.
Co-Authored-By: Claude Fable 5.1 <noreply at anthropic.com>
[OpenMP][offload] Trade threads for blocks in Generic-SPMD kernels
The threads of a Generic-SPMD block run the inner parallel loops, whose
trip counts are unknown. Halve the threads down to one warp while the
distribute loop has an iteration for every block, and default to 6
blocks per CU on AMDGPU (LIBOMPTARGET_AMDGPU_GENERIC_SPMD_TEAMS_PER_CU).
libomptarget reads the number of compute units and the platform backend
of the device through liboffload, as part of its geometry properties.
This is an upstream port of the corresponding downstream.
Claude assisted with this patch.
[AArch64][GlobalISel] Combine load+shuffles to LD2/3/4 (#230438)
Similar to #228514, this adds a combine to form a LD2/LD3/LD4 from a
load and shuffles. We start from the load and look at the uses, as we
need to match multiple shuffles. The intent is that this can be easily
extended to deinterleave intrinsics too when they are available in
gisel.
[AArch64][llvm] Combine SVE AND-NOT operations into BIC for _m forms
Replace NOT followed by merging AND with BIC for expressions such as:
return svand_u32_m(pg, a, svnot_u32_x(pg, b));
Combine when NOT is the second operand and its predicate matches the AND
predicate or is all-active.
Use predicated BIC to preserve the AND's first operand in inactive
lanes. Use unpredicated BIC when the AND predicate is all-active.
Do not commute merging AND operands, since this would change inactive
results. Leave pairs with incompatible predicates unchanged.
This applies to all integer element widths. Update the pre-commit LLVM
expectations, including cases where combining would change the
result.
[flang-rt] Fix CopyOutAssign unit tests on Darwin (#233999)
The flang-rt unittests are built with -D_POSIX_C_SOURCE=200809 on
Darwin, which hides MAP_ANON/MAP_ANONYMOUS in <sys/mman.h>.
This made AllocateAnonymousPages() fall back to mapping /dev/zero,
which Darwin doesn't support (mmap fails with ENODEV), causing the
CopyOutAssign tests that use it to fail.
Define _DARWIN_C_SOURCE before including system headers, as
trampoline.cpp already does, to re-expose the anonymous mapping flags.
Assisted-by: Claude Opus 5.5
[clang][bytecode] Lazily run ctor func of local blocks (#233250)
The problem with the attached test case is that a conditional operator
will force initialize the current variable scope, so we know that the
scope is initialized in both arms of the conditional operator. However,
this causes problems if the conditional operator (and thus its force
initialization of the scope) is itself not always executed, e.g. if
preceded by `0 &&`. In that case , the binary operator will skip the
RHS.
Remove the `InitScope` op altogether and simply call
`Block::invokeCtor()` when accessing a local variable for the first
time. This way, we automatically run the ctor, even if the `InitScope`
wasn't reached (if it still existed anyway).
This also allows us to remove a similar workaround from `Pointer.cpp`.
Fixes https://github.com/llvm/llvm-project/issues/232854
[mlir][LLVM] Add LLVMStructType::getElementOffset()
Since bb6f7fcb46cd LLVMStructType::getTypeSizeInBits() uses
allocation sizes, but there are a few places where we still
compute field offsets based on store sizes.
This change factors out the computations into a single method,
a counterpart of LLVM's StructLayout::getElementOffset(), so
that all now agree in how they do that.
Also simplify the surrounding code a bit while there.
[Triple] Simplify ELFv2 ABI and Secure PLT handling for FreeBSD (#233047)
FreeBSD 13 is the baseline supported version and it uses the
ELFv2 ABI on big-endian powerpc64 and Secure PLT on 32-bit
powerpc, so drop the OS version checks and treat all FreeBSD
targets as using them.
[Clang] Use getNonTypeTemplateArgumentType fallback in getTypeOfConstantTemplateParameter (#231983)
Follow-up to c169131b760c (#231599).
Arg.getNonTypeTemplateArgumentType() in
Sema::getTypeOfConstantTemplateParameter when Arg does not name a
constant template parameter, and remove the unnecessary T.isNull() check
in isUndeducedAuto.
[CUDA][NVPTX] Add dp4a/dp2a builtins; define CUDA-13.4's __nv_idp*_impl externs (#233434)
Since CUDA 13.4 `__dp4a/__dp2a_lo/__dp2a_hi` from `sm_61_intrinsics.hpp`
call nvcc-internal device functions and are declared as plain `extern
"C"` in the corresponding header, namely ` __nv_idp4a_{s_s,u_u}_impl,
__nv_idp2a_{lo,hi}_{s_s,u_u}_impl`.
They were implemented as inline assembly before.
As a result, Clang leaves any use of `__dp4a` as an unresolved `.extern`
in the PTX and ptxas fails with
```
ptxas fatal : Unresolved extern function '__nv_idp4a_s_s_impl'
```
The NVPTX backend already has `llvm.nvvm.idp4a.* / llvm.nvvm.idp2a.*`.
This change:
* Exposes them as builtins: `__nvvm_idp4a_{s,u}_{s,u}` and
[6 lines not shown]
[mlir] Fold traverseRegionGraph into isRegionReachable (NFC)
traverseRegionGraph had one caller, and that caller's stop condition only
compared against the target region. Inline it into isRegionReachable as a
plain worklist search. Drop the "has no parent op" error path, which cannot
fire because every region on the worklist comes from the op's own
getSuccessorRegions. insideMutuallyExclusiveRegions now returns early when
both ops are in the same region instead of running both searches first.
Assisted-by: Claude Code (Opus 5.5).
[libc++] Replace __libcpp_allocate with std::allocator in small_bufer.h (#234158)
We use `__libcpp_allocate` and frineds only in very specific
circumstances. Instead of providing a private API we can make
`std::allocator` the default API for the uses of `__libcpp_allocate`.
This is a step towards that goal.
[NFC][WebAssembly] Partial reduce precommit tests (#234142)
Create a CostModel directory for our LoopVectorize tests. Integer MAC
tests have been updated to look at more costs.
[analyzer] Default to fresh state in addTransitionImpl (#234123)
When `CheckerContext::addTransitionImpl` is called with a null `State`,
it defaulted to using the state of the node that was passed to the
constructor of `CheckerContext` -- even if the parent of the new node
(`P`) was another more recent node.
This logic could have "jumped back" to a slightly older, obsolete state
in the case when the state of `P` was distinct from the state of the
node that was passed to the constructor of `CheckerContext`. I did not
observe this in practice (and I verified that it never happens among the
LIT tests), but it is better to completely rule it out.
Using the state of `P` should be a very safe fallback choice, so I don't
expect disruptions from this change. A checker has to be _very_ buggy if
this change (i.e. _not_ forgetting its state updates) triggered buggy
behavior in it.
[AArch64] Enable quad variant st1b/ld1b for callee-saved spills (#225100)
Currently, only the pair variant is generated by callee-saved spills.
Generate quad variants when:
- 4 consecutive registers (example: z8, z9, z10, z11)
- First register will be divisible by 4. (example: z8)
- Offset will be divisible by 4. (example: 4, mul vl)
- Offset in range -32 to 28
A correction was also made in the expensive checks block, where I
corrected the c.Reg1 == PPR to c.Type == PPR
[clangd] Extract to function: Suppress pure forwarding wrappers (#232654)
Extracting a single statement that's just a lone call (or a return of
one), where every operand that would need to become a parameter is
already exactly that parameter value unchanged, produces nothing but a
renamed call: `foo(x);` becomes `void extracted(int x) { foo(x); }`
called as `extracted(x);`, with no abstraction gained. A value-less
`return;` is the same kind of no-op: there's nothing to abstract over
at all. Both are now rejected.
This is deliberately narrow and per-operand, not a naive argument-count
check: `foo(100)` (a literal), `foo(globalVar)` (an already-visible
global), and `foo(x + y)` (real computation) are all still offered,
since each does something a plain rename wouldn't.
Assisted-by: Claude Code
[Clang][C2y] Fix pre-c2y-compat expectations in c2y-if-decl-while.c
The -std=c2y run line passes -Wpre-c2y-compat, so the compat form of the
'if'/'switch' declaration diagnostic fires. Give that run a 'compat'
prefix and expect the warnings.
Co-Authored-By: Claude Fable 5.1 <noreply at anthropic.com>
[sancov][NFC] Store raw coverage addresses in a DenseSet
Union inserts the same addresses over and over. A std::set walks a tree for every one of them. A hash set checks whether the address is already present in one step. Sort once on output so the bytes stay ordered. On 5,000 llc dumps, union went from 39s to 5s.
Assisted-by: Cursor (Grok 4.7)
[sancov][NFC] Append a coverage file into an existing address set
Union was reading each .sancov file into its own address set and then
inserting that set into the union. Read the file straight into the
caller's set instead. append returns the file header so a bitness
mismatch still warns, and read is implemented on top of it.
Assisted-by: Cursor (Grok 4.7)
[X86] Remove v4i64 S/UMUL_LOHI lowering and consistently rely on MULHS/U (#231976)
Improve the MULH lowering logic - only scalarize if i64 MUL is legal
(i.e. 64-bit target) and vXi64 VPMULLQ isn't, - always for MULHS and
only for MULHU if the operands have other uses.
v8i64 is always better to stay on the FPU as scalarization is so messy,
even if we don't have VPMULLQ.
CodeGen: Stop running LiveVariables in the optimized pipeline
Nothing in the optimized register allocation pipeline requires
LiveVariables any more. The pass will subsequently be deleted. The
only tricky part here is dealing with the AMDGPU pipeline previously
using LiveVariables as an insertion point.
Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
SelectionDAG: Mark physreg defs dead on scheduler-cloned nodes
When the list scheduler clones a node to break a physreg dependency,
the copies share one SDNode, so InstrEmitter can't tell that a copy's
implicit physreg def (e.g. EFLAGS) lost its users and didn't mark it
dead. LiveVariables recomputes it later, but dead flags are most useful
to earlier optimizations.
Instead, mark the def dead at emission time if the copy has no
scheduler edge for it. This lets convertToThreeAddress form LEAs again,
and is a step toward removing LiveVariables.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
