[Hexagon] Handle trunc to i1 in matchRightShift (#174737)
Fix of test regression seen when working on
https://github.com/llvm/llvm-project/issues/172888
this will handle "trunc(x) to i1" as "icmp_ne(and(x,1),0)"
updates matchRightShift to match this pattern and promoteTo to map the
trunc to "icmp_ne(and(x,1),0)"
[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)
RISCVVectorPeephole and RISCVVLOptimizer use the ElementsDependOn field
to know if it's safe to change the VL of a vector instruction.
By default instructions are EltDepsNone, i.e.
RISCVVectorPeephole::tryReduceVL will reduce its VL by default, but we
might forget to mark unsafe instructions in newer extensions. This patch
changes the default to EltDepsVLMask and instead explicitly marks any
instructions which want to have their VL reduced.
There is an assert in RISCVVLOptimizer::isCandidate that ensures that
all previously isSupported instructions are still marked correctly.
[SelectionDAG] Use virtual registers instead of arbitrary physical registers in unit tests. NFC (#183205)
These tests use constants in the physical register space. These will
correspond to different registers on different targets and aren't
stable.
Using virtual registers makes more sense here. This will print in a
coherent way if you anyone were to dump the DAG created by these tests.
[mlir][Analysis] Print all blocks in `-test-liveness-analysis` (#183308)
Improve the output of the test pass: print liveness for block arguments
from all blocks.
[clang] allow canonicalizing assumed template names (#183222)
Assumed template names are part of error recovery and encode just a
declaration name, making them always canonical. This patch allows them
to be canonicalized, which is trivial.
Fixes #183075
[RISCV] Remove -riscv-enable-p-ext-simd-codegen (#183156)
All known crashes have been fixed.
We do still need to work out how fixed length vectors are handled when V
and P are both enabled, but I don't think this option is the solution
for that.
[RISCV] Remove unnecessary And before seteq/ne in some cases. (#183221)
Fold (and X, Mask) ==/!= C -> X ==/!= sext(C, countr_one(Mask))if the
Mask is only clearing redundant sign bits.
The AND may have come from type legalization of a narrower setcc.
Type legalization will check computeNumSignBits before inserting
the AND, but sometimes the sign bits don't appear until after
op legalization. In the motivating examples, the inputs isn't known
to be sign extended until EXTRACT_VECTOR_ELT is converted to vmv.x.s.
Spotted in the before code from #182684.
build: alter condition for adding `_DEBUG` CPP macro (#183120)
Unlike many other platforms, Microsoft does not maintain ABI across
debug and release binaries. When building LLVM in release+asserts, the
injection of `_DEBUG` which controls the behaviour of `assert` as per
the C specification, also alters the behaviour of the C/C++ runtime's
internal assertions and relies on debug only symbols. As such, the
`_DEBUG` macro handling is not _MSVC_ specific but rather MS STL and
UCRT specific. Adjust the build condition from `MSVC` to `WIN32` to
indicate that this is a Windows-ism. Note that `MINGW` is the proper way
to check for MinGW, so that should not be impacted by this change.
Making this more precise permits the use of `clang` and `clang++` to
build LLVM for Windows.
[mlir][tosa] Converted TosaAvailability pass to ModuleOp from FuncOp, fixes crash in threaded pass manager (#183063)
The `TosaAvailability` pass originally worked on a per function basis
and was automatically threaded, however it used llvm::outs() which
involves the thread-unsafe `raw_ostream`.
To fix this, we convert the pass into a pass over `ModuleOp` instead of
`FuncOp`s, and iterate sequentially over all functions instead. This
removes all threading and we no longer require `-mlir-disable-threading`
which is mentioned in TosaAvailability's `availability.mlir` test.
Closes #182255.
[profcheck] Expose likely/unlikely weights as constants in MDBuilder (#183252)
Define `kLikelyBranchWeight` and `kUnlikelyBranchWeight` as static
constexpr members in MDBuilder.h and use them in
createLikelyBranchWeights and createUnlikelyBranchWeights. This makes
the weights used for likely/unlikely branches more discoverable and
reusable.
Co-authored-by: Jin Huang <jingold at google.com>
[bazel][libc] Add some deps for layering_check (#183235)
This adds a whole bunch of deps to get things _mostly_ building w/
`layering_check` enabled. It does not yet enable `layering_check`.
I used some tools to add deps to all these targets that break when
enabling the layering check feature, and a few things were added in
between when I ran the script and where trunk is at now. Since this is a
large change, I plan to do a second (and possibly third) pass later to
catch those new changes, at which point it would be safer to actually
enable `layering_check` for this package.
[clang][ARM] Refactor argument handling in `EmitAArch64BuiltinExpr` (3/N) (NFC)
Remove the outstanding calls to `EmitScalarExpr` in
`EmitAArch64BuiltinExpr` that are no longer required.
This is a follow-up for #181794 and #181974 - please refer to that PR
for more context.
[clang] allow canonicalizing assumed template names
Assumed template names are part of error recovery and encode just a
declaration name, making them always canonical. This patch allows
them to be canonicalized, which is trivial.
Fixes #183075
[clang][TypePrinter][NFC] Extract logic that handles AnonymousTagNameStyle::SourceLocation into helper function (#183304)
In https://github.com/llvm/llvm-project/pull/168533 we're adding a new
`AnonymousTagMode` and will be handled in `printAnonymousTagDecl`.
This patch extracts the logic that handles
`AnonymousTagNameStyle::SourceLocation` into a helper function to make
`printAnonymousTagDecl` easier to follow.
Drive-by changes:
* While copying the code into the helper I changed it to use
early-return style.
[clang] create local instantiation scope for matching template template parameters (#183219)
This fixes a bug where a partial substitution from the enclosing scope
is used to prepopulate an unrelated template argument deduction.
Fixes #181166
[lldb][Process/FreeBSDKernel] Add arm support (#180674)
This is LLDB version of
https://cgit.freebsd.org/ports/tree/devel/gdb/files/kgdb/arm-fbsd-kern.c.
This enables selecting arm and reading registers from PCB structure on
core dump and live kernel debugging while trapframe unwinding support
will be implemented in future. Test files using core dump from arm will
be implemented once other kernel debugging improvements are done.
---------
Signed-off-by: Minsoo Choo <minsoochoo0122 at proton.me>
[NFC][RegisterInfoEmitter] Add target name prefix for a few variables (#183074)
Add target name prefix for a few static global variables in the
generated code. Also rework the TargetRegisterInfo constructor a bit to
use a ArrayRef for array of register classes and rename a few
constructor arguments to match the member names they initialize.
AMDGPU: Implement expansion for f64 exp
I asked AI to port the device libs reference implementation.
It mostly worked, though it got the compares wrong and also
missed a fold that happened in compiler. With that fixed I get
identical DAG output, and almost the same globalisel output (differing
by an inverted compare and select). Also adjusted some stylistic choices.
[clang][ARM] Refactor argument handling in `EmitAArch64BuiltinExpr` (3/N) (NFC)
Remove the outstanding calls to `EmitScalarExpr` in
`EmitAArch64BuiltinExpr` that are no longer required.
This is a follow-up for #181794 and #181974 - please refer to that PR
for more context.
[SPIRV] Enable SPV_EXT_relaxed_printf_string_address_space by default for Intel (#183103)
It's easy to hit the address space limitation when using printf locally,
so just enable the extension by default for Intel.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Rename Thumb1 SetResultRegister to ReturnResult
Also remove the return instructions following it in the main macro,
which aren't needed, since it does the returning itself.
[InstCombine] Replace alloca with undef size with poison instead of null
When an alloca instruction has an undef (or poison) array size, InstCombine
was previously replacing all uses of the alloca with a null pointer. This
caused invalid IR when the alloca was used by @llvm.lifetime intrinsics.
According to the @llvm.lifetime intrinsic specification, the pointer
argument must be either:
- A pointer to an alloca instruction, or
- A poison value
Since null is neither an alloca pointer nor poison, the previous
transformation violated the intrinsic's requirements and produced
invalid IR.
Fix by replacing the alloca with a poison value instead of null, which
satisfies the @llvm.lifetime requirements and produces valid IR.
Rename Thumb1 SetResultRegister to ReturnResult
Also remove the return instructions following it in the main macro,
which aren't needed, since it does the returning itself.
