[mlir][SPIR-V] Verify ExecutionMode operand count and kind (#212828)
Add a verifier for spirv.ExecutionMode enforcing the correct number of
literal operands per execution mode and rejecting `<id>`-only modes and
share the operand schema with spirv.ExecutionModeId
[AMDGPU] Limit register pressure of pipelined loops
Opt AMDGPU into the generic MachinePipeliner register-pressure detector via
shouldLimitRegPressure(), and supply an occupancy-aware verdict in
isScheduleRegPressureTooHigh(): reject a schedule whose SGPR or VGPR/AGPR
pressure would drop the kernel below its target occupancy, or exceed a
register class's addressability cap. On gfx90a+ VGPRs and AGPRs share one
register file, so their combined footprint is bounded together. These match
the limits GCNSchedStrategy enforces.
[libc++] Tweak comments for workaround about `fpclassify` overloads (#212388)
Explaining why we have `_LIBCPP_PREFERRED_OVERLOAD` and template
versions.
[AArch64][Windows] Fix swift async context slot placement (#212922)
Swift async functions can miscompile on Windows ARM64 at `-O2`, when
there's enough register pressure that a local gets scavenged into the
callee-save area: the local ends up sharing an address with the saved
caller x29, so the epilogue restores a value the function has already
overwritten. swiftlang/swift#90920 has a reduced repro.
`assignCalleeSavedSpillSlots` creates the swift async context object
before the callee-save loop instead of inside it next to the FP slot.
MachineFrameInfo ends up with it above the frame record while the
prologue stores it below at FP-8, and the 8 byte disagreement leaves a
hole in the middle of the callee-save area. PEI's scavenger hands that
hole to the local. Only reproduces at -O2 and up since scavenging is
gated on the opt level.
```
sub sp, sp, #112
str x19, [sp, #16] // 8-byte Spill
[22 lines not shown]
[Verifier] Clean up load atomic elementwise mem access sizes check (NFC) (#213864)
I refactored the `load atomic elementwise` check to have the same
cleaner pattern as `atomicrmw elementwise` and remove the `ScalarTy`
intermediate.
The previous code had this segment:
```
if (VecTy) {
checkAtomicMemAccessSize(ScalarTy, &LI);
ScalarTy = VecTy->getElementType();
}
```
Which is confusing because it's checking the atomic access size on the
whole vector and then assigning `ScalarTy` to the element type so that
the second check does the check on the element type. It's cleaner to
reverse this and have the first check operate on the element type so
that the second check always checks the entire type.
[libc++] Granularize <__locale> into __locale_dir (#213667)
The <__locale> header was a collection of distinct utilities. This patch
splits it up into granular headers under __locale_dir/. This patch
however does not use the granular headers from users of <__locale>: this
will be done in a separate patch.
Assisted by Claude
[Verifier] Reject elementwise atomicrmw with sub-byte element type (#213753)
In https://github.com/llvm/llvm-project/pull/208510/ I accidentally
introduced a bug where I allowed sub-byte element types with atomicrmw
elementwise (i.e. `<8 x i1>`).
The LangRef states:
```
The access type
must then be a fixed vector type whose total bit width is a power of two and
whose element type is supported by the corresponding scalar atomic instruction.
```
The second part of this sentence rejects sub-byte element types.
The fix is that elementwise atomics need to additionally call
`checkAtomicMemAccessSize` on the vector element type (they already call
it on the whole vector).
[dyndbg][AsmPrinter] Add tail padding attributes (#194852)
"tail-pad-to-size"="n": Pad functions up to at least 'n' bytes.
"tail-pad-value"="n": Pad using the value 'n' (default 0).
This patch is to support dynamic debugging, RFC:
https://discourse.llvm.org/t/90113
In order to transfer control from an optimized to an unoptimized function a
debugger may patch the optimized version with a jump to the unoptimized
one.
This patch adds a mechanism to ensure there's enough padding between functions
to avoid patches overwriting unrelated code. It adds padding to the end of
functions smaller then 'n' bytes.
The `.fill` directive expression was discussed here:
https://discourse.llvm.org/t/89658
See the RFC and pull request for discussions of alternative approaches.
[RISCV] Lower scalar `CLMUL` to `vclmul` if `clmul` instruction not available (#212616)
The `Zbc` and `Zvbc` extensions in RISC-V are independent, thus some
hardware may support `Zvbc` (`vclmul(h)`), but not `Zbc` (`clmul(h)`).
Rather than forcing scalar `CLMUL(H)` to expand in this case, simply
insert into a vector register, use `vclmul(h)`, and extract instead.
For now, only allow this for RV64, where `clmul` and `vclmul` both
operate on the same width. RV32 has the potential for similar tricks,
but it would be more complicated, and is left as a FIXME for now.
[lldb][test] Skip the API tests a WebAssembly target cannot support (#213788)
This is the final batch of skips. Together with a handful of local
changes to LLDB and WAMR, the test suite now passes when targeting
WebAssembly. Each test has a short comment explaining why it's skipped.
[mlir][ArmSVE] move transform entry points into arm_sve namespace (NFC) (#213949)
This PR moves `populateLowerContractionToSVE*` entry points into the
`arm_sve` namespace for consistency with their Arm Neon counterparts.
[dsymutil][ARM][NFC] Require AArch64 for fat-dylib-update.test (#213836)
fat-test.arm.dylib contains armv7, armv7s, and arm64 slices, so the test
needs the AArch64 backend in addition to ARM.
