[BOLT][RISCV] Add RV32 bare-metal support (#193913)
Enable BOLT to read, analyze, and rewrite 32-bit RISC-V (RV32) ELF
binaries. This lets us use BOLT as the core of our internal binary
analysis tooling for RV32 targets.
Scope is limited to statically linked, non-PIE programs. PLT, GOT,
dynamic relocations, TLS, and the instrumentation runtime are out of
scope for this change yet, and we plan to support those stuff in future
changes.
[DebugInfo][test] Replace Intel-proprietary intrinsics in fortran-basic.ll [NFC] (#198697)
The test was originally captured from Intel's Fortran compiler and
references two intrinsics that have never existed in upstream LLVM:
- @llvm.intel.subscript.p0.i64.i64.p0.i64 was only declared and never
called, so it can simply be dropped.
- @llvm.for.cpystr.i64.i64.i64 lowers to a string copy; rewrite the one
call site using @llvm.memcpy.p0.p0.i64. The test only checks the emitted
CodeView debug info, so the precise lowering of the string copy does not
matter.
[AMDGPU] Enable support for Wave64 on gfx13 (#198629)
This is a temporary workaround needed to unblock ongoing GFX13-related
changes. This will be removed by
https://github.com/llvm/llvm-project/pull/197991
[AMDGPU][test] Replace invalid intrinsic calls in two tests [NFC] (#198696)
These tests reference intrinsics that do not exist:
- sched.barrier.inverted.mask.ll calls @llvm.amdcn.s.nop, a typo of
@llvm.amdgcn.s.nop that has been in the test since it was added in
f1156fb622a7.
- si-split-load-store-alias-info.ll calls
@llvm.amdgcn.wmma.f32.16x16x16.f32, which has never existed (only the
.f16/.bf16/.fp8/.bf8 input variants are defined). The intrinsic was only
used to keep the loaded value alive between the load and the store; an
fadd serves the same purpose while exercising the same alias-info
propagation path being tested.
The dyn_cast<IntrinsicInst> we rely on in passes such as
ReplaceWithVeclib only checks the "llvm." prefix and does not validate
the intrinsic name, so these calls have silently become IntrinsicInst
with Intrinsic::not_intrinsic. Fix the tests so that strengthening the
check does not turn into a spurious regression.
Assisted-by: Opus 4.7
[GlobalISel] Add tablegen pattern for shufflevector combine (#198514)
Related to #197693 which filters the worklist to only include opcodes
for which there are combines. It's mostly handled by canMatchOpcode
which is tablgen'ed but some old combines like this shufflevector one
are missing a tablegen pattern and require extra handling. This adds a
simple wrapper so it gets picked up by canMatchOpcode and we can delete
the C++ handling.
I was expecting this to be NFC but it does change codegen on AMDGPU. I
tried re-ordering the patterns so the old shuffle combine comes before
this one but it didn't help.
Assisted-by: codex
[Analysis][NFC] Reduce memory usage of CodeMetrics (#198518)
FunctionSpecializer will keep the CodeMetrics of many functions at the
same time, causing the hash table in CodeMetrics to substantially
contribute to overall memory usage. Therefore, replace the DenseMap with
a vector indexed by block number.
On ArrayFunctionsRegistration.bc, this reduces the memory usage at the
time IPSCCP runs from 655.0MiB to 577.5MiB (measured with massif).
[libc] Use scope_exit to clean up resources in tests (#196120)
Simplify socket and FILE unit tests by using the `scope_exit` helper to
automatically clean up resources (sockets and FILE pointers), preventing
leaks on test failures.
Assisted by Gemini.
[cmake][runtimes] Refactor passthrough option handling into a macro (#198504)
Deduplicates code and enables making fixes in just one place instead of two.
[ARM][test] Replace removed @llvm.arm.neon.vshiftn calls with lshr+trunc [NFC] (#198693)
@llvm.arm.neon.vshiftn was removed in 170daafe015f (2014), which
intentionally replaced the intrinsic with the plain shift+truncate IR
sequence. The 2012-08-27-CopyPhysRegCrash.ll regression test was added
before that change and still calls the removed intrinsic; the call
silently lowers to an external call because @llvm.arm.neon.vshiftn no
longer corresponds to any known intrinsic.
Rewrite the two call sites with the lshr+trunc form the removal commit
documents as the canonical replacement. The test only checks that
codegen does not crash, so behaviour is preserved.
[ELF] -r: Don't let a weaker offset-0 R_RISCV_ALIGN suppress ALIGN synthesis (#198147)
PR #151639 skipped synthesizing the section-start R_RISCV_ALIGN whenever
any R_RISCV_ALIGN existed at offset 0, regardless of its alignment. This
works with newer LLVM integrated assembler (#150816).
However, older MC and GNU Assembler as of today
(https://sourceware.org/bugzilla/show_bug.cgi?id=33236) can carry a weak
offset-0 R_RISCV_ALIGN (addend 2 => align 4) while its real alignment
requirement comes from a `.option norelax` .balign, which emits no
relocation.
Fix the condition to not suppress synthesis.
Link: https://sourceware.org/bugzilla/show_bug.cgi?id=33236#c4
[lldb] Recheck connection state in webinspector-wasm EnsureConnected (#198701)
m_remote_platform_sp can be non-null while the remote is disconnected
(PlatformWasm::ConnectRemote installs the pointer before the connect
call). Also check IsConnected() so a prior failed connect doesn't make
EnsureConnected falsely report success.
[clang] Don't cutoff parsing when load C++ named module failed (#187858)
Since https://github.com/llvm/llvm-project/pull/173130, clang convert
module name pp-token sequence into a annot_module_name token for C++20
module/import directive. This PR follows the changes and correct the
module name handling in clangd.
This PR avoid parsing cutoff when hit an C++ named module loading.
Fixes https://github.com/llvm/llvm-project/issues/181358.
Signed-off-by: yronglin <yronglin777 at gmail.com>
[clang][tooling] Handle C++20 annot_module_name in syntax tokens (#198544)
The token collector will ignore all the annotation tokens, but IIUC, the
annot_module_name shoulde not be ignored.
Signed-off-by: yronglin <yronglin777 at gmail.com>
[dsymutil] Update modules test for divergence between the two linkers (#198661)
The parallel linker keeps DW_AT_GNU_dwo_id on linked CUs while the
classic linker drops it. Gate the four `CHECK-NOT: DW_AT_GNU_dwo_id`
assertions to a CLASSIC-only prefix so the test reflects the actual,
intended behavior of each linker.
[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs
These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.
Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
[AMDGPU] Implement CFI for CSR spills
Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.
Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.
Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[Clang] Default to async unwind tables for amdgcn
To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.
There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.
Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
[AMDGPU] Emit entry function Dwarf CFI
Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.
Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Implement CFI for non-kernel functions
This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.
Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU
While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).
Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
[MIR] Error on signed integer in getUnsigned
Previously we effectively took the absolute value of the APSInt, instead
diagnose the unexpected negative value.
Change-Id: I4efe961e7b29fdf1d5f97df12f8139aac12c9219
