LLVM/project b66895b — lld/ELF MarkLive.cpp

[ELF] MarkLive: Walk each level depth-first with work sharing on idle. NFC (#242181)

markParallel (#189321) visits each queued section's subtree to depth 3.
On deep narrow graphs the level barrier overhead is large.

Adopt the approach of #240243 (lld/MachO): each worker claims chunks of
a level and walks depth-first on its own stack. Once another worker is
idle, try donating the stack to the next level, but only after 256
visits in this level to avoid barrier overhead due to entering the next
level.
DeltaFile
+40-24lld/ELF/MarkLive.cpp
+40-241 files

LLVM/project 1303f6b — llvm/lib/Target/RISCV RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rvp-widening-convert-isel.ll

[RISCV][P-ext] Add the missing zext_invec pattern (#242288)

Fixes #242268. We mark `v2i32 zext_invec` as legal, but we missed the
pattern `v8i8 -> v2i32`.
DeltaFile
+30-0llvm/test/CodeGen/RISCV/rvp-widening-convert-isel.ll
+2-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+32-02 files

LLVM/project fb99825 — llvm/include/llvm/CodeGen CommandFlags.h, llvm/lib/CodeGen CodeGenToolOptions.td CommandFlags.cpp

[CodeGen] Declare most CommandFlags options in TableGen (#242159)

Move the 34 RegisterCodeGenFlags options that only
codegen::getTargetOptions and codegen::setFunctionAttributes read into a
private CodeGenToolOptions struct, which codegen::getToolOptions adds to
the tool options, and remove their getters from CommandFlags.h.
getNumOccurrences checks become optional fields.

Like other tool options, these are listed only by -help-hidden.
clang-linker-wrapper, which does not pass the tool options, now rejects
them in -mllvm and --offload-opt.

LLM-aided
DeltaFile
+103-371llvm/lib/CodeGen/CommandFlags.cpp
+37-99llvm/include/llvm/CodeGen/CommandFlags.h
+93-0llvm/lib/CodeGen/CodeGenToolOptions.td
+35-24llvm/tools/llc/lib/llcdriver.cpp
+17-13llvm/tools/opt/optdriver.cpp
+13-13llvm/tools/lli/lli.cpp
+298-52018 files not shown
+391-57624 files

LLVM/project a241fe2 — flang-rt/lib/runtime ieee_arithmetic.f90, flang/docs F202X.md

[flang] Classify IEEE_ARITHMETIC subroutines as SIMPLE and fix DO CONCURRENT checks (#232479)

Mark IEEE rounding and underflow mode subroutines as `SIMPLE` per F2023.
Fix intrinsic-module provenance checking for C1145/C1146, update the
prohibited procedure list, and add regression tests.

F2023 C1145 no longer prohibits `IEEE_SET_FLAG` inside `DO CONCURRENT`,
so these calls are now accepted.

Fixes #231858
DeltaFile
+52-1flang/test/Semantics/doconcurrent01.f90
+33-0flang/test/Semantics/ieee-arithmetic-simple.f90
+8-8flang/lib/Semantics/check-do-forall.cpp
+6-6flang-rt/lib/runtime/ieee_arithmetic.f90
+3-1flang/docs/F202X.md
+102-165 files

LLVM/project ed00c57 — clang/include/clang/Driver Distro.h, clang/lib/Driver Distro.cpp

Add support for Ubuntu 27.04 - Tenacious T-Rex (#242284)
DeltaFile
+2-1clang/include/clang/Driver/Distro.h
+1-0clang/lib/Driver/Distro.cpp
+3-12 files

LLVM/project 16b64c6 — llvm/lib/CodeGen RegisterCoalescer.cpp, llvm/test/CodeGen/X86 coalescer-erasable-implicit-def-partial-redef.mir

[RegisterCoalescer] Keep endpoints of lane-carrying IMPLICIT_DEF (#230141)

Since #196895, pruneValues discards the endpoints of a value copied from
an erasable IMPLICIT_DEF. A partial IMPLICIT_DEF without `<read-undef>`
carries other lanes those endpoints may read, so discarding them leaves
a hole in the live range. Keep them unless the source has no ValidLanes.

Assisted-by: Claude Opus 5.5
DeltaFile
+67-0llvm/test/CodeGen/X86/coalescer-erasable-implicit-def-partial-redef.mir
+14-7llvm/lib/CodeGen/RegisterCoalescer.cpp
+81-72 files

LLVM/project 688e223 — llvm/include/llvm/IR InstrTypes.h, llvm/lib/IR Instruction.cpp Instructions.cpp

Attributor: Volatile calls may access inaccessible memory (#239071)

AAMemoryLocation only used the callee's memory locations for calls, so
a function doing a volatile memcpy between its arguments was
memory(argmem: readwrite). Add inaccessible memory for volatile calls,
as CallBase::getMemoryEffects does.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+42-0llvm/test/Transforms/Attributor/memory-location-volatile-intrinsics.ll
+16-0llvm/lib/IR/Instructions.cpp
+1-13llvm/lib/IR/Instruction.cpp
+14-0llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+4-4llvm/test/Transforms/Attributor/nosync.ll
+4-0llvm/include/llvm/IR/InstrTypes.h
+81-176 files

LLVM/project 5185c50 — llvm/test/Analysis/CostModel/AArch64 shuffle-other.ll

Merge branch 'users/mrsidims/aarch64-narrow-two-source-shuffle-tests' into users/mrsidims/aarch64-narrow-two-source-shuffle-cost
DeltaFile
+31-31llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
+31-311 files

LLVM/project 2cceab7 — llvm/test/CodeGen/ARM/GlobalISel arm-instruction-select-combos.mir arm-instruction-select.mir

ARM: Use inline register class syntax in MIR tests (#242053)

Delete the registers section when unnecessary.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+297-663llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+168-394llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+168-378llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
+141-313llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-binops.mir
+130-303llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+102-226llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
+1,006-2,277183 files not shown
+1,792-4,684189 files

LLVM/project c82da66 — offload/plugins-nextgen/cuda/src rtl.cpp

[Offload][Cuda] make getAllocInfo report not found on host ptr (#242363)

On some newer CUDA stacks getAllocInfo returns success on host pointers
even it doesn't provide information. Make the call return `NOT_FOUND` in
this situation as other plugins.

Fixes regression from #241895

Bug analysis and solution provided by Claude.

---------

Co-authored-by: Ivan R. Ivanov <iivanov at nvidia.com>
DeltaFile
+7-0offload/plugins-nextgen/cuda/src/rtl.cpp
+7-01 files

LLVM/project 0104168 — libc/include/llvm-libc-macros cfloat128-macros.h

[libc] Update minimum clang version for cfloat128. (#242396)

This fixes a build issue caused by #241999, which updated the minimum
version for using `__float128`.

A follow-up will move LIBC_TYPES_HAS_FLOAT128 from
llvm-libc-types/float128.h to llvm-libc-macros/ so it can be used in
cfloat128-macros.h.
DeltaFile
+2-2libc/include/llvm-libc-macros/cfloat128-macros.h
+2-21 files

LLVM/project d064823 — llvm/test/Transforms/SLPVectorizer/X86 or-like-select-chain.ll

[SLP][NFC]Add extra or select tests, NFC

Pull-request: https://github.com/llvm/llvm-project/pull/242401
DeltaFile
+126-0llvm/test/Transforms/SLPVectorizer/X86/or-like-select-chain.ll
+126-01 files

LLVM/project 5e59267 — llvm/include/llvm/IR PassManagerImpl.h

format
DeltaFile
+1-2llvm/include/llvm/IR/PassManagerImpl.h
+1-21 files

LLVM/project 66ada7f — clang/test/CIR/CodeGen no-odr-use.cpp array.cpp, clang/test/CIR/CodeGenOpenCL amdgpu-array-subscript.cl

[CIR] Lower get_element's leading zero with the index's type

The GEP that cir.get_element lowers to starts with a zero index.  It was
a raw constant, which MLIR's translation always emits as i32, so CIR
produced `getelementptr [N x T], ptr %p, i32 0, i64 %i` where classic
codegen produces `i64 0, i64 %i`.  The zero is now a constant of the
index operand's type, so the two match on x86_64 and on AMDGPU for flat,
global and constant pointers.

In AMDGPU's 32-bit private and local address spaces, the lowering
truncates the index to i32 before the GEP, so both indices are i32 there
while classic codegen keeps them i64.

Assisted-by: Cursor / Claude Opus 5.5
DeltaFile
+20-62clang/test/CIR/CodeGen/array-subscript-inbounds.c
+39-0clang/test/CIR/CodeGenOpenCL/amdgpu-array-subscript.cl
+18-18clang/test/CIR/CodeGenOpenMP/device-array-subscript.c
+14-4clang/test/CIR/Lowering/get-element.cir
+8-8clang/test/CIR/CodeGen/array.cpp
+6-6clang/test/CIR/CodeGen/no-odr-use.cpp
+105-988 files not shown
+127-12114 files

LLVM/project 03ca4b5 — llvm/lib/Target/MSP430 MSP430InstrInfo.td

[MSP430] Use INSERT_SUBREG of IMPLICIT_DEF for anyext. NFC (#242305)

SUBREG_TO_REG means that the instruction defining the subregister also
defined the other bits of the register, which is not true in general
for the i8 operand of an anyext. The high byte of an anyext is
undefined,
which is what INSERT_SUBREG into an IMPLICIT_DEF expresses.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>

---

<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+1-1llvm/lib/Target/MSP430/MSP430InstrInfo.td
+1-11 files

LLVM/project 4097c7a — llvm/lib/Target/MSP430 MSP430InstrInfo.td, llvm/test/CodeGen/MSP430 zext-i8.ll

[MSP430] Fix zext of i8 values not defined by a byte instruction (#242304)

A byte instruction that writes a register clears the high byte of the
register, so a zext of its result can be selected to SUBREG_TO_REG. The
def8 predicate that checks for this excluded a few nodes that are known
not to be selected to such an instruction, but allowed everything else.
This included select and variable shifts, which are expanded into
control flow with a PHI, so the high byte was not cleared on some paths:

```
  bit #1, r12
  jne .LBB1_2
  mov.b r14, r13
.LBB1_2:
  mov r13, r12 ; high byte of %x is not cleared
```

Change def8 to only allow nodes that are always selected to a single
byte instruction that writes a register.

    [9 lines not shown]
DeltaFile
+22-7llvm/lib/Target/MSP430/MSP430InstrInfo.td
+6-5llvm/test/CodeGen/MSP430/zext-i8.ll
+28-122 files

LLVM/project 4147abd — llvm/test/CodeGen/MSP430 zext-i8.ll

[MSP430] Precommit tests for zext of i8 select and variable shift. NFC (#242303)

These are currently miscompiled: the zext of an i8 value is assumed to
be
free because byte instructions that write a register clear its high
byte, but select and variable shifts are expanded into control flow with
a PHI, so on some paths no byte instruction clears the high byte.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>

---

<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+74-0llvm/test/CodeGen/MSP430/zext-i8.ll
+74-01 files

LLVM/project 6a9d123 — llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp, mlir/test/Target/LLVMIR omptarget-depend.mlir omptarget-nowait.mlir

[OMPIRBuilder] Omit redundant zero-offset GEP (#242374)
DeltaFile
+6-25llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+2-6mlir/test/Target/LLVMIR/omptarget-nowait.mlir
+2-6mlir/test/Target/LLVMIR/omptarget-nowait-llvm.mlir
+1-2mlir/test/Target/LLVMIR/omptarget-depend.mlir
+11-394 files

LLVM/project dcda889 — llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU fdiv.bf16.ll llvm.log2.bf16.ll

[AMDGPU] Mitigate TRANS f16 to partial VGPR write WAW hazard

Fixes: ROCM-33929
DeltaFile
+175-0llvm/test/CodeGen/AMDGPU/hazard-partial-trans-f16-write.mir
+113-0llvm/test/CodeGen/AMDGPU/hazard-partial-trans-f16-write-fake16.mir
+91-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+29-16llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
+24-13llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
+10-7llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
+442-365 files not shown
+459-4011 files

LLVM/project d38c5b4 — llvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/MachineVerifier/AMDGPU verify-scale-offset.mir

[AMDGPU] Lowercase error messages in scale_offset verifier (#241541)
DeltaFile
+2-2llvm/test/MachineVerifier/AMDGPU/verify-scale-offset.mir
+2-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+4-42 files

LLVM/project 20112db — llvm/test/Analysis/CostModel/AArch64 shuffle-other.ll

use poison operands
DeltaFile
+31-31llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
+31-311 files

LLVM/project 10e9d4f — mlir/lib/Dialect/LLVMIR/IR NVVMSyncOps.cpp NVVMTcgenOps.cpp

[mlir][NVVM] Partition the NVVM dialect ops

Including `NVVMDialect.h` is expensive. The header declares all 219 ops of the dialect regardless of how many ops are being used by an includer.
The dialect library pays the same price: each of its 12 TUs includes all op declarations through a precompiled `NVVMDialect.h`, including the 8 TUs that each define an eighth of the ops and `NVVMDialect.cpp`, which implements all of them.

This patch replaces the index sharding with op partitions ("logical sharding", #239254). The ops are grouped by topic into 10 partitions.
Every partition has its own header, which declares the ops of the partition, and its own source file, which defines them together with their hand-written implementations (verifiers, parsers, printers, builders, intrinsic lowerings, etc.).

`NVVMDialect.h` stays as an umbrella header that includes all partition headers, but its use is discouraged. Its includers in MLIR and flang now include what they use instead unless they require the majority of the headers.

Measurements where "Memory" is the sum of the max RSS of every TU, and the users are the TUs in MLIR outside the dialect library that include NVVM dialect headers:

| TUs                          | Compiler | Wall time (s)       | CPU time (s)       | Total memory (GiB)  |
|------------------------------|----------|---------------------|--------------------|---------------------|
| `MLIRNVVMDialect` (12 -> 14) | clang    | 22.3 -> 20.1 (-10%) | 208 -> 193 (-7%)   | 9.1 -> 8.6 (-5%)    |
| `MLIRNVVMDialect` (12 -> 14) | clang -g | 26.4 -> 24.8 (-6%)  | 241 -> 234 (-3%)   | 9.7 -> 9.1 (-6%)    |
| `MLIRNVVMDialect` (12 -> 14) | gcc      | 25.3 -> 21.9 (-13%) | 222 -> 198 (-11%)  | 14.9 -> 14.0 (-6%)  |
| `MLIRNVVMDialect` (12 -> 14) | gcc -g   | 36.8 -> 33.4 (-9%)  | 324 -> 296 (-9%)   | 21.0 -> 18.8 (-10%) |
| Users (10)                   | clang    | 27.8 -> 24.3 (-13%) | 176 -> 149 (-15%)  | 9.3 -> 8.0 (-14%)   |

    [3 lines not shown]
DeltaFile
+11-7,501mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+2,452-0mlir/lib/Dialect/LLVMIR/IR/NVVMMmaOps.cpp
+1,333-0mlir/lib/Dialect/LLVMIR/IR/NVVMConvertOps.cpp
+1,173-0mlir/lib/Dialect/LLVMIR/IR/NVVMMemoryOps.cpp
+1,118-0mlir/lib/Dialect/LLVMIR/IR/NVVMTcgenOps.cpp
+781-0mlir/lib/Dialect/LLVMIR/IR/NVVMSyncOps.cpp
+6,868-7,50141 files not shown
+8,389-7,58947 files

LLVM/project 20df00f — clang/include/clang/Basic DiagnosticGroups.td DiagnosticSemaKinds.td, clang/test/ParserHLSL group_shared.hlsl group_shared_202x.hlsl

[HLSL][202x][0010] Update auto keyword to be an HLSL 202x extension instead of 202y (#242101)

Create a 202x diag group. Update the HLSL auto warning to be in the 202x
diag group instead of 202y. Emit the warning if the HLSL version is
below 202x instead of 202y. Add a new test which checks for the warning,
and update existing tests.
Closes #240492
DeltaFile
+23-0clang/test/SemaHLSL/Language/Auto-warning.hlsl
+0-7clang/test/SemaHLSL/group_shared_202x.hlsl
+0-5clang/test/ParserHLSL/group_shared_202x.hlsl
+2-2clang/include/clang/Basic/DiagnosticSemaKinds.td
+2-1clang/include/clang/Basic/DiagnosticGroups.td
+0-2clang/test/ParserHLSL/group_shared.hlsl
+27-173 files not shown
+28-209 files

LLVM/project 4f5c273 — llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp, llvm/test/Analysis/CostModel/AArch64 shuffle-other.ll

apply review
DeltaFile
+12-12llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+4-4llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
+16-162 files

LLVM/project fa5211e — llvm/lib/Transforms/Instrumentation DataFlowSanitizer.cpp, llvm/test/Instrumentation/DataFlowSanitizer abilist_aggregate.ll abilist.ll

[DFSan] Omit redundant zero-offset GEP (#242367)
DeltaFile
+2-6llvm/test/Instrumentation/DataFlowSanitizer/origin_abilist.ll
+2-4llvm/test/Instrumentation/DataFlowSanitizer/abilist.ll
+2-2llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
+1-2llvm/test/Instrumentation/DataFlowSanitizer/abilist_aggregate.ll
+7-144 files

LLVM/project f8bd16b — clang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp, clang/test/CIR/Transforms/abi-lowering amdgpu-union.cir

add tests and fix store align for packed
DeltaFile
+173-1clang/test/CIR/Transforms/abi-lowering/amdgpu-union.cir
+5-0clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+178-12 files

LLVM/project a537687 — llvm/include/llvm/CodeGen BasicTTIImpl.h, llvm/test/Analysis/CostModel/AMDGPU frexp.ll

[BasicTTIImpl] Add cost entries for powi and frexp (#242360)
DeltaFile
+96-96llvm/test/Analysis/CostModel/AMDGPU/frexp.ll
+40-40llvm/test/Analysis/CostModel/X86/powi.ll
+6-0llvm/include/llvm/CodeGen/BasicTTIImpl.h
+142-1363 files

LLVM/project 48248dc — flang/test/Fir/OpenMP bounds-generation-for-char-arrays.f90, mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[Flang][OpenMP] Fix non-contiguous and empty target updates (#240503)

Fix compiler lowering and runtime handling of non-contiguous `target
update` operations so multidimensional Fortran sections transfer only
the selected elements.

Preserve physical source strides and scalar-subscript shape, normalize
character bounds and strides, and retain descriptor storage for deferred
`nowait` updates. In libomptarget, merge only consecutive innermost
contiguous dimensions, skip empty updates before presence checks and
transfers, and use 64-bit traversal counts.

Add Flang/MLIR and C/C++/Fortran offload regression coverage for both
transfer directions, multidimensional gaps, empty and `present` updates,
wide characters, and `nowait`.

Includes https://github.com/llvm/llvm-project/pull/235006.

Fixes:

    [3 lines not shown]
DeltaFile
+237-0mlir/test/Target/LLVMIR/omptarget-update-non-contiguous.mlir
+138-0offload/test/offloading/fortran/target-update-noncontiguous.f90
+119-13mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+120-7flang/test/Fir/OpenMP/bounds-generation-for-char-arrays.f90
+104-0offload/test/offloading/strided_update/strided_update_multidim_gap.c
+97-0mlir/test/Target/LLVMIR/omptarget-update-nowait-non-contiguous.mlir
+815-2017 files not shown
+1,457-5523 files

LLVM/project 7791462 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 merge-input-operands.ll freeze-repeated-lanes.ll

[SLP]Pack repeated freezes before the vector freeze

The lanes of a vector freeze are frozen independently, so a freeze
repeated in several lanes may get different values. Do not keep the
original lanes with duplicates for freeze nodes, pack the unique values
and reshuffle them.

Pull-request: https://github.com/llvm/llvm-project/pull/242377
DeltaFile
+8-8llvm/test/Transforms/SLPVectorizer/X86/freeze-repeated-lanes.ll
+6-6llvm/test/Transforms/SLPVectorizer/X86/merge-input-operands.ll
+5-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+19-163 files

LLVM/project 7daae79 — libc/cmake/caches baremetal_common.cmake

[libc] Enable -Werror in baremetal_common.cmake cache file (#241983)

After recent fixes, all the warnings are gone in baremetal builds.

Enable -Werror again so that we can catch warnings as they come.
DeltaFile
+1-2libc/cmake/caches/baremetal_common.cmake
+1-21 files