AMDGPU/GlobalISel: RegbankLegalize rules for G_BITCAST (#193025)
Move RegbankLegalize handling for G_BITCAST from AMDGPURegBankLegalize to
AMDGPURegBankLegalizeRules by implementing rules for all supported types.
[lldb] Remove trailing newlines from AppendErrorWithFormat calls (#192965)
This call adds a newline if there isn't one. Changing these will
eventually let us always add a newline, which is in line with the other
methods on CommandReturnObject.
This is a small part of calls found with:
* VSCode search for
`(\.AppendErrorWithFormat\(([\s\r\n]+)?"(?:(?:\\.|[^"\\])*))\\n"` and
replace with `$1"`.
* Asserting that the last character of the format string is not a
newline.
* Manual inspection.
[lldb] Add EXPORT to lldb-tblgen (#192610)
Fixes #192408
You can tell an llvm build to use existing tools using options like
LLVM_NATIVE_TOOL_DIR.
When you do this, the tools are usually still built in case they need to
be part of a later install. For example if you provide a clang-tblgen,
we still build another clang-tblgen as part of the build.
Which means if you install that build, it is a complete install, and if
you are doing a cross build, you get a cross built copy of clang-tblgen
that you can use on the target machine.
In #159812, lldb-tblgen was added to the list of tools to install, so
that installed builds could be used as a base for subsequent builds.
However we were missing the EXPORT flag for lldb-tblgen. As far as I can
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[LV] Add flag to always force a scalable VF when feasible. (#182467)
`-scalable-vectorization=always` means the LV will always favour using
scalable VFs when the cost is valid and scalable vectors are feasible.
This is mostly a hidden flag for experimentation purposes.
AMDGPU/GlobalISel: RegbankLegalize rules for undef and constants (#193024)
Move RegbankLegalize handling for G_IMPLICIT_DEF, G_CONSTANT and G_FCONSTANT
from AMDGPURegBankLegalize to AMDGPURegBankLegalizeRules by implementing
rules for all supported types.
[clang-tidy][readability-identifier-length] Add a line count threshold (#185319)
This PR implements the feature described in #185318
A new parameter named `LineCountThreshold` is added to the
`readability-identifier-length` check, which controls how many lines of
code must separate the the last use of a variable from its declaration
for the check to warn. For backwards-compatibility, the default value
for this parameter is set to 0.
Increasing the threshold to 1 allows for short names in one-liners (for
example: `std::transform(..., [](auto i){ return i*i; });`), and in the
general case with `LineCountThreshold = N` a variable is allowed to have
a shorter name than otherwise required if it is never used again after
`N` lines (including its declaration line).
This feature is implemented ~using a secondary `MatchFinder`~ by calling
the `utils::decl_ref_expr::allDeclRefExprs` helper function for each
variable with a short name. For performance reasons, the new piece of
code is short-circuited if `LineCountThreshold` is set to 0 (the default
value).
[ConstantMerge] don't merge constants with COMDAT (#192477)
After merging #190995 (now reverted) the CI failed because ConstantMerge
currently merges constants with differing COMDATs. This can result in a
function referencing globals with a different COMDAT than before the
merge, producing a linking error when that global gets discarded.
It is still possible to merge same comdats, or to merge a non-key comdat
constant into a non-comdat constant.
[libc] Implement shutdown on linux (#192933)
- added the relevant constant definitions
- enabled the entry point on x86_64, aarch64 and riscv
- testing by checking that the call causes an EOF on read (on the
appropriate end)
[Hexagon] Add missing MIRParser link dependency (#191010)
cd66d79be19b added parseMachineFunctionInfo to HexagonTargetMachine
which calls parseNamedRegisterReference from LLVMMIRParser, but did not
add the library dependency. This causes link failures for executables
like dsymutil and llvm-split when building with BUILD_SHARED_LIBS=OFF.
Add MIRParser to LINK_COMPONENTS.
(cherry picked from commit 95af7de3e9de2fadfbe7b2cbbfaecfdfbc7fd7af)
[Hexagon] Add AP register to liveins when used for frame index access (#188942)
This is a follow-up to commit 3ef59d80c5ce ("[Hexagon] Fix
use-before-def of AP register in prologue CSR spills").
When the AP (alignment pointer) register is used as a base register for
frame index elimination, add it to the basic block's livein set. This
ensures liveness information is accurate for the machine verifier.
The original commit fixed the use-before-def issue by moving PS_aligna
after CSR spills. However, when the prologepilog pass is run in
isolation (as in MIR tests) with expensive checks enabled, the verifier
reports an error because AP is used in blocks where it's not marked as
live-in.
In the full compilation pipeline, the Hexagon Packetizer adds AP as an
implicit operand to instruction bundles, which satisfies the verifier.
However, when running only the prologepilog pass (before packetization),
AP remains an explicit operand and must be in the livein set.
This fix adds AP to liveins when AP is used as the base register,
ensuring correct liveness tracking regardless of whether packetization
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[Hexagon][MIR] Serialize HexagonMachineFunctionInfo::StackAlignBaseReg to MIR (#190003)
This patch adds serialization of HexagonMachineFunctionInfo::StackAlignBaseReg
into MIR. This field stores the physical register used as the aligned-stack base pointer
when a function has both variable-sized stack objects and requires stack
alignment greater than the default.
This replaces the workaround from commit 2e10b6299591 ("[Hexagon] Add AP
register to liveins when used for frame index access") which manually added
AP to liveins. That approach was incorrect because it only updated one
block without updating predecessors, breaking liveness invariants.
(cherry picked from commit cd66d79be19b6db00500ba4508b3946ef1caec88)
[Hexagon] Fix use-before-def of AP register in prologue CSR spills (#188504)
PS_aligna initializes the AP register (eg:callee-saved R16) with an
aligned value derived from FP. It was being placed before the
CSR spills, causing the spill of R16 to save the AP value instead of the
caller's original R16, breaking the callee-saved register contract and
it must be defined before any AP-relative stack accesses. Fix by moving
PS_aligna to after all CSR spills in insertCSRSpillsInBlock().
Fixes #184531
(cherry picked from commit 3ef59d80c5ce51738a055d9e8eb98aa3c8effb2f)
[AMDGPU] Unmark wave reduce intrinsics for constant folding
The `add`, `sub`, and `xor` wave reduction intrinsics cannot
be constant folded, as `add` and `sub` need to be multipled
by the number of active lanes, and `xor` depends on the parity
of the number of active lanes.
[ELF] Fix heap-use-after-free with INPUT(relative-path) (#193146)
`ScriptParser::addFile` Case 4 (relative path resolved against the
script's parent directory) passes a `SmallString<0>` stack local by
StringRef, causing asan error after #191690.
Fix with ctx.saver similar to other cases.
[X86] Quote symbol names that collide with registers/keywords in Intel syntax (#186570)
When outputting Intel syntax assembly, symbol names that match register
names (e.g., `rsi`, `rax`) or keywords (`byte`, `ptr`, etc.) must be
quoted, otherwise the assembler parses them as registers/keywords
instead of symbol references.
Fix this by populating MCAsmInfo::ReservedIdentifiers with all X86
register names and Intel syntax keywords. isValidUnquotedName() checks
this set and forces quoting when a symbol name matches.
```
% cat rsi.c
void rsi(void); void foo(void) { rsi(); }
// old clang
% clang -c rsi.c -save-temps -masm=intel -fno-pic -o - | llvm-objdump -dr -
...
4: ff d6 callq *%rsi
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