LLVM/project b1c24eallvm/lib/Target/Mips MipsSEISelLowering.cpp, llvm/test/CodeGen/Mips/msa buildvector-undef-loop.ll

[Mips] Legalize vector UNDEF instead of expanding to zero BUILD_VECTOR (#211503)

Currently, MIPS MSA expands ISD::UNDEF into a BUILD_VECTOR of all zeros
during legalization. This creates an infinite loop in DAGCombiner when
the following occurs:
1.Mips lower BUILD_VECTOR expands non-splat vectors into
INSERT_VECTOR_ELT with creating undef node
2.Then legalization expands UNDEF back to BUILD_VECTOR zero 
3.Mips lower BUILD_VECTOR converts zero vector to BITCAST 
4.DAGCombiner optimizes BITCAST(zero) to UNDEF
5.Back to step 2, infinite loop

Fix #210229.
DeltaFile
+37-0llvm/test/CodeGen/Mips/msa/buildvector-undef-loop.ll
+1-0llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+38-02 files

LLVM/project fe2500cllvm/unittests/CodeGen/GlobalISel CMakeLists.txt, llvm/utils/gn/secondary/llvm/unittests/CodeGen/GlobalISel BUILD.gn

[GISel] Fix link error when dylib is enabled

This is to fix link error caused by e21cfc08414e.
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/unittests/CodeGen/GlobalISel/BUILD.gn
+1-0llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
+2-02 files

LLVM/project a97f512llvm/lib/Target/Mips MipsInstrInfo.cpp

[Mips] Fix getInstSizeInBytes for instructions with delay slots (#216665)

MIPS branch/jump instructions (B, BEQ, JALR64Pseudo, PseudoReturn64,
etc.) have a delay slot. The actual encoded size is 8 bytes (instr +
NOP). This fixes "out of range PC16 fixup" errors on large functions.

This issue was exposed in llvm 23 by commit pr #191460 which changed
MipsBranchExpansion to use MBB::iterator instead of instr_iterator,
making the MBB size calculation more accurate and revealing the
pre-existing bug.

Thanks for the pr #187703 `AllowOverEstimate` to help find instr which
actual size mismatch expected size .

Fix #112010.
DeltaFile
+4-0llvm/lib/Target/Mips/MipsInstrInfo.cpp
+4-01 files

LLVM/project 85651c2bolt/lib/Core BinaryEmitter.cpp, bolt/test/runtime/X86 lsda-absolute-udata4.test

[BOLT] Fix overflow issue when using absolute addressing in LSDA (#216654)

Currently, in the emitLSDA() flow, signed data is used when using
absolute addresses to update the LSDA for non PIE/DSO. But when the PC
is higher than 0x7fffffff(2GB), this will be sign-extended into an
invalid 64-bit address. Especially when the output binary is large,
silent errors can easily occur (we have met this problem in real
scenarios).

So this patch changes the signed data to unsigned data, thereby fixing
the incorrect address extension like this:
```
.gcc_except_table
  LSDA:
    LPStartEncoding: DW_EH_PE_omit   // No LPStart
    CallSiteEncoding: DW_EH_PE_sdata4 -> udata4   // Changed from sdata4 to udata4
    call-site table:
      call-site 1:
        start = ...

    [4 lines not shown]
DeltaFile
+18-0bolt/test/runtime/X86/lsda-absolute-udata4.test
+1-1bolt/lib/Core/BinaryEmitter.cpp
+19-12 files

LLVM/project 8d59b0bclang/include/clang/Basic BuiltinsAMDGPUDocs.td BuiltinsAMDGPU.td, clang/test/CodeGenCXX dynamic-cast-address-space.cpp

[NFC][AMDGPU] Introduce a new target feature for N=16 WMMAs
DeltaFile
+30-28llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+28-28clang/include/clang/Basic/BuiltinsAMDGPU.td
+20-0clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+10-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+7-1llvm/lib/Target/AMDGPU/AMDGPU.td
+2-2clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
+97-642 files not shown
+99-668 files

LLVM/project 2e81e9fclang/include/clang/Basic BuiltinsAMDGPUDocs.td BuiltinsAMDGPU.td, clang/test/CodeGenCXX dynamic-cast-address-space.cpp

[NFC][AMDGPU] Introduce a new target feature for N=16 WMMAs
DeltaFile
+30-28llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+28-28clang/include/clang/Basic/BuiltinsAMDGPU.td
+20-0clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+10-5llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+7-1llvm/lib/Target/AMDGPU/AMDGPU.td
+2-2clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
+97-642 files not shown
+99-668 files

LLVM/project 72988dellvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-amdgcn.ptr.s.buffer.load.ll regbankselect-mui-salu-float.mir

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+17-17llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
+36-36375 files not shown
+495-495381 files

LLVM/project 2b1f2eallvm/include/llvm/CodeGen MachineBasicBlock.h, llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+17-17llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+10-6llvm/include/llvm/CodeGen/MachineBasicBlock.h
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+43-39376 files not shown
+505-501382 files

LLVM/project 1c794fbllvm/test/Analysis/CostModel/RISCV arith-fp.ll int-bit-manip.ll, llvm/test/Transforms/VectorCombine/RISCV vpintrin-scalarization.ll

[IR] Autoupgrade trivial VP intrinsics to their non-VP counterparts (#212490)

As a first step towards removing trivial VP intrinsics, autoupgrade them
to their non-VP counterparts for backwards compatibility. Subsequent PRs
can then remove the intrinsics themselves.

Since trivial VP intrinsics only set lanes to poison, it's safe to
replace them with non predicated versions.

RFC: https://discourse.llvm.org/t/rfc-remove-trivial-vp-intrinsics/90972
DeltaFile
+0-1,763llvm/test/Analysis/CostModel/RISCV/cast.ll
+250-545llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll
+370-416llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
+308-308llvm/test/Analysis/CostModel/RISCV/fround.ll
+310-167llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
+0-470llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
+1,238-3,66946 files not shown
+2,127-4,67752 files

LLVM/project 1c66392llvm/utils/gn/secondary/llvm/lib/Analysis BUILD.gn

[gn build] Port e21cfc08414e (#217503)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn
+1-01 files

LLVM/project c68e793clang/lib/CIR/CodeGen CIRGenCXX.cpp CIRGenFunction.h, clang/lib/CIR/Dialect/Transforms LoweringPrepare.cpp

[CIR] Destroy a static local's extended temporary in its cir.local_init (#216210)

A temporary lifetime-extended by a function-local static had its
destructor hung off the cir.global, which the verifier rejects: a static
local is initialized and destroyed in-function under its guard, via
cir.local_init. Thread the region emitCXXSpecialVarDeclInit already
picks down to pushTemporaryCleanup, which registers into it in reverse
construction order.

Fixes SPEC2026: yaml-cpp's IsValidPlainScalar (736.ocio_r,
772/872.marian).
DeltaFile
+106-0clang/test/CIR/CodeGen/static-local-guard-abort.cpp
+84-0clang/test/CIR/CodeGen/local-static-temp-dtor.cpp
+44-8clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+16-15clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+8-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+5-0clang/lib/CIR/CodeGen/CIRGenCXX.cpp
+263-231 files not shown
+263-247 files

LLVM/project 002905dllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 split-node-reused-in-later-vector.ll copyable-extractelement-in-stores.ll

[SLP]Add extractelement as a main opcode for copyables

Model a bundle of extractelements from a common vector plus a foreign scalar
as a copyable node: matching lanes reuse the source vector and copyable lanes
are inserted into it. Limited to the identity extract order without a reuse
shuffle, other cases fall back to gather.

Fixes #192849

Reviewers: RKSimon, bababuck

Pull Request: https://github.com/llvm/llvm-project/pull/216503
DeltaFile
+94-21llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+22-15llvm/test/Transforms/SLPVectorizer/X86/same-values-sub-node-with-poisons.ll
+11-9llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-and-reordered-operand.ll
+2-16llvm/test/Transforms/SLPVectorizer/X86/copyable-extractelement-in-stores.ll
+9-9llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
+6-8llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-in-later-vector.ll
+144-786 files not shown
+162-10012 files

LLVM/project 9033be2llvm/include/llvm/Analysis LibcallLoweringInfo.h, llvm/include/llvm/CodeGen LibcallLoweringInfo.h

Revert "Analysis: Move LibcallLoweringInfo from CodeGen to Analysis (#210322)"

This reverts commit e21cfc08414e861e45ac9cd3383a30a39d26d869.
DeltaFile
+0-160llvm/include/llvm/Analysis/LibcallLoweringInfo.h
+114-13llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
+35-23llvm/lib/CodeGen/LibcallLoweringInfo.cpp
+0-49llvm/lib/Analysis/LibcallLoweringInfo.cpp
+5-5llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp
+5-5llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
+159-25515 files not shown
+173-27621 files

LLVM/project 4b88cd2llvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU packed-u64.ll fold-imm-pk64.mir

[AMDGPU] Optimize SGPR splat reg sequences for packed 64-bit instructions (#217182)

This work optimizes SGPR register sequences for packed 64-bit instructions by eliminating
redundant register copies when a scalar value is splatted across multiple lanes.

The optimization is implemented in SIFoldOperands::tryFoldSGPRSplatRegSequence, which:
1. Detects SGPR register sequences where all elements are identical
2. Verifies all uses are packed 64-bit instructions supporting single
SGPR read
3. Replaces redundant elements with undef to allow copy elimination

This reduces SGPR register pressure and eliminates unnecessary copies in
kernels using packed operations with splat scalars.
DeltaFile
+94-0llvm/test/CodeGen/AMDGPU/fold-sgpr-splat-pk64.mir
+82-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+8-14llvm/test/CodeGen/AMDGPU/packed-fp64.ll
+2-5llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
+1-1llvm/test/CodeGen/AMDGPU/fold-imm-pk64.mir
+0-1llvm/test/CodeGen/AMDGPU/packed-u64.ll
+187-216 files

LLVM/project f5e4be4llvm/include/llvm/CodeGen Passes.h, llvm/lib/CodeGen CFIInstrInserter.cpp

Add Legacy suffix go pass creation function.
DeltaFile
+1-1llvm/lib/Target/X86/X86TargetMachine.cpp
+1-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-1llvm/lib/CodeGen/CFIInstrInserter.cpp
+1-1llvm/include/llvm/CodeGen/Passes.h
+4-44 files

LLVM/project bc78463offload/languages/kernel CMakeLists.txt, offload/languages/kernel/include Stream.h LanguageUtils.h

add event cleanup
DeltaFile
+85-0offload/languages/kernel/src/Stream.cpp
+39-21offload/languages/kernel/include/LanguageUtils.h
+14-12offload/languages/kernel/src/LanguageRuntime.cpp
+19-0offload/languages/kernel/include/Stream.h
+6-2offload/languages/kernel/src/State.cpp
+1-0offload/languages/kernel/CMakeLists.txt
+164-356 files

LLVM/project 658978allvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 cmp-with-same-operands.ll

[SLP]Fix unscheduled-deps assertion for cmp with identical operands

Same-operands cmps (icmp sge %x, %x) took the reordered dependency
counting path, which undercounts the second use while scheduling
releases one dep per operand column. Treat them as non-commutative so
each use is checked against its own edge.

Fixes #217408

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/217495
DeltaFile
+20-0llvm/test/Transforms/SLPVectorizer/X86/cmp-with-same-operands.ll
+4-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+24-22 files

LLVM/project 7ef5ee3flang-rt/lib/runtime assign.cpp, flang-rt/unittests/Runtime Assign.cpp

Reject CHARACTER types in AssignSimple and add death tests

AssignSimple is only intended for trivial intrinsic types (integer, real,
complex, logical). Add a guard that crashes on CHARACTER type input,
matching the existing derived-type guard.

Add death tests covering all five crash paths in AssignSimple: rank
mismatch, element-bytes mismatch, derived type, character type, and
non-allocatable element count mismatch.

Co-Authored-By: Claude Opus 4 (1M context) <noreply at anthropic.com>
DeltaFile
+72-0flang-rt/unittests/Runtime/Assign.cpp
+3-0flang-rt/lib/runtime/assign.cpp
+75-02 files

LLVM/project 754283fllvm/include/llvm/CodeGen CFIInstrInserter.h, llvm/lib/CodeGen CFIInstrInserter.cpp

[NewPM] Port CFIInstrInserter to the new pass manager

Adds a newPM pass for CFIInstrInserter (cfi-instr-inserter).

- Extracts the pass's working state (MBBVector, CSRLocMap) and logic
  into a CFIInstrInserterImpl class with a run method, called by both
  the legacy pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass CFIInstrInserterPass, using
  RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
  calls skipFunction, so it always runs unconditionally and should not
  be skippable in the new PM either. run() unconditionally returns
  PreservedAnalyses::all(), matching the legacy pass's own
  AU.setPreservesAll() declaration -- the same shape CFIFixupPass (an
  already-ported sibling CFI pass) already uses.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder.
- Wires the pass into X86's and RISC-V's newPM pipelines, matching
  their existing legacy-PM gating conditions:
  - X86 replaces an existing TODO inside an already-correct

    [13 lines not shown]
DeltaFile
+48-30llvm/lib/CodeGen/CFIInstrInserter.cpp
+25-0llvm/include/llvm/CodeGen/CFIInstrInserter.h
+7-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-4llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir
+2-0llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+88-3513 files not shown
+108-3819 files

LLVM/project 9afd75fllvm/include/llvm/CodeGen FuncletLayout.h, llvm/lib/CodeGen FuncletLayout.cpp

[NewPM] Port FuncletLayout to the new pass manager (#217490)

Adds a newPM pass for FuncletLayout (funclet-layout).

- Extracts the pass's logic (which has no per-instance state) into a
shared runFuncletLayout free function, called by both the legacy pass
and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass FuncletLayoutPass, using
RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
calls skipFunction, so it always runs unconditionally and should not be
skippable in the new PM either.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder
-- FuncletLayoutPass was already unconditionally invoked from
CodeGenPassBuilder.h via a DUMMY_MACHINE_FUNCTION_PASS stub, so no
separate enablement change was needed.
- Fixes four pipeline-dump tests (X86, RISC-V x2, Lanai) whose CHECK
lines expected the stub's class-name fallback ("FuncletLayoutPass")
rather than the real pass's registered pipeline name ("funclet-layout").

    [4 lines not shown]
DeltaFile
+31-19llvm/lib/CodeGen/FuncletLayout.cpp
+28-0llvm/include/llvm/CodeGen/FuncletLayout.h
+4-4llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1-1llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+1-1llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+1-1llvm/test/CodeGen/Lanai/llc-pipeline-npm.ll
+66-266 files not shown
+72-2912 files

LLVM/project 8548eaellvm/include/llvm/CodeGen CFIInstrInserter.h, llvm/lib/CodeGen CFIInstrInserter.cpp

[NewPM] Port CFIInstrInserter to the new pass manager

Adds a newPM pass for CFIInstrInserter (cfi-instr-inserter).

- Extracts the pass's working state (MBBVector, CSRLocMap) and logic
  into a CFIInstrInserterImpl class with a run method, called by both
  the legacy pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass CFIInstrInserterPass, using
  RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
  calls skipFunction, so it always runs unconditionally and should not
  be skippable in the new PM either. run() unconditionally returns
  PreservedAnalyses::all(), matching the legacy pass's own
  AU.setPreservesAll() declaration -- the same shape CFIFixupPass (an
  already-ported sibling CFI pass) already uses.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder.
- Wires the pass into X86's and RISC-V's newPM pipelines, matching
  their existing legacy-PM gating conditions:
  - X86 replaces an existing TODO inside an already-correct

    [13 lines not shown]
DeltaFile
+48-30llvm/lib/CodeGen/CFIInstrInserter.cpp
+25-0llvm/include/llvm/CodeGen/CFIInstrInserter.h
+7-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-4llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir
+2-0llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+88-3513 files not shown
+108-3819 files

LLVM/project d207b59llvm/include/llvm/CodeGen FuncletLayout.h, llvm/lib/CodeGen FuncletLayout.cpp

[NewPM] Port FuncletLayout to the new pass manager

Adds a newPM pass for FuncletLayout (funclet-layout).

- Extracts the pass's logic (which has no per-instance state) into a
  shared runFuncletLayout free function, called by both the legacy
  pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass FuncletLayoutPass, using
  RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
  calls skipFunction, so it always runs unconditionally and should not
  be skippable in the new PM either.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder
  -- FuncletLayoutPass was already unconditionally invoked from
  CodeGenPassBuilder.h via a DUMMY_MACHINE_FUNCTION_PASS stub, so no
  separate enablement change was needed.
- Fixes four pipeline-dump tests (X86, RISC-V x2, Lanai) whose CHECK
  lines expected the stub's class-name fallback ("FuncletLayoutPass")
  rather than the real pass's registered pipeline name

    [6 lines not shown]
DeltaFile
+31-19llvm/lib/CodeGen/FuncletLayout.cpp
+28-0llvm/include/llvm/CodeGen/FuncletLayout.h
+4-4llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1-1llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+1-1llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+1-1llvm/test/CodeGen/Lanai/llc-pipeline-npm.ll
+66-266 files not shown
+72-2912 files

LLVM/project 4ef5f0bclang/lib/CodeGen CGBuiltin.cpp

s/CAT/CountAttributedTy/
DeltaFile
+5-4clang/lib/CodeGen/CGBuiltin.cpp
+5-41 files

LLVM/project ef645f2llvm/include/llvm InitializePasses.h, llvm/include/llvm/CodeGen FuncletLayout.h

[NewPM] Port FuncletLayout to the new pass manager

Adds a newPM pass for FuncletLayout (funclet-layout).

- Extracts the pass's logic (which has no per-instance state) into a
  shared runFuncletLayout free function, called by both the legacy
  pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix.
- Adds the new pass manager pass FuncletLayoutPass, using
  RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
  calls skipFunction, so it always runs unconditionally and should not
  be skippable in the new PM either.
- Updates MachinePassRegistry.def, PassBuilder, and CodeGenPassBuilder
  -- FuncletLayoutPass was already unconditionally invoked from
  CodeGenPassBuilder.h via a DUMMY_MACHINE_FUNCTION_PASS stub, so no
  separate enablement change was needed.
- Fixes four pipeline-dump tests (X86, RISC-V x2, Lanai) whose CHECK
  lines expected the stub's class-name fallback ("FuncletLayoutPass")
  rather than the real pass's registered pipeline name

    [6 lines not shown]
DeltaFile
+31-19llvm/lib/CodeGen/FuncletLayout.cpp
+28-0llvm/include/llvm/CodeGen/FuncletLayout.h
+4-4llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1-1llvm/lib/CodeGen/CodeGen.cpp
+1-1llvm/include/llvm/Passes/MachinePassRegistry.def
+1-1llvm/include/llvm/InitializePasses.h
+66-266 files not shown
+72-2912 files

LLVM/project d28bc6bllvm/test/CodeGen/AMDGPU llvm.is.fpclass.f16.ll freeze.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshr.ll fshl.ll

[AMDGPU] Remove more redundant ANDs (#216900)

Remove more redundant AND X, IMM instructions by allowing:

1.  s_and_b32 operations to be processed.
2. IMM can have values beside 0xffff.
3. The instruction defining X can be another AND instruction.
4. IMM can be either source operand.

---------

Signed-off-by: John Lu <John.Lu at amd.com>
DeltaFile
+2,569-0llvm/test/CodeGen/AMDGPU/redundant-and.mir
+0-2,191llvm/test/CodeGen/AMDGPU/high-bits-zeroed-16-bit-ops.mir
+209-275llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+191-257llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+67-145llvm/test/CodeGen/AMDGPU/freeze.ll
+56-121llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+3,092-2,98918 files not shown
+3,237-3,17924 files

LLVM/project e27e417llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-freeze.mir regbankselect-fexp2.mir

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
+22-22358 files not shown
+452-452364 files

LLVM/project 6a719c0llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-amdgcn.ptr.s.buffer.load.ll regbankselect-mui-salu-float.mir

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+17-17llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll
+36-36375 files not shown
+495-495381 files

LLVM/project 4af508dllvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-freeze.mir regbankselect-fexp2.mir

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
+22-22358 files not shown
+452-452364 files

LLVM/project 18f48d7llvm/test/CodeGen/AArch64/GlobalISel arm64-regbankselect.mir, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-whole-wave-functions.mir regbankselect-mad_64_32.mir

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
+2-2llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+20-20198 files not shown
+266-266204 files

LLVM/project 5b1a52dllvm/test/CodeGen/AArch64/GlobalISel arm64-regbankselect.mir, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-whole-wave-functions.mir regbankselect-mad_64_32.mir

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-whole-wave-functions.mir
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
+2-2llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+20-20198 files not shown
+266-266204 files