LLVM/project c347b26llvm/include/llvm/Analysis RuntimeLibcallInfo.h

Remove LLVM_ABI from members of RuntimeLibraryAnalysis (NFC) (#170850)

Fix Windows build error: attribute 'dllexport' cannot be applied to member of 'dllexport' class
DeltaFile
+2-3llvm/include/llvm/Analysis/RuntimeLibcallInfo.h
+2-31 files

LLVM/project e05899ellvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lsx issue170976.ll vmskcond.ll

[LoongArch] Custom lowering for 128-bit vector integer shifts
DeltaFile
+59-51llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+74-0llvm/test/CodeGen/LoongArch/lsx/issue170976.ll
+62-1llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+18-36llvm/test/CodeGen/LoongArch/lsx/ir-instruction/avg.ll
+28-16llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+13-0llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll
+254-1042 files not shown
+261-1068 files

LLVM/project bd1bd17compiler-rt/test/fuzzer reduce_inputs.test

[fuzzer][test-only] Bump runs for reduce_inputs.test unseeded run (#169641)

I have seen a failure whereby the fuzzer failed to reach the expected
input and thus failed the test.

This patch bumps the max executions to 10,000,000 in order to give the
fuzzer a better chance of reaching the expected input. Most runs
complete successfully, so I do not see this adding test time in the
general case; I believe it's a fair tradeoff for the unlucky seed to run
for longer if it reduces the noise from false positives. Note, this
updates a different `RUN:` to
https://github.com/llvm/llvm-project/pull/165402.

rdar://162122184
DeltaFile
+1-1compiler-rt/test/fuzzer/reduce_inputs.test
+1-11 files

LLVM/project ec1ea0allvm/docs ReleaseNotes.md, llvm/include/llvm-c Core.h

[llvm-c] Deprecate functions working on the global context (#163979)

One of the most common mistakes when working with the LLVM C API is to
mix functions that work on the global context and those that work on an
explicit context. This often results in seemingly nonsensical errors
because types from different contexts are mixed.

We have considered the APIs working on the global context to be obsolete
for a long time already, and do not add any new APIs using the global
context. However, the fact that these still exist (and have shorter
names) continues to cause issues.

This PR proposes to deprecate these APIs, with intent to remove them at
some point in the future.

RFC:
https://discourse.llvm.org/t/rfc-deprecate-c-api-functions-using-the-global-context/88639
DeltaFile
+117-33llvm/include/llvm-c/Core.h
+68-54llvm/unittests/ExecutionEngine/MCJIT/MCJITCAPITest.cpp
+39-33llvm/tools/llvm-c-test/debuginfo.c
+32-28llvm/lib/IR/Core.cpp
+35-0llvm/docs/ReleaseNotes.md
+21-13llvm/tools/llvm-c-test/metadata.c
+312-16119 files not shown
+434-23425 files

LLVM/project ec78750llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-vector-gep.ll

Revert "[AMDGPU] Enable i8 GEP promotion for vector allocas" (#171087)

Reverts llvm/llvm-project#166132

Broke libc on GPU tests.
https://lab.llvm.org/buildbot/#/builders/10/builds/18635
DeltaFile
+0-144llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
+3-18llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+3-1622 files

LLVM/project 95470b6clang/lib/AST/ByteCode InterpBuiltin.cpp

Replace interp__builtin_blend with interp__builtin_ia32_shuffle_gener… (#170217)

Fixes #169994

---------

Co-authored-by: Timm Baeder <tbaeder at redhat.com>
DeltaFile
+9-34clang/lib/AST/ByteCode/InterpBuiltin.cpp
+9-341 files

LLVM/project 75437ecllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-vector-gep.ll

Revert "[AMDGPU] Enable i8 GEP promotion for vector allocas (#166132)"

This reverts commit 6ec8c4351cfc1d0627d1633b02ea787bd29c77d8.
DeltaFile
+0-144llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
+3-18llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+3-1622 files

LLVM/project 7b65219llvm/include/llvm/IR Constants.h, llvm/lib/IR Constants.cpp

[IR] Add ImplicitTrunc argument to ConstantInt::get() (#170865)

Add an ImplicitTrunc argument to ConstantInt::get(), which allows
controlling whether implicit truncation of the value is permitted.
    
This argument currently defaults to true, but will be switched to false
in the future to guard against signed/unsigned confusion, similar to
what has already happened for APInt.
    
The argument gives an opt-out for cases where the truncation is
intended. The patch contains one illustrative example where this
happens.
DeltaFile
+7-6llvm/lib/IR/Constants.cpp
+9-4llvm/include/llvm/IR/Constants.h
+3-1llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+19-113 files

LLVM/project 3d24efdclang-tools-extra/test/clang-tidy .clang-tidy

[clang-tidy][NFC] Add empty '.clang-tidy' file in tests dir to silent warnings in IDE (#171029)

When working on tests, `clangd` with option `--clang-tidy` will report
warnings from
[root](https://github.com/llvm/llvm-project/blob/main/.clang-tidy)
clang-tidy config.
I believe these warnings serve no purpose in tests, so we better disable
them to silent warnings in IDE.
DeltaFile
+1-0clang-tools-extra/test/clang-tidy/.clang-tidy
+1-01 files

LLVM/project 9c60d70llvm/test/CodeGen/RISCV rvp-ext-rv32.ll

[RISCV] Re-generate rvp-ext-rv32.ll after #170399. NFC

Some instructions got renamed by #170399, but new tests cases were
added after that PR was created.
DeltaFile
+5-5llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+5-51 files

LLVM/project 46341d5llvm/lib/Target/RISCV RISCVInstrInfoP.td RISCVInstrInfoZb.td, llvm/test/CodeGen/RISCV rv32p.ll rv64p.ll

[RISCV] Update P extension to the 018 version of the spec. (#170399)

Rename the PPACK* instructions to PPAIR*. Rename PDIF* to PABD*. Remove
Zba/Zbb instructions from P.

https://www.jhauser.us/RISCV/ext-P/
DeltaFile
+2-668llvm/test/CodeGen/RISCV/rv32p.ll
+0-629llvm/test/CodeGen/RISCV/rv64p.ll
+50-77llvm/test/MC/RISCV/rv32p-valid.s
+34-64llvm/test/MC/RISCV/rv64p-valid.s
+41-48llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+17-26llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+144-1,51213 files not shown
+190-1,59619 files

LLVM/project 2e2eea7llvm/lib/Target/RISCV RISCVInstrInfoXSfmm.td

Revert "[RISCV] Use GPRNoX0 instead of AVL for Xsfmm pseudos. NFC (#170726)"

This reverts commit 446a3a19ed93449a9b50533f924f4bb658fd113e.
DeltaFile
+11-12llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
+11-121 files

LLVM/project 446a3a1llvm/lib/Target/RISCV RISCVInstrInfoXSfmm.td

[RISCV] Use GPRNoX0 instead of AVL for Xsfmm pseudos. NFC (#170726)

AVL allows immediates, but we don't have an equivalent of vsetivli for
XSfmm.
DeltaFile
+12-11llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
+12-111 files

LLVM/project b93a2e6clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Lowering/DirectToLLVM LowerToLLVM.cpp

[CIR] Make CIR-to-LLVM a one shot conversion

This had to fix memory and conversion bugs due to now immediate
conversion patterns and no longer present original MLIR.
DeltaFile
+85-42clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+1-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+86-432 files

LLVM/project 4b800d3llvm/lib/Target/RISCV RISCVCodeGenPrepare.cpp

[RISCV] Remove last use of @llvm.experimental.vp.splat in RISCVCodeGenPrepare. NFCI (#170543)

RISCVCodeGenPrepare is the last user of the vp.splat intrinsic, where it
uses it to expand a zero strided load into a scalar load and splat.
Originally this was to avoid vl toggles inside vectorized loops, but
nowadays this shouldn't be necessary because we have RISCVVLOptimizer.
To preserve the test cases where there's no store with VL, this replaces
it with a regular splat followed by a vp_merge to set the lanes past EVL
as poison. We need to set the EVL here because RISCVISelDAGToDAG will
try and recombine it back into a zero strided load, and we want to
preserve the original VL.
DeltaFile
+4-2llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+4-21 files

LLVM/project 8e39bcdlld/docs/ELF linker_script.rst

[lld][docs] Document two linker-script related options for lld ELF (#166313)

This is a follow up of the discussions in
https://github.com/llvm/llvm-project/pull/163497
DeltaFile
+19-0lld/docs/ELF/linker_script.rst
+19-01 files

LLVM/project c6f45f5llvm/lib/Target/PowerPC PPCInstrVSX.td PPCISelLowering.cpp, llvm/test/CodeGen/PowerPC scalar-min-max.ll fminimum-fmaximum.ll

PowerPC/VSX: Select FMINNUM and FMAXNUM (#135739)

In LangRef, we claim that FMINNUM and FMAXNUM should follow the minNum
and maxNum operators in IEEE754-2008.

PowerPC/VSX does have these instructions XSMINDP and XSMAXDP.

Now we use FMINNUM_IEEE and FMAXNUM_IEEE, since they are used by the
non-arch expand codes now.
In future, we may replace all FMINNUM_IEEE/FMAXNUM_IEEE with FMINNUM and
FMAXNUM.

---------

Co-authored-by: Your Name <you at example.com>
DeltaFile
+225-44llvm/test/CodeGen/PowerPC/scalar-min-max.ll
+34-99llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
+25-27llvm/lib/Target/PowerPC/PPCInstrVSX.td
+7-0llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+291-1704 files

LLVM/project 4125e73libcxx/include module.modulemap.in, libcxx/include/__memory shared_ptr.h

[libc++] Applied `[[nodiscard]]` to `hash<shared_ptr>`, `hash<unique_ptr>`, etc. (#170674)

`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.

- https://libcxx.llvm.org/CodingGuidelines.html


1. `hash<shared_ptr>`, `hash<unique_ptr>`, `std::integer_sequence<>`
etc.
2. Also implements fixes to
https://github.com/llvm/llvm-project/issues/169634 on the go (issues
discovered during current implementation)

---------

Co-authored-by: A. Jiang <de34 at live.cn>
Co-authored-by: Hristo Hristov <zingam at outlook.com>
DeltaFile
+21-0libcxx/test/libcxx/utilities/intseq/nodiscard.verify.cpp
+11-0libcxx/test/libcxx/utilities/smartptr/nodiscard.verify.cpp
+6-1libcxx/include/module.modulemap.in
+6-0libcxx/test/libcxx/diagnostics/functional.nodiscard.verify.cpp
+2-2libcxx/include/__memory/shared_ptr.h
+1-1libcxx/include/__utility/integer_sequence.h
+47-43 files not shown
+49-79 files

LLVM/project e442904llvm/lib/Target/AMDGPU AMDGPUAttributor.cpp, llvm/lib/Transforms/IPO AttributorAttributes.cpp

[AMDGPU] Apply alignment attr for make.buffer.rsrc (#166914)

Calculating alignment for `make.buffer.rsrc` intrinsic. The logic is the
alignment on use of return value of `make.buffer.rsrc` should be capped
by the base operand's alignment of `make.buffer.rsrc`.

For example:
```ll
define float @foo(ptr addrspace(1) align X %ptr) {
  %fat.ptr = call ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1) %ptr, i16 0, i32 C, i32 0)
  %y = load float, ptr addrspace(7) %fat.ptr, align Y
  ret float %y
}
```

We hopes that `Y = min(X, Y)`

---


    [8 lines not shown]
DeltaFile
+40-0llvm/test/CodeGen/AMDGPU/attr-amdgpu-align.ll
+20-1llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+5-1llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+2-2llvm/test/Transforms/Attributor/AMDGPU/tag-invariant-loads.ll
+67-44 files

LLVM/project 6ec8c43llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-vector-gep.ll

[AMDGPU] Enable i8 GEP promotion for vector allocas (#166132)

This patch adds support for the pattern:
```llvm
  %index = select i1 %idx_sel, i32 0, i32 4
  %elt = getelementptr inbounds i8, ptr addrspace(5) %alloca, i32 %index
```
by scaling the byte offset to an element index (index >>
log2(ElemSize)),
allowing the vector element to be updated with insertelement instead of
using
scratch memory.
DeltaFile
+144-0llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
+18-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+162-32 files

LLVM/project b0e9842compiler-rt/lib/builtins/cpu_model aarch64.c, compiler-rt/lib/builtins/cpu_model/aarch64 hwcap.inc

Revert "[FMV][AArch64] Add initial AT_HWCAP3 / AT_HWCAP4 support (#161595)" (#171071)

Crashing with older glibc.

This reverts commit edb43192516a55165cc4c158eb4fd4b2d81a8fce,
57b5ba00cb421b9be17bac10036763f42fbe9298 and
9715ccae1f98162f03ac0884a3dce5045b6b9a6e.
DeltaFile
+2-18compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc
+1-5compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc
+4-2compiler-rt/lib/builtins/cpu_model/aarch64.c
+0-4compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc
+0-4compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
+7-335 files

LLVM/project 2d80486llvm/lib/Target/RISCV RISCVInstrInfo.cpp

[RISCV] Use a switch in RISCVInstrInfo::verifyInstruction. NFC (#170961)

The immediate only operands handled with a range check and a switch
nested under the default case.
DeltaFile
+191-183llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+191-1831 files

LLVM/project 62355f1.github/workflows release-sources.yml

Update actions/checkout action to v6 (#171065)

This PR contains the following updates:

| Package | Type | Update | Change |
|---|---|---|---|
| [actions/checkout](https://redirect.github.com/actions/checkout) |
action | major | `v5.0.0` -> `v6.0.1` |
DeltaFile
+1-1.github/workflows/release-sources.yml
+1-11 files

LLVM/project 3562217utils/bazel/llvm-project-overlay/mlir BUILD.bazel

Fix bazel build for 5dbd049662001535a475cdb7d290dfb63a0515fc
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project fc92e4dllvm/lib/Transforms/InstCombine InstCombinePHI.cpp

[InstCombine] Fix bail-out in `PHIsEqualValue()` (#170650)

We encountered a such case: `PHIsEqualValue()` is called with a PHI node
`PN` whose incoming values are all PHI nodes, and `NonPhiInVal` is
nullptr. When the size of `ValueEqualPHIs` reaches 16, `NonPhiInVal` is
still nullptr, then we keep scanning PHI node operands, this time the
recursion won't bail out even if we have visited too many PHI nodes.

In our case, the recursion ends with ~1700 PHI nodes visited, causes
InstCombine time-consuming.
DeltaFile
+1-1llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
+1-11 files

LLVM/project 000e462utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Fix mlir build after #171024 (#171068)

DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project 25c4d5dllvm/test/CodeGen/AMDGPU inline-asm-use-bool.ll inline-asm.ll

move test
DeltaFile
+0-15llvm/test/CodeGen/AMDGPU/inline-asm-use-bool.ll
+12-0llvm/test/CodeGen/AMDGPU/inline-asm.ll
+12-152 files

LLVM/project 00c592ellvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU inline-asm-use-bool.ll

[AMDGPU] Fix a crash when a bool variable is used in inline asm
DeltaFile
+15-0llvm/test/CodeGen/AMDGPU/inline-asm-use-bool.ll
+5-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+20-02 files

LLVM/project 72b4a5dlibcxx/test/std/containers/container.adaptors/flat.map/flat.map.cons deduct.pass.cpp deduct_pmr.pass.cpp, libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.cons deduct.pass.cpp sorted_container.pass.cpp

[libcxx] Removal of narrowing conversions in `flat_[multi]{set, map}` tests for compatibility with MSVC (#170909)

Impacts files in `test/std/containers/container.adaptors/flat.xxx`. No
meaning is changed; only appropriate types are spelled out to prevent
compiler warnings.

- Replace `char`s and `short`s used in tests of `flat_[multi]{set, map}`
with `long`s to prevent warnings about narrowing conversions when
running tests. Allow increased test coverage for MSVC STL.
- Make test code robust against evil overloads of operator comma .(2
files)
- Add `[[maybe_unused]]` to some local `typedef`s that are sometimes
unused due to usage of `LIBCPP_STATIC_ASSERT`.

For discussion and suggested changes, see the LLVM Discord
https://discord.com/channels/636084430946959380/636732894974312448/1445901676400742533
DeltaFile
+27-27libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.cons/deduct.pass.cpp
+27-27libcxx/test/std/containers/container.adaptors/flat.map/flat.map.cons/deduct.pass.cpp
+14-14libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.cons/sorted_container.pass.cpp
+14-14libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.cons/deduct_pmr.pass.cpp
+14-14libcxx/test/std/containers/container.adaptors/flat.map/flat.map.cons/deduct_pmr.pass.cpp
+13-13libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.cons/range.pass.cpp
+109-10928 files not shown
+277-27534 files

LLVM/project e49da4fllvm/test/TableGen RegClassByHwModeCompressPat.td RegClassByHwModeErrors.td, llvm/test/TableGen/Common RegClassByHwModeCommon.td

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+315-0llvm/test/TableGen/RegClassByHwModeCompressPat.td
+88-0llvm/test/TableGen/RegClassByHwModeErrors.td
+7-57llvm/test/TableGen/RegClassByHwMode.td
+44-0llvm/test/TableGen/Common/RegClassByHwModeCommon.td
+18-15llvm/utils/TableGen/CompressInstEmitter.cpp
+12-9llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
+484-814 files not shown
+500-8710 files