LLVM/project bf3622ellvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch musttail-tailcc.ll

[LoongArch] Support `tail` calling convention
DeltaFile
+163-0llvm/test/CodeGen/LoongArch/musttail-tailcc.ll
+1-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+164-02 files

LLVM/project 3a8b5e3lldb/tools/lldb-dap OutputRedirector.cpp OutputRedirector.h

[lldb-dap] Use MainLoop instead of a background thread in OutputRedirector. (#199970)

Replace the background thread in OutputRedirector with LLDB's MainLoop
event loop. This reduces the number of threads created and ensures file
descriptors are properly closed when no longer needed.

Since debugger's output is not I/O intensive, there is no risk of
hitting the pipe buffer limit with this approach.
DeltaFile
+39-34lldb/tools/lldb-dap/OutputRedirector.cpp
+23-12lldb/tools/lldb-dap/OutputRedirector.h
+14-11lldb/tools/lldb-dap/DAP.cpp
+76-573 files

LLVM/project d627924mlir/lib/Analysis SliceAnalysis.cpp, mlir/test/Dialect/Affine slicing-utils.mlir

[mlir][SliceAnalysis] Fix visited set to avoid infinite recursion  (#200008)

Fixes #139694, which introduced use-def cycle detection during slice
analysis, but some cycles were still not detected, potentially leading
to infinite recursion.

This PR fixes the handling of the visited set, which tracks the current
DFS path during recursion. Previously, the set could fail to detect
double cycles because entries were erased even when no recursive call
was made. The insert/erase operations are now only performed when
recursion actually occurs, ensuring that cycle detection correctly
reflects the active DFS path.
DeltaFile
+23-0mlir/test/Dialect/Affine/slicing-utils.mlir
+12-8mlir/lib/Analysis/SliceAnalysis.cpp
+35-82 files

LLVM/project f8bf8afclang/lib/Headers wasm_simd128.h, cross-project-tests/intrinsic-header-tests wasm_simd128.c

[WebAssembly] Add f16x8.demote_f32x4_zero to wasm_simd128.h. (#199795)

Missing header intrinsic.
DeltaFile
+8-0clang/lib/Headers/wasm_simd128.h
+6-0cross-project-tests/intrinsic-header-tests/wasm_simd128.c
+14-02 files

LLVM/project 5dc633bllvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp, llvm/test/CodeGen/AArch64 fabs.ll bf16-instructions.ll

[AArch64][GlobalISel] Add BF16 fabs and fneg (#198655)

These should be very simple as they are just legal or expanded based on
whether fullfp16 is available, as the FP16 FNEG and FABS instructions can
be used equally for BF16.
DeltaFile
+42-17llvm/test/CodeGen/AArch64/fabs.ll
+35-12llvm/test/CodeGen/AArch64/bf16-instructions.ll
+21-8llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
+17-8llvm/test/CodeGen/AArch64/fneg.ll
+12-9llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+3-2llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+130-566 files

LLVM/project f16c0ec.github/workflows issue-release-workflow.yml

workflows/issue-release-workflow: Remove template expansion of login names (#199772)

https://github.com/llvm/llvm-project/security/code-scanning/1609
https://github.com/llvm/llvm-project/security/code-scanning/1610
DeltaFile
+2-1.github/workflows/issue-release-workflow.yml
+2-11 files

LLVM/project a8e1f5cflang-rt/cmake/modules AddFlangRTOffload.cmake, flang-rt/include/flang-rt/runtime io-stmt.h

[flang-rt][cuda] Use a thinner I/O in CUDA build (#199769)

Reduce the footprint of IO in the CUDA build. This helps including IO
when using non relocatable device code mode.
DeltaFile
+194-0flang-rt/lib/runtime/io-stmt-minimal.cpp
+36-0flang-rt/lib/runtime/io-api-common.h
+9-0flang-rt/include/flang-rt/runtime/io-stmt.h
+4-1flang-rt/lib/runtime/CMakeLists.txt
+3-0flang-rt/cmake/modules/AddFlangRTOffload.cmake
+246-15 files

LLVM/project 5b38edd.github/workflows pr-code-lint.yml

workflows/pr-code-lint: Pin container image (#199767)

https://github.com/llvm/llvm-project/security/code-scanning/1678
DeltaFile
+1-1.github/workflows/pr-code-lint.yml
+1-11 files

LLVM/project ed918c1llvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/Transforms/AtomicExpand/RISCV atomicrmw-widen-volatile.ll

[AtomicExpand] Preserve volatile in widenPartwordAtomicRMW. (#199722)

widenPartwordAtomicRMW widens a sub-word atomicrmw to the target's
minimum cmpxchg size by calling CreateAtomicRMW, which has no
IsVolatile parameter, and didn't copy isVolatile() from the original.
Every other expansion path in this file already does.  Affects targets
whose MinCmpXchgSizeInBits exceeds the value width (RISC-V without
Zabha, LoongArch base, SPARC, AMDGPU, etc.).

This bug was found by a large run of Opus 4.7 looking for bugs in LLVM.
DeltaFile
+41-0llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-widen-volatile.ll
+1-0llvm/lib/CodeGen/AtomicExpandPass.cpp
+42-02 files

LLVM/project 8275507llvm/utils profcheck-xfail.txt

[ProfCheck] Fix #199174 (#200013)

The patch added another large fp conversion test, which we currently are
missing some profile annotations for, so add it to the xfail list for
now.
DeltaFile
+1-0llvm/utils/profcheck-xfail.txt
+1-01 files

LLVM/project f6af6ce.github/workflows libclang-abi-tests.yml

workflows/libclang-abi-tests: Remove template expansion (#199792)

https://github.com/llvm/llvm-project/security/code-scanning/1627
https://github.com/llvm/llvm-project/security/code-scanning/1628
https://github.com/llvm/llvm-project/security/code-scanning/1629
https://github.com/llvm/llvm-project/security/code-scanning/1630
https://github.com/llvm/llvm-project/security/code-scanning/1631
https://github.com/llvm/llvm-project/security/code-scanning/1632
https://github.com/llvm/llvm-project/security/code-scanning/1633
https://github.com/llvm/llvm-project/security/code-scanning/1634
https://github.com/llvm/llvm-project/security/code-scanning/1635
https://github.com/llvm/llvm-project/security/code-scanning/1636
https://github.com/llvm/llvm-project/security/code-scanning/1637
https://github.com/llvm/llvm-project/security/code-scanning/1638
DeltaFile
+19-9.github/workflows/libclang-abi-tests.yml
+19-91 files

LLVM/project 9998aedllvm/test/CodeGen/RISCV/rvy rvy-invalid-operands.mir

add MIR test for RISCVInstrInfo::verifyInstruction

Created using spr 1.3.8-beta.1
DeltaFile
+34-0llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
+34-01 files

LLVM/project 7a1a542.github/workflows release-documentation.yml

workflows/release-documentation: Validate input and remove template expansion (#199760)

https://github.com/llvm/llvm-project/security/code-scanning/1715
https://github.com/llvm/llvm-project/security/code-scanning/1716
https://github.com/llvm/llvm-project/security/code-scanning/1717
https://github.com/llvm/llvm-project/security/code-scanning/1718
https://github.com/llvm/llvm-project/security/code-scanning/1719
https://github.com/llvm/llvm-project/security/code-scanning/1720
https://github.com/llvm/llvm-project/security/code-scanning/1721
https://github.com/llvm/llvm-project/security/code-scanning/1722
DeltaFile
+15-8.github/workflows/release-documentation.yml
+15-81 files

LLVM/project 077210allvm/utils/gn/secondary/compiler-rt/lib/builtins BUILD.gn, llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port commits (#200011)

0d6aac78ad96
7938535a54b5
ed11d7a52a50
DeltaFile
+1-1llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+2-0llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
+4-13 files

LLVM/project a1cba5aflang/include/flang/Semantics openmp-utils.h, flang/lib/Semantics check-omp-structure.cpp openmp-utils.cpp

[flang][OpenMP] Optionally get final symbol in Get(Argument|Object)Sy… (#196816)

…mbol

Originally these functions returned the ultimate symbol for the one
obtained from the argument or object. However, this may be somewhat
unintuitive/unexpected, so instead return the original symbol, and add a
flag to optionally return the ultimate one.
DeltaFile
+16-14flang/lib/Semantics/check-omp-structure.cpp
+17-7flang/lib/Semantics/openmp-utils.cpp
+4-2flang/include/flang/Semantics/openmp-utils.h
+1-1flang/lib/Semantics/check-omp-loop.cpp
+38-244 files

LLVM/project 00b1353flang/lib/Lower/OpenMP OpenMP.cpp, flang/lib/Lower/Support PrivateReductionUtils.cpp

[Flang][OpenMP] Support declare reduction without initializer (#196211)

For declare reduction without an explicit initializer clause, the init
callback now handles initialization inline rather than relying on the
_FortranAInitialize runtime call, which is available on the device
runtime but has known issues on GPU targets.

The initialization logic first checks whether an initializer clause is
present. If one is provided, it is used directly. Otherwise, for derived
types, the code checks whether the type has default component
initialization. If it does, each component is initialized inline:
components with explicit default values use those values, components
that are themselves derived types with defaults are recursively
initialized, and components without any default are zero-initialized.

Derived types with allocatable components that require runtime
initialization are guarded by a TODO.

Assisted by: Claude Opus 4.6
DeltaFile
+97-0flang/test/Lower/OpenMP/declare-reduction-no-initializer-derived.f90
+83-0flang/test/Lower/OpenMP/declare-reduction-no-initializer-intrinsic.f90
+67-15flang/lib/Lower/OpenMP/OpenMP.cpp
+73-0flang/test/Lower/OpenMP/declare-reduction-target-intrinsic.f90
+56-0flang/test/Lower/OpenMP/declare-reduction-no-initializer-target-derived.f90
+48-0flang/lib/Lower/Support/PrivateReductionUtils.cpp
+424-157 files not shown
+502-2213 files

LLVM/project 2677f6ellvm/lib/Target/RISCV RISCVInstrInfoY.td RISCVInstrInfo.cpp, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

clean up tablegen operands

Created using spr 1.3.8-beta.1
DeltaFile
+7-8llvm/lib/Target/RISCV/RISCVInstrInfoY.td
+6-0llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+3-3llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+3-2llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+2-2llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+21-155 files

LLVM/project d98fd41llvm/lib/CodeGen ExpandIRInsts.cpp, llvm/test/Transforms/ExpandIRInsts/X86 expand-large-fp-convert-fpto-sat-vector.ll

[ExpandIRInsts] Support llvm.fpto{u,s}i.sat (#199174)

Previously, running ExpandIRInsts on a program which needs to expand a
vector fptoui.sat would hit llvm_unreachable, because the `scalarize`
function didn't handle this intrinsic.

This bug was found by a large run of Opus 4.7 looking for bugs in LLVM.
DeltaFile
+320-0llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fpto-sat-vector.ll
+6-1llvm/lib/CodeGen/ExpandIRInsts.cpp
+326-12 files

LLVM/project 753008dflang/lib/Lower/OpenMP OpenMP.cpp, flang/test/Lower/OpenMP target-inreduction.f90

[flang][OpenMP] Lower target in_reduction for host fallback

Teach Flang lowering and MLIR OpenMP translation to carry
in_reduction through omp.target for the host-fallback path.

The translation looks up task reduction-private storage with
__kmpc_task_reduction_get_th_data and binds the target region's
in_reduction block argument to that private pointer, so uses inside the
region do not keep referring to the original variable.

The patch also preserves in_reduction operands in the TargetOp builder
path and ensures target in_reduction list items are mapped into the
target region when needed.

The device/offload-entry path remains diagnosed as not yet implemented.
DeltaFile
+90-1mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+83-3mlir/test/Target/LLVMIR/openmp-todo.mlir
+64-6flang/lib/Lower/OpenMP/OpenMP.cpp
+60-0mlir/test/Dialect/OpenMP/invalid.mlir
+50-0mlir/test/Target/LLVMIR/openmp-target-in-reduction.mlir
+28-0flang/test/Lower/OpenMP/target-inreduction.f90
+375-103 files not shown
+412-309 files

LLVM/project 981acb7llvm/lib/Target/RISCV RISCVInstrInfoY.td

indentation

Created using spr 1.3.8-beta.1
DeltaFile
+3-3llvm/lib/Target/RISCV/RISCVInstrInfoY.td
+3-31 files

LLVM/project 6d46223llvm/lib/Target/RISCV RISCVInstrInfoY.td, llvm/test/MC/RISCV/rvy rvy-basic.s

fix copy-paste error

Created using spr 1.3.8-beta.1
DeltaFile
+7-0llvm/test/MC/RISCV/rvy/rvy-basic.s
+1-1llvm/lib/Target/RISCV/RISCVInstrInfoY.td
+8-12 files

LLVM/project 7b993d2llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine ldexp.ll

[InstCombine] Use sadd.sat for chained ldexp fold (#199274)

ldexp(ldexp(x, a), b) -> ldexp(x, a + b) didn't consider the fact that
`a + b` may overflow!  Use a saturating add instead.

This bug was found by a large run of Opus 4.7 looking for bugs in LLVM.
DeltaFile
+67-11llvm/test/Transforms/InstCombine/ldexp.ll
+42-18llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+109-292 files

LLVM/project 860e4b8llvm/lib/Target/X86 X86AvoidStoreForwardingBlocks.cpp, llvm/test/CodeGen/X86 avoid-sfb.ll

[X86][AvoidStoreForwardingBlocks] Skip volatile/atomic accesses. (#199698)

The pass splits an XMM/YMM load+store pair into smaller copies when a
preceding narrower store would block store-to-load forwarding into the
load, but it didn't check the MachineMemOperand's isVolatile/isAtomic
bits.

This bug was found by a large run of Opus 4.7 looking for bugs in LLVM.
DeltaFile
+163-0llvm/test/CodeGen/X86/avoid-sfb.ll
+7-1llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
+170-12 files

LLVM/project e1e52c9llvm/lib/Support Win64EH.cpp, llvm/test/tools/llvm-objdump/COFF win64-unwindv3-multi-epilog.yaml

[win][x64] Updated `llvm-objdump` and `llvm-readobj` to be able to dump Windows x64 Unwind v3 information. (#199120)

Public docs:
<https://learn.microsoft.com/en-us/cpp/build/x64-unwind-information-v3?view=msvc-170>

The change adds Windows x64 unwind v3 info decoding and printing support
in LLVM, including new data structures, enums, and decoding functions to
handle the different WOD opcodes and epilog descriptors. It also updates
the dumping utilities (llvm-readobj and llvm-objdump) to correctly
interpret v3 unwind info.
DeltaFile
+364-0llvm/lib/Support/Win64EH.cpp
+287-5llvm/tools/llvm-objdump/COFFDump.cpp
+233-3llvm/tools/llvm-readobj/Win64EHDumper.cpp
+191-0llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-v3-multi-epilog.yaml
+173-0llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-v3-all-wods.yaml
+164-0llvm/test/tools/llvm-objdump/COFF/win64-unwindv3-multi-epilog.yaml
+1,412-838 files not shown
+5,528-944 files

LLVM/project 2713d94llvm/docs SandboxIR.md, llvm/include/llvm/SandboxIR Tracker.h Context.h

Reapply "[SandboxIR][Tracker] Implement accept(/*AcceptAll*/) and revert(/*RevertAll*/)" (#199776) (#199805)

This reverts commit a7aceff0b1e552cbc2306e575e9ac649853fda8e.
DeltaFile
+55-0llvm/unittests/SandboxIR/TrackerTest.cpp
+23-8llvm/lib/SandboxIR/Tracker.cpp
+18-6llvm/include/llvm/SandboxIR/Tracker.h
+2-2llvm/include/llvm/SandboxIR/Context.h
+2-1llvm/docs/SandboxIR.md
+100-175 files

LLVM/project db9b595llvm/include/llvm/DebugInfo/CodeView CodeViewRegisters.def, llvm/lib/Target/X86/MCTargetDesc X86MCTargetDesc.cpp

[X86][APX] Add CodeView register IDs and mapping for APX EGPR (#199586)

Resolves #187924

Refer to
https://devblogs.microsoft.com/cppblog/msvc-version-1451-available/
DeltaFile
+64-0llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
+64-0llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+37-0llvm/test/DebugInfo/COFF/apx-egpr.ll
+165-03 files

LLVM/project ea3cb0fllvm/lib/Target/AMDGPU SIFrameLowering.cpp

Fix for noassert buildbot break in #183153 (#199781)

Change-Id: I285adf09ac2df239d0ab05459f7388b6970247ad
DeltaFile
+1-2llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+1-21 files

LLVM/project 3768e13llvm/test/CodeGen/X86 vector-shuffle-combining-avx512vbmi2.ll

[X86] Add test coverage for #145276 (#200004)
DeltaFile
+16-0llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi2.ll
+16-01 files

LLVM/project 95f08b1llvm/lib/Target/RISCV RISCVInstrInfoP.td

[RISCV][P-ext] Make the direction argument for RVPPairShift* classes required. NFC (#199799)

It's part of the encoding. I don't think we should have a preference for
one of the bit values being the default.
DeltaFile
+54-52llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+54-521 files

LLVM/project 38555dbllvm/lib/Target/RISCV RISCVISelDAGToDAG.cpp RISCVInstrInfoP.td

[RISCV][P-ext] Replace some custom isel code with tablegen patterns. NFC (#199881)
DeltaFile
+0-51llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+17-1llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+17-522 files