[LLVM][CodeGen] Rename `gc-empty-basic-blocks` to `enable-gc-empty-basic-blocks` (#176018)
Rename the `gc-empty-basic-blocks` command line option to
`enable-gc-empty-basic-blocks` in preparation of adding calls to
initializing the pass in `initializeCodeGen` and also make the flag more
consistent with other existing flags to enable or disable passes.
Keep `gc-empty-basic-blocks` as an alias to allow all users to migrate
to the new option.
[Support] Suppress old MSVC warning for [[msvc::no_unique_address]] (#176130)
MSVC versions prior to 19.43 (Visual Studio 2022 version 17.13) emit a
warning when using the [[msvc::no_unique_address]] attribute prior to
C++20.
This is now considered a bug and fixed in later releases of MSVC.
Suppress the warning for older MSVC versions by disabling the warning
around the attribute usage. This allows for warning-free builds when
targeting older MSVC versions.
More details and discussion about the warning can be found here:
https://developercommunity.visualstudio.com/t/msvc::no_unique_address-Should-Not-W/10118435
Revert "[NFC][MI] Tidy Up RegState enum use (1/2)" (#176190)
Reverts llvm/llvm-project#176091
Reverting because some compilers were erroring on the call to
`Reg.isReg()` (which is not `constexpr`) in a `constexpr` function.
[NFC][MI] Tidy Up RegState enum use (1/2) (#176091)
This Change is to prepare to make RegState into an enum class. It:
- Updates documentation to match the order in the code.
- Brings the `get<>RegState` functions together and makes them
`constexpr`.
- Adopts the `get<>RegState` where RegStates were being chosen with
ternary operators in backend code.
- Introduces `hasRegState` to make querying RegState easier once it is
an enum class.
- Adopts `hasRegState` where equivalent was done with bitwise
arithmetic.
- Introduces `RegState::NoFlags`, which will be used for the lack of
flags.
- Documents that `0x1` is a reserved flag value used to detect if
someone is passing `true` instead of flags (due to implicit bool to
unsigned conversions).
- Updates two calls to `MachineInstrBuilder::addReg` which were passing
`false` to the flags operand, to no longer pass a value.
- Documents that `getRegState` seems to have forgotten a call to
`getEarlyClobberRegState`.
[LifetimeSafety] Test lifetime safety on stmt-local analysis test suite (#175906)
Add CFG-based lifetime analysis tests for dangling pointer detection
alongside the existing AST-based analysis.
This change helps validate that the new CFG-based lifetime analysis
correctly detects the same dangling pointer issues as the existing
AST-based analysis. It also documents current limitations of the
CFG-based approach with FIXME comments, providing a roadmap for future
improvements. The test ensures that both analysis methods can work
side-by-side, with the CFG-based analysis eventually intended to replace
the AST-based approach.
Reapply "AMDGPU: Do not infer implicit inputs for !nocallback intrinsics" (#176081)
This reverts #174224 and re-applies #131759 .
Note: If #117544 is reverted, this should also be reverted.
[SLPVectorizer] Check std::optional coming out of getPointersDiff (#175784)
Fixes https://github.com/llvm/llvm-project/issues/175768
There are other unchecked uses std::optional in this pass but I couldn't
figure out a test that triggers them
[DebugInfo] Drop stale entry value-limitation for call site values (#172340)
Entry value operations could previously not be combined with other
operations in debug expressions, meaning that we had to skip emitting
call site values in such cases. This DIExpression limitation was removed
in 57a371d7010802804343d17b85ac5e0d28d0f309, so we should be free to
emit call site values for such cases now, for example:
extern void call(int, int);
void entry_value (int param) {
call(param + 222, param - 444);
}
This change exposed a call site parameter entry order issue in the
dbgcall-site-expr-entry-value.mir test case. That ordering issue is
tracked in #43998, and I don't think there is anything inherent in this
patch that caused that.
[AMDGPU] Rematerialize VGPR candidates when SGPR spills to VGPR over the VGPR limit
Before, when selecting candidates to rematerialize, we would only
consider SGPR candidates when there was an excess of SGPR registers.
Failing to eliminate the excess would result in spills to VGPRs.
This is normally not an issue, unless spilling to VGPRs results in
excess VGPRs.
This patch does 2 things:
* It relaxes the GCNRPTarget success criteria: now we accept regions
where we spill SGPRs to VGPRs, as long as this does not end up in
excess VGPRs.
* It changes isSaveBeneficial to consider the excess VGPRs (which
includes the SGPRs that would be spilled to VGPR).
With these changes, the compiler rematerializes VGPRs when the excess
SGPRs would result in VGPR excess.
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[openmp] Add support for Arm64X to libomp
This patch allows building libomp.dll and libomp.lib as Arm64X binaries
containing both arm64 and arm64ec code and useable from applications
compiled for both architectures.
InstCombine: Handle multiple use fneg(fabs(x)) in SimplifyDemandedFPClass
This ends up being smarter than the single use case, so these should
be merged at some point.
[SPIRV] Improve vector legalization and type deduction (#175067)
This patch adds support for scalarizing vector loads in the legalizer
and
implements legalization for the spv_const_composite intrinsic. It also
refactors stack temporary creation for vector operations to ensure
correct
SPIR-V types are assigned. Additionally, type deduction in the
PostLegalizer is improved to handle GEP and Load instructions.
Fixes https://github.com/llvm/llvm-project/issues/170534
