AMDGPU: Correct value and name for ID_RTN_SAVE_WAVE_HAS_TDM
The old name and ID value do not match the documentation. The
documentation calls this RTN_SAVE_WAVE_HAS_TDM with the value
0x98.
[VectorCombine] Skip dead shufflevector in GetIndexRangeInShuffles to fix crash. (#179217)
Update GetIndexRangeInShuffles to skip unused shuffles. This matches the
behavior in the loop below and without it, we end up with an index
mis-match, causing a crash for the added test case.
PR: https://github.com/llvm/llvm-project/pull/179217
[lldb-dap] Remove end line and column from disassemble response (#180037)
The end line entry calculated from the instruction's end address is
unreliable and could produce incorrect source ranges. especially if the
instruction spans multiple lines.
We can end in situations where the current end line is the next start
line and the source line is show to the client twice. confusing users
what maps to what.
| With EndLine |
| :------------: |
| <img width="892" height="486" alt="Screenshot 2026-02-05 at 21 37 08"
src="https://github.com/user-attachments/assets/f2fef592-5754-4168-bf93-2baba4742c5d"
/> |
| Without Endline |
| :---------------: |
| <img width="892" height="486" alt="Screenshot 2026-02-05 at 21 59 29"
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sys/conf/options: remove improper full stops
Only keep them when used in a sentence.
Reviewed by: vexeduxr
Signed-off-by: Quentin Thébault <quentin.thebault at defenso.fr>
Sponsored by: Defenso
Closes: https://github.com/freebsd/freebsd-src/pull/2004
NAS-139647 / 26.0.0-BETA.1 / optimize interface/sync.py (#18157)
This makes a single call to "get_links" before we configure any
interfaces to reduce the number of netlink calls we make when
configuring these interfaces. The truenas_pynetif functions were written
with this in mind and so this just changes it so that we take advantage
of it. Instead of calling "get_links" (which enumerates all interfaces)
for every interface, it only calls it once and the cache is updated with
each interface after it has been configured.
While here, fix the socket type annotation.
[ExpandIRInsts] Freeze input in itofp expansion (#180157)
We are introducing branches on the value, and branch on undef/poison is
UB, so the value needs to be frozen.
[LV] Support conditional scalar assignments of masked operations (#178862)
This patch extends the support added in #158088 to loops where the
assignment is non-speculatable (e.g. a conditional load or divide).
For example, the following loop can now be vectorized:
```
int simple_csa_int_load(
int* a, int* b, int default_val, int N, int threshold)
{
int result = default_val;
for (int i = 0; i < N; ++i)
if (a[i] > threshold)
result = b[i];
return result;
}
```
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AMDGPU: Add llvm.amdgcn.s.wait.event intrinsic
Exactly match the s_wait_event instruction. For some reason we already
had this instruction used through llvm.amdgcn.s.wait.event.export.ready,
but that hardcodes a specific value. This should really be a bitmask that
can combine multiple wait types.
gfx11 -> gfx12 broke compatabilty in a weird way, by inverting the
interpretation of the bit but also shifting the used bit by 1. Simplify
the selection of the old intrinsic by just using the magic number 2, which
should satisfy both cases.
InstCombine: Only propagate callsite attributes in sqrt->sqrtf (#180160)
This was propagating the callee's attributes instead of just the
callsite. It's illegal to set denormal_fpenv on a callsite. This
was also losing callsite attributes which may have been more useful;
there's no point in setting the callee's attributes on the callsite.
[AArch64][GloballISel] Put result of fp16 -> s16 convert intrinsic on fpr
Previously, RegBankSelect would place the result of an fp16 -> s16 conversion intrinsic on a gpr. This would cause Instruction Selection to fail, as there are no 16-bit gprs.
Floating point convert intrinsics affected:
fcvtnu / fcvtns
fcvtau / fcvtas
fcvtmu / fcvtms
fcvtpu / fcvtps
ccid: updated to 1.7.1
1.7.1 - 4 February 2026, Ludovic Rousseau
- Add support of
- ACS APG8201-B2
- BUDGET E-ID BUD001
- CHERRY Smart Board 1150
- CryptnoxCR CryptnoxCR
- Diebold Nixdorf PN7362au CCID
- FT BioPass FIDO2 Pro
- Nitrokey Nitrokey Passkey
- Add SCARD_CTL_CODE(3601): USB path of the reader
- Some other minor improvements
Allow scaling of the media size (-m arg)
Note that we cannot use gpt_size_get() as that needs gpt->secsz
to have been set already (ie: can only be used after gpt_open)
and treats unscaled numbers as multiples of sectors, whereas the
-m arg has always been a byte size.
For gpt_human_get() or simply using dehumanize_number() we
would need to handle 's' and 'b' suffixes by hand anyway, so it
is simpler to simply to the whole thing longhand in this case.
This also allows (with some hackery) for the media size to be
set as some number of sectors, when we do not yet know the
sector size - it gets corrected later once the sector size has
been determined.
[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)
Mark the memory operand of spill load/stores as MOThreadPrivate, so that
these loads and stores are emitted with `nv` set.
The reason is that scratch memory used by spills will never be shared by
another thread. It's purely thread local and thus a good fit for the
`nv` bit, which is controlled by the MOThreadPrivate flag.
Ensure sizes are a multiple of the sector size.
In gpt_size_get() ensure that the size returned is a multiple
of the sector size. This is automatic for unscaled numbers
(treated as multiples of the sector size) but in other cases
it is not automatic. Note that even nK is not guartamteed to
be a multiple of the sector size if that happens to be 4K and
n is not a multiple of 4.
[VPlan] Ignore poison incoming values when creating blend (#180005)
We have an optimization in VPPredicator when creating blends where if
all the incoming values are the same, we just return that value.
This extends it to handle cases like "phi [%x, %x, poison, %x]" by
ignoring poison values.
This is split off from #176143 to prevent regressions when maintaining
SSA by adding PHIs with a poison incoming value.
