AMDGPU: Fix true16 build_vector (0, x) pattern using a 16-bit shift operand
The real true16 pattern for (build_vector 0, VGPR_16:$x) fed the 16-bit
register directly to V_LSHLREV_B32, which takes a 32-bit operand. Widen
it with a REG_SEQUENCE first. This avoids redundant 16-bit moves in
SelectionDAG, and fixes a GlobalISel selection failure when the 16-bit
input is a G_TRUNC of a 32-bit value, as the shift's operand class
constrained the trunc result to vgpr_32.
I also don't know why this pattern is overcomplicating this. I would expect
true16 to literally translate build_vector to reg_sequence plus a materialize
of the 0.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AMDGPU: Promote 16-bit atomic load/store to extending i32
16-bit atomic loads are really extending loads into a 32-bit register,
and 16-bit atomic stores are truncating stores of a 32-bit value. Without
real true16, promote i16, f16 and bf16 atomic load and store to i32 as
any-extending loads and truncating stores, matching how regular loads
and stores are handled. With real true16, select all 16-bit types
directly using the type-generic atomic patterns, as is done for the
wider types.
Teach LegalizeDAG to promote ATOMIC_LOAD and ATOMIC_STORE to a wider
integer type, preserving the extension type. The i16-only atomic
patterns are now only needed for real true16, so remove the rest.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Fix test added in #229871 to work in C++20 mode. (#230875)
Our downstream compiler defaults to c++20 mode for the compiler, so this
newly added test from #229871 failed because in C++20 mode there are a
different set of warnings/notes emitted by the compiler.
This PR adds testing for both c++17 and c++20 modes and adds the
appropriate checks for both modes.
[VPlan] Remove unused recipe constructor overloads (NFC) (#230857)
Remove the VPSingleDefRecipe constructors without a result type (taking
only a DebugLoc, or an underlying Value and a DebugLoc) and the
VPRecipeWithIRFlags constructor without a result type. All recipes now
pass an explicit result type, so these overloads have no users.
CodeGen: Merge TargetLoweringObjectFile::getModuleMetadata into Initialize (#226837)
getModuleMetadata had a single caller, which invoked it immediately
after Initialize. Pass the module to Initialize and fold it in.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
[Verifier][IR] Make sure bitcast doesn't change type size (#230914)
`CastInst::castIsValid` doesn't check whether the source type and
destination type share the same size for bitcast between pointer and
byte types. Since DL is unavailable in this function, we perform the
DL-aware size check in the verifier. `CastInst::castIsValid` also
rejects unsized and target extension types to avoid assertions in
`getTypeSize`.
The tests are generated by DeepSeek-V4.1-Flash. Without this check llubi
will assert in `fromBytes/toBytes`.
[llubi] Reset retval for noop inline asm (#230849)
When a call is followed by a call to noop inline asm, `setResult` inside
`returnFromCallee` will reuse the previous return value (moved) and
trigger assertions.
The test is generated by DeepSeek-V4.1-Flash.
[llubi] Use correct tag bitwidth to recover provenances (#230852)
Tag always uses the pointer width rather than the padded one. Previously
the tag lookup always missed due to the width mismatch.
The test is generated by DeepSeek-V4.1-Flash.
[llubi] Fix wrong assert when writing `poison` at an unaligned bit offset (#230819)
Writing `poison` that starts at a bit offset not a multiple of 8 and
spans more than one byte could trigger an assert, even though each write
stayed within a single byte.
- `Context::toBytes` marks bits as `poison` one byte at a time, from
`OffsetInBits + I`.
- The assert checked the bits from `OffsetInBits` instead, missing the
offset `I`.
[libc++][chrono][threading] Implement LWG 3504: `condition_variable::wait_for` is overspecified (#222443)
Implement the relative-to-absolute conversion mandated by LWG 3504 using
`ceil<steady_clock::duration>` to avoid precision loss with
floating-point
durations.
- Add internal `chrono::__ceil` (usable in all dialects) and make
`chrono::ceil`
forward to it.
- Introduce `__rel_to_abs` helper and update all `wait_for` overloads on
`condition_variable` / `condition_variable_any`.
- Move the previous nanosecond conversion into `__do_timed_wait` to
avoid recursion after the change.
- Add regression tests for floating-point durations.
Fixes #189807
Skip zvol snapshot extents in iscsi.extent.pool_import
## Problem
iSCSI extents can be backed by a read-only zvol snapshot. `pool_import` passed those paths to `zfs.resource.list_impl`, which rejects any path containing `@`, so the `pool.post_import` hook failed and volthreading was never turned off for any zvol extent on the imported pool (including at boot).
## Solution
Leave snapshot paths out of the query, the same way extent create/update/delete already do. Snapshots don't have a volthreading property, so there is nothing to set on them anyway.
[Analysis][ARM] Remove unused getNumBytesToPadGlobalArray (NFC) (#230912)
The last caller of TargetTransformInfo::getNumBytesToPadGlobalArray was
removed on June 30, 2025 in commit
183acdd27985afd332463e3d9fd4a2ca46d85cf1, leaving
TargetTransformInfoImplBase::getNumBytesToPadGlobalArray,
ARMTTIImpl::getNumBytesToPadGlobalArray, and the command-line option
UseWidenGlobalArrays unused as well.
Assisted-by: Antigravity
TwoAddressInstructions: Keep undef INSERT_SUBREG lanes defined
%reg = INSERT_SUBREG undef %reg, %subreg, subidx defines all of %reg, so
reading the lanes outside subidx afterwards is valid. Rewriting it to
undef %reg.subidx = COPY %subreg narrows the definition to subidx and
leaves those reads without a live subrange, failing the "No live subrange
at use"
machine verifier check.
When a subrange outside subidx is still live past the def, insert an
IMPLICIT_DEF of the full register and drop the undef flag. In the common
case, where the lanes the INSERT_SUBREG left undefined are dead, keep the
undef flag and avoid an IMPLICIT_DEF that survives to the end of codegen
when the COPY is not coalesced.
Co-authored-by: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
CodeGen: Remove stale last-block case when splitting a critical edge
Before f264f9ad7df5, a new block at the end of the function began at the
old end index, so the isLastMBB case had to extend live-out intervals
over it. Now the new block always ends at the old end index, so they
already cover it. The extension became a no-op, and the case also
skipped trimming registers not live into the successor, leaving a dead
segment.
block-placement.ll needs a volatile store to keep its nested loop.
common-chain.ll gets shrink-wrapped.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
