FreeNAS/freenas f0437b6src/middlewared/middlewared/plugins/network_ global_config.py, tests/api2 test_service_announcement.py

Fix tests
DeltaFile
+33-8tests/api2/test_service_announcement.py
+22-9src/middlewared/middlewared/plugins/network_/global_config.py
+55-172 files

NetBSD/pkgsrc-wip 69465bddnsdist Makefile COMMIT_MSG, powerdns PLIST

powerdns, powerdns-recursor, dnsdist: remove, updated in pkgsrc
DeltaFile
+0-299powerdns-recursor/distinfo
+0-100powerdns-recursor/cargo-depends.mk
+0-75dnsdist/Makefile
+0-61powerdns/PLIST
+0-53dnsdist/COMMIT_MSG
+0-51powerdns-recursor/Makefile
+0-63925 files not shown
+3-1,04631 files

LLVM/project 0a83196llvm/test/CodeGen/AMDGPU schedule-amdgpu-tracker-physreg.ll

[AMDGPU] Adjusted GCN tracker option after rebasing on top of
users/dhruvachak/add_physical_to_gcn_trackers_after_rename.
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
+1-11 files

LLVM/project be81a90llvm/test/CodeGen/AMDGPU bf16.ll minimumnum.bf16.ll

[AMDGPU] Regenerated tests after rebasing.
DeltaFile
+8,626-9,213llvm/test/CodeGen/AMDGPU/bf16.ll
+2,364-2,564llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,314-2,514llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+1,340-1,343llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+1,244-1,250llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+1,109-1,102llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+16,997-17,98660 files not shown
+26,853-27,93166 files

LLVM/project 93ba1d4llvm/test/CodeGen/AMDGPU call-argument-types.ll amdgcn.bitcast.768bit.ll

[AMDGPU] Regenerated tests after rebasing on top of
users/dhruvachak/add_physical_to_gcn_trackers_after_rename.
DeltaFile
+284-572llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+227-225llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+180-196llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
+171-143llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+131-80llvm/test/CodeGen/AMDGPU/bf16.ll
+88-94llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
+1,081-1,3109 files not shown
+1,477-1,70115 files

LLVM/project 38fdc71llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

[AMDGPU] Enabled GCN trackers (amdgpu-use-amdgpu-trackers) by default.

The LIT tests have been generally updated in one of the following ways:
(1) If the above option was not present and the test was auto-generated,
the test has now been auto-generated.
(2) If the above option was not present and the test was not
auto-generated, added the option -amdgpu-use-amdgpu-trackers=0 so as to
preserve any specific attributes the test was already checking.
(3) If the above option was present in a test, then its value has been
updated to reflect the change in the default.

Currently, there are 4 tests in category (2). They are:
CodeGen/AMDGPU/
  addrspacecast.ll
  schedule-regpressure-limit.ll
  schedule-regpressure-limit2.ll
  sema-v-unsched-bundle.ll

There are 8 tests in category (3). They are:

    [15 lines not shown]
DeltaFile
+77,782-77,355llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+13,255-13,280llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+9,928-9,400llvm/test/CodeGen/AMDGPU/bf16.ll
+4,484-4,395llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+3,842-3,812llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+3,802-3,690llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+113,093-111,932155 files not shown
+169,016-166,668161 files

LLVM/project 1f80bc7llvm/lib/Target/AMDGPU GCNRegPressure.cpp

clang-format fix.
DeltaFile
+3-4llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+3-41 files

LLVM/project 6744fdellvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add comment

Change-Id: I2180bba631fe4a01ed3c3fbcfa8c19cbefa84133
DeltaFile
+1-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+1-01 files

LLVM/project 8203e76llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h

Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484
DeltaFile
+7-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+7-01 files

LLVM/project 64b74c4llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

clang-format

Change-Id: I534b1a979f55339a814ef3416c2492252845add5
DeltaFile
+6-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+6-31 files

LLVM/project 2bfdfe2llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Make fence heuristic work bottom-up

Change-Id: I629cbc8905b87a962e8b123287e5f60a3154df6b
DeltaFile
+19-17llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+19-171 files

LLVM/project 6edc82allvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

[AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5
DeltaFile
+323-0llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+77-23llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+18-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+418-233 files

LLVM/project 63e3675llvm/include/llvm/IR IntrinsicsDirectX.td, llvm/test/Transforms/DirectX getpointer-sink-behavior.ll

[DirectX] Denote `dx.resource.getpointer` with `IntrInaccessibleMemOnly` and `IntrReadMem` (#193593)

`IntrConvergent` was originally added to `dx.resource.getpointer` to
prevent optimization passes (`SimplifyCFG`, `GVN`) from sinking the
intrinsic out of control flow branches, which would create phi nodes on
the returned pointer.

Using `IntrInaccessibleMemOnly` and `IntrReadMem` semantics still
prevent passes from merging or sinking identical calls across branches.
However, this allows the call to be moved within a single control flow
path.

Updates relevant tests and adds a new test to demonstrate a now legal
potential optimization.

This was discovered when
https://github.com/llvm/llvm-project/pull/188792 caused the following
failure:
https://github.com/llvm/llvm-project/actions/runs/24577221310/job/71865579618.

    [5 lines not shown]
DeltaFile
+31-0llvm/test/Transforms/DirectX/getpointer-sink-behavior.ll
+3-3llvm/test/Transforms/SimplifyCFG/DirectX/no-sink-dxgetpointer.ll
+3-2llvm/test/Transforms/GVN/no-sink-dxgetpointer.ll
+1-1llvm/include/llvm/IR/IntrinsicsDirectX.td
+38-64 files

LLVM/project 466f439llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f
DeltaFile
+7-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+7-11 files

LLVM/project 3e26f22llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-sched-effective-stall.mir

Adrress comments from https://github.com/llvm/llvm-project/pull/188658

Change-Id: Ia94c567a753168c1ffa16dc5d91195e7dd0ba044
DeltaFile
+114-114llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
+3-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+117-1172 files

LLVM/project df359d8llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 slp-fma-loss.ll

[SLP] Skip FMulAdd conversion for alt-shuffle FAdd/FSub nodes (#193960)

isAddSubLikeOp() admits alt-shuffle nodes that mix FAdd and FSub, so
transformNodes() was marking them with CombinedOp = FMulAdd. The cost
model then priced the node as a single llvm.fmuladd vector intrinsic,
but emission for an alt shuffle still goes through the ShuffleVector
path and produces fmul + fadd + fsub + shufflevector, which the backend
cannot fuse into a single fmuladd. The resulting under-count made SLP
choose the vector form over the scalar form even when the scalar form
lowers to real FMAs (e.g. fmadd + fmsub on AArch64).
DeltaFile
+12-12llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll
+2-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+14-132 files

LLVM/project ccdba25llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Remove unused function

Change-Id: I9f2de1497f793d2848dedaf645e21e07a4ba82d6
DeltaFile
+2-62llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+2-621 files

LLVM/project 2be3852llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Merge conflict

Change-Id: I24f471688f9d0604b45e95a4fa4da85fb0d9ed76
DeltaFile
+23-22llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+29-5llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+52-272 files

LLVM/project 9c4fb32llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

Formatting

Change-Id: I3d89fba145471141ef945b1de15330caa245e82d
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+4-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+8-72 files

LLVM/project 02c0716llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp

Address comments from https://github.com/llvm/llvm-project/pull/187413

Change-Id: I0fad2fc504d42b72a664f78823e63c63ba2e4045
DeltaFile
+3-7llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+3-71 files

LLVM/project bc92b41llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp AMDGPUCoExecSchedStrategy.h, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

Claude Code review

Change-Id: Iab06de2981b27667cc29a56931dd378ecf7a1b0c
DeltaFile
+115-109llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+16-26llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+5-0llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+136-1353 files

LLVM/project f27ded2llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.cpp GCNSchedStrategy.cpp, llvm/test/CodeGen/AMDGPU coexec-scheduler.ll

[AMDGPU] Add block carried latency to CoExecSched

Change-Id: Ib04e40e57d38e127d6c5452d1719e32dacef2ade
DeltaFile
+880-4llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
+167-7llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+0-37llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+23-6llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+0-4llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+1,070-585 files

LLVM/project 9e4ef19llvm/lib/Target/AMDGPU AMDGPUCoExecSchedStrategy.h AMDGPUCoExecSchedStrategy.cpp

Address Review comments

Change-Id: I6972e887edd5db44ee9bcaed1f79e0c9933f611e
DeltaFile
+17-3llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
+6-1llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+23-42 files

FreeBSD/ports 94ac9catextproc/py-jinja2-cli Makefile distinfo, textproc/py-jinja2-cli/files patch-pyproject.toml

textproc/py-jinja2-cli: Update to 1.0.1

PR:             294758
Reported by:    Einar Bjarni Halldórsson <einar at isnic.is>
DeltaFile
+11-0textproc/py-jinja2-cli/files/patch-pyproject.toml
+6-5textproc/py-jinja2-cli/Makefile
+3-3textproc/py-jinja2-cli/distinfo
+20-83 files

LLVM/project 1ba6cc0clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-intrinsics.c

[clang][CIR] Add lowering for vcvtd_n_ and vcvts_n_ conversion intrinsics (#190961) (#193273)

This PR adds lowering for the missing conversion intrinsics with an
immediate argument (identified by `_n_` in the intrinsic name), namely
the `vcvts_n_` and `vcvtd_n_` variants.

It also moves the corresponding tests from:
  * clang/test/CodeGen/AArch64/neon_intrinsics.c

to:
  * clang/test/CodeGen/AArch64/neon/intrinsics.c

The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.

Reference:
[1] https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
DeltaFile
+88-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-80clang/test/CodeGen/AArch64/neon-intrinsics.c
+8-0clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+96-803 files

LLVM/project cbda767llvm/lib/IR ModuleSummaryIndex.cpp, llvm/lib/Transforms/IPO FunctionImport.cpp

[ThinLTO] Reduce the number of renaming due to promotions in distribu… (#188074)

…ted mode

For thin-lto, the pull request [1] reduced the number of renaming due to
promotions in process mode. This has been used in linux kernel ([2]) as
it helps kernel live patching a lot.

Recently, I found Rong Xu has added thin-lto distributed mode support in
linux kenrel ([3]) and it is likely to be merged in kernel as well. So
it would be a good idea for llvm to support reducing the number of
renaming in distributed mode too.

To implement this, in function gatherImportedSummariesForModule(),
import functions into summaries if those functions does not need rename.
This will ensure that imported functions have the same name as in there
original module.

  [1] https://github.com/llvm/llvm-project/pull/183793

    [3 lines not shown]
DeltaFile
+86-0llvm/test/ThinLTO/X86/reduce-promotion-same-local-name-distributed.ll
+56-0llvm/test/ThinLTO/X86/reduce-promotion-distributed.ll
+30-0llvm/lib/Transforms/IPO/FunctionImport.cpp
+5-7llvm/lib/Transforms/Utils/FunctionImportUtils.cpp
+7-0llvm/lib/IR/ModuleSummaryIndex.cpp
+184-75 files

LLVM/project e8f32abllvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/CodeGen TargetInstrInfo.cpp

CodeGen: Fix double counting bundles in inst size verification (#191460)

The AMDGPU implementation handles bundles by summing the
member instructions. This was starting with the size of the
bundle instruction, then re-adding all of the same instructions.

This loop is over the iterator, not instr_iterator, so it should
not be looking through the bundled instructions. Most of the other
uses of getInstSizeInBytes are also on the iterator, not the
instr_iterator so the convention seems to be targets need to handle
BUNDLE correctly themselves.
DeltaFile
+1-12llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+1-12llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+1-12llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+12-0llvm/lib/CodeGen/TargetInstrInfo.cpp
+0-12llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+8-0llvm/include/llvm/CodeGen/TargetInstrInfo.h
+23-4814 files not shown
+41-6320 files

FreeNAS/freenas c14f774src/middlewared/middlewared/plugins/zfs destroy_impl.py snapshot_create_impl.py

NAS-140785 / 26.0.0-BETA.2 / Mypy fixes (#18803)
DeltaFile
+1-1src/middlewared/middlewared/plugins/zfs/destroy_impl.py
+1-1src/middlewared/middlewared/plugins/zfs/snapshot_create_impl.py
+2-22 files

FreeNAS/freenas 8d98fe5src/middlewared/middlewared/plugins/network_ global_config.py, tests/api2 test_service_announcement.py

Fix tests
DeltaFile
+22-9src/middlewared/middlewared/plugins/network_/global_config.py
+6-1tests/api2/test_service_announcement.py
+28-102 files

NetBSD/pkgsrc-wip 3230020rust-beta Makefile

rust-beta: fix last comment

More clean-up will follow upon beta.5 release.
DeltaFile
+6-6rust-beta/Makefile
+6-61 files