[lld][llvm-objcopy] Fix iterator invalidation when mutating vectors during iteration (#228183)
In lld/wasm/Driver.cpp (processStubLibraries), addStubSymbolDeps() can
insert new symbols into the symbol table, reallocating the underlying
symbol vector and invalidating range-for iterators over
symtab->symbols(). Iterate by index instead.
In llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp (removeNotes),
Obj.updateSectionData() replaces a section by appending a new section to
the object's sections vector, which can reallocate the vector and
invalidate range-for iterators over Obj.sections(). Collect the matching
SHT_NOTE section pointers before iterating and updating section data.
Motivation: these iterator invalidations cause failures when vector
growth rate is lowered from 2x (which I'm experimenting with).
Note: these fixes were generated by AI, but I (the human ezbr) added the
comments manually and am in the loop.
[clang] Set _GNU_SOURCE for AArch64 bare-metal targets (#225071)
Set the _GNU_SOURCE macro when compiling for aarch64-none-elf in C++
mode. This enables GNU interfaces globally so libc++ headers can use
libc functions such as `strtof_l`. This also matches ARM.cpp when
compiling for arm-none-eabi, further aligning aarch64 and arm bare-metal
behaviour.
[InstCombine] Fold fpto[su]i of llvm.trunc
fptoui and fptosi already round toward zero, so a preceding llvm.trunc
is redundant and the conversion can take the untruncated value. NaN,
infinity, and out of range inputs produce poison in both forms.
```llvm
%t = call float @llvm.trunc.f32(float %x)
%r = fptosi float %t to i32
-->
%r = fptosi float %x to i32
```
The trunc may have other users; only the conversion operand is replaced.
ipsec: move ping_hosts.sh to legacy plugin and harden
The script doesn't need to be in core and does not need to be
run by default. Tampering with /tmp/tmpHOSTS without legacy
IPsec running would allow creating the file with a non-root
user which the script would pick up and potentially evaluate.
The fix for ping_hosts.sh will be in the matching plugins commit.
Reported by: Adam Korczynski of Ada Logics using Anrophic
X86: Mark the dead EFLAGS clobbers in the SjLj expansions (#227271)
The zero materializations and the shadow stack delta shifts emitted by
the setjmp/longjmp custom inserters never have their EFLAGS clobber
read, so set the dead flag where the instructions are built.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
[AArch64][SDAG] Generate TBL for shuffles in single block loops. (#227593)
When lowering shuffles we can either generate multiple zip/trn/ins/etc,
or a single tbl with a mask generated from a constant pool. The sequence
of 2 instructions will be quicker and smaller for a one-off instruction,
the tbl will be quicker if the mask load is loop invarinant and can be
loaded once and used many times.
This and several other places are examples of where the lowering should
be dependant on whether the current basic block is inside a relatively
small loop. (Very large loops act like standard straight-line code).
This patch adds a simple heiristic that makes use of the current
BasicBlock being selected, changing the behaviour of shuffle generation
if it is a single self-looping block. This keeps the types of block
where this would apply constrained and ensures it will only trigger for
small loops that can reliably pull the constant pool out of the loop. If
this is acceptable there are a few other optimizations that could reuse
the same pattern.
[libc++] Don't explicitly rethrow in flat container function try blocks (#230988)
We currently have some relatively complex code in the flat containers'
function catch blocks to work around a GCC warning. Instead, we can let
the rethrow happen implicitly.
As a drive-by this also simplifies the brace positioning.
[VPlan] Do not clear the NUW flag on the IV increment during lowering (#230550)
Removes the call in addVPLaneMaskPhiAndUpdateExitBranch which
clears the NUW flag if present. If the canonical IV increment
can overflow for any candidate VF, tryToBuildVPlan already
clears the flag earlier when building the plan.
[libc++] Merge the various search loops in __hash_table (#230440)
The core part of the search is always the same, so we can save some code
duplication. The hash and chash are passed into the new function to
avoid recalculating it.
[LV][NFC] Add early bail-out in setCostBasedWideningDecision (#230414)
While doing recent work to improve the debug output when setting
widening decisions I realised that we were unnecessarily printing out
debug for all members of the interleave group. I thought in general it's
perhaps clearer to bail out early if a particular memory access has
already been decided.
[LSR] Prefer equality loop exits for targets
Allow targets to request conversion of relational latch exits to
equality comparisons when SCEV can determine a constant exit value.
Keep correctness independent of poison-derived nowrap flags. Pass
the new comparison through LSR post-increment handling.
Enable it for RISC-V Zibi immediates when the original comparison
does not already lower to a branch against x0.
Assisted-by: TRAE CLI (GPT-5.6-Sol)
[LSR] Precommit tests for relational loop exits
Add baseline IR and assembly coverage for relational latch exits
with unit and non-unit induction variable strides.
Assisted-by: TRAE CLI (GPT-5.6-Sol)
[AMDGPU] Do not widen int to fp sources to i64 (#231324)
There is no instruction that converts from a 64-bit integer, so folding
(sint_to_fp (trunc nsw x)) and (uint_to_fp (trunc nuw x)) to the i64
source replaces a 32-bit conversion with the i64 expansion.
[Attributor] Only follow addrspacecasts in AAPointerInfo (#225290)
AAPointerInfo followed every cast of a pointer except ptrtoint
instructions. A ptrtoaddr, a ptrtoint/ptrtoaddr constant expression, or
a bitcast to a byte type thus produced a non-pointer value that was
tracked as a pointer, which asserted in getPointerAddressSpace() once it
reached a PHI.
Only follow addrspacecasts, the only casts that preserve the pointer.
Fixes #221852.
Assisted-by: Claude
TableGen: Move value reference locations into Record
RecordVal kept reference locations that only the TableGen language
server uses, but every copy of every field paid for them. Keep them in
the owning Record instead. This shrinks RecordVal from 48 to 32 bytes.
Parsing AMDGPU.td with llvm-tblgen --null-backend, peak memory drops
from 834 MB to 638 MB with 22% fewer page faults.
Add a language server test for references to fields and template
arguments, which were not covered before.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[DebugInfo] Remove dead debug intrinsic handling (NFC) (#231379)
This patch removes leftover code for legacy debug intrinsics
(DbgInfoIntrinsic and its subclasses) in two categories:
- Conditional checks, assertions, and switch cases that never trigger
because debug intrinsics do not appear in these passes.
- Unused member functions on DbgVariableIntrinsic, DbgValueInst, and
DbgAssignIntrinsic, along with the unimplemented
Verifier::visitDbgLabelIntrinsic declaration.
Note that this patch leaves the DirectX backend alone for now because
it still converts DbgRecord objects back into debug intrinsics during
DXIL lowering.
Assisted-by: Antigravity
[AArch64] Reorder callee-saved spills to maximise load/store register groupings (#229349)
Currently, the callee-saved spills reorder to maximize ZPR pairs, but do
not reorder to maximize ZPR quads. Modify the reordering algorithm to
also maximize ZPR quads and pairs.
Note: Quad spills are not enabled yet but will implemented in a
subsequent PR.
The main idea behind the reordering is to align the starting offset of
the ZPR quads when we begin the spill due to the conditions required to
form a ZPR quad store/load. To do this, we calculate the starting offset
and use pairs/single spills to align the offset.
RISCV: Make GPRAll non-allocatable
GPRAll contains the reserved DUMMY_REG_PAIR_WITH_X0, which cannot be
spilled, so the class should not be allocatable. Nothing creates virtual
registers in it yet, but inline asm constraint lookup returns GPRAll for
cases like {x8} with i32 on riscv64.
This increases spilling in some tests due to RegisterClassInfo defects.
RegisterClassInfo::computePSetLimit subtracts the reserved registers of
the largest allocatable class in the GPR pressure set, which is now
GPRF16 instead of GPRAll. The reserved dummy unit is no longer
subtracted, raising the limit by one.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
