AMDGPU: Remove deprecated getArchAttr and ArchFeatures TableGen
Everything should now use getFeatureBitset*
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[clang-tools-extra][docs] Fix stylesheet cache busting and table wrapping
Generate Furo's combined light and dark Pygments stylesheet before Sphinx renders HTML so the cache-busting query matches the final file. Rebuild HTML when the generated stylesheet changes.
Allow the two clang-tidy check tables to wrap long identifiers and give their columns semantic widths.
AMDGPU: Migrate R600 onto generated TargetParser bitset
Follow the new amdgcn system so we don't have to carry 2 different
forms of this infrastructure.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[MLIR][CMake] Remove aggregate generated-header ordering
Remove the broad mlir-headers prerequisites now that direct links and
HEADER_LIBS relationships provide generated-header ordering.
Keep own generators and intentional source-generation dependencies explicit.
Document migration options for downstream projects that relied on aggregate
ordering.
Assisted-by: Codex
Assisted-by: Claude Code
Co-Authored-By: Claude Fable 5.1 <noreply at anthropic.com>
[MLIR][CMake] Add HEADER_LIBS and document CMake infrastructure
Add HEADER_LIBS as a flat list of literal library targets for generated headers
included without a link relationship. Resolve aliases and forward references,
accept imported libraries as already generated, follow nested HEADER_LIBS and
link interfaces, and reject missing, executable, utility, or generator-
expression entries with configure-time diagnostics. Represent header-only
edges in the common internal INTERFACE graph, including cyclic relationships.
Record links added by mlir_target_link_libraries for the same deferred ordering.
Add explicit, commented HEADER_LIBS edges for every audited header-only include
that is not covered by mlir-generic-headers, and keep this facility a rare
layering escape hatch.
Document dialects, interfaces, passes, PDLL, generated documentation, library
visibility, C API aggregation, tools, exports, standalone consumers, and the
generated-file model. Add a CMake fixture covering cycles, aliases, conditions,
LINK_ONLY, imported and ignored items, post-hoc links, and invalid providers.
Build each consumer independently from a clean state to verify transitive
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X86: Mark EFLAGS dead on MOV32r0 emitted outside SelectionDAG
Currently these get set by LiveVariables after the fact, but
ideally we would not rely on that since it's long overdue for
deletion.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
AMDGPU: Remove deprecated getArchAttr and ArchFeatures TableGen
Everything should now use getFeatureBitset*
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
AMDGPU: Migrate R600 onto generated TargetParser bitset
Follow the new amdgcn system so we don't have to carry 2 different
forms of this infrastructure.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[CIR] Drop res_attrs when a rewritten return has no result
An Indirect return moves the value to an sret pointer argument the pass
inserts, and an Ignore return drops it, so the rewritten func or call
has no result for the per-result `res_attrs` array to describe. The
function rewrite and both call rewrites now remove it.
Assisted-by: Cursor / claude-opus-5
ZIO: Batch lightweight ZIOs
This further develops concept of ZIO batching from #18921, extending
it from the leaf vdev layer up the stack. Now it covers the case of
I/O scheduler enabled, not covered before. I/O aggregation of the
scheduler can complete several ZIOs at once, creating opportunity
for batching.
This change allows ZIO pipeline stages to return more than one ZIO,
chaining them via the field added in previous commit, renaming it
to more generic io_exec_next. To identify ZIOs to batch, this change
introduces a new ZIO flag ZIO_FLAG_LIGHTWEIGHT, set for members of
a batch. So once zio_done() or possibly other stage handlers return
a list of ZIOs, zio_execute() has now ability to decide which of them
to execute itself, and which to dispatch to taskqueues as before.
With this change my tests of 32KB block writes to 3x 5-wide NVMe RAIDZ1
on 64-core system with scheduler=on show throughput increase from
15.0GiB/s to 16.1GiB/s, while the taskqueue lock contention is
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[SandboxVec][VecUtils] Introduce DeadInstrMorgue
Move dead instructions collector and erasor into VecUtils, so that
it is usable by both, BundleVec and LoadStoreVec, vectorizers. NFC
[mlir] Migrate aggregate builders to explicit properties
Pass typed property structs and discardable attributes separately at ODS
aggregate builder call sites. Preserve direct FIR callees and cover call
property and discardable attribute preservation in FIR and Func lowering.
Assisted-by: Codex
