[CIR] Implement support for MatrixSingleSubscript expr (#232079)
Implement support for the MatrixSingleSubscript expr in the HLSL target
with column-major support.
Issue https://github.com/llvm/llvm-project/issues/221772
[flang][OpenMP] Don't drop NOTHING with clauses in METADIRECTIVE (#233981)
A METADIRECTIVE replacement of NOTHING was treated as having no
directive, even when it had clauses. A selected `nothing apply(...)` was
therefore lowered as a no-op, silently dropping the loop transformation.
Keep NOTHING as a replacement when it has clauses, and report it as not
yet implemented in lowering.
Assisted-by: GitHub Copilot (Claude Opus 5.5)
[mlir] Reduce contention in parallel pass execution and timing (#232948)
Replace per-operation executor scans with stable per-task worker
indices. Allow default timing callbacks to run concurrently using
thread-local stacks and synchronized parent-scope publication. Existing
instrumentations and custom timing managers retain serialized callbacks
unless they opt in.
Benchmark: 200,000 trivial functions with nested CSE, Release with
assertions disabled. Medians of seven alternating samples against main,
which includes #232520. With timing enabled:
| Metric | Before | After |
|---|---:|---:|
| Pipeline wall | 1.0945 s | 0.1699 s |
| mlir-opt wall | 1.7564 s | 0.8329 s |
| mlir-opt system CPU | 15.4775 s | 2.0195 s |
This is a 6.44x pipeline speedup, 2.11x end-to-end speedup.
Assisted-by: Codex
[flang][OpenMP] Set the target in bbc's semantics context (#233976)
bbc created a target machine but never passed its triple and features to
the semantics context. Without a target triple, semantics treats device
and implementation context selectors as possibly matching, so it checked
METADIRECTIVE replacements that can never be selected for the target.
For example, bbc reported a COLLAPSE error for the SIMD replacement of
when(device={arch(nvptx64)}: simd collapse(2)) on x86-64, while flang
accepts it.
Set the semantics target triple and features from the target machine, as
the flang driver does.
Fixes https://github.com/llvm/llvm-project/issues/233027.
Assisted-by: GitHub Copilot (Claude Opus 5.5)
[libcxx][docker] Update android libc++ builders (#232887)
The base images were consolidated in #225214. Move to the new base
image.
Ensure we run as root, since the new base image runs as `gha`.
To test:
$ sudo docker compose --file \
libcxx/utils/ci/docker/docker-compose.yml build \
libcxx-android-builder
Link: #223854
[SLP] Do not seed store vectorization with struct-typed stores
Vectorized struct cannot be stored as a single wide store, exclude such
stores from the store seeds.
Fixes #234176
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/234249
AMDGPU: Stop adding kill flags in SILoadStoreOptimizer (#234189)
No pre-RA pass should try to create kill flags on virtual registers.
They're unused in any pre/mid-RA pass, and stripped by LiveIntervals.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Count WMMA scale copies against both operands
Copying a shared scale while its partner stays an SGPR adds a va_ssrc
issue without removing one. Choose copies from both scale operands.
[AMDGPU] Materialize WMMA SGPR scales to VGPRs before scheduling
v_wmma_scale scale operands accept an SGPR or a VGPR. On GFX12,
depctr_va_ssrc is a 1-deep counter, so each VALU instruction that reads
an SGPR scale takes the only scalar-source slot. A run of WMMA ops that
all read SGPR scales therefore serializes. One cross-bank copy pays for
that slot once; later WMMA ops then read a VGPR and no longer contend
for va_ssrc.
SIMaterializeWMMAScale runs at the end of the machine SSA optimizations,
after SIShrinkInstructions and before scheduling. It is skipped at -O0
and on targets older than GFX12. GFX1250 is included: the separate VALU
read-after-write hazard no longer applies there, but the dependency
counter still does.
The pass walks every WMMA that has scale_src0 and records virtual SGPR
uses of scale_src0 and scale_src1, grouped by register. Physical
registers and subregister uses are left alone. For each SGPR it inserts
a COPY into a low aligned VGPR (the lo256 class matching the scale's
[26 lines not shown]
[AMDGPU] Materialize subregister WMMA scales at lane width
Copy an SGPR subregister scale into a VGPR of that lane's size so two
lanes of one tuple stay independent.
Co-authored-by: Cursor <cursoragent at cursor.com>
AArch64: Skip physical registers in MIPeepholeOpt visitORR (#234194)
Doubt this appears in any real case, but ran into this when auditing
cases which could possibly need to clear kill flags on physical
registers. Also stop using getUniqueVRegDef in an SSA pass.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeadMIElim: Require SSA
Require SSA for DeadMachineInstructionElim. This is only used in the
SSA pipeline. The only test using a non-SSA run is apparently testing
LiveIntervals preservation, which it does not use or preserve.
[mlir][tosa] Fix GCC 7 build failure in TosaProfileCompliance (#234239)
Fixes a GCC 7 build failure introduced by 45b9b97b83db (#233949).
Drop noexcept from the move constructors and move assignment operators
of VersionedTypeInfo and OpComplianceInfo to match their implicit
exception specifications.
Assisted-by: Gemini
[AArch64]Increase the cost of SVE integer compares with lower throughput
SVE integer compares write a predicate and issue on fewer pipelines than
Neon compares on many cores (Olympus: 2/cycle vs 6/cycle, Neoverse V2:
1/cycle vs 4/cycle). LoopVectorize picked vscale x 32 for an any-of
reduction over i64 compares, which runs about 2x slower than the fixed
VF 16 loop on both cores. Double the cost of scalable icmp when the
scheduling model reports lower throughput for the SVE compare than for
the Neon compare, the same way as for fcmp.
Assisted-by: Cursor
Reviewers: sjoerdmeijer, sdesmalen-arm
Pull Request: https://github.com/llvm/llvm-project/pull/233469
[llvm-c][ocaml] Accept Module instead of Context in IRBuilder bindings (#234209)
This deprecates `LLVMCreateBuilderInContext` in favor of
`LLVMCreateBuilderForModule`, which takes `LLVMModuleRef` instead of
`LLVMContextRef`.
In the OCaml bindings, `builder llcontext` is replaced with `builder
llmodule`.
This propagates https://github.com/llvm/llvm-project/pull/229430 to
bindings.
[CIR] Wire AMDGPU into the call-convention lowering pass (#220197)
**Summary:**
- Add an `AMDGPU` target to `CallConvLowering`
(`-cir-call-conv-lowering=target=amdgpu`), driven by the LLVM ABI
library's AMDGPU classifier.
- Add an AMDGPU `CIRABIClassifier` subclass and pass the calling
convention through `CIRABIClassifierCommon`.
- Report NYI for byref (IndirectAliased) and indirect arguments in
non-default address spaces.
- Add cir-opt tests for the supported cases and the NYI errors.
Clang pipeline does not select AMDGPU yet. The triple mapping and clang
tests are in #233822, stacked on this PR.
Related to issue: #220471
Assisted by: Claude Opus 4.8
Attributor: Add only new attributes when manifesting
manifestAttrs collected the attributes to add in an AttrBuilder, then
copied the position's attribute set into another AttrBuilder to merge
them in. Collect them in an array and merge them into the set in one
pass. This requires the attributes passed to manifestAttrs to be sorted
like an attribute set, which all callers already do. The only one
passing more than one attribute is AMDGPUAttributor, whose implicit
argument attributes are sorted.
Instructions spent in amdgpu-attributor:
rocPRIM test_device_scan, gfx942: 770.2M -> 710.8M (-7.7%)
Blender Cycles HIP kernel, gfx1100: 380.0M -> 379.5M (-0.1%)
rocPRIM 16 tests, full LTO, closed world: 3019.8M -> 2855.9M (-5.4%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
IR: Add attributes from an array to an attribute set
Add AttributeSet::addAttributes and AttributeList::addAttributesAtIndex
overloads taking an array of attributes sorted like an attribute set,
with distinct kinds. They merge the attributes into the set in one pass,
without first copying the set into an AttrBuilder and adding each
attribute to it.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[mlir] Reduce template work in operation registration (NFC) (#233051)
Save use 3.18% less user CPU when building LLVM/NVVM/ROCDL, and 0.96%
total user CPU when building mlir-opt. Linked mlir-opt code is 0.60%
smaller.
The main thing is to share no-op helper specializations among traits
that do not define fold, verification, region-verification, or interface
hooks. We also preserve pack order and short-circuiting while removing
the extra interface-pack forwarding instantiation.
Assisted-by: Codex
[libc++abi] Retain the old CMP0155 behavior for GCC compatibility (#232803)
Raising the minimum CMake version to 3.31 enables automatic module
dependency scanning for the C++23 libc++abi object libraries. GCC 16 and
17 then probe the libstdc++ bits/stdc++.h header when processing libc++
headers and fail if it is absent.
Set CMP0155 to OLD within libc++abi until GCC's optional header lookup
is fixed. Keep the policy change scoped to libc++abi and guard it for
CMake versions predating the policy.
GCC bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127940
Assisted-by: Codex
[CIR][OpenCL] avoid sys/types.h macro issue in OpenCL Attr (#234237)
CIROpsAttributes.cpp.inc would use initializers for this that looked
like function type macros, which were defined for a while in
sys/sysmacros.h. This caused us problems.
This fixes it by renaming these to majorVersion and minorVersion.
I am going to instantly merge this as it'll unblock buildbots for
build-by-default clangir, but if someone would like to rename these
something different, please do. In the meantime this seemed like a
reasonable name.
[SLP]Fix operand to scalar lane mapping for reordered insert/store nodes
Insertelement/insertvalue and store nodes reorder only operands, so the
scalar for operand lane L is the I with ReorderIndices[I] == L. The
copyable data mapping used ReorderIndices[L] and skipped insertelement
nodes, which assigned the copyable elements to wrong users after the
dependencies are recalculated in the final scheduling.
Fixes https://github.com/llvm/llvm-project/pull/226268#issuecomment-6314083254
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/234235
