FreeBSD/src 0a35e0asys/netpfil/pf pf.c, tests/sys/netpfil/pf mld.py

pf: allow unspecified addressed for certain MLD messages

As per RFC 3590 MLD Report and Done messages are permitted to use the
unspecified address as a source address (e.g. during duplicate address
detection for the first IPv6 address). Allow this, but only this.

Reported by:    Alexander Leidinger <Alexander at Leidinger.net>
Reviewed by:    bms
See also:       OpenBSD, sashan <sashan at openbsd.org>, 60036e8507
Sponsored by:   Rubicon Communications, LLC ("Netgate")
Differential Revision:  https://reviews.freebsd.org/D59334
DeltaFile
+57-0tests/sys/netpfil/pf/mld.py
+9-1sys/netpfil/pf/pf.c
+66-12 files

FreeBSD/src 7d810f2sys/netpfil/pf pf.c

pf: Prevent pf dropping TCP state with crafted reset packet.

Revision 1.1212 of pf.c weakened the TCP reset check in stateful
connection tracking to let legitimate resets pass in the backwards
window.  Such a reset is accepted only if its acknowledgment number
matches perfectly.  But as a workaround for broken stacks, pf
replaces an acknowledgment number of 0 in a reset with the tracked
sequence of the peer.  Then the perfect match always succeeds, and
an attacker can spoof resets more easily than intended.  Use the
acknowledgment number from the wire, before the workaround has
modified it.

discovered by Minghao Zhang; OK sashan@

Obtained from:  OpenBSD, bluhm <bluhm at openbsd.org>, 1e0a1f4b82
Sponsored by:   Rubicon Communications, LLC ("Netgate")
DeltaFile
+3-2sys/netpfil/pf/pf.c
+3-21 files

LLVM/project 9707960llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination and-implied-by-operands.ll induction-exit-condition-or-and.ll

[ConstraintElim] Handle single And/Or as exit condition in loop. (#221228)

In some cases, exits conditions in the loop are And/Or of and IV-based
condition and another condition. If the loop continues only if all
conditions are true (AND + true successor is the header, OR + false
successor is the header), we can still use the IV based condition to
bound the IV.

For now, just peels a single AND/OR.

This enables folds in a few additional cases:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1193.

PR: https://github.com/llvm/llvm-project/pull/221228
DeltaFile
+468-0llvm/test/Transforms/ConstraintElimination/induction-exit-condition-or-and.ll
+22-4llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+1-2llvm/test/Transforms/ConstraintElimination/and-implied-by-operands.ll
+491-63 files

LLVM/project c529265llvm/include/llvm InitializePasses.h, llvm/include/llvm/CodeGen MachinePipeliner.h

[CodeGen][NPM] Port MachinePipeliner to NPM
DeltaFile
+95-33llvm/lib/CodeGen/MachinePipeliner.cpp
+37-9llvm/include/llvm/CodeGen/MachinePipeliner.h
+3-0llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-1llvm/lib/CodeGen/CodeGen.cpp
+1-1llvm/include/llvm/InitializePasses.h
+1-0llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-loop-carried-mem.mir
+138-445 files not shown
+143-4411 files

FreeBSD/ports 2dfe786www/py-w3lib distinfo Makefile

www/py-w3lib: update to 2.4.1

Changelog highlights (1.21.0 -> 2.4.1):
- Python 3.8+ required (dropped 2.7/3.7 support)
- Removed dependency on six
- Build converted to pep517 (hatchling backend)
- New URL parsing behavior: canonicalize_url() no longer removes dot-segments

Port changes:
- DISTVERSION 2.4.1, drop PORTREVISION
- Convert USE_PYTHON distutils -> pep517
- RUN_DEPENDS: drop py-six; add BUILD_DEPENDS on py-hatchling
- Enable tests: USE_PYTHON += pytest (241 passed, 76 xfailed)

PR:             297778
Reported by:    skreuzer
DeltaFile
+3-4www/py-w3lib/Makefile
+3-3www/py-w3lib/distinfo
+6-72 files

NetBSD/pkgsrc-wip 639c680openjdk25 Makefile distinfo

openjdk25: add bootstrap for NetBSD-*-aarch64 and NetBSD-*-x86_64
DeltaFile
+16-0openjdk25/bootstrap.mk
+6-0openjdk25/distinfo
+1-0openjdk25/Makefile
+23-03 files

FreeBSD/ports c2b3fcdTools/scripts bump-revision.sh

Tools/scripts/bump-revision.sh: insert PORTREVISION after DISTVERSIONSUFFIX

When a port has a DISTVERSIONSUFFIX, PORTREVISION was inserted right
after DISTVERSION, before DISTVERSIONSUFFIX, which breaks the variable
order required by portlint.  Insert PORTREVISION after the last version
line (DISTVERSIONSUFFIX if present, otherwise DISTVERSION/PORTVERSION).

PR:             259289
DeltaFile
+9-1Tools/scripts/bump-revision.sh
+9-11 files

FreeBSD/ports 46ab808audio/waves Makefile distinfo

audio/waves: Update to 0.1.47

- Mark BROKEN on i386 [1]. It does not compile with the following
  error:

vendor/modernc.org/libc/libc_freebsd.go:247:25: cannot use int64(off) (value of type int64) as int32 value in assignment
vendor/modernc.org/libc/libc_freebsd.go:269:50: cannot use int64(off) (value of type int64) as int32 value in assignment
vendor/modernc.org/libc/libc_freebsd.go:1638:17: invalid operation: Uint64(Uint64FromInt32(-1)) / uint64(255) * size_t(c) (mismatched types uint64 and size_t)
vendor/modernc.org/libc/libc_freebsd.go:1639:192: invalid operation: *(*uint64)(unsafe.Pointer(w)) ^ k (mismatched types uint64 and size_t)
vendor/modernc.org/libc/libc_freebsd.go:1658:42: cannot use &l1 (value of type *size_t) as *uint64 value in argument to AssignUint64
vendor/modernc.org/libc/libc_freebsd.go:1658:47: cannot use size_t((int64(X__strchrnul(tls, var1, '=')) - int64(var1)) / 1) (value of uint32 type size_t) as uint64 value in argument to AssignUint64
vendor/modernc.org/libc/libc_freebsd.go:1667:19: invalid operation: l1 + l2 + uint64(2) (mismatched types size_t and uint64)
vendor/modernc.org/libc/libc_freebsd.go:1673:48: invalid operation: l2 + uint64(1) (mismatched types size_t and uint64)
vendor/modernc.org/libc/libc_freebsd.go:1686:6: cannot use uint64(0) (constant 0 of type uint64) as size_t value in assignment
vendor/modernc.org/libc/libc_freebsd.go:1696:57: invalid operation: l + uint64(1) (mismatched types size_t and uint64)
vendor/modernc.org/libc/libc_freebsd.go:1696:57: too many errors

ChangeLog:


    [4 lines not shown]
DeltaFile
+5-5audio/waves/distinfo
+4-2audio/waves/Makefile
+9-72 files

LLVM/project 7a67a1allvm/lib/Analysis InstructionSimplify.cpp, llvm/test/Transforms/InstCombine ptr-int-cast.ll

[InstSimplify] Don't fold ptrtoint of ptradd of sub (#221188)

Don't fold `ptrtoint (ptradd (Ptr, X - ptrtoint(Ptr))) -> X`. While
valid by itself, the fact that LLVM currently does not properly model
the ptrtoint side effect means that we lose the provenance exposure of
Ptr. This results in end-to-end miscompiles that led to the revert of
#210729.

We can still perform the optimization for ptrtoaddr, which does not
expose provenance.
DeltaFile
+11-2llvm/test/Transforms/InstSimplify/ptrtoint.ll
+6-2llvm/lib/Analysis/InstructionSimplify.cpp
+6-1llvm/test/Transforms/InstCombine/ptr-int-cast.ll
+23-53 files

NetBSD/pkgsrc rf2pze0textproc/enchant2 options.mk distinfo

   enchant2: updated to 2.8.21

   2.8.21 (September 3, 2026)

   This release fixes two bugs in composite dictionaries: first, if any
   dictionary creation failed during creation of a composite dictionary,
   dictionaries already created would be leaked; and secondly, the broker error
   status could end up indicating an error incorrectly when one provider or
   language failed and a fallback later succeeded. Thanks to @lpyuu for the
   report and fixes.


   2.8.20 (August 25, 2026)

   This release improves the man page for enchant(1), mostly by documenting
   Ispell command-line options and pipe-mode commands that it ignores.
VersionDeltaFile
1.62+15-18textproc/enchant2/Makefile
1.45+4-4textproc/enchant2/distinfo
1.4+2-2textproc/enchant2/options.mk
+21-243 files

LLVM/project 6b94ea6llvm/test/CodeGen/AMDGPU/GlobalISel regbankcombiner-merge-readanylane.mir regbankcombiner-smed3.mir

comments
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-merge-readanylane.mir
+5-53 files

LLVM/project 1b4ecc4llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPU.h

comments
DeltaFile
+18-25llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+3-3llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+23-303 files

LLVM/project f89dbdallvm/lib/Target/AMDGPU AMDGPUPassRegistry.def AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankcombiner-smed3.mir regbankcombiner-clamp-fmed3-const.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankCombiner" to NPM
DeltaFile
+81-32llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+13-2llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-2llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+2-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
+2-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
+101-381 files not shown
+102-387 files

LLVM/project 2c972d4llvm/lib/Target/AMDGPU AMDGPUPassRegistry.def AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-mui.mir regbankselect-load.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankLegalize" to NPM
DeltaFile
+50-17llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+21-3llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+3-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+1-1llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+1-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
+78-231 files not shown
+79-237 files

LLVM/project f76e073llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-mui-regbankselect.mir

comments
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
+1-11 files

LLVM/project b95b9a7llvm/lib/Target/AMDGPU AMDGPUPassRegistry.def AMDGPURegBankSelect.cpp

comments
DeltaFile
+23-21llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+24-222 files

LLVM/project 54e54acllvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPUPassRegistry.def, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-mui-regbankselect.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankSelect" to NPM
DeltaFile
+44-18llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
+18-3llvm/lib/Target/AMDGPU/AMDGPU.h
+3-2llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
+68-255 files

FreeBSD/ports f06ee1bnet/py-python-ldap Makefile distinfo

net/py-python-ldap: update to 3.4.7

PR:             297276
Reported by:    Ivan Rozhuk <rozhuk.im at gmail.com>
DeltaFile
+3-3net/py-python-ldap/distinfo
+2-1net/py-python-ldap/Makefile
+5-42 files

NetBSD/src 3pOLcl1sys/arch/sparc/sparc autoconf.c

   s/Cyrus/Cypress/ in comment.
VersionDeltaFile
1.274+3-3sys/arch/sparc/sparc/autoconf.c
+3-31 files

FreeBSD/src fb144a7usr.sbin/pw pw.8

pw(8): Brace the name-or-id synopsis so it matches the code

An unbraced pipe list made -n look like it could take a uid (or gid).
Use braces for a single choice of name or id, and keep -u newuid /
-g newgid on the name invocation only. Drop the USER/GROUP OPTIONS
sentences that said -n could be a numeric id.

PR:     269193
MFC after:      3 days
Reviewed by:    bapt
Differential Revision:  https://reviews.freebsd.org/D59472
DeltaFile
+9-16usr.sbin/pw/pw.8
+9-161 files

LLVM/project 90bc5b1llvm/test/tools/gold lit.local.cfg, llvm/test/tools/gold/X86 multiple-data.s multiple-sections.ll

[gold] Switch section-ordering-file tests to use ld.bfd (#219150)

ld.bfd supports `--section-ordering-file` since 2.43. Use it if the
binutils version is sufficiently recent.

The implementation in ld.bfd is significantly different, with the
section ordering file looking more like an incomplete linker script,
rather than a plain section listing.

The addresses of the sections are also slightly different than with
ld.gold. Use hex matches + arithmetic to just check the correct
order/offsets instead of hardcoding the exact choice of address.

ld.bfd also supports --start-lib/--end-lib since 2.47, but it seems like
those don't actually work with linker plugins, so I'm not migrating them
(https://sourceware.org/bugzilla/show_bug.cgi?id=34572).

Followup to https://github.com/llvm/llvm-project/pull/130981.
DeltaFile
+27-0llvm/test/tools/gold/lit.local.cfg
+10-9llvm/test/tools/gold/X86/multiple-sections.ll
+6-11llvm/test/tools/gold/X86/multiple-data.s
+5-0llvm/test/tools/gold/X86/Inputs/multiple-data-section-ordering.txt
+48-204 files

FreeBSD/src a971034release Makefile.vm, release/tools ec2_setpass ec2_desktop_extras

EC2: Add desktop flavour

Desktop AMIs have xrdp enabled and boot to a KDE desktop; they are
as compatible as possible with EC2 Windows AMIs, setting a random
password and printing it to the console in encrypted format to be
retrieved using the EC2 GetPasswordData API.

Two rc.d scripts are included in this commit which will not exist
in the long term: ec2_addpass will become part of the ec2-scripts
package, and ec2_desktop_extras will go away once its functionality
is included elsewhere.

MFC After:      1 month
Relnotes:       yes
Sponsored by:   Amazon
DeltaFile
+73-0release/tools/ec2-desktop.conf
+60-0release/tools/ec2_desktop_extras
+58-0release/tools/ec2_setpass
+2-1release/Makefile.vm
+193-14 files

LLVM/project c01caeaclang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/CodeGen/PowerPC aix-vec-extabi-module-flag.c

PPC: Replace EnableAIXExtendedAltivecABI with "target-abi" module flag

Continue purging ABI-influencing TargetOptions fields. Eliminate this case
by migrating to a module flag, reusing the generic target-abi module flag
with a new value.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+22-21llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+12-12llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll
+18-0clang/test/CodeGen/PowerPC/aix-vec-extabi-module-flag.c
+13-0flang/test/Integration/PowerPC/aix-vec-extabi.f90
+0-11clang/lib/Driver/ToolChains/CommonArgs.cpp
+8-2llvm/lib/Target/PowerPC/PPC.h
+73-4676 files not shown
+190-18982 files

LLVM/project d1a653ellvm/lib/Target/Sparc SparcInstrInfo.h DelaySlotFiller.cpp

[Sparc] Fix instruction size for delay slot with UNIMP (#220955)

Sparc currently reports all instructions with delay slots as having
twice the size. However, there is a special case for struct returns,
where there is an extra UNIMP instruction. Move needsUnimp() into
SparcInstrInfo, and account for it in the instruction size calculation.

Part of enabling instruction size verification by default.
DeltaFile
+38-2llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+2-35llvm/lib/Target/Sparc/DelaySlotFiller.cpp
+4-0llvm/lib/Target/Sparc/SparcInstrInfo.h
+44-373 files

LLVM/project 5950bbfllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize replicate-region-branch-weights.ll

[VPlan] Fix merged replicate region frequency when only one is known. (#221607)

When merging two replicate regions guarded by the same mask, the merged
region's entry frequency should be the higher of the two original
frequencies, since it now fires whenever either original region did.

The existing check only updated the frequency when both were known,
leaving the second region's own (possibly much lower) frequency in place
whenever the first was unknown. This means we might set a misleadingly
low frequency. Conservatively set to unknown instead.
DeltaFile
+105-0llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
+8-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+113-22 files

LLVM/project 76b7218clang/utils/TableGen CIRLoweringEmitter.cpp

[CIR] Derive lowering attr names from cppClassName, not the def name

CIRLoweringEmitter built its CXX_ABI_ALWAYS_LEGAL_ATTRS entries with
GetOpCppClassName, which splits the TableGen def name at the first
underscore. That works only while every def is named CIR_<CppClassName>Attr.
When one is not, the emitter writes an `isa<>` for a class that does not
exist, and the failure lands as a compile error in generated code.

Attributes carry the authoritative name in cppClassName, which
GenerateAttrToValueVisitor was already reading. Factor that out as
GetAttrCppClassRef and use it for both attribute paths. GetOpCppClassName
stays for operations.

NFC, and checkable. No CIR attribute overrides cppClassName, so the generated
CIRLowering.inc is byte-identical.
DeltaFile
+16-10clang/utils/TableGen/CIRLoweringEmitter.cpp
+16-101 files

LLVM/project 6de2e48clang/include/clang/CIR/Dialect/IR CIREnumAttr.td CIROps.td

[CIR] Drop dead ceremony around the CIR enum attributes

Five things that no longer earn their place in the CIR enum attribute
machinery.

CIR_CleanupKindAttr carried three. Its cppClassName restated the default
AttrDef already derives. Its skipDefaultBuilders plus hand-written
AttrBuilder existed only to default $value to CleanupKind::All, which no
caller relies on, so the generated builders stayed suppressed for nothing.
And its summary and description restated the name, overriding the enum's own
"cleanup kind" that EnumAttr would otherwise inherit. The isNormal, isEH and
isNormalAndEH helpers stay.

CIR_TLSModelAttr's summary restated its name the same way, so only that goes.
CIR_DefaultValuedEnumParameter has never had a user.

NFC.
DeltaFile
+0-16clang/include/clang/CIR/Dialect/IR/CIROps.td
+0-5clang/include/clang/CIR/Dialect/IR/CIREnumAttr.td
+0-212 files

LLVM/project 4f205e9clang/include/clang/CIR/Dialect/IR CIRTypes.td CIRCUDAAttrs.td, clang/test/CIR/IR invalid-call.cir

[CIR] Move the CIR enums off the legacy EnumAttrInfo hierarchy

MLIR has two enum hierarchies. `EnumAttrInfo` doubles as an `IntegerAttr`
constraint, so every CIR enum had to clear `genSpecializedAttr` to say it did
not want one. `EnumInfo` describes a C++ enum and nothing more.

Derive the CIR bases from `I32Enum`, `I64Enum` and `I32BitEnum`, and widen
`CIR_EnumAttr` to the `EnumInfo` that upstream `EnumAttr` already takes. The
flag no longer exists to clear. `FPClassTestEnum` gets unquoted printing from
`BitEnumBase` rather than overriding `printBitEnumQuoted`, and
`CIR_KnownFuncKind` drops a `parameterPrinter` the generated `operator<<`
now covers, still spelling `#cir.func_identity<"std::find">`.

AMDGPU wraps an `I32Enum` in an `EnumAttr` with this same bracketed format.
Parsing moves to the generated `FieldParser`, whose diagnostic names the
accepted spellings, so two `expected-error` lines change. Generated attribute
code drops 16 KB as 28 inlined parsers collapse into it.
DeltaFile
+33-73clang/include/clang/CIR/Dialect/IR/CIROps.td
+23-53clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+13-9clang/include/clang/CIR/Dialect/IR/CIREnumAttr.td
+2-4clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
+1-3clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+1-1clang/test/CIR/IR/invalid-call.cir
+73-1431 files not shown
+74-1447 files

LLVM/project d1fb42bclang/include/clang/CIR/Dialect/IR CIROps.td, clang/test/CIR/CodeGenBuiltins builtin-isinf-sign.c builtin-isfpclass.c

[CIR] Migrate the FPClassTest bit enum and unquote its flags

cir.is_fp_class printed its flags inconsistently. Single-bit values came out
bare, as in `fcSNan`, while group values and combinations came out quoted, as
in `"fcInf"` and `"fcSNan|fcNegInf"`. That comes from I32BitEnumAttr setting
printBitEnumQuoted, which EnumAttr.td keeps only for backwards compatibility.

Clearing the bit and using the `enum` directive selects the separator-aware
parser and printer, so every value now spells unquoted:

  cir.is_fp_class %x, fcSNan|fcNegInf : (!cir.float) -> !cir.bool

The enum also drops its specialized IntegerAttr for a CIR_EnumAttr wrapper,
giving it the standalone spelling `#cir.fp_class<fcSNan|fcNegInf>`. This
changes operation syntax, so it updates 37 CHECK lines.
DeltaFile
+20-20clang/test/CIR/CodeGenBuiltins/builtin-fpclassify.c
+16-16clang/test/CIR/CodeGenBuiltins/builtin-isfpclass.c
+20-0clang/test/CIR/IR/enum-attrs.cir
+12-2clang/include/clang/CIR/Dialect/IR/CIROps.td
+1-1clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
+69-395 files

LLVM/project 64420a7llvm/lib/Target/PowerPC PPC.h PPCSubtarget.h, llvm/test/CodeGen/PowerPC target-abi-module-flag.ll

PPC: Read the ELF ABI from the "target-abi" module flag

Resolve the ELFv2 ABI from the effective ABI name module flag,
rather than strictly relying on the -target-abi flag.

Also start emitting "target-abi" for PPC from clang.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+37-0llvm/test/CodeGen/PowerPC/target-abi-module-flag.ll
+18-17llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+5-3llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+4-3llvm/lib/Target/PowerPC/PPCTargetMachine.h
+4-1llvm/lib/Target/PowerPC/PPCSubtarget.h
+4-0llvm/lib/Target/PowerPC/PPC.h
+72-245 files not shown
+79-3011 files