Merge tag 'spi-fix-v6.19-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A few small fixes for SPI that came in during the merge window,
nothing too exciting here"
* tag 'spi-fix-v6.19-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: microchip-core: Fix an error handling path in mchp_corespi_probe()
spi: cadence-qspi: Fix runtime PM imbalance in probe
Merge tag 'regulator-fix-v6.19-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
Pull regulator fixes from Mark Brown:
"A few fixes that came in during the merge window, nothing too
exciting - the one core fix improves error propagation from gpiolib
which hopefully shouldn't actually happen but is safer"
* tag 'regulator-fix-v6.19-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator:
regulator: spacemit: Align input supply name with the DT binding
regulator: fixed: Rely on the core freeing the enable GPIO
regulator: check the return value of gpiod_set_value_cansleep()
ZIO: ZIO_STAGE_DDT_WRITE is a blocking stage
ddt_lookup() in zio_ddt_write() might require synchronous DDT ZAP
read. Running it from interrupt taskq might lead to deadlock.
Inclusion of ZIO_STAGE_DDT_WRITE into ZIO_BLOCKING_STAGES should
hopefully fix that, even though I am not sure how I got there.
Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Alexander Motin <alexander.motin at TrueNAS.com>
Closes #17981
LinuxKPI: 802.11: lock down the "txq_scheduled" tailq
For consistency rename the "scheduled_txqs" tailq to
"txq_scheduled" and add a lock per txq ("txq_scheduled_lock[]").
We use the "_bh" locking as this called from the device driver.
This fixes panics due to concurrent access to the tailq, especially
in between "first" and "remove" on the out-direction and between
"insert" and "elem_init" on the in-direction.
This was easily reproducible just running iperf3 at basic rates for
a few seconds to minutes with multiple chipsets, not only rtw89.
Sponsored by: The FreeBSD Foundation
PR: 290636
Reported by: arved, and others before
MFC after: 3 days
[compiler-rt] follow-up to 166837, rename COMPILER_RT_FORCE_TEST_BUILTINS_DIR to COMPILER_RT_TEST_BUILTINS_DIR (#171741)
Co-authored-by: David Tenty <daltenty at ibm.com>
[RISC-V][MC] Fix tied operand register class mismatch in P-extension
I have a change to validate the operand classes emitted in the AsmParser
and that caused llvm/test/MC/RISCV/rv32p-valid.s to fail due to the rd_wb
register using a different register class from rd:
`PWADDA_H operand 1 register X6 is not a member of register class GPRPair`
This happens because tablegen's AsmMatcherEmitter emits code to literally
copy over the tied registers and does not feed them through the equivalent
of RISCVAsmParser::validateTargetOperandClass() which would allow adjusting
these operand classes.
Ideally we would handle this in tablegen (or at least add an error), but
the tied operand handling logic is rather complex and I don't understand
it yet. For now just update the rd register class to match rd_wb.
Pull Request: https://github.com/llvm/llvm-project/pull/171738
[TableGen] Replace reachable assertion with error in *ByHwMode
Having duplicate mode entries previously asserted (or silently replaced
the last value with a new one in release builds). Report an error with
a helpful message instead.
Pull Request: https://github.com/llvm/llvm-project/pull/171715
Add a _regexp-break-add and some more tests for the b alias. (#171236)
This commit leaves "b" aliased to the old _regexp-break for now. The two
variants are identical except that `_regexp-break` allows you to say:
`(lldb) b <unrecognized_input>
`
which gets translated to:
`break set <unrecognized_input>
`
So switching people to `_regexp-break-add` would be a surprising
behavior change. It would be wrong for `_regexp_break-add` have one
branch that call `break set`, so to avoid surprise, I'll add the command
and let people who are playing with `break add` instead of `break set`
can set the alias to the new one by hand for now.
[AArch64] Restrict TBI to ignore top 4 bits for Darwin targets.
In order to allow arm64 code to run on MTE environments, we need to make the
compiler only assume the top 4 bits can be ignored as MTE occupies the lower 4.
rdar://164645323
Merge tag 'slab-for-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab
Pull slab fix from Vlastimil Babka:
- A stable fix for performance regression in tests that perform
kmem_cache_destroy() a lot, due to unnecessarily wide scope of
kvfree_rcu_barrier() (Harry Yoo)
* tag 'slab-for-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab:
mm/slab: introduce kvfree_rcu_barrier_on_cache() for cache destruction
