Dreckly/dreckly ca271d8x11/xearth distinfo, x11/xearth/patches patch-gifout.c

xearth: Fix implicit decl of exit(3)
DeltaFile
+14-0x11/xearth/patches/patch-gifout.c
+1-0x11/xearth/distinfo
+15-02 files

OPNSense/core 370d04csrc/etc rc.loader

rc: steer loader ZFS handing during build
DeltaFile
+7-2src/etc/rc.loader
+7-21 files

Dreckly/dreckly e576932x11/xephem Makefile

xephem: Fix SunOS build
DeltaFile
+1-1x11/xephem/Makefile
+1-11 files

Dreckly/dreckly c2ab10ax11/xephem Makefile distinfo, x11/xephem/patches patch-aa

xephem: Update to 4.2.0
DeltaFile
+39-19x11/xephem/Makefile
+27-12x11/xephem/patches/patch-aa
+7-6x11/xephem/distinfo
+5-1x11/xephem/PLIST
+78-384 files

Dreckly/dreckly 11db684x11/xgrk distinfo, x11/xgrk/patches patch-xgrk.c

xgrk: Fix building with recent GCC.
DeltaFile
+24-0x11/xgrk/patches/patch-xgrk.c
+1-0x11/xgrk/distinfo
+25-02 files

LLVM/project e60c11fclang/lib/CIR/CodeGen CIRGenModule.cpp TargetInfo.cpp, clang/lib/CIR/CodeGen/Targets AMDGPU.cpp

[CIR][AMDGPU] Add AMDGPU-specific function attributes for HIP kernels
DeltaFile
+256-0clang/lib/CIR/CodeGen/Targets/AMDGPU.cpp
+82-0clang/test/CIR/CodeGenHIP/amdgpu-attrs.hip
+24-3clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMIR.cpp
+8-6clang/lib/CIR/CodeGen/CIRGenModule.cpp
+13-0clang/lib/CIR/CodeGen/TargetInfo.cpp
+5-0clang/lib/CIR/CodeGen/TargetInfo.h
+388-91 files not shown
+389-97 files

Dreckly/dreckly 0f0647ax11/xnodecor distinfo, x11/xnodecor/patches patch-aa

xnodecor: Fix implicit decl of rindex(3)
DeltaFile
+4-2x11/xnodecor/patches/patch-aa
+1-1x11/xnodecor/distinfo
+5-32 files

Dreckly/dreckly d56440ax11/xpaste distinfo, x11/xpaste/patches patch-aa patch-ab

xpaste: Fix build with recent gcc.
DeltaFile
+15-14x11/xpaste/patches/patch-aa
+26-2x11/xpaste/patches/patch-ab
+2-2x11/xpaste/distinfo
+43-183 files

LLVM/project bdfb59blibclc/clc/include/clc/math remquo_decl.inc, libclc/clc/include/clc/shared binary_with_out_arg_scalarize.inc

Address comments
DeltaFile
+5-0libclc/clc/include/clc/shared/binary_with_out_arg_scalarize.inc
+0-4libclc/clc/include/clc/math/remquo_decl.inc
+5-42 files

LLVM/project 083b36blibclc/clc/lib/generic/math clc_remainder.cl clc_remainder.inc

libclc: Update remainder

Previously this was failing conformance without -cl-denorms-are-zero
in the float case, and always failing in the double case.
DeltaFile
+17-212libclc/clc/lib/generic/math/clc_remainder.cl
+171-0libclc/clc/lib/generic/math/clc_remainder.inc
+188-2122 files

LLVM/project 0a0e785libclc/clc/lib/generic/math clc_remainder.inc clc_remainder.cl

libclc: Implement remainder with remquo

This fixes conformance failures for double and
without -cl-denorms-are-zero. Optimizations are
able to eliminate the unusued quo handling without
duplicating most of the code.
DeltaFile
+2-160libclc/clc/lib/generic/math/clc_remainder.inc
+1-25libclc/clc/lib/generic/math/clc_remainder.cl
+3-1852 files

LLVM/project b7ee3b0libclc/clc/lib/generic/math clc_remquo_stret.inc clc_remquo.inc

Fix missing definitions
DeltaFile
+163-0libclc/clc/lib/generic/math/clc_remquo_stret.inc
+0-154libclc/clc/lib/generic/math/clc_remquo.inc
+28-1libclc/clc/lib/generic/math/clc_remquo.cl
+191-1553 files

LLVM/project 7c6996fllvm/include/llvm/CodeGen ValueTypes.h, llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp

[ValueType][NFC] Add widenIntegerElementType method (#187816)

Fixes #187805
DeltaFile
+9-20llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+9-1llvm/include/llvm/CodeGen/ValueTypes.h
+18-212 files

LLVM/project 85ab2a9llvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

[AsmPrinter] Add generic support for verifying instruction sizes (#187703)

Many backends rely on TII reporting correct instruction sizes for MIR
level branch relaxation passes. Reporting a too small size can result in
MC fixup failures (or silent miscompiles for unvalidated fixups).

Some time ago I added validation to the PPC asm printer to verify that
the TII instruction size matches the actually emitted size. This was
very helpful to systematically fix all incorrectly reported instruction
sizes.

However, the same problem also exists in lots of other backends, so this
moves the validation into AsmPrinter, controlled by a new
getInstSizeVerifyMode() hook in TII, which is disabled by default.

The intention here is to gradually enable this validation for more
backends (which requires fixing them first).
DeltaFile
+35-0llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+0-26llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+16-0llvm/include/llvm/CodeGen/TargetInstrInfo.h
+8-0llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+3-0llvm/lib/Target/PowerPC/PPCInstrInfo.h
+62-265 files

FreeBSD/ports 0c3c387cad/surelog pkg-plist Makefile, cad/surelog/files patch-include_Surelog_Design_ModuleInstance.h patch-src_DesignCompile_CompileExpression.cpp

cad/{surelog,uhdm}: Update 1.84 => 1.86, unbreak cad/surelog on i386

cad/uhdm: Update 1.84 => 1.86

Changelogs:
* https://github.com/chipsalliance/UHDM/releases/tag/v1.86
* https://github.com/chipsalliance/UHDM/releases/tag/v1.85
* https://github.com/chipsalliance/UHDM/compare/v1.85...v1.86
* https://github.com/chipsalliance/UHDM/compare/v1.84...v1.85

* Use dynamic SOVERSION
* Pet portclippy(1) and portfmt(1)

cad/surelog: Update 1.84 => 1.86

Changelogs:
* https://github.com/chipsalliance/Surelog/releases/tag/v1.86
* https://github.com/chipsalliance/Surelog/releases/tag/v1.85
* https://github.com/chipsalliance/Surelog/compare/v1.85...v1.86

    [12 lines not shown]
DeltaFile
+179-4cad/surelog/pkg-plist
+13-15cad/surelog/Makefile
+7-7cad/surelog/files/patch-include_Surelog_Design_ModuleInstance.h
+7-7cad/surelog/distinfo
+0-10cad/surelog/files/patch-src_DesignCompile_CompileExpression.cpp
+0-10cad/surelog/files/patch-src_DesignCompile_ElaborationStep.cpp
+206-537 files not shown
+224-7913 files

LLVM/project 0d6185ellvm/test/CodeGen/AMDGPU callee-frame-setup.ll

[AMDGPU] Update test to match comment. NFC (#187273)

The comment says there shouldn't be any free registers, so update the
inline assembly to clobber all non-preserved SGPRs.
DeltaFile
+68-18llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+68-181 files

LLVM/project 31caa34llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/lib/Target/RISCV RISCVISelLowering.cpp

[LoongArch][RISCV] Fix incorrect indexing of incoming byval arguments in tail call eligibility check
DeltaFile
+48-0llvm/test/CodeGen/LoongArch/issue187832.ll
+48-0llvm/test/CodeGen/RISCV/issue187832.ll
+2-2llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-2llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+100-44 files

FreeBSD/ports 1bd6ae7print/ghostscript10 Makefile distinfo, print/ghostscript10/files patch-configure patch-base_ocr.mak

print/ghostscript10: Update to 10.07.0

* Satisfy portclippy(1)

Reviewed by:    fuz, jrm
Differential Revision:  https://reviews.freebsd.org/D55883
Release Notes:  https://ghostscript.readthedocs.io/en/gs10.07.0/News.html
DeltaFile
+32-33print/ghostscript10/Makefile
+0-17print/ghostscript10/files/patch-configure
+0-11print/ghostscript10/files/patch-base_ocr.mak
+3-3print/ghostscript10/distinfo
+35-644 files

LLVM/project bb86440clang-tools-extra/clang-tidy/bugprone DerivedMethodShadowingBaseMethodCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Correctly ignore function templates in derived-method-shadowing-base-method (#185741) (#185875)

This commit fixes a false positive in the
derived-method-shadowin-base-method clang-tidy check, as described in
[ticket 185741](https://github.com/llvm/llvm-project/issues/185741)

Fixes #185741

---------

Co-authored-by: Tom James <tom.james at siemens.com>
Co-authored-by: Zeyi Xu <mitchell.xu2 at gmail.com>
DeltaFile
+6-2clang-tools-extra/clang-tidy/bugprone/DerivedMethodShadowingBaseMethodCheck.cpp
+7-0clang-tools-extra/test/clang-tidy/checkers/bugprone/derived-method-shadowing-base-method.cpp
+4-0clang-tools-extra/docs/ReleaseNotes.rst
+17-23 files

LLVM/project de514fbbolt/include/bolt/Profile DataReader.h, bolt/include/bolt/Rewrite RewriteInstance.h

[BOLT] Remove some unused code (NFC) (#183880)

Remove some unused code in BOLT:
- `RewriteInstance::linkRuntime` is declared but not defined
- `BranchContext` typedef is never used
- `FuncBranchData::getBranch` is defined but never used
- `FuncBranchData::getDirectCallBranch` is defined but never used
DeltaFile
+0-29bolt/lib/Profile/DataReader.cpp
+0-10bolt/include/bolt/Profile/DataReader.h
+0-3bolt/include/bolt/Rewrite/RewriteInstance.h
+0-423 files

OpenBSD/src ucxe2PClib/libz compress.3 zlib.h, sys/lib/libz zlib.h

   ENONBLOCK -> EWOULDBLOCK, former does not exist
   ok tb@
VersionDeltaFile
1.35+3-3lib/libz/compress.3
1.33+1-1lib/libz/zlib.h
1.35+1-1sys/lib/libz/zlib.h
+5-53 files

OPNSense/core daefb17src/opnsense/mvc/app/views/OPNsense/Diagnostics log.volt

system: adjust spacing for severity and process name
DeltaFile
+2-2src/opnsense/mvc/app/views/OPNsense/Diagnostics/log.volt
+2-21 files

OpenBSD/src askGCsgregress/usr.bin/ssh hostbased.sh

   Add special handling of TEST_SSH_HOSTBASED_AUTH=setupandrun.

   This will MODIFY THE CONFIG OF THE SYSTEM IT IS RUNNING ON to enable
   hostbased authentication to/from itself and run the hostbased tests.  It
   won't undo these changes, so don't do this on a system where this matters.
VersionDeltaFile
1.6+21-2regress/usr.bin/ssh/hostbased.sh
+21-21 files

LLVM/project 3fa88f0mlir/lib/Dialect/Tensor/IR TensorOps.cpp, mlir/test/Dialect/Tensor canonicalize.mlir

[mlir][tensor] Fix empty tensor with cast encoding fold (#187963)

Fixed a todo where empty tensor with cast fold can't fold encoding or
attributes.
DeltaFile
+13-0mlir/test/Dialect/Tensor/canonicalize.mlir
+3-5mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
+16-52 files

OpenBSD/src RhMBQoSusr.bin/tmux grid.c

   Check lastgc is not NULL before using it, GitHub issue 4935 from Pavel
   Lavrukhin.
VersionDeltaFile
1.145+2-2usr.bin/tmux/grid.c
+2-21 files

OpenBSD/src A4KctxMusr.bin/tmux mode-tree.c

   Fix a NULL dereference and use after free, GitHub issue 4936 from Pavel
   Lavrukhin.
VersionDeltaFile
1.80+6-5usr.bin/tmux/mode-tree.c
+6-51 files

LLVM/project 66afa8fllvm/lib/Target/X86 X86ISelLoweringCall.cpp, llvm/test/CodeGen/X86 x86-fp80-ret-no-x87.ll

[X86] Emit user-friendly error for x86_fp80 with x87 disabled on x86_64 (#183932)

When compiling a function that uses `x86_fp80` on x86_64 with x87 disabled (`-mattr=-x87`), LLVM crashes with a cryptic internal error.

Fixes #182450
DeltaFile
+13-0llvm/test/CodeGen/X86/x86-fp80-ret-no-x87.ll
+13-0llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+26-02 files

OpenBSD/src gY8l2cVusr.bin/tmux input.c

   Use window options for cursor-style to avoid crash when no pane, from
   Arden Packeer in GitHub issue 4942.
VersionDeltaFile
1.255+6-5usr.bin/tmux/input.c
+6-51 files

LLVM/project 252eb2aflang/include/flang/Optimizer/Dialect FIROps.td, flang/lib/Optimizer/CodeGen CodeGen.cpp

[flang][FIR] add a new fir.bitcast operation (#187793)

This patch introduces a new bitcast operation for integer, float,
character, and logical.

The main rational for it is that it is currently not possible to express
such bitcast in FIR without going trough memory and there is a need to
have some bitcast support when interfacing with the memref dialect where
one cannot use fir.char<> and fir.logical and must use the underlying
storage type. Using fir.convert is not a good idea because it is a
semantic cast and it will for instance normalize integers when
converting from/to logical.

This could also be used to simplify the implementation of TRANSFER for
the cases of simple scalars of those types.

Assisted by: Claude
DeltaFile
+123-0flang/test/Fir/convert-to-llvm.fir
+51-9flang/lib/Optimizer/CodeGen/CodeGen.cpp
+48-0flang/test/Fir/invalid.fir
+48-0flang/lib/Optimizer/Dialect/FIROps.cpp
+28-0flang/include/flang/Optimizer/Dialect/FIROps.td
+26-0flang/test/Fir/bitcast-fold.fir
+324-91 files not shown
+348-97 files

LLVM/project d705957clang/include/clang/Basic AArch64CodeGenUtils.h, clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp

[clang][Neon] Extract code shared by classic and CIR codegen (NFC) (#186448)

Extract intrinsic maps shared by the classic and CIR codegen into a new
header, AArch64CodeGenUtils.h, which is reused by both. This keeps the
implementations in sync and avoids code duplication.

The maps are moved without modification. The accompanying code (e.g.
`ARMVectorIntrinsicInfo`) is updated to follow Clang coding style
(CamelCase instead of the camelCase used in CIR).
DeltaFile
+14-676clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+651-0clang/include/clang/Basic/AArch64CodeGenUtils.h
+2-627clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+667-1,3033 files