OPNSense/core 7eaf080src/opnsense/mvc/tests/app/library/OPNsense/Core ConfigTest.php

tests: ConfigTest: we can cast and do not need save
DeltaFile
+1-2src/opnsense/mvc/tests/app/library/OPNsense/Core/ConfigTest.php
+1-21 files

HardenedBSD/src 45b2360sys/cam/scsi scsi_all.c, sys/dev/pci pci.c

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+122-1sys/dev/usb/controller/xhcireg.h
+3-3sys/dev/usb/controller/xhci.c
+3-1sys/dev/usb/controller/xhci_pci.c
+2-2sys/cam/scsi/scsi_all.c
+1-1usr.sbin/bhyve/pci_xhci.c
+1-1sys/dev/pci/pci.c
+132-91 files not shown
+133-107 files

HardenedBSD/ports fba22b5shells/nu_plugin_formats distinfo, shells/nu_plugin_gstat distinfo

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+195-145shells/nu_plugin_polars/distinfo
+147-97shells/nushell/distinfo
+96-71shells/nu_plugin_polars/Makefile.crates
+75-57shells/nu_plugin_formats/distinfo
+73-49shells/nushell/Makefile
+65-47shells/nu_plugin_gstat/distinfo
+651-46657 files not shown
+1,164-84363 files

LLVM/project 64e3bcdllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

[AMDGPU] Add an assertion. NFCI.
DeltaFile
+1-0llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+1-01 files

FreeNAS/freenas 76040e3src/middlewared/middlewared/plugins smb.py, src/middlewared/middlewared/plugins/smb_ passdb.py

NAS-138801 / 25.10.2 / Simplify error handling for corrupted passdb.tdb file (by anodos325) (#17759)

This commit simplifies error handling when we encounter a
corrupted passdb.tdb file. The synchronize_passdb job should
automatically recover from this situation.

Original PR: https://github.com/truenas/middleware/pull/17758

---------

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+8-8src/middlewared/middlewared/plugins/smb_/passdb.py
+1-1src/middlewared/middlewared/plugins/smb.py
+9-92 files

LLVM/project fc7b7bbbolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp, bolt/unittests/Core MCPlusBuilder.cpp

[BOLT] Add assert wehn calling insertBTI on empty BBs

BOLT may generate empty BBs, e.g. around function splitting, to hold
temporary labels. If they are the target of a new indirect branch, the
BTI should be inserted into the first "real" BasicBlock.
DeltaFile
+14-0bolt/unittests/Core/MCPlusBuilder.cpp
+4-0bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+18-02 files

LLVM/project f827e4dlldb/tools/lldb-dap DAPLog.cpp

[lldb-dap] show a useful timestamp in log messages (#170737)

It becomes easier to see the time difference between requests and
responses
DeltaFile
+3-3lldb/tools/lldb-dap/DAPLog.cpp
+3-31 files

OPNSense/core 6e634f6. plist, src/opnsense/mvc/tests/app/library/OPNsense/Core ConfigTest.php

tests: add a Core\Config class test for toArray/fromArray
DeltaFile
+83-0src/opnsense/mvc/tests/app/library/OPNsense/Core/ConfigTest.php
+48-0src/opnsense/mvc/tests/app/library/OPNsense/Core/ConfigConfig/backup/config.xml
+2-0plist
+133-03 files

OPNSense/core b9d7cf3src/opnsense/mvc/tests/app/models/OPNsense/Base BaseModelTest.php, src/opnsense/mvc/tests/app/models/OPNsense/Base/BaseModelConfig/backup config.xml

tests: BaseModelTest: disable backups and mock revision

Change class invokes to self and add a $configDir variable.
DeltaFile
+79-78src/opnsense/mvc/tests/app/models/OPNsense/Base/BaseModelTest.php
+3-3src/opnsense/mvc/tests/app/models/OPNsense/Base/BaseModelConfig/backup/config.xml
+82-812 files

LLVM/project b36f89fllvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU rotr.ll rotl.ll

[AMDGPU] Make rotr illegal (#166558)

fshr is already legal and is strictly more powerful than rotr, so we
should only need selection patterns for fshr.
DeltaFile
+281-107llvm/test/CodeGen/AMDGPU/rotr.ll
+153-72llvm/test/CodeGen/AMDGPU/rotl.ll
+16-22llvm/test/CodeGen/AMDGPU/packetizer.ll
+0-27llvm/lib/Target/AMDGPU/SIInstructions.td
+7-8llvm/test/CodeGen/AMDGPU/shl.ll
+6-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+463-2364 files not shown
+465-24810 files

LLVM/project 740a3adllvm/test/CodeGen/AMDGPU atomicrmw_usub_sat.ll atomicrmw_usub_cond.ll, llvm/test/Transforms/AtomicExpand/AMDGPU expand-atomic-i32-agent.ll expand-atomic-i16.ll

AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)

Split off from https://github.com/llvm/llvm-project/pull/105553 as per
discussion there.
DeltaFile
+4,091-0llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
+1,315-0llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
+956-40llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-agent.ll
+614-284llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
+779-6llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
+686-9llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i32-system.ll
+8,441-33930 files not shown
+10,340-44536 files

LLVM/project 9e31e81clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/Sema SemaExpr.cpp

Adding compatibility tests for vector half to _Float16
DeltaFile
+75-0clang/test/SemaOpenCL/half-float16-vector-compatibility.cl
+30-30clang/include/clang/Basic/BuiltinsAMDGPU.def
+36-0clang/test/CodeGen/half-float16-vector-compatibility.cl
+6-0clang/lib/Sema/SemaExpr.cpp
+147-304 files

LLVM/project 89e9b4aclang/lib/CodeGen BackendUtil.cpp, llvm/include/llvm/Passes PassPlugin.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.5-bogner
DeltaFile
+23-10clang/lib/CodeGen/BackendUtil.cpp
+26-5llvm/include/llvm/Passes/PassPlugin.h
+0-5llvm/lib/Passes/PassPlugin.cpp
+49-203 files

FreeBSD/ports c325758textproc/py-zensical distinfo Makefile

textproc/py-zensical: Update to 0.0.11

Changelog:

https://github.com/zensical/zensical/releases/tag/0.0.11
DeltaFile
+3-3textproc/py-zensical/distinfo
+1-1textproc/py-zensical/Makefile
+4-42 files

HardenedBSD/ports c325758textproc/py-zensical distinfo Makefile

textproc/py-zensical: Update to 0.0.11

Changelog:

https://github.com/zensical/zensical/releases/tag/0.0.11
DeltaFile
+3-3textproc/py-zensical/distinfo
+1-1textproc/py-zensical/Makefile
+4-42 files

FreeBSD/ports ddf1394www/py-django-q2 distinfo Makefile

www/py-django-q2: Upgrade to 1.9.0

Changelog:

https://github.com/django-q2/django-q2/releases/tag/v1.9.0

PR:             291417
DeltaFile
+3-3www/py-django-q2/distinfo
+1-1www/py-django-q2/Makefile
+4-42 files

HardenedBSD/ports ddf1394www/py-django-q2 distinfo Makefile

www/py-django-q2: Upgrade to 1.9.0

Changelog:

https://github.com/django-q2/django-q2/releases/tag/v1.9.0

PR:             291417
DeltaFile
+3-3www/py-django-q2/distinfo
+1-1www/py-django-q2/Makefile
+4-42 files

LLVM/project db84960clang/test/CodeGen/AArch64/sme2-intrinsics acle_sme2_bfscale.c acle_sme2_bfmul.c, llvm/include/llvm/IR IntrinsicsAArch64.td

[AArch64] Add intrinsics for multi-vector FEAT_SVE_BFSCALE instructions (#163536)

These are the intrinsics prototype implemented, according to [1]
//BFMUL:
svbfloat16x2_t svmul[_bf16_x2](svbfloat16x2_t zd, svbfloat16x2_t zm) __arm_streaming;
svbfloat16x2_t svmul[_single_bf16_x2](svbfloat16x2_t zd, svbfloat16_t zm) __arm_streaming;
svbfloat16x4_t svmul[_bf16_x4](svbfloat16x4_t zd, svbfloat16x4_t zm) __arm_streaming;
svbfloat16x4_t svmul[_single_bf16_x4](svbfloat16x4_t zd, svbfloat16_t zm) __arm_streaming;

//BFSCALE
svbfloat16x2_t svscale[_bf16_x2](svbfloat16x2_t zdn, svint16x2_t zm) __arm_streaming;
svbfloat16x2_t svscale[_single_bf16_x2](svbfloat16x2_t zn, svint16_t zm) __arm_streaming;
svbfloat16x4_t svscale[_bf16_x4](svbfloat16x4_t zdn, svint16x4_t zm) __arm_streaming;
svbfloat16x4_t svscale[_single_bf16_x4](svbfloat16x4_t zn, svint16_t zm) __arm_streaming;
[1]ARM-software/acle#410
DeltaFile
+76-0clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
+76-0clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
+56-0llvm/test/CodeGen/AArch64/sme2-intrinsics-bfmul.ll
+56-0llvm/test/CodeGen/AArch64/sme2-intrinsics-bfscale.ll
+41-2llvm/include/llvm/IR/IntrinsicsAArch64.td
+24-0llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+329-21 files not shown
+340-27 files

LLVM/project bb5e556bolt/include/bolt/Core MCPlusBuilder.h, bolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp

[BOLT][BTI] rename addBTItoBBStart to insertBTI
DeltaFile
+14-14bolt/unittests/Core/MCPlusBuilder.cpp
+3-3bolt/include/bolt/Core/MCPlusBuilder.h
+1-1bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+18-183 files

FreeBSD/ports 623207ewww/apache24 Makefile distinfo

www/apache24: Security update to 2.4.66

PR:             291413
Security:       6ebe4a30-d138-11f0-af8c-8447094a420f
MFH:            2025Q4
DeltaFile
+5-2www/apache24/Makefile
+3-3www/apache24/distinfo
+8-52 files

HardenedBSD/ports 623207ewww/apache24 Makefile distinfo

www/apache24: Security update to 2.4.66

PR:             291413
Security:       6ebe4a30-d138-11f0-af8c-8447094a420f
MFH:            2025Q4
DeltaFile
+5-2www/apache24/Makefile
+3-3www/apache24/distinfo
+8-52 files

LLVM/project ac7fddbclang/lib/Analysis ThreadSafety.cpp, clang/test/SemaCXX warn-thread-safety-analysis.cpp

Add more tests
DeltaFile
+13-6clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+1-4clang/lib/Analysis/ThreadSafety.cpp
+14-102 files

LLVM/project 533b502clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/Sema SemaExpr.cpp

Adding compatibility tests for vector half to _Float16
DeltaFile
+75-0clang/test/SemaOpenCL/half-float16-vector-compatibility.cl
+30-30clang/include/clang/Basic/BuiltinsAMDGPU.def
+36-0clang/test/CodeGen/half-float16-vector-compatibility.cl
+5-0clang/lib/Sema/SemaExpr.cpp
+146-304 files

NetBSD/pkgsrc IB1YChSdoc CHANGES-2025

   Updated devel/py-incremental, devel/py-txaio
VersionDeltaFile
1.7048+3-1doc/CHANGES-2025
+3-11 files

NetBSD/pkgsrc KFjbAdAdevel/py-txaio distinfo Makefile

   py-txaio: updated to 25.12.1

   25.12.1
   Automated wheel build from commit 2d0ca8e
VersionDeltaFile
1.21+4-4devel/py-txaio/distinfo
1.20+2-2devel/py-txaio/Makefile
1.6+2-2devel/py-txaio/PLIST
+8-83 files

NetBSD/pkgsrc TnJ0xnldevel/py-incremental Makefile distinfo

   py-incremental: updated to 24.11.0

   Incremental 24.11.0 (2025-11-27)

   Features

   - Incremental now provides a CLI script, ``incremental``, allowing you to run it with ``pipx run incremental``.
     The ``incremental update`` subcommand offers the same functionality as ``python -m incremental.update``.
   - Incremental now depends on packaging instead of setuptools at runtime
   - Add Python 3.13 and 3.14 to the test matrix.


   Bugfixes

   - Build Incremental itself with Hatchling, working around failures with certain versions of setuptools


   Improved Documentation


    [8 lines not shown]
VersionDeltaFile
1.11+8-4devel/py-incremental/Makefile
1.9+4-4devel/py-incremental/distinfo
1.5+2-2devel/py-incremental/PLIST
1.1+1-0devel/py-incremental/ALTERNATIVES
+15-104 files

LLVM/project cf53228clang/lib/Analysis ThreadSafety.cpp, clang/test/SemaCXX warn-thread-safety-analysis.cpp

false-posiitve thread-safety
DeltaFile
+16-0clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+7-0clang/lib/Analysis/ThreadSafety.cpp
+23-02 files

LLVM/project d17284amlir/python/mlir ir.py, mlir/test/python/ir auto_location.py

[python] Fix loc_tracebacks() (#170831)

There were two bugs lurking in mlir.ir.loc_tracebacks():
  1) The default None parameter was not handled correctly (passed to a
     C++ function that expects ints.
  2) The `yield` was incorrectly indented meaning loc_tracebacks()
     could not be nested (a "generator didn't yield" exception would be
     raised).

Added testing of loc_tracebacks by replacing the custom contextmanager
in the auto_location.py test with the loc_tracebacks() API.

Had to harden the test to line number differences.

---------

Co-authored-by: James Molloy <jmolloy at google.com>
DeltaFile
+13-18mlir/test/python/ir/auto_location.py
+2-1mlir/python/mlir/ir.py
+15-192 files

LLVM/project 77b1d7fllvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp

Fixed formatting
DeltaFile
+48-32llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+48-321 files

LLVM/project 990289cllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 pr167793.ll

[X86] LowerShuffle - don't call canonicalizeShuffleMaskWithHorizOp if we could shuffle whole lanes (#170838)

canonicalizeShuffleMaskWithHorizOp was getting stuck as it was
canonicalizing a SHUFFLE(HADD(X,X)) to only refer to the results of the
LHS X, but the original shuffle was shuffling entire lanes (with
VPERM2F128), and the canonicalised shuffle was then attempting to
lowering back to the original VPERM2F128 pattern.

I think we can drop this call to canonicalizeShuffleMaskWithHorizOp once
#143000 is addressed as vectorcombine should fold away all the patterns
this addresses.

Fixes #167793
DeltaFile
+30-0llvm/test/CodeGen/X86/pr167793.ll
+12-8llvm/lib/Target/X86/X86ISelLowering.cpp
+42-82 files