[AMDGPU] Fix layering violations in AMDGPUMCExpr.cpp. NFC (#168242)
AMDGPUMCExpr lives in the MC layer it should not depend on Function.h or
GCNSubtarget.h
Move the function that needed GCNSubtarget to the one file that called
it.
[CIR] Upstream handling for BaseToDerived casts (#167769)
Upstream handling for BaseToDerived casts, adding the
cir.base_class_addr operation and lowering to LLVM IR.
shell: make HTTPS fingerprint command more readable and fix lower case "sha256"
This makes it match the OpenSSH fingerprint output.
(cherry picked from commit d6031bf593161b1fa79ef5971a188056a7de75d5)
[CMake] Declare all parts of *GenRegisterInfo.inc as outputs.
This tells the build system to check and regenerate the
*GenRegisterInfo*.inc files, should any of them be missing for
whatever reason.
A follow-up from
<https://github.com/llvm/llvm-project/pull/167700>.
deskutils/kdeconnect-kde: backport upstream patch:
Check that the device ID doesn't change during the handshake.
(cherry picked from commit d49ea24d98b0a267090aa96d45de0b59799120c2)
[MLIR][SparseTensor] Dense Outer Loop Ordering Strategy (#160168)
This PR builds upon the infrastructure set up for Sparse Tensor Loop
Ordering Heuristics (#154656) by adding a preference to have dense loops
outer and sparse loops inner.
As always I'd love to get feedback and know if there's any other
direction to go with this work that might be better.
[LLVM-Tablegen] Pretty Printing Arguments in LLVM Intrinsics (#162629)
This patch adds LLVM infrastructure to support pretty printing of the
intrinsic arguments.
The motivation is to improve the readability of LLVM intrinsics and
facilitate easy
modifications and debugging of LLVM IR.
This feature adds a property `ArgInfo<ArgIndex, [ArgName<"argName">,
ImmArgPrinter<"functionName">]>`
to the intrinsic arguments to print self-explanatory inline comments for
the arguments.
The addition of pretty print support can provide a simple, low-overhead
feature that
enhances the usability of LLVM intrinsics without disrupting existing
workflows.
Link to the RFC, where this feature was discussed:
[6 lines not shown]
[BOLT][BTI] Skip inlining BBs with indirect tailcalls
In the Inliner pass, we need to convert tailcalls to normal calls
in the BB we want to inline.
These tailcalls can be indirect: in this case we would need to update the BTI
on their TargetBB to keep correctness.
As we don't know the targets of indirect tailcalls, we should skip
inlining such blocks.
Remove shadowing "size" field from classes that inherit from SyntheticSection (#166323)
A field-named 'size' already available and perfectly usable via
inheritance from InputSection, and these variables shadow it for no good
reason.
The only interesting change here is in PaddingSection, because a
parent's field cannot be initialized via a constructor initializer list,
setting it needs to be done inside the constructor body.
[MLIR][NVVM][NFC] Re-order mem_scope and shared_space attrs (#168348)
The mbarrier Ops also require access to the `mem_scope` and
`shared_space` attributes. Hence, this patch moves their definitions
to the beginning of the file alongside the other attribute definitions.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
