FreeBSD/ports 86eadd9databases/mroonga distinfo Makefile

databases/mroonga: Update version 15.11=>15.16

Changelog: https://mroonga.org/docs/news/15.html#release-15-16
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FreeBSD/ports 259d71ddevel/py-flatland Makefile

devel/py-flatland: Return to pool
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FreeBSD/ports 4358934textproc/groonga distinfo Makefile

textproc/groonga: Update version 15.1.3=>15.1.4

Changelog: https://groonga.org/docs/news/15.html#release-15-1-4
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FreeBSD/ports 8f2f9a4www/py-gunicorn distinfo Makefile

www/py-gunicorn: Update version 25.0.1=>25.0.2

Changelog: https://github.com/benoitc/gunicorn/releases/tag/25.0.2
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FreeBSD/ports 7de69d2devel/py-doit Makefile distinfo

devel/py-doit: Update version 0.36.0=>0.37.0

Changelog: https://github.com/pydoit/doit/releases/tag/0.37.0
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+3-3devel/py-doit/distinfo
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FreeBSD/ports 3c4eecedevel/cirrus-cli distinfo Makefile

devel/cirrus-cli: Update version 0.161.3=>0.161.4

Changelog: https://github.com/cirruslabs/cirrus-cli/releases/tag/v0.161.4
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+5-5devel/cirrus-cli/distinfo
+1-1devel/cirrus-cli/Makefile
+6-62 files

FreeBSD/ports 4bf3c46databases/redis distinfo Makefile

databases/redis: Update version 8.4.0=>8.4.1

Changelog: https://github.com/redis/redis/releases/tag/8.4.1
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+3-3databases/redis/distinfo
+1-2databases/redis/Makefile
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FreeBSD/ports a1ef11fdatabases/freetds-devel distinfo Makefile

databases/freetds-devel: Update version 1.5.244=>1.5.245
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FreeBSD/ports b95fa25databases/redis82 distinfo Makefile

databases/redis82: Update version 8.2.3=>8.2.4

Changelog: Changelog: https://github.com/redis/redis/releases/tag/8.2.4
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FreeBSD/ports b7edf35databases/freetds distinfo Makefile

databases/freetds: Update version 1.5.10=>1.5.11
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+3-3databases/freetds/distinfo
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LLVM/project 7068b52libc/shared/math log10f.h, libc/src/__support/math log10f.h CMakeLists.txt

[libc][math] Refactor log10f to Header Only. (#176520)

closes : #176511
DeltaFile
+228-0libc/src/__support/math/log10f.h
+2-208libc/src/math/generic/log10f.cpp
+23-0libc/shared/math/log10f.h
+16-6utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+13-0libc/src/__support/math/CMakeLists.txt
+2-6libc/src/math/generic/CMakeLists.txt
+284-2203 files not shown
+287-2209 files

Linux/linux dc855b7Documentation/devicetree/bindings/interrupt-controller renesas,r9a09g077-icu.yaml, arch/arm64/boot/dts/renesas r9a09g077.dtsi r9a09g087.dtsi

Merge tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq chip driver updates from Thomas Gleixner:

 - Add support for the Renesas RZ/V2N SoC

 - Add a new driver for the Renesas RZ/[TN]2H SoCs

 - Preserve the register state of the RISCV APLIC interrupt controller
   accross suspend/resume

 - Reinitialize the RISCV IMSIC registers after suspend/resume

 - Make the various Loongson interrupt chip drivers 32/64-bit aware

 - Handle the number of hardware interrupts in the SIFIVE PLIC driver
   correctly

   The hardware interrupt 0 is reserved which resulted in inconsistent

    [28 lines not shown]
DeltaFile
+280-0drivers/irqchip/irq-renesas-rzt2h.c
+236-0Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml
+169-1drivers/irqchip/irq-riscv-aplic-main.c
+45-37drivers/irqchip/irq-sifive-plic.c
+73-0arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+73-0arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+876-3821 files not shown
+1,172-12027 files

pfSense/pfsense ccf782esrc/usr/local/www system.php

Simplify description wording for pre-login message
DeltaFile
+1-3src/usr/local/www/system.php
+1-31 files

LLVM/project 979132allvm/lib/Target/AMDGPU SILoadStoreOptimizer.cpp, llvm/test/CodeGen/AMDGPU promote-constOffset-to-imm-gfx12.ll promote-constOffset-to-imm-gfx12.mir

[AMDGPU] Fix LDS address correction in promoteConstantOffsetToImm for async stores (#180220)

`updateAsyncLDSAddress`, introduces by
https://github.com/llvm/llvm-project/pull/176816, previously only
handled async loads , where the LDS address is in the `vdst` operand.
Therefore Async stores produced a nullptr dereference since the LDS
address is in `vdata` for those instructions.

---------

Co-authored-by: Jay Foad <jay.foad at gmail.com>
DeltaFile
+48-0llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
+36-0llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
+14-8llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+98-83 files

LLVM/project 1e086d0llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AMDGPU dagcombine-reassociate-multi-memop.ll

[DAGCombiner] Fix crash in reassociationCanBreakAddressingModePattern for multi-memop nodes (#180268)

Two code paths in `reassociationCanBreakAddressingModePattern` were
missing a `hasUniqueMemOperand()` guard before calling
`getAddressSpace()`. Note that on `L1214` we already have the same guard
in place.

`getAddressSpace()` chains through `getPointerInfo()` to
`getMemOperand()`, which asserts that the node has exactly one memory
operand.
DeltaFile
+52-0llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll
+4-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+56-12 files

LLVM/project be335beclang/lib/CodeGen CGObjCMac.cpp, clang/test/CodeGenObjC direct-method-ret-mismatch.m

fix test
DeltaFile
+13-14clang/lib/CodeGen/CGObjCMac.cpp
+6-7clang/test/CodeGenObjC/direct-method-ret-mismatch.m
+19-212 files

FreeBSD/src 98c44ccsys/modules/brcm80211/brcmfmac Makefile

brcmfmac: deal with bus attachments to the module Makefile

As with LinuxKPI-based wireless drivers, e.g., rtw88, PCI depends
on PCI being compiled into the kernel, SDIO will depend on
MMCCAM in the kernel once supported, and USB can always be
loaded.

Sponsored by:   The FreeBSD Foundation
MFC after:      3 days
DeltaFile
+10-7sys/modules/brcm80211/brcmfmac/Makefile
+10-71 files

pfSense/pfsense 8977f0asrc/usr/local/www system_crlmanager.php

Clarify wording when a CRL does not have any certs
DeltaFile
+1-1src/usr/local/www/system_crlmanager.php
+1-11 files

LLVM/project 057ace3libc/shared/math log1pf.h, libc/src/__support/math log1pf.h CMakeLists.txt

[libc][math] Refactor log1pf to Header Only. (#176525)

closes : #176512
DeltaFile
+177-0libc/src/__support/math/log1pf.h
+2-156libc/src/math/generic/log1pf.cpp
+23-0libc/shared/math/log1pf.h
+15-6utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+14-0libc/src/__support/math/CMakeLists.txt
+2-7libc/src/math/generic/CMakeLists.txt
+233-1693 files not shown
+236-1699 files

Linux/linux 66bbe4aarch/mips/kernel cevt-r4k.c, arch/mips/sgi-ip27 ip27-timer.c

Merge tag 'irq-core-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq core updates from Thomas Gleixner:
 "Updates for the interrupt core subsystem:

   - Remove the interrupt timing infrastructure

     This was added seven years ago to be used for power management
     purposes, but that integration never happened.

   - Clean up the remaining setup_percpu_irq() users

     The memory allocator is available when interrupts can be requested
     so there is not need for static irq_action. Move the remaining
     users to request_percpu_irq() and delete the historical cruft.

   - Warn when interrupt flag inconsistencies are detected in
     request*_irq().


    [24 lines not shown]
DeltaFile
+0-959kernel/irq/timings.c
+1-111kernel/irq/internals.h
+30-51kernel/irq/manage.c
+4-20include/linux/interrupt.h
+0-11arch/mips/kernel/cevt-r4k.c
+2-8arch/mips/sgi-ip27/ip27-timer.c
+37-1,16012 files not shown
+53-1,20018 files

LLVM/project 31e1bcfllvm/lib/Target/RISCV RISCVPostRAExpandPseudoInsts.cpp RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rv64p.ll rv32p.ll

[RISCV] Add basic scalar support for MERGE, MVM, and MVMN from P extension (#180677)

These are 3 variations of the same operation with a different operand
tied to the destination register. We need to pick the one that
minimizes the number of mvs.

To do this we take the approach used by AArch64 to select between
BIT, BIF, and BSL which the same operations. We define a pseudo
with no tied constraint and expand it after register allocation based
on where the destination register ended up. If the destination
register is none of the operands, we'll insert a mv.

I've replaced RISCVISD::MVM with RISCVISD::MERGE and updated the operand
order accordingly. I find the MERGE name easier to read so I've made it
the canonical name.

Ideally we could use commuteInstructionImpl and the
TwoAddressInstructionPass
to select the opcode before register allocation. That only works if

    [14 lines not shown]
DeltaFile
+135-0llvm/test/CodeGen/RISCV/rv64p.ll
+135-0llvm/test/CodeGen/RISCV/rv32p.ll
+70-0llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+17-7llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+358-85 files

LLVM/project 04bb0e2libc/shared/math log10f16.h, libc/src/__support/math log10f16.h CMakeLists.txt

[libc][math] Refactor log10f16 to Header Only. (#176523)

closes : #176510
DeltaFile
+185-0libc/src/__support/math/log10f16.h
+2-155libc/src/math/generic/log10f16.cpp
+29-0libc/shared/math/log10f16.h
+18-1utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+18-0libc/src/__support/math/CMakeLists.txt
+2-11libc/src/math/generic/CMakeLists.txt
+254-1673 files not shown
+257-1679 files

FreeBSD/src 2274153sys/contrib/dev/broadcom/brcm80211/brcmfmac usb.c bcdc.c

brcmfmac: make USB parts compile (and not panic right away)

Fix casts and consts and add one extra error check for a NULL pointer.
This will require [a future] linuxkpi_usb.

There are very few dongles I know off:
- the original Raspberry PI USB dongle [1]
- Cisco Linksys AE1200

The reason for making USB compile despite the limited 11n 150/300 Mbit/s
adapters is that it is the simplest way to work on cfg80211 while on the
road, not requiring a full PCIe slot or another SoC for SDIO.

Sponsored by:           The FreeBSD Foundation
Hardware donated by:    Martin Husemann (martin NetBSD.org) [1]
MFC after:              3 days
DeltaFile
+52-0sys/contrib/dev/broadcom/brcm80211/brcmfmac/usb.c
+6-0sys/contrib/dev/broadcom/brcm80211/brcmfmac/bcdc.c
+58-02 files

FreeBSD/src 902136esys/compat/linuxkpi/common/include/linux/platform_data brcmfmac.h, sys/contrib/dev/broadcom/brcm80211/brcmfmac cfg80211.c pcie.c

brcm80211: add LinuxKPI files and module Makefiles

sys/compat/linuxkpi/common/include/linux/platform_data/brcmfmac.h
is based on
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
e5f0a698b34ed76002dc5cff3804a61c80233a7a ( tag: v6.17 ).

Currently only PCIe is made to compile.
It does load firmware (if needed, e.g., on arm64 with an alignment
issue fixed), and starts to come up.

To make it work there is a cfg80211 layer and netdevice integration
to do, so do not hold your breath just yet.
DeltaFile
+190-0sys/contrib/dev/broadcom/brcm80211/brcmfmac/cfg80211.c
+185-0sys/compat/linuxkpi/common/include/linux/platform_data/brcmfmac.h
+117-0sys/contrib/dev/broadcom/brcm80211/brcmfmac/pcie.c
+89-0sys/modules/brcm80211/brcmfmac/Makefile
+35-0sys/contrib/dev/broadcom/brcm80211/brcmfmac/common.c
+34-0sys/contrib/dev/broadcom/brcm80211/brcmfmac/msgbuf.c
+650-022 files not shown
+1,007-028 files

LLVM/project 7892f84llvm/test/MC/RISCV rv64zbb-aliases-valid.s rv32zbb-aliases-valid.s

[RISCV] Remove non-alias tests from rv32zbb-aliases-valid.s and rv64zbb-aliases-valid.s. NFC (#180317)

These are real instructions and are tested in rv32zbb-only-valid.s,
rv64-zbb-valid.s, or rvzbb-valid.s

I think this is some artifact of the refactoring that happened when some
of the Bitmanip extensions/instructions were removed years ago.
DeltaFile
+0-12llvm/test/MC/RISCV/rv64zbb-aliases-valid.s
+0-12llvm/test/MC/RISCV/rv32zbb-aliases-valid.s
+0-242 files

LLVM/project 5a8144dlibc/shared/math llogbl.h, libc/src/__support/math llogbl.h CMakeLists.txt

[libc][math] Refactor llogbl to be header-only (#175376)

Fixes: #175361
DeltaFile
+28-0libc/src/__support/math/llogbl.h
+23-0libc/shared/math/llogbl.h
+18-1utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+10-0libc/src/__support/math/CMakeLists.txt
+2-6libc/src/math/generic/llogbl.cpp
+1-1libc/src/math/generic/CMakeLists.txt
+82-83 files not shown
+85-89 files

LLVM/project 643c235llvm/lib/Target/SPIRV SPIRVLegalizerInfo.cpp, llvm/test/CodeGen/SPIRV/legalization icmp_extended_int.ll

[SPIRV] Legalize extended integers for compare instructions. (#180254)

Currently, legalization fails for integer (lower than 8 bit) comparison
with extensions, for example, SPV_INTEL_int4. This PR extends integers
for supported extensions.

---------

Co-authored-by: Michal Paszkowski <michal at michalpaszkowski.com>
DeltaFile
+34-0llvm/test/CodeGen/SPIRV/legalization/icmp_extended_int.ll
+4-0llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+38-02 files

LLVM/project 8dde305mlir/include/mlir/Dialect/Vector/Transforms LoweringPatterns.h, mlir/lib/Dialect/Vector/TransformOps VectorTransformOps.cpp

[mlir][vector] Add finer grained populate methods for multi_reduction (NFC). (#180750)

Thiese commits add three more populate methods for
`vector.multi_reduction`'s lowering patterns:

* populateVectorMultiReductionTransformationPatterns
* populateVectorMultiReductionFlatteningPatterns
* populateVectorMultiReductionUnrollingPatterns

These methods have a
finer level of granularity and allow users to select between unrolling,
flattening, and applying transformations that would set up operations
for unrolling and flattening.

The previous populateVectorMultiReductionLoweringPatterns method
is rewritten in terms of these new methods.
DeltaFile
+39-7mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp
+31-7mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
+37-0mlir/test/Dialect/Vector/vector-multi-reduction-lowering.mlir
+5-1mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
+112-154 files

LLVM/project 61521a9llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Ensure countable region in narrowInterleaveGroups.

This tightens the legality checks. Currently should not have any impact,
but is needed to avoid mis-compiles in follow-up changes.
DeltaFile
+10-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+10-01 files

FreeBSD/doc 3b5ca5fwebsite/static/security advisory-template.txt

SA template: Update CVE URL
DeltaFile
+1-1website/static/security/advisory-template.txt
+1-11 files