FreeBSD/ports cbc8291dns/powerdns distinfo Makefile

dns/powerdns: Update to 5.0.5

PR:             295516
Security:       0823ac26-6040-11f1-ba4a-50ebf6bdf8e9
Approved by:    maintainer

(cherry picked from commit 824add6a167bd95eb178c5778b34cda742671ba0)
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+3-3dns/powerdns/distinfo
+1-1dns/powerdns/Makefile
+4-42 files

FreeNAS/freenas 5d8ab31src/freenas/usr/local/libexec disable-rootfs-protection, src/middlewared/middlewared/plugins boot.py

NAS-141261 / 26.0.0-RC.1 / Serialize rootfs read-only/sysext toggles with a shared lock (by anodos325) (#19070)

Remove the ability for concurrent calls to do things with root
filesystem unlocked (either administratively through
disable-rootfs-protection) or internal middleware callers that do things
in /usr to clobber each other.

Protection takes belt-and-suspenders approach of taking pthread lock,
then taking flock.

Original PR: https://github.com/truenas/middleware/pull/19069

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+29-0src/middlewared/middlewared/utils/rootfs_protection.py
+17-8src/middlewared/middlewared/plugins/boot.py
+12-7src/freenas/usr/local/libexec/disable-rootfs-protection
+6-2src/middlewared/middlewared/plugins/system_advanced/nvidia.py
+64-174 files

LLVM/project 034243ellvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AMDGPU dagcombine-freeze-extract-subvector-loop.ll

Style, named test vars
DeltaFile
+25-28llvm/test/CodeGen/AMDGPU/dagcombine-freeze-extract-subvector-loop.ll
+1-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+26-302 files

LLVM/project 90bb386llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AMDGPU dagcombine-freeze-extract-subvector-loop.ll

[SelectionDAG] Fold extracts of subvector inserts

Fold extract_subvector(insert_subvector(...)) when the extraction is
outside the inserted subvector or the inserted subvector only amends
the extracted

In particular,
1. vA extract_subvector (vB insert_subvector(vB X, vC Y, C1), C2) =>
vA extract_subvector(X, C2) when [C2, C2 + A) intersect [C1, C1 + C)
is the empty set
2. ... => extract_subvector(Y, C2 - C1) if [C2, C2 + Y) is a subset of
[C1, C1 + C) - an existing simplification
3. ... => vA insert_subvector(vA extract_subvector(vB X, C2), vC Y, C1 - C2)
if [C1, C1 + C) is a subset of [C2, C2 + A) - that is, if you're only
updating the extracted sub-part.

Adds a regresssion tests for an infinite SelectionDAG cycle that is
fixed by a stack of commits that ends with this one.


    [3 lines not shown]
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+72-56llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+44-48llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+45-0llvm/test/CodeGen/AMDGPU/dagcombine-freeze-extract-subvector-loop.ll
+28-7llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+15-17llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
+4-8llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
+208-1361 files not shown
+212-1447 files

LLVM/project 3434296llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-load-store-legalisation.ll

scalable vector test updates
DeltaFile
+772-772llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+4-20llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
+4-2llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+780-7943 files

LLVM/project 6fe756allvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 vector-shuffle-combining-avx512bwvl.ll

[SelectionDAG] Fold subvector inserts into concat operands

Push insert_subvector into the containing CONCAT_VECTORS operand when the insertion is wholly contained there.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
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+34-10llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+8-36llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
+42-462 files

LLVM/project 8c982f1llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

Make this work on scalable vectors
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+12-15llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+12-151 files

LLVM/project 93ad7e0llvm/test/CodeGen/AArch64 sve-fixed-vector-llrint.ll sve-fixed-vector-lrint.ll, llvm/test/CodeGen/AMDGPU bf16.ll

[SelectionDAG] Fold extracts spanning concat operands

Factor the extract_subvector-of-CONCAT_VECTORS logic and handle
extracts that cover multiple whole concat operands by rebuilding a
smaller concat directly.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+992-904llvm/test/CodeGen/AMDGPU/bf16.ll
+187-229llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+187-229llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+196-176llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
+142-140llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+120-120llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
+1,824-1,79811 files not shown
+2,204-2,27917 files

LLVM/project 956037fllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[SelectionDAG] Fold nonzero extract-of-extract indices

Generalize the extract_subvector-of-extract_subvector fold to compose
nonzero indices instead of only handling an outer index of zero.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
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+8-8llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+8-81 files

LLVM/project 9f3674cllvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

Review feedback I forgot to push lol
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+2-2llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+2-21 files

LLVM/project e6fb47allvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

Review style etc.
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+9-10llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+9-101 files

LLVM/project e28a0c1llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/X86 freeze-vector.ll

[SelectionDAG] Track bitcast demanded elements in noundef tests

Bitcasts preserve undef/poison status, but vector bitcasts can change
which source lanes cover a demanded result lane. Map the demanded
element mask through fixed-length vector bitcasts before checking the
source where possible.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+12-36llvm/test/CodeGen/X86/freeze-vector.ll
+41-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+53-362 files

LLVM/project 4e363a0llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

Review feedback
DeltaFile
+4-8llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+4-81 files

LLVM/project 49425d9llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/X86 freeze-vector.ll

[SelectionDAG] Track demanded select elements in noundef checks

Propagate demanded elements through to the two arms of a select, and
check the condition with or without demanded elements depending on if
it's a vector or not.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+17-2llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+0-11llvm/test/CodeGen/X86/freeze-vector.ll
+17-132 files

LLVM/project bb6627bllvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

Review comments
DeltaFile
+4-9llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+4-91 files

LLVM/project fc2b3efllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/X86 freeze-fp.ll pr91005.ll

[SelectionDAG] Look through freeze in undef demanded checks

There were cycles where the freeze combiner and thet
demanded-elements simplification code would get into fights about
whethere the operands to a shuffle or a concat should be
`freeze undef` or `undef` once the simplifier had concluded zero
elements were demanded from some operation. This PR prevents such
cases.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+11-7llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+2-1llvm/test/CodeGen/X86/freeze-fp.ll
+2-1llvm/test/CodeGen/X86/pr91005.ll
+15-93 files

LLVM/project 6014499llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/X86 freeze-vector.ll

[SelectionDAG] Track demanded concat elements in noundef checks

Teach isGuaranteedNotToBeUndefOrPoison to distribute fixed-length
demanded element masks across CONCAT_VECTORS operands. This is part of
the series of fixes needed to resolve a SelectionDAG hang by making it
possible to prove certain values don't need to be frozen.

AI note: an LLM generated the code and the test, I've read them

Co-Authored-By: OpenAI Codex <codex at openai.com>
DeltaFile
+23-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+4-12llvm/test/CodeGen/X86/freeze-vector.ll
+27-122 files

LLVM/project 98eefa5clang/lib/AST ASTContext.cpp, clang/test/SemaTemplate ctad.cpp

[clang] fix assertion for DeducedAsPack DeducedTemplateSpecializationType

This fixes a regression introduced in #186727, which was never released,
so there are no release notes.

Fixes #200418
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+16-0clang/test/SemaTemplate/ctad.cpp
+0-5clang/lib/AST/ASTContext.cpp
+16-52 files

FreeNAS/freenas 712b3bdsrc/freenas/usr/local/libexec disable-rootfs-protection, src/middlewared/middlewared/plugins boot.py

NAS-141261 / 27.0.0-BETA.1 / Serialize rootfs read-only/sysext toggles with a shared lock (#19069)

Remove the ability for concurrent calls to do things with root
filesystem unlocked (either administratively through
disable-rootfs-protection) or internal middleware callers that do things
in /usr to clobber each other.

Protection takes belt-and-suspenders approach of taking pthread lock,
then taking flock.

(cherry picked from commit 88ff7ff65276f4fd818ceeed562374289181513a)
DeltaFile
+29-0src/middlewared/middlewared/utils/rootfs_protection.py
+17-8src/middlewared/middlewared/plugins/boot.py
+12-7src/freenas/usr/local/libexec/disable-rootfs-protection
+6-2src/middlewared/middlewared/plugins/system_advanced/nvidia.py
+64-174 files

LLVM/project 1970332compiler-rt/lib/scudo/standalone combined.h

[scudo] Log if randomness degrades. (#201482)
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+5-1compiler-rt/lib/scudo/standalone/combined.h
+5-11 files

FreeBSD/ports 824add6dns/powerdns distinfo Makefile

dns/powerdns: Update to 5.0.5

PR:             295516
Security:       0823ac26-6040-11f1-ba4a-50ebf6bdf8e9
Approved by:    maintainer
DeltaFile
+3-3dns/powerdns/distinfo
+1-1dns/powerdns/Makefile
+4-42 files

FreeBSD/ports bdf70f4security/vuxml/vuln 2026.xml

security/vuxml: Document PowerDNS vulnerabilities
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+48-0security/vuxml/vuln/2026.xml
+48-01 files

FreeBSD/ports 6dc0a5cbenchmarks/clpeak distinfo Makefile

benchmarks/clpeak: update to 2.0.10

Changes:        https://github.com/krrishnarraj/clpeak/releases/tag/2.0.10
Reported by:    GitHub (watch releases)
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+3-3benchmarks/clpeak/distinfo
+1-1benchmarks/clpeak/Makefile
+4-42 files

FreeNAS/freenas d4c0f67src/middlewared/middlewared/plugins/app_registry utils.py, src/middlewared/middlewared/plugins/apps_images update_alerts.py utils.py

NAS-141149 / 26.0.0-RC.1 / Use Docker Registries auth when checking for and pulling image updates (by sonicaj) (#19066)

This commit fixes an issue where the image update checker and the
middleware's own image pull ignored the credentials stored in Docker
Registries, so updates to private images (e.g. ghcr.io) were never
detected and pulls 401'd. We now thread the stored registry credentials
through the manifest/token calls and the pull fallback so the bearer
token carries read scope on private repos.

The registry-URI authority normalization that both paths rely on
(stripping scheme/path/slash and collapsing Docker Hub aliases) was
duplicated across app_registry and apps_images with slightly diverging
alias sets, so it now lives in a single
middlewared.utils.docker_registry helper that both import, with unit
tests covering the normalization.

Original PR: https://github.com/truenas/middleware/pull/19059

Co-authored-by: Waqar Ahmed <waqarahmedjoyia at live.com>
DeltaFile
+35-0src/middlewared/middlewared/utils/docker_registry.py
+33-0src/middlewared/middlewared/pytest/unit/utils/test_docker_registry.py
+23-6src/middlewared/middlewared/plugins/apps_images/update_alerts.py
+15-11src/middlewared/middlewared/plugins/apps_images/utils.py
+24-1src/middlewared/middlewared/plugins/app_registry/utils.py
+14-8src/middlewared/middlewared/plugins/apps_images/client.py
+144-266 files

FreeBSD/ports 7c9d31femulators/rpcs3 distinfo Makefile

emulators/rpcs3: update to 0.0.41

Changes:        https://github.com/RPCS3/rpcs3/compare/ea0d8a0d78...40e9ee5af0

(cherry picked from commit c9d179d2a32c4c035f57be28fb710ac82276398a)
(cherry picked from commit c0d64aeac72a7ce8006aa162de986d769724cbd5)
(cherry picked from commit 03dfe6b5a6f1a522336515f9ffc41f75b7b698ce)
(cherry picked from commit 4c160bc7a195d4e065a0f8c097de0fb2346086c3)
(cherry picked from commit 8a76a4205a564fecea9d39a1c90295edf9bbdb77)
(cherry picked from commit d84d24cdc2b103b47ef1deedf5388aa53371619f)
(cherry picked from commit af2e24f9084803c69eff96fc0b96b9c395bd850b)
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+3-3emulators/rpcs3/distinfo
+2-2emulators/rpcs3/Makefile
+5-52 files

FreeBSD/ports af2e24femulators/rpcs3 distinfo Makefile

emulators/rpcs3: update to 0.0.41

Changes:        https://github.com/RPCS3/rpcs3/compare/3fa1241ac0...40e9ee5af0
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+3-3emulators/rpcs3/distinfo
+2-2emulators/rpcs3/Makefile
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LLVM/project c5a631flldb/docs/use variable.rst variable.md

Merge branch 'main' into users/hvdijk/directx-delay-converting-debug-info
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+1,496-0lldb/docs/use/variable.md
+0-1,426lldb/docs/use/map.rst
+1,300-0lldb/docs/use/map.md
+0-741lldb/docs/use/tutorial.rst
+727-0lldb/docs/use/tutorial.md
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+8,017-7,809141 files

LLVM/project 07c318fllvm/test/CodeGen/AArch64/GlobalISel prelegalizercombiner-sextload-from-sextinreg.mir

Add missing REQUIRES: asserts to test case which needs it (#201626)
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+4-0llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
+4-01 files

FreeNAS/freenas 834aaa7src/middlewared/middlewared/api/v25_04_0 common.py, src/middlewared/middlewared/api/v25_04_2 common.py

Less false positives in markdown check
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+5-5src/middlewared/middlewared/api/v25_04_0/common.py
+5-5src/middlewared/middlewared/api/v25_10_0/common.py
+5-5src/middlewared/middlewared/api/v25_10_1/common.py
+5-5src/middlewared/middlewared/api/v27_0_0/common.py
+5-5src/middlewared/middlewared/api/v25_04_2/common.py
+5-5src/middlewared/middlewared/api/v25_10_2/common.py
+30-309 files not shown
+54-5015 files

FreeNAS/freenas c9a12dc

Empty commit to create PR on github.

You should reset it
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