FreeBSD/ports 2229f30 — security/vuxml/vuln 2026.xml

security/vuxml: Document MIT krb5 Security Advisory 2026-001
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FreeBSD/src 307e725 — contrib/netbsd-tests/kernel t_mqueue.c, tests/freebsd_test_suite macros.h

Revert "Remove {ATF,PLAIN}_REQUIRE_KERNEL_MODULE macros"

The change breaks the build of tests/sys/net/routing/test_rtsock_l3.c.

This reverts commit e34b159d4c64575aa45763968b6ad01dfd7c2337.
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+13-13tests/freebsd_test_suite/macros.h
+3-15tests/sys/net/routing/rtsock_config.h
+4-0contrib/netbsd-tests/kernel/t_mqueue.c
+0-1tests/sys/kern/Makefile
+20-294 files

NetBSD/pkgsrc 54y56fo — wm/awesome Makefile

   awesome: (smallest ever) recursive revbump for devel/lua-gi

   The real dependency for glib2-introspection lies there, and this will
   fail during the configure stage when the tooling finds it can't call
   lua-gi as it expects.
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1.111+2-4wm/awesome/Makefile
+2-41 files

LLVM/project d714d0a — llvm/test/CodeGen/AMDGPU vcmp-saveexec-to-vcmpx-set-kill.mir

Add test for v_cmp kill preserved on v_cmpx
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+20-0llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
+20-01 files

LLVM/project 4337e1d — llvm/lib/Target/AMDGPU SIOptimizeExecMasking.cpp

AMDGPU: Clear v_cmpx source kill flags locally

clearKillFlags is potentially expensive and should be avoided. When
the v_cmp is folded into a v_cmpx at the saveexec, only kills of
registers overlapping the compare sources between the v_cmp and the
saveexec become invalid. Clear those directly when applying the fold,
instead of collecting candidate kills during matching and then
clearing every kill of the sources in the function.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
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+16-351 files

NetBSD/pkgsrc gCq0URG — doc CHANGES-2026

   doc: Updated devel/lua-gi to 0.9.2nb10
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1.7910+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc MTX9ARi — devel/lua-gi Makefile

   lua-gi: mark runtime dependency on glib2-introspection

   This package exports objects provided by glib2-introspection to Lua
   runtime environments (in pkgsrc's case, anyway, just wm/awesome).

   Runtime failure of awesome noted by Fekete Zoltán on pkgsrc-users@.
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1.22+5-3devel/lua-gi/Makefile
+5-31 files

LLVM/project b5c97eb — llvm/include/llvm/Analysis VectorUtils.h, llvm/lib/Analysis VectorUtils.cpp

[SLP]Vectorize sincos with both fields used in one tree

- Reuse the vectorized struct call for the second extractvalue
  field instead of a struct gather, which rejected the tree. Do
  not trim the call while it is still reused.
- Cost vector sincos as vector sin and cos calls when
  ReplaceWithVeclib splits it; move the split check to VectorUtils.

Fixes #239948

Assisted-by: Cursor

Reviewers: bababuck, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/240154
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+23-127llvm/test/Transforms/SLPVectorizer/X86/sincos-libmvec.ll
+1-34llvm/lib/CodeGen/ReplaceWithVeclib.cpp
+23-0llvm/lib/Analysis/VectorUtils.cpp
+18-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+7-0llvm/include/llvm/Analysis/VectorUtils.h
+6-0llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
+78-1626 files

NetBSD/pkgsrc UVZWfXr — cross/mingw-w64-i686-winpthreads Makefile

   cross/mingw-w64-i686-winpthreads: Fix COMMENT
VersionDeltaFile
1.8+2-2cross/mingw-w64-i686-winpthreads/Makefile
+2-21 files

NetBSD/pkgsrc d8l75es — devel/lua-gi DESCR

   lua-gi: touch up grammar/style consistency in DESCR
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1.2+1-1devel/lua-gi/DESCR
+1-11 files

NetBSD/pkgsrc 6o3xQaw — cross/mingw-w64-i686-gcc-msvcrt DESCR

   cross/mingw-w64-i686-gcc-msvcrt: Fix typo in DESCR
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1.2+1-1cross/mingw-w64-i686-gcc-msvcrt/DESCR
+1-11 files

LLVM/project a12d184 — llvm/test/Transforms/Attributor light-preserved-analyses.ll

Attributor: Fix light-preserved-analyses.ll with GCC-built opt

The printed RequireAnalysisPass type name depends on the host
compiler. GCC omits the defaulted AnalysisManager template argument,
so the check line failed on GCC-built bots. Match it with a regex like
the other pass manager tests.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
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+1-1llvm/test/Transforms/Attributor/light-preserved-analyses.ll
+1-11 files

LLVM/project 3be6acf — compiler-rt/lib/scudo/standalone/tests wrappers_c_test.cpp

[scudo] Modify wrapper test to handle different configs. (#240642)

If enabling only a few of the AbortOnDeallocXXX flags, the wrappers test
would fail. Therefore, seperate out the different checks so that it's
possible to only test the values that are enabled.

In addition, remove the setting of the defines for Android. Use the
build system to set any necessary flags.
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+46-24compiler-rt/lib/scudo/standalone/tests/wrappers_c_test.cpp
+46-241 files

LLVM/project 7c1f7b4 — lldb/source/Plugins/ObjectFile/Mach-O ObjectFileMachO.cpp

[lldb] Fix ObjectFileMachO build on embedded (#241011)

The TARGET_OS_IPHONE-only ParseSymtab path bitrotted: #209926 dropped a
brace after the __IMPORT check and #190183 made the AsCString argument
mandatory.
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+3-2lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
+3-21 files

LLVM/project 33407fa — lldb/source/Host/macosx/objcxx HostInfoMacOSX.mm

[lldb] Fix IsBundleCodeSignTrusted build on embedded (#241010)

SecStaticCode APIs are macOS-only. Return false elsewhere.
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+4-0lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
+4-01 files

LLVM/project ad574d6 — llvm/test/CodeGen/X86 bitinsert-bitextract-vector.ll

[SelectionDAG] Use x86-64 levels in vector `bitinsert`/`bitextract` X86 test
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+361-58llvm/test/CodeGen/X86/bitinsert-bitextract-vector.ll
+361-581 files

LLVM/project a3b4efe — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/X86 vector-deinterleave7-i8.ll vector-interleave7-i32.ll

Merge branch 'main' into users/adams381/cir-get-element-inbounds

Assisted-by: Cursor / Claude Opus 5.5
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+89,147-91,827llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,378-26,402llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+29,293-0llvm/test/CodeGen/X86/vector-interleave7-i16.ll
+29,228-0llvm/test/CodeGen/X86/vector-interleaved7-i8.ll
+27,225-0llvm/test/CodeGen/X86/vector-interleave7-i32.ll
+26,140-0llvm/test/CodeGen/X86/vector-deinterleave7-i8.ll
+226,411-118,22918,815 files not shown
+1,900,944-601,79818,821 files

LLVM/project 03801ff — utils/bazel/llvm-project-overlay/libc/test/UnitTest BUILD.bazel

[bazel] Port 528affb94ef8e664f04cab92758c06886e56fea9 (#241007)

This commit also add `layering_check` to package features so future
layering issues show up in CI and can be handled by the auto-fixing
Bazel bot.
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+9-1utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
+9-11 files

LLVM/project 6367f33 — flang/lib/Optimizer/OpenACC/Transforms ACCOptimizeDataMapping.cpp, flang/test/Transforms/OpenACC acc-optimize-data-mapping.fir

[flang][acc] Issue implicit copies before optimized copyins (#240643)

Optimized copyins are appended so the remaining implicit copies are
issued first. This is done because this pass relies on alias analysis,
which takes advantage of Fortran aliasing rules: for example, dummy
arguments do not alias. However, if they did alias, then we are now
depending on the order ACCImplicitData decided to map, because a copyin
followed by a copy is not the same as a copy followed by a copyin (since
only the first data action maps, everything else updates the counter).
By issuing the copies before the copyins, we can ensure we do not break
anything even if we relied on the language rules to do the optimization.
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+80-1flang/test/Transforms/OpenACC/acc-optimize-data-mapping.fir
+61-0flang/lib/Optimizer/OpenACC/Transforms/ACCOptimizeDataMapping.cpp
+141-12 files

LLVM/project b543957 — clang/test/OpenMP irbuilder_unroll_unroll_partial_heuristic.c irbuilder_unroll_partial_heuristic_runtime_for.c, llvm/include/llvm/Frontend/OpenMP OMPConstants.h OMPIRBuilder.h

OpenMP: Stop using TTI to pick the partial unroll factor in OMPIRBuilder

When the unrolled loop's CanonicalLoopInfo is needed by an enclosing
loop directive and no factor was given, unrollLoopPartial computed one
by constructing its own TargetMachine with default TargetOptions and a
standalone FunctionAnalysisManager, then running LoopUnrollPass's cost
model on the function while it was still being built.

This is a layering violation. Frontends should not be using codegen
optimization information to construct the original program. This will
not have a properly configured TargetTransformInfo from a pass
manager. The cost model is also not meaningful on incomplete,
unoptimized IR.

Use a factor of 2, matching what Sema's OpenMP loop transformation
uses for a partial clause without a factor. This removes the hidden
-openmp-ir-builder-unroll-threshold-factor option.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
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+1-190llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+4-8llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+4-4clang/test/OpenMP/irbuilder_unroll_unroll_partial_heuristic.c
+4-4clang/test/OpenMP/irbuilder_unroll_partial_heuristic_runtime_for.c
+4-4clang/test/OpenMP/irbuilder_unroll_partial_heuristic_constant_for.c
+4-0llvm/include/llvm/Frontend/OpenMP/OMPConstants.h
+21-2101 files not shown
+22-2117 files

LLVM/project 2c0fe64 — llvm/lib/Target/Hexagon HexagonISelLoweringHVX.cpp HexagonISelLowering.h, llvm/test/CodeGen/Hexagon hlx-mem-intrinsics.ll

[Hexagon] Add HLX load and store memory intrinsics (#240995)

Lower the HLX temporary-load and new-value-store intrinsics to their
corresponding pseudo instructions and describe them as memory intrinsics
so that the selected nodes carry correct MachineMemOperands.

This adds:
- the isel patterns mapping int_hexagon_LX_L16b_tmp and
int_hexagon_LX_S16b_new onto LX_L16b_pseudo and LX_S16b_pseudo;
- getTgtMemIntrinsic support that infers the access type, pointer,
alignment, and memory flags from the intrinsic signature;
- lowering of the paired load/store intrinsics int_hexagon_LX_LL16b_tmp
and int_hexagon_LX_SS16b_new, splitting each pair access into two
single-vector accesses.

Marking INTRINSIC_W_CHAIN as custom to lower the paired HLX intrinsics
also routes HVX chained intrinsics through LowerHvxOperation, so a
pass-through case is added there to keep them selected by the existing
patterns.
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+64-0llvm/lib/Target/Hexagon/HexagonISelLoweringHLX.cpp
+33-0llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+27-0llvm/test/CodeGen/Hexagon/hlx-mem-intrinsics.ll
+8-0llvm/lib/Target/Hexagon/HexagonIntrinsics.td
+1-0llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+1-0llvm/lib/Target/Hexagon/HexagonISelLowering.h
+134-06 files

LLVM/project d8f1473 — lldb/source/Plugins/Platform/MacOSX/objcxx PlatformiOSSimulatorCoreSimulatorSupport.h PlatformiOSSimulatorCoreSimulatorSupport.mm

[lldb] Remove unused methods from PlatformiOSSimulatorCoreSimulatorSupport (#240970)
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+0-5lldb/source/Plugins/Platform/MacOSX/objcxx/PlatformiOSSimulatorCoreSimulatorSupport.h
+0-132 files

LLVM/project 2bbbf2d — llvm/lib/Transforms/IPO Attributor.cpp

Attributor: Only destroy the cached opcodes' instruction vectors

The FunctionInfo destructor checked all of the ~70 opcode slots of
OpcodeInstMap, but only the interesting opcodes are ever filled in.
Loop over those instead.

Instruction counts (callgrind) of attributor-light:
sqlite3 -0.02%, kimwitu++ k -0.30%, SPASS cnf -0.03%, consumer-typeset
z08 -0.01%.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
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+16-21 files

LLVM/project ddf367f — flang/include/flang/Lower/Support Utils.h, flang/lib/Lower PFTBuilder.cpp OpenACC.cpp

[flang][OpenACC] Bind a module COMMON block named in a data clause (#239811)

A COMMON block declared in a module and named in a data clause of a
module procedure crashes lowering when the procedure does not reference
any of the block's members:

```fortran
module m
  integer :: a
  common /c/ a
contains
  subroutine s()
    !$acc enter data create(/c/)
  end subroutine
end module
```

```
Assertion `detail::isPresent(Val) && "dyn_cast on a non-existent value"' failed.

    [64 lines not shown]
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+117-0flang/test/Lower/OpenACC/acc-module-common-unreferenced.f90
+7-19flang/lib/Lower/OpenACC.cpp
+18-0flang/lib/Lower/Support/Utils.cpp
+11-1flang/lib/Lower/PFTBuilder.cpp
+6-0flang/include/flang/Lower/Support/Utils.h
+159-205 files

LLVM/project 0eb53b9 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 shuffle-mask-emission.ll copyable-freeze.ll

[SLP]Support freeze as copyable main op

Model non-freeze lanes as freeze(V), which refines V, so mixed
bundles become a single vector freeze instead of a gather.

Assisted-by: Cursor

Original Pull Request: https://github.com/llvm/llvm-project/pull/239999

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/241009
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+24-110llvm/test/Transforms/SLPVectorizer/X86/copyable-freeze.ll
+50-25llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+3-6llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
+77-1413 files

LLVM/project b84ab9c — llvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU waitcnt-vavdst-ordered-xdl.mir

[AMDGPU] Model ordered XDL writes in expert scheduling (#218326)

Treat qualifying XDL WMMA as VA_VDST fences so expert scheduling can use
nonzero waits after out-of-order event mixes.

An XDL instruction with a destination register of 8 or more VGPRs
decrements VA_VDST after all instructions that were issued earlier.

This offers a significant benefit in compute bound kernels since we are
not required to pessimistically wait for WMMAs to write their results
when interleaving LDS.

```
VALU def r0
TRANS
VALU
TRANS
WMMA
va_vdst(1) # previously this would require va_vdst(0)
DS_LOAD use r0
```
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+162-8llvm/test/CodeGen/AMDGPU/waitcnt-vavdst-ordered-xdl.mir
+92-21llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+12-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+6-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+272-294 files

FreeBSD/ports 4691be5 — www/piwigo pkg-plist Makefile

www/piwigo: Update to 16.5.0.
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+3-3www/piwigo/distinfo
+2-2www/piwigo/Makefile
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+6-53 files

LLVM/project 384d653 — lldb/docs/use links.md

[lldb][docs] Add GPU debugging blog post to links page (#240930)

This Meta blog post is a great resource about the GPU/accelerator
debugging support in LLDB and lldb-server.
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LLVM/project 0cb1335 — llvm/lib/Target/AMDGPU GCNHazardRecognizer.cpp, llvm/test/CodeGen/AMDGPU fdiv.bf16.ll llvm.log2.bf16.ll

[AMDGPU] Mitigate TRANS f16 to partial VGPR write WAW hazard

Fixes: ROCM-33929
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+175-0llvm/test/CodeGen/AMDGPU/hazard-partial-trans-f16-write.mir
+113-0llvm/test/CodeGen/AMDGPU/hazard-partial-trans-f16-write-fake16.mir
+91-0llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+29-16llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
+24-13llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
+10-7llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
+442-365 files not shown
+455-4011 files

LLVM/project 7387a4d — clang/test/OffloadTools/clang-nvlink-wrapper thinlto-save-temps.c lto-save-temps.ll, clang/tools/clang-nvlink-wrapper ClangNVLinkWrapper.cpp

[clang-nvlink-wrapper] Keep LTO task outputs distinct (#238883)

With `--save-temps` and multiple LTO tasks, the wrapper reuses the same
PTX and cubin names, so later tasks overwrite earlier results and
`nvlink` receives duplicate inputs. Give each task a distinct output
name, serialize creation of shared temporary-file bookkeeping, and skip
inactive task slots.

Fixes #238882

Testing:
- Full LTO two-partition and single-partition `FileCheck` regressions;
Unified ThinLTO regression for the unused task slot.
- CUDA 13.2 `ptxas` and `nvlink`: successfully linked a two-kernel,
two-partition image for `sm_90` and `sm_103a` with `--save-temps`. The
unpatched current baseline fails with duplicate definitions.
- Loaded and ran both kernels on two GH200 GPUs and one B300 GPU;
results were 111 and 222 on each device.


    [10 lines not shown]
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+14-4clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
+10-0clang/test/OffloadTools/clang-nvlink-wrapper/thinlto-save-temps.c
+49-43 files