FreeBSD/ports f9c4099dns/dnsmasq Makefile distinfo, dns/dnsmasq/files patch-src_util.c update.py

dns/dnsmasq: update to v2.92 + inotify patch

Changelog:      https://lists.thekelleys.org.uk/pipermail/dnsmasq-discuss/2026q1/018380.html

We keep the local patch to enable inotify on FreeBSD 15,
which was only merged after the release but had been in this port
already.

Make it so the pkg-message is printed on new installs and upgrades.
DeltaFile
+0-73dns/dnsmasq/files/patch-src_util.c
+52-0dns/dnsmasq/files/update.py
+5-5dns/dnsmasq/Makefile
+3-3dns/dnsmasq/distinfo
+1-1dns/dnsmasq/files/pkg-message.in
+0-0dns/dnsmasq/files/simon-kelley-keyring.asc
+61-826 files

LLVM/project eaa7516llvm/lib/Target/X86 X86ISelLowering.cpp X86InstrSSE.td, llvm/test/CodeGen/X86 clmul.ll clmul-x86.ll

[X86] Lower scalar llvm.clmul intrinsics to PCLMULQDQ (#175189) (#175216)

Add support for lowering scalar llvm.clmul intrinsics (i8/i16/i32/i64)
to the PCLMULQDQ hardware instruction on X86 targets with the PCLMUL
feature, instead of using the default software expansion.

The lowering:

- Extends smaller types to the target's native width (i64 on x86-64, i32
on i686)
- Uses SCALAR_TO_VECTOR to create vectors (v2i64 on x86-64, v4i32 with
bitcast to v2i64 on i686)
- Performs X86ISD::PCLMULQDQ with immediate 0x00
- Extracts the result and truncates back to the original type

i8/i16/i32 CLMUL is enabled on both 32-bit and 64-bit targets. i64
CLMUL/CLMULH is only enabled on 64-bit targets.

Also adds ISD::CLMULH i64 support by extracting the upper element from

    [2 lines not shown]
DeltaFile
+215-0llvm/test/CodeGen/X86/clmul.ll
+58-0llvm/lib/Target/X86/X86ISelLowering.cpp
+11-13llvm/lib/Target/X86/X86InstrSSE.td
+18-0llvm/test/CodeGen/X86/clmul-x86.ll
+4-4llvm/lib/Target/X86/X86InstrAVX512.td
+3-0llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+309-172 files not shown
+315-178 files

FreeNAS/freenas 1c5735csrc/middlewared/middlewared/plugins/account_ constants.py privilege.py, src/middlewared/middlewared/utils privilege_constants.py

NAS-139304 / 26.04 / Convert ALLOWED_BUILTIN_GIDS to frozenset (#18023)

Correcting issues with #17894
The LocalAdminGroups included non-admin groups. Split those groups into
a separate enum class.
Renamed the class to more clearly indicate they are 'builtin' groups.
Changed the ALLOWED_BUILTIN_GIDS set to a frozenset and populate it with
the values of the new enum classes.

This passes all CI tests related to 'privilege' and manual targeted
testing.
DeltaFile
+10-10src/middlewared/middlewared/plugins/account_/constants.py
+9-5src/middlewared/middlewared/utils/privilege_constants.py
+3-3src/middlewared/middlewared/plugins/account_/privilege.py
+22-183 files

FreeNAS/freenas b472932src/middlewared/middlewared/plugins dlm.py

In local_reset start any stopped lockspace on a BlockingIOError
DeltaFile
+9-1src/middlewared/middlewared/plugins/dlm.py
+9-11 files

FreeNAS/freenas ad7ac8bsrc/middlewared/middlewared/plugins/iscsi_ alua.py scst.py

Add additional lun health checks to standby_after_start

- Ensure that all expected IQNs and LUNs are present
- Ensure that SCST deems the LUN healthy to add to copy manager
DeltaFile
+43-1src/middlewared/middlewared/plugins/iscsi_/alua.py
+14-0src/middlewared/middlewared/plugins/iscsi_/scst.py
+57-12 files

FreeNAS/freenas 488ae19src/middlewared/middlewared/plugins/iscsi_ fs_attachment_delegate.py extents.py

Improve ALUA handling with locked or disabled extents

Previously iscsi.target.active_targets did not return any targets
where any LUNs were either disabled or locked.  This prevented the
STANDBY node from offering these targets when ALUA was enabled.

Once this was rectified then improvements wrt LUN status change
were required for both disable/enable and lock/unlock.

To optimize handling of LUNs locking added an optional
do_reload parameter to iscsi.alua.removed_target_extent
DeltaFile
+117-1src/middlewared/middlewared/plugins/iscsi_/fs_attachment_delegate.py
+78-3src/middlewared/middlewared/plugins/iscsi_/extents.py
+53-19src/middlewared/middlewared/plugins/iscsi_/targets.py
+10-14src/middlewared/middlewared/plugins/iscsi_/target_to_extent.py
+5-2src/middlewared/middlewared/plugins/iscsi_/alua.py
+263-395 files

FreeNAS/freenas 8ba60dcsrc/middlewared/middlewared/plugins/iscsi_ alua.py, src/middlewared/middlewared/plugins/service_/services iscsitarget.py

Ensure standby_fix_cluster_mode does not run too soon

Ensure that we have reached a certain point in standby_after_start
before allowing standby_fix_cluster_mode to run.
DeltaFile
+11-1src/middlewared/middlewared/plugins/iscsi_/alua.py
+3-0src/middlewared/middlewared/plugins/service_/services/iscsitarget.py
+14-12 files

FreeNAS/freenas 824a893src/middlewared/middlewared/plugins/iscsi_ iscsi_global.py

Eliminate redundant reload of iscsitarget on STANDBY node

This code pre-dated the introduction of standby_after_start, etc
DeltaFile
+0-6src/middlewared/middlewared/plugins/iscsi_/iscsi_global.py
+0-61 files

FreeNAS/freenas cd632easrc/middlewared/middlewared/etc_files systemd.py

For HA systems do not use systemd to start scst

Instead it will be started by vrrp_master and if ALUA is enabled
vrrp_backup.  This allows finer control.
DeltaFile
+3-0src/middlewared/middlewared/etc_files/systemd.py
+3-01 files

FreeNAS/freenas 2a61254src/middlewared/middlewared/plugins/iscsi_ alua.py utils.py

Chunk the IO in set_all_cluster_mode
DeltaFile
+2-6src/middlewared/middlewared/plugins/iscsi_/alua.py
+7-0src/middlewared/middlewared/plugins/iscsi_/utils.py
+3-2src/middlewared/middlewared/plugins/iscsi_/scst.py
+12-83 files

FreeNAS/freenas 60eaac6src/middlewared/middlewared/plugins dlm.py, src/middlewared/middlewared/plugins/iscsi_ alua.py

Improve iscsi.alua.reset_active

Also call reset_active from standby_after_start
DeltaFile
+18-29src/middlewared/middlewared/plugins/iscsi_/alua.py
+7-0src/middlewared/middlewared/plugins/dlm.py
+25-292 files

LLVM/project fb0881fmlir/lib/Dialect/SCF/Transforms TileUsingInterface.cpp, mlir/lib/Dialect/Tensor/Transforms SwapExtractSliceWithProducerPatterns.cpp

[mlir][Tensor] Add rank-reducing slice in generatedSlices (#174248)

When `replaceExtractSliceWithTiledProducer `creates a rank-reducing
slice to handle type mismatches, it should be tracked in
`generatedSlices `so downstream cleanup patterns (like IREE's
FoldExtractSliceOfBroadcast) can process it.
 
This PR also fixes an infinite loop in getUntiledProducerFromSliceSource
where adding the slice to generatedSlices caused the fusion worklist to
repeatedly try to re-fuse producers already inside the innermost loop;
the fix skips producers that are already inside the innermost loop via
an isProperAncestor check.

Added a lit test (@fuse_through_rank_reducing_slice) demonstrating
correct fusion through rank-reducing slices. Note that demonstrating the
generatedSlices tracking benefit requires a cleanup pattern
(SwapExtractSliceWithFillPatterns) to consume the slice; IREE's full CI
suite (iree-org/iree#23012) validates this works correctly in practice
with patterns like FoldExtractSliceOfBroadcast.

    [3 lines not shown]
DeltaFile
+60-0mlir/test/Interfaces/TilingInterface/tile-and-fuse-using-interface.mlir
+12-1mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
+4-1mlir/test/Interfaces/TilingInterface/tile-and-fuse-with-reduction-tiling.mlir
+1-0mlir/lib/Dialect/Tensor/Transforms/SwapExtractSliceWithProducerPatterns.cpp
+77-24 files

LLVM/project a0b71b0lldb/source/Plugins/Language/CPlusPlus MsvcStlVariant.cpp, lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant TestDataFormatterStdVariant.py main.cpp

Revert "[LLDB] Fix MS STL `variant` with non-trivial types" (#176059)

Reverts llvm/llvm-project#171489 because it causes
`TestDataFormatterStdVariant.py` to fail on Darwin.

Affected bots:

- https://ci.swift.org/view/all/job/llvm.org/view/LLDB/job/as-lldb-cmake/
- https://ci.swift.org/view/all/job/llvm.org/view/LLDB/job/lldb-cmake/
DeltaFile
+0-21lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant/TestDataFormatterStdVariant.py
+5-11lldb/source/Plugins/Language/CPlusPlus/MsvcStlVariant.cpp
+0-5lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant/main.cpp
+5-373 files

LLVM/project 21b3642lldb/source/Plugins/SymbolFile/NativePDB PdbAstBuilderClang.cpp PdbAstBuilder.cpp, lldb/source/Plugins/TypeSystem/Clang TypeSystemClang.h

[LLDB][NativePDB] Introduce PdbAstBuilderClang (#175840)

This changes `PdbAstBuilder` to a language-neutral abstract interface
and moves all of its functionality to the `PdbAstBuilderClang` derived
class.

All Clang-specific methods with external callers are now public methods
on `PdbAstBuilderClang`. `TypeSystemClang` and `UdtRecordCompleter` use
`PdbAstBuilderClang` directly.

Did my best to clean up includes and unused methods.

RFC for context:

https://discourse.llvm.org/t/rfc-lldb-make-pdbastbuilder-language-agnostic/89117
DeltaFile
+1,547-0lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilderClang.cpp
+0-1,544lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
+182-0lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilderClang.h
+23-148lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.h
+7-1lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
+3-4lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.h
+1,762-1,6975 files not shown
+1,770-1,70711 files

FreeNAS/freenas ed2436btests/api2 test_300_nfs.py

Skip the NFS bindip test if no static IP is available.
DeltaFile
+10-0tests/api2/test_300_nfs.py
+10-01 files

LLVM/project 0f85aa1lldb/source/Plugins/Language/CPlusPlus MsvcStlVariant.cpp, lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant TestDataFormatterStdVariant.py main.cpp

Revert "[LLDB] Fix MS STL `variant` with non-trivial types (#171489)"

This reverts commit 9a632fd684e1729b93f9f5272ad6b5798f38ba77.
DeltaFile
+0-21lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant/TestDataFormatterStdVariant.py
+5-11lldb/source/Plugins/Language/CPlusPlus/MsvcStlVariant.cpp
+0-5lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/variant/main.cpp
+5-373 files

LLVM/project 1463fballvm/test/CodeGen/AMDGPU local-stack-alloc-add-references.gfx8.mir coalesce-copy-to-agpr-to-av-registers.mir, llvm/test/MC/Disassembler/AMDGPU gfx12_dasm_vop1_dpp8.txt

[AMDGPU] Allow allocation of lo128 registers from all banks

We can encode 16-bit operands in a short form for VGPRs [0..127].
When we have 1K registers available we can in fact allocate 4
times more from all 4 banks. That, however, requires an allocatable
class for these operands. When for most of the instructions it will
result in the VOP3 longer form, for V_FMAAMK/FMADAK_F16 it will
simply prohibit the encoding because these do not have VOP3 forms.

A straight forward solution would be to create a register class
with all registers having bit 8 of the encoding zero, i.e. to
create a register class with holes punched in it: [0-127, 256-383,
512-639, 768-895]. LLVM, however, does not like register classes
with punched holes when they also have subregisters. The cross-
product of all classes explodes and some combinations of a 'class
having a common subreg with another' becomeing impossible. Just
doing so explodes our register info to 4+Gb, uncompilable too.

The solution proposed is to define _lo128 RC with contigous 896

    [17 lines not shown]
DeltaFile
+180-180llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
+118-118llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
+90-90llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
+177-0llvm/test/CodeGen/AMDGPU/shrink-vgpr_lo128-gfx1250-t16.mir
+49-46llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
+94-0llvm/test/CodeGen/AMDGPU/regalloc-vgpr_lo128-gfx1250-t16.mir
+708-43440 files not shown
+1,340-73446 files

FreeNAS/freenas 42340cedebian/debian ix-reboot.service

NAS-139317 / 25.10.2 / Call ha_panic for ix-reboot.service as we do for ix-shutdown (by bmeagherix) (#18029)

Recently in PR #17833 the `ha_panic` script was added and called on
`ExecStop` in `ix-shutdown.service`.

This PR makes a similar change to `ix-reboot.service` for the same
rationale.

Original PR: https://github.com/truenas/middleware/pull/18028

Co-authored-by: Brian M <brian.meagher at ixsystems.com>
DeltaFile
+1-0debian/debian/ix-reboot.service
+1-01 files

FreeNAS/freenas 19e197adebian/debian ix-reboot.service

NAS-139317 / 26.04 / Call ha_panic for ix-reboot.service as we do for ix-shutdown (#18028)

DeltaFile
+1-0debian/debian/ix-reboot.service
+1-01 files

LLVM/project f1821a5clang/include/clang/Options Options.td, llvm/docs MemProf.rst

[docs][MemProf]Update compiler options for static data partitioning (#175872)

https://github.com/llvm/llvm-project/pull/124991 introduces a Clang
option for static data partitioning. Update the LLVM option with the
Clang option and some notes on how data hotness is inferred from
profiles.
DeltaFile
+16-5llvm/docs/MemProf.rst
+1-1clang/include/clang/Options/Options.td
+17-62 files

FreeNAS/freenas c5ddd8fdebian/debian ix-reboot.service

Call ha_panic for ix-reboot.service as we do for ix-shutdown
DeltaFile
+1-0debian/debian/ix-reboot.service
+1-01 files

LLVM/project 782bf6allvm/lib/Target/X86 X86ISelLoweringCall.cpp X86ISelLowering.h, llvm/test/CodeGen/X86 musttail-struct.ll musttail-tailcc.ll

x86: fix musttail sibcall miscompilation (#168956)

fixes https://github.com/llvm/llvm-project/issues/56891
fixes https://github.com/llvm/llvm-project/issues/72390
fixes https://github.com/llvm/llvm-project/issues/147813

Currently the x86 backend miscompiles straightforward tail calls when
the stack is used for argument passing. This program segfaults on any
optimization level:

https://godbolt.org/z/5xr99jr4v

```c
typedef struct {
    uint64_t x;
    uint64_t y;
    uint64_t z;
} S;


    [41 lines not shown]
DeltaFile
+320-0llvm/test/CodeGen/X86/musttail-struct.ll
+154-34llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+0-18llvm/test/CodeGen/X86/musttail-tailcc.ll
+16-0llvm/lib/Target/X86/X86ISelLowering.h
+7-2llvm/test/CodeGen/X86/sibcall.ll
+2-4llvm/test/CodeGen/X86/swifttailcc-store-ret-address-aliasing-stack-slot.ll
+499-583 files not shown
+502-649 files

LLVM/project 44b691autils/bazel/llvm-project-overlay/clang BUILD.bazel

[bazel] Update for #175873 (BuiltinsAMDGPU)
DeltaFile
+9-0utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+9-01 files

OpenZFS/src 3fffe4emodule Makefile.in

Fix --enable-invariants on FreeBSD

The make symbols were never getting forwarded to the correct make
subprocess.  As far as I can tell, this has never worked.  Either that,
or something has changed in the behavior of make.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Signed-off-by: Alan Somers <asomers at gmail.com>
Closes #18131
DeltaFile
+3-2module/Makefile.in
+3-21 files

OpenZFS/src 09e4e01module/zfs zfs_ioctl.c, tests/zfs-tests/tests/functional/cli_root/zpool_create zpool_create_tempname.ksh

Fix history logging for `zpool create -t`

`zpool create` is supposed to log the command to the new pool’s history,
as a special record that never gets evicted from the ring buffer. but
when you create a pool with `zpool create -t`, no such record is ever
logged (#18102). that bug may be the cause of issues like #16408.

`zpool create -t` (83e9986f6eefdf0afc387f06407087bba3ead4e9) and `zpool
import -t` (26b42f3f9d03f85cc7966dc2fe4dfe9216601b0e) are both designed
to override the on-disk zpool property `name` with an in-core
“temporary” name, but they work somewhat differently under the hood.

importing with a temporary name sets `spa->spa_import_flags |=
ZFS_IMPORT_TEMP_NAME` in ZFS_IOC_POOL_IMPORT, which tells
spa_write_cachefile() and spa_config_generate() to use the
ZPOOL_CONFIG_POOL_NAME in `spa->spa_config` instead of `spa->spa_name`.

creating with a temporary name permanently(!) sets the internal zpool
property `tname` (ZPOOL_PROP_TNAME) in the `zc->zc_nvlist_src` of

    [17 lines not shown]
DeltaFile
+8-2module/zfs/zfs_ioctl.c
+2-0tests/zfs-tests/tests/functional/cli_root/zpool_create/zpool_create_tempname.ksh
+10-22 files

LLVM/project 8ac6c4aclang/test/Frontend rewrite-includes-bom.c

[Clang] Fix rewrite-includes-bom.c to use POSIX-compliant regex (#176043)

As `\s` is a GNU extension, it is not supported by the system grep on
AIX and thus fails in the
[buildbot](https://lab.llvm.org/buildbot/#/builders/64/builds/6835):

```
******************** TEST 'Clang :: Frontend/rewrite-includes-bom.c' FAILED ********************
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
cat /home/llvm/llvm-external-buildbots/workers/aix-ppc64/clang-ppc64-aix/llvm-project/clang/test/Frontend/Inputs/rewrite-includes-bom.h | od -t x1 | grep -q 'ef\s*bb\s*bf'
# executed command: cat /home/llvm/llvm-external-buildbots/workers/aix-ppc64/clang-ppc64-aix/llvm-project/clang/test/Frontend/Inputs/rewrite-includes-bom.h
# executed command: od -t x1
# executed command: grep -q 'ef\s*bb\s*bf'
# note: command had no output on stdout or stderr
# error: command failed with exit status: 1
--

    [6 lines not shown]
DeltaFile
+2-2clang/test/Frontend/rewrite-includes-bom.c
+2-21 files

LLVM/project 95a1581llvm/include/llvm/CodeGen TargetLowering.h

[CodeGen] Remove legacy getTgtMemIntrinsic overload

It is now fully unused.

commit-id:028dd72d
DeltaFile
+1-19llvm/include/llvm/CodeGen/TargetLowering.h
+1-191 files

LLVM/project 4fbc3c6llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU waitcnt-unscoped.ll llvm.amdgcn.load.to.lds.ll

[AMDGPU] Return two MMOs for load-to-lds and store-from-lds intrinsics

Accurately represent both the load and the store part of those
intrinsics.

The test changes seem to be mostly fairly insignificant changes caused by
subtly different scheduler behavior.

commit-id:0269189c
DeltaFile
+61-51llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-4llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll
+2-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
+2-4llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
+68-634 files

LLVM/project 1c445d8llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/lib/Target/AMDGPU SIISelLowering.cpp

[CodeGen] Refactor targets to override the new getTgtMemIntrinsic overload (NFC)

This is a fairly mechanical change. Instead of returning true/false,
we either keep the Infos vector empty or push one entry.

commit-id:c7770af6
DeltaFile
+99-53llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+78-59llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+40-21llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+36-22llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+36-22llvm/lib/Target/ARM/ARMISelLowering.cpp
+26-18llvm/lib/Target/X86/X86ISelLowering.cpp
+315-19516 files not shown
+397-26822 files

LLVM/project 09515b2llvm/include/llvm/CodeGen SelectionDAGNodes.h TargetLowering.h, llvm/lib/CodeGen/GlobalISel IRTranslator.cpp

[CodeGen] Add getTgtMemIntrinsic overload for multiple memory operands (NFC)

There are target intrinsics that logically require two MMOs, such as
llvm.amdgcn.global.load.lds, which is a copy from global memory to LDS,
so there's both a load and a store to different addresses.

Add an overload of getTgtMemIntrinsic that produces intrinsic info in a
vector, and implement it in terms of the existing (now protected)
overload.

GlobalISel and SelectionDAG paths are updated to support multiple MMOs.
The main part of this change is supporting multiple MMOs in
MemIntrinsicNodes.

Converting the backends to using the new overload is a fairly mechanical step
that is done in a separate change in the hope that that allows reducing merging
pains during review and for downstreams. A later change will then enable
using multiple MMOs in AMDGPU.

commit-id:b4a924aa
DeltaFile
+83-32llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+64-25llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+38-29llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+19-28llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+20-3llvm/include/llvm/CodeGen/TargetLowering.h
+17-3llvm/include/llvm/CodeGen/SelectionDAG.h
+241-1203 files not shown
+246-1239 files