dpaa/dtsec: advertise RX/TX csum
Apply 6464974 to dTSEC, since it supports the same offload capabilities
as mEMAC.
The DPAA_CSUM_TX_OFFLOAD macro moves from if_memac.c to the shared
dpaa_eth.h since both drivers now reference it.
drm/xe: Don't hand out the flat CCS storage as usable VRAM
get_flat_ccs_offset() reads the base of the flat CCS storage from the
hardware, scales it by the number of enabled L3 nodes, and rounds the
result up to 128K. Everything below that offset is then handed to the
VRAM allocator as usable memory.
Rounding a limit that means "usable memory ends here" upwards publishes
whatever lies between the real base and the rounded one as free memory,
and that memory belongs to the compression hardware. The scaled value
has no reason to be 128K aligned, and on a Battlemage G21 with 16 GiB it
is not:
flat CCS base: raw 0x3fafff800, rounded 0x3fb000000
so the last 2 KiB of page 0x3fafff000 is CCS storage, in the allocator's
pool. Whatever is allocated there gets that tail overwritten by the
compression hardware, which needs no page-table entry, no buffer object
and no GPU submission to do it, and does it before userspace exists.
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Merge tag 'mm-hotfixes-stable-2026-08-19-21-33' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
Pull hotfixes from Andrew Morton:
"8 hotfixes. 5 are cc:stable. 5 are for MM.
All are singletons, please see their changelogs for details"
* tag 'mm-hotfixes-stable-2026-08-19-21-33' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm:
mm/pagewalk: fix stale walk->action escaping walk_pmd_range()
mm, swap: don't free a hibernation slot that is in the swap cache
mm: memcg-v1: fix memsw and TCP failcnt accounting
mm/vmscan: report RCU-tasks quiescent states in shrink_lruvec()
mailmap: add entries for Guodong Xu
MAINTAINERS, mailmap: update email address for JP Kobryn
MAINTAINERS: remove git URL for Squashfs
memcg: keep folio's objcg same as its node
[CHERI][RISCV][MC] Add shared support for aligning globals to an "alignment granule", which is applied to both the alignment and the allocated size. (#203872)
On CHERI targets, bounds are generally stored in a compressed format
which imposes alignment requirements based on allocation size. When
emitting globals, we need to align and tail-pad them as appropriate to
ensure that the pointer to the global will have bounds that are precise,
i.e. not covering any non-padding bytes that either precede or follow
While this patch adds the plumbing necessary to support this feature on
arbitrary targets, it only concretely implements it for RISCV Y-base and
XCheriot. Support for other targets (such as AArch64/MTE and
AArch64/Morello) is left as future work here.
Based on https://github.com/llvm/llvm-project/pull/121957
Co-authored-by: Florian Mayer <fmayer at google.com>
Co-authored-by: Florian Mayer <fmayer at google.com>
DPAA: Minor performance improvements
* Add interrupt coalescing for DQRR and MR, with thresholds and period
as tunable sysctls under the `hw.qman` tree.
* Do lazy/sloppy buffer management to avoid constantly checking
thresholds via QMan portal round-trips.
* Add cache stashing to prewarm caches, reducing latency.
* Fix the definition of Context_A in the init_fq MC command/result
structures, they're 64-bit fields, not 32-bit.
* Reorder the dpaa_eth_frame_info as a bit of cleanup.
* Take advantage of the fact that UMA small allocations are returned in
the DMAP, and avoid pmap_kextract().
These changes together improve throughput by ~1.5%
(925Mbps->935-940Mbps) consistently, and reduce CPU usage by a bit,
increasing idle CPU from 30%->35% minimum.
fman: Fix duplicate port identifiers
fman_qman_channel_id returns the QMan FMan channel for a given port.
If a port isn't found, the wrong channel number will be returned.
sdhci_fsl_fdt: Add support for PowerPC eSDHC controllers
Migrate all PowerPC QorIQ to the sdhci_fsl_fdt SDHC driver. There are a
few differences that need to be accounted for:
* On PowerPC device trees, the `clock-frequency` property defines the
clock rate, not a `clocks` reference property.
* On some older SoCs (P1022 only?) the BURST fields of the WML register
are reserved, and must be 0x10, so add a FSL quirk (errata field) to
account for this.
* The PowerPC eSDHC controllers must have the DMA SNOOP bit set for DMA
to work properly and avoid corruption.
As part of this, make the fallback "fsl,esdhc" compat data work for
PowerPC. If these fallbacks are not compatible with ARM SoCs, newer
compat strings could be added for those, but the conservative catch-all
should work for most SoCs, though perhaps less optimal.
Differential Revision: https://reviews.freebsd.org/D58630
powerpc/dma: Fix accounting and loading large segments
When the first page of a segment fits alignment, the second likely does
not, so the DMA infrastructure (must_bounce()) thinks it needs to bounce
the pages. Fix this by passing the previous end (address of byte
following the previous segment) as a third argument to must_bounce(), so
that the alignment check is done against the start of a new segment if
and only if necessary, instead of the current page.
Reviewed by: adrian
Differential Revision: https://reviews.freebsd.org/D58627
sdhci_fsl_fdt: Allow setting extra quirks
Respect the `hw.sdhci.quirk_set` and `hw.sdhci.quirk_clear` tunables in
the QorIQ eSDHC driver. This lets us tweak quirks for debugging or
platform specifics.
Allocate TLS 1.3 receive buffers lazily
The receive buffer is not used for records created for sending. Avoid
allocating a maximum-sized buffer in tls13_record_new() and instead
allocate a header-sized buffer when tls13_record_recv() is first called.
The buffer will grow as needed once the record length is known.
This avoids an unnecessary allocation for outgoing records and reduces
the initial allocation size for incoming records.
ok tb jsing
tailscale: update to 1.102.3
- Tailscale refuses host-scoped IPv4 destinations at every point that
acts on an unmapped 4via6 address. This fix addresses a security
vulnerability described in TS-2026-011.
- When MagicDNS is disabled, unqualified hostnames are correctly
forwarded to the configured nameservers.
- Resolved an issue where nodes with Tailnet Lock enabled on large
tailnets would experience startup failures.
