[bazel] Make CAPIIR depend on TransformsPassIncGen (#174902)
CAPIIR includes this in some of its source files, so we need to ensure
the header is around.
[RISCV] Fold (fma (splat (fneg X)), Y, Z) -> (fma (fneg (splat X)), Y, Z) (#173808)
We use fli+fneg to generate negative float, eliminate the fneg for fma.
Fold fma to vfnmsac.vf,vfnmsub.vf, vfnmacc.vf, vfnmadd.vf
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
[SPIRV] Handle aggregate arguments to `spv_store` (#172348)
This patch handles the special case where an extract value yields an
aggregate result, which then is used as an argument to a store. The
SPIRV BE uses special intrinsics (`spv_extractv` and `spv_store`) to
represent these through IRTranslator, however this creates a problem:
`spv_store` is called as a function, and IRTranslator cannot handle
arguments that take more than a vreg. For other functions, the aggregate
argument replacement pass would have solved things, but it does not
apply here. Hence, we apply the same mutate-into-Int32 solution here
when dealing with stores, and restore the extract value's type (which we
have available as a ValueAttr) during instruction selection.
avoid small reads when there's a preferred IO size.
a discussion on port-sparc here:
https://mail-index.netbsd.org/port-sparc/2025/12/29/msg003063.html
showed that the "file type" 4-byte read was failing on tape devices
as they need a specific IO size to work.
since we already pass this 4 bytes to the real decompressor, avoid this
problem by checking if there's a st_blksize value from stat(2) and use
a buffer of that size for the first read.
rename handle_stdin() to handle_fd_decomp() and use the same backend
for stdin as well as readable non-file files (device, fifo, socket).
tested by Nobuyoshi SATO on port-sparc, atf, and a few other manual
things.
[WebAssembly] Fold constant `i8x16.swizzle` and `i8x16.relaxed.swizzle` to `shufflevector` (#169110)
Resolves #169058.
This adds ~~an InstCombine pass~~ a TTI hook to the WebAssembly backend
that folds `i8x16.swizzle` and `i8x16.relaxed.swizzle` operations to
`shufflevector` operations if their mask operands are constant.
This is mainly useful for abstractions over the raw intrinsics--for
instance, in architecture-generic SIMD code that may not be able to
expose the constant shuffles due to type system limitations.
I took most of this from the x86 backend (in particular,
`simplifyX86vpermilvar` in `X86InstCombineIntrinsic`), and adapted it
for the WebAssembly backend. There wasn't any previous
`instCombineIntrinsic` method on the WebAssembly `TargetTransformInfo`,
so I added it. Right now, this swizzle optimization is the only one it
performs.
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[mlir][vector] Emit error when `kind` attribute is not a CombiningKind (#173659)
This PR fixes a crash by validating the type of the `kind` attribute.
For `vector.contract` and `vector.outerproduct`, the verifier now emits
an error when `kind` is not a CombiningKindAttr. Fixes #173555.
[RISC-V] Ensure MCTargetStreamer is initialized. (#174800)
Fixes a failure on llc for ubsan builds:
../lib/Target/RISCV/RISCVAsmPrinter.cpp:552:7: runtime error: downcast
of null pointer of type 'RISCVTargetStreamer'
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior
../lib/Target/RISCV/RISCVAsmPrinter.cpp:552:7
[flang] Make fir.result Pure operation. (#173508)
This allows speculating recursively speculatable operations
containing `fir.result`. Note that making it Pure does not allow
speculating `fir.result` itself from its containing operation,
since it is a terminator.
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
This commit adds support for family specific support for the following
intrinsics:
- ldmatrix
- stmatrix
- mma.block_scale, mma.sp.block_scale
- redux.sync
- cvt.rs
- clusterlaunchcontrol
- setmaxnreg
- tcgen05.mma
Removed `hasTcgen05Instructions` function in the favour of `hasTcgen05InstSupport` Updated wmma.py script with family specific support and added new tests
NAS-139212 / 26.04 / use statx provided by truenas_pyos (#17972)
This commit removes the ctypes definition for statx and replaces with
the implemntatoin from truenas_pyos (cpython).
[Clang][DebugInfo] Add a flag to use expansion loc for macro params.
This patch adds a flag to allow users to preserve the old behaviour - use the macro expansion location for parameters. This is useful for wider testing of sample profile driven PGO which relies on debug information based mapping.
remove __packed from a bunch of ioctl structures.
i noticed a warning unrelated to an evbarm llvm build failure here, and
it turns out that we have a few things using __packed that should be
using the right types instead, or don't need __packed at all.
struct netbsd32_if_data and struct netbsd32_ksyms_gvalue use
netbsd32_uint64 now, to avoid forcing the whole-struct alignment to 8.
struct netbsd32_ifdatareq, struct netbsd32_dkwedge_list, and
struct netbsd32_disk_strategy don't need __packed at all.
structure sizes confirmed to remain the same on amd64.
[LLDB] Tentative fix for lldb-arm-ubuntu buildbot. (#174893)
Not sure if this will fix the problem because I don't have a 32-bit arm
machine to test with.
[WebAssembly] Expand vector frem instructions
Commit 6ad41bc changed how frem is expanded during legalization and it
broke WebAssembly but we were missing test coverage. We want to maintain
our previous behavior of unrolling vectors and using a libcall to
implement scalar frem. I'm not sure why this now has to be different
(in ISelLowering) from other libcalls like fsin which work the same way
in the end, but this code does accurately describe what we want.
Fixes: https://github.com/emscripten-core/emscripten/issues/25991
[WebAssembly] Disable explicit-locals in the libcalls.ll test. NFC (#174811)
The keep-registers mode isn't super useful without disabling
explicit-locals,
as the local gets/sets are irrelevant noise in most cases.
Switching this test makes the output much more concise and will make
upcoming
changes easier to review.
