[Flang][NFC] Remove FOR_EACH_*_KIND macros (#238748)
Third cleanup after #216960
The `FOR_EACH_*_KIND` macros only expand to a single item. In cases
where this was already the case before #216960, such as `SomeDerived`,
it was spelled out without a macro. Do the same for `FOR_EACH_*_KIND` .
[mlir][ToLLVM] Fix dead FileCheck in func-to-llvm-datalayout.mlir (NFC) (#238964)
The RUN line did not pipe into FileCheck, so none of the CHECK lines
were evaluated. Add the missing FileCheck and update the CHECK lines to
the current printer output (compact `dl_spec` syntax, no argument names
for private function declarations).
Found while looking into the static mode of `convert-to-llvm`, which
ignores `dlti.dl_spec`. Its test coverage is intentionally not extended
here: per the discussion in #156557, the static mode is a candidate for
removal rather than a fix. The open question is whether `dynamic=true`
should become the default.
Co-authored-by: Sven Lukas <sven.lukas at gmail.com>
[bazel][lldb] Port eeb24ee48aa2: Add PluginRegisterCore (#239177)
Fixes the Bazel build after eeb24ee48aa2 ([lldb] Extract reusable core
register contexts (#237442)), which moved the core register contexts to
lldb/source/Plugins/Register/Core.
[DebugInfo] Escape strings echoed into .debug_str comments (#223384)
Since 1a23bca645dc, `DwarfStringPool::emit` echoes each string into the
assembler comment next to its bytes. Strings can contain arbitrary
bytes, e.g. non-ASCII identifiers, and some assemblers reject those even
inside comments: `ptxas` (before CUDA 13.1) aborts with "Unexpected
non-ASCII character encountered" (JuliaGPU/CUDA.jl#3274). Escape the
string, as is already done when it is emitted as a quoted `.asciz`
directive.
Building the escaped comment is no longer free like the lazy `Twine` it
replaces, so only do it for verbose assembly output.
Get RegisterClassInfo from MachineRegisterClassInfoWrapperPass
Use the shared analysis instead of computing a private RegisterClassInfo, and
update its reserved registers after freezeReservedRegs(), as RegAllocBase does.
Assisted-by: Claude Opus 5.5
[libc++] Allow the compiler to reorder computation in reduction loops (#237918)
This PR allows Clang to vectorize and interleave loops in the reduction
algorithms: `std::reduce` and `std::transform_reduce`.
This is permitted by
https://eel.is/c++draft/numerics.defns#lib:GENERALIZED_SUM.
Currently it's enabled only for Clang, it's unclear if GCC has a direct
equivalent.
A new macro `_LIBCPP_ENABLE_LOOP_VECTORIZATION` is tentatively placed in
`__configuration/attributes.h`, though it's not an attribute per-se.
Ideally we might want to refactor `__configuration/pstl.h` to be less
PSTL-specific and put the new macro there instead.
Part of #234887
[mlir][NFC] Remove includes provided by generated declarations and definitions (#238848)
#236155 and #238735 made the generated declarations and definitions of
ops, attributes, types and interfaces include the core MLIR headers they
require. Includes that headers and source files only had for the
generated code are therefore redundant. This removes them in MLIR, Flang
and ClangIR.
Includes of headers that the hand-written code uses directly are kept,
even when the generated code includes them as well.
---------
Co-authored-by: Claude <noreply at anthropic.com>
elf: do not read past the note section data
The loop copied a note header while any byte was left, so a last note
followed by padding shorter than a header made it read past the section.
The ABI descriptor was then read without checking that it fits, and the
name was compared with strcmp() although it is not necessarily
terminated.
Only read a whole header, check that the name and the descriptor fit
before using them, compare the name with the length the note declares,
and advance with the per field padding the format defines.
[AMDGPU][NewInsertWaitcnt] Event Tracker (2/2)
See #226970 for context and history regarding this patch.
This is intended to begin review as a 1-1 equivalent of #226970 with only one change: a "Drain"
test that Claude added and I found useful, so I left it in.
Builds upon the previous patch to include the functionality needed to import
events from predecessor basic blocks into a basic block, so a MBB can be aware of
previous state.
This adds the "age" system, which is necessary to preserve chronology across control-flow edges,
especially in asymmetrical diamonds, alongside a way to import predecessor state via a `enterBlock`
function.
Assisted-by: AI Coding Assistants for basic boilerplate/research/etc. - no logic was written by LLMs except some unit tests.
[LLVM] Use CreatePtrAddFrom(Signed|Unsigned)Offset helpers more (#239153)
Both to simplify code and make sure that the correct offset type
is always used (some places were hardcoding 64 or 32 bits, which
may not match the pointer index type).
arti: update to 2.8.0.
# Arti 2.8.0 — 3 November 2026
Arti 2.8.0 continues our steady progress on relay and directory authority development,
including on computing the consensus from votes,
bootstrapping router descriptors and microdescriptors,
as well as relay bandwidth rate-limiting,
descriptor encoding, and the relay DNS cache implementation.
Additionally, we have made a number of cleanups and
clarifications to the Tor specification.
This release has a number of security fixes; please see below.
As usual, there are also many under-the-hood improvements and bug fixes,
which are documented below.
### Security fixes
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[NVPTX] Support native 128-bit atomic load + store (#236423)
Lower i128 atomic loads and stores to ld/st.b128 on SM 70 and newer with
PTX 8.3, instead of emulating them with compare-and-swap or exchange.
Split values into pairs of i64 operands and preserve the memory ordering
and scope so instruction selection inserts the required fences.
Add coverage for i128 and fp128 loads and stores, including memory
ordering, address spaces, volatile accesses, and unsupported targets.
Update scalar and elementwise atomic CAS loop checks to use 128-bit
loads.
Assisted by: Codex
---------
Co-authored-by: Akshay Deodhar <adeodhar at nvidia.com>
