[AMDGPU] Fix codesize estimate after #198005 (#200033)
This fixes failure in libc tests which checks the exact encoding
size. Encoding is now shorter, but it did not recognize fp16
immediates as an inlinable constant and assumes literal encoding.
Shorter encodings were created here:
https://github.com/llvm/llvm-project/pull/198005
[llvm-profgen] Fix -Wunused-variable (#200038)
Inline the variable definition into the assertion given the variable
name does not add much and release builds will end up with an unused
variable otherwise.
[Support] Add MemoryBuffer::randomAccessIfMmap() (#199265)
For read-only MemoryBuffer_MMap, advise the kernel that access pattern
will be random, disabling readahead. This calls `madvise(MADV_RANDOM)`
on *NIX. This function should not be called on a writable buffer.
The implementation follows existing pattern in
`mapped_file_region::dontNeedImpl()` and
`mapped_file_region::willNeedImpl()`.
See intended usage: https://github.com/llvm/llvm-project/pull/199230
[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs
These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.
Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
[AMDGPU] Implement CFI for non-kernel functions
This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.
Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Implement CFI for CSR spills
Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.
Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.
Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Emit entry function Dwarf CFI
Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.
Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU
While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).
Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
[MIR] Error on signed integer in getUnsigned
Previously we effectively took the absolute value of the APSInt, instead
diagnose the unexpected negative value.
Change-Id: I4efe961e7b29fdf1d5f97df12f8139aac12c9219
[Clang] Default to async unwind tables for amdgcn
To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.
There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.
Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
[AMDGPU] Implement CFI for CSR spills (#183150)
Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.
Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.
Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Fix codesize estimate after #198005
This fixes failure in libc tests which checks the exact encoding
size. Encoding is now shorter, but it did not recognize fp16
immediates as an inlinable constant and assumes literal encoding.
Shorter encodings were created here:
https://github.com/llvm/llvm-project/pull/198005
NAS-141142 / 26.0.0-RC.1 / VM/container: parallelize shutdown and fix force_after_timeout (by Qubad786) (#19025)
## Problem
When middleware itself stops VMs and containers — on system
shutdown/reboot via the `system.shutdown` event, or during HA failover —
it loops through guests one at a time, waiting up to the per-guest
shutdown timeout (90s by default) for each. With many guests this
serializes into a long wait, even though stopping different guests has
no dependency on one another.
Separately, `vm.stop(force_after_timeout=True)` was silently ignored —
`stop_vm` only checked `options.force`. A VM that didn't respond to ACPI
within its `shutdown_timeout` was left running, contradicting the API
docstring and behaving inconsistently with the container path which
honored the flag correctly.
## Solution
[12 lines not shown]
Add window-pane-status-format options and adjust the default second
status line to show panes, also change how window-style is checked now
it is a pane option.
