[dyndbg][LLD][ELF] Add dynamic debugging support for `--wrap=<symbol>` (#222990)
* Forward the `--wrap=<symbol>` arguments to the "inner" relocatable
link.
* In the "outer" main link, set the `isDynDbgRef` flag appropriately for
the symbols involved.
[AMDGPU] Recognize workitem.id.x as the lane ID in isThreadID
The matchers for wave shuffles use `isThreadID`, which only recognized
the mbcnt()-based form. However,
1) This gets canonicalized to workitem-id-based checks in some cases
and
2) Masking the workitem ID (when we know it changes between waves at a
power of 2) is a valid and typical way to express the lane ID.
Therefore, amend isThreadID to catch these forms of lane ID.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
[AMDGPU][NFC] Add lane-index-from-workitem.id.x tests for wave shuffles (#231234)
mbcnt()-based lane IDs are sometimes rewritten to workitem ID-based
ones, precommit tests for this.
AI disclosure: Claude wrote these tests, I wrote the commit message
and renamed the tests / trimmed down comments
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
[AArch64] Support FP atomic stores with memory hints
This patch extends the atomic-store-hint pseudos to accept preserved
floating-point atomic stores. It adds an FPR16 pseudo family and direct
half, bfloat, float, and double patterns for the supported addressing
modes.
The pseudos expand relaxed stores to STR and RCPC3 release stores to
STLUR, retaining memory hints without cross-register-bank copies.
[AArch64] Support direct RCPC3 FP atomic loads and stores
This patch preserves half, bfloat, float, and double atomic loads and
stores through AtomicExpand for acquire and release orderings when RCPC3
and NEON are available.
It adds SelectionDAG patterns for the RCPC3 LDAPUR and STLUR operations,
including unscaled offsets, and updates the existing FP lane patterns to
match the preserved floating-point atomic nodes. Targets without the
required features continue to use integer lowering.
[AArch64] Support direct relaxed FP atomic loads and stores
This patch preserves half, bfloat, float, and double atomic loads and
stores through AtomicExpand when they use unordered or monotonic
ordering and the target supports floating point.
It adds SelectionDAG patterns that select the accesses directly in the
floating-point register bank. Unsupported targets, stronger orderings,
and stores carrying memory hints continue to use integer lowering.
NAS-144299 / 27.0.0 / Use cached `tn_connect.hostname.details` to render WebShare config file (by themylogin) (#20003)
Changes to TN Connect plugin left the webshare TN hostname cache behind.
It uses stale cache item that is now not updated.
Let's move that cache to TN Connect plugin to prevent things like this
from happening in the future.
Original PR: https://github.com/truenas/middleware/pull/19995
Co-authored-by: themylogin <themylogin at gmail.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
*/*: Rename KDE_APPLICATIONS6_SHLIB_VER to KDE_PIM6_SHLIB_VER to avoid confusion
Although KDE PIM uses Gear version for tarballs, it still uses
internal PIM version for its own libraries.
(cherry picked from commit 7f34c9f8832d6032af5d41e0e89f66957deb0cbc)
