[lldb][windows] recommend building with Python 3.11 (#191159)
As of https://github.com/llvm/llvm-project/pull/176387 and release 22,
official builds of lldb on Windows use Python 3.11 both on x64 and
arm64.
The Windows lldb build bots use 3.11+ versions of Python:
[lldb-x86_64-win](https://lab.llvm.org/buildbot/#/builders/211) -
`3.12.7`
[lldb-remote-linux-win](https://lab.llvm.org/buildbot/#/builders/197) -
`3.12.7`
[lldb-aarch64-windows](https://lab.llvm.org/buildbot/#/builders/141) -
`3.11.9`
This patch changes the cmake config and documentation to recommend
building lldb on Windows with Python 3.11 or more recent.
In the future, given the reduced number of lldb maintainers on Windows
compared to other platforms, bumping the Python version on Windows would
help reduce the surface area of Python related bugs.
[AMDGPU] Fix .Lfunc_end label placement (#191526)
Now it is placed after the kernel descriptor, even the section is
.rodata, which is wrong. This allows proper code size calculation in MC.
[clang][modules] Don't prune the top level module cache for implicitly built modules (#192171)
There are build systems that put explicitly built modules in the same
module cache directory as implicitly built modules. Pruning those in an
implicit build can cause the build to fail due to missing modules.
rdar://174790709
[MachineScheduler] Improve handling of phys regs in GenericScheduler. (NFC). (#187572)
Factor out the handling of coalesced preg COPYs from SystemZMachineScheduler.cpp into MachineScheduler.cpp.
This extends the handling to other types of instructions than COPYs or immediate
loads, such as Load Address and takes care of maintaining the original input
order if both SUs are biased the same way in the same zone.
Another target that uses GenericScheduler can enable this by setting the new
MachineSchedPolicy member BiasPRegsExtra to true (default false). In a derived
scheduling strategy, this could be used either by passing /*BiasPRegsExtra=*/true
to biasPhysReg() (extra instruction detection), or by calling tryBiasPhysRegs()
instead which also preserves the original order if biased the same way.
[llvm-otool] Add -a option to print archive headers (#189411)
Wire up llvm-otool's -a to the existing --archive-headers machinery with
a default of displaying all architectures to match classic otool
behaviour.
NAS-140621 / 26.0.0-BETA.2 / Delete containers when pool is exported with cascade (by Qubad786) (#18746)
## Problem
During pool export with cascade=true, containers are not removed from
the database via the
attachment delegate. As a result, container records persist even when
cascade implies that all related attachments must be removed, leading to
stale and inconsistent state.
## Solution
Updated container attachment delegate to make sure that when pool is
being exported with config that related attachments are to be deleted,
we actually delete them.
Original PR: https://github.com/truenas/middleware/pull/18745
Co-authored-by: M. Rehan <mrehanlm93 at gmail.com>
15876 NFS v4.1 server delegations
16390 BACKCHANNEL op implementation.
Portions contributed by: Gordon Ross <gordon.w.ross at gmail.com>
Reviewed by: Toomas Soome <tsoome at me.com>
Reviewed by: Cedric Blancher <cedric.blancher at gmail.com>
Reviewed by: Dan Shelton <dan.f.shelton at gmail.com>
Approved by: Robert Mustacchi <rm at fingolfin.org>
[lldb][windows] use a marker to drain the ConPTY's init sequence (#191472)
This patch improves the ConPTY method that drains the init sequence. It
uses a string marker to ensure that the init sequence has been received.
The previous implementation was prone to race condition, because the
method could return before all the init sequence was received.
This only seems to reproduce on windows-server-2019.
[InstCombine] Generalize zext(add X, -C) + C folding (#191723)
This patch generalizes an existing InstCombine optimization:
zext(X - 1) + 1 → zext(X)
to support arbitrary constants C:
zext(X - C) + C → zext(X)
when X is known to be >= C using KnownBits analysis.
This avoids missed simplifications for non-unit constants while ensuring
correctness under wrap semantics.
Includes test coverage for:
- Positive case where the fold applies
- Negative case where the fold must not apply
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[AMDGPU][Scheduler] Fix non-monotonic SlotIndex after schedule revert (#192039)
modifyRegionSchedule restores the original instruction order by splicing
MIs before RegionEnd. When an MI is already at the expected position
(MII == RegionEnd) its SlotIndex was left unchanged, even though earlier
splices may have shifted neighboring indices. This could leave a stale,
lower-numbered slot on a non-moved MI, breaking SlotIndex monotonicity
and corrupting LiveIntervals.
The corruption surfaced as a "register isn't live" assertion in
GCNDownwardRPTracker when PreRARematStage's finalizeGCNSchedStage
globally reverted regions that were already locally reverted by
checkScheduling.
Fix by calling LIS->handleMove for non-moved MIs whose SlotIndex has
become non-monotonic (PrevIdx >= MI_Idx). Additionally, track whether
checkScheduling already reverted a region and skip the redundant global
revert in finalizeGCNSchedStage.
Assisted-by: Claude Opus
Reapply "[cmake] Add support for statically linking libxml2" (#192088)
This applies a fix for windows not discovering libxml
This reverts commit 2a9c32496b5e8e63844597f638bdf67e4732fd35.