NetBSD/src iQbu3gOsys/compat/netbsd32 netbsd32_ioctl.c

   revert previous -- was fixed by removing __packed entirely.
VersionDeltaFile
1.124+5-4sys/compat/netbsd32/netbsd32_ioctl.c
+5-41 files

LLVM/project 84cc153flang/include/flang/Optimizer/Dialect FIROps.td, flang/test/Transforms licm.fir

[flang] Make fir.result Pure operation. (#173508)

This allows speculating recursively speculatable operations
containing `fir.result`. Note that making it Pure does not allow
speculating `fir.result` itself from its containing operation,
since it is a terminator.
DeltaFile
+85-0flang/test/Transforms/licm.fir
+3-3flang/include/flang/Optimizer/Dialect/FIROps.td
+88-32 files

LLVM/project 777017ellvm/test/CodeGen/NVPTX tcgen05-mma-block-scale-ptx88.ll tcgen05-mma-block-scale-ptx88-aa.ll

[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)

This commit adds support for family specific support for the following
intrinsics:
- ldmatrix
- stmatrix
- mma.block_scale, mma.sp.block_scale
- redux.sync
- cvt.rs
- clusterlaunchcontrol
- setmaxnreg
- tcgen05.mma

Removed `hasTcgen05Instructions` function in the favour of `hasTcgen05InstSupport` Updated wmma.py script with family specific support and added new tests
DeltaFile
+59-293llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88.ll
+246-0llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88-aa.ll
+219-0llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-i8.ll
+4-212llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane.ll
+168-0llvm/test/CodeGen/NVPTX/tcgen05-mma-ws-i8.ll
+166-0llvm/test/CodeGen/NVPTX/tcgen05-mma-i8.ll
+862-50519 files not shown
+1,105-84025 files

HardenedBSD/src 7991435sys/compat/linuxkpi/common/include/linux kmsg_dump.h font.h, sys/compat/linuxkpi/common/include/media cec.h cec-notifier.h

Merge remote-tracking branch 'origin/hardened/current/master' into hardened/current/cross-dso-cfi
DeltaFile
+147-35sys/net/iflib.c
+51-0sys/compat/linuxkpi/common/include/linux/kmsg_dump.h
+33-0sys/compat/linuxkpi/common/include/linux/font.h
+23-0sys/compat/linuxkpi/common/include/media/cec.h
+20-0sys/compat/linuxkpi/common/include/linux/spinlock.h
+17-0sys/compat/linuxkpi/common/include/media/cec-notifier.h
+291-357 files not shown
+332-3913 files

FreeNAS/freenas ba3d694src/middlewared/middlewared/plugins filesystem.py, src/middlewared/middlewared/utils/filesystem stat_x.py utils.py

NAS-139212 / 26.04 / use statx provided by truenas_pyos (#17972)

This commit removes the ctypes definition for statx and replaces with
the implemntatoin from truenas_pyos (cpython).
DeltaFile
+7-121src/middlewared/middlewared/utils/filesystem/stat_x.py
+0-103tests/unit/test_statx.py
+0-18src/middlewared/middlewared/utils/filesystem/utils.py
+4-13src/middlewared/middlewared/utils/filesystem/copy.py
+5-6src/middlewared/middlewared/plugins/filesystem.py
+4-3src/middlewared/middlewared/utils/filesystem/directory.py
+20-2643 files not shown
+20-2679 files

HardenedBSD/src 27dd91fsys/compat/linuxkpi/common/include/linux kmsg_dump.h font.h, sys/compat/linuxkpi/common/include/media cec.h cec-notifier.h

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+147-35sys/net/iflib.c
+51-0sys/compat/linuxkpi/common/include/linux/kmsg_dump.h
+33-0sys/compat/linuxkpi/common/include/linux/font.h
+23-0sys/compat/linuxkpi/common/include/media/cec.h
+20-0sys/compat/linuxkpi/common/include/linux/spinlock.h
+17-0sys/compat/linuxkpi/common/include/media/cec-notifier.h
+291-357 files not shown
+332-3913 files

FreeBSD/ports 563c23bgames/openbor distinfo Makefile

games/openbor: update to 7760

Changes:        https://github.com/DCurrent/openbor/compare/52921e77...7569231a
DeltaFile
+3-3games/openbor/distinfo
+2-2games/openbor/Makefile
+5-52 files

LLVM/project 4d4e375clang/lib/CodeGen CGDebugInfo.cpp, clang/test/DebugInfo/Generic macro-info.c

[Clang][DebugInfo] Add a flag to use expansion loc for macro params.

This patch adds a flag to allow users to preserve the old behaviour - use the macro expansion location for parameters. This is useful for wider testing of sample profile driven PGO which relies on debug information based mapping.
DeltaFile
+19-16clang/lib/CodeGen/CGDebugInfo.cpp
+12-6clang/test/DebugInfo/Generic/macro-info.c
+31-222 files

FreeBSD/ports a642b90graphics/mesa-devel distinfo Makefile, graphics/mesa-devel/files patch-renderdoc

graphics/mesa-devel: update to 25.3.b.3164

Changes:        https://gitlab.freedesktop.org/mesa/mesa/-/compare/7ed6679361f...5ac41be6777
DeltaFile
+0-25graphics/mesa-devel/files/patch-renderdoc
+3-3graphics/mesa-devel/distinfo
+2-2graphics/mesa-devel/Makefile
+5-303 files

FreeBSD/ports bee11b6games/veloren-weekly distinfo Makefile

games/veloren-weekly: update to s20260107

Changes:        https://gitlab.com/veloren/veloren/-/compare/253b0afc73...a5ef556b04
DeltaFile
+3-3games/veloren-weekly/distinfo
+2-2games/veloren-weekly/Makefile
+5-52 files

NetBSD/src qJQOVIAsys/compat/netbsd32 netbsd32_ioctl.h

   remove __packed from a bunch of ioctl structures.

   i noticed a warning unrelated to an evbarm llvm build failure here, and
   it turns out that we have a few things using __packed that should be
   using the right types instead, or don't need __packed at all.

   struct netbsd32_if_data and struct netbsd32_ksyms_gvalue use
   netbsd32_uint64 now, to avoid forcing the whole-struct alignment to 8.

   struct netbsd32_ifdatareq, struct netbsd32_dkwedge_list, and
   struct netbsd32_disk_strategy don't need __packed at all.

   structure sizes confirmed to remain the same on amd64.
VersionDeltaFile
1.81+20-20sys/compat/netbsd32/netbsd32_ioctl.h
+20-201 files

LLVM/project ff73ccalldb/test/API/commands/frame/var-dil/expr/Casts TestFrameVarDILCast.py

[LLDB] Tentative fix for lldb-arm-ubuntu buildbot. (#174893)

Not sure if this will fix the problem because I don't have a 32-bit arm
machine to test with.
DeltaFile
+14-7lldb/test/API/commands/frame/var-dil/expr/Casts/TestFrameVarDILCast.py
+14-71 files

LLVM/project 3faa34dllvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/WebAssembly libcalls.ll simd-unsupported.ll

[WebAssembly] Expand vector frem instructions

Commit 6ad41bc changed how frem is expanded during legalization and it
broke WebAssembly but we were missing test coverage. We want to maintain
our previous behavior of unrolling vectors and using a libcall to
implement scalar frem. I'm not sure why this now has to be different
(in ISelLowering) from other libcalls like fsin which work the same way
in the end, but this code does accurately describe what we want.

Fixes: https://github.com/emscripten-core/emscripten/issues/25991
DeltaFile
+68-59llvm/test/CodeGen/WebAssembly/libcalls.ll
+14-0llvm/test/CodeGen/WebAssembly/simd-unsupported.ll
+5-1llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+87-603 files

LLVM/project c99db71llvm/test/CodeGen/WebAssembly libcalls.ll

[WebAssembly] Disable explicit-locals in the libcalls.ll test. NFC (#174811)

The keep-registers mode isn't super useful without disabling
explicit-locals,
as the local gets/sets are irrelevant noise in most cases.
Switching this test makes the output much more concise and will make
upcoming
changes easier to review.
DeltaFile
+74-173llvm/test/CodeGen/WebAssembly/libcalls.ll
+74-1731 files

FreeBSD/ports 2137141www/pmwiki pkg-plist distinfo

www/pmwiki: Update to 2.5.4

Changelog: https://www.pmwiki.org/wiki/PmWiki/ChangeLog

Port return to pool

Sponsored by:   Netzkommune GmbH
DeltaFile
+224-223www/pmwiki/pkg-plist
+3-3www/pmwiki/distinfo
+2-2www/pmwiki/Makefile
+229-2283 files

NetBSD/src nZ2hd3wsys/arch/arm/broadcom bcm283x_platform.c

   fix previous (use a static variable and initialize it)
VersionDeltaFile
1.54+6-5sys/arch/arm/broadcom/bcm283x_platform.c
+6-51 files

LLVM/project 2789464llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp RISCVTargetTransformInfo.h, llvm/test/Analysis/CostModel/RISCV constant-pool.ll

[RISCV] Improve cost modeling of RISCVTTIImpl::getConstantPoolLoadCost() (#174438)

Some machines are able to make use of AUIPC + ADDI or LUI + ADDI fusion, make sure to consider that in the cost model for `RISCVTTIImpl::getConstantPoolLoadCost()`.
DeltaFile
+37-0llvm/test/Analysis/CostModel/RISCV/constant-pool.ll
+22-2llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+4-0llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+63-23 files

LLVM/project ec10afcclang/lib/CodeGen CGDebugInfo.cpp, clang/test/DebugInfo/Generic macro-info.c

[Clang][DebugInfo] Add a flag to use expansion loc for macro params.

This patch adds a flag to allow users to preserve the old behaviour - use the macro expansion location for parameters. This is useful for wider testing of sample profile driven PGO which relies on debug information based mapping.
DeltaFile
+10-10clang/lib/CodeGen/CGDebugInfo.cpp
+12-6clang/test/DebugInfo/Generic/macro-info.c
+22-162 files

OpenZFS/src 794f158module/zfs dmu_recv.c, tests/runfiles common.run

When receiving a stream with the large block flag, activate feature

ZFS send streams include a feature flag DMU_BACKUP_FEATURE_LARGE_BLOCKS
to indicate the presence of large blocks in the dataset. On the sending
side, this flag is included if the `-L` flag is passed to `zfs send`
and the feature is active in the dataset. On the receive side, the
stream is refused if the feature is active in the destination dataset
but the stream does not include the feature flag.

The problem is the feature is only activated when a large block is
born. If a large block has been born in the destination, but never
the source, the send can't work. This can arise when sending streams
back and forth between two datasets.

This commit fixes the problem by always activating the large blocks
feature when receiving a stream with the large block feature flag.

Reviewed-by: Brian Behlendorf <behlendorf1 at llnl.gov>
Reviewed-by: Alexander Motin <alexander.motin at TrueNAS.com>
Signed-off-by: Austin Wise <AustinWise at gmail.com>
Closes #18105
DeltaFile
+86-0tests/zfs-tests/tests/functional/rsend/send_large_blocks_initial.ksh
+83-0tests/zfs-tests/tests/functional/rsend/send_large_blocks_incremental.ksh
+16-0module/zfs/dmu_recv.c
+2-0tests/zfs-tests/tests/Makefile.am
+1-0tests/runfiles/common.run
+188-05 files

FreeNAS/freenas b7021c7src/middlewared/middlewared/utils/filesystem directory.py

Fix
DeltaFile
+1-1src/middlewared/middlewared/utils/filesystem/directory.py
+1-11 files

LLVM/project 7f7feb3clang/docs ReleaseNotes.rst, clang/include/clang/Basic CodeGenOptions.def

[clang][driver] Expose a frontend option for trap-unreachable

We have several issues that list surprising behavior around UB. In many
cases, this causes undesirable control flow, such as execution falling
through to the next function (or whatever is in memory) instead of
remaining within the bounds of the procedure. #174844, #48943, #146791,
and #137741 all discuss a host of related issues. In #174844, it was
mentioned that we have backend support for this for Rust, and at least
one big class of these issues could be addressed by exposing the option
to clang.

This patch adds a new driver option that does just that. For now, we're
leaving this option off by default, though we expect only small
differences in code size or performance as a result if it were to be
enabled. There will be an RFC in the future when we have more confidence
this should be the default configuration.

Fixes #174844
DeltaFile
+18-0clang/test/CodeGen/X86/unreachable-trap.c
+7-0clang/include/clang/Options/Options.td
+5-0clang/test/Driver/clang_f_opts.c
+3-0clang/include/clang/Basic/CodeGenOptions.def
+3-0clang/lib/Driver/ToolChains/Clang.cpp
+2-0clang/docs/ReleaseNotes.rst
+38-01 files not shown
+39-07 files

FreeNAS/freenas a49957csrc/middlewared/middlewared/utils/filesystem directory.py

Fix
DeltaFile
+3-3src/middlewared/middlewared/utils/filesystem/directory.py
+3-31 files

LLVM/project 5185f07llvm/lib/Target/RISCV RISCVRedundantCopyElimination.cpp, llvm/test/CodeGen/RISCV xandesperf-redundant-copy-elim.ll

[RISCV] Add support for XAndesPerf branch on immediate in RISCVRedundantCopyElimination (#174706)

This patch is like what Xqcibi did in
https://github.com/llvm/llvm-project/pull/174358.
DeltaFile
+62-0llvm/test/CodeGen/RISCV/xandesperf-redundant-copy-elim.ll
+9-5llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
+71-52 files

LLVM/project 8ae3fc2llvm/test/CodeGen/RISCV xqcibi-redundant-copy-elim.ll

[RISCV] Simplify testcases in xqcibi-redundant-copy-elim.ll. NFC. (#174695)

Remove unneeded load instructions and only remain one comparison
instruction.
DeltaFile
+41-130llvm/test/CodeGen/RISCV/xqcibi-redundant-copy-elim.ll
+41-1301 files

FreeBSD/ports 7b64641x11/polybar Makefile distinfo

x11/polybar: Fix build

Fix build error due to missing libfreetype by pulling in upstream patch.
DeltaFile
+4-1x11/polybar/Makefile
+3-1x11/polybar/distinfo
+7-22 files

NetBSD/src AR453Z6sys/compat/netbsd32 netbsd32_ioctl.c

   Avoid taking address of packed member.
VersionDeltaFile
1.123+4-5sys/compat/netbsd32/netbsd32_ioctl.c
+4-51 files

LLVM/project 4bd5ef7llvm/lib/Target/RISCV RISCVAsmPrinter.cpp, llvm/lib/Target/RISCV/MCTargetDesc RISCVELFStreamer.cpp RISCVTargetStreamer.cpp

[RISC-V][ELF] Move emitNoteGnuPropertySection to RISCVTargetELFStreamer. [NFCI] (#174890)

This function is invoked only for ELF targets, therefore it has been
moved to the ELF-specific streamer.

An assertion has been added to catch its invocations outside of an
invocation that targets ELF.
DeltaFile
+41-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+0-41llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+4-2llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+1-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+0-1llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+46-445 files

NetBSD/src HLQlb5rsys/arch/arm/broadcom bcm283x_platform.c

   Avoid taking address of packed member.
VersionDeltaFile
1.53+4-2sys/arch/arm/broadcom/bcm283x_platform.c
+4-21 files

LLVM/project a3c9b72llvm/lib/Analysis Loads.cpp, llvm/test/Transforms/GVN condprop.ll

[IR] Fix canReplacePointersIfEqual to properly validate vector pointers (#174142)

Previously, `canReplacePointersIfEqual` unconditionally returned
`true` for vectors of pointers (e.g., `<2 x ptr>`) because it only
checked for scalar pointer types.

This resulted in a failure to perform appropriate verification for
these types. This patch fixes the logic to ensure they are properly
validated.

Fixes https://github.com/llvm/llvm-project/issues/174045
DeltaFile
+33-0llvm/test/Transforms/InstSimplify/select-icmp.ll
+11-0llvm/test/Transforms/GVN/condprop.ll
+3-3llvm/lib/Analysis/Loads.cpp
+47-33 files

LLVM/project 1171e30llvm/lib/Target/WebAssembly WebAssemblyInstrSIMD.td WebAssemblyInstrInfo.td, llvm/test/CodeGen/WebAssembly simd-load-zero-offset.ll simd-load-store-alignment.ll

[WebAssembly] Support v128.load{32,64}_zero for f32 and f64 types (#172291)

This patch extends the `load_zero` pattern matching to
support floating-point vector types (`v4f32` and `v2f64`).

Previously, the optimization to generate `v128.load32_zero` and
`v128.load64_zero` was only enabled for integer types
(`v4i32` and `v2i64`). This change adds the necessary TableGen
patterns to correctly match scalar floating-point loads inserted
into zero-initialized vectors.
DeltaFile
+227-0llvm/test/CodeGen/WebAssembly/simd-load-zero-offset.ll
+112-0llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
+7-1llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+5-0llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
+351-14 files