LLVM/project 0fd0200llvm/lib/Target/AMDGPU SIInstructions.td

[AMDGPU] Make use of !ne. NFC. (#217855)
DeltaFile
+15-15llvm/lib/Target/AMDGPU/SIInstructions.td
+15-151 files

LLVM/project 5d9888fllvm/include/llvm/ADT GenericUniformityImpl.h

[UniformityAnalysis] Miscellaneous comment fixes (#217661)
DeltaFile
+5-4llvm/include/llvm/ADT/GenericUniformityImpl.h
+5-41 files

LLVM/project 8ae295dllvm/test/Transforms/IRCE unsigned_comparisons_ugt.ll unsigned_comparisons_ult.ll, llvm/test/Transforms/IndVarSimplify loop-predication.ll

[Analysis] Use usub_sat during SCEV expansion in some cases (#216975)

When expanding code in visitAddExpr we can look for the pattern

  -C + umax(X, C)

and transform this into

--> usub.sat(X, C)

which simplifies the IR in some tests.

Please see https://github.com/llvm/llvm-project/pull/118195 for the
original instcombine that this PR copies from. It contains the alive
link: https://alive2.llvm.org/ce/z/oSWe5S
DeltaFile
+76-4llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
+20-37llvm/test/Transforms/IRCE/unsigned_comparisons_ult.ll
+14-29llvm/test/Transforms/IRCE/unsigned_comparisons_ugt.ll
+12-24llvm/test/Transforms/IndVarSimplify/ARM/code-size.ll
+8-17llvm/test/Transforms/LoopPredication/predicate-exits.ll
+6-12llvm/test/Transforms/IndVarSimplify/loop-predication.ll
+136-12314 files not shown
+179-16620 files

FreeBSD/ports a809273math/R-cran-gss Makefile distinfo

math/R-cran-gss: Update to 3.0.0
DeltaFile
+3-3math/R-cran-gss/distinfo
+1-1math/R-cran-gss/Makefile
+4-42 files

FreeBSD/ports 9a0b832archivers/R-cran-zip Makefile distinfo

archivers/R-cran-zip: Update to 3.0.2
DeltaFile
+3-3archivers/R-cran-zip/distinfo
+1-1archivers/R-cran-zip/Makefile
+4-42 files

LLVM/project c660ef8llvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp, llvm/test/CodeGen/AArch64/GlobalISel select-reduce-add.mir select-reduce-minmax.mir

[AArch64][GlobalISel] Select integer vector reductions into GPRs (#212976)

Prototyping a new minimal type-based approach to RegBankSelect (#199040)
for compile-time purposes exposed various gaps in instruction selection
when not using the existing RegBankSelect pass. These manifested as new
fallbacks when compiling CTMark and the IR dataset from [1].

Imported patterns require an FPR result. This patch teaches instruction
selection to handle vector reductions with GPR results by using a
temporary FPR and inserting a cross-bank copy.

Assisted-by: codex

[1] https://davemgreen.github.io/gisel.html
DeltaFile
+106-0llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-minmax.mir
+86-0llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
+27-0llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+219-03 files

LLVM/project 3629a88clang/include/clang/AST ASTContext.h, clang/lib/AST RecordLayoutBuilder.cpp ExprConstant.cpp

[clang][AST] Add ASTContext::hasLayout() (#216541)

Whenever we add a new call to e.g. `ASTContext::getASTRecordLayout()`,
we inevitably cause a problem because that function has quite a few
prerequisites:

```c++
  D = D->getDefinition();
  assert(D && "Cannot get layout of forward declarations!");
  assert(!D->isInvalidDecl() && "Cannot get layout of invalid decl!");
  assert(D->isCompleteDefinition() && "Cannot layout type before complete!");
```

Add a function to check whether a record decl can be pased to
`getASTRecordLayout()` and update a few callers.
DeltaFile
+8-2clang/lib/AST/ByteCode/Pointer.cpp
+7-0clang/include/clang/AST/ASTContext.h
+2-2clang/lib/StaticAnalyzer/Core/MemRegion.cpp
+4-0clang/lib/AST/ExprConstant.cpp
+0-3clang/lib/AST/RecordLayoutBuilder.cpp
+3-0clang/lib/StaticAnalyzer/Checkers/PaddingChecker.cpp
+24-71 files not shown
+25-87 files

LLVM/project ef1a70alld/ELF SyntheticSections.cpp SyntheticSections.h, lld/test/ELF ppc32-ifunc-nonpreemptible-pic.s ppc32-ifunc-nonpreemptible-nopic.s

[ELF] Emit synthetic local in symbol table for non-preemptible IFUNC (#210616)

Currently we create an internal alias of the original symbol and then
rewrite the latter to point to the IPLT entry, which means we lose
symbol table information for the actual resolver. In practice compilers
also emit a normal function symbol for the resolver due to how IFUNCs
are represented in GNU C so that at least shows up, but we shouldn't be
relying on it. By emitting a synthetic local we can keep having a symbol
for the resolver whilst still redirecting references to the IPLT entry.
DeltaFile
+18-0lld/test/ELF/gnu-ifunc-i386.s
+2-3lld/ELF/Relocations.cpp
+1-2lld/ELF/SyntheticSections.h
+1-1lld/test/ELF/ppc32-ifunc-nonpreemptible-pic.s
+1-1lld/test/ELF/ppc32-ifunc-nonpreemptible-nopic.s
+1-1lld/ELF/SyntheticSections.cpp
+24-86 files

LLVM/project db8ad40lld/ELF Symbols.h

[NFC][ELF] Remove Symbol's unused copy constructor (#210615)

Now that we are no longer copying symbols via the copy constructor we
can remove it. Given we track symbol pointers in various data structures
it can be dangerous to have multiple objects for the same symbol that
would risk being viewed inconsistently, or even moved and the original
lost, though no such cases exist upstream that I'm aware of.

Copying a symbol entirely is also a weird thing to do, and can be
inefficient, so when copies are being made it's best to be explicit
about the members to copy. This also makes it clearer to understand what
members are relevant, rather than implicitly copying all the members,
most of which aren't relevant in practice.

Whilst the copy/move constructors/assignment operators are currently
implicitly deleted due to the atomic flags member, explicitly delete
them all so they remain deleted in case that ever changes.
DeltaFile
+6-3lld/ELF/Symbols.h
+6-31 files

LLVM/project a6ec980lld/ELF Relocations.cpp

[NFC][ELF] Only create alias in handleNonPreemptibleIfunc if needed (#210613)

In the no direct relocations case, the original IFUNC symbol keeps its
value, and so there's no need to create a separate alias; it's only
needed when the original symbol is being redirected to the IPLT as a
normal function symbol.

This change also shifts the isInIplt assignment to be explicit and
mirror the allocateAux/pltIdx uses, rather than relying on makeDefined
copying it, and to be clear that this is in fact deliberately and
consistently being copied like them.

A future commit will also change the exact way in which we create this
alias, and will rely on it only existing for the direct relocations
case.
DeltaFile
+23-18lld/ELF/Relocations.cpp
+23-181 files

LLVM/project 9a9c9a5lld/ELF Relocations.cpp

[NFC][ELF] Create fresh alias in handleNonPreemptibleIfunc (#210614)

We don't need to copy the full symbol here, we just want an internal
alias to use for the IPLT and IGOTPLT entries and IRELATIVE relocation's
addend.
DeltaFile
+3-1lld/ELF/Relocations.cpp
+3-11 files

LLVM/project 36a5f08mlir/test/python pass_manager.py

[MLIR] Fix invalid escape sequences (#94036)

Co-authored-by: Eisuke Kawashima <e-kwsm at users.noreply.github.com>
DeltaFile
+1-1mlir/test/python/pass_manager.py
+1-11 files

pkgng/pkgng bde69a3tests/frontend musl.bin musl.binin

tests/frontend: store musl fixture as .binin

musl.bin was committed directly instead of as musl.binin like every
other ELF fixture, so it was missing from out-of-tree builds and the
abi:elfparse / create-parsebin tests failed.
DeltaFile
+0-0tests/frontend/musl.bin
+0-0tests/frontend/musl.binin
+0-02 files

LLVM/project 3db5350llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp LegalizeVectorOps.cpp, llvm/test/CodeGen/VE/Vector vp_urem.ll vp_srem.ll

[DAG] Expand vp.*rem and vp.cttz.elts with non-vp nodes.

Trivial VP SDNodes will be removed in an upcoming patch. The division is still predicated so we avoid UB.
DeltaFile
+24-12llvm/test/CodeGen/VE/Vector/vp_urem.ll
+24-12llvm/test/CodeGen/VE/Vector/vp_srem.ll
+5-5llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+3-5llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+56-344 files

LLVM/project 4ec5f0allvm/include/llvm/IR VPIntrinsics.def, llvm/lib/CodeGen/SelectionDAG MatchContext.h LegalizeVectorOps.cpp

[DAG] Remove trivial VP SDNodes. NFC

This removes the codegen parts of the trivial VP intrinsics. It's quite far reaching, but the general categories of code removed are:

- Removing definitions from VPIntrinsics.def
- Legalization and expansion code
- MatchContext used to match over both VP and non-VP nodes
- Some dead DAGCombines and folds in SelectionDAGBuilder

There are still more things to be cleaned up after this, e.g. removing more of the VPIntrinsic class hierarchy, removing ExpandVectorPredication/moving expansion into other places, removing MatchContext from SDPatternMatch
DeltaFile
+80-283llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+3-340llvm/include/llvm/IR/VPIntrinsics.def
+6-336llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+47-282llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+7-217llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+0-182llvm/lib/CodeGen/SelectionDAG/MatchContext.h
+143-1,64011 files not shown
+188-2,01417 files

LLVM/project 1396edcllvm/lib/Target/VE VVPNodes.def

[VE] Remove trivial VP SDNode mappings. NFC

These SDNodes aren't emitted anymore and will be removed in an upcoming patch.
DeltaFile
+9-9llvm/lib/Target/VE/VVPNodes.def
+9-91 files

LLVM/project fdfa8a7llvm/include/llvm/IR IntrinsicInst.h, llvm/lib/IR IntrinsicInst.cpp

[IR] Remove VPIntrinsic::getFor{Opcode,Intrinsic}. NFC

These convert from non-VP to VP opcodes, which is only used by
LoopUtils for creating predicated reductions. This inlines it to make
removing the intrinsics easier in an upcoming patch.
DeltaFile
+0-106llvm/unittests/IR/VPIntrinsicTest.cpp
+39-6llvm/lib/Transforms/Utils/LoopUtils.cpp
+0-32llvm/lib/IR/IntrinsicInst.cpp
+0-7llvm/include/llvm/IR/IntrinsicInst.h
+39-1514 files

LLVM/project 9dfb676llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/RISCV vpintrin-scalarization-shufflevector-splat.ll vpintrin-scalarization.ll

[VectorCombine] Remove scalarizeVPIntrinsic

After #212490 all bin op VP intrinsics are upgraded to non-VP intrinsics, so this is now dead.

The one exception is div/rem VP intrinsics which aren't upgraded, but the loop vectorizer will never emit a VP div/rem of this form if the operands are scalar, and will emit a scalar replication instead.
DeltaFile
+0-1,354llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll
+0-125llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+0-16llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization-shufflevector-splat.ll
+0-1,4953 files

LLVM/project 4881a50llvm/docs LangRef.md, llvm/include/llvm/IR VPIntrinsics.def Intrinsics.td

[IR] Remove trivial VP intrinsics. NFC

Trivial VP intrinsics are now all autoupgraded to their non-VP counterparts, so the intrinsics themselves are dead.

This removes the intrinsics and their corresponding LangRef definitions, as well as the VPIntrinsic subclasses and some methods in ExpandVectorPredication which are now dead. Removing the SDNodes is deferred to a separate patch.
DeltaFile
+0-2,733llvm/docs/LangRef.md
+1-317llvm/include/llvm/IR/Intrinsics.td
+97-143llvm/include/llvm/IR/VPIntrinsics.def
+2-170llvm/lib/CodeGen/ExpandVectorPredication.cpp
+1-87llvm/lib/IR/IntrinsicInst.cpp
+0-72mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
+101-3,5228 files not shown
+107-3,76814 files

NetBSD/pkgsrc-wip 410d676fresh Makefile distinfo

Update editors/frsh to v.0.4.10
DeltaFile
+3-3fresh/distinfo
+1-1fresh/Makefile
+4-42 files

NetBSD/pkgsrc-wip 49f0a98clang distinfo, clang/patches patch-lib_Driver_ToolChain.cpp

`-fuse-ld=<name>` is broken on NetBSD — driver looks for `nb.lld`,
which does not exist. Applies to lang/clang as well.
DeltaFile
+0-16clang/patches/patch-lib_Driver_ToolChain.cpp
+0-1clang/distinfo
+0-172 files

LLVM/project 00c5435llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU permute.ll

[AMDGPU] Fix matchPERM infinite loop on sub-dword vector sources (#217813)

getDWordFromOffset rebuilt these as a BUILD_VECTOR, which legalization
turns back into the same OR pattern matchPERM matched, so DAGCombine
looped forever

Bitcast to a dword vector and extract instead
DeltaFile
+95-0llvm/test/CodeGen/AMDGPU/permute.ll
+8-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+103-02 files

LLVM/project 3ef5046llvm/lib/CodeGen ComplexDeinterleavingPass.cpp, llvm/test/CodeGen/AArch64 complex-deinterleaving-negation.ll

[CodeGen] Fix crash matching a negated implicit complex multiply (#217650)

identifyNodeWithImplicitAdd used Op after checking I0 with isNeg(),
which does not populate Op. When no earlier matcher initialized Op,
subsequent matching could dereference an invalid Value pointer and crash
the compiler.
DeltaFile
+34-0llvm/test/CodeGen/AArch64/complex-deinterleaving-negation.ll
+1-1llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
+35-12 files

LLVM/project 431980fflang/lib/Lower PFTBuilder.cpp, flang/lib/Semantics resolve-labels.cpp

PR review fixes
DeltaFile
+55-0flang/test/Lower/assigned-goto-labeled-end.f90
+11-12flang/lib/Lower/PFTBuilder.cpp
+4-1flang/test/Lower/assigned-goto-format-target.f90
+1-1flang/lib/Semantics/resolve-labels.cpp
+71-144 files

LLVM/project 77b7901flang/include/flang/Semantics semantics.h, flang/lib/Lower PFTBuilder.cpp

[flang] Do not branch to a FORMAT statement from an assigned GO TO

Label analysis already classifies which labeled statements may be named by
a statement that branches.  Record the positions of those statements in the
semantics context and consult it when lowering records the targets of an
assigned GO TO, so that a FORMAT statement is not given a target block.

A GO TO whose variable holds only a format label now reaches the run-time
error instead of branching into the FORMAT statement.

The label analysis is built once and shared: AnalyzeLabels() runs the
constraint checks first and records the branch targets only if they pass,
since a program with fatal errors is not lowered.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+75-0flang/test/Lower/assigned-goto-format-target.f90
+24-4flang/lib/Semantics/resolve-labels.cpp
+17-2flang/lib/Lower/PFTBuilder.cpp
+14-0flang/include/flang/Semantics/semantics.h
+4-2flang/lib/Semantics/resolve-labels.h
+6-0flang/test/Semantics/assign07.f90
+140-81 files not shown
+141-97 files

LLVM/project 6203e6dflang/lib/Semantics resolve-labels.cpp, flang/test/Semantics label20.f90

[flang] Record the position of a labeled program-unit END statement

The END statement of a program unit is visited in advance, before the
statement visitor has moved its current position onto it, so the position
recorded for a label on that statement was whatever statement came last --
a null source position for the first program unit in a file, and the
preceding unit's position for the others.  Pass the statement position to
AddTargetLabelDefinition explicitly instead of reading it from the visitor.

A diagnostic anchored on such a label had no location to report:

  subroutine s(j)
    integer :: j
    write(*,fmt=40)
    go to j
  40 end subroutine

before:


    [11 lines not shown]
DeltaFile
+77-0flang/test/Semantics/label20.f90
+15-9flang/lib/Semantics/resolve-labels.cpp
+92-92 files

FreeBSD/ports d629faddevel/p5-Type-Tiny-Signatures Makefile

devel/p5-Type-Tiny-Signatures: Set PORTSCOUT
DeltaFile
+2-0devel/p5-Type-Tiny-Signatures/Makefile
+2-01 files

LLVM/project c315c9dmlir/lib/Target/LLVMIR ModuleImport.cpp, mlir/test/Target/LLVMIR/Import function-metadata.ll

[MLIR][LLVM] Preserve unknown function metadata on import (#203022)

Import representable non-debug function metadata without a kind-specific
dialect conversion into `LLVMFuncOp` `function_metadata`. Preserve
repeated metadata kinds through the generic carrier so LLVM IR import
and export can round-trip the supported generic metadata subset.

Warn and drop attachments outside that subset while continuing to import
the function.
DeltaFile
+124-0mlir/test/Target/LLVMIR/Import/function-metadata.ll
+32-5mlir/lib/Target/LLVMIR/ModuleImport.cpp
+156-52 files

LLVM/project 676d006llvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp, llvm/test/CodeGen/AArch64/GlobalISel select-unmerge.mir

[AArch64][GlobalISel] Select unmerging s128 FPR value into two s64 GPR values (#215995)

RegBankSelect treats s128s like vectors when unmerging and assigns the
s64 results to FPR. Prototyping an alternative type-based RBS (#199040)
that assigns 64-bit scalar values to GPR exposed a gap in the
instruction selector.

Select the two s64 results directly with UMOVvi64.

Assisted-by: codex
DeltaFile
+33-11llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+24-0llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
+57-112 files

FreeBSD/ports a6f1888www/uwsgi Makefile

www/uwsgi: Mark PORTSCOUT
DeltaFile
+2-0www/uwsgi/Makefile
+2-01 files