AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (23) (#209214)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
[libc][cpp::string] Don't allocate a string in operator=(string_view)
This PR:
- Updates `opreator=(string_view)` to avoid allocating a temporary string: https://github.com/llvm/llvm-project/blob/67ebc4b221c3e94028b33004cd5cd08deee95048/libc/src/__support/CPP/string.h#L106-L108
- Changes `operator+=(const string&)` to accept a `string_view` so that strings may be appended without allocation.
- Adds asserts to make it clear that `cpp::string` does not support self assignment. Currently, `cpp::string s = "abc"; s = s;` will zero out the string.
[Clang] Require x86 target for some tests (#209532)
These tests assert behavior about the always-inliner which now requires
a target to be present to check function attribute compatibility for
inlining.
Fix forward for 37b8e765ce4837a7577e6f762bcdffe4b232759c.
[clang][cuda] Use the source filename for module ID (#209239)
Prior to
[#184065](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/184065") (relanded in
[#201849](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/201849")), the code
introduced in https://reviews.llvm.org/D42922 was using the GUID of an
internal linkage GlobalValue to create a module id, which would then be
used in a few cuda-specific places (including creating a symbol name
suffix).
[#184065](vscode-file://vscode-app/Applications/Visual%20Studio%20Code.app/Contents/Resources/app/out/vs/code/electron-browser/workbench/workbench.html
"https://github.com/llvm/llvm-project/issues/184065") assumed the
linkage of that symbol is external - which it isn't - and, thus, all
module IDs computed for this would be identical.
The fix is to not rely on GlobalValue GUIDs in the first place. What is
needed here is a hash that's specific to this module. So we're creating
that and explicitly decoupling that calculation from GlobalValue's
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[VPlan] Use VPlan::hasTailFolded in materializeConstantVectorTC. (#209502)
The current checks in materializeConstantVectorTripCount miss
tail-folded cases when vectorizing loops with fmax without fast-math
flags. Use recently added hasTailFolded helper to ensure we always bail
out on tail-folded loops.
Fixes https://github.com/llvm/llvm-project/issues/209159.
[Hexagon] Add lowering for `{max,min}num` (#202938)
Since the floating point requirements for `{max,min}num` are less strict
than the ones for `{max,min}imumnum`, it is fine to lower them to the
same instructions that already meet the requirements for the latter.
This is similar to what the RISC-V backend does for example.
This is also a lot better than generating a standard library call.
[AMDGPU] Fix CFI emission when scratch instructions are used to spill
4b1cfc5d7c606e "[NFCI][AMDGPU] Final touch before moving to
`GET_SUBTARGETINFO_MACRO` (#177401)" (or more generally the move to
hasFlatScratchEnabled over just enableFlatScratch) was missed during the
CFI upstreaming for AMDGPU, and so we currently define the CFA
incorrectly for the architected flat scratch case.
This incorrect CFI is generated for e.g. gfx942. For such architecture,
the stack pointer (s32) holds a swizzled address (per-lane offset) but
the CFA needs to be an unswizzled address (per-wave).
In the incorrect program, we have a prologue looking like:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_mov_b32 s0, s33
s_mov_b32 s33, s32
[...]
s_add_i32 s32, s32, 16
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Merge tag 'for-7.2-rc3-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux
Pull btrfs fixes from David Sterba:
- fix root structure leak after relocation error
- fix optimization when checksums are read from commit root, fall back
to checksum root during relocation
- in tree-checker, validate length of inode reference in items
- validate properties before setting them
- validate free space cache entries on load
- transaction abort fixes
- fix printing of internal trees as signed numbers
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[docker][Windows] install libxml2 using vcpkg (#209422)
Since https://github.com/llvm/llvm-project/pull/209258, lldb uses
`lldb-server.exe` by default if libxml2 is available at build time. This
means that lldb-server requires installing libxml2 in the CI
environments to test it.
This patch adds a step to install libxml2 in the docker container used
for lldb pre-merge testing on Windows.
[lldb] Add release note for SymStore and generate settings docs (#209469)
We didn't have a release note for the symstore symbol locator and the
settings weren't included on https://lldb.llvm.org/use/settings.html.
The second part is probably because both were landing at the same time,
so I missed the JSON output there.
[AMDGPU] Add stackPtrOffsetReg to llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
Prepare for this being observable to the CFA generation code.
Change-Id: I56d00133148fd2c8f0e0ed41edca446553c664bc
[AMDGPU] Fix CFI emission when scratch instructions are used to spill
A change upstream (4b1cfc5d7c606e "4b1cfc5d7c606 [NFCI][AMDGPU] Final
touch before moving to `GET_SUBTARGETINFO_MACRO` (#177401)") seem to
have not been fully propagated into the downstream amd-staging branch.
This caused incorrect CFI to be generated on some architectures such as
gfx942. For such architecture, the stack pointer (s32) holds a swizzled
address (per-lane offset) but the CFA needs to be an unswizzled address
(per-wave).
In the incorrect program, we have a prologue looking like:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_mov_b32 s0, s33
s_mov_b32 s33, s32
[...]
s_add_i32 s32, s32, 16
[...]
[23 lines not shown]
[AMDGPU] Fix type for DWARF register number in SIFrameLowering
It so happened that using MCRegister here happened to work, but
the encoded dwarf number is definitely not an MCRegister.
Change-Id: I13ef6a9ee870cf12db11f0cd20e03268e70e9bf9
bsd.cpu.mk: Add a workaround for erratum 843419
Add a workaround for the Arm Cortex-A53 erratum 843419. This has been
targeted when the build is either unoptimised for any CPU/architecture
or targets the Cortex-A53 or ARMv8.0 architecture.
PR: 296240
PR: 296395
Reported by: Hal Murray <halmurray+freebsd at sonic.net>
Reported by: Andreas Schuh <x55839 at icloud.com>
Reviewed by: cognet, mmel
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D58212
[AMDGPU][CodeGen] Fix `S_NOP` insertion during `S_SET_VGPR_MSB` placement
The issue arises when co-issue optimizations move the initial insertion
position for `S_SET_VGPR_MSB` to an earlier spot, creating a mismatch
with the position used to determine whether a `S_NOP` is needed.
init(8): extract reroot transient code into reroot_seed
Since init become dynamically linked, reroot appeared to be broken
because init copies itself into a transient tmpfs mount to continue
controlling execution right after the reboot(REROOT) syscall. Because
the binary is dynamically linked, it cannot be properly executed.
Provide a minimal static binary 'reroot_seed' embedded into the init as
byte stream, which performs what the 'init -r' did, namely, the second
phase reroot.
For the static build of init as part of the /rescue crunch, keep the
inline reroot code.
Reported and tested by: markj
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Differential revision: https://reviews.freebsd.org/D58164
