Interfaces: Assignments - add interface configuration settings in new assignments page. for https://github.com/opnsense/core/issues/10568
Refactor NetworkInterface model to reuse existing property names as much as possible, move from/to legacy logic into a custom fieldtype and store all legacy settings in a container named "pending" to ease reconfiguration and updating legacy configurations.
[MLIR] Document the OperationState properties invariant (#216686)
OperationState keeps `properties` together with the `propertiesDeleter`
and `propertiesSetter` hooks: the two `function_ref`s are non-null
whenever `properties` is non-null, and they are only ever called after
checking `properties`.
Static analyzers do not see that invariant. Because an empty
`function_ref` leaves its `callable` field indeterminate, Coverity
reports "Uninitialized scalar variable" at every site that copies an
OperationState: 6,436 of the 7,201 outstanding findings in the LLVM
Coverity project, nearly all in tblgen-generated `Op::create` methods.
Per review feedback, this no longer initializes `function_ref::callable`
in ADT. Instead it documents the invariant and suppresses the false
positive locally with a `// coverity[uninit_member]` annotation.
[mlir][scf] Sink ops into multi-block scf.execute_region (#216993)
Teach scf.execute_region to report its body is invoked exactly once via
RegionBranchOpInterface. This make the execute_region eligible for
sinking.
Also walk all blocks in a region instead of just the entry block so uses
in non-entry blocks can trigger sinking.
Fixes #216733
[Clang] Fix BitInt padding clearing on big-endian targets
This patch fixes the padding clearing logic of `_BitInt`s.
Before this patch, the clearing logic assumed little endian. But the
memory layout of BitInts differs between little and big endian:
- In LE, the occupied bits start from the lowest address and go on
contiguously up until the BitInt's declared size. The padding bits
then start from that point and go contiguously until the end of the
storage unit.
- In BE, since the byte order is reversed, the occupied bit interval
is not contiguous if the storage unit is larger than the BitInt's
size.
Therefore, the logic must tell the two cases apart and perform the
calculations accordingly.
[AArch64][ISel] Enable factor 3 interleave/deinterleave i1 support (#215524)
Add support for factor 3 interleave/deinterleave SVE predicate vectors.
This works by converting predicate operands to packed integer vectors,
reusing the existing interleave/deinterleave lowering, then converting
the nonzero results back to predicates.
[SLP]Fix narrow-tree gate width and extract miscount
Measure the narrowness of in-loop trees by the actual vectorization
width instead of the feeder-load width, and skip vector-typed scalars
in the instruction count check to match the cost model.
Fixes #216715
Reviewers: efriedma-quic, bababuck, RKSimon, kartcq
Pull Request: https://github.com/llvm/llvm-project/pull/216797
[SystemZ] Support the 'M' code for the odd register in inline-asm (#215481)
GCC considers 'M' to be an alias of 'N' when it comes to register
operands - regardless of the actual operand size [1]:
$ cat 1.c
void f(void) {
__int128 x;
asm volatile("# M=%M0 N=%N0" : "=r" (x));
}
$ gcc -S -O3 1.c
$ cat 1.s
[...]
# M=%r3 N=%r3
[...]
Do the same in LLVM; duplicate the existing 'N' test.
[1]
https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/s390/s390.cc;h=038eb57759ef#l9104
[JITLink] Make JITLink default in LLJIT for SystemZ (#215486)
ClangReplInterpreterTests fails on SystemZ with:
ExecutorNativePlatform requires ObjectLinkingLayer
JITLink seems to have become a superset of rtdyld on SystemZ. Make it
default.
