LLVM/project d927768flang/lib/Lower/OpenMP OpenMP.cpp

fix adding numThreadsNumDims to ParallelOperands apply method
DeltaFile
+1-0flang/lib/Lower/OpenMP/OpenMP.cpp
+1-01 files

LLVM/project fc81a66mlir/include/mlir/Dialect/Linalg/Utils Utils.h, mlir/lib/Dialect/Linalg/Transforms Specialize.cpp

[NFC][Linalg] Add `matchConvolutionOpOfType` API and make `isaConvolutionOpOfType` API a wrapper (#174722)

-- This commit involves the following updates pertaining to
`isaConvolutionOpOfType` API :-
1. We don't want dilations/strides of convolution op to be returned as
pointer arguments to the API function - to tackle this we create a new
API `matchConvolutionOpOfType` which would return an optional struct of
dilations/stride.
2. To not break the original API's use case as a simple querying
functionality with true/false return - we keep `isaConvolutionOpOfType`
as a wrapper API which will invoke `matchConvolutionOpOfType` API and
return true/false depending on whether `matchConvolutionOpOfType` API
returned any value or not.
3. Dilations/strides of named convolution op are also populated now (it
was missed in the previous PRs while creating `isaConvolutionOpOfType`).
4. [Max/Min]UnsignedPool ops' body matcher now only matches unsigned int
ops (refer: https://github.com/llvm/llvm-project/pull/166070)

-- No tests are being added as all the above are NFC changes around the

    [2 lines not shown]
DeltaFile
+956-617mlir/lib/Dialect/Linalg/Utils/Utils.cpp
+19-5mlir/include/mlir/Dialect/Linalg/Utils/Utils.h
+4-4mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
+979-6263 files

LLVM/project d186277mlir/lib/Dialect/Bufferization/IR BufferizationOps.cpp, mlir/test/Dialect/Bufferization canonicalize.mlir

[MLIR][Bufferization] Fold LoadOp only when the buffer is read only (#172595)

When we `memref.load` from a buffer, it folded to `tensor.extract` even
when the buffer was writable, causing unexpected results. For example:

```mlir
func.func @load_after_write_from_buffer_cast(%arg0: index, %arg1: index,
                            %arg2: tensor<?x?xf32>) -> f32 {
  %0 = bufferization.to_buffer %arg2 : tensor<?x?xf32> to memref<?x?xf32>
  linalg.ceil ins(%0 : memref<?x?xf32>) outs(%0 : memref<?x?xf32>)
  %1 = memref.load %0[%arg0, %arg1] : memref<?x?xf32>
  return %1 : f32
}
```
would fold into
```mlir
module {
  func.func @load_after_write_from_buffer_cast(%arg0: index, %arg1: index, %arg2: tensor<?x?xf32>) -> f32 {
    %0 = bufferization.to_buffer %arg2 : tensor<?x?xf32> to memref<?x?xf32>

    [5 lines not shown]
DeltaFile
+19-1mlir/test/Dialect/Bufferization/canonicalize.mlir
+2-2mlir/test/Dialect/SparseTensor/sparse_perm_lower.mlir
+2-1mlir/test/Dialect/SparseTensor/fuse_sparse_pad_with_consumer.mlir
+1-1mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
+1-1mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir
+1-1mlir/test/Dialect/SparseTensor/sparse_pack.mlir
+26-76 files

FreeBSD/ports c8048cedevel/p5-Locale-gettext distinfo Makefile

devel/p5-Locale-gettext: use default DISTNAME.

PR: 292324
Submitted by:   Evgenii Khramtsov <2khramtsov at gmail.com>
DeltaFile
+3-3devel/p5-Locale-gettext/distinfo
+0-1devel/p5-Locale-gettext/Makefile
+3-42 files

LLVM/project 84c19e7clang/lib/Interpreter IncrementalExecutor.cpp

[clang-repl] Use more precise search to find the orc runtime. (#175805)

The new mechanism relies on the path in the toolchain which should be
the autoritative answer. This patch tweaks the discovery of the orc
runtime from unittests where the resource directory is hard to deduce.

Should address the issue raised in #175435 and #175322
DeltaFile
+76-71clang/lib/Interpreter/IncrementalExecutor.cpp
+76-711 files

LLVM/project c7e4350llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-ext-rv64.ll rvp-ext-rv32.ll

[RISCV][llvm] Support select codegen for P extension (#175741)

This is scalar condition with fixed vector true/false value, we can just
handle it same as scalars.
DeltaFile
+55-0llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+37-0llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+24-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+116-03 files

LLVM/project 2f2ec93llvm/lib/Target/RISCV RISCVInstrInfoP.td, llvm/test/CodeGen/RISCV rvp-ext-rv64.ll rvp-ext-rv32.ll

[RISCV][llvm] Support vselect codegen for P extension (#175744)

The only difference between vselect vs. select is condition value(a.k.a.
mask), we can select by using bitwise operation:
vselect(mask, true, false) = (mask & true) | (~mask & false)
DeltaFile
+58-0llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+39-0llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+10-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+107-03 files

FreeBSD/ports 8062a57devel/llvm13 Makefile

devel/llvm13: fix build with python 3.12

PR:             285957
DeltaFile
+2-0devel/llvm13/Makefile
+2-01 files

LLVM/project 0e6ef95llvm/lib/Target/RISCV RISCVInstrInfoVVLPatterns.td RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vfclass-sdnode.ll fixed-vectors-vfclass.ll

[RISCV][llvm] Support IS_FPCLASS codegen for zvfbfa (#175758)

DeltaFile
+203-13llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
+206-4llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
+6-0llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+2-2llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+417-194 files

FreeBSD/ports 4c11029devel/llvm12 Makefile

devel/llvm12: fix build with python 3.12

PR:             285957
DeltaFile
+2-0devel/llvm12/Makefile
+2-01 files

LLVM/project 9ced34dflang/lib/Lower/OpenMP ClauseProcessor.cpp Clauses.cpp, flang/test/Lower/OpenMP num-teams-dims.f90

[FLANG] Add flang to mlir lowering for num_teams
DeltaFile
+52-0flang/test/Lower/OpenMP/num-teams-dims.f90
+27-10flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+23-4flang/lib/Lower/OpenMP/Clauses.cpp
+15-3flang/lib/Lower/OpenMP/OpenMP.cpp
+117-174 files

FreeBSD/ports ef909ccmisc/crush distinfo Makefile

misc/crush: Update to 0.32.1

Changelog: https://github.com/charmbracelet/crush/releases/tag/v0.32.1

Reported by:    GitHub (watch releases)
DeltaFile
+5-5misc/crush/distinfo
+1-1misc/crush/Makefile
+6-62 files

LLVM/project 7cc013allvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/include/llvm/Target CGPassBuilderOption.h

[CodeGen][NPM] Add support for -print-regusage in New Pass Manager (#169761)

Support `-print-regusage` flag in NPM for printing register usage information
DeltaFile
+3-4llvm/lib/CodeGen/RegisterUsageInfo.cpp
+5-0llvm/include/llvm/Passes/CodeGenPassBuilder.h
+4-0llvm/lib/CodeGen/TargetPassConfig.cpp
+1-0llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
+1-0llvm/include/llvm/Target/CGPassBuilderOption.h
+14-45 files

Linux/linux c537e12arch/riscv/net bpf_jit_comp64.c, kernel/bpf verifier.c

Merge tag 'bpf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf

Pull bpf fixes from Alexei Starovoitov:

 - Fix incorrect usage of BPF_TRAMP_F_ORIG_STACK in riscv JIT (Menglong
   Dong)

 - Fix reference count leak in bpf_prog_test_run_xdp() (Tetsuo Handa)

 - Fix metadata size check in bpf_test_run() (Toke Høiland-Jørgensen)

 - Check that BPF insn array is not allowed as a map for const strings
   (Deepanshu Kartikey)

* tag 'bpf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf:
  bpf: Fix reference count leak in bpf_prog_test_run_xdp()
  bpf: Reject BPF_MAP_TYPE_INSN_ARRAY in check_reg_const_str()
  selftests/bpf: Update xdp_context_test_run test to check maximum metadata size
  bpf, test_run: Subtract size of xdp_frame from allowed metadata size
  riscv, bpf: Fix incorrect usage of BPF_TRAMP_F_ORIG_STACK
DeltaFile
+17-8net/bpf/test_run.c
+11-3tools/testing/selftests/bpf/prog_tests/xdp_context_test_run.c
+2-4arch/riscv/net/bpf_jit_comp64.c
+5-0kernel/bpf/verifier.c
+35-154 files

FreeBSD/ports a9b5c8esecurity/bitwarden-cli Makefile, security/bitwarden-cli/files/packagejsons package-lock.json package.json

security/bitwarden-cli: Update to 2025.12.1

While here, convert to use USES=electron for fetching and archiving
node modules, and adjust Makefile accordingly.

Changelog: https://github.com/bitwarden/clients/releases/tag/cli-v2025.12.1

Reported by:    GitHub (watch releases)
DeltaFile
+6,172-4,115security/bitwarden-cli/files/packagejsons/package-lock.json
+55-58security/bitwarden-cli/files/packagejsons/package.json
+5-67security/bitwarden-cli/Makefile
+11-15security/bitwarden-cli/files/packagejsons/apps/desktop/desktop_native/napi/package.json
+6-9security/bitwarden-cli/files/packagejsons/apps/desktop/package.json
+11-0security/bitwarden-cli/files/packagejsons/libs/subscription/package.json
+6,260-4,2644 files not shown
+6,272-4,27610 files

LLVM/project aefccacllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU vector-reduce-mul.ll integer-mad-patterns.ll

[AMDGPU][GlobalISel] Add RegBankLegalize support for S64 G_MUL

Patch 4 of 4 patches to implement full G_MUL support in regbanklegalize.
DeltaFile
+195-203llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+106-101llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+98-49llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+21-21llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
+23-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+5-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+448-3752 files not shown
+450-3758 files

LLVM/project fcdae37llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-smul.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_S_MUL_*

Patch 3 of 4 patches to implement full G_MUL support in regbanklegalize.

Current mul.ll test is only partially updated and expected to fail.
It will be updated in the fourth patch.
DeltaFile
+92-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smul.mir
+19-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+117-04 files

LLVM/project de7c7f7llvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/test/MC/AMDGPU gfx1250_asm_wmma_w32.s

[AMDGPU] Fix the encoding of VOP3PX2 instructions

ISA spec says `SCALE_OPSEL[0:1]` determines which parts of S3 and S4 are used, and `SCALE_OPSEL_HI[0:1]` should be zero.
DeltaFile
+40-40llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
+20-20llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
+2-2llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+62-623 files

LLVM/project 0b3d001llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-mad_64_32.mir

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_MAD_*

Patch 2 of 4 patches to implement full G_MUL support in regbanklegalize.

Current mul.ll test is only partially updated and expected to fail.
It will be updated in the fourth patch.
DeltaFile
+47-162llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
+131-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+2-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+1-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
+185-1625 files

LLVM/project 58f9bdallvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel mul.ll

[AMDGPU][GlobalISel] Add partial RegBankLegalize support for G_MUL

Implement S16, S32, V2S16 support for G_MUL.

Part 1 of 4 patches to implement full G_MUL support in regbanklegalize.
Current mul.ll test is only partially updated due to missing S64 support that
will be implemented in the fourth patch thus mul.ll test will fail if it is run
without the fourth patch.
DeltaFile
+238-43llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+7-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+245-442 files

LLVM/project 07538acllvm/test/MC/Disassembler/AMDGPU gfx1250_dasm_wmma_w32.txt

[NFC][AMDGPU] Generate dasm tests from asm tests
DeltaFile
+894-840llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
+894-8401 files

LLVM/project c6e03c7llvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/test/MC/AMDGPU gfx1250_asm_wmma_w32.s

[AMDGPU] Fix the encoding of VOP3PX2 instructions

ISA spec says `SCALE_OPSEL[0:1]` determines which parts of S3 and S4 are used, and `SCALE_OPSEL_HI[0:1]` should be zero.
DeltaFile
+157-157llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
+20-20llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
+2-2llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+179-1793 files

LLVM/project 57a153allvm/test/MC/Disassembler/AMDGPU gfx1250_dasm_wmma_w32.txt

[NFC][AMDGPU] Generate dasm tests from asm tests
DeltaFile
+923-869llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
+923-8691 files

LLVM/project 6e62d40flang/lib/Semantics check-omp-loop.cpp, flang/test/Semantics/OpenMP linear-clause01.f90

[flang][OpenMP] Fix LINEAR clause validation and test expectations (#175707)

Fixes #175688

After #175383 was merged, the test
`Semantics/OpenMP/linear-clause01.f90` was failing because it had an
early return that prevented multiple errors from being reported.

This PR fixes two issues:

1. **Removes the early return** after detecting a modifier error on
DO/SIMD directives. Previously, when a modifier error was found, the
function would return immediately without checking other restrictions
like the scalar requirement. Now all applicable errors are reported.

2. **Updates test expectations** to expect both the modifier error AND
the scalar error for Case 1, where `arg(:)` is an array used with `uval`
modifier on a DO directive.


    [2 lines not shown]
DeltaFile
+3-5flang/test/Semantics/OpenMP/linear-clause01.f90
+1-1flang/lib/Semantics/check-omp-loop.cpp
+4-62 files

LLVM/project 6df63dcllvm/lib/Target/LoongArch LoongArchExpandPseudoInsts.cpp LoongArchMergeBaseOffset.cpp, llvm/lib/Target/LoongArch/AsmParser LoongArchAsmParser.cpp

[llvm][LoongArch] Add PC-relative address materialization using pcadd instructions

This patch adds support for PC-relative address materialization using
pcadd-class relocations, covering the HI20/LO12 pair and their GOT and
TLS variants (IE, LD, GD, and DESC).

Link: https://gcc.gnu.org/pipermail/gcc-patches/2025-December/703312.html
DeltaFile
+149-90llvm/test/CodeGen/LoongArch/code-models.ll
+132-89llvm/test/CodeGen/LoongArch/merge-base-offset.ll
+153-54llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
+114-30llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+42-28llvm/test/CodeGen/LoongArch/double-imm.ll
+39-16llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp
+629-30726 files not shown
+949-44732 files

LLVM/project f7b943elibcxx/test/libcxx/ranges/range.adaptors/range.join.with nodiscard.verify.cpp, libcxx/test/libcxx/ranges/range.adaptors/range.join.with/range.join.with.iterator eq.nodiscard.verify.cpp

[libc++][ranges][NFC] Merge  `join_with_view`s `[[nodiscard]]` tests (#175734)

This just merges all tests in a single `nodiscard.verify.cpp` as is the
common practice.
DeltaFile
+99-0libcxx/test/libcxx/ranges/range.adaptors/range.join.with/nodiscard.verify.cpp
+0-35libcxx/test/libcxx/ranges/range.adaptors/range.join.with/range.join.with.sentinel/eq.nodiscard.verify.cpp
+0-33libcxx/test/libcxx/ranges/range.adaptors/range.join.with/range.join.with.overview/adaptor.nodiscard.verify.cpp
+0-30libcxx/test/libcxx/ranges/range.adaptors/range.join.with/range.join.with.view/base.nodiscard.verify.cpp
+0-30libcxx/test/libcxx/ranges/range.adaptors/range.join.with/range.join.with.iterator/eq.nodiscard.verify.cpp
+0-28libcxx/test/libcxx/ranges/range.adaptors/range.join.with/range.join.with.view/begin.nodiscard.verify.cpp
+99-1563 files not shown
+99-2409 files

LLVM/project 309ca6dclang/lib/Headers opencl-c.h

[Clang][OpenCL] Add cl_intel_split_work_group_barrier extension (#175878)

The extension adds support for split work group barriers in OpenCL C.
The spec is available at:

https://registry.khronos.org/OpenCL/extensions/intel/cl_intel_split_work_group_barrier.html
DeltaFile
+12-0clang/lib/Headers/opencl-c.h
+12-01 files

FreeBSD/ports 3141751databases Makefile, databases/timescaledb-parallel-copy Makefile distinfo

databases/timescaledb-parallel-copy: New port
DeltaFile
+20-0databases/timescaledb-parallel-copy/Makefile
+5-0databases/timescaledb-parallel-copy/distinfo
+3-0databases/timescaledb-parallel-copy/pkg-descr
+1-0databases/Makefile
+29-04 files

FreeBSD/src c498eaasys/dev/asmc asmcvar.h asmc.c

asmc: Add support for MacBookPro11,5

  Add support for the MacBookPro11,5 (Mid 2015, 15-inch with AMD Radeon R9 M370X GPU)
  to the Apple SMC driver.

  Debug testing revealed this model lacks several SMC keys present on MacBookPro11,4
  (IBLC, ICMC, IC2C), that model-specific sensor definitions.

Differential Revision:  https://reviews.freebsd.org/D54665
Reviewed by:    adrian
DeltaFile
+35-0sys/dev/asmc/asmcvar.h
+7-0sys/dev/asmc/asmc.c
+42-02 files

OpenBSD/src ewedm2Qusr.sbin/vmctl vmctl.c, usr.sbin/vmd vmd.c vm.c

   Simplify vmd(8) structs, removing embedded vmm(4) structs.

   This removes some hard dependencies from vmctl(8) on the structures
   from vmm(4) and makes naming of identifiers more explicit.

   Oh the surface, this is cosmetic, but the intention is to decouple
   as much as possible from the dev/vmm/vmm.h to allow for upcoming
   work to change vmm(4) without causing a large blast radius.

   Testing help from mlarkin@ & bluhm@.

   ok mlarkin@
VersionDeltaFile
1.171+87-105usr.sbin/vmd/vmd.c
1.123+71-69usr.sbin/vmd/vm.c
1.14+57-64usr.sbin/vmd/x86_vm.c
1.95+50-65usr.sbin/vmctl/vmctl.c
1.134+39-41usr.sbin/vmd/virtio.c
1.144+55-24usr.sbin/vmd/vmd.h
+359-36813 files not shown
+466-48519 files