LLVM/project d6d5c5fclang/docs ReleaseNotes.rst, clang/include/clang/Basic DiagnosticSemaKinds.td

[Clang] Warn when `std::atomic_thread_fence` is used with `fsanitize=thread` (#166542)

- ThreadSanitizer currently does not support `std::atomic_thread_fence`,
leading to false positives:
https://github.com/llvm/llvm-project/issues/52942.
- GCC produces a warning when `std::atomic_thread_fence` is used with
`-fsanitize=thread` while Clang doesn't.
- This PR introduces a matching warning in Clang to avoid confusion as
in the linked issue.

---------

Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
DeltaFile
+70-0clang/test/SemaCXX/warn-tsan-atomic-fence.cpp
+67-0clang/lib/Sema/SemaChecking.cpp
+7-2clang/include/clang/Sema/Sema.h
+2-2clang/lib/Sema/Sema.cpp
+3-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+2-0clang/docs/ReleaseNotes.rst
+151-46 files

OPNSense/core 632d5bbsrc/opnsense/mvc/app/views/OPNsense/Kea dhcpv4.volt, src/opnsense/www/js opnsense_bootgrid.js

bootgrid: allow conditional command rendering through a filter function

(cherry picked from commit 3fe0cc4a28c37b874a53807abdb3a605db41d46e)
(cherry picked from commit 3736489db27e0f5a1406ba5d0bad0c4bf71153d7)
(cherry picked from commit 1356068da4043874475f6ed0a20b611d05ca6a70)
(cherry picked from commit d25a8acd8ed5f17c6cad005525af2245cf623ed9)
DeltaFile
+183-121src/opnsense/www/js/opnsense_bootgrid.js
+35-39src/opnsense/mvc/app/views/OPNsense/Kea/dhcpv4.volt
+218-1602 files

LLVM/project 4a22a1cllvm/lib/Target/AArch64 AArch64InstrInfo.cpp

Swap checks

Co-authored-by: Benjamin Maxwell <benjamin.maxwell at arm.com>
DeltaFile
+1-1llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+1-11 files

LLVM/project 054ee2fllvm/lib/Target/CSKY CSKYISelLowering.h, llvm/test/CodeGen/CSKY/fpu fp16-promote.ll

[CSKY] Use `softPromoteHalfType` (#175138)

Follow suite from other targets.

Fixes the C-SKY portion of
https://github.com/llvm/llvm-project/issues/97975
Fixes the C-SKY portion of
https://github.com/llvm/llvm-project/issues/97981
DeltaFile
+24-24llvm/test/CodeGen/CSKY/fpu/fp16-promote.ll
+2-2llvm/test/CodeGen/Generic/half-op.ll
+1-1llvm/test/CodeGen/Generic/half.ll
+2-0llvm/lib/Target/CSKY/CSKYISelLowering.h
+29-274 files

LLVM/project a06bf00llvm/lib/Target/VE VEISelLowering.h, llvm/test/CodeGen/Generic half-op.ll half.ll

[VE] Use `softPromoteHalfType` (#175141)

Follow suite from other targets.

Fixes the (unlisted) VE portion of
https://github.com/llvm/llvm-project/issues/97975
Fixes the (unlisted) VE portion of
https://github.com/llvm/llvm-project/issues/97981
DeltaFile
+2-9llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll
+1-1llvm/test/CodeGen/Generic/half-op.ll
+1-1llvm/test/CodeGen/Generic/half.ll
+1-0llvm/lib/Target/VE/VEISelLowering.h
+5-114 files

LLVM/project 2a254d4llvm/lib/Target/M68k M68kISelLowering.h, llvm/test/CodeGen/Generic half-op.ll

[M68k] Use `softPromoteHalfType` (#175140)

Follow suite from other targets.

Fixes the M68k portion of
https://github.com/llvm/llvm-project/issues/97975
Fixes the M68k portion of
https://github.com/llvm/llvm-project/issues/97981
DeltaFile
+2-0llvm/lib/Target/M68k/M68kISelLowering.h
+1-1llvm/test/CodeGen/Generic/half-op.ll
+3-12 files

LLVM/project 8857534llvm/lib/Target/MSP430 MSP430ISelLowering.h, llvm/test/CodeGen/Generic half-op.ll

[MSP430] Use `softPromoteHalfType` (#175139)

Follow suite from other targets.

Fixes the MSP430 portion of
https://github.com/llvm/llvm-project/issues/97975
Fixes the MSP430 portion of
https://github.com/llvm/llvm-project/issues/97981
DeltaFile
+17-18llvm/test/CodeGen/MSP430/llvm.sincos.ll
+2-0llvm/lib/Target/MSP430/MSP430ISelLowering.h
+1-1llvm/test/CodeGen/Generic/half-op.ll
+20-193 files

LLVM/project a218940llvm/lib/Target/Lanai LanaiISelLowering.h, llvm/test/CodeGen/Generic half-op.ll

[Lanai] Use `softPromoteHalfType` (#175137)

There are currently no other tests checking `half` so I am unsure how
well supported the type is, but the patch here resolves the op tests.

Fixes the (unlisted) Lanai portion of
https://github.com/llvm/llvm-project/issues/97975
Fixes the (unlisted) Lanai portion of
https://github.com/llvm/llvm-project/issues/97981
DeltaFile
+2-0llvm/lib/Target/Lanai/LanaiISelLowering.h
+1-1llvm/test/CodeGen/Generic/half-op.ll
+3-12 files

LLVM/project b540103llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/RISCV/rvv vsplats-zfa.ll

[DAG]Add ISD::SPLAT_VECTOR to TargetLowering::getNegatedExpression (#173967)

Fold splat_vector(fneg(X)) -> splat_vector(-X)
Call the getCheaperNegatedExpression function, and ISD::SPLAT_VECTOR
return NegatibleCost::Cheaper.
This optimization is applied only to the fneg instruction.
DeltaFile
+46-0llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll
+12-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+58-02 files

LLVM/project dcaa9cbllvm/lib/Target/AArch64 AArch64InstrInfo.cpp

Add a mustAvoidNeonAtMBBI() wrapper to simplify logic.
DeltaFile
+12-5llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+12-51 files

LLVM/project affc5f1mlir/include/mlir/Dialect/Tosa/IR TosaShapeOps.td, mlir/lib/Dialect/Tosa/Transforms TosaValidation.cpp

[mlir][tosa] Add mod_shape op  (#170343)

Adds support for the mod_shape operation after spec change:
https://github.com/arm/tosa-specification/commit/efc88a100e2db06c2d6bc479fa63b26daab899ce.

This includes the operator definition, same rank checks and level checks
during validation. It does not currently include support for folding or
shape inference. This will be added in a later commit.
DeltaFile
+18-0mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
+10-0mlir/test/Dialect/Tosa/verifier.mlir
+10-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+10-0mlir/test/Dialect/Tosa/level_check.mlir
+9-0mlir/test/Dialect/Tosa/ops.mlir
+1-0mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+58-01 files not shown
+59-07 files

OPNSense/core 88e6e05src/www guiconfig.inc

firewall: remove unused function pprint_address()
DeltaFile
+0-17src/www/guiconfig.inc
+0-171 files

OpenBSD/ports JjzoDdHarchivers/kapsul distinfo Makefile, archivers/kapsul/patches patch-go_sum patch-go_mod

   Fix for Go >=1.26.
   Prodded by tb@
VersionDeltaFile
1.1+14-0archivers/kapsul/patches/patch-go_sum
1.1+14-0archivers/kapsul/patches/patch-go_mod
1.2+4-4archivers/kapsul/distinfo
1.2+4-0archivers/kapsul/Makefile
1.2+1-1archivers/kapsul/modules.inc
+37-55 files

FreeBSD/src a556febshare/man/man7 freebsd-base.7

freebsd-base.7: Fix stray -r

Remote stray "-r" from the example of installing a toolchain
to alternate root.

Reviewed by:    ivy
Differential Revision:  https://reviews.freebsd.org/D54611
DeltaFile
+1-1share/man/man7/freebsd-base.7
+1-11 files

NetBSD/src Fi1Wtp9libexec/ld.elf_so xmalloc.c

   Port the FreeBSD change

       Remove remnants of optimization for > pagesize allocations.

       In the past, this allocator seems to have allocated things larger than
       a page seperately. Much of this code was removed at some point (perhaps
       along with sbrk() used) so remove the rest. Instead, keep allocating in
       power-of-two bins up to FIRST_BUCKET_SIZE << (NBUCKETS - 1). If we want
       something more efficent, we should use a fancier allocator.

       While here, remove some vestages of sbrk() use. Most importantly, don't
       try to page align the pagepool since it's always page aligned by mmap().
VersionDeltaFile
1.17+17-53libexec/ld.elf_so/xmalloc.c
+17-531 files

LLVM/project 1e5c4c0llvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+118-2llvm/docs/AMDGPUUsage.rst
+118-21 files

LLVM/project 15d5f43clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.def
+96-03 files

LLVM/project 084f235llvm/lib/Target/AMDGPU SIISelLowering.cpp

Use enum values for src modifiers.
DeltaFile
+6-7llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-71 files

NetBSD/src 51pZPissys/sys exec_ecoff.h

   Sprinkle #include <sys/endian.h>
VersionDeltaFile
1.23+3-1sys/sys/exec_ecoff.h
+3-11 files

LLVM/project 5243501llvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine icmp-srem.ll

[InstCombine] Guard foldICmpSRemConstant against zero divisors (#173702)

instcombine can create srem X, 0 or icmp ult X, 0 mid-pass when
operands fold to zero, which trips assertions in foldICmpSRemConstant.
Bail out on zero divisors / zero ULT constants instead of asserting,
and add a regression test from the minimized reproducer.

This was found by a fuzzer I'm working on.  The high-level design is to
randomly generate LLVM IR, run a pass on it, and then run the original
and new IR through the interpreter.  They should produce the same
results.  Right now I'm only fuzzing instcombine.
DeltaFile
+15-0llvm/test/Transforms/InstCombine/icmp-srem.ll
+2-2llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+17-22 files

LLVM/project a4ee3d9llvm/lib/Analysis InstructionSimplify.cpp, llvm/test/Transforms/InstCombine minmax-fp.ll

[Instcombine] Fix crash in foldMinimumMaximumSharedOp (#173705)

We were missing a check that the inner intrinsic is in fact a min/max
op.  We'd crash if it was any other intrinsic!

This was found by a fuzzer I'm working on.  The high-level design is to
randomly generate LLVM IR, run a pass on it, and then run the original
and new IR through the interpreter.  They should produce the same
results.  Right now I'm only fuzzing instcombine.
DeltaFile
+16-5llvm/lib/Analysis/InstructionSimplify.cpp
+16-0llvm/test/Transforms/InstCombine/minmax-fp.ll
+32-52 files

LLVM/project c39f8b4llvm/lib/Transforms/InstCombine InstCombineSelect.cpp, llvm/test/Transforms/InstCombine 2012-05-28-select-hang.ll

[Instcombine] Fix infinite loop in visitSelectInst (#173704)

Doing a nop replaceOperand leads us into an infinite loop here.

This was found by a fuzzer I'm working on.  The high-level design is to
randomly generate LLVM IR, run a pass on it, and then run the original
and new IR through the interpreter.  They should produce the same
results.  Right now I'm only fuzzing instcombine.
DeltaFile
+27-0llvm/test/Transforms/InstCombine/2012-05-28-select-hang.ll
+2-2llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+29-22 files

LLVM/project 4684e50llvm/lib/Transforms/InstCombine InstCombineMulDivRem.cpp, llvm/test/Transforms/InstCombine instcombine-dominance-fixup.ll

[Instcombine] Ensure simplifyValueKnownNonZero adds instrs in dominance order (#173703)

This was found by a fuzzer I'm working on.  The high-level design is to
randomly generate LLVM IR, run a pass on it, and then run the original
and new IR through the interpreter.  They should produce the same
results.  Right now I'm only fuzzing instcombine.
DeltaFile
+23-0llvm/test/Transforms/InstCombine/instcombine-dominance-fixup.ll
+7-3llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+30-32 files

LLVM/project 1c07ba6llvm/lib/Transforms/Scalar SeparateConstOffsetFromGEP.cpp, llvm/test/Transforms/SeparateConstOffsetFromGEP negative-i32-offset.ll

[SeparateConstOffsetFromGEP] Use getSigned() for accumulated offset

It's a signed quantity.

Fixes the issue reported at:
https://github.com/llvm/llvm-project/pull/171456#issuecomment-3727345950
DeltaFile
+16-0llvm/test/Transforms/SeparateConstOffsetFromGEP/negative-i32-offset.ll
+1-1llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+17-12 files

LLVM/project bd87ab1llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 stack-hazard.ll arm64-ccmp.ll

[AArch64] Optimize ANDS(CSET, CSET) to CCMP. (#174919)

We have existing optimizations for and(cset, cset) and or(cset, cset),
converting them to more optimal ccmp chains. This makes use of the same
optimization for ANDS instructions that do not require the result of the
AND (i.e. TSTs). We generate a cmp from a cset, for the flags produced
by the ANDS. This will then be optimised away in many cases, leaving the
ccmp and use of the flags.
DeltaFile
+12-18llvm/test/CodeGen/AArch64/stack-hazard.ll
+10-16llvm/test/CodeGen/AArch64/arm64-ccmp.ll
+20-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-4llvm/test/CodeGen/AArch64/fcmp-fp128.ll
+44-404 files

OPNSense/core 7abbca5src/opnsense/mvc/app/models/OPNsense/Radvd Radvd.php Radvd.xml

Add MinRtrAdvInterval and AdvDefaultLifetime validations to Radvd.php as the require calculations
DeltaFile
+57-1src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.php
+1-2src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.xml
+58-32 files

OPNSense/core daefd8asrc/opnsense/scripts/suricata setup.sh

Services: Intrusion Detection - load ipdivert for new inline mode (missing in https://github.com/opnsense/core/pull/9561)
DeltaFile
+3-0src/opnsense/scripts/suricata/setup.sh
+3-01 files

OpenBSD/ports JKRwjXJdevel/jjui distinfo modules.inc

   Update to jjui v0.9.9

   https://github.com/idursun/jjui/releases/tag/v0.9.9
VersionDeltaFile
1.17+40-22devel/jjui/distinfo
1.9+10-5devel/jjui/modules.inc
1.17+1-1devel/jjui/Makefile
+51-283 files

LLVM/project 1c9ef2cllvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+118-2llvm/docs/AMDGPUUsage.rst
+118-21 files

LLVM/project 5c4650dclang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.def
+96-03 files