FreeBSD/src a09d06blib/libc/gen Makefile.inc

libc: Add missing MLINK for stravis(3)

MFC after:      1 week
Fixes:          8dfeba04eb36 ("Update to a June 8th snapshot of (un)vis form NetBSD.")
Reviewed by:    ziaee
Differential Revision:  https://reviews.freebsd.org/D56260
DeltaFile
+1-0lib/libc/gen/Makefile.inc
+1-01 files

LLVM/project 5d95920llvm/test/CodeGen/AMDGPU asyncmark-pregfx12.ll

[NFC][AMDGPU] don't test asyncmark for non-async variants on pre-gfx12

The test for asyncmark on pref-gfx12 targets, checks the effect of async marks
on both async and non-async instructions. This is achieved by a sed invocation
in the RUN line to remove the .async from intrinsic name.

Such a test serves no purpose other than a minor flex. The two sets of CHECK
lines using the WITH and WITHOUT prefix are not easy to compare by a simple
eyeballing. Eliminating this hack makes it easier to add GISEL variants later.
With and without GISEL, the combinations will increase to four instead of the
current two.

Assisted-By: Claude Opus 4.6
DeltaFile
+13-216llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
+13-2161 files

FreeBSD/ports e330aefwww/deno/files patch-cargo-crates_libuv-sys-lite

www/deno: Fix build when llvm22 is installed

For whatever reason the build fails if llvm22 is installed / used,
the generated bindings.rs file doesn't have all the needed definitions.
Fix this by providing libuv bindgen likes it's done for others OS [3]
(it was generated with llvm21).

error be like:
libuv-sys-lite-1.48.2/src/functions.rs
    |
785 |       addr: *mut sockaddr_in,
    |                  ^^^^^^^^^^^ help: a struct with a similar name exists: `sockaddr`

For reference: deno issue [1], libuv-sys-lite issue [2] and fix [3]

[1] https://github.com/denoland/deno/issues/32351
[2] https://github.com/nathanwhit/libuv-sys-lite/issues/1
[3] https://github.com/nathanwhit/libuv-sys-lite/commit/37c1821e8e94f70dc0c768092d8a44920609d045


    [2 lines not shown]
DeltaFile
+7,400-0www/deno/files/patch-cargo-crates_libuv-sys-lite
+7,400-01 files

LLVM/project 6d3d88fllvm/test/CodeGen/AMDGPU frem.ll llvm.minimum.f16.ll

AMDGPU: Use SmallSet for VOPD scalar reg tracking (#190650)

Use SmallSet instead of SmallVector for UniqueScalarRegs.
VCC_LO was pushed without uniqueness check, so when both
components used VCC implicitly it was counted twice,
rejecting valid VOPD pairings.

Co-Authored-By: Claude Opus 4.6 <noreply at anthropic.com>
DeltaFile
+38-41llvm/test/CodeGen/AMDGPU/frem.ll
+23-25llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
+23-25llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
+13-14llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
+13-14llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
+8-11llvm/test/CodeGen/AMDGPU/fmed3.ll
+118-1308 files not shown
+153-17014 files

LLVM/project aacd600llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp, llvm/test/CodeGen/AMDGPU amdgpu-sw-lower-lds-static-alloca-placement.ll

[AMDGPU][ASAN] Move allocas to entry block in amdgpu-sw-lower-lds pass
DeltaFile
+95-0llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-alloca-placement.ll
+13-1llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+108-12 files

LLVM/project 543ec35orc-rt/include/orc-rt Session.h, orc-rt/lib/executor Session.cpp

[orc-rt] Add managed-code-calls TaskGroup. (#190740)

Adds a ManagedCodeCallsGroup TaskGroup to Session, and updates the
shutdown sequence to wait until all calls into managed code have
completed before proceeding to shut down the Session's Services and the
Session itself.

To support safe calls into managed code two new helper template methods
are added:

callManagedCodeSync attempts to acquire a TaskGroup::Token for the
ManagedCodeCallsGroup before calling the given function and returning
its result.

callManagedCodeAsync attempts to acquire a TaskGroup::Token for the
ManagedCodeCallsGroup before calling the given async function. The
wrapped Return call for the async function will carry the acquired
Token, ensuring that shutdown waits for the async Return call to be
destroyed (whether or not it's actually called).
DeltaFile
+218-1orc-rt/unittests/SessionTest.cpp
+126-2orc-rt/include/orc-rt/Session.h
+26-17orc-rt/lib/executor/Session.cpp
+370-203 files

LLVM/project 546787emlir/include/mlir/Dialect/SPIRV/IR SPIRVTosaTypes.td, mlir/test/Dialect/SPIRV/IR tosa-ops-verification.mlir

[mlir][spirv] Fix SPIRV TOSA per-channel rescale length verification (#190748)

`TensorLengthMatchesPerChannel` was checking `rank(input) - 1` instead
of `input_shape[rank(input) - 1]`. Fix the predicate and update the
rescale verifier tests accordingly.

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+8-8mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
+2-2mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
+10-102 files

LLVM/project aa4c76dmlir/include/mlir/IR BuiltinDialectBytecode.td, mlir/unittests/Bytecode BytecodeTest.cpp

[mlir][BytecodeReader] Fix crash reading FusedLoc with empty locations (#189228)

FusedLoc::get(context, locs) may return UnknownLoc when locs is empty
and no metadata is provided. The bytecode reader's cBuilder used
cast<FusedLoc>() on this result, which crashes with an assertion
failure.

Fix by giving the FusedLoc DialectAttribute its own cBuilder that passes
Attribute() explicitly, causing getChecked<FusedLoc> to call the
two-parameter storage constructor directly and always produce a
FusedLoc.

Fixes #99626

Assisted-by: Claude Code
DeltaFile
+26-0mlir/unittests/Bytecode/BytecodeTest.cpp
+6-2mlir/include/mlir/IR/BuiltinDialectBytecode.td
+32-22 files

FreeNAS/freenas 93f66d4.github/workflows mypy.yml

Use mypy from pip

(cherry picked from commit e471a832219a5d464d839952ddf5182892eed4a3)
DeltaFile
+0-3.github/workflows/mypy.yml
+0-31 files

FreeNAS/freenas 2c980c0.github/workflows mypy.yml

NAS-140580 / 27.0.0-BETA.1 / Use mypy from pip (#18661)

We already have it in the developer image
DeltaFile
+0-3.github/workflows/mypy.yml
+0-31 files

FreeBSD/ports 4ec7b41devel/R-cran-ellipsis Makefile distinfo

devel/R-cran-ellipsis: Update to 0.3.3

- Update to 0.3.3
- Correct LICENSE to MIT (missed in 82dbc8dd9ef7)

Reported by:    portscout
Fixes:          82dbc8dd9ef7 devel/R-cran-ellipsis: Update to 0.3.2
DeltaFile
+3-5devel/R-cran-ellipsis/Makefile
+3-3devel/R-cran-ellipsis/distinfo
+6-82 files

FreeBSD/src 359d6e3. Makefile.inc1, release/packages create-sets.sh generate-ucl.sh

packages: Always use the bootstrap flua

To avoid breaking the build due to incompatible changes in flua or lua
libraries on the host, use the bootstrap flua for the package build.

MFC after:      2 weeks
Reviewed by:    kevans, emaste
Sponsored by:   https://www.patreon.com/bsdivy
Differential Revision:  https://reviews.freebsd.org/D56271
DeltaFile
+11-10Makefile.inc1
+1-1release/packages/create-sets.sh
+1-1release/packages/generate-ucl.sh
+13-123 files

FreeBSD/src 50de0bf. Makefile.inc1

flua: Always build as a bootstrap tool

We want to use flua from the source tree (not the host) during package
build, firstly to protect us from breaking changes in lua or libucl,
and secondly to allow (in future) cross-building of packages from
Linux or macOS.

Since we don't know if the user will be building packages during the
bootstrap phase, and because flua is fairly small and generally useful,
build it as a bootstrap tool unconditionally.

MFC after:      2 weeks
Reviewed by:    kevans, emaste
Sponsored by:   https://www.patreon.com/bsdivy
Differential Revision:  https://reviews.freebsd.org/D56270
DeltaFile
+8-10Makefile.inc1
+8-101 files

FreeBSD/ports df98c2fsecurity/p5-Crypt-OpenSSL-AES Makefile distinfo, security/p5-Crypt-OpenSSL-AES/files patch-t_00-openssl-version.t patch-t_09-key-size.t

security/p5-Crypt-OpenSSL-AES: Update 0.21 => 0.23

Changelog:
https://metacpan.org/release/TIMLEGGE/Crypt-OpenSSL-AES-0.23/source/Changes

- Use %%SSLBIN%% for substitution instead of SSLBIN.

PR:             294293
Sponsored by:   UNIS Labs
DeltaFile
+7-7security/p5-Crypt-OpenSSL-AES/files/patch-t_00-openssl-version.t
+6-3security/p5-Crypt-OpenSSL-AES/Makefile
+3-3security/p5-Crypt-OpenSSL-AES/files/patch-t_09-key-size.t
+3-3security/p5-Crypt-OpenSSL-AES/distinfo
+19-164 files

LLVM/project fe8a597clang/lib/ExtractAPI DeclarationFragments.cpp, clang/test/ExtractAPI type-alias.cpp

[clang][ExtractAPI] emit correct spelling for type aliases (#134007)

Previously, C++11 type aliases were serialized using "typedef"
regardless of the source spelling.
This checks if the TypedefNameDecl is actually a TypeAliasDecl and
corrects the spelling.
DeltaFile
+56-0clang/test/ExtractAPI/type-alias.cpp
+19-7clang/lib/ExtractAPI/DeclarationFragments.cpp
+1-1clang/test/Index/extract-api-cursor-cpp.cpp
+76-83 files

LLVM/project de6d86cflang/include/flang/Semantics openmp-utils.h, flang/lib/Semantics openmp-utils.cpp

[flang][OpenMP] Use OmpDirectiveSpecifications in helper functions (#190644)

This will make them more reusable, for example when processing APPLY
clause in the future.

Issue: https://github.com/llvm/llvm-project/issues/185287
DeltaFile
+45-54flang/lib/Semantics/openmp-utils.cpp
+3-3flang/include/flang/Semantics/openmp-utils.h
+48-572 files

LLVM/project 3f583d4llvm/lib/Transforms/Vectorize VPlanTransforms.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize find-last-iv-sinkable-expr.ll find-last-iv-sinkable-expr-epilogue.ll

[VPlan] Optimize FindLast of (binop %IV, live-in) by sinking. (#183911)

When we are finding the last occurrence of a value of an expression that
depends on an induction, we can vectorize this by just selecting the IV
and sinking the expression in the middle block

This follows one of @ayalz's suggestions during earlier discussions for
adding support for CAS/FindLast patterns.

This patch starts with the simplest case, where the selected value is a
simple binary expression of a wide IV and a loop-invariant operand.

This should always be profitable, as the current restriction to binary
operators ensures that the width of the wide IV matches the original
reduction width, we won't introduce any new, wider reduction phi
recipes, and remove the boolean reduction + the horizontal reduction in
the loop.

PR: https://github.com/llvm/llvm-project/pull/183911
DeltaFile
+480-32llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
+105-11llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+61-12llvm/test/Transforms/LoopVectorize/AArch64/find-last-iv-sinkable-expr-epilogue.ll
+24-30llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-epilogue.ll
+19-28llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
+20-3llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+709-1166 files

LLVM/project db3302dllvm/lib/CodeGen Rematerializer.cpp, llvm/unittests/CodeGen RematerializerTest.cpp

[CodeGen] Fix incorrect rematerialization order in rematerializer (#189485)

When rematerializing DAGs of registers wherein multiple paths exist
between some regsters of the DAG, it is possible that the
rematerialization determines an incorrect rematerialization order that
does not ensure that a register's dependencies are rematerialized before
itself; an invariant that is otherwise required.

This fixes that using a simpler recursive logic to determine a correct
rematerialization order that honors this invariant. A minimal unit test
is added that fails on the current implementation.
DeltaFile
+19-33llvm/lib/CodeGen/Rematerializer.cpp
+38-0llvm/unittests/CodeGen/RematerializerTest.cpp
+57-332 files

FreeNAS/freenas 29b382esrc/middlewared pyproject.toml

truenas_acme_utils and truenas_crypto_utils are type-safe now
DeltaFile
+1-1src/middlewared/pyproject.toml
+1-11 files

LLVM/project b79a6b5llvm/lib/Target/AMDGPU SIISelLowering.cpp

Review comments:
use input wave instruction for checks
DeltaFile
+7-7llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+7-71 files

LLVM/project b09f286llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] DPP wave reduction for long types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,113-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,079-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+72-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,264-3083 files

LLVM/project bac21bellvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fsub.ll llvm.amdgcn.reduce.fadd.ll

[AMDGPU] DPP wave reduction for double types - 2

Supported Ops: `fadd` and `fsub`
DeltaFile
+1,030-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+1,008-130llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+12-10llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,050-2703 files

LLVM/project 44172dallvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmax.ll llvm.amdgcn.reduce.fmin.ll

[AMDGPU] DPP wave reduction for double types - 1

Supported Ops: `fmin` and `fmax`
DeltaFile
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+1,112-234llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+27-13llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,251-4813 files

LLVM/project 1639f1fllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

[AMDGPU] DPP wave reduction for long types - 3

Supported Ops: `and`, `or`, `xor`
DeltaFile
+984-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+960-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+12-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2,916-3494 files

LLVM/project a8dff3ellvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.max.ll llvm.amdgcn.reduce.min.ll

[AMDGPU] DPP wave reduction for long types - 1

Supported Ops: `min`, `max`, `umin`, `umax`
DeltaFile
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+1,084-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+1,044-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+185-43llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4,441-4755 files

LLVM/project e129d09llvm/lib/Target/AMDGPU SIISelLowering.cpp

Avoid capturing the structed binding.
DeltaFile
+3-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-11 files

OpenBSD/src wz673OEsys/dev/pci/drm/amd/pm/swsmu amdgpu_smu.c, sys/dev/pci/drm/amd/pm/swsmu/smu11 smu_v11_0.c

   drm/amd/pm: fix amdgpu_irq enabled counter unbalanced on smu v11.0

   From Yang Wang
   5eeba3a7bf496d5c24379305d47933c6061e462a in linux-6.18.y/6.18.21
   e12603bf2c3d571476a21debfeab80bb70d8c0cc in mainline linux
VersionDeltaFile
1.12+6-1sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
1.28+5-2sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
+11-32 files

OpenBSD/src KqHLfobsys/dev/pci/drm/amd/pm/swsmu/smu13 smu_v13_0_6_ppt.c

   drm/amd/pm: Return -EOPNOTSUPP for unsupported OD_MCLK on smu_v13_0_6

   From Asad Kamal
   54c143028eb45baec385e8731eb42e22b9c25333 in linux-6.18.y/6.18.21
   2f0e491faee43181b6a86e90f34016b256042fe1 in mainline linux
VersionDeltaFile
1.9+1-1sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+1-11 files

FreeNAS/freenas e471a83.github/workflows mypy.yml

Use mypy from pip
DeltaFile
+0-3.github/workflows/mypy.yml
+0-31 files

OpenBSD/src LbhPX0zsys/dev/pci/drm/i915/display intel_plane.c

   drm/i915: Unlink NV12 planes earlier

   From Ville Syrjala
   70e2eb91cb6310a3508439f6f2539dfffa0abf77 in linux-6.18.y/6.18.21
   bfa71b7a9dc6b5b8af157686e03308291141d00c in mainline linux
VersionDeltaFile
1.2+9-2sys/dev/pci/drm/i915/display/intel_plane.c
+9-21 files