[HLSL] Implement the `fwidth` intrinsic for DXIL and SPIR-V target (#161378)
Adds the fwidth intrinsic for HLSL.
The DXIL path only requires modification to the hlsl headers.
The SPIRV path implements the OpFwidth builtin in Clang and instruction
selection for the OpFwidth instruction in LLVM.
Also adds shader stage tests to the ddx_coarse and ddy_coarse
instructions used by fwidth.
Closes #99120
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Co-authored-by: Alexander Johnston <alexander.johnston at amd.com>
qt6: updated to 6.10.1
As a patch release, Qt 6.10.1 does not introduce new features but delivers over
450 bug fixes, security updates, and enhancements on top of the Qt 6.10.1
release. For a detailed breakdown of the most significant changes, refer to
the Qt 6.10.1 release notes.
lang/spidermonkey78: Mark DEPRECATED
- Legacy version as there are more recent versions in the tree
- No more dependent ports remaining
- Set EXPIRATION_DATE 2025-12-20
deskutils/py-bugwarrior: Mark DEPRECATED
- Broken for more than 6 months
- Although upstream has minor activities they have not released any new
versions
- Set EXPIRATION_DATE 2025-12-31
If someone needs this port feel free to undeprecate and takeover
maintainership.
databases/redis82: New port
This is the redis 8.2.X branch of redis copied from databases/redis in
preparation for upgrading redis to redis 8.4.X branch.
[BOLT][BTI] Add MCPlusBuilder::addBTItoBBStart
This function contains most of the logic for BTI:
- it takes the BasicBlock and the instruction used to jump to it.
- then it checks if the first non-pseudo instruction is a sufficient
landing pad for the used call.
- if not, it generates the correct BTI instruction.
Also introduce the isBTIVariantCoveringCall helper to simplify the logic.
