LLVM/project 7c29ed5libc/src/__support/wctype/conversion/utils slice.h CMakeLists.txt

[libc][wctype] Upstream custom slice implementation from PtrHash-cc prototype to LLVM libc
DeltaFile
+112-0libc/src/__support/wctype/conversion/utils/slice.h
+11-0libc/src/__support/wctype/conversion/utils/CMakeLists.txt
+123-02 files

FreeBSD/ports 4730089mail Makefile, mail/opensmtpd-table-socketmap Makefile distinfo

mail/opensmtpd-table-socketmap: new port

The socketmap table addon for OpenSMTPD allows querying information through the
socketmap protocol.
DeltaFile
+26-0mail/opensmtpd-table-socketmap/Makefile
+3-0mail/opensmtpd-table-socketmap/distinfo
+2-0mail/opensmtpd-table-socketmap/pkg-descr
+1-0mail/Makefile
+32-04 files

LLVM/project db737bcclang/include/clang/Basic CodeGenOptions.def, clang/include/clang/Options Options.td

review: use function attr instead cl::opt flag
DeltaFile
+17-15llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll
+3-11llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+7-0clang/include/clang/Options/Options.td
+4-0clang/include/clang/Basic/CodeGenOptions.def
+2-0clang/lib/CodeGen/Targets/AMDGPU.cpp
+33-265 files

LLVM/project 88b77d5llvm/lib/Target/SPIRV SPIRVLegalizerInfo.cpp SPIRVPostLegalizer.cpp, llvm/test/CodeGen/SPIRV/legalization vector-arithmetic-6.ll load-store-global.ll

[SPIRV] Support non-constant indices for vector insert/extract (#172514)

This patch updates the legalization of spv_insertelt and spv_extractelt
to
handle non-constant (dynamic) indices. When a dynamic index is
encountered, the
vector is spilled to the stack, and the element is accessed via
OpAccessChain
(lowered from spv_gep).

This patch also adds custom legalization for G_STORE to scalarize vector
stores
and refines the legalization rules for G_LOAD, G_STORE, and
G_BUILD_VECTOR.

Fixes https://github.com/llvm/llvm-project/issues/170534
DeltaFile
+234-48llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+45-54llvm/test/CodeGen/SPIRV/legalization/vector-arithmetic-6.ll
+32-64llvm/test/CodeGen/SPIRV/legalization/load-store-global.ll
+66-0llvm/test/CodeGen/SPIRV/legalization/spv-extractelt-legalization.ll
+18-30llvm/test/CodeGen/SPIRV/llvm-intrinsics/matrix-transpose.ll
+40-3llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+435-1991 files not shown
+443-2107 files

FreeBSD/src 3b6615eusr.bin/netstat inet.c

netstat: fix a segfault with --libxo

Fix a segfault when printing the "protocol" field.  The field-format and
encoding-format were expecting different numbers of arguments.

Also, fix the width of the tcp-state field in encoded output.

PR:             292228
Fixes:          c2b08c13c20 netstat: add support for UDP-Lite endpoints
MFC after:      1 week
Sponsored by:   ConnectWise
Reviewed by:    tuexen, js, des
Differential Revision: https://reviews.freebsd.org/D54567
DeltaFile
+5-6usr.bin/netstat/inet.c
+5-61 files

FreeNAS/freenas e0aec72src/middlewared/middlewared/api/v25_10_0 core.py, src/middlewared/middlewared/api/v25_10_1 core.py

NAS-139180 / 25.10.2 / Change error on core.bulk op to LongString (by anodos325) (#17957)

Depending on the circumstances and exact arguments passed to a method,
the operation may fail with a detail python traceback that requires a
LongString for the error message.

Original PR: https://github.com/truenas/middleware/pull/17956

Co-authored-by: Andrew Walker <awalker at ixsystems.com>
DeltaFile
+1-1src/middlewared/middlewared/api/v25_10_0/core.py
+1-1src/middlewared/middlewared/api/v25_10_1/core.py
+1-1src/middlewared/middlewared/api/v25_10_2/core.py
+3-33 files

LLVM/project c65c6aellvm/test/CodeGen/AArch64 arm64-cvtf-simd-itofp.ll

fixup! [AArch64][llvm] Add codegen for simd fpcvt intrinsics

Use @llvm.experimental.constrained.* to test strict nodes
DeltaFile
+12-12llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
+12-121 files

LLVM/project 758ded1llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

review: move hardwareLimit inside AMDGPUBaseInfo
DeltaFile
+36-46llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+18-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+17-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+71-463 files

LLVM/project e61a150llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

Update SIInsertWaitcnts.cpp

Co-authored-by: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
DeltaFile
+1-1llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+1-11 files

LLVM/project 52a1048llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

fix: resolve issue after rebase
DeltaFile
+0-15llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+0-151 files

LLVM/project fa1ea58llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

Update SIInsertWaitcnts.cpp

Co-authored-by: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
DeltaFile
+1-1llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+1-11 files

LLVM/project 8aa920allvm/test/CodeGen/AMDGPU expand-waitcnt-profiling.ll

add more test
DeltaFile
+225-0llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll
+225-01 files

LLVM/project 92958dcllvm/test/CodeGen/AMDGPU expand-waitcnt-profiling.ll

add run line for diff GPU Gen and counter types
DeltaFile
+567-203llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll
+567-2031 files

LLVM/project 7f1d01cllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU expand-waitcnt-profiling.ll

skip expanding out-of-order events
DeltaFile
+143-20llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll
+42-12llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+185-322 files

LLVM/project 734a367llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

Address reviewer feedback: fix getWaitCountMax and reduce code duplication

- Fix getWaitCountMax() to use correct bitmasks based on architecture:
  - Pre-GFX12: Use getVmcntBitMask/getLgkmcntBitMask for LOAD_CNT/DS_CNT
  - GFX12+: Use getLoadcntBitMask/getDscntBitMask for LOAD_CNT/DS_CNT
- Refactor repetitive if-blocks for LOAD_CNT, DS_CNT, EXP_CNT into
  a single loop using getCounterRef helper function
- Fix X_CNT to return proper getXcntBitMask(IV) instead of 0
DeltaFile
+18-32llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+18-321 files

LLVM/project c7c5259lldb/source/Plugins/Language/CPlusPlus MsvcStlSpan.cpp CPlusPlusLanguage.cpp, lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/span TestDataFormatterStdSpan.py

[LLDB] Add MSVC STL span formatter (#173053)

`std::span` didn't have a formatter for MSVC's STL yet. The type is
quite useful in C++ 20, so this PR adds a formatter for it.

Since the formatter is new, I made it work with both DWARF and PDB from
the start.
DeltaFile
+134-0lldb/source/Plugins/Language/CPlusPlus/MsvcStlSpan.cpp
+24-5lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/span/TestDataFormatterStdSpan.py
+17-9lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
+6-0lldb/source/Plugins/Language/CPlusPlus/MsvcStl.h
+1-0lldb/source/Plugins/Language/CPlusPlus/CMakeLists.txt
+182-145 files

LLVM/project 03e0c1ellvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU expand-waitcnt-profiling.ll

[AMDGPU] Add -amdgpu-expand-waitcnt-profiling option for PC-sampling profiling
DeltaFile
+230-0llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll
+172-22llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+402-222 files

LLVM/project 82ba5f6llvm/lib/Target/SPIRV SPIRVRegularizer.cpp, llvm/test/CodeGen/SPIRV icmp-i1.ll

[SPIRV] Lower i1 comparisons to logical operations in regularizer pass.

UGT, UGE, ULT, ULE, SGT, SGE, SLT, SLE predicates for i1 types are now
lowered to equivalent logical operations (AND, OR, NOT) to ensure
valid SPIR-V, since SPIR-V boolean types only support logical operations.
DeltaFile
+132-0llvm/test/CodeGen/SPIRV/icmp-i1.ll
+73-0llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
+205-02 files

LLVM/project 2e7c3dallvm/lib/Target/SPIRV SPIRVRegularizer.cpp

[review] Take name.
DeltaFile
+1-1llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
+1-11 files

LLVM/project 632d077llvm/lib/Target/SPIRV SPIRVRegularizer.cpp

[review] Use IRBuilder and inline call.
DeltaFile
+7-21llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
+7-211 files

LLVM/project a2ae83bllvm/lib/Target/SPIRV SPIRVRegularizer.cpp

[review] Take name.
DeltaFile
+1-1llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
+1-11 files

LLVM/project 757f57cllvm/lib/Target/SPIRV SPIRVRegularizer.cpp

[review] Use IRBuilder and inline call.
DeltaFile
+7-21llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
+7-211 files

OPNSense/core 6c325c9src/opnsense/mvc/app/controllers/OPNsense/Hostdiscovery/forms general.xml

interfaces: adjust promisc hostwatch help text
DeltaFile
+1-1src/opnsense/mvc/app/controllers/OPNsense/Hostdiscovery/forms/general.xml
+1-11 files

FreeNAS/freenas 6956d02src/middlewared/middlewared main.py, src/middlewared/middlewared/api/base/server/ws_handler rpc.py

NAS-139199 / 25.10.2 / Fix Futures resource leak in run_coroutine_threadsafe (by yocalebo) (#17969)

This fixes a leak whereby we're not tracking `Future` objects correctly.
This means they're never cleaned up and overtime they'll build up on the
main event loop.

I confirmed this behavior by running `midclt call interface.query` in a
tight loop on a box and then connecting a remote pdb session with the
middleware process. It was designed to "overrun" the main event loop,
what it did was build up a queue that never cleared itself. There were
~2.3k PENDING futures in our thread pool.

This does 2 things:
1. creates a `run_coroutine_threadsafe` wrapper that properly tracks the
futures so they're cleaned up
2. logs any exceptions that may occur in these "fire and forget"
futures.

Original PR: https://github.com/truenas/middleware/pull/17967

Co-authored-by: caleb <yocalebo at gmail.com>
DeltaFile
+35-0src/middlewared/middlewared/utils/threading.py
+3-2src/middlewared/middlewared/apps/webshell_app.py
+3-2src/middlewared/middlewared/apps/websocket_app.py
+2-1src/middlewared/middlewared/main.py
+2-1src/middlewared/middlewared/plugins/failover_/reboot.py
+2-1src/middlewared/middlewared/api/base/server/ws_handler/rpc.py
+47-76 files

FreeBSD/ports 602ce26audio/mumble Makefile distinfo

audio/mumble: Fix build on aarch64

pkg-static: Unable to access file /wrkdirs/usr/ports/audio/mumble/work/stage/usr/local/lib/mumble/libmumbleoverlay.so:No such file or directory
pkg-static: Unable to access file /wrkdirs/usr/ports/audio/mumble/work/stage/usr/local/lib/mumble/libmumbleoverlay.so.1.5.0:No such file or directory

Upstream issue:
https://github.com/mumble-voip/mumble/issues/6971
https://github.com/mumble-voip/mumble/pull/6978

Reported by:    pkg-fallout
Tested by:      fuz
DeltaFile
+6-0audio/mumble/Makefile
+3-1audio/mumble/distinfo
+9-12 files

LLVM/project e5623b1llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/AMDGPU div_v2i128.ll fptoi.i128.ll

Revert "SelectionDAG: Do not propagate divergence through glue (#174766)"

This reverts commit 47a0d0e42832558f999b149b22cfd48c46ef2a57.

Reverted due to test failures in LLVM_ENABLE_EXPENSIVE_CHECKS builds.
DeltaFile
+328-336llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+256-262llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+200-204llvm/test/CodeGen/AMDGPU/rem_i128.ll
+163-167llvm/test/CodeGen/AMDGPU/div_i128.ll
+22-5llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+3-4llvm/test/CodeGen/AMDGPU/dag-divergence.ll
+972-9786 files

FreeNAS/freenas d5fe122src/middlewared/middlewared main.py, src/middlewared/middlewared/api/base/server/ws_handler rpc.py

fix cherry-pick
DeltaFile
+35-0src/middlewared/middlewared/utils/threading.py
+3-2src/middlewared/middlewared/apps/webshell_app.py
+3-2src/middlewared/middlewared/apps/websocket_app.py
+2-1src/middlewared/middlewared/main.py
+2-1src/middlewared/middlewared/plugins/failover_/reboot.py
+2-1src/middlewared/middlewared/api/base/server/ws_handler/rpc.py
+47-76 files

LLVM/project 9315747libclc CMakeLists.txt

[libclc] Initial support for cross-compiling OpenCL libraries (#174022)

Summary:
The other GPU enabled libraries, (openmp, flang-rt, compiler-rt, libc,
libcxx, libcxx-abi) all support builds through a runtime cross-build. In
these builds we use a separate CMake build that cross-compiles to a
single target.

This patch provides basic support for this with the `libclc` libraries.
Changes include adding support for the more standard GPU compute triples
(amdgcn-amd-amdhsa, nvptx64-nvidia-cuda) and building only one target in
this mode.

Some things left to do:

This patch does not change the compiler invocations, this method would
allow us to use standard CMake routines but this keeps it minimal.

The prebuild support is questionable and doesn't fit into this scheme

    [3 lines not shown]
DeltaFile
+10-2libclc/CMakeLists.txt
+10-21 files

FreeBSD/src d07198frelease Makefile, release/tools openstack.conf vagrant.conf

release: stop disabling sendmail

sendmail is already disabled by default everywhere since 14.0

MFC After:      1 week
Approved by:    emaste (re)
Reviewed by:    emaste (re)
Differential Revision:  https://reviews.freebsd.org/D54575
DeltaFile
+0-6release/tools/openstack.conf
+0-6release/tools/vagrant.conf
+0-4release/tools/arm.subr
+0-3release/Makefile
+0-1release/tools/oracle.conf
+0-205 files

LLVM/project d45d8cbllvm/lib/Frontend/OpenMP OMPIRBuilder.cpp, offload/test/offloading/fortran default-mapper-nested-derived-type.f90

[OpenMP][OMPIRBuilder] Attach `Attribute::OptimizeNone` to user-defined (and default) mappers

Disabling opts for user-defined mappers since, in some cases (see
`default-mapper-nested-derived-type.f90`), some optimizations and
instrumentations causes runtime crashes on the host. In particular, the
following:
- ths `X86DAGToDAGISel` pass and
- `OptNoneInstrumentation` (TODO zoom in further on passes that use this
instrumention object to find out the exact pass(es) causing the crash).

I couldn't find a way to fine-tune this for only the problematic passes
yet. I am very reluctant to do this, please let me know if there are
better solutions.
DeltaFile
+34-0offload/test/offloading/fortran/default-mapper-nested-derived-type.f90
+9-0llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+43-02 files