LLVM/project 0cf3b17offload/languages/kernel/include LanguageUtils.h, offload/languages/kernel/src LanguageRuntime.cpp LanguageLaunch.cpp

add blocking semantics to LaunchKernel and Memcpy
DeltaFile
+131-0offload/test/offloading/CUDA/blocking_stream_semantics.cu
+125-0offload/test/offloading/HIP/blocking_stream_semantics.hip
+47-4offload/languages/kernel/include/LanguageUtils.h
+17-3offload/languages/kernel/src/LanguageLaunch.cpp
+10-5offload/languages/kernel/src/LanguageRuntime.cpp
+4-2offload/test/offloading/HIP/stream_api.hip
+334-144 files not shown
+343-1810 files

LLVM/project f39d581libc/include CMakeLists.txt signal.yaml, libc/include/llvm-libc-macros/linux signal-macros.h

[libc] Minor fixes/additions to signal.h header. (#217469)

* Fix a typo for si_overrun field inside siginfo_t struct (it is
accessible via `si_overrun` macro, and names should match)
* Add `sig_t` type which is used in BSD for signal handler function.
It's identical to GNU's `sighandler_t`, and glibc provides both. Clarify
this in their YAML entries.
* Add more Linux-specific `SI_*` values.
DeltaFile
+20-0libc/include/llvm-libc-types/sig_t.h
+5-0libc/include/signal.yaml
+4-0libc/include/llvm-libc-macros/linux/signal-macros.h
+1-1libc/include/llvm-libc-types/siginfo_t.h
+1-0libc/include/llvm-libc-types/CMakeLists.txt
+1-0libc/include/CMakeLists.txt
+32-16 files

LLVM/project 5dff3feclang/include/clang/Sema SemaSwift.h, clang/lib/Sema SemaDecl.cpp SemaSwift.cpp

[clang] Redeclarations should inherit all unique SwiftAttrs (#217187)

SwiftAttrs are inherited by redeclarations but only the first attribute
was inherited, the rest was dropped. This behavior is confusing and
inconsistent that lead to some subtle bugs consuming these annotations.
This PR makes sure every instance with a unique argument is inherited.

Co-authored-by: Gabor Horvath <gaborh at apple.com>
DeltaFile
+70-0clang/test/AST/attr-swift_attr-redeclaration.c
+10-0clang/lib/Sema/SemaSwift.cpp
+3-0clang/include/clang/Sema/SemaSwift.h
+2-0clang/lib/Sema/SemaDecl.cpp
+85-04 files

LLVM/project 7a9b0c1llvm/lib/Transforms/Scalar LoopFuse.cpp, llvm/test/Transforms/LoopFusion guarded_peel.ll different_guards.ll

[LoopFusion]  Do not peel guarded loops to enable fusion (#217379)

Loop fusion currently tries to peel guarded loops to expose fusion opportunity.
The logic has a bug: Once we confirm two loops have small difference in
their iteration count and are eligible for peeling, we blindly allow them to
have different guards. The problem is that in some cases, conditions of the
loop guards have nothing to do with the loop iteration count. This is more
likely to be the case when a loop has constant iteration count. At the moment
fusion allows peeling only when both loops have constant iteration counts.
DeltaFile
+63-0llvm/test/Transforms/LoopFusion/different_guards.ll
+13-36llvm/test/Transforms/LoopFusion/guarded_peel.ll
+15-14llvm/lib/Transforms/Scalar/LoopFuse.cpp
+91-503 files

LLVM/project e45fa77lldb/unittests/Target TargetAPIMutexTest.cpp

[lldb][test] Unlock the mutex completely before exiting the test (#217466)

This test fails with hardened libcxx otherwise.

Fixes #212872

---------

Co-authored-by: Med Ismail Bennani <ismail at bennani.ma>
DeltaFile
+9-0lldb/unittests/Target/TargetAPIMutexTest.cpp
+9-01 files

LLVM/project 851ff0emlir/lib/Dialect/X86/Transforms MoveAccumulatorForContractLoop.cpp, mlir/test/Dialect/X86 move-acc-for-contract-loop.mlir

[MLIR][X86] Track accumulator rewrites (#217477)

Route accumulator and result-user operand updates through
PatternRewriter. This lets greedy rewrite listeners observe every
in-place mutation.

Assisted-by: Codex
DeltaFile
+4-2mlir/lib/Dialect/X86/Transforms/MoveAccumulatorForContractLoop.cpp
+0-3mlir/test/Dialect/X86/move-acc-for-contract-loop.mlir
+4-52 files

NetBSD/pkgsrc-wip bc42ecbgrafana distinfo go-modules.mk, grafana/patches patch-go.mod patch-.._k8s.io_apiserver_pkg_server_options_serving__unix.go

grafana: carry over illumos fix from www/

... but add the patch locally here rather than
pointing at jperkin's fork for maintainability.
DeltaFile
+1,039-1,046grafana/go-modules.mk
+46-0grafana/patches/patch-.._k8s.io_apiserver_pkg_server_options_serving__noportreuse.go
+4-23grafana/distinfo
+16-7grafana/patches/patch-go.sum
+10-0grafana/patches/patch-.._k8s.io_apiserver_pkg_server_options_serving__unix.go
+3-1grafana/patches/patch-go.mod
+1,118-1,0771 files not shown
+1,120-1,0777 files

LLVM/project 3b44108clang/lib/CodeGen CGBuiltin.cpp

Fix typo in assert string
DeltaFile
+1-1clang/lib/CodeGen/CGBuiltin.cpp
+1-11 files

LLVM/project e21cfc0llvm/include/llvm/Analysis LibcallLoweringInfo.h, llvm/include/llvm/CodeGen LibcallLoweringInfo.h

Analysis: Move LibcallLoweringInfo from CodeGen to Analysis (#210322)

Middle end passes need to be able to reason about library call
availability and potentially emit them without depending on codegen.
TargetLibraryInfo already lives in Analysis, and this is a step towards
the eventual merger. For now this is a mostly mechanical move, type
erasing the reference to TargetSubtargetInfo.

The per-subtarget customization (TargetSubtargetInfo::initLibcallLoweringInfo)
is inverted into a caller-supplied function_ref, so the Analysis types
carry no CodeGen/TargetSubtargetInfo reference. The module map is keyed on 
an opaque erased pointer. CodeGen continues looking up based on the subtarget.

It is not yet in a state where it is usable from middle end passes; that
will come later. In principle we should be able to write arbitrary rules based 
on a function's ABI attributes for which calls can be used.

Co-authored-by: Claude (Claude Opus 4.8) <noreply at anthropic.com>
DeltaFile
+160-0llvm/include/llvm/Analysis/LibcallLoweringInfo.h
+13-114llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
+23-35llvm/lib/CodeGen/LibcallLoweringInfo.cpp
+49-0llvm/lib/Analysis/LibcallLoweringInfo.cpp
+5-5llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp
+5-5llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
+255-15915 files not shown
+276-17321 files

Illumos/gate 9381e2cusr/src/uts/common/io/cxgbe/t4nex cudbg_lib.c

18363 cxgbetool cudbg --collect rss panics host
Reviewed by: Robert Mustacchi <rm at fingolfin.org>
Reviewed by: Andy Fiddaman <illumos at fiddaman.net>
Reviewed by: Kyle Simpson <kyle at oxide.computer>
Approved by: Dan McDonald <danmcd at edgecast.io>
DeltaFile
+1-1usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
+1-11 files

LLVM/project c38d6cellvm/lib/Transforms/Vectorize VPlanPredicator.cpp, llvm/test/Transforms/LoopVectorize div-exact.ll uniform-blend.ll

[VPlan][Predicator] Preserve some uniform control flow

Implements "Partial Control-Flow Linearization" by Simon Moll and
Sebastian Hack. Does **NOT** improve predication/masking yet, so
applicability is artificially narrowed, only some uniform branches are
preserved. In particular, the following is left for future PRs:

* Block masks still contains now-unnecessary term for the preserved
  uniform branches.
* Mixed blends/phis aren't supported yet. Detecting where they would be
  necessary is as complex as implementing proper support (which would
  need either Luke's `reconstructSSA` or Iterated Dominance Frontier),
  so we also limit it to a trivial/structured CFG where there's only
  single block where those would need to be inserted.

I think even the current version might be enough to start implementing
an alternative to https://github.com/llvm/llvm-project/pull/141900 (see
BOSCC in the paper).
DeltaFile
+81-45llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
+107-3llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
+45-38llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
+32-8llvm/test/Transforms/LoopVectorize/uniform-blend.ll
+18-10llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-multi-block.ll
+14-6llvm/test/Transforms/LoopVectorize/div-exact.ll
+297-11015 files not shown
+398-13421 files

LLVM/project 044bb98llvm/test/Transforms/LoopVectorize/VPlan predicator.ll

Create actual test functions (AI-assisted)
DeltaFile
+478-25llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
+478-251 files

LLVM/project 342af1bllvm/test/Transforms/LoopVectorize/VPlan predicator.ll

Generate CHECKs
DeltaFile
+1,101-1llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
+1,101-11 files

LLVM/project ae9ee79llvm/test/Transforms/LoopVectorize/VPlan predicator.ll

Add `*_no_phi` versions
DeltaFile
+623-0llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
+623-01 files

LLVM/project df7ca0allvm/lib/Transforms/Vectorize VPlanPredicator.cpp, llvm/test/Transforms/LoopVectorize predicator.ll

Implement non-uniform part of partial linearization algorithm
DeltaFile
+92-92llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
+104-17llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
+4-4llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
+3-3llvm/test/Transforms/LoopVectorize/predicator.ll
+203-1164 files

LLVM/project 7e8164cllvm/test/Transforms/LoopVectorize/VPlan predicator.ll

Predicator tests for uniform control flow preservation
DeltaFile
+168-0llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
+168-01 files

LLVM/project 8e74b3fllvm/lib/Transforms/Vectorize VPlanPredicator.cpp

[NFC][VPlan] Move `introduceMasksAndLinearize` into a `VPPredicator`'s method

To reduce diff in the next PR.
DeltaFile
+15-10llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
+15-101 files

LLVM/project adb5956clang/lib/CodeGen CodeGenModule.h CodeGenSYCL.cpp, clang/test/CodeGenSYCL offload-include-binary.cpp

[clang][SYCL] Align device binary (un)registration with CUDA/HIP/OpenMP (#217173)

The SYCL offload wrapper still registers and unregisters the device
binary the way the offloading runtimes did before 421085fd740d (#86830):
a constructor and a destructor, both at priority 1. That commit moved
OpenMP/CUDA/HIP off a destructor and priority 1, and the reasons apply
to SYCL equally.

With no destructor left to emit, wrapSYCLBinaries() only ever hands back
one function, so shrink its out-parameter to a single Function *. This
also lets CodeGenModule::Release() emit the SYCL constructor next to the
CUDA one instead of ahead of registerGlobalDtorsWithAtExit(), where it
had to sit only because AddGlobalDtor() additions are dropped after that
call.

co-authored by claude
DeltaFile
+19-10llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
+10-8clang/test/CodeGenSYCL/offload-include-binary.cpp
+8-8llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
+6-9clang/lib/CodeGen/CodeGenModule.cpp
+6-7clang/lib/CodeGen/CodeGenSYCL.cpp
+3-3clang/lib/CodeGen/CodeGenModule.h
+52-452 files not shown
+55-478 files

FreeBSD/ports 274fc92x11/waveterm Makefile

x11/waveterm: Bump port revision after electron41 update (5b86dcd2f377)
DeltaFile
+1-1x11/waveterm/Makefile
+1-11 files

FreeBSD/ports 5b86dcddevel/electron41 Makefile.version distinfo, devel/electron41/files patch-electron_spec_api-protocol-spec.ts

devel/electron41: Update to 41.10.6

Changelog: https://github.com/electron/electron/releases/tag/v41.10.6

Reported by:    GitHub (watch releases)
DeltaFile
+7-7devel/electron41/distinfo
+2-2devel/electron41/files/patch-electron_spec_api-protocol-spec.ts
+1-1devel/electron41/Makefile.version
+10-103 files

LLVM/project 3a7967cmlir/lib/Dialect/EmitC/Transforms WrapFuncInClass.cpp, mlir/test/Dialect/EmitC wrap-func-in-class.mlir

[MLIR][EmitC] Rewrite globals before moving function body (#217474)

WalkPatternRewriter only permits erasing matched operations or their
descendants. Replace get_global operations while they still belong to
the matched function before transferring its body into the new class
method.

Assisted-by: Codex
DeltaFile
+9-8mlir/lib/Dialect/EmitC/Transforms/WrapFuncInClass.cpp
+0-2mlir/test/Dialect/EmitC/wrap-func-in-class.mlir
+9-102 files

LLVM/project feb882dclang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/Driver cuda-flush-denormals-to-zero.cu amdgpu-xnack-sramecc-flags.c

clang/AMDGPU: Stop passing redundant -target-cpu to cc1

Now that the exact target is encoded in the triple's subarch field,
-target-cpu is redundant. This avoids polluting the resultant IR with
unwanted "target-cpu" attributes. The net result is the desired codegen
when compiling libraries for a major subarch and linking it into a
program compiled for a specific arch. e.g., compiling for "gfx9-generic"
would pollute the IR with "target-cpu"="gfx9-generic", so codegen
would ultimately be performed for the generic target even after
linking into the concrete gfx9 cpu. The specialization will now be
achieved by merging the triples without the linker or optimization
passes needing to fixup function attributes.
DeltaFile
+62-62clang/test/Driver/amdgpu-mcpu.cl
+26-26clang/test/Driver/hip-sanitize-options.hip
+12-16clang/test/Driver/hip-rdc-device-only.hip
+18-6clang/lib/Driver/ToolChains/CommonArgs.cpp
+10-10clang/test/Driver/amdgpu-xnack-sramecc-flags.c
+6-6clang/test/Driver/cuda-flush-denormals-to-zero.cu
+134-12626 files not shown
+188-20732 files

LLVM/project 05c3a88llvm/include/llvm/TargetParser AMDGPUTargetParser.h, llvm/lib/Target/AMDGPU AMDGPUTargetParser.td GCNProcessors.td

AMDGPU: Start using subarch in attributor instead of subtarget

Avoid querying the subtarget for functions when the relevant
properties are known from the triple. The various subtarget
group size functions should also be decoupled from the subtarget,
but those are trickier to untangle.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+26-18llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+9-9llvm/lib/Target/AMDGPU/GCNProcessors.td
+15-1llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+10-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+2-0llvm/lib/Target/AMDGPU/AMDGPUTargetParser.td
+62-285 files

LLVM/project 6943454clang/lib/Driver ToolChain.cpp, clang/test/Driver amdgpu-subarch-library-paths.cl

Add subarch fallback to getArchSpecificLibPaths
DeltaFile
+25-0clang/test/Driver/amdgpu-subarch-library-paths.cl
+12-4clang/lib/Driver/ToolChain.cpp
+0-0clang/test/Driver/Inputs/resource_dir_amdgpu_legacy_triple/lib/amdgcn-amd-amdhsa/libclang_rt.builtins.a
+37-43 files

LLVM/project 87a055fclang/lib/Driver Driver.cpp, clang/lib/Driver/ToolChains CommonArgs.cpp

clang: Start using new amdgpu subarch triples

Fixup invocations using --target=amdgcn + -mcpu to introduce
the subarch in the triple.

For offload toolchains, a single toolchain is constructed for the
top level amdgpu architecture, and the effective triple is used for
target specific tool invocations.

The specifics of the resource directory layout are tbd. This does
try to find resources in the subarch named directory. The paths
are searched at toolchain creation time, so that does not work
when there are multiple subarches.

Fixes #154925
DeltaFile
+59-59clang/test/Driver/offload-arch-translation-amdgpu.cu
+43-43clang/test/Driver/hip-phases.hip
+33-33clang/test/Driver/hip-binding.hip
+48-14clang/lib/Driver/ToolChains/CommonArgs.cpp
+43-12clang/lib/Driver/Driver.cpp
+54-0clang/test/CodeGen/amdgpu-builtin-processor-is-subarch.c
+280-161105 files not shown
+993-498111 files

LLVM/project 935bfc7clang/include/clang/CIR/Dialect/IR CIRTypes.td, clang/lib/CIR/CodeGen CIRGenRecordLayoutBuilder.cpp

[CIR] Mark bit-field access units as their own member kinds (#216864)

A bit-field access unit is only as wide as the compiler needs it to be,
which can be narrower than the type the bit-fields were declared with.
Nothing in the record type says so. The unit just gets `data`, or
`empty` when none of its bit-fields are named, and an ordinary field
gets those same marks.

That makes `struct { long long x : 32; }` and `struct { unsigned x; }`
look identical here. Classic CodeGen tells them apart and coerces the
first to `i64`, the second to `i32`. It reads the declared type, where
the bit-field still leaves user data past bit 32.

The fix is to give a unit its own marks, `bitfield` and
`empty_bitfield`. Nothing reads them yet, and no record's emptiness
answer changes. The next PR records a zero-width bit-field, which the
marks miss too, and pad-aware classification can then use both.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+82-0clang/test/CIR/CodeGen/no-unique-address.cpp
+33-15clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+27-13clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
+30-8clang/test/CIR/CodeGen/record-member-kinds.c
+13-11clang/test/CIR/CodeGen/record-member-kinds.cpp
+21-0clang/unittests/CIR/RecordMemberKindTest.cpp
+206-4713 files not shown
+271-7819 files

OpenBSD/ports zOOTDWtnet/miniflux Makefile modules.inc, net/miniflux/pkg miniflux.rc

   Update to miniflux-2.3.3

   While there, update with miniflux.rc with:

   - By default miniflux logs to standard error, so setting the daemon
     output will hook it up with syslogd out of the box.

   - Service now supports reloading. It's only for reloading TLS
     certificates, not log files. If you wish to do anything extra with
   your log files, you'll have to do it with syslogd by setting the
   logging back to default as mentioned in the previous paragraph.

   From Igor Zornik (maintainer)
VersionDeltaFile
1.31+78-110net/miniflux/distinfo
1.29+26-37net/miniflux/modules.inc
1.35+2-2net/miniflux/Makefile
1.3+1-1net/miniflux/pkg/miniflux.rc
+107-1504 files

LLVM/project aacef70clang/lib/CIR/Lowering CIRPasses.cpp, clang/test/CIR/CodeGen complex-mul-div.cpp complex-compound-assignment.cpp

[CIR] Move LoweringPrepare before callconv lowering (#216498)

Complex division returns a wrong imaginary part. CIR declares `__divsc3`
as returning `{ float, float }` where classic CodeGen coerces the return
to `<2 x float>`, so the caller reads the two halves out of two
registers while the callee packs both into one. Dividing 3+4i by 1+2i
gives 2.2 and 4.0 instead of 2.2 and -0.4, with no diagnostic. The
helper call is synthesized by LoweringPrepare, which runs after the
calling-convention pass, so it is never classified.

Moving LoweringPrepare before CallConvLowering lets the classifier see
everything the pass emits rather than complex alone. Complex mul and div
are the only calls it synthesizes today that need coercion, but anything
emitted there later is lowered properly too.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+81-0clang/test/CIR/CodeGen/complex-libcall-abi.c
+51-0clang/test/CIR/CodeGen/complex-libcall-abi-global-init.cpp
+28-8clang/test/CIR/CodeGen/complex-compound-assignment.cpp
+22-7clang/test/CIR/CodeGen/complex-mul-div.cpp
+6-2clang/lib/CIR/Lowering/CIRPasses.cpp
+188-175 files

OpenBSD/ports GNSsRIWwww/minify modules.inc Makefile

   Update to minify-2.24.17

   From Igor Zornik (maintainer)
VersionDeltaFile
1.6+14-14www/minify/distinfo
1.5+3-3www/minify/modules.inc
1.6+3-3www/minify/Makefile
+20-203 files

OpenBSD/ports cbGWdXzsysutils/fzf modules.inc Makefile

   Update to fzf-0.74.3

   From Laurent Cheylus (maintainer)
VersionDeltaFile
1.54+6-6sysutils/fzf/distinfo
1.23+1-1sysutils/fzf/modules.inc
1.63+1-1sysutils/fzf/Makefile
+8-83 files