FreeBSD/doc 603eb0awebsite/data/ru/news news.toml

website/ru: Update data/ru/news/news.toml

Sync to EN 93638e3a34527b82b05221edf993c55761e77a7c
DeltaFile
+13-1website/data/ru/news/news.toml
+13-11 files

FreeBSD/ports b4e7cd4finance/odoo pkg-plist

finance/odoo: Fix pkg-plist with non-default python

Incorrect auto-substitution - "311" was replaced with "%%PYTHON_SUFFIX%%".

PR:             294248
Approved by:    blanket (fix build)
Sponsored by:   UNIS Labs
MFH:            2026Q2

(cherry picked from commit ea944aa0d4683c78c94b7bd1ae883d92d5e2795d)
DeltaFile
+1-1finance/odoo/pkg-plist
+1-11 files

FreeBSD/src dc752c2. RELNOTES

RELNOTES: Make an entry for supporting an NFSv4 root fs
DeltaFile
+6-0RELNOTES
+6-01 files

FreeBSD/ports ea944aafinance/odoo pkg-plist

finance/odoo: Fix pkg-plist with non-default python

Incorrect auto-substitution - "311" was replaced with "%%PYTHON_SUFFIX%%".

PR:             294248
Approved by:    blanket (fix build)
Sponsored by:   UNIS Labs
MFH:            2026Q2
DeltaFile
+1-1finance/odoo/pkg-plist
+1-11 files

OPNSense/core 267f5a4src/etc/inc/plugins.inc.d radvd.inc, src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms dialogEntry.xml

radvd: allow user controlled hop limit

PR: #9688
DeltaFile
+10-0src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms/dialogEntry.xml
+8-1src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.xml
+1-0src/etc/inc/plugins.inc.d/radvd.inc
+19-13 files

LLVM/project c7c9025bolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp CMakeLists.txt, bolt/unittests/Core MCPlusBuilder.cpp

[BOLT][AArch64] Optimize the mov-imm-to-reg operation (#189304)

On AArch64, logical immediate instructions are used to encode some
special immediate values. And even at `-O0` level, the AArch64 backend
would not choose to generate 4 instructions (movz, movk, movk, movk) for
moving such a special value to a 64-bit regiter.

For example, to move the 64-bit value `0x0001000100010001` to `x0`, the
AArch64 backend would not choose a 4-instruction-sequence like
```
movz x0, 0x0001
movk x0, 0x0001, lsl 16
movk x0, 0x0001, lsl 32
movk x0, 0x0001, lsl 48
```
Actually, the AArch64 backend would choose to generate one instruction
```
mov x0, 0x0001000100010001
```

    [10 lines not shown]
DeltaFile
+97-0bolt/unittests/Core/MCPlusBuilder.cpp
+63-24bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+1-0bolt/lib/Target/AArch64/CMakeLists.txt
+161-243 files

LLVM/project 5baec2cbolt/include/bolt/Profile DataAggregator.h, bolt/lib/Profile DataAggregator.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+86-3bolt/lib/Profile/DataAggregator.cpp
+6-0bolt/include/bolt/Profile/DataAggregator.h
+92-32 files

LLVM/project e382a95llvm/test/Transforms/LoopVectorize/WebAssembly memory-interleave.ll, llvm/test/Transforms/LoopVectorize/X86/CostModel interleaved-load-i8-stride-8.ll interleaved-load-i16-stride-8.ll

[LV] Update remaining tests to use VPlan cost output (NFC). (#190038)

Move remaining tests checking legacy cost output to check the VPlan's
cost model output.

In some cases, checks become much more compact (checking a single
interleave group cost vs checking the individual members which all have
the group's cost). In some cases, auto-generation consistently checks
all relevant VFs.

PR: https://github.com/llvm/llvm-project/pull/190038
DeltaFile
+1,157-452llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
+123-284llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll
+123-252llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
+111-248llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll
+111-248llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll
+129-212llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll
+1,754-1,696109 files not shown
+10,338-7,066115 files

LLVM/project 88a78f6clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/CodeGen CIRGenClass.cpp

[CIR] Add support for variable sized array new. (#190656)

This change adds support for array new with variable size. This required
extending the cir.array.ctor operation to accept a value for the size
and a direct pointer to the element size instead of a pointer to an
array.

Assisted-by: Cursor / claude-4.6-opus-high
Assisted-by: Cursor / composer-2-fast
DeltaFile
+218-0clang/test/CIR/IR/invalid-array-structor.cir
+146-0clang/test/CIR/CodeGen/new.cpp
+49-45clang/lib/CIR/CodeGen/CIRGenClass.cpp
+55-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+31-3clang/include/clang/CIR/Dialect/IR/CIROps.td
+20-4clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+519-521 files not shown
+538-527 files

FreeBSD/ports 919c360misc/py-vllm Makefile, misc/py-vllm/files patch-cmake_cpu__extension.cmake patch-vllm_platforms_cpu.py

misc/py-vllm: New port: High-throughput and memory-efficient LLM inference engine
DeltaFile
+109-0misc/py-vllm/Makefile
+78-0misc/py-vllm/files/patch-cmake_cpu__extension.cmake
+42-0misc/py-vllm/files/patch-vllm_platforms_cpu.py
+35-0misc/py-vllm/files/patch-vllm_distributed_parallel__state.py
+29-0misc/py-vllm/files/patch-vllm_platforms_____init____.py
+26-0misc/py-vllm/files/patch-pyproject.toml
+319-06 files not shown
+377-012 files

FreeBSD/ports 3a02618graphics Makefile, graphics/py-opencv-python-headless Makefile distinfo

graphics/py-opencv-python-headless: New port: Wrapper package for OpenCV python bindings
DeltaFile
+51-0graphics/py-opencv-python-headless/Makefile
+21-0graphics/py-opencv-python-headless/files/patch-setup.py
+19-0graphics/py-opencv-python-headless/files/patch-pyproject.toml
+7-0graphics/py-opencv-python-headless/distinfo
+5-0graphics/py-opencv-python-headless/pkg-descr
+1-0graphics/Makefile
+104-06 files

FreeBSD/ports 24c58c7misc Makefile, misc/py-compressed-tensors Makefile pkg-descr

misc/py-compressed-tensors: New port: Library for storing and loading compressed PyTorch models
DeltaFile
+31-0misc/py-compressed-tensors/Makefile
+11-0misc/py-compressed-tensors/files/patch-setup.py
+9-0misc/py-compressed-tensors/files/patch-pyproject.toml
+3-0misc/py-compressed-tensors/pkg-descr
+3-0misc/py-compressed-tensors/distinfo
+1-0misc/Makefile
+58-06 files

FreeBSD/ports fd5e125graphics/f3d distinfo pkg-plist, graphics/f3d/files patch-application_F3DSystemTools.cxx

graphics/{,py-}f3d: update 3.4.1 → 3.5.0
DeltaFile
+6-23graphics/f3d/files/patch-application_F3DSystemTools.cxx
+3-3graphics/py-f3d/distinfo
+3-3graphics/f3d/distinfo
+3-3graphics/f3d/pkg-plist
+1-2graphics/f3d/Makefile
+1-1graphics/py-f3d/Makefile
+17-356 files

LLVM/project d4ed2a7llvm/test/CodeGen/AMDGPU rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll

Trimmed test options and passes.
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
+2-21 files

LLVM/project 9744f1bclang/lib/Headers wasm_simd128.h, cross-project-tests/intrinsic-header-tests wasm_simd128.c

[WebAssembly] Support promoting lower lanes of f16x8 to f32x4. (#129786)
DeltaFile
+40-15llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+20-0llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
+9-0clang/lib/Headers/wasm_simd128.h
+6-0cross-project-tests/intrinsic-header-tests/wasm_simd128.c
+3-0llvm/test/MC/WebAssembly/simd-encodings.s
+2-0llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+80-156 files

OpenBSD/ports 6Rmgosnsecurity/openssl/3.5/patches patch-Configurations_unix-Makefile_tmpl patch-exporters_cmake_OpenSSLConfig_cmake_in, security/openssl/3.6/patches patch-Configurations_unix-Makefile_tmpl

   openssl: regen patches
VersionDeltaFile
1.2+2-2security/openssl/3.6/patches/patch-Configurations_unix-Makefile_tmpl
1.3+2-2security/openssl/3.5/patches/patch-Configurations_unix-Makefile_tmpl
1.2+1-1security/openssl/3.5/patches/patch-exporters_cmake_OpenSSLConfig_cmake_in
1.2+1-1security/openssl/3.5/patches/patch-exporters_pkg-config_libcrypto_pc_in
1.2+1-1security/openssl/3.5/patches/patch-exporters_pkg-config_libssl_pc_in
1.2+1-1security/openssl/3.5/patches/patch-exporters_pkg-config_openssl_pc_in
+8-88 files not shown
+16-1614 files

LLVM/project a030dfblldb/source/Commands CommandObjectThread.cpp, lldb/source/Target Thread.cpp

[lldb] Add --provider option to thread backtrace (#181071)
DeltaFile
+402-12lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/TestFrameProviderPassThroughPrefix.py
+188-5lldb/source/Commands/CommandObjectThread.cpp
+110-0lldb/test/API/functionalities/scripted_frame_provider/thread_filter/frame_provider.py
+94-0lldb/test/API/functionalities/scripted_frame_provider/thread_filter/TestFrameProviderThreadFilter.py
+65-8lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/frame_provider.py
+32-17lldb/source/Target/Thread.cpp
+891-4210 files not shown
+959-4816 files

FreeNAS/freenas e42eb14. CLAUDE.md, src/middlewared/middlewared/api/v26_0_0 zpool_scrub.py

docstring in API model
DeltaFile
+4-0CLAUDE.md
+1-0src/middlewared/middlewared/api/v27_0_0/zpool_scrub.py
+1-0src/middlewared/middlewared/api/v26_0_0/zpool_scrub.py
+6-03 files

NetBSD/pkgsrc OZg37CQdevel/cargo-c/patches patch-.._vendor_zeroize-1.8.2_src_lib.rs

   devel/cargo-c: restore zeroize patch
VersionDeltaFile
1.3+0-0devel/cargo-c/patches/patch-.._vendor_zeroize-1.8.2_src_lib.rs
+0-01 files

NetBSD/pkgsrc Q1Ik7nIdoc CHANGES-2026

   doc: Added sysutils/uutils-coreutils version 0.8.0
VersionDeltaFile
1.2141+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc XQQAfTTsysutils Makefile

   Add uutils-coreutils
VersionDeltaFile
1.1188+2-1sysutils/Makefile
+2-11 files

NetBSD/pkgsrc 2a7vLdgsysutils/uutils-coreutils distinfo cargo-depends.mk

   sysutils/uutils-coreutils: import package

   uutils coreutils is a cross-platform reimplementation of the GNU coreutils in
   Rust. While all programs have been implemented, some options might be missing
   or different behavior might be experienced.

   This project aims to be a drop-in replacement for the GNU utils. Differences
   with GNU are treated as bugs.

   uutils aims to work on as many platforms as possible, to be able to use the
   same utils on Linux, Mac, Windows and other platforms. This ensures, for
   example, that scripts can be easily transferred between platforms.
VersionDeltaFile
1.1+1,232-0sysutils/uutils-coreutils/distinfo
1.1+411-0sysutils/uutils-coreutils/cargo-depends.mk
1.1+214-0sysutils/uutils-coreutils/PLIST
1.1+40-0sysutils/uutils-coreutils/Makefile
1.1+10-0sysutils/uutils-coreutils/DESCR
+1,907-05 files

LLVM/project 3098b4dflang/include/flang/Optimizer/Transforms Passes.td Passes.h, flang/lib/Optimizer/Transforms LoopInvariantCodeMotion.cpp

[flang] Added LICM hoisting for nested regions. (#190696)

This patch adds a couple of experimental LICM modes
that allow hoisting operations from regions nested
inside a loop, e.g. when there is `fir.if` inside
`fir.do_loop`. The aggressive mode hoists all operations
that are safe to hoist. The cheap mode hoists only
"cheap" operations (currently, only `fir.convert`),
though the definition of "cheap" needs to be worked out.
DeltaFile
+341-0flang/test/Transforms/licm.fir
+117-31flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
+13-0flang/include/flang/Optimizer/Transforms/Passes.td
+8-0flang/include/flang/Optimizer/Transforms/Passes.h
+479-314 files

LLVM/project e6c262bllvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp, llvm/test/CodeGen/AMDGPU rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll

[AMDGPU] Added debugging output/test for multiple store to spill slot.
DeltaFile
+7-3llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+11-32 files

FreeNAS/freenas ce8167fsrc/middlewared/middlewared/api/v26_0_0 zpool_scrub.py __init__.py

v26 API models
DeltaFile
+29-0src/middlewared/middlewared/api/v26_0_0/zpool_scrub.py
+1-0src/middlewared/middlewared/api/v26_0_0/__init__.py
+30-02 files

NetBSD/pkgsrc iB1YM6Odoc CHANGES-2026 TODO

   doc: Updated devel/cargo-c to 0.10.21
VersionDeltaFile
1.2140+2-1doc/CHANGES-2026
1.27072+1-2doc/TODO
+3-32 files

NetBSD/pkgsrc LrOH1nodevel/cargo-c distinfo cargo-depends.mk, devel/cargo-c/patches patch-.._vendor_memchr-2.8.0_src_memchr.rs patch-.._vendor_memchr-2.8.0_src_memmem_searcher.rs

   devel/cargo-c: update to 0.10.21

    - cargo 0.95
VersionDeltaFile
1.29+417-366devel/cargo-c/distinfo
1.26+136-119devel/cargo-c/cargo-depends.mk
1.1+128-0devel/cargo-c/patches/patch-.._vendor_memchr-2.8.0_src_memchr.rs
1.1+78-0devel/cargo-c/patches/patch-.._vendor_memchr-2.8.0_src_memmem_searcher.rs
1.1+24-0devel/cargo-c/patches/patch-.._vendor_memchr-2.8.0_src_arch_aarch64_memchr.rs
1.1+15-0devel/cargo-c/patches/patch-.._vendor_memchr-2.8.0_src_arch_aarch64_mod.rs
+798-4858 files not shown
+822-49514 files

NetBSD/pkgsrc 1hp1TKJdoc CHANGES-2026

   doc: Updated security/openssl to 3.6.2
VersionDeltaFile
1.2139+2-1doc/CHANGES-2026
+2-11 files

NetBSD/pkgsrc aBpewjIsecurity/openssl distinfo PLIST, security/openssl/patches patch-crypto_initthread.c

   openssl: update to 3.6.2.

   OpenSSL 3.6.2 is a security patch release. The most severe CVE fixed in this
   release is Medium.

   This release incorporates the following bug fixes and mitigations:

     * Fixed incorrect failure handling in RSA KEM RSASVE encapsulation.
       ([CVE-2026-31790])

     * Fixed loss of key agreement group tuple structure when the `DEFAULT` keyword
       is used in the server-side configuration of the key-agreement group list.
       ([CVE-2026-2673])

     * Fixed out-of-bounds read in AES-CFB-128 on x86-64 CPUs with AVX-512 support.
       ([CVE-2026-28386])

     * Fixed potential use-after-free in DANE client code.
       ([CVE-2026-28387])

    [13 lines not shown]
VersionDeltaFile
1.188+4-5security/openssl/distinfo
1.26+3-1security/openssl/PLIST
1.317+2-2security/openssl/Makefile
1.2+1-1security/openssl/patches/patch-crypto_initthread.c
+10-94 files

OpenBSD/ports rUHpcbYlang/erlang/26 distinfo Makefile, lang/erlang/27 Makefile distinfo

   lang/erlang: Update to 26.2.5.19, 27.3.4.10, 28.4.2

   Fixes for
   CVE-2026-28810
   CVE-2026-32144
VersionDeltaFile
1.16+10-10lang/erlang/28/Makefile
1.28+9-9lang/erlang/27/Makefile
1.26+4-4lang/erlang/26/distinfo
1.23+4-4lang/erlang/27/distinfo
1.15+4-4lang/erlang/28/distinfo
1.31+3-3lang/erlang/26/Makefile
+34-346 files