LLVM/project a12adfbllvm/lib/Target/AMDGPU GCNSubtarget.h AMDGPU.td

[NFCI][AMDGPU] Convert more `SubtargetFeatures` to use `AMDGPUSubtargetFeature` and X-macros

Extend the X-macro pattern to eliminate boilerplate for additional subtarget features.

This reduces ~50 lines of repetitive member declarations and getter definitions.
DeltaFile
+123-140llvm/lib/Target/AMDGPU/GCNSubtarget.h
+100-154llvm/lib/Target/AMDGPU/AMDGPU.td
+3-3llvm/lib/Target/AMDGPU/R600Subtarget.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
+1-1llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+229-3005 files

LLVM/project 6367c4bcmake/Modules HandleDoxygen.cmake

[cmake][NFC] CRLF -> LF
DeltaFile
+40-40cmake/Modules/HandleDoxygen.cmake
+40-401 files

LLVM/project dd363d0llvm/lib/Transforms/Vectorize VPlanUnroll.cpp VPlan.h

[VPlan] Replace UnrollPart for VPScalarIVSteps with start index op (NFC) (#170906)

Replace the unroll part operand for VPScalarIVStepsRecipe with the start
index. This simplifies https://github.com/llvm/llvm-project/pull/170053
and is also a first step to break down the recipe into its components.

PR: https://github.com/llvm/llvm-project/pull/170906
DeltaFile
+36-5llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
+17-7llvm/lib/Transforms/Vectorize/VPlan.h
+3-19llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+11-0llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+3-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+70-345 files

FreeNAS/freenas 0f66d93src/middlewared/middlewared/plugins/iscsi_ alua.py

In standby_after_start order service reload ACTIVE/STANDBY

This has the added benefit that the reload on STANDBY will still
complete if the ACTIVE one is skipped for any reason.
DeltaFile
+25-14src/middlewared/middlewared/plugins/iscsi_/alua.py
+25-141 files

LLVM/project 8aa83e9llvm/utils/TableGen/Common CodeGenRegisters.cpp

[TableGen] Prefer base class on tied RC sizes

When searching for a matching subclass tablegen behavior is non
deterministic if we have several classes with the same size.
Break the tie by chooisng a class with smaller BaseClassOrder.
DeltaFile
+4-1llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+4-11 files

FreeNAS/freenas 15dfa1etests/sharing_protocols/iscsi test_261_iscsi_cmd.py

Add additional _wait_for_alua_settle calls
DeltaFile
+9-3tests/sharing_protocols/iscsi/test_261_iscsi_cmd.py
+9-31 files

LLVM/project 6ec2f97utils/bazel .bazelrc

[bazel] Suppress `-Wunused-command-line-argument` for header parsing (#177246)

Running bazel CI is full of warnings like this:
```
INFO: From Compiling libc/hdr/types/clock_t.h:
clang-21: warning: argument unused during compilation: '-c' [-Wunused-command-line-argument]
```
https://github.com/bazelbuild/rules_cc/pull/573 is a possible fix in
bazel itself. Until then, just use a copt to ignore it.
DeltaFile
+5-0utils/bazel/.bazelrc
+5-01 files

LLVM/project 9c103e7llvm/include/llvm/TargetParser Triple.h, llvm/lib/Target/RISCV RISCVFeatures.td RISCVTargetMachine.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+21-8llvm/lib/TargetParser/TargetDataLayout.cpp
+21-0llvm/lib/Target/RISCV/RISCVFeatures.td
+8-0llvm/test/CodeGen/RISCV/rvy/datalayout.ll
+3-2llvm/include/llvm/TargetParser/Triple.h
+2-2llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-0llvm/test/CodeGen/RISCV/features-info.ll
+57-123 files not shown
+60-139 files

LLVM/project 92bbad5clang/test/Driver print-supported-extensions-riscv.c, llvm/lib/Target/RISCV RISCVFeatures.td

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+21-0llvm/lib/Target/RISCV/RISCVFeatures.td
+2-0llvm/test/CodeGen/RISCV/features-info.ll
+1-0llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+1-0clang/test/Driver/print-supported-extensions-riscv.c
+25-04 files

GhostBSD/networkmgr e2b3a3b. setup.py, src link-up.py auto-switch.py

Merge pull request #123 from ghostbsd/devd

Improve devd scripts and bump version to 6.8
DeltaFile
+17-39src/link-up.py
+21-23src/auto-switch.py
+12-14src/setup-nic.py
+4-4src/networkmgr.conf
+1-1setup.py
+55-815 files

LLVM/project 6788e8cllvm/lib/Target/AArch64 AArch64ConditionOptimizer.cpp, llvm/test/CodeGen/AArch64 aarch64-condopt-nzcvdef.mir

[AArch64] Handle all NZCV clobbers in AArch64ConditionOptimizer (#177034)

This pass was special casing some instructions that could clobber NZCV between
a CMP and a Bcc. This patch alters that to all instructions that might modify
NZCV, making sure we handle all cases.
DeltaFile
+63-0llvm/test/CodeGen/AArch64/aarch64-condopt-nzcvdef.mir
+2-21llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+65-212 files

LLVM/project 489e4eflibc/src/__support/math log1p.h log2.h, libc/src/math/generic log1p.cpp log2.cpp

address review feedback

Created using spr 1.3.7
DeltaFile
+256-819llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1,070-0libc/src/__support/math/log1p.h
+2-1,050libc/src/math/generic/log1p.cpp
+978-0libc/src/__support/math/log2.h
+2-960libc/src/math/generic/log2.cpp
+919-0libc/src/__support/math/log10.h
+3,227-2,829128 files not shown
+7,138-7,526134 files

FreeBSD/ports 0abc606science/afni distinfo Makefile

science/afni: Update to 26.0.04
DeltaFile
+3-3science/afni/distinfo
+1-1science/afni/Makefile
+4-42 files

GhostBSD/networkmgr 7289d2dsrc link-up.py

Add PIPE to subprocess.run in link-up.py for stdout capture

- Updated subprocess.run with `stdout=PIPE` for capturing output
- Removed unnecessary `close_fds` parameter (default True in Python 3)
DeltaFile
+2-2src/link-up.py
+2-21 files

FreeNAS/freenas 1f86a8esrc/middlewared/middlewared/plugins/service_/services nfs.py

Add wait for lock file release on NFS stop.
This commit includes debug.
DeltaFile
+19-0src/middlewared/middlewared/plugins/service_/services/nfs.py
+19-01 files

NetBSD/pkgsrc D4xJfFadoc pkg-vulnerabilities

   pkg-vulnerabilities: add last 12 hours CVEs

   + bind, glib2 (fixed in 2.87.1, unclear if 2.86.x is affected and/or will get a
     backport),
     moodle (no further details, assume not fixed and maybe not even reported
     upstream),
     php-phpgadmin (no further details, assume not fixed and maybe not even
     reported upstream),
     proftpd (no further details, assume not fixed and maybe not even
     reported upstream),
     python (fixed upstream, no stable releases with the fix)
VersionDeltaFile
1.720+11-1doc/pkg-vulnerabilities
+11-11 files

NetBSD/pkgsrc lbrd9dowww/palemoon-gtk3 PLIST

   palemoon-gtk3: fix PLIST
VersionDeltaFile
1.2+1-2www/palemoon-gtk3/PLIST
+1-21 files

Dreckly/dreckly b8d4329www/palemoon-gtk3 PLIST

fix PLIST
DeltaFile
+0-1www/palemoon-gtk3/PLIST
+0-11 files

FreeNAS/freenas 9add5afsrc/middlewared/middlewared/utils tdb.py

NAS-139396 / 26.04 / Simplify TDB handle validation (#18071)

Since NAS-139387 we now have access to the tdb_fd through the samba
python tdb bindings and so we can directly check whether our handle is
still valid.
DeltaFile
+4-12src/middlewared/middlewared/utils/tdb.py
+4-121 files

OpenBSD/ports rlvebK2graphics/tkpng Makefile

   MODTK_VERSION=8.5

   TkPNG is only needed for Tk 8.5. Tk 8.6 has all the functionality.
VersionDeltaFile
1.12+1-0graphics/tkpng/Makefile
+1-01 files

FreeNAS/freenas 2b48401src/middlewared/middlewared/plugins cache.py

flake8 fix
DeltaFile
+3-1src/middlewared/middlewared/plugins/cache.py
+3-11 files

LLVM/project b5077a7llvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.cpp, llvm/test/CodeGen/AArch64 aarch64-mops.ll load-store-forwarding.ll

[AArch64][GlobalISel] Extend smaller than i32 gpr loads/stores in RegBankSelect. (#175810)

A i8 / i16 load and store is only legal for FPR registers. This patch extends
the types on i8/i16 G_LOADS and G_STORES to i32 using anyext / trunc, so that
selection can be simpler and does not need to handle illegal operations.

This can leave some anyext(trunc) operations that could be removed yet but
should be possible to optimize away.
DeltaFile
+48-20llvm/test/CodeGen/AArch64/aarch64-mops.ll
+44-7llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+18-24llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+8-16llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
+22-0llvm/test/CodeGen/AArch64/load-store-forwarding.ll
+4-7llvm/test/CodeGen/AArch64/cpa-globalisel.ll
+144-742 files not shown
+152-808 files

LLVM/project 14fe4a8lldb/include/lldb/Utility UserID.h

[lldb] Remove unused nested class UserID::IDMatches (NFC) (#177211)

DeltaFile
+0-20lldb/include/lldb/Utility/UserID.h
+0-201 files

FreeNAS/freenas 8b2245dsrc/middlewared/middlewared/plugins cache.py, src/middlewared/middlewared/plugins/catalog features.py apps_details.py

Add persistent option to cache plugin

This commit adds ability to persistently set cache entries
(survives across middleware restarts / reboots, but not system
upgrades), and set clustered cache entries (ditto about
lifecycle).
DeltaFile
+265-16src/middlewared/middlewared/plugins/cache.py
+226-0tests/unit/test_cache.py
+6-3src/middlewared/middlewared/plugins/catalog/features.py
+4-4src/middlewared/middlewared/plugins/catalog/apps_details.py
+2-2src/middlewared/middlewared/plugins/directoryservices_/connection.py
+503-255 files

LLVM/project fa4f765llvm/lib/Target/AMDGPU AMDGPU.td VOP3Instructions.td

[AMDGPU] Further improve `AMDGPUSubtargetFeature` multiclass (#177077)

This PR extends the multiclass to support two additional parameters: one
for specifying whether an `AssemblerPredicate` should be generated, and
another for dependent `SubtargetFeatures`. This allows 15 more
definitions to be converted to use the multiclass.
DeltaFile
+95-107llvm/lib/Target/AMDGPU/AMDGPU.td
+3-3llvm/lib/Target/AMDGPU/VOP3Instructions.td
+1-4llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/VOP1Instructions.td
+100-1154 files

LLVM/project d64d373llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 phi-multi-same-nodes.ll

[SLP]Correctly handle vector nodes, coming from same incoming blocks in PHI nodes

If multiple nodes are generated from same PHI node for the same block,
still need to vectorize vector nodes, even if the value for the incoming block was already emitted.

Fixes #177124
DeltaFile
+86-0llvm/test/Transforms/SLPVectorizer/X86/phi-multi-same-nodes.ll
+11-8llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+97-82 files

LLVM/project 795d940lldb/source/API CMakeLists.txt

[lldb][cmake] Fix standalone Xcode build header staging (#177033)

The LLDB standalone build using Xcode fails because the staging
directory custom command output is attached to multiple
liblldb-stage-header-* targets, but none of these targets depend on each
other. Xcode's new build system doesn't allow this.

This creates a new target `liblldb-header-staging-dir` that depends on
the staging directory creation, and makes all header staging targets
depend on it instead of directly depending on the directory in their
custom commands. This ensures all targets share a common dependency,
satisfying Xcode's build system requirements.
DeltaFile
+5-2lldb/source/API/CMakeLists.txt
+5-21 files

FreeNAS/freenas 42d050asrc/middlewared/middlewared/plugins cache.py

Fix
DeltaFile
+3-3src/middlewared/middlewared/plugins/cache.py
+3-31 files

LLVM/project ee0fb4cllvm/test/MC/AMDGPU gfx1250_asm_load_tr.s

[AMDGPU] Auto-generate checks for gfx1250_asm_load_tr.s, NFC (#177220)

DeltaFile
+75-74llvm/test/MC/AMDGPU/gfx1250_asm_load_tr.s
+75-741 files

LLVM/project b1907c1mlir/include/mlir/Dialect/LLVMIR ROCDLOps.td, mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp

[ROCDL] Refactored MFMA ops in ODS; added constraints (#175775)

This PR improves the ROCDL MFMA intrinsics by making their operand and
result types explicit in the IR and by modeling immediate arguments
(immargs) as attributes rather than opaque operands.

This brings MFMA intrinsics in line with recent changes made to ROCDL
WMMA operations, where intrinsic signatures were clarified to avoid
treating them as an unstructured “blob of arguments”.
DeltaFile
+346-421mlir/test/Dialect/LLVMIR/rocdl.mlir
+253-326mlir/test/Target/LLVMIR/rocdl.mlir
+120-88mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+39-39mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
+31-37mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
+20-19mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+809-9302 files not shown
+837-9588 files