FreeBSD/ports bdc7494security/vuxml/vuln 2026.xml

security/vuxml: add textproc/p5-Text-CSV_XS

Reported by:    H.Merijn Brand - Tux <linux at tux.freedom.nl>
Security:       CVE-2026-7111
Reviewed by:    osa, vvd (mentors)
Approved by:    osa (mentor)
Differential Revision: https://reviews.freebsd.org/D56749
DeltaFile
+41-0security/vuxml/vuln/2026.xml
+41-01 files

NetBSD/pkgsrc-wip f0e089es-nail distinfo, s-nail/patches patch-src_mx_file-streams.c

s-nail: fixed compiling on macOS
DeltaFile
+13-0s-nail/patches/patch-src_mx_file-streams.c
+1-1s-nail/distinfo
+14-12 files

FreeBSD/ports a4a400bdevel/brpc pkg-plist Makefile, devel/brpc/files patch-src_brpc_socket.cpp patch-src_bthread_fd.cpp

devel/brpc: add new ports.

PR:             293396
DeltaFile
+541-0devel/brpc/pkg-plist
+124-0devel/brpc/files/patch-src_brpc_socket.cpp
+92-0devel/brpc/files/patch-src_bthread_fd.cpp
+49-0devel/brpc/files/patch-CMakeLists.txt
+44-0devel/brpc/files/patch-src_butil_logging.cc
+41-0devel/brpc/Makefile
+891-022 files not shown
+1,249-028 files

LLVM/project a3afdb1clang/lib/Driver/ToolChains HIPUtility.cpp

clang: Use correct triple when constructing offload bundler command

Use the toolchain triple for the particular input instead of the top
level toolchain. NFC for now, but avoids mismatched triples in
a future change.
DeltaFile
+3-3clang/lib/Driver/ToolChains/HIPUtility.cpp
+3-31 files

LLVM/project aee55a8llvm/test/CodeGen/X86 vector-reduce-umin.ll vector-reduce-umax.ll

[X86] combineMinMaxReduction - match any minmax reduction to a legal scalar (#195261)

Further relaxation of the VECREDUCE minmax folds - recognise any
>=128-bit vector that reduces to a legal scalar.

Adds custom ops for more VECREDUCE types (inc vXi32/vXi64 types)

Remaining issues are sub-128-bit vector reductions (unnecessary padding
with neutral elements) and handling of i64 types on 32-bit targets - I'm
working on fixes for both of these.
DeltaFile
+532-602llvm/test/CodeGen/X86/vector-reduce-umin.ll
+521-588llvm/test/CodeGen/X86/vector-reduce-umax.ll
+340-398llvm/test/CodeGen/X86/vector-reduce-smin.ll
+333-389llvm/test/CodeGen/X86/vector-reduce-smax.ll
+245-311llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
+245-310llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
+2,216-2,5985 files not shown
+2,420-2,88211 files

LLVM/project 83ecdb7llvm/lib/Target/ARM ARMISelLowering.cpp, llvm/test/CodeGen/ARM sdiv-pow2-thumb-size.ll sdiv-pow2-arm-size.ll

ARM: Support OR and XOR in targetShrinkDemandedConstant (#165106)

Also some changes for AND, OR, and XOR, including not changing if it
is legal. This prevents overcorrection to the mask, especially if it
is valid already.
DeltaFile
+135-64llvm/lib/Target/ARM/ARMISelLowering.cpp
+110-39llvm/test/CodeGen/ARM/sdiv-pow2-thumb-size.ll
+52-32llvm/test/CodeGen/ARM/sdiv-pow2-arm-size.ll
+3-7llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
+2-4llvm/test/CodeGen/ARM/urem-seteq-illegal-types.ll
+2-2llvm/test/CodeGen/ARM/fpenv.ll
+304-1484 files not shown
+309-15510 files

LLVM/project 7df6714llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 neon-saba.ll arm64-neon-aba-abd.ll

[AArch64] Use add_like for SABD and UABA (#194421)

Similar to the other patches that have made use of add_like recent, this
adds add_like to the SABA and UABA patterns.
DeltaFile
+24-33llvm/test/CodeGen/AArch64/neon-saba.ll
+12-24llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
+13-13llvm/lib/Target/AArch64/AArch64InstrInfo.td
+49-703 files

LLVM/project b09174bllvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Transforms/LoopUnroll/AMDGPU runtime-unroll.ll

[AMDGPU] Enable runtime loop unrolling (#194924)

Enable auto runtime unrolling for AMDGPU by setting `UP.Runtime = true`
in `getUnrollingPreferences`, with `PartialThreshold = Threshold / 4` to
limit code-size growth.

Benchmarked on **MI350X (gfx950)** and **MI300X (gfx942)** using
Composable Kernel, xpu-perf, and llama.cpp. Results showed some some
improvements and no real regressions.

AI Disclaimer: Cursor was used to evaluate the change and run
benchmarking experiments.
DeltaFile
+63-0llvm/test/Transforms/LoopUnroll/AMDGPU/runtime-unroll.ll
+5-2llvm/test/Transforms/SimpleLoopUnswitch/AMDGPU/uniform-unswitch.ll
+4-1llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+72-33 files

LLVM/project 8bb6419clang/test/Analysis analyzeOneFunction.cpp, clang/test/Analysis/ctu on-demand-parsing.c on-demand-parsing.cpp

[TEST-ONLY] Make sure clang-extdef-mapping don't infer database (#195196)
DeltaFile
+1-1clang/test/Tooling/clang-extdef-mapping.cpp
+1-1clang/test/Analysis/analyzeOneFunction.cpp
+1-1clang/test/Analysis/ctu/on-demand-parsing.c
+1-1clang/test/Analysis/ctu/on-demand-parsing.cpp
+4-44 files

LLVM/project f86d707llvm/docs LangRef.rst TransformMetadata.rst, llvm/lib/Transforms/Scalar WarnMissedTransforms.cpp

[LoopVectorize] Reland: Add metadata to distinguish vectorized loop body from scalar remainder (#194912)

Reland of #190258, reverted in #194901 due to a null-pointer dereference
when the scalar preheader is absent. Fixed by guarding the metadata
emission with a null check on `ScalarPH`. Also adds a dedicated test
(`vectorize-loop-kind-metadata.ll`) verifying the metadata is emitted
only when remarks are enabled.

---

Add two new loop metadata attributes — `llvm.loop.vectorize.body` and
`llvm.loop.vectorize.epilogue` — that the loop vectorizer sets on the
generated vector loop and epilogue loop respectively. The metadata is
only emitted when optimization remarks are enabled (`ORE->enabled()`),
so it has zero cost in normal compilation.

These enable downstream passes (LoopUnroll, WarnMissedTransforms) to
produce more precise optimization remarks. Instead of the generic "loop
not unrolled" warning on a source line that was vectorized, the unroller

    [25 lines not shown]
DeltaFile
+120-0llvm/test/Transforms/LoopTransformWarning/vectorizer-loop-kind-unroll-warning.ll
+110-0llvm/test/Transforms/LoopUnroll/vectorizer-loop-kind-remarks.ll
+42-0llvm/docs/LangRef.rst
+34-0llvm/test/Transforms/LoopVectorize/vectorize-loop-kind-metadata.ll
+21-0llvm/docs/TransformMetadata.rst
+10-3llvm/lib/Transforms/Scalar/WarnMissedTransforms.cpp
+337-36 files not shown
+380-912 files

FreeNAS/freenas 0d7fc28src/middlewared/middlewared/plugins zettarepl.py

NAS-140875 / 27.0.0-BETA.1 / remove pytz (#18879)

Deprecated and replaced officially with builtin `zoneinfo` module
DeltaFile
+2-2src/middlewared/middlewared/plugins/zettarepl.py
+2-21 files

FreeNAS/freenas 0ad58f4src/middlewared/middlewared/plugins/failover_ event.py, src/middlewared/middlewared/plugins/iscsi_ lio.py alua.py

Add middleware support for LIO ALUA HA

Wire up the middleware side of LIO ALUA high-availability: load
lio_ha.ko with per-node addresses on service start, manage the
4-row ALUA state table (MASTER/BACKUP × synced/not-synced) across
failover events, clean up STANDBY configfs on pool export, and
add pre-flight validation that targets have static initiator ACLs
before ALUA can be enabled.
DeltaFile
+318-97src/middlewared/middlewared/utils/lio/config.py
+179-1src/middlewared/middlewared/plugins/iscsi_/lio.py
+62-9src/middlewared/middlewared/plugins/iscsi_/alua.py
+33-21src/middlewared/middlewared/plugins/failover_/event.py
+34-19src/middlewared/middlewared/plugins/iscsi_/iscsi_global.py
+28-0src/middlewared/middlewared/plugins/iscsi_/global_linux.py
+654-1474 files not shown
+690-14810 files

LLVM/project bcaaf61libc/docs CMakeLists.txt, libc/docs/headers index.rst

[libc][docs] Add pwd.h POSIX header documentation (#186292)

Add YAML metadata for `pwd.h` listing all POSIX-mandated functions
(`endpwent`, `getpwent`, `getpwnam`, `getpwnam_r`, `getpwuid`,
`getpwuid_r`, `setpwent`). This header defines no macros per POSIX.

Add `pwd` to `index.rst` and `CMakeLists.txt` `docgen_list`.

Verified with `python3 docgen.py pwd.h` — generates valid RST with
correct POSIX links.

Partial fix for #122006

Co-authored-by: Jeff Bailey <jbailey at raspberryginger.com>
DeltaFile
+15-0libc/utils/docgen/pwd.yaml
+1-0libc/docs/CMakeLists.txt
+1-0libc/docs/headers/index.rst
+17-03 files

NetBSD/pkgsrc-wip fd20258libnfs options.mk Makefile, libnfs/patches patch-cmake_ConfigureChecks.cmake patch-cmake_config.h.cmake

libnfs: switch to build with cmake

+ various minor changes
DeltaFile
+36-3libnfs/options.mk
+11-22libnfs/Makefile
+19-0libnfs/patches/patch-cmake_ConfigureChecks.cmake
+16-0libnfs/patches/patch-cmake_config.h.cmake
+15-0libnfs/patches/patch-CMakeLists.txt
+0-15libnfs/patches/patch-configure.ac
+97-402 files not shown
+106-428 files

LLVM/project f3d0ac9llvm/lib/Analysis Loads.cpp, llvm/unittests/Analysis LoadsTest.cpp

[Loads] Fix crash on mixed-address-space pointers in no-AA store check (#195256)

Fix crash on mixed-address-space pointers in no-AA store check.
`areNonOverlapSameBaseLoadAndStore` built `ConstantRanges` from `APInts`
sized by the load and store pointer index widths. When those widths
differ (AMDGPU's AS=0 vs AS=5), `ConstantRange::intersectWith` asserts.
Adds early return mirroring `BasicAA` path.

This can happen when `FindAvailableLoadedValue` is called without
`BatchAAResults`. The path with `BatchAAResults` already handles it.

This crash was observed in #190607, so it was reverted in #195135.
DeltaFile
+29-0llvm/unittests/Analysis/LoadsTest.cpp
+2-0llvm/lib/Analysis/Loads.cpp
+31-02 files

LLVM/project 4fa459dllvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/test/MC/AArch64 armv9a-tlbip.s

fixup! Address Carol's PR comments
DeltaFile
+5-0llvm/test/MC/AArch64/armv9a-tlbip.s
+3-0llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+8-02 files

LLVM/project 6900ebellvm/lib/Transforms/IPO Attributor.cpp

Attributor: Avoid double map lookup in updateAttrMap (#182666)

This will leave behind the map entry in the unchanged case,
but this seems to not matter. Could erase the newly inserted
entry if that happens, but that also doesn't seem to make a
difference.
DeltaFile
+7-8llvm/lib/Transforms/IPO/Attributor.cpp
+7-81 files

LLVM/project ed25e1fllvm/lib/Transforms/Vectorize VPlanUtils.cpp VPlan.h

[VPlan] Add missing const-qualifications (NFC) (#195248)
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+2-2llvm/lib/Transforms/Vectorize/VPlan.h
+1-1llvm/lib/Transforms/Vectorize/VPlanUtils.h
+7-73 files

FreeBSD/ports 902fcfawww/py-google-api-python-client Makefile distinfo

www/py-google-api-python-client: Update to 2.195.0

- Convert to PEP517

ChangeLog:      https://github.com/googleapis/google-api-python-client/releases/tag/v2.195.0
Reported by:    "release-please[bot]" <notifications at github.com>
DeltaFile
+4-2www/py-google-api-python-client/Makefile
+3-3www/py-google-api-python-client/distinfo
+7-52 files

FreeBSD/ports c68d3ddmultimedia/go2tv distinfo Makefile

multimedia/go2tv: Update to 2.3.0

ChangeLog:      https://github.com/alexballas/go2tv/releases/tag/v2.3.0
Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+5-5multimedia/go2tv/distinfo
+2-2multimedia/go2tv/Makefile
+7-72 files

LLVM/project a6a53ealibc/docs CMakeLists.txt, libc/docs/headers index.rst

[libc][docs] Add sched.h POSIX header documentation (#186290)

Add YAML metadata for `sched.h` listing all POSIX-mandated macros
(`SCHED_FIFO`, `SCHED_OTHER`, `SCHED_RR`, `SCHED_SPORADIC`) and
functions
(`sched_get_priority_max`, `sched_get_priority_min`, `sched_getparam`,
`sched_getscheduler`, `sched_rr_get_interval`, `sched_setparam`,
`sched_setscheduler`, `sched_yield`).

Add `sched` to `index.rst` and `CMakeLists.txt` `docgen_list`.

Verified with `python3 docgen.py sched.h` — generates valid RST with
correct POSIX links.

Partial fix for #122006

Co-authored-by: Jeff Bailey <jbailey at raspberryginger.com>
DeltaFile
+27-0libc/utils/docgen/sched.yaml
+1-0libc/docs/CMakeLists.txt
+1-0libc/docs/headers/index.rst
+29-03 files

FreeBSD/doc 31e233awebsite/data/en/press press.toml

press: Add latest FreeBSD YouTube video to press

Sponsored by:   FreeBSD Foundation
Differential Revision:  https://reviews.freebsd.org/D56755
DeltaFile
+9-0website/data/en/press/press.toml
+9-01 files

FreeBSD/ports 0f0eae0textproc/quarto distinfo Makefile

textproc/quarto: update 1.10.0 → 1.10.3

PR:     294904
DeltaFile
+5-5textproc/quarto/distinfo
+1-1textproc/quarto/Makefile
+6-62 files

LLVM/project c549abaflang/lib/Semantics check-omp-loop.cpp openmp-utils.cpp, flang/test/Parser/OpenMP linear-clause.f90

[flang][OpenMP] Check conflicts between predetermined/explicit DSA (#194961)

Improve checks for loop iteration variables with predetermined DSA
appearing in DSA clauses. Show both the location of the variable in the
offending clause, and in the loop.

Make the checks a bit more accurate as well: only allow LINEAR clause on
SIMD construct with a single affected loop.
DeltaFile
+86-22flang/lib/Semantics/check-omp-loop.cpp
+27-0llvm/include/llvm/Frontend/OpenMP/OMP.h
+11-14flang/test/Parser/OpenMP/linear-clause.f90
+18-3flang/test/Semantics/OpenMP/do01.f90
+14-6flang/lib/Semantics/openmp-utils.cpp
+0-15flang/lib/Semantics/check-omp-structure.cpp
+156-608 files not shown
+173-9114 files

LLVM/project e7db558libc/docs CMakeLists.txt, libc/docs/headers index.rst

[libc][docs] Add spawn.h POSIX header documentation (#186291)

Add YAML metadata for `spawn.h` listing all POSIX-mandated macros
(`POSIX_SPAWN_RESETIDS`, `POSIX_SPAWN_SETPGROUP`,
`POSIX_SPAWN_SETSCHEDPARAM`,
`POSIX_SPAWN_SETSCHEDULER`, `POSIX_SPAWN_SETSID`,
`POSIX_SPAWN_SETSIGDEF`,
`POSIX_SPAWN_SETSIGMASK`) and all 23 functions (`posix_spawn`,
`posix_spawnp`,
`posix_spawn_file_actions_*`, `posix_spawnattr_*`).

Add `spawn` to `index.rst` and `CMakeLists.txt` `docgen_list`.

Verified with `python3 docgen.py spawn.h` — generates valid RST with
correct POSIX links.

Partial fix for #122006
DeltaFile
+63-0libc/utils/docgen/spawn.yaml
+1-0libc/docs/headers/index.rst
+1-0libc/docs/CMakeLists.txt
+65-03 files

LLVM/project d7c907allvm/lib/Target/AArch64/MCTargetDesc AArch64InstPrinter.cpp

fixup! Address PR comment about shortened `sysp` with xzr/xzr
DeltaFile
+17-16llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+17-161 files

LLVM/project f35bcd8llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp, llvm/test/MC/AArch64 armv9-sysp-diagnostics.s

fixup! Improve error parsing
DeltaFile
+46-25llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+12-12llvm/test/MC/AArch64/armv9-sysp-diagnostics.s
+58-372 files

LLVM/project 33a7f77llvm/lib/Target/AArch64 AArch64RegisterInfo.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Implement Marian's suggestion to implement as XSeqPairsClass + [XZR, XZR]
DeltaFile
+54-82llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+35-73llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+12-9llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+8-1llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+0-7llvm/test/MC/AArch64/armv9a-sysp.s
+1-3llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
+110-1756 files

LLVM/project 1421144llvm/lib/Target/AArch64 AArch64InstrFormats.td

fixup! Remove superfluous code
DeltaFile
+0-7llvm/lib/Target/AArch64/AArch64InstrFormats.td
+0-71 files

LLVM/project 5990d03llvm/lib/Target/AArch64/MCTargetDesc AArch64InstPrinter.cpp, llvm/test/MC/AArch64 armv9a-sysp.s

fixup! Add no-alias tests
DeltaFile
+7-0llvm/test/MC/AArch64/armv9a-sysp.s
+4-3llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+11-32 files