LLVM/project 9c10ec2llvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mfma.gfx950.ll v_mov_b64-isel.ll

[AMDGPU] Select `V_MOV_B64_e32` directly if a target supports it
DeltaFile
+192-204llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
+119-0llvm/test/CodeGen/AMDGPU/v_mov_b64-isel.ll
+25-26llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
+30-0llvm/lib/Target/AMDGPU/SIInstructions.td
+3-2llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll
+385-2481 files not shown
+386-2487 files

FreeBSD/ports 03dbba3net/keycloak pkg-plist distinfo

net/keycloak: Update 26.6.3 => 26.6.4 (8 CVEs)

Release Notes:
https://www.keycloak.org/2026/06/keycloak-2664-released

PR:             296367
Security:       CVE-2026-9099
Security:       CVE-2026-9083
Security:       CVE-2026-9086
Security:       CVE-2026-9705
Security:       CVE-2026-9795
Security:       CVE-2026-9799
Security:       CVE-2026-9800
Security:       CVE-2026-11800
Sponsored by:   UNIS Labs
MFH:            2026Q2

(cherry picked from commit e9dd3d7873620832266a43b81635d2391d6668ed)
DeltaFile
+163-162net/keycloak/pkg-plist
+3-3net/keycloak/distinfo
+1-1net/keycloak/Makefile
+167-1663 files

FreeBSD/doc fccfbb3website/content/ru administration.adoc

website/ru: Update administration.adoc

Update original revision info in the FRDP footer.
DeltaFile
+1-1website/content/ru/administration.adoc
+1-11 files

LLVM/project 83bda78llvm/lib/Target/RISCV RISCVCallingConv.cpp RISCVISelLowering.cpp, llvm/lib/Target/RISCV/GISel RISCVCallLowering.cpp

[RISCV] Make getArgGPRs take a const RISCVSubtarget & (NFC) (#206327)

This aligns the signature with getArgFPRs(), as suggested here:
https://github.com/llvm/llvm-project/pull/204929#discussion_r3462814724
DeltaFile
+5-3llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1-1llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+1-1llvm/lib/Target/RISCV/RISCVCallingConv.h
+1-1llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+9-75 files

LLVM/project 9404cc4mlir/include/mlir-c Interfaces.h, mlir/lib/CAPI/Interfaces Interfaces.cpp CMakeLists.txt

[mlir-c] Add RegionBranchOpInterface C API bindings
DeltaFile
+68-0mlir/test/CAPI/ir.c
+42-0mlir/lib/CAPI/Interfaces/Interfaces.cpp
+34-0mlir/include/mlir-c/Interfaces.h
+1-0mlir/lib/CAPI/Interfaces/CMakeLists.txt
+145-04 files

LLVM/project c5c2ce7mlir/include/mlir-c Interfaces.h, mlir/lib/CAPI/Interfaces Interfaces.cpp CMakeLists.txt

[mlir-c] Add DestinationStyleOpInterface C API bindings
DeltaFile
+58-0mlir/test/CAPI/ir.c
+42-0mlir/lib/CAPI/Interfaces/Interfaces.cpp
+40-0mlir/include/mlir-c/Interfaces.h
+1-0mlir/lib/CAPI/Interfaces/CMakeLists.txt
+141-04 files

LLVM/project aa97fe4mlir/include/mlir-c Interfaces.h, mlir/lib/CAPI/Interfaces Interfaces.cpp CMakeLists.txt

[mlir-c] Add LoopLikeOpInterface C API bindings
DeltaFile
+81-0mlir/test/CAPI/ir.c
+61-0mlir/lib/CAPI/Interfaces/Interfaces.cpp
+45-0mlir/include/mlir-c/Interfaces.h
+1-0mlir/lib/CAPI/Interfaces/CMakeLists.txt
+188-04 files

LLVM/project 1816101mlir/include/mlir-c IR.h, mlir/lib/CAPI/IR IR.cpp

[mlir-c] Add mlirValueReplaceUsesWithIf
DeltaFile
+52-0mlir/test/CAPI/ir.c
+14-0mlir/include/mlir-c/IR.h
+10-0mlir/lib/CAPI/IR/IR.cpp
+76-03 files

LLVM/project 02c3ebbmlir/include/mlir-c IR.h, mlir/lib/CAPI/IR IR.cpp

[mlir-c] Add structural operation equivalence
DeltaFile
+70-0mlir/test/CAPI/ir.c
+25-0mlir/include/mlir-c/IR.h
+24-0mlir/lib/CAPI/IR/IR.cpp
+119-03 files

LLVM/project d24b49bmlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

[mlir-c] Add RewriterBase insertion point save/restore
DeltaFile
+63-0mlir/test/CAPI/rewrite.c
+26-0mlir/lib/CAPI/Transforms/Rewrite.cpp
+19-0mlir/include/mlir-c/Rewrite.h
+108-03 files

LLVM/project 1260960mlir/include/mlir-c Rewrite.h, mlir/lib/CAPI/Transforms Rewrite.cpp

[mlir-c] Add TypeConverter target materialization
DeltaFile
+90-0mlir/test/CAPI/rewrite.c
+9-0mlir/lib/CAPI/Transforms/Rewrite.cpp
+7-0mlir/include/mlir-c/Rewrite.h
+106-03 files

LLVM/project 8a3261bmlir/include/mlir-c Analysis.h, mlir/lib/CAPI/IR Analysis.cpp

[mlir-c] Add getBlocksSortedByDominance and topologicalSort
DeltaFile
+76-0mlir/test/CAPI/ir.c
+21-1mlir/include/mlir-c/Analysis.h
+20-0mlir/lib/CAPI/IR/Analysis.cpp
+117-13 files

LLVM/project 76e5e13clang/docs ReleaseNotesTemplate.txt

[docs] Convert clang release notes template to Markdown
DeltaFile
+121-160clang/docs/ReleaseNotesTemplate.txt
+121-1601 files

FreeBSD/ports e9dd3d7net/keycloak pkg-plist distinfo

net/keycloak: Update 26.6.3 => 26.6.4 (8 CVEs)

Release Notes:
https://www.keycloak.org/2026/06/keycloak-2664-released

PR:             296367
Security:       CVE-2026-9099
Security:       CVE-2026-9083
Security:       CVE-2026-9086
Security:       CVE-2026-9705
Security:       CVE-2026-9795
Security:       CVE-2026-9799
Security:       CVE-2026-9800
Security:       CVE-2026-11800
Sponsored by:   UNIS Labs
MFH:            2026Q2
DeltaFile
+163-162net/keycloak/pkg-plist
+3-3net/keycloak/distinfo
+1-1net/keycloak/Makefile
+167-1663 files

LLVM/project 628fe77clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/test/CIR/CodeGen global-temporary-comdat.cpp

[CIR] Emit comdat for weak global temporaries (#206530)

A lifetime-extended temporary with static or thread storage takes its
extending variable's linkage.  When that linkage is weak-for-linker -- an
inline variable or a variable template binding a const reference to a
temporary -- and the target supports COMDAT, classic CodeGen puts the
temporary's global in a comdat.  CIRGen's getAddrOfGlobalTemporary hit
errorNYI for that case, so `inline const int &r = 42;` failed to compile
under -fclangir.  It is a recurring blocker in the libcxx std/ suite
(flat_map/flat_set construction, vector<bool>, format ranges).

CIR globals already carry a comdat flag, and the weak-for-linker path
elsewhere in CIRGenModule already sets it; this does the same for the
materialized temporary.  The existing comdat lowering emits the symbol-named
`comdat any`, so the lowered IR matches classic byte-for-byte.
DeltaFile
+17-0clang/test/CIR/CodeGen/global-temporary-comdat.cpp
+1-2clang/lib/CIR/CodeGen/CIRGenModule.cpp
+18-22 files

FreeNAS/freenas d13ed50src/middlewared/middlewared/plugins/network_ dns.py, src/middlewared/middlewared/utils dns.py

Fix error handling
DeltaFile
+24-0tests/unit/test_dns.py
+10-7src/middlewared/middlewared/plugins/network_/dns.py
+15-0src/middlewared/middlewared/utils/dns.py
+49-73 files

LLVM/project debf392llvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp, llvm/tools/llvm-jitlink CMakeLists.txt

[AArch64][llvm-jitlink] Fix two QNX cross-compile build failures (NFC) (#206290)

Fixes two build failures when cross-compiling LLVM for QNX
(aarch64-unknown-nto-qnx8.0.0).

gcc `-Wstringop-overread` false-positive in `AArch64InstructionSelector.cpp`:  
GCC's static analysis misreads the SmallVector fill constructor in 
`selectUnmergeValues()` as potentially reading `NumInsertRegs *
sizeof(Register)`
bytes from the 16-byte inline buffer of `SmallVector<Register, 4>`,
emitting:

```
warning: reading between 20 and 17179869180 bytes from a region of size 16 [-Wstringop-overread]
```

Replacing the constructor-then-move with `assign()` fills the already-live object in place,
which GCC can analyze correctly.


    [6 lines not shown]
DeltaFile
+4-0llvm/tools/llvm-jitlink/CMakeLists.txt
+1-1llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+5-12 files

LLVM/project e3813eflld/COFF ICF.cpp

rm stray semi
DeltaFile
+1-1lld/COFF/ICF.cpp
+1-11 files

LLVM/project ce515bcmlir/include/mlir-c Interfaces.h, mlir/lib/CAPI/Interfaces Interfaces.cpp CMakeLists.txt

[mlir-c] Add RegionBranchOpInterface C API bindings
DeltaFile
+57-0mlir/test/CAPI/ir.c
+27-0mlir/lib/CAPI/Interfaces/Interfaces.cpp
+22-0mlir/include/mlir-c/Interfaces.h
+1-0mlir/lib/CAPI/Interfaces/CMakeLists.txt
+107-04 files

LLVM/project 2a711f6clang/lib/Driver/ToolChains/Arch X86.cpp

[Arch][X86] Raising FreeBSD low requirement to pentium4 (#183554)

Using pentium4 by default allows us to build 32bit compiler-rt.builtins
on x86_64 platform since _Float16 requires SSE2, which is only available
after pentium3. Since FreeBSD does not support x86 after 16-CURRENT. It
makes sense to put the x86_64 compatibility first.

In FreeBSD's base, we set the target to i686 with -sse2 to build 32bit
compiler-rt.builtins. But we don't ship x86 compiler-rt.builtins in our
llvm port.
DeltaFile
+0-2clang/lib/Driver/ToolChains/Arch/X86.cpp
+0-21 files

LLVM/project d4b11efllvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.fmed3.ll

[AMDGPU] Guard fneg-into-fmed3 fold with nnan (#203827)
DeltaFile
+16-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
+6-0llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+23-73 files

LLVM/project 86db679mlir/include/mlir-c Interfaces.h, mlir/lib/CAPI/Interfaces Interfaces.cpp CMakeLists.txt

[mlir-c] Add DestinationStyleOpInterface C API bindings
DeltaFile
+58-0mlir/test/CAPI/ir.c
+42-0mlir/lib/CAPI/Interfaces/Interfaces.cpp
+38-0mlir/include/mlir-c/Interfaces.h
+1-0mlir/lib/CAPI/Interfaces/CMakeLists.txt
+139-04 files

LLVM/project e86a260flang/include/flang/Parser openmp-utils.h, flang/lib/Lower/OpenMP Clauses.cpp

[flang][OpenMP] Use utility functions to get things from OmpObject (#206066)

Instead of using std::get_if or parser::Unwrap, use utility functions.
This also adds two additional functions: GetLocatorFromObj and
GetCommonBlockFromObj.
DeltaFile
+12-17flang/lib/Semantics/check-omp-structure.cpp
+7-8flang/lib/Semantics/openmp-utils.cpp
+11-3flang/lib/Parser/openmp-utils.cpp
+3-3flang/lib/Lower/OpenMP/Clauses.cpp
+3-0flang/include/flang/Parser/openmp-utils.h
+1-1flang/lib/Semantics/resolve-directives.cpp
+37-321 files not shown
+38-337 files

LLVM/project 0249877llvm/lib/Target/Lanai LanaiTargetMachine.h

[Lanai] Mark as verifier clean

Now that we have fixes for verifier failures on all the in-tree tests,
we can mark Lanai as verifier clean.

Reviewers: jpienaar

Pull Request: https://github.com/llvm/llvm-project/pull/206202
DeltaFile
+0-4llvm/lib/Target/Lanai/LanaiTargetMachine.h
+0-41 files

LLVM/project e610b01clang/lib/CIR/CodeGen CIRGenExprConstant.cpp, llvm/test/CodeGen/RISCV/GlobalISel atomicrmw-and-or-xor.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+10,260-9,388llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
+0-7,069llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+5,907-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc-fake16.txt
+3,268-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-and-or-xor.ll
+2,020-0llvm/test/MC/M68k/MOVE.s
+308-868clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+21,763-17,3251,110 files not shown
+51,392-29,9621,116 files

FreeBSD/ports 638ebd4filesystems/py-libzfs distinfo Makefile

filesystems/py-libzfs: v2.0.1

This fixes a bug with the ZFSVdev.Replace method.

https://github.com/asomers/py-libzfs/releases/tag/v2.0.1

Sponsored by:   ConnectWise
DeltaFile
+3-3filesystems/py-libzfs/distinfo
+1-1filesystems/py-libzfs/Makefile
+4-42 files

LLVM/project d9afdcfllvm/test/CodeGen/Lanai llc-pipeline-npm.ll codemodel.ll

[Lanai] Add test coverage for NewPM

Just duplicate all the RUN lines to additionally call llc with the NewPM
given there are only a handful of tests.

Reviewers: jpienaar

Pull Request: https://github.com/llvm/llvm-project/pull/206200
DeltaFile
+93-0llvm/test/CodeGen/Lanai/llc-pipeline-npm.ll
+4-0llvm/test/CodeGen/Lanai/codemodel.ll
+3-0llvm/test/CodeGen/Lanai/mem_alu_combiner.ll
+3-0llvm/test/CodeGen/Lanai/delay_filler.ll
+1-0llvm/test/CodeGen/Lanai/comparisons_i32.ll
+1-0llvm/test/CodeGen/Lanai/constant_multiply.ll
+105-018 files not shown
+123-024 files

LLVM/project 7321eb8clang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp, clang/test/CIR/Transforms/abi-lowering coerce-direct-offset.cir

[CIR] Honor Direct coercion offset in callconv

A Direct classification with a coerced type assumed the coerced value
started at byte 0 of the original aggregate.  On x86-64 SysV a 16-byte
record whose low eightbyte is NO_CLASS carries its live value in the high
eightbyte and is classified as getDirect(coerceType, offset=8); the
coercion path read and wrote the wrong eightbyte for that shape.

Add a directOffset to ArgClassification (with a getDirect(coerced, offset)
overload).  emitCoercionToMemory now applies the offset to the coerced
(scalar) side of the slot via a u8 ptr_stride before the typed view, so the
aggregate side stays at offset 0 while the scalar is read from / written to
the right bytes.  The offset is threaded through both emitCoercion overloads,
insertReturnCoercion, and the call-site and entry-block Direct arms.  Offset
0 takes the original plain-bitcast path and is byte-identical to before.

The Test target parser gains an optional direct_offset key so cir-opt can
inject this classification; coerce-direct-offset.cir covers the offset-8
return and argument plus an offset-0 negative case.
DeltaFile
+66-34clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+75-0clang/test/CIR/Transforms/abi-lowering/coerce-direct-offset.cir
+15-3mlir/lib/ABI/Targets/Test/TestTarget.cpp
+13-0mlir/include/mlir/ABI/ABIRewriteContext.h
+5-2mlir/include/mlir/ABI/Targets/Test/TestTarget.h
+174-395 files

LLVM/project c16aa6aclang/lib/CIR/CodeGen CIRGenExprConstant.cpp, llvm/test/CodeGen/RISCV/GlobalISel atomicrmw-and-or-xor.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+10,260-9,388llvm/test/MC/AMDGPU/gfx11_asm_vopc.s
+0-7,069llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc.txt
+5,907-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vopc-fake16.txt
+3,268-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-and-or-xor.ll
+2,020-0llvm/test/MC/M68k/MOVE.s
+308-868clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
+21,763-17,3251,110 files not shown
+51,392-29,9621,116 files

LLVM/project 1b7c3e5llvm/lib/Target/Lanai LanaiInstrInfo.td, llvm/test/CodeGen/Lanai machine-verifier-regression.ll sub-cmp-peephole.ll

[Lanai] BRCC should not set isBarrier

BRCC allows fall through, so we need to set isBarrier = 0, otherwise we
get machine verifier failures.

Co-Authored-By: Jacques Pienaar <jpienaar at google.com>

Reviewers: jpienaar

Pull Request: https://github.com/llvm/llvm-project/pull/206195
DeltaFile
+32-0llvm/test/CodeGen/Lanai/machine-verifier-regression.ll
+3-3llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll
+2-2llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.generated.expected
+2-2llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.nogenerated.expected
+2-1llvm/lib/Target/Lanai/LanaiInstrInfo.td
+41-85 files