OPNSense/core 78e7de1src/opnsense/mvc/app/models/OPNsense/Firewall Filter.xml

Firewall: Rules [new] - rename model description and add "any" direction option to be inline with legacy implementation
DeltaFile
+2-1src/opnsense/mvc/app/models/OPNsense/Firewall/Filter.xml
+2-11 files

LLVM/project 0689a59clang/include/clang/Basic DiagnosticParseKinds.td, clang/lib/Parse ParseOpenMP.cpp

[NFC] [OpenMP] Fix typo and add initializer to modifier. (#174784)

Fixed typo and added initialization of modifier.
DeltaFile
+2-0clang/lib/Parse/ParseOpenMP.cpp
+1-1clang/include/clang/Basic/DiagnosticParseKinds.td
+1-1clang/test/OpenMP/need_device_ptr_kind_messages.cpp
+4-23 files

LLVM/project c8674f6llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 combine-fma-concat.ll

[X86] combineConcatVectorOps - IsConcatFree - detect splats that comes from a common load/broadcastload (#174986)

Allows us to handle freely concatable cases after a broadcast load has
become shared by different vector width uses by peeking through
bitcasts/extract_subvector nodes
DeltaFile
+25-16llvm/test/CodeGen/X86/combine-fma-concat.ll
+7-1llvm/lib/Target/X86/X86ISelLowering.cpp
+32-172 files

LLVM/project da560b6llvm/lib/Target/RISCV/MCTargetDesc RISCVInstPrinter.cpp RISCVInstPrinter.h, llvm/test/MC/RISCV hex-imm-macho.s

[RISC-V][Mach-O] Print immediate operands in hexadecimal format. (#174505)

This is done for logical operations and auipc/lui.

Patch based on code written by Tim Northover.
DeltaFile
+17-1llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+16-0llvm/test/MC/RISCV/hex-imm-macho.s
+2-0llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
+35-13 files

LLVM/project f5c39a6llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/transcoding ConvertPtrInGlobalInit.ll

[SPIRV] Additional fixes for const init via `UtoPtr` (#172584)

#166494 added support for using `inttoptr` in global initialisation, and
lowering int into `OpSpecConstantOp OpConvertUToPtr`. Unfortunately, it
slightly more subtle case / exposed an existing issue around the `COPY`
pseudo-op. This patch ensures that we glance through a `COPY` when
figuring out whether an `OpConvertUToPtr` is actually operating on a
global. We also correctly handle the case where a `G_PTR_ADD` is used by
an `OpSpecConstantOp` in the context of global initialisation, which
would otherwise lead to broken SPIR-V wherein the latter would reference
a non constant Op.

---------

Co-authored-by: Marcos Maronas <marcos.maronas at intel.com>
DeltaFile
+4-3llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+2-1llvm/test/CodeGen/SPIRV/transcoding/ConvertPtrInGlobalInit.ll
+6-42 files

LLVM/project 5ca6327llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll ran-out-of-sgprs-allocation-failure.mir

[InlineSpiller][AMDGPU] Implement subreg reload during RA spill

Currently, when a virtual register is partially used, the
entire tuple is restored from the spilled location, even if
only a subset of its sub-registers is needed. This patch
introduces support for partial reloads by analyzing actual
register usage and restoring only the required sub-registers.
This improvement enhances register allocation efficiency,
particularly for cases involving tuple virtual registers.
For AMDGPU, this change brings considerable improvements
in workloads that involve matrix operations, large vectors,
and complex control flows.
DeltaFile
+3,429-4,107llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+81-102llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+35-56llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+91-0llvm/test/CodeGen/AMDGPU/skip-partial-reload-for-16bit-regaccess.mir
+40-40llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
+26-52llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+3,702-4,35767 files not shown
+4,016-4,57173 files

LLVM/project 5bae7a3llvm/test/CodeGen/AMDGPU regpressure-mitigation-with-subreg-reload.mir

[AMDGPU] Test precommit for subreg reload

This test currently fails due to insufficient
registers during allocation. Once the subreg
reload is implemented, it will begin to pass
as the partial reload help mitigate register
pressure.
DeltaFile
+37-0llvm/test/CodeGen/AMDGPU/regpressure-mitigation-with-subreg-reload.mir
+37-01 files

LLVM/project 64d13e3llvm/lib/Target/AMDGPU SIRegisterInfo.cpp SIRegisterInfo.h

[AMDGPU] Put back ProperlyAlighedRC helper functions

Putting back the functions that are recently deleted
as they were found unused. They are needed for
implementing subreg reload during RA.
DeltaFile
+22-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+5-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+27-02 files

LLVM/project b86e3c5llvm/include/llvm/CodeGen LiveRangeEdit.h, llvm/lib/CodeGen LiveRangeEdit.cpp

[CodeGen] Enhance createFrom for sub-reg aware cloning

Instead of just cloning the virtual register, this
function now creates a new virtual register derived
from a subregister class of the original value.
DeltaFile
+9-1llvm/lib/CodeGen/LiveRangeEdit.cpp
+5-2llvm/include/llvm/CodeGen/LiveRangeEdit.h
+14-32 files

LLVM/project 81b204dllvm/include/llvm/CodeGen TargetRegisterInfo.h, llvm/lib/CodeGen TargetRegisterInfo.cpp

[AMDGPU] Make AMDGPURewriteAGPRCopyMFMA aware of subreg reload

AMDGPURewriteAGPRCopyMFMA pass is currently not subreg-aware.
In particular, the logic that optimizes spills into COPY
instructions assumes full register reloads. This becomes
problematic when the reload instruction partially restores
a tuple register. This patch introduces the necessary changes
to make this pass subreg-aware, for a future patch that
implements subreg reload during RA.
DeltaFile
+41-1llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+10-0llvm/lib/CodeGen/TargetRegisterInfo.cpp
+3-0llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+54-13 files

LLVM/project da3d4c3llvm/test/CodeGen/AMDGPU ran-out-of-sgprs-allocation-failure.mir ra-inserted-scalar-instructions.mir

[AMDGPU] Introduce Offset field in SGPR spill Pseudos

Currently, SGPR spill pseudo-instructions lack
an offset field to represent non-zero stack offsets.
This patch introduces an additional offset field to
SGPR spill pseudo-instructions and updates all
relevant passes that handle spill lowering to support
this new field. This field is essential for a future
patch that implements subreg reload of tuple registers
from their stack location during RA.
DeltaFile
+26-26llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+22-22llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
+16-16llvm/test/CodeGen/AMDGPU/remat-sop.mir
+14-14llvm/test/CodeGen/AMDGPU/remat-smrd.mir
+9-9llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
+8-8llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
+95-9535 files not shown
+164-16241 files

LLVM/project 089bb8ellvm/lib/Target/AMDGPU SIRegisterInfo.cpp SIRegisterInfo.h

[AMDGPU] Make getNumSubRegsForSpillOp externally available (NFC).
DeltaFile
+3-3llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-0llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+5-32 files

OPNSense/src 81a777bsys/netpfil/pf pf.c

pf: Fix handling of IPv6 divert packets
DeltaFile
+72-5sys/netpfil/pf/pf.c
+72-51 files

LLVM/project 9fb45c5llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 extractelements-subnodes-same-index.ll insert-subvector.ll

[SLP]Do not generate extractelement subnodes with the same indeces

The compiler should not generate subvectors with the same extractelement
instructions, it may cause a crash and leads to inefficient
vectorization.

Fixes #174773
DeltaFile
+113-0llvm/test/Transforms/SLPVectorizer/X86/extractelements-subnodes-same-index.ll
+3-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1-3llvm/test/Transforms/SLPVectorizer/X86/insert-subvector.ll
+117-43 files

LLVM/project 218b3a5clang/lib/Analysis/LifetimeSafety LifetimeAnnotations.cpp, clang/test/Sema warn-lifetime-analysis-nocfg.cpp

only-for-owners
DeltaFile
+3-1clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
+2-1clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
+5-22 files

NetBSD/pkgsrc M2iXbq5doc CHANGES-2026

   Updated security/libsodium, math/py-gwcs
VersionDeltaFile
1.185+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc DxkcHqHmath/py-gwcs PLIST distinfo

   py-gwcs: updated to 0.26.1

   0.26.1 (2025-11-19)

   - Fix an indexing bug in ``spectroscopy.SellmeierZemax`` where the output ``n`` for array-type wavelength
     inputs had the correct shape, but had the same value for all elements.
   - Deprecate the private ``_toindex`` function in favor of a public ``to_index`` function.


   0.26.0 (2025-09-18)

   - Fix the computation of ``lon_pole`` for Zenitahl projections and declination of +/-90 deg.
   - Enable ``inputs_mapping`` in ``selector.LabelMapperArray``.
   - Deprecate ``with_units`` argument in favor of the high level Shared API.
VersionDeltaFile
1.4+44-4math/py-gwcs/PLIST
1.6+4-4math/py-gwcs/distinfo
1.14+3-3math/py-gwcs/Makefile
+51-113 files

FreeBSD/doc f01d6d9documentation/content/en/books/handbook introduction.adoc

books/handbook: version bump for 15.0
DeltaFile
+1-1documentation/content/en/books/handbook/introduction.adoc
+1-11 files

LLVM/project 79fd11cclang/lib/Headers avx512vlbwintrin.h

[Headers][X86] __builtin_ia32_pmovwb128_mask is not constexpr (#174985)

Appears to be a copy+paste type - most of the x86 masked truncation intrinsics still can't be made constexpr at this time

Fixes #166814
DeltaFile
+2-2clang/lib/Headers/avx512vlbwintrin.h
+2-21 files

LLVM/project 9973e38llvm/include/llvm/CodeGen SDPatternMatch.h, llvm/unittests/CodeGen SelectionDAGPatternMatchTest.cpp

[SDPatternMatch] Add m_FAbs matcher (#174975)

Adds a pattern matcher for floating-point absolute value (ISD::FABS),
following the same pattern as m_Abs for integer absolute value.

Fixes #174751
DeltaFile
+6-0llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+4-0llvm/include/llvm/CodeGen/SDPatternMatch.h
+10-02 files

LLVM/project 012097dcompiler-rt/lib/builtins/aarch64 sme-abi.S

[compiler-rt][AArch64] Exit early from __arm_za_disable. (#174942)

Because `__arm_za_disable` is a private-ZA function, it's only ever
entered with ZA state `off` or `dormant`. If the state is `off` then we
can safely return and there is no need to call `__arm_tpidr2_save` or to
explicitly set PSTATE.ZA or TPIDR2_EL0 to zero.
DeltaFile
+7-0compiler-rt/lib/builtins/aarch64/sme-abi.S
+7-01 files

NetBSD/pkgsrc 5ACvh3usecurity/libsodium distinfo, security/libsodium/patches patch-src_libsodium_crypto__ipcrypt_crypto_ipcrypt.c patch-src_libsodium_crypto__ipcrypt_ipcrypt__armcrypto.c

   libsodium: add upstream commits as comments
VersionDeltaFile
1.22+4-4security/libsodium/distinfo
1.2+2-1security/libsodium/patches/patch-src_libsodium_crypto__ipcrypt_crypto_ipcrypt.c
1.2+2-1security/libsodium/patches/patch-src_libsodium_crypto__ipcrypt_ipcrypt__armcrypto.c
1.2+2-1security/libsodium/patches/patch-src_libsodium_include_sodium_crypto__ipcrypt.h
+10-74 files

NetBSD/pkgsrc PxELpm2security/libsodium distinfo PLIST, security/libsodium/patches patch-src_libsodium_crypto__ipcrypt_ipcrypt__armcrypto.c patch-src_libsodium_crypto__ipcrypt_crypto_ipcrypt.c

   libsodium: updated to 1.0.21

   * Version 1.0.21-stable
    - Export missing crypto_ipcrypt_nd_keygen() helper function.
    - Fixed compilation with GCC on aarch64.

   * Version 1.0.21
     This point release includes all the changes from 1.0.20-stable, which
   include a security fix for the `crypto_core_ed25519_is_valid_point()`
   function, as well as two new sets of functions:
    - The new `crypto_ipcrypt_*` functions implement mechanisms for securely
   encrypting and anonymizing IP addresses as specified in https://ipcrypt-std.github.io
    - The `sodium_bin2ip` and `sodium_ip2bin` helper functions have been added
   to complement the `crypto_ipcrypt_*` functions and easily convert addresses
   between bytes and strings.
    - XOF: the `crypto_xof_shake*` and `crypto_xof_turboshake*` functions
   are standard extendable output functions. From input of any length, they can
   derive output of any length with the same properties as hash functions. These
   primitives are required by many post-quantum mechanisms, but can also be used

    [2 lines not shown]
VersionDeltaFile
1.1+34-0security/libsodium/patches/patch-src_libsodium_crypto__ipcrypt_ipcrypt__armcrypto.c
1.1+19-0security/libsodium/patches/patch-src_libsodium_crypto__ipcrypt_crypto_ipcrypt.c
1.1+17-0security/libsodium/patches/patch-src_libsodium_include_sodium_crypto__ipcrypt.h
1.21+7-6security/libsodium/distinfo
1.12+7-1security/libsodium/PLIST
1.19+3-4security/libsodium/Makefile
+87-112 files not shown
+89-138 files

LLVM/project 21dc73flibcxx/include any

[libc++][NFC] Update <any> to a more modern code style (#174619)

This patch refactors `enable_if`s inside `<any>` to use the `..., int> =
0` variant that we try to use throughout the code base and inlines some
of the functions into the class body to avoid duplicating the
`enable_if`s.
DeltaFile
+44-62libcxx/include/any
+44-621 files

FreeBSD/src 16f8ea6sys/amd64/conf MINIMAL GENERIC

amd64: Remove tpm(4) from GENERIC for now

It breaks suspend/resume and no one has had time to investigate and fix
it.

PR:             291067
Reviewed by:    emaste
Fixes:          3deb21f1afd5 ("random: TPM_HARVEST should have been named RANDOM_ENABLE_TPM")
Differential Revision:  https://reviews.freebsd.org/D54587
DeltaFile
+2-1sys/amd64/conf/MINIMAL
+2-1sys/amd64/conf/GENERIC
+4-22 files

FreeBSD/ports d0f5025textproc/py-mdformat Makefile distinfo, textproc/py-mdformat/files patch-pyproject.toml patch-src_mdformat___conf.py

textproc/py-mdformat: Update to 1.0.0

- Remove files/patch-pyproject.toml
- Fix pyproject.toml (via a post-patch target), because the build
  framework does not recognise its new format.
  (see https://packaging.python.org/en/latest/guides/writing-pyproject-toml/#license-and-license-files )
- Pet port(clippy|fmt)

ChangeLog:      https://mdformat.readthedocs.io/en/stable/users/changelog.html#id1
DeltaFile
+12-10textproc/py-mdformat/Makefile
+0-13textproc/py-mdformat/files/patch-pyproject.toml
+5-4textproc/py-mdformat/files/patch-src_mdformat___conf.py
+3-3textproc/py-mdformat/distinfo
+20-304 files

LLVM/project a4f1798clang/lib/Parse ParseDeclCXX.cpp, clang/test/Parser cxx2c-trivially-relocatable.cpp

[Clang] expunge `trivially_relocate_if_eligible` (#174344)

In Kona, WG21 decided to revert trivial relocation (P2786).

Keep the notion of relocatability
(used in the wild and likely to come back),
but remove the keyword which is no longer conforming
DeltaFile
+0-148clang/test/SemaCXX/ptrauth-type-traits.cpp
+0-123clang/test/SemaCXX/cxx2c-trivially-relocatable.cpp
+5-46clang/lib/Parse/ParseDeclCXX.cpp
+0-43clang/test/SemaCXX/trivially-relocatable-ptrauth.cpp
+0-31clang/test/Parser/cxx2c-trivially-relocatable.cpp
+0-24clang/test/SemaCXX/ptrauth-triviality.cpp
+5-41510 files not shown
+13-47916 files

NetBSD/src U6FmGGbdistrib/sets/lists/comp md.i386 md.amd64

   Mark all gcc=10 headers as unconditionally obsolete.
VersionDeltaFile
1.215+85-169distrib/sets/lists/comp/md.i386
1.310+85-169distrib/sets/lists/comp/md.amd64
1.113+21-41distrib/sets/lists/comp/ad.powerpc
1.2514+13-25distrib/sets/lists/comp/mi
1.116+11-21distrib/sets/lists/comp/ad.arm
1.62+7-13distrib/sets/lists/comp/ad.aarch64
+222-43811 files not shown
+251-48517 files

LLVM/project 5c324b5llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-use-after-erase.ll

use `Value *` instead of useless `WeakVH`
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+2-0llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
+3-12 files

OPNSense/core 1b11fca. plist, src/opnsense/mvc/app/models/OPNsense/Radvd Radvd.xml

Add VipLinkLocalField for the source_address validation
DeltaFile
+111-0src/opnsense/mvc/app/models/OPNsense/Radvd/FieldTypes/VipLinkLocalField.php
+2-2src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.xml
+1-0plist
+114-23 files