[Hexagon] Add the predicated HLX temporary load instruction (#242292)
Add assembler and disassembler support for the V85 HLX instruction "if
(Pv4) Ld16.tmp = mem(Rs32)".
Assisted by AI
Co-authored-by: Alexey Karyakin <akaryaki at qti.qualcomm.com>
[Hexagon] Lower HLX vector pair stack accesses to LL16b.tmp/SS16b.new (#242289)
HLX pair registers are interleaved, so a plain load or store of an HLX
vector pair is not equivalent to two HLX vector memory accesses and
cannot be selected. Clang still creates such accesses for pair locals
and arguments at -O0, and llc fails with "Cannot select" on them.
Rewrite aligned, non-volatile, non-atomic loads and stores without
!nontemporal on HLX vector pair allocas that survive optimization into
the LL16b.tmp/SS16b.new intrinsics, which define the pair memory layout.
Other pair memory accesses are left unchanged.
Assisted by AI
[mlir][tosa] Add pass to reduce reshapes (#239661)
Add tosa-reduce-reshapes to propagate rank-expanding reshapes backward
through elementwise operations and casts. This lets consecutive reshapes
compose and reshapes of constants fold.
libdoom-umapinfo: Update to 2.0.1
2.0.1 2026-10-31 Release
--------------------------
Fixed:
- Add missing braces for initializer of union doom_umi2_i_value_data
- Cleanup in codepath for read error of command line utility
[Hexagon] Add HLX codegen tests for mul, shift, select, pair arguments (#242290)
Add coverage for HLX lowering that is already supported but untested:
widening and high-half multiplies, v1024i32 shifts with vector shift
amounts, select on HLX vectors and pairs, interleaved single/pair
argument registers, and the diagnostics for unsupported HLX
operation/type combinations.
Assisted by AI
Co-authored-by: Sergei Larin <slarin at qti.qualcomm.com>
Co-authored-by: Poornima M Patgar <pmpatgar at qti.qualcomm.com>
[Hexagon] Add HLX pair spill support (#242186)
Expand HLX register-pair spills and reloads into two single-vector
memory operations using VTCM stack slots.
Co-authored-by: Yashas Andaluri <yandalur at qti.qualcomm.com>
---------
Co-authored-by: Yashas Andaluri <yandalur at qti.qualcomm.com>
[BasicAA] Preserve GEP element sizes at the pointer index width (#242013)
Converting a GEP element size to `unsigned` truncates sizes of 4 GiB or
more, so BasicAA can return `MustAlias` for different pointers. Constructing
the scale also asserts if the size does not fit a narrower pointer
index.
Construct the `APInt` directly from the full allocation size, allowing
truncation only to the pointer index width.
Fixes #242012.
Assisted-by: Claude Code
Assisted-by: OpenAI Codex
Co-authored-by: Nikita Popov <npopov at redhat.com>
clock_gettime: Add capability mode check
clock_gettime is permitted in capability mode, and it calls get_cputime
if clock_id is negative. get_cputime did not check the target pid in
capability mode.
Reported by: llm-postcr
Reviewed by: markj, Osvaldo Janeri Filho <ojanerif at amd.com>
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D61469
