ports-mgmt/pkg-devel: update to 2.8.99.2
Changes:
- fix build with openssl4 (which drop supports for old version of
signatures)
- support longarch64
- solver: hold an upgrade back instread of removing an explicitly
installed package
- solver: require an explicit confirmation before remove installed
package
- solver report why each installed package is planed to be removed
- scheduler: fix support for shlibs ordering and provider/requires
ordering
- checksum add sha512
- repo: fix hang when using a hashed repository
- repo: keep previously fetched catalogue when an update failes
- fetch detect http server that do not carry a 304 Not Modified
- metalog: escape spaces
- config: make PKG_CONFIG_FILE a configuration variable
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[X86][StackClash] Fix guard page skip with -fstack-clash-protection (#230951)
- issue: https://github.com/llvm/llvm-project/issues/230949
- Fixes possible guard page skip while using `-fstack-clash-protection`.
- If `AlignOffset = 0`, and `Offset` is a multiple of `StackProbeSize`,
the "N-1 pages" loop will leave:
`ChunkSize = Offset - CurrentOffset = StackProbeSize`.
- This is problematic since the tail allocation does not add a probe, as
it assumes `ChunkSize < StackProbeSize`.
So it will allocate `StackProbeSize` without a probe.
[IR] Use getFirstNonPHIIt for unreachable handling (NFC) (#233020)
This patch replaces BasicBlock::getFirstNonPHIOrPseudoProbe with
BasicBlock::getFirstNonPHIIt when checking whether a block contains only
an UnreachableInst or when replacing a dead block with an
UnreachableInst in SCCP.
Note that llvm.pseudoprobe is marked nounwind and willreturn, so
SimplifyCFG eliminates pseudo probes preceding an UnreachableInst, and
SCCP does not need to preserve leading pseudo probes when erasing dead
blocks.
Assisted-by: Antigravity
graphics/simpleviewer: update the port to the last 3.1.x release
- The project had moved to GitHub, adjust WWW and Makefile logic
accordingly, shorten the COMMENT while here
- Regenerate `CMakeLists.txt' patch due to changes made upstream
(mostly cosmetic)
Return conflicting compositions from addComposite immediately
Check for an existing composition up front: return a conflicting one
right away, instead of after updating B's ranges from a composition that
isn't recorded. This no longer needs the try_emplace result. The
generated code for all in-tree targets is unchanged, and the instruction
count is the same.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Interfaces: Assignments - minor cleanup in "Prefix delegation size", make field required to avoid none and blank both being valid options. Since "none" was the previous default, let's keep it that way for now.
Initialize targets before creating a LibraryOptionsContext. NFC (#233041)
Initialize the targets to register their library options, before parsing
command line arguments.
This prepares for removing the T::Global fallback in
`LibraryOptionsContext::get<T>()`.
(The -mtriple change of llvm-split was originally added for
AMDGPU --lto-partitions #83128)
[LTO,lld] Set -mllvm library options in the LTO context. NFC (#233026)
Follow-up to #231407: move tools off cl::ParseCommandLineOptions, which
sets the libraries' `XXXOptions::Global`, to
`cl::parseCommandLineOptions(LibraryOptionsContext &, ...)`.
lto::Config::LibraryOptions replays into every LLVMContext that LTO
creates: the regular LTO context, each ThinLTO backend, and split code
generation.
This prepares for removing the T::Global fallback in
LibraryOptionsContext::get<T>().
LLM-aided
TableGen: Look up sub-register index compositions in an array
compose() looked up each composition in a std::map. It is called for
every super-register class set in extendSuperRegClasses, and by
addComposite. Sub-register indices are numbered densely, so also keep
each index's compositions in an array indexed by enum value. For
AMDGPU's 400 indices this is about 1 MB.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 746 474 148
After 721 (-3.4%) 446 (-6.1%) 139 (-5.8%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Skip classes without matching super-register classes in RegisterBankEmitter
visitRegisterBankClasses checks every sub-register index for every pair
of register classes. Skip the per-index loop if RC is not in any of the
class's super-register class sets.
AMDGPU tablegen run for AMDGPUGenRegisterBank.inc:
Gigacycles CPU seconds
Before 51.7 16.0
After 48.4 (-6.4%) 14.9 (-6.9%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Insert super-register class sets in one step
extendSuperRegClasses added each super-register class to the composed
index's set with a separate addSuperRegClass call, which looks up the
set in the DenseMap every time. Look up the set once and insert the
whole range.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 797 489 153
After 755 (-5.2%) 477 (-2.4%) 149 (-2.5%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Free the sub-register map once the sorted array is built
The map is not modified after computeSuperRegs, so keep only the array,
with the sub-register index pointers so it can also be iterated, and
search it by the index's enum value.
AMDGPU tablegen runs that build the register bank:
Gigacycles CPU seconds Peak RSS (RegisterBank)
Before 541 169 857 MB
After 540 (-0.1%) 169 (+0.1%) 792 MB (-7.6%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Return early from addComposite for known compositions
computeComposites calls addComposite for each pair of sub-registers of
every register with a distinct sub-register structure, so most calls
repeat a composition that is already known. Each call still did three
std::map lookups per hardware mode to update the sub-register ranges.
If the composition already exists and its result has an offset in every
mode, the rest of the function has no effect, so return early. Cache
whether the result has an offset in every mode, since offsets are never
cleared once set.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 916 540 169
After 797 (-13.0%) 489 (-9.5%) 153 (-9.4%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
