[NFC][Linalg] Add `matchConvolutionOpOfType` API and make `isaConvolutionOpOfType` API a wrapper (#174722)
-- This commit involves the following updates pertaining to
`isaConvolutionOpOfType` API :-
1. We don't want dilations/strides of convolution op to be returned as
pointer arguments to the API function - to tackle this we create a new
API `matchConvolutionOpOfType` which would return an optional struct of
dilations/stride.
2. To not break the original API's use case as a simple querying
functionality with true/false return - we keep `isaConvolutionOpOfType`
as a wrapper API which will invoke `matchConvolutionOpOfType` API and
return true/false depending on whether `matchConvolutionOpOfType` API
returned any value or not.
3. Dilations/strides of named convolution op are also populated now (it
was missed in the previous PRs while creating `isaConvolutionOpOfType`).
4. [Max/Min]UnsignedPool ops' body matcher now only matches unsigned int
ops (refer: https://github.com/llvm/llvm-project/pull/166070)
-- No tests are being added as all the above are NFC changes around the
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[MLIR][Bufferization] Fold LoadOp only when the buffer is read only (#172595)
When we `memref.load` from a buffer, it folded to `tensor.extract` even
when the buffer was writable, causing unexpected results. For example:
```mlir
func.func @load_after_write_from_buffer_cast(%arg0: index, %arg1: index,
%arg2: tensor<?x?xf32>) -> f32 {
%0 = bufferization.to_buffer %arg2 : tensor<?x?xf32> to memref<?x?xf32>
linalg.ceil ins(%0 : memref<?x?xf32>) outs(%0 : memref<?x?xf32>)
%1 = memref.load %0[%arg0, %arg1] : memref<?x?xf32>
return %1 : f32
}
```
would fold into
```mlir
module {
func.func @load_after_write_from_buffer_cast(%arg0: index, %arg1: index, %arg2: tensor<?x?xf32>) -> f32 {
%0 = bufferization.to_buffer %arg2 : tensor<?x?xf32> to memref<?x?xf32>
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[clang-repl] Use more precise search to find the orc runtime. (#175805)
The new mechanism relies on the path in the toolchain which should be
the autoritative answer. This patch tweaks the discovery of the orc
runtime from unittests where the resource directory is hard to deduce.
Should address the issue raised in #175435 and #175322
[RISCV][llvm] Support select codegen for P extension (#175741)
This is scalar condition with fixed vector true/false value, we can just
handle it same as scalars.
[RISCV][llvm] Support vselect codegen for P extension (#175744)
The only difference between vselect vs. select is condition value(a.k.a.
mask), we can select by using bitwise operation:
vselect(mask, true, false) = (mask & true) | (~mask & false)
[CodeGen][NPM] Add support for -print-regusage in New Pass Manager (#169761)
Support `-print-regusage` flag in NPM for printing register usage information
Merge tag 'bpf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf
Pull bpf fixes from Alexei Starovoitov:
- Fix incorrect usage of BPF_TRAMP_F_ORIG_STACK in riscv JIT (Menglong
Dong)
- Fix reference count leak in bpf_prog_test_run_xdp() (Tetsuo Handa)
- Fix metadata size check in bpf_test_run() (Toke Høiland-Jørgensen)
- Check that BPF insn array is not allowed as a map for const strings
(Deepanshu Kartikey)
* tag 'bpf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf:
bpf: Fix reference count leak in bpf_prog_test_run_xdp()
bpf: Reject BPF_MAP_TYPE_INSN_ARRAY in check_reg_const_str()
selftests/bpf: Update xdp_context_test_run test to check maximum metadata size
bpf, test_run: Subtract size of xdp_frame from allowed metadata size
riscv, bpf: Fix incorrect usage of BPF_TRAMP_F_ORIG_STACK
security/bitwarden-cli: Update to 2025.12.1
While here, convert to use USES=electron for fetching and archiving
node modules, and adjust Makefile accordingly.
Changelog: https://github.com/bitwarden/clients/releases/tag/cli-v2025.12.1
Reported by: GitHub (watch releases)
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_S_MUL_*
Patch 3 of 4 patches to implement full G_MUL support in regbanklegalize.
Current mul.ll test is only partially updated and expected to fail.
It will be updated in the fourth patch.
[AMDGPU] Fix the encoding of VOP3PX2 instructions
ISA spec says `SCALE_OPSEL[0:1]` determines which parts of S3 and S4 are used, and `SCALE_OPSEL_HI[0:1]` should be zero.
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_AMDGPU_MAD_*
Patch 2 of 4 patches to implement full G_MUL support in regbanklegalize.
Current mul.ll test is only partially updated and expected to fail.
It will be updated in the fourth patch.
[AMDGPU][GlobalISel] Add partial RegBankLegalize support for G_MUL
Implement S16, S32, V2S16 support for G_MUL.
Part 1 of 4 patches to implement full G_MUL support in regbanklegalize.
Current mul.ll test is only partially updated due to missing S64 support that
will be implemented in the fourth patch thus mul.ll test will fail if it is run
without the fourth patch.
[AMDGPU] Fix the encoding of VOP3PX2 instructions
ISA spec says `SCALE_OPSEL[0:1]` determines which parts of S3 and S4 are used, and `SCALE_OPSEL_HI[0:1]` should be zero.
[flang][OpenMP] Fix LINEAR clause validation and test expectations (#175707)
Fixes #175688
After #175383 was merged, the test
`Semantics/OpenMP/linear-clause01.f90` was failing because it had an
early return that prevented multiple errors from being reported.
This PR fixes two issues:
1. **Removes the early return** after detecting a modifier error on
DO/SIMD directives. Previously, when a modifier error was found, the
function would return immediately without checking other restrictions
like the scalar requirement. Now all applicable errors are reported.
2. **Updates test expectations** to expect both the modifier error AND
the scalar error for Case 1, where `arg(:)` is an array used with `uval`
modifier on a DO directive.
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[llvm][LoongArch] Add PC-relative address materialization using pcadd instructions
This patch adds support for PC-relative address materialization using
pcadd-class relocations, covering the HI20/LO12 pair and their GOT and
TLS variants (IE, LD, GD, and DESC).
Link: https://gcc.gnu.org/pipermail/gcc-patches/2025-December/703312.html
[libc++][ranges][NFC] Merge `join_with_view`s `[[nodiscard]]` tests (#175734)
This just merges all tests in a single `nodiscard.verify.cpp` as is the
common practice.
asmc: Add support for MacBookPro11,5
Add support for the MacBookPro11,5 (Mid 2015, 15-inch with AMD Radeon R9 M370X GPU)
to the Apple SMC driver.
Debug testing revealed this model lacks several SMC keys present on MacBookPro11,4
(IBLC, ICMC, IC2C), that model-specific sensor definitions.
Differential Revision: https://reviews.freebsd.org/D54665
Reviewed by: adrian
Simplify vmd(8) structs, removing embedded vmm(4) structs.
This removes some hard dependencies from vmctl(8) on the structures
from vmm(4) and makes naming of identifiers more explicit.
Oh the surface, this is cosmetic, but the intention is to decouple
as much as possible from the dev/vmm/vmm.h to allow for upcoming
work to change vmm(4) without causing a large blast radius.
Testing help from mlarkin@ & bluhm@.
ok mlarkin@
