virtio: Restore mb() calls
Until an issue seen on amd64 can be investigated restore two mb() calls
to virtio.
Reviewed by: andrew
Fixes: c499ad6f997c ("virtio: Use bus_dma for ring and indirect buffer allocations")
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D55766
virtio: Restore mb() calls
Until an issue seen on amd64 can be investigated restore two mb() calls
to virtio.
Reviewed by: andrew
Fixes: c499ad6f997c ("virtio: Use bus_dma for ring and indirect buffer allocations")
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D55766
Use findAllocaInsertPoint when possible and move the affinity packing logic to OpenMPToLLVMIRTranslation
- Move the omp.affinity_list packing logic from OMPIRBuilder to
OpenMPToLLVMIRTranslation so that we have all the omp.affinity_list
allocating logic inside the lambda defined in buildAffinityData
- all the allocation logic for affinity list is now using
findAllocaInsertPoint when possible (static count)
- `task_affinity_iterator_dynamic_tripcount` in
openmp-iterator.mlir is a regression test add previously for
dynamic tripcount
[lld][WebAssembly] Restore inactive checks relocatable.ll test. NFC (#185569)
Back in 6474d1b20 this test was updated, removing the NORMAL vs SHARED
distinction in the output checking. However many of the NORMAL-NEXT
lines were left unmodified, making them effectively disabled.
This restores and updates the expectations.
[copmiler-rt] Initial support for building profile library on the GPU (#185552)
Summary:
As suggested in https://github.com/llvm/llvm-project/pull/177665, we
should build a GPU version of the compiler-rt profile library instead of
writing it in-line in the lowering. This PR does not define anything GPU
specific, it simply re-uses the baremetal handling. Later PRs will
prevent the GPU specific handling we would want to do to optimize
counter handling on the GPU.
Note that this will require using the cache file, or setting these
options
manually for existing users. Hopefully if people are using the cache
file
as they should it won't break anything.
Tor Browser: sync unveil changes from firefox-esr
Original commit message from landry@:
"www/firefox-esr: add some missing unveils
- content process already accesses /etc/localtime, add /usr/share/zoneinfo
- main process already has /usr/share/zoneinfo, add /etc/localtime
- main process sometimes parses /etc/hosts (mostly on network.trr.mode
changes ?) so unveil it.
- unveil.socket is wrong but time is running out, and the socket process
isnt used much anyway (network.http.network_access_on_socket_process.enabled defaults to false)
required by upcoming changes to pledge/unveil"
[SystemZ][z/OS] Remove use of subsections.
HLASM has no notion of subsections. There are several possible solutions
how to deal with this. However,
- using a different section introduces a lot of relocations, which slows
down the binder later
- emitting the PPA1 after the code changes the location which may break
existing tools
The choosen solution is to record the PPA1 data, and emit them at the
end of the assembly into the code section. This solves both issues,
at the expense of having to do some bookkeeping.
This change moves the position of the PPA2, too, but this is less
critical.
Add sancov support for large AArch64 binaries. (#185374)
In AArch64 calls have a +/-128MB range
(https://developer.arm.com/documentation/ddi0602/2025-12/Base-Instructions/BL--Branch-with-link-).
In cases where the .text is larger than that, the linker adds functions
that just jumps to the sanitizer functions and places them to some code
location where the rest of the binary can call it. These functions have
the prefix __AArch64ADRPThunk__.
This commit marks calls to this function as coverage points.
[AArch64][GlobalISel] Add G_SQDMULL node
Previously, GISel was failing to lower the sqdmulls.scalar intrinsic. This is just a variation of sqdmull, but on two 32-bit S registers.
To fix this, create a G_SQDMULL node, and lower sqdmulls.scalar to that. This node is linked to the SD patterns for sqdmull, which allow this version of the intrinsic to lower.
[AArch64][PAC] Don't skip global legalization for AUTH_TCRETURN (#182513)
The 77bcab835aca1 folds llvm.ptrauth.resign intrinsic in case intrinsic
discriminant and key match those in call ptrauth bundle. However
assertion is now fired in AArch64AsmPrinter when PAC is enabled and
we're tail calling a global, because AUTH_TCRETURN expects address to be
stored in register.
