LLVM/project dd4e284llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp, llvm/test/CodeGen/AMDGPU vgpr-setreg-mode-swar.mir hazard-setreg-vgpr-msb-gfx1250.mir

[AMDGPU] Fix setreg handling in the VGPR MSB lowering

There are multiple issues with it:

1. It can skip inserting S_SET_VGPR_MSB if we set the mode via
   piggybacking. We are now relying on the HW bug for correct
   behavior. If/when the bug is fixed lowering will be incorrect.
2. We should just unconditionally update MSBs if immediate allows it.
   We shall set correct bits and keep the rest of the immediate
   (that is done). There is no reasonable way for an user to change
   MSBs nor does it do anything good to set it with SETREG and then
   immediately overwrite with S_SET_VGPR_MSB.
3. We can always update immediate if Offset is zero.
4. Redundant mode changes created as seen in the
   hazard-setreg-vgpr-msb-gfx1250.mir.

With unconditional immediate update most of time and not relying on
the SETREG for setting MSBs there is no good reason to complicate
handling by supporting SETREG as a piggybacking target. Moreover,

    [10 lines not shown]
DeltaFile
+209-47llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
+27-40llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+12-18llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir
+248-1053 files

LLVM/project e8566f8lldb/bindings/interface SBModuleSpecListExtensions.i, lldb/test/API/python_api/sbmodule TestSBModule.py

[lldb][python] Add polymorphic `__getitem__` to `SBModuleSpecList` for Pythonic indexing (#189125)

### Summary

`SBModuleSpecList` already supports `len()` and iteration via `__len__`
and `__iter__`, but is not subscriptable — `specs[0]` raises
`TypeError`.

This adds a `__getitem__` method that supports integer indexing (with
negative index support) and string lookup using `endswith()` matching,
which works for both Unix and Windows paths.

### Supported key types

| Key type | Example | Behavior |
|---|---|---|
| `int` | `specs[0]`, `specs[-1]` | Direct index with negative index
support |
| `str` | `specs['a.out']`, `specs['/usr/lib/liba.dylib']` | Lookup by

    [64 lines not shown]
DeltaFile
+60-0lldb/test/API/python_api/sbmodule/TestSBModule.py
+21-9lldb/bindings/interface/SBModuleSpecListExtensions.i
+81-92 files

FreeBSD/ports 75ee539japanese/navi2ch pkg-plist Makefile

japanese/navi2ch: Refactor

Lint with portclippy.
Switch LISPDIR variable to NLISPDIR and add NICONDIR.
Switch from INSTALL_DATA to COPYTREE_SHARE.

PR:             291381
Approved by:    osa (mentor)
DeltaFile
+73-73japanese/navi2ch/pkg-plist
+10-10japanese/navi2ch/Makefile
+83-832 files

FreeBSD/ports f8cebdfjapanese/navi2ch Makefile

japanese/navi2ch: Take maintainership

Remove the mona font from the default option as ASCII art is becoming
obsolete.

PR:             291381
Approved by:    hrs (maintainer timeout)
Approved by:    osa (mentor)
DeltaFile
+2-3japanese/navi2ch/Makefile
+2-31 files

FreeBSD/ports 4225bc1japanese/navi2ch pkg-message Makefile, japanese/navi2ch/files patch-navi2ch-list.el patch-navi2ch-multibbs.el

japanese/navi2ch: Switch RUN_DEPENDS from p5-2chproxy to proxy2ch

Update GH_TAGNAME from faebfd1 to 7811dba.
Add NO_ARCH=yes.
Add a patch to accommodate the url change.
Update pkg-descr.

Changelog:
https://github.com/naota/navi2ch/compare/faebfd1...7811dba

PR:             291381
Approved by:    hrs (maintainer timeout)
Approved by:    osa (mentor)
DeltaFile
+28-0japanese/navi2ch/files/patch-navi2ch-list.el
+20-0japanese/navi2ch/files/patch-navi2ch-multibbs.el
+15-0japanese/navi2ch/files/patch-navi2ch-article.el
+12-3japanese/navi2ch/files/patch-navi2ch-vars.el
+4-4japanese/navi2ch/pkg-message
+4-2japanese/navi2ch/Makefile
+83-92 files not shown
+89-138 files

LLVM/project df461c1clang/lib/CIR/CodeGen CIRGenBuiltin.cpp, clang/test/CIR/CodeGenBuiltins builtin-fpclassify.c

[CIR][CodeGen] Implement __builtin_fpclassify (#187977)

I implemented CIR version of __builtin_fpclassify function.
DeltaFile
+356-0clang/test/CIR/CodeGenBuiltins/builtin-fpclassify.c
+79-1clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+435-12 files

LLVM/project a8cf1a0bolt/lib/Profile DataReader.cpp, bolt/test/X86 pre-aggregated-perf-buildid.test

[BOLT] Allow empty buildid in pre-aggregated profile addresses (#190675)

Allow `parseString()` to return an empty `StringRef` when the delimiter
appears at position 0. This enables parsing pre-aggregated profile
addresses with an omitted buildid but preserved colon (`:addr` format),
where the empty buildid corresponds to the main binary.

Previously, `parseString()` rejected zero-length fields by treating
`StringEnd == 0` the same as `StringRef::npos` (delimiter not found).
These are distinct situations: `npos` means no delimiter exists, while
`0` means the field before the delimiter is empty. The fix removes the
`StringEnd == 0` sub-condition so only the missing-delimiter case
errors.

The existing test for buildid-prefixed addresses is extended to also
verify that `:addr` input produces identical output to the plain-address
and non-empty-buildid variants.

Test Plan:

    [2 lines not shown]
DeltaFile
+9-0bolt/test/X86/Inputs/pre-aggregated-buildid-empty.txt
+8-0bolt/test/X86/pre-aggregated-perf-buildid.test
+1-2bolt/lib/Profile/DataReader.cpp
+18-23 files

LLVM/project ae57606clang/lib/ScalableStaticAnalysisFramework/Analyses SSAFAnalysesCommon.h

fix build issue
DeltaFile
+1-0clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
+1-01 files

LLVM/project 79e669fllvm/lib/CAS DatabaseFile.cpp

[CAS] Revert an unintentional change in #190634 (#190686)

Revert an unintentional change in #190634 that did an unintentional
implicit signed to unsigned cast.
DeltaFile
+1-1llvm/lib/CAS/DatabaseFile.cpp
+1-11 files

LLVM/project 8a11fe9llvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis Propagating.ll Banerjee.ll

[DA] Require `nsw` for AddRecs involved in GCD test (#186892)

Similar to other tests, we are adding code that the AddRecs used in GCD
test are `nsw`. In this case, all recursively identified `AddRec`s are
also checked. Note that there is already a similar check in
`getConstantCoefficient` for expressions processed in that function.
DeltaFile
+3-3llvm/test/Analysis/DependenceAnalysis/Propagating.ll
+2-2llvm/test/Analysis/DependenceAnalysis/Banerjee.ll
+2-0llvm/lib/Analysis/DependenceAnalysis.cpp
+1-1llvm/test/Analysis/DependenceAnalysis/exact-rdiv-addrec-wrap.ll
+8-64 files

LLVM/project 62ce560lldb/source/Plugins/Disassembler/LLVMC DisassemblerLLVMC.cpp

[lldb] Remove some unreachable code (NFC) (#190529)

`isRISCV()` check always returns false because we only get here if
`min_op_byte_size` and `max_op_byte_size` are equal, which is not true
for RISC-V.
Also, replase `if (!got_op)` check with an `else`. The check is
equivalent to
`if (min_op_byte_size != max_op_byte_size)`, and the `if` above checks
for the opposite condition.
DeltaFile
+3-15lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+3-151 files

FreeNAS/freenas b5c4001src/middlewared/middlewared/plugins etc.py api_key.py, src/middlewared/middlewared/plugins/auth_ login_ex_impl.py

NAS-140566 / 26.0.0-BETA.2 / Remove pam_truenas etc_group (by anodos325) (#18659)

At this point there's not really a strong reason to have a separate
pam_truenas etc group. The truenas-specific entries depend on what's
generated in regular pam etc group. This commit also fixes an issue
whereby PAM files weren't updated on remote controller when user enables
DS authentication. This commit also updates various call-sites to
generate pam rather than pam_truenas.

Original PR: https://github.com/truenas/middleware/pull/18657

---------

Co-authored-by: Andrew Walker <andrew.walker at truenas.com>
DeltaFile
+3-10src/middlewared/middlewared/plugins/etc.py
+4-4src/middlewared/middlewared/plugins/api_key.py
+5-1src/middlewared/middlewared/plugins/system_general/update.py
+2-2src/middlewared/middlewared/plugins/auth.py
+2-2src/middlewared/middlewared/plugins/auth_/login_ex_impl.py
+2-2tests/api2/test_audit_websocket.py
+18-214 files not shown
+22-2710 files

FreeNAS/freenas 3d6bf3bsrc/middlewared/middlewared/plugins etc.py api_key.py, src/middlewared/middlewared/plugins/auth_ login_ex_impl.py

NAS-140566 / 27.0.0-BETA.1 / Remove pam_truenas etc_group (#18657)

At this point there's not really a strong reason to have a separate
pam_truenas etc group. The truenas-specific entries depend on what's
generated in regular pam etc group. This commit also fixes an issue
whereby PAM files weren't updated on remote controller when user enables
DS authentication. This commit also updates various call-sites to
generate pam rather than pam_truenas.
DeltaFile
+3-10src/middlewared/middlewared/plugins/etc.py
+4-4src/middlewared/middlewared/plugins/api_key.py
+5-1src/middlewared/middlewared/plugins/system_general/update.py
+2-2src/middlewared/middlewared/plugins/auth.py
+2-2src/middlewared/middlewared/plugins/auth_/login_ex_impl.py
+2-2tests/api2/test_api_key.py
+18-214 files not shown
+22-2710 files

FreeBSD/ports e9587b9sysutils/zellij distinfo Makefile.crates, sysutils/zellij/files patch-zellij-client_src_lib.rs patch-cargo-crates_nix-0.23.1_src_sys_event.rs

sysutils/zellij: Update to 0.44.0

- Add dependency on SQLite
- Remove non-applicable patches
- Add a patch to fix panic on terminal close [0]

PR:             294250 [0]

Co-authored-by: Michael Johnson <ahze at ahze.net>
DeltaFile
+235-389sysutils/zellij/distinfo
+115-193sysutils/zellij/Makefile.crates
+52-0sysutils/zellij/files/patch-zellij-client_src_lib.rs
+27-0sysutils/zellij/files/patch-cargo-crates_nix-0.23.1_src_sys_event.rs
+26-0sysutils/zellij/files/patch-cargo-crates_polling-2.2.0_src_kqueue.rs
+6-14sysutils/zellij/files/patch-Cargo.lock
+461-5963 files not shown
+468-6149 files

LLVM/project 020b3b2clang/test/Analysis/Scalable/ssaf-format list.test

Update clang/test/Analysis/Scalable/ssaf-format/list.test

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
DeltaFile
+2-2clang/test/Analysis/Scalable/ssaf-format/list.test
+2-21 files

LLVM/project ef71584llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp

[NFC][AMDGPU] Add some debug prints to SIMemoryLegalizer (#190658)
DeltaFile
+69-0llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+69-01 files

LLVM/project 7087ecemlir/lib/ExecutionEngine CudaRuntimeWrappers.cpp, mlir/test/Integration/GPU/CUDA async.mlir

[MLIR][ExecutionEngine] Tolerate CUDA_ERROR_DEINITIALIZED in mgpuModuleUnload (#190563)

`mgpuModuleUnload` may be called from a global destructor (registered by
`SelectObjectAttr`'s `appendToGlobalDtors`) after the CUDA primary
context has already been destroyed during program shutdown. In this
case, `cuModuleUnload` returns `CUDA_ERROR_DEINITIALIZED`, which is
benign since the module's resources are already freed with the context.

## Reproduction

Any program that uses `gpu.launch_func` and is AOT-compiled (via
`mlir-translate --mlir-to-llvmir | llc | cc -lmlir_cuda_runtime`) will
print `'cuModuleUnload(module)' failed with '<unknown>'` on exit. This
is because `SelectObjectAttr` registers the module unload as a global
destructor, which runs after the CUDA primary context is released.

This script reproduces the error message from `mgpuModuleUnload` on my
system:


    [40 lines not shown]
DeltaFile
+29-5mlir/lib/ExecutionEngine/CudaRuntimeWrappers.cpp
+2-5mlir/test/Integration/GPU/CUDA/async.mlir
+31-102 files

LLVM/project af95b0allvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp2.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.i16.ll atomicrmw_uinc_wrap.ll

[AMDGPU] Remove implicit super-reg defs on mov64 pseudos   (#190379)

The mov64 pseudo is split into two 32 bit movs, but those 32 bit movs
had the full 64-bit register still implicitly defined. VOPD formation is
affected, so we can emit more of them.
DeltaFile
+279-279llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+254-254llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+166-278llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
+184-184llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+147-174llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+121-135llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
+1,151-1,30490 files not shown
+2,283-2,60696 files

LLVM/project 9bddf47mlir/lib/Dialect/XeGPU/Transforms XeGPUWgToSgDistribute.cpp, mlir/test/Dialect/XeGPU xegpu-wg-to-sg-unify-ops.mlir xegpu-wg-to-sg-unify-ops-rr.mlir

[MLIR][XeGPU] Extend Wg-to-Sg Distribution of Multi-Reduction Op for round-robin layout (#189988)

This PR enhance the multi-reduction op pattern of wg-to-sg distribution
pass:
1. allows each sg have multiple distribution of sg_data tiles.
2. expand the slm buffer size.
3. construct the layout based on the partial reduced vector and use
layout.computeDistributedCoords() to compute coordinates. the layout is
constructed so that the store is cooperative, and load overlapps with
neighbour threads.
4. perform save and load.
DeltaFile
+63-76mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
+8-68mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+52-0mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir
+123-1443 files

LLVM/project 9ab2b6dllvm/lib/CAS DatabaseFile.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+1-1llvm/lib/CAS/DatabaseFile.cpp
+1-11 files

LLVM/project 97d50c1llvm/lib/Target/AArch64 AArch64.h AArch64PassRegistry.def, llvm/lib/Target/AArch64/GISel AArch64PreLegalizerCombiner.cpp

[NewPM] Adds a port for AArch64PreLegalizerCombiner (#190567)

Standard porting (note that TargetPassConfig dependency was [removed
earlier](https://github.com/llvm/llvm-project/commit/e27e7e433974b24c90fed9f0b646bed84e47681e)).

---------

Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
DeltaFile
+92-30llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+15-1llvm/lib/Target/AArch64/AArch64.h
+2-0llvm/lib/Target/AArch64/AArch64PassRegistry.def
+1-1llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+1-0llvm/test/CodeGen/AArch64/GlobalISel/combine-2-icmps-of-0-and-or.mir
+111-325 files

LLVM/project ee51de9llvm/include/llvm/ProfileData/Coverage CoverageMapping.h, llvm/lib/ProfileData/Coverage CoverageMapping.cpp

[llvm-cov] add ability to show non executed test vectors for mc/dc coverage (#187517)

- Added `-show-mcdc-non-executed-vectors` option
- Non-executed test vectors now are tracked
- When the opt is present it's get written to UI
DeltaFile
+145-2llvm/test/tools/llvm-cov/mcdc-const.test
+132-4llvm/test/tools/llvm-cov/mcdc-general.test
+133-3llvm/test/tools/llvm-cov/mcdc-macro.test
+122-2llvm/test/tools/llvm-cov/mcdc-general-none.test
+64-35llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
+37-23llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
+633-696 files not shown
+774-10412 files

LLVM/project d917027llvm/lib/ProfileData/Coverage CoverageMapping.cpp, llvm/test/tools/llvm-cov main-view-fileid-regression.test

[llvm-cov] Guard against empty CountedRegions in findMainViewFileID (#189270)

When processing coverage generated from branch coverage mode, some
functions can reach findMainViewFileID with an empty CountedRegions
list. In that case the current logic still proceeds to infer the main
view file, even though there is no regular counted region available to
do so.

Return std::nullopt early when CountedRegions is empty.

This was observed when reproducing issue #189169 with:
  cargo llvm-cov --lib --branch

The issue appears related to branch-only coverage information being
recorded separately in CountedBranchRegions, while
findMainViewFileID currently only consults CountedRegions.
This patch is a defensive fix for the empty-region case; further
investigation may still be needed to determine whether branch regions
should participate in main view file selection.

Co-authored-by: Zile Xiong <xiongzile99 at gmail.com>
DeltaFile
+32-0llvm/test/tools/llvm-cov/Inputs/main-view-fileid-regression.proftext
+16-0llvm/test/tools/llvm-cov/main-view-fileid-regression.test
+2-0llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
+0-0llvm/test/tools/llvm-cov/Inputs/main-view-fileid-regression.covmapping
+50-04 files

LLVM/project 9033e87llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.update.dpp.ll regbankselect-amdgcn.update.dpp.mir

[AMDGPU][GISel] RegBankLegalize rules for update_dpp (#190662)
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
+4-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
+8-43 files

LLVM/project 9f30927clang/test/Headers __clang_hip_math.hip, llvm/test/CodeGen/AMDGPU clmul.ll integer-mad-patterns.ll

rebase

Created using spr 1.3.4
DeltaFile
+3,666-5,073llvm/test/CodeGen/RISCV/rvv/expandload.ll
+4,371-0llvm/test/CodeGen/AMDGPU/clmul.ll
+1,103-1,014clang/test/Headers/__clang_hip_math.hip
+1,318-117llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+835-387llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
+440-640llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+11,733-7,2311,387 files not shown
+49,773-26,5641,393 files

LLVM/project 260a784clang/test/Headers __clang_hip_math.hip, llvm/test/CodeGen/AMDGPU clmul.ll integer-mad-patterns.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]
DeltaFile
+3,666-5,073llvm/test/CodeGen/RISCV/rvv/expandload.ll
+4,371-0llvm/test/CodeGen/AMDGPU/clmul.ll
+1,103-1,014clang/test/Headers/__clang_hip_math.hip
+1,318-117llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+835-387llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
+440-640llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+11,733-7,2311,387 files not shown
+49,773-26,5641,393 files

LLVM/project 8966581llvm/include/llvm/Analysis BlockFrequencyInfoImpl.h

[Analysis][NFC] Use block numbers in BlockFrequencyInfo (#190669)

Block pointers are only stored while constructing the analysis, so the
value handle to catch erased blocks is no longer needed when using
stable block numbers.
DeltaFile
+59-109llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+59-1091 files

FreeNAS/freenas 8d642ab. CLAUDE.md, src/middlewared/middlewared/plugins/pool_ scrub.py

re-raise pylibzfs exceptions as `CallError`
DeltaFile
+50-30src/middlewared/middlewared/plugins/zpool/exceptions.py
+9-21src/middlewared/middlewared/plugins/zpool/scrub.py
+1-1src/middlewared/middlewared/plugins/pool_/scrub.py
+1-1CLAUDE.md
+61-534 files

LLVM/project 92b595bflang/lib/Semantics check-cuda.cpp, flang/test/Semantics cuf25.cuf

[flang][cuda] Take associate into account for host array diagnostic (#190673)
DeltaFile
+22-0flang/test/Semantics/cuf25.cuf
+4-3flang/lib/Semantics/check-cuda.cpp
+26-32 files

FreeBSD/ports d403e15games/freeciv21 distinfo Makefile

games/freeciv21: Update 3.1.0 => 3.1.1

This is a security release:
https://github.com/longturn/freeciv21/security/advisories/GHSA-f76g-6w3f-f6r3

Changelog:
https://github.com/longturn/freeciv21/releases/tag/v3.1.1

PR:             293964
Approved by:    makc (mentor)
DeltaFile
+3-3games/freeciv21/distinfo
+1-1games/freeciv21/Makefile
+4-42 files