FreeNAS/freenas cb5990csrc/middlewared/middlewared/plugins/pool_ sed.py

Properly handle post license update for SED feature

This commit adds changes to make sure that on post license update, we mark disks as SED/non-SED correctly and after that is in place - we appropriately mark pools as all-sed.
DeltaFile
+14-1src/middlewared/middlewared/plugins/pool_/sed.py
+14-11 files

FreeBSD/ports bfdf500x11/walker distinfo Makefile

x11/walker: Update to 2.12.1

Changelog:
- https://github.com/abenz1267/walker/releases/tag/v2.12.0
- https://github.com/abenz1267/walker/releases/tag/v2.12.1

Reported by:    GitHub (watch releases)
DeltaFile
+3-3x11/walker/distinfo
+1-2x11/walker/Makefile
+1-0x11/walker/pkg-plist
+5-53 files

FreeBSD/ports 7098547sysutils/elephant distinfo Makefile

sysutils/elephant: Update to 2.17.1

While here, remove Go version pinning.[1]

Changelog:
- https://github.com/abenz1267/elephant/releases/tag/v2.17.0
- https://github.com/abenz1267/elephant/releases/tag/v2.17.1

Reported by:    GitHub (watch releases),
                adamw (via private email) [1]
DeltaFile
+5-5sysutils/elephant/distinfo
+2-3sysutils/elephant/Makefile
+7-82 files

FreeBSD/ports e471704net Makefile

net/Makefile: Fix unintended change in 7f937bcc8e50bc4a626c72aba2b09a160154db48
DeltaFile
+1-1net/Makefile
+1-11 files

FreeBSD/ports 1195526net/socat distinfo Makefile

net/socat: Update to 1.8.1.0
DeltaFile
+3-3net/socat/distinfo
+1-1net/socat/Makefile
+4-42 files

LLVM/project c3a50a0llvm/include/llvm/MC MCInstPrinter.h, llvm/test/TableGen RegClassByHwModeAlias.td RegClassByHwModeErrors.td

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+48-0llvm/test/TableGen/RegClassByHwModeAlias.td
+33-0llvm/test/TableGen/RegClassByHwModeErrors.td
+19-5llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+12-11llvm/include/llvm/MC/MCInstPrinter.h
+13-9llvm/utils/TableGen/AsmWriterEmitter.cpp
+10-6llvm/utils/TableGen/Common/InfoByHwMode.cpp
+135-315 files not shown
+159-3811 files

LLVM/project 22b3541llvm/include/llvm/MC MCInstPrinter.h, llvm/test/TableGen RegClassByHwModeAlias.td RegClassByHwModeErrors.td

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+48-0llvm/test/TableGen/RegClassByHwModeAlias.td
+33-0llvm/test/TableGen/RegClassByHwModeErrors.td
+19-5llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+12-11llvm/include/llvm/MC/MCInstPrinter.h
+13-9llvm/utils/TableGen/AsmWriterEmitter.cpp
+10-6llvm/utils/TableGen/Common/InfoByHwMode.cpp
+135-312 files not shown
+147-338 files

LLVM/project 86c5539llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/Analysis/CostModel/RISCV vp-intrinsics.ll

[IR][RISCV] Remove @llvm.experimental.vp.splat (#171084)

@llvm.experimental.vp.splat was originally added in #98731 in order to
prevent VL toggles when optimizing a zero strided load to a scalar load
+ splat on RISC-V: #101329

However, the need to explicitly set the VL operand has been superseded
by RISCVVLOptimizer which can infer this automatically based on the
splat's users, and the use of the vp.splat intrinsic was removed in
#170543.

Now that there are no users of @llvm.experimental.vp.splat internal to
LLVM and it's unlikely we will need it in future due to
RISCVVLOptimizer, this patch removes the intrinsic. I couldn't find any
publicly available out-of-tree users of the intrinsic with a quick
search on GitHub.
DeltaFile
+0-744llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
+0-636llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
+0-151llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
+2-131llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+0-107llvm/test/CodeGen/RISCV/rvv/vp-splat-mask.ll
+5-53llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+7-1,82210 files not shown
+14-1,95316 files

NetBSD/src 5cc9E90external/mit/xorg/bin/xkbcomp Makefile

   update for xkbcomp 1.5.0.
VersionDeltaFile
1.13+1-2external/mit/xorg/bin/xkbcomp/Makefile
+1-21 files

NetBSD/xsrc zMh9FKkexternal/mit/xkbcomp/dist utils.h expr.c

   merge xkbcomp 1.5.0.
VersionDeltaFile
1.8+8-16external/mit/xkbcomp/dist/utils.h
1.6+7-3external/mit/xkbcomp/dist/expr.c
1.3+4-2external/mit/xkbcomp/dist/xkbcomp.c
+19-213 files

NetBSD/xsrc rXOCxy6external/mit/xkbcomp/dist aclocal.m4 xkbparse.c

   initial import of xkbcomp-1.5.0
VersionDeltaFile
1.1.1.15+3,252-3,019external/mit/xkbcomp/dist/aclocal.m4
1.1.1.13+841-741external/mit/xkbcomp/dist/xkbparse.c
1.1.1.14+692-245external/mit/xkbcomp/dist/config.sub
1.1.1.16+415-301external/mit/xkbcomp/dist/configure
1.1.1.16+314-0external/mit/xkbcomp/dist/ChangeLog
1.1+240-0external/mit/xkbcomp/dist/meson.build
+5,754-4,30632 files not shown
+6,268-4,65338 files

LLVM/project 6f4fe69llvm/include/llvm/MC MCInstPrinter.h, llvm/lib/MC MCInstPrinter.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+48-0llvm/test/TableGen/RegClassByHwModeAlias.td
+12-11llvm/include/llvm/MC/MCInstPrinter.h
+13-9llvm/utils/TableGen/AsmWriterEmitter.cpp
+8-1llvm/lib/MC/MCInstPrinter.cpp
+81-214 files

LLVM/project 48d5d8fclang/lib/AST/ByteCode Pointer.cpp Interp.h, llvm/test/Transforms/LoopUnroll/RISCV vector.ll

rebase

Created using spr 1.3.8-beta.1
DeltaFile
+157-136llvm/test/Transforms/LowerTypeTests/import.ll
+129-7llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
+67-57clang/lib/AST/ByteCode/Pointer.cpp
+31-31clang/lib/AST/ByteCode/Interp.h
+38-20clang/lib/AST/ByteCode/Descriptor.cpp
+19-20clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+441-27124 files not shown
+605-34630 files

LLVM/project 0893fdbclang/lib/AST/ByteCode Pointer.cpp Interp.h, llvm/test/Transforms/LoopUnroll/RISCV vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+157-136llvm/test/Transforms/LowerTypeTests/import.ll
+129-7llvm/test/Transforms/LoopUnroll/RISCV/vector.ll
+67-57clang/lib/AST/ByteCode/Pointer.cpp
+31-31clang/lib/AST/ByteCode/Interp.h
+38-20clang/lib/AST/ByteCode/Descriptor.cpp
+19-20clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+441-27124 files not shown
+605-34630 files

LLVM/project 5079260llvm/test/TableGen RegClassByHwModeErrors.td RegClassByHwMode.td, llvm/test/TableGen/Common RegClassByHwModeCommon.td

[TableGen] Slightly improve error location for a fatal error

I was hitting this error and the error location was pointing to the
register class definition instead of the incorrect InstAlias. Pass in
the InstAlias location to make it easier to debug.

Happens with `def : InstAlias<"foo", (Inst X0)>`, where `Inst` takes
a RegClassByHwMode operand that is not necessarily satisfied by
register X0. Similar problem with the CompressPat backend.

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/170790
DeltaFile
+88-0llvm/test/TableGen/RegClassByHwModeErrors.td
+7-57llvm/test/TableGen/RegClassByHwMode.td
+44-0llvm/test/TableGen/Common/RegClassByHwModeCommon.td
+12-9llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
+8-6llvm/utils/TableGen/CompressInstEmitter.cpp
+10-2llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+169-743 files not shown
+175-789 files

LLVM/project 9baf76allvm/test/CodeGen/Mips setcc-se.ll micromips-pseudo-mtlohi-expand.ll, llvm/test/CodeGen/Mips/llvm-ir load.ll store.ll

[MCAsmStreamer] Print register names in --show-inst mode

Passing the context to `Inst.dump_pretty()` allows printing symbolic
register names instead of `<MCOperand Reg:1234>` in the output.
I plan to use this in a future RVY test cases where we have register
class with the same name in assembly syntax, but different underlying
register enum values. Printing the name of the enum value makes it
easier to test that we selected the correct register.

Reviewed By: lenary

Pull Request: https://github.com/llvm/llvm-project/pull/171252
DeltaFile
+795-795llvm/test/CodeGen/Mips/llvm-ir/load.ll
+450-450llvm/test/CodeGen/Mips/llvm-ir/store.ll
+157-157llvm/test/CodeGen/Mips/setcc-se.ll
+148-148llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+66-66llvm/test/MC/Lanai/memory.s
+40-40llvm/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll
+1,656-1,6565 files not shown
+1,702-1,70211 files

NetBSD/src uqVvGDcexternal/mit/xorg/server/xorg-server/glamor Makefile.glamor, external/mit/xorg/server/xorg-server/hw/xfree86/glamor_egl Makefile

   update for xorg-server 21.2.21.
VersionDeltaFile
1.3+2-5external/mit/xorg/server/xorg-server/glamor/Makefile.glamor
1.5+2-3external/mit/xorg/server/xorg-server/hw/xfree86/glamor_egl/Makefile
1.164+2-2share/mk/bsd.x11.mk
+6-103 files

FreeBSD/src f9500e7sbin/shutdown shutdown.8

shutdown(8): Document additional formats supported by the code.

MFC after:      1 week
DeltaFile
+47-15sbin/shutdown/shutdown.8
+47-151 files

LLVM/project b1b3629clang/include/clang/Basic Builtins.def, clang/lib/AST ASTContext.cpp

[AMDGPU] Removal of language sensitive option for _Float16 and half( 'e') handling
DeltaFile
+2-6clang/lib/AST/ASTContext.cpp
+0-1clang/include/clang/Basic/Builtins.def
+2-72 files

FreeBSD/ports ae7e911shells/fd Makefile pkg-descr, shells/fd/files patch-_fdrc patch-fd.h

shells/fd: Assign to submitter

While here,
- Update MASTER_SITES, WWW
- Add LICENSE
etc.
DeltaFile
+12-16shells/fd/Makefile
+8-8shells/fd/files/patch-_fdrc
+12-3shells/fd/files/patch-fd.h
+3-3shells/fd/files/patch-machine.h
+1-1shells/fd/pkg-descr
+36-315 files

LLVM/project 773a6a9clang/lib/AST/ByteCode Pointer.cpp Interp.h

Revert "[clang][bytecode] Allocate InitMaps via Program/InterpState allocators (#170272)"

This reverts commit 8fe38c4c9c71c7a86ecdba476ee5bae4c02c0dfe.

This breaks the clang-armv7-2stage build bot:
https://lab.llvm.org/buildbot/#/builders/79/builds/2531
DeltaFile
+67-57clang/lib/AST/ByteCode/Pointer.cpp
+31-31clang/lib/AST/ByteCode/Interp.h
+38-20clang/lib/AST/ByteCode/Descriptor.cpp
+19-20clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+6-26clang/lib/AST/ByteCode/Descriptor.h
+9-11clang/lib/AST/ByteCode/Pointer.h
+170-1656 files not shown
+188-18512 files

LLVM/project 0df8306clang/include/clang/Basic BuiltinsNVPTX.td OffloadArch.h, clang/lib/Basic Cuda.cpp OffloadArch.cpp

[Clang][CUDA] Add support for SM_88, SM_110, and SM_110a architectures (#170258)

This patch adds support for new GPU architectures introduced in CUDA
13.0 in Clang:
- SM_88: Ampere architecture variant
- SM_110/SM_110a: Blackwell architecture variants

Additionally, this patch deprecates SM_101/SM_101a support for CUDA 13.0
and later versions. The SM_101 architecture is superseded by SM_110 and
is no longer supported by CUDA 13.0+ toolchain components.
DeltaFile
+7-3clang/include/clang/Basic/BuiltinsNVPTX.td
+8-0clang/lib/Basic/Cuda.cpp
+6-0clang/lib/Basic/Targets/NVPTX.cpp
+3-0clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+3-0clang/include/clang/Basic/OffloadArch.h
+3-0clang/lib/Basic/OffloadArch.cpp
+30-32 files not shown
+34-38 files

LLVM/project a899a04clang/include/clang/Basic BuiltinsAMDGPU.def

[AMDGPU] Modifies builtin def to take _Float16('x') for both HIP/C++ and for OpenCL
DeltaFile
+17-17clang/include/clang/Basic/BuiltinsAMDGPU.def
+17-171 files

FreeBSD/ports 7f937bcnet Makefile, net/py-icmplib pkg-descr Makefile

net/py-icmplib: Add new port

icmplib provides the capability to easily forge ICMP packets to build
ping- and tracroute-like functionality into python scripts. A full
description can be found at,

        https://pypi.org/project/icmplib/
DeltaFile
+24-0net/py-icmplib/pkg-descr
+19-0net/py-icmplib/Makefile
+3-0net/py-icmplib/distinfo
+2-1net/Makefile
+48-14 files

LLVM/project 93c7ad1llvm/lib/Transforms/IPO LowerTypeTests.cpp, llvm/test/Transforms/LowerTypeTests import.ll

[LTT] Bias branch weights as "expected" when lowering type tests with conditional (#170752)

We expect the type test to succeed.
DeltaFile
+13-10llvm/test/Transforms/LowerTypeTests/import.ll
+5-1llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+0-2llvm/utils/profcheck-xfail.txt
+18-133 files

LLVM/project 4727ca7clang/lib/CodeGen CGExpr.cpp CodeGenFunction.h, clang/test/CodeGen attr-counted-by.c attr-counted-by-for-pointers.c

[Clang][counted_by] Correct signed counted_by values

If the 'counted_by' value is signed, we will incorrectly allow accesses
when the value is negative. This has obvious bad effects as it will
allow accessing a huge swath of unallocated memory.

Also clarify and rearrange the parameters to make them more
perspicuous.

Fixes: 170987
DeltaFile
+309-274clang/test/CodeGen/attr-counted-by.c
+67-57clang/test/CodeGen/attr-counted-by-for-pointers.c
+61-36clang/lib/CodeGen/CGExpr.cpp
+35-36clang/test/DebugInfo/Generic/bounds-checking-debuginfo.c
+9-8clang/lib/CodeGen/CodeGenFunction.h
+481-4115 files

LLVM/project 82a1a33llvm/test/CodeGen/AArch64 arm64-homogeneous-prolog-epilog-tail-call.mir

Remove cleanup of incorrect output in test dir
DeltaFile
+0-1llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir
+0-11 files

LLVM/project ce76c39llvm/test/CodeGen/AArch64 arm64-homogeneous-prolog-epilog-tail-call.mir

Fix test outputting to test dir (#171255)

The test introduced in #171118 has `llc` inadvertently producing an
output into the same dir as the test file itself. Most build bots don't
clean up the local git repo, which is assumed to not be written by build
+ test, and patch on top (for build performance reasons), which means
the produced output from the aforementioned PR is treated as a test from
here onwards, by all bots. Since it's missing `RUN` lines, we get
errors, for example
 https://lab.llvm.org/buildbot/#/builders/108/builds/20674

This patch fixes the `llc` line and also removes the `.s`. This avoids
all bot maintainers go restart their bots. Then, the cleanup is removed
in #171256.
DeltaFile
+2-1llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-tail-call.mir
+2-11 files

LLVM/project ab41b50llvm/test/CodeGen/Mips setcc-se.ll, llvm/test/CodeGen/Mips/llvm-ir load.ll store.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+795-795llvm/test/CodeGen/Mips/llvm-ir/load.ll
+450-450llvm/test/CodeGen/Mips/llvm-ir/store.ll
+157-157llvm/test/CodeGen/Mips/setcc-se.ll
+148-148llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+66-66llvm/test/MC/Lanai/memory.s
+121-0llvm/test/TableGen/RegClassByHwModeErrors.td
+1,737-1,61617 files not shown
+1,943-1,79223 files

LLVM/project 0835d70llvm/test/CodeGen/Mips setcc-se.ll, llvm/test/CodeGen/Mips/llvm-ir load.ll store.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+795-795llvm/test/CodeGen/Mips/llvm-ir/load.ll
+450-450llvm/test/CodeGen/Mips/llvm-ir/store.ll
+157-157llvm/test/CodeGen/Mips/setcc-se.ll
+148-148llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+66-66llvm/test/MC/Lanai/memory.s
+88-0llvm/test/TableGen/RegClassByHwModeErrors.td
+1,704-1,61614 files not shown
+1,877-1,78020 files