FreeBSD/ports f1872dbnews/inn Makefile pkg-plist, news/inn-current pkg-plist Makefile

news/inn{-current}: Modernize the port

Update to modern ports practices while retaining same functionality.

- Option helpers
- GNU_CONFIGURE with overrides for existing filesystem layout
- USES gssapi for krb5, clean up ac_cv_ hacks
- Fix setuid for SETGID_INEWS and UUCP_RNEWS
- Add newer config files as @sample: inn-radius.conf, inn-secrets.conf
- Install all filter scripts as @sample
- Remove ex script and install empty history as @sample
- Use find to run bin/.so strip list instead of manual list
- Clean up inn-current slave port
- portclippy
DeltaFile
+142-180news/inn/Makefile
+18-90news/inn/files/pkg-install.in
+18-16news/inn-current/pkg-plist
+18-16news/inn/pkg-plist
+9-11news/inn-current/Makefile
+205-3135 files

FreeBSD/ports e6ca093news/cleanfeed Makefile pkg-install

news/cleanfeed: Clean up the port

- Use plist to handle ownerships and installation to filter_innd.pl
- Install bad_ files as sample so the admin can edit them
DeltaFile
+17-20news/cleanfeed/Makefile
+0-26news/cleanfeed/pkg-install
+15-10news/cleanfeed/pkg-plist
+32-563 files

LLVM/project 740e3a0llvm/test/CodeGen/AArch64/Atomics aarch64-atomicrmw-lse2.ll aarch64-atomicrmw-rcpc3.ll, llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll

Merge branch 'main' into users/zhaoqi5/test-vpermiw
DeltaFile
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+2,870-0llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll
+1,250-1,305llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+1,250-1,305llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
+1,250-1,305llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
+14,911-8,5333,247 files not shown
+129,959-53,8373,253 files

LLVM/project 0e3c4c4utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[bazel] Update WebAssemblyGenGlobalISel.inc -gisel-extended-llt

Fixup for #193047
DeltaFile
+4-1utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+4-11 files

FreeBSD/ports 58300d1x11/py-nwg-displays Makefile distinfo

x11/py-nwg-displays: Update to 0.4.0

While here, switch to USE_PYTHON=pep517.

Changelog: https://github.com/nwg-piotr/nwg-displays/releases/tag/v0.4.0

Reported by:    GitHub (watch releases)
DeltaFile
+4-2x11/py-nwg-displays/Makefile
+3-3x11/py-nwg-displays/distinfo
+7-52 files

FreeBSD/ports 7026b24x11/hyprlauncher distinfo Makefile, x11/hyprlauncher/files patch-src_config_ConfigManager.cpp patch-src_finders_desktop_DesktopFinder.cpp

x11/hyprlauncher: Update to 0.1.6

While here, remove upstreamed patches.

Changelog: https://github.com/hyprwm/hyprlauncher/releases/tag/v0.1.6

Reported by:    GitHub (watch releases)
DeltaFile
+0-11x11/hyprlauncher/files/patch-src_config_ConfigManager.cpp
+0-10x11/hyprlauncher/files/patch-src_finders_desktop_DesktopFinder.cpp
+3-3x11/hyprlauncher/distinfo
+1-2x11/hyprlauncher/Makefile
+4-264 files

LLVM/project 8e9fc75clang/test/CodeGen/AArch64/sve2p3-intrinsics acle_sve2p3_subp.c, llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll

dynamic version

Created using spr 1.3.8-beta.1
DeltaFile
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+2,870-0llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll
+1,509-924mlir/utils/vscode/package-lock.json
+1,779-131llvm/test/CodeGen/SystemZ/memset-08.ll
+970-0llvm/test/CodeGen/SystemZ/memmove-01.ll
+928-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_subp.c
+13,117-5,2171,757 files not shown
+62,781-22,0421,763 files

LLVM/project 9e4748eclang/test/Analysis/Scalable/EndToEnd/UnsafeBufferFlow connected_units_by_ret.cpp disconnected_units.cpp

[SSAF][UnsafeBufferReachableAnalysis] add end-to-end testing
DeltaFile
+183-0clang/test/Analysis/Scalable/EndToEnd/UnsafeBufferFlow/connected_units_by_ret.cpp
+138-0clang/test/Analysis/Scalable/EndToEnd/UnsafeBufferFlow/disconnected_units.cpp
+117-0clang/test/Analysis/Scalable/EndToEnd/UnsafeBufferFlow/connected_units_by_calls.cpp
+111-0clang/test/Analysis/Scalable/EndToEnd/UnsafeBufferFlow/connected_units_by_global.cpp
+83-0clang/test/Analysis/Scalable/EndToEnd/UnsafeBufferFlow/connected_units_by_class_and_clients.cpp
+632-05 files

LLVM/project 8419579clang/include/clang/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis SourcePassAnalysis.h, clang/include/clang/ScalableStaticAnalysisFramework/Core/WholeProgramAnalysis WPASuite.h

[SSAF] Add UnsafeBufferReachableDebugAnalysis--a source pass analysis

Also added temporary workaround for LUNamespace and Entity linkage info
DeltaFile
+103-1clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageAnalysis.cpp
+26-0clang/lib/ScalableStaticAnalysisFramework/Core/Serialization/JSONFormat/WPASuite.cpp
+5-1clang/test/Analysis/Scalable/help.cpp
+5-0clang/include/clang/ScalableStaticAnalysisFramework/Core/WholeProgramAnalysis/WPASuite.h
+4-1clang/lib/ScalableStaticAnalysisFramework/Core/TUSummary/TUSummaryBuilder.cpp
+2-0clang/include/clang/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis/SourcePassAnalysis.h
+145-318 files not shown
+164-324 files

LLVM/project e555021orc-rt/unittests SimpleNativeMemoryMapSPSCITest.cpp

[orc-rt] Remove explicit addSimpleNativeMemoryMap call. NFCI. (#194766)

The SimpleNativeMemoryMap::Create call two lines below will add this
interface anyway, so the explicit call is redundant.
DeltaFile
+0-1orc-rt/unittests/SimpleNativeMemoryMapSPSCITest.cpp
+0-11 files

LLVM/project 8da581dclang/lib/CodeGen CGException.cpp CGDecl.cpp, clang/test/CodeGenCXX exceptions-seh.cpp

[WinEH] Diagnose SEH object unwinding in skipped __except bodies (#187718)

When an SEH __except block has no EH branches, CodeGen skips emitting the handler
body. This also skipped the existing diagnostic for local variables that require destruction
under C++ exceptions

Diagnose those variables before dropping the skipped handler body, and add coverage
for both sync and async exception modes
DeltaFile
+11-14clang/test/CodeGenCXX/exceptions-seh.cpp
+11-0clang/lib/CodeGen/CGException.cpp
+0-2clang/lib/CodeGen/CGDecl.cpp
+22-163 files

LLVM/project c7e805cclang/include/clang/Frontend FrontendOptions.h, clang/include/clang/Options Options.td

[SSAF] Add CLI option for SourcePassAnalysis
DeltaFile
+78-0clang/lib/ScalableStaticAnalysisFramework/Frontend/SourcePassAnalysisFrontendAction.cpp
+33-0clang/include/clang/ScalableStaticAnalysisFramework/Frontend/SourcePassAnalysisFrontendAction.h
+14-0clang/include/clang/Options/Options.td
+6-0clang/include/clang/Frontend/FrontendOptions.h
+4-0clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
+1-0clang/lib/ScalableStaticAnalysisFramework/Frontend/CMakeLists.txt
+136-06 files

GhostBSD/ghostbsd 3a8717crelease/packages/ucl ghostbsd-cert-all.ucl, stand/defaults loader.conf.5 loader.conf

Merge pull request #385 from ghostbsd/ghostbsd/issues#312

loader: add hidden boot menu option and fix verbose/mute interaction
DeltaFile
+51-8stand/lua/menu.lua
+23-18stand/lua/gfx-glogo.lua
+14-0release/packages/ucl/ghostbsd-cert-all.ucl
+11-0stand/defaults/loader.conf.5
+2-1stand/defaults/loader.conf
+1-1sys/conf/package-version
+102-283 files not shown
+105-309 files

LLVM/project 3ac2a32llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-fp-setcc.ll fixed-vectors-setcc-fp-vp.ll

Merge branch 'fix-blockfreq-unroll-unconditional-latches--fast' into fix-blockfreq-unroll-unconditional-latches--uniform
DeltaFile
+4,811-4,818llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+1,872-1,883llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+565-2,727llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+1,117-1,613llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+11,921-16,1234,339 files not shown
+191,359-100,5894,345 files

NetBSD/src Mwk0qcOsys/arch/amiga/include param.h, sys/arch/atari/include param.h

   No need for N copies of NPTEPG; two is just fine, thanks.
VersionDeltaFile
1.19+1-3sys/arch/news68k/include/param.h
1.15+3-1sys/arch/m68k/include/pmap_68k.h
1.37+1-3sys/arch/atari/include/param.h
1.52+1-3sys/arch/amiga/include/param.h
1.15+1-3sys/arch/next68k/include/param.h
1.55+1-3sys/arch/hp300/include/param.h
+8-168 files not shown
+18-3714 files

LLVM/project 1c55073clang/test/CodeGen/AArch64/sve2p3-intrinsics acle_sve2p3_subp.c, llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll

rebase

Created using spr 1.3.8-beta.1
DeltaFile
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+2,870-0llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll
+1,509-924mlir/utils/vscode/package-lock.json
+1,779-131llvm/test/CodeGen/SystemZ/memset-08.ll
+970-0llvm/test/CodeGen/SystemZ/memmove-01.ll
+928-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_subp.c
+13,117-5,2171,756 files not shown
+62,768-22,0411,762 files

LLVM/project 385f862llvm/utils/TableGen AsmMatcherEmitter.cpp

[TableGen] Fix indentation of generated code. NFC

This line was missing the indent(4) call. Noticed while looking at the
generated code.

Pull Request: https://github.com/llvm/llvm-project/pull/194765
DeltaFile
+2-1llvm/utils/TableGen/AsmMatcherEmitter.cpp
+2-11 files

LLVM/project 81545fallvm/lib/TargetParser TargetDataLayout.cpp, llvm/test/CodeGen/RISCV/rvy datalayout.ll

[RISC-V][RVY] Add a DataLayout component for CHERI capabilities

This adds a new pointer address space to the data layout when RVY is
enabled, making use of the new 'e' flag for pointers with
[external state](https://github.com/llvm/llvm-project/pull/105735).
I chose address space 200 since that is what has been used in the
downstream CHERI forks for the past decade and therefore makes it slightly
easier to upstream tests, etc. but am happy to use any other value if that
is preferred. We can look at the ABI name parameter to detect
pure-capability ABIs, so this does not support the "hybrid" CHERI case that
is supported downstream where capability registers are supported (i.e.
the AS200 pointer attributes exist in the data layout), but the default
address spaces are still integers instead of AS200.
to handle the "hybrid" case where only some pointers use Y registers.

Reviewed By: topperc, lenary

Pull Request: https://github.com/llvm/llvm-project/pull/177249
DeltaFile
+18-7llvm/lib/TargetParser/TargetDataLayout.cpp
+15-0llvm/test/CodeGen/RISCV/rvy/datalayout.ll
+33-72 files

LLVM/project 3aa3966lldb/packages/Python/lldbsuite/test lldbplatformutil.py

[lldb] Add support for two-component tiple (#194764)

Support a two component triple (e.g. wasm32-wasip1) in
lldbplatformutil.py.
DeltaFile
+9-2lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
+9-21 files

LLVM/project f1c76f8clang/test/Analysis/Scalable/ssaf-analyzer/Inputs lu-noext lu.json, clang/test/Analysis/Scalable/ssaf-analyzer/Outputs all.json both.json

Pull in the draft PR "[clang][ssaf] Add clang-ssaf-analyzer #188881"
DeltaFile
+131-0clang/tools/clang-ssaf-analyzer/SSAFAnalyzer.cpp
+126-0clang/test/Analysis/Scalable/ssaf-analyzer/Inputs/lu-noext
+126-0clang/test/Analysis/Scalable/ssaf-analyzer/Inputs/lu.json
+126-0clang/test/Analysis/Scalable/ssaf-analyzer/Inputs/lu-badext.txt
+90-0clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/all.json
+81-0clang/test/Analysis/Scalable/ssaf-analyzer/Outputs/both.json
+680-011 files not shown
+1,011-017 files

LLVM/project a1fc904lldb/packages/Python/lldbsuite/test lldbtest.py

[lldb] Pass `settings set` as a raw command (#194762)

To prevent settings start with a dash to be interpreter as a command
option, always pass them as raw values. An example of this is passing
`platform.plugin.wasm.runtime-args` with the dotest.py `--settings`
flag.
DeltaFile
+1-1lldb/packages/Python/lldbsuite/test/lldbtest.py
+1-11 files

LLVM/project 06878abflang/lib/Optimizer/CodeGen CodeGen.cpp, flang/test/Fir dso-local.fir

[flang] Do not mark CUDA device variables as dso_local (#194500)

A follow-up to https://github.com/llvm/llvm-project/pull/189709.

```fortran
integer, constant :: zzz = 4
bind(c, name='zzz_from_c') :: zzz
```

In this code, `zzz` is a CUDA `constant` variable with an initializer.
With PIE enabled, flang marks it as `dso_local`, causing LLVM to emit
direct addressing (`leaq`) instead of GOT-indirect addressing (`movq
@GOTPCREL`). The CUDA runtime interposes on these symbols via
`cudaRegisterVar`, so the wrong address gets registered, leading to a
segfault.

Fix: skip `dso_local` for globals with a CUDA data attribute.
DeltaFile
+32-0flang/test/Fir/dso-local.fir
+7-1flang/lib/Optimizer/CodeGen/CodeGen.cpp
+39-12 files

LLVM/project 6fcda8eclang/include/clang/ScalableStaticAnalysisFramework SSAFBuiltinForceLinker.h, clang/include/clang/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis SourcePassAnalysisRegistry.h SourcePassAnalysis.h

[SSAF] Add SourcePassAnalysis framework

SourcePassAnalysis is for analyses/actions to be performed in a second
pass on source code, after the SSAF whole-program analysis.

SourcePassAnalysis is defined as an ASTConsumer abstraction that
depends on a whole-program analysis result.

This commit adds:
- SourcePassAnalysis base classes
- SourcePassAnalysis registry
- unit test for registry

rdar://175802731
DeltaFile
+105-0clang/include/clang/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis/SourcePassAnalysisRegistry.h
+82-0clang/unittests/ScalableStaticAnalysisFramework/Registries/SourcePassAnalysisRegistryTest.cpp
+63-0clang/include/clang/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis/SourcePassAnalysis.h
+46-0clang/lib/ScalableStaticAnalysisFramework/Core/SourcePassAnalysis/SourcePassAnalysisRegistry.cpp
+6-0clang/include/clang/ScalableStaticAnalysisFramework/SSAFBuiltinForceLinker.h
+1-0clang/lib/ScalableStaticAnalysisFramework/Core/CMakeLists.txt
+303-01 files not shown
+304-07 files

LLVM/project 10e0472clang/include/clang/ScalableStaticAnalysisFramework/Analyses/PointerFlow PointerFlowAnalysis.h, clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageAnalysis.h

[NFC][SSAF] Rename PointerFlowReachableAnalysis to UnsafeBufferReachableAnalysis

The previous-named PointerFlowReachableAnalysis is essentially
propagating unsafe buffers on a pointer flow graph.  The pointer flow
analysis is a dependency, instead of the subject.  So do the rename
and move.
DeltaFile
+434-0clang/unittests/ScalableStaticAnalysisFramework/WholeProgramAnalysis/PointerFlowReachableAnalysisTest.cpp
+0-114clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowAnalysis.cpp
+111-0clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageAnalysis.cpp
+19-2clang/include/clang/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageAnalysis.h
+0-13clang/include/clang/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowAnalysis.h
+564-1295 files

LLVM/project 1b4563ellvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll, llvm/test/CodeGen/RISCV/rvv fixed-vectors-fp-setcc.ll fixed-vectors-setcc-fp-vp.ll

Merge remote-tracking branch 'origin/main' into HEAD
DeltaFile
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+326-4,626llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+3,230-456llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
+565-2,727llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+2,870-0llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll
+1,117-1,613llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+13,169-13,5844,465 files not shown
+183,119-94,8944,471 files

LLVM/project 630bff8llvm/include/llvm/Bitcode LLVMBitCodes.h, llvm/include/llvm/Support AMDGPUSummary.h

[RFC][AMDGPU] Add AMDGPU_SUMMARY bitcode block for ThinLTO

With AMDGPU object linking, device functions are compiled separately from the
kernels that call them. Without whole-program visibility, the compiler must be
conservative about occupancy for every device function, leading to suboptimal
resource usage. However, GPU kernels typically carry explicit occupancy control
attributes that constrain the launch environment. ThinLTO is the natural place
to propagate these kernel attributes to callees: the combined module summary
index contains a cross-TU call graph, allowing occupancy information to be
propagated top-down from kernels to all reachable device functions. The backend
can then generate better code with the propagated constraints, achieving
whole-program awareness without the compile-time overhead of full LTO.

This patch introduces a dedicated AMDGPU_SUMMARY bitcode block that serializes
per-function summary data alongside the standard module summary. The block is
scoped to AMDGPU so that non-AMDGPU targets are completely unaffected. A
follow-up patch will add the ThinLTO propagation logic that reads these
summaries and applies conservative attribute bounds to device functions
reachable from multiple kernels.
DeltaFile
+87-1llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+83-1llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+47-0llvm/test/ThinLTO/AMDGPU/amdgpu-summary-roundtrip.ll
+46-0llvm/include/llvm/Support/AMDGPUSummary.h
+11-0llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
+10-0llvm/include/llvm/Bitcode/LLVMBitCodes.h
+284-21 files not shown
+289-27 files

LLVM/project 03aad37llvm/docs AMDGPUUsage.rst, llvm/docs/AMDGPU DeveloperGuideline.rst

[NFC][AMDGPU][Doc] Add developer guideline

This guideline covers topics on top of existing LLVM guideline.
DeltaFile
+356-0llvm/docs/AMDGPU/DeveloperGuideline.rst
+1-0llvm/docs/AMDGPUUsage.rst
+357-02 files

LLVM/project 383733eclang/lib/CIR/CodeGen CIRGenRecordLayoutBuilder.cpp, clang/test/CIR/CodeGen no-unique-address.cpp

[CIR] Always set base subobject type for C++ records (#194504)

For unions and final C++ classes, computeRecordLayout previously left
the base-subobject type as a default-constructed (null) cir::RecordType.
The non-virtual size always equals the size for those kinds of records,
so no separate ".base" variant is needed, but `BaseSubobjectType` itself
was never set to the complete type either.

That null leaked through
getCIRGenRecordLayout(RD).getBaseSubobjectCIRType(), which is called by
getStorageType(const CXXRecordDecl *) when laying out a
[[no_unique_address]] / potentially-overlapping field. The null
mlir::Type was then stored as MemberInfo::data and tripped a
SmallVector::back() !empty() assertion in
CIRRecordLowering::fillOutputFields, because a member with null data is
interpreted as a bitfield placeholder and reads fieldTypes.back() that
was never pushed.

Match classic CodeGen (CGRecordLayoutBuilder.cpp) and unconditionally

    [15 lines not shown]
DeltaFile
+56-0clang/test/CIR/CodeGen/no-unique-address.cpp
+13-5clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
+69-52 files

LLVM/project eac20c0llvm/utils/gn/secondary/llvm/lib/ProfileData BUILD.gn

[gn build] Port c26ae41c8765



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194759
DeltaFile
+0-1llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn
+0-11 files

LLVM/project bec51b8clang/test/CodeGen/AArch64/sve2p3-intrinsics acle_sve2p3_subp.c, llvm/test/CodeGen/AMDGPU regalloc-hoist-spill-live-range-upd.ll

rebase

Created using spr 1.3.8-beta.1
DeltaFile
+5,061-4,162llvm/test/CodeGen/Thumb2/mve-clmul.ll
+2,870-0llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.ll
+1,509-924mlir/utils/vscode/package-lock.json
+1,779-131llvm/test/CodeGen/SystemZ/memset-08.ll
+970-0llvm/test/CodeGen/SystemZ/memmove-01.ll
+928-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_subp.c
+13,117-5,2171,718 files not shown
+61,711-21,2881,724 files