LLVM/project 5603cd1llvm/lib/Target/AMDGPU SIDefines.h

[NFCI][AMDGPU] Update Mode register mask for gfx1250

SPG says two bits for each operand.
DeltaFile
+5-5llvm/lib/Target/AMDGPU/SIDefines.h
+5-51 files

LLVM/project 47a0d0ellvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/AMDGPU div_v2i128.ll fptoi.i128.ll

SelectionDAG: Do not propagate divergence through glue (#174766)

Glue does not carry any value (in the LLVM IR Value sense) that could be
considered uniform or divergent.
DeltaFile
+336-328llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+262-256llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+204-200llvm/test/CodeGen/AMDGPU/rem_i128.ll
+167-163llvm/test/CodeGen/AMDGPU/div_i128.ll
+5-22llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+4-3llvm/test/CodeGen/AMDGPU/dag-divergence.ll
+978-9726 files

FreeBSD/src 98b9f1dshare/man/man4 mrsas.4

mrsas.4: Cleaning

+ Rewrite SYNOPSIS for consistency
+ Rewrite HARDWARE for HW Relnotes, and add some stragglers
+ Correct mdoc grammar, making sysctls aproposable and linking xrefs
+ Clean up TODO, cannonicalize to CAVEATS, a standard section
+ Editorial pass, tag SPDX

MFC after:              3 days
Reviewed by:            imp
Differential Revision:  https://reviews.freebsd.org/D52125

(cherry picked from commit 52eb7e394a7e28e9b08e2096c4a085a384cc1dd0)
DeltaFile
+91-108share/man/man4/mrsas.4
+91-1081 files

FreeBSD/ports e931c70benchmarks/netperfmeter Makefile

benchmarks/netperfmeter: Fix build on aarch64

"Too many args to microtask: 17!"

While here:
- Replace desktop-file-utils with shared-mime-info - port doesn't
  install *.desktop files, but it does install
  share/mime/packages/netperfmeter.xml.
- Fix warning from portclippy: swap the CMAKE_ON and CMAKE_OFF.

PR:     292237
DeltaFile
+6-2benchmarks/netperfmeter/Makefile
+6-21 files

LLVM/project 1719aa4llvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp

resolve review comments
DeltaFile
+10-7llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+10-71 files

FreeBSD/src ac8b22bshare/man/man4 mrsas.4

mrsas.4: Cleaning

+ Rewrite SYNOPSIS for consistency
+ Rewrite HARDWARE for HW Relnotes, and add some stragglers
+ Correct mdoc grammar, making sysctls aproposable and linking xrefs
+ Clean up TODO, cannonicalize to CAVEATS, a standard section
+ Editorial pass, tag SPDX

MFC after:              3 days
Reviewed by:            imp
Differential Revision:  https://reviews.freebsd.org/D52125

(cherry picked from commit 52eb7e394a7e28e9b08e2096c4a085a384cc1dd0)
DeltaFile
+91-108share/man/man4/mrsas.4
+91-1081 files

LLVM/project 82c1f94mlir/include/mlir/Transforms Passes.td Passes.h, mlir/lib/Transforms RemoveDeadValues.cpp

[mlir][Transforms] `remove-dead-values`: Rely on canonicalizer for region simplification (#173505)

This commit simplifies the `remove-dead-values` pass and fixes a bug in
the handling of `RegionBranchOpInterface` ops. The pass used to produce
invalid IR ("null value found") for the newly added test case.

`remove-dead-values` is a pass for additional IR simplification that
cannot be performed by the canonicalizer pass. Based on a liveness
analysis, it erases dead values / IR. (The liveness analysis is a
dataflow analysis that has more information about the IR than a
canonicalization pattern, which can see only "local" information.)

Region-based ops are difficult. The liveness analysis may determine that
an SSA value is dead. However, that does not mean that the value can
actually be removed. Doing so may violate an region data flow (as
modeled by the `RegionBranchOpInterface`). As an example, consider the
case where a region branch terminator may dispatch to one of two region
successor with the same forwarded values. A successor input (block
argument) can be erased only if it is dead on both successors.

    [11 lines not shown]
DeltaFile
+143-304mlir/lib/Transforms/RemoveDeadValues.cpp
+110-45mlir/test/Transforms/remove-dead-values.mlir
+10-0mlir/include/mlir/Transforms/Passes.td
+1-0mlir/include/mlir/Transforms/Passes.h
+264-3494 files

FreeBSD/src ee1daaetests/sys/netinet6 ra.py

tests: Fix style in ra.py

No functional change intended.

MFC after:      2 weeks

(cherry picked from commit 7080c1b09d72e64f17185e90d7b660175f8fbaba)
DeltaFile
+12-10tests/sys/netinet6/ra.py
+12-101 files

FreeBSD/src 65cf47bsbin/ifconfig af_inet6.c, tests/sys/netinet6 ndp.sh ra.py

ifconfig: Fix the -L flag when using netlink

By default, when ifconfig shows a v6 address derived from a
router-advertised prefix, it shows the initial preferred and valid
lifetimes.  When -L is specified, it is supposed to show the remaining
lifetimes, but this was broken in the conversion to netlink.

Fix that, and add a regression test which validates ifconfig output
before and after a short-lived address expires.

Reported by:    Franco Fichtner <franco at opnsense.org>
Reviewed by:    melifaro, allanjude, Seyed Pouria Mousavizadeh Tehrani
Fixes:          4c91a5dfe483 ("ifconfig: make interface and address listing use Netlink as transport")
MFC after:      2 weeks
Sponsored by:   OPNsense
Sponsored by:   Klara, Inc.
Differential Revision:  https://reviews.freebsd.org/D54294

(cherry picked from commit df6861d755c8f72380ae7fb8df535b27eba8c0be)
DeltaFile
+62-0tests/sys/netinet6/ndp.sh
+10-1tests/sys/netinet6/ra.py
+4-2sbin/ifconfig/af_inet6.c
+76-33 files

FreeBSD/src 5738812sys/dev/random armv8rng.c

armv8rng: Fix an inverted test in random_rndr_read_one()

If we get a random number, the NZCV is set to 0b0000.  Then
"cset %w1, ne" will test whether Z == 0 and set %w1 to 1 if so.
More specifically, "cset %w1, ne" maps to "csinc %w1, wzr, wzr, eq",
which stores 0 in %w1 when NZCV == 0b0100 and 1 otherwise.

Thus, on a successful read we expect ret != 0, so the loop condition
needs to be fixed.  In practice this means that we would end up trying
to fetch entropy up to ten times in a row.  If all attempts are
successful, the last will be returned, otherwise no entropy will be
returned.

Reported by:    Kevin Day <kevin at your.org>
Reviewed by:    andrew
Fixes:          9eecef052155 ("Add an Armv8 rndr random number provider")
MFC after:      1 week
Differential Revision:  https://reviews.freebsd.org/D54259

(cherry picked from commit 93811883500b99f9f1fb4ffd6e764226d37dcfd0)
DeltaFile
+1-1sys/dev/random/armv8rng.c
+1-11 files

FreeBSD/src b87f70fsys/net pfvar.h, sys/netpfil/pf pf_ioctl.c if_pfsync.c

pfsync: Avoid zeroing the state export union

pfsync_state_export() takes a pointer to a union that is in reality a
pointer to one of the three state formats (1301, 1400, 1500), and zeros
the union.  The three formats do not have the same size, so zeroing is
wrong when the format isn't that which has the largest size.

Refactor a bit so that the zeroing happens at the layer where we know
which format we're dealing with.

Reported by:    CHERI
Reviewed by:    kp
MFC after:      1 week
Sponsored by:   CHERI Research Centre (EPSRC grant UKRI3001)
Differential Revision:  https://reviews.freebsd.org/D54163

(cherry picked from commit 796abca7e281f0d4b7f72f48da4f941e1c8b139c)
DeltaFile
+19-7sys/netpfil/pf/pf_ioctl.c
+6-4sys/netpfil/pf/if_pfsync.c
+4-2sys/net/pfvar.h
+29-133 files

FreeBSD/src 284f29fsys/dev/netmap netmap_mem2.c

netmap: Let memory allocator parameters be settable via loader.conf

This is useful when dev.netmap.port_numa_affinity is set to 1.  When
interfaces attach, they get a memory allocator that is copied from
nm_mem.  Parameters in nm_mem can be set using sysctls, but this happens
after their values are copied.

To work around this, we can make it possible to set these memory
parameters as tunables.

Reviewed by:    vmaffione
MFC after:      1 week
Sponsored by:   Klara, Inc.
Differential Revision:  https://reviews.freebsd.org/D54178

(cherry picked from commit c694122f3cfb7d52b882fa79086d49f45a2c7fd2)
DeltaFile
+19-15sys/dev/netmap/netmap_mem2.c
+19-151 files

FreeBSD/src e08642csys/kern uipc_socket.c

socket: Fix the name of a parameter in a comment

Reported by:    des
Fixes:          0a68f644dca1 ("socket: Split up soreceive_generic()")
MFC after:      1 week

(cherry picked from commit a0d607957533c7fbefaac5cd81d34c037cc27344)
DeltaFile
+1-1sys/kern/uipc_socket.c
+1-11 files

LLVM/project 4fdbe05clang/lib/AST/ByteCode Compiler.cpp, clang/test/AST/ByteCode complex.cpp

[clang][bytecode] Fix some imag/real corner cases (#174764)

Fix real/imag when taking a primitive parameter _and_ being discarded,
and fix the case where their subexpression can't be classified.

Fixes https://github.com/llvm/llvm-project/issues/174668
DeltaFile
+26-0clang/test/AST/ByteCode/complex.cpp
+7-3clang/lib/AST/ByteCode/Compiler.cpp
+33-32 files

LLVM/project 412e86allvm/test/CodeGen/AMDGPU carryout-selection.ll llvm.amdgcn.wmma.gfx1250.w32.ll

[AMDGPU] Handle `s_setreg_imm32_b32` targeting `MODE` register

On certain hardware, this instruction clobbers VGPR MSB `bits[12:19]`, so we need to restore the current mode.
DeltaFile
+713-2llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+246-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+220-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+212-0llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+174-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+166-0llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+1,731-2146 files not shown
+6,212-3152 files

FreeBSD/ports ab2efa0sysutils/treemd distinfo Makefile.crates

sysutils/treemd: Update to 0.5.5

ChangeLog:      https://github.com/Epistates/treemd/releases/tag/v0.5.5
Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+349-81sysutils/treemd/distinfo
+174-40sysutils/treemd/Makefile.crates
+1-1sysutils/treemd/Makefile
+524-1223 files

FreeNAS/freenas 097e252src/middlewared/middlewared/plugins/failover_ remote.py, src/middlewared/middlewared/plugins/zfs mount_events.py events_read.py

NAS-139201 / 26.04 / fix start_daemon_thread callers (#17970)

These were missed in the last PR
https://github.com/truenas/middleware/pull/17968
DeltaFile
+1-1src/middlewared/middlewared/plugins/zfs_/zfs_events.py
+1-1src/middlewared/middlewared/plugins/zfs/mount_events.py
+1-1src/middlewared/middlewared/plugins/zfs/events_read.py
+1-1src/middlewared/middlewared/plugins/failover_/remote.py
+4-44 files

LLVM/project d206fb1mlir/include/mlir/Transforms Passes.td Passes.h, mlir/lib/Transforms RemoveDeadValues.cpp

tmp commit

simple test working

draft: do not erase IR, just replace uses
DeltaFile
+143-304mlir/lib/Transforms/RemoveDeadValues.cpp
+110-45mlir/test/Transforms/remove-dead-values.mlir
+10-0mlir/include/mlir/Transforms/Passes.td
+1-0mlir/include/mlir/Transforms/Passes.h
+264-3494 files

FreeBSD/ports 9cca368net-im/py-zapzap distinfo Makefile

net-im/py-zapzap: Update to 6.2.5

ChangeLog:      https://github.com/rafatosta/zapzap/releases/tag/6.2.5
Reported by:    Rafael Tosta <notifications at github.com>
DeltaFile
+3-3net-im/py-zapzap/distinfo
+1-5net-im/py-zapzap/Makefile
+4-82 files

LLVM/project 1ab7b66llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/CodeGen/AMDGPU combine-scalar-selects.ll combine-scalar-selects-asm.ll

Revert "[VectorCombine] Fold scalar selects from bitcast into vector select" (#174758)

Reverts llvm/llvm-project#173990
Reverting to address post-commit review feedback. Will recommit with
fixes.
DeltaFile
+0-1,874llvm/test/CodeGen/AMDGPU/combine-scalar-selects.ll
+0-1,372llvm/test/CodeGen/AMDGPU/combine-scalar-selects-asm.ll
+0-118llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+0-3,3643 files

LLVM/project 448933dllvm/lib/Target/SPIRV SPIRVRegularizer.cpp, llvm/test/CodeGen/SPIRV icmp-i1.ll

[SPIRV] Lower i1 comparisons to logical operations in regularizer pass.

UGT, UGE, ULT, ULE, SGT, SGE, SLT, SLE predicates for i1 types are now
lowered to equivalent logical operations (AND, OR, NOT) to ensure
valid SPIR-V, since SPIR-V boolean types only support logical operations.
DeltaFile
+132-0llvm/test/CodeGen/SPIRV/icmp-i1.ll
+73-0llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
+205-02 files

LLVM/project 807cc99llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

Update llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Co-authored-by: Jay Foad <jay.foad at amd.com>
DeltaFile
+2-5llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+2-51 files

OPNSense/core 6e6369asrc/opnsense/mvc/app/controllers/OPNsense/Interfaces/forms dialogSettings.xml, src/opnsense/mvc/app/models/OPNsense/Interfaces/FieldTypes DUIDField.php

interfaces: settings: convert to MVC (#9569)

DeltaFile
+0-441src/www/system_advanced_network.php
+93-0src/opnsense/scripts/interfaces/gen_duid.php
+92-0src/opnsense/mvc/app/models/OPNsense/Interfaces/FieldTypes/DUIDField.php
+87-0src/opnsense/mvc/app/models/OPNsense/Interfaces/Migrations/M1_0_0.php
+74-0src/opnsense/mvc/app/controllers/OPNsense/Interfaces/forms/dialogSettings.xml
+73-0src/opnsense/mvc/app/views/OPNsense/Interface/settings.volt
+419-44124 files not shown
+792-50930 files

FreeNAS/freenas 23a8547src/middlewared/middlewared/plugins zettarepl.py, src/middlewared/middlewared/plugins/device_ netlink_events.py udev_events.py

NAS-139200 / 26.04 / Force name keyword arg in start_daemon_thread (#17968)

While tracing middlewared process, I found a bunch of threads attached
to parent process with just names like `Thread-0`, `Thread-1`, etc. This
is the default thread_name_prefix given to a `Thread` in python. That's
unhelpful so this forces a `name` keyword argument to be given to
`start_daemon_thread`.
DeltaFile
+16-2src/middlewared/middlewared/utils/threading.py
+6-4src/middlewared/middlewared/plugins/zettarepl.py
+1-1src/middlewared/middlewared/plugins/device_/netlink_events.py
+1-1src/middlewared/middlewared/plugins/device_/udev_events.py
+1-1src/middlewared/middlewared/plugins/failover_/datastore.py
+25-95 files

FreeNAS/freenas cefa1b2

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas 33d77e3src/middlewared/middlewared main.py, src/middlewared/middlewared/api/base/server/ws_handler rpc.py

NAS-139199 / 26.04 / Fix Futures resource leak in run_coroutine_threadsafe (#17967)

This fixes a leak whereby we're not tracking `Future` objects correctly.
This means they're never cleaned up and overtime they'll build up on the
main event loop.

I confirmed this behavior by running `midclt call interface.query` in a
tight loop on a box and then connecting a remote pdb session with the
middleware process. It was designed to "overrun" the main event loop,
what it did was build up a queue that never cleared itself. There were
~2.3k PENDING futures in our thread pool.

This does 2 things:
1. creates a `run_coroutine_threadsafe` wrapper that properly tracks the
futures so they're cleaned up
2. logs any exceptions that may occur in these "fire and forget"
futures.
DeltaFile
+35-0src/middlewared/middlewared/utils/threading.py
+3-2src/middlewared/middlewared/apps/webshell_app.py
+3-2src/middlewared/middlewared/apps/websocket_app.py
+2-1src/middlewared/middlewared/main.py
+2-1src/middlewared/middlewared/plugins/failover_/reboot.py
+2-1src/middlewared/middlewared/api/base/server/ws_handler/rpc.py
+47-76 files

LLVM/project faa7edellvm/tools/llvm-stress llvm-stress.cpp

[llvm-stress] Allow implicit truncation

This is generating a random integer, so truncating is fine.

Fixes the issue reported in:
https://github.com/llvm/llvm-project/pull/171456#issuecomment-3718690088
DeltaFile
+2-1llvm/tools/llvm-stress/llvm-stress.cpp
+2-11 files

LLVM/project 9363750.github/workflows release-binaries.yml release-binaries-all.yml

worklows/release-binaries: Add Windows release binary builds (#150793)

Windows x86 binaries will now be built and uploaded automatically when a new release is tagged.
DeltaFile
+71-6.github/workflows/release-binaries.yml
+1-0.github/workflows/release-binaries-all.yml
+72-62 files

OPNSense/core f9fa4b8src/opnsense/mvc/app/controllers/OPNsense/Radvd/Api ServiceController.php, src/opnsense/mvc/app/models/OPNsense/Radvd Radvd.xml

Fix comment style for points that need work still
DeltaFile
+2-2src/opnsense/mvc/app/views/OPNsense/Radvd/settings.volt
+1-1src/opnsense/mvc/app/controllers/OPNsense/Radvd/Api/ServiceController.php
+1-1src/opnsense/mvc/app/models/OPNsense/Radvd/ACL/ACL.xml
+1-1src/opnsense/mvc/app/models/OPNsense/Radvd/Menu/Menu.xml
+1-1src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.xml
+6-65 files

LLVM/project 542d2a5clang/include/clang/Basic arm_sve.td, clang/test/CodeGen/AArch64/sve2p2-intrinsics acle_sve2_cvtnt.c

[Clang][LLVM][AArch64] Add support for FCVTXNT, FCVTLT, {B}FCVTNT int… (#170356)

…rinsics

This patch adds support in Clang for these assembly instructions
FCVTXNT, FCVTLT, {B}FCVTNT
By implementing these prototypes:

// Variant is available for _f64_f32
svfloat32_t     svcvtlt_f32[_f16]_z     (svbool_t pg, svfloat16_t op);

// Variants are available for:
// _f32_f64, _bf16_f32
svfloat16_t svcvtnt_f16[_f32]_z (svfloat16_t even, svbool_t pg,
svfloat32_t op);

svfloat32_t svcvtxnt_f32[_f64]_z (svfloat32_t even, svbool_t pg,
svfloat64_t op);


    [6 lines not shown]
DeltaFile
+138-0clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2_cvtnt.c
+53-0llvm/test/CodeGen/AArch64/sve2p2-intrinsics-fp-converts.ll
+48-0clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p2_OR_sme2p2_RP___sme_AND_LP_sve2p2_OR_sme2p2_RP.c
+12-4llvm/lib/Target/AArch64/SVEInstrFormats.td
+12-0clang/include/clang/Basic/arm_sve.td
+6-2llvm/include/llvm/IR/IntrinsicsAArch64.td
+269-61 files not shown
+273-107 files