FreeBSD/doc f01d6d9documentation/content/en/books/handbook introduction.adoc

books/handbook: version bump for 15.0
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+1-1documentation/content/en/books/handbook/introduction.adoc
+1-11 files

LLVM/project 79fd11cclang/lib/Headers avx512vlbwintrin.h

[Headers][X86] __builtin_ia32_pmovwb128_mask is not constexpr (#174985)

Appears to be a copy+paste type - most of the x86 masked truncation intrinsics still can't be made constexpr at this time

Fixes #166814
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+2-2clang/lib/Headers/avx512vlbwintrin.h
+2-21 files

LLVM/project 9973e38llvm/include/llvm/CodeGen SDPatternMatch.h, llvm/unittests/CodeGen SelectionDAGPatternMatchTest.cpp

[SDPatternMatch] Add m_FAbs matcher (#174975)

Adds a pattern matcher for floating-point absolute value (ISD::FABS),
following the same pattern as m_Abs for integer absolute value.

Fixes #174751
DeltaFile
+6-0llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+4-0llvm/include/llvm/CodeGen/SDPatternMatch.h
+10-02 files

LLVM/project 012097dcompiler-rt/lib/builtins/aarch64 sme-abi.S

[compiler-rt][AArch64] Exit early from __arm_za_disable. (#174942)

Because `__arm_za_disable` is a private-ZA function, it's only ever
entered with ZA state `off` or `dormant`. If the state is `off` then we
can safely return and there is no need to call `__arm_tpidr2_save` or to
explicitly set PSTATE.ZA or TPIDR2_EL0 to zero.
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+7-0compiler-rt/lib/builtins/aarch64/sme-abi.S
+7-01 files

LLVM/project 21dc73flibcxx/include any

[libc++][NFC] Update <any> to a more modern code style (#174619)

This patch refactors `enable_if`s inside `<any>` to use the `..., int> =
0` variant that we try to use throughout the code base and inlines some
of the functions into the class body to avoid duplicating the
`enable_if`s.
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+44-62libcxx/include/any
+44-621 files

FreeBSD/src 16f8ea6sys/amd64/conf MINIMAL GENERIC

amd64: Remove tpm(4) from GENERIC for now

It breaks suspend/resume and no one has had time to investigate and fix
it.

PR:             291067
Reviewed by:    emaste
Fixes:          3deb21f1afd5 ("random: TPM_HARVEST should have been named RANDOM_ENABLE_TPM")
Differential Revision:  https://reviews.freebsd.org/D54587
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+2-1sys/amd64/conf/MINIMAL
+2-1sys/amd64/conf/GENERIC
+4-22 files

FreeBSD/ports d0f5025textproc/py-mdformat Makefile distinfo, textproc/py-mdformat/files patch-pyproject.toml patch-src_mdformat___conf.py

textproc/py-mdformat: Update to 1.0.0

- Remove files/patch-pyproject.toml
- Fix pyproject.toml (via a post-patch target), because the build
  framework does not recognise its new format.
  (see https://packaging.python.org/en/latest/guides/writing-pyproject-toml/#license-and-license-files )
- Pet port(clippy|fmt)

ChangeLog:      https://mdformat.readthedocs.io/en/stable/users/changelog.html#id1
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+12-10textproc/py-mdformat/Makefile
+0-13textproc/py-mdformat/files/patch-pyproject.toml
+5-4textproc/py-mdformat/files/patch-src_mdformat___conf.py
+3-3textproc/py-mdformat/distinfo
+20-304 files

LLVM/project a4f1798clang/lib/Parse ParseDeclCXX.cpp, clang/test/Parser cxx2c-trivially-relocatable.cpp

[Clang] expunge `trivially_relocate_if_eligible` (#174344)

In Kona, WG21 decided to revert trivial relocation (P2786).

Keep the notion of relocatability
(used in the wild and likely to come back),
but remove the keyword which is no longer conforming
DeltaFile
+0-148clang/test/SemaCXX/ptrauth-type-traits.cpp
+0-123clang/test/SemaCXX/cxx2c-trivially-relocatable.cpp
+5-46clang/lib/Parse/ParseDeclCXX.cpp
+0-43clang/test/SemaCXX/trivially-relocatable-ptrauth.cpp
+0-31clang/test/Parser/cxx2c-trivially-relocatable.cpp
+0-24clang/test/SemaCXX/ptrauth-triviality.cpp
+5-41510 files not shown
+13-47916 files

LLVM/project 5c324b5llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-use-after-erase.ll

use `Value *` instead of useless `WeakVH`
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+2-0llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
+3-12 files

OPNSense/core 1b11fca. plist, src/opnsense/mvc/app/models/OPNsense/Radvd Radvd.xml

Add VipLinkLocalField for the source_address validation
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+111-0src/opnsense/mvc/app/models/OPNsense/Radvd/FieldTypes/VipLinkLocalField.php
+2-2src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.xml
+1-0plist
+114-23 files

FreeNAS/freenas cb894e2src/middlewared/middlewared/plugins account.py

Fix
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+1-1src/middlewared/middlewared/plugins/account.py
+1-11 files

FreeNAS/freenas 2cef43bsrc/middlewared/middlewared/alembic/versions/26.04 2025-12-31_15-39_split_smb_path.py, src/middlewared/middlewared/plugins smb.py

split SMB path field
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+72-0src/middlewared/middlewared/alembic/versions/26.04/2025-12-31_15-39_split_smb_path.py
+28-1src/middlewared/middlewared/service/sharing_service.py
+18-8src/middlewared/middlewared/plugins/smb.py
+118-93 files

LLVM/project cc1bb84mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[mlir][OpenMP] Fix sanitizer error in buildTaskLikeBodyGenCallback  (#174983)

This is a fix for the asan bot after
https://github.com/llvm/llvm-project/pull/174386

Failing bot: https://lab.llvm.org/buildbot/#/builders/24/builds/16371

This commit undoes a simplification I thought reduced copied+pasted
code. I will merge it like this now to unblock the bot, and then work
separately on a different way to share code between both callbacks.
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+172-101mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+172-1011 files

LLVM/project 1677b3ellvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-use-after-erase.ll

fix comments
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+5-5llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+2-2llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
+7-72 files

LLVM/project 5b1a032llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-use-after-erase.ll

[AMDGPU] Fix a potential use-after-erase in `AMDGPUPromoteAlloca` pass

In some cases, the placeholder itself can be used as the value for its corresponding block in `SSAUpdater`, and later used as an incoming value in another block in `GetValueInMiddleOfBlock`. If we erase it too early, this can lead to a use-after-erase. The tricky part is that it may not trigger any error right away, but can cause weird and completely unrelated issues later in the pipeline.
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+34-0llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
+11-2llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+45-22 files

LLVM/project db26ce5llvm/test/CodeGen/PowerPC vector-lrint.ll vector-llrint.ll

[PowerPC] Change `half` to use soft promotion rather than `PromoteFloat` (#152632)

On PowerPC targets, `half` uses the default legalization of promoting to
a `f32`. However, this has some fundamental issues related to inability
to round trip. Resolve this by switching to the soft legalization, which
passes `f16` as an `i16`.

The PowerPC ABI Specification does not define a `_Float16` type, so the
calling convention changes are acceptable.

Fixes the PowerPC part of
https://github.com/llvm/llvm-project/issues/97975
Fixes the PowerPC part of
https://github.com/llvm/llvm-project/issues/97981
DeltaFile
+957-1,766llvm/test/CodeGen/PowerPC/vector-lrint.ll
+957-1,766llvm/test/CodeGen/PowerPC/vector-llrint.ll
+275-590llvm/test/CodeGen/PowerPC/half.ll
+71-80llvm/test/CodeGen/PowerPC/llvm.frexp.ll
+30-75llvm/test/CodeGen/PowerPC/pr48519.ll
+49-34llvm/test/CodeGen/PowerPC/llvm.modf.ll
+2,339-4,3118 files not shown
+2,364-4,39714 files

LLVM/project 5f590edllvm/lib/Target/SystemZ SystemZAsmPrinter.cpp

[SystemZ][z/OS] Improve use of formatv (#174503)

Using a `raw_svector_ostream` object is not necessary, because this is
hidden in the conversion function. In addition, there is no need to
reason about a zero termination of the string. Declaring the ascii and
ebcdic version of the string variables at the same time makes sure that
both strings are allocated with the same size.
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+9-15llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+9-151 files

LLVM/project fa53d92flang/lib/Semantics expression.cpp, flang/test/Semantics bug127425.f90

[flang] Check for errors when analyzing array constructors (#173092)

Errors in array constructor values result in the array having
less elements than it should, which can cause other errors that
will confuse the user. Avoid this by not returning an expression
on errors.

Fixes #127425
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+10-0flang/test/Semantics/bug127425.f90
+4-0flang/lib/Semantics/expression.cpp
+14-02 files

OPNSense/core f0f9e1f. plist, src/opnsense/mvc/app/models/OPNsense/Radvd Radvd.xml

Add VipLinkLocalField for the source_address validation
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+114-0src/opnsense/mvc/app/models/OPNsense/Radvd/FieldTypes/VipLinkLocalField.php
+2-2src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.xml
+1-0plist
+117-23 files

OPNSense/core 6d92f2asrc/opnsense/mvc/app/controllers/OPNsense/Radvd/forms dialogEntry.xml

Change labels in dialog
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+4-2src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms/dialogEntry.xml
+4-21 files

LLVM/project f084590llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp SOPInstructions.td

[AMDGPU] Add intrinsic exposing s_alloc_vgpr

Make it possible to use `s_alloc_vgpr` at the IR level. This is a huge
footgun and use for anything other than compiler internal purposes is
heavily discouraged. The calling code must make sure that it does not
allocate fewer VGPRs than necessary - the intrinsic is NOT a request to
the backend to limit the number of VGPRs it uses (in essence it's not so
different from what we do with the dynamic VGPR flags of the
`amdgcn.cs.chain` intrinsic, it just makes it possible to use this
functionality in other scenarios).
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+63-0llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
+16-0llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+11-0llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+9-0llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
+4-2llvm/lib/Target/AMDGPU/SOPInstructions.td
+4-0llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+107-21 files not shown
+108-27 files

LLVM/project d7ebd9cllvm/include/llvm/IR IntrinsicsAMDGPU.td

Address review comments
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+4-5llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+4-51 files

LLVM/project 7c316c7llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp

Silence warning
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+2-2llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+2-21 files

LLVM/project 9e78d8autils/bazel/llvm-project-overlay/mlir BUILD.bazel

Revert "[BAZEL] Move FuncTransformsPassIncGen to CAPIIR header dep (#174982)"

This reverts commit 46d0862773ac3ac07fd1a8abe76db623b26d7d45.

This previously landed a couple commits ago and now duplicates the dep,
breaking the bazel build.
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+0-1utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+0-11 files

OpenBSD/ports aAG3sE8math/lapack Makefile distinfo

   switch to GH_* so that portroach can find distfiles
   keep at 3.12.0 for now, 3.12.1 needs a patch and wider arch testing
VersionDeltaFile
1.41+17-21math/lapack/Makefile
1.9+2-2math/lapack/distinfo
+19-232 files

LLVM/project 46d0862utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[BAZEL] Move FuncTransformsPassIncGen to CAPIIR header dep (#174982)

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+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

Illumos/gate ef0efd1usr/src/uts/common/io/sfxge/common efx_nvram.c

17762 sfxge: variable dereferenced before check
Reviewed by: Jason King <jason.brian.king at gmail.com>
Reviewed by: Marco van Wieringen <marco.van.wieringen at planets.elm.net>
Approved by: Patrick Mooney <pmooney at pfmooney.com>
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+3-2usr/src/uts/common/io/sfxge/common/efx_nvram.c
+3-21 files

LLVM/project 94c1209mlir/include/mlir/Interfaces ControlFlowInterfaces.td

[mlir][Interfaces] Document that `RegionBranchTerminatorOpInterface` is mandatory
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+19-2mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+19-21 files

NetBSD/pkgsrc qwDbt1vdevel/php-xdebug Makefile, graphics/php-jpgraph Makefile

   Remove reference to php81.
VersionDeltaFile
1.60+2-2devel/php-xdebug/Makefile
1.26+2-2graphics/php-jpgraph/Makefile
1.9+2-2mail/php-dmarc-srg/Makefile
1.42+2-2mail/php-imap/Makefile
1.4+2-2multimedia/php-avideo-encoder-network/Makefile
1.6+2-2multimedia/php-avideo-encoder/Makefile
+12-1218 files not shown
+48-4824 files

LLVM/project f76417dllvm/lib/Transforms/Utils LoopConstrainer.cpp, llvm/test/Transforms/IRCE loop-guarded-bounds.ll

[IRCE] Prove predicates with and without loop-guarded SCEVs (#174843)

IRCE may fail to prove predicates when loop bounds are rewritten by
LoopConstrainer::applyLoopGuards(). In such cases, simple predicates
(e.g. %start < %limit) become obscured by strengthened SCEV expressions,
even though they are trivially implied by the guard in the loop
preheader.

See: https://github.com/llvm/llvm-project/issues/167827

This change makes IRCE attempt to prove predicates both on the original
SCEVs and on the guarded SCEVs, preventing incorrect rejection of loops
with safe bounds.
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+136-0llvm/test/Transforms/IRCE/loop-guarded-bounds.ll
+20-14llvm/lib/Transforms/Utils/LoopConstrainer.cpp
+156-142 files