FreeBSD/ports 821f460math/py-pywavelets Makefile distinfo, math/py-pywavelets/files patch-pyproject.toml

math/py-pywavelets: Update to 1.10.0

Release notes: https://github.com/PyWavelets/pywt/releases/tag/v1.10.0
DeltaFile
+3-5math/py-pywavelets/files/patch-pyproject.toml
+3-3math/py-pywavelets/distinfo
+2-3math/py-pywavelets/Makefile
+8-113 files

FreeBSD/ports 099249aemulators/dosbox-staging Makefile pkg-plist, emulators/dosbox-staging/files patch-meson.build patch-cmake_add__install__rules.cmake

emulators/dosbox-staging: Update to 0.83.0

Switch to CMake, Meson is not supported anymore. ALSA and FLUIDSYNTH
support could be made optional again by patching build files, however
I do not want touch them more than required for building DOSBox.

Release notes: https://www.dosbox-staging.org/releases/release-notes/0.83.0/
DeltaFile
+143-77emulators/dosbox-staging/pkg-plist
+16-28emulators/dosbox-staging/Makefile
+29-0emulators/dosbox-staging/files/patch-CMakeLists.txt
+24-0emulators/dosbox-staging/files/patch-src_network_ethernet__slirp.cpp
+22-0emulators/dosbox-staging/files/patch-cmake_add__install__rules.cmake
+0-20emulators/dosbox-staging/files/patch-meson.build
+234-1253 files not shown
+250-1389 files

FreeBSD/ports 498b333archivers/7-zip Makefile distinfo

archivers/7-zip: Update to 26.03

Release notes: https://sourceforge.net/p/sevenzip/discussion/45797/thread/db6922e1d0/
DeltaFile
+3-3archivers/7-zip/distinfo
+1-1archivers/7-zip/Makefile
+4-42 files

FreeBSD/ports b2659bbgames/legend-of-edgar Makefile distinfo, games/legend-of-edgar/files patch-makefile

games/legend-of-edgar: Update to 1.38

Release notes: https://github.com/riksweeney/edgar/releases/tag/1.38
DeltaFile
+12-3games/legend-of-edgar/files/patch-makefile
+3-3games/legend-of-edgar/distinfo
+1-2games/legend-of-edgar/Makefile
+16-83 files

LLVM/project 8e84c4allvm/test/CodeGen/AArch64 arm64-abi_align.ll, llvm/test/CodeGen/Hexagon/vect vect-xor.ll vect-v4i16.ll

llvm: Remove phantom ssp-buffers-size attributes from tests (#221928)

"ssp-buffers-size" was never a real function attribute. There is
"stack-protector-buffer-size". This may have existed in a downstream
fork, but it's also irrelevant for these tests.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+4-4llvm/test/CodeGen/AArch64/arm64-abi_align.ll
+2-2llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
+1-1llvm/test/Transforms/LoopVectorize/vectorize-once.ll
+1-1llvm/test/Transforms/LoopVectorize/dbg.value.ll
+1-1llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
+1-1llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
+10-102 files not shown
+12-128 files

NetBSD/pkgsrc ZG1d75Kdatabases/lmdb Makefile distinfo, databases/openldap Makefile.version distinfo

   openldap: updated to 2.7.1

   OpenLDAP 2.7.1 Release (2026/09/08)
        Fixed libldap BER leak on notice of disconnection
        Fixed libldap request leak on malformed BER response
        Fixed libldap error stack handling with OpenSSL < 4.0
        Fixed lload non-blocking BIO handling in SSL renegotiations
        Fixed slapo-ppolicy handling of old passwords
        Documentation
                slapo-pcache added note about referral chasing
        Minor Cleanup
VersionDeltaFile
1.149+4-4databases/openldap/distinfo
1.50+4-4databases/openldap-doc/distinfo
1.44+4-4databases/lmdb/distinfo
1.31+2-3databases/lmdb/Makefile
1.49+2-2databases/openldap/Makefile.version
+16-175 files

FreeNAS/freenas afb3dbe

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

FreeNAS/freenas d87350c

Empty commit to create PR on github.

You should reset it
DeltaFile
+0-00 files

LLVM/project 7f0421bllvm/lib/Target/AMDGPU SIISelLowering.h SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU mmra.ll idemponent-atomics.ll

[AMDGPU] Remove unsound idempotent atomicrmw to atomic load lowering (#218377)

An idempotent atomicrmw still holds a slot in the modification order, so
folding it to a plain load can drop synchronization the memory model
requires
DeltaFile
+223-58llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
+33-2llvm/test/CodeGen/AMDGPU/mmra.ll
+5-24llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+0-3llvm/lib/Target/AMDGPU/SIISelLowering.h
+261-874 files

LLVM/project 17b659blldb/unittests/Target MemoryTest.cpp

[lldb] [unittests] Cover what the memory cache reads from the inferior (#221015)

`MemoryCache`'s tests checked how many bytes a read returned, never
which requests the cache made to get them, so a change to the request
shape could not fail a test.  Add four tests over the request log
`DummyProcess` now keeps.

Two assert what the cache sends: `TestReadRequestShape` checks the
address and size of every request, and `TestReadRangesFromCaches` checks
that a range the cache already holds is served without reaching the
inferior.

`TestFlushAtTheTopOfTheAddressSpace` pins `Flush`'s current behavior at
the wrap, not correct behavior.  When a flushed range wraps past
`UINT64_MAX`, `Flush` counts cache lines only from the start of the
range to the top of the address space, never the lines the wrapped
portion covers between address 0 and the range's end.  This bug predates
this change; the following cache-partition change fixes it, and this
test's assertion that address 0 survives the flush will need to flip

    [13 lines not shown]
DeltaFile
+236-46lldb/unittests/Target/MemoryTest.cpp
+236-461 files

LLVM/project 0c62d83llvm/lib/Transforms/Vectorize VPlan.cpp VPlanUtils.cpp

[VPlan] Record estimated branch probabilities on VPlan0 for cost modeling (#216172)

Update execution frequency/probability tracking in VPlan to also include
estimates from BFI, and use the information in VPlan for VPlan-based
cost computations, removing another remaining IR-based lookup.

We need to differentiate between estimated and concrete profile
information when annotating branches with information from BFI (using
custom !vplan.prof.estimated metadata instead of !prof) and track if a
computed frequency contains any estimates using an extra bool which is
also encoded in the metadata (so we do not synthesize !prof
for such frequencies during codegen).

The new code should only request BFI if needed, and compile-time impact
should be in the noise:

https://llvm-compile-time-tracker.com/compare.php?from=8436dd4a2bfe57d0b3fb6c9c11c69d75c1d1bccb&to=4d60694fed5e5765d4f5a2a72aac7b8674e512e2&stat=instructions:u

PR: https://github.com/llvm/llvm-project/pull/216172
DeltaFile
+33-25llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+41-9llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+43-3llvm/lib/Transforms/Vectorize/VPlan.h
+24-16llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+18-11llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+15-0llvm/lib/Transforms/Vectorize/VPlan.cpp
+174-6411 files not shown
+227-9217 files

LLVM/project 4b8b168llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU read-register-src-flat-scratch-base.ll write-register-src-flat-scratch-base.ll

[AMDGPU] Add getRegisterByName support for src_flat_scratch_base (#220560)

Expose `src_flat_scratch_base`, `src_flat_scratch_base_lo`, and
`src_flat_scratch_base_hi` through `llvm.read_register` /
`llvm.write_register`.

The implementation is basically the same as the existing named-register
support for `flat_scratch`

It errors out on targets without `FeatureGloballyAddressableScratch`
(pre-gfx1250).
DeltaFile
+92-0llvm/test/CodeGen/AMDGPU/type-mismatch-src-flat-scratch-base.ll
+52-0llvm/test/CodeGen/AMDGPU/read-write-register-src-flat-scratch-base-invalid-subtarget.ll
+38-0llvm/test/CodeGen/AMDGPU/write-register-src-flat-scratch-base.ll
+35-0llvm/test/CodeGen/AMDGPU/read-register-src-flat-scratch-base.ll
+23-9llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+240-95 files

LLVM/project d6a334dllvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/test/MC/AMDGPU buffer-op-lds-operand.s

[AMDGPU][AsmParser]: Use dummy operand for parsing buffer LDS isAsync… (#219459)

… operand.

After the introduction of .async for LDS buffer ops variants, there a
similar mca crash addressed in
https://github.com/llvm/llvm-project/pull/165305. This parses a dummy
operand as a placeholder.
DeltaFile
+51-0llvm/test/tools/llvm-mca/AMDGPU/buffer-op-lds-operand.s
+29-0llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
+4-0llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+84-03 files

OpenBSD/ports psQjOA8devel/kf6/kmime distinfo Makefile, devel/kf6/kmime/pkg PLIST DESCR

   Initial revision
VersionDeltaFile
1.1+103-0devel/kf6/kmime/pkg/PLIST
1.1+16-0devel/kf6/kmime/Makefile
1.1+2-0devel/kf6/kmime/distinfo
1.1+1-0devel/kf6/kmime/pkg/DESCR
1.1.1.1+0-0devel/kf6/kmime/pkg/PLIST
1.1.1.1+0-0devel/kf6/kmime/pkg/DESCR
+122-02 files not shown
+122-08 files

OpenBSD/ports ACdXbp4devel/ruff Makefile crates.inc

   Update to ruff 0.16.6 from maintainer

   https://github.com/astral-sh/ruff/releases/tag/0.16.3
   https://github.com/astral-sh/ruff/releases/tag/0.16.4
   https://github.com/astral-sh/ruff/releases/tag/0.16.5
   https://github.com/astral-sh/ruff/releases/tag/0.16.6
VersionDeltaFile
1.18+24-16devel/ruff/distinfo
1.18+11-7devel/ruff/crates.inc
1.19+1-1devel/ruff/Makefile
+36-243 files

LLVM/project cd2f665llvm/include/llvm/CodeGen/GlobalISel GISelWorkList.h

[GlobalISel] Lazily reserve worklist maps (NFC) (#221900)

Small -0.03% geomean improvement on CTMark aarch64-O0-g, but consistent
little improvements across the board.

https://llvm-compile-time-tracker.com/compare.php?from=97cbc1e404b980edc58bfbcabb6f1c61793b624b&to=1729db67721b79fcb72469111d543e6df28c1185&stat=instructions:u

Assisted-by: codex
DeltaFile
+2-4llvm/include/llvm/CodeGen/GlobalISel/GISelWorkList.h
+2-41 files

OpenBSD/ports CsNyJ0Ydevel/uv Makefile crates.inc

   Update to uv 0.12.10 from maintainer

   https://github.com/astral-sh/uv/releases/tag/0.12.7
   https://github.com/astral-sh/uv/releases/tag/0.12.8
   https://github.com/astral-sh/uv/releases/tag/0.12.9
   https://github.com/astral-sh/uv/releases/tag/0.12.10
VersionDeltaFile
1.39+22-28devel/uv/distinfo
1.38+10-13devel/uv/crates.inc
1.43+1-1devel/uv/Makefile
+33-423 files

LLVM/project 9a14832llvm/lib/Target/AMDGPU SIInstrInfo.cpp

[AMDGPU] Check a wide copy dst reg against the dst operand's regclass (#221789)

The wide-copy check added in #214561 tested the destination against the
source operand's class. No test change: V_MOV_B64's source class VS_64
also accepts a VGPR destination, which is why it currently works. Adding
@robertvirany.

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+7-5llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+7-51 files

LLVM/project 411a8eeopenmp/runtime/src kmp_settings.cpp kmp_traits.h, openmp/runtime/src/i18n en_US.txt

[libomp] Parse OMP_DEFAULT_DEVICE with new device trait parser (#176166)

... but do not yet expose the new functionalities to the user. This is a
backward compatible update that is going to be followed by the step to
the OpenMP 6.0 semantics as defined in 4.3.8.
DeltaFile
+105-0openmp/runtime/unittests/Traits/TestOMPTraitParser.cpp
+24-0openmp/runtime/src/kmp_traits.cpp
+8-0openmp/runtime/src/kmp_traits.h
+3-2openmp/runtime/src/kmp_settings.cpp
+3-0openmp/runtime/src/i18n/en_US.txt
+143-25 files

LLVM/project f42f403clang/test/Frontend optimization-remark-target-features-arm.c optimization-remark-target-features-aarch64.c, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

[AsmPrinter] target-features optimization remarks

In clang we have --print-enabled-extensions which will print the
AArch64 extensions enabled for a given TU. However, sometimes it is
useful to be able to print out the actual subtarget features for each
function, for debugging/testing purposes. Add an optimization remark
for that.
DeltaFile
+45-0llvm/test/CodeGen/AArch64/optimization-remark-target-features.ll
+30-0clang/test/Frontend/optimization-remark-target-features-aarch64.c
+30-0llvm/test/CodeGen/ARM/optimization-remark-target-features.ll
+19-0clang/test/Frontend/optimization-remark-target-features-arm.c
+17-0llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+141-05 files

LLVM/project 68a77b6clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-wave32.hip builtins-amdgcn-wave64.hip

[CIR][AMDGPU] Implement inverse_ballot and read_exec codegen (#221661)

This commit implements the CIR codegen for the following AMDGPU
builtins:
- __builtin_amdgcn_inverse_ballot_w32
- __builtin_amdgcn_inverse_ballot_w64
- __builtin_amdgcn_read_exec
- __builtin_amdgcn_read_exec_lo
- __builtin_amdgcn_read_exec_hi

inverse_ballot_w32/w64 map to llvm.amdgcn.inverse.ballot. read_exec,
read_exec_lo and read_exec_hi read the exec mask as a ballot over an
all-true predicate, at least as wide as the wavefront.
DeltaFile
+42-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave64.hip
+40-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-wave32.hip
+21-10clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+103-103 files

FreeBSD/ports f1c5375audio/waves Makefile distinfo

audio/waves: Update to 0.1.49

ChangeLog:

1. https://github.com/llehouerou/waves/releases/tag/v0.1.49

Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+5-5audio/waves/distinfo
+1-1audio/waves/Makefile
+6-62 files

LLVM/project f796b25llvm/lib/Target/Mips MipsAsmPrinter.h MipsAsmPrinter.cpp, llvm/test/CodeGen/Mips jalr-no-mangle.ll

[Mips] Strip \x01 no-mangle prefix from R_MIPS_JALR symbol name (#219427)

R_MIPS_JALR relocation did not strip the \x01 no-mangle prefix, causing
linker to see two different symbols: my_target_sym and
\x01my_target_sym.

Use Mangler::getNameWithPrefix() to process the symbol name.

Fix #207470.
DeltaFile
+30-0llvm/test/CodeGen/Mips/jalr-no-mangle.ll
+7-7llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+3-0llvm/lib/Target/Mips/MipsAsmPrinter.h
+40-73 files

FreeBSD/ports b086623devel/py-virtualenv distinfo Makefile

devel/py-virtualenv: Update to 21.7.9

- Disable test target due to the following startup error:

pluggy._manager.PluginValidationError: Plugin 'black' for hook 'pytest_collect_file'
hookimpl definition: pytest_collect_file(file_path, path, parent)
Argument(s) {'path'} are declared in the hookimpl but can not be found in the hookspec

See https://github.com/pytest-dev/pytest/issues/14651

- Pet portfmt

ChangeLog:      https://github.com/pypa/virtualenv/releases/tag/21.7.9

Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+8-4devel/py-virtualenv/Makefile
+3-3devel/py-virtualenv/distinfo
+11-72 files

LLVM/project 1c21c5fllvm/test/CodeGen/AArch64 arm64-abi_align.ll, llvm/test/CodeGen/Hexagon/vect vect-xor.ll vect-v4i16.ll

llvm: Remove phantom ssp-buffers-size attributes from tests

"ssp-buffers-size" was never a real function attribute. There is
"stack-protector-buffer-size". This may have existed in a downstream
fork, but it's also irrelevant for these tests.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+4-4llvm/test/CodeGen/AArch64/arm64-abi_align.ll
+2-2llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
+1-1llvm/test/Transforms/LoopVectorize/vectorize-once.ll
+1-1llvm/test/Transforms/LoopVectorize/dbg.value.ll
+1-1llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
+1-1llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
+10-102 files not shown
+12-128 files

LLVM/project 6390ccdllvm/test/CodeGen/AArch64 arm64-abi_align.ll, llvm/test/CodeGen/Hexagon/vect vect-xor.ll vect-v4i16.ll

llvm: Remove phantom relocation-model attributes from tests

"relocation-model" was never a real function attribute.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+4-4llvm/test/CodeGen/AArch64/arm64-abi_align.ll
+2-2llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
+1-1llvm/test/Transforms/LoopVectorize/vectorize-once.ll
+1-1llvm/test/Transforms/LoopVectorize/dbg.value.ll
+1-1llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
+1-1llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
+10-102 files not shown
+12-128 files

LLVM/project 39ffb93llvm/test/CodeGen/AArch64 arm64-abi_align.ll, llvm/test/CodeGen/Hexagon/vect vect-xor.ll vect-v4i16.ll

llvm: Remove phantom fp-contract-model attributes from tests (#221925)

This attribute has never been consumed by upstream llvm,
or emitted by upstream clang. I can only guess this existed in
at least one downstream fork.
DeltaFile
+4-4llvm/test/CodeGen/AArch64/arm64-abi_align.ll
+2-2llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
+1-1llvm/test/Transforms/LoopVectorize/vectorize-once.ll
+1-1llvm/test/Transforms/LoopVectorize/dbg.value.ll
+1-1llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
+1-1llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
+10-102 files not shown
+12-128 files

OpenBSD/src q3wrp4Jusr.bin/tmux layout-custom.c

   Add a nesting limit for v1 layouts, reported by M Khalilov, fix based on
   issue 5572 from Afonso Januário. Also tweak some language while here.
VersionDeltaFile
1.41+16-9usr.bin/tmux/layout-custom.c
+16-91 files

FreeBSD/src 6af3031sys/dev/tpm tpm_crb.c

tpm: crb: make the Pluton startmethod more resilient

The original implementation assumed that the start/reply doorbells
lived within the device _CRS space, but that isn't always the case.  On
my AMD Ryzen 7640U-based frame.work laptop, device memory runs from
0xc0500000-0xc0500fff while the doorbells are up around 0xc0508000.

Stop sanity checking the addresses and just map them in to work reliably
whether they're within the device range or not.

pluton_wait_reply is cribbed from tpm_wait_for_u32, but rewritten
slightly to read in just one place and to read one last time before
giving up at the end of the timeout, just in case.

Reviewed by:    kbowling
Differential Revision:  https://reviews.freebsd.org/D59327
DeltaFile
+88-29sys/dev/tpm/tpm_crb.c
+88-291 files

LLVM/project 1770693llvm/lib/Transforms/Vectorize VPlanRecipes.cpp

[VPlan] Add scalar-type-infer assert for casts (NFC) (#222258)

Casts require the ResultTy to be passed: add an assert to
computeScalarTypeForInstruction to guard against incorrect usage.
DeltaFile
+2-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+2-01 files