[SLP]Drop auxiliary subtrees to pass the VF=2 instruction-count veto
The veto rejected the whole VF=2 tree when an optional splat gather
root or gathered loads subtree tipped the vector instruction count
over the scalar count. Drop the reused auxiliary subtrees while the
tree exceeds the budget; the surviving gathers re-materialize their
scalars.
Assisted-by: Cursor
Reviewers: bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/224108
WebAssembly: Partially clean up subtarget construction
There should be just one getSubtargetImpl(Function&) override like every
other target, but this is relying on the global subtarget. Remove the
argumentless form since it's unnecessary.
WebAssemblyCoalesceFeaturesAndStripAtomics doesn't really need to construct
a full new subtarget for its purpose and can directly take the global subtarget
feature bits. This pass is also doing quite a lot of other bad things, like
mutating the TargetMachine.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
*/*: Deprecate python2 consumers
lang/python2 and lang/python27 have been deprecated since 2020-01-01 and their
EXPIRATION_DATE of 2020-12-31 passed nearly six years.
Set the same expiration date on the remaining python:2.7 consumers so that
python2 and python27 can be removed on 2026-11-01
The date was chosen to fall after the 2026Q4 branch is created, so that the
removal happens on main only and the quarterly branch keeps python2 for its
full lifetime.
Approved by: portmgr
[libc] Add support for SYS_fchmodat2 in fchmodat (#223997)
### Summary
Linux kernel 6.6 introduced the `SYS_fchmodat2` system call, which
accepts a 4th `flags` argument (`int fchmodat2(int dirfd, const char
*pathname, mode_t mode, unsigned int flags)`). This allows flags like
`AT_SYMLINK_NOFOLLOW` and `AT_EMPTY_PATH` to be passed directly to the
kernel.
Following the discussion on #223165, this patch adds support for
`SYS_fchmodat2` in `fchmodat`, while providing fallbacks when
`SYS_fchmodat2` is not supported.
Fixes #223953
Formatted using Gemini.
---------
Co-authored-by: Pavel Labath <pavel at labath.sk>
clang-linker-wrapper: Set the host DataLayout on the offload wrapper module (#224280)
The offload wrapper module was created with only a target triple, and
the datalayout wasn't set until later, where it was copied from the
TargetMachine, after the wrapping code already ran.
The wrapping code did query the datalayout for the pointer size, so this
was broken for host and devices with different pointer sizes. queries the
DataLayout (e.g. the size_t / intptr type via getSizeTTy), so on a
host whose pointer size differs from the default layout (e.g. a 32-bit
host) it used the wrong integer width for image offsets.
This removes a use of TargetMachine::createDataLayout, which I am trying
to remove.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Add middleware support for LIO ALUA HA
Wire up the middleware side of LIO ALUA high-availability: load
lio_ha.ko with per-node addresses on service start, manage ALUA
state across failover events, clean up STANDBY configfs on pool
export, and add pre-flight validation that targets have static
initiator ACLs before ALUA can be enabled.
For each target, create a portal-less phantom TPG carrying the peer
node's controller group so that a single RTPG response from any
connected port lists both ALUA groups. Write tpgt_N/rtpi explicitly
before enable so that relative target port IDs in RTPG match the
tag formula (portal.tag on Node A, portal.tag + 32000 on Node B)
rather than being auto-assigned sequentially by the kernel.
ALUA group states are driven by role and ha_state:
MASTER + synced local=OPTIMIZED remote=NONOPTIMIZED
MASTER + connected local=OPTIMIZED remote=TRANSITIONING
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[SLP]Model or-reduction of masked shifted lanes as a bitfield pack
An or reduction of and(shl(x, s), m) lanes that each cover a disjoint
contiguous byte field of the result is a repacking of the per-lane field
contents, not a shift and reduce. Prove the fields disjoint from the
per-lane possibly-set bits (a saturating numeric upper bound combined with
known bits), then emit the pack as a trunc, an optional per-lane lshr, a
byte shuffle and a bitcast. A plain byte reversal becomes a bswap, an
identity byte order needs no shuffle, and byte-zext lanes compact for free.
Fixes #175446
Assisted-by: Cursor
Reviewers: bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/219731
[RISCV] Account for VL toggle cost when splitting VP memory intrinsics (#223992)
Not an alternative to #222836 since this doesn't handle all cases, but
something we should do anyway in the TTI to be accurate.
For vp.load/vp.gather/vp.strided.load and their store counterparts, when
they're split they introduce extra vl toggles which involve computation
on the evl, e.g.
vsetvli a2, zero, e8, mf4, ta, ma
vmv1r.v v8, v0
csrr a2, vlenb
srli a3, a2, 3
vslidedown.vx v0, v0, a3
sub a3, a1, a2
sltu a4, a1, a3
addi a4, a4, -1
slli a5, a2, 3
and a3, a4, a3
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kernel - Fix lost wakeup in fifo_open()
* fifo_open() tests fi_readers, drops the fifo and vnode locks, then
tsleeps. A peer opening in that window bumps the counter and issues
its wakeup before the sleeper is queued, so open(2) blocks forever
with a peer already attached. Both paths are affected.
* Queue with tsleep_interlock() before releasing the locks and sleep
with PINTERLOCKED.
Reviewed-by: @dillon
[clang][bytecode] Add a function frame allocator (#220229)
Add a function frame allocator we share across evaluations.
For code like
```c++
consteval int foo() {
int a = 0;
for (int i = 0; i != 10; ++i)
inc(a);
return a;
}
```
We previously `new[]`-ed a frame for every call of `inc()`, and
`delete[]`d the memory again directly after, resulting in lots of small
(in this case) allocations.
Add a `FrameAllocator` class that handles frames like a LIFO stack and
allocates memory in 4kb chunks. If a newly created frame fits into an
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[AArch64] Use SVE for load-extend-broadcast (#221689)
On certain cores, it is faster to use SVE ld1r instructions to load,
extend and broadcast an integer value to a vector in all cases other
than 64bit vectors where no type promotion occurs.
To acheive this, introduce a tuning option, `PreferSVEVectors` for use
when combining DUP instructions to create a Splat Vector to the scalable
alternative, and then use the already implemented scheduling model
patterns for splat vectors to end up generate the ld1r instruction.
If used in a loop, the predicate will be hoisted outside of the loop.
icmp: Limit routing table updates to the FIB of the redirect
When we receive an ICMP redirect, rib_add_redirect() is used to apply
the redirect to all FIBs. This has been the case since support for
multiple FIBs was added. However, it seems rather dubious: the new
gateway might not be routable from all FIBs, and the validation done for
v4 redirects in icmp_verify_redirect_gateway() is only applied to the
FIB from which the redirect originated.
Modify the handler to apply the redirect only in the originating FIB.
Reported by: Yuxiang Yang, Yizhou Zhao, Ao Wang, Xuewei Feng, Qi Li,
and Ke Xu from Tsinghua University using GLM-5.1 from Z.ai
Reviewed by: pouria, zlei, glebius, melifaro
MFC after: 3 weeks
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D59567
