[RISCV][SelectionDAG] Add a ISD::CTLS node for count leading redundant sign bits. Use it to select CLS(W). (#173417)
The RISC-V P extension adds an instruction equivalent to
__builtin_clrsb. AArch64 has a similar instruction that we currently fail to
select when using the builtin.
This patch adds a combine based on the canonical version of the pattern
emitted by clang for the builtin, (add (ctlz (xor x, (sra x, bw-1)))),
-1). I'm starting the combine at the ctlz because the outer add can
easily be combined into other nodes obscuring the full pattern. So we
generate (add (ctls x), 1) and hope the add will be combined away.
I've also added a combine for the pattern AArch64 recognizes
(ctlz_zero_undef (or (shl (xor x, (sra x, bw-1)), 1), 1)).
I've only enabled the combines when the target has a Legal or Custom
action for the operation, taking into account type promotion. We
can relax this in the future by adding a default expansion to
LegalizeDAG and adding more type legalization rules.
py-filelock: update to 3.20.2.
Support Unix systems without O_NOFOLLOW by @mwilliamson in #463
[pre-commit.ci] pre-commit autoupdate by @pre-commit-ci[bot] in #464
py-astroid: update to 4.0.3.
Release date: 2026-01-03
Fix inference of IfExp (ternary expression) nodes to avoid prematurely narrowing
results in the face of inference ambiguity.
Closes #2899
Fix base class inference for dataclasses using the PEP 695 typing syntax.
Refs pylint-dev/pylint#10788
py-aiohttp: update to 3.13.3.
3.13.3 (2026-01-03)
===================
This release contains fixes for several vulnerabilities. It is advised to
upgrade as soon as possible.
Bug fixes
---------
- Fixed proxy authorization headers not being passed when reusing a connection, which caused 407 (Proxy authentication required) errors
- Fixed multipart reading failing when encountering an empty body part
- Fixed a case where the parser wasn't raising an exception for a websocket continuation frame when there was no initial frame in context.
Removals and backward incompatible breaking changes
---------------------------------------------------
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[RISCV] Update Andes45 vector load/stores scheduling info (#173806)
This PR adds latency/throughput for all RVV load/stores to the Andes45
series scheduling model.
Merge tag 'devicetree-fixes-for-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree fixes from Rob Herring:
- Fix an error path memory leak in DT unittest
- Update Saravana's bouncing email
* tag 'devicetree-fixes-for-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
of: unittest: Fix memory leak in unittest_data_add()
MAINTAINERS: Update Saravana Kannan's email address
refactor the matching of sk->sk_states entries in pf_find_state()
ive been looking at and trying to comprehend this code for what
feels like months of my life, and the af-to handling in particular.
it wasn't until i found the PF_AFRT handling in pf_test that it
suddenly clicked.
i figure it doesnt hurt to pull the code here apart a bit and put
some comments in place to help future travellers.
ok sashan@
