FreeBSD/src a556febshare/man/man7 freebsd-base.7

freebsd-base.7: Fix stray -r

Remote stray "-r" from the example of installing a toolchain
to alternate root.

Reviewed by:    ivy
Differential Revision:  https://reviews.freebsd.org/D54611
DeltaFile
+1-1share/man/man7/freebsd-base.7
+1-11 files

LLVM/project 1e5c4c0llvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+118-2llvm/docs/AMDGPUUsage.rst
+118-21 files

LLVM/project 15d5f43clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.def
+96-03 files

LLVM/project 084f235llvm/lib/Target/AMDGPU SIISelLowering.cpp

Use enum values for src modifiers.
DeltaFile
+6-7llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-71 files

LLVM/project 5243501llvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine icmp-srem.ll

[InstCombine] Guard foldICmpSRemConstant against zero divisors (#173702)

instcombine can create srem X, 0 or icmp ult X, 0 mid-pass when
operands fold to zero, which trips assertions in foldICmpSRemConstant.
Bail out on zero divisors / zero ULT constants instead of asserting,
and add a regression test from the minimized reproducer.

This was found by a fuzzer I'm working on.  The high-level design is to
randomly generate LLVM IR, run a pass on it, and then run the original
and new IR through the interpreter.  They should produce the same
results.  Right now I'm only fuzzing instcombine.
DeltaFile
+15-0llvm/test/Transforms/InstCombine/icmp-srem.ll
+2-2llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+17-22 files

LLVM/project a4ee3d9llvm/lib/Analysis InstructionSimplify.cpp, llvm/test/Transforms/InstCombine minmax-fp.ll

[Instcombine] Fix crash in foldMinimumMaximumSharedOp (#173705)

We were missing a check that the inner intrinsic is in fact a min/max
op.  We'd crash if it was any other intrinsic!

This was found by a fuzzer I'm working on.  The high-level design is to
randomly generate LLVM IR, run a pass on it, and then run the original
and new IR through the interpreter.  They should produce the same
results.  Right now I'm only fuzzing instcombine.
DeltaFile
+16-5llvm/lib/Analysis/InstructionSimplify.cpp
+16-0llvm/test/Transforms/InstCombine/minmax-fp.ll
+32-52 files

LLVM/project c39f8b4llvm/lib/Transforms/InstCombine InstCombineSelect.cpp, llvm/test/Transforms/InstCombine 2012-05-28-select-hang.ll

[Instcombine] Fix infinite loop in visitSelectInst (#173704)

Doing a nop replaceOperand leads us into an infinite loop here.

This was found by a fuzzer I'm working on.  The high-level design is to
randomly generate LLVM IR, run a pass on it, and then run the original
and new IR through the interpreter.  They should produce the same
results.  Right now I'm only fuzzing instcombine.
DeltaFile
+27-0llvm/test/Transforms/InstCombine/2012-05-28-select-hang.ll
+2-2llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+29-22 files

LLVM/project 4684e50llvm/lib/Transforms/InstCombine InstCombineMulDivRem.cpp, llvm/test/Transforms/InstCombine instcombine-dominance-fixup.ll

[Instcombine] Ensure simplifyValueKnownNonZero adds instrs in dominance order (#173703)

This was found by a fuzzer I'm working on.  The high-level design is to
randomly generate LLVM IR, run a pass on it, and then run the original
and new IR through the interpreter.  They should produce the same
results.  Right now I'm only fuzzing instcombine.
DeltaFile
+23-0llvm/test/Transforms/InstCombine/instcombine-dominance-fixup.ll
+7-3llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+30-32 files

LLVM/project 1c07ba6llvm/lib/Transforms/Scalar SeparateConstOffsetFromGEP.cpp, llvm/test/Transforms/SeparateConstOffsetFromGEP negative-i32-offset.ll

[SeparateConstOffsetFromGEP] Use getSigned() for accumulated offset

It's a signed quantity.

Fixes the issue reported at:
https://github.com/llvm/llvm-project/pull/171456#issuecomment-3727345950
DeltaFile
+16-0llvm/test/Transforms/SeparateConstOffsetFromGEP/negative-i32-offset.ll
+1-1llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+17-12 files

LLVM/project bd87ab1llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 stack-hazard.ll arm64-ccmp.ll

[AArch64] Optimize ANDS(CSET, CSET) to CCMP. (#174919)

We have existing optimizations for and(cset, cset) and or(cset, cset),
converting them to more optimal ccmp chains. This makes use of the same
optimization for ANDS instructions that do not require the result of the
AND (i.e. TSTs). We generate a cmp from a cset, for the flags produced
by the ANDS. This will then be optimised away in many cases, leaving the
ccmp and use of the flags.
DeltaFile
+12-18llvm/test/CodeGen/AArch64/stack-hazard.ll
+10-16llvm/test/CodeGen/AArch64/arm64-ccmp.ll
+20-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-4llvm/test/CodeGen/AArch64/fcmp-fp128.ll
+44-404 files

OPNSense/core 7abbca5src/opnsense/mvc/app/models/OPNsense/Radvd Radvd.php Radvd.xml

Add MinRtrAdvInterval and AdvDefaultLifetime validations to Radvd.php as the require calculations
DeltaFile
+57-1src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.php
+1-2src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.xml
+58-32 files

OPNSense/core daefd8asrc/opnsense/scripts/suricata setup.sh

Services: Intrusion Detection - load ipdivert for new inline mode (missing in https://github.com/opnsense/core/pull/9561)
DeltaFile
+3-0src/opnsense/scripts/suricata/setup.sh
+3-01 files

OpenBSD/ports JKRwjXJdevel/jjui distinfo modules.inc

   Update to jjui v0.9.9

   https://github.com/idursun/jjui/releases/tag/v0.9.9
VersionDeltaFile
1.17+40-22devel/jjui/distinfo
1.9+10-5devel/jjui/modules.inc
1.17+1-1devel/jjui/Makefile
+51-283 files

LLVM/project 1c9ef2cllvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+118-2llvm/docs/AMDGPUUsage.rst
+118-21 files

LLVM/project 5c4650dclang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.def
+96-03 files

LLVM/project b341295llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fadd.ll llvm.amdgcn.reduce.fsub.ll

[AMDGPU] Add wave reduce intrinsics for double types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,115-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+1,102-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+84-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2,303-204 files

LLVM/project 5ddf50ellvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmin.ll llvm.amdgcn.reduce.fmax.ll

[AMDGPU] Canonicalize NAN values for float reduction intrinsics
DeltaFile
+144-78llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+144-78llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+22-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+310-1573 files

LLVM/project 1ef30bcllvm/lib/Target/AMDGPU SIISelLowering.cpp

Refactor
DeltaFile
+9-8llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+9-81 files

LLVM/project 4f9a9ebllvm/lib/Target/AMDGPU SIInstrInfo.cpp SIInstrInfo.h, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll ran-out-of-sgprs-allocation-failure.mir

[AMDGPU] Add liverange split instructions into BB Prolog

The COPY inserted for liverange split during sgpr-regalloc
pipeline currently breaks the BB prolog during the subsequent
vgpr-regalloc phase while spilling and/or splitting the vector
liveranges. This patch fixes it by correctly including the
the LR split instructions during sgpr-regalloc and wwm-regalloc
pipelines into the BB prolog.
DeltaFile
+710-684llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+58-62llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
+27-7llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+797-7534 files

LLVM/project 7d21940llvm/include/llvm/CodeGen MachineInstr.h, llvm/lib/CodeGen SplitKit.cpp

[CodeGen] Introduce MI flag for Live Range split instructions

For some targets, it is required to identify the COPY instruction
corresponds to the RA inserted live range split. Adding the new
flag `MachineInstr::LRSplit` to serve the purpose.
DeltaFile
+2-1llvm/include/llvm/CodeGen/MachineInstr.h
+2-0llvm/lib/CodeGen/SplitKit.cpp
+4-12 files

FreeBSD/ports d1bd9b0security Makefile, security/py-k5test Makefile pkg-descr

[NEW PORT] security/py-k5test: Library for setting up self-contained Kerberos 5 environments

Co-authored-by: Michael Osipov <michaelo at FreeBSD.org>
PR:             278820
DeltaFile
+22-0security/py-k5test/Makefile
+3-0security/py-k5test/pkg-descr
+3-0security/py-k5test/distinfo
+1-0security/Makefile
+29-04 files

NetBSD/src CXIPiYzcommon/lib/libc/arch/hppa/atomic Makefile.inc, common/lib/libc/atomic atomic_init_testset.c

   hppa: Provide and expose ATOMIC64_OPS
VersionDeltaFile
1.17+20-14common/lib/libc/arch/hppa/atomic/Makefile.inc
1.21+3-2common/lib/libc/atomic/atomic_init_testset.c
1.35+2-1sys/arch/hppa/include/types.h
+25-173 files

LLVM/project 35e540dclang/include/clang/Sema Template.h, clang/test/SemaTemplate concepts.cpp

[Clang] Let isAnyArgInstantiationDependent handle Null template arguments (#174698)

Unused template parameters, though never referenced during substitution,
must remain in the MLTAL to preserve consistent template parameter
indices.

The null type placeholder plays this role, while
isAnyArgInstantiationDependent() doesn't properly handle this case when
checking nested constraints.

There is no release note because this is a regression from concept
parameter mapping.

Fixes https://github.com/llvm/llvm-project/issues/174667
DeltaFile
+10-0clang/test/SemaTemplate/concepts.cpp
+3-1clang/include/clang/Sema/Template.h
+13-12 files

LLVM/project 9f5efd5libcxx/include optional, libcxx/test/std/utilities/optional/optional.object/optional.object.assign copy.pass.cpp

[libc++] Correct `optional<T&>` implementation (#174537)

Resolves #174350

- Several issues were found in the current implementation of
`optional<T&>`
- `value()`, `operator*()`, `and_then()`, `transform()`, `operator->()`
still provided their ref-qualified versions for rvalues and `const&`.
- Using the listed methods on an rvalue `optional<T&>` would cause a
compile failure due to a mismatch in return types.
- On the latter, `operator*`, `operator->` would return `const` for a
`optional<T&>`, which is an incorrect deep const.
- A few constructors were missing (`optional<U>&`), and most
constructors relevant to `optional<T&>` were missing `noexcept`
- Constructors and `emplace` were not correctly constructing a `T&` as
specified in _`convert-ref-init-val`_
- Also corrects the behavior of `value_or` which should return
`remove_cv_t<T>` (in our case `decay_t<_Tp>`)
- Add several test cases to verify behavior, update `value_or` tests
DeltaFile
+261-79libcxx/include/optional
+84-0libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/optional_U.pass.cpp
+73-1libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_optional_U.pass.cpp
+66-1libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/U.pass.cpp
+44-22libcxx/test/std/utilities/optional/optional.object/optional.object.observe/dereference_const.pass.cpp
+55-1libcxx/test/std/utilities/optional/optional.object/optional.object.assign/copy.pass.cpp
+583-10428 files not shown
+1,192-18134 files

LLVM/project a2e8394lld/MinGW Options.td Driver.cpp, lld/test/MinGW driver.test

[LLD] [MinGW] Add the --fat-lto-objects flag (#174962)

This uses the same syntax as the ELF linker (added in
14e3bec8fc3e1f10c3dc57277ae3dbf9a4087b1c), mapping it to the recently
added COFF linker flag in
759fb0a224e85c01fffcd42b1e71a4bea6fc757e.
DeltaFile
+8-1lld/test/MinGW/driver.test
+8-0lld/MinGW/Options.td
+4-0lld/MinGW/Driver.cpp
+20-13 files

FreeBSD/ports 850ad03sysutils/hw-probe distinfo Makefile

sysutils/hw-probe: Upgrade port to 1.6.6

PR:             290230
Approved by:    danfe (maintainer timeout)
DeltaFile
+3-3sysutils/hw-probe/distinfo
+1-1sysutils/hw-probe/Makefile
+4-42 files

LLVM/project 5ac8a9bllvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fadd.ll llvm.amdgcn.reduce.fsub.ll

[AMDGPU] Add wave reduce intrinsics for double types - 2

Supported Ops: `add`, `sub`
DeltaFile
+1,115-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+1,102-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+84-20llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2-0llvm/lib/Target/AMDGPU/SIInstructions.td
+2,303-204 files

LLVM/project 0954641llvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+118-2llvm/docs/AMDGPUUsage.rst
+118-21 files

LLVM/project 20011f9clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.def
+96-03 files

LLVM/project dc068a6llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmax.ll llvm.amdgcn.reduce.fmin.ll

[AMDGPU] Canonicalize NAN values for float reduction intrinsics
DeltaFile
+144-78llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+144-78llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+21-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+309-1573 files