[ORC] Move ExecutorSharedMemoryMapperService names to sps_ci (#222835)
Relocate the service's interface names and SPS signatures from rt:: in
OrcRTBridge into a new Shared/SPSCI/SharedMemoryMapperSPSCI.h, matching
the existing SPSCI descriptor convention. Name-neutral: the symbol
strings are unchanged.
[MLIR] Fix infinite loop in tryFold in Graph Regions (#189232)
In a graph region (e.g. the module body), an op may use its own result
as an operand, creating a circular SSA dependency. When such an op was
passed to OpBuilder::tryFold, the do-while loop could spin forever:
1. foldCommutative moved the constant operand to the RHS (in-place fold,
foldResults still empty).
2. The next fold call returned the op's own result, signalling an
in-place fold, but foldSingleResultHook re-ran trait folds, found
nothing to swap, and returned success with empty foldResults.
3. Step 2 repeated without end.
Fix: cap the number of in-place fold iterations at 64. Legitimate chains
are very short in practice (foldCommutative swaps once, then the op folds to
a value or constant), so the cap is never reached for correct IR. For the
circular-SSA case the loop now terminates and tryFold returns failure,
letting dialect conversion fall through to a conversion pattern instead of
looping.
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[KnownFPClass] Add sNaN deductions for log/log2/log10 (#219703)
`log(x)` can only produce `sNaN` if `x` is `sNaN`.
This also affects tests for `llvm.amdgcn.log.f16` and
`llvm.amdgcn.log.f32`.
RISCV: Maintain VL/VTYPE liveness when clearing dead flags in InsertVSETVLI (#222862)
Drop the stale VL/VTYPE ranges when a dead flag is cleared.
RISCVInsertVSETVLI marks the VL and VTYPE defs of an explicit VSETVLI as
live by clearing their dead flags, but did not update LiveIntervals. When a def
was previously a dead def, its live range is a zero-length dead-def segment
ending at the def slot; clearing the flag extends the def past that slot
without extending the range leaving a segment that references no instruction.
Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
[GVN] Skip instructions without value numbers in `processNonLocalLoad` (#219851)
GVN may insert coercion instructions (MaterializeAdjustedValue) without
assigning them value numbers. If one becomes a GEP index of a PRE'd load
in the same processBlock sweep, the GEP-index scalar PRE in
processNonLocalLoad reaches it before the next re-numbering iteration
and the verifying VN.lookup() may assert. Avoid performing PRE on such
instructions.
Fixes: #216265.
[AArch64] Parameterize repeated FP divisor combine threshold by subtarget (#216930)
Changes:
This patch makes the threshold for combining repeated FP divisors
configurable per AArch64 subtarget, instead of using a single fixed
value 3 for all CPUs. Additionaly, set this value 2 for A64FX based on
observed profitability for this transform on A64FX.
Motivation:
Today, AArch64 uses a fixed threshold of 3 for reciprocal transform.
This means the transform runs when there are 3 FDIVs with the same
divisor (not 2). That is conservative for some subtargets, and it can
miss profitable opportunities on CPUs such as A64FX, where a lower
threshold appears to produce better code generation.
```
a / D; b / D; ...
=>
recip = 1.0 / D; a * recip; b * recip; ...
```
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[AMDGPU] Update buildbot cmake cache files (#222807)
This fixes one issue where the compiler-rt entry was not propagated to
the build.
We also want to select libgcc as the default unwindlib explicitly (as
this is what we do downstream).
[lldb] Fix handling of lldb managed software breakpoints (#222009)
Fixes #217910.
When the debug server can manage its own breakpoints this is called an
"external" breakpoint. When it cannot, lldb must manage the breakpoint
itself from the client side.
Part of doing that is FindInRange which is used to patch reads and
writes over software breakpoint sites. It had an issue where it would
not account for a breakpoint that started before the range, but extended
into the range. For example:
```
Memory content: ABCDEFGHIJKL
Read range: ----[--]----
Breakpoint location: -BKPT-------
Overlap with read: ----@-------
Expected read result: ----EFGH----
Would actually get: ----TFGH----
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ARM: Avoid relying on kill flags for determining CPSR liveness
When forming CBZ/CBNZ in ARMConstantIslands, check if CPSR is live-out
of the block instead of relying on the kill flag. Kill flags have been
soft deprecated for over a decade.
Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
[Clang] Improve error recovery for indexed template names (#222328)
There were a few issues here:
- Names that are not templates were not diagnosed and led to a crash (in
part because clang think they can be template names that will be later
resolved by ADL)
- Names that refer to a variable template decl, etc also led to a crash.
Fixes #220502
Co-authored-by: Cursor <cursoragent at cursor.com>
igb: Reinitialize through iflib after media changes
A media change can require a complete controller reset. Resetting the
controller directly from the admin task leaves iflib rings, filters, and
interface state programmed for the pre-reset controller.
Request an iflib reset for every media change. This already was done
when SR-IOV was active; use the same lifecycle for the ordinary PF case.
Sponsored by: BBOX.io
(cherry picked from commit 6248e7de9d6c0f14294afc5792170a68de6a3b53)
e1000: Serialize 82579 CSR writes with the Management Engine
The 82579 PCIm2PCI arbiter can acknowledge a host MAC CSR write while
the Management Engine is accessing another CSR. The host write can be
lost; subsequent target accesses may no longer be claimed by the MAC and
can hang the system.
For 82579 controllers with valid management firmware, wait for the ME
CSR access indication before every MAC CSR write. Keep the wait bounded
and use DELAY because writes occur in interrupt and datapath contexts.
Verify every transmit and receive tail write. If a tail does not hold
the requested value, disable its datapath direction and request a full
iflib reset.
Keep the ordinary register-write path as a direct MMIO write behind a
predicted per-device gate. Contain the wait and tail recovery in the
82579 slow path rather than adding tail-specific accessors and state to
the rest of the e1000 family.
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igb: Report 82580 memory ECC errors
82580 exposes clear-on-read, saturating corrected error counters for
the receive and transmit packet buffers. Its two PCIe command memories
expose RW1C indications for uncorrectable ECC errors.
Sample the packet buffer counters and PCIe indications from the regular
hardware statistics update. Fatal recovery samples the PCIe indications
from the serialized admin path rather than the interrupt filter. Thus,
either the regular statistics pass or recovery reads and clears each
indication, but they cannot both account it. Also preserve indications
observed while initialization is completing.
Expose the exact packet buffer error total and observed PCIe command
memory indications under the memory_errors sysctl node. Multiple PCIe
errors between samples can collapse into one indication per memory.
Validated on an Intel I340-T2 (82580, revision 1). A clean boot and
three down/up cycles left the packet-buffer, PCIe, and region-specific
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e1000: Recover from 82580 memory errors
82580 reports fatal parity and uncorrectable ECC errors through ICR.FER
and its four region PEIND hierarchy. Region specific status registers
identify PCIe, DMA transmit, DMA receive, DMA host, and LAN port
memories that can leave traffic stopped.
Enable the documented DMA, PCIe, packet-buffer, and host-owned LAN
parity and ECC checks only after initializing queue and filter tables.
Leave the flexible filter parity controls under management firmware
ownership. Capture read-clear and RW1C status in the interrupt filter
and keep FER masked until the admin task resolves the event.
Reset for a host-owned region or an unknown FER source. Leave
management-only recovery to firmware. Use CTRL.RST before master
disable because fatal 82580 memory errors can stop PCIe traffic. Do not
use CTRL.DEV_RST: specification update item 9 declares that bit reserved
and says it must always be written as zero. Wait for EEPROM auto read
completion; STATUS bit 21 is reserved on 82580, not PF_RST_DONE.
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e1000: Limit the TSO sentinel to lem(4) controllers
The TSO workaround splits the final DMA segment to create a four byte
sentinel descriptor. Intel documents the premature descriptor writeback
erratum and this workaround in the 82540EP and 82545GM specification
updates (erratum 3) and the 82546GB specification update (erratum 1).
Limit the workaround and its preceding TSO state to the legacy PCI and
PCI-X controllers so PCIe controllers retain their natural descriptor
layout using one fewer descriptor per TSO packet, no split of the final
segment, and one less four byte DMA.
Sponsored by: BBOX.io
(cherry picked from commit 2a7af8ebcf90af83f01f9523b25bfc6e58c7b809)
bsdinstall: add a hardening knob for unprivileged kenv access
It makes sense.
Reviewed by: zleei
(cherry picked from commit 6e81fbf5833d43529fd8a253b592af9666b04e8e)
route/fib_algo: Free leaked radix_masks in radix_lockless
radix_lockless algorithm creates its own radix tree and
allocates its own radix_masks by directly calling rnh_addaddr().
However, during destruction, it only frees the radix_tree without
freeing its allocated radix_masks.
Fix the leak by calling rn_delete() during radix_destroy().
PR: 297339
Reviewed by: melifaro
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D59112
(cherry picked from commit 790817f5a7a640c9ceb5c2ad99135f1a69aeb77d)
