LLVM/project 45408d7llvm/lib/Target/AMDGPU SIDefines.h, llvm/lib/Target/AMDGPU/Utils AMDGPUAsmUtils.cpp

AMDGPU: Correct value and name for ID_RTN_SAVE_WAVE_HAS_TDM

The old name and ID value do not match the documentation. The
documentation calls this RTN_SAVE_WAVE_HAS_TDM with the value
0x98.
DeltaFile
+6-2llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
+1-1llvm/lib/Target/AMDGPU/SIDefines.h
+1-1llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+8-43 files

LLVM/project 1ab00fdllvm/lib/Target/AMDGPU AMDGPUGlobalISelUtils.cpp

review: remove using IntrinsicLaneMaskAnalyzer for SI_IF and SI_ELSE
DeltaFile
+0-5llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+0-51 files

LLVM/project 197bfa9llvm/test/CodeGen/X86 select-big-integer.ll

[X86] Add tests showing potential for vectorising i128/256/512 select nodes (#180173)

DeltaFile
+730-0llvm/test/CodeGen/X86/select-big-integer.ll
+730-01 files

LLVM/project b472fd3clang/include/clang/Basic DiagnosticGroups.td DiagnosticSemaKinds.td

Reorganise permissive and strict diagnostic groups
DeltaFile
+59-12clang/include/clang/Basic/DiagnosticGroups.td
+7-10clang/include/clang/Basic/DiagnosticSemaKinds.td
+66-222 files

LLVM/project 8e16553clang/include/clang/Analysis/Analyses/LifetimeSafety Facts.h, clang/lib/Analysis/LifetimeSafety Checker.cpp LifetimeAnnotations.cpp

use-after-invalidation
DeltaFile
+337-0clang/test/Sema/warn-lifetime-safety-invalidations.cpp
+74-7clang/lib/Analysis/LifetimeSafety/Checker.cpp
+68-0clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
+26-1clang/test/Sema/Inputs/lifetime-analysis.h
+25-0clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h
+24-0clang/lib/Sema/AnalysisBasedWarnings.cpp
+554-89 files not shown
+619-915 files

LLVM/project 689c995llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine load-shufflevector.ll

[VectorCombine] Skip dead shufflevector in GetIndexRangeInShuffles to fix crash. (#179217)

Update GetIndexRangeInShuffles to skip unused shuffles. This matches the
behavior in the loop below and without it, we end up with an index
mis-match, causing a crash for the added test case.

PR: https://github.com/llvm/llvm-project/pull/179217
DeltaFile
+16-0llvm/test/Transforms/VectorCombine/load-shufflevector.ll
+5-0llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+21-02 files

LLVM/project bde4754lldb/tools/lldb-dap/Handler DisassembleRequestHandler.cpp

[lldb-dap] Remove end line and column from disassemble response (#180037)

The end line entry calculated from the instruction's end address is
unreliable and could produce incorrect source ranges. especially if the
instruction spans multiple lines.

We can end in situations where the current end line is the next start
line and the source line is show to the client twice. confusing users
what maps to what.

| With EndLine | 
| :------------: |
| <img width="892" height="486" alt="Screenshot 2026-02-05 at 21 37 08"
src="https://github.com/user-attachments/assets/f2fef592-5754-4168-bf93-2baba4742c5d"
/> |

| Without Endline |
| :---------------: |
| <img width="892" height="486" alt="Screenshot 2026-02-05 at 21 59 29"

    [17 lines not shown]
DeltaFile
+0-16lldb/tools/lldb-dap/Handler/DisassembleRequestHandler.cpp
+0-161 files

LLVM/project 85db121libc/src/__support wctype_utils.h CMakeLists.txt, libc/test/src/__support wctype_utils_test.cpp CMakeLists.txt

[libc][wctype] Implement internal UTF8 wctype classification functions (#174607)

Closes [#174604](https://github.com/llvm/llvm-project/issues/174604)

This patch implements the internal wide character classification
functions with Unicode support.
The ASCII paths which were not implemented are taken from
[ctype_utils.h](https://github.com/llvm/llvm-project/blob/main/libc/src/__support/ctype_utils.h)



The tests mainly cover the dispatch logic between ASCII and UTF8, the
UTF8 variants are already comprehensively tested in
[wctype_classification_utils_test.cpp](https://github.com/mleleszi/llvm-project/blob/main/libc/test/src/__support/wctype/wctype_classification_utils_test.cpp).
DeltaFile
+536-0libc/test/src/__support/wctype_utils_test.cpp
+357-145libc/src/__support/wctype_utils.h
+11-1libc/src/__support/CMakeLists.txt
+12-0libc/test/src/__support/CMakeLists.txt
+916-1464 files

GhostBSD/build 4c17317packages base

add missing firmware
DeltaFile
+2-1packages/base
+2-11 files

FreeBSD/src 87b2c01sys/conf options

sys/conf/options: remove improper full stops

Only keep them when used in a sentence.

Reviewed by: vexeduxr
Signed-off-by: Quentin Thébault <quentin.thebault at defenso.fr>
Sponsored by: Defenso
Closes: https://github.com/freebsd/freebsd-src/pull/2004
DeltaFile
+17-17sys/conf/options
+17-171 files

FreeBSD/src 9124181sys/kern subr_module.c

sys/subr_module: remove useless macro gates

These constants are always defined by sys/sys/linker.h.

Reviewed by: vexeduxr
Signed-off-by: Quentin Thébault <quentin.thebault at defenso.fr>
Sponsored by: Defenso
MFC after: 2 weeks
Closes: https://github.com/freebsd/freebsd-src/pull/2004
DeltaFile
+0-8sys/kern/subr_module.c
+0-81 files

FreeNAS/freenas dba061asrc/middlewared/middlewared/plugins/interface vlan.py bond.py

NAS-139647 / 26.0.0-BETA.1 / optimize interface/sync.py (#18157)

This makes a single call to "get_links" before we configure any
interfaces to reduce the number of netlink calls we make when
configuring these interfaces. The truenas_pynetif functions were written
with this in mind and so this just changes it so that we take advantage
of it. Instead of calling "get_links" (which enumerates all interfaces)
for every interface, it only calls it once and the cache is updated with
each interface after it has been configured.

While here, fix the socket type annotation.
DeltaFile
+11-5src/middlewared/middlewared/plugins/interface/vlan.py
+11-4src/middlewared/middlewared/plugins/interface/bond.py
+11-4src/middlewared/middlewared/plugins/interface/bridge.py
+7-3src/middlewared/middlewared/plugins/interface/sync.py
+40-164 files

LLVM/project b93d49dcompiler-rt/lib/builtins CMakeLists.txt

Merge branch 'users/statham-arm/arm-fp-cmake-properties' into users/statham-arm/arm-fp-double-support
DeltaFile
+13-0compiler-rt/lib/builtins/CMakeLists.txt
+13-01 files

LLVM/project 0287d78llvm/test/CodeGen/AMDGPU itofp.i128.ll, llvm/test/CodeGen/X86 expand-large-fp-optnone.ll

[ExpandIRInsts] Freeze input in itofp expansion (#180157)

We are introducing branches on the value, and branch on undef/poison is
UB, so the value needs to be frozen.
DeltaFile
+82-5llvm/test/Transforms/ExpandIRInsts/X86/expand-int-convert-small.ll
+30-23llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-ui129tofp.ll
+18-11llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll
+5-5llvm/test/CodeGen/X86/expand-large-fp-optnone.ll
+3-5llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+4-3llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-optnone.ll
+142-521 files not shown
+146-527 files

LLVM/project 4f90eb6llvm/lib/Analysis IVDescriptors.cpp, llvm/lib/Transforms/Vectorize VPlanConstruction.cpp

[LV] Support conditional scalar assignments of masked operations (#178862)

This patch extends the support added in #158088 to loops where the
assignment is non-speculatable (e.g. a conditional load or divide).

For example, the following loop can now be vectorized:

```
int simple_csa_int_load(
  int* a, int* b, int default_val, int N, int threshold)
{
  int result = default_val;
  for (int i = 0; i < N; ++i)
    if (a[i] > threshold)
      result = b[i];
  return result;
}
```


    [2 lines not shown]
DeltaFile
+1,144-0llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
+100-0llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-vplan.ll
+79-0llvm/unittests/Analysis/IVDescriptorsTest.cpp
+49-4llvm/lib/Analysis/IVDescriptors.cpp
+25-2llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+0-9llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
+1,397-151 files not shown
+1,398-167 files

LLVM/project fecc0bfclang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaAMDGPU.cpp

AMDGPU: Add llvm.amdgcn.s.wait.event intrinsic

Exactly match the s_wait_event instruction. For some reason we already
had this instruction used through llvm.amdgcn.s.wait.event.export.ready,
but that hardcodes a specific value. This should really be a bitmask that
can combine multiple wait types.

gfx11 -> gfx12 broke compatabilty in a weird way, by inverting the
interpretation  of the bit but also shifting the used bit by 1. Simplify
the selection of the old intrinsic by just using the magic number 2, which
should satisfy both cases.
DeltaFile
+42-9llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
+27-0clang/test/SemaOpenCL/builtins-amdgcn-s-wait-event.cl
+24-0clang/lib/Sema/SemaAMDGPU.cpp
+11-0llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+7-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+2-4llvm/lib/Target/AMDGPU/SOPInstructions.td
+113-131 files not shown
+114-137 files

LLVM/project d4638adllvm/lib/Transforms/Utils SimplifyLibCalls.cpp, llvm/test/Transforms/InstCombine double-float-shrink-1.ll sqrt.ll

InstCombine: Only propagate callsite attributes in sqrt->sqrtf (#180160)

This was propagating the callee's attributes instead of just the
callsite. It's illegal to set denormal_fpenv on a callsite. This
was also losing callsite attributes which may have been more useful;
there's no point in setting the callee's attributes on the callsite.
DeltaFile
+48-22llvm/test/Transforms/InstCombine/double-float-shrink-1.ll
+5-4llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
+3-3llvm/test/Transforms/InstCombine/sqrt.ll
+56-293 files

LLVM/project a815330llvm/test/CodeGen/AArch64 fp16_i16_intrinsic_scalar.ll

[AArch64][GlobalIsel] Update test checks
DeltaFile
+0-9llvm/test/CodeGen/AArch64/fp16_i16_intrinsic_scalar.ll
+0-91 files

LLVM/project dfcb0bellvm/lib/Target/AArch64 AArch64SVEInstrInfo.td AArch64ISelLowering.cpp

[AArch64] NFC: Replace CTTZ_ELTS predicate pattern with predicate. (#179909)

This also swaps the general predicate and source operand, to match other
nodes.

Follow-up from
https://github.com/llvm/llvm-project/pull/178674#discussion_r2767753614
DeltaFile
+28-28llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+8-12llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-1llvm/lib/Target/AArch64/AArch64InstrInfo.td
+38-413 files

LLVM/project 06f35e7llvm/lib/Target/AArch64/GISel AArch64RegisterBankInfo.cpp

[AArch64][GloballISel] Put result of fp16 -> s16 convert intrinsic on fpr

Previously, RegBankSelect would place the result of an fp16 -> s16 conversion intrinsic on a gpr. This would cause Instruction Selection to fail, as there are no 16-bit gprs.
Floating point convert intrinsics affected:
fcvtnu / fcvtns
fcvtau / fcvtas
fcvtmu / fcvtms
fcvtpu / fcvtps
DeltaFile
+7-6llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+7-61 files

OpenBSD/ports Uut1pNLeditors/vim Makefile distinfo, editors/vim/patches patch-runtime_autoload_tar_vim

   update to vim-9.1.2135
VersionDeltaFile
1.26+70-4editors/vim/pkg/PLIST
1.298+11-1editors/vim/Makefile
1.152+2-2editors/vim/distinfo
1.12+1-1editors/vim/patches/patch-runtime_autoload_tar_vim
+84-84 files

LLVM/project 25ccda7clang/include/clang/Basic BuiltinsAMDGPU.td

rebase
DeltaFile
+4-4clang/include/clang/Basic/BuiltinsAMDGPU.td
+4-41 files

NetBSD/pkgsrc Hi7B8gIdoc CHANGES-2026

   Updated archivers/unrar, security/ccid
VersionDeltaFile
1.926+3-1doc/CHANGES-2026
+3-11 files

NetBSD/pkgsrc sjupwSSsecurity/ccid distinfo Makefile

   ccid: updated to 1.7.1

   1.7.1 - 4 February 2026, Ludovic Rousseau
      - Add support of
       - ACS APG8201-B2
       - BUDGET E-ID BUD001
       - CHERRY Smart Board 1150
       - CryptnoxCR CryptnoxCR
       - Diebold Nixdorf PN7362au CCID
       - FT BioPass FIDO2 Pro
       - Nitrokey Nitrokey Passkey
      - Add SCARD_CTL_CODE(3601): USB path of the reader
      - Some other minor improvements
VersionDeltaFile
1.31+4-4security/ccid/distinfo
1.52+2-2security/ccid/Makefile
+6-62 files

NetBSD/src Dgh7rLosbin/gpt main.c

   Allow scaling of the media size (-m arg)

   Note that we cannot use gpt_size_get() as that needs gpt->secsz
   to have been set already (ie: can only be used after gpt_open)
   and treats unscaled numbers as multiples of sectors, whereas the
   -m arg has always been a byte size.

   For gpt_human_get() or simply using dehumanize_number() we
   would need to handle 's' and 'b' suffixes by hand anyway, so it
   is simpler to simply to the whole thing longhand in this case.

   This also allows (with some hackery) for the media size to be
   set as some number of sectors, when we do not yet know the
   sector size - it gets corrected later once the sector size has
   been determined.
VersionDeltaFile
1.16+89-6sbin/gpt/main.c
+89-61 files

LLVM/project 6824db4llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir

[AMDGPU] Set MOThreadPrivate on memory accesses for spills (#179414)

Mark the memory operand of spill load/stores as MOThreadPrivate, so that
these loads and stores are emitted with `nv` set.

The reason is that scratch memory used by spills will never be shared by
another thread. It's purely thread local and thus a good fit for the
`nv` bit, which is controlled by the MOThreadPrivate flag.
DeltaFile
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+1,260-1,260llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+902-902llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+180-180llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
+166-167llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+12,350-12,35142 files not shown
+13,185-13,18448 files

NetBSD/src 0MvCFAqsbin/gpt gpt.c

   Ensure sizes are a multiple of the sector size.

   In gpt_size_get() ensure that the size returned is a multiple
   of the sector size.   This is automatic for unscaled numbers
   (treated as multiples of the sector size) but in other cases
   it is not automatic.   Note that even nK is not guartamteed to
   be a multiple of the sector size if that happens to be 4K and
   n is not a multiple of 4.
VersionDeltaFile
1.98+12-1sbin/gpt/gpt.c
+12-11 files

LLVM/project 3f4d94fllvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/AArch64 select-shuffle.ll

[VectorCombine] foldShuffleOfBinops - support multiple uses of shuffled binops (#179429)

Resolves #173035
DeltaFile
+52-0llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
+28-9llvm/test/Transforms/VectorCombine/X86/shuffle-of-cmps.ll
+23-9llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+2-3llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
+105-214 files

LLVM/project 33a2c3ellvm/lib/Transforms/Vectorize VPlanPatternMatch.h VPlanPredicator.cpp, llvm/test/Transforms/LoopVectorize uniform-blend.ll unused-blend-mask-for-first-operand.ll

[VPlan] Ignore poison incoming values when creating blend (#180005)

We have an optimization in VPPredicator when creating blends where if
all the incoming values are the same, we just return that value.

This extends it to handle cases like "phi [%x, %x, poison, %x]" by
ignoring poison values.

This is split off from #176143 to prevent regressions when maintaining
SSA by adding PHIs with a poison incoming value.
DeltaFile
+58-16llvm/test/Transforms/LoopVectorize/uniform-blend.ll
+6-14llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll
+10-0llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
+2-4llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
+3-1llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
+79-355 files

NetBSD/pkgsrc yQT2sXgarchivers/unrar distinfo Makefile.common

   unrar: updated to 7.2.4

   7.2.4
   Unknown changes
VersionDeltaFile
1.116+4-4archivers/unrar/distinfo
1.68+2-2archivers/unrar/Makefile.common
+6-62 files