OPNSense/core e174540src/etc/inc/plugins.inc.d radvd.inc, src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms dialogEntry.xml

radvd: Add Base6Interface constructor (#9615)

DeltaFile
+14-4src/etc/inc/plugins.inc.d/radvd.inc
+11-0src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.php
+10-0src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms/dialogEntry.xml
+1-0src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.xml
+36-44 files

OPNSense/core ac82437src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms dialogEntry.xml, src/opnsense/mvc/app/models/OPNsense/Radvd Radvd.php

Tighten scope via validation, Base6Interface shall not be the same as interface.
DeltaFile
+11-0src/opnsense/mvc/app/models/OPNsense/Radvd/Radvd.php
+1-1src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms/dialogEntry.xml
+12-12 files

LLVM/project 56398ed.github/workflows ids-check.yml

ids-check: Disable workflow on push (#175752)

The workflow is only meant to run on PRs.
DeltaFile
+0-4.github/workflows/ids-check.yml
+0-41 files

LLVM/project c745e9blldb/packages/Python/lldbsuite/test lldbtest.py, lldb/packages/Python/lldbsuite/test/tools/lldb-dap dap_server.py

[lldb-dap] Add testcases for stdio redirection on different console types. (#175048)

There are some bugs when launching in terminal with args and stdio
redirection.

- lldb-dap `--stdio` args is passed to the debuggee (should we change
this to use `--` to separate debuggee args from lldb-dap args, similar
to how we handle the `--client` args? ).

#### It also changes the behaviour of stdio redirection.
If a redirection is not specified, it uses to lldb default value. e.g.
```jsonc
"stdio": ["./stdin"]` 
// now becomes 
"stdio", ["./stdio", "./default_stdout", "./default_stderr"]
// instead of 
"stdio", ["./stdin", "./stdin", "./stdin"]
// took quite some time to figure out where my output is going to.
```

    [5 lines not shown]
DeltaFile
+356-0lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io.py
+15-13lldb/tools/lldb-dap/Handler/RequestHandler.cpp
+24-0lldb/test/API/tools/lldb-dap/launch/io/main.cpp
+11-7lldb/tools/lldb-dap/JSONUtils.cpp
+12-3lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
+12-1lldb/packages/Python/lldbsuite/test/lldbtest.py
+430-245 files not shown
+448-3211 files

LLVM/project aa0ba7eclang/docs ReleaseNotes.rst, clang/include/clang/Basic DiagnosticDriverKinds.td

[LoongArch][Driver] Allow `-gsplit-dwarf` and `-mrelax` to be used together (#175727)

Benefit from https://github.com/llvm/llvm-project/pull/166597 and
https://github.com/llvm/llvm-project/pull/164813, DWARF fission is now
compatible with linker relaxation.

Similar to RISC-V, this commit allows `-gsplit-dwarf` and `-mrelax` to
be used together.

A new test `relax_dwo_ranges.ll` same as RISC-V is also added.
DeltaFile
+206-0llvm/test/DebugInfo/LoongArch/relax_dwo_ranges.ll
+0-12clang/test/Driver/loongarch-relax-features.c
+2-9clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
+3-0clang/docs/ReleaseNotes.rst
+0-3clang/include/clang/Basic/DiagnosticDriverKinds.td
+3-0llvm/docs/ReleaseNotes.md
+214-246 files

FreeNAS/freenas b2f42e0src/middlewared/middlewared/plugins sysdataset.py, src/middlewared/middlewared/plugins/apps upgrade.py

Make all `zfs.resource` calls type-safe
DeltaFile
+29-47src/middlewared/middlewared/plugins/pool_/snapshot.py
+13-17src/middlewared/middlewared/plugins/apps/upgrade.py
+11-18src/middlewared/middlewared/plugins/zfs/snapshot_crud.py
+14-14src/middlewared/middlewared/plugins/sysdataset.py
+12-16src/middlewared/middlewared/plugins/docker/migrate.py
+11-12src/middlewared/middlewared/plugins/vm/clone.py
+90-12438 files not shown
+246-26144 files

LLVM/project c8843dcllvm/test/CodeGen/X86 masked_store.ll masked_load.ll

[X86] Add test coverage showing AVX1/2 poor handling of scalar -> bool vectors for masked load/store (#175746)

Test coverage to help #175385
DeltaFile
+3,375-2,202llvm/test/CodeGen/X86/masked_store.ll
+3,101-2,189llvm/test/CodeGen/X86/masked_load.ll
+6,476-4,3912 files

LLVM/project 7c40b0eutils/bazel/llvm-project-overlay/mlir BUILD.bazel

Fix Bazel build for 1562161 (#175751)

Co-authored-by: Pranav Kant <prka at google.com>
DeltaFile
+17-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+17-01 files

LLVM/project b5f98fbclang/lib/CIR/Dialect/IR CIRDialect.cpp, mlir/include/mlir/Interfaces ControlFlowInterfaces.td ControlFlowInterfaces.h

[mlir][Interfaces] Simplify and align `RegionSuccessor` API
DeltaFile
+36-27mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
+9-15clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+11-13mlir/lib/Dialect/SCF/IR/SCF.cpp
+10-6mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+5-5mlir/test/lib/Dialect/Test/TestOpDefs.cpp
+5-5mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+76-7116 files not shown
+108-10522 files

LLVM/project c5c45c2llvm/docs AMDGPUUsage.rst

[AMDGPU][Docs] Document amdgpu-expand-waitcnt-profiling attribute
DeltaFile
+6-0llvm/docs/AMDGPUUsage.rst
+6-01 files

LLVM/project 6e04d71flang/test/Lower array-expression-slice-1.f90 array-expression-subscript.f90

[flang][NFC] Converted five tests from old lowering to new lowering (part 5) (#175008)

Tests converted in Lower: array-elemental-subroutines.f90,
array-expression-slice-1.f90, array-expression-slice-2.f90,
array-expression-subscript.f90, array-substring.f90
DeltaFile
+41-363flang/test/Lower/array-expression-slice-1.f90
+99-149flang/test/Lower/array-expression-subscript.f90
+20-39flang/test/Lower/array-substring.f90
+13-27flang/test/Lower/array-elemental-subroutines.f90
+23-8flang/test/Lower/array-expression-slice-2.f90
+196-5865 files

LLVM/project 25b4d1eclang/lib/AST/ByteCode InterpBuiltin.cpp Compiler.cpp, clang/test/AST/ByteCode builtins.cpp

[clang][bytecode] Don't evaluate builtin_assume argument (#175740)

This is what the current interpreter does.
DeltaFile
+8-3clang/test/AST/ByteCode/builtins.cpp
+3-2clang/lib/AST/ByteCode/InterpBuiltin.cpp
+3-1clang/test/Parser/MicrosoftExtensions.c
+4-0clang/lib/AST/ByteCode/Compiler.cpp
+18-64 files

OPNSense/core e28c113src/etc config.xml.sample

system: adjust dhcpv6 range with isc default
DeltaFile
+2-2src/etc/config.xml.sample
+2-21 files

OPNSense/core c5ce6b6src/etc config.xml.sample, src/etc/inc interfaces.inc

interfaces: introduce idassoc6 mode #9155

We're adding a bit of technical debt here for the simple reason
to decouple the track6 mode from automatic radvd and dhcpv6 runs.

Specifically avoid the "dhcpd6track6allowoverride" flag in this
mode but keep the data the same otherwise for interoperability.
DeltaFile
+140-57src/www/interfaces.php
+4-2src/etc/inc/interfaces.inc
+2-2src/opnsense/scripts/shell/setaddr.php
+3-0src/opnsense/scripts/shell/banner.php
+1-1src/opnsense/mvc/tests/app/models/OPNsense/ACL/AclConfig/config.xml
+1-1src/etc/config.xml.sample
+151-631 files not shown
+152-647 files

OPNSense/core d3672a3src/etc/inc interfaces.inc, src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms dialogEntry.xml

Merge branch 'master' into dnsmasq-ipv6-defaults
DeltaFile
+0-613src/www/services_router_advertisements.php
+0-441src/www/system_advanced_network.php
+216-0src/opnsense/mvc/app/controllers/OPNsense/Radvd/forms/dialogEntry.xml
+0-205src/opnsense/mvc/app/library/OPNsense/OpenVPN/TheGreenBow.php
+147-47src/etc/inc/interfaces.inc
+194-0src/opnsense/mvc/app/models/OPNsense/Radvd/Migrations/M1_0_0.php
+557-1,30699 files not shown
+2,510-1,724105 files

LLVM/project 762512flldb/unittests/Symbol TestTypeSystemClang.cpp

[lldb][tests] Add signed-ness tests for _BitInt

We have special logic for creating `_BitInt` types by name. This patch adds tests to ensure we create the types with the correct signed-ness.
DeltaFile
+10-0lldb/unittests/Symbol/TestTypeSystemClang.cpp
+10-01 files

OPNSense/core fe03fe3src/etc/inc interfaces.inc

interface: POC for multi-dhcp6c support

I'm not entirely sure why we settled for a single deamon of
dhcp6c back in the day, but there are certianly downsides to
it and I don't see something that wasn't fixed in the meantime
that makes this not work.

At the moment this splits off dhcp6c only but we need to
change the daemon's print a bit to avoid complaining about
"other" devices since the situation to ignore a non-listening
interface is normal and not "ignoring" something obvious as
the INFO log message suggests.

rtsold still needs to be split to allow for HUP reload of
a single interface instead of forcing a restart of all
DHCPv6 WAN clients at the same time.
DeltaFile
+9-23src/etc/inc/interfaces.inc
+9-231 files

OPNSense/core 390a12esrc/etc/inc interfaces.inc console.inc, src/opnsense/mvc/tests/app/models/OPNsense/ACL/AclConfig config.xml

interfaces: introduce idassoc6 mode #9155

We're adding a bit of technical debt here for the simple reason
to decouple the track6 mode from automatic radvd and dhcpv6 runs.

Specifically avoid the "dhcpd6track6allowoverride" flag in this
mode but keep the data the same otherwise for interoperability.
DeltaFile
+140-57src/www/interfaces.php
+4-2src/etc/inc/interfaces.inc
+2-2src/opnsense/scripts/shell/setaddr.php
+3-0src/opnsense/scripts/shell/banner.php
+1-1src/etc/inc/console.inc
+1-1src/opnsense/mvc/tests/app/models/OPNsense/ACL/AclConfig/config.xml
+151-631 files not shown
+152-647 files

LLVM/project 6aaa7fdllvm/lib/Target/AMDGPU GCNSchedStrategy.cpp GCNSchedStrategy.h, llvm/test/CodeGen/AMDGPU machine-scheduler-rematerialization-scoring.mir machine-scheduler-sink-trivial-remats-attr.mir

[AMDGPU][Scheduler] Scoring system for rematerializations (#175050)

This is a significant refactoring of the scheduler's rematerialization
stage meant to improve rematerialization capabilities and lay strong
foundations for future improvements.

As before, the stage identifies scheduling regions in which RP must be
reduced (so-called "target regions"), then rematerializes registers to
try and achieve the desired reduction. All regions affected by
rematerializations are re-scheduled, and, if the MIR is deemed worse
than before, rematerializations are rolled back to leave the MIR in its
pre-stage state.

The core contribution is a scoring system to estimate the benefit of
each rematerialization candidate. This score favors rematerializing
candidates which, in order, would

1. (if the function is spilling) reduce RP in highest-frequency target
regions,

    [16 lines not shown]
DeltaFile
+502-288llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+523-0llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
+194-194llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
+242-35llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
+208-50llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+5-5llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
+1,674-5721 files not shown
+1,675-5737 files

LLVM/project 98925a0lldb/source/Plugins/Language/CPlusPlus LibStdcppUniquePointer.cpp

[lldb] Fix crash in lldb when unique pointer is not valid (#175737)

check if the internal pointer is not null.
DeltaFile
+4-2lldb/source/Plugins/Language/CPlusPlus/LibStdcppUniquePointer.cpp
+4-21 files

LLVM/project bf260afllvm/test/tools/llvm-exegesis/AArch64 setReg_init_check.s

[llvm-exegesis] Fix non-existent lit substitution in setReg_init_check.s (#175547)

According to [1] there is no '%d' substitution. Not sure if it was
intended as a substitution but it's confusing, so I've updated the test
to dump the object file to '%t.o', i.e.:

  <build_dir>/test/tools/llvm-exegesis/AArch64/Output/setReg_init_check.s.tmp.o

[1] https://llvm.org/docs/CommandGuide/lit.html#substitutions
DeltaFile
+36-36llvm/test/tools/llvm-exegesis/AArch64/setReg_init_check.s
+36-361 files

FreeBSD/ports cd3f4e4net-im/py-zapzap distinfo Makefile

net-im/py-zapzap: Update to 6.2.6

ChangeLog:      https://github.com/rafatosta/zapzap/releases/tag/6.2.6
Reported by:    Rafael Tosta <notifications at github.com>
DeltaFile
+3-3net-im/py-zapzap/distinfo
+1-1net-im/py-zapzap/Makefile
+4-42 files

LLVM/project 3d418e5.github/workflows ids-check.yml

ids-check: Specify path input for `changed-files` (#175723)

This was causing issues when running the workflow.

https://github.com/llvm/llvm-project/actions/runs/20948190719/job/60195336123
DeltaFile
+1-0.github/workflows/ids-check.yml
+1-01 files

LLVM/project 75006cdllvm/test/MC/AMDGPU gfx12_asm_vop3-fake16.s gfx11_asm_vop3-fake16.s

[AMDGPU] Generate checks for *_asm_vop3-fake16.s
DeltaFile
+2,555-2,554llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+2,196-2,195llvm/test/MC/AMDGPU/gfx11_asm_vop3-fake16.s
+4,751-4,7492 files

NetBSD/pkgsrc-wip 8127a08flatbuffers PLIST Makefile

flatbuffers: Upgrade to 25.12.19
DeltaFile
+43-0flatbuffers/PLIST
+21-0flatbuffers/Makefile
+12-0flatbuffers/buildlink3.mk
+5-0flatbuffers/distinfo
+4-0flatbuffers/DESCR
+3-0flatbuffers/COMMIT_MSG
+88-06 files

LLVM/project 5cbd2f1llvm/test/CodeGen/X86 masked_gather.ll

[X86] masked_gather.ll - add mask from scalar value and test coverage for "fast-gather" avx2 targets (#175736)

Test coverage to help #175385
DeltaFile
+1,703-815llvm/test/CodeGen/X86/masked_gather.ll
+1,703-8151 files

LLVM/project 055174allvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPUGlobalISelUtils.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fpext.ll unmerge-sgpr-s16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES

Move G_UNMERGE_VALUES handling to AMDGPURegBankLegalizeRules.cpp.
Fix sgpr S16 unmerge by lowering using shift and using S32.
Previously sgpr S16 unmerge was selected using _lo16 and _hi16 subreg
indexes which are exclusive to vgpr register classes.
For remaing cases we do trivial mapping, assigns same reg bank
to all operands, vgpr or sgpr.
DeltaFile
+47-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+13-27llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
+36-0llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
+18-0llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+10-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+6-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+130-282 files not shown
+137-318 files

LLVM/project 8246257llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/AMDGPU combine-scalar-selects.ll

Reapply "[VectorCombine] Fold scalar selects from bitcast into vector select" (#174762)

Reapply https://github.com/llvm/llvm-project/pull/173990 with fixes for
post-commit review comments.

---------

Co-authored-by: padivedi <padivedi at amd.com>
Co-authored-by: Christudasan Devadasan <christudasan.devadasan at amd.com>
DeltaFile
+1,874-0llvm/test/Transforms/VectorCombine/AMDGPU/combine-scalar-selects.ll
+130-0llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+2,004-02 files

NetBSD/pkgsrc-wip cb84a7erust191 Makefile

rust191: whitespace cleanup
DeltaFile
+2-2rust191/Makefile
+2-21 files

NetBSD/pkgsrc-wip eef8d36rust191 distinfo, rust191/patches patch-vendor_libc-0.2.168_src_unix_bsd_netbsdlike_netbsd_mod.rs patch-libc-0.2.168_src_unix_bsd_netbsdlike_netbsd_mod.rs

rust191: rename patch per pkglint
DeltaFile
+15-0rust191/patches/patch-vendor_libc-0.2.168_src_unix_bsd_netbsdlike_netbsd_mod.rs
+0-15rust191/patches/patch-libc-0.2.168_src_unix_bsd_netbsdlike_netbsd_mod.rs
+1-1rust191/distinfo
+16-163 files