LLVM/project 49d387c — llvm/lib/Transforms/Scalar InferAddressSpaces.cpp, llvm/test/Transforms/InferAddressSpaces/AMDGPU constexpr-addrspacecast.ll

[InferAddressSpaces] Treat addrspacecast constant expressions from flat as roots

The pass uses the pointer operand of an `addrspacecast` instruction as a root,
but it misses the same cast folded into a constant expression unless the
constant is itself in a root position, such as a load or store pointer. So a
round trip from LDS through flat back to LDS is not folded when it is, for
example, a call operand.

This PR treats such casts in any operand as roots, including nested ones. Other
constant expressions only produce another flat pointer.

Fixes LCOMPILER-3204.

This PR was assisted by AI but I reviewed all the changes.
DeltaFile
+71-0llvm/test/Transforms/InferAddressSpaces/AMDGPU/constexpr-addrspacecast.ll
+24-0llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
+95-02 files

FreeBSD/ports 16cc233 — www/rubygem-addressable28 Makefile

www/rubygem-addressable28: Mark DEPRECATED

PR:             299358
Approved by:    ruby (maintainer, timeout 2 weeks)
Approved by:    osa, fluffy (mentors, implicit)
MFH:            2026Q4

(cherry picked from commit e20b1008473dd32c5924aa78b9a9e76aee3c5878)
DeltaFile
+4-0www/rubygem-addressable28/Makefile
+4-01 files

FreeBSD/ports e20b100 — www/rubygem-addressable28 Makefile

www/rubygem-addressable28: Mark DEPRECATED

PR:             299358
Approved by:    ruby (maintainer, timeout 2 weeks)
Approved by:    osa, fluffy (mentors, implicit)
MFH:            2026Q4
DeltaFile
+4-0www/rubygem-addressable28/Makefile
+4-01 files

LLVM/project fa6280e — llvm/lib/Target/Hexagon HexagonQFPOptimizer.cpp

Hexagon: Remove dead kill flag maintenance in HexagonQFPOptimizer

The operands are virtual registers, which can no longer carry kill
flags.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+9-28llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp
+9-281 files

LLVM/project 8e8d827 — llvm/lib/Target/RISCV RISCVVectorPeephole.cpp, llvm/test/CodeGen/RISCV/rvv vmand-to-masked-compare.mir vmerge-peephole.mir

RISCV: Fix ensureDominates crashes on operands without a vreg def (#241034)

ensureDominates used an unchecked getVRegDef on every register
operand. This crashed on physical register uses or undef vregs. Also
fix dropping an incoming undef flag which would fail the verifier.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+49-0llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
+23-0llvm/test/CodeGen/RISCV/rvv/vmand-to-masked-compare.mir
+8-1llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+80-13 files

LLVM/project d5cbc17 — clang/include/clang/AST TypeBase.h, clang/include/clang/Basic Attr.td AttrDocs.td

Revert "[RISCV][clang] Support XSfmm ABI attributes (#206260)" (#241096)

This reverts commit 09dcbfb936c629a1285fb04fff9974456f041804. Revert for
now and investigate why compile time increase.
DeltaFile
+0-146clang/test/Sema/sifive-xsfmm-func-attr.c
+0-105clang/lib/Sema/SemaRISCV.cpp
+7-98clang/include/clang/AST/TypeBase.h
+0-102clang/lib/Sema/SemaType.cpp
+0-67clang/include/clang/Basic/AttrDocs.td
+0-35clang/include/clang/Basic/Attr.td
+7-55319 files not shown
+9-75125 files

LLVM/project 22c2948 — llvm/lib/Transforms/IPO Attributor.cpp

Attributor: Decide which instructions access memory in the opcode switch

initializeInformationCache already switches over the opcode of every
instruction, and then called mayReadOrWriteMemory out of line for each
one. Decide in the switch instead, where only calls need to check their
memory effects.

Instruction counts (callgrind) with other pending attributor-light
changes applied: attributor-light sqlite3 -0.79%, kimwitu++ k -0.32%,
SPASS cnf -0.31%, consumer-typeset z08 -8.59%; the full attributor
-0.02% to -0.08%.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+22-7llvm/lib/Transforms/IPO/Attributor.cpp
+22-71 files

LLVM/project 3731f41 — clang/lib/Driver/ToolChains Linux.cpp, clang/test/Driver linux-ld.c

[Clang][Driver][MIPS] Fix musl dynamic linker path (#240826)

Clang's Linux driver selects an incorrect dynamic linker for several
MIPS musl configurations.

- select the correct musl dynamic linker for MIPS targets
- add driver tests

Closes: #240798

Signed-off-by: Pepper Gray <hello at peppergray.xyz>
DeltaFile
+44-0clang/test/Driver/linux-ld.c
+23-0clang/lib/Driver/ToolChains/Linux.cpp
+67-02 files

LLVM/project d5486a2 — llvm/include/llvm/Transforms/IPO Attributor.h, llvm/lib/Transforms/IPO Attributor.cpp

Attributor: Make IRPosition::verify inline without expensive checks (#241087)

IRPosition::verify only checks anything with EXPENSIVE_CHECKS, but
every IRPosition constructor still called it out of line. This
prevented keeping the position in registers plus the cost of the call.

Instruction counts (callgrind) over 68 llvm-test-suite TUs, with other
pending attributor-light changes applied, median:
attributor-light -0.71% (-0.45%), attributor-light-cgscc -0.31%
(-0.38%), attributor -0.35% (-0.45%).

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+2-2llvm/lib/Transforms/IPO/Attributor.cpp
+4-0llvm/include/llvm/Transforms/IPO/Attributor.h
+6-22 files

LLVM/project 750a60b — llvm/include/llvm/IR RuntimeLibcalls.td, llvm/test/Transforms/Util/DeclareRuntimeLibcalls divmod.ll

RuntimeLibcalls: Annotate divrem libcall remainder out arguments (#240731)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+16-5llvm/include/llvm/IR/RuntimeLibcalls.td
+3-2llvm/test/Transforms/Util/DeclareRuntimeLibcalls/divmod.ll
+19-72 files

OPNSense/core 5a45bc9 — src/etc/inc system.inc

system: bump Vietnamese to full language as it is 100% done

(cherry picked from commit 0d28abe198b97e0c700f0083590569b5a87f826c)
DeltaFile
+1-1src/etc/inc/system.inc
+1-11 files

OPNSense/core 0d28abe — src/etc/inc system.inc

system: bump Vietnamese to full language as it is 100% done
DeltaFile
+1-1src/etc/inc/system.inc
+1-11 files

LLVM/project 8461e2a — lldb/include/lldb/Core Module.h, lldb/include/lldb/Symbol ObjectFile.h

[lldb] Don't cache symtabs for memory modules w/ corefile (#237050)

In https://github.com/llvm/llvm-project/pull/229305 I added a new
setting, `symbols.enable-lldb-index-cache-memory-modules` which creates
a DataFileCache symtab file for memory-read modules. Reading the symbol
table out of memory is a serious performance issue, and caching those
tables on the debug host is worth doing by default.

This is not the correct tradeoff if we are doing corefile debugging,
where reading memory is cheap. In that case we need to ignore the
`symbols.enable-lldb-index-cache-memory-modules` setting and not create
the symtabs, unless the user has set
`symbols.enable-lldb-index-cache` themselves.

This patchset is a little tricky because the layers where we can make
this judgement (DynamicLoader or Process) is pretty far away from the
place where we create the Symtab, `ObjectFile::GetSymtab` and there is
another scenario I want to override the default for in the future that
is only knowable to the DynamicLoader (if the DynamicLoader believes ALL

    [28 lines not shown]
DeltaFile
+110-0lldb/test/API/functionalities/module_cache/corefile_memory_module/TestModuleCacheCorefileMemoryModule.py
+24-7lldb/include/lldb/Core/Module.h
+17-2lldb/source/Symbol/Symtab.cpp
+19-0lldb/test/API/functionalities/module_cache/corefile_memory_module/main.cpp
+14-0lldb/include/lldb/Symbol/ObjectFile.h
+9-4lldb/source/Core/Module.cpp
+193-134 files not shown
+209-1810 files

LLVM/project 7fcc520 — llvm/include/llvm/Analysis VectorUtils.h, llvm/lib/Analysis VectorUtils.cpp

[VectorUtils] Preserve cache-hint metadata
DeltaFile
+84-0llvm/unittests/Analysis/VectorUtilsTest.cpp
+53-0llvm/lib/Analysis/VectorUtils.cpp
+9-4llvm/test/Transforms/SLPVectorizer/X86/cache-hint.ll
+9-4llvm/test/Transforms/LoadStoreVectorizer/NVPTX/cache-hint.ll
+5-0llvm/include/llvm/Analysis/VectorUtils.h
+160-85 files

LLVM/project 9217344 — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/asm-rm-4-regallocfast-fold' into users/void/asm-rm-5-prefer-reg
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project 9f45bd2 — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/asm-rm-3-direct-mem-output-error' into users/void/asm-rm-4-regallocfast-fold
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project 084b057 — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/asm-rm-2f-peephole-asm-load-fold' into users/void/asm-rm-3-direct-mem-output-error
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project ca8bcc9 — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/asm-rm-2e-fold-asm-memoperands' into users/void/asm-rm-2f-peephole-asm-load-fold
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project 9df30c3 — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/asm-rm-2d-prefer-spilling-foldable' into users/void/asm-rm-2e-fold-asm-memoperands
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project 3444b53 — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/asm-rm-2c-fold-subreg-offset' into users/void/asm-rm-2d-prefer-spilling-foldable
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project 2e6295e — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/asm-rm-2b-fold-all-reg-operands' into users/void/asm-rm-2c-fold-subreg-offset
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project c8c28ac — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/asm-rm-2-fold-tied-operands' into users/void/asm-rm-2b-fold-all-reg-operands
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project 504a79b — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/mir-inline-asm-func-kind' into users/void/asm-rm-2-fold-tied-operands
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project b8dcdda — llvm/include/llvm/IR InlineAsm.h

Merge branch 'users/void/mir-inline-asm-operand-count' into users/void/mir-inline-asm-func-kind
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

LLVM/project cd7990e — llvm/lib/Target/ARM ARMRegisterInfo.td

ARM: Mark GPRsp as not allocatable (#240935)

This only contains SP which is always reserved.
DeltaFile
+1-0llvm/lib/Target/ARM/ARMRegisterInfo.td
+1-01 files

LLVM/project af26319 — llvm/include/llvm/IR InlineAsm.h

Use maskTrailingOnes() for the largest operand count

There's nothing in <bit> that builds a mask, but maskTrailingOnes() does,
and it's what Bitfield uses for the field's own mask. Unlike a shift or a
rotate, it's also right for a field as wide as an unsigned.

Assisted-by: Claude Opus 5.5
DeltaFile
+2-1llvm/include/llvm/IR/InlineAsm.h
+2-11 files

OpenBSD/src d1xHnTH — sys/dev/pci/drm/amd/amdgpu amdgpu.h amdgpu_amdkfd.h, sys/dev/pci/drm/amd/amdkfd kfd_chardev.c

   drm/amdkfd: correct vram_available calculation

   From Zhen Han
   58d07ddaa5f33052a29cb26ca226da281e5f3475 in linux-6.18.y/6.18.63
   9131cc85d0dedd8ba4cae60dbe5985d081551f30 in mainline linux
VersionDeltaFile
1.30+55-39sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
1.31+33-0sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
1.20+19-1sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.h
1.34+10-2sys/dev/pci/drm/amd/amdkfd/kfd_chardev.c
1.32+10-1sys/dev/pci/drm/amd/amdgpu/amdgpu.h
+127-435 files

FreeBSD/ports e1d11ce — devel/py-ty Makefile.crates Makefile, devel/py-ty/files patch-cargo-crates_mio-1.0.4_src_sys_unix_selector_kqueue.rs

devel/py-ty: Update to 0.0.100

Changelog: https://github.com/astral-sh/ty/blob/0.0.100/CHANGELOG.md

Reported by:    portscout
DeltaFile
+0-10devel/py-ty/files/patch-cargo-crates_mio-1.0.4_src_sys_unix_selector_kqueue.rs
+5-5devel/py-ty/distinfo
+1-1devel/py-ty/Makefile.crates
+1-1devel/py-ty/Makefile
+7-174 files

LLVM/project ddea95c — llvm/include/llvm/Analysis VectorUtils.h, llvm/lib/Analysis VectorUtils.cpp

[VectorUtils] Preserve cache-hint metadata
DeltaFile
+84-0llvm/unittests/Analysis/VectorUtilsTest.cpp
+54-0llvm/lib/Analysis/VectorUtils.cpp
+9-4llvm/test/Transforms/SLPVectorizer/X86/cache-hint.ll
+9-4llvm/test/Transforms/LoadStoreVectorizer/NVPTX/cache-hint.ll
+5-0llvm/include/llvm/Analysis/VectorUtils.h
+161-85 files

LLVM/project 18d58e0 — llvm/test/Transforms/LoadStoreVectorizer/NVPTX cache-hint.ll, llvm/test/Transforms/SLPVectorizer/X86 cache-hint.ll

[VectorUtils] Add cache-hint tests
DeltaFile
+297-0llvm/test/Transforms/LoadStoreVectorizer/NVPTX/cache-hint.ll
+229-0llvm/test/Transforms/SLPVectorizer/X86/cache-hint.ll
+526-02 files