[libc] Implement lchown in unistd (#230851)
Implement the standard POSIX function `lchown(const char *path, uid_t
owner, gid_t group)` in `<unistd.h>`.
Fixes #230837.
[ids-check] Print diff before updating issue (#230315)
This way if the script errors out trying to update the issue, the diff
is still logged to stdout.
[InstCombine] Combine ((ext(A) * ext(B)) >> N) -> ext(mulh(A, B)). (#224311)
The source values must be equally extended to double their width.
The result is sign/zero-extended for an arithmetic/logical shift.
This is a simplified version of DAGCombiner's combineShiftToMULH.
InjectTLIMappings: skip TLI mapping injection for variadic calls. (#202016)
Declarations such as `int pow();` produce variadic libcalls. When
compiling with -fveclib, inject-tli-mappings can reach
addVariantDeclaration(), which asserts that vararg function types are
unsupported. Return early when the call's function type is variadic.
Fixes #174172
[SLP]Use the emitted scalar type for gather slice size
Minbitwidth narrowed gathers were sliced using the original scalar type,
so the mask parts did not match the emitted vector and createShuffle
crashed.
Fixes #231076
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/231142
[libunwind][MIPS] Add o32 single-float support (#218994)
On FPUs that only support single precision, such as the PSP's Allegrex,
libunwind fails to assemble for o32 because the save/restore code uses
sdc1/ldc1. Save and restore all 32 FPRs with swc1/lwc1 instead, keeping
each register in an 8-byte slot so the context layout is the same for
every o32 FPU configuration.
Check __mips_single_float before __mips_fpr: GCC defines __mips_fpr as
32 for single-float targets and Clang defines it as 0, but both define
__mips_single_float.
In Registers.hpp, treat each FPR as an independent 32-bit value when
__mips_single_float is set, rather than pairing even/odd registers.
Add a compile-only test that checks the size of the o32 context.
[IR] Return poison instead of undef for poison shufflevector elements (#225598)
Poison shufflevector mask elements should result in a poison element
during constant folding.
[DAG] FoldConstantArithmetic - add support for ISD::MULO/ADDO/SUBO constant folding (#228877)
Add a `SDVTList` overload of `SelectionDAG::FoldConstantArithmetic` so
nodes with multiple results can be constant folded, returning the folded
results as a `MERGE_VALUES` node.
Use it to constant fold `ISD::[SU]ADDO`, `ISD::[SU]SUBO` and
`ISD::[SU]MULO` with scalar or splat constant operands (opaque constants
are not folded):
- `getNode()` for multiple result nodes now calls
`FoldConstantArithmetic`, so these nodes are folded on creation.
- `visitMULO` uses it instead of its own inline fold (resolving the
existing TODO), and `visitADDO` / `visitSUBO` use it as well.
The overflow result is created with `getBoolConstant(Overflow, DL,
CarryVT, VT)`, using the operand type for the boolean contents, as
suggested in #224713.
Fixes #224943
[DebugInfo] Accept DW_OP_xderef_size and DW_OP_lit1..DW_OP_lit31. (#227839)
- Accept DW_OP_lit0..DW_OP_lit31 and DW_OP_xderef_size in
DIExpression::isValid and DwarfExpression::addExpression.
- Treat DW_OP_lit<n> as DW_OP_constu n in DIExpression::isConstant; add
getConstantValue() for callers.
- extractAddressClass: match the trailing address space sequence (it
previously matched at the front but stripped the tail), accept the
DW_OP_lit<n> and DW_OP_xderef_size forms, and return multi-location
expressions unchanged rather than as a spurious match with an
uninitialized address class.
- Reject DW_OP_(x)deref_size operands that do not fit in a byte instead
of truncating them, and stop describeLoadedValue and
PrologEpilogInserter from producing them.
- PrologEpilogInserter: drop implicit locations of stack objects larger
than an address instead of emitting an invalid DW_OP_deref_size.
- Document the new operators in SourceLevelDebugging.
Assisted-by: LLM
[LV] Rewrite Scalable preference computation (NFCI)
The computation is now in a single place, making precedence easier to
understand. The change is not completely NFC, but it is NFC where it
matters to keep the computation simple.
Previously, -force-vector-width="vscale x ..." would always override
-scalable-vectorization and yield Scalable=SK_AlwaysScalable. Now,
-scalable-vectorization always take precedence over -force-vector-width
to keep things simple. In practice, it doesn't really matter because
both CLI debug options aren't used together when a "vscale x ..." width
is forced.
[InstCombine] Fold fpto[su]i.sat of NaN guarded select
fpto[su]i.sat returns 0 for both NaN and $\pm 0.0$, so a select that
replaces a NaN input with zero does not change the result, and the call
can take X directly.
```llvm
%not.nan = fcmp ord float %x, 0.0
%sel = select i1 %not.nan, float %x, float 0.0
%r = call i32 @llvm.fptosi.sat.i32.f32(float %sel)
-->
%r = call i32 @llvm.fptosi.sat.i32.f32(float %x)
```
The inverted form `select (fcmp uno X, 0.0), 0.0, X` is folded too.
Only the canonical `fcmp ord/uno X, 0.0` is matched, which also covers
`oeq/une X, X` after fcmp canonicalization.
[InstCombine] Add tests for fpto[su]i.sat of NaN guarded select. NFC
fpto[su]i.sat returns 0 for NaN and +/-0.0, so the select is redundant.
Cover ord/oeq/uno/une checks, scalar and vector, and negative cases.
