editors/openoffice-4: fix build on powerpc64
set_soenv.in only knows the JRE library directories for gcj on powerpc64,
so the sax and bean modules were linked with three empty -L arguments
that swallowed -L/usr/local/lib. Set them for OpenJDK like on amd64.
databases/clickhouse: enable on powerpc64le
The bundled OpenSSL ships POWER8 assembly pre-generated with the
big-endian "linux64v2" perlasm flavour, which gives wrong AES results
on little-endian. Regenerate it with "linux64le" before configuring.
Until rtld annotates the end of the stack on powerpc64, the bundled
libunwind crashes when it collects a backtrace on the main thread.
Drop its fallback to the link register, as the base libunwind does.
Approved by: bofh (maintainer, via email)
databases/clickhouse-devel: enable on powerpc64le
The bundled OpenSSL ships POWER8 assembly pre-generated with the
big-endian "linux64v2" perlasm flavour, which gives wrong AES results
on little-endian. Regenerate it with "linux64le" before configuring.
Until rtld annotates the end of the stack on powerpc64, the bundled
libunwind crashes when it collects a backtrace on the main thread.
Drop its fallback to the link register, as the base libunwind does.
Approved by: bofh (maintainer, via email)
[CodeGenPrepare] Fold disjoint or into addressing modes (#233669)
The addressing-mode matcher only looks through `add`. When the address
is used in another block, the `or` is computed separately instead of
folding into the memory operand:
```
; before
leal 1(,%ecx,4), %ecx
movzbl (%eax,%ecx), %eax
; after
movzbl 1(%ecx,%eax,4), %eax
```
Treat `or disjoint` like `add`.
InstCombine canonicalizes `add X, C` to `or disjoint X, C` when the
operands have no common set bits
LLM-aided
[mlir] Detect hasLoop cycles with a single DFS
Calling isRegionReachable for every region the traversal popped made
hasLoop quadratic in the number of region successor edges. Use one
depth-first search from the entry regions instead. Reaching a region
that is still on the DFS stack is a loop, reaching a finished one is
not. Each region is queried at most once and the search stops at the
first loop.
Both traversals now get a region's successors from
RegionBranchOpInterface::getSuccessorRegions(Region &) instead of
asking each terminator with null operand attributes. The in-tree
terminators that override getSuccessorRegions (scf.condition and
cir.condition) return the same regions as their parent op when no
operand is constant.
Restore the dropped debug output. Rename the multi-branch test and
drive its mock op from attributes. Add tests for a diamond, a loop
through the entry region, a loop in an unreachable region and
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[FastISel] Don't fold loads from swifterror values (#234061)
Where the target supports swifterror, the value lives in a register, so
a
load from it can't become a memory operand. X86 load selection already
refuses such loads, but tryToFoldLoad didn't, so at -O0 on x86-64 a load
from a swifterror argument that feeds a compare was folded into
`cmpq $0, (%r12)`: it read through the error register instead of testing
it. Swift's dispatch thunks for methods with a typed error emit this
pattern and crashed at -Onone on x86-64.
Assisted-by: Claude Opus 5.5
Assisted-by: Codex (gpt-6-astra)
www/domoticz: fix failing stage-qa
Fixing stage-qa by removing internal maintainer script to make
"packages" for Linux, so this is unneeded. Fix USES=lua
PR: 299428
Reported by: Daniel Engberg <diizzy at FreeBSD.org>
[AMDGPU] Materialize subregister WMMA scales at lane width
Copy an SGPR subregister scale into a VGPR of that lane's size so two
lanes of one tuple stay independent.
Co-authored-by: Cursor <cursoragent at cursor.com>
[AMDGPU] Materialize WMMA SGPR scales to VGPRs before scheduling
v_wmma_scale scale operands accept an SGPR or a VGPR. On GFX12,
depctr_va_ssrc is a 1-deep counter, so each VALU instruction that reads
an SGPR scale takes the only scalar-source slot. A run of WMMA ops that
all read SGPR scales therefore serializes. One cross-bank copy pays for
that slot once; later WMMA ops then read a VGPR and no longer contend
for va_ssrc.
SIMaterializeWMMAScale runs at the end of the machine SSA optimizations,
after SIShrinkInstructions and before scheduling. It is skipped at -O0
and on targets older than GFX12. GFX1250 is included: the separate VALU
read-after-write hazard no longer applies there, but the dependency
counter still does.
The pass walks every WMMA that has scale_src0 and records virtual SGPR
uses of scale_src0 and scale_src1, grouped by register. Physical
registers and subregister uses are left alone. For each SGPR it inserts
a COPY into a low aligned VGPR (the lo256 class matching the scale's
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[AMDGPU] Count WMMA scale copies against both operands
Copying a shared scale while its partner stays an SGPR adds a va_ssrc
issue without removing one. Choose copies from both scale operands.
