FreeBSD/ports 61993c2devel/R-cran-rJava Makefile

devel/R-cran-rJava: pin to java 8

Does not build with JDK11+.

PR:     291568
DeltaFile
+3-1devel/R-cran-rJava/Makefile
+3-11 files

LLVM/project 9a727afutils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Port c22d82a1d43465912edeb0f67929245f40a8a822 (#171885)

DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

OpenBSD/src abbUGhLusr.sbin/bgpd rde_adjout.c rde.h

   PREFIX_ADJOUT_FLAG_DEAD is no longer needed and can be replaced with
   a check that the attrs pointer is NULL. Refactor the code now a bit
   since the logic got a bit simpler.

   OK tb@
VersionDeltaFile
1.10+10-19usr.sbin/bgpd/rde_adjout.c
1.330+2-4usr.sbin/bgpd/rde.h
+12-232 files

FreeBSD/ports ae208e4science/colt Makefile

science/colt: pin to openjdk8

It fails on jdk21:
error: as of release 9, '_' is a keyword, and may not be used as an identifier

Build.xml also needed an encoding="ISO-8859-1" in the javac target.

NB: Upstream didn't make a release since 2004.

PR:     272855
Approved-by:    no maintainer
DeltaFile
+2-0science/colt/Makefile
+2-01 files

FreeBSD/ports 23fef9dsysutils/auto-admin distinfo Makefile

sysutils/auto-admin: Update to 0.8.4.2

auto-update-system: Remove auto-restart-services
(Should have been done in previous commit)
DeltaFile
+3-3sysutils/auto-admin/distinfo
+2-1sysutils/auto-admin/Makefile
+5-42 files

LLVM/project 8d59ccalldb/source/Plugins/Platform CMakeLists.txt, lldb/source/Plugins/Platform/WebAssembly PlatformWasm.cpp PlatformWasm.h

[lldb] Add WebAssembly platform (#171507)

This PR adds a platform for WebAssembly. Heavily inspired by Pavel's
QemuUser, the platform lets you configure a WebAssembly runtime to run a
Wasm binary.

For example, the following configuration can be used to launch binaries
under the WebAssembly Micro Runtime (WARM):

```
settings set -- platform.plugin.wasm.runtime-args --heap-size=1048576
settings set -- platform.plugin.wasm.port-arg -g=127.0.0.1:
settings set -- platform.plugin.wasm.runtime-path /path/to/iwasm-2.4.0
```

With the settings above, you can now launch a binary directly under
WAMR:

```

    [24 lines not shown]
DeltaFile
+213-0lldb/source/Plugins/Platform/WebAssembly/PlatformWasm.cpp
+79-0lldb/source/Plugins/Platform/WebAssembly/PlatformWasm.h
+23-0lldb/source/Plugins/Platform/WebAssembly/PlatformWasmProperties.td
+23-0lldb/source/Plugins/Platform/WebAssembly/CMakeLists.txt
+5-2llvm/docs/ReleaseNotes.md
+1-0lldb/source/Plugins/Platform/CMakeLists.txt
+344-26 files

FreeBSD/src 8ac7a38. UPDATING, share/man/man4 scsi.4

cam: Reduce overly long timeout values for initial device probing

Currently, we have very long timeouts for the initial probing
commands. However, these are not appropriate for modern (post 2010) SCSI
disks. Sandards since SPC3 state that these commands should not wait for
media access. Since we retry them several times during the initial bus
scan, these delays can delay the boot by minutes (5 minutes per errant
disk in our expereince). These delays don't help and only hurt, so
reduce the TESTUNITREADY, INQUIRY and MODESENSE commands (during the
initial probe). Provide sysctl/tuneables to change the time for these
and also the REPORTLUNS commands for people that might need to adjust
them for devices that violate this belief but none-the-less work with
longer timeouts.
        kern.cam.tur_timeout            (default was 60s, now 1s)
        kern.cam.inquiry_timeout        (default was 60s, now 1s)
        kern.cam.reportluns_timeout     (default is 60s)
        kern.cam.modesense_timeout      (default was 60s, now 1s)
This can be partially merged: the sysctls can, but the new defaults likely
shouldn't.

    [3 lines not shown]
DeltaFile
+33-1share/man/man4/scsi.4
+22-6sys/cam/scsi/scsi_xpt.c
+11-0UPDATING
+66-73 files

LLVM/project f6c04cdclang-tools-extra/clang-doc/assets namespace-template.mustache, clang-tools-extra/test/clang-doc namespace.cpp mustache-separate-namespace.cpp

[clang-doc] Serialize the global namespace name in JSON (#171701)

Previously, the global namespace's "Name" field was left empty. It could
be identified this way, but it could also be identified by its USR.
Actually populating the "Name" field allows for nicer output in the
future.
DeltaFile
+4-4clang-tools-extra/test/clang-doc/namespace.cpp
+1-1clang-tools-extra/clang-doc/assets/namespace-template.mustache
+1-1clang-tools-extra/test/clang-doc/json/concept.cpp
+1-1clang-tools-extra/test/clang-doc/json/namespace.cpp
+1-1clang-tools-extra/test/clang-doc/mustache-separate-namespace.cpp
+1-1clang-tools-extra/unittests/clang-doc/JSONGeneratorTest.cpp
+9-91 files not shown
+11-97 files

HardenedBSD/src 3255fcesys/compat/linux linux_misc.c linux_misc.h, sys/dts/arm imx53x.dtsi imx51x.dtsi

Merge branch 'freebsd/current/main' into hardened/current/master
DeltaFile
+0-712sys/dts/arm/imx53x.dtsi
+0-619sys/dts/arm/imx51x.dtsi
+0-151sys/dts/arm/digi-ccwmx53.dts
+0-125sys/dts/arm/efikamx.dts
+27-0sys/compat/linux/linux_misc.c
+11-0sys/compat/linux/linux_misc.h
+38-1,6076 files not shown
+50-1,61512 files

HardenedBSD/src ed83f5fcddl/lib/libdtrace io.d, sys/netinet ip_divert.c

Merge branch 'freebsd/15-stable/main' into hardened/15-stable/main
DeltaFile
+16-6sys/riscv/riscv/pmap.c
+9-8sys/netinet/ip_divert.c
+1-1cddl/lib/libdtrace/io.d
+26-153 files

LLVM/project 5e3549aclang-tools-extra/clang-doc JSONGenerator.cpp, clang-tools-extra/test/clang-doc/json class.cpp

[clang-doc] Serialize private members in JSON (#171700)

DeltaFile
+10-0clang-tools-extra/test/clang-doc/json/class.cpp
+6-0clang-tools-extra/clang-doc/JSONGenerator.cpp
+16-02 files

HardenedBSD/ports 796c90adevel/git pkg-plist, graphics/gpu-firmware-amd-kmod pkg-plist

Merge branch 'freebsd/main' into hardenedbsd/main
DeltaFile
+821-822java/intellij-ultimate/pkg-plist
+443-0security/vuxml/vuln/2025.xml
+15-8net/samba422/pkg-plist.cluster
+23-0devel/git/pkg-plist
+20-0graphics/gpu-firmware-amd-kmod/pkg-plist
+16-3graphics/gpu-firmware-kmod/Makefile
+1,338-833103 files not shown
+1,660-1,087109 files

LLVM/project ed398f2llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/AMDGPU extract-insert-i8.ll shuffles-of-length-changing-shuffles.ll

VectorCombine: Fold chains of shuffles fed by length-changing shuffles

Such chains can arise from folding insert/extract chains.

commit-id:a960175d
DeltaFile
+192-0llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+4-32llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
+4-8llvm/test/Transforms/VectorCombine/AMDGPU/shuffles-of-length-changing-shuffles.ll
+200-403 files

LLVM/project 352f05bllvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/AMDGPU extract-insert-i8.ll

VectorCombine: Improve the insert/extract fold in the narrowing case

Keeping the extracted element in a natural position in the narrowed
vector has two beneficial effects:

1. It makes the narrowing shuffles cheaper (at least on AMDGPU), which
   allows the insert/extract fold to trigger.
2. It makes the narrowing shuffles in a chain of extract/insert
   compatible, which allows foldLengthChangingShuffles to successfully
   recognize a chain that can be folded.

There are minor X86 test changes that look reasonable to me. The IR
change for AVX2 in llvm/test/Transforms/VectorCombine/X86/extract-insert-poison.ll
doesn't change the assembly generated by `llc -mtriple=x86_64-- -mattr=AVX2`
at all.

commit-id:c151bb04
DeltaFile
+6-16llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+2-16llvm/test/Transforms/VectorCombine/AMDGPU/extract-insert-i8.ll
+8-4llvm/test/Transforms/VectorCombine/X86/extract-insert-poison.ll
+4-4llvm/test/Transforms/VectorCombine/X86/extract-insert.ll
+2-2llvm/test/Transforms/VectorCombine/X86/pr126085.ll
+22-425 files

FreeNAS/freenas b1980f7tests do_not_merge.txt

Testing PR only.
DeltaFile
+1-0tests/do_not_merge.txt
+1-01 files

LLVM/project 8483d3cllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-scoring.ll promote-alloca-negative-index.ll

AMDGPU/PromoteAlloca: Refactor into analysis / commit phases

This change is motivated by the overall goal of finding alternative ways
to promote allocas to VGPRs. The current solution is effectively limited
to allocas whose size matches a register class, and we can't keep adding
more register classes. We have some downstream work in this direction,
and I'm currently looking at cleaning that up to bring it upstream.

This refactor paves the way to adding a third way of promoting allocas,
on top of the existing alloca-to-vector and alloca-to-LDS. Much of the
analysis can be shared between the different promotion techniques.

Additionally, the idea behind splitting the pass into an analysis
phase and a commit phase is that it ought to allow us to more easily make
better "big picture" decision about which allocas to promote how in the
future.

commit-id:138f5985
DeltaFile
+347-304llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+34-30llvm/test/CodeGen/AMDGPU/promote-alloca-scoring.ll
+2-4llvm/test/CodeGen/AMDGPU/promote-alloca-negative-index.ll
+383-3383 files

FreeNAS/freenas 507eae1src/middlewared/middlewared/apps webshell_app.py

NAS-138885 / 26.04 / Replace usage of `select.select` in webshell_app.py (#17808)

We avoid the use of this function since it can fail for large file
descriptors.
DeltaFile
+7-3src/middlewared/middlewared/apps/webshell_app.py
+7-31 files

LLVM/project 75cd29bllvm/lib/Transforms/Instrumentation MemProfUse.cpp, llvm/test/Transforms/PGOProfile memprof-dump-matched-alloc-site.ll

[MemProf] Add option to emit full call context for matched allocations (#170516)

Add the -memprof-print-matched-alloc-stack option to enable emitting the
full allocation call context (of stack ids) for each matched allocation
reported by -memprof-print-match-info. Noop when the latter is not
enabled.
DeltaFile
+64-28llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
+19-11llvm/test/Transforms/PGOProfile/memprof-dump-matched-alloc-site.ll
+83-392 files

LLVM/project ca6eb2fclang-tools-extra/clang-doc JSONGenerator.cpp, clang-tools-extra/test/clang-doc/json inheritance.cpp

[clang-doc] Add JSON bools for parents, vparents and test (#171699)

Parents and virtual parents didn't have "Has" bools in JSON output. That
made it difficult to only create output conditionally.

Also add an explicit test for inheritance and parents, vparents, and
bases which actually weren't tested in JSON
DeltaFile
+111-0clang-tools-extra/test/clang-doc/json/inheritance.cpp
+6-2clang-tools-extra/clang-doc/JSONGenerator.cpp
+2-0clang-tools-extra/unittests/clang-doc/JSONGeneratorTest.cpp
+119-23 files

LLVM/project 3a6c8c4llvm/include/llvm/CodeGen LibcallLoweringInfo.h, llvm/include/llvm/SandboxIR Constant.h

llvm: Add missing `LLVM_ABI` annotations (#171629)

This patch updates various LLVM headers to properly add the `LLVM_ABI`
and `LLVM_ABI_FOR_TEST` annotations to build LLVM as a DLL on Windows.

This effort is tracked in #109483.

---------

Co-authored-by: Nikita Popov <github at npopov.com>
DeltaFile
+4-3llvm/include/llvm/Support/Hash.h
+2-1llvm/include/llvm/Transforms/Utils/DebugSSAUpdater.h
+1-1llvm/include/llvm/SandboxIR/Constant.h
+1-1llvm/include/llvm/CodeGen/LibcallLoweringInfo.h
+8-64 files

LLVM/project c22d82amlir/include/mlir/Conversion/AMDGPUToROCDL AMDGPUToROCDL.h, mlir/lib/Conversion/AMDGPUToROCDL AMDGPUToROCDL.cpp

[mlir][amdgpu] Move GPU memory spaces conversion to single place (#171876)

DeltaFile
+17-12mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+2-12mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
+1-13mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+4-3mlir/lib/Dialect/GPU/TransformOps/CMakeLists.txt
+5-0mlir/include/mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h
+29-405 files

LLVM/project 0afd6eeclang-tools-extra/clang-doc JSONGenerator.cpp, clang-tools-extra/clang-doc/assets class-template.mustache

[clang-doc] Serialize "IsStatic" for fields (#171698)

DeltaFile
+2-2clang-tools-extra/clang-doc/assets/class-template.mustache
+1-1clang-tools-extra/test/clang-doc/basic-project.mustache.test
+2-0clang-tools-extra/test/clang-doc/json/class.cpp
+2-0clang-tools-extra/unittests/clang-doc/JSONGeneratorTest.cpp
+1-0clang-tools-extra/clang-doc/JSONGenerator.cpp
+8-35 files

FreeBSD/ports ab2aaddnet/samba422 pkg-plist.cluster

net/samba422: Fix pkg-plist.cluster

PR:             291104
Reported by:    vvd
DeltaFile
+15-8net/samba422/pkg-plist.cluster
+15-81 files

HardenedBSD/ports ab2aaddnet/samba422 pkg-plist.cluster

net/samba422: Fix pkg-plist.cluster

PR:             291104
Reported by:    vvd
DeltaFile
+15-8net/samba422/pkg-plist.cluster
+15-81 files

LLVM/project ef24946llvm/include/llvm/Transforms/Utils LoopPeel.h, llvm/lib/Transforms/Scalar LoopUnrollPass.cpp

[LoopPeel] Peel loops to enable natural-sized loads
DeltaFile
+479-0llvm/test/Transforms/LoopUnroll/peel-last-for-load-widening.ll
+338-1llvm/lib/Transforms/Utils/LoopPeel.cpp
+172-0llvm/test/Transforms/LoopUnroll/peel-load-widening-edge-cases.ll
+15-3llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+13-1llvm/include/llvm/Transforms/Utils/LoopPeel.h
+3-1llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1,020-61 files not shown
+1,022-77 files

FreeNAS/freenas 242a4e3src/middlewared/middlewared/apps webshell_app.py

no need to suppress
DeltaFile
+1-2src/middlewared/middlewared/apps/webshell_app.py
+1-21 files

LLVM/project 125fd3ellvm/lib/Target/AArch64 AArch64InstrGISel.td, llvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp AArch64RegisterBankInfo.cpp

[GlobalISel][AArch64] Added support for sli/sri intrinsics (#171448)

sli intrinsic now lowers correctly for all vector types.
DeltaFile
+110-16llvm/test/CodeGen/AArch64/arm64-vshift.ll
+15-0llvm/lib/Target/AArch64/AArch64InstrGISel.td
+14-0llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+4-0llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+143-164 files

LLVM/project 5eb2ec2llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine ldexp.ll fold-select-fmul-if-zero.ll

InstCombine: Fold ldexp with constant exponent to fmul (#171731)

If we can represent this with an fmul, prefer it as a canonical
form. More optimizations will understand fmul, and allows contract to
fma.
DeltaFile
+36-26llvm/test/Transforms/InstCombine/ldexp.ll
+13-0llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+2-8llvm/test/Transforms/InstCombine/fold-select-fmul-if-zero.ll
+51-343 files

HardenedBSD/ports 30b1436sysutils/py-hcloud distinfo Makefile

sysutils/py-hcloud: update to 2.12.0

Changes:        https://github.com/hetznercloud/hcloud-python/blob/v2.12.0/CHANGELOG.md
Reported by:    repology,portscout
DeltaFile
+3-3sysutils/py-hcloud/distinfo
+1-1sysutils/py-hcloud/Makefile
+4-42 files

FreeBSD/ports 30b1436sysutils/py-hcloud distinfo Makefile

sysutils/py-hcloud: update to 2.12.0

Changes:        https://github.com/hetznercloud/hcloud-python/blob/v2.12.0/CHANGELOG.md
Reported by:    repology,portscout
DeltaFile
+3-3sysutils/py-hcloud/distinfo
+1-1sysutils/py-hcloud/Makefile
+4-42 files