FreeNAS/freenas 9f7c1c9 — src/middlewared/middlewared/api/v27_0_0 system_ntpserver.py, src/middlewared/middlewared/api/v28_0_0 system_ntpserver.py

Remove implementation details from the NTP server create schema

- Drop the NTPServerCreate docstring
- Give the overridden `address` field its description back; the
  generated JSON schema had lost the inherited one

Check chrony server addresses for whitespace in one pass

Use any(c.isspace() ...), which stops at the first whitespace character,
and build the list of servers in the same loop that logs the skipped
ones instead of checking each address twice.
DeltaFile
+3-8src/middlewared/middlewared/api/v28_0_0/system_ntpserver.py
+3-8src/middlewared/middlewared/api/v27_0_0/system_ntpserver.py
+5-4src/middlewared/middlewared/etc_files/chrony/chrony.conf.mako
+11-203 files

FreeBSD/ports 98cb923 — misc/codex Makefile, misc/codex/files patch-codex-rs_core_src_tools_handlers_apply__patch.rs patch-codex-rs_core_src_tools_runtimes_apply__patch__tests.rs

misc/codex: Restore apply_patch's ability for deleting files

PR:             298698
Reported by:    shurd
DeltaFile
+27-0misc/codex/files/patch-codex-rs_core_src_tools_runtimes_apply__patch.rs
+18-0misc/codex/files/patch-codex-rs_core_src_tools_runtimes_apply__patch__tests.rs
+6-6misc/codex/files/patch-codex-rs_core_src_tools_handlers_apply__patch.rs
+1-0misc/codex/Makefile
+52-64 files

LLVM/project 263476d — mlir/lib/Dialect/OpenACC/IR OpenACC.cpp, mlir/test/Dialect/OpenACC invalid.mlir

[mlir][acc] Fixes Issue HostDataOp verifier crash on block-argument data operands (#228226)

Used dyn_cast_if_present in HostDataOp::verify so data operands with no
defining op (block arguments) emit "expect data entry operation as
defining op" instead of asserting in dyn_cast.

Fixes #226641
DeltaFile
+10-0mlir/test/Dialect/OpenACC/invalid.mlir
+1-1mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+11-12 files

FreeNAS/freenas c826cb7 — src/middlewared/middlewared/utils/disks_ disk_class.py

Log the reason when SED initial setup fails

Every failure during SED initial setup returned a status and threw
away the error. A wrong password, a disk that dropped off the bus and
a drive that refused commands all looked the same in the log.

The error is now logged with its traceback before the status is
returned. The returned status does not change.
DeltaFile
+7-0src/middlewared/middlewared/utils/disks_/disk_class.py
+7-01 files

LLVM/project 9919736 — mlir/lib/Dialect/OpenACC/Transforms ACCCGToGPU.cpp, mlir/test/Dialect/OpenACC acc-cg-to-gpu-launch-mapping.mlir acc-cg-to-gpu-attrless-parallel-ancestors.mlir

[mlir][OpenACC] Diagnose unmapped parallel loops in GPU lowering (#225641)

ACCCGToGPU requires parallel dimensions to be assigned before lowering.
Diagnose scf.parallel operations without acc.par_dims inside
acc.compute_region before rewriting.

Keep barrier ancestor lookups within the current compute region so
enclosing host loops are not treated as GPU execution scopes.

Add diagnostic coverage for unmapped parallel loops in func.func and
gpu.func, including nested regions, and verify that surrounding host
loops remain valid. Give the launch-argument remapping test explicit
sequential dimensions.
DeltaFile
+87-0mlir/test/Dialect/OpenACC/acc-cg-to-gpu-attrless-parallel-ancestors.mlir
+38-28mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
+3-2mlir/test/Dialect/OpenACC/acc-cg-to-gpu-launch-mapping.mlir
+128-303 files

LLVM/project 2d91fec — llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-trunc.ll

[X86] combineConcatVectorOps - ensure all suboperand concatenation types are simple (#228522)

Fixes #228264
DeltaFile
+49-0llvm/test/CodeGen/X86/vector-trunc.ll
+12-10llvm/lib/Target/X86/X86ISelLowering.cpp
+61-102 files

LLVM/project 7232ec8 — compiler-rt/lib/sanitizer_common/symbolizer/scripts global_symbols.txt build_symbolizer.sh

[NFC][sanitizer] Link LLVMOption and allow strtof in internal symbolizer (#228490)

Commit f6c78b8262f4 (#228321) moved MC command-line options into
`MCCLOptions.cpp` and added an `LLVMOption` dependency to `LLVMMC`.
Because
`MCAsmInfo.cpp` references `MCCLOptions::Global`, `MCCLOptions.cpp` and
its
generated option parser (which also calls `strtof` via `llvm::to_float`)
are
pulled into the internal symbolizer link.

Add `LLVMOption` to `build_symbolizer.sh` and `strtof U` to
`global_symbols.txt` so internal symbolizer builds and symbol
verification
succeed.

Fixes: https://lab.llvm.org/buildbot/#/builders/66/builds/38119

Assisted-by: Gemini
DeltaFile
+2-1compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh
+1-0compiler-rt/lib/sanitizer_common/symbolizer/scripts/global_symbols.txt
+3-12 files

LLVM/project 7c67d4b — mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp

Update comment
DeltaFile
+2-2mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+2-21 files

LLVM/project 2938b86 — mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp, mlir/test/Dialect/LLVMIR inlining-alias-scopes.mlir

[mlir][LLVM] Use a disjoint scope domain when inlining noalias

This matches recent changes to the LLVM inliner.

AI disclosure: Claude wrote the code, I wrote the commit message and
have done initial review.
DeltaFile
+28-25mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+10-18mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
+38-432 files

LLVM/project be0b7ff — mlir/test/Dialect/LLVMIR inlining-alias-scopes.mlir

Test that the inliner keeps the flag when it clones a domain

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+35-0mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
+35-01 files

LLVM/project 9501a74 — mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp

Remove pointless comment
DeltaFile
+0-2mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+0-21 files

LLVM/project 9727b01 — mlir/include/mlir/Dialect/LLVMIR LLVMAttrDefs.td, mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp

[mlir][LLVM] Add disjointScopes to AliasScopeDomainAttr

This also updates the MLIR-side inliner to clone disjoint domains
while cloning alias scopes, matching changes to LLVM.

AI disclosure: Claude wrote the code, I wrote the commit message and
looked at the code.
DeltaFile
+25-0mlir/test/Target/LLVMIR/Import/metadata-alias-scopes.ll
+23-0mlir/test/Target/LLVMIR/attribute-alias-scopes.mlir
+17-2mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+4-1mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+2-2mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+3-1mlir/lib/Target/LLVMIR/ModuleImport.cpp
+74-66 files

LLVM/project 50ae32b — llvm/lib/Target/AMDGPU AMDGPULowerModuleLDSPass.cpp, llvm/test/CodeGen/AMDGPU remove-no-kernel-id-attribute.ll

[AMDGPU] Use a disjoint scope domain for merged LDS structs

When lowering LDS values, all the values are mutually disjoint, so we
can use the newly-added disjoint scopes feature to simplify the IR.

AI disclosure: Claude wrote this and I reviewed it and wrote the
 commit message
DeltaFile
+16-51llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+8-12llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
+24-632 files

LLVM/project 39b6370 — llvm/test/CodeGen/AMDGPU lower-kernel-and-module-lds.ll lower-module-lds-via-hybrid.ll

Test fixups
DeltaFile
+28-19llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
+36-10llvm/test/CodeGen/AMDGPU/lower-module-lds-precise-allocate-to-module-struct.ll
+17-17llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
+15-18llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
+11-13llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
+9-9llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll
+116-865 files not shown
+148-12011 files

LLVM/project a5e6d4c — llvm/lib/Target/AMDGPU AMDGPULowerKernelArguments.cpp, llvm/test/CodeGen/AMDGPU lower-kernargs.ll si-split-load-store-alias-info.ll

[AMDGPU] Use a disjoint scope domain for noalias kernel arguments

All noalias arguments of a kernel are disjoint with each other, so we
can use a disjoint scope to save on metadata construction.

AI disclosure: Claude wrote this, I looked at it and wrote this
message.
DeltaFile
+90-105llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
+19-13llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
+11-11llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
+8-8llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
+4-4llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
+132-1415 files

LLVM/project a318aa0 — clang/test/CodeGen arm-v8.2a-neon-intrinsics-generic.c arm_neon_intrinsics.c, llvm/lib/Transforms/Utils InlineFunction.cpp

[Inliner] Use a disjoint scope domain for noalias arguments

InlineFunction creates alias.scope/noalias metadata to represent the
set of `noalias` arguments to a function. We don't need the `!noalias`
now that we have the ability to use disjoint scopes, saving us IR size
and metadata bloat.

TODO move these to a previous commit.
Also changes InstCombine to not drop the experimental.noalias.scope.decl
for disjoint scopes even if they're not mentioned in a `!noalias`, but
do still delete them if they're not used.
DeltaFile
+324-324clang/test/CodeGen/arm_neon_intrinsics.c
+72-72clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
+35-30llvm/lib/Transforms/Utils/InlineFunction.cpp
+13-14llvm/test/Transforms/Inline/noalias-calls2.ll
+12-12llvm/test/Transforms/Inline/noalias2.ll
+11-11llvm/test/Transforms/PhaseOrdering/pr39282.ll
+467-4639 files not shown
+487-48315 files

LLVM/project ac050e4 — llvm/test/Transforms/Inline noalias2.ll

Test a callee that has both noalias arguments and its own scopes

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+51-0llvm/test/Transforms/Inline/noalias2.ll
+51-01 files

LLVM/project 0240730 — flang/test/Fir/CUDA cuda-data-transfer.fir, flang/test/HLFIR simplify-hlfir-intrinsics-eoshift.fir

Make Flang dialect assembly formats strict properties compatible (#226602)

Enable strict properties in FIR, HLFIR, CUF, MIF, and FIRCG. Bind
inherent attributes explicitly in custom formats and update Flang
assembly checks.

Assisted-by: Codex
DeltaFile
+219-219flang/test/Transforms/licm.fir
+210-210flang/test/Lower/split-sum-expression-tree-lowering.f90
+164-164flang/test/Fir/CUDA/cuda-data-transfer.fir
+140-140flang/test/HLFIR/simplify-hlfir-intrinsics-eoshift.fir
+99-99flang/test/Transforms/loop-versioning.fir
+88-88flang/test/Lower/derived-allocatable-components.f90
+920-9201,046 files not shown
+10,358-10,3131,052 files

LLVM/project c851fb6 — clang/test/CodeGen arm_neon_intrinsics.c arm-v8.2a-neon-intrinsics-generic.c, llvm/lib/Bitcode/Reader MetadataLoader.cpp

[IR] Add alias scope domains with disjoint scopes (#218768)

See RFC at

https://discourse.llvm.org/t/rfc-disjoint-scope-alias-scope-noalias-domains/91537

This commit adds support for declaring an alias scope domain disjoint.
Disjoint domains are ones where each scope is implicitly `!noalias`
with each other scope in the domain. This is represented by adding an
`i1` into the scope's domain as the second argument, with `i1 true`
representing disjoint scopes and `i1 false` representing the old
non-disjoint behavior. AutoUpgrade mechanisms have been added to add
in the missing `i1 false` to existing metadata.

This commit updates alias analysis to know about disjoint scopes and
updates the function cloner to also clone the alias domain if it's
disjoint (since, as a herd of LLMs discovered, you don't want the old
IR to be noalias with a clone of itself).


    [4 lines not shown]
DeltaFile
+72-72clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
+116-0llvm/test/Transforms/InstCombine/noalias-scope-decl-disjoint-domain.ll
+54-54clang/test/CodeGen/arm_neon_intrinsics.c
+95-0llvm/lib/Bitcode/Reader/MetadataLoader.cpp
+42-42llvm/test/Transforms/LoopUnroll/peel-loop-noalias-scope-decl.ll
+39-35llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
+418-203196 files not shown
+1,414-735202 files

LLVM/project 2ff5972 — clang/include/clang/Serialization ASTReader.h ASTWriter.h, clang/lib/Serialization ASTReader.cpp ASTWriter.cpp

[clang][Modules] Reimplement Macro Expansion Record Source Location Delta Encoding (#223759)

Source location delta encoding was removed by
https://github.com/llvm/llvm-project/pull/145670 due to a difficult (and
eventually abandoned) bug fix
https://github.com/llvm/llvm-project/pull/145529.

This PR reimplements the encoding to avoid the bug, and adjusts the
order of the fields in the record so that delta encoding achieves more
savings relative to the order we had before.

Assisted by: Claude Code Opus 5.
DeltaFile
+117-0clang/unittests/Serialization/SourceLocationEncodingTest.cpp
+108-0clang/include/clang/Serialization/SourceLocationEncoding.h
+52-9clang/lib/Serialization/ASTWriter.cpp
+24-4clang/lib/Serialization/ASTReader.cpp
+21-0clang/include/clang/Serialization/ASTWriter.h
+18-0clang/include/clang/Serialization/ASTReader.h
+340-131 files not shown
+341-147 files

LLVM/project 9428f1b — llvm/lib/CodeGen AllocationOrder.cpp, llvm/lib/Target/AArch64 AArch64RegisterInfo.cpp

[CodeGen] Use SmallSetVector for getRegAllocationHints (#224472)

Change `TargetRegisterInfo::getRegAllocationHints` and all target
overrides to accept `SmallSetVector<MCPhysReg, 16> &Hints` instead of
`SmallVectorImpl`, structurally preventing duplicate register allocation
hints while preserving insertion order.

Assisted-by: Gemini
Link: #190139
Link: #193011
Link: #219007
Link: #224448
Link: #224451
Link: #224742
DeltaFile
+46-0llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
+13-14llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+10-12llvm/lib/Target/X86/X86RegisterInfo.cpp
+7-9llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+6-6llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
+5-5llvm/lib/CodeGen/AllocationOrder.cpp
+87-4612 files not shown
+111-7518 files

LLVM/project e513e2b — clang-tools-extra/docs/clang-tidy/checks/readability uppercase-literal-suffix.md string-compare.md

[clang-tidy][docs] Address readability Markdown review feedback [5/5]
DeltaFile
+17-14clang-tools-extra/docs/clang-tidy/checks/readability/suspicious-call-argument.md
+1-1clang-tools-extra/docs/clang-tidy/checks/readability/uppercase-literal-suffix.md
+1-1clang-tools-extra/docs/clang-tidy/checks/readability/string-compare.md
+19-163 files

FreeNAS/freenas 7e4917b — tests/api2 test_ntpserver_alert.py test_ntpserver_nts.py

Fix NTP integration test failures

- Clear chronyd's systemd start limit in the NTP test helpers, before
  the test and before restoring the original servers. With the two NTS
  servers the migration adds there are five stock servers, so removing
  them and adding a test server starts chronyd six times within ten
  seconds. systemd refuses the sixth start and service.control only logs
  it, so chronyd was stopped for the alert and authdata checks
- Expect the client's ValidationErrors from system.security.update. A
  job reports its validation errors with the client's exception class,
  not the middleware's
DeltaFile
+9-1tests/api2/test_ntpserver_nts.py
+5-0tests/api2/test_ntpserver_alert.py
+14-12 files

LLVM/project 32681de — compiler-rt/lib/asan asan_win_static_runtime_thunk.cpp, compiler-rt/lib/interception interception_win.h interception_win.cpp

[ASan][Windows] Intercept memcpy when the CRT provides it separately from memmove (#221491)

This is the third retry in a attempt to fix
https://github.com/llvm/llvm-project/issues/126077 (the other two
attempts being https://github.com/llvm/llvm-project/pull/192060 and
https://github.com/llvm/llvm-project/pull/193633)

I was looking at the wrong thing: I was trying to compare `&memcpy` and
`&memmove` in the ASan runtime itself; but the real problem in
https://github.com/llvm/llvm-project/issues/126077 was the dynamic CRT,
which provides non-aliased `&memcpy`.

Please see repro and output:

[output.txt](https://github.com/user-attachments/files/31870348/output.txt)

Historically, the CRT provided `memcpy` and `memmove` as a single
implementation, aliasing both symbols. Since Visual Studio 17.7
(vcruntime140.dll 14.38), [a rewrite of

    [11 lines not shown]
DeltaFile
+56-16compiler-rt/lib/interception/interception_win.cpp
+29-9compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc
+37-0compiler-rt/test/asan/TestCases/Windows/intercept_memmove.cpp
+23-1compiler-rt/lib/asan/asan_win_static_runtime_thunk.cpp
+13-0compiler-rt/lib/interception/tests/interception_win_test.cpp
+8-0compiler-rt/lib/interception/interception_win.h
+166-266 files

LLVM/project 62e30e3 — llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp, llvm/test/CodeGen/AMDGPU mad-mix.ll

[AMDGPU][GlobalISel] Fold neg/abs modifiers when mad-mix selects the low half (#223535)

selectVOP3PMadMixModsImpl re-runs the fneg/fabs match after rewriting Src to the 32-bit register the 16-bit value is a half of, but only did so on the isExtractHiElt path, not for isExtractLoElt.

The two halves are not symmetric. An fneg/fabs of a 32-bit float only touches bit 31, which is the sign bit of the high half, so folding it into a modifier on the selected high half is correct. The low half's sign bit is bit 15, which such an fneg/fabs leaves alone, so only a modifier that acts on each 16-bit element can be folded there. So the source must be a 2 x 16-bit vector to fold it.
DeltaFile
+972-0llvm/test/CodeGen/AMDGPU/mad-mix.ll
+252-257llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+20-22llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+10-16llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
+9-6llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+1,263-3015 files

LLVM/project cd8c5d3 — compiler-rt/lib/ubsan/offload CMakeLists.txt

[compiler-rt][ubsan] Add powerpc64le support to offload UBSan HSA interceptors (#228007)

The HSA interceptor library was limited to` x86_64` and `aarch64`,
causing the `hsa-load-order` and `hsa-missing` lit tests to fail on
`powerpc64le`.

All dependencies (sanitizer_offload, RTSanitizerOffload,
llvm-libc-common-utilities)
are already available on powerpc64le Linux and the INTERCEPTOR macro
works
via standard ELF symbol interposition on that platform.

Add PPC64 to ALL_UBSAN_OFFLOAD_SUPPORTED_ARCH to extend support for
powerpc64le.

Co-authored-by: Riyaz Ahmad <riyaz.ahmad at ibm.com>
DeltaFile
+1-1compiler-rt/lib/ubsan/offload/CMakeLists.txt
+1-11 files

LLVM/project fea6c3c — clang/include module.modulemap

[clang] Add SPIRVTypes.def to the module map (#228240)

Follow-up to https://github.com/llvm/llvm-project/pull/207077, which
added the file without listing it. Fixes "missing submodule
'Clang_Basic.SPIRVTypes'" in modular builds.
DeltaFile
+1-0clang/include/module.modulemap
+1-01 files

LLVM/project e54e42e — clang/test/CodeGen/RISCV rvp-intrinsics.c, clang/test/CodeGen/X86 avx512bw-builtins.c

Merge branch 'main' into users/vitalybuka/spr/nfcsanitizer-link-llvmoption-and-allow-strtof-in-internal-symbolizer
DeltaFile
+0-872llvm/utils/TableGen/OptionParserEmitter.cpp
+871-0llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
+214-231llvm/test/CodeGen/X86/masked-udiv.ll
+444-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+364-0clang/test/CodeGen/X86/avx512bw-builtins.c
+285-62offload/libompaccsupport/device.cpp
+2,178-1,165222 files not shown
+8,053-2,716228 files

LLVM/project 0a3ea38 — clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

rebase to trigger CI

Created using spr 1.3.7
DeltaFile
+444-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+192-193utils/bazel/MODULE.bazel.lock
+303-0llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-partial-unit-ref-addr.test
+134-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+108-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+107-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+1,288-19334 files not shown
+2,018-30540 files

LLVM/project d5c0738 — flang/include/flang/Semantics expression.h, flang/lib/Evaluate intrinsics.cpp

[flang][Semantics] Enforce F2023 C1545 only for generic references

F2023 C1545 requires the consequent-args of a conditional argument to
agree on corank and on the ALLOCATABLE and POINTER attributes, but only
in a reference to a generic procedure. Flang applied the constraint to
every reference containing a conditional argument and rejected conforming
code.

Move the cross-consequent checks out of CheckConditionalArg() and run
them from CheckAndResolveGenericReference(), before ResolveGeneric()
and only when the reference is generic. C1545 is a constraint, not one
of the generic resolution rules in F2023 15.5.5, so check it separately
from candidate matching.

When C1545 fails, return a GenericResolution with errorReported set
without calling ResolveGeneric(). The callers stop analyzing the
reference without additional generic-resolution diagnostics.
GetCalleeAndArguments() also returns before fallback intrinsic probing.
The parse-tree symbol stays generic, so a second analysis of the

    [24 lines not shown]
DeltaFile
+261-18flang/test/Semantics/conditional-arg.f90
+65-48flang/lib/Semantics/check-call.cpp
+34-5flang/lib/Semantics/expression.cpp
+16-0flang/lib/Evaluate/intrinsics.cpp
+14-0flang/include/flang/Semantics/expression.h
+8-0flang/lib/Semantics/check-call.h
+398-711 files not shown
+403-717 files