LLVM/project 5f7f76cclang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/Driver opencl-libclc.cl

Stop trying to handle -nostdlib -stdlib
DeltaFile
+3-8clang/lib/Driver/ToolChains/CommonArgs.cpp
+0-10clang/test/Driver/opencl-libclc.cl
+3-182 files

LLVM/project 77513e7llvm/lib/Target/SPIRV SPIRVGlobalRegistry.h SPIRVISelLowering.cpp

[SPIRV] Add a `SPIRVTypeInst` type with some guardrails (#179947)

The idea behind this PR is to propose a type that we can deploy
gradually to add some guardrails and enforce invariants in the SPIRV
backend.

The PR has 3 commits:
* A first commit where the `SPIRVTypeInst` type is proposed. It's just a
wrapper around `MachineInstr` that adds an assert to check that a
`SPIRVTypeInst` defines a register with the type register class.
* A second commit that shows how the migration could look like for a
single function.
* A third commit that motivates why: we have a `SPIRVType *TypeInst`
that never defines a type in a function whose intention looks very
confusing.
DeltaFile
+55-0llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+8-5llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+63-52 files

LLVM/project 78b8fdcclang/include/clang/Driver CommonArgs.h, clang/lib/Driver/ToolChains CommonArgs.cpp AMDGPU.cpp

clang/AMDGPU: Do not look for rocm device libs if environment is llvm

Introduce usage of the llvm environment type. This will be useful as
a switch to eventually stop depending on externally provided libraries,
and only take bitcode from the resource directory.

I wasn't sure how to handle the confusing mess of -no-* flags. Try
to handle them all. I'm not sure --no-offloadlib makes sense for OpenCL
since it's not really offload, but interpret it anyway. Handle
-nostdlib/-stdlib as a pair overridable
DeltaFile
+33-0clang/test/Driver/opencl-libclc.cl
+21-6clang/lib/Driver/ToolChains/CommonArgs.cpp
+11-3clang/lib/Driver/ToolChains/AMDGPU.cpp
+11-0clang/test/Driver/hip-device-libs-llvm-env.hip
+2-2libclc/CMakeLists.txt
+2-1clang/include/clang/Driver/CommonArgs.h
+80-123 files not shown
+83-129 files

LLVM/project cd719f4clang/include/clang/Driver RocmInstallationDetector.h, clang/lib/Driver/ToolChains AMDGPU.cpp

clang/AMDGPU: Remove dead code in RocmInstallationDetector

The defaulted constructor argument isn't used anywhere, so
this path is unreachable.
DeltaFile
+1-3clang/lib/Driver/ToolChains/AMDGPU.cpp
+1-2clang/include/clang/Driver/RocmInstallationDetector.h
+2-52 files

LLVM/project 7e34aaeclang/include/clang/Analysis/Scalable/Model PrivateFieldNames.def, clang/include/clang/Analysis/Scalable/Serialization SerializationFormat.h

[clang][ssaf][NFC] Refactor SerializationFormat to use macro-based field accessors (#180842)

This reduces code duplication and makes it easier to add new field
accessors.

Assisted-By: claude
DeltaFile
+1-61clang/lib/Analysis/Scalable/Serialization/SerializationFormat.cpp
+30-0clang/include/clang/Analysis/Scalable/Model/PrivateFieldNames.def
+7-22clang/include/clang/Analysis/Scalable/Serialization/SerializationFormat.h
+1-1clang/unittests/Analysis/Scalable/Registries/MockSerializationFormat.cpp
+39-844 files

LLVM/project eed35c9llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 xar.ll sve2-xar.ll

[AArch64] Avoid selecting XAR for reverse operations. (#178706)

Rotations that implement reverse operations, for example:
```c
uint64x2_t foo(uint64x2_t r) {
  return (r >> 32) | (r << 32);
}
```
Are currently lowered as XAR (when available):
```gas
foo:
  movi    v1.2d, #0000000000000000
  xar     v0.2d, v0.2d, v1.2d, #32
  ret
```
This is suboptimal as REV* instructions typically have higher throughput
than XAR and do not require the zero operand.

This patch combines half-rotations to Neon or SVE REVs so that they're
no longer selected as XAR.
DeltaFile
+100-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+93-3llvm/test/CodeGen/AArch64/xar.ll
+67-0llvm/test/CodeGen/AArch64/sve2-xar.ll
+260-33 files

LLVM/project ec18b92clang/lib/CIR/CodeGen CIRGenBuilder.h CIRGenBuiltinAArch64.cpp, clang/lib/CodeGen/TargetBuiltins ARM.cpp

[CIR][NEON] Add lowering for `vnegd_s64` and `vnegh_f16` (#180597)

Add CIR lowering support for the non-overloaded NEON intrinsics
`vnegd_s64` and `vnegh_f16`.

The associated tests are shared with the existing default codegen tests:
  * `neon-intrinsics.c` → `neon/intrinsics.c`
  * `v8.2a-fp16-intrinsics.c` → `neon/fullfp16.c`

A new test file,
  * `clang/test/CodeGen/AArch64/neon/fullfp16.c`

is introduced and is intended to eventually replace:
  * `clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c`

Since both intrinsics are non-overloaded, the CIR and default codegen
handling is moved to the appropriate switch statements. The previous
placement was incorrect.

This change also includes minor refactoring in `CIRGenBuilder.h` to
better group related hooks.
DeltaFile
+42-0clang/test/CodeGen/AArch64/neon/fullfp16.c
+17-0clang/lib/CIR/CodeGen/CIRGenBuilder.h
+12-2clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+11-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-10clang/test/CodeGen/AArch64/neon-intrinsics.c
+4-4clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+86-161 files not shown
+86-237 files

FreeNAS/freenas 1d1f3ebsrc/middlewared/middlewared/plugins/container container.py

NAS-139714 / 26.0.0-BETA.1 / Validate capabilities_state keys in container create/update (#18169)

## Context

We were missing validation for capabilities state which meant that any
invalid value provided by consumer would get stored in the database even
though if it won't have any effect in usage with `nsenter` but still we
should not allow this to happen in the first place.
DeltaFile
+7-0src/middlewared/middlewared/plugins/container/container.py
+7-01 files

FreeBSD/ports 95f2169devel/go-wire distinfo Makefile, devel/go-wire/files patch-vendor_modules.txt

devel/go-wire: Update 0.6.0 => 0.7.0, take maintainership

Changelog:
https://github.com/google/wire/releases/tag/v0.7.0

PR:             292969
Approved by:    Boris Korzun <drtr0jan at yandex.ru> (former maintainer)
DeltaFile
+5-5devel/go-wire/distinfo
+0-10devel/go-wire/files/patch-vendor_modules.txt
+2-3devel/go-wire/Makefile
+7-183 files

OPNSense/core 774a51dsrc/opnsense/mvc/app/views/OPNsense/Firewall alias.volt

Firewall: Aliases - allow TTL usage on host entries, closes https://github.com/opnsense/core/issues/9767
DeltaFile
+2-1src/opnsense/mvc/app/views/OPNsense/Firewall/alias.volt
+2-11 files

LLVM/project e84659bllvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoZvabd.td, llvm/test/CodeGen/RISCV/rvv fixed-vectors-sad.ll

[RISCV][CodeGen] Combine vwaddu+vabd(u) to vwabda(u)

Note that we only support SEW=8/16 for `vwabda(u)`.

Reviewers: topperc, lukel97, preames

Reviewed By: topperc, lukel97

Pull Request: https://github.com/llvm/llvm-project/pull/180162
DeltaFile
+44-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+14-10llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+19-1llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
+14-2llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+91-134 files

LLVM/project 435a162mlir/include/mlir/Dialect/LLVMIR NVVMOps.td

[MLIR][NVVM][NFC] Fix PTX builder class api (#180787)

Previously, `NVVM_PTXBuilder_Op` included `BasicPtxBuilderOpInterface`
as part of the default value of the `traits` parameter. This meant any
subclass that provided an explicit traits list would silently replace
the default and lose the interface, defeating the purpose of the base
class. Callers had to redundantly re-specify the interface.
DeltaFile
+5-5mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+5-51 files

LLVM/project 6f0b8a7llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 aarch64-vector-functions.ll accelerate-vector-functions.ll

[SLP] Use the correct calling convention for vector math routines (#180759)

When vectorising calls to math intrinsics such as llvm.pow we
correctly detect and generate calls to the corresponding vector
math variant. However, we don't pick up and use the calling
convention for the vector math function. This matters for veclibs
such as ArmPL where the aarch64_vector_pcs calling convention
can improve codegen by reducing the number of registers that
need saving across calls.
DeltaFile
+1,656-0llvm/test/Transforms/SLPVectorizer/AArch64/aarch64-vector-functions.ll
+0-1,411llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
+1-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1,657-1,4113 files

OpenBSD/ports zO0VgsEgraphics/libjxl distinfo Makefile

   graphics/libjxl: update to 0.11.2.

   fixes CVE-2025-12474 & CVE-2026-1837
   see https://github.com/libjxl/libjxl/releases/tag/v0.11.2
VersionDeltaFile
1.9+4-4graphics/libjxl/distinfo
1.19+2-2graphics/libjxl/Makefile
+6-62 files

LLVM/project 2a0b530llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 vec-combine-dup-trunc-sext.ll

[AArch64] Eliminate XTN/SSHLL for vector splats

Combine:
  sext(duplane(insert_subvector(undef, trunc(X), 0), idx))
Into:
  duplane(X, idx)

This avoids XTN/SSHLL instruction sequences that occur when splatting
elements from boolean vectors after type legalization, which is common
when using shufflevector with comparison results.
DeltaFile
+93-0llvm/test/CodeGen/AArch64/vec-combine-dup-trunc-sext.ll
+56-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+149-02 files

LLVM/project c84ab35llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility BUILD.gn

[gn build] Port 6b7dd97b1ff9
DeltaFile
+1-0llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
+1-01 files

LLVM/project 6b7dd97lldb/source/Plugins/Process/Utility RegisterInfoPOSIX_ppc64.cpp RegisterInfoPOSIX_ppc64.h

[lldb][AIX] Added RegisterInfo file for PPC64 (#165367)

This PR is in reference to porting LLDB on AIX.
Link to discussions on llvm discourse and github:

1. https://discourse.llvm.org/t/port-lldb-to-ibm-aix/80640
2. https://github.com/llvm/llvm-project/issues/101657
The complete changes for porting are present in this draft PR:
https://github.com/llvm/llvm-project/pull/102601

- Added register information file for PPC64 big-endian architecture
(used by AIX)
DeltaFile
+61-0lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.cpp
+31-0lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.h
+1-0lldb/source/Plugins/Process/Utility/CMakeLists.txt
+93-03 files

LLVM/project 56eb89ellvm/test/CodeGen/RISCV/rvv fixed-vectors-sad.ll

[RISCV] Add precommit test for vwabda(u) combine



Reviewers: preames, topperc, lukel97, mshockwave, VoltrexKeyva

Reviewed By: lukel97, mshockwave, VoltrexKeyva

Pull Request: https://github.com/llvm/llvm-project/pull/180161
DeltaFile
+120-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+120-01 files

FreeBSD/ports 9cb207fdevel/got distinfo Makefile

devel/got: update to 0.122

User-visible changes:
- make 'tog diff' indent log messages above patches for safety
DeltaFile
+3-3devel/got/distinfo
+1-1devel/got/Makefile
+4-42 files

OpenBSD/src MnZwCxausr.sbin/bgpd rde_filter.c rde_update.c

   Create rde_filter_out() to optimise filter matching

   rde_filter_match() now just uses struct filter_match data for matching
   and the peer info from struct filter_peer is only used by rde_filter().
   Outbound filters are per-peer and so the filter_peer check is done during
   configuration of the peer.  So rde_filter_out() just calls rde_filter_match().

   OK tb@
VersionDeltaFile
1.143+94-62usr.sbin/bgpd/rde_filter.c
1.193+4-4usr.sbin/bgpd/rde_update.c
1.341+4-1usr.sbin/bgpd/rde.h
+102-673 files

OpenBSD/ports LZ9fvOqgraphics/py-Pillow Makefile distinfo

   update to py3-Pillow-12.1.1
VersionDeltaFile
1.78+4-2graphics/py-Pillow/Makefile
1.47+2-2graphics/py-Pillow/distinfo
+6-42 files

LLVM/project 304c680lldb/include/lldb/Target Platform.h, lldb/source/Plugins/Architecture/Arm ArchitectureArm.cpp

[lldb] Step over non-lldb breakpoints (#174348)

Several languages support some sort of "breakpoint" function, which adds
ISA-specific instructions to generate an interrupt at runtime. However,
on some platforms, these instructions don't increment the program
counter. When LLDB sets these instructions it isn't a problem, as we
remove them before continuing, then re-add them after stepping over the
location. However, for breakpoint sequences that are part of the
inferior process, this doesn't happen - and so users might be left
unable to continue past the breakpoint without manually interfering with
the program counter.

This patch adds logic to LLDB to intercept SIGTRAPs, inspect the bytes
of the inferior at the program counter, and if the instruction looks
like a BRK or BKPT or similar, increment the pc by the size of the
instruction we found. This unifies platform behaviour (e.g. on x86_64,
LLDB debug sessions already look like this) and improves UX (in my
opinion, but I think it beats messing with stuff every break).


    [21 lines not shown]
DeltaFile
+87-61lldb/source/Target/Platform.cpp
+76-0lldb/test/API/functionalities/builtin-debugtrap/TestBuiltinDebugTrap.py
+0-71lldb/test/API/macosx/builtin-debugtrap/TestBuiltinDebugTrap.py
+42-0lldb/source/Target/StopInfo.cpp
+30-0lldb/source/Plugins/Architecture/Arm/ArchitectureArm.cpp
+29-0lldb/include/lldb/Target/Platform.h
+264-13213 files not shown
+344-14719 files

OpenBSD/ports BmGsNKGdatabases/py-alembic Makefile distinfo

   update to py3-alembic-1.18.4
VersionDeltaFile
1.33+4-1databases/py-alembic/Makefile
1.24+2-2databases/py-alembic/distinfo
+6-32 files

OpenBSD/ports X9n6Y1esysutils/salt distinfo Makefile

   update to 3007.12
VersionDeltaFile
1.75+2-2sysutils/salt/distinfo
1.200+1-1sysutils/salt/Makefile
+3-32 files

LLVM/project 75fb34alibcxx/include __tree map, libcxx/include/__functional operations.h

[libc++] Only make comparators transparent in __tree if they don't cause a conversion (#179453)

We're currently unwrapping `less<T>` even if the `key_type` isn't `T`.
This causes the removal of an implicit conversion to `const T&` if the
types mismatch. Making `less<T>` transparent in that case changes
overload resolution and makes it fail potentially.

Fixes #179319

(cherry picked from commit 9d2303103288f6110622644f78dbd26c8bcf28d5)
DeltaFile
+11-7libcxx/include/__type_traits/make_transparent.h
+12-0libcxx/test/std/containers/associative/map/map.ops/find.pass.cpp
+3-2libcxx/include/__tree
+2-2libcxx/include/map
+2-2libcxx/include/__functional/operations.h
+30-135 files

LLVM/project 4f551b5llvm/lib/Transforms/Scalar IndVarSimplify.cpp, llvm/test/Transforms/IndVarSimplify scev-update-loop-opt.ll

[IndVarSimplify] Add safety check for getTruncateExpr in genLoopLimit (#172234)

getTruncateExpr may not always return a SCEVAddRecExpr when truncating
loop bounds. Add a check to verify the result type before casting, and
bail out of the transformation if the cast would be invalid.

This prevents potential crashes from invalid casts when dealing with
complex loop bounds.

Co-authored by Michael Rowan

Resolves [#153090](https://github.com/llvm/llvm-project/issues/153090)
DeltaFile
+93-89llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
+149-0llvm/test/Transforms/IndVarSimplify/scev-update-loop-opt.ll
+242-892 files

LLVM/project d660455clang/lib/Basic/Targets AArch64.cpp AArch64.h

[AArch64][clang] Use DenseSet for target feature lookup (NFC) (#180734)

This resolves a recent AArch64 compile-time regression triggered by
#176755, which inadvertently grew the feature lookup `StringSwitch` too
large. This patch replaces the `StringSwitch` with a `DenseSet` of
target features. This is built with a new `FeatureLookupBuilder` helper,
which allows reusing all the existing cases (to avoid unintentionally
changing any of them).

Compiler-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=c9753859d19b07315c5a9a493efaa4df18db84ab&to=cb0684b602d5c741ca99b22bb3bc5f902b7a5a7e&stat=instructions:u
DeltaFile
+30-4clang/lib/Basic/Targets/AArch64.cpp
+7-0clang/lib/Basic/Targets/AArch64.h
+37-42 files

LLVM/project 728aa16mlir/include/mlir/Dialect/Tosa/IR TosaShapeOps.td, mlir/lib/Dialect/Tosa/IR TosaCanonicalizations.cpp

[mlir][tosa]: Add Unary Shape Ops folders (#180762)

* EXP2_SHAPE
* LOG2_CEIL_SHAPE
* LOG2_FLOOR_SHAPE

Signed-off-by: Udaya Ranga <udaya.ranga at arm.com>
DeltaFile
+108-11mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
+90-0mlir/test/Dialect/Tosa/constant_folding.mlir
+6-0mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
+204-113 files

LLVM/project 4688b97lld/ELF/Arch Hexagon.cpp, lld/test/ELF hexagon-tls-ie.s

[lld][Hexagon] Fix R_HEX_TPREL_11_X relocation on duplex instructions (#179860)

findMaskR11() was missing handling for duplex instructions. This caused
incorrect encoding when R_HEX_TPREL_11_X relocations were applied to
duplex instructions with large TLS offsets.

For duplex instructions, the immediate bits are located at positions
20-25 (mask 0x03f00000), not in the standard positions used for
non-duplex instructions.

This fix adds the isDuplex() check to findMaskR11() to return the
correct mask for duplex instruction encodings.

(cherry picked from commit 62d018b87a161bb2797c1ed03a482ffcdc8b162c)
DeltaFile
+35-1lld/test/ELF/hexagon-tls-ie.s
+2-0lld/ELF/Arch/Hexagon.cpp
+37-12 files

FreeBSD/ports 5671056databases/py-mysqlclient distinfo Makefile, databases/py-mysqlclient/files patch-pyproject.toml

databases/py-mysqlclient: update to 2.2.8 release (+)

Now support Python 3.14

Release notes:  https://github.com/PyMySQL/mysqlclient/releases/tag/v2.2.8
DeltaFile
+11-0databases/py-mysqlclient/files/patch-pyproject.toml
+3-3databases/py-mysqlclient/distinfo
+1-1databases/py-mysqlclient/Makefile
+15-43 files