OPNSense/tools 123de22config/26.7 build.conf

config: nice typo you got there
DeltaFile
+1-1config/26.7/build.conf
+1-11 files

LLVM/project 696f4d5llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp

[AMDGPU] Fix immediate parsing for packed types (#202417)

We should use the element, instead of the vector type, to get floating
point Semantics.The issue is not exposed in upstream yet, but still better to
be fixed.
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+1-11 files

LLVM/project d4d061bclang/lib/AST/ByteCode Interp.h, clang/test/AST/ByteCode codegen.c

[clang][bytecode] Fix right shifts greater than bitwidth (#202851)

We're not erroring in C, but we did compute the wrong result.
DeltaFile
+10-10clang/lib/AST/ByteCode/Interp.h
+3-0clang/test/AST/ByteCode/codegen.c
+13-102 files

LLVM/project 55f4ff4llvm/tools CMakeLists.txt

[cmake] Add llvm-readobj before lldb (#202715)

After #199152, following CMake error is found when building llvm-lit:

```
CMake Error at cmake/modules/AddLLVM.cmake:2816 (get_target_property):
  get_target_property() called with non-existent target "llvm-readobj".
Call Stack (most recent call first):
  cmake/modules/AddLLVM.cmake:1513 (get_host_tool_path)
  cmake/modules/AddLLVM.cmake:1556 (export_executable_symbols)
  tools/llvm-lto2/CMakeLists.txt:27 (export_executable_symbols_for_plugins)
```
Fixed by adding llvm-readobj before lldb. (Similar to
https://github.com/llvm/llvm-project/pull/201648)

Co-authored-by: himadhith <himadhith.v at ibm.com>
DeltaFile
+1-0llvm/tools/CMakeLists.txt
+1-01 files

OPNSense/ports 165c6f4opnsense/filterlog Makefile, opnsense/filterlog/files filterlog.c Makefile

opnsense/filterlog: port to libpfctl for 15.1

Also works on 14.3.  Just need to replace the write locks
in that new path in the kernel now.
DeltaFile
+12-16opnsense/filterlog/files/filterlog.c
+5-2opnsense/filterlog/Makefile
+1-1opnsense/filterlog/files/Makefile
+18-193 files

LLVM/project 3c191d6llvm/lib/ObjectYAML ELFEmitter.cpp, llvm/test/tools/yaml2obj/ELF bb-addr-map-pgo-analysis-map.yaml

[ObjectYAML] Fix yaml2obj crash when BBAddrMap entry has invalid feature (#201729)

Warn and skip the entry instead of dereferencing the Error-holding
Expected returned by Features::decode.
DeltaFile
+21-3llvm/test/tools/yaml2obj/ELF/bb-addr-map-pgo-analysis-map.yaml
+5-4llvm/lib/ObjectYAML/ELFEmitter.cpp
+26-72 files

LLVM/project d20eca1orc-rt/include CMakeLists.txt, orc-rt/include/orc-rt/sps-ci CallSPSCI.h

[orc-rt] Add initial call-function SPS CIs. (#202860)

Adds orc_rt_call_void_void and orc_rt_call_main, which can be used to
call functions with `void(void)` and `int(int, char*[])` signatures,
respectively.
DeltaFile
+116-0orc-rt/unittests/CallSPSCITest.cpp
+61-0orc-rt/lib/executor/sps-ci/CallSPSCI.cpp
+26-0orc-rt/include/orc-rt/sps-ci/CallSPSCI.h
+1-0orc-rt/include/CMakeLists.txt
+1-0orc-rt/lib/executor/CMakeLists.txt
+1-0orc-rt/unittests/CMakeLists.txt
+206-06 files

LLVM/project edd3e4fclang/include/clang/Basic BuiltinsAMDGPU.td, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics

Assisted by - Claude-sonnet:4.6
DeltaFile
+189-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+18-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+9-0clang/include/clang/Basic/BuiltinsAMDGPU.td
+216-03 files

LLVM/project 60b6529llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

Modify test run lines
DeltaFile
+154-74llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+134-64llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+134-64llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+422-2023 files

LLVM/project 6d3d523clang/test/Sema wave-reduce-builtins-validate-amdgpu.cl

Missing SEMA tests
DeltaFile
+26-0clang/test/Sema/wave-reduce-builtins-validate-amdgpu.cl
+26-01 files

LLVM/project a2315b5llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.and.ll

Promote at legalization
DeltaFile
+32-25llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+25-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+25-18llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+4-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+90-665 files

LLVM/project 2e39890llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] Support Wave Reduction for true-16 types - 2

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+87-39llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+79-35llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+166-742 files

LLVM/project dbb421fllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.and.ll llvm.amdgcn.reduce.or.ll

Use only SALU opcodes
DeltaFile
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+13-13llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+1-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+40-444 files

LLVM/project b902772llvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.min.ll

Use `REG_SEQUENCE` instead of `COPY`
Use SALU opcodes for all reductions
DeltaFile
+1-2llvm/lib/Target/AMDGPU/SIInstructions.td
+1-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+2-22 files

LLVM/project afee918llvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.umax.ll llvm.amdgcn.reduce.umin.ll

[AMDGPU] Support Wave Reduction for true-16 types - 1

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `min`, `umin`, `max`, `umax`.
Supports only the iterative stratergy, DPP is yet
to be supported.
DeltaFile
+162-53llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+134-64llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+63-29llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+63-28llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+2-1llvm/lib/Target/AMDGPU/SIInstructions.td
+0-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+424-1766 files

LLVM/project b839e57llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.xor.ll llvm.amdgcn.reduce.or.ll

[AMDGPU] Support Wave Reduction for i16 types - 3

Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+591-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+491-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+491-136llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+8-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1,581-4334 files

LLVM/project 65e7673llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.or.ll llvm.amdgcn.reduce.xor.ll

Drop unsed test prefixes
DeltaFile
+16-21llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+16-21llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+16-21llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+48-633 files

LLVM/project 8db3a2fllvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

Promote at legalization
DeltaFile
+24-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+24-15llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+6-4llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+6-2llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+60-374 files

LLVM/project ab2f87cllvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.add.ll

[AMDGPU] Support Wave Reduction for i16 types - 2

Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
DeltaFile
+642-177llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+621-173llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+2-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1,265-3503 files

LLVM/project 83c18d0llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp

Move variable decl to inner if-statement.
DeltaFile
+2-2llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+3-32 files

LLVM/project ac71616llvm/lib/Transforms/Utils LoopUtils.cpp, llvm/test/Transforms/LoopVectorize minmax-reduction-unknown-prof.ll

[LoopUtils] Mark createMinMaxOp's new select with unknown branch weights (#201750)

`createMinMaxOp()` lowers an FP min/max reduction to a freshly built
fcmp+select. That select is not derived from any existing branch, so it
carries no real profile data, and prof-verify reports a "select
annotation missing" failure. Mark the synthesized select's branch
weights as explicitly unknown when the enclosing function is profiled,
guarded by the existing profcheck-disable-metadata-fixes option.

Add a unit test covering the profiled and non-profiled cases.
DeltaFile
+156-0llvm/test/Transforms/LoopVectorize/minmax-reduction-unknown-prof.ll
+4-0llvm/lib/Transforms/Utils/LoopUtils.cpp
+160-02 files

OpenBSD/ports Q6BywCWlang/rust Makefile

   lang/rust: fix -gdb RUN_DEPENDS for following MODCLANG_VERSION

   make RUN_DEPENDS-gdb to depends on MODCLANG_VERSION (without hardcoding the version)

   noticed by tb@
VersionDeltaFile
1.249+8-4lang/rust/Makefile
+8-41 files

LLVM/project a46c5eellvm/lib/Support GlobPattern.cpp

[NFC][Support] Refactor bracket parsing in GlobPattern (#202848)

Extract BitVector from Expected before flipping to
prepare for future modifications.

Assisted-by: Gemini
DeltaFile
+8-6llvm/lib/Support/GlobPattern.cpp
+8-61 files

NetBSD/src VZiqazKdistrib/sets/lists/xbase md.amd64 md.evbarm, distrib/sets/lists/xdebug md.amd64 md.evbarm

   updates for libdrm 2.4.134.
VersionDeltaFile
1.24+2-2distrib/sets/lists/xbase/md.amd64
1.12+2-2distrib/sets/lists/xbase/md.evbarm
1.38+2-2distrib/sets/lists/xbase/md.i386
1.71+2-2distrib/sets/lists/xdebug/md.amd64
1.41+2-2distrib/sets/lists/xdebug/md.evbarm
1.68+2-2distrib/sets/lists/xdebug/md.i386
+12-122 files not shown
+16-158 files

LLVM/project 8b25b86bolt/docs profiles.md, bolt/include/bolt/Profile DataAggregator.h

rebase

Created using spr 1.3.8-beta.1
DeltaFile
+27-0bolt/unittests/Profile/DataAggregator.cpp
+15-7bolt/lib/Profile/DataAggregator.cpp
+11-6bolt/test/X86/pre-aggregated-records.s
+2-1bolt/include/bolt/Profile/DataAggregator.h
+1-1bolt/docs/profiles.md
+56-155 files

LLVM/project a3ae9a6bolt/docs profiles.md, bolt/include/bolt/Profile DataAggregator.h

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+27-0bolt/unittests/Profile/DataAggregator.cpp
+11-6bolt/test/X86/pre-aggregated-records.s
+11-2bolt/include/bolt/Profile/DataAggregator.h
+6-3bolt/lib/Profile/DataAggregator.cpp
+2-2bolt/docs/profiles.md
+57-135 files

FreeBSD/ports ad096bcshells/bash distinfo Makefile

shells/bash: Update to 5.3.15
DeltaFile
+7-1shells/bash/distinfo
+1-1shells/bash/Makefile
+8-22 files

NetBSD/xsrc OkSNQumexternal/mit/libdrm/dist xf86drm.c, external/mit/libdrm/dist/amdgpu amdgpu.h amdgpu_vamgr.c

   merge libdrm 2.4.134
VersionDeltaFile
1.6+154-0external/mit/libdrm/dist/amdgpu/amdgpu.h
1.16+87-12external/mit/libdrm/dist/include/drm/drm.h
1.35+79-7external/mit/libdrm/dist/xf86drm.c
1.6+50-3external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c
1.8+44-2external/mit/libdrm/dist/amdgpu/amdgpu_bo.c
1.21+24-7external/mit/libdrm/dist/tests/modetest/modetest.c
+438-3128 files not shown
+475-3734 files

NetBSD/xsrc G4AFnpuexternal/mit/libdrm/dist/amdgpu amdgpu_asic_id.c, external/mit/libdrm/dist/data amdgpu.ids

   initial import of libdrm-2.4.134
VersionDeltaFile
1.1.1.9+303-1external/mit/libdrm/dist/tests/util/pattern.c
1.1.1.14+300-0external/mit/libdrm/dist/include/drm/amdgpu_drm.h
1.1.1.11+230-32external/mit/libdrm/dist/include/drm/drm_fourcc.h
1.1.1.13+207-44external/mit/libdrm/dist/data/amdgpu.ids
1.1.1.4+189-5external/mit/libdrm/dist/amdgpu/amdgpu_asic_id.c
1.1.1.16+193-1external/mit/libdrm/dist/include/drm/drm_mode.h
+1,422-8341 files not shown
+2,263-21147 files

LLVM/project 51b373cclang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-vector-callingconv-llvm-ir.c riscv-vector-callingconv-llvm-ir.cpp

rebase

Created using spr 1.3.7
DeltaFile
+14-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+5-5llvm/lib/Support/GlobPattern.cpp
+8-0clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+2-2llvm/include/llvm/Support/GlobPattern.h
+2-1clang/lib/CodeGen/Targets/RISCV.cpp
+31-85 files