AMDGPU/GlobalISel: RegBankLegalize rules for sched barriers intrinsics (#203425)
Add rules for sched barrier intrinsics. Note, there are regressions due
to AGPR results being copied back to VGPR un-necessarily. That will be
addressed in a future follow-up patch.
[Bitcode] Decode small byte constants as signed values (#203408)
Decode small byte constants the same way we encode them. The bitcode
writer stores ConstantByte values as signed integers, so the reader must
rebuild them using the signed ConstantByte::get path. This has high-bit
values like b8 255 round-trip as their canonical signed form, b8 -1,
instead of tripping the APInt width assertion. This matches current i8
behavior.
Before the fix, the new test crashes in llvm-dis with: "APInt.h:
Assertion `llvm::isUIntN(BitWidth, val) && "Value is not an N-bit
unsigned value"' failed."
Bug found while investigating this PR
(https://github.com/llvm/llvm-project/pull/177908), which transitions
the LSV to emitting the byte type. Fix assisted by AI.
[MIR] Serialize/Deserialize MachineInstr::LRSplit attribute
The LRSplit MachineInstr flag is set by SplitKit on copies inserted for
live-range splitting.
Until now the flag had no MIR-text representation.
This patch fixes that so that it gets easier to reproduce/capture issues
that involves SplitKit.
Round-trip coverage in
llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir.