LLVM/project 256e742clang/lib/CodeGen QualTypeMapper.cpp, clang/test/CodeGen/X86 x86_64-empty-cxx-member-abi.cpp

[LLVMABI] Align RecordType::isEmpty() with Clang's isEmptyRecord() (#218546)

[LLVMABI] Align RecordType::isEmpty() with Clang's isEmptyRecord()

While working on empty record handling for AArch64, I stumbled across a
couple of differences between the LLVM ABI library's
`RecordType::isEmpty()` and Clang's `CodeGen::isEmptyRecord()`. Testing
verified this led to observable differences in classification when using
the ABI library.

This change updates the ABI library's empty record handling to match
Clang.

Assisted-by: Cursor / various models
DeltaFile
+128-0llvm/unittests/ABI/TypesTest.cpp
+25-11llvm/lib/ABI/Types.cpp
+35-0clang/test/CodeGen/X86/x86_64-empty-cxx-member-abi.cpp
+7-6llvm/include/llvm/ABI/Types.h
+2-3clang/lib/CodeGen/QualTypeMapper.cpp
+1-0llvm/utils/gn/secondary/llvm/unittests/ABI/BUILD.gn
+198-201 files not shown
+199-207 files

LLVM/project adf79c9llvm/include/llvm/SandboxIR Context.h, llvm/lib/SandboxIR Context.cpp

Reapply "[SandboxIR] Callback registration now allows specifying order (#221008) (#221017)

This reverts commit 89082772bed1ed16c0311b12147a96c35bb063d8.
And includes the fix.
DeltaFile
+96-0llvm/unittests/SandboxIR/SandboxIRTest.cpp
+57-16llvm/include/llvm/SandboxIR/Context.h
+33-39llvm/lib/SandboxIR/Context.cpp
+186-553 files

LLVM/project 2a7e471llvm/test/Transforms/LowerTypeTests pr37625.ll export-symver.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+16-18llvm/test/Transforms/LowerTypeTests/cfi-icall-alias.ll
+3-7llvm/test/Transforms/LowerTypeTests/export-inline.ll
+3-7llvm/test/Transforms/LowerTypeTests/export-cross-dso-cfi.ll
+2-6llvm/test/Transforms/LowerTypeTests/pr37625.ll
+2-6llvm/test/Transforms/LowerTypeTests/export-symver.ll
+2-6llvm/test/Transforms/LowerTypeTests/export-rename-local.ll
+28-507 files not shown
+38-8813 files

LLVM/project 6a20989orc-rt/include/orc-rt-internal/bedrock/sys PageSize.h, orc-rt/lib/bedrock ExecutorProcessInfo.cpp

[orc-rt] Make ExecutorProcessInfo platform-generic (#220938)

ExecutorProcessInfo was part generic, part system-specific: some of its
methods were implemented directly in its own .cpp, others only existed
as out-of-line definitions in per-OS files under lib/bedrock/sys/.

Move the system-specific pieces into free functions under orc_rt::sys
(mirroring the existing support/sys/ convention), and have
ExecutorProcessInfo consume them like any other client. The class itself
is now fully generic, with no system-specific code of its own.

No functional change, except that page-size detection (previously
hardcoded to POSIX sysconf) now goes through the same per-OS split as
the rest of ExecutorProcessInfo; a Windows implementation is left for a
follow-up.
DeltaFile
+0-133orc-rt/test/unit/bedrock/ExecutorProcessInfoTest.cpp
+12-52orc-rt/lib/bedrock/ExecutorProcessInfo.cpp
+34-26orc-rt/lib/bedrock/sys/darwin/CPUFeatures.cpp
+58-0orc-rt/test/unit/bedrock/sys/TargetTripleTest.cpp
+38-0orc-rt/lib/bedrock/sys/posix/PageSize.cpp
+29-0orc-rt/include/orc-rt-internal/bedrock/sys/PageSize.h
+171-21113 files not shown
+289-26719 files

LLVM/project fefa6aelldb/test lldbflakes.py, lldb/test/API lit.cfg.py lldbtest.py

[lldb][test] Rerun tests that hit a known flaky failure (#221006)

macOS 26.3 denies debugserver permission to attach when too many debug
sessions start at once, which surfaces as a test failing with "process
exited with status -1". The denial is intermittent and a rerun normally
gets through.

Gate the rerun on a list of known flake signatures rather than retrying
every failure, because a blanket retry masks real bugs. Adding to that
list is a last resort for defects outside LLDB's control.
DeltaFile
+40-0lldb/test/lldbflakes.py
+7-0lldb/test/API/lldbtest.py
+5-1lldb/test/Shell/helper/toolchain.py
+1-0lldb/test/Shell/lit.cfg.py
+1-0lldb/test/API/lit.cfg.py
+54-15 files

LLVM/project c71cf14mlir/lib/Interfaces/Utils InferIntRangeCommon.cpp

[MLIR] Move inferred remainder bounds into results (NFC) (#221081)

Move locally computed signed and unsigned remainder bounds into their
final range accumulators when the special-case bounds are selected.

Found by Coverity.

Assisted-by: Codex
DeltaFile
+4-4mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
+4-41 files

LLVM/project b43d3c3llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Carry null operands and intrinsic names across when promoting to VGPRs
DeltaFile
+145-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+42-2llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+187-22 files

LLVM/project e99e97dllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Count the intrinsics that really become calls when refusing promotion
DeltaFile
+81-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+30-9llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+111-92 files

LLVM/project ae36e10llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-private-object-vgprs.mir

Propagate object liveness to every changed successor, not only back edges
DeltaFile
+56-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-private-object-vgprs.mir
+14-4llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+70-42 files

LLVM/project 9f90875llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp AMDGPUMemoryUtils.h, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Promote private objects into the VGPR address space via flag
DeltaFile
+279-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+138-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+1-35llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+23-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+19-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+460-395 files

LLVM/project 8bd7ecdllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-promote.ll

Refuse promotion only when the object is live across a call
DeltaFile
+183-4llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-promote.ll
+117-15llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+300-192 files

LLVM/project ba81031llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-divergent.ll

Treat a sub-dword VGPR-memory load as divergent too
DeltaFile
+83-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-divergent.ll
+3-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+86-12 files

LLVM/project c5475c1llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-budget.ll

Diagnose an object that does not fit the function's register budget
DeltaFile
+82-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-budget.ll
+36-13llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+118-132 files

LLVM/project 0e7882ellvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-allocate.ll as-vgpr-across-call.ll

Do not add a second lifetime start when allocating VGPRs again
DeltaFile
+21-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+17-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+0-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+38-43 files

LLVM/project 9044d4bllvm/unittests/Target/AMDGPU VGPRAsMemory.cpp

Pin the width guard that keeps sub-dword accesses out of aliasing decisions
DeltaFile
+66-0llvm/unittests/Target/AMDGPU/VGPRAsMemory.cpp
+66-01 files

LLVM/project 019fe44llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-across-call.ll as-vgpr-private-object-vgprs.mir

Allocate and reserve registers for address space 13 objects
DeltaFile
+340-0llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+178-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-object-regalloc.ll
+140-12llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+133-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+106-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-private-object-vgprs.mir
+80-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+977-1218 files not shown
+1,280-2324 files

LLVM/project 5f012fbllvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-asm-clobber.ll

Diagnose inline asm that clobbers a VGPR-memory object's registers
DeltaFile
+93-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-asm-clobber.ll
+31-5llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+124-52 files

LLVM/project cb5850dllvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits-encoding.ll as-vgpr-bits.ll

Regenerate the sub-dword expectations for the M0 setup change
DeltaFile
+38-54llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits-control-flow.ll
+30-49llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits.ll
+1-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits-encoding.ll
+69-1043 files

LLVM/project 6ec5118llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-index-demanded-bits.ll

Regenerate the demanded-bits expectations for the gfx1250 entry sequence
DeltaFile
+24-16llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-index-demanded-bits.ll
+24-161 files

LLVM/project e88b9a5llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp

Document the sub-dword access rules for the VGPR address space
DeltaFile
+14-12llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+7-0llvm/docs/AMDGPUUsage.rst
+21-122 files

LLVM/project e0cd146llvm/lib/Target/AMDGPU AMDGPULowerIdxOps.cpp SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-lower-idx-ops.mir as-vgpr-verifier.mir

Check the encodings of the sub-dword VGPR-memory accesses
DeltaFile
+71-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits-encoding.ll
+0-40llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-verifier-m0.mir
+32-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-verifier.mir
+8-18llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+8-8llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-lower-idx-ops.mir
+2-10llvm/lib/Target/AMDGPU/AMDGPULowerIdxOps.cpp
+121-761 files not shown
+125-797 files

LLVM/project b28072cllvm/lib/Target/AMDGPU SIInstructions.td SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-lower-idx-ops.mir

Inherit the M0 operand when expanding the sub-dword VGPR-memory pseudos
DeltaFile
+21-4llvm/lib/Target/AMDGPU/AMDGPULowerIdxOps.cpp
+12-11llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-lower-idx-ops.mir
+1-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+0-2llvm/lib/Target/AMDGPU/SIInstructions.td
+34-194 files

LLVM/project 4e119e8llvm/lib/Target/AMDGPU SIInstructions.td, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-verifier.mir as-vgpr-lower-idx-ops.mir

Adopt subarch triples in the sub-dword tests and drop the redundant VALU
DeltaFile
+6-6llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits.ll
+4-4llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits-control-flow.ll
+2-2llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits-encoding.ll
+0-2llvm/lib/Target/AMDGPU/SIInstructions.td
+1-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-verifier.mir
+1-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-lower-idx-ops.mir
+14-166 files

LLVM/project 18f2aeellvm/lib/Target/AMDGPU SIInstructions.td

Simplify the sub-dword VGPR-memory pseudo definitions
DeltaFile
+25-32llvm/lib/Target/AMDGPU/SIInstructions.td
+25-321 files

LLVM/project fadc24ellvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits.ll

Also build the sub-dword VGPR-memory tests for wave64
DeltaFile
+8-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits.ll
+8-01 files

LLVM/project 6937bddllvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits.ll as-vgpr-index-demanded-bits.ll

Fix tests
DeltaFile
+105-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-index-demanded-bits.ll
+10-5llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits.ll
+115-52 files

LLVM/project c986504llvm/lib/Target/AMDGPU SIInstrInfo.cpp

Do not describe sub-dword VGPR-memory accesses by index and width
DeltaFile
+7-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+7-01 files

LLVM/project 59df807llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-bits-control-flow.ll

Test sub-dword VGPR-memory accesses across control flow
DeltaFile
+316-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-bits-control-flow.ll
+316-01 files

LLVM/project 15b6afdllvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-verifier-m0.mir

Cover the remaining VGPR-memory operand invariants
DeltaFile
+26-12llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-verifier-m0.mir
+26-121 files

LLVM/project cdd2b57llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULowerIdxOps.cpp

NFC: track the downstream implementation more closely
DeltaFile
+21-14llvm/lib/Target/AMDGPU/AMDGPULowerIdxOps.cpp
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+22-152 files