OPNSense/core 1b601a1src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms dialogSNatRule.xml, src/opnsense/mvc/app/library/OPNsense/Firewall SNatRule.php

Firewall: NAT: Source NAT: fix port alias and well known port usage in target_port (#10793)

* Firewall: NAT: Source NAT: fix port alias usage in target_port

* Add use statements for BooleanField and ProtocolField
DeltaFile
+22-6src/opnsense/mvc/app/library/OPNsense/Firewall/SNatRule.php
+12-1src/opnsense/mvc/app/models/OPNsense/Firewall/Filter.php
+7-2src/opnsense/mvc/app/models/OPNsense/Firewall/FieldTypes/SourceNatRuleField.php
+1-1src/opnsense/mvc/app/controllers/OPNsense/Firewall/forms/dialogSNatRule.xml
+2-0src/opnsense/mvc/app/models/OPNsense/Firewall/Filter.xml
+44-105 files

LLVM/project e1c2a9cclang/docs ReleaseNotes.md, clang/lib/CodeGen CGExprComplex.cpp

[PowerPC][Clang] fix IEEE f128 complex div/mul use IBM f128 libcalls on powerpc (#218151)

fixes https://github.com/llvm/llvm-project/issues/216820

Previously the IBM f128 libcall was used also for IEEE f128 complex
mul/div.
DeltaFile
+31-3clang/test/CodeGen/fp128_complex.c
+8-4clang/lib/CodeGen/CGExprComplex.cpp
+1-0clang/docs/ReleaseNotes.md
+40-73 files

LLVM/project 55d3cebclang/lib/AST/ByteCode Interp.h Context.cpp, clang/unittests/AST/ByteCode Pointer.cpp

[clang][bytecode] Add `StringPointer` (#216736)

This is a new pointer type that points to a string literal. We do not
allocate any memory for it but we _can_ read from it.

A `StringPointer` only consists of a `StringLiteral` (or rather a
"Base", which can also be a `PredefinedExpr`), and an ID which is only
increased on `GetStringPtr` ops. This way we can know whether two
literals have been created via the same evaluation. This is needed for
the "overlapping string literals" diagnostics, particularly in the loop
case:

```c++
constexpr bool different_in_loop(bool b = false) {
  if (b) return false;

  const char *p[2] = {};
  for (const char *&r : p)
    r = "hello";

    [4 lines not shown]
DeltaFile
+95-55clang/lib/AST/ByteCode/InterpBuiltin.cpp
+138-8clang/lib/AST/ByteCode/Pointer.h
+83-9clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+82-0clang/unittests/AST/ByteCode/Pointer.cpp
+55-12clang/lib/AST/ByteCode/Context.cpp
+42-22clang/lib/AST/ByteCode/Interp.h
+495-10615 files not shown
+637-22121 files

FreeBSD/ports 6a6190awww/phpgroupware Makefile

www/phpgroupware: Deprecate, upstream is dead

The GNU Project has decommissioned the package (Savannah reports
"Development Status: 9 - Decommissioned"), the last release on
SourceForge dates back to 2010, git.savannah.gnu.org no longer carries
the repository, and no active fork exists.  The phpgroupware.org domain
has lapsed and now redirects to an unrelated site, so point WWW at the
Savannah project page instead.
DeltaFile
+4-1www/phpgroupware/Makefile
+4-11 files

FreeBSD/src 9186704sys/arm64/include armreg.h

arm64: Fix the indentation of ID_AA64ISAR2_EL1

Some ID_AA64ISAR2_EL1 fields values are incorrectly indented. Values
have an extra space before the macro to make scanning for them easier.

Add this extra space to the two fields that were missing it.

Sponsored by:   Arm Ltd
DeltaFile
+4-4sys/arm64/include/armreg.h
+4-41 files

FreeBSD/src 137ce1esys/arm64/include armreg.h

arm64: Use decimal values for op and CR macros

Using hex here breaks the instruction generated by MRS_REG_ALT_NAME.
Switch to a decimal value.

Sponsored by:   Arm Ltd
DeltaFile
+15-15sys/arm64/include/armreg.h
+15-151 files

NetBSD/pkgsrc-wip f6224bdmodular-xorg-server distinfo options.mk, modular-xorg-server/patches patch-include_meson.build patch-include_Xserver.d

modular-xorg-server: improve dtrace option on NetBSD

still doesn't build
DeltaFile
+13-0modular-xorg-server/patches/patch-include_meson.build
+13-0modular-xorg-server/patches/patch-include_Xserver.d
+13-0modular-xorg-server/patches/patch-dix_meson.build
+4-5modular-xorg-server/options.mk
+3-0modular-xorg-server/distinfo
+46-55 files

NetBSD/pkgsrc-wip 4b37681. TODO

TODO: + llama.cpp-0.3.0.
DeltaFile
+1-0TODO
+1-01 files

NetBSD/pkgsrc 5UNpQ2Pdoc TODO

   doc/TODO: + ggml-0.22.0.
VersionDeltaFile
1.27820+2-1doc/TODO
+2-11 files

LLVM/project 91033f9llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp

[AArch64][GISel] Allow import of DAG FCVT/CVTF patterns using fixedpoint immediate (#215812)

Currently, fp_to_int(fmul) patterns only work for DAG, this is due to
the use of fixedpoint immediate type which GISel could not import.

Add GlobalISel matchers for fixed-point immediates, allowing these
patterns to be imported and used during instruction selection.

I originally added these to allow fp_to_int(fmul) fold DAG patterns from
this [PR](https://github.com/llvm/llvm-project/pull/210987) to import,
but this also enables fdiv(int_to_fmul) folds to work in GISel
DeltaFile
+376-1,106llvm/test/CodeGen/AArch64/fcvt-fixed.ll
+61-28llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+35-22llvm/lib/Target/AArch64/AArch64InstrInfo.td
+472-1,1563 files

LLVM/project b284741llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 inline-asm-named-z-reg-constraints.ll

[AArch64] Reject non-scalable types in named Z-register constraints (#217551)

LLVM currently handles typed named Z-register constraints
inconsistently. Depending on the operand type and whether SVE is
available, compilation may succeed, crash, or trigger an assertion.

Reject typed Z-register operands when SVE or streaming SVE is
unavailable, and reject non-scalable operand types. Preserve the
existing behavior for untyped Z-register clobbers.

Fixes #169027
DeltaFile
+382-0llvm/test/CodeGen/AArch64/inline-asm-named-z-reg-constraints.ll
+33-8llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+415-82 files

LLVM/project 68f2756llvm/test/CodeGen/AArch64 atomic-vector-store.ll

[AArch64][Atomics] Add test file for testing <1xTy> store atomics (#216028)

Currently, there exists no testing for <1xTy> store atomic.
These used to throw a widening legalization error but was fixed due to
this [PR](https://github.com/llvm/llvm-project/pull/197618)
Add these tests for AArch64 to ensure regression does not occur.

Note: Currently <1xi64> has a instruction selection issue and this is
why it has not been added.
A future patch will fix this case.
DeltaFile
+47-0llvm/test/CodeGen/AArch64/atomic-vector-store.ll
+47-01 files

LLVM/project 28bb07fllvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 vecreduce-add-vector.ll

[AArch64][SelectionDAG] Optimise ADDLV reductions inserted into zero vector (#215814)

{U/S}ADDLV instruction inserts result into lane 0 and clear unused lanes
to zero, so we can just return the result as a vector without extra
insert into a zeroed vector.
Add patterns that recognize the redundant zero vector insert and remove
it.
DeltaFile
+421-0llvm/test/CodeGen/AArch64/vecreduce-add-vector.ll
+53-12llvm/lib/Target/AArch64/AArch64InstrInfo.td
+474-122 files

FreeNAS/freenas 7363e93src/middlewared/middlewared/plugins/failover_ event.py, src/middlewared/middlewared/plugins/iscsi_ iscsi_global.py alua.py

Add middleware support for LIO ALUA HA

Wire up the middleware side of LIO ALUA high-availability: load
lio_ha.ko with per-node addresses on service start, manage ALUA
state across failover events, clean up STANDBY configfs on pool
export, and add pre-flight validation that targets have static
initiator ACLs before ALUA can be enabled.

For each target, create a portal-less phantom TPG carrying the peer
node's controller group so that a single RTPG response from any
connected port lists both ALUA groups.  Write tpgt_N/rtpi explicitly
before enable so that relative target port IDs in RTPG match the
tag formula (portal.tag on Node A, portal.tag + 32000 on Node B)
rather than being auto-assigned sequentially by the kernel.

ALUA group states are driven by role and ha_state:

  MASTER  + synced        local=OPTIMIZED     remote=NONOPTIMIZED
  MASTER  + connected     local=OPTIMIZED     remote=TRANSITIONING

    [4 lines not shown]
DeltaFile
+494-128src/middlewared/middlewared/utils/lio/config.py
+214-2src/middlewared/middlewared/plugins/iscsi_/lio.py
+62-9src/middlewared/middlewared/plugins/iscsi_/alua.py
+37-21src/middlewared/middlewared/plugins/iscsi_/iscsi_global.py
+33-21src/middlewared/middlewared/plugins/failover_/event.py
+38-0src/middlewared/middlewared/utils/iscsi/constants.py
+878-1815 files not shown
+950-18811 files

OPNSense/core 3114792src/opnsense/mvc/app/views/layout_partials form_input_tr.volt

revisit
DeltaFile
+5-5src/opnsense/mvc/app/views/layout_partials/form_input_tr.volt
+5-51 files

NetBSD/src 4kgNje1distrib/sets/lists/base mi, external/cddl/osnet/lib/libdtrace Makefile

   install psinfo.d again, now that it's fixed
VersionDeltaFile
1.37+2-2external/cddl/osnet/lib/libdtrace/Makefile
1.1390+2-2distrib/sets/lists/base/mi
+4-42 files

NetBSD/src 43G3ywGexternal/cddl/osnet/lib/libdtrace psinfo.d

   psinfo.d needs /dev/ksyms

   Mark it as such. From RVP, inspired by FreeBSD, in PR 58630.
VersionDeltaFile
1.7+3-1external/cddl/osnet/lib/libdtrace/psinfo.d
+3-11 files

LLVM/project 4b884dallvm/lib/Target/AMDGPU SIPeepholeSDWA.cpp, llvm/test/CodeGen/AMDGPU sdwa-peephole-movrels.mir sdwa-peephole-movrels.ll

[AMDGPU] Reject SDWA forms the subtarget cannot encode (#218592)

isConvertibleToSDWA only checked the base opcode, so it could still fold
into an SDWA form the target cannot encode and crash later
DeltaFile
+72-0llvm/test/CodeGen/AMDGPU/sdwa-peephole-movrels.ll
+40-0llvm/test/CodeGen/AMDGPU/sdwa-peephole-movrels.mir
+2-1llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+114-13 files

FreeBSD/ports 1bf844ewww/phalcon Makefile distinfo

www/phalcon: update to 5.20.1.
DeltaFile
+3-3www/phalcon/distinfo
+1-1www/phalcon/Makefile
+4-42 files

LLVM/project 79aaa63flang/test/Driver tco-test-gen.fir, mlir/test/Conversion/GPUCommon memory-attrbution.mlir

minor test fixes
DeltaFile
+0-2flang/test/Driver/tco-test-gen.fir
+1-1mlir/test/Dialect/X86/AMX/legalize-for-llvm.mlir
+1-1mlir/test/Conversion/GPUToLLVMSPV/gpu-to-llvm-spv.mlir
+1-1mlir/test/Conversion/GPUCommon/memory-attrbution.mlir
+3-54 files

LLVM/project 057a04fflang/test/Fir convert-to-llvm-openmp-and-fir.fir, mlir/test/Conversion/MemRefToLLVM convert-static-memref-ops.mlir convert-dynamic-memref-ops.mlir

[mlir] Build llvm.mlir.constant attributes from the result type

Many conversion patterns created `llvm.mlir.constant` with a value attribute
whose type does not match the result type. The most common case was pairing an
`index`-typed attribute with the converted index type:

  llvm.mlir.constant(1 : index) : i64

but there were also plain width and signedness mismatches, e.g. NVGPU's
`makeI64Const` built `i64` constants from `i32` attributes, and the NVVM
`fdiv` expansion used `ui32` attributes on `i32` values.

Translation to LLVM IR ignores the attribute type and uses the result type, so
the emitted IR was correct, but the attribute type is meaningless in this state
and anything that reads it back sees the wrong type. Derive the attribute from
the result type in every case; where the result is the converted index type the
existing `createIndexAttrConstant` helper does this already, so use it. In
`ArithToLLVM`, retype the value attribute when the type converter maps `index`
to a different integer type, and fail the match rather than reinterpret a

    [5 lines not shown]
DeltaFile
+63-63mlir/test/Target/LLVMIR/llvmir.mlir
+58-58mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
+55-55mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
+49-43flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
+45-45mlir/test/Conversion/MemRefToLLVM/convert-dynamic-memref-ops.mlir
+43-43mlir/test/Conversion/MemRefToLLVM/convert-static-memref-ops.mlir
+313-307105 files not shown
+962-892111 files

LLVM/project d767b55flang/lib/Optimizer/CodeGen CodeGen.cpp, flang/test/Fir global-initialization.fir

[flang][CodeGen] Fix element type of folded insert_on_range initializers (#218587)

`GlobalOpConversion` folds a full-range `fir.insert_on_range` into a
dense constant. When the inserted value comes from a `fir.convert`, the
fold reached through the conversion and built the dense attribute from
the type of the *source* constant. For a `logical(4)` array initialized
to `.true.` this produced

```
llvm.mlir.constant(dense<true> : vector<32768xi1>) : !llvm.array<32768 x i32>
```

where the attribute element type `i1` disagrees with the result element
type `i32`. Translation to LLVM IR ignores the attribute type and uses
the result type, so the emitted global is still correct today, but the
IR is malformed and any consumer that trusts the attribute type sees the
wrong element width.

Build the dense attribute from the converted element type instead. A

    [9 lines not shown]
DeltaFile
+34-18flang/lib/Optimizer/CodeGen/CodeGen.cpp
+16-1flang/test/Fir/global-initialization.fir
+50-192 files

LLVM/project b3ab190clang/include/clang/AST ASTContext.h, clang/lib/AST ASTContext.cpp

[clang][AST] Clean up AST element count functions (#215456)

Make them static and clarify documentation.
DeltaFile
+5-7clang/lib/AST/ASTContext.cpp
+7-5clang/include/clang/AST/ASTContext.h
+12-122 files

FreeNAS/freenas 2d7807fsrc/middlewared/middlewared/alembic/versions/26.0 2026-08-24_12-00_remove_tier_oneshot_alerts.py, src/middlewared/middlewared/alert/source zfs_tier.py

Make ZFS tier alerts normal alerts

(cherry picked from commit a93b7b04ae06a2fe60a31bad3588d8d50a810971)
DeltaFile
+128-214src/middlewared/middlewared/alert/source/zfs_tier.py
+324-0tests/api2/zfs_tier/test_alerts.py
+26-0src/middlewared/middlewared/alembic/versions/26.0/2026-08-24_12-00_remove_tier_oneshot_alerts.py
+4-1src/middlewared/middlewared/plugins/zfs/tier.py
+482-2154 files

LLVM/project 864a266flang/lib/Optimizer/CodeGen CodeGen.cpp, flang/test/Fir tbaa.fir convert-to-llvm.fir

[flang][CodeGen] Use a signless attribute for the addendum flag masks (#218606)

The descriptor addendum flag masks were built as `ui8` attributes but
attached to `i8` constants:

```
llvm.mlir.constant(254 : ui8) : i8
```

The LLVM dialect only models signless integers, so the attribute type
and the result type disagree. Use the signless `i8` type for the
attribute as well; the bit patterns are unchanged, only their printed
form is (`254 : ui8` becomes `-2 : i8`).

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+2-2flang/test/Fir/convert-to-llvm.fir
+2-2flang/lib/Optimizer/CodeGen/CodeGen.cpp
+1-1flang/test/Fir/tbaa.fir
+5-53 files

LLVM/project c7b266dclang/lib/StaticAnalyzer/Core ExprEngine.cpp CoreEngine.cpp

[analyzer] Return null from makeNode on PosteriorlyOverconstrained (#218472)

Previously node creation methods like `ExprEngine::makeNode` had two
ways to signal failure: they returned `nullptr` when they would have
reached an already existing node (through a second path) and created a
sink node (returning it) when the state was `PosteriorlyOverconstrained`
(i.e. self-contradictory, not corresponding to a real possibility).

Both kinds of failures need to be handled in the same way (return
early), so this commit ensures that `makeNode` returns `nullptr` after
creating a node with `PosteriorlyOverconstrained` state. (It still
creates the nodes with the `PosteriorlyOverconstrained` state to ensure
that those infeasible execution paths end in sinks.)

For motivation and further plans see the discussion at:

https://discourse.llvm.org/t/simplifying-failure-modes-in-explodednode-creation/91542/5

As node creation could already return `nullptr` when "caching out"

    [11 lines not shown]
DeltaFile
+2-4clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+3-3clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
+5-72 files

LLVM/project e31e714clang/test/CodeGen/LoongArch/lasx builtin.c builtin-alias.c, llvm/docs/DirectX DXContainer.md DXContainer.rst

Merge branch 'main' into users/adams381/llvmabi-union-empty-member-storage
DeltaFile
+733-733clang/test/CodeGen/LoongArch/lasx/builtin.c
+733-733clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+0-1,275llvm/docs/GlobalISel/GenericOpcode.rst
+1,116-0llvm/docs/GlobalISel/GenericOpcode.md
+0-1,061llvm/docs/DirectX/DXContainer.rst
+1,060-0llvm/docs/DirectX/DXContainer.md
+3,642-3,802593 files not shown
+23,817-15,204599 files

LLVM/project 426eff6clang/lib/AST/ByteCode Descriptor.cpp

[clang][bytecode] No primitive types need their ctor function called (#218666)

Both Pointer and MemberPointer are fine with being all-zero initialized.

I've left the code for this in the file for now though, in case I need
it later.
DeltaFile
+65-54clang/lib/AST/ByteCode/Descriptor.cpp
+65-541 files

LLVM/project d8e3a21clang/test/CIR/CodeGen pack-indexing.cpp cxx-rewritten-binary-operator.cpp

[CIR] Regenerate CHECK lines for seventeen callconv opt-out tests (#218293)

After #214742 (empty class) and #215117 (`_Complex` and other float
formats), seventeen tests carried `-fno-clangir-call-conv-lowering` even
though the pass refuses nothing in them. They compile clean with the
flag gone. Their CHECK lines still described the un-lowered signature,
so they failed on the coercion rather than on a missing feature.

Update the expectations and drop the opt-out.

Assisted by: Cursor / claude-opus-5
DeltaFile
+285-316clang/test/CIR/CodeGen/cleanup-conditional.cpp
+147-44clang/test/CIR/CodeGen/complex.cpp
+101-46clang/test/CIR/CodeGen/three-way-cmp.cpp
+28-22clang/test/CIR/CodeGen/nrvo.cpp
+28-19clang/test/CIR/CodeGen/cxx-rewritten-binary-operator.cpp
+29-14clang/test/CIR/CodeGen/pack-indexing.cpp
+618-46111 files not shown
+701-57017 files

FreeBSD/ports a0f3215net/rustconn Makefile Makefile.crates

net/rustconn: Update to 0.20.8

ChangeLog:      https://github.com/totoshko88/RustConn/releases/tag/v0.20.8
Reported by:    "github-actions[bot]" <notifications at github.com>
DeltaFile
+9-9net/rustconn/distinfo
+3-3net/rustconn/Makefile.crates
+1-1net/rustconn/Makefile
+13-133 files