LLVM/project a2f9da5lldb/source/Host/windows ConnectionConPTYWindows.cpp, lldb/source/Plugins/Process/Windows/Common ProcessWindows.cpp

[lldb][windows] fix race condition in ConPTY on process exit (#194631)
DeltaFile
+8-3lldb/source/Host/windows/ConnectionConPTYWindows.cpp
+2-1lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
+10-42 files

LLVM/project 0052113clang/include/clang/Basic DiagnosticDriverKinds.td, clang/lib/Driver/ToolChains Clang.cpp

[SYCL][Driver] Set -std=c++17 as default for SYCL compilations (#194014)

This PR ensures SYCL compilations default to C++17 when no explicit
standard is specified, and validates that user-provided standards meet
SYCL's C++17 minimum requirement. It also fixes Windows MSVC compilation
by enabling -fms-extensions for SYCL device code.
DeltaFile
+67-0clang/test/Driver/sycl-std-default.cpp
+41-3clang/lib/Driver/ToolChains/Clang.cpp
+2-0clang/include/clang/Basic/DiagnosticDriverKinds.td
+110-33 files

LLVM/project d089e73llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port f5b6e4fc2022 (#194645)
DeltaFile
+0-1llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+0-11 files

LLVM/project bfaab0eclang/test/CodeGen/AArch64/neon intrinsics.c

[clang][cir][nfc] Add missing comment (#194644)
DeltaFile
+7-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+7-01 files

LLVM/project 268bac6flang/include/flang/Parser openmp-utils.h, flang/lib/Parser openmp-utils.cpp

[flang][OpenMP] Move implementation detail from header to source, NFC (#194638)
DeltaFile
+0-22flang/include/flang/Parser/openmp-utils.h
+22-0flang/lib/Parser/openmp-utils.cpp
+22-222 files

LLVM/project 5b82a26llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUMCExpr.cpp

[AMDGPU][NFC] Remove redundant Args.size() assertions from AMDGPUMCExpr (#194488)

Remove redundant `Args.size()` assertions from `AMDGPUMCExpr` evaluate
functions (`evaluateExtraSGPRs`, `evaluateTotalNumVGPR`,
`evaluateAlignTo`, `evaluateOccupancy`).

These assertions are redundant with the `zip_equal` size checking
performed in the `evaluateMCExprs` helper function introduced in
#193859.

---

*This PR was developed with AI assistance (GitHub Copilot).*
DeltaFile
+0-8llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
+0-81 files

LLVM/project 77cfc55mlir/utils/vscode package-lock.json package.json

[MLIR] Update minimatch dependency in VSCode plugin, resolving security alerts (#188613)
DeltaFile
+1,509-924mlir/utils/vscode/package-lock.json
+1-1mlir/utils/vscode/package.json
+1,510-9252 files

LLVM/project cf2708fflang/include/flang/Parser openmp-utils.h, flang/lib/Parser openmp-utils.cpp

[flang][OpenMP] Move implementation detail from header to source, NFC
DeltaFile
+0-22flang/include/flang/Parser/openmp-utils.h
+22-0flang/lib/Parser/openmp-utils.cpp
+22-222 files

LLVM/project 61d795cllvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP][NFC]Cache IsExternallyUsed by Value in cost computation

Same V is commonly seen in multiple TEs (shared scalars), and the
expensive part of IsExternallyUsed walks V->users() with multiple
match() pattern checks plus per-user getTreeEntries lookups - all
V-only-dependent. Split out the V-dependent body and memoize by
Value pointer, leaving the TE-specific copyable check at the call
site. DeletedNodes is read-only during the cost loop, so caching
is safe.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194637
DeltaFile
+42-33llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+42-331 files

LLVM/project b0f3cd1lldb/source/Plugins/Process/Windows/Common ProcessWindows.cpp

[lldb][windows] fix a race condition in IO reader thread (#194422)
DeltaFile
+34-0lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
+34-01 files

LLVM/project 56a1e51lld/ELF SyntheticSections.cpp Relocations.cpp, lld/ELF/Arch AArch64.cpp

[PAC][lld] Do not emit AUTH relocs against undef weak non-preemptible symbols

Undefined weak non-preemptible symbols should be statically resolved to
the addend value and not signed. Previously, a dynamic relocation
against such symbols was emitted, which is not a correct behavior.

See also docs: https://github.com/ARM-software/abi-aa/pull/391

Resolves #173296
DeltaFile
+39-0lld/test/ELF/aarch64-reloc-pauth-undef-weak-dso.s
+38-0lld/test/ELF/aarch64-reloc-pauth-undef-weak-pie.s
+38-0lld/test/ELF/aarch64-reloc-pauth-undef-weak.s
+16-5lld/ELF/Arch/AArch64.cpp
+15-5lld/ELF/SyntheticSections.cpp
+13-6lld/ELF/Relocations.cpp
+159-161 files not shown
+161-177 files

LLVM/project da0455allvm/test/Transforms/PhaseOrdering/X86 vector-reductions-expanded.ll

[PhaseOrdering][X86] vector-reductions-expanded.ll - use passes list instead of piped opt stages (#194608)

Cleanup to make it easier to regenerate checks for #194473
DeltaFile
+1-1llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
+1-11 files

LLVM/project e6e9e1fllvm/docs KeyInstructionsDebugInfo.md InstrRefDebugInfo.md

[Docs] Fixes indents for InstrRefDebugInfo and KeyInstructionsDebugInfo (#194532)

This distinguishes the doc title from the headers.

Fixes navigation indents for Furo theme update (see
https://github.com/llvm/llvm-project/pull/184440).
DeltaFile
+11-11llvm/docs/KeyInstructionsDebugInfo.md
+7-7llvm/docs/InstrRefDebugInfo.md
+18-182 files

LLVM/project 74781cflldb/test/API/functionalities/multi-breakpoint TestMultiBreakpoint.py

[lldb] Disable gdbremote test on windows (#194627)

This is causing bot failures.
DeltaFile
+1-0lldb/test/API/functionalities/multi-breakpoint/TestMultiBreakpoint.py
+1-01 files

LLVM/project 367d140llvm/test/TableGen directive2.td directive1.td, llvm/utils/TableGen/Basic DirectiveEmitter.cpp

[TableGen] Emit constexpr versions of some directive/clause functions

A variant of https://github.com/llvm/llvm-project/pull/176253 with a
change to reduce compile-time impact.

Since "llvm_unreachable" is actually allowed in constexpr functions,
simply emit the bodies of the selected functions in the header file.

In the previous PR the `isAllowedClauseForDirective` function was made
constexpr, but since it was very long it had a significant impact on
compilation time. In this PR that function is no longer constexpr.
DeltaFile
+26-27llvm/test/TableGen/directive2.td
+26-27llvm/test/TableGen/directive1.td
+21-27llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
+73-813 files

LLVM/project ca27dc2llvm/lib/Target/SPIRV SPIRVLegalizePointerCast.cpp, llvm/test/CodeGen/SPIRV/pointers load-store-matrix-in-struct.ll

[SPIR-V] Matrix in struct pointer legalization (#193073)

When looking to load an object at the start of a struct, the types do
not always match exactly. When we have an HLSL matrix the type in the
load will not match the type in memory. We need to improve the pointer
legalization pass to look for any "compatible" type at the start of an
aggragate.

A compatible are two types that the pass knows know to convert from one
to another.

This involves a refactoring of the code to make the check more general.

Assisted-by: Gemini


<!-- branch-stack-start -->

<!-- branch-stack-end -->
DeltaFile
+119-101llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
+57-0llvm/test/CodeGen/SPIRV/pointers/load-store-matrix-in-struct.ll
+176-1012 files

LLVM/project e459ce5llvm/lib/Target/PowerPC PPCRegisterInfo.td PPCMacroFusion.def

Revert "[PowerPC] Enable using HwMode for instructions (#191051)" (#194464)

This reverts commit 2a83068537786696d4950ce694e7d34480631f48.

It causes test suite failures in the 7zip benchmark.
DeltaFile
+13-8llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+3-3llvm/lib/Target/PowerPC/PPCMacroFusion.def
+2-2llvm/lib/Target/PowerPC/PPCRegisterClasses.td
+4-0llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
+2-2llvm/lib/Target/PowerPC/PPCInstrInfo.td
+2-1llvm/lib/Target/PowerPC/P10InstrResources.td
+26-162 files not shown
+30-178 files

LLVM/project 4e030aellvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP][NFC]Cache MightBeIgnored result in gather-shuffle analysis

Each V in VL is queried up to 3 times for MightBeIgnored (direct +
NeighborMightBeIgnored from both neighbors), and the underlying
areAllUsersVectorized walks the instruction's user list. Memoize per
Value pointer to avoid the redundant walks.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194619
DeltaFile
+13-4llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+13-41 files

LLVM/project a2409e0libc/include ucontext.h.def CMakeLists.txt, libc/include/sys ucontext.h.def ucontext.h

[libc][NFC] Move sys/ucontext.h to YAML generation (#194573)

Renamed sys/ucontext.h to sys/ucontext.h.def and created a corresponding
sys/ucontext.yaml, following the pattern used by sys/prctl. Updated
CMakeLists.txt to use add_header_macro.

Also removed the orphaned top-level ucontext.h.def which was never
referenced by ucontext.yaml.
DeltaFile
+16-0libc/include/sys/ucontext.h.def
+0-16libc/include/ucontext.h.def
+0-14libc/include/sys/ucontext.h
+5-3libc/include/CMakeLists.txt
+4-0libc/include/sys/ucontext.yaml
+25-335 files

LLVM/project cd95096clang/test/Driver modules-driver-import-std.cpp

[clang][modules-driver] Further constrain import-std test (#194604)

The root cause for the failing test was found in
https://github.com/llvm/llvm-project/pull/194475#issuecomment-4335023585.
The test uses `--target=x86_64-linux-gnu` which is only available with
`-DLLVM_TARGETS_TO_BUILD=all` or on native x86 targets.
DeltaFile
+1-2clang/test/Driver/modules-driver-import-std.cpp
+1-21 files

LLVM/project b48aa05llvm/include/llvm/Support IOSandbox.h

[llvm] Mark IOSandbox::ScopedSetting nodiscard and maybe_unused (#194602)

The goal is to have the same attributes on ScopedSetting regardless if
this cmake setting is enabled or not.

Both of these should have nodiscard and maybe_unused attributes.
DeltaFile
+2-2llvm/include/llvm/Support/IOSandbox.h
+2-21 files

LLVM/project 83164a4clang/docs ReleaseNotes.rst, clang/lib/Parse ParseExprCXX.cpp

[Clang] fix assertion failure in ::template operator parsing (#194097)

when parsing an invalid `::template operator`, the parser incorrectly
kept the consumed tokens on error. This caused the token cache to go out
of sync and crash. This patch fixes it by reverting the tokens and
properly returning the error
fixes #186582
DeltaFile
+4-4clang/lib/Parse/ParseExprCXX.cpp
+8-0clang/test/Parser/gh186582.cpp
+1-0clang/docs/ReleaseNotes.rst
+13-43 files

LLVM/project ad23908llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

[SLP][NFC]Cache isUsedOutsideBlock results in gather-shuffle analysis

Hoist loop-invariant predicates and memoize per-UserTE
all_of(Scalars, isUsedOutsideBlock) in
isGatherShuffledSingleRegisterEntry and vectorizeTree to avoid
redundant walks over scalar user lists in the gather-shuffle hot path.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/194612
DeltaFile
+55-15llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+55-151 files

LLVM/project a6df7ebflang/include/flang/Optimizer/Dialect FIROps.td, flang/lib/Optimizer/CodeGen PreCGRewrite.cpp

[flang] allow rebox/embox of OPTIONAL (#194319)

Delay materialization of branches when building local temporary
descriptor for OPTIONAL from hlfir-to-fir until pre-cg-rewrite.
This makes the IR easier to analyze with OPTIONAL (for instance alias
analysis does not need to handle the branches to find the source).

This is done by adding an "optional" attribute to fir.embox, fir.rebox,
and fir.rebox_assumed_rank to indicate that their cogeneration must be
conditional.

The conditional aspect is implemented in pre-cg-rewrite to avoid
complexifying codegen and the fir.cg dialect.

Assisted by: Claude
DeltaFile
+113-31flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp
+89-0flang/test/Fir/rebox-embox-optional-codegen.fir
+21-32flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
+29-8flang/test/HLFIR/declare-codegen.fir
+31-6flang/lib/Optimizer/Transforms/AssumedRankOpConversion.cpp
+24-8flang/include/flang/Optimizer/Dialect/FIROps.td
+307-854 files not shown
+373-8810 files

LLVM/project 9d3f237clang/lib/AST/ByteCode InterpBuiltinBitCast.cpp Interp.cpp, clang/test/AST/ByteCode builtin-bit-cast-bitfields.cpp new-delete.cpp

[clang][bytecode] Don't start record field lifetime by default (#193496)

Even though we have per-field lifetime information we did not previously
diagnose this test:
```c++
  struct R {
    struct Inner { constexpr int f() const { return 0; } };
    int a = b.f();
    Inner b;
  };
  constexpr R r;
```
because the life time was started by default.

This patch makes record members be `Lifetime::NotStarted` by default
(unless they are primitive arrays) and then starts the lifetime when in
`Pointer::initialize()`.
DeltaFile
+72-47clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
+37-13clang/lib/AST/ByteCode/Interp.cpp
+24-16clang/lib/AST/ByteCode/Compiler.cpp
+9-13clang/test/AST/ByteCode/builtin-bit-cast-bitfields.cpp
+8-9clang/test/AST/ByteCode/new-delete.cpp
+13-0clang/test/AST/ByteCode/records.cpp
+163-987 files not shown
+180-10113 files

LLVM/project 34e136bllvm/test/Transforms/PhaseOrdering/X86 horizontal-reduce-smax.ll horizontal-reduce-smin.ll

[PhaseOrdering][X86] Copy backend horizontal min/max reduction tests to phaseordering (#194601)

As discussed on #194473 - add middleend test coverage to ensure we're
creating vXi8/vXi16 llvm.vector.reduce calls to ensure we can lower to
PHMINPOS instructions

Also demonstrates that we're still not matching partial reduction
patterns in vectorcombine
DeltaFile
+419-0llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smax.ll
+419-0llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-smin.ll
+419-0llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umax.ll
+419-0llvm/test/Transforms/PhaseOrdering/X86/horizontal-reduce-umin.ll
+1,676-04 files

LLVM/project c5e941dllvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx bitrev.ll bitset.ll

[LoongArch] Support VBIT{CLR,SET,REV}I patterns for non-native element sizes (#193719)

Extend vsplat_uimm_{pow2,inv_pow2} matching to allow specifying an
explicit element bit width, enabling recognition of splat patterns whose
logical element size differs from the vector's native element type.

Introduce templated selectVSplatUimm{Pow2,InvPow2} helpers with an
optional EltSize parameter, and add corresponding ComplexPattern
definitions for i8/i16/i32 element widths. This allows TableGen patterns
to match cases such as operating on v8i32/v4i64 vectors with masks
derived from smaller element sizes.

With these changes, AND/OR/XOR operations using inverse power-of-two or
power-of-two splat masks are now correctly selected to VBITCLRI,
VBITSETI, and VBITREVI instructions instead of falling back to vector
logical operations with materialized constants.
DeltaFile
+35-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+27-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+8-4llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+3-6llvm/test/CodeGen/LoongArch/lasx/bitrev.ll
+3-6llvm/test/CodeGen/LoongArch/lasx/bitset.ll
+3-6llvm/test/CodeGen/LoongArch/lasx/bitclr.ll
+79-224 files not shown
+90-4110 files

LLVM/project 378b411clang/test/CodeGen/AArch64/sve2p3-intrinsics acle_sve2p3_qshr.c acle_sve2p3_qrshr.c, clang/test/Sema/AArch64 arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c

[clang][AArch64][SVE2p3][SME2p3] Add intrinsics for v9.7a shift operations (#186087)

Add the following new clang intrinsics based on the ACLE specification
https://github.com/ARM-software/acle/pull/428 (Add alpha support for 9.7
data processing intrinsics)

Multi-vector saturating rounding shift right narrow and interleave
instructions
- SQRSHRN
- svint8_t svqrshrn_s8(svint16x2_t, uint64_t) / svint8_t
svqrshrn_n_s8_s16_x2(svint16x2_t, uint64_t)

- UQRSHRN
- svuint8_t svqrshrn_u8(svuint16x2_t, uint64_t) / svuint8_t
svqrshrn_n_u8_u16_x2(svuint16x2_t, uint64_t)

- SQRSHRUN
- svuint8_t svqrshrun_u8(svint16x2_t, uint64_t) / svuint8_t
svqrshrun_n_u8_s16_x2(svint16x2_t, uint64_t)

    [18 lines not shown]
DeltaFile
+255-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_qshr.c
+144-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_qrshr.c
+87-0clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
+66-0clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
+58-0llvm/test/CodeGen/AArch64/sve2p3-intrinsics/sve2p3-intrinsics-qshr.ll
+51-0clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_qshrn.cpp
+661-05 files not shown
+734-1611 files

LLVM/project c28d907llvm/test/tools/llubi intr_vector_interleave.ll intr_vector_manip.ll, llvm/tools/llubi/lib Interpreter.cpp

[llubi] Implement vector reduction/manipulation intrinsics (#194345)

This PR implements vector reduction and manipulation intrinsics. 

Note that floating-point vector reduction intrinsics are not covered by
this change; they will be added in a follow-up PR after #188453 is
merged.
DeltaFile
+181-0llvm/tools/llubi/lib/Interpreter.cpp
+61-0llvm/test/tools/llubi/intr_vector_interleave.ll
+56-0llvm/test/tools/llubi/intr_vector_manip.ll
+55-0llvm/test/tools/llubi/intr_vector_reduce.ll
+17-0llvm/test/tools/llubi/intr_vector_stepvector.ll
+370-05 files

LLVM/project f82a74aflang/test/Lower submodule.f90 statement-function.f90

[flang][NFC] Converted five tests from old lowering to new lowering (part 51) (#194522)

Converted Lower/associate-construct.f90,
Lower/default-initialization.f90, Lower/select-type-2.f90,
Lower/statement-function.f90, and Lower/submodule.f90 from legacy
lowering (-hlfir=false) to new lowering (-emit-hlfir).
DeltaFile
+65-72flang/test/Lower/submodule.f90
+59-59flang/test/Lower/statement-function.f90
+46-33flang/test/Lower/associate-construct.f90
+30-22flang/test/Lower/default-initialization.f90
+6-5flang/test/Lower/select-type-2.f90
+206-1915 files