[mlir][xegpu] Check uArch block shapes in VectorToXeGPU transfer lowering (#217179)
vector.transfer_read/transfer_write were lowered to xegpu.load_nd /
xegpu.store_nd whenever the target chip was pvc, bmg or cri and the
transfer had rank >= 2, without asking whether the target's subgroup 2D
block instructions can access the requested tile at all.
Changing it to query the uArch 2D block load/store description up front
and keep the block path only for tiles whose two innermost dims are each
a multiple of a supported block size- the property the later layout
propagation and blocking passes rely on when they split a tile into
hardware-sized blocks. Everything else takes the scattered
load_gather/store_scatter fallback that both patterns already have.
Deriving 2D block support from the uArch instruction registry also
replaces the hardcoded chip list, resolving the TODO left there; the
three chips that registry covers are the same three that were listed.
assisted by claude
[lldb-dap] End the session before sending the disconnect response (#227106)
Previously the `disconnect` request asks the debug adapter to disconnect
from the debuggee, ending the debug session, and then to shut down.
lldb-dap responded right after killing or detaching the process. So the
`exited` event, terminatedCommands and exitedCommands can be sent after
`disconnect` could reaches the client.
`DisconnectRequestHandler` now stores its response in
`DAP::on_session_end`. `DAP::Loop()` sends it once the session ended.
The teardown/cleanup is now:
- The event threads stop, after they report the exit of a killed
process.
- `terminated` Event is sent, if the event thread didn't send it.
- The transport thread stops.
- If there is a pending `configuration_done` we reply.
- The requests queued behind `disconnect` request are cancelled.
- The `disconnect` response is sent last.
- The debugger is destroyed.
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[Clang] Do not assume existing substition for template specialization
Mangled symbol is not always available when having template
specialization. For example, a template alias mangled the type when
actually doing substitution. In previous code, B in A<B>::foo() is
always mangled when reaching A<B>. When doing substition insides A<T>,
B is always available. Alias is not the case here, B is mangled when
reaching A<T> inside.
As now, TemplateName::SubstTemplateTemplateParm might needs to be
resolved further as B is not always defined, we remove it from the
switch case and find recursively like the origianl path.
Assisted-by: Claude # Tests, ReleaseNotes
[BOLT] Emit DW_AT_high_pc matching the class of its form (#227066)
DW_AT_high_pc holding an offset from DW_AT_low_pc is a DWARF 4 addition;
in DWARF 2 and 3 the attribute is always class address.
updateLowPCHighPC() always wrote "HighPC - LowPC" while reusing whatever
form the input DIE had, so a DWARF 2 CU using DW_FORM_addr ended up
storing a length where an end address is expected.
BOLT should write the end address when the form is DW_FORM_addr, and
the length otherwise. The default form for a new attribute is now
DW_FORM_addr below DWARF 4, and size needs to be widened to 64 bits so
DW_FORM_data8 won't be truncated. The FunctionRanges.empty() code path
no longer treats a raw DW_FORM_addr high_pc as a size.
Assited-by: opus
[libc][aarch64] Use inline_memcpy_aligned_access_64bit under -mstrict-align (#227428)
Under `-mstrict-align`, clang cannot determine both `src` and `dst` are
aligned. The end of `inline_memcpy_aarch64` aligns `src` but it cannot
confirm `dst` is aligned. As a result,
`builtin::Memcpy<64>::loop_and_tail(dst, src, count)` lowers to
`__builtin_memcpy_inline(..., 64)` but clang emits many many single-byte
load/store instructions to ensure correctness. This can be very slow, so
if unaligned accesses are not supported, opt for adjusting both `src`
and `dst` such that we can use 8-byte loads/stores.
`inline_memcpy_aligned_access_64bit` already does this so we can just
reuse that.
[Hexagon,test] Enable +audio for intrinsics-v67.ll (#227362)
The test uses llvm.hexagon.M7.vdmpy{,.acc}, which lower to
M7_dcmpyrwc{,_acc}. Those instructions require the audio feature, so add
-mattr=+audio to the RUN line to avoid a predicate-check crash in the
asm printer.
[clang][docs] Use doc links to HLSL/ResourceTypes in AttrDocs.td (#227407)
#222504 made the docs build warn about absolute links to pages of the
same Sphinx project, and the docs build turns warnings into errors. The
HLSL resource attribute docs added in #213346 linked to
https://clang.llvm.org/docs/HLSL/ResourceTypes.html, which after #226729
broke the clang docs build (docs-clang-html, docs-clang-man). Use the
{doc} role instead, like the rest of AttrDocs.td.
[lldb] Add label, title and divider ANSI settings (#226606)
Commands that print structured listings hard-coded their colors, but
terminal themes render ANSI colors differently, so users couldn't adjust
them the way they can with the prompt, progress or autosuggestion
colors.
Add `label-ansi-prefix`, `title-ansi-prefix` and `divider-ansi-prefix`
settings, each with a matching suffix, for the field labels, entry
titles and dividers such listings are made of. Their defaults are the
colors `scripting extension list` uses today, and it now reads them from
these settings.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
[flang][openacc] Add ACCEraseUnusedKernelAllocations pass (#227481)
fir.declare carries a debug-memory effect and fir.freemem is a real
free, so an unused fir.allocmem inside acc.compute_region stays live
through ordinary dead-code elimination and is lowered to a checked
device malloc.
Delete that allocation when it has no uses, or when every use is
fir.freemem, a ViewLikeOpInterface view such as fir.convert, or
fir.declare of that storage. A load, store, or other memory use keeps
it. An unused private-recipe allocation is removed the same way as an
unused source array.
[clang][CIR] Match CIR return value with OGCG using mem2reg (#227241)
This fixes the test failure introduced by
[226534](https://github.com/llvm/llvm-project/pull/226534)
Currently, the `sve/len.c` test fails because of this difference between
OGCG and CIR:
```
; classic codegen ; CIR (-fclangir)
%2 = mul nuw i64 %1, 16 %6 = mul nuw i64 %5, 16
ret i64 %2 store i64 %6, ptr %3 ; retval slot
%7 = load i64, ptr %3
ret i64 %7
```
So, adding the return value checks as they are breaks the test.
This adds `mem2reg`, so that the CIR output matches OGCG and the same
return value check works for both.
[RISCV][P-ext] Add scalar multiply high intrinsics (#225561)
Add intrinsics, Clang builtins and SelectionDAG support for the scalar
multiply high operations.
Support
[multiply-high](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#multiply-high).
On RV32 the non-rounding forms map to the M-extension mulh/mulhu/mulhsu
instructions and the rounding forms to the P-extension
mulhr/mulhru/mulhrsu instructions.
On RV64 the scalar spellings reuse the packed pmulh.w family on the low
words via the existing PMULH*_W patterns.
[LLVMABI][AARCH64] Handle vector types (#225201)
This adds handling for vector types in the AArch64 implementation of the
LLVM ABI library. Legal vectors are passed and returned directly.
Illegal vectors are coerced to an integer or an integer vector, or
passed indirectly if they are too large. Sizeless SVE types are passed
in a register of their own, and fixed-length SVE vectors are coerced to
a scalable vector that occupies the same register. SVE tuples still
report NYI under AAPCS.
Assisted-by: Cursor / claude-opus-5
[AMDGPU][NFC] De-factorize scalar_to_vector bf16 patterns (#226847)
For Fake16, an SGPR and a VGPR can share the same scalar_to_vector
pattern because there is no 16-bit SGPR at all. The separate uniform
SGPR pattern is therefore only needed for Real True16, where the
divergent case uses a VGPR_16 REG_SEQUENCE.
This de-factorization is to prepare for follow-up PRs to separate SGPR
and VGPR patterns of scalar_to_vector for other types.
[lldb] Fix deadlock when a REPL expression hits a breakpoint (#227400)
When a REPL expression stops at a breakpoint,
REPL::IOHandlerInputComplete calls RunIOHandlerAsync to drop into the
command interpreter while it still holds the error stream lock.
RunIOHandlerAsync then takes the IOHandler stack mutex. At the same
time, the event handler thread reports the stop through
IOHandlerStack::PrintAsync, which takes the IOHandler stack mutex first
and the output mutex second. The opposite lock order can deadlock,
leaving lldb hung after it prints "Execution stopped at breakpoint."
The lock scope that covers the call was introduced in 5007dd9d0945
(#183600). Keep printing under the lock, but defer RunIOHandlerAsync
until the lock is released.
This patch adds a test that exercises this path with the C REPL. Because
the deadlock is a race, the test only catches a regression
intermittently: without the fix it hung in about 6% of runs under
parallel load, and in every run when a delay was injected inside the
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[obj2yaml] Suppress leak check on abnormal exit (#227444)
This is a common issue with lsan after exit().
exit() is noreturn, so we cannot expect that the compiler will
preserve pointers to allocations done by callers.
Fixes https://lab.llvm.org/buildbot/#/builders/169/builds/27022
Assisted-by: Gemini
TwoAddressInstructions: Fix subranges straddling the INSERT_SUBREG subreg index (#227427)
Rewriting INSERT_SUBREG into a subregister COPY narrows the def from the
whole register down to one subreg index. The live interval fixup for that only
handled subranges entirely disjoint from the inserted lane mask, so a partially
overlapping subrange keeps a value whose def no longer writes all of its lanes.
The stale value makes the lanes outside the inserted subregister look
defined by the COPY, so the copy that actually provides them ends up
dead and its value is lost. Refine the subranges against the subreg index
before narrowing the def, leaving each one either fully redefined by the COPY
or untouched by it.
Fixes a miscompile reported on RISC-V and restores the pre-6286f77214be
output of Thumb2/mve-vst2.ll, Thumb2/mve-vst3.ll and PowerPC/dmr-enable.ll.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
[CIR] Coerce record returns from memory like CreateCoercedLoad
Read a coerced record return straight from the alloca it was loaded
from. If that isn't possible, copy the record's bytes into a coercion
slot and read from there. Neither path stores the record as a value.
A union stored as a value keeps only its storage member and loses the
bytes that are padding in that member.
Assisted-by: Claude Code / Claude Opus 5.5
Use new-style triples in SRAMECC mode test
Resolve the processor from the triple subarch as requested in review.
Change-Id: Ibbfd674a974fa19e71ef08497c27010e7a452c43
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
[HLSL][Matrix] Convert loaded bool matrices to `i1` (#226599)
Fixes #226308.
This PR converts loaded bool matrices to their `i1` representation
before use, like bool vectors do, and updates the affected matrix
codegen tests.
It also splits matrix tests out of `or.hlsl` into its own `or_mat.hlsl`
file to match the convention of the other matrix intrinsic tests.
Assisted-by: Claude Opus 4.8
[AMDGPU] Validate scale_sel in v_cvt_scale_*
These instructions can be block16 or block32 depending on the target
and scale_sel bits. Block16 is not supported in strict mode.
Re-enable the rest of the instructions in the strict mode but validate
the scale selector.
[AMDGPU][GlobalISel] Keep typed LLTs in RegBankLegalize combines
The S1 cleanup combines in AMDGPURegBankLegalize built new registers
with an untyped s32, missed when lowering switched to extended LLTs.
The regbank combiner later unified these with typed registers, so
constrainRegAttrs retyped e.g. an i32 G_CTPOP result to s32, which
failed instruction selection.
Take the type from the source or destination register instead.
Change-Id: I06cfb7278af045dbaa3ca0cc6c77a3938f4cef01
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
[lldb] Bounds-check ELF relocation offsets (#227046)
Relocations applied to ELF debug sections were written at r_offset
without checking that the target fits in the section. A malformed object
file could therefore write anywhere relative to the file buffer.
Check every relocation target against the section data. Skip and report
relocations that fall outside it.
rdar://186921964
[CIR] Lower variadic arguments through an indirect call
On x86_64, CallConvLowering now classifies an indirect call with
ellipsis arguments from its own operands, as it does a direct variadic
call. Those arguments stay out of the retyped callee's function type, as
in classic CodeGen.
The cir.call verifier now checks indirect calls against the callee
pointer's function type, and CIRGen's asm-label redirect keeps a
variadic declaration's ellipsis instead of dropping it.
Assisted-by: Claude Code / claude-opus-5-5
