LLVM/project a8ba28f — llvm/include/llvm/MC MCSubtargetInfo.h

drop useless comment
DeltaFile
+0-2llvm/include/llvm/MC/MCSubtargetInfo.h
+0-21 files

LLVM/project ceca7fd — .github CODEOWNERS

Add Vassil's responsibilities to the CODEOWNERS file. (#228167)

I'd like to get more reliable github-based routing when pull requests
arrive in the areas I am maintaining.

For reference, see clang/Maintainers.md
DeltaFile
+7-0.github/CODEOWNERS
+7-01 files

LLVM/project 7320cc1 — llvm/lib/CodeGen TargetLoweringObjectFileImpl.cpp, llvm/test/CodeGen/SystemZ zos-landingpad.ll zos-eh.ll

[SystemZ][z/OS] Fix GOFF exception table (LSDA) section generation (#228097)

Fixes #226804

The z/OS Binder rejects LSDA exception tables with `IEW2353E ... ERROR
CODE IS 25000E` when emitted as renamable PRs under an initial-load
`C_WSA64` ED parented to the root code section.

Following the fix suggested by @mms-it-ch in #226804, emit the LSDA
similarly to static WSA data:
- Under its own Section Definition (`SD`) named `GCC_except.<func>` with
`ESD_BSC_Section`.
- With a `C_WSA64` Element Definition (`ED`) using deferred load
(`GOFF::ESD_LB_Deferred`) and doubleword alignment.
- As a non-renamable Part Reference (`PR`).

Co-authored-by: Yusra Syeda <yusra.syeda at ibm.com>
DeltaFile
+8-5llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+4-5llvm/test/CodeGen/SystemZ/zos-landingpad.ll
+5-4llvm/test/CodeGen/SystemZ/zos-eh.ll
+17-143 files

LLVM/project 6c538e7 — llvm/include/llvm/MC MCContext.h MCSubtargetInfo.h, llvm/lib/MC MCContext.cpp

add a clone() function instead and drop the bumpptrallocator
DeltaFile
+3-6llvm/utils/TableGen/SubtargetEmitter.cpp
+5-4llvm/include/llvm/MC/MCSubtargetInfo.h
+2-4llvm/test/TableGen/HwModeBitSet.td
+2-2llvm/lib/MC/MCContext.cpp
+3-1llvm/include/llvm/MC/MCContext.h
+15-175 files

LLVM/project 1e1f35b — compiler-rt/lib/fuzzer FuzzerDriver.cpp FuzzerFlags.def

[libFuzzer] Fix typos and punctuation in flag descriptions (#122619)

Co-authored-by: Stan Ulbrych <stan at python.org>
DeltaFile
+36-36compiler-rt/lib/fuzzer/FuzzerFlags.def
+1-1compiler-rt/lib/fuzzer/FuzzerDriver.cpp
+37-372 files

LLVM/project b7cf639 — llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU VOP3Instructions.td AMDGPULowerIntrinsics.cpp

[AMDGPU] Validate scale_sel in v_cvt_scale_*

These instructions can be block16 or block32 depending on the target
and scale_sel bits. Block16 is not supported in strict mode.

Re-enable the rest of the instructions in the strict mode but validate
the scale selector.
DeltaFile
+268-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk-scale-range.ll
+135-16llvm/test/MC/AMDGPU/gfx1250-strict_err.s
+61-0llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+47-0llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+7-9llvm/lib/Target/AMDGPU/VOP3Instructions.td
+6-8llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+524-333 files not shown
+533-489 files

LLVM/project f3eb046 — clang/include/clang/Basic BuiltinsAMDGPU.td, clang/test/SemaOpenCL builtins-amdgcn-error-gfx1250-strict.cl

[AMDGPU] v_cvt_scale_pk8_* are block32 in strict mode (#227426)

Re-enable these instructions in strict mode.

Fixes: LCOMPILER-2841
DeltaFile
+15-14llvm/lib/Target/AMDGPU/VOP3Instructions.td
+0-27llvm/test/MC/AMDGPU/gfx1250-strict_err.s
+10-9llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+9-9clang/include/clang/Basic/BuiltinsAMDGPU.td
+0-9clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-strict.cl
+34-685 files

LLVM/project d47315b — compiler-rt/lib/sanitizer_common/symbolizer sanitizer_wrappers.cpp, compiler-rt/test/ubsan/TestCases/Misc/Posix hsa-load-order.cpp shared-libsan-dso.cpp

[compiler-rt] Fix -shared-libsan usage with internal symbolizer (#227717)

Summary:
https://github.com/llvm/llvm-project/pull/226551 exposed a preexisting
issue when using `-shared-libsan` nad the internal symbolizer builds.
The symbolizer will try to look up the symbol via `RTLD_NEXT`, which
goes in load order. If the sanitizer library is loaded *after* `libc.so`
then this `dlsym` call will miss it.

The solution is to have a fallback that checks using `RTLD_DEFAULT`.
This
should allow us to find the symbol in these exceptional cases. I don't
expect much fallout as this covers a case that currently returns `NULL`.
Loading it in means it could grab a reference ahead of the runtime that
was intended to be intercepted, but for this use-case I don't think this
will apply.
DeltaFile
+23-0compiler-rt/test/ubsan/TestCases/Misc/Posix/shared-libsan-dso.cpp
+8-1compiler-rt/lib/sanitizer_common/symbolizer/sanitizer_wrappers.cpp
+0-4compiler-rt/test/ubsan/TestCases/Misc/Posix/hsa-load-order.cpp
+31-53 files

LLVM/project 87db728 — clang/docs ReleaseNotes.md, clang/lib/AST ExprConstant.cpp

[clang] Fix crash constant-evaluating the construction of huge arrays (#226899)

Fixes #173728

The constant evaluator runs on ordinary code all the time (range checks
for `-W` warnings, `isEvaluatable` in codegen), and it
default-constructs an array by building one `APValue` per element. The
element count got truncated to `unsigned` first and nothing checked its
size, so a local like `struct T {} s[0xFFFFFFFF][0]` ran it out of
memory; with the issue's reproducer, where the count wraps to 2^64 - 4,
an assertions build hits the "bounds check failed" assertion in
`adjustIndex` first. Copying such an array, e.g. into a lambda capture,
had the same problem. This goes back to at least Clang 3.4. The bytecode
interpreter has its own version: it emits code for every element, so a
constructor with a member like `T a[0xFFFFFFFF]` runs it out of memory
too.

Array default construction and `ArrayInitLoopExpr` now go through the
existing `CheckArraySize` guard, the same one `new` already uses, so

    [6 lines not shown]
DeltaFile
+61-0clang/test/AST/ByteCode/dynalloc-limits.cpp
+15-2clang/lib/AST/ByteCode/Compiler.cpp
+7-0clang/lib/AST/ByteCode/InterpHelpers.h
+4-0clang/lib/AST/ExprConstant.cpp
+4-0clang/docs/ReleaseNotes.md
+91-25 files

LLVM/project d6a906b — lldb/source/Core Module.cpp

[LLDB] Acquire the module mutex at the start of SetLoadAddress (#227149)

Fixes a potential dead-lock from parallel module loading. 

I received a quick-stack of LLDB hung loading a core with parallel
module loading enabled, where two threads were trying to mutate a given
module and an object file, but having acquired the module mutex first in
one case, and the object file's section mutex first in the second case,
which each trying to subsequently acquire the other lock.

In the update case, [SetLoadAddress acquires the section list mutex and
then tries to acquire the module
mutex](https://github.com/llvm/llvm-project/blob/60f717946cb5ca911b6be22169b9bd646225c59f/lldb/source/Symbol/ObjectFile.cpp#L614)

```
SectionList *ObjectFile::GetSectionList(bool update_module_section_list) {
  std::lock_guard<std::recursive_mutex> guard(m_sections_mutex);
  if (m_sections_up)
    return m_sections_up.get();

    [26 lines not shown]
DeltaFile
+4-0lldb/source/Core/Module.cpp
+4-01 files

LLVM/project 88156f8 — clang/lib/CodeGen CGStmtOpenMP.cpp, clang/test/OpenMP teams_generic_loop_reduction_distribute_codegen.cpp

[clang][OpenMP] Don't use fused dist schedule for teams loop emitted as distribute (#228129)

Fix teams loop reductions lowered as 'distribute' lose their loop.

Claude assisted with this patch.
DeltaFile
+63-0clang/test/OpenMP/teams_generic_loop_reduction_distribute_codegen.cpp
+9-0clang/lib/CodeGen/CGStmtOpenMP.cpp
+72-02 files

LLVM/project 6321d0c — clang/test/CodeGenOpenCL builtins-amdgcn-make-buffer-rsrc.cl, llvm/lib/Target/AMDGPU AMDGPUInstCombineIntrinsic.cpp

[AMDGPU] Canonicalize num_records to its actual width in InstCombine

llvm.amdgcn.make.buffer.rsrc is overloaded on the type of its
num_records argument, but the hardware field it ends up in has a fixed
width (32 bits, or 45 bits on gfx1250 and up). Rewrite the intrinsic to
use that width, zero-extending or truncating num_records as needed, so
that IR-level optimizations can see that the extra bits of, for example,
the i64 that Clang emits are not demanded.

Targets that aren't concrete enough for the buffer resource layout to be
known are left alone.

AI disclosure: This was my idea but Claude wrote the code (and I've
tried to tighten up the comments)
DeltaFile
+36-44clang/test/CodeGenOpenCL/builtins-amdgcn-make-buffer-rsrc.cl
+22-12llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+21-1llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+1-1llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+80-584 files

LLVM/project 9247019 — llvm/test/Transforms/InstCombine/AMDGPU make-buffer-rsrc-num-records.ll

[AMDGPU] Pre-commit tests for num_records canonicalizations (#217067)

Add tests for having InstCombine canonicalize the num_records argument
of llvm.amdgcn.make.buffer.rsrc to the width it will ultimately have,
which lets later passes see that, for example, the high bits of the i64
that Clang emits aren't used.

AI disclosure: Claude generated these and I've looked at them
DeltaFile
+153-0llvm/test/Transforms/InstCombine/AMDGPU/make-buffer-rsrc-num-records.ll
+153-01 files

LLVM/project 152d32e — clang/lib/CodeGen/TargetBuiltins RISCV.cpp, clang/test/CodeGen/RISCV rvp-intrinsics.c

[Clang][RISCV][P-ext] Add packed Q-format widening accumulate intrinsics (#228009)

Add support for the Packed "Q-format" Multiply with Widening Accumulate
intrinsics:

- `__riscv_pmqwacc_i32x2`
- `__riscv_pmqrwacc_i32x2`

RV32 selects the direct instructions, while RV64 lowers to the
spec-listed `zip16p` and packed Q-format accumulate sequences.
DeltaFile
+32-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+28-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+24-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+17-5llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+16-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+9-0clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+126-53 files not shown
+144-59 files

LLVM/project 5d9419f — clang/include/clang/CodeGenUtils TargetUtils.h, clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp

[CIR][CodeGen][NFC] Share hasExtraNeonArgument

Deduplicates `hasExtraNeonArgument` between CIR and classic CodeGen into
`TargetUtils.h`.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+2-38clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+3-34clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+25-0clang/lib/CodeGenUtils/TargetUtils.cpp
+6-0clang/include/clang/CodeGenUtils/TargetUtils.h
+36-724 files

LLVM/project 4cfbae7 — clang/include/clang/CodeGenUtils RecordLayoutUtils.h, clang/lib/CIR/CodeGen TargetInfo.h TargetInfo.cpp

[CIR][CodeGen][NFC] Share isEmptyFieldForLayout and isEmptyRecordForLayout

Deduplicates `isEmptyFieldForLayout` and `isEmptyRecordForLayout` between CIR
and classic CodeGen into a new `RecordLayoutUtils.h`. `ABIInfoImpl.h` and CIR's
`TargetInfo.h` re-export them with using-declarations, so the ~30 unqualified
callers are untouched.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+45-0clang/lib/CodeGenUtils/RecordLayoutUtils.cpp
+0-34clang/lib/CIR/CodeGen/TargetInfo.cpp
+34-0clang/include/clang/CodeGenUtils/RecordLayoutUtils.h
+0-33clang/lib/CodeGen/ABIInfoImpl.cpp
+3-9clang/lib/CodeGen/ABIInfoImpl.h
+3-9clang/lib/CIR/CodeGen/TargetInfo.h
+85-851 files not shown
+86-857 files

LLVM/project ae13a22 — clang/include/clang/CodeGenUtils RecordLayoutUtils.h, clang/lib/CIR/CodeGen CIRGenRecordLayoutBuilder.cpp

[CIR][CodeGen][NFC] Share hasOwnStorage

Deduplicates `hasOwnStorage` between CIR and classic CodeGen into
`RecordLayoutUtils.h`.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+4-17clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
+1-16clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
+12-0clang/lib/CodeGenUtils/RecordLayoutUtils.cpp
+5-0clang/include/clang/CodeGenUtils/RecordLayoutUtils.h
+22-334 files

LLVM/project 1f1f902 — clang/include/clang/CodeGenUtils ItaniumCXXABIUtils.h, clang/lib/CIR/CodeGen CIRGenItaniumCXXABI.cpp

[CIR][CodeGen][NFC] Share canUseSingleInheritance

Deduplicates `canUseSingleInheritance` between CIR and classic CodeGen into
`ItaniumCXXABIUtils.h`.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+2-30clang/lib/CodeGen/ItaniumCXXABI.cpp
+2-28clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
+22-0clang/lib/CodeGenUtils/ItaniumCXXABIUtils.cpp
+5-0clang/include/clang/CodeGenUtils/ItaniumCXXABIUtils.h
+31-584 files

LLVM/project bfe776a — clang/include/clang/CodeGenUtils ItaniumCXXABIUtils.h, clang/lib/CIR/CodeGen CIRGenItaniumCXXABI.cpp

[CIR][CodeGen][NFC] Share the Itanium __vmi_class_type_info flags computation

Deduplicates the `__vmi_class_type_info` and `__base_class_type_info` flags and
`computeVMIClassTypeInfoFlags` between CIR and classic CodeGen into
`ItaniumCXXABIUtils.h`.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+3-79clang/lib/CodeGen/ItaniumCXXABI.cpp
+3-77clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
+54-0clang/lib/CodeGenUtils/ItaniumCXXABIUtils.cpp
+21-0clang/include/clang/CodeGenUtils/ItaniumCXXABIUtils.h
+81-1564 files

LLVM/project b7cdaec — clang/include/clang/CodeGenUtils ClassUtils.h FunctionUtils.h, clang/lib/CodeGenUtils ClassUtils.cpp FunctionUtils.cpp

[CIR][CodeGen][NFC] Retire the CodeGenUtils.h catch-all header

Moves the last helpers out of `CodeGenUtils.h` into `ClassUtils.h`,
`ModuleUtils.h`, `TargetUtils.h` and `FunctionUtils.h` (`checkTargetFeatures`,
since it came from CodeGenFunction.cpp) and deletes the header. Only moves code
already on main, so it can be dropped on its own.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+0-233clang/lib/CodeGenUtils/CodeGenUtils.cpp
+120-0clang/lib/CodeGenUtils/FunctionUtils.cpp
+78-0clang/lib/CodeGenUtils/ClassUtils.cpp
+0-65clang/include/clang/CodeGenUtils/CodeGenUtils.h
+24-2clang/include/clang/CodeGenUtils/FunctionUtils.h
+18-0clang/include/clang/CodeGenUtils/ClassUtils.h
+240-30016 files not shown
+279-31222 files

LLVM/project 5d98a76 — clang/include/clang/CodeGenUtils TargetUtils.h, clang/lib/CIR/CodeGen TargetInfo.h TargetInfo.cpp

[CIR][CodeGen][NFC] Share requiresAMDGPUProtectedVisibility

Deduplicates `requiresAMDGPUProtectedVisibility` between CIR and classic CodeGen
into `TargetUtils.h`. The shared version takes a bool for "currently hidden" in
place of the `llvm::GlobalValue` and `cir::VisibilityKind` the two callers
passed.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+3-15clang/lib/CodeGen/Targets/AMDGPU.cpp
+0-14clang/lib/CIR/CodeGen/Targets/AMDGPU.cpp
+14-0clang/lib/CodeGenUtils/TargetUtils.cpp
+6-2clang/lib/CIR/CodeGen/TargetInfo.cpp
+6-0clang/include/clang/CodeGenUtils/TargetUtils.h
+0-4clang/lib/CIR/CodeGen/TargetInfo.h
+29-356 files

LLVM/project 30ba8dc — clang/include/clang/CodeGenUtils TargetUtils.h, clang/lib/CIR/CodeGen/Targets AArch64.cpp

[CIR][CodeGen][NFC] Share the Arm SME inlinability check

Deduplicates `ArmSMEInlinability` and `getArmSMEInlinability` between CIR and
classic CodeGen into a new `TargetUtils.h`.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+18-60clang/lib/CodeGen/Targets/AArch64.cpp
+3-52clang/lib/CIR/CodeGen/Targets/AArch64.cpp
+51-0clang/include/clang/CodeGenUtils/TargetUtils.h
+50-0clang/lib/CodeGenUtils/TargetUtils.cpp
+1-0clang/lib/CodeGenUtils/CMakeLists.txt
+123-1125 files

LLVM/project e36851e — clang/include/clang/CodeGenUtils RecordLayoutUtils.h, clang/lib/CIR/CodeGen CIRGenRecordLayoutBuilder.cpp

[CIR][CodeGen][NFC] Share the bit-field and vbase layout ABI predicates

Deduplicates `isDiscreteBitFieldABI` and `isOverlappingVBaseABI` between CIR and
classic CodeGen into `RecordLayoutUtils.h`, as free functions taking the
`ASTContext`.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+7-24clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
+4-19clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
+12-0clang/include/clang/CodeGenUtils/RecordLayoutUtils.h
+9-0clang/lib/CodeGenUtils/RecordLayoutUtils.cpp
+32-434 files

LLVM/project 3454957 — clang/include/clang/CodeGenUtils ItaniumCXXABIUtils.h, clang/lib/CIR/CodeGen CIRGenItaniumCXXABI.cpp

[CIR][CodeGen] Share isStandardLibraryRTTIDescriptor

Deduplicates `isStandardLibraryRTTIDescriptor` between CIR and classic CodeGen
into `ItaniumCXXABIUtils.h`, taking the classic implementation. The two copies
have been equivalent since #227781 filled in the builtin types CIR was missing.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+3-154clang/lib/CodeGen/ItaniumCXXABI.cpp
+1-153clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
+147-0clang/lib/CodeGenUtils/ItaniumCXXABIUtils.cpp
+4-0clang/include/clang/CodeGenUtils/ItaniumCXXABIUtils.h
+155-3074 files

LLVM/project ab166be — clang/include/clang/CodeGenUtils ItaniumCXXABIUtils.h, clang/lib/CIR/CodeGen CIRGenItaniumCXXABI.cpp

[CIR][CodeGen][NFC] Share the Itanium __pbase_type_info flags and predicates

Deduplicates the `__pbase_type_info` flags, `containsIncompleteClassType` and
`extractPBaseFlags` between CIR and classic CodeGen into `ItaniumCXXABIUtils.h`.

Assisted-by: Claude Code (Claude Fable 5.1).
DeltaFile
+4-95clang/lib/CodeGen/ItaniumCXXABI.cpp
+6-90clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
+52-0clang/lib/CodeGenUtils/ItaniumCXXABIUtils.cpp
+44-3clang/include/clang/CodeGenUtils/ItaniumCXXABIUtils.h
+106-1884 files

LLVM/project 31be831 — llvm/lib/Target/AArch64 AArch64InstrInfo.cpp, llvm/lib/Target/Hexagon HexagonVLIWPacketizer.cpp HexagonOptAddrMode.cpp

Targets: Remove redundant TRI arguments from InstrInfo helpers

This is directly available in TargetInstrInfo.

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+9-8llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+7-8llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+6-8llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+4-6llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+3-3llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+2-2llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+31-358 files not shown
+41-5014 files

LLVM/project 89e290a — llvm/include/llvm/CodeGen MachineScheduler.h, llvm/lib/CodeGen MachineScheduler.cpp

Fix unused variables
DeltaFile
+11-19llvm/lib/CodeGen/MachineScheduler.cpp
+2-5llvm/include/llvm/CodeGen/MachineScheduler.h
+0-1llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+13-253 files

LLVM/project b568be8 — llvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/lib/CodeGen TargetInstrInfo.cpp

CodeGen: Remove TRI arguments from TargetInstrInfo hooks

TRI can now always directly be referenced from TargetInstrInfo

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+24-29llvm/lib/Target/X86/X86InstrInfo.cpp
+16-18llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+14-19llvm/include/llvm/CodeGen/TargetInstrInfo.h
+9-13llvm/lib/Target/X86/X86InstrInfo.h
+10-10llvm/lib/CodeGen/TargetInstrInfo.cpp
+6-9llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+79-9826 files not shown
+140-18432 files

LLVM/project db77a46 — flang/lib/Semantics check-omp-syntax.cpp

[flang][OpenMP] Simplify uses of llvm::omp::EnumSet a bit, NFC (#228142)
DeltaFile
+3-10flang/lib/Semantics/check-omp-syntax.cpp
+3-101 files

LLVM/project 2631319 — lldb/include/lldb/Host/common NativeThreadProtocol.h, lldb/source/Plugins/Process/Windows/Common NativeThreadWindows.cpp

[lldb-server] Handle jThreadExtendedInfo
DeltaFile
+49-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+42-0lldb/test/API/windows/thread-extended-info/TestThreadExtendedInfo.py
+4-0lldb/source/Plugins/Process/Windows/Common/NativeThreadWindows.cpp
+3-0lldb/include/lldb/Host/common/NativeThreadProtocol.h
+3-0lldb/test/API/windows/thread-extended-info/Makefile
+3-0lldb/test/API/windows/thread-extended-info/main.c
+104-04 files not shown
+111-010 files