[LoopInterchange] Swap preheader contents before rebuilding LCSSA (#218468)
adjustLoopLinks() swapped the inner/outer preheader bodies only after
adjustLoopBranches() had already moved the reduction PHIs and rebuilt
LCSSA via formLCSSAForInstructions(). A reduction init defined in the
inner preheader was therefore still stranded below its use on the seed
edge when LCSSA was rebuilt, so formLCSSAForInstructions() was handed
dominance-broken IR.
Move the swapBBContents() call into adjustLoopBranches(), after the
replacePhiUsesWith() relabeling and before the LCSSA rebuild, so the
reduction init is relocated into the new outer preheader and dominates
the seed edge. With the swap moved, adjustLoopLinks() only forwarded to
adjustLoopBranches(), so it is inlined into its sole caller and removed.
Fixes #215511
AI tools have been used to generate portions of this patch
[mlir] Fix mlir-pdll-lsp-server link. (#220123)
This is the same fix TableGenLspServerLib got in 9e469ced42cd. This
addresses the mlir-pdll-lsp-server instance of #152371.
MLIRPdllLspServerLib transitively needs LLVMTableGen, which is not part
of libLLVM.so, so MLIRPDLLParser already brings in static LLVMSupport.
Linking the dylib here as well gives mlir-pdll-lsp-server two copies of
LLVMSupport. Linking still succeeds, but with assertions
view-output.test fails. The test trips over the two copies having
different Hashing.h seeds, which is a separate defect to be addressed in
another PR.
It has not shown up in CI because it needs the dylib and assertions at
the same time, which rarely coincide. It also only became reachable once
a3a25996b114 moved the LSP transport into libLLVM.so.
Assisted-By: Claude Opus 5
[CodeGen][RegCoalescer] Preserve valid lanes when keeping IMPLICIT_DEF (#215272)
A subregister definition without the undef flag is a read-modify-write,
including when it is defined by IMPLICIT_DEF. When the IMPLICIT_DEF cannot be
erased, retain the lanes carrying values from the preceding definition.
Otherwise the coalescer can miss the interference between %src and %dst and
turn the first two copies below into a destructive in-place permutation.
[AMDGPU] Add tests for scalar hi-half f16 fma and mad on GFX9 (#219432)
v_fma_f16 and v_mad_legacy_f16 both support op_sel on GFX9, so a 16-bit
ternary
whose sources come from the high halves of packed registers could be a
single
instruction. SelectVOP3OpSel() does not set op_sel yet, so the high
halves are
extracted and re-inserted with explicit shifts instead. Add tests for
both SDAG
and GlobalISel so that the improvement is visible if this is ever fixed.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
[LV] Give each RUN line in smax-idx.ll its own check prefix (NFC). (#220210)
The three RUN lines share the CHECK prefix, which only works while all
three VF/IC configurations produce identical output. This fixes the
dropped checks for smax_idx_max_no_exit_user.
While touching the file, also modernize the naming a bit, to be more
uniform with existing tests.
[IVDescriptors] Implement MonotonicDescriptor
RFC link: https://discourse.llvm.org/t/rfc-loop-vectorization-of-compress-store-expand-load-patterns/86442
"Monotonic" variable is similar to induction variable, but its value is updated under some condition, e.g.:
```
int idx = 0;
for(int i = 0; i < n; ++i) {
// some uses of idx
if (cond)
++idx;
}
```
In this example, `i` is induction variable and `idx` is monotonic variable: it's updated only when cond == true. In LLVM IR, this looks like:
```
loop_header:
%monotonic_phi = [%start, %prehader], [ %chain_phi0, %latch]
step_bb:
[26 lines not shown]
[lldb] Add Guarded<T, Mutex> to Locked.h (#219421)
LLDB's code base has many variables that have an associated mutex that
needs to be locked to safely access that variable from multiple threads.
However, this locking scheme is currently not enforced by the compiler
and code sometimes accesses these variables without aquiring the
respective mutex first.
This patch introduces a `Guarded` class that strictly enforces that some
memory is only accessed after the respective mutex has been aquired.
This class hands out `Locked` objects for every access which guarentee
that the mutex is held as long as the variable is in scope.
[Verifier] Diagnose local scope chains that miss their DISubprogram
visitFunction() resolved a DILocation's subprogram via
DILocalScope::getSubprogram(), which recurses through
DILexicalBlockBase::getScope() and casts each parent to DILocalScope.
A DILexicalBlock parented to a non-local scope, such as a DIFile,
therefore aborted the verifier before visitDILexicalBlockBase could
report "invalid local scope".
[C++20] [Modules] Profiling the lambda call operator only (#220203)
Close https://github.com/llvm/llvm-project/issues/220187
The root cause of the problem is that during the deserialization process
some of the implicit functions are out of sync. They will be the same in
the end. But at the point of profiling, they are different.
This patch fixes this by profiling the explicit lambda call only, which
should be correct too. This was the intention of
CXXRecordDecl::getLambdaCallOperator(), but we didn't use it due to
deserialization ordering issues.
[LV] Vectorize fmin/fmax reductions (#198300)
Teach LoopVectorize to recognize fmin/fmax reductions. This patch only
supports reductions of this kind which have the FP `minimum/maximum` and
`minimumnum/maximumnum` semantics.
[AArch64][GlobalISel] Regenerate knownbits tests. NFC (#220200)
Mostly just adding IsKnownNeverZero. knownbits-srem.mir now has auto
generated check lines.
[VPlan] Expand AddRecs in Plan's entry (#209921)
Extend VPSCEVExpander to expand AddRecs in the Plan's entry. In the
general case, an AddRec's loop header refers to a BasicBlock that is no
longer in the Plan, and we have to fall back to the IR SCEV expander.
However, when the Plan's entry has a canonical IV that we can re-use as
a VPIRPhi, expand the AddRec to VPInstructions.
