LLVM/project 52d922amlir/include/mlir/Dialect/SPIRV/IR CMakeLists.txt, mlir/lib/Dialect/SPIRV/IR SPIRVDialect.cpp CMakeLists.txt

[MLIR][spirv] Shard generated operation definitions (NFC) (#221811)

Generate SPIR-V operation definitions in eight shards and use the
generated registration hook. Keep parser, printer, and verification
helpers in the existing implementation TU and expose them through a
private header.

Assisted-by: Codex
DeltaFile
+43-0mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinition.h
+18-22mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinition.cpp
+17-0mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinitions.cpp
+15-0mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
+8-1mlir/include/mlir/Dialect/SPIRV/IR/CMakeLists.txt
+1-5mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
+102-281 files not shown
+103-287 files

LLVM/project 93a9429llvm/include/llvm/DTLTO DTLTO.h, llvm/include/llvm/LTO LTO.h

Comments
DeltaFile
+6-9llvm/include/llvm/LTO/LTO.h
+2-10llvm/lib/LTO/LTO.cpp
+1-3llvm/lib/LTO/LTOBackend.cpp
+1-1llvm/include/llvm/DTLTO/DTLTO.h
+10-234 files

LLVM/project 1be7d4bllvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/test/MC/AMDGPU misaligned-vgpr-tuples-err.s

[AMDGPU] Route no-modifier reg-or-inline AsmParser operands through HwMode predicate

Convert the reg-or-inline operands with no modifiers (MFMA VGPR/AGPR
sources, VCSrc, v_pk_mov_b32, VOP scalar f64) from the fixed-class
isRegOrInlineNoMods to the HwMode-aware isRegOrInlineNoModsByHwMode, so an
odd-aligned tuple is rejected at the offending operand column instead of by
the validateVGPRAlign catch-all.

Co-Authored-By: Claude <noreply at anthropic.com>
DeltaFile
+53-46llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+7-7llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
+60-532 files

LLVM/project cb0e500llvm/test/CodeGen/SPIRV/hlsl-intrinsics sinh_mat.ll sqrt_mat.ll

[SPIRV] Add matrix type legalization for many float global opcodes (#220782)

fixes #220723

The issue in #220723 is that the global opcodes can not deduce the
element type when the input is a shuffle vector. This is the same issue
as #213783. All we have to do to fix this is to have deduceTypeFromUses
in the SPIRVPostLegalizer know that we need to look up the type from the
results register for these opcodes.

The secondary issue is that there were no matrix tests for any of these
global opcodes so I added them. I did not follow the template started by
the atan2 tests because those are overkill and testing way to much stuff
not related to opcode legalization.

Assisted on the tests by MAI-Code-1.1-Flash
DeltaFile
+72-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10_mat.ll
+66-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh_mat.ll
+66-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt_mat.ll
+66-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc_mat.ll
+66-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh_mat.ll
+66-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan_mat.ll
+402-014 files not shown
+1,279-020 files

LLVM/project 09f1a51llvm/test/CodeGen/X86 active_lane_mask.ll

[X86] Add basic llvm.get.active.lane.mask test coverage (#221978)
DeltaFile
+5,248-0llvm/test/CodeGen/X86/active_lane_mask.ll
+5,248-01 files

LLVM/project a4e8604clang/lib/Format UnwrappedLineParser.cpp, clang/unittests/Format FormatTestVerilog.cpp

[clang-format] Recognize the signed modifier for Verilog struct (#219694)

after

```SystemVerilog
struct packed signed {
  int a;
} pack1;
```

before

```SystemVerilog
struct packed signed { int a; }
pack1;
```
DeltaFile
+21-0clang/unittests/Format/FormatTestVerilog.cpp
+3-1clang/lib/Format/UnwrappedLineParser.cpp
+24-12 files

LLVM/project ff55cb3llvm/include/llvm/Target TargetOptions.h, llvm/lib/Target/PowerPC PPCISelLowering.cpp PPCTargetMachine.cpp

CodeGen: Remove TargetOptions::PPCGenScalarMASSEntries

This was PPC specific and wasn't directly written by a generic cl::opt.
It also was inappropriately written based based on a check of the flag
in the TargetPassConfig, which is only likely to be the first use.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+2-6llvm/include/llvm/Target/TargetOptions.h
+2-4llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+4-1llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+8-113 files

LLVM/project b10dc27lld/test/ELF/lto cache.ll thinlto-cache.ll, llvm/include/llvm/LTO/legacy LTOCodeGenerator.h

[lld] Add caching for `--lto-partitions`

Add an opt-in cache for the (full) LTO partitions generated via `--lto-partitions=N` when `N > 1`.
This is primarily for AMDGPU but implemented in a target-agnostic way. The goal is to avoid recompiling entire very large modules (can be hundreds of megabytes of bitcode) if someone just changed a single function or two, which don't affect most partitions.

This uses the LTO Config hash + a hash of the bitcode module itself. This is a very conservative approach, we may be able to fine-tune it to improve cache hits if it turns out the hit rate is poor.

Solves LCOMPILER-59
DeltaFile
+122-0lld/test/ELF/lto/lto-partitions-cache.ll
+0-112lld/test/ELF/lto/cache.ll
+70-42llvm/lib/LTO/LTO.cpp
+112-0lld/test/ELF/lto/thinlto-cache.ll
+83-0llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h
+62-6llvm/lib/LTO/LTOBackend.cpp
+449-16012 files not shown
+654-22318 files

LLVM/project 305a71dlld/ELF LTO.cpp, lld/test/ELF/lto lto-partitions-cache.ll lto-partitions-cache-warnings.ll

Address comments
DeltaFile
+0-57lld/test/ELF/lto/lto-partitions-cache-warnings.ll
+21-21lld/test/ELF/lto/lto-partitions-cache.ll
+9-22lld/ELF/LTO.cpp
+8-11llvm/include/llvm/LTO/LTO.h
+9-6llvm/include/llvm/DTLTO/DTLTO.h
+6-5llvm/lib/LTO/LTO.cpp
+53-1224 files not shown
+59-13610 files

LLVM/project 7e66e78llvm/docs AMDGPUUsage.rst

Update docs
DeltaFile
+20-13llvm/docs/AMDGPUUsage.rst
+20-131 files

LLVM/project e591ef0llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll

rebase
DeltaFile
+3-0llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+3-01 files

LLVM/project a394278llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPUMemoryUtils.h, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll

Comments
DeltaFile
+4-3llvm/lib/Target/AMDGPU/SIDefines.h
+1-3llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+9-106 files

LLVM/project 5d53989llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp SIDefines.h

[AMDGPU] Add synthetic apertures and use them for barriers

Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
DeltaFile
+72-90llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+44-5llvm/docs/AMDGPUUsage.rst
+21-23llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+18-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-0llvm/lib/Target/AMDGPU/SIDefines.h
+9-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+176-1354 files not shown
+186-14010 files

LLVM/project aaa60a0llvm/docs AMDGPUUsage.rst

Comments
DeltaFile
+1-1llvm/docs/AMDGPUUsage.rst
+1-11 files

LLVM/project 83d866cllvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.h AMDGPUMemoryUtils.cpp

Comments
DeltaFile
+7-12llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+8-10llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+8-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+6-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+4-1llvm/docs/AMDGPUUsage.rst
+1-1llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
+34-243 files not shown
+38-269 files

LLVM/project cc18a34llvm/test/CodeGen/AMDGPU attributor-flatscratchinit-undefined-behavior.ll

rebase
DeltaFile
+4-4llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
+4-41 files

LLVM/project ce338dfclang/test/CodeGen target-data.c, clang/test/CodeGenOpenCL amdgpu-env-amdgcn.cl

Fix DL
DeltaFile
+2-2clang/test/CodeGen/target-data.c
+1-1clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
+3-32 files

LLVM/project 0341092llvm/lib/Target/AMDGPU AMDGPUMachineFunctionInfo.cpp, llvm/test/CodeGen/AMDGPU s-barrier-lowering-bad-absolute-symbol.ll null-named-barrier-gv.ll

comments
DeltaFile
+18-18llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+8-4llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
+1-1llvm/test/CodeGen/AMDGPU/s-barrier-lowering-bad-absolute-symbol.ll
+1-1llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
+28-244 files

LLVM/project bc65ed6lld/test/ELF/lto amdgpu.ll, llvm/lib/IR AutoUpgrade.cpp

Add DL auto-upgrade
DeltaFile
+19-11llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+4-0llvm/lib/IR/AutoUpgrade.cpp
+1-1lld/test/ELF/lto/amdgpu.ll
+24-123 files

LLVM/project b4cb3b0llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll s-barrier-signal-var-gep.ll

rebase
DeltaFile
+56-44llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
+21-14llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+77-582 files

LLVM/project 95857b8llvm/lib/IR AutoUpgrade.cpp, llvm/unittests/Bitcode DataLayoutUpgradeTest.cpp

Fix Autoupgrade
DeltaFile
+7-5llvm/lib/IR/AutoUpgrade.cpp
+4-2llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+11-72 files

LLVM/project f355d9ellvm/lib/IR AutoUpgrade.cpp, llvm/unittests/Bitcode DataLayoutUpgradeTest.cpp

Add reserved AS to autoupgrade
DeltaFile
+31-19llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+4-2llvm/lib/IR/AutoUpgrade.cpp
+35-212 files

LLVM/project 398c0dallvm/lib/Target/AMDGPU AMDGPUMachineFunctionInfo.cpp, llvm/lib/TargetParser TargetDataLayout.cpp

Rebase + comments
DeltaFile
+7-7llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+1-4llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
+2-1llvm/lib/TargetParser/TargetDataLayout.cpp
+10-123 files

LLVM/project b389763llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU amdgpu-lower-exec-sync.ll amdgpu-lower-exec-sync-and-module-lds.ll

[RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.
DeltaFile
+474-0llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+72-61llvm/test/CodeGen/AMDGPU/s-barrier.ll
+59-43llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+52-14llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+32-32llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
+32-32llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
+721-18247 files not shown
+1,174-53053 files

LLVM/project fdffea8llvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/test/CodeGen/AMDGPU fminimum3.ll fmaximum3.ll

[AMDGPU] Prefer packed minimum/maximum ops for two-input ops (#215449)

A two-input f16 fminimum or fmaximum operation should translate to a
packed two-input minimum/maximum instruction when the target supports
one.

It currently can be selected through the minimum3/maximum3 fallback
pattern instead. That emits a three-input instruction with one input
operand duplicated.

Keep the fallback for nested min/max expressions that can use the real
three-input instruction. Add a higher-priority direct pattern for
non-nested two-input operations on targets with packed IEEE
minimum/maximum opcodes.
DeltaFile
+23-56llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
+23-56llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
+32-0llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+9-9llvm/test/CodeGen/AMDGPU/fminimum3.ll
+9-9llvm/test/CodeGen/AMDGPU/fmaximum3.ll
+96-1305 files

LLVM/project 27bb4d2mlir/lib/Dialect/Vector/Transforms VectorDropLeadUnitDim.cpp, mlir/test/Dialect/Vector vector-dropleadunitdim-transforms.mlir

[mlir][vector] Update `CastAwayTransfer{Read|Write}LeadingOneDim` (#219499)

Updates `CastAwayTransfer{Read|Write}LeadingOneDim` to use
`vector.shape_cast`, rather than `vector.extract`, as the canonical form
for stripping unit dimensions.

This change was originally implemented by @krzysz00 in #196206, but was
subsequently reverted in #199546. This PR intentionally restores only a
subset of #196206, making it easier to identify and triage any potential
regressions.

Co-authored-by: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
DeltaFile
+25-37mlir/lib/Dialect/Vector/Transforms/VectorDropLeadUnitDim.cpp
+6-6mlir/test/Dialect/Vector/vector-dropleadunitdim-transforms.mlir
+31-432 files

LLVM/project c4babfbllvm/docs ReleaseNotes.md

[Docs] Document persistent metadata printing (#220967)

Document how persistent metadata IDs affect intermediate and standalone
textual output. Final assembly output remains canonically renumbered.

Follow-up to #220390.
DeltaFile
+20-0llvm/docs/ReleaseNotes.md
+20-01 files

LLVM/project 08a32ballvm/lib/Target/RISCV/GISel RISCVInstructionSelector.cpp, llvm/test/CodeGen/RISCV/GlobalISel load-store.ll

[RISCV][GlobalISel] Fold large constant offsets in selectAddrRegImm (#219161)

Fold ADDI adjustment (AddiPair) for offsets in [-4096, 4094] and split
larger constants into materialized Hi + Lo12 offset, matching SDAG. Add
isWorthFoldingAdd to guard the split and extract the shared ADDI
renderer into renderAddiPair.

Assisted-by: Claude
DeltaFile
+641-0llvm/test/CodeGen/RISCV/GlobalISel/load-store.ll
+97-53llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+738-532 files

LLVM/project f20b6e5lldb/include/lldb/Target Process.h, lldb/source/Target Process.cpp

[lldb] Remove return value from RemoveBreakpointOpcodesFromBuffer (#221979)

It was never set to anything and the one caller ignored it.
DeltaFile
+23-25lldb/source/Target/Process.cpp
+2-2lldb/include/lldb/Target/Process.h
+25-272 files

LLVM/project 651d01eclang/lib/AST StmtPrinter.cpp, clang/unittests/AST TypePrinterTest.cpp

[clang][AST] Fix infinite recursion when printing fully qualified template parameters (#219044)

This fixes an infinite recursion crash that was introduced in #206041.

When printing a `DeclRefExpr` using
`PrintingPolicy::FullyQualifiedName`, we were previously trying to print
the fully qualified name of all decls. However, when the decl is a
template parameter, its `DeclContext` is the template specialization
itself. If a template specialization's arguments depend on that same
template parameter (e.g., `template<int Count> struct
View<int[Count]>`), attempting to print the qualified name forces Clang
to recursively evaluate the enclosing context. This led to unbounded
recursion (`View<int[Count]>::Count` ->
`View<int[View<int[Count]>::Count]>::Count` and so on). Since template
parameters are inherently scoped to their template declarations and do
not require a fully qualified name, this patch resolves the issue by
skipping `printQualifiedName` if the decl is a template parameter
(`!VD->isTemplateParameter()`).

Fixes #218076.
DeltaFile
+18-0clang/unittests/AST/TypePrinterTest.cpp
+2-1clang/lib/AST/StmtPrinter.cpp
+20-12 files