[AArch64][Bitcode] Use target memory for SME state (#205829)
Model AArch64 ZA and ZT0 intrinsic state using target_mem instead of
inaccessiblemem.
Bump the bitcode memory-attribute encoding and upgrade old AArch64
bitcode so prior inaccessiblemem effects are preserved on the new target
memory locations. Non-AArch64 bitcode keeps the old interpretation.
[Clang] Require X86 backend for some coroutine tests (#207681)
The wrapper functions are generated without target features.
They can still be inlined based on target-specific logic, but this
requires the target to be available.
We should fix this by properly generating the target features,
but for now add a REQUIRES to unbreak the tests.
[NVPTX] Add missing Range attr to tensormap.replace intrinsics. (#207099)
Add missing `Range=[0, 5)` for `%ord imm` operand in
`nvvm.tensormap.replace` intrinsics.
[mlir][memref] Implement ValueBoundsOpInterface for memref.extract_strided_metadata/assume_alignment (#206466)
Add ValueBoundsOpInterface external models for memref.assume_alignment
and memref.extract_strided_metadata, so dimension and metadata bounds
can be propagated through these view-like ops during value-bounds
analysis.
[AArch64] Fold -smin/-smax(X,0) to neg + masked AND
smin(X, 0) lowers to X & M and smax(X, 0) to X & ~M, where M is X
arithmetically shifted right by the bit width minus one (a 0 or -1 sign
mask). When negation is applied, -(X & M) is equivalent to (-X) & M. The
latter form is slightly better because the shift no longer depends on the
negation and the two can issue in parallel. Instruction count is unchanged.
The fold is suppressed when the result feeds a comparison because then the
negation is folded into a cmn for free. This covers the compare feeding a
SETCC, SELECT_CC, or BR_CC.
smin: https://alive2.llvm.org/ce/z/SfmPfH
smax: https://alive2.llvm.org/ce/z/_lVM0r
Assisted-by: Opus 4.8
[libc++abi] Always enable -fvisibility=hidden (#207333)
Building with `-fvisibility=hidden` is generally a good idea, since it
avoids unnecessary relocations when loading a dylib. For libc++abi this
should be a no-op, since most things are annotated explicitly. By
enabling `-fvisibility=hidden` we can remove these explicit annotations
however.
[LoongArch] Remove inaccurate LASX conversion pattern and use [X]VFFINT.S.L instead (#207107)
Original LASX signed/unsigned 64-bit integer & floating point will
suffer from double rounding issue, due to it implements such logic: `i64
-> double -> float` that will lead to precision loss. So delete it and
introduce the `[X]VFFINT.S.L` instruction, which could convert 4 or 8
signed 64-bit integer into float in one instrunction.
Also, create the `MergeBlocksConvert` helper function to reuse the logic
about merge two blocks into one, avoid unnecessary code size bloat.
[libc++] Split the multidimensional algorithms out of uninitialized_algorithms.h (#207447)
While these algorithms are conceptually related to other
`uninitialized_*` algorithms, they're likely only ever going to be used
by `shared_ptr`. `uninitialized_algorithms.h` itself is also getting
rather large, so it makes sense to split the multidimensional versions
into their own header.
Fixes #207417
[InlineCost] Never inline functions with incompatible target features (#205113)
If inlining is unsound due to incompatible target feature attributes, we
should not inline the call even if alwaysinline is set. This will likely
result in a crash during instruction selection.
We tried this previously in
https://github.com/llvm/llvm-project/commit/d6f994acb3d545b80161e24ab742c9c69d4bbf33,
but the change had to be reverted because the quality of our
areInlineCompatible() hooks was very bad at the time, which resulted in
inlining not happening in many cases where it was safe.
I think we're in a much better position now. Most notably, we now have a
default areInlineCompatible() implementation that actually does
something sensible (https://github.com/llvm/llvm-project/pull/117493),
inlining compatibility for target features is now specified in TableGen
(https://github.com/llvm/llvm-project/pull/205348). Various
target-specific issues have been fixed as well, e.g. ARM's overly strict
feature whitelist (https://github.com/llvm/llvm-project/pull/205763) and
X86's overly conservative ABI compatibility checks
(https://github.com/llvm/llvm-project/pull/205106).
[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic
The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.
Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:
- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
Operations use APInt arithmetic at WideBits, chosen to guarantee no
intermediate overflow:
$$
WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
$$
This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
extra bits.
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[clangd] Null-check AutoTypeLoc in CollectExtraHighlightings::VisitDeclaratorDecl (#207323)
A Decl's getType() can have a getContainedAutoType() without
its TypeSourceInfo's type having one, because the two types
can differ in type sugar such as DecltypeType which
getContainedAutoType[Loc]() deliberately does not look through.
Fixes https://github.com/llvm/llvm-project/issues/207139
[DA] Rewrite BanerjeeMIV test with safe APInt interval arithmetic
The old banerjeeMIVtest computed inequality bounds using SCEV
arithmetic on 64-bit integers. Intermediate operations like
$(A^{-} - B^{+}) \times Iterations$ could overflow i64 even when all individual
coefficients and loop bounds fit, producing unsound results.
Replace the symbolic bound machinery with a self-contained APInt
interval arithmetic implementation. Key design decisions:
- BanerjeeInterval holds [Lower, Upper] signed-inclusive bounds.
Operations use APInt arithmetic at WideBits, chosen to guarantee no
intermediate overflow:
$$
WideBits = max(8, 2 \times BaseBits + MaxLevels + 8)
$$
This is provably sufficient, each term product needs at most `2 \times BaseBits + 1`
bits, and summing across MaxLevels terms needs at most ceil($\log_2 (MaxLevels)$)
extra bits.
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[Hexagon] Allow reservation of caller saved registers via -ffixed-rXX (#205733)
Previously, hexagon allowed only callee saved registers to be reserved
since reserving caller saved regs can create problems, since it cannot
be sure that the callee (from a different module) also reserves the
register.
The responsibility of reserving register and managing it is now on the
user. However, a warning will be displayed if the user tries to reserve a
caller saved register.
---------
Co-authored-by: quic-santdas <quic_santdas at qti.qualcomm.com>
[InstCombine] Skip redundant demanded element queries in insert chains (#205948)
Avoid re-running `SimplifyDemandedVectorElts` on intermediate
`insertelement` chain nodes when a bounded scan proves the top-level
all-lanes query cannot change the IR.
The skip is implemented inside the `InsertElement` case of
`SimplifyDemandedVectorElts` and is limited to the top-level all-lanes
query (`Depth == 0 && DemandedElts.isAllOnes()`). The bounded scan
matches the existing SDVE depth window and only skips chains with
distinct in-range constant insert indices. This keeps the normal SDVE
path for duplicate indices, variable indices, out-of-range indices,
multi-use chains, and the final chain root.
This was motivated by a cutile matmul compile-time case where loop
unrolling produced 128-lane vector insert/extract chains. Before this
change, InstCombine repeatedly invoked SDVE on intermediate
`insertelement` nodes in those chains. On the representative IR, the
affected InstCombine pass time went from about `44.9 ms` to `29.8 ms`,
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[RISCV] Remove -riscv-v-fixed-length-vector-lmul-max option (#207312)
Whilst reviewing https://github.com/llvm/llvm-project/pull/207254, I
threw claude at it and it found a crash when passing in a non-default
-riscv-v-fixed-length-vector-lmul-max flag.
This option was added 5 years ago around the time initial fixed vector
support was being added in a719b667a9794, and IIUC it was added so that
support for more LMULs could be added over time.
We don't have any substantial codegen testing for it and I couldn't find
any downstream users either. So rather than trying to fix
https://github.com/llvm/llvm-project/pull/207254 to handle it it seems
easier just to remove it now that fixed vector support for RVV has
matured.
[InstSimplify] Fold value-preserving zext/sext of trunc (#204089)
Fold a value-preserving `zext (trunc nuw X)` / `sext (trunc nsw X)` back
to
`X` in `simplifyCastInst` (when the trunc source type equals the extend
result type and the no-wrap flag guarantees the round-trip is identity).
After indvars canonicalizes a min-index loop, the running-index select
has a
`trunc nuw nsw i64 %iv to i32` on its true side while `arr[i]` is
addressed
directly with the i64 `%iv`. When PHI-translating the select-dependent
address along the backedge (see #203863), the true side becomes
`gep base, zext nneg (trunc nuw %iv)`, which has no matching instruction
in
the loop, so the select dependency is never formed and the redundant
load
survives.
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