clang/ARM: Derive -pg mcount name from the triple environment
For a glibc/gnueabi ARM and AArch64 targets, GCC's -pg instrumentation
always calls __gnu_mcount_nc (with the caller pushing LR, per the "nc"
no-LR-clobber ABI). clang only produced this when -meabi=gnu was passed
explicitly; a separate gnueabi triple wrongly called plain "mcount".
On ARM, glibc's EABI profiling entry point is __gnu_mcount_nc
(sysdeps/arm/arm-mcount.S, exported since GLIBC_2.8). It does provide plain
mcount/_mcount, but only as a legacy APCS compat alias (__mcount_arm_compat,
gated on GCC_COMPAT(4,3)/SHLIB_COMPAT) that reads an APCS frame-pointer
record rather than following the EABI push-LR convention. Calling it from
EABI -pg code is thus an ABI mismatch, not the intended entry point.
Derive the GNU-vs-plain mcount name from the triple environment in addition
to the explicit -meabi=gnu, so a gnueabi target gets the correct __gnu_mcount_nc
call by default, matching GCC:
push {lr}
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[flang][OpenMP] incorrect handling for local variable in OpenMP parallel workshare firstprivate(P) (#195616)
Changes to handle "!$omp parallel workshare firstprivate(P)" where P is
an array. Handling the creation and initialization of the local copy
properly.
This also Fixes
[195337](https://github.com/llvm/llvm-project/issues/195337) .
---------
Sunil Kuravinakop <koops at hpe.com>
[GVN] Enforce MemDep/MemorySSA mutual exclusion for cl::opt overrides (#217896)
parseGVNOptions() already keeps the gvn<...> pass parameters mutually
exclusive, but the -enable-gvn-{memdep,memoryssa} cl::opt overrides
default independently. Two fixes for that path:
- Enabling MemorySSA now implies MemDep is off, so
-enable-gvn-memoryssa=true on its own no longer trips the on-demand
MemorySSA assertion.
- Explicitly enabling both is a contradiction and is now rejected with a
diagnostic instead of resolving it arbitrarily.
[ADT] Invalidate iterators on move and swap in SmallPtrSet and StringMap (#220796)
This patch adds missing incrementEpoch() calls to:
- StringMapImpl's move constructor.
- SmallPtrSetImplBase's moveHelper() (move construction and assignment).
- SmallPtrSetImplBase's swap().
This ensures that existing iterators pointing into moved-from or
swapped containers are properly invalidated in debug mode.
Assisted-by: Antigravity
[AMDGPU] Expose addressable LDS size features to TargetParser
Expose addressable LDS size through the per-GPU feature bitset without
serializing scalar settings into target-feature strings. Validate that
generic targets retain a conservative addressable size.
Change-Id: I3bc5265e190497817867fcaae16847d2eac81cf2
[CIR][NFC] Share getSuccessorRegions across region-branch ops
Six of the ten CIR ops implementing RegionBranchOpInterface reported the same
successors: any of their regions may be entered from the parent operation, and
every region exit goes back to it. Add a CIR_EnterAnyRegionBranchOpBase class
that appends that definition to the one inherited from CIR_RegionBranchOpBase,
retarget the six ops onto it and delete their hand-written definitions.
The shared definition walks getRegions() rather than naming region accessors.
For all six ops the entry regions were exactly the declared regions in
declaration order, so it reports the same successors in the same order. The doc
comments of the deleted ScopeOp and TernaryOp definitions go with them, instead
of being left behind on the neighbouring builders.
IfOp, GlobalOp, TryOp and AwaitOp stay on the base class, since their successors
depend on the operation: IfOp falls back to the parent when the else region is
empty, GlobalOp skips its optional ctor and dtor regions, TryOp iterates
variadic handler regions, and AwaitOp routes ready to resume and suspend.
[CIR][NFC] Share getSuccessorInputs across region-branch ops
The ten CIR ops implementing RegionBranchOpInterface each hand-wrote
getSuccessorInputs, and all ten bodies were equivalent: regions take no
inputs, and returning to the parent yields the parent's results. Three did
not look equivalent but are: CleanupScopeOp and CoroBodyOp returned an empty
ValueRange unconditionally and declare no results, and AwaitOp returned
region block arguments but carries NoRegionArguments, so those ranges are
always empty.
Add a CIR_RegionBranchOpBase ODS class that declares the method and generates
the single shared body through extraClassDefinition, mirroring the existing
CIR_LoopOpBase, and retarget all ten ops onto it.
The generated CIROps.h.inc is unchanged and CIROps.cpp.inc gains exactly the
ten definitions removed from CIRDialect.cpp.
[CIR] Add RegionBranchOpInterface unit tests and fix cir.await successors
Five of the ten ops implementing RegionBranchOpInterface have no unit test
coverage: cir.case, cir.cleanup.scope, cir.global, cir.await and
cir.coro.body. Add tests for all five.
Covering cir.await exposes a disagreement with its own terminator.
cir.condition terminates the ready region and reports {resume, suspend} as
its successors when the parent is an await, but AwaitOp::getSuccessorRegions
listed all three regions as entry successors and reported the parent op as
the successor of every region exit. Fix it to match cir.condition: ready is
the only entry successor, exiting ready branches to resume or suspend, and
exiting suspend or resume returns to the parent operation.
cir.await declares no results and carries NoRegionArguments, so successor
operand and input counts stay at zero along every edge and the MLIR verifier
is unaffected.
[SLP][modularisation][NFC] Move REVEC cost helpers to SLPCostAnalysis (#220594)
Move the following BoUpSLP-independent cost helpers out of
SLPVectorizer.cpp into SLPVectorizer/SLPCostAnalysis.{h,cpp}:
getMaskedDivRemCost
getScalarizationOverhead
getVectorInstrCost
getExtractWithExtendCost
These were deferred from the earlier SLPCostAnalysis extraction because
they read the SLPReVec cl::opt. SLPReVec stays static in
SLPVectorizer.cpp; the moved helpers take its value as an explicit bool
parameter. Behavior is unchanged.
Part of the SLPVectorizer.cpp modularization effort:
https://discourse.llvm.org/t/modularizing-slpvectorizer-cpp/90922
[AMDGPU] Add getLDSAllocGranule to TargetParser
Expose the LDS allocation granule from GPUKind and subarch without an
MCSubtargetInfo. Consolidate backend users on the byte-valued query while
preserving the existing feature-based mapping.
Change-Id: Ic0c9345e7657ec3c6978a646628598cb7608b390
[AMDGPU] Expose addressable LDS size features to TargetParser
Expose addressable LDS size through the per-GPU feature bitset without
serializing scalar settings into target-feature strings. Validate that
generic targets retain a conservative addressable size.
Change-Id: I3bc5265e190497817867fcaae16847d2eac81cf2
[flang][OpenMP] Lower DO, SIMD, and DO SIMD metadirective variants (#218555)
A standalone metadirective and its associated loop are represented as
sibling PFT evaluations. For example:
```
!$omp metadirective &
!$omp& when(user={condition(flag)}: do) &
!$omp& otherwise(nothing)
do i = 1, n
a(i) = i
end do
```
has the following evaluation shape:
```
METADIRECTIVE
DO
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