[X86] Emit ADD instead of SHL by 1 when shrinking TEST with a mask (#217508)
The immediate-TEST shrink rewrites (and x, 0x7fffffffffffffff) == 0 into
SHL64ri $1 + TEST64rr, expecting the redundant TEST to be "subsequently
eliminated" (per the comment). For shift amounts 1-3 it never is:
isDefConvertible() rejects those SHLs so that they stay convertible to
LEA, and the dead TEST survives into final binaries.
Emit ADD64rr x, x instead when the shift amount is 1. Doubling is value-
and ZF-identical to the shift at the same encoding length, executes on
more ports, and ADDrr is def-convertible, so the peephole really does
fold the TEST away, leaving add+jcc/setcc instead of shl+test+jcc/setcc.
The shape is common: it is Rust libstd's panic-counter fast path
(GLOBAL_PANIC_COUNT & ~(1 << 63) == 0, inlined at every
std::thread::panicking() check -- 249 copies in uutils coreutils) and
LLVM's own is_fpclass zero-class lowering, as the is_fpclass.ll diff
shows.
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[mlir][SparseTensor] Use split discardable/inherent attribute APIs (#218904)
Migrate SparseTensor IR, lowering, code generation, and loop emission to
explicit discardable or operation-specific attribute access.
Assisted-by: Codex
[mlir][Func][Async][EmitC] Use split discardable/inherent attribute APIs (#218905)
Use operation-specific accessors and explicit discardable attribute APIs
in the Func, Async, and EmitC dialects and their associated conversions.
Assisted-by: Codex
[AMDGPU] Fix unsaturated add when moving 64-bit ctlz/cttz to the VALU (#216707)
The ffbh/ffbl add is saturated via a clamp modifier, but on gfx6/7/8 it
lowers to V_ADD_CO_U32_e32, which has no clamp operand, so
ctlz/cttz.i64(0, false) returns 31 instead of 64 there
ffbh/ffbl only produce 0..31 or -1, so uaddsat(x, 32) is just x | 32
Use V_OR_B32_e32 instead, which needs no clamp and works everywhere
[MLIR][Shape] Enable strict property assembly format (#218903)
Enable the strict properties assembly format mode for the Shape dialect.
Bind the broadcast diagnostic attribute directly. Keep its optional
clause unambiguous after variadic operands, and cover the custom and
rejected attr-dict spellings.
Assisted-by: Codex
[mlir][LLVM] Verify that constant attribute and result types match
`llvm.mlir.constant` only checked that the kind of the value attribute suits
the kind of the result type, never that the types themselves agree. All of the
following verified:
%0 = llvm.mlir.constant(1 : index) : i64
%1 = llvm.mlir.constant(1 : i8) : i16
%2 = llvm.mlir.constant(dense<1> : vector<4xi32>) : vector<4xi64>
Translation ignores the attribute type and uses the result type, so the
attribute type was effectively decorative for integers, and passes that read it
back could observe a type that has nothing to do with the value.
Require exact type equality for integer attributes and exact element type
equality for integer elements attributes, mirroring the `AllTypesMatch`
constraint `arith.constant` gets from ODS. The op cannot use that trait itself
because `value` is an `AnyAttr` that also holds `StringAttr` and `ArrayAttr`.
The element type check is also run on the scalable vector path, which
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CodeGen: Fix MachineCSE PRE insert point with SUCC_ARGS
Hoist to getBlockEndInsertPt() instead of getFirstTerminator(), so a hoisted
instruction lands before the SUCC_ARGS cluster rather than inside it.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
MachineLICM: Fix preheader insertion point with SUCC_ARGS
Hoist loop-invariant instructions to getBlockEndInsertPt() instead of
getFirstTerminator(), so they land before the SUCC_ARGS cluster rather
than inside it.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
CodeGen: Represent block arguments on MachineBasicBlock
The receiver half of the block-argument representation: a block declares a list
of virtual registers that receive values forwarded by each predecessor's
SUCC_ARGS. Unlike a PHI, a block argument is defined by the block itself, not by
an instruction.
MachineBasicBlock holds the argument list, printed and parsed as an "arguments:"
block header line. MachineRegisterInfo maps each argument to its defining block,
so getDefBlock works for these registers. The verifier treats an argument as
defined at block entry and requires each predecessor to supply one matching
SUCC_ARGS.
This is only building infrastructure, and is not yet used.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
CodeGen: Add SUCC_ARGS pseudo-instruction
The sender half of a block-argument representation for Machine IR: a
"reverse PHI" that forwards values from a predecessor's bottom to a
successor block's arguments along one CFG edge. Operand 0 is the successor
block; the rest are the forwarded value registers, mapped positionally.
Like PHI, SUCC_ARGS is edge-specific: it must stay in its block, so it is
excluded from CSE and hoisting, and it defines no register but is not dead.
SUCC_ARGS are clustered contiguously immediately before the terminators,
mirroring how PHIs are clustered at the top of a block; the verifier
enforces this and the succ_args() range and getBlockEndInsertPt() let
consumers work with the cluster. Inert; no producer emits it yet.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
[lldb] Guard MemoryCache::ReadRanges against a short buffer (#218706)
`Process::DoReadMemoryRanges` asserts the caller's buffer is long enough
before it writes into it, and returns empty ranges when asserts are off.
`MemoryCache::ReadRanges` writes a cache hit into the same buffer with
no
such check, in `lldb/source/Target/Memory.cpp`:
```
316: results.push_back(buffer.take_front(len)); // take_front clamps 16 -> 8
317: buffer = buffer.drop_front(len); // asks to drop 16 from 8
318: memcpy(results.back().data(), cached, len); // writes 16 into 8 bytes
```
With assertions on, `MutableArrayRef::drop_front` aborts one line before
the `memcpy`, so the new test dies on the wrong message:
```
Death test: { read_results = cache.ReadRanges(ranges, short_buffer); }
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[CodeGen][DWARF][NFC] Add casts to a few asserts to avoid msvc warning. (#218386)
Fix some comparisons to correct the msvc warning: C4805: '==': unsafe
mix of type 'IntType' and type 'bool' in operation
Assisted-by: LLM.
