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[clang][TypePrinter] Replace AppendScope with printNestedNameSpecifier (#168534)

In debug-info we soon have the need to print names using the full scope
of the entity (see discussion in
https://github.com/llvm/llvm-project/pull/159592). Particularly, when a
structure is scoped inside a function, we'd like to emit the name as
`func()::foo`. `CGDebugInfo` uses the `TypePrinter` to print type names
into debug-info. However, `TypePrinter` stops (and ignores)
`DeclContext`s that are functions. I.e., it would just print `foo`.
Ideally it would behave the same way `printNestedNameSpecifier` does.
The FIXME in
https://github.com/llvm/llvm-project/blob/47c1aa4cef638c97b74f3afb7bed60e92bba1f90/clang/lib/AST/TypePrinter.cpp#L1520-L1521
motivated this patch.

See https://github.com/llvm/llvm-project/pull/168533 for how this will
be used by `CGDebugInfo`. The plan is to introduce a new
`PrintingPolicy` that prints anonymous entities using their full scope
(including function/anonymous scopes) and the mangling number.

[DAGCombiner] Strip outer match in visitBITREVERSE (NFC) (#169020)

[clang-tidy][NFC] Reformat code and set 'KeepEmptyLines' to false (#168131)

Currently, default `clang-format` LLVM style is configured like this:
```
KeepEmptyLines:
  AtEndOfFile:     false
  AtStartOfBlock:  true
  AtStartOfFile:   true
```
This PR sets `AtStartOfBlock` and `AtStartOfFile` to false.
I think this is the general style pattern we tend to follow, in
particular Eugene made comments about empty newlines at start of
functions.

[Review] Drop the caller is device condition

Revert "[ubsan_minimal] Allow UBSan handler from Minimal runtime to accept arguments (#152192)" (#168812)

This partially reverts #152192, keeping updated tests and
some code reordering in clang/lib/CodeGen/CGExpr.cpp.

compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp is exact revert
(with followup #152419)

We don't have a good use case for that, so revert it before we are stuck
maintaining this API.

21.x does not have this patch.

This reverts commit a1209d868632b8aea10450cd2323848ab0b6776a.

[IR2VEC] Rewrite triples.mir and entities.mir. NFC (#168574)

These test change and need updating every time a new instruction is
added, including generic G_ global isel instructions. The opcodes of all
instructions change force a manual update of the file, which makes it
very high cost for what it is testing.

I have rewritten it to use regexes for the triplets.mir test and just
test a couple of opcodes in the entities.mir file.

[HIP] Perform implicit pointer cast when compiling device code, not when -fcuda-is-device

When compiling HIP device code, we add implicit casts for the pointer
arguments being passed to builtin calls.

When compiling for the host, apply the same casts for __device__ or __kernel__ functions,
since the device side of the source should still pass type checks.

This patch changes the condition depending on -fcuda-is-device to depend
on if the builtin's caller is marked as __device__ or __kernel__.

stack-info: PR: https://github.com/llvm/llvm-project/pull/165387, branch: users/jmmartinez/fix/load_lds_typesignature/1

[VPlan] Drop poison-generating flags on induction trunc (#168922)

After truncating an integer-induction, neither nuw nor nsw hold.

Fixes #168902.

Co-authored-by: Florian Hahn <flo at fhahn.com>

[MLIR][XeGPU][TransformOps] Add slice_dims argument to set_op_layout_attr and set_desc_layout (#168929)

`set_op_layout_attr` and `set_desc_layout` transform ops wrap
`xegpu.layout` in an `xegpu.slice` attribute if `slice_dims` argument is
set.

[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250)

This patch enables the multi-group xnack replay mode by
configuring the hardware MODE register at kernel entry.
This aligns the hardware behavior with the compiler's
existing multi-group s_wait_xcnt insertion logic.

[MLIR][CODEOWNERS] Add XeGPU transform ops code owners (#168940)

Add charithaintc, Jianhui-Li and tkarna as code owners of XeGPU/TransformOps directories.

[mlir][llvm] Handle debug record import edge cases (#168774)

This commit enables the direct import of debug records by default and
fixes issues with two edge cases:
- Detect early on if the address operand is an argument list (calling
getAddress() for argument lists asserts)
- Use getAddress() to check if the address operand is null, which means
the address operand is an empty metadata node, which currently is not
supported.
- Add support for debug label records.

This is a follow-up to:
https://github.com/llvm/llvm-project/pull/167812

fix

[LoongArch] Custom legalize vector_shuffle to `[x]vpermi.w`

[LoongArch][NFC] Pre-commit tests for `[x]vpermi.w`

[orc-rt] Rename 'Session' variables to avoid ambiguity with type. NFCI. (#168999)

Re-using Session as a variable name risks confusion with the Session
type.

[PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for adding the vector {1, 1, 1, 1} (#160882)

This patch optimizes vector addition operations involving **`all-ones`**
vectors by leveraging the generation of vectors of -1s(using `xxleqv`,
which is cheaper than generating vectors of 1s(`vspltisw`). These are
the respective vector types.
`v2i64`: **`A + vector {1, 1}`**
`v4i32`: **`A + vector {1, 1, 1, 1}`**
`v8i16`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1}`**
`v16i8`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1}`**

The optimized version replaces `vspltisw (4 cycles)` with `xxleqv (2
cycles)` using the following identity:
`A - (-1) = A + 1`.

---------

Co-authored-by: himadhith <himadhith.v at ibm.com>
Co-authored-by: Tony Varghese <tonypalampalliyil at gmail.com>

rebase after vshuf4i_d was defined

[LoongArch] Custom legalize vector_shuffle to `xvshuf4i.d`

fix typo

[LoongArch] Custom legalize vselect to vector_shuffle for most constant condition cases

[C++20] [Modules] Check TULocal entity within exported entities

See the attached test for example.

[NVPTX] Fix PTX and SM conditions for narrow FP conversions (#168680)

This change fixes the PTX and SM conditions for narrow FP
conversion intrinsics and adds support for family-conditionals.

clang-format

[AMDGPU] Make SIShrinkInstructions pass return valid changed state

[PowerPC] Fix Wparentheses warning

PPCISelLowering.cpp:15567:27: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
15567 |          CC == ISD::SETEQ && "CC mus be ISD::SETNE or ISD::SETEQ");
      |          ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Using `memcpy` for bit pattern

clear min runtime args

Created using spr 1.3.7

[Clang][OpenMP] Bug fix Default clause variable category (#168846)

Same changes as in fix for
https://github.com/llvm/llvm-project/pull/165276 except for changes in
test case :
  1)   remove unnecessary include in test to restore Ubuntu build.
This is not needed as allocatable modifier is not applicable to the
default clause in C/C++.
2) Changes in CHECK statements to accommodate testing failure on
toolchain
builders at Google, Reported by Prabhu Rajasekaran.

---------

Co-authored-by: Sunil Kuravinakop <kuravina at pe31.hpc.amslabs.hpecorp.net>

[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)

This commit implements a complete load/store optimization pass for the
RISC-V Zilsd extension, which combines pairs of 32-bit load/store
instructions into single 64-bit LD/SD instructions when possible.
Default alignment is 8, it also provide zilsd-4byte-align feature for
looser condition.

Related work: https://reviews.llvm.org/D144002

---------

Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>