LLVM/project 7206901libc/src/__support/CPP/type_traits is_constructible.h is_assignable.h

[libc] Include correct headers in type_traits (#197691)

Otherwise we end up with errors like the following when building with
bazel:
```c++
In file included from external/+_repo_rules+llvm-project/libc/src/__support/CPP/type_traits/is_move_constructible.h:12:
external/+_repo_rules+llvm-project/libc/src/__support/CPP/type_traits/is_constructible.h:32:14: error: no template named 'bool_constant'
   32 |     : public bool_constant<__is_constructible(T, Args...)> {};
```
DeltaFile
+1-1libc/src/__support/CPP/type_traits/is_constructible.h
+1-1libc/src/__support/CPP/type_traits/is_assignable.h
+2-22 files

LLVM/project d1a6d7bllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/AArch64 aarch64-mulv.ll

[DAG] SimplifyMultipleUseDemandedBits - fold (mul X, 1) -> X (#197677)

Use DemandedElts + KnownBits to match hidden identity patterns - helps
especially with reduction patterns padded by legalisation

Once #197455 has landed, I'm intending to convert this (plus
SMIN/SMAX/UMIN/UMAX and the existing ISD::ADD case) to use
isIdentityElement directly.
DeltaFile
+14-23llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+13-13llvm/test/CodeGen/X86/srem-vector-lkk.ll
+10-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+3-6llvm/test/CodeGen/AArch64/aarch64-mulv.ll
+2-2llvm/test/CodeGen/X86/dpbusd_const.ll
+42-445 files

LLVM/project 2a110felldb/source/Plugins/Process/Utility RegisterContextWindows_x86_64.cpp

[lldb][windows] fix x86_64 arg register mapping for lldb-server (#197663)
DeltaFile
+6-6lldb/source/Plugins/Process/Utility/RegisterContextWindows_x86_64.cpp
+6-61 files

LLVM/project 290d0f6llvm/test/Transforms/LoopVectorize/AArch64 sve-interleaved-accesses.ll sve-interleaved-masked-accesses.ll

[LV][NFC] Remove instcombine from RUN lines in AArch64 tests (#197448)

This PR continues other work I've been doing trying to remove
unnecessary extra passes from the RUN lines in order to make it easier
to map the expected vectoriser output to the CHECK lines. As a result it
has exposed some potential optimisations that we may be able to perform
in VPlan.

Here is a summary of the changes I've noticed:

1. instcombine likes to canonicalise GEPs into certain forms. I'm not
sure if there is value in VPlan trying to guess what the canonical form
should be.
2. In tests like sve-cond-inv-loads.ll, etc. the pattern sub(urem) is
often replaced with and(sub). This is potentially something the
vectoriser could improve although I don't know if it would change the
cost model.
3. There is poor codegen in gather_nxv4i32_ind64_stride2 in the file
sve-gather-scatter.ll, which is due to

    [19 lines not shown]
DeltaFile
+176-182llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
+141-143llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
+85-82llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+70-53llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll
+68-47llvm/test/Transforms/LoopVectorize/AArch64/reduction-small-size.ll
+47-37llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
+587-54411 files not shown
+756-68817 files

LLVM/project d2de1d2clang/include/clang/Basic BuiltinsPPC.def, clang/test/CodeGen/PowerPC builtins-ppc-dmf.c ppc-dmf-mma-builtin-err.c

[PowerPC] Update base crypto builtins and intrinsics (#197017)

Update the base crypto builtins and LLVM intrinsics to drop the mma_
prefix. Also fix the builtin definitions for dmsha2hash, dmsha3hash,
and dmxxshapad to use the correct immediate constraints.
DeltaFile
+33-33clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c
+17-17llvm/test/CodeGen/PowerPC/mmaplus-crypto.ll
+15-15clang/include/clang/Basic/BuiltinsPPC.def
+15-0clang/test/Sema/builtins-ppc-crypto.c
+6-6clang/test/CodeGen/PowerPC/ppc-dmf-mma-builtin-err.c
+3-3clang/test/Sema/PowerPC/ppc-dmf-mma-builtin-err.c
+89-744 files not shown
+99-8410 files

LLVM/project 16b2ef3llvm/include/llvm/CodeGen MachineOutliner.h, llvm/lib/CodeGen RegisterScavenging.cpp LiveRegUnits.cpp

[CodeGen] Debug insns must not affect liveness analysis (#193104)

Register references in debug instructions can affect LiveRegUnits
analysis. Skip over debug instructions.

Tests in this PR would fail due to calls to LiveRegUnits::stepBackward
in RegisterScavenging, DeadMachineInstructionElim, and
AArch64InstrInfo.cpp getOutlinableRanges().

Other call-sites to stepBackward may also pass debug instructions to
LiveRegUnits::stepBackward, but LIT testing did not fail when
-debugify-and-strip-all-safe was enabled by default.

---------

Signed-off-by: John Lu <John.Lu at amd.com>
DeltaFile
+25-0llvm/test/CodeGen/AMDGPU/debug-independence-dead-mi-elimination.mir
+4-2llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+2-2llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
+2-1llvm/lib/CodeGen/RegisterScavenging.cpp
+3-0llvm/lib/CodeGen/LiveRegUnits.cpp
+2-1llvm/include/llvm/CodeGen/MachineOutliner.h
+38-68 files not shown
+49-814 files

LLVM/project 439e422flang/lib/Frontend CompilerInvocation.cpp

lowerCamelize variable names
DeltaFile
+12-12flang/lib/Frontend/CompilerInvocation.cpp
+12-121 files

LLVM/project 5fc2cd4flang/docs ReleaseNotes.md

Update release notes
DeltaFile
+1-1flang/docs/ReleaseNotes.md
+1-11 files

LLVM/project e42de9dllvm/docs GettingInvolved.rst

[docs] Add the Clang Static Analysis WG to sync-ups (#197679)

See
https://discourse.llvm.org/t/rfc-forming-a-static-analysis-working-group-in-the-clang-ecosystem/90719/17
DeltaFile
+5-0llvm/docs/GettingInvolved.rst
+5-01 files

LLVM/project e39b020clang/include/clang/AST DeclTemplate.h TypeBase.h, clang/lib/AST DeclTemplate.cpp ASTContext.cpp

[clang] NFC: add asserts enforcing template parameters have valid positions

Some tests are violating these assertions, so they are commented out.

For the test in `clang/test/SemaTemplate/concepts.cpp`, that was broken by #195995
and needs a partial revert at least.
DeltaFile
+25-34clang/include/clang/AST/DeclTemplate.h
+14-15clang/lib/AST/DeclTemplate.cpp
+6-3clang/lib/AST/ASTContext.cpp
+7-2clang/include/clang/AST/TypeBase.h
+5-2clang/test/SemaTemplate/concepts-lambda.cpp
+3-1clang/test/SemaTemplate/concepts.cpp
+60-572 files not shown
+64-608 files

LLVM/project 7c7ed92clang/lib/Sema SemaTemplateDeductionGuide.cpp, clang/test/AST ast-dump-ctad-alias.cpp

[clang] CTAD: fix transformation of template template parameters (#197611)

This fixes the CTAD template parameter transforms so they produce
template template parameters which have correct depth for their own
template parameters.

This also stops calling SubstDecl directly on the non-type template
parameters, so that a template parameter with correct position is
produced directly, instead of manually fixing that up later. This helps
#197598 by making it possible to add assertions that the positions are
always valid.
DeltaFile
+151-23clang/lib/Sema/SemaTemplateDeductionGuide.cpp
+2-2clang/test/SemaTemplate/deduction-guide.cpp
+1-1clang/test/AST/ast-dump-ctad-alias.cpp
+154-263 files

LLVM/project ca3a210llvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp, llvm/test/CodeGen/AArch64/GlobalISel legalizer-info-validation.mir

[AArch64][GlobalISel] Add always legal action builders. (#197238)

This defined some always legal actions, removing our dependency on the
Legacy ruleset in aarch64.
DeltaFile
+9-8llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+5-0llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+14-82 files

LLVM/project 7415c04llvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp GCNSubtarget.h

[AMDGPU][NFC] Remove redundant hasMadU64U32NoCarry helper

Use hasMadNC64_32Insts() (backed by SubtargetFeature) for MAD 64_32
no-carry and drop the old helper.
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+0-4llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+3-73 files

LLVM/project c4054b5llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize pr37248.ll multi_early_exit.ll

[VPlan] Simplify BCast with onlyScalarsUsed (#195444)
DeltaFile
+21-27llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll
+1-4llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll
+1-4llvm/test/Transforms/LoopVectorize/X86/pr109581-unused-blend.ll
+1-4llvm/test/Transforms/LoopVectorize/pr37248.ll
+4-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-2llvm/test/Transforms/LoopVectorize/multi_early_exit.ll
+29-416 files

LLVM/project f816732llvm/test/CodeGen/AMDGPU andorn2.ll

[AMDGPU][NFC] Autogenerate checks in andorn2.ll (#197613)

For this PR: https://github.com/llvm/llvm-project/pull/196325
DeltaFile
+463-36llvm/test/CodeGen/AMDGPU/andorn2.ll
+463-361 files

LLVM/project 4e2ad71llvm/lib/Target/AMDGPU AMDGPUAsmPrinter.cpp, llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUTargetStreamer.cpp

[NFC] Format two AMDGPU files (#197672)

- `llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp`
- `llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp`
DeltaFile
+19-17llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+16-8llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+35-252 files

LLVM/project 508e8c5llvm/lib/Analysis TargetTransformInfo.cpp, llvm/test/Analysis/UniformityAnalysis/AMDGPU nodivergencesource.ll

[UniformityAnalysis] Fix nodivergencesource calls (#197656)

NFC #168903 introduced a subtle behavior change for calls with the
nodivergencesource attribute and divergent operands.

Calls with the nodivergencesource attribute are *not* always uniform.
They just do not introduce any new divergence. If any operand is
divergent,
the result must still be reported as divergent.

Revert to pre-#168903 behavior by allowing the standard propagation to
work for target's NeverUniform while keeping Default and AlwaysUniform
unchanged.
DeltaFile
+15-0llvm/test/Analysis/UniformityAnalysis/AMDGPU/nodivergencesource.ll
+5-4llvm/lib/Analysis/TargetTransformInfo.cpp
+20-42 files

LLVM/project ffb2cfcllvm/lib/ProfileData InstrProf.cpp

feedback

Created using spr 1.3.7
DeltaFile
+4-7llvm/lib/ProfileData/InstrProf.cpp
+4-71 files

LLVM/project 5f5435ellvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel zextload.ll legalize-sextload-global.mir

AMDGPU/GlobalISel: Legalize scalar extloads with large memory type (#197648)

Add narrowScalar for scalar sext/zextload when the memory type is
larger then 32 bits. There is no narrow scalar implementation when
NarrowSize < MemSize (split load) but we don't want that anyway.
Narrow scalar to MemSize creates large normal load + extension to dst.
DeltaFile
+52-0llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
+10-5llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
+8-5llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
+7-0llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+77-104 files

LLVM/project 981f42ellvm/unittests/ADT SmallVectorTest.cpp

address comments
DeltaFile
+1-3llvm/unittests/ADT/SmallVectorTest.cpp
+1-31 files

LLVM/project 84ac884llvm/test/CodeGen/AArch64 bf16-v8-instructions.ll, llvm/test/CodeGen/AMDGPU/GlobalISel sdivrem.ll

Merge branch 'main' into users/shiltian/single-line-brace-rule
DeltaFile
+7,584-740llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+8,195-0llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
+8,182-0llvm/test/MC/AMDGPU/gfx13_asm_vop3-fake16.s
+6,862-0llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-sve-instructions.s
+3,436-2,769llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
+4,686-918llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
+38,945-4,4275,019 files not shown
+272,072-97,6265,025 files

LLVM/project d7f8673llvm/lib/Analysis GlobalsModRef.cpp LazyValueInfo.cpp

[NFC][Analysis] Use `isa<ConstantPointerNull>` for null pointer checks (#197544)

Make Analysis null pointer checks use `isa<ConstantPointerNull>` rather
than generic null value checks (`isNullValue()`).
DeltaFile
+3-2llvm/lib/Analysis/GlobalsModRef.cpp
+4-0llvm/lib/Analysis/LazyValueInfo.cpp
+7-22 files

LLVM/project 25c8999libc/src/__support/CPP/type_traits is_constructible.h is_assignable.h, libc/src/__support/FPUtil rounding_mode.h

[libc] Fix shared math for gcc-7 or older compatibility. (#197476)

- Add gcc-7 or older compatibility for cpp::is_assignable and
cpp::is_constructible.
- Apply LIBC_CONSTEXPR to FPUtil/rounding_mode.h
DeltaFile
+65-0libc/src/__support/CPP/type_traits/is_constructible.h
+63-0libc/src/__support/CPP/type_traits/is_assignable.h
+18-0libc/src/__support/macros/attributes.h
+5-5libc/src/__support/FPUtil/rounding_mode.h
+3-4libc/src/__support/CPP/type_traits/is_copy_assignable.h
+3-4libc/src/__support/CPP/type_traits/is_move_assignable.h
+157-134 files not shown
+165-1910 files

LLVM/project b5d577dllvm/lib/Target/RISCV RISCVRegisterInfo.cpp, llvm/test/CodeGen/RISCV local-stack-slot-allocation.ll

[RISCV] Check SP-relative offset in needsFrameBaseReg when FP offset overflows (#197368)

When a frame pointer is present, `needsFrameBaseReg` previously only
checked the FP-relative offset to decide if a virtual base register was
needed. If the worst-case FP offset exceeded the 12-bit immediate range,
a base register was always materialized, even when the SP-relative
offset would fit.

Since `getFrameIndexReference` can now select SP over FP when the offset
fits in the compressed instruction immediate range, also check the
SP-relative offset before deciding a base register is needed. This
avoids unnecessary base register materialization and results in some
code size savings.
DeltaFile
+17-18llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
+7-1llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+2-3llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
+26-223 files

LLVM/project 3ed8aa3llvm/lib/Target/AMDGPU AMDGPUAsmPrinter.cpp, llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUTargetStreamer.cpp

[NFC] Format two AMDGPU files

- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
DeltaFile
+19-17llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+16-8llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+35-252 files

LLVM/project d730ab7clang/test/OpenMP declare_target_local_codegen.cpp spirv_target_teams_reduction_addrspace.c, mlir/test/Target/LLVMIR omptarget-teams-distribute-reduction-array-descriptor.mlir openmp-target-launch-device.mlir

fixes after merge
DeltaFile
+3-3clang/test/OpenMP/declare_target_local_codegen.cpp
+2-2mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction-array-descriptor.mlir
+2-2mlir/test/Target/LLVMIR/openmp-target-launch-device.mlir
+1-1clang/test/OpenMP/spirv_target_teams_reduction_addrspace.c
+1-1mlir/test/Target/LLVMIR/omptarget-region-device-llvm.mlir
+1-1offload/plugins-nextgen/common/src/PluginInterface.cpp
+10-101 files not shown
+11-117 files

LLVM/project c5695b8libc/src/__support/OSUtil/linux/syscall_wrappers mkdir.h chmod.h

[libc] prefer *at syscalls in sys/stat wrappers (#195792)

  - so the changes flips the #ifdef order to prefer the *at syscalls over normal ones.
  - In modern architectures, *at system calls are preferred over normal
    system calls.
  - so by checking for "*at" sys calls first, we ensure better
    compatibility with modern systems.
  - then normal syscalls moved to else for support of older ones.

Signed-off-by: udaykiriti <udaykiriti624 at gmail.com>
DeltaFile
+3-3libc/src/__support/OSUtil/linux/syscall_wrappers/mkdir.h
+3-3libc/src/__support/OSUtil/linux/syscall_wrappers/chmod.h
+6-62 files

LLVM/project 5366692libc/src/__support/OSUtil/linux/syscall_wrappers accept4.h accept.h, libc/src/sys/socket/linux sendto.cpp recvfrom.cpp

[libc] Remove legacy SYS_socketcall fallbacks (#197189)

This patch removes legacy SYS_socketcall fallback paths from all Linux
socket entry points. The individual syscall entry points were
[added](https://github.com/torvalds/linux/commit/9dea5dc921b5f4045a18c63eb92e84dc274d17eb)
in linux 4.3 (on x86, other architectures have had them even sooner).
Our policy is to support the lowest kernel version on
https://kernel.org/, which is 5.10 as of this writing.

This is motivated by the problems in

[testing](https://github.com/llvm/llvm-project/pull/196903#pullrequestreview-4263553670)
the fallback paths -- to make sure this even builds, one needs to get a
hold of very old kernel headers, or otherwise hack its build to force it
to select the fallback path.

New ABIs don't have the accept syscall (only accept4), so I've added an
accept->accept4 fallback.

Assisted by Gemini.
DeltaFile
+2-16libc/src/sys/socket/linux/sendto.cpp
+2-16libc/src/sys/socket/linux/recvfrom.cpp
+4-12libc/src/sys/socket/linux/send.cpp
+4-12libc/src/sys/socket/linux/recv.cpp
+1-15libc/src/__support/OSUtil/linux/syscall_wrappers/accept4.h
+5-11libc/src/__support/OSUtil/linux/syscall_wrappers/accept.h
+18-8210 files not shown
+26-21116 files

LLVM/project 9371564libc/src/__support/math exp10m1f.h

[libc][math] Fix exp10m1f(-0) in SKIP_ACCURATE_PASS mode (#197650)

exp10m1f(-0) should return -0, just like expm1f does. But if you build
with the LIBC_MATH_SKIP_ACCURATE_PASS flag, it accidentally returned +0,
and failed the src.math.smoke.exp10m1f_test test.

The check for -0 is normally done by EXP10M1F_EXCEPTS_LO, a list of
cases that are misrounded by the calculation in the branch for small
input values. In SKIP_ACCURATE_PASS, that list is omitted, trading off
accuracy for code size. But the check for -0 went with them. The fix is
to reinsert that in a `#else` clause, if the list isn't included.
DeltaFile
+9-0libc/src/__support/math/exp10m1f.h
+9-01 files

LLVM/project 21a8d85lldb/source/Plugins/Process/FreeBSD NativeRegisterContextFreeBSD_arm64.cpp, lldb/source/Plugins/Process/Linux NativeRegisterContextLinux_arm64.cpp NativeRegisterContextLinux_loongarch64.cpp

[lldb] Member initialise hardware breakpoint structures (#197127)

These are delcared in NativeRegisterContextDBReg so we should zero-init
them there rather than have everyone memset them later.

ppc64le has its own equivalent that I've made the same change to.
DeltaFile
+2-2lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg.h
+0-3lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+0-3lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp
+0-3lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
+1-1lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.h
+0-2lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
+3-141 files not shown
+3-157 files