LLVM/project 8539dcallvm/include/llvm/MC MCAsmInfo.h, llvm/lib/MC MCAsmInfo.cpp

[MC] Consistent use of inline field initializers in MCAsmInfo (#183343)

DeltaFile
+3-3llvm/include/llvm/MC/MCAsmInfo.h
+0-4llvm/lib/MC/MCAsmInfo.cpp
+3-72 files

LLVM/project a5f52b0llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,976 files not shown
+394,965-143,0555,982 files

LLVM/project b2430bbllvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,976 files not shown
+394,965-143,0555,982 files

LLVM/project c7103a4llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,976 files not shown
+394,965-143,0555,982 files

LLVM/project 85a73a6llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,976 files not shown
+394,965-143,0555,982 files

LLVM/project 812a378llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,995 files not shown
+395,998-143,0896,001 files

LLVM/project ac0d3e6llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,995 files not shown
+395,998-143,0896,001 files

LLVM/project 90bbc06clang/docs ClangIRCleanupAndEHDesign.md, clang/lib/CIR/Dialect/Transforms IdiomRecognizer.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+193-0lldb/source/Plugins/ScriptInterpreter/Lua/LuaState.cpp
+0-191lldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
+102-73mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+94-55clang/docs/ClangIRCleanupAndEHDesign.md
+119-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.ll
+96-0clang/lib/CIR/Dialect/Transforms/IdiomRecognizer.cpp
+604-31967 files not shown
+1,508-75073 files

LLVM/project 33ae573clang/docs ClangIRCleanupAndEHDesign.md, clang/lib/CIR/Dialect/Transforms IdiomRecognizer.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+193-0lldb/source/Plugins/ScriptInterpreter/Lua/LuaState.cpp
+0-191lldb/source/Plugins/ScriptInterpreter/Lua/Lua.cpp
+102-73mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
+94-55clang/docs/ClangIRCleanupAndEHDesign.md
+119-0llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.ll
+96-0clang/lib/CIR/Dialect/Transforms/IdiomRecognizer.cpp
+604-31967 files not shown
+1,508-75073 files

LLVM/project ee3bb59llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Rebase, use correct macro name

Created using spr 1.3.6-beta.1
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,992 files not shown
+395,957-143,0785,998 files

LLVM/project 0de8ae1llvm/test/CodeGen/PowerPC clmul-vector.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+25,051-14,920llvm/test/CodeGen/RISCV/clmul.ll
+16,004-0llvm/test/MC/AMDGPU/gfx13_asm_vopd3.s
+13,198-0llvm/test/CodeGen/RISCV/clmulr.ll
+12,863-0llvm/test/CodeGen/RISCV/clmulh.ll
+8,874-0llvm/test/CodeGen/PowerPC/clmul-vector.ll
+3,298-3,437llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+79,288-18,3575,991 files not shown
+395,954-143,0765,997 files

LLVM/project fa3b86bllvm/lib/Target/RISCV RISCVMoveMerger.cpp, llvm/test/CodeGen/RISCV rv32-move-merge.ll double-round-conv-sat.ll

[RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (#182416)

Extends RISCVMoveMerger to identify adjacent 32-bit moves that can be
combined into a single 64-bit move instruction. In particular, this
patch adds support for extension zdinx (`fmv.d`) and p(`padd.dw`).

Fixes #180831
DeltaFile
+113-23llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
+46-0llvm/test/CodeGen/RISCV/rv32-move-merge.ll
+12-24llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
+10-20llvm/test/CodeGen/RISCV/double-select-icmp.ll
+26-0llvm/test/CodeGen/RISCV/rv32-merge-non-arg-reg.mir
+7-14llvm/test/CodeGen/RISCV/rv32p.ll
+214-819 files not shown
+227-10715 files

LLVM/project 5a629e6llvm/lib/Target/ARM/MCTargetDesc ARMMCAsmInfo.cpp, llvm/lib/Target/LoongArch/MCTargetDesc LoongArchMCAsmInfo.cpp

[MC] Remove redundant setting of AllowDollarAtStartOfIdentifier. NFC (#183339)

This setting defaults to false so there is no need to set it unless we
want it to be true.

This makes it easy to see at a glace which backends support this, and
matches the existing behaviour of other fields such as
`AllowAtAtStartOfIdentifier`, `AllowQuestionAtStartOfIdentifier`,
`UseAssignmentForEHBegin` and `AllowAtInName`. These are all only ever
set to true in subclasses, never false.
DeltaFile
+0-5llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
+0-3llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
+0-2llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
+0-1llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCAsmInfo.cpp
+0-1llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
+0-125 files

LLVM/project 0668d99lldb/examples/python formatter_bytecode.py

[lldb] Improve unittest invocation in formatter_bytecode.py (#183394)

DeltaFile
+1-6lldb/examples/python/formatter_bytecode.py
+1-61 files

LLVM/project 3ddabd8llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlan.h, llvm/test/Transforms/LoopVectorize vplan-based-stride-mv.ll

[VPlan] Implement VPlan-based stride speculation
DeltaFile
+945-1,055llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+277-152llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+292-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+43-0llvm/lib/Transforms/Vectorize/VPlan.h
+5-5llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+7-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1,569-1,2155 files not shown
+1,590-1,21811 files

LLVM/project 30969cclldb/test/API/tools/lldb-dap/stopped-events TestDAP_stopped_events.py

[lldb] Fix logic issue in TestDAP_stopped_events.py (#183382)

The subset should actually be the expected data because the real thread
data may have additional information.
DeltaFile
+1-1lldb/test/API/tools/lldb-dap/stopped-events/TestDAP_stopped_events.py
+1-11 files

LLVM/project 642763cmlir/lib/Dialect/AMDGPU/Transforms FoldMemRefsOps.cpp, mlir/test/Dialect/AMDGPU amdgpu-fold-memrefs.mlir

[AMDGPU] Adding FoldMemRefOpsIntoTransposeLoadOp pattern (#183330)

Before the fix we wouldn't fold a trivial expand_shape as index
computation. This will later force expand_shape to materialize into a
extract_stride_metadata and a reinterpret_cast unnecessarily. The
example below showcase the motivation of a source IR that won't be able
to fold today.

```mlir
%expanded = memref.expand_shape %buf [[0, 1], [2, 3]]
    : memref<32x128xf16, strided<[128, 1], offset: ?>, #gpu.address_space<workgroup>>
    into memref<1x32x8x16xf16, strided<..., offset: ?>, #gpu.address_space<workgroup>>
amdgpu.transpose_load %expanded[%i, %j, %k, %l]
    : memref<1x32x8x16xf16, ...> -> vector<4xf16>
```

With this pattern that matches the more generic
`FoldMemRefAliasOpsPass`, the expand_shape can now fold into
transpose_load op like other load/stores.

    [4 lines not shown]
DeltaFile
+103-0mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
+23-2mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
+126-22 files

LLVM/project 3031ba9llvm/lib/CodeGen ExpandIRInsts.cpp, llvm/test/CodeGen/AMDGPU div_v2i128.ll div_i128.ll

[CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts. (#180654)

Previously, power-of-2 div/rem operations wider than
MaxLegalDivRemBitWidth were excluded from IR expansion and left for
backend peephole optimizations. Some backends can fail to process such
instructions in case we switch off DAGCombiner.

Now ExpandIRInsts expands them into shift/mask sequences:
- udiv X, 2^C  ->  lshr X, C
- urem X, 2^C  ->  and X, (2^C - 1)
- sdiv X, 2^C  ->  bias adjustment + ashr X, C
- srem X, 2^C  ->  X - (((X + Bias) >> C) << C)

Special cases handled:
- Division/remainder by 1 or -1 (identity, negation, or zero)
- Exact division (sdiv exact skips bias, produces ashr exact)
- Negative power-of-2 divisors (result is negated)
- INT_MIN divisor (correct via countr_zero on bit pattern)


    [2 lines not shown]
DeltaFile
+69-1,283llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+255-0llvm/test/Transforms/ExpandIRInsts/X86/divrem-pow2.ll
+57-95llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
+116-9llvm/lib/CodeGen/ExpandIRInsts.cpp
+44-60llvm/test/CodeGen/AMDGPU/div_i128.ll
+34-27llvm/test/CodeGen/AMDGPU/rem_i128.ll
+575-1,4742 files not shown
+579-1,4788 files

LLVM/project 5cd6bb0clang/lib/Driver ModulesDriver.cpp

[Clang][Modules] Fix -Wunused-variable from #182182

https://lab.llvm.org/staging/#/builders/227/builds/1093
DeltaFile
+1-1clang/lib/Driver/ModulesDriver.cpp
+1-11 files

LLVM/project fd1ffdbllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 faddv-fp16.ll faddv.ll

Address comments 1

Removed:
Flags.setNoSignedZeros(true);

Because technically the produced result can be a signed zero, it just
does not matter.
DeltaFile
+48-24llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+54-0llvm/test/CodeGen/AArch64/faddv-fp16.ll
+45-0llvm/test/CodeGen/AArch64/faddv.ll
+2-3llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
+149-274 files

LLVM/project 414c666llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 faddv.ll

[AArch64] Decompose FADD reductions with known zero elements

FADDV is matched into FADDPv4f32 + FADDPv2f32p but this can be relaxed
when one element (usually the 4th) or more are known to be zero.

Before:
movi d1, #0000000000000000
mov v0.s[3], v1.s[0]
faddp v0.4s, v0.4s, v0.4s
faddp s0, v0.2s

After:
mov s1, v0.s[2]
faddp s0, v0.2s
fadd s0, s0, s1
DeltaFile
+256-0llvm/test/CodeGen/AArch64/faddv.ll
+101-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+357-02 files

LLVM/project b7ce37cllvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 arm64-cvt-simd-intrinsics.ll sve-fixed-vector-lrint.ll

Revert "[AArch64] Wrap integer SCALAR_TO_VECTOR nodes in bitcasts  (#172837)" (#183380)

This reverts commit eff183b6a7e351e10444977fc2110edc2a518e6f.

And followup commit commit 87d9dad579b9d947f6181d1736fb11e8f683e246.

Causes breakages, see
https://github.com/llvm/llvm-project/pull/172837#issuecomment-3961532435.
DeltaFile
+1-1,205llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
+533-499llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+277-246llvm/test/CodeGen/AArch64/vector-lrint.ll
+187-172llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+72-68llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
+32-47llvm/lib/Target/AArch64/AArch64InstrInfo.td
+1,102-2,23726 files not shown
+1,366-2,53332 files

LLVM/project 4a8d532clang/docs ClangIRCleanupAndEHDesign.md, clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR] Update cir::ResumeOp to require an EH token (#183192)

This updates the cir::ResumeOp operation to require an EH token operand.
We already had the token available at both locations where the operation
was being created. Adding this operand makes finding the token more
robust during CFG flattening.

This change was entirely AI generated, but I have reviewed it closely.
DeltaFile
+11-9clang/include/clang/CIR/Dialect/IR/CIROps.td
+7-7clang/test/CIR/Transforms/flatten-cleanup-scope-eh.cir
+5-5clang/docs/ClangIRCleanupAndEHDesign.md
+4-4clang/test/CIR/IR/invalid-eh-flat.cir
+6-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+3-3clang/test/CIR/CodeGen/try-catch-tmp.cpp
+36-285 files not shown
+46-3711 files

LLVM/project 33fd75fllvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU GCNProcessors.td

[AMDGPU] Add gfx12-5-generic subtarget (#183381)

This is functionally equivalent to gfx1250.
DeltaFile
+7-0llvm/docs/AMDGPUUsage.rst
+7-0llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
+5-0llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+5-0llvm/lib/Target/AMDGPU/GCNProcessors.td
+5-0llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
+4-0llvm/lib/TargetParser/TargetParser.cpp
+33-019 files not shown
+65-225 files

LLVM/project 9f46362offload/liboffload/src OffloadImpl.cpp

[Offload] Fix type mismatch by using `uint64_t` instead of `size_t` (#183375)

The variant uses uint64_t, so should the get.
DeltaFile
+3-2offload/liboffload/src/OffloadImpl.cpp
+3-21 files

LLVM/project af2b6edflang/lib/Lower/OpenMP ClauseProcessor.cpp, flang/test/Lower/OpenMP ordered-simd.f90

[flang][openmp] Add support for ordered regions in SIMD directives (#… (#183379)

Add support for ordered regions within SIMD directives (!$omp simd
ordered and !$omp do simd ordered). This initial implementation matches
Clang's behavior.

In SIMD directives, loop induction variables have an implicit linear
clause with deferred store semantics (storing to .linear_result). To
properly support ordered regions, the LinearClauseProcessor rewrites
variable references to use .linear_result in:
- omp.ordered.region: Code inside ordered blocks
- omp_region.finalize: Code after ordered blocks

Note: The vectorizer cannot currently vectorize loops with ordered
regions. Future enhancement would require generating lane loops or
unrolling ordered regions across SIMD lanes while maintaining ordering
semantics.

This PR is a reland for https://github.com/llvm/llvm-project/pull/181012
and fixes the regression caused by syntax change in IR for linear clause
DeltaFile
+90-0mlir/test/Target/LLVMIR/openmp-wsloop-simd-ordered.mlir
+87-0mlir/test/Target/LLVMIR/openmp-simd-ordered.mlir
+57-0flang/test/Lower/OpenMP/ordered-simd.f90
+18-6mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+0-11mlir/test/Target/LLVMIR/openmp-todo.mlir
+5-0flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+257-172 files not shown
+259-188 files

LLVM/project 2981f5fllvm/test/CodeGen/Generic shadow-stack-gc-lowering.ll

[CodeGen] Add tests for ShadowStackGCLowering IR pass (#183167)

Add llvm/test/CodeGen/Generic/shadow-stack-gc-lowering.ll testing the
opt-level behavior of the shadow-stack-gc-lowering module pass,
covering:
- Single root: frame push/pop at entry and return
- Two roots: multi-slot frame, NumRoots=2/NumMeta=0 in the frame map
- Root with non-null metadata: NumMeta=1, metadata array in gc_map
- Mixed metadata: CollectRoots ordering (metadata roots sorted first)
- No roots: pass must leave the function unchanged
- Invoke: EscapeEnumerator inserts pop on both normal and unwind exits

As requested in https://github.com/llvm/llvm-project/pull/178436, since
the only existing tests seem to be that llc doesn't crash (in
llvm/test/CodeGen/X86/GC)

Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+194-0llvm/test/CodeGen/Generic/shadow-stack-gc-lowering.ll
+194-01 files

LLVM/project 66ca3ebllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 faddv-fp16.ll faddv.ll

Address comments 1

Removed:
Flags.setNoSignedZeros(true);

Because technically the produced result can be a signed zero, it just
does not matter.
DeltaFile
+49-24llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+54-0llvm/test/CodeGen/AArch64/faddv-fp16.ll
+45-0llvm/test/CodeGen/AArch64/faddv.ll
+2-3llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
+150-274 files

LLVM/project 2d108ffllvm/include/llvm/CodeGen MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp

[AMDGPU][MC] Replace shifted registers in CFI instructions

Change-Id: I0d99e9fe43ec3b6fecac20531119956dca2e4e5c
DeltaFile
+67-67llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+33-0llvm/lib/MC/MCDwarf.cpp
+15-15llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+10-0llvm/lib/CodeGen/MachineFunction.cpp
+4-4llvm/test/CodeGen/AMDGPU/debug-frame.ll
+4-0llvm/include/llvm/CodeGen/MachineFunction.h
+133-864 files not shown
+141-8810 files

LLVM/project 2ac7c3fllvm/lib/Target/AMDGPU SIFrameLowering.cpp SIMachineFunctionInfo.h, llvm/test/CodeGen/AMDGPU amdgpu-spill-cfi-saved-regs.ll

[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs

These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.

Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
DeltaFile
+2,998-0llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll
+37-12llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+11-2llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+9-0llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+7-0llvm/lib/Target/AMDGPU/SIFrameLowering.h
+2-1llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+3,064-152 files not shown
+3,067-168 files