LLVM/project 3cde605 — llvm/lib/Target/Mips MipsSERegisterInfo.cpp MipsRegisterInfo.cpp

Mips: Route ABI queries through the subtarget

MipsSubtarget::getABI() already forwards to the target machine, so every
direct MipsTargetMachine::getABI() reader can use the subtarget instead.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
DeltaFile
+4-8llvm/lib/Target/Mips/MipsMachineFunction.cpp
+4-4llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+2-4llvm/lib/Target/Mips/MipsCallLowering.cpp
+1-4llvm/lib/Target/Mips/MipsFastISel.cpp
+1-3llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
+1-3llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+13-264 files not shown
+17-3310 files

LLVM/project 96b5cc3 — llvm/include/llvm/Analysis BranchProbabilityInfo.h, llvm/lib/Analysis BranchProbabilityInfo.cpp

[BPI] Add getEdgeProbabilitiesFromWeights (NFC). (#226560)

Move computing edge probabilities from branch weights to a static
helper. This allows re-using the core logic when computing execution
frequencies in VPlan, fixing a number of subtle differences.

While touching the code, also modernize the code slightly.

Note that the helper does not handle the case where all successors are
unreachable. This would need additional info and is not needed for the
VPlan case.

PR: https://github.com/llvm/llvm-project/pull/226560
DeltaFile
+33-28llvm/lib/Analysis/BranchProbabilityInfo.cpp
+6-0llvm/include/llvm/Analysis/BranchProbabilityInfo.h
+39-282 files

LLVM/project 406b232 — llvm/lib/CodeGen DetectDeadLanes.cpp, llvm/test/CodeGen/AMDGPU detect-dead-lanes-reg-sequence-narrow-slot.mir true16-uniform-f16-phi-copysign.ll

Revert "[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched w…"

This reverts commit 201e76d4559e9d8acdfec1c202df8f2269acbd8b.
DeltaFile
+1,052-1,538llvm/test/CodeGen/AMDGPU/frem.ll
+0-72llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
+0-24llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
+2-13llvm/lib/CodeGen/DetectDeadLanes.cpp
+1,054-1,6474 files

LLVM/project c0b6ee1 — llvm/test/CodeGen/AArch64 sve-fixed-length-shuffle-reverse.ll

[AArch64] Add tests for sve fixed length reverse shuffles. NFC (#226661)
DeltaFile
+158-0llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
+158-01 files

LLVM/project 5f609f9 — llvm/docs CommandLine.md, llvm/include/llvm/Support CommandLine.h

[Support] Remove cl::bits (#226628)

cl::list covers the same use, and cl::bits would block migration to
TableGen based representation.

LLM-aided
DeltaFile
+0-145llvm/include/llvm/Support/CommandLine.h
+0-66llvm/docs/CommandLine.md
+5-10llvm/unittests/Support/CommandLineTest.cpp
+5-2213 files

LLVM/project 46f2d1c — clang/lib/CIR/CodeGen CIRGenAsm.cpp CIRGenExpr.cpp, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Propagate the record address space to get_member
DeltaFile
+71-0clang/test/CIR/CodeGen/get-member-addrspace.cpp
+24-0clang/test/CIR/CodeGenHIP/inline-asm-multi-output-addrspace.hip
+14-0clang/test/CIR/IR/invalid-struct.cir
+6-3clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+3-1clang/lib/CIR/CodeGen/CIRGenAsm.cpp
+3-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+121-43 files not shown
+125-79 files

LLVM/project 4ad5c70 — clang/lib/CIR/CodeGen CIRGenModule.h CIRGenDecl.cpp, clang/test/CIR/CodeGen amdgpu-array-addrspace.cpp

[CIR] Cast global addresses to their declared address space
DeltaFile
+95-0clang/test/CIR/CodeGenCUDA/global-addrspace-cast.cu
+26-11clang/test/CIR/CodeGen/amdgpu-array-addrspace.cpp
+18-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+3-9clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+3-2clang/test/CIR/CodeGenCUDA/address-spaces.cu
+4-0clang/lib/CIR/CodeGen/CIRGenModule.h
+149-251 files not shown
+151-267 files

LLVM/project 0b4f72d — clang/lib/CodeGen BackendConsumer.h CodeGenAction.cpp, clang/lib/Interpreter Interpreter.cpp DeviceOffload.h

[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation (#218337)

This PR implements the IncrementalHIPDeviceParser. It takes each
incremental statement's device code and lowers it all the way to a
loadable HIP fat binary: linking the ROCm device libraries, running the
AMDGPU optimization/codegen pipeline, producing a .hsaco code object,
and embedding it as __hip_fatbin for the host runtime to register and
launch.

This PR only adds the parser class, wiring it into Interpreter.cpp and
the end-to-end tests will come in a follow-up.

Assisted by Claude Opus 4.8
DeltaFile
+209-8clang/lib/Interpreter/DeviceOffload.cpp
+55-9clang/lib/Interpreter/DeviceOffload.h
+50-0clang/unittests/Basic/TargetIDTest.cpp
+9-0clang/lib/CodeGen/CodeGenAction.cpp
+8-0clang/lib/CodeGen/BackendConsumer.h
+1-6clang/lib/Interpreter/Interpreter.cpp
+332-233 files not shown
+340-259 files

LLVM/project 8259037 — orc-rt/include/orc-rt/support bind.h, orc-rt/test/unit/support bind-test.cpp

[orc-rt] make bind_front match std::bind_front semantics. (#226646)

orc_rt::bind_front stands in for std::bind_front until the ORC runtime
can use C++20, so code written against it should keep working after the
switch. This commit brings its behavior in line with std::bind_front:

- noexcept propagation
- const and rvalue call operators, forwarding the wrapper's qualifiers
- no fallback to a differently-qualified call operator
- reference return types
- member pointers
- copyable wrappers, including nested binds

The unit tests are reorganized and extended to cover these.

Assisted-by: Claude
DeltaFile
+252-26orc-rt/test/unit/support/bind-test.cpp
+81-7orc-rt/include/orc-rt/support/bind.h
+333-332 files

LLVM/project 4257da8 — llvm/lib/Transforms/Vectorize LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize/AArch64 low-trip-count-fixed-vf-no-epilogue.ll

[LV] Always try to use fixed VF for low TC loops if no epilogue allowed. (#226318)

Remove the MaxPowerOf2RuntimeVF gate for falling back to using fixed
width VFs when no epilogue is allowed and the trip count is below the
minimum for tail folding.

MaxPowerOf2RuntimeVF being not set means we cannot compute the maximum
runtime VF, due to missing max vscale. In that case we are not able to
determine if a epilogue loop remains for scalable VFs, but we can still
pick a fixed VF, if no epilogue remains for it.

Also updates processLoop to ignore CM_EpilogueNotNeededFoldTail, if the
trip count is below the tail-folding threshold.

PR: https://github.com/llvm/llvm-project/pull/226318
DeltaFile
+108-0llvm/test/Transforms/LoopVectorize/AArch64/low-trip-count-fixed-vf-no-epilogue.ll
+22-22llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
+15-13llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+145-353 files

LLVM/project c489679 — lldb/include/lldb/Target Process.h, lldb/source/API SBProcess.cpp

[lldb] Rebuild stack frames when a process address mask changes (#224989)
DeltaFile
+22-0lldb/test/API/python_api/process/address-masks/TestAddressMasks.py
+18-0lldb/source/Target/Process.cpp
+3-0lldb/source/API/SBProcess.cpp
+1-0lldb/include/lldb/Target/Process.h
+44-04 files

LLVM/project 6a37cee — clang/lib/Interpreter IncrementalAction.cpp, clang/test/Interpreter nonexistent-xcc-file.cpp

Fix for a clang-repl crash when passing non-existent file to --Xcc (#225861)

Problem: When clang-repl fails to initialize because an --Xcc file does
not exist, Interpreter::create() destroys the partially initialized
Interpreter. Its destructor unconditionally calls FinalizeAction(),
which invokes FrontendAction::EndSourceFile() without a registered
CompilerInstance and triggers an assertion.
Fix: Track whether interpreter initialization completed successfully and
only finalize the frontend action for successfully initialized
interpreters.
Test: Add a regression test covering a nonexistent --Xcc file.

This change resolves https://github.com/llvm/llvm-project/issues/225429

Assisted by gpt-5.6-luna

---------

Co-authored-by: Anutosh Bhat <andersonbhat491 at gmail.com>
DeltaFile
+7-0clang/test/Interpreter/nonexistent-xcc-file.cpp
+2-1clang/lib/Interpreter/IncrementalAction.cpp
+9-12 files

LLVM/project af83fa1 — llvm/include/llvm/Analysis ValueLattice.h

[ValueLattice] Use two uint64_t when possible
DeltaFile
+83-28llvm/include/llvm/Analysis/ValueLattice.h
+83-281 files

LLVM/project e0316c1 — clang/lib/AST ExprConstShared.h ExprConstant.cpp, clang/lib/AST/ByteCode EvalEmitter.h EvaluationResult.h

Revert "[clang][bytecode] Stop relying on `CheckEvaluationResult()` (… (#226637)

…#186045)"

This reverts commit 55b498466a7b2620d09fcdf1b2300f71a35f6d8b.

This breaks two msan builders and reproducing the failure locally takes
forever.
DeltaFile
+1-381clang/lib/AST/ByteCode/EvaluationResult.cpp
+99-48clang/lib/AST/ExprConstant.cpp
+24-46clang/lib/AST/ByteCode/EvalEmitter.cpp
+0-42clang/lib/AST/ExprConstShared.h
+10-22clang/lib/AST/ByteCode/EvaluationResult.h
+3-14clang/lib/AST/ByteCode/EvalEmitter.h
+137-55314 files not shown
+159-60020 files

LLVM/project e52ae3f — clang/lib/CIR/CodeGen CIRGenAsm.cpp CIRGenExpr.cpp, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Propagate the record address space to get_member

A member is stored inside its record, so a pointer to it is in the same
address space as the record. Several get_member builders created the
result pointer in the default address space regardless of the base:

  cir.get_member %p[0] : !cir.ptr<!rec_S, target_address_space(4)>
                      -> !cir.ptr<!s32i>

On SPIR-V the default address space is private, so a SYCL kernel reading
a captured pointer from its closure (in the generic address space) went
through a private pointer. For unions, lowering emitted a bitcast that
changed the address space, which is invalid LLVM IR.

Take the address space from the base in emitAddrOfFieldStorage,
getAddrOfBitFieldStorage, the Address-based createGetMember, multi-output
inline asm (whose temporary is an AS 5 alloca on AMDGPU) and the NVPTX
printf argument buffer. Add a verifier check so a mismatch fails early.
DeltaFile
+71-0clang/test/CIR/CodeGen/get-member-addrspace.cpp
+24-0clang/test/CIR/CodeGenHIP/inline-asm-multi-output-addrspace.hip
+14-0clang/test/CIR/IR/invalid-struct.cir
+6-3clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+3-1clang/lib/CIR/CodeGen/CIRGenAsm.cpp
+3-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+121-43 files not shown
+125-79 files

LLVM/project 7515b8d — clang/lib/CIR/CodeGen CIRGenModule.h CIRGenDecl.cpp, clang/test/CIR/CodeGen amdgpu-array-addrspace.cpp

[CIR] Cast global addresses to their declared address space

A global can live in a different address space than its declared type,
e.g. a CUDA __device__ or __shared__ variable. Classic CodeGen casts the
address once where it is formed (GetOrCreateLLVMGlobal and
getOrCreateStaticVarDecl), so every user sees a pointer in the declared
(generic) address space. CIR kept the global's address space on the value
and relied on each user to cast it. Users that did not, such as returning
or storing the address, bitcast the destination slot instead,
reinterpreting the pointer:

  __shared__ int sh;
  __device__ int *f() { return &sh; }

stored the raw shared-window address as a generic pointer, with no
cvta.shared on NVPTX. After #226455 the same applies to function-local
__shared__ variables.

Do the same check as classic CodeGen where CIR first has the address as a

    [5 lines not shown]
DeltaFile
+95-0clang/test/CIR/CodeGenCUDA/global-addrspace-cast.cu
+26-11clang/test/CIR/CodeGen/amdgpu-array-addrspace.cpp
+18-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+3-9clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+3-2clang/test/CIR/CodeGenCUDA/address-spaces.cu
+4-0clang/lib/CIR/CodeGen/CIRGenModule.h
+149-251 files not shown
+151-267 files

LLVM/project 18af9ef — clang/docs ReleaseNotes.md, clang/lib/Sema SemaOpenMP.cpp

Revert "[clang][OpenMP] Only accept char strings in the message clause" (#226636)

Reverts llvm/llvm-project#226080

The newly added test error_message.c is failing on the PS4 bot 
https://lab.llvm.org/buildbot/#/builders/144/builds/66294
DeltaFile
+0-33clang/test/OpenMP/error_message.c
+0-29clang/test/OpenMP/error_message.cpp
+1-3clang/lib/Sema/SemaOpenMP.cpp
+1-1clang/test/OpenMP/parallel_message_messages.cpp
+0-1clang/docs/ReleaseNotes.md
+2-675 files

LLVM/project 60059de — libcxx/include/__ranges zip_view.h views.h

[libc++][NFC] Avoid empty namespace in internal headers of `<ranges>` (#226034)

...in pre-C++20/23 modes. This follows up
0c94a978df783bd67535350eac84088fc482716a and fixes more complaints from
clang-tidy checks in CI.
DeltaFile
+4-4libcxx/include/__ranges/zip_view.h
+4-4libcxx/include/__ranges/views.h
+4-4libcxx/include/__ranges/transform_view.h
+4-4libcxx/include/__ranges/to.h
+4-4libcxx/include/__ranges/take_while_view.h
+4-4libcxx/include/__ranges/take_view.h
+24-2425 files not shown
+124-12331 files

LLVM/project be7d200 — llvm/include/llvm/Transforms/Utils SCCPSolver.h, llvm/lib/Transforms/Utils SCCPSolver.cpp

[SCCP] Use Small Vector for struct
DeltaFile
+5-5llvm/lib/Transforms/Utils/SCCPSolver.cpp
+1-1llvm/include/llvm/Transforms/Utils/SCCPSolver.h
+6-62 files

LLVM/project 3441f36 — clang/docs ReleaseNotes.md, clang/lib/Sema SemaOpenMP.cpp

Revert "[clang][OpenMP] Only accept char strings in the message clause (#226080)"

This reverts commit 5eb23d2ae9f1dab06a31e5f9d7d64fa23a775604.
DeltaFile
+0-33clang/test/OpenMP/error_message.c
+0-29clang/test/OpenMP/error_message.cpp
+1-3clang/lib/Sema/SemaOpenMP.cpp
+1-1clang/test/OpenMP/parallel_message_messages.cpp
+0-1clang/docs/ReleaseNotes.md
+2-675 files

LLVM/project 1639504 — clang/include/clang/CIR/Dialect/Builder CIRBaseBuilder.h, clang/lib/CIR/CodeGen CIRGenDecl.cpp

[CIR] Attach address space to global variables (#226455)

Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
DeltaFile
+5-5clang/test/CIR/CodeGenCUDA/address-spaces.cu
+6-3clang/lib/CIR/CodeGen/CIRGenDecl.cpp
+4-4clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
+15-123 files

LLVM/project 240a9cb — mlir/python/mlir/dialects ext.py, mlir/test/python/dialects ext.py

[MLIR][Python] Allow `Attribute` to denote unconstrained attributes in Python-defined ops (#224679)

Operation definitions support attribute constraints such as
`IntegerAttr`, `StringAttr`, and `IntegerAttr | StringAttr`, but
currently reject `Attribute` itself.

This change allows `Attribute` to denote an unconstrained attribute,
accepting both built-in and Python-defined attributes:

```python
class MyOp(MyDialect.Operation, name="my_op"):
    arg: Operand
    attr: Attribute
    res: Result
```

This complements the unconstrained `Operand` and `Result` annotations
introduced in #220216. The annotation also works with `attribute()`
field specifiers, including `kw_only` and `default_factory`.

Assisted-by: Codex / GPT6
DeltaFile
+73-0mlir/test/python/dialects/ext.py
+5-0mlir/python/mlir/dialects/ext.py
+78-02 files

LLVM/project e59a0c6 — orc-rt/include/orc-rt/bedrock Session.h, orc-rt/lib/bedrock Session.cpp

[orc-rt] Pass the reporting Session to Session error reporters. (#226622)

Session error reporters previously received only the Error, and had to
be supplied to the Session constructor, so they had no direct way to
refer to the Session reporting the error (e.g. to include its address in
a log message).

This commit changes ErrorReporterFn to take the reporting Session along
with the Error, and adds a Session::logErrors reporter that logs errors
via ORC_RT_LOG at Error level in the Session category. logErrors is only
available when Error-level logging is compiled in
(ORC_RT_LOG_ENABLED(Error)), so that it can't silently discard errors in
configurations where logging is compiled out. The noErrors and
AccumulateErrors test helpers are updated to work as both plain and
Session error reporters.
DeltaFile
+24-6orc-rt/test/unit/bedrock/SessionTest.cpp
+24-3orc-rt/test/unit/CommonTestUtils.h
+22-2orc-rt/include/orc-rt/bedrock/Session.h
+11-0orc-rt/lib/bedrock/Session.cpp
+1-1orc-rt/tools/ogre/ogre.cpp
+1-1orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
+83-136 files

LLVM/project ab08c75 — bolt/lib/Passes BinaryPasses.cpp ReorderFunctions.cpp, bolt/lib/Profile DataAggregator.cpp

[BOLT] Remove cl::callback uses (#226359)

cl::callback will be removed to enable migration to TableGen based
representation.

https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3

LLM-aided
DeltaFile
+7-8bolt/lib/Passes/ReorderFunctions.cpp
+6-8bolt/lib/Passes/BinaryPasses.cpp
+6-6bolt/lib/Profile/DataAggregator.cpp
+19-223 files

LLVM/project 0b61b73 — clang-tools-extra/clangd/tool ClangdMain.cpp

[clangd] Report retired flags after parsing (#226360)

cl::callback will be removed to enable migration to TableGen

https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3

LLM-aided
DeltaFile
+9-5clang-tools-extra/clangd/tool/ClangdMain.cpp
+9-51 files

LLVM/project 90c150f — clang/tools/clang-format ClangFormat.cpp, llvm/lib/CodeGen/AsmPrinter AsmPrinter.cpp

Replace cl::bits with cl::list. NFC (#226399)

cl::bits packs enum values into an unsigned, which would block migration
to TableGen based representation. The three users only test membership.

LLM-aided
DeltaFile
+11-17llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+3-3llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
+2-2clang/tools/clang-format/ClangFormat.cpp
+16-223 files

LLVM/project 8c697f0 — clang/test/CodeGenHLSL/builtins WaveReadLaneFirst.hlsl, libcxx/test/std/algorithms/alg.modifying.operations/alg.swap pstl.swap_ranges.pass.cpp

Rebase, improvements

Created using spr 1.3.7
DeltaFile
+1,538-1,052llvm/test/CodeGen/AMDGPU/frem.ll
+733-228llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
+389-0llvm/test/Transforms/LoopFusion/guard_skip_empty_block.ll
+187-0libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
+129-15llvm/test/CodeGen/X86/llvm.frexp.ll
+120-0clang/test/CodeGenHLSL/builtins/WaveReadLaneFirst.hlsl
+3,096-1,295147 files not shown
+5,950-1,866153 files

LLVM/project f8c2918 — llvm/test/Transforms/SLPVectorizer/AArch64 ordered-reduction-of-loads.ll, llvm/test/Transforms/SLPVectorizer/RISCV ordered-reduction.ll

[SLP][NFC]Add extra test for reductions vectorization, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/226618
DeltaFile
+77-0llvm/test/Transforms/SLPVectorizer/RISCV/ordered-reduction.ll
+48-0llvm/test/Transforms/SLPVectorizer/AArch64/ordered-reduction-of-loads.ll
+125-02 files

LLVM/project 3a2787d — orc-rt/include/orc-rt-c config.h.in, orc-rt/include/orc-rt-c/support Logging.h

[orc-rt] Move ORC_RT_LOG_ENABLED into config.h. (#226617)

ORC_RT_LOG_ENABLED depends only on the logging configuration values
defined in config.h, but was defined in Logging.h, so checking whether a
log level is compiled in required pulling in the logging backend's
headers (e.g. <os/log.h>).

This commit moves ORC_RT_LOG_ENABLED (and its level-token aliases) into
config.h, so that headers can check the logging configuration without
including Logging.h.
DeltaFile
+32-0orc-rt/include/orc-rt-c/config.h.in
+2-26orc-rt/include/orc-rt-c/support/Logging.h
+34-262 files

LLVM/project 201e76d — llvm/lib/CodeGen DetectDeadLanes.cpp, llvm/test/CodeGen/AMDGPU detect-dead-lanes-reg-sequence-narrow-slot.mir true16-uniform-f16-phi-copysign.ll

[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (#226556)

isCrossCopy() returned early whenever source and destination shared a
register class, treating the transfer as lane-for-lane. That is wrong
when a REG_SEQUENCE names a subregister slot narrower than the source
operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit
vreg. Only take the early exit when the two widths match; otherwise fall
through to findCommonRegClass().

Fixes: ROCM-31212
DeltaFile
+1,538-1,052llvm/test/CodeGen/AMDGPU/frem.ll
+72-0llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
+24-0llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
+13-2llvm/lib/CodeGen/DetectDeadLanes.cpp
+1,647-1,0544 files