LLVM/project c2fca81llvm/lib/Target/RISCV RISCVInstrInfoV.td, llvm/lib/Target/RISCV/MCA RISCVCustomBehaviour.cpp

[RISCV] Rename nf->nfields in MC layer. NFC (#179365)

The RISC-V vector spec uses 'nf' to refer to the encoded value of
nfields. Doing the same in the MC layer make it more clear that
!add(nfields, -1) is converting from nfields to the encoded nf. I plan
to sink this !add down one level in a follow up patch.

I might do the same rename throughout tablegen, but I haven't reviewed
yet.
DeltaFile
+109-113llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+8-8llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+117-1212 files

LLVM/project 7423017llvm/lib/Target/RISCV RISCVInstrFormatsV.td

[RISCV] Add common base classes for loads/stores in RISCVInstrFormatsV.td. NFC (#179329)

Only bits 24-20 have a different meaning between the different loads and
stores, vs2, rs2, or lumop/sumop.
DeltaFile
+28-68llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+28-681 files

LLVM/project d0a4f8dllvm/lib/CodeGen CodeGenPrepare.cpp

clang-format
DeltaFile
+2-1llvm/lib/CodeGen/CodeGenPrepare.cpp
+2-11 files

LLVM/project d755ba9clang-tools-extra/clang-tidy/bugprone ArgumentCommentCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Check inherited constructors in bugprone-argument-comment (#179105)

Currently, C++11 inherited constructors are not checked. For example:

```cpp
struct Base {
    explicit Base(int val) {}
};

struct Over : public Base {
    using Base::Base;
};

int main() {
    Base b{/*wrong=*/2}; // checked
    Over o{/*wrong=*/3}; // NOT checked right now
}
```


    [7 lines not shown]
DeltaFile
+32-0clang-tools-extra/test/clang-tidy/checkers/bugprone/argument-comment-cxx-11-inherited-constructors.cpp
+5-0clang-tools-extra/clang-tidy/bugprone/ArgumentCommentCheck.cpp
+4-0clang-tools-extra/docs/ReleaseNotes.rst
+41-03 files

LLVM/project 600073allvm/lib/Target/SystemZ SystemZAsmPrinter.cpp SystemZAsmPrinter.h, llvm/test/CodeGen/SystemZ zos-lower-constant.ll

Formatting and add test
DeltaFile
+24-0llvm/test/CodeGen/SystemZ/zos-lower-constant.ll
+1-5llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+3-1llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
+28-63 files

LLVM/project 26921d7llvm/lib/Target/X86 X86CodeGenPassBuilder.cpp, llvm/test/CodeGen/X86 llc-pipeline-npm.ll

[NewPM] Fix callsite for x86-lvi-ret (#179383)

DeltaFile
+3-3llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+4-2llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+7-52 files

LLVM/project c57f8acllvm/lib/Target/SPIRV SPIRVSymbolicOperands.td SPIRVInstrInfo.td

[SPIR-V] Fix FmaKHR CapabilityOperand and Op (#179174)

Specification:
https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_fma.html
DeltaFile
+1-1llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+1-1llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+2-22 files

LLVM/project 7c48059llvm/lib/CodeGen CodeGenPrepare.cpp, llvm/lib/Transforms/Utils BasicBlockUtils.cpp

Reland "[BasicBlockUtils] Fix dominator tree update for entry block in splitBlockBefore() (#178895)"
DeltaFile
+19-44llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+25-0llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp
+2-2llvm/lib/CodeGen/CodeGenPrepare.cpp
+46-463 files

LLVM/project c373d76lldb/source/Target Thread.cpp ExecutionContext.cpp, lldb/test/API/functionalities/scripted_frame_provider TestScriptedFrameProvider.py

[lldb] Fix variable access in old SBFrames after inferior function calls (#178823)

When a user holds an SBFrame reference and then triggers an inferior
function
call (via expression evaluation or GetExtendedBacktraceThread),
variables in
that frame become inaccessible with "register fp is not available"
errors.

This happens because inferior function calls execute through
ThreadPlanCallFunction, which calls ClearStackFrames() during cleanup to
invalidate the unwinder state. ExecutionContextRef objects in the old
SBFrames
were tracking StackFrameLists via weak_ptr, which became stale when
ClearStackFrames() created new instances.

The fix uses stable StackFrameList identifiers that persist across
ClearStackFrames():
- ID = 0: Normal unwinder frames (constant across all instances)

    [35 lines not shown]
DeltaFile
+330-3lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py
+144-0lldb/test/API/macosx/extended-backtrace-api/TestExtendedBacktraceAPI.py
+106-33lldb/source/Target/Thread.cpp
+56-18lldb/source/Target/ExecutionContext.cpp
+53-0lldb/test/API/macosx/extended-backtrace-api/main.m
+29-11lldb/source/Target/StackFrameList.cpp
+718-658 files not shown
+809-8514 files

LLVM/project 618df12llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU isel-amdgcn-cs-chain-intrinsic-w32.ll isel-amdgcn-cs-chain-intrinsic-w64.ll

[AMDGPU] Allow hoising of V_READFIRSTLANE_B32 for uniform operand

readfirstlane can be moved across control flow for uniform inputs.
The MachineInstr::NoConvergent attribute allows hoisting
which is otherwise prohibited for a convergent instruction.
DeltaFile
+82-82llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
+52-52llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
+24-24llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
+33-0llvm/test/CodeGen/AMDGPU/readanylane.ll
+16-16llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
+11-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+218-1744 files not shown
+227-18010 files

LLVM/project 0e961a2llvm/include/llvm/CodeGen SelectionDAGNodes.h, llvm/lib/CodeGen/SelectionDAG InstrEmitter.cpp SelectionDAGDumper.cpp

Add SDNodeFlag::NoConvergent
DeltaFile
+6-1llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+3-0llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+3-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+12-13 files

LLVM/project 6d52d26llvm/lib/Transforms/Utils BasicBlockUtils.cpp, llvm/unittests/Transforms/Utils BasicBlockUtilsTest.cpp

Revert "[BasicBlockUtils] Fix dominator tree update for entry block in splitBlockBefore() (#178895)" (#179373)

This reverts commit ad8d5349d46734826aaeae4a2ebdc6f427a5bad8.

LLVM Buildbot detected a failure,
https://lab.llvm.org/buildbot/#/builders/210/builds/8229
DeltaFile
+44-19llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+0-25llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp
+44-442 files

LLVM/project 79fcfcellvm/include/llvm/CodeGen TargetLowering.h

[CodeGen] Remove legacy getTgtMemIntrinsic overload

It is now fully unused.

commit-id:028dd72d
DeltaFile
+1-19llvm/include/llvm/CodeGen/TargetLowering.h
+1-191 files

LLVM/project 8050acellvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU waitcnt-unscoped.ll llvm.amdgcn.load.to.lds.ll

[AMDGPU] Return two MMOs for load-to-lds and store-from-lds intrinsics

Accurately represent both the load and the store part of those
intrinsics.

The test changes seem to be mostly fairly insignificant changes caused by
subtly different scheduler behavior.

commit-id:0269189c
DeltaFile
+59-51llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-4llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll
+2-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
+2-4llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
+66-634 files

LLVM/project 611f22dllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU BUILD.gn

[gn build] Port 5cc4b05380ae
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
+1-01 files

LLVM/project 5cc4b05llvm/lib/Target/AMDGPU AMDGPUHazardLatency.cpp AMDGPUHazardLatency.h, llvm/test/CodeGen/AMDGPU gfx11-sgpr-hazard-latency.mir atomic_optimizations_local_pointer.ll

[AMDGPU] Add scheduling DAG mutation for hazard latencies (#170075)

Improve waitcnt merging in ML kernel loops by increasing latencies on
VALU writes to SGPRs.
Specifically this helps with the case of V_CMP output feeding V_CNDMASK
instructions.
DeltaFile
+169-0llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
+45-51llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+40-39llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+77-0llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp
+24-0llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.h
+8-12llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+363-1024 files not shown
+372-10610 files

LLVM/project 6f0b873llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/lib/Target/AMDGPU SIISelLowering.cpp

[CodeGen] Refactor targets to override the new getTgtMemIntrinsic overload (NFC) (#175844)

This is a fairly mechanical change. Instead of returning true/false,
we either keep the Infos vector empty or push one entry.
DeltaFile
+113-60llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+78-59llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+40-21llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+36-22llvm/lib/Target/ARM/ARMISelLowering.cpp
+36-22llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+26-18llvm/lib/Target/X86/X86ISelLowering.cpp
+329-20216 files not shown
+411-27522 files

LLVM/project ad8d534llvm/lib/Transforms/Utils BasicBlockUtils.cpp, llvm/unittests/Transforms/Utils BasicBlockUtilsTest.cpp

[BasicBlockUtils] Fix dominator tree update for entry block in splitBlockBefore() (#178895)

06dfbb50d70eea4ae38d655842626a0b9b224d5c fixed dominator update for
entry block in `SplitBlockPredecessors()`, this patch fixes dominator
tree update for entry block in `splitBlockBefore()` with
`UpdateAnalysisInformation()`.
DeltaFile
+19-44llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+25-0llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp
+44-442 files

LLVM/project 7ba94c2compiler-rt/lib/sanitizer_common sanitizer_posix_libcdep.cpp

[compiler-rt][common] Don't unmap stacks not mapped by the runtime

When the sanitizer hasn't mapped the alternate signal stack, but the
host program has (like LLVM), the runtime still tries to unilaterally
unmap the alternate stack. Instead, the runtime should just check if
it's actually mmaped the alternate stack, and only unmap it if it has.
DeltaFile
+8-1compiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp
+8-11 files

LLVM/project a084def.github renovate.json

[Github] Try changing package name

To see if this actually captures the python upgrades within that file.
The previous commit did not fix the issue.
DeltaFile
+1-1.github/renovate.json
+1-11 files

LLVM/project 25ae460.github/workflows commit-access-review.yml

workflows/commit-access-review: Use a GitHub App access token instead of llvmbot

This replaces the use of an access token associated with the llvmbot
account with one that is generated by a GitHub App.  This is slightly
better, because it eliminates the need to periodically rotate the
llvmbot tokens, which is difficult to do, since it requires sharing
a password and 2fa code among all the admins.

The tokens generated by the app automatically expire after an hour, and
the private key that is used to request it can be easily rotated by
an LLVM Organization owner.  Also, since a single private key can
be used to generate many tokens, there is only one secret to rotate
instead of many.
DeltaFile
+11-1.github/workflows/commit-access-review.yml
+11-11 files

LLVM/project 478b9a3.github/workflows commit-access-review.yml

Update permissions
DeltaFile
+2-0.github/workflows/commit-access-review.yml
+2-01 files

LLVM/project b9b9cfe.github/workflows commit-access-review.yml

Some cleanups
DeltaFile
+1-1.github/workflows/commit-access-review.yml
+1-11 files

LLVM/project 79ad091llvm/lib/Transforms/InstCombine InstCombineAddSub.cpp, llvm/test/Transforms/InstCombine fneg.ll

[InstCombine] Preserve fdiv metadata on fneg folds (#179157)

Copy metadata from the original fdiv when folding fneg into fdiv or
hoisting fneg above fdiv. This keeps !fpmath (and other metadata)
intact, preventing !fpmath loss seen in libclc tanpi function. fneg only
flips sign bit, so it does not affect precision.
DeltaFile
+33-0llvm/test/Transforms/InstCombine/fneg.ll
+11-4llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+44-42 files

LLVM/project 388bd13.github/workflows commit-access-review.yml

Add uses
DeltaFile
+1-0.github/workflows/commit-access-review.yml
+1-01 files

LLVM/project 234736aclang-tools-extra/docs/clang-tidy/checks list.rst, clang-tools-extra/docs/clang-tidy/checks/cert dcl58-cpp.rst env33-c.rst

[clang-tidy][NFC] Fix incorrect `list.rst` modification by `add_new_check.py` (#179297)

We have observed unexpected and extensive modifications to `list.rst` in
a few Pull Requests. After some investigation I found that
`add_new_check.py` was misclassifying existing checks, leading to
instability in the generated documentation list.

More specifically:
- The script relies on `http-equiv=refresh` meta tags to identify alias
checks, which is missing in several existing checks, causing them to be
incorrectly listed as regular checks.
- The script fails to detect fix-its in checks that use CamelCase helper
methods.

With this patch, running `add_new_check.py` now generates a stable and
correct `list.rst` consistent with the actual codebase state.
DeltaFile
+2-6clang-tools-extra/docs/clang-tidy/checks/list.rst
+2-0clang-tools-extra/docs/clang-tidy/checks/fuchsia/multiple-inheritance.rst
+2-0clang-tools-extra/docs/clang-tidy/checks/cert/dcl58-cpp.rst
+2-0clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst
+2-0clang-tools-extra/docs/clang-tidy/checks/cert/err52-cpp.rst
+2-0clang-tools-extra/docs/clang-tidy/checks/cert/flp30-c.rst
+12-64 files not shown
+18-710 files

LLVM/project 5f7e5e5llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/MC/AMDGPU gfx8_asm_vop3.s gfx7_asm_vop3.s

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+121,423-138,333llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+42,349-42,348llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
+41,419-41,418llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
+36,428-36,427llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
+28,175-28,174llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
+313,117-331,52512,458 files not shown
+2,497,968-1,797,95512,464 files

LLVM/project 398c8callvm/lib/CodeGen/SelectionDAG ScheduleDAGSDNodes.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+7-1llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+7-11 files

LLVM/project 50a9141llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port 7b6f1235b9353
DeltaFile
+1-0llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+1-01 files

LLVM/project 12d1099llvm/utils/gn/secondary/llvm/lib/Target/X86 BUILD.gn

[gn build] Port 9d5a42c8411b2
DeltaFile
+12-1llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
+12-11 files