LLVM / project - FreshBSD

LLVM/project 1e5adb0 — llvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/Transforms/InstCombine select-binop-associative-prof.ll

2026-01-26 19:30:30 UTC by Snehasish Kumar on ⎇

users/snehasish/01-24-_instcombine_preserve_prof_metadata_when_creating_select_instructions

[InstCombine] Preserve !prof metadata when creating select instructions.

Delta		File
+19	-0	llvm/test/Transforms/InstCombine/select-binop-associative-prof.ll
+3	-1	llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+22	-1	2 files

LLVM/project 7b9b88f — llvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/Transforms/InstCombine branch.ll

2026-01-26 19:30:30 UTC by Snehasish Kumar on ⎇

users/snehasish/01-14-_instcombine_profcheck_propogate_profile_metadata_when_transforming_br_x_y_to_br_x_y_

[InstCombine][profcheck] Propogate profile metadata when transforming br (X && !Y) to br (!X || Y)

Updated visitBranchInst to propagate and swap !prof metadata when transforming br (X && !Y) to br (!X || Y).

Delta		File
+21	-13	llvm/test/Transforms/InstCombine/branch.ll
+12	-0	llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+33	-13	2 files

LLVM/project ac454a2 — mlir/lib/Dialect/Tosa/IR TosaOps.cpp, mlir/test/Dialect/Tosa tosa-infer-shapes.mlir

2026-01-26 19:24:49 UTC by Yi-Chi Lee via GitHub on ⎇

main

[mlir][tosa] Guard pooling shape inference on unranked inputs (#177999)

Fix #177946

poolingInferReturnTypes didn't properly guard the unknown rank,
triggering an assertion in ShapeAdaptor::getDimSize.

Delta		File
+9	-0	mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+1	-1	mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+10	-1	2 files

LLVM/project 528c99d — llvm/lib/Analysis ValueTracking.cpp

2026-01-26 19:24:28 UTC by Matt Arsenault via GitHub on ⎇

main

ValueTracking: Use m_CheckedFp in isKnownIntegral (#178019)

Delta		File
+1	-20	llvm/lib/Analysis/ValueTracking.cpp
+1	-20	1 files

LLVM/project 5582f29 — llvm/docs ReleaseNotes.md

2026-01-26 19:24:23 UTC by Matt Arsenault on ⎇

users/arsenm/dag/remove-softPromoteHalfType

Release note

Delta		File
+2	-0	llvm/docs/ReleaseNotes.md
+2	-0	1 files

LLVM/project d39f030 — llvm/lib/CodeGen/SelectionDAG LegalizeFloatTypes.cpp LegalizeTypes.h

2026-01-26 19:24:22 UTC by Matt Arsenault on ⎇

users/arsenm/dag/remove-softPromoteHalfType

Delete the implementation functions

Delta		File
+0	-655	llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+0	-37	llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+0	-692	2 files

LLVM/project 80e5ab9 — llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen TargetLoweringBase.cpp

2026-01-26 19:24:20 UTC by Matt Arsenault on ⎇

users/arsenm/dag/remove-softPromoteHalfType

DAG: Remove softPromoteHalfType

Remove the now unimplemented target hook and associated DAG machinery
for the old half legalization path.

Really fixes #97975

Delta		File
+7	-22	llvm/include/llvm/CodeGen/TargetLowering.h
+0	-20	llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+0	-11	llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+2	-7	llvm/lib/CodeGen/TargetLoweringBase.cpp
+0	-8	llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+0	-2	llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+9	-70	1 files not shown
+9	-71	7 files

LLVM/project 89e38d6 — llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

2026-01-26 19:21:20 UTC by vporpo via GitHub on ⎇

main

[AMDGPU][SIInsertWaitcnts][NFC] Move static array definition (#178014)

Move the array out of the member function.

Delta		File
+31	-35	llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+31	-35	1 files

LLVM/project 6b9c9ed — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

2026-01-26 19:21:09 UTC by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpadd-external-uses-estimations-into-tree-throttling

Fix formatting

Created using spr 1.3.7

Delta		File
+2	-2	llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2	-2	1 files

LLVM/project 4d460d6 — lldb/test/API/functionalities/process_save_core TestProcessSaveCore.py

2026-01-26 19:19:45 UTC by Charles Zablit via GitHub on ⎇

main

[lldb][windows] fix ProcessSaveCoreTestCase.test_save_core_to_nonwritable_dir (#178016)

This patch fixes the
`ProcessSaveCoreTestCase.test_save_core_to_nonwritable_dir` test on
Windows.

This test fails on Windows because `os.chmod` does not work on Windows.
It was used to make the directory unwritable.

[`icacls`](https://learn.microsoft.com/en-us/windows-server/administration/windows-commands/icacls)
can be used instead to block the directory.

This is a followup to https://github.com/llvm/llvm-project/pull/177496.

Delta		File
+15	-3	lldb/test/API/functionalities/process_save_core/TestProcessSaveCore.py
+15	-3	1 files

LLVM/project 680388a — lldb/packages/Python/lldbsuite/test/tools/lldb-dap dap_server.py

2026-01-26 19:18:13 UTC by Ebuka Ezike via GitHub on ⎇

main

[lldb-dap] Fix assertion on the recv thread. (#177977)

threading.current_thread is a function

Delta		File
+1	-1	lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
+1	-1	1 files

LLVM/project 6c9fc1b — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 deleted-instructions-clear.ll vec_list_bias_external_insert_shuffled.ll

2026-01-26 19:17:32 UTC by Alexey Bataev on ⎇

users/alexey-bataev/spr/slpadd-external-uses-estimations-into-tree-throttling

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

Delta		File
+110	-25	llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+16	-15	llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
+12	-14	llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias_external_insert_shuffled.ll
+12	-13	llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
+12	-13	llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
+162	-80	5 files

LLVM/project 51f4c5e — clang-tools-extra/clang-tidy/readability ContainerContainsCheck.cpp ContainerContainsCheck.h

2026-01-26 19:11:21 UTC by Victor Chernyakin via GitHub on ⎇

main

[clang-tidy] Speed up `readability-container-contains` (#175121)

This is currently one of our most expensive checks according to
`--enable-check-profile`. I measured using [the usual
setup](https://github.com/llvm/llvm-project/pull/174357#issue-3780188615):
```sh
hyperfine \
    --shell=none \
    --prepare='cmake --build build/release --target clang-tidy' \
    './build/release/bin/clang-tidy --checks=-*,readability-container-contains all_headers.cpp -header-filter=.* -system-headers -- -std=c++23 -fno-delayed-template-parsing'
```

First, the status quo:
```txt
  Time (mean ± σ):      5.243 s ±  0.158 s    [User: 4.964 s, System: 0.248 s]
  Range (min … max):    5.133 s …  5.612 s    10 runs
```
This PR improves that in two independent commits. The first commit
changes the default traversal mode from `TK_AsIs` to

    [12 lines not shown]

Delta		File
+28	-48	clang-tools-extra/clang-tidy/readability/ContainerContainsCheck.cpp
+1	-1	clang-tools-extra/clang-tidy/readability/ContainerContainsCheck.h
+29	-49	2 files

LLVM/project 794a96a — clang/lib/Parse ParsePragma.cpp

2026-01-26 19:09:51 UTC by Florian Mayer on ⎇

users/fmayer/spr/do-not-submit-run-177979-on-buildbot

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6

Delta		File
+1	-1	clang/lib/Parse/ParsePragma.cpp
+1	-1	1 files

LLVM/project 7fd2056 — llvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Analysis/ScalarEvolution ptrtoaddr.ll ptrtoaddr-i32-index-width.ll

2026-01-26 19:01:38 UTC by Florian Hahn via GitHub on ⎇

main

[SCEV] Sink SCEVPtrToAddr to leaf SCEVUnknowns. (#174437)

Use CastSinkingRewriter for SCEVPtrToAddr expressions as well, sinking
them the same as SCEVPtrToInt expressions.

Depends on https://github.com/llvm/llvm-project/pull/174435 
and https://github.com/llvm/llvm-project/pull/158032.

PR: https://github.com/llvm/llvm-project/pull/174437

Delta		File
+21	-28	llvm/lib/Analysis/ScalarEvolution.cpp
+19	-1	llvm/test/Analysis/ScalarEvolution/ptrtoaddr.ll
+1	-1	llvm/test/Analysis/ScalarEvolution/ptrtoaddr-i32-index-width.ll
+41	-30	3 files

LLVM/project c4585b4 — lldb/include/lldb/Host ProcessLaunchInfo.h, lldb/source/Host/windows ProcessLauncherWindows.cpp

2026-01-26 18:56:23 UTC by Charles Zablit via GitHub on ⎇

main

[lldb][windows] do not attach to a PseudoConsole if it is not opened (#177934)

# Summary

This patch ensures lldb will not try to read from a PseudoConsole if it
has not been opened.

# Original issue

https://github.com/llvm/llvm-project/pull/168729 introduces support for
the Windows ConPTY in `lldb-dap`. This caused a regression in `lldb`
which was not caught by our tests:
https://github.com/llvm/llvm-project/issues/175652.

This patch fixes https://github.com/llvm/llvm-project/issues/175652.

`lldb_private::ProcessLauncherWindows::LaunchProcess` connects the
debuggee to a PseudoConsole only if:
```cpp

    [15 lines not shown]

Delta		File
+8	-8	lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
+12	-0	lldb/include/lldb/Host/ProcessLaunchInfo.h
+4	-3	lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
+1	-3	lldb/source/Host/windows/ProcessLauncherWindows.cpp
+25	-14	4 files

LLVM/project ab310f3 — llvm/lib/Analysis ValueTracking.cpp

2026-01-26 18:55:34 UTC by Matt Arsenault on ⎇

users/arsenm/valuetracking/use-m_CheckedFp-isKnownIntegral

ValueTracking: Use m_CheckedFp in isKnownIntegral

Delta		File
+1	-20	llvm/lib/Analysis/ValueTracking.cpp
+1	-20	1 files

LLVM/project a25c7d7 — llvm/include/llvm/Analysis ValueTracking.h, llvm/lib/Analysis ValueTracking.cpp

2026-01-26 18:55:14 UTC by Matt Arsenault via GitHub on ⎇

users/arsenm/valuetracking/use-m_CheckedFp-isKnownIntegral

ValueTracking: Extract isKnownIntegral out of AMDGPU (#177912)

Also do some basic conversions to use SimplifyQuery and add tests to
show assume works in a new context.

Delta		File
+14	-88	llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+67	-0	llvm/lib/Analysis/ValueTracking.cpp
+38	-0	llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
+5	-0	llvm/include/llvm/Analysis/ValueTracking.h
+124	-88	4 files

LLVM/project 6039b47 — llvm/lib/Target/AMDGPU R600ISelLowering.cpp, llvm/test/CodeGen/AMDGPU kernel-args.ll

2026-01-26 18:49:26 UTC by Matt Arsenault via GitHub on ⎇

users/arsenm/valuetracking/use-m_CheckedFp-isKnownIntegral

Reapply "R600: Remove softPromoteHalfType (#177420)" (#178013)

This reverts commit 38b7176c92f31c274226ff418891545046dcf1f0.

Delta		File
+174	-0	llvm/test/CodeGen/AMDGPU/kernel-args.ll
+11	-4	llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+185	-4	2 files

LLVM/project 674b020 — llvm/lib/Target/RISCV RISCVInstrInfo.cpp RISCVInstrInfo.h, llvm/test/CodeGen/RISCV machine-outliner-call-reg-live-across.mir

2026-01-26 18:47:18 UTC by Nemanja Ivanovic via GitHub on ⎇

users/arsenm/valuetracking/use-m_CheckedFp-isKnownIntegral

[RISC-V] Fix outliner candidate analysis (#177126)

When analyzing outliner candidates, there is no check that the tail-call
expansion register is live across the candidate call site. That can
result in a situation where the original function sets the volatile
register and uses it in the section that gets outlined. This of course
results in the use of the register receiving the incorrect value. Namely
the address of the outlined function since that is what the tail-call
sequence placed in the register.

Delta		File
+354	-0	llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir
+22	-6	llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+1	-0	llvm/lib/Target/RISCV/RISCVInstrInfo.h
+377	-6	3 files

LLVM/project 8d28955 — llvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/Transforms/InstCombine select-binop-associative-prof.ll

2026-01-26 18:44:45 UTC by Snehasish Kumar on ⎇

users/snehasish/01-24-_instcombine_preserve_prof_metadata_when_creating_select_instructions

[InstCombine] Preserve !prof metadata when creating select instructions.

Delta		File
+19	-0	llvm/test/Transforms/InstCombine/select-binop-associative-prof.ll
+3	-1	llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+22	-1	2 files

LLVM/project 9297558 — llvm/lib/Transforms/InstCombine InstructionCombining.cpp, llvm/test/Transforms/InstCombine branch.ll

2026-01-26 18:44:45 UTC by Snehasish Kumar on ⎇

users/snehasish/01-14-_instcombine_profcheck_propogate_profile_metadata_when_transforming_br_x_y_to_br_x_y_

[InstCombine][profcheck] Propogate profile metadata when transforming br (X && !Y) to br (!X || Y)

Updated visitBranchInst to propagate and swap !prof metadata when transforming br (X && !Y) to br (!X || Y).

Delta		File
+18	-7	llvm/test/Transforms/InstCombine/branch.ll
+12	-0	llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+30	-7	2 files

LLVM/project 0ae2043 — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll

2026-01-26 18:35:12 UTC by Matt Arsenault via GitHub on ⎇

main

AMDGPU: Disable machine verifier for gfx6 run line in test (#178008)

Hack around expensive checks failures for now.

Delta		File
+1	-1	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+1	-1	1 files

LLVM/project c9e0cf1 — llvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/Target/AMDGPU AMDGPUInstructions.td

2026-01-26 18:33:00 UTC by Mirko Brkušanin via GitHub on ⎇

main

[AMDGPU] Update patterns for v_cvt_flr and v_cvt_rpi (#177962)

Support GlobalISel and switch to checking `nnan` flag on instruction
instead of TargetOptions.
    
Instruction are renamed to v_cvt_floor and v_cvt_nearest on gfx11+
so add gfx11 tests as well.

Delta		File
+289	-39	llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
+248	-36	llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
+11	-9	llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+8	-0	llvm/include/llvm/Target/TargetSelectionDAG.td
+3	-0	llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td
+2	-1	llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+561	-85	6 files

LLVM/project ecb1b0b — mlir/lib/Bindings/Python IRCore.cpp

2026-01-26 18:32:08 UTC by Rolf Morel via GitHub on ⎇

main

[MLIR][Python] Fix overly specific type annotation on PyValue.owner (#178003)

Delta		File
+2	-1	mlir/lib/Bindings/Python/IRCore.cpp
+2	-1	1 files

LLVM/project bcf6d52 — llvm/test/MC/RISCV zibi-valid.s

2026-01-26 18:28:07 UTC by Fangrui Song via GitHub on ⎇

main

[RISCV] Test Zibi relocation type (#177896)

Zibi beqi/bnei (#127463) use a modified B-type format (replace `rs2`
with `cimm`) and reuse the R_RISCV_BRANCH relocation type.

Delta		File
+6	-1	llvm/test/MC/RISCV/zibi-valid.s
+6	-1	1 files

LLVM/project a2cf1d9 — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

2026-01-26 18:26:33 UTC by Florian Mayer on ⎇

users/fmayer/spr/hwasan-mte-allow-lifetimes-with-multiple-starts

rebase

Created using spr 1.3.6

Delta		File
+52,760	-0	polly/lib/External/isl/include/isl/typed_cpp.h
+19,051	-23,588	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+30,864	-0	polly/lib/External/isl/include/isl/cpp.h
+21,192	-0	polly/lib/External/isl/include/isl/cpp-checked.h
+19,097	-0	polly/lib/External/isl/interface/isl.py.core
+7,381	-11,318	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+150,345	-34,906	778 files not shown
+250,094	-135,053	784 files

LLVM/project 5aff076 — llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.960bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

2026-01-26 18:26:28 UTC by Florian Mayer on ⎇

users/fmayer/spr/main.hwasan-mte-allow-lifetimes-with-multiple-starts

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6

[skip ci]

Delta		File
+52,760	-0	polly/lib/External/isl/include/isl/typed_cpp.h
+19,051	-23,588	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+30,864	-0	polly/lib/External/isl/include/isl/cpp.h
+21,192	-0	polly/lib/External/isl/include/isl/cpp-checked.h
+19,097	-0	polly/lib/External/isl/interface/isl.py.core
+7,381	-11,318	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+150,345	-34,906	778 files not shown
+250,094	-135,053	784 files

LLVM/project fc6a5ed — llvm/lib/Transforms/Utils MemoryTaggingSupport.cpp, llvm/test/CodeGen/AArch64 stack-tagging-split-lifetime.ll stack-tagging-untag-placement.ll

2026-01-26 18:25:31 UTC by Florian Mayer via GitHub on ⎇

users/fmayer/spr/main.hwasan-mte-allow-lifetimes-with-multiple-starts

[HWASan] [MTE] use precise lifetimes even if they don't cover all exits

Previously, for performance reasons, we would only use precise lifetimes
if they cover all reachable exits. Now, if they do not, we use precise
lifetimes in addition to untagging at every exit that is not dominated
by them.

This is the behavior of ASan.

Reviewers: vitalybuka, pcc

Pull Request: https://github.com/llvm/llvm-project/pull/174875

Delta		File
+417	-14	llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
+46	-2	llvm/test/CodeGen/AArch64/stack-tagging-split-lifetime.ll
+9	-19	llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
+4	-2	llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll
+2	-1	llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll
+478	-38	5 files

LLVM/project c327d46 — llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.fract.ll llvm.amdgcn.frexp.mant.ll

2026-01-26 18:23:40 UTC by vangthao95 via GitHub on ⎇

users/fmayer/spr/main.hwasan-mte-allow-lifetimes-with-multiple-starts

[AMDGPU][GlobalISel] Add frexp_mant/fract intrinsic RegBankLegalize r… (#177512)

…ules

Delta		File
+96	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
+76	-0	llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
+8	-0	llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+180	-0	3 files