LLVM / project - FreshBSD

LLVM/project 0458162 — llvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

2026-01-19 05:49:36 UTC by vikhegde on ⎇

users/vikramRH/npm/npm_disable_machine_verifier

[CodeGen][NPM] Disable Machine verifier at the end of default pipelines

Delta		File
+4	-8	llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+3	-6	llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+0	-3	llvm/include/llvm/Passes/CodeGenPassBuilder.h
+7	-17	3 files

LLVM/project 72b9ae5 — llvm/lib/Target/RISCV RISCVFoldMemOffset.cpp, llvm/test/CodeGen/RISCV fold-mem-offset-zilsd.ll

2026-01-19 05:49:30 UTC by Sudharsan Veeravalli via GitHub on ⎇

main

[RISCV] Add Zilsd to RISCVFoldMemOffset (#176544)

Delta		File
+151	-0	llvm/test/CodeGen/RISCV/fold-mem-offset-zilsd.ll
+2	-0	llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+153	-0	2 files

LLVM/project ff783aa — llvm/lib/Transforms/Scalar LoopStrengthReduce.cpp

2026-01-19 05:43:54 UTC by vikhegde on ⎇

users/vikramRH/npm/lsr_lcssa_npm

[CodeGen][LSR][NPM] Make LoopStrengthReduce pass preserve LCSSA

Delta		File
+4	-0	llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+4	-0	1 files

LLVM/project 5572170 — llvm/lib/Target/AMDGPU SILowerControlFlow.cpp, llvm/test/CodeGen/AMDGPU si-lower-control-flow-preserve-dom-tree.mir

2026-01-19 05:43:54 UTC by vikhegde on ⎇

users/vikramRH/npm/preserve_dom_tree

[AMDGPU] Fix DomTree preservation in SILowerControlFlow when nodes are deleted

Delta		File
+59	-0	llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
+5	-0	llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+64	-0	2 files

LLVM/project 0e8e428 — llvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

2026-01-19 05:43:52 UTC by vikhegde on ⎇

users/vikramRH/npm/canon_freeze_mssa

[CodeGen][NPM] Isolate CanonicalizeFreezeInLoopsPass into a different adaptor

Delta		File
+4	-4	llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+4	-4	llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+6	-1	llvm/include/llvm/Passes/CodeGenPassBuilder.h
+14	-9	3 files

LLVM/project 6efff59 — clang/lib/CodeGen CGClass.cpp CGExprCXX.cpp

2026-01-19 05:39:09 UTC by VASU SHARMA via GitHub on ⎇

main

[UBSAN] [NFC] resolve clang-format errors (#175716)

PR to resolve clang-format errors in the files:

- `clang/lib/CodeGen/CGExprAgg.cpp`
- `clang/lib/CodeGen/CGExprCXX.cpp`
- `clang/lib/CodeGen/CGClass.cpp`

Co-authored-by: vasu-ibm <Vasu.Sharma2 at ibm.com>

Delta		File
+818	-852	clang/lib/CodeGen/CGClass.cpp
+235	-258	clang/lib/CodeGen/CGExprCXX.cpp
+82	-97	clang/lib/CodeGen/CGExprAgg.cpp
+1,135	-1,207	3 files

LLVM/project 10ceffb — llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

2026-01-19 05:29:41 UTC by vikhegde on ⎇

users/vikramRH/npm/complete_fast_regalloc

[AMDGPU][NPM] Complete fast regalloc pipeline

Delta		File
+38	-0	llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+10	-1	llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+48	-1	2 files

LLVM/project a312567 — llvm/lib/CodeGen LiveIntervals.cpp

2026-01-19 05:29:41 UTC by vikhegde on ⎇

users/vikramRH/npm/liveintervals_dump

[CodeGen][NPM] dump slot index info with -debug while running LiveIntervals

Delta		File
+4	-2	llvm/lib/CodeGen/LiveIntervals.cpp
+4	-2	1 files

LLVM/project 97b4714 — llvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

2026-01-19 05:29:41 UTC by vikhegde on ⎇

users/vikramRH/npm/physregusage_once

[CodeGen][NPM] Add "PhysicalRegisterUsageAnalysis" once

Delta		File
+6	-9	llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+1	-4	llvm/include/llvm/Passes/CodeGenPassBuilder.h
+7	-13	2 files

LLVM/project f2e1aff — llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp

2026-01-19 05:29:40 UTC by vikhegde on ⎇

users/vikramRH/npm/amdgpu_aa_opt

[AMDGPU][NPM] Obey "enable-amdgpu-aa" option

Delta		File
+2	-1	llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+2	-1	1 files

LLVM/project 01fe1c4 — llvm/lib/CodeGen BranchFolding.cpp BranchRelaxation.cpp, llvm/lib/Target/AMDGPU SIPreEmitPeephole.cpp

2026-01-19 05:29:40 UTC by vikhegde on ⎇

users/vikramRH/npm/update_block_numbers

[CodeGen][NPM] Update dominator tree and post dominator tree consistently

Delta		File
+11	-2	llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+11	-1	llvm/lib/CodeGen/BranchFolding.cpp
+10	-1	llvm/lib/CodeGen/BranchRelaxation.cpp
+7	-4	llvm/lib/CodeGen/MachineBlockPlacement.cpp
+39	-8	4 files

LLVM/project bfcbf5d — llvm/lib/CodeGen BranchFolding.cpp MachineBlockPlacement.cpp, llvm/lib/Target/AMDGPU SIPreEmitPeephole.cpp

2026-01-19 05:29:40 UTC by vikhegde on ⎇

users/vikramRH/npm/update_block_numbers

review comment

Delta		File
+8	-9	llvm/lib/CodeGen/BranchFolding.cpp
+9	-8	llvm/lib/CodeGen/MachineBlockPlacement.cpp
+8	-8	llvm/lib/CodeGen/BranchRelaxation.cpp
+7	-8	llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+32	-33	4 files

LLVM/project 1ccfb97 — llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

2026-01-19 05:29:40 UTC by vikhegde on ⎇

users/vikramRH/npm/amdgpu_enable_agpr_copy_mfma

[AMDGPU][NPM] Enable "AMDGPURewriteAGPRCopyMFMAPass"

Delta		File
+420	-418	llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+2	-0	llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+422	-418	2 files

LLVM/project 1887fca — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-ext-rv32.ll

2026-01-19 05:22:50 UTC by Brandon Wu via GitHub on ⎇

main

[RISCV][llvm] Handle sub-register vector shifts for P-extension (#176109)

For sub-register width vectors (v2i16, v4i8) on RV64 with P-extension,
the type legalizer widens them to legal types, i.e. v4i16, v8i8, before
they're getting unrolled, so they'll be redundant computation for higher
part of register.
The correct way to handle is similar to widening div/rem where there's
undef padded for high part.

stack on: https://github.com/llvm/llvm-project/pull/176093

Delta		File
+39	-119	llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+27	-1	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+66	-120	2 files

LLVM/project ed6b47d — clang/include/clang/Basic BuiltinsAMDGPU.def, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

2026-01-19 04:57:17 UTC by Aaditya on ⎇

users/easyonaadit/amdgpu/wave-reduce-intrinsics-double-builtins

[AMDGPU] Add builtins for wave reduction intrinsics

Delta		File
+84	-0	clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8	-0	clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4	-0	clang/include/clang/Basic/BuiltinsAMDGPU.def
+96	-0	3 files

LLVM/project 8adbac0 — llvm/docs AMDGPUUsage.rst

2026-01-19 04:57:17 UTC by Aaditya on ⎇

users/easyonaaditya/amdgpu/wave-reduce-intrinsics-update-docs

[AMDGPU] Update documentation for wave reduction intrinsics

Delta		File
+70	-4	llvm/docs/AMDGPUUsage.rst
+70	-4	1 files

LLVM/project f34c4e9 — llvm/lib/Target/AMDGPU SIISelLowering.cpp

2026-01-19 04:56:56 UTC by Aaditya on ⎇

users/easyonaadit/amdgpu/wave-reduce-intrinsics-double-add-sub

Use enum values for source modifiers

Delta		File
+3	-3	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3	-3	1 files

LLVM/project 2df642e — llvm/lib/Target/AMDGPU SIISelLowering.cpp

2026-01-19 04:51:59 UTC by Aaditya on ⎇

users/easyonaadit/amdgpu/wave-reduce-intrinsics-double-add-sub

Use pseudo opcode for switch statements

Delta		File
+10	-10	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+10	-10	1 files

LLVM/project b718f0a — llvm/lib/Target/AMDGPU SIISelLowering.cpp

2026-01-19 04:51:59 UTC by Aaditya on ⎇

users/easyonaadit/amdgpu/wave-reduce-intrinsics-double-add-sub

Use enum values for src modifiers.

Delta		File
+8	-8	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+8	-8	1 files

LLVM/project 7533267 — llvm/lib/Target/AMDGPU SIISelLowering.cpp

2026-01-19 04:51:59 UTC by Aaditya on ⎇

users/easyonaadit/amdgpu/wave-reduce-intrinsics-double-add-sub

Use `e32` encoding as placeholder

Delta		File
+10	-10	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+10	-10	1 files

LLVM/project b77bd3c — llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fadd.ll llvm.amdgcn.reduce.fsub.ll

2026-01-19 04:51:58 UTC by Aaditya on ⎇

users/easyonaadit/amdgpu/wave-reduce-intrinsics-double-add-sub

[AMDGPU] Add wave reduce intrinsics for double types - 2

Supported Ops: `add`, `sub`

Delta		File
+1,115	-0	llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+1,102	-0	llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+80	-19	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+2	-0	llvm/lib/Target/AMDGPU/SIInstructions.td
+2,299	-19	4 files

LLVM/project bae79cc — llvm/lib/Target/AMDGPU SIISelLowering.cpp

2026-01-19 04:49:17 UTC by Aaditya on ⎇

users/easyonaadit/amdgpu/wave-reduce-intrinsics-double-min-max

Use enum values for src modifiers

Delta		File
+4	-4	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+4	-4	1 files

LLVM/project 2a8a694 — llvm/lib/Target/RISCV RISCVCallingConv.cpp RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-ext-rv64.ll rvp-ext-rv32.ll

2026-01-19 04:09:27 UTC by Brandon Wu via GitHub on ⎇

main

[RISCV][llvm] Handle calling convention for P extension fixed vectors (#176093)

P extension packed SIMD types are passed in GPRs. For types larger than
XLen (e.g. v8i8 on RV32), they are split and passed via the 2XLen
mechanism, similar to i64 on RV32.

FIXME: Need to figure out the mechanism when P and V are enabled at the
same time.

stack on: https://github.com/llvm/llvm-project/pull/176193

Delta		File
+744	-1,642	llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+758	-1,393	llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+361	-0	llvm/test/CodeGen/RISCV/calling-conv-p-ext-vector.ll
+13	-6	llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+1	-11	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+10	-0	llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+1,887	-3,052	1 files not shown
+1,888	-3,052	7 files

LLVM/project 0e4c326 — .github/workflows ids-check.yml

2026-01-19 03:09:59 UTC by Mend Renovate via GitHub on ⎇

main

[Github] Update actions/upload-artifact action to v6 (#176677)

This PR contains the following updates:

| Package | Type | Update | Change |
|---|---|---|---|
|
[actions/upload-artifact](https://redirect.github.com/actions/upload-artifact)
| action | major | `v5.0.0` → `v6.0.0` |

---

> [!WARNING]
> Some dependencies could not be looked up. Check the Dependency
Dashboard for more information.

---

### Release Notes

    [40 lines not shown]

Delta		File
+1	-1	.github/workflows/ids-check.yml
+1	-1	1 files

LLVM/project 77009ca — llvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchFloat32InstrInfo.td, llvm/test/CodeGen/LoongArch load-itofp-combine.ll

2026-01-19 02:55:55 UTC by yangzhaoxin on ⎇

users/ylzsx/load-itofp-combine

[LoongArch] Convert ld to fld when result is only used by sitofp

If the result of an integer load is only used by an integer-to-float
conversion, use a fp load instead. This eliminates an
integer-to-float-move (movgr2fr) instruction.

Delta		File
+44	-0	llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+8	-23	llvm/test/CodeGen/LoongArch/load-itofp-combine.ll
+5	-0	llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
+3	-0	llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
+60	-23	4 files

LLVM/project 02eb33b — llvm/test/CodeGen/LoongArch load-itofp-combine.ll

2026-01-19 02:30:10 UTC by Zhaoxin Yang via GitHub on ⎇

main

[LoongArch][NFC] Add tests for sitofp(load) combine (#165521)

Delta		File
+89	-0	llvm/test/CodeGen/LoongArch/load-itofp-combine.ll
+89	-0	1 files

LLVM/project fb3a5b0 — llvm/test/tools/llvm-profgen coff-profile.test, llvm/tools/llvm-profgen ProfiledBinary.cpp ProfiledBinary.h

2026-01-19 01:44:42 UTC by Haohai Wen via GitHub on ⎇

main

[PseudoProbe] Support loading pseudo probe from debug binary (#175698)

Pseudo probe and DWARF sections can occupy a significant amount of space
in binary for large application. An executable PE image file should not
be larger than 2GB on Windows. To support LBR collection for those large
applications, user can use llvm-objcopy to strip those debug sections
and produce a smaller binary for profiling. The original binary can then
be used as the debug binary to load pseudo probe and DWARF info.

Delta		File
+34	-19	llvm/tools/llvm-profgen/ProfiledBinary.cpp
+5	-4	llvm/tools/llvm-profgen/ProfiledBinary.h
+5	-0	llvm/test/tools/llvm-profgen/coff-profile.test
+44	-23	3 files

LLVM/project 7f96336 — llvm/lib/LTO LTOBackend.cpp, llvm/test/ThinLTO/X86 thinlto-savetemps-mod.ll

2026-01-19 01:34:25 UTC by Tianle Liu via GitHub on ⎇

main

[LTOBackend] Add -filter-save-modules= for save-temps to only dump specific modules. (#175696)

Only if module's name contains a string in -filter-save-modules, will
its temp BC files be saved. If -filter-save-modules= not set, all
modules' BC files will be saved. This feature is more useful for ThinLto
when huge numbers of modules are built separately. Using
-filter-save-modules= can reduce build time and size of generated files,
even avoid crash if some other unrelated files have issues during BC
files dumping.

Delta		File
+46	-0	llvm/test/ThinLTO/X86/thinlto-savetemps-mod.ll
+17	-1	llvm/lib/LTO/LTOBackend.cpp
+63	-1	2 files

LLVM/project 447a1db — llvm/lib/Target/X86 X86FixupSetCC.cpp, llvm/test/CodeGen/X86/apx setzucc.ll

2026-01-19 01:21:59 UTC by Phoebe Wang via GitHub on ⎇

main

[X86][APX] Ignore the use of EFLAGS when ZU is enabled (#176645)

Since we don't need to insert the XOR instruction.

Fixes redundant MOVXZ in https://godbolt.org/z/s9Kq6TPoW

Delta		File
+13	-0	llvm/test/CodeGen/X86/apx/setzucc.ll
+2	-1	llvm/lib/Target/X86/X86FixupSetCC.cpp
+15	-1	2 files

LLVM/project b140fb2 — mlir/lib/Dialect/MemRef/IR MemRefOps.cpp, mlir/test/Dialect/MemRef canonicalize.mlir

2026-01-19 01:11:36 UTC by Longsheng Mou via GitHub on ⎇

main

[mlir][memref] Support folding memref.load from global splat constants (#176627)

This change extends the memref.load folding hook to fold loads from
global constant memrefs initialized with splat values.

Delta		File
+18	-1	mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
+19	-0	mlir/test/Dialect/MemRef/canonicalize.mlir
+37	-1	2 files