LLVM/project 3891beaclang/lib/CIR/CodeGen CIRGenBuiltin.cpp, clang/test/CIR/CodeGenBuiltins builtin-undef-rvalue.cpp builtin-sync.cpp

[CIR] Implement missing __sync_* atomic builtins (#214606)

Add CIR codegen support for five legacy __sync_* builtins that
previously emitted "Not Yet Implemented" errors:

  __sync_val_compare_and_swap  ->  cir.atomic.cmpxchg (seq_cst)
  __sync_bool_compare_and_swap ->  cir.atomic.cmpxchg + cmp (seq_cst)
  __sync_swap                  ->  cir.atomic.xchg (seq_cst)
  __sync_lock_test_and_set     ->  cir.atomic.xchg (seq_cst)
  __sync_lock_release          ->  cir.store 0 (release)

Size-suffixed forms (_1, _2, _4, _8) are handled, covering 20 builtin
variants in total; the unsuffixed forms are rewritten by Sema and the
_16 variants fall back to errorBuiltinNYI.

The existing emitBinaryAtomic / emitBinaryAtomicPost infrastructure
already handled the arithmetic __sync_* family (fetch_and_add, etc.).
This patch adds the remaining compare-and-swap, exchange, and
lock-release helpers: emitAtomicCmpXchgValue, emitAtomicCmpXchgBool,

    [10 lines not shown]
DeltaFile
+186-0clang/test/CIR/CodeGenBuiltins/builtin-sync.cpp
+68-7clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
+1-1clang/test/CIR/CodeGenBuiltins/builtin-undef-rvalue.cpp
+255-83 files

LLVM/project cf618e1llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/lib/IR Verifier.cpp

Restrict intrinsic to fixed->scalable with same min EC

This simplifies a lot of the legalisation code. The codegen regressions
for 64b -> scalable 128b can be addressed with a DAG combiner in a
follow-up.
DeltaFile
+56-200llvm/test/CodeGen/AArch64/sve-vector-broadcast.ll
+16-71llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+23-59llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+0-68llvm/test/CodeGen/AArch64/vector-broadcast.ll
+17-17llvm/test/Verifier/vector-broadcast-intrinsic-invalid.ll
+9-18llvm/lib/IR/Verifier.cpp
+121-4337 files not shown
+135-49813 files

LLVM/project 155fe33llvm/test/CodeGen/AMDGPU llvm.sin.bf16.ll llvm.cos.bf16.ll, llvm/test/Transforms/InstCombine cos-sin-intrinsic.ll

[AMDGPU] Allow constant folding of bfloat
DeltaFile
+43-26llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+39-8llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll
+39-8llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll
+39-8llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
+39-8llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
+36-0llvm/test/Transforms/InstCombine/cos-sin-intrinsic.ll
+235-582 files not shown
+243-668 files

LLVM/project 74bed73clang/docs ReleaseNotes.md, clang/docs/analyzer checkers.md

[analyzer] Move the lifetime checkers from alpha.cplusplus to alpha.core (#216739)

This PR moves the lifetime checkers from `alpha.cplusplus` to
`alpha.core`. This PR is the beginning of future PRs that will bring the
lifetime checkers from `alpha` to `core`. To meet the requirements of a
`core` checker there are still missing works for these checkers that is
the reason this PR only moves them from `alpha.cplusplus` to
`alpha.core`.
DeltaFile
+60-59clang/docs/analyzer/checkers.md
+16-16clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
+2-2clang/test/Analysis/lifetime-bound.cpp
+1-1clang/test/Analysis/debug-lifetime-bound.cpp
+1-1clang/test/Analysis/dangling-ptr-deref.cpp
+2-0clang/docs/ReleaseNotes.md
+82-796 files

LLVM/project f30a8dfmlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp, mlir/test/Dialect/LLVMIR inlining-alias-scopes.mlir

[mlir][LLVM] Use a disjoint scope domain when inlining noalias

This matches recent changes to the LLVM inliner.

AI disclosure: Claude wrote the code, I wrote the commit message and
have done initial review.
DeltaFile
+28-25mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+10-18mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
+38-432 files

LLVM/project 56b7bf7mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp

Update comment
DeltaFile
+2-2mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+2-21 files

LLVM/project 6095daamlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp

Remove pointless comment
DeltaFile
+0-2mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+0-21 files

LLVM/project b67912emlir/test/Dialect/LLVMIR inlining-alias-scopes.mlir

Test that the inliner keeps the flag when it clones a domain

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+35-0mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
+35-01 files

LLVM/project 0cdf988mlir/include/mlir/Dialect/LLVMIR LLVMAttrDefs.td, mlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp

[mlir][LLVM] Add disjointScopes to AliasScopeDomainAttr

This also updates the MLIR-side inliner to clone disjoint domains
while cloning alias scopes, matching changes to LLVM.

AI disclosure: Claude wrote the code, I wrote the commit message and
looked at the code.
DeltaFile
+25-0mlir/test/Target/LLVMIR/Import/metadata-alias-scopes.ll
+23-0mlir/test/Target/LLVMIR/attribute-alias-scopes.mlir
+17-2mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
+4-2mlir/lib/Target/LLVMIR/ModuleImport.cpp
+4-1mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+2-2mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+75-76 files

LLVM/project e389b79llvm/lib/Target/AMDGPU AMDGPULowerKernelArguments.cpp, llvm/test/CodeGen/AMDGPU lower-kernargs.ll si-split-load-store-alias-info.ll

[AMDGPU] Use a disjoint scope domain for noalias kernel arguments

All noalias arguments of a kernel are disjoint with each other, so we
can use a disjoint scope to save on metadata construction.

AI disclosure: Claude wrote this, I looked at it and wrote this
message.
DeltaFile
+53-64llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
+20-13llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
+11-11llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
+8-8llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
+4-4llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
+96-1005 files

LLVM/project e719840llvm/lib/Target/AMDGPU AMDGPULowerModuleLDSPass.cpp, llvm/test/CodeGen/AMDGPU lower-lds-struct-aa-memcpy.ll remove-no-kernel-id-attribute.ll

[AMDGPU] Use a disjoint scope domain for merged LDS structs

When lowering LDS values, all the values are mutually disjoint, so we
can use the newly-added disjoint scopes feature to simplify the IR.

AI disclosure: Claude wrote this and I reviewed it and wrote the
 commit message
DeltaFile
+15-52llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+35-10llvm/test/CodeGen/AMDGPU/lower-module-lds-precise-allocate-to-module-struct.ll
+15-18llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
+11-13llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
+8-12llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
+9-10llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll
+93-1156 files not shown
+139-16112 files

LLVM/project c25e2cdllvm/test/Transforms/Inline noalias2.ll

Test a callee that has both noalias arguments and its own scopes

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+51-0llvm/test/Transforms/Inline/noalias2.ll
+51-01 files

LLVM/project 3d4d493clang/test/CodeGen arm_neon_intrinsics.c arm-v8.2a-neon-intrinsics-generic.c, llvm/lib/Bitcode/Reader MetadataLoader.cpp

[IR] Add alias scope domains with disjoint scopes

See RFC at
https://discourse.llvm.org/t/rfc-disjoint-scope-alias-scope-noalias-domains/91537

This commit adds support for declaring an alias scope domain disjoint.
Disjoint domains are ones where each scope is implicitly `!noalias`
with each other scope in the domain. This is represented by adding an
`i1` into the scope's domain as the second argument, with `i1 true`
representing disjoint scopes and `i1 false` representing the old
non-disjoint behavior. AutoUpgrade mechanisms have been added to add
in the missing `i1 false` to existing metadata.

This commit updates alias analysis to know about disjoint scopes and
updates the function cloner to also clone the alias domain if it's
disjoint (since, as a herd of LLMs discovered, you don't want the old
IR to be noalias with a clone of itself).

Commits to migrate passes to use disjoint scopes where that's an

    [4 lines not shown]
DeltaFile
+72-72clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
+54-54clang/test/CodeGen/arm_neon_intrinsics.c
+97-0llvm/lib/Bitcode/Reader/MetadataLoader.cpp
+95-0llvm/test/Transforms/InstCombine/noalias-scope-decl-disjoint-domain.ll
+42-42llvm/test/Transforms/LoopUnroll/peel-loop-noalias-scope-decl.ll
+39-35llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
+399-203189 files not shown
+1,342-718195 files

LLVM/project 1d8c2b1clang/test/CodeGen arm-v8.2a-neon-intrinsics-generic.c arm_neon_intrinsics.c, llvm/lib/Transforms/Utils InlineFunction.cpp

[Inliner] Use a disjoint scope domain for noalias arguments

InlineFunction creates alias.scope/noalias metadata to represent the
set of `noalias` arguments to a function. We don't need the `!noalias`
now that we have the ability to use disjoint scopes, saving us IR size
and metadata bloat.

TODO move these to a previous commit.
Also changes InstCombine to not drop the experimental.noalias.scope.decl
for disjoint scopes even if they're not mentioned in a `!noalias`, but
do still delete them if they're not used.
DeltaFile
+324-324clang/test/CodeGen/arm_neon_intrinsics.c
+72-72clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
+35-30llvm/lib/Transforms/Utils/InlineFunction.cpp
+13-14llvm/test/Transforms/Inline/noalias-calls2.ll
+12-12llvm/test/Transforms/Inline/noalias2.ll
+11-11llvm/test/Transforms/PhaseOrdering/pr39282.ll
+467-4639 files not shown
+487-48315 files

LLVM/project bd58db9llvm/test/tools/UpdateTestChecks/update_test_checks dot_value_in_metadata_string.test, llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs dot_value_in_metadata_string.ll dot_value_in_metadata_string.ll.expected

[UTC] Don't rename %. inside quoted strings in test checkseg (#218767)

Replacing `%.foo` with `%dotfoo` everywhere also caught any `%.foo`
inside metadata, which would then cause incorrect CHECK lines to be
generated (since the value in the metedata isn't going to be
modified).

This commit fixes this by moving from a search-replace on the input to
mangling in the variable name emitter.

AI disclosure: Claude found and fixed this, I wrote the commit message.
DeltaFile
+22-0llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/dot_value_in_metadata_string.ll.expected
+11-0llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/dot_value_in_metadata_string.ll
+10-0llvm/test/tools/UpdateTestChecks/update_test_checks/dot_value_in_metadata_string.test
+2-2llvm/utils/UpdateTestChecks/common.py
+45-24 files

LLVM/project 8b2867eflang/docs/MeetingNotes/2026 2026-08-26.md

[flang] Adding Flang Community Call notes from the 2026-08-26 meeting (#219051)
DeltaFile
+82-0flang/docs/MeetingNotes/2026/2026-08-26.md
+82-01 files

LLVM/project a1ab1f7clang/lib/Sema SemaChecking.cpp

[clang][Sema] Fix iterator invalidation in isLayoutCompatibleUnion (#219112)

This patch fixes an iterator invalidation bug in
isLayoutCompatibleUnion.

Without this patch, if we delete a matching field, we end up
evaluating I == E even though the iterators are invalidated.  Deleting
a match after the loop fixes the problem.

This bug was discovered with tightened epoch checks in
SmallPtrSetIterator.

Assisted-by: Antigravity
DeltaFile
+6-12clang/lib/Sema/SemaChecking.cpp
+6-121 files

LLVM/project 58bf038llvm/lib/Target/NVPTX NVPTXSubtarget.h NVPTXSubtarget.cpp, llvm/test/CodeGen/NVPTX sm-version.ll sm-110-rename.ll

[NVPTX] Rewrite sm_110* to sm_101* as demanded by PTX version (#218968)
DeltaFile
+44-0llvm/test/CodeGen/NVPTX/sm-110-rename.ll
+27-3llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+8-6llvm/test/CodeGen/NVPTX/sm-version.ll
+1-1llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+80-104 files

LLVM/project 68bdb06llvm/lib/Target/WebAssembly WebAssemblyInstrSIMD.td, llvm/test/CodeGen/WebAssembly f16-intrinsics.ll

[WebAssembly] Add v8f16 bitselect pattern (#218954)
DeltaFile
+12-0llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
+1-1llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+13-12 files

LLVM/project 731cb34llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV zicond-opts.ll

[RISCV] Optimize `(and (i1) f, (setcc a, b, eq))` to use the zicond extension (#217946)

This is a generalization of the previously existing rule, that required
one of the sides of the `setcc` to be zero.

With this commit we now support comparisons between any two variables.
This requires us to insert an additional instruction to compare the two.
But it is still beneficial vs the unoptimized lowering as it reduces 1
instruction in the output.

This fixes one of the issues identified in #179584. Namely `test_lt3`,
now uses `czero.{nez,eqz}` for those cases.

AI Disclosure: I have used AI to help me understand the LLVM build and
test system as well as to understand the existing codebase. The new code
add in this PR is authored by me.
DeltaFile
+124-8llvm/test/CodeGen/RISCV/zicond-opts.ll
+23-7llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+147-152 files

LLVM/project 68fa1e1clang/docs ReleaseNotes.md

Update the release notes.
DeltaFile
+2-0clang/docs/ReleaseNotes.md
+2-01 files

LLVM/project fd62b48llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

Refactor to enable scalars inline instead of seperate helper function
DeltaFile
+23-38llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+50-0llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+73-382 files

LLVM/project f1e4e4cllvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

Testing updates per PR feedback, add some new test cases
DeltaFile
+87-6llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+87-61 files

LLVM/project 4f2cc7ellvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-mixed-width-access.ll

[AMDGPU] PromoteAlloca: split scalar accesses that span several elements

promoteAllocaToVector already splits a *vector* access across several
elements when it is a multiple of the element size, but a *scalar* access
had to be bitcastable to the element type, so an i64 load from an alloca
promoted to <8 x i32> was rejected as "not a supported access type" and
the object stayed in scratch.

Accept a scalar access that is a whole multiple of the element size and
route it through the existing subvector path, which already builds the
value from consecutive elements and bitcasts. Accesses with padding are
still rejected, since splitting those would put the pieces at the wrong
offsets, as are non-integer non-float types.
DeltaFile
+78-0llvm/test/CodeGen/AMDGPU/promote-alloca-mixed-width-access.ll
+28-4llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+106-42 files

LLVM/project ac2d1cfllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-select.ll promote-alloca-homogeneous-struct.ll

[AMDGPU] PromoteAlloca: flatten homogeneous structs to vectors

getVectorTypeForAlloca() peeled nested ArrayType and one inner
FixedVectorType, but stopped at any StructType. An alloca of an array of
structs was therefore rejected with "Cannot convert type to vector" and
fell back to scratch, even when the struct was a trivial wrapper around a
scalar.

Peel structs too, but only when every field has the same type and the
struct has no padding, so flattened elements keep the byte offsets the
surrounding index arithmetic assumes. Structs with differing field types
or with padding are left alone.
DeltaFile
+59-0llvm/test/CodeGen/AMDGPU/promote-alloca-homogeneous-struct.ll
+35-6llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+6-1llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
+100-73 files

LLVM/project 11e4850llvm/test/CodeGen/AMDGPU promote-alloca-homogeneous-struct.ll

Update script version and triple format per PR feedback
DeltaFile
+2-2llvm/test/CodeGen/AMDGPU/promote-alloca-homogeneous-struct.ll
+2-21 files

LLVM/project 79a6d76llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-select.ll promote-alloca-homogeneous-struct.ll

Simplify logic via suggestions from PR feedback. Add additional test cases, make tests a bit more complex so they don't fold into simple store of constant
DeltaFile
+101-8llvm/test/CodeGen/AMDGPU/promote-alloca-homogeneous-struct.ll
+4-16llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+4-4llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.ll
+109-283 files

LLVM/project a8612a9libc/include/llvm-libc-types struct_sigevent.h

[libc] Add self-define for sigev_notify_thread_id field. (#219067)

Support downstream code that assumes `sigev_notify_thread_id`, even
though defined for Linux is a macro that expands to use private `struct
sigevent` fields.
DeltaFile
+3-0libc/include/llvm-libc-types/struct_sigevent.h
+3-01 files

LLVM/project 71d2dc2flang/include/flang/Semantics openmp-modifiers.h, flang/lib/Semantics check-omp-variant.cpp check-omp-structure.h

[flang][OpenMP] Remove OmpVerifyModifiers

Verification of clause modifiers is now done in a single place.
The OmpVerifyModifiers function was left in place, but was reduced
to always return "true".

Remove the definition and all calls to it.

The large amount of apparent changes is mostly due to unindenting
and reformatting previously indented code.
DeltaFile
+175-265flang/lib/Semantics/check-omp-structure.cpp
+44-49flang/lib/Semantics/check-omp-loop.cpp
+0-6flang/include/flang/Semantics/openmp-modifiers.h
+0-2flang/lib/Semantics/check-omp-variant.cpp
+0-2flang/lib/Semantics/check-omp-structure.h
+219-3245 files

LLVM/project fafffb0flang/test/Semantics/OpenMP declare-variant-v61.f90

Add testcase for missing required modifier group
DeltaFile
+30-0flang/test/Semantics/OpenMP/declare-variant-v61.f90
+30-01 files