LLVM/project d600ac3llvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/CodeGen/ARM atomic-load-store.ll

[AtomicExpand] Add bitcasts when expanding load atomic vector

AtomicExpand fails for aligned `load atomic <n x T>` because it
does not find a compatible library call. This change adds appropriate
bitcasts so that the call can be lowered.

commit-id:f430c1af
DeltaFile
+65-0llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+51-0llvm/test/CodeGen/ARM/atomic-load-store.ll
+30-0llvm/test/CodeGen/X86/atomic-load-store.ll
+17-3llvm/lib/CodeGen/AtomicExpandPass.cpp
+163-34 files

LLVM/project 28f6bf3llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Split vector types for atomic load

Vector types that aren't widened are split
so that a single ATOMIC_LOAD is issued for the entire vector at once.
This change utilizes the load vectorization infrastructure in
SelectionDAG in order to group the vectors. This enables SelectionDAG
to translate vectors with type bfloat,half.

commit-id:3a045357
DeltaFile
+171-0llvm/test/CodeGen/X86/atomic-load-store.ll
+39-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+211-03 files

LLVM/project 6897d31llvm/include/llvm/CodeGen SelectionDAG.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGAddressAnalysis.cpp SelectionDAG.cpp

[SelectionDAG][X86] Remove unused elements from atomic vector.

After splitting, all elements are created. The two components must
be found by looking at the upper and lower half of EXTRACT_ELEMENT.
This change extends EltsFromConsecutiveLoads
to understand AtomicSDNode so that unused elements can be removed.

commit-id:b83937a8
DeltaFile
+16-151llvm/test/CodeGen/X86/atomic-load-store.ll
+31-12llvm/lib/Target/X86/X86ISelLowering.cpp
+17-13llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
+12-8llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+5-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+2-2llvm/include/llvm/CodeGen/SelectionDAG.h
+83-1876 files

LLVM/project fc2debellvm/include/llvm/CodeGen SelectionDAG.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGAddressAnalysis.cpp SelectionDAG.cpp

[SelectionDAG][X86] Remove unused elements from atomic vector.

After splitting, all elements are created. The two components must
be found by looking at the upper and lower half of EXTRACT_ELEMENT.
This change extends EltsFromConsecutiveLoads
to understand AtomicSDNode so that unused elements can be removed.

commit-id:b83937a8
DeltaFile
+16-151llvm/test/CodeGen/X86/atomic-load-store.ll
+31-12llvm/lib/Target/X86/X86ISelLowering.cpp
+17-13llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
+12-8llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+5-1llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+2-2llvm/include/llvm/CodeGen/SelectionDAG.h
+83-1876 files

LLVM/project 681d443llvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/CodeGen/ARM atomic-load-store.ll

[AtomicExpand] Add bitcasts when expanding load atomic vector

AtomicExpand fails for aligned `load atomic <n x T>` because it
does not find a compatible library call. This change adds appropriate
bitcasts so that the call can be lowered.

commit-id:f430c1af
DeltaFile
+65-0llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+51-0llvm/test/CodeGen/ARM/atomic-load-store.ll
+30-0llvm/test/CodeGen/X86/atomic-load-store.ll
+17-3llvm/lib/CodeGen/AtomicExpandPass.cpp
+163-34 files

LLVM/project 218ce15llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/lib/Target/X86 X86InstrCompiler.td

[SelectionDAG][X86] Widen <2 x T> vector types for atomic load

Vector types of 2 elements must be widened. This change does this
for vector types of atomic load in SelectionDAG
so that it can translate aligned vectors of >1 size. Also,
it also adds Pats to remove an extra MOV.

commit-id:2894ccd1
DeltaFile
+83-21llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+81-0llvm/test/CodeGen/X86/atomic-load-store.ll
+7-0llvm/lib/Target/X86/X86InstrCompiler.td
+1-2llvm/test/CodeGen/X86/atomic-unordered.ll
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+173-235 files

LLVM/project acfcbccllvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Add atomic vector tests for unaligned >1 sizes.

Unaligned atomic vectors with size >1 are lowered to calls.
Adding their tests separately here.

commit-id:a06a5cc6
DeltaFile
+253-0llvm/test/CodeGen/X86/atomic-load-store.ll
+253-01 files

LLVM/project fdc2107llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Manage atomic load of fp -> int promotion in DAG

When lowering atomic <1 x T> vector types with floats, selection can fail since
this pattern is unsupported. To support this, floats can be casted to
an integer type of the same size.

commit-id:f9d761c5
DeltaFile
+37-0llvm/test/CodeGen/X86/atomic-load-store.ll
+4-0llvm/lib/Target/X86/X86ISelLowering.cpp
+41-02 files

LLVM/project db5b862llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Split vector types for atomic load

Vector types that aren't widened are split
so that a single ATOMIC_LOAD is issued for the entire vector at once.
This change utilizes the load vectorization infrastructure in
SelectionDAG in order to group the vectors. This enables SelectionDAG
to translate vectors with type bfloat,half.

commit-id:3a045357
DeltaFile
+171-0llvm/test/CodeGen/X86/atomic-load-store.ll
+37-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+209-03 files

LLVM/project ae25bedllvm/docs LangRef.rst ReleaseNotes.md, llvm/lib/IR Verifier.cpp

IR/Verifier: Allow vector type in atomic load and store

Vector types on atomics are assumed to be invalid by the verifier. However,
this type can be valid if it is lowered by codegen.

commit-id:72529270
DeltaFile
+19-0llvm/test/Assembler/atomic.ll
+8-7llvm/test/Verifier/atomics.ll
+8-6llvm/lib/IR/Verifier.cpp
+4-4llvm/docs/LangRef.rst
+1-0llvm/docs/ReleaseNotes.md
+40-175 files

LLVM/project e7805ffllvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Legalize <1 x T> vector types for atomic load

`load atomic <1 x T>` is not valid. This change legalizes
vector types of atomic load via scalarization in SelectionDAG
so that it can, for example, translate from `v1i32` to `i32`.

commit-id:5c36cc8c
DeltaFile
+119-2llvm/test/CodeGen/X86/atomic-load-store.ll
+15-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+135-23 files

LLVM/project cd6c4b6llvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp, llvm/test/CodeGen/AMDGPU mad-mix.ll mad-mix-lo.ll

[AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (#124995)

remove unnecessary COPY for SDAG for mad-mix pattern
DeltaFile
+75-170llvm/test/CodeGen/AMDGPU/mad-mix.ll
+57-135llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+15-18llvm/test/CodeGen/AMDGPU/frem.ll
+5-0llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+152-3234 files

LLVM/project 3f1267eclang/tools/clang-offload-bundler ClangOffloadBundler.cpp

[NFC][clang-offload-bundler] Simplify main function (#138555)

Applied "no else after return" rule from the LLVM's Coding Standards
https://llvm.org/docs/CodingStandards.html#don-t-use-else-after-a-return
DeltaFile
+4-7clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
+4-71 files

LLVM/project 4253405llvm/lib/Target/AArch64/MCTargetDesc AArch64ELFObjectWriter.cpp, llvm/test/MC/AArch64 ilp32-diagnostics.s adrp-auth-relocation.s

AArch64: Clean up relocation error messages.

"<foo> relocation is not supported in ILP32" is more accurate than
what we have now.

Also, remove "LP64 eqv:" annotations because they create a maintenance
burden and are unlikely to be helpful.

Reviewers: kovdan01, MaskRay

Reviewed By: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/138625
DeltaFile
+39-79llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+29-29llvm/test/MC/AArch64/ilp32-diagnostics.s
+1-1llvm/test/MC/AArch64/adrp-auth-relocation.s
+1-1llvm/test/MC/AArch64/error-location.s
+70-1104 files

LLVM/project 6c8ba82llvm/lib/Target/AArch64/MCTargetDesc AArch64ELFObjectWriter.cpp

Remove unnecessary bool

Created using spr 1.3.6-beta.1
DeltaFile
+4-3llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+4-31 files

LLVM/project 6234aballvm/lib/Target/X86 X86FrameLowering.cpp

[llvm] No DWARF CFI for UEFI (#138602)

UEFI target uses WinCFI. Update emitEpilogue function to reflect this.
DeltaFile
+2-1llvm/lib/Target/X86/X86FrameLowering.cpp
+2-11 files

LLVM/project 91218b4llvm/lib/Target/AArch64/MCTargetDesc AArch64ELFObjectWriter.cpp, llvm/test/MC/AArch64 ilp32-diagnostics.s adrp-auth-relocation.s

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+35-76llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+29-29llvm/test/MC/AArch64/ilp32-diagnostics.s
+1-1llvm/test/MC/AArch64/adrp-auth-relocation.s
+1-1llvm/test/MC/AArch64/error-location.s
+66-1074 files

LLVM/project c6c2e21utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[bazel] Update Sparc (for #138450)
DeltaFile
+4-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+4-01 files

LLVM/project 658cac8clang/include/clang/Basic BuiltinsRISCVXCV.td, clang/lib/CodeGen/TargetBuiltins RISCV.cpp

[RISCV] Rename XCValu intrinsic name *_slet(u) to *_sle(u)) (#138498)

The instruction name and intrinsic name have been renamed to sle(u). The
`t` was removed. Please refer to
https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md.
DeltaFile
+6-6clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
+6-6clang/test/CodeGen/RISCV/riscv-xcvalu.c
+4-4clang/lib/Headers/riscv_corev_alu.h
+4-4llvm/test/CodeGen/RISCV/xcvalu.ll
+2-2clang/include/clang/Basic/BuiltinsRISCVXCV.td
+2-2clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+24-246 files

LLVM/project ca1ebffclang/test/Driver riscv-cpus.c, clang/test/Driver/print-enabled-extensions riscv-sifive-p870.c

[RISCV] Add processor definition for SiFive P870 (#137725)

SiFive P870 is a RVA23 compatible high-performance CPU:
https://www.sifive.com/cores/performance-p800

Scheduling model will be added in a follow-up PR.
DeltaFile
+81-0clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c
+24-0llvm/lib/Target/RISCV/RISCVProcessors.td
+5-0clang/test/Driver/riscv-cpus.c
+2-0clang/test/Misc/target-invalid-cpu-note/riscv.c
+1-0llvm/docs/ReleaseNotes.md
+113-05 files

LLVM/project 5709a2cllvm/utils/gn/secondary/llvm/lib/Target/Sparc BUILD.gn

[gn build] Port 7aa67378f01f
DeltaFile
+11-0llvm/utils/gn/secondary/llvm/lib/Target/Sparc/BUILD.gn
+11-01 files

LLVM/project 8404b29llvm/lib/Transforms/Utils Local.cpp

[llvm][NFC] Fix bracing from #138414 (#138620)

I had forgotten to upload the formatting change.
DeltaFile
+1-2llvm/lib/Transforms/Utils/Local.cpp
+1-21 files

LLVM/project 43eafc0llvm/lib/Transforms/Utils Local.cpp, llvm/test/Transforms/GVNSink pr138345.ll

[llvm][gvn-sink] Don't try to sink inline asm (#138414)

Fixes #138345. Before this patch, gvn-sink would try to sink inline
assembly statements. Other GVN passes avoid them (see
https://github.com/llvm/llvm-project/blob/b4fac94181c4cf17dbb7ecc2ae975712b0e4a6d1/llvm/lib/Transforms/Scalar/GVN.cpp#L2932
Similarly, gvn-sink should skip these instructions, since they are not
safe to move. To do this, we update the early exit in
canReplaceOperandWithVariable, since it should have caught this case.
It's more efficient to also skip numbering in GVNSink if the instruction
is InlineAsm, but that should be infrequent.

The test added is reduced from a failure when compiling Fuchsia with
gvn-sink.
DeltaFile
+46-0llvm/test/Transforms/GVNSink/pr138345.ll
+2-1llvm/lib/Transforms/Utils/Local.cpp
+48-12 files

LLVM/project 35f9dfbllvm/test/CodeGen/AMDGPU global-atomicrmw-fadd.ll gep-const-address-space.ll, llvm/test/CodeGen/AMDGPU/GlobalISel divergent-control-flow.ll

[AMDGPU] Don't run InferAddressSpacesPass in code generation pipeline
DeltaFile
+0-341llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+56-54llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
+38-8llvm/test/CodeGen/AMDGPU/gep-const-address-space.ll
+18-17llvm/test/CodeGen/AMDGPU/uniform_branch_with_floating_point_cond.ll
+16-11llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
+10-15llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
+138-4465 files not shown
+172-46511 files

LLVM/project 1c1238dlldb/tools/lldb-dap DAP.cpp

[lldb-dap] Don't error out when the process is in eStateUnloaded (#138601)

DAP::WaitForProcessToStop treats the process in eStateUnloaded as an
error. The process is in this state when it has just been created
(before an attach or launch) or when it's restarted. Neither should be
treated as errors.

The current implementation can trigger this error (and a corresponding
test failure) when we call WaitForProcessToStop after attaching in
asynchronous mode (for example when using ConnectRemote which is always
asynchronous (due to a bug).
DeltaFile
+1-3lldb/tools/lldb-dap/DAP.cpp
+1-31 files

LLVM/project 4727529llvm/include/llvm/ProfileData DataAccessProf.h, llvm/lib/ProfileData DataAccessProf.cpp

resolve review feedback
DeltaFile
+22-21llvm/lib/ProfileData/DataAccessProf.cpp
+24-13llvm/include/llvm/ProfileData/DataAccessProf.h
+11-12llvm/unittests/ProfileData/MemProfTest.cpp
+57-463 files

LLVM/project b12d780clang/lib/Sema SemaExprCXX.cpp

[clang] Ensure type aware allocators handle transparent decl contexts

We were testing the immediate DeclContext for found new and delete
operators, which is incorrect if the declarations are contained by
a transparent decl as can be induced with extern or export statements.
DeltaFile
+13-8clang/lib/Sema/SemaExprCXX.cpp
+13-81 files

LLVM/project 8b9ae65llvm/lib/Target/AMDGPU GCNIterativeScheduler.cpp, llvm/test/CodeGen/AMDGPU coalesce-copy-to-agpr-to-av-registers.mir

Revert "[AMDGPU] Extend test coverage for cross RC register coalescing (#132137)"

This reverts commit 0bd065dc943ff65e0749a9f2a7b7a672acd45193.
DeltaFile
+1-2,258llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
+0-5llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
+1-2,2632 files

LLVM/project 0261c9cllvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-6.ll vector-interleaved-store-i16-stride-7.ll, llvm/test/Transforms/InstCombine/AArch64 sve-intrinsics-combine-to-u-forms.ll sve-intrinsic-comb-m-forms-no-active-lanes.ll

Avoid using InstSP directly

Created using spr 1.3.5
DeltaFile
+0-2,021llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-combine-to-u-forms.ll
+866-874llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+744-762llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,102-274mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+0-1,324llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-m-forms-no-active-lanes.ll
+1,235-0llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll
+3,947-5,2552,146 files not shown
+55,233-27,7342,152 files

LLVM/project 017dfacllvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-6.ll vector-interleaved-store-i16-stride-7.ll, llvm/test/Transforms/InstCombine/AArch64 sve-intrinsics-combine-to-u-forms.ll sve-intrinsic-comb-m-forms-no-active-lanes.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.5

[skip ci]
DeltaFile
+0-2,021llvm/test/Transforms/InstCombine/AArch64/sve-intrinsics-combine-to-u-forms.ll
+866-874llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+744-762llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+1,102-274mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+0-1,324llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-m-forms-no-active-lanes.ll
+1,235-0llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll
+3,947-5,2552,145 files not shown
+55,221-27,7142,151 files