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[RISCV] Don't unroll vectorized loops with vector operands (#171089)

We have disabled unrolling for vectorized loops in #151525 but this
PR only checked the instruction type.

For some loops, there is no instruction with vector type but they
are still vector operations (just like the memset zero test in the
precommit test).

Here we check the operands as well to cover these cases.

fix missing newline

Created using spr 1.3.8-beta.1

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]

[OpenCL] Add missing Intel extensions to OpenCLExtensions.def (#169875)

Add following extensions:
cl_intel_bfloat16_conversion
cl_intel_subgroup_buffer_prefetch
cl_intel_subgroup_local_block_io
cl_intel_subgroups_char
cl_intel_subgroups_long

This allows targets to expose these extensions via
getSupportedOpenCLOpts and ensures macros are defined when enabled.

Merge branch 'main' into broadcastpropagation

add setUnitDimData/Layout interface and refactor

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1

[RISCV] Precommit test for unrolling loops with vector operands

[LTT] Add `unknown` branch weights when lowering type tests with conditional

[NFC] Run UTC --check-globals on LowerTypeTests/import.ll (#170755)

[AArch64] Fix missing register definitions in homogeneous epilog lowering (#171118)

The lowering for HOM_Epilog did not transfer explicit register defs from
the pseudo-instruction to the generated helper calls. MachineVerifier
would complain if a following tail call uses one of the restored CSRs.
This scenario occurs in code generated by the Swift compiler, where X20
is used to pass swiftself.

This patch fixes the issue by adding the missing defs back to the helper
call as implicit defs.

[NFC][libclc] Delete OpenCL builtin declarations (#170803)

This is follow-up of comment
https://github.com/llvm/llvm-project/pull/168318#discussion_r2588117855

libclc OpenCL library is already compiled with flag
`-fdeclare-opencl-builtins -finclude-default-header`.

release notes

Created using spr 1.3.7

[AMDGPU][NFC] cleanup whitespace in debug log of SIInsertWaitcnts

doc

Created using spr 1.3.7

[AMDGPU][NFC] fix function names in debug log for SIInsertWaitcnts

test

Created using spr 1.3.7

[NVPTX] Fix lit test issue from used_bytes_mask (#171220)

Whoops, I made the same mistake as
https://github.com/llvm/llvm-project/pull/169535/files again, so
https://github.com/llvm/llvm-project/commit/5c8c7f3d21ce37bfecd671de4e139a4d933f9be9
is causing build issues.

[PowerPC] Use the same lowering rule for vector rounding instructions (#166307)

They should have the same lowering rule.

[Flang][Fir] Fix the comparison when lowering `fir.iterate_while` to `scf.while`. (#171080)

The comparison depends on the sign of the `step`, and when `step == 0` it always returns `false`.

[mlir][math] Add FP software implementation lowering pass: math-to-apfloat

[AArch64] Treat NOP as a separate instruction. (#170968)

Previously, nop was treated as just an alias for hint #0. The
consequence of that was that all the general rules for hint instructions
applied to nop too, in particular that during binary analysis, they were
assumed to have unknown effects. This commit adds AArch64::NOP as a
standalone instruction with no side effects.

The scheduling update in A55-load-store-alias.s is probably not entirely
accurate, but should be more accurate than the previous result.

[mlir][math] Add FP software implementation lowering pass: math-to-apfloat

[mlir][CMake] enable disabling MLIR_ENABLE_EXECUTION_ENGINE (#171060)

Currently if you pass MLIR_ENABLE_EXECUTION_ENGINE=OFF it's overwritten.

[Clang] Fix unused variable warning from 1911ce132659222aee353882bd55… (#171223)

…70d689745a7d

These are only used in assertions so trigger warnings in release builds.
Fix this per the LLVM programming standards.

[mlir][math] Add FP software implementation lowering pass: math-to-apfloat

[CIR][X86] Implement lowering for sqrt builtins (#169310)

Implements CIR IR generation for X86-specific sqrt builtin functions,
addressing issue #167765.

## Test Results 

Successfully tested the implementation locally. All tests pass:

```bash
$ ./bin/llvm-lit -v ../clang/test/CIR/CodeGen/X86/cir-sqrt-builtins.c

Testing: 1 tests, 1 workers
PASS: Clang :: CIR/CodeGen/X86/cir-sqrt-builtins.c (1 of 1)

Testing Time: 1.18s
Total Discovered Tests: 1
  Passed: 1 (100.00%)
```

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[mlir][math] Add FP software implementation lowering pass: math-to-apfloat

AMDGPU: Fix truncstore from v6f32 to v6f16 (#171212)

The v6bf16 cases work, but that's likely because v6bf16 isn't
currently an MVT.

Fixes: SWDEV-570985

Fix a typo in "breakpoint add file" and add a test (#171206)

lldbutil.run_to_line_breakpoint had usages that set column breakpoints,
so I thought there was coverage of that on the command-line, but
actually all the `run_to` utilities use the SB API's, and there weren't
any tests of setting file line & column breakpoint through
`run_break_set`. So I missed that I had typed the column option `c` -
that's taken by `--command`.

This patch fixes that typo and adds a CLI test for file + line + column.