LLVM/project eec05ea — llvm/docs/CommandGuide llvm-readobj.md llvm-readelf.md

[llvm-readobj][docs] Update the --stack-sizes description

The description said that --stack-sizes is only implemented for GNU
style output, which hasn't been the case for a while. Describe the LLVM
and JSON output instead: each entry also identifies its function as
--call-graph-info does, by its address in a linked file, or by the
relocation that applies to it in a relocatable file.

Assisted-by: Gemini
DeltaFile
+4-2llvm/docs/CommandGuide/llvm-readobj.md
+4-2llvm/docs/CommandGuide/llvm-readelf.md
+8-42 files

LLVM/project b43c036 — libc/src/__support/OSUtil/linux/syscall_wrappers CMakeLists.txt sched_rr_get_interval.h, libc/src/sched/linux CMakeLists.txt sched_rr_get_interval.cpp

[libc] Use a syscall wrapper for `sched_rr_get_interval` (#232310)

This PR move `sched_rr_get_interval` behind the centralized syscall
wrappers, following `libc/docs/dev/syscall_wrapper_refactor.md`.
DeltaFile
+52-0libc/src/__support/OSUtil/linux/syscall_wrappers/sched_rr_get_interval.h
+32-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+4-19libc/src/sched/linux/sched_rr_get_interval.cpp
+14-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+4-2libc/src/sched/linux/CMakeLists.txt
+106-215 files

LLVM/project 05404ce — llvm/lib/Analysis ValueTracking.cpp, llvm/test/CodeGen/AArch64/GlobalISel knownfpclass-ops.mir

[ValueTracking] Check noundef before applying square (fmul_self) (#232178)

`computeKnownFPClass` for `ValueTracking.cpp` will now test
`isGuaranteedNotToBeUndef` before determining that `fmul %x, %x` is
squaring.

I also added a test for maybe-undef squaring for `computeKnownFPClass`
for `GISelValueTracking.cpp`

Resolves
https://github.com/llvm/llvm-project/pull/227248#discussion_r4207466257
DeltaFile
+15-0llvm/test/CodeGen/AArch64/GlobalISel/knownfpclass-ops.mir
+2-2llvm/lib/Analysis/ValueTracking.cpp
+1-1llvm/test/Transforms/Attributor/nofpclass-fmul.ll
+18-33 files

LLVM/project 6941494 —

[SCEVExpander] Simplify expanding AddRecs from the canonical IV (NFC). (#232287)

In canonical mode, visitAddRecExpr expands AddRecs with more than 2
operands literally, so all AddRecs handled afterwards are affine. Remove
the trivially true isAffine() checks and the unreachable expansion of
chains of recurrences via evaluateAtIteration.

When {0,+,F} is expanded from the canonical IV, the IV has the type of
the AddRec, so the truncate and extend are no-ops, and {0,+,1} needs no
special case, as the multiply by 1 folds away.

Also handle pointer AddRecs before splitting off the start, as the start
of a pointer AddRec is never zero, and build {0,+,F} directly from its
step, as S is affine.
DeltaFile
+0-00 files

LLVM/project e849295 — llvm/lib/Transforms/Utils ScalarEvolutionExpander.cpp

[SCEVExpander] Simplify expanding AddRecs from the canonical IV (NFC). (#232287)

In canonical mode, visitAddRecExpr expands AddRecs with more than 2
operands literally, so all AddRecs handled afterwards are affine. Remove
the trivially true isAffine() checks and the unreachable expansion of
chains of recurrences via evaluateAtIteration.

When {0,+,F} is expanded from the canonical IV, the IV has the type of
the AddRec, so the truncate and extend are no-ops, and {0,+,1} needs no
special case, as the multiply by 1 folds away.

Also handle pointer AddRecs before splitting off the start, as the start
of a pointer AddRec is never zero, and build {0,+,F} directly from its
step, as S is affine.
DeltaFile
+14-50llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
+14-501 files

LLVM/project 44a6d2f — flang/test/Semantics simple-ieee-arithmetic-functions.f90

[flang] Check SIMPLE on every IEEE_ARITHMETIC elemental function family (#231952)

Follow-up to #223254, test only.

`simple-ieee-arithmetic-functions.f90` checks that one specific,
`ieee_is_finite_a4`, is SIMPLE. The prefix is applied by 29 independent
`#define` macros in `flang-rt/lib/runtime/ieee_arithmetic.f90`, one per
elemental function family, so removing it from any other family passes
the test.

This references one specific per family and checks each with
`-fdebug-dump-symbols`, the same style as
`simple-ieee-arithmetic-operators.f90`. The CHECK lines follow the
dump's alphabetical order.

Assisted-by: AI
DeltaFile
+30-4flang/test/Semantics/simple-ieee-arithmetic-functions.f90
+30-41 files

LLVM/project 56abf41 — llvm/test/tools/llvm-readobj/ELF stack-sizes.test, llvm/tools/llvm-readobj ELFDumper.cpp

[llvm-readobj][ELF] Print the relocation of each --stack-sizes entry

In a relocatable file, print the relocation that applies to each
.stack_sizes entry as a Relocation object in the LLVM and JSON output,
with the same fields as in --call-graph-info. The code that prints the
object is shared with --call-graph-info.

As in --call-graph-info, clear the Thumb bit from the address that the
relocation resolves to on ARM, so that Thumb functions are found.

Assisted-by: Gemini
DeltaFile
+197-2llvm/test/tools/llvm-readobj/ELF/stack-sizes.test
+76-33llvm/tools/llvm-readobj/ELFDumper.cpp
+273-352 files

LLVM/project ca24671 — llvm/test/tools/llvm-readobj/ELF stack-sizes.test, llvm/tools/llvm-readobj ELFDumper.cpp

[llvm-readobj][ELF] Print the address of each --stack-sizes entry

In a linked file, print the function address that each .stack_sizes
entry holds as Address in the LLVM and JSON output. The entries can then
be matched with --call-graph-info output by address, without looking up
function names.

As --call-graph-info does, clear the Thumb bit from the address on ARM.
This also lets Thumb functions be found: they were reported as unknown,
with a warning.

Assisted-by: Gemini
DeltaFile
+70-2llvm/test/tools/llvm-readobj/ELF/stack-sizes.test
+23-9llvm/tools/llvm-readobj/ELFDumper.cpp
+93-112 files

LLVM/project 74b1c81 — llvm/test/Transforms/LoopVectorize/AArch64 sve-tail-folding.ll early_exit_with_stores_tail_folding.ll

[LV][NFC] Add SVE tests for uniform scatters with tail-folding (#232290)

Add SVE tests in preparation for

https://github.com/llvm/llvm-project/pull/172799
DeltaFile
+54-0llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores_tail_folding.ll
+42-0llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
+96-02 files

LLVM/project d375d07 — llvm/test/CodeGen/ARM/Windows trap-unreachable.ll, llvm/test/CodeGen/X86 windows-trap-unreachable.ll

ARM, X86: Test code after noreturn calls against the exception model

Add ARM and X86 versions of the AArch64 windows-trap-unreachable test
from #229681

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+24-0llvm/test/CodeGen/X86/windows-trap-unreachable.ll
+23-0llvm/test/CodeGen/ARM/Windows/trap-unreachable.ll
+47-02 files

LLVM/project b621a34 — offload/liboffload/API Memory.td, offload/liboffload/src OffloadImpl.cpp

[Offload][omp] Move is_accessible_ptr to liboffload (#231801)

Implement a new method in liboffload to access isAccessiblePtr method in
GenericDeviceTy and use it in libomptarget to substitute the direct call
to GenericPluginTy.

Assisted by Claude.
DeltaFile
+173-0offload/unittests/OffloadAPI/memory/olMemIsAccessible.cpp
+34-0offload/liboffload/src/OffloadImpl.cpp
+18-0offload/liboffload/API/Memory.td
+0-16offload/plugins-nextgen/common/src/PluginInterface.cpp
+14-0offload/plugins-nextgen/common/include/OffloadError.h
+2-8offload/plugins-nextgen/level_zero/src/L0Queue.cpp
+241-244 files not shown
+256-2910 files

LLVM/project 07bfb20 — llvm/test/CodeGen/AMDGPU vgpr-large-tuple-alloc-error.ll

AMDGPU: Keep argument live in vgpr-large-tuple-alloc-error.ll (#232308)

The register pressure in this test comes from exporting the argument
to virtual registers. The export is only needed when the argument is
used outside the entry block, so use it in a second block. This avoids
breaking the test in a future patch which avoids emitting the
unnecessary copies.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+7-0llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
+7-01 files

LLVM/project 478116c — llvm/test/tools/llvm-readobj/ELF call-graph-info.test call-graph-info-warn-malformed.test, llvm/tools/llvm-readobj ELFDumper.cpp

[llvm-readobj][ELF] Print Names for call graph relocations (#230654)

In a relocatable object file, an entry identified by a relocation had no
Names. Compute the address that the relocation resolves to with
RelocationResolver, look up the functions at that address in the section
of the relocation's symbol, and print them as Names before the
Relocation object.

As with Names for an Address, the names follow --demangle. Nothing is
printed for an undefined symbol, or when no function is at the address.
A relocation type that RelocationResolver doesn't support, or a symbol
whose section can't be found, gets a warning.

Assisted-by: Gemini
DeltaFile
+60-3llvm/tools/llvm-readobj/ELFDumper.cpp
+52-0llvm/test/tools/llvm-readobj/ELF/call-graph-info-warn-malformed.test
+26-8llvm/test/tools/llvm-readobj/ELF/call-graph-info.test
+138-113 files

LLVM/project f23308b — llvm/test/tools/llvm-readobj/ELF call-graph-info-warn-malformed.test, llvm/tools/llvm-readobj ELFDumper.cpp

[llvm-readobj][ELF] Fall back to Address when no single relocation applies (#230653)

In a relocatable object file, --call-graph-info identifies a function by
the relocation that applies to its address field. If a field had no
relocation, nothing in the output identified the function. If the
relocation section had an invalid sh_link, the dump stopped. If a field
had more than one relocation, the first one was used silently.

In all of these cases, print the value stored in the field as Address,
as for linked files. Warn once if a call graph section has no relocation
section, and warn about each field with no relocation or more than one.
If the relocations can't be read, only that is reported.

Assisted-by: Gemini
DeltaFile
+146-11llvm/test/tools/llvm-readobj/ELF/call-graph-info-warn-malformed.test
+70-48llvm/tools/llvm-readobj/ELFDumper.cpp
+216-592 files

LLVM/project 7ca8916 — llvm/test/tools/llvm-readobj/ELF call-graph-info.test, llvm/tools/llvm-readobj ELFDumper.cpp

[llvm-readobj][ELF] Print implicit addends of call graph relocations (#230652)

A SHT_REL relocation, or a SHT_CREL relocation without explicit addends,
keeps its addend in the field that it applies to. Print the
sign-extended field value as the Addend of such a relocation instead of
dropping it. The ARM test now uses SHT_REL and covers the same cases as
the SHT_RELA tests: named symbols, a negative addend, and a section
symbol with an addend.

Assisted-by: Gemini
DeltaFile
+41-13llvm/test/tools/llvm-readobj/ELF/call-graph-info.test
+5-1llvm/tools/llvm-readobj/ELFDumper.cpp
+46-142 files

LLVM/project e636999 — llvm/test/tools/llvm-readobj/ELF call-graph-info-warn-malformed.test call-graph-info.test, llvm/tools/llvm-readobj ELFDumper.cpp

[llvm-readobj][ELF] Print a Relocation object instead of Name in --call-graph-info (#230651)

In a relocatable file, the address fields of a call graph section hold
placeholders, and the relocation that applies to each field identifies
the function. Name showed only the relocation's symbol name, made up
from the section name for an unnamed section symbol, and dropped the
addend. So entries that refer to a function through a section symbol
couldn't be told apart.

Print a Relocation object instead, with the symbol index, the symbol
name exactly as recorded in st_name, and the addend if it is non-zero.
With --demangle, the demangled symbol name is printed as DemangledName.
If the symbol can't be read, the existing warning is reported and only
the symbol index is printed.

Assisted-by: Gemini
DeltaFile
+204-22llvm/test/tools/llvm-readobj/ELF/call-graph-info.test
+35-7llvm/tools/llvm-readobj/ELFDumper.cpp
+14-1llvm/test/tools/llvm-readobj/ELF/call-graph-info-warn-malformed.test
+253-303 files

LLVM/project 41e9cdb — llvm/test/TableGen getRegClassFromMatchKind.td RegisterClassCopyCost.td, llvm/utils/TableGen RegisterInfoEmitter.cpp

Revert "[TableGen] Declare `MCRegisterClassStorageType` as `constexpr` (NFC)" (#232303)

This has caused the buildbot to fail:
https://lab.llvm.org/buildbot/#/builders/46/builds/42846.

Reverts llvm/llvm-project#232010
DeltaFile
+1-1llvm/utils/TableGen/RegisterInfoEmitter.cpp
+1-1llvm/test/TableGen/getRegClassFromMatchKind.td
+1-1llvm/test/TableGen/RegisterClassCopyCost.td
+3-33 files

LLVM/project d7e800d — llvm/test/DebugInfo/MIR/Hexagon live-debug-values-bundled-entry-values.mir, llvm/test/DebugInfo/MIR/InstrRef out-of-scope-blocks.mir

DebugInfo: Fix contradictory dead flags in MIR tests

Remove the duplicate implicit-def dead $pc from Hexagon L4_return, and
drop the dead flag from sub-register defs that also have a live
super-register implicit-def. These will fail a future verifier rule.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+4-4llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
+1-1llvm/test/DebugInfo/X86/dwarf-gnu-call-target-clobbered.mir
+1-1llvm/test/DebugInfo/MIR/X86/live-debug-values.mir
+1-1llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir
+1-1llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir
+1-1llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
+9-92 files not shown
+11-118 files

LLVM/project abcc2e6 — mlir/lib/Dialect/Tosa/IR TosaOps.cpp

[mlir][tosa] Remove unnecessary conv verifier checks (#231825)

The `verifyConvOpModes` function wasn't verifying anything. Likely this
was left behind when the verifier was relaxed to stop checking
accumulation type alignment with input/output types. This commit removes
the unnecessary function call.
DeltaFile
+4-24mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+4-241 files

LLVM/project 47c7786 — lld/docs/MachO index.md

[lld][docs] Corrected deprecated usage of `fuse-ld` (#231507)

Using full paths with `fuse-ld` has been deprecated in Clang 12. It
should use `ld-path` in combination with `fuse-ld`.
DeltaFile
+1-1lld/docs/MachO/index.md
+1-11 files

LLVM/project 6ae56ea — libc/src/__support/OSUtil/linux/syscall_wrappers execveat.h, libc/src/unistd fexecve.h

[libc] Implement fexecve in unistd (#231230)

Implement the POSIX function `fexecve` in `<unistd.h>`.

Fixes #231206

Assisted by Antigravity and reviewed by Aman Maurya.
DeltaFile
+71-0libc/test/integration/src/unistd/fexecve_test.cpp
+37-0libc/src/unistd/linux/fexecve.cpp
+35-0libc/src/__support/OSUtil/linux/syscall_wrappers/execveat.h
+27-0libc/test/src/unistd/fexecve_test.cpp
+25-0libc/src/unistd/fexecve.h
+22-0libc/test/integration/src/unistd/CMakeLists.txt
+217-09 files not shown
+276-015 files

LLVM/project ba09a49 — libc/include/llvm-libc-types struct_ifreq.h, libc/include/llvm-libc-types/linux CMakeLists.txt struct_ifmap.h

[libc] Make struct ifreq compatible with linux/if.h (#225793)

When <linux/if.h> is included after <net/if.h>, compilation fails for
several reasons:
- <linux/libc-compat.h> expects libc to coordinate using the
  __UAPI_DEF_IF_IFREQ and __UAPI_DEF_IF_IFMAP macros. Because we didn't
  define them, the kernel headers fell back to defining them as 1, which
  caused <linux/if.h> to redefine struct ifreq.
- <linux/if.h> defines field access macros (ifr_name, ifr_addr, etc.)
  pointing to members of named ifr_ifrn and ifr_ifru unions. Our struct
  ifreq used an anonymous union, so those defines broke member access.
- Our struct ifreq omitted the `struct ifmap ifru_map` member. Besides
  breaking the ifr_map macro from <linux/if.h>, this also made
  sizeof(struct ifreq) 32 bytes instead of 40 on 64-bit Linux (as
  struct ifmap is 24 bytes while all other union members are at most 16
  bytes), mismatching the kernel ioctl ABI.
To fix this:
- define `struct ifmap` and add it to `struct ifreq`
- define `__UAPI_DEF_IF_IFMAP 0` and `__UAPI_DEF_IF_IFREQ 0` to prevent

    [16 lines not shown]
DeltaFile
+62-0libc/include/llvm-libc-types/linux/struct_ifreq.h
+37-0libc/test/include/net/linux/net_if_and_linux_if_test.cpp
+29-0libc/include/llvm-libc-types/linux/struct_ifmap.h
+3-22libc/include/llvm-libc-types/struct_ifreq.h
+20-0libc/test/include/net/linux/linux_if_helper.cpp
+16-0libc/include/llvm-libc-types/linux/CMakeLists.txt
+167-224 files not shown
+191-2510 files

LLVM/project 0b8a284 — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64-big-endian-vector-zext.ll

[AArch64] Use NVCAST instead of BITCAST in LowerZERO_EXTEND_VECTOR_INREG (#232160)

Under big endian BITCAST materializes as a REV, corrupting the lane
arrangement of zip1(x, 0).

Fix #232154
DeltaFile
+37-0llvm/test/CodeGen/AArch64/arm64-big-endian-vector-zext.ll
+2-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+39-22 files

LLVM/project 4368245 — .github/workflows libcxx-run-benchmarks.yml libcxx-pr-benchmark.yml

[libc++] Produce output when running benchmark jobs (#232306)

This makes the jobs more debuggable. In addition, add a keepalive
background process that keeps producing output even while a benchmark is
running, as a workaround for #226230, which causes jobs running on K8s
to be killed if they have not produced output for more than 5 minutes.
DeltaFile
+7-2.github/workflows/libcxx-pr-benchmark.yml
+6-0.github/workflows/libcxx-run-benchmarks.yml
+13-22 files

LLVM/project a6dd402 — libc/src/__support/OSUtil/linux/syscall_wrappers CMakeLists.txt sched_rr_get_interval.h, libc/src/sched/linux CMakeLists.txt sched_rr_get_interval.cpp

[libc] Use a syscall wrapper for sched_rr_get_interval
DeltaFile
+52-0libc/src/__support/OSUtil/linux/syscall_wrappers/sched_rr_get_interval.h
+32-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+4-19libc/src/sched/linux/sched_rr_get_interval.cpp
+14-0libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+4-2libc/src/sched/linux/CMakeLists.txt
+106-215 files

LLVM/project 87ea512 — llvm/test/CodeGen/AMDGPU extract_vector_dynelt.ll, llvm/test/CodeGen/NVPTX i32x2-instructions.ll f32x2-instructions.ll

DAG: Don't export arguments for FastISel if it won't be used

LowerArguments decided whether to export arguments to virtual
registers based on TM.Options.EnableFastISel. That option is set at
-O0 even for targets that have no FastISel implementation. This is
unnecessary without fast isel, so stop doing that.

The unneeded CopyToReg was an extra use of every argument, which
blocked some combines. The dead copies also survived to register
allocation. These copies were an edge case that regallocfast would
introduce dead flags on.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+725-1,475llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
+704-890llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
+522-621llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+309-438llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
+303-418llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
+336-352llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+2,899-4,19436 files not shown
+3,965-5,74042 files

LLVM/project d225e5e — llvm/test/CodeGen/AMDGPU vgpr-large-tuple-alloc-error.ll

AMDGPU: Keep argument live in vgpr-large-tuple-alloc-error.ll

The register pressure in this test comes from exporting the argument
to virtual registers. The export is only needed when the argument is
used outside the entry block, so use it in a second block. This avoids
breaking the test in a future patch which avoids emitting the
unnecessary copies.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+7-0llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
+7-01 files

LLVM/project c331608 — llvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Analysis/ScalarEvolution exit-count-greater-than.ll trip-multiple-guard-info.ll

[SCEV] Use loop guards to rule out IV overflow in LT/GT exit counts. (#228691)

In some cases, loop guards can provide tighter bounds on RHS, which
allows ruling out overflow in more cases.

This enables additional vectorization, unrolling, IndVarSimplify and a
few more folds:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1539

Compile-time impact in the noise:

https://llvm-compile-time-tracker.com/compare.php?from=c0359c6d8bd87f3a0f1823a800304c0e7fe6efa1&to=e4b344c980ea293e3ec189801a5dffbe5e44b663&stat=instructions:u

Depends on https://github.com/llvm/llvm-project/pull/228687

PR: https://github.com/llvm/llvm-project/pull/228691
DeltaFile
+442-0llvm/test/Analysis/ScalarEvolution/trip-count-lt-overflow-from-guard.ll
+10-10llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
+7-6llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll
+2-2llvm/test/Analysis/ScalarEvolution/exit-count-greater-than.ll
+3-1llvm/lib/Analysis/ScalarEvolution.cpp
+464-195 files

LLVM/project a9e852d — llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp, llvm/test/CodeGen/AMDGPU noclobber-barrier.ll

[AMDGPU] Preserve noclobber after acquire operations from a different addrspace

Follow-up to #219991 to address reviewer comments:
AMDGPUAnnotateUniformValues should annotate uniform global loads as
`!amdgpu.noclobber` if the memory they are reading is never clobbered (since
kernel launch) before the load is executed.
PR #219991 strengthened the logic to consider acquire operations before the
load as clobbering (because they cause stores from other threads to be observed
by the load without a data race).

This PR weakens this criterion to ignore acquire operations that don't affect
the global address space (because they don't affect what the load in question
may or may not see). This addresses the performance-relevant case of s_barriers
with LDS-only fences.

The logic is still overly pessimistic for one-as load acquires, they could also
be ignored when looking for clobbering operations.

Disclaimer: Claude gave review comments and suggestions that I addressed during

    [5 lines not shown]
DeltaFile
+16-13llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+12-2llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+28-152 files

LLVM/project a15de64 — llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp, llvm/test/CodeGen/AMDGPU implicit-kernarg-backend-usage.ll memory-legalizer-invalid-addrspace.mir

Put the toSIAtomicAddrSpace logic into a table and make it consistent with isExtendedGlobalAddrSpace

With that, the change is no longer NFC, since constant addrspaces and
addrspaces above `MAX_AMDGPU_ADDRESS` now map to `SIAtomicAddrSpace::GLOBAL`
instead of `OTHER`. This means that atomics on these addrspaces are no longer
rejected by SIMemoryLegalizer.

The tests only show differences in the generated ISA for volatile loads from
the constant addrspaces; so far we haven't waited directly after each such
volatile load, with this change we do. Arguably, these waits are unnecessary
since the accessed memory is not supposed to change, but, on the other hand,
one could argue that volatile accesses to memory that doesn't change are
pointless in the first place.
DeltaFile
+0-69llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
+20-17llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+8-14llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
+14-8llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
+12-8llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
+5-8llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
+59-1244 files not shown
+72-13010 files