RegisterCoalescer: Restore subrange PHI inputs of pruned undef values
When joining erases an IMPLICIT_DEF or a copy, the liveness of undefined
lanes may have started at that instruction, so pruneSubRegValues removes
those subrange values. If such a value was live-out into a subrange PHI,
the PHI is left without an input from that predecessor, even though
after the join the lane value from the earlier def of the joined
register reaches it. The main range does not have this gap because
pruneValues collects the pruned end points and joinVirtRegs restores
them with extendToIndices.
Record the PHI kills of the pruned value, the predecessor block ends
where it is live-out into a PHI as in LiveIntervals::hasPHIKill, and
restore them with extendToIndices once operands are rewritten, together
with the existing subrange shrinking. The rewrite is needed so
computeSubRangeUndefs sees the defs of both registers. Only PHI kills are
restored; the in-block kills of a pruned value are reads of an undef
lane and get undef flags instead.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[clang] Don't add built-in operator candidates that can't be viable (#227584)
If an operand of an operator has (or converts to) an arithmetic or
enumeration type, AddBuiltinOperatorCandidates() adds a built-in
candidate for every pair of promoted arithmetic types, and each
candidate tries to convert both operands. That's 121 candidates for `a
== b` on arm64 macOS.
If an operand can't convert to any of these types, none of these
candidates are viable (e.g. `e == E::kFoo` for a scoped enumeration E).
So conservatively track if each operand can convert to an arithmetic
type, and only add these candidates if all operands can convert.
Non-viable built-in candidates aren't used for anything and are safe to
not add.
For 60 random Chromium TUs (linux x64, -O2) picked with probability
proportional to their compile time, sum over all TUs:
CPU time: 186.6 s => 183.3 s, -1.81%
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[lldb] Add StringPool and per-debugger and system pool handles (NFC) (#228611)
Move the ConstString pool into a StringPool class and add a non-owning
StringPoolRef handle. This is in preparation for having one global and
multiple per-Debugger ConstString pool. Strings at the SB API layer will
be interned into the appropriate pool. As long as these remain
references, this operation is a NOOP.
[SPIRV] Splat scalar condition for vector OpSelect prior to SPIR-V 1.4 (#229267)
Before SPIR-V 1.4, the Condition operand of an OpSelect instruction with
a vector Result Type must be a vector of Booleans with the same number
of components as the result vector. LLVM IR allows a scalar i1 condition
when selecting between vectors, which causes spirv-val to reject the
module on SPIR-V 1.0 through 1.3 targets.
When targeting SPIR-V versions below 1.4, splat a scalar boolean
condition into a matching boolean vector via OpCompositeConstruct before
emitting OpSelect.
[NewPM] Properly initialize NewPM reg-bank-select (#229534)
The NewPM initialization of the pass didn't call computeOptMode as the
legacy one does. Missed in porting:
https://github.com/llvm/llvm-project/pull/217756
[clang] Fix handling of invalid nonnull attribute arguments (#229519)
The nonnull attribute accepts a variadic list of indexes to function
pointer parameters, specifying which ones are not allowed to take a null
value. If an index is invalid (e.g. the referenced function parameter is
not a pointer), then the index is dropped from the semantic attribute
retained in the AST.
Previously, if all the specified indicies were invalid, Clang would
associate a semantic nonnull attribute with no arguments on the
FunctionDecl, which would cause all pointer arguments to be treated as
nonnull. Now, if there are no valid indicies specified, the attribute is
dropped entirely and so no pointer arguments are treated as nonnull.
Fixes #228670
[mlir] Migrate AMDGPU/ROCDL to targets, not chipset versions
**migration tl;dr:** Replace usages of `amdgpu::Chipset` with `ROCDL::TargetInfo`, ideally move from `chipset=` to `arch=`. If you don't use upstream pipelines, call 'TargetInfo::migrateArchFeaturesToModuleFlags` at the appropriate location.
Further note: if you've got a build pipeline that's getting a `gfxXXX` name from something like `rocm_agent_enumerator`, using a full triple name like the ones you get from `rocminfo` is preferred.
`amdgpu::Chipset` was an awkward hack that was hard to keep up to date
with changes in the compiler/new architectures, and didn't properly
support generic targets (and has been strongly disfavored by the
compiler team).
This PR replaces `amdgpu::Chipset` with `ROCDL::TargetInfo`, a
structure that uses LLVM's TargetParser and the underlying LLVM
features tables to get the real nature of the target being compiled
for.
This also helps MLIR move to
new-style (`-mtriple=amdgpuX.YZ-amd-amdhsa`) over "old
style" (`-mtriple=amdgcn-amd-amdhsa -mcpu=gfxXYZ`) triples.
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AMDGPU: Select region address space loads and stores (#229500)
Fix the annoying asymmetry where we handle local and region for some
atomics but not the full suite of operations. I run into this about once per
year and want to be done with it.
The ugly bits here are to deal with the fact that it appears m0 still requires
initialization in gfx9+. It was simpler to handle the true16 case by
preprocessing the selection to a 32-bit extload as the load truly is, and go
through the ordinary m0 gluing.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[flang][OpenMP] Switch clause verification to descriptor-based
Delete all the scattered pieces of clause verification that are now
replaced by the unified handling.
[flang][OpenMP] Improve diagnostics about modifier properties
Use OpenMPDeprecated and OpenMPFuture warning categories for modifier
diagnostics as well, analogously to how they are used for clauses.
AMDGPU/GlobalISel: Use integer types when narrowing loads and stores
The narrowScalar mutation for loads and stores produced untyped scalars.
For FP-typed values this resulted in an untyped G_OR in the lowerLoad
expansion for unaligned private accesses, which failed to select.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[flang][Semantics] Enforce F2023 C1545 only for generic references
F2023 C1545 requires the consequent-args of a conditional argument to
agree on corank and on the ALLOCATABLE and POINTER attributes, but only
in a reference to a generic procedure. Flang applied the constraint to
every reference containing a conditional argument and rejected conforming
code.
Move the cross-consequent checks out of CheckConditionalArg() and run
them from CheckAndResolveGenericReference(), before ResolveGeneric()
and only when the reference is generic. C1545 is a constraint, not one
of the generic resolution rules in F2023 15.5.5, so check it separately
from candidate matching.
When C1545 fails, return a GenericResolution with errorReported set
without calling ResolveGeneric(). The callers stop analyzing the
reference without additional generic-resolution diagnostics.
GetCalleeAndArguments() also returns before fallback intrinsic probing.
The parse-tree symbol stays generic, so a second analysis of the
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AMDGPU: Fix SILoadStoreOptimizer dropping gds bit on DS merges (#229520)
When forming read2/write2 from a pair of DS_READ/DS_WRITE
instructions, the gds operand was unconditionally set to 0, turning
GDS accesses into LDS accesses. Preserve the gds bit, refuse to pair
an LDS access with a GDS access, and select the M0-reading opcode
variant for GDS on targets that otherwise use the _gfx9 forms.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
GlobalISel: Use integer types when splitting loads in lowerLoad
lowerLoad built the split pieces using the destination type with the
element size changed, which preserved floating-point types. An
unaligned f64 load was decomposed into G_ZEXTLOAD, G_SHL and G_OR on
f32 and f64, which then crashed in AMDGPU RegBankLegalize. Build the
pieces as integers and bitcast to a non-integer result type, as
lowerStore already does.
The pieces are now consistently integer typed, which allows more
constants to be CSEd in the existing tests.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[libc++] Pass -fsized-deallocation to the sized_delete tests on AppleClang 23 (#229257)
AppleClang 23 still defaults to -fno-sized-deallocation, so explicitly
pass -fsized-deallocation in the tests that require it.
[AMDGPU] Extract byte lanes of a split vector from the 32-bit source
After a <4 x i8> is split into i16 halves, a byte lane is extended
from an i16 shift of a truncate. Rewrite it on the 32-bit source as an
and of srl or a sign_extend_inreg of srl, which select to a single bit
field extract.
Uniform zero and any extends are left alone, their i16 shift is already
promoted to i32.
