LLVM/project ef0b5eclibc/utils/hdrgen/tests/expected_output test_small_proxy.h

Update test_small_proxy.h
DeltaFile
+1-0libc/utils/hdrgen/tests/expected_output/test_small_proxy.h
+1-01 files

LLVM/project c5aefc7flang/include/flang/Support Fortran-features.h, flang/lib/Semantics definable.cpp definable.h

[flang] Downgrade an overly strict error to a warning (#187524)

Fortran allows a PURE subroutine to have dummy argument with INTENT(IN
OUT). An actual argument that is associated with an INTENT(IN OUT) dummy
argument must be definable. Consequently, there's a hole in the language
that allows a PURE subroutine to modify arbitrary global state: the
argument could have a derived type with an impure FINAL subroutine, and
that FINAL subroutine could be invoked by an assignment to the dummy
argument. I consider this to be a mistake in the language design.

So the compiler was reporting this case as an error, although it is
indeed conforming usage, and not flagged by any other compiler.
Unfortunately, somebody has a code that needs this usage to be accepted,
because (I presume) they can't modify the dummy argument to be
INTENT(IN).

Consequently, we'll need to allow this usage. But it will elicit a
warning, and the warning is on by default.
DeltaFile
+29-0flang/test/Semantics/bug181353.f90
+13-2flang/lib/Semantics/definable.cpp
+2-1flang/lib/Semantics/definable.h
+1-1flang/include/flang/Support/Fortran-features.h
+1-0flang/lib/Semantics/check-call.cpp
+1-0flang/lib/Support/Fortran-features.cpp
+47-46 files

LLVM/project 1017991llvm/lib/Target/X86 X86.h X86CodeGenPassBuilder.cpp, llvm/lib/Target/X86/GISel X86PostLegalizerCombiner.cpp

[X86][GISEL] Port X86PostLegalizerCombiner to npm (#182787)

Port X86PostLegalizerCombiner to npm as part of llvm/llvm-project#178192

Also added cli option for lpm X86PostLegalizerCombiner pass for testing.
DeltaFile
+66-29llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
+9-2llvm/lib/Target/X86/X86.h
+5-0llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+2-2llvm/lib/Target/X86/X86TargetMachine.cpp
+1-0llvm/lib/Target/X86/X86PassRegistry.def
+83-335 files

LLVM/project ea782f5libclc/clc/lib/generic/math clc_tanpi.inc clc_cospi.inc

libclc: Update trigpi functions

These were originally ported from rocm device
libs in bc81ebefb7d9d9d71d20bfee2ce4cccb09701e9b.
Merge in more recent changes.
DeltaFile
+62-105libclc/clc/lib/generic/math/clc_tanpi.inc
+3-106libclc/clc/lib/generic/math/clc_cospi.inc
+2-104libclc/clc/lib/generic/math/clc_sinpi.inc
+23-62libclc/clc/lib/generic/math/clc_sincos_helpers_fp64.inc
+50-0libclc/clc/lib/generic/math/clc_sincospi.inc
+27-0libclc/clc/lib/generic/math/clc_sincos_helpers.inc
+167-37715 files not shown
+308-39821 files

LLVM/project d397027llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp, llvm/test/CodeGen/AMDGPU vgpr-setreg-mode-swar.mir

[AMDGPU] Fix decoding of SETREG MSBs

Decoding of the immediate was wrong with non-zero offset
and did not factor MSB fixup offset handling.
DeltaFile
+40-0llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
+5-2llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+45-22 files

LLVM/project e8b5a0bllvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp

fixup! Add overloaded AArch64DAGToDAGISel::EmitMultiVectorLutiLane() for reuse
DeltaFile
+39-50llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+39-501 files

LLVM/project c07e04ellvm/include/llvm-c Core.h, llvm/lib/IR Core.cpp

[spr] initial version

Created using spr 1.3.8-wip
DeltaFile
+6-3llvm/include/llvm-c/Core.h
+6-3llvm/lib/IR/Core.cpp
+12-62 files

LLVM/project 11b439cllvm/lib/LTO LTO.cpp, llvm/tools/llvm-lto2 llvm-lto2.cpp

[DTLTO] Speed up temporary file removal in the ThinLTO backend (#186988)

Deleting the temporary files produced by the DTLTO ThinLTO backend can
be expensive on Windows hosts. For a Clang link (Debug build with
sanitizers and instrumentation) using an optimized toolchain (PGO
non-LTO, llvmorg-22.1.0) on a Windows 11 Pro (Build 26200), AMD Family
25 @ ~4.5 GHz, 16 cores / 32 threads, 64 GB RAM machine, the mean
duration of the "Remove DTLTO temporary files" time trace scope was
1267.789 ms (measured over 10 runs).

This patch performs the deletions on a background thread, allowing them
to overlap with the remainder of the link to hide this cost.

Based on work by @romanova-ekaterina and @kbelochapka.
DeltaFile
+49-7llvm/lib/LTO/LTO.cpp
+6-1llvm/tools/llvm-lto2/llvm-lto2.cpp
+55-82 files

LLVM/project 9ae3077clang/include/clang/Basic Module.h, clang/lib/Frontend CompilerInstance.cpp

[clang][modules] Remove `Module::ASTFile` (#185994)

This removes the assumption that a deserialized module is backed by a
`FileEntry`. The `OptionalFileEntryRef` member is replaced with
`ModuleFile{Name,Key}`.
DeltaFile
+21-9clang/include/clang/Basic/Module.h
+9-8clang/lib/Serialization/ASTReader.cpp
+4-6clang/lib/Frontend/CompilerInstance.cpp
+2-7clang/tools/c-index-test/c-index-test.c
+3-5clang/lib/Serialization/ModuleManager.cpp
+1-6clang/tools/libclang/CIndex.cpp
+40-4112 files not shown
+62-5518 files

LLVM/project 633d1fallvm/lib/Support raw_socket_stream.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+3-1llvm/lib/Support/raw_socket_stream.cpp
+3-11 files

LLVM/project 662c12dllvm/lib/CodeGen CodeGenPrepare.cpp, llvm/test/Transforms/CodeGenPrepare/AArch64 ptrauth.ll

[CGP][PAC] Flip PHI and blends when all immediate modifiers are the same

GVN PRE, SimplifyCFG and possibly other passes may hoist the call to
`@llvm.ptrauth.blend` intrinsic, introducing multiple duplicate call
instructions hidden behind a PHI node. This prevents the instruction
selector from generating safer code by absorbing the address and
immediate modifiers into separate operands of AUT, PAC, etc. pseudo
instruction.

This patch makes CodeGenPrepare pass detect when discriminator is
computed as a PHI node with all incoming values being blends with the
same immediate modifier. Each such discriminator value is replaced by a
single blend, whose address argument is computed by a PHI node.
DeltaFile
+142-0llvm/test/Transforms/CodeGenPrepare/AArch64/ptrauth.ll
+75-0llvm/lib/CodeGen/CodeGenPrepare.cpp
+217-02 files

LLVM/project 1edc6ccllvm/lib/Target/AMDGPU AMDGPULowerVGPREncoding.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[AMDGPU] Fix setreg handling in the VGPR MSB lowering

There are multiple issues with it:

1. It can skip inserting S_SET_VGPR_MSB if we set the mode via
   piggybacking. We are now relying on the HW bug for correct
   behavior. If/when the bug is fixed lowering will be incorrect.
2. We should just unconditionally update MSBs if immediate allows it.
   We shall set correct bits and keep the rest of the immediate
   (that is done). There is no reasonable way for an user to change
   MSBs nor does it do anything good to set it with SETREG and then
   immediately overwrite with S_SET_VGPR_MSB.
3. We can always update immediate if Offset is zero.
4. Redundant mode changes created as seen in the
   hazard-setreg-vgpr-msb-gfx1250.mir.
5. Decoding of the immediate was also wrong with non-zero offset
   and did not factor MSB fixup offset handling.

With unconditional immediate update most of time and not relying on

    [12 lines not shown]
DeltaFile
+126-33llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
+30-38llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+12-18llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir
+5-2llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+173-914 files

LLVM/project 15fee18llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64InstrInfo.td, llvm/lib/Target/AArch64/GISel AArch64CallLowering.cpp

[AArch64][PAC] Rework discriminator analysis for calls and tail calls

Make use of fixupBlendComponents for AUTH_TCRETURN[_BTI] and for
BLRA[_RVMARKER] pseudos the same way it is done for AUT/PAC/AUTPAC.

This patch unifies discriminator analysis for DAGISel and GlobalISel
and improves cross-BB analysis in case of DAGISel.
DeltaFile
+24-41llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+23-16llvm/test/CodeGen/AArch64/ptrauth-isel.ll
+6-18llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+4-8llvm/test/CodeGen/AArch64/deactivation-symbols.ll
+3-1llvm/lib/Target/AArch64/AArch64InstrInfo.td
+2-2llvm/test/CodeGen/AArch64/ptrauth-call.ll
+62-866 files

LLVM/project 2b91043flang/lib/Semantics openmp-utils.cpp

format
DeltaFile
+4-4flang/lib/Semantics/openmp-utils.cpp
+4-41 files

LLVM/project 2632ffelibc/src/stdio/linux stderr.cpp stdin.cpp

[libc][stdio] Fix standard streams in overlay mode. (#187522)

https://github.com/llvm/llvm-project/pull/184669 changed the behavior of
standard streams in overlay mode, bringing in some symbols that are only
available in full build mode.
DeltaFile
+9-0libc/src/stdio/linux/stderr.cpp
+9-0libc/src/stdio/linux/stdin.cpp
+9-0libc/src/stdio/linux/stdout.cpp
+27-03 files

LLVM/project 44d44c1clang/lib/Basic/Targets AArch64.cpp, clang/test/Preprocessor aarch64-target-features.c

fixup! Address PR comments
DeltaFile
+18-12llvm/lib/Target/AArch64/SVEInstrFormats.td
+0-29clang/lib/Basic/Targets/AArch64.cpp
+0-23clang/test/Preprocessor/aarch64-target-features.c
+13-9llvm/lib/Target/AArch64/SMEInstrFormats.td
+1-6llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+1-4llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+33-831 files not shown
+33-857 files

LLVM/project f307d6dllvm/lib/Target/AArch64 AArch64ISelDAGToDAG.cpp

fixup! Reuse SelectMultiVectorLuti()
DeltaFile
+6-36llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+6-361 files

LLVM/project be6c329clang/test/CodeGen/AArch64/sme2p3-intrinsics acle_sme2p3_luti6.c, clang/test/CodeGen/AArch64/sve2p3-intrinsics acle_sve2p3_luti6.c

[AArch64][clang][llvm] Add support for Armv9.7-A lookup table intrinsics

Add support for the following Armv9.7-A Lookup Table (lut)
instruction intrinsics:

SVE2.3
```c
  // Variant is  also available for: _u8 _mf8
  svint8_t svluti6[_s8](svint8x2_t table, svuint8_t indices);
```

SVE2.3 and SME2.3
``` c
  // Variants are also available for _u16_x2 and _f16_x2.
  svint16_t svluti6_lane[_s16_x2](svint16x2_t table, svuint8_t indices, uint64_t imm_idx);
```

SME2.3
```c

    [9 lines not shown]
DeltaFile
+175-0clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
+112-0clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
+105-0llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
+102-0llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+79-0llvm/test/Verifier/AArch64/luti6-intrinsics.ll
+55-0llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
+628-016 files not shown
+876-322 files

LLVM/project a7d2d8alibclc/clc/lib/generic/math clc_flush_if_daz.inc clc_flush_if_daz.cl

libclc: Replace flush_if_daz implementation

The fallback non-canonicalize path didn't work. Use a more
straightforward implementation. Eventually this should use
the pattern from #172998
DeltaFile
+3-7libclc/clc/lib/generic/math/clc_flush_if_daz.inc
+4-0libclc/clc/lib/generic/math/clc_flush_if_daz.cl
+7-72 files

LLVM/project adbb122libc/include wctype.yaml, libc/src/wctype iswprint.cpp iswprint.h

[libc] Implement iswprint entrypoint (#185251)

Implemented the iswprint entrypoint and tests for issue #185136
DeltaFile
+21-0libc/src/wctype/iswprint.cpp
+21-0libc/src/wctype/iswprint.h
+21-0libc/test/src/wctype/iswprint_test.cpp
+12-1libc/src/wctype/CMakeLists.txt
+10-0libc/test/src/wctype/CMakeLists.txt
+6-0libc/include/wctype.yaml
+91-18 files not shown
+99-114 files

LLVM/project 8e1e371llvm/docs ReleaseNotes.md, llvm/include/llvm/Analysis IRSimilarityIdentifier.h

[IR][NFC] Mark BranchInst as deprecated (#187314)

All in-tree uses of BranchInst are eliminated, so mark as deprecated as
per the RFC.

https://discourse.llvm.org/t/rfc-split-branchinst-into-uncondbr-and-condbr/90022
DeltaFile
+15-1llvm/include/llvm/IR/Instructions.h
+6-1llvm/include/llvm/Analysis/IRSimilarityIdentifier.h
+4-0llvm/unittests/IR/InstructionsTest.cpp
+4-0llvm/include/llvm/IR/InstVisitor.h
+3-0llvm/lib/IR/Core.cpp
+2-0llvm/docs/ReleaseNotes.md
+34-26 files

LLVM/project ae6fbd0mlir/lib/Dialect/Linalg/Transforms Vectorization.cpp, mlir/test/Dialect/Linalg/vectorization extract-with-patterns.mlir

[mlir][linalg] Fix vectorizer generating invalid vector.gather for 0-D tensor.extract (#187085)

Vectorizing a rank-0 `linalg.generic` whose body contains
`tensor.extract` with data-dependent indices hits the Gather
classification in `getTensorExtractMemoryAccessPattern` because
`isOutput1DVector` returns false for a 0-D result. This produces an
invalid `vector.gather` where operand #2 must be a vector of index
values but gets a scalar `index` instead.

Fix classifies a 0-D result as ScalarBroadcast rather than Gather, and
skips mask generation for 0-D in that path.
DeltaFile
+36-0mlir/test/Dialect/Linalg/vectorization/extract-with-patterns.mlir
+18-10mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
+54-102 files

LLVM/project 0492bf9flang/lib/Lower/OpenMP ClauseProcessor.cpp, flang/test/Lower/OpenMP linear_modifier.f90 declare-simd.f90

Add OpenMP version guard for linear modifier

- Add OpenMP 5.2 version guard for linear modifier to make sure
we don't set val for OpenMP 4.5 and 5.0 which support explicit
linear modifier
- Update test to revert changes in version < 5.2
- Update declare simd test (add declare_simd for 6.0)
- Refactor logic in flang lowering
DeltaFile
+31-27flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+54-0flang/test/Lower/OpenMP/linear_modifier.f90
+12-0flang/test/Lower/OpenMP/declare-simd.f90
+6-6flang/test/Lower/OpenMP/composite_simd_linear.f90
+5-5flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
+5-5flang/test/Lower/OpenMP/simd-linear.f90
+113-433 files not shown
+119-499 files

LLVM/project 0450247libclc/clc/lib/amdgpu CMakeLists.txt, libclc/clc/lib/amdgpu/math clc_amdgpu_cbrt.inc clc_cbrt.cl

libclc: Override cbrt for AMDGPU
DeltaFile
+77-0libclc/clc/lib/amdgpu/math/clc_amdgpu_cbrt.inc
+34-0libclc/clc/lib/amdgpu/math/clc_cbrt.cl
+1-0libclc/clc/lib/amdgpu/CMakeLists.txt
+112-03 files

LLVM/project fd3cf1cllvm/include/llvm/Transforms/Vectorize LoopVectorizationLegality.h, llvm/lib/Transforms/Vectorize VPlanConstruction.cpp LoopVectorize.cpp

[LV] Move dereferenceability check from Legal to VPlan (NFC) (#185323)

Instead of checking dereferenceability early during
LoopVectorizationLegality, defer the check to VPlan construction via
areAllLoadsDereferenceable.

This in preparation for supporting early exit vectorization of
non-dereferencable loads, e.g. via speculative loads
(https://discourse.llvm.org/t/rfc-provide-intrinsics-for-speculative-loads/89692)
or first-faulting loads. Detection in VPlan allows easily replacing
potentially non-deref loads with other loads as needed.

PR: https://github.com/llvm/llvm-project/pull/185323
DeltaFile
+58-3llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+17-1llvm/unittests/Transforms/Vectorize/VPlanTestBase.h
+8-10llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1-15llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+8-3llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+0-9llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+92-414 files not shown
+103-4710 files

LLVM/project 29e2922flang/include/flang/Semantics openmp-utils.h, flang/lib/Semantics openmp-utils.cpp check-omp-loop.cpp

[flang][OpenMP] Introduce `WithReason<T>` for nest/sequence properties

This helper class contains an optional value and a "reason" message.
It replaces the uses of std::pair<optional<...>, Reason>.

Issue: https://github.com/llvm/llvm-project/issues/185287
DeltaFile
+81-40flang/lib/Semantics/openmp-utils.cpp
+33-8flang/include/flang/Semantics/openmp-utils.h
+12-13flang/lib/Semantics/check-omp-loop.cpp
+126-613 files

LLVM/project 2f1e242llvm/test/CodeGen/AArch64 ptrauth-isel.ll

[AArch64][PAC] Precommit ptrauth-isel.ll tests on calls and tail calls
DeltaFile
+209-0llvm/test/CodeGen/AArch64/ptrauth-isel.ll
+209-01 files

LLVM/project 486bd96libcxx/include version, libcxx/test/std/language.support/support.limits/support.limits.general new.version.compile.pass.cpp version.version.compile.pass.cpp

[libc++][NFC] Remove redundant guard for `__cpp_lib_destroying_delete` (#187473)

In `<version>` and test files, `__cpp_lib_destroying_delete` is already
properly guarded with standard modes, so it's redundant to say standard
revision in `test_suite_guard`/`libcxx_guard`.
DeltaFile
+6-6libcxx/test/std/language.support/support.limits/support.limits.general/new.version.compile.pass.cpp
+6-6libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
+2-2libcxx/utils/generate_feature_test_macro_components.py
+1-1libcxx/include/version
+15-154 files

LLVM/project 88cbac0libcxx/utils generate_abi_list.py generate_escaped_output_table.py, libcxx/utils/ci/lnt run-benchmarks

[libc++] Unify python shebangs (#187258)

As per PEP-0394[1], there is no real concensus over what binary names
Python has, specifically 'python' could be Python 3, Python 2, or not
exist.

However, everyone has a python3 interpreter and the scripts are all
written for Python 3. Unify the shebangs so that the ~50% of shebangs
that use python now use python3.

[1] https://peps.python.org/pep-0394/
DeltaFile
+1-1libcxx/utils/ci/lnt/run-benchmarks
+1-1libcxx/utils/generate_abi_list.py
+1-1libcxx/utils/generate_escaped_output_table.py
+1-1libcxx/utils/generate_extended_grapheme_cluster_table.py
+1-1libcxx/utils/generate_extended_grapheme_cluster_test.py
+1-1libcxx/utils/generate_feature_test_macro_components.py
+6-69 files not shown
+15-1515 files

LLVM/project 7657ea5libclc/clc/lib/generic/math clc_sin.inc clc_cos.inc

libclc: Implement sin and cos with sincos

This eliminates duplicated epilog code. The unused half
optimizes out just fine after inlining.
DeltaFile
+2-64libclc/clc/lib/generic/math/clc_sin.inc
+3-57libclc/clc/lib/generic/math/clc_cos.inc
+2-12libclc/clc/lib/generic/math/clc_sin.cl
+2-8libclc/clc/lib/generic/math/clc_cos.cl
+9-1414 files