LLVM/project 5c6cc0fclang/include/clang/Basic DiagnosticParseKinds.td

move diagnostic to the top
DeltaFile
+3-1clang/include/clang/Basic/DiagnosticParseKinds.td
+3-11 files

LLVM/project 16c6374.github/workflows llvm-abi-tests.yml

workflows/llvm-abi-tests: Fix typo (#209917)

Introduced by 9bd8bbb2b76c55ca83ddb6e0aa8a3a79b65706d4.
DeltaFile
+1-1.github/workflows/llvm-abi-tests.yml
+1-11 files

LLVM/project 694c561llvm/include/llvm/ADT GenericCycleImpl.h GenericCycleInfo.h, llvm/lib/Transforms/Utils FixIrreducible.cpp

[CycleInfo] Store cycles in a flat preorder array. NFC (#209981)

Store cycles by value in one array in cycle-forest preorder, each cycle
immediately followed by its descendants, instead of heap-allocating each
cycle and holding its children in a std::vector<std::unique_ptr<>>.
Child and top-level iteration become pointer arithmetic that skips a
subtree via a new NumDescendants count, and sizeof(GenericCycle) drops
from 72 to 48. GenericCycleInfoCompute builds the forest with temporary
nodes, then flatten() moves it into the array.

GenericCycle still exposes raw pointers into this array. The eventual
goal is to replace them with an opaque handle, so all access goes
through GenericCycleInfo and the storage stays an implementation detail.

Aided by Fable 5
DeltaFile
+98-111llvm/include/llvm/ADT/GenericCycleImpl.h
+52-71llvm/include/llvm/ADT/GenericCycleInfo.h
+2-9llvm/lib/Transforms/Utils/FixIrreducible.cpp
+152-1913 files

LLVM/project d76f524lldb/tools/lldb-server lldb-gdbserver.cpp

[lldb][Windows] Don't let the inferior inherit the --pipe handle (#207024)

`lldb-server` writes its listening socket id to the `--pipe` handle and
then closes it. The parent process that spawned it reads the pipe until
EOF purely as a synchronization point (`"the server is now listening"`).

On Windows the inferior is launched with `bInheritHandles=TRUE` (it
needs the ConPTY handles), so it also inherited the pipe's write end.
That kept the write end open after `lldb-server` closed its own handle,
so the parent never saw EOF: it blocked until its read timeout and the
client's connection handshake timed out first.

This patch clears `HANDLE_FLAG_INHERIT` on the `--pipe` handle so the
inferior cannot keep the write end open, while leaving it valid for
lldb-server's own use.

rdar://180736036
DeltaFile
+13-1lldb/tools/lldb-server/lldb-gdbserver.cpp
+13-11 files

LLVM/project 71956dcllvm/lib/Transforms/Utils SimplifyCFG.cpp, llvm/test/Transforms/SimplifyCFG/AMDGPU convergent-jump-threading.ll

[SimplifyCFG] Do not thread branches into uncontrolled convergent regions

SimplifyCFG's foldCondBranchOnValueKnownInPredecessor can thread an edge past
a block that acts as a reconvergence point. If the threaded destination reaches
an uncontrolled convergent operation before returning to the threaded-through
block, the transform can change which dynamic instance of the convergent
operation is executed.

Add a conservative destination scan for this fold and skip the threading
candidate when it can reach an uncontrolled convergent call before returning
to the original block. Controlled convergent operations using convergence
control tokens are left alone.

Fixes ROCM-26496.
DeltaFile
+68-6llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+53-4llvm/test/Transforms/SimplifyCFG/AMDGPU/convergent-jump-threading.ll
+121-102 files

LLVM/project c78de0bllvm/test/Transforms/SimplifyCFG/AMDGPU convergent-jump-threading.ll

[NFC] Pre-commit a test case for a SimplifyCFG issue
DeltaFile
+94-0llvm/test/Transforms/SimplifyCFG/AMDGPU/convergent-jump-threading.ll
+94-01 files

LLVM/project 66ec277llvm/lib/Target/RISCV RISCVRegisterInfo.td

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+6-6llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+6-61 files

LLVM/project c728067clang/lib/AST ExprConstant.cpp, clang/lib/Sema SemaExprCXX.cpp

Fix references to complete types in attribute references (#209537)

This is a regression from #197215.

Attributes are not REALLY in the body of a function (though the name of
said function is... awkwardly inaccurate at best), but still need to pay
attention to the completeness of their references. As a result, we
weren't marking the expression as invalid, but were also trying to
evaluate it.

This patch fixes this in 2 ways. First, we re-add the
CXXThisTypeOverride check, but except constant substitution, since that
has some additional 'this' behavior from #197215. x

Secondly, we also make the constant evaluator give up on incomplete
types when handling an L value member. This stops us from trying to
evaluate the value if it is incomplete during template instantiation,
when the type is incomplete. We don't diagnose, since it is still
potentially a constant expression, but isn't currently one.

    [3 lines not shown]
DeltaFile
+39-0clang/test/SemaCXX/enable_if.cpp
+11-2clang/lib/AST/ExprConstant.cpp
+8-0clang/lib/Sema/SemaExprCXX.cpp
+58-23 files

LLVM/project 88c69e5llvm/lib/Object GOFFObjectFile.cpp

[Object][GOFF] Recognize RLD and LEN records (#207118)

This patch adds explicit cases for RT_RLD and RT_LEN records when
parsing GOFF objects. These record types are not handled yet, but
recognizing them allows us to diagnose them and avoids teating them as
unexpected records.

(cherry picked from commit c40401dd8d28e88519433531c041b0b7e5ada8a9)
DeltaFile
+10-1llvm/lib/Object/GOFFObjectFile.cpp
+10-11 files

LLVM/project 23780dfpolly/lib/CodeGen IslNodeBuilder.cpp BlockGenerators.cpp, polly/test/CodeGen issue205732.ll

[Polly] Fix codegen assertions to account for DefinedBehaviorContext (#209188)

DeLICM may produce new read access relations whose domain is restricted
to the DefinedBehaviorContext (e.g., only valid when a parameter ensures
no UB). The validation in setNewAccessRelation already accounts for
this, but the debug assertions in createNewAccesses and
generateScalarLoads did not, causing false assertion failures during
code generation.

Intersect the checked domains with getBestKnownDefinedBehaviorContext()
to match the contract that DeLICM relies on.

Fixes #205732

(cherry picked from commit ea612545644d1e3f238ac4cd053758f569f9bf3b)
DeltaFile
+40-0polly/test/CodeGen/issue205732.ll
+10-2polly/lib/CodeGen/IslNodeBuilder.cpp
+5-0polly/lib/CodeGen/BlockGenerators.cpp
+55-23 files

LLVM/project a2520c9polly/include/polly/CodeGen LoopGenerators.h, polly/lib/CodeGen IslNodeBuilder.cpp LoopGenerators.cpp

[Polly] Skip vectorize.enable for FP loops with dist=1 dependences (#205756)

When -polly-annotate-metadata-vectorize is active, Polly marks its
generated loops with llvm.loop.vectorize.enable=true. This is harmful
for loops with a loop-carried dependence of distance 1 that involve
floating-point operations: the Loop Vectorizer reorders FP operations
(e.g. scalar reduction like q = factor*q), producing results that differ
from the sequential scalar reference and causing correctness failures.

Two changes are made:

1. IslAst.cpp: add PollyVectorizeMetadata to the PerformParallelTest
gate so that dependence-distance computation is performed whenever
-polly-annotate-metadata-vectorize is passed, not only when
-polly-parallel or a vectorizer is active.

2. IslNodeBuilder.cpp / LoopGenerators.cpp: when a loop has a dist=1
dependence involving FP operations, omit the vectorize.enable annotation
entirely. This lets the Loop Vectorizer apply its own cost model and

    [3 lines not shown]
DeltaFile
+56-0polly/test/CodeGen/Metadata/skip_vec_annotate_fp_dist1.ll
+45-2polly/lib/CodeGen/IslNodeBuilder.cpp
+6-6polly/lib/CodeGen/LoopGenerators.cpp
+5-1polly/include/polly/CodeGen/LoopGenerators.h
+4-1polly/lib/CodeGen/IslAst.cpp
+2-2polly/test/CodeGen/Metadata/basic_vec_annotate.ll
+118-126 files

LLVM/project 53dae32libsycl/include/sycl/__impl queue.hpp

[libsycl] fix nd_range template resolution (#210081)

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+4-3libsycl/include/sycl/__impl/queue.hpp
+4-31 files

LLVM/project 8568b08llvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU global-saddr-load.ll

AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for applyD16Load
DeltaFile
+14-1llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+2-2llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+16-32 files

LLVM/project 1a46ea2llvm/test/CodeGen/AMDGPU llvm.log10.ll llvm.log.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fpow.ll

AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper

Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
DeltaFile
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log.ll
+2,760-1,251llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+912-86llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+536-218llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+290-131llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+11,694-4,8624 files not shown
+12,158-5,07110 files

LLVM/project d44f464llvm/lib/Target/AMDGPU AMDGPUPreLegalizerCombiner.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-short-clamp.ll

AMDGPU/GlobalISel: Use integers for clamp i64 to i16 prelegalizer combine
DeltaFile
+26-46llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+6-6llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+32-522 files

LLVM/project 6fb39c6llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU codegen-prepare-addrspacecast-non-null.ll

GlobalISel: Use extended LLTs in extract lowering
DeltaFile
+60-29llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+1-1llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+79-485 files

LLVM/project 5b85ddcllvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU fptrunc.f16.ll fptrunc.ll

GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering
DeltaFile
+1,282-1,453llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+264-432llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+364-243llvm/test/CodeGen/AMDGPU/fptrunc.ll
+238-239llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
+176-91llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+47-47llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+2,371-2,5056 files

LLVM/project a5b7090llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp SIISelLowering.cpp

[AMDGPU] Guard more intrinsics with target features (#203956)
DeltaFile
+1-51llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+0-42llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+16-17llvm/lib/Target/AMDGPU/AMDGPU.td
+17-14llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+0-24llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+15-2llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+49-15024 files not shown
+109-20230 files

LLVM/project bfa63d4llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.prefetch.inst.ll llvm.amdgcn.s.prefetch.data.ll, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-load.mir regbankselect-waterfall-call.mir

AMDGPU/GlobalISel: Use integers for read-any-lane split type
DeltaFile
+150-72llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
+106-106llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+33-17llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
+24-24llvm/test/CodeGen/AMDGPU/indirect-call.ll
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+341-2476 files not shown
+364-27212 files

LLVM/project 3a3e8d5llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel zextload.ll

AMDGPU/GlobalISel: Fix extending load narrow scalar

isAnyScalar is explicit LLT::scalar check but we want to narrow scalar
integer types as well.
DeltaFile
+6-7llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+7-82 files

LLVM/project ae56abdllvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-constant.mir

AMDGPU/GlobalISel: Use integer as MMO type for loads and stores lowering

We could get away with just the type from MMO in most cases, but MMO splitting
creates MMO with LLT::scalar and we prefer integer.
DeltaFile
+1,622-1,442llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,064-944llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+828-738llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+842-722llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+250-220llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+121-121llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+4,727-4,1878 files not shown
+4,995-4,28614 files

LLVM/project c9ec54allvm/lib/Target/RISCV RISCVInstrInfo.cpp, llvm/test/CodeGen/RISCV rvp-simd-64.ll

[RISCV] Add DUMMY_REG_PAIR_WITH_X0->GPR copy to copyPhysReg. (#209964)

The register coalescer can convert (extract_subreg x0_pair, sub_gpr_odd)
to a read of DUMMY_REG_PAIR_WITH_X0. This patch treats it the same as a
copy from X0.

I don't know if this is a good long term fix, but I think it's ok for
now. I will continue to look for other options.
DeltaFile
+14-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+9-0llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+23-02 files

LLVM/project f57bdc6llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination and-negative.ll

[ConstraintElim] Handle (X & Y) <s 0 as X <s 0 && Y <s 0. (#210033)

InstCombine canonicalizes X <s 0 && Y <s 0 as (X & Y) <s 0. Teach
ConstraintElimination to recover the signed-negative information by
looking through compares of binary ANDs.

Alive2 Proof: https://alive2.llvm.org/ce/z/R6DWqD

Depends on https://github.com/llvm/llvm-project/pull/209743 

PR: https://github.com/llvm/llvm-project/pull/210033
DeltaFile
+87-0llvm/test/Transforms/ConstraintElimination/and-negative.ll
+48-0llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
+17-12llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+152-123 files

LLVM/project 5cdb956llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

AMDGPU/GlobalISel: Explicitly widen scalar to i32 for load and store

Affects f16 and bf16. Earlier, they were widened to f32 and s32 respectively.
The actual error was the artifact combiner creating a copy between f32/i32
which fails in the machine verifier. Maybe we could create a bitcast there.
However i32 is more efficient for us and matches well with how argument
lowering keeps f16 and bf16 in i32 copies to/from physical registers.
Also starting from f16 store, G_STORE %0(f16), %1(p1) :: (store (f16),
and doing widen scalar to 32 bit type, i32 makes more sense since store
will store 16 least significant bits G_STORE %0(i32), %1(p1) :: (store (f16)
compared to G_STORE %0(f32), %1(p1) :: (store (f16), which looks incorrect if
we assume input was really in f32 format.
DeltaFile
+2,008-2,008llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,164-1,164llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+963-963llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+556-556llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+486-486llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+108-108llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+5,285-5,28515 files not shown
+5,362-5,36821 files

LLVM/project b7d6572llvm/test/CodeGen/AMDGPU vector-reduce-smax.ll vector-reduce-smin.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.i16.ll insertelement.i8.ll

AMDGPU/GlobalISel: Fix legalizer lowering for G_EXTRACT/INSERT_VECTOR_ELT

Use LLT::integer in bit twiddling lowering for extract/insert vector element.
DeltaFile
+2,741-4,467llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+1,627-4,750llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+990-990llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+975-439llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+8,357-11,51426 files not shown
+13,363-14,10532 files

LLVM/project 689fa1dclang/include/clang/AST CommentLexer.h

Fix Unintialised char *CommentLexer resulting in potential UB. (#210067)

The patch intialised the  pointer to a .
Previously the pointer would have some garbage value which might have
resulted in UB.

closes #210034
DeltaFile
+1-1clang/include/clang/AST/CommentLexer.h
+1-11 files

LLVM/project 8f0a479llvm/lib/Transforms/IPO Instrumentor.cpp, llvm/test/Instrumentation/Instrumentor load_store_gpu_ind.ll load_store_gpu_ind.json

[Instrumentor] Fix indirect arguments on gpu targets (#209835)

When an argument is passed indirectly,
`IRTCallDescription::createLLVMCall` spills it into a temporary alloca
and passes that alloca address to the runtime call. The alloca is
created in the target's alloca address space. On GPUs it is not address
space 0, which is what the runtime expects for indirect parameters. The
alloca pointer was passed as the argument, so its type didn't match the
call's declared parameter type, causing a "bad signature" assertion in
`CallInst::init` when instrumenting GPU code that requires indirection.
The solution is therefore to cast this pointer to address space 0 before
passing it the the instrumentor call.
DeltaFile
+221-0llvm/test/Instrumentation/Instrumentor/load_store_gpu_ind.ll
+111-0llvm/test/Instrumentation/Instrumentor/load_store_gpu_ind.json
+3-3llvm/lib/Transforms/IPO/Instrumentor.cpp
+335-33 files

LLVM/project 608d741llvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Stop using changeTo in legaizer actions

Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
DeltaFile
+855-425llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+783-389llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+759-377llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+253-160llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+232-138llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+58-80llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+2,940-1,56911 files not shown
+3,066-1,65117 files

LLVM/project 01ef99ellvm/test/CodeGen/AMDGPU memset-param-combinations.ll shrink-add-sub-constant.ll, llvm/test/CodeGen/AMDGPU/GlobalISel ssubsat.ll saddsat.ll

AMDGPU/GlobalISel: Fix G_MERGE_VALUES lowering for extended LLTs

Use integer type for bit twiddling instead of scalar.
DeltaFile
+1,801-1,013llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
+1,584-1,032llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+1,583-1,004llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+1,449-654llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+1,314-625llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+989-704llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+8,720-5,032186 files not shown
+29,005-19,793192 files

LLVM/project 8641737llvm/test/CodeGen/AMDGPU freeze.ll vector-reduce-fmin.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f16.ll

AMDGPU/GlobalISel: Fix G_UNMERGE_VALUES lowering for extended LLTs

Use integer type for bit twiddling instead of scalar.
DeltaFile
+1,623-486llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+1,155-361llvm/test/CodeGen/AMDGPU/freeze.ll
+663-347llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+663-347llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+590-290llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+545-261llvm/test/CodeGen/AMDGPU/mad-mix.ll
+5,239-2,092150 files not shown
+15,641-10,429156 files