[CodeGenPrepare] Use make_early_inc_range to avoid iterator invalidation. (#215347)
While iterating users of a {s|z}ext's source operand in optimizeExtUses
we explicitly replace the use with a trunc instruction thereby
invalidating iterator of the loop. Update the loop to use
make_early_inc_range to avoid invalidation.
[lldb] Handle implicit values followed by full-width piece operations (#219160)
`DW_OP_implicit_value` stores its bytes in a `Value` whose internal type
is `HostAddress`. The `DW_OP_piece` and `DW_OP_bit_piece` evaluators
therefore mistook the backing-buffer address for a memory location and
rejected valid full-width pieces.
Use the saved implicit location-description kind to recognize this
storage representation. Full-width byte pieces and zero-offset
full-width bit pieces now preserve the backing bytes, while genuine host
addresses and partial pieces retain their existing behavior.
Add a unit test for both expressions from the issue.
Fixes #203224
[IR][TableGen] Add RangeSet TableGen intrinsic property (#203623)
This change introduces a `RangeSet` TableGen intrinsic property.
Existing `Range<idx, lo, hi>` keeps its current half-open semantics and
continues to emit the existing range attribute.
TableGen syntax: `RangeSet<idx, [[lo0, hi0], [lo1, hi1], ...]>` where
`[lo, hi]` are closed ordered and non-overlapped intervals.
[SCEV] Update comment for check BE formula in howManyLT (NFC) (#219170)
Update outdate comments around the code for picking the check BE
formula. It includes the following updates:
* define End = max(RHS,Start), as used later, use instead of incorrect
max(End,Start)
* precondition for the code use check min(RHS,Start) > Start - Stride
* update remaining test to be consistent
* Stride = umax(1, Stride) instead of umin, which matches the code
above; umin would not avoid divide by 0.
Preparation for https://github.com/llvm/llvm-project/pull/218694
PR: https://github.com/llvm/llvm-project/pull/219170
AMDGPU: Pass MachineRegisterInfo to getImmOrMaterializedImm (#219422)
The only used the operand to reach the MachineRegisterInfo. Pass it
directly so it no longer depends on MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[lldb] Reject an unusable memory-cache-line-size (#219217)
`target.process.memory-cache-line-size` is an unbounded `UInt64`, so
`settings set` accepts 0, and `MemoryCache` keeps the value in a
`uint32_t`, so it also accepts any multiple of 2^32, which truncates to
0. Every consumer then takes a remainder by 0.
`Process::ReadCStringFromMemory` divides on the first iteration of its
loop, before it touches inferior memory, so any address reproduces it.
On an x86_64 host that is a `SIGFPE` and lldb dies; on AArch64 `udiv` by
zero yields 0, so `addr % 0` evaluates to `addr` and the subtraction
underflows to a huge chunk size, and the bug hides.
```
$ lldb -b \
-o 'settings set target.process.memory-cache-line-size 0' \
-o 'target create --core linux-x86_64.core'
Floating point exception: 8
```
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RISCV: Pass MachineRegisterInfo to isVLKnownLE (#219402)
isVLKnownLE and its getEffectiveImm helper used the VL operands to reach
the MachineRegisterInfo. Pass it directly so they no longer depend on
MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
AMDGPU: Pass MachineRegisterInfo to getImmOrMaterializedImm
The only used the operand to reach the MachineRegisterInfo. Pass it
directly so it no longer depends on MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
CodeGen: Pass instruction and operand index to isPCRelRegisterOperandLegal
Replace the MachineOperand argument to the
TargetInstrInfo::isPCRelRegisterOperandLegal hook with the containing
instruction and operand index. The M68k implementation only used the operand
to recover its parent instruction and operand number, so this drops the
dependence on MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[SelectionDAG] Preserve CTTZ_ELTS lane count during expansion (#217982)
Fixes #216649
`expandCttzElts` derives `VL` from its legalized auxiliary step vector.
When that helper vector is widened for target legality, its lane count
may differ from the logical lane count of the `CTTZ_ELTS` operand.
On X86 with AVX512F, the step vector for a semantic `<4 x i1>` mask is
widened from `v4i8` to `v16i8`. As a result, an all-zero
`llvm.experimental.cttz.elts` input returns 16 instead of the required
result of 4.
Preserve the `ElementCount` from the `CTTZ_ELTS` operand and use it when
materializing `VL`. Auxiliary step-vector legalization can still widen
its representation without changing the logical lane domain of the
operation.
Add AVX512F regression coverage for the affected `v4i1` and `v8i1`
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[Clang] Fix -Wunused-parameter for implicit coroutine uses (#217518)
Clang's coroutine semantic analysis builds references to coroutine
parameters
while looking up a class-specific allocation function. When overload
resolution
falls back to a size-only `operator new`, these speculative references
currently
suppress `-Wunused-parameter`.
Preserve each parameter's referenced state while collecting placement
arguments, then mark the parameters referenced only when those arguments
are
included in the selected allocation call. Keep this distinction when
placement
arguments are replaced by `std::nothrow`.
Apply the same rule to promise initialization: when initialization using
the
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Revert "Revert "workflows/release-binaries: Disable flang on Darwin (#164667)"" (#218978)
Reverts llvm/llvm-project#216667
This change was ported to the `release/23.x` branch in #217059, and when
we created the first release that included this change (3.1.0), the job
for the MacOS ARM binaries was killed when the job hit the 6 hour mark.
Previous 3.1.0-rc release did not include this change and all completed
well within the 6 hour time out.
To enable the job that builds the release binaries to complete within
the allotted time, I am reverting this change which will essentially
disable flang from building on Darwin.
In the future if we get faster builders, we can explore re-enabling
building flang.
(cherry picked from commit 3d771f477aa026ca41cb3c4e492d7a07fa852cbe)
[X86] LowerAVXCONCAT_VECTORS - fix some clang-format messiness. NFC. (#218504)
Bad indentation and missing braces
Pulled out of #218381 to simplify functional diff
(cherry picked from commit a6eb1e1e75a2d29f8f458c6ee513ae5b030ff9a0)
[X86] LowerAVXCONCAT_VECTORS - collect all subvector operands before ReplaceAllUsesWith call (#218381)
We can end up referencing a node replaced with ISD::DELETED_NODE
Fixes #218379
(cherry picked from commit 7bced7f78781d3bdc179e64c777f50ef46ab1375)
[SLP]Fix narrow-tree gate width and extract miscount
Measure the narrowness of in-loop trees by the actual vectorization
width instead of the feeder-load width, and skip vector-typed scalars
in the instruction count check to match the cost model.
Fixes #216715
Reviewers: efriedma-quic, bababuck, RKSimon, kartcq
Pull Request: https://github.com/llvm/llvm-project/pull/216797
[GlobalISel] Fix inverted libcall status check in createFCMPLibcall (#219242)
BuildLibcall tested `if (!Status)` on the LegalizeResult returned by
createLibcall. Since LegalizeResult is an enum with AlreadyLegal == 0,
that condition is false for both Legalized and UnableToLegalize, so a
failed libcall was never detected. The helper then built an ICMP against
the undefined result register and reported success, so the legalizer
never fell back.
Check `Status != Legalized` instead, so failures propagate and the
caller can bail out.
On arm64ec, GlobalISel call lowering is unimplemented, so this silently
dropped `fp128` compare libcalls at `-O0`. Add a test that checks the
expected `__eqtf2`, `__lttf2` and `__unordtf2` calls are emitted at both
`-O0` and `-O2`.
(cherry picked from commit ded76cf640b9b7c1425f9543c54da402bbda7ca5)
[LoongArch] Fix selection of BRCOND with constant conditions (#216027)
LoongArch DAG instruction selection could fail to select
`LoongArchISD::BRCOND` when its condition was a constant integer. Add
patterns to lower constant zero and one conditions to `BEQZ` and `BNEZ`.
Co-authored-by: wanglei <wanglei at loongson.cn>
Fixes: https://github.com/llvm/llvm-project/issues/215935
(cherry picked from commit 17adf57f977f24685e535d649d2244610b104a13)
[VectorCombine] Fix foldBitcastOfVPLoad reordering loads (#218336)
We were inserting the new vp.load where the bitcast was, which would
reorder loads. This should hopefully fix RISC-V buildbot failures that
were exposed after 93ac788df8ff
(cherry picked from commit 2eda652e5cd7d70de8dd4f33a7cece6b70465163)
[lldb] Add Guarded<T, Mutex> to Locked.h
LLDB's code base has many variables that have an associated mutex that
needs to be locked to safely access that variable from multiple
threads. However, this locking scheme is currently not enforced by the
compiler and code sometimes accesses these variables without aquiring
the respective mutex first.
This patch introduces a `Guarded` class that strictly enforces that
some memory is only accessed after the respective mutex has been
aquired. This class hands out `Locked` objects for every access which
guarentee that the mutex is held as long as the variable is in scope.
X86: Use use_instructions in CompressEVEX cross-block check (#219408)
The loop only checks the using instruction's parent block, so iterate
use_instructions() instead of the operands and checking their parents.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Hexagon: Use use_instructions in EarlyIfConversion predicate check (#219405)
The loop only checks whether any user is a PHI, so iterate
use_instructions() instead of the operands to query the parents.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[SelectionDAG] Unique VT lists in a DenseSet instead of a FoldingSet (#219364)
Every getVTList call serializes the list's raw bits into a
FoldingSetNodeID and hashes it with xxh3, and every SDVTListNode carries
an interned copy of that profile. The list itself is the key.
Key VTLists on the ArrayRef the returned SDVTList already points at, and
let the two-, three- and four-type overloads share the ArrayRef one.
Aided by Opus 5
