[ARM][KCFI] Fix bundle sizes to reflect worst-case expansion (#164917)
The KCFI_CHECK pseudo-instruction size for ARM got miscalculated. These
should represent worst-case expansion to ensure correct branch range
calculations and code layout.
Update the Size field for each ARM sub-architecture:
- ARM: 28 → 40 bytes (10 instructions @ 4 bytes when r3 spill needed)
- Thumb2: 32 → 34 bytes (mixed 16/32-bit instructions with r3 spill)
- Thumb1: 50 → 38 bytes (19 instructions @ 2 bytes with r2+r3 spills)
The ARM and Thumb2 sizes were underestimating the case where the target
register is r12, requiring r3 to be used as scratch and
spilled/restored. The Thumb1 size was overestimated and has been
corrected to the actual worst-case of 19 instructions.
[CI] Make Premerge Advisor Upload to Both Advisor Instances
So that we do not have to worry about synchronizing data between the two
clusters. This also enables this script to work on AArch64, although
we'll look at enabling that later.
Reviewers: cmtice
Reviewed By: cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/165058
[X86][ISel] Improve VPTERNLOG matching for negated logic trees (#164863)
This patch extends VPTERNLOG pattern matching to handle cases where an
outer NOT wraps a pure logical tree, such as `~(A | B | C)`. By
recognizing these negated logic trees, the instruction selector can now
emit a single vpternlog instruction.
The change preserves the match for patterns like `(x != C1) & (x !=
C2)`, which also have the xor-with-all-ones pattern outside. The patch
conservatively peels the outer XOR-with-all-ones only when it directly
wraps a foldable logical operator (AND, OR, XOR, or ANDNP).
Resolves #163738
[CI] Make Postcommit Testing Pass In Correct Flags to Premerge Advisor
Before this patch we were passing in the previous commit rather than the
current commit due to a copy and paste adjustment failure from the PR
flow. We want the base SHA to just be the commit SHA for postcommit. We
also were not attaching the run number which made the source ID the
first JUnit XML file rather than the buildbot run number.
[lldb] Introduce internal stop hooks (#164506)
Introduce the concept of internal stop hooks.
These are similar to LLDB's internal breakpoints:
LLDB itself will add them and users of LLDB will
not be able to add or remove them.
This change adds the following 3
independently-useful concepts:
* Maintain a list of internal stop hooks that will be populated by LLDB
and cannot be added to or removed from by users. They are managed in a
separate list in `Target::m_internal_stop_hooks`.
* `StopHookKind:CodeBased` and `StopHookCoded` represent a stop hook
defined by a C++ code callback (instead of command line expressions or a
Python class).
* Stop hooks that do not print any output can now also suppress the
printing of their header and description when they are hit via
`StopHook::GetSuppressOutput`.
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[CI] Update Windows premerge testing to use clang-cl.exe (#164900)
Now that the Windows container contains clang, use it for building the
premerge tests. Measurements show this is significantly faster than
using msvc cl. Note we had to disable four warnings -Wc++98-compat,
-Wc++14-compat, -Wunsafe-buffer-usage, and -Wold-style-cast to make
this work with 'check-mlir' on Windows (clang generates a lot of warnings
that msvc cl does not).
[AMDGPU] Reset VGPR MSBs at the end of fallthrough basic block
By convention a basic block shall start with MSBs zero. We also
need to know a previous mode in all cases as SWDEV-562450 asks
to record the old mode in the high bits of the mode.
[CIR] Emit CIR builtins: coroAlloc, coroBegin, and coroSize (#164180)
This PR adds support for emitting the builtins coroAlloc, coroBegin, and
coroSize.
[ADT] Rename identity_cxx20 to identity (#164927)
Now that the old llvm::identity has moved into IndexedMap.h under a
different name, this patch renames identity_cxx20 to identity. Note
that llvm::identity closely models std::identity from C++20.
