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[AMDGPU][MC] Validate atomics with TH_ATOMIC_RETURN (#182888)

Have AsmParser validate that atomics that use th:TH_ATOMIC_RETURN also
have an extra operand representing the destination as opposed to no-rtn
variants.

In cases where it was not specified parsing would pass because it would
assume it was a no-rtn variant but would still set th bits properly
after parsing modifiers. Register for destination would default to v0
(encoded as 0).

Also update invalid tests.

Merge branch 'main' into users/kasuga-fj/da-fix-strong-siv-overlap-check

[MLIR] [Python] Added a missing cast to `__repr__` in the adaptors (#182867)

Without it the return type is inferred as `nanobind::object` which
results in invalid type stubs, since `__repr__` must return `str`.

[cmake] forward LLVM_EXTERNAL_*_SOURCE_DIR to runtimes (#180399)

Allow runtime source directories to live outside the top-level tree by
honoring LLVM_EXTERNAL_*_SOURCE_DIR and propagating the values via
RUNTIMES_CMAKE_ARGS.

[Thumb2] mve-vmovimm.ll - regenerate with missing check prefixes (#183019)

Add prefixes to discriminate between -mattr=+mve and -mattr=+mve.fp to
add missing check coverage

Fixes update_llc_test_checks warnings and simplifies regeneration for an
upcoming patch

[BOLT][BTI] Patch ignored functions in place when targeting them with indirect branches (#177165)

When applying BTI fixups to indirect branch targets, ignored functions
are
considered as a special case:
- these hold no instructions,
- have no CFG,
- and are not emitted in the new text section.

The solution is to patch the entry points in the original location.

If such a situation occurs in a binary, recompilation using the
-fpatchable-function-entry flag is required. This will place a nop at
all
function starts, which BOLT can use to patch the original section.

Without the extra nop, BOLT cannot safely patch the original .text
section.


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[NFC][AArch64] AArch64ConditionOptimizer extract shared instruction finding logic (#182244)

Extract cmp/cond instruction finding logic from cross- and intra-block
paths into shared functions

[X86] getFauxShuffleMask - OR(SHUF(),SHUF()) - treat undemanded elements as undef (#182678)

We have to be careful when attempting to decode OR() patterns as
shuffles - we can't forward demanded undef elements in both sources as
an undef result as it can lead to infinite loops during widening
(#49393).

But if we don't demand the element in the first place (based off
demanded elts masks during recursive shuffle combines), then it doesn't
matter what the elements contain and we can treat it as a
SM_SentinelUndef shuffle element.

Noticed while working on #137422

[libc++] Add segmented iterator optimization to std::equal (#179242)

```
Benchmark                                                 97fa3e593693    a820f8f10736    Difference    % Difference
------------------------------------------------------  --------------  --------------  ------------  --------------
std::equal(deque<int>)_(it,_it,_it)/1024                        510.92           82.64       -428.27         -83.82%
std::equal(deque<int>)_(it,_it,_it)/1048576                  518795.61        87141.29    -431654.32         -83.20%
std::equal(deque<int>)_(it,_it,_it)/50                           29.24            6.77        -22.46         -76.84%
std::equal(deque<int>)_(it,_it,_it)/8                             4.20            3.71         -0.49         -11.61%
std::equal(deque<int>)_(it,_it,_it)/8192                       3972.84          643.83      -3329.01         -83.79%
std::equal(deque<int>)_(it,_it,_it,_it)/1024                    417.45           81.52       -335.93         -80.47%
std::equal(deque<int>)_(it,_it,_it,_it)/1048576              539228.26        87480.92    -451747.34         -83.78%
std::equal(deque<int>)_(it,_it,_it,_it)/50                       22.25            7.25        -15.00         -67.41%
std::equal(deque<int>)_(it,_it,_it,_it)/8                         4.75            4.44         -0.31          -6.45%
std::equal(deque<int>)_(it,_it,_it,_it)/8192                   3259.01          641.31      -2617.70         -80.32%
std::equal(deque<int>)_(it,_it,_it,_it,_pred)/1024              532.68          327.58       -205.10         -38.50%
std::equal(deque<int>)_(it,_it,_it,_it,_pred)/1048576        600755.28       402988.04    -197767.24         -32.92%
std::equal(deque<int>)_(it,_it,_it,_it,_pred)/50                 27.26           25.29         -1.97          -7.22%
std::equal(deque<int>)_(it,_it,_it,_it,_pred)/8                   5.20            5.58          0.38           7.31%

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[lldb][TypeSystemClang] Unconditionally set access control to AS_public (#182956)

This patch removes all our manual adjustments to the access control
specifiers of Clang decls we create from DWARF.

This has led to occasional subtle bugs in the past (the latest being
https://github.com/llvm/llvm-project/issues/171913) and it's ultimately
redundant because Clang already has provisions for LLDB to bypass access
control for C++ and Objective-C. Access control doesn't affect name
lookup so really we're doing a lot of bookkeeping for not much benefit.
The only "feature" that relied on this was that `type lookup <foo>`
would print the access specifier in the output structure layout. I'm not
convinced that's worth keeping the infrastructure in place for (but
happy to be convinced otherwise).

I'd rather lean fully into the Clang access control bypass instead.

Note, i still kept the `AccessType` parameters to the various
`TypeSystemClang` APIs to reduce the size of the diff. A follow-up NFC
change will remove those parameters and adjust all the call-sites.

[compiler-rt][ARM] Enable strict mode in divsf3/mulsf3 tests (#179918)

Commit 5efce7392f3f6cc added optimized AArch32 assembly versions of
mulsf3 and divsf3, with more thorough tests. The new tests included test
cases specific to Arm's particular NaN handling rules, which are
disabled on most platforms, but were intended to be enabled for Arm.

Unfortunately, they were not enabled under any circumstances, because I
made a mistake in `test/builtins/CMakeLists.txt`: the command-line `-D`
option that should have enabled them was added to the cflags list too
early, before the list was reinitialized from scratch. So it never ended
up on the command line.

Also, the test file mulsf3.S only even _tried_ to enable strict mode in
Thumb1, even though the Arm/Thumb2 implementation would also have met
its requirements.

Because the strict-mode tests weren't enabled, I didn't notice that they
would also have failed absolutely everything, because they checked the

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[WebAssembly] Use generic CPU by default in llvm-mc (#181460)

Other tools, such as `llc`, use `generic` cpu by default, if you don't
give any `-mcpu`:

https://github.com/llvm/llvm-project/blob/75f738b0b2a15281c6f285380ea947e973a6e02f/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp#L38-L39

But `llvm-mc` didn't do that. This makes `generic` also the default CPU
for `llvm-mc`.

Add simple hasOneNonDBGUse check

[mlir][SPIRV] Add sub-element-byte lowering support for atomic_rmw ori/andi ops (#179831)

When the memref element type (e.g., i8) is narrower than the SPIR-V
storage type (e.g., i32 on Vulkan), ori and andi can be lowered with a
single wide atomic instruction because OR-with-0 and AND-with-1 are
identity operations.

The revision follows `IntStoreOpPattern` to compute offsets/sizes via
`adjustAccessChainForBitwidth` method and `getOffsetForBitwidth` method.
Additionally, it handles the returned value (which is the old value by
definition), which is different from `IntStoreOpPattern`. E.g., the
check of `spirv::Capability::Kernel` is the same.


https://github.com/llvm/llvm-project/blob/07ebb18e07fb9e009b1f738d6214a49c7bbe8fee/mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp#L847-L867

There are refactoring opportunities and it is not performed within the
revision because the current implementation is already complicated. The
refactoring can be happenned in a follow-up with its own patch, so

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[libc++] Make `__wrap_iter` comparison operators hidden friends (#179590)

Prelude to #179389

[WIP][ROCDL] Added SWMMAC ops for gfx12 and gfx1250 (#181943)

This PR adds SWMMAC ops for gfx12 and gfx1250 arch.

Merge remote-tracking branch 'external-upstream/main' into users/mariusz-sikora-at-amd/gfx13/add-vopc

SafeStack: Add missing lit.local.cfg to SPARC subdirectory

Forgot to commit file in 8604b52e380fb37a3599539b1d87a68666ab6ed5

[AArch64] Match CTPOP combine without zero extend  (#182859)

Helps improve: https://github.com/llvm/llvm-project/issues/182625.

This does not fully solve the issues with using `ctpop` as the vector
type chosen for the reduction is not ideal in all cases. This results in
extra extends, which can be seen in a few test cases.

[AMDGPU] Add VOP2 to gfx13 (#182812)

Co-authored-by: Ivan Kosarev <ivan.kosarev at amd.com>

Fix formatting

Remove wip_match_opcode, add TODO for regression

Adjust combine pattern.

[AMDGPU] Add VOPD to gfx13 (#182815)

Co-authored-by: Jay Foad <jay.foad at amd.com>

Move combine into AMDGPURegBankCombiner

[AMDGPU][GlobalISel] Add COPY_SCC_VCC combine for VCC-SGPR-VGPR pattern

Eliminate VCC->SGPR->VGPR bounce created by UniInVcc when the uniform boolean
result is consumed by a VALU instruction that requires the input in VGPRs.

Reapply "RuntimeLibcalls: Fix adding __safestack_pointer_address by default" (#182949) (#183005)

This reverts commit 6d37110e091569509f54e2b1f3ef35e8a50e5b70.

Now with aarch64 test.

Update .mir test, add .ll test

Bump version to 22.1.0

[AMDGPU] Test hazard-getreg-waitalu.mir on gfx13