LLVM/project a6d6fd7flang-rt/lib/runtime CMakeLists.txt

Post-merge fixes
DeltaFile
+5-4flang-rt/lib/runtime/CMakeLists.txt
+5-41 files

LLVM/project 5d9301dlibclc/clc/lib/generic/math clc_erfc.cl clc_erf.cl, llvm/test/CodeGen/AMDGPU memmove-param-combinations.ll ctls.ll

Merge commit 'cfeee082b671e2ac6ee6c24babddf5dc89dd264c' into HEAD
DeltaFile
+601-1,016llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
+290-378llvm/test/CodeGen/X86/srem-vector-lkk.ll
+624-0llvm/test/CodeGen/AMDGPU/ctls.ll
+5-507libclc/clc/lib/generic/math/clc_erfc.cl
+5-496libclc/clc/lib/generic/math/clc_erf.cl
+334-131llvm/test/CodeGen/RISCV/memmove.ll
+1,859-2,528779 files not shown
+18,823-10,796785 files

LLVM/project cfeee08libclc/clc/lib/generic/math clc_erfc.cl clc_erf.cl, llvm/test/CodeGen/AMDGPU memmove-param-combinations.ll ctls.ll

Merge commit '6854802a3dc90c8344e64bfa03dff6e839c8c59f' into HEAD
DeltaFile
+601-1,016llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
+290-378llvm/test/CodeGen/X86/srem-vector-lkk.ll
+624-0llvm/test/CodeGen/AMDGPU/ctls.ll
+5-507libclc/clc/lib/generic/math/clc_erfc.cl
+5-496libclc/clc/lib/generic/math/clc_erf.cl
+334-131llvm/test/CodeGen/RISCV/memmove.ll
+1,859-2,528779 files not shown
+18,820-10,792785 files

LLVM/project 6854802libclc/clc/lib/generic/math clc_erfc.cl clc_erf.cl, llvm/test/CodeGen/AMDGPU memmove-param-combinations.ll ctls.ll

Merge commit 'b164e7c61020aa40995779574bb7e8064f165a09' into HEAD
DeltaFile
+601-1,016llvm/test/CodeGen/AMDGPU/memmove-param-combinations.ll
+290-378llvm/test/CodeGen/X86/srem-vector-lkk.ll
+624-0llvm/test/CodeGen/AMDGPU/ctls.ll
+5-507libclc/clc/lib/generic/math/clc_erfc.cl
+5-496libclc/clc/lib/generic/math/clc_erf.cl
+334-131llvm/test/CodeGen/RISCV/memmove.ll
+1,859-2,528779 files not shown
+18,820-10,792785 files

LLVM/project 8e59c3amlir/lib/Conversion/XeVMToLLVM XeVMToLLVM.cpp

[XeVM] Fix the cache-control metadata string generation. (#187591)

Previously, it generated extra `single` quote marks around the outer
braces (i.e., `'{'` `6442:\220,1\22` `'}'`). SPIR-V backend does not
expect that. It expects `{6442:\220,1\22}`.
DeltaFile
+4-4mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
+4-41 files

LLVM/project c6fa976llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-proper-value-replacement.ll

AMDGPU: Make VarIndex WeakTrackingVH in AMDGPUPromoteAlloca (#188921)

The test used to look all good, but actually not. The WeakVH just make
itself null after the pointed value being replaced. So a zero value was
used because VarIndex become null. The test checks looks all good.

Actually only the WeakTrackingVH have the ability to be updated to new
value.

Change the test slightly to make that using zero index is wrong.
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/promote-alloca-proper-value-replacement.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+4-42 files

LLVM/project bc12c38clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp, clang/lib/CodeGen CGDebugInfo.cpp

[Clang] remove redundant uses of dyn_cast (NFC) (#189106)

This removes dyn_cast invocations where the argument is already of the
target type (including through subtyping). This was created by adding a
static assert in dyn_cast and letting an LLM iterate until the code base
compiled. I then went through each example and cleaned it up. This does
not commit the static assert in dyn_cast, because it would prevent a lot
of uses in templated code. To prevent backsliding we should instead add
an LLVM aware version of
https://clang.llvm.org/extra/clang-tidy/checks/readability/redundant-casting.html
(or expand the existing one).
DeltaFile
+12-16clang/lib/Sema/Sema.cpp
+8-9clang/lib/CodeGen/CGDebugInfo.cpp
+4-6clang/tools/driver/cc1gen_reproducer_main.cpp
+4-6clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+5-5clang/lib/Frontend/InterfaceStubFunctionsConsumer.cpp
+3-4clang/lib/Sema/SemaFunctionEffects.cpp
+36-469 files not shown
+48-6315 files

LLVM/project 5bb4eeallvm/test/CodeGen/Hexagon constext-store-imm.ll target-objfile-sdata.ll

[Hexagon] Add coverage tests for AsmPrinter and misc CodeGen (#183953)

Add tests targeting assembly printing and miscellaneous CodeGen areas
with low coverage:

- asm-printer-cpool.ll: HexagonAsmPrinter exercising constant pool entry
emission.

- asm-operand-modifiers.ll: Inline asm operand modifier printing paths
(lo/hi/mem).

- target-objfile-sdata.ll, split-double-volatile.ll, reg-info-types.ll:
Miscellaneous CodeGen coverage for HexagonTargetObjectFile small data
classification, HexagonSplitDouble volatile load handling, and
HexagonRegisterInfo register class queries.

- constext-store-imm.ll: HexagonConstExtenders store-immediate
optimization paths.
DeltaFile
+56-0llvm/test/CodeGen/Hexagon/constext-store-imm.ll
+40-0llvm/test/CodeGen/Hexagon/target-objfile-sdata.ll
+33-0llvm/test/CodeGen/Hexagon/asm-printer-cpool.ll
+31-0llvm/test/CodeGen/Hexagon/reg-info-types.ll
+31-0llvm/test/CodeGen/Hexagon/asm-operand-modifiers.ll
+31-0llvm/test/CodeGen/Hexagon/split-double-volatile.ll
+222-06 files

LLVM/project 9be0cc1llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU fsqrt.f64.ll rsq.f64.ll

AMDGPU: Skip last corrections and scaling for afn llvm.sqrt.f64 (#183697)

Device libs has a fast sqrt macro implemented this way.
DeltaFile
+240-652llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
+140-602llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+23-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+22-17llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+425-1,2884 files

LLVM/project 1264ffcclang/lib/CodeGen/Targets RISCV.cpp, clang/test/CodeGen/RISCV riscv-fpcc-struct.c riscv64-abi.c

[clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (#110690)

The code generated for calls with FPCC eligible structs as arguments
doesn't consider the bitfield, which results in a store crossing the
boundary of the memory allocated using alloca, e.g.
For the code:
```
struct __attribute__((packed, aligned(1))) S {
   const float  f0;
   unsigned f1 : 1;
};
unsigned  func(struct S  arg)
{
    return arg.f1;
} 
```
The generated IR is:
```
 define dso_local signext i32 @func(

    [29 lines not shown]
DeltaFile
+28-0clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
+7-0clang/lib/CodeGen/Targets/RISCV.cpp
+2-2clang/test/CodeGen/RISCV/riscv64-abi.c
+37-23 files

LLVM/project 7b2b252llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Parse instructions in AArch64AsmParser.cpp
DeltaFile
+87-5llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+0-14llvm/lib/Target/AArch64/AArch64InstrInfo.td
+87-192 files

LLVM/project 2528d2cllvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU fsqrt.f64.ll rsq.f64.ll

AMDGPU: Skip last corrections and scaling for afn llvm.sqrt.f64

Device libs has a fast sqrt macro implemented this way.
DeltaFile
+240-652llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
+140-602llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+23-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+22-17llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+425-1,2884 files

LLVM/project c4847d2clang/cmake/caches Fuchsia-stage2.cmake

[Fuchsia] Set LIBCXX_ABI_UNSTABLE instead of LIBCXX_ABI_VERSION (#189123)

Use the generic switch rather than encoding the version number it
currently corresponds to.
DeltaFile
+6-6clang/cmake/caches/Fuchsia-stage2.cmake
+6-61 files

LLVM/project a5fa4dbcompiler-rt/lib/asan asan_malloc_linux.cpp asan_allocator.cpp, compiler-rt/lib/hwasan hwasan_allocation_functions.cpp

[compiler-rt] Add interceptors for free_[aligned_]sized for asan+hwasan (#189109)
DeltaFile
+32-0compiler-rt/lib/hwasan/hwasan_allocation_functions.cpp
+22-0compiler-rt/lib/asan/asan_malloc_linux.cpp
+13-0compiler-rt/lib/asan/asan_allocator.cpp
+3-0compiler-rt/lib/asan/asan_allocator.h
+1-1compiler-rt/test/sanitizer_common/TestCases/Linux/free_aligned_sized.c
+1-1compiler-rt/test/sanitizer_common/TestCases/Linux/free_sized.c
+72-26 files

LLVM/project 15bc5b0libclc/clc/lib/generic/math clc_fract.inc

libclc: Simplify fract implementation (#189080)
DeltaFile
+2-2libclc/clc/lib/generic/math/clc_fract.inc
+2-21 files

LLVM/project ae0b107flang/lib/Lower/OpenMP ClauseProcessor.cpp, flang/test/Lower/OpenMP depend-iterator.f90

[Flang][OpenMP] Support iterator modifier in depend clause

This patch depend on #189090 and is part of feature work for #188061

Assisted with copilot
DeltaFile
+198-0flang/test/Lower/OpenMP/depend-iterator.f90
+63-14flang/lib/Lower/OpenMP/ClauseProcessor.cpp
+0-10flang/test/Lower/OpenMP/Todo/depend-clause.f90
+261-243 files

LLVM/project ae63230libc/include stdint.yaml float.yaml, libc/include/sys stat.yaml epoll.yaml

[libc] Remove more header template files (#189066)

Get rid of several .h.def files which were used to ensure that the
macro definitions from llvm-libc-macro would be included in the public
header. Replace this logic with YAML instead - add entries to the
"macros" list that point to the correct "macro_header" to ensure it
would be included.

For C standard library headers, list several standard-define macros
to document their availability. For POSIX/Linux headers, only reference
a handful of macro, since more planning is needed to decide how to
represent platform-specific macro in YAML.
DeltaFile
+123-2libc/include/stdint.yaml
+17-68utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+81-2libc/include/float.yaml
+36-4libc/include/endian.yaml
+5-20libc/include/sys/stat.yaml
+5-14libc/include/sys/epoll.yaml
+267-11028 files not shown
+321-43934 files

LLVM/project 7be9972libclc CMakeLists.txt, libclc/cmake/modules AddLibclc.cmake

[libclc] Fix llvm-spirv dependency when llvm-spirv is built in-tree (#188896)

When SPIRV-LLVM-Translator is built in-tree (i.e., placed in
llvm/projects folder), llvm-spirv target exists.

Drop legacy llvm-spirv_target dependency (was for non-runtime build) and
add llvm-spirv to runtimes dependencies.
DeltaFile
+1-1libclc/cmake/modules/AddLibclc.cmake
+1-1llvm/runtimes/CMakeLists.txt
+0-1libclc/CMakeLists.txt
+2-33 files

LLVM/project 89ae675llvm/lib/Target/SPIRV SPIRVLegalizePointerCast.cpp, llvm/test/CodeGen/SPIRV/pointers store-array-of-vectors-to-vector.ll

[SPIRV][Matrix] Legalize store of matrix to array of vector memory layout (#188139)

fixes #188131

This change address stylistic changes @bogners requested in
https://github.com/llvm/llvm-project/pull/186215/ It also adds the
`storeMatrixArrayFromVector`. to
SPIRVLegalizePointerCast.cpp when we detect the matrix array of vector
memory layout
Changes to storeArrayFromVector were cleanup

Assisted-by Github Copilot for test case check lines
DeltaFile
+67-43llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
+107-0llvm/test/CodeGen/SPIRV/pointers/store-array-of-vectors-to-vector.ll
+174-432 files

LLVM/project 1128d74lld/docs/ELF linker_script.rst

[LLD][skip ci] Fix typo in linker_script.rst (#148867)
DeltaFile
+1-1lld/docs/ELF/linker_script.rst
+1-11 files

LLVM/project efba01acompiler-rt/lib/builtins/cpu_model riscv.c, llvm/lib/Target/RISCV RISCVFeatures.td

[RISCV] Allocate feature bits for Zifencei and Zmmul (#143306)

As proposed in
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/110.

No real compiler-rt implementation as Linux does not list these
extensions in hwprobe.

Signed-off-by: Luke Wren <wren6991 at gmail.com>
DeltaFile
+4-2llvm/lib/Target/RISCV/RISCVFeatures.td
+4-0compiler-rt/lib/builtins/cpu_model/riscv.c
+8-22 files

LLVM/project fe03ef0llvm/test/MC/AArch64 armv9.4a-gcs.s arm64-aliases.s

fixup! Move new tests into arm64-aliases.s
DeltaFile
+0-40llvm/test/MC/AArch64/armv9.4a-gcs.s
+32-0llvm/test/MC/AArch64/arm64-aliases.s
+25-0llvm/test/MC/AArch64/armv9a-sysp-pairs.s
+2-6llvm/test/MC/AArch64/brbe.s
+0-5llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
+0-5llvm/test/MC/AArch64/armv8.9a-debug-pmu.s
+59-566 files

LLVM/project a2d84b5llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/test/Bitcode amdgpu-wmma-drop-ab-mods-upgrade.ll

[AMDGPU] Remove neg support from 4 more gfx1250 WMMA (#189115)

These are previously covered by AMDGPUWmmaIntrinsicModsAllReuse.
DeltaFile
+16-192llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
+40-40llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
+52-0llvm/test/Bitcode/amdgpu-wmma-drop-ab-mods-upgrade.ll
+16-16llvm/test/CodeGen/AMDGPU/waitcnt-loop-opt.mir
+16-16llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
+4-21llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+144-28512 files not shown
+216-32918 files

LLVM/project 0448764llvm/include/llvm/IR ProfDataUtils.h, llvm/test/Transforms/SimplifyCFG branch-weight-disjunction-overflow.ll

[ProfInfo] Fix integer overflow in getDisjunctionWeights (#189079)

This PR fixes an integer overflow in
[`getDisjunctionWeights`](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/IR/ProfDataUtils.h#L241)
and adds a regression test to cover the failing case. Casting branch
weights before the computations solved the issue.

Issue https://github.com/llvm/llvm-project/issues/189021
DeltaFile
+87-0llvm/test/Transforms/SimplifyCFG/branch-weight-disjunction-overflow.ll
+15-2llvm/include/llvm/IR/ProfDataUtils.h
+102-22 files

LLVM/project d6ff5e7libc/utils/docgen header.py

[libc][docs] Parse inline macro_value from YAML in docgen (#189118)

The docgen script was previously hardcoded to assume all implemented
macros must be placed in a *-macros.h header. This updates docgen to
read inline macro_value properties directly from the source YAML files,
correctly recognizing them as implemented.
DeltaFile
+24-0libc/utils/docgen/header.py
+24-01 files

LLVM/project aa1d6fallvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! More tablegen fixes
DeltaFile
+31-69llvm/lib/Target/AArch64/AArch64SystemOperands.td
+31-691 files

LLVM/project 368fdf2llvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! Refactor TLBI tablegen
DeltaFile
+233-120llvm/lib/Target/AArch64/AArch64SystemOperands.td
+233-1201 files

LLVM/project 58f1e28llvm/lib/Target/AArch64 AArch64SystemOperands.td

fixup! Change tablegen as suggested
DeltaFile
+52-30llvm/lib/Target/AArch64/AArch64SystemOperands.td
+52-301 files

LLVM/project 920d133llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

fixup! Push these changes further into the backend
DeltaFile
+25-14llvm/lib/Target/AArch64/AArch64SystemOperands.td
+11-6llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+6-9llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+4-4llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+46-334 files

LLVM/project 9167fb5llvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/test/MC/AArch64 armv8.7a-xs.s armv9.5a-tlbiw.s

fixup! Move nxs bit into TLBIEntry rather than override
DeltaFile
+57-56llvm/test/MC/AArch64/armv8.7a-xs.s
+21-33llvm/lib/Target/AArch64/AArch64SystemOperands.td
+10-10llvm/test/MC/AArch64/armv9.5a-tlbiw.s
+88-993 files