[clang] fix redeclarations of the injected class name (#207301)
The declaration used to represent an injected class name should never be
part of any redeclaration chain.
Fixes #202320
[compiler-rt][hwasan] Remove internal linkage from check templates (NFC) (#207430)
`SigTrap`, `CheckAddress`, and `CheckAddressSized` are static function
templates in `hwasan_checks.h`, so any TU that includes the header
without instantiating them trips -Wunused-template. Dropping static
clears the warning.
Part of #202945
[PowerPC] Remove itinerary IIC_LdStDCBA
The itinerary IIC_LdStDCBA is defined and used in scheduling models, but no instruction is assigned to it. However, since the instruction is basically retired (not part of the portable Power ISA), and all scheduling models model it similar to IIC_LdStDCBF, the itinerary can be removed.
[VPlan] Add m_VScale() pattern matcher. (NFC) (#207394)
Add a dedicated m_VScale() matcher for VPInstruction::VScale, in line
with other VPInstruction matchers.
[X86] Pool sparse disassembler opcode rows (#202666)
The XOP, 3DNow, and VEX/EVEX map 4-7 decoder tables contain 1,760
context rows but only 266 distinct values. Keep the four common opcode
maps as direct tables and intern rows only for these eight sparse maps.
This reduces fully stripped arm64 llvm-mc from 8,333,344 to 6,797,728
bytes, saving 1,535,616 bytes (18.43%). X86Disassembler.cpp.o decreases
by 1,525,328 bytes (52.36%); constant data falls by 1,526,328 bytes
while text grows by 848 bytes. The stripped all-tools multicall binary
decreases from 145,103,200 to 143,567,584 bytes, saving 1,535,616 bytes
(1.058%).
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
[compiler-rt][sanitizer_common] Remove internal linkage from RegisterFlag (NFC) (#206308)
RegisterFlag is a static function template in a header, so every TU that
includes it without calling it trips `-Wunused-template`. Dropping
static gives it normal external linkage and clears the warning.
NFC. Part of #202945.
[clang] fix redeclarations of the injected class name
The declaration used to represent an injected class name should never
be part of any redeclaration chain.
Fixes #202320
[SPIRV] Preserve FP types in atomic load/store instead of casting to integer (#194583)
The default
`TargetLowering::shouldCastAtomicLoadInIR`/`shouldCastAtomicStoreInIR`
cast all FP atomics to integer, producing unnecessary bitcasts in SPIR-V
output. Override both to return None, matching the existing
`shouldCastAtomicRMWIInIR` behavior and letting
`OpAtomicLoad`/`OpAtomicStore` operate on FP types directly.
Also updated 16-bit atomics tests from #184312 to use native load/store
atomic instructions now that the SPIRV backend supports them (landed in
#185696).
AI-assisted: Claude Sonnet 4.6 (commercial SaaS)
[clang-format] Fix crash on numeric literals with an incomplete exponent (#206594)
NumericLiteralInfo could read into tokens out of bounds due to the token
processing assuming well-formed numeric literals and incrementing
pointers to read past them. The fix properly bounds the searches to the
token size via std::min and accounts for the new trimmed string size.
Fixes #206593
Used Claude Code for help with identifying the source of the bug and
checking correctness with fuzzing, wrote the solution myself
[clang-format] Fix annotating paren after in (#206810)
The y.in(foo) was considered a cast, and thus the following - annotated
as unary operator.
Fixes #206339
AMDGPU/GlobalISel: Switch to extended LLTs
IRtranslator now translates bfloat. Switch tablegen to use extendedLLTs.
Around 300 regression tests fail to inst-select because GIM_SwitchType
does not accept LLT::scalar. Around 100 mir inst select tests had input
updated to i32/f32 and selects successfully. Then there are 24 various
crashes, mostly combiner or machine-verifier, those tests are disabled.
Most problems come from mixing s32 with i32/f32 and the way
operator== works with extendedLLTs compared to GIM_SwitchType.
In general, for inst-select fixes, think it would be best to try and avoid
explicit use of LLT::scalar in lowering to avoid mixing it with i32/f32
See inst-select-extendedLLTs.mir and inst-select-extendedLLTs-err.mir.
[NFC][LLVM] Define range attribute for `llvm.prefetch` args (#207300)
Define valid range for `llvm.prefetch` immarg values and eliminate C++
verification code.
Additionally, change the range verification failure message to include
the argument number and simplify formatting using `formatv`.