LLVM/project 9df49aellvm/include/llvm InitializePasses.h, llvm/include/llvm/CodeGen LiveRangeShrink.h

[NewPM] Port LiveRangeShrink to the new pass manager

Follow the same pattern used for EHContGuardTargets and
CFGuardLongjmp: extract the pass body into a free function, rename
the legacy pass to LiveRangeShrinkLegacy, and add a
LiveRangeShrinkPass for the new pass manager. Register it in
MachinePassRegistry.def, replacing the DUMMY_MACHINE_FUNCTION_PASS
stub, and add the missing include to X86CodeGenPassBuilder.cpp,
which already called addMachineFunctionPass(LiveRangeShrinkPass(),
PMW) in its addPreRegAlloc.

Unlike EHContGuardTargets/CFGuardLongjmp, this pass is skippable
(runOnMachineFunction calls skipFunction), so the new-PM pass uses
OptionalPassInfoMixin rather than RequiredPassInfoMixin, matching
BreakFalseDepsPass.

Update llc-pipeline-npm.ll: the pass now prints its registered
"lrshrink" name instead of falling back to the raw C++ type name.
Add -enable-new-pm RUN lines to the three existing lrshrink tests;

    [4 lines not shown]
DeltaFile
+24-10llvm/lib/CodeGen/LiveRangeShrink.cpp
+24-0llvm/include/llvm/CodeGen/LiveRangeShrink.h
+2-2llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+1-1llvm/lib/CodeGen/CodeGen.cpp
+1-1llvm/include/llvm/Passes/MachinePassRegistry.def
+1-1llvm/include/llvm/InitializePasses.h
+53-155 files not shown
+58-1511 files

LLVM/project dd8afceclang/lib/CodeGen CGObjC.cpp, clang/test/CodeGenObjC property-aggregate.m

[Clang] Remove dead code related to atomics (NFC) (#216614)

This PR cleans up dead code in `CGObjC.cpp` related to unaligned
atomics.

Because the synchronization strategy (native vs. objc_copyStruct) is
baked into the ABI for compiled frameworks, it can essentially never be
changed for existing architectures like x86 without breaking backwards
compatibility.
DeltaFile
+3-16clang/lib/CodeGen/CGObjC.cpp
+2-5clang/test/CodeGenObjC/property-aggregate.m
+5-212 files

LLVM/project 4c14735llvm/lib/Transforms/Vectorize LoopVectorize.cpp

[LoopVectorize] Verify the function once per pass, not once per loop (#216448)

processLoop verifies the whole function once per vectorized loop, making
LoopVectorize quadratic in the number of loops per function on assertion
builds. In an `opt -O3` run the verifier accounts for 59% of the
instructions for a function with 800 vectorizable loops, and 5.6% for
SingleSource/Benchmarks/Linpack/linpack-pc.c.

Move the call to the end of runImpl. Assertion builds still verify what
LoopVectorize produces, but once per function instead of once per
vectorized loop, which costs 0.1-0.7% of the O3 run.

The call was added under DEBUG() in 2012 and became unconditional on
assertion builds in c9f63297e24a. 0aa75fb12faa hit the same problem in
SLPVectorizer and fixed it with EXPENSIVE_CHECKS (#48033).
DeltaFile
+5-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+5-11 files

LLVM/project 8a6ebe4llvm/include/llvm/CodeGen CFGuardLongjmp.h, llvm/lib/CodeGen CFGuardLongjmp.cpp

[NewPM] Port CFGuardLongjmp to the new pass manager

Follow the same pattern used for EHContGuardTargets: extract the pass
body into a free function, rename the legacy pass to
CFGuardLongjmpLegacy, and add a CFGuardLongjmpPass for the new pass
manager. Register it in MachinePassRegistry.def and wire it into
X86's NewPM CodeGenPassBuilder pipeline (AArch64 and ARM do not yet
have a NewPM CodeGenPassBuilder).

The pass only adds post-instruction symbols and never modifies the
CFG, so mark it CFG-preserving in both the legacy getAnalysisUsage
override and the new-PM run() return value, matching the fix applied
to EHContGuardTargets in #217843.

Assisted-by: Claude Sonnet 5
DeltaFile
+46-28llvm/lib/CodeGen/CFGuardLongjmp.cpp
+44-0llvm/test/CodeGen/X86/cfguard-longjmp.ll
+24-0llvm/include/llvm/CodeGen/CFGuardLongjmp.h
+2-2llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+1-1llvm/lib/Target/X86/X86TargetMachine.cpp
+2-0llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+119-317 files not shown
+126-3713 files

LLVM/project ada2299llvm/lib/Target/RISCV RISCVInstrInfoP.td

[RISCV] Fix size of PseudoMERGE (#218171)

This can expand to two 4-byte instructions, so mark it as size 8.
Usually it will expand to just one 4-byte instruction.

This was found in #218170.
DeltaFile
+1-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+1-01 files

LLVM/project 6e967f6llvm/include/llvm/CodeGen EHContGuardTargets.h, llvm/lib/CodeGen EHContGuardTargets.cpp

[NewPM] Port EHContGuardTargets to the new pass manager (#217843)

Adds a newPM pass for EHContGuardTargets (eh-cont-guard-targets).

- Extracts the pass's logic (which has no per-instance state) into a
shared runEHContGuardTargets free function, called by both the legacy
pass and the new pass manager pass.
- Renames the old pass with the "Legacy" suffix, and (matching the same
convention already applied to CFIInstrInserter) renames
createEHContGuardTargetsPass() to createEHContGuardTargetsLegacy() at
all three legacy call sites (X86, AArch64, ARM).
- Adds the new pass manager pass EHContGuardTargetsPass, using
RequiredPassInfoMixin: the legacy pass's runOnMachineFunction never
calls skipFunction, so it always runs unconditionally and should not be
skippable in the new PM either.
- Updates MachinePassRegistry.def and PassBuilder.
- Wires the pass into X86's newPM pipeline, replacing an existing TODO
inside the already-correct TT.isOSWindows() conditional in
X86CodeGenPassBuilder.cpp. AArch64 and ARM have no newPM

    [7 lines not shown]
DeltaFile
+46-30llvm/lib/CodeGen/EHContGuardTargets.cpp
+25-0llvm/include/llvm/CodeGen/EHContGuardTargets.h
+2-2llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
+1-1llvm/lib/Target/X86/X86TargetMachine.cpp
+1-1llvm/lib/Target/ARM/ARMTargetMachine.cpp
+2-0llvm/test/CodeGen/X86/llc-pipeline-npm.ll
+77-347 files not shown
+84-3913 files

LLVM/project a0dba47llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 narrowed-reduction-chain-use.ll

[SLP]Fix erasing scalars used by narrowed reduction chain instructions

Narrowed reduction chain instructions may use non-root tree scalars;
clear such uses before erasing the scalars.

Fixes https://github.com/llvm/llvm-project/pull/216062#issuecomment-5381262165

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/218174
DeltaFile
+60-0llvm/test/Transforms/SLPVectorizer/AArch64/narrowed-reduction-chain-use.ll
+20-3llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+80-32 files

LLVM/project 2d47daa.github/workflows release-tasks.yml release-documentation.yml

workflows: Merge release-doxygen into release-documenation (#214366)

These two workflows use the same script and have the same structure,
so it's easier just to have one job that builds both.
DeltaFile
+0-130.github/workflows/release-doxygen.yml
+40-13.github/workflows/release-documentation.yml
+0-16.github/workflows/release-tasks.yml
+40-1593 files

LLVM/project fa5249a.github/workflows release-documentation.yml

Fix step id
DeltaFile
+3-3.github/workflows/release-documentation.yml
+3-31 files

LLVM/project 6e2ed23llvm/docs/CommandGuide llvm-reduce.rst

[llvm-reduce][Docs] Add docs on --delta-passes option (#218158)
DeltaFile
+10-4llvm/docs/CommandGuide/llvm-reduce.rst
+10-41 files

LLVM/project e23ec3f.ci/metrics metrics.py

[CI] Add metrics for MacOS jobs (#218154)
DeltaFile
+1-0.ci/metrics/metrics.py
+1-01 files

LLVM/project 33b5894llvm/include/llvm/Analysis BlockFrequencyInfoImpl.h, llvm/test/Analysis/BlockFrequencyInfo irreducible.ll

[BFI] Preserve zero-mass exits in solveIrreducibleMass (#218140)

Fixes #217740.

Keep zero-mass exits in `solveIrreducibleMass`.

Although their mass is zero, these exits are later reused when building
enclosing irreducible SCCs... dropping them can change SCC membership
and eventually trigger the "**unhandled irreducible control flow**"
assertion.

---------

Co-authored-by: Fangrui Song <i at maskray.me>
DeltaFile
+39-0llvm/test/Analysis/BlockFrequencyInfo/irreducible.ll
+0-2llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+39-22 files

LLVM/project f2f8569llvm/test/Transforms/SLPVectorizer/X86 interchangeable-cmp-predicates.ll

[SLP][NFC]Add tests for interchange compares, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/218169
DeltaFile
+359-0llvm/test/Transforms/SLPVectorizer/X86/interchangeable-cmp-predicates.ll
+359-01 files

LLVM/project 2ef00dbllvm/lib/Target/RISCV CMakeLists.txt RISCVPostRAExpandPseudoInsts.cpp

[RISCV][NFC] Split PreRAExpandPseudo to new file (#218167)

Also update the comments on all the other ExpandPseudo passes, to
clarify where they are run in the pipeline, and that there are many
target-specific pseudo expansion passes, in addition to the generic
passes.
DeltaFile
+278-0llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp
+4-250llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+3-3llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+3-3llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+1-0llvm/lib/Target/RISCV/CMakeLists.txt
+289-2565 files

LLVM/project 3ff8254clang/include/clang/AST GlobalDecl.h, clang/include/clang/Basic FileManager.h

[clang] Trim large(-ish) includes from common headers (#216946)

Several widely included Clang headers pull in whole subsystems to name
types they only use through pointers, references, or declarations.
Because these headers sit underneath SourceManager.h, Sema.h, and
CompilerInstance.h, nearly every translation unit in Clang pays for
them, as well as many down-stream users of Clang.

Translation units across Clang and clang-tools-extra that were relying
on any of the removed transitive includes now include what they use.

Out-of-tree code that was relying on any of these transitive includes
needs the same treatment. The failure is an incomplete type or an
undeclared identifier at the point of use, and the fix is to include the
header that declares it; llvm/Support/VirtualFileSystem.h and AST/Attr.h
account for most of it, since Basic/FileManager.h and AST/GlobalDecl.h
are reached from so much of Clang.

Measured on a random 90 translation unit sample of clang's 1006 library

    [4 lines not shown]
DeltaFile
+23-26clang/include/clang/AST/GlobalDecl.h
+46-0clang/lib/AST/GlobalDecl.cpp
+5-20clang/include/clang/Frontend/FrontendAction.h
+24-1clang/lib/Frontend/FrontendAction.cpp
+14-10clang/include/clang/Basic/FileManager.h
+15-0clang/lib/Basic/TargetInfo.cpp
+127-5779 files not shown
+240-8685 files

LLVM/project 0f9791cllvm/lib/CodeGen/GlobalISel IRTranslator.cpp, llvm/test/CodeGen/AArch64/GlobalISel irtranslator-subvector.ll

[AArch64][GlobalISel] Use integer types for scalable vector insert / extract index. (#218150)
DeltaFile
+6-6llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
+2-2llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+8-82 files

LLVM/project 3cd29d9clang/docs ReleaseNotes.md, clang/lib/Sema SemaExpr.cpp

[Clang] Fixed an assertion caused by Microsoft integer literals exceeding the maximum value (#212743)

Rewrites the truncation logic for Microsoft integer literals.

Fix #212504

---------

Co-authored-by: A. Jiang <de34 at live.cn>
DeltaFile
+23-2clang/test/SemaCXX/ms_integer_suffix.cpp
+4-1clang/lib/Sema/SemaExpr.cpp
+1-0clang/docs/ReleaseNotes.md
+28-33 files

LLVM/project 8f8fea3llvm/include/llvm/ProfileData SampleProf.h, llvm/lib/ProfileData SampleProf.cpp SampleProfReader.cpp

[ProfileData] Use SortedVectorMap for BodySampleMap, TypeCountMap, and CallsiteTypeMap (#216530)

This patch switches several maps in the sample profile reader/writer
from std::map to SortedVectorMap.

The memory efficiency of SortedVectorMap improves multiple performance
metrics:

Profile merging:

Metric               Baseline  SortedVectorMap   Change
-------------------------------------------------------
Wall Clock            200.22s          157.73s   -21.2%
User Time             108.93s           92.79s   -14.8%
System Time            70.34s           45.83s   -34.8%
Total CPU Time        179.27s          138.62s   -22.7%
Peak RSS            58.42 GiB        48.11 GiB   -17.6%
Minor Page Faults  28,705,225       17,904,042   -37.6%
Major Page Faults           7                0  -100.0%

    [4 lines not shown]
DeltaFile
+59-24llvm/include/llvm/ProfileData/SampleProf.h
+4-0llvm/lib/ProfileData/SampleProfReader.cpp
+1-0llvm/tools/llvm-profdata/llvm-profdata.cpp
+1-0llvm/lib/ProfileData/SampleProf.cpp
+65-244 files

LLVM/project fae36f2llvm/lib/Target/AArch64/GISel AArch64CallLowering.cpp, llvm/test/CodeGen/AArch64/GlobalISel irtranslator-vararg.ll

[AArch64][GlobalISel] Use f128 types for varargs registers. (#218166)
DeltaFile
+16-16llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vararg.ll
+1-1llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+17-172 files

LLVM/project bb884c8llvm/include/llvm/Support GenericDomTree.h, llvm/lib/Transforms/Scalar NewGVN.cpp

[DomTree] Make addChild/removeChild private, update NewGVN caller (#218164)

NewGVN's value numbering loop converges more quickly when blocks are
processed in a reverse post order. The code additionally ensures a
property the pass does not need (commit 6658cc9ead67 in 2016): in a
preorder of the dominator tree the instructions dominated by a block are
contiguous.

Use the default RPO and drop addChild/removeChild callers, so that the
two members can be made private. `opt -passes=newgvn` slightly
decreases.
DeltaFile
+22-24llvm/include/llvm/Support/GenericDomTree.h
+3-31llvm/lib/Transforms/Scalar/NewGVN.cpp
+25-552 files

LLVM/project 8dba613mlir/lib/Conversion/VectorToXeGPU VectorToXeGPU.cpp, mlir/lib/Conversion/XeGPUToXeVM XeGPUToXeVM.cpp

[mlir][xegpu] Lower dynamic high-D nd load/store via base-pointer fold (#215711)

Reworks lowering of >2D (batched)
`xegpu.create_nd_tdesc`/`load_nd`/`store_nd`/ `prefetch_nd` (batched
GEMM, rank-4 flash-attention) to keep the full high-D memref as the
descriptor source and carry the leading (batch) offsets as a row offset
into a flattened 2D plane, instead of slicing a per-batch
`memref.subview` during blocking.
 
For example, the wg-level IR read a 4d vector out of a dynamic shaped
memref.
 ```mlir
    %0 = vector.transfer_read %source[%i, %j, %k, %l], %c0
{in_bounds = [true, true, true, true]} : memref<?x?x8x16xf32>,
vector<2x4x8x16xf32>
 ```
This lowers with no subview — the full memref is the descriptor source
and all four offsets stay on the load:


    [35 lines not shown]
DeltaFile
+59-195mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
+171-45mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
+89-52mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
+42-51mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
+4-54mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
+32-20mlir/test/Conversion/VectorToXeGPU/transfer-write-to-xegpu.mlir
+397-41717 files not shown
+714-54523 files

LLVM/project 73484e4llvm/lib/Target/RISCV RISCVCodeGenPassBuilder.cpp RISCVPassRegistry.def, llvm/test/CodeGen/RISCV expand-atomic-pseudo.mir

[RISCV] Port ExpandAtomicPseudo to NewPM (#218161)
DeltaFile
+38-22llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+44-0llvm/test/CodeGen/RISCV/expand-atomic-pseudo.mir
+9-2llvm/lib/Target/RISCV/RISCV.h
+2-2llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+96-272 files not shown
+98-278 files

LLVM/project 7e5edd5llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/test/CodeGen/AMDGPU addrspacecast-widen-vector.ll

SelectionDAG: Fix widening of vector addrspacecast results (#217898)

WidenVecRes_ADDRSPACECAST unconditionally called GetWidenedVector on the
source operand, which asserts the operand is itself in the
widened-vector
map. When the source vector type does not require widening (e.g. a
<5 x ptr addrspace(3)> cast to <5 x ptr>, where the source is padded
rather than widened), this asserted or crashed. Handle the non-widened
source by padding it up to the widened element count instead.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+64-0llvm/test/CodeGen/AMDGPU/addrspacecast-widen-vector.ll
+16-2llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+80-22 files

LLVM/project fc9f8ecllvm/lib/Transforms/Vectorize VPlanUtils.h VPlanUtils.cpp, llvm/test/Transforms/LoopVectorize/X86 cost-model.ll

[VPlan] Expand sequential/regular UMin SCEVs in VPSCEVExpander. (#209786)

Add support for expanding SequentialUMinExpr SCEV expressions in
VPSCEVExpander.

For regular UMin expressions, the expansion unconditionally expands &
executes all operands, while the semantics of sequential UMin only
require the first operand to be evaluated unconditionally.

For sequential UMin expressions, we need to make sure potentially
UB/poison generating operands must be accounted for. Matching IR SCEV
expander, make sure that divisors of UDiv are poison-free and non-zero
inside sequential UMin. Similarly, freeze all operands other than the
first, to avoid poison from propagating.

PR: https://github.com/llvm/llvm-project/pull/209786
DeltaFile
+33-7llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+4-0llvm/lib/Transforms/Vectorize/VPlanUtils.h
+2-1llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+39-83 files

LLVM/project 4f1d586llvm/lib/Target/RISCV RISCVPassRegistry.def RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV postra-expand-pseudo.mir

[RISCV] Port Post-RA Expand Pseudos to NewPM (#218080)

Assisted-by: AI
DeltaFile
+50-26llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+27-0llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir
+9-2llvm/lib/Target/RISCV/RISCV.h
+2-2llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-1llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+2-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+91-313 files not shown
+94-329 files

LLVM/project 0008a69llvm/lib/Transforms/Scalar InferAddressSpaces.cpp, llvm/test/Transforms/InferAddressSpaces/AMDGPU phi-cycle-uninitialized-addrspace.ll

[InferAddressSpaces] Lower stuck uninitialized values to flat before rewriting (#215525)
DeltaFile
+272-0llvm/test/Transforms/InferAddressSpaces/AMDGPU/phi-cycle-uninitialized-addrspace.ll
+64-25llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
+336-252 files

LLVM/project 1411f47llvm/lib/Target/DirectX DXIL.td DXILOpLowering.cpp, llvm/test/CodeGen/DirectX CreateHandleHeap.ll CreateHandleHeap-NURI.ll

[DirectX] Lower `llvm.dx.resource.handlefromheap` intrinsic (#216459)

Add lowering of `llvm.dx.resource.handlefromheap` intrinsic. It gets
translated to DXIL ops `createHandleFromHeap` and `annotateHandle`.

For example, the intrinsic call

```llvm
%typed = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0)
    @llvm.dx.resource.handlefromheap.tdx.TypedBuffer_v4f32_1_0_0(i32 3)
```

will lower to

```llvm
%0 = call %dx.types.Handle @dx.op.createHandleFromHeap(i32 218, i32 3, i1 false, i1 false)
%1 = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle %0,
         %dx.types.ResourceProperties { i32 4106, i32 1033 })
```

    [4 lines not shown]
DeltaFile
+46-0llvm/lib/Target/DirectX/DXILOpLowering.cpp
+32-0llvm/test/CodeGen/DirectX/CreateHandleHeap.ll
+32-0llvm/test/CodeGen/DirectX/CreateHandleHeap-NURI.ll
+8-0llvm/lib/Target/DirectX/DXIL.td
+118-04 files

LLVM/project 05819ffllvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/InstSimplify urem-sub-nonzero.ll

[InstSimplify] Simplify nonzero comparisons involving X urem Y via X u>= Y (#216072)

This teaches ValueTracking that `X` and `X urem Y` are non-equal when a
dominating condition implies `X u>= Y`.

It also handles cases where `X u>= Y` can be proven structurally, such
as when `X` is an `add nuw` of `A` and `Y`.

For a defined `urem`, let `R = X urem Y`. Then:

```text
R == X  <=>  X u< Y
R != X  <=>  X u>= Y
```

This allows InstSimplify's existing nonzero reasoning to simplify
comparisons equivalent to `(X - R) != 0`, including:

- `(X - R) u>= 1` and `(X - R) u< 1`

    [8 lines not shown]
DeltaFile
+412-0llvm/test/Transforms/InstSimplify/urem-sub-nonzero.ll
+22-0llvm/lib/Analysis/ValueTracking.cpp
+434-02 files

LLVM/project ef22de8llvm/include/llvm/Transforms/Coroutines CoroShape.h, llvm/lib/Transforms/IPO AttributorAttributes.cpp

[Transforms] Remove dead declarations (#218110)

initABI: The corresponding function definition was removed on October 3,
2024 in commit 66227bf7ee2cd674e0306d9a1e9f1d86bc75123f.

AccessAsInstructionInfo: The last use was removed on March 8, 2022 in
commit e8fadafe774c7e601129be50cedce1dd20843cea.
DeltaFile
+0-9llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+0-2llvm/include/llvm/Transforms/Coroutines/CoroShape.h
+0-112 files

LLVM/project a4402bdmlir/lib/Bindings/Python IRCore.cpp, mlir/lib/CAPI/IR ExtensibleDialect.cpp

[MLIR][Python] Add effect and speculatability specifiers for Python-defined ops (#216773)

This PR adds standalone effect and speculatability specifiers for
Python-defined operations.

`NoMemoryEffect` and `AlwaysSpeculatable`, previously nested under
`Pure`, are now public, and `RecursivelySpeculatable` is added. `Pure`
remains a shorthand for attaching `NoMemoryEffect` and
`AlwaysSpeculatable`.

This also exposes `OpTrait::HasRecursiveMemoryEffects` through the C API
and Python bindings as `ir.RecursiveMemoryEffectsTrait`, allowing
region-bearing Python-defined operations to derive their memory effects
from nested operations:

```python
class LeafOp(
    TestDialect.Operation,
    name="leaf",

    [22 lines not shown]
DeltaFile
+494-0mlir/test/python/ir/memory_effects_op_interface.py
+0-357mlir/test/python/dialects/memory_effects_op_interface.py
+71-0mlir/test/python/dialects/ext.py
+48-9mlir/lib/Bindings/Python/IRCore.cpp
+37-16mlir/python/mlir/dialects/ext.py
+15-0mlir/lib/CAPI/IR/ExtensibleDialect.cpp
+665-3822 files not shown
+682-3828 files