LLVM/project 4f3eb80llvm/lib/Target/Xtensa/MCTargetDesc XtensaInstPrinter.cpp XtensaMCCodeEmitter.cpp

[Xtensa] Call isUInt<8> in range-check asserts (#204731)

`printOffset8m8_AsmOperand` and `getSelect_256OpValue` assert on
`isUInt<8>` without calling it, so the expression takes the function's
address and the range check never runs. This also trips
`-Werror,-Wpointer-bool-conversion` in builds with assertions enabled.
Pass the operand value so the bound is actually checked.
DeltaFile
+2-1llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
+1-1llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
+3-22 files

LLVM/project 31f308ellvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp SIISelLowering.cpp

[AMDGPU] Guard more intrinsics with target features
DeltaFile
+1-51llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+0-42llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+0-24llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+15-2llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+4-4llvm/test/CodeGen/AMDGPU/unsupported-av-store.ll
+4-4llvm/test/CodeGen/AMDGPU/unsupported-av-load.ll
+24-12712 files not shown
+45-14318 files

LLVM/project c1037feclang/lib/CodeGen CodeGenAction.cpp, llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp

[RFC][CodeGen] Add generic target feature checks for intrinsics

This PR adds target-independent infrastructure for annotating LLVM intrinsics
with required subtarget feature expressions.

It introduces a TargetFeatures string field to intrinsic TableGen records.
TableGen emits an intrinsic-to-feature mapping table.

Both SelectionDAG and GlobalISel now perform this check before lowering target
intrinsics. This allows targets to opt in by annotating intrinsic definitions
directly, rather than adding custom checks during lowering, legalization, or
instruction selection.

This PR uses one AMDGPU intrinsic as an example.
DeltaFile
+96-3llvm/lib/MC/MCSubtargetInfo.cpp
+37-0clang/lib/CodeGen/CodeGenAction.cpp
+36-0llvm/lib/IR/DiagnosticInfo.cpp
+33-1llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+28-0llvm/test/TableGen/intrinsic-target-features.td
+25-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+255-414 files not shown
+391-920 files

LLVM/project d845955llvm/lib/IR Verifier.cpp VerifierAMDGPU.cpp, llvm/test/Verifier callbr-intrinsic.ll

[RFC][IR] Extract AMDGPU-specific verification logic into `VerifierAMDGPU.cpp`

`Verifier.cpp` is large and already mixes generic IR verification with
target-specific checks. We also have a growing amount of AMDGPU verifier logic
downstream, which would all end up in the same file if we don't address this,
and that is not ideal.

This patch extracts AMDGPU-specific verification logic into a separate
`VerifierAMDGPU.cpp` file, with shared infrastructure (`VerifierSupport`) moved
into `VerifierInternal.h`.

This is purely a code organization change, not a target-dependent IR verifier.
All checks remain compiled and linked into `LLVMCore` regardless of the target
triple. The extracted functions are called unconditionally at well-defined
extension points in `Verifier.cpp`, and each function internally gates on
target-specific conditions (for example, triple checks or intrinsic IDs) as
needed. The file is strictly limited to AMDGPU-specific IR constructs (amdgcn
intrinsics, AMDGPU module flags, etc.), and does not contain generic IR rules
that vary by target.

    [10 lines not shown]
DeltaFile
+23-530llvm/lib/IR/Verifier.cpp
+401-0llvm/lib/IR/VerifierAMDGPU.cpp
+233-0llvm/lib/IR/VerifierInternal.h
+6-6llvm/test/Verifier/callbr-intrinsic.ll
+1-0llvm/lib/IR/CMakeLists.txt
+1-0llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
+665-5366 files

LLVM/project e0cc08dclang/lib/AST/ByteCode InterpBuiltin.cpp, clang/lib/Headers avx512vnniintrin.h avx512vlvnniintrin.h

[clang][x86] Add constexpr support for VNNI intrinsics (#190549)

Fixes #161340.

It adds constexpr support for VNNI
intrinsics by modifying their header files, their TableGen definitions,
how they're interpreted in InterpBuiltin.cpp and ExprConstant.cpp, and
adds unit tests in the headers' corresponding unit test files.
DeltaFile
+190-1clang/test/CodeGen/X86/avx512vlvnni-builtins.c
+162-0clang/test/CodeGen/X86/avxvnni-builtins.c
+86-1clang/test/CodeGen/X86/avx512vnni-builtins.c
+74-1clang/lib/AST/ByteCode/InterpBuiltin.cpp
+32-35clang/lib/Headers/avx512vnniintrin.h
+29-34clang/lib/Headers/avx512vlvnniintrin.h
+573-723 files not shown
+659-1189 files

LLVM/project a12b7afllvm/lib/Target/X86 X86InstrMisc.td, llvm/test/CodeGen/X86 bmi.ll

[X86] Select BLSI for i8 operands (#202344) (#204746)

Adds a tablegen pattern to select BLSI 32 for `and (neg x), x` at i8.

Fixes #202344
DeltaFile
+94-0llvm/test/CodeGen/X86/bmi.ll
+12-1llvm/lib/Target/X86/X86InstrMisc.td
+106-12 files

LLVM/project 9b36e4forc-rt/include/orc-rt QueueingRunner.h, orc-rt/unittests QueueingTaskDispatcherTest.cpp SessionTest.cpp

[orc-rt] Replace TaskDispatcher with Session-supplied wrapper-runner. (#204965)

TaskDispatcher was only used to run wrapper-function calls that
originated from the controller. Replace it with a callable type:

  Session::RunWrapperCall = move_only_function<void(
      orc_rt_SessionRef, uint64_t, orc_rt_WrapperFunctionReturn,
      orc_rt_WrapperFunction, WrapperFunctionBuffer)>

Each call carries an outstanding ManagedCodeTaskGroup token; the runner
must eventually invoke Fn (which calls Return) or call Return directly
to bail out, otherwise Session shutdown blocks indefinitely.

Clients can supply any callable that satisfies the contract above. The
new QueueingRunner and ThreadPoolRunner classes (replacing
QueueingTaskDispatcher and ThreadPoolTaskDispatcher, respectively) are
provided as off-the-shelf options.
DeltaFile
+0-291orc-rt/unittests/QueueingTaskDispatcherTest.cpp
+85-141orc-rt/unittests/SessionTest.cpp
+153-0orc-rt/unittests/ThreadPoolRunnerTest.cpp
+133-0orc-rt/unittests/QueueingRunnerTest.cpp
+0-110orc-rt/unittests/ThreadPoolTaskDispatcherTest.cpp
+82-0orc-rt/include/orc-rt/QueueingRunner.h
+453-54219 files not shown
+668-98425 files

LLVM/project 7b85647llvm/test/CodeGen/AArch64 inline-asm-prepare.ll

[CodeGen][NFC] Use llc instead of opt
DeltaFile
+1-3llvm/test/CodeGen/AArch64/inline-asm-prepare.ll
+1-31 files

LLVM/project 4417256llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.cpp, llvm/test/Transforms/LoopVectorize/AArch64 vplan-native-outer-loop-wide-type.ll

[LV] Avoid zero-width VF in computeVPlanOuterloopVF. (#204918)

RegSize / WidestType may be 0 for types wider than the vector register
size. Clamp VF to at least 1 (scalar), to avoid a crash. This matches
inner loop behavior.
DeltaFile
+59-0llvm/test/Transforms/LoopVectorize/AArch64/vplan-native-outer-loop-wide-type.ll
+1-1llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+60-12 files

LLVM/project 71c2febflang/test/Integration split-lto-unit-2.f90

Support for -fsplit-lto-unit option in flang driver (#204904)

Fix for buildbot failures in #202858

This commit fixes a regression introduced in commit
12aefe26cedd9a8f94546cc1f2be285cfddcc861 (Support for -fsplit-lto-unit
option in flang driver). When the compiler is built only for aarch64 one
of the testcase failed.

Added explicit check %if x86-registered-target for this testcase to
resolve the issue.
DeltaFile
+6-6flang/test/Integration/split-lto-unit-2.f90
+6-61 files

LLVM/project 8947e49llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine assume.ll

[InstCombine] Move alignment assumptions to the base of constant offset GEPs (#204602)
DeltaFile
+14-0llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+3-6llvm/test/Transforms/InstCombine/assume.ll
+17-62 files

LLVM/project f42072ellvm/include/llvm/Support KnownBits.h, llvm/lib/Analysis ValueTracking.cpp

[Analysis] Add `KnownBits` optimization for `pdep` and `pext` (#204223)

Fixes #204136
DeltaFile
+91-0llvm/test/Analysis/ValueTracking/knownbits-pext.ll
+89-0llvm/test/Analysis/ValueTracking/knownbits-pdep.ll
+65-0llvm/lib/Support/KnownBits.cpp
+3-9llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+10-0llvm/lib/Analysis/ValueTracking.cpp
+6-0llvm/include/llvm/Support/KnownBits.h
+264-91 files not shown
+266-97 files

LLVM/project 7376a70compiler-rt/lib/tsan/rtl tsan_platform.h

[tsan] fit Go/s390x mapping under QEMU (#204503)

QEMU linux-user first tries guest_base=0. In that identity-mapped mode,
fixed guest mappings use the same host addresses. On an x86-64 host
with four-level page tables, the Go/s390x meta shadow starts at
144 TiB, beyond the 128 TiB userspace limit, and its mmap fails with
ENOMEM during TSan initialization.

Move the meta shadow down by 32 TiB to
[0x700000000000, 0x780000000000), restoring the 16 TiB gap after the
shadow and placing all Go/s390x TSan regions below 2^47. Correct the
mapping comment's shadow size and ratio.

Failure report and native s390x comparison:
https://github.com/golang/go/issues/67881

QEMU identity guest-base selection:

https://github.com/qemu/qemu/blob/v10.2.3/linux-user/elfload.c#L1036-L1042

    [9 lines not shown]
DeltaFile
+8-5compiler-rt/lib/tsan/rtl/tsan_platform.h
+8-51 files

LLVM/project 2978e2fllvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/CodeGen/X86 atomic-load-store.ll

Merge branch 'main' into users/ikudrin/clang-findallocationfunction-simplify
DeltaFile
+203-329llvm/test/CodeGen/X86/atomic-load-store.ll
+214-266llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+366-0llvm/test/tools/llvm-objcopy/MachO/linkedit-alignment.test
+241-0llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
+232-0llvm/test/Transforms/VectorCombine/X86/shuffle-chain-reduction-subvector.ll
+182-2llvm/test/Transforms/InstCombine/or.ll
+1,438-597120 files not shown
+4,268-1,755126 files

LLVM/project 5066d3aclang/include/clang/Sema Sema.h, clang/lib/Sema SemaExprCXX.cpp SemaOverload.cpp

fixup! Streamline overload resolution
DeltaFile
+202-175clang/lib/Sema/SemaExprCXX.cpp
+2-2clang/include/clang/Sema/Sema.h
+1-1clang/lib/Sema/SemaOverload.cpp
+205-1783 files

LLVM/project 9d6c686orc-rt/include/orc-rt Session.h, orc-rt/lib/executor Session.cpp

[orc-rt] Sink Session::sendWrapperResult into Session.cpp. NFC. (#204956)

This function is never called inline (except by Session::wrapperReturn,
which is also in Session.cpp), so there's no need for it to be in the
header.
DeltaFile
+1-6orc-rt/include/orc-rt/Session.h
+7-0orc-rt/lib/executor/Session.cpp
+8-62 files

LLVM/project e1f65fallvm/lib/Transforms/Utils SimplifyCFG.cpp, llvm/test/Transforms/SimplifyCFG convergent-loop-header.ll

[SimplifyCFG] Avoid threading loop-header branches in convergent functions

SimplifyCFG can fold a conditional branch when the condition is known from
a predecessor. When the destination is a loop header in a convergent function,
this can change the dynamic convergence structure of the loop even though the
scalar CFG rewrite is otherwise valid.

Skip this fold for loop-header branches in convergent functions so convergent
control flow is preserved.

Fixes ROCM-26496.
DeltaFile
+6-4llvm/test/Transforms/SimplifyCFG/convergent-loop-header.ll
+4-1llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+10-52 files

LLVM/project 0cddd5fllvm/test/Transforms/SimplifyCFG convergent-loop-header.ll

[NFC] Pre-commit a test case for a SimplifyCFG issue
DeltaFile
+50-0llvm/test/Transforms/SimplifyCFG/convergent-loop-header.ll
+50-01 files

LLVM/project ec56065.github/workflows new-prs.yml

workflows/new-prs: Remove obsolete code (#204955)

This was left over after 57e4352de0d2617bae1656dc2e2b3ca430e83c4c and
causing the jobs to fail.
DeltaFile
+0-1.github/workflows/new-prs.yml
+0-11 files

LLVM/project afac572clang/test CMakeLists.txt

[clang] Add clang-format-check-format instead to CLANG_TEST_DEPS (#204908)

Ensure that clang-format doesn't break the existing format of its own
source.

Reverts #199169 and #199638.
DeltaFile
+1-5clang/test/CMakeLists.txt
+1-51 files

LLVM/project 61d601ellvm/lib/Target/AMDGPU GCNVOPDUtils.cpp

[AMDGPU][VOPD] Cache load reachability checks in VOPDpairing (#204854)

#201930 causes significant compilation time regression when building
ROCm mathlibs.

Major regressions are caused by repeated queries to `DAG->IsReachable`
to detect possible scalarisation of loads when fusing a pair of
VOPD-capable instructions.
This patch caches the set of reachable loads for every potentially
hazardous load instruction to avoid the need to invoke
`DAG->IsReachable` at all.
DeltaFile
+74-48llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+74-481 files

LLVM/project 959f069llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Keep split vector atomic store value in a vector register (#201566)

When the value of an ATOMIC_STORE has a vector type whose legalization
action is split (e.g. <4 x half>/<4 x bfloat> on X86 without F16C),
SplitVecOp_ATOMIC_STORE bitcast the value straight to a scalar integer
spanning the memory width. For a split vector that bitcast is expanded
element by element, reassembling the value in GPRs (a long pextrw/shl/or
sequence) before the store.

Instead, keep the value in a vector register when a legal vector form
exists: reinterpret it as a same-shaped integer-element vector (an FP
element type may have no legal vector form, e.g. bfloat on SSE2, while
the integer-of-element-size form does), widen that to a legal vector,
and extract the low integer element of the memory width. This issues the
store directly from a vector register (a single MOVQ/MOVD on X86),
matching the widen-path codegen already produced on AVX targets. Falls
back to the scalar bitcast when no suitable legal vector type exists.

Stacked on top of https://github.com/llvm/llvm-project/pull/197861; and
below of #197862.
DeltaFile
+203-329llvm/test/CodeGen/X86/atomic-load-store.ll
+33-6llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+236-3352 files

LLVM/project 3c5f0c2llvm/test/Transforms/LoopVectorize/VPlan/AArch64 vplan-memory-op-decisions.ll

[VPlan] Add memory op decision test for scalarizing loads. (NFC) (#204949)

VPlan printing tests for
https://github.com/llvm/llvm-project/pull/196842
DeltaFile
+175-0llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
+175-01 files

LLVM/project 5502491llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/AArch64 transform-narrow-interleave-to-widen-memory-with-wide-ops.ll transform-narrow-interleave-to-widen-memory-with-wide-ops-and-casts.ll

[VPlan] Properly check predicates and types in canNarrowOps. (#204948)

Update canNarrowOps to properly check the types of all members match.
Similarly, for recipes with predicates, the predicates must match.
DeltaFile
+241-0llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
+176-0llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops-and-casts.ll
+6-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+423-23 files

LLVM/project d0c2776llvm/test/Analysis/BasicAA recphi.ll phi-and-select.ll

[BasicAA] Add additional tests with GEPs with phi/select pointer ops (NFC) (#204947)
DeltaFile
+92-0llvm/test/Analysis/BasicAA/recphi.ll
+27-0llvm/test/Analysis/BasicAA/phi-and-select.ll
+21-0llvm/test/Analysis/BasicAA/phi-aa.ll
+140-03 files

LLVM/project a891d7bllvm/lib/ObjCopy/MachO MachOLayoutBuilder.cpp MachOObjcopy.cpp

[llvm-objcopy][MachO] Use alignToPowerOf2 instead of alignTo (#204033)

During the review of #203680 I noticed that Mach-O objcopy files seems
to use `alignTo` and import `Alignment.h` to align some offsets to page
boundaries and similar requirements. However, the `alignTo` in
`Alignment.h`, while being intended for powers of 2, requires using an
alignment of type `llvm::Align`, and needs explicit conversion from
`uint64_t` and similar. Single `Alignment.h` includes `MathExtras.h`,
the `alignTo` being invoked ends up being a generic `alignTo` that does
not require powers of 2, and perform divisions and multiplications.
While some of those might be optimized by the compiler into efficient
power of 2 operations, there's an explicit `alignToPowerOf2` version
that is optimized and asserts the alignment is a power of 2 (with
asserts enabled). Since all the alignments should be power of 2 for the
Mach-O binary format, change from `alignTo` to `alignToPowerOf2` to make
the fact more visible (and get the extra safety net of the assertions).

As expected, the test suite of objcopy doesn't show any regressions, but
I have not done a performance benchmark around this either.
DeltaFile
+15-13llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
+4-3llvm/lib/ObjCopy/MachO/MachOObjcopy.cpp
+2-2llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.h
+21-183 files

LLVM/project 18c1cbcllvm/lib/ObjCopy/MachO MachOLayoutBuilder.cpp MachOWriter.cpp, llvm/test/tools/llvm-objcopy/MachO linkedit-alignment.test symbol-table.test

[llvm-objcopy][MachO] Align __LINKEDIT entries to pointer size (#203680)

Align Mach-O __LINKEDIT entries to the target pointer size when building
the tail layout. This matches the behavior of ld64 and lld-macho.

dyld on macOS 27 rejects loading dylibs with misaligned __LINKEDIT
entries.

See #203678 for details and the motivation of this fix.

AI Tool Use Disclosure:

Regarding the PR and the linked issue, I have personally wrote every
single part of the PR by myself, and have/ran/verified every single part
of the issue report as well without any AI tool usage.

I have used LLM-based coding agents only for debugging purposes, e.g. to
figure out why the dylib was not loading (from the original bug report),
and figuring out how to build, run, and test my local `llvm-objcopy`.
DeltaFile
+366-0llvm/test/tools/llvm-objcopy/MachO/linkedit-alignment.test
+51-34llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
+30-12llvm/lib/ObjCopy/MachO/MachOWriter.cpp
+2-2llvm/test/tools/llvm-objcopy/MachO/symbol-table.test
+2-1llvm/test/tools/llvm-objcopy/MachO/linkedit-order-1.test
+2-1llvm/test/tools/llvm-objcopy/MachO/linkedit-order-2.test
+453-506 files

LLVM/project cb85dfellvm/lib/Transforms/Vectorize VPlanUtils.cpp, llvm/test/Transforms/LoopVectorize shl-shift-amount-out-of-range-scev.ll

[VPlan] Skip shl->mul SCEV rewrite for out-of-range shift amounts. (#204921)

getSCEVExprForVPValue rewrites `shl x, c` as `x * (1 << c)` using
ScalarEvolution::getPowerOfTwo, which asserts that the power is less
than the type's bit width.

Only perform the rewrite when the shift amount is less than the
operand's bit width, to avoid assertion.
DeltaFile
+65-0llvm/test/Transforms/LoopVectorize/shl-shift-amount-out-of-range-scev.ll
+5-2llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+70-22 files

LLVM/project b9c334dllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 insertvalue-reordered-operands.ll

[SLP] Fix scheduling crash for reordered insertvalue buildvector nodes

Insertvalue nodes keep scalars in program order but reorder operands, like
stores. Remap the operand lane via ReorderIndices for InsertValueInst (not
just StoreInst) in scheduling and the copyable helpers, fixing the
"Operand not found" assertion.

Fixes https://github.com/llvm/llvm-project/pull/200274#issuecomment-4753792761

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/204941
DeltaFile
+62-0llvm/test/Transforms/SLPVectorizer/X86/insertvalue-reordered-operands.ll
+6-5llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+68-52 files

LLVM/project 2df672allvm/include/llvm/Support WithColor.h raw_ostream.h, llvm/utils/FileCheck FileCheck.cpp

[FileCheck] Use default colors in input dumps

This patch makes two improvements to colors used in FileCheck input
dumps:

1. Without this patch, input line numbers and ellipses have a
   foreground color of black, which is hard to see in a terminal with
   a dark color theme.  This patch changes that to the terminal's
   default color.
2. Without this patch, the input text is accidentally set to bold when
   neither `-v` or `-vv` is specified.  Perhaps I never noticed
   because I tend to always use `-vv`.  This patch changes that to use
   the terminal's default color.

Case 2 exposes a problem with LLVM's color implementation.  Without
this patch, the call to `WithColor`'s constructor actually specifies
bold as `false`, but `WithColor` ignores that when the color is
`SAVEDCOLOR`.  While it seems like that should be fixed, I am
concerned about the impact of such a fix on other tools that might

    [12 lines not shown]
DeltaFile
+14-4llvm/utils/FileCheck/FileCheck.cpp
+4-0llvm/include/llvm/Support/WithColor.h
+2-0llvm/include/llvm/Support/raw_ostream.h
+20-43 files