LLVM/project 500afbdllvm/include/llvm/ExecutionEngine/JITLink ppc64.h, llvm/lib/ExecutionEngine/JITLink JITLink.cpp

[JITLink][ORC] Add ppc64 to generic stub API; use it in DLLImportDefinitionGenerator (#207968)

`getAnonymousPointerCreator` and `getPointerJumpStubCreator` provide
arch-neutral factory functions for pointer slots and PLT jump stubs, but
ppc64/ppc64le were missing from both switch tables.

Add ppc64 support: `createAnonymousPointer` maps directly, while
`createAnonymousPointerJumpStub` requires a lambda wrapper to fix the
endianness template parameter and supply _LongBranchSaveR2_ as the stub
kind (the correct default for external calls that must preserve the TOC
pointer). Callers needing a different stub kind can construct a
`PointerJumpStubCreator` lambda directly. Update
`DLLImportDefinitionGenerator::createStubsGraph` to use these
arch-neutral factories instead of calling jitlink::x86_64:: directly,
completing part of the work tracked in issue
https://github.com/llvm/llvm-project/issues/57162
DeltaFile
+21-9llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
+13-0llvm/include/llvm/ExecutionEngine/JITLink/ppc64.h
+9-0llvm/lib/ExecutionEngine/JITLink/JITLink.cpp
+43-93 files

LLVM/project 3eeed35llvm/include/llvm/ADT APInt.h, llvm/lib/Support APInt.cpp

[ADT] Mark deprecated APInt constructor deleted (#216371)

Mark deprecated APInt constructor, taking uint64_t[] deleted instead of
removing it as the comment suggests.
DeltaFile
+5-9llvm/include/llvm/ADT/APInt.h
+0-5llvm/lib/Support/APInt.cpp
+5-142 files

LLVM/project bbff70cllvm/test/CodeGen/NVPTX tcgen05-mma-collector-b.ll tcgen05-mma-sp-disable-output-lane-collector-b.ll

[NVPTX] Add tcgen05.mma kind::ti16 for sm_107f + mxf4{nvf4} for sm_107a (#215624)

Extend NVPTX `tcgen05.mma*` with `kind::ti16` for `sm_107f`.
DeltaFile
+692-0llvm/test/CodeGen/NVPTX/tcgen05-mma-ti16-kind.ll
+572-0llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-mxf4-mxf4nvf4-kind.ll
+309-0llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-collector-b.ll
+217-0llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-collector-b.ll
+212-0llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-disable-output-lane-collector-b.ll
+151-0llvm/test/CodeGen/NVPTX/tcgen05-mma-collector-b.ll
+2,153-011 files not shown
+2,320-11017 files

LLVM/project 585178dllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 intrinsic-vector-match-sve2.ll

[AArch64] Remove search size limit in VECTOR_MATCH lowering (#215786)

Any legal (64/128-bits) needle vector can be lowered to `match`.
DeltaFile
+29-0llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
+0-8llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+29-82 files

LLVM/project 23e0cbelldb/source/Expression DWARFExpression.cpp, lldb/unittests/Expression DWARFExpressionTest.cpp

[LLDB] fix lldb breg adress width (#216291)

`DW_OP_breg0..31` and `DW_OP_bregx` preserved the scalar width supplied
by the register backend and added their displacement as a `uint64_t`. On
32-bit targets this could leave a 64-bit value on the expression stack,
so later generic address arithmetic did not wrap at the target address
size.

Perform the register-plus-offset calculation using the evaluator's
address-sized generic representation. This keeps `DW_OP_breg*` results
at the target address width without changing shared register reading or
the generic
operand compatibility rule.

Add unit tests for both compact and extended breg opcodes. They cover a
32-bit register value, a backend-provided 64-bit register value on i386,
a negative displacement, and modulo-32-bit overflow.

Fixes #209728
DeltaFile
+31-0lldb/unittests/Expression/DWARFExpressionTest.cpp
+4-2lldb/source/Expression/DWARFExpression.cpp
+35-22 files

LLVM/project d0bc528llvm/tools/llvm-nm llvm-nm.cpp

Address review comments on the parameter.
DeltaFile
+2-3llvm/tools/llvm-nm/llvm-nm.cpp
+2-31 files

LLVM/project 04956d9llvm/include/llvm/Analysis DXILResource.h, llvm/include/llvm/IR IntrinsicsDirectX.td

[DirectX] Add support for heap resources to `DXILResourceMap`.

- `DXILResourceMap` now handles a new `llvm.dx.resource.handlefromheap` intrisics
  and adds the heap resources to the resource map.

- A new member `HeapResourceID` has been added to `ResourceInfo` to distinguish
  between heap resource instances created from different indices. The `HeapResourceID`
  is unique for each heap index `Value*`, so multiple handle creation calls using
  the same index `Value*` resolve to the same resource.

- Heap resources do not have register bindings, so the `Binding` member
  on `ResourceInfo` is now optional.

- All places that were always expecting binding are updated to handle
  heap resources. In most cases that means skipping them, such as when
  generating DXIL resource metadata, creating PSV resource entries or
  pretty-printing the resource table comment for the module disassembly
  output.


    [2 lines not shown]
DeltaFile
+174-0llvm/test/Analysis/DXILResource/buffer-fromheap.ll
+50-14llvm/lib/Analysis/DXILResource.cpp
+24-7llvm/include/llvm/Analysis/DXILResource.h
+9-5llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
+12-0llvm/test/CodeGen/DirectX/resource_from_heap_counter_error.ll
+10-0llvm/include/llvm/IR/IntrinsicsDirectX.td
+279-262 files not shown
+289-268 files

LLVM/project 22eba47lld/ELF SyntheticSections.cpp, lld/test/ELF eh-frame-hdr-oscillation.s

[ELF] Prevent .eh_frame_hdr size oscillation in address assignment (#216248)

When .eh_frame_hdr size shifts, section addresses can change whether
FDEs evaluate to identical PC-relative offsets, causing FDE
deduplication count to toggle and section size to oscillate infinitely
between passes.

Prevent .eh_frame_hdr from shrinking during iterative address assignment
passes (matching .relr.dyn) to ensure monotonic convergence.
DeltaFile
+51-0lld/test/ELF/eh-frame-hdr-oscillation.s
+6-0lld/ELF/SyntheticSections.cpp
+57-02 files

LLVM/project 05ed268llvm/include/llvm/Analysis DXILResource.h, llvm/lib/Analysis DXILResource.cpp

[NFC][DirectX] Rename ResourceInfo::RecordID to BindingID (#216376)

Rename `ResourceInfo::RecordID` to `BindingID` to better reflect its
purpose. This field is set only for resources with an associated
binding. This also clarifies the distinction from the upcoming
`HeapResourceID` member, which will identify resources originating from
a heap. The existing `RecordID` name could be ambiguous once both
identifiers are present.

The change also removes the `RecordID` argument from the `ResourceIfo`
constructor because it has always been called with `0` value. The
`BindingID` is set later via `setBindingID` after all resource instances
are collected.
DeltaFile
+32-34llvm/unittests/Analysis/DXILResourceTest.cpp
+10-10llvm/test/Analysis/DXILResource/buffer-frombinding.ll
+10-10llvm/include/llvm/Analysis/DXILResource.h
+4-5llvm/lib/Analysis/DXILResource.cpp
+3-3llvm/test/Analysis/DXILResource/has-atomic64-use.ll
+2-2llvm/test/Analysis/DXILResource/buffer-frombinding-unbounded.ll
+61-642 files not shown
+63-668 files

LLVM/project 25e6e73llvm/lib/Target/AMDGPU SIInstrInfo.td, llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.cpp

[AMDGPU][MC] Fix a crash when invalid SDWA encoding is used

Fixes #215006.
DeltaFile
+16-0llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+14-0llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
+4-1llvm/lib/Target/AMDGPU/SIInstrInfo.td
+34-13 files

LLVM/project 0cd9f45llvm/lib/Target/AMDGPU SIInstrInfo.td, llvm/lib/Target/AMDGPU/Disassembler AMDGPUDisassembler.cpp

[AMDGPU][MC] Fix a crash when invalid SDWA encoding is used

Fixes #215006.
DeltaFile
+16-0llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+14-0llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
+4-1llvm/lib/Target/AMDGPU/SIInstrInfo.td
+34-13 files

LLVM/project b43c56bclang-tools-extra/clangd Diagnostics.cpp, clang-tools-extra/clangd/unittests DiagnosticsTests.cpp

[clangd][clang-tidy] Factor out mergeFixits() logic and reuse it in clangd (#208682)

This patch extracts `mergeFixits()` from `DiagnosticRenderer` to
`clang::edit` and reuses it in clangd. This prevents syntax errors
caused by token merging when applying clang-tidy fixits via clangd.

Fixes #207618
DeltaFile
+56-6clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
+54-0clang/lib/Edit/EditedSource.cpp
+1-51clang/lib/Frontend/DiagnosticRenderer.cpp
+11-3clang-tools-extra/clangd/Diagnostics.cpp
+9-0clang/include/clang/Edit/EditedSource.h
+2-0clang-tools-extra/docs/ReleaseNotes.md
+133-601 files not shown
+134-607 files

LLVM/project 125c8d3llvm/lib/DWARFLinker/Parallel AcceleratorRecordsSaver.cpp, llvm/test/tools/dsymutil/AArch64 lit.local.cfg debug-names-accel-table-types.ll

[DWARFLinker] Index Swift mangled type names in the parallel linker (#216429)

Swift records a type's mangled name in DW_AT_linkage_name. The classic
linker indexes it as a type accelerator entry alongside the short
DW_AT_name, but the parallel linker indexed only the short name.

Port the DW_LANG_Swift block added to the classic linker in 8234f8ae2685
to the parallel linker's type case.
DeltaFile
+213-0llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/debug-names-swift-mangled-type.s
+35-14llvm/lib/DWARFLinker/Parallel/AcceleratorRecordsSaver.cpp
+3-3llvm/test/tools/dsymutil/AArch64/debug-names-accel-table-types.ll
+1-1llvm/test/tools/dsymutil/AArch64/lit.local.cfg
+252-184 files

LLVM/project 34cce43llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 recalc-copyable-deps-on-reorder.ll

Revert "[SLP]Recalculate copyable-element deps after tree reordering"

This reverts commit 8024076c7591b6477d23c3519652a7c6487d97d3 to fix
buildbot https://lab.llvm.org/buildbot/#/builders/210/builds/12275

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/216444
DeltaFile
+0-188llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
+0-50llvm/test/Transforms/SLPVectorizer/RISCV/recalc-copyable-deps-on-reorder.ll
+2-34llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-2723 files

LLVM/project 101a9b5llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 recalc-copyable-deps-on-reorder.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+0-188llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
+0-50llvm/test/Transforms/SLPVectorizer/RISCV/recalc-copyable-deps-on-reorder.ll
+2-34llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-2723 files

LLVM/project 8024076llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/AArch64 recalc-copyable-deps-on-reorder.ll

[SLP]Recalculate copyable-element deps after tree reordering

Reordering permutes the operand columns of the entries and may move an
operand between copyable-covered and plain edges, making the computed
dependency counts stale and tripping the unscheduled-deps assertion.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/216442
DeltaFile
+188-0llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
+50-0llvm/test/Transforms/SLPVectorizer/RISCV/recalc-copyable-deps-on-reorder.ll
+34-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+272-23 files

LLVM/project ef3a908clang/docs/analyzer checkers.md, clang/docs/analyzer/developer-docs InitializerLists.md

[docs][clang] Finish MyST migration for analyzer docs
DeltaFile
+210-198clang/docs/analyzer/user-docs/Annotations.md
+32-33clang/docs/analyzer/developer-docs/InitializerLists.md
+21-22clang/docs/analyzer/user-docs/CommandLineUsage.md
+15-16clang/docs/analyzer/user-docs/CrossTranslationUnit.md
+12-13clang/docs/analyzer/checkers.md
+5-6clang/docs/analyzer/user-docs/UsingWithXCode.md
+295-2889 files not shown
+312-31415 files

LLVM/project 7dc88ccllvm/lib/Target/RISCV RISCVInstrInfoSFB.td RISCVFeatures.td, llvm/test/CodeGen/RISCV short-forward-branch-opt-zibi.ll sfb-merge-base-offset.ll

[RISCV] Remove short-forward-branch-imm. (#216401)

Just use short-forward-branch-ialu. I hope implentations that implement
short-forward-branch, do it equally for all branch types. Doing anything
else would create complex tradeoffs.

I'm planning to add conditional c.mv fusion support for Zibi and I don't
want to add an immediate version flag there.

The patterns that checked NoShortForwardBranchImm were not checking that
an immediate branch ISA was enabled. So I've changed them to
NoVendorXqcibiOrNoShortForwardBranch.
DeltaFile
+7-7llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+2-7llvm/lib/Target/RISCV/RISCVFeatures.td
+3-3llvm/test/CodeGen/RISCV/sfb-merge-base-offset.ll
+2-2llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
+1-2llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
+17-2313 files not shown
+29-3619 files

LLVM/project 47aa7b9llvm/test/Transforms/SLPVectorizer/AMDGPU elementwise-fma-operand1.ll

[NFC][SLP] Add a test for fma fusion with the fmul on operand 1 (#216428)

canConvertToFMA only looks at operand 0 of the fadd, so the accumulator
shape fadd c, a * b is never recognised, and the fmul it does find is
priced with the target's fusion discount already applied. The threshold
puts the decision right at the cost boundary so the checks record which
way SLP goes today.
DeltaFile
+114-0llvm/test/Transforms/SLPVectorizer/AMDGPU/elementwise-fma-operand1.ll
+114-01 files

LLVM/project 8a6a59allvm/include/llvm/DWARFLinker AddressesMap.h, llvm/lib/DWARFLinker/Classic DWARFLinker.cpp

[DWARFLinker] Constrain a function's high_pc to its own symbol (#216432)

Mach-O objects built with .subsections_via_symbols make every symbol an
independently placeable atom, and the linker packs atoms without
preserving the spacing they had in the object file.

I have an example where the compiler describes such a subprogram as
extending past its own atom. While it's debatable whether that's a good
idea, it's not invalid in the object file. However, once linked, it is
invalid.

We can make dsymutil resilient against this by looking at the size of
the symbol in the debug map and adjusting the end_pc. I'm doing so
conservatively so that only a collision is repaired. Already
overlapping/invalid ranges remain untouched.

rdar://184768778
DeltaFile
+88-0llvm/test/tools/dsymutil/subprogram-high-pc-past-symbol.test
+76-0llvm/test/tools/dsymutil/Inputs/subprogram-high-pc-past-symbol.s
+72-0llvm/test/tools/dsymutil/Inputs/subprogram-high-pc-past-symbol-dwarf2.s
+38-8llvm/include/llvm/DWARFLinker/AddressesMap.h
+34-2llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
+24-6llvm/tools/dsymutil/DwarfLinkerForBinary.h
+332-163 files not shown
+371-209 files

LLVM/project 5f491a4llvm/include/llvm/ABI TargetInfo.h, llvm/lib/ABI CMakeLists.txt

[LLVMABI] Create a skeleton for AArch64 ABI handling (#216222)

This change adds the most basic implementation of llvm::abi::TargetInfo
for AArch64 targets and establishes a unit test for it.

There was no isolated testing for previous targets implemented in the
ABI library. They were only tested through clang. My plan with AArch64
is to create unit tests so that the library can be tested without
building the clang target, but also to have clang tests so that the
handling can be compared to clang's ABI handling as a meaningful point
of reference for correct behavior.

For this initial change, because no real handling is implemented yet, I
am not introducing the clang hook or any clang-based tests.

Assisted-by: Cursor / Grok 4.5 (test generation)
DeltaFile
+94-0llvm/unittests/ABI/AArch64TargetInfoTest.cpp
+41-0llvm/lib/ABI/Targets/AArch64.cpp
+10-0llvm/include/llvm/ABI/TargetInfo.h
+9-0llvm/unittests/ABI/CMakeLists.txt
+1-0llvm/unittests/CMakeLists.txt
+1-0llvm/lib/ABI/CMakeLists.txt
+156-06 files

LLVM/project 5aec94alldb/include/lldb/Symbol SymbolLocator.h, lldb/source/Core DynamicLoader.cpp

[lldb] Search for a corefile's images before loading any of them (#216431)

A userland or kernel corefile can list hundreds of images, and searching
for one can shell out to a symbol server or fetch over the network.
Searching for them one at a time is where loading such a corefile spends
its time.

Add a batch form of SymbolLocator::Locate that runs the searches on the
debugger's thread pool, gated on target.parallel-module-load. Results
come back in the order the requests were given, since that order decides
the Target's module order. Only the results are ordered, and anything a
search reports to the user arrives in whatever order the searches finish
in.

Only the plugin searches run concurrently, so a platform hook does not
have to be thread safe to take part, and reading a binary's UUID out of
memory stays on the calling thread.

Setting up a platform binary can replace the Target's platform and

    [5 lines not shown]
DeltaFile
+141-4lldb/unittests/Symbol/SymbolLocatorTest.cpp
+79-63lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
+76-11lldb/source/Symbol/SymbolLocator.cpp
+34-20lldb/source/Core/DynamicLoader.cpp
+25-0lldb/test/API/macosx/lc-note/multiple-binary-corefile/TestMultipleBinaryCorefile.py
+19-0lldb/include/lldb/Symbol/SymbolLocator.h
+374-986 files

LLVM/project 9a592bdclang/docs/analyzer conf.py, libc/docs/_static copybutton.js

[clang][docs] Prototype Furo theme setup
DeltaFile
+140-0utils/docs/llvm_sphinx/_static/furo-common.css
+0-71llvm/docs/_static/custom.css
+0-56llvm/docs/_static/copybutton.js
+0-56libc/docs/_static/copybutton.js
+56-0utils/docs/llvm_sphinx/_static/copybutton.js
+10-34clang/docs/analyzer/conf.py
+206-2179 files not shown
+335-39215 files

LLVM/project af1ce4doffload/languages/kernel/src LanguageRuntime.cpp, offload/test/offloading/CUDA devicesync_streams.cu

add proper deviceSync
DeltaFile
+98-0offload/test/offloading/CUDA/devicesync_streams.cu
+97-0offload/test/offloading/HIP/devicesync_streams.hip
+19-5offload/languages/kernel/src/LanguageRuntime.cpp
+1-1offload/test/offloading/HIP/launch_tu.hip
+1-1offload/test/offloading/HIP/basic_launch_multi_arg.hip
+1-1offload/test/offloading/HIP/basic_launch_blocks_and_threads.hip
+217-87 files not shown
+224-1113 files

LLVM/project c1dbf96clang/docs Toolchain.md LanguageExtensions.md, clang/docs/analyzer checkers.rst

[clang][docs] Remove page-local contents directives
DeltaFile
+0-10clang/docs/DriverInternals.md
+0-4clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
+0-4clang/docs/analyzer/checkers.rst
+0-4clang/docs/Toolchain.md
+0-4clang/docs/LanguageExtensions.md
+0-4clang/docs/FunctionEffectAnalysis.md
+0-3074 files not shown
+0-25080 files

LLVM/project 7a1dedeoffload/languages/kernel/include LanguageUtils.h, offload/languages/kernel/src LanguageLaunch.cpp LanguageRuntime.cpp

add blocking semantics to LaunchKernel and Memcpy
DeltaFile
+131-0offload/test/offloading/CUDA/blocking_stream_semantics.cu
+125-0offload/test/offloading/HIP/blocking_stream_semantics.hip
+50-4offload/languages/kernel/include/LanguageUtils.h
+20-5offload/languages/kernel/src/LanguageRuntime.cpp
+17-3offload/languages/kernel/src/LanguageLaunch.cpp
+4-2offload/test/offloading/HIP/stream_api.hip
+347-143 files not shown
+355-179 files

LLVM/project db315b5lldb/source/Plugins/ObjectFile/Mach-O ObjectFileMachO.cpp, lldb/source/Symbol SymbolLocator.cpp

Undo botched rebase (#216421)

When rebasing #215393, I accidentally pulled in the change for #215952.
I then later rebased the latter, leaving only the changes requested
during review. Undo this mess so I can land the two PRs correctly.
DeltaFile
+4-141lldb/unittests/Symbol/SymbolLocatorTest.cpp
+63-79lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
+0-88llvm/test/tools/dsymutil/subprogram-high-pc-past-symbol.test
+11-76lldb/source/Symbol/SymbolLocator.cpp
+0-76llvm/test/tools/dsymutil/Inputs/subprogram-high-pc-past-symbol.s
+0-72llvm/test/tools/dsymutil/Inputs/subprogram-high-pc-past-symbol-dwarf2.s
+78-5329 files not shown
+118-74515 files

LLVM/project fbc0797llvm/include/llvm/Support Endian.h

[Support] Remove deprecated endian::byte_swap/read/write overloads (#216300)

These overloads took the endianness as a template parameter and were
deprecated in favour of the versions that take it as a function
argument. There are no remaining in-tree users, so drop them.

Co-authored-by: Claude <noreply at anthropic.com>
DeltaFile
+1-21llvm/include/llvm/Support/Endian.h
+1-211 files

LLVM/project b3601a3mlir/lib/TableGen Attribute.cpp, mlir/test/IR enum-attr-invalid.mlir

[MLIR][TableGen] Fix EnumAttr not recognized as enum in OpFormatGen (#189046)

`Attribute::isEnumAttr()` checked `isSubClassOf("EnumAttrInfo")`, but
the newer `EnumAttr` class (from `mlir/include/mlir/IR/EnumAttr.td`)
extends `AttrDef`, not `EnumAttrInfo`. This caused `canFormatEnumAttr`
in `OpFormatGen.cpp` to return `false` for `EnumAttr`-backed attributes,
forcing them to use the generic format path instead of the enum keyword
format path.

The fix has two parts:
1. Update `Attribute::isEnumAttr()` to also check
`isSubClassOf("EnumAttr")`.
2. Add `getEnumInfoRecord()` helper in `OpFormatGen.cpp` that, for
`EnumAttr`-based attributes, retrieves the `enum` sub-field (which is
the actual `EnumInfo` record) rather than the attribute def itself.
Update `canFormatEnumAttr`, `genEnumAttrParser`, and
`genEnumAttrPrinter` to use this helper.

Add a test to `op-format.td` verifying that an `EnumAttr`-wrapped enum

    [4 lines not shown]
DeltaFile
+74-0mlir/test/mlir-tblgen/op-format.td
+36-5mlir/tools/mlir-tblgen/OpFormatGen.cpp
+3-6mlir/test/IR/enum-attr-invalid.mlir
+3-1mlir/lib/TableGen/Attribute.cpp
+116-124 files

LLVM/project 120a8b7llvm/utils/gn/secondary/lldb/source/Target BUILD.gn

[gn build] Port 251ab4a3f2a2 (#216427)
DeltaFile
+1-0llvm/utils/gn/secondary/lldb/source/Target/BUILD.gn
+1-01 files