LLVM/project 045375dclang/include/clang/Basic Cuda.h BuiltinsNVPTX.td, clang/lib/Basic Cuda.cpp

[clang][CUDA] Add new new CUDA and PTX versions (#197992)

PTX 9.1 and 9.2 already exists in LLVM, so this change just plumbs these
versions into clang to allow using newer instructions when we're
compiling with cuda-13.x
DeltaFile
+9-0clang/lib/Driver/ToolChains/Cuda.cpp
+4-2clang/include/clang/Basic/Cuda.h
+1-1clang/include/clang/Basic/BuiltinsNVPTX.td
+2-0clang/lib/Basic/Cuda.cpp
+16-34 files

LLVM/project 0dd2996llvm/test/TableGen address-space-patfrags.td, llvm/test/TableGen/GlobalISelCombinerEmitter match-table-variadics.td

[TableGen] Resolve GlobalISel strict weak ordering check. (#197071)

This is aiming to resolve:
`llvm-tblgen failed: error executing TdGenerate command llvm-tblgen
-gen-global-isel-combiner '-combiners=AArch64PostLegalizerCombiner'
[...]
llvm-project/llvm/lib/Target/AArch64/AArch64GenPostLegalizeGICombiner.inc`
`strict_weak_ordering_check.h:50: libc++ Hardening assertion
!__comp(*(__first + __a), *(__first + __b)) failed: Your comparator is
not a valid strict-weak ordering`.
DeltaFile
+30-25llvm/test/TableGen/address-space-patfrags.td
+11-11llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td
+5-0llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+46-363 files

LLVM/project 0c18098llvm/lib/DebugInfo/PDB/Native PDBFileBuilder.cpp

Initialize PDBFileBuilder::Strings
DeltaFile
+2-2llvm/lib/DebugInfo/PDB/Native/PDBFileBuilder.cpp
+2-21 files

LLVM/project d6f5793flang-rt/lib/runtime extrema.cpp matmul.cpp

[flang-rt][NFC] Split up expensive .cpp files into multiple files (#198111)

Summary:
This PR simply takes the existing `.cpp` files for the heaviest
implementations and separates them logically, typically between real,
integer, and complex types. The existing `.cpp` file is turned into a
`.h` file and we create new `.cpp` files that *only* contain the old
portion that used `RTDEF`. This allows for far more build system
parallelism, and it also means that static library linking semantics
mean that if the user only uses integer routines the linker will not
include the unused complex / real routines in the final executable.

All around this is a good practice for runtime libraries. Verified that
all `_Fortran` entrypoint routines are still present, port was strictly
mechanical.

The result of all of this is that I can now build `flang-rt` in ~10s
with all threads instead of ~50s due to the most expensive files being
split into parallelizable chunks.
DeltaFile
+0-878flang-rt/lib/runtime/extrema.cpp
+0-478flang-rt/lib/runtime/matmul.cpp
+471-0flang-rt/lib/runtime/matmul.h
+434-0flang-rt/lib/runtime/extrema.h
+0-407flang-rt/lib/runtime/findloc.cpp
+0-378flang-rt/lib/runtime/matmul-transpose.cpp
+905-2,14127 files not shown
+3,385-2,41033 files

LLVM/project d70adc0llvm/lib/DebugInfo/DWARF DWARFExpressionPrinter.cpp, llvm/test/tools/llvm-dwarfdump/NVPTX ptx-register-name.yaml lit.local.cfg

[llvm-dwarfdump] Decode the virtual register names from the dwarf register numbers (#192353)

Backends like `NVPTX` encode virtual register names as the DWARF
register number- the ASCII bytes of the name are concatenated into a
uint64_t.

This change adds fallback logic to decode these dwarf register numbers
into strings.

This improves the readability of Dwarfdump output.
e.g. 
Before the change- 
` DW_AT_location        (DW_OP_regx 0x25726431)`

After the change- 
` DW_AT_location        (DW_OP_regx %rd1)`
DeltaFile
+110-0llvm/test/tools/llvm-dwarfdump/NVPTX/ptx-register-name.yaml
+68-12llvm/lib/DebugInfo/DWARF/DWARFExpressionPrinter.cpp
+58-0llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp
+2-0llvm/test/tools/llvm-dwarfdump/NVPTX/lit.local.cfg
+238-124 files

LLVM/project d5ad811llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV load-store.ll

[SLP] Generate StoreChainContext for all chains for a given base pointer first (#193616)

Rather than generating the chains for a `RelatedStoreInsts` worth of
stores at a time and then vectorizing that group, create the
StoreChainContext for all chains in all `RelatedStoreInsts`, and then
vectorize at the end.

Will allow easier integration with runtime strided stores since those
will exist across `RelatedStoreInsts`.

Bigger VF chains are now attempted before smaller VF chains across all
`RelatedStoreInsts` groups for a base value type, so some behavioral
changes in the vectorization of overlapping chains as the relative order
in which we attempt to vectorize them may have changed (longer before
shorter).
DeltaFile
+17-28llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4-10llvm/test/Transforms/SLPVectorizer/RISCV/load-store.ll
+21-382 files

LLVM/project a11ca82clang/lib/CodeGen/TargetBuiltins ARM.cpp

[clang][AArch64][NFC] Remove redundant bitcasts in builtin codegen (#196988)

Update CodeGen for the ACLE AdvSIMD “extract one element from vector”
builtins to avoid emitting unnecessary bitcasts:

* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#extract-one-element-from-vector

The existing tests continue to cover the generated IR and require no
updates, confirming that this is an NFC cleanup.

This is similar to #195825.
DeltaFile
+0-28clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+0-281 files

LLVM/project 20d89acmlir/test/Dialect/MemRef emulate-narrow-type-cf.mlir emulate-narrow-type-cf-types.mlir, mlir/test/lib/Dialect/MemRef TestEmulateNarrowType.cpp CMakeLists.txt

[MLIR][test] Add lit coverage for cf.br/cond_br/switch under narrow-type emulation (#198053)

Wires `cf::populateCFStructuralTypeConversionsAndLegality` into the
in-tree `TestEmulateNarrowType` pass and adds lit coverage that
exercises `cf.br` / `cf.cond_br` / `cf.switch` operand and successor
block-argument rewriting when emulating sub-byte element types:

* `memref<NxiW>` carried across `cf.br` / `cf.cond_br` / `cf.switch`.
* Sub-byte integer scalars across `cf.br`.
* Sub-byte integer vectors across `cf.br`.

This PR initially added thin wrapper functions
(`memref::populateMemRefNarrowTypeEmulationCFPatterns`,
`vector::populateVectorNarrowTypeEmulationCFPatterns`) over
`cf::populateCFStructuralTypeConversionsAndLegality`. Per review
feedback those wrappers were redundant, so callers (including the
in-tree test pass) now call
`cf::populateCFStructuralTypeConversionsAndLegality`
directly. Net contribution is the test-pass plumbing and the new lit
tests demonstrating that the existing cf structural type conversion
correctly handles narrow-type-emulated values.
DeltaFile
+78-0mlir/test/Dialect/MemRef/emulate-narrow-type-cf.mlir
+38-0mlir/test/Dialect/MemRef/emulate-narrow-type-cf-types.mlir
+8-3mlir/test/lib/Dialect/MemRef/TestEmulateNarrowType.cpp
+1-0mlir/test/lib/Dialect/MemRef/CMakeLists.txt
+125-34 files

LLVM/project 9bc88acllvm/include/llvm/Transforms/IPO InstrumentorUtils.h, llvm/lib/Transforms/IPO InstrumentorUtils.cpp InstrumentorStubPrinter.cpp

[Instrumentor] Provide source location to runtime calls

To allow runtime calls to inspect the source location of the
instrumentation opportunity, we encode it in the module. This allows the
use in all environments, e.g., on GPUs, which might lack runtime dwarf
reading or libunwind. The stub printer is extended to make handling with
the encoded location information easy.
DeltaFile
+189-0llvm/lib/Transforms/IPO/InstrumentorUtils.cpp
+90-36llvm/test/Instrumentation/Instrumentor/default_rt.c
+99-4llvm/lib/Transforms/IPO/InstrumentorStubPrinter.cpp
+98-0llvm/include/llvm/Transforms/IPO/InstrumentorUtils.h
+64-0llvm/test/Instrumentation/Instrumentor/default_rt.h
+45-15llvm/test/Instrumentation/Instrumentor/rt_config.json
+585-556 files not shown
+742-10712 files

LLVM/project df6994dllvm/include/llvm/CodeGen/GlobalISel CombinerHelper.h, llvm/include/llvm/Target/GlobalISel Combine.td

[AArch64][GlobalISel] Add pre-legalizer combines for AVGFLOOR and AVGCEIL (#192866)

This patch adds GlobalISel pre-legalizer combines to pattern-match and
optimize average operations, bringing GlobalISel on par with
SelectionDAG.

Specifically, it matches:
- `(a + b) >> 1` into `G_UAVGFLOOR` / `G_SAVGFLOOR`
- `(a + b + 1) >> 1` into `G_UAVGCEIL` / `G_SAVGCEIL`

Support is included for both scalar and vector types, correctly handling
constants and splat vectors via `isOneOrOneSplat()`. This builds upon
the generic opcodes introduced for AArch64 intrinsics lowering and
enables optimal emission of Neon instructions (e.g., `urhadd`, `shadd`)
directly from generic IR.

Fixes #118083
DeltaFile
+337-0llvm/test/CodeGen/AArch64/GlobalISel/combine-avg.mir
+84-218llvm/test/CodeGen/AArch64/arm64-vhadd.ll
+26-92llvm/test/CodeGen/AArch64/hadd-combine.ll
+50-1llvm/include/llvm/Target/GlobalISel/Combine.td
+13-0llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+3-0llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+513-3116 files

LLVM/project e383eb9llvm/lib/Transforms/IPO InstrumentorStubPrinter.cpp Instrumentor.cpp, llvm/test/Instrumentation/Instrumentor default_rt.h rt_config.json

[Instrumentor] Improve stub printer (for C/C++ and value packs)

The stub printer now emits a helper header to deal with value packs (in
C and C++). We also make the files C/C++ compatible and use the proper
format strings for int32_t and int64_t.
DeltaFile
+410-5llvm/lib/Transforms/IPO/InstrumentorStubPrinter.cpp
+264-0llvm/test/Instrumentation/Instrumentor/default_rt.h
+190-2llvm/test/Instrumentation/Instrumentor/rt_config.json
+124-0llvm/test/Instrumentation/Instrumentor/default_rt.c
+0-37llvm/test/Instrumentation/Instrumentor/default_rt
+7-6llvm/lib/Transforms/IPO/Instrumentor.cpp
+995-504 files not shown
+1,004-5110 files

LLVM/project 4046dc4llvm/cmake/modules CrossCompile.cmake

Make sure optional components are excluded (#187824)

Extends a fix from
https://github.com/llvm/llvm-project/commit/b1e92f8def98c5e34fdb3b4c18ac16d65fb613a2
to examples and docs, both of which may be missing but are
unconditionally included if missing

This fixes an issue where the Chapel team vendors LLVM (and subsequently
deletes directories like docs and examples for smaller file sizes), but
if those directories are missing the build will fail

Signed-off-by: Jade Abraham <jademabraham17 at gmail.com>
DeltaFile
+2-0llvm/cmake/modules/CrossCompile.cmake
+2-01 files

LLVM/project 545fea0clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/Sema SemaObjC.cpp SemaDecl.cpp

[Clang] Improve __block attribute coverage for ivars and static variables (#198167)

As discussed in #194856, we need to improve the diagnostic coverage for
the `__block` attribute.

The modifications I made are as follows:
1. added diagnostic definitions
2. modified diagnostic logic
3. added test cases
4. modified the affected test cases

close #197213
DeltaFile
+24-3clang/lib/Sema/SemaObjC.cpp
+10-6clang/test/Sema/block-misc.c
+9-4clang/include/clang/Basic/DiagnosticSemaKinds.td
+11-0clang/test/SemaObjC/block-on-ivar.m
+0-11clang/test/Sema/block-on-objc-ivars.m
+5-4clang/lib/Sema/SemaDecl.cpp
+59-285 files not shown
+77-3311 files

LLVM/project 1b7f9a0.github/workflows pr-code-lint.yml

[Github][CI] Don't build analysis targets when no relevant projects present (#196882)

Fixes error described in
[link](https://github.com/llvm/llvm-project/pull/194442#issuecomment-4330108752),
When `clang-tools-extra` project was not computed to build but
`genconfusable` (part of `clang-tools-extra`) was build anyway.
DeltaFile
+10-3.github/workflows/pr-code-lint.yml
+10-31 files

LLVM/project 332c06bllvm/include/llvm/Target Target.td, llvm/test/TableGen aarch64-apple-tuning-features.td

[llvm] Sort the Subtarget feature implies list by name (#197700)
DeltaFile
+76-76llvm/test/TableGen/aarch64-apple-tuning-features.td
+1-1llvm/include/llvm/Target/Target.td
+77-772 files

LLVM/project 44027b2llvm/lib/Transforms/Scalar LoopInterchange.cpp

address review comment
DeltaFile
+17-14llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+17-141 files

LLVM/project 0646ec9clang/include/clang/AST ASTContext.h, clang/include/clang/Basic Builtins.td

Revert "Add clang warning if fp exception functions are called without appropriate flags/pragmas" (#198341)

Reverts llvm/llvm-project#187860

Reason: this breaks compiling several different versions of libc, and is
also issuing diagnostics for platforms that are incompatible (see
https://github.com/llvm/llvm-project/pull/187860 for details).

Revert for now until we resolve how to move forward and reland.
DeltaFile
+0-68clang/test/Sema/fenv-access.c
+0-55clang/include/clang/Basic/Builtins.td
+0-51clang/test/Sema/builtin-fenv.c
+0-36clang/lib/Serialization/ASTReader.cpp
+1-34clang/include/clang/AST/ASTContext.h
+0-35clang/test/Sema/fenv-access-implicit.c
+1-27914 files not shown
+2-42420 files

LLVM/project 72daa33clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-across.c neon-intrinsics.c

[CIR] max-across-vector (vmaxv_*) intrinsics (#197095)

Part of #185382 
Added the vmax_v variants.
Moved the test cases to
[intrinsics.c](https://github.com/llvm/llvm-project/pull/clang/test/CodeGen/AArch64/neon/intrinsics.c)
Removed the test cases from
[neon-intrinsics.c](clang/test/CodeGen/AArch64/neon/intrinsics.c)
DeltaFile
+169-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+1-112clang/test/CodeGen/AArch64/neon-across.c
+0-39clang/test/CodeGen/AArch64/neon-intrinsics.c
+15-0clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+185-1514 files

LLVM/project 6a86650mlir/include/mlir/Dialect/AMDGPU/Utils MemorySpaceUtils.h, mlir/lib/Dialect/AMDGPU/Transforms MemoryAccessOpInterfacesImpl.cpp FoldMemRefsOps.cpp

[mlir][AMDGPU] Move memory access op folding to memref interfaces (#197310)

This PR implements IndexedAccessOpInterface and
IndexedMemCopyOpInterface for relevant ops in the AMDGPU dialect,
removing the custom folding pass we used to have now that there's
interfaces for this sort of thing.

As a result:

- The in-bonuds semantics of various AMDGPU ops have been clarified
- Interface methods to enable oob checks on DMA operations have been
added (to prevent accidental `disjoint`ing and the like)
- Said memref rewrite patterns have been hardened to allow for mixed
tensor/memref semantics.
- Helpers for detecting memory spaces were factored out of
`AMDGPUOps.cpp` so that they could be re-used in the interface
implementations.

# Breaking changes / migration

    [4 lines not shown]
DeltaFile
+644-0mlir/test/Dialect/AMDGPU/fold-memref-alias-ops.mlir
+0-470mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
+258-0mlir/lib/Dialect/AMDGPU/Transforms/MemoryAccessOpInterfacesImpl.cpp
+0-211mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
+94-0mlir/test/Dialect/AMDGPU/invalid.mlir
+64-0mlir/include/mlir/Dialect/AMDGPU/Utils/MemorySpaceUtils.h
+1,060-68112 files not shown
+1,244-77318 files

LLVM/project daff70eutils/bazel/llvm-project-overlay/mlir BUILD.bazel

[Bazel] Fixes 755732f (#198347)

This fixes 755732f184ea73b9f6f28765b33cf3030c0dc9d7.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+2-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+2-01 files

LLVM/project 2a53990lldb/packages/Python/lldbsuite/test lldbtest.py dotest.py

[lldb][test] Use octal literal (NFC) (#198343)
DeltaFile
+1-3lldb/packages/Python/lldbsuite/test/lldbtest.py
+2-2lldb/packages/Python/lldbsuite/test/dotest.py
+3-52 files

LLVM/project 755732fmlir/include/mlir/Dialect/GPU/IR GPUOps.td, mlir/lib/Conversion/GPUToNVVM LowerGpuOpsToNVVMOps.cpp

[mlir][GPU] Extend gpu.barrier with scope and named-barrier support (#195692)

This commit adds two features to gpu.barrier that are supported on
targets like recent AMDGPU chips, Nvidia's hardware, and SPIR-V.

The first of these is named barriers, which allow creating a barrier
object that is initialized with the number of subgroups that must arrive
at it before those subgroups are released. These are represented in MLIR
with a new `!gpu.named_barrier` type and created by
`gpu.initialized_named_barrier` operation. These named barriers then
become arguments to `gpu.barrier`.

The other change is adding a "scope" enum and using it to specify the
execution scope of barriers. This allows for rerpresenting cluster- and
subgroup-wide barriers (the latter exists on AMDGPU and Nvidia, and
while I suspect Nvidia has cluster-scope barriers, I didn't go looking)
and allows us to fully lower to SPIR-V's OpControlBarrier.

While these are two different features, I figured I'd land them in one

    [4 lines not shown]
DeltaFile
+173-53mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+131-8mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
+83-16mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
+69-8mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
+69-0mlir/test/Dialect/GPU/named-barrier.mlir
+54-0mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir
+579-8516 files not shown
+863-9322 files

LLVM/project 7eab3e0flang/lib/Optimizer/Transforms FIRToMemRef.cpp, flang/test/Transforms/FIRToMemRef omp-wsloop-simd-private.mlir

[FIRToMemRef] Fix fir.convert insertion inside omp.wsloop (#197653)

When replaceFIRMemrefs inserted a fir.convert before an op inside a
LoopWrapperInterface region (e.g. omp.simd inside omp.wsloop), it
violated the single-nested-op invariant, producing a verifier error. Fix
by walking up the LoopWrapperInterface parent chain and inserting before
the outermost wrapper instead.

Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>

Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+33-0flang/test/Transforms/FIRToMemRef/omp-wsloop-simd-private.mlir
+7-1flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
+40-12 files

LLVM/project 58ee64eclang/lib/Driver/ToolChains OHOS.cpp Fuchsia.cpp, clang/test/Driver fuchsia.c ohos.c

[Driver] Uniform handling of invalid rtlib across drivers (#198219)

This is mostly an NFC except for a different diagnostic being emitted.
The goal is to unify validation and handling of invalid rtlib value
across different drivers to simplify supporting more -rtlib= values in
the future.
DeltaFile
+4-4clang/lib/Driver/ToolChains/OHOS.cpp
+4-4clang/lib/Driver/ToolChains/Fuchsia.cpp
+1-1clang/lib/Driver/ToolChains/Darwin.cpp
+1-1clang/test/Driver/fuchsia.c
+1-1clang/test/Driver/ohos.c
+11-115 files

LLVM/project 9886c72llvm/include/llvm/Analysis FunctionPropertiesAnalysis.h, llvm/include/llvm/IR FunctionProperties.def

Add noreturn call count to FunctionPropertiesAnalysis pass (#198322)

Adding this metric to visualize how many noreturn functions there are
with the idea of analyzing their relationship with unreachable
instructions
DeltaFile
+4-0llvm/lib/Analysis/FunctionPropertiesAnalysis.cpp
+1-0llvm/include/llvm/Analysis/FunctionPropertiesAnalysis.h
+1-0llvm/include/llvm/IR/FunctionProperties.def
+6-03 files

LLVM/project 1d4c14bclang/include/clang/AST ASTContext.h, clang/include/clang/Basic Builtins.td

Revert "Add clang warning if fp exception functions are called without approp…"

This reverts commit 5f2bedca745d5efa1955369cfe352bcd09be4633.
DeltaFile
+0-68clang/test/Sema/fenv-access.c
+0-55clang/include/clang/Basic/Builtins.td
+0-51clang/test/Sema/builtin-fenv.c
+0-36clang/lib/Serialization/ASTReader.cpp
+0-35clang/test/Sema/fenv-access-implicit.c
+1-34clang/include/clang/AST/ASTContext.h
+1-27914 files not shown
+2-42420 files

LLVM/project 823be5ellvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-local.mir

rebase

Created using spr 1.3.7
DeltaFile
+23,873-20,923llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+8,633-8,584llvm/test/CodeGen/Thumb2/mve-clmul.ll
+1,243-8,768llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
+0-4,752llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s
+4,549-0llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test
+3,706-328llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+42,004-43,3552,168 files not shown
+133,338-93,5472,174 files

LLVM/project c93c17bclang/include/clang/DependencyScanning ModuleDepCollector.h, clang/lib/DependencyScanning ModuleDepCollector.cpp

[clang][deps] Move `ModuleDepCollectorPP` to .cpp file (#197964)

This PR moves the `ModuleDepCollectorPP` type into the .cpp file. It's
an implementation detail that the header doesn't need to expose.
DeltaFile
+54-45clang/lib/DependencyScanning/ModuleDepCollector.cpp
+2-33clang/include/clang/DependencyScanning/ModuleDepCollector.h
+56-782 files

LLVM/project f4ee477llvm/test/Transforms/HotColdSplit issue-197982.ll

[NFC][CodeExtractor] simplify test for #197986 (#198011)
DeltaFile
+16-63llvm/test/Transforms/HotColdSplit/issue-197982.ll
+16-631 files

LLVM/project dd199b4llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp

[AMDGPU][GlobalISel] Remove dependency on legal ruleset (#197371)

This fills in always legal rules, to remove the dependency on the legacy
ruleset. This is not guaranteed to be all the rules, just the ones that
appear in tests.
DeltaFile
+7-0llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+7-01 files