[LifetimeSafety] Run analysis in post-order of CallGraph for better annotation propagation (#174178)
Add functionality to analyze functions in the post-order of the call
graph.
The PR includes the following changes:
1. **Call Graph Generation**: Uses `clang::CallGraph` and
`addToCallGraph` to generate a call graph.
2. **Topological Traversal**: Uses `llvm::post_order` to iterate through
the CallGraph.
3. **New Frontend Flag**: The post-order analysis is enabled via a new
frontend flag `-fexperimental-lifetime-safety-inference-post-order`
Example:
```css
#include <iostream>
#include <string>
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[flang] Added OperationMoveOpInterface for controlling LICM. (#175108)
In #173438 I added a FIR specific loop invariant code motion pass.
During the review, Tom pointed out certain limitations about OpenMP
dialect operations that should be taken into consideration during
transformations such as LICM:
https://github.com/llvm/llvm-project/pull/173438#discussion_r2657612148
I also found issues with hoisting operations out of `acc.loop`
operations in certain conditions (see the added test in `licm.fir`).
I am proposing a new operation interface that will allow to control
movement of operations during MLIR transformations. In particular, I
propose two methods (there might be more):
* op.canMoveOutOf(cand) - returns true, if it is allowed to move 'cand'
operation out of 'op'.
* op.canMoveFromDescendant(descendant, cand) - return true, if it is
allowed to move 'cand' out of 'descendant' and into 'op'.
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[lldb][CMake] Don't condition libc++ requirement on LLDB_ENFORCE_STRICT_TEST_REQUIREMENTS (#175955)
This reverts:
```
commit 78769d51c6b183b6d88fbd1ef825fff7cf3aad21
Author: Adrian Prantl <aprantl at apple.com>
Date: Tue Nov 4 08:29:47 2025 -0800
[LLDB] Don't check for libcxx if LLDB_ENFORCE_STRICT_TEST_REQUIREMENTS is off
```
This was needed as an [escape hatch for our ASAN
bot](https://github.com/llvm/llvm-zorg/commit/e78725d94b72227e4e524e9b76900ed197791419)
because we couldn't build libc++ on it. Ever since
https://github.com/llvm/llvm-zorg/pull/702 we can.
Most people wouldn't know to `LLDB_ENFORCE_STRICT_TEST_REQUIREMENTS`
when building LLDB. Which means they'd never know to build libc++, and
thus would have worse test-coverage for our data-formatters.
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[mlir][tosa] Separate layerwise folding and simple folder tests (NFC) (#172691)
This commit moves the 'simple' folder tests (invoked via
`--canonicalize`) away from other layerwise constant folding tests
(invoked via `--tosa-layerwise-constant-fold`) into a separate test file
to help reduce confusion.
Also rename the layerwise folding test file to reflect the the pass name
that they are invoked by.
InstCombine: Improve single use fabs SimplifyDemandedFPClass handling (#176359)
SimplifyDemandedFPClass's handling of fabs recently became smarter in
the multiple use case than single. Unify these so the single use case
is equally as smart. This includes propagating ninf / nnan context into
the instruction, and accounting for nsz if the only bit difference is
for zero.
AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES
Move G_UNMERGE_VALUES handling to AMDGPURegBankLegalizeRules.cpp.
Fix sgpr S16 unmerge by lowering using shift and using S32.
Previously sgpr S16 unmerge was selected using _lo16 and _hi16 subreg
indexes which are exclusive to vgpr register classes.
For remaing cases we do trivial mapping, assigns same reg bank
to all operands, vgpr or sgpr.
[DSE][Verifier] Respect the calling convention of the function specified by "alloc-variant-zeroed" (#175911)
Require that the calling convention between the zeroed and non-zeroed
variants is the same, and set it appropriate in the DSE transform.
[AMDGPU] si-peephole-sdwa: Handle V_PACK_B32_F16_e64 (WIP)
Change si-peephole-sdwa to eliminate V_PACK_B32_F16_e64 instructions
by changing the second operand to write to the upper word of the
destination directly.
[AMDGPU] Enable ISD::{FSIN,FCOS} custom lowering to work on v2f16
Currently ISD::FSIN and ISD::FCOS of type MVT::v2f16 are legalized by
first expanding and then using a custom lowering on the resulting f16
instructions. This ordering prevents using packed math variants of the
instructions introduced by the legalization (e.g. the multiplication),
if available, and makes it difficult to eliminate the packing of the
results by using SDWA form; previous attempts to deal with the latter
situation in the si-peephole-sdwa pass were unwieldly since it was
necessary to reconstruct the association between the source and target
vectors.
Change the legalization action for ISD::FSIN and ISD::FCOS of type
MTF::v2f16 to Custom and change the custom intrinsic lowering to deal
with the v2f16 for the intrinsics introduced in this way.
[AMDGPU] SIIselLowering: Use intrinsics in LowerTrig
This allows to apply further legalization actions to the
resulting nodes which is a preparatory step to extend the
custom lowering to vector types.
[MLIR][XeGPU] Add support for cross-subgroup reduction from wg to sg (#170936)
This PR adds support for cross-sg reduction whilst distributing from
workgroup to subgroup. It has following limitation
1. Cannot reduce to a scalar
2. For cross-sg, only 1:1 decomposition (each sg should be assigned only
one tile in the original WG tile) is supported for now. For example for
a WG tile of size 256x128, sg_layout = [8, 4], sg_data = [16, 16] wont
be supported.
[github] Fix release parameter to uncomment download links step (#176386)
I thought I could remove validate-tag from the "needs" because
release-binaries also "needs" validate-tag. Turns out that we get the
release version from an output of validate-tag and if it isn't in the
"needs" section we get an empty string when substitution happens.
Leading to this error:
./llvm/utils/release/./github-upload-release.py --token "$GITHUB_TOKEN"
--release uncomment_download_links
github-upload-release.py: error: the following arguments are required:
command
Put back validate-tag.
Fixes 822a45f4b4909289f84d119f1e5891b486d74f5e.
