[X86] Fix VECREDUCE_XOR to PARITY lowering for 16-bit elements (#219216)
We can't lower vecreduce.xor to parity(movmsk) if the movmsk doesn't
match the element size. For 16-bit elements we'd use movmskb, which
would result in two bits per element, which are always the same. Thus
the parity is always zero.
Disclosure: Test case identified by AI, patch is my own.
[SPIR-V] Honor explicit memory_order/memory_scope in atomic load/store (#215572)
atomic_load_explicit and atomic_store_explicit ignored their
memory_order/memory_scope arguments
Translate the explicit arguments via the existing
buildMemSemanticsReg/buildScopeReg helpers, as buildAtomicRMWInst
already does
[gold] Handle absence of gold linker in tests (#219901)
If we get a NOTFOUND executable, directly report plugin support
as unavailable, instead of trying to invoke the linker.
This fixes a regression from #130981.
[Sema][NFC] Add additional tests for declarations in expansion statements (#211948)
I came up with these additional tests for declarations in expansion
statements that previously failed but now correctly diagnose the errors.
[LAA] Give the symbolic strides map a named type (NFC) (#216731)
LoopAccessInfo collects SCEVUnknown strides, collectStridedAccess casts
to it when inserting, but the map was typed as holding a plain SCEV, so
the invariant had to be restated at each use.
[LoongArch] Add late branch optimization pass (#216261)
The patch adds a late optimization pass that replaces conditional
branches that can be statically evaluated with an unconditinal branch.
This pass is inspired by RISC-V's RISCVLateBranchOpt pass.
[clang][bytecode] Keep sourcemaps smaller (#219878)
Only add new entries if they are different than the currently last
entry. This means we won't have an entry for _all_ opcodes in the source
map anymore.
[libc++] Remove NaCl support from __cxx03 headers (#219787)
Completes the NaCl cleanup started in #148983 by removing the remaining
references from the frozen `__cxx03/` headers.
Changes:
* Remove the `_LIBCPP_USING_NACL_RANDOM` comment block and
`#elif defined(__native_client__)` branch from
`include/__cxx03/__config`
* Remove `defined(__pnacl__)` from the `#if` condition in
`include/__cxx03/limits`
The `_LIBCPP_USING_NACL_RANDOM` macro was defined but never consumed;
its
previous consumer in `src/random.cpp` was already removed in #148983.
Fixes #219588
[CodeGen][AMDGPU] Fixed FileCheck patterns in #212201 regression test (#219683)
Quick follow up to fix failures from merging #212201. Removes `llvm::`
from FileCheck in `si-preallocate-wwm-regs-preserve.mir` test.
[clang][bytecode] Iterate scope only once in Destroy() (#219874)
Call deallocate() here directly instead of iterating the scope again in
`InterpFrame::destroy()`.
[VectorCombine] Allow equal-cost scalarization for single-use loads (#218340)
Allow scalarizeLoadExtract to scalarize a single-use vector load when
the scalarized cost is equal to the original cost.
For a single extract user, this does not increase the number of memory
operations and narrows the memory access, which can expose further
optimizations such as store-to-load forwarding and DSE.
Keep requiring a strict cost improvement for loads with multiple users.
Proof https://alive2.llvm.org/ce/z/YAck5U
Fixes https://github.com/llvm/llvm-project/issues/217598
[LoongArch] Fold selects sharing operands with binary operations (#215520)
Fold selects of the form
select C, (binop X, Y), X
into
binop X, (select C, Y, 0)
Support ADD, OR, XOR, and eligible SUB patterns while preserving the
operand-order restrictions of SUB.
[NFC][LoopVectorize] Add test for early-exit trip count that may cause UB … (#219883)
Pre-commit test for https://github.com/llvm/llvm-project/issues/219371,
where a udiv in the trip count is speculated into the preheader even
when its divisor may be poison.
[NVPTX] Add intrinsics for ff/f16/bf16 to ue5m3 conversions (#218677)
This patch adds the following intrinsics for `ff/f16/bf16` to `ue5m3`
conversions introduced in PTX 9.4:
- `cvt{.rn,.rz,.rp}{.satfinite}.ue5m3x2.f32`
- `cvt{.rn,.rz}{.satfinite}.scaled::n1::ue8m0.ue5m3x2.f32`
- `cvt{.rn,.rz,.rp}{.satfinite}.ue5m3x2{.f16x2,.bf16x2}`
- `cvt{.rn,.rz}{.satfinite}.scaled::n1::ue8m0.ue5m3x2{.f16x2,.bf16x2}`
Tests have been verified through `ptxas-13.4`.
PTX ISA Reference:
https://docs.nvidia.com/cuda/developer-preview/13.4/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt
---------
Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
flang-rt: improve endian conversion performance (#218302)
Improve endian conversion performance in the flang runtime.
This patch updates the implementation of endian conversion in
flang-rt/lib/runtime/unit.cpp and adds a driver test for endian
conversion handling.
The modified helper functions were not unit-tested directly because
they have internal linkage.
Addresses #208193.
