[DWARFLinker] Emit DW_AT_addr_base for units that had none (#219357)
Fix DWARFv5 units that reach the linker without DW_AT_addr_base, as GCC
emits them at -O2. Both linkers rewrite range and location lists into
base_addressx entries, which resolve through DW_AT_addr_base, but they
only ever patch an attribute copied from the input. With nothing to
patch, the classic linker hits the llvm_unreachable in patchAddrBase(),
and the parallel linker writes indices with no base, so the unit's
ranges resolve from address 0.
Add DW_AT_addr_base to every DWARFv5 unit root that lacks one, whatever
its tag, and emit the unit's .debug_addr contribution even when no
address was pooled, so the attribute always points at a table. Update
mode does not rewrite ranges, so nothing is added there.
The tests link a compile unit root and a partial unit root with both
linkers and check the attribute, the address table, the range list and
--verify. The compile unit test also checks that update mode adds no
attribute, and a third test links a unit that pools no address.
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[DAGCombiner] Fold umin(fp_to_uint(x), 0) to 0 (#232231)
`PerformUMinFpToSatCombine` turns `umin(fp_to_uint(x), (2^n)-1)` into
`fp_to_uint_sat`.
When the clamp width is 0 (2^0-1), `n` is also 0, and `getIntegerVT(0)`
then asserts in `IntegerType::get`, which requires a width of at least
1.
Since an unsigned value is never below 0, the `umin`'s result will
always be 0 as well.
[RISCV][P-ext] Use concat_vectors with 0 in widenPackedVectorWithZeros.
This will be legalized and combined to a vector_shuffle. That
shuffle can then be matched to a pack with x0 after #232892.
This changes the zext.w to a pack, but that's not obviously worse.
If we need to canonicalize we can add a DAG combine later.
[RISCV][P-ext] Remove custom lowering of insert_subvector for v2i16/v4i8 on RV64.
This was for handling inserting into a zero vector. After #232892
we let the insert_subvector legalize to a shuffle_vector which we
can then lower as pack.
This changes the codegen from zext.w to pack, but that's not
necessarily worse. If it turns out to be a problem we can
canonicalize pack with zero with a DAGCombine or isel patterns in
the future.
[RISCV][P-ext] Create zero vector rather than bitcasting from i32 0 in lowerINSERT_SUBVECTOR. (#232852)
Teach LowerBUILD_VECTOR to create SPLAT_VECTOR when all operands are the
same to prevent regression.
[RISCV][P-ext] Call tryWidenMaskForShuffle at the end of P extension shuffle lowering. (#232892)
If the shuffle mask has contiguous elements we can try shuffling them
using a large element type.
[flang,unittest] Initialize targets before creating a CompilerInstance. NFC (#233117)
Initialize targets first to register library options before creating a
CompilerInstance.
[libc][math] Optimize integer-only expf and factor out shared utilities.
- Optimize `expf_integer_eval` for both code size and performance.
- Factor out the shared range reduction and `2^u` fixed point evaluation to
be used by `exp2f` and `exp10f` integer-only versions.
Assisted-by: Gemini for analysis and refactoring.
[NVPTX] Attach !atomic.ignore.denormal.mode when upgrading legacy NVVM atomic add intrinsics (#232725)
Legacy NVVM floating-point atomic add intrinsics
(`@llvm.nvvm.atomic.load.add.f32.p*`,
`@llvm.nvvm.atomic.load.add.f64.p*`, and
`@llvm.nvvm.atomic.add.gen.f.*`) specifically targeted the PTX
`atom.add` instruction, which flushes f32 denormals to zero on global
memory.
Attach `!atomic.ignore.denormal.mode` metadata when auto-upgrading these
intrinsics to `atomicrmw fadd` so that they continue to lower to native
`atom.add` instructions when `-nvptx-allow-ftz-atomics` defaults to
`false` (#231429), matching the Clang lowering of
`__nvvm_atom_add_gen_f` (#217587).
[X86] Add v8f16 X86selects fallback patterns to masked VMOVSH (#231724)
Masked scalar patterns rely on `X86selects_mask`, which rejects fusing
the underlying operation into a masked instruction when that operation
has multiple users (checked via `isProfitableToFormMaskedOp`). In that
case, the bare `X86ISD::SELECTS` node must be selected separately as a
masked register move.
These fallback patterns already exist for `v4f32` (VMOVSS) and `v2f64`
(VMOVSD), but were never added for `v8f16` when AVX-512 FP16 was
introduced. In the reproducer, CSE merges identical conversions into a
single `VFPROUNDS` node with two users; pattern fusion is rejected, no
`v8f16` fallback matches, and ISel fails.
Add the missing `v8f16` fallback patterns lowering to `VMOVSHZrrk` and
`VMOVSHZrrkz`, mirroring the existing float/double logic.
Fixes #231640
Assisted-by: Claude Code for initial root-cause analysis and pattern
investigation.
MachineVerifier: Reject dead and live defs of the same register
Previously an instruction could have a dead and a live def of the same
physical register, which has no consistent interpretation.
Some passes, namely register pressure tracking, implicitly rely on the
dead flag adjustments performed by running LiveVariables. In cases of
repeated defs, LiveVariables strips dead flags. When a super-register
is only partially used, it marks the super-register def dead and adds
a live implicit-def of the used sub-register.
Prior to #222627, pressure tracking treated live defs as winning. That
PR fixed some asserts by switching to a dead wins system where any
dead flag taints those regunits for the whole instruction. #225079
reverts the remainder of #222627, back closer to the interpretation of
this verifier check.
Only a dead def with a live def of the same register is
rejected. Mixed dead flags on overlapping defs of different registers
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[mlir][LLVMIR] Precompile NVVM and ROCDL operation declarations (NFC) (#233106)
The eight source shards in each dialect repeatedly parse their operation
headers after loading the shared LLVM PCH. Give each dialect a local PCH
containing LLVMIR/pch.h followed by its operation header. Disable
downstream reuse so other libraries retain their existing PCH selection.
Reduces CPU from 103.12 to 87.48 s (-15.17%) for the affected objects.
Assisted-by: Codex
[libc++] Disable automatic module scanning on ARM CI builders
The ARM Buildkite toolchains do not expose clang-scan-deps to CMake.
When CMP0155 enables automatic scanning for libc++abi C++23 sources,
these standalone runtimes builds fail with the scanner set to NOTFOUND.
Pass CMAKE_CXX_SCAN_FOR_MODULES=OFF in the eight ARM job invocations,
including the no-exceptions variants, until their toolchains provide a
matching scanner. Keep the other CI configurations on their defaults.
Validated bash syntax, git diff --check, and argument dispatch for all
eight ARM jobs with generic C++20, C++23, and modules jobs as controls.
Assisted-by: Codex
[libc++] Provision a suitable CMake for CI builds
The previous commit raised cmake_minimum_required to 3.31. The GitHub
jobs already satisfy it (the Linux image pins 3.31.0, macOS uses brew,
Windows uses the hosted image), but some self-hosted Buildkite agents
ship an older CMake and their images cannot be updated by us.
Teach run-buildbot to check the CMake version up front. When the cmake
on PATH is new enough, this costs a single `cmake --version` and nothing
else changes. Otherwise, download a pinned, SHA-256 verified CMake
3.31.12 release binary into ${XDG_CACHE_HOME:-~/.cache}/libcxx (outside
the build directory that run-buildbot wipes) and, when no binary exists
for the host or it cannot run there, bootstrap it from source with the
host compilers rather than the runtime's CC/CXX. The install is
published with an atomic rename so concurrent builders on one agent
never see a partial cache entry.
An explicit CMAKE override is still honored but now validated; in the
provisioned or overridden cases its directory is prepended to PATH so
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[libc++abi] Retain the old CMP0155 behavior for GCC compatibility
Raising the minimum CMake version to 3.31 enables automatic module dependency
scanning for the C++23 libc++abi object libraries. GCC 16 and 17 then probe
the libstdc++ bits/stdc++.h header when processing libc++ headers and fail
if it is absent.
Set CMP0155 to OLD within libc++abi only when using GCC until its optional
header lookup is fixed. Preserve automatic scanning with Clang and guard
the policy setting for older CMake versions.
GCC bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127940
Validated the policy workaround on the CMake 3.31 minimum-version branch
with GCC 16.2.0 and CMake 3.31.12: the focused cxa_handlers.cpp reproducer
compiles. Clang 22.1.0 still generates and successfully executes the
clang-scan-deps rule for that source. git diff --check passes.
Assisted-by: Codex
[NVPTX] Set default value of nvptx-allow-ftz-atomics to false
This restores the strict FTZ default originally introduced in #200732
and temporarily relaxed in #206154.
Frontends can now explicitly opt in to native FTZ-mismatched atomics on a
per-instruction basis using !atomic.ignore.denormal.mode metadata (#217585,
#217586), which is supported in Clang, MLIR, and XLA. Users who need the
previous behavior globally can still pass -nvptx-allow-ftz-atomics=true.
Update test cases to verify the new default disallow behavior.
[SLP]Do not seed on vectorizer-created compares
With revec, alternate compares are emitted as pairs of compares on
the same operands, which were re-seeded and hanged the compiler.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/233101
[Mips] Select RINT instructions for scalar rint on R6 (#233042)
Legalize FRINT and STRICT_FRINT for supported scalar floating-point
types on standard-encoding MIPS R6 targets, and match both operations to
the existing RINT_S and RINT_D instructions instead of libcalls.
Preserve strict FP exception semantics using the existing instruction
properties.
