LLVM/project 8401a8dllvm/test/Bitcode aarch64-sve-rev-upgrade.ll aarch64-sve-rev-upgrade.ll.bc

[NFC][LLVM] Add bitcode tests for llvm.aarch64.sve.rev
DeltaFile
+111-0llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll
+0-0llvm/test/Bitcode/aarch64-sve-rev-upgrade.ll.bc
+111-02 files

LLVM/project 9ed1927llvm/include/llvm/MC MCSection.h, llvm/lib/MC MCSection.cpp

[server-llvm-21][MC] Fixing vector overflow

Summary:

Test Plan:

Reviewers:

Subscribers:

Tasks:

Tags:

Differential Revision: https://phabricator.intern.facebook.com/D87662897
DeltaFile
+13-12llvm/include/llvm/MC/MCSection.h
+2-2llvm/lib/MC/MCSection.cpp
+15-142 files

LLVM/project 0b16512llvm/utils/TableGen README.md

[llvm][Tablegen] Link to tutorial before programmer's reference

The natural assumption is that there's some sort of order here
and having people read the reference manual before the basic
tutorial does not make sense to me.
DeltaFile
+1-1llvm/utils/TableGen/README.md
+1-11 files

LLVM/project c3c3d16clang/lib/AST ExprConstant.cpp, clang/lib/AST/ByteCode InterpBuiltin.cpp

[Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - Allow AVX512 VPMULTISHIFTQB intrinsics to be used in constexpr (#168995)

Resolves #167477
DeltaFile
+134-7clang/test/CodeGen/X86/avx512vbmi-builtins.c
+95-13clang/test/CodeGen/X86/avx512vbmivl-builtin.c
+32-40clang/lib/Headers/avx512vbmivlintrin.h
+58-0clang/lib/AST/ByteCode/InterpBuiltin.cpp
+39-0clang/lib/AST/ExprConstant.cpp
+17-21clang/lib/Headers/avx512vbmiintrin.h
+375-811 files not shown
+378-847 files

LLVM/project 650eeb8llvm/include/llvm/CodeGen MachineBasicBlock.h, llvm/lib/CodeGen ShrinkWrap.cpp

[ShrinkWrap] Modify shrink wrapping to accommodate functions terminated by no-return blocks (#167548)

At present, the shrink wrapping pass misses opportunities to shrink wrap
in the presence of machine basic blocks which exit the function without
returning. Such cases arise from C++ functions like the following:
```cxx
int foo(int err, void* ptr) {
    if (err == -1) {
         if (ptr == nullptr) {
             throw MyException("Received `nullptr`!", __FILE__, __LINE__);
         }
         
         handle(ptr);
    }
    
    return STATUS_OK;
}
```
In particular, assuming `MyException`'s constructor is not marked

    [6 lines not shown]
DeltaFile
+179-0llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
+5-7llvm/lib/CodeGen/ShrinkWrap.cpp
+7-0llvm/include/llvm/CodeGen/MachineBasicBlock.h
+191-73 files

LLVM/project 6c51a00lldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp UnwindAssemblyInstEmulation.h, lldb/unittests/UnwindAssembly/ARM64 TestArm64InstEmulation.cpp

Address review comment

Created using spr 1.3.7
DeltaFile
+2-2lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+2-2lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
+1-1lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h
+5-53 files

LLVM/project 0520093lldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+2-2lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+2-21 files

LLVM/project f598476lldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

Rebased

Created using spr 1.3.7
DeltaFile
+2-2lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+2-21 files

LLVM/project 918427elldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+2-2lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+2-21 files

LLVM/project 980669elldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

Rebased

Created using spr 1.3.7
DeltaFile
+2-2lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+2-21 files

LLVM/project fd225c8lldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+2-2lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+2-21 files

LLVM/project f00f52clldb/source/Plugins/UnwindAssembly/InstEmulation UnwindAssemblyInstEmulation.cpp

Address review comments

Created using spr 1.3.7
DeltaFile
+2-2lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+2-21 files

LLVM/project a4ef96cllvm/lib/IR Verifier.cpp, llvm/test/CodeGen/AMDGPU isel-amdgcn-cs-chain-intrinsic-w32.ll

[AMDGPU] Relax restrictions on amdgcn.cs.chain intrinsic

We have a new use-case for chain functions, so slightly relax the
restriction on which calling conventions may contain calls to chain
functions.
DeltaFile
+630-0llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
+5-7llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
+7-3llvm/lib/IR/Verifier.cpp
+642-103 files

LLVM/project c28c99fclang/test/SemaHIP amdgpu-gfx950-load-to-lds.hip

[NFC][HIP] Add __builtin_*_load_lds type check test cases (#165388)

This tests show how type-checking is performed for
`__builtin_amdgcn_load_to_lds`,
but not for `__builtin_amdgcn_raw_ptr_buffer_load_lds`,
`__builtin_amdgcn_struct_ptr_buffer_load_lds` and
`__builtin_amdgcn_global_load_lds` since they are declared with the 't'
attribute.


Stacked on top of: https://github.com/llvm/llvm-project/pull/165387
DeltaFile
+26-1clang/test/SemaHIP/amdgpu-gfx950-load-to-lds.hip
+26-11 files

LLVM/project dc8311fllvm/test/CodeGen/Thumb2 mve-vpt-2-blocks-ctrl-flow.mir mve-vpt-2-blocks.mir

[ARM] Remove IR from mve vpt mir tests. NFC

As far as I can tell the llvm.arm.mve.vminnm.m intrinsic used in these tests
was the pre-upstream name of llvm.arm.mve.min.predicated. The tests should not
need IR sections, so remove them just relying on the MIR portions.
DeltaFile
+5-28llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir
+2-24llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir
+2-23llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir
+2-23llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir
+2-23llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir
+2-23llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir
+15-1444 files not shown
+23-23010 files

LLVM/project 9cb9b16mlir/lib/Target/LLVMIR/Dialect/LLVMIR LLVMIRToLLVMTranslation.cpp, mlir/test/Target/LLVMIR/Import metadata-profiling.ll

[mlir][llvm] Fix import of branch weights with "expected" field (#169776)

This commit fixes the import of `branch_weights` metadata from LLVM IR
to the LLVM dialect. Previously, `branch_weights` metadata containing
the `!"expected"` field were rejected because the importer expected
integer weights at operand 1, but found a string.
DeltaFile
+36-0mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
+18-5mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.cpp
+54-52 files

LLVM/project 1c7ec06llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV uniform-load-store.ll tail-folding-fixed-order-recurrence.ll

[VPlan] Optimize LastActiveLane to EVL - 1 (#169766)

With EVL tail folding, the LastActiveLane can be computed with EVL - 1.
This removes the need for a header mask and vfirst.m for loops with live
outs on RISC-V:

     # %bb.5:                                # %for.cond.cleanup7
    -       vsetvli zero, zero, e32, m2, ta, ma
    -       vmv.v.x v8, s1
    -       vmsleu.vv       v10, v8, v22
    -       vfirst.m        a0, v10
    -       srli    a1, a0, 63
    -       czero.nez       a0, a0, a1
    -       czero.eqz       a1, s8, a1
    -       or      a0, a0, a1
    -       addi    a0, a0, -1
    -       vsetvli zero, zero, e64, m4, ta, ma
    -       vslidedown.vx   v8, v12, a0
    +       addi    s1, s1, -1
    +       vslidedown.vx   v8, v12, s1
DeltaFile
+2-12llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
+11-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-6llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
+1-6llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
+1-6llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
+1-5llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
+17-371 files not shown
+18-417 files

LLVM/project 008decallvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

[OpenMP][flang] Support GPU team reductions on allocatables

Extends the work started in #165714 by supporting team reductions.
Similar to what was done in #165714, this PR introduces proper
allocations, loads, and stores for by-ref reductions in teams-related
callbacks:
* `_omp_reduction_list_to_global_copy_func`,
* `_omp_reduction_list_to_global_reduce_func`,
* `_omp_reduction_global_to_list_copy_func`, and
* `_omp_reduction_global_to_list_reduce_func`.
DeltaFile
+148-47llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+121-0mlir/test/Target/LLVMIR/allocatable_gpu_reduction_teams.mlir
+14-10llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+2-0mlir/test/Target/LLVMIR/allocatable_gpu_reduction.mlir
+285-574 files

LLVM/project 0ab5258clang/include/clang/Analysis/Analyses/LifetimeSafety Origins.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp Origins.cpp

Multi-origin changes
DeltaFile
+153-371clang/test/Sema/warn-lifetime-safety-dataflow.cpp
+384-30clang/test/Sema/warn-lifetime-safety.cpp
+213-90clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+119-64clang/lib/Analysis/LifetimeSafety/Origins.cpp
+96-22clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
+56-30clang/unittests/Analysis/LifetimeSafetyTest.cpp
+1,021-6078 files not shown
+1,093-64414 files

LLVM/project aa61f21llvm/lib/Target/LoongArch LoongArchISelLowering.cpp

modify comment
DeltaFile
+1-1llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+1-11 files

LLVM/project 6abbbcallvm/lib/Transforms/AggressiveInstCombine AggressiveInstCombine.cpp, llvm/test/Transforms/AggressiveInstCombine umulh_carry4.ll umulh_ladder.ll

[AggressiveInstCombine] Match long high-half multiply (#168396)

This patch adds recognition of high-half multiply by parts into a single
larger multiply.

Considering a multiply made up of high and low parts, we can split the
multiply into:
  x * y == (xh*T + xl) * (yh*T + yl)
where `xh == x>>32` and `xl == x & 0xffffffff`. `T = 2^32`.
This expands to
  xh*yh*T*T + xh*yl*T + xl*yh*T + xl*yl
which I find it helpful to be drawn as
  [  xh*yh  ]
       [  xh*yl  ]
       [  xl*yh  ]
            [  xl*yl  ]

We are looking for the "high" half, which is xh*yh + xh*yl>>32 + xl*yh>>32 +
carrys. The carry makes this difficult and there are multiple ways of

    [15 lines not shown]
DeltaFile
+3,019-0llvm/test/Transforms/AggressiveInstCombine/umulh_carry4.ll
+858-0llvm/test/Transforms/AggressiveInstCombine/umulh_ladder.ll
+755-0llvm/test/Transforms/AggressiveInstCombine/umulh_carry.ll
+530-0llvm/test/Transforms/AggressiveInstCombine/umulh_ladder4.ll
+324-0llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+5,486-05 files

LLVM/project bb9449dllvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine get_vector_length.ll

[InstCombine] Fold @llvm.experimental.get.vector.length when cnt <= max_lanes (#169293)

On RISC-V, some loops that the loop vectorizer vectorizes pre-LTO may
turn out to have the exact trip count exposed after LTO, see #164762.

If the trip count is small enough we can fold away the
@llvm.experimental.get.vector.length intrinsic based on this corollary
from the LangRef:

> If %cnt is less than or equal to %max_lanes, the return value is equal
to %cnt.

This on its own doesn't remove the @llvm.experimental.get.vector.length
in #164762 since we also need to teach computeKnownBits about
@llvm.experimental.get.vector.length and the sub recurrence, but this PR
is a starting point.

I've added this in InstCombine rather than InstSimplify since we may
need to insert a truncation (@llvm.experimental.get.vector.length can

    [3 lines not shown]
DeltaFile
+89-0llvm/test/Transforms/InstCombine/get_vector_length.ll
+21-0llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+110-02 files

LLVM/project 71f25eallvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchLASXInstrInfo.td

[LoongArch] Make rotl/rotr custom for lsx/lasx
DeltaFile
+60-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+5-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+5-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+1-0llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+71-04 files

LLVM/project f1b04aellvm/test/CodeGen/LoongArch/lasx rotl-rotr.ll, llvm/test/CodeGen/LoongArch/lsx rotl-rotr.ll

add tests
DeltaFile
+36-71llvm/test/CodeGen/LoongArch/lasx/rotl-rotr.ll
+34-71llvm/test/CodeGen/LoongArch/lsx/rotl-rotr.ll
+70-1422 files

LLVM/project f1ddb2fllvm/test/CodeGen/LoongArch/lasx rotl-rotr.ll, llvm/test/CodeGen/LoongArch/lsx rotl-rotr.ll

[LoongArch][NFC] Pre-commit tests for vector rotl/rotr (#161115)

DeltaFile
+283-0llvm/test/CodeGen/LoongArch/lsx/rotl-rotr.ll
+283-0llvm/test/CodeGen/LoongArch/lasx/rotl-rotr.ll
+566-02 files

LLVM/project 326a1a4mlir/include/mlir/Dialect/XeGPU/IR XeGPUOps.td, mlir/lib/Dialect/XeGPU/IR XeGPUOps.cpp

[MLIR][XeGPU] Add anchor_layout and update propagation to honor user-specified layouts (#169267)

Introduce anchor layout for XeGPU anchor ops: load_nd, store_nd,
prefetch_nd, dpas, load, store, prefetch, load_matrix, store_matrix, and
atomic_rmw. Anchor layout is permanent, and is guaranteed to be honored
by XeGPU distribution and lowerinngs once specified.
1. Add anchor_layout for XeGPU anchor OPs: load_nd, store_nd,
prefetch_nd, dpas, load, store, prefetch, load_matrix, store_matrix, and
atomic_rmw.
2. rename layout attributes to anchor_layout for these ops: load, store,
load_matrix, store_matrix
3. update layout propagation pass: Only when user doesn't specify anchor
layout, the pass computes a default layout and set to anchor op's
permant layout and use that for propagation. if user specified anchor
layout, the pass takes user-specified anchor layout. permant layout and
use that for propagation. if user specified anchor layout, the pass
takes user-specified anchor layout.
DeltaFile
+329-119mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+267-177mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+41-40mlir/test/Dialect/XeGPU/propagate-layout.mlir
+13-11mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
+10-10mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
+10-2mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
+670-3591 files not shown
+670-3607 files

LLVM/project a9cc7fellvm/include/llvm/ProfileData SampleProf.h

[NFC][SampleFDO] Use const& to avoid copies (#164584)

Use const& in range-based for loop to avoid unnecessary copies
DeltaFile
+1-1llvm/include/llvm/ProfileData/SampleProf.h
+1-11 files

LLVM/project f6712b6libcxx/test/std/utilities/optional/optional.object/optional.object.ctor copy.pass.cpp move.pass.cpp

[libc++] Reformat `optional` constructor tests (#169231)

- Mass-reformat tests in
`std/utilities/optional/optional.object/optional.object.ctor` and
rearrange header `#include`s
- No functional changes
- Prelude for #169203
DeltaFile
+133-141libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/copy.pass.cpp
+110-117libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/move.pass.cpp
+94-113libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/rvalue_T.pass.cpp
+82-106libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/in_place_t.pass.cpp
+91-93libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/U.pass.cpp
+82-97libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_T.pass.cpp
+592-66711 files not shown
+978-1,11217 files

LLVM/project 82640a9clang/include/clang/Analysis/Analyses/LifetimeSafety Origins.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp Origins.cpp

Multi-origin changes
DeltaFile
+384-30clang/test/Sema/warn-lifetime-safety.cpp
+213-90clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+117-64clang/lib/Analysis/LifetimeSafety/Origins.cpp
+96-22clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
+56-30clang/unittests/Analysis/LifetimeSafetyTest.cpp
+27-7clang/lib/Analysis/LifetimeSafety/LifetimeSafety.cpp
+893-2437 files not shown
+931-27013 files

LLVM/project 07a2dbaclang/test/Sema/AArch64 arm_sve_feature_dependent_sve___sme.c, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

Merge branch 'main' into users/ylzsx/precommit-rotr-custom
DeltaFile
+53,205-51,210llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+18,277-15,993llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+19,255-3,889llvm/test/CodeGen/RISCV/atomic-rmw.ll
+19,470-0clang/test/Sema/AArch64/arm_sve_feature_dependent_sve___sme.c
+5,981-8,885llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
+5,981-8,885llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
+122,169-88,86220,850 files not shown
+1,624,754-725,03320,856 files