LLVM/project c417046flang-rt/lib/cuda allocator.cpp, flang/include/flang/Optimizer/Builder CUDAIntrinsicCall.h

[flang][cuda] Lower set/get default stream for arrays (#181432)

DeltaFile
+51-0flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
+39-0flang/module/cuda_runtime_api.f90
+24-0flang/test/Lower/CUDA/cuda-default-stream.cuf
+6-0flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
+2-4flang-rt/lib/cuda/allocator.cpp
+1-3flang/include/flang/Runtime/CUDA/allocator.h
+123-72 files not shown
+127-108 files

LLVM/project f980f21lldb/include/lldb/Core Highlighter.h, lldb/source/Plugins/Highlighter/TreeSitter TreeSitterHighlighter.cpp TreeSitterHighlighter.h

Avoid pointers
DeltaFile
+18-19lldb/source/Plugins/Highlighter/TreeSitter/TreeSitterHighlighter.cpp
+4-0lldb/include/lldb/Core/Highlighter.h
+1-1lldb/source/Plugins/Highlighter/TreeSitter/TreeSitterHighlighter.h
+23-203 files

LLVM/project 49fa2a4clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 rd-builtins.c

[CIR] Support x86 builtin rdtsc (#180714)

This PR implements CodeGen for rdtsc builtins in CIR upstream.
Towards #167765
DeltaFile
+36-0clang/test/CIR/CodeGenBuiltins/X86/rd-builtins.c
+17-4clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+53-42 files

LLVM/project 4aa5573.github/workflows prune-unused-branches.py

[Github] Only delete branches seen previously in pruning workflow (#181430)

This eliminates any possibility of race conditions around the workflow
deleting branches that were created around when it starts.
DeltaFile
+41-2.github/workflows/prune-unused-branches.py
+41-21 files

LLVM/project 304582c.github/workflows build-libc-container.yml, .github/workflows/containers/libc Dockerfile

[Github] Add libc container (#181434)

This will let us run the libc full build tests inside of a container
which means that we have same time by not having to install dependencies
on every run in addition to not running into issues due to dependencies
failing to install particularly around LLVM releases with the llvm.sh
script.
DeltaFile
+53-0.github/workflows/build-libc-container.yml
+24-0.github/workflows/containers/libc/Dockerfile
+77-02 files

LLVM/project a8124b1utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel][mlir] Fix #181286 Remove redundant SideEffectInterfaces from CAPIIR (#181435)

Remove redundant SideEffectInterfaces from CAPIIR. It's introduced in
#181286 due to merge.
DeltaFile
+0-1utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+0-11 files

LLVM/project 14beb29utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[mlir] fix #176920 Add SideEffectInterfaces to dependencies (#181286)

#176920 adds the dependency and breaks the bazel.  Fix private headers usage detected when layering check is enabled.
DeltaFile
+7-2utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+7-21 files

LLVM/project 7b01c69clang-tools-extra/clang-doc/assets head-template.mustache, clang-tools-extra/test/clang-doc basic-project.mustache.test

[clang-doc] Change highlight.js theme for light or dark themes (#181317)

Adds another `<link>` tag to load in a dark theme for highlight.js. The
appropriate theme is then loaded for the current system theme. Using a
dark theme for highlight.js in dark mode makes for a much better user
experience since declaration text has a higher contrast compared to the
dark background.
DeltaFile
+8-4clang-tools-extra/test/clang-doc/basic-project.mustache.test
+2-1clang-tools-extra/clang-doc/assets/head-template.mustache
+10-52 files

LLVM/project 6eeb03bllvm/lib/Target/RISCV RISCVISelDAGToDAG.cpp, llvm/test/CodeGen/RISCV add-imm64-to-sub.ll

[RISCV][NFC] Fix UBSan issue in ISel (#181422)

If `int Imm` is `INT64_MIN`, then negating this value overflows, which
is undefined behaviour. This adds this case to the tests, and avoids
this case.

Co-authored-by: Sampath Vutkoori <svutkoor at qti.qualcomm.com>
DeltaFile
+18-0llvm/test/CodeGen/RISCV/add-imm64-to-sub.ll
+2-0llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+20-02 files

LLVM/project 2938044.github/workflows prune-unused-branches.py

[Github] Account for cross-repo PRs in prune-unused-branches (#181232)

Some users (as reported in the discourse thread) use user branches
purely as a diff base for cross repo pull requests. This patch makes it
so that we do not delete branches that are used in this way.
DeltaFile
+38-19.github/workflows/prune-unused-branches.py
+38-191 files

LLVM/project d14cc97clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup! Improve error diagnostics, and other cleanups
DeltaFile
+12-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+4-2clang/lib/Sema/SemaARM.cpp
+2-1clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-0clang/lib/Headers/arm_acle.h
+1-1clang/include/clang/Basic/DiagnosticSemaKinds.td
+1-1clang/test/Sema/AArch64/pcdphint-atomic-store.c
+22-56 files

LLVM/project 7b099a4llvm/lib/Transforms/IPO LowerTypeTests.cpp, llvm/test/Transforms/LowerTypeTests cond-loop.ll

LowerTypeTests: Remove the optimization for llvm.cond.loop.

Because in the new IR pattern for conditional traps the llvm.cond.loop
is generated late, the LowerTypeTests pass will never see it, so we no
longer need to be able to optimize it. Therefore, remove the code for
optimizing it.

This reverts commit 1de721c414407f4b92d3e2458ce9ca38563cef9c.

Reviewers: fmayer, vitalybuka

Reviewed By: fmayer

Pull Request: https://github.com/llvm/llvm-project/pull/181301
DeltaFile
+0-45llvm/test/Transforms/LowerTypeTests/cond-loop.ll
+5-20llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+5-652 files

LLVM/project 55857e1clang/lib/CodeGen CGExpr.cpp, clang/test/CodeGenCXX sanitize-trap-loop.cpp

CodeGen: Switch to generating llvm.looptrap instead of llvm.cond.loop.



Reviewers: fmayer, vitalybuka

Reviewed By: fmayer

Pull Request: https://github.com/llvm/llvm-project/pull/181300
DeltaFile
+8-9clang/lib/CodeGen/CGExpr.cpp
+6-4clang/test/CodeGenCXX/sanitize-trap-loop.cpp
+14-132 files

LLVM/project b703f63llvm/docs LangRef.rst, llvm/include/llvm/IR Intrinsics.td

Add llvm.looptrap intrinsic.

The '``llvm.looptrap``' intrinsic is equivalent to
``llvm.cond.loop(true)``, but is also considered to be ``noreturn``,
which enables certain optimizations by allowing the optimizer to
assume that a branch leading to a call to this intrinsic was not
taken. A late optimization pass will convert this intrinsic to either
``llvm.cond.loop(true)`` or ``llvm.cond.loop(pred)``, where ``pred``
is a predicate for a conditional branch leading to the intrinsic call,
if possible.

Reviewers: fmayer, vitalybuka

Pull Request: https://github.com/llvm/llvm-project/pull/181299
DeltaFile
+155-0llvm/test/Transforms/PreISelIntrinsicLowering/looptrap.ll
+48-0llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+22-0llvm/docs/LangRef.rst
+2-0llvm/include/llvm/IR/Intrinsics.td
+227-04 files

LLVM/project 5223400llvm/docs LangRef.rst, llvm/lib/CodeGen PreISelIntrinsicLowering.cpp

Note revert in commit message

Created using spr 1.3.6-beta.1
DeltaFile
+7-7llvm/docs/LangRef.rst
+11-0llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+18-72 files

LLVM/project cbae61bllvm/docs LangRef.rst, llvm/lib/CodeGen PreISelIntrinsicLowering.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+7-7llvm/docs/LangRef.rst
+11-0llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+18-72 files

LLVM/project 8f33584llvm/docs LangRef.rst, llvm/lib/CodeGen PreISelIntrinsicLowering.cpp

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+7-7llvm/docs/LangRef.rst
+11-0llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+18-72 files

LLVM/project 7dafd1cllvm/docs LangRef.rst, llvm/lib/CodeGen PreISelIntrinsicLowering.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+7-7llvm/docs/LangRef.rst
+11-0llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+18-72 files

LLVM/project a584ecallvm/docs LangRef.rst, llvm/lib/CodeGen PreISelIntrinsicLowering.cpp

Add comments, fix formatting, traduire en anglais

Created using spr 1.3.6-beta.1
DeltaFile
+7-7llvm/docs/LangRef.rst
+11-0llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+18-72 files

LLVM/project d485417libcxx/docs index.rst, libcxx/docs/ReleaseNotes 22.rst

[libc++] Increase the minimum deployment target on macOS to 11.0 (#176094)

#166172 moved the effective minimum deployment target on macOS to 10.15
(because `aligned_alloc` is not defined before that in the C stdlib),
and indeed, it was mentioned in that PR that libc++ only supports macOS
11 and later.

This PR rectifies the documentation and the code to reflect the actually
supported deployment targets on macOS. See [1] for additional discussion
about this.

[1]: https://discourse.llvm.org/t/minimum-macos-deployment-target-increases-to-11-0-in-v22-1-visibility-discussion-on-update-policy
DeltaFile
+3-3libcxx/include/__configuration/availability.h
+2-0libcxx/docs/ReleaseNotes/22.rst
+1-1libcxx/docs/index.rst
+6-43 files

LLVM/project fa5f4afllvm/tools/llubi/lib Interpreter.cpp

[llubi] Return void for `InstExecutor::visit*` methods. NFC. (#181421)

The status is now maintained inside of `setResult` and other helper
functions. So we don't need to propagate the error.
This patch was part of https://github.com/llvm/llvm-project/pull/181393.
DeltaFile
+177-189llvm/tools/llubi/lib/Interpreter.cpp
+177-1891 files

LLVM/project a38584eclang/include/clang/DependencyScanning DependencyScanningService.h, clang/lib/DependencyScanning ModuleDepCollector.cpp DependencyScannerImpl.cpp

[clang][deps] Extract service config into a struct (#181405)

Adding new configuration knobs in the scanner is fairly painful now,
especially with a diverging downstream. This patch extracts what was
previously passed into the service constructor into a struct. This
encourages one knob customization per line, reduces difficult merge
conflicts, `/*ArgName=*/`-style comments with copy-pasted defaults, etc.
DeltaFile
+25-33clang/include/clang/DependencyScanning/DependencyScanningService.h
+10-10clang/lib/DependencyScanning/ModuleDepCollector.cpp
+9-8clang/lib/DependencyScanning/DependencyScannerImpl.cpp
+5-8clang/lib/DependencyScanning/DependencyScanningService.cpp
+8-3clang/tools/clang-scan-deps/ClangScanDeps.cpp
+6-4clang/unittests/Tooling/DependencyScannerTest.cpp
+63-663 files not shown
+73-729 files

LLVM/project 75cc975llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVISelDAGToDAG.cpp, llvm/test/CodeGen/RISCV rv32p.ll

[RISCV] Combine ADDD(lo, hi, x, 0) -> WADDAU(lo, hi, x, 0). Combine WADDAU (WADDAU lo, hi, x, 0), y, 0 -> WADDAU lo, hi, x, y (#181396)

WADDAU is rd += zext(rs1) + zext(rs2)

If we only have 1 32-bit input can force rs2 to avoid zeroing the upper
part of a register pair to use ADDD.

Unfortunately, WADDAU clobbers rd so it might need a GPRPair copy
if we need the old value of rd. We might need to look into that in
the future. Maybe we could have convertToThreeAddress could turn
it back into ADDD+WADDU or ADDD+LI.

Assisted-by: claude
DeltaFile
+48-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+40-6llvm/test/CodeGen/RISCV/rv32p.ll
+27-18llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+9-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+124-244 files

LLVM/project 65deb6cllvm/lib/Target/Hexagon HexagonGlobalScheduler.cpp, llvm/test/CodeGen/Hexagon global-sched-skip-vsub_fake.ll pull-up-slots.mir

Revert "Add HexagonGlobalScheduler pass (#180803)" (#181418)

This reverts commit 892ac614bf8fafd4d13381bb45b369721309785a.
DeltaFile
+0-5,319llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
+0-831llvm/test/CodeGen/Hexagon/global-sched-skip-vsub_fake.ll
+0-363llvm/test/CodeGen/Hexagon/pull-up-slots.mir
+0-311llvm/test/CodeGen/Hexagon/avoid-debug-increment.mir
+0-305llvm/test/CodeGen/Hexagon/dbg-label-pullup.ll
+0-268llvm/test/CodeGen/Hexagon/pull-delayed-new.mir
+0-7,39710 files not shown
+4-7,71216 files

LLVM/project e9034b6clang/include/clang/Basic BuiltinsAArch64.def, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup!

More small issues tidied, and remove gating.
DeltaFile
+6-2clang/test/Sema/AArch64/pcdphint-atomic-store.c
+2-2clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+0-2clang/lib/Headers/arm_acle.h
+1-1clang/lib/Sema/SemaARM.cpp
+1-1clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+1-1clang/include/clang/Basic/BuiltinsAArch64.def
+11-96 files

LLVM/project bc632a6clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/Sema/AArch64 pcdphint-atomic-store.c

fixup!

A few small tidyups
DeltaFile
+7-6clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4-4llvm/lib/Target/AArch64/AArch64InstrFormats.td
+4-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+15-103 files

LLVM/project ebdd55bclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin

Add `__arm_atomic_store_with_stshh` implementation as defined
in the ACLE. Validate that the arguments passed are correct, and
lower it to the stshh intrinsic plus an atomic store with the
allowed orderings.

Gate this on FEAT_PCDPHINT so that availability matches
hardware support for the `STSHH` instruction. Use an i64
immediate and side-effect modeling to satisfy tablegen and decoding.
DeltaFile
+140-0clang/lib/Sema/SemaARM.cpp
+48-0clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+31-0clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+29-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+13-0llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+10-2llvm/lib/Target/AArch64/AArch64InstrFormats.td
+271-25 files not shown
+298-211 files

LLVM/project 49b4991clang/include/clang/Basic BuiltinsAArch64.def, clang/lib/CodeGen/TargetBuiltins ARM.cpp

fixup!

More small issues tidied, and remove gating.
DeltaFile
+6-2clang/test/Sema/AArch64/pcdphint-atomic-store.c
+2-2clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+1-1clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+1-1clang/lib/Sema/SemaARM.cpp
+0-2clang/lib/Headers/arm_acle.h
+1-1clang/include/clang/Basic/BuiltinsAArch64.def
+11-96 files

LLVM/project b3dcf48llvm/lib/Transforms/Vectorize VPlan.cpp VPlanHelpers.h, llvm/test/Transforms/LoopVectorize/AArch64 conditional-branches-cost.ll

[VPlan] Compute NumPredStores for VPReplicateRecipe costs in VPlan.

Compute the number of predicated stores directly in VPlan instead of
using CM.useEmulatedMaskMemRefHack(), which will only account for the
number of predicated stores for the last VF the legacy cost model
considered.

Fixes https://github.com/llvm/llvm-project/issues/181183
DeltaFile
+69-0llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
+30-0llvm/lib/Transforms/Vectorize/VPlan.cpp
+5-3llvm/lib/Transforms/Vectorize/VPlanHelpers.h
+1-5llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1-1llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+106-95 files

LLVM/project b692925clang/include/clang/StaticAnalyzer/Core/PathSensitive CoreEngine.h, clang/lib/StaticAnalyzer/Core ExprEngineCXX.cpp

[NFC][analyzer] Remove NodeBuilder::iterator (#181381)

This iterator class was used only once and even there it was easily
replaced by a more appropriate solution.

This commit is motivated by the fact that my recent commit
320d0b5467b9586a188e06dd2620126f5cb99318 turned
`IndirectGotoNodeBuilder` and `SwitchNodeBuilder` into subclasses of
`NodeBuilder` and those classes have their own (slightly more useful)
`::iterator`s with very different behavior.
DeltaFile
+0-7clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h
+3-4clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
+3-112 files