Revert "[Driver][SYCL] Add compile-time device library linking for SPIR-V targets" (#212550)
Reverts llvm/llvm-project#196656
The CI does not yet build compiler-rt with SPIR-V support, so
libclang_rt.builtins.bc is absent on that bot. This change made the
missing file a hard error, breaking all libsycl functional tests that
compile with -fsycl.
Re-landing after CI is updated to build compiler-rt for SPIR-V.
PowerPC: Rename "float-abi" module flag to "long-double-type" (#210817)
PPC was emitting a "float-abi" module flag for indicating the type of
long double. The "float ABI" naming is already widely taken by soft vs.
hard float controls (e.g., the clang flag is called -mfloat-abi), so this
shouldn't have taken it. This should also not be PPC specific; x86 has
the same problem. Rename the flag to the more specific
long-double-type, and add appropriate verification and documentation
(which was also missing). Also changes the value names to match the IR
type names.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[clang][ClangScanDeps] Relax logging-two-threads for duplicate module validation (#210587)
`ClangScanDeps/logging-two-threads.c` is flaky. It asserts each module's
timestamp is written exactly once, but under
`-fmodules-validate-once-per-build-session` two workers scanning
different TUs can both notice the shared module is unvalidated this
session and each validate and record it before the other's write lands,
so its timestamp is written once or twice depending on the interleaving.
The double write is harmless: the timestamp field is atomic and both
workers store the same session time. Only the exact-count assertion was
wrong.
Relax the test to the real invariant: the shared module A is written
once or twice and the single-TU module B exactly once. Module compile
and pcm write stay exactly once (the in-memory cache builds each module
once) and the per-module event ordering is still checked by the sequence
blocks.
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[CodeGen] Stop requiring analyses that no pass reads (#212430)
Remove analysis requirements whose pass never calls getAnalysis for
them, and MachineSchedContext::MDT, which no scheduler reads. Also remove
addPreserved calls subsumed by setPreservesCFG (MachineDominatorTree and
MachineLoopInfo are CFG-only analyses) and a now-unpaired INITIALIZE_PASS_DEPENDENCY.
The PowerPC, Hexagon and R600 pipelines each drop a MachineDominatorTree
construction.
Aided by Claude Opus 5
[SPIRV] Preserve sign-sensitive width record across G_TRUNC replacement (#211626)
**Summary**
Follow-up to #203661. When the `G_TRUNC` handler in `SPIRVPreLegalizer`
collapses source and destination to the same widened width, it calls
`MRI.replaceRegWith(DstReg, MaskedReg)` and drops the original
`G_TRUNC`. The `SignSensitiveInfo.OrigWidth` map, however, was still
keyed on `DstReg`, so `widenSignSensitiveOps` no longer found the narrow
original width and skipped the `shl/ashr` sign extension for signed
users of the truncated value.
Rekey `OrigWidth` from `DstReg` to `MaskedReg` before the
`replaceRegWith` so signed ops fed by the truncated value still receive
`G_SEXT_INREG` on the widened type.
**Test plan**
New test case is added to
`llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll`: `trunc i8 →
i4` feeding `icmp slt` — src and dst both widen to `i8`, exercising the
same-width `replaceRegWith` path. Checks that the widened `i8` compare
is preceded by matching `OpShiftLeftLogical / OpShiftRightArithmetic`
pairs on both operands.
[SimplifyCFG] Handle degenerate conditional branch (#212552)
IR before entering the function:
```
define void @func(i1 %cond) {
entry:
br i1 %cond, label %exit, label %exit
exit: ; preds = %entry, %entry
%phi = phi i1 [ false, %entry ], [ false, %entry ]
tail call void @llvm.assume(i1 %phi)
ret void
}
```
The original code only removes one edge. There is still an edge from
entry to exit, triggering the `Deleted edge still exists in the CFG`
assertion.
Closes https://github.com/llvm/llvm-project/issues/212542
[asan][NFC] Fix comments in asan_poisoning.cpp (#212449)
Remove duplicated wording and fix typos in comments.
Signed-off-by: Jinseok Kim <always.starving0 at gmail.com>
[lldb] Report the unwound PC for WebAssembly caller frames (#212326)
RegisterContextWasm delegated the PC register read to
GDBRemoteRegisterContext, which reports the live innermost PC for every
frame. Resolving a variable whose DWARF location is a location list in a
caller frame therefore chose the entry using the innermost frame's PC
instead of the caller's, so the variable read back as unavailable even
though its location covered the caller's PC.
Return the program counter the WebAssembly unwinder recorded for the
frame (from qWasmCallStack) when reading a caller frame's PC, so the
location list entry uses the correct frame.
[CIR] Accept __int128 in x86_64 calling-convention lowering (#211142)
The x86_64 calling-convention bridge rejected every integer wider than 64
bits, so a function taking or returning `__int128` hit `errorNYI` even though
its ABI treatment is simple.
On x86_64 `__int128` is Direct and passes in a pair of integer registers,
matching an i128 argument or return in classic CodeGen. `isSupportedType` now
accepts non-bitint integers of width 128 alongside the register-sized widths.
A struct holding a single `__int128` is exactly two eightbytes, so it reaches
the aggregate path and is Direct-coerced to i128; a struct spanning more than
two eightbytes stays Indirect (byval/sret).
`_BitInt` stays rejected pending its register-pair coercion and padding
handling, including `_BitInt(128)`. Non-C intermediate widths (65..127) stay
rejected too: the scalar Direct branch would pass them through unchanged,
without the register-pair coercion they would need.
[NFC][VPlan] Add initial tests for future VPlan-based stride MV (#182594)
I tried to include both the features that current
LoopAccessAnalysis-based transformation supports (e.g., trunc/sext of
stride) but also cases where the current implementation behaves poorly,
e.g., https://godbolt.org/z/h31c3zKxK; as well as some other potentially
interesting scenarios I could imagine.
The are two test files with the same content. One is for VPlan dump
change of the future transformation alone (I'll update
`-vplan-print-after` in the next PR), another is for the full vectorizer
pipeline. The latter has two `RUN:` lines:
* No multiversioning, so the next PR diff can show the transformation
itself
* Stride multiversionin performed in LAA, so that we can compare next
PR's
VPlan-based transformation vs old behavior.
[test] Use temp directory for output (#212379)
Test was added in #208072
Some test environment run tests in a readonly directory. Writing is only
allowed in temp directory.
[mlir] Make lit site configs relocatable (#212406)
Follow the same pattern as all the other test suites where the PATHS
option to configure_lit_site_cfg and the path() function in the lit site
config are used to make site configs relocatable.
[llvm-objcopy] Address review feedback for AMDGPU test in cross-arch-headers
Per reviewer feedback, use the existing non-AMDGPU input (%t.o, EM_NONE)
to test conversion to elf64-amdgpu. This properly demonstrates that
--output-format changes the machine type, consistent with all other cases
in this test file.
The output reports Arch: unknown because converting from a non-AMDGPU ELF
produces e_flags=0 (no EF_AMDGPU_MACH set); added a comment explaining
this. Flag control is a separate concern for a follow-on PR.
[libc++] Reduce sequence container benchmark size ladder (#212281)
The sequence containers were registered for 32, 1024 and 8192. This
patch drops the mid-size point to get roughly a 30% speedup when running
the benchmarks.
[libc++] Drop char8_t instantiation from string benchmarks (#212283)
The string benchmarks instantiated every benchmark for char, char8_t and
wchar_t. char8_t exercises the same code paths as char, so drop it to
get roughly a 30% speedup on this benchmark time.
[libc++] Defer removal of two escape hatches to LLVM 25 (#211553)
Rather than removing the escape hatches for trivially default
constructible allocator and bitset's const reference type in LLVM 24,
keep them around for another release since they have not been widely
deployed yet.
[llvm-objcopy] Add AMDGPU case to binary-output-target.test
Add test coverage for converting binary input to elf64-amdgpu format,
verifying the output has the correct format string, arch (amdgpu),
and machine type (EM_AMDGPU 0xE0). Follows the same pattern as all
other architectures in this test file.
[llvm-objcopy] Fix AMDGPU arch string in test: amdgpu not amdgcn
llvm-readobj reports 'Arch: amdgpu' for EM_AMDGPU ELF files
(the generic AMDGPU ELF format used by elf64-amdgpu). The test
was incorrectly expecting 'amdgcn', which is the AMDGCN-specific
arch string used by ROCm HSA code objects.
[llvm-objcopy] Fix AMDGPU arch checks in tests
ELFObjectFile.h getArch() for EM_AMDGPU returns Triple::UnknownArch
when e_flags & EF_AMDGPU_MACH is 0 (no GPU target specified). Only
when a MACH flag in the AMDGCN range is present does it return
Triple::amdgpu.
- cross-arch-headers.test: restore EF_AMDGPU_MACH_AMDGCN_GFX900 flag
on the input ELF so that after format conversion the output correctly
reports Arch: amdgpu.
- binary-output-target.test: expect Arch: unknown since converting
from raw binary input (-I binary) produces an ELF with e_flags=0
(no MACH flags), giving UnknownArch. This is correct behavior.
