[clang] Integrate LLVMABI for function call ABI lowering (#194460)
This PR wires the LLVM ABI library (prototyped in
https://github.com/llvm/llvm-project/pull/140112) into Clang's function
call ABI lowering pipeline, behind a new `-fexperimental-abi-lowering`
cc1 flag.
When the flag is enabled and the active target has an LLVMABI
implementation, `CodeGenTypes::arrangeLLVMFunctionInfo` constructs an
`llvm::abi::FunctionInfo` from the call's argument and result types
(using QualTypeMapper(https://github.com/llvm/llvm-project/pull/174634)
to translate Clang QualTypes into ABI types).
Asks the target's `llvm::abi::TargetInfo` to classify it, and then
translates each `llvm::abi::ArgInfo` back into the ABIArgInfo consumed
by the rest of CodeGen. The translation is handled by a new
`convertABIArgInfo` helper covering the Direct, Extend, Indirect, and
Ignore kinds, with coerce-to types lifted back into LLVM IR via a new
IRTypeMapper.
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[MLIR][SPIRV] Enable strict property assembly format
Enable strict property assembly format mode for SPIR-V and add property
dictionaries to declarative formats that still carry inherent attributes outside
explicit operands or clauses.
Refresh ARM graph and TOSA tests so GraphConstant uses prop-dict spelling for
its inherent constant identifier.
Assisted-by: Codex
[MLIR][NVVM] Enable strict property assembly format
Enable strict property assembly format mode for the NVVM dialect and update
custom assembly formats to expose property dictionaries explicitly.
Refresh NVVM tests so inherent operation properties are printed and parsed
through the property dictionary while non-property attributes remain in the
attribute dictionary.
Assisted-by: Codex
[Flang][OpenMP] Fix Flang crash and incorrect ordering with OpenMP detached task (#194840)
Fixes - [#194563](https://github.com/llvm/llvm-project/issues/194563)
This PR fixes the runtime crash and incorrect task ordering reported in
the testcase involving:
```
!$omp task if(.false.) depend(out:x) detach(ev)
```
The testcase had two issues:
**1. Segmentation fault near omp_fulfill_event(ev)**
The detach event handle was not being initialized or preserved correctly
before the nested task used it.
**2. Incorrect execution order**
The task with depend(in:x) was running before the detach event was
fulfilled, which violates OpenMP dependency semantics.
#### Changes in this PR
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[MLIR][ControlFlow] Enable strict property assembly format
Enable the strict properties assembly format mode for the ControlFlow dialect.
The dialect formats already cover their inherent attributes, except for a test
that still used attr-dict spelling for branch weights.
Update that test to use the existing weights(...) syntax so the inherent
attribute is parsed through the declarative format.
Assisted-by: Codex
[Flang][OpenMP] Preserve MapInfoOp loc on descriptor base-address maps (#196086)
This PR tries to fix another issue which was discovered after
https://github.com/llvm/llvm-project/issues/195333 was fixed. Now when
we run the same steps, we see the following output
```
omptarget device 0 info: Entering OpenMP data region with being_mapper at test.f90:18:9 with 5 arguments:
omptarget device 0 info: alloc(ptr(1:1024))[48]
omptarget device 0 info: to(ptr(1:1024))[0]
omptarget device 0 info: to(ptr(1:1024))[40]
omptarget device 0 info: to(unknown)[8]
omptarget device 0 info: to(unknown)[4096]
```
Notice "unknown" in the last 2 lines. This happens because
`MapInfoFinalization` splits box descriptor `omp.map.info` ops into a
parent map and a base-address member map (fir.box_offset + inner map
with var_ptr_ptr). The `genBaseAddrMap` used `descriptor.getLoc()` for
those new ops, which dropped the `NameLoc` that lowering attaches for
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[BOLT][AArch64] Refuse to run retpoline insertion pass (#196179)
RetpolineInsertion (`--insert-retpolines`) is specific to X86, but
currently rejects non-X86 targets with an assert. For consistency, this
should be an error message.
- Add a non-X86 guard
- Add the error message to unsupported-passes.test
[BOLT][AArch64] Refuse to run memcpy1 specialization (#196196)
SpecializeMemcpy1 (`--memcpy1-spec=main`) is implemented only for X86.
It does not crash but would be useful to inform the user that it is a
no-op.
- Guard against non-X86
- Add error to unsupported-passes.test
[flang] Remove legacy (non-HLFIR) lowering options from tests (#196137)
Update flang LIT tests to drop references to compiler options that
controlled legacy non-HLFIR lowering: `-flang-experimental-hlfir`,
`-flang-deprecated-no-hlfir`, the bbc `-hlfir`/`--hlfir` switch, and
`--use-desc-for-alloc=false`. The dropped flags were either no-ops or
selected behavior that is now the only supported lowering path.
Delete `Driver/hlfir-no-hlfir-error.f90`, which existed solely to test
mutual exclusion of `-flang-experimental-hlfir` and
`-flang-deprecated-no-hlfir`.
This commit contains only test changes; the option/code removal will be
done in separate commits.
Assisted-by: AI
[lldb] Trim and show embedded zeros in `charN_t` arrays (#195514)
When formatting `char[N]` (N > 0), the read buffer is limited to the
array size and trailing zeros are trimmed.
`charN_t[N]` was treated like a `charN_t *` and the formatter read until
the first zero byte.
If the array doesn't have any zero bytes in it, this will read too much.
If the array has zero bytes in it, it will show too little.
With this PR, `wchar_t[N]` and `charN_t[N]` are printed like `char[N]`.
[MLIR][ODS] Add strict property assembly format mode
Introduce a dialect-level ODS flag for strict property handling in declarative
assembly formats. It is disabled by default for now, preserving existing parser
behavior unless a dialect opts in.
Enable the mode immediately for dialects whose declarative assembly formats
already satisfy these binding rules.
When enabled, a property-backed op format must bind every inherent attribute
and property directly or include prop-dict.
Generated parsers for opted-in dialects also reject inherent attributes that
arrive through attr-dict, preventing Operation::setAttrs from populating
properties through that path.
Add mlir-tblgen coverage and document default and strict dialect behavior.
Assisted-by: Codex
[SelectionDAG] Support vector types in llvm.convert.from.arbitrary.fp expansion (#196185)
Move the bit-twiddling expansion of ISD::CONVERT_FROM_ARBITRARY_FP from
LegalizeDAG to TargetLowering and make it working on vector destination
types.
[TableGen][GlobalISel] Skip REG_SEQUENCE with incompatible subreg index (#196184)
The REG_SEQUENCE branch of GlobalISelEmitter::constrainOperands called
SuperClass->getMatchingSubClassWithSubRegs(...) and dereferenced the
returned SrcRCDstRCPair unconditionally, aborting on a libstdc++
optional assertion when incorrect subreg index was passed.
Add the missing guard so the malformed pattern is reported via
failedImport (a skipped pattern) instead of crashing tblgen.
Assisted by Claude.
Fixes https://github.com/llvm/llvm-project/issues/172690
[mlir][SPIR-V] Add support for SPV_INTEL_long_composites extension (#195685)
Add serialization and deserialization support for the
SPV_INTEL_long_composites extension, which allows splitting
composite/struct instructions that exceed the SPIR-V 16-bit word count
limit (65535 words) into a head instruction followed by one or more
continuation instructions
[LV][NFC] Remove simplifycfg pass from RUN lines (#195817)
All the simplifycfg pass really did was remove empty blocks. I don't
believe it added any real value, but it does make the tests run slower.
[clang-tidy] Reject malformed -std spellings in `check_clang_tidy.py`. NFC. (#195609)
`check_clang_tidy.py` expanded any `-std` value containing `-or-later`,
even when extra text followed the suffix. e.g. `c++20-or-latermisc` was
treated like `c++20-or-later`.
This commit requires `-or-later` to be the actual end of the spelling
before expanding it, so malformed values are passed through and
diagnosed by clang.
[AArch64][GlobalISel] Clean up and extend BF16 tests. NFC (#196175) (#196255)
This attempts to fill in the gap between the different bf16 test files,
making sure they all contain the same tests.
