LLVM/project e570faaclang/lib/Driver/ToolChains HIPAMD.cpp, clang/test/Driver hip-toolchain-no-rdc.hip spirv-amd-toolchain.c

[SPIR-V][HIP] Disable SPV_KHR_untyped_pointers (#183530)

SPV_KHR_untyped_pointers in SPIR-V to LLVM translator is incomplete with
few known issues. Therefore we better not to rely on this extension for SPIR-V
generation.
DeltaFile
+1-1clang/lib/Driver/ToolChains/HIPAMD.cpp
+1-1clang/test/Driver/hip-toolchain-no-rdc.hip
+1-1clang/test/Driver/spirv-amd-toolchain.c
+3-33 files

LLVM/project acb8a6dllvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 neon-extractbitcast-mir.ll

[AArch64] Fix type mismatch in bitconvert + vec_extract patterns (#183549)

This patch fixes mismatch in element width during isel of bitconvert +
vec_extract nodes. This resolves issue reported on
[this](https://github.com/llvm/llvm-project/pull/172837) PR.
DeltaFile
+18-0llvm/test/CodeGen/AArch64/neon-extractbitcast-mir.ll
+2-2llvm/lib/Target/AArch64/AArch64InstrInfo.td
+20-22 files

LLVM/project c9d065allvm/test/CodeGen/X86 shift-i256.ll funnel-shift-i256.ll

[X86] Add i256 shift / funnel shift coverage to match i512 tests (#184346)

shift-i256.ll - added x86-64/x86-64-v2/x86-64-v3/x86-64-v4 coverage and retained the x86 test coverage
DeltaFile
+3,169-313llvm/test/CodeGen/X86/shift-i256.ll
+2,056-0llvm/test/CodeGen/X86/funnel-shift-i256.ll
+5,225-3132 files

LLVM/project 5b976c9libc/include/llvm-libc-macros/linux sys-ipc-macros.h, libc/include/llvm-libc-types struct_ipc_perm.h

[libc][sys] add header and functions for sys ipc (#182700)

Split from a larger change. This PR contains the base impl for sys ipc,
sys sem will come after this. @SchrodingerZhu

this PR implements for:
https://github.com/llvm/llvm-project/issues/182161

see the last PR for more detail:
https://github.com/llvm/llvm-project/pull/182683
DeltaFile
+59-0libc/test/src/sys/ipc/linux/ftok_test.cpp
+51-0libc/include/sys/ipc.yaml
+38-0libc/src/sys/ipc/linux/ftok.cpp
+34-0libc/src/sys/ipc/linux/kernel_statx.h
+34-0libc/include/llvm-libc-types/struct_ipc_perm.h
+24-0libc/include/llvm-libc-macros/linux/sys-ipc-macros.h
+240-018 files not shown
+421-024 files

LLVM/project c782e2dllvm/lib/Target/SPIRV SPIRVModuleAnalysis.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers fun-ptr-service-func.ll

[SPIRV] Don't emit service function basic block names (#184206)

Right now if a module has a service function we always emit `OpName
entry` for the service function's basic block.

The actual service function isn't emitted and no other instruction uses
the basic block `OpName` instruction, so don't emit it.

Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
DeltaFile
+6-3llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
+4-0llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+1-1llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-service-func.ll
+11-43 files

LLVM/project bbde3e3llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize if-pred-stores.ll

[VPlan] Preserve IsSingleScalar for sunken predicated stores. (#184329)

The predicated stores may be single scalar (e.g. for VF = 1). We should
preserve IsSingleScalar. As all stores access the same address,
IsSingleScalar must match across all stores in the group.

This fixes an assertion when interleaving-only with sunken stores.

Fixes https://github.com/llvm/llvm-project/issues/184317

PR: https://github.com/llvm/llvm-project/pull/184329
DeltaFile
+181-0llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
+7-5llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+188-52 files

LLVM/project 7c2c505llvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Move rollback capabilities outside of the rematerializer

The rematerializer implements support for rolling back
rematerializations by modifying MIs that should normally be deleted in
an attempt to make them "transparent" to other analyses. This involves:

1. setting their opcode to DBG_VALUE and
2. setting their read register operands to the sentinel register.

This approach has several drawbacks.

1. It forces the rematerializer to support tracking these "dead MIs".
2. It is not actually clear whether this mechanism will interact well
   with all other analyses. This is an issue since the intent of the
   rematerializer is to be usable in as many contexts as possible.
3. In practice, it has shown itself to be relatively error-prone.

This commit removes rollback support from the rematerializer and moves
those capabilties to a rematerializer listener than can be instantiated

    [5 lines not shown]
DeltaFile
+153-130llvm/lib/CodeGen/Rematerializer.cpp
+98-80llvm/include/llvm/CodeGen/Rematerializer.h
+108-23llvm/unittests/CodeGen/RematerializerTest.cpp
+359-2333 files

LLVM/project 8b1ec1cllvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Allow rematerializer to rematerialize at the end of a block

This makes the rematerializer able to rematerialize MIs at the end of a
basic block. We achive this by tracking the parent basic block of every
region inside the rematerializer and adding an explicit target region to
some of the class's methods. The latter removes the requirement that we
track the MI of every region (`Rematerializer::MIRegion`) after the
analysis phase; the class member is therefore deleted.

This new ability will be used shortly to improve the design of the
rollback mechanism.
DeltaFile
+35-25llvm/lib/CodeGen/Rematerializer.cpp
+32-27llvm/include/llvm/CodeGen/Rematerializer.h
+16-14llvm/unittests/CodeGen/RematerializerTest.cpp
+83-663 files

LLVM/project ef56bdellvm/lib/CodeGen Rematerializer.cpp

Format
DeltaFile
+1-1llvm/lib/CodeGen/Rematerializer.cpp
+1-11 files

LLVM/project d41b7fflibsycl/docs index.rst, libsycl/include/sycl/__impl queue.hpp property_list.hpp

fix comments

Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
DeltaFile
+15-23libsycl/include/sycl/__impl/queue.hpp
+7-16libsycl/src/detail/queue_impl.hpp
+2-2libsycl/include/sycl/__impl/detail/default_async_handler.hpp
+1-1libsycl/include/sycl/__impl/property_list.hpp
+1-1libsycl/docs/index.rst
+1-1libsycl/include/sycl/__impl/async_handler.hpp
+27-446 files

LLVM/project 1eeb2ecclang-tools-extra/clang-tidy/bugprone StdNamespaceModificationCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Handle specialization of user-defined type in `bugprone-std-namespace-modification` (#183984)

Ignore `templateSpecializationType` based on user-define classes too.

Fixes #183752
DeltaFile
+15-0clang-tools-extra/test/clang-tidy/checkers/bugprone/std-namespace-modification.cpp
+7-4clang-tools-extra/clang-tidy/bugprone/StdNamespaceModificationCheck.cpp
+5-0clang-tools-extra/docs/ReleaseNotes.rst
+3-0clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/system-header-simulation.h
+30-44 files

LLVM/project 33864eflld/COFF Driver.cpp, lld/wasm OutputSections.cpp

[lld] Turn misc copy-assign to move-assign (#184145)

That's an automated patch generated from clang-tidy
performance-use-std-move as a follow-up to #184136
DeltaFile
+1-1lld/COFF/Driver.cpp
+1-1lld/wasm/OutputSections.cpp
+2-22 files

LLVM/project 3b20f09clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp

Tweak NYI msgs
DeltaFile
+8-15clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+8-151 files

LLVM/project 0991e23llvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp

[CodeGen] Add listener support to the rematerializer (NFC)

This change adds support for adding listeners to the
target-independent rematerializer; listeners can catch certain
rematerialization-related events to implement some additional
functionnality on top of what the rematerializer already performs.

This has no user at the moment, but the plan is to have listeners start
being responsible for secondary/optional functionnalities that are at
the moment integrated with the rematerializer itself. Two examples of
that are:
1. rollback support (currently optional), and
2. region tracking (currently mandatory, but not fundamentally necessary
   to the rematerializer).
DeltaFile
+43-0llvm/include/llvm/CodeGen/Rematerializer.h
+7-1llvm/lib/CodeGen/Rematerializer.cpp
+50-12 files

LLVM/project 534d6e8llvm/include/llvm/Analysis BlockFrequencyInfoImpl.h

[Analysis][NFC] Store CallbackVH in vector, not in map (#184323)

This avoid non-trivial move operations whenever the map grows.
DeltaFile
+31-30llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+31-301 files

LLVM/project 97043e5mlir/lib/Dialect/Vector/Transforms VectorDistribute.cpp, mlir/test/Dialect/Vector vector-warp-distribute.mlir

[mlir][Vector][GPU] Distribute expanding `shape_cast` ops (#183830)

The initial implementation of `shape_cast` distribution only focused on
scenarios with collapsing shape casts. Within downstream pipelines such
as IREE, commit 962a9a3 exposes an issue with this implementation, where
the rank-expanding cast ops (stemming from the new `vector.broadcast`
canonicalization) silently fall through to the "collapsing-or-no-op"
logic. This brings about bugs with rank mismatches and firing validation
assertions when distributing rather common reshaping sequences
encountered after CSE/ canonicalization, such as below:
```
  // Example 1: gather op
  %weight = arith.constant dense_resource<__elided__> : tensor<256xi8>
  %c0 = arith.constant 0 : index
  ...
  %expand = vector.shape_cast <...> : vector<1xindex> to vector<1x1xindex>
  %gather = vector.gather %weight[%c0] [%expand], <...>, <...> : memref<256xi8>, vector<1x1xindex>, vector<1x1xi1>, vector<1x1xi8> into vector<1x1xi8>
  %collapse_back = vector.shape_cast %gather : vector<1x1xi8> to vector<1xi8>
  // Example 2: multi-reduction

    [19 lines not shown]
DeltaFile
+68-0mlir/test/Dialect/Vector/vector-warp-distribute.mlir
+45-10mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
+113-102 files

LLVM/project 6d83be8llvm/test/CodeGen/AMDGPU select-nsz-known-values-to-fmin-fmax.ll

AMDGPU: Add more tests for fp min/max combines

There's some overlap with existing tests which
use the nnan flag. The vector cases get missed here.
DeltaFile
+956-0llvm/test/CodeGen/AMDGPU/select-nsz-known-values-to-fmin-fmax.ll
+956-01 files

LLVM/project de69348clang/include/clang/APINotes APINotesReader.h, clang/lib/APINotes APINotesReader.cpp APINotesManager.cpp

[Reland] [APINotes] Refactor APINotesReader to propagate llvm::Error (#184212)

Reland of #183812 with the explicit `std::move` restored to fix buildbot
failures on older compilers.
DeltaFile
+431-404clang/lib/APINotes/APINotesReader.cpp
+11-4clang/lib/APINotes/APINotesManager.cpp
+4-3clang/include/clang/APINotes/APINotesReader.h
+446-4113 files

LLVM/project fa6eef8llvm/lib/Analysis InstructionSimplify.cpp, llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

Revert "Avoid maxnum(sNaN, x) optimizations / folds (#170181)" (#184125)

This reverts commit ea3fdc5972db7f2d459e543307af05c357f2be26.

Re-enable const-folding for maxnum/minnum in the middle-end, GlobalISel,
and SelectionDAG.

Re-enable optimizations that depend on maxnum/minnum sNaN semantics in
InstCombine and DAGCombiner.

Now that maxnum(x, sNaN) is specified to non-deterministically produce
either NaN or x, these constant-foldings and optimizations are now valid
again according to the newly clarified semantics in #172012 .
DeltaFile
+8-37llvm/test/CodeGen/X86/fminnum.ll
+8-37llvm/test/CodeGen/X86/fmaxnum.ll
+7-32llvm/test/CodeGen/ARM/fminmax-folds.ll
+13-22llvm/test/Transforms/InstSimplify/fminmax-folds.ll
+14-11llvm/lib/Analysis/InstructionSimplify.cpp
+8-7llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+58-1466 files not shown
+66-17412 files

LLVM/project 7036495llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/X86 known-never-zero.ll

[DAG] isKnownNeverZero - add ISD::OR DemandedElts handling (#183228)

This patch updates `SelectionDAG::isKnownNeverZero` to support `ISD::OR`
by forwarding the `DemandedElts` mask to its operands.

Previously, `ISD::OR` dropped the mask, causing the compiler to be
overly conservative if any lane in the vector was zero, even if that
lane wasn't demanded. This change allows the compiler to prove a vector
result is non-zero even if ignored lanes are zero.

Fixes #183037

**Tests:**

- Moved tests from the C++ file to the IR assembly file
(`known-never-zero.ll`) as requested.
- Confirmed the code now correctly tracks which parts of a vector are
actually needed for `ISD::OR`.
- This allows the compiler to prove a result is "never zero" even if
some unused lanes contain zeros.
DeltaFile
+9-18llvm/test/CodeGen/X86/known-never-zero.ll
+2-2llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+11-202 files

LLVM/project d908184llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 arm64-neon-select_cc.ll

[AArch64] Limit support to f32 and f64 in performSelectCombine (#184315)

This prevents a crash with fp128 types, other types (f16) were already
excluded.

Fixes #184300
DeltaFile
+36-0llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+37-12 files

LLVM/project ec7f350mlir/test/Interfaces/LoopLikeInterface test-block-loop.mlir, mlir/test/lib/Interfaces/LoopLikeInterface TestBlockInLoop.cpp

[MLIR] Make test-block-is-in-loop pass a module pass (#184036)

This pass can't run in parallel on function as it would trigger race conditions.

Fixes #183999
DeltaFile
+13-11mlir/test/lib/Interfaces/LoopLikeInterface/TestBlockInLoop.cpp
+1-1mlir/test/Interfaces/LoopLikeInterface/test-block-loop.mlir
+14-122 files

LLVM/project a368bd4clang/lib/CIR/CodeGen CIRGenModule.cpp CIRGenModule.h, clang/test/CIR/CodeGenCUDA kernel-args.cu

[CIR][CUDA]: Handle duplicate mangled names (#183976)

Replace the NYI for duplicate function defs with the proper diagnostic
logic from OG codegen.

Related: #175871, #179278
DeltaFile
+40-0clang/test/CIR/CodeGenCUDA/kernel-args.cu
+23-1clang/lib/CIR/CodeGen/CIRGenModule.cpp
+5-0clang/lib/CIR/CodeGen/CIRGenModule.h
+68-13 files

LLVM/project acfc1a8clang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/IR Verifier.cpp

fixup! More small optimisations Kerry spotted
DeltaFile
+7-12clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-3llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+1-2llvm/lib/IR/Verifier.cpp
+10-173 files

LLVM/project 2cbe5eeclang/lib/CodeGen/TargetBuiltins ARM.cpp, llvm/lib/IR Verifier.cpp

fixup! More small optimisations Kerry spotted
DeltaFile
+3-6clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-3llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+1-2llvm/lib/IR/Verifier.cpp
+6-113 files

LLVM/project ac6fd51clang/lib/Sema SemaARM.cpp, llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ExpandPseudoInsts.cpp

fixup! Small fixes Kerry has suggested
DeltaFile
+112-40llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+7-11clang/lib/Sema/SemaARM.cpp
+7-9llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+127-614 files

LLVM/project 55bcb7cllvm/lib/Target/AArch64 AArch64ISelLowering.cpp

fixup! Fix tests
DeltaFile
+2-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-01 files

LLVM/project c004dbaclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

fixup! More small fixes
DeltaFile
+15-37clang/lib/Sema/SemaARM.cpp
+11-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+5-3clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-2clang/lib/Headers/arm_acle.h
+0-1clang/test/CodeGen/arm_acle.c
+33-435 files

LLVM/project 4b3554bllvm/test/CodeGen/AArch64 pcdphint-atomic-store.ll

fixup! Sort out testcases
DeltaFile
+54-102llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
+54-1021 files

LLVM/project 1300ed5clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Headers arm_acle.h

fixup! Address Carol's comments and fix git clang-format issues
DeltaFile
+27-0llvm/test/CodeGen/AArch64/pcdphint-atomic-store-diagnostic.ll
+20-0llvm/lib/IR/Verifier.cpp
+12-6clang/lib/Sema/SemaARM.cpp
+0-11clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+2-4llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+4-2clang/lib/Headers/arm_acle.h
+65-236 files