LLVM/project fe69e13llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Simplify getElementSz using getLoadStore-helpers (NFC) (#222908)
DeltaFile
+3-13llvm/lib/Analysis/ScalarEvolution.cpp
+3-131 files

LLVM/project 0753606llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Remove (X && Y) | (X && !Y) -> X combine. NFC

We have smaller combines that can take care of this now that we process recipes in a worklist
DeltaFile
+1-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-81 files

LLVM/project 0e73bb8llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

[VPlan] Append recipes created via builder to worklist

The previous PR appended the top most created recipe to the worklist, and this PR extends it to any other nested recipes that were created, similar to InstCombine.

This removes the header mask in a good few more places on RISC-V as measured on SPEC CPU 2017, e.g. for the following loop:

```c
long f(const int *p, const int *q, long n) {
  long a = 0, b = 0;
  for (long i = 0;; i++) {
    if (p[i] && q[i]) { a += i; b += i; }
    if (i + 1 == n) break;
  }
  return a + b;
}
```

Before:


    [49 lines not shown]
DeltaFile
+26-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+5-7llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+42-193 files

LLVM/project b96eb6dllvm/test/Transforms/LoopVectorize/RISCV tail-folding-complex-mask.ll

Precommit test
DeltaFile
+163-0llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
+163-01 files

LLVM/project 885af64llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Unindent loop
DeltaFile
+14-13llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+14-131 files

LLVM/project 6015194llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

No need to dyn_cast to singledef recipe anymore
DeltaFile
+1-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-31 files

LLVM/project a91d1ballvm/test/Transforms/LoopVectorize blend-i1.ll

Make then branch non-dead
DeltaFile
+10-6llvm/test/Transforms/LoopVectorize/blend-i1.ll
+10-61 files

LLVM/project 9a0ef7dllvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Address review comments

- Limit to double initial worklist size
- Use VPSingleDefRecipe type
DeltaFile
+11-6llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-61 files

LLVM/project e0614e9llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Switch to SmallVector with space on stack

SmallVector allows for much larger small sizes than SetVector, so use 256 to match InstructionWorklist.
We don't need to worry about duplicate worklist entries until we add users to the worklist.
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-41 files

LLVM/project fb6d199llvm/test/Transforms/LoopVectorize blend-i1.ll

Precommit test
DeltaFile
+58-0llvm/test/Transforms/LoopVectorize/blend-i1.ll
+58-01 files

LLVM/project 90d7782llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Use make_pointer_range
DeltaFile
+1-2llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-21 files

LLVM/project 2f49232llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize iv_outside_user.ll blend-i1.ll

[VPlan] Process simplifyRecipes in a worklist

This brings simplifyRecipes further in line with InstCombine, and asides from unlocking more simplifications it also helps avoid spurious test churn whenever passes are moved around simplifyRecipes.

For now just push the new recipe onto the worklist, not its users.
This uses a post order traversal so we maintain the same simplification order as before.

I've gone through and checked every simplification we do is a canonicalisation that converges, and I checked on llvm-test-suite + SPEC CPU 2017 in various configurations that we don't hit any cycles.
DeltaFile
+23-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+4-8llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
+2-3llvm/test/Transforms/LoopVectorize/blend-i1.ll
+1-2llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+30-274 files

LLVM/project 66ec80clibcxx/include deque, libcxx/test/libcxx/containers/sequences/deque nodiscard.verify.cpp

[libc++][deque] Apply `[[nodiscard]]` to `deque::get_allocator` (#223599)

Added the missing `[[nodiscard]]`.


https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
DeltaFile
+1-1libcxx/include/deque
+2-0libcxx/test/libcxx/containers/sequences/deque/nodiscard.verify.cpp
+3-12 files

LLVM/project 591077ellvm/lib/Transforms/Vectorize VPlan.h VPlanTransforms.cpp

Update comments
DeltaFile
+2-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-1llvm/lib/Transforms/Vectorize/VPlan.h
+3-22 files

LLVM/project 2eb384fmlir/include/mlir/Dialect/Linalg/Transforms Transforms.h, mlir/lib/Dialect/Linalg/IR LinalgInterfaces.cpp

[MLIR][Linalg] Improve morphism semantics (#222959)

As exposed on the issues linked, the linalg morphism semantics could be
improved.

This PR changes the following semantics:
* Completes support for `-linalg-morph-ops` to include contractions and
ternary elementwise.
* Adds a `-linalg-categorize-ops`, which moves both named and generic
ops to category.
* Adds the possibility of "stopping at category" for both specialization
and generalization (not accessible from command line options but used by
the new categorize / old morph-ops pass).
* Removes the morphism options structure, since it's just a Boolean
flag.
* Improve test coverage, and make sure that `-linalg-morph-ops` does the
same thing as the other options.

It does NOT:

    [10 lines not shown]
DeltaFile
+297-216mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
+470-0mlir/test/Dialect/Linalg/categorize-named-ops.mlir
+184-203mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
+49-25mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
+57-5mlir/lib/Dialect/Linalg/Transforms/Generalization.cpp
+31-15mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
+1,088-4649 files not shown
+1,174-51915 files

LLVM/project 3e7af90llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize tail_fold_uncountable_exits.ll early_exit_with_stores.ll

Don't unwrap the freeze, copy it over in side effect early exit loops
DeltaFile
+27-27llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
+12-12llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
+8-8llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
+8-8llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
+6-6llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-2llvm/test/Transforms/LoopVectorize/tail_fold_uncountable_exits.ll
+63-632 files not shown
+67-678 files

LLVM/project e78970fllvm/lib/Target/AMDGPU AMDGPU.td VOP3Instructions.td, llvm/test/MC/AMDGPU gfx13_asm_vop3_err-fake16.s gfx13_asm_vop3_err.s

[AMDGPU] MC support for v_wave_match_b32 on gfx13 (#223360)
DeltaFile
+45-0llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
+45-0llvm/test/MC/AMDGPU/gfx13_asm_vop3-fake16.s
+37-0llvm/test/MC/AMDGPU/gfx13_asm_vop3_err.s
+30-0llvm/test/MC/AMDGPU/gfx13_asm_vop3_err-fake16.s
+11-0llvm/lib/Target/AMDGPU/VOP3Instructions.td
+5-0llvm/lib/Target/AMDGPU/AMDGPU.td
+173-06 files

LLVM/project 1e6a620llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86/avx512-shuffles shuffle-chained-bf16.ll

Make extract vector for bf16 types legal (#222913)

Fixes #222585

Makes EXTRACT_SUBVECTOR legal for bf16 types leading to this new codegen
```asm
# $ ./build/bin/clang test.c -O3 -march=novalake -mprefer-vector-width=512 -ffast-math -S -o -
foo:
        vmovups (%rsi), %zmm0
        vmulph  (%rdi), %zmm0, %zmm0
        vextractf64x4   $1, %zmm0, %ymm1
        vaddph  %zmm1, %zmm0, %zmm0
        vextractf128    $1, %ymm0, %xmm1
        vaddph  %xmm1, %xmm0, %xmm0
        vshufpd $1, %xmm0, %xmm0, %xmm1         # xmm1 = xmm0[1,0]
        vaddph  %xmm1, %xmm0, %xmm0
        vmovshdup       %xmm0, %xmm1            # xmm1 = xmm0[1,1,3,3]
        vaddph  %xmm1, %xmm0, %xmm0
        vpsrld  $16, %xmm0, %xmm1

    [19 lines not shown]
DeltaFile
+2-22llvm/test/CodeGen/X86/avx512-shuffles/shuffle-chained-bf16.ll
+1-0llvm/lib/Target/X86/X86ISelLowering.cpp
+3-222 files

LLVM/project 492410dclang/include/clang/Basic TargetID.h, clang/lib/Basic TargetID.cpp

Reapply "clang: Use TargetID parsing from AMDGPUTargetParser" (#213824) (#213847)

This reverts commit 8f82ba2c79f4e6a69a884cc9e19bd0b8c0bbe932.

Clang subarch patches have landed, so the prematurely build bots should be OK now.
DeltaFile
+30-167clang/lib/Basic/TargetID.cpp
+61-64clang/lib/Driver/ToolChains/AMDGPU.cpp
+39-42clang/lib/Driver/OffloadBundler.cpp
+10-34clang/include/clang/Basic/TargetID.h
+25-18clang/lib/Basic/Targets/AMDGPU.cpp
+20-14clang/lib/Basic/Targets/AMDGPU.h
+185-3397 files not shown
+256-38113 files

LLVM/project c6ec955llvm/include/llvm/CodeGen TargetInstrInfo.h, llvm/test/CodeGen/AArch64 wineh-async-eh-pad-instr-size.ll

[TargetInstrInfo] Disable size verification for EH_LABEL (#223641)

EH_LABEL may produce a nop if using async exceptions and followed
by a trapping instruction.

Suppress the verification error until the incorrect size reporting
is fixed.
DeltaFile
+34-0llvm/test/CodeGen/AArch64/wineh-async-eh-pad-instr-size.ll
+3-0llvm/include/llvm/CodeGen/TargetInstrInfo.h
+37-02 files

LLVM/project 3d2514fllvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp

[NFC][LLVM][AArch64TTI] Remove redundant type checking of convert_to_svbool operand. (#222945)
DeltaFile
+4-6llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+4-61 files

LLVM/project fe47933llvm/docs LangRef.md, llvm/include/llvm/Support CodeGen.h

IR: Introduce "exception-model" module flag (#220052)

Add an "exception-model" IR module flag intended to replace
TargetOptions::ExceptionModel, such that the ABI is fully
computable from the IR alone. Add the basic documentation and
verifier/linker tests, but doesn't wire up the consumers.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+49-0llvm/include/llvm/Support/CodeGen.h
+44-0llvm/docs/LangRef.md
+43-0llvm/test/Assembler/module-flags-exception-model.ll
+37-0llvm/test/Verifier/module-flags-exception-model.ll
+28-0llvm/test/Linker/module-flags-exception-model.ll
+11-0llvm/lib/IR/Verifier.cpp
+212-011 files not shown
+248-1517 files

LLVM/project f215866llvm/lib/Transforms/Scalar LICM.cpp, llvm/test/Transforms/LICM promote-single-thread.ll

LICM: Drop -licm-force-thread-model-single in favor of the module flag (#223158)

Now that the threading model is carried by the "thread-model" IR module
flag, the hidden -licm-force-thread-model-single override is redundant: a test
can select the single-threaded model by setting the module flag directly.
isThreadLocalObject reads only Module::getThreadModel.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+1-5llvm/lib/Transforms/Scalar/LICM.cpp
+3-1llvm/test/Transforms/LICM/promote-single-thread.ll
+3-0llvm/test/Transforms/LICM/Inputs/thread-model-single.ll
+7-63 files

LLVM/project 16449e7llvm/lib/Target/SPIRV SPIRVNonSemanticDebugInfo200.h SPIRVNonSemanticDebugInfo200.cpp

[reviews] Simplify nested namespaces.
DeltaFile
+2-6llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugInfo200.h
+2-6llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugInfo200.cpp
+2-6llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+6-183 files

LLVM/project 3ac6885llvm/test/Transforms/LoopVectorize fmin-without-fast-math-flags.ll epilog-vectorization-fmaxnum-reductions.ll, llvm/test/Transforms/LoopVectorize/AArch64 fmax-without-fast-math-flags.ll

Remove VPInstruction::usesFirstLaneOnly change

InstCombine will canonicalize this anyway https://godbolt.org/z/r7PsGxh6G
DeltaFile
+66-29llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
+51-24llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
+43-20llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
+42-20llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
+33-15llvm/test/Transforms/LoopVectorize/epilog-vectorization-fmaxnum-reductions.ll
+22-10llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
+257-1183 files not shown
+290-1409 files

LLVM/project 791fec8llvm/test/CodeGen/AMDGPU merge-m0.mir

review: fix test
DeltaFile
+12-28llvm/test/CodeGen/AMDGPU/merge-m0.mir
+12-281 files

LLVM/project 96ecbc9llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp

Fix build error after rebase.
DeltaFile
+2-1llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+2-11 files

LLVM/project 1232d0ellvm/lib/Target/AArch64 AArch64SVEInstrInfo.td AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fp-constrained-intrinsics.ll

[LLVM][CodeGen][SVE] Add isel for constrained cast operations. (#221976)

Implements lowering for constrained variants of fpext, fptosi, fptoui,
fptrunc, rint, sitofp and uitofp. Support covers scalable vectors of
half, float and double element type, with bfloat support due in a
follow-up PR.
DeltaFile
+368-9llvm/test/CodeGen/AArch64/sve-fp-constrained-intrinsics.ll
+56-38llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+8-8llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+432-553 files

LLVM/project e5f0af8llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.cpp SPIRVNonSemanticDebugInfo200.cpp, llvm/test/CodeGen/SPIRV/debug-info debug-expression-extra-ops-200.ll debug-declare-expression-unsupported-200.ll

[SPIR-V] Emit extra DebugExpression ops under NonSemantic.Shader.DebugInfo.200

Map DWARF ops beyond Fragment only when -spirv-nonsemantic-debug-info-version=200.
DeltaFile
+194-0llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugInfo200.h
+159-0llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugInfo200.cpp
+38-17llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+53-0llvm/test/CodeGen/SPIRV/debug-info/debug-expression-operations-200.ll
+44-0llvm/test/CodeGen/SPIRV/debug-info/debug-declare-expression-unsupported-200.ll
+42-0llvm/test/CodeGen/SPIRV/debug-info/debug-expression-extra-ops-200.ll
+530-172 files not shown
+536-208 files

LLVM/project 36ef642llvm/lib/Target/SPIRV SPIRVNonSemanticDebugHandler.h SPIRVNonSemanticDebugHandler.cpp

[review] Simplify code.
DeltaFile
+14-17llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
+0-2llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
+14-192 files