LLVM/project 46b7102 — llvm/test/CodeGen/AMDGPU float-to-arbitrary-fp-fp8-hw.ll vector-reduce-smin.ll

split in smaller patches
DeltaFile
+1,503-1,456llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+382-214llvm/test/CodeGen/AMDGPU/bf16.ll
+170-349llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
+174-102llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+174-102llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+108-101llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+2,511-2,32427 files not shown
+3,103-2,98533 files

LLVM/project 05e432a — clang/test/Driver invalid-target-id.cl, llvm/docs AMDGPUUsage.rst

[AMDGPU] Support xnack on/off on gfx125x (#232080)

Default is 'any' effectively same as 'on'.
DeltaFile
+0-59llvm/test/CodeGen/AMDGPU/module-flag-xnack-no-on-off-modes.ll
+0-24llvm/test/CodeGen/AMDGPU/target-id-xnack-always-on.ll
+0-21clang/test/Driver/invalid-target-id.cl
+4-4llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+4-4llvm/docs/AMDGPUUsage.rst
+2-5llvm/unittests/TargetParser/TargetParserTest.cpp
+10-1177 files not shown
+24-13313 files

LLVM/project 5388c76 — llvm/utils/TableGen RegisterInfoEmitter.cpp

TableGen: Reserve per-register lists in RegisterInfoEmitter

The sub-register, super-register and register unit lists of each
register were built one element at a time, although their sizes are
known in advance. AMDGPU has about 20000 registers, so there were a
lot of realloc calls.

Generating AMDGPUGenRegisterInfo.inc executes 0.4% fewer instructions
with 4% fewer page faults. This greatly reduces the time impact with
MALLOC_PERTURB_=1.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+4-0llvm/utils/TableGen/RegisterInfoEmitter.cpp
+4-01 files

LLVM/project 377cf92 — clang/test/SemaCUDA deferred-ctor-initializers.cu, llvm/test/CodeGen/AArch64 vector-ldst-offset.ll

Merge branch 'main' into revert-231420-users/arsenm/clang/reapply-targetid-parsing-amdgpu-targetparser
DeltaFile
+322-342llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
+200-200llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
+200-200llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
+334-0clang/test/SemaCUDA/deferred-ctor-initializers.cu
+98-0llvm/test/Transforms/SLPVectorizer/AArch64/or-reduction-byte-pack.ll
+69-0llvm/test/Transforms/SLPVectorizer/X86/copyable-non-schedulable-reused-by-vectorized.ll
+1,223-74228 files not shown
+1,487-82134 files

LLVM/project d137cfe — llvm/test/CodeGen/Thumb2 expand-pseudos.mir t2call-bti-expand.mir

Merge test file
DeltaFile
+0-30llvm/test/CodeGen/Thumb2/t2call-bti-expand.mir
+24-0llvm/test/CodeGen/Thumb2/expand-pseudos.mir
+24-302 files

LLVM/project 0de93f3 — llvm/lib/Target/NVPTX NVPTXISelLowering.cpp, llvm/test/CodeGen/NVPTX i16x2-instructions.ll

[NVPTX] Mark SMUL_LOHI and UMUL_LOHI as Expand for v2i16 (#225808)

`SMUL_LOHI` and `UMUL_LOHI` were inadvertently left as `Legal` for
`v2i16` in NVPTX, despite the backend having no instruction patterns to
select them. As a result, the vector legalizer expands `v2i16`
high-multiplies (`mulhs`/`mulhu`) and constant divisions into `v2i16`
`smul_lohi`/`umul_lohi` nodes instead of scalarizing them into `i16`
operations, causing an instruction selection crash. Marking both
operations as `Expand` for `v2i16` ensures they are properly scalarized.

Assisted-by: Gemini

---------

Co-authored-by: Yonah Goldberg <ygoldberg at nvidia.com>
DeltaFile
+38-0llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
+4-3llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+42-32 files

LLVM/project e80745b — libc/src/__support/math asinbf16.h asin_utils.h, libc/test/src/math/smoke acosbf16_test.cpp

[libc][math] Use float-only evaluation in asinbf16 and acosbf16 (#228734)

Update `asinbf16` and `acosbf16` to use a shared `float` polynomial
instead of the double-precision `asin_eval` helper. Reuse the polynomial
coefficients from `asinf16`.

For small `acosbf16` inputs, return pi/2 rounded to `bfloat16` before
squaring the input or evaluating the polynomial. This avoids spurious
underflow from intermediate products.

Related: #202079
Assisted-by: GPT-6-Astra
DeltaFile
+25-0libc/test/src/math/smoke/acosbf16_test.cpp
+10-11libc/src/__support/math/acosbf16.h
+16-0libc/src/__support/math/asin_utils.h
+2-4libc/src/__support/math/asinbf16.h
+53-154 files

LLVM/project c7ce110 — llvm/test/CodeGen/WinEH wineh-empty-seh-scope.ll

Update wineh-empty-seh-scope.ll for the Windows trap change

An unreachable that does not follow a call no longer traps, so the empty
function gets the generic zero-length function nop, as on X86.
DeltaFile
+1-1llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
+1-11 files

LLVM/project ee03a65 — llvm/lib/Target/X86 X86InstrInfo.cpp, llvm/test/CodeGen/X86 expand-post-ra-pseudo.mir

X86: Preserve dead flag when expanding MOV32ri64

The expansion narrowed the dead 64-bit def to a dead 32-bit def, but
added a live implicit-def of the 64-bit register. This avoids failing
a future verifier check.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+9-0llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir
+2-1llvm/lib/Target/X86/X86InstrInfo.cpp
+11-12 files

LLVM/project c66fa97 — clang/docs ReleaseNotes.md, clang/lib/Sema UsedDeclVisitor.h Sema.cpp

[Clang] [CUDA] Follow ctor/member initializers in DeferredDiagnosticsEmitter (#232044)

We are currently ignoring the fact that a constructor invocation also
runs constructor/member initializers, which causes us to miss some
diagnostics about `__host__`/`__device__` mismatch. Inherited constructors
are likewise not handled correctly.

This patch fixes both.

Fixes #118415.

Assisted-by: Codex
DeltaFile
+334-0clang/test/SemaCUDA/deferred-ctor-initializers.cu
+9-2clang/lib/Sema/Sema.cpp
+4-0clang/lib/Sema/UsedDeclVisitor.h
+3-0clang/docs/ReleaseNotes.md
+350-24 files

LLVM/project 71fc6b8 — llvm/test/CodeGen/Mips/llvm-ir load.ll, llvm/test/CodeGen/Mips/longbranch branch-limits-msa.mir

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+725-1,475llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
+704-890llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
+614-614llvm/test/CodeGen/Mips/llvm-ir/load.ll
+522-621llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+410-410llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
+309-438llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
+3,284-4,448648 files not shown
+25,300-20,118654 files

LLVM/project 7a9fb86 —

rebase

Created using spr 2.0.0-beta.1
DeltaFile
+0-00 files

LLVM/project 78e5f7f — libc/src/__support/math expf.h

rebase

Created using spr 2.0.0-beta.1
DeltaFile
+0-63libc/src/__support/math/expf.h
+0-631 files

LLVM/project dfbbe6a — libc/src/__support/math expf.h

rebase

Created using spr 2.0.0-beta.1
DeltaFile
+63-0libc/src/__support/math/expf.h
+63-01 files

LLVM/project 034f10d — llvm/test/Transforms/SampleProfile remapper-reread-loaded-profile.ll, llvm/test/Transforms/SampleProfile/Inputs remapper-reread-loaded-profile.prof

[SampleProf][test] Precommit test to demonstrate the duplicated vtable error upon repeated profile read. (#232461)

Extend test case in #231339 with a vtable type record to surface the
duplicated vtable warning message

warning: Duplicate vtable type _ZTV4Base at the same location.
Additional
    counters will be ignored.

This is how the doubled head/body samples documented in #231339 were
first noticed.

Assisted by: Claude
DeltaFile
+19-3llvm/test/Transforms/SampleProfile/remapper-reread-loaded-profile.ll
+1-0llvm/test/Transforms/SampleProfile/Inputs/remapper-reread-loaded-profile.prof
+20-32 files

LLVM/project cd96642 — llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-masked-gather-scatter.ll zext-to-tbl.ll

[DAGCombiner] Narrow truncating stores of extended values (#231338)

Previous code did `truncstore(extend(x)) -> store(x)`. This patch adds
the following combine: `truncstore(extend(x)) -> narrower_truncstore(x)`
to get rid of the extension in more cases.
DeltaFile
+322-342llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
+20-8llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+7-14llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
+8-8llvm/test/CodeGen/AArch64/zext-to-tbl.ll
+5-6llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
+0-2llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
+362-3806 files

LLVM/project 63008d7 — flang/lib/Semantics check-omp-atomic.cpp check-omp-structure.h, flang/test/Semantics/OpenMP clause-validity01.f90 flush02.f90

[flang][OpenMP] Switch clause verification to descriptor-based

Delete all the scattered pieces of clause verification that are now
replaced by the unified handling.
DeltaFile
+57-273flang/lib/Semantics/check-omp-structure.cpp
+300-0flang/lib/Semantics/check-omp-syntax.cpp
+22-10flang/lib/Semantics/check-omp-structure.h
+0-31flang/lib/Semantics/check-omp-atomic.cpp
+8-8flang/test/Semantics/OpenMP/flush02.f90
+8-7flang/test/Semantics/OpenMP/clause-validity01.f90
+395-32937 files not shown
+517-38443 files

LLVM/project 9d1a67d — flang/lib/Semantics check-omp-syntax.cpp, flang/test/Semantics/OpenMP allocate_do1.f90 uses-allocators-version50.f90

[flang][OpenMP] Improve diagnostics about modifier properties

Use OpenMPDeprecated and OpenMPFuture warning categories for modifier
diagnostics as well, analogously to how they are used for clauses.
DeltaFile
+67-31flang/lib/Semantics/check-omp-syntax.cpp
+4-4flang/test/Semantics/OpenMP/map-modifiers-v60.f90
+3-3flang/test/Semantics/OpenMP/uses-allocators-version50.f90
+3-3flang/test/Semantics/OpenMP/to-clause-v45.f90
+3-3flang/test/Semantics/OpenMP/from-clause-v45.f90
+2-2flang/test/Semantics/OpenMP/allocate_do1.f90
+82-466 files not shown
+89-5312 files

LLVM/project b34f67d — flang/include/flang/Parser openmp-utils.h, flang/lib/Semantics check-omp-structure.h check-omp-syntax.cpp

[flang][OpenMP] Account for using different versions for modifier checks

When a modifier from a past/future version is accepted, use its properties
from the nearest version in which it is allowed.
DeltaFile
+118-75flang/lib/Semantics/check-omp-syntax.cpp
+3-1flang/include/flang/Parser/openmp-utils.h
+2-1llvm/include/llvm/Frontend/Directive/Spelling.h
+1-0flang/lib/Semantics/check-omp-structure.h
+124-774 files

LLVM/project 7885c83 — flang/include/flang/Parser openmp-utils.h, flang/lib/Parser openmp-utils.cpp

[flang][OpenMP] Create generic interfaces for "container" entities

In short, clauses are containers of modifiers, and directives are
containers of clauses. With the abstractions in place, clauses and
modifiers look almost the same from the point of view of syntactic
properties.

Use these functions to implement generic GetAllowedElements and
GetElementVersionRange functions.
DeltaFile
+17-55flang/lib/Semantics/check-omp-syntax.cpp
+56-0flang/include/flang/Parser/openmp-utils.h
+31-0flang/lib/Parser/openmp-utils.cpp
+104-553 files

LLVM/project 1f4f204 — flang/lib/Semantics check-omp-syntax.cpp

[flang][OpenMP] Properly use GetAllowedElements

Allowed elements are not just those explicitly listed, but also those
from the union of allowed sets.

For example, the set of modifiers allowed on a clause are those that
are listed on a given clause, plus the union of all modifier sets that
the clause allows.
DeltaFile
+25-13flang/lib/Semantics/check-omp-syntax.cpp
+25-131 files

LLVM/project 0a4c3af — llvm/include/llvm/Frontend/OpenMP OMPDescriptors.h OMPDescriptors.h.inc, llvm/lib/Frontend/OpenMP OMPDescriptors.cpp OMPDescriptors.inc

[OpenMP] Introduce descriptors for directives, clause groups and sets

Reuse Association and Category enum definitions from OMP.h.inc.
DeltaFile
+1,110-1llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
+110-1llvm/include/llvm/Frontend/OpenMP/OMPDescriptors.h.inc
+110-0llvm/lib/Frontend/OpenMP/OMPDescriptors.cpp
+63-0llvm/include/llvm/Frontend/OpenMP/OMPDescriptors.h
+1,393-24 files

LLVM/project 0bafe11 — llvm/test/Transforms/SLPVectorizer/AArch64 or-reduction-byte-pack.ll

[SLP][NFC]Add some more test with bitpack vectorization, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/232468
DeltaFile
+98-0llvm/test/Transforms/SLPVectorizer/AArch64/or-reduction-byte-pack.ll
+98-01 files

LLVM/project f19b75e — llvm/test/Analysis/CostModel/LoongArch arith-int.ll, llvm/test/CodeGen/AMDGPU gfx-callable-argument-types.ll amdgcn.bitcast.1024bit.ll

Merge branch 'main' into users/arsenm/amdgpu-attributor/single-call-walk-v2
DeltaFile
+7,716-7,532llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+725-1,475llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
+704-890llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
+660-717llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+614-614llvm/test/CodeGen/Mips/llvm-ir/load.ll
+1,161-0llvm/test/Analysis/CostModel/LoongArch/arith-int.ll
+11,580-11,2281,074 files not shown
+46,974-43,6941,080 files

LLVM/project 66eaa71 — utils/bazel/llvm-project-overlay/libc BUILD.bazel

[bazel][libc] Add __support_math_expf_float_utils target (#232450)

9dc80b90f811 (#231671) added src/__support/math/expf_float_utils.h and
included it in src/__support/math/expf_float_eval.h without updating the
Bazel overlay.
DeltaFile
+14-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+14-01 files

LLVM/project d7da080 — llvm/test/DebugInfo/MIR/InstrRef spill-slot-idx-limits.mir

[LiveDebugValues] Fix broken test, NFC (#232465)
DeltaFile
+2-2llvm/test/DebugInfo/MIR/InstrRef/spill-slot-idx-limits.mir
+2-21 files

LLVM/project de6737e — llvm/lib/Target/AMDGPU VOPInstructions.td, llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUMCCodeEmitter.cpp

[AMDGPU] Encode op_sel_hi as zero for the V_PK 64-bit instructions (#230662)

VOP3P defaults unused op_sel_hi bits to one, but the gfx1251 64-bit
packed instructions have no op_sel and SP3 encodes those bits as zero.

Add a ZeroOutOpSelHi bit on VOPProfile and InstSI, set it on the V_PK
64-bit profiles, and honor it in VOP3Pe and in AMDGPUMCCodeEmitter via the new
AMDGPU::zeroesOutOpSelHi() query.

Fixes: LCOMPILER-2952 (partially)
DeltaFile
+200-200llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
+200-200llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
+12-0llvm/lib/Target/AMDGPU/VOPInstructions.td
+10-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+4-1llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+5-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+431-4013 files not shown
+441-4019 files

LLVM/project c17cf74 — clang/lib/Driver/ToolChains Flang.cpp, flang/test/Driver version-loops-trip-count.f90

[flang][driver] Honor trailing -O0 and test -mmlir overrides for trip-count versioning
DeltaFile
+30-0flang/test/Integration/loop-tripcount-versioning.f90
+8-5clang/lib/Driver/ToolChains/Flang.cpp
+9-0flang/test/Driver/version-loops-trip-count.f90
+47-53 files

LLVM/project 55ce745 — clang/lib/CIR/CodeGen CIRGenerator.cpp

[CIR]  Only load ACC/OMP dialect if they are enabled. (#232434)

This reduces the overall instr count of a ClangIR build without these
languages by ~6%, which seems worth-while.

We DID have to unconditionally load the LLVMDialect, as we previously
were only getting it via the OpenACC dialect transitively.
DeltaFile
+8-3clang/lib/CIR/CodeGen/CIRGenerator.cpp
+8-31 files

LLVM/project 6ef4f2b — flang/include/flang/Optimizer/Passes CommandLineOpts.h, flang/lib/Optimizer/Passes Pipelines.cpp CommandLineOpts.cpp

[flang] Plumb -loop-tripcount-versioning-max-unrolled-ops through the pipeline
DeltaFile
+5-0flang/lib/Optimizer/Passes/CommandLineOpts.cpp
+2-1flang/lib/Optimizer/Passes/Pipelines.cpp
+1-0flang/include/flang/Optimizer/Passes/CommandLineOpts.h
+8-13 files