LLVM / project - FreshBSD

LLVM/project a2756bd — mlir/include/mlir-c IR.h, mlir/lib/CAPI/IR IR.cpp

2026-08-01 08:26:25 UTC by makslevental on ⎇

users/makslevental/mlir-c-operation-equivalence

Address review: fix -Wenum-compare build failure, add structural hash, expand flag coverage

Delta		File
+115	-2	mlir/test/CAPI/ir.c
+11	-16	mlir/lib/CAPI/IR/IR.cpp
+19	-7	mlir/include/mlir-c/IR.h
+145	-25	3 files

LLVM/project 50b15d6 — mlir/include/mlir-c IR.h, mlir/lib/CAPI/IR IR.cpp

2026-08-01 08:26:22 UTC by makslevental on ⎇

users/makslevental/mlir-c-operation-equivalence

[mlir-c] Add structural operation equivalence

Delta		File
+70	-0	mlir/test/CAPI/ir.c
+25	-0	mlir/include/mlir-c/IR.h
+24	-0	mlir/lib/CAPI/IR/IR.cpp
+119	-0	3 files

LLVM/project 9947b7f — mlir/cmake/modules AddMLIR.cmake, mlir/lib CMakeLists.txt

2026-08-01 08:20:40 UTC by makslevental on ⎇

users/makslevental/mlir-ir-pch

[MLIR][CMake] Extend MLIRIR PCH reuse to transitive dependants

llvm_update_pch() only offers a PCH to targets that name the defining
library as a *direct* dependency, because across LLVM subprojects a
transitively reused PCH drags in unrelated headers and causes name
collisions. Within MLIR that concern is much weaker: mlir/IR/pch.h holds
MLIR core headers that essentially every MLIR library includes anyway.

Add mlir_reuse_ir_pch(), which offers MLIRIR's PCH to any target that
actually reaches MLIRIR through its link graph. The reachability check
matters: a PCH containing MLIR IR headers emits out-of-line symbols that
only libMLIRIR provides, so handing it to a Support-only target such as
tblgen-lsp-server breaks the link.

The helper is called from add_mlir_library() and add_mlir_tool(), and
again from mlir_target_link_libraries(), where most tests, unittests and
libMLIR.so-avoiding libraries actually attach their MLIR dependencies. It
is idempotent and skips targets that define their own PCH, that opt out
with DISABLE_PCH_REUSE, that override RTTI/EH, or that contain C/ObjC

    [18 lines not shown]

Delta		File
+135	-2	mlir/cmake/modules/AddMLIR.cmake
+7	-4	mlir/lib/CMakeLists.txt
+5	-0	mlir/lib/Tools/PDLL/ODS/CMakeLists.txt
+5	-0	mlir/lib/Tools/PDLL/AST/CMakeLists.txt
+1	-0	mlir/unittests/CMakeLists.txt
+153	-6	5 files

LLVM/project 6b98f82 — cmake/Modules GetTripleCMakeSystemName.cmake, llvm/include/llvm/TargetParser TripleName.def

2026-08-01 07:41:32 UTC by Matt Arsenault via GitHub on ⎇

main

cmake: Derive CMake system name from a triple via new mechanism (#208773)

Delta		File
+118	-110	llvm/include/llvm/TargetParser/TripleName.def
+206	-0	llvm/test/tools/TargetParser/get_triple_system_name_test.py
+148	-0	llvm/utils/get_triple_system_name.py
+40	-0	cmake/Modules/GetTripleCMakeSystemName.cmake
+4	-4	llvm/lib/TargetParser/Triple.cpp
+6	-0	llvm/test/tools/TargetParser/get-triple-system-name.test
+522	-114	6 files

LLVM/project 2605272 — llvm/lib/Target/RISCV RISCVInstrInfoC.td, llvm/test/MC/RISCV priv-invalid.s

2026-08-01 06:52:24 UTC by Alexander Richardson on ⎇

users/arichardson/spr/risc-vmcrvy-add-support-for-rvy-loadsstores

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1-arichardson

Delta		File
+465	-0	llvm/test/MC/RISCV/rvy/rvyc-valid-load-store.s
+199	-0	llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
+91	-95	llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+170	-0	llvm/test/TableGen/getRegClassFromMatchKind.td
+158	-0	llvm/test/MC/RISCV/rvy/rvyc-invalid-load-store.s
+91	-47	llvm/test/MC/RISCV/priv-invalid.s
+1,174	-142	52 files not shown
+2,275	-472	58 files

LLVM/project de41429 — llvm/lib/Target/RISCV RISCVInstrInfo.td RISCVInstrInfoC.td, llvm/test/MC/RISCV target-abi-invalid.s priv-invalid.s

2026-08-01 06:52:23 UTC by Alexander Richardson on ⎇

users/arichardson/spr/main.risc-vmcrvy-add-support-for-rvy-loadsstores

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1-arichardson

[skip ci]

Delta		File
+82	-88	llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+170	-0	llvm/test/TableGen/getRegClassFromMatchKind.td
+91	-47	llvm/test/MC/RISCV/priv-invalid.s
+61	-59	llvm/test/MC/RISCV/target-abi-invalid.s
+44	-50	llvm/lib/Target/RISCV/RISCVInstrInfo.td
+85	-1	llvm/utils/TableGen/AsmMatcherEmitter.cpp
+533	-245	36 files not shown
+816	-404	42 files

LLVM/project f9a6d13 — llvm/lib/Transforms/InstCombine InstCombineLoadStoreAlloca.cpp, llvm/test/Transforms/InstCombine atomic.ll

2026-08-01 06:40:26 UTC by Harrison Hao on ⎇

users/harrisonGPU/instcombine-load-atomic

[InstCombine] Don't change the type of elementwise atomic loads

Delta		File
+11	-0	llvm/test/Transforms/InstCombine/atomic.ll
+3	-0	llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+14	-0	2 files

LLVM/project 586a5ba — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.cpp

2026-08-01 06:16:19 UTC by Alexander Richardson on ⎇

users/arichardson/spr/riscv-select-the-capability-abi-by-default-when-the-y-extension-is-enabled

add more error cases

Created using spr 1.3.8-beta.1-arichardson

Delta		File
+12	-6	llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+11	-6	llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+4	-4	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+27	-16	3 files

LLVM/project a77fad1 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.cpp

2026-08-01 06:16:03 UTC by Alexander Richardson on ⎇

users/arichardson/spr/main.riscv-select-the-capability-abi-by-default-when-the-y-extension-is-enabled

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1-arichardson

[skip ci]

Delta		File
+4	-4	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2	-4	llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+1	-2	llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+7	-10	3 files

LLVM/project c27bee2 — llvm/lib/Target/AMDGPU VOP3PInstructions.td SIInstrInfo.h

2026-08-01 06:15:50 UTC by K.Roy via GitHub on ⎇

main

[AMDGPU] Generalize MFMA VGPR->AGPR opcode mapping (NFC) (#213274)

Move the VGPR/AGPR pairing out of MFMATable into a generalized
AGPRFormTable class and rename getMFMASrcCVDstAGPROp to getAGPRFormOp.
MFMATable inherits AGPRFormTable, so the instantiation sites and the
generated table are unchanged.

Other instruction families with paired VGPR/AGPR pseudos, such as DS,
can now be tagged with AGPRFormTable.

Related to #168983

Delta		File
+10	-5	llvm/lib/Target/AMDGPU/SIInstrInfo.td
+3	-4	llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+1	-5	llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+3	-3	llvm/lib/Target/AMDGPU/SIInstrInfo.h
+3	-3	llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+20	-20	5 files

LLVM/project 3c3a18e — clang/include/clang/Basic OffloadArch.h, clang/lib/Basic Cuda.cpp OffloadArch.cpp

2026-08-01 06:14:04 UTC by Matt Arsenault via GitHub on ⎇

main

clang: Store vendor GPU kinds in OffloadArch instead of re-listing GPUs (#213362)

OffloadArch was a flat enum that hand-duplicated every AMDGPU and NVPTX
target, plus a few edge cases. This was yet another place that needed
updating every time a new target is added, which should now be avoided.
Replace with a tagged union-like scheme.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+103	-143	clang/include/clang/Basic/OffloadArch.h
+73	-136	clang/lib/Basic/OffloadArch.cpp
+42	-19	clang/unittests/Basic/OffloadArchTest.cpp
+12	-28	clang/lib/Basic/Cuda.cpp
+27	-10	clang/test/Misc/target-invalid-cpu-note/nvptx.c
+12	-14	clang/lib/Driver/Driver.cpp
+269	-350	8 files not shown
+304	-381	14 files

LLVM/project 521ac0d — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/lib/Target/RISCV/MCTargetDesc RISCVBaseInfo.cpp

2026-08-01 05:59:28 UTC by Alexander Richardson on ⎇

users/arichardson/spr/riscv-change-riscvabicomputetargetabi-to-return-expectedabi

clang-format

Created using spr 1.3.8-beta.1-arichardson

Delta		File
+4	-4	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2	-4	llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+1	-2	llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+7	-10	3 files

LLVM/project c72e559 — mlir/include/mlir/IR pch.h, mlir/lib CMakeLists.txt

2026-08-01 05:56:14 UTC by makslevental on ⎇

users/makslevental/mlir-ir-pch

[MLIR][CMake] Add PCH for MLIRIR

Add a precompiled header for MLIRIR, following the infrastructure added in
llvm#176420 and the per-component PCHs for llvm/IR (llvm#183303),
llvm/CodeGen (llvm#183346) and clang/AST (llvm#183358).

The header list was selected with the same methodology: compile all 1173
CUs under mlir/lib with -ftime-trace, rank mlir headers by the time spent
parsing them (including transitively included headers), then greedily pick
the header with the largest marginal coverage until the marginal gain
falls off. Candidates were restricted to headers already reachable from
MLIRIR's own sources, so the PCH does not invert the library layering.

Over the mlir/lib CUs, the selected set covers 1227s of 3674s total
frontend time (33%). On a Release+assertions build of mlir-opt
(Apple M-series, -j16), clean build wall time goes from 468.3s to 440.8s
(-5.9%); 715 of 1536 MLIR objects reuse the PCH.

mlir/lib/CMakeLists.txt gains an explicit add_subdirectory(IR) before the

    [7 lines not shown]

Delta		File
+47	-0	mlir/include/mlir/IR/pch.h
+8	-8	mlir/lib/Tools/mlir-lsp-server/LSPServer.cpp
+4	-1	mlir/lib/CMakeLists.txt
+3	-0	mlir/lib/IR/CMakeLists.txt
+62	-9	4 files

LLVM/project b12686d — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

2026-08-01 05:52:04 UTC by Alexander Richardson on ⎇

users/arichardson/spr/riscv-select-the-capability-abi-by-default-when-the-y-extension-is-enabled

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1-arichardson

Delta		File
+61	-59	llvm/test/MC/RISCV/target-abi-invalid.s
+67	-1	llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+36	-30	llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+10	-16	llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+8	-14	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+10	-7	llvm/lib/TargetParser/RISCVISAInfo.cpp
+192	-127	8 files not shown
+241	-142	14 files

LLVM/project 733727d — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

2026-08-01 05:52:03 UTC by Alexander Richardson on ⎇

users/arichardson/spr/main.riscv-select-the-capability-abi-by-default-when-the-y-extension-is-enabled

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1-arichardson

[skip ci]

Delta		File
+61	-59	llvm/test/MC/RISCV/target-abi-invalid.s
+36	-30	llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+42	-1	llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+10	-16	llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+8	-14	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+6	-6	llvm/test/CodeGen/RISCV/target-abi-invalid.ll
+163	-126	4 files not shown
+187	-132	10 files

LLVM/project 3d7fc37 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

2026-08-01 05:51:42 UTC by Alexander Richardson on ⎇

users/arichardson/spr/riscv-change-riscvabicomputetargetabi-to-return-expectedabi

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1-arichardson

Delta		File
+61	-59	llvm/test/MC/RISCV/target-abi-invalid.s
+36	-30	llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+42	-1	llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+10	-16	llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+8	-14	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+6	-6	llvm/test/CodeGen/RISCV/target-abi-invalid.ll
+163	-126	4 files not shown
+187	-132	10 files

LLVM/project b94b699 — llvm/lib/TargetParser RISCVISAInfo.cpp, llvm/unittests/Target/RISCV CMakeLists.txt RISCVBaseInfoTest.cpp

2026-08-01 05:45:19 UTC by Alexander Richardson via GitHub on ⎇

main

[RISCV] Fix ISCVISAInfo::computeDefaultABI() result for xcheriot (#212129)

XCheriot was not considered in this function, so RV32E+XCheriot
defaulted
to ilp32e instead of cheriot when no -target-abi was given.

Since this function does not have unit test coverage, this adds new
tests
for the ABI inference functions: RISCVISAInfo::computeDefaultABI() and
RISCVABI::computeTargetABI.

This change was created with the help of AI tools

Delta		File
+50	-0	llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+21	-0	llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+2	-0	llvm/lib/TargetParser/RISCVISAInfo.cpp
+1	-0	llvm/unittests/Target/RISCV/CMakeLists.txt
+74	-0	4 files

LLVM/project d9e6999 — llvm/lib/Target/X86/MCTargetDesc X86AsmBackend.cpp

2026-08-01 05:35:03 UTC by Fangrui Song via GitHub on ⎇

main

[X86AsmBackend] Define reset() hook (#213409)

Noticed when reviewing #175830: MCObjectStreamer::reset frees the
fragments PendingBA and PrevInstPosition point into, but X86AsmBackend
keeps them. Define the hook.

Delta		File
+7	-0	llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+7	-0	1 files

LLVM/project dbefa87 — clang/include/clang/Basic OffloadArch.h, clang/lib/Basic Cuda.cpp

2026-08-01 05:27:05 UTC by Matt Arsenault on ⎇

users/arsenm/clang/offloadarch-use-direct-methods

clang: Replace Is*OffloadArch free functions with OffloadArch methods

Drop the IsNVIDIAOffloadArch/IsAMDOffloadArch/IsIntel*OffloadArch free
functions in favor of the OffloadArch member predicate functions.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+29	-19	clang/unittests/Basic/OffloadArchTest.cpp
+6	-6	clang/lib/Driver/Driver.cpp
+0	-9	clang/include/clang/Basic/OffloadArch.h
+4	-4	clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
+2	-2	clang/lib/Basic/Cuda.cpp
+1	-1	clang/lib/Driver/ToolChains/Clang.cpp
+42	-41	1 files not shown
+43	-42	7 files

LLVM/project 60be55c — clang/include/clang/Basic OffloadArch.h, clang/lib/Basic Cuda.cpp OffloadArch.cpp

2026-08-01 05:27:04 UTC by Matt Arsenault on ⎇

users/arsenm/clang/offloadarch-store-vendor-gpukind

clang: Store vendor GPU kinds in OffloadArch instead of re-listing GPUs

OffloadArch was a flat enum that hand-duplicated every AMDGPU and NVPTX
targets, plus a few edge cases. This was yet another place that needed
updating every time a new target is added, which should now be avoided.
Replace with a tagged union-like scheme.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Delta		File
+103	-143	clang/include/clang/Basic/OffloadArch.h
+73	-136	clang/lib/Basic/OffloadArch.cpp
+42	-19	clang/unittests/Basic/OffloadArchTest.cpp
+12	-28	clang/lib/Basic/Cuda.cpp
+27	-10	clang/test/Misc/target-invalid-cpu-note/nvptx.c
+12	-14	clang/lib/Driver/Driver.cpp
+269	-350	8 files not shown
+304	-381	14 files

LLVM/project 9a15298 — lldb/test/API/functionalities/json/symbol-file TestSymbolFileJSON.py

2026-08-01 05:22:42 UTC by Jonas Devlieghere via GitHub on ⎇

main

[lldb][test] Skip the JSON symbol file test on WebAssembly (#213407)

A JSON symbol file requires the UUID of the module it describes, and a
WebAssembly module carries no UUID.

Delta		File
+1	-0	lldb/test/API/functionalities/json/symbol-file/TestSymbolFileJSON.py
+1	-0	1 files

LLVM/project e89830d — clang/tools/clang-format git-clang-format

2026-08-01 05:22:14 UTC by eoineoineoin via GitHub on ⎇

main

Add option to format a whole file using git-clang-format (#204336)

Today, git-clang-format will only format lines which have been modified.
However, in some cases, that's not sufficient to get a "clean" file
which would be unmodified by running `clang-format` manually.

I've got a minimal repro using the default clang-format rules. Setup a
new git repository and create a commit with an empty file:

```
mkdir /tmp/bla
cd /tmp/bla
git init
touch t.cpp
git add t.cpp
git commit -m "V1"
```

Add a line to that file containing a comment:

    [27 lines not shown]

Delta		File
+29	-16	clang/tools/clang-format/git-clang-format
+29	-16	1 files

LLVM/project d857103 — flang/lib/Lower ConvertExpr.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll bf16.ll

2026-08-01 05:08:25 UTC by Alexander Richardson on ⎇

users/arichardson/spr/riscv-add-baseline-unit-tests-for-abi-inference

rebase, fix commit message

Created using spr 1.3.8-beta.1-arichardson

Delta		File
+9,385	-9,006	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,575	-5,393	llvm/test/CodeGen/AMDGPU/maximumnum.ll
+5,454	-5,259	llvm/test/CodeGen/AMDGPU/minimumnum.ll
+4,728	-4,968	llvm/test/CodeGen/AMDGPU/bf16.ll
+3,972	-3,823	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+0	-7,750	flang/lib/Lower/ConvertExpr.cpp
+29,114	-36,199	8,245 files not shown
+332,421	-267,964	8,251 files

LLVM/project 7f07052 — llvm/docs LangRef.rst, llvm/lib/Support UnicodeNameToCodepointGenerated.cpp

2026-08-01 05:00:02 UTC by Alex Richardson via Alexander Richardson on ⎇

users/arichardson/spr/tablegen-generate-getregclassfrommatchkind-for-asmmatchers

rebase after change to no longer allow direct access to the regclass

Created using spr 1.3.8-beta.1-arichardson

Delta		File
+46,326	-45,879	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,784	-36,416	llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+24,053	-23,916	llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+27,856	-11,102	llvm/test/CodeGen/RISCV/clmul.ll
+12,227	-23,140	llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+0	-33,097	llvm/docs/LangRef.rst
+136,246	-173,550	27,760 files not shown
+1,812,315	-1,188,725	27,766 files

LLVM/project e4d410e — llvm/docs LangRef.rst, llvm/lib/Support UnicodeNameToCodepointGenerated.cpp

2026-08-01 04:59:33 UTC by Ayokunle Amodu via Alexander Richardson on ⎇

users/arichardson/spr/main.tablegen-generate-getregclassfrommatchkind-for-asmmatchers

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1-arichardson

[skip ci]

Delta		File
+46,326	-45,879	llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+25,784	-36,416	llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+24,053	-23,916	llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+27,856	-11,102	llvm/test/CodeGen/RISCV/clmul.ll
+12,227	-23,140	llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+0	-33,097	llvm/docs/LangRef.rst
+136,246	-173,550	27,759 files not shown
+1,812,303	-1,188,712	27,765 files

LLVM/project 56eb9ab — lldb/source/Plugins/Process/wasm UnwindWasm.h UnwindWasm.cpp, lldb/test/API/functionalities/gdb_remote_client TestWasm.py

2026-08-01 04:44:20 UTC by Jonas Devlieghere via GitHub on ⎇

main

[lldb] Bound a WebAssembly backtrace by the target's maximum depth (#213397)

Only UnwindLLDB honored target.process.thread.max-backtrace-depth, so
UnwindWasm reported every frame the stub sent and a stack that recursed
without end was walked to its end.

Bound the frame count by the depth on every query rather than dropping
the frames that exceed it. A Wasm call stack arrives whole on the first
query, so a depth lowered after that has to still apply, which is when a
user reaches for it. The synthetic call frame addresses stay derived
from the whole stack, so the order of the frames does not depend on the
depth.

Delta		File
+39	-0	lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
+12	-3	lldb/source/Plugins/Process/wasm/UnwindWasm.cpp
+4	-0	lldb/source/Plugins/Process/wasm/UnwindWasm.h
+55	-3	3 files

LLVM/project 9466be2 — llvm/lib/Target/X86 X86WinEHUnwindV3.cpp, llvm/test/CodeGen/X86 win64-eh-unwindv3-egpr-funclet.ll win64-eh-unwindv3-egpr-per-function.ll

2026-08-01 04:43:17 UTC by Feng Zou via GitHub on ⎇

main

[X86][APX] Fix per-function V3 unwind for EGPR functions on Windows x64 (#212924)

A function that saves a callee-saved EGPR (R16-R31) cannot be encoded with V1/V2 unwind info, so it must use V3 even when the module default stays on V1/V2 (e.g. an APX clone created by auto-dispatch alongside a baseline generic clone). The previous code rejected such functions with a recoverable backend diagnostic ("EGPR (R16-R31) requires V3 unwind info on Windows x64") instead of emitting valid V3 unwind info.

Introduce a single shared predicate, requiresWinX64UnwindV3(MF), that returns true when the whole module is in V3 mode, or when the function needs an unwind table and may use EGPR. It is consumed by X86FrameLowering (SEH prolog/epilog layout), the X86WinEHUnwindV2 pass (which skips such functions), and the X86WinEHUnwindV3 pass (which stamps a per-function .seh_unwindversion 3 on every WinEH frame -- the entry block and each funclet). Also widen the SEH_UnwindVersion pseudo operand from i1imm to i8imm since it holds 1, 2 or 3.

Delta		File
+53	-0	llvm/test/CodeGen/X86/win64-eh-unwindv3-egpr-version-switch-v1.ll
+30	-21	llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
+47	-0	llvm/test/CodeGen/X86/win64-eh-unwindv3-egpr-version-switch.ll
+39	-0	llvm/test/CodeGen/X86/win64-eh-unwindv3-egpr-v2-module.ll
+32	-0	llvm/test/CodeGen/X86/win64-eh-unwindv3-egpr-per-function.ll
+31	-0	llvm/test/CodeGen/X86/win64-eh-unwindv3-egpr-funclet.ll
+232	-21	6 files not shown
+284	-47	12 files

LLVM/project caaad6b — llvm/test/Transforms/LoopVectorize simplify-logic.ll

2026-08-01 04:39:37 UTC by Luke Lau via GitHub on ⎇

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[VPlan] Fix comments on logical-and/or combines. NFC (#213406)

The ordering needs to be adjusted to preserve poison blocking behaviour.

Delta		File
+2	-2	llvm/test/Transforms/LoopVectorize/simplify-logic.ll
+2	-2	1 files

LLVM/project 4d8c8ff — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize simplify-logic.ll

2026-08-01 04:33:50 UTC by Luke Lau via GitHub on ⎇

main

Revert "[VPlan] Remove redundant x && (y && x) -> x && y combine (#213219)" (#213405)

This reverts commit 8db13de265a5f12d49147930da6d16a3ad7b40e3.

Logical ands block poison, and commuting the operands doesn't preserve
it

Delta		File
+10	-4	llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1	-2	llvm/test/Transforms/LoopVectorize/simplify-logic.ll
+11	-6	2 files

LLVM/project cfb2eab — llvm/test/Transforms/LoopVectorize simplify-logic.ll

2026-08-01 03:47:53 UTC by Luke Lau via GitHub on ⎇

main

[VPlan] Add tests for logical and and logical or combines. NFC (#213402)

Delta		File
+481	-0	llvm/test/Transforms/LoopVectorize/simplify-logic.ll
+481	-0	1 files