LLVM/project 49c714eclang-tools-extra/clang-tidy/bugprone StdExceptionBaseclassCheck.cpp StdExceptionBaseclassCheck.h, clang-tools-extra/clang-tidy/hicpp ExceptionBaseclassCheck.cpp ExceptionBaseclassCheck.h

[clang-tidy] Rename hicpp-exception-baseclass to bugprone-exception-baseclass (#183474)

Part of the work in https://github.com/llvm/llvm-project/issues/183462.

Closes https://github.com/llvm/llvm-project/issues/183463.
DeltaFile
+0-284clang-tools-extra/test/clang-tidy/checkers/hicpp/exception-baseclass.cpp
+284-0clang-tools-extra/test/clang-tidy/checkers/bugprone/std-exception-baseclass.cpp
+0-57clang-tools-extra/clang-tidy/hicpp/ExceptionBaseclassCheck.cpp
+57-0clang-tools-extra/clang-tidy/bugprone/StdExceptionBaseclassCheck.cpp
+0-34clang-tools-extra/clang-tidy/hicpp/ExceptionBaseclassCheck.h
+34-0clang-tools-extra/clang-tidy/bugprone/StdExceptionBaseclassCheck.h
+375-3758 files not shown
+426-40214 files

LLVM/project c53ee83llvm/test/CodeGen/AMDGPU dynamic_stackalloc.ll wave-reduce-dpp-i32.mir

[AMDGPU] DPP implementations for Wave Reduction

Adding DPP reduction support for i32 types.
Supported Ops: `umin`, `min`, `umax`, `max`,
`add`, `sub`, `and`, `or`, `xor`.
DeltaFile
+2,113-1,374llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+1,255-0llvm/test/CodeGen/AMDGPU/wave-reduce-dpp-i32.mir
+1,096-146llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+1,047-142llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+986-132llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+894-108llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+7,391-1,9028 files not shown
+12,444-2,80314 files

LLVM/project d5a5761clang-tools-extra/test/clang-tidy/checkers/bugprone narrowing-conversions-bitfields.cpp incorrect-enable-if.cpp, clang-tools-extra/test/clang-tidy/checkers/misc unconventional-assign-operator.cpp

[clang-tidy][NFC] Use universal utility mock in testcases [2/N] (#185797)

As of AI Usage: Gemini 3 and Codex is used for cleanup and pre-commit
reviewing.
DeltaFile
+20-30clang-tools-extra/test/clang-tidy/checkers/bugprone/narrowing-conversions-bitfields.cpp
+1-26clang-tools-extra/test/clang-tidy/checkers/performance/string-view-conversions.cpp
+2-23clang-tools-extra/test/clang-tidy/checkers/modernize/avoid-c-arrays.cpp
+1-11clang-tools-extra/test/clang-tidy/checkers/modernize/use-constraints-first-greatergreater.cpp
+1-11clang-tools-extra/test/clang-tidy/checkers/bugprone/incorrect-enable-if.cpp
+1-11clang-tools-extra/test/clang-tidy/checkers/misc/unconventional-assign-operator.cpp
+26-11210 files not shown
+45-18316 files

LLVM/project c04fbadlibunwind/src libunwind.cpp, libunwind/test cfi_violating_handler.pass.cpp

[libunwind][PAC] Defang ptrauth's PC in valid CFI range abort

It turns out making the CFI check a release mode abort causes many,
if not the majority, of JITs to fail during unwinding as they do not
set up CFI sections for their generated code. As a result any JITs
that do nominally support unwinding (and catching) through their JIT
or assembly frames trip this abort.

rdar://170862047
DeltaFile
+101-0libunwind/test/cfi_violating_handler.pass.cpp
+11-17libunwind/src/libunwind.cpp
+112-172 files

LLVM/project a95f4acllvm/lib/Target/RISCV RISCVInstrInfoZb.td RISCVFeatures.td

[RISCV] Replace HasStdExtZbcOrZbkc with HasStdExtZbkc. NFC (#185790)

Zbc now implies Zbkc so we don't need an Or. I've moved the diagnostic
string from HasStdExtZbcOrZbkc to HasStdExtZbkc to avoid assembler
output changes.
DeltaFile
+6-6llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+3-8llvm/lib/Target/RISCV/RISCVFeatures.td
+9-142 files

LLVM/project 7a43f77compiler-rt/lib/builtins CMakeLists.txt, compiler-rt/lib/builtins/wasm __c_longjmp.S

[WebAssembly] Remove `__c_longjmp` from compiler-rt (#185798)

This is similar to #185770 where it removes an
exception-handling-related symbol from `compiler-rt` in favor of having
definitions elsewhere. The compiler-rt library is linked into all shared
objects, for example, which can result in duplicate definitions of a
symbol where this tag wants to have one unique definition. The intention
behind this commit is to defer the definition of this symbol to
downstream libraries, such as the definition of `longjmp` itself. An
example of this is WebAssembly/wasi-libc#772 where the responsibility of
defining this symbol now lies with wasi-libc.
DeltaFile
+0-26compiler-rt/lib/builtins/wasm/__c_longjmp.S
+0-6llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni
+0-1compiler-rt/lib/builtins/CMakeLists.txt
+0-333 files

LLVM/project 217dcabllvm/test/Analysis/DependenceAnalysis weak-zero-siv-delta-signed-min.ll

[DA] Add tests for the Weak Zero SIV tests miss dependency (NFC) (#184998)

Add test cases where the Weak Zero SIV tests miss dependencies due to
the calculation of negative values. SCEV represents the negative value
of `x` as `-1 * x`. When `x` is the signed minimum value, this
expression effectively evaluates to `x`, which causes DA to miss the
dependency. In DA, if we cannot prove that the value is not the signed
minimum when computing the negative value, the analysis should bail out.
DeltaFile
+111-0llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-delta-signed-min.ll
+111-01 files

LLVM/project bbd80eaclang/include/clang/AST Decl.h, clang/lib/AST Decl.cpp

[Clang][NFC] Make remaining Decl.h methods accept const ASTContext

Complete the const-correctness of ASTContext parameters in Decl.h by
updating the three previously excepted methods:

- TranslationUnitDecl::Create() and constructor: Now accept const
  ASTContext& and store it as a const reference. The getASTContext()
  method uses const_cast to maintain API compatibility with code that
  expects a non-const reference. This is safe since the ASTContext is
  always created as non-const.

- DefaultedOrDeletedFunctionInfo::Create(): Now accepts const ASTContext&
  since ASTContext::Allocate() is already a const method.

All Create(), CreateDeserialized(), and constructor methods in Decl.h
now consistently accept const ASTContext& references with zero exceptions.

Assisted-By: Claude Sonnet 4.5
DeltaFile
+7-5clang/include/clang/AST/Decl.h
+3-3clang/lib/AST/Decl.cpp
+10-82 files

LLVM/project 6f3ef34clang/lib/Index USRGeneration.cpp, clang/lib/UnifiedSymbolResolution USRGeneration.cpp

Merge branch 'main' into users/kasuga-fj/da-weak-zero-siv-delta-min
DeltaFile
+1,352-0clang/lib/UnifiedSymbolResolution/USRGeneration.cpp
+0-1,284clang/lib/Index/USRGeneration.cpp
+1,151-0llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+1,066-36llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
+334-580llvm/test/CodeGen/X86/funnel-shift-i256.ll
+692-76llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
+4,595-1,976909 files not shown
+31,253-11,074915 files

LLVM/project 7baee63libunwind/src libunwind.cpp, libunwind/test cfi_violating_handler.pass.cpp

[libunwind][PAC] Defang ptrauth's PC in valid CFI range abort

It turns out making the CFI check a release mode abort causes many,
if not the majority, of JITs to fail during unwinding as they do not
set up CFI sections for their generated code. As a result any JITs
that do nominally support unwinding (and catching) through their JIT
or assembly frames trip this abort.

rdar://170862047
DeltaFile
+73-0libunwind/test/cfi_violating_handler.pass.cpp
+11-17libunwind/src/libunwind.cpp
+84-172 files

LLVM/project 5799a5dlldb/packages/Python/lldbsuite/test lldbtest.py decorators.py

[lldb/test] Add generic test variant infrastructure (#185145)

Add a generic `TestVariant` class and `_expand_test_variants` function
that can be used to create new test variant dimensions (similar to the
existing debug_info variant expansion).

Each TestVariant describes a dimension that multiplies test methods by
different configurations. The infrastructure handles method expansion,
xfail/skip decorator support, and setUp-time configuration.

This also generalizes `_xfailForDebugInfo`/`_skipForDebugInfo` into
`_xfailForVariant`/`_skipForVariant`, and changes the decorator's inner
fn() to accept **kwargs so variant values can be passed by name.

The `_test_variants` list is currently empty — downstream forks (i.e.
swift) can register their own variants without modifying the metaclass
logic.

Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
DeltaFile
+215-39lldb/packages/Python/lldbsuite/test/lldbtest.py
+44-10lldb/packages/Python/lldbsuite/test/decorators.py
+259-492 files

LLVM/project 7472b4aclang/include/clang/Basic AttrDocs.td Attr.td, clang/lib/CodeGen CodeGenFunction.cpp

Basic,Sema: introduce `__attribute__((__personality__(...)))` (#185225)

This attribute allows specifying a custom personality routine for a
function, overriding the default emitted by Clang. The motivating use
case is the Swift concurrency runtime, where C/C++ runtime functions
need to act as barriers for exception propagation — the custom
personality ensures exceptions do not propagate through these frames
unchecked. More generally, this is useful whenever a language runtime is
implemented in a host language with different EH semantics. LLVM IR
already supports arbitrary personality functions on definitions; this
attribute simply exposes that capability to the C/C++ frontend.

Co-authored-by: Erich Keane <ekeane at nvidia.com>
DeltaFile
+80-0clang/test/CodeGen/attr-personality.c
+30-0clang/test/CodeGen/attr-personality-failures.c
+27-0clang/lib/Sema/SemaDeclAttr.cpp
+18-0clang/include/clang/Basic/AttrDocs.td
+9-0clang/lib/CodeGen/CodeGenFunction.cpp
+7-0clang/include/clang/Basic/Attr.td
+171-05 files not shown
+188-011 files

LLVM/project f2f5845llvm/lib/Target/WebAssembly WebAssemblyFastISel.cpp, llvm/test/CodeGen/WebAssembly load-ext.ll offset-fastisel.ll

[WebAssembly][FastISel] Fold AND mask operations into ZExt load (#183743)

FastISel emits separate load and AND instructions for bitmasking.
(before) %1:i32 = LOAD_I32 %addr; %2:i32 = AND_I32 %1, 255

Fold AND masks into ZExt loads by verifying operands with
maskTrailingOnes. A getFoldedLoadOpcode wrapper is implemented
to manage dispatching logic for better extensibility.
(after) %1:i32 = LOAD8_U_I32 %addr

Fixed: https://github.com/llvm/llvm-project/issues/180783
DeltaFile
+40-72llvm/test/CodeGen/WebAssembly/load-ext.ll
+64-3llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+1-3llvm/test/CodeGen/WebAssembly/offset-fastisel.ll
+105-783 files

LLVM/project 3752a35llvm/test/CodeGen/AArch64 clmul-fixed.ll, llvm/test/CodeGen/PowerPC clmul-vector.ll

Merge branch 'fix-blockfreq-unroll-unconditional-latches--fast' into fix-blockfreq-unroll-unconditional-latches--uniform
DeltaFile
+54,752-7,425llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+18,872-3,329llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+6,812-3,080llvm/test/CodeGen/AArch64/clmul-fixed.ll
+5,488-0llvm/test/CodeGen/X86/bit-manip-i512.ll
+2,338-2,209llvm/test/CodeGen/PowerPC/clmul-vector.ll
+1,561-2,812llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+89,823-18,8553,075 files not shown
+208,349-63,4473,081 files

LLVM/project e950a80llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/WebAssembly simd-offset.ll

[WebAssembly] Look through freeze nodes when folding vector load + ext (#185143)

When folding loads with extensions, the extension operand can be a freeze node
in addition to a load. We can look through it to do the desirability check.

Fixes #184676
DeltaFile
+16-0llvm/test/CodeGen/WebAssembly/simd-offset.ll
+7-1llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+23-12 files

LLVM/project 53a2fd9llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 icmp-shift-opt.ll

[DAGCombiner] Combine (fshl A, B, S) | (fshr C, D, BW-S) --> (fshl (A|C), (B|D), S) (#180889)

This is similar to the FSHL/FSHR handling in
hoistLogicOpWithSameOpcodeHands.
Here the opcodes aren't exactly the same, but the operations are
equivalent.

Fixes regressions from #180888
DeltaFile
+8-12llvm/test/CodeGen/X86/icmp-shift-opt.ll
+18-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+26-122 files

LLVM/project c95450fllvm/test/CodeGen/AArch64 clmul-fixed.ll, llvm/test/CodeGen/PowerPC clmul-vector.ll

Merge branch 'fix-blockfreq-unroll-unconditional-latches' into fix-blockfreq-unroll-unconditional-latches--fast
DeltaFile
+54,752-7,425llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+18,872-3,329llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+6,812-3,080llvm/test/CodeGen/AArch64/clmul-fixed.ll
+5,488-0llvm/test/CodeGen/X86/bit-manip-i512.ll
+2,338-2,209llvm/test/CodeGen/PowerPC/clmul-vector.ll
+1,561-2,812llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+89,823-18,8553,075 files not shown
+208,349-63,4473,081 files

LLVM/project 482bb3dllvm/include/llvm/Transforms/Vectorize/SandboxVectorizer DependencyGraph.h, llvm/lib/Transforms/Vectorize/SandboxVectorizer DependencyGraph.cpp

[SandboxVec][DAG] Mark UnscheduledSuccs as invalid when vectorized (#185519)

When a DAG node gets scheduled, it's UnscheduledSuccs variable becomes
invalid. Up until now we had no way in the code of expressing this.

This patch converts UnscheduledSuccs to an std::optional in order to
protect its use when not valid.
DeltaFile
+24-10llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.h
+21-4llvm/unittests/Transforms/Vectorize/SandboxVectorizer/DependencyGraphTest.cpp
+3-3llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
+48-173 files

LLVM/project 86bf89aclang/test/AST/ByteCode builtin-functions.cpp, clang/test/Sema constant-builtins-2.c

[test] Add bit < 8 testcase for x86 __builtin_bswapg (#180124)

### Summary
the related PR: https://github.com/llvm/llvm-project/pull/179177, add
bits < 8 testcase for __builtin_bswapg
DeltaFile
+3-0clang/test/AST/ByteCode/builtin-functions.cpp
+2-0clang/test/Sema/constant-builtins-2.c
+2-0clang/test/SemaCXX/builtin-bswapg.cpp
+7-03 files

LLVM/project 2410418llvm/lib/Target/RISCV RISCVISelLowering.cpp

[RISCV] Refactor lowerBUILD_VECTOR splat opcode selection to avoid duplication. NFC. (#185573)

Hoist the common ANY_EXTEND, DAG.getNode, and convertFromScalableVector
calls out of the duplicated if/else branches. Use a single IsScalar bool
to select between VMV_S_X_VL/VFMV_S_F_VL and VMV_V_X_VL/VFMV_V_F_VL.
DeltaFile
+9-15llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+9-151 files

LLVM/project a3f2823compiler-rt/lib/builtins CMakeLists.txt, compiler-rt/lib/builtins/wasm __cpp_exception.S

[WebAssembly] Move __cpp_exception to libunwind (#185770)

The `__cpp_exception` symbol is now defined in libunwind instead of
compiler-rt. This is moved for a few reasons, but the primary reason is
that compiler-rt is linked duplicate-ly into all shared objects meaning
that it's not suitable for define-once symbols such as
`__cpp_exception`. By moving the definition to the user of the symbol,
libunwind itself, that guarantees that the symbol should be defined
exactly once and only when appropriate. A secondary reason for this
movement is that it avoids the need to compile compiler-rt twice: once
with exception and once without, and instead the same build can be used
for both exceptions-and-not.
DeltaFile
+0-26compiler-rt/lib/builtins/wasm/__cpp_exception.S
+15-0libunwind/src/Unwind-wasm.c
+0-1llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni
+0-1compiler-rt/lib/builtins/CMakeLists.txt
+15-284 files

LLVM/project 7ad5ff1cmake/Modules LLVMVersion.cmake, libcxx/include __config

Bump version to 22.1.2
DeltaFile
+1-1cmake/Modules/LLVMVersion.cmake
+1-1libcxx/include/__config
+1-1llvm/utils/gn/secondary/llvm/version.gni
+1-1llvm/utils/lit/lit/__init__.py
+1-1llvm/utils/mlgo-utils/mlgo/__init__.py
+5-55 files

LLVM/project 78beeb7clang/lib/Driver/ToolChains WebAssembly.cpp, clang/test/Driver wasm-toolchain.cpp

[WebAssembly] Clang support for exception-based lookup paths (#185775)

This commit is an attempt to make progress on WebAssembly/wasi-sdk#565
where with wasi-sdk I'd like to ship a single toolchain which is capable
of building binaries both with C++ exceptions and without. This means
that there can't be a single set of precompiled libraries that are used
because one set of libraries is wrong for the other mode. The support
added here is to use `-fwasm-exceptions` to automatically select a
lookup path in the sysroot. The intention is then that wasi-sdk will
ship both a "eh" set of C++ libraries as well as a "noeh" set of C++
libraries too. Clang will automatically select the correct one based on
compilation flags which means that the final distribution will be able
to build both binaries with exceptions and without.
DeltaFile
+35-16clang/lib/Driver/ToolChains/WebAssembly.cpp
+35-0clang/test/Driver/wasm-toolchain.cpp
+70-162 files

LLVM/project 757a0f8llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp DAGCombiner.cpp, llvm/test/CodeGen/X86 nofpclass.ll

SelectionDAG: Use ISD::AssertNoFPClass for Load with nofpclass metadata (#184952)

1. Use ISD::AssertNoFPClass if LoadInst has !nofpclass metadata.
2. Strip ISD::AssertNoFPClass when try to combine load with bitcast
    in DAGCombiner::visitBITCAST.
DeltaFile
+55-0llvm/test/CodeGen/X86/nofpclass.ll
+12-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+2-0llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+69-03 files

LLVM/project f0ad981llvm/lib/MC MCLFIRewriter.cpp, llvm/lib/MC/MCParser LFIAsmParser.cpp

[NFC][MC] Style cleanup in MC-level LFI files (#185508)

Following
https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-define-previously-declared-symbols
and https://llvm.org/docs/CodingStandards.html#restrict-visibility.
DeltaFile
+3-3llvm/lib/MC/MCParser/LFIAsmParser.cpp
+1-2llvm/lib/MC/MCLFIRewriter.cpp
+4-52 files

LLVM/project b84ea71clang/lib/Headers hexagon_types.h, clang/test/Headers hexagon-types-b0-conflict.c

[Hexagon] Fix B0 macro conflict between hexagon_types.h and termios.h (#184539)

POSIX termios.h defines `#define B0 0000000` for baud rate 0. This
conflicts with the B0() member functions in hexagon_types.h vector
classes, causing compilation failures when both headers are included.

Use #pragma push_macro/pop_macro to save, undefine, and restore B0
around the class definitions so the header is safe to use alongside
termios.h without losing the macro afterward.

Fixes #183815
DeltaFile
+23-20clang/lib/Headers/hexagon_types.h
+38-0clang/test/Headers/hexagon-types-b0-conflict.c
+61-202 files

LLVM/project b8fc15dllvm/test/CodeGen/AArch64 clmul-fixed.ll, llvm/test/CodeGen/PowerPC clmul-vector.ll

Merge branch 'fix-blockfreq-unroll-unconditional-latches--prep' into fix-blockfreq-unroll-unconditional-latches
DeltaFile
+54,752-7,425llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+18,872-3,329llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+6,812-3,080llvm/test/CodeGen/AArch64/clmul-fixed.ll
+5,488-0llvm/test/CodeGen/X86/bit-manip-i512.ll
+2,338-2,209llvm/test/CodeGen/PowerPC/clmul-vector.ll
+1,561-2,812llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+89,823-18,8553,075 files not shown
+208,349-63,4473,081 files

LLVM/project aa5767elibclc CMakeLists.txt, libclc/cmake/modules AddLibclc.cmake

[libclc][CMake] Add back OUTPUT_FILENAME and PARENT_TARGET (#185633)

They were droped in e20ae16ce672.
OUTPUT_FILENAME is helpful for customizing library name. PARENT_TARGET
could be helpful for customizing dependency control.
DeltaFile
+18-6libclc/cmake/modules/AddLibclc.cmake
+2-0libclc/CMakeLists.txt
+20-62 files

LLVM/project cf8833ellvm/lib/Target/BPF BPFMISimplifyPatchable.cpp, llvm/test/CodeGen/BPF/CORE offset-reloc-simplify-patchable-4.ll offset-reloc-simplify-patchable-5.ll

[BPF] Fix CORE optimization bug in BPFMISimplifyPatchable (#183446)

Commit ffd57408efd4 ("[BPF] Enable relocation location for
load/store/shifts") enabled CORE relocation for load/store/shirts. In
particular, the commit did optimization to have load/store/shift insn
itself having the relocation. For the load and store, the optimization
has the following:
  rX = *(rY + <relocation>) and *(rX + <relocation>) = rY

There is no value-range check for the above '<relocation>'. For example,
if the original `<relocation>` is 0x10006 due to a large struct, the
insn encoding of `<relocaiton>` will be truncated into '6' and incorrect
result will happen.

This patch fixed the issue by checking the value range of
'<relocation>'. If the `<relocation>` is more than INT16_MAX,
optimization will be skipped.

Even llvm side is fixed, libbpf side may still have issues with the

    [35 lines not shown]
DeltaFile
+123-0llvm/test/CodeGen/BPF/CORE/offset-reloc-simplify-patchable-4.ll
+123-0llvm/test/CodeGen/BPF/CORE/offset-reloc-simplify-patchable-5.ll
+22-3llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
+268-33 files

LLVM/project 69a5eb9llvm/lib/Target/AMDGPU AMDGPUMCInstLower.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp AMDGPUBaseInfo.h

[AMDGPU] Add asm comments if setreg changes MSBs
DeltaFile
+45-0llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
+19-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+13-5llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+7-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+2-1llvm/test/CodeGen/AMDGPU/code-size-estimate.ll
+86-65 files