LLVM/project fea0bd0clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU][Clang] Use ScopeModel in ProcessOrderScopeAMDGCN [NFC]
DeltaFile
+16-31clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+16-311 files

LLVM/project 9d62e96llvm/include/llvm/IR Operator.h InstrTypes.h, llvm/lib/IR Instructions.cpp Operator.cpp

[IR] Store fast-math flags in subclasses of Instruction (#191190)

Move fast-math flags out from `Value`, because we are out of space of
`Value::SubclassOptionalData` and it is incompatible with other
optimization flags like `nneg`.
FP variant for `call/select/phi` is not introduced, because of
`mutateType`, it may change the type of the `Instruction` instance,
which may cause UB.

RFC:
https://discourse.llvm.org/t/rfc-store-fast-math-flags-in-subclasses-of-instruction/
DeltaFile
+20-64llvm/include/llvm/IR/Operator.h
+65-2llvm/include/llvm/IR/InstrTypes.h
+47-13llvm/lib/IR/Instructions.cpp
+23-0llvm/lib/IR/Operator.cpp
+9-7llvm/include/llvm/IR/Instructions.h
+6-6llvm/include/llvm/IR/Instruction.def
+170-921 files not shown
+172-927 files

LLVM/project 2d9407bllvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-reduce-smin.ll vector-reduce-smax.ll

[X86] Add handling for sub-128bit minmax reductions (#198319)

Fold sub-128bit minmax reductions as ISD::VECREDUCE nodes.

This needed some cleanup to correct discard "identity value padded"
upper elements from legalisation - existing folds struggle to do this
due to the DemandedElts mask needing to be accurate enough (and
reductions nearly always result in multiple uses of source operands) -
I've been trying to do something similar in
TargetLowering::expandVecReduce but haven't managed it yet.

Final backend patch blocking #194473 - still some middle-end reduction
pattern matching that needs some fixing first though.
DeltaFile
+43-77llvm/test/CodeGen/X86/vector-reduce-smin.ll
+42-76llvm/test/CodeGen/X86/vector-reduce-smax.ll
+25-12llvm/lib/Target/X86/X86ISelLowering.cpp
+13-22llvm/test/CodeGen/X86/vector-reduce-umin.ll
+13-20llvm/test/CodeGen/X86/vector-reduce-umax.ll
+2-2llvm/test/CodeGen/X86/vector-extract-last-active.ll
+138-2096 files

LLVM/project cecdf6cflang/include/flang/Optimizer/Dialect/CUF/Attributes CUFAttr.h, flang/lib/Optimizer/Transforms CompilerGeneratedNames.cpp

[CUF] Fix CompilerGeneratedNamesConversion renaming managed companion globals

CUFAddConstructor creates a companion pointer global (e.g. foo.managed.ptr)
for each non-allocatable managed variable. When CompilerGeneratedNamesConversion
ran after CUFAddConstructor, it replaced the dots with 'X',
so CUFOpConversionLate could no longer find the companion by name and fell back
to CUFGetDeviceAddress with the wrong host pointer, causing cudaErrorInvalidSymbol.

Fix: mark the companion global with a cuf.managed_ptr unit attribute in
CUFAddConstructor and skip it in CompilerGeneratedNamesConversionPass.

Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+51-0flang/test/Fir/CUDA/cuda-managed-ptr-companion.mlir
+7-0flang/include/flang/Optimizer/Dialect/CUF/Attributes/CUFAttr.h
+3-1flang/lib/Optimizer/Transforms/CompilerGeneratedNames.cpp
+2-2flang/test/Fir/CUDA/cuda-constructor-2.f90
+3-0flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
+66-35 files

LLVM/project 0a3b9c2flang/include/flang/Optimizer/Dialect/CUF/Attributes CUFAttr.h, flang/lib/Optimizer/Transforms CompilerGeneratedNames.cpp

[CUF] Handle renamed managed companion pointer in CUFDeviceAddressOpConversion

CUFAddConstructor creates a companion pointer global (@sym.managed.ptr) for
each non-allocatable managed variable. CompilerGeneratedNamesConversion may
run before CUFOpConversionLate and rename the global by replacing dots with
'X', producing @symXmanagedXptr. Extend CUFDeviceAddressOpConversion to try
both the original and the renamed suffix when looking up the companion pointer.

Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+0-51flang/test/Fir/CUDA/cuda-managed-ptr-companion.mlir
+30-0flang/test/Fir/CUDA/cuda-device-address.mlir
+0-7flang/include/flang/Optimizer/Dialect/CUF/Attributes/CUFAttr.h
+6-0flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
+1-3flang/lib/Optimizer/Transforms/CompilerGeneratedNames.cpp
+2-2flang/test/Fir/CUDA/cuda-constructor-2.f90
+39-631 files not shown
+39-667 files

LLVM/project b6d485fllvm/include/llvm/CodeGen MachineScheduler.h, llvm/lib/Target/RISCV RISCVTargetMachine.cpp

[MISched] Make TG MacroFusion creation target specific(NFC) (#198304)

This patch moves TableGen-based macro fusion initialization from generic
MachineScheduler factory methods, to the specific targets that use it,
currently only RISCV. This better enables targets to have complete
control over DAG mutation ordering, e.g. for porting other targets to
TableGen macro fusion. More specifically, AArch64 requires the inverse
partial order between ld/st clustering and macro fusion, as part of an
attempt to migrate it to TableGen.
DeltaFile
+2-14llvm/include/llvm/CodeGen/MachineScheduler.h
+10-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+12-142 files

LLVM/project 916347allvm/lib/Target/AArch64 AArch64Processors.td

[AArch64] Apply generational deltas for Apple tuning features (#197115)

This patch refactors how we manage tuning features for AArch64 Apple
CPUs. Instead of duplicating feature lists for each generation, we now
form a chain such that every generation only adds or removes features
from the immediate predecessor.

This creates a much more compact representation, enables to view
generational changes at a glance, and can reduce potential copy-paste
errors by establishing a more structured dataflow.

However, not without pitfalls: to gather a feature list for a specific
gen we need to traverse a chain, and feature addition and removal
becomes more subtle as it propagates across the chain. The TableGen test
of complete feature lists per generation may alleviate these issues a
bit.
DeltaFile
+28-188llvm/lib/Target/AArch64/AArch64Processors.td
+28-1881 files

LLVM/project c606dbd.github CODEOWNERS

[AMDGPU] Add Pierre-vh and ritter-x2a as memory model code owners (#198247)

Covers both SIMemoryLegalizer (code sequence lowering) and
InsertWaitcnt.
DeltaFile
+7-3.github/CODEOWNERS
+7-31 files

LLVM/project ed990cdllvm/runtimes CMakeLists.txt

[cmake][runtimes] Remove obsolete LLVM_RUNTIMES_PREFIX (#198367)

Hasn't been used by anything for close to 8 years.

Fixes: 887f26d4703616934fd7a11b6649f605e1c7b4e3
DeltaFile
+1-2llvm/runtimes/CMakeLists.txt
+1-21 files

LLVM/project 4e2f71dllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/RISCV basic-strided-stores.ll

[SLP] Properly handle re-ordering of strided stores (#198408)

Currently, strided stores that are reordered (except for reversed strided stores) output incorrect shuffle indexes.
DeltaFile
+6-5llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-2llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-stores.ll
+8-72 files

LLVM/project 6054851llvm/lib/Target/X86 X86FrameLowering.cpp

[x86] De-type getMinimalPhysRegClass uses (NFC) (#198332)

Pulled out of #197495 which is de-typing this API. There's very few uses
of this API with a type across the whole codebase and only three in x86
related to callee-saves where an RC can instead be chosen directly.
DeltaFile
+11-18llvm/lib/Target/X86/X86FrameLowering.cpp
+11-181 files

LLVM/project 0df8d47llvm/lib/Target/AMDGPU SILowerSGPRSpills.cpp

[AMDGPU] De-type getMinimalPhysRegClass uses (NFC) (#198301)

Pulled out of #197495 which is de-typing this API. There's very few uses
of this API with a type across the whole codebase and only two in AMDPU.
No test fallout when dropping the type from these calls, so I'm assuming
they're not necessary.
DeltaFile
+2-4llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+2-41 files

LLVM/project f60e413libc/src/__support/OSUtil/linux/syscall_wrappers CMakeLists.txt accept.h

[libc] Migrate socket syscall wrappers to syscall_checked (#198241)

Also update the file headers while I'm at it. Move includes into a
single block so that clang-format can enforce a consistent ordering. Fix
a couple of discrepancies in the cmake file.

Assisted by Gemini.
DeltaFile
+18-7libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
+11-11libc/src/__support/OSUtil/linux/syscall_wrappers/accept.h
+10-9libc/src/__support/OSUtil/linux/syscall_wrappers/setsockopt.h
+10-9libc/src/__support/OSUtil/linux/syscall_wrappers/getsockopt.h
+10-9libc/src/__support/OSUtil/linux/syscall_wrappers/connect.h
+10-9libc/src/__support/OSUtil/linux/syscall_wrappers/accept4.h
+69-544 files not shown
+89-7810 files

LLVM/project 94dbed2clang/lib/StaticAnalyzer/Checkers/WebKit RawPtrRefCallArgsChecker.cpp, clang/test/Analysis/Checkers/WebKit call-args.cpp

[alpha.webkit.UncountedCallArgsChecker] Check arguments of function pointers (#188162)

This PR fixes a hole in WebKit's static analysis that we weren't
checking the soundness of argumnets to a function call via a (member)
function pointer.
DeltaFile
+58-48clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
+23-0clang/test/Analysis/Checkers/WebKit/call-args.cpp
+81-482 files

LLVM/project c459d86clang/lib/StaticAnalyzer/Checkers/WebKit ASTUtils.cpp PtrTypesSemantics.cpp, clang/test/Analysis/Checkers/WebKit call-args.cpp binding-to-refptr.cpp

[alpha.webkit.UncountedCallArgsChecker] Emit a warning for a WeakPtr argument. (#184563)

This PR fixes a bug in UncountedCallArgsChecker that it would not emit a
warning when a function is called with a WeakPtr local variable as an
argument.

We normally don't generate a warning for a local variable passed to a
function argument in UncountedCallArgsChecker as the variable may have a
guardian in an outer scope but only UncountedLocalVarsChecker is capable
of locating one. So rather than generating a warning in
UncountedCallArgsChecker directly, we rely on UncountedLocalVarsChecker
to generate a warning for the local variable.

This all falls apart in the case of a WeakPtr local variable because a
WeakPtr is explicitly allowed as a local variable by
UncountedLocalVarsChecker.

So, this PR fixes the bug by detecting this exact scenario (a WeakPtr
local variable used as a function argument), and generate a warning

    [7 lines not shown]
DeltaFile
+18-0clang/test/Analysis/Checkers/WebKit/call-args.cpp
+14-4clang/test/Analysis/Checkers/WebKit/binding-to-refptr.cpp
+14-4clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
+15-2clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
+5-1clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
+3-0clang/test/Analysis/Checkers/WebKit/mock-types.h
+69-116 files

LLVM/project 07d0ff1clang/test/Preprocessor riscv-target-features.c, llvm/lib/Target/RISCV RISCVInstrInfoXqccmt.td RISCVFeatures.td

[RISCV] Add assembler and disassembler support for Xqccmt extension (#197673)

Xqccmt is Qualcomm's vendor extension providing compressed (16-bit) jump
table instructions, equivalent to (and mutually exclusive with) the
standard Zcmt extension.

Two instructions are added:
- qc.cm.jt  (index 0-31):  jump via table, no link register written
- qc.cm.jalt (index 32-255): jump via table with link; bit 0 of the jump
table entry selects the link register at runtime: 0 = ra (x1), 1 = t0
(x5)

The encoding is identical to cm.jt/cm.jalt from Zcmt. Xqccmt and Zcmt
are mutually exclusive and cannot be combined. Xqccmt is also
incompatible with Zcd (overlapping encoding space).

Spec: https://github.com/riscv/riscv-unified-db/pull/1788
DeltaFile
+51-0llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td
+45-0llvm/test/MC/RISCV/xqccmt-valid.s
+29-0llvm/test/MC/RISCV/xqccmt-user-csr-name.s
+14-0clang/test/Preprocessor/riscv-target-features.c
+13-0llvm/test/MC/RISCV/xqccmt-invalid.s
+8-0llvm/lib/Target/RISCV/RISCVFeatures.td
+160-010 files not shown
+189-116 files

LLVM/project d09ffballdb/docs/resources formatterbytecode.rst, lldb/examples/python formatter_bytecode.py

[lldb][bytecode] Add GetParent and Clone selectors (#197312)

`GetParent` and `Clone` are needed to implement a `std::optional<T>`
data formatter for libc++.
DeltaFile
+15-0lldb/source/DataFormatters/FormatterBytecode.cpp
+11-0lldb/examples/python/formatter_bytecode.py
+2-0lldb/docs/resources/formatterbytecode.rst
+2-0lldb/include/lldb/DataFormatters/FormatterBytecode.def
+30-04 files

LLVM/project b20b8d4llvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/Target/X86 X86InstrSSE.td X86InstrAVX512.td

[X86] Remove extra MOV after widening atomic store

This change adds patterns to optimize out an extra MOV present after
widening the atomic store. Covers <2 x i8> (SSE4.1+), <2 x i16>,
<4 x i8>, <2 x i32>, <2 x float>, <4 x i16>, <2 x ptr addrspace(270)>.
DeltaFile
+47-64llvm/test/CodeGen/X86/atomic-load-store.ll
+30-24llvm/test/CodeGen/X86/atomic-unordered.ll
+35-0llvm/include/llvm/Target/TargetSelectionDAG.td
+10-10llvm/lib/Target/X86/X86InstrSSE.td
+6-6llvm/lib/Target/X86/X86InstrAVX512.td
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+129-1056 files

LLVM/project 7637943llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Widen <2 x T> vector types for atomic store

Vector types of 2 elements must be widened. This change does this
for vector types of atomic store in SelectionDAG so that it can
translate aligned vectors of >1 size.
DeltaFile
+198-0llvm/test/CodeGen/X86/atomic-load-store.ll
+54-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+253-03 files

LLVM/project 94667a7lldb/include/lldb/ValueObject ValueObject.h, lldb/source/API SBValue.cpp

[lldb] Increase availability of ValueObject::GetParent (#197311)

While working formatter bytecode, one of the C++ formatters needs
`GetParent`. While adding `GetParent` support in the bytecode, I noticed
the SB API also does not expose `GetParent`. This remedies that.

During review of this PR, it was pointed out that `GetParent` does work
with synthetic value objects. This PR also addresses that shortcoming.

Assisted-by: claude
DeltaFile
+39-0lldb/test/API/python_api/sbvalue_get_parent/TestSBValueGetParent.py
+15-0lldb/test/API/python_api/sbvalue_get_parent/main.cpp
+12-2lldb/include/lldb/ValueObject/ValueObject.h
+14-0lldb/source/API/SBValue.cpp
+3-0lldb/source/ValueObject/ValueObjectSynthetic.cpp
+2-0lldb/test/API/python_api/sbvalue_get_parent/Makefile
+85-22 files not shown
+88-28 files

LLVM/project 3e70c42llvm/lib/Target/AMDGPU AMDGPULibCalls.cpp, llvm/test/CodeGen/AMDGPU amdgpu-simplify-libcall-ldexp.ll

[AMDGPU] AMDGPULibCalls: Set new ldexp intrinsic calling convention to C (#198246)

Found the issue while trying to add libclc test for ldexp.
DeltaFile
+10-0llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-ldexp.ll
+1-0llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+11-02 files

LLVM/project 00b13e2clang/lib/AST/ByteCode Interp.h Interp.cpp, clang/test/SemaCXX constant-expression-p2280r4.cpp

[clang][bytecode] Improve constexpr-unknown handling (#196334)

1) Global variables as well as dummies can not be marked
constexpr-unknown. There is a subtlety here with global variables: we
can't register it as constexpr-unknown and later figure out that it
actually _isn't_.
 2) Add a `GetRefGlobal` op similar to the existing `GetRefLocal`.
 3) Reject constexpr-unknown values in `CmpHelperEQ<Pointer>`
 4) Diagnose constexpr-unknown values in `GetTypeidPtr`
DeltaFile
+26-38clang/test/SemaCXX/constant-expression-p2280r4.cpp
+44-7clang/lib/AST/ByteCode/Interp.h
+18-4clang/lib/AST/ByteCode/Interp.cpp
+7-10clang/lib/AST/ByteCode/Pointer.cpp
+11-5clang/lib/AST/ByteCode/Program.cpp
+10-6clang/lib/AST/ByteCode/Compiler.cpp
+116-703 files not shown
+122-739 files

LLVM/project 2377f82llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU SIISelLowering.cpp

[AMDGPU] Add amdgcn.av.(load|store).b128 intrinsics (#191390)

The new `@llvm.amdgcn.av` family of intrinsics have availability and
visibility semantics as described in #191246. Each of them takes a scope
operand that is then translated to target-specific cache policy bits.
This allows the user to control how the side-effects of these loads and
stores are made visible to other threads.

This patch was extracted from #172090.

Co-authored-by: macurtis-amd <macurtis at amd.com>
Assisted-by: Claude Opus 4.6
DeltaFile
+12,365-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
+2,148-0llvm/test/CodeGen/AMDGPU/amdgcn-av-scopes.ll
+1,551-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
+94-0llvm/docs/AMDGPUUsage.rst
+57-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+29-0llvm/test/Verifier/AMDGPU/intrinsics-av.ll
+16,244-06 files not shown
+16,350-012 files

LLVM/project 4cad982clang/include/clang/Analysis/Analyses/LifetimeSafety LifetimeAnnotations.h, clang/lib/Analysis/LifetimeSafety LifetimeAnnotations.cpp FactsGenerator.cpp

[LifetimeSafety] Fix false negative for GSL Owner methods inherited from a non-Owner base
DeltaFile
+44-0clang/test/Sema/warn-lifetime-safety.cpp
+20-8clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
+4-3clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+3-1clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
+1-1clang/lib/Sema/CheckExprLifetime.cpp
+72-135 files

LLVM/project c1b4748llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-bitcast-paired.ll rvp-narrowing-shift-trunc.ll

[RISCV][P-ext] Set BITCAST to Custom for 64-bit packed vectors on RV32 (#198267)

Bitcasts between i64 and v8i8/v4i16/v2i32 used to expand to a stack
roundtrip, and the resulting concat_vectors let DAG combine split
paired-register arithmetic into two single-reg ops (e.g. v8i8 add became
two padd.b instead of one padd.db). The existing Is64BitCast handler in
LowerOperation already treats these as no-ops; this just routes through
it.
DeltaFile
+100-0llvm/test/CodeGen/RISCV/rvp-bitcast-paired.ll
+0-4llvm/test/CodeGen/RISCV/rvp-narrowing-shift-trunc.ll
+1-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+101-43 files

LLVM/project 476b8c8lldb/source/API SBValue.cpp, lldb/source/Plugins/Language/CPlusPlus LibCxxMap.cpp LibCxx.cpp

[lldb] Change ValueObject::Clone to take StringRef (NFC) (#198035)

Make `ValueObject`'s name being a `ConstString` more of an
implementation detail by changing `Clone` and `SetName` take a
`StringRef`.
DeltaFile
+6-6lldb/source/ValueObject/ValueObject.cpp
+5-5lldb/source/Plugins/Language/CPlusPlus/LibCxxMap.cpp
+5-5lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
+2-6lldb/source/ValueObject/ValueObjectCast.cpp
+3-3lldb/source/Plugins/Language/CPlusPlus/MsvcStlSmartPointer.cpp
+3-3lldb/source/API/SBValue.cpp
+24-2818 files not shown
+48-5524 files

LLVM/project 39e36baclang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/test/CodeGenOpenCL builtins-amdgcn-gfx1250-load-monitor.cl

[AMDGPU][Clang] use a ScopeModel when emitting load_monitor [NFC]

Assisted-By: Claude Opus 4.6
DeltaFile
+27-0clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
+16-9clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+1-1clang/test/SemaHIP/incorrect-atomic-scope.hip
+44-103 files

LLVM/project f7c49a9clang/docs ReleaseNotes.rst, clang/lib/Sema SemaDecl.cpp

[Clang] Fixed a crash when instantiating an invalid out-of-line static data member definition in a local class (#196772)

Add check before the function that cause assertion.
Fix #176152, Fix #195416
DeltaFile
+21-0clang/test/SemaTemplate/gh176152.cpp
+3-0clang/lib/Sema/SemaDecl.cpp
+1-1clang/docs/ReleaseNotes.rst
+25-13 files

LLVM/project 91d102fclang/lib/Driver/ToolChains AMDGPU.cpp AMDGPU.h, llvm/include/llvm/TargetParser AMDGPUTargetParser.h TargetParser.h

[NFC][AMDGPU] Remove AMDGPU related code from generic TargetParser.cpp
DeltaFile
+659-0llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+1-643llvm/lib/TargetParser/TargetParser.cpp
+109-0llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+1-90llvm/include/llvm/TargetParser/TargetParser.h
+1-1clang/lib/Driver/ToolChains/AMDGPU.cpp
+1-1clang/lib/Driver/ToolChains/AMDGPU.h
+772-73527 files not shown
+797-76033 files

LLVM/project c48bc2fclang/test/CodeGen link-builtin-bitcode.c, clang/test/CodeGenOpenCL builtins-amdgcn.cl

[AMDGPU] Add three target features msad-insts, mqsad-pk-insts, and mqsad-insts
DeltaFile
+43-7llvm/lib/Target/AMDGPU/AMDGPU.td
+29-0llvm/lib/TargetParser/TargetParser.cpp
+8-10clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+5-7llvm/lib/Target/AMDGPU/VOP3Instructions.td
+11-0llvm/test/MC/AMDGPU/gfx12_5_generic_asm_vop3_err.s
+3-3clang/test/CodeGen/link-builtin-bitcode.c
+99-276 files not shown
+113-3512 files