[AMDGPU] Fix SDWA selection combining (#218512)
Fix miscompile when the combined SDWA instruction computes a different
value than the two instructions it replaces
- Stop merging dst_sel, because two dst_sel cannot be merged into one
- Stop merging equal high src_sel, because the operand already shifted
its field down to the low bits
- Use the operand sext only when the instruction reads the whole dword,
otherwise keep the instruction sext
[KnownFPClass] Remove propagateDenormal and propagateCanonicalizingSrc (#229898)
Removes `propagateDenormal` and `propagateCanonicalizingSrc` since there
are no remaining in-tree uses for these functions, and because there are
no unit tests for these functions.
https://github.com/llvm/llvm-project/pull/225904 removes the last
remaining in-tree uses for
`propagateDenormal` and `propagateCanonicalizingSrc`, which was only
used to handle the special case of `ldexp(x, 0) --> x`.
It may be worth exploring re-adding these functions back in the future,
as they are non-trivial to implement.
Also removed references to `propagateCanonicalizingSrc` in the
documentation for `KnownFPClass::canonicalize`.
[libc] Make entrypoint object linting incremental (#231311)
The entrypoint lint rules used add_custom_target directly, forcing all
lint targets to re-run every time libc-lint was invoked.
Switch to add_custom_command with a stamp file so targets are only
re-linted when their sources or dependencies change.
Assisted-by: Automated tooling, human reviewed.
[DAGCombiner] `visitANY_EXTEND` - fold `(aext (freeze (load x)))` -> `(aext (truncate (freeze (extload x))))` (#218454)
Adds the fold `aext (freeze (load x))` (no multiple uses of `load x`
supported with `freeze`):
1. `freeze (extload x )` when one use of `freeze (load x)`
2. `freeze (extload x )` & when multiple uses of `freeze (load x)` are
there, the `freeze (load x)` is replaced with `truncate (freeze (extload
x ))`
while keeping the existing behaviour where `aext (load x)` is folded to:
1. `extload x` when one use of `load x`
2. `extload x` & when multiple uses of `load x` are there, the `load x`
is replaced with `truncate (extload x )`
[X86] combineX86ShufflesRecursively - bail on any illegal type or if the type is larger than the root (#231505)
MVT now supports various non-pow2 types, so we can't just check for
isSimple() and assert on the sizes anymore - check for legality instead.
Fixes #231453
[SimplifyLibCalls] Fold more FP libcalls to intrinsics. (#227697)
Previously SimplifyLibCalls would only replace a subset of libcalls with
intrinsics.
It looks like a number of intrinsics are currently not handled, but that
looks unintentional unless I am missing something.
This patch adds a number of missing intrinsics to be converted.
This should ensure middle-end passes only have to deal with the
intrinsic versions.
Should mostly be NFC end-to-end:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1505.
PR: https://github.com/llvm/llvm-project/pull/227697
[libc][cmake] Cache compile options from config and arch to speed up configuration. (#225438)
Caching the results of `_get_compile_options_from_config`,
`_get_compile_options_from_arch`, and `_get_common_compile_options`
reduces redundant option computation during the CMake configuration
stage across hundreds of entrypoint objects. Also adds an early return
in `_get_compile_options_from_flags` when no flags are supplied.
[SelectionDAG] Don't unfold a load in the pre-RA schedulers if the unfolded load already exists (#226652)
Fixes #204079
When the pre-RA scheduler has to duplicate a flags-producing instruction
with a folded load (a `CMP32mi` here) to break an EFLAGS interference,
it first tries to unfold it into a plain load and a register operation.
`X86InstrInfo::unfoldMemoryOperand` builds that load with
`getMachineNode`, which CSEs it with a load of the same address that is
already in the DAG, and `TryUnfoldSU` then redirects the chain uses of
the folded node to that existing load. Its chain result already had
users, so one of the redirected `TokenFactor`s became a duplicate of
another one and `ReplaceAllUsesOfValueWith` deleted it, while the
scheduler still had an SUnit pointing at it. The emitter later ran into
the freed node, hence the `<<Deleted Node!>>` in the report.
`ScheduleDAGFast` carries the same code and crashes the same way with
`-pre-RA-sched=fast`.
Both schedulers now give up on unfolding when the unfolded load already
[7 lines not shown]
IR: Add wasm_emscripten_invokecc calling convention keyword
WASM_EmscriptenInvoke had no textual IR spelling and was printed as
cc99. Tests using cc99 as an arbitrary custom convention now use cc1000.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[X86][FP16] Widen v8f16/v16f16 compares to 512 bits without VLX (#231437)
With AVX512FP16 but without AVX512VL, v8f16/v16f16 compares are
scalarized: one VUCOMISH and SETcc per element, then the mask is rebuilt
with VPINSRB/VPMOVZXBQ/VPTESTMQ. This also makes the FP logic conversion
in convertIntLogicToFPLogic a loss for scalar f16 compares, which it
combines as v8f16 compares.
Mark v8f16/v16f16 SETCC as Custom whenever AVX512FP16 is available, and
select the resulting CMPM nodes without VLX by widening them to a
512-bit VCMPPH, as is already done for f32 and f64. Strict compares are
left alone, since widening them could raise exceptions for the upper
elements.
The first commit precommits tests in `avx512fp16-novl.ll` (register,
masked and broadcast forms, and a pair of scalar compares); the existing
`select` test also improves.
Split out of #226222, so that its f16 FP logic conversion no longer
[2 lines not shown]
[AMDGPU][GISel] Match constrained shifts across register bank copies
The constrained shift PatFrags (csh_mask_* wrapped by cshl_/csrl_/csra_)
supply GISelPredicateCode and are imported into the GlobalISel match
table, but they never fired for a divergent shift. AMDGPURegBankLegalize
places a cross-bank COPY in two positions inside the shape they match:
- the mask constant stays in the SGPR bank, so a divergent G_AND reads
it through a COPY and the frag's imm operand is not a G_CONSTANT;
- a uniform G_AND feeding a divergent shift is copied to the VGPR bank,
so the shift's amount operand is not a G_AND.
Either way GIM_CheckOpcode rejects the rule before isUnneededShiftMask
is ever consulted, and the redundant v_and_b32 survives into the output.
Set GIIgnoreCopies so the matcher emits GIM_RecordInsnIgnoreCopies for
those operands. A frag's flags only govern how its own operands are
found, so the first position needs the flag on csh_mask_* while the
second needs it on the node holding the shift; split the masked
[17 lines not shown]
[offload][omp] Load and resolve device binaries through liboffload
Migrate DeviceTy::loadBinary and global/kernel symbol resolution off
GenericPluginTy::load_binary/get_global/get_function onto liboffload's
Program/Symbol API, encapsulated in a new ProgramTy abstraction that wraps
an ol_program_handle_t. Kernel symbol resolution still needs the plugin's
opaque GenericKernelTy* handle for the legacy launch path, obtained via a
temporary __ol_tgt_GetKernelFromSymbol helper rather than new public
liboffload API surface. Removes the now-dead __tgt_device_binary type and
the corresponding GenericPluginTy methods and exports entries.
Attributor: Don't crash on indirect calls in AAInvariantLoadPointer
AAInvariantLoadPointerCallSiteReturned assumed every call has a known
callee, and dereferenced the missing function of an indirect call. This
crashed on most of CTMark with -attributor-enable=full. Nothing is known
about the result of an indirect call, so give up on it.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[lldb] Split register descriptions from ProcessUtility (#222330)
Register-related code has cluttered up the `Process/Utility` and the
naming `RegisterContext/RegisterInfo` is also inconsistent across
different files. Create a new lldb library `lldbRegisterSupport` to
isolate classes derived from `RegisterInfoInterface`. The classes named
`RegisterContext*` that are derived from `RegisterInfoInterface` will be
renamed to `RegisterInfo*` in following commits.
Move some x86 register descriptions from `RegisterContextPOSIX_x86` to
`RegisterContext_x86` since they are independent from the POSIX
interface.
Assisted-by: GPT
[libc++] Assume separate storage in vector (#225325)
The compiler doesn't know in general that `this` and `this->__begin_`
don't alias. Since we do know that `operator new`'s returned pointers
don't alias anything else we can at least inform the compiler that they
don't alias if we have a `std::allocator`.
Fixes #181249
lldb: Wait for the private state thread before destroying a process
StopForDestroyOrDetach only halted the process if the public or private
state was running. After an SBProcess::Continue from another thread, the
public state can still say stopped, and the private state says stopped as
soon as the next stop arrives, while the private state thread is still
handling it and may decide to resume. DestroyImpl then discarded thread
plans concurrently with it, which hit the "Can't pop the base thread
plan" assert.
Let the private state thread finish its pending events first, and use
the state it last handled instead of the private state.
This fixes the flaky test_sb_api_listener_resume, so re-enable it on
Linux. Under heavy load it failed 10 of 1344 runs before and 0 of 4416
after. Keep it disabled on Windows until verified there (#231113).
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[libc++] Fix search_n with an invalid count (#223747)
search_n would incorrectly compute pointer offsets based on the
user-provided count, which wasn't checked for being negative. This patch
adds checks for negativity to prevent computing and accessing
potentially out-of-bounds pointers.
[InstCombine] Move type evaluation depth limit to TableGen options (#231408)
Follow up to #217879 per review. Move
instcombine-max-type-eval-depth to TableGen options.
[KnownFPClass] Refine `KnownFPClass::bitcast` deductions for `x86_fp80` (#224072)
Improves `KnownFPClass` deductions `i80` to `x86_fp80` bitcasts.
Non-canonical NaN's are treated as `fcSNan` if the quiet bit is known
clear, and `fcQNan` if the quiet bit is known set.
AI Disclosure:
I used ChatGPT Codex (5.6 sol and Astra-6) and Claude (Sonnet/Opus 5) to
help generate the tests and to review the code.
[libc++] Suppress unsigned-integer-overflow warning in <charconv> (#225801)
Invoking __complement with 0 as parameter triggers the unsigned integer
overflow UBSan.
[lldb][minidump][test] Disable test_size_of_image... when remote testing (#231498)
The test assumes that the program can load the shared library, which it
cannot unless we copy it to the remote.
The shared library is also built outside of the usual build process, so
it's using the host compiler and possibly other host things.
[X86] Don't form (FM)ADDSUB for bf16, or for narrow f16 vectors without VLX (#231445)
The shuffle combines that form (FM)ADDSUB only check for FMA, and only
exclude f16 from ADDSUB. There are no bf16 (FM)ADDSUB instructions, and
the AVX512-FP16 FMADDSUB needs VLX for 128/256-bit vectors. So an
add/sub shuffle of `<8 x half>` with `+avx512fp16` but no VLX, or of `<8
x bfloat>` (from FSUB/FADD or from FMA/FMSUB) with `+avx10.2`, fails to
select:
```
LLVM ERROR: Cannot select: t16: v8f16 = X86ISD::FMADDSUB t2, t4, t6
LLVM ERROR: Cannot select: t20: v8bf16 = X86ISD::FMADDSUB t7, t8, t9
```
Check the element type in both combines: reject bf16, and accept f16
only where f16 FMA is legal for the vector type (512-bit with
AVX512-FP16, 128/256-bit also with VLX). The new tests cover
128/256/512-bit f16 with and without VLX, and bf16 with and without
`contract` and from FMAs; the f16 no-VLX and bf16 RUN lines crash
[6 lines not shown]
[flang] Fix null pointer dereference in OUT_OF_RANGE folding (#224270)
Folding `OUT_OF_RANGE` could crash when the default logical kind is
8:`CompareUnsigned` assumed intrinsic comparisons always yield
`LogicalResult`(LOGICAL(4)). Unwrap as `SomeLogical` and convert to
`LogicalResult`.
Add a `fold-out_of_range.f90` RUN line with `-fdefault-integer-8` and
a`test_kind` check.
Fixes #212392
