LLVM/project 3c0e69ecompiler-rt/cmake/Modules CompilerRTUtils.cmake

[compiler-rt] Fix undefined AMDGPU variable not set for builtins (#202733)

Summary:
compiler-rt is weird and has multiple config files, make sure this is
set for both libs and builtins.
DeltaFile
+6-0compiler-rt/cmake/Modules/CompilerRTUtils.cmake
+6-01 files

LLVM/project 2aaaff7flang/lib/Semantics check-omp-structure.cpp openmp-utils.cpp, flang/test/Semantics/OpenMP assumed-size-array-dsa.f90 cray-pointer-usage.f90

[flang][OpenMP] Move assumed-size array check to list item verification (#201385)

The presence of whole assumed-size arrays will now be diagnosed in a
single location, together with the verification of list item kinds.
DeltaFile
+19-17flang/lib/Semantics/check-omp-structure.cpp
+4-4flang/test/Semantics/OpenMP/assumed-size-array-dsa.f90
+3-3flang/test/Semantics/OpenMP/cray-pointer-usage.f90
+3-3flang/test/Semantics/OpenMP/reduction-assumed.f90
+4-1flang/lib/Semantics/openmp-utils.cpp
+0-1flang/lib/Semantics/check-omp-loop.cpp
+33-291 files not shown
+33-307 files

LLVM/project a9141a0llvm/lib/Transforms/Scalar LoopInterchange.cpp

address review
DeltaFile
+52-52llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+52-521 files

LLVM/project 7e526f7mlir/lib/Dialect/Affine/Transforms SuperVectorize.cpp, mlir/test/Dialect/Affine/SuperVectorize vectorize_2d_inbounds.mlir vectorize_affine_apply.mlir

[mlir][affine] emit `in_bounds` on `transfer_read`/`write` when statically provable in `affine-super-vectorize` (#201180)

This patch fixes an issue reported on the MLIR Discourse ([May
2026](https://discourse.llvm.org/t/mlir-affine-affine-super-vectorize-does-not-set-in-bounds-on-transfer-ops-for-statically-divisible-shapes/90785/3)),
that I also came across during a study I reported in [my blog
post](https://federicobruzzone.github.io/posts/mlir-study.html).

`affine-super-vectorize` always creates `vector.transfer_read` and
`vector.transfer_write` without an `in_bounds` attribute, even when it
is statically provable that every access stays within bounds. This
forces downstream lowering to unconditionally emit
`llvm.intr.masked.load`/`llvm.intr.masked.store`: masked intrinsics that
carry $\sim3\times$ overhead on AArch64/NEON and prevent
auto-vectorization (see the MLIR Discourse).

## Root cause

`vectorizeAffineLoad` and `vectorizeAffineStore` in `SuperVectorize.cpp`
forwarded neither the `in_bounds` mask nor any analysis of it when

    [55 lines not shown]
DeltaFile
+52-0mlir/test/Dialect/Affine/SuperVectorize/vectorize_2d_inbounds.mlir
+30-2mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
+6-6mlir/test/Dialect/Affine/SuperVectorize/vectorize_affine_apply.mlir
+4-4mlir/test/Dialect/Affine/SuperVectorize/vectorize_1d.mlir
+3-3mlir/test/Dialect/Affine/SuperVectorize/vectorize_reduction.mlir
+2-2mlir/test/Dialect/Affine/SuperVectorize/vectorize_2d.mlir
+97-171 files not shown
+98-187 files

LLVM/project 13a95bfllvm/utils/gn/secondary/bolt/unittests/Profile BUILD.gn, llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port commits (#202730)

1ef2f3b98b13
2426b855f303
2bd098b819c1
69215c5e4f03
88bd366041fd
a08dce6881f6
fc9bf89cfd9a
DeltaFile
+1-1llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+1-1llvm/utils/gn/secondary/bolt/unittests/Profile/BUILD.gn
+1-0llvm/utils/gn/secondary/lldb/source/Target/BUILD.gn
+0-1llvm/utils/gn/secondary/llvm/lib/Frontend/Offloading/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
+5-33 files not shown
+7-49 files

LLVM/project 150717aclang/test/CodeGen/LoongArch/lasx builtin-alias.c builtin.c, llvm/test/CodeGen/AArch64 bf16-v8-instructions.ll bf16-v4-instructions.ll

Merge branch 'main' into users/kparzysz/s05-assumed-size-arrays
DeltaFile
+8,895-3,632llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
+3,563-3,543llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+6,598-111llvm/test/CodeGen/X86/clmul-vector.ll
+3,951-1,914llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
+2,749-2,749clang/test/CodeGen/LoongArch/lasx/builtin-alias.c
+2,745-2,745clang/test/CodeGen/LoongArch/lasx/builtin.c
+28,501-14,6943,604 files not shown
+245,166-95,9813,610 files

LLVM/project 9c3de27flang/lib/Semantics check-omp-structure.cpp openmp-utils.cpp, flang/test/Semantics/OpenMP declare-target01.f90 threadprivate01.f90

[flang][OpenMP] Move check for substring to semantic checks (#201384)

Move it to CheckVarIsNotPartOfAnotherVar, which is also refactored a
bit.
DeltaFile
+16-16flang/test/Semantics/OpenMP/declare-target01.f90
+18-14flang/lib/Semantics/check-omp-structure.cpp
+20-0flang/lib/Semantics/openmp-utils.cpp
+4-4flang/test/Semantics/OpenMP/threadprivate01.f90
+4-4flang/test/Semantics/OpenMP/parallel-sections01.f90
+0-8flang/lib/Semantics/resolve-directives.cpp
+62-4616 files not shown
+86-6722 files

LLVM/project 36c3a04llvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange complex-inner-latch-condition.ll

[LoopInterchange] Bail out if inner latch branch cond is not CmpInst
DeltaFile
+8-23llvm/test/Transforms/LoopInterchange/complex-inner-latch-condition.ll
+2-0llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+10-232 files

LLVM/project 0398a93clang/include/clang/DependencyScanning DependencyScanningFilesystem.h, clang/lib/CIR/CodeGen CIRGenFunction.cpp

Merge branch 'main' into users/kparzysz/s04-substring-check
DeltaFile
+294-0llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
+140-143clang/lib/DependencyScanning/DependencyScanningFilesystem.cpp
+72-143clang/include/clang/DependencyScanning/DependencyScanningFilesystem.h
+211-0clang/unittests/DependencyScanning/DependencyScanningFilesystemTest.cpp
+103-92clang/test/Driver/hip-phases.hip
+138-51clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+958-429176 files not shown
+2,779-1,306182 files

LLVM/project 6554622clang/lib/Driver Driver.cpp, clang/test/Driver hip-phases.hip hip-rdc-device-only.hip

Revert "[Clang] Set default LTO mode for AMDGCN/SPIR-V targets to full" (#202714)

Reverts llvm/llvm-project#201457

Caused flang lit test failures, e.g.
https://lab.llvm.org/buildbot/#/builders/80/builds/22848
DeltaFile
+103-92clang/test/Driver/hip-phases.hip
+96-21clang/lib/Driver/Driver.cpp
+20-20clang/test/Driver/hip-rdc-device-only.hip
+12-13clang/test/Driver/hip-binding.hip
+9-10clang/test/Driver/hip-spirv-backend-phases.c
+3-15clang/test/Driver/hip-device-compile.hip
+243-17131 files not shown
+328-27937 files

LLVM/project 473fc95clang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

[LifetimeSafety] Diagnose UAF for aligned and nothrow new expressions (#202286)

Previously LifetimeSafety skips issuing a heap allocation loan for
replaceable global allocation functions such as aligned and nothrow
operator new. This commit fixes that by modeling those forms as heap
allocations.

Closes https://github.com/llvm/llvm-project/issues/196208
DeltaFile
+57-1clang/test/Sema/warn-lifetime-safety.cpp
+15-7clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+6-0clang/test/Sema/Inputs/lifetime-analysis.h
+1-1clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+79-94 files

LLVM/project b891954clang/lib/Sema SemaAPINotes.cpp

[APINotes] Early return when no apinotes files are loaded

When no APINotes readers are available, let's not spend time trying to determine the current decl's context or do other redundant work.

Resolves https://github.com/llvm/llvm-project/issues/202214
DeltaFile
+14-11clang/lib/Sema/SemaAPINotes.cpp
+14-111 files

LLVM/project 5fd8036llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp SPIRVTypeInst.cpp, llvm/test/CodeGen/SPIRV/transcoding store-atomic-ptr.ll atomic-load-store-unsupported.ll

[SPIRV] Let atomic store store pointers (#201251)

SPIRV atomic store permits only integer or floats as per SPIRV spec.
When compiling libc there several places in the code where pointers are
atomically stored causing compilation to break. It can be fixed by using
casting in the libc code but in order to keep the libc code clean it is
preferrable to do it in SPIRV backend. This change will cast pointer
parameters to integers of appropriate size and generate atomic store
instruction that uses integers per SPIRV spec.
DeltaFile
+50-5llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+31-0llvm/test/CodeGen/SPIRV/transcoding/store-atomic-ptr.ll
+9-0llvm/test/CodeGen/SPIRV/transcoding/atomic-load-store-unsupported.ll
+4-0llvm/lib/Target/SPIRV/SPIRVTypeInst.cpp
+2-0llvm/lib/Target/SPIRV/SPIRVTypeInst.h
+96-55 files

LLVM/project 5a62b2allvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange complex-inner-latch-condition.ll

[LoopInterchange] Bail out if inner latch branch cond is not CmpInst
DeltaFile
+48-46llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+8-23llvm/test/Transforms/LoopInterchange/complex-inner-latch-condition.ll
+56-692 files

LLVM/project 146abedllvm/lib/Target/AArch64/MCTargetDesc AArch64InstPrinter.cpp

[AArch64][NFC] Avoid relocations in LdStNInstrDesc (#202025)

These are small strings, so instead of an 8 byte string pointer that
needs a relocation store the strings directly inline. This avoids 320
relocations in libLLVM.so.
DeltaFile
+6-6llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+6-61 files

LLVM/project db58421llvm/test/Transforms/LoopInterchange complex-inner-latch-condition.ll

[LoopInterchange] Add test for legality check misses latch cond (NFC)
DeltaFile
+78-0llvm/test/Transforms/LoopInterchange/complex-inner-latch-condition.ll
+78-01 files

LLVM/project 14b2935compiler-rt CMakeLists.txt, compiler-rt/cmake base-config-ix.cmake

compiler-rt: Consolidate regex checks for amdgpu targets (#202281)
DeltaFile
+7-1compiler-rt/cmake/base-config-ix.cmake
+3-3compiler-rt/CMakeLists.txt
+2-2compiler-rt/lib/profile/CMakeLists.txt
+2-2compiler-rt/lib/builtins/CMakeLists.txt
+1-1compiler-rt/test/ubsan_minimal/CMakeLists.txt
+1-1compiler-rt/cmake/Modules/CompilerRTUtils.cmake
+16-102 files not shown
+18-128 files

LLVM/project 335641ellvm/test/MC/AMDGPU gfx11_asm_vop3_dpp16.s, llvm/test/MC/Disassembler/AMDGPU gfx11_dasm_vop3_dpp16.txt gfx11_dasm_vop3_dpp16-fake16.txt

[AMDGPU][NFC] Templatise and roundtrip gfx11_asm_vop3_dpp16.s

I tried to make sure this covers all important cases from asm/disasm
tests here upstream and the true16 branch downstream.

This will resolve ~4k lines of differences vs the true16 branch.
DeltaFile
+8,554-3,250llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+0-6,200llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+4,380-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16-fake16.txt
+12,934-9,4503 files

LLVM/project 5f689cdlldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime AppleObjCTrampolineHandler.cpp AppleObjCTrampolineHandler.h

Remove support for the obsolete "_fixup" and "_fixedup" modes of objc_msgSend (#202449)

This was one of a long series of tricks for accelerating ObjC dispatch,
but this one hasn't been used for many years now, and the ObjC
maintainers have no intention of reviving this notion.
DeltaFile
+14-78lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.cpp
+0-3lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.h
+14-812 files

LLVM/project 93bc18flld/MachO ConcatOutputSection.cpp ConcatOutputSection.h, lld/test/MachO arm64-thunk-stubs.s arm64-thunk-stubs-multi-text.s

[lld][macho] Fix thunks with multiple text sections (#199747)

When there are multiple `__text` sections, LLD might not generate thunks
to stubs sections when they are required, leading to relocation errors.
```
ld64.lld: error: a.o:(symbol _foo+0x0): relocation BRANCH26 is out of range: 134217744 is not in [-134217728, 134217727]; references _extern_sym
```

Create `TextOutputSection::estimateStubsEndVA()` to correctly estimate
the end VA of the last stubs section so we can tell when branches to
stub symbols will be in range.

Technically this could cause lld to generate more thunks in some cases.
If a binary requires thunks (the `__TEXT` segment is >128MiB) and has
multiple `__text` sections like `__text_cold` or `__lcxx_override`, then
all branches to stub symbols will require thunks. Without this change we
could get the relocation errors above. We might be able to workaround
the problem by placing the `__text` section last.

Fixes https://github.com/llvm/llvm-project/issues/195387.
DeltaFile
+75-0lld/test/MachO/arm64-thunk-stubs.s
+44-11lld/MachO/ConcatOutputSection.cpp
+50-0lld/test/MachO/arm64-thunk-stubs-multi-text.s
+0-18lld/test/MachO/arm64-thunks.s
+5-1lld/MachO/ConcatOutputSection.h
+174-305 files

LLVM/project 93c95d3clang/test/OffloadTools/clang-linker-wrapper linker-wrapper.c linker-wrapper-hip-no-rdc.c, clang/tools/clang-linker-wrapper ClangLinkerWrapper.cpp

[HIP] Fix `-flto` overriding `--no-lto` not that it is default (#202699)

Summary:
The previous changes to LTO made the flto flag passed by default which
overrode the hack we did to ervert to the old non-LTO pipline. This is a
temporary hack so I'm hacking it even further to fix it.
DeltaFile
+6-11clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
+7-7clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
+3-3clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-hip-no-rdc.c
+16-213 files

LLVM/project c1003f2clang/lib/Driver Driver.cpp, clang/test/Driver hip-phases.hip hip-rdc-device-only.hip

Revert "[Clang] Set default LTO mode for AMDGCN/SPIR-V targets to full (#201457)"

This reverts commit 859ee9d83ef227848a98c5948f887574f5e7420c.
DeltaFile
+103-92clang/test/Driver/hip-phases.hip
+96-21clang/lib/Driver/Driver.cpp
+20-20clang/test/Driver/hip-rdc-device-only.hip
+12-13clang/test/Driver/hip-binding.hip
+9-10clang/test/Driver/hip-spirv-backend-phases.c
+3-15clang/test/Driver/hip-device-compile.hip
+243-17131 files not shown
+328-27937 files

LLVM/project b7cdfe4.github/workflows subscriber.yml issue-subscriber.yml

workflows: Consolidate pr-subscriber and issue-subscriber (#200503)

This consolidates duplicate logic from the pr-subscriber and
issue-subscriber workflows into a single workflow.
DeltaFile
+74-0.github/workflows/subscriber.yml
+0-52.github/workflows/issue-subscriber.yml
+0-52.github/workflows/pr-subscriber.yml
+74-1043 files

LLVM/project 95bd483compiler-rt/lib/asan CMakeLists.txt

[asan] Make exceptions for asan_new_delete.cpp conditional (#202436)

Introduce the COMPILER_RT_ASAN_ENABLE_EXCEPTIONS CMake
option to control whether the ASan C++ runtime
(asan_new_delete.cpp) is compiled with exception
support.

This fixes build failures on platforms with noexcept
toolchains (like Fuchsia's noexcept variant) where
ASan was compiled with exceptions but linked against a
noexcept libc++abi, resulting in undefined symbol
errors for __cxa_begin_catch and __gxx_personality_v0.

The option defaults to ON to preserve the behavior of
#200719, but automatically defaults to OFF if
LIBCXX_ENABLE_EXCEPTIONS or LIBCXXABI_ENABLE_EXCEPTIONS
is set to OFF in the same runtimes build.
DeltaFile
+20-5compiler-rt/lib/asan/CMakeLists.txt
+20-51 files

LLVM/project 26c5508llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 recalc-copyable-operand-deps-non-scheduled-node.ll

[SLP] Recompute copyable operand deps of bundled members in scheduleBlock

An instruction modeled as a copyable element in one node may be used directly
by another node registered only after its deps were last computed. The
deferred recomputation is consumed before that node joins the tree, so the
direct def-use edge is missed and the count stays too low, tripping the
unscheduled-deps assertion. Clear and recompute such bundled members against
the full tree in scheduleBlock.

Fixes #202463

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/202712
DeltaFile
+49-0llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-non-scheduled-node.ll
+14-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+63-02 files

LLVM/project 5f864f9llvm/tools/llvm-exegesis/lib Assembler.h

[NFC][llvm-exegesis] Disable CFI-icall for JIT-executed function (#202472) (#202682)

Reland of #202472 reverted with #202571.

Here we are going to use LLVM_NO_SANITIZE.
DeltaFile
+3-1llvm/tools/llvm-exegesis/lib/Assembler.h
+3-11 files

LLVM/project de42f4f.github/workflows release-documentation.yml release-tasks.yml, llvm/utils/release build-docs.sh

[docs] Release man pages (#201376)

This adds the possibility to generate man pages from the `llvm/utils/release/build-docs.sh` script. Furthermore the `release-documentation` github workflow was modified to build and upload the man pages.

This was done to prevent dependency problems when myst-parser will become a hard dependency to build the documentation in LLVM. See https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840/26?u=kwk

Additionally the `build-docs.sh` script now determines the release from the source directory if no release was given. Otherwise the generated tarballs would be missing the release entirely. To make it clear that something was generated from any git directory, a short git revision will be attached to the release (e.g. `23.0.0-gc823de88d51f58`).

The script generates a total of 67 man pages for the 22.1.7 release (see below).

`lld` has their own man page hardcoded in [`lld/docs/ld.lld.1`](https://github.com/llvm/llvm-project/blob/main/lld/docs/ld.lld.1). It gets packaged manually because of a missing cmake target. To get all projects install their man pages in the same directory to package up, we have to run the install targets rather than just the build targets (e.g. `install-docs-clang-man` instead of just `docs-clang-man`).

Here's what's in the tarball for the `22.1.7` release when you run the script from this change:

```console
$ rm -rf llvm_man_pages-* docs-build llvm-project
$ ./llvm/utils/release/build-docs.sh  -no-sphinx  -no-doxygen -release 22.1.7
```


    [70 lines not shown]
DeltaFile
+59-4.github/workflows/release-documentation.yml
+47-7llvm/utils/release/build-docs.sh
+6-1.github/workflows/release-tasks.yml
+1-1.github/workflows/release-doxygen.yml
+113-134 files

LLVM/project f4ee842compiler-rt CMakeLists.txt

compiler-rt: Suppress -g error for gpu builds (#202230)
DeltaFile
+1-1compiler-rt/CMakeLists.txt
+1-11 files

LLVM/project c0e8b29clang/lib/CIR/CodeGen CIRGenFunction.cpp

[CIR][NFC] Align emitLValue with classic codegen (#202448)

This reorganizes the `CIRGenFunction::emitLValue` function to align it
with `CodeGenFunction::EmitLValueHelper` in classic codegen. Previously,
the default handler for the switch statement reported an NYI diagnostic
for any l-value class that wasn't handled in the function. This change
adds case handlers for every class that is handled by classic codegen,
giving each their own NYI diagnostic.

The purpose of this is to more explicitly show what is missing and to
make it easier to port the classic codegen implementation to CIR.

The existing CIR handling is not changed, just the order.
DeltaFile
+138-51clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+138-511 files

LLVM/project 48a4b66clang/docs ReleaseNotes.rst, clang/lib/AST ExprClassification.cpp

[clang] Classify binary op value kinds use ClassifyExprValueKind when it's type-dependent (#202696)

The crash is from an internal inconsistency in Clang’s expression
classification.

Expr::ClassifyImpl computes a classification like CL_LValue or
CL_PRValue, then asserts that this agrees with the AST node’s own value
category:

- clang/lib/AST/ExprClassification.cpp:37
- CL_LValue must satisfy E->isLValue()
- CL_PRValue must satisfy E->isPRValue()

Fixes https://github.com/llvm/llvm-project/issues/202693.

Signed-off-by: yronglin <yronglin777 at gmail.com>
DeltaFile
+39-0clang/test/AST/dependent-assignment-classification.cpp
+5-4clang/lib/AST/ExprClassification.cpp
+2-0clang/docs/ReleaseNotes.rst
+46-43 files