TableGen: Add none_of for negating features in AssemblerPredicate
AssemblerPredicates are currently specified with "all_of", "any_of",
and then "not" as the odd one out. The use of these operators relies
on the "forward declaration" of not, which is not a language feature
tablegen has. This "not" operator isn't actually the same empty record
as all_of/any_of, and is in fact usually supplied by the PatFrag to
match xor -1 in from TargetSelectionDAG.td. The predicate parser just
special cases the name.
Introduce none_of to go with the other predicate operators, which is
more consistent and expressive. This will help cleanup some tablegen
include dependencies, like avoiding redeclaring not in every target's
TargetParser generation.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Clang ssaf driver 4 (#231999)
Add a tool that runs a source transformation over a project as it builds
and presents the result. It knows which summaries and which
whole-program analysis each transformation needs, so a user names only
the transformation and the build command; cpp-bounded-buffers is the
first. It drives projects built with make through
clang-ssaf-orchestrator-make.
The driver writes the link unit's source edits as a patch, and prints
the transformation report the way a compiler prints diagnostics as well
as writing it as SARIF. A merge resolves only the conflicts among its
own inputs, so an edit that overlaps a reported conflict is left out of
the patch. With --apply the driver also applies the edits with
clang-apply-replacements, which it looks for before the build, and
checks that the sources end up as the patch shows them.
This is a generalization of a tool that we
proposed earlier - clang-reforge. We want to build a general-purpose
analysis and transformation driver decoupled from the specifics.
[libc++] Remove redundant `_LIBCPP_HIDE_FROM_ABI` from detail headers a-c (#201722)
This is the first bulk-removal patch of `_LIBCPP_HIDE_FROM_ABI`. While
this is something we could do over time, actively removing the redundant
annotations significanly improves readability, and QoI.
This happens in a few patches to keep the size somewhat manageable.
[LifetimeSafety] Propagate origins through BaseToDerived casts (#231896)
In addition to what the title says, I added a few tests demonstrating
the pre-existing origin shape mismatch detection and borrow drop
behavior.
Assissted-By: claude
[AMDGPU] Materialize WMMA SGPR scales to VGPRs before scheduling
v_wmma_scale scale operands accept an SGPR or a VGPR. On GFX12,
depctr_va_ssrc is a 1-deep counter, so each VALU instruction that reads
an SGPR scale takes the only scalar-source slot. A run of WMMA ops that
all read SGPR scales therefore serializes. One cross-bank copy pays for
that slot once; later WMMA ops then read a VGPR and no longer contend
for va_ssrc.
SIMaterializeWMMAScale runs at the end of the machine SSA optimizations,
after SIShrinkInstructions and before scheduling. It is skipped at -O0
and on targets older than GFX12. GFX1250 is included: the separate VALU
read-after-write hazard no longer applies there, but the dependency
counter still does.
The pass walks every WMMA that has scale_src0 and records virtual SGPR
uses of scale_src0 and scale_src1, grouped by register. Physical
registers and subregister uses are left alone. For each SGPR it inserts
a COPY into a low aligned VGPR (the lo256 class matching the scale's
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[CIR][OpenMP] Add initial support for distribute
This patch adds initial support for the OpenMP 'distribute' directive. Basic
code generation for the standalone and combined cases is introduced. Support
for clauses will be added in the future. The composite 'teams distribute
parallel for' form will be added in a subsequent patch.
Assisted-by: Cursor / Claude Sonnet 5 High
[SLP][TTI][RISCV] Update BuildVectorUseOp to support intrinsics (#231400)
Allows TTI::getBuildVectorContextHint() to in turn handle splats feeding intrinsics.
Addresses #231116.
AI Usage: Assisted by Codex
[Support][IR] Set library options per LLVMContext (#231407)
`OptionsStruct<..., perContext = true>` lets each LLVMContext hold its
own values of a library's options, so that two contexts in one process
can compile with different values. The static member `Global` becomes
private, and readers call `Ctx.getLibraryOptions().get<T>()`, which
returns the context's copy, (temporary fallback) or `Global` if it has
none. InstCombine and Vectorize are the first such libraries.
SandboxVectorizerPass builds its pipeline from the options of the first
context it runs in.
The new cl::parseCommandLineOptions sets per-context libraries' options
in the given cl::LibraryOptionsContext instead of Global. opt parses
into its LLVMContext; clang -cc1 parses -mllvm into its CompilerInstance
and assigns the arguments to the code generation LLVMContext at each
input. An embedder calls assign({"-x=v"}), which dispatches through the
cl:: registry.
https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877
LLM-aided
[Clang] [CUDA] Fix calling convention for forward-declared kernels (#231628)
The calling convention was not being set properly, leading to linker
errors in nvlink. We already set the calling convention this way for
AMDGPU, so do the same for NVPTX.
Fixes #118212.
Assisted-by: Codex
Select map and motion iterators from source references
Map and motion locators chose their iterator ranges from the folded
designator, so a reference such as a(0*i + 1) lost its iterator and was
mapped unconditionally, even when the range was empty.
Build Map, To and From locator lists with the source iterator references
already used for AFFINITY and DEPEND, and select each locator's ranges from
them. Locators without an iterator modifier are unchanged.
[NVPTX] Use default legalizer for truncating store that have memory VT == i1 (#231592)
NVPTXTargetLowering set action to "Expand" to legalize i1 MemVT.
However, custom lowering intercept this case and to do wrong lowering
which triggers Tmp3.getValueType() == MVT::i1 assertion.
Fixes: https://github.com/llvm/llvm-project/issues/197699
Signed-off-by: ZakyHermawan <zaky.hermawan9615 at gmail.com>
Co-authored-by: Justin Fargnoli <jfargnoli at nvidia.com>
Attributor: Deduce noundef returns if poison-generating attributes hold
Instead of giving up on noundef for returns with poison-generating
attributes, check that the attributes are assumed to hold for all
returned values. This uses the Attributor's own deductions for the
returned values (AANonNull, AAAlign, AAValueConstantRange and
AANoFPClass), so e.g. a range only known from a callee is enough.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Attributor: Don't infer noundef returns with poison-generating attributes
Returning a value that violates an existing return attribute results
in poison. AANoUndef did not account for this and could mark such
returns noundef. Give up on returns with poison-generating attributes.
This loses 2 of 3 noundef returns that would have been proven over
CTMark with -attributor-enable=full, and no call site attributes. A
follow-up instead checks that the attributes hold for the returned
values, using the Attributor's own deductions for them.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[VectorCombine] Add instructions created by IRBuilder into Worklist automatically (#230618)
Previously, users have to add newly generated instructions into Worklist
_manually_. Which can be quite easy to forget and leave potential
optimization opportunities on the table. Especially that, unlike
InstCombine, VectorCombine runs only like 2 times in the pipeline.
This patch uses a custom IRBuilder inserter to add newly generated
instructions automatically into VectorCombine's Worklist, just like what
InstCombine is doing. The patch also fixes several places to use
`VectorCombine::Builder` rather than a local IRBuilder instance.
[lldb] Replace const char * with StringRef in ValueObject::GetSyntheticExpressionPathChild (#231711)
I'm doing some refactoring and having this go in first makes some later
stuff easier to review.
[mlir][OpenMP] Model recursive memory effects of omp.masked (#230493)
Change the test-side-effects test pass to emit recursive side effects.
Update side-effect tests.
Directly test for recursive memory effects.
AI-Assisted-by: Codex (testing)
---------
Co-authored-by: Jamie.Rowlinson-Patel at arm.com <jamrow01 at ip-10-252-16-38.eu-west-1.compute.internal>
[AMDGPU] Support the RF and m inline asm constraints (#195123)
This patch supports the RF inline asm constraint for memory operands in
the flat address space as well as the generic 'm' constraint.
[CoroSplit] Keep scalable allocas on the stack when no use crosses a suspend
Lifetime markers can conservatively span a suspend point even when no use of
the alloca does (e.g. a local whose C++ scope covers a co_await). For scalable
allocas this forces them onto the frame, which cannot hold them, and CoroSplit
aborts with "Coroutines cannot handle non static or vscale allocas yet". If
the address does not escape and no non-lifetime use crosses a suspend point,
keep the alloca on the stack instead.
Assisted-By: Claude
[CoroSplit] Keep scalable allocas on the stack when no use crosses a suspend
Lifetime markers can conservatively span a suspend point even when no use of
the alloca does (e.g. a local whose C++ scope covers a co_await). For scalable
allocas this forces them onto the frame, which cannot hold them, and CoroSplit
aborts with "Coroutines cannot handle non static or vscale allocas yet". If
the address does not escape and no non-lifetime use crosses a suspend point,
keep the alloca on the stack instead.
Assisted-By: Claude
[libc] Add bare-metal Hexagon port (#217528)
Add support for llvm-libc on Hexagon bare-metal targets.
Recognize the hexagon architecture in CMake.
Add the Hexagon bare-metal config: config.json, entrypoints.txt,
headers.txt. Add Hexagon startup code (crt1) with semihosting trap
handling. Add a Hexagon FEnvImpl and select it in FEnvImpl.h; define
fenv_t for Hexagon. Add bare-metal signal macros and wire the bare-metal
include path into signal-macros.h.
memory_size: detect signed addition overflow with a builtin instead of
relying on undefined behavior.
---------
Signed-off-by: Kushal Pal <kushpal at qti.qualcomm.com>
RuntimeLibcalls: Define vector math libcall signatures in tablegen
Give vector math libcalls a signature in tablegen. The vector modf,
sincos and sincospi types now come from the generated signature instead of
being manually constructed, though the attributes are still manually applied.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
RuntimeLibcalls: Define vector math libcall signatures in tablegen
Add vector FuncArgTypes and replace some of the manual signature
construction in getFunctionTy. Add masked and unmasked variants for
the scalable vector cases, with mapping functions between the versions.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Add heuristic to set CarriedLatencies (#224057)
After
https://github.com/llvm/llvm-project/commit/8723e4a1bc0b6078e35c17532952f79fb8480f53
users have some control to defer scheduling instructions which depend on
loads from predecessor blocks. This PR adds a simple heuristic to
control setting the Fence mode, which has shown to be the most useful in
practice.
We would like to defer scheduling the ATOMIC_FENCE, if 1. there is a
corresponding load/store in flight, and 2. there have not been enough
cycles for that instruction to reasonably finish. Unfortunately, since
we are reasoning about loads/stores in predecessor blocks, we can not
reliably know where these will in the final schedule. However, we can
inspect the dependency structure to identify cases where these
instructions may be pushed back.
This heuristic identifies predecessor blocks in which ds_loads must be
scheduled after all wmma instructions, as this dependency structure
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