LLVM/project 5918619llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 logical-op-with-not.ll atomicrmw-O0.ll

[AArch64][CodeGen] match (or x (not y)) to generate mov+orn (#191145)

Fixes: #100045

Adds a tablegen pattern that matches (or x (not y)) and generates a
mov+orn instead of the original mvn+orr.

The number of instructions still stay the same but mov+orn can be
considered better than mvn+orr for two reasons:
1. Symmetry: For the same input with an 'and' instead of 'or', mov+bic
is generated.
2. Optimzation through register rename: If mov is immediate (for
example, 'mov x1, #0x4'), it can be retired early by the register
renamer and never issued for execution.

This patch was reverted as I wanted to change my email associated with
the patch.

Original patch: #190769

    [2 lines not shown]
DeltaFile
+32-8llvm/test/CodeGen/AArch64/logical-op-with-not.ll
+12-12llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
+4-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+2-2llvm/test/CodeGen/AArch64/arm64-atomic.ll
+50-224 files

LLVM/project 13f1492llvm/include/llvm/ADT GenericUniformityImpl.h, llvm/include/llvm/Analysis UniformityAnalysis.h

refactor: update variable names in uniformity analysis
DeltaFile
+35-35llvm/include/llvm/ADT/GenericUniformityImpl.h
+36-33llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+19-19llvm/lib/Analysis/UniformityAnalysis.cpp
+4-4llvm/include/llvm/Analysis/UniformityAnalysis.h
+4-3llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
+98-945 files

LLVM/project ff388adllvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[LV] NFCI: Create VPExpressions in transformToPartialReductions.

With this change, all logic to generate partial reductions and
recognising them as VPExpressions is contained in
`transformToPartialReductions`, without the need for a second
transform pass.
The PR intends to be a non-functional change.
DeltaFile
+54-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+54-141 files

LLVM/project b9c8733clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 v8.2a-fp16-intrinsics.c

[CIR][Aarch64] upstream scalar & vector intrinsics (FP16) (#190310)

This PR upstreams the following fp16 intrinsics as part of #185382:

- vaddh_f16, 
- vsubh_f16, 
- vmulh_f16, 
- vdivh_f16

This is my first PR to LLVM, so any feedback is greatly appreciated!
DeltaFile
+52-0clang/test/CodeGen/AArch64/neon/fullfp16.c
+0-28clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
+8-4clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+60-323 files

LLVM/project ff604fdclang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-intrinsics.c

[clang][CIR] Add lowering for vcvt_n_ and vcvtq_n_ conversion intrinsics

This PR adds lowering for the conversion intrinsics with an immediate
argument (identified by `_n_` in the intrinsic name), excluding FP16
variants.

It also moves the corresponding tests from:
  * clang/test/CodeGen/AArch64/neon_intrinsics.c

to:
  * clang/test/CodeGen/AArch64/neon/intrinsics.c

The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp and adds the `getFloatNeonType` helper
to support it. The remaining changes are code motion and refactoring.

Reference:
[1] https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
DeltaFile
+197-147clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+222-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-201clang/test/CodeGen/AArch64/neon-intrinsics.c
+419-3483 files

LLVM/project 7cccf56mlir/lib/Transforms CSE.cpp, mlir/test/Transforms cse.mlir

Revert "[mlir][CSE] Delete dead code immediately in CSE pass" (#191146)

Reverts llvm/llvm-project#190926 ; this is crashing on simple examples
like:

```
func.func @test(%arg0: i1) {
  %c0_i32 = arith.constant 0 : i32
  %0 = arith.select %arg0, %c0_i32, %c0_i32 : i32
  %1 = scf.if %arg0 -> (i32) {
    %c0_i32_0 = arith.constant 0 : i32
    scf.yield %c0_i32_0 : i32
  } else {
    %c0_i32_0 = arith.constant 0 : i32
    scf.yield %c0_i32_0 : i32
  }
  return
}
```
DeltaFile
+0-32mlir/test/Transforms/cse.mlir
+5-9mlir/lib/Transforms/CSE.cpp
+5-412 files

LLVM/project 918e446lldb/packages/Python/lldbsuite/test lldbutil.py, lldb/test/API/macosx/simulator TestSimulatorPlatform.py

[lldb] Handle simulator printout in TestSimulatorPlatform (#189571)

This test invokes a binary in a simulator and then reads the first line
of stderr to parse the PID of the invoked binary.

This approach fails when the simulator itself prints a warning/error on
startup. In this case, we try to parse the error as the PID and fail.

This patch just removes the line limit. It doesn't seem to add any value
as we anyway need to search until we find the PID line, and if there is
no PID line we cannot do anything but time out eventually.

See also rdar://169799464
DeltaFile
+15-13lldb/packages/Python/lldbsuite/test/lldbutil.py
+0-1lldb/test/API/macosx/simulator/TestSimulatorPlatform.py
+15-142 files

LLVM/project e1ed14fllvm/lib/Transforms/Vectorize VPlan.h LoopVectorize.cpp

[VPlan] Add ::getSingleVF() helper and use it (NFC). (#191055)

Suggested as follow-up during recent reviews, including
https://github.com/llvm/llvm-project/pull/190393.
DeltaFile
+7-0llvm/lib/Transforms/Vectorize/VPlan.h
+2-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+9-22 files

LLVM/project 0646ebcllvm/test/TableGen/GlobalISelCombinerEmitter match-table-hoisting.td, llvm/test/TableGen/GlobalISelEmitter MatchTableOptimizerSameOperand-invalid.td

[GlobalISel] Prevent hoisting of CheckIsSameOperand from creating invalid match tables (#190963)

Fixes #188513

This patch adds logic to ask PredicateMatchers whether they'd like to be
hoisted out of a specific Matcher or not.
SameOperandMatcher can use it to check if it's being hoisted out of the
RuleMatcher that defines the operand it relies on.

Assisted-By: Claude Opus 4.6
Context of Use: Claude was only used to add LLVM-style RTTI to the
matcher class (repetitive work). I then reviewed and cleaned up the code
it generated.
DeltaFile
+97-0llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td
+38-1llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
+13-17llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+12-9llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td
+160-274 files

LLVM/project d6aa3fbmlir/lib/Transforms CSE.cpp, mlir/test/Transforms cse.mlir

Revert "[mlir][CSE] Delete dead code immediately in CSE pass (#190926)"

This reverts commit f73f8754cabd4caf3c9989d8f542d2b9a9f85d07.
DeltaFile
+0-32mlir/test/Transforms/cse.mlir
+5-9mlir/lib/Transforms/CSE.cpp
+5-412 files

LLVM/project a2d3d35llvm/include/llvm/ADT PostOrderIterator.h, llvm/lib/Target/SPIRV SPIRVUtils.h

fix + better MLIR use

Created using spr 1.3.8-wip
DeltaFile
+7-15llvm/unittests/ADT/PostOrderIteratorTest.cpp
+4-15mlir/include/mlir/IR/Iterators.h
+3-0llvm/include/llvm/ADT/PostOrderIterator.h
+1-0llvm/lib/Target/SPIRV/SPIRVUtils.h
+15-304 files

LLVM/project 8521290llvm/lib/Transforms/Scalar SeparateConstOffsetFromGEP.cpp, llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV split-gep.ll

[SeparateConstOffsetFromGEP] Fix incorrect inbounds flag in case of non-negative index but negative offset (#190192)

Fixes #190187 

Currently, SeparateConstOffsetFromGEP preserves inbounds attribute if
new sequence of GEPs from the same base pointer has non-negative offsets
in each GEP (this was mentioned in
https://github.com/llvm/llvm-project/pull/159515). This statement seems
correct for me (if the sequence consists from 2 GEPs), but current
implementation has a flaw: it checks that constant byte offset and GEP
indices are non-negative. However, in some corner cases we can have a
situation when the index is non-negative, but its offset (in bytes) is
negative, so we can't preserve inbounds attribute. In the example, GEP
index after transformation can have values
`0x7ffffffffffffffd`/`0x7ffffffffffffffe`/`0x7fffffffffffffff`; they are
all non-negative (sign bit is zero), however, after multiplication on
sizeof(i64) they become negative and inbounds can't be preserved
anymore.

The proposed fix is to check that Idx * ElementStride is non-negative
(instead of checking Idx only).
DeltaFile
+28-13llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+2-2llvm/test/Transforms/SeparateConstOffsetFromGEP/RISCV/split-gep.ll
+30-152 files

LLVM/project 3f3a83cclang/include/clang/StaticAnalyzer/Core/PathSensitive SValBuilder.h, clang/test/Analysis atomics.c

[analyzer] Canonicalize _Atomic pointers in makeNullWithType (#190131)

Fixes #187925
DeltaFile
+4-3clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
+5-0clang/test/Analysis/atomics.c
+9-32 files

LLVM/project a9b863ellvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp, llvm/test/CodeGen/AArch64/GlobalISel knownbits-stepvector.mir

[GlobalISel] Add G_STEP_VECTOR to computeKnownBits. (#190598)

This code is adapted from SelectionDAG::computeKnownBits.
part of https://github.com/llvm/llvm-project/issues/150515.
ticks off STEP_VECTOR.
DeltaFile
+116-0llvm/test/CodeGen/AArch64/GlobalISel/knownbits-stepvector.mir
+24-0llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+140-02 files

LLVM/project d404a2ellvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 logical-op-with-not.ll atomicrmw-O0.ll

Revert "[AArch64][CodeGen] match (or x (not y)) to generate mov+orn" (#191138)

Reverts llvm/llvm-project#190769

[Need to change email for the commit]
DeltaFile
+8-32llvm/test/CodeGen/AArch64/logical-op-with-not.ll
+12-12llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
+2-2llvm/test/CodeGen/AArch64/arm64-atomic.ll
+0-4llvm/lib/Target/AArch64/AArch64InstrInfo.td
+22-504 files

LLVM/project a0908aeclang/docs/analyzer/user-docs Annotations.rst, clang/include/clang/Basic AttrDocs.td

[clang][docs] Improve documentation of [[ownership_returns]] attribute (#191005)

The 2 parameter use of this attribute wasn't documented.

This clarification is based of the following two commits:
 - https://github.com/llvm/llvm-project/commit/d21139a34f51
 - https://github.com/llvm/llvm-project/commit/893a303962608
DeltaFile
+13-3clang/include/clang/Basic/AttrDocs.td
+11-2clang/docs/analyzer/user-docs/Annotations.rst
+24-52 files

LLVM/project e8ec1e2llvm/test/Analysis/DependenceAnalysis exact-rdiv-addrec-wrap.ll

[DA] Remove "FIXME" for a test that has been fixed
DeltaFile
+0-3llvm/test/Analysis/DependenceAnalysis/exact-rdiv-addrec-wrap.ll
+0-31 files

LLVM/project 7fa216bllvm/lib/Transforms/InstCombine InstCombineCompares.cpp, llvm/test/Transforms/InstCombine fp-floor-ceil.ll

[InstCombine] Simplify `floor`/`ceil` to `trunc` for integral tests (#190620)

Partially fix https://github.com/llvm/llvm-project/issues/188035

Some proof checks:

`fcmp oeq ceil(x), x` -> `fcmp oeq trunc(x), x`
[Proof](https://alive2.llvm.org/ce/z/kLQeFQ)
`fcmp one floor(x), x` -> `fcmp one trunc(x), x`
[Proof](https://alive2.llvm.org/ce/z/vyVAUX)
`fcmp ueq ceil(x), x` -> `fcmp ueq trunc(x), x`
[Proof](https://alive2.llvm.org/ce/z/DbFMZb)
`fcmp une floor(x), x` -> `fcmp une trunc(x), x`
[Proof](https://alive2.llvm.org/ce/z/QVLQLw)

This may be useful for CSE (due to `trunc(x) == x` is quite common
integral test) or further simplifications specific to `trunc`. Also,
`trunc` is cheaper if it lowered to
[libm](https://git.musl-libc.org/cgit/musl/tree/src/math/trunc.c) /
[libc](https://github.com/llvm/llvm-project/blob/b4f50cfd4a3a086db3f88271c9595056a877ef90/libc/src/__support/FPUtil/NearestIntegerOperations.h#L25)
call
DeltaFile
+140-16llvm/test/Transforms/InstCombine/fp-floor-ceil.ll
+9-1llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+149-172 files

LLVM/project 3d76932llvm/lib/Target/AArch64 AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 logical-op-with-not.ll atomicrmw-O0.ll

Revert "[AArch64][CodeGen] match (or x (not y)) to generate mov+orn (#190769)"

This reverts commit 42629d7a174a62b98835e2e4c738ccdce027590b.
DeltaFile
+8-32llvm/test/CodeGen/AArch64/logical-op-with-not.ll
+12-12llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
+2-2llvm/test/CodeGen/AArch64/arm64-atomic.ll
+0-4llvm/lib/Target/AArch64/AArch64InstrInfo.td
+22-504 files

LLVM/project 3ad6afepolly/lib/Transform Canonicalization.cpp

[Polly] Remove pipeline-level Oz handling for LoopRotate (#191137)

This handling was moved fully into the pass in
1662c200a5b151ad15b7efc82837076d8967dc11. However, that changed
missed the usage of LoopRotate in polly.
DeltaFile
+1-1polly/lib/Transform/Canonicalization.cpp
+1-11 files

LLVM/project ff34860llvm/include/llvm/Support TargetOpcodes.def, llvm/include/llvm/Target GenericOpcodes.td

[LLVM][GlobalISel] Implement G_STRICT_FCMP in IRTranslator (#190754)

- `G_STRICT_FCMP` and `G_STRICT_FCMPS` are constrained operations in
gMIR.
DeltaFile
+80-0llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-constrained-fcmp.ll
+17-0llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+6-0llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+6-0llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+2-0llvm/include/llvm/Target/GenericOpcodes.td
+2-0llvm/include/llvm/Support/TargetOpcodes.def
+113-06 files

LLVM/project f10050cllvm/include/llvm/ADT GenericUniformityImpl.h, llvm/include/llvm/Analysis UniformityAnalysis.h

refactor: update variable names in uniformity analysis
DeltaFile
+25-22llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+15-15llvm/lib/Analysis/UniformityAnalysis.cpp
+7-7llvm/include/llvm/ADT/GenericUniformityImpl.h
+4-4llvm/include/llvm/Analysis/UniformityAnalysis.h
+4-3llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
+55-515 files

LLVM/project 623d3bbflang/lib/Semantics check-omp-structure.cpp check-omp-loop.cpp, flang/test/Semantics/OpenMP assumed-size-array-dsa.f90 cray-pointer-usage.f90

[Flang][OpenMP] Data-sharing restrictions on assumed-size arrays (#189324)

Per `OpenMP 5.0 2.19.1 Data-Sharing Attribute Rules`, assumed-size
arrays are predetermined shared and may not appear in a data-sharing
clause besides `shared`.

Patch adds a semantics check for assumed-size arrays appearing in
clauses where they aren't allowed.
DeltaFile
+48-0flang/test/Semantics/OpenMP/assumed-size-array-dsa.f90
+15-0flang/lib/Semantics/check-omp-structure.cpp
+3-0flang/test/Semantics/OpenMP/cray-pointer-usage.f90
+1-0flang/lib/Semantics/check-omp-loop.cpp
+1-0flang/lib/Semantics/check-omp-structure.h
+68-05 files

LLVM/project 5a7c1e0clang-tools-extra/clang-tidy/readability NonConstParameterCheck.cpp, clang-tools-extra/docs ReleaseNotes.rst

[clang-tidy] Fix false positive in readability-non-const-parameter with dependent array subscripts (#190936)

Fixes #60163

---------

Co-authored-by: Zeyi Xu <zeyi2 at nekoarch.cc>
DeltaFile
+16-0clang-tools-extra/test/clang-tidy/checkers/readability/non-const-parameter.cpp
+9-5clang-tools-extra/docs/ReleaseNotes.rst
+6-1clang-tools-extra/clang-tidy/readability/NonConstParameterCheck.cpp
+31-63 files

LLVM/project 2684dfallvm/include/llvm/Analysis UniformityAnalysis.h, llvm/lib/Analysis UniformityAnalysis.cpp

refactor: update variable names in uniformity analysis
DeltaFile
+15-15llvm/lib/Analysis/UniformityAnalysis.cpp
+4-4llvm/include/llvm/Analysis/UniformityAnalysis.h
+19-192 files

LLVM/project fcb8fbaorc-rt/unittests SessionTest.cpp

[orc-rt] Move RedundantAsyncShutdown to SessionTest suite. NFCI. (#191130)

RedundantAsyncShutdown is a Session test, not a ControllerAccess test.
DeltaFile
+16-16orc-rt/unittests/SessionTest.cpp
+16-161 files

LLVM/project d512d4allvm/include/llvm/ADT GenericUniformityImpl.h, llvm/lib/Analysis UniformityAnalysis.cpp

[UniformityAnalysis] Skip CycleAnalysis on targets without branch divergence (#189948)

UniformityAnalysis unconditionally computes CycleAnalysis even on
targets that don't care about divergence, causing measurable
compile-time overhead (see [#99878
(comment)](https://github.com/llvm/llvm-project/pull/175167#issuecomment-4156230947)).

---------

Co-authored-by: padivedi <padivedi at amd.com>
DeltaFile
+13-12llvm/lib/Analysis/UniformityAnalysis.cpp
+10-4llvm/include/llvm/ADT/GenericUniformityImpl.h
+23-162 files

LLVM/project d2b1229clang/include/clang/Analysis/Analyses PostOrderCFGView.h, clang/lib/Analysis PostOrderCFGView.cpp

Fix Clang+MLIR

Created using spr 1.3.8-wip
DeltaFile
+11-180llvm/include/llvm/ADT/PostOrderIterator.h
+0-51clang/include/clang/Analysis/Analyses/PostOrderCFGView.h
+26-15mlir/include/mlir/IR/Iterators.h
+33-5clang/lib/Analysis/PostOrderCFGView.cpp
+2-1llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
+2-1llvm/include/llvm/Analysis/LoopIterator.h
+74-2534 files not shown
+78-25710 files

LLVM/project 4852657orc-rt/include/orc-rt Session.h, orc-rt/lib/executor Session.cpp

[orc-rt] Remove Session::waitForShutdown. (#191124)

The existing implementation triggered Session shutdown and then blocked
on a std::future that would be unblocked by an on-shutdown callback that
waitForShutdown had installed. Since there is no guarantee that this
callback would be the last one run, the result was that waitForShutdown
only guaranteed that it would not return until the shutdown sequence had
started (rather than completed).

This could have been fixed, but the Session destructor is already
supposed to block until the Session can be safely destroyed, so a
"working" waitForShutdown would be effectively redundant. Since it was
also a potential footgun (calling it from an on-detach or on-shutdown
callback could deadlock) it was safer to just remove it entirely.

Some Session unit tests do rely on testing properties of the Session
after the shutdown sequence has started, so a new utility has been added
to SessionTests.cpp to support this.
DeltaFile
+36-36orc-rt/unittests/SessionTest.cpp
+14-13orc-rt/lib/executor/Session.cpp
+6-10orc-rt/include/orc-rt/Session.h
+56-593 files

LLVM/project b743d7dclang/test/CIR/CodeGenHIP builtins-amdgcn.hip

update temp file name in test
DeltaFile
+2-2clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+2-21 files