Attributor: Add only new attributes when manifesting (#234241)
manifestAttrs collected the attributes to add in an AttrBuilder, then
copied the position's attribute set into another AttrBuilder to merge
them in. Collect them in an array and merge them into the set in one
pass. This requires the attributes passed to manifestAttrs to be sorted
like an attribute set, which all callers already do. The only one
passing more than one attribute is AMDGPUAttributor, whose implicit
argument attributes are sorted.
Instructions spent in amdgpu-attributor:
rocPRIM test_device_scan, gfx942: 770.2M -> 710.8M (-7.7%)
Blender Cycles HIP kernel, gfx1100: 380.0M -> 379.5M (-0.1%)
rocPRIM 16 tests, full LTO, closed world: 3019.8M -> 2855.9M (-5.4%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Index defs by direct superclass for getAllDerivedDefinitions
getAllDerivedDefinitions visited every def to find those derived from the
requested class. The results are cached per class, but adding a def
clears the cache, so each !instances during parsing scans again.
Generating the RISC-V DAG instruction selector scans all 260,000 defs 26
times.
Record each def under its direct superclasses when it is added, and have
a query test those superclasses instead of every def. A def with several
matching superclasses is found more than once, so remove the duplicates
after sorting.
RISCVGenDAGISel.inc tablegen run:
Gigainstructions Gigacycles CPU seconds
Before 61.4 33.8 10.5
After 60.9 (-0.8%) 31.7 (-6.0%) 9.9 (-5.8%)
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[Offload][omp] Route data memory operations through liboffload (#233884)
Use olMemcpy for DeviceTy::submitData/retrieveData/dataExchange and
olMemFill for omp_target_memset. Use `nullptr` instead of finding a host
device for operations involving the host.
Remove the now unused data_submit, data_submit_async,
data_retrieve_async, data_exchange, data_exchange_async and
is_data_exchangable plugin entry points.
Assisted by Claude.
[clang][C2y] Add the WG14 papers adopted in Ottawa (#234935)
Continues to only list papers that impact the frontend, so excludes
purely editorial changes and library-only changes.
[flang][OpenMP] Validate substrings (#234661)
IsSubstring discarded expression-analysis diagnostics while leaving
symbols marked erroneous. Those erroneous symbols would cause an
assertion failure if visited again.
Retain those diagnostics and improve diagnostics with more useful errors
that distinguish correctly between substrings and arrays.
Assisted-by: Codex
[Inliner] Use alloc size for byval copies (#234808)
Byval copies were sized with the store size, which is smaller than the
alloc size for types such as x86_fp80 and i24.
Fixes #234047
[AVR] Fix byte spills and stack args on AVRTiny
AVRTiny cores have no load/store with displacement, yet 8-bit spills,
reloads and stack arguments in functions without a reserved call frame
were still emitted as STDPtrQRr/LDDRdPtrQ. llc then aborted in the
AsmPrinter, so any function that spilled a byte failed to compile, also
with the default register allocator and at -O0, and builds without
assertions silently emitted std/ldd instead.
Expand both instructions on AVRTiny the same way as their 16-bit
counterparts: a plain st/ld when the displacement is zero, as it always
is for spill slots, and pointer adjustments around it otherwise.
[VPlan] Use llvm.mask.beforefirst for computing early exit mask
This makes the cost more accurate and improves codegen for RISC-V. The codegen for an early exit loop with side effects then goes from:
.LBB0_3: # %vector.body
# =>This Inner Loop Header: Depth=1
vl1r.v v16, (a3)
vsetvli zero, zero, e8, m1, ta, ma
vmseq.vi v16, v16, 0
vfirst.m a7, v16
srli t0, a7, 63
czero.nez a7, a7, t0
czero.eqz t0, a1, t0
or a7, t0, a7
vsetvli zero, zero, e64, m8, ta, ma
vmsltu.vx v0, v8, a7
vle8.v v17, (a5), v0.t
vcpop.m t1, v16
vsetvli zero, zero, e8, m1, ta, ma
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[SelectionDAG] Handle splitting in get_active_lane_mask expansion
Split when the type is legal, e.g. v64i1, but the step vector needed for expansion needs split, e.g. v64i8.
This can happen on avx512 when the 512 bit registers are disabled.
[DAG] Fix get_active_lane_mask expansion on 32-bit targets (#234487)
On e.g. wasm32, OpVT can be 32 bits whilst the StepVector type can be
v2i64. When this happens DAG.getConstant asserts because maxUIntN
doesn't fit into the 32 bits. Fix this by clamping it to OpVT's max
size.
[AArch64][llvm] Add support for FEAT_SME_F16F8F16 (#231435)
Add support for FEAT_SME_F16F8F16 (SME half-precision and FP8
sum-of-products accumulating to half-precision instructions).
[AArch64][llvm] Armv9.8-A: Add support for FEAT_SVE_PERM256 (#231433)
Add support for FEAT_SVE_PERM256 (SVE 128-bit element permute
instructions), which enables already existing instructions,
independently of FEAT_F64MM
[RISCV] Enable TunePreferAscendingLoadStore for spacemit-a100 (#234532)
Like spacemit-x60, a100 benefits from ascending LD/ST fusion.
Rename spacemitx60-stack-reorder.ll to stack-reorder.ll, add
spacemit-a100 and -mattr lines.
[clang][C] Update the C DR Status page (#234928)
WG14 has switched their issue processing system and so this now links to
the new issue logs instead of the historical ones, for improved
consistency. This also adds all of the issues filed against C23.
It does not add the issues filed against C2y because C2y is still in
progress and so those aren't really defect reports. However, we may want
to track them at some point to ensure we're conforming to their
resolutions.
[flang] Fix diagnostic order for invalid coarray dimension declarations (#219282)
Summary: Drop spurious "expected entity declarations" after missing '::'
#215886 made `withMessage()` anchor its message at the parser's start
location when no tokens matched. The nonstandard "`,` in place of `::`"
fallback for type declaration statements wraps its `,` in
`withMessage()`,
so when no `,` followed the attribute list it reported "expected entity
declarations" at the same location as the standard "expected '::'". The
two
messages tied and came out in the wrong order:
```fortran
integer :: d
real, dimension (0:d)[0:d] :: ra
end
```
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[LLDB][NativePDB] Set IsDynamicCXXType metadata for records (#155853)
All records were marked as not being a dynamic C++ type - even ones that
contain virtual methods. However, these _are_ dynamic C++ types.
With this PR, the metadata for dynamic C++ types is now set when a
record is completed and a type is considered dynamic if it has any
virtual method (e.g. destructor).
I'm not sure how to test this. I noticed this when implementing a
Microsoft ABI runtime to resolve types based on their vtables (PR TBD).
[Offload] Avoid invoking liboffload functions when uninitialized (#234645)
When libomptarget reads/detects `OMP_TARGET_OFFLOAD=disabled`, it skips
invoking `olInit()`, so subsequent calls to liboffload functions return
errors in most cases. This change adds minimal tracking of liboffload to
avoid such type of errors.
Assisted by Claude
[VPlan] Use llvm.mask.beforefirst for computing early exit mask
This makes the cost more accurate and improves codegen for RISC-V. The codegen for an early exit loop with side effects then goes from:
.LBB0_3: # %vector.body
# =>This Inner Loop Header: Depth=1
vl1r.v v16, (a3)
vsetvli zero, zero, e8, m1, ta, ma
vmseq.vi v16, v16, 0
vfirst.m a7, v16
srli t0, a7, 63
czero.nez a7, a7, t0
czero.eqz t0, a1, t0
or a7, t0, a7
vsetvli zero, zero, e64, m8, ta, ma
vmsltu.vx v0, v8, a7
vle8.v v17, (a5), v0.t
vcpop.m t1, v16
vsetvli zero, zero, e8, m1, ta, ma
[22 lines not shown]
