[llc] Fix -mcpu=help for default target triple (#187878)
Previously, a command like `llc -mcpu=help` would fail on invalid target
triple, due to wrongly passing empty target to `Triple::normalize`
resulting in `unknown`.
[opt] Enable -mcpu=help without an input file (#187876)
This patch enables `-mcpu=help` or `-mattr=help` invocation without an
input file, like `llc`. For example, the following command `opt
-mtriple=aarch64 -mattr=help` would previously hang but now it succeeds.
The implementation is similar to llc, creating a target machine for help
printing side effects and existing early. Note: llc has a bug in the
default triple handling that we already fix here upfront. Ill submit a
separate fix for llc.
[ASan] Enable __SANITIZER_DISABLE_CONTAINER_OVERFLOW__ tests (#181721)
Now that the corresponding libcxx change has landed, these tests should
be passing on some platforms.
This patch re-enables them for all platforms, so that we can see which
bots these do not work on and mark them unsupported accordingly.
rdar://167946476
[LegalizeTypes] Keep non-negative info in SUB(CTLZ) (#186338)
When legalizing CTLZ for a wider type with a SUB bit-width compensation,
the result for a zero-defined case can have an extra bit that exceeds
the maximum value of the original type width. Unlike CTLS, which covers
all bits within its type width, CTLZ leads to producing undefined
KnownBits. So, after subtraction, the KnownBits could represent a
negative value, which prevents subsequent optimizations.
This patch ensures that non-negative information is preserved during the
SUB(CTLZ) expansion, so that KnownBits after SUB will take a stricter
range within the type width, thus allowing further combine optimizations
following by SUB. Particularly, this enables the DAG Combiner to remove
unnecessary AND instructions for CTLZ output type conversion.
Fixes #136516
---------
Co-authored-by: Simon Pilgrim <git at redking.me.uk>
[libclc][NFC] Remove __CLC_BIT_INTN macro (#188023)
This macro was originally introduced in 64735ad63975 for relational
built-ins. It is functionally identical to __CLC_S_GENTYPE. Replacing it
simplifies gentype.inc, which is widely used in the library.
[C++20] [Modules] Apply DeclUpdate lazily in reduced BMI (#175498)
Previously we will apply all decl update unconditionally, but it might
not be best. See the attached example
'class-instantiate-no-change-02.cppm' for example. Sometimes these BMIs
are reducible.
Would land after 22 cut.
[ORC] Add a bootstrap symbols JITDylib to ExecutionSession. (#188172)
The ExecutionSession constructor now creates a "<bootstrap>" JITDylib
and populates it with the bootstrap symbols from the
ExecutorProcessControl object. This allows bootstrap symbols to be
looked up via ExecutionSession::lookup, providing greater consistency
with other JIT symbol lookups.
[DA] Add a test where the Weak Crossing SIV test misses dependency (NFC) (#188183)
The root cause is that the Weak Crossing SIV test assumes the
coefficients are non‑zero without verifying it.
libclc: Use nextup and nextdown in place of nextafter (#188141)
Unfortunately it seems the optimizer isn't able to clean this
up, so this is a code quality improvement.
Add XCOFF object file support in sanitizer coverage tool (#179884)
The sancov tool fails to find coverage symbols in XCOFF object files
because XCOFF uses a "." prefix for function entry point symbols. For
example, `__sanitizer_cov_trace_pc_guard appears` as
`.__sanitizer_cov_trace_pc_guard` in the symbol table.
Before this change, sancov reports:
`ERROR: __sanitizer_cov* functions not found`
This change strips the prefix "." when checking symbol names in XCOFF
files, allowing sancov to correctly identify coverage symbols.
---------
Co-authored-by: Honey Goyal <honey.goyal3 at ibm.com>
[LV][NFC] Remove some unused attributes from tests (#188091)
The local_unnamed_addr and dso_local attributes add no value to any of
the tests and simply increase file size, so I've removed all instances.
Revert "AMDGPU: Delay value replacement in PromoteAlloca (#186944)" (#188180)
This reverts commit 5624cce586c74ec7cfcbd0243f65cb1870677af7.
This is causing libclc failure. revert to fix it properly.
[clangd] Add ArcsinX as a maintainer (#187886)
To address clangd maintance problem, I'm nominating myself as a clangd
maintainer.
I'm currently actively reviewing PRs. I also participated in
clangd-related discourse discussions, subscribed to clangd issues and
PRs. For a while I plan to spend some time for PRs review in clangd.
[Hexagon] Optimize load/store instruction during widening (#186962)
This change enhances the Hexagon Load-Store Widening pass to recognize
and optimize a specific pattern involving the S2_addasl_rrri
instruction. When widening loads/stores, the pass now detects cases
where the base register is defined by an S2_addasl_rrri instruction and
combines the operations into a single load double/store double
instruction with register shift op, eliminating the intermediate address
calculation.
Eg, for load,
If the definition of the base register came from a addasl instruction,
we generate a
memd(Rs + Rt << #imm) instead of memd(Rs + #imm) instruction.
Transform:
%18 = S2_addasl_rrri %8, %17, 3
[9 lines not shown]
