LLVM/project e018166llvm/test/TableGen generic-tables-instruction.td generic-tables.td, llvm/utils/TableGen SearchableTableEmitter.cpp

[TableGen][NFC] Use templated std::clamp (#179400)

DeltaFile
+3-4llvm/utils/TableGen/SearchableTableEmitter.cpp
+2-2llvm/test/TableGen/generic-tables-instruction.td
+1-1llvm/test/TableGen/generic-tables.td
+6-73 files

LLVM/project 25890daclang-tools-extra/docs/clang-tidy/checks/abseil unchecked-statusor-access.rst

integer

Created using spr 1.3.6
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+1-1clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
+1-11 files

LLVM/project 3564a43clang-tools-extra/docs/clang-tidy/checks/abseil unchecked-statusor-access.rst

check

Created using spr 1.3.6
DeltaFile
+1-1clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
+1-11 files

LLVM/project 49adfb6clang-tools-extra/docs/clang-tidy/checks/abseil unchecked-statusor-access.rst

rst

Created using spr 1.3.6
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+1-0clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
+1-01 files

LLVM/project 28146a0clang-tools-extra/docs/clang-tidy/checks/abseil unchecked-statusor-access.rst

typo

Created using spr 1.3.6
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+1-1clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
+1-11 files

LLVM/project 0711a8emlir/test/Dialect/MemRef high-rank-overflow.mlir

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.6

[skip ci]
DeltaFile
+2-0mlir/test/Dialect/MemRef/high-rank-overflow.mlir
+2-01 files

LLVM/project 9ca78f2clang-tools-extra/docs/clang-tidy/checks/abseil unchecked-statusor-access.rst, mlir/test/Dialect/MemRef high-rank-overflow.mlir

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6
DeltaFile
+17-0clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
+2-0mlir/test/Dialect/MemRef/high-rank-overflow.mlir
+19-02 files

LLVM/project 114f3b5mlir/include/mlir/Dialect/Arith/IR ArithOps.td, mlir/test/Dialect/Arith invalid.mlir

[MLIR][Arith] Fix crash in `arith.select` verification with mixed types (#178840)

The `BooleanConditionOrMatchingShape` trait was assuming that if the
condition was not i1, both condition and result must be `ShapedTypes`.
It would then call `AllShapesMatch` which performs a blind cast to
`ShapedType`, causing a crash when one of the operands was a scalar.
This PATCH fixes the problem.

Closes [#178230](https://github.com/llvm/llvm-project/issues/178230)
DeltaFile
+8-0mlir/test/Dialect/Arith/invalid.mlir
+3-1mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+11-12 files

LLVM/project 14bebdellvm/cmake/modules TableGen.cmake

Revert "[TargetParser][cmake] Recurse for TableGen deps" (#179588)

Reverts llvm/llvm-project#177274

Appears to be breaking some bots.
DeltaFile
+1-1llvm/cmake/modules/TableGen.cmake
+1-11 files

LLVM/project 28d0208llvm/cmake/modules TableGen.cmake

[TargetParser][cmake] Recurse for TableGen deps (#177274)

In the dependency tracking for TableGen-generated files, globbing was
previously limited to the root of include directories. This missed
transitive dependencies in subdirectories, such as the target-specific
intrinsic definitions located in llvm/IR/.

Modifying these untracked files could cause global state (like the
intrinsic enum) to shift without triggering a rebuild of downstream
instruction selectors. This resulted in "Cannot select: intrinsic"
errors during incremental builds. Using a recursive glob ensures all
relevant TableGen files are correctly tracked regardless of their
directory depth.

Fixes #156744
DeltaFile
+1-1llvm/cmake/modules/TableGen.cmake
+1-11 files

LLVM/project 1ffe788llvm/lib/Target/PowerPC PPCISelLowering.cpp, llvm/test/CodeGen/PowerPC scalar_cmp.ll fsel.ll

[PowerPC] Remove NoInfsFPMath uses (#163029)

Only `ninf` should be used.
This is the PowerPC part.
DeltaFile
+458-888llvm/test/CodeGen/PowerPC/scalar_cmp.ll
+125-70llvm/test/CodeGen/PowerPC/fsel.ll
+34-76llvm/test/CodeGen/PowerPC/scalar-equal.ll
+0-67llvm/test/CodeGen/PowerPC/change-no-infs.ll
+1-1llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+618-1,1025 files

LLVM/project 22cc68cutils/bazel/llvm-project-overlay/mlir/test/Dialect BUILD.bazel

[bazel][mlir][emitc][test] Port #177339: tosa -> emitc test deps (#179578)

DeltaFile
+2-0utils/bazel/llvm-project-overlay/mlir/test/Dialect/BUILD.bazel
+2-01 files

LLVM/project 39f3d72libclc/clc/include/clc/math math.h, libclc/clc/lib/clspv/math clc_sw_fma.cl

[libclc] Only use software fma for r600 target (#179428)

Implement generic __clc_fma with __builtin_elementwise_fma for all
targets except for r600.

Add --spirv-ext=+SPV_KHR_fma flag to SPIR-V generation. SPIR-V target
supports @llvm.fma since SPV_KHR_fma was implemented in llvm-spirv
(https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/3467) and
SPIR-V backend (8f8dfbf8c9f0).
This PR assumes SPIR-V consumer with modern hardware supports fma.
DeltaFile
+0-274libclc/clc/lib/clspv/math/clc_sw_fma.cl
+174-0libclc/clc/lib/r600/math/clc_sw_fma.cl
+0-165libclc/clc/lib/generic/math/clc_sw_fma.cl
+0-16libclc/opencl/lib/spirv/math/fma.cl
+16-0libclc/clc/lib/r600/math/clc_fma.inc
+1-15libclc/clc/include/clc/math/math.h
+191-47013 files not shown
+218-52019 files

LLVM/project b9ceceellvm/lib/Bitcode/Reader MetadataLoader.cpp, llvm/test/DebugInfo/Generic lexical-block-types.ll inlined-local-type.ll

Reland "[DebugMetadata][DwarfDebug] Support function-local types in lexical block scopes (4/7)" (#165032)

This is an attempt to merge https://reviews.llvm.org/D144006 with LTO
fix.

The last merge attempt was
https://github.com/llvm/llvm-project/pull/75385.
The issue with it was investigated in
https://github.com/llvm/llvm-project/pull/75385#issuecomment-2386684121.
The problem happens when 
1. Several modules are being linked.
2. There are several DISubprograms that initially belong to different
modules but represent the same source code function (for example, a
function included from the same source code file).
3. Some of such DISubprograms survive IR linking. It may happen if one
of them is inlined somewhere or if the functions that have these
DISubprograms attached have internal linkage.
4. Each of these DISubprograms has a local type that corresponds to the
same source code type. These types are initially from different modules,

    [39 lines not shown]
DeltaFile
+424-0llvm/test/DebugInfo/Generic/lexical-block-types.ll
+124-54llvm/lib/Bitcode/Reader/MetadataLoader.cpp
+161-0llvm/test/DebugInfo/X86/local-type-as-template-parameter.ll
+139-0llvm/unittests/Transforms/Utils/CloningTest.cpp
+127-0llvm/test/DebugInfo/Generic/inlined-local-type.ll
+118-0llvm/test/Transforms/FunctionImport/funcimport-debug-retained-nodes.ll
+1,093-5430 files not shown
+1,760-24836 files

LLVM/project 3bd2ae7llvm/test/CodeGen/X86 vector-shuffle-combining-avx512f.ll

[X86] Add test coverage for #179008 (#179562)

DeltaFile
+35-0llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
+35-01 files

LLVM/project aa00a34llvm/lib/Target/RISCV RISCVInstrInfoV.td

[RISCV] Sink some encoding related lets into class/def bodies. NFC (#179544)

Rather than using lets around classes/defs, override them in the class
def/body.

Some of these lets were around single class/def were I thought it was
better to be inside. Some were around multiple unrelated classes where
it seemed better not to link their encodings like that.

For vmv, I added a multiclass to better encapsulate them but still kept
the let scope to avoid repetition. The encodings are closely related
enough that I thought this was ok.
DeltaFile
+40-28llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+40-281 files

LLVM/project 8a8c0cdmlir/lib/Dialect/MemRef/Transforms FoldMemRefAliasOps.cpp, mlir/test/Dialect/MemRef fold-memref-alias-ops.mlir

[mlir][MemRef] Make fold-memref-alias-ops use memref interfaces

This replaces the large switch-cases and operation-specific patterns
in FoldMemRefAliashops with patterns that use the new
IndexedAccessOpInterface and IndexedMemCopyOpInterface, which will
allow us to remove the memref transforms' dependency on the NVGPU
dialect.

This does also resolve some bugs and potential unsoundnesses:
1. We will no longer fold in expand_shape into vector.load or
vector.transfer_read in cases where that would alter the strides
between dimensions in multi-dimensional loads. For example, if we have
a `vector.load %e[%i, %j, %k] : memref<8x8x9xf32>, vector<2x3xf32>`
where %e is
`expand_shape %m [[0], [1], [2. 3]] : memref<8x8x3x3xf32> to 8x8x9xf32,
we will no longer fold in that shape, since that would change which
value would be read (the previous patterns tried to account for this
but failed).
2. Subviews that have non-unit strides in positions that aren't being

    [15 lines not shown]
DeltaFile
+425-440mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
+294-3mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
+719-4432 files

LLVM/project f665cf3llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+9-72 files

LLVM/project 4cae644libc/config/baremetal config.json

[libc] Disable strong stack protector for baremetal (#179559)

Strong stack protector introduces references to __stack_chk_guard
symbols with GOT relocation in ARM 32 bit targets which is not supported
in typical baremetal environments. Turning this off for baremetal.
DeltaFile
+5-0libc/config/baremetal/config.json
+5-01 files

LLVM/project efee25dllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+9-72 files

LLVM/project 65cc695llvm/include/llvm/CodeGen SelectionDAGISel.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGISel.cpp

Reapply "[SelectionDAGISel] Separate the operand numbers in OPC_EmitNode/MorphNodeTo into their own table. (#178722)"

This includes a fix to use size_t instead of uint64_t in one place.
DeltaFile
+57-6llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+17-8llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+6-2llvm/test/TableGen/CPtrWildcard.td
+7-0llvm/test/TableGen/RegClassByHwMode.td
+3-3llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+1-1llvm/include/llvm/CodeGen/SelectionDAGISel.h
+91-206 files

LLVM/project 4f04770llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv sext.mir zext.mir, llvm/test/CodeGen/RISCV/rvv vl-opt-op-info.mir vl-opt.mir

[RISCV] Print MIR comments for AVL and VEC_RM operands (#179542)

Such that we can now have something like:
```
PseudoVFMACC_VV_M2_E64 %1, %28, %28, 7 /* frm=dyn */, %21 /* vl */, 6 /* e64 */, 0 /* tu, mu */
```
or
```
PseudoVFMACC_VV_M2_E64 %1, %28, %28, 7 /* frm=dyn */, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */
```
Hopefully this could make reading RISC-V MIR (a little) less painful.
DeltaFile
+414-414llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+115-115llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+60-60llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
+56-56llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
+56-56llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir
+56-56llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir
+757-75750 files not shown
+1,232-1,21856 files

LLVM/project b0b9046llvm/lib/Target/BPF BTFDebug.cpp BPFISelLowering.cpp

[BPF] Replace copy-assign by move-assign in llvm/lib/Target/BPF/ (#179462)

An SDLoc transitively contains a TrackingMDRef which have a specialized
move constructor. It's more efficient to move element to it instead of
copying them.

FileContent contains std::vector<...> values. It's more efficient to
move then to copy the whole vector.
DeltaFile
+1-1llvm/lib/Target/BPF/BTFDebug.cpp
+1-1llvm/lib/Target/BPF/BPFISelLowering.cpp
+2-22 files

LLVM/project d0ee00bllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+9-72 files

LLVM/project 254b3b1mlir/lib/TableGen AttrOrTypeDef.cpp, mlir/test/IR test-verifiers-type.mlir

[mlir][tblgen] Add PredTypeTrait/PredAttrTrait support (#169153)

This patch adds support for `PredTypeTrait` and `PredAttrTrait` in type
and attribute definitions, enabling declarative predicate-based
verification similar to how `PredOpTrait` works for operations.

  ## Motivation

In 802bf02 (from 2021), `PredTypeTrait`/`PredAttrTrait` were defined in
TableGen but not implemented in the code generator. Using them causes
mlir-tblgen to crash with an assertion failure when trying to cast
`PredTrait` to `InterfaceTrait`. This patch fixes the crash and
implements the actual verification code generation.

  ## Usage

Use `$paramName` syntax in predicates to reference type/attribute
parameters:


    [15 lines not shown]
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+48-0mlir/test/IR/test-verifiers-type.mlir
+30-6mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
+30-0mlir/test/lib/Dialect/Test/TestTypeDefs.td
+5-3mlir/lib/TableGen/AttrOrTypeDef.cpp
+113-94 files

LLVM/project 43faefdllvm/lib/Transforms/IPO ArgumentPromotion.cpp, llvm/test/Transforms/ArgumentPromotion dbg.ll

[ArgPromotion] Add DW_CC_nocall to DISubprogram (#178973)

ArgumentPromotion pass may change function signatures. If this happens
and debuginfo is enabled, adding DW_CC_nocall allows dwarf to generate
    DW_AT_calling_convention        (DW_CC_nocall)
for DW_TAG_subprogram.
DeadArgumentElimination ([1]) already has similar implementation.

The pahole tool ([2]) is used in linux kernel build to generate vmlinux
BTF. One of its input is linux kernel dwarf. Currently, pahole
checks *all* DW_TAG_subprogram functions and find whether the source
signature matches the architecture ABI or not. If mismatch, pahole will
try to do some adjustment for those parameters. See [3]
and function parameter__new().

The linux kernel typically has ~65K functions and roughly 1100 functions
may have signature changed due to compile optimization. Without
DW_CC_nocall,
signatures of all of 64K functions will be checked in parameter__new().

    [34 lines not shown]
DeltaFile
+16-1llvm/test/Transforms/ArgumentPromotion/dbg.ll
+11-0llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
+27-12 files

LLVM/project d835071mlir/lib/Conversion/GPUToROCDL LowerGpuOpsToROCDLOps.cpp, mlir/test/Conversion/GPUToROCDL gpu-to-rocdl-subgroup-id.mlir

[mlir] GPUToROCDL: lower `gpu.subgroup_id` to the intrinsic where possible (#179422)

Lower `gpu.subgroup_id` to `wave.id` intrinsic on gfx12+, lower to
`linearized_thread_id / subgroup_size` on older.
DeltaFile
+63-2mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
+40-0mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-subgroup-id.mlir
+103-22 files

LLVM/project f9b5ab1lldb/include/lldb/DataFormatters FormatterBytecode.h

[lldb] Add missing include guard in FormatterBytecode.h (#179528)

DeltaFile
+5-0lldb/include/lldb/DataFormatters/FormatterBytecode.h
+5-01 files

LLVM/project f646131llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel unmerge-sgpr-s16.mir

AMDGPU/GlobalISel: Fix sgpr s16 unmerge lowering in regbanklegalize

Used to fail EXPENSIVE_CHECKS because of type mismatch.
DeltaFile
+5-3llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
+9-72 files

LLVM/project 7c29a09utils/bazel/llvm-project-overlay/lldb BUILD.bazel

[bazel][lldb] Port #179355: data formatters location (#179552)

DeltaFile
+1-2utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
+1-21 files