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[Polly] Reject scalable vector types (#177871)

Polly currently does not consider types without fixed length, which can
be encountered if an input source uses e.g. ARM SVE builtins. Such
programs have already been optimized manually. Non-fixed type lengths
also add to the difficulty of dependency analysis. Skip such types
entirely for now.
 
Fixes: #177859

[mlir][DialectUtils] Fix 0 step handling in `constantTripCount` (#177329)

A step size of "zero" does not indicate "zero iterations". It may
indicate an infinite number of iterations.

This commit makes some transformations more conservative. We used to
fold away some loops with step size 0 and that's now no longer the case.

Relation discussion:
https://discourse.llvm.org/t/infinite-loops-and-dead-code/89530

DAG: Use poison instead of undef in some vector combines (#177612)

Use poison for the unused or out of bounds vector components.

[SLP]Support for tree throttling in SLP graphs with gathered loads

Gathered loads forming DAG instead of trees in SLP vectorizer. When
doing the throttling analysis for such graphs, need to consider partially
matched gathered loads DAG nodes and consider extract and/or gather
operations and their costs.
The patch adds this analysis and allows cutting off the expensive
sub-graphs with gathered loads.

Reviewers: hiraditya, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/177855

[clang] Don't assert on perfect overload match with _Atomic (#176619)

An assertion incorrectly treated difference in _Atomic qualification as
different types for the purpose of verifying a perfect match in overload
resolution in C++.

Fixes #170433

[VectorCombine] Fold vector.reduce.OP(F(X)) == 0 -> OP(X) == 0 (#173069)

This commit introduces a pattern to do the following fold:

  vector.reduce.OP f(X_i) == 0 -> vector.reduce.OP X_i == 0

In order to decide on this fold, we use the following properties:

1. OP X_i == 0 <=> \forall i \in [1, N] X_i == 0 1'. OP X_i == 0 <=>
\exists j \in [1, N] X_j == 0
  2.  f(x) == 0 <=> x == 0

From 1 and 2 (or 1' and 2), we can infer that

  OP f(X_i) == 0 <=> OP X_i == 0.

For some of the OP's and f's, we need to have domain constraints on X to
ensure properties 1 (or 1') and 2.


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[clang][test] Fix builtin-rotate.c test __int128 test failure on ARM32 (#177732)

- Run the INT128 prefix checks on 64-bit targets since __int128 is not
supported on ARM32

Fixes https://lab.llvm.org/buildbot/#/builders/154/builds/26813

[bazel] Add missing dependencies for 778a2491149512109541cd5d59bad2d55024bdb7

update comments

DAG: Use poison instead of undef in some vector combines

Use poison for the unused or out of bounds vector components.

InstCombine: Apply parameter nofpclass in SimplifyDemandedFPClass (#176104)

Apply the use operand's nofpclass to the demanded mask.

InstCombine: Handle multiple use copysign

Handle multiple use copysign in SimplifyDemandedFPClass

InstCombine: Handle nsz in copysign SimplifyDemandedFPClass

If the only sign bit difference is for 0, fold through the source.

Address comments

InstCombine: Add baseline tests for SimplifyDemandedFPClass copysign improvements

Prepare to support more folds and multiple uses.

InstCombine: Improve single-use fneg(fabs(x)) SimplifyDemandedFPClass handling

Match the multi-use case's logic for understanding no-nan/no-inf context.
Also only apply the nsz handling in the single use case. alive2 seems to treat
nsz as nondeterministic for each use.

[DAG] Extend MinMax matchers to detect flippable sign (#177504)

Fixes #174328

[MLIR] Fix GCC's `-Wreturn-type` warnings (#177654)

This patch fixes `-Wreturn-type` warnings which happens if MLIR is built
with GCC compiler (11.5 is used for detecting)


Founded errors
```
build/llvm-llvmorg-21.1.8/mlir/lib/CAPI/Transforms/Rewrite.cpp: In function ‘MlirGreedyRewriteStrictness mlirGreedyRewriteDriverConfigGetStrictness(MlirGreedyRewriteDriverConfig)’:
build/llvm-llvmorg-21.1.8/mlir/lib/CAPI/Transforms/Rewrite.cpp:399:1: warning: control reaches end of non-void function [-Wreturn-type]
  399 | }
      | ^
build/llvm-llvmorg-21.1.8/mlir/lib/CAPI/Transforms/Rewrite.cpp: In function ‘MlirGreedySimplifyRegionLevel mlirGreedyRewriteDriverConfigGetRegionSimplificationLevel(MlirGreedyRewriteDriverConfig)’:
build/llvm-llvmorg-21.1.8/mlir/lib/CAPI/Transforms/Rewrite.cpp:414:1: warning: control reaches end of non-void function [-Wreturn-type]
  414 | }
      | ^
build/llvm-llvmorg-21.1.8/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp: In member function ‘mlir::Speculation::Speculatability mlir::gpu::SubgroupBroadcastOp::getSpeculatability()’:
build/llvm-llvmorg-21.1.8/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp:2522:1: warning: control reaches end of non-void function [-Wreturn-type]
 2522 | }

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[MoveAutoInit] Fix for miscompilation for #150120 (#173961)

Fixes the miscompilation discussed for the PR #164882 as part of
generalizing the optimization for the issue #150120.

Without this commit, MoveAutoInit moves the store instruction to a
different branch which does not dominate the user dominator node. This
results in UB at runtime. The example in the test case is specifically
for an irreducible loop, in which all the predecessor may not dominate
user dominator head.

To fix this problem, we've introduced a new check to verify if the
predecessor of the user dominator node does in fact dominate user
dominator node before deciding that it is the node where the instruction
will be moved to.

[MLIR][Python] Add a DSL for defining dialects in Python bindings (#169045)

Python bindings for the IRDL dialect were introduced in #158488. They
are currently usable—for constructing IR and dynamically loading modules
that contain `irdl.dialect` into MLIR. However, there are still several
pain points when working with them:

* The IRDL IR-building interface is not very intuitive and tends to be
quite verbose.
* We do not yet have the corresponding `OpView` classes for IRDL-defined
operations.

To address these issues, I propose creating a wrapper (effectively a
small “DSL”) on top of the existing IRDL Python bindings. This wrapper
aims to simplify IR construction and automatically generate the
corresponding `OpView` types. A simple example is shown below.

Currently, using the IRDL bindings looks like this:


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InstCombine: Infer nnan/ninf on rounding intrinsics (#177770)

Fix a crash in TTI

Created using spr 1.3.7

InstCombine: Infer nnan and ninf on fptrunc (#177769)

Teach SimplifyDemandedFPClass to do this, although this is
not yet applied directly to the cast.

[NFCI][AMDGPU] Use `GET_SUBTARGETINFO_MACRO` in `GCNSubtarget.h` and `R600Subtarget.h` (#177402)

We can finally get rid of the manually defined boolean variables, like
other targets. Even though most of them are now defined by macros, we
still need to add the entries.

InstCombine: Infer nnan and ninf on fpext (#177768)

Teach SimplifyDemandedFPClass to do this, although this is
not yet applied directly to the cast.

InstCombine: Infer nnan/ninf on canonicalize (#177771)

InstCombine: Infer nnan and ninf flags on log intrinsics (#177767)

Use the new common utility function to try fold to constant
or introduce flags.

InstCombine: Infer nnan and ninf flags on exp intrinsics (#177766)

Use the new common utility function to try fold to constant
or introduce flags.

[gn build] Port 49d464ccaf44

[gn build] Port 9311996261e1