Reapply [IRBuilder] Assert correct offset width for CreatePtrAdd (#239262)
Reapply #238806 without changes after fixing more CreatePtrAdd uses.
-----
Assert that the offset width matches the pointer index width. This is
supposed to become an IR well-formedness requirement when we switch to
ptradd, so we should start asserting it in the builder now.
Helpers like CreatePtrAddWith(Unsigned|Signed)Offset and
CreatePtrAddWith[SZ]ExtOrTrunc can be used to more conveniently create
ptradds with appropriately sized offsets.
Problematic uses of CreatePtrAdd were already adjusted in #238347.
[MemorySanitizer] Consistently use unsigned offsets (NFC) (#239193)
Helper functions for getting origin/shadow etc accepted a mix of int and
unsigned. I believe all of these offsets are non-negative, so use
unsigned everywhere to avoid confusion.
[RISCV][P-ext] Remove line breaks from argument list of function definition in tests. NFC (#238881)
These line breaks cause the update_llc_test_checks.py script to put the
checks in the middle of the argument list.
[mlir][ODS] Include headers required by generated dialect declarations and definitions (#239215)
Generated dialect declarations and definitions use C++ constructs that
are not declared by any header they include. They therefore relied on
the surrounding source file to include these headers first.
The dialect declarations now include the header declaring the dialect
base class, and the headers declaring `StringAttr` and `Operation` if
the dialect has discardable attributes. The dialect definitions include
`MLIRContext.h` if they load dependent dialects.
Similar to #236155 and #238735 but for the dialect generator.
Co-authored-by: Claude <noreply at anthropic.com>
[LoongArch] Fix misaligned frame-index offset for vldrepl.{h,w,d}
eliminateFrameIndex did not check that the final offset is a multiple of
the access size for [X]VLDREPL_{H,W,D}, so a byte-aligned stack object
could produce an unencodable immediate. Materialize the address in a
scratch register in that case, as is already done for [X]VSTELM_*.
Assisted-by: LLM
[TargetLowering] Use DAG.getLibcalls() in expandMultipleResultFPLibCall (#239150)
`getLibcallLoweringInfo` and the helper `getLibcallImplCallingConv`
access the `Libcalls` from TargetLoweringBase, which is constructed
without the LLVM Module being available. This affects the libcalls
available through module flags like `long-double-type`. SelectionDAG
already consults the module flags, so missing it here can lead
inconsistencies in which libcalls are available.
Fixes: #239145
[Offload][Omp] Decouple RecordReplay from PluginInterface (#236814)
After we broke the `GenericKernelyTy` dependence in the RecordReplay
(RR), most of it became independent from the `PluginInterface`.
This PR moves the RR logic from the `PluginInterface` to libomptarget
and changes RR to use OpenMP errors and liboffload for data transfers.
Still, the _VirtualAddress_ interfaces are not available through the
liboffload API so we use them through temporary helpers.
I purposely didn't move the RR source files from the plugin directory so
the changes in this PR would easier to review. The code will be
reorganized in a follow-up NFC PR.
It was verified by @kevinsala on NVIDIA and AMD gpus.
Assisted by Claude
---------
Co-authored-by: Kevin Sala <salapenades1 at llnl.gov>
Attributor: Only check once if time trace scopes are recorded
Every initialization and update of an abstract attribute opened a
TimeTraceScope, which checks if the time profiler is enabled out of line.
Check it once per Attributor instead. NFC.
CTMark instructions:u with -attributor-enable=light changes by O3 -0.02%,
ThinLTO -0.03%. The attributor-light pass itself is 0.3-0.8% faster
(callgrind), and 0.3-1.9% faster with the other pending Attributor
compile-time changes applied.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[mlir][nvgpu] Don't swizzle shared memory rows that aren't a power of 2 (#237179)
`nvgpu-optimize-shared-memory` miscompiles memrefs whose rows aren't a
power
of 2 long. The swizzle XORs the index of each 16-byte vector in a row
with low
bits of the row index. When a row holds a power of 2 number of vectors,
the
result is always an index in the same row, so the swizzle only reorders
each
row. Otherwise, the result can be past the end of the row: the access
then
lands in the next row and overwrites one of its vectors, or past the end
of
the buffer for the last rows.
Skip such memrefs and leave their accesses unswizzled.
Assisted-by: Claude
[orc-rt] Add sps::lookupInJITDylib controller-call wrapper (#239494)
sps::lookupInJITDylib asks the controller to look up a SymbolLookupSet
in the JITDylib identified by the given key address, calling the
controller handler identified by the new
orc_rt_tag_sps_lookupSymbolsInJITDylib tag.
Clients index the result by lookup-set position, so a controller result
whose length doesn't match the lookup set is reported as an error rather
than passed on.
This commit also adds DirectControllerAccess to the unit-test utilities:
a ControllerAccess that routes executor-to-controller calls to handlers
registered by tag and runs them on the calling thread. The new tests use
it to check that arguments and results survive the round trip; lookup
semantics belong to the controller and aren't tested here.
[Flang][OpenMP] Warn about SAVE variables in MAP w/o ALWAYS modifier (#209134)
When mapping a variable that has the SAVE attribute, a MAP clause is not
effective unless it has the ALWAYS modifier. The reason is that the
reference count of the variable on the device is infinite and thus no
data transfer occur when ALWAYS is not present. This is a common source
of errors and the compiler should warn about this behavior.
---------
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot at users.noreply.github.com>
[CIR][AMDGPU] Look through address_space views of __retval in insertSRetStores (#239151)
Summary:
- On AMDGPU, a non-trivial record is returned through a default address
space `sret` pointer, but `CIRGen` puts `__retval` in addrspace(5) and
uses it through an `address_space` cast.
- `insertSRetStores` replaced the alloca with the sret pointer even
though the types differ. The cast then became an identity cast:
`%0` = cir.cast address_space %arg0 : !cir.ptr<!rec_NT> ->
!cir.ptr<!rec_NT>`
- When the types differ, replace the alloca's `address_space` views with
the sret pointer instead, and erase the alloca once its return loads are
gone.
- Test: `amdgpu-sret-nontrivial.cir`
Relates to: https://github.com/llvm/llvm-project/issues/220471
Assisted by : claude opus 5.5
[clang] Update C++ DR status page (#239482)
This is a follow-up for #237113 that contains missing updates for the
C++ DR status page and fixes a typo in an issue status comment (it
didn't make it to the status page last time, so no one noticed).
[flang] Treat stack save/restore and fir.unreachable as not accessing memory (#239240)
These operations do not declare memory effects, so the alias analysis
assumed they may modify and reference any memory. They do not access
memory: answer NoModRef for them.
[tsan] Intercept C11 thrd_create, thrd_join and thrd_detach on glibc (#238768)
glibc implements thrd_create, thrd_join and thrd_detach by calling its
internal pthread functions directly, so the pthread interceptors never
see C11 threads. A thread created with thrd_create has no ThreadState
and crashes on its first instrumented access or intercepted call
(#199585).
Intercept them, forwarding to the real functions. thrd_create starts the
thread in a C11 trampoline, __tsan_c11_thread_start_func, and reuses the
pthread_create bookkeeping; reports strip the trampoline from thread
stacks, as they do __tsan_thread_start_func. thrd_exit needs no
interceptor.
Only glibc needs this: FreeBSD, NetBSD and Android implement the C11
functions with the public pthread functions, which are already
intercepted. The new SANITIZER_INTERCEPT_C11_THREADS will also be used
by the other sanitizers that need these interceptors.
Assisted-by: Claude
[DSE] Drop outdated header docs (NFC) (#239143)
Literally every sentence in the current documentation is wrong. Drop them, it's
easy to find the implementation file with more accurate documentation.
[clang][bytecode] Split up `InterpState::dealllocate()` (#239185)
Split it into the common case of "block has no pointers to it" and
"block that _does_".
[AMDGPU][GlobalISel] Form min3/max3 from minimumnum and maximumnum (#225795)
Map these to FMAX3/FMIN3 as SelectionDAG does, not the NaN-propagating
FMAXIMUM3/FMINIMUM3
[AMDGPU] Track GLOBAL_INV/WB/WBINV with xcnt on gfx12.5 (#236045)
Currently, GLOBAL_INV, GLOBAL_WB and GLOBAL_WBINV take the early FLAT
return in getEventsForImpl and never get VMEM_GROUP, so with XNACK an
$exec def after them gets no s_wait_xcnt. This patch adds VMEM_GROUP to
all three when the subtarget has xcnt and XNACK is enabled.
As a result, an s_load followed by one of these ops now counts as an
SMEM-to-VMEM switch, so the s_load address wait is dropped. An earlier
global_load address wait becomes s_wait_xcnt 1 instead of s_wait_xcnt 0.
