[mlir][python] Fix Python binding cast diagnostics for nanobind 2.13
nanobind 2.13.0 changed failing `nb::cast<T>()` to raise `cast_error`
(an alias for `std::bad_cast`) for all failures, including `None`,
instead of the previous distinct exception types. The bindings relied
on catching `std::runtime_error` separately from `cast_error` to emit a
helpful "(None?)" hint, so that branch became dead code and the `None`
diagnostics regressed (e.g. "(std::bad_cast)" instead of "(None?)"),
breaking check-mlir Python tests.
Decide the `None` hint from the value via `is_none()` rather than the
exception type. This is robust across nanobind versions (2.10-2.13).
Fixes #205329
[CodeGen] Search predecessors from the back in removePredecessor() (#206070)
In many passes involving CFG updates, it is a common pattern to process
the Predecessors vector from back to front for efficiency. However, the
current forward search in removePredecessor often results in an O(N)
complexity.
So this patch tries to change the search logic to a reverse search to
better align with the majority of actual CFG manipulation scenarios.
And in a real-world case (with ~16k predecessors), this modification can
help to reduce the execution time of the BranchFolder pass from
166.4951s to 6.0717s.
---------
Co-authored-by: Reid Kleckner <rkleckner at nvidia.com>
[mlir-c] Add ConversionTarget dynamic legality C API
Add mlirConversionTargetAddDynamicallyLegalOp,
mlirConversionTargetAddDynamicallyLegalDialect,
mlirConversionTargetMarkOpRecursivelyLegal, and
mlirConversionTargetMarkUnknownOpDynamicallyLegal to enable
per-instance legality callbacks from C.
[AArch64] Define GCS operations as SYS and SYSL aliases
Move the remaining `GCS` instructions from dedicated opcodes to `SYSxt/SYSLxt`
aliases, keeping a tied `SYSL` pseudo for codegen where `GCS` preserves the`
input register when disabled at runtime.
Update `GCS` intrinsic selection, scheduling, disassembly aliases, and MC
coverage for the generic `SYS/SYSL` encodings.
[LoongArch] Use vector extend for sitofp/uitofp (#202496)
Called sign/zero extend first in `performS[U]INT_TO_FPCombine` before
doing vector sitofp/uitofp, which avoid inefficient scalarization.
[LoongArch] Legalize LASX truncate with XVPICKEV instruction (#202485)
Add LASX truncate patterns for wide truncates (e.g. `v8i64 trunc to
v8i8`) with `XVPICKEV` instructions.
To merge two registers into one, return concat_vectors as is while its
two operations are `ISD::TRUNCATE`, also dealing with illegal results in
`ReplaceNodeResults`.
[Clang][OpenMP] Remove unnecessary LParentLoc in ThreadLimit and NumTeams clauses
The LParentLoc is already a field of the OMPVarListClause class. The ThreadLimit
and NumTeams clause classes should not need to define it.
[mlir-c] Add ConversionTarget dynamic legality C API
Add mlirConversionTargetAddDynamicallyLegalOp,
mlirConversionTargetAddDynamicallyLegalDialect,
mlirConversionTargetMarkOpRecursivelyLegal, and
mlirConversionTargetMarkUnknownOpDynamicallyLegal to enable
per-instance legality callbacks from C.
[AArch64][llvm] Tighten SYSP; don't disassemble invalid encodings
Tighten SYSP aliases, so that invalid encodings are disassembled
to `<unknown>`. This is because:
```
Cn is a 4-bit unsigned immediate, in the range 8 to 9
Cm is a 4-bit unsigned immediate, in the range 0 to 7
op1 is a 3-bit unsigned immediate, in the range 0 to 6
op2 is a 3-bit unsigned immediate, in the range 0 to 7
```
Ensure we check this when disassembling, and also constrain
tablegen for compile-time errors of invalid encodings.
Also adjust the testcases in `armv9-sysp-diagnostics.s` and
`llvm/test/MC/AArch64/armv9a-sysp.s` as they were invalid,
and added a few invalid (outside of range) SYSP-alikes to
test that `<unknown>` is printed
[mlir-c] Add DominanceInfo and PostDominanceInfo C API bindings
Expose DominanceInfo and PostDominanceInfo through the MLIR C API with
operation/block/value dominance queries, nearest common dominator,
reachability, and invalidation.
[mlir-c] Add DominanceInfo and PostDominanceInfo C API bindings
Expose DominanceInfo and PostDominanceInfo through the MLIR C API with
operation/block/value dominance queries, nearest common dominator,
reachability, and invalidation.
[AArch64][llvm] Implement HINT instructions as aliases (NFCI)
Implement some `HINT`-space encodings as aliases of `HINT`
instead of dedicated instructions. Re-implement these isns:
* bti
* psb
* stshh
* stcph
* shuh
* tsb
Parse aliases explicitly in `AArch64AsmParser::parseHintAlias()` as they
have custom operands. Remove the (now unused) `PSB`, `BTI`, `CMH`, `PHint`
and `TSB` tablegen defs, operand classes, parser hooks and printer helpers.
Also, tighten the BTI check in the parser. The old bitmask matched non-BTI
`HINT` immediates such as `shuh/stcph`; use an exact BTI HINT encoding
check instead (`isHintSpaceBTI()`)
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[clangd] Remove unused onlyValue<bool> overload (NFC) (#206312)
BundledEntry has three `std::string` members and no bool member, so the
bool overload of onlyValue can never be instantiated. It has been dead
since it was added and trips -Wunused-template.
NFC. Part of #202945.
