LLVM/project 7c55ad0llvm/docs Statepoints.md YamlIO.md, llvm/docs/Proposals GitHubMove.md

[LLVM][docs] Finish MyST migration for remaining docs (batch 11) (#223100)

Migration notes:

- I left several eval-rest blocks in `TableGen/ProgRef` which uses EBNF
production lists to define grammars. This apparently doesn't work in
myst.
- Accidental list blockquotes were converted to native lists. The
project-layout and Makefile entries in `Projects` are native definition
lists.

Tracking issue: #201242
See the [migration guide] for more information. 

[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is a stacked PR based on #223098, which is a standalone commit that
renames *.rst -> *.md before this PR lands for history preservation
purposes.

This was prepared with rst2myst plus LLM-assisted cleanup.
DeltaFile
+1,423-1,298llvm/docs/TableGen/ProgRef.md
+682-725llvm/docs/YamlIO.md
+619-706llvm/docs/TableGen/BackEnds.md
+619-612llvm/docs/Proposals/GitHubMove.md
+411-500llvm/docs/TableGen/BackGuide.md
+328-361llvm/docs/Statepoints.md
+4,082-4,20224 files not shown
+7,074-7,63830 files

LLVM/project 3830f77llvm/docs/Proposals GitHubMove.rst GitHubMove.md, llvm/docs/TableGen BackEnds.rst BackEnds.md

[LLVM][docs] Rename remaining reST docs to Markdown (batch 11) (#223098)

Tracking issue: #201242
See the [migration guide] for more information. 

[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines

This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.

The stacked conversion and cleanup is in #223100.
DeltaFile
+0-2,287llvm/docs/TableGen/ProgRef.rst
+2,287-0llvm/docs/TableGen/ProgRef.md
+0-1,213llvm/docs/TableGen/BackEnds.rst
+1,213-0llvm/docs/TableGen/BackEnds.md
+0-1,083llvm/docs/Proposals/GitHubMove.rst
+1,083-0llvm/docs/Proposals/GitHubMove.md
+4,583-4,58354 files not shown
+14,002-14,00260 files

LLVM/project 02e6ae3clang/lib/AST/ByteCode Compiler.cpp, clang/test/ASTMerge/class-template-partial-spec test.cpp

[clang][bytecode] Lazily evaluate static variables (#208794)

They usually go through `evaluateAsInitializer()`, which is where we
register them as global variables. But if they're imported, they don't.
Just try to evaluate them in `VisitMemberExpr()`.
DeltaFile
+6-2clang/lib/AST/ByteCode/Compiler.cpp
+4-0clang/test/ASTMerge/class-template-partial-spec/test.cpp
+10-22 files

LLVM/project 8fef76fclang-tools-extra/clang-tidy/modernize UseDesignatedInitializersCheck.cpp, clang-tools-extra/docs ReleaseNotes.md

[clang-tidy] Add null-checking in Use designated Initializer check (#220093)

Part of #219739

This null check should avoid null dereferencing crash in the Use
designated Initializer check.

AI has been used in this contribution to understand the code as I'm a
beginner to the codebase. The problem understanding and proposed fix is
mine.
DeltaFile
+19-0clang-tools-extra/test/clang-tidy/checkers/modernize/use-designated-initializers-invalid-decl-no-crash.cpp
+4-0clang-tools-extra/docs/ReleaseNotes.md
+1-1clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp
+24-13 files

LLVM/project 376f9b6llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mul.i24.ll

[AMDGPU] Fold 24 bit multiply with zero low bits

Fold `MUL_I24` and `MUL_U24` to zero when either operand has known zero
low 24 bits.

For example:
```
  llvm.amdgcn.mul.i24(x, 0x01000000) -> 0
```
DeltaFile
+21-33llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+5-0llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+26-332 files

LLVM/project 0229963llvm/test/CodeGen/AMDGPU llvm.amdgcn.mul.i24.ll

[AMDGPU] Add tests for zero MUL_I24 operands. NFC (#224536)

<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
DeltaFile
+155-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+155-21 files

LLVM/project f8de1a4llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 shuffle-lane-permute-cycle.ll

[X86] Prevent legalization cycles in lane-permute shuffle lowering (#224265)

When a cross-lane shuffle reproduces the original mask, trying a finer
sublane size can produce a decomposition that legalization transforms
back into the original shuffle. This causes legalization to cycle
indefinitely.

Stop trying finer sublane sizes when this condition is detected, and add
a regression test for the shuffle that previously caused `llc` to hang.

Fixes #224266
DeltaFile
+26-21llvm/lib/Target/X86/X86ISelLowering.cpp
+17-0llvm/test/CodeGen/X86/shuffle-lane-permute-cycle.ll
+43-212 files

LLVM/project c0c5635llvm/lib/Transforms/Scalar ConstraintElimination.cpp

[ConstraintElim] Add isNoWrap overload taking opcode + ops (NFC). (#224758)

Add overload that is independent of an IR value/instruction, and only
takes opcode + operands.

This prepares for using it in saturating/overflowing op simplification
in follow-ups.

PR: https://github.com/llvm/llvm-project/pull/224758
DeltaFile
+33-27llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+33-271 files

LLVM/project 534934cllvm/lib/Target/AArch64 AArch64InstrInfo.cpp, llvm/test/CodeGen/AArch64 early-ifcvt-fpr128.ll early-ifcvt-fpr128.mir

[AArch64] If-convert diamonds merging a 128-bit vector (#220616)

canInsertSelect handles GPRs via csel and 32/64-bit FPRs via fcsel, but
returns false for everything else. For example, EarlyIfConversion
flattens a diamond merging a v4i16 but leaves the equivalent v4i32
branchy.

We can create a conditional select similarly to how vector selects are
lowered in the backend by spreading the condition into an all-1's /
all-0's mask and use a bit select.

Assisted-by: Opus 5.0
DeltaFile
+164-0llvm/test/CodeGen/AArch64/early-ifcvt-fpr128.mir
+153-0llvm/test/CodeGen/AArch64/early-ifcvt-fpr128.ll
+30-1llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+347-13 files

LLVM/project a986c09mlir/lib/IR PatternMatch.cpp, mlir/test/Transforms remove-dead-values-return-segments.mlir remove-dead-values-llvm-call-segments.mlir

[MLIR] Preserve operand segment sizes when removing dead inputs (#223154)

`RemoveDeadRegionBranchOpSuccessorInputs` was calling `eraseOperands`
and ignoring potential `AttrSizedOperandSegments`. Trying to use
`populateRegionBranchOpInterfaceCanonicalizationPatterns` on downstream
control flow op with it resulted in broken IR. Update the segments sizes
if present.

Also fix LLVM dialect `CallOp` and `InvokeOp` `getArgOperandsMutable`
which were dropping segment sizes and a parser bug uncovered by the
tests.

Code was vibed and then edited, tests were vibed and not particularly
edited.
DeltaFile
+125-0mlir/test/Transforms/region-branch-operand-segments.mlir
+93-0mlir/test/Transforms/remove-dead-values-llvm-call-segments.mlir
+77-0mlir/test/Transforms/remove-dead-values-return-segments.mlir
+42-0mlir/test/lib/Dialect/Test/TestOpDefs.cpp
+31-0mlir/test/lib/Dialect/Test/TestOps.td
+31-0mlir/lib/IR/PatternMatch.cpp
+399-05 files not shown
+438-1011 files

LLVM/project 3dcd66dmlir/lib/Dialect/SCF/Transforms LoopSpecialization.cpp, mlir/test/Dialect/Linalg transform-op-peel-and-vectorize.mlir transform-op-peel-and-vectorize-conv.mlir

[mlir][scf] Do not peel an iteration out of an empty loop (#223257)
DeltaFile
+20-10mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
+9-9mlir/test/Dialect/SCF/for-loop-peeling.mlir
+7-4mlir/test/Dialect/SCF/for-loop-peeling-front.mlir
+2-2mlir/test/Dialect/SparseTensor/sparse_vector_peeled.mlir
+2-2mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize.mlir
+2-2mlir/test/Dialect/Linalg/transform-op-peel-and-vectorize-conv.mlir
+42-296 files

LLVM/project a9bd24allvm/include/llvm/CodeGen BasicTTIImpl.h, llvm/test/Analysis/CostModel/AArch64 sve-mulh.ll mulh.ll

[TTI] Add basic costs for llvm.[su]mulh. (#224002)

Defaults to the expansion (trunc ((ext(A) * ext(B)) >> BW)).
DeltaFile
+414-0llvm/test/Analysis/CostModel/RISCV/mulh.ll
+160-160llvm/test/Analysis/CostModel/X86/arith-mulh.ll
+181-0llvm/test/Analysis/CostModel/AArch64/mulh.ll
+36-0llvm/test/Analysis/CostModel/AArch64/sve-mulh.ll
+25-0llvm/include/llvm/CodeGen/BasicTTIImpl.h
+816-1605 files

LLVM/project 483b4dellvm/test/CodeGen/ARM vlldm-vlstm-uops.mir

ARM: Fix mixed dead and not-dead LR operands in vlldm-vlstm-uops.mir

This operand list had LR listed twice, once from its implicit-defs on
the instruction definition, and another in the variadic argument list.
One had a dead flag, and the other didn't which should be a verifier error
in the future, so remove the redundant operand.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+1-1llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
+1-11 files

LLVM/project 1415226llvm/lib/Target/LoongArch LoongArchExpandPseudoInsts.cpp, llvm/test/CodeGen/LoongArch test_bl_fixupkind.mir

LoongArch: Simplify handling of call pseudo operands when expanding.

copyImplicitOperands isn't really intended for the call instruction case
where there are also variadic operands. This avoids duplicating the R1
implicit-def operand when expanding calls. This avoids having mixed dead
and not dead flags on the same register, which will fail a future verifier
check.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+22-35llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
+2-2llvm/test/CodeGen/LoongArch/test_bl_fixupkind.mir
+24-372 files

LLVM/project 2bb259allvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp, llvm/test/CodeGen/AArch64 partial-reduction-sub.ll

[SelectionDAG] Allow PARTIAL_REDUCE_SUMLA in getPartialReduceMLS (#220886)

foldPartialReduceMLAMulOp turns

    partial_reduce_*mla(acc, neg(mul(sext(a), zext(b))), splat(1))

into a PARTIAL_REDUCE_SUMLA node and, because of the negation, builds it
through SelectionDAG::getPartialReduceMLS. That helper only accepted
UMLA
and SMLA, so the mixed-sign case hit its "Unexpected opcode" assertion
whenever the target marks SUMLA as legal or custom for the transformed
types. The loop vectorizer produces exactly this shape for a reduction
chain that mixes adds and subs, e.g.

    acc += (int)s8_a[i] * (int)u8_b[i];
    acc -= (int)s8_c[i] * (int)u8_d[i];

so this crashed at -O2 in builds with assertions enabled on AArch64 with
+dotprod, and since #205373 also on X86 with AVX512-VNNI (release builds

    [9 lines not shown]
DeltaFile
+466-0llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
+69-0llvm/test/CodeGen/AArch64/partial-reduction-sub.ll
+2-1llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+537-13 files

LLVM/project 991d80dllvm/include/llvm/Option OptTable.h, llvm/lib/Option OptTable.cpp

[Option] Store the StringTable by value. NFC (#224818)

Suggested by
https://github.com/llvm/llvm-project/pull/224805#discussion_r4052408942

A StringTable is just a StringRef. Hold it by value and build it from
the storage array in optionTables(), so the generated OptionStrTable
object (16 bytes of .data.rel.ro and a relocation per table) is
unreferenced and discarded, and string lookups skip a load.

Aided by Opus 5
DeltaFile
+14-14llvm/lib/Option/OptTable.cpp
+11-11llvm/include/llvm/Option/OptTable.h
+3-2llvm/utils/TableGen/OptionParserEmitter.cpp
+28-273 files

LLVM/project 7364128llvm/lib/Target/Mips Mips.td MipsSubtarget.cpp

[Mips] Remove experimental warning bits in a few places (#223230)

- Remove the warning message "warning: MIPS-I support is experimental" from
  MipsSubtarget.cpp. The warning can interfere with build systems that do not
  expect diagnostic output on stderr.
- Remove experimental / highly experimental from a few MIPS processors.
  MIPS I is on track and the rest I wouldn't consider experimental anymore.
DeltaFile
+0-7llvm/lib/Target/Mips/MipsSubtarget.cpp
+3-3llvm/lib/Target/Mips/Mips.td
+3-102 files

LLVM/project 8a371caorc-rt/include/orc-rt/bedrock/sps SimpleRemoteCA.h, orc-rt/lib/bedrock/sps SimpleRemoteCA.cpp

[orc-rt] In SimpleRemoteCA, carry tag field as uint64_t (#224814)

A message's tag field is a 64-bit value on the wire, so carry it as a
uint64_t inside SimpleRemoteCA and only convert to an ExecutorAddr or
ResultKind only where needed, with validation.
DeltaFile
+31-9orc-rt/lib/bedrock/sps/SimpleRemoteCA.cpp
+4-5orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCA.h
+2-2orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
+37-163 files

LLVM/project b3ef5fellvm/include/llvm/Option Option.h OptTable.h, llvm/lib/Option OptTable.cpp

[Option] Shrink Info from 40 to 24 bytes (#224807)

Few options set MetaVar, AliasArgs, Values, help text variants, or
subcommands (12%, 4%, 4%, 0.1%, 0.06% of 6955 options), yet every entry
carries all five. Move them to a deduplicated InfoExtra side table
reached by a 16-bit offset; row 0 serves options that set none. Narrow
Visibility to 16 bits; clang uses seven.

clang's table shrinks from 155 KB to 93 KB plus 4 KB of extras.

Aided by Opus 5
DeltaFile
+43-35llvm/include/llvm/Option/OptTable.h
+36-34llvm/utils/TableGen/OptionParserEmitter.cpp
+2-7llvm/include/llvm/Option/Option.h
+3-3llvm/lib/Option/OptTable.cpp
+84-794 files

LLVM/project 130c6b1llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mul.i24.ll

[AMDGPU] Fold 24 bit multiply with zero low bits

Fold `MUL_I24` and `MUL_U24` to zero when either operand has known zero
low 24 bits.

For example:
```
  llvm.amdgcn.mul.i24(x, 0x01000000) -> 0
```
DeltaFile
+21-33llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+5-0llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+26-332 files

LLVM/project 8b4c363llvm/test/CodeGen/AMDGPU llvm.amdgcn.mul.i24.ll

[AMDGPU] Add tests for zero MUL_I24 operands
DeltaFile
+155-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+155-21 files

LLVM/project 88c7a2allvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU wave32.ll spill-scavenge-offset.ll

[AMDGPU] Always optimize out llvm.amdgcn.mbcnt.hi in wave32 mode (#224573)

The instruction v_mbcnt_hi_u32_b32 does nothing useful in wave32 mode so
we can always optimize it regardless of the workgroup size.
DeltaFile
+3-16llvm/test/CodeGen/AMDGPU/wqm.ll
+9-10llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
+3-9llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+1-2llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
+0-2llvm/test/CodeGen/AMDGPU/wave32.ll
+0-2llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
+16-411 files not shown
+16-427 files

LLVM/project 7d091d5llvm/include/llvm/Option OptTable.h, llvm/lib/Option OptTable.cpp

[Option] Derive the prefix union in the constructor. NFC (#224813)

The union is a function of the prefix table, so compute it in the
OptTable constructor instead of emitting OptionPrefixesUnion and
carrying it in Tables.

LLM-aided, extracted from #224805
DeltaFile
+4-24llvm/utils/TableGen/OptionParserEmitter.cpp
+12-6llvm/lib/Option/OptTable.cpp
+0-1llvm/include/llvm/Option/OptTable.h
+16-313 files

LLVM/project 9109452libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.wait lost_wakeup.pass.cpp

[libcxx] Avoid a busy-loop in atomic's lost_wakeup.pass.cpp (#211242)

Fixes #207763
On single-core or heavily loaded systems, using this_thread::yield()
prevents the notifier from burning all its allocated time on the
busy-loop.

The measurements were done on my Linux box, the time is the one reported
by lit. To isolate the test on a single core I used the following
commands:

export LIT_FILTER="wait/lost_wakeup.pass.cpp"
taskset -c 0 ninja -C build check-cxx

| Configuration  | Linux futex |             | Fallback |             |
| -------------- | ----------- | ----------- | -------- | ----------- |
|                | Normal      | Pinned core | Normal   | Pinned core |
| Before         | 1.50s       | 8.44s       | 1.57s    | 301.02s     |
| With yield     | 1.73s       | 7.36s       | 1.64s    | 8.88s       |

Both configurations are with the `run < 10` change.
DeltaFile
+4-1libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.wait/lost_wakeup.pass.cpp
+4-11 files

LLVM/project 3efbad6llvm/tools/llvm-ifs llvm-ifs.cpp, llvm/tools/llvm-objcopy ObjcopyOptions.cpp

[Option] Replace the OptionTables object with a function. NFC (#224805)

The generated `Tables` holds seven addresses, so needs dynamic
relocations in PIE and shared library builds:

```
static constexpr llvm::opt::OptTable::Tables OptionTables = {
    OptionStrTable, OptionPrefixesTable, OptionPrefixesUnion, ...};
...
  FooOptTable() : OptTable(OptionTables) {}
```

Emit a function instead. The caller builds the aggregate on the stack
from PC-relative addresses, which the linker resolves:

```
static constexpr llvm::opt::OptTable::Tables optionTables() {
  return {OptionStrTable, OptionPrefixesTable, OptionInfoTable, ...};
}

    [7 lines not shown]
DeltaFile
+27-25llvm/utils/TableGen/OptionParserEmitter.cpp
+6-5llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
+2-2llvm/tools/llvm-rc/llvm-rc.cpp
+2-2llvm/tools/llvm-objdump/llvm-objdump.cpp
+3-1llvm/tools/llvm-readtapi/llvm-readtapi.cpp
+3-1llvm/tools/llvm-ifs/llvm-ifs.cpp
+43-3642 files not shown
+89-7948 files

LLVM/project 6f516d1flang/lib/Optimizer/Transforms/CUDA CUFAddConstructor.cpp, flang/test/Fir/CUDA cuda-constructor-2.f90

[flang][cuda] Emit cuda sentinel only when compiling main (#224507)

The sentinel must be added only when the `PROGRAM` is build in the TU.
DeltaFile
+20-6flang/test/Fir/CUDA/cuda-constructor-2.f90
+6-2flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
+26-82 files

LLVM/project 2230387flang/include/flang/Optimizer/Builder MutableBox.h, flang/include/flang/Optimizer/Dialect/CUF CUFOps.td

[flang][cuda] Split realloc for host-accessible CUDA Fortran allocatable assigns (#224195)

Allow SeparateAllocatableAssign to peel reallocation off hlfir.assign
for
managed, pinned, and unified allocatables, using cuf.alloc/cuf.free so
the
CUDA Fortran allocator is honored. Device (and other
non-host-accessible)
storage still keeps the runtime realloc path as well as derived-type.

Drop the extra op-level MemFree on cuf.free so OptimizedBufferization
can
see the freed pointer. Without that, a valueless Free effect between the
elemental and the assign forced a temporary for cases such as
`a = int(ran*100)` on a managed allocatable in the example below.

```
subroutine foo(n, a, ran)
  integer :: n

    [7 lines not shown]
DeltaFile
+51-0flang/test/HLFIR/opt-bufferization-dealloc-conflict.fir
+38-11flang/lib/Optimizer/Builder/MutableBox.cpp
+24-11flang/lib/Optimizer/HLFIR/Transforms/SeparateAllocatableAssign.cpp
+28-7flang/test/HLFIR/separate-allocatable-assign.fir
+5-2flang/include/flang/Optimizer/Builder/MutableBox.h
+1-1flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
+147-326 files

LLVM/project e35f904clang/include/clang/CIR/Dialect/IR CIRDialect.td, clang/lib/CIR/CodeGen CIRGenModule.h CIRGenFunction.h

[CIR][SYCL] Emit attributes on the SYCL kernel caller (#224667)

Emit norecurse, mustprogress, and sycl-module-id.

This matches the classic behavior that is specific to the SYCL kernel
caller.

---------

Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
DeltaFile
+47-0clang/test/CIR/CodeGenSYCL/kernel-caller-attributes.cpp
+27-3clang/lib/CIR/CodeGen/CIRGenSYCL.cpp
+21-6clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+16-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+3-0clang/include/clang/CIR/Dialect/IR/CIRDialect.td
+2-0clang/lib/CIR/CodeGen/CIRGenModule.h
+116-96 files

LLVM/project 18f2436lldb/test/API/functionalities/scripted_process TestScriptedProcess.py

[lldb/test] Register the addressable_bits_scripted_process module with the script interpreter (#224803)

`test_scripted_process_addressable_bits` imported
`addressable_bits_scripted_process` into the test process, which makes
the module's constants available to the test but tells lldb's own script
interpreter nothing about it, so
`SBLaunchInfo::SetScriptedProcessClassName()` had nothing to resolve:

```
  error: failed to create ScriptedProcess: failed to create script object:
  Could not find script class:
  addressable_bits_scripted_process.AddressableBitsScriptedProcess
```

Import the file with `command script import` the way the other scripted
process tests in this file do.
DeltaFile
+5-0lldb/test/API/functionalities/scripted_process/TestScriptedProcess.py
+5-01 files

LLVM/project 5d05951flang/test/Driver bbc-openmp-target-context.f90, flang/tools/bbc bbc.cpp

Set bbc target context for semantics
DeltaFile
+17-0flang/test/Driver/bbc-openmp-target-context.f90
+2-0flang/tools/bbc/bbc.cpp
+19-02 files