LLVM/project 2eeb5f1lldb/packages/Python/lldbsuite/test skip_reason.py lldbtest.py, lldb/test/API/functionalities/multi-breakpoint TestMultiBreakpoint.py

[lldb] Gate debugserver tests on advertised qSupported features (#214768)

Tests that need a recent `debugserver` skipped themselves with
`@skipIfOutOfTreeDebugserver`, which asks whether the stub was built in
the tree
rather than whether it supports the feature under test. A system
`debugserver`
that already ships the feature was skipped anyway, and a stale in-tree
build was
not.  Every year, we remove some `@skipIfOutOfTreeDebugserver` because
the new feature shipped in system `debugserver`.

Ask the stub instead.  Tests get the supported features of stub, and
only run the test if stub advertises the very feature.

`TestConsecutiveWatchpoints` keeps the decorator, because it covers a
`debugserver`
bug fix that no capability describes and it also runs against
`lldb-server`.

    [27 lines not shown]
DeltaFile
+12-0lldb/packages/Python/lldbsuite/test/lldbutil.py
+10-0lldb/test/API/test_utils/TestDecorators.py
+10-0lldb/packages/Python/lldbsuite/test/lldbtest.py
+2-4lldb/test/API/functionalities/multi-breakpoint/TestMultiBreakpoint.py
+4-2lldb/packages/Python/lldbsuite/test/skip_reason.py
+5-1lldb/test/API/macosx/expedited-stack-memory/TestExpeditedStackMemory.py
+43-75 files not shown
+51-1311 files

LLVM/project a6d40b4openmp/runtime/src kmp_runtime.cpp

[libomp] Fix hang when a fatal error is raised before library registration (#215988)

Uncovered by debug-build testing, not triggered for non-debug builds due
to absence of KMP_DEBUG_ASSERT.

Claude assisted with this patch.
DeltaFile
+16-0openmp/runtime/src/kmp_runtime.cpp
+16-01 files

LLVM/project 274d957clang/lib/CodeGen BackendUtil.cpp, llvm/include/llvm/Analysis RuntimeLibcallInfo.h

CodeGen: Remove TargetOptions::FloatABIType

This is now fully replaced with the "float-abi" module flag.
If the module flag is not present, the default is computed
from the triple. Consumers are updated to read the module flag.

RuntimeLibraryAnalysis now defers analysis until run() on a Module,
instead of during the pass constructor as before. This requires copying
all of the remaining relevant TargetOptions so they are available
when the module is seen.

Unfortunately, ARM still depends on TargetOptions for determining
the float-abi. -target-abi=aapcs16 still changes the default float-abi,
but an explicit module flag wins.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+45-0llvm/test/LTO/ARM/float-abi-module-flag.ll
+19-17llvm/include/llvm/Analysis/RuntimeLibcallInfo.h
+15-20llvm/lib/Target/ARM/ARMTargetMachine.cpp
+28-0llvm/test/Transforms/Util/DeclareRuntimeLibcalls/float-abi-module-flag.ll
+5-18llvm/lib/Analysis/RuntimeLibcallInfo.cpp
+3-14clang/lib/CodeGen/BackendUtil.cpp
+115-6923 files not shown
+175-12829 files

LLVM/project c24ac2fllvm/lib/CodeGen CommandFlags.cpp

Remove opt description change
DeltaFile
+1-3llvm/lib/CodeGen/CommandFlags.cpp
+1-31 files

LLVM/project 3c4a403llvm/lib/CodeGen CommandFlags.cpp, llvm/test/CodeGen/ARM float-abi-module-flag.ll float-abi-synthesize-flag.ll

Error on -float-abi conflicting with the "float-abi" module flag
DeltaFile
+17-5llvm/lib/CodeGen/CommandFlags.cpp
+5-3llvm/test/CodeGen/ARM/float-abi-module-flag.ll
+6-2llvm/test/CodeGen/ARM/float-abi-synthesize-flag.ll
+3-2llvm/test/CodeGen/CSKY/float-abi-module-flag.ll
+31-124 files

LLVM/project 43628cfllvm/lib/CodeGen CommandFlags.cpp, llvm/test/CodeGen/ARM float-abi-synthesize-flag.ll

CodeGen: Synthesize "float-abi" module flag from -float-abi

Avoid annoying test updates when the corresponding TargetOptions
field is removed. Make the -float-abi llc/opt option a lit test
convenience that records the floating-point ABI in the IR,
mirroring how -mcpu/-mattr are recorded as function attributes.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+32-0llvm/test/CodeGen/ARM/float-abi-synthesize-flag.ll
+11-1llvm/lib/CodeGen/CommandFlags.cpp
+43-12 files

LLVM/project 8a34f9dllvm/test/CodeGen/AArch64 complex-deinterleaving-crash.ll vec3-loads-ext-trunc-stores.ll

[DAGCombine][AArch64][X86] Adjust profitability check on and(anyext, c) -> zext(and) transform (#214749)

This existing fold was using a profitability check that did not work for
vector operations. It can be profitable to fold (and (anyext V), c) ->
(zext (and V, c)) if it allows the And to work on a narrower type and
possibly for the zext to be folded into other operations.

The combine is profitable or equal if the zext is the same cost as a
anyext. The old isTruncFree was removed as the value being truncated is
a constant. A basic version of isNarrowingProfitable is added for
AArch64 to allow vector types to fold providing that the result type is
legal and a isAnyExtFree method is added for the anyext cost.
DeltaFile
+49-54llvm/test/CodeGen/AArch64/zext.ll
+48-54llvm/test/CodeGen/AArch64/zext-to-tbl.ll
+24-52llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
+20-29llvm/test/CodeGen/AArch64/neon-extadd.ll
+15-29llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
+11-25llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll
+167-24312 files not shown
+225-29118 files

LLVM/project bd45111llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp

changes as per review feedback
DeltaFile
+33-30llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+33-301 files

LLVM/project 97f17a7llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp

[AMDGPU] Lower LDS flat round trips without provenance analysis
DeltaFile
+42-151llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+42-1511 files

LLVM/project d53ff04llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp, llvm/test/CodeGen/AMDGPU amdgpu-sw-lower-lds-flat-ptr-arg-asan.ll

update
DeltaFile
+231-94llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+213-30llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-ptr-arg-asan.ll
+444-1242 files

LLVM/project b8d2a47llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp, llvm/test/CodeGen/AMDGPU amdgpu-sw-lower-lds-flat-ptr-arg-asan.ll

[AMDGPU] Fix LDS access via flat pointer argument in amdgpu-sw-lower-lds
DeltaFile
+82-0llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+73-0llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-ptr-arg-asan.ll
+155-02 files

LLVM/project 38da688llvm/lib/Target/RISCV RISCVInstrInfo.cpp, llvm/test/CodeGen/RISCV optimize-cond-branch-undef.mir

RISCV: Fix optimizeCondBranch crash on an undef register (#216633)

Found by AI while working on something else.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+36-0llvm/test/CodeGen/RISCV/optimize-cond-branch-undef.mir
+6-1llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+42-12 files

LLVM/project 14c9bb9clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

[RISCV][P-ext] Support Packed Narrowing Clip Pair (#215779)
DeltaFile
+208-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+96-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+76-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+70-2llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+68-0llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+51-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+569-24 files not shown
+631-310 files

LLVM/project a045cb5llvm/lib/Target/DirectX DXILShaderFlags.cpp

Update size check in DXILShaderFlags
DeltaFile
+1-1llvm/lib/Target/DirectX/DXILShaderFlags.cpp
+1-11 files

LLVM/project 351d869llvm/lib/Target/X86 X86TargetTransformInfo.cpp, llvm/test/Analysis/CostModel/X86 zext-gep-index.ll

[X86][CostModel] Free a clean narrow zext used as a GEP index (#216256)

`getCastInstrCost` already treats a narrow (i8/i16) zext of a load as
free (the extension folds into the load). This extends the same
movzx-free reasoning to any narrow zext whose single use is a **GEP
index** with a provably-clean source — a load, a `zeroext` argument, or
known-zero high bits. On x86-64 `[base + index*scale + disp]` reads the
index at full width, so a clean narrow index needs no `movzx`. A dirty
source (e.g. an `i16 add` used only as an index) still needs one and is
unchanged. The cost is consumed by SimplifyCFG's two-entry-PHI fold
budget (`TCK_SizeAndLatency`); overcharging a clean index by one kept
small select diamonds branched on x86.

Test: `llvm/test/Analysis/CostModel/X86/zext-gep-index.ll` — fails on
trunk
(clean known-bits index reports 1), passes with the patch.

---------

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+141-0llvm/test/Analysis/CostModel/X86/zext-gep-index.ll
+31-0llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+172-02 files

LLVM/project 2b5f970clang/lib/Driver/ToolChains Clang.cpp, clang/lib/Driver/ToolChains/Arch RISCV.cpp

[RISCV] Move -mtune=native expansion into riscv::getRISCVTuneCPU. NFC (#215891)

Previously it was applied at one of the call sites. Applying it inside
makes it more clear how it is supposed to interact with
-mexperimental-mtune-syntax
DeltaFile
+13-7clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+3-6clang/lib/Driver/ToolChains/Clang.cpp
+6-0clang/test/Driver/riscv-mtune-tune-features.c
+22-133 files

LLVM/project 6a114fbllvm/unittests/ExecutionEngine/Orc SymbolLookupSetTest.cpp

[ORC] Extend SymbolLookupSet unit test coverage (#216617)

Covers the rest of the public API: construction, add/append, remove,
remove_if, forEachWithRemoval, getSymbolNames, sortByName, sortByAddress
and containsDuplicates.
DeltaFile
+392-9llvm/unittests/ExecutionEngine/Orc/SymbolLookupSetTest.cpp
+392-91 files

LLVM/project d2028c3llvm/include/llvm/Target TargetInstrPredicate.td, llvm/lib/Target/AArch64 AArch64SchedPredicates.td

[TableGen] Add checks for CheckRegOperand/CheckImmOperand (#215230)

`CheckRegOperand`, `CheckImmOperand`, and their related predicates
currently call `getReg()` and `getImm()` without first verifying that
the operand is a register or an immediate. Users must explicitly use
`CheckIsRegOperand` and `CheckIsImmOperand` to avoid errors for other
operand kinds, as exposed by #213815.

This PR adds default `isReg()` and `isImm()` checks to those predicates
before accessing the corresponding values, and also removes redundant
`CheckIsRegOperand` and `CheckIsImmOperand` checks from existing users
in the X86, ARM, and RISCV backends.
DeltaFile
+285-0llvm/test/TableGen/PredicateExpander.td
+114-50llvm/utils/TableGen/Common/PredicateExpander.cpp
+67-41llvm/include/llvm/Target/TargetInstrPredicate.td
+37-48llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+6-7llvm/utils/TableGen/Common/PredicateExpander.h
+5-5llvm/test/TableGen/ResolveSchedClass.td
+514-1516 files not shown
+520-18112 files

LLVM/project 7fb4cc0llvm/lib/Target/RISCV RISCVInstrInfo.cpp, llvm/test/CodeGen/RISCV optimize-cond-branch-undef.mir

RISCV: Fix optimizeCondBranch crash on an undef register

Found by AI while working on something else.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+36-0llvm/test/CodeGen/RISCV/optimize-cond-branch-undef.mir
+6-1llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+42-12 files

LLVM/project d04e49dmlir/include/mlir-c Interfaces.h, mlir/lib/Bindings/Python DialectTransform.cpp IRInterfaces.cpp

[MLIR][CAPI][Python] Add support for querying memory effect instances (#213459)

The current memory-effect bindings are write-only. Python interface
implementations can append effects to a temporary
`MemoryEffectInstancesList`, but callers cannot inspect an effect
instance or ask an operation for its effects.

This patch adds the missing query support to the C API and exposes it in
Python. Effect instances can be inspected and copied, and the Python
APIs use regular `MemoryEffectInstance` objects and Python-native
`list`s. The Transform helpers follow the same model.

`MemoryEffectInstancesList` is **removed** from both the C and Python
APIs. Python implementations and helpers now return effects instead of
mutating a supplied list, while the C API passes effects through
callbacks (`MlirMemoryEffectInstancesCallback`).

When an API produces a batch of effects, it invokes
`MlirMemoryEffectInstancesCallback` with a count and an array. The

    [15 lines not shown]
DeltaFile
+149-28mlir/lib/Bindings/Python/IRInterfaces.cpp
+97-34mlir/test/python/dialects/memory_effects_op_interface.py
+87-4mlir/test/CAPI/ir.c
+69-16mlir/include/mlir-c/Interfaces.h
+68-5mlir/lib/CAPI/Interfaces/Interfaces.cpp
+44-21mlir/lib/Bindings/Python/DialectTransform.cpp
+514-1089 files not shown
+649-15915 files

LLVM/project 77bdc16clang/lib/CodeGen BackendUtil.cpp

[dyndbg][Clang] Avoid memcpy on nullptr from #216307 (#216625)

As reported in
https://github.com/llvm/llvm-project/pull/216307#issuecomment-5311023374,
the new tests fail on UBSan buildbots (e.g.,
https://lab.llvm.org/buildbot/#/builders/25/builds/19323) because the
directory may be empty (only the file is initialized [*]). The StringRef
from getDirectory() would be default-initialized, and hashing it results
in memcpy'ing from a null pointer.

This patch attempts to fix-forward by not hashing the output of
getDirectory() if it is empty.

[*] e.g., `!3 = !DIFile(filename:
"/usr/local/google/home/thurston/llvm-projectA/clang/test/DebugInfo/DynamicDebugging/<stdin>",
directory: "")`
DeltaFile
+3-1clang/lib/CodeGen/BackendUtil.cpp
+3-11 files

LLVM/project c11305ellvm/lib/CodeGen MachineSink.cpp, llvm/test/CodeGen/X86 machinesink-coalesce-undef.mir

CodeGen: Fix MachineSink trivial coalescing crash on an undef register

Fix unchecked getVRegDef use. Found by AI while working on something else.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+39-0llvm/test/CodeGen/X86/machinesink-coalesce-undef.mir
+1-1llvm/lib/CodeGen/MachineSink.cpp
+40-12 files

LLVM/project ddba329llvm/include/llvm/ADT FoldingSet.h, llvm/lib/Support FoldingSet.cpp

[ADT] Clean up FoldingSet.* (NFC) (#216619)

This patch cleans up minor issues in FoldingSet.*.

- FoldingSetBase::NodeID never existed in the history of FoldingSet.
  The comment should refer to FoldingSetNodeID instead.

- GetBucketPtr lost the first line of its doc comment on February 4,
  2008 in commit e2887863563f, leaving only "testing.".

- ImmutableSetTest.cpp was relying on FoldingSet.h to include
  ArrayRef.h.

Other changes should be self-explanatory.

Assisted-by: Antigravity
DeltaFile
+5-6llvm/include/llvm/ADT/FoldingSet.h
+1-0llvm/unittests/ADT/ImmutableSetTest.cpp
+1-0llvm/lib/Support/FoldingSet.cpp
+7-63 files

LLVM/project 3cc0457clang/include/clang/CIR LoweringHelpers.h, clang/lib/CIR/Lowering LoweringHelpers.cpp

[CIR] Correct union lowering behavior re-padding (#216349)

Most of the code that CIR lowers to LLVM counts on the fact that our
alignnments are correct/calculated in LLVM to get our layout correctly.
This works for the most part, and unions have the storage type of the
'highest' alignment type.

However, when creating a constant, we have to convert the type of the
union to have a 'storage' type that matches the data being inserted (not
the union's storage type!). The result was that if we had a storage type
where the alignment was smaller than the actual storage type, LLVM would
mis-calculate the padding.

This patch adds the padding explicitly when we make that conversion to
get the alignment set up correctly.

Note: there is one mild IR-equivilency-regression to this patch. There
isn't really a great way to tell the difference between a
union-tail-padding needing zero-init vs undef-init in this case. This

    [2 lines not shown]
DeltaFile
+103-19clang/lib/CIR/Lowering/LoweringHelpers.cpp
+56-3clang/test/CIR/CodeGen/union-agg-init.c
+14-3clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+13-0clang/test/CIR/CodeGen/union-agg-init.cpp
+8-0clang/include/clang/CIR/LoweringHelpers.h
+3-3clang/test/CIR/CodeGen/unions-with-zero-init.cpp
+197-281 files not shown
+198-297 files

LLVM/project 9cd4a3dclang/test/CIR/CodeGen vtable-emission.cpp vtt.cpp, clang/test/CIR/CodeGenCXX vtable-linkage.cpp

[CIR] Fix the 'constant'-ness of vtable-variables (#216434)

The createOrReplaceCXXRuntimeVariable sets the variable to be 'constant'
in classic codegen, this sets that right. However, 1 use of it (in
buildVTablePointer) doesn't match classic-codegen (it instead calls
getOrInsertGlobal directly), so this patch adds a bit of a fixup there
to minimize the impact of this change.
DeltaFile
+57-57clang/test/CIR/CodeGenCXX/vtable-linkage.cpp
+10-10clang/test/CIR/CodeGen/thunks.cpp
+5-9clang/test/CIR/CodeGen/vtable-linkage-explicit-instantiation.cpp
+6-6clang/test/CIR/CodeGen/vtt.cpp
+6-6clang/test/CIR/CodeGen/multi-vtable.cpp
+3-6clang/test/CIR/CodeGen/vtable-emission.cpp
+87-948 files not shown
+105-10714 files

LLVM/project a878778mlir/include/mlir/Interfaces ControlFlowInterfaces.h, mlir/lib/Dialect/SCF/IR SCF.cpp

[mlir] Fix RemoveDeadRegionBranchOpSuccessorInputs producing invalid scf.for

RemoveDeadRegionBranchOpSuccessorInputs builds its tied-value sets from
RegionBranchOpInterface::getSuccessorOperandInputMapping, which is derived from
getSuccessorRegions. For an scf.for with a statically-known trip count of 1,
getSuccessorRegions drops the region->region back edge (the loop provably never
iterates back). That back edge is what forwards a yield operand to the region
iter_args, so without it an iter_arg and its corresponding op result are no
longer tied through a shared operand. The pattern then removes a dead iter_arg
without its (structurally required) result, producing an scf.for with
mismatched loop-carried counts:

    'scf.for' op mismatch in number of loop-carried values and defined values

The greedy driver repairs this on a later iteration (InlineRegionBranchOp folds
the single-trip loop), so it is only observed with
MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS, which verifies the IR after every
pattern application. It shows up across Linalg tiling / pack-unpack /
convolution lowering and scf loop canonicalization; see issue #163599.

    [15 lines not shown]
DeltaFile
+29-7mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+25-2mlir/lib/Dialect/SCF/IR/SCF.cpp
+17-2mlir/include/mlir/Interfaces/ControlFlowInterfaces.h
+71-113 files

LLVM/project 62540c7llvm/include/llvm/IR RuntimeLibcalls.td, llvm/test/CodeGen/X86 fp128-libcalls-gnu.ll

RuntimeLibcalls: Provide fp128 long double libcalls on X86

16a8d8d038a3  removed the l-suffixed long double math functions
from the default set and re-added them per-target gated on
isLongDoubleF128, but X86 was not given the re-add. On targets
whose long double is fp128 (e.g. x86_64 Android/OHOS) this dropped
the fp128 l-suffixed libcalls.

Fixes the regression reported on #214944.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+264-4llvm/test/CodeGen/X86/fp128-libcalls-gnu.ll
+8-0llvm/include/llvm/IR/RuntimeLibcalls.td
+272-42 files

LLVM/project 6530e27llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp

[CodeGen] Pass the atomic instruction to supportsUnalignedAtomics
DeltaFile
+2-2llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+3-1llvm/include/llvm/CodeGen/TargetLowering.h
+5-32 files

LLVM/project 4dc3ef8mlir/lib/Interfaces ControlFlowInterfaces.cpp

[mlir] Fix RemoveDeadRegionBranchOpSuccessorInputs producing invalid scf.for

RemoveDeadRegionBranchOpSuccessorInputs builds its tied-value sets from
RegionBranchOpInterface::getSuccessorOperandInputMapping, which is derived from
getSuccessorRegions. For an scf.for with a statically-known trip count of 1,
getSuccessorRegions drops the region->region back edge (the loop provably never
iterates back). That back edge is what forwards a yield operand to the region
iter_args, so without it an iter_arg and its corresponding op result are no
longer tied through a shared operand. The pattern then removes a dead iter_arg
without its (structurally required) result, producing an scf.for with
mismatched loop-carried counts:

    'scf.for' op mismatch in number of loop-carried values and defined values

The greedy driver repairs this on a later iteration, so it is only observed
with MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS (which verifies the IR after
every pattern application). It shows up across Linalg tiling / pack-unpack /
convolution lowering and scf loop canonicalization; see issue #163599.


    [6 lines not shown]
DeltaFile
+65-0mlir/lib/Interfaces/ControlFlowInterfaces.cpp
+65-01 files

LLVM/project d0b4c1bllvm/lib/CodeGen TargetRegisterInfo.cpp, llvm/lib/Target/PowerPC PPCInstrInfo.cpp

PowerPC: Fix FMA reassociation crash on an undef multiply operand (#216602)

Make sure getVRegDef succeeded.

Found by AI while working on something else.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+73-0llvm/test/CodeGen/PowerPC/fma-reassoc-undef-mul.mir
+1-1llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+1-1llvm/lib/CodeGen/TargetRegisterInfo.cpp
+75-23 files