[libc][math][c23] Add sinbf16 function (#185441)
This PR intends to add sinbf16 higher math function for bfloat16 type .
( The new header comments are updated using gemini flash 3.8 (low) )
[MC] Declare -asm-macro-max-nesting-depth in TableGen (#239994)
Move to MCCLOptions and expose it through
MCAsmInfo::getAsmMacroMaxNestingDepth. The lone MCParser option does not
justify creating MCParserOptions.td.
[mlir][docs] Fix minor typos in mlir/docs (#239256)
* Tutorials/Toy; cheks -> checks
* Bindings/Python.md; attribtues -> attribute
The former was found by reading the Toy Tutorial.
The latter was found by having AI scan the mlir/docs dir.
AI tool used: codex with GPT-6-Luna
[AMDGPU] Warn about missing async barrier replay workarounds
Warn by default when assembly lacks the recognized EXEC-zero B8 replay
after an async barrier arrival. Keep recognition within a straight-line
assembly block and support targeted and general warning controls.
[SPARC] Load integers directly into FP registers for sitofp (#237919)
Load the integer into the FP register directly instead of going via the
stack when the conversion is the only user of the loaded value.
Assisted-by: Claude
[SLP]Skip FP identity columns in reassoc chains
- Treat -0.0 (fadd), 1.0 (fmul) and +0.0 (subtracted fadd column) as
identities, so identity-only columns are not combined.
- Model a copyable identity by the sign of its column: -0.0 in a
subtracted fadd column turned a -0.0 lane into +0.0 without nsz.
Assisted-by: Cursor
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/239971
[AMDGPU] Expand async barrier replay during MC emission
Keep the replay as a counted load pseudo until MC emission, where it
expands to the EXEC save, zero-EXEC load, and restore. Preserve register
accounting, instruction size, clause boundaries, bank selection, and
the trailing scalar delay.
Gate the pass by subarchitecture in both pipelines, retain per-function
feature overrides, and simplify EXEC scratch renaming. Replace the small
high-bank MIR-to-assembly test with IR and cover the expansion boundaries.
[clang-repl] Restore the lookup of out-of-line definitions' predecessors (#229780)
Undoing the out-of-line definition of a member removes it from the
lookup table of its semantic context, its class or namespace, and then
makes its surviving previous declaration visible again. But the previous
declaration was made visible in the lookup table of the lexical context,
the enclosing context of the definition. The member was then not found
in its class or namespace anymore, but in the enclosing context instead:
struct K { static int s; };
int K::s = 4;
%undo
int K::s = 5; // error: no member named 's' in 'K'
Make the previous declaration visible in its own semantic context.
Assisted-by: Claude Opus 5.5
[SCEV] Prove non-strict & not-equal later isBasicBlockEntryGuard (NFCI). (#239818)
isBasicBlockEntryGuardedByCond eagerly tried to prove a strict predicate
as its non-strict half and non-equality, up front and for each guarding
condition, even if a later condition implies the predicate directly.
Trying all conditions directly instead first can speed up compile-time,
because either the predicate holds directly or we can avoid the more
expensive non-equality proofs because the non-strict predicate also does
not hold.
stage1-O3: -0.15%
stage1-ReleaseThinLTO: -0.13%
stage1-ReleaseLTO-g: -0.11%
stage1-aarch64-O3: -0.16%
stage2-O3: -0.14%
stage2-clang: -0.02%
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[AMDGPU] Price misaligned flat and LDS accesses with the LDS misaligned bug
In WGP mode on subtargets with the LDS misaligned bug, a flat access is
split into pieces no wider than its alignment and no narrower than 4
bytes, and an LDS access aligned below 4 bytes uses 8-byte pieces as one
aligned to 4 does.
[AMDGPU] Price buffer fat pointer memory operations
Price buffer fat pointer accesses as global accesses, except that an
aligned load is not widened and a vector of odd width elements is not
split element by element. Without relaxed buffer bounds checking, a
vector of elements that are a multiple of 32 bits wide is accessed in
pieces no wider than its alignment and no narrower than 4 bytes, and a
vector of other byte-sized or power of 2 wide elements in pieces of the
largest power of 2 bytes that divides the element size. The width comes
from buffer fat pointer lowering, which now exposes it. When the pointer
is a buffer resource plus a constant offset, the offset and a constant
number of records give the same bounds facts lowering uses to access it
in wider pieces.
[AMDGPU] Price constant address space memory operations
Price constant address space accesses as global accesses, except for
loads selected to scalar loads of up to 64 bytes. These are loads from
the 32-bit constant address space, and loads from the constant address
space whose pointer is an argument passed in SGPRs or a constant, plus
constant offsets, both aligned to 4 bytes or to their size. A scalar
load is widened as its lowering does. An integer whose size is not a
multiple of 4 bytes is loaded as whole dwords, plus a byte load when its
size is 7 modulo 8, since the last byte of such a remainder is left out
of the scalar load. A type with no legal dword vector equivalent is
split into the largest power of 2 pieces that fit, and once the
remainder fits in the alignment it is widened to a power of 2 piece of
up to the alignment, at most 8 bytes for byte vectors. A 3-dword
remainder of a legal dword vector takes a fourth dword when aligned to 8
on a subtarget without scalar dwordx3 loads.
