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[clang-tidy][NFC] Fix misc-override-with-different-visibility warnings (#182763)

Ran with config:
```yaml
  - key:             misc-override-with-different-visibility.DisallowedVisibilityChange
    value:           widening
```
I think we should only care about widening changes.

[clang-tidy][NFC] Fix readability-inconsistent-ifelse-braces warnings (#182764)

This align with [LLVM coding
conventions](https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements):
Quote:
```cpp
// Use braces for the `if` block to keep it uniform with the `else` block.
if (isa<FunctionDecl>(D)) {
  handleFunctionDecl(D);
} else {
  // In this `else` case, it is necessary that we explain the situation with
  // this surprisingly long comment, so it would be unclear without the braces
  // whether the following statement is in the scope of the `if`.
  handleOtherDecl(D);
}
```

[clang-tidy][NFC] Fix readability-redundant-parentheses warnings (#182766)

[AMDGPU] Add VOPD to gfx13

[AMDGPU] Add VOP2 to gfx13

[SPIR-V] Don't emit alignment decoration for non-kernel SPIR-V (#182772)

Fixes: https://github.com/llvm/llvm-project/issues/135165

[RISCV] Reduce duplicated SFB patterns in RISCVInstrInfoXAndes.td. NFC. (#182800)

This PR is similar to what we did in RISCVInstrInfoSFB.td.

[AMDGPU] Add VFLAT, VGLOBAL, VSCRATCH to gfx13

[AMDGPU] Move `advanceBeforeNext` before `advanceToNext`

The document of `advanceToNext` says, `advanceBeforeNext` has to be called first.

[NFC][AMDGPU] Move `advanceBeforeNext` before `advanceToNext`

The document of `advanceToNext` says, `advanceBeforeNext` has to be called first.

formatting

Created using spr 1.3.7

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]

formatting

Created using spr 1.3.7

[MLIR][Python] Add Python and C API of `mlir::DynamicType` (#182751)

This PR adds C and Python API support for `mlir::DynamicType`. It
primarily enables types in dialects that are dynamically generated via
IRDL to be constructed in Python, and allows retrieving the parameters
contained in a dynamic type from Python.

---------

Co-authored-by: Rolf Morel <rolfmorel at gmail.com>

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[VPlan] Handle extracts for middle blocks also used by early exiting blocks. NFC (#181789)

Currently createExtractsForLiveOuts only handles creating extracts when
the middle block has one predecessor, but if an early exit exits to the
same block as the latch then it might have multiple predecessors.

This handles the latter case to avoid the need to handle it in
VPlanTransforms::handleUncountableEarlyExits. Addresses the comment in
https://github.com/llvm/llvm-project/pull/174864#discussion_r2794153217

[TargetLowering][RISCV] Avoid ISD::MUL in expandCLMUL if hasBitTest or MUL requires a library call. (#182389)

Scalar multiply is not part of the most basic RISC-V ISA. Use a
and+setcc+select for these targets.

The and+setcc+select is also beneficial for targets with bit test
instructions. RISC-V may not get the full benefit here due to
not having a cmove-like instruction without Zicond.

Co-authored-by: fbrv <Fabio.Baravalle at gmail.com>

[CodeGen][NewPM] Name parameters in buildCodeGenPipeline

This is consistent with the coding style, and makes things consistent
between the various header files/improves readability slightly.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/182774

[RISCV] Update Andes45 vector floating-point arithmetic scheduling info (#181289)

This PR adds latency/throughput for all RVV floating-point arithmetic to
the andes45 series scheduling model.

[libc++] Fix typo in atomic.h comment (#182719)

[mlir] Make [tensor|memref]::ExpandShapeOp verifier stricter. (#181020)

The number of dynamic dims in output_shape is expected to be as the same
as the result type.

The revision also trims double whitespaces from the doc, because it also
updates the op description.

---------

Signed-off-by: hanhanW <hanhan0912 at gmail.com>

[libclc][CMake] Add COMPONENT ${ARG_PARENT_TARGET} to install (#182716)

Toolchain can specify the component to selectively install libclc to a
deploy folder. E.g. our downstream SYCL toolchain deploy:
https://github.com/intel/llvm/blob/e7b423fd517d/sycl/CMakeLists.txt#L531

Also check ARG_PARENT_TARGET is defined and non-empty.

Co-authored-by: Jinsong Ji <jinsong.ji at intel.com>