[docs] Add a shared intersphinx inventory for LLVM projects
Define the documentation sites of the LLVM subprojects in one place so each
project's Sphinx configuration can resolve cross-project links through
intersphinx instead of absolute URLs. The mapping is not used by any project
yet; follow-up changes adopt it. Document the `inv:` link syntax in the Sphinx
quickstart so authors know how to write these links.
Part of #214861
LLM-aided
[docs] Use intersphinx for Clang cross-project links
Configure the Clang documentation with the external project inventories it
references and replace absolute cross-project documentation URLs with
validated intersphinx document and reference roles.
Part of #214861
LLM-aided
[docs] Use intersphinx for LLVM cross-project links
Configure the LLVM documentation with the external project inventories it
references and replace absolute cross-project documentation URLs with
validated intersphinx document and reference roles.
Part of #214861
LLM-aided
[KnownFPClass][NFC] Remove DenormalMode default arguments (#237074)
Removes the `DenormalMode` default arguments from `KnownFPClass`
functions. Currently, all in-tree callers explicitly pass the
`DenormalMode` anyways.
Motivated by ongoing issues with the handling of the `NSZ` flag. The
current proposal for correctly handling the `NSZ` flag is to handle it
the same way that input denormal modes are handled via the
`applyInputDenormalMode` helper. This would require adding an `NSZ`
parameter to almost every `KnownFPClass` function. However, one pattern
I've noticed is that applying the input/output denormal mode inside or
outside of the `KnownFPClass` function makes no difference. So I think
the better way forward would be to move `DenormalMode` handling outside
of the `KnownFPClass` functions completely, and have all `KnownFPClass`
functions assume the IEEE input/output denormal mode. The main exception
to this is `KnownFPClass::fmuladd` since it applies input/output
denormal flushing as an intermediate step.
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LoongArch: Remove clearKillFlags calls on virtual registers (#239804)
Kill flags are no longer permitted on virtual registers, so clearing
them is a no-op. Remove the calls where the register can only be
virtual.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[docs] Use intersphinx for LLVM cross-project links
Configure the LLVM documentation with the external project inventories it
references and replace absolute cross-project documentation URLs with
validated intersphinx document and reference roles.
Part of #214861
LLM-aided
[docs] Add a shared intersphinx inventory for LLVM projects
Define the documentation sites of the LLVM subprojects in one place so each
project's Sphinx configuration can resolve cross-project links through
intersphinx instead of absolute URLs. The mapping is not used by any project
yet; follow-up changes adopt it.
Part of #214861
LLM-aided
[docs] Use intersphinx for Clang cross-project links
Configure the Clang documentation with the external project inventories it
references and replace absolute cross-project documentation URLs with
validated intersphinx document and reference roles.
Part of #214861
LLM-aided
[SystemZ][z/OS] Support naked functions as XPLINK stubs
A function with the `naked` attribute has no prologue or epilogue. On
z/OS XPLINK it maps to a stub function, which has a stub entry marker
instead of the normal entry point marker and has no PPA1.
AsmPrinter:
* For naked functions, emitFunctionEntryLabel() no longer calls
calculatePPA1() and no longer emits the 16-byte entry point marker.
It emits an 8-byte stub marker (eyecatcher 0x00C300C500C500, mark type
C'4'), preceded by 8 bytes of zero padding. The padding keeps the
entry
point at function start + 16, the same offset as for a normal
function.
* emitFunctionBodyEnd() returns early for naked functions. Otherwise it
would use DeferredPPA1.back(), which is the previous function's entry
or an empty vector.
ISel:
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[AMDGPU] Remove write-only RegIdx in ANDMaskResult (NFC) (#239808)
The last read of ANDMaskResult::RegIdx in SIFoldOperands.cpp was removed
on November 6, 2026 in commit 54c4c971aaba65906dc9036e46104e75220e8cbc.
Assisted-by: Antigravity
[CIR] Add support for direct with align in calling convention lowering (#238929)
This change adds the infrastructure for handling arguments that are
classified as `Direct` with a required alignment. These arguments are
passed unmodified but required an `alignstack` attribute. There are no
cases where this is needed for x86, so these changes can only be tested
via unit tests. This support will be needed when AAPCS targets are
supported.
See clang/test/CodeGen/AArch64/args-hfa.c for an example of this
classification in classic codegen.
Assisted-by: Cursor / various models
[lldb] Add LanguageRuntime::EvaluateEntryValue (NFC) (#239813)
DW_OP_entry_value(reg) is the value reg had on entry to the function.
LLDB looks it up in the call site parameters of the caller, but a
language runtime may know it without them. Swift async functions, for
example, receive their async context in a register, and the Swift
runtime's unwind plan makes that context the CFA of the frame. The frame
above an async function in the backtrace is its continuation, not its
caller, so there are no call site parameters to find.
This patch adds a LanguageRuntime hook that DWARFExpression calls before
it searches the caller. The runtime may also consume operations after
the DW_OP_entry_value and evaluate them together with it, when it knows
their combined result but not the entry value alone.
Assisted-by: Claude
[RISCV][veclib] Remove non-existent Sleef_ilogbfx_rvvm2 and Sleef_ldexpfx_rvvm2 entries (#238910)
When compiling for RISC-V with `-vector-library=sleefgnuabi`, LLVM maps
`ilogbf` and `ldexpf` to `Sleef_ilogbfx_rvvm2` and
`Sleef_ldexpfx_rvvm2`.
However, SLEEF does not implement single-precision (`f32`) versions for
`ilogb` and `ldexp` for any architecture. Only the double-precision
`f64` functions exist. Because of this, programs that vectorize these
functions fail to link due to missing symbols.
This patch removes both invalid entries from `VecFuncs.def` and
`RuntimeLibcalls.td` and updates the tests. The 64-bit entries
(`Sleef_ilogbdx_rvvm2` and `Sleef_ldexpdx_rvvm2`) are valid and are kept
intact.
Fixes #235694.
[WebAssembly] Fix comments about _Unwind_GetWasmLPadContext (#239441)
After #222747, code generated by WasmEHPrepare does not access
`__wasm_lpad_context` directly and use `_Unwind_GetWasmLPadContext`, but
it was not reflected in the code comments.
RuntimeLibcalls: Add _Unwind_RaiseException (#239840)
This exists in libunwind and libgcc. BPF is currently emitting a call
to this directly by name.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[lldb] Interrupt the read thread when stopping it
ThreadedCommunication::StopReadThread clears m_read_thread_enabled and
joins the read thread, which checks that flag only once its read
returns. When no data comes, the read returns only when it times out,
after five seconds.
Before lldb reports that a process it launched has exited or that it
detached from the process, it stops the read thread of the process's
terminal. A process that lldb detaches from usually keeps running, and
if it does not write to its terminal, the detach takes five seconds.
StopSTDIOMonitoring closes lldb's own descriptor for the secondary side
of the terminal first, but that ends the read only once the process has
closed its descriptors too. Meanwhile, debugserver or lldb-server exits,
and since the process is not detached yet, ProcessGDBRemote gives it an
exit status, so lldb reports that the process exited.
Interrupt the read after clearing the flag, as SynchronizeWithReadThread
does. A connection reports an interrupt only when no data is pending,
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[Clang] Fix thread sync in amdgpuintrin.h (#239832)
Summary:
This should be doing the same operation the one in HIP does. The
intrinsic doesn't have a fenec associated with it so we emit it
manually.
RISCV: Remove clearKillFlags calls (#239838)
Kill flags on physical registers here are either never set by the time
this code runs or are on reserved or constant registers where they
carry no information.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
AMDGPU: Check address alignment when merging TBUFFER accesses
SILoadStoreOptimizer only checked the alignment of the immediate
offset when merging TBUFFER accesses, ignoring the rest of the
address. This could undo splitting done for alignment and cause
hangs. This is a theoretically stronger fix to piglit failures with
mesa which were previously hidden by conditioning this transform on
relaxed OOB mode.
Check the alignment of the whole address from the memory operand, and
assume each access is already aligned to its component size. Since the
buffer intrinsics don't provide any alignment information, accesses
with 8-bit or 16-bit components can no longer be merged from IR.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Preserve f32 canonicalization through DPP shuffle (#233553)
Teach isCanonicalized to look through amdgcn.update.dpp when all rows
and banks are enabled and bound_ctrl selects zero for out-of-bounds
lanes. The result then consists entirely of source values or canonical
zeros.
This removes redundant canonicalization after shuffling canonical f32
values. An AITER FP8 blockwise quantization kernel compiles to 289
static instructions instead of 329 on gfx950, with unchanged register
counts and scratch usage.
Add positive and negative regression coverage.
[clang][Lex][NFC] Share directory module map processing (#239538)
Share directory cache handling and module map discovery between
`parseModuleMapFile` and `parseAndLoadModuleMapFile`. Use an explicit
`Load` parameter to preserve their distinct processing and cache state
updates.
[Support][mlir][llvm-mc] Support column checks in verify directives (#227570)
Allow an optional 1-based `:<col>` after the line specifier, e.g.
`expected-error@-1:8 {{...}}`, which additionally requires the
diagnostic to be at that column. Directives without a column still match
any column on their line. This also works for MLIR's
`-verify-diagnostics`.
Note that in Clang, `@<file>:<line>` instead refers to a line in another
file, but file-qualified directives are not supported here.
Assisted-by: AI tooling
Pull-Request: https://github.com/llvm/llvm-project/pull/227570
[MemProf] Cache context nodes for callsite stack ids during matching (NFC) (#239822)
updateStackNodes and assignStackNodesPostOrder repeatedly looked up the
context node for each stack id of each call being matched. Save the
nodes in CallContextInfo when they are first looked up and use them
throughout. The stack ids themselves are no longer saved, as they are
available via each node's OrigStackOrAllocId. The sort of calls with the
same last stack id now orders by those ids, and identical sequences are
detected by comparing the node vectors.
This efficiency improvement is leveraged in a follow on PR to avoid
adding another round of context node lookups.
Assisted-by: Gemini
