LLVM/project dbd0122clang/lib/CIR/CodeGen CIRGenExprScalar.cpp, clang/test/CIR/CodeGen choose-expr.cpp

[CIR] Add support the ChooseExpr for scalar (#171882)

Add support the ChooseExpr for scalar expr
DeltaFile
+44-0clang/test/CIR/CodeGen/choose-expr.cpp
+1-2clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+45-22 files

LLVM/project fa5aab1llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU bf16.ll

AMDGPU: Fix selection failure on bf16 inverse sqrt

On !hasBF16TransInsts targets, an illegal rsq would form
and fail to select.
DeltaFile
+820-0llvm/test/CodeGen/AMDGPU/bf16.ll
+3-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+823-12 files

LLVM/project 4dbd16bllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel buffer-load-byte-short.ll llvm.amdgcn.struct.buffer.load.ll

[AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#167798)

This patch adds register bank legalization support for buffer load byte
and short operations in the AMDGPU GlobalISel pipeline.
DeltaFile
+253-0llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
+6-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+3-3llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
+1-1llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
+267-86 files

LLVM/project ff3dcd0llvm/lib/Transforms/IPO GlobalOpt.cpp, llvm/test/Transforms/GlobalOpt disable-globals-aa.ll

[GlobalOpt][profcheck] Mark as `unknown` the branch weights of global shrunk to boolean (#171530)

DeltaFile
+24-4llvm/test/Transforms/GlobalOpt/disable-globals-aa.ll
+0-6llvm/utils/profcheck-xfail.txt
+4-1llvm/lib/Transforms/IPO/GlobalOpt.cpp
+28-113 files

LLVM/project 7ef4f1allvm/docs CMake.rst

update docs for LLVM_BUILD_EXAMPLES

Created using spr 1.3.5-bogner
DeltaFile
+4-3llvm/docs/CMake.rst
+4-31 files

LLVM/project 0570cabmlir/lib/Dialect/Utils IndexingUtils.cpp

[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in IndexingUtils.cpp (NFC)
DeltaFile
+9-9mlir/lib/Dialect/Utils/IndexingUtils.cpp
+9-91 files

LLVM/project f7b69d6clang/test/Sema/AArch64 arm_sve_feature_dependent_sve_AND_sve-bfscale___sme_AND_sve-bfscale_AND_sme2.c

fixup! [AArch64][llvm] Add intrinsics for SVE BFSCALE

Add guarding tests
DeltaFile
+94-0clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve-bfscale___sme_AND_sve-bfscale_AND_sme2.c
+94-01 files

LLVM/project d4f149dclang/test/CodeGen builtin-allow-sanitize-check-lower.c

tweak test

Created using spr 1.3.8-beta.1
DeltaFile
+2-2clang/test/CodeGen/builtin-allow-sanitize-check-lower.c
+2-21 files

LLVM/project 101830eflang/lib/Lower/OpenMP OpenMP.cpp Clauses.cpp, flang/lib/Parser openmp-parsers.cpp openmp-utils.cpp

[flang][OpenMP] Implement COMBINER clause

This adds parsing and lowering of the COMBINER clause. It utilizes the
existing lowering code for combiner-expression to lower the COMBINER
clause as well.
DeltaFile
+67-73flang/lib/Lower/OpenMP/OpenMP.cpp
+88-0flang/test/Parser/OpenMP/declare-reduction-combiner.f90
+31-18flang/lib/Lower/OpenMP/Clauses.cpp
+20-11llvm/include/llvm/Frontend/OpenMP/ClauseT.h
+16-9flang/lib/Parser/openmp-parsers.cpp
+11-5flang/lib/Parser/openmp-utils.cpp
+233-1167 files not shown
+261-12413 files

LLVM/project d7cbc7flldb/source/Plugins/InstrumentationRuntime/TSan InstrumentationRuntimeTSan.cpp, lldb/source/Plugins/InstrumentationRuntime/UBSan InstrumentationRuntimeUBSan.cpp

[lldb][InstrumentationRuntime] Run sanitizer utility expressions as C (#172019)

The utility expressions in the `InstrumentationRuntime` plugins are just
plain C code, but we run them as `ObjC++`. That meant we were doing
redundant work (like looking up decls in the Objective-C runtime). The
sanitizer tests sporadically time out while looking up function symbols
in the Objective-C runtime. This patch switches the expression language
to `C`.

Didn't find a great way of testing this other than looking at the
expression log.

rdar://165656320
DeltaFile
+1-1lldb/source/Plugins/InstrumentationRuntime/UBSan/InstrumentationRuntimeUBSan.cpp
+1-1lldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp
+1-1lldb/source/Plugins/InstrumentationRuntime/Utility/ReportRetriever.cpp
+3-33 files

LLVM/project fabadb6llvm/test/CodeGen/AArch64 sve-intrinsics-fp-arith.ll

fixup! [AArch64][llvm] Add intrinsics for SVE BFSCALE

Add lowering testcase
DeltaFile
+11-0llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll
+11-01 files

LLVM/project 66f2b66lldb/source/Plugins/Process/gdb-remote ProcessGDBRemote.cpp ProcessGDBRemote.h

[lldb][nfc] Change ProcessGDBRemote::ParseMultiMemReadPacket signature (#172020)

Instead of returning an `Expected<vector<...>>` it now returns an Error,
and receives a vector argument to fill in. This will be useful to
support a change were ParseMultiMemReadPacket will be called multiple
times in a loop with the same vector; without this change, we would have
to concatenate vectors and copy memory around.
DeltaFile
+11-14lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+4-4lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
+15-182 files

LLVM/project fcc7cd1llvm/lib/Target/AArch64 AArch64InstrGISel.td, llvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp AArch64RegisterBankInfo.cpp

[AArch64][GlobalISel] Renamed GI nodes describing intrinsics with immediate offsets

In SDAG, nodes that expect an immediate offset end with _I. This is now reflected in GISel for the vector shifts.
DeltaFile
+6-6llvm/lib/Target/AArch64/AArch64InstrGISel.td
+4-4llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+1-1llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+11-113 files

LLVM/project 5ce7f44clang/test/CodeGen builtin-allow-sanitize-check.c, llvm/test/Transforms lower-builtin-allow-check.ll lower-builtin-allow-check-remarks.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+719-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check.ll
+0-719llvm/test/Transforms/lower-builtin-allow-check.ll
+78-0clang/test/CodeGen/builtin-allow-sanitize-check.c
+70-0llvm/test/Transforms/LowerAllowCheck/sanitize-check.ll
+0-36llvm/test/Transforms/lower-builtin-allow-check-remarks.ll
+36-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check-remarks.ll
+903-75516 files not shown
+1,176-76522 files

LLVM/project 6368450llvm/lib/Transforms/Instrumentation LowerAllowCheckPass.cpp, llvm/test/Transforms lower-builtin-allow-check.ll lower-builtin-allow-check-remarks.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+719-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check.ll
+0-719llvm/test/Transforms/lower-builtin-allow-check.ll
+70-0llvm/test/Transforms/LowerAllowCheck/sanitize-check.ll
+0-36llvm/test/Transforms/lower-builtin-allow-check-remarks.ll
+36-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check-remarks.ll
+22-6llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp
+847-7614 files not shown
+866-76410 files

LLVM/project 248a343llvm/lib/Transforms/Instrumentation LowerAllowCheckPass.cpp, llvm/test/Transforms lower-builtin-allow-check.ll lower-builtin-allow-check-remarks.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+0-719llvm/test/Transforms/lower-builtin-allow-check.ll
+719-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check.ll
+70-0llvm/test/Transforms/LowerAllowCheck/sanitize-check.ll
+0-36llvm/test/Transforms/lower-builtin-allow-check-remarks.ll
+36-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check-remarks.ll
+22-6llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp
+847-7614 files not shown
+866-76410 files

LLVM/project c032affllvm/test/Transforms lower-builtin-allow-check.ll lower-builtin-allow-check-remarks.ll, llvm/test/Transforms/LowerAllowCheck lower-builtin-allow-check.ll lower-builtin-allow-check-remarks.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+0-719llvm/test/Transforms/lower-builtin-allow-check.ll
+719-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check.ll
+0-36llvm/test/Transforms/lower-builtin-allow-check-remarks.ll
+36-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check-remarks.ll
+0-3llvm/test/Transforms/lower-builtin-allow-check-pipeline.ll
+3-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check-pipeline.ll
+758-7586 files

LLVM/project 4a28064llvm/test/Transforms lower-builtin-allow-check.ll lower-builtin-allow-check-remarks.ll, llvm/test/Transforms/LowerAllowCheck lower-builtin-allow-check.ll lower-builtin-allow-check-remarks.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+0-719llvm/test/Transforms/lower-builtin-allow-check.ll
+719-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check.ll
+36-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check-remarks.ll
+0-36llvm/test/Transforms/lower-builtin-allow-check-remarks.ll
+0-3llvm/test/Transforms/lower-builtin-allow-check-pipeline.ll
+3-0llvm/test/Transforms/LowerAllowCheck/lower-builtin-allow-check-pipeline.ll
+758-7586 files

LLVM/project 65f03ddmlir/include/mlir/Dialect/PDL/IR PDLOps.td, mlir/include/mlir/IR OpDefinition.h

[mlir][PDL] Relax PDL verification constraints

This commit introduces the following changes:

1. HasParentNotOf: A trait that verifies an operation's parent is not one of
   the specified parent operations.

2. Adds a `nonmaterializable` attribute to `pdl.pattern`
   that indicates a pattern cannot be directly lowered to pdl_interp. This
   allows patterns to contain non-PDL operations (e.g., func.call), and relax
   other constraint for when a pattern requires further transformations before
   materialization. An example, of such transformation is function inlining on
   the example below.

3. Relax parent constraints in PDL. For example, instead of `HasParent<RewriteOp>`
   use `HasParentNotOf<PatternOp>`, as the latter has the same intended meaning within
   PDL, but allows using the ops outside PDL like in func.func.

4. Add error in PDLToPDLInterp pass for nonmaterializable patterns. It's responsibility

    [30 lines not shown]
DeltaFile
+42-0mlir/test/IR/traits.mlir
+19-10mlir/include/mlir/Dialect/PDL/IR/PDLOps.td
+26-0mlir/test/Dialect/PDL/ops.mlir
+21-0mlir/include/mlir/IR/OpDefinition.h
+14-0mlir/test/Conversion/PDLToPDLInterp/invalid.mlir
+10-0mlir/lib/Conversion/PDLToPDLInterp/PDLToPDLInterp.cpp
+132-103 files not shown
+150-129 files

LLVM/project 44c0469llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor/AMDGPU nofpclass-amdgcn-rsq.ll

ValueTracking: Handle amdgcn.rsq intrinsic in computeKnownFPClass (#171837)

We have other target intrinsics already in ValueTracking functions,
and no access to TTI.
DeltaFile
+56-56llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-rsq.ll
+38-0llvm/lib/Analysis/ValueTracking.cpp
+94-562 files

LLVM/project 4960712llvm/lib/Target/AMDGPU SIInstructions.td SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU insert_vector_dynelt.ll extract_vector_dynelt.ll

Reapply "[AMDGPU][SDAG] Add missing cases for SI_INDIRECT_SRC/DST (#170323)"

This reverts commit 4f94941dc101b5d45b53c3efe361cd7b4b916517.
DeltaFile
+5,963-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+3,310-0llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+16-0llvm/lib/Target/AMDGPU/SIInstructions.td
+8-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+9,297-04 files

LLVM/project 55c0e2ellvm/lib/Target/AMDGPU SIInstrInfo.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU/GlobalISel inst-select-insert-vector-elt.mir inst-select-extract-vector-elt.mir

[AMDGPU] Add missing cases for V_INDIRECT_REG_{READ/WRITE}_GPR_IDX and V/S_INDIRECT_REG_WRITE_MOVREL (#171835)

A buildbot failure in https://github.com/llvm/llvm-project/pull/170323
when expensive checks were used highlighted that some of these patterns
were missing.

This patch adds `V_INDIRECT_REG_{READ/WRITE}_GPR_IDX` and
`V/S_INDIRECT_REG_WRITE_MOVREL` for `V6` and `V7` vector sizes.
DeltaFile
+139-0llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
+126-0llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
+24-0llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+8-0llvm/lib/Target/AMDGPU/SIInstructions.td
+297-04 files

LLVM/project ec1bf9cclang/include/clang/AST VTableBuilder.h, clang/lib/AST VTableBuilder.cpp

Use `llvm::SmallVector` instead of `OwningArrayRef` in `VTableLayout`. (#168768)

This simplifies the code by removing the manual optimization for size ==
1, and also gives us an optimization for other small sizes.

Accept a `llvm::SmallVector` by value for the constructor and move it
into the destination, rather than accepting `ArrayRef` that we copy
from. This also lets us not have to construct a reference to the
elements of a `std::initializer_list`, which requires reading the
implementation of the constructor to know whether it's safe.

Also explicitly document that the constructor requires the input indexes
to have a size of at least 1.
DeltaFile
+9-23clang/include/clang/AST/VTableBuilder.h
+13-12clang/lib/AST/VTableBuilder.cpp
+22-352 files

LLVM/project 3ae5f27mlir/include/mlir/Dialect/LLVMIR ROCDLOps.td, mlir/test/Dialect/LLVMIR rocdl.mlir

[ROCDL] Added LDS barrier ops to ROCDL (gfx1250) (#171810)

Added `ds.atomic.barrier.arrive.rtn.b64` and
`ds.atomic.async.barrier.arrive.b64` to ROCDL. These are parts of the
LDS memory barrier concept in GFX1250. Also added alias analysis to
`global/flat` data prefetch ops. Extended rocdl tests.
DeltaFile
+60-4mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+9-0mlir/test/Dialect/LLVMIR/rocdl.mlir
+9-0mlir/test/Target/LLVMIR/rocdl.mlir
+78-43 files

LLVM/project 7a43921llvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-fixed-length-fptrunc.ll

[AArch64][SVE] Fix -msve-vector-bits=256 fixed width vector crash (#171776)

This adds tests for and fixes an issue where v8bf16 ISD::FP_ROUND v8f32
cannot be lowered when -msve-vector-bits=256.
DeltaFile
+36-0llvm/test/CodeGen/AArch64/sve-fixed-length-fptrunc.ll
+1-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+37-12 files

LLVM/project 6009abaclang/include/clang/Basic arm_sve.td, clang/test/CodeGen/AArch64/sve-intrinsics acle_sve_bfscale.c

[AArch64][llvm] Add intrinsics for SVE BFSCALE

Add AArch64 intrinsics for BFloat16 floating-point adjust exponent vectors:

```c
  svbfloat16_t svscale[_bf16]_m (svbool_t pg, svbfloat16_t zdn, svint16_t zm);
  svbfloat16_t svscale[_bf16]_x (svbool_t pg, svbfloat16_t zdn, svint16_t zm);
  svbfloat16_t svscale[_bf16]_z (svbool_t pg, svbfloat16_t zdn, svint16_t zm);
  svbfloat16_t svscale[_n_bf16]_m (svbool_t pg, svbfloat16_t zdn, int16_t zm);
  svbfloat16_t svscale[_n_bf16]_x (svbool_t pg, svbfloat16_t zdn, int16_t zm);
  svbfloat16_t svscale[_n_bf16]_z (svbool_t pg, svbfloat16_t zdn, int16_t zm);
```
DeltaFile
+140-0clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
+10-0clang/include/clang/Basic/arm_sve.td
+7-3llvm/lib/Target/AArch64/SVEInstrFormats.td
+1-1llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+1-1llvm/lib/Target/AArch64/AArch64InstrInfo.td
+159-55 files

LLVM/project 2436d9bllvm/lib/Support/rpmalloc rpmalloc.c malloc.c, llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp SIInsertWaitcnts.cpp

Merge branch 'main' into users/jmmartinez/reapply/fix/extract_insert_vector_dynelt_with_O0-1
DeltaFile
+3,996-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+724-724llvm/lib/Support/rpmalloc/malloc.c
+677-36mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+347-304llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+637-0mlir/test/Dialect/LLVMIR/nvvm-mma-sparse-blockscale.mlir
+329-289llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+6,710-5,349772 files not shown
+27,890-13,148778 files

LLVM/project 7345233lldb/include/lldb/Host Terminal.h, lldb/include/lldb/Host/common DiagnosticsRendering.h

[lldb] improve the heuristics for checking if a terminal supports Unicode (#171832)

This patch improves the way lldb checks if the terminal it's opened in
(if any) supports Unicode or not.

On POSIX systems, we check if `LANG` contains `UTF-8`.

On Windows, we always return `true` since we use the `WriteToConsoleW`
api.

This is a relanding of https://github.com/llvm/llvm-project/pull/168603.

The tests failed because the bots support Unicode but the tests expect
ASCII. To avoid different outputs depending on the environment the tests
are running in, this patch always force ASCII in the tests.
DeltaFile
+18-1lldb/include/lldb/Host/common/DiagnosticsRendering.h
+17-0lldb/source/Host/common/Terminal.cpp
+7-7lldb/test/Shell/Commands/command-expr-diagnostics.test
+6-6lldb/test/Shell/Commands/command-options.test
+12-0lldb/include/lldb/Host/Terminal.h
+5-6lldb/source/Host/common/DiagnosticsRendering.cpp
+65-202 files not shown
+70-258 files

LLVM/project 95e6d23llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-shuffle-combining-avx2.ll

[X86] combineHorizOpWithShuffle - ensure we handle undef elements from widened shuffle (#172014)

Since #170838 we no longer canonicalise away whole-lane shuffles of
horizontal ops, so we need to better handle cases where widened shuffle
masks might still contain undefs.

Fixes #172010
DeltaFile
+33-0llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
+5-3llvm/lib/Target/X86/X86ISelLowering.cpp
+38-32 files

LLVM/project 568ce76mlir/include/mlir/Dialect/LLVMIR/Transforms UseDefaultVisibilityPass.h Passes.td, mlir/lib/Dialect/LLVMIR/Transforms UseDefaultVisibilityPass.cpp CMakeLists.txt

[MLIR][LLVM] Add pass to update ops with default visibility (#171727)

To support the `-fvisibility=...` option in Flang, we need a pass to
rewrite all the global definitions in the LLVM dialect that have the
default visibility to have the specified visibility. This change adds
such a pass.

Note that I did not add an option for `visiblity=default`; I believe
this makes sense for compiler drivers since users may want to tack an
option on at the end of a compile line to override earlier options, but
I don't think it makes sense for this pass to accept
`visibility=default`--it would just be an early exit IIUC.
DeltaFile
+179-0mlir/test/Dialect/LLVMIR/use-default-visibility.mlir
+54-0mlir/lib/Dialect/LLVMIR/Transforms/UseDefaultVisibilityPass.cpp
+25-0mlir/include/mlir/Dialect/LLVMIR/Transforms/UseDefaultVisibilityPass.h
+20-1mlir/include/mlir/Dialect/LLVMIR/Transforms/Passes.td
+1-0mlir/lib/Dialect/LLVMIR/Transforms/CMakeLists.txt
+279-15 files