LLVM/project ed2f22cmlir/lib/Bindings/Python IRModule.h IRAffine.cpp, mlir/test/python/ir affine_expr.py builtin_types.py

remove "isinstance" from core bindings
DeltaFile
+8-8mlir/test/python/ir/affine_expr.py
+0-12mlir/lib/Bindings/Python/IRModule.h
+5-5mlir/test/python/ir/builtin_types.py
+4-4mlir/test/python/ir/attributes.py
+0-6mlir/lib/Bindings/Python/IRAffine.cpp
+0-6mlir/lib/Bindings/Python/IRCore.cpp
+17-416 files

LLVM/project 3c581c2llvm/lib/ProfileData MemProfSummary.cpp, llvm/test/Transforms/PGOProfile memprof_max_cold_threshold.test memprof.ll

Move summary print into another patch
DeltaFile
+6-16llvm/test/tools/llvm-profdata/memprof-yaml.test
+0-10llvm/tools/llvm-profdata/llvm-profdata.cpp
+1-1llvm/test/Transforms/PGOProfile/memprof_max_cold_threshold.test
+1-1llvm/lib/ProfileData/MemProfSummary.cpp
+1-1llvm/test/Transforms/PGOProfile/memprof.ll
+9-295 files

LLVM/project d22d2e3mlir/lib/Bytecode/Reader BytecodeReader.cpp

[mlir][bytecode] fix on macos after #172901 (#173084)

`uint64_t` != `size_t` on macos (use `uint64_t` to match other uses in
this impl)
DeltaFile
+3-2mlir/lib/Bytecode/Reader/BytecodeReader.cpp
+3-21 files

LLVM/project 175504dllvm/tools/llvm-profdata llvm-profdata.cpp

excessive logs
DeltaFile
+0-3llvm/tools/llvm-profdata/llvm-profdata.cpp
+0-31 files

LLVM/project ac387ceclang/lib/Sema SemaHLSL.cpp

[HLSL][NFC] Add assert ensuring divide by zero can't happen (#173072)

Add assert ensuring divide by zero can't happen in the case we are
initializing an incomplete array type object.
DeltaFile
+4-1clang/lib/Sema/SemaHLSL.cpp
+4-11 files

LLVM/project 0f0281dllvm/include/llvm/ProfileData MemProfSummary.h, llvm/lib/ProfileData MemProfSummary.cpp IndexedMemProfData.cpp

[llvm-profdata][StaticDataLayout] Print summary of data access profile
in llvm-profdata
DeltaFile
+20-10llvm/test/tools/llvm-profdata/memprof-yaml.test
+21-1llvm/lib/ProfileData/MemProfSummary.cpp
+11-9llvm/lib/ProfileData/IndexedMemProfData.cpp
+13-1llvm/include/llvm/ProfileData/MemProfSummary.h
+3-0llvm/tools/llvm-profdata/llvm-profdata.cpp
+1-1llvm/test/Transforms/PGOProfile/memprof.ll
+69-221 files not shown
+70-237 files

LLVM/project 023ccc3utils/bazel extensions.bzl

[bazel] Add another libpfm url (#173083)

This is pointing to the same thing but without this subdomain which is
currently down. I'm not sure that is temporary or not but I think this
is the more canonical URL
DeltaFile
+1-0utils/bazel/extensions.bzl
+1-01 files

LLVM/project feb98f6mlir/lib/Bytecode/Reader BytecodeReader.cpp

[mlir][bytecode] fix on macos after #172901

`uint64_t` != `size_t` on macos (use `uint64_t` to match other uses in this impl)
DeltaFile
+3-2mlir/lib/Bytecode/Reader/BytecodeReader.cpp
+3-21 files

LLVM/project 42dc78fllvm/lib/CodeGen/GlobalISel Utils.cpp, llvm/test/CodeGen/AArch64/GlobalISel combine-canonicalize-fcmp.mir combine-cannonicalize-fcmp.mir

[GlobalISel] Fix FCMP constant folding in presence trunc/zext/sext chain (#171878)

The instruction combine ``canonicalize_fcmp`` tries to fold constant
values in fcmp, however, it fails when the source defs have different FP
types. This occurs because it uses
``getFConstantVRegValWithLookThrough`` to get the constants value def,
even through trunc, zext, or sext.

Related to #171856
DeltaFile
+133-0llvm/test/CodeGen/AArch64/GlobalISel/combine-canonicalize-fcmp.mir
+0-119llvm/test/CodeGen/AArch64/GlobalISel/combine-cannonicalize-fcmp.mir
+4-2llvm/lib/CodeGen/GlobalISel/Utils.cpp
+137-1213 files

LLVM/project b6c4590clang/test/CodeGen/X86 avx512vlcd-builtins.c

[clang] Disable avx512vlcd test on Arm 32-bit

When clang is compiled with a more recent clang
(that includes 5d7f324614d7a5c0de89cfe8295a9b2b7ef5d073),
the code produced enforces 64-bit alignment on a type
that is used during this test.

For reasons not known yet, that type is not 64-bit aligned
though you would normally expect it to be.

See https://github.com/llvm/llvm-project/issues/172994.

I would xfail this but I'm not 100% sure that it always fails.
Memory layout may make it pass sometimes.
DeltaFile
+2-0clang/test/CodeGen/X86/avx512vlcd-builtins.c
+2-01 files

LLVM/project 5897f27llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU promote-alloca-vector-dynamic-idx-bitcasts-llc.ll promote-alloca-vector-dynamic-idx-bitcasts.ll

[AMDGPU] In promote-alloca, if index is dynamic, sandwich load with bitcasts to reduce excessive codegen (#171253)

Investigation revealed that scalarized copy results in a long chain of
extract/insert elements which can explode in generated temps in the
AMDGPU backend as there is no efficient representation for extracting
subvector with dynamic index. Using identity bitcasts can reduce the
number of extract/insert elements down to 1 and produce much smaller,
efficient generated code.

Credit: ruiling
DeltaFile
+497-0llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
+315-0llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts.ll
+31-0llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+843-03 files

LLVM/project 3f3a57cutils/bazel/llvm-project-overlay/llvm BUILD.bazel

[bazel] Port 6c51c17eecd8a19813d28b293590fc7197137594 (#173082)

DeltaFile
+1-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+1-01 files

LLVM/project f34d068clang/test/CodeGen arm-bf16-convert-intrinsics.c, llvm/lib/Transforms/Scalar SROA.cpp

[SROA] Refactor rewritePartition alloca type selection process (#167771)

This PR does two things:
1. Refactor the rewritePartition type selection process to move the
logic inside of a lambda. Previously the selection process would make
use of a mutable `SliceTy`. Each phase of the type selection would do
something like `if (!SliceTy) { // try to set sliceTy` }. But you also
have `if (!SliceTy && <condition>)` and `if (!SliceTy || <condition>)`.
I think this style makes the priority mechanism confusing. The new way I
wrote the selection process is equivalent (except for the second
contribution of this PR), and works by checking a condition, followed by
returning the selected type right away. I think it makes the priority
clearer.

2. What motivated the rewrite is that there are some cases with small
aggregate allocas that have mixed type loads and stores that SROA fails
to promote.

For example, given:

    [33 lines not shown]
DeltaFile
+98-45llvm/lib/Transforms/Scalar/SROA.cpp
+73-0llvm/test/Transforms/SROA/prefer-integer-partition.ll
+20-23clang/test/CodeGen/arm-bf16-convert-intrinsics.c
+191-683 files

LLVM/project f2192b0llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-shuffle-combining-avx2.ll

[X86] combineConcatVectorOps - fix typo where we were comparing the same subvector types (#173075)

Make it clearer that the subvector sources of a concat(extend_vector_inreg(x),extend_vector_inreg(y)) pair must have the same type.

Fixes #173030
DeltaFile
+14-12llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
+4-4llvm/lib/Target/X86/X86ISelLowering.cpp
+18-162 files

LLVM/project 56c0173llvm CMakeLists.txt

Revert "[llvm][clang] Enable IO sandbox for assert builds" (#173074)

Reverts llvm/llvm-project#171935.

The sandbox infrastructure was (incorrectly) only implemented for `clang
-cc1` jobs created by the driver in llvm/llvm-project#165350. Direct
`clang -cc1` invocations had the sandbox disabled. This reduced the
coverage of our test suite and lead to sandbox violations for people
using asserts-enabled Clang.

This PR temporarily disables the sandbox for asserts builds, so that we
have time to investigate and fix sandbox violations for direct `clang
-cc1` commands and re-enable for asserts builds at a later time.
DeltaFile
+1-1llvm/CMakeLists.txt
+1-11 files

LLVM/project 22d2420mlir/python/mlir/dialects arith.py memref.py, mlir/python/mlir/dialects/linalg/opdsl/lang emitter.py

[mlir][Python] use canonical Python isinstance instead of Type.isinstance
DeltaFile
+33-68mlir/python/mlir/dialects/linalg/opdsl/lang/emitter.py
+2-22mlir/python/mlir/dialects/arith.py
+11-4mlir/python/mlir/dialects/memref.py
+3-3mlir/test/python/dialects/arith_dialect.py
+1-1mlir/test/python/ir/auto_location.py
+50-985 files

LLVM/project 1b4eed4llvm/test/tools/llvm-ml extern.asm

[llvm-ml] Add a test for `extrn` (#173059)

This adds a test for the change from https://reviews.llvm.org/D140679.
DeltaFile
+7-0llvm/test/tools/llvm-ml/extern.asm
+7-01 files

LLVM/project fcd7026mlir/include/mlir/Dialect/OpenACC OpenACCOps.td, mlir/lib/Dialect/OpenACC/IR OpenACC.cpp

[acc] add RegionBranchOpInterface to acc.loop (#172940)

Add RegionBranchOpInterface to acc.loop so that dataflow analysis can
propagate properly.
DeltaFile
+88-0mlir/test/Dialect/OpenACC/region-branchop-interface.mlir
+20-1mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+1-0mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
+109-13 files

LLVM/project 88799cdmlir/include/mlir/Bindings/Python Globals.h, mlir/lib/Bindings/Python Globals.cpp

try fix windows badcast
DeltaFile
+9-9mlir/python/CMakeLists.txt
+1-4mlir/include/mlir/Bindings/Python/Globals.h
+5-0mlir/lib/Bindings/Python/Globals.cpp
+15-133 files

LLVM/project fefda86llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVSubtarget.cpp, llvm/test/CodeGen/RISCV bigendian-load-store.ll bigendian-f64-call.ll

[RISCV] Handle codegen for Big Endian (#172668)

- Handle BE in RISCVSubtarget
- Handle riscv big-endian f64
- Handle loads/stores
- Add tests for LE vs BE
DeltaFile
+435-0llvm/test/CodeGen/RISCV/bigendian-load-store.ll
+94-0llvm/test/CodeGen/RISCV/bigendian-f64-call.ll
+78-0llvm/test/CodeGen/RISCV/bigendian-double-bitmanip.ll
+64-14llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-1llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+3-0llvm/lib/Target/RISCV/RISCVSubtarget.h
+676-156 files

LLVM/project 4012c1flldb/test/API/lang/c/conflicting-symbol TestConflictingSymbol.py, lldb/test/API/lang/c/conflicting-symbol/One OneConstant.c

[lldb][test] Avoid out-of-bounds reads in TestConflictingSymbol.py (#172792)

Generic data variables are considered to be of the type `void *&`, see
`ClangExpressionDeclMap::AddOneGenericVariable()`. On 64-bit platforms
(e.g. AArch64), this type is 8 bytes long, while the
`conflicting_symbol` variables are defined as `int`, which is typically
4 bytes. `test_conflicting_symbols` could fail if the next 4 bytes in the
memory after any of the variables are not zero. This can be reproduced
by adding a variable with a non-zero value after `conflicting_symbol`:
```
--- a/lldb/test/API/lang/c/conflicting-symbol/One/OneConstant.c
+++ b/lldb/test/API/lang/c/conflicting-symbol/One/OneConstant.c
@@ -1 +1,2 @@
 int __attribute__ ((visibility("hidden"))) conflicting_symbol = 11111;
+int guard = 1;
```

In this case, the test fails with:
```

    [10 lines not shown]
DeltaFile
+7-5lldb/test/API/lang/c/conflicting-symbol/TestConflictingSymbol.py
+1-1lldb/test/API/lang/c/conflicting-symbol/One/OneConstant.c
+1-1lldb/test/API/lang/c/conflicting-symbol/Two/TwoConstant.c
+9-73 files

LLVM/project f0aa99cllvm/include/llvm/Analysis DXILResource.h, llvm/lib/Target/DirectX DXILMemIntrinsics.cpp

[DirectX] Resources and simple GEP traversal in DXILMemIntrinsics

Walk through GEPs and recognize resource target extension types when
trying to infer the underlying types of memory intrinsics.
DeltaFile
+106-0llvm/test/CodeGen/DirectX/MemIntrinsics/memcpy-pointee.ll
+52-13llvm/lib/Target/DirectX/DXILMemIntrinsics.cpp
+8-0llvm/include/llvm/Analysis/DXILResource.h
+166-133 files

LLVM/project d7b854bflang/test/Fir/CUDA cuda-code-gen.mlir cuda-gpu-launch-func.mlir, flang/test/Transforms tbaa-for-common-vars.fir tbaa.fir

test changes
DeltaFile
+29-48mlir/test/Dialect/LLVMIR/layout.mlir
+9-9flang/test/Fir/CUDA/cuda-code-gen.mlir
+9-9flang/test/Transforms/tbaa-for-common-vars.fir
+6-6mlir/test/Target/LLVMIR/Import/data-layout.ll
+6-6flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir
+5-5flang/test/Transforms/tbaa.fir
+64-8349 files not shown
+136-15555 files

LLVM/project 11fefb1mlir/include/mlir/Dialect/LLVMIR LLVMTypes.h LLVMTypes.td, mlir/lib/Conversion/PtrToLLVM PtrToLLVM.cpp

Source changes
DeltaFile
+30-143mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
+34-1mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
+0-35mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
+22-1mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+9-5mlir/lib/Conversion/PtrToLLVM/PtrToLLVM.cpp
+3-5mlir/lib/Target/LLVMIR/DataLayoutImporter.cpp
+98-1907 files not shown
+113-19913 files

LLVM/project 6e44ac9mlir/include/mlir/IR OpImplementation.h, mlir/lib/IR AsmPrinter.cpp

[mlir] Add dialect hooks for registering custom type and attribute alias printers

This patch introduces a mechanism for dialects to register custom alias printers
for types and attributes via the `OpAsmDialectInterface`. This allows dialects
to provide alternative printed representations for types and attributes based
on their TypeID, including types/attributes from other dialects.

The new `registerAttrAliasPrinter` and `registerTypeAliasPrinter` virtual
methods accept callbacks that register printers for specific TypeIDs. When
printing, these custom printers are invoked in registration order, and the
first one to produce output is used.

The precedence for alias resolution is:
1. Explicit type/attribute aliases returned by `getAlias`
2. Dialect-specific alias printers registered via the new hooks
3. Default type/attribute printers

Signed-off-by: Fabian Mora <fabian.mora-cordero at amd.com>
DeltaFile
+187-18mlir/lib/IR/AsmPrinter.cpp
+48-0mlir/test/lib/Dialect/Test/TestDialectInterfaces.cpp
+29-3mlir/include/mlir/IR/OpImplementation.h
+14-0mlir/test/IR/print-attr-type-dialect-aliases.mlir
+278-214 files

LLVM/project b184f00llvm/test/CodeGen/X86 vector-shuffle-combining-avx2.ll

[X86] Add test case for #173030 (#173060)

DeltaFile
+68-0llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
+68-01 files

LLVM/project 3ba3410llvm CMakeLists.txt

Revert "[llvm][clang] Enable IO sandbox for assert builds (#171935)"

This reverts commit f83de973a5daab2181442071d34758a0b413b6f2.
DeltaFile
+1-1llvm/CMakeLists.txt
+1-11 files

LLVM/project d921b54llvm/lib/Target/Sparc/MCTargetDesc SparcInstPrinter.cpp, llvm/lib/Target/WebAssembly/AsmParser WebAssemblyAsmTypeCheck.cpp

[LLVM][Target] Use ListSeparator in lib/Target (#172919)

Use `ListSeparator` in various places in Target.
DeltaFile
+6-8llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
+4-7llvm/lib/Target/X86/X86DomainReassignment.cpp
+4-5llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
+14-203 files

LLVM/project e26837amlir/python CMakeLists.txt

try fix windows badcast
DeltaFile
+9-9mlir/python/CMakeLists.txt
+9-91 files

LLVM/project f030054llvm/test/CodeGen/X86 coalesce-commutative-tied-def-subreg.mir

[RegisterCoalescer] Fix failing coalescer test for commuting instructions (#173043)

Fix for the failing tests introduced in #169031
DeltaFile
+42-28llvm/test/CodeGen/X86/coalesce-commutative-tied-def-subreg.mir
+42-281 files