LLVM/project 7d292a5lldb/source/Plugins/Process/gdb-remote GDBRemoteCommunicationServerLLGS.cpp GDBRemoteCommunicationServerLLGS.h

[lldb-server][NFC] Factor out code handling breakpoint packets

This commit extracts the code handling breakpoint packets into a helper
function that can be used by a future implementation of the
MultiBreakpointPacket.

It is meant to be purely NFC.

There are two functions handling breakpoint packets (`handle_Z`
and `handle_z`) with a lot of repeated code. This commit did not attempt
to merge the two, as that would make the diff much larger due to subtle
differences in the error message produced by the two. The only
deduplication done is in the code processing a GDBStoppointType, where a
helper struct (`BreakpointKind`) and function (`std::optional<BreakpointKind> getBreakpointKind(GDBStoppointType stoppoint_type)`) was created.

https://github.com/llvm/llvm-project/pull/192910
DeltaFile
+147-105lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+28-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
+175-1052 files

LLVM/project bb07440lldb/test/API/functionalities/multi-breakpoint TestMultiBreakpoint.py main.c, lldb/tools/debugserver/source RNBRemote.cpp JSON.h

[debugserver] Implement MultiBreakpoint

This implements the packet as described in https://github.com/llvm/llvm-project/pull/192910
DeltaFile
+196-0lldb/test/API/functionalities/multi-breakpoint/TestMultiBreakpoint.py
+69-0lldb/tools/debugserver/source/RNBRemote.cpp
+7-0lldb/test/API/functionalities/multi-breakpoint/main.c
+3-0lldb/test/API/functionalities/multi-breakpoint/Makefile
+2-0lldb/tools/debugserver/source/JSON.h
+2-0lldb/tools/debugserver/source/RNBRemote.h
+279-06 files

LLVM/project 2f5fe2cclang/include/clang/StaticAnalyzer/Core/PathSensitive ExprEngine.h

[analyzer] Fix typo in ExprEngine.h (#193535)

While I was studying the code base I have spotted some typo in the
`ExprEngine.h` in this PR I have fixed these typos.
DeltaFile
+13-13clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
+13-131 files

LLVM/project 19d9772llvm/lib/Target/SystemZ SystemZTDC.cpp, llvm/test/CodeGen/SystemZ tdc-08.ll

[LLVM][CodeGen] Ensure SystemZTDCPass::convertFCmp only accepts scalar floating point types. (#193738)

Fixes https://lab.llvm.org/buildbot/#/builders/117/builds/18799
DeltaFile
+53-0llvm/test/CodeGen/SystemZ/tdc-08.ll
+2-2llvm/lib/Target/SystemZ/SystemZTDC.cpp
+55-22 files

LLVM/project e9ef76dclang/include/clang/Analysis/Analyses/LifetimeSafety Loans.h

[LifetimeSafety] Simplify `AccessPath` root `PointerUnion` (#193520)

Stores generic `Expr*` and `Decl*` in `AccessPath`'s `PointerUnion` to
avoid problems where we do not have enough available low bits when more
template parameters are added.
DeltaFile
+12-11clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h
+12-111 files

LLVM/project 47523f7clang/www cxx_status.html

[clang][docs] open details of C++{17,14,11} implementation by default (#193141)

Before
https://github.com/llvm/llvm-project/commit/b9c0e590f1fd4ea37da5c2b9b78d8e715c885f56
switched the C++ status page to a reverse chronological order, it made
sense to avoid wasting vertical space for already-implemented standards.
After that switch, it would make sense however to unfold them by
default.

This is for example why I had opened #61426, because CRTL+F did not show
P0588 on the status page[^1]. But not just for this paper, I think the
ease of finding papers is a good argument for folding out those tables.

[^1]: together with the fact that other status pages
([example](https://en.cppreference.com/cpp/compiler_support/20)) have
sorted this paper under C++20 rather than C++11.
DeltaFile
+3-3clang/www/cxx_status.html
+3-31 files

LLVM/project 72b0618clang/docs InternalsManual.rst

[clang][docs] fix typo; NFC (#193648)
DeltaFile
+1-1clang/docs/InternalsManual.rst
+1-11 files

LLVM/project c32d2d1flang/docs Overview.md, flang/lib/Optimizer/Passes Pipelines.cpp CMakeLists.txt

[flang] Add the MLIR pass pipelines for dumping (#183144)

The flang driver never registered passes in the MLIR pass registry, so
--mlir-print-ir-before=<pass> always failed with `Cannot find option`.

This commit adds pass registration calls before CLI option parsing in
the -mmlir handler such that all ~30 pipeline passes are now selectable.
DeltaFile
+30-0flang/lib/Optimizer/Passes/Pipelines.cpp
+15-0flang/test/Fir/print-ir-pass.fir
+13-0flang/test/Driver/mmlir-print-ir.f90
+4-7flang/tools/fir-opt/fir-opt.cpp
+8-1flang/docs/Overview.md
+5-0flang/lib/Optimizer/Passes/CMakeLists.txt
+75-84 files not shown
+84-810 files

LLVM/project a88516blldb/test/API/functionalities/data-formatter/bytecode-synthetic TestBytecodeSynthetic.py, lldb/test/API/lang/objc/module-import-log TestClangModuleImportLog.py

[lldb/test] Update remaining `filecheck` call sites to use `filecheck_log` (NFC) (#193654)
DeltaFile
+1-1lldb/test/API/functionalities/data-formatter/bytecode-synthetic/TestBytecodeSynthetic.py
+1-1lldb/test/API/lang/objc/module-import-log/TestClangModuleImportLog.py
+2-22 files

LLVM/project f6c4280libc/docs CMakeLists.txt, libc/docs/headers index.rst

[libc][docs] Add poll.h POSIX header documentation (#122006) (#193734)

Add poll.h implementation-status docs to llvm-libc.
DeltaFile
+27-0libc/utils/docgen/poll.yaml
+1-0libc/docs/CMakeLists.txt
+1-0libc/docs/headers/index.rst
+29-03 files

LLVM/project 8212cablldb/test/API/functionalities/data-formatter/data-formatter-objc TestDataFormatterObjCNSBundle.py

[lldb/test] Relax NSBundle formatter test for Darwin embedded platforms (#193659)

Some Foundation APIs have been migrated from Objective-C to Swift while
maintaining backward compatibility. For instance, that can cause
`NSBundle` created via `initWithURL:` to format without the `@"..."`
prefix.

Match the path string without requiring the @ prefix so the test passes
with both the ObjC and Swift implementations

rdar://175394563

Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
DeltaFile
+1-1lldb/test/API/functionalities/data-formatter/data-formatter-objc/TestDataFormatterObjCNSBundle.py
+1-11 files

LLVM/project 68075d1llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp

Update llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Co-authored-by: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
DeltaFile
+1-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+1-01 files

LLVM/project 1b9c1bcllvm/lib/Target/SPIRV SPIRVISelLowering.cpp

Review: fix warning-as-error
DeltaFile
+4-4llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+4-41 files

LLVM/project fca14f7llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp

Update llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Co-authored-by: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
DeltaFile
+1-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+1-01 files

LLVM/project 867ac2cllvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp

Review: Combine memory semantics and storage class
DeltaFile
+6-2llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+6-21 files

LLVM/project be4adbfllvm/include/llvm/IR IntrinsicsSPIRV.td, llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp SPIRVISelLowering.cpp

Review: use spv_atomic_load/store intrinsics
DeltaFile
+36-29llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+36-15llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+27-10llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+4-2llvm/include/llvm/IR/IntrinsicsSPIRV.td
+103-564 files

LLVM/project e8e7b2bllvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing alias-load-store-atomic.ll

Review: Change of course, do not emit spv_intel_memory_access_aliasing for atomic load/store
DeltaFile
+1-7llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+1-4llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-load-store-atomic.ll
+2-112 files

LLVM/project eefa5d3llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp

Review: mrsidims remarks
DeltaFile
+12-10llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+12-101 files

LLVM/project 7e3de98llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing alias-load-store-atomic.ll

Review atomic load/store start working on the memory_aliasing info
DeltaFile
+33-7llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-load-store-atomic.ll
+7-2llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+40-92 files

LLVM/project 9e557d0llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp SPIRVTypeInst.cpp, llvm/test/CodeGen/SPIRV/transcoding store-atomic.ll load-atomic.ll

[SPIRV] Lower load/store atomic to OpAtomicLoad/OpAtomicStore
DeltaFile
+96-7llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+19-26llvm/test/CodeGen/SPIRV/transcoding/store-atomic.ll
+19-25llvm/test/CodeGen/SPIRV/transcoding/load-atomic.ll
+41-0llvm/test/CodeGen/SPIRV/transcoding/atomic-load-store-unsupported.ll
+18-0llvm/lib/Target/SPIRV/SPIRVTypeInst.cpp
+8-0llvm/lib/Target/SPIRV/SPIRVTypeInst.h
+201-583 files not shown
+211-669 files

LLVM/project a62c46dllvm/lib/Target/SPIRV SPIRVTypeInst.cpp SPIRVTypeInst.h

Review: simplify isTypeFloat function
DeltaFile
+2-14llvm/lib/Target/SPIRV/SPIRVTypeInst.cpp
+2-6llvm/lib/Target/SPIRV/SPIRVTypeInst.h
+4-202 files

LLVM/project 0ff393fllvm/include/llvm/Target RegisterTargetPassConfigCallback.h

[NFC][Target] Fixed rule-of-three for RegisterTargetPassConfigCallback class (#193470)

- This PR fixes ```RegisterTargetPassConfigCallback``` classes default
member functions as per rule of three
(https://en.cppreference.com/cpp/language/rule_of_three)
DeltaFile
+4-0llvm/include/llvm/Target/RegisterTargetPassConfigCallback.h
+4-01 files

LLVM/project ce58a29flang/include/flang/Optimizer/Dialect FIROps.td, flang/lib/Optimizer/CodeGen CodeGen.cpp

[flang][debug] generate llvm.fake.use for arguments at -g and O0
DeltaFile
+56-0flang/test/Transforms/debug-fake-use.fir
+27-14flang/lib/Optimizer/CodeGen/CodeGen.cpp
+20-1flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
+12-0flang/test/Fir/fake_use-codegen.fir
+10-0flang/include/flang/Optimizer/Dialect/FIROps.td
+8-0flang/lib/Optimizer/Passes/Pipelines.cpp
+133-151 files not shown
+137-177 files

LLVM/project ff125aellvm/lib/Analysis ConstantFolding.cpp, llvm/test/Transforms/InstCombine constant-fold-nextafter.ll constant-fold-nexttoward-fp128.ll

[ConstantFolding] Constant fold nextafter and nexttoward (#168794)

Closes #74368.

This patch enables us to constant fold `nextafter` and `nexttoward` as
long as we know that `errno` won't be written. In the latter case, we
should keep the function call so the programmer can observe the side
effect.
DeltaFile
+300-0llvm/test/Transforms/InstCombine/constant-fold-nextafter.ll
+291-0llvm/test/Transforms/InstCombine/constant-fold-nexttoward-fp128.ll
+127-0llvm/test/Transforms/InstCombine/constant-fold-nexttoward-x86-fp80.ll
+127-0llvm/test/Transforms/InstCombine/constant-fold-nexttoward-ppc-fp128.ll
+57-1llvm/lib/Analysis/ConstantFolding.cpp
+902-15 files

LLVM/project 2a51267llvm/lib/Target/AMDGPU SIRegisterInfo.cpp, llvm/test/CodeGen/AMDGPU eliminate-frame-index-scalar-scc-clobber.mir

[AMDGPU] Fix s_cselect scc clobber issue (#193498)

The frame index elimination e.g., for S_CSELECT_B32 (which reads SCC)
uses the SCC-preserving S_ADDC_U32+S_BITCMP1_B32+S_BITSET0_B32 sequence
instead of a plain S_ADD_I32, even when the regscavenger reports SCC as
unused due to its backward scan removing the SCC def from the live set.

Root cause: scavengeRegisterBackwards scans backward from MI and calls
LiveRegUnits::stepBackward() on each instruction. stepBackward removes
defs from the live set. When it processes the S_AND_B64 (which defines
SCC) immediately before S_CSELECT_B32, SCC is removed from LiveUnits.
This makes RS->isRegUsed(SCC) return false, so NeedSaveSCC was false
before the fix.

The fix adds MI->readsRegister(SCC) to the NeedSaveSCC condition so the
SCC-preserving ADDC+BITCMP1+BITSET0 sequence is always used when MI
reads SCC, regardless of what the regscavenger reports.

- commit message and the test are generated by claude
DeltaFile
+114-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
+3-2llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+117-22 files

LLVM/project 49dad16flang/include/flang/Support LangOptions.def, flang/lib/Frontend CompilerInvocation.cpp

[flang] Ignore -fno-realloc-lhs for polymorphic allocatable LHS with warning (#192697)

When -fno-realloc-lhs is specified and the LHS of an assignment is a
polymorphic allocatable (class(*) or class(T)), reallocation semantics
are required by the Fortran 2003 standard for dynamic type tracking and
cannot be safely skipped. Previously, the compiler generated invalid FIR
in such cases (type mismatch between i32 and
!fir.class<!fir.heap<none>>), causing a compilation error.

With this change, when -fno-realloc-lhs is in effect and a polymorphic
allocatable LHS is detected, the compiler emits a warning that the
option is being ignored for that assignment and proceeds with
reallocation semantics.
DeltaFile
+26-0flang/test/Semantics/no-realloc-lhs-poly.f90
+13-5flang/lib/Lower/Bridge.cpp
+15-1flang/test/Lower/reallocate-lhs.f90
+4-0flang/include/flang/Support/LangOptions.def
+3-1flang/lib/Frontend/CompilerInvocation.cpp
+3-0flang/lib/Semantics/expression.cpp
+64-72 files not shown
+67-88 files

LLVM/project 0d6652allvm/utils/lit/tests progress-bar.py

[lit] Fix `progress-bar.py` flaky test

The `lit` progress-bar test was checking for exact progress-bar text
like `0.. 10.. 20.. 30.. 40..`, but that output is not stable from run
to run.

The progress bar is based on timing estimates, including saved timings
from earlier runs, so small timing differences can change which numbers
get printed.

That made the test flaky: FileCheck could match the wrong Testing: line
and then fail later, even though the actual test failures were correct.

Relax the test to verify ordering instead of exact progress-bar
contents. The updated checks assert that the test header is printed, that
each failing test result is separated by a Testing: progress-bar line,
and that the final failed-tests summary lists all expected tests in order.

This preserves coverage for the simple progress-bar path while removing

    [3 lines not shown]
DeltaFile
+16-9llvm/utils/lit/tests/progress-bar.py
+16-91 files

LLVM/project 41d05aellvm/utils/lit/lit TestRunner.py InprocBuiltins.py

Revert "[Lit][NFC] Refactor shell environment functionality and in-process builtins from TestRunner.py into new modules (Reopened)" (#193740)

Reverts llvm/llvm-project#177358

Bot failure: https://lab.llvm.org/buildbot/#/builders/181/builds/41934
DeltaFile
+577-34llvm/utils/lit/lit/TestRunner.py
+0-315llvm/utils/lit/lit/InprocBuiltins.py
+0-271llvm/utils/lit/lit/ShellEnvironment.py
+577-6203 files

LLVM/project ac59400llvm/utils/lit/lit TestRunner.py InprocBuiltins.py

Revert "[Lit][NFC] Refactor shell environment functionality and in-process bu…"

This reverts commit 9b986d49d6ca963bc22f265ce4045affbde427b4.
DeltaFile
+577-34llvm/utils/lit/lit/TestRunner.py
+0-315llvm/utils/lit/lit/InprocBuiltins.py
+0-271llvm/utils/lit/lit/ShellEnvironment.py
+577-6203 files

LLVM/project b005fd3llvm/lib/Target/LoongArch LoongArchLSXInstrInfo.td LoongArchLASXInstrInfo.td, llvm/test/CodeGen/LoongArch/lasx bitsel.ll

[LoongArch] Add patterns for vector bitwise selection

Add instruction selection patterns for VBITSEL_V/XVBITSEL_V and
VBITSELI_B/XVBITSELI_B to match the canonical bitwise select idiom:

`(a & b) | (~a & c)`

This enables the backend to generate dedicated bitwise select
instructions instead of separate AND/ANDN/OR sequences.
DeltaFile
+5-15llvm/test/CodeGen/LoongArch/lasx/bitsel.ll
+5-15llvm/test/CodeGen/LoongArch/lsx/bitsel.ll
+11-0llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+11-0llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+32-304 files