MC: Remove MCAsmInfo::ExceptionsType
The exception model now comes from the module, and the MCAsmInfo
predicates that depend on it take the model as a parameter. The
target's default model is still available from
Triple::getDefaultExceptionHandling.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
WebAssembly: Use reportFatalUsageError for eh option errors
Avoid using the deprecated report_fatal_error, and add missing
error test coverage.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
CodeGen: Remove TargetOptions::ExceptionModel
The exception model now comes only from the "exception-model" module
flag. Remove the TargetOptions field and its copy into MCAsmInfo, so
MCAsmInfo only knows the target's default model.
The WebAssembly model checks move from the TargetMachine constructor
into the Emscripten EH/SjLj lowering pass. Clang relied on the backend
to reject non-wasm models for wasm targets, so it now rejects them
itself.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[mlir][linalg] Fix rank-reducing insert_slice vectorization writing to wrong dims (#226490)
Vectorizing a rank-reducing `tensor.insert_slice` took the vector shape
from the non-dropped result dims, but wrote the vector back with an
implied minor-identity permutation map, i.e. onto the trailing result
dims. When the dropped unit dims are not the trailing ones, those are
the wrong dims.
Inserting a `tensor<5xi32>` into `tensor<5x3xi32>` at `[0, 2] [5, 1] [1,
1]` fills column 2, one element per row. Vectorized, the write went
along dim 1, so only the first element landed and the other four were
discarded by the out-of-bounds check. With user-provided vector sizes
the write was masked with `dim(1) - index(0)` and stored past the end of
the row instead.
Fixed by passing a permutation map built from the non-dropped result
dims, and by making `createWriteOrMaskedWrite` use the dims that map
selects, both to decide whether a mask is needed and to size it: each
mask size is `dim - index` for that dim.
[17 lines not shown]
CodeGen: Read the exception model from the module flag
Module::getExceptionModel() now falls back to the triple's default
model instead of falling back to the TargetMachine.
The pass pipeline is built before the module is known, so schedule each
EH preparation pass when the target supports a model, and let the pass
check the module's model. Add TargetMachine::supportsExceptionModel so
the pass config can skip definitely irrelevant passes. SjLjEHPrepare is
now scheduled on every target with exception handling, and WinEHPrepare
only on COFF and Wasm targets. WinEHPrepare and WasmEHPrepare are
scheduled for Wasm by the base pass configs, replacing the WebAssembly
override.
This is almost the last step towards removing TargetOptions::ExceptionModel.
Co-authored-by: Claude Opus <noreply at anthropic.com>
[libc++abi] Retain the old CMP0155 behavior for GCC compatibility
Raising the minimum CMake version to 3.31 enables automatic module dependency
scanning for the C++23 libc++abi object libraries. GCC 16 and 17 then probe
the libstdc++ bits/stdc++.h header when processing libc++ headers and fail
if it is absent.
Set CMP0155 to OLD within libc++abi only when using GCC until its optional
header lookup is fixed. Preserve automatic scanning with Clang and guard
the policy setting for older CMake versions.
GCC bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127940
Validated the policy workaround on the CMake 3.31 minimum-version branch
with GCC 16.2.0 and CMake 3.31.12: the focused cxa_handlers.cpp reproducer
compiles. Clang 22.1.0 still generates and successfully executes the
clang-scan-deps rule for that source. git diff --check passes.
Assisted-by: Codex
[libc++] Disable automatic module scanning on ARM CI builders
The ARM Buildkite toolchains do not expose clang-scan-deps to CMake.
When CMP0155 enables automatic scanning for libc++abi C++23 sources,
these standalone runtimes builds fail with the scanner set to NOTFOUND.
Pass CMAKE_CXX_SCAN_FOR_MODULES=OFF in the eight ARM job invocations,
including the no-exceptions variants, until their toolchains provide a
matching scanner. Keep the other CI configurations on their defaults.
Validated bash syntax, git diff --check, and argument dispatch for all
eight ARM jobs with generic C++20, C++23, and modules jobs as controls.
Assisted-by: Codex
[libc++] Provision a suitable CMake for CI builds
The previous commit raised cmake_minimum_required to 3.31. The GitHub
jobs already satisfy it (the Linux image pins 3.31.0, macOS uses brew,
Windows uses the hosted image), but some self-hosted Buildkite agents
ship an older CMake and their images cannot be updated by us.
Teach run-buildbot to check the CMake version up front. When the cmake
on PATH is new enough, this costs a single `cmake --version` and nothing
else changes. Otherwise, download a pinned, SHA-256 verified CMake
3.31.12 release binary into ${XDG_CACHE_HOME:-~/.cache}/libcxx (outside
the build directory that run-buildbot wipes) and, when no binary exists
for the host or it cannot run there, bootstrap it from source with the
host compilers rather than the runtime's CC/CXX. The install is
published with an atomic rename so concurrent builders on one agent
never see a partial cache entry.
An explicit CMAKE override is still honored but now validated; in the
provisioned or overridden cases its directory is prepended to PATH so
[5 lines not shown]
PowerPC: Use minimal tablegen inputs for TargetParser
Generate PPCGenTargetFeatures.inc from a file that only includes the
feature and processor definitions, instead of the full PPC.td. Add
stub SchedMachineModel, as was recently done for AArch64 in #231954,
since the TargetParser usage does not need them.
llvm-min-tblgen -gen-target-features
Gigainstructions Peak RSS .td deps
PPC.td 1.72 85 MB 81
PPCTargetParserDef.td 0.01 6 MB 7
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
PowerPC: Move subtarget features to PPCFeatures.td
Move the subtarget features, predicates and processor feature lists out
of PPC.td, so they can be used without parsing the instruction and
register definitions.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
PowerPC: Move the PPC32 and PPC64 hardware modes to PPCRegisterInfo.td
They are only used by the register, instruction and calling convention
definitions. This allows the feature definitions to be used without
HwMode.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[X86][StackClash] Fix guard page skip with -fstack-clash-protection (#230951)
- issue: https://github.com/llvm/llvm-project/issues/230949
- Fixes possible guard page skip while using `-fstack-clash-protection`.
- If `AlignOffset = 0`, and `Offset` is a multiple of `StackProbeSize`,
the "N-1 pages" loop will leave:
`ChunkSize = Offset - CurrentOffset = StackProbeSize`.
- This is problematic since the tail allocation does not add a probe, as
it assumes `ChunkSize < StackProbeSize`.
So it will allocate `StackProbeSize` without a probe.
[IR] Use getFirstNonPHIIt for unreachable handling (NFC) (#233020)
This patch replaces BasicBlock::getFirstNonPHIOrPseudoProbe with
BasicBlock::getFirstNonPHIIt when checking whether a block contains only
an UnreachableInst or when replacing a dead block with an
UnreachableInst in SCCP.
Note that llvm.pseudoprobe is marked nounwind and willreturn, so
SimplifyCFG eliminates pseudo probes preceding an UnreachableInst, and
SCCP does not need to preserve leading pseudo probes when erasing dead
blocks.
Assisted-by: Antigravity
Return conflicting compositions from addComposite immediately
Check for an existing composition up front: return a conflicting one
right away, instead of after updating B's ranges from a composition that
isn't recorded. This no longer needs the try_emplace result. The
generated code for all in-tree targets is unchanged, and the instruction
count is the same.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Initialize targets before creating a LibraryOptionsContext. NFC (#233041)
Initialize the targets to register their library options, before parsing
command line arguments.
This prepares for removing the T::Global fallback in
`LibraryOptionsContext::get<T>()`.
(The -mtriple change of llvm-split was originally added for
AMDGPU --lto-partitions #83128)
[LTO,lld] Set -mllvm library options in the LTO context. NFC (#233026)
Follow-up to #231407: move tools off cl::ParseCommandLineOptions, which
sets the libraries' `XXXOptions::Global`, to
`cl::parseCommandLineOptions(LibraryOptionsContext &, ...)`.
lto::Config::LibraryOptions replays into every LLVMContext that LTO
creates: the regular LTO context, each ThinLTO backend, and split code
generation.
This prepares for removing the T::Global fallback in
LibraryOptionsContext::get<T>().
LLM-aided
TableGen: Look up sub-register index compositions in an array
compose() looked up each composition in a std::map. It is called for
every super-register class set in extendSuperRegClasses, and by
addComposite. Sub-register indices are numbered densely, so also keep
each index's compositions in an array indexed by enum value. For
AMDGPU's 400 indices this is about 1 MB.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 746 474 148
After 721 (-3.4%) 446 (-6.1%) 139 (-5.8%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Skip classes without matching super-register classes in RegisterBankEmitter
visitRegisterBankClasses checks every sub-register index for every pair
of register classes. Skip the per-index loop if RC is not in any of the
class's super-register class sets.
AMDGPU tablegen run for AMDGPUGenRegisterBank.inc:
Gigacycles CPU seconds
Before 51.7 16.0
After 48.4 (-6.4%) 14.9 (-6.9%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Insert super-register class sets in one step
extendSuperRegClasses added each super-register class to the composed
index's set with a separate addSuperRegClass call, which looks up the
set in the DenseMap every time. Look up the set once and insert the
whole range.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 797 489 153
After 755 (-5.2%) 477 (-2.4%) 149 (-2.5%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
Free the sub-register map once the sorted array is built
The map is not modified after computeSuperRegs, so keep only the array,
with the sub-register index pointers so it can also be iterated, and
search it by the index's enum value.
AMDGPU tablegen runs that build the register bank:
Gigacycles CPU seconds Peak RSS (RegisterBank)
Before 541 169 857 MB
After 540 (-0.1%) 169 (+0.1%) 792 MB (-7.6%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
TableGen: Return early from addComposite for known compositions
computeComposites calls addComposite for each pair of sub-registers of
every register with a distinct sub-register structure, so most calls
repeat a composition that is already known. Each call still did three
std::map lookups per hardware mode to update the sub-register ranges.
If the composition already exists and its result has an offset in every
mode, the rest of the function has no effect, so return early. Cache
whether the result has an offset in every mode, since offsets are never
cleared once set.
AMDGPU tablegen runs that build the register bank:
Gigainstructions Gigacycles CPU seconds
Before 916 540 169
After 797 (-13.0%) 489 (-9.5%) 153 (-9.4%)
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
[FuzzMutate] Parse fuzzer options into a context. NFC (#233035)
Move tools off cl::ParseCommandLineOptions, which sets the libraries'
`XXXOptions::Global`, to
`cl::parseCommandLineOptions(LibraryOptionsContext &, ...)`.
Create LibraryOptionsContext after initializing the targets (which may
register library options).
This prepares for removing the T::Global fallback in
`LibraryOptionsContext::get<T>()`.
