LLVM/project 2d26fceclang/test/OpenMP task_codegen.cpp threadprivate_codegen.cpp, llvm/test/CodeGen/AMDGPU whole-wave-functions.ll accvgpr-spill-scc-clobber.mir

update

Created using spr 1.3.7
DeltaFile
+5,528-5,528llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+4,314-4,314llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,458-2,041clang/test/OpenMP/task_codegen.cpp
+2,140-2,140clang/test/OpenMP/threadprivate_codegen.cpp
+1,260-1,260llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+902-902llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+17,602-16,1851,586 files not shown
+94,037-42,6781,592 files

LLVM/project edcec54llvm/lib/CodeGen ExpandIRInsts.cpp, llvm/test/CodeGen/AMDGPU div_i128.ll rem_i128.ll

[CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts.

Previously, power-of-2 div/rem operations wider than
MaxLegalDivRemBitWidth were excluded from IR expansion and left for
backend peephole optimizations. Some backends can fail to process such
instructions in case we switch off DAGCombiner.

Now ExpandIRInsts expands them into shift/mask sequences:
- udiv X, 2^C  ->  lshr X, C
- urem X, 2^C  ->  and X, (2^C - 1)
- sdiv X, 2^C  ->  bias adjustment + ashr X, C
- srem X, 2^C  ->  X - (((X + Bias) >> C) << C)

Special cases handled:
- Division/remainder by 1 or -1 (identity, negation, or zero)
- Exact division (sdiv exact skips bias, produces ashr exact)
- Negative power-of-2 divisors (result is negated)
- INT_MIN divisor (correct via countr_zero on bit pattern)
DeltaFile
+148-0llvm/test/Transforms/ExpandIRInsts/X86/sdiv129.ll
+129-8llvm/lib/CodeGen/ExpandIRInsts.cpp
+115-0llvm/test/Transforms/ExpandIRInsts/X86/srem129.ll
+20-49llvm/test/CodeGen/AMDGPU/div_i128.ll
+34-27llvm/test/CodeGen/AMDGPU/rem_i128.ll
+51-0llvm/test/Transforms/ExpandIRInsts/X86/udiv129.ll
+497-841 files not shown
+522-847 files

LLVM/project 8fc59bcllvm/lib/Target/SPIRV SPIRVISelLowering.cpp SPIRVISelLowering.h, llvm/test/CodeGen/SPIRV atomicrmw-uinc-udec-wrap.ll AtomicCompareExchange.ll

[SPIRV] Add handling for `uinc_wrap` and `udec_wrap` atomics (#179114)

This adds atomicrmw `uinc_wrap` and `udec_wrap` operations support for
SPIR-V. Since SPIR-V doesn't provide dedicated instructions for those
two operations, we have to use the `AtomicExpand` pass to expand the
operations into CAS forms.

Closes #177204.
DeltaFile
+57-0llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
+33-1llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+19-0llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll
+5-0llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+2-0llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
+2-0llvm/test/CodeGen/SPIRV/llc-pipeline.ll
+118-16 files

LLVM/project 48dffbc.github/workflows release-documentation.yml release-tasks.yml

workflows/release-task: Use less privileged token for uploading release notes (#180299) (#180650)

We were using one token for both pushing to the llvmbot fork and for
creating a pull request against the www-releases repository, since the
fork and the repository have different owners, we were using a classic
access token which has very coarse-grained permissions. By using two
separate tokens, we limit the permissions to just what we need to do the
task.

This is a re-commit of b6ee085068972a41f3b2735a9f7e3ca48eab0f00 minus
the environment changes which were causing the workflow to fail.
DeltaFile
+5-1.github/workflows/release-documentation.yml
+1-0.github/workflows/release-tasks.yml
+6-12 files

LLVM/project cfbb9a6llvm/lib/Transforms/Instrumentation MemorySanitizer.cpp, llvm/test/Instrumentation/MemorySanitizer switch-icmp.ll

Revert "[msan] Switch switch() from strict handling to (icmp eq)-style handling" (#180636)

Reverts llvm/llvm-project#179851

Breaks https://lab.llvm.org/buildbot/#/builders/164/builds/18551 and
https://lab.llvm.org/buildbot/#/builders/94/builds/15188
DeltaFile
+0-41llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+5-20llvm/test/Instrumentation/MemorySanitizer/switch-icmp.ll
+5-612 files

LLVM/project 481f248lldb/include/lldb/Host HostInfoBase.h, lldb/include/lldb/Target DynamicLoader.h

[lldb] Get shared cache path from inferior, open (#180323)

Get the shared cache filepath and uuid that the inferior process is
using from debugserver, try to open that shared cache on the lldb host
mac and if the UUID matches, index all of the binaries in that shared
cache. When looking for binaries loaded in the process, get them from
the already-indexed shared cache.

Every time a binary is loaded, PlatformMacOSX may query the shared cache
filepath and uuid from the Process, and pass that to
HostInfo::GetSharedCacheImageInfo() if available (else fall back to the
old HostInfo::GetSharedCacheImageInfo method which only looks at lldb's
own shared cache), to get the file being requested.

ProcessGDBRemote caches the shared cache filepath and uuid from the
inferior, once it has a non-zero UUID. I added a lock for this ivar
specifically, so I don't have 20 threads all asking for the shared cache
information from debugserver and updating the cached answer. If we never
get back a non-zero UUID shared cache reply, we will re-query at every

    [20 lines not shown]
DeltaFile
+48-29lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+51-6lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
+18-4lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp
+14-2lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
+16-0lldb/include/lldb/Host/HostInfoBase.h
+10-3lldb/include/lldb/Target/DynamicLoader.h
+157-4411 files not shown
+194-6317 files

LLVM/project 55d6c6fclang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/Driver fuzzer.c sanitizer-ld.c

[clang][driver] Correcting arguments when using `libFuzzer` with `-shared-libsan` (#164842)

This PR contains two commits:
- Add required dependencies when using `-shared-libsan` and fuzzer.
Since libFuzzer is a static library we need to make sure that we add its
dependencies when building with `-shared-libsan`. E.g libFuzzer uses
`ceilf()` from `libm.so` when building on Gnu toolchain.
Previously, the resulting command did not contain the required link
libraries, giving build failures
(only a static sanitizer runtime would trigger the call to
`linkSanitizerRuntimeDeps`).
    
- Correcting dependency order when using fuzzer.
When building using `-shared-libsan` the sanitizer library needs to be
first in link order.
Since the fuzzer requires `-lstdc++` we have to make sure that the
sanitizer library is added before `-lstdc++`.

---------

Signed-off-by: Björn Svensson <bjorn.a.svensson at est.tech>
DeltaFile
+11-1clang/test/Driver/fuzzer.c
+8-3clang/lib/Driver/ToolChains/CommonArgs.cpp
+8-0clang/test/Driver/sanitizer-ld.c
+27-43 files

LLVM/project 19d6950libc/docs/headers time.rst, libc/docs/headers/math index.rst

 [libc][docs] Fix stale entrypoints links and time.h table duplication (#180347)

Update stale links and remove duplication in table.
DeltaFile
+7-9libc/docs/headers/time.rst
+8-4libc/docs/headers/math/index.rst
+15-132 files

LLVM/project 19705bdllvm/lib/Target/SPIRV SPIRVUtils.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers apint-constant.ll

[SPIR-V] Emit ceil(Bitwidth / 32) words during OpConstant creation (#180218)

Fixes error of handing constant integers with width in (64; 128) range.
Found during review of
https://github.com/llvm/llvm-project/pull/180182
DeltaFile
+30-0llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
+9-7llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+39-72 files

LLVM/project 853a390llvm/lib/Target/AArch64 AArch64CallingConvention.td, llvm/test/CodeGen/AArch64 cfguard-checks.ll

[win][aarch64] The Windows Control Flow Guard Check function also preserves X15 (#179738)

The target function to be checked by the Control Flow Guard Check
function is stored in `X15` on AArch64. This register is guaranteed to
be preserved by that function (on success), thus after it returns `X15`
can be used to branch to the target function instead of having to load
it from another register or the stack.
DeltaFile
+58-21llvm/test/CodeGen/AArch64/cfguard-checks.ll
+5-2llvm/lib/Target/AArch64/AArch64CallingConvention.td
+63-232 files

LLVM/project d44d6eaclang-tools-extra/docs/clang-tidy/checks/abseil unchecked-statusor-access.rst

[NFC] [clang-tidy] [doc] Don't use unicode character in doc
DeltaFile
+1-1clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
+1-11 files

LLVM/project 68d4175llvm/test/Transforms/LoopVectorize find-last-sink-based-iv-expr.ll

[LV] Add FindLast tests where IV-based expression could be sunk. (NFC)

Add set of FindLast tests where the selected expression is based on an
IV and could be sunk.
DeltaFile
+934-0llvm/test/Transforms/LoopVectorize/find-last-sink-based-iv-expr.ll
+934-01 files

LLVM/project 0c94a18utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[Bazel] NFC refactor out redundant is_x86_64_non_windows config (#180296)

The logic of `is_x86_64_non_windows` looks unnecessarily complicated and
is only used at one site... clean up the unused targets and refactor
x86_64 BLAKE3 asm sources into a separate filegroup. And then
`is_x86_64_non_windows` can be put inside a default condition.
DeltaFile
+15-43utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+15-431 files

LLVM/project 5339ad9llvm/test/MC/RISCV rv64p-valid.s

[RISCV] Add missing instruction tests to rv64p-valid.s. NFC (#180316)

An AI told me these were missing and helped me add them.
DeltaFile
+12-0llvm/test/MC/RISCV/rv64p-valid.s
+12-01 files

LLVM/project 06cffa5llvm/test/Transforms/LoopVectorize vplan-iv-transforms.ll vplan-widen-struct-return.ll

[VPlan] Auto-generate CHECKs in some VPlan printing tests.

Use new UTC support to re-generate check lines.
DeltaFile
+82-71llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
+97-36llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll
+43-17llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll
+29-26llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
+251-1504 files

LLVM/project 5d57c40utils/bazel/llvm-project-overlay/llvm driver.bzl

[bazel] Fix multicall tool invocation disambiguation (#180607)

The code seems to have considered the potential problem but did not
quite succeed in solving it ;)
DeltaFile
+5-2utils/bazel/llvm-project-overlay/llvm/driver.bzl
+5-21 files

LLVM/project d53272flibc/config/baremetal config.json, libc/src/__support str_to_float.h

[libc] Disable Clinger fast path for baremetal (#180598)

Clinger fast path bloats baremetal targets which are constrained in
binary size. Disabling it for baremetal libc builds.
DeltaFile
+3-3libc/src/__support/str_to_float.h
+3-0libc/config/baremetal/config.json
+6-32 files

LLVM/project 2b9a1aellvm/test/Transforms/LoopVectorize reduction-with-invariant-store.ll, llvm/test/Transforms/LoopVectorize/AArch64 partial-reduce-with-invariant-stores.ll

[LV] Add additional tests for reductions with intermediate stores. (NFC)

Adds missing test coverage for reductions with intermediate stores,
including partial reductions with intermediate stores, as well as
chained min/max reductions with intermediate stores.
DeltaFile
+91-0llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
+69-3llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-with-invariant-stores.ll
+160-32 files

LLVM/project c978bfellvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Fix a comment

Created using spr 1.3.7
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+1-11 files

LLVM/project 040d1efllvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Fix formatting

Created using spr 1.3.7
DeltaFile
+2-2llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-21 files

LLVM/project ccd9318mlir/include/mlir/Dialect/Utils StaticValueUtils.h, mlir/lib/Dialect/Utils StaticValueUtils.cpp

[MLIR][Utils] Fix overflow in constantTripCount for narrow types (#179985)

Extend operands when computing ub - lb to avoid overflow in signed
arithmetic. E.g., i8: ub=127, lb=-128 yields 255, which overflows
without extension.
DeltaFile
+18-0mlir/test/Dialect/SCF/trip_count.mlir
+12-3mlir/lib/Dialect/Utils/StaticValueUtils.cpp
+4-0mlir/include/mlir/Dialect/Utils/StaticValueUtils.h
+34-33 files

LLVM/project bf91c09libcxx/utils/ci BOT_OWNERS.txt

[libc++] Add myself as a FreeBSD point of contact
DeltaFile
+2-2libcxx/utils/ci/BOT_OWNERS.txt
+2-21 files

LLVM/project 5b6896ellvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 bool-mask.ll subvector-minbitwidth-unsigned-value.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+72-306llvm/test/Transforms/SLPVectorizer/X86/bool-mask.ll
+82-7llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4-10llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
+158-3233 files

LLVM/project d69ccf3llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-shuffle-merge.ll fixed-vectors-shuffle-int.ll

[RISCV] Combine shuffle of shuffles to a single shuffle (#178095)

Compressing to a single shuffle doesn't remove any information and the backend can better apply specific optimizations to a single shuffle.

Addresses #176218.

---------

Co-authored-by: Luke Lau <luke_lau at igalia.com>
DeltaFile
+441-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-merge.ll
+55-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+3-6llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
+499-73 files

LLVM/project 815cf3bclang/include/clang/Lex PPCallbacks.h, clang/lib/Frontend CompilerInstance.cpp

[clang][modules] Add single-module-parse-mode callback (#179714)

This PR adds new preprocessor callback that's invoked whenever the
single-module-parse-mode skips over a module import. This will be used
later on from the dependency scanner.
DeltaFile
+46-0clang/unittests/Frontend/CompilerInstanceTest.cpp
+12-0clang/include/clang/Lex/PPCallbacks.h
+2-0clang/lib/Frontend/CompilerInstance.cpp
+60-03 files

LLVM/project a9ea1cflld/test/wasm data-layout.s export-all.s, lld/wasm Writer.cpp Config.h

[lld][WebAssembly] Add new __rodata_start/__rodata_end symbols (#172102)

This is similar to etext/_etext in the ELF linker. Its useful in
emscripten to know where the RO data data ends and the data begins (even
though the Wasm format itself has no concept of RO data).

See
https://github.com/emscripten-core/emscripten/discussions/25939#discussioncomment-15243731
DeltaFile
+23-4lld/test/wasm/data-layout.s
+12-6lld/test/wasm/export-all.s
+12-6lld/test/wasm/mutable-global-exports.s
+8-0lld/wasm/Writer.cpp
+5-0lld/wasm/Config.h
+4-1lld/wasm/Driver.cpp
+64-176 files

LLVM/project e1d2ff6llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/hlsl-resources Sample3D.ll Sample1D.ll

[SPIRV] Implement lowering for HLSL Texture2D sampling intrinsics (#179312)

This patch implements the SPIR-V lowering for the following HLSL
intrinsics:
- SampleBias
- SampleGrad
- SampleLevel
- SampleCmp
- SampleCmpLevelZero

It defines the required LLVM intrinsics in 'IntrinsicsDirectX.td' and
'IntrinsicsSPIRV.td'.

It updates 'SPIRVInstructionSelector.cpp' to handle the new intrinsics
and
generates the correct 'OpImageSample*' instructions with the required
operands
(Bias, Grad, Lod, ConstOffset, MinLod, etc.).


    [3 lines not shown]
DeltaFile
+185-43llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+70-0llvm/test/CodeGen/SPIRV/hlsl-resources/Sample3D.ll
+69-0llvm/test/CodeGen/SPIRV/hlsl-resources/Sample1D.ll
+68-0llvm/test/CodeGen/SPIRV/hlsl-resources/SampleCmp.ll
+68-0llvm/test/CodeGen/SPIRV/hlsl-resources/SampleGrad.ll
+67-0llvm/test/CodeGen/SPIRV/hlsl-resources/SampleBias.ll
+527-4310 files not shown
+860-4816 files

LLVM/project c1059b2.github/workflows release-documentation.yml release-tasks.yml

Revert "workflows/release-task: Use less privileged token for uploading release notes (#180299)"

This reverts commit b6ee085068972a41f3b2735a9f7e3ca48eab0f00.

This reverts commit e624d5088d57eff4ec0fd1e8c3122541b81e1aa0.

This was causing failures like the following:
https://github.com/llvm/llvm-project/actions/runs/21842945533. The
follow up fix is also reverted as it did not actually fix the issue.
DeltaFile
+1-6.github/workflows/release-documentation.yml
+0-3.github/workflows/release-tasks.yml
+1-92 files

LLVM/project e624d50.github/workflows release-tasks.yml

[Github] Add runs-on to release-tasks.yml

This was failing validation against main and sending everyone emails.
Try adding the fix that was suggested in the workflow run.
DeltaFile
+1-0.github/workflows/release-tasks.yml
+1-01 files

LLVM/project d1ec04dllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize outer_loop_test2.ll outer-loop-inner-latch-successors.ll

[VPlan] Simplify single-entry VPWidenPHIRecipe.

Include VPWidenPHIRecipe in phi simplification if there's a single
incoming value.
DeltaFile
+6-7llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
+3-4llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
+3-3llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-4llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
+2-4llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll
+1-2llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
+17-242 files not shown
+19-288 files