[AMDGPU][InstCombine] Fold zero dot operands to accumulator
Fold AMDGPU dot intrinsics when either operand is zero.
`dot(a, 0) = 0` and `dot(0, b) = 0`, so replace the intrinsic with its accumulator.
This avoids unrelated clamp and add/sub reassociation cases.
[AMDGPU][InstCombine] Canonicalize dot constant operands (#225083)
Move constant dot product source operands to the right hand side
and add tests for signed and unsigned dot intrinsics.
[flang] Fold fir.if with a constant condition (#225542)
Use `populateRegionBranchOpInterfaceInliningPattern` to fold `fir.if`
when the condition is a constant. It inlines the region the condition
selects, replacing uses of the `fir.if` results with the operands of
that region's `fir.result`, and erases the `fir.result`. A false
condition with no else region leaves nothing behind.
[orc-rt] Make StandaloneMachOUnwindInfoRegistrar internal. (#225982)
StandaloneMachOUnwindInfoRegistrar depends on libunwind's
__unw_add_find_dynamic_unwind_sections, which is only available on
Darwin, and is only consumed within the runtime. Move its header to
orc-rt-internal/bedrock/sys/darwin/ (no longer installed), and its
sources and unit test to the corresponding sys/darwin/ directories.
The SPS CI adder header stays public, but is now installed only on Apple
platforms.
[RISCV][MC] Allow x0 as the destination of qc.inw (#225602)
According to the Xqciio specification, `qc.inw` does not impose any
restriction that excludes `x0` as the destination register. In
`qc.inw.yaml`, `rd` is defined as:
```
- name: rd
location: 11-7
```
This commit removes the incorrect `x0` restriction for `qc.inw`.
Link:
https://github.com/qualcomm/riscv-unified-db/blob/main/arch_overlay/qc_iu/inst/Xqci/qc.inw.yaml
[RISCV] Support getJumpTableIndex (#224197)
This patch implements getJumpTableIndex hook for RISC-V; it trace from
PseudoBRIND back to the %jump-table.N.
The li instruction in jumptable dispatch block exists because the phi
constant is emitted during instruction selection. LLVM chooses the
source block in which to place the phi constant, then postpones moving
it to MachineSink, which relocates the phi constant closer to its use
site. However, to sink it out of the jump table dispatch block,
MachineSink needs to split the critical edge, which requires updating
the jump table entry. It needs the getJumpTableIndex hook to know which
jump table to update.
This avoids unnecessary instructions in the hot path (the jump table
dispatch block).
[AMDGPU] Measure MFMA read hazards at each producer
Introduce more sophisticated traversal to avoid the following traps:
- order-dependent traversal and discarding seen BBs despite shorter path
- mis-matching distance and window of different producers
Record the best distance per BB instead of a visited flag and sweep the
arrivals in nondecreasing distance (bucket queue). This pairs producers
with their actual distance to a consumer in one go.
Fixed scenarios:
- MFMA reading an MFMA result as srcA, srcB or srcC
- VALU, memory or export instruction reading an MFMA result
rewrite-vgpr-mfma-to-agpr.ll gains an s_nop 2: a 4-pass XDL write that
partially overlaps the srcC read two slots later requires five wait
states, and none were emitted because the nearest producer wrote the
register in full.
AI-assisted.
[AMDGPU][NFC] Extract the MFMA read-window calculation
Move the wait states a consumer needs before reading an MFMA result out
of checkMAIHazards90A into getMFMAReadWaitStates, taking the producer as
an argument, so a caller can ask about a specific producer. The partial
srcC overlap half moves into getMFMAOverlappedSrcCWaitStates. The caller
passes the producer the walk recorded, so nothing changes.
AI-assisted.
[AMDGPU] Measure MFMA overwrite hazards at each instruction
Apply previously established processing to:
- VALU overwriting an MFMA result
- VALU overwriting a register an MFMA took as srcC
AI-assisted.
[RISCV][GlobalISel] Fix fptosi/fptoui from half to i64 on RV32 (#222316)
The fcvt.l[u].h patterns are RV64-only, so RV32 had no rule for
`G_FPTOSI/G_FPTOUI` with `{s64, s16}.` The magnitude of a half is at
most `65504`, so with Zfh the i32 result of `fcvt.w[u].h` never
overflows and can simply be extended to i64.
[AMDGPU] Use synthetic fixtures for generic feature validation tests (#225551)
Remove the classification test that includes the full AMDGPU target.
Real targets are validated when generating AMDGPUTargetParserDef.inc
during the build.
Extend the lightweight generic feature tests to cover inherited
classifications of backend-only features, support through member-side
implications, and unsupported generic-side implied features.
Addresses the timeout reported on #223179
[PowerPC] Restore LiveVariables run before PPCTLSDynamicCallPass (#225816)
This change is a partial revert of 7818c91f7151. Removing the explicit
LiveVariables run before PPCTLSDynamicCallPass causes a crash on ppc64le
-fPIC builds:
```
fatal error: error in backend: Use not jointly dominated by defs.
```
This change was first added in 2016 with an unresolved FIXME.
Unfortunately, the root cause still needs to be understood and
investigated, so restore this for now to fix the broken buildbots.
[CIR] Introduce the cir.sdk_version module attribute (#225953)
CIRGen records the platform SDK version on the module as a
`cir.sdk_version` string attribute, and LoweringPrepare's CUDA/HIP
registration reads it instead of `getTargetInfo().getSDKVersion()` to gate
`__cudaRegisterFatBinaryEnd`, dropping one more `ASTContext` dependency
from the post-CIRGen pipeline.
LLVM IR already records the same fact as the "SDK Version" module flag
(`Module::setSDKVersion/getSDKVersion`), so an attribute on the module
is proper.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
[flang] Remove FIRBuilder dependency from optimizer support utilities (#225836)
Fix a GCC 16 build failure where FIROps.cpp.o had undefined references
to
fir::FirOpBuilder::setCommonAttributes(mlir::Operation *) const from
FirOpBuilder::notifyOperationInserted,
RewriterBase::ForwardingListener's notifyOperationInserted, and
OpBuilder::createOrFold<fir::ConvertOp>.
FIROps.cpp includes Optimizer/Support/Utils.h, which previously included
FIRBuilder.h. That exposes the inline virtual override
FirOpBuilder::notifyOperationInserted and its call to the out-of-line
setCommonAttributes implementation. Speculative devirtualization can
turn an ordinary virtual listener call into a guarded direct call and
inline that override, introducing a reference to setCommonAttributes
without an explicit use of FirOpBuilder in FIROps.cpp. This is
consistent with the reported call sites and GCC 16's expanded
speculative devirtualization.
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[clangd] Enforce SymbolKind YAML coverage with -Wswitch (#225945)
Turn the SymbolKind YAML mappings into switch cases so missing mappings
trigger -Wswitch.
Follow-up to #222070.
[RISCV] Combine two consecutive VSLIDEDOWN_VL nodes into one (#225232)
Given this pattern
```
%down0 = RISCVISD::VSLIDEDOWN_VL undef, %val, %offset0, %mask, %vl0
%down1 = RISCVISD::VSLIDEDOWN_VL undef, %down0, %offset1, %mask, %vl1
```
we can turn it into
```
%down1 = RISCVISD::VSLIDEDOWN_VL undef, %val, %offset2, %mask, %vl1
```
where %offset2 is `%offset0 + %offset1`, if `%vl0 >= %offset1 + %vl1`.
[BOLT] Make .debug_names emission reproducible (#225218)
--update-debug-sections does not produce the same binary twice when the
input has a .debug_names section, or is given one with
--create-debug-names-section. Three sections vary from run to run:
.debug_str, .debug_names and .debug_str_offsets. On a two-CU split-DWARF
test binary, ten runs of the same llvm-bolt produced three different
outputs.
PR #197859 made the per-bucket work merge in partition order precisely
so the output would be reproducible, but missed this section. Two
issues:
- .debug_str offsets were handed out from the workers, so main.dwo.dwo
added by the merge step lands in a different place in each run. The
string offsets stored in .debug_names follow from it, and so does
.debug_str_offsets;
- hash colliding names were ordered by insertion (worker) order, also
non-deterministic.
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[CIR] Fix the order of temporary object cleanup (#225560)
We had a problem in CIR where we were performing cleanups in the wrong
order when conditional and unconditional cleanups were needed for
temporary objects created in a single expression. The unconditional
cleanups were being emitted as they occur, while the conditional
cleanups were deferred until the entire expression had been emitted. The
result was that conditional cleanups were performed after unconditional
cleanups, even if the unconditionally destroyed object was created
first.
This change fixes that problem by reorganizing the way conditional
cleanups are handled. A cir.cleanup.scope operation is now created
eagerly where a conditional begins rather than at the start of the full
expression, so that it nests inside the cleanup scopes of temporaries
created before the conditional and outside those created after it. Scope
nesting determines the order in which the cleanup regions run, so this
yields reverse-of-construction order. A ConditionalCleanupScope object
tracks the scope and the conditional cleanups waiting to be emitted into
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[flang][cuda] Lower device is active as an operation (#225583)
Instead of lowering straight to a functin call, go through an op so it
can be lowered differently between device and host.
[GlobalOpt] Fix constructor folding on global with explicit section. (#220729)
Make sure we don't try to emit a non-zero value into BSS, or anything
similar to that.
[HLSLSemanticSignatures] Implement the optimal packing of elements (#218064)
Implements the optimal packing algorithm by sorting the elements in an
optimal order before sorting with prefix packing. This also adds an
explicit packing stage for the clip/cull signature elements that allows
them to be packed with other compatible semantic types.
Resolves: #205874.
Assisted by: Claude Opus 5 and GPT-5.6 Sol
[SystemZ][z/OS] Fix compile errors cused by sys::fs::file_t (#225539)
Follow-up to #224859: some calls/prototypes are guarded on z/OS, and
also need to be updated. This change fixes various compile errors.
