LLVM/project eb5d41c — llvm/test/tools/llvm-ar error-opening-permission.test

by Vitaly Buka on ⎇
Reword comment

Created using spr 1.3.7
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LLVM/project 531c589 — llvm/test/tools/llvm-ar error-opening-permission.test

by Vitaly Buka on ⎇
Move comment next to chmod line

Created using spr 1.3.7
DeltaFile
+2-2llvm/test/tools/llvm-ar/error-opening-permission.test
+2-21 files

LLVM/project a2dbe81 — llvm/test/CodeGen/X86/AMX pr228950.ll

by John Hui via GitHub on ⎇
[X86] Pin debug variable locations mode in pr228950.ll (#231278)

The CHECK lines in pr228950.ll assume instruction-referencing variable
locations, which is the x86_64 default. Under VarLoc-based
LiveDebugValues, llc emits a #DEBUG_VALUE comment between ldtilecfg and
tilezero, and the CHECK-NEXT fails.

Pass -experimental-debug-variable-locations=true so the test does not
depend on the default. This does not change upstream output.

rdar://189810853

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
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LLVM/project d6df1a3 — llvm/test/tools/llvm-ar error-opening-permission.test

by Vitaly Buka on ⎇
[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
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+2-0llvm/test/tools/llvm-ar/error-opening-permission.test
+2-01 files

LLVM/project d814497 — llvm/lib/Transforms/Utils BypassSlowDivision.cpp

by yinghao via GitHub on ⎇
[NFC] Fix wrong comment in insertFastDivAndRem (#230879)

The branch checks that the divisor IS a constant, not the opposite.
DeltaFile
+1-1llvm/lib/Transforms/Utils/BypassSlowDivision.cpp
+1-11 files

LLVM/project f7e87c3 — llvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel half-fcmp.ll

by Zeyi Xu via GitHub on ⎇
[RISCV][GlobalISel] Promote f16 to f32 for G_FCMP without Zfh (#231097)

Without Zfh, G_FCMP with f16 operands had no matching legalization rule,
so GlobalISel failed to legalize it.
This commit widen the operands to f32 instead, matching SelectionDAG,
which promotes f16 SETCC when Zfh is not available.

Godbolt link: https://godbolt.org/z/Y9P7Yqa8d
DeltaFile
+341-0llvm/test/CodeGen/RISCV/GlobalISel/half-fcmp.ll
+1-0llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+342-02 files

LLVM/project 106392e — llvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel half-imm.ll

by Zeyi Xu via GitHub on ⎇
[RISCV][GlobalISel] Use Zfhmin for G_FCONSTANT s16 (#230723)

`fmv.h.x` is available with Zfhmin, and the selector already
materializes f16 constants through a GPR and `fmv.h.x`. SelectionDAG
handles f16 constants with Zfhmin, but GlobalISel would abort because
G_FCONSTANT s16 was only legal with Zfh.

SelectionDAG: https://godbolt.org/z/coMc7j3x9
GlobalISel: https://godbolt.org/z/MqzdG1r4v
DeltaFile
+46-0llvm/test/CodeGen/RISCV/GlobalISel/half-imm.ll
+1-1llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+47-12 files

LLVM/project fc7cdf2 — llvm/lib/Target/RISCV/GISel RISCVLegalizerInfo.cpp, llvm/test/CodeGen/RISCV/GlobalISel half-convert.ll

by Zeyi Xu via GitHub on ⎇
[RISCV][GlobalISel] Use Zfhmin for G_FPEXT from f16 to f64 (#230721)

From SPEC: If the D extension is present, the fcvt.d.h and fcvt.h.d
instructions are also included.

Link:
https://github.com/riscv/riscv-isa-manual/blob/1b9ca13819259df4b3bc87a7d7dcda06dd2fb6a9/src/unpriv/zfhmin.adoc?plain=1#L14-L17

Follow up of https://github.com/llvm/llvm-project/pull/227225
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+42-0llvm/test/CodeGen/RISCV/GlobalISel/half-convert.ll
+2-1llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+44-12 files

LLVM/project eb883e1 — llvm/lib/Transforms/InstCombine InstCombineSelect.cpp, llvm/test/Transforms/InstCombine select-and-cmp.ll select-or-cmp.ll

by Aiden Grossman via GitHub on ⎇
[InstCombine] Fix profiles in FoldSelectWithAndOrCond (#231327)

3b38314a2b69847305b692677dbe64f1eb43235a also incorrectly applied branch
weights. The fact that the true and false arms have the same value says
little about the value distribution of the condition. For example, if we
take the following case:

```llvm
%A = icmp ne i32 %x, %z
%B = icmp eq i32 %y, %z
%C = and i1 %A, %B
%D = select i1 %C, i32 %z, i32 %x, !prof !1
ret i32 %D
```

which LLVM folds to

```llvm
%B = icmp eq i32 %y, %z

    [9 lines not shown]
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+14-19llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+13-6llvm/test/Transforms/InstCombine/select-factorize.ll
+2-3llvm/test/Transforms/InstCombine/select-or-cmp.ll
+1-1llvm/test/Transforms/InstCombine/select-and-cmp.ll
+0-1llvm/utils/profcheck-xfail.txt
+30-305 files

LLVM/project 0b906b4 — llvm/include/llvm/ExecutionEngine/JITLink aarch64.h, llvm/test/ExecutionEngine/JITLink/AArch64 ELF_branch_addends.s

by Chibuoyim (Wilson) Ogbonna via GitHub on ⎇
[JITLink][AArch64] Preserve destination addends on external branches (#231231)

Currently, an external branch such as `b target + addend` is incorrectly
redirected to `stub + addend` instead of `target + addend`. With an
addend of 4, for example, this skips the `adrp` in the stub's `adrp +
ldr + br` sequence, leaving `x16` without the expected page address,
which may cause a segmentation fault.

Reproducer on AArch64:
```asm
// caller.s
.text
.p2align 2
.globl main
main:
    mov x16, #0     // Make the skipped adrp expose the bug.
    b target + 4
```
```asm

    [24 lines not shown]
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+4-1llvm/include/llvm/ExecutionEngine/JITLink/aarch64.h
+41-12 files

LLVM/project c951fe6 — compiler-rt/lib/asan asan_report.cpp asan_errors.cpp, compiler-rt/test/asan/TestCases assume_dereferenceable_halt_on_error.cpp assume_dereferenceable_pass.cpp

by PiJoules via GitHub on ⎇
Reland "[compiler-rt][asan] Add asan checks for __builtin_assume_dereferencable" (#224163)

This relands commit bf8cf4b7b31b956ea4dfec93b0b4d77b359b188b (#190871),
which was reverted in commit e3b3706ceeea94ade3557275628a0e589e10ba24
(#193655).

This checks that the range covered by this intrinsic is dereferenceable.
Specifically it checks for `llvm.assume` intrinsics using the
`dereferenceable` operator bundle and asserts that the shadow for this
range is zero.

Fixes included in this reland:
1. Darwin Stable ABI: Added `__asan_report_assume_dereferenceable` and
`__asan_report_assume_dereferenceable_noabort` to `asan_abi_tbd.txt` to
resolve the interface symbols diff failure in
llvm_interface_symbols.cpp.
2. MSVC Support: Added `UNSUPPORTED: msvc` to the new
`assume_dereferenceable*.cpp` tests, as
`__builtin_assume_dereferenceable` is a Clang builtin not supported by

    [7 lines not shown]
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+90-0compiler-rt/test/asan/TestCases/assume_dereferenceable.cpp
+30-8compiler-rt/lib/asan/asan_errors.cpp
+37-0llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+36-0compiler-rt/test/asan/TestCases/assume_dereferenceable_pass.cpp
+23-4compiler-rt/lib/asan/asan_report.cpp
+23-0compiler-rt/test/asan/TestCases/assume_dereferenceable_halt_on_error.cpp
+239-1211 files not shown
+322-2017 files

LLVM/project b4aba96 — llvm/utils profcheck-xfail.txt

by Aiden Grossman via GitHub on ⎇
[ProfCheck] Update XFAIL list (#231328)

This test was apparently fixed by other patches.
DeltaFile
+0-1llvm/utils/profcheck-xfail.txt
+0-11 files

LLVM/project 161eb9f — llvm/test/Transforms/InstCombine ctpop.ll

by Luke Lau on ⎇
Add vector test
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+15-0llvm/test/Transforms/InstCombine/ctpop.ll
+15-01 files

LLVM/project 7466db2 — llvm/lib/Transforms/InstCombine InstCombineAddSub.cpp, llvm/test/Transforms/InstCombine ctpop.ll

by Luke Lau on ⎇
[InstCombine] Fold trunc(ctpop(A)) + trunc(ctpop(B)) -> trunc(ctpop(A) + ctpop(B))

This allows the combine added in #231321 to kick in and fold the motivating ctpop case in automotive-bitcount:

```c
static char bits[256] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8};

int CDECL ntbl_bitcount(long int x)
{
      return
            bits[ (int) (x & 0x0000000FUL)       ] +
            bits[ (int)((x & 0x000000F0UL) >> 4) ] +
            bits[ (int)((x & 0x00000F00UL) >> 8) ] +
            bits[ (int)((x & 0x0000F000UL) >> 12)] +
            bits[ (int)((x & 0x000F0000UL) >> 16)] +
            bits[ (int)((x & 0x00F00000UL) >> 20)] +
            bits[ (int)((x & 0x0F000000UL) >> 24)] +
            bits[ (int)((x & 0xF0000000UL) >> 28)];
}
```
DeltaFile
+5-13llvm/test/Transforms/InstCombine/ctpop.ll
+6-0llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+11-132 files

LLVM/project c858152 — llvm/test/Transforms/InstCombine ctpop.ll

by Luke Lau on ⎇
Precommit tests
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+17-01 files

LLVM/project ffdc919 — lldb/docs/resources lldbgdbremote.md, lldb/include/lldb/Utility AcceleratorGDBRemotePackets.h

by satyanarayana reddy janga via GitHub on ⎇
[lldb] Add jLLDBSettings remote packet (#229179)

## Summary

Add the negotiated `jLLDBSettings` packet for LLDB-specific settings on
a GDB-remote connection. The initial fields are:

- `dyld_plugin_name`: dynamic-loader plugin LLDB should use.
- `accelerator_plugin_name`: identifies the server-side accelerator
plugin.
- `send_dyld_packet_to_accelerator`: selects the accelerator or native
connection for dynamic-loader queries.

The object can be extended with additional settings. LLDB only sends the
packet when the server advertises `lldb-settings+`; servers that do not
advertise it retain existing behavior.

This is the protocol foundation for #217393.


    [4 lines not shown]
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+40-0lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+37-0lldb/docs/resources/lldbgdbremote.md
+22-0lldb/unittests/Utility/AcceleratorGDBRemotePacketsTest.cpp
+17-0lldb/include/lldb/Utility/AcceleratorGDBRemotePackets.h
+16-0lldb/source/Utility/AcceleratorGDBRemotePackets.cpp
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+187-09 files

LLVM/project 894e6cd — llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoP.td

by Craig Topper via GitHub on ⎇
[RISCV][P-ext] Remove RISCVISD::PPAIROE_H. NFC (#230356)

This is redundant with RISCVISD::PPAIROE.

Assisted-by: Claude
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+1-8llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-92 files

LLVM/project c3818a7 — llvm/lib/Transforms/InstCombine InstCombineAddSub.cpp

by Luke Lau on ⎇
Remove superfluous comment
DeltaFile
+1-2llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+1-21 files

LLVM/project 2599104 — llvm/lib/Target/RISCV RISCVISelLowering.cpp RISCVInstrInfoP.td

by Craig Topper via GitHub on ⎇
[RISCV][P-ext] Combine MHACC_H_B0 and MHACC_W_H0. NFC (#230362)

These semantically do the same operation only with different types.

Assisted-by: Claude
DeltaFile
+30-41llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+7-11llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+37-522 files

LLVM/project b4b25c7 — llvm/lib/Transforms/InstCombine InstCombineAddSub.cpp, llvm/test/Transforms/InstCombine ctpop.ll

by Luke Lau on ⎇
[InstCombine] Fold ctpop((X >> C1) & M1) + ctpop((X >> C2) & M2)

Following up from #231225, automotive-bitcount in llvm-test-suite and GCC use a "per-nibble" ctpop table lookup, where they split the operation up into smaller ctpop table lookups over chunks of the input:

```c
unsigned table_u32(unsigned x) {
  static const unsigned char ctpop[16] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4};
  return ctpop[x & 15] + ctpop[(x >> 4) & 15];
}
```

PR #231225 now converts the individual table lookups to ctpop intrinsics, so now we're left with `ctpop(X & 0xf) + ctpop((X >> 4) & 0xf) + ctpop((X >> 8) & 0xf) + ...`. We can combine these into `ctpop(X & 0xfff)` provided the extracted bits from X don't overlap.
DeltaFile
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+6-16llvm/test/Transforms/InstCombine/ctpop.ll
+52-162 files

LLVM/project 428d520 — llvm/lib/Target/AMDGPU AMDGPUTargetTransformInfo.cpp, llvm/test/Transforms/SLPVectorizer/AMDGPU complex-mul-fma.ll ordered-reduction-coalesced-loads.ll

by Dmitry Sidorov via GitHub on ⎇
[AMDGPU] Limit the fmul fusion discount to a matching context type (#229845)

The fmul is free when its context instruction feeds a fusable fadd or
fsub. A vector fmul priced with a scalar lane as the context inherits
that fusion only when it is emitted lane by lane. On a packed type the
scalar user does not show that the vector fmul feeds a vector fadd, and
products extracted into a scalar fadd chain keep the packed fmul while
the fma is lost.
DeltaFile
+38-37llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll
+36-6llvm/test/Transforms/SLPVectorizer/AMDGPU/fma-operand-contract-selection.ll
+7-11llvm/test/Transforms/SLPVectorizer/AMDGPU/alt-fmul-fadd-cost.ll
+8-8llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-coalesced-loads.ll
+5-2llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+1-1llvm/test/Transforms/SLPVectorizer/AMDGPU/complex-mul-fma.ll
+95-656 files

LLVM/project c5a8ee0 — compiler-rt/lib/builtins CMakeLists.txt

by Sharjeel Khan via GitHub on ⎇
[compiler-rt][ARM] Mark optimized FP add/sub asm as superseding aeabi_[df]rsub.c (#230739)

#179921 (`arm/adddf3.S`) and #179929 (`arm/addsf3.S` and
`arm/thumb1/addsf3fast.S`) introduced optimized assembly implementations
for floating-point addition, subtraction, and reversed subtraction
(`__aeabi_drsub` and `__aeabi_frsub`), but omitted `arm/aeabi_drsub.c`
and `arm/aeabi_frsub.c` from `SUPERSEDES` (and `PROVIDES`), causing
duplicate symbol errors during lld linking in Android.

Assisted-by: Gemini
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+3-31 files

LLVM/project 5b8af5a — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize epilog-vectorization-reductions.ll

by Florian Hahn via GitHub on ⎇
[VPlan] Simplify extracts of the last lane of live-ins (#231312)

Live-ins are single scalars, so simplify their extracts like other
single-scalar live-in values.

This allows reusing a single resume phi for multiple reductions whose
results fold to the same live-in.
DeltaFile
+3-4llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
+2-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+5-52 files

LLVM/project 26dd72d — llvm/test/Transforms/InstCombine ctpop.ll

by Luke Lau on ⎇
Precommit tests
DeltaFile
+111-0llvm/test/Transforms/InstCombine/ctpop.ll
+111-01 files

LLVM/project 3c4e13e — mlir/include/mlir/Dialect/LLVMIR ROCDLOps.td

by Krzysztof Drewniak on ⎇
[MLIR][ROCDL] Note the deprecation of the <4 x i32> buffer ops

While we don't have a way to flag a MLIR op as deprecated yet, go
ahead and add a note to the old `<4 x i32>` intriinsic ops that
they're actively deprecated.

AI disclosure: Claude made this edit, though I checked the wording and
wrote up this message.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
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+24-0mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+24-01 files

LLVM/project e10e2b6 — llvm/docs AMDGPUUsage.rst ReleaseNotes.md

by Krzysztof Drewniak on ⎇
[AMDGPU][docs] Document the <4 x i32> buffer intrinsic deprecation

Flag the deprecation of <4 x i32> buffer intrinsics in the release
notes, flagging the migration path and the s.buffer.load subtleties.

AI disclosure: Claude did draft some of this, but I deleted basically
all of it and the words are mine

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+31-0llvm/docs/ReleaseNotes.md
+24-1llvm/docs/AMDGPUUsage.rst
+55-12 files

LLVM/project e5d1102 — llvm/test/CodeGen/AMDGPU deprecated-buffer-intrinsics-warn-loc.ll deprecated-buffer-intrinsics-warn.ll

by Krzysztof Drewniak on ⎇
[AI fixup] Test nits

Address review nits from PR #231308 on the deprecation warning tests:
- Use `< %s` instead of passing the file as an argument.
- Keep the RUN lines contiguous and the CHECK lines in one block
  instead of splitting them up with blank lines.
- Fix subject/verb agreement in the header comment.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+3-6llvm/test/CodeGen/AMDGPU/deprecated-buffer-intrinsics-warn.ll
+1-1llvm/test/CodeGen/AMDGPU/deprecated-buffer-intrinsics-warn-loc.ll
+4-72 files

LLVM/project 02fa2ed — llvm/lib/Target/AMDGPU AMDGPUAsmPrinter.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

by Krzysztof Drewniak on ⎇
[AMDGPU] Warn for using <4 x i32> buffer intrinsics

The buffer intrinsics that take their resource as a <4 x i32> have been
documented as deprecated in IntrinsicsAMDGPU.td for some time, but only
in a TableGen comment, so nothing told users about it. They've all got
`ptr addrspace(8)` counterparts now that #209243 landed, so we can be
slightly more official about asking people to move.

The warning lives in AMDGPUAsmPrinter::doInitialization next to the
no-subarch deprecation warning.

We warn once per intrinsic used, not once per call (it'd cause
unbounded warning spam) and not once per declaration (it'd catch the
same intrinsic but with different types repeatedly). We try to be
clever to point at a specific call if we can find one with a debug
location.

Users can pass -amdgpu-warn-deprecated-buffer-intrinsics=0 to suppress
this.

    [5 lines not shown]
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+86-0llvm/unittests/Target/AMDGPU/BufferIntrinsicDeprecationTest.cpp
+60-0llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+58-0llvm/test/CodeGen/AMDGPU/deprecated-buffer-intrinsics-warn.ll
+35-0llvm/test/CodeGen/AMDGPU/deprecated-buffer-intrinsics-warn-loc.ll
+9-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+6-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+254-01 files not shown
+255-07 files

LLVM/project 286b8f0 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll

by Krzysztof Drewniak on ⎇
[AI fixup] Test nits

Address review nits from PR #231308 and clean up stray comment lines:
- Use `< %s` instead of `-o - %s`.
- Spell `-global-isel=0` on the SDAG run lines and `-global-isel=1` on
  the GlobalISel ones, rather than leaving the SDAG lines implicit.
- Drop the runs of bare `;` lines that had accumulated in front of the
  first check of each function. Re-running
  utils/update_llc_test_checks.py does not reintroduce them, and the
  regenerated file is byte-identical to this one.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
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+4-341 files

LLVM/project ab14de3 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll

by Krzysztof Drewniak on ⎇
[AMDGPU][NFC] Add d16 integer coverage for raw.ptr.buffer.load.format

raw.ptr.buffer.load.format didn't have test coverage for the d16
paths, while other related intrinsics (like the non-`.ptr` versions)
did. This commit fixes the issue.

AI disclosure: Claude wrote these tests

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
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+117-21 files