[flang] Lower initial values via ConvertConstant instead of the legacy expression lowering (#210621)
Global and component initial values were lowered with
`createSomeInitializerExpression` (the legacy, non-HLFIR expression
lowering). Route them through ConvertConstant instead, which is
self-contained and safe inside a fir.global initializer region: it never
consults the symbol map, allocates temporaries, or outlines constants
into memory.
Observable IR change: fir.no_reassoc no longer appears in fir.global
initializer regions for parenthesized scalar/derived constants. Update
global-initialization-parens.f90 -- previously a pre-commit baseline
pinning the old fir.no_reassoc behavior -- to assert the new folded
form, and add common-block-derived-initialization.f90 (a
DATA-initialized common block with a derived-type member).
Assisted-by: AI
[flang][OpenMP] Lower iterator indices with genExprValue instead of the legacy expression lowering (#210385)
`getIteratorElementIndices()` lowered the depend/affinity iterator
subscript expressions with `createSomeExtendedExpression` (the legacy,
non-HLFIR expression lowering). Switch it to
`AbstractConverter::genExprValue`, matching the idiom already used
elsewhere in OpenMP/Utils.cpp, so this code no longer depends on the
legacy expression lowering.
The iterator LIT tests are updated to reflect the induction values now
being materialized in memory (store + hlfir.declare + load) and the
subscript arithmetic lowering through HLFIR (hlfir.no_reassoc instead of
fir.no_reassoc).
Assisted-by: AI
[clang] Use 0 for wasm_funcref in non-Wasm address space maps (NFCI) (#210253)
The __funcref keyword is only supported by the WebAssembly target, so
the wasm_funcref entries in other targets' address space maps are
unused.
Use 0 for these entries, which is consistent with other unsupported
address spaces.
[lldb][RISCV] Fix x8 register aliasing for gdb-remote targets (#209070)
GDB remote target descriptions can expose the RISC-V `x8` register as
`fp`. LLDB previously used `fp` as the primary name and `s0` as the
alternate name, leaving no register name for `x8`.
This commit changes `s0` as the primary name, `x8` as the alternate
name, and mark the register as the generic frame pointer. Allowing `fp`,
`s0`, and `x8` to resolve to the same register.
Fixes #127900
[clang-tidy][docs] Remove obsolete doc8 instructions. NFC. (#210576)
Remove the doc8 setup and invocation instructions from the contributing
guide as clang-tidy documentation transitions to Markdown.
Part of https://github.com/llvm/llvm-project/issues/201242
[GlobalISel] Add `isKnownNeverZero` to `GISelValueTracking` (#198438)
## Summary of changes
* This patch adds `GISelValueTracking::isKnownNeverZero`, modeled after
the SelectionDAG query, and uses it in the GlobalISel count-zero
combiner.
* The root combines enabled by this patch are:
* `G_CTLZ x -> G_CTLZ_ZERO_POISON x`
* `G_CTTZ x -> G_CTTZ_ZERO_POISON x`
* The combine only fires when the source is known nonzero and the
zero-poison opcode is legal, or when the combiner is running before
legalization.
* For the initial proof set, this patch handles `G_OR`, `G_SELECT`, and
`G_SHL`. These are not new root combines; they are source-expression
cases used by `isKnownNeverZero` to prove that the input to `G_CTLZ` /
`G_CTTZ` is nonzero. Other structural cases can be added in follow-up
patches. For other opcodes, the query falls back to existing KnownBits
[21 lines not shown]
[CycleInfo] Identify cycles with a single-pass DFS algorithm (#210491)
Replace the Havlak-Tarjan construction in GenericCycleInfoCompute, a DFS
followed by a reverse-preorder scan, with the single-pass algorithm of
Wei, Mao, Zou and Chen, "A New Algorithm for Identifying Loops in
Decompilation" (SAS 2007). One depth-first traversal tags every block
with its innermost loop header on the fly; tagLoopHeader weaves the
per-block header chains, replacing UNION-FIND.
The flat forest is reconstructed from the tags, dropping the temporary
cycle objects and the per-block worklist passes. An edge re-entering an
already-closed cycle records non-header entries, so entries need no
predecessor scan.
The cycle sets, headers, reducibility and nesting are identical for the
given DFS order, cross-checked against the old construction on random
reducible and irreducible CFGs. Two implementation-defined orders change
(with minor test churn): sibling cycles are laid out in decreasing
header preorder, and non-header entries in block preorder.
[6 lines not shown]
Revert "[flang][OpenMP] Fix new metadirective-loop-nest.f90 test expectation with collapse changes in #208528" (#210860)
Reverts llvm/llvm-project#210753
Revert with #208528 pending llvm-test-suite fix.
[Clang][AIX] Switch -mloadtime-comment-vars name matching to mangled IR names
Replace source-qualified name matching in matchesLoadTimeCommentVarName with
mangled IR symbol name matching via getMangledName(GlobalDecl(VD)).
[ProfileData] Refactor SampleProfileNameTable into a polymorphic class hierarchy (NFC) (#210252)
This patch refactors SampleProfileNameTable into an abstract base
class with concrete derived classes like LazySampleProfileNameTable
and EagerSampleProfileNameTable.
The motivation is twofold:
- I want each derived class to focus on one data representation
instead of using complex if-then-else. Plus, I'm planning to
introduce one more data representation [1].
- I want each class to be populated and ready for use as soon as it is
constructed. That is, there is no intermediate state like
"constructed but waiting to be populated".
Now, you might notice that the iterator uses virtual operator[]. I
would argue that this is acceptable. We have three places where we
iterate over the entire range of the name table entries. Two of
[8 lines not shown]
[TableGen] Add sub-register overflow tests for exact-fit and non-covered registers (#210529)
Follow-up to #206346. Adds two cases the overflow check's companion test
missed: an exact-fit tiling that must be accepted, and a register
without `CoveredBySubRegs` that must be left alone. Test only.
[NFC][SLP] Precommit tests for ordered fadd-reduction FMA-fusion cost (#210835)
Baseline coverage for an ordered fadd-of-fmul reduction that is
currently vectorized even on FMA-capable targets, breaking the scalar
fmul + fadd -> fma fusion. A follow-up teaches the reduction cost model
to account for the lost fusion and keep these reductions scalar, at
which point these CHECK lines update. Covers X86 avx2, AMDGPU gfx90a and
NVPTX sm_80.
It is a pre-requisite for
https://github.com/llvm/llvm-project/pull/210399
Assisted-By: Claude Opus 4.8
