LLVM/project 74b6413llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-allocate.ll as-vgpr-across-call.ll

Do not add a second lifetime start when allocating VGPRs again
DeltaFile
+21-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+17-3llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+0-1llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+38-43 files

LLVM/project 8c52b03llvm/lib/Target/AMDGPU AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-asm-clobber.ll

Diagnose inline asm that clobbers a VGPR-memory object's registers
DeltaFile
+93-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-asm-clobber.ll
+31-5llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+124-52 files

LLVM/project f5f16ecllvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp AMDGPUPrivateObjectVGPRs.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-across-call.ll as-vgpr-private-object-vgprs.mir

Allocate and reserve registers for address space 13 objects
DeltaFile
+340-0llvm/lib/Target/AMDGPU/AMDGPUPrivateObjectVGPRs.cpp
+178-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-object-regalloc.ll
+140-12llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+133-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-allocate.ll
+106-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-private-object-vgprs.mir
+80-0llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-across-call.ll
+977-1218 files not shown
+1,280-2324 files

LLVM/project 42a986f.github/workflows libcxx-pr-conformance-tests.yaml, libcxx/include/__functional weak_result_type.h

[libc++] Upgrade to GCC 16 (#206235)

This also removes a few `// UNSUPPORTED: gcc` which are unnecessary as a
drive-by.
DeltaFile
+8-3libcxx/include/__functional/weak_result_type.h
+0-9libcxx/test/std/utilities/utility/pairs/pairs.pair/assign_pair.pass.cpp
+4-4.github/workflows/libcxx-pr-conformance-tests.yaml
+0-6libcxx/src/experimental/time_zone.cpp
+2-3libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/is_implicit_lifetime.pass.cpp
+2-3libcxx/include/__ranges/concat_view.h
+16-2820 files not shown
+44-4726 files

LLVM/project 1b3b7e5llvm/lib/Target/X86 X86PartialReduction.cpp, llvm/test/CodeGen/X86 byte-sum.ll

[X86][PartialReduction] Lower zext-byte add reductions to vpsadbw (#201076)

Loops of the form `for (i) sum += bytes[i];` (`uint8_t` input, `i32`/`i64` accumulator)
lower to `vpmovzxbd` + `vpaddd` today, although `PSADBW(x, 0)`
computes the same sum in one instruction per 128/256/512-bit lane.

Teach `X86PartialReduction` to rewrite the `zext <N x i8> to <N x i32|i64>`
leaves of an add reduction (N >= 16) into `PSADBW(x, 0)`, split across
SSE2/AVX2/AVX-512BW lanes per the subtarget. `i64` accumulators consume
`PSADBW`'s natural `<N/8 x i64>` output directly.

Tests: `x86-partial-reduction-byte-sum*.ll` (matcher in isolation),
`byte-sum-{positive,negative}.ll` (full CodeGen on +sse2/+avx2/+avx512bw).
DeltaFile
+1,278-0llvm/test/CodeGen/X86/byte-sum.ll
+679-0llvm/test/Transforms/PhaseOrdering/X86/x86-partial-reduction-byte-sum.ll
+115-1llvm/lib/Target/X86/X86PartialReduction.cpp
+43-0llvm/test/Transforms/PhaseOrdering/X86/x86-partial-reduction-byte-sum-debugloc.ll
+2,115-14 files

LLVM/project 7c517dallvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR as-vgpr-unsupported.ll

Reject under-aligned whole-dword VGPR-memory accesses
DeltaFile
+34-8llvm/test/CodeGen/AMDGPU/AddressSpaceVGPR/as-vgpr-unsupported.ll
+14-7llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+14-6llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+62-213 files

LLVM/project e4a3922llvm/include/llvm/Analysis VectorUtils.h, llvm/lib/Transforms/Vectorize LoopVectorizationLegality.cpp

Fixups
DeltaFile
+1-2llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+1-1llvm/include/llvm/Analysis/VectorUtils.h
+2-32 files

LLVM/project 77673e2llvm/lib/Frontend/OpenMP OMPDescriptors.inc

Apply property-related errata for 6.0 spec
DeltaFile
+4-4llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
+4-41 files

LLVM/project 17930a3lldb/source/Plugins/Process/Linux NativeRegisterContextLinux_arm64.h NativeRegisterContextLinux_arm64.cpp

[lldb][AArch64][Linux] Add function to get register buffers (#213977)

Replaces Get<set>Buffer methods.
DeltaFile
+115-63lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+2-22lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+117-852 files

LLVM/project 42b0f56llvm/lib/Target/AArch64 AArch64SVEInstrInfo.td, llvm/test/CodeGen/AArch64 vector-absolute-difference.ll

[LLVM][CodeGen][SVE] Prefer uadalp over sabalb/sabalt. (#216301)

Partially reverts https://github.com/llvm/llvm-project/pull/212800
becuase for SVE2 using uadalp has better accumulator throughput than a
sabalb/sabalt sequence.
DeltaFile
+24-12llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
+0-14llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+24-262 files

LLVM/project 0132faclldb/test/API/tools/lldb-dap/attach TestDAP_attachByPortNum.py

[lldb-dap] Spawn debug sever in the build directory. (#216078)

The debugserver may create files such as the socket in the working
directory.
DeltaFile
+4-1lldb/test/API/tools/lldb-dap/attach/TestDAP_attachByPortNum.py
+4-11 files

LLVM/project f5418f3llvm/lib/Target/X86 X86InstrInfo.cpp, llvm/test/CodeGen/X86/apx memfold-remat-physreg.ll

[X86][APX] Add missing VRM argument (#216240)

It happens when a rematerialized load is from global variable, see
https://godbolt.org/z/ddsh8PP4K

Assisted-by: Claude Opus 4.8
DeltaFile
+74-0llvm/test/CodeGen/X86/apx/memfold-remat-physreg.ll
+1-1llvm/lib/Target/X86/X86InstrInfo.cpp
+75-12 files

LLVM/project 3faf820clang/include/clang/CIR/Dialect/IR CIRDialect.h CIRAttrs.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Drop `cir.offload.container` and represent offload modules through a unit market on MLIR modules.
DeltaFile
+106-60clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+52-26clang/test/CIR/IR/invalid-offload-container.cir
+0-59clang/include/clang/CIR/Dialect/IR/CIROps.td
+42-0clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
+17-21clang/test/CIR/IR/offload-container.cir
+12-0clang/include/clang/CIR/Dialect/IR/CIRDialect.h
+229-1661 files not shown
+232-1667 files

LLVM/project 207f72dlldb/packages/Python/lldbsuite/test decorators.py

[lldb] introduce the requireMacOS decorator (#216135)

This is not used in llvm.org yet, but will be used in swiftlang with
https://github.com/swiftlang/llvm-project/pull/13750.
DeltaFile
+7-0lldb/packages/Python/lldbsuite/test/decorators.py
+7-01 files

LLVM/project acd9446clang/docs ClangFormatStyleOptions.rst ClangFormatStyleOptions.md, clang/include/clang/Basic AttrDocs.td

Merge branch 'main' into users/Men-cotton/cir/attach-opencl-kernel-arg-metadata
DeltaFile
+13,767-6,856llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-sve-instructions.s
+6,347-3,146llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-neon-instructions.s
+4,558-4,154clang/include/clang/Basic/AttrDocs.td
+8,221-0clang/docs/ClangFormatStyleOptions.md
+0-8,004clang/docs/ClangFormatStyleOptions.rst
+3,980-3,687llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+36,873-25,84712,377 files not shown
+734,321-388,01712,383 files

LLVM/project a4bea99flang/docs Extensions.md, flang/include/flang/Support Fortran-features.h

[flang] Add warning when BOZ literal is too large for assignment (#210749)

Generate a warning when a BOZ literal assignment does not fit into the
left-hand side variable.

AI use disclaimer: Github CoPilot assisted with this PR. I manually
reviewed and tested the code.

Co-authored-by: John Otken john.otken at hpe.com

---------

Co-authored-by: John Otken <john.otken at hpe.com>
DeltaFile
+26-0flang/test/Semantics/boz-truncation.f90
+11-0flang/lib/Semantics/expression.cpp
+2-1flang/include/flang/Support/Fortran-features.h
+1-0flang/lib/Support/Fortran-features.cpp
+1-0flang/docs/Extensions.md
+41-15 files

LLVM/project 3d0f993clang/unittests/Interpreter InterpreterExtensionsTest.cpp, llvm/lib/ExecutionEngine/Orc LLJIT.cpp

Remove incompatible triple error
DeltaFile
+0-52llvm/unittests/ExecutionEngine/Orc/LLJITTest.cpp
+2-8llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
+1-1clang/unittests/Interpreter/InterpreterExtensionsTest.cpp
+0-1llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
+3-624 files

LLVM/project 6baa105clang Maintainers.md

Add John McCall as Swift conformance maintainer (#216041)

We've had a small number of PRs and issues come up that touch on Swift,
so this adds John as the point of contact for Swift related concerns as
they come up in Clang.
DeltaFile
+6-0clang/Maintainers.md
+6-01 files

LLVM/project 4918b51clang/test/CIR/Analysis alias-analysis-underlying-object.cir

[CIR] Fix test added in #215683 (#216286)
DeltaFile
+9-9clang/test/CIR/Analysis/alias-analysis-underlying-object.cir
+9-91 files

LLVM/project 619937fllvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS GenericMemoryManagerProxySpecs.h MemoryAccessProxySpecs.h, llvm/include/llvm/ExecutionEngine/Orc/Shared/SPSCI NativeDylibManagerSPSCI.h CallSPSCI.h

[ORC] Give the SPS controller interface a home in OrcShared (#216275)

The proxy specs in Orc/RTBridge/SPS fused the wire contract (an
operation's controller-interface symbol name and SPS signature) with the
controller-side machinery that calls it. This was dragging Orc Core APIs
(e.g. ExecutionSession) into the OrcTargetProcess library via
OrcRTBootstrap.cpp.

Fix this by introducing Orc/Shared/SPSCI, holding one descriptor per
operation:

  struct MemWriteUInt8s {
    static constexpr char Name[] = "orc_rt_ci_sps_mem_write_uint8s";
    using SPSSig = void(SPSSequence<SPSMemoryAccessUInt8Write>);
  };

The filenames mirror orc-rt/include/orc-rt/sps-ci/*SPSCI.h, so the two
sides of each contract pair up by name. ProxySpec now takes a descriptor
in place of a signature and a name pointer:

    [12 lines not shown]
DeltaFile
+17-87llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/MemoryAccessProxySpecs.h
+102-0llvm/include/llvm/ExecutionEngine/Orc/Shared/SPSCI/MemoryAccessSPSCI.h
+72-0llvm/include/llvm/ExecutionEngine/Orc/Shared/SPSCI/SimpleNativeMemoryMapSPSCI.h
+60-0llvm/include/llvm/ExecutionEngine/Orc/Shared/SPSCI/CallSPSCI.h
+52-0llvm/include/llvm/ExecutionEngine/Orc/Shared/SPSCI/NativeDylibManagerSPSCI.h
+10-41llvm/include/llvm/ExecutionEngine/Orc/RTBridge/SPS/GenericMemoryManagerProxySpecs.h
+313-12814 files not shown
+443-30220 files

LLVM/project 21ab522llvm/include/llvm/Analysis IVDescriptors.h, llvm/lib/Analysis IVDescriptors.cpp

Fixups
DeltaFile
+2-2llvm/include/llvm/Analysis/IVDescriptors.h
+1-1llvm/lib/Analysis/IVDescriptors.cpp
+3-32 files

LLVM/project 0bdcce7llvm/lib/Target/AMDGPU AMDGPUPreloadKernelArguments.cpp, llvm/test/CodeGen/AMDGPU preload-implicit-kernargs-IR-lowering.ll

[AMDGPU] Skip pointer users with no uses when preloading kernel args (#216281)

A dead GEP has no users, so dereferencing user_begin() looking for a
load hits the end iterator and asserts
DeltaFile
+18-0llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-IR-lowering.ll
+2-1llvm/lib/Target/AMDGPU/AMDGPUPreloadKernelArguments.cpp
+20-12 files

LLVM/project ad74217clang/lib/CodeGen BackendUtil.cpp, clang/lib/Driver/ToolChains Clang.cpp

Revert "[dyndbg][Clang] Implement nested-ELF dynamic debugging support" (#216298)

Reverts llvm/llvm-project#194860

failure example:
https://lab.llvm.org/buildbot/#/builders/154/builds/35126
DeltaFile
+1-110clang/lib/CodeGen/BackendUtil.cpp
+0-72clang/test/DebugInfo/DynamicDebugging/symbols-globals.cpp
+0-37clang/test/DebugInfo/DynamicDebugging/compiler-used.cpp
+2-35clang/lib/Driver/ToolChains/Clang.cpp
+0-33clang/test/DebugInfo/DynamicDebugging/symbols-functions.cpp
+0-32clang/test/Driver/dynamic-debugging-flags.c
+3-31920 files not shown
+11-53926 files

LLVM/project c0d54f1clang/lib/CodeGen BackendUtil.cpp, clang/lib/Driver/ToolChains Clang.cpp

Revert "[dyndbg][Clang] Implement nested-ELF dynamic debugging support (#194860)"

This reverts commit c024bb531b2158fe13c9678c78e134710ec56510.
DeltaFile
+1-110clang/lib/CodeGen/BackendUtil.cpp
+0-72clang/test/DebugInfo/DynamicDebugging/symbols-globals.cpp
+0-37clang/test/DebugInfo/DynamicDebugging/compiler-used.cpp
+2-35clang/lib/Driver/ToolChains/Clang.cpp
+0-33clang/test/DebugInfo/DynamicDebugging/symbols-functions.cpp
+0-32clang/test/Driver/dynamic-debugging-flags.c
+3-31920 files not shown
+11-53926 files

LLVM/project 6d189e5llvm/docs NVPTXUsage.md, llvm/include/llvm/IR IntrinsicsNVVM.td

[NVVM][NVPTX] Add tensor map override support in S2G and Reduce intrinsics (#215503)

This change adds support for tensor map override in S2G and Reduce
intrinsics. These variants allow overriding tensor map properties.
DeltaFile
+512-0llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce-override.ll
+243-0llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-override.ll
+178-16llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+182-0llvm/docs/NVPTXUsage.md
+131-3llvm/include/llvm/IR/IntrinsicsNVVM.td
+1,246-195 files

LLVM/project 879d325llvm/include/llvm/ADT GenericSSAContext.h GenericUniformityImpl.h, llvm/lib/CodeGen MachineSSAContext.cpp

[UniformityAnalysis] Mark divergent cycle-exit PHIs selecting differing values
DeltaFile
+129-0llvm/test/Analysis/UniformityAnalysis/AMDGPU/divergent-cycle-exit-phi.ll
+57-0llvm/include/llvm/ADT/GenericUniformityImpl.h
+17-0llvm/lib/CodeGen/MachineSSAContext.cpp
+16-0llvm/lib/IR/SSAContext.cpp
+7-0llvm/include/llvm/ADT/GenericSSAContext.h
+226-05 files

LLVM/project 22a6dc1lldb/test/API/tools/lldb-server TestGdbRemoteThreadsInStopReply.py

[lldb][test] Check debugserver's expedited memory in its replies (#216165)

debugserver expedites memory in two replies and no test asserts any of it is there.

`test_stop_reply_expedites_frame_pointer_backchain` checks the stop reply: every
`memory:` entry carries `2 * ptrsize` bytes, and there are at most two, the cap
that keeps the reply small. The count is not pinned to exactly two, how far the
walk gets depends on where the backchain terminates.

`test_threads_info_expedites_stopped_frame_stack` checks `jThreadsInfo` by chunk
size: every thread carries at least one backchain entry, the stopped thread
carries one or two chunks that are not, and no other thread carries any. The
addresses are not checked, debugserver anchors frame 0's window at `$fp` or at
`$sp` depending on the inferior's prologue.

Sizes come from `qProcessInfo`, not a hard-coded 16, so they hold on a 32-bit
target. `gather_threads_info` is split out of `gather_threads_info_pcs`.
debugserver only.
DeltaFile
+78-4lldb/test/API/tools/lldb-server/TestGdbRemoteThreadsInStopReply.py
+78-41 files

LLVM/project ff38501lldb/source/Plugins/SymbolFile/NativePDB PdbIndex.cpp PdbSymUid.cpp

[lldb][NativePDB] Migrate away from `lldbassert` (#216152)

`lldbassert` has a note on the lldb docs that reads:
> New code should not be using `lldbassert()` and existing uses should
be replaced by other means of error handling.

(Native)PDB is the largest user of `lldbassert`. This migrates NativePDB
away. I kept the DIA PDB asserts, because we want to remove it
regardless.

There are two main reasons `lldbassert` is used:
1. Checking internal invariants. For example checking that we haven't
already created a type when saving it to a map. I replaced this with
`assert`.
2. Checking for invalid debug info. For example checking that the base
class of a record is another record. I replaced this with a log and
early out. We shouldn't even `assert` here.
DeltaFile
+93-32lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
+44-19lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilderClang.cpp
+15-10lldb/source/Plugins/SymbolFile/NativePDB/PdbUtil.cpp
+13-9lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.cpp
+14-0lldb/source/Plugins/SymbolFile/NativePDB/PdbSymUid.cpp
+6-5lldb/source/Plugins/SymbolFile/NativePDB/PdbIndex.cpp
+185-753 files not shown
+193-809 files

LLVM/project 60b03d4clang/lib/CIR/CodeGen CIRGenModule.cpp, clang/test/CIR/CodeGenOpenCL kernel-arg-info-single-as.cl

fix: document CIR OpenCL kernel argument metadata
DeltaFile
+10-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-2clang/test/CIR/CodeGenOpenCL/kernel-arg-info-single-as.cl
+12-22 files

LLVM/project 79eed78llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/llvm-intrinsics sincos-opencl.ll

[SPIR-V] Avoid dead OpLoad for unused cosine result in llvm.sincos lowering (#215773)
DeltaFile
+6-5llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+11-0llvm/test/CodeGen/SPIRV/llvm-intrinsics/sincos-opencl.ll
+17-52 files