[MLIR][XeGPU] Support Layout propagation for interleave and deintereleave op (#194966)
Enable propagation of interleave and deinterleave with their own
propagation rules.
---------
Co-authored-by: Claude Sonnet 4.5 <noreply at anthropic.com>
[clang][test] Add missing `FileCheck` in Import/destructor/test.cpp (#195778)
The test had `CHECK` directives that were never executed because the
`RUN` line did not pipe output to `FileCheck`. This also replaces
`CHECK-NEXT` with `CHECK-SAME` so the subsequent `CHECK-SAME` directives
match the remaining destructor properties in order.
[AARCH64] Add intrinsic support for new s/udot intrinsics (#189424)
The intrinsics are based on the following
[proposal](https://github.com/ARM-software/acle/pull/428). These are:
```
svint16_t svdot_s16_s8(svint16_t zda, svint8_t zn, svint8_t zm);
svint16_t svdot_n_s16_s8(svint16_t zda, svint8_t zn, int8_t zm);
svint16_t svdot_lane_s16_s8(svint16_t zda, svint8_t zn, svint8_t zm, uint64_t imm_idx);
svuint16_t svdot_u16_u8(svuint16_t zda, svuint8_t zn, svuint8_t zm);
svuint16_t svdot_n_u16_u8(svuint16_t zda, svuint8_t zn, uint8_t zm);
svuint16_t svdot_lane_u16_u8(svuint16_t zda, svuint8_t zn, svuint8_t zm, uint64_t imm_idx);
```
[AMDGPU] Support Wave Reduction for true-16 types - 3
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
[AMDGPU] Support Wave Reduction for i16 types - 3
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
[AMDGPU] Support Wave Reduction for true-16 types - 2
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
[AMDGPU] Support Wave Reduction for i16 types - 2
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
[OpenMP][OMPT] Update tools header for OpenMP v6.0 (#195829)
Add new enum values, structs and variables to `omp-tools.h` header,
according to the OpenMP v6.0 specification.
Update `openmp` and `offload` tools headers to recognize the new values
to ease testing once those features are implemented.
Since no feature is implemented here, update the docs to mention
`partial` support, pointing to this PR for the enums.
---------
Signed-off-by: Jan André Reuter <j.reuter at fz-juelich.de>
[AMDGPU] Support Wave Reduction for true-16 types - 3
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
[libc] Add socket test support library (#193207)
A couple of tests (and I plan to add a couple more) need to
create/compare unix domain socket addresses. This isn't completely
trivial due to the the interaction between the `addrlen` argument and
the terminating '\0', and the existing code doing that was subtly wrong
in some cases.
This patch centralizes the functions for these operations, reducing code
duplication and ensuring consistent (and correct) behavior everywhere.
[AMDGPU] Support Wave Reduction for i16 types - 3
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
[AMDGPU] Support Wave Reduction for true-16 types - 2
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
[AMDGPU] Support Wave Reduction for i16 types - 2
Supported Ops: `add`, `sub`.
Supports only the iterative stratergy, DPP is yet
to be supported.
Supports only Fake-16 versions of the lowering.
True-16 support is yet to be added.
