LLVM/project 14c6949lldb/packages/Python/lldbsuite/test/make Makefile.rules, lldb/test/Shell/helper toolchain.py

Partially revert "[NFCI][lldb][test][asm] Enable AT&T syntax explicitly (#166770)" (#172233)

Flag changes reverted as those require the X86 target to be enabled.  
Don't have time to test fixes as I need to go to sleep so will revert for now.

Reverts: 423919d31f4b55f22b09cd5066534f7c91e71d4b
DeltaFile
+0-7lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+0-4lldb/test/Shell/helper/toolchain.py
+0-112 files

LLVM/project f12fcf0mlir/lib/Bindings/Python IRCore.cpp, mlir/python/mlir/dialects memref.py

[MLIR][Transform][Python] transform.foreach wrapper and .owner OpViews (#172228)

Friendlier wrapper for transform.foreach.

To facilitate that friendliness, makes it so that OpResult.owner returns
the relevant OpView instead of Operation. For good measure, also changes
Value.owner to return OpView instead of Operation, thereby ensuring
consistency. That is, makes it is so that all op-returning .owner
accessors return OpView (and thereby give access to all goodies
available on registered OpViews.)

Reland of #171544 due to fixup for integration test.
DeltaFile
+52-0mlir/test/python/dialects/transform.py
+50-0mlir/python/mlir/dialects/transform/__init__.py
+4-4mlir/lib/Bindings/Python/IRCore.cpp
+1-2mlir/python/mlir/dialects/memref.py
+1-1mlir/test/python/integration/dialects/pdl.py
+108-75 files

LLVM/project 76817c0llvm/test/tools/UpdateTestChecks lit.local.cfg

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+2-1llvm/test/tools/UpdateTestChecks/lit.local.cfg
+2-11 files

LLVM/project 423919dlldb/packages/Python/lldbsuite/test/make Makefile.rules, lldb/test/API/functionalities/disassembler-variables loop_reg_rotate.s live_across_call.s

[NFCI][lldb][test][asm] Enable AT&T syntax explicitly (#166770)

Implementation files using the Intel syntax typically explicitly specify it.
Do the same for the few files using AT&T syntax.

This enables building LLVM with `-mllvm -x86-asm-syntax=intel` in one's Clang config files
(i.e. a global preference for Intel syntax).
DeltaFile
+7-0lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+3-2lldb/test/API/functionalities/disassembler-variables/loop_reg_rotate.s
+4-0lldb/test/Shell/helper/toolchain.py
+2-1lldb/test/API/functionalities/disassembler-variables/live_across_call.s
+2-1lldb/test/API/functionalities/disassembler-variables/d_original_example.s
+1-1lldb/test/API/functionalities/disassembler-variables/Makefile
+19-517 files not shown
+36-523 files

LLVM/project bebc28autils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Port for f785ca0d72cc37ac951afe81cba37c292b0027eb
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project b9fe653mlir/lib/Bindings/Python IRCore.cpp, mlir/python/mlir/dialects memref.py

Revert "[MLIR][Transform][Python] transform.foreach wrapper and .owner OpViews" (#172225)

Reverts llvm/llvm-project#171544 ; bots are broken.
DeltaFile
+0-52mlir/test/python/dialects/transform.py
+0-50mlir/python/mlir/dialects/transform/__init__.py
+4-4mlir/lib/Bindings/Python/IRCore.cpp
+2-1mlir/python/mlir/dialects/memref.py
+6-1074 files

LLVM/project db308edmlir/lib/Bindings/Python IRCore.cpp, mlir/python/mlir/dialects memref.py

Revert "[MLIR][Transform][Python] transform.foreach wrapper and .owner OpView…"

This reverts commit 4cdec92827e6901e077e7f50a382d6acabe7aaf0.
DeltaFile
+0-52mlir/test/python/dialects/transform.py
+0-50mlir/python/mlir/dialects/transform/__init__.py
+4-4mlir/lib/Bindings/Python/IRCore.cpp
+2-1mlir/python/mlir/dialects/memref.py
+6-1074 files

LLVM/project bcbbe2cllvm/lib/Transforms/Vectorize VPlan.h LoopVectorize.cpp

[VPlan] Pass backedge value directly to FOR and reduction phis (NFC).

Pass backedge values directly to VPFirstOrderRecurrencePHIRecipe and
VPReductionPHIRecipe directly, as they must be provided and availbale.

Split off from https://github.com/llvm/llvm-project/pull/168291.
DeltaFile
+13-9llvm/lib/Transforms/Vectorize/VPlan.h
+10-12llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+23-212 files

LLVM/project ab4febcclang/include/clang/CIR/Dialect/IR CIRTypeConstraints.td, clang/lib/CIR/CodeGen CIRGenClass.cpp CIRGenExprAggregate.cpp

[CIR] Add BuildableType traits to relevant constraints (NFC)

This also eliminates some explicit uses of buildable types.
DeltaFile
+41-27clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
+4-4clang/lib/CIR/CodeGen/CIRGenClass.cpp
+2-3clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
+1-4clang/lib/CIR/Dialect/Transforms/LoweringPrepareItaniumCXXABI.cpp
+1-2clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
+1-2clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
+50-421 files not shown
+51-437 files

LLVM/project 4cdec92mlir/lib/Bindings/Python IRCore.cpp, mlir/python/mlir/dialects memref.py

[MLIR][Transform][Python] transform.foreach wrapper and .owner OpViews (#171544)

Friendlier wrapper for `transform.foreach`.

To facilitate that friendliness, makes it so that `OpResult.owner`
returns the relevant `OpView` instead of `Operation`. For good measure,
also changes `Value.owner` to return `OpView` instead of `Operation`,
thereby ensuring consistency. That is, makes it is so that all
op-returning `.owner` accessors return `OpView` (and thereby give access
to all goodies available on registered `OpView`s.)
DeltaFile
+52-0mlir/test/python/dialects/transform.py
+50-0mlir/python/mlir/dialects/transform/__init__.py
+4-4mlir/lib/Bindings/Python/IRCore.cpp
+1-2mlir/python/mlir/dialects/memref.py
+107-64 files

LLVM/project 53cf22fllvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanConstruction.cpp, llvm/test/Transforms/LoopVectorize lcssa-crashes.ll scalable-iv-outside-user.ll

[VPlan] Simplify live-ins early using SCEV. (#155304)

Use SCEV to simplify all live-ins during VPlan0 construction. This
enables us to remove special SCEV queries when constructing
VPWidenRecipes and improves results in some cases.

This leads to simplifications in a number of cases in real-world
applications (~250 files changed across LLVM, SPEC, ffmpeg)

PR: https://github.com/llvm/llvm-project/pull/155304
DeltaFile
+14-22llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
+3-26llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+2-18llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
+6-12llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+18-0llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+2-3llvm/test/Transforms/LoopVectorize/pr58811-scev-expansion.ll
+45-812 files not shown
+48-838 files

LLVM/project 9a33836clang/lib/Sema SemaDecl.cpp, clang/test/Sema warn-lifetime-safety.cpp

merge-attr-implicit-this
DeltaFile
+58-6clang/lib/Sema/SemaDecl.cpp
+22-0clang/test/Sema/warn-lifetime-safety.cpp
+21-0clang/test/SemaCXX/attr-lifetimebound.cpp
+101-63 files

LLVM/project 164217cclang/test/CodeGen/arm-mve-intrinsics compare.c, llvm/test/CodeGen/AArch64 vector-lrint.ll vector-llrint.ll

Merge branch 'main' into users/makslevental/mlirpythonsupport
DeltaFile
+3,030-1,430clang/test/CodeGen/arm-mve-intrinsics/compare.c
+2,502-1,473llvm/test/CodeGen/AArch64/vector-lrint.ll
+1,265-1,312llvm/test/CodeGen/RISCV/idiv_large.ll
+1,301-712llvm/test/CodeGen/AArch64/vector-llrint.ll
+948-980llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+686-883llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
+9,732-6,790803 files not shown
+41,923-17,668809 files

LLVM/project 9975cb1libcxx/include/__expected expected.h, libcxx/test/libcxx/utilities/expected nodiscard.verify.cpp

[libc++][expected] Applied `[[nodiscard]]` (#170245)

[[nodiscard]] should be applied to functions where discarding the return
value is most likely a correctness issue.

- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/expected.bad.void
- https://wg21.link/expected.bad
- https://wg21.link/expected.expected
- https://wg21.link/expected.void
- https://wg21.link/expected.unexpected

It was already discussed not to mark the type `std::expected` as
`[[nodiscard]]` see:
https://github.com/llvm/llvm-project/pull/139651
https://github.com/llvm/llvm-project/pull/130820
Also:
https://github.com/llvm/llvm-project/pull/154943
DeltaFile
+175-0libcxx/test/libcxx/utilities/expected/nodiscard.verify.cpp
+56-56libcxx/include/__expected/expected.h
+8-8libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp
+8-8libcxx/test/libcxx/utilities/expected/expected.void/or_else.mandates.verify.cpp
+8-8libcxx/test/libcxx/utilities/expected/expected.void/and_then.mandates.verify.cpp
+8-8libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp
+263-888 files not shown
+312-13014 files

LLVM/project 3361524llvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU rsq.f32-safe.ll amdgpu-codegenprepare-fdiv.ll

AMDGPU: Stop requiring afn for f32 rsq formation

We were checking for afn or !fpmath attached to the sqrt. We
are not trying to replace a correctly rounded rsqrt; we're replacing
the two correctly rounded operations with the contracted operation.
It's net a better precision, so contract on both instructions should
be sufficient. Both the contracted and uncontracted sequences pass
the OpenCL conformance test, with a lower maximum error contracted.
DeltaFile
+504-1,529llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll
+52-45llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
+6-25llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+562-1,5993 files

LLVM/project a0ae283llvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp

swap
DeltaFile
+3-3llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+3-31 files

LLVM/project 0c6735cllvm/test/CodeGen/AMDGPU rsq.f64.ll amdgpu-codegenprepare-fdiv.f64.ll

nnan not useful
DeltaFile
+8-12llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+6-4llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
+14-162 files

LLVM/project 89df092llvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU rsq.f64.ll amdgpu-codegenprepare-fdiv.f64.ll

AMDGPU: Introduce f64 rsq pattern in AMDGPUCodeGenPrepare

Handle this here instead of DAGCombine, mostly because the f32
case is handled here due to the dependency on !fpmath. Also we can
take advantage of computeKnownFPClass.
DeltaFile
+4,536-3,195llvm/test/CodeGen/AMDGPU/rsq.f64.ll
+309-56llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
+129-12llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+4,974-3,2633 files

LLVM/project 1aa7a1fllvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp

Interested mask bug
DeltaFile
+1-1llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+1-11 files

LLVM/project 5faa732llvm/lib/Target/AMDGPU AMDGPUCodeGenPrepare.cpp

nnan not useful
DeltaFile
+1-3llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+1-31 files

LLVM/project 02e6b0ellvm/test/CodeGen/AMDGPU amdgpu-codegenprepare-fdiv.f64.ll

AMDGPU: Add baseline tests for f64 rsq pattern handling
DeltaFile
+526-0llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
+526-01 files

LLVM/project 1d5805dclang/test/CodeGen/arm-mve-intrinsics compare.c, llvm/lib/Support/rpmalloc rpmalloc.c

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+3,996-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+3,030-1,430clang/test/CodeGen/arm-mve-intrinsics/compare.c
+4,091-0llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
+2,515-1,481llvm/test/CodeGen/AArch64/vector-lrint.ll
+3,051-413llvm/test/CodeGen/X86/bitcnt-big-integer.ll
+2,852-185llvm/test/CodeGen/X86/shift-i512.ll
+19,535-7,5053,775 files not shown
+167,847-84,0773,781 files

LLVM/project 8f93365compiler-rt/lib/tsan/rtl tsan.syms.extra

[tsan] Export __cxa_guard_ interceptors from TSan runtime. (#171921)

These functions from C++ ABI are defined in
compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp and are supposed to
replace implementations from libstdc++/libc++abi.

We need to export them similar to why we need to export other
interceptors and TSan runtime functions - e.g. if a dlopen-ed shared
library depends on `__cxa_guard_acquire`, it needs to pick up the
exported definition from the TSan runtime that was linked into the main
executable calling the dlopen()

However, because the `__cxa_guard_` functions don't use traditional
interceptor machinery, they are omitted from the auto-generated
`libclang_rt.tsan.a.syms` files. Fix this by adding them to
tsan.syms.extra file explicitly.

Co-authored-by: Vitaly Buka <vitalybuka at google.com>
DeltaFile
+3-0compiler-rt/lib/tsan/rtl/tsan.syms.extra
+3-01 files

LLVM/project 4b267d5mlir/lib/Conversion/MemRefToLLVM MemRefToLLVM.cpp, mlir/test/Conversion/MemRefToLLVM invalid.mlir

[MLIR][MemRef] Emit error on atomic generic result op defined outside the region (#172190)

While figuring out how to perform an atomic exchange on a memref, I
tried the generic atomic rmw with the yielded value captured from the
enclosing scope (instead of a plain atomic_rmw with
`arith::AtomicRMWKind::assign`). Instead of segfaulting, this PR changes
the pass to produce an error when the result is not found in the
region's IR map.

It might be more useful to give a suggestion to the user, but giving an
error message instead of a crash is at least an imrovement, I think.

See: #172184
DeltaFile
+12-0mlir/test/Conversion/MemRefToLLVM/invalid.mlir
+6-1mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
+18-12 files

LLVM/project dd33690llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] combineVectorSizedSetCCEquality - convert to mayFoldIntoVector helper (#172215)

Add AssumeSingleUse (default = false) argument to mayFoldIntoVector to
allow us to match combineVectorSizedSetCCEquality behaviour with
AssumeSingleUse=true

Hopefully we can drop the AssumeSingleUse entirely soon, but there are a
number of messy test regressions that need handling first
DeltaFile
+6-8llvm/lib/Target/X86/X86ISelLowering.cpp
+6-81 files

LLVM/project e82edd2lldb/tools/lldb-dap/Handler LocationsRequestHandler.cpp RequestHandler.h, lldb/tools/lldb-dap/Protocol ProtocolRequests.h ProtocolRequests.cpp

[lldb-dap] Migrate locations request to structured types (#171099)

This patch migrates `locations` request into structured types and adds
test for it.
DeltaFile
+32-139lldb/tools/lldb-dap/Handler/LocationsRequestHandler.cpp
+50-0lldb/unittests/DAP/ProtocolRequestsTest.cpp
+35-0lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
+20-0lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
+6-3lldb/tools/lldb-dap/Handler/RequestHandler.h
+143-1425 files

LLVM/project 1d2dff6clang/test/CodeGen/arm-mve-intrinsics compare.c, llvm/lib/Support/rpmalloc rpmalloc.c

Removed empty() check

Created using spr 1.3.7
DeltaFile
+17,522-20,773llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
+8,857-10,952llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+8,840-10,957llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+3,996-3,996llvm/lib/Support/rpmalloc/rpmalloc.c
+4,725-0llvm/test/tools/llvm-mca/RISCV/SpacemitX60/vlseg-vsseg.s
+3,030-1,430clang/test/CodeGen/arm-mve-intrinsics/compare.c
+46,970-48,1085,190 files not shown
+287,696-158,9355,196 files

LLVM/project 9de41eelldb/source/Plugins/SymbolFile/NativePDB UdtRecordCompleter.cpp, lldb/test/Shell/SymbolFile/NativePDB nested-types.cpp ast-types.cpp

[LLDB][NativePDB] Create typedefs in structs (#169248)

Typedef/using declarations in structs and classes were not created with
the native PDB plugin. The following would only create `Foo` and
`Foo::Bar`:
```cpp
struct Foo {
    struct Bar {};
    using Baz = Bar;
    using Int = int;
};
```

With this PR, they're created. One complication is that typedefs and
nested types show up identical. The example from above gives:
```
  0x1006 | LF_FIELDLIST [size = 40, hash = 0x2E844]
           - LF_NESTTYPE [name = `Bar`, parent = 0x1002]
           - LF_NESTTYPE [name = `Baz`, parent = 0x1002]

    [5 lines not shown]
DeltaFile
+43-14lldb/test/Shell/SymbolFile/NativePDB/nested-types.cpp
+26-0lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.cpp
+5-5lldb/test/Shell/SymbolFile/NativePDB/ast-types.cpp
+74-193 files

LLVM/project 8a53c01compiler-rt/test/xray/TestCases/Posix fdr-mode.cpp

[XRay][test] Mark fdr-mode.cpp test as unsupported for RISC-V

Commit c6f501d479e8 fixed an issue where some tests were incorrectly
marked as unsupported for a bootstrapping build. This exposed in our
'slow' full-bootstrap qemu-system CI that the fdr-mode.cpp fails on
RISC-V. We mark it as unsupported. I believe _xray_ArgLoggerEntry needs
to be implemented in xray_trampoline_risc*.S for this to work.
DeltaFile
+2-0compiler-rt/test/xray/TestCases/Posix/fdr-mode.cpp
+2-01 files

LLVM/project 8d7c3fallvm/lib/Target/X86 X86ISelLowering.cpp

[X86] combineVectorSizedSetCCEquality - ensure the load is a normal load (#172212)

Noticed while trying to replace the IsVectorBitCastCheap helper with
mayFoldIntoVector (still some work to do as we have a number of multiuse
cases) - technically its possible for a extload to reach this point.
DeltaFile
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+1-11 files