LLVM/project 8bdbb17llvm/lib/Target/SystemZ/MCTargetDesc SystemZHLASMAsmStreamer.cpp

Fix formatting.
DeltaFile
+3-3llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+3-31 files

LLVM/project cddf8d2llvm/include/llvm/MC MCSymbolGOFF.h, llvm/lib/MC GOFFObjectWriter.cpp

Add back isInSection()

Also add isInEDSection() as simple check.
DeltaFile
+5-12llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+4-0llvm/include/llvm/MC/MCSymbolGOFF.h
+1-1llvm/lib/MC/GOFFObjectWriter.cpp
+10-133 files

LLVM/project f44740aoffload/libomptarget omptarget.cpp interface.cpp, offload/test/offloading struct_mapping_with_pointers.cpp

[NFC][Offload] Fix minor debug print issues introduced in #170425. (#172377)

DeltaFile
+22-22offload/test/offloading/struct_mapping_with_pointers.cpp
+2-1offload/libomptarget/omptarget.cpp
+1-1offload/libomptarget/interface.cpp
+25-243 files

LLVM/project 89658f5clang/bindings/python/tests/cindex test_cursor_language.py

[libclang/python] Fix cindex test for cpp lang (#172368)

Fix typo in cindex.py where the C++ support test was incorrectly named
test_c instead of test_cpp
DeltaFile
+1-1clang/bindings/python/tests/cindex/test_cursor_language.py
+1-11 files

LLVM/project 644fd3bllvm/lib/CodeGen/SelectionDAG SelectionDAGISel.cpp, llvm/test/CodeGen/X86 cfguard-checks.ll

[FastISel] Don't select a CallInst as a BasicBlock in the SelectionDAG fallback if it has bundled ops (#162895)

This was discovered while looking at the codegen for x64 when Control
Flow Guard is enabled.

When using `SelectionDAG`, LLVM would generate the following sequence
for a CF guarded indirect call:
```
        leaq    target_func(%rip), %rax
        rex64 jmpq      *__guard_dispatch_icall_fptr(%rip) # TAILCALL
```

However, when Fast ISel was used the following is generated:
```
        leaq    target_func(%rip), %rax
        movq    __guard_dispatch_icall_fptr(%rip), %rcx
        rex64 jmpq      *%rcx                   # TAILCALL
```


    [12 lines not shown]
DeltaFile
+6-3llvm/test/CodeGen/X86/cfguard-checks.ll
+8-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+14-32 files

LLVM/project b51bba3compiler-rt/lib/sanitizer_common/symbolizer CMakeLists.txt, compiler-rt/lib/sanitizer_common/symbolizer/scripts build_symbolizer.sh

yay

Created using spr 1.3.7
DeltaFile
+0-6compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh
+0-1compiler-rt/lib/sanitizer_common/symbolizer/CMakeLists.txt
+0-72 files

LLVM/project e59cd45compiler-rt/lib/sanitizer_common/symbolizer/scripts build_symbolizer.sh

experiment

Created using spr 1.3.7
DeltaFile
+8-5compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh
+8-51 files

LLVM/project 63ba4c9clang/test/CodeGen/arm-mve-intrinsics compare.c, llvm/test/CodeGen/AArch64 vector-lrint.ll vector-llrint.ll

rebase

Created using spr 1.3.7
DeltaFile
+5,963-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+3,030-1,430clang/test/CodeGen/arm-mve-intrinsics/compare.c
+2,502-1,473llvm/test/CodeGen/AArch64/vector-lrint.ll
+3,310-0llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+1,265-1,312llvm/test/CodeGen/RISCV/idiv_large.ll
+1,301-712llvm/test/CodeGen/AArch64/vector-llrint.ll
+17,371-4,9271,165 files not shown
+67,121-22,2211,171 files

LLVM/project 1ab91d2compiler-rt/lib/sanitizer_common/symbolizer CMakeLists.txt, compiler-rt/lib/sanitizer_common/symbolizer/scripts build_symbolizer.sh

change

Created using spr 1.3.7
DeltaFile
+4-1compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh
+2-2compiler-rt/lib/sanitizer_common/symbolizer/CMakeLists.txt
+6-32 files

LLVM/project 83eea87llvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlanConstruction.cpp

[VPlan] Create header phis once, after constructing VPlan0 (NFC). (#168291)

Together with https://github.com/llvm/llvm-project/pull/168289 &
https://github.com/llvm/llvm-project/pull/166099 we can construct header
phis once up front, after creating VPlan0, as the
induction/reduction/first-order-recurrence classification applies across
all VFs.

Depends on https://github.com/llvm/llvm-project/pull/168289 &
https://github.com/llvm/llvm-project/pull/166099 

PR: https://github.com/llvm/llvm-project/pull/168291
DeltaFile
+36-124llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+105-0llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+6-12llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+11-0llvm/lib/Transforms/Vectorize/VPlanTransforms.h
+158-1364 files

LLVM/project ef95590llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port fa79e0a4001a
DeltaFile
+1-0llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+1-01 files

LLVM/project 4d0bcf4llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/abseil BUILD.gn

[gn build] Port 908a5a8292ea
DeltaFile
+1-0llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/abseil/BUILD.gn
+1-01 files

LLVM/project 5db0d5allvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port 1e15dbe311eb
DeltaFile
+2-0llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+2-01 files

LLVM/project 518c328flang-rt/lib/runtime io-stmt.cpp pseudo-unit.cpp

[flang][runtime] Fix GPU output for multiple statements (#172363)

I recently broke PRINT statements in GPU device code when multiple
PRINTs occur in the same kernel by trying to preserve the allocated
pseudo-unit. This turned out to be a bad idea overall, and I'm reverting
to the original protocol that minimizes allocated memory.
DeltaFile
+4-6flang-rt/lib/runtime/io-stmt.cpp
+3-4flang-rt/lib/runtime/pseudo-unit.cpp
+7-102 files

LLVM/project dbb4f5cllvm/lib/Transforms/Vectorize LoopVectorize.cpp VPlan.h

[VPlan] Set VF scale factor in tryToCreatePartialReduction (NFCI).

Split off unrelated change from approved
https://github.com/llvm/llvm-project/pull/168291/ to land separately as
suggested.
DeltaFile
+5-2llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+7-0llvm/lib/Transforms/Vectorize/VPlan.h
+12-22 files

LLVM/project bbb517cclang/lib/Sema SemaDeclCXX.cpp

Remove `const` from local variable
DeltaFile
+1-1clang/lib/Sema/SemaDeclCXX.cpp
+1-11 files

LLVM/project 5216a8bclang/include/clang/Analysis CFGStmtMap.h

format
DeltaFile
+1-1clang/include/clang/Analysis/CFGStmtMap.h
+1-11 files

LLVM/project 0ac0c16llvm/lib/DebugInfo/BTF BTFParser.cpp

Use `SmallVector` interface
DeltaFile
+1-2llvm/lib/DebugInfo/BTF/BTFParser.cpp
+1-21 files

LLVM/project bf52548llvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

addressed PR171942 review comments
DeltaFile
+3-3llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+3-31 files

LLVM/project d39863fllvm/include/llvm/DebugInfo/BTF BTFParser.h, llvm/lib/DebugInfo/BTF BTFParser.cpp

[llvm] Replace `OwningArrayRef` with `SmallVector` in `BTFParser`

`OwningArrayRef` requires that the size and the capacity are the same. This prevents reusing memory allocations unless the size happens to be exactly the same (which is rare enough we don't even try). Switch to `SmallVector` instead so that we're not repeatedly calling `new[]` and `delete[]`.
DeltaFile
+3-2llvm/lib/DebugInfo/BTF/BTFParser.cpp
+1-1llvm/include/llvm/DebugInfo/BTF/BTFParser.h
+4-32 files

LLVM/project 691b04dllvm/utils/gn/secondary/llvm/test BUILD.gn

[gn] port c81d44942e56
DeltaFile
+1-1llvm/utils/gn/secondary/llvm/test/BUILD.gn
+1-11 files

LLVM/project 30298bdllvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp

Update llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
DeltaFile
+1-1llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+1-11 files

LLVM/project 4b78647llvm/lib/Transforms/Instrumentation MemProfUse.cpp, llvm/test/Transforms/PGOProfile memprof_annotate_indirect_call.test

[MemProf] Add CalleeGUIDs from profile to existing VP metadata (#171495)

Previously, we only synthesized VP metadata with the callee GUIDs from
the memprof profile if no VP metadata already existed (i.e. from PGO).
With this change we will add in any that are not already in the VP
metadata, also with count 1.
DeltaFile
+43-24llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
+22-6llvm/test/Transforms/PGOProfile/memprof_annotate_indirect_call.test
+65-302 files

LLVM/project 908a5a8clang-tools-extra/clang-tidy/abseil UncheckedStatusOrAccessCheck.cpp, clang-tools-extra/docs/clang-tidy/checks/abseil unchecked-statusor-access.rst

[clang-tidy] add abseil-unchecked-statusor-access



Pull Request: https://github.com/llvm/llvm-project/pull/171188
DeltaFile
+427-0clang-tools-extra/test/clang-tidy/checkers/abseil/Inputs/type_traits
+384-0clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
+346-0clang-tools-extra/test/clang-tidy/checkers/abseil/Inputs/absl/status/statusor.h
+138-0clang-tools-extra/test/clang-tidy/checkers/abseil/unchecked-statusor-access.cpp
+69-0clang-tools-extra/test/clang-tidy/checkers/abseil/Inputs/absl/status/status.h
+68-0clang-tools-extra/clang-tidy/abseil/UncheckedStatusOrAccessCheck.cpp
+1,432-07 files not shown
+1,532-013 files

LLVM/project 3c31c84mlir/lib/Dialect/Tosa/Transforms TosaValidation.cpp, mlir/test/Dialect/Tosa tosa-validation-version-1p0-invalid.mlir tosa-validation-version-1p1-valid.mlir

[mlir][tosa] Allow dynamic dims in `--tosa-validate` pass (#171463)

This commit allows tensor dimensions to be dynamic when the specified
target TOSA specification version is `1.1.draft` or higher. This is
because this version of the specification supports representation
operations that are dynamic until backend compile time.
DeltaFile
+15-2mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
+8-0mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
+8-0mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
+31-23 files

LLVM/project 9741a84clang/lib/CodeGen CGExprCXX.cpp

[NFC][HIP] Disable device-side kernel launches for HIP (#171043)

#165519 added support for launching kernels from the device side. This is only available in CUDA at the moment. We have to explicitly check whether we are compiling for HIP to guard against this path being exercised, since the CUDA and HIP languages rely on the same `CUDAIsDevice` bit to check for device side compilation, and it is not possible to disambiguate otherwise.
DeltaFile
+2-1clang/lib/CodeGen/CGExprCXX.cpp
+2-11 files

LLVM/project cbb2aa9llvm/lib/Transforms/InstCombine InstCombineSelect.cpp InstructionCombining.cpp

InstCombine: Replace some isa<FPMathOperator> with dyn_cast (#172356)

This isa and get flag pattern is essentially an abstracted
isa and dyn_cast, so make this more direct.
DeltaFile
+4-4llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+2-2llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+6-62 files

LLVM/project 770719allvm/lib/Target/AMDGPU SIInsertWaitcnts.cpp, llvm/test/CodeGen/AMDGPU waitcnt-loop-ds-opt-eligible.mir

addressed PR171942 review comments
DeltaFile
+19-21llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+2-5llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-opt-eligible.mir
+21-262 files

LLVM/project 478f003clang/include/clang/Analysis CFGStmtMap.h, clang/lib/Analysis CFGStmtMap.cpp

[clang][NFC] In `CFGStmtMap`, remove mutable `getBlock` overload.

The mutable version of the overload is not used. The way we implemented code sharing in the const vs. mutable overloads had a const-correctness violation, anyway.
DeltaFile
+1-5clang/include/clang/Analysis/CFGStmtMap.h
+2-2clang/lib/Analysis/CFGStmtMap.cpp
+3-72 files

LLVM/project 1141669clang/lib/CIR/CodeGen CIRGenStmtOpenMP.cpp, llvm/test/CodeGen/AMDGPU insert_vector_dynelt.ll extract_vector_dynelt.ll

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+5,963-0llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+3,310-0llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+771-910llvm/test/CodeGen/X86/vector-compress.ll
+394-457llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
+689-0llvm/utils/git-llvm-push
+460-0clang/lib/CIR/CodeGen/CIRGenStmtOpenMP.cpp
+11,587-1,367368 files not shown
+22,989-4,521374 files