LLVM/project 59e6f31llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Remove absolute value calculations in the Weak Zero SIV tests
DeltaFile
+7-7llvm/lib/Analysis/DependenceAnalysis.cpp
+7-71 files

LLVM/project 9140528llvm/test/Analysis/DependenceAnalysis weak-zero-siv-addrec-wrap.ll

[DA] Update tests for the Weak Zero SIV tests (NFC)
DeltaFile
+112-0llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-addrec-wrap.ll
+112-01 files

LLVM/project 030571bllvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Consolidate the core logic of the Weak Zero SIV tests (NFCI)
DeltaFile
+80-124llvm/lib/Analysis/DependenceAnalysis.cpp
+5-0llvm/include/llvm/Analysis/DependenceAnalysis.h
+85-1242 files

LLVM/project e60dd7fllvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak-zero-siv-addrec-wrap.ll

[DA] Add nsw check for addrecs in the Weak Zero SIV tests
DeltaFile
+31-16llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-addrec-wrap.ll
+3-0llvm/lib/Analysis/DependenceAnalysis.cpp
+34-162 files

LLVM/project b7992dfllvm/lib/Target/AMDGPU AMDGPULowerKernelAttributes.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h AMDGPUBaseInfo.cpp

Reapply "AMDGPU: Annotate group size ABI loads with range metadata (#185420)"

This reverts commit d5685ac6db0ae4cbca1745f18d8f2f7dc7d673a5.

Fix off by one error. The end of the range is open.
DeltaFile
+122-15llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
+48-19llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
+8-7llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
+8-7llvm/test/CodeGen/AMDGPU/implicit-arg-block-count.ll
+5-2llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+0-5llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+191-552 files not shown
+193-578 files

LLVM/project a682073llvm/lib/Target/X86 X86InstrAVX10.td X86IntrinsicsInfo.h, llvm/test/CodeGen/X86 avx10_2minmax-intrinsics.ll

Fixing upper lane return source for X86 intrinsics (#185329)

Closes https://github.com/llvm/llvm-project/issues/184245
DeltaFile
+57-0llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll
+12-12llvm/lib/Target/X86/X86InstrAVX10.td
+9-6llvm/lib/Target/X86/X86IntrinsicsInfo.h
+78-183 files

LLVM/project 432745fmlir/lib/Dialect/LLVMIR/Transforms InlinerInterfaceImpl.cpp, mlir/test/Dialect/LLVMIR inlining.mlir

[MLIR][LLVMIR] Preserve byval alignment in memcpy after inlining (#185433)

This PR adds alignment attributes to the generated memcpy intrinsics
after inlining functions with byval arguments.
DeltaFile
+20-0mlir/test/Dialect/LLVMIR/inlining.mlir
+11-1mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
+31-12 files

LLVM/project b093513llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Remove absolute value calculations in the Weak Zero SIV tests
DeltaFile
+7-7llvm/lib/Analysis/DependenceAnalysis.cpp
+7-71 files

LLVM/project d47612dllvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak-zero-siv-addrec-wrap.ll

[DA] Add nsw check for addrecs in the Weak Zero SIV tests
DeltaFile
+31-16llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-addrec-wrap.ll
+3-0llvm/lib/Analysis/DependenceAnalysis.cpp
+34-162 files

LLVM/project 0e06371llvm/test/Analysis/DependenceAnalysis weak-zero-siv-addrec-wrap.ll

[DA] Update tests for the Weak Zero SIV tests (NFC)
DeltaFile
+112-0llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-addrec-wrap.ll
+112-01 files

LLVM/project d056888llvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Consolidate the core logic of the Weak Zero SIV tests (NFCI)
DeltaFile
+75-124llvm/lib/Analysis/DependenceAnalysis.cpp
+5-0llvm/include/llvm/Analysis/DependenceAnalysis.h
+80-1242 files

LLVM/project a266f60llvm/test/CodeGen/AArch64 sve2-bf16-converts.ll sve-bf16-converts.ll, llvm/test/CodeGen/PowerPC scalar_cmp.ll

[SelectionDAG] Remove `NoNaNsFPMath` uses (#183448)

This pr removes the rest uses in LLVMCodeGen.
DeltaFile
+112-68llvm/test/CodeGen/AArch64/sve2-bf16-converts.ll
+71-40llvm/test/CodeGen/AArch64/sve-bf16-converts.ll
+15-15llvm/test/CodeGen/X86/avx512fp16-fminimum-fmaximum.ll
+13-13llvm/test/CodeGen/X86/fminimum-fmaximum.ll
+13-13llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll
+10-12llvm/test/CodeGen/PowerPC/scalar_cmp.ll
+234-1619 files not shown
+261-18415 files

LLVM/project 710ce4eclang/lib/Driver/ToolChains AMDGPU.cpp, clang/test/Driver hip-sanitize-options.hip amdgpu-openmp-sanitize-options.c

Revert "[ASan] Enable Internalization for 'asanrtl.bc' in Driver (#18… (#185458)

…2825)"

Enabling internalization of `asanrtl.bc` breaks the asan reporting on
hip side , due to duplicate `__asan_report_XXX` calls in code object and
the llvm-ir.

This reverts commit dc26edd9b6602857b67f35c8d2f6fe4ed13c8137.
DeltaFile
+12-12clang/test/Driver/hip-sanitize-options.hip
+1-1clang/test/Driver/amdgpu-openmp-sanitize-options.c
+1-1clang/lib/Driver/ToolChains/AMDGPU.cpp
+1-1clang/test/Driver/rocm-device-libs.cl
+15-154 files

LLVM/project a2a3708llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Remove absolute value calculations in the Weak Zero SIV tests
DeltaFile
+7-7llvm/lib/Analysis/DependenceAnalysis.cpp
+7-71 files

LLVM/project d140ee5llvm/lib/Analysis DependenceAnalysis.cpp, llvm/test/Analysis/DependenceAnalysis weak-zero-siv-addrec-wrap.ll

[DA] Add nsw check for addrecs in the Weak Zero SIV tests
DeltaFile
+4-4llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-addrec-wrap.ll
+3-0llvm/lib/Analysis/DependenceAnalysis.cpp
+7-42 files

LLVM/project 3b6243ellvm/test/Analysis/DependenceAnalysis weak-zero-siv-addrec-wrap.ll

[DA] Update tests for the Weak Zero SIV tests (NFC)
DeltaFile
+127-0llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-addrec-wrap.ll
+127-01 files

LLVM/project 6907dc1llvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Consolidate the core logic of the Weak Zero SIV tests (NFCI)
DeltaFile
+75-124llvm/lib/Analysis/DependenceAnalysis.cpp
+5-0llvm/include/llvm/Analysis/DependenceAnalysis.h
+80-1242 files

LLVM/project 737b4f4llvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Extract reversing dependence logic (NFCI)
DeltaFile
+10-7llvm/lib/Analysis/DependenceAnalysis.cpp
+6-0llvm/include/llvm/Analysis/DependenceAnalysis.h
+16-72 files

LLVM/project 54b671elibcxx/include optional

[libc++][NFC] Simplify most of `optional.observe` (#185252)

- Hoist `operator*()`, `operator->()`, `value()` into their respective
`optional_storage_base` to reduce the amount of concepts flying around.
- `value_or()` has been deliberately left out since that seems to
produce extra (superfluous) error messages during invalid template
instantiation.
DeltaFile
+75-115libcxx/include/optional
+75-1151 files

LLVM/project 8616f01llvm/test/CodeGen/RISCV ctselect-fallback-vector-rvv.ll ctselect-fallback-edge-cases.ll

[LLVM][RISCV] Regenerate ct.select test CHECK lines

Update CHECK lines to match the new constant-time AND/OR/XOR expansion
from the CT_SELECT legalization fix.
DeltaFile
+132-344llvm/test/CodeGen/RISCV/ctselect-fallback-vector-rvv.ll
+66-78llvm/test/CodeGen/RISCV/ctselect-fallback-edge-cases.ll
+62-77llvm/test/CodeGen/RISCV/ctselect-fallback-patterns.ll
+7-8llvm/test/CodeGen/RISCV/ctselect-side-effects.ll
+267-5074 files

LLVM/project 29f089dllvm/include/llvm/Analysis DependenceAnalysis.h, llvm/lib/Analysis DependenceAnalysis.cpp

[DA] Rewrite formula in the Weak Zero SIV tests
DeltaFile
+31-36llvm/lib/Analysis/DependenceAnalysis.cpp
+8-8llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll
+4-8llvm/include/llvm/Analysis/DependenceAnalysis.h
+2-6llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-overflow.ll
+45-584 files

LLVM/project abaf18ellvm/include/llvm/Frontend/OpenMP OMPIRBuilder.h, llvm/lib/Frontend/OpenMP OMPIRBuilder.cpp

Fix affinity type, handle unexpected iterator loop body and accumulate affinity entry for one register call

- Generate kmpTaskAffinityInfoTy based on platform and create a helper
  in OMPIRBuilder so that we can use it in OpenMPToLLVMIRTranslation and
  OMPIRBuilder
- Handle invalid iterator loop body and add unit test
- Accumulate affinity info and only one register call for a task
  construct
- remove `this->` in member fucntion
DeltaFile
+67-5llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+23-24mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+24-0llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+12-0openmp/runtime/src/kmp_tasking.cpp
+6-2mlir/test/Target/LLVMIR/openmp-iterator.mlir
+4-0llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+136-316 files

LLVM/project 38c934bllvm/test/CodeGen/AArch64 ragreedy-csr.ll, llvm/test/CodeGen/X86 lsr-addrecloops.ll

[LSR][RFC] Improve LCSSA preservation
DeltaFile
+111-116llvm/test/CodeGen/AArch64/ragreedy-csr.ll
+70-37llvm/test/Transforms/LoopStrengthReduce/X86/normalization-during-scev-expansion.ll
+34-37llvm/test/CodeGen/X86/lsr-addrecloops.ll
+34-22llvm/test/Transforms/LoopStrengthReduce/X86/postinc-iv-used-by-urem-and-udiv.ll
+16-10llvm/test/Transforms/LoopStrengthReduce/wrong-hoisting-iv.ll
+7-8llvm/test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll
+272-23037 files not shown
+389-33043 files

LLVM/project 48473ddllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-insert.ll insertelt-int-rv32.ll

[RISCV] Handle sign_extend of i32 in insert_vector_elt for RV32 (#185548)

On RV32 with <N x i64> vectors, inserting a value that is a
sign_extend of an i32 only uses the lower 32 bits, so it can be
lowered without scalar legalization, same as i32 constants.
DeltaFile
+12-6llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+17-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
+12-0llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
+41-63 files

LLVM/project 269b17aclang/lib/AST/ByteCode PrimType.h Compiler.cpp, clang/test/AST/ByteCode c.c

[clang][bytecode] Check for integral types in evaluateStrlen (#185481)

The pointer might point to a primitive array of non-integer type.
DeltaFile
+20-18clang/lib/AST/ByteCode/PrimType.h
+10-9clang/lib/AST/ByteCode/Compiler.cpp
+7-0clang/test/AST/ByteCode/c.c
+4-1clang/lib/AST/ByteCode/Context.cpp
+1-1clang/lib/AST/ByteCode/Interp.h
+1-1clang/lib/AST/ByteCode/InterpBuiltin.cpp
+43-306 files

LLVM/project 02ef01dclang/test/AST/ByteCode constexpr.c

[Clang] Remove clang/test/AST/Bytecode/constexpr.c (#185447)

Remove duplicate test since Sema/constexpr.c handles the constexpr
tests.
Discussed in #181965
DeltaFile
+0-370clang/test/AST/ByteCode/constexpr.c
+0-3701 files

LLVM/project b47ea96libc/src/__support/math inv_trigf_utils.h acospif.h, libc/test/src/math/exhaustive asinpif_test.cpp

[libc][math] correct the output of `asinpif` and `acospi` (#185544)

Currently, we have accuracy issues and some points fail in the asinpif
exhaustive test. This change fixes it by increasing the degree of the
used polynomial

```
-- Testing for FE_TONEAREST in range [0x0, 0x7f800000) --
Failed to match Func(x) against LIBC_NAMESPACE::testing::mpfr::get_mpfr_matcher<Op>( x, Func(x), 0.5, rounding).
Match value not within tolerance value of MPFR result:
  Input decimal: 0.00000011348398487598387873731553554534912109375000
     Input bits: 0x33F3B47B = (S: 0, E: 0x0067, M: 0x0073B47B)

  Match decimal: 0.00000003612307253320068411994725465774536132812500
     Match bits: 0x331B25BD = (S: 0, E: 0x0066, M: 0x001B25BD)

    MPFR result: 0.00000003612307608591436292044818401336669921875000
   MPFR rounded: 0x331B25BE = (S: 0, E: 0x0066, M: 0x001B25BE)


    [41 lines not shown]
DeltaFile
+26-21libc/src/__support/math/inv_trigf_utils.h
+7-5libc/src/__support/math/acospif.h
+3-3libc/test/src/math/exhaustive/asinpif_test.cpp
+2-2libc/test/src/math/smoke/acospif_test.cpp
+38-314 files

LLVM/project a17289bclang/include/clang/Basic BuiltinsAMDGPU.td, clang/test/CodeGenHIP builtins-amdgcn-gfx12-f16-w64.hip builtins-amdgcn-gfx12-f16-w32.hip

[Clang][AMDGPU] Change __fp16 to _Float16 in builtin definitions (#185446)

Change the type signature of `SWMMAC, load, cvt` builtins from `__fp16
to _Float16` in the tablegen builtin definitions.
DeltaFile
+96-0clang/test/CodeGenHIP/builtins-amdgcn-gfx12-f16-w64.hip
+96-0clang/test/CodeGenHIP/builtins-amdgcn-gfx12-f16-w32.hip
+88-0clang/test/CodeGenHIP/builtins-amdgcn-f16-misc.hip
+70-0clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-f16-misc.hip
+27-0clang/test/CodeGenHIP/builtins-amdgcn-gfx950-f16.hip
+13-13clang/include/clang/Basic/BuiltinsAMDGPU.td
+390-138 files not shown
+399-2214 files

LLVM/project 5464d68clang/lib/CodeGen CGHLSLBuiltins.cpp, clang/lib/Headers/hlsl hlsl_alias_intrinsics.h

[HLSL][DXIL][SPRIV] Added WaveActiveProduct intrinsic (#184645)

From issue #99165, adds the implementation of WaveActiveProduct. This
time with the new types for SPIRVTypeInst

- [x] Implement WaveActiveProduct clang builtin,
- [x] Link WaveActiveProduct clang builtin with hlsl_intrinsics.h
- [x] Add sema checks for WaveActiveProduct to
CheckHLSLBuiltinFunctionCall in SemaChecking.cpp
- [x] Add codegen for WaveActiveProduct to EmitHLSLBuiltinExpr in
CGBuiltin.cpp
- [x] Add codegen tests to
clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl
- [x] Add sema tests to
clang/test/SemaHLSL/BuiltIns/WaveActiveProduct-errors.hlsl
- [x] Create the int_dx_WaveActiveProduct intrinsic in
IntrinsicsDirectX.td
- [x] Create the DXILOpMapping of int_dx_WaveActiveProduct to 119 in
DXIL.td

    [8 lines not shown]
DeltaFile
+143-0llvm/test/CodeGen/DirectX/WaveActiveProduct.ll
+123-0clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
+55-38llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+45-0clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl
+41-0llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveProduct.ll
+33-7clang/lib/CodeGen/CGHLSLBuiltins.cpp
+440-459 files not shown
+507-4615 files

LLVM/project cf2d599clang/test/Driver/print-enabled-extensions riscv-xt-c920v2.c riscv-xt-c910v2.c, llvm/lib/Target/RISCV RISCVFeatures.td

[RISCV] Make Zbc imply Zbkc. (#185543)

Zbkc contains 2 of the 3 instructions from Zbc. Making Zbc imply Zbkc
will make the __riscv_zbkc define be set when Zbc is enabled.

This does not change the diagnostics printed by the assembler.

There's a PR to add this rule to the ISA manual too
https://github.com/riscv/riscv-isa-manual/pull/2524
DeltaFile
+8-7llvm/lib/Target/RISCV/RISCVFeatures.td
+2-2llvm/test/CodeGen/RISCV/attributes.ll
+2-1clang/test/Driver/print-enabled-extensions/riscv-xt-c920v2.c
+2-1clang/test/Driver/print-enabled-extensions/riscv-xt-c910v2.c
+1-1llvm/test/MC/RISCV/attribute-arch.s
+15-125 files