[SSAF][clang-reforge] Add end-to-end clang-reforge tests
- Make CppBoundedBuffers adapt to flattened WPA results;
- Let CppBoundedBuffers use qualified EntityNames so that it can
associate ASTNodes with WPA results;
- Add end-to-end tests
Final step of:
rdar://185840466
[SSAF] Fix stage-2 clang build error on TestTransformationPlugin
The plugin code defines the extern variable
SSAFTestTransformationAnchorSource, which is supposed to be used to
force static linking, so not needed here.
The variable definition should undoubtedly be removed, as doing so
solves the build issue locally. The explanation below regarding why
this variable causes the issue was provided by Claude. I repeatedly
asked Claude questions, and he revised his reasoning several times
until it became consistent. However, we should still take the
following explanation with a grain of salt:
ASan created a private alias symbol for the extern variable
SSAFTestTransformationAnchorSource. The linker, when in
'-flat_namespace' mode, treated the symbol as a name-based bind, which
later failed to be resolved through name searching by the loader.
rdar://185749574
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[mlir][IR] Require inherent symbol attributes for Symbol operations (#218920)
Require SymbolTable operations to implement SymbolOpInterface and store
symbol names and visibility as inherent attributes.
Add missing symbol properties/interfaces to GPU, OpenACC, OpenMP, EmitC,
and Toy operations, and update affected tests and the GPU Python
builder.
Assisted-by: Codex
[LV] Support EVL for partial reduction and VPExpressionRecipe. (#205741)
This patch adds the support for partial reduction with EVL tail-folding
by not creating a new VPExpressionEVLRecipes but just changing the last
expressionRecipes from VPReductionRecipe to VPReductionEVLRecipe.
Currently, all partial reductions will be converted to
VPExpressionRecipe
when construction. So this patch also supports the VPExpressionRecipe
for EVL.
[BOLT][RISCV] Avoid evaluating indirect branches as direct branches (#218088)
The RISC-V branch evaluator can resolve JALR when the base register
state is known. In particular, jalr zero, zero, 0 evaluates to address
zero even though it remains an indirect branch.
Do not send indirect branches through the direct branch symbolization
path. Leave them to the existing indirect branch handling instead.
Add a regression test modeling a tail call to an undefined weak symbol
relaxed by GNU ld.
[CIR][AARCH64] Fix neon conversion test (#219069)
This fixes the neon intrinsics test, which has been failing since a
recent change to introduce more conversion handling. The test had an
inadvertantly repeated CIR check.
Revert "Revert "workflows/release-binaries: Disable flang on Darwin (#164667)"" (#218978)
Reverts llvm/llvm-project#216667
This change was ported to the `release/23.x` branch in #217059, and when
we created the first release that included this change (3.1.0), the job
for the MacOS ARM binaries was killed when the job hit the 6 hour mark.
Previous 3.1.0-rc release did not include this change and all completed
well within the 6 hour time out.
To enable the job that builds the release binaries to complete within
the allotted time, I am reverting this change which will essentially
disable flang from building on Darwin.
In the future if we get faster builders, we can explore re-enabling
building flang.
[ELF] Avoid repeated scans when merging strings
Build per-worker shard lists before inserting merge pieces. This keeps
each shard's input order deterministic while avoiding a full scan of every
piece by every worker. Reuse SectionPiece::outputOff for packed temporary
(section, piece) links.
Both the worker and shard counts are capped at 32,
as a result the auxiliary list storage is bounded at 16 KiB
regardless of the number of input sections.
Focused benchmark on Linux 6.16, Btrfs, 16 pinned CPUs, --threads=16. The
input is 16 copies of an object containing 2,000,000 identical mergeable
strings (32,000,000 pieces total) averaged across 20 runs and 3 warmups.
(RSS is the median)
wall CPU RSS
before 0.353 s 1.523 s 682.5 MiB
after 0.343 s 1.167 s 682.7 MiB
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[mlir][Linalg] Split explicit inherent/discardable attribute APIs access (#218916)
Migrate Linalg, Bufferization, and MemRef users to explicit discardable
or operation-specific attribute access, including the Linalg generator
and C API.
Assisted-by: Codex
[AMDGPU] Add MaxHWAddressableLocalMemorySize to TargetParser (#219020)
This is to aid in resolving
https://github.com/ROCm/llvm-project/issues/3298 : "Comgr should use
target information from upstream TargetParser rather than maintaining
its own"
[AMDGPU] Move the LDS bank count query into TargetParser
Emit LDSBankCount as a column of the generated AMDGPU GPU table and
expose getLDSBankCount() from TargetParser, so consumers that only have
a GPUKind or subarch can read it without an MCSubtargetInfo.
Change-Id: Id792a6886a53de80326bac14bc9b7d973a38d6cc
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
[AMDGPU] Add FeatureLDSBankCount64 for gfx12.5
gfx1250, gfx1251 and gfx1250-strict have 64 LDS banks rather than 32.
Set the count on FeatureISAVersion12_50_Common so all three, and the
gfx12-5-generic target covering them, inherit it.
Change-Id: Idf9a69ae6e3218dd1685d1c8102bb0477ecbccba
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
[CIR] Drop call-conv-lowering opt-out from OpenACC declare tests
The six OpenACC declare tests opted out of CallConvLowering because the pass
did not handle parameters of an empty or tag class. CallConvLowering handles
them now, so they can run the pass and pin what it produces.
Assisted-by: Cursor / claude-opus-5
[Hexagon] Emit PS_aligna in the prologue with the final stack alignment (#204660)
Hexagon uses PS_aligna to set up the aligned stack base register when a
function has variable-sized stack objects. That pseudo is created during
instruction selection using the maximum stack alignment known at that
point.
Register allocation can later introduce HVX spill slots with stricter
alignment, for example 128-byte alignment in HVX 128-byte mode. If
PS_aligna keeps the older immediate, the aligned base register can be
under-aligned, and aligned HVX spill stores may address stack slots with
insufficient alignment.
In order to address this bug, insert PS_aligna during prologue emission
once its final value is known instead of manually updating it throughout
the backend multiple times.
[mlir][LLVM] Use a disjoint scope domain when inlining noalias
This matches recent changes to the LLVM inliner.
AI disclosure: Claude wrote the code, I wrote the commit message and
have done initial review.
