LLVM/project 8a25f95clang/include/clang/CIR MissingFeatures.h, clang/lib/CIR/CodeGen CIRGenExpr.cpp CIRGenModule.cpp

[CIR] Implement non-odr use of reference type lowering (#185720)

This is used somewhat rarely, but is a pretty simple emission of
pointers, and ends up using infrastructure we already have.
Additionally, this is the first use of `getNaturalTypeAlignment` that
uses the `pointee` argument, so this adds the implementation there,
which includes some alignment work for CXXRecordDecls, so this
implements that as well.
DeltaFile
+35-0clang/test/CIR/CodeGen/non-odr-use-non-ref.cpp
+11-2clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+8-2clang/lib/CIR/CodeGen/CIRGenModule.cpp
+2-1clang/lib/CIR/CodeGen/CIRGenModule.h
+0-1clang/include/clang/CIR/MissingFeatures.h
+56-65 files

LLVM/project 1ea11e4clang/lib/CIR/CodeGen CIRGenExpr.cpp, clang/test/CIR/CodeGenBuiltins builtin-bcopy.cpp

[CIR] Implement 'builtin-addressof' for 'getPointerWithAlignment' (#185684)

The 'getPointerWithAlignment' is really only called when evaluating
arguments for builtins, so the test is a touch weird as it test through
bcopy. However, this shows up in some headers, so it is important that
we support this.

This patch just adds the implementation, which mirrors classic-codegen,
except that we don't generate TBAA.
DeltaFile
+18-0clang/test/CIR/CodeGenBuiltins/builtin-bcopy.cpp
+5-3clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+23-32 files

LLVM/project 6bc0fafclang/lib/CIR/CodeGen CIRGenItaniumCXXABI.cpp CIRGenVTables.cpp, clang/test/CIR/CodeGenCXX vtable-linkage.cpp vtable-virt-thunk-adj.cpp

[CIR] Implement deferred V-Table emission (#185655)

We are currently only emitting Vtables that have an 'immediate' need to
emit. There rest, we are supposed to add to a list and emit at the end
of the translation unit if necessary. This patch implements that
infrastructure.

The test added is from classic-codegen and came in at the same time as
the deferred vtable emission over there, and only works with deferred
vtable emission, and while it does test the deferred emission, tests
quite a bit more than that. AND since it came in with the same
functionality in classic codegen, seemed to make sense to come in here
too.
DeltaFile
+258-0clang/test/CIR/CodeGenCXX/vtable-linkage.cpp
+146-3clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
+75-0clang/test/CIR/CodeGenCXX/vtable-virt-thunk-adj.cpp
+63-0clang/lib/CIR/CodeGen/CIRGenVTables.cpp
+20-0clang/lib/CIR/CodeGen/CIRGenModule.h
+10-3clang/lib/CIR/CodeGen/CIRGenModule.cpp
+572-63 files not shown
+579-109 files

LLVM/project d8f3be7mlir/lib/Transforms/Utils DialectConversion.cpp, mlir/test/Transforms test-legalize-type-conversion.mlir

[mlir][dialect-conversion] Fix OOB crash in convertFuncOpTypes for funcs with extra block args (#185060)

Some function ops (e.g., gpu.func with workgroup memory arguments) have
more entry block arguments than their FunctionType has inputs. The
workgroup memory arguments are not part of the public function signature
but are present as additional block arguments.

`convertFuncOpTypes` previously created a `SignatureConversion` sized
only for `type.getNumInputs()`, then called `applySignatureConversion`
on the entry block. When the block had more arguments (e.g., workgroup
args), the loop in `applySignatureConversion` would call
`getInputMapping(i)` with out-of-bounds indices, causing an assertion
failure in `SmallVector::operator[]`.

Fix this by:
1. Sizing the `SignatureConversion` for all entry block arguments.
2. Adding identity mappings for extra block args beyond the function
type inputs.
3. Using only the converted function-type-input types when updating the

    [5 lines not shown]
DeltaFile
+29-9mlir/lib/Transforms/Utils/DialectConversion.cpp
+19-0mlir/test/Transforms/test-legalize-type-conversion.mlir
+48-92 files

LLVM/project b78ceefmlir/lib/Dialect/SCF/Utils Utils.cpp, mlir/test/Transforms parametric-tiling.mlir

[mlir][scf] Fix crash in extractFixedOuterLoops with iter_args loops (#184106)

The stripmineSink helper splices loop body operations into a new inner
scf.for that has no iter_args. When the target loop carries iter_args,
values yielded by the spliced body are moved inside the inner loop, but
the outer loop's yield terminator still references those values,
creating an SSA invariant violation. In debug builds this triggers the
assertion
  use_empty() && "Cannot destroy a value that still has uses\!"
when the outer RewriterBase tries to erase the now-broken operations.

Fix: in extractFixedOuterLoops, skip the strip-mining transformation if
any of the collected perfectly-nested loops have iter_args.

Add a regression test to parametric-tiling.mlir.

Fixes #129044

Assisted-by: Claude Code
DeltaFile
+19-0mlir/test/Transforms/parametric-tiling.mlir
+9-0mlir/lib/Dialect/SCF/Utils/Utils.cpp
+28-02 files

LLVM/project 7beba38mlir/lib/Interfaces ValueBoundsOpInterface.cpp, mlir/test/Dialect/ControlFlow value-bounds-op-interface-impl.mlir

[MLIR] Fix crash in ValueBoundsConstraintSet for non-entry block args (#185048)

When two vector transfer ops share a non-entry block argument as an
index (e.g., in a loop with unstructured control flow), calling
`ValueBoundsConstraintSet::areEqual` on those values caused a crash.

The first `populateConstraints` call would insert the block argument
into the constraint set. The second call found it already mapped and
called `getPos`, which hit an assert requiring the value to be either an
OpResult or an entry-block argument.

Fix with two changes:
1. In `insert()`, suppress adding non-entry block arguments to the
worklist. `ValueBoundsOpInterface` cannot derive bounds for such values,
so the worklist push was a no-op and triggered the re-entrant `getPos`
call.
2. Remove the overly conservative assert in `getPos`. Looking up a
previously inserted non-entry block argument is valid; the assert was
preventing legitimate use after the value had already been inserted.

    [3 lines not shown]
DeltaFile
+26-0mlir/test/Dialect/ControlFlow/value-bounds-op-interface-impl.mlir
+10-4mlir/lib/Interfaces/ValueBoundsOpInterface.cpp
+36-42 files

LLVM/project 2b6bd31llvm/test/tools/llvm-mca/X86/AlderlakeP resources-x86_64.s, llvm/test/tools/llvm-mca/X86/Atom resources-x86_64.s

[X86] Add mayLoad/mayStore to legacy instructions CMPS/LODS/MOVS/SCAS/STOS (#185689)

When LLVM is used to disassemble instructions, legacy X86 strings
instructions doesn't report memory access with mayLoad and mayStore.

Note that INS and OUTS may also need sush flags, but I'm not totally
sure which one.
DeltaFile
+20-20llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_64.s
+20-20llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
+20-20llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s
+20-20llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s
+20-20llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_64.s
+20-20llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
+120-12014 files not shown
+391-39120 files

LLVM/project 776589allvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/VPlan find-last.ll

[VPlan] Handle FindLast in VPIRFlags::printFlags (#185857)

Noticed this when -vplan-print-after-all crashed on a find-last
reduction. We don't yet return an opcode for it because there's no
in-loop reduction.
DeltaFile
+91-0llvm/test/Transforms/LoopVectorize/VPlan/find-last.ll
+3-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+94-02 files

LLVM/project b157e09libclc/clc/lib/generic/math clc_hypot.inc clc_hypot.cl

libclc: Update hypot implementation

This avoids bithacking on the values and improves value
tracking.
DeltaFile
+30-67libclc/clc/lib/generic/math/clc_hypot.inc
+8-6libclc/clc/lib/generic/math/clc_hypot.cl
+38-732 files

LLVM/project aa90addllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 reduced-value-stored.ll

[SLP]Track vectorized values in reductions for correct handling between vectorization

Need to use WeakTrackingVH handler instead of the Value * to correctly
track modified/replaced vectorized instructions

Fixes https://github.com/llvm/llvm-project/pull/182760#issuecomment-4036706233
DeltaFile
+62-0llvm/test/Transforms/SLPVectorizer/X86/reduced-value-stored.ll
+14-11llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+76-112 files

LLVM/project 3a6aa13llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 combine-add.ll

[X86] Optimized ADD + ADC to ADC (#173543)

This patch folds an `adc` followed by an `add` into a single `adc` instruction when adding constants.

Fixes #173408
DeltaFile
+79-0llvm/test/CodeGen/X86/combine-add.ll
+22-0llvm/lib/Target/X86/X86ISelLowering.cpp
+101-02 files

LLVM/project 8778333libclc/clc/lib/generic/math clc_hypot.inc clc_hypot.cl

libclc: Update hypot implementation

This avoids bithacking on the values and improves value
tracking.
DeltaFile
+32-67libclc/clc/lib/generic/math/clc_hypot.inc
+8-6libclc/clc/lib/generic/math/clc_hypot.cl
+40-732 files

LLVM/project 95dddf6libclc/clc/include/clc/math clc_frexp_exp.h, libclc/clc/include/clc/shared unary_decl_with_int_return.inc

libclc: Add frexp_exp utility function

Many functions want to extract the exponent and
currently rely on bithacking to do it. These can be
better handled with frexp. AMDGPU has a dedicated
instruction for each of the frexp return values. Other
targets could override this to do the bithacking (though
they would be better off teaching codegen to optimize
frexp with a discarded output).
DeltaFile
+22-0libclc/clc/include/clc/math/clc_frexp_exp.h
+13-0libclc/clc/lib/generic/math/clc_frexp_exp.cl
+13-0libclc/clc/lib/generic/math/clc_frexp_exp.inc
+9-0libclc/clc/include/clc/shared/unary_decl_with_int_return.inc
+1-0libclc/clc/lib/generic/CMakeLists.txt
+58-05 files

LLVM/project 33584b6llvm/lib/CodeGen StackSlotColoring.cpp, llvm/test/CodeGen/AMDGPU si-lower-sgpr-spills-vgpr-lanes-usage.mir

[StackSlotColoring] Check for zero stack slot size in RemoveDeadStores (#182673)

The default implementations of the methods isLoadFromStackSlot() and
isStoreToStackSlot() used in StackSlotColoring::RemoveDeadStores() set
the number of bytes loaded from the stack (MemBytes) to zero to indicate
that the value is unknown. This means that
StackSlotColoring::RemoveDeadStores() must abort if the size is zero
otherwise the stack slot size check doesn't mean anything.

As backends that use this are required to override the default
implementations this should not impose any degradation of the code.

As the registers also must match in
StackSlotColoring::RemoveDeadStores() for the store to be optimized away
there is small risk of this being a real bug.

---------

Co-authored-by: Karl-Johan Karlsson <karl-johan.karlsson at ericsson.com>
DeltaFile
+3-0llvm/lib/CodeGen/StackSlotColoring.cpp
+3-0llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
+6-02 files

LLVM/project d8a7467clang/lib/CodeGen/Targets NVPTX.cpp, clang/test/CodeGen scoped-atomic-ops.c

[NVPTX] Support __scoped_atomic_* operations in NVPTX (#184737)

Summary:
All the infrastructure for this is here, it's just no one's turned it
on.
DeltaFile
+1,419-130clang/test/CodeGen/scoped-atomic-ops.c
+33-0clang/lib/CodeGen/Targets/NVPTX.cpp
+1,452-1302 files

LLVM/project 71608f4libcxx/utils/ci/images libcxx_next_runners.txt

[libc++] Update the libcxx-next-runners image (#185871)
DeltaFile
+1-1libcxx/utils/ci/images/libcxx_next_runners.txt
+1-11 files

LLVM/project 5368b81mlir/include/mlir/Dialect/Arith/IR ArithOps.td, mlir/lib/Dialect/Arith/IR ArithCanonicalization.td ArithOps.cpp

[MLIR][Arith] Add canonicalization rules for int-to-float of integer extension (#185386)

Three patterns are valid but were missing:

1. `sitofp(extsi(x)) → sitofp(x)`: extsi preserves the sign and value,
so it represents the same signed integer as x.

2. `uitofp(extui(x)) → uitofp(x)`: same reasoning as above, but for
unsigned extension.

3. `sitofp(extui(x)) → uitofp(x)` extui zero-extends, so the extended
value is always non-negative. For non-negative integers, sitofp and
uitofp produce the same result, meaning we could replace the left
expression by `uitofp(extui(x))`. At this point rule 2. above can be
used to simplify further to `uitofp(x)`.

All three rewrites have been verified with Alive2.
DeltaFile
+36-1mlir/test/Dialect/Arith/canonicalize.mlir
+23-0mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
+7-4mlir/test/Dialect/Arith/emulate-wide-int-canonicalization.mlir
+10-0mlir/lib/Dialect/Arith/IR/ArithOps.cpp
+2-0mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+78-55 files

LLVM/project acd52a2flang/include/flang/Utils OpenMP.h, flang/lib/Lower/OpenMP Utils.cpp Utils.h

[flang][OpenMP][DoConcurrent] Emit declare mapper for records (#179936)

Extends `do concurrent` device support by emitting compiler-generated
declare mapper ops for live-ins whose types are record types and have
allocatable members.
DeltaFile
+9-107flang/lib/Lower/OpenMP/Utils.cpp
+104-0flang/lib/Utils/OpenMP.cpp
+33-1flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
+28-0flang/test/Transforms/DoConcurrent/implicit_mapper.f90
+8-4flang/lib/Lower/OpenMP/Utils.h
+9-0flang/include/flang/Utils/OpenMP.h
+191-1122 files not shown
+202-1158 files

LLVM/project 3b8cd6cmlir/lib/Dialect/Affine/Transforms SuperVectorize.cpp, mlir/test/Dialect/Affine/SuperVectorize vectorize_1d.mlir

[mlir][affine] Fix crash in affine-super-vectorize for index constants inside loops (#184614)

When an arith.constant of index type is defined inside the loop body
being vectorized, vectorizeConstant creates a vector<Nxindex> constant
and registers it as the vector replacement. However,
getScalarValueReplacementsFor (used by vectorizeAffineStore to compute
indices for vector.transfer_write) looks only in the scalar replacement
map. With no scalar replacement registered for the index constant, it
falls back to the original scalar value, which is erased when the scalar
loop is cleaned up. This results in a "operation destroyed but still has
uses" crash.

Fix: when vectorizeConstant processes an index-typed constant, also
create a new scalar constant in the vector loop body and register it as
the scalar replacement. This ensures that memory operation index
computation can find a live value in the vectorized IR.

Fixes #122213

Assisted-by: Claude Code
DeltaFile
+22-0mlir/test/Dialect/Affine/SuperVectorize/vectorize_1d.mlir
+13-0mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
+35-02 files

LLVM/project 4fd826dllvm/include/llvm/IR Instructions.h Instruction.def, llvm/lib/IR Instructions.cpp

[IR] Split Br into UncondBr and CondBr (#184027)

BranchInst currently represents both unconditional and conditional
branches. However, these are quite different operations that are often
handled separately. Therefore, split them into separate opcodes and
classes to allow distinguishing these operations in the type system.
Additionally, this also slightly improves compile-time performance.
DeltaFile
+207-51llvm/include/llvm/IR/Instructions.h
+112-111llvm/test/tools/llvm-ir2vec/entities.ll
+89-89llvm/test/Transforms/IRNormalizer/regression-infinite-loop.ll
+81-80llvm/include/llvm/IR/Instruction.def
+38-38llvm/test/tools/llvm-ir2vec/triplets.ll
+36-31llvm/lib/IR/Instructions.cpp
+563-40065 files not shown
+838-65571 files

LLVM/project c7aaaealibcxx/test/benchmarks adjacent_view_begin.bench.cpp filesystem.bench.cpp, libcxx/test/benchmarks/algorithms swap_ranges.bench.cpp

[libc++] Rename a few benchmarks to allow identifying what's being benchmarked from the name (#185747)
DeltaFile
+76-76libcxx/test/benchmarks/libcxxabi/dynamic_cast.bench.cpp
+23-23libcxx/test/benchmarks/adjacent_view_begin.bench.cpp
+21-14libcxx/test/benchmarks/filesystem.bench.cpp
+13-6libcxx/test/benchmarks/algorithms/swap_ranges.bench.cpp
+8-8libcxx/test/benchmarks/format/formatter_int.bench.cpp
+141-1275 files

LLVM/project d8f71b1llvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter masked-gather-scatter.ll vector-of-pointers-ptrtoint.ll

[SPIR-V] Add support for SPV_INTEL_masked_gather_scatter extension (#185418)

Fixes the first bullet in #184638 

Corresponding patch to add support for vector operands in
OpConvertPtrToU/OpConvertUToPtr operations in spirv-val:
https://github.com/KhronosGroup/SPIRV-Tools/pull/6575

SPIR-V extension reference used:
https://github.com/KhronosGroup/SPIRV-Registry/blob/278044a51fee280bfc91322cdb55b51357db5cb8/extensions/INTEL/SPV_INTEL_masked_gather_scatter.asciidoc
DeltaFile
+103-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/masked-gather-scatter.ll
+94-0llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+80-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+24-10llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+33-0llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/vector-of-pointers-ptrtoint.ll
+19-2llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+353-1210 files not shown
+428-1216 files

LLVM/project 1d5ba1allvm/utils/gn/secondary/clang/lib/Analysis BUILD.gn

[gn] port 6bc779506107d
DeltaFile
+2-0llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
+2-01 files

LLVM/project f6cafcbllvm/utils/gn/secondary/clang-tools-extra/clang-doc BUILD.gn, llvm/utils/gn/secondary/clang/lib/Analysis/Scalable BUILD.gn

[gn] port 65cb738ff41995 more (clang UnifiedSymbolResolution)
DeltaFile
+11-0llvm/utils/gn/secondary/clang/lib/UnifiedSymbolResolution/BUILD.gn
+1-1llvm/utils/gn/secondary/clang/lib/Analysis/Scalable/BUILD.gn
+1-1llvm/utils/gn/secondary/clang/lib/CrossTU/BUILD.gn
+1-1llvm/utils/gn/secondary/clang/lib/Tooling/Refactoring/BUILD.gn
+1-1llvm/utils/gn/secondary/clang/lib/ExtractAPI/BUILD.gn
+1-1llvm/utils/gn/secondary/clang-tools-extra/clang-doc/BUILD.gn
+16-55 files not shown
+21-511 files

LLVM/project ce0488fllvm/include/llvm/Analysis Delinearization.h, llvm/lib/Analysis Delinearization.cpp

[Delinearization] Fix comment in Delinearization.cpp/h (#182596)
DeltaFile
+1-3llvm/include/llvm/Analysis/Delinearization.h
+1-3llvm/lib/Analysis/Delinearization.cpp
+2-62 files

LLVM/project dc93e6elibclc/clc/include/clc/math gentype.inc, libclc/clc/lib/generic/conversion clc_convert_float.inc

libclc: Add gentype infinity macro (#185864)
DeltaFile
+4-5libclc/clc/lib/generic/conversion/clc_convert_float.inc
+1-0libclc/clc/include/clc/math/gentype.inc
+5-52 files

LLVM/project cb3fbe9llvm/lib/Target/AMDGPU AMDGPU.td GCNSubtarget.cpp, llvm/test/CodeGen/AMDGPU function-alignment.ll s_code_end.ll

[AMDGPU] Set preferred function alignment based on icache geometry (#183064)

Non-entry functions were unconditionally aligned to 4 bytes with no
architecture-specific preferred alignment, and setAlignment() was used
instead of ensureAlignment(), overwriting any explicit IR attributes.

Add instruction cache line size and fetch alignment data to GCNSubtarget
for each generation (GFX9: 64B/32B, GFX10: 64B/4B, GFX11+: 128B/4B). Use
this to call setPrefFunctionAlignment() in SITargetLowering, aligning
non-entry functions to the cache line size by default. Change
setAlignment to ensureAlignment in AMDGPUAsmPrinter so explicit IR align
attributes are respected.

Empirical thread trace analysis on gfx942, gfx1030, gfx1100, and gfx1200
showed that only GFX9 exhibits measurable fetch stalls when functions
cross the 32-byte fetch window boundary. GFX10+ showed no alignment
sensitivity. A hidden option -amdgpu-align-functions-for-fetch-only is
provided to use the fetch granularity instead of cache line size.

Assisted-by: Claude Opus
DeltaFile
+116-0llvm/test/CodeGen/AMDGPU/function-alignment.ll
+22-7llvm/lib/Target/AMDGPU/AMDGPU.td
+9-0llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+4-4llvm/test/CodeGen/AMDGPU/s_code_end.ll
+6-0llvm/lib/Target/AMDGPU/GCNSubtarget.h
+3-3llvm/test/CodeGen/AMDGPU/hsa-func.ll
+160-143 files not shown
+166-179 files

LLVM/project e08fd82llvm/lib/Target/X86 X86ISelLowering.cpp X86SelectionDAGInfo.cpp

[X86] LowerINTRINSIC_W_CHAIN - ensure the X86ISD::CMPCCXADD X86CondCode is a i8 target constant (#185856)

Fixes verification failure in X86SelectionDAGInfo::verifyTargetNode (#185649)
DeltaFile
+5-4llvm/lib/Target/X86/X86ISelLowering.cpp
+0-2llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+5-62 files

LLVM/project 3669d2eclang/docs ReleaseNotes.rst, clang/lib/Sema SemaTemplateInstantiate.cpp

[Clang] Fix ICE in constraint normalization when substituting concept template parameters (#184406)

23341c3d139b889e8c46867f8d704ab3c22b51f8 introduced
`SubstituteConceptsInConstraintExpression` to substitute non-dependent
concept template arguments into a concept's constraint expression during
normalization, as part of the P2841R7 implementation
([temp.constr.normal]/1.4).

The `ConstraintExprTransformer` added in that commit overrides
`TransformTemplateArgument` to only transform concept-related arguments
and preserve all others. However, `TransformUnresolvedLookupExpr` called
`Sema::SubstExpr`, which creates a separate `TemplateInstantiator` that
performs full substitution bypassing the selective override entirely.

This caused all template parameters in the constraint expression to be
substituted using the concept's MLTAL. For example, given:

```cpp
template <class A, template <typename...> concept C>

    [22 lines not shown]
DeltaFile
+34-5clang/lib/Sema/SemaTemplateInstantiate.cpp
+36-0clang/test/SemaCXX/cxx2c-template-template-param.cpp
+1-0clang/docs/ReleaseNotes.rst
+71-53 files

LLVM/project 1930089libcxx/utils/ci/docker docker-compose.yml

[libc++] Update the docker base image version (#185863)
DeltaFile
+2-2libcxx/utils/ci/docker/docker-compose.yml
+2-21 files