LLVM/project 0e2216d — llvm/lib/Target/AArch64 AArch64TargetTransformInfo.h, llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64 expand-masked-load.ll expand-masked-store.ll

[AArch64] Mark masked load/store data types that get legalized to scalars illegal (#228122)

Masked load/stores cannot handle data types that get scalarized during
type legalization. This PR marks them illegal in AArch64 TTI so they get
expanded before reaching SDAG.

Fixes e.g. the crash:

```llvm
; llc -mtriple=aarch64 -mattr=+sve crash.ll

define <1 x half> @masked_load_v1f16(ptr %p, <1 x i1> %mask) vscale_range(2,2) {
  %load = call <1 x half> @llvm.masked.load.v1f16.p0(ptr %p, <1 x i1> %mask, <1 x half> poison)
  ret <1 x half> %load
}
```
DeltaFile
+114-0llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/expand-masked-store.ll
+87-0llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/expand-masked-load.ll
+6-0llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+207-03 files

LLVM/project 0f410d4 — llvm/lib/Target/AMDGPU AMDGPUEventTracking.cpp AMDGPUEventTracking.h

Claude Opus 5.5-powered doc cleanups (with human touch)
DeltaFile
+86-70llvm/lib/Target/AMDGPU/AMDGPUEventTracking.h
+34-36llvm/lib/Target/AMDGPU/AMDGPUEventTracking.cpp
+120-1062 files

LLVM/project bbd682b — llvm/include/llvm/MC MCAsmInfo.h, llvm/lib/CodeGen/AsmPrinter WinException.cpp

MC: Make usesWindowsCFI a pure object-format predicate

Whether unwind information is encoded with SEH opcodes (.seh_*, .pdata
and .xdata) is a property of the object format. Whether a function uses
that encoding depends on the exception model, but usesWindowsCFI()
conflated the two. Make it report only the format, and add
MachineFunction::usesWindowsUnwindInfo() for the combined question and
needsWinCFI() for the common case that also requires an unwind table
entry.

This moves the exception model check to the point of use, in preparation
for removing ExceptionModel from TargetOptions. The assembler now accepts
.seh_* directives whenever the object format supports them (i.e., MC
only tools will no longer have a notion of ExceptionModel).

Co-authored-by: Claude Opus <noreply at anthropic.com>
DeltaFile
+10-19llvm/lib/Target/X86/X86FrameLowering.cpp
+5-11llvm/lib/Target/ARM/ARMFrameLowering.cpp
+6-10llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+4-10llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+7-7llvm/lib/CodeGen/AsmPrinter/WinException.cpp
+8-4llvm/include/llvm/MC/MCAsmInfo.h
+40-6118 files not shown
+79-9824 files

LLVM/project 406ee2c — llvm/lib/Target/AMDGPU AMDGPUEventTracking.h

Comments fixed by me
DeltaFile
+34-41llvm/lib/Target/AMDGPU/AMDGPUEventTracking.h
+34-411 files

LLVM/project 452c9b5 — clang/test/CodeGen/AArch64/sve maxv.c, clang/test/CodeGen/AArch64/sve-intrinsics acle_sve_maxv.c

[clang][CIR] Add tests for SVE MAXV intrinsics (#230080)

adds CIR tests for svmaxv (plain SVE) intrinsics.

Moves and adapts sve-intrinsics/acle_sve_maxv.c to sve/maxv.c.

Part of #223963
DeltaFile
+0-207clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxv.c
+207-0clang/test/CodeGen/AArch64/sve/maxv.c
+207-2072 files

LLVM/project b1767ea — clang/test/CodeGen/AArch64/sve eorv.c, clang/test/CodeGen/AArch64/sve-intrinsics acle_sve_eorv.c

[clang][CIR] Add tests for SVE EORV intrinsics (#230083)

adds CIR tests for sveorv (plain SVE) intrinsics.

Moves and adapts sve-intrinsics/acle_sve_eorv.c to sve/eorv.c.

Part of #223963
DeltaFile
+159-0clang/test/CodeGen/AArch64/sve/eorv.c
+0-155clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eorv.c
+159-1552 files

LLVM/project ce36ebd — llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp

update
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+2-21 files

LLVM/project b91277a — llvm/include/llvm/TableGen Record.h, llvm/lib/TableGen Record.cpp

TableGen: Cache resolved class instantiations

The same class instantiation is often referenced many times in one
record, and each reference was resolved again from scratch along with
everything nested in its arguments. Cache the results in MapResolver and
RecordResolver. The cache is cleared when the mappings change, and is
bypassed while a mapped variable is being resolved.

Nested instantiations are resolved through a TrackUnresolvedResolver,
which does not change the result. These share the cache of the
underlying resolver, which also records whether any references were left
unresolved so the trackers can be updated on a hit.

Gigainstructions executed by llvm-tblgen --null-backend

             before   after
  AMDGPU.td   71.75   18.22  -74.6%
  X86.td       6.10    6.15   +0.8%
  AArch64.td   3.28    3.32   +1.3%

    [3 lines not shown]
DeltaFile
+142-3llvm/include/llvm/TableGen/Record.h
+14-4llvm/lib/TableGen/Record.cpp
+156-72 files

LLVM/project 3ab5ef2 — llvm/include/llvm/TableGen Record.h, llvm/lib/TableGen Record.cpp

TableGen: Skip resolving values that cannot change

Lists, dags, bits and arguments made only of leaf values always resolve
to themselves, but resolving them still walked every element. Record
this when they are created and return early.

Gigainstructions executed by llvm-tblgen --null-backend

             before   after
  AMDGPU.td   79.12   71.73   -9.3%
  X86.td       6.25    6.12   -2.1%
  AArch64.td   3.40    3.28   -3.7%
  RISCV.td     8.34    8.19   -1.8%

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+18-2llvm/include/llvm/TableGen/Record.h
+19-0llvm/lib/TableGen/Record.cpp
+37-22 files

LLVM/project 6d66a46 — llvm/lib/TableGen Record.cpp

TableGen: Use DenseMap for the IntInit pool

Gigainstructions executed by llvm-tblgen --null-backend

             before   after
  AMDGPU.td   79.34   79.13   -0.3%
  X86.td       6.30    6.25   -0.7%
  AArch64.td   3.43    3.41   -0.6%
  RISCV.td     8.40    8.34   -0.7%

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+1-2llvm/lib/TableGen/Record.cpp
+1-21 files

LLVM/project 8590be0 — bolt/test/RISCV constant-island-branch-rescan.s validate-multiple-branch-targets.s

[BOLT][RISCV] Add RISCV tests for external branch target validation (#223991)

Add RISC-V regression tests to complement #221927, covering two external
branch target validation cases.
DeltaFile
+38-0bolt/test/RISCV/validate-multiple-branch-targets.s
+36-0bolt/test/RISCV/constant-island-branch-rescan.s
+74-02 files

LLVM/project 985239e — mlir/include/mlir/Dialect/OpenACC OpenACC.h, mlir/lib/Dialect/OpenACC/Transforms ACCComputeLowering.cpp ACCEmitRemarksLoop.cpp

[mlir][acc] Report independent loops not parallelized due to unstructured control flow (#230066)

An independent acc loop whose body has unstructured control flow (for
example a backward GOTO) cannot be represented as a structured loop, so
it is executed sequentially. This happened silently: no remark was
emitted for the loop, and the user only saw a serial kernel without a
reason.

Emit a remark for such loops stating that they are not parallelized
because their control flow could not be represented as a structured
loop. This lets users identify loops that are asserted parallel but run
sequentially.

Co-Authored-By: Claude
DeltaFile
+100-0mlir/test/Dialect/OpenACC/acc-compute-lowering-unstructured.mlir
+22-0mlir/test/Dialect/OpenACC/acc-emit-remarks-loop.mlir
+15-3mlir/lib/Dialect/OpenACC/Transforms/ACCEmitRemarksLoop.cpp
+13-0mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
+7-0mlir/include/mlir/Dialect/OpenACC/OpenACC.h
+157-35 files

LLVM/project f90c789 — clang/lib/Sema SemaDeclAttr.cpp

[clang][CUDA] Perform lvalue-to-rvalue conversion on `__cluster_dims__` attribute arguments (#227998)

A `ConstantExpr` with an lvalue subexpression should always have an
lvalue APValue result.
DeltaFile
+5-1clang/lib/Sema/SemaDeclAttr.cpp
+5-11 files

LLVM/project cd1b8e8 — llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp, llvm/test/CodeGen/AMDGPU amdgpu-sw-lower-lds-flat-arg-kernel-id.ll

[AMDGPU][SwLowerLDS] Lower non-kernels with LDS instructions and assign kernel IDs to their callers
DeltaFile
+122-84llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+152-0llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-arg-kernel-id.ll
+274-842 files

LLVM/project 6550729 — llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp, llvm/test/CodeGen/AMDGPU amdgpu-sw-lower-lds-flat-to-lds-cast.ll amdgpu-sw-lower-lds-flat-to-lds-cast-roundtrip.ll

use ptrtoaddr
DeltaFile
+127-0llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-to-lds-cast-vector.ll
+5-5llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+2-2llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-to-lds-cast.ll
+2-2llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-to-lds-cast-roundtrip.ll
+136-94 files

LLVM/project 7091437 — llvm/lib/Target/AMDGPU AMDGPUSwLowerLDS.cpp, llvm/test/CodeGen/AMDGPU amdgpu-sw-lower-lds-flat-to-lds-cast-roundtrip.ll amdgpu-sw-lower-lds-flat-to-lds-cast.ll

[AMDGPU][SwLowerLDS] Rebase flat to LDS addrspacecasts to buffer offsets
DeltaFile
+117-0llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-to-lds-cast.ll
+87-0llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-flat-to-lds-cast-roundtrip.ll
+33-5llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+237-53 files

LLVM/project c53c089 — libc CMakeLists.txt, libc/docs/dev code_style.md

[libc] Fail configure if requested linting cannot run (#231001)

If linting was requested but could not run, CMake previously disabled it
with a warning and generated an empty libc-lint target.

Change these conditions to FATAL_ERROR so misconfigurations fail early:
* Compiler is not Clang
* clang-tidy is not found
* Auto-discovered clang-tidy has a mismatched major version

If LLVM_LIBC_CLANG_TIDY is set explicitly, treat version mismatches as a
warning instead of an error.

Document the configure requirements in code_style.md.

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+71-35libc/CMakeLists.txt
+29-0libc/docs/dev/code_style.md
+100-352 files

LLVM/project 057f9bf — llvm/include/llvm/Analysis VecFuncs.def, llvm/include/llvm/IR RuntimeLibcalls.td

[AMDLIBM] Map new vector calls in VecFuncs (#224614)

Emit vector variant amd_vr* calls for atan2/tanh/cosh/exp10/acos calls

aocl-libm-ose repo :
[amdlibm_vec.h](https://github.com/amd/aocl-libm-ose/blob/master/include/external/amdlibm_vec.h)
DeltaFile
+343-6llvm/test/Transforms/Util/add-TLI-mappings.ll
+119-0llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls-finite.ll
+80-22llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
+34-0llvm/include/llvm/Analysis/VecFuncs.def
+17-0llvm/include/llvm/IR/RuntimeLibcalls.td
+593-285 files

LLVM/project 898c619 — mlir/include/mlir/Dialect/LLVMIR LLVMOpBase.td LLVMOps.td, mlir/lib/Dialect/LLVMIR/IR LLVMDialect.cpp

[mlir][LLVM] Add ignore_denormal_mode UnitAttr to LLVM::AtomicRMWOp
DeltaFile
+22-5mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+8-7mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+8-0mlir/test/Dialect/LLVMIR/invalid.mlir
+7-0mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
+0-6mlir/lib/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.cpp
+4-0mlir/test/Target/LLVMIR/Import/instructions.ll
+49-184 files not shown
+56-2210 files

LLVM/project e725ea1 — clang/lib/CodeGen TargetInfo.cpp TargetInfo.h, clang/lib/CodeGen/TargetBuiltins NVPTX.cpp

[clang][NVPTX] Emit !atomic.ignore.denormal.mode for CUDA atomics (#217587)

CUDA's atomicAdd() family is defined in terms of PTX atom.add, whose
denormal behavior is fixed by the hardware. Without any annotation the
backend has to assume the function's denormal mode must be honored and
expands these into CAS loops whenever the two disagree. Mark them with
!atomic.ignore.denormal.mode so the native instruction is used.

That covers the __nvvm_atom_*_add_gen_f builtins that atomicAdd(),
atomicAdd_block() and atomicAdd_system() are written in terms of, plus
C11/C++11 atomics under -fatomic-ignore-denormal-mode and the
[[clang::atomic(ignore_denormal_mode)]] attribute, which requires
teaching the NVPTX target about AtomicOptions.

The condition for when the metadata is meaningful is now shared with the
AMDGPU and SPIR-V targets in addAtomicIgnoreDenormalModeMetadata(). It
takes an AllowHalf flag because whether f16 denormals are observable is
target specific: PTX exposes no FTZ control for f16 operations, so
atom.add.f16 never flushes and the opt-in is meaningful there, whereas

    [4 lines not shown]
DeltaFile
+321-0clang/test/CodeGenCUDA/atomic-ignore-denormal-mode-nvptx.cu
+19-4clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
+18-0clang/lib/CodeGen/TargetInfo.h
+15-0clang/lib/CodeGen/TargetInfo.cpp
+12-0clang/lib/CodeGen/Targets/NVPTX.cpp
+2-4clang/lib/CodeGen/Targets/SPIR.cpp
+387-85 files not shown
+402-1711 files

LLVM/project b822a27 — compiler-rt/test/msan release_origin_999.c release_origin_998.c

convert to cherry-pick PR and simplify message

Created using spr 1.3.7
DeltaFile
+0-1compiler-rt/test/msan/release_origin_999.c
+0-1compiler-rt/test/msan/release_origin_998.c
+0-1compiler-rt/test/msan/release_origin_997.c
+0-1compiler-rt/test/msan/release_origin_996.c
+0-1compiler-rt/test/msan/release_origin_995.c
+0-1compiler-rt/test/msan/release_origin_994.c
+0-6994 files not shown
+0-1,0001,000 files

LLVM/project d1e15b6 — llvm/lib/CodeGen BranchFolding.cpp, llvm/test/CodeGen/X86 branchfolding-debug-invariant.mir

[BranchFolding] Ignore debug instructions in singleton cond branch check (#228715)

DBG_VALUE was counted when checking for a single-branch block, so the
duplicate branch was kept only under -g.

Fixes #228713

Assisted-by: Claude Opus 5.5
DeltaFile
+68-0llvm/test/CodeGen/X86/branchfolding-debug-invariant.mir
+2-1llvm/lib/CodeGen/BranchFolding.cpp
+70-12 files

LLVM/project 0edf624 — mlir/lib/Transforms RemoveDeadValues.cpp, mlir/test/Transforms remove-dead-values.mlir

[mlir][RemoveDeadValues] Replace dead function argument uses with poison (#208881)

Dropping all uses of a dead function argument can leave null operands in
surviving side-effecting operations in unreachable code.
Subsequent canonicalization may then crash while folding the invalid
operation.

This PR replaces the remaining uses with `ub.poison` before erasing the
argument and add a regression test.

Fixes #206920, fixes #203226
DeltaFile
+49-0mlir/test/Transforms/remove-dead-values.mlir
+14-3mlir/lib/Transforms/RemoveDeadValues.cpp
+63-32 files

LLVM/project 3bfed00 — mlir/lib/IR AffineExpr.cpp, mlir/test/Dialect/Affine canonicalize.mlir

[MLIR] Guard against overflow when simplifying affine expressions. (#228010)

Fixes https://github.com/llvm/llvm-project/issues/224577.

Current canonicalizer may lead to signed integer overflow while
simplifying affine expressions. This change adds overflow checks and
returns `failure()` when an overflow is detected.
DeltaFile
+36-0mlir/test/Dialect/Affine/canonicalize.mlir
+10-3mlir/lib/IR/AffineExpr.cpp
+46-32 files

LLVM/project 0f8a76d — compiler-rt/test/msan release_origin.c

pin to single CPU instead of chunking memset

Created using spr 1.3.7
DeltaFile
+14-2compiler-rt/test/msan/release_origin.c
+14-21 files

LLVM/project 9b9e3f0 — llvm/test/tools/llvm-ar error-opening-permission.test

[test][llvm-ar] Restore file permissions in error-opening-permission.test (#230361)

error-opening-permission.test sets chmod 100 on %t/permission.b to test
EACCES handling, leaving an unreadable file in the build directory after
the test finishes. This causes permission errors for tools like rsync
when copying the build directory.

Restore permissions with chmod 700 at the end of the test, matching
llvm/test/tools/llvm-ranlib/error-opening-permission.test.

Assisted-by: Gemini
DeltaFile
+2-1llvm/test/tools/llvm-ar/error-opening-permission.test
+2-11 files

LLVM/project 255b974 — compiler-rt/test/msan release_origin_999.c release_origin_998.c

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+1-0compiler-rt/test/msan/release_origin_999.c
+1-0compiler-rt/test/msan/release_origin_998.c
+1-0compiler-rt/test/msan/release_origin_997.c
+1-0compiler-rt/test/msan/release_origin_996.c
+1-0compiler-rt/test/msan/release_origin_995.c
+1-0compiler-rt/test/msan/release_origin_899.c
+6-0994 files not shown
+1,000-01,000 files

LLVM/project 807027f — compiler-rt/test/msan release_origin_901.c release_origin_9.c

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+2-1compiler-rt/test/msan/release_origin.c
+1-0compiler-rt/test/msan/release_origin_901.c
+1-0compiler-rt/test/msan/release_origin_9.c
+1-0compiler-rt/test/msan/release_origin_90.c
+1-0compiler-rt/test/msan/release_origin_900.c
+1-0compiler-rt/test/msan/release_origin_899.c
+7-1995 files not shown
+1,002-11,001 files

LLVM/project ca18429 — llvm/test/tools/llvm-ar error-opening-permission.test

Refactor permission test for llvm-ar

Update permission test to handle command chaining
DeltaFile
+2-2llvm/test/tools/llvm-ar/error-opening-permission.test
+2-21 files

LLVM/project 6115c6d — clang/test/CodeGen/AArch64/sve orv.c, clang/test/CodeGen/AArch64/sve-intrinsics acle_sve_orv.c

[clang][CIR] Add tests for SVE ORV intrinsics (#230082)

adds CIR tests for svorv (plain SVE) intrinsics.

Moves and adapts sve-intrinsics/acle_sve_orv.c to sve/orv.c.

Part of #223963
DeltaFile
+159-0clang/test/CodeGen/AArch64/sve/orv.c
+0-155clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orv.c
+159-1552 files