[SystemZ][z/OS] Correctly align the constant pool and the PPA1
Both should be half-word aligned. However, testing revealed that
both can end up on odd addresses, which leads to relocation errors.
Fix is to change the alignment.
[lldb] Remove ConstString from CommandObjectType interfaces (#218811)
CommandObjectType was creating ConstStrings type names, function names,
etc. before they needed to be. I'd like to remove ConstString from the
DataFormatter code entirely, so pushing the creation down as far as
possible first is a good first step.
The only remaining use (outside of function arguments) is
ScriptAddOptions. I need to understand it more before I can really
remove it.
[llc] add target-features optimization remark
In clang we have --print-enabled-extensions which will print the
AArch64 extensions enabled for a given TU. However, sometimes it is
useful to be able to print out the actual subtarget features for each
function, for debugging/testing purposes. Add an optimization remark
for that.
MachineLICM: Fix preheader insertion point with SUCC_ARGS
Hoist loop-invariant instructions to getBlockEndInsertPt() instead of
getFirstTerminator(), so they land before the SUCC_ARGS cluster rather
than inside it.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
CodeGen: Fix MachineCSE PRE insert point with SUCC_ARGS
Hoist to getBlockEndInsertPt() instead of getFirstTerminator(), so a hoisted
instruction lands before the SUCC_ARGS cluster rather than inside it.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
CodeGen: Add SUCC_ARGS pseudo-instruction
The sender half of a block-argument representation for Machine IR: a
"reverse PHI" that forwards values from a predecessor's bottom to a
successor block's arguments along one CFG edge. Operand 0 is the successor
block; the rest are the forwarded value registers, mapped positionally.
Like PHI, SUCC_ARGS is edge-specific: it must stay in its block, so it is
excluded from CSE and hoisting, and it defines no register but is not dead.
SUCC_ARGS are clustered contiguously immediately before the terminators,
mirroring how PHIs are clustered at the top of a block; the verifier
enforces this and the succ_args() range and getBlockEndInsertPt() let
consumers work with the cluster. Inert; no producer emits it yet.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
CodeGen: Represent block arguments on MachineBasicBlock
The receiver half of the block-argument representation: a block declares a list
of virtual registers that receive values forwarded by each predecessor's
SUCC_ARGS. Unlike a PHI, a block argument is defined by the block itself, not by
an instruction.
MachineBasicBlock holds the argument list, printed and parsed as an "arguments:"
block header line. MachineRegisterInfo maps each argument to its defining block,
so getDefBlock works for these registers. The verifier treats an argument as
defined at block entry and requires each predecessor to supply one matching
SUCC_ARGS.
This is only building infrastructure, and is not yet used.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
PowerPC: Fix VSX swap removal crash on an undef register (#216714)
formWebs walks each vector-register use and unions its equivalence class
with that of its defining instruction, which it requires to be present
in the swap map. A use of an undef register has no defining instruction, so
the web formation crashed. Treat it like a physical-register mention so the
web is conservatively rejected.
Found by AI while working on something else.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
[libc] Generate a stub for libdl.a (#222098)
Avoid link errors when build rules explicitly add `-ldl` to the linker
invocation -
create an empty `libdl.a` static archive on Linux. It's necessary, for
example,
to build Clang (https://github.com/llvm/llvm-project/issues/97191)
Follow the approach from f88e9de37a52abf9b269a7232bf4d4028bc4ace8
which added a similar stub for `libpthread.a`. Like pthread, dynamic
loader
functions (although they are mostly unimplemented in LLVM-libc as of
today)
are residing in the main `libc.a` archive instead.
[VPlan] Remove VPWidenInductionRecipe::getStartValue (NFC). (#222015)
It now shadows VPHeaderPHIRecipe::getStartValue, which returns the same
VPValue and, as the base class accessor, also has a non-const overload.
Narrowing the return type to VPIRValue * was its only purpose.
[lldb] Fix infinite recursion in ArchSpec's core matching (#221899)
`target create` never returns for a little-endian 32-bit MIPS ELF file,
on any host whose platform advertises `armv7m`/`armv7em` compatibility.
On Darwin that is every platform, since
`PlatformDarwin::GetCompatibleArchs()`
lists both for every arm64/arm64e host and falls through to that same
list
for any other host core. It is found by `lldb-target-fuzzer`.
Reproduce with a 52-byte ELF32 header (`ELFCLASS32`, `ELFDATA2LSB`,
`e_machine = EM_MIPS`, `e_flags = EF_MIPS_ARCH_32`, everything else
zero),
saved as `mips32el.elf`:
```
(lldb) target create mips32el.elf
```
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[VPlan] Don't cost scalar IV steps if the vector body runs at most once. (#221974)
If the vector loop executes exactly once, each scalar IV step folds to a
constant, and there's nothing to cost.
Similarly to BranchOnCount and VPRegionBlock::cost, treat
VPScalarIVSteps as free in that case.
This fixes a slight inaccuracy introduced when moving to computing
VPScalarIVSteps costs in VPlan directly.
PR: https://github.com/llvm/llvm-project/pull/221974
[SystemZ][z/OS] Emit alignment in HLASM syntax
While trying to understand a crash, I noted that the emitted alignment
in HLASM is wrong. There are 2 issues:
- The decision which suffix to use looks at `FillLen` instead of
`Alignment`
- The label alignment `DS 0H` is hard-coded
This change fixes the issues. To get the correct suffix for the
label alignment, the emission of the alignment is postponed in
certain cases, and the label definition picks up the alignment
suffix.
[Attributor] Compare an indirect call's callee in the program address space (#222097)
Specializing an indirect call emits, for each candidate callee, an
`icmp` between
the call's callee operand and the candidate. The operand was first
normalized to
address space 0, but the candidates are functions, and functions live in
the
target's program address space. Where that is not 0 the two sides of the
comparison had different types and the `icmp` asserted:
```
Instructions.h:1266: void llvm::ICmpInst::AssertOK(): Assertion
`getOperand(0)->getType() == getOperand(1)->getType() &&
"Both operands to ICmp instruction are not of the same type!"' failed.
```
Normalize to the program address space instead. It is 0 unless a target
says
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[CIR] Accept a union covered only by a bit-field's declared type
The size of a union is calculated by its largest member. When that
member is a bit-field, the unit storing it can be narrower than the type
it was declared with, and it is the declared type that accounts for the
union's bytes. BitFieldType gains a query for that declared type, and
the x86_64 union rule reads it rather than the stored size, so
`union { int x : 3; }` and `union { int x : 3; char c; }` now both pass
as i32.
A union larger than one eightbyte still needs a member covering it
outright, since the coerce basis skips the entry carrying the
declaration.
Assisted-by: Cursor / claude-opus-5
[OpenMP][offload] Add LIBOMPTARGET_KERNEL_EXE_TIME
If set to 1, prints kernel-specific execution time.
This is a port of the original downstream ROCm patch, extended with the
inclusion of the kernel name in the printed line.
Claude assisted with this patch.
Co-authored-by: Kewen Meng <kewen.meng at amd.com>
[ConstraintElim] Support IV increments via [u|s]add.with.overflow. (#221771)
Treat [u|s]add.with.overflow like plain add when looking for increment
of an IV. We do not retrieve any wrap flags from the IR in that case, and
leave it to SCEV to determine them as needed.
This did not show any improvements on the workloads in
llvm-opt-benchmark-nightly, but helps to remove runtime checks for Swift
code end-to-end (see newly added PhaseOrdering test).
Alive2 Proof: https://alive2.llvm.org/ce/z/o2vMyw
PR: https://github.com/llvm/llvm-project/pull/221771
[compiler-rt] Add llvm-link deps when building compiler-rt builtins for spirv64 targets (#221906)
https://github.com/llvm/llvm-project/pull/214149 uses llvm-link to
create libclang_rt.builtins.bc from static archive library. It is better
to follow libclc approach to add llvm-link dependency for
builtin-spirv64* in llvm runtime CMakeLists.txt.
Signed-off-by: jinge90 <ge.jin at intel.com>
Fix extension matching and reachable path merging
Metadirective semantic checking relies on ranked selection to decide which
replacements need validation. With match_any and match_none, a selector can
remain applicable even when some construct traits are absent. The existing
matching and path-merging assumptions do not fully account for this, so
ranking can crash or discard a reachable replacement, allowing invalid loop
nests to pass unchecked.
Make applicability, scoring, and reachable-path merging agree on what these
matching extensions can observe. Preserve enough construct context to rank
partially matching selectors and distinguish paths whose nesting changes
the selected replacement. That context must also remain visible inside a
BLOCK associated with a selected directive, so nested metadirectives are
checked against the context in which they can execute.
[SelectionDAG][NFC] Move EmitStackConvert from LegalizeDAG to SelectionDAG (#221357)
I've ran into multiple instances, include #221358 , where I need to
effectively "bitcast" an integer value to a floating point value with
different width (and vice versa). To my best understandings storing into
stack and loading back is the only feasible way. LegalizeDAG already has
this routine, so I thought it might be a good idea to extract it out and
put inside SelectionDAG.
NFC.
