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Created using spr 1.3.7

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

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rebase

Created using spr 1.3.7

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]

rebase

Created using spr 1.3.7

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]

rebase

Created using spr 1.3.7

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]

[mlir][SPIR-V] Reject initializer on Import-linkage GlobalVariable (#192302)

Per the SPIR-V spec, a module-scope OpVariable with Import linkage must
not have an initializer

clean up

[AMDGPU] Add true16 patterns for build_vector (vgpr, 0)

It is shorter than VOP3 and instruction and in some cases
can save a second move.

[AMDGPU] Enable true16 pattern to build vectors (0, vgpr) (#191896)

Fixes: https://github.com/llvm/llvm-project/issues/190796

AMDGPU/GlobalISel: RegBankLegalize rules for async LDS loads (#192179)

Add RegBankLegalize rules for async LDS load intrinsics:
llvm.amdgcn.asyncmark
llvm.amdgcn.wait.asyncmark
llvm.amdgcn.global.load.async.to.lds.b8
llvm.amdgcn.global.load.async.to.lds.b32
llvm.amdgcn.global.load.async.to.lds.b64
llvm.amdgcn.global.load.async.to.lds.b128

[clang] Store size & mtime in in-memory module cache (#190207)

In this PR, the in-memory module cache now stores the size and
modification time of PCM files. This is needed so that the
`ModuleManager` doesn't need to consult the file system to obtain this
information, which _might_ be in a different state than when we stored
the PCM file buffer into the in-memory cache.

[AMDGPU] Mark s_get_*_barrier_state intrinsics always uniform (#192190)

Both intrinsics return a 32-bit SGPR value containing the barrier's
member count and signal count.

[llvm][DebugInfo] Use formatv in DWARFAcceleratorTable (#191981)

This relates to #35980.

AMDGPU/GlobalISel: RegBankLegalize rules for G_AMDGPU_S_BUFFER_PREFETCH (#191315)

[compiler-rt][Fuchsia] Use dynamic shadow global in hwasan runtime (#192148)

For now, the global is still default initialized to zero.

[CIR] Add EH handling for lifetime extended cleanups (#192305)

This adds code to call pushDestroyAndDeferDeactivation from the
pushLifetimeExtendedDestroy function. This was needed to generate the
correct code for lifetime extended cleanups when exceptions are enabled.
An extended version of the cleanup with automatic storage duration is
used as a test case.

To make this work correctly, I had to add a CleanupDeactivationScope to
RunCleanupsScope and force deactivation when forceCleanup is called.
This matches the corresponding code in classic codegen.

I surveyed other places where classic codegen is using
CleanupDeactivationScope and added a MissingFeatures marker in one
location where it was not previously marked. Other places where it was
missing were already marked in this way.

[flang] implements a rewrite pattern to constant fold fir::BoxEleSizeOp (#192320)

Implements a rewrite pattern to constant fold an `fir::BoxEleSizeOp`
when possible.

[flang][test] Experimental support of MemoryEffectOpInterface for fir.call. (#191580)

I would like to experiment with `fir.call` implementing
`MemoryEffectOpInterface`. So the main change is the fall-through
path in FIR AA. It should be NFC for Flang.

fix build issue

fix merge issues

concise findCXXNewExpr

[CUDA] Change __CUDACC__ definition to 1 (#189457)

I recently encountered an issue where `nccl` used `#if __CUDACC__` ,
assuming `__CUDACC__` is not only defined but having a #if-able value.


https://github.com/NVIDIA/nccl/blob/v2.28.3-1/src/include/nccl_device/coop.h#L18

Looking at nvcc invocation, I see that:
```
echo "" | nvcc -x cu -E -Xcompiler -dM - | grep __CUDACC__
#define __CUDACC__ 1
```

Changing __CUDACC__ to 1 to match what NVIDIA downstream code
assumptions.

format

Merge branch 'users/ziqingluo/PR-172429193-2-split-2' into users/ziqingluo/PR-172429193-2-split-3

 Conflicts:
        clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp

add docs

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Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484

Formatting

Change-Id: I3d89fba145471141ef945b1de15330caa245e82d