LLVM/project 383f4cfllvm/include/llvm/ExecutionEngine/Orc DlfcnSPS.h Dlfcn.h, llvm/include/llvm/ExecutionEngine/Orc/Shared/SPSCI DlfcnSPSCI.h

[ORC] Drive LLJIT dlopen/dlupdate/dlclose via proxies (#224881)

Add Dlfcn proxies (Dlfcn.h), their SPS specs (DlfcnSPS.h) and CI
descriptors (DlfcnSPSCI.h), and route ORCPlatformSupport's three
callSPSWrapper sites through them via recordProxy.
DeltaFile
+38-45llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
+51-0llvm/include/llvm/ExecutionEngine/Orc/Shared/SPSCI/DlfcnSPSCI.h
+38-0llvm/include/llvm/ExecutionEngine/Orc/Dlfcn.h
+36-0llvm/include/llvm/ExecutionEngine/Orc/DlfcnSPS.h
+163-454 files

LLVM/project 08daaa8libcxx/test/std/containers/container.adaptors/flat.map types.verify.cpp, libcxx/test/std/containers/container.adaptors/flat.multimap types.verify.cpp

[libc++] Update container adaptors' type verification tests (#224810)

1. Improves the error message for LWG2566.
2. Converts related compile.fail.cpp tests to verify.cpp tests.
3. Updates all related tests.
4. Removes some redundant tests (e.g. `[[nodiscard]]` is tested
elsewhere).

References:
- https://wg21.link/lwg2566
- https://wg21.link/container.adaptors
- https://wg21.link/flat.map.overview#7
- https://wg21.link/flat.map.overview#8
- https://wg21.link/flat.multimap.overview#7
- https://wg21.link/flat.multimap.overview#8
- https://wg21.link/flat.multiset.overview#7
- https://wg21.link/flat.multiset.overview#8
- https://wg21.link/flat.set.overview#7
- https://wg21.link/flat.set.overview#8

    [4 lines not shown]
DeltaFile
+0-35libcxx/test/std/containers/container.adaptors/stack/stack.defn/types.compile.fail.cpp
+33-0libcxx/test/std/containers/container.adaptors/flat.multimap/types.verify.cpp
+33-0libcxx/test/std/containers/container.adaptors/flat.map/types.verify.cpp
+26-0libcxx/test/std/containers/container.adaptors/flat.set/types.verify.cpp
+26-0libcxx/test/std/containers/container.adaptors/flat.multiset/types.verify.cpp
+0-22libcxx/test/std/containers/container.adaptors/stack/stack.defn/empty.verify.cpp
+118-5713 files not shown
+194-15219 files

LLVM/project c4f702aclang/lib/AST/ByteCode Pointer.h Interp.cpp

[clang][bytecode] Remove unnecessary pointer type checks in CheckLoad/CheckStore (#224884)

Only check the pointer type once.
DeltaFile
+24-18clang/lib/AST/ByteCode/Interp.cpp
+4-1clang/lib/AST/ByteCode/Pointer.h
+28-192 files

LLVM/project 780937fclang/lib/AST/ByteCode Interp.h Opcodes.td, clang/test/AST/ByteCode module-default-ctor.cpp

[clang][bytecode] Add a special opcode for trivial default initializers (#224839)

Trivial default initializers from modules are not implicitly defined in
the AST, so we would diagnose the attached test case as an undefined
constructor. Do what the current interpreter does and special-case this.

Fixes https://github.com/llvm/llvm-project/issues/221400
DeltaFile
+63-0clang/lib/AST/ByteCode/Interp.cpp
+12-0clang/test/AST/ByteCode/Inputs/default-ctor.cppm
+11-0clang/test/AST/ByteCode/module-default-ctor.cpp
+10-0clang/lib/AST/ByteCode/Compiler.cpp
+5-0clang/lib/AST/ByteCode/Opcodes.td
+1-0clang/lib/AST/ByteCode/Interp.h
+102-06 files

LLVM/project ccf2bd8clang/test/CodeGenCXX builtin-clear-padding-codegen.cpp, llvm/lib/Target/Xtensa XtensaS3DSPInstrInfo.td

minor cleanups, should be ready now

Created using spr 1.3.8-beta.1
DeltaFile
+11,213-152llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+4,377-4,141llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,753-0llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td
+2,822-2,774llvm/test/CodeGen/AMDGPU/bf16.ll
+4,402-1,088clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+2,633-2,496llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+31,200-10,6514,046 files not shown
+205,345-93,1734,052 files

LLVM/project 2d2c16eclang/test/CodeGenCXX builtin-clear-padding-codegen.cpp, llvm/lib/Target/Xtensa XtensaS3DSPInstrInfo.td

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+11,213-152llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+4,377-4,141llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+5,753-0llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td
+2,822-2,774llvm/test/CodeGen/AMDGPU/bf16.ll
+4,402-1,088clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+2,633-2,496llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+31,200-10,6514,042 files not shown
+205,283-93,0944,048 files

LLVM/project 892d3e9llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.mul.i24.ll rotl.ll

[SelectionDAG] Handle constants in SimplifyMultipleUseDemandedBits

Replace a non-zero constant with zero when none of its set bits are
demanded.

This allows users of `SimplifyMultipleUseDemandedBits` to eliminate
irrelevant constant bits while preserving the convention that a null
SDValue indicates no simplification.
DeltaFile
+38-45llvm/test/CodeGen/AMDGPU/rotl.ll
+3-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+3-4llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll
+2-4llvm/test/CodeGen/SystemZ/shift-08.ll
+2-4llvm/test/CodeGen/SystemZ/shift-04.ll
+6-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+54-632 files not shown
+57-668 files

LLVM/project 0213704llvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

[SelectionDAG][AMDGPU] Fold mul24 with an AND operand whose low bits are zero

Use SimplifyMultipleUseDemandedBits to simplify AND operands based on the
low 24 bits consumed by mul24.

Fold the multiply to zero when the simplified operand is zero.

This folds cases such as:

  mul24(x & 0xff000000, y) -> 0
DeltaFile
+8-8llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+6-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
+5-0llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+19-113 files

LLVM/project 761561alldb/test/API/functionalities/scripted_process TestScriptedProcess.py

[lldb/test] Skip test_scripted_process_addressable_bits on Windows (#224878)

This test is the first one in its directory to reach `self.build()` on
Windows, where the Makefile only knows how to build a dylib, so linking
the test binary fails on an undefined `baz` symbol.

Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
DeltaFile
+2-0lldb/test/API/functionalities/scripted_process/TestScriptedProcess.py
+2-01 files

LLVM/project 85ac560clang/docs ReleaseNotes.md, clang/lib/CodeGen CGDecl.cpp

[Clang][CodeGen] Fix crash in EmitParmDecl for bodyless destructors with -fextend-variable-liveness (#218830)

The fake-use coroutine check in EmitParmDecl calls
FnDecl->getBody()->getStmtClass() without guarding against a null
getBody(). This crashes when processing implicit parameters (e.g.
should_call_delete) of MSVC deleting destructors whose base destructor
is only declared, not defined.
DeltaFile
+17-0clang/test/CodeGen/fake-use-msvc-dtor.cpp
+1-1clang/lib/CodeGen/CGDecl.cpp
+1-0clang/docs/ReleaseNotes.md
+19-13 files

LLVM/project b1aa74dllvm/unittests/Target/RISCV RISCVInstrInfoTest.cpp

[RISCV][XQCI] Add a test that shows getInstSizeInBytes returning an incorrect instruction size. NFC (#224787)

Follow up to https://github.com/llvm/llvm-project/pull/223913 that shows
`getInstSizeInBytes` returning an incorrect instruction size of 2 when
the 6 byte `Xqci` instruction compresses to a 4 byte instruction.

An AI agent assisted in the generation of the test.
DeltaFile
+97-2llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+97-21 files

LLVM/project c37874bllvm/lib/CodeGen ProcessImplicitDefs.cpp, llvm/test/CodeGen/AMDGPU early-lis-two-address-regsequence-undef.mir detect-dead-lanes-tied-undef.mir

[CodeGen] Reject undef tied use sharing a virtual register with another read (#222832)

A virtual use operand, tied to a def of a different register, sharing
the register with another read, carries obligation that is hard to
follow by passes. For example, twoaddressinstruction would use different
physical registers, breaking the expectation of the `IsUndef` flag:

```
define void @f() {
  %y = freeze i32 undef
  %m = mul i32 %y, %y
  call void asm sideeffect "# use $0", "{cx}"(i32 %m)
  ret void
}

%2 = IMUL32rr undef %1(tied-def 0), undef %1   ; before twoaddressinstruction
%2 = IMUL32rr undef %2(tied-def 0), undef %1   ; after
imull %eax, %ecx                               ; different regs
```

    [10 lines not shown]
DeltaFile
+71-0llvm/test/CodeGen/X86/process-implicit-defs-tied-undef.mir
+18-6llvm/lib/CodeGen/ProcessImplicitDefs.cpp
+23-0llvm/test/CodeGen/AMDGPU/detect-dead-lanes-tied-undef.mir
+22-0llvm/test/MachineVerifier/tied-undef-use.mir
+21-0llvm/test/CodeGen/AMDGPU/early-lis-two-address-regsequence-undef.mir
+20-0llvm/test/CodeGen/X86/freeze.ll
+175-69 files not shown
+229-4015 files

LLVM/project 40e045elibc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll bf16.ll

Merge cascade
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+9,382-9,576llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+11,213-152llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+4,770-4,849llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+2,212,997-20,7025,127 files not shown
+2,470,325-154,8885,133 files

LLVM/project 3fbb4ddlibc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll bf16.ll

Merge cascade
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+9,382-9,576llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+11,213-152llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+4,770-4,849llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+2,212,997-20,7025,127 files not shown
+2,470,325-154,8885,133 files

LLVM/project 2dc308clibc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll bf16.ll

Merge cascade
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+9,382-9,576llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+11,213-152llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+4,770-4,849llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+2,212,997-20,7025,127 files not shown
+2,470,325-154,8885,133 files

LLVM/project bce6829libc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.512bit.ll bf16.ll

Merge cascade
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+9,382-9,576llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+11,213-152llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+4,770-4,849llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+2,212,997-20,7025,127 files not shown
+2,470,325-154,8885,133 files

LLVM/project a74fb3flibc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU bf16.ll amdgcn.bitcast.960bit.ll

Merge cascade
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+65,634-64,263llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+11,404-11,457llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,656-7,977llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+2,270,326-89,8227,672 files not shown
+2,683,491-293,6237,678 files

LLVM/project 5d2132dlibc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU bf16.ll amdgcn.bitcast.960bit.ll

Merge cascade
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+65,634-64,263llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+11,404-11,457llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,656-7,977llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+2,270,326-89,8227,672 files not shown
+2,683,491-293,6237,678 files

LLVM/project 1323d24libc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU bf16.ll amdgcn.bitcast.960bit.ll

Merge cascade
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+65,634-64,263llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+11,404-11,457llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,656-7,977llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+2,270,326-89,8227,672 files not shown
+2,683,491-293,6237,678 files

LLVM/project e8b3177libc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU bf16.ll amdgcn.bitcast.960bit.ll

Merge cascade
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+65,634-64,263llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+11,404-11,457llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,656-7,977llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+2,270,326-89,8227,672 files not shown
+2,683,491-293,6237,678 files

LLVM/project e31da6allvm/utils/gn/secondary/llvm/lib/Support BUILD.gn

[gn build] Port fce3facdfe49 (#224872)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
+1-01 files

LLVM/project 0ada78bllvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc BUILD.gn

[gn build] Port f43368b4d45e (#224871)
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
+1-01 files

LLVM/project e3adc74llvm/utils/gn/secondary/libcxx/include BUILD.gn

[gn build] Port 551af79c9031 (#224870)
DeltaFile
+1-0llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+1-01 files

LLVM/project 5261c03libc/test/src/math/exhaustive cos.wc sin.wc, llvm/test/CodeGen/AMDGPU bf16.ll amdgcn.bitcast.960bit.ll

Merge cascade
DeltaFile
+1,091,085-0libc/test/src/math/exhaustive/sin.wc
+1,090,178-0libc/test/src/math/exhaustive/cos.wc
+65,634-64,263llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+11,404-11,457llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+5,656-7,977llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+6,369-6,125llvm/test/CodeGen/AMDGPU/bf16.ll
+2,270,326-89,8227,669 files not shown
+2,682,654-293,5607,675 files

LLVM/project 9c3bc81llvm/lib/Target/AMDGPU AMDGPU.td, llvm/lib/TargetParser AMDGPUTargetParser.cpp

[AMDGPU] Add LDS encoding granularity to TargetParser

Model LDS encoding granularity with dedicated features and expose the
byte-valued getLDSEncodingGranule query for GPUKind and subarch. Keep
encoding independent of the hardware allocation granularity used for
occupancy; GFX10.3, GFX11 and GFX12.0 encode in 512-byte units while
allocating 1024-byte blocks.

Migrate program resource register and PAL metadata encoding to the new
query and remove getLdsDwGranularity from AMDGPUBaseInfo. gfx9-4-generic
uses gfx950's 1280-byte encoding granule independently of LDS capacity.

Test encoding queries, feature membership, generic-target validation and
encoded LDS sizes, including the GFX10.3 allocation/encoding distinction.

Change-Id: I9d3c2c041605e9a45fa8fbda09fc3460a74953ea
DeltaFile
+57-31llvm/unittests/TargetParser/TargetParserTest.cpp
+37-5llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td
+34-1llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+34-0llvm/test/CodeGen/AMDGPU/lds-size-gfx9-4-generic.ll
+26-0llvm/test/CodeGen/AMDGPU/lds-size-gfx1030.ll
+20-0llvm/lib/Target/AMDGPU/AMDGPU.td
+208-377 files not shown
+235-5913 files

LLVM/project 1843845llvm/lib/Target/AMDGPU AMDGPUFeatures.td AMDGPU.td, llvm/lib/TargetParser AMDGPUTargetParser.cpp

[AMDGPU] Add `getLDSAllocGranule` to TargetParser (#220051)
DeltaFile
+95-0llvm/unittests/TargetParser/TargetParserTest.cpp
+30-22llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
+42-0llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td
+34-1llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+29-5llvm/lib/Target/AMDGPU/AMDGPU.td
+14-0llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
+244-283 files not shown
+256-329 files

LLVM/project b03138autils/bazel/llvm-project-overlay/libc BUILD.bazel, utils/bazel/llvm-project-overlay/libc/test/src/math BUILD.bazel

[bazel] Fix the build after 8c8740bd92197171d5873f77a66bb68217926fb2/2747501774ba93685fc460abafb395e585a86b13 (#224868)
DeltaFile
+117-14utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+22-3utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
+22-3utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
+161-203 files

LLVM/project fd2f25dclang/lib/StaticAnalyzer/Checkers/WebKit RawPtrRefLocalVarsChecker.cpp

[WebKit Checkers][NFC] Thread the sink type through the local vars checker (#224862)

So an upcoming borrow checker can track assignment through indirection.

For example, in `out = &vec`, where `out`'s declared type is
`Vector<char>*&`, the relevant sink type is `Vector<char>*`.

Assisted-by: Claude
DeltaFile
+11-10clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
+11-101 files

LLVM/project c89ca1bllvm/test/Transforms/SLPVectorizer/X86 extracted-subfields.ll

[SLP][NFC]Add a test with a missed vectorization, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/224865
DeltaFile
+384-0llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields.ll
+384-01 files

LLVM/project acd9cdallvm/utils/release github-upload-release.py

github-upload-release: Create draft releases (#209876)

https://discourse.llvm.org/t/rfc-enabling-immutable-releases-v2/91180
DeltaFile
+3-1llvm/utils/release/github-upload-release.py
+3-11 files