LLVM/project ad9ecc4libcxx/docs ABIGuarantees.rst, libcxx/include deque

[libcxx] Configuration option to lower deque block size (#198348)
DeltaFile
+26-20libcxx/test/libcxx/containers/sequences/deque/spare_block_handling.pass.cpp
+29-0libcxx/test/libcxx/containers/sequences/deque/lower_deque_block_size.default.compile.pass.cpp
+28-0libcxx/test/libcxx/containers/sequences/deque/lower_deque_block_size.lower.compile.pass.cpp
+7-0libcxx/include/deque
+4-0libcxx/docs/ABIGuarantees.rst
+1-0libcxx/utils/libcxx/test/features/libcxx_macros.py
+95-201 files not shown
+96-207 files

LLVM/project ec013bfllvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx vhaddw.ll vhsubw.ll

Fix DAG combine for illegal vector types
DeltaFile
+8-252llvm/test/CodeGen/LoongArch/lasx/vhaddw.ll
+8-252llvm/test/CodeGen/LoongArch/lasx/vhsubw.ll
+6-39llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll
+6-39llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll
+3-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+31-5825 files

LLVM/project bd3d292llvm/lib/Target/LoongArch LoongArchISelLowering.cpp LoongArchLSXInstrInfo.td

[LoongArch] Add DAG combine for horizontal widening add/sub

Add a DAG combine to recognize horizontal widening add/subtract patterns
and lower them to the corresponding LSX/LASX instructions.

The following pattern is matched for both signed and unsigned variants:

```
  ADD/SUB(SEXT/ZEXT(BUILD_VECTOR(extract_elt(vj, 1), extract_elt(vj, 3), ...)),
          SEXT/ZEXT(BUILD_VECTOR(extract_elt(vk, 0), extract_elt(vk, 2), ...)))
```

This covers the following instructions:

```
  LSX:  VHADDW.H.B,  VHADDW.W.H,  VHADDW.D.W
        VHADDW.HU.BU, VHADDW.WU.HU, VHADDW.DU.WU
        VHSUBW.H.B,  VHSUBW.W.H,  VHSUBW.D.W
        VHSUBW.HU.BU, VHSUBW.WU.HU, VHSUBW.DU.WU

    [10 lines not shown]
DeltaFile
+119-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+31-5llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+24-4llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+174-93 files

LLVM/project 4ca9a58llvm/test/CodeGen/LoongArch/lasx vhaddw.ll vhsubw.ll, llvm/test/CodeGen/LoongArch/lsx vhaddw.ll vhsubw.ll

[LoongArch][NFC] Add horizontal widening add/sub tests (#201487)
DeltaFile
+547-0llvm/test/CodeGen/LoongArch/lasx/vhaddw.ll
+547-0llvm/test/CodeGen/LoongArch/lasx/vhsubw.ll
+217-0llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll
+217-0llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll
+1,528-04 files

LLVM/project 1b6cb0dclang/lib/Sema SemaExprCXX.cpp, clang/test/CXX/drs cwg22xx.cpp cwg5xx.cpp

[Clang] Implement CWG 2282

Link: https://wg21.link/cwg2282

For non-overaligned types, overload resolution now falls back to aligned
allocation functions in C++20 and later.
DeltaFile
+41-16clang/lib/Sema/SemaExprCXX.cpp
+34-4clang/test/CXX/drs/cwg22xx.cpp
+8-5clang/test/CXX/expr/expr.unary/expr.new/p14.cpp
+7-6clang/test/SemaCXX/new-delete.cpp
+6-0clang/test/SemaCXX/std-align-val-t-in-operator-new.cpp
+3-2clang/test/CXX/drs/cwg5xx.cpp
+99-332 files not shown
+103-348 files

LLVM/project 264ac33clang/lib/Sema SemaExprCXX.cpp

[Clang][Sema][NFCI] Simplify `resolveAllocationOverload()`

`resolveAllocationOverload()` performs multiple rounds of overload
resolution (typed and untyped, aligned and unaligned), each requiring a
slightly different argument list. Previously, the argument vector was
mutated in-place, which made the flow hard to follow.

This refactor prepares the list of arguments before calling
`resolveAllocationOverload()`. The preferred argument list is passed in
`PrefArgs`, while the fallback arguments are passed in `FallbackArgs`.
If the fallback resolution is not required, `FallbackArgs` is empty.
When making a nested call to perform the resolution with the fallback
arguments, the current set of candidates is passed in `PrefCandidates`
(formerly, `AlignedCandidates`). This argument also serves as a flag
used to distinguish the top-level call from nested fallback calls.
DeltaFile
+77-98clang/lib/Sema/SemaExprCXX.cpp
+77-981 files

LLVM/project 884793dclang/lib/Sema SemaExprCXX.cpp, clang/test/CXX/drs cwg22xx.cpp cwg5xx.cpp

[Clang] Implement CWG 2282

Link: https://wg21.link/cwg2282

For non-overaligned types, overload resolution now falls back to aligned
allocation functions.
DeltaFile
+41-16clang/lib/Sema/SemaExprCXX.cpp
+34-4clang/test/CXX/drs/cwg22xx.cpp
+8-5clang/test/CXX/expr/expr.unary/expr.new/p14.cpp
+7-6clang/test/SemaCXX/new-delete.cpp
+6-0clang/test/SemaCXX/std-align-val-t-in-operator-new.cpp
+3-2clang/test/CXX/drs/cwg5xx.cpp
+99-332 files not shown
+103-348 files

LLVM/project d74770cllvm/include/llvm/Transforms/Coroutines CoroInstr.h, llvm/lib/Transforms/IPO ThinLTOBitcodeWriter.cpp WholeProgramDevirt.cpp

cfi creates alias
DeltaFile
+20-33llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
+20-5llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
+10-7llvm/test/Transforms/ThinLTOBitcodeWriter/comdat.ll
+16-0llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+13-0llvm/test/Transforms/Coroutines/coro-id-alias.ll
+8-4llvm/include/llvm/Transforms/Coroutines/CoroInstr.h
+87-498 files not shown
+116-6914 files

LLVM/project 6f02138llvm/include/llvm/IR GlobalValue.h, llvm/include/llvm/Transforms/Utils AssignGUID.h

Reland #184065
DeltaFile
+61-17llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+45-30llvm/lib/LTO/LTO.cpp
+64-2llvm/lib/IR/Globals.cpp
+49-3llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+45-5llvm/include/llvm/IR/GlobalValue.h
+49-0llvm/include/llvm/Transforms/Utils/AssignGUID.h
+313-57116 files not shown
+848-401122 files

LLVM/project 4808462clang/test/OpenMP target_map_nested_ptr_member_mapper_codegen.cpp, offload/test/mapping mapper_map_ptee_only_2_ptr_indirections_array.c mapper_map_ptee_only_2ndlevel_array.c

[NFC][OpenMP] Add mapper-specific tests exercising pointee seciton mapping.

Also add a couple of tests that require correct propagation of map-type-modifier
bits into the mapper.
DeltaFile
+211-0clang/test/OpenMP/target_map_nested_ptr_member_mapper_codegen.cpp
+93-0offload/test/mapping/mapper_map_ptee_only_2_ptr_indirections_array.c
+82-0offload/test/mapping/mapper_map_ptee_only_2ndlevel_array.c
+78-0offload/test/mapping/mapper_map_ptee_only_always_array.c
+61-0offload/test/mapping/mapper_map_ptee_only_2_ptr_indirections.c
+59-0offload/test/mapping/mapper_map_ptee_only_array.c
+584-011 files not shown
+875-717 files

LLVM/project edc5f47utils/bazel/llvm-project-overlay/llvm BUILD.bazel

[bazel][AVR] Fix 930a46d2379914172f9e9e5e108510aa43fb7934 (#204264)

Add AVR to the intrinsics list
DeltaFile
+4-0utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+4-01 files

LLVM/project 8bea2ffclang/lib/ScalableStaticAnalysisFramework/Core/Serialization/JSONFormat TUSummaryEncoding.cpp LUSummary.cpp, clang/unittests/ScalableStaticAnalysisFramework EntityLinkerTest.cpp

Reland "[clang][ssaf] Track target triple in TU and LU summaries. #204027" (#204259)

This commit introduces the following changes:

- Add `TargetTriple` field to `TUSummary`, `LUSummary`, and their encodings.
- Frontend captures the triple from `CompilerInstance::getTarget()` when extracting a TU summary.
- JSON format reads/writes a `target_triple` field at the root of each summary; reader rejects strings not in `llvm::Triple::normalize` form.
- All TU/LU JSON test inputs/outputs and unit tests updated to include the new field.
    
`clang-ssaf-linker` uses a hardcoded triple value for the link unit; surfacing the triple through the tool will be handled in a follow-up PR.
    
rdar://179403011
DeltaFile
+24-1clang/lib/ScalableStaticAnalysisFramework/Core/Serialization/JSONFormat/TUSummaryEncoding.cpp
+24-1clang/lib/ScalableStaticAnalysisFramework/Core/Serialization/JSONFormat/LUSummary.cpp
+24-1clang/lib/ScalableStaticAnalysisFramework/Core/Serialization/JSONFormat/LUSummaryEncoding.cpp
+24-1clang/lib/ScalableStaticAnalysisFramework/Core/Serialization/JSONFormat/TUSummary.cpp
+12-9clang/unittests/ScalableStaticAnalysisFramework/EntityLinkerTest.cpp
+16-0clang/lib/ScalableStaticAnalysisFramework/Core/Serialization/JSONFormat/JSONFormatImpl.cpp
+124-13177 files not shown
+573-175183 files

LLVM/project 0852756lldb/test/API/lang/cpp/abi_tag_structors TestAbiTagStructors.py, lldb/test/API/lang/cpp/namespace TestNamespaceLookup.py

[lldb][test] Skip even more unsupported tests on WebAssembly (#204255)

A second pass over the full API suite for tests that depend on features
unavailable on wasm32-wasip1 or in LLDB's Wasm support:

- Expression evaluation (skipIfWasm) for the C++ tests that the
"expression" category doesn't cover, since that category only applies to
commands/expression/*.

- Attaching to a running process (skipIfWasm). These tests have the
harness spawn the inferior as a host process and then attach, but a
.wasm module isn't a native executable, so exec'ing it fails with
ENOEXEC ("Exec format error"). The wasm module only runs inside the
runtime (e.g. iwasm) that LLDB launches, so there is no host process to
attach to.

Where a test also has supported, passing cases, the decorator is applied
per method.
DeltaFile
+4-1lldb/test/API/lang/cpp/symbols/TestSymbols.py
+4-1lldb/test/API/lang/cpp/operators/TestCppOperators.py
+4-1lldb/test/API/lang/cpp/printf/TestPrintf.py
+3-0lldb/test/API/lang/cpp/abi_tag_structors/TestAbiTagStructors.py
+3-0lldb/test/API/lang/cpp/namespace/TestNamespaceLookup.py
+2-0lldb/test/API/python_api/hello_world/TestHelloWorld.py
+20-318 files not shown
+39-524 files

LLVM/project dec01d8llvm/lib/Target/DirectX DXContainerPDB.cpp

Use c_str for formatv
DeltaFile
+2-2llvm/lib/Target/DirectX/DXContainerPDB.cpp
+2-21 files

LLVM/project 9ededdaclang/lib/CodeGen CGCall.cpp, clang/test/CodeGenHLSL/resources cbuffer_struct_passing.hlsl

[HLSL] Codegen for passing cbuffer structs as function args (#203961)

Constant buffer structs are in `hlsl_constant` address space and have a
different layout than structs in default address space. They need to be
copied element-by-element and not by `memcpy`.

This change adds a check for the `hlsl_constant` address space to the
code path that avoids materializing a temporary copy for simple
`CK_LValueToRValue ` casts. This makes sure the constant buffer structs
is copied element-by-element to a temporary before being passed to a
function.
DeltaFile
+120-0clang/test/CodeGenHLSL/resources/cbuffer_struct_passing.hlsl
+11-7clang/lib/CodeGen/CGCall.cpp
+131-72 files

LLVM/project ea1b8c3clang/lib/Sema SemaExprCXX.cpp

[Clang][Sema][NFCI] Simplify `resolveAllocationOverload()`

`resolveAllocationOverload()` performs multiple rounds of overload
resolution (typed and untyped, aligned and unaligned), each requiring a
slightly different argument list. Previously, the argument vector was
mutated in-place, which made the flow hard to follow.

This refactor prepares the list of arguments before calling
`resolveAllocationOverload()`. The preferred argument list is passed in
`PrefArgs`, while the fallback arguments are passed in `FallbackArgs`.
If the fallback resolution is not required, `FallbackArgs` is empty.
When making a nested call to perform the resolution with the fallback
arguments, the current set of candidates is passed in `PrefCandidates`
(formerly, `AlignedCandidates`). This argument also serves as a flag
used to distinguish the top-level call from nested fallback calls.
DeltaFile
+77-98clang/lib/Sema/SemaExprCXX.cpp
+77-981 files

LLVM/project 2208263lldb/bindings/python CMakeLists.txt, lldb/examples/python delayed_enable.py

Add a useful command to the python examples & "lldb.utils" (#204251)

When debugging GUI programs where you have a bunch of breakpoints set
that you only want to have trigger when in the middle of some UI
interaction (a drag and drop for example) but not before, you need a way
to have the breakpoints disabled till a certain point, then re-enabled.
But since you are in the middle of the interaction, you can't interact
with the debugger to do that.

This little command disables your breakpoints, continues if you were
stopped, waits for a prescribed interval, then re-enables them.
DeltaFile
+69-0lldb/examples/python/delayed_enable.py
+1-0lldb/bindings/python/CMakeLists.txt
+70-02 files

LLVM/project 33b2aa3llvm/lib/Target/Mips/AsmParser MipsAsmParser.cpp, llvm/lib/Target/RISCV RISCVInstrInfoY.td RISCVInstrInfoZc.td

rebase

Created using spr 1.3.8-beta.1
DeltaFile
+171-0llvm/test/TableGen/getRegClassFromMatchKind.td
+80-0llvm/utils/TableGen/AsmMatcherEmitter.cpp
+0-22llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+8-8llvm/lib/Target/RISCV/RISCVInstrInfoY.td
+5-5llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+1-0llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+265-359 files not shown
+274-3515 files

LLVM/project 6d2a201llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, llvm/test/CodeGen/AMDGPU/NextUseAnalysis spill-vreg-many-lanes.mir acyclic-770bb.mir

Merge branch 'main' into users/ilovepi/clang-trap-unreachable
DeltaFile
+275,101-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+92,890-85,927llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+144,679-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+44,396-53,126llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+57,682-0llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+28,845-27,920llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+643,593-166,97338,347 files not shown
+4,718,876-1,847,02438,353 files

LLVM/project 5639b33compiler-rt/lib/scudo/standalone combined.h, compiler-rt/lib/scudo/standalone/tests combined_test.cpp

[scudo] For a realloc that shrinks, retag the extra. (#204031)

When MTE is enabled and an allocations is reallocated from a large size
to a smaller size, zero tag the rest of the allocation. Before this
change only a single granule after the new size was zero tagged. This
adds extra security and use after realloc protection if code would have
tried to read/write into the old size, past the new size.
DeltaFile
+38-0compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
+17-7compiler-rt/lib/scudo/standalone/combined.h
+55-72 files

LLVM/project 1e3b03dllvm/lib/Target/BPF/AsmParser BPFAsmParser.cpp, llvm/lib/Target/M68k/AsmParser M68kAsmParser.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+171-0llvm/test/TableGen/getRegClassFromMatchKind.td
+80-0llvm/utils/TableGen/AsmMatcherEmitter.cpp
+1-0llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+1-0llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
+1-0llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+1-0llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+255-06 files not shown
+261-012 files

LLVM/project 212ae44llvm/lib/Target/AMDGPU/Disassembler CMakeLists.txt

AMDGPU: Add TargetParser to disassembler dependencies (#204250)

Should fix build failure after #203979, but should be reverted
in #204150
DeltaFile
+1-0llvm/lib/Target/AMDGPU/Disassembler/CMakeLists.txt
+1-01 files

LLVM/project e604dbellvm/lib/Target/RISCV RISCVRegisterInfo.td, llvm/test/MC/RISCV/rvy rvyc-valid-load-store.s rvy-valid-load-store.s

restack on top of main instead

Created using spr 1.3.8-beta.1
DeltaFile
+0-465llvm/test/MC/RISCV/rvy/rvyc-valid-load-store.s
+12-274llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+0-199llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
+0-144llvm/test/MC/RISCV/rvy/rvyc-invalid-load-store.s
+38-78llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+0-93llvm/test/MC/RISCV/rvy/rvy-invalid-load-store.s
+50-1,25340 files not shown
+170-1,85146 files

LLVM/project f2d2d98bolt/runtime instr.cpp, bolt/test/runtime setup-race.cpp

[BOLT] Delay indirect call pointer setup (#204229)

There is a race in the instrumentation runtime during setup. The setup
initializes the function pointers for indirect call instrumentation
before the indirect call counters array. If the application spawns a
background thread through a constructor (as does jemalloc), the
background thread has a chance to derefence that uninitialized array
pointer. Defer initialization of these function pointers to prevent this
race.

Fixes #198181.

Co-authored-by: Fabian Parzefall <parzefall at meta.com>
DeltaFile
+45-0bolt/test/runtime/setup-race.cpp
+6-2bolt/runtime/instr.cpp
+51-22 files

LLVM/project 312bd8allvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp SIISelLowering.cpp

[AMDGPU] Guard more intrinsics with target features
DeltaFile
+1-51llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+0-42llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+0-24llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+15-2llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+4-4llvm/test/CodeGen/AMDGPU/unsupported-av-store.ll
+4-4llvm/test/CodeGen/AMDGPU/unsupported-av-load.ll
+24-12712 files not shown
+45-14318 files

LLVM/project 9486b07clang/lib/CodeGen CodeGenAction.cpp, llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp

[RFC][CodeGen] Add generic target feature checks for intrinsics

This PR adds target-independent infrastructure for annotating LLVM intrinsics
with required subtarget feature expressions.

It introduces a TargetFeatures string field to intrinsic TableGen records.
TableGen emits an intrinsic-to-feature mapping table.

Both SelectionDAG and GlobalISel now perform this check before lowering target
intrinsics. This allows targets to opt in by annotating intrinsic definitions
directly, rather than adding custom checks during lowering, legalization, or
instruction selection.

This PR uses one AMDGPU intrinsic as an example.
DeltaFile
+96-3llvm/lib/MC/MCSubtargetInfo.cpp
+37-0clang/lib/CodeGen/CodeGenAction.cpp
+36-0llvm/lib/IR/DiagnosticInfo.cpp
+33-1llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+28-0llvm/test/TableGen/intrinsic-target-features.td
+25-0llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+255-414 files not shown
+391-920 files

LLVM/project 2ff7220llvm/lib/Target/RISCV RISCVRegisterInfo.td, llvm/test/MC/RISCV/rvy rvyc-valid-load-store.s rvy-valid-load-store.s

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+0-465llvm/test/MC/RISCV/rvy/rvyc-valid-load-store.s
+12-274llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+0-199llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
+0-144llvm/test/MC/RISCV/rvy/rvyc-invalid-load-store.s
+38-78llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+0-93llvm/test/MC/RISCV/rvy/rvy-invalid-load-store.s
+50-1,25328 files not shown
+157-1,86934 files

LLVM/project ac131ebclang/lib/CodeGen CodeGenModule.cpp, clang/test/CodeGenCXX cxx20-nttp-object-layout.cpp

[Clang][CodeGen] Fix C++20 NTTP object field indexing (#204174)

C++20 allows a class object to be used as a non-type template
parameter. For example, a template can take an object of a struct like
`{ char A; long long B; char C; char First[2]; char Second[2]; }`.

That struct has padding before `B`. The constant emitter can represent
the value with an ordinary LLVM struct and let LLVM provide that padding
implicitly. Normal record CodeGen instead uses the memory type for the
record, which may contain explicit padding fields so C++ fields have
stable LLVM field numbers.

The bytes are laid out the same, but the LLVM field numbers are not.
For the normal padded record type, `First` has one field index. For the
compact constant type, that same index names a later field. Clang was
computing the field index for the padded record type, then applying it
to the compact template parameter object type. As a result, reading
`First` could read from the bytes for `Second` instead.


    [3 lines not shown]
DeltaFile
+44-0clang/test/CodeGenCXX/cxx20-nttp-object-layout.cpp
+3-2clang/lib/CodeGen/CodeGenModule.cpp
+47-22 files

LLVM/project e6a0490clang/lib/Format DefinitionBlockSeparator.cpp, clang/unittests/Format DefinitionBlockSeparatorTest.cpp

[clang-format] Stop inserting blank line in disabled region (#201995)

Previously, a blank got inserted before the `// clang-format off`
comment with the `SeparateDefinitionBlocks` option set.

Fixes #106983 and #146317.
DeltaFile
+30-0clang/unittests/Format/DefinitionBlockSeparatorTest.cpp
+5-0clang/lib/Format/DefinitionBlockSeparator.cpp
+35-02 files

LLVM/project e6f0dfbllvm/lib/Target/AMDGPU/Disassembler CMakeLists.txt

AMDGPU: Add TargetParser to disassembler dependencies

Should fix build failure after #203979, but should be reverted
in #204150
DeltaFile
+1-0llvm/lib/Target/AMDGPU/Disassembler/CMakeLists.txt
+1-01 files