[Clang][ExprConst] Accept prvalue for nothrow new
A user defined operator new can accept prvalue for nothrow. There is
no guarantee in spec that it should be lvalue. Relax the check with
side effect only.
[Clang][RISC-V] Fix lto-module-asm-abi.c on non-asserts/no-lld builds
Pass `-fno-discard-value-names` so the `entry:` label is preserved in
non-asserts builds, and drop `-fuse-ld=lld` so the driver check succeeds
on bots that do not have `ld.lld` installed.
Fixes: bf529329b5ce ("[RISC-V][LTO] Add baseline tests for LTO inline assembly and mapping symbols (#225129)")
[SDPatternMatch] Simplify EffectiveOperands and drop the template specialization. NFC (#226036)
The chain and glue operands are in fixed locations, we don't need a loop
to find them.
Use the template parameter to skip the constructor body instead of using
template specialization.
[MLIR][LLVM] Produce canonical const GEP in convertGEPOp (#226699)
The DataLayout overload of ConstantExpr::getGetElementPtr is the form
that replaces typed constant GEPs. Use it for inrange GEPs and fail
translation when the indices cannot be reduced to a byte offset.
This resolves
https://github.com/llvm/llvm-project/pull/220424#discussion_r4092337505
Assisted-by: grok-4.7
Signed-off-by: Letu Ren <fantasquex at gmail.com>
[Github] Build BOLT docs on changes (#226747)
We were already set up to build the BOLT docs, but the workflow did not
actually trigger on changes to the BOLT docs specifically. This change
fixes that.
[ValueTracking] Support Array and Structure in contains* check
Support Vector and Structure in containsUndefinedElement,
containsUndefOrPoisonElement, and containsConstantExpression. This is
achieved by using containsMatchingElement helper function, which
checks type recursively as Structure and Array are aggregates, which
can contain basically anything inside. This allows InstCombine to
fold these two types correctly.
[AMDGPU] Remove BaseInfo duplicates of TargetParser APIs
Use TargetParser for LDS sizes and VGPR hardware limits, retaining the
backend handling of dynamic VGPR allocation and architectural VGPRs on
targets with a unified register file.
Remove the TargetID factory wrapper and redundant type and SGPR constant
aliases. Update the subtarget, assembler, disassembler, target streamer,
and occupancy calculator callers.
Cover physical LDS allocation boundaries across GPU generations and
full/half-SIMD modes in the assembler tests.
Change-Id: Iacae35d939d8bc1d5d78ad9e545c6f1eb5cd38fe
[RISC-V] Update streamer ArchString in emitTargetFeaturePush() (#225133)
Previously, RISCVAsmPrinter::emitTargetFeaturePush() only emitted `.option push`
and `.option arch` without updating the streamer's active ArchString. When
emitting an ELF object file directly (`-filetype=obj`),
RISCVTargetELFStreamer::emitDirectiveOptionArch() is a no-op while
emitTargetFeaturePop() resets ArchString back to the pushed ArchString, so
module-level inline assembly and functions with custom `target-features` failed
to emit updated `$x<arch>` mapping symbols.
Call RTS.setArchString() with the parsed ISA string in emitTargetFeaturePush()
so `-filetype=obj` records the active `$x<arch>` mapping symbol alongside
`.option arch`.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225133
[RISC-V][MC] Update ELF streamer ArchString in setFlagsFromFeatures() (#225140)
During LTO, the TargetMachine subtarget is initialized with the linker's
default CPU (e.g. `generic-rv64`, `rv64i2p1`), while
RISCVAsmPrinter::emitStartOfAsmFile() reconstructs the module's actual ISA from
the `riscv-isa` module flag and calls RISCVTargetStreamer::setFlagsFromFeatures()
and RISCVTargetStreamer::emitTargetAttributes(). Because
RISCVTargetELFStreamer previously only initialized InitialArchString and
ArchString in its constructor rather than in setFlagsFromFeatures(), direct
object emission bypassed the update and tagged `.text` with `$xrv64i2p1`
instead of the module's full architecture string.
Move the InitialArchString and ArchString initialization into
RISCVTargetELFStreamer::setFlagsFromFeatures() and also call setArchString()
alongside emitTextAttribute(RISCVAttrs::ARCH, ...) in
RISCVTargetStreamer::emitTargetAttributes().
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225140
[RISC-V][MC] Fix mapping symbol section tracking on popSection() (#225131)
Previously, RISCVELFStreamer::changeSection() saved LastEMS and LastEmittedArch
under getPreviousSection().first instead of getCurrentSection().first. When
MCStreamer::popSection() switches back to a previous section,
getPreviousSection() already points to the destination section being restored
rather than the section being exited. This clobbered the destination section's
saved mapping symbol state and caused duplicate `$x<arch>` mapping symbols to
be emitted whenever returning to `.text`.
Use getCurrentSection().first instead, matching AArch64ELFStreamer and
ARMELFStreamer.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225131
[LTO] Preserve module inline asm target properties for .lto_discard and symvers (#225130)
Previously, LTO::addRegularLTO() and IRLinker::run() called
prependModuleInlineAsm() and appendModuleInlineAsm() with a plain string when
synthesizing `.lto_discard` and imported `.symver` directives, creating a new
GlobalAsmFragment with empty TargetCPU and TargetFeatures instead of preserving
the existing module inline asm's properties. Copy the front fragment's Props so
these synthesized directives are merged into the module's inline asm with the
same target features.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225130
[RISC-V][LTO] Add baseline tests for LTO inline assembly and mapping symbols (#225129)
No functional change intended here, just adding test coverage for RISC-V LTO
inline assembly ABI handling (following up on
https://github.com/llvm/llvm-project/pull/223606) and for the `$x<arch>` ELF
mapping symbols emitted for module and function target features.
The `TODO`s for `.lto_discard` dropping module inline asm target features and
for the missing/duplicate `$x<arch>` mapping symbols will be addressed in the
following commits.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225129
[M68k] Finish implementation of `MOVX` (move and extend) pseudo-instructions and fix related errors (#218938)
This patch adds remaining addressing modes to the "move and extend"
pseudo-instructions, and fixes a few errors and inconsistencies in the
logic that caused inefficient code generation.
- Remaining addressing modes were implemented to match non-pseudo `MOVE`
instructions.
- Names of the pseudos now correctly reflect the register classes they
operate on, e.g. `MOVZXd32r16` for XR16 -> DR32.
- Fixed an issue where `MOVZX` could be allocated to an address
register, which has no way to zero-extend the result. (There were even
some of these in the test `register-spills.ll`, emitted as illegal
instructions, but the test doesn't have instruction verification
enabled, so it wasn't caught.)
- Fixed some `extload` patterns where the register was unnecessarily
extended to 32 bits before being truncated to its final size, causing
redundant instructions to be omitted.
- Fixed `anyext` patterns lowering to `MOVZX` instead of `MOVX`, causing
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[SCEV] Remove unused classof(const SCEVUse *) overloads (NFC) (#226734)
isa/cast/dyn_cast on SCEVUse go through simplify_type or CastInfo.
classof(SCEVUse) is unused.
[LAA] Remove unused functions (NFC) (#226733)
Remove RuntimePointerChecking::empty and LoopAccessInfo::getNumLoads /
getNumStores, which have no callers, together with the NumLoads and
NumStores counters that were only read by the latter.
[LV] Skip low-trip count logic there is no scalar tail. (#225633)
https://github.com/llvm/llvm-project/pull/195823 added logic consider
vectorization of low trip count loops if there was no or a single
iteration remaining.
This causes loops to be vectorized with a VF where no scalar tail
remains, even if it is required for legality (loop with multiple
countable exits require scalar epilogue to pick the exit).
For now, limit to cases where there's a scalar iteration remaining.
PR: https://github.com/llvm/llvm-project/pull/225633
[VPlan] Take wide induction wrap flags from the increment of the phi. (#226726)
The binary operator of an integer InductionDescriptor is the incoming
value from the latch, which is not required to have the phi as operand.
E.g. for
%x = add i32 %iv, 5
%iv.next = add nuw nsw i32 %x, 1
the flags only apply to %x + 1, while the induction step is 6, and %iv +
6 may wrap even though %iv.next does not. Determine the wrap flags from
the increment of the header phi instead, and only if it adds to or
subtracts from the phi directly.
[LLVM][Docs] Define IR in the lexicon (#221388)
Define IR in the LLVM lexicon using terminology from the LLVM Language
Reference Manual, including its SSA-based structure and three equivalent
representations.
Fixes #139867
AI Usage: ChatGPT
FastISel: Assert the emitted instruction defines the result
The fallback path copied the result out of implicit_defs()[0], assuming
the first implicit physical register def is the result. That is an X86
assumption about MUL/IMUL, and it is unreachable for all but
fastEmitInst_r: FastISelEmitter skips any instruction whose first
operand is not an output register, so every opcode reaching these
helpers from generated code has an explicit def.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
ARM: Remove cached TargetABI from ARMBaseTargetMachine (#226482)
This cannot account for the "target-abi" module flag, so
let the uses query that. ARMElfTargetObjectFile was the one user of
this value, so this failed to respect the module flag.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
Mips: Properly account for target-abi in subtarget construction
Store the used ABI from the target-abi module flag and add it to the
subtarget map key, so the module flag is properly respected.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
[libc++][pstl] Add more benchmarks of the parallel algorithms (#225908)
This PR adds benchmarks of these 3 parallel algorithms:
- `std::find(policy, ...)`
- `std::sort(policy, ...)`
- `std::transform_reduce(policy, ...)`
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
[AArch64] Reorganise perfect shuffle generation. NFC (#224526)
This adds a generatePerfectShuffle implementation for parsing through
the perfect shuffle tables, generating a list of ShuffleEntry's that
represent the sequence of shuffles that need to be performed. This is
intended to be a NFC as-is, allowing it to be reused in global isel and
extended in the future to handle shuffles that are not part of the
shuffle table. The number of instructions generated can also be used for
costing shuffles, as we do for immediate generation.
[LV] Add tests for wide induction wrap flags (NFC). (#226715)
Add tests for:
* inductions where the lane offsets may signed-overflow, even if the
scalar induction values do not,
* inductions whose increment does not directly update the phi, where the
increment's wrap flags do not apply to the induction,
* narrow inductions where the VF may exceed the signed maximum of the
induction type.
