LLVM/project e2e8caflldb/docs/use/tutorials custom-frame-recognizers.md, lldb/source/Plugins/ScriptInterpreter/Python/Interfaces ScriptedStackFrameRecognizerPythonInterface.cpp

Add the ability to provide a scripted "step through" plan. (#218812)

This is a scripted equivalent of the "trampoline handler" that lldb uses
to run to the target of a dynamic dispatch stub, or to the target of
std::function, or an objc message send.
DeltaFile
+90-0lldb/test/API/commands/frame/recognizer/step-through/recognizer.py
+56-0lldb/test/API/commands/frame/recognizer/step-through/TestFrameRecognizerStepThrough.py
+43-0lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedStackFrameRecognizerPythonInterface.cpp
+26-0lldb/docs/use/tutorials/custom-frame-recognizers.md
+17-7lldb/source/Target/StackFrameRecognizer.cpp
+17-0lldb/test/API/commands/frame/recognizer/step-through/main.c
+249-713 files not shown
+333-719 files

LLVM/project aa8a758lld/MachO Config.h Options.td, lld/test/MachO strip-swift-force-load.s

[lld] strip __swift_FORCE_LOAD_$ dyld fixups in __DATA,__const (#214584)

Add a new flag to optionally strip swift FORCE_LOAD symbol sections,
which are used by the compiler to force dylib load commands. This has
shown a ~30% reduction in binds for some large applications, with
corresponding size reduction for the number of elided pointers.

This is based on a similar ld64 optimisation that removes the fixups for
the force load sections:

https://github.com/keith/ld64/blob/37d025c536163da612874999d0ea94a4e4e475e7/src/ld/passes/dylibs.cpp#L385-L389
DeltaFile
+112-0lld/test/MachO/strip-swift-force-load.s
+74-0lld/MachO/StripSwiftForceLoad.cpp
+32-0lld/MachO/StripSwiftForceLoad.h
+6-0lld/MachO/Driver.cpp
+3-0lld/MachO/Options.td
+1-0lld/MachO/Config.h
+228-01 files not shown
+229-07 files

LLVM/project 3e892fallvm/lib/Target/X86 X86ISelLoweringCall.cpp

[llvm][NFC] remove an unused variable (#219889)

Remove a variable `InsIndex` which was defined but never used anywhere.

Signed-off-by: Hardik Kumar <hardikxk at gmail.com>
DeltaFile
+1-2llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+1-21 files

LLVM/project 5406ca3flang/lib/Optimizer/Transforms/CUDA CUFDeviceFuncTransform.cpp, flang/test/Fir/CUDA cuda-device-func-transform.mlir

[flang][cuda] Extend CUF kernel host stub line table to the END statement (#219608)

`CUFDeviceFuncTransform` creates a host stub for a kernel, with an empty
body holding nothing but a `return`. Both the stub and its `return` keep
only the original declaration location, so the stub's line table ends up
with rows only for the declaration line.

This change extends the line table to span the procedure's whole source
line range, by using the location of the original `END` statement for
the stub's `return`. A debugger can then set a breakpoint on a line
inside the kernel body and stop there.

Lit test `cuda-device-func-transform.mlir` is enhanced to guard this
change.
DeltaFile
+16-0flang/test/Fir/CUDA/cuda-device-func-transform.mlir
+8-1flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
+24-12 files

LLVM/project 6f93872llvm/lib/Target/AMDGPU AMDGPU.td, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: Add visible features for aperture regs, doorbell ID and AGPR alloc (#219985)

These fields are needed to migrate AMDGPUAttributor to using
TargetParser information instead of subtarget features.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+21-6llvm/lib/Target/AMDGPU/AMDGPU.td
+4-3llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+25-92 files

LLVM/project ae35002llvm/test CMakeLists.txt

[Test] Add missing dependency for llvm-ordergen (#219992)

Without this dependency, `llvm-ordergen` is not build when running the
tests only, resulting in failures for the tool.
DeltaFile
+4-0llvm/test/CMakeLists.txt
+4-01 files

LLVM/project e85d0f7llvm/lib/Transforms/Scalar LoopFuse.cpp, llvm/test/Transforms/LoopFusion store_then_accumulate.ll

[LoopFusion] Allow fusing adjacent loops with same-iteration scalar deps (#216242)

The scalar dependence branch rejected all non-invariant flow deps, while
the array branch already accepted EQ-only direction vectors. Treat
same-iteration scalar flow/anti patterns as safe to fuse when the
dependence direction has no GT/LT component, matching the array logic.

Extra tests are added in
https://github.com/llvm/llvm-project/pull/216243
DeltaFile
+81-0llvm/test/Transforms/LoopFusion/store_then_accumulate.ll
+14-0llvm/lib/Transforms/Scalar/LoopFuse.cpp
+95-02 files

LLVM/project 7b91afalld/MachO Driver.cpp, lld/test/MachO exported-symbols-list-escapes.s

[GlobPattern] add AsLiteral to help lld determine if a symbol is literal (#215854)

lld determines if a `symbolName` is literal by `find_first_of("*?[]")`,
which is not accurate and ignored escape characters, we do the
following:

1. Add a new API `std::optional<std::string> asLiteral(...)` that dumps
the pattern as a literal string if it is one.
2. All `symbolNames` are considered as `GlobPattern` first to leverage
`asLeteral` to help us determine if a string is a literal. The quick
path in during `GlobPattern` construction is `if
(!S.find_first_of(PrefixMetas)) return Pat;`, so for strings without
`*?[]` (most of the `symbolName`s), the performance should be about the
same.
3. `symbolName`s that are literal go back to hashing like lld did before

Added tests in lld and unit test for GlobPattern

---------

Co-authored-by: Ellis Hoag <ellis.sparky.hoag at gmail.com>
DeltaFile
+89-0llvm/unittests/Support/GlobPatternTest.cpp
+73-0lld/test/MachO/exported-symbols-list-escapes.s
+28-0llvm/lib/Support/GlobPattern.cpp
+14-6lld/MachO/Driver.cpp
+11-0llvm/include/llvm/Support/GlobPattern.h
+215-65 files

LLVM/project 51e608flldb/source/Plugins/TypeSystem/Clang TypeSystemClang.cpp, lldb/test/API/lang/cpp/diamond main.cpp TestCppDiamond.py

[lldb][MSABI] Take offset of vbptr into account (#190679)

In the MS ABI, the offset found in the virtual base table is relative to
the virtual base pointer. See Clang's
`MicrosoftCXXABI::emitVBTableDefinition`:
https://github.com/llvm/llvm-project/blob/1a0ca1019d214a24b55a45704dc71fa183672362/clang/lib/CodeGen/MicrosoftCXXABI.cpp#L2247-L2261

We previously assumed the offset was relative to the record's start.

For example for `B` in
```cpp
struct Extra {
  int e1 = 1;
};
struct A {
  int a = 3;
};
struct B : public Extra, public virtual A {
  int b = 4;

    [24 lines not shown]
DeltaFile
+31-0lldb/test/API/lang/cpp/diamond/TestCppDiamond.py
+9-0lldb/test/API/lang/cpp/diamond/main.cpp
+2-0lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
+42-03 files

LLVM/project 77381f9llvm/lib/Target/AMDGPU AMDGPUMemoryUtils.cpp

Rename "mayAlias" -> "MayAlias"
DeltaFile
+4-4llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+4-41 files

LLVM/project 22f2915llvm/lib/Target/Hexagon HexagonXQFloatGenerator.cpp

Hexagon: Use use_instructions in checkHVXUses32/checkHVXUses16 (#220003)

The loops only inspect the using instruction, so iterate instructions
directly instead of operands and their parents.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+4-6llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
+4-61 files

LLVM/project bdaf20bllvm/lib/Target/PowerPC PPCReduceCRLogicals.cpp

PowerPC: Use use_instr_nodbg_begin in PPCReduceCRLogicals (#219988)

Fetch the using instruction directly through the instruction iterator
instead of dereferencing an operand's parent.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+1-1llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
+1-11 files

LLVM/project 7a845cellvm/lib/Target/AMDGPU SIInstrInfo.h SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU lit.local.cfg

add machine verifier check
DeltaFile
+84-3llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-0llvm/lib/Target/AMDGPU/SIInstrInfo.h
+2-0llvm/test/CodeGen/AMDGPU/lit.local.cfg
+89-33 files

LLVM/project eda5507llvm/test/CodeGen/AMDGPU flat-atomicrmw-fsub.ll flat-atomicrmw-fmin.ll

fix pattern
DeltaFile
+8,380-0llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
+1,481-1,527llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+542-1,095llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+12,029-5,90761 files not shown
+18,100-14,42367 files

LLVM/project 4c500c9llvm/test/CodeGen/AMDGPU fptoui-sat-scalar.ll usubsat.ll, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.raw.tbuffer.store.f16.ll

update test
DeltaFile
+154-269llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+146-218llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+106-170llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+123-131llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+42-89llvm/test/CodeGen/AMDGPU/usubsat.ll
+13-41llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+584-91813 files not shown
+718-1,10319 files

LLVM/project 3cc35d0llvm/test/CodeGen/AMDGPU global-atomicrmw-fadd.ll amdgcn.bitcast.128bit.ll, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-llvm.amdgcn.image.sample.a16.ll

calling conv update
DeltaFile
+4,190-4,346llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+2,769-2,019llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+1,592-1,625llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+748-1,428llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+1,308-842llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+1,248-856llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+11,855-11,116166 files not shown
+32,303-24,896172 files

LLVM/project 1e72279llvm/test/CodeGen/AMDGPU fptoui-sat-vector.ll fptosi-sat-vector.ll

Legalize sgpr16 in sdag
DeltaFile
+2,231-2,790llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+2,231-2,790llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+1,527-1,576llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+1,324-1,324llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+213-220llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+139-146llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+7,665-8,84634 files not shown
+8,915-10,24440 files

LLVM/project 854a747llvm/lib/Target/AMDGPU AMDGPUISelDAGToDAG.cpp, llvm/test/CodeGen/AMDGPU llvm.frexp.ll flat_atomics.ll

add more cases
DeltaFile
+53-35llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+46-38llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+40-39llvm/test/CodeGen/AMDGPU/flat_atomics.ll
+18-12llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
+18-12llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
+10-18llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
+185-15425 files not shown
+352-28731 files

LLVM/project e36563cllvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.sub.ll llvm.amdgcn.reduce.xor.ll, llvm/test/CodeGen/AMDGPU/GlobalISel bswap.ll

Legalize sgpr16 copy in gisel
DeltaFile
+393-208llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+55-167llvm/test/CodeGen/AMDGPU/fptrunc.ll
+106-99llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
+70-127llvm/test/CodeGen/AMDGPU/minmax.ll
+39-70llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+38-70llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+701-74141 files not shown
+1,236-1,46847 files

LLVM/project cda89a5llvm/lib/Target/AMDGPU SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.alignbyte.ll true16-fold.mir

fold sgpr32 via vgpr16
DeltaFile
+122-0llvm/test/CodeGen/AMDGPU/true16-fold.mir
+26-58llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+57-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+4-11llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
+212-741 files not shown
+213-767 files

LLVM/project 7650392llvm/lib/ExecutionEngine/Orc/TargetProcess LibraryResolver.cpp, llvm/lib/Passes CodeGenPassBuilder.cpp

[llvm] Remove unused includes (NFC) (#219915)

Identified by clang-tidy and verified with local builds.
DeltaFile
+0-7llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryResolver.cpp
+0-6llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp
+0-6llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
+0-6llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+0-6llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+0-6llvm/lib/Passes/CodeGenPassBuilder.cpp
+0-37263 files not shown
+0-396269 files

LLVM/project 435344cllvm/lib/Target/NVPTX NVPTXISelLowering.h NVPTXInstrInfo.td, llvm/test/CodeGen/NVPTX machinelicm-no-preheader.mir

[NVPTX] Use MCSymbols in Isel, remove mutable StrPool (NFC) (#219530)

Using MCSymbols is more idiomatic and allows us to remove mutable
members from the TM and simplifies MFI data structures.
DeltaFile
+36-37llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+11-19llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
+14-8llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+14-8llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+8-8llvm/test/CodeGen/NVPTX/machinelicm-no-preheader.mir
+5-5llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+88-858 files not shown
+107-10714 files

LLVM/project 8689d72llvm/docs AMDGPUMemoryModel.md AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUAnnotateUniformValues.cpp AMDGPUMemoryUtils.cpp

[AMDGPU] Make amdgpu.noclobber respect acquire operations

AMDGPUAnnotateUniformValues should annotate uniform global loads as
`!amdgpu.noclobber` if the memory they are reading is never clobbered (since
kernel launch) before the load is executed. That allows the backend to use
scalar `s_load_*` instructions instead of vector loads (which would otherwise
be illegal because the scalar cache is not kept coherent with the vector
cache).

So far, loads were annotated if the thread executing the load has not clobbered
the relevant memory location, but changes from concurrent threads that were
acquired via synchronization were ignored (which is unsound).

This patch defines a semantics for `!amdgpu.noclobber` metadata in the
AMDGPUUsage and changes AMDGPUAnnotateUniformValues to respect that semantics.
Now, loads are no longer annotated if they are atomic or if an acquire fence or
load can be executed before them (since they can read from stores in other
threads in these cases).


    [13 lines not shown]
DeltaFile
+288-280llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+42-51llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+24-12llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+12-0llvm/docs/AMDGPUUsage.rst
+7-0llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
+2-0llvm/docs/AMDGPUMemoryModel.md
+375-3436 files

LLVM/project f78208bllvm/test/CodeGen/AMDGPU noclobber-barrier.ll

[AMDGPU] Add and generalize noclobber tests

Some noclobber tests included barrier-and-fence constructs that are unrelated
to what the tests are supposed to check. So far, that hasn't been an issue
because barriers and fences were ignored when inferring noclobber annotations.
However, fences do need to be considered for noclobber annotations (since they
can make clobbering stores from other threads visible in the considered
thread). This PR removes those unrelated barriers and fences so that the tests
will still be meaningful once a subsequent PR fixes the noclobber inference.
For the same reason, some `seq_cst` memory orderings in the tests are relaxed
to `monotonic`: `seq_cst` includes acquire semantics which can bring in
clobbering stores from other threads.

The PR also adds tests to cover more cases in the amdgpu.noclobber inference.
Some of them highlight more problematic cases in the current implementation
that subsequent PRs should fix.

The PR further regenerates all opt check lines via `update_test_checks.py`, so
that it's easier to keep them up to date.

    [2 lines not shown]
DeltaFile
+675-187llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+675-1871 files

LLVM/project 7622da6llvm/lib/Target/Hexagon HexagonXQFloatGenerator.cpp

Hexagon: Use use_instructions in checkHVXUses32/checkHVXUses16

The loops only inspect the using instruction, so iterate instructions
directly instead of operands and their parents.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+4-6llvm/lib/Target/Hexagon/HexagonXQFloatGenerator.cpp
+4-61 files

LLVM/project edbf358flang/docs ReleaseNotes.md, flang/lib/Optimizer/Passes Pipelines.cpp

[flang] Enable FIR loop invariant code motion by default (#218703)

The FIR loop invariant code motion pass was added in #173438, where it
was disabled by default. This enables it for optimization levels above
`-O0`. The option `-disable-fir-licm` has been added in place of
`-enable-fir-licm`. The pass itself is unchanged.

Relates to #208086 and fixes #110613. Tests updated.

Assisted-by: Copilot
DeltaFile
+5-0flang/docs/ReleaseNotes.md
+1-2flang/test/Driver/tco-test-gen.fir
+3-0flang/test/Fir/basic-program.fir
+3-0flang/test/Driver/mlir-pass-pipeline.f90
+3-0flang/test/Driver/bbc-mlir-pass-pipeline.f90
+1-1flang/lib/Optimizer/Passes/Pipelines.cpp
+16-32 files not shown
+18-58 files

LLVM/project d746736llvm/lib/Target/AMDGPU AMDGPU.td, llvm/lib/TargetParser AMDGPUTargetParser.cpp

AMDGPU: Add visible features for aperture regs, doorbell ID and AGPR alloc

These fields are needed to migrate AMDGPUAttributor to using TargetParser
information instead of subtarget features.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+21-6llvm/lib/Target/AMDGPU/AMDGPU.td
+4-3llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+25-92 files

LLVM/project eb6b7bdllvm/lib/Target/RISCV/GISel RISCVInstructionSelector.cpp

RISCV: Pass instruction and operand index to replacePtrWithInt (#219958)

The helper used the operand's parent instruction as the insertion point.
Pass the containing instruction and operand index directly so it no
longer depends on MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+9-9llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+9-91 files

LLVM/project 2fd412ellvm/lib/Target/AMDGPU AMDGPUGlobalISelUtils.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel llvm.amdgcn.raw.ptr.buffer.offset-split.ll

[AMDGPU][GIsel] Make getBaseWithConstantantOffset see `or disjoint` (#219551)

This change is split from #207821, where it was made in the process of
implementing that change to make getBaseWithConstantOffset() have the
same behavior as the SelectionDAG version.

AI disclosure: I'm pretty sure this was Codex code, and I do recall it
being an AI-found discrepancy.
DeltaFile
+5-5llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
+4-3llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+9-82 files

LLVM/project 702e97aclang/lib/AST/ByteCode ByteCodeEmitter.cpp

[clang][bytecode][NFC] Remove an unreachable parameter check (#219977)

We check this both in Context and in ByteCodeEmitter. The latter is not
reachable since the former will already not create Function instances
for such functions.
DeltaFile
+0-5clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
+0-51 files