LLVM/project b556e41llvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor nofpclass-ldexp.ll

ValueTracking: Use computeKnownBits for ldexp integer handling (#179234)

Switch to using computeKnownBits instead of computeConstantRange
in computeKnownFPClass's ldexp handling. This is preparation to
move the handling into KnownFPClass. Since KnownFPClass is in Support,
it can make use of KnownBits as the input argument. ConstantRange is in
IR, so it cannot be used from Support.
DeltaFile
+5-7llvm/lib/Analysis/ValueTracking.cpp
+2-2llvm/test/Transforms/Attributor/nofpclass-ldexp.ll
+7-92 files

LLVM/project c4b531cllvm/include/llvm/IR SymbolTableListTraits.h

Fix grammar in comments (#179269)

Path 
llvm-project -> llvm -> include -> llvm -> IR -> SymbolTableListTraits

Changed:-
all uses it  -> all its uses
DeltaFile
+1-1llvm/include/llvm/IR/SymbolTableListTraits.h
+1-11 files

LLVM/project 628972allvm/include/llvm/CodeGen/GlobalISel CallLowering.h, llvm/lib/CodeGen/GlobalISel CallLowering.cpp

[NFC][GlobalISel] Expose `CallLowering::buildCopyFromRegs` and `CallLowering::buildCopyToRegs` (#179185)

Makes `CallLowering::buildCopyFromRegs` and
`CallLowering::buildCopyToRegs` public so targets not making use of
`ValueHandler` don't have to duplicate this functionality.

For future use in the WASM GlobalISel backend.
DeltaFile
+7-15llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+21-0llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
+28-152 files

LLVM/project 7889f72llvm/lib/Transforms/Scalar LoopUnrollPass.cpp, llvm/test/Transforms/LoopUnroll peel-loop-phi-analysis-iv.ll

[LoopUnroll] Remove preceding whitespace in loop peeling optimization remark (#178951)

DeltaFile
+5-5llvm/test/Transforms/LoopUnroll/peel-loop-phi-analysis-iv.ll
+1-1llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+6-62 files

LLVM/project 1bcff55llvm/test/Analysis/CostModel/X86 clmul.ll

[CostModel][X86] clmul.ll - add i16 and 128/256/512-bit vector cost tests (#179283)

DeltaFile
+79-1llvm/test/Analysis/CostModel/X86/clmul.ll
+79-11 files

LLVM/project 65d6b1fllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-rounding-intrinsics.ll simplify-demanded-fpclass-fma.ll

InstCombine: Fix SimplifyDemandedFPClass bug with known-snan sources

If the result can be a qnan, the source can be a signaling nan.
DeltaFile
+21-5llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+14-7llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
+10-5llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll
+6-3llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll
+4-2llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
+4-2llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
+59-248 files not shown
+76-3314 files

LLVM/project 48e64a7llvm/test/Transforms/InstCombine simplify-demanded-fpclass-rounding-intrinsics.ll simplify-demanded-fpclass-fma.ll

InstCombine: Add baseline tests for broken snan handling (#179243)

SimplifyDemandedFPClass doesn't correctly account for possible
quieting in all cases.
DeltaFile
+93-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
+65-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll
+43-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fadd.ll
+40-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll
+29-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
+29-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
+299-414 files not shown
+582-520 files

LLVM/project a9a5ebbclang/include/clang/CIR MissingFeatures.h, clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR] Upstream support for array new with empty initializer list (#178806)

This adds CIR support for array new with an empty initializer list for
zero-initializable types.

This is part of https://github.com/llvm/llvm-project/issues/160383
DeltaFile
+111-3clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
+43-23clang/test/CIR/CodeGen/new.cpp
+33-0clang/include/clang/CIR/Dialect/IR/CIROps.td
+9-0clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+6-0clang/lib/CIR/CodeGen/CIRGenBuilder.h
+1-0clang/include/clang/CIR/MissingFeatures.h
+203-266 files

LLVM/project 4acd581llvm/lib/Transforms/Coroutines CoroCleanup.cpp, llvm/test/Transforms/Coroutines coro-cleanup-noop-elide.ll coro-cleanup-noop-erase.ll

Revert "[CoroCleanup] Noop coroutine elision for load-and-call pattern" (#179289)

There is a CI fail. Reverts llvm/llvm-project#179154
DeltaFile
+24-64llvm/lib/Transforms/Coroutines/CoroCleanup.cpp
+0-51llvm/test/Transforms/Coroutines/coro-cleanup-noop-elide.ll
+24-0llvm/test/Transforms/Coroutines/coro-cleanup-noop-erase.ll
+48-1153 files

LLVM/project 5d5b4aallvm/include/llvm/CodeGen SelectionDAGNodes.h, llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

[SelectionDAG][NFC] Rename isConstantSequence to isArithmeticSequence (#179108)

The previous name was misleading: the method checks for an arithmetic
progression `(start, start+stride, start+2*stride, ...)`, not just any
constant sequence. The new name uses precise mathematical terminology.

https://github.com/llvm/llvm-project/pull/176671#discussion_r2735571479
DeltaFile
+2-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+1-1llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+1-1llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+1-1llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
+5-54 files

LLVM/project cf9ed46clang Maintainers.rst

Update ObjC and Itanium maintainership (#177950)

John is stepping down from both of these roles as well. We do not have a
replacement for Itanium ABI at this time, but this PR leaves the section
in the maintainers file so it's clear we need to fill it.

Akira Hatanaka has graciously agreed to step up for Objective-C, thank
you!
DeltaFile
+3-5clang/Maintainers.rst
+3-51 files

LLVM/project e0e65f2mlir/include/mlir/Target/LLVM/ROCDL Utils.h, mlir/lib/Target/LLVM/ROCDL Target.cpp

[mlir][ROCDL] do not hardcode partial lld path in utilities (#179201)

`ROCDL::linkObjectCode` was unconditionally appending llvm/bin/ld.lld to
the path it is been passed to to look for lld, which isn't desirable for
a utility function and makes it unusable with, e.g., system lld or one
from the LLVM's own build directory. Move this logic to the caller and
let the utility take a full path.
DeltaFile
+4-4mlir/lib/Target/LLVM/ROCDL/Target.cpp
+1-1mlir/include/mlir/Target/LLVM/ROCDL/Utils.h
+5-52 files

LLVM/project f3df4b9mlir/lib/Rewrite ByteCode.cpp, mlir/test/Rewrite pdl-bytecode.mlir

[mlir][PDL] Support running `pdl_interp.foreach` on ranges of values and types (#173161)

The foreach execution only works for operation ranges, typically
stemming from pdl_interp.get_users.
Custom rewrites/constraints can return ranges of types and values as
well, however.
This pr adds support for executing `pdl_interp.foreach` in those cases.
DeltaFile
+86-0mlir/test/Rewrite/pdl-bytecode.mlir
+30-0mlir/lib/Rewrite/ByteCode.cpp
+15-0mlir/test/lib/Rewrite/TestPDLByteCode.cpp
+131-03 files

LLVM/project 2d1110allvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fpext.ll unmerge-sgpr-s16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES (#171653)

Move G_UNMERGE_VALUES handling to AMDGPURegBankLegalizeRules.cpp.
Fix sgpr S16 unmerge by lowering using shift and using S32.
Previously sgpr S16 unmerge was selected using _lo16 and _hi16 subreg
indexes which are exclusive to vgpr register classes.
For remaing cases we do trivial mapping, assigns same reg bank
to all operands, vgpr or sgpr.
DeltaFile
+47-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+13-27llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
+36-0llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
+24-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+14-9llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+14-9llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+148-452 files not shown
+156-498 files

LLVM/project 96c45c0llvm/lib/IR Intrinsics.cpp, llvm/utils/TableGen/Basic IntrinsicEmitter.cpp

[LLVM][Intrinsics] Allow IIT fixed encoding table to be 32-bit (#178531)

Change Intrinsics.cpp to rely on the type `FixedEncodingTy` emitted by
the intrinsic emitter in `getIntrinsicInfoTableEntries` to process the
intrinsic type table. This enables downstream targets that need a 32-bit
fixed encoding table to just change the value of `Use16BitFixedEncoding`
in the intrinsic emitter to enable 32-bit fixed encoding table.
DeltaFile
+13-6llvm/lib/IR/Intrinsics.cpp
+6-5llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+19-112 files

LLVM/project 36fea45clang/include/clang/CIR/Dialect/IR CIROps.td, clang/lib/CIR/Dialect/IR CIRDialect.cpp

[CIR] Create cir.cleanup.scope operation (#178085)

This adds the CIR dialect definitions for the cir.cleanup.scope
operation. Nothing is being added yet to generate this operation. That
will be done in a later change.
DeltaFile
+116-0clang/test/CIR/IR/cleanup-scope.cir
+109-2clang/include/clang/CIR/Dialect/IR/CIROps.td
+43-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+268-23 files

LLVM/project aa54288libcxx/include any, libcxx/test/std/utilities/any/any.class/any.cons value.pass.cpp

[libc++] Short-cut constraints of single-argument `any` constructor (#177082)

When a default template argument of a function template uses
`std::is_copy_constructible<T>::value` and `T` is convertible from and
to `any`, the changes in 21dc73f6a46cd786394f10f5aef46ec4a2d26175 would
introduce constraint meta-recursion when compiling with Clang.

This patch short-cuts constraints of the related constructor to avoid
computing `is_copy_constructible<T>` when `decay_t<T>` is `any`, which
gets rid of constraint meta-recursion in the overload resolution of copy
construction of `T`.

Fixes #176877.
DeltaFile
+21-1libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp
+7-4libcxx/include/any
+28-52 files

LLVM/project 98e83adclang/lib/Sema SemaCoroutine.cpp, clang/test/CodeGenCoroutines coro-await-elidable.cpp

[Clang] Fix coro_await_elidable breaking with parenthesized expressions (#178495)

The `applySafeElideContext` function used `IgnoreImplicit()` to find the
underlying CallExpr, but this didn't strip `ParenExpr` nodes. When code
like `co_await (fn(leaf()))` was parsed, the operand was wrapped in a
`ParenExpr`, causing safe elide attribution to fail in Clang stage.

This fix chains `IgnoreImplicit()->IgnoreParens()->IgnoreImplicit()` to
handle both orderings of implicit nodes and parentheses in the AST.

Fixes https://github.com/llvm/llvm-project/issues/178256. Except that
`IgnoreParen()` should be a better suggestion than
`IgnoreParenImpCast()`.
DeltaFile
+50-0clang/test/CodeGenCoroutines/coro-await-elidable.cpp
+6-1clang/lib/Sema/SemaCoroutine.cpp
+56-12 files

LLVM/project 94d4f3cclang/include/clang/Basic TargetInfo.h, clang/lib/AST ASTContext.cpp

convert to exec-charset inside getPredefinedStringLiteralFromCache, test __builtin_FILE()
DeltaFile
+28-0clang/test/CodeGen/systemz-charset.cpp
+10-0clang/lib/AST/ASTContext.cpp
+3-0clang/lib/Basic/TargetInfo.cpp
+2-0clang/include/clang/Basic/TargetInfo.h
+1-0clang/lib/Lex/TextEncodingConfig.cpp
+44-05 files

LLVM/project 395858dllvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2 exec_mode3.ll

Revert "[SPIRV] Emit intrinsics for globals only in function that references them (#178143 (#179268)

This reverts commit 1daef5927ff0e43b92d615380a8d60f213cc5e52.

From the ASAN buildbot:

```bash
FAIL: LLVM :: CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll (46596 of 94488)
******************** TEST 'LLVM :: CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm_build_asan/bin/llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll -o - --spirv-ext=+SPV_INTEL_function_pointers | /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm_build_asan/bin/FileCheck /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll
# executed command: /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm_build_asan/bin/llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll -o - --spirv-ext=+SPV_INTEL_function_pointers
# note: command had no output on stdout or stderr
# error: command failed with exit status: 1
# executed command: /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm_build_asan/bin/FileCheck /home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll

    [9 lines not shown]
DeltaFile
+4-116llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+38-48llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
+30-46llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll
+15-15llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_faddfsub_vec_float16.ll
+15-15llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_fminfmax_vec_float16.ll
+102-2405 files

LLVM/project 39413afcompiler-rt/lib/builtins CMakeLists.txt, compiler-rt/lib/builtins/arm aeabi_uread8.S aeabi_uread4.S

[Compiler-rt] Implement AEABI Unaligned Read/Write Helpers in compiler-rt (#167913)

This patch adds implementations for the __aeabi_uread and __aeabi_uwrite
helper functions to compiler-rt.

Without these helpers, LLVM would need to inline byte wise sequences ,
which can increases code size, especially at -Os/-Oz. Using the helper
functions allows to retain correctness while avoiding the code-size
growth.

GCC-based toolchains already provide these AEABI helpers, so supporting
them in compiler-rt ensures parity and avoids accidental dependencies on
libgcc when LLVM begins emitting these calls.
DeltaFile
+100-0compiler-rt/lib/builtins/arm/aeabi_uread8.S
+86-0compiler-rt/test/builtins/Unit/arm/aeabi_unaligned_access_test.c
+63-0compiler-rt/lib/builtins/arm/aeabi_uread4.S
+51-0compiler-rt/lib/builtins/arm/aeabi_uwrite8.S
+35-0compiler-rt/lib/builtins/arm/aeabi_uwrite4.S
+4-0compiler-rt/lib/builtins/CMakeLists.txt
+339-06 files

LLVM/project 09a6842llvm/include/llvm/IR RuntimeLibcalls.td, llvm/lib/Target/ARM ARMISelLowering.cpp ARMISelLowering.h

[ARM] Lower unaligned loads/stores to aeabi functions. (#172672)

When targeting architectures that do not support unaligned memory
accesses or when explictly pass -mno-unaligned-access, it requires the
compiler to expand each unaligned load/store into an inline sequences.
For 32-bit operations this typically involves:

        1. 4× LDRB (or 2× LDRH),
        2. multiple shift/or instructions

These sequences are emitted at every unaligned access site, and
therefore contribute significant code size in workloads that touch
packed or misaligned structures.

When compiling with -Oz and in combination with -mno-unaligned-access,
this patch lowers unaligned 32 bit and 64 bit loads and stores to below
AEABI heper calls:
```
         __aeabi_uread4

    [21 lines not shown]
DeltaFile
+728-0llvm/test/CodeGen/ARM/unaligned_load_store_aeabi.ll
+139-7llvm/lib/Target/ARM/ARMISelLowering.cpp
+59-63llvm/test/CodeGen/ARM/i64_volatile_load_store.ll
+21-0llvm/include/llvm/IR/RuntimeLibcalls.td
+5-1llvm/lib/Target/ARM/ARMISelLowering.h
+952-715 files

LLVM/project 84ba547clang Maintainers.rst

Move John Ericson to the inactive maintainers list (#179264)

While reaching out to folks for a maintainers list refresh, John asked
to step down due to other commitments. Thank you for all your help!
DeltaFile
+1-3clang/Maintainers.rst
+1-31 files

LLVM/project 5b80848clang/lib/AST/ByteCode InterpBuiltin.cpp, clang/test/SemaCXX alloc-token.cpp

[clang][bytecode] Fix crash on __builtin_infer_alloc_token with struct argument (#178936)

## Summary
- Fix crash when passing non primitive types (structs) to
`__builtin_infer_alloc_token`
- The bytecode interpreter's discard loop dereferenced an empty
`OptPrimType` for non primitive arguments

## Test plan
- Added regression test in `clang/test/SemaCXX/alloc-token.cpp`
- Existing tests continue to pass

Fixes #178892
DeltaFile
+5-0clang/test/SemaCXX/alloc-token.cpp
+1-1clang/lib/AST/ByteCode/InterpBuiltin.cpp
+6-12 files

LLVM/project fa675aallvm/test/Transforms/LoopUnroll unroll-multi-exit-loop-heuristics.ll

[NFC][LoopUnroll] Add `-unroll-runtime-other-exit-predictable=false` to `unroll-multi-exit-loop-heuristics.ll` (#179198)

Adds `-unroll-runtime-other-exit-predictable=false` option to
`unroll-multi-exit-loop-heuristics.ll` test for stability reasons.

This is a followup to a discussion in #164799 and a similar patch
https://reviews.llvm.org/D98098. Since this option is false by default,
this is an NFC.
DeltaFile
+2-2llvm/test/Transforms/LoopUnroll/unroll-multi-exit-loop-heuristics.ll
+2-21 files

LLVM/project dc8d35allvm/utils/TableGen CompressInstEmitter.cpp

[NFC][TableGen] Adopt `IfDefEmitter` in `CompressInstEmitter` (#178998)

DeltaFile
+14-22llvm/utils/TableGen/CompressInstEmitter.cpp
+14-221 files

LLVM/project e8cbfbdllvm/lib/Target/SPIRV SPIRVEmitIntrinsics.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2 exec_mode3.ll

Revert "[SPIRV] Emit intrinsics for globals only in function that references them (#178143)"

This reverts commit 1daef5927ff0e43b92d615380a8d60f213cc5e52.
DeltaFile
+4-116llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+38-48llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
+30-46llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll
+15-15llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_fminfmax_vec_float16.ll
+15-15llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_faddfsub_vec_float16.ll
+102-2405 files

LLVM/project a81625cflang/lib/Semantics resolve-names.cpp

Remove leftover unrelated change
DeltaFile
+4-0flang/lib/Semantics/resolve-names.cpp
+4-01 files

LLVM/project 8987ab4llvm/test/CodeGen/AMDGPU strict_fsub.f16.ll strict_ldexp.f32.ll, llvm/test/CodeGen/PowerPC fp-strict.ll

[DAG] Change default expansion of strictfp vector operations

The previous default implementation unrolled strictfp vector operation,
producing its scalar version. This behavior can result in low
performance in some cases.  A better behavior is to convert strictfp
nodes into default-mode operations. This method has already been used to
support strictfp nodes on targets with limited support of strictfp
operations.

Many targets already implement lowering of strictfp and default-mode
nodes identically. Small number of deviations from this rule is fixed in
this change. Identical treatment of strictfp and default mode nodes is
natural because both represent the same operation in the resulting code,
the only difference is additional restrictions that compiler should
apply when it handles strictfp nodes.

Unrolling vector operations can also violate user expectations. In
strictfp mode, vector operations cannot be created by auto-vectorization
because of the side effect of constrained functions, so the vector

    [3 lines not shown]
DeltaFile
+169-521llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
+99-331llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
+156-156llvm/test/CodeGen/X86/avx512fp16-frem.ll
+69-144llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
+9-182llvm/test/CodeGen/PowerPC/fp-strict.ll
+9-168llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll
+511-1,50211 files not shown
+695-2,02817 files

LLVM/project 20dc8eallvm/lib/Target/AArch64 AArch64SystemOperands.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Remove `+xs` gating for `tlbip *nxs` instructions

A recent spec update has removed FEAT_XS gating for `tlbip *nxs`
instructions. It remains gated on FEAT_XS for `tlbi *nxs` instructions.
DeltaFile
+6-16llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+8-9llvm/test/MC/AArch64/armv9a-sysp.s
+0-8llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+2-2llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s
+1-2llvm/lib/Target/AArch64/AArch64SystemOperands.td
+17-375 files