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Fix formatting.

Add back isInSection()

Also add isInEDSection() as simple check.

[NFC][Offload] Fix minor debug print issues introduced in #170425. (#172377)

[libclang/python] Fix cindex test for cpp lang (#172368)

Fix typo in cindex.py where the C++ support test was incorrectly named
test_c instead of test_cpp

[FastISel] Don't select a CallInst as a BasicBlock in the SelectionDAG fallback if it has bundled ops (#162895)

This was discovered while looking at the codegen for x64 when Control
Flow Guard is enabled.

When using `SelectionDAG`, LLVM would generate the following sequence
for a CF guarded indirect call:
```
        leaq    target_func(%rip), %rax
        rex64 jmpq      *__guard_dispatch_icall_fptr(%rip) # TAILCALL
```

However, when Fast ISel was used the following is generated:
```
        leaq    target_func(%rip), %rax
        movq    __guard_dispatch_icall_fptr(%rip), %rcx
        rex64 jmpq      *%rcx                   # TAILCALL
```


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yay

Created using spr 1.3.7

experiment

Created using spr 1.3.7

rebase

Created using spr 1.3.7

change

Created using spr 1.3.7

[VPlan] Create header phis once, after constructing VPlan0 (NFC). (#168291)

Together with https://github.com/llvm/llvm-project/pull/168289 &
https://github.com/llvm/llvm-project/pull/166099 we can construct header
phis once up front, after creating VPlan0, as the
induction/reduction/first-order-recurrence classification applies across
all VFs.

Depends on https://github.com/llvm/llvm-project/pull/168289 &
https://github.com/llvm/llvm-project/pull/166099 

PR: https://github.com/llvm/llvm-project/pull/168291

[gn build] Port fa79e0a4001a

[gn build] Port 908a5a8292ea

[gn build] Port 1e15dbe311eb

[flang][runtime] Fix GPU output for multiple statements (#172363)

I recently broke PRINT statements in GPU device code when multiple
PRINTs occur in the same kernel by trying to preserve the allocated
pseudo-unit. This turned out to be a bad idea overall, and I'm reverting
to the original protocol that minimizes allocated memory.

[VPlan] Set VF scale factor in tryToCreatePartialReduction (NFCI).

Split off unrelated change from approved
https://github.com/llvm/llvm-project/pull/168291/ to land separately as
suggested.

Remove `const` from local variable

format

Use `SmallVector` interface

addressed PR171942 review comments

[llvm] Replace `OwningArrayRef` with `SmallVector` in `BTFParser`

`OwningArrayRef` requires that the size and the capacity are the same. This prevents reusing memory allocations unless the size happens to be exactly the same (which is rare enough we don't even try). Switch to `SmallVector` instead so that we're not repeatedly calling `new[]` and `delete[]`.

[gn] port c81d44942e56

Update llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>

[MemProf] Add CalleeGUIDs from profile to existing VP metadata (#171495)

Previously, we only synthesized VP metadata with the callee GUIDs from
the memprof profile if no VP metadata already existed (i.e. from PGO).
With this change we will add in any that are not already in the VP
metadata, also with count 1.

[clang-tidy] add abseil-unchecked-statusor-access



Pull Request: https://github.com/llvm/llvm-project/pull/171188

[mlir][tosa] Allow dynamic dims in `--tosa-validate` pass (#171463)

This commit allows tensor dimensions to be dynamic when the specified
target TOSA specification version is `1.1.draft` or higher. This is
because this version of the specification supports representation
operations that are dynamic until backend compile time.

[NFC][HIP] Disable device-side kernel launches for HIP (#171043)

#165519 added support for launching kernels from the device side. This is only available in CUDA at the moment. We have to explicitly check whether we are compiling for HIP to guard against this path being exercised, since the CUDA and HIP languages rely on the same `CUDAIsDevice` bit to check for device side compilation, and it is not possible to disambiguate otherwise.

InstCombine: Replace some isa<FPMathOperator> with dyn_cast (#172356)

This isa and get flag pattern is essentially an abstracted
isa and dyn_cast, so make this more direct.

addressed PR171942 review comments

[clang][NFC] In `CFGStmtMap`, remove mutable `getBlock` overload.

The mutable version of the overload is not used. The way we implemented code sharing in the const vs. mutable overloads had a const-correctness violation, anyway.

Rebase, address comments

Created using spr 1.3.7