[RISCV][NewPM] Finish pipeline
This finishes the wire-up in CodeGenPassBuilder to match the current
TargetPassConfig, minus GISel.
Reviewers: lenary, topperc, wangpc-pp
Pull Request: https://github.com/llvm/llvm-project/pull/235807
[llubi] Add support for llvm.mask.beforefirst
This has the same LangRef behaviour where any poison lane makes the result poison, even after the first active lane.
Assisted-by: Opus 5.5
[X86] Move CodeGenPassBuilder callbacks into the correct order
I've been trying to put the hooks in the order they actually get called.
This patch actually makes that so.
Reviewers: arsenm, aengelke, topperc, RKSimon, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/235626
[VPlan] Vectorize early exit loops with side effects in the vector loop
Rename UncountableExitStyle::ReadOnly to MaskedHandleExitInVectorLoop and
use it for early exit loops with stores, when every store comes after all
the early exits. Each early exiting block branches to the latch on the
lanes from the first exiting one on, so the stores after it are masked off
for them, and values from the skipped blocks are poison on those edges.
Loops fall back to MaskedHandleExitInScalarLoop if a store is in the latch,
a store isn't properly dominated by every early exiting block, the latch's
exit condition uses a value from a block the exits can skip, or a load
might fault.
[VPlan] Keep early exit conditions and values in SSA
The exit conditions were MaskedConds in each exiting block, used directly
in the latch, and the exit values were extracted from the exiting blocks
in the vector early exit blocks. Neither is valid SSA when the exiting
block doesn't dominate the latch, so the verifier had to make exceptions
for MaskedCond.
Instead, carry them to the latch with reconstructSSA. An exit's condition
is false on any path that didn't go through its exiting block, which also
masks it, so it no longer needs a MaskedCond. An exit's value is poison on
those paths, since only the lanes that took the exit read it.
The lanes after the first one that exits run iterations that the scalar
loop never does, and keep going past their exits, so freeze the
conditions of the branches in the loop body so they never branch on
poison. This also keeps the phis carrying the exit conditions well
defined for those lanes.
Remove the MaskedCond exceptions from the verifier.
[VPlan] Skip poison incoming values computeBlendEdges
A poison value can be replaced with anything, so we don't need to create an incoming value for it when converting phis to blends.
Needed to avoid regressions in an upcoming PR to keep SSA with early exits.
[VPlan] Simplify BLEND X/M, false, ..., false -> M && X
If an i1 blend has false for all but one incoming value, then we can simplify this to the one non-false value. Blends by construction never have any overlapping mask values, so we don't need to worry about the order as the masks can't "shortcut" each other.
[RISCV][P-ext] Add isel pattern for macc.w01/macc.w11 (#237064)
`macc.w01` multiplies the sign-extended lower word of rs1 by the
sign-extended upper word of rs2 and adds the product to rd. `macc.w11`
does the same with the sign-extended upper words of both. Both are
RV64 only.
Previously, (sra X, 32) was selected as a separate srai feeding
`macc.w00`. Match it directly so the shift is folded. As with
`macc.w00`, the patterns require the multiply to have a single use.
[libc] Fix race condition in wait_status_test (#237029)
In `stopped_and_continued()`, after the parent sends `SIGCONT`, the
child can wake up and call `exit(0)` before the parent calls
`waitpid(pid, &status, WCONTINUED)`. Because `waitpid` always implies
`WEXITED`, the kernel reaps the exited zombie first and returns `0`
(`WIFEXITED`) instead of `0xffff` (`WIFCONTINUED`), making the test
flaky under load.
Block the child on a pipe after `raise(SIGSTOP)` until the parent has
observed `WIFCONTINUED(status)` and closed the write end. Also switch
the test from public `<signal.h>`/`<sys/wait.h>` headers to internal and
proxy headers.
Assisted-by: Gemini
[clang-tidy][NFC] Move isStatic matcher into utils::Matchers (#228546)
AI Usage: Assisted by Grok 4.6 (Cursor)
Co-authored-by: Cursor <cursoragent at cursor.com>
[clang-tidy][NFC] Move isOverloadedOperator matcher into utils::Matchers (#228548)
AI Usage: Assisted by Grok 4.6 (Cursor)
Co-authored-by: Cursor <cursoragent at cursor.com>
SelectionDAG: Mark inline asm clobbers dead when an output covers the read (#233202)
An inline asm clobber was only marked dead if no glued CopyFromReg
read an overlapping register. A read of an output register that
overlaps a wider clobber kept the whole clobber live, even though the
output def already provides the read value. For example,
"={a1},~{a[0:15]}" left the $agpr0_..._agpr15 clobber live.
Ignore glued reads fully covered by an output def of the asm,
producing the same flags LiveVariables would later add, with a live
def of the output and a dead def of the clobber.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
