LLVM/project d2bbdf9 — llvm/lib/CodeGen TargetPassConfig.cpp, llvm/lib/Passes CodeGenPassBuilder.cpp

CodeGen: Read the exception model from the module flag

Module::getExceptionModel() now falls back to the triple's default
model instead of falling back to the TargetMachine.

The pass pipeline is built before the module is known, so schedule each
EH preparation pass when the target supports a model, and let the pass
check the module's model. Add TargetMachine::supportsExceptionModel so
the pass config can skip definitely irrelevant passes. SjLjEHPrepare is
now scheduled on every target with exception handling, and WinEHPrepare
only on COFF and Wasm targets. WinEHPrepare and WasmEHPrepare are
scheduled for Wasm by the base pass configs, replacing the WebAssembly
override.

This is almost the last step towards removing TargetOptions::ExceptionModel.

Co-authored-by: Claude Opus <noreply at anthropic.com>
DeltaFile
+38-35llvm/lib/CodeGen/TargetPassConfig.cpp
+35-34llvm/lib/Passes/CodeGenPassBuilder.cpp
+69-0llvm/test/CodeGen/X86/exception-model-flag-eh-prepare.ll
+64-0llvm/test/CodeGen/X86/exception-model.ll
+31-0llvm/lib/Target/TargetMachine.cpp
+25-0llvm/test/CodeGen/AMDGPU/exception-model.ll
+262-6940 files not shown
+362-15046 files

LLVM/project ce01597 — llvm/test/CodeGen/AArch64 windows-trap-unreachable.ll

Avoidable check prefix
DeltaFile
+2-3llvm/test/CodeGen/AArch64/windows-trap-unreachable.ll
+2-31 files

LLVM/project 962d0a7 — clang/test/CIR/CodeGen sve-vector-arith-ops.c, llvm/lib/Frontend/OpenMP OMPDescriptors.inc

Merge branch 'main' into users/mamini/libcxx-ci-cmake-bootstrap
DeltaFile
+0-1,299mlir/test/Dialect/LLVMIR/mem2reg.mlir
+1,299-0mlir/test/Transforms/Mem2Reg/llvm.mlir
+0-1,120mlir/test/Dialect/SCF/mem2reg.mlir
+1,120-0mlir/test/Transforms/Mem2Reg/scf.mlir
+1,110-1llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
+983-0clang/test/CIR/CodeGen/sve-vector-arith-ops.c
+4,512-2,420550 files not shown
+25,300-12,009556 files

LLVM/project c7ddcfa — lldb/source/Plugins/Process/Utility RegisterInfoPOSIX_loongarch64.cpp RegisterInfo_loongarch64.cpp

[lldb] Rename common register metadata providers (#232566)

These files are not specific to POSIX. For example, Windows plugins use
these as RegisterInfoInterface while Darwin does not make use of these
even though it is a POSIX-compliant OS.
DeltaFile
+0-681lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+681-0lldb/source/Plugins/Process/Utility/RegisterInfo_arm64.cpp
+0-226lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+226-0lldb/source/Plugins/Process/Utility/RegisterInfo_arm64.h
+0-215lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp
+215-0lldb/source/Plugins/Process/Utility/RegisterInfo_loongarch64.cpp
+1,122-1,12279 files not shown
+2,617-2,61785 files

LLVM/project e5b1dbc — llvm/test/CodeGen/WinEH wineh-empty-seh-scope.ll

Update wineh-empty-seh-scope.ll for the Windows trap change

An unreachable that does not follow a call no longer traps, so the empty
function gets the generic zero-length function nop, as on X86.
DeltaFile
+1-1llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
+1-11 files

LLVM/project d6465a4 — llvm/lib/Target/AArch64 AArch64TargetMachine.cpp AArch64AsmPrinter.cpp, llvm/test/CodeGen/AArch64 windows-trap-unreachable.ll

AArch64: Move the Windows trap after noreturn calls into the AsmPrinter

With Windows unwind info, the unwinder finds the function or funclet
for a frame from its return address, so a call must not be the last
instruction of one.

This was hackily handled by overwriting TrapUnreachable in the
TargetMachine constructor which inserts traps after every
unreachable. X86 handles the same problem by padding calls in the
AsmPrinter, so do the same here: emit a trap only after a noreturn
call that would end a function or funclet. This addresses the FIXME
about eliding the trap when the next instruction is in the same
region, so noreturn calls in the middle of a function no longer get a
trap.

This removes one of the last obstacles to removing ExceptionModel from
TargetOptions.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+86-13llvm/test/CodeGen/AArch64/windows-trap-unreachable.ll
+24-0llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+0-11llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+110-243 files

LLVM/project 3fb6c48 — utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Port c12cfa7f0fc867191c2e867f85df04a49f561007 (#232962)
DeltaFile
+1-1utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-11 files

LLVM/project da3be94 — utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Port 3f38810694ad36f3aa8282b412f580f07fdd0d2f (#232961)
DeltaFile
+15-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+15-01 files

LLVM/project 253634e — compiler-rt/lib/scudo/standalone/tests quarantine_test.cpp

[scudo] Avoid QuarantineBatch leak in GlobalQuarantineRecycleInvalidCount (#232905)

In GlobalQuarantineRecycleInvalidCount,
Quarantine.drainAndRecycle(&Cache, Cb)
dequeues B from Cache before hitting the CHECK failure on B->Count. On
platforms where death tests execute in a thread within the same address
space
(such as Fuchsia zxtest), Cache is already empty after
SCUDO_EXPECT_DEATH
returns, so deallocateCache(&Cache) fails to free B and triggers a
LeakSanitizer failure.

Deallocate B directly via Cb.deallocate(B) instead.
DeltaFile
+1-1compiler-rt/lib/scudo/standalone/tests/quarantine_test.cpp
+1-11 files

LLVM/project 4fc7e7a — llvm/lib/Transforms/IPO AttributorAttributes.cpp, llvm/test/Transforms/Attributor invariant-load-indirect-call.ll

Attributor: Don't crash on indirect calls in AAInvariantLoadPointer (#231519)

AAInvariantLoadPointerCallSiteReturned assumed every call has a known
callee, and dereferenced the missing function of an indirect call. This
crashed on most of CTMark with -attributor-enable=full. Nothing is known
about the result of an indirect call, so give up on it.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+16-0llvm/test/Transforms/Attributor/invariant-load-indirect-call.ll
+5-1llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+21-12 files

LLVM/project 709035d — flang/lib/Semantics openmp-utils.cpp, flang/test/Lower/OpenMP metadirective-implementation.f90

[OpenMP][flang] Score unknown context selector properties by selector

Flang records an unknown property such as kind(bogus) or vendor(bogus)
as TraitProperty::invalid, which belongs to no selector. Under
match_any or match_none, where such a variant can still be selected,
the property therefore lost its selector's weight: kind(bogus) added
nothing, while an unmatched kind(gpu) adds 2^l. A score on a selector
that mixes known and unknown properties was also added twice, once for
the known property and once for invalid, and unknown properties in
different selectors shared a single score.

Add VariantMatchInfo::addUnknownTrait, which keeps the property
unmatched and records its selector and score, and score that selector
like any other. Use it in Flang. Clang drops unknown properties while
parsing and is unaffected.

Assisted-by: GitHub Copilot (Claude Opus 5.5)
DeltaFile
+38-1llvm/unittests/Frontend/OpenMPContextTest.cpp
+30-0flang/test/Lower/OpenMP/metadirective-implementation.f90
+15-0llvm/include/llvm/Frontend/OpenMP/OMPContext.h
+6-2llvm/lib/Frontend/OpenMP/OMPContext.cpp
+2-4flang/lib/Semantics/openmp-utils.cpp
+91-75 files

LLVM/project fcc5833 — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

[VPlan] Derive extend kind and types in canFoldOuterExtendIntoMul (NFC) (#232903)

Look up the inner extends from the operands of the mul instead of
passing the extend kind and source types separately. A non-extend RHS is
a constant that fits in the source type of the LHS.

Both callers already require the inner extends to have the same kind as
the outer extend, so using the inner kind does not change behavior.
DeltaFile
+11-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+11-81 files

LLVM/project 81da325 — clang/lib/Driver/ToolChains Clang.cpp CommonArgs.cpp, clang/test/Driver aarch64-uefi-constructed-args.c

[clang][Driver] Use the Windows ARM64 defaults for aarch64-unknown-uefi

Match the Windows ARM64 driver defaults for aarch64-unknown-uefi, which
follows the same ABI:

* char is signed, so do not pass -fno-signed-char,
* the frame chain must stay valid even when frame pointers are omitted,
  so -fomit-frame-pointer yields -mframe-pointer=reserved rather than
  none, as the backend reserves the frame pointer for UEFI as well.

Assisted-by: Claude
DeltaFile
+9-0clang/test/Driver/aarch64-uefi-constructed-args.c
+4-4clang/lib/Driver/ToolChains/CommonArgs.cpp
+1-1clang/lib/Driver/ToolChains/Clang.cpp
+14-53 files

LLVM/project ff28f8e — clang/lib/Basic/Targets AArch64.h AArch64.cpp, clang/lib/Driver Driver.cpp

[clang] Add aarch64-unknown-uefi target

Add the aarch64-unknown-uefi target to clang, building on the backend
support added in the preceding patches. Like x86_64-unknown-uefi it
follows the Microsoft ABI conventions, matching the Windows ARM64 target
which is the only way EFI applications for AArch64 can be built with
Clang/LLVM today:

* add UEFIAArch64TargetInfo: LLP64 types, Microsoft C++ ABI, char*
  based va_list and the Win64 calling convention kind,
* use the Windows AArch64 ABI info in CodeGen for UEFI,
* accept aarch64 for *-uefi triples in the driver.

The UEFI toolchain already handles the linker invocation (lld-link with
/subsystem:efi_application), so no further driver changes are needed.

Assisted-by: Claude
DeltaFile
+50-0clang/lib/Basic/Targets/AArch64.cpp
+43-0clang/test/CodeGen/AArch64/uefi-abi.c
+19-0clang/test/Driver/aarch64-uefi-constructed-args.c
+14-0clang/lib/Basic/Targets/AArch64.h
+0-6clang/test/Driver/unsupported-target-arch.c
+4-2clang/lib/Driver/Driver.cpp
+130-89 files not shown
+147-915 files

LLVM/project 5d14240 — llvm/docs ReleaseNotes.md, llvm/lib/Target/AArch64 AArch64CodeLayoutOpt.cpp AArch64MachineFunctionInfo.cpp

[AArch64] Apply the Windows SEH and CRT codegen constraints to UEFI

aarch64-unknown-uefi uses SEH unwind information and has no C runtime
library, so the remaining Windows specific codegen decisions that follow
from this apply to it too:

* do not align loops or basic blocks, since SEH unwind info generation
  needs the exact function layout before alignment padding is inserted,
* sign return addresses with the B key by default and reject A key
  signing, matching the pac_sign_lr unwind code used by the unwinder,
* do not lower wide shifts to libcalls at -Oz, as those helpers are not
  available.

The corresponding Windows tests gain aarch64-unknown-uefi run lines and
the LLVM release notes announce the new target, which completes the
backend side of aarch64-unknown-uefi support.

Assisted-by: Claude
DeltaFile
+5-5llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-2llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
+4-0llvm/docs/ReleaseNotes.md
+1-1llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
+1-0llvm/test/CodeGen/AArch64/windows-trap.ll
+1-0llvm/test/CodeGen/AArch64/windows-pac-invalid-a-key.ll
+14-81 files not shown
+15-87 files

LLVM/project fcf882c — llvm/lib/CodeGen/GlobalISel IRTranslator.cpp, llvm/lib/Target/AArch64 AArch64FastISel.cpp AArch64ISelLowering.cpp

[AArch64] Classify global references on UEFI like Windows COFF

Apply the Windows COFF rules for global references to
aarch64-unknown-uefi, which produces the same PE/COFF images:

* classify dllimport and non-dso-local globals with MO_DLLIMPORT /
  MO_COFFSTUB, so extern_weak symbols are referenced through a stub that
  can be resolved to zero by the linker,
* keep the existing SelectionDAG, FastISel and GlobalISel handling of
  calls and tail calls to extern_weak functions in sync with that,
* default to the PIC relocation model, so jump tables and other
  references stay position independent in relocatable PE images,
* lower ifuncs on UEFI as COFF has no support for them.

The extern weak and jump table tests gain aarch64-unknown-uefi run lines.

Assisted-by: Claude
DeltaFile
+3-3llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+3-3llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+2-2llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+2-1llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+3-0llvm/test/CodeGen/AArch64/windows-extern-weak.ll
+1-1llvm/lib/Target/AArch64/AArch64FastISel.cpp
+14-102 files not shown
+16-118 files

LLVM/project 6f1531a — llvm/include/llvm/IR RuntimeLibcalls.td, llvm/lib/CodeGen/GlobalISel IRTranslator.cpp

[AArch64] Use Windows style stack probing on UEFI

Like Windows, and like x86_64-unknown-uefi already does, probe large
stack frames and dynamic allocas through the __chkstk helper on
aarch64-unknown-uefi instead of the inline stack probe loop:

* make the __chkstk STACK_PROBE libcall available for AArch64 UEFI,
* select the Windows stack probe paths in frame lowering,
  LowerDYNAMIC_STACKALLOC and the SME state buffer allocation, honouring
  the "no-stack-arg-probe" attribute as on Windows,
* fall back from GlobalISel to SelectionDAG for dynamic allocas, as is
  done for Windows, since the IRTranslator does not implement the probing.

The existing chkstk and alloca tests gain aarch64-unknown-uefi run lines.

Assisted-by: Claude
DeltaFile
+3-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+3-2llvm/include/llvm/IR/RuntimeLibcalls.td
+2-2llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+1-1llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+1-1llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
+2-0llvm/test/CodeGen/AArch64/chkstk.ll
+12-93 files not shown
+15-109 files

LLVM/project 01eecd0 — llvm/lib/TargetParser AArch64TargetParser.cpp, llvm/test/CodeGen/AArch64 arm64-platform-reg.ll

[AArch64] Reserve x18 as the platform register on UEFI

Both the Windows ARM64 ABI, which UEFI follows, and the firmware
ecosystem (EDK2 builds AArch64 with -ffixed-x18) treat x18 as a reserved
platform register. Reserve it by default for aarch64-unknown-uefi, as is
already done for Windows, Darwin, Android, Fuchsia and OHOS.

Assisted-by: Claude
DeltaFile
+1-1llvm/lib/TargetParser/AArch64TargetParser.cpp
+1-0llvm/test/CodeGen/AArch64/arm64-platform-reg.ll
+2-12 files

LLVM/project eb1aed7 — llvm/lib/Target/AArch64 AArch64RegisterInfo.cpp AArch64Subtarget.h, llvm/lib/Target/AArch64/GISel AArch64LegalizerInfo.cpp

[AArch64] Use the Windows ARM64 ABI for UEFI targets

UEFI follows the Windows ARM64 procedure call standard (the UEFI
specification defines AArch64 EFI images in terms of the Microsoft
toolchain, and that is how EDK2 and clang-built firmware are linked
today), and x86_64-unknown-uefi likewise uses the Win64 ABI. Introduce
AArch64Subtarget::isTargetUEFI() and isTargetWindowsOrUEFI() and use the
latter for the core ABI decisions that currently key off
isTargetWindows():

* the Win64 calling convention for C/Fast/Swift calls, including the
  Windows variadic convention which homes all argument registers and
  passes floating point variadic arguments in GPRs,
* the char* based va_list (va_copy size and getVaListSizeInBits),
* the Windows callee saved register list and the matching frame record
  pairing rules in AArch64FrameLowering, which have to agree so that the
  SEH save_regp/save_fplr unwind codes describe consecutive registers,
* the requirement that the frame chain stays valid in every function.


    [11 lines not shown]
DeltaFile
+76-0llvm/test/CodeGen/AArch64/uefi-frame-record-pairing.ll
+7-8llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+8-7llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+9-2llvm/lib/Target/AArch64/AArch64Subtarget.h
+5-4llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+4-3llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+109-244 files not shown
+115-2810 files

LLVM/project ee96fed — llvm/lib/Target/AArch64 AArch64MCInstLower.cpp, llvm/lib/Target/AArch64/MCTargetDesc AArch64MCTargetDesc.cpp

[AArch64] Use the Microsoft COFF MCAsmInfo for UEFI targets

UEFI follows the MSVC toolchain conventions and lld-link is used to
produce the PE/COFF images, so aarch64-unknown-uefi should use the
Microsoft COFF MCAsmInfo like the X86 backend already does for
x86_64-unknown-uefi, rather than the GNU (MinGW) flavour it currently
gets by virtue of being a non-MSVC COFF triple. This enables associative
COMDATs and COMDAT constant pool entries (which AsmPrinter already
expects for UEFI, see GetCPISymbol).

Also relax the AArch64MCInstLower assertion that only Windows COFF
targets exist.

This is the first in a series of patches adding aarch64-unknown-uefi
support to the AArch64 backend and clang.

Assisted-by: Claude
DeltaFile
+2-2llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
+1-1llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
+1-0llvm/test/CodeGen/AArch64/win_cst_pool.ll
+4-33 files

LLVM/project f0dc8ba — llvm/lib/Target/NVPTX NVPTXISelLowering.cpp, llvm/test/CodeGen/NVPTX mul-with-overflow.ll

[CodeGen][NVPTXISelLowering] Fix missing lowering of smul_lohi and umul_lohi (#230234)

NVPTX ISelLowering was missing legalization rules for i16/i32 umul_lohi
and smul_lohi. This would cause codegen failure when the combiner was
disabled as they are not legal in ptx. Adds custom lowering to mul.wide.
Adds a test with combiner disabled.
DeltaFile
+27-0llvm/test/CodeGen/NVPTX/mul-with-overflow.ll
+22-3llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+49-32 files

LLVM/project 5bb07b4 — clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGenBuiltins/X86 avx-builtins-constrained.c avx-builtins.c

[CIR][X86] Add support for roundpd, roundps, roundsd, roundss builtins (#215787)

Issue #167765
DeltaFile
+253-0clang/test/CIR/CodeGenBuiltins/X86/sse41-builtins.c
+124-0clang/test/CIR/CodeGenBuiltins/X86/sse41-builtins-constrained.c
+120-0clang/test/CIR/CodeGenBuiltins/X86/avx-builtins.c
+100-0clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+62-0clang/test/CIR/CodeGenBuiltins/X86/avx-builtins-constrained.c
+659-05 files

LLVM/project 643443a — libcxx/utils/ci run-buildbot

[libc++] Disable automatic module scanning on ARM CI builders

The ARM Buildkite toolchains do not expose clang-scan-deps to CMake.
When CMP0155 enables automatic scanning for libc++abi C++23 sources,
these standalone runtimes builds fail with the scanner set to NOTFOUND.

Pass CMAKE_CXX_SCAN_FOR_MODULES=OFF in the eight ARM job invocations,
including the no-exceptions variants, until their toolchains provide a
matching scanner. Keep the other CI configurations on their defaults.

Validated bash syntax, git diff --check, and argument dispatch for all
eight ARM jobs with generic C++20, C++23, and modules jobs as controls.

Assisted-by: Codex
DeltaFile
+16-6libcxx/utils/ci/run-buildbot
+16-61 files

LLVM/project 3f38810 — mlir/include/mlir/Dialect/DLTI DLTIOpInterfaces.td, mlir/lib/Dialect/DLTI DLTI.cpp

[mlir][DLTI] Introduce an operation interface for scoped DLTI queries (#232733)

So far, DLTI queries have relied on scanning discardable attributes for
values implementing DLTIQueryInterface. This is problematic when that
data is used to determine operation semantics: semantic information
belongs in an operation's inherent attributes/properties, and should
have an explicit contract rather than depend on arbitrary discardable
attribute attachments.

Introduce DLTIQueryOpInterface, an OpInterface instead of the existing
AttributeInterface, with symmetric queryDlti and setDlti methods for
individual keys. Provide default implementations backed by an inherent
dlti attribute. Updates preserve unrelated map entries, a null value
removes a key, and attempts to mutate non-map representations fail.

Resolve the first query key by walking the operation and its ancestors
that implement the new interface, continuing upward when a scope cannot
answer that key. Resolve subsequent keys recursively through the
returned attribute's DLTIQueryInterface without restarting the ancestor

    [27 lines not shown]
DeltaFile
+100-43mlir/test/Dialect/DLTI/query.mlir
+82-23mlir/lib/Dialect/DLTI/DLTI.cpp
+43-32mlir/test/Target/LLVMIR/target-to-data-layout-and-target-features.mlir
+70-2mlir/test/lib/Dialect/DLTI/TestDataLayoutQuery.cpp
+58-0mlir/include/mlir/Dialect/DLTI/DLTIOpInterfaces.td
+53-0mlir/lib/Dialect/Func/IR/FuncOps.cpp
+406-10032 files not shown
+687-16038 files

LLVM/project 9895fee — llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 vector-fshr-256.ll smul_fix_sat.ll

[X86] LowerFunnelShift - handle fsh*(x,y,0) case (#232923)

Normally DAGCombine handles this, but we might end up with an all-zero shift amount during legalization (via splitting etc.)

Fixes #232596
DeltaFile
+14-1llvm/test/CodeGen/X86/umul_fix_sat.ll
+9-5llvm/test/CodeGen/X86/smul_fix_sat.ll
+5-0llvm/lib/Target/X86/X86ISelLowering.cpp
+2-2llvm/test/CodeGen/X86/vector-fshr-256.ll
+30-84 files

LLVM/project 88239f3 — llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 combine-max-min.ll

[DAGCombiner] Allow (sub 0, (max X, (sub 0, X))) --> (min X, (sub 0, X)) when neither min/max are legal/custom. (#232486)

If the max isn't legal/custom and the min isn't legal/custom it really
doesn't matter if we keep the max. They'll be expanded very similarly
with different condition codes on the select/branch. Might as well
remove the neg.

Note this code really should take type legalization promotion into
account, but that's a separate problem.
DeltaFile
+52-96llvm/test/CodeGen/RISCV/neg-abs.ll
+15-26llvm/test/CodeGen/AArch64/combine-max-min.ll
+5-1llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+72-1233 files

LLVM/project 7a0f64d — flang/lib/Lower/OpenMP OpenMP.cpp Utils.cpp, flang/test/Lower/OpenMP declare-variant-construct.f90 variant-source-context.f90

[flang][OpenMP] Match variant selectors in the source construct context

The construct context for METADIRECTIVE and DECLARE VARIANT came from
enclosing MLIR operations. It recognized only a few operations, followed
operation nesting instead of source nesting, kept constructs outside an
enclosing TARGET, and used the body context for clause expressions and
loop bounds.

Build the context from the evaluation's source ancestors and from frames
for construct regions entered during lowering:
- A selected METADIRECTIVE replacement stands in for its source construct.
- TARGET discards the outer context.
- Constructs without a selector property still add a nesting level.
- Clause expressions see only enclosing constructs.
- Loop bounds see the leaves that precede the first loop-associated leaf.
- Specification expressions see no construct.

Add llvm::omp::getConstructTraits, which returns the construct traits a
directive adds in source order, with an invalid placeholder for a

    [10 lines not shown]
DeltaFile
+580-0flang/test/Lower/OpenMP/declare-variant-loop-bounds.f90
+303-0flang/test/Lower/OpenMP/declare-variant-metadirective-context.f90
+211-0flang/test/Lower/OpenMP/variant-source-context.f90
+86-22flang/lib/Lower/OpenMP/Utils.cpp
+90-2flang/test/Lower/OpenMP/declare-variant-construct.f90
+71-18flang/lib/Lower/OpenMP/OpenMP.cpp
+1,341-4215 files not shown
+1,721-5621 files

LLVM/project bb34ff4 — llvm/lib/CodeGen/SelectionDAG LegalizeTypes.h LegalizeIntegerTypes.cpp, llvm/test/CodeGen/RISCV abdu-neg.ll abdu.ll

[SelectionDAG][RISCV] Use SExtOrZExtPromotedOperands to promote ABDU in PromoteIntegerResult. (#232037)

Similar to UMIN/UMAX, ABDU can be promoted using sext or zext. Use to
SExtOrZExtPromotedOperands to pick whatever is profitable for the
target. For RISC-V, this means we can use sext.w instead of pair of
shifts.

This covers part of what #231881 was trying to do.
DeltaFile
+77-67llvm/test/CodeGen/RISCV/abdu.ll
+18-22llvm/test/CodeGen/RISCV/abdu-neg.ll
+7-6llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+1-1llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+103-964 files

LLVM/project 7c92781 — llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-simd-32.ll

[RISCV][P-ext] Use concat_vectors with 0 in widenPackedVectorWithZeros.

This will be legalized and combined to a vector_shuffle. That
shuffle can then be matched to a pack with x0 after #232892.

This changes the zext.w to a pack, but that's not obviously worse.
If we need to canonicalize we can add a DAG combine later.
DeltaFile
+8-8llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+4-5llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+12-132 files

LLVM/project 5ae9577 — llvm/lib/Support UnicodeNameToCodepointGenerated.cpp, llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll frem.ll

rebase to main

Created using spr 1.3.7
DeltaFile
+32,088-15,710llvm/test/CodeGen/AMDGPU/frem.ll
+23,347-23,371llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+31,848-0llvm/test/CodeGen/NVPTX/atomicrmw-elementwise-sm60.ll
+31,310-0llvm/test/CodeGen/NVPTX/atomicrmw-elementwise-sm70.ll
+22,710-0llvm/test/CodeGen/NVPTX/atomicrmw-elementwise-sm90.ll
+10,540-10,356llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+151,843-49,4379,061 files not shown
+742,998-338,7199,067 files