LLVM/project 8fb7dfellvm/lib/Target/SPIRV SPIRVStructurizer.cpp

[SPIR-V] Cache PartialOrderingVisitor in Splitter instead of rebuilding per call (#211198)
DeltaFile
+7-12llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
+7-121 files

LLVM/project 03e8192clang/test/Driver/flang multiple-inputs-mixed.f90 runtimes.f90

Revert "[NFC][clang][Driver] Add tests for --driver-mode=flang (#207658)"

This reverts commit d814be1bb794baf0650158a6bd1dda23f4f86e99.
DeltaFile
+0-22clang/test/Driver/flang/multiple-inputs-mixed.f90
+0-8clang/test/Driver/flang/runtimes.f90
+0-302 files

LLVM/project a7d2602libcxx/docs ReleaseProcedure.rst

[libc++] Update release procedure for libc++ & friends (#210383)

The release procedure implied that some tasks were done by the release
manager, but in practice they are done by the libc++ developers.

Also, mention using the `llvm-premerge-libcxx-release-runners` runner
set on the release branch, which was overlooked in the previous notes.

Other than that, minor reformulations.
DeltaFile
+13-24libcxx/docs/ReleaseProcedure.rst
+13-241 files

LLVM/project b0b0a53clang/lib/Serialization ASTReader.cpp ASTWriter.cpp, clang/test/CodeGen/SystemZ zos-check-lanuage.c

Write original source language when writing and reading AST (#209353)

FAIL: Clang :: Frontend/ast-main.c
FAIL: Clang :: Frontend/ast-main.cpp

were failing on z/OS; this change fixes these lit failures.

The issue here is that on z/OS the original source code language needs
to be passed through to the IR so that the backend can encode this
information in the PPA2 in the object file. That means that it needs to
be exported to the AST so that going from saved AST -> IR will carry the
language through.
DeltaFile
+27-0clang/test/CodeGen/SystemZ/zos-check-lanuage.c
+1-0clang/lib/Serialization/ASTReader.cpp
+1-0clang/lib/Serialization/ASTWriter.cpp
+29-03 files

LLVM/project 144595fllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/AArch64 smul_fix_sat.ll umul_fix_sat.ll

[SelectionDAG][AArch64][X86] Don't scalarize vector smul.fix.sat/umul.fix.sat (#209351)

Vector SMULFIXSAT/UMULFIXSAT were not handled by expandFixedPointMul in
the vector legalizer (a FIXME) and were unrolled to per-lane scalar
code: a single <8 x i16> smul.fix.sat was ~100 instructions on both
AArch64 and x86.

Expand the saturating variants like the non-saturating ones, and build
the saturation clamp with SETCC + VSELECT for vector types so it stays
vectorized instead of being scalarized by SELECT_CC legalization. Scalar
lowering is unchanged: the clamp change is guarded on isVector(), so
scalar fixed-point codegen on every target is bit-identical.

Additionally custom-lower SMULFIXSAT on AArch64 for scale == eltbits-1,
which is exactly sqdmulh, to a single instruction.

To the FIXME note - results in a ~12x speedup over the unroll fallback.

AI was used in the making of this PR, and if its feedback is to be

    [2 lines not shown]
DeltaFile
+111-585llvm/test/CodeGen/AArch64/smul_fix_sat.ll
+71-463llvm/test/CodeGen/AArch64/umul_fix_sat.ll
+62-114llvm/test/CodeGen/X86/smul_fix_sat.ll
+31-88llvm/test/CodeGen/X86/vector-mulfix-legalize.ll
+17-77llvm/test/CodeGen/X86/umul_fix_sat.ll
+22-16llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+314-1,3431 files not shown
+316-1,3507 files

LLVM/project 5f31853llvm/test/CodeGen/AArch64 aarch64-mops.ll

[AArch64] Fix volatile flags in mops tests (NFC) (#211511)
DeltaFile
+22-22llvm/test/CodeGen/AArch64/aarch64-mops.ll
+22-221 files

LLVM/project 7d566aaoffload/plugins-nextgen/level_zero/src L0Program.cpp

[OFFLOAD][L0] Restore function pointer lookup. (#211520)

PR #201352 incorrectly removed the calls to zeModuleGetGlobalPointer
when looking up a symbol.
DeltaFile
+9-5offload/plugins-nextgen/level_zero/src/L0Program.cpp
+9-51 files

LLVM/project fd67f99clang/lib/Basic/Targets AMDGPU.cpp, clang/test/CodeGenOpenCL amdgpu-wavefront-size-from-subarch.cl

clang/AMDGPU: Fix handling of subarch triples with no -mcpu (#211467)
DeltaFile
+37-0clang/test/CodeGenOpenCL/amdgpu-wavefront-size-from-subarch.cl
+24-0clang/test/Preprocessor/amdgpu-subarch-cc1-target-cpu.cl
+8-2llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+5-2clang/lib/Basic/Targets/AMDGPU.cpp
+74-44 files

LLVM/project 38b7237offload/plugins-nextgen/level_zero/src L0Device.cpp

[OFFLOAD][L0] Add NUM_LANES info (#211526)
DeltaFile
+1-1offload/plugins-nextgen/level_zero/src/L0Device.cpp
+1-11 files

LLVM/project 48d5c3eclang/lib/StaticAnalyzer/Checkers BasicObjCFoundationChecks.cpp ObjCSuperDeallocChecker.cpp

[analyzer][NFC] Remove unused ProgramStateRef local variables (#211517)

Several checkers and ExprEngine declare a ProgramStateRef local that is
never read (typically `State = C.getState();` immediately followed by
code that re-fetches the state directly). These are not flagged by
-Wunused-variable because ProgramStateRef has a non-trivial destructor.

Found with a clang-query matcher over clang/lib/StaticAnalyzer.
Assisted-by: claude
DeltaFile
+1-2clang/lib/StaticAnalyzer/Checkers/BasicObjCFoundationChecks.cpp
+0-2clang/lib/StaticAnalyzer/Checkers/ObjCSuperDeallocChecker.cpp
+0-2clang/lib/StaticAnalyzer/Checkers/ExprInspectionChecker.cpp
+0-1clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
+0-1clang/lib/StaticAnalyzer/Checkers/PointerArithChecker.cpp
+0-1clang/lib/StaticAnalyzer/Checkers/VAListChecker.cpp
+1-91 files not shown
+1-107 files

LLVM/project ad1b243llvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/AArch64 shuffletoidentity-concat.ll shuffletoidentity.ll

[VectorCombine] foldShuffleToIdentity - ensure we push any created instructions to the WorkList (#211508)

generateNewInstTree is recursive - ensure all new instructions are
pushed to the WorkList (and in the correct order).

I also renamed the local Worklist variable -> Candidates to stop
shadowing VectorCombine::WorkList - there's more "WorkLists" in
VectorCombine that need fixing but this was causing a particular
annoyance to this patch.
DeltaFile
+34-29llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+1-3llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity-concat.ll
+1-2llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
+36-343 files

LLVM/project ecf4c97clang/lib/StaticAnalyzer/Core ExprEngineCXX.cpp

[analyzer][NFC] Remove leftover PreElideState stash in copy elision (#211518)

computeObjectUnderConstruction stashed the program state into
PreElideState "before trying to elide, as it'll get overwritten", but
never used it. That comment and stash are fossils of the old
prepareForObjectConstruction, which returned and threaded the state
(`std::tie(State, V) = ...`); the failure path then reverted it with
`State = PreElideState;`.

The refactor to the SVal-returning computeObjectUnderConstruction (State
is now passed by value and the state updates moved to
updateObjectsUnderConstruction) dropped that revert but left the stash
and comment behind. State is never overwritten here anymore, so remove
the dead PreElideState and reword the comment to describe only the
CallOpts stash, which is still needed (CallOpts is passed by reference
and genuinely overwritten by the elision attempt).

Found with a clang-query matcher over clang/lib/StaticAnalyzer.
Assisted-by: claude
DeltaFile
+2-2clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
+2-21 files

LLVM/project de7cd65clang/test/Analysis/z3 z3-bitint-arithmetic.c

[analyzer][Z3] Fix z3-bitint-arithmetic.c test RUN line (#211515)

I used to get these errors on M4 with `LLVM_ENABLE_Z3_SOLVER`:

```
error: 'expected-error' diagnostics seen but not expected:
  File clang/test/Analysis/z3/z3-bitint-arithmetic.c Line 26: unsigned _BitInt of bit sizes greater than 128 not supported
  File clang/test/Analysis/z3/z3-bitint-arithmetic.c Line 29: unsigned _BitInt of bit sizes greater than 128 not supported
```

Fixes up #210525
Another nail in the coffin of #184695
DeltaFile
+1-0clang/test/Analysis/z3/z3-bitint-arithmetic.c
+1-01 files

LLVM/project d814be1clang/test/Driver/flang multiple-inputs-mixed.f90 runtimes.f90

[NFC][clang][Driver] Add tests for --driver-mode=flang (#207658)

This patch intends to clarify the current behaviors, not to state the
expected/desirable behaviors.

---------

Co-authored-by: Tarun Prabhu <tarunprabhu at gmail.com>
DeltaFile
+22-0clang/test/Driver/flang/multiple-inputs-mixed.f90
+8-0clang/test/Driver/flang/runtimes.f90
+30-02 files

LLVM/project 1c825bellvm/lib/Transforms/Vectorize VectorCombine.cpp, llvm/test/Transforms/VectorCombine/X86 load-inseltpoison.ll

[VectorCombine] Check load offsets in APInt before narrowing shuffle indices (#210904)

vectorizeLoadInsert narrowed the APInt element offset to unsigned before
checking its range. Large offsets could wrap and select the wrong vector
element.

Check the offset range as an APInt before converting it to the shuffle
index. This prevents invalid load widening and is covered by
a regression test.

Fixes #210903
DeltaFile
+16-0llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
+3-2llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+19-22 files

LLVM/project a6be842llvm/lib/Transforms/InstCombine InstCombineAddSub.cpp

[InstCombine] Fix typo in assert message for Fp state (#211244)
DeltaFile
+2-2llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+2-21 files

LLVM/project cc1dd6bllvm/lib/Transforms/Utils LoopUnroll.cpp, llvm/test/Transforms/LoopUnroll partial-unroll-reductions.ll

[LoopUnroll] Make the list of supported recurrence kinds inclusive. (#210957)

This excludes Sub, AddChainWithSubs, FSub and FAddChainWithSubs
recurrence kinds by making the list of supported types opt-in as opposed
to opt-out. This will hopefully mean that as more recurrence kinds are
added in the future, the list supported by the unrolling remains valid.

Fixes #201065
DeltaFile
+47-0llvm/test/Transforms/LoopUnroll/partial-unroll-reductions.ll
+11-4llvm/lib/Transforms/Utils/LoopUnroll.cpp
+58-42 files

LLVM/project 794f7d5llvm/docs ReleaseNotes.md

[docs] Add BOLT release notes
DeltaFile
+7-0llvm/docs/ReleaseNotes.md
+7-01 files

LLVM/project 0037f09clang/include/clang/StaticAnalyzer/Core/PathSensitive ExprEngine.h, clang/lib/StaticAnalyzer/Core ExprEngineC.cpp

[NFC][analyzer] Eliminate the NodeBuilder in VisitUnaryOperator (#211304)

This is part of the commit series to gradually remove the class
`NodeBuilder` from the analyzer codebase.

This was a relatively complex situation because there were many
different `generateNode` calls and two situations where the the node
from `CheckedSet` was left in `EvalSet` without changes (which is
implicit with the `NodeBuilder` but now requires explicit
`EvalSet.insert(N)` calls).
DeltaFile
+17-31clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
+0-3clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
+17-342 files

LLVM/project f953ed4clang/include/clang/StaticAnalyzer/Core/PathSensitive SMTConv.h, clang/test/Analysis/z3 z3-crosscheck.c

[analyzer][z3] Fix crash in Z3 SMTConv when casting atomic int (#211489)

CPP-7675
DeltaFile
+8-0clang/test/Analysis/z3/z3-crosscheck.c
+2-2clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConv.h
+10-22 files

LLVM/project 492d726clang/lib/Headers avx10_2satcvtdsintrin.h, clang/test/CodeGen/X86 avx10_2satcvtds-builtins-x64.c avx10_2satcvtds-builtins.c

[X86][AVX10.2] Add missing _mm_cvtts_ss/sd* intrinsics (#211185)

Fixes part of #210947

Assisted-by: Claude Opus 4.8
DeltaFile
+67-0clang/lib/Headers/avx10_2satcvtdsintrin.h
+36-0clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c
+36-0clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c
+139-03 files

LLVM/project c66c625llvm/lib/Target/RISCV RISCVProcessors.td

[RISCV] Add TuneNoDefaultUnroll to spacemit-x60 (#211502)

This feature has been added to generic CPUs in #135318 and we don't
see any significant regression on `spacemit-x60`.
DeltaFile
+2-1llvm/lib/Target/RISCV/RISCVProcessors.td
+2-11 files

LLVM/project 280099ellvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/VPlan/AArch64 vplan-memory-op-decisions.ll

[VPlan] Widen reverse unit-stride accesses in makeMemOpWideningDesc (NFCI) (#208807)

Update widenConsecutiveMemOps to also widen reversed consecutive
accesses (stride == -1), by creating a VPVectorEndPointerRecipe via
VPBuilder, load and reverse.

PR: https://github.com/llvm/llvm-project/pull/208807
DeltaFile
+29-18llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+7-3llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
+36-212 files

LLVM/project 21f36e3llvm/lib/Target/X86 X86TargetTransformInfo.cpp, llvm/test/Analysis/CostModel/X86 clmul.ll

[CostModel][X86] Add PCLMUL cost table (#211113)

The current cost modeling for X86 does not have `ISD::CLMUL` listed in
any cost table, so the cost for `llvm.clmul` falls back to the default
for `Custom`, which is twice the type legalization cost. Since `CLMUL`
uses the `xmm` registers with `pclmulqdq`, this operation is typically
much more expensive. Add a new table for PCLMUL to reflect this.

Note that AVX, AVX512, and VPCLMULQDQ are still not modeled correctly.
This is left as a FIXME for now.

Assisted-by: Claude Opus 4.8
DeltaFile
+50-50llvm/test/Analysis/CostModel/X86/clmul.ll
+17-0llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+67-502 files

LLVM/project 20d8cb4llvm/docs/CommandGuide llvm-pdbutil.rst, llvm/docs/DirectX DXContainer.rst

[docs][tools][DirectX] Document DXContainer debug info parts (#204021)

This patch adds ILDB, ILDN, VERS, SRCI parts format documentation. It
describes how to use LLVM tools to inspect them. Additionally,
llvm-pdbutil documentation has been expanded with information on how to
inspect PDB files generated by the DirectX compiler.
DeltaFile
+482-6llvm/docs/DirectX/DXContainer.rst
+71-0llvm/docs/CommandGuide/llvm-pdbutil.rst
+553-62 files

LLVM/project 509b7dcllvm/test/MC/AMDGPU amdgcn-target-directive-subarch-cpu-field.s hsa-diag-v4.s

AMDGPU: Use llvm-mc -triple= arguments instead of space separator

-triple=amdgcn.. is the dominant form over -triple amdgcn. Convert
the outliers for easier subarch triple conversion.
DeltaFile
+9-9llvm/test/MC/AMDGPU/amdgcn-target-directive-subarch-cpu-field.s
+8-8llvm/test/MC/AMDGPU/hsa-diag-v4.s
+7-7llvm/test/MC/AMDGPU/isa-version-hsa.s
+7-7llvm/test/MC/AMDGPU/isa-version-unk.s
+7-7llvm/test/MC/AMDGPU/isa-version-pal.s
+5-5llvm/test/MC/AMDGPU/amdgcn-target-directive-conflict.s
+43-4343 files not shown
+121-12149 files

LLVM/project 797ead5llvm/test/CodeGen/AMDGPU llvm.amdgcn.cvt.fp8.f16.ll code-size-estimate-gfx1250.ll, llvm/test/MC/AMDGPU gfx13_asm_vop1_dpp16.s gfx1250_asm_vop3-fake16.s

[AMDGPU] Add gfx13 support for v_cvt_pk_{fp8,bf8}_f16 (#211263)

GFX13 supports VOP1 and VOP3 forms of these instructions; GFX1250 keeps
its VOP3-only encoding.

Co-authored-by: Guo Chen <guochen2 at amd.com>
DeltaFile
+272-25llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
+70-28llvm/test/CodeGen/AMDGPU/code-size-estimate-gfx1250.ll
+89-0llvm/test/MC/AMDGPU/gfx13_asm_vop1_dpp16.s
+28-36llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt
+18-24llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s
+18-24llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s
+495-1379 files not shown
+638-16515 files

LLVM/project 73f2489llvm/lib/Bitcode/Writer BitcodeWriter.cpp

Test
DeltaFile
+1-0llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+1-01 files

LLVM/project 55356d3llvm/test/MachineVerifier/AMDGPU dpp-sgpr-src1.mir dpp-imm-src1.mir

AMDGPU: Migrate more machine verifier tests to subarch triples
DeltaFile
+3-3llvm/test/MachineVerifier/AMDGPU/dpp-sgpr-src1.mir
+3-3llvm/test/MachineVerifier/AMDGPU/dpp-imm-src1.mir
+1-1llvm/test/MachineVerifier/AMDGPU/hazard-gfx1250-flat-src-hi.mir
+1-1llvm/test/MachineVerifier/AMDGPU/invalid-vop3-source-modifiers.mir
+1-1llvm/test/MachineVerifier/AMDGPU/issue98474-missing-def-liveout-physical-subregister.mir
+1-1llvm/test/MachineVerifier/AMDGPU/lit64.mir
+10-1020 files not shown
+30-3026 files

LLVM/project b476a59llvm/lib/Transforms/Utils FunctionComparator.cpp, llvm/test/Transforms/MergeFunc atomic-elementwise.ll atomic-load-elementwise.ll

Support atomicrmw
DeltaFile
+42-0llvm/test/Transforms/MergeFunc/atomic-elementwise.ll
+0-22llvm/test/Transforms/MergeFunc/atomic-load-elementwise.ll
+3-0llvm/lib/Transforms/Utils/FunctionComparator.cpp
+45-223 files