LLVM/project 3d01fffllvm/test/CodeGen/SPIRV/transcoding OpGroupAsyncCopy-strided-64.ll

Merge branch 'users/mgcarrasco/spirv/fix-spirv-val-tests' into users/jmmartinez/spirv/memory_consumption
DeltaFile
+0-1llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided-64.ll
+0-11 files

LLVM/project 40f2a5dllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fpext.ll unmerge-sgpr-s16.ll

AMDGPU/GlobalISel: Regbanklegalize rules for G_UNMERGE_VALUES

Move G_UNMERGE_VALUES handling to AMDGPURegBankLegalizeRules.cpp.
Fix sgpr S16 unmerge by lowering using shift and using S32.
Previously sgpr S16 unmerge was selected using _lo16 and _hi16 subreg
indexes which are exclusive to vgpr register classes.
For remaing cases we do trivial mapping, assigns same reg bank
to all operands, vgpr or sgpr.
DeltaFile
+47-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+13-27llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
+36-0llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
+24-0llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+14-9llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+14-9llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+148-452 files not shown
+156-498 files

LLVM/project 8370304lldb/source/API SBBreakpointName.cpp, lldb/test/API/functionalities/breakpoint/breakpoint_names TestBreakpointNames.py

[lldb] Fix SBBreakpointName::SetEnabled to propagate changes to breakpoints (#178734)

When setting the enabled state of a breakpoint name via the API, the
change was not being propagated to breakpoints using that name.
This was inconsistent with the CLI behaviour where `breakpoint name
configure --enable/--disable` correctly updates all associated
breakpoints.
DeltaFile
+66-2lldb/test/API/functionalities/breakpoint/breakpoint_names/TestBreakpointNames.py
+1-0lldb/source/API/SBBreakpointName.cpp
+67-22 files

LLVM/project f5c80a6clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp, clang/lib/Sema SemaAMDGPU.cpp

Address comments
DeltaFile
+51-0clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
+24-14clang/lib/Sema/SemaAMDGPU.cpp
+32-0clang/test/SemaHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
+12-17clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+26-0clang/test/SemaHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
+25-0clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
+170-311 files not shown
+175-377 files

LLVM/project 3bf2c83lldb/source/Plugins/Process/scripted ScriptedFrame.cpp

[lldb] Clean up #includes. NFC.
DeltaFile
+4-6lldb/source/Plugins/Process/scripted/ScriptedFrame.cpp
+4-61 files

LLVM/project 956770allvm/lib/Transforms/Utils SimplifyCFG.cpp, llvm/test/Transforms/SimplifyCFG jump-threading.ll

[SimplifyCFG] Fix null pointer dereference in foldCondBranchOnValueKnownInPredecessorImpl (#178835)

DeltaFile
+41-0llvm/test/Transforms/SimplifyCFG/jump-threading.ll
+2-0llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+43-02 files

LLVM/project c8132f3llvm/test/CodeGen/SPIRV event-zero-const-64.ll event-zero-const.ll, llvm/test/CodeGen/SPIRV/transcoding spirv-event-null.ll spirv-event-null-64.ll

[SPIRV] Split async copy tests and fix invalid tests

After a spirv-val update, tests that mix spirv32 and spirv64 targets with
the same LLVM IR are now correctly flagged as invalid. The SPIR-V
specification requires that NumElements and Stride operands in
OpGroupAsyncCopy must be 32-bit integers when the addressing model is
Physical32, and 64-bit integers for Physical64.
DeltaFile
+55-52llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll
+101-0llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null-64.ll
+37-0llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided-64.ll
+16-15llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided.ll
+27-0llvm/test/CodeGen/SPIRV/event-zero-const-64.ll
+6-6llvm/test/CodeGen/SPIRV/event-zero-const.ll
+242-736 files

LLVM/project d0ed0acllvm/lib/Analysis ValueTracking.cpp, llvm/test/Transforms/Attributor nofpclass-fma.ll nofpclass-fmul.ll

ValueTracking: Revert noundef checks in computeKnownFPClass for fmul/fma

This functionally reverts fd5cfcc41311c6287e9dc408b8aae499501660e1 and
35ce17b6f6ca5dd321af8e6763554b10824e4ac4.

This was correct and necessary, but is causing performance regressions
since isGuaranteedNotToBeUndef is apparently not smart enough to detect
through recurrences. Revert this for the release branch.

Also the test coverage was inadequate for the fma case, so add a new
case which changes with and without the check.
DeltaFile
+24-0llvm/test/Transforms/Attributor/nofpclass-fma.ll
+4-5llvm/lib/Analysis/ValueTracking.cpp
+1-1llvm/test/Transforms/Attributor/nofpclass-fmul.ll
+29-63 files

LLVM/project 710449bllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll

Merge branch 'users/mgcarrasco/spirv/fix-spirv-val-tests' into users/jmmartinez/spirv/memory_consumption
DeltaFile
+93,308-106,563llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+33,140-38,089llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+12,028-14,711llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+7,381-11,318llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+8,488-9,853llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+6,645-10,108llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+160,990-190,6421,832 files not shown
+327,251-331,0191,838 files

LLVM/project 369e787llvm/include/llvm/Target/GlobalISel Combine.td, llvm/test/CodeGen/AMDGPU/GlobalISel postlegalizer-combiner-merge.mir

[GlobalISel] Insert bitcast instead of register replacement when types don't match. (#177397)

Cases like the newly added test with the vector types currently hit
```Assertion `canReplaceReg(OldReg, Replacement, MRI) && \"Cannot
replace register?\"' failed."``` because source and destination
registers have mismatching types. Apart from the assertion, it also
fails when using `--verify-machineinstrs`. This PR adds a bitcast in
those cases.
DeltaFile
+58-4llvm/include/llvm/Target/GlobalISel/Combine.td
+47-0llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-merge.mir
+105-42 files

LLVM/project 4238693llvm/lib/Target/AMDGPU SIISelLowering.cpp SIInstructions.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmin.ll llvm.amdgcn.reduce.fmax.ll

[AMDGPU] Add wave reduce intrinsics for double types - 1 (#170811)

Supported Ops: `min`, `max`
DeltaFile
+1,280-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+1,280-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+70-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+3-1llvm/lib/Target/AMDGPU/SIInstructions.td
+2,633-24 files

LLVM/project d3c6463llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-streaming-mode-fixed-length-int-mulh.ll sve-streaming-mode-fixed-length-fp-rounding.ll

[DAG] Enable bitcast STLF for Constant/Undef (#172523)

This patch introduces support for Store-to-Load Forwarding (STLF) in
`DAGCombiner::ForwardStoreValueToDirectLoad` when the store and load
have **different types but equal memory size** (e.g., storing an `i32`
then loading a `float` from the same location).

### What this patch does:
**Enables Optimization:** It allows for the safe forwarding of the
stored value as a Bitcast when the value is:
* A **Constant** (`ConstantSDNode`, `ConstantFPSDNode`,
`ConstantPoolSDNode`).
    * **Undef**.
    * And the memory sizes (`LdMemSize` == `StMemSize`) match.

### Scope and Next Steps:

This patch **only implements forwarding for constant and undef values
that has the same memory size** so far.

    [14 lines not shown]
DeltaFile
+71-0llvm/test/CodeGen/X86/dag-stlf-mismatch.ll
+8-22llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
+26-3llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+0-14llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
+4-8llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
+12-0llvm/test/CodeGen/AArch64/sve-stlf.ll
+121-4736 files not shown
+187-17242 files

LLVM/project 034e5d6llvm/lib/Transforms/Scalar MemCpyOptimizer.cpp, llvm/test/Transforms/MemCpyOpt memset-memcpy-oversized.ll lifetime-missing.ll

[MemCpyOpt] Extend `performMemCpyToMemSetOptzn` to partially memset'd region

While doing memset-to-memcpy forwarding, take into account memset
that covers memory regions from a given offset, and the leading
bytes of such a region are undef.

Fixes: https://github.com/llvm/llvm-project/issues/172326.
DeltaFile
+36-18llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
+10-5llvm/test/Transforms/MemCpyOpt/memset-memcpy-oversized.ll
+5-1llvm/test/Transforms/MemCpyOpt/lifetime-missing.ll
+51-243 files

LLVM/project 6fdcdbdllvm/test/Transforms/MemCpyOpt memset-memcpy-oversized.ll

[MemCpyOpt] Avoid introducing UB, precommit tests (NFC)
DeltaFile
+108-5llvm/test/Transforms/MemCpyOpt/memset-memcpy-oversized.ll
+108-51 files

LLVM/project afb2e4fclang/lib/AST/ByteCode Function.h Context.cpp

[clang][bytecode] Clean up `interp::Function` parameter handling (#178621)

Replace the multiple data structures with a vector + a map holding all
`ParamDescriptor`s. Update docs.
DeltaFile
+29-15clang/lib/AST/ByteCode/Function.h
+11-22clang/lib/AST/ByteCode/Context.cpp
+9-8clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
+7-5clang/lib/AST/ByteCode/Function.cpp
+4-4clang/lib/AST/ByteCode/InterpFrame.cpp
+2-2clang/lib/AST/ByteCode/Interp.cpp
+62-566 files

LLVM/project e89c634llvm/include/llvm/ADT GenericUniformityImpl.h, llvm/include/llvm/CodeGen TargetInstrInfo.h

Implement per-output machine uniformity analysis
DeltaFile
+66-11llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
+48-11llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+12-10llvm/include/llvm/ADT/GenericUniformityImpl.h
+9-1llvm/lib/Analysis/UniformityAnalysis.cpp
+5-2llvm/include/llvm/CodeGen/TargetInstrInfo.h
+2-5llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/per-output-uniformity.mir
+142-401 files not shown
+146-427 files

LLVM/project cf0f862llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR per-output-uniformity.mir

Add test for amdgcn.if/else uniformity analysis

This test documents the current behavior where both outputs of
amdgcn.if and amdgcn.else are marked as divergent. The second
output (exec mask) should be uniform.
DeltaFile
+42-0llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/per-output-uniformity.mir
+42-01 files

LLVM/project c391efeclang/docs LanguageExtensions.rst, clang/include/clang/Options Options.td

[Driver][Frontend] Add -f[no-]ms-anonymous-structs flag to control Microsoft anonymous struct/union extension                                                                                                                       (#176551)

Add a Clang driver option -fms-anonymous-structs and
-fno-ms-anonymous-structs
to enable or disable Microsoft anonymous struct/union support
independently of -fms-extensions.

**Motivation**:
- On some platforms (e.g. AIX), enabling `-fms-extensions` can conflict
    with system headers (such as usage of `__ptr32`).
  - Some codebases rely specifically on Microsoft anonymous struct/union
    behavior without requiring other Microsoft extensions.

This change allows users to selectively enable the anonymous
struct/union
extension at the driver level without enabling full Microsoft
compatibility
mode.


    [28 lines not shown]
DeltaFile
+76-0clang/test/Sema/MicrosoftAnonymousStructs.c
+54-0clang/lib/Driver/ToolChains/Clang.cpp
+44-0clang/docs/LanguageExtensions.rst
+38-0clang/test/Driver/ms-anonymous-structs.c
+24-0clang/test/Frontend/ms-anon-structs-args.c
+8-0clang/include/clang/Options/Options.td
+244-03 files not shown
+249-19 files

LLVM/project 6944b81lldb/test/API/tools/lldb-dap/completions TestDAP_completions.py, lldb/tools/lldb-dap/Handler CompletionsHandler.cpp

[lldb-dap] Fix the completion provided to the DAP client. (#177151)

Previously, completion behavior was inconsistent,
sometimes including the partial token or removing existing user text.
Since LLDB completions includes the partial token by default, we now
strip it before sending to the client.

The completion heuristic:
1. Strip the commandEscapePrefix
2. Request completions from the debugger
3. Get the line at cursor position
4. Calculate the length of any partial token
5. Offset each completion by the partial token length

In all cases, the completion starts from the cursor position. then
offsets by `Length` to the left and inserts the completion.

Examples (single quotes show whitespace and are not part of the input):
```md

    [15 lines not shown]
DeltaFile
+250-119lldb/test/API/tools/lldb-dap/completions/TestDAP_completions.py
+18-9lldb/tools/lldb-dap/Handler/CompletionsHandler.cpp
+4-4lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
+272-1323 files

LLVM/project 8dcfcf2llvm/test/CodeGen/AMDGPU release-vgprs-spill.ll

[AMDGPU] Add test for early release VGPRs with spills (#178444)

(cherry picked from commit 1873c746c6a79fcfd3f5e5884b42f3843cc7c5aa)
DeltaFile
+49-0llvm/test/CodeGen/AMDGPU/release-vgprs-spill.ll
+49-01 files

LLVM/project 12f90edllvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU release-vgprs-spill.ll

[AMDGPU] Fix DEALLOC_VGPRS in the presence of spills to scratch (#178461)

(cherry picked from commit dbd42401305b45e4a2854d24a1987d0f01b75754)
DeltaFile
+5-4llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-3llvm/test/CodeGen/AMDGPU/release-vgprs-spill.ll
+6-72 files

LLVM/project f0eba4fmlir/lib/Dialect/Shape/IR Shape.cpp, mlir/test/Dialect/Shape canonicalize.mlir

[mlir][shape] Fix crash in FromExtentsOp::fold with poison operands (#178844)

## Summary
- Fix assertion failure in `shape.from_extents` fold when operands
include `ub.poison`
- The fold assumed all non null attributes were `IntegerAttr`, but
poison produces a different attribute type
- Use `dyn_cast_if_present` to safely handle non integer attributes

Fixes #178820

## Test plan
- Added regression test `@from_extents_poison` in canonicalize.mlir
DeltaFile
+12-0mlir/test/Dialect/Shape/canonicalize.mlir
+6-4mlir/lib/Dialect/Shape/IR/Shape.cpp
+18-42 files

LLVM/project 3425b82llvm/lib/CodeGen ExpandIRInsts.cpp, llvm/test/CodeGen/AMDGPU fptoi.i128.ll

[ExpandIRInst] Support expanding fptoi to smaller type (#178690)

In order to support expanding fptoi where the target type is smaller,
make most of the code work on the float-as-integer type, rather than the
target type of the cast. We only need to cast the final result to the
target type, or prior to performing a left shift.

This not only allows us to handle casts to a smaller type, but also
avoids performing intermediate calculations on unnecessarily large
types.

This also matches how compiler-rt handles this:
https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fp_fixint_impl.inc

Proof: https://alive2.llvm.org/ce/z/3pJ9pE

(Note that there is a pre-existing issue that we produce the same code
for fptosi and fptoui.)
DeltaFile
+678-852llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+84-72llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptosi129.ll
+84-72llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptoui129.ll
+116-24llvm/test/Transforms/ExpandIRInsts/X86/expand-fp-convert-small.ll
+24-20llvm/lib/CodeGen/ExpandIRInsts.cpp
+986-1,0405 files

LLVM/project 6c94856llvm/lib/CodeGen InlineSpiller.cpp, llvm/test/CodeGen/Hexagon regalloc-bad-undef.mir

[InlineSpiller] Hoist spills only when all of its subranges are available (#177703)

Context:
https://github.com/llvm/llvm-project/issues/176001#issuecomment-3793846479

When we're hoisting a spill to another block, and storing one of its
sibling values there instead, we need to make sure all sub ranges of
that sibling value is alive at the insertion point. Otherwise, we might
accidentally store compromised subranges values back to the spill slot.

(cherry picked from commit 75f03a62d1f9b0081fff57ceebb29a3ae1560a61)
DeltaFile
+146-0llvm/test/CodeGen/RISCV/pr176001.ll
+8-2llvm/lib/CodeGen/InlineSpiller.cpp
+4-4llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
+158-63 files

LLVM/project c099597llvm/include/llvm/CodeGen TargetLoweringObjectFileImpl.h, llvm/include/llvm/MC MCGOFFAttributes.h

[SystemZ] Implement ctor/dtor emission via @@SQINIT and .xtor sections (#171476)

This patch implements support for constructors/destructors by
introducing the
`@@SQINIT` section and emitting `.xtor.<priority>` sections within the
SystemZ
AsmPrinter and in the GOFF object lowering layer.

(cherry picked from commit 41567d8ec21b79e16c9f1223e2df23c65c1bc195)
DeltaFile
+63-0llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+36-0llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+34-0llvm/test/CodeGen/SystemZ/zos_sinit.ll
+2-0llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
+1-0llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
+1-0llvm/include/llvm/MC/MCGOFFAttributes.h
+137-06 files

LLVM/project b4c7518llvm/lib/Transforms/Vectorize VPlanRecipes.cpp VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize/AArch64 partial-reduce-fdot-product.ll

[LV] Add support for extended fadd reductions (#178447)

This makes use of the llvm.vector.partial.reduce.fadd intrinsics added
in #163975 to handle the following with FDOT:
```
float32_t fdot(float16_t *src, int N) {
  float32_t sum = 0.0f;
  for (int i=0; i<N; ++i)
    sum += src[i];
  return sum;
}
```
DeltaFile
+141-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+15-12llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+9-7llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+2-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+167-204 files

LLVM/project ffb7a9fllvm/lib/Target/AArch64 AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sve-sext-zext.ll

[AArch64] Fix sign-extend-inreg combine for i1 types (#177976)

This fixes https://github.com/llvm/llvm-project/issues/177925
DeltaFile
+28-0llvm/test/CodeGen/AArch64/sve-sext-zext.ll
+3-3llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+31-32 files

LLVM/project 0985ac8clang/lib/Basic/Targets RISCV.h, clang/test/CodeGen ext-int-cc.c

Revert "[RISCV] Support RISCV BitInt larger than 128 (#175515)" (#178311)

This reverts commit e3156c531da5aa4ec604605ed4e19638879d773c.

We need to resolve a crash on trunk and LLVM 22. Reverting makes it
easier to backport.

Fixes #176637.
DeltaFile
+850-5,393llvm/test/CodeGen/RISCV/fpclamptosat.ll
+0-2,175llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
+36-218clang/test/CodeGen/RISCV/bitint.c
+0-4clang/lib/Basic/Targets/RISCV.h
+2-0clang/test/CodeGen/ext-int-cc.c
+0-2llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+888-7,7926 files

LLVM/project c70cf16llvm/lib/CodeGen/LiveDebugValues VarLocBasedImpl.cpp, llvm/test/CodeGen/Hexagon livedebugvalues-bundle-terminator.mir

Fix insert DBG_VALUE after terminator Failure for Hexagon (#173401)

This patch fixes an assertion failure on VLIW targets like Hexagon,
where a packet can contain both a terminator and a spill/copy. The
existing code did not look inside bundles, hence, it could leave a
transfer anchored on a terminator. When LiveDebugValues later
attempted to insert a DBG_VALUE after that packet, it hit:

  Assertion `!TR.TransferInst->isTerminator() && "Cannot insert
DBG_VALUE after terminator"' failed

The change switches to instr_iterator and walks each packet with
getBundleStart/getBundleEnd. Packets containing a terminator are skipped
for insertion; non‑terminator ops in other packets are still processed
normally. This avoids illegal insertion points while keeping spill/copy
tracking intact.

(cherry picked from commit 02771a3eaff153002ec544c3dc4427d56ccd4456)
DeltaFile
+38-0llvm/test/CodeGen/Hexagon/livedebugvalues-bundle-terminator.mir
+30-3llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
+68-32 files

LLVM/project dffe3dflldb/source/Host/windows MainLoopWindows.cpp, lldb/test/Shell/DAP TestSTDINConsole.test

[lldb-dap][windows] allow STDIN to be a console (#178642)

(cherry picked from commit e17374a33f051d7580f35fcac5712d300bfdd9a2)
DeltaFile
+62-0lldb/test/Shell/DAP/TestSTDINConsole.test
+1-1lldb/source/Host/windows/MainLoopWindows.cpp
+63-12 files