LLVM/project 83a8c33llvm/lib/Target/DirectX/DirectXIRPasses DXILDebugInfo.cpp, llvm/test/tools/dxil-dis di-subprogram.ll

[DirectX] Drop unsupported DISubprogram flags (#197457)

These flags did not exist in LLVM 3.7 so should be omitted.
DeltaFile
+11-5llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
+1-1llvm/test/tools/dxil-dis/di-subprogram.ll
+12-62 files

LLVM/project b8ed8a2llvm/lib/Target/RISCV/Disassembler RISCVDisassembler.cpp

[RISCV][Disassembler] Refactor simple predicate decoders using a template

This replaces the manual boilerplate for DecodeGPRNoX0, DecodeGPRNoX2,
DecodeGPRNoX31, and DecodeGPRPairNoX0 with a universal filtering template
and constexpr predicate functions.

I will need more of these for the RVY patch series, so submitting this NFC
cleanup first.

Pull Request: https://github.com/llvm/llvm-project/pull/198146
DeltaFile
+17-31llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+17-311 files

LLVM/project e4b331ellvm/lib/MC/MCParser AsmParser.cpp MasmParser.cpp, llvm/test/MC/AsmParser macro-unknown-directive.s macros-darwin.s

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+29-4llvm/lib/MC/MCParser/AsmParser.cpp
+29-4llvm/lib/MC/MCParser/MasmParser.cpp
+2-2llvm/test/MC/AsmParser/macro-unknown-directive.s
+2-2llvm/test/MC/AsmParser/macros-darwin.s
+1-2llvm/test/MC/AsmParser/unmatched-if-macro.s
+63-145 files

LLVM/project 5c63509lldb/source/Host/macosx/objcxx HostInfoMacOSX.mm

[LLDB] Add a progress event to xcrun invocations (#198931)

LLDB invokes xcrun to find SDKs on disk. This is usually very fast, but
sometimes (after an Xcode update, or when the searched SDK does not
exist) it can take very long (10s or more). The progress event provides
user feedback to explain the hang.
DeltaFile
+8-0lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
+8-01 files

LLVM/project 262207b.github/workflows libc-fullbuild-tests.yml libc-overlay-tests.yml

[Github] Do not restrict branches for CI workflows (#198925)

This is covered in our CI best practices document in
https://llvm.org/docs/CIBestPractices.html#ensuring-workflows-run-on-the-correct-events.

Otherwise we cannot run libc CI workflows on stacked pull requests.
DeltaFile
+0-1.github/workflows/libc-fullbuild-tests.yml
+0-1.github/workflows/libc-overlay-tests.yml
+0-1.github/workflows/libc-freebsd-vm-tests.yml
+0-33 files

LLVM/project 33bccad.github/workflows libc-shared-tests.yml libc-freebsd-vm-tests.yml

[Github] Do not run libc workflows on forks (#198932)

https://llvm.org/docs/CIBestPractices.html#disabling-jobs-in-forks
DeltaFile
+2-0.github/workflows/libc-shared-tests.yml
+1-0.github/workflows/libc-freebsd-vm-tests.yml
+1-0.github/workflows/libc-fullbuild-tests.yml
+1-0.github/workflows/libc-overlay-tests.yml
+5-04 files

LLVM/project 432b6f3.github/workflows libc-freebsd-vm-tests.yml

[Github] Add version number to libc FreeBSD workflow (#198926)

633539bfa1516e616b798b2eae98bea689b3c410 used the ToT version but does
not necessarily need it. Use the latest release and the standard syntax.

This follows
https://llvm.org/docs/CIBestPractices.html#hash-pinning-dependencies.
DeltaFile
+1-1.github/workflows/libc-freebsd-vm-tests.yml
+1-11 files

LLVM/project d991796clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow PointerFlowExtractor.cpp, clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage UnsafeBufferUsageExtractor.cpp

[SSAF] Let UnsafeBufferUsageExtractor & PointerFlowExtractor ignore templates

Templates are ignored for two reasons:

- Template instantiations are still handled. Template facts can be
  inferred from their instantiations.
- Templates are inherently difficult to reason about. Their ASTs can
  contain dependent expression types (such as ParenListExpr) that
  complicate analysis.
DeltaFile
+33-0clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
+32-0clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
+6-0clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
+6-0clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
+77-04 files

LLVM/project 493ebf7libcxx/include/__thread/support pthread.h

[libc++] Add support for thread-id handling for llvm-libc. (#198595)

This change adds support for properly defining and obtaining
`__libcpp_thread_id` when llvm-libc is used. It defines the integral
thread-id (which satisfies necessary restrictions of having total order,
being hashable and formattable) as `pthread_id_np_t` type and uses
`pthread_getthreadid_np` and `pthread_getunique_np` functions to obtain
it (added in
https://github.com/llvm/llvm-project/pull/197027, following the
discussions in https://github.com/llvm/llvm-project/pull/195139 and
https://github.com/llvm/llvm-project/pull/195202).

We also let `_LIBCPP_NULL_THREAD` macro use a more portable
`PTHREAD_NULL` (defined in the latest POSIX) when this macro is
available, so that it would work as expected for opaque `pthread_t`
implementations, where default constructor might not necessarily
zero-initialize all the members.

This is the last remaining change to allow building libc++ against
llvm-libc with threads enabled (test-suite results TBD).
DeltaFile
+16-3libcxx/include/__thread/support/pthread.h
+16-31 files

LLVM/project 205f4bfllvm/lib/Target/NVPTX NVPTXInstrInfo.cpp, llvm/test/CodeGen/NVPTX machine-cse-predicate-inversion.ll machine-cse-predicate-no-inversion.ll

[NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates (#191890)

Inverted predicates can be used freely in PTX. If we can invert a
predicate and CSE the generating instruction we can save calculating the
inverse.

Teach the NVPTX `commuteInstructionImpl` that SETP instructions can be
inverted to allow CSEing with previous SETP that match the inverted
form. This also inverts the branch users of the predicate to maintain
correctness.

Currently only allow the SETP inversion if all users are branches.
Future work can extend this to `sel` and `not` instructions.

Depends on #191889.

Assisted-by: Cursor / Claude
DeltaFile
+3,903-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll
+1,490-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll
+164-0llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+98-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll
+66-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-rollback.mir
+53-0llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
+5,774-02 files not shown
+5,784-28 files

LLVM/project b996b4elibc/src/__support/OSUtil/linux/syscall_wrappers rt_sigprocmask.h, libc/src/signal pthread_sigmask.h

[libc] Implement pthread_sigmask (#198682)

* Extract `rt_sigprocmask` syscall wrapper into the
libc/src/__support/OSUtil/linux/syscall_wrappers/ directory
* Convert all existing users of this syscall, and simplify the logic
where applicable.
* Implement `pthread_sigmask`, which is effectively another POSIX
wrapper around `rt_sigprocmask` syscall similar to `sigprocmask`
DeltaFile
+64-0libc/test/src/signal/pthread_sigmask_test.cpp
+36-0libc/src/__support/OSUtil/linux/syscall_wrappers/rt_sigprocmask.h
+33-0libc/src/signal/linux/pthread_sigmask.cpp
+27-0libc/src/signal/pthread_sigmask.h
+10-12libc/src/signal/linux/signal_utils.h
+15-2libc/src/signal/linux/CMakeLists.txt
+185-1411 files not shown
+248-3617 files

LLVM/project 57d2c4clibc/include/sys prctl.yaml, libc/src/sys/prctl prctl.h

[libc] Update prctl() declaration to use variadic arguments. (#198654)

prctl declaration should typically use variadic arguments (e.g. see
https://man7.org/linux/man-pages/man2/prctl.2.html), as the types /
quantity of subsequent arguments depends on the `option`. We can't
depend on all `<prctl.h>` users to explicitly cast arguments to
`unsigned long` and passing all 5 of them every time.

* Don't add any option-specific logic, and just consume `arg2`-`arg5`
from variadic arguments and pass them to syscall implementation as-is,
assuming that they won't be used by the kernel if they are not needed,
and consuming these arguments won't lead to crashes.
* Updated the test to use `prctl` variants with less than 5 explicit
arguments (for PR_SET_NAME and PR_GET_NAME).
DeltaFile
+6-12libc/test/src/sys/prctl/linux/prctl_test.cpp
+11-3libc/src/sys/prctl/linux/prctl.cpp
+1-4libc/include/sys/prctl.yaml
+1-2libc/src/sys/prctl/prctl.h
+19-214 files

LLVM/project 1a41236llvm/include/llvm/IR Use.h

format

Created using spr 1.3.6-beta.1
DeltaFile
+4-4llvm/include/llvm/IR/Use.h
+4-41 files

LLVM/project 62e427fclang/lib/CIR/CodeGen CIRGenExpr.cpp CIRGenFunction.cpp, clang/test/CIR/CodeGen amdgpu-stack-alloca-array-decay.cpp

[CIR][CIRGen] Cast stack allocas to the language-visible address space (#196868)

This patch aims to improve parity with OG codegen on targets with
non-flat alloca address space. I observed this after getting some
crashes while compiling PolybenchGpu for HIP (amdgpu). This work had
previously been merged in the incubator, most notably:
https://github.com/llvm/clangir/pull/2090,
https://github.com/llvm/clangir/pull/2088.

CIR currently returns the raw `cir.alloca` address from temporary/local
alloca creation. On AMDGPU, stack allocas live in private addrspace(5),
but ordinary C/C++/HIP auto variables are still used through the
language-visible generic/flat address space.

OG CodeGen handles this by creating the alloca in the target stack
address space and immediately casting it to the language-visible address
space when those differ. For example:

```llvm

    [11 lines not shown]
DeltaFile
+45-20clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+42-0clang/test/CIR/CodeGen/amdgpu-stack-alloca-array-decay.cpp
+9-9clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
+7-6clang/lib/CIR/CodeGen/CIRGenFunction.cpp
+11-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+8-1clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
+122-366 files not shown
+139-4712 files

LLVM/project 5610e5cllvm/include/llvm/IR Use.h User.h

[𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1
DeltaFile
+15-0llvm/include/llvm/IR/Use.h
+0-15llvm/include/llvm/IR/User.h
+15-152 files

LLVM/project cf7e148llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 non-schedulable-user-different-bb.ll non-schedulable-node-with-non-schedulable-parent.ll

[SLP]Bail out when copyable has cross-block reused non-schedulable user

When a copyable scalar in the bundle being scheduled has a same-block,
non-PHI, non-schedulable user with multiple uses, and at least one of
those uses is a non-PHI use in another block, the user's dependency
tracking across multiple bundles can be inconsistent.
Cancel scheduling of such copyable bundles instead.

Fixes #198364.

Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/198915
DeltaFile
+73-0llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-user-different-bb.ll
+10-13llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-node-with-non-schedulable-parent.ll
+18-0llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+101-133 files

LLVM/project 28112c8llvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/CodeGen/ARM atomic-load-store.ll

[AtomicExpand] Add bitcasts when expanding store atomic vector

AtomicExpand fails for aligned \`store atomic <n x T>\` because it
does not find a compatible library call. This change adds appropriate
ptrtoint + bitcast so that the call can be lowered, mirroring the
load-side handling from #148900.
DeltaFile
+99-6llvm/test/CodeGen/X86/atomic-load-store.ll
+98-0llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+49-0llvm/test/CodeGen/ARM/atomic-load-store.ll
+4-2llvm/lib/CodeGen/AtomicExpandPass.cpp
+250-84 files

LLVM/project 0d958f9llvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/Target/X86 X86InstrFragmentsSIMD.td X86InstrAVX512.td

[X86] Cast atomic vectors in IR to support floats

Extend the X86 \`alignedstore\` PatFrag to also match \`atomic_store\`
with vector-size alignment, so existing MOVAPS/MOVAPD/MOVDQA-family
aligned-store patterns cover 128-bit aligned vector atomic stores on
SSE/AVX/AVX-512 without per-type duplicates. \`<4 x float>\`,
\`<2 x double>\`, \`<2 x i64>\`, \`<4 x i32>\`, \`<8 x half>\`, \`<8 x bfloat>\`
all codegen to a single \`movaps\`/\`movapd\` on AVX+ via this.

Adds v8f16/v8bf16 bitconvert variants to the widen-path
\`atomic_store_32\` / \`atomic_store_64\` patterns so \`<2 x half>\`,
\`<2 x bfloat>\`, \`<4 x half>\`, \`<4 x bfloat>\` atomic stores reaching
the PR4 widen path also collapse to a single instruction on AVX+
targets.

Vectors whose \`getTypeAction\` is split rather than widen still rely
on PR6's \`SplitVecOp_ATOMIC_STORE\` — that path bitcasts the vector
to a scalar integer and issues an integer \`atomic_store_N\`, picked
up by the pre-existing scalar atomic-store patterns. The two

    [4 lines not shown]
DeltaFile
+86-0llvm/test/CodeGen/X86/atomic-load-store.ll
+5-4llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+3-2llvm/lib/Target/X86/X86InstrAVX512.td
+1-1llvm/include/llvm/Target/TargetSelectionDAG.td
+95-74 files

LLVM/project 98275c5llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Split vector types for atomic store

Vector types that aren't widened are split so that a single ATOMIC_STORE
is issued for the entire vector at once. This enables SelectionDAG to
translate vectors with type bfloat,half.
DeltaFile
+440-0llvm/test/CodeGen/X86/atomic-load-store.ll
+20-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+461-03 files

LLVM/project 7fb4fcfllvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/Target/X86 X86InstrSSE.td X86InstrAVX512.td

[X86] Remove extra MOV after widening atomic store

This change adds patterns to optimize out an extra MOV present after
widening the atomic store. Covers <2 x i8> (SSE4.1+), <2 x i16>,
<4 x i8>, <2 x i32>, <2 x float>, <4 x i16>, <2 x ptr addrspace(270)>.
DeltaFile
+47-64llvm/test/CodeGen/X86/atomic-load-store.ll
+30-24llvm/test/CodeGen/X86/atomic-unordered.ll
+35-0llvm/include/llvm/Target/TargetSelectionDAG.td
+10-10llvm/lib/Target/X86/X86InstrSSE.td
+6-6llvm/lib/Target/X86/X86InstrAVX512.td
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+129-1056 files

LLVM/project 63ef83cllvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Widen <2 x T> vector types for atomic store

Vector types of 2 elements must be widened. This change does this
for vector types of atomic store in SelectionDAG so that it can
translate aligned vectors of >1 size.
DeltaFile
+198-0llvm/test/CodeGen/X86/atomic-load-store.ll
+56-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+255-03 files

LLVM/project bc7894aclang/docs ReleaseNotes.rst

[Clang] [Docs] Remove stray release note (#198913)

The patch that added this release note was reverted (#198341), but then
(#198167) accidentally added it back.
DeltaFile
+0-3clang/docs/ReleaseNotes.rst
+0-31 files

LLVM/project 8a3f021clang/docs ReleaseNotes.rst, clang/include/clang/Sema Scope.h

[Clang] Disallow `break`/`continue` in loop conditions (#198436)

tl;dr: This makes e.g. `while (({ break; 1; })) {}` ill-formed.

GCC used to allow this a long time ago (< GCC 9 I believe), but
eventually removed support for it; we originally allowed this both for
GCC compatibility and because there was actual code in the wild using it
(see Richard’s comment here for more background:
https://github.com/llvm/llvm-project/pull/152606#issuecomment-3166130973).

Note that this _is_ still allowed inside another loop, e.g. this
```c++
for (;;) {
    while (({ break; true; })) {}
}
```
is well-formed; the `break` here will break out of the `for` loop.

Removing support for this gets rid of quite a bit of code and has a few

    [32 lines not shown]
DeltaFile
+114-0clang/test/Sema/break-continue-cond.c
+25-25clang/test/Sema/loop-control.c
+14-32clang/lib/Parse/ParseStmt.cpp
+12-24clang/include/clang/Sema/Scope.h
+0-35clang/lib/Sema/SemaStmt.cpp
+31-0clang/docs/ReleaseNotes.rst
+196-11610 files not shown
+228-21716 files

LLVM/project 671bb1fllvm/lib/CodeGen AtomicExpandPass.cpp, llvm/test/CodeGen/ARM atomic-load-store.ll

[AtomicExpand] Add bitcasts when expanding store atomic vector

AtomicExpand fails for aligned \`store atomic <n x T>\` because it
does not find a compatible library call. This change adds appropriate
ptrtoint + bitcast so that the call can be lowered, mirroring the
load-side handling from #148900.
DeltaFile
+99-6llvm/test/CodeGen/X86/atomic-load-store.ll
+98-0llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+49-0llvm/test/CodeGen/ARM/atomic-load-store.ll
+4-2llvm/lib/CodeGen/AtomicExpandPass.cpp
+250-84 files

LLVM/project 1d7267allvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/Target/X86 X86InstrFragmentsSIMD.td X86InstrAVX512.td

[X86] Cast atomic vectors in IR to support floats

Extend the X86 \`alignedstore\` PatFrag to also match \`atomic_store\`
with vector-size alignment, so existing MOVAPS/MOVAPD/MOVDQA-family
aligned-store patterns cover 128-bit aligned vector atomic stores on
SSE/AVX/AVX-512 without per-type duplicates. \`<4 x float>\`,
\`<2 x double>\`, \`<2 x i64>\`, \`<4 x i32>\`, \`<8 x half>\`, \`<8 x bfloat>\`
all codegen to a single \`movaps\`/\`movapd\` on AVX+ via this.

Adds v8f16/v8bf16 bitconvert variants to the widen-path
\`atomic_store_32\` / \`atomic_store_64\` patterns so \`<2 x half>\`,
\`<2 x bfloat>\`, \`<4 x half>\`, \`<4 x bfloat>\` atomic stores reaching
the PR4 widen path also collapse to a single instruction on AVX+
targets.

Vectors whose \`getTypeAction\` is split rather than widen still rely
on PR6's \`SplitVecOp_ATOMIC_STORE\` — that path bitcasts the vector
to a scalar integer and issues an integer \`atomic_store_N\`, picked
up by the pre-existing scalar atomic-store patterns. The two

    [4 lines not shown]
DeltaFile
+86-0llvm/test/CodeGen/X86/atomic-load-store.ll
+5-4llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+3-2llvm/lib/Target/X86/X86InstrAVX512.td
+1-1llvm/include/llvm/Target/TargetSelectionDAG.td
+95-74 files

LLVM/project 9f6ca39llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Split vector types for atomic store

Vector types that aren't widened are split so that a single ATOMIC_STORE
is issued for the entire vector at once. This enables SelectionDAG to
translate vectors with type bfloat,half.
DeltaFile
+440-0llvm/test/CodeGen/X86/atomic-load-store.ll
+20-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+461-03 files

LLVM/project 1613d11llvm/include/llvm/Target TargetSelectionDAG.td, llvm/lib/Target/X86 X86InstrSSE.td X86InstrAVX512.td

[X86] Remove extra MOV after widening atomic store

This change adds patterns to optimize out an extra MOV present after
widening the atomic store. Covers <2 x i8> (SSE4.1+), <2 x i16>,
<4 x i8>, <2 x i32>, <2 x float>, <4 x i16>, <2 x ptr addrspace(270)>.
DeltaFile
+47-64llvm/test/CodeGen/X86/atomic-load-store.ll
+30-24llvm/test/CodeGen/X86/atomic-unordered.ll
+35-0llvm/include/llvm/Target/TargetSelectionDAG.td
+10-10llvm/lib/Target/X86/X86InstrSSE.td
+6-6llvm/lib/Target/X86/X86InstrAVX512.td
+1-1llvm/lib/Target/X86/X86ISelLowering.cpp
+129-1056 files

LLVM/project 297678eflang/lib/Evaluate formatting.cpp, flang/lib/Semantics expression.cpp

Revert "[flang][PPC] Improve vector type names in expression diagnost… (#198908)

…ics (NFC…"

This reverts commit b387674b529fa137f3d0b05b93ee3712e39240e2.
DeltaFile
+0-15flang/test/Semantics/PowerPC/ppc-vector-diagnostics.f90
+1-3flang/lib/Semantics/expression.cpp
+0-3flang/lib/Evaluate/formatting.cpp
+1-213 files

LLVM/project a5dd368llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp LegalizeTypes.h, llvm/test/CodeGen/X86 atomic-load-store.ll

[SelectionDAG] Widen <2 x T> vector types for atomic store

Vector types of 2 elements must be widened. This change does this
for vector types of atomic store in SelectionDAG so that it can
translate aligned vectors of >1 size.
DeltaFile
+198-0llvm/test/CodeGen/X86/atomic-load-store.ll
+56-0llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+1-0llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+255-03 files

LLVM/project 5dd334cllvm/docs SphinxQuickstartTemplate.md GitHub.rst

Touch up migration, link to stacked pull request guide
DeltaFile
+3-3llvm/docs/SphinxQuickstartTemplate.md
+2-0llvm/docs/GitHub.rst
+5-32 files