[libc] Give struct sockaddr its full sa_data (#236518)
sa_data was one byte, with a comment saying it stood in for a longer
array, which made sizeof(struct sockaddr) four rather than sixteen. Code
sizes address buffers against that: the kernel's sockaddr_vm computes
its padding by subtracting the known fields from sizeof(struct
sockaddr), which underflowed to an array of 2^64 elements
A real address is passed as one of the per-family structures, so the
array only has to fix the size. Fourteen bytes is the size the kernel
and every other libc give it
AI disclosure: this patch was written with Claude Code. I reviewed the
change. There is no test since this is a type definition
Assisted-by: Claude
[CIR] Default the fenv attribute and elide it when empty
Floating-point operations carried `fenv` as an optional attribute, so an
attached `#cir.fenv<>` that set no field still printed as `fenv<>` and
lowered to a constrained intrinsic. Make `fenv` a default-valued attribute
whose default is the empty `#cir.fenv<>`: it does not constrain the
operation and is not printed. Codegen always sets every field of the fenv
it attaches, so its output is unchanged. Verifiers, folding, memory effects
and lowering now use the new `getConstrainedFenv()` interface method, which
returns null for the empty attribute. The custom builders that only passed
an empty fenv are dropped; the generated ones default it.
Assisted-by: Claude Code (Opus 5.5).
[CIR] Fix cir.try successor regions (#231449)
`TryOp::getSuccessorRegions` sent every exit from the try region back to
the parent, so nothing led from the try region to the handlers. A
`cir.resume` ending the try region, left there once FlattenCFG has
flattened an inner cleanup scope, unwinds into a handler, and
`CIRTryOpFlattening` branches it to the handler dispatch block. Most
handlers are entered by an unwind out of a call in the try region
instead, which is not a region branch point, so the edges from the
parent and from every try-region exit stand in for it. Without them,
generic MLIR passes treat such a handler as dead, and `cir-opt
-remove-dead-values` empties it. Take this try:
```mlir
cir.try {
cir.brcond %cond ^normal, ^unwind
^normal:
cir.call @may_throw() : () -> ()
cir.yield
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[CIR] Match classic codegen for saturating fixed-point negation and padded conversions
Three CIR fixed-point paths diverged from classic codegen. Unary minus on a
saturating fixed-point type emitted a plain subtraction instead of a
saturating 0 - x. With -fpadding-on-unsigned-fixed-point, float to unsigned
fixed-point conversion used fptoui and compared against 0 as unsigned, so the
clamp to 0 never fired; it now converts and clamps as signed, like
llvm::FixedPointBuilder. A saturating fixed-point conversion that kept the
width but changed signedness returned a value of the source CIR type, which
broke the cir.cmp verifier and needed a pointer bitcast to store; it now
casts to the destination type.
Assisted-by: Claude Code (Opus 5.5).
[mlir][tosa] Move RESCALE zero-point value checks from the verifier to tosa-validate (#234443)
Part of #233457.
Move the RESCALE input/output zero-point value constraints out of
`RescaleOp::verify()` into the `ERROR_IF` checks in `tosa-validate`,
matching the TOSA specification, where these are conformance rules
rather
than dialect well-formedness requirements.
- `TosaOps.cpp`: drop the zp value checks from `RescaleOp::verify()`;
type checks stay in the verifier.
- `TosaValidation.cpp`: add the same checks to `checkErrorIfRescale()`,
reusing the op's verify helpers, gated on `strict-op-spec-alignment`.
The accepted/rejected set and diagnostics are unchanged.
- `TosaToLinalg.cpp`: add a fail-closed backstop in `RescaleConverter`
so
conversion without validation rejects invalid zps instead of silently
lowering incorrect arithmetic.
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[mlir][tosa] Avoid copying profile compliance metadata (#232774)
Return compliance maps by const reference and pass matching inputs
through ArrayRef to avoid copying entire maps and nested type signatures
during validation.
[Clang][CodeGen] Update the TBAA info for potential aliases
The stores of a _Complex number were tagged as "unsigned long", but
loads were tagged as "float". TBAA reports no aliases if the store and
loads went through different pointers and GVN forwards a stale value.
Fix this by giving the "store" the "omnipotent char" tag, so that TBAA
treats it as aliasing every access to the destination's members. Using
that tag over "Dest.getTBAAInfo()" because it doesn't depend on how
CodeGenTBAA happens to tag struct and _Complex types.
Assisted-by: Claude for testcases.
[libc] Implement ether_aton and ether_aton_r (#235886)
The format is simple enough that I'm parsing it by hand. strtointeger is
not a particularly great fit as it also accepts leading whitespace and a
sign.
A few implementation notes:
- each octet can have one or two hex digits, so the output of ether_ntoa
("1:2:a:...") can be parsed back
- following musl (but unlike glibc), the address must not be followed by
any trailing characters, not even whitespace. glibc accepts trailing
whitespace (and ignores anything after it), and even garbage directly
after a two-digit final octet (e.g. "...:abfoo").
- the internal function does not take a string_view, as that would
require us to scan the entire string needlessly (we stop at the first
invalid character). In the worst case, the string might not be
terminated, and we'd crash trying to find the end.
- the output struct is not modified if parsing fails (glibc can leave it
partially written)
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[mlir][llvm] Add an op for the `llvm.vector.repeat` intrinsic (#236453)
Add an LLVM dialect op for `llvm.vector.repeat`, which repeats a
fixed-width vector to fill a scalable vector.
The LLVM intrinsic was introduced in:
https://github.com/llvm/llvm-project/pull/208212
[AMDGPU] Fix DPP combine when a mov feeds several REG_SEQUENCE lanes (#217902)
The subreg index came from the first operand reading the mov, so the
wrong operand was marked undef
Also skip lanes that other reads still use
[libc] Add a linux-x86_64-Release-Asserts fullbuild CI job (#236096)
Currently, none of the hosted Linux fullbuild CI jobs run tests with
assertions enabled: the Debug job only builds tests (`testing: BUILD`),
and the Release jobs build with `-DNDEBUG`. (The monolithic premerge
Linux job builds with `LLVM_ENABLE_ASSERTIONS=ON`, but only tests the
overlay configuration.)
This patch adds a new `linux-x86_64-Release-Asserts` job, which is the
same as `linux-x86_64-Release`, but with `LLVM_ENABLE_ASSERTIONS=ON`.
The new job doesn't build the fuzzing tests, as those are already
covered by
the regular Release job.
Assisted-by: Gemini
[clang][modules] Allow merging module-local class members across modules (#236509)
When the same variable template specialization is instantiated in two
module units and a TU imports both, clang merges the lambda closure
types (closure types are merged by identity), but not their `operator()`
members: the instantiated `operator()` is module-local to the
instantiating module, and `ASTContext::isSameEntity` refuses to merge
module-local declarations from different modules. The merged closure
type then has two `operator()` declarations that are not redeclarations
of each other, which is diagnosed as a false ODR violation during
deserialization.
The change allows merging class members across modules even when they
are marked module-local, provided that the (already checked) shared
declaration context is a class: a class definition determines its
members, so two members of the same class are the same entity. Two
*distinct* module-local classes are still not merged — the module-local
rule still applies to the classes themselves — so their members are
never compared, which is what that check exists for.
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[LoopPeel] Peel last iteration to enable load widening
In loops that contain multiple consecutive small loads (e.g., 3 bytes
loading i8's), peeling the last iteration makes it safe to read beyond
the accessed region, enabling the use of a wider load (e.g., b32) for
all other N-1 iterations.
Patterns such as:
```
%a = load i8, ptr %p
%b = load i8, ptr %p+1
%c = load i8, ptr %p+2
...
%p.next = getelementptr i8, ptr %p, 3
```
Can be transformed to:
```
%wide = load b32, ptr %p ; Read 4 bytes
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[Clang][CodeGen] Add support for _Complex arguments to "asm goto"
Clang emitted "=*r" for _Complex register outputs. On a callbr, the
SelectionDAG stores that output only on the fallthrough path, which
would silently skip adding a "store" on the indirect paths (#235940
turns that into an error). The HandleOutputConstraints method acceps
scalar and aggregate kinds, but not _Complex.
We fix this by treating a _Complex as an aggregate for this specific
case. The infrastructure already exists to handle {T, T} structs, so the
asm goto successor stores come for "free."
Fixes: 235946
Assisted-by: Claude for generating testcases
[mlir][Python] Fix defaulting type names without stub postprocessing
Use the package prefix in the Context and Location caster descriptions.
Generate extension stubs directly in their package and remove the text
rewrite step.
Signed-off-by: Twice <twice at apache.org>
[CIR] Fix cir.try successor regions
`TryOp::getSuccessorRegions` sent every exit from the try region back to the
parent, so nothing led from the try region to the handlers. A `cir.resume`
ending the try region, left there once FlattenCFG has flattened an inner
cleanup scope, unwinds into a handler, and `CIRTryOpFlattening` branches it
to the handler dispatch block. Now every exit from the try region can enter
the handlers, and a `cir.resume` leaves the op only when there are none. The
parent keeps its edges to the handlers. An unwind out of a call in the try
region is not a region branch point, so these edges stand in for it, and
without them -remove-dead-values empties a handler that is reached only that
way.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[AMDGPU] Enable SlotIndexes compaction by default
Add TargetRegisterInfo::shouldCompactSlotIndexes() so targets can opt
in to dropping dead SlotIndexes entries before greedy allocation, one
target at a time. An explicit -greedy-compact-slot-indexes still
overrides the target. Enable it for AMDGPU, where the leftover entries
skew live range priorities enough to cause heavy spilling.
[GlobalOpt] Skip use analysis for saturated function unnamed_addr (#236455)
For functions, `processGlobal()` only strengthens `unnamed_addr`: to
`unnamed_addr` for local linkage, or to `local_unnamed_addr` otherwise.
If the function already has that attribute or a stronger one, analyzing
its uses cannot lead to any change, so skip
`GlobalStatus::analyzeGlobal()`. Local functions with
`local_unnamed_addr` still need the analysis because they can be
upgraded to `unnamed_addr`.
This avoids redundant use-list walks observed while profiling large
Kotlin/Native builds.
Assisted-by: OpenAI Codex
[CIR] Keep cir.cleanup.scope cleanup regions reachable (#232217)
`getSuccessorRegions` must list every region that may run next. A
`cir.cleanup.scope` cleanup can also run from the middle of the body: on
an unwind out of a call, or on a `cir.return`, `cir.break`,
`cir.continue` or `cir.goto`. None of those is a region branch point, so
a cleanup reached only that way had no predecessor and generic MLIR
passes treated it as dead. For example, `cir-opt -remove-dead-values`
erased this whole scope, store included:
```mlir
cir.cleanup.scope {
cir.call @may_throw() : () -> ()
cir.yield
} cleanup eh {
%c = cir.const #cir.int<7> : !s32i
cir.store %c, %p : !s32i, !cir.ptr<!s32i>
cir.yield
}
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[Offload][Omp] Launch kernels through liboffload (#233735)
Launch kernels through olLaunchKernel. Stop using KernelLaunchArgsTy
from the PluginInterface and use ol_kernel_launch_size_args_t. Removed
unused Plugin and Device launch kernel interfaces.
OpenMP specific trip count information was still being passed through
KernelLaunchArgs only to be printed inside the AMD plugin. Moved the
print to libomptarget which allowed to remove the last OpenMP piece from
KernelLaunchArgsTy.
Tested on Intel and AMD GPUs.
Assisted by Claude.
[mlir] Move bufferization external models into their own libraries (#236459)
Prior to this PR the external models for `BufferizableOpInterface`,
`BufferDeallocationOpInterface`, `BufferViewFlowOpInterface` and
`AllocationOpInterface` lived in each dialect's Transforms library.
Every user of an unrelated transform therefore depended on the
Bufferization dialect and transforms.
This PR moves each model into its own `MLIR<Dialect><Interface>Impl`
library such that only users of those library requires dependent
libraries to be built. In particular, the Arith, ControlFlow, GPU,
MLProgram, SCF and Shape Transforms libraries no longer link
MLIRBufferizationDialect or MLIRBufferizationTransforms and
MLIRTensorTransforms no longer links MLIRLinalgDialect. This gives 104
targets a smaller link closure, e.g. MLIRControlFlowTransforms (-22
libraries), MLIRMLProgramTransforms (-20), MLIRSCFTransforms (-8) and
MLIRTensorTransforms (-7).
The Linalg model and the Func model in MLIRBufferizationTransforms stay
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[ARM] Ignore register tuples when emitting CodeView locations (#222347)
CodeView has register numbers for ARM's core, status, S, D and Q
registers, but none for the synthetic register tuples. A variable
assigned to one -- for example the odd-even D pair D1_D2 -- reached
getCodeViewRegNum and aborted the whole object file with "unknown
codeview register D1_D2".
Override isIgnoredCVReg for ARM so those registers are skipped, as
AArch64 already does for SVE Z and P registers. The variable is still
emitted and reports as optimized out. No register number would be
correct for a tuple, and naming one half of it would put the debugger in
the wrong place.
The check names the tuple register classes rather than treating every
unmapped register as ignorable, so a mapping that is genuinely missing
still reports an error instead of being dropped silently.
DPair contains the Q registers as well as the odd-even D pairs, so QPR
is excluded from the check; the qreg variable in the test is the control
that would catch losing them.
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