LLVM/project 2e1eb8allvm/test/CodeGen/SystemZ zos-ppa1-name.ll zos-ppa1.ll

[SystemZ][z/OS] Correctly align the constant pool and the PPA1

Both should be half-word aligned. However, testing revealed that
both can end up on odd addresses, which leads to relocation errors.
Fix is to change the alignment.
DeltaFile
+19-0llvm/test/CodeGen/SystemZ/zos-align-constpool.ll
+6-6llvm/test/CodeGen/SystemZ/zos-stack-protector.ll
+5-5llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
+4-4llvm/test/CodeGen/SystemZ/zos-ppa1.ll
+4-4llvm/test/CodeGen/SystemZ/zos-ppa1-argarea.ll
+1-1llvm/test/CodeGen/SystemZ/zos-ppa1-name.ll
+39-203 files not shown
+43-229 files

LLVM/project 43e82f2lldb/source/Commands CommandObjectType.cpp

[lldb] Remove ConstString from CommandObjectType interfaces (#218811)

CommandObjectType was creating ConstStrings type names, function names,
etc. before they needed to be. I'd like to remove ConstString from the
DataFormatter code entirely, so pushing the creation down as far as
possible first is a good first step.

The only remaining use (outside of function arguments) is
ScriptAddOptions. I need to understand it more before I can really
remove it.
DeltaFile
+55-58lldb/source/Commands/CommandObjectType.cpp
+55-581 files

LLVM/project de2a0ddllvm/utils/gn/secondary/clang/lib/CodeGen BUILD.gn, llvm/utils/gn/secondary/clang/lib/CodeGenUtils BUILD.gn

[gn build] Port commits (#222125)

9853cb54d9d2
b182b415d9b2
b90c062f3f03
e91092685eab
4c986c23921d
DeltaFile
+10-0llvm/utils/gn/secondary/clang/lib/CodeGenUtils/BUILD.gn
+1-1llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
+1-0llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
+1-0llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+1-0llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn
+15-16 files

LLVM/project cbbdbfcclang/test/Frontend optimization-remark-target-features-arm.c optimization-remark-target-features-aarch64.c, llvm/lib/CodeGen MachineFunction.cpp

[llc] add target-features optimization remark

In clang we have --print-enabled-extensions which will print the
AArch64 extensions enabled for a given TU. However, sometimes it is
useful to be able to print out the actual subtarget features for each
function, for debugging/testing purposes. Add an optimization remark
for that.
DeltaFile
+45-0llvm/test/CodeGen/AArch64/optimization-remark-target-features.ll
+30-0clang/test/Frontend/optimization-remark-target-features-aarch64.c
+30-0llvm/test/CodeGen/ARM/optimization-remark-target-features.ll
+19-0clang/test/Frontend/optimization-remark-target-features-arm.c
+17-0llvm/lib/CodeGen/MachineFunction.cpp
+1-1llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
+142-16 files

LLVM/project fee4360clang/include/clang/CIR/Dialect/IR CIRTypes.td, clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp

[CIR][NFC] Rewrite two comments based on reviewer feedback

Assisted-by: Cursor / claude-opus-5
DeltaFile
+4-10clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+3-7clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+7-172 files

LLVM/project 08add38llvm/lib/CodeGen MachineLICM.cpp, llvm/test/CodeGen/X86 machinelicm-hoist-before-succ-args.mir

MachineLICM: Fix preheader insertion point with SUCC_ARGS

Hoist loop-invariant instructions to getBlockEndInsertPt() instead of
getFirstTerminator(), so they land before the SUCC_ARGS cluster rather
than inside it.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+48-0llvm/test/CodeGen/X86/machinelicm-hoist-before-succ-args.mir
+2-2llvm/lib/CodeGen/MachineLICM.cpp
+50-22 files

LLVM/project 42c0fb1llvm/lib/CodeGen MachineCSE.cpp, llvm/test/CodeGen/PowerPC machine-cse-pre-succ-args.mir

CodeGen: Fix MachineCSE PRE insert point with SUCC_ARGS

Hoist to getBlockEndInsertPt() instead of getFirstTerminator(), so a hoisted
instruction lands before the SUCC_ARGS cluster rather than inside it.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+99-0llvm/test/CodeGen/PowerPC/machine-cse-pre-succ-args.mir
+1-1llvm/lib/CodeGen/MachineCSE.cpp
+100-12 files

LLVM/project 7024b9eclang/lib/CIR/CodeGen CIRGenExprScalar.cpp, clang/test/CIR/CodeGen vector-strict-fp.cpp

[CIR] Support fp strict for vector logical and, or ops (#221808)

Support fp strict for vector logical `cir.or` and `cir.and` ops
DeltaFile
+88-8clang/test/CIR/CodeGen/vector-strict-fp.cpp
+6-10clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
+94-182 files

LLVM/project b33a076llvm/include/llvm/CodeGen MachineBasicBlock.h, llvm/lib/CodeGen MachineVerifier.cpp

CodeGen: Add SUCC_ARGS pseudo-instruction

The sender half of a block-argument representation for Machine IR: a
"reverse PHI" that forwards values from a predecessor's bottom to a
successor block's arguments along one CFG edge. Operand 0 is the successor
block; the rest are the forwarded value registers, mapped positionally.

Like PHI, SUCC_ARGS is edge-specific: it must stay in its block, so it is
excluded from CSE and hoisting, and it defines no register but is not dead.
SUCC_ARGS are clustered contiguously immediately before the terminators,
mirroring how PHIs are clustered at the top of a block; the verifier
enforces this and the succ_args() range and getBlockEndInsertPt() let
consumers work with the cluster. Inert; no producer emits it yet.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+40-0llvm/test/CodeGen/MIR/X86/succ-args.mir
+38-0llvm/include/llvm/CodeGen/MachineBasicBlock.h
+34-0llvm/test/CodeGen/X86/machine-cse-succ-args.mir
+33-0llvm/test/MachineVerifier/X86/succ-args-empty.mir
+29-0llvm/test/CodeGen/X86/machinelicm-succ-args.mir
+27-0llvm/lib/CodeGen/MachineVerifier.cpp
+201-014 files not shown
+345-820 files

LLVM/project 19059d6llvm/lib/CodeGen MachineBasicBlock.cpp MachineVerifier.cpp, llvm/lib/CodeGen/MIRParser MIParser.cpp

CodeGen: Represent block arguments on MachineBasicBlock

The receiver half of the block-argument representation: a block declares a list
of virtual registers that receive values forwarded by each predecessor's
SUCC_ARGS. Unlike a PHI, a block argument is defined by the block itself, not by
an instruction.

MachineBasicBlock holds the argument list, printed and parsed as an "arguments:"
block header line. MachineRegisterInfo maps each argument to its defining block,
so getDefBlock works for these registers. The verifier treats an argument as
defined at block entry and requires each predecessor to supply one matching
SUCC_ARGS.

This is only building infrastructure, and is not yet used.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+131-0llvm/test/CodeGen/MIR/X86/block-args.mir
+53-0llvm/test/CodeGen/MIR/X86/block-args-invalid.mir
+48-2llvm/lib/CodeGen/MachineVerifier.cpp
+37-0llvm/lib/CodeGen/MIRParser/MIParser.cpp
+33-0llvm/lib/CodeGen/MachineBasicBlock.cpp
+32-0llvm/test/CodeGen/MIR/X86/block-args-named-blocks.mir
+334-213 files not shown
+539-619 files

LLVM/project 542ba89llvm/include/llvm/CodeGen MIRYamlMapping.h MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp MIRPrinter.cpp

CodeGen: Add UsesBlockArgs MachineFunction property

Bringup guard for block argument support.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+20-0llvm/test/CodeGen/MIR/X86/uses-block-args-property.mir
+3-1llvm/include/llvm/CodeGen/MachineFunction.h
+2-0llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+2-0llvm/include/llvm/CodeGen/MIRYamlMapping.h
+1-0llvm/lib/CodeGen/MachineFunction.cpp
+1-0llvm/lib/CodeGen/MIRPrinter.cpp
+29-16 files

LLVM/project f91b6a0llvm/lib/Target/PowerPC PPCVSXSwapRemoval.cpp, llvm/test/CodeGen/PowerPC vsx-swap-removal-undef.mir

PowerPC: Fix VSX swap removal crash on an undef register (#216714)

formWebs walks each vector-register use and unions its equivalence class
with that of its defining instruction, which it requires to be present
in the swap map. A use of an undef register has no defining instruction, so
the web formation crashed. Treat it like a physical-register mention so the
web is conservatively rejected.

Found by AI while working on something else.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+21-0llvm/test/CodeGen/PowerPC/vsx-swap-removal-undef.mir
+13-5llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
+34-52 files

LLVM/project ede01delibc/lib CMakeLists.txt

[libc] Generate a stub for libdl.a (#222098)

Avoid link errors when build rules explicitly add `-ldl` to the linker
invocation -
create an empty `libdl.a` static archive on Linux. It's necessary, for
example,
to build Clang (https://github.com/llvm/llvm-project/issues/97191) 

Follow the approach from f88e9de37a52abf9b269a7232bf4d4028bc4ace8
which added a similar stub for `libpthread.a`. Like pthread, dynamic
loader
functions (although they are mostly unimplemented in LLVM-libc as of
today)
are residing in the main `libc.a` archive instead.
DeltaFile
+1-1libc/lib/CMakeLists.txt
+1-11 files

LLVM/project 0f71c2dclang/test/OpenMP teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp, llvm/test/CodeGen/AArch64 arm64-big-endian-bitconverts.ll arm64-xaluo.ll

Merge branch 'main' into users/jmmartinez/build_shared_orc
DeltaFile
+4,997-0llvm/test/CodeGen/AArch64/overflow-vec.ll
+1,653-1,679llvm/test/CodeGen/AArch64/arm64-xaluo.ll
+1,299-431llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
+1,503-0llvm/test/CodeGen/AMDGPU/dpp_combine_rev_opcode.ll
+588-588clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+568-568clang/test/OpenMP/teams_distribute_parallel_for_simd_if_openmp52_codegen.cpp
+10,608-3,266242 files not shown
+18,769-7,841248 files

LLVM/project 220294cllvm/lib/Transforms/Vectorize VPlan.h

[VPlan] Remove VPWidenInductionRecipe::getStartValue (NFC). (#222015)

It now shadows VPHeaderPHIRecipe::getStartValue, which returns the same
VPValue and, as the base class accessor, also has a non-const overload.
Narrowing the return type to VPIRValue * was its only purpose.
DeltaFile
+0-3llvm/lib/Transforms/Vectorize/VPlan.h
+0-31 files

LLVM/project 4afa58elldb/source/Utility ArchSpec.cpp, lldb/unittests/Utility ArchSpecTest.cpp

[lldb] Fix infinite recursion in ArchSpec's core matching (#221899)

`target create` never returns for a little-endian 32-bit MIPS ELF file,
on any host whose platform advertises `armv7m`/`armv7em` compatibility.
On Darwin that is every platform, since
`PlatformDarwin::GetCompatibleArchs()`
lists both for every arm64/arm64e host and falls through to that same
list
for any other host core.  It is found by `lldb-target-fuzzer`.

Reproduce with a 52-byte ELF32 header (`ELFCLASS32`, `ELFDATA2LSB`,
`e_machine = EM_MIPS`, `e_flags = EF_MIPS_ARCH_32`, everything else
zero),
saved as `mips32el.elf`:

```
(lldb) target create mips32el.elf
```


    [62 lines not shown]
DeltaFile
+17-25lldb/source/Utility/ArchSpec.cpp
+40-0lldb/unittests/Utility/ArchSpecTest.cpp
+57-252 files

LLVM/project 6a77c91llvm/lib/Transforms/Vectorize VPlanRecipes.cpp, llvm/test/Transforms/LoopVectorize/AArch64 scalar-steps-cost.ll

[VPlan] Don't cost scalar IV steps if the vector body runs at most once. (#221974)

If the vector loop executes exactly once, each scalar IV step folds to a
constant, and there's nothing to cost.

Similarly to BranchOnCount and VPRegionBlock::cost, treat
VPScalarIVSteps as free in that case.

This fixes a slight inaccuracy introduced when moving to computing
VPScalarIVSteps costs in VPlan directly.

PR: https://github.com/llvm/llvm-project/pull/221974
DeltaFile
+5-0llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+1-1llvm/test/Transforms/LoopVectorize/AArch64/scalar-steps-cost.ll
+6-12 files

LLVM/project e4c2498llvm/lib/Target/SystemZ/MCTargetDesc SystemZHLASMAsmStreamer.cpp, llvm/test/CodeGen/SystemZ zos-ppa1.ll mixed-ptr-sizes.ll

[SystemZ][z/OS] Emit alignment in HLASM syntax

While trying to understand a crash, I noted that the emitted alignment
in HLASM is wrong. There are 2 issues:

 - The decision which suffix to use looks at `FillLen` instead of
   `Alignment`
 - The label alignment `DS 0H` is hard-coded

This change fixes the issues. To get the correct suffix for the
label alignment, the emission of the alignment is postponed in
certain cases, and the label definition picks up the alignment
suffix.
DeltaFile
+64-41llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+45-45llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+42-42llvm/test/CodeGen/SystemZ/call-zos-01.ll
+35-35llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
+17-17llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
+14-17llvm/test/CodeGen/SystemZ/zos-ppa1.ll
+217-19721 files not shown
+288-26227 files

LLVM/project 57e1aecoffload/plugins-nextgen/amdgpu/src rtl.cpp, offload/plugins-nextgen/common/include PluginInterface.h

implement feedback
DeltaFile
+5-4offload/plugins-nextgen/amdgpu/src/rtl.cpp
+3-1offload/plugins-nextgen/common/include/PluginInterface.h
+8-52 files

LLVM/project 37dd96fllvm/lib/Transforms/IPO AttributorAttributes.cpp, llvm/test/Transforms/Attributor indirect_call_program_address_space.ll

[Attributor] Compare an indirect call's callee in the program address space (#222097)

Specializing an indirect call emits, for each candidate callee, an
`icmp` between
the call's callee operand and the candidate. The operand was first
normalized to
address space 0, but the candidates are functions, and functions live in
the
target's program address space. Where that is not 0 the two sides of the
comparison had different types and the `icmp` asserted:

```
Instructions.h:1266: void llvm::ICmpInst::AssertOK(): Assertion
`getOperand(0)->getType() == getOperand(1)->getType() &&
"Both operands to ICmp instruction are not of the same type!"' failed.
```

Normalize to the program address space instead. It is 0 unless a target
says

    [17 lines not shown]
DeltaFile
+54-0llvm/test/Transforms/Attributor/indirect_call_program_address_space.ll
+9-3llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+63-32 files

LLVM/project 30cfec3llvm/test/CodeGen/AArch64 arm64-popcnt.ll arm64-big-endian-bitconverts.ll

[AArch64] Regenerate and update arm64-big-endian-bitconverts.ll. NFC (#222107)
DeltaFile
+1,299-431llvm/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
+1-1llvm/test/CodeGen/AArch64/arm64-popcnt.ll
+1,300-4322 files

LLVM/project b8d0491clang/include/clang/CIR/Dialect/IR CIRTypes.td, clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp

[CIR] Accept a union covered only by a bit-field's declared type

The size of a union is calculated by its largest member.  When that
member is a bit-field, the unit storing it can be narrower than the type
it was declared with, and it is the declared type that accounts for the
union's bytes.  BitFieldType gains a query for that declared type, and
the x86_64 union rule reads it rather than the stored size, so
`union { int x : 3; }` and `union { int x : 3; char c; }` now both pass
as i32.

A union larger than one eightbyte still needs a member covering it
outright, since the coerce basis skips the entry carrying the
declaration.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+172-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-union-bitfield.c
+124-0clang/test/CIR/Transforms/abi-lowering/x86_64-union.cir
+63-9clang/test/CIR/Transforms/abi-lowering/x86_64-aggregate-nyi.cir
+28-7clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+34-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-union-bitfield.cpp
+10-0clang/include/clang/CIR/Dialect/IR/CIRTypes.td
+431-161 files not shown
+439-167 files

LLVM/project 7945346offload/plugins-nextgen/amdgpu/src rtl.cpp, offload/plugins-nextgen/common/include PluginInterface.h

[OpenMP][offload] Add LIBOMPTARGET_KERNEL_EXE_TIME

If set to 1, prints kernel-specific execution time.

This is a port of the original downstream ROCm patch, extended with the
inclusion of the kernel name in the printed line.

Claude assisted with this patch.

Co-authored-by: Kewen Meng <kewen.meng at amd.com>
DeltaFile
+81-2offload/plugins-nextgen/amdgpu/src/rtl.cpp
+24-0offload/test/env/kernel_exe_time.c
+19-0offload/plugins-nextgen/common/include/PluginInterface.h
+124-23 files

LLVM/project 3ba57d1llvm/lib/Transforms/Scalar ConstraintElimination.cpp, llvm/test/Transforms/ConstraintElimination induction-condition-in-loop-exit-postinc.ll header-induction-start-bounds.ll

[ConstraintElim] Support IV increments via [u|s]add.with.overflow. (#221771)

Treat [u|s]add.with.overflow like plain add when looking for increment
of an IV. We do not retrieve any wrap flags from the IR in that case, and
leave it to SCEV to determine them as needed.

This did not show any improvements on the workloads in
llvm-opt-benchmark-nightly, but helps to remove runtime checks for Swift
code end-to-end (see newly added PhaseOrdering test).

Alive2 Proof: https://alive2.llvm.org/ce/z/o2vMyw

PR: https://github.com/llvm/llvm-project/pull/221771
DeltaFile
+543-0llvm/test/Transforms/ConstraintElimination/header-induction-start-bounds.ll
+415-0llvm/test/Transforms/ConstraintElimination/induction-condition-in-loop-exit-postinc.ll
+124-0llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
+17-5llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+1,099-54 files

LLVM/project 31cb39eflang/lib/Semantics check-omp-structure.h check-omp-variant.cpp, flang/test/Semantics/OpenMP metadirective-loop-applicability.f90

Remove redundant handling, improve style, and add documentation
DeltaFile
+13-21flang/lib/Semantics/check-omp-variant.cpp
+8-4flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
+6-4flang/lib/Semantics/check-omp-structure.h
+4-3llvm/lib/Frontend/OpenMP/OMPContext.cpp
+31-324 files

LLVM/project 1a4e4cbllvm/runtimes CMakeLists.txt

[compiler-rt] Add llvm-link deps when building compiler-rt builtins for spirv64 targets (#221906)

https://github.com/llvm/llvm-project/pull/214149 uses llvm-link to
create libclang_rt.builtins.bc from static archive library. It is better
to follow libclc approach to add llvm-link dependency for
builtin-spirv64* in llvm runtime CMakeLists.txt.

Signed-off-by: jinge90 <ge.jin at intel.com>
DeltaFile
+8-1llvm/runtimes/CMakeLists.txt
+8-11 files

LLVM/project 3ff772bflang/lib/Semantics check-omp-variant.cpp, flang/test/Semantics/OpenMP metadirective-ordered-paths.f90 metadirective-loop-applicability.f90

Fix extension matching and reachable path merging

Metadirective semantic checking relies on ranked selection to decide which
replacements need validation. With match_any and match_none, a selector can
remain applicable even when some construct traits are absent. The existing
matching and path-merging assumptions do not fully account for this, so
ranking can crash or discard a reachable replacement, allowing invalid loop
nests to pass unchecked.

Make applicability, scoring, and reachable-path merging agree on what these
matching extensions can observe. Preserve enough construct context to rank
partially matching selectors and distinguish paths whose nesting changes
the selected replacement. That context must also remain visible inside a
BLOCK associated with a selected directive, so nested metadirectives are
checked against the context in which they can execute.
DeltaFile
+53-33flang/lib/Semantics/check-omp-variant.cpp
+47-34llvm/lib/Frontend/OpenMP/OMPContext.cpp
+71-0flang/test/Semantics/OpenMP/metadirective-match-any-paths.f90
+68-0flang/test/Semantics/OpenMP/metadirective-loop-applicability.f90
+65-1llvm/unittests/Frontend/OpenMPContextTest.cpp
+45-0flang/test/Semantics/OpenMP/metadirective-ordered-paths.f90
+349-686 files

LLVM/project bc37989llvm/test/CodeGen/RISCV convert-to-arbitrary-fp.ll

fixup! nounwind
DeltaFile
+8-56llvm/test/CodeGen/RISCV/convert-to-arbitrary-fp.ll
+8-561 files

LLVM/project f749e1dllvm/lib/CodeGen/SelectionDAG TargetLowering.cpp, llvm/test/CodeGen/RISCV convert-to-arbitrary-fp.ll

[SelectionDAG] Fix incorrect expansion of `CONVERT_TO_ARBITRARY_FP`
DeltaFile
+826-0llvm/test/CodeGen/RISCV/convert-to-arbitrary-fp.ll
+49-12llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+875-122 files

LLVM/project 49d09aallvm/include/llvm/CodeGen SelectionDAG.h, llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp LegalizeDAG.cpp

[SelectionDAG][NFC] Move EmitStackConvert from LegalizeDAG to SelectionDAG (#221357)

I've ran into multiple instances, include #221358 , where I need to
effectively "bitcast" an integer value to a floating point value with
different width (and vice versa). To my best understandings storing into
stack and loading back is the only feasible way. LegalizeDAG already has
this routine, so I thought it might be a good idea to extract it out and
put inside SelectionDAG.

NFC.
DeltaFile
+2-35llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+36-0llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+7-0llvm/include/llvm/CodeGen/SelectionDAG.h
+45-353 files