LLVM/project 9afb651clang/include/clang/AST OpenMPClause.h, clang/lib/AST OpenMPClause.cpp

Adding support for iterator in motion clauses. (#159112)

As described in section 2.14.6 of openmp spec, the patch implements
support for iterator in motion clauses.

---------

Co-authored-by: Shashwathi N <nshashwa at pe31.hpc.amslabs.hpecorp.net>
DeltaFile
+27-17clang/include/clang/AST/OpenMPClause.h
+26-16clang/lib/Sema/SemaOpenMP.cpp
+24-14clang/lib/AST/OpenMPClause.cpp
+28-10clang/lib/Sema/TreeTransform.h
+35-0clang/test/OpenMP/target_update_iterator_serialization.cpp
+21-12clang/lib/Parse/ParseOpenMP.cpp
+161-698 files not shown
+239-7214 files

LLVM/project 05b1989mlir/lib/Conversion/ArithToAPFloat ArithToAPFloat.cpp, mlir/lib/ExecutionEngine APFloatWrappers.cpp

[mlir][arith] Add support for `negf` to `ArithToAPFloat` (#169759)

Add support for `arith.negf`.
DeltaFile
+45-2mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
+10-0mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
+9-0mlir/lib/ExecutionEngine/APFloatWrappers.cpp
+4-0mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
+68-24 files

LLVM/project 96bf22coffload/include/OpenMP omp.h

add comment
DeltaFile
+1-0offload/include/OpenMP/omp.h
+1-01 files

LLVM/project 316d2f8mlir/lib/Conversion/ArithToAPFloat ArithToAPFloat.cpp, mlir/lib/ExecutionEngine APFloatWrappers.cpp

[mlir][arith] Add support for `negf` to `ArithToAPFloat`
DeltaFile
+45-2mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
+10-0mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
+9-0mlir/lib/ExecutionEngine/APFloatWrappers.cpp
+4-0mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
+68-24 files

LLVM/project f67b018mlir/test/Conversion/UBToSPIRV ub-to-spirv.mlir

[mlir][SPIRV] Improve ub.unreachable lowering test case (#170083)

Addresses a comment on the PR that introduces the ub.reachable ->
spriv.Unreachable lowering
(https://github.com/llvm/llvm-project/pull/169872#discussion_r2573670611).
DeltaFile
+9-7mlir/test/Conversion/UBToSPIRV/ub-to-spirv.mlir
+9-71 files

LLVM/project 7ce7141mlir/lib/Dialect/Linalg/Utils Utils.cpp

[NFC][Linalg] Follow-up on ConvMatchBuilder (#170080)

-- This commit addresses [follow-up review comments on
169704](https://github.com/llvm/llvm-project/pull/169704#pullrequestreview-3521785548).
-- Contains NFC nit/minor changes.

Signed-off-by: Abhishek Varma <abhvarma at amd.com>
DeltaFile
+85-71mlir/lib/Dialect/Linalg/Utils/Utils.cpp
+85-711 files

LLVM/project 17677adllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize iv_outside_user.ll

[LV] Don't create WidePtrAdd recipes for scalar VFs (#169344)

While attempting to remove the use of undef from more loop vectoriser
tests I discovered a bug where this assert was firing:

```
llvm::Constant* llvm::Constant::getSplatValue(bool) const: Assertion `this->getType()->isVectorTy() && "Only valid for vectors!"' failed.
...
 #8 0x0000aaaab9e2fba4 llvm::Constant::getSplatValue
 #9 0x0000aaaab9dfb844 llvm::ConstantFoldBinaryInstruction
```

This seems to be happening because we are incorrectly generating
WidePtrAdd recipes for scalar VFs. The PR fixes this by checking whether
a plan has a scalar VF only in legalizeAndOptimizeInductions.

This PR also removes the use of undef from the test `both` in
Transforms/LoopVectorize/iv_outside_user.ll, which is what started
triggering the assert.

Fixes #169334
DeltaFile
+93-46llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+2-1llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+95-472 files

LLVM/project 4d7abe5mlir/lib/Conversion/ArithToAPFloat ArithToAPFloat.cpp, mlir/lib/ExecutionEngine APFloatWrappers.cpp

[mlir][arith] Add support for `cmpf` to `ArithToAPFloat` (#169753)

Add support for `arith.cmpf`.
DeltaFile
+147-5mlir/lib/Conversion/ArithToAPFloat/ArithToAPFloat.cpp
+15-0mlir/test/Conversion/ArithToApfloat/arith-to-apfloat.mlir
+11-0mlir/lib/ExecutionEngine/APFloatWrappers.cpp
+4-0mlir/test/Integration/Dialect/Arith/CPU/test-apfloat-emulation.mlir
+177-54 files

LLVM/project 9b86aefmlir/test/Conversion/UBToSPIRV ub-to-spirv.mlir

[mlir][SPIRV] Improve ub.unreachable lowering test case
DeltaFile
+9-7mlir/test/Conversion/UBToSPIRV/ub-to-spirv.mlir
+9-71 files

LLVM/project a751ed9bolt/include/bolt/Core BinaryContext.h, bolt/include/bolt/Rewrite RewriteInstance.h

[BOLT] Support runtime library hook via DT_INIT_ARRAY (#167467)

Major part of this PR is commit implementing support for DT_INIT_ARRAY
for BOLT runtime libraries initialization. Also, it adds related
hook-init test & fixes couple of X86 instrumentation tests.

This commit follows implementation of instrumentation hook via
DT_FINI_ARRAY (https://github.com/llvm/llvm-project/pull/67348) and
extends it for BOLT runtime libraries (including instrumentation
library) initialization hooking.

Initialization has has differences compared to finalization:
- Executables always use ELF entry point address. Update code checks it
and updates init_array entry if ELF is shared library (have no interp
entry) and have no DT_INIT entry. Also this commit introduces
"runtime-lib-init-hook" option to select primary initialization hook
(entry_point, init, init_array) with fall back to next available hook in
input binary. e.g. in case of libc we can explicitly set it to
init_array.

    [7 lines not shown]
DeltaFile
+212-21bolt/lib/Rewrite/RewriteInstance.cpp
+221-0bolt/test/AArch64/hook-init.s
+221-0bolt/test/X86/hook-init.s
+11-3bolt/test/AArch64/hook-fini.s
+10-1bolt/include/bolt/Rewrite/RewriteInstance.h
+9-0bolt/include/bolt/Core/BinaryContext.h
+684-253 files not shown
+708-269 files

LLVM/project bbb0dbaclang/include/clang/AST Decl.h, clang/lib/AST ExprConstant.cpp ComparisonCategories.cpp

[clang][AST] Add `RecordDecl::getNumFields()` (#170022)

Not sure why that didn't exist yet, but we have quite a few places using
the same `std::distance` pattern.
DeltaFile
+8-11clang/lib/AST/ExprConstant.cpp
+2-4clang/lib/CodeGen/CGHLSLRuntime.cpp
+5-0clang/include/clang/AST/Decl.h
+1-2clang/lib/Sema/CodeCompleteConsumer.cpp
+1-1clang/lib/AST/ComparisonCategories.cpp
+17-185 files

LLVM/project 622e7bdmlir/include/mlir/Dialect/OpenMP OpenMPClauses.td, mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

Comments fix
DeltaFile
+2-1mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+1-1mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
+3-22 files

LLVM/project dc5ce79llvm/test/Transforms/LoopVectorize struct-return.ll

[LV] Regenerate some check lines. NFC

The scalar loop doesn't exist anymore after 8907b6d39371d439461cdd3475d5590f87821377
DeltaFile
+16-12llvm/test/Transforms/LoopVectorize/struct-return.ll
+16-121 files

LLVM/project 9416b19llvm/lib/Transforms/InstCombine InstCombineSelect.cpp, llvm/test/Transforms/InstCombine saturating-add-sub.ll

[InstCombine] Add missing constant check (#170068)

`cast<Constant>` is not guarded by a type check during canonicalization
of predicates. This patch adds a type check in the outer if to avoid the
crash. `dyn_cast` may introduce another nested if, so I just use
`isa<Constant>` instead.

Address the crash reported in
https://github.com/llvm/llvm-project/pull/153053#issuecomment-3593914124.
DeltaFile
+16-0llvm/test/Transforms/InstCombine/saturating-add-sub.ll
+1-0llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+17-02 files

LLVM/project 036279alldb/tools/debugserver/source DNB.cpp, lldb/tools/debugserver/source/MacOSX MachProcess.mm MachProcess.h

[lldb][debugserver] Return shared cache filepath in jGetSharedCacheInfo (#168474)

Add a "shared_cache_path" key-value to the jGetSharedCacheInfo response,
if we can fetch the shared cache path.

If debugserver and the inferior process are running with the same shared
cache UUID, there is a simple SPI to get debugserver's own shared cache
filepath and we will return that.

On newer OSes, there are SPI we can use to get the inferior process'
shared cache filepath, use that if necessary and the SPI are available.

The response for the jGetSharedCacheInfo packet will now look like


{"shared_cache_base_address":6609256448,"shared_cache_uuid":"B69FF43C-DBFD-3FB1-B4FE-A8FE32EA1062","no_shared_cache":false,"shared_cache_private_cache":false,"shared_cache_path":"/System/Volumes/Preboot/Cryptexes/OS/System/Library/dyld/dyld_shared_cache_arm64e"}

when we have the full information about the shared cache in the
inferior. There are three possible types of responses:

    [16 lines not shown]
DeltaFile
+121-4lldb/tools/debugserver/source/MacOSX/MachProcess.mm
+13-1lldb/tools/debugserver/source/MacOSX/MachProcess.h
+1-1lldb/tools/debugserver/source/DNB.cpp
+135-63 files

LLVM/project 5eb1e66llvm/lib/Target/AMDGPU AMDGPURewriteAGPRCopyMFMA.cpp AMDGPURewriteAGPRCopyMFMA.h, llvm/unittests/Target/AMDGPU AMDGPURewriteAGPRCopyMFMATest.cpp CMakeLists.txt

[AMDGPU] Verify dominance when rewriting spills to registers

Rev1: Updated condition to check for "joint domination", i.e. no reload
is reachable from entry without reaching a store to the same slot. Still
working on reduced test or unit test.

When performing spill elimination in the AGPR copy rewrite pass it was
possible to see spill reloads that were not jointly dominated by any
store. This caused invalid MIR to be generated where vreg uses were not
dominated by defs. This patch adds a joint dominance check before
rewriting spills.
DeltaFile
+196-0llvm/unittests/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMATest.cpp
+110-4llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+32-0llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.h
+1-0llvm/unittests/Target/AMDGPU/CMakeLists.txt
+339-44 files

LLVM/project 095badfllvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/lib/Target/SPIRV SPIRVBuiltins.cpp

actually fix windows build

Created using spr 1.3.7
DeltaFile
+798-0llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
+254-0llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
+73-0llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+45-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+32-0llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+28-0mlir/test/Dialect/Affine/loop-coalescing.mlir
+1,230-121 files not shown
+1,355-4027 files

LLVM/project 81c5d46mlir/lib/Dialect/LLVMIR/IR NVVMDialect.cpp, mlir/test/Dialect/LLVMIR nvvm-target-invalid.mlir

[MLIR][NVVM] Propagate verification failure for unsupported SM targets (#170001)

Fixes: https://github.com/llvm/llvm-project/issues/169113

Correctly propagate verification failure when
`NVVM::RequiresSMInterface` check fails during `gpu.module`
verification.
Previously, the walk was interrupted but the function returned
`success()`, causing a mismatch between the emitted diagnostic and the
return status. This led to assertion failures in Python bindings which
expect `failure()` when diagnostics are emitted.

CC: @grypp
DeltaFile
+14-10mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+11-0mlir/test/Dialect/LLVMIR/nvvm-target-invalid.mlir
+25-102 files

LLVM/project 602639cllvm/unittests/CAS CASTestConfig.h

Fix missing header on windows

Created using spr 1.3.7
DeltaFile
+1-0llvm/unittests/CAS/CASTestConfig.h
+1-01 files

LLVM/project 8a17fd7llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[AMDGPU][NPM] Enable SIModeRegister and SIInsertHardclauses passes
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+5-52 files

LLVM/project 5eefe1fllvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp

review comment
DeltaFile
+1-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-21 files

LLVM/project 68c9eb1llvm/lib/Target/AMDGPU SIShrinkInstructions.cpp

clang-format
DeltaFile
+5-3llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+5-31 files

LLVM/project 7b56e30llvm/lib/Target/AMDGPU SIShrinkInstructions.cpp

[AMDGPU] Make SIShrinkInstructions pass return valid changed state
DeltaFile
+60-35llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+60-351 files

LLVM/project 2136cffllvm/include/llvm/Passes CodeGenPassBuilder.h, llvm/test/CodeGen/AMDGPU llc-pipeline-npm.ll

[NPM] Schedule PhysicalRegisterUsageAnalysis before RegUsageInfoCollectorPass
DeltaFile
+3-3llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
+3-1llvm/include/llvm/Passes/CodeGenPassBuilder.h
+6-42 files

LLVM/project e218140llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV rvp-ext-rv32.ll rvp-ext-rv64.ll

[RISCV][llvm] Correct shamt in P extension EXTRACT_VECTOR_ELT lowering (#169823)

During operation legalization, element type should have been turn into
XLenVT which makes the SHL a no-op. We need to use exact vector element
type instead.
DeltaFile
+32-0llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+12-0llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+1-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+45-13 files

LLVM/project 6369279llvm/docs LangRef.rst, llvm/include/llvm/CodeGen ISDOpcodes.h

Revert "Revert "LangRef: Clarify llvm.minnum and llvm.maxnum about sNaN and signed zero (#112852)"" (#170067)

Reverts llvm/llvm-project#168838

Justification is confused and this did not receive adequate discussion,
particularly during a holiday week
DeltaFile
+56-54llvm/docs/LangRef.rst
+15-5llvm/include/llvm/CodeGen/ISDOpcodes.h
+71-592 files

LLVM/project 7494f3dllvm/docs SPIRVUsage.rst, llvm/lib/Target/SPIRV SPIRVBuiltins.cpp SPIRVInstrInfo.td

[SPIRV] Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point and name change of SPV_INTEL_arbitrary_precision_integers to SPV_ALTERA_arbitrary_precision_integers  (#136085)

--Added support for extension SPV_ALTERA_arbitrary_precision_fixed_point
--Added test files for extension
SPV_ALTERA_arbitrary_precision_fixed_point
DeltaFile
+254-0llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
+73-0llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+24-0llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+21-0llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+14-0llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+8-5llvm/docs/SPIRVUsage.rst
+394-514 files not shown
+433-3820 files

LLVM/project f5bd5bfllvm/docs LangRef.rst, llvm/include/llvm/CodeGen ISDOpcodes.h

Revert "Revert "LangRef: Clarify llvm.minnum and llvm.maxnum about sNaN and s…"

This reverts commit 75aa01b89553bf4213a3b0e83829b6d0689941b9.
DeltaFile
+56-54llvm/docs/LangRef.rst
+15-5llvm/include/llvm/CodeGen/ISDOpcodes.h
+71-592 files

LLVM/project 2e21bb8llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV zicond-fp-select-zfinx.ll

[RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx (#169299)

### Summary

This patch let RISCVTargetLowering::lowerSELECT to lower some
floating-point select operations through an integer zicond select when:
* Zicond is available, and 
* FP values live in GPRs (Zfinx/Zdinx), and
* Select condition is an integer type.

In that scenario there is no extra cost for GPR <-> "FP GPR" moves, so
we can implement FP selects with a CZERO-based sequence instead of a
branch.

For example, for  
```c
float foo(int cond, float x) {
    return (cond != 0) ? x : 0.0f;
}

    [42 lines not shown]
DeltaFile
+798-0llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
+44-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+842-02 files

LLVM/project e110abcmlir/lib/Dialect/Affine/Utils LoopUtils.cpp, mlir/test/Dialect/Affine loop-coalescing.mlir

[mlir][affine] Use iter argument replace init when delete loop in the coalesceLoops function (#169514)

Fix https://github.com/llvm/llvm-project/issues/169483 by using iter
argument replace init when delete loop in the coalesceLoops function.
DeltaFile
+28-0mlir/test/Dialect/Affine/loop-coalescing.mlir
+6-0mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
+34-02 files