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[gn] port b11722f1d3bd5de (llvm-calc-occupancy) (#213266)

[flang] Delete the legacy array-value operations from FIR (#213159)

Nothing in flang has produced fir.array_load, fir.array_fetch,
fir.array_update, fir.array_modify, fir.array_access, fir.array_amend,
or fir.array_merge_store since the legacy (non-HLFIR) expression
lowering was deleted (#210385, #210621, #210639, #210873), and the
array-value-copy pass that legalized them is gone (#211816, #212643).
Delete the operations and the surface that existed only for them:

- FIROps.td: the "Array value operations" section including the
copy-in/copy-out design comment; FIROps.cpp: the ops verifiers, effects
and getExtents. fir.array_coor is unrelated and stays, as does the
validTypeParams helper shared with fir.pack_array.
- Tests: the ops roundtrip/verifier blocks in fir-ops.fir and
invalid.fir; scaffolding rewrites in inline-elemental.fir (store via
hlfir.designate; hlfir.apply-in-do_loop coverage preserved),
loop-versioning.fir @test4 (the versioned loops are untouched), and
simplifyintrinsics.fir (inert copy-back loops dropped; no CHECK lines
affected).

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[Build] Fix llvm-calc-occupancy link errors when using LLVM_LINK_LLVM_DYLIB. (#213262)

[libc++][NFC] Make size_t -> int conversions explicit in a few PSTL tests (#213145)

The implicit truncating conversions that were introduced in some PSTL
tests are causing warnings on MSVC. This PR fixes that.

See
https://github.com/llvm/llvm-project/pull/212366#discussion_r3679252259
for more details.

[mlir][linalg] Support non-unit dilations in im2col decomposition (#208424)

The im2col patterns for conv_2d_nhwc_hwcf, conv_2d_nchw_fchw and
conv_2d_nhwc_fhwc avoided non-unit dilations, but the restriction
doesn't seem to be fundamental: dilation only affects the gather step,
which can fold it into its indexing map. Generalize the convolved index
expression from `oh * stride + fh` to `oh * stride + fh * dilation` and
drop the match failures.

Verified by comparing the results of a dilated convolution lowered
directly to loops against the im2col decomposition with mlir-runner.

Assisted-By: Claude Code (for generating tests).

AMDGPU: Add missing msad-insts to gfx13 frontend feature map (#213122)

fillAMDGCNFeatureMap omitted msad-insts for gfx1310/gfx13-generic, so
clang wrongly rejected __builtin_amdgcn_msad_u8 on those targets even
though the backend enables the feature (FeatureGFX9 generation,
inherited through FeatureGFX13). Add it to the gfx13 case.

Co-authored-by: Claude (Claude-Opus-4.8)

[lldb-dap] Migrate console and restart tests (#213019)

Migrated Tests
- TestDAP_console.py
- TestDAP_redirection_to_console.py
- TestDAP_restart.py
- TestDAP_restart_console.py

[lldb][Windows] Don't cut the loader helper off after 250ms (#213010)

`LoadLibraryW` runs on the debuggee with a timeout of 250ms (the
default). On a loaded machine (in CI), this timeout is reached quite
often, causing tests failures.

This patch gives both loader helpers an explicit timeout of 5s (clamped
to half the overall timeout so the two stay consistent).

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7

[libsycl] Add missing header include to global_objects.hpp (#213020)

Fixes a build error observed on Windows.

[lld][MachO] Preserve class-address addends in ObjC category merging (#211431)

Mach-O category merging can encounter Swift class references as an
enclosing
metadata symbol plus a non-zero addend after LTO removes the exact
class-address alias. For example, a category can refer to a `CMf` symbol
plus
the offset of the class object within that metadata record.

`tryGetSymbolAtIsecOffset()` previously resolved such a relocation to
the
enclosing symbol and discarded the residual addend. `getClassRo()` then
read
the class layout at the wrong address. For valid Swift metadata this can
return
null; before the defensive check in the first commit the linker
dereferenced
that result and crashed, while the check alone safely skipped a category
that

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[clang][Analysis] Add argument accessors to clang::AnyCall (#212934)

Add APIs to `clang::AnyCall` for accessing expression-backed call
arguments.

`AnyCall` already exposes formal parameters through `parameters()`,
`param_begin()`, `param_end()`, `param_size()`, and `param_empty()`.
This adds the corresponding argument-side helpers:

- `arguments()`
- `arg_begin()`
- `arg_end()`
- `arg_size()`
- `arg_empty()`
- `getArg()`

This lets clients reuse `AnyCall` for callee/argument inspection instead
of
open-coding argument extraction.

Prequel PR to #206337

[SLP][NFC]Add some extra tests for reductions, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/213257

DAG: Use poison for some load/store offsets in legalizer

Unindexed load/store offsets are a don't-care operand that must be poison
rather than undef now that poison is legal. Convert the remaining producers
that build the offset with getUNDEF (in SelectionDAGBuilder and the ARM,
Hexagon, RISCV, and X86 lowerings) to getPOISON, and strengthen the offset
asserts in the SelectionDAG memory-node builders to require POISON exactly
instead of accepting any undef-or-poison value.

Co-Authored-By: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

[AMDGPU] Lower LDS flat round trips without provenance analysis

[libc++abi] Add a clang-tidy config and test (#207324)

This essentially copies the `.clang-tidy` file from libc++ into
libc++abi, except that the naming conventions are updated to not add
underscores and some checks are disabled that don't pass currently. They
will be fixed in follow-ups.

[libc++] Simplify clear_padding.h a bit (#212426)

[libc++] Make __has_array_cookie a variable template (#212767)

Using variable templates is slightly faster to compile and more
readable, so we might as well use them.

[NFC][PowerPC] add more `copysign` tests (#213236)

AMDGPU: Do not give gfx12.5 bvh-ray-tracing-insts

bvh-ray-tracing-insts was listed in the FeatureGFX12 generation, so
gfx1250/gfx1251/gfx12-5-generic inherited it even though they have no BVH.
Move the feature out of the common base and into FeatureISAVersion12, which
This stops clang from wrongly accepting __builtin_amdgcn_image_bvh_intersect_ray*
on gfx1250.

Co-authored-by: Claude (Claude-Opus-4.8)

[ORC] Add VoidVoid and IntVoid Callers, with tests. (#213211)

Add rt::VoidVoidCaller (void()) and rt::IntVoidCaller (int64_t())
runtime-agnostic interfaces and their rt::sps implementations, targeting
the orc_rt_ci_sps_call_void_void and orc_rt_ci_sps_call_int_void
controller-interface wrappers. Both are experimental and may be removed.

Extend SPSCallersTest to cover the new callers. VoidVoidCaller is the
first caller instantiated with a void result type, which exposed a
latent bug in sps::Caller::callAsync: its result handler declared a
CalleeRetT parameter, ill-formed when CalleeRetT is void. It now
special-cases void via `if constexpr`.

Address review comments

[VPlan] Remove redundant x && (y && x) -> x && y combine (#213219)

It can be subsumed by making the combine above commutative. In theory
this isn't NFC as it changes the order, in practice it doesn't make a
difference.

[TableGen] Speed up intrinsic lookups with DenseMap (NFC) (#213198)

Store in DenseMap, avoids linear lookups.
Speeds up NVPTX -gen-dag-isel and -gen-instr-info by 10%.
RISCV shows similar gains.
Neutral or marginally beneficial for other targets.

AMDGPU: Add missing msad-insts to gfx13 frontend feature map

fillAMDGCNFeatureMap omitted msad-insts for gfx1310/gfx13-generic, so
clang wrongly rejected __builtin_amdgcn_msad_u8 on those targets even
though the backend enables the feature (FeatureGFX9 generation, inherited
through FeatureGFX13). Add it to the gfx13 case.

Co-authored-by: Claude (Claude-Opus-4.8)

[LLVM][CodeGen][SVE] Use pairwise instruction for partial_reduce_[s/u]mla. (#212772)

[MachineLICM] Use `RegisterClassInfo::getRegPressureSetLimit` (#211715)

This recommits #119826, which taught `MachineLICM` to use
`RegisterClassInfo` when computing register pressure limits so
reserved registers are accounted for (#118787).

The original change was reverted by eeac0ff because it increased
compile time by causing repeated `RegisterClassInfo` computations.

This PR is based on #210826, in which `MachineRegisterClassInfo`
analysis pass was added. `MachineRegisterClassInfo` is required
by `MachineLICM` now, but the intervening machine passes that do
not affect `RegisterClassInfo` now preserve it, so the analysis
is reused instead of recomputed.

Assisted-by: TRAE CLI (GPT-5.5)

[Mips] Fix $gp was restored when used as global register variable (#201778)

The function `eliminateDeadMI` would check `if (MRI.isReserved(Reg))`,
now we only set GP to reserved when `!Subtarget.isABICalls()`. So
`eliminateDeadMI` delete the `move $gp, $4`. And we would restore $gp
after instr selection through `$gp_64 = LD $sp_64, 8`.

Check the module metadata `llvm.named.register.$28` to detect if $28 is
used as global register. Then append new conditon when set $gp to
reserverd status and return CalleeSavedRegs without $gp.

Fix #176546.

GlobalISel: Fix lowerMergeValues when dst type is float (#212795)

Lowering is done in the integer domain. Similar to the type
mismatch when dst is a pointer, make a bitcast when dst is float.

AMDGPU: Give v_cvt_sr_pk_bf16_f32 its own subtarget feature (#213150)

v_cvt_sr_pk_bf16_f32 was gated on bf16-cvt-insts, but that feature is
also present on gfx950 where the (non-sr) v_cvt_pk_bf16_f32 was first
added. The stochastic-rounding v_cvt_sr_pk_bf16_f32 was only added
for gfx1250 and has no gfx950 encoding, so it would mis-select and
later hit the "Invalid opcode" assert. Introduce
cvt-sr-pk-bf16-f32-inst, currently added to gfx13 and 125*

Co-authored-by: Claude (Claude-Opus-4.8)