LLVM/project f3fb6feclang/lib/AST/ByteCode Interp.cpp, clang/test/AST/ByteCode new-delete.cpp

[clang][bytecode] Check for block pointers in Free() (#205043)

We need a block pointer here for the following operations, and non-block
pointers aren't valid anyway.
DeltaFile
+13-0clang/test/AST/ByteCode/new-delete.cpp
+3-0clang/lib/AST/ByteCode/Interp.cpp
+16-02 files

LLVM/project 63f9955llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU packed-u64.ll

AMDGPU/GlobalISel: RegBankLegalize rules for pk_u64 add and sub
DeltaFile
+23-7llvm/test/CodeGen/AMDGPU/packed-u64.ll
+3-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+26-82 files

LLVM/project c56e892llvm/test/CodeGen/AMDGPU vector-reduce-umin.ll vector-reduce-smax.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f32.ll

AMDGPU/GlobalISel: Remove -new-reg-bank-select option (#203929)

AMDGPU's -global-isel pipeline that uses AMDGPURegBankSelect and
AMDGPURegBankLegalize, previously -global-isel -new-reg-bank-select,
is now the default -global-isel pipeline.

Remove -new-reg-bank-select option from the compiler.
Remove -new-reg-bank-select from all llvm regression tests.
Edit a couple comments to reference RegBankLegalize instead of
-new-reg-bank-select.
DeltaFile
+12-12llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+12-12llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+12-12llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+12-12llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+11-11llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
+71-71893 files not shown
+2,533-2,541899 files

LLVM/project b95e1e8llvm/include/llvm/Support Allocator.h, llvm/unittests/Support AllocatorTest.cpp

[Allocator] Keep bump pointer at a minimum alignment (#203718)

Add a `MinAlign` template parameter (default 8, sizeof(size_t) on 64-bit
platforms) so that the common case `Alignment <= MinAlign` can skip
realigning `CurPtr`.

This is achieved by rounding each allocation's size up to MinAlign, so
the bump pointer stays MinAlign-aligned between allocations.

SpecificBumpPtrAllocator::DestroyAll() walks objects at a fixed
sizeof(T) stride and needs tight packing, so it uses MinAlign=1. (alignof(T) would
pack just as tightly and reuse the default instantiation, but T may be
incomplete here, e.g. `SpecificBumpPtrAllocator<MCSectionELF>`.)

Its `Allocate` still skips the realign: the slab is max_align_t-aligned
and every size is a multiple of alignof(T), so the bump pointer stays
alignof(T)-aligned and we can just request alignment 1. Over-aligned
types (alignof(T) > alignof(max_align_t)) keep requesting alignof(T).


    [5 lines not shown]
DeltaFile
+51-27llvm/include/llvm/Support/Allocator.h
+19-0llvm/unittests/Support/AllocatorTest.cpp
+70-272 files

LLVM/project 2a1f306clang/lib/AST/ByteCode Interp.cpp, clang/test/AST/ByteCode dynamic-cast.cpp

[clang][bytecode] Add more sanity checks for pointers used in `dynamic_cast` (#205070)

Make sure it's initialized and that it points to a record.
DeltaFile
+16-0clang/test/AST/ByteCode/dynamic-cast.cpp
+4-2clang/lib/AST/ByteCode/Interp.cpp
+20-22 files

LLVM/project 05d84fdllvm/test/CodeGen/AMDGPU/GlobalISel dropped_debug_info_assert.ll

[AMDGPU] Run update script on test. NFC (#204570)

There's some bogus whitespace in the generated CHECKs that changes when
touching the test.
DeltaFile
+37-37llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
+37-371 files

LLVM/project 12d0fcfllvm/test/CodeGen/AMDGPU vector-reduce-umin.ll vector-reduce-smax.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f32.ll

AMDGPU/GlobalISel: Remove -new-reg-bank-select option

AMDGPU's -global-isel pipeline that uses AMDGPURegBankSelect and
AMDGPURegBankLegalize, previously -global-isel -new-reg-bank-select,
is now the default -global-isel pipeline.

Remove -new-reg-bank-select option from the compiler.
Remove -new-reg-bank-select from all llvm regression tests.
Edit a couple comments to reference RegBankLegalize instead of
-new-reg-bank-select.
DeltaFile
+12-12llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+12-12llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+12-12llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+12-12llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+11-11llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
+71-71893 files not shown
+2,533-2,541899 files

LLVM/project a2289b7lldb/test/API/macosx/deny-attach main.c TestDenyAttach.py, lldb/tools/debugserver/source/MacOSX MachProcess.mm

Revert "[lldb] Survive ptrace(PT_DENY_ATTACH) when attaching" (#205075)

Reverts llvm/llvm-project#204688

This breaks green dragon where the error message is `error: attach
failed: this is a non-interactive debug session, cannot get permission
to debug processes.`
DeltaFile
+5-87lldb/tools/debugserver/source/MacOSX/MachProcess.mm
+0-60lldb/test/API/macosx/deny-attach/main.c
+0-36lldb/test/API/macosx/deny-attach/TestDenyAttach.py
+0-3lldb/test/API/macosx/deny-attach/Makefile
+5-1864 files

LLVM/project 192ef55llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU maximumnum.ll minimumnum.ll

AMDGPU/GlobalISel: Use AMDGPURegBankSelect + AMDGPURegBankLegalize by default (#203928)

AMDGPU/GlobalISel: Use AMDGPURegBankSelect + AMDGPURegBankLegalize by default

Change AMDGPU's default -global-isel pipeline to use AMDGPURegBankSelect
and AMDGPURegBankLegalize (previously -global-isel -new-reg-bank-select)
by default instead of RegBankSelect which uses AMDGPURegisterBankInfo.

-global-isel pipeline that used RegBankSelect/AMDGPURegisterBankInfo is
now deprecated, since it could not generate functionally correct code in
some cases involving divergent control flow and phis.

-new-reg-bank-select option does nothing and will be removed in followup
patch.

Delete regbankselect-mui.ll and regbankselect-mui-salu-float.ll, which
existed to compare the -global-isel vs -global-isel -new-reg-bank-select.

Temporarily disable a couple of tests that are missing AMDGPURegBankLegalize
support.
DeltaFile
+0-643llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
+0-52llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.ll
+13-13llvm/test/CodeGen/AMDGPU/maximumnum.ll
+13-13llvm/test/CodeGen/AMDGPU/minimumnum.ll
+5-9llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+3-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
+34-7332 files not shown
+36-7358 files

LLVM/project 00086d6clang/include/clang/Basic DiagnosticGroups.td, clang/test/Sema/LifetimeSafety dangling-global.cpp

[LifetimeSafety] Add `LifetimeSafetyDanglingGlobalMoved` to strict diagnostic group (#204891)

Fixes #204213

`-Wlifetime-safety-dangling-global-moved` was defined but not included
in any parent diagnostic group, meaning `-Wlifetime-safety-all` and
`-Wno-lifetime-safety-all` had no effect on it.

`LifetimeSafetyDanglingGlobal` (the non-moved variant) was already
correctly placed under `LifetimeSafetyPermissive`. Following the same
pattern as the other `-moved` sibling warnings
(`DanglingFieldMoved`, `ReturnStackAddrMoved`, `UseAfterScopeMoved`),
this patch adds `LifetimeSafetyDanglingGlobalMoved` to
`LifetimeSafetyStrict`, which is part of the `lifetime-safety-all`
hierarchy.

Assisted-by: Claude (Anthropic) — used for learning and understanding 
the codebase, not for generating code directly.
DeltaFile
+9-0clang/test/Sema/LifetimeSafety/dangling-global.cpp
+1-0clang/include/clang/Basic/DiagnosticGroups.td
+10-02 files

LLVM/project 283514bllvm/test/tools/llvm-objcopy/ELF decompress-sections-unsupported-zlib.test decompress-sections-unsupported-zstd.test, llvm/tools/llvm-objcopy ObjcopyOptions.cpp

[llvm-objcopy] Report unsupported formats before compression (#202357)

Fixes #197877.

`llvm-objcopy --compress-sections` now reports unavailable compression
support while parsing the option, matching the behavior of
`--compress-debug-sections`. This avoids reaching compression code with
an unavailable format.

Decompression (either via `--decompress-debug-sections` or
`--compress-sections` with a `none` format) is still checked when the
relevant compressed section is processed, because the required
compression format is determined from the section header rather than
from the command-line option.

The `compress-sections-within-segment` test now requires zlib because
`--compress-sections .text=zlib` is diagnosed during option parsing when
zlib support is unavailable, before the test can reach the intended
"section within a segment" diagnostic.
DeltaFile
+40-0llvm/test/tools/llvm-objcopy/ELF/decompress-sections-unsupported-zlib.test
+40-0llvm/test/tools/llvm-objcopy/ELF/decompress-sections-unsupported-zstd.test
+0-18llvm/test/tools/llvm-objcopy/ELF/decompress-debug-sections-unsupported-zlib.test
+6-0llvm/test/tools/llvm-objcopy/ELF/compress-sections-zlib-unsupported.test
+6-0llvm/test/tools/llvm-objcopy/ELF/compress-sections-zstd-unsupported.test
+5-0llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
+97-183 files not shown
+101-239 files

LLVM/project 9e8615fllvm/include/llvm/Support ConvertUTF.h, llvm/lib/Support ConvertUTFWrapper.cpp

[NFC][llvm] simplify convertWideToUTF8 overloads (#204552)

Remove the C-String overload of `convertWideToUTF8` and convert the
`ArrayRef` one to use `std::wstring_view` in order to simplify the API.
DeltaFile
+2-8llvm/include/llvm/Support/ConvertUTF.h
+1-5llvm/lib/Support/ConvertUTFWrapper.cpp
+3-132 files

LLVM/project 75440edllvm/test/tools/llvm-mca/AArch64/Cortex forwarding-A57.s A57-forwarding.s

[NFC][AArch64][MCA] Rename A55/A57 mca tests (#204551)

Rename several llvm-mca tests for cortex-a55 and cortex-a57 to follow
the same pattern as the other testss
DeltaFile
+0-501llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s
+501-0llvm/test/tools/llvm-mca/AArch64/Cortex/A57-forwarding.s
+0-60llvm/test/tools/llvm-mca/AArch64/Cortex/direct-branch.s
+60-0llvm/test/tools/llvm-mca/AArch64/Cortex/A57-direct-branch.s
+31-0llvm/test/tools/llvm-mca/AArch64/Cortex/A57-shifted-register.s
+0-31llvm/test/tools/llvm-mca/AArch64/Cortex/shifted-register.s
+592-5922 files not shown
+600-6008 files

LLVM/project 8d83748lld/ELF Writer.cpp

Address review comments
DeltaFile
+18-13lld/ELF/Writer.cpp
+18-131 files

LLVM/project 0401597llvm/test/CodeGen/RISCV clmul.ll clmulr.ll, llvm/test/CodeGen/RISCV/rvv clmulh-sdnode.ll clmul-sdnode.ll

Merge branch 'main' into users/rovkaspr/main/150473b0
DeltaFile
+25,784-36,416llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+12,227-23,140llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+4,004-11,142llvm/test/CodeGen/RISCV/clmul.ll
+3,502-9,174llvm/test/CodeGen/X86/clmul-vector.ll
+3,985-7,989llvm/test/CodeGen/Thumb2/mve-clmul.ll
+4,144-6,437llvm/test/CodeGen/RISCV/clmulr.ll
+53,646-94,2981,133 files not shown
+98,422-138,6531,139 files

LLVM/project f623ee0llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll, llvm/test/CodeGen/RISCV clmul.ll clmulr.ll

Merge branch 'main' into users/kovdan01/pauth-relr-rela-movement
DeltaFile
+31,001-87,165llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+15,519-26,130llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+12,134-24,576llvm/test/CodeGen/RISCV/clmul.ll
+16,791-15,581llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+8,309-12,701llvm/test/CodeGen/RISCV/clmulr.ll
+7,968-12,512llvm/test/CodeGen/RISCV/clmulh.ll
+91,722-178,66513,430 files not shown
+1,076,799-677,45713,436 files

LLVM/project 5804784llvm/test/CodeGen/AMDGPU vector-reduce-umin.ll integer-mad-patterns.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fdiv.f32.ll

AMDGPU/GlobalISel: Remove -new-reg-bank-select option

AMDGPU's -global-isel pipeline that uses AMDGPURegBankSelect and
AMDGPURegBankLegalize, previously -global-isel -new-reg-bank-select,
is now the default -global-isel pipeline.

Remove -new-reg-bank-select option from the compiler.
Remove -new-reg-bank-select from all llvm regression tests.
Edit a couple comments to reference RegBankLegalize instead of
-new-reg-bank-select.
DeltaFile
+12-12llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+12-12llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+12-12llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+12-12llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+11-11llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
+71-71893 files not shown
+2,533-2,541899 files

LLVM/project 0b1fe74mlir/include/mlir/Dialect/Bufferization/IR UnstructuredControlFlow.h, mlir/lib/Dialect/Bufferization/IR BufferizableOpInterface.cpp

[mlir][bufferization] Introduce reconcileBufferTypeMismatchFn hook (#202667)

This PR is the first part of the work that aims to allow customizations
in resolving mismatching buffer types.

Add a new bufferization hook that lets downstream bufferization
implementations define how to handle buffer mismatches that appear
during type inference in various upstream scenarios.

The hook is used as a fallback mechanism in several upstream operations.
For example, when bufferizing block signatures (scf.execute_region), and
resolving "branch" conflicts (scf.if, scfl.index_switch, scf.for,
arith.select).

The hook returns a valid buffer type when reconciliation succeeded;
failure indicates reconciliation failure and should be treated as
bufferization failure. The caller of the hook is expected to use the
returned buffer type. By default, a memref with fully-dynamic layout map
is returned (for unranked case, buffers are assumed to match).

    [3 lines not shown]
DeltaFile
+282-0mlir/test/Dialect/Bufferization/Transforms/test-one-shot-module-bufferize.mlir
+100-3mlir/test/lib/Dialect/Test/TestOps.td
+35-50mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
+71-0mlir/test/lib/Dialect/Test/TestOpDefs.cpp
+40-13mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
+24-26mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
+552-926 files not shown
+613-11812 files

LLVM/project 5c0d97ellvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU maximumnum.ll minimumnum.ll

AMDGPU/GlobalISel: Use AMDGPURegBankSelect + AMDGPURegBankLegalize by default

Change AMDGPU's default -global-isel pipeline to use AMDGPURegBankSelect
and AMDGPURegBankLegalize (previously -global-isel -new-reg-bank-select)
by default instead of RegBankSelect which uses AMDGPURegisterBankInfo.

-global-isel pipeline that used RegBankSelect/AMDGPURegisterBankInfo is
now deprecated, since it could not generate functionally correct code in
some cases involving divergent control flow and phis.

-new-reg-bank-select option does nothing and will be removed in followup
patch.

Delete regbankselect-mui.ll and regbankselect-mui-salu-float.ll, which
existed to compare the -global-isel vs -global-isel -new-reg-bank-select.

Temporarily disable a couple of tests that are missing AMDGPURegBankLegalize
support.
DeltaFile
+0-643llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
+0-52llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.ll
+13-13llvm/test/CodeGen/AMDGPU/maximumnum.ll
+13-13llvm/test/CodeGen/AMDGPU/minimumnum.ll
+5-9llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+3-3llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
+34-7332 files not shown
+36-7358 files

LLVM/project b5dfea0llvm/lib/Target/ARM ARMBaseInstrInfo.cpp ARMRegisterInfo.td, llvm/test/CodeGen/ARM machine-outliner-thunk-tcgpr.mir

[ARM] Fix Machine Outliner crash when tBLXr uses non-tcGPR register  (#200684)

When the Machine Outliner selects MachineOutlinerThunk mode for a
sequence ending in tBLXr/tBLXr_noip, it converts the indirect call to
tTAILJMPr in buildOutlinedFrame. However tTAILJMPr requires its operand
to be in tcGPR (R0-R3, R12), while tBLXr accepts any GPR.

If the register is callee-saved (e.g. r4), the Machine Verifier crashes
with 'Illegal physical register for instruction'.

Fixes #188076 
DeltaFile
+40-0llvm/test/CodeGen/ARM/machine-outliner-thunk-tcgpr.mir
+5-3llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+3-2llvm/lib/Target/ARM/ARMRegisterInfo.td
+48-53 files

LLVM/project 3aeb6c1mlir/include/mlir/Dialect/SPIRV/IR SPIRVCompositeOps.td SPIRVBase.td, mlir/test/Dialect/SPIRV/IR composite-ops.mlir

[mlir][spirv] Re-enable bf16/fp8 for vector composite ops (#204848)

Allow bf16 and fp8 vector element types in VectorExtractDynamic,
VectorInsertDynamic, and VectorShuffle.
DeltaFile
+54-0mlir/test/Dialect/SPIRV/IR/composite-ops.mlir
+8-8mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td
+6-0mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+68-83 files

LLVM/project 78fc168clang/lib/Driver/ToolChains Clang.cpp

clang: Use the effective triple string for offload jobs

Track the future effective triple for the job, rather than
the toolchain's default triple. In the future this will
change the result when amdgpu starts adjusting the triples
to contain subarches.
DeltaFile
+12-7clang/lib/Driver/ToolChains/Clang.cpp
+12-71 files

LLVM/project b0bf2c7clang/docs ConstantInterpreter.rst

[clang][bytecode] Update high-level documentation (#202596)
DeltaFile
+85-53clang/docs/ConstantInterpreter.rst
+85-531 files

LLVM/project 6daa021mlir/lib/Dialect/Tosa/IR TosaOps.cpp, mlir/test/Dialect/Tosa verifier.mlir

[mlir][tosa] Check same input/output types in pooling ops verifier (#203565)

Adds a missing check to make sure the input and output types of pooling
ops have the same element type.
DeltaFile
+22-0mlir/test/Dialect/Tosa/verifier.mlir
+8-5mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+30-52 files

LLVM/project f782f54llvm/include/llvm/Transforms/Scalar Reassociate.h, llvm/lib/Transforms/Scalar Reassociate.cpp

review
DeltaFile
+6-1llvm/include/llvm/Transforms/Scalar/Reassociate.h
+2-3llvm/lib/Transforms/Scalar/Reassociate.cpp
+8-42 files

LLVM/project 6be53abllvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp, llvm/test/CodeGen/AArch64 pr204118.ll

[AArch64][GISel] Remove hard-coded operand index from FCVT renderers (#204118)
DeltaFile
+28-0llvm/test/CodeGen/AArch64/GlobalISel/pr204118.mir
+13-0llvm/test/CodeGen/AArch64/pr204118.ll
+2-2llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+43-23 files

LLVM/project 0972d5cclang/include/clang/AST Decl.h

[clang][NFC] Add LLVM_PREFERRED_TYPE to EvaluatedStmt bitfields (#205026)
DeltaFile
+16-8clang/include/clang/AST/Decl.h
+16-81 files

LLVM/project bdde0e5. .gitignore

gitignore: Add emacs lock files
DeltaFile
+2-0.gitignore
+2-01 files

LLVM/project e4df739llvm/lib/Target/AMDGPU AMDGPUInstructionSelector.h AMDGPUInstructionSelector.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.h

[AMDGPU] Remove stale declarations. NFC. (#205047)

Remove declarations of functions that are never defined. Also remove
unused field AMDGPUInstructionSelector::TM.

Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
DeltaFile
+0-21llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+1-5llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
+2-4llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+0-5llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+0-2llvm/lib/Target/AMDGPU/R600ISelLowering.h
+0-2llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+3-392 files not shown
+4-418 files

LLVM/project 1eb70f1clang/lib/Driver Driver.cpp, clang/lib/Driver/ToolChains CommonArgs.cpp AMDGPU.cpp

clang/AMDGPU: Use effective triple instead of raw toolchain triple

Start using the effective triple instead of the raw toolchain triple.
For the moment this is NFC, but will change when new uses of the subarch
field are introduced.
DeltaFile
+3-2clang/lib/Driver/ToolChains/CommonArgs.cpp
+2-2clang/lib/Driver/ToolChains/AMDGPU.cpp
+1-1clang/lib/Driver/Driver.cpp
+1-1clang/lib/Driver/ToolChains/HIPAMD.cpp
+7-64 files