[ProfileData] Avoid magic layout indices in SampleProfileWriter (NFC) (#215981)
This patch removes hardcoded section layout indices in
SampleProfileWriterExtBinary in favor of finding the first unwritten
matching entry in SectionHdrLayout.
Previously, writeDefaultLayout and writeCtxSplitLayout passed magic
integer indices to writeOneSection to specify the position of each
section in SectionHdrLayout.
This patch introduces findUnwrittenEntry to dynamically look up the
matching unwritten section entry in SectionHdrLayout and determine its
ordinal among sections of the same type. This allows
writeDefaultLayout and writeCtxSplitLayout to iterate over declarative
arrays of sections without magic indices, and allows removing the
index-based addSectionFlag overload.
Assisted-by: Antigravity
[ProfileData] Remove SampleSorter (NFC) (#215941)
This patch removes SampleSorter in favor of direct iteration over
BodySamples and CallsiteSamples.
Originally, BodySamples and CallsiteSamples used DenseMap. Because
DenseMap does not guarantee iteration order, SampleSorter was
introduced to sort samples by LineLocation on demand when printing or
writing text profiles.
In December 2015, commit 10cf124bb920 switched BodySamples and
CallsiteSamples from DenseMap to std::map to reduce memory usage, but
SampleSorter was retained. Since std::map is already ordered by
LineLocation, SampleSorter is redundant.
Assisted-by: Antigravity
Reland "[Profile] Add a more descriptive message to the bad_header error" (#216230)
At the moment, the raw profile reader diagnoses different problem with
the same error message "invalid instrumentation profile data (file
header is corrupt)". On AIX, we had users report such problems thinking
it's a compiler bug, while the real problem was truncated profiles. The
particular case they hit was the condition
[here](https://github.com/llvm/llvm-project/blob/668803fa73bdf2f8d095162a1f81c000d18458c9/llvm/lib/ProfileData/InstrProfReader.cpp#L652):
```
Error RawInstrProfReader<IntPtrT>::readHeader(...) {
...
if (Start + ValueDataOffset > DataBuffer->getBufferEnd())
return error(instrprof_error::bad_header);
```
This could indicate a corrupted header (large garbage values for some
sections) or a truncated file.
I figured if we print the values and sizes we read in the header, it
will give the user more info.
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[BOLT][RISCV][NFC] Add a test for GOT references with a non-adjacent load (#215991)
The RISC-V psABI pairs the two halves of a PC-relative address through
the label that the %pcrel_lo relocation refers to, so the load holding
the low part does not have to follow the AUIPC directly.
Pin down the current behavior in that case. All three references name
the same symbol and should therefore resolve to the same GOT entry, but
only the first one does, because BOLT takes the low part from whatever
instruction follows the AUIPC: an unrelated ADDI in the second case, and
the terminator of the basic block in the third. The next commit fixes
this and updates the checks.
[DebugInfo][NFC] Document debug record salvage (#215907)
Document the order salvageDebugInfoForDbgValues works in: a dbg.assign
address before its variable location, stop once a variable location
can't be salvaged, and kill every supplied record when none of them were
processed.
salvageDebugInfo is documented on both its declaration and its
definition, keep the header copy and update it.
No regressions on check-llvm.
[ORC] Realign EPCGenericJITLinkMemoryManager Create API (#216216)
Bring EPCGenericJITLinkMemoryManager into alignment with
EPCGenericMemoryAccess and EPCGenericDylibManager: a Bindings
constructor plus static Create methods that build the bindings from the
ProxySpecs using the default controller-interface names.
Create(JITDylib&) resolves the SimpleNativeMemoryMap symbols in the
given JITDylib; Create(ExecutionSession&) uses the bootstrap JITDylib.
Clients targeting a different protocol can construct their own Bindings
directly.
This replaces the previous scheme where Create took a
SimpleExecutorMemoryManagerSymbolNames override.
[libc][Semaphore] Fix tests - remove APPEND_LIBC_TEST macro uses. (#216219)
APPEND_LIBC_TEST was removed in abeb492322c12860a4533426208d6d26155cd0bc
, remove it from the newly added semaphore tests as well.
[CIR][CodeGen] Emit cir.fmuladd for FP-contracted mul+add/sub (#215382)
Ports the FP-contraction fusion from classic CodeGen (`tryEmitFMulAdd` /
`buildFMulAdd`) to CIRGen. Under `-ffp-contract=on / fast`, `a * b + c`
and `a * b - c` fuse into `cir.fmuladd` (with the addend negated for the sub
form) instead of separate `cir.fmul` + `cir.fadd/fsub`.
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
[mlir][xegpu] Lower lane_data repack convert_layout to lane_shuffle (#210837)
Extend the SgToLaneConvertLayout pattern to lower a convert_layout that
only repacks lane_data between round-robin and contiguous form (keeping
lane_layout and order unchanged) into xegpu.lane_shuffle. Each lane
keeps the same elements and total bits along the repacked dimension, but
their assignment to lanes changes, so the data is moved across lanes
with a bit-preserving bitcast_shuffle.
assisted-by-claude
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
[mlir][XeGPU] Distribute create_nd_tdesc/load/store with SliceAttr layout (#216104)
## Summary
- `WgToSgCreateNdOp` and `XeGPUWgToSgDistributePass`'s dynamic legality
check only matched `xegpu::LayoutAttr` on a tensor_desc's layout, not
`xegpu::SliceAttr` (also a `DistributeLayoutAttr`).
- A tensor_desc feeding a unit-dim-expanding `vector.shape_cast` carries
a `SliceAttr`, so such `create_nd_tdesc`/`load_nd` ops were left
undistributed while their consumers were already converted to subgroup
shape, causing a `vector.shape_cast` element-count mismatch.
- Match on `DistributeLayoutAttr` instead, consistent with the rest of
the pass (`getSgShapeAndCount`, `genOffsetsList`, etc.).
## Test plan
- [x] Added a regression test to `xegpu-wg-to-sg.mlir`:
`create_nd_tdesc`/`load_nd` with a `SliceAttr` layout feeding
`shape_cast` (expand) → `arith.addf` → `shape_cast` (collapse) →
`store_nd`.
- [x] Verified the new test fails on `main` with the reported error and
passes with this fix.
[ORC] Align GDB-JIT alloc-action names with the ORC runtime (#216024)
Align LLVM's GDB-JIT registration alloc-action names with the names
added to the ORC runtime in 4a0fdbc25bb, and add a name for the
deregistration action.
Look these names up in the Bootstrap JITDylib rather than the Process
JITDylib. Since the lookup no longer depends on process symbols, drop
the "requires process symbols" preconditions guarding MachO debugger
support in llvm-jitlink and enableDebuggerSupport.
GDBJITDebugInfoRegistrationPlugin::Create also loses its Triple
parameter, which is now unused.
Together this lets GDBJITDebugInfoRegistrationPlugin work against either
the LLVM OrcTargetProcess or ORC runtime implementation of these
actions.
[lldb] Search for a corefile's images before loading any of them
A userland or kernel corefile can list hundreds of images, and searching for
one can shell out to a symbol server or fetch over the network. Searching for
them one at a time is where loading such a corefile spends its time.
Add a batch form of SymbolLocator::Locate that runs the searches on the
debugger's thread pool, gated on target.parallel-module-load. Results come
back in the order the requests were given, since that order decides the
Target's module order. Only the results are ordered, and anything a search
reports to the user arrives in whatever order the searches finish in.
Only the plugin searches run concurrently, so a platform hook does not have to
be thread safe to take part, and reading a binary's UUID out of memory stays
on the calling thread.
Setting up a platform binary can replace the Target's platform and dynamic
loader, and now happens for every image before any of them is searched for, so
the platform a corefile asks for is the one all of its images are searched
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[DWARFLinker] Constrain a function's high_pc to its own symbol
Mach-O objects built with .subsections_via_symbols make every symbol an
independently placeable atom, and the linker packs atoms without
preserving the spacing they had in the object file.
I have an example where the compiler describes such a subprogram as
extending past its own atom. While it's debatable whether that's a good
idea, it's not invalid in the object file. However, once linked, it is
invalid.
We can make dsymutil resilient against this by looking at the size of
the symbol in the debug map and adjusting the end_pc. I'm doing so
conservatively so that only a collision is repaired. Already
overlapping/invalid ranges remain untouched.
rdar://184768778
[CIR] Handle label address difference (#205437)
This change adds handling for emitting AddrLabelDiff constants. These
constants can be used to initialize static variables within a function
by computing the difference between the addresses of two labels. These
constant values are represented in the AST using the APValue class. The
code generator needs to emit them as initializers for the global
corresponding to the static variable.
This change introduces a new CIR attribute type, BlockAddrDiffAttr to
represent this constant value, deferring the label block address
resolution until we lower the initializer to the LLVM dialect.
Assisted-by: Cursor / claude-opus-4.8
[CIR] Implement CIRBasicAliasAnalysis::getUnderlyingObject (#215683)
This implements the CIRBasicAliasAnalysis::getUnderlyingObject to follow
casts, pointer strides, array element, and struct member accesses back
to the underlying alloca operation if the operation does not introduce
an offset from the original pointer operand.
This still conservatively returns MayAlias for any comparison involving
a pointer with a non-zero offset from its base alloca address. We could
go further, calculating the offset and determining non-alias or partial
alias from offset pointers, but that is deferred until a future PR.
Assisted-by: Claude / Sonnet-4.6
[mlir][mem2reg] Promote whole-buffer memref to a vector SSA value (#211880)
**Problem**
After bufferization, an accumulator that is repeatedly read and written
at a fixed location inside a loop becomes a temporary memref carried
across iterations via transfer_read / transfer_write. These buffers are
pure register-candidates — the memory location is loop-invariant, only
the contents change — but nothing today promotes a whole-buffer
(multi-element) accumulator to a vector SSA value. Upstream mem2reg only
promotes scalar slots.
This PR extends mem2reg to recognize a matching whole-buffer
vector.transfer_read / vector.transfer_write pair as a promotable use,
so the accumulator is promoted to a vector<...> loop iter_arg and the
buffer is eliminated.
**Why not improve the existing tensor/vector hoisting transforms?**
The existing hoisting transforms (hoist_loop_invariant_subsets,
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