LLVM/project ff13eb7llvm/test/CodeGen/RISCV selectopt.ll

Refactor tests

Created using spr 1.3.6-beta.1
DeltaFile
+47-77llvm/test/CodeGen/RISCV/selectopt.ll
+47-771 files

LLVM/project 2c7cf89llvm/lib/Transforms/Utils UnifyLoopExits.cpp ControlFlowUtils.cpp, llvm/test/Transforms/UnifyLoopExits no-exit-blocks.ll

[llvm][UnifyLoopExits] Avoid optimization if no exit block is found (#165343)

If there is not an exit block, we should not try unify the loops.
Instead we should just return.

Fixes #165252
DeltaFile
+15-0llvm/test/Transforms/UnifyLoopExits/no-exit-blocks.ll
+5-0llvm/lib/Transforms/Utils/UnifyLoopExits.cpp
+2-0llvm/lib/Transforms/Utils/ControlFlowUtils.cpp
+22-03 files

LLVM/project c03d0feclang/docs LanguageExtensions.rst, clang/include/clang/Basic OpenCLExtensions.def

[OpenCL] Add clang internal extension __cl_clang_function_scope_local_variables  (#176726)

OpenCL spec restricts that variable in local address space can only be
declared at kernel function scope.
Add a Clang internal extension __cl_clang_function_scope_local_variables
to lift the restriction.

To expose static local allocations at kernel scope, targets can either
force-inline non-kernel functions that declare local memory or pass a
kernel-allocated local buffer to those functions via an implicit argument.

Motivation: support local memory allocation in libclc's implementation
of work-group collective built-ins, see example at:
https://github.com/intel/llvm/blob/41455e305117/libclc/libspirv/lib/amdgcn-amdhsa/group/collectives_helpers.ll
https://github.com/intel/llvm/blob/41455e305117/libclc/libspirv/lib/amdgcn-amdhsa/group/collectives.cl#L182

Right now this is a Clang-only OpenCL extension intended for compiling
OpenCL libraries with Clang. It could be proposed as a standard OpenCL
extension in the future.
DeltaFile
+44-0clang/docs/LanguageExtensions.rst
+22-9clang/test/SemaOpenCL/storageclass.cl
+19-0clang/test/CodeGenOpenCL/local-scope.cl
+11-2clang/lib/Sema/SemaDecl.cpp
+5-0clang/test/SemaOpenCL/extension-version.cl
+1-0clang/include/clang/Basic/OpenCLExtensions.def
+102-116 files

LLVM/project 20c15c7libclc/clc/lib/generic/math clc_remquo.inc clc_remquo.cl

[libclc] replace float remquo with amd ocml implementation (#177131)

Current implementation has two issues:
* unconditionally soft flushes denormal.
* can't pass OpenCL CTS test "test_bruteforce remquo" on intel gpu.

This PR upstreams remquo implementation from
https://github.com/ROCm/llvm-project/tree/amd-staging/amd/device-libs/ocml/src/remainderF_base.h
It supports denormal and can pass OpenCL CTS test. Number of LLVM IR
instructions of function _Z6remquoffPU3AS5i increased from 96 to 680.

---------

Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
DeltaFile
+70-57libclc/clc/lib/generic/math/clc_remquo.inc
+10-1libclc/clc/lib/generic/math/clc_remquo.cl
+80-582 files

LLVM/project cdc6a84llvm/test/CodeGen/ARM vminmax.ll minnum-maxnum-intrinsics.ll, llvm/test/CodeGen/WebAssembly simd-arith.ll f64.ll

TargetLowering: Allow FMINNUM/FMAXNUM to lower to FMINIMUM/FMAXIMUM even without `nsz` (#177828)

This restriction was originally added in
https://reviews.llvm.org/D143256, with the given justification:

> Currently, in TargetLowering, if the target does not support fminnum,
we lower to fminimum if neither operand could be a NaN. But this isn't
quite correct because fminnum and fminimum treat +/-0 differently; so,
we need to prove that one of the operands isn't a zero.

As far as I can tell, this was never correct. Before
https://github.com/llvm/llvm-project/pull/172012, `minnum` and `maxnum`
were nondeterministic with regards to signed zero, so it's always been
perfectly legal to lower them to operations that order signed zeroes.
DeltaFile
+337-176llvm/test/CodeGen/ARM/vminmax.ll
+78-314llvm/test/CodeGen/WebAssembly/simd-arith.ll
+43-112llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
+14-26llvm/test/CodeGen/WebAssembly/f64.ll
+11-20llvm/test/CodeGen/WebAssembly/f32.ll
+16-12llvm/test/CodeGen/ARM/lower-vmax.ll
+499-6601 files not shown
+503-6687 files

LLVM/project 7b445ddllvm/test/Transforms/LoopVectorize early-exit-load-live-out.ll single_early_exit_unsafe_ptrs.ll, llvm/test/Transforms/LoopVectorize/AArch64 early_exit_cost.ll

[LV] Add additional tests for early-exit loops loads not known deref.

Add additional test coverage for loops with loads that are not known to
be dereferenceable.
DeltaFile
+236-0llvm/test/Transforms/LoopVectorize/early-exit-load-live-out.ll
+132-0llvm/test/Transforms/LoopVectorize/AArch64/early_exit_cost.ll
+38-0llvm/test/Transforms/LoopVectorize/single_early_exit_unsafe_ptrs.ll
+406-03 files

LLVM/project 9b3b643llvm/lib/Transforms/InstCombine InstCombineSelect.cpp, llvm/test/Transforms/InstCombine fcmp-fadd-select.ll minmax-fp.ll

[InstCombine] Don't convert a compare+select into a minnum/maxnum intrinsic that can't be lowered back to a compare+select (#177821)

This is a step on the yak-shaving expedition to properly implement the
new `minnum`/`maxnum` signed-zero semantics.

`InstCombineSelect` will convert a `fcmp`+`select` sequence to a
`minnum`/`maxnum` intrinsic. It doesn't require the `fcmp` to have any
particular fast-math flags, just that the `select` has `nnan` and `nsz`
(or is being used in a context where the result doesn't care about
signed zero).

It's not correct to propagate the `nnan` flag from the `fcmp`
instruction for poison-propagation reasons. Patches like
https://github.com/llvm/llvm-project/pull/117977 and
https://github.com/llvm/llvm-project/pull/141010 have *generously* made
it so that if `fcmp` doesn't have fast-math flags, we can still perform
the transformation by simply dropping the flags on the generated
intrinsic.


    [25 lines not shown]
DeltaFile
+107-92llvm/test/Transforms/InstCombine/fcmp-fadd-select.ll
+25-25llvm/test/Transforms/InstCombine/minmax-fp.ll
+27-3llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+7-7llvm/test/Transforms/InstCombine/unordered-fcmp-select.ll
+6-6llvm/test/Transforms/InstCombine/fcmp-select.ll
+2-2llvm/test/Transforms/InstCombine/fneg.ll
+174-1356 files

LLVM/project e5d2358polly/include/polly ScopDetectionDiagnostic.h ScopDetection.h, polly/lib/Analysis ScopDetectionDiagnostic.cpp ScopDetection.cpp

[Polly] Reject scalable vector types (#177871)

Polly currently does not consider types without fixed length, which can
be encountered if an input source uses e.g. ARM SVE builtins. Such
programs have already been optimized manually. Non-fixed type lengths
also add to the difficulty of dependency analysis. Skip such types
entirely for now.
 
Fixes: #177859
DeltaFile
+95-0polly/test/ScopDetectionDiagnostics/ReportIncompatibleType.ll
+32-0polly/lib/Analysis/ScopDetectionDiagnostic.cpp
+28-0polly/include/polly/ScopDetectionDiagnostic.h
+17-0polly/lib/Analysis/ScopDetection.cpp
+4-0polly/include/polly/ScopDetection.h
+176-05 files

LLVM/project 14bdd06mlir/lib/Dialect/SCF/Transforms LoopSpecialization.cpp, mlir/lib/Dialect/Utils StaticValueUtils.cpp

[mlir][DialectUtils] Fix 0 step handling in `constantTripCount` (#177329)

A step size of "zero" does not indicate "zero iterations". It may
indicate an infinite number of iterations.

This commit makes some transformations more conservative. We used to
fold away some loops with step size 0 and that's now no longer the case.

Relation discussion:
https://discourse.llvm.org/t/infinite-loops-and-dead-code/89530
DeltaFile
+11-3mlir/lib/Dialect/Utils/StaticValueUtils.cpp
+8-2mlir/test/Dialect/SCF/for-loop-peeling.mlir
+4-3mlir/test/Dialect/SCF/canonicalize.mlir
+3-0mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
+26-84 files

LLVM/project 544c300llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

DAG: Use poison instead of undef in some vector combines (#177612)

Use poison for the unused or out of bounds vector components.
DeltaFile
+48-48llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+48-481 files

LLVM/project 0666a77llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/SLPVectorizer/X86 vec_list_bias-inseltpoison.ll

[SLP]Support for tree throttling in SLP graphs with gathered loads

Gathered loads forming DAG instead of trees in SLP vectorizer. When
doing the throttling analysis for such graphs, need to consider partially
matched gathered loads DAG nodes and consider extract and/or gather
operations and their costs.
The patch adds this analysis and allows cutting off the expensive
sub-graphs with gathered loads.

Reviewers: hiraditya, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/177855
DeltaFile
+99-14llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+12-13llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
+111-272 files

LLVM/project 73ebadaclang/docs ReleaseNotes.rst, clang/include/clang/Sema Overload.h

[clang] Don't assert on perfect overload match with _Atomic (#176619)

An assertion incorrectly treated difference in _Atomic qualification as
different types for the purpose of verifying a perfect match in overload
resolution in C++.

Fixes #170433
DeltaFile
+16-0clang/test/SemaCXX/crash-GH170433.cpp
+2-1clang/include/clang/Sema/Overload.h
+1-0clang/docs/ReleaseNotes.rst
+19-13 files

LLVM/project 9d6f011llvm/include/llvm/IR PatternMatch.h, llvm/lib/Transforms/Vectorize VectorCombine.cpp

[VectorCombine] Fold vector.reduce.OP(F(X)) == 0 -> OP(X) == 0 (#173069)

This commit introduces a pattern to do the following fold:

  vector.reduce.OP f(X_i) == 0 -> vector.reduce.OP X_i == 0

In order to decide on this fold, we use the following properties:

1. OP X_i == 0 <=> \forall i \in [1, N] X_i == 0 1'. OP X_i == 0 <=>
\exists j \in [1, N] X_j == 0
  2.  f(x) == 0 <=> x == 0

From 1 and 2 (or 1' and 2), we can infer that

  OP f(X_i) == 0 <=> OP X_i == 0.

For some of the OP's and f's, we need to have domain constraints on X to
ensure properties 1 (or 1') and 2.


    [52 lines not shown]
DeltaFile
+672-0llvm/test/Transforms/VectorCombine/X86/icmp-vector-reduce.ll
+672-0llvm/test/Transforms/VectorCombine/AArch64/icmp-vector-reduce.ll
+183-0llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+9-0llvm/include/llvm/IR/PatternMatch.h
+1,536-04 files

LLVM/project 9eaa1ffclang/test/CodeGen builtin-rotate.c

[clang][test] Fix builtin-rotate.c test __int128 test failure on ARM32 (#177732)

- Run the INT128 prefix checks on 64-bit targets since __int128 is not
supported on ARM32

Fixes https://lab.llvm.org/buildbot/#/builders/154/builds/26813

DeltaFile
+4-3clang/test/CodeGen/builtin-rotate.c
+4-31 files

LLVM/project 029efa6utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Add missing dependencies for 778a2491149512109541cd5d59bad2d55024bdb7
DeltaFile
+2-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+2-01 files

LLVM/project 13d82f3llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

update comments
DeltaFile
+5-5llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+5-51 files

LLVM/project 4e1d431llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

DAG: Use poison instead of undef in some vector combines

Use poison for the unused or out of bounds vector components.
DeltaFile
+43-43llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+43-431 files

LLVM/project a80d432llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Apply parameter nofpclass in SimplifyDemandedFPClass (#176104)

Apply the use operand's nofpclass to the demanded mask.
DeltaFile
+11-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+5-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+16-02 files

LLVM/project b1b8410llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

InstCombine: Handle multiple use copysign

Handle multiple use copysign in SimplifyDemandedFPClass
DeltaFile
+36-3llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+7-7llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+7-0llvm/include/llvm/Support/KnownFPClass.h
+50-103 files

LLVM/project 9a0bca2llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Handle nsz in copysign SimplifyDemandedFPClass

If the only sign bit difference is for 0, fold through the source.
DeltaFile
+31-1llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+2-4llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+33-52 files

LLVM/project 78ce56cllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp

Address comments
DeltaFile
+3-3llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+3-31 files

LLVM/project 025f150llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Add baseline tests for SimplifyDemandedFPClass copysign improvements

Prepare to support more folds and multiple uses.
DeltaFile
+651-0llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+651-01 files

LLVM/project 0b24eacllvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass.ll

InstCombine: Improve single-use fneg(fabs(x)) SimplifyDemandedFPClass handling

Match the multi-use case's logic for understanding no-nan/no-inf context.
Also only apply the nsz handling in the single use case. alive2 seems to treat
nsz as nondeterministic for each use.
DeltaFile
+244-11llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
+74-20llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+318-312 files

LLVM/project 2370bf2llvm/include/llvm/CodeGen SDPatternMatch.h, llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp

[DAG] Extend MinMax matchers to detect flippable sign (#177504)

Fixes #174328
DeltaFile
+115-0llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+68-0llvm/test/CodeGen/AArch64/abds.ll
+22-8llvm/include/llvm/CodeGen/SDPatternMatch.h
+8-8llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+213-164 files

LLVM/project 61c1621mlir/lib/CAPI/Transforms Rewrite.cpp, mlir/lib/Dialect/ArmNeon/Transforms LowerContractToNeonPatterns.cpp

[MLIR] Fix GCC's `-Wreturn-type` warnings (#177654)

This patch fixes `-Wreturn-type` warnings which happens if MLIR is built
with GCC compiler (11.5 is used for detecting)


Founded errors
```
build/llvm-llvmorg-21.1.8/mlir/lib/CAPI/Transforms/Rewrite.cpp: In function ‘MlirGreedyRewriteStrictness mlirGreedyRewriteDriverConfigGetStrictness(MlirGreedyRewriteDriverConfig)’:
build/llvm-llvmorg-21.1.8/mlir/lib/CAPI/Transforms/Rewrite.cpp:399:1: warning: control reaches end of non-void function [-Wreturn-type]
  399 | }
      | ^
build/llvm-llvmorg-21.1.8/mlir/lib/CAPI/Transforms/Rewrite.cpp: In function ‘MlirGreedySimplifyRegionLevel mlirGreedyRewriteDriverConfigGetRegionSimplificationLevel(MlirGreedyRewriteDriverConfig)’:
build/llvm-llvmorg-21.1.8/mlir/lib/CAPI/Transforms/Rewrite.cpp:414:1: warning: control reaches end of non-void function [-Wreturn-type]
  414 | }
      | ^
build/llvm-llvmorg-21.1.8/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp: In member function ‘mlir::Speculation::Speculatability mlir::gpu::SubgroupBroadcastOp::getSpeculatability()’:
build/llvm-llvmorg-21.1.8/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp:2522:1: warning: control reaches end of non-void function [-Wreturn-type]
 2522 | }

    [20 lines not shown]
DeltaFile
+2-0mlir/lib/CAPI/Transforms/Rewrite.cpp
+2-0mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
+1-0mlir/test/lib/Dialect/Test/TestOpDefs.cpp
+1-0mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+1-0mlir/lib/Dialect/ArmNeon/Transforms/LowerContractToNeonPatterns.cpp
+7-05 files

LLVM/project 2297e0dllvm/lib/Transforms/Utils MoveAutoInit.cpp, llvm/test/Transforms/MoveAutoInit loop-store.ll

[MoveAutoInit] Fix for miscompilation for #150120 (#173961)

Fixes the miscompilation discussed for the PR #164882 as part of
generalizing the optimization for the issue #150120.

Without this commit, MoveAutoInit moves the store instruction to a
different branch which does not dominate the user dominator node. This
results in UB at runtime. The example in the test case is specifically
for an irreducible loop, in which all the predecessor may not dominate
user dominator head.

To fix this problem, we've introduced a new check to verify if the
predecessor of the user dominator node does in fact dominate user
dominator node before deciding that it is the node where the instruction
will be moved to.
DeltaFile
+59-0llvm/test/Transforms/MoveAutoInit/loop-store.ll
+2-1llvm/lib/Transforms/Utils/MoveAutoInit.cpp
+61-12 files

LLVM/project 2cc4d45mlir/include/mlir/Bindings/Python IRCore.h, mlir/python CMakeLists.txt

[MLIR][Python] Add a DSL for defining dialects in Python bindings (#169045)

Python bindings for the IRDL dialect were introduced in #158488. They
are currently usable—for constructing IR and dynamically loading modules
that contain `irdl.dialect` into MLIR. However, there are still several
pain points when working with them:

* The IRDL IR-building interface is not very intuitive and tends to be
quite verbose.
* We do not yet have the corresponding `OpView` classes for IRDL-defined
operations.

To address these issues, I propose creating a wrapper (effectively a
small “DSL”) on top of the existing IRDL Python bindings. This wrapper
aims to simplify IR construction and automatically generate the
corresponding `OpView` types. A simple example is shown below.

Currently, using the IRDL bindings looks like this:


    [72 lines not shown]
DeltaFile
+471-0mlir/python/mlir/dialects/ext.py
+340-0mlir/test/python/dialects/ext.py
+4-3mlir/include/mlir/Bindings/Python/IRCore.h
+1-0mlir/python/CMakeLists.txt
+816-34 files

LLVM/project db4405ellvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-rounding-intrinsics.ll

InstCombine: Infer nnan/ninf on rounding intrinsics (#177770)

DeltaFile
+52-42llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll
+8-0llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+60-422 files

LLVM/project b98e160llvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Fix a crash in TTI

Created using spr 1.3.7
DeltaFile
+4-1llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+4-11 files

LLVM/project 2f94635llvm/lib/Transforms/InstCombine InstCombineSimplifyDemanded.cpp, llvm/test/Transforms/InstCombine simplify-demanded-fpclass-fptrunc-round.ll simplify-demanded-fpclass-fptrunc.ll

InstCombine: Infer nnan and ninf on fptrunc (#177769)

Teach SimplifyDemandedFPClass to do this, although this is
not yet applied directly to the cast.
DeltaFile
+31-21llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc-round.ll
+19-19llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc.ll
+11-11llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+61-513 files