LLVM/project 211314dllvm/include/llvm/ADT STLForwardCompat.h STLExtras.h, llvm/unittests/ADT STLForwardCompatTest.cpp STLExtrasTest.cpp

[ADT] Add is_sorted_constexpr, equivalent to C++20 std::is_sorted  (#180867)

`std::is_sorted` is not `constexpr` until Cpp20, so need custom `is_sorted_constexpr` function.
DeltaFile
+36-0llvm/unittests/ADT/STLForwardCompatTest.cpp
+18-0llvm/include/llvm/ADT/STLForwardCompat.h
+10-0llvm/unittests/ADT/STLExtrasTest.cpp
+8-0llvm/include/llvm/ADT/STLExtras.h
+72-04 files

LLVM/project b39ab2ellvm/lib/Target/RISCV RISCVInstrInfo.cpp, llvm/test/CodeGen/RISCV make-compressible-zilsd.mir

[RISCV] Use PADD_DW instead of ADDD for GPRPair copy on RV32 with P extension (#181316)

DeltaFile
+2-2llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+2-2llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
+4-42 files

LLVM/project 2b5eb2dclang/docs ClangIRCleanupAndEHDesign.md, clang/include/clang/CIR/Dialect/IR CIROps.td

[CIR][docs] Add cir.catch_param to ClangIR cleanup and EH design doc (#181284)

This updates the ClangIR cleanup and exception handling design document
to describe the requirement to use cir.catch_param operations to begin
the catch regions of a cir.try operation in the structured form of CIR.

This also includes minor changes to the descriptions in the CIROps.td
definitions of cir.try and cir.catch_param
DeltaFile
+32-1clang/docs/ClangIRCleanupAndEHDesign.md
+2-1clang/include/clang/CIR/Dialect/IR/CIROps.td
+34-22 files

LLVM/project 7046ceeclang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/test/Sema/AArch64 pcdphint-atomic-store.c

fixup!

A few small tidyups
DeltaFile
+7-6clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+4-4llvm/lib/Target/AArch64/AArch64InstrFormats.td
+4-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+15-103 files

LLVM/project 07ee679llvm/test/Transforms/LowerMatrixIntrinsics select.ll

feedback

Created using spr 1.3.7
DeltaFile
+2-2llvm/test/Transforms/LowerMatrixIntrinsics/select.ll
+2-21 files

LLVM/project 674d546clang/lib/CodeGen/TargetBuiltins ARM.cpp, clang/lib/Sema SemaARM.cpp

[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin

Add `__arm_atomic_store_with_stshh` implementation as defined
in the ACLE. Validate that the arguments passed are correct, and
lower it to the stshh intrinsic plus an atomic store with the
allowed orderings.

Gate this on FEAT_PCDPHINT so that availability matches
hardware support for the `STSHH` instruction. Use an i64
immediate and side-effect modeling to satisfy tablegen and decoding.
DeltaFile
+140-0clang/lib/Sema/SemaARM.cpp
+48-0clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+31-0clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+29-0clang/test/Sema/AArch64/pcdphint-atomic-store.c
+13-0llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+10-2llvm/lib/Target/AArch64/AArch64InstrFormats.td
+271-25 files not shown
+298-211 files

LLVM/project de9f320mlir/include/mlir/Dialect/IRDL/IR IRDLOps.td

[mlir][irdl] Add IsolatedFromAbove trait to irdl.operation, irdl.attribute and irdl.type (#181108)

https://github.com/llvm/llvm-project/pull/180556 depend it.Prevent CSE
from hoisting pure operations from the irdl.operation region into the
irdl.dialect region. You can see
https://github.com/llvm/llvm-project/pull/180556#issuecomment-3889133389.
DeltaFile
+3-3mlir/include/mlir/Dialect/IRDL/IR/IRDLOps.td
+3-31 files

LLVM/project b217e5copenmp/runtime/test/tasking issue-94260-2.c

[OpenMP][lit] Disable flaky test tasking/issue-94260-2.c (#176452)

The test sporadically fails on Linux. See
https://github.com/llvm/llvm-project/issues/176451 for more info.

Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
DeltaFile
+3-0openmp/runtime/test/tasking/issue-94260-2.c
+3-01 files

LLVM/project d521863mlir/include/mlir/Dialect/XeGPU/IR XeGPUAttrs.td XeGPUOps.td, mlir/lib/Dialect/XeGPU/IR XeGPUDialect.cpp

[MLIR][XeGPU] Add support for Convert Layout from Wg to Sg (#178922)

DeltaFile
+91-25mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
+106-0mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
+30-6mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
+11-11mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+4-6mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
+4-0mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
+246-483 files not shown
+250-549 files

LLVM/project a2f7504clang/include/clang/Basic DiagnosticSemaKinds.td, clang/lib/CodeGen/TargetBuiltins ARM.cpp

[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin

Add `__arm_atomic_store_with_stshh` implementation as defined
in the ACLE. Validate that the arguments passed are correct, and
lower it to the stshh intrinsic plus an atomic store with the
allowed orderings.

Gate this on FEAT_PCDPHINT so that availability matches
hardware support for the `STSHH` instruction. Use an i64
immediate and side-effect modeling to satisfy tablegen and decoding.
DeltaFile
+136-0clang/lib/Sema/SemaARM.cpp
+48-0clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+31-0clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
+13-0llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+10-2llvm/lib/Target/AArch64/AArch64InstrFormats.td
+9-0clang/include/clang/Basic/DiagnosticSemaKinds.td
+247-24 files not shown
+265-210 files

LLVM/project 59553faclang/docs ReleaseNotes.rst, clang/lib/Lex Preprocessor.cpp

[clang] avoid reentering header-name lexing on nested macro expansion (#179151)

Fixes #178635

---

This PR addressed the issue when header-name _lexing_ reentered on
nested macro expansion.

`__has_include`/`__has_embed` lex a header name by calling
`LexHeaderName`, and neither expects nested expansion in that context.

If `__has_include` appears inside the header name expression (e.g.,
`__has_include(__has_include)`, or `__has_embed(__has_include)`)


https://github.com/llvm/llvm-project/blob/6a18039298174562a38f28ca06d12dcbf7f14f06/clang/lib/Lex/PPMacroExpansion.cpp#L1252

macro expansion reenters `LexHeaderName` and hits the assertion

    [5 lines not shown]
DeltaFile
+9-3clang/lib/Lex/Preprocessor.cpp
+11-0clang/test/Preprocessor/embed___has_embed_parsing_errors.c
+10-0clang/test/Preprocessor/has_include.c
+1-0clang/docs/ReleaseNotes.rst
+31-34 files

LLVM/project b3ca0dfmlir/include/mlir/IR BuiltinAttributes.td BuiltinAttributes.h, mlir/lib/AsmParser AttributeParser.cpp

[mlir][IR] Separate `DenseStringElementsAttr` from `DenseElementsAttr`
DeltaFile
+93-17mlir/include/mlir/IR/BuiltinAttributes.td
+38-39mlir/lib/IR/BuiltinAttributes.cpp
+27-12mlir/unittests/IR/AttributeTest.cpp
+27-10mlir/lib/AsmParser/AttributeParser.cpp
+7-30mlir/include/mlir/IR/BuiltinAttributes.h
+14-8mlir/lib/CAPI/IR/BuiltinAttributes.cpp
+206-1163 files not shown
+211-1239 files

LLVM/project 9deb4fdllvm/lib/CodeGen TwoAddressInstructionPass.cpp, llvm/test/CodeGen/AMDGPU twoaddr-regsequence-keep-copy-on-use.mir

[CodeGen][AMDGPU] TwoAddress: Only skip undef COPY at REG_SEQUENCE lowering when there is Live info or no uses for subreg (#175598)

Currently, the compiler doesn't create a COPY for undef operands while
lowering REG_SEQUENCE, and only if LIS information is available, it
propagates the undef flag to the subreg uses. So, if LIS isn't
available, we can end up with some uses without def of those lanes.
Now, we check which lanes are used in a single scan of
use_nodbg_operands() per REG_SEQ, and perform the skip of the COPY only
if LIS is avaible (as undef will be propagated later) or if there are no
uses for that lane.
There is still a scan of the use list, but now it's only one per REG_SEQ
and I think it's necessary, as there is no guarantee to have LIS or
other analysis pass information at this stage.

This is a proposal fix for issue:
https://github.com/llvm/llvm-project/issues/175596

---------

Co-authored-by: Carl Ritson <critson at perlfu.co.uk>
DeltaFile
+69-0llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
+17-2llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+86-22 files

LLVM/project ede1a96llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanConstruction.cpp, llvm/test/Transforms/LoopVectorize multiple-early-exits.ll unsupported_early_exit.ll

[LV] Vectorize early exit loops with multiple exits. (#174864)

Building on top of the recent changes to introduce BranchOnTwoConds,
this patch adds support for vectorizing loops with multiple early exits,
all dominating a countable latch. The early exits must form a
dominance chain, so we can simply check which early exit has been taken
in dominance order.

Currently LoopVectorizationLegality ensures that all exits other than
the latch must be uncountable. handleUncountableEarlyExits now collects
those uncountable exits and processes each exit.

In the vector region, we compute if any exit has been taken, by taking
the OR of all early exit conditions (EarlyExitConds) and checking if
there's
any active lane.

If the early exit is taken, we exit the loop and compute which early
exit

    [8 lines not shown]
DeltaFile
+535-241llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
+198-63llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+68-59llvm/test/Transforms/LoopVectorize/unsupported_early_exit.ll
+70-0llvm/test/Transforms/LoopVectorize/multi_early_exit.ll
+58-1llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
+14-20llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
+943-3848 files not shown
+985-40814 files

LLVM/project 8c162b7lldb/include/lldb/Core SourceManager.h, lldb/source/Core SourceManager.cpp

[lldb] Pass the frame's language type to the highlighter (#181094)

This threads the frame's language type through the source manager to the
highlighter. Previously, we'd always pass "unknown" as the language type
and rely on the language plugin to figure out the language based on the
file extension.

This change is motivated by #170250. For languages like Swift or Rust
that don't have an upstream language plugin, we need the frame's
language for syntax highlighting.
DeltaFile
+16-15lldb/source/Core/SourceManager.cpp
+12-7lldb/include/lldb/Core/SourceManager.h
+2-1lldb/source/Target/StackFrame.cpp
+30-233 files

LLVM/project 913f154clang/lib/Sema SemaType.cpp, clang/lib/Serialization ASTReaderDecl.cpp

Revert "[Serialization] Stop demote var definition as declaration (#172430) (…"

This reverts commit 013b345af992f66d5ecfd168844ebfc6956ccae0.
DeltaFile
+0-110clang/test/Modules/var-inst-def.cppm
+0-104clang/test/Modules/pr149404-02.cppm
+0-94clang/test/Modules/demote-var-def.cpp
+24-52clang/lib/Sema/SemaType.cpp
+0-47clang/test/Modules/pr172241.cppm
+14-0clang/lib/Serialization/ASTReaderDecl.cpp
+38-4076 files

LLVM/project 94b5adcllvm/utils/git requirements_formatting.txt requirements_formatting.txt.in

[Github] Update requirements_formatting.txt (#181184)

We should not need to be explicitly adding transitive dependencies to
requirements_formatting.txt.in to enforce a higher version is used. We
also should always be using == to ensure a strict version match, not
just a compatible version (~=). This patch removes transitive
dependencies introduced in 6fdf93c5d812197dd5dc9362f324b944105b2e8e and
updates the lockfile (although only unnecessary packages are removed).
DeltaFile
+4-65llvm/utils/git/requirements_formatting.txt
+0-3llvm/utils/git/requirements_formatting.txt.in
+4-682 files

LLVM/project 04fbb1dclang-tools-extra/test/clang-tidy check_clang_tidy.py, clang-tools-extra/test/clang-tidy/checkers/modernize pass-by-value-multi-fixes.cpp pass-by-value-header.cpp

[clang-tidy] Header check support for check_clang_tidy.py (#175735)

As of AI-Usage: Gemini CLI was used for pre-commit review and finding
testcases that need to be updated.

Closes [#133515](https://github.com/llvm/llvm-project/issues/133515)

---------

Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
DeltaFile
+178-45clang-tools-extra/test/clang-tidy/check_clang_tidy.py
+5-9clang-tools-extra/test/clang-tidy/checkers/modernize/pass-by-value-multi-fixes.cpp
+4-9clang-tools-extra/test/clang-tidy/checkers/modernize/pass-by-value-header.cpp
+2-9clang-tools-extra/test/clang-tidy/checkers/modernize/concat-nested-namespaces.cpp
+4-3clang-tools-extra/test/clang-tidy/checkers/modernize/Inputs/concat-nested-namespaces/modernize-concat-nested-namespaces.h
+2-5clang-tools-extra/test/clang-tidy/checkers/performance/unnecessary-value-param-header.cpp
+195-805 files not shown
+208-8211 files

LLVM/project b58677allvm/docs LangRef.rst, llvm/test/CodeGen/X86 ctselect.ll

[LangRef][ConstantTime] Add documentation for llvm.ct.select.* constant-time intrinsics (#181042)

This PR introduces and documents the llvm.ct.select.* constant-time
intrinsics, providing timing-independent selection operations for
security-sensitive code. The LangRef is updated with syntax, semantics,
supported types, and usage guidance.

Additionally, test coverage is extended with a new <8 x float> variant
(llvm.ct.select.v8f32) and corresponding X86 codegen tests to ensure
correct lowering on both x64 and x32 targets.
DeltaFile
+188-0llvm/test/CodeGen/X86/ctselect.ll
+132-0llvm/docs/LangRef.rst
+320-02 files

LLVM/project 0b887bellvm/utils/gn/secondary/llvm/lib/Target/Hexagon BUILD.gn

[gn build] Port 892ac614bf8f
DeltaFile
+1-0llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn
+1-01 files

LLVM/project ec0b22fllvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize select-cmp.ll pr44488-predication.ll

[VPlan] Reuse introduces-broadcast logic in narrowToSingleScalars (#174444)

narrowToSingleScalarRecipes' operands check is a bit too restrictive by
permitting a single user. Factor out and reuse the existing
introduces-broadcast logic to improve results.
DeltaFile
+18-18llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+6-12llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
+6-6llvm/test/Transforms/LoopVectorize/select-cmp.ll
+3-8llvm/test/Transforms/LoopVectorize/pr44488-predication.ll
+33-444 files

LLVM/project 424686amlir/docs/Bindings Python.md

[MLIR][Docs] Add docs about Python-defined dialects (#181372)

This PR adds documentation to the MLIR Python bindings introducing
support for Python-defined dialects (initially introduced in #169045).
DeltaFile
+36-1mlir/docs/Bindings/Python.md
+36-11 files

LLVM/project 48fb939mlir/docs/Bindings Python.md

fix code
DeltaFile
+1-0mlir/docs/Bindings/Python.md
+1-01 files

LLVM/project 892ac61llvm/lib/Target/Hexagon HexagonGlobalScheduler.cpp, llvm/test/CodeGen/Hexagon global-sched-skip-vsub_fake.ll pull-up-slots.mir

Add HexagonGlobalScheduler pass (#180803)

This patch adds the HexagonGlobalScheduler, a post-packetization pass
that performs global instruction scheduling and pull-up optimizations to
improve packet density on Hexagon VLIW architecture.

The scheduler operates on scheduling regions (super-blocks with single
entry and multiple exits) and attempts to move instructions across basic
blocks to fill packet slots more efficiently. It supports both
speculative and predicative scheduling modes.

Key features:
- Global instruction scheduling across basic blocks
- Speculative scheduling with safety checks
- Predicative scheduling using predication
- Local pull-up within basic blocks
- Dual jump formation
- Branch optimizations
- Liveness preservation using HexagonLiveVariables

    [24 lines not shown]
DeltaFile
+5,319-0llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
+831-0llvm/test/CodeGen/Hexagon/global-sched-skip-vsub_fake.ll
+363-0llvm/test/CodeGen/Hexagon/pull-up-slots.mir
+311-0llvm/test/CodeGen/Hexagon/avoid-debug-increment.mir
+305-0llvm/test/CodeGen/Hexagon/dbg-label-pullup.ll
+268-0llvm/test/CodeGen/Hexagon/pull-delayed-new.mir
+7,397-010 files not shown
+7,711-416 files

LLVM/project 637e9bdlibcxx/utils/ci/lnt run-benchmarks

[libc++] Run all the microbenchmarks in run-benchmarks (#181374)

Running all the benchmarks does not significantly increase the total
time, and it ensures that what we upload to LNT corresponds exactly to
what's in the test suite.
DeltaFile
+1-4libcxx/utils/ci/lnt/run-benchmarks
+1-41 files

LLVM/project ca8a6b8clang/docs ReleaseNotes.rst, clang/lib/AST ExprConstant.cpp

[Clang] fix crash when constexpr evaluation encounters uninitialized GCC vector (#180293)

Fixes #180044

---

This patch addresses the regression caused by
https://github.com/llvm/llvm-project/commit/77534291fcbd2c784c54e39a60895e4f60f19742.
The crash happens because


https://github.com/llvm/llvm-project/blob/85d94e17144f2ca250c91b827b59e6ddea675d31/clang/lib/AST/ExprConstant.cpp#L4294

tries to read a vector element when the `APValue` is still
`Indeterminate` or `Absent`. These changes _populate_ vector `APValue`
to ensure elements exist before access.
DeltaFile
+34-1clang/test/SemaCXX/constexpr-vectors-access-elements.cpp
+16-0clang/lib/AST/ExprConstant.cpp
+1-0clang/docs/ReleaseNotes.rst
+51-13 files

LLVM/project 320d0b5clang/include/clang/StaticAnalyzer/Core/PathSensitive CoreEngine.h ExprEngine.h, clang/lib/StaticAnalyzer/Core CoreEngine.cpp ExprEngine.cpp

[NFCI][analyzer] Regularize NodeBuilder classes (#180960)

This commit removes virtual methods from the `NodeBuilder` class
hierarchy (because they were only relevant for the "enclosing builder"
feature of `StmtNodeBuilder` which was not used anywhere), then moves
the classes `IndirectGotoNodeBuilder` and `SwitchNodeBuilder` into this
hierarchy. (Previously they were independent classes with some
duplicated logic in the `generateNode()`-like functions.)

Updating `SwitchNodeBuilder` is a prerequisite for activating the
`BranchCondition` checkers on the condition of the `switch` statement
because `CheckerContext` requires the presence of a `NodeBuilder`.

Updating `IndirectGotoNodeBuilder` doesn't have any analogous goals --
I'm just doing it for the sake of consistency.

I also added some very basic tests because this area wasn't properly
covered by the old tests.

I'm planning to do more cleanup (e.g. the removal of `StmtNodeBuilder`)
in follow-up commits.
DeltaFile
+110-0clang/test/Analysis/switch-basics.c
+85-0clang/test/Analysis/indirect-goto-basics.c
+33-52clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h
+25-55clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
+18-28clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
+4-3clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
+275-1386 files

LLVM/project a820c8butils/bazel/llvm-project-overlay/mlir BUILD.bazel

[bazel] Port a1d7cda.
DeltaFile
+1-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+1-01 files

LLVM/project 40c778alibcxx/test/std/ranges/range.factories/range.iota.view indices.pass.cpp

[libc++][NFC] Remove already fixed FIXME from range.iota.view/indices.pass.cpp (#181344)

DeltaFile
+0-3libcxx/test/std/ranges/range.factories/range.iota.view/indices.pass.cpp
+0-31 files

LLVM/project 2bcc2c7mlir/docs/Bindings Python.md

fix wording
DeltaFile
+1-1mlir/docs/Bindings/Python.md
+1-11 files