LLVM/project 7940a5alibc/docs configure.rst

[libc][NFC] update configure page with wchar flag (#177050)

Whenever the cmake runs it updates configure.rst based on the contents
of config.json. This PR just applies the change generated after #176110
DeltaFile
+1-0libc/docs/configure.rst
+1-01 files

LLVM/project 35bf2d9llvm/lib/Target/AMDGPU SIInstrInfo.cpp SIInstrInfo.h

remove leftover code
DeltaFile
+0-14llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+1-9llvm/lib/Target/AMDGPU/SIInstrInfo.h
+1-232 files

LLVM/project 6ef98c6libc/startup/linux gnu_property_section.cpp

[libc] Cast in startup to silence warning (#177048)

In #174772 gcc warns on an implicit cast from `ElfW(Xword)` (unsigned
long
int) to `ElfW(word)` (unsigned int). This PR adds an explicit cast.
DeltaFile
+1-1libc/startup/linux/gnu_property_section.cpp
+1-11 files

LLVM/project c491352utils/bazel/third_party_build pybind.BUILD robin_map.BUILD

[bazel] Add cc_library loads to third_party_build files (#177042)

This will become required in bazel 9
DeltaFile
+2-0utils/bazel/third_party_build/pybind.BUILD
+2-0utils/bazel/third_party_build/robin_map.BUILD
+2-0utils/bazel/third_party_build/vulkan_headers.BUILD
+2-0utils/bazel/third_party_build/nanobind.BUILD
+1-0utils/bazel/third_party_build/pfm.BUILD
+1-0utils/bazel/third_party_build/mpc.BUILD
+10-01 files not shown
+11-07 files

LLVM/project 39b74fdflang/include/flang/Optimizer/Transforms Passes.td, flang/lib/Optimizer/Transforms CMakeLists.txt

[flang][cuda] Add cuf.device_address conversion into separate pass (#177035)

Some conversion are better done later in the pipeline. Add
cuf.device_address conversion in its own pass so it can be scheduled
late.

The pattern will be removed from CUFOpConversion once this pass has
landed.
DeltaFile
+120-0flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
+14-0flang/test/Fir/CUDA/cuda-device-address.mlir
+5-0flang/include/flang/Optimizer/Transforms/Passes.td
+1-0flang/lib/Optimizer/Transforms/CMakeLists.txt
+140-04 files

LLVM/project 646255dllvm/test/Transforms/AtomicExpand/Xtensa atomicrmw-expand.ll

[Xtensa] Fix atomicrmw-expand test. (#177038)

DeltaFile
+1-1llvm/test/Transforms/AtomicExpand/Xtensa/atomicrmw-expand.ll
+1-11 files

LLVM/project 61d215fllvm/lib/Transforms/Vectorize SLPVectorizer.cpp

Fix formatting

Created using spr 1.3.7
DeltaFile
+6-6llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+6-61 files

LLVM/project 98c60ablld/COFF InputFiles.cpp, llvm/include/llvm/LTO LTO.h

[NFC][LTO] Move isPreservedName out of IRSymtab into LTO's Symbol 

This resolves the FIXME in IRSymtab and cleans up the semantics of the
IRSymtab. The list of preserved symbols really shouldn't be seen as a
property of the IR symbol table, since it's an LTO-specific concern, and
it's very tenuous to claim that this information is actually present in
the bitcode file to be exposed through its symbol table.

Instead, this PR moves this logic into LTO's view of the symbol, which
allows consumers to determine preserved-ness themselves. This was broken
out of #164916; this prevents that PR from introducing a circular
dependency, but it still seems like an independently good idea by virtue
of the above.
DeltaFile
+13-3llvm/lib/LTO/LTO.cpp
+2-11llvm/lib/Object/IRSymtab.cpp
+4-3llvm/lib/LTO/ThinLTOCodeGenerator.cpp
+4-1llvm/include/llvm/LTO/LTO.h
+4-1lld/COFF/InputFiles.cpp
+27-195 files

LLVM/project ab4adedllvm/lib/Target/Sparc DelaySlotFiller.cpp SparcInstrInfo.td, llvm/test/CodeGen/SPARC 2011-01-19-DelaySlot.ll

[SPARC] Prevent RESTORE from sourcing from %o7 in call delay slots (#172593)

Combining instructions that reads from %o7 with a RESTORE in call delay
slots will result in a RESTORE instruction that reads from %o7, which
has been overwritten by the call instruction, resulting in junk values
being produced.

This should fix the issue with `test-suite::lencod.test`.
DeltaFile
+111-21llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+42-11llvm/lib/Target/Sparc/DelaySlotFiller.cpp
+5-5llvm/lib/Target/Sparc/SparcInstrInfo.td
+158-373 files

LLVM/project 95d1dd5clang/lib/CIR/CodeGen CIRGenBuiltinX86.cpp, clang/test/CIR/CodeGen/X86 prefetchw-builtin.c

[CIR] Add X86 prefetch builtins (#168051)

Add support for the X86 sse2 `prefetch` builtin, `prefetchh` and `prefetchw` builtins to ClangIR
DeltaFile
+36-0clang/test/CIR/CodeGen/X86/prefetchw-builtin.c
+30-0clang/test/CIR/CodeGenBuiltins/X86/sse-builtins.c
+30-0clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+96-03 files

LLVM/project 6574918libc/include elf.yaml, libc/startup/linux gnu_property_section.cpp gnu_property_section.h

[libc][linux] add support to parse PT_GNU_PROPERTY (#174772)

In order to add Control-flow Enforcement Technology (CET) Shadow Stack
(SHSTK) support, we need to parse the `PT_GNU_PROPERTY` program header
and the corresponding section to evaluate if the binary being started
was compiled with the necessary support.

PS: This is my first PR to llvm-libc, I might have made obvious styling
mistakes so I'd appreciate any feedback or suggestions to improve it.

I have a prototype branch using this change to enable SHSTK support:
https://github.com/jakos-sec/llvm-project/tree/add-shstk-support
DeltaFile
+133-0libc/startup/linux/gnu_property_section.cpp
+45-0libc/startup/linux/gnu_property_section.h
+14-0libc/startup/linux/CMakeLists.txt
+7-0libc/include/elf.yaml
+4-0libc/startup/linux/do_start.cpp
+203-05 files

LLVM/project 0844d9fllvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/test/Transforms/PhaseOrdering/X86 pr48223.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+228-13llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+2-6llvm/test/Transforms/PhaseOrdering/X86/pr48223.ll
+230-192 files

LLVM/project ddd220fllvm/test/CodeGen/AArch64 atomic-ops-lse.ll trampoline.ll

[AArch64] Consider MOVaddr* as cheap if fuse-adrp-add

These pseudo-instructions usually translate into a pair of adrp+add and
have a single cycle latency on some micro-architectures.
DeltaFile
+88-88llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+43-34llvm/test/CodeGen/AArch64/trampoline.ll
+55-0llvm/test/CodeGen/AArch64/cheap-as-a-move-MOVaddr.ll
+34-19llvm/test/CodeGen/AArch64/machine-outliner-loh.ll
+14-12llvm/test/CodeGen/AArch64/cfguard-checks.ll
+12-10llvm/test/CodeGen/AArch64/atomic-ops.ll
+246-16310 files not shown
+291-19416 files

LLVM/project a746d42llvm/lib/Target/AMDGPU SIPreEmitPeephole.cpp, llvm/test/CodeGen/AMDGPU issue176578.ll insert-skip-from-vcc.mir

AMDGPU: Fix assert when looking for s_and_b64 + vcc branch pattern (#177031)

Fixes #176578
DeltaFile
+137-0llvm/test/CodeGen/AMDGPU/issue176578.ll
+56-0llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir
+3-2llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+196-23 files

LLVM/project 41cfe83libc/src/__support/wchar character_converter.cpp character_converter.h, libc/src/stdio/printf_core char_converter.h

[libc] Reland %lc support in printf (#176110)

Add support for %lc in printf by calling internal wcrtomb function and
relevant end-to-end sprintf test.

Additionally, made the following changes:
- Modified printf parser for recognizing length modifier
- Added two internal error codes. 
- Added a flag to disable wchar support on windows platform.
- To keep printf interface header only, converted wcrtomb and
CharacterConverter to header only implementation and removed the cpp
source.

Resolves GPU libc issues in #169983 and original issue: #166598

---------

Co-authored-by: shubhe25p <shubhp at mbm3a24.local>
Co-authored-by: Joseph Huber <huberjn at outlook.com>
DeltaFile
+0-176libc/src/__support/wchar/character_converter.cpp
+163-5libc/src/__support/wchar/character_converter.h
+97-1libc/test/src/stdio/sprintf_test.cpp
+44-6libc/src/stdio/printf_core/char_converter.h
+0-50libc/src/__support/wchar/wcrtomb.cpp
+35-4libc/src/__support/wchar/wcrtomb.h
+339-24210 files not shown
+426-25316 files

LLVM/project cf6a281llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUInstPrinter.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

fix review comments
DeltaFile
+1-25llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+20-4llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+2-2llvm/test/MC/AMDGPU/gfx11_asm_vop2-fake16.s
+2-2llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt
+2-2llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
+2-2llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
+29-372 files not shown
+29-418 files

LLVM/project 561f1a4lld/COFF InputFiles.cpp, llvm/include/llvm/LTO LTO.h

[NFC] Move isPreservedName out of IRSymtab into LTO's Symbol 
DeltaFile
+13-3llvm/lib/LTO/LTO.cpp
+2-11llvm/lib/Object/IRSymtab.cpp
+4-3llvm/lib/LTO/ThinLTOCodeGenerator.cpp
+4-1llvm/include/llvm/LTO/LTO.h
+4-1lld/COFF/InputFiles.cpp
+27-195 files

LLVM/project 5c24d56llvm/lib/Target/AMDGPU SIPreEmitPeephole.cpp, llvm/test/CodeGen/AMDGPU issue176578.ll insert-skip-from-vcc.mir

AMDGPU: Fix assert when looking for s_and_b64 + vcc branch pattern

Fixes #176578
DeltaFile
+137-0llvm/test/CodeGen/AMDGPU/issue176578.ll
+56-0llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir
+3-2llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+196-23 files

LLVM/project d377911lldb/include/lldb/Host/windows PseudoConsole.h, lldb/source/Host/windows PseudoConsole.cpp

[LLDB] Close previously opened handles in `PseudoConsole` (#176775)

In
https://github.com/llvm/llvm-project/pull/175837#issuecomment-3749408432
I mentioned that any handles that were previously opened and haven't
been closed since, won't be closed in the destructor nor in
`OpenPseudoConsole`.

In this PR, I added `Close` calls to these methods. Calling `Close()` is
a no-op if the handles are invalid.
DeltaFile
+11-2lldb/source/Host/windows/PseudoConsole.cpp
+8-0lldb/include/lldb/Host/windows/PseudoConsole.h
+19-22 files

LLVM/project d34c30bllvm/lib/Target/AArch64/GISel AArch64PreLegalizerCombiner.cpp AArch64O0PreLegalizerCombiner.cpp

AArch64/GlobalISel: Use LibcallLoweringInfo in utils (#176946)

Wire up the boilerplate to get the query for bzero from
LibcallLoweringInfo instead of TargetLowering.
DeltaFile
+16-7llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+13-5llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
+4-3llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+2-1llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h
+35-164 files

LLVM/project 85d64d1offload/libomptarget omptarget.cpp, offload/libomptarget/OpenMP Mapping.cpp

[Offload] Cast to `void *` in the debug message (#177019)

There are a few places where data types based on character array or
string are printed in the debug message while they do not represent
strings. Such expressions should be casted to `void *` unless they
represent actual strings. Change also includes casting from integral
type to pointer type when appropriate.
DeltaFile
+13-7offload/libomptarget/OpenMP/Mapping.cpp
+7-4offload/plugins-nextgen/common/src/PluginInterface.cpp
+6-4offload/libomptarget/omptarget.cpp
+26-153 files

LLVM/project 72e9d30llvm/include/llvm/ADT STLExtras.h, llvm/unittests/ADT STLExtrasTest.cpp

Revert "Reland "[STLExtras] Add a template for detecting whether a type has an equality comparison operator" (#176893)"

This reverts commit 2984a28612bb8c56cd85d858b00319a24c95409a.

Another buildbot is unhappy with another static assert: https://lab.llvm.org/buildbot/#/builders/108/builds/22080
DeltaFile
+0-27llvm/unittests/ADT/STLExtrasTest.cpp
+0-11llvm/include/llvm/ADT/STLExtras.h
+0-382 files

LLVM/project d2c40c3llvm/lib/Transforms/Vectorize LoopVectorize.cpp

[LV] Check if VPlan contains FindLast reduction directly (NFC).

Directly check the VPlan to see if there are any FindLast reductions.
Currently this is NFC, but checking in the VPlan is more future proof,
e.g. if reductions are simplified, removed or transformed. Then checking
in legacy LoopVectorizationLegality is inaccruate.
DeltaFile
+19-9llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+19-91 files

LLVM/project 0c812a6clang/lib/CodeGen CGHLSLBuiltins.cpp

mark assert-only variables from 11b1836 maybe_unused (#177011)

Fix for variables added in 11b18362822759ac1592cee5b857943fa2320f8c.
DeltaFile
+2-2clang/lib/CodeGen/CGHLSLBuiltins.cpp
+2-21 files

LLVM/project db2f0f8mlir/include/mlir/Dialect/XeGPU/IR XeGPUTypes.td, mlir/lib/Conversion/VectorToXeGPU VectorToXeGPU.cpp

[MLIR][XeGPU]: Reject `tensor_desc` types with unknown bitwidth (#173922)

Fixes https://github.com/llvm/llvm-project/issues/173851

1. Only allow XeGPU_ScalarType element types in `xegpu::TensorDescType`
(via verifier, keeping mlir::Type params in api)
2. Fix `VectorToXeGPU` to prevent vectors with invalid TensorDescType
element types from lowering
DeltaFile
+6-0mlir/test/Dialect/XeGPU/invalid.mlir
+4-0mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
+4-0mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+1-1mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
+15-14 files

LLVM/project b23840dllvm/test/Transforms/LoopUnroll/branch-weights-freq unroll-epilog.ll peel.ll

[LoopUnroll][NFC] Simplify recent block frequency tests

Refactor a number of recent tests in
`llvm/test/Transforms/LoopUnroll/branch-weights-freq` to make it
easier to understand and extend them.

The changes mostly resemble the refactoring I recently did in
PR#165635 in response to reviewer comments:
- For each case (e.g., each `-unroll-count` value in
  `unroll-epilog.ll`), group all FileCheck directives together.  That
  way, while digesting a single case, the reader does not need to sift
  through all other cases and a complex FileCheck prefix scheme.
- Reduce CFG testing.  Drop many FileCheck directives that check for
  all basic block labels and branches, and drop the cryptic
  `-implicit-check-not` that excludes others.  Instead, just use
  positive checks for every loop body (represented by `call void @f`),
  for relevant metadata, and for the branch instructions to which the
  metadata is attached, and use simple negative checks (e.g.,
  `-implicit-check-not='!prof'`) to be sure we have not missed any.

    [4 lines not shown]
DeltaFile
+184-122llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-epilog.ll
+31-43llvm/test/Transforms/LoopUnroll/branch-weights-freq/peel.ll
+34-37llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial.ll
+249-2023 files

LLVM/project cf63329llvm/docs LangRef.rst

[IR] Update dereferencable wording after opaque pointers (#176991)

The documentation for the dereferenceable argument attribute mentioned
pointee types. Making a distinction around a pointee type no longer
makes sense after the move to opaque pointers.
DeltaFile
+4-5llvm/docs/LangRef.rst
+4-51 files

LLVM/project 7d4865emlir/include/mlir/Dialect/NVGPU/Transforms MemoryAccessOpInterfacesImpl.h, mlir/lib/Dialect/NVGPU/Transforms MemoryAccessOpInterfacesImpl.cpp

clang-format
DeltaFile
+3-4mlir/lib/Dialect/NVGPU/Transforms/MemoryAccessOpInterfacesImpl.cpp
+0-1mlir/include/mlir/Dialect/NVGPU/Transforms/MemoryAccessOpInterfacesImpl.h
+3-52 files

LLVM/project 0784819llvm/lib/Target/AMDGPU FLATInstructions.td

[AMDGPU] Allow predicates for alias in VFLAT_Real_AllAddr_gfx1250 (#176987)

Expose alias definition earlier, and add a new argument to specify the predicates for alias definition.
 This is for downstream development and NFC for now.
DeltaFile
+8-14llvm/lib/Target/AMDGPU/FLATInstructions.td
+8-141 files

LLVM/project 1061207llvm/lib/Target/PowerPC PPCTargetTransformInfo.cpp PPCTargetTransformInfo.h, llvm/test/Analysis/CostModel/PowerPC ld-st-with-length.ll

[PowerPC] cost modeling for length type VP intrinsic load/store (#168938)

Override and fill in the target hooks for PPC that allow opt to cost
using length style VP intrinsics for load/store.
DeltaFile
+321-0llvm/test/Analysis/CostModel/PowerPC/ld-st-with-length.ll
+96-1llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+15-0llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+432-13 files