LLVM/project 159ec47mlir/lib/Conversion/FuncToEmitC FuncToEmitC.cpp

fix after rebase
DeltaFile
+2-2mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
+2-21 files

LLVM/project 1cd8a0fmlir/docs SymbolsAndSymbolTables.md

address comments
DeltaFile
+3-2mlir/docs/SymbolsAndSymbolTables.md
+3-21 files

LLVM/project 2dcc5a9mlir/docs SymbolsAndSymbolTables.md, mlir/include/mlir/IR SymbolTable.h SymbolInterfaces.td

[mlir][IR] Fix symbol table visibility API
DeltaFile
+51-40mlir/include/mlir/IR/SymbolInterfaces.td
+52-32mlir/lib/IR/SymbolTable.cpp
+11-5mlir/include/mlir/IR/SymbolTable.h
+7-4mlir/docs/SymbolsAndSymbolTables.md
+4-3mlir/lib/Interfaces/FunctionImplementation.cpp
+7-0mlir/unittests/IR/SymbolTableTest.cpp
+132-844 files not shown
+142-9210 files

LLVM/project 126061emlir/test/Conversion/MPIToLLVM mpitollvm.mlir

fix stacking regression
DeltaFile
+3-3mlir/test/Conversion/MPIToLLVM/mpitollvm.mlir
+3-31 files

LLVM/project ad9dc60mlir/lib/Transforms ViewOpGraph.cpp, mlir/lib/Transforms/Utils DialectConversion.cpp

[mlir][IR][Rewrite] Use split inherent/discardable attribute APIs (#218907)

Migrate core IR implementation, interfaces, rewriting, pass printing,
and focused tests to explicit discardable or inherent attribute access.

Assisted-by: Codex
DeltaFile
+11-9mlir/test/lib/IR/TestVisitorsGeneric.cpp
+10-7mlir/lib/Transforms/Utils/DialectConversion.cpp
+11-3mlir/lib/Transforms/ViewOpGraph.cpp
+8-5mlir/test/lib/IR/TestFunc.cpp
+6-6mlir/unittests/Pass/PassManagerTest.cpp
+7-5mlir/unittests/Interfaces/DataLayoutInterfacesTest.cpp
+53-3522 files not shown
+122-7628 files

LLVM/project 0d79745llvm/lib/Target/X86 X86ISelDAGToDAG.cpp, llvm/test/CodeGen/X86 is_fpclass.ll cmp.ll

[X86] Emit ADD instead of SHL by 1 when shrinking TEST with a mask (#217508)

The immediate-TEST shrink rewrites (and x, 0x7fffffffffffffff) == 0 into
SHL64ri $1 + TEST64rr, expecting the redundant TEST to be "subsequently
eliminated" (per the comment). For shift amounts 1-3 it never is:
isDefConvertible() rejects those SHLs so that they stay convertible to
LEA, and the dead TEST survives into final binaries.

Emit ADD64rr x, x instead when the shift amount is 1. Doubling is value-
and ZF-identical to the shift at the same encoding length, executes on
more ports, and ADDrr is def-convertible, so the peephole really does
fold the TEST away, leaving add+jcc/setcc instead of shl+test+jcc/setcc.

The shape is common: it is Rust libstd's panic-counter fast path
(GLOBAL_PANIC_COUNT & ~(1 << 63) == 0, inlined at every
std::thread::panicking() check -- 249 copies in uutils coreutils) and
LLVM's own is_fpclass zero-class lowering, as the is_fpclass.ll diff
shows.


    [7 lines not shown]
DeltaFile
+101-0llvm/test/CodeGen/X86/cmp.ll
+15-1llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+2-4llvm/test/CodeGen/X86/is_fpclass.ll
+118-53 files

LLVM/project e803e57clang/test/CodeGen/RISCV rvp-intrinsics.c, cross-project-tests/intrinsic-header-tests riscv_packed_simd.c

[RISCV][P-ext] Support Packed "Q-format" Multiply Parts Accumulate Intrinsics(#217918)
DeltaFile
+388-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+177-0llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+169-0llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+126-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+88-4llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+87-0llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+1,035-46 files not shown
+1,210-912 files

LLVM/project aa09790mlir/lib/Dialect/SparseTensor/Transforms Sparsification.cpp SparseReinterpretMap.cpp, mlir/lib/Dialect/SparseTensor/Transforms/Utils CodegenUtils.cpp

[mlir][SparseTensor] Use split discardable/inherent attribute APIs (#218904)

Migrate SparseTensor IR, lowering, code generation, and loop emission to
explicit discardable or operation-specific attribute access.

Assisted-by: Codex
DeltaFile
+5-4mlir/lib/Dialect/SparseTensor/Transforms/SparseVectorization.cpp
+5-4mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
+4-3mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
+2-2mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
+2-2mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
+2-2mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
+20-172 files not shown
+23-198 files

LLVM/project 7b6eb69mlir/docs SymbolsAndSymbolTables.md

address comments
DeltaFile
+3-2mlir/docs/SymbolsAndSymbolTables.md
+3-21 files

LLVM/project 20ad451mlir/lib/Conversion/FuncToEmitC FuncToEmitC.cpp, mlir/lib/Conversion/FuncToLLVM FuncToLLVM.cpp

[mlir][Func][Async][EmitC] Use split discardable/inherent attribute APIs (#218905)

Use operation-specific accessors and explicit discardable attribute APIs
in the Func, Async, and EmitC dialects and their associated conversions.

Assisted-by: Codex
DeltaFile
+25-19mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
+16-5mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
+7-4mlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
+5-4mlir/lib/Dialect/EmitC/IR/EmitC.cpp
+4-4mlir/lib/Dialect/Func/IR/FuncOps.cpp
+4-3mlir/lib/Dialect/Async/IR/Async.cpp
+61-397 files not shown
+76-5213 files

LLVM/project a908adbllvm/lib/Target/AMDGPU SIInstrInfo.cpp, llvm/test/CodeGen/AMDGPU cttz_zero_poison.ll ctlz_zero_poison.ll

[AMDGPU] Fix unsaturated add when moving 64-bit ctlz/cttz to the VALU (#216707)

The ffbh/ffbl add is saturated via a clamp modifier, but on gfx6/7/8 it
lowers to V_ADD_CO_U32_e32, which has no clamp operand, so
ctlz/cttz.i64(0, false) returns 31 instead of 64 there

ffbh/ffbl only produce 0..31 or -1, so uaddsat(x, 32) is just x | 32

Use V_OR_B32_e32 instead, which needs no clamp and works everywhere
DeltaFile
+484-8llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
+4-7llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+2-2llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
+2-2llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
+492-194 files

LLVM/project 2e32621mlir/include/mlir/Dialect/Shape/IR ShapeBase.td ShapeOps.td, mlir/test/Dialect/Shape ops.mlir invalid.mlir

[MLIR][Shape] Enable strict property assembly format (#218903)

Enable the strict properties assembly format mode for the Shape dialect.

Bind the broadcast diagnostic attribute directly. Keep its optional
clause unambiguous after variadic operands, and cover the custom and
rejected attr-dict spellings.

Assisted-by: Codex
DeltaFile
+10-1mlir/test/Dialect/Shape/ops.mlir
+10-1mlir/test/Dialect/Shape/invalid.mlir
+2-1mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
+1-0mlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
+23-34 files

LLVM/project 776df1emlir/docs SymbolsAndSymbolTables.md, mlir/include/mlir/IR SymbolTable.h SymbolInterfaces.td

[mlir][IR] Fix symbol table visibility API
DeltaFile
+51-40mlir/include/mlir/IR/SymbolInterfaces.td
+52-32mlir/lib/IR/SymbolTable.cpp
+11-5mlir/include/mlir/IR/SymbolTable.h
+7-4mlir/docs/SymbolsAndSymbolTables.md
+4-3mlir/lib/Interfaces/FunctionImplementation.cpp
+7-0mlir/unittests/IR/SymbolTableTest.cpp
+132-844 files not shown
+142-9210 files

LLVM/project 1341c9dclang/docs/analyzer checkers.md

Update clang/docs/analyzer/checkers.md

Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
DeltaFile
+1-2clang/docs/analyzer/checkers.md
+1-21 files

LLVM/project 8d735a0mlir/lib/Conversion/ArithToLLVM ArithToLLVM.cpp, mlir/lib/Dialect/LLVMIR/IR LLVMDialect.cpp

[mlir][LLVM] Verify that constant attribute and result types match

`llvm.mlir.constant` only checked that the kind of the value attribute suits
the kind of the result type, never that the types themselves agree. All of the
following verified:

  %0 = llvm.mlir.constant(1 : index) : i64
  %1 = llvm.mlir.constant(1 : i8) : i16
  %2 = llvm.mlir.constant(dense<1> : vector<4xi32>) : vector<4xi64>

Translation ignores the attribute type and uses the result type, so the
attribute type was effectively decorative for integers, and passes that read it
back could observe a type that has nothing to do with the value.

Require exact type equality for integer attributes and exact element type
equality for integer elements attributes, mirroring the `AllTypesMatch`
constraint `arith.constant` gets from ODS. The op cannot use that trait itself
because `value` is an `AnyAttr` that also holds `StringAttr` and `ArrayAttr`.
The element type check is also run on the scalable vector path, which

    [11 lines not shown]
DeltaFile
+56-0mlir/test/Dialect/LLVMIR/invalid.mlir
+42-11mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+12-12mlir/test/Dialect/LLVMIR/roundtrip.mlir
+23-0mlir/test/Conversion/ArithToLLVM/constant-index-bitwidth.mlir
+11-4mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
+7-7mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
+151-3414 files not shown
+180-5920 files

LLVM/project 0181e05clang/docs/analyzer checkers.md

Explanation for suppressing the fp report.
DeltaFile
+3-1clang/docs/analyzer/checkers.md
+3-11 files

LLVM/project 6f21734libcxx/utils/ci/lnt dispatch-benchmarks

[libc++] Remove confusing summary (#218897)

It doesn't add much more than the preceding output.
DeltaFile
+1-9libcxx/utils/ci/lnt/dispatch-benchmarks
+1-91 files

LLVM/project 7d62df8llvm/include/llvm/Transforms/Utils LoopUtils.h, llvm/lib/Transforms/Utils LoopUtils.cpp

Fixups
DeltaFile
+128-181llvm/test/Transforms/LoopVectorize/compress-idioms.ll
+40-9llvm/test/Transforms/LoopVectorize/compress-idioms-negative-tests.ll
+16-20llvm/test/Transforms/LoopVectorize/AArch64/compress-idioms.ll
+12-16llvm/test/Transforms/LoopVectorize/VPlan/compress-idioms.ll
+9-1llvm/lib/Transforms/Utils/LoopUtils.cpp
+4-3llvm/include/llvm/Transforms/Utils/LoopUtils.h
+209-2301 files not shown
+212-2337 files

LLVM/project 737f1a3clang/docs/analyzer checkers.md

Remove test and text for dereference in return statement.
DeltaFile
+2-12clang/docs/analyzer/checkers.md
+2-121 files

LLVM/project 1f3365dllvm/lib/CodeGen MachineCSE.cpp, llvm/test/CodeGen/PowerPC machine-cse-pre-succ-args.mir

CodeGen: Fix MachineCSE PRE insert point with SUCC_ARGS

Hoist to getBlockEndInsertPt() instead of getFirstTerminator(), so a hoisted
instruction lands before the SUCC_ARGS cluster rather than inside it.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+99-0llvm/test/CodeGen/PowerPC/machine-cse-pre-succ-args.mir
+1-1llvm/lib/CodeGen/MachineCSE.cpp
+100-12 files

LLVM/project 3cf438cllvm/lib/CodeGen MachineLICM.cpp, llvm/test/CodeGen/X86 machinelicm-hoist-before-succ-args.mir

MachineLICM: Fix preheader insertion point with SUCC_ARGS

Hoist loop-invariant instructions to getBlockEndInsertPt() instead of
getFirstTerminator(), so they land before the SUCC_ARGS cluster rather
than inside it.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+48-0llvm/test/CodeGen/X86/machinelicm-hoist-before-succ-args.mir
+2-2llvm/lib/CodeGen/MachineLICM.cpp
+50-22 files

LLVM/project 560672fllvm/lib/CodeGen MachineBasicBlock.cpp MachineVerifier.cpp, llvm/lib/CodeGen/MIRParser MIParser.cpp

CodeGen: Represent block arguments on MachineBasicBlock

The receiver half of the block-argument representation: a block declares a list
of virtual registers that receive values forwarded by each predecessor's
SUCC_ARGS. Unlike a PHI, a block argument is defined by the block itself, not by
an instruction.

MachineBasicBlock holds the argument list, printed and parsed as an "arguments:"
block header line. MachineRegisterInfo maps each argument to its defining block,
so getDefBlock works for these registers. The verifier treats an argument as
defined at block entry and requires each predecessor to supply one matching
SUCC_ARGS.

This is only building infrastructure, and is not yet used.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+131-0llvm/test/CodeGen/MIR/X86/block-args.mir
+53-0llvm/test/CodeGen/MIR/X86/block-args-invalid.mir
+48-2llvm/lib/CodeGen/MachineVerifier.cpp
+37-0llvm/lib/CodeGen/MIRParser/MIParser.cpp
+34-0llvm/lib/CodeGen/MachineBasicBlock.cpp
+32-0llvm/test/CodeGen/MIR/X86/block-args-named-blocks.mir
+335-213 files not shown
+540-619 files

LLVM/project c74ef0dllvm/include/llvm/CodeGen MachineBasicBlock.h, llvm/lib/CodeGen MachineVerifier.cpp

CodeGen: Add SUCC_ARGS pseudo-instruction

The sender half of a block-argument representation for Machine IR: a
"reverse PHI" that forwards values from a predecessor's bottom to a
successor block's arguments along one CFG edge. Operand 0 is the successor
block; the rest are the forwarded value registers, mapped positionally.

Like PHI, SUCC_ARGS is edge-specific: it must stay in its block, so it is
excluded from CSE and hoisting, and it defines no register but is not dead.
SUCC_ARGS are clustered contiguously immediately before the terminators,
mirroring how PHIs are clustered at the top of a block; the verifier
enforces this and the succ_args() range and getBlockEndInsertPt() let
consumers work with the cluster. Inert; no producer emits it yet.

Co-Authored-By: Claude <noreply at anthropic.com> (Claude Opus 4.8)
DeltaFile
+40-0llvm/test/CodeGen/MIR/X86/succ-args.mir
+34-0llvm/test/CodeGen/X86/machine-cse-succ-args.mir
+33-0llvm/test/MachineVerifier/X86/succ-args-empty.mir
+29-0llvm/test/CodeGen/X86/machinelicm-succ-args.mir
+26-0llvm/include/llvm/CodeGen/MachineBasicBlock.h
+22-0llvm/lib/CodeGen/MachineVerifier.cpp
+184-010 files not shown
+280-416 files

LLVM/project 0ff91a7llvm/include/llvm/CodeGen MIRYamlMapping.h MachineFunction.h, llvm/lib/CodeGen MachineFunction.cpp MIRPrinter.cpp

CodeGen: Add UsesBlockArgs MachineFunction property

Bringup guard for block argument support.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+20-0llvm/test/CodeGen/MIR/X86/uses-block-args-property.mir
+3-1llvm/include/llvm/CodeGen/MachineFunction.h
+2-0llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+2-0llvm/include/llvm/CodeGen/MIRYamlMapping.h
+1-0llvm/lib/CodeGen/MachineFunction.cpp
+1-0llvm/lib/CodeGen/MIRPrinter.cpp
+29-16 files

LLVM/project 01bb84clldb/source/Target Process.cpp Memory.cpp, lldb/unittests/Target MemoryTest.cpp

[lldb] Guard MemoryCache::ReadRanges against a short buffer (#218706)

`Process::DoReadMemoryRanges` asserts the caller's buffer is long enough
before it writes into it, and returns empty ranges when asserts are off.
`MemoryCache::ReadRanges` writes a cache hit into the same buffer with
no
such check, in `lldb/source/Target/Memory.cpp`:

```
316:      results.push_back(buffer.take_front(len));   // take_front clamps 16 -> 8
317:      buffer = buffer.drop_front(len);             // asks to drop 16 from 8
318:      memcpy(results.back().data(), cached, len);  // writes 16 into 8 bytes
```

With assertions on, `MutableArrayRef::drop_front` aborts one line before
the `memcpy`, so the new test dies on the wrong message:

```
Death test: { read_results = cache.ReadRanges(ranges, short_buffer); }

    [21 lines not shown]
DeltaFile
+38-1lldb/unittests/Target/MemoryTest.cpp
+11-0lldb/source/Target/Memory.cpp
+2-1lldb/source/Target/Process.cpp
+51-23 files

LLVM/project 9448898clang/lib/StaticAnalyzer/Core MemRegion.cpp

[analyzer][NFC] Clean up `MemRegion.cpp` and align with llvm coding style (#218860)

A small change that was previously mixed into #218264
DeltaFile
+11-12clang/lib/StaticAnalyzer/Core/MemRegion.cpp
+11-121 files

LLVM/project 9e415dbllvm/include/llvm/CodeGen DIE.h

[CodeGen][DWARF][NFC] Add casts to a few asserts to avoid msvc warning. (#218386)

Fix some comparisons to correct the msvc warning: C4805: '==': unsafe
mix of type 'IntType' and type 'bool' in operation

Assisted-by: LLM.
DeltaFile
+4-2llvm/include/llvm/CodeGen/DIE.h
+4-21 files

LLVM/project 5264488llvm/lib/Transforms/Vectorize LoopVectorizationLegality.cpp, llvm/test/Transforms/LoopVectorize compress-idioms-negative-tests.ll

Add out-of-loop use check
DeltaFile
+32-0llvm/test/Transforms/LoopVectorize/compress-idioms-negative-tests.ll
+10-2llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+42-22 files

LLVM/project 48d0361llvm/lib/Transforms/Vectorize VPRecipeBuilder.h

Add comment
DeltaFile
+3-0llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+3-01 files

LLVM/project c7079d1llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlan.h, llvm/test/Transforms/LoopVectorize compress-idioms.ll

[LoopVectorize] Support vectorization of compressing patterns in VPlan

RFC link: https://discourse.llvm.org/t/rfc-loop-vectorization-of-compress-store-expand-load-patterns/86442

This adds loop vectorizer support for "compressing" patterns,
for example:

```
int dst_idx = 0;
for (int i = 0; i < n; i++) {
  if (cond[i])
    dst[dst_idx++] = src[i];
}
```

Can be vectorized with a `llvm.masked.compressstore` as:

```
int dst_idx = 0;

    [52 lines not shown]
DeltaFile
+424-0llvm/test/Transforms/LoopVectorize/compress-idioms.ll
+157-0llvm/test/Transforms/LoopVectorize/VPlan/compress-idioms.ll
+132-0llvm/test/Transforms/LoopVectorize/AArch64/compress-idioms.ll
+112-15llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+60-4llvm/lib/Transforms/Vectorize/VPlan.h
+49-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+934-1915 files not shown
+1,117-2721 files