Reapply "AMDGPU: Annotate group size ABI loads with range metadata (#185420)"
This reverts commit d5685ac6db0ae4cbca1745f18d8f2f7dc7d673a5.
Fix off by one error. The end of the range is open.
[MLIR][LLVMIR] Preserve byval alignment in memcpy after inlining (#185433)
This PR adds alignment attributes to the generated memcpy intrinsics
after inlining functions with byval arguments.
Revert "[ASan] Enable Internalization for 'asanrtl.bc' in Driver (#18… (#185458)
…2825)"
Enabling internalization of `asanrtl.bc` breaks the asan reporting on
hip side , due to duplicate `__asan_report_XXX` calls in code object and
the llvm-ir.
This reverts commit dc26edd9b6602857b67f35c8d2f6fe4ed13c8137.
[libc++][NFC] Simplify most of `optional.observe` (#185252)
- Hoist `operator*()`, `operator->()`, `value()` into their respective
`optional_storage_base` to reduce the amount of concepts flying around.
- `value_or()` has been deliberately left out since that seems to
produce extra (superfluous) error messages during invalid template
instantiation.
[LLVM][RISCV] Regenerate ct.select test CHECK lines
Update CHECK lines to match the new constant-time AND/OR/XOR expansion
from the CT_SELECT legalization fix.
Fix affinity type, handle unexpected iterator loop body and accumulate affinity entry for one register call
- Generate kmpTaskAffinityInfoTy based on platform and create a helper
in OMPIRBuilder so that we can use it in OpenMPToLLVMIRTranslation and
OMPIRBuilder
- Handle invalid iterator loop body and add unit test
- Accumulate affinity info and only one register call for a task
construct
- remove `this->` in member fucntion
[RISCV] Handle sign_extend of i32 in insert_vector_elt for RV32 (#185548)
On RV32 with <N x i64> vectors, inserting a value that is a
sign_extend of an i32 only uses the lower 32 bits, so it can be
lowered without scalar legalization, same as i32 constants.
[Clang] Remove clang/test/AST/Bytecode/constexpr.c (#185447)
Remove duplicate test since Sema/constexpr.c handles the constexpr
tests.
Discussed in #181965
[libc][math] correct the output of `asinpif` and `acospi` (#185544)
Currently, we have accuracy issues and some points fail in the asinpif
exhaustive test. This change fixes it by increasing the degree of the
used polynomial
```
-- Testing for FE_TONEAREST in range [0x0, 0x7f800000) --
Failed to match Func(x) against LIBC_NAMESPACE::testing::mpfr::get_mpfr_matcher<Op>( x, Func(x), 0.5, rounding).
Match value not within tolerance value of MPFR result:
Input decimal: 0.00000011348398487598387873731553554534912109375000
Input bits: 0x33F3B47B = (S: 0, E: 0x0067, M: 0x0073B47B)
Match decimal: 0.00000003612307253320068411994725465774536132812500
Match bits: 0x331B25BD = (S: 0, E: 0x0066, M: 0x001B25BD)
MPFR result: 0.00000003612307608591436292044818401336669921875000
MPFR rounded: 0x331B25BE = (S: 0, E: 0x0066, M: 0x001B25BE)
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[Clang][AMDGPU] Change __fp16 to _Float16 in builtin definitions (#185446)
Change the type signature of `SWMMAC, load, cvt` builtins from `__fp16
to _Float16` in the tablegen builtin definitions.
[HLSL][DXIL][SPRIV] Added WaveActiveProduct intrinsic (#184645)
From issue #99165, adds the implementation of WaveActiveProduct. This
time with the new types for SPIRVTypeInst
- [x] Implement WaveActiveProduct clang builtin,
- [x] Link WaveActiveProduct clang builtin with hlsl_intrinsics.h
- [x] Add sema checks for WaveActiveProduct to
CheckHLSLBuiltinFunctionCall in SemaChecking.cpp
- [x] Add codegen for WaveActiveProduct to EmitHLSLBuiltinExpr in
CGBuiltin.cpp
- [x] Add codegen tests to
clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl
- [x] Add sema tests to
clang/test/SemaHLSL/BuiltIns/WaveActiveProduct-errors.hlsl
- [x] Create the int_dx_WaveActiveProduct intrinsic in
IntrinsicsDirectX.td
- [x] Create the DXILOpMapping of int_dx_WaveActiveProduct to 119 in
DXIL.td
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[RISCV] Make Zbc imply Zbkc. (#185543)
Zbkc contains 2 of the 3 instructions from Zbc. Making Zbc imply Zbkc
will make the __riscv_zbkc define be set when Zbc is enabled.
This does not change the diagnostics printed by the assembler.
There's a PR to add this rule to the ISA manual too
https://github.com/riscv/riscv-isa-manual/pull/2524