[SCEV] Drop samesign in getLoopInvariantPredicate
SCEV's getLoopInvariantPredicate tries to replace a comparison of an IV
against a loop-invariant value with the comparison value on loop entry.
For that it tries to prove that the comparison is:
- (A) monotonic: i.e. if c_i is true, then c_{i+1} is true,
- (B) guards the backedge: the backedge is taken only if c_i is true.
Then each c_i may be replaced with c_0.
It works for the icmp instruction without the samesign flag.
With the samesign flag, however, the comparison is poison when its
operands have different signs.
To prove the backedge guard (B), we may rely on picking that poison as
true, while proving the monotonicity (A) may need the same poison
to be picked as false.
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[mlir][X86] Fold VNNI operand unpacking into contractions (#232800)
Matmul loops often transpose and flatten a VNNI-packed RHS before
`vector.contract`, hiding the packed lanes from the X86 AMX lowering
patterns and preventing the contraction from being lowered to an AMX dot
product (nanokernels).
- Adding a contract-loop preparation pattern for bf16 and i8 matmul
loops where the RHS is unpacked using a transpose and shape cast.
- Reading the RHS in packed VNNI layout and contract over the K and
VNNI-lane dimensions, preserving fastmath attributes.
- Supporting already-packed and flat RHS reads, leading unit dimensions,
and dynamically sized innermost dimensions.
- Rejecting layouts that cannot be packed safely.
In follow-up PRs we could add more normalization patterns:
- Accepting other/similar pattern expressing the same (like generated by
triton-cpu)
- CanonicalizeLoopIV: Fold exact round-downs and safe casts so reads can
use the loop IV directly.
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[IndVarSimplify][NFC] Add tests for loop-invariant samesign compares
Add tests for replacing a samesign compare of an IV with a
loop-invariant value by its value on loop entry.
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
[AArch64][llvm] Fix incorrect diagnostic (index/immediate in simm9) (#229563)
Improve the error message in the simm9 diagnostics and use the
correct word `immediate` instead of `index`. This was noticed when
creating the `CFLT` instructions for Armv9.8-A, but would have
caused a lot of unrelated churn if merged as part of that change.
Co-authored-by: Martin Wehking <martin.wehking at arm.com>
[NFC][CIR][AMDGPU] Build fence scope triple from enums (#235907)
Drop the legacy amdgcn-amd-amdhsa string, matching how OffloadArch and
SPIR targets build the AMDGPU triple
[OpenMP] Switch the underlying type of llvm::omp::Version to int
It was unsigned before. The goal is to unify Version and VersionRange,
and VersionRange stores versions as int.
[CIR][AMDGPU][SPIR-V] Emit AMDGPU atomic memory metadata for spirv64-amd (#236037)
Match classic codegen so AMD SPIR-V atomic RMW ops do not lower to CAS
loops
[mlir][test] Initialise targets in WindowsArm64.cpp (#236074)
Fixes #229719 / f330666ac78564db6651c81cd1d4658ff27758a8.
Without initializing targets the test fails:
https://lab.llvm.org/buildbot/#/builders/207/builds/23792
C:\Users\tcwg\llvm-worker\flang-arm64-windows-msvc\llvm-project\mlir\unittests\ExecutionEngine\WindowsArm64.cpp:144
Failed
Unable to find target for this triple (no targets are registered)
Relates to #232235.
[OpenMP] Replace cast operator with member function
Replace the explicit cast operator to the underlying type with a
member function "value()" that returns the underlying value.
[AArch64][DAG] Add ISel for SVE floating-point non-temporal loads and stores. (#232171)
loads/stores with non-temporal metadata for types 1: float point
scalable length vector or 2: float point fixed length wider vectors with
sve-vector-length bigger than 128 get error:
```
LLVM ERROR: Cannot select: t7: nxv2f32,ch = masked_load<(non-temporal load unknown-size from %ir.a, align 1)> t0, t2, poison:i64, t4, poison:nxv2f32
```
This patch fixes above error:
1: if the type has related non-temporal load/store instructions, select
the instructions
2: if the type has no non-temporal load/store instructions, select the
normal load/store instread of crash
[mlir][vector][tensor] Scalarize select conditions from broadcast and splat (#235593)
## Summary
Canonicalize `arith.select` with a mask produced by `vector.broadcast`
of a scalar `i1`, or by `tensor.splat`, to a select on the scalar
condition.
```python
%mask = vector.broadcast %p : i1 to vector<4xi1>
%result = arith.select %mask, %a, %b : vector<4xi1>, vector<4xi32>
```
becomes:
```python
%result = arith.select %p, %a, %b : vector<4xi32>
```
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