LLVM/project 609355alibcxx/docs/Status Cxx26Papers.csv

release notes 23 -> 24
DeltaFile
+1-1libcxx/docs/Status/Cxx26Papers.csv
+1-11 files

LLVM/project a35bcaellvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

AMDGPU/GlobalISel: Explicitly widen scalar to i32 for load and store (#210095)

Affects f16 and bf16. Earlier, they were widened to f32 and s32 respectively.
The actual error was the artifact combiner creating a copy between f32/i32
which fails in the machine verifier. Maybe we could create a bitcast there.
However i32 is more efficient for us and matches well with how argument
lowering keeps f16 and bf16 in i32 copies to/from physical registers.
Also starting from f16 store, G_STORE %0(f16), %1(p1) :: (store (f16),
and doing widen scalar to 32 bit type, i32 makes more sense since store
will store 16 least significant bits G_STORE %0(i32), %1(p1) :: (store (f16)
compared to G_STORE %0(f32), %1(p1) :: (store (f16), which looks incorrect if
we assume input was really in f32 format.
DeltaFile
+2,008-2,008llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,164-1,164llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+963-963llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+556-556llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+486-486llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+108-108llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+5,285-5,28515 files not shown
+5,362-5,36821 files

LLVM/project 8fc0b82libcxx/docs/Status Cxx26Issues.csv Cxx23Papers.csv

release notes 23 -> 24
DeltaFile
+4-4libcxx/docs/Status/Cxx26Issues.csv
+2-2libcxx/docs/Status/Cxx23Papers.csv
+1-1libcxx/docs/Status/Cxx23Issues.csv
+7-73 files

LLVM/project ac41c58clang/docs InternalsManual.rst

[clang][docs] Fix include path in InternalsManual (#209458)

The paths `include/Basic/StmtNodes.td` and `include/AST/Expr*.h` in the
Clang Internals Manual are incorrect.
DeltaFile
+2-2clang/docs/InternalsManual.rst
+2-21 files

LLVM/project 0000fd1llvm/test/Transforms/VectorCombine/AArch64 load-widening.ll, llvm/test/Transforms/VectorCombine/X86 load-widening.ll

[VectorCombine] load-widening.ll - add test coverage for all 4 x86-64 cpu levels and aarch64 endian test coverage (#210690)

Removed x86 endianess tests which makes no sense (and are likely to misbehave) and add equivalent test coverage to aarch64

Noticed while reviewing #209775
DeltaFile
+458-0llvm/test/Transforms/VectorCombine/AArch64/load-widening.ll
+4-4llvm/test/Transforms/VectorCombine/X86/load-widening.ll
+462-42 files

LLVM/project 90c7db7libcxx/docs/ReleaseNotes 23.rst 24.rst

release notes 23 -> 24
DeltaFile
+0-5libcxx/docs/ReleaseNotes/23.rst
+2-0libcxx/docs/ReleaseNotes/24.rst
+2-52 files

LLVM/project 1a52064llvm/docs LangRef.rst, llvm/lib/Support UnicodeNameToCodepointGenerated.cpp

Merge branch 'main' into users/c8ef/generator
DeltaFile
+31,001-87,165llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
+36,531-36,463llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+35,948-24,498llvm/test/CodeGen/RISCV/clmul.ll
+24,053-23,916llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
+15,519-26,130llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
+0-32,980llvm/docs/LangRef.rst
+143,052-231,15225,225 files not shown
+1,976,109-1,266,12325,231 files

LLVM/project ca276b4llvm/lib/Target/RISCV RISCVTargetTransformInfo.cpp, llvm/lib/Transforms/Scalar ExpandMemCmp.cpp

[ExpandMemCmp][RISCV] Expand memcmp/bcmp for aligned pointers on strict-align targets (#209738)

`RISCVTTIImpl::enableMemCmpExpansion` previously disabled `memcmp`/`bcmp`
expansion whenever the target lacks unaligned scalar memory access. This is
too conservative: when both pointers are statically known to be
sufficiently aligned (e.g. `bcmp(ptr align 8, ptr align 8, 32)`), only
naturally aligned loads are needed, which are fine on strict-align
targets.

`ExpandMemCmp` now keeps a candidate load size only if, given the known
common alignment of the two pointers, the access is naturally aligned or
the target reports it via `allowsMisalignedMemoryAccesses`; otherwise it
falls back to the libcall. The query tests whether the access is
*allowed* (not *fast*), so it is a no-op for targets that already allow
unaligned access (X86, AArch64, ...).

The known alignment now also folds in the `align` attributes on the call
arguments (`CallBase::getParamAlign`), not just the pointer value.


    [5 lines not shown]
DeltaFile
+1,540-1,269llvm/test/CodeGen/RISCV/memcmp.ll
+465-943llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+641-0llvm/test/Transforms/ExpandMemCmp/RISCV/memcmp-strict-align.ll
+43-2llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
+14-7llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+2-0llvm/test/Transforms/ExpandMemCmp/RISCV/lit.local.cfg
+2,705-2,2216 files

LLVM/project 8e4a7ablibcxx/docs/ReleaseNotes 24.rst 23.rst

release notes 23 -> 24
DeltaFile
+1-0libcxx/docs/ReleaseNotes/24.rst
+0-1libcxx/docs/ReleaseNotes/23.rst
+1-12 files

LLVM/project 51b8166llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir, llvm/test/CodeGen/RISCV clmul.ll

Merge branch 'main' into users/c8ef/atomic_minmax
DeltaFile
+23,904-12llvm/test/CodeGen/RISCV/clmul.ll
+5,784-5,784llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+5,003-5,051llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+4,606-4,641llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+4,366-3,719llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+4,324-3,437llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+47,987-22,6447,715 files not shown
+335,666-185,6337,721 files

LLVM/project 2cdd343llvm/test/CodeGen/AMDGPU vector-reduce-smin.ll vector-reduce-smax.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.i16.ll insertelement.i8.ll

AMDGPU/GlobalISel: Fix legalizer lowering for G_EXTRACT/INSERT_VECTOR_ELT (#210094)

Use LLT::integer in bit twiddling lowering for extract/insert vector element.
DeltaFile
+2,741-4,467llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+1,627-4,750llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+990-990llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+975-439llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+8,357-11,51426 files not shown
+13,363-14,10532 files

LLVM/project c30b1fallvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers BUILD.gn

[gn build] Port b21fb937f165 (#210698)
DeltaFile
+1-1llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
+1-11 files

LLVM/project 1caf9e1mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE pack-unpack-mmt4d.mlir

[mlir][ArmSVE] Fix comment inconsistency for `pack_lhs` in `ArmSVE/pack-unpack-mmt4d.mlir` (NFC) (#210502)

This PR simply fix a comment inconsistency for `pack_lhs` in
[ArmSVE/pack-unpack-mmt4d.mlir](https://github.com/llvm/llvm-project/compare/main...FedericoBruzzone:nfc-armsve?expand=1#diff-7be071860c440806b8dad954ed61946e7e9f27e032ed6044a704f0c0f70e4407)
as identified in #208226.

Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
DeltaFile
+3-2mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-mmt4d.mlir
+3-21 files

LLVM/project 27fe16dllvm/lib/Transforms/Instrumentation AddressSanitizer.cpp, llvm/test/Instrumentation/AddressSanitizer darwin-mte-tag-stripping.ll

[Darwin][ASan] Strip MTE-tags for inlined shadow translations (#204827)

https://github.com/llvm/llvm-project/pull/166453 stripped these tags
when the runtime performed the mem-to-shadow translation, but did not
account for ASan's inline translations. When an MTE-tagged address gets
translated, the tag bits are right-shifted too, resulting in a very high
address that faults when accessed.

This patch strips the MTE-tag bits before applying the translation on
Apple platforms.

rdar://180032780
DeltaFile
+36-0llvm/test/Instrumentation/AddressSanitizer/darwin-mte-tag-stripping.ll
+6-0llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+42-02 files

LLVM/project d9c8806clang/include/clang/StaticAnalyzer/Core AnalyzerOptions.h, clang/include/clang/StaticAnalyzer/Core/PathSensitive SMTConv.h

[analyzer] Fix _BitInt support & casting behavior for Z3 symbolic execution (#210525)

Forces symbolic cast to be enabled for z3 symbolic execution, and
switches away from Ctx.getTypeSize for getting the bit width of integral
types.

The current patch might be a bit problematic for z3 cross-check, as this
relies on symbolic integer cast to be always on. I am not sure if
turning on ShouldSupportSymbolicIntegerCasts would cause issues for the
supported range-based solver, so I only kept it turned on when
AnalysisConstraintsOpt == Z3ConstraintsModel.

Assisted-by: Codex
DeltaFile
+18-37clang/include/clang/StaticAnalyzer/Core/PathSensitive/SMTConv.h
+36-0clang/test/Analysis/z3/z3-bitint-arithmetic.c
+5-13llvm/lib/Support/Z3Solver.cpp
+3-5clang/lib/StaticAnalyzer/Core/ExprEngineC.cpp
+5-0clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
+4-0clang/test/Analysis/z3/z3-logicalexpr-eval.c
+71-553 files not shown
+77-579 files

LLVM/project 35a6fd0llvm/test/CodeGen/AMDGPU div_i128.ll div_v2i128.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

GlobalISel: Use extended LLTs in lshr narrow combine
DeltaFile
+3,024-2,355llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+3,080-2,174llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+1,894-2,067llvm/test/CodeGen/AMDGPU/div_i128.ll
+1,365-1,378llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+1,625-788llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+218-153llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+11,206-8,91510 files not shown
+12,049-9,47316 files

LLVM/project ba94b97llvm/lib/Target/AMDGPU AMDGPURegBankCombiner.cpp, llvm/test/CodeGen/AMDGPU global-saddr-load.ll

AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for applyD16Load
DeltaFile
+14-1llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+2-2llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+16-32 files

LLVM/project 297c44fllvm/test/CodeGen/AMDGPU llvm.log10.ll llvm.log.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fpow.ll

AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper

Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
DeltaFile
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log.ll
+2,760-1,251llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+912-86llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+536-218llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+290-131llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+11,694-4,8624 files not shown
+12,158-5,07110 files

LLVM/project 2fe9a5fllvm/lib/Target/AMDGPU AMDGPUPreLegalizerCombiner.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel combine-short-clamp.ll

AMDGPU/GlobalISel: Use integers for clamp i64 to i16 prelegalizer combine
DeltaFile
+26-46llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
+6-6llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+32-522 files

LLVM/project 54829fallvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU codegen-prepare-addrspacecast-non-null.ll

GlobalISel: Use extended LLTs in extract lowering
DeltaFile
+60-29llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+4-4llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+2-2llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+1-1llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+79-485 files

LLVM/project 05dc167llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel zextload.ll

AMDGPU/GlobalISel: Fix extending load narrow scalar

isAnyScalar is explicit LLT::scalar check but we want to narrow scalar
integer types as well.
DeltaFile
+6-7llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+7-82 files

LLVM/project 3480578llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-constant.mir

AMDGPU/GlobalISel: Use integer as MMO type for loads and stores lowering

We could get away with just the type from MMO in most cases, but MMO splitting
creates MMO with LLT::scalar and we prefer integer.
DeltaFile
+1,622-1,442llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,064-944llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+828-738llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+842-722llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+250-220llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+121-121llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+4,727-4,1878 files not shown
+4,995-4,28614 files

LLVM/project df526c1llvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp, llvm/test/CodeGen/AMDGPU fptrunc.f16.ll fptrunc.ll

GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering
DeltaFile
+1,282-1,453llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+264-432llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+364-243llvm/test/CodeGen/AMDGPU/fptrunc.ll
+238-239llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
+176-91llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+47-47llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+2,371-2,5056 files

LLVM/project c28dfc8llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.prefetch.inst.ll llvm.amdgcn.s.prefetch.data.ll, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-load.mir regbankselect-waterfall-call.mir

AMDGPU/GlobalISel: Use integers for read-any-lane split type
DeltaFile
+150-72llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
+106-106llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+33-17llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
+24-24llvm/test/CodeGen/AMDGPU/indirect-call.ll
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
+12-12llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
+341-2476 files not shown
+364-27212 files

LLVM/project 2b031c2llvm/test/CodeGen/AMDGPU/GlobalISel legalize-load-global.mir legalize-load-local.mir

AMDGPU/GlobalISel: Explicitly widen scalar to i32 for load and store

Affects f16 and bf16. Earlier, they were widened to f32 and s32 respectively.
The actual error was the artifact combiner creating a copy between f32/i32
which fails in the machine verifier. Maybe we could create a bitcast there.
However i32 is more efficient for us and matches well with how argument
lowering keeps f16 and bf16 in i32 copies to/from physical registers.
Also starting from f16 store, G_STORE %0(f16), %1(p1) :: (store (f16),
and doing widen scalar to 32 bit type, i32 makes more sense since store
will store 16 least significant bits G_STORE %0(i32), %1(p1) :: (store (f16)
compared to G_STORE %0(f32), %1(p1) :: (store (f16), which looks incorrect if
we assume input was really in f32 format.
DeltaFile
+2,008-2,008llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+1,164-1,164llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+963-963llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+556-556llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+486-486llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+108-108llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+5,285-5,28515 files not shown
+5,362-5,36821 files

LLVM/project 8abc269llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 pr209714.ll

[X86] combineShiftRightLogical - fold srl(vecreduce_umax(x),bw-1) as MOVMSK signbit reduction (#210281)

VectorCombine may have folded:
  icmp_eq(vecreduce_or(splatsign(x)),0) --> icmp_sgt(vecreduce_umax(x),-1)

which DAG folds to:
  srl(vecreduce_umax(x),bw-1).

This match attempts to lower:
  srl(vecreduce_umax(x),bw-1) --> icmp_ne(movmsk(x),0) "any_of negative"
  srl(not(vecreduce_umax(x)),bw-1) --> icmp_eq(movmsk(x),0) "none_of negative"

The correct fix would be to improve vecreduce_or costs to prevent
VectorCombine doing this, but that change is far too big to be merged
into 23.x - so I've created the narrow backend fix.

Fixes #209714
DeltaFile
+1,407-0llvm/test/CodeGen/X86/pr209714.ll
+32-0llvm/lib/Target/X86/X86ISelLowering.cpp
+1,439-02 files

LLVM/project 99efad6llvm/test/CodeGen/AMDGPU vector-reduce-smax.ll vector-reduce-smin.ll, llvm/test/CodeGen/AMDGPU/GlobalISel insertelement.i16.ll insertelement.i8.ll

AMDGPU/GlobalISel: Fix legalizer lowering for G_EXTRACT/INSERT_VECTOR_ELT

Use LLT::integer in bit twiddling lowering for extract/insert vector element.
DeltaFile
+2,741-4,467llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
+1,627-4,750llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+990-990llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+1,012-434llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+975-439llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+8,357-11,51426 files not shown
+13,363-14,10532 files

LLVM/project 25b75a1llvm/test/CodeGen/AMDGPU llvm.exp10.f64.ll llvm.exp.f64.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fshl.ll fshr.ll

AMDGPU/GlobalISel: Stop using changeTo in legalizer actions (#209203)

Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
DeltaFile
+855-425llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+783-389llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+759-377llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+253-160llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+232-138llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+58-80llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+2,940-1,56911 files not shown
+3,066-1,65117 files

LLVM/project 648aec1llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64ISelLowering.h

[AArch64] NFC: Factor out code from FP_TO_INT (SVE). (#207200)

This just moves out some of the SVE lowering code from
LowerVectorFP_TO_INT into a separate function, so that we can reuse that
in LowerVectorFP_TO_INT_SAT.
DeltaFile
+54-26llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-0llvm/lib/Target/AArch64/AArch64ISelLowering.h
+56-262 files

LLVM/project 31569a8llvm/test/CodeGen/AMDGPU llvm.log10.ll llvm.log.ll, llvm/test/CodeGen/AMDGPU/GlobalISel fpow.ll

AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper

Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
DeltaFile
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+3,598-1,588llvm/test/CodeGen/AMDGPU/llvm.log.ll
+2,760-1,251llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+912-86llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+536-218llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+290-131llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+11,694-4,8624 files not shown
+12,158-5,07110 files