LLVM/project 2a57482llvm/lib/CodeGen/SelectionDAG SelectionDAGBuilder.cpp

[SelectionDAGBuilder] Replace asserts inside LLVM_DEBUG (#199748)

These assert were inside an LLVM_DEBUG macro, meaning they were very
rarely if ever tested. The second "LowerFormalArguments emitted a value
with the wrong type!" assert would fire in a number of tests so has been
removed. The other was replaced with an all_of assert.

Noticed when looking at #198107 / #199412.
DeltaFile
+2-8llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+2-81 files

LLVM/project 3c16e92llvm/lib/Target/AArch64 AArch64TargetTransformInfo.cpp AArch64TargetTransformInfo.h, llvm/test/Transforms/EarlyCSE/AArch64 intrinsics-1xN.ll

[AArch64][TTI][EarlyCSE] Add support for ld1xN and st1xN intrinsics (#198765)

Handle ld1x2, ld1x3, ld1x4, st1x2, st1x3, st1x4 in:
- AArch64TTIImpl::getTgtMemIntrinsic
- AArch64TTIImpl::getOrCreateResultFromMemIntrinsic

This enables EarlyCSE to optimize these NEON load/store intrinsics.

To test the changes, a new testcase (intrinsics-1xN.ll) derived from
llvm/test/Transforms/EarlyCSE/AArch64/intrinsics.ll is added.
DeltaFile
+194-0llvm/test/Transforms/EarlyCSE/AArch64/intrinsics-1xN.ll
+28-3llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+0-6llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+222-93 files

LLVM/project 3d9cc99llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp

always diagnose unknown metadata
DeltaFile
+5-3llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+5-31 files

LLVM/project 090df8flibsycl/test lit.cfg.py, llvm/utils/lit/lit TestingConfig.py main.py

Revert "[lit] Move maxIndividualTestTime from global to test suite config" (#199886)

Reverts llvm/llvm-project#198192

To fix  https://lab.llvm.org/buildbot/#/builders/195/builds/25357
DeltaFile
+0-16llvm/utils/lit/lit/TestingConfig.py
+12-1llvm/utils/lit/lit/main.py
+4-4llvm/utils/lit/lit/TestRunner.py
+1-4llvm/utils/lit/lit/LitConfig.py
+2-2llvm/utils/lit/lit/formats/googletest.py
+1-1libsycl/test/lit.cfg.py
+20-285 files not shown
+25-3311 files

LLVM/project 2c6fcedclang/lib/CodeGen CGBuiltin.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-image.hip

Merge branch 'main' into users/chenshanzhi/AArch64-TTI-getTgtMemIntrinsic
DeltaFile
+1,521-0clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+993-0clang/test/CodeGen/builtin-clear-padding-codegen.c
+886-0libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
+466-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-image.hip
+416-0mlir/test/Conversion/TosaToSPIRVTosa/tosa-to-spirv.mlir
+344-0clang/lib/CodeGen/CGBuiltin.cpp
+4,626-090 files not shown
+6,266-98596 files

LLVM/project 0d6aac7libcxx/include/__concepts referenceable.h, libcxx/include/__type_traits is_referenceable.h add_pointer.h

[libc++] Remove workarounds for __{add,remove}_pointer on AppleClang (#199821)

We've updated the supported AppleClang version, so we can drop those
workarounds now.

This also removes `__is_referenceable_v`, since it's no longer used.
DeltaFile
+0-190libcxx/test/libcxx/utilities/meta/is_referenceable.compile.pass.cpp
+0-34libcxx/include/__type_traits/is_referenceable.h
+3-28libcxx/include/__type_traits/add_pointer.h
+30-0libcxx/include/__concepts/referenceable.h
+3-16libcxx/include/__type_traits/remove_pointer.h
+0-12libcxx/test/std/utilities/meta/meta.trans/objc_support.compile.pass.mm
+36-28010 files not shown
+45-29616 files

LLVM/project 3060f65llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vector-interleave-fixed.ll fixed-vectors-shuffle-int-interleave.ll

Revert "[RISCV][CodeGen] Use vzip.vv for e64 interleave shuffles with Zvzip" (#199899)

Reverts llvm/llvm-project#199512

LLVM Buildbot has detected a build error for this PR.
DeltaFile
+20-6llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+17-8llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+4-9llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+41-233 files

LLVM/project 4def779libcxx/test/libcxx-03/vendor/apple disable-availability.sh.cpp, libcxx/test/selftest/modules std-and-std.compat-module.sh.cpp

[libc++][NFC] Remove lit annotations for older AppleClang versions (#199817)

We don't support anything older than apple-clang-21, so we can remove
those annotations.
DeltaFile
+0-4libcxx/test/libcxx-03/vendor/apple/disable-availability.sh.cpp
+0-3libcxx/test/std/modules/std.compat.pass.cpp
+0-3libcxx/test/std/modules/std.pass.cpp
+0-3libcxx/test/std/numerics/c.math/signbit.pass.cpp
+0-3libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/is_implicit_lifetime.verify.cpp
+0-3libcxx/test/selftest/modules/std-and-std.compat-module.sh.cpp
+0-196 files not shown
+3-3112 files

LLVM/project d1324cfclang/lib/CodeGen CGBuiltin.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-image.hip

Merge branch 'main' into users/ssahasra/refactor-acq-rel
DeltaFile
+1,521-0clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+993-0clang/test/CodeGen/builtin-clear-padding-codegen.c
+886-0libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
+466-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-image.hip
+416-0mlir/test/Conversion/TosaToSPIRVTosa/tosa-to-spirv.mlir
+344-0clang/lib/CodeGen/CGBuiltin.cpp
+4,626-055 files not shown
+6,162-68861 files

LLVM/project c63a424llvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

Merge branch 'main' into users/statham-arm/arm-fp-f2d2f
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+16,047-2,4481,268 files not shown
+54,473-19,0211,274 files

LLVM/project 3496778llvm/lib/Target/AMDGPU SIMemoryLegalizer.cpp, llvm/test/CodeGen/AMDGPU memory-legalizer-av-unknown.ll

diagnose unknown metadata
DeltaFile
+21-3llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+11-0llvm/test/CodeGen/AMDGPU/memory-legalizer-av-unknown.ll
+32-32 files

LLVM/project 09b607allvm/test/Transforms/LoopVectorize/AArch64 partial-reduce-usabs.ll

Add comment
DeltaFile
+3-0llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-usabs.ll
+3-01 files

LLVM/project 99e6632clang/lib/CIR/CodeGen CIRGenBuiltinAArch64.cpp, clang/test/CodeGen/AArch64 neon-intrinsics.c poly64.c

[CIR][AArch64] Upstream vector-shift-right-and-insert NEON builtins (#196776)

Related to https://github.com/llvm/llvm-project/issues/185382

CIR lowering for vector-shift-right-and-insert intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-insert)

Port tests from clang/test/CodeGen/AArch64/neon_intrinsics.c and
clang/test/CodeGen/AArch64/poly64.c to
clang/test/CodeGen/AArch64/neon/intrinsics.c
DeltaFile
+315-0clang/test/CodeGen/AArch64/neon/intrinsics.c
+0-282clang/test/CodeGen/AArch64/neon-intrinsics.c
+83-9clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+0-28clang/test/CodeGen/AArch64/poly64.c
+398-3194 files

LLVM/project b186960llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vector-interleave-fixed.ll fixed-vectors-shuffle-int-interleave.ll

Revert "[RISCV][CodeGen] Use vzip.vv for e64 interleave shuffles with Zvzip (…"

This reverts commit a4b1361f33139e7a0a02edee1a1b012740951e01.
DeltaFile
+20-6llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+17-8llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+4-9llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+41-233 files

LLVM/project c94e5f3llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeHelper.cpp

AMDGPU/GlobalISel: Move executeInWaterfallLoop call from lower (#199701)

WFI is an argument to applyMappingSrc and lower,
move executeInWaterfallLoop after these two return.
Also set insert point in executeInWaterfallLoop to
avoid need to set insert point before calling it.
DeltaFile
+6-5llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+6-51 files

LLVM/project 698d44bclang/lib/CodeGen CGBuiltin.cpp, clang/lib/Sema SemaChecking.cpp

[clang] Add builtin to clear padding bytes (prework for P0528R3) (#75371)

Add builtin to clear padding bytes. This is the pre-work to implement
`std::atomic::compare_exchange_[weak/strong]` that ignores padding bits.
PR draft here: https://github.com/llvm/llvm-project/pull/76180

This PR picked up this patch from 3 years ago
https://reviews.llvm.org/D87974

The above patch no longer works as things changed quite a lot. I've made
some changes on top of the above patch:


it handles:
- struct
- builtin types with paddings (like `long double` and types with
`__attribute__((ext_vector_type(N)))`
- _Complex long double
- constant array

    [7 lines not shown]
DeltaFile
+1,521-0clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
+993-0clang/test/CodeGen/builtin-clear-padding-codegen.c
+886-0libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
+344-0clang/lib/CodeGen/CGBuiltin.cpp
+98-0clang/test/SemaCXX/builtin-clear-padding.cpp
+64-0clang/lib/Sema/SemaChecking.cpp
+3,906-03 files not shown
+3,968-09 files

LLVM/project 19d2965llvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

update perf_test

Created using spr 1.3.8-beta.1
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+16,047-2,4481,723 files not shown
+68,398-29,5951,729 files

LLVM/project 72795dbllvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+16,047-2,4481,722 files not shown
+68,396-29,5941,728 files

LLVM/project d63f996bolt/test merge-fdata-no-lbr-event-multi.test merge-fdata-no-lbr-event.test, bolt/tools/merge-fdata merge-fdata.cpp

[BOLT][merge-fdata] Preserve event names



Test Plan: added merge-fdata-no-lbr-event*.test

Reviewers:
maksfb, paschalis-mpeis, yozhu, yota9, yavtuk, rafaelauler, ayermolo

Reviewed By: rafaelauler

Pull Request: https://github.com/llvm/llvm-project/pull/199323
DeltaFile
+21-2bolt/tools/merge-fdata/merge-fdata.cpp
+22-0bolt/test/merge-fdata-no-lbr-event-multi.test
+18-0bolt/test/merge-fdata-no-lbr-event.test
+61-23 files

LLVM/project 7a93152clang/include/clang/Basic riscv_vector.td, clang/lib/CodeGen/TargetBuiltins RISCV.cpp

Merge commit '853d532794be83adc97d51c9ff8c9095ce32631b' into users/chenshanzhi/AArch64-TTI-getTgtMemIntrinsic
DeltaFile
+178-267llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+71-67llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+49-43clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+32-27clang/include/clang/Basic/riscv_vector.td
+21-18clang/utils/TableGen/RISCVVEmitter.cpp
+10-12clang/lib/Support/RISCVVIntrinsicUtils.cpp
+361-4343 files not shown
+371-4389 files

LLVM/project 3e0c818clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp CIRGenTypes.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn-image.hip

[CIR][AMDGPU] Adds lowering for amdgcn image load/store builtins (#198184)

Support for lowering of amdgcn_image_load/store for AMDGPU builtins to
clangIR.
Followed similar lowering from clang->llvmir:
`clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp`.

Upstreaming clangIR PR: https://github.com/llvm/clangir/pull/2058
DeltaFile
+466-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-image.hip
+73-12clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+17-0clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+556-123 files

LLVM/project 4c9296dbolt/tools/driver llvm-bolt.cpp

[BOLT][NFC] Unify perf data setting

Combine opts::PerfData handling into one place per driver (llvm-bolt and
heatmap).
* Allow using perf data directly after DataAggregator/DataReader
  unification in #195986.
* Drop redundant perf data checks in perf2boltMode done by setProfile.

Test Plan: NFC

Reviewers:
ritter-x2a, david-salinas, grypp, Pierre-vh, dcaballe, aartbik, adam-smnk, fabianmcg, yota9, JDevlieghere, banach-space, xlauko, nikic, #reviewers-libcxx, rafaelauler, Moxinilian, nicolasvasilache, yozhu, ayermolo, paschalis-mpeis, lamb-j, andykaylor, #reviewers-libc, vangthao95, bcardosolopes, yavtuk, aaronmondal, rupprecht, matthias-springer, keith, maksfb, lanza, Jianhui-Li, charithaintc

Reviewed By: yozhu, rafaelauler

Pull Request: https://github.com/llvm/llvm-project/pull/199322
DeltaFile
+3-22bolt/tools/driver/llvm-bolt.cpp
+3-221 files

LLVM/project c797b79clang/test/CodeGen builtin-masked.c, clang/test/Sema warn-lifetime-safety.cpp

Merge branch 'main' into users/chenshanzhi/AArch64-TTI-getTgtMemIntrinsic
DeltaFile
+178-267llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+416-0mlir/test/Conversion/TosaToSPIRVTosa/tosa-to-spirv.mlir
+109-109clang/test/Sema/warn-lifetime-safety.cpp
+195-0clang/test/CodeGen/builtin-masked.c
+71-67llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+127-0mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaOps.cpp
+1,096-44355 files not shown
+1,620-77761 files

LLVM/project b926cf7mlir/include/mlir/Conversion/TosaToSPIRVTosa TosaToSPIRVTosa.h, mlir/lib/Conversion/TosaToSPIRVTosa TosaToSPIRVTosaOps.cpp CMakeLists.txt

[mlir][tosa][spirv] Lower TOSA elementwise ops to SPIR-V TOSA (#199505)

Add conversion patterns for simple TOSA elementwise operations to the
SPIR-V TOSA dialect.

The lowering covers unary and binary elementwise ops with shared pattern
templates, plus min/max handling for NaN propagation mode.

Add focused conversion tests that check the generated SPIR-V TOSA ops.

Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
DeltaFile
+416-0mlir/test/Conversion/TosaToSPIRVTosa/tosa-to-spirv.mlir
+127-0mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaOps.cpp
+2-0mlir/include/mlir/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosa.h
+1-0mlir/lib/Conversion/TosaToSPIRVTosa/CMakeLists.txt
+1-0mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaPass.cpp
+547-05 files

LLVM/project 9923871bolt/include/bolt/Profile DataAggregator.h, bolt/lib/Profile DataAggregator.cpp

[BOLT][NFC] Split out DataAggregator::parseInput



Test Plan: NFC

Reviewers:
paschalis-mpeis, maksfb, ayermolo, yavtuk, yozhu, rafaelauler, yota9

Reviewed By: yozhu, rafaelauler

Pull Request: https://github.com/llvm/llvm-project/pull/199321
DeltaFile
+12-7bolt/lib/Profile/DataAggregator.cpp
+4-1bolt/include/bolt/Profile/DataAggregator.h
+16-82 files

LLVM/project 66bafd4mlir/lib/Support TypeID.cpp

[MLIR] Improve TypeID anonymous namespace check to handle GCC's __PRETTY_FUNCTION__ format (#199634)

The anonymous namespace detection in
`FallbackTypeIDResolver::registerImplicitTypeID` only checked for
Clang's `(anonymous namespace)` and MSVC's `anonymous-namespace`
formats. GCC produces `{anonymous}` in `__PRETTY_FUNCTION__`, silently
bypassing the check.
DeltaFile
+7-5mlir/lib/Support/TypeID.cpp
+7-51 files

LLVM/project ed944cdllvm/test/CodeGen/AMDGPU accvgpr-spill-scc-clobber.mir pei-build-av-spill.mir, mlir/lib/Dialect/XeGPU/Transforms XeGPUSubgroupDistribute.cpp

Merge remote-tracking branch 'upstream/users/ssahasra/refactor-acq-rel' into users/ssahasra/av-metadata
DeltaFile
+5,568-0llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+3,000-96llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+3,075-0llvm/test/CodeGen/AMDGPU/debug-frame.ll
+0-2,280mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
+2,208-72llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+2,196-0llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+16,047-2,4481,538 files not shown
+59,243-23,2091,544 files

LLVM/project f5bda2bclang/test/Sema warn-lifetime-safety.cpp

[LifetimeSafety] Change new tests' warnings to new ones  (#199887)

cc: @usx95
DeltaFile
+3-3clang/test/Sema/warn-lifetime-safety.cpp
+3-31 files

LLVM/project a4b1361llvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV/rvv vector-interleave-fixed.ll fixed-vectors-shuffle-int-interleave.ll

[RISCV][CodeGen] Use vzip.vv for e64 interleave shuffles with Zvzip (#199512)

Allow e64 interleave shuffles to use the standard Zvzip `vzip.vv`
lowering when the operand type is legal for Zvzip, just the same as what
XrivosVizip already does.
DeltaFile
+6-20llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+8-17llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+9-4llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+23-413 files

LLVM/project 6de9a33llvm/docs/CommandGuide llvm-debuginfo-analyzer.rst, llvm/include/llvm/DebugInfo/LogicalView/Readers LVIRReader.h

Revert "[llvm-debuginfo-analyzer] Add support for LLVM IR format. (#135440)" (#199890)

This reverts commit 6bbbf743ae49736ba438e9dbd14a5bd0f4166382.

There are link issues with some buildbots.
DeltaFile
+0-2,630llvm/lib/DebugInfo/LogicalView/Readers/LVIRReader.cpp
+0-362llvm/unittests/DebugInfo/LogicalView/IRReaderTest.cpp
+0-302llvm/include/llvm/DebugInfo/LogicalView/Readers/LVIRReader.h
+134-87llvm/docs/CommandGuide/llvm-debuginfo-analyzer.rst
+0-168llvm/test/tools/llvm-debuginfo-analyzer/IR/08-ir-multiple-compile-units.test
+0-151llvm/test/tools/llvm-debuginfo-analyzer/IR/01-ir-select-logical-elements.test
+134-3,70035 files not shown
+152-5,40641 files