LLVM/project 73c7c56llvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/AArch64 sve-ldst-sext.ll sve-ldst-zext.ll

[LLVM][DAGCombiner] Look through freeze when combining extensions of loads (#175022)

Following on from https://github.com/llvm/llvm-project/pull/172484 I
have added support to tryToFoldExtOfLoad for looking through freezes, in
order to catch more cases of extending loads. This type of code is
sometimes seen being generated by the loop vectoriser. For now I've
limited this to cases where the load is only used by the freeze, since
otherwise it leads to worse code in some X86 tests.
DeltaFile
+435-0llvm/test/CodeGen/AArch64/sve-ldst-sext.ll
+426-0llvm/test/CodeGen/AArch64/sve-ldst-zext.ll
+36-19llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+31-0llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
+4-8llvm/test/CodeGen/X86/avx512-ext.ll
+6-6llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
+938-339 files not shown
+966-4715 files

LLVM/project 3fb8601lldb/source/Interpreter Options.cpp

[lldb] Refactor command option printing (#178208)

So I have an easier time fixing #177570.

Changes I have made:
* Init a variable inside if statement to reduce scope.
* Added const to some variables.
* Early return if we print a single line, and dedent the "else" that
handles multiple lines.
* Only convert lldb's short codes into ansi codes once.
* Rename a couple of variables where they could have either referred to
the visible text or the raw data with the ansi codes in.
DeltaFile
+44-41lldb/source/Interpreter/Options.cpp
+44-411 files

LLVM/project aeee859llvm/lib/Target/AArch64 AArch64SystemOperands.td AArch64Features.td, llvm/lib/Target/AArch64/AsmParser AArch64AsmParser.cpp

[AArch64][llvm] Gate some `tlbip` insns with +tlbid or +d128

Change the gating of `tlbip` instructions containing `*E1IS*`, `*E1OS*`,
`*E2IS*` or `*E2OS*` to be used with `+tlbid` or `+d128`. This is because
the 2025 Armv9.7-A MemSys specification says:

```
All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions
that are currently dependent on FEAT_D128 are updated to be dependent
on FEAT_D128 or FEAT_TLBID
```
DeltaFile
+259-0llvm/test/MC/AArch64/tlbip-tlbid-or-d128.s
+110-110llvm/test/MC/AArch64/armv9a-sysp.s
+18-4llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+21-0llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+13-2llvm/lib/Target/AArch64/AArch64SystemOperands.td
+7-4llvm/lib/Target/AArch64/AArch64Features.td
+428-1204 files not shown
+449-12610 files

LLVM/project 4ebede7lldb/source/Host/windows MainLoopWindows.cpp, lldb/test/Shell/DAP TestSTDINConsole.test

Revert "[lldb-dap][windows] allow STDIN to be a console (#178409)" (#178641)

DeltaFile
+0-62lldb/test/Shell/DAP/TestSTDINConsole.test
+1-1lldb/source/Host/windows/MainLoopWindows.cpp
+1-632 files

LLVM/project 7f661d2llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/mcdc/nest/nest' into users/chapuni/mcdc/nest/trunk
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6065,137 files not shown
+778,450-525,5865,143 files

LLVM/project ad26fa5llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/mcdc/nest/covmapdesc' into users/chapuni/mcdc/nest/nest

Conflicts:
        clang/docs/ReleaseNotes.rst
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6065,137 files not shown
+778,450-525,5865,143 files

LLVM/project da7eac4llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/single/binop' into users/chapuni/mcdc/nest/covmapdesc
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,007-484,5894,121 files

LLVM/project 00df2aellvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/merge/merge-mcdc' into users/chapuni/cov/merge/trunk
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,005-484,5874,121 files

LLVM/project f08a00dllvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/merge/strategy' into users/chapuni/cov/merge/merge-mcdc
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,005-484,5874,121 files

LLVM/project f0a9223llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/merge/forfile' into users/chapuni/cov/merge/strategy

Conflicts:
        llvm/test/tools/llvm-cov/Inputs/branch-templates.cpp
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,005-484,5874,121 files

LLVM/project a3aabe4llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/merge/region_segment' into users/chapuni/cov/merge/forfile
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,007-484,5894,121 files

LLVM/project c9faee1llvm/test/CodeGen/AMDGPU amdgcn.bitcast.1024bit.ll amdgcn.bitcast.512bit.ll, polly/lib/External/isl/include/isl typed_cpp.h cpp.h

Merge branch 'users/chapuni/cov/single/binop' into users/chapuni/cov/merge/region_segment

Conflicts:
        llvm/test/tools/llvm-cov/branch-macros.test
DeltaFile
+121,418-138,354llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+43,323-44,825llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+52,760-0polly/lib/External/isl/include/isl/typed_cpp.h
+12,842-18,547llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+30,864-0polly/lib/External/isl/include/isl/cpp.h
+14,350-15,880llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+275,557-217,6064,115 files not shown
+702,007-484,5894,121 files

LLVM/project 94aea76llvm/lib/Target/LoongArch LoongArchInstrInfo.cpp, llvm/test/CodeGen/LoongArch disable-reloc-sched.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+48-0llvm/test/CodeGen/LoongArch/disable-reloc-sched.ll
+12-0llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+60-02 files

LLVM/project 1dd9e20lldb/packages/Python/lldbsuite/test decorators.py configuration.py, lldb/test/API/functionalities/ubsan/basic TestUbsanBasic.py

[lldb] Fix UbSan decorator (#177964)

the ubsan decorator previously assumes the platform is macOS.

macOS has an extra underscore in symbols names match two or more.
uses the llvm-nm that is built instead of the system's nm.
DeltaFile
+9-27lldb/packages/Python/lldbsuite/test/decorators.py
+12-0lldb/packages/Python/lldbsuite/test/configuration.py
+2-2lldb/test/API/functionalities/ubsan/basic/TestUbsanBasic.py
+3-0lldb/packages/Python/lldbsuite/test/dotest.py
+26-294 files

LLVM/project 3f2f920flang/test/Integration/OpenMP target-nesting-in-host-ops.f90 target-use-device-nested.f90, mlir/lib/Target/LLVMIR/Dialect/OpenMP OpenMPToLLVMIRTranslation.cpp

[MLIR][OpenMP] Simplify OpenMP device codegen

After removing host operations from the device MLIR module, it is no longer
necessary to provide special codegen logic to prevent these operations from
causing compiler crashes or miscompilations.

This patch removes these now unnecessary code paths to simplify codegen logic.
Some MLIR tests are now replaced with Flang tests, since the responsibility of
dealing with host operations has been moved earlier in the compilation flow.

MLIR tests holding target device modules are updated to no longer include now
unsupported host operations.
DeltaFile
+166-302mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+0-160mlir/test/Target/LLVMIR/openmp-target-nesting-in-host-ops.mlir
+87-0flang/test/Integration/OpenMP/target-nesting-in-host-ops.f90
+24-37mlir/test/Target/LLVMIR/omptarget-memcpy-align-metadata.mlir
+0-46mlir/test/Target/LLVMIR/openmp-target-use-device-nested.mlir
+46-0flang/test/Integration/OpenMP/target-use-device-nested.f90
+323-54512 files not shown
+484-73618 files

LLVM/project 7682d2aflang/lib/Optimizer/OpenMP FunctionFiltering.cpp

rebase fix
DeltaFile
+1-1flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
+1-11 files

LLVM/project f1235bdlldb/source/Host/windows MainLoopWindows.cpp, lldb/test/Shell/DAP TestSTDINConsole.test

[lldb-dap][windows] allow STDIN to be a console (#178409)

Co-authored-by: Ebuka Ezike <yerimyah1 at gmail.com>
DeltaFile
+62-0lldb/test/Shell/DAP/TestSTDINConsole.test
+1-1lldb/source/Host/windows/MainLoopWindows.cpp
+63-12 files

LLVM/project f9b0efellvm/lib/Target/AMDGPU SIInstructions.td

[AMDGPU] Remove obsolete comment again

Obsoleted by e4464bf3d458 "AMDGPU/GlobalISel: Select scalar v2s16 G_BUILD_VECTOR".
Removed by cb64455faa36 "[AMDGPU] Remove obsolete comment".
Accidentally reintroduced by a8d9d50762c4 "[AMDGPU] gfx90a support".
DeltaFile
+0-2llvm/lib/Target/AMDGPU/SIInstructions.td
+0-21 files

LLVM/project 11715e6flang/lib/Optimizer/OpenMP FunctionFiltering.cpp, flang/test/Lower/OpenMP host-eval.f90 declare-target-link-tarop-cap.f90

[Flang][OpenMP] Minimize host ops remaining in device compilation

This patch updates the function filtering OpenMP pass intended to remove host
functions from the MLIR module created by Flang lowering when targeting an
OpenMP target device.

Host functions holding target regions must be kept, so that the target regions
within them can be translated for the device. The issue is that non-target
operations inside these functions cannot be discarded because some of them hold
information that is also relevant during target device codegen. Specifically,
mapping information resides outside of `omp.target` regions.

This patch updates the previous behavior where all host operations were
preserved to then ignore all of those that are not actually needed by target
device codegen. This, in practice, means only keeping target regions and mapping
information needed by the device. Arguments for some of these remaining
operations are replaced by placeholder allocations and `fir.undefined`, since
they are only actually defined inside of the target regions themselves.


    [3 lines not shown]
DeltaFile
+516-0flang/test/Transforms/OpenMP/function-filtering-host-ops.mlir
+350-2flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
+137-0flang/test/Transforms/OpenMP/function-filtering.mlir
+0-137flang/test/Transforms/omp-function-filtering.mlir
+37-18flang/test/Lower/OpenMP/host-eval.f90
+10-9flang/test/Lower/OpenMP/declare-target-link-tarop-cap.f90
+1,050-1662 files not shown
+1,053-1718 files

LLVM/project 8756292mlir/include/mlir/IR BuiltinTypeInterfaces.td, mlir/lib/IR BuiltinTypeInterfaces.cpp BuiltinTypes.cpp

[mlir] Fix integer overflow in ShapedType::getNumElements and `makeCanonicalStridedLayoutExpr` (#178395)

Add to `ShapedTypeInterface` a new `tryGetNumElements()` API which
returns `std::optional<int64_t>` - returns `std::nullopt` on overflow
instead of UB, using `llvm::checkedMul` for proper overflow detection.
`getNumElements()` now uses this new API to assert on overflow.

Also fix `AffineExpr` canonicalization to avoid crashing on overflow
using `llvm::checkedMul`.

Fixes #178362
Fixes #177816

---------

Co-authored-by: Claude Opus 4.5 <noreply at anthropic.com>
DeltaFile
+23-0mlir/unittests/IR/ShapedTypeTest.cpp
+19-3mlir/lib/IR/BuiltinTypeInterfaces.cpp
+21-0mlir/test/Dialect/MemRef/high-rank-overflow.mlir
+11-0mlir/include/mlir/IR/BuiltinTypeInterfaces.td
+8-2mlir/lib/IR/BuiltinTypes.cpp
+82-55 files

LLVM/project 224a6fflibcxx/include __bit_reference, libcxx/include/__algorithm swap_ranges.h specialized_algorithms.h

[libc++] Refactor swap_ranges to use __specialized_algorithm for the vector<bool>::iterator specialization (#173384)

DeltaFile
+24-151libcxx/include/__algorithm/swap_ranges.h
+151-10libcxx/include/__bit_reference
+83-0libcxx/test/libcxx/algorithms/specialized_algorithms.compile.pass.cpp
+1-0libcxx/include/__algorithm/specialized_algorithms.h
+259-1614 files

LLVM/project a0e0f51clang/lib/Driver/ToolChains/Arch AArch64.cpp, clang/test/Driver aarch64-mcpu-native.c

[AArch64][Driver] Enable host supported features with march=native. (#177128)

Currently, march=native enables the base features implied by the host
system architecture, such as Armv8.2-A, Armv9-A, etc, rather than the
actual features supported by the host (e.g. crypto). This is suboptimal
as it generally leaves optional but supported features disabled.

This patch aligns the behaviour of march=native with mcpu=native by
using the latter's decoding logic to decode the former as well. This
means both options should enable a similar set of features. We also set
the target-cpu accordingly, so that march=native becomes a drop-in
replacement for mcpu=native.
DeltaFile
+19-0clang/test/Driver/aarch64-mcpu-native.c
+8-2clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+5-0clang/test/Driver/print-enabled-extensions/aarch64-grace.c
+32-23 files

LLVM/project 12dd342lldb/test/API/commands/help TestHelp.py

[lldb][test] Add tests for formatting of command option descriptions (#178235)

These test the existing behaviour before I work on #177570.
    
I chose "breakpoint set" because it has options with ANSI underlines
in the description.
    
The tests cover no ANSI (use-colour off) and with ANSI (use-color on).
The latter is where we have problems right now.
DeltaFile
+56-0lldb/test/API/commands/help/TestHelp.py
+56-01 files

LLVM/project a5ffce0lldb/include/lldb/Host MemoryMonitor.h, lldb/source/Host/common MemoryMonitor.cpp

[lldb] Fix memory monitor shutdown on Linux using eventfd (#178083)

The current linux implementation has a 1 second timeout when polling for
memory pressure. lldb-dap may take up to an extra 1 second to shutdown.
Use an event file descriptor to immediately stop the memory monitor
thread.

Fixes #150220
DeltaFile
+102-31lldb/source/Host/common/MemoryMonitor.cpp
+2-1lldb/include/lldb/Host/MemoryMonitor.h
+104-322 files

LLVM/project 822756cllvm/lib/Target/RISCV RISCVInstrInfoZb.td, llvm/test/CodeGen/RISCV rv32zbs.ll rv64zbs.ll

[RISCV] Add ISEL pattern to convert add (shl -1, X), Y to sub Y, (bset zero, X) (#178601)

Fixes #178588
DeltaFile
+30-12llvm/test/CodeGen/RISCV/rv32zbs.ll
+22-4llvm/test/CodeGen/RISCV/rv64zbs.ll
+2-0llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+54-163 files

LLVM/project 655c31dllvm/lib/Target/AMDGPU VOP3PInstructions.td, llvm/lib/Target/AMDGPU/MCTargetDesc AMDGPUMCCodeEmitter.cpp

[AMDGPU] Change scale_src2 encoding from vgpr0 to literal 0 (#178404)

This changes the fix from #167777 to use the encoding for literal 0
instead of the encoding for vgpr0, to match new SP3 behaviour and for
consistency with all other unused VALU source operands since #175753.
DeltaFile
+122-122llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
+106-106llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
+0-13llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+3-3llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+231-2444 files

LLVM/project ba0cddblibcxx/include __config, libcxx/include/__cxx03 __config

[libc++][NFC] Remove _LIBCPP_FREESTANDING (#176907)

`_LIBCPP_FREESTANDING` isn't used and it is unclear what libc++'s
strategy is going to be for implementing freestanding at the moment.
Therefore, remove the macro.
DeltaFile
+0-20libcxx/test/libcxx/libcpp_freestanding.sh.cpp
+0-20libcxx/test/libcxx-03/libcpp_freestanding.sh.cpp
+0-4libcxx/include/__config
+0-4libcxx/include/__cxx03/__config
+0-484 files

LLVM/project 12c13e0llvm/lib/Target/AMDGPU AMDGPURegisterBankInfo.cpp SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.s.buffer.load.ll

[AMDGPU][GFX1250] Implement offset handling in s.buffer.load (#178389)

Divergent path of s.buffer.load must handle 32b offset extension
behaviour on GFX1250.
Tests in llvm.amdgcn.s.buffer.load.ll are rewritten to avoid using
export instructions not available on GFX1250.
DeltaFile
+2,801-1,573llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
+2,635-1,150llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
+452-517llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
+6-2llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+5-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5,899-3,2435 files

LLVM/project 0dd61b2llvm/lib/Target/WebAssembly WebAssemblyISelLowering.cpp, llvm/test/CodeGen/WebAssembly simd-shuffle-widen.ll

[WebAssembly] Fix crash in ReplaceNodeResults for ANY_EXTEND_VECTOR_INREG (#178374)

Fixes a crash during type legalization by allowing
ISD::ANY_EXTEND_VECTOR_INREG to fall back to default expansion instead
of hitting llvm_unreachable.

Fixed: #177209
(cherry picked from commit 16d8d4b84edd257a81b243767d7b6bd62bbfb9fa)
DeltaFile
+50-0llvm/test/CodeGen/WebAssembly/simd-shuffle-widen.ll
+1-0llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+51-02 files

LLVM/project 399f25fclang/include/clang/Analysis/Analyses/LifetimeSafety FactsGenerator.h, clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp

[LifetimeSafety] Handle temporaries of non-trivial view types (#177878)

Fixes https://github.com/llvm/llvm-project/issues/177802

This enables the analysis to correctly track lifetimes through
non-trivial view types that require temporary binding due to having a
destructor.

This is fixed by handling `MaterializeTemporaryExpr` even for
lifetime-extended temporaries and fixing the flow of origins.
DeltaFile
+22-0clang/test/Sema/warn-lifetime-safety.cpp
+10-7clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+1-0clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
+33-73 files