LLVM/project a84ff9cflang/test/Integration/PowerPC ppc-vec-convert.f90 ppc-vec-shift-be-le.f90, flang/test/Lower/PowerPC ppc-vec-convert.f90 ppc-vec-shift-be-le.f90

[Flang] Move integration Lit tests to the right directory, NFC

Flang unit tests that involve multiple stages of the compiler are
intended to be placed in flang/test/Integration. However, many existing
unit tests meeting this condition are currently located in the Lower
subdirectory.

This patch moves all tests in Lower that emit LLVM IR from Fortran or
run the FIR MLIR lowering pipeline via `tco` to Integration, and adds the
corresponding notice at the top of each file.

Assisted-by: Claude Opus 4.8.
DeltaFile
+1,709-0flang/test/Integration/PowerPC/ppc-mma-outer-product-1.f90
+0-1,701flang/test/Lower/PowerPC/ppc-mma-outer-product-1.f90
+1,420-0flang/test/Integration/PowerPC/ppc-vec-shift-be-le.f90
+0-1,412flang/test/Lower/PowerPC/ppc-vec-shift-be-le.f90
+1,349-0flang/test/Integration/PowerPC/ppc-vec-convert.f90
+0-1,342flang/test/Lower/PowerPC/ppc-vec-convert.f90
+4,478-4,455141 files not shown
+17,775-17,197147 files

LLVM/project f6f87b9orc-rt/include/orc-rt Session.h, orc-rt/lib/executor InProcessControllerAccess.cpp Session.cpp

[orc-rt] Report the disconnection mode to Session clients (#217236)

ControllerAccess::notifyDisconnected now takes an Error describing how
the controller connection ended: success if the disconnection was
orderly, otherwise an Error describing what went wrong. A
ControllerAccess passes its terminal error here rather than to
reportError; with no on-disconnect handler installed the Session
forwards it to the error reporter.

Session::setOnDisconnect installs that handler. It is called exactly
once as the Session detaches, including on a Session that never attached
a controller (reporting success), so a client can use it both to record
the Session's result and to decide whether to shut down.
DeltaFile
+262-8orc-rt/test/unit/SessionTest.cpp
+90-3orc-rt/include/orc-rt/Session.h
+37-5orc-rt/lib/executor/Session.cpp
+1-1orc-rt/lib/executor/InProcessControllerAccess.cpp
+390-174 files

LLVM/project dd53a94clang/lib/AST/ByteCode DynamicAllocator.cpp Compiler.cpp

[clang][bytecode] Move `Descriptor` metadata to `Block` (#217280)

The metadata in `Descriptor`s was only ever used for "toplevel"
descriptors, i.e. never for fields or array elements. Those are also the
descriptors we allocate into `Block`s though, so move the metadata there
and save some space in `Descriptor`.
DeltaFile
+52-56clang/lib/AST/ByteCode/Program.cpp
+37-37clang/lib/AST/ByteCode/InterpBlock.h
+32-41clang/lib/AST/ByteCode/Descriptor.cpp
+14-26clang/lib/AST/ByteCode/Descriptor.h
+10-17clang/lib/AST/ByteCode/Compiler.cpp
+6-10clang/lib/AST/ByteCode/DynamicAllocator.cpp
+151-18713 files not shown
+183-22419 files

LLVM/project 54702ffllvm/lib/Target/X86 X86ISelDAGToDAG.cpp, llvm/test/CodeGen/X86 urem-vector-lkk.ll lea-opt.ll

[X86] Fold `B + (-C)*A` into `neg + lea` (#215145)

Closes: #37287
DeltaFile
+266-0llvm/test/CodeGen/X86/neg-shl-lea.ll
+57-16llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+49-0llvm/test/CodeGen/X86/neg-shl-lea-32.ll
+22-18llvm/test/CodeGen/X86/lea-opt.ll
+6-6llvm/test/CodeGen/X86/urem-vector-lkk.ll
+2-4llvm/test/CodeGen/X86/apx/ndd-neg-addr-index.ll
+402-442 files not shown
+408-498 files

LLVM/project d97bf43flang/test/Fir omp-declare-target-data.fir, flang/test/Lower/OpenMP declare-target-func-and-subr.f90

[MLIR][OpenMP] DeclareTargetInterface and DeclareTargetAttr cleanup, NFCI

The changes introduced by this patch are intended to avoid triggering
multiple by name lookups to the "omp.declare_target" attribute every
time any data from the `DeclareTargetInterface` is queried, remove the
need for keeping multiple default values for the same data, clean up
the assembly format and generally improve the usage of the interface.

List of changes:
- `DeclareTargetInterface` only provides `setDeclareTarget` and
  `getDeclareTarget` methods to handle the "omp.declare_target"
  attribute, maintaining a single canonical way of accessing it.
- `DeclareTargetAttr` provides direct access to the capture clause and
  device type enums, rather than wrapping them into an `Attribute`.
  These are now mandatory as well. Both changes together make accessing
  them more straightforward and simplify the attribute representation.
DeltaFile
+44-44mlir/test/Dialect/OpenMP/mark-declare-target.mlir
+15-60mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
+30-30mlir/test/Dialect/OpenMP/attr.mlir
+23-23flang/test/Lower/OpenMP/declare-target-func-and-subr.f90
+22-22flang/test/Fir/omp-declare-target-data.fir
+25-19mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+159-19857 files not shown
+411-43263 files

LLVM/project abea6f7mlir/include/mlir/Dialect/OpenMP OpenMPDialect.td, mlir/lib/Dialect/OpenMP/IR OpenMPDialect.cpp

[MLIR][OpenMP] Add verification for DeclareTargetInterface

This patch introduces checks to ensure the "omp.declare_target"
attribute is only attached to `DeclareTargetInterface` operations, it is
always the right type attribute and its properties do not conflict with
the operation they are attached to.
DeltaFile
+42-0mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
+28-0mlir/test/Dialect/OpenMP/invalid-interface.mlir
+0-18mlir/test/Dialect/OpenMP/attr.mlir
+1-0mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.td
+71-184 files

LLVM/project 779cfd5flang/test/Lower/OpenMP declare-target-implicit-func-and-subr-cap-enter.f90 declare-target-data.f90, mlir/lib/Dialect/OpenMP/Transforms MarkDeclareTarget.cpp

[MLIR][OpenMP] Support calls added between MarkDeclareTarget runs (#214185)

Currently, if there are multiple executions of the `MarkDeclareTarget`
pass in a compiler pipeline and somewhere between both runs function
calls get added to a non-declare_target function that was marked as such
implicitly, potential changes to the `device_type` won't get propagated.

This is because we can't distinguish between a user-specified
`declare_target` function attribute and one added by that pass. This
patch addresses this by adding a new parameter to `DeclareTargetAttr`
that is used by that pass to know whether new `declare_target`
information could be propagated to it.

The `automap` and `implicit` parameters are given default values to
simplify the representation of these attributes.
DeltaFile
+62-40mlir/test/Dialect/OpenMP/mark-declare-target.mlir
+25-47mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
+23-23flang/test/Lower/OpenMP/declare-target-func-and-subr.f90
+21-21flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90
+19-19flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90
+19-19flang/test/Lower/OpenMP/declare-target-data.f90
+169-16912 files not shown
+221-20618 files

LLVM/project af19308flang/test/Integration/OpenMP function-filtering-2.f90, flang/test/Lower/OpenMP declare-target-implicit-tarop-cap.f90 declare-target-implicit-func-and-subr-cap-enter.f90

[Flang][OpenMP] Improve implicit declare_target propagation (#214184)

After starting to run the `MarkDeclareTarget` pass later in the
pipeline, some limitations of its original implementation started to be
hit; specifically, some calls being missed could result in an overly
restrictive marking that would cause the `HostOpFiltering` pass to
remove reachable device code.

This patch aims to address these problems by making the following
changes:
- It makes sure to mark functions in every `RecipeInterface` op pointed
to by OpenMP operations.
- It recursively propagates and combines declare_target information from
target regions and explicitly set declare_target functions to unmarked
functions, but it never modifies explicitly marked functions.
- External and public functions can now only be marked with
`device_type(any)`. Before, marking them as `nohost` or `host` was
possible, but without the ability to see all users we can't give such
guarantees.

    [6 lines not shown]
DeltaFile
+267-124mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
+200-187flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90
+363-0mlir/test/Dialect/OpenMP/mark-declare-target.mlir
+174-161flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90
+86-73flang/test/Lower/OpenMP/declare-target-implicit-tarop-cap.f90
+46-44flang/test/Integration/OpenMP/function-filtering-2.f90
+1,136-5897 files not shown
+1,208-60613 files

LLVM/project 79ec8e3flang/include/flang/Optimizer/OpenMP Passes.td, flang/lib/Optimizer/OpenMP DeleteUnreachableTargets.cpp

[Flang][OpenMP] Remove the DeleteUnreachableTargets pass (#214183)

The `DeleteUnreachableTargets` pass was initially added to work around a
problem caused by the interaction between the function filtering and
host op filtering passes and generic MLIR optimizations.

Specifically, by running function and host op filtering before these
optimizations, we would lose the ability to detect unreachable
`omp.target` operations when compiling for the device. This would cause
GPU kernels being created for them, for which no host counterpart
existed.

By now having moved both passes towards the end of the compilation
pipeline, after FIR to LLVM lowering, removal of unreachable host and
device code is no longer impacted by them. This makes the
`DeleteUnreachableTargets` pass redundant.
DeltaFile
+0-322flang/test/Transforms/OpenMP/delete-unreachable-targets.mlir
+271-0flang/test/Integration/OpenMP/target-dead-code.f90
+0-88flang/test/Lower/OpenMP/target-dead-code.f90
+0-76flang/lib/Optimizer/OpenMP/DeleteUnreachableTargets.cpp
+0-12flang/include/flang/Optimizer/OpenMP/Passes.td
+0-3flang/lib/Optimizer/Passes/Pipelines.cpp
+271-5011 files not shown
+271-5027 files

LLVM/project a5bb77fflang/lib/Optimizer/OpenMP UnimplementedDeviceCheck.cpp FunctionFiltering.cpp, flang/test/Transforms omp-function-filtering-todo.mlir

[Flang][MLIR][OpenMP] Move function filtering to the omp dialect (#214182)

The `FunctionFilteringPass`, which removes host-only functions when
compiling for an OpenMP target device, is currently defined only for
Flang. However, it implements logic that would generally be useful for
other frontends that can generate OpenMP offloading code. This patch
makes that transition by implementing the following changes:
- It rewrites the `FunctionFilteringPass` to work on lower level non-FIR
MLIR modules.
- It splits off preexisting logic to check for not-yet-implemented
target device features during function filtering to its own pass and it
improves context detection to properly diagnostic only device code.
- It delays function filtering to run at the end of the pipeline, as
well as the `MarkDeclareTargetPass`. This will enable the latter to run
only once in the pipeline after the `UnimplementedDeviceCheckPass`
becomes no longer necessary.

One side effect of these changes is that delaying the filtering will
cause all following passes to process host functions that are eventually

    [3 lines not shown]
DeltaFile
+0-155flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
+152-0mlir/test/Dialect/OpenMP/function-filter.mlir
+0-137flang/test/Transforms/OpenMP/function-filtering.mlir
+109-0mlir/lib/Dialect/OpenMP/Transforms/FunctionFiltering.cpp
+98-0flang/lib/Optimizer/OpenMP/UnimplementedDeviceCheck.cpp
+67-5flang/test/Transforms/omp-function-filtering-todo.mlir
+426-29720 files not shown
+800-61026 files

LLVM/project 157af9cllvm/lib/Target/AMDGPU SILowerI1Copies.h SILowerI1Copies.cpp

AMDGPU: Extract mergeIncomingLaneMasks from SILowerI1Copies lowerPhis (#216995)
DeltaFile
+96-87llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+12-0llvm/lib/Target/AMDGPU/SILowerI1Copies.h
+108-872 files

LLVM/project af882d5llvm/test/Transforms/LoopVectorize/AArch64 sve2-histcnt.ll sve-interleaved-accesses.ll, llvm/test/Transforms/LoopVectorize/RISCV tail-folding-bin-unary-ops-args.ll strided-accesses.ll

[LV] Optimise code created by createElementCount (#216981)

At the moment when creating an element count we generate vplan like this

  mul(vscale, EC)

however since we know that the VF should always be a power of 2 we can
just do

  shl(vscale, log2(EC))

instead. This leads to IR simplifications in quite a few tests, where
redundant shifts get folded away.

There are some instances in tests like

AArch64/partial-reduce-dot-product.ll

where a nsw flag is being dropped, however I don't see this as a bad
thing since again I'm not sure how we could previously justify the nsw
flag anyway.
DeltaFile
+63-84llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
+45-60llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
+41-58llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+36-54llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
+40-50llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
+34-45llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+259-351104 files not shown
+1,012-1,408110 files

LLVM/project aa5ffd9llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Strip dead gcd function (NFC) (#217299)
DeltaFile
+0-14llvm/lib/Analysis/ScalarEvolution.cpp
+0-141 files

LLVM/project e8ea457llvm/lib/Target/AMDGPU AMDGPUPassRegistry.def AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel regbankcombiner-smed3.mir regbankcombiner-clamp-fmed3-const.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankCombiner" to NPM
DeltaFile
+66-26llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+13-2llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-2llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+2-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
+2-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir
+86-3210 files not shown
+97-3216 files

LLVM/project 70c1f1bllvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPU.h

comments
DeltaFile
+2-2llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPU.h
+4-43 files

LLVM/project cda4849llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPU.h, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-load.mir regbankselect-freeze.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankLegalize" to NPM
DeltaFile
+48-20llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+21-3llvm/lib/Target/AMDGPU/AMDGPU.h
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+3-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
+3-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
+3-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
+80-25160 files not shown
+256-26166 files

LLVM/project c14c20ellvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPUPassRegistry.def, llvm/test/CodeGen/AMDGPU/GlobalISel regbankselect-mui-regbankselect.mir

[AMDGPU][GIsel][NPM] Port "AMDGPURegBankSelect" to NPM
DeltaFile
+44-18llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
+18-3llvm/lib/Target/AMDGPU/AMDGPU.h
+3-2llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+2-2llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-0llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbankselect.mir
+68-255 files

LLVM/project 7f07ffcllvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp AMDGPUPassRegistry.def, llvm/test/CodeGen/AMDGPU/GlobalISel combine-add-nullptr.mir amdgpu-prelegalizer-combiner-crash.mir

[AMDGPU][GIsel][NPM] Port "AMDGPUPreLegalizerCombiner" to NPM
DeltaFile
+62-21llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+8-1llvm/lib/Target/AMDGPU/AMDGPU.h
+2-1llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+1-1llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+1-0llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
+1-0llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
+75-244 files not shown
+79-2410 files

LLVM/project 56bb311clang/lib/CodeGen/Targets Mips.cpp, clang/test/CodeGen/Mips variadic-aggregate.c

[MIPS] don't pass variadic arguments in float registers (#216519)

At least, I think that's what is going on here. Really it doesn't make
sense to use `inreg` float parameters here. Apparently the backend can
handle it on smaller floats but `_Complex long double` hits some edge
case and miscompiles.

https://godbolt.org/z/nqTM46Ej5

```c
extern void sink(int, ...);

void variadic_cld(_Complex long double z) { sink(0, z); }
```

Clang only sets up register 4 for the `int`, I think with the assumption
that the `f128` arguments are already in the right place:

```asm

    [48 lines not shown]
DeltaFile
+51-45clang/test/CodeGen/Mips/variadic-aggregate.c
+11-8clang/lib/CodeGen/Targets/Mips.cpp
+62-532 files

LLVM/project bec1e53flang/lib/Lower HlfirIntrinsics.cpp, flang/lib/Optimizer/HLFIR/IR HLFIROps.cpp

Revert "[Flang][HLFIR] Lower PACK(array, .TRUE.) to hlfir.reshape" (#217310)

Reverts llvm/llvm-project#213603 due to regressions
DeltaFile
+0-109flang/test/HLFIR/simplify-hlfir-intrinsics-pack.fir
+0-67flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
+8-41flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
+0-48flang/test/Lower/HLFIR/pack_scalar_true.f90
+1-29flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+0-25flang/lib/Lower/HlfirIntrinsics.cpp
+9-3194 files not shown
+35-35810 files

LLVM/project de0cc43llvm/lib/Target/AArch64 MachineSMEABIPass.cpp AArch64ISelLowering.cpp, llvm/test/CodeGen/AArch64 sme-dynamic-tls.ll

[AArch64][SME] Handle SME state around Darwin TLS-descriptor calls (#216017)

Handle Darwin TLS descriptor calls like we handle ELF/Linux calls (see
https://github.com/llvm/llvm-project/pull/155608).

Fixes https://github.com/llvm/llvm-project/issues/215824
DeltaFile
+181-0llvm/test/CodeGen/AArch64/sme-dynamic-tls.ll
+21-0llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+2-0llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+204-03 files

LLVM/project 4cd3535libc/shared/math nearbyintf128.h, libc/src/__support/math nearbyintf128.h

[libc] Modify nearbyintf128 to use emulated Float128 type  (#217025)
DeltaFile
+4-7libc/src/__support/math/nearbyintf128.h
+0-6libc/shared/math/nearbyintf128.h
+5-1libc/src/math/generic/nearbyintf128.cpp
+5-0libc/test/src/math/smoke/nearbyintf128_test.cpp
+5-0libc/src/math/nearbyintf128.h
+3-1utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+22-1519 files not shown
+45-2825 files

LLVM/project 29c2660utils/bazel/llvm-project-overlay/flang/lib/Utils BUILD.bazel

[Bazel] Fixes 5ee2778 (#217305)

This fixes 5ee2778b60725219579eb6d439e6b250c2ff1f85 (#212251).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=5ee2778b60725219579eb6d439e6b250c2ff1f85

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+2-0utils/bazel/llvm-project-overlay/flang/lib/Utils/BUILD.bazel
+2-01 files

LLVM/project 31b6269flang/lib/Lower HlfirIntrinsics.cpp, flang/lib/Optimizer/HLFIR/IR HLFIROps.cpp

Revert "[Flang][HLFIR] Lower PACK(array, .TRUE.) to hlfir.reshape (#213603)"

This reverts commit b5e18ba8d7439f5ba6da35c0a0de71f06651003e.
DeltaFile
+0-109flang/test/HLFIR/simplify-hlfir-intrinsics-pack.fir
+0-67flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
+8-41flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp
+0-48flang/test/Lower/HLFIR/pack_scalar_true.f90
+1-29flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
+0-25flang/lib/Lower/HlfirIntrinsics.cpp
+9-3194 files not shown
+35-35810 files

LLVM/project df37e2bllvm/lib/Transforms/Vectorize LoopVectorizationPlanner.cpp LoopVectorizationPlanner.h

[LV] Take LoopVectorizeHints from VFSelectionContext (NFC) (#216737)

VFSelectionContext already holds the LoopVectorizeHints for the loop, so
both the planner and LoopVectorizationCostModel can use it from
VFSelectionContext.

This moves out another piece of VF independent information.

PR: https://github.com/llvm/llvm-project/pull/216737
DeltaFile
+16-18llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+5-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+1-1llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+22-233 files

LLVM/project 5b9a230llvm/include/llvm/CodeGen/GlobalISel MIPatternMatch.h, llvm/lib/Target/RISCV/GISel RISCVInstructionSelector.cpp

GlobalISel: Let m_GSExtInReg match its immediate with a sub-matcher

Add m_SpecificImm/m_Imm literal-immediate operand matchers, and give
m_GSExtInReg an optional immediate sub-matcher argument instead of binding the
raw int64_t. The RISCV selectSExtBits complex renderer now matches the width
directly with m_SpecificImm(Bits). NFC.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
DeltaFile
+45-10llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+4-5llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+49-152 files

LLVM/project dc44a1fmlir/include/mlir/Dialect/GPU/IR GPUOps.td, mlir/test/Conversion/GPUToNVVM wmma-ops-to-nvvm.mlir

[MLIR][GPU] Enable strict property assembly format (#217278)

Enable the strict property assembly format mode for the GPU dialect.
Remove unnecessary property dictionaries from GPU operation assembly
formats and spell subgroup MMA properties directly in the assembly
syntax.

Assisted-by: Codex
DeltaFile
+67-67mlir/test/Conversion/VectorToGPU/vector-to-mma-ops.mlir
+12-12mlir/test/Dialect/GPU/fold-memref-alias-ops.mlir
+12-12mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-khr-coop-matrix.mlir
+13-10mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
+10-10mlir/test/Conversion/GPUToNVVM/wmma-ops-to-nvvm.mlir
+9-9mlir/test/Dialect/GPU/invalid.mlir
+123-12010 files not shown
+162-15816 files

LLVM/project 62f90c1llvm/lib/Transforms/InstCombine InstCombineCalls.cpp, llvm/test/Transforms/InstCombine intrinsic-distributive-laws-crash.ll

[InstCombine] fix assertion failure in intrinsic distributive laws (#216483)

Fixes #216295.

Prevent's invalid cast to `BinaryOperator` when simplifying intrinsic
distributive laws in `InstCombine`.
DeltaFile
+32-0llvm/test/Transforms/InstCombine/intrinsic-distributive-laws-crash.ll
+9-15llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+41-152 files

LLVM/project d141332llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen TargetLoweringBase.cpp

[CodeGen][AArch64] Use vector parts for internal non-power-of-two vectors (#213982)

Decompose fixed-length, non-power-of-two vectors into legal vector
parts, rather than scalarizing these. Apply this only to internal register 
values.

Continue using the existing scalar breakdown for arguments and returns,
preserving the existing calling convention behaviour.
DeltaFile
+476-0llvm/test/CodeGen/AArch64/non-pow2-fixed-vectors.ll
+85-43llvm/include/llvm/CodeGen/TargetLowering.h
+54-22llvm/test/CodeGen/AArch64/phi.ll
+34-23llvm/lib/CodeGen/TargetLoweringBase.cpp
+5-3llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+4-0llvm/lib/Target/AArch64/AArch64ISelLowering.h
+658-911 files not shown
+659-927 files

LLVM/project 9f4703cllvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp, llvm/test/CodeGen/PowerPC fp128-vector-setcc.ll

[LegalizeTypes] Allow v1i128 as a valid SETCC result type during vector operand scalarization (#216136)

PowerPC registers v1i128 as a legal type when P8Altivec is available.
When lowering <4 x fp128> comparisons, the type legalizer hits a v1i1
only assert. Generalize the assert to accept any single-element vector
result type.
DeltaFile
+22-0llvm/test/CodeGen/PowerPC/fp128-vector-setcc.ll
+7-4llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+29-42 files