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Add the ability to provide a scripted "step through" plan. (#218812)

This is a scripted equivalent of the "trampoline handler" that lldb uses
to run to the target of a dynamic dispatch stub, or to the target of
std::function, or an objc message send.

[lld] strip __swift_FORCE_LOAD_$ dyld fixups in __DATA,__const (#214584)

Add a new flag to optionally strip swift FORCE_LOAD symbol sections,
which are used by the compiler to force dylib load commands. This has
shown a ~30% reduction in binds for some large applications, with
corresponding size reduction for the number of elided pointers.

This is based on a similar ld64 optimisation that removes the fixups for
the force load sections:

https://github.com/keith/ld64/blob/37d025c536163da612874999d0ea94a4e4e475e7/src/ld/passes/dylibs.cpp#L385-L389

[llvm][NFC] remove an unused variable (#219889)

Remove a variable `InsIndex` which was defined but never used anywhere.

Signed-off-by: Hardik Kumar <hardikxk at gmail.com>

[flang][cuda] Extend CUF kernel host stub line table to the END statement (#219608)

`CUFDeviceFuncTransform` creates a host stub for a kernel, with an empty
body holding nothing but a `return`. Both the stub and its `return` keep
only the original declaration location, so the stub's line table ends up
with rows only for the declaration line.

This change extends the line table to span the procedure's whole source
line range, by using the location of the original `END` statement for
the stub's `return`. A debugger can then set a breakpoint on a line
inside the kernel body and stop there.

Lit test `cuda-device-func-transform.mlir` is enhanced to guard this
change.

AMDGPU: Add visible features for aperture regs, doorbell ID and AGPR alloc (#219985)

These fields are needed to migrate AMDGPUAttributor to using
TargetParser information instead of subtarget features.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

[Test] Add missing dependency for llvm-ordergen (#219992)

Without this dependency, `llvm-ordergen` is not build when running the
tests only, resulting in failures for the tool.

[LoopFusion] Allow fusing adjacent loops with same-iteration scalar deps (#216242)

The scalar dependence branch rejected all non-invariant flow deps, while
the array branch already accepted EQ-only direction vectors. Treat
same-iteration scalar flow/anti patterns as safe to fuse when the
dependence direction has no GT/LT component, matching the array logic.

Extra tests are added in
https://github.com/llvm/llvm-project/pull/216243

[GlobPattern] add AsLiteral to help lld determine if a symbol is literal (#215854)

lld determines if a `symbolName` is literal by `find_first_of("*?[]")`,
which is not accurate and ignored escape characters, we do the
following:

1. Add a new API `std::optional<std::string> asLiteral(...)` that dumps
the pattern as a literal string if it is one.
2. All `symbolNames` are considered as `GlobPattern` first to leverage
`asLeteral` to help us determine if a string is a literal. The quick
path in during `GlobPattern` construction is `if
(!S.find_first_of(PrefixMetas)) return Pat;`, so for strings without
`*?[]` (most of the `symbolName`s), the performance should be about the
same.
3. `symbolName`s that are literal go back to hashing like lld did before

Added tests in lld and unit test for GlobPattern

---------

Co-authored-by: Ellis Hoag <ellis.sparky.hoag at gmail.com>

[lldb][MSABI] Take offset of vbptr into account (#190679)

In the MS ABI, the offset found in the virtual base table is relative to
the virtual base pointer. See Clang's
`MicrosoftCXXABI::emitVBTableDefinition`:
https://github.com/llvm/llvm-project/blob/1a0ca1019d214a24b55a45704dc71fa183672362/clang/lib/CodeGen/MicrosoftCXXABI.cpp#L2247-L2261

We previously assumed the offset was relative to the record's start.

For example for `B` in
```cpp
struct Extra {
  int e1 = 1;
};
struct A {
  int a = 3;
};
struct B : public Extra, public virtual A {
  int b = 4;

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Rename "mayAlias" -> "MayAlias"

Hexagon: Use use_instructions in checkHVXUses32/checkHVXUses16 (#220003)

The loops only inspect the using instruction, so iterate instructions
directly instead of operands and their parents.

Co-authored-by: Claude (Claude-Opus-4.8)

PowerPC: Use use_instr_nodbg_begin in PPCReduceCRLogicals (#219988)

Fetch the using instruction directly through the instruction iterator
instead of dereferencing an operand's parent.

Co-authored-by: Claude (Claude-Opus-4.8)

add machine verifier check

fix pattern

update test

calling conv update

Legalize sgpr16 in sdag

add more cases

Legalize sgpr16 copy in gisel

fold sgpr32 via vgpr16

[llvm] Remove unused includes (NFC) (#219915)

Identified by clang-tidy and verified with local builds.

[NVPTX] Use MCSymbols in Isel, remove mutable StrPool (NFC) (#219530)

Using MCSymbols is more idiomatic and allows us to remove mutable
members from the TM and simplifies MFI data structures.

[AMDGPU] Make amdgpu.noclobber respect acquire operations

AMDGPUAnnotateUniformValues should annotate uniform global loads as
`!amdgpu.noclobber` if the memory they are reading is never clobbered (since
kernel launch) before the load is executed. That allows the backend to use
scalar `s_load_*` instructions instead of vector loads (which would otherwise
be illegal because the scalar cache is not kept coherent with the vector
cache).

So far, loads were annotated if the thread executing the load has not clobbered
the relevant memory location, but changes from concurrent threads that were
acquired via synchronization were ignored (which is unsound).

This patch defines a semantics for `!amdgpu.noclobber` metadata in the
AMDGPUUsage and changes AMDGPUAnnotateUniformValues to respect that semantics.
Now, loads are no longer annotated if they are atomic or if an acquire fence or
load can be executed before them (since they can read from stores in other
threads in these cases).


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[AMDGPU] Add and generalize noclobber tests

Some noclobber tests included barrier-and-fence constructs that are unrelated
to what the tests are supposed to check. So far, that hasn't been an issue
because barriers and fences were ignored when inferring noclobber annotations.
However, fences do need to be considered for noclobber annotations (since they
can make clobbering stores from other threads visible in the considered
thread). This PR removes those unrelated barriers and fences so that the tests
will still be meaningful once a subsequent PR fixes the noclobber inference.
For the same reason, some `seq_cst` memory orderings in the tests are relaxed
to `monotonic`: `seq_cst` includes acquire semantics which can bring in
clobbering stores from other threads.

The PR also adds tests to cover more cases in the amdgpu.noclobber inference.
Some of them highlight more problematic cases in the current implementation
that subsequent PRs should fix.

The PR further regenerates all opt check lines via `update_test_checks.py`, so
that it's easier to keep them up to date.

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Hexagon: Use use_instructions in checkHVXUses32/checkHVXUses16

The loops only inspect the using instruction, so iterate instructions
directly instead of operands and their parents.

Co-authored-by: Claude (Claude-Opus-4.8)

[flang] Enable FIR loop invariant code motion by default (#218703)

The FIR loop invariant code motion pass was added in #173438, where it
was disabled by default. This enables it for optimization levels above
`-O0`. The option `-disable-fir-licm` has been added in place of
`-enable-fir-licm`. The pass itself is unchanged.

Relates to #208086 and fixes #110613. Tests updated.

Assisted-by: Copilot

AMDGPU: Add visible features for aperture regs, doorbell ID and AGPR alloc

These fields are needed to migrate AMDGPUAttributor to using TargetParser
information instead of subtarget features.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

RISCV: Pass instruction and operand index to replacePtrWithInt (#219958)

The helper used the operand's parent instruction as the insertion point.
Pass the containing instruction and operand index directly so it no
longer depends on MachineOperand::getParent().

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

[AMDGPU][GIsel] Make getBaseWithConstantantOffset see `or disjoint` (#219551)

This change is split from #207821, where it was made in the process of
implementing that change to make getBaseWithConstantOffset() have the
same behavior as the SelectionDAG version.

AI disclosure: I'm pretty sure this was Codex code, and I do recall it
being an AI-found discrepancy.

[clang][bytecode][NFC] Remove an unreachable parameter check (#219977)

We check this both in Context and in ByteCodeEmitter. The latter is not
reachable since the former will already not create Function instances
for such functions.