LLVM/project 4812a67clang/lib/CIR/CodeGen CIRGenBuiltinAMDGPU.cpp, clang/test/CIR/CodeGenHIP builtins-amdgcn.hip builtins-amdgcn-vi-f16.hip

[CIR][AMDGPU] Add support for AMDGCN frexp_mant builtins (#198121)

Adds codegen for the following AMDGCN frexp mantissa builtins:

- __builtin_amdgcn_frexp_mant (double)
- __builtin_amdgcn_frexp_mantf (float)
- __builtin_amdgcn_frexp_manth (half)

These are lowered to the corresponding `llvm.amdgcn.frexp.mant`
intrinsic.
DeltaFile
+16-0clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
+8-0clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
+2-4clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+26-43 files

LLVM/project acd3fcfclang/lib/CodeGen CodeGenModule.cpp, clang/test/CodeGen call-graph-section.cpp call-graph-section-templates.cpp

[clang] Emit call graph type metadata for internal linkage symbols (#210194)
DeltaFile
+18-18clang/test/CodeGen/call-graph-section.cpp
+18-16clang/lib/CodeGen/CodeGenModule.cpp
+13-13clang/test/CodeGen/call-graph-section-templates.cpp
+9-9llvm/test/CodeGen/ARM/call-graph-section-assembly.ll
+8-8llvm/test/CodeGen/X86/call-graph-section-tailcall.ll
+8-8clang/test/CodeGen/call-graph-section.c
+74-7214 files not shown
+135-13720 files

LLVM/project f9b7acblld/ELF Relocations.h

[NFC][ELF] Remove unused R_TLS*_HINT RelExprs (#210519)

As of 5e87f8147d68 ("[ELF] Add target-specific relocation scanning for
PPC32 (#181517)") these are never generated, and as of 46d29d43ba8e
("[ELF] Remove unused handleTlsRelocation (#184951)") these are not even
handled anywhere.
DeltaFile
+0-2lld/ELF/Relocations.h
+0-21 files

LLVM/project 2144ee4lld/ELF Relocations.h

[NFC][ELF] Remove unused R_TLSDESC_CALL RelExpr (#210518)

As of 4ea72c1e8cbd ("[ELF] Add target-specific relocation scanning for
RISC-V (#181332)") this is never generated, and as of 46d29d43ba8e
("[ELF] Remove unused handleTlsRelocation (#184951)") this is not even
handled anywhere.
DeltaFile
+0-1lld/ELF/Relocations.h
+0-11 files

LLVM/project 0b5073alld/ELF InputSection.cpp Relocations.h

[NFC][ELF] Remove unused R_RELAX_TLS_* RelExprs (#210517)

As of 46d29d43ba8e ("[ELF] Remove unused handleTlsRelocation (#184951)")
these are never generated.
DeltaFile
+0-7lld/ELF/InputSection.cpp
+0-7lld/ELF/Relocations.h
+0-142 files

LLVM/project 6e4eadcflang/lib/Parser openmp-parsers.cpp, llvm/include/llvm/Frontend/OpenMP OMP.h

[OpenMP] Add constexpr enum ranges for all clauses and all directives
DeltaFile
+9-0llvm/include/llvm/Frontend/OpenMP/OMP.h
+2-5flang/lib/Parser/openmp-parsers.cpp
+2-4llvm/lib/Frontend/OpenMP/OMP.cpp
+2-4llvm/unittests/Frontend/OpenMPDirectiveNameParserTest.cpp
+15-134 files

LLVM/project c739ce6llvm/test/TableGen subreg-index-overflow-allowed.td subreg-index-overflow.td, llvm/utils/TableGen/Common CodeGenRegisters.cpp CodeGenRegisters.h

[TableGen] Diagnose sub-register indices that overflow their register (#206346)
DeltaFile
+79-0llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+37-0llvm/test/TableGen/subreg-index-overflow-allowed.td
+29-0llvm/test/TableGen/subreg-index-overflow.td
+5-0llvm/utils/TableGen/Common/CodeGenRegisters.h
+150-04 files

LLVM/project 53096b7llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86/apx sub.ll

[X86][APX] Optimize usub.sat(X,1) to cmp+adc with NDD (#208475)

When NDD is available, usub.sat(X, 1) is lowered from xor+sub+cmov (3
insns) to cmp+adc (2 insns).

All X86 tests pass.

Fixes #207888

Co-authored-by: AntonyCJ30 <cj6186609 at gmail@gmail.com>
DeltaFile
+188-195llvm/test/CodeGen/X86/apx/sub.ll
+24-2llvm/lib/Target/X86/X86ISelLowering.cpp
+212-1972 files

LLVM/project be68a88llvm/include/llvm/ADT Sequence.h

[ADT] Fix non-assertion build after 36c812f771 (#210511)

E.g. https://lab.llvm.org/buildbot/#/builders/228/builds/5253
DeltaFile
+7-2llvm/include/llvm/ADT/Sequence.h
+7-21 files

LLVM/project f6d9ec4clang/lib/Headers riscv_packed_simd.h, clang/test/CodeGen/RISCV rvp-intrinsics.c

[RISCV] Add packed narrowing convert intrinsics (#210389)

Add RISC-V P-extension packed narrowing convert header APIs for `pncvt`
and `pncvth`.

The new APIs lower through generic IR: RV32 uses truncate / logical
shift plus truncate forms, while RV64 uses existing packed unzip shuffle
forms. This reuses the existing backend lowering and TableGen aliases
rather than adding intrinsic-specific lowering.

Tests cover Clang IR generation and cross-project header assembly checks
for RV32/RV64 spec-listed mnemonics.
DeltaFile
+158-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+50-0clang/lib/Headers/riscv_packed_simd.h
+42-0cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+250-03 files

LLVM/project 94b08b5llvm/lib/Support/Unix Signals.inc

[Support] Improve the logic for re-raising signals (#177864)

On most systems, checking `si_pid` is not actually valid unless
`si_code` equals one of the relevant signal codes (`SI_USER`,
`SI_QUEUE`, and on some OSs, `SI_LWP`), or the signal is `SIGCHLD`. So
on e.g. NetBSD, we would misinterpret the `SIGSEGV` fault address as the
sending PID and incorrectly conclude that the signal came from a
different process.

But as far as I can tell, there's not even a valid reason for us to be
checking `si_pid != getpid()`, because the signal could very well have
been explicitly sent by another thread in the current process. So we
really just need to check `si_code` for the aforementioned signal codes.

Darwin is the exception because it just doesn't set `si_code` at all in
the case of the `SI_*` signal codes. So keep the old logic there, even
though it misses the corner case of signals sent by a thread in the
current process.


    [4 lines not shown]
DeltaFile
+33-12llvm/lib/Support/Unix/Signals.inc
+33-121 files

LLVM/project af0c933llvm/test/CodeGen/PowerPC ppcf128-constrained-fp-intrinsics.ll, llvm/test/Transforms/EarlyCSE replace-calls-def-attrs.ll

[IR] Make semantics of strictfp consistent (#209465)

Although the section on constrainedfp in the LangRef clearly states "All
function definitions that use constrained floating point intrinsics must
have the strictfp attribute", indicating that a function with strictfp
calls must be marked with strictfp, the general description of strictfp
does not specify this. Refine its semantics and make it so, eliminating
the inconsistency.
DeltaFile
+35-32llvm/test/Transforms/EarlyCSE/replace-calls-def-attrs.ll
+25-25mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+22-18llvm/test/Transforms/InstCombine/erf.ll
+16-14llvm/test/Transforms/SimplifyCFG/X86/merge-compatible-invokes-of-landingpad.ll
+24-0llvm/unittests/IR/VerifierTest.cpp
+2-14llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
+124-10317 files not shown
+169-13623 files

LLVM/project 2b90a32llvm/include/llvm/ADT Sequence.h

format
DeltaFile
+2-2llvm/include/llvm/ADT/Sequence.h
+2-21 files

LLVM/project 303ca9fllvm/include/llvm/ADT Sequence.h

[ADT] Fix non-assertion build after 36c812f771

https://lab.llvm.org/buildbot/#/builders/228/builds/5253
DeltaFile
+6-1llvm/include/llvm/ADT/Sequence.h
+6-11 files

LLVM/project fdf1adcorc-rt/include/orc-rt Session.h

[orc-rt] Add comment for Session::HandlerTag type. NFC. (#210510)
DeltaFile
+2-0orc-rt/include/orc-rt/Session.h
+2-01 files

LLVM/project 36c812fllvm/include/llvm/ADT Sequence.h, llvm/unittests/ADT SequenceTest.cpp

[ADT] Make enum iterators constexpr (#210405)

<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
DeltaFile
+137-26llvm/unittests/ADT/SequenceTest.cpp
+89-57llvm/include/llvm/ADT/Sequence.h
+226-832 files

LLVM/project 7b44629llvm/include/llvm/Support MathExtras.h, llvm/unittests/Support MathExtrasTest.cpp

[Support] Add constexpr versions of Add/Sub/MulOverflow (#210404)

<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
DeltaFile
+131-0llvm/unittests/Support/MathExtrasTest.cpp
+79-43llvm/include/llvm/Support/MathExtras.h
+210-432 files

LLVM/project d199b28orc-rt/docs Design.md, orc-rt/include/orc-rt Session.h

[orc-rt] Drop callManagedCodeAsync; tokens guard execution (#210508)

callManagedCodeSync is renamed to callManagedCode, and
callManagedCodeAsync is removed.

callManagedCodeAsync held a ManagedCodeTaskGroup token from the initial
call until the async continuation ran -- across the gap in which the
call is suspended and no managed code is executing. A token is meant to
guard managed code that is executing on a stack, so holding one across
that gap guards nothing while blocking shutdown.

callManagedCode holds a token only for the synchronous call to the
wrapped function, including anything the function runs inline on the
same thread before returning. An async function is called the same way,
with its continuation passed as an ordinary argument. Work deferred past
the function's return -- stashed, or handed to another thread -- runs on
a stack the token no longer guards; whoever later runs it is responsible
for ensuring a token covers it, acquiring one and aborting if the
acquire is denied.

    [3 lines not shown]
DeltaFile
+18-106orc-rt/test/unit/SessionTest.cpp
+36-76orc-rt/include/orc-rt/Session.h
+25-0orc-rt/docs/Design.md
+79-1823 files

LLVM/project 4525be9llvm/docs NVPTXUsage.rst NVPTXUsage.md, llvm/test/CodeGen/NVPTX atomicrmw-sm60.ll atomicrmw-sm70.ll

Rebase, improvements

Created using spr 1.3.7
DeltaFile
+0-4,767llvm/docs/NVPTXUsage.rst
+2,949-1,487llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
+2,871-1,461llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
+4,253-0llvm/docs/NVPTXUsage.md
+1,635-849llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+982-327llvm/test/Transforms/LoopIdiom/cyclic-redundancy-check.ll
+12,690-8,8911,255 files not shown
+67,694-30,4231,261 files

LLVM/project 3b3fa14clang/lib/Interpreter Interpreter.cpp

[Clang][Interpreter] Respect default setting on Windows

MSCV does not support the -fPIC option. When it is passed, Clang falls
back to PIC level 2 on x86_64 and to a static binary on AArch64. Without
-fPIC, however, PIC is already enabled by default on both targets.

As a result, the PCH (built with the default PIC level by toolchain
hint) and the clang-repl instance (using the fallback PIC level) end up
with different PIC settings, consuming a mismatch.

Avoid passing -fPIC when targeting MSVC on Windows. This preserve the
existing semantics, since PIC is already enabled by default, while
ensuring that both the PCH and clang-repl use the same PIC level.
DeltaFile
+8-2clang/lib/Interpreter/Interpreter.cpp
+8-21 files

LLVM/project 0c5b225llvm/lib/Analysis ScalarEvolution.cpp, llvm/test/Transforms/IndVarSimplify strengthen-overflow.ll drop-exact.ll

[SCEV] Infer no-wrap flags for shl by a constant. (#208434)

Treat `shl %a, C` as `mul %a, 1 << C` in
getStrengthenedNoWrapFlagsFromBinOp
if possible.

Only transfer NSW from shl to mul, if the shift amount is < Bitwidth -
1, otherwise the result would be more poisonous.

Alive2 proofs: https://alive2.llvm.org/ce/z/iBPpkv

Compile-time impact in noise:
https://llvm-compile-time-tracker.com/compare.php?from=a037729976f91dc11b41a76834dfca9d8812c4fe&to=2050d622aed5606774f0902b352bbb2142e654e1&stat=instructions:u

PR: https://github.com/llvm/llvm-project/pull/208434
DeltaFile
+120-0llvm/test/Transforms/IndVarSimplify/strengthen-overflow.ll
+21-10llvm/lib/Analysis/ScalarEvolution.cpp
+2-2llvm/test/Transforms/IndVarSimplify/drop-exact.ll
+1-1llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
+1-1llvm/test/Transforms/IndVarSimplify/pr66066.ll
+145-145 files

LLVM/project af0aa94llvm/lib/Target/AArch64 AArch64AsmPrinter.cpp AArch64InstrInfo.td, llvm/test/CodeGen/AArch64 ptrauth-intrinsic-auth-resign-with-blend.ll

[AArch64][PAC] Rework the expansion of AUT/AUTPAC pseudos (#169699)

Refactor `AArch64AsmPrinter::emitPtrauthAuthResign` to improve
readability and tune the conditions when `emitPtrauthDiscriminator` is
allowed to clobber address discriminator operands.

When resigning, do not clobber address discriminator register used for
authentication if it is also used for signing. Such clobbering would
prevent passing raw, 64-bit value as the new discriminator. Clarify
other corner cases of clobbering address discriminator operands.

Reuse `enum PtrauthCheckMode` instead of separate `ShouldCheck` and
`ShouldTrap` flags and drop its `Default` enumerator.
DeltaFile
+443-10llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-with-blend.ll
+106-73llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+6-0llvm/lib/Target/AArch64/AArch64InstrInfo.td
+555-833 files

LLVM/project c69896amlir/lib/Interfaces ValueBoundsOpInterface.cpp

[mlir][interface] Use populateAndCompare cleanup compare (NFC) (#200156)
DeltaFile
+1-3mlir/lib/Interfaces/ValueBoundsOpInterface.cpp
+1-31 files

LLVM/project 1f4d6acmlir/lib/Dialect/Bufferization/IR BufferizationOps.cpp, mlir/test/Dialect/Bufferization canonicalize.mlir

[mlir][bufferization] Avoid invalid memref.cast in to_buffer folding (#208973)

Fixes #202782

When folding bufferization.to_buffer(bufferization.to_tensor(...)), only
create a memref.cast if the source and destination memref types are
cast-compatible.

This avoids asserting on unranked memrefs with different memory spaces
and leaves the original bufferization ops in place instead.

 Assisted-by: OpenAI Codex
DeltaFile
+18-0mlir/test/Dialect/Bufferization/canonicalize.mlir
+5-4mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
+23-42 files

LLVM/project e96755fllvm/lib/Transforms/Vectorize VPlanUtils.cpp VPlanUtils.h

[VPlan] Factor vputils::getOpcodeOrIntrinsicID (NFC) (#208993)

The check for recipes in vputils::isElementWise is necessary to prevent
regressions.
DeltaFile
+27-27llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+8-4llvm/lib/Transforms/Vectorize/VPlanUtils.h
+2-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+3-0llvm/lib/Transforms/Vectorize/VPlan.h
+40-354 files

LLVM/project d46a352lldb/test/API/python_api/sbvalue_set_type_synthetic_override TestSBValueSetTypeSyntheticOverride.py

[lldb] Fix TestSBValueSetTypeSyntheticOverride with libstdc++ (#210495)

My test added in #209056 assumed that a `CXXSyntheticChildren`
implementation for `std::vector` is readily available on all platforms,
that is not the case.

Do the simplest thing and remove this part of the test for now.

Fixes: https://lab.llvm.org/buildbot/#/builders/59/builds/35839
```
FAIL: test (TestSBValueSetTypeSyntheticOverride.TestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/llvm-project/lldb/test/API/python_api/sbvalue_set_type_synthetic_override/TestSBValueSetTypeSyntheticOverride.py", line 22, in test
    self.checkOverride(vec, before=None)
  File "/home/tcwg-buildbot/worker/lldb-aarch64-ubuntu/llvm-project/lldb/test/API/python_api/sbvalue_set_type_synthetic_override/TestSBValueSetTypeSyntheticOverride.py", line 43, in checkOverride
    self.assertIsNone(impl_before)
AssertionError: <lldb.formatters.cpp.gnu_libstdcpp.StdVectorSynthProvider object at 0xfb088f787bb0> is not None
```
DeltaFile
+15-8lldb/test/API/python_api/sbvalue_set_type_synthetic_override/TestSBValueSetTypeSyntheticOverride.py
+15-81 files

LLVM/project 1faa9f7llvm/lib/Transforms/Vectorize VPlanTransforms.cpp VPlanEVLTailFolding.cpp

[VPlan] Infer SrcTy in createScalarExtOrTrunc (NFC) (#210423)

The argument is redundant and can be inferred from Op.
DeltaFile
+10-13llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+6-11llvm/lib/Transforms/Vectorize/VPlanEVLTailFolding.cpp
+4-5llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
+4-4llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+2-3llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+26-365 files

LLVM/project 8c2d7ccmlir/include/mlir/IR SymbolInterfaces.td, mlir/lib/IR SymbolTable.cpp

[mlir][IR] Add SymbolUserTypeInterface (#198435)

This change adds SymbolUserTypeInterface, analogous to
SymbolUserAttrInterface, and extends SymbolTable verification to check
participating types.

Verification visits the types owned by an operation, (operand/result
types, block argument types, attribute-contained types, nested type
parameters) and checks each distinct type at most once, interrupting on
the first failure. Deduplication spans the whole symbol-table walk, so a
type used by multiple operations is checked only once.

Attribute (SymbolUserAttrInterface) verification also gets deduped the
same way.

Assisted-by: Codex (OpenAI)
Assisted-by: Claude (Anthropic)
DeltaFile
+95-0mlir/test/IR/test-verifiers-symbol-user-type.mlir
+57-0mlir/lib/IR/SymbolTable.cpp
+27-18utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+20-1mlir/include/mlir/IR/SymbolInterfaces.td
+13-0mlir/test/lib/Dialect/Test/TestTypes.cpp
+9-0mlir/test/lib/Dialect/Test/TestTypeDefs.td
+221-193 files not shown
+225-199 files

LLVM/project ccd0e98lldb/source/Plugins/SymbolFile/NativePDB UdtRecordCompleter.cpp, lldb/test/API/lang/cpp/enum-limits TestCPPEnumLimits.py main.cpp

[lldb][NativePDB] Fix width and signedness of enum constants (#210338)

Enumerator values aren't always encoded in the correct bit width and
signedness. This happens with both MSVC and Clang.

On MSVC, unsigned 64bit enumerators can be encoded as signed. For
example `ULONGLONG_MAX` will be encoded as `-1`.
Clang/LLVM will always encode the values as unsigned.

Example: https://godbolt.org/z/96YjGW48W.

I fixed this by setting the expected width and signedness when creating
the enumerator constant. We can't use a shell test like for the other
PDB tests, because no output shows the enum values.
DeltaFile
+91-0lldb/test/API/lang/cpp/enum-limits/TestCPPEnumLimits.py
+48-0lldb/test/API/lang/cpp/enum-limits/main.cpp
+17-1lldb/source/Plugins/SymbolFile/NativePDB/UdtRecordCompleter.cpp
+3-0lldb/test/API/lang/cpp/enum-limits/Makefile
+159-14 files

LLVM/project 2730fc8llvm/lib/Target/SPIRV SPIRVInstructionSelector.cpp, llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16 bfloat16.ll

[SPIR-V] Handle bfloat in getZeroFP/getOneFP (#202859)

Related spirv-val change:
https://github.com/KhronosGroup/SPIRV-Tools/pull/6734

---------

Co-authored-by: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
DeltaFile
+57-8llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16.ll
+4-0llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+61-82 files