[AMDGPU] Fix CFI emission when scratch instructions are used to spill
4b1cfc5d7c606e "[NFCI][AMDGPU] Final touch before moving to
`GET_SUBTARGETINFO_MACRO` (#177401)" (or more generally the move to
hasFlatScratchEnabled over just enableFlatScratch) was missed during the
CFI upstreaming for AMDGPU, and so we currently define the CFA
incorrectly for the architected flat scratch case.
This incorrect CFI is generated for e.g. gfx942. For such architecture,
the stack pointer (s32) holds a swizzled address (per-lane offset) but
the CFA needs to be an unswizzled address (per-wave).
In the incorrect program, we have a prologue looking like:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_mov_b32 s0, s33
s_mov_b32 s33, s32
[...]
s_add_i32 s32, s32, 16
[24 lines not shown]
[AMDGPU] Add stackPtrOffsetReg to llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir (#209533)
Prepare for this being observable to the CFA generation code.
Reland "[compiler-rt] [sanitizer_common] Fix SIGSEGV in ForEachMappedRegion for DSOs with custom image base" (#209576)
Attempt 2 at #206299, fixing a linkage issue with gotsan on older
versions of glibc. Rather than forcing linkage of libdl (which may not
be safe with go), this just disables the dladdr usage under go builds.
This bug only affected MSAN and DFSAN anyway, and the code should be
unused by TSAN.
`ForEachMappedRegion` processes dynamic linker map entries to track
loaded segments. However, it assumes map->l_addr is the address of the
ELF header. For DSOs linked with a custom preferred image base offset
(e.g. -Wl,--image-base=0x4000000), `map->l_addr` contains the relocation
bias: `map->l_addr = actual_load_address - preferred_base`
In this case, map->l_addr points below the first loaded segment in
unmapped or PROT_NONE memory. Doing a read dereference at this address
triggers a SIGSEGV. Add a call to dladdr() on the dynamic section
pointer map->l_ld to obtain the true ELF header base address.
[8 lines not shown]
Revert "[PGO][ICP] Prevent indirect call promotion to functions with incompatible target features" (#209572)
Reverts llvm/llvm-project#208774
The failure that caused the revert last time should be fixed by
37b8e765ce4837a7577e6f762bcdffe4b232759c.
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (38)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (37)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (35)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (36)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (34)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (33)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (32) (#209561)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
[Clang][C2y] Add support for if declarations (N3356 paper) (#198244)
Add support for _if declarations_ in `C2y` mode by exploiting existing
C++ code.
The only new changes to the code is narrowing the code path to `C` mode
and introduce new errors and warnings for some pitfalls with the syntax
and what is expected from the standard and old language modes.
It should be noted that the first clause in the standard paper can only
be declaration. This means we can't allow expression statement in the
first clause of the condition, and that's the goal of the new
warnings/errors. Also this is different from C++ grammar.
[libc] Fix potential timespec type mismatch for arm32 targets in futex_utils.h. (#209556)
This causes the arm32 build bots to hang.
Assisted-by: Gemini 3.5 Flash.
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (31) (#209560)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
[lit] Don't crash in _write_message when getsourcefile() returns None (#206957)
LitConfig._write_message currently derives the file to report a
note()/warning()/ error() against with:
file = os.path.abspath(inspect.getsourcefile(f))
inspect.getsourcefile(f) returns None when the calling frame's source is
not on disk and not in linecache -- for example when lit is packaged
into a zip archive, or when a config is exec'd from a synthetic
filename. In that case os.path.abspath(None) raises TypeError: expected
str, bytes or os.PathLike object, not NoneType, which turns an
informational diagnostic into a fatal config-parse crash.
Fall back to inspect.getfile(f), which returns the frame's co_filename
and is always a str, so the diagnostic is emitted (tagged with
co_filename) instead of crashing. Since all tests normally pass
currently on build bots, this new code should never trigger and only
works as a backup in the case I'm running into on a different test infra
[4 lines not shown]
[SLP] Fix ScatterVectorize reorder desyncing scalars from operands
Record the reorder in ReorderIndices instead of permuting the scatter node's
Scalars, keeping them aligned with the per-lane operand list the scheduler
reads.
Fixes #209444
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/209594
[flang][cuda] Size managed globals with descriptor components via LLVM Type (#209577)
When we do `-cuda -gpu=unified` (or `managed`) on a derived type with an
allocatable/pointer component, recent change
https://github.com/llvm/llvm-project/pull/209292 implicitly
attributed the component making lowering place the enclosing
derived-type global
in CUF managed memory. `CUFAddConstructor` then sizes that global via
`getTypeSizeAndAlignmentOrCrash`, which has no case for the descriptor
component
(`!fir.box<...>`) and aborts.
With this change, instead of aborting, we fall back to converting the
global to its LLVM type which
inlines the fixed-size descriptors, and query the data layout.
[mlir][bufferization] Handle arith.select-based deallocs in static memory planner
Allocs freed indirectly via arith.select chains were previously skipped.
This adds forward select-chain traversal so patterns like:
%2 = arith.select %c, %0, %1
memref.dealloc %2
are now handled correctly.
A group constraint ensures that all allocs sharing a select-based
dealloc are either all placed in the arena or all skipped — putting
one alloc in while leaving its peer out would break the dealloc.
Also fixes the O(n*m) block scan in buildAllocInfos by doing a single
upfront pass with a DenseMap index.
Tests added for single-alloc select, shared select-dealloc, and the
two-select two-dealloc pattern.
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (30) (#209559)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (29) (#209558)
Mechanically migrate the command-line target spelling on llc/opt RUN
lines in llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the
folded subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
[VPlan] Introduce VPIRFlags::getNWFlagsOrNone (NFC) (#207176)
Similar to getFMFOrNone. Also introduce a default WrapFlagsTy
constructor to go along with it.
[AMDGPU] Fix CFI emission when scratch instructions are used to spill
4b1cfc5d7c606e "[NFCI][AMDGPU] Final touch before moving to
`GET_SUBTARGETINFO_MACRO` (#177401)" (or more generally the move to
hasFlatScratchEnabled over just enableFlatScratch) was missed during the
CFI upstreaming for AMDGPU, and so we currently define the CFA
incorrectly for the architected flat scratch case.
This incorrect CFI is generated for e.g. gfx942. For such architecture,
the stack pointer (s32) holds a swizzled address (per-lane offset) but
the CFA needs to be an unswizzled address (per-wave).
In the incorrect program, we have a prologue looking like:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
s_mov_b32 s0, s33
s_mov_b32 s33, s32
[...]
s_add_i32 s32, s32, 16
[24 lines not shown]
[AMDGPU] Add stackPtrOffsetReg to llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
Prepare for this being observable to the CFA generation code.
Change-Id: I56d00133148fd2c8f0e0ed41edca446553c664bc
[AMDGPU] Fix type for DWARF register number in SIFrameLowering (#209535)
It so happened that using MCRegister here happened to work, but
the encoded dwarf number is definitely not an MCRegister.
[libc++][pstl] Add missing #pragma GCC system_header to libdispatch.h (#209579)
This adds `#pragma GCC system_header` to libdispatch.h, as removing the
`[system]` attributes in the modulemap surfaced this gap.
[CodeGen] Split determineCalleeSaves into smaller functions. (#203981)
The function `getMustPreserveRegisters` - returns the list of registers
that must be preserved by the function.
The function `determineUncondPrologCalleeSaves` - determines which of
the registers reported by `getMustPreserveRegisters` must be saved in
prolog and reloaded in epilog regardless of whether or not they were
modified by the function.
