LLVM/project 0092cd8 — llvm/lib/Transforms/Utils Local.cpp, llvm/test/Transforms/GVN duplicate-select-profile.ll

[Transforms] Preserve select profiles in combineMetadata (#233487)

getMergedProfMetadata will return nullptr in circumstances where we can
otherwise preserve the profile. Add a GVN regression test for where this
showed up.

Found from a bootstrapping LLVM build with `-mllvm
-enable-profcheck-in-pipeline`.
DeltaFile
+25-0llvm/test/Transforms/GVN/duplicate-select-profile.ll
+7-2llvm/lib/Transforms/Utils/Local.cpp
+32-22 files

LLVM/project e0a5972 — llvm/lib/CodeGen/AsmPrinter DwarfUnit.h DwarfUnit.cpp, llvm/lib/IR LLVMContextImpl.h

Allow 128-bit bounds in DISubrangeType (#231928)

When adding DISubrangeType, I neglected to account for the case of
128-bit array bounds. While unusual, this is valid in Ada, and a type
like this will cause a crash in LLVM:

    type Big_Range is range 2**127 - 15 .. 2**127 - 1;
    type Big_Array is array (Big_Range) of Boolean;

This patch adds support for this situation to DISubrangeType. DISubrange
is not modified, as gnat-llvm does not need this.

Some extra work was needed in the DWARF writer. In particular,
DW_AT_lower_bound (et al) are in both the 'constant' and 'exprloc'
class, and so DW_FORM_block* will be interpreted as an expression -- one
of the many weirdnesses of DWARF.

To handle this, I've added support for emitting these attributes using
DW_FORM_data16.

    [4 lines not shown]
DeltaFile
+49-15llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+5-36llvm/lib/IR/LLVMContextImpl.h
+38-0llvm/test/DebugInfo/Generic/subrange_type_128.ll
+3-2llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
+1-1llvm/test/DebugInfo/Generic/subrange_type.ll
+96-545 files

LLVM/project 9605d92 — clang/include/clang/CIR/Dialect Passes.td, clang/lib/CIR/Dialect/Transforms GotoSolver.cpp

[CIR] Only scan globals and constants for block addresses in GotoSolver (#232870)

The pass walked every op in the module checking inherent attributes for
BlockAddrInfoAttr/BlockAddrDiffAttr. Block addresses only appear in
attributes carried by globals and cir.const values (process() collects
cir.block_address ops directly), so scan just those ops and fold the two
attribute walks into one. The scan assumes module scope, so the pass is
declared on ModuleOp like the other lowering passes.

Successor order now follows attribute order: constant labels precede
cir.block_address labels, and mixed attribute kinds in one initializer
follow initializer order instead of grouping by kind. This matches the
order the pass documents, program behavior is unchanged.

Saves most of the 0.3-3.0s GotoSolver time on the slowest self-host TUs
(e.g. 3.0s -> 0.14s on clang/lib/Sema/SemaExpr.cpp).
DeltaFile
+65-0clang/test/CIR/Transforms/goto_solver.cir
+29-21clang/lib/CIR/Dialect/Transforms/GotoSolver.cpp
+1-1clang/include/clang/CIR/Dialect/Passes.td
+95-223 files

LLVM/project ab32b85 — llvm/lib/Transforms/Vectorize SLPVectorizer.cpp, llvm/lib/Transforms/Vectorize/SLPVectorizer SLPMemoryUtils.h SLPMemoryUtils.cpp

[SLP][NFCI] Cache getPointersDiff results (#232083)

SLP recomputes the same pointer distances repeatedly while sorting and
classifying loads, which dominates compile time on large blocks.

Assisted-by: Claude
DeltaFile
+44-16llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
+27-10llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+31-4llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.h
+102-303 files

LLVM/project a3689ed — clang/test/CodeGen/AArch64 abi-classify-opencl-arg-types.cl abi-classify-arg-types.cpp, llvm/lib/ABI/Targets AArch64.cpp

[LLVMABI][AARCH64] Implement general aggregate classification (#230631)

This implements general aggregate type classification for arguments and
return values on AArch64 targets. Aggregates of at most 16 bytes are
passed or return directly in registers or on the stack. Larger
aggregates are passed or returned indirectly.

Assisted-by: Cursor / various models
DeltaFile
+316-0llvm/unittests/ABI/AArch64TargetInfoTest.cpp
+172-14clang/test/CodeGen/AArch64/abi-classify-arg-types.c
+104-4llvm/lib/ABI/Targets/AArch64.cpp
+68-12clang/test/CodeGen/AArch64/abi-classify-return-types.c
+68-8clang/test/CodeGen/AArch64/abi-classify-arg-types.cpp
+49-0clang/test/CodeGen/AArch64/abi-classify-opencl-arg-types.cl
+777-389 files not shown
+822-6515 files

LLVM/project 5999876 — llvm/lib/CodeGen RegisterCoalescer.cpp, llvm/test/CodeGen/AMDGPU register-coalescer-early-clobber-reserved-physreg.mir

[CodeGen] Fix register coalescing early-clobber defs into reserved physregs (#233450)

Problem arises due to `joinReservedPhysRegs` creating a new dead def
`getRegSlot()` without checking if the vreg definition operand was an
early-clobber.

After adding the `isEarlyClobber` check, `getNextNonNullIndex` preserves
the early-clobber index slot kind, so every step of the loop visit the
next instruction at its early-clobber slot. With that the loop get past
the COPY instruction and falsely rejected the join. So to fix this a
`MachineInstruction` iterator is used, rather than checking per slot.

Fixes : https://github.com/llvm/llvm-project/issues/229778
DeltaFile
+28-0llvm/test/CodeGen/AMDGPU/register-coalescer-early-clobber-reserved-physreg.mir
+10-7llvm/lib/CodeGen/RegisterCoalescer.cpp
+38-72 files

LLVM/project 1d6f5b0 — clang/include/clang/CIR/Dialect/IR CIRDialect.h CIRDialect.td, clang/lib/CIR/Dialect/IR CIRTypes.cpp CIRDialect.cpp

[CIR] Memoize FuncType purity checks in the CIR dialect (#232863)

FuncType::verify walks every type in the signature to prove it only
contains CIR types, and it runs on every FuncType construction in
asserts-enabled builds. Signatures share the same record types over and
over, so the same graphs were re-walked thousands of times per
translation unit (15% of CXXABILowering).

Memoize "purity" per type in the CIR dialect object: the dialect gives
the cache exactly the context lifetime, and a mutex guards the map
(computing outside the lock is safe since two threads store the same
value). Records gain members when completed, so a 'pure' answer is only
cached when the walk saw no incomplete record; 'impure' answers are
always stable.

CXXABILowering on clang/lib/Sema/SemaExpr.cpp (selfhosting) goes from
6.3s to 3.0s and `-emit-cir` from 49.4s to 29.3s (asserts-enabled
build); output is unchanged.
DeltaFile
+27-0clang/lib/CIR/Dialect/IR/CIRDialect.cpp
+10-0clang/test/CIR/IR/invalid-func.cir
+2-7clang/lib/CIR/Dialect/IR/CIRTypes.cpp
+8-0clang/include/clang/CIR/Dialect/IR/CIRDialect.td
+2-0clang/include/clang/CIR/Dialect/IR/CIRDialect.h
+49-75 files

LLVM/project c59e95e — clang/include/clang/Basic DiagnosticFrontendKinds.td, clang/lib/Frontend CompilerInvocation.cpp

Revert "[HLSL] Use icmp ne instead of trunc on boolean load (#221105)"

This reverts commit f9897a670796e4e4bfc9d987d3480ead10351814.
DeltaFile
+30-15clang/test/CodeGenHLSL/builtins/BoolSwizzles.hlsl
+0-19clang/test/CodeGenHLSL/bool-vector-load.hlsl
+8-7clang/test/CodeGenHLSL/strict-bool.hlsl
+0-10clang/lib/Frontend/CompilerInvocation.cpp
+0-3clang/test/Driver/HLSL/load-bool-from-mem.hlsl
+0-3clang/include/clang/Basic/DiagnosticFrontendKinds.td
+38-571 files not shown
+38-587 files

LLVM/project 0c265f8 — flang/include/flang/Optimizer/Transforms Passes.td, flang/lib/Optimizer/Transforms/CUDA CUFAllocDelay.cpp

[flang][cuda] Keep delayed descriptor allocs out of CFG loops (#232992)

CUFAllocDelay places a descriptor's cuf.alloc, its initial store and its
fir.declare at the nearest common dominator of all their uses. When a DO
loop lowers to branches, for example because it contains a RETURN, and
the descriptor is used both inside the loop and after it, that block is
the loop header. The group then runs on every trip, including the exit
trip, and the code after the loop reads a fresh, empty descriptor:

```fortran
do jj = 1, 1
   if (.false.) return
   allocate(clvars(1))
end do
allocate(cvars(1))
cvars(:) = clvars(:)   ! Assign: mismatching element counts (to 1, from 0)
```

After computing the common dominator, climb the dominator tree while the

    [8 lines not shown]
DeltaFile
+231-0flang/test/Transforms/CUF/cuf-alloc-delay.fir
+30-4flang/lib/Optimizer/Transforms/CUDA/CUFAllocDelay.cpp
+2-1flang/include/flang/Optimizer/Transforms/Passes.td
+263-53 files

LLVM/project a83ae25 — libc/src/unistd execvp.h, libc/src/unistd/linux CMakeLists.txt execvp.cpp

[libc] implement execvp (#232008)

Slightly more complex than a normal syscall wrapper. This also needs to
search the PATH.

Described by POSIX:
https://pubs.opengroup.org/onlinepubs/9799919799/functions/exec.html

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+136-0libc/test/integration/src/unistd/execvp_test.cpp
+105-0libc/src/unistd/linux/execvp.cpp
+25-0libc/src/unistd/execvp.h
+24-0libc/test/integration/src/unistd/CMakeLists.txt
+23-0libc/test/integration/src/unistd/testdata/execvp_test_normal_exit.cpp
+22-0libc/src/unistd/linux/CMakeLists.txt
+335-06 files not shown
+372-012 files

LLVM/project ad409f3 — llvm/lib/Target/PowerPC/AsmParser PPCAsmParser.cpp, llvm/test/MC/AsmParser ppc-memop-from-set.s ppc-memop-from-set-diag.s

[PowerPC] Accept .set directive in mem operand (#229992)

It is common practice to give register numbers
symbolic names using .set directives. Parsing
memory operands should accept such identifiers
just like other operands do. This patch just
adds that handling so asm such as:
.set SP,1
std 3, -8(SP)
is handled correctly.

Fixes: https://github.com/llvm/llvm-project/issues/41472
DeltaFile
+10-0llvm/test/MC/AsmParser/ppc-memop-from-set-diag.s
+8-1llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+6-0llvm/test/MC/AsmParser/ppc-memop-from-set.s
+1-1llvm/test/MC/PowerPC/ppc32-tls.s
+25-24 files

LLVM/project a1d78ee — mlir/test/Integration/Dialect/Linalg/CPU/ArmSME lit.local.cfg, mlir/test/Integration/Dialect/Vector/CPU/ArmSME lit.local.cfg

[mlir][ArmSME] Mark integration tests unsupported under ASan on Darwin (#233445)

In an ASan build on macOS arm64, the ArmSME integration tests fail with:

```
  Assertion failed: (isInt<28>(Addend) && "Branch target is out of range.")
  (RuntimeDyldMachOAArch64.h, encodeAddend)
```

What happens:
- `mlir-runner` JIT-compiles the program to machine code in memory
- That code calls the SME ABI routines (e.g., `__arm_tpidr2_save`),
which live in `libmlir_arm_sme_abi_stubs`
- On AArch64 a direct branch (bl) can only reach about +/-128 MB from
where it is, see
[here](https://support.arm.com/documentation/dui0801/l/A64-General-Instructions/BL--A64-?lang=en)
- The AArch64 backend emits these calls as direct branches and ignores
the code model, so a large code model in the JIT does not help
- Under ASan the library can be mapped farther than that, the offset

    [9 lines not shown]
DeltaFile
+7-0mlir/test/Integration/Dialect/Vector/CPU/ArmSME/lit.local.cfg
+7-0mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/lit.local.cfg
+14-02 files

LLVM/project fd29cd9 — clang/lib/Headers cpuid.h

[clang][X86] fix bit_PKU (#232394)

Should be `1 << 3`.

See AMD64 APM Vol. 3. Section E.3.6 Function 7h—Structured Extended
Feature Identifiers.

Link: https://docs.amd.com/v/u/en-US/24594_3.38_APM_Vol3_PUB
DeltaFile
+1-1clang/lib/Headers/cpuid.h
+1-11 files

LLVM/project 934c5b4 — llvm/lib/Transforms/Scalar IndVarSimplify.cpp, llvm/test/Transforms/IndVarSimplify floating-point-iv.ll

[IndVarSimplify] Ensure fp to int32 conversion stays in bound (#230179)

IndVarSimplify converting floating-point induction variables into integer ones, some cases Exit value of the loop overflows and gives wrong result.
DeltaFile
+49-59llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
+94-0llvm/test/Transforms/IndVarSimplify/floating-point-iv.ll
+143-592 files

LLVM/project e5cd5b8 — llvm/lib/Transforms/Scalar InferAddressSpaces.cpp, llvm/test/Transforms/InferAddressSpaces/NVPTX clone_constexpr.ll

[InferAddressSpaces] Do not rewrite index operands of a constant GEP (#229491)

InferAddressSpaces rewrites flat (generic) pointers into a specific
address space once it can infer one. For constant expressions it does
this in cloneConstantExprWithNewAddressSpace(), which clones the
expression with the pointer operand moved into the inferred address
space.

For a constant getelementptr, that function used to recurse into every
operand, including the indices. Only operand 0, the base pointer, has to
live in the inferred address space. An index is an integer, and it can
be built from a pointer in a different address space, for example
ptrtoint (ptr addrspacecast (ptr addrspace(1) @g to ptr) to i64).
Rewriting it for the base's address space is wrong. In an assertions
build it hits the AddrSpaceCast assert, which expects the cast's source
to already be in the inferred address space:

assert(CE->getOperand(0)->getType()->getPointerAddressSpace() ==
NewAddrSpace)

    [11 lines not shown]
DeltaFile
+23-38llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
+24-1llvm/test/Transforms/InferAddressSpaces/NVPTX/clone_constexpr.ll
+47-392 files

LLVM/project cb6ac59 — llvm/lib/Transforms/Utils FunctionComparator.cpp, llvm/test/Transforms/MergeFunc atomic-align.ll

[MergeFunctions] Compare alignment of cmpxchg and atomicrmw (#233444)

FunctionComparator compared the alignment of loads and stores but not of
cmpxchg and atomicrmw, so MergeFunctions merged functions whose atomics only
differed in it. The alignment decides whether an atomic is emitted inline or
as a libatomic call.
DeltaFile
+45-0llvm/test/Transforms/MergeFunc/atomic-align.ll
+6-0llvm/lib/Transforms/Utils/FunctionComparator.cpp
+51-02 files

LLVM/project dc29460 — llvm/test/CodeGen/AArch64 fsh.ll vec-combine-compare-to-bitmask.ll, llvm/test/CodeGen/AArch64/GlobalISel combine-simplify-demanded-bits-trunc-xor-select.mir

feat(gisel): mirror trunc/xor/select demanded bits

Mirror SelectionDAG demand propagation, known-bits folding, truncation
of logical shifts, and XOR narrowing and constant simplifications.
Respect shared producers, legality and target profitability, including
AArch64 XOR/shift commuting. Preserve integer LLTs when narrowing.
DeltaFile
+1,327-1,103llvm/test/CodeGen/AArch64/neon-dotreduce.ll
+526-520llvm/test/CodeGen/AArch64/overflow-vec.ll
+388-390llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+744-0llvm/test/CodeGen/AArch64/GlobalISel/combine-simplify-demanded-bits-trunc-xor-select.mir
+201-222llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
+159-172llvm/test/CodeGen/AArch64/fsh.ll
+3,345-2,40739 files not shown
+4,140-3,03145 files

LLVM/project 1942513 — llvm/include/llvm/Transforms/IPO LowerTypeTests.h, llvm/lib/Transforms/IPO LowerTypeTests.cpp FatLTOCleanup.cpp

[LLVM][LowerTypeTests] Drop llvm.type.checked.load in drop-type-tests<all> (#232865)

drop-type-tests<all> dropped `llvm.type.test` but left
`llvm.type.checked.load[.relative]` behind, which the backend cannot
select. Handle them there too via `FatLTOCleanup`'s cleanup helper, now
shared. All mode only: in `Assume` mode a checked load may feed a CFI
trap check that must keep trapping.
DeltaFile
+89-0llvm/test/Transforms/LowerTypeTests/drop-type-checked-load.ll
+8-79llvm/lib/Transforms/IPO/FatLTOCleanup.cpp
+55-1llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+32-0llvm/test/Transforms/FatLTOCleanup/remove-type-checked-load.ll
+27-0llvm/test/Transforms/LowerTypeTests/drop-type-checked-load-no-type-test.ll
+6-0llvm/include/llvm/Transforms/IPO/LowerTypeTests.h
+217-801 files not shown
+219-817 files

LLVM/project 413e320 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll

[AMDGPU][NFC] Add d16 integer coverage for raw.ptr.buffer.load.format (#231300)

raw.ptr.buffer.load.format didn't have test coverage for the d16
paths, while other related intrinsics (like the non-`.ptr` versions)
did. This commit fixes the issue.

AI disclosure: Claude wrote these tests

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>

---------

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+87-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll
+87-21 files

LLVM/project e0bb0ab — llvm/include/llvm/IR IntrinsicsAMDGPU.td, llvm/test/CodeGen/AMDGPU llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll

[AMDGPU] Let llvm.amdgcn.raw.ptr.buffer.load.format also return any legal type (#231308)

While llvm.amdgcn.raw.buffer.load.format can handle several float and
integer (and vectors of those) types, and so
can llvm.amdgcn.struct.ptr.buffer.load.format,
llvm.amdgcn.raw.ptr.buffer.format was restricted to floats for some
reason, probably somebody forgetting to loosen it.

This commit fixes the issue so integer-format typed loads can migrate
off of the non-pointer intrinsic.

AI disclosure: Claude noticed it when I asked it draft up a stronger
deprecation for the non-ptr intrinsics, and I wrote the commit message.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>

---------

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+89-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll
+1-1llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+90-12 files

LLVM/project 69ad8f2 — llvm/test/CodeGen/AMDGPU llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll

[AMDGPU][NFC] Use ptr ops in ptr.buffer.atomic.fadd_rtn_errors.ll (#231298)

llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll had tests that were
using the deprecated `<4 x i32>` intrinsics. This commit fixes the
issue.

AI disclosure: Claude found this and made the change, I wrote this
message and reviewed.

Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+6-6llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
+6-61 files

LLVM/project a715dbc — mlir/test/Integration/Dialect/Linalg/CPU vectorize-insert-slice-rank-reducing.mlir

[mlir][linalg] Fix memory leak in `vectorize-insert-slice-rank-reducing` test (#233435)

The e2e test added in #226490 bufferizes a `tensor.empty` with
`-one-shot-bufferize`, which allocates the buffer but never frees it.
The LeakSanitizer reports the leak in builds with ASAN, see
[here](https://github.com/llvm/llvm-project/pull/226490#issuecomment-6267203174).

With this PR, the lowered IR now contains the `free` instruction.

**Note**: I could not check the LeakSanitizer report directly, as LSan
is not supported on macOS arm64 :(

Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
DeltaFile
+2-1mlir/test/Integration/Dialect/Linalg/CPU/vectorize-insert-slice-rank-reducing.mlir
+2-11 files

LLVM/project bd9c0d5 — llvm/lib/Target/SystemZ/MCTargetDesc SystemZHLASMAsmStreamer.cpp, llvm/test/CodeGen/SystemZ zos-ada-relocations.ll

[SystemZ][z/OS] Escape apostrophes and ampersands in HLASM ALIAS (#233067)

HLASM wants every apostrophe and ampersand inside a character
constant doubled (Language Reference SC26-4940-09, p.131), but the
streamer printed ALIAS C'...' with the external name as is. So a name
with an apostrophe in it, like one from an asm label, ended the string
early and broke the assembly. This adds a small helper that does the
doubling and uses it in all three places that emit ALIAS.
DeltaFile
+13-3llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+8-0llvm/test/CodeGen/SystemZ/zos-ada-relocations.ll
+21-32 files

LLVM/project 9e0927d — libunwind/src UnwindCursor.hpp, libunwind/test signal_frame.pass.cpp

[libunwind] Clear the signal frame state after compact unwind steps (#232823)

`_isSignalFrame` was only updated by DWARF steps. After stepping out of a
signal frame (always DWARF, since compact unwind can't encode them; see
#186458), compact steps left it set, so later return addresses were
treated as exact IPs. Besides misreporting `unw_is_signal_frame`, this
looks up the wrong function's unwind info when a return address is the
start of the next function (e.g. if there was a noreturn call at the end
of a function). Clear the state on compact steps.

Assisted-by: Claude Opus 5.5
DeltaFile
+11-3libunwind/test/signal_frame.pass.cpp
+2-0libunwind/src/UnwindCursor.hpp
+13-32 files

LLVM/project e0a93cc — llvm/include/llvm/CodeGen TargetLowering.h, llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp TargetLowering.cpp

[SelectionDAG] Add extension attributes in more places. (#232128)

- ubsantrap argument extension.
- atomic memset value argument extension.
- atomic memcopy/memmove/memset Size args passed as size_t.

Co-authored with IBM Bob.
DeltaFile
+100-0llvm/test/CodeGen/SystemZ/libcall-argext-atomic-mem-size.ll
+14-11llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+15-4llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+17-0llvm/test/CodeGen/SystemZ/libcall-argext-ubsantrap.ll
+11-5llvm/include/llvm/CodeGen/TargetLowering.h
+15-0llvm/test/CodeGen/SystemZ/libcall-argext-atomic-memset-value.ll
+172-203 files not shown
+178-259 files

LLVM/project 1b81c92 — flang/lib/Semantics openmp-utils.cpp, flang/test/Lower/OpenMP metadirective-user.f90

[flang][OpenMP] Don't treat different runtime conditions as subsets

When two METADIRECTIVE candidates have the same score and one selector is
a strict subset of the other, the superset wins. Flang ranks every
runtime condition with the same property, so isStrictSubset saw
different conditions as the same:

  !$omp metadirective &
  !$omp& when(user={condition(a)}, &
  !$omp&      implementation={vendor(score(4): llvm)}: taskyield) &
  !$omp& when(user={condition(b)}, device={kind(host)}, &
  !$omp&      implementation={vendor(score(3): llvm)}: taskwait)

Both candidates score 5, and `b` was tested first, so TASKWAIT ran when
both conditions were true. Neither selector is a subset of the other, so
clause order should decide.

This patch adds a UserCondition key to VariantMatchInfo, and
isStrictSubset requires equal keys when the first selector has a

    [9 lines not shown]
DeltaFile
+77-0flang/test/Lower/OpenMP/metadirective-user.f90
+37-0llvm/unittests/Frontend/OpenMPContextTest.cpp
+13-3flang/lib/Semantics/openmp-utils.cpp
+7-0llvm/lib/Frontend/OpenMP/OMPContext.cpp
+4-0llvm/include/llvm/Frontend/OpenMP/OMPContext.h
+138-35 files

LLVM/project 0873434 — clang/lib/CodeGen CGHLSLRuntime.cpp

clang format
DeltaFile
+7-5clang/lib/CodeGen/CGHLSLRuntime.cpp
+7-51 files

LLVM/project 47b8b97 — clang/include/clang/Basic AttrDocs.td, clang/lib/CodeGen CGHLSLRuntime.h CGHLSLRuntime.cpp

[CGHLSL][SPIRV] Add emission of interpolation modifiers
DeltaFile
+139-102clang/lib/CodeGen/CGHLSLRuntime.cpp
+107-0clang/test/CodeGenHLSL/semantics/interpolation-spirv.hlsl
+29-26clang/lib/CodeGen/CGHLSLRuntime.h
+33-0clang/test/CodeGenHLSL/semantics/interpolation-aggregate.hlsl
+26-0llvm/test/CodeGen/SPIRV/capability-SampleRateShading.ll
+8-3clang/include/clang/Basic/AttrDocs.td
+342-1312 files not shown
+350-1348 files

LLVM/project 0dd0f36 — clang/test/Driver amdgpu-xnack-sramecc-flags.c

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LLVM/project d4599c5 — llvm/lib/LTO LTO.cpp, llvm/test/ThinLTO/X86 macho-guid-collision.ll

[ThinLTO] Record prevailing GUIDs by linker symbol name (#226911)

`LTO::addThinLTO` updates `GlobalResolutions` using the IR name from a
summary, but that map is keyed by mangled linker symbol names. On
Mach-O, the IR name `_foo` can therefore match the resolution for `foo`
(whose linker name is `_foo`). This assigns `_foo`'s GUID to `foo` and
can incorrectly internalize `foo` even when another module references
it, producing an undefined-symbol error.

Move the GUID assignment into the symbol loop, where `Sym.getName()`
identifies the correct resolution and the GUID has already been obtained
using `Sym.getIRName()`. Preserve the prevailing-definition check and
the existing fallback for bitcode without a GUID table.

This fixes a regression introduced by
39dcb0ff91b312bb269334168d5e32be78b60417 (#201849). It surfaced when
linking mimalloc 3.5.3 into a PGO/ThinLTO build of LLVM on macOS. The
standalone reproducer below needs only Clang, LLD, and the macOS SDK.


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