LLVM/project 9b1c677flang/test/Parser/OpenMP linear-clause-v45.f90

Add test with step being an array
DeltaFile
+47-20flang/test/Parser/OpenMP/linear-clause-v45.f90
+47-201 files

LLVM/project 3e1921cllvm/lib/Target/RISCV RISCVISelLowering.cpp

drop warning message that is now printed by subtarget

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+2-8llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-81 files

LLVM/project 4ef2e75clang/test/CodeGen openacc-noop-decl.c, clang/test/Modules codegen-opt.test

[FileCheck] Avoid matching IR keywords in source filenames (#213809)

Anchor checks for declare, define, and comdat to the start of lines or another fixture so
paths in module headers cannot satisfy or invalidate them.

Tested with make check.

Assisted by AI.
DeltaFile
+2-2llvm/test/tools/llvm-reduce/remove-dso-local.ll
+1-1llvm/test/tools/llvm-reduce/remove-module-data.ll
+1-1llvm/test/tools/llvm-reduce/remove-function-attributes.ll
+1-0clang/test/Modules/codegen-opt.test
+1-0clang/test/CodeGen/openacc-noop-decl.c
+6-45 files

LLVM/project 80e60aallvm/test/CodeGen/AMDGPU buffer-fat-pointer-atomicrmw-fmin.ll buffer-fat-pointer-atomicrmw-fadd.ll

fix review comments

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+3,809-3,814llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+3,809-3,814llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+3,465-3,511llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+3,465-3,511llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+3,299-3,240llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+2,594-2,524llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+20,441-20,4142,671 files not shown
+160,880-93,5852,677 files

LLVM/project ced31fdllvm/test/MC/RISCV rv32i-invalid.s

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1-arichardson
DeltaFile
+15-1llvm/test/MC/RISCV/rv32i-invalid.s
+15-11 files

LLVM/project 2e9d9cdllvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.h

remove verbose comment
DeltaFile
+1-4llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+1-41 files

LLVM/project 7832329llvm/test/CodeGen/AMDGPU llvm.amdgcn.rcp.bf16.ll

Add missing test
DeltaFile
+68-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
+68-01 files

LLVM/project cd459f2llvm/lib/Target/SPIRV SPIRVLegalizerInfo.cpp, llvm/test/CodeGen/SPIRV/instructions phi-large-vector-shader.ll

[SPIRV] Split wide shader PHIs before applying explicit supported types (#213806)

fixes #213802

Apply the maximum-vector-size rule before the explicit PHI legality
rules for type. This way if we see a size 16 vector we split it
beforehand.

In more precise words this preserves existing legality rules while
ensuring shader PHIs wider than four lanes are split first.

Assisted by Copilot (GPT 5.6 Sol)
DeltaFile
+78-16llvm/test/CodeGen/SPIRV/instructions/phi-large-vector-shader.ll
+10-10llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+88-262 files

LLVM/project aa76963llvm/lib/Target/X86 X86ISelLowering.cpp

[X86] LowerPARITY - use countMaxActiveBits to determine if representable as uint8_t. NFC. (#214056)

Much cleaner than using the MaskedValueIsZero check.

Fix i64 -> xor(i32,i32) parity stage comment as well.
DeltaFile
+2-3llvm/lib/Target/X86/X86ISelLowering.cpp
+2-31 files

LLVM/project 2178db6llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 avx512-masked-op-fusion.ll

[X86] Handle multi-use setcc in commuteSelect (#213645)

When a setcc condition is shared between multiple vselects,
commuteSelect previously bailed out due to the m_OneUse constraint.
Extend it to check all users of the setcc and, if they all benefit from
commuting, invert the condition once with ReplaceAllUsesOfValueWith and
swap all vselect operands.

This fixes a write-mask fusion regression where masked min/max
reductions produced unfused vminps + vmovaps {%k} instead of a single
write-masked vminps {%k}.
DeltaFile
+29-6llvm/lib/Target/X86/X86ISelLowering.cpp
+9-13llvm/test/CodeGen/X86/avx512-masked-op-fusion.ll
+38-192 files

LLVM/project 46b8eb8clang/docs ConstantInterpreter.rst

[NFC][Clang][Docs] Fix minor typos in Constant Interpreter doc. (#211608)

First: Typo is obvious. 
Second: In the example, the a.y field is missing and field a.b.y is
required.
DeltaFile
+2-2clang/docs/ConstantInterpreter.rst
+2-21 files

LLVM/project 9d069ballvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Update PredicatedMaxBTC heuristic
DeltaFile
+5-4llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+5-41 files

LLVM/project 03f86c6clang/lib/Driver/ToolChains MSVC.cpp, lldb/include/lldb/Host/windows windows.h

[Support][Driver][LLDB] Guard WIN32_LEAN_AND_MEAN definitions with #ifndef (#213045)

Several Windows headers/TUs unconditionally `#define
WIN32_LEAN_AND_MEAN`. When a build predefines the macro on the compiler
command line (e.g. a toolchain that passes -DWIN32_LEAN_AND_MEAN, which
clang treats as `#define WIN32_LEAN_AND_MEAN 1`), the differing token
lists trigger -Wmacro-redefined, which becomes a hard error under
-Werror.

Guard the definitions with #ifndef, matching the adjacent NOMINMAX
handling and the existing pattern in
llvm/lib/Support/rpmalloc/rpmalloc.c. The macro is only a presence flag,
so keeping an externally-provided definition is correct.

Sites guarded:
  llvm/include/llvm/Support/Windows/WindowsSupport.h
  llvm/lib/WindowsDriver/MSVCPaths.cpp
  clang/lib/Driver/ToolChains/MSVC.cpp
  lldb/include/lldb/Host/windows/windows.h

    [13 lines not shown]
DeltaFile
+8-6clang/lib/Driver/ToolChains/MSVC.cpp
+2-0llvm/lib/WindowsDriver/MSVCPaths.cpp
+2-0llvm/include/llvm/Support/Windows/WindowsSupport.h
+2-0lldb/include/lldb/Host/windows/windows.h
+14-64 files

LLVM/project 81c182dflang/lib/Evaluate tools.cpp fold-integer.cpp, flang/lib/Semantics mod-file.cpp resolve-names.cpp

Did the following:
  - Updated intrinsic.md document
  - Simplified the code per recommendations
  - Fixed constant folding to be context aware and only report errors
    in constant expressions.  Otherwise they are left for runtime.
  - Corrected namelist declaration error.
  - Corrected enumeration type attributes.
  - Added/modified test cases are appropriate.
DeltaFile
+106-104flang/lib/Evaluate/fold-implementation.h
+30-34flang/lib/Evaluate/fold-integer.cpp
+22-10flang/test/Semantics/enumeration-type-intrinsics.f90
+23-8flang/lib/Semantics/resolve-names.cpp
+12-17flang/lib/Evaluate/tools.cpp
+19-4flang/lib/Semantics/mod-file.cpp
+212-17711 files not shown
+297-19217 files

LLVM/project c314303llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.permlane.ptr.ll llvm.amdgcn.permlane.ll

[AMDGPU][GlobalISel] RegBankLegalize rules for amdgcn_permlane16
DeltaFile
+3,980-3,687llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
+629-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ptr.ll
+8-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+4,617-3,6883 files

LLVM/project f20b64flldb/test/API/functionalities/process_save_core_minidump/size_mismatch TestProcessSaveCoreMinidumpSizeMismatch.py

[lldb] Disable TestProcessSaveCoreMinidumpSizeMismatch on Windows hosts (#214044)

The buildbot
[lldb-remote-linux-win](https://lab.llvm.org/buildbot/#/builders/197) is
red after #212861. #212861 cannot be reverted automatically now because of
#212641. So disable TestProcessSaveCoreMinidumpSizeMismatch on Windows
hosts to make the buildbot green again.
DeltaFile
+1-0lldb/test/API/functionalities/process_save_core_minidump/size_mismatch/TestProcessSaveCoreMinidumpSizeMismatch.py
+1-01 files

LLVM/project d52e988llvm/test/CodeGen/AMDGPU schedule-amdgpu-tracker-physreg-crash.ll

[NFC][AMDGPU] Fix exit code mismatch with EXPENSIVE_CHECK in schedule… (#214027)

…-amdgpu-tracker-physreg-crash.ll

Observed in
https://ci.swift.org/job/llvm.org/job/clang-stage1-RA-expensive/job/main/1155
with LLVM_ENABLE_EXPENSIVE_CHECKS enabled,
`CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll` fails due to
MachineVerifier running, causing an exit 1.

Modified to always run the `-verify-machineinstrs`.

rdar://184010766
DeltaFile
+1-1llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll
+1-11 files

LLVM/project 83fb72allvm/include/llvm/DWP DWP.h, llvm/lib/DWP DWP.cpp

[DWP] Eagerly clear buffers after writing (#213345)

Lowers peak memory usage on a llvm-dwp invocation from 12.37GB ->
11.19GB.

This actually now beats out GNU dwp (11.35GB) at least when the output
file is in tmpfs.
DeltaFile
+10-7llvm/lib/DWP/DWP.cpp
+8-1llvm/include/llvm/DWP/DWP.h
+18-82 files

LLVM/project 44c6aedflang/lib/Lower/OpenMP Decomposer.cpp

[flang][OpenMP] Diagnose failed construct decomposition instead of falling through (#214012)

`buildConstructQueue` asserts that decomposition produced output:

```cpp
ConstructDecomposition decompose(modOp, semaCtx, eval, compound, clauses);
assert(!decompose.output.empty() && "Construct decomposition failed");
```

Release builds have no check, so the empty queue falls through to the
loop below and out to the
caller. That is undefined behaviour, and it is reachable — semantics
does not catch every
directive/clause combination that cannot be decomposed. The result is an
intermittent segfault
rather than a diagnostic.

#211430 is one way in: `allocate` is an OpenMP 5.0 clause, but most
directives declare it in

    [45 lines not shown]
DeltaFile
+27-1flang/lib/Lower/OpenMP/Decomposer.cpp
+27-11 files

LLVM/project 8343c53utils/bazel/llvm-project-overlay/clang BUILD.bazel

[Bazel] Fixes 04722a4 (#214049)

This fixes 04722a4a32e6fec1897cc3cb5a54809fcd8c9cae (#211409).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=04722a4a32e6fec1897cc3cb5a54809fcd8c9cae

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/clang/BUILD.bazel
+1-01 files

LLVM/project c740c54llvm/lib/Support/Unix Signals.inc

[SystemZ][z/OS] Add guard for SI_USER  (#213101)

SI_USER is not defined on z/OS and is causing the following build
failure. `error: use of undeclared identifier 'SI_USER'` 
This patch adds a guard to check whether SI_USER is defined
before using it.
DeltaFile
+4-1llvm/lib/Support/Unix/Signals.inc
+4-11 files

LLVM/project 0d1b546llvm/test/TableGen RegClassByHwMode.td, llvm/utils/TableGen AsmMatcherEmitter.cpp

[TableGen][AsmMatcher] Resolve RegClassByHwMode kinds for all operands

validateOperandClass() only remapped a RegClassByHwMode operand kind
when the actual parsed operand was a register. When the operand was
something else entirely (e.g. a bare immediate where a register was
expected), this fell through to the generic "Kind <= MCK_LAST_REGISTER"
diagnostic check, so we end up with a generic Match_InvalidOperand.

No test changes here, but this is needed to avoid diagnostic regressions
with the RVY load/store support (PR #177073).

Pull Request: https://github.com/llvm/llvm-project/pull/213479
DeltaFile
+5-1llvm/utils/TableGen/AsmMatcherEmitter.cpp
+1-1llvm/test/TableGen/RegClassByHwMode.td
+6-22 files

LLVM/project dee70a0llvm/lib/Target/PowerPC/AsmParser PPCAsmParser.cpp, llvm/lib/Target/SystemZ/AsmParser SystemZAsmParser.cpp

[TableGen] Generate `getRegClassFromMatchKind()` for AsmMatchers

This helper can be useful in validateTargetOperandClass to get the
MCRegisterClass for the MCK_* enum.
Migrate the RVY logic to use this new generated function. Checking all
register classes instead of just the RVY ones will marginally slow down
validateTargetOperandClass, but since this is already a slow path it
should not matter.

If multiple RegisterOperands share a ParserMatchClass but map to different
RegisterClasses, omit them from the generated getRegClassFromMatchKind
mapping function. I originally tried to emit an error here, but it turns
out there are many targets that rely on sharing the ParserMatchClass with
different (but similar) RegisterClasses so ignoring them is safer.

Reviewed By: lenary

Pull Request: https://github.com/llvm/llvm-project/pull/200453
DeltaFile
+170-0llvm/test/TableGen/getRegClassFromMatchKind.td
+80-0llvm/utils/TableGen/AsmMatcherEmitter.cpp
+1-0llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
+1-0llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+1-0llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+1-0llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+254-06 files not shown
+260-012 files

LLVM/project cddc107llvm/lib/Target/AMDGPU AMDGPULateCodeGenPrepare.cpp, llvm/test/CodeGen/AMDGPU preload-implicit-kernargs.ll indirect-call-known-callees.ll

[AMDGPU] Do not widen constant loads that may not be dereferenceable (#184790)
DeltaFile
+83-20llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
+17-18llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
+11-8llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
+6-10llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
+117-564 files

LLVM/project a43a053llvm/test/Transforms/LoopVectorize/VPlan vplan-based-stride-mv.ll

Update SCALABLE RUN-line/checks
DeltaFile
+56-31llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+56-311 files

LLVM/project 6428384llvm/test/Transforms/LoopVectorize/VPlan vplan-based-stride-mv.ll, llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs pre-process.ll pre-process.ll.expected

Merge branch 'stride-mv-vscale-test' into vplan-based-stride-mv-rt-guard
DeltaFile
+284-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
+12-6llvm/utils/update_analyze_test_checks.py
+1-13llvm/utils/update_test_checks.py
+14-0llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/pre-process.ll.expected
+13-0llvm/utils/UpdateTestChecks/common.py
+9-0llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/pre-process.ll
+333-192 files not shown
+340-268 files

LLVM/project b3ce07bllvm/include/llvm/Support PerThreadBumpPtrAllocator.h

[SystemZ][z/OS] use LLVM_THREAD_LOCAL instead of thread_local (#214039)

This patch is to fix the following error on z/OS

```
llvm/include/llvm/Support/PerThreadBumpPtrAllocator.h:75:12: error: thread-local storage is not supported for the current target
   75 |     static thread_local std::vector<AllocatorTy *> Cache;
      |            ^
```
DeltaFile
+1-1llvm/include/llvm/Support/PerThreadBumpPtrAllocator.h
+1-11 files

LLVM/project 30a38bcclang/docs InternalsManual.md InternalsManual.rst, clang/test/CIR/CodeGen pragma-fenv_access.c

Merge remote-tracking branch 'origin/main' into vplan-based-stride-mv-rt-guard
DeltaFile
+4,993-0llvm/test/CodeGen/RISCV/clmul.ll
+0-3,941clang/docs/InternalsManual.rst
+3,920-0clang/docs/InternalsManual.md
+1,716-0clang/test/CIR/CodeGen/pragma-fenv_access.c
+6-1,412libcxx/include/__locale
+673-482llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
+11,308-5,8351,402 files not shown
+46,954-25,3781,408 files

LLVM/project d0bd7c1llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.tanh.ll

[AMDGPU][GISel] Add RegBankLegalize rules for amdgcn_tanh

Enable the existing gfx1250 and gfx13 GlobalISel coverage now that tanh operands are assigned to VGPRs.

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+570-31llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+571-322 files

LLVM/project a967e37llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel legalize-fneg.mir legalize-fabs.mir

[AMDGPU][GlobalISel] Legalize BF16 fneg and fabs

Restore the BF16 semantic types omitted by the extended LLT migration and preserve packed vector legalization.

Co-authored-by: Cursor <cursoragent at cursor.com>
DeltaFile
+112-0llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
+112-0llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
+3-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+227-13 files