LLVM/project 6b281d1flang/test/Transforms/OpenACC acc-implicit-declare-type-descriptor-type_desc.F90 acc-implicit-declare-type-descriptor-alloca.F90

[flang][acc] Add tests for implicit `acc declare` of type descriptors (#203100)

Adds 4 tests to cover different cases which requires implicit `acc
declare` for type descriptors.
DeltaFile
+29-0flang/test/Transforms/OpenACC/acc-implicit-declare-type-descriptor-type_desc.F90
+27-0flang/test/Transforms/OpenACC/acc-implicit-declare-type-descriptor-alloca.F90
+26-0flang/test/Transforms/OpenACC/acc-implicit-declare-type-descriptor-embox.F90
+21-0flang/test/Transforms/OpenACC/acc-implicit-declare-type-descriptor-rebox.F90
+103-04 files

LLVM/project 7571b8bclang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp

[CIR] NFC: Address byval review feedback in CallConvLowering

Second-pass review cleanup on the byval/byref argument lowering in
CIRABIRewriteContext, no functional change.

updateArgAttrs now builds its attributes through an mlir::Builder, so the
arg-attr construction reads as getNamedAttr / getI64IntegerAttr /
getUnitAttr instead of spelling out StringAttr::get and the IntegerType
plumbing by hand; the Extend branch loses its empty-vs-nonempty special
case since the append path handles both.  The llvm.byval / llvm.byref
comment now says why the pointee type is carried explicitly: it is a
typed attribute and the type cannot be recovered from the opaque LLVM
pointer after lowering.

insertArgCoercion gains an early continue for the classifications that
need no entry-block fixup (Extend, Ignore, and Direct without coercion),
so the remaining if/else covers exactly the two cases that do work
(Direct-with-coercion and Indirect) with no silent do-nothing branch.


    [3 lines not shown]
DeltaFile
+37-36clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+37-361 files

LLVM/project 4221ca9mlir/test/Integration/Dialect/XeGPU/LANE xegpu_dpas_mx_prepacked_bf8.mlir xegpu_dpas_mx_prepacked_e2m1.mlir

[MLIR][XeGPU] Use updated dpas_mx op print format. (#202700)

Old assembly format causes parse error.
DeltaFile
+1-1mlir/test/Integration/Dialect/XeGPU/LANE/xegpu_dpas_mx_prepacked_bf8.mlir
+1-1mlir/test/Integration/Dialect/XeGPU/LANE/xegpu_dpas_mx_prepacked_e2m1.mlir
+2-22 files

LLVM/project 4a21c2allvm/lib/Target/DirectX DXContainerGlobals.cpp

[DirectX] Fix -Wunused-variable warning (#203107)
DeltaFile
+0-3llvm/lib/Target/DirectX/DXContainerGlobals.cpp
+0-31 files

LLVM/project 0e8fe79llvm/lib/Support GlobPattern.cpp

[NFC][Support] Define Prefix/SuffixMetacharacters constants (#202850)

Extract literal metacharacter strings used in GlobPattern into static
constexpr arrays to improve consistency and maintainability.

Assisted-by: Gemini
DeltaFile
+6-3llvm/lib/Support/GlobPattern.cpp
+6-31 files

LLVM/project a848df2llvm/include module.modulemap

[IR] Add BundleAttributes.def to modulemap as textual header (#203106)

Fixes stage 2 builds broken by 88bd366041fd539d2e8d75f2b2ae081940922f8e
DeltaFile
+1-0llvm/include/module.modulemap
+1-01 files

LLVM/project 1f668fallvm/docs LangRef.md

AI-generated review
DeltaFile
+45-72llvm/docs/LangRef.md
+45-721 files

LLVM/project 59eb0d2libc/shared/math isnanf128.h, libc/src/__support/math isnanf128.h

[libc][math] Add isnanf128 (#199206)

## Summary

- Add a fputil-based isnanf128 implementation and wire it into libc math
entrypoints, public math header generation, and shared math wrappers.

- Add smoke test coverage for float128 NaN classification and shared
math runtime/constexpr coverage.

Part of #195400

---------

Signed-off-by: Vedant Neve <vedantneve13 at gmail.com>
DeltaFile
+31-0libc/src/__support/math/isnanf128.h
+29-0libc/shared/math/isnanf128.h
+21-0libc/src/math/isnanf128.h
+17-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+16-0libc/src/math/generic/isnanf128.cpp
+13-0libc/test/src/math/smoke/isnanf128_test.cpp
+127-017 files not shown
+184-023 files

LLVM/project 5aab006llvm/test/CodeGen/AMDGPU mdt-preserving-crash.ll, llvm/test/CodeGen/PowerPC p10-spill-crun.ll subreg-postra.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+76-80llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
+95-37llvm/test/CodeGen/X86/2011-09-14-valcoalesce.ll
+52-57llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
+44-48llvm/test/CodeGen/PowerPC/subreg-postra.ll
+30-2llvm/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll
+13-17llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
+310-2414 files not shown
+342-25510 files

LLVM/project 4a9bf9bllvm/test/CodeGen/X86 2011-09-14-valcoalesce.ll 2009-11-17-UpdateTerminator.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+101-37llvm/test/CodeGen/X86/2011-09-14-valcoalesce.ll
+36-2llvm/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll
+137-392 files

LLVM/project 93ae6d9llvm/test/CodeGen/X86 2011-09-14-valcoalesce.ll 2009-11-17-UpdateTerminator.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+101-37llvm/test/CodeGen/X86/2011-09-14-valcoalesce.ll
+36-2llvm/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll
+137-392 files

LLVM/project a06dd7aclang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp

[CIR] NFC: Extract rewriteIndirectReturnCall helper

The sret call-site rewrite was a large block inside rewriteCallSite.
Move it into a dedicated rewriteIndirectReturnCall helper in the
anonymous namespace, leaving rewriteCallSite to dispatch to it when the
return is indirect.

Pure code motion: the Indirect-and-has-result guard stays at the call
site (the moved block dereferences the call result, so the guard cannot
fold into the helper), and the helper derives its MLIR context from the
call.  No behavior change.
DeltaFile
+93-80clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+93-801 files

LLVM/project e159feaclang/test/CodeGen/RISCV rvp-intrinsics.c, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-load-i8-stride-8.ll

rebase

Created using spr 1.3.7
DeltaFile
+8,699-3,233llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+0-6,200llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+4,380-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16-fake16.txt
+1,962-1,920llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+3,349-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+1,166-1,460llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+19,556-12,8131,272 files not shown
+64,585-31,6661,278 files

LLVM/project e49bd05clang/test/CodeGen/RISCV rvp-intrinsics.c, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-load-i8-stride-8.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+8,699-3,233llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+0-6,200llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+4,380-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16-fake16.txt
+1,962-1,920llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+3,349-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+1,166-1,460llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+19,556-12,8131,272 files not shown
+64,585-31,6661,278 files

LLVM/project 5aea8eeclang/test/CodeGen/RISCV rvp-intrinsics.c, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-load-i8-stride-8.ll

rebase

Created using spr 1.3.7
DeltaFile
+8,699-3,233llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+0-6,200llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+4,380-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16-fake16.txt
+1,962-1,920llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+3,349-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+1,166-1,460llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+19,556-12,8131,272 files not shown
+64,585-31,6661,278 files

LLVM/project ba72638clang/test/CodeGen/RISCV rvp-intrinsics.c, llvm/test/CodeGen/X86 vector-interleaved-store-i16-stride-7.ll vector-interleaved-load-i8-stride-8.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]
DeltaFile
+8,699-3,233llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+0-6,200llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+4,380-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16-fake16.txt
+1,962-1,920llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+3,349-0clang/test/CodeGen/RISCV/rvp-intrinsics.c
+1,166-1,460llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
+19,556-12,8131,272 files not shown
+64,585-31,6661,278 files

LLVM/project 90a1eebclang/include/clang/CIR LoweringHelpers.h, clang/lib/CIR/Lowering LoweringHelpers.cpp

[CIR] Lower pointer const_array globals without insertvalue chains (#198427)

`cir.global` initializers that are `const_array` of `global_view` (no
indices) or null pointers were lowered through an initializer region
full of `llvm.insertvalue` ops even though the elements are all
attribute-representable.  That forced the O(N²) MLIR-to-LLVM IR path
on large tables (SPEC CPU 2026 `gcc/insn-automata.cc`).

When `lowerConstArrayAttr` can build the whole initializer, emit the
global with one aggregate attribute instead.  String literals with
`trailing_zeros` are padded into `DenseElementsAttr` so C string tables
take the same bulk path.  Indexed `global_view`, `#cir.zero` arrays, and
other non-bulk cases still use the insertvalue path.

MLIR prerequisite
[#198424](https://github.com/llvm/llvm-project/pull/198424) is merged on
`main`; this branch is rebased and CIR-only.

---------

Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
DeltaFile
+141-10clang/lib/CIR/Lowering/LoweringHelpers.cpp
+40-22clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+55-0clang/test/CIR/Lowering/const-array-bulk-lowering-fallbacks.cir
+38-0clang/test/CIR/CodeGen/global-pointer-array-fast-lowering.cpp
+18-0clang/test/CIR/Lowering/const-array-of-pointers.cir
+2-1clang/include/clang/CIR/LoweringHelpers.h
+294-331 files not shown
+294-347 files

LLVM/project 8738174utils/bazel/llvm-project-overlay/flang/unittests BUILD.bazel

[Bazel] Fixes f5c08d6 (#203102)

This fixes f5c08d6d63bbb7e2c1f07fe980ad2b93029651a8.

Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
DeltaFile
+1-0utils/bazel/llvm-project-overlay/flang/unittests/BUILD.bazel
+1-01 files

LLVM/project 0382badclang/lib/CIR/Dialect/Transforms/TargetLowering CIRABIRewriteContext.cpp, clang/test/CIR/Transforms/abi-lowering indirect-return-sret.cir

[CIR] NFC: Address sret review feedback in CallConvLowering

Apply andykaylor's second-round feedback on the sret lowering.
All source changes are behavior-preserving:

- Use llvm::append_range when copying arg_attrs into the sret
  call's and the definition's attribute lists.
- Replace the manual pad loop in applySretSlotAttrs with an
  assert plus resize to the rewritten operand count.
- Rename the Ignore-drop loop's index variables so the outer
  one (argInfoIdx) indexes fc.argInfos and the inner one
  (blockIdx) is the real block-argument index, matching the
  convention insertArgCoercion already uses.
- Clarify the "hidden pointer" comments: the sret pointer is
  synthesized by the ABI and is not part of the source-level
  signature.
- Note why the llvm.sret attribute must carry the return type
  explicitly, since LLVM pointers are opaque once lowered.


    [6 lines not shown]
DeltaFile
+45-8clang/test/CIR/Transforms/abi-lowering/indirect-return-sret.cir
+25-19clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
+70-272 files

LLVM/project 83ff96dllvm/lib/Transforms/IPO Instrumentor.cpp, llvm/test/CodeGen/X86 atomic-load-store.ll

Merge branch 'main' into users/amara/fix-modulemap
DeltaFile
+996-0llvm/test/CodeGen/X86/atomic-load-store.ll
+280-0llvm/test/Instrumentation/Instrumentor/numeric.ll
+0-280llvm/test/Instrumentation/Instrumentor/operations.ll
+61-1llvm/lib/Transforms/IPO/Instrumentor.cpp
+23-21mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
+30-0llvm/test/Instrumentation/Instrumentor/numeric_config.json
+1,390-3024 files not shown
+1,410-34210 files

LLVM/project e7aff7bllvm/test/CodeGen/X86 atomic-load-store.ll

[X86] Add aligned atomic vector store tests wider than 128 bits (NFC) (#202537)

These >128-bit stores are expanded to __atomic_store libcalls regardless
of alignment, since x86 caps atomic ops at 128 bits.
DeltaFile
+996-0llvm/test/CodeGen/X86/atomic-load-store.ll
+996-01 files

LLVM/project 3584126mlir/tools/mlir-tblgen AttrOrTypeFormatGen.cpp

[MLIR][ODS] Do not emit code when printing empty lists in Type/Attr assembly printer (NFC) (#201174)

In TableGen's code generator, `DefFormat::genCommaSeparatedPrinter` can
emit code like
```
void FooType::print(::mlir::AsmPrinter &odsPrinter) const {
  ::mlir::Builder odsBuilder(getContext());
  odsPrinter << "<";
  {
    bool _firstPrinted = true;
  }
  odsPrinter << ">";
}
```

This results in unused variable warnings for `_firstPrinted` when
compiling the table-gen'd code:
```
warning: unused variable '_firstPrinted' [-Wunused-variable]

    [7 lines not shown]
DeltaFile
+23-21mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
+23-211 files

LLVM/project bf4da3dllvm/include module.modulemap

[IR] Add BundleAttributes.def to modulemap as textual header

Fixes stage 2 builds broken by 88bd366041fd539d2e8d75f2b2ae081940922f8e
DeltaFile
+1-0llvm/include/module.modulemap
+1-01 files

LLVM/project 6a05e9bllvm/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/test/CodeGen/X86 vector-interleaved-store-i64-stride-6.ll vector-interleaved-store-i16-stride-6.ll

[SelectionDAG] Fold extracts of subvector inserts

Fold extract_subvector(insert_subvector(...)) when the extraction is
outside the inserted subvector or the inserted subvector only amends
the extracted

In particular,
1. vA extract_subvector (vB insert_subvector(vB X, vC Y, C1), C2) =>
vA extract_subvector(X, C2) when [C2, C2 + A) intersect [C1, C1 + C)
is the empty set
2. ... => extract_subvector(Y, C2 - C1) if [C2, C2 + Y) is a subset of
[C1, C1 + C) - an existing simplification
3. ... => vA insert_subvector(vA extract_subvector(vB X, C2), vC Y, C1 - C2)
if [C1, C1 + C) is a subset of [C2, C2 + A) - that is, if you're only
updating the extracted sub-part.

Adds a regresssion tests for an infinite SelectionDAG cycle that is
fixed by a stack of commits that ends with this one.


    [3 lines not shown]
DeltaFile
+72-56llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
+44-48llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
+27-7llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+15-17llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
+4-8llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
+4-8llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
+166-1446 files

LLVM/project 47ca5e8llvm/include/llvm/Transforms/IPO Instrumentor.h, llvm/lib/Transforms/IPO Instrumentor.cpp

[Instrumentor] Add instruction flags to NumericIO (#200709)
DeltaFile
+280-0llvm/test/Instrumentation/Instrumentor/numeric.ll
+0-280llvm/test/Instrumentation/Instrumentor/operations.ll
+61-1llvm/lib/Transforms/IPO/Instrumentor.cpp
+30-0llvm/test/Instrumentation/Instrumentor/numeric_config.json
+0-28llvm/test/Instrumentation/Instrumentor/operations.json
+12-8llvm/include/llvm/Transforms/IPO/Instrumentor.h
+383-3172 files not shown
+391-3218 files

LLVM/project f5c08d6utils/bazel/llvm-project-overlay/flang BUILD.bazel, utils/bazel/llvm-project-overlay/flang/include/flang/Optimizer/Dialect BUILD.bazel

[bazel] Added targets for flang, flang-rt, and openmp (#202791)

This change adds the necessary targets for a fortran toolchain. `flang`
for the compiler itself, `flang-rt` for executable support, and `openmp`
for `!$omp` directives within fortran code.
DeltaFile
+375-0utils/bazel/llvm-project-overlay/openmp/runtime/src/BUILD.bazel
+324-0utils/bazel/llvm-project-overlay/flang/unittests/BUILD.bazel
+268-0utils/bazel/llvm-project-overlay/flang/BUILD.bazel
+200-0utils/bazel/llvm-project-overlay/flang/include/flang/Optimizer/Dialect/BUILD.bazel
+114-0utils/bazel/llvm-project-overlay/flang/include/flang/Optimizer/HLFIR/BUILD.bazel
+108-0utils/bazel/llvm-project-overlay/flang/lib/Frontend/BUILD.bazel
+1,389-048 files not shown
+3,710-054 files

LLVM/project a80b840llvm/lib/Demangle DLangDemangle.cpp, llvm/unittests/Demangle DLangDemangleTest.cpp

[Demangle] Implement type D demangling and add all D basic type encodings (#202834)

This patch adds type name output to D demangler `parseType` and adds all
D basic type encodings to it.
DeltaFile
+138-10llvm/lib/Demangle/DLangDemangle.cpp
+37-12llvm/unittests/Demangle/DLangDemangleTest.cpp
+175-222 files

LLVM/project 662d9a8llvm/lib/Target/AMDGPU/AsmParser AMDGPUAsmParser.cpp, llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

[AMDGPU] Validate WMMA scale/format combination

Only some combinations are listed as supported.

Fixes: https://github.com/ROCm/llvm-project/issues/2634
DeltaFile
+27-7llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+16-16llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
+16-16llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
+31-0llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+12-12llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
+20-0llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
+122-513 files not shown
+152-519 files

LLVM/project 607250allvm/lib/Target/AMDGPU SIISelLowering.cpp

use decimal number rather than hex
DeltaFile
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1-11 files

LLVM/project f0c60f5llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.reduce.fmin.ll llvm.amdgcn.reduce.fmax.ll

[AMDGPU] Support Wave Reduction intrinsics for half types

Supported Ops: `fmin`, `fmax`, `fadd`, `fsub`.
DeltaFile
+941-264llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+941-264llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+902-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+899-160llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+18-5llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+15-3llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+3,716-8566 files