LLVM/project 64ddaeallvm/lib/Target/AMDGPU GCNPreRAOptimizations.cpp

[AMDGPU] Use subclass query for VGPR_16 RA hinting. NFCI (#177017)

DeltaFile
+1-2llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
+1-21 files

LLVM/project 6ed45a0mlir/include/mlir/Dialect/LLVMIR NVVMOps.td, mlir/lib/Dialect/LLVMIR/IR NVVMDialect.cpp

[MLIR][NVVM] Add tensormap.replace NVVM Op (#174926)

This change adds the `nvvm.tensormap.replace` Op to the NVVM
dialect for the `tensormap.replace` PTX instruction.

PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-tensormap-replace
DeltaFile
+189-0mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+186-0mlir/test/Target/LLVMIR/nvvm/tensormap_replace.mlir
+129-0mlir/test/Target/LLVMIR/nvvm/tensormap_replace_invalid.mlir
+120-0mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+624-04 files

LLVM/project b716ca4llvm/docs AMDGPUUsage.rst

[AMDGPU] Update documentation for wave reduction intrinsics
DeltaFile
+70-4llvm/docs/AMDGPUUsage.rst
+70-41 files

LLVM/project 65a27a4clang/include/clang/Basic BuiltinsAMDGPU.td, clang/lib/CodeGen/TargetBuiltins AMDGPU.cpp

[AMDGPU] Add builtins for wave reduction intrinsics
DeltaFile
+84-0clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+8-0clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+4-0clang/include/clang/Basic/BuiltinsAMDGPU.td
+96-03 files

LLVM/project c94739allvm/lib/CodeGen MachineCombiner.cpp

[MachineCombiner] Defer pattern order verfication. NFC (#177081)

The `verifyPatternOrder` function was created to check if machine
combiner patterns are ordered by their latency reduction degree. This
function can be merged into the following loop, which iterates through
all the patterns, such that (1) `TII::genAlternativeCodeSequence`, which
can be quite expensive, won't be called twice (2) since it's now placed
after we print out the candidate sequence through debug print, if
anything goes wrong during the verification, we at least know what the
sequence looks like (3) we don't need to verify all patterns if we will
eventually exit early.

This should be a NFC
DeltaFile
+15-33llvm/lib/CodeGen/MachineCombiner.cpp
+15-331 files

LLVM/project 8636af3llvm/test/CodeGen/RISCV clmul.ll, llvm/test/CodeGen/X86 clmul-vector.ll

Address review comments

Created using spr 1.3.6-beta.1
DeltaFile
+12,546-0llvm/test/CodeGen/RISCV/clmul.ll
+6,171-5,115llvm/test/CodeGen/X86/clmul-vector.ll
+5,421-5,421llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+2,919-2,919llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+36,182-22,5803,009 files not shown
+269,044-176,5533,015 files

LLVM/project 6aa3ab3llvm/test/CodeGen/RISCV clmul.ll, llvm/test/CodeGen/X86 clmul-vector.ll

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]
DeltaFile
+12,546-0llvm/test/CodeGen/RISCV/clmul.ll
+6,171-5,115llvm/test/CodeGen/X86/clmul-vector.ll
+5,421-5,421llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+2,919-2,919llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+36,182-22,5803,006 files not shown
+269,001-176,5383,012 files

LLVM/project 2c3e3cfllvm/test/CodeGen/RISCV clmul.ll, llvm/test/CodeGen/X86 clmul-vector.ll

Rebase

Created using spr 1.3.6-beta.1
DeltaFile
+12,546-0llvm/test/CodeGen/RISCV/clmul.ll
+6,171-5,115llvm/test/CodeGen/X86/clmul-vector.ll
+5,421-5,421llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
+5,392-5,392llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3c.txt
+3,733-3,733llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt
+2,919-2,919llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vopc.txt
+36,182-22,5803,006 files not shown
+269,001-176,5383,012 files

LLVM/project ecdfa89llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx/ir-instruction extractelement.ll

[LoongArch] Remove DAG combination for extractelement

Combination for `trunc+extend+extractelement` to a single
`extractelement` may occur error, because the high bits of the
extract index truncated by `trunc` operation are reserved
after the combination.

This commit remove this combination and the issue
https://github.com/llvm/llvm-project/issues/176839 will never
appear.
DeltaFile
+0-43llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+26-12llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
+26-552 files

LLVM/project 8bb659fllvm/utils/lit/tests filter-failed-rerun.py

[lit] Fix filter-failed-rerun.py on readonly FSes (#177075)

This test invokes lit in a directory and then tries to overwrite
fail.txt within that directory. With the project sources mounted as
read-only, fail.txt ends up being marked readonly, which causes cp to
fail without -f. Use cp -f to ensure we overwrite the existing fail.txt.
DeltaFile
+1-1llvm/utils/lit/tests/filter-failed-rerun.py
+1-11 files

LLVM/project 27fc45bllvm/lib/Target/AMDGPU AMDGPU.td VOP3Instructions.td

[AMDGPU] Further improve `AMDGPUSubtargetFeature` multiclass

This PR extends the multiclass to support two additional parameters: one for specifying whether an `AssemblerPredicate` should be generated, and another for dependent `SubtargetFeatures`. This allows 15 more definitions to be converted to use the multiclass.
DeltaFile
+95-107llvm/lib/Target/AMDGPU/AMDGPU.td
+3-3llvm/lib/Target/AMDGPU/VOP3Instructions.td
+2-2llvm/lib/Target/AMDGPU/GCNSubtarget.h
+1-1llvm/lib/Target/AMDGPU/VOP1Instructions.td
+101-1134 files

LLVM/project 3f64e18utils/bazel/llvm-project-overlay/libc BUILD.bazel, utils/bazel/llvm-project-overlay/libc/test/src/stdio BUILD.bazel

[Bazel] Fix libc build (#177072)

Add the necessary wchar components to the tests and create targets that
do not already exist that are needed.
DeltaFile
+69-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2-0utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
+71-02 files

LLVM/project f3c7c93clang/lib/CodeGen CGDebugInfo.cpp, compiler-rt/lib/hwasan hwasan_linux.cpp hwasan.h

update commit message

Created using spr 1.3.8-beta.1
DeltaFile
+12-12llvm/lib/Bitcode/Reader/MetadataLoader.cpp
+14-2compiler-rt/lib/hwasan/hwasan_linux.cpp
+7-7clang/lib/CodeGen/CGDebugInfo.cpp
+8-1compiler-rt/lib/hwasan/hwasan.h
+3-5llvm/include/llvm/IR/DebugInfoMetadata.h
+3-3llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+47-3010 files not shown
+63-4616 files

LLVM/project 49834b7flang/lib/Optimizer/Transforms/CUDA CUFOpConversion.cpp

[flang][cuda][NFC] Fix filename in header (#177070)

DeltaFile
+1-1flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
+1-11 files

LLVM/project 3d7172fllvm/lib/Target/RISCV RISCVInstrInfoY.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+242-0llvm/test/MC/RISCV/rvy/rvy-valid-mode-independent.s
+194-0llvm/test/MC/RISCV/rvy/rvy-auipc.s
+118-0llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
+115-0llvm/lib/Target/RISCV/RISCVInstrInfoY.td
+93-0llvm/test/MC/RISCV/rvy/rvy-invalid-load-store.s
+80-5llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+842-516 files not shown
+1,216-6222 files

LLVM/project 1e16d3bllvm/lib/Target/RISCV RISCVInstrInfoY.td RISCVInstrFormatsY.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+242-0llvm/test/MC/RISCV/rvy/rvy-valid-mode-independent.s
+118-0llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
+115-0llvm/lib/Target/RISCV/RISCVInstrInfoY.td
+93-0llvm/test/MC/RISCV/rvy/rvy-invalid-load-store.s
+77-0llvm/lib/Target/RISCV/RISCVInstrFormatsY.td
+63-0llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+708-015 files not shown
+986-4921 files

LLVM/project 202df1ellvm/lib/Transforms/Vectorize VPlan.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize exact.ll tripcount.ll

capture weights
DeltaFile
+29-7llvm/lib/Transforms/Vectorize/VPlan.cpp
+30-3llvm/test/Transforms/LoopVectorize/exact.ll
+13-10llvm/test/Transforms/LoopVectorize/tripcount.ll
+8-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+80-204 files

LLVM/project 5d44eacllvm/lib/Target/RISCV RISCVInstrInfoY.td RISCVInstrFormatsY.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+242-0llvm/test/MC/RISCV/rvy/rvy-valid-mode-independent.s
+118-0llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
+115-0llvm/lib/Target/RISCV/RISCVInstrInfoY.td
+93-0llvm/test/MC/RISCV/rvy/rvy-invalid-load-store.s
+77-0llvm/lib/Target/RISCV/RISCVInstrFormatsY.td
+63-0llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+708-015 files not shown
+986-4921 files

LLVM/project 3f5a4c6llvm/lib/Target/RISCV RISCVInstrInfoY.td RISCVInstrFormatsY.td, llvm/lib/Target/RISCV/AsmParser RISCVAsmParser.cpp

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.8-beta.1

[skip ci]
DeltaFile
+242-0llvm/test/MC/RISCV/rvy/rvy-valid-mode-independent.s
+108-0llvm/lib/Target/RISCV/RISCVInstrInfoY.td
+77-0llvm/lib/Target/RISCV/RISCVInstrFormatsY.td
+55-0llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+42-0llvm/test/MC/RISCV/rvy/rvy-invalid-mode-independent.s
+39-0llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+563-09 files not shown
+636-515 files

LLVM/project 32d2132compiler-rt/lib/hwasan hwasan_linux.cpp hwasan.h

[HWASAN] [RISC-V] Update EnableTaggingAbi for RISC-V linux. (#176616)

Enabling pointer tagging in the userspace ABI for RISC-V kernels differs
to that of Aarch64. It requires requesting a particular number of masked
pointer bits, an error is returned if the platform could not accommodate
the request:
https://docs.kernel.org/arch/riscv/uabi.html#pointer-masking

While experimenting with enabling RISC-V HWASAN on GCC I was hitting the
error

> HWAddressSanitizer failed to enable tagged address syscall ABI

when attempting to run instrumented programs in the spike simulator
running kernel release 6.18. This patch successfully allows the tagged
address syscall ABI to be enabled by the support runtime.
DeltaFile
+14-2compiler-rt/lib/hwasan/hwasan_linux.cpp
+8-1compiler-rt/lib/hwasan/hwasan.h
+22-32 files

LLVM/project 08778d8llvm/lib/Target/RISCV/MCTargetDesc RISCVMCTargetDesc.cpp

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1
DeltaFile
+12-2llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+12-21 files

LLVM/project 8f90efdclang/lib/CodeGen CGDebugInfo.cpp, llvm/include/llvm/IR DebugInfoMetadata.h DIBuilder.h

[llvm][DebugInfo][NFC] Remove DITypeRefArray in favour of DITypeArray (#177066)

`DITypeRefArray` is just an alias (since
https://github.com/llvm/llvm-project/pull/176938). Remove it in favour
of just using `DITypeArray`.
DeltaFile
+12-12llvm/lib/Bitcode/Reader/MetadataLoader.cpp
+7-7clang/lib/CodeGen/CGDebugInfo.cpp
+3-5llvm/include/llvm/IR/DebugInfoMetadata.h
+3-3llvm/include/llvm/IR/DIBuilder.h
+3-3llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
+3-3llvm/lib/IR/DIBuilder.cpp
+31-337 files not shown
+40-4213 files

LLVM/project 58bdc20llvm/lib/Transforms/Vectorize VPlan.cpp LoopVectorize.cpp, llvm/test/Transforms/LoopVectorize exact.ll tripcount.ll

capture weights
DeltaFile
+29-7llvm/lib/Transforms/Vectorize/VPlan.cpp
+30-3llvm/test/Transforms/LoopVectorize/exact.ll
+9-6llvm/test/Transforms/LoopVectorize/tripcount.ll
+2-0llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+70-164 files

LLVM/project 04d69fcorc-rt/lib/executor SimpleNativeMemoryMap.cpp

[orc-rt] Fix typo in comment.
DeltaFile
+1-1orc-rt/lib/executor/SimpleNativeMemoryMap.cpp
+1-11 files

LLVM/project 5eb3969llvm/lib/Target/RISCV RISCVRegisterInfo.td

[RISC-V][MC] Add a RegisterClass definition for RVY (CHERI)

This is the first commit in a series of changes to add initial MC-layer
support for the upcoming Y extension for CHERI.

Specification: https://riscv.github.io/riscv-cheri/
Co-authored-by: Jessica Clarke <jrtc27 at jrtc27.com>

Pull Request: https://github.com/llvm/llvm-project/pull/176869
DeltaFile
+64-0llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+64-01 files

LLVM/project 597c4f1llvm/lib/Transforms/Utils ControlFlowUtils.cpp, llvm/test/Transforms/Util control-flow-hub-finalize-same-succ-crash.ll

[ControlFlowHub] Fix duplicate DomTree updates when branch successors are identical (#176620)

When a conditional branch has both successors pointing to the same block
(e.g., `br i1 %cond, label %bb, label %bb`), `ControlFlowHub::finalize`
generates duplicate `Delete` updates for the same CFG edge. This can
cause assertion in `fix-irreducible` pass.

Fixes #176553.
DeltaFile
+106-0llvm/test/Transforms/Util/control-flow-hub-finalize-same-succ-crash.ll
+13-5llvm/lib/Transforms/Utils/ControlFlowUtils.cpp
+119-52 files

LLVM/project 81ae828clang/test/CIR/CodeGen inline-asm.c, libcxx/test/libcxx/time nodiscard.verify.cpp

fix tests after latest changes

Created using spr 1.3.8-beta.1
DeltaFile
+453-975llvm/test/CodeGen/X86/avgceils.ll
+1,197-0llvm/test/CodeGen/AArch64/nontemporal-store.ll
+259-819llvm/test/CodeGen/X86/avgceilu.ll
+0-798llvm/test/CodeGen/AArch64/nontemporal.ll
+751-2clang/test/CIR/CodeGen/inline-asm.c
+603-0libcxx/test/libcxx/time/nodiscard.verify.cpp
+3,263-2,594360 files not shown
+14,749-6,107366 files

LLVM/project 6b0dcf5clang/test/OpenMP target_data_use_device_ptr_fallback_codegen.cpp

Add newline at end of file.
DeltaFile
+1-1clang/test/OpenMP/target_data_use_device_ptr_fallback_codegen.cpp
+1-11 files

LLVM/project f57c5c4llvm/test/CodeGen/RISCV clmul.ll, llvm/test/CodeGen/X86 clmul-vector.ll

Merge remote-tracking branch 'upstream/main' into users/abhinavgaba/udp-fallback-4
DeltaFile
+12,546-0llvm/test/CodeGen/RISCV/clmul.ll
+5,892-5,598llvm/test/CodeGen/X86/clmul-vector.ll
+4,065-1,302llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
+3,137-2,053mlir/utils/vscode/package-lock.json
+0-4,569llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
+3,157-0llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8-fake16.txt
+28,797-13,5221,472 files not shown
+77,877-35,1981,478 files

LLVM/project aeed737offload/test/mapping/use_device_ptr target_data_use_device_ptr_class_member_ref_fallback.cpp target_data_use_device_ptr_class_member_fallback.cpp

[NFC][OpenMP][Offload] Add tests for `use_device_ptr(fb_preserve/nullify)`. (3/4) (#173930)

Depends on #170578.

The fallback modifiers are currently part of OpenMP 6.1. 4/8 of the
tests check for the current bad output, with FIXME comments.

3 of these "bad" tests will be fixed with the 4th PR in this stack with
the `fb_nullify` codegen changes.

4th bad test will need a follow-up fix to privatization of byref
`use_device_ptr` operands.

Dependent PR: #173931.
DeltaFile
+33-0offload/test/mapping/use_device_ptr/target_data_use_device_ptr_class_member_ref_fallback.cpp
+32-0offload/test/mapping/use_device_ptr/target_data_use_device_ptr_class_member_fallback.cpp
+31-0offload/test/mapping/use_device_ptr/target_data_use_device_ptr_class_member_ref_fallback_nullify.cpp
+30-0offload/test/mapping/use_device_ptr/target_data_use_device_ptr_class_member_fallback_nullify.cpp
+29-0offload/test/mapping/use_device_ptr/target_data_use_device_ptr_class_member_ref_fallback_preserve.cpp
+28-0offload/test/mapping/use_device_ptr/target_data_use_device_ptr_class_member_fallback_preserve.cpp
+183-07 files not shown
+324-2113 files