LLVM/project 2d78b14clang/include/clang/Basic OpenMPKinds.def OpenMPKinds.h, clang/lib/Parse ParseOpenMP.cpp

[OpenMP][Clang] Parsing/Sema support for `need_device_ptr(fb_nullify/fb_preserve)`. (#168905)

This patch adds parsing, semantic handling, and diagnostics for the
`OpenMP 6.1 fb_nullify` and` fb_preserve` fallback modifiers used with
the `need_device_ptr` map modifier.
DeltaFile
+31-0clang/lib/Parse/ParseOpenMP.cpp
+26-0clang/test/OpenMP/need_device_ptr_kind_messages.cpp
+24-0clang/test/OpenMP/need_device_ptr_kind_ast_print.cpp
+8-0clang/include/clang/Basic/OpenMPKinds.def
+7-0clang/include/clang/Basic/OpenMPKinds.h
+4-0clang/include/clang/Basic/DiagnosticParseKinds.td
+100-01 files not shown
+102-07 files

LLVM/project a8e0afeclang/lib/CIR/CodeGen CIRGenExpr.cpp CIRGenFunction.h, clang/test/CIR/CodeGen vector-ext-element.cpp

[CIR] ArraySubscriptExpr on ExtVectorElementExpr (#169158)

Implement ArraySubscriptExpr support for ExtVectorElementExpr
DeltaFile
+43-10clang/lib/CIR/CodeGen/CIRGenExpr.cpp
+24-0clang/test/CIR/CodeGen/vector-ext-element.cpp
+2-0clang/lib/CIR/CodeGen/CIRGenFunction.h
+69-103 files

LLVM/project dce95b2clang/lib/CIR/CodeGen CIRGenStmtOpenACC.cpp CIRGenOpenACCClause.cpp

[OpenACC][CIR][NFC] Remove 'NYI' diagnostics, since we're done with t… (#169543)

…hese

We've finished all of the clauses/etc that we're going to use this
visitor for, so we can remove the SourceLocation we used just for that,
and replace all NYI with unreachables.
DeltaFile
+25-46clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp
+21-48clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
+7-9clang/lib/CIR/CodeGen/CIRGenFunction.h
+1-2clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
+1-2clang/lib/CIR/CodeGen/CIRGenStmtOpenACCLoop.cpp
+55-1075 files

LLVM/project 6c8ff4fllvm/lib/Target/NVPTX NVPTXISelLowering.cpp

[NVPTX] Fix maybe unused variable in 17852ded (#169542)

DeltaFile
+1-1llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+1-11 files

LLVM/project 8f1bb92llvm/test/CodeGen/NVPTX masked-store-vectors-256.ll masked-load-vectors.ll

[NVPTX] Fix lit test issues from masked load/store implementation (#169535)

From this commit:
https://github.com/llvm/llvm-project/commit/17852deda7fb9dabb41023e2673025c630b9369d,
Build was broken here:
https://lab.llvm.org/buildbot/#/builders/155/builds/15135/steps/7/logs/stdio.
I think this should fix things.
DeltaFile
+3-3llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
+3-3llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
+1-1llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
+7-73 files

LLVM/project 5c6608cllvm/lib/Target/AMDGPU AMDGPUInstructionSelector.cpp AMDGPUISelDAGToDAG.cpp, llvm/test/CodeGen/AMDGPU gws_agpr.ll verify-ds-gws-align.mir

AMDGPU: Use RegClassByHwMode to manage GWS operand special case

On targets that require even aligned 64-bit VGPRs, GWS operands
require even alignment of a 32-bit operand. Previously we had a hacky
post-processing which added an implicit operand to try to manage
the constraint. This would require special casing in other passes
to avoid breaking the operand constraint. This moves the handling
into the instruction definition, so other passes no longer need
to consider this edge case. MC still does need to special case this,
to print/parse as a 32-bit register. This also still ends up net
less work than introducing even aligned 32-bit register classes.

This also should be applied to the image special case.
DeltaFile
+108-234llvm/test/CodeGen/AMDGPU/gws_agpr.ll
+41-9llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+31-2llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
+31-2llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+32-0llvm/test/MC/AMDGPU/ds_gws_sgpr_err.s
+15-15llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
+258-2627 files not shown
+302-26513 files

LLVM/project 1d30ae6llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp

AMDGPU: Stop forcing RequiresCodeGenSCCOrder (#169522)

This hasn't been strictly necessary since c897c13dde.
Practically this makes little difference; we still enable IPRA
by default which implies this option. By removing this explicit
force, -enable-ipra=0 has the expected change in the pass pipeline
to remove the DummyCGSCC runs.
DeltaFile
+0-4llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+0-41 files

LLVM/project d7dcc10llvm/docs DeveloperPolicy.rst, llvm/utils/git github-automation.py

[GitHub] Add review instructions for commit access requests (#168971)

As discussed in
https://discourse.llvm.org/t/clarification-on-how-to-accept-commit-access-requests/88728,
clarify reviewer instructions for how to accept commit access requests.
DeltaFile
+4-1llvm/docs/DeveloperPolicy.rst
+2-0llvm/utils/git/github-automation.py
+6-12 files

LLVM/project 8cbaffcllvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU codegen-prepare-addrspacecast-non-null.ll

AMDGPU: Try to use zext to implement constant-32-bit addrspacecast

If the high bits are assumed 0 for the cast, use zext. Previously
we would emit a build_vector and a bitcast with the high element
as 0. The zext is more easily optimized. I'm less convinced this is
good for globalisel, since you still need to have the inttoptr back
to the original pointer type.

The default value is 0, though I'm not sure if this is meaningful
in the real world. The real uses might always override the high
bit value with the attribute.
DeltaFile
+24-24llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
+18-18llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
+16-16llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
+18-9llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
+6-6llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+8-2llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+90-752 files not shown
+95-778 files

LLVM/project 882ea7allvm/test/CodeGen/AMDGPU constant-address-space-32bit.ll

AMDGPU: Add more tests for 32-bit constant address space

The sub-dword cases just assert now, so comment those out.
DeltaFile
+1,560-19llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
+1,560-191 files

LLVM/project 0c9c62allvm/lib/Target/PowerPC PPCISelLowering.cpp, llvm/test/CodeGen/PowerPC memCmpUsedInZeroEqualityComparison.ll

[PowerPC ]convert `(setcc (and X, 1), 0, eq)`  to  `XORI (and X, 1), 1` (#168384)

Convert `(setcc (and X, 1), 0, eq)` to `XORI (and X, 1), 1`  , it will save one instruction.
DeltaFile
+69-0llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+1-2llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
+70-22 files

LLVM/project f545c2cclang/lib/Sema SemaDeclCXX.cpp

[clang][NFC] Don't copy into a vector just to iterate in `IsInitListMemberExprInitialized` (#169385)

DeltaFile
+11-11clang/lib/Sema/SemaDeclCXX.cpp
+11-111 files

LLVM/project 4822f49clang/lib/Analysis CFG.cpp, clang/test/Analysis lifetime-cfg-output.cpp scopes-cfg-output.cpp

[LifetimeSafety] Add parameter lifetime tracking in CFG (#169320)

This PR enhances the CFG builder to properly handle function parameters
in lifetime analysis:

1. Added code to include parameters in the initial scope during CFG
construction for both `FunctionDecl` and `BlockDecl` types
2. Added a special case to skip reference parameters, as they don't need
automatic destruction
3. Fixed several test cases that were previously marked as "FIXME" due
to missing parameter lifetime tracking

Previously, Clang's lifetime analysis was not properly tracking the
lifetime of function parameters, causing it to miss important
use-after-return bugs when parameter values were returned by reference
or address. This change ensures that parameters are properly tracked in
the CFG, allowing the analyzer to correctly identify when stack memory
associated with parameters is returned.

Fixes https://github.com/llvm/llvm-project/issues/169014
DeltaFile
+50-7clang/test/Sema/warn-lifetime-safety.cpp
+28-0clang/test/Analysis/lifetime-cfg-output.cpp
+19-1clang/lib/Analysis/CFG.cpp
+10-1clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
+2-0clang/test/Analysis/scopes-cfg-output.cpp
+109-95 files

LLVM/project 3a86b08clang-tools-extra/clangd/test lit.cfg.py index-tools.test

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+14-1clang-tools-extra/clangd/test/lit.cfg.py
+2-4clang-tools-extra/clangd/test/index-tools.test
+3-1clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
+2-1clang-tools-extra/clangd/test/system-include-extractor.test
+1-0clang-tools-extra/clangd/test/CMakeLists.txt
+22-75 files

LLVM/project 4bbebd6clang-tools-extra/clangd/test index-tools.test include-cleaner-batch-fix.test

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+2-4clang-tools-extra/clangd/test/index-tools.test
+3-1clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
+2-1clang-tools-extra/clangd/test/system-include-extractor.test
+1-0clang-tools-extra/clangd/test/CMakeLists.txt
+8-64 files

LLVM/project 69fdf37clang-tools-extra/clangd/test index-tools.test include-cleaner-batch-fix.test

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+2-4clang-tools-extra/clangd/test/index-tools.test
+3-1clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
+2-1clang-tools-extra/clangd/test/system-include-extractor.test
+1-0clang-tools-extra/clangd/test/CMakeLists.txt
+8-64 files

LLVM/project d5aa686mlir/lib/Dialect/GPU/Pipelines GPUToXeVMPipeline.cpp

[GPUToXeVMPipeline][Pipeline] Modify pipeline to add `convert-vector-to-llvm`. (#166204)

`convert-vector-to-llvm` pass applies a set of vector transformation
patterns that are not included in the standard `convert-to-llvm` pass
interface. These additional transformations are required to properly
lower MLIR vector operations. Since not all vector ops have direct
`llvm` dialect lowering, many of them must first be progressively
rewritten into simpler or more canonical vector ops, which are then
lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is
necessary to ensure a complete and correct lowering of vector operations
to the `llvm` dialect.
DeltaFile
+3-0mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
+3-01 files

LLVM/project 6a6b99aclang/test/CIR/CodeGenOpenACC loop-private-clause.cpp combined-firstprivate-clause.cpp, flang/test/Lower/OpenACC acc-reduction.f90

[acc][flang][cir] Add recipes to data entry operations (#149210)

This patch refactors the OpenACC dialect to attach recipe symbols
directly to data operations (acc.private, acc.firstprivate,
acc.reduction)
rather than to compute constructs (acc.parallel, acc.serial, acc.loop).

Motivation:
The previous design required compute constructs to carry both the recipe
symbol and the variable reference, leading to complexity. Additionally,
recipes were required even when they could be generated automatically
through MappableType interfaces.

Changes:
- Data operations (acc.private, acc.firstprivate, acc.reduction) now
  require a 'recipe' attribute referencing their respective recipe
  operations
- Verifier enforces recipe attribute presence for non-MappableType
  operands; MappableType operands can generate recipes on demand

    [21 lines not shown]
DeltaFile
+99-181mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+74-74flang/test/Lower/OpenACC/acc-reduction.f90
+72-72clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
+72-72clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
+72-72clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
+72-72clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
+461-54334 files not shown
+1,126-1,16140 files

LLVM/project 44cffbellvm/lib/Target/RISCV RISCVISelLowering.cpp, llvm/test/CodeGen/RISCV fma-combine.ll

[RISCV] Propagate SDNode flags when combining `(fmul (fneg X), ...)` (#169460)

In #157388, we turned `(fmul (fneg X), Y)` into `(fneg (fmul X, Y))`.
However, we forgot to propagate SDNode flags, specifically fast math
flags, from the original FMUL to the new one. This hinders some of the
subsequent (FMA) DAG combiner patterns that relied on the contraction
flag and as a consequence, missed some of the opportunities to generate
negation FMA instructions like `fnmadd`.

This patch fixes this issue by propagating the flags.

---------

Co-authored-by: Craig Topper <craig.topper at sifive.com>
DeltaFile
+56-0llvm/test/CodeGen/RISCV/fma-combine.ll
+2-1llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+58-12 files

LLVM/project 84df446llvm/lib/Target/AMDGPU AMDGPUTargetMachine.cpp, llvm/test/CodeGen/AMDGPU llc-pipeline.ll

AMDGPU: Remove DummyCGSCC use after buffer lowering passes (#169519)

The fixme the comment refers to was removed.
DeltaFile
+205-210llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+0-3llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+205-2132 files

LLVM/project d125cabllvm/lib/Transforms/InstCombine InstCombineCasts.cpp, llvm/test/Transforms/InstCombine cast.ll known-bits-lerp-pattern.ll

[InstCombine] Support multi-use values in cast elimination transforms (#165877)

`canEvaluateTruncated` and `canEvaluateSExtd` previously rejected
multi-use values to avoid duplication. This was overly conservative, if
all users of a multi-use value are part of the transform, we can
evaluate it in a different type without duplication.

This change tracks visited values and defers decisions on multi-use
values until we verify all their users were visited.
`EvaluateInDifferentType` now memoizes multi-use values to avoid
creating duplicates.

Applied to truncation and sext. Zext unchanged due to its dual-return
nature.
DeltaFile
+314-78llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+144-0llvm/test/Transforms/InstCombine/cast.ll
+46-47llvm/test/Transforms/InstCombine/known-bits-lerp-pattern.ll
+21-29llvm/test/Transforms/InstCombine/cast-mul-select.ll
+6-8llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
+6-8llvm/test/Transforms/InstCombine/logical-select.ll
+537-1702 files not shown
+544-1808 files

LLVM/project 4877c59llvm/lib/Target/SPIRV SPIRVCombinerHelper.cpp SPIRVCombine.td, llvm/test/CodeGen/SPIRV/GlobalISel/InstCombine prelegalizercombiner-select-to-faceforward.mir

[SPIRV] Add PreLegalizer pattern matching for `faceforward` (#139959)

Tasks completed:
- Pattern match`select(fcmp(dot(p2, p3), 0), p1, -p1)` to
`faceforward(p1, p2, p3)`
- Add pattern matching tests to
`prelegalizercombiner-select-to-faceforward.mir` and `faceforward.ll`
- Add CL extension error test
`llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll`
- Add CL extension test for no pattern matching in
`llvm/test/CodeGen/SPIRV/opencl/faceforward.ll`

Closes #137255.
DeltaFile
+163-62llvm/test/CodeGen/SPIRV/hlsl-intrinsics/faceforward.ll
+199-0llvm/test/CodeGen/SPIRV/GlobalISel/InstCombine/prelegalizercombiner-select-to-faceforward.mir
+151-0llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
+29-0llvm/test/CodeGen/SPIRV/opencl/faceforward.ll
+13-0llvm/test/CodeGen/SPIRV/opencl/faceforward-error.ll
+8-1llvm/lib/Target/SPIRV/SPIRVCombine.td
+563-631 files not shown
+565-637 files

LLVM/project 012721dmlir/lib/Bindings/Python IRCore.cpp, mlir/test/python/ir operation.py

[mlir][python] Propagate error diagnostics when an op couldn't be created. (#169499)

DeltaFile
+16-1mlir/test/python/ir/operation.py
+2-1mlir/lib/Bindings/Python/IRCore.cpp
+18-22 files

LLVM/project bab0310bolt/include/bolt/Core MCPlusBuilder.h, bolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp

[BOLT][BTI] Add MCPlusBuilder::addBTItoBBStart

This function contains most of the logic for BTI:
- it takes the BasicBlock and the instruction used to jump to it.
- then it checks if the first non-pseudo instruction is a sufficient
landing pad for the used call.
- if not, it generates the correct BTI instruction.

Also introduce the isBTIVariantCoveringCall helper to simplify the logic.
DeltaFile
+105-0bolt/unittests/Core/MCPlusBuilder.cpp
+75-0bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+13-0bolt/include/bolt/Core/MCPlusBuilder.h
+193-03 files

LLVM/project c3f271fbolt/include/bolt/Core MCPlusBuilder.h, bolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp

[BOLT][BTI] Add MCPlusBuilder::updateBTIVariant

Checks if an instruction is BTI, and updates the immediate value to the
newly requested variant.
DeltaFile
+8-0bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+6-0bolt/include/bolt/Core/MCPlusBuilder.h
+6-0bolt/unittests/Core/MCPlusBuilder.cpp
+20-03 files

LLVM/project 83d9c63utils/bazel/third_party_build zlib-ng.BUILD

[bazel] Add alias for zlib-ng for WORKSPACE compat (#169530)

The consumer of zlib in third-party/BUILD.bazel expects zlib-ng from the
BCR, if you still load this version from your WORKSPACE / MODULE.bazel
you need to use this name instead.
DeltaFile
+5-0utils/bazel/third_party_build/zlib-ng.BUILD
+5-01 files

LLVM/project 4533699bolt/include/bolt/Core MCPlusBuilder.h, bolt/lib/Target/AArch64 AArch64MCPlusBuilder.cpp

[BOLT][BTI] Add MCPlusBuilder::isBTILandingPad (#167306)

- takes both implicit and explicit BTIs into account
- fix related comment in 
   llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
DeltaFile
+18-0bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+17-0bolt/unittests/Core/MCPlusBuilder.cpp
+14-0bolt/include/bolt/Core/MCPlusBuilder.h
+3-2llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
+52-24 files

LLVM/project 8187592clang/lib/Analysis CFG.cpp, clang/test/Analysis lifetime-cfg-output.cpp scopes-cfg-output.cpp

fix-missing-lifetimeends-for-params
DeltaFile
+50-7clang/test/Sema/warn-lifetime-safety.cpp
+28-0clang/test/Analysis/lifetime-cfg-output.cpp
+19-1clang/lib/Analysis/CFG.cpp
+10-1clang/unittests/Analysis/FlowSensitive/LoggerTest.cpp
+2-0clang/test/Analysis/scopes-cfg-output.cpp
+109-95 files

LLVM/project 1441f04clang/lib/CIR/CodeGen CIRGenExprCXX.cpp Address.h, clang/test/CIR/CodeGen placement-new.cpp

[CIR] Upstream reserved placement new handling (#169436)

This upstreams the code to support reserved placement new calls.
DeltaFile
+40-0clang/test/CIR/CodeGen/placement-new.cpp
+21-2clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
+6-0clang/lib/CIR/CodeGen/Address.h
+67-23 files

LLVM/project 8380a48llvm/test/Transforms/LoopVectorize vectorize-zero-estimated-trip-count.ll

[PGO] Add REQUIRES to test (#169531)

The test was added by b8ef25aa643761233dc5b74d9fb7c38a2064d9c7. It
failed on at least the following bots, but the failure did not reproduce
on my test machines or in pre-commit CI:

- https://lab.llvm.org/buildbot/#/builders/190/builds/31643
- https://lab.llvm.org/buildbot/#/builders/65/builds/25949
- https://lab.llvm.org/buildbot/#/builders/154/builds/24417

d69e70149636efa0293310303878fbf9a5f31433 did not fix the failure.
Hopefully this will.
DeltaFile
+1-0llvm/test/Transforms/LoopVectorize/vectorize-zero-estimated-trip-count.ll
+1-01 files