LLVM/project 5798791llvm/lib/Transforms/InstCombine InstCombineSelect.cpp, llvm/test/Transforms/InstCombine select-cmpxchg.ll

[InstCombine] Allow simplifying FP selects of cmpxchg instructions. (#181977)

We already simplify selects that test the flag returned by a cmpxchg and
select between the value the cmpxchg loaded and the compare operand.

This patch extends the fold to FP (and vector) compare-exchange
operations, where the compare operand and loaded value are bitcast.
DeltaFile
+67-0llvm/test/Transforms/InstCombine/select-cmpxchg.ll
+26-2llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+93-22 files

LLVM/project 44a15dcclang/lib/Analysis/LifetimeSafety Origins.cpp FactsGenerator.cpp, clang/test/Sema warn-lifetime-safety-suggestions.cpp

lambda and captured this
DeltaFile
+8-5clang/lib/Analysis/LifetimeSafety/Origins.cpp
+11-0clang/test/Sema/warn-lifetime-safety-suggestions.cpp
+3-2clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+22-73 files

LLVM/project c29779fllvm/lib/Target/SPIRV SPIRVGlobalRegistry.cpp SPIRVGlobalRegistry.h

rename
DeltaFile
+94-84llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+4-4llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+98-882 files

LLVM/project 5a5e2bfllvm/lib/Target/SPIRV SPIRVGlobalRegistry.cpp SPIRVGlobalRegistry.h

[NFC][SPIRV] Remove last uses of SPIRVType and do some renaming for consistency
DeltaFile
+50-47llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+7-5llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+4-4llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+0-6llvm/lib/Target/SPIRV/SPIRVTypeInst.h
+61-624 files

LLVM/project 3c31c0fllvm/lib/Target/SPIRV SPIRVGlobalRegistry.h SPIRVTypeInst.h

[NFC][SPIRV] Replace `SPIRVType` with `SPIRVTypeInst`
DeltaFile
+4-4llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+1-1llvm/lib/Target/SPIRV/SPIRVTypeInst.h
+1-1llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+6-63 files

LLVM/project 0e2fac0mlir/docs/DefiningDialects Operations.md AttributesAndTypes.md, mlir/lib/TableGen AttrOrTypeDef.cpp

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+98-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+82-0mlir/test/mlir-tblgen/attrdefs.td
+82-0mlir/test/mlir-tblgen/typedefs.td
+42-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+39-0mlir/docs/DefiningDialects/Operations.md
+24-0mlir/docs/DefiningDialects/AttributesAndTypes.md
+367-07 files not shown
+432-413 files

LLVM/project 3239246llvm/include/llvm/CodeGen Rematerializer.h, llvm/lib/CodeGen Rematerializer.cpp CMakeLists.txt

[CodeGen] Introduce MIR-level target-independent rematerialization helper (#177080)

This introduces a `Rematerializer` class that identifies register
rematerialization opportunities within a machine function and provides
an API to easily perform those rematerializations with a high level of
control. Its key feature is its ability to model relationships between
rematerializable registers and rematerialize arbitrarily complex groups
of registers at once to specific locations. The class comment describes
the underlying model in details.

This includes unit tests for the class to both verify its correct
behavior and showcase its current rematerialization capabilities.

This hopefully can be a step toward addressing long-standing
rematerialization limitations in LLVM backends. In the future, the goal
is to pair this support with generic or target-dependent strategies for
picking the best rematerialization opportunities to perform to achieve
some kind of objective (e.g., a specific register pressure target in
scheduling regions). As a concrete example, I intend to use this in the
AMDGPU scheduler to help in reducing spilling and/or increasing
occupancy in kernels.
DeltaFile
+789-0llvm/lib/CodeGen/Rematerializer.cpp
+592-0llvm/unittests/CodeGen/RematerializerTest.cpp
+475-0llvm/include/llvm/CodeGen/Rematerializer.h
+1-0llvm/lib/CodeGen/CMakeLists.txt
+1-0llvm/unittests/CodeGen/CMakeLists.txt
+1,858-05 files

LLVM/project 87eee80clang/test/CodeGenHIP printf.cpp printf_nonhostcall.cpp, llvm/lib/Transforms/Utils AMDGPUEmitPrintf.cpp

[AMDGPUEmitPrintf] Use CreatePtrDiff() (#182283)

Use CreatePtrDiff() to emit the pointer subtraction, which will use
ptrtoaddr instead of ptrtoint.

Add a conservative cast to i64 as the return value of CreatePtrDiff is
no longer guaranteed to be a i64.
DeltaFile
+20-20clang/test/CodeGenHIP/printf.cpp
+18-18clang/test/CodeGenHIP/printf_nonhostcall.cpp
+2-3llvm/lib/Transforms/Utils/AMDGPUEmitPrintf.cpp
+40-413 files

LLVM/project e24526cllvm/lib/Target/NVPTX NVPTXCtorDtorLowering.cpp, llvm/test/CodeGen/NVPTX lower-ctor-dtor.ll

[NVPTXCtorDtorLowering] Removing unnecessary pointer arithmetic (#182269)

This code was computing `begin + ((end - begin) exact/ 8) * 8`, which is
a very complicated way to spell `end`.
DeltaFile
+3-10llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp
+1-6llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll
+4-162 files

LLVM/project 418ba6eclang/lib/CodeGen CGDebugInfo.cpp, clang/test/DebugInfo/CXX callsite-edges.cpp callsite-derived.cpp

[clang][DebugInfo] Add virtuality call-site target information in DWARF. (#167666)

Given the test case:

  struct CBase {
    virtual void foo();
  };

  void bar(CBase *Base) {
    Base->foo();
  }

and using '-emit-call-site-info' with llc, the following DWARF
is produced for the indirect call 'Base->foo()':

1$: DW_TAG_structure_type "CBase"
      ...
2$:   DW_TAG_subprogram "foo"
        ...

    [18 lines not shown]
DeltaFile
+93-0clang/test/DebugInfo/CXX/callsite-edges.cpp
+71-0cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/callsite-dwarf.cpp
+58-0clang/test/DebugInfo/CXX/callsite-derived.cpp
+48-0clang/test/DebugInfo/CXX/callsite-base.cpp
+28-1llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+17-0clang/lib/CodeGen/CGDebugInfo.cpp
+315-118 files not shown
+380-2324 files

LLVM/project 1b0c975llvm/test/Transforms/InstSimplify/ConstProp vector-type-constant-folding.ll

Use named values in tests. (#182102)

Address
https://github.com/llvm/llvm-project/pull/181695#discussion_r2821774068.
DeltaFile
+5-5llvm/test/Transforms/InstSimplify/ConstProp/vector-type-constant-folding.ll
+5-51 files

LLVM/project fa84bdcmlir/include/mlir/TableGen AttrOrTypeDef.h, mlir/lib/TableGen AttrOrTypeDef.cpp Operator.cpp

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+98-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+82-0mlir/test/mlir-tblgen/attrdefs.td
+82-0mlir/test/mlir-tblgen/typedefs.td
+42-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+14-0mlir/include/mlir/TableGen/AttrOrTypeDef.h
+11-0mlir/lib/TableGen/Operator.cpp
+329-05 files not shown
+369-411 files

LLVM/project f04d3a2mlir/lib/Dialect/Transform/Interfaces TransformInterfaces.cpp

[MLIR] Apply clang-tidy fixes for performance-unnecessary-value-param in TransformInterfaces.cpp (NFC)
DeltaFile
+4-1mlir/lib/Dialect/Transform/Interfaces/TransformInterfaces.cpp
+4-11 files

LLVM/project 6ca0e29mlir/lib/Dialect/Tosa/IR TosaOps.cpp, mlir/test/Dialect/Tosa tosa-infer-shapes.mlir

[mlir][tosa] Refactor convolution infer return type (#178869)

Lots of logic was repeated for Conv2D, Conv3D and Conv2DBlockScaled ops.
This commit factors out common logic to reduce code duplication.

In doing so, a bug in calculating the bias shape was also fixed. Since
DepthwiseConv2D and TransposeConv2D were fixed independently, this
commit fixes #175765.
DeltaFile
+249-190mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
+20-2mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
+269-1922 files

LLVM/project df05694llvm/lib/Target/AMDGPU VOPCInstructions.td, llvm/test/MC/AMDGPU gfx12_asm_vopcx.s gfx12_asm_vopc.s

[AMDGPU] Add VOPC to gfx13
DeltaFile
+1,246-1,232llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+737-721llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
+186-181llvm/lib/Target/AMDGPU/VOPCInstructions.td
+78-50llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+68-28llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+4-25llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+2,319-2,23723 files not shown
+2,391-2,25329 files

LLVM/project 62d1536llvm/lib/Target/PowerPC PPCInstrInfo.td P10InstrResources.td, llvm/test/MC/Disassembler/PowerPC ppc64le-encoding.txt ppc64-encoding.txt

[PowerPC] Add support for MSGSNDP instruction (#180974)

Message Send Privileged X-form

`msgsndp RB`
```
opcode : 0-5 (5bits)  ===> 31    
RB     : 16-20 (5 bits) 
xo     : 21-30 (10 bits)   ==> 142  

```

---------

Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
DeltaFile
+10-1llvm/lib/Target/PowerPC/PPCInstrInfo.td
+5-0llvm/test/MC/PowerPC/ppc64-encoding.s
+3-0llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
+2-1llvm/lib/Target/PowerPC/P10InstrResources.td
+2-1llvm/lib/Target/PowerPC/P9InstrResources.td
+3-0llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+25-31 files not shown
+26-37 files

LLVM/project cc704f8llvm/test/CodeGen/SystemZ fp-sincos-01.ll patchable-function-entry.ll

[SystemZ] Fix duplicate RUN lines in tests (#182273)

DeltaFile
+0-1llvm/test/CodeGen/SystemZ/fp-sincos-01.ll
+0-1llvm/test/CodeGen/SystemZ/patchable-function-entry.ll
+0-22 files

LLVM/project 2c9ba73mlir/include/mlir/TableGen Operator.h, mlir/lib/TableGen Operator.cpp AttrOrTypeDef.cpp

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+98-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+82-0mlir/test/mlir-tblgen/typedefs.td
+82-0mlir/test/mlir-tblgen/attrdefs.td
+44-0mlir/lib/TableGen/Operator.cpp
+41-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+10-0mlir/include/mlir/TableGen/Operator.h
+357-05 files not shown
+395-411 files

LLVM/project eb88b28mlir/lib/Dialect/GPU/Transforms SubgroupIdRewriter.cpp

[MLIR] Apply clang-tidy fixes for readability-identifier-naming in SubgroupIdRewriter.cpp (NFC)
DeltaFile
+2-2mlir/lib/Dialect/GPU/Transforms/SubgroupIdRewriter.cpp
+2-21 files

LLVM/project e03a87cmlir/lib/Target/LLVMIR ModuleTranslation.cpp

[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in ModuleTranslation.cpp (NFC)
DeltaFile
+3-3mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+3-31 files

LLVM/project 6dc400eflang/lib/Lower/OpenMP Clauses.cpp, flang/lib/Parser openmp-parsers.cpp

format
DeltaFile
+1-1flang/lib/Lower/OpenMP/Clauses.cpp
+1-1flang/lib/Parser/openmp-parsers.cpp
+2-22 files

LLVM/project ff97195llvm/test/CodeGen/X86 knownbits-vpmadd52.ll

[X86] knownbits-vpmadd52.ll - replace extended unicode character with regular ascii (#182278)

Stops update_llc_test_checks.py from complaining / unnecessarily changing the file
DeltaFile
+1-1llvm/test/CodeGen/X86/knownbits-vpmadd52.ll
+1-11 files

LLVM/project 8a7413bllvm/lib/Target/AMDGPU AMDGPULibCalls.cpp

Fix MSVC "not all control paths return a value" warning. NFC. (#182262)

DeltaFile
+1-0llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+1-01 files

LLVM/project d4f9e78llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp

gisel fshl/r
DeltaFile
+31-16llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+31-161 files

LLVM/project 2a75e2dmlir/include/mlir/TableGen Operator.h, mlir/lib/TableGen Operator.cpp AttrOrTypeDef.cpp

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+101-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+82-0mlir/test/mlir-tblgen/typedefs.td
+82-0mlir/test/mlir-tblgen/attrdefs.td
+44-0mlir/lib/TableGen/Operator.cpp
+41-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+10-0mlir/include/mlir/TableGen/Operator.h
+360-05 files not shown
+398-411 files

LLVM/project 64c5676flang/lib/Lower/OpenMP Clauses.cpp, flang/test/Lower/OpenMP/Todo depth-clause.f90

[flang][OpenMP] Initial support for DEPTH clause

The semantic checks do not check any conditions on the associated loop
nest (such as actual depth or whether it is a perfect nest).
Lowering will emit a not-implemented-yet message.
DeltaFile
+38-0flang/test/Parser/OpenMP/depth-clause.f90
+18-0flang/test/Lower/OpenMP/Todo/depth-clause.f90
+17-0flang/test/Semantics/OpenMP/depth-clause.f90
+9-1llvm/include/llvm/Frontend/OpenMP/ClauseT.h
+7-1llvm/include/llvm/Frontend/OpenMP/OMP.td
+6-0flang/lib/Lower/OpenMP/Clauses.cpp
+95-24 files not shown
+105-210 files

LLVM/project 78bc9c7mlir/include/mlir/IR OpBase.td AttrTypeBase.td, mlir/include/mlir/TableGen Operator.h

[MLIR][TableGen] Add inheritableExtraClassDeclaration/Definition for Op and AttrOrTypeDef
DeltaFile
+101-0mlir/test/mlir-tblgen/op-decl-and-defs.td
+44-0mlir/lib/TableGen/Operator.cpp
+41-0mlir/lib/TableGen/AttrOrTypeDef.cpp
+10-0mlir/include/mlir/TableGen/Operator.h
+9-0mlir/include/mlir/IR/OpBase.td
+9-0mlir/include/mlir/IR/AttrTypeBase.td
+214-03 files not shown
+234-49 files

LLVM/project 19ce561llvm/lib/CodeGen/GlobalISel GISelValueTracking.cpp

gisel rem
DeltaFile
+16-0llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+16-01 files

LLVM/project 54ab131libclc CMakeLists.txt, libclc/opencl/lib/clspv subnormal_config.cl

[libclc] Completely remove ENABLE_RUNTIME_SUBNORMAL option (#182125)

Summary:
This isn't really used and this simplifies the code. I could go deeper
to remove this content entirely as they all return `false` but I figured
    this was an easier change to do first.

---------

Co-authored-by: Wenju He <wenju.he at intel.com>
DeltaFile
+0-21libclc/CMakeLists.txt
+0-16libclc/opencl/lib/clspv/subnormal_config.cl
+0-16libclc/opencl/lib/spirv/subnormal_config.cl
+0-16libclc/opencl/lib/generic/subnormal_helper_func.ll
+0-9libclc/opencl/lib/generic/subnormal_disable.ll
+0-9libclc/opencl/lib/generic/subnormal_use_default.ll
+0-874 files not shown
+5-9110 files

LLVM/project 15fb543llvm/lib/Target/AMDGPU VOPCInstructions.td, llvm/test/MC/AMDGPU gfx12_asm_vopc.s gfx12_asm_vopcx.s

[AMDGPU] Add VOPC to gfx13
DeltaFile
+186-181llvm/lib/Target/AMDGPU/VOPCInstructions.td
+78-50llvm/test/MC/AMDGPU/gfx12_asm_vopc.s
+68-28llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopc.txt
+32-16llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vopcx.txt
+28-14llvm/test/MC/AMDGPU/gfx12_asm_vopcx.s
+4-25llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c.txt
+396-31423 files not shown
+468-33029 files