LLVM / project - FreshBSD

LLVM/project 852649d — llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

2026-01-23 19:33:57 UTC by Matt Arsenault via GitHub on ⎇

main

AMDGPU: Remove an unnecessary lookup of the AMDGPUSubtarget (#177646)

Delta		File
+1	-2	llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+1	-2	1 files

LLVM/project 4435083 — libc/shared/math f16fmal.h, libc/src/__support/math f16fmal.h CMakeLists.txt

2026-01-23 19:30:28 UTC by Prajwal via GitHub on ⎇

main

[libc][math] Refactor f16fmal to header-only (#176576)

closes #175324 
part of #175313

Delta		File
+34	-0	libc/src/__support/math/f16fmal.h
+31	-0	libc/shared/math/f16fmal.h
+12	-1	utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+10	-0	libc/src/__support/math/CMakeLists.txt
+2	-4	libc/src/math/generic/f16fmal.cpp
+1	-2	libc/src/math/generic/CMakeLists.txt
+90	-7	3 files not shown
+95	-7	9 files

LLVM/project 01ed562 — clang/lib/Analysis/LifetimeSafety FactsGenerator.cpp, clang/test/Sema warn-lifetime-safety.cpp

2026-01-23 19:11:45 UTC by Utkarsh Saxena on ⎇

users/usx95/01-23-fix_issue_with_references_to_fields

Fix issue with references to fields

Delta		File
+15	-0	clang/test/Sema/warn-lifetime-safety.cpp
+2	-1	clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
+17	-1	2 files

LLVM/project 896a667 — llvm/include/llvm/Support KnownBits.h, llvm/lib/CodeGen/SelectionDAG SelectionDAG.cpp

2026-01-23 19:11:38 UTC by Craig Topper via GitHub on ⎇

main

[KnownBits][SelectionDAG] Add KnownBits::clmul. Support trailing bits.  NFC (#177517)

Borrow the known trailing bits logic from KnownBits::mul, but using
APIntOps::clmul.

Delta		File
+37	-0	llvm/lib/Support/KnownBits.cpp
+1	-5	llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+3	-0	llvm/include/llvm/Support/KnownBits.h
+3	-0	llvm/unittests/Support/KnownBitsTest.cpp
+44	-5	4 files

LLVM/project e7e2c2b — llvm/lib/Target/RISCV RISCVInstrInfoZb.td, llvm/test/CodeGen/RISCV rv64zbc-intrinsic.ll rv64zbc-zbkc-intrinsic.ll

2026-01-23 19:11:11 UTC by Craig Topper via GitHub on ⎇

main

[RISCV] Select (clmul (zext_inreg X, i32), (zext_inreg X, i32)) as (clmulh (slli X, 32), (slli X, 32)). (#177429)

Without Zba. We do the same for MUL->MULHU without Zba.

Delta		File
+9	-0	llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+1	-3	llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
+1	-3	llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
+11	-6	3 files

LLVM/project ff2535a — llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp, llvm/test/CodeGen/AMDGPU ctlz.ll

2026-01-23 19:05:23 UTC by Matt Arsenault on ⎇

users/arsenm/amdgpu/use-legal-type-checks-instead-of-subtarget-predicate

AMDGPU: Use generic legality checks instead of checking subtarget feature

Avoid checking predicates on AMDGPUSubtarget when possible. Also add a couple
of tests for the ctlz combine where ffbh isn't legal. I'm not sure what
the point of the previous check was.

Delta		File
+495	-1	llvm/test/CodeGen/AMDGPU/ctlz.ll
+20	-22	llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+515	-23	2 files

LLVM/project fdb05bb — llvm/lib/Transforms/Scalar DeadStoreElimination.cpp

2026-01-23 19:03:09 UTC by cmtice via GitHub on ⎇

users/arsenm/amdgpu/use-legal-type-checks-instead-of-subtarget-predicate

[LLVM] Update assert to removed unused variable warning. (#177632)

Remove the variable definition and move the function call directly into
the assert statement. Otherwise builds with -Werror that don't use
asserts would fail.

Delta		File
+1	-3	llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
+1	-3	1 files

LLVM/project ff97d1a — libc/shared/math dfmaf128.h, libc/src/__support/math dfmaf128.h CMakeLists.txt

2026-01-23 19:02:46 UTC by Madhur Kumar via GitHub on ⎇

users/arsenm/amdgpu/use-legal-type-checks-instead-of-subtarget-predicate

[libc][math] Refactor dfmaf128 to Header Only (#176480)

Closes https://github.com/llvm/llvm-project/issues/175315, Part of
https://github.com/llvm/llvm-project/issues/175344

Delta		File
+31	-0	libc/src/__support/math/dfmaf128.h
+29	-0	libc/shared/math/dfmaf128.h
+12	-1	utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+2	-9	libc/src/math/generic/dfmaf128.cpp
+10	-0	libc/src/__support/math/CMakeLists.txt
+1	-2	libc/src/math/generic/CMakeLists.txt
+85	-12	3 files not shown
+89	-12	9 files

LLVM/project b94c5e0 — llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU strict_ldexp.f16.ll strict_ldexp.f64.ll

2026-01-23 18:49:14 UTC by vangthao95 via GitHub on ⎇

main

[AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (#177525)

Delta		File
+87	-15	llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
+40	-8	llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll
+31	-4	llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
+1	-1	llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+159	-28	4 files

LLVM/project 7c8a13a — llvm/include/llvm/Transforms/Utils LoopPeel.h, llvm/lib/Transforms/Scalar LoopFuse.cpp LoopUnrollPass.cpp

2026-01-23 18:49:03 UTC by Justin Fargnoli via GitHub on ⎇

main

[LoopPeel] change `peelLoop`'s return type from `bool` to `void` (#177488)

Delta		File
+43	-45	llvm/lib/Transforms/Scalar/LoopFuse.cpp
+8	-10	llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+1	-3	llvm/lib/Transforms/Utils/LoopPeel.cpp
+1	-1	llvm/include/llvm/Transforms/Utils/LoopPeel.h
+53	-59	4 files

LLVM/project 8b00b1d — llvm Maintainers.md

2026-01-23 18:48:35 UTC by Justin Fargnoli via GitHub on ⎇

main

Fix formatting in `Maintainers.md` (#177498)

Delta		File
+1	-1	llvm/Maintainers.md
+1	-1	1 files

LLVM/project f7361ef — llvm/lib/Support Threading.cpp, llvm/lib/Support/Unix Threading.inc

2026-01-23 18:48:20 UTC by Jessica Clarke via GitHub on ⎇

main

[Support] Avoid misguided FreeBSD hack (#177508)

FreeBSD doesn't do anything wrong here, it just happens to define and
use a struct thread in its own headers. The problems arise because here
in LLVM we have using namespace llvm prior to including system headers,
which is bad practice for precisely this reason. If we instead play by
the rules and defer our using namespace llvm until after we've included
the system headers then we no longer need this hack.

This hack is particularly problematic by being conditional on
__FreeBSD__ as of 9093ba9f7ee5 ("[Support] Include Support/thread.h
before api implementations (#111175)"), since on non-FreeBSD
Threading.inc can reference anything in Support/thread.h, only causing
errors on FreeBSD, which is precisely what happened in 64be34c562a2
("Enable using threads on z/OS (#171847)").

By deferring the using namespace llvm until after Threading.inc is
included there may be build failures introduced on untested platforms
due to needing to replace unqualified identifiers with qualified ones by
prepending llvm::.

Delta		File
+13	-15	llvm/lib/Support/Threading.cpp
+5	-9	llvm/lib/Support/Unix/Threading.inc
+5	-4	llvm/lib/Support/Windows/Threading.inc
+23	-28	3 files

LLVM/project f6f5ad3 — llvm/test/Analysis/CostModel/AArch64 arith.ll

2026-01-23 18:44:22 UTC by David Green on ⎇

main

[AArch64] Add some basic i128 arithmetic cost test cases. NFC

Delta		File
+50	-0	llvm/test/Analysis/CostModel/AArch64/arith.ll
+50	-0	1 files

LLVM/project 0d0249e — llvm/lib/Target/AMDGPU AMDGPUIGroupLP.cpp, llvm/test/CodeGen/AMDGPU inlineasm-sgmask.ll

2026-01-23 18:43:53 UTC by Patrick Simmons via GitHub on ⎇

main

Try To Guess SGMasks for Inline Asm Instructions (#155491)

Addresses SWDEV-549227

Delta		File
+179	-0	llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll
+57	-0	llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+236	-0	2 files

LLVM/project c45684f — llvm/test/CodeGen/AMDGPU frem.ll fract-match.ll, llvm/test/CodeGen/AMDGPU/GlobalISel frem.ll

2026-01-23 18:43:23 UTC by Matt Arsenault via GitHub on ⎇

main

AMDGPU: Ignore type legality in isFAbsFree (#177630)

This treats it as free on targets without legal f16. This
matches the existing logic in fneg, and they should be the same.
The test changes are mostly neutral with a few improvements.

Delta		File
+130	-148	llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+93	-93	llvm/test/CodeGen/AMDGPU/frem.ll
+22	-24	llvm/test/CodeGen/AMDGPU/fract-match.ll
+11	-21	llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
+12	-15	llvm/test/CodeGen/AMDGPU/fp-classify.ll
+8	-8	llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
+276	-309	3 files not shown
+285	-318	9 files

LLVM/project 1f8ae28 — clang/include/clang/Driver ToolChain.h, clang/lib/Driver/ToolChains Linux.cpp MSVC.cpp

2026-01-23 18:36:52 UTC by Joseph Huber via GitHub on ⎇

main

[HIP] Pass HIP library directly and refactor (#176019)

Summary:
Currently we pass `-L` and `-l` to get the HIP library. Because we are
attached to a single HIP installation it's far better to pass it by
filename. This is because the `-L` could be out of order with other user
libraries and those could override it. If someone uses HIP with a
specific ROCm installation they most likely want that library, otherwise
incompatibilities can occur. This is still overridable with command line
flags if users want to pass a different one for some reason.

This PR also refactors the handling to be more generic for future
additions.

Delta		File
+20	-11	clang/lib/Driver/ToolChains/Linux.cpp
+11	-6	clang/lib/Driver/ToolChains/MSVC.cpp
+0	-15	clang/lib/Driver/ToolChains/CommonArgs.cpp
+5	-5	clang/test/Driver/hip-runtime-libs-linux.hip
+4	-4	clang/include/clang/Driver/ToolChain.h
+3	-3	clang/test/Driver/rocm-detect.hip
+43	-44	4 files not shown
+50	-50	10 files

LLVM/project 98b55bc — llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp SIISelLowering.cpp

2026-01-23 18:36:26 UTC by Matt Arsenault via GitHub on ⎇

main

AMDGPU: Move f16 legality configuration to SITargetLowering (#177629)

f16 is never legal for R600 so this should not be in the common
base class.

Delta		File
+2	-11	llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+3	-0	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5	-11	2 files

LLVM/project 7edf4e1 — llvm/include/llvm/MC MCRegisterInfo.h, llvm/test/TableGen regunit-intervals.td regunit-intervals-impossible.td

2026-01-23 18:30:26 UTC by Ryan Mitchell via GitHub on ⎇

main

[TableGen] Allow targets to enforce regunits assignment as intervals (#175823)

General tablegen infrastructure for #174888

Delta		File
+100	-2	llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+73	-0	llvm/test/TableGen/regunit-intervals.td
+35	-0	llvm/test/TableGen/regunit-intervals-impossible.td
+17	-1	llvm/include/llvm/MC/MCRegisterInfo.h
+17	-0	llvm/utils/TableGen/RegisterInfoEmitter.cpp
+13	-1	llvm/utils/TableGen/Common/CodeGenRegisters.h
+255	-4	3 files not shown
+279	-5	9 files

LLVM/project 51c617c — llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

2026-01-23 18:29:30 UTC by Matt Arsenault on ⎇

users/arsenm/amdgpu/remove-unnecessary-lookup-amdgpusubtarget

AMDGPU: Remove an unnecessary lookup of the AMDGPUSubtarget

Delta		File
+1	-2	llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+1	-2	1 files

LLVM/project e67f934 — llvm/lib/Transforms/Utils IntegerDivision.cpp, llvm/test/CodeGen/RISCV idiv_large.ll

2026-01-23 18:29:20 UTC by Jin Huang via GitHub on ⎇

main

[profcheck] Fix profle metatdata propagation for Large Integer operations (#175862)

This PR improves the propagation of profile metadata within the
ExpandIRInsts pass. When lowering large integer division operations, the
pass now ensures that branch weights are correctly attached to the
generated control flow, preventing the loss of profile data during IR
expansion.

This PR improves signed and unsigned division/remainder for non-native
bit widths (e.g., `sdiv/udiv i129`, `srem/urem i129`) and implemented
Heuristic-Based Branch Weights labeling using established heuristics for
edge cases e.g., `Division-by-zero guards` and `Magnitude comparisons
between dividends and divisors`.

It also adds detailed comments within the expansion logic to explain the
rationale behind specific branch weight choices and the underlying
mathematical invariants.

Please refer to the implementation details in the source code for the

    [2 lines not shown]

Delta		File
+600	-601	llvm/test/CodeGen/RISCV/idiv_large.ll
+252	-249	llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
+243	-236	llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
+99	-88	llvm/test/CodeGen/X86/pr38539.ll
+49	-39	llvm/test/Transforms/ExpandIRInsts/X86/vector.ll
+52	-3	llvm/lib/Transforms/Utils/IntegerDivision.cpp
+1,295	-1,216	6 files not shown
+1,388	-1,248	12 files

LLVM/project 41567d8 — llvm/include/llvm/CodeGen TargetLoweringObjectFileImpl.h, llvm/include/llvm/MC MCGOFFAttributes.h

2026-01-23 18:29:08 UTC by Amy Kwan via GitHub on ⎇

users/arsenm/amdgpu/remove-unnecessary-lookup-amdgpusubtarget

[SystemZ] Implement ctor/dtor emission via @@SQINIT and .xtor sections (#171476)

This patch implements support for constructors/destructors by
introducing the
`@@SQINIT` section and emitting `.xtor.<priority>` sections within the
SystemZ
AsmPrinter and in the GOFF object lowering layer.

Delta		File
+63	-0	llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+36	-0	llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+34	-0	llvm/test/CodeGen/SystemZ/zos_sinit.ll
+2	-0	llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
+1	-0	llvm/include/llvm/MC/MCGOFFAttributes.h
+1	-0	llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
+137	-0	6 files

LLVM/project 9f3d143 — llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp

2026-01-23 18:24:24 UTC by Matt Arsenault via GitHub on ⎇

main

AMDGPU: Remove dead code configuring f16 is_fpclass (#177626)

isTypeLegal can never be true here. The register classes
are registered at the end of the target lowering constructor,
and in the subclasses.

Delta		File
+0	-5	llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+0	-5	1 files

LLVM/project 1986628 — llvm/lib/Target/AMDGPU AMDGPUPromoteAlloca.cpp, llvm/test/CodeGen/AMDGPU flat-scratch.ll target-cpu.ll

2026-01-23 18:24:19 UTC by Shilei Tian on ⎇

users/shiltian/remove-promote-alloca-target-feature

[AMDGPU] Remove `FeaturePromoteAlloca`

Delta		File
+14	-14	llvm/test/CodeGen/AMDGPU/flat-scratch.ll
+10	-10	llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+1	-16	llvm/test/CodeGen/AMDGPU/target-cpu.ll
+7	-7	llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
+6	-6	llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
+7	-4	llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+45	-57	23 files not shown
+95	-121	29 files

LLVM/project 09685b7 — llvm/lib/Target/AMDGPU AMDGPURegBankLegalizeRules.cpp, llvm/test/CodeGen/AMDGPU/GlobalISel fmax_legacy.ll fmin_legacy.ll

2026-01-23 18:11:24 UTC by vangthao95 via GitHub on ⎇

main

[AMDGPU][GlobalISel] Add RegBankLegalize rules for fmin/fmax_legacy (#177520)

Delta		File
+26	-3	llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
+26	-3	llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
+4	-0	llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+56	-6	3 files

LLVM/project 9109c60 — mlir/include/mlir/Dialect/XeGPU/uArch IntelGpuXe2.h uArchBase.h, mlir/lib/Dialect/XeGPU/Transforms XeGPUPropagateLayout.cpp

2026-01-23 18:10:51 UTC by Artem Kroviakov via GitHub on ⎇

main

[MLIR][XeGPU] Add uArch limitation to scatter load store (#172845)

Delta		File
+98	-35	mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
+71	-2	mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
+32	-4	mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
+7	-1	mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h
+208	-42	4 files

LLVM/project fef6a14 — llvm/lib/Target/AMDGPU AMDGPU.td

2026-01-23 18:09:43 UTC by Shilei Tian via GitHub on ⎇

main

[NFCI][AMDGPU] Fix the predicate `HasDsSrc2Insts` (#177621)

I'm not sure why the predicate has a `!`, and more surprisingly,
removing it doesn't change anything.

Delta		File
+1	-5	llvm/lib/Target/AMDGPU/AMDGPU.td
+1	-5	1 files

LLVM/project 6cf189a — clang/test/CodeGen builtin-rotate.c

2026-01-23 18:06:47 UTC by NagaChaitanya Vellanki via GitHub on ⎇

main

[clang][test] Fix builtin-rotate.c failure on ARM32 (#177290)

Replace unsigned __int128 with unsigned _BitInt(128) since __int128 is
not supported on ARM 32-bit targets.

Fixes https://lab.llvm.org/buildbot/#/builders/79/builds/2754

Delta		File
+14	-4	clang/test/CodeGen/builtin-rotate.c
+14	-4	1 files

LLVM/project 4237e74 — llvm/include/llvm/Analysis TargetTransformInfo.h, llvm/lib/Analysis TargetTransformInfo.cpp

2026-01-23 18:04:06 UTC by Kavin Gnanapandithan via GitHub on ⎇

main

[VectorCombine] foldShuffleOfBinops - failure to track OperandValueInfo (#171934)

Resolves #170500.

Implemented mergeInfo static helper to return common
TTI::OperandValueInfo data .

Added common OperandValueInfo `Op0Info` && `Op1Info` to NewCost
calculation.

Delta		File
+193	-0	llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
+15	-0	llvm/include/llvm/Analysis/TargetTransformInfo.h
+10	-4	llvm/lib/Analysis/TargetTransformInfo.cpp
+7	-4	llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+225	-8	4 files

LLVM/project 4f09b7a — llvm/test/CodeGen/AMDGPU frem.ll fract-match.ll, llvm/test/CodeGen/AMDGPU/GlobalISel frem.ll

2026-01-23 18:02:01 UTC by Matt Arsenault on ⎇

users/arsenm/amdgpu/simplify-isFAbsFree-ignore-legal-type

AMDGPU: Ignore type legality in isFAbsFree

This treats it as free on targets without legal f16. This
matches the existing logic in fneg, and they should be the same.
The test changes are mostly neutral with a few improvements.

Delta		File
+130	-148	llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
+93	-93	llvm/test/CodeGen/AMDGPU/frem.ll
+22	-24	llvm/test/CodeGen/AMDGPU/fract-match.ll
+11	-21	llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
+12	-15	llvm/test/CodeGen/AMDGPU/fp-classify.ll
+8	-8	llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
+276	-309	3 files not shown
+285	-318	9 files

LLVM/project c1de2a9 — llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp SIISelLowering.cpp

2026-01-23 17:46:21 UTC by Matt Arsenault on ⎇

users/arsenm/amdgpu/move-f16-legality-to-sitargetlowering

AMDGPU: Move f16 legality configuration to SITargetLowering

f16 is never legal for R600 so this should not be in the common
base class.

Delta		File
+2	-11	llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+3	-0	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+5	-11	2 files