[CIR] Pointer and vptr width from a CIR-native data-layout entry (#204185)
PointerType and VPtrType have hard-coded sizes and alignments of 64/8
bits. On targets with 32-bit pointers (e.g., nvptx, spirv32), this trips
the record layout builder. Any record containing a pointer hit the
insertPadding assertion (offset >= size)
because the pointer was sized at 8 bytes while the following field was
placed at the AST-mandated 4-byte offset.
### Changes:
- CIRGenerator: attaches a CIR-native cir.ptr data-layout entry at
module setup, storing {size-in-bits, abi-align-in-bits} read
from the target DataLayout (only for the default address space).
- CIRTypes: PointerType reads its size/alignment from that entry
(falling back to 64/8 when absent); VPtrType routes through a cir.ptr so
it picks up the same width.
- LowerToLLVM: strips the cir.ptr entry during CIR→LLVM lowering, since
cir.ptr has no meaning in LLVM IR.
- Unit test: checking 4-byte pointer/vptr layout on nvptx, verified
across CIR, CIR→LLVM.
If the address of the isa_pointer is returned as an error don't ask if it is a tagged pointer (#213163)
The answer isn't right and the wrong type might stick and cause
downstream failures.
Note, the correct solution to this is to distinguish between "couldn't
get the address" and "got a real value of LLDB_INVALID_ADDRESS" but
piping an optional all the way down and then through all the uses is an
intrusive change which I don't have time for right now. That only risk
is that this really IS a tagged pointer with the value
LLDB_INVALID_ADDRESS, so this seems an acceptable workaround.
I ran across this when debugging the ObjC test failures in the ObjC
testuite after 8b9cce358bef26ae4cb9275dd6a43f903bafbaa0. This patch
clears up all those testsuite failures, which should stand as a test for
this patch when I resubmit that change.
[CIR] Implement most of 'musttail' statement attr (#213154)
This implements the basics, and leaves NYI in a few places (particularly
those that require cleanup calculations). There IS some additional work
that needs to be done when the ABI work is put in place as well, and the
thunk 'tail' hint isn't implemented either, and is left as a
missing-feature.
This is necessary for compiling the bytecode interpreter in Clang in a
few places during self-build.
[OpenMP][Offload] Fix use-after-free of the packed firstprivate transfer buffer (#212905)
`packAndTransfer()` called `submitData()`, which captured the address of
the data of
the `SmallVector` member of `PrivateArgumentManagerTy`, as the host
source of an
async transfer. The manager was later moved into an `AsyncInfo`
post-processing
lambda, changing the underlying address of the data:
`addPostProcessingFunction()`
copies the closure rather than moving it, but even if it "moved", the
address of the data owned by `SmallVector`'s inline capacity would have
changed.
The AMDGPU plugin read from the stale host source address when doing the
actual transfer.
Fix: allocate the packed buffer via
`getOrCreateSourceBufferForSubmitData()`, so
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[lldb/docs] Document the remaining scripted-extension plugin categories (#213140)
`python_extensions.md` only covered the first five plugin categories.
This commit adds the missing sections for every plugin category added
since: `ScriptedBreakpointResolver`, `ScriptedHook`,
`ScriptedStackFrameRecognizer`, `ScriptedCommand`, `ParsedCommand`,
`ScriptedStringSummary`, and `ScriptedSyntheticChildren`.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
[lldb] Add target.jit-engine setting (#212998)
Add a target.jit-engine setting that lets users choose which LLVM
execution engine (MCJIT or ORC) is used to JIT expressions. Defaults to
MCJIT to preserve current behavior. This is groundwork for migrating
expression evaluation from MCJIT to ORC; IRExecutionUnit does not yet
consult this setting.
[SandboxVectorizer] Implement topdown/bottomup vectorizers in unison (#205249)
Extend the Sandbox Vectorizer's `bottom-up-vec` pass so a single
implementation can vectorize in either direction, and add the top-down
strategy that walks def-use chains forward from a seed.
Direction selection
--------------------
The pass direction is chosen from the Region's auxiliary pass argument:
"bottom-up" (or empty, the default) and "top-down" map onto a
SchedDirection, and any other value is rejected with a fatal usage
error.
The vectorizer always runs in the same direction as the scheduler.
Top-down traversal
------------------
Bottom-up starts from a seed slice (e.g. stores to consecutive
addresses)
and recurses into operands. Top-down instead starts from a seed of
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[SandboxVec][DAG] Fix notifyEraseInstr to skip scheduled neighbors (#212868)
Guard both loops with !PredN->scheduled() so scheduled neighbors are
left untouched, and add a unit test that erases a node with one
scheduled and one unscheduled predecessor to cover the fix.
[BOLT] Fix RELR addend updates for non-zero image bases (#213000)
This patch fixes an AArch64 BOLT failure exposed by LLVM commit
`fbba327208d7f6994f9a28a51dca3e913e3b444a`, which enabled packed
relative relocations (RELR) globally. BOLT incorrectly used a virtual
relocation address as a file offset when updating RELR addends,
corrupting instrumented executables when their image base was non-zero.
The observed CMake compiler-check failure was only a consequence of the
corrupted BOLT-instrumented Clang executable crashing; the defect itself
is in BOLT, not CMake.
The regression test links an AArch64 PIE with a non-zero image base and
verifies that BOLT updates the RELR addend at the correct file offset.
Assisted-by: Codex
[msan][test] Disable UB cases in vararg_shadow.cpp (#204246)
This patch comments out the tests for char and float, which have
undefined behavior: `warning: second argument to 'va_arg' is of
promotable type 'char'/'float'; this va_arg has undefined behavior
because arguments will be promoted to 'int'/'double' [-Wvarargs]`.
The non-UB way to rewrite the tests is to use `va_arg()` with int and
double types (when the original variables are char and float), but there
are already test cases for int and double.
Note also that the float test makes an assumption that
`cast<float>(cast<double>(float))` will maintain the original shadow,
which MSan need not guarantee. In particular,
https://github.com/llvm/llvm-project/pull/204197 breaks that assumption
(which led to a buildbot breakage and revert).
[libc][__support] Implement exact linear binning for TLSFFreeStoreImpl
Previously, size_to_bit_index used size >> UNIT_SIZE_LOG2 for linear bins,
which mapped size 24 to bin 1 and size 17 to bin 1, causing a mismatch
between allocation request sizes and physical block bucket sizes.
This change introduces exact mapping for linear bins:
- Sizes <= MIN_INNER_SIZE map to bin 0.
- Larger linear sizes use ((size - MIN_INNER_SIZE - 1) >> UNIT_SIZE_LOG2) + 1.
- Exponential bins remain unchanged (verified by z3).
TAG=agy
CONV=811f354e-5729-4a5f-af17-de4b5ca9e647
[NVPTX] Cleanup PTX virtual register encoding (NFC) (#212395)
Unify the scheme used to carry PTX virtual registers through
`MCOperand`s. The register class was encoded and decoded
by two hand-written switchtables, one in
`NVPTXAsmPrinter::encodeVirtualRegister` and one in
`NVPTXInstPrinter::printRegName`, kept in sync only by
comment. Both now share a `VirtualRegisterKind` enum and
`getVirtualRegisterPrefix` in `NVPTXBaseInfo.h`, which also
subsumes `getNVPTXRegClassStr` and drops the stale
`%f`/`%fd` cases left over from the typed float register
classes.
Co-Authored by Opus-5.
Revert "[github] Move BOLT reviewers to team (#211422)" (#213141)
We haven't really being tagged in new PRs anymore, so it looks like this
is not working.
Revert for now until we can fix this, so we don't miss PRs.
This reverts commit 04f124f6151e8c8410e28aba28dc38e590e34c58.
AMDGPU: Give v_cvt_sr_pk_bf16_f32 its own subtarget feature
v_cvt_sr_pk_bf16_f32 was gated on bf16-cvt-insts, but that feature is
also present on gfx950 where the (non-sr) v_cvt_pk_bf16_f32 was first
added. The stochastic-rounding v_cvt_sr_pk_bf16_f32 was only added
for gfx1250 and has no gfx950 encoding, so it would mis-select and
later hit the "Invalid opcode" assert. Introduce cvt-sr-pk-bf16-f32-inst,
currently added to gfx13 and 125*
Co-authored-by: Claude (Claude-Opus-4.8)
[clang-format] Prevent re-assigning type on finalized tokens (#210763)
Prevents a finalized token inside modifyContext from being reassigned
through the setType member function by checking if the token is
finalized.
This ensures ill-defined code like does not trigger an assertion failure
during reformatting.
Fixes #210509
[Offload][Test] Add llvm bin in the PATH for offload-unit suite (#213149)
This PR makes the offload-unit suite put llvm bin directory on PATH so
that tests need lld can find. It fixes the issue exposed in:
https://github.com/llvm/llvm-project/pull/212860
[SBVec] Add top-down vectorization to the unified Sandbox Vectorizer
Extend the Sandbox Vectorizer's `bottom-up-vec` pass so a single
implementation can vectorize in either direction, and add the top-down
strategy that walks def-use chains forward from a seed.
Direction selection
--------------------
The pass direction is chosen from the Region's auxiliary pass argument:
"bottom-up" (or empty, the default) and "top-down" map onto a
SchedDirection, and any other value is rejected with a fatal usage error.
The vectorizer always runs in the same direction as the scheduler.
Top-down traversal
------------------
Bottom-up starts from a seed slice (e.g. stores to consecutive addresses)
and recurses into operands. Top-down instead starts from a seed of
consecutive loads and recurses into *users*:
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