LLVM/project 69653c1llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

[RISCV][NFC] Move ZacasABIFix Pass Declaration

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVZacasABIFix.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 077b10dllvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

[RISCV][NFC] Move RISCVCodeGenPrepare Declarations

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVCodeGenPrepare.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project 4be849cllvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV prefer-w-inst.mir

[RISCV] Port Opt W Instrs to NewPM

Assisted-by: AI
DeltaFile
+44-22llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+35-0llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+3-3llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+88-297 files not shown
+97-3113 files

LLVM/project 5236852llvm/lib/Target/RISCV RISCVPassRegistry.def RISCV.h

[RISCV] Port Fold Memory Offset Pass to NewPM

Assisted-by: AI
DeltaFile
+37-16llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+36-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/lib/Target/RISCV/RISCVPassRegistry.def
+78-213 files not shown
+81-219 files

LLVM/project 8dce5c8llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.mir

[RISCV] Port Vector Peephole to NewPM

Assisted-by: AI
DeltaFile
+66-44llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+39-0llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+111-497 files not shown
+119-4913 files

LLVM/project ecaa557llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp, llvm/test/CodeGen/RISCV/rvv vl-opt.mir

[RISCV] Port VL Optimizer to NewPM

Assisted-by: AI
DeltaFile
+56-31llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+36-0llvm/lib/Target/RISCV/RISCVVLOptimizer.h
+1-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+98-363 files not shown
+101-369 files

LLVM/project f13ce96llvm/lib/Target/RISCV RISCV.h

Remove useless header
DeltaFile
+0-1llvm/lib/Target/RISCV/RISCV.h
+0-11 files

LLVM/project 64d780abolt/lib/Profile DataAggregator.cpp

[Perf2bolt] Support multi-PID filtering for multiple perf inputs (#215541)

#199324 added support for multiple perf inputs in perf2bolt. Building on
that, this patch additionally supports filtering by multiple PIDs via
--pid=pid1,pid2...
DeltaFile
+25-16bolt/lib/Profile/DataAggregator.cpp
+25-161 files

LLVM/project 035c725llvm/test/CodeGen/NVPTX cmpxchg-sm90.ll f32x2-instructions.ll

[NVPTX] Cleanup PTX ISA subtarget features (#214623)
DeltaFile
+1,514-802llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
+654-654llvm/test/CodeGen/NVPTX/tcgen05-st.ll
+573-573llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+493-301llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
+354-298llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
+276-276llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+3,864-2,90489 files not shown
+8,229-7,04695 files

LLVM/project f47dbacllvm/unittests/ADT SmallVectorTest.cpp, llvm/unittests/IR IntrinsicsTest.cpp

llvm/unittests: Prune unused templates [-Wunused-template] (#215565)
DeltaFile
+0-5llvm/unittests/Support/RecyclerTest.cpp
+0-5llvm/unittests/ADT/SmallVectorTest.cpp
+0-3llvm/unittests/IR/IntrinsicsTest.cpp
+0-133 files

LLVM/project 826edcallvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

[RISCV][NFC] Move ZacasABIFix Pass Declaration

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVZacasABIFix.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVZacasABIFix.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project cde8d00llvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp

[RISCV][NFC] Move RISCVCodeGenPrepare Declarations

This change moves them into their own header, as has been done for the
other NewPM passes.

Assisted-by: AI
DeltaFile
+40-0llvm/lib/Target/RISCV/RISCVCodeGenPrepare.h
+0-12llvm/lib/Target/RISCV/RISCV.h
+1-1llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+1-0llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+1-0llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+43-135 files

LLVM/project aeebb24llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV fold-mem-offset.mir

[RISCV] Port Fold Memory Offset Pass to NewPM

Assisted-by: AI
DeltaFile
+37-16llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+36-0llvm/lib/Target/RISCV/RISCVFoldMemOffset.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/fold-mem-offset.mir
+78-213 files not shown
+81-219 files

LLVM/project 83abe65llvm/lib/Target/RISCV RISCVCodeGenPassBuilder.cpp RISCVOptWInstrs.h, llvm/test/CodeGen/RISCV O3-newpm-pipeline.ll O1-newpm-pipeline.ll

[RISCV] Port Opt W Instrs to NewPM

Assisted-by: AI
DeltaFile
+44-22llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+35-0llvm/lib/Target/RISCV/RISCVOptWInstrs.h
+3-3llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+4-0llvm/test/CodeGen/RISCV/prefer-w-inst.mir
+2-1llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+2-1llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+90-277 files not shown
+97-3113 files

LLVM/project 5d27eb9llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv vmv.v.v-peephole.mir

[RISCV] Port Vector Peephole to NewPM

Assisted-by: AI
DeltaFile
+66-44llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+39-0llvm/lib/Target/RISCV/RISCVVectorPeephole.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+111-497 files not shown
+119-4913 files

LLVM/project 9b25bfbllvm/lib/Target/RISCV RISCVTargetMachine.cpp RISCVCodeGenPassBuilder.cpp, llvm/test/CodeGen/RISCV/rvv vl-opt.mir

[RISCV] Port VL Optimizer to NewPM

Assisted-by: AI
DeltaFile
+56-31llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+36-0llvm/lib/Target/RISCV/RISCVVLOptimizer.h
+1-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+1-0llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+98-363 files not shown
+101-369 files

LLVM/project f922643llvm/lib/Target/RISCV RISCV.h

Remove useless header
DeltaFile
+0-1llvm/lib/Target/RISCV/RISCV.h
+0-11 files

LLVM/project 1a499d7llvm/lib/Target/RISCV RISCV.h RISCVTargetMachine.cpp, llvm/test/CodeGen/RISCV/rvv fixed-vectors-strided-load-store.ll

[RISCV] Port Gather/Scatter Lowering to NewPM (#215669)

This change also adds some missing pass dependencies to the legacy
version of the pass, to reflect some analyses that are already being
used.

Assisted-by: AI
DeltaFile
+72-45llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
+40-0llvm/lib/Target/RISCV/RISCVGatherScatterLowering.h
+0-3llvm/lib/Target/RISCV/RISCV.h
+2-1llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+2-1llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+2-0llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
+118-505 files not shown
+124-5011 files

LLVM/project 60936b3llvm/lib/CodeGen TypePromotion.cpp, llvm/test/CodeGen/RISCV pr148084.ll

[TypePromotion][RISCV][ARM] Ignore the condition operand of selects. (#215685)

We don't need to promote the condition operand in order to promote a
select. It must always be an i1 type so it doesn't matter where it comes
from.

The change to pr148084.ll is a regression, but I don't think it's
directly related to select. TypePromotion is using a zero extend
promotion which makes constants that are harder to materialize and
prevents the use of `not`. This kind of thing can happen independent of
selects being involved.
DeltaFile
+29-29llvm/test/Transforms/TypePromotion/ARM/casts.ll
+17-10llvm/test/CodeGen/RISCV/pr148084.ll
+7-0llvm/lib/CodeGen/TypePromotion.cpp
+53-393 files

LLVM/project 602c4b5llvm/lib/Target/LoongArch LoongArchISelLowering.cpp, llvm/test/CodeGen/LoongArch/lasx vec-extract-brcond.ll

[LoongArch] Fold shifted vector extract comparisons

Fold comparisons of the form:

  (shl (extract_vector_elt X, I), GRLen - EleBits) ==/!= 0

into:

  (extract_vector_elt X, I) ==/!= 0

When the shift amount equals `GRLen - EleBits`, the left shift only moves
the extracted element into the most significant bits without affecting
whether the value is zero. This canonicalization exposes
EXTRACT_VECTOR_ELT to later combines and enables selecting
VPICKVE2GR_* instructions directly.
DeltaFile
+12-27llvm/test/CodeGen/LoongArch/lsx/vec-extract-brcond.ll
+12-27llvm/test/CodeGen/LoongArch/lasx/vec-extract-brcond.ll
+17-0llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+41-543 files

LLVM/project ab1e23cllvm/test/CodeGen/LoongArch/lasx vec-extract-brcond.ll, llvm/test/CodeGen/LoongArch/lsx vec-extract-brcond.ll

[LoongArch][NFC] Add tests for vector extract comparison combines
DeltaFile
+137-0llvm/test/CodeGen/LoongArch/lsx/vec-extract-brcond.ll
+137-0llvm/test/CodeGen/LoongArch/lasx/vec-extract-brcond.ll
+274-02 files

LLVM/project c402a3bclang/lib/CIR/CodeGen CIRGenModule.cpp, clang/test/CIR/CodeGen lambda-generic-in-cxx11abi-lambda.cpp

[CIR] Fix a linking problem with a abi_tag deduced lambda (#215702)

This showed up in self build, but only happens when there is a lambda
with a deduced return type inside another lambda, that returns a type
with an abi_tag on it (std::string in this case). The problem was that
we weren't pulling our mangled name out of the cache, and instead were
re-calculating it every time. This takes code effectively-exactly from
classic-codegen an d puts it into CIRGenModule.cpp

Note the teest is a little fragile for the reproducer, so it needs to be
its own file. Also, there are some parts that are not necessary in it to
reproduce (the 'i' in particular) because this avoids us having 'padded'
lambdas, which results in a call-conv NYI. I considered disabling that,
but it is more work to go back and un-do that flag later, than to just
deal with an extra 'i' for the near future.
DeltaFile
+49-0clang/test/CIR/CodeGen/lambda-generic-in-cxx11abi-lambda.cpp
+10-0clang/lib/CIR/CodeGen/CIRGenModule.cpp
+59-02 files

LLVM/project e7efe8fclang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded vwabdau.c, clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded vwabdau.c

[Clang][RISCV] Fix vwabda[u] operand order (#215494)

See https://github.com/riscv-non-isa/riscv-rvv-intrinsic-doc/pull/435.
DeltaFile
+195-195clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
+195-195clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
+187-187clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
+187-187clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
+102-102clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
+102-102clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
+968-9682 files not shown
+1,166-1,1668 files

LLVM/project 2b46188llvm/lib/Target/AMDGPU SILoadStoreOptimizer.cpp, llvm/test/CodeGen/AMDGPU merge-tbuffer-gfx9.mir merge-tbuffer-gfx12.mir

[AMDGPU] Gate TBUFFER merging on relaxed OOB mode (#212695)

SILoadStoreOptimizer can combine adjacent TBUFFER accesses into a wider
typed buffer instruction. This changes the granularity of hardware OOB
handling and may affect neighboring components when an access is
partially
out of bounds.

Only allow TBUFFER load/store merging when
`amdgpu.tbuffer.oob.mode` is set to relaxed. Keep the accesses separate
when
the flag is absent, any, or strict to preserve strict OOB semantics.

Reference: https://github.com/llvm/llvm-project/pull/160922
DeltaFile
+189-257llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
+127-175llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
+127-175llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
+127-175llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
+6-0llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+576-7825 files

LLVM/project ba5bccflibcxx/test/benchmarks/containers/associative map.bench.cpp unordered_map.bench.cpp, libcxx/test/benchmarks/format formatter_float.bench.cpp write_int_comparison.bench.cpp

[libc++] Fix duplicate names in benchmarks (#215676)

A few benchmarks were using names that were reused elsewhere in the test
suite. All benchmarks must have a unique name, otherwise we can't
distinguish them in LNT.
DeltaFile
+17-11libcxx/test/benchmarks/format/write_int_comparison.bench.cpp
+17-11libcxx/test/benchmarks/format/write_double_comparison.bench.cpp
+4-1libcxx/test/benchmarks/format/formatter_float.bench.cpp
+2-1libcxx/test/benchmarks/containers/associative/unordered_map.bench.cpp
+1-1libcxx/test/benchmarks/containers/associative/map.bench.cpp
+41-255 files

LLVM/project f75f03blibc/src/__support/FPUtil dyadic_float.h, libc/src/__support/builtins CMakeLists.txt truncxfbf2.h

[compiler-rt][builtins] libc-backed float80-bfloat16/float16 conversion builtins
DeltaFile
+78-17libc/src/__support/builtins/fpconvert_helper.h
+38-24libc/src/__support/FPUtil/dyadic_float.h
+41-0libc/src/__support/builtins/extendhfxf2.h
+40-0libc/src/__support/builtins/truncxfhf2.h
+39-0libc/src/__support/builtins/truncxfbf2.h
+37-0libc/src/__support/builtins/CMakeLists.txt
+273-4111 files not shown
+475-4117 files

LLVM/project 57a9c4fllvm/lib/Target/AMDGPU SIInstrInfo.cpp SIFoldOperands.cpp, llvm/test/CodeGen/AMDGPU llvm.amdgcn.sqrt.bf16.ll llvm.amdgcn.sin.bf16.ll

[AMDGPU] VOP1 bf16 instructions read high 16 bit of an inline (#215688)

VOP1 cannot be used in this case and VOP3 shall use OPSEL.
DeltaFile
+18-2llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+20-0llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+8-8llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+4-4llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
+2-2llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
+54-184 files not shown
+62-2610 files

LLVM/project 5d27e3aclang/lib/Driver/ToolChains Flang.cpp, flang/test/Driver fast-math.f90

[Flang][Driver] Override -ffast-math floating point contraction with -ffp-contract= (#213574)

This patch allows overriding the floating point contract settings
implied by -ffast-math by explicitly specifying -ffp-contract=. The
final floating point contract mode follows the usual last-flag-wins
behavior. In addition, -fno-fast-math only cancels the effects of
-ffast-math and preserves any explicitly specified -ffp-contract=
setting.

A warning is emitted when an explicit -ffp-contract= option overrides
the floating point contract mode implied by -ffast-math.

This behavior is consistent with Clang.
DeltaFile
+51-10flang/test/Driver/fast-math.f90
+39-20clang/lib/Driver/ToolChains/Flang.cpp
+90-302 files

LLVM/project 486b922llvm/lib/Target/AMDGPU VOP1Instructions.td, llvm/test/MC/AMDGPU gfx1250_asm_vop3_from_vop1-fake16.s

[AMDGPU] Allow OPSEL in bf16 trans instructions in fake16 (#215687)
DeltaFile
+24-0llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp8.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1_dpp16.txt
+8-8llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
+2-0llvm/lib/Target/AMDGPU/VOP1Instructions.td
+50-245 files

LLVM/project 661cffbclang/lib/CIR/CodeGen CIRGenCall.cpp CIRGenModule.cpp, clang/test/CIR/CodeGen asm-label-redirect.c alloc-size.c

[CIR] Record target-cpu and target-features on function declarations (#214986)

A function declaration carried no CPU or feature attributes. CIRGen set
them from `setNonAliasAttributes`, which runs only for a definition,
where classic CodeGen sets them from `ConstructAttributeList` for a
declaration too. We now set them properly in `constructAttributeList`
alongside the other non-call-site attributes.

Recording them on a declaration exposes a second bug. When a function is
declared first and defined later with a `target` attribute,
`setNonAliasAttributes` wrote the definition's values over the
declaration's rather than replacing them, so a `tune-cpu` that the
`target` attribute suppresses survived. It now clears the three
attributes before writing, which is safe because
`getCPUAndFeaturesAttributes` resolves the most recent declaration, so
its result supersedes anything an earlier one wrote.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+29-0clang/test/CIR/CodeGen/attr-target-x86.c
+15-6clang/lib/CIR/CodeGen/CIRGenModule.cpp
+8-1clang/lib/CIR/CodeGen/CIRGenCall.cpp
+2-2clang/test/CIR/CodeGen/asm-label-redirect.c
+2-2clang/test/CIR/CodeGen/alloc-size.c
+3-1clang/test/CIR/CodeGen/global-init.cpp
+59-121 files not shown
+62-127 files