[AMDGPU] Rematerialize VGPR candidates when SGPR spills results in VGPR Excess (#168079)
Before, when selecting candidates to rematerialize, we would only
consider SGPR candidates when there was an excess of SGPR registers.
Failing to eliminate the excess would result in spills to VGPRs.
This is normally not an issue, unless spilling to VGPRs results in
excess VGPRs.
This patch does 2 things:
* It relaxes the GCNRPTarget success criteria: now we accept regions
where we spill SGPRs to VGPRs, as long as this does not end up in
excess VGPRs.
* It changes isSaveBeneficial to consider the excess VGPRs (which
includes the SGPRs that would be spilled to VGPR).
With these changes, the compiler rematerializes VGPRs when the excess
SGPRs would result in VGPR excess.
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Revert "[llvm-readobj] Dump callgraph section info for ELF" (#176221)
Reverts llvm/llvm-project#157499
Following up on discourse post. Reverting this patch and will attempt a
reland addressing post merge comments.
(cherry picked from commit 97576a86eb25696a2b57cd42370991b172c08405)
[flang] Fix crash with coarray teams #171048 (#172259)
This PR updates the `CHANGE TEAM` construct to fix the bug mentioned in
the issue #171048.
When a construct such as `IfConstruct` was present in the `CHANGE TEAM`
region, several BB were created but outside the region.
(cherry picked from commit 1d4f9ac37c043198d823e85e3cd777dc970d8b75)
[lldb-dap] Move targetId and debuggerId into a session property (#175930)
This makes it clear the fields required for attaching to an existing
debug session.
It also makes it easier to check mutually exclusive fields required to
attach.
(cherry picked from commit 6977e6812c3e2027f0f427506ee151011f1e55bb)
[JITLink][CompactUnwind] Explicitly enumerate mergeable encodings. NFCI. (#176317)
Updates CompactUnwindTraits_MachO_arm64 and
CompactUnwindTraits_MachO_x86_64 encodingCanBeMerged methods to use
switch statements that clearly list mergeable encodings, and have a
default "false" case.
Since the new scheme explicitly covers DWARF modes (always
non-mergeable), this patch removes the separate DWARF mode check from
mergeRecords in CompactUnwindSupport.h.
[RISCV] Use NoV0 register classes for masked `VPseudoBinaryM` (#175706)
There are two constraints:
1. The same register can't have two EEWs. `V0` is already the mask
register, so other register source operands can't be `V0`.
2. The destination and source registers can't overlap. We have added
`@earlyclobber` constraint so we won' allocate `V0` to destination.
[BOLT][BTI] Patch LLD-generated PLTs to contain BTI landing pad
This patch adds the patchPLTEntryForBTI to enable patching PLT entries
generated by LLD.
Context:
To keep BTI consistent, targets of stubs inserted in LongJmp need to be
patched. As PLTs are not optimized and emitted by BOLT, this patch adds
a helper for patching them in the original location.
For PLTs generated by LLD, this is safe as LLD inserts extra nops to
PLTs which don't already contain a BTI.
PLT entry before patching:
adrp x16, Page(&(.got.plt[n]))
ldr x17, [x16, Offset(&(.got.plt[n]))]
add x16, x16, Offset(&(.got.plt[n]))
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[BOLT][BTI] Disassemble PLT entries when processing BTI binaries (#169663)
PLT entries are PseudoFunctions, and are not disassembled or emitted.
For BTI, we need to check the first MCInst of PLT entries, to see
if indirectly calling them is safe or not.
This patch disassembles PLTs for binaries using BTI, while not changing
the behaviour for binaries without BTI.
The PLTs are only disassembled, not emitted.
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Co-authored-by: Paschalis Mpeis <paschalis.mpeis at arm.com>
