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[Clang] Add support for the C `_Defer` TS (#162848)

This implements WG14 N3734 (https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3734.pdf),
aka `_Defer`; it is currently only supported in C if `-fdefer-ts` is passed.

[RISCV] Add Xsfmm vlte and vste intrinsics to getTgtMemIntrinsics. (#171747)

Replace dyn_cast with cast. The dyn_cast can never fail now. Previously
it never succeeded.

[RISCV] Use GPR instead of ixlenimm for sextshamt in PseudoMaskedAMOMinMax. NFC (#171736)

This operand is always a register.

doc

Created using spr 1.3.7

address comments

Created using spr 1.3.7

[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]

[NFC] isOSGlibc: musl is not glibc. (#171734)

Previously, `isOSGlibc()` was returning true for musl triples as well.
This commit changes `isOSGlibc()` to return false for musl triples, and
updates all existing `isOSGlibc()` checks to call `isOSGlibc() ||
isMusl()`, in order to preserve existing behaviour.

[RISCV] Add an OperandType for ordering for atomic pseudos. (#171744)

Address weining's comments

adjust the layout for expandedUnitDims and wg-to-sg distribution shapecast op

[Tooling] Fix misleading progress report when files have multiple compile commands (#169640)

This patch fixes an issue in progress reporting where the processed item
counter could exceed the total item count, leading to confusing outputs
like [22/18].

Closes [#169168](https://github.com/llvm/llvm-project/issues/169168)

[libunwind] fix building on Haiku i386 (#171586)

Co-authored-by: Jérôme Duval <jerome.duval at gmail.com>

[PPC] XFAIL ppc/fixtfti_test.c and ppc/fixunstfti_test.c and track them under issue 171751

[flang][cuda] Add support for allocate with device source (#171743)

Add support for allocate statement with a source that is a device
variable.

[RISCV] Use sew and vec_policy for Rivos vector instruction operands. (#171721)

This enables MachineVerifier and MachineIR printing support for these
operands.

Revert "[SelectionDAG] Salvage debuginfo when combining load and sext… (#171745)

… instrs. (#169779)"

This reverts commit 2b958b9ee24b8ea36dcc777b2d1bcfb66c4972b6.

I might have broken the sanitizer-x86_64-linux bot


/home/b/sanitizer-x86_64-linux/build/llvm-project/compiler-rt/lib/sanitizer_common/sanitizer_procmaps_linux.cpp
clang++:
/home/b/sanitizer-x86_64-linux/build/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:248:
const T &llvm::ArrayRef<llvm::DbgValueLocEntry>::operator[](size_t)
const [T = llvm::DbgValueLocEntry]: Assertion `Index < Length &&
"Invalid index!"' failed.

rebase after fix landed

Created using spr 1.3.8-beta.1

clang-format

Created using spr 1.3.8-beta.1

[compiler-rt] follow-up to 166837, rename COMPILER_RT_FORCE_TEST_BUILTINS_DIR to COMPILER_RT_TEST_BUILTINS_DIR (#171741)

Co-authored-by: David Tenty <daltenty at ibm.com>

[RISC-V][MC] Fix tied operand register class mismatch in P-extension

I have a change to validate the operand classes emitted in the AsmParser
and that caused llvm/test/MC/RISCV/rv32p-valid.s to fail due to the rd_wb
register using a different register class from rd:
`PWADDA_H operand 1 register X6 is not a member of register class GPRPair`
This happens because tablegen's AsmMatcherEmitter emits code to literally
copy over the tied registers and does not feed them through the equivalent
of RISCVAsmParser::validateTargetOperandClass() which would allow adjusting
these operand classes.

Ideally we would handle this in tablegen (or at least add an error), but
the tied operand handling logic is rather complex and I don't understand
it yet. For now just update the rd register class to match rd_wb.

Pull Request: https://github.com/llvm/llvm-project/pull/171738

[TableGen] Replace reachable assertion with error in *ByHwMode

Having duplicate mode entries previously asserted (or silently replaced
the last value with a new one in release builds). Report an error with
a helpful message instead.

Pull Request: https://github.com/llvm/llvm-project/pull/171715

Add a _regexp-break-add and some more tests for the b alias. (#171236)

This commit leaves "b" aliased to the old _regexp-break for now. The two
variants are identical except that `_regexp-break` allows you to say:

`(lldb) b <unrecognized_input> 
`
which gets translated to:

`break set <unrecognized_input>
`

So switching people to `_regexp-break-add` would be a surprising
behavior change. It would be wrong for `_regexp_break-add` have one
branch that call `break set`, so to avoid surprise, I'll add the command
and let people who are playing with `break add` instead of `break set`
can set the alias to the new one by hand for now.

working

[AArch64] Restrict TBI to ignore top 4 bits for Darwin targets.

In order to allow arm64 code to run on MTE environments, we need to make the
compiler only assume the top 4 bits can be ignored as MTE occupies the lower 4.

rdar://164645323

clang-format

Created using spr 1.3.8-beta.1

clang-format

Created using spr 1.3.8-beta.1

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1

fix test

Created using spr 1.3.8-beta.1

[𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1

[Clang][counted_by] Correct signed counted_by values (#171260)

If the 'counted_by' value is signed, we will incorrectly allow accesses
when the value is negative. This has obvious bad effects as it will
allow accessing a huge swath of unallocated memory.

Also clarify and rearrange the parameters to make them more
perspicuous.

Fixes: #170987.