LLVM/project 2693adflibc/shared/math bf16addf128.h, libc/src/__support/math bf16addf128.h CMakeLists.txt

[libc][math] Refactor bf16addf128 to header only (#181058)

Resolves #181018
Part of #147386
DeltaFile
+32-0libc/src/__support/math/bf16addf128.h
+29-0libc/shared/math/bf16addf128.h
+15-0utils/bazel/llvm-project-overlay/libc/BUILD.bazel
+10-0libc/src/__support/math/CMakeLists.txt
+2-5libc/src/math/generic/bf16addf128.cpp
+1-5libc/src/math/generic/CMakeLists.txt
+89-103 files not shown
+94-109 files

LLVM/project d6dee90lld/ELF/Arch RISCV.cpp

[ELF] Move RISCV scanSectionImpl next to getRelExpr. NFC

Move scanSectionImpl and scanSection to right after getRelExpr and
before relocate, matching the ordering used in X86_64.cpp and PPC64.cpp.
DeltaFile
+46-46lld/ELF/Arch/RISCV.cpp
+46-461 files

LLVM/project 78d9957lld/ELF Target.cpp, lld/ELF/Arch RISCVInternalRelocations.h RISCV.cpp

Revert "[LLD] Add support for statically resolved vendor-specific RISCV relocations. (#169273)" (#181336)

This reverts commit 0c6d7a40187e5e6cbdff1cf5dbdb6fe91054bef4 and
follow-up 7dfa132936a89a966befb6045f306cb9905c6dab.

It landed prematurely with multiple issues in the implementation and
tests.
DeltaFile
+0-113lld/ELF/Arch/RISCVInternalRelocations.h
+8-38lld/ELF/Arch/RISCV.cpp
+5-12lld/test/ELF/riscv-vendor-relocations.s
+0-9lld/ELF/Target.cpp
+13-1724 files

LLVM/project cfc311elldb/bindings/interface SBMemoryRegionInfoListExtensions.i SBTypeExtensions.i, lldb/test/API/python_api/find_in_memory TestFindInMemory.py

[lldb/API] Add __getitem__ subscript support to python SBAPI list class (#181457)

This patch adds __getitem__ method to the SBAPI list classes that were
missing subscript support, enabling Pythonic index access (e.g.,
list[0], list[-1]) in Python bindings.

The implementation adds __getitem__ to the following classes:
- SBStringList
- SBFileSpecList
- SBProcessInfoList
- SBMemoryRegionInfoList
- SBThreadCollection
- SBBreakpointList
- SBModuleSpecList
- SBTypeList

Each implementation follows the same pattern:
- Type validation (raises TypeError for non-integer indices)
- Range validation with negative index support (raises IndexError for

    [7 lines not shown]
DeltaFile
+18-0lldb/test/API/python_api/sbsavecoreoptions/TestSBSaveCoreOptions.py
+15-0lldb/test/API/python_api/find_in_memory/TestFindInMemory.py
+13-0lldb/bindings/interface/SBMemoryRegionInfoListExtensions.i
+10-0lldb/bindings/interface/SBTypeExtensions.i
+10-0lldb/test/API/python_api/type/TestTypeList.py
+10-0lldb/bindings/interface/SBBreakpointListExtensions.i
+76-010 files not shown
+151-016 files

LLVM/project 7fd56a0llvm/test/CodeGen/RISCV/rvv fixed-vectors-setcc-fp-vp.ll fixed-vectors-fp-setcc.ll

[RISCV] Calculate max call frame size in RISCVTargetLowering::finalizeLowering. (#181302)

I want to enable the frame pointer when the call frame size is too large
to access emergency spill slots. To do that I need to know the call
frame size early enough to reserve FP.

The code here is copied from AArch64. ARM does the same. I did not check
other targets.

Splitting this off separately because it stops us from unnecessarily
reserving the base pointer in the some RVV tests. That appears to due to
this check

(!hasReservedCallFrame(MF) && (!MFI.isMaxCallFrameSizeComputed() ||
MFI.getMaxCallFrameSize() != 0))) &&

By calculating early !MFI.isMaxCallFrameSizeComputed() is no longer true
and the size is zero.
DeltaFile
+648-640llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+88-88llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+83-81llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+60-60llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
+44-44llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
+18-18llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+941-9314 files not shown
+963-94610 files

LLVM/project bc50d9allvm/lib/Target/RISCV RISCVInstrInfoV.td RISCVInstrInfoZvfofp8min.td

[RISCV] Convert some multiclasses in RISCVInstrInfoV.td to classes if they only have one child def. NFC (#181408)

The child def requires an empty string which looks odd. Use classes and
inheritance instead.
DeltaFile
+77-91llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+3-3llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td
+2-2llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
+82-963 files

LLVM/project 74be8edllvm/lib/CodeGen/GlobalISel LegalizerHelper.cpp

[GlobalISel] Fix type mismatch in LegalizerHelper ternary (#180865)

### Summary

Fix type mismatch in ternary expression that causes GCC `-Werror=extra`
to fail.

### Details

GCC's `-Werror=extra` enforces stricter type consistency in ternary
expressions, in this case unsigned and an enum literal.

### Tested

- Built with ToT clang and GCC 13.3.0 on Linux x86_64 (not really
because there are other warnings, but this one is gone).
- All existing tests pass
DeltaFile
+3-2llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+3-21 files

LLVM/project 5c4a8c1llvm/test/CodeGen/AArch64 clmul-scalable.ll, llvm/test/CodeGen/AMDGPU fptoi.i128.ll

Rebase before commit

Created using spr 1.3.6-beta.1
DeltaFile
+1,560-1,560llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s
+80-2,209llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-loops-large-matrixes.ll
+470-1,417llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
+1,060-707llvm/test/CodeGen/AArch64/clmul-scalable.ll
+0-1,543llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
+1,542-0llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions.ll
+4,712-7,4361,519 files not shown
+63,907-35,8981,525 files

LLVM/project 74599c6clang/test/Driver riscv-cpus.c, clang/test/Driver/print-enabled-extensions riscv-spacemit-a100.c

[RISCV] Add SpacemiT A100 processor definition (#174052)

DeltaFile
+102-0clang/test/Driver/print-enabled-extensions/riscv-spacemit-a100.c
+32-0llvm/lib/Target/RISCV/RISCVProcessors.td
+8-0clang/test/Driver/riscv-cpus.c
+2-0clang/test/Misc/target-invalid-cpu-note/riscv.c
+1-0llvm/docs/ReleaseNotes.md
+145-05 files

LLVM/project e003440clang/test/CXX/drs cwg24xx.cpp cwg4xx.cpp

[clang][NFC] Add missing indentation for expected-notes in C++ DR tests
DeltaFile
+3-3clang/test/CXX/drs/cwg24xx.cpp
+2-2clang/test/CXX/drs/cwg4xx.cpp
+1-1clang/test/CXX/drs/cwg30xx.cpp
+1-1clang/test/CXX/drs/cwg18xx.cpp
+1-1clang/test/CXX/drs/cwg16xx.cpp
+8-85 files

LLVM/project faa0be4clang/include/clang/Basic CodeGenOptions.def, clang/include/clang/Options Options.td

[clang] Ensure -mno-outline adds attributes

Before this change, `-mno-outline` and `-moutline` only controlled the
pass pipelines for the invoked compiler/linker.

The drawback of this implementation is that, when using LTO, only the
flag provided to the linker invocation is honoured (and any files which
individually use `-mno-outline` will have that flag ignored).

This change serialises the `-mno-outline` flag into each function's
IR/Bitcode, so that we can correctly disable outlining from functions in
files which disabled outlining, without affecting outlining choices for
functions from other files. This matches how other optimisation flags
are handled so the IR/Bitcode can be correctly merged during LTO.
DeltaFile
+7-10clang/include/clang/Options/Options.td
+14-3clang/test/CodeGen/attr-no-outline.c
+6-5clang/lib/Driver/ToolChains/CommonArgs.cpp
+3-1clang/lib/CodeGen/CodeGenModule.cpp
+3-0clang/include/clang/Basic/CodeGenOptions.def
+1-1clang/test/Driver/x86-outliner.c
+34-203 files not shown
+37-239 files

LLVM/project 984175cclang/docs ReleaseNotes.rst

Release Note
DeltaFile
+2-0clang/docs/ReleaseNotes.rst
+2-01 files

LLVM/project d2be26aclang/include/clang/Basic AttrDocs.td Attr.td, clang/test/CodeGen attr-no-outline.c

[clang] Add clang::no_outline Attribute (#163666)

This change:

- Adds a `[[clang::no_outline]]` function attribute for C and C++. There
is no equivalent GNU syntax for this attribute, so no `__attribute__`
syntax.
- Uses the presence of `[[clang::no_outline]]` to add the `nooutline`
attribute to IR function definitions.
- Adds test for the above.

The `nooutline` attribute disables both the Machine Outliner (enabled at
Oz for some targets), and the IR Outliner (disabled by default).

Fixes #144135
DeltaFile
+107-0clang/test/CodeGen/attr-no-outline.c
+40-0clang/test/CodeGenObjC/attr-no-outline.m
+12-0clang/include/clang/Basic/AttrDocs.td
+7-0clang/test/Sema/attr-no-outline.c
+7-0clang/test/Sema/attr-no-outline.cpp
+7-0clang/include/clang/Basic/Attr.td
+180-03 files not shown
+187-09 files

LLVM/project e640d38llvm/lib/Target/RISCV RISCVFeatures.td, llvm/lib/TargetParser RISCVISAInfo.cpp

[RISCV] Simplify Extension Predicates, Compatibility (#181255)

This pushes some of our simplifications to extension dependencies into
other parts of RISCVISAInfo and into the tablegen predicates.

The key affected pieces are:
- Error messages around Zcd incompatibilities now reference only `zcd`.
- We now have a big list of extensions that are rv32-only.
DeltaFile
+51-72llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+17-30llvm/lib/TargetParser/RISCVISAInfo.cpp
+1-1llvm/lib/Target/RISCV/RISCVFeatures.td
+69-1033 files

LLVM/project bb71a33utils/bazel/llvm-project-overlay/mlir BUILD.bazel

[mlir] Fix #176920 Add MLIRBindingsPythonLibHeaders library (#181447)

MLIRBindingsPythonLibHeaders includes internal headers.
DeltaFile
+9-0utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
+9-01 files

LLVM/project 4833c51llvm/utils/TableGen DAGISelMatcherOpt.cpp DAGISelMatcher.h

Revert "[TableGen] Introduce MatcherList to manage a linked list of Matchers. NFC (#177875)"

This reverts commit 39613943855e6a82b1bb4c3d16fbaf2289a5d739.

It's failing across multiple build bots.
DeltaFile
+202-222llvm/utils/TableGen/DAGISelMatcherOpt.cpp
+59-250llvm/utils/TableGen/DAGISelMatcher.h
+59-53llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+61-15llvm/utils/TableGen/DAGISelMatcher.cpp
+17-14llvm/utils/TableGen/DAGISelMatcherGen.cpp
+8-8llvm/utils/TableGen/DAGISelEmitter.cpp
+406-5626 files

LLVM/project 1b2196bflang-rt/lib/cuda allocator.cpp, flang-rt/unittests/Runtime/CUDA DefaultStream.cpp CMakeLists.txt

[flang][cuda] Add entry point for set/get default stream (#181440)

DeltaFile
+27-0flang-rt/unittests/Runtime/CUDA/DefaultStream.cpp
+8-0flang-rt/lib/cuda/allocator.cpp
+2-0flang/include/flang/Runtime/CUDA/allocator.h
+1-0flang-rt/unittests/Runtime/CUDA/CMakeLists.txt
+38-04 files

LLVM/project 3961394llvm/utils/TableGen DAGISelMatcherOpt.cpp DAGISelMatcher.h

[TableGen] Introduce MatcherList to manage a linked list of Matchers. NFC (#177875)

The previous memory management involved passing around references to the
std::unique_ptr next pointer in each Matcher. Scopes and
SwitchOpcode/SwitchType did not use std::unique_ptr internally, but
would sometimes need to have the pointers to their children moved to
temporary std::unique_ptrs that may be modified and then put back into
the Scope/Switch. Other code used manual deletion.

This patch introduces a MatcherList object that encapsulates list
management and ownership. The interface is based on std::forward_list
using the libcxx implementation for reference.

Once a Matcher is added to a MatcherList it can only be in that list or
spliced into another list. This ensures it is always owned by a list
that will be responsible for deleting it.

Scope and SwitchOpcode/Type children are now MatcherLists rather than
Matcher*. A nice side effect of this is that we no longer need a Size

    [7 lines not shown]
DeltaFile
+222-202llvm/utils/TableGen/DAGISelMatcherOpt.cpp
+250-59llvm/utils/TableGen/DAGISelMatcher.h
+53-59llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+15-61llvm/utils/TableGen/DAGISelMatcher.cpp
+14-17llvm/utils/TableGen/DAGISelMatcherGen.cpp
+8-8llvm/utils/TableGen/DAGISelEmitter.cpp
+562-4066 files

LLVM/project 560e229libclc/clc/lib/generic/math clc_remquo.inc clc_remquo.cl

Revert "[libclc] replace float remquo with amd ocml implementation" (#181443)

Reverts llvm/llvm-project#177131
It broke SPIRV target: error in backend: unable to legalize instruction:
%88:fid(s32) = G_FCANONICALIZE
DeltaFile
+57-70libclc/clc/lib/generic/math/clc_remquo.inc
+1-10libclc/clc/lib/generic/math/clc_remquo.cl
+58-802 files

LLVM/project 75fcaeflibclc/opencl/lib/amdgcn/mem_fence fence.cl, libclc/opencl/lib/ptx-nvidiacl/mem_fence fence.cl

[libclc] Fix memory_scope and memory_order of *mem_fence builtins (#181311)

See OpenCL spec 6.15.12.5.
https://registry.khronos.org/OpenCL/specs/3.0-unified/html/OpenCL_C.html#fences

// Older syntax memory fences are equivalent to atomic_work_item_fence
with the // same flags parameter, memory_scope_work_group scope, and
ordering as follows:
void mem_fence(cl_mem_fence_flags flags)        // memory_order_acq_rel
void read_mem_fence(cl_mem_fence_flags flags)   // memory_order_acquire
void write_mem_fence(cl_mem_fence_flags flags)  // memory_order_release

---------

Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
DeltaFile
+10-5libclc/opencl/lib/amdgcn/mem_fence/fence.cl
+10-5libclc/opencl/lib/ptx-nvidiacl/mem_fence/fence.cl
+20-102 files

LLVM/project 41d2a0dlibclc/clc/lib/generic/math clc_remquo.inc clc_remquo.cl

Revert "[libclc] replace float remquo with amd ocml implementation (#177131)"

This reverts commit 20c15c7afe97a546d339a5500d3fa273412e2fda.
DeltaFile
+57-70libclc/clc/lib/generic/math/clc_remquo.inc
+1-10libclc/clc/lib/generic/math/clc_remquo.cl
+58-802 files

LLVM/project edae8a4llvm/lib/Target/Hexagon HexagonISelLowering.cpp, llvm/test/CodeGen/Hexagon udiv-vector-nonuniform.ll

[Hexagon] Fix APInt assertion in getBuildVectorConstInts (#181202)

Truncate the ConstantSDNode APInt value to the element bit width before
creating the ConstantInt. After type legalization, a ConstantSDNode may
have a wider type than the vector element (e.g., i32 constant for an i16
element).
DeltaFile
+16-0llvm/test/CodeGen/Hexagon/udiv-vector-nonuniform.ll
+2-1llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+18-12 files

LLVM/project 2bd77c8clang/include/clang/Driver SyclInstallationDetector.h, clang/lib/Driver/ToolChains SYCL.cpp Linux.cpp

[SYCL][Driver] Pass path to libsycl.so by default for SYCL compilation. (#174877)

This patch updates the default behavior for `SYCL` offload compilations.

Specifically, we now pass the path to the SYCL runtime library,
`libsycl.so`, by default to the `clang-linker-wrapper` tool, which is
responsible for linking the `SYCL` runtime library. We also add the SYCL
header include paths by default to both the SYCL host and device
compilations.
DeltaFile
+21-4clang/lib/Driver/ToolChains/SYCL.cpp
+8-0clang/include/clang/Driver/SyclInstallationDetector.h
+8-0clang/test/Driver/sycl-offload-jit.cpp
+2-0clang/lib/Driver/ToolChains/Linux.cpp
+39-44 files

LLVM/project d406ce8lldb/include/lldb/Core ModuleList.h, lldb/include/lldb/Host HostInfoBase.h

[lldb][macOS] Don't fetch settings in Host, to keep layering (#181406)

I introduced a dependency from Host on Core without realizing it in an
earlier PR, while adding a setting to disable the new shared cache
binary blob scanning/reading in HostInfoMacOSX, which caused build
problems. Thanks to Alex for figuring out the build failure I caused.

Add a bool to the methods in HostInfoMacOSX, and have the callers (in
Core and various plugins etc) all fetch the
symbols.shared-cache-binary-loading setting from ModuleList, and pass
the result in.

The least obvious part of this is in ProcessGDBRemote where we first
learn the shared cache filepath & uuid, it calls
HostInfoMacOSX::SharedCacheIndexFiles() - this is only called when the
shared cache binary loading is enabled, so I conditionalize the call to
this method based on the setting.

rdar://148939795
DeltaFile
+30-14lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
+24-2lldb/include/lldb/Core/ModuleList.h
+16-3lldb/include/lldb/Host/HostInfoBase.h
+4-7lldb/source/Core/ModuleList.cpp
+8-2lldb/source/Plugins/SymbolLocator/DebugSymbols/SymbolLocatorDebugSymbols.cpp
+6-3lldb/include/lldb/Host/macosx/HostInfoMacOSX.h
+88-317 files not shown
+115-4313 files

LLVM/project 2f3594dclang/lib/CodeGen BackendUtil.cpp, lld/COFF LTO.cpp

Update callback to return TargetOptions
DeltaFile
+5-2llvm/include/llvm/LTO/Config.h
+2-4llvm/lib/LTO/LTO.cpp
+4-2llvm/lib/LTO/LTOCodeGenerator.cpp
+4-2lld/ELF/LTO.cpp
+4-1clang/lib/CodeGen/BackendUtil.cpp
+4-1lld/COFF/LTO.cpp
+23-123 files not shown
+30-179 files

LLVM/project 58184df.github/workflows/containers/libc Dockerfile

[Github] Update libc container

Add git/cmake which are needed by the workflow. Add some comments pulled
from the libc workflow. Also use a user rather than running as root to
prevent file permissions tests from failing.
DeltaFile
+19-1.github/workflows/containers/libc/Dockerfile
+19-11 files

LLVM/project 897754allvm/lib/Transforms/Instrumentation HWAddressSanitizer.cpp, llvm/test/Instrumentation/HWAddressSanitizer prologue.ll use-after-scope.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+75-75llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
+62-0llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
+27-12llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+16-16llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll
+21-9llvm/test/Instrumentation/HWAddressSanitizer/RISCV/use-after-scope-setjmp.ll
+19-7llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope-setjmp.ll
+220-1197 files not shown
+232-13113 files

LLVM/project c9f1b1dllvm/test/Instrumentation/HWAddressSanitizer prologue.ll alloca.ll, llvm/test/Instrumentation/HWAddressSanitizer/RISCV use-after-scope-setjmp.ll alloca.ll

[𝘀𝗽𝗿] changes to main this commit is based on

Created using spr 1.3.7

[skip ci]
DeltaFile
+75-75llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
+16-16llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll
+4-4llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll
+2-2llvm/test/Instrumentation/HWAddressSanitizer/RISCV/use-after-scope-setjmp.ll
+2-2llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
+2-2llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
+101-1015 files not shown
+106-10611 files

LLVM/project 6d255d0llvm/test/Instrumentation/HWAddressSanitizer prologue.ll alloca.ll, llvm/test/Instrumentation/HWAddressSanitizer/RISCV alloca.ll use-after-scope-setjmp.ll

[𝘀𝗽𝗿] initial version

Created using spr 1.3.7
DeltaFile
+75-75llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
+16-16llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll
+4-4llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll
+2-2llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
+2-2llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
+2-2llvm/test/Instrumentation/HWAddressSanitizer/RISCV/use-after-scope-setjmp.ll
+101-1015 files not shown
+106-10611 files

LLVM/project c417046flang-rt/lib/cuda allocator.cpp, flang/include/flang/Optimizer/Builder CUDAIntrinsicCall.h

[flang][cuda] Lower set/get default stream for arrays (#181432)

DeltaFile
+51-0flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
+39-0flang/module/cuda_runtime_api.f90
+24-0flang/test/Lower/CUDA/cuda-default-stream.cuf
+6-0flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
+2-4flang-rt/lib/cuda/allocator.cpp
+1-3flang/include/flang/Runtime/CUDA/allocator.h
+123-72 files not shown
+127-108 files