LLVM/project 30a0a51llvm/lib/Target/AArch64 AArch64ISelLowering.cpp

[AArch64] Fix FPCR abbreviations and an incorrect association in a comment (NFC) (#211188)
DeltaFile
+5-5llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+5-51 files

LLVM/project 6d0e882libc/include langinfo.yaml CMakeLists.txt, libc/include/llvm-libc-macros langinfo-macros.h CMakeLists.txt

[libc] Add langinfo.h header generation, macros, and types (#210941)

Add header generation support for langinfo.h, including nl_item type
definition, langinfo macros, and YAML header specification.

* libc/include/llvm-libc-types/nl_item.h: Define nl_item type
* libc/include/llvm-libc-macros/langinfo-macros.h: Define POSIX macros
* libc/include/langinfo.yaml: Define langinfo.h interface
* libc/include/langinfo.h.def: Header template
* libc/config/linux/*/headers.txt: Enable langinfo header for Linux

Assisted-by: Automated tooling, human reviewed.
DeltaFile
+131-0libc/include/langinfo.yaml
+86-0libc/include/llvm-libc-macros/langinfo-macros.h
+19-0libc/include/llvm-libc-types/nl_item.h
+11-0libc/include/CMakeLists.txt
+8-0libc/include/llvm-libc-macros/CMakeLists.txt
+1-0libc/include/llvm-libc-types/CMakeLists.txt
+256-05 files not shown
+261-011 files

LLVM/project b9f8a9b

[lldb] Fix SymbolFilePDBTests after FileSpec change f9b5264523b1 (#208425)

GetDirectory() returns a StringRef now which doesn't convert to bool
implicitly
DeltaFile
+0-00 files

LLVM/project 16042c9mlir/lib/Conversion/MathToSPIRV MathToSPIRV.cpp, mlir/test/Conversion/MathToSPIRV math-to-opencl-spirv.mlir

[mlir][SPIR-V] Add MathToSPIRV conversion for copysign on OpenCL targets (#205994)
DeltaFile
+7-0mlir/lib/Conversion/MathToSPIRV/MathToSPIRV.cpp
+4-0mlir/test/Conversion/MathToSPIRV/math-to-opencl-spirv.mlir
+11-02 files

LLVM/project 4bb9022lldb/test/API/tools/lldb-dap/breakpoint-assembly TestDAP_breakpointAssembly.py, lldb/test/API/tools/lldb-dap/instruction-breakpoint TestDAP_instruction_breakpoint.py

[lldb-dap] Migrate breakpointAssembly and instructionBreakpoint test (#211054)
DeltaFile
+85-131lldb/test/API/tools/lldb-dap/breakpoint-assembly/TestDAP_breakpointAssembly.py
+61-81lldb/test/API/tools/lldb-dap/instruction-breakpoint/TestDAP_instruction_breakpoint.py
+146-2122 files

LLVM/project 28972b1llvm/lib/Analysis PHITransAddr.cpp, llvm/test/Transforms/GVN phi-translate-cross-function-cast.ll

[GVN] Fix PHITransAddr crash scanning cross-function cast users (#211169)

When PHI-translating a load address through a select of module-level
constant expressions, the folded side becomes a global constant whose
use-list spans multiple functions. Scanning that use-list for an
available cast could return a cast from another function, which then
made DominatorTree::dominates() query a block from a different function
and trip an assertion.

This patch restricts the search to casts in the current function,
matching the existing guards on the GEP and add paths.

Fixes #211034
DeltaFile
+54-0llvm/test/Transforms/GVN/phi-translate-cross-function-cast.ll
+12-7llvm/lib/Analysis/PHITransAddr.cpp
+66-72 files

LLVM/project 1dc7446libc/src/__support/printf_core float_dec_converter.h, libc/src/stdio/printf_core float_dec_converter.h

Merge branch 'main' into users/c8ef/generator
DeltaFile
+13,068-0llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-max-min-umax-umin.ll
+2,559-652llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
+1,270-764llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+1,253-322llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
+1,248-0libc/src/__support/printf_core/float_dec_converter.h
+0-1,248libc/src/stdio/printf_core/float_dec_converter.h
+19,398-2,986847 files not shown
+49,787-16,914853 files

LLVM/project 6c560cdflang/lib/Lower/Support ReductionProcessor.cpp, flang/test/Lower/OpenMP reduction-array-section.f90

[flang][Lower][OpenMP] Fix reduction on array sections aborting in lowering (#209701)

**Summary**

This regression was introduced by #196094, which added a special
lowering path for reductions on a single array element, such as `a(2)`.

The problem is that Flang also treated an array section like `a(2:96)`
as if it were a single element. Because of this, the section was sent to
a code path that only supports scalar elements.

That path produced an array type that the reduction initialization code
could not handle, so Flang reached a `TODO` and aborted with a “not yet
implemented” error.

**Fix**


The fix is to use the special element path only when the expression has

    [12 lines not shown]
DeltaFile
+39-0flang/test/Lower/OpenMP/reduction-array-section.f90
+5-1flang/lib/Lower/Support/ReductionProcessor.cpp
+44-12 files

LLVM/project d00d24bflang-rt/include/flang-rt/runtime namelist.h, flang-rt/lib/runtime namelist.cpp

[flang-rt] enable IsNamelistNameOrSlash lookahead for scalar namelist items

Problem
-------
An empty NAMELIST assignment on a scalar item — e.g. `l =` in

    &nml l= i_count=7 r_value=2.72/

— aborted at runtime with

    fatal Fortran runtime error: Bad character 'i' in LOGICAL input field

Every EditIntegerInput / EditRealInput / EditLogicalInput /
EditCharacterInput function starts its list-directed arm with

    if (IsNamelistNameOrSlash(io)) return false;   // no value

which peeks ahead (via SavedPosition, no stream consumption) for a
`<name>=` / `<name>%` / `<name>(` shape or one of the terminators

    [21 lines not shown]
DeltaFile
+125-0flang-rt/unittests/Runtime/Namelist.cpp
+10-2flang-rt/lib/runtime/namelist.cpp
+1-1flang-rt/include/flang-rt/runtime/namelist.h
+136-33 files

LLVM/project dabf57fllvm/lib/Target/AArch64 AArch64SVEInstrInfo.td SVEInstrFormats.td, llvm/test/CodeGen/AArch64 imm-splat-ops.ll aarch64-minmaxv.ll

[LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to cover 64-bit vectors. (#209833)

This extends https://github.com/llvm/llvm-project/issues/165559 to
include 64-bit vectors.
DeltaFile
+348-18llvm/test/CodeGen/AArch64/imm-splat-ops.ll
+60-28llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
+27-20llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+16-12llvm/test/CodeGen/AArch64/bsl.ll
+19-0llvm/lib/Target/AArch64/SVEInstrFormats.td
+5-6llvm/test/CodeGen/AArch64/sve-vector-compress.ll
+475-843 files not shown
+483-929 files

LLVM/project ab9a979llvm/lib/Transforms/Scalar GVN.cpp, llvm/test/Transforms/GVN operand-bundle-unique-vn.ll

[fixup] Update tests
DeltaFile
+57-5llvm/test/Transforms/GVN/operand-bundle-unique-vn.ll
+2-0llvm/lib/Transforms/Scalar/GVN.cpp
+59-52 files

LLVM/project 4598148clang/include/clang/Analysis/Analyses/LifetimeSafety Utils.h, clang/lib/Analysis/LifetimeSafety Checker.cpp LoanPropagation.cpp

multiple-compile-time-improv
DeltaFile
+144-52clang/lib/Analysis/LifetimeSafety/Checker.cpp
+84-31clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
+68-32clang/lib/Analysis/LifetimeSafety/Dataflow.h
+53-30clang/lib/Analysis/LifetimeSafety/LiveOrigins.cpp
+35-13clang/include/clang/Analysis/Analyses/LifetimeSafety/Utils.h
+30-16clang/lib/Analysis/LifetimeSafety/MovedLoans.cpp
+414-1747 files not shown
+456-18613 files

LLVM/project 9bb81c2mlir/lib/Dialect/Affine/IR AffineOps.cpp, mlir/test/Dialect/Affine unroll-jam.mlir

[MLIR][Affine] Preserve discardable attrs when adding loop yields (#210571)

`replaceWithAdditionalYields` only appends loop-carried values, so
preserve the loop's discardable attributes, matching `scf.for`.

Assisted-by: OpenAI Codex gpt-5.6-sol max
DeltaFile
+5-5mlir/test/Dialect/Affine/unroll-jam.mlir
+3-0mlir/lib/Dialect/Affine/IR/AffineOps.cpp
+8-52 files

LLVM/project d622ff1llvm CMakeLists.txt

[AMDGPU] Make libc build backwards compatible (triple)

https://github.com/llvm/llvm-project/pull/210032 updated the triple but
did not introduce backwards compatibility, leading to, e.g., failing
check-offload tests due to missing libc.
DeltaFile
+5-1llvm/CMakeLists.txt
+5-11 files

LLVM/project f07e2f1clang/lib/Analysis ThreadSafety.cpp, clang/test/Sema warn-thread-safety-analysis.c

Thread Safety Analysis: Don't warn at joins that re-branch on a try-lock result (#209796)

Previously, when the result of a try-lock call is branched on more than
once, the paths between the branches would disagree on whether the
capability is held while remaining consistent at each branch. The analysis
then gave a false positive warning at the intermediate join:

    mutex 'lock' is not held on every path through here

Create getTerminatorTrylockCall() helper from getEdgeLockset(); if the terminator
of a block branches on the result of a call to a try_acquire_capability-function
(perhaps negated or stored in a local variable), this helper returns that call and
its callee.

Use this new helper in getTerminatorTrylockCaps(), which will return the
capabilities acquired by a trylock; feed these capabilites to intersectAndWarn()
during a branch join, in order to avoid false positives.

Soundness is preserved because intersectAndWarn() still removes the

    [7 lines not shown]
DeltaFile
+102-31clang/lib/Analysis/ThreadSafety.cpp
+54-0clang/test/SemaCXX/warn-thread-safety-analysis.cpp
+15-0clang/test/Sema/warn-thread-safety-analysis.c
+171-313 files

LLVM/project 5205cd7llvm/test/tools/llvm-reduce/Inputs sleep-and-check-stores.py

[llvm-reduce] Tighten the check to count actual store NFC (#210933)
DeltaFile
+1-1llvm/test/tools/llvm-reduce/Inputs/sleep-and-check-stores.py
+1-11 files

LLVM/project b9ba0bellvm/docs LangRef.md, llvm/lib/CodeGen/SelectionDAG LegalizeVectorTypes.cpp TargetLowering.cpp

[SDAG] Specify unsigned compares for loop.dependence.{war|raw} masks (#197437)

Previously, the LangRef was ambiguous about the sign of comparisons used
to create the loop dependence masks. This resulted in the expansion not
following the intended semantics for extreme inputs.

For example, %ptrA = 0, %ptrB = UINT_MAX, should result in a (RAW) mask
with all lanes active. However, previously we'd do ``(%elementSize *
lane) < abs(%ptrB - %ptrA)``, which due to incorrectly using signed
arithmetic would result in a mask with a single lane active as
``abs(%ptrB - %ptrA)`` resulted in 1, not `UINT_MAX`. In other words,
``abs(%ptrB - %ptrA)`` should be ``unsigned-absolute-difference(%ptrA,
%ptrB)``.

Follow up to #188248.
DeltaFile
+25-30llvm/test/CodeGen/AArch64/alias_mask.ll
+24-29llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
+23-20llvm/docs/LangRef.md
+5-26llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+18-9llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+17-5llvm/test/CodeGen/AArch64/alias_mask_scalable_nosve2.ll
+112-1191 files not shown
+129-1197 files

LLVM/project 8beb627lldb/source/Interpreter CommandInterpreter.cpp OptionArgParser.cpp, lldb/test/API/commands/memory/read TestMemoryRead.py

[lldb] Add array decaying (#210918)

In C, an array name in an expression "decays" into a pointer to its
first element. LLDB did not honor this: commands like `memory read
my_array` did not work correctly, because an aggregate type has no
scalar value, so trying to obtain one (ResolveValue/GetValueAsUnsigned)
failed.

This MR adds explicit array decay: for array-typed expressions, the
address of the array object itself is used instead of its (non-existent)
scalar value.
DeltaFile
+42-0lldb/test/API/commands/memory/read/TestMemoryRead.py
+18-1lldb/source/Interpreter/CommandInterpreter.cpp
+13-2lldb/source/Interpreter/OptionArgParser.cpp
+73-33 files

LLVM/project cf7a612lldb/test/API/tools/lldb-dap/completions TestDAP_completions.py

[lldb-dap] Migrate the Completions tests (#210829)

Drop the Scenario dataclass as it is now clear what we are testing for.
DeltaFile
+202-258lldb/test/API/tools/lldb-dap/completions/TestDAP_completions.py
+202-2581 files

LLVM/project 3e009b9llvm/lib/Transforms/Vectorize VPlanEVLTailFolding.cpp

[VPlan] Simplify EVL strided load match in optimizeMaskToEVL. nfc (#211193)
DeltaFile
+5-8llvm/lib/Transforms/Vectorize/VPlanEVLTailFolding.cpp
+5-81 files

LLVM/project e1c80c5llvm/docs AMDGPUUsage.rst

Comments
DeltaFile
+1-1llvm/docs/AMDGPUUsage.rst
+1-11 files

LLVM/project 37509c7llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPUISelLowering.cpp AMDGPULegalizerInfo.cpp

Comments
DeltaFile
+7-12llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+8-10llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+8-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+6-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+4-1llvm/docs/AMDGPUUsage.rst
+1-1llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
+34-243 files not shown
+38-269 files

LLVM/project aa74678llvm/lib/Target/AMDGPU SIISelLowering.cpp AMDGPULegalizerInfo.cpp, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll s-barrier-signal-var-gep.ll

[RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.
DeltaFile
+474-0llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+81-74llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
+72-61llvm/test/CodeGen/AMDGPU/s-barrier.ll
+59-43llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+52-14llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+32-32llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
+770-22448 files not shown
+1,234-57454 files

LLVM/project d2bf47cllvm/lib/Target/AMDGPU SIDefines.h AMDGPUMemoryUtils.h, llvm/test/CodeGen/AMDGPU addrspacecast-barrier.ll

Comments
DeltaFile
+4-3llvm/lib/Target/AMDGPU/SIDefines.h
+1-3llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
+1-1llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+1-1llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+1-1llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+9-106 files

LLVM/project 9986706llvm/docs AMDGPUUsage.rst

Update docs
DeltaFile
+20-13llvm/docs/AMDGPUUsage.rst
+20-131 files

LLVM/project 757c7b1llvm/docs AMDGPUUsage.rst, llvm/lib/Target/AMDGPU AMDGPULegalizerInfo.cpp SIISelLowering.cpp

[AMDGPU] Add synthetic apertures and use them for barriers

Define what a synthetic aperture is, and adjust the barrier AS
to use this new system. This makes the barrier AS even safer to
use as now we can use all 32 bits of it without ever risking
hitting a valid address of any kind (LDS or outside LDS).
DeltaFile
+72-87llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
+44-5llvm/docs/AMDGPUUsage.rst
+21-23llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+18-17llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+12-0llvm/lib/Target/AMDGPU/SIDefines.h
+9-0llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
+176-1324 files not shown
+186-13710 files

LLVM/project 1c0c47eclang/docs AMDGPUSupport.md

Add docs
DeltaFile
+27-0clang/docs/AMDGPUSupport.md
+27-01 files

LLVM/project c23ad1blibcxx/test/benchmarks/containers/sequence sequence_container_benchmarks.h

[libc++] Remove {Pause,Resume}Timing from fast push_back benchmarks (#209130)

These benchmarks are expected to run for a very short time, and
`{Pause,Resume}Timing` should only be used when operations are expected
to take a long time. Removing them reduces the amount of noise in these
benchmarks.

Fixes #208719
DeltaFile
+1-3libcxx/test/benchmarks/containers/sequence/sequence_container_benchmarks.h
+1-31 files

LLVM/project 948c4a2llvm/lib/Target/AArch64/GISel AArch64InstructionSelector.cpp, llvm/test/CodeGen/AArch64/GlobalISel select-extract-vector-elt.mir

[AArch64][GlobalISel] Select vector element extract into GPR (#210030)

Prototyping a new minimal type-based approach to RegBankSelect (#199040)
for compile-time purposes exposed various gaps in instruction selection
when not using the existing RegBankSelect pass. These manifested as new
fallbacks when compiling the IR dataset from [1].

This patch teaches instruction selection to handle extracts of scalar
i8/i16/i32 into GPR directly. This will prevent new fallbacks being
introduced when a new type-based RBS pass is added.

The test cases are extracted from [1].

Assisted-by: codex

[1] https://davemgreen.github.io/gisel.html
DeltaFile
+92-0llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
+29-7llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+121-72 files

LLVM/project ca52c1bllvm/lib/Transforms/Scalar LoopInterchange.cpp, llvm/test/Transforms/LoopInterchange transform-stop-partway.ll pr57148.ll

[LoopInterchange] Prevent the transformation stage from stopping partway (#205564)

As mentioned in #205562, there are cases where the transformation stage
in LoopInterchange stops partway through, and the output IR ends up
partially modified rather than interchanged. Notably, the interchange is
recognized as having succeeded internally even in such cases. Apparently
this happens not to cause any miscompiles at the moment, but it is
clearly dangerous.

This patch removes the early exit in the transformation phase. We cannot
simply remove it, which checks for the presence of a unique successor of
the inner loop header, because there is a case where the header actually
has multiple successors. To avoid that situation, this patch changes the
code to call SplitBlock on the inner loop header unconditionally.

The test changes fall into two categories: some are simply due to newly
added redundant BBs. In the others, the expected interchanges are now
applied as intended, whereas previously the transformation failed and
the interchanges were not applied before this patch.
DeltaFile
+20-39llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+15-19llvm/test/Transforms/LoopInterchange/transform-stop-partway.ll
+18-14llvm/test/Transforms/LoopInterchange/pr57148.ll
+12-14llvm/test/Transforms/LoopInterchange/pr43326-ideal-access-pattern.ll
+11-13llvm/test/Transforms/LoopInterchange/interchanged-loop-nest-3.ll
+11-9llvm/test/Transforms/LoopInterchange/guarded-inner-loop.ll
+87-1083 files not shown
+101-1169 files