LLVM/project 3805d81mlir/docs/DefiningDialects Operations.md, mlir/test/IR properties.mlir

[mlir] Print unit prop-dict entries by presence (#219315)

Teach generated prop-dict parsers and printers to use a bare key for
`UnitAttr` and false-default `UnitProp` entries while retaining the
explicit value spelling for compatibility.

Assisted-by: Codex
DeltaFile
+78-17mlir/tools/mlir-tblgen/OpFormatGen.cpp
+15-2mlir/test/IR/properties.mlir
+2-1mlir/test/lib/Dialect/Test/TestOps.td
+3-0mlir/docs/DefiningDialects/Operations.md
+1-1mlir/test/mlir-tblgen/op-format.mlir
+1-1mlir/test/mlir-tblgen/op-format-custom-properties-printer.td
+100-226 files

LLVM/project 20f25d1clang-tools-extra/clang-ssaf-src-edit-merge CMakeLists.txt

[clang][ssaf] Fix Windows link error by adding clangAST dependency (#219305)

Fixes link failure in SrcEditMerge(Introduced in #216183) on Windows due
to a missing clangAST dependency.

rdar://179151250
DeltaFile
+1-0clang-tools-extra/clang-ssaf-src-edit-merge/CMakeLists.txt
+1-01 files

LLVM/project ff19396lldb/source/Plugins/Process/Linux NativeProcessLinux.cpp

lldb: Linux: restore __ptrace_request typedef for bionic+musl (#219237)

glibc declares ptrace as taking an enum __ptrace_request as its first
argument. Because C++ does not allow implicit conversion from int to an
enumeration type, callers must cast int arguments to __ptrace_request
(e.g., static_cast<__ptrace_request>(req)).
    
However, bionic and musl declare ptrace as taking an int and do not
define __ptrace_request. Providing a fallback typedef int
__ptrace_request
allows the static_cast to compile across all three libcs.

I removed this typedef by accident in
ef9085f5bdb52b27258c150bd7e1fd812fc406c8.

Fixes: commit ef9085f5bdb5 ("lldb: Linux: empty Ptrace.h pollyfill")
Link: https://github.com/llvm/llvm-project/issues/217413
DeltaFile
+7-0lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
+7-01 files

LLVM/project 1f38227llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

Drop removeCommonBlendMask from simplifyBlends, seems to be a no-op now
DeltaFile
+0-19llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+0-191 files

LLVM/project 75973e1clang/test/CodeGen/AArch64/neon load.c, libcxx/test/std/language.support/support.limits/support.limits.general version.version.compile.pass.cpp

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+0-6,246llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
+0-4,877llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
+2,428-0llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-0.ll
+2,426-0llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-1.ll
+2,240-0clang/test/CodeGen/AArch64/neon/load.c
+2,058-2libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
+9,152-11,1252,013 files not shown
+93,591-40,6762,019 files

LLVM/project 13b8540llvm/lib/Transforms/Vectorize VPlanTransforms.cpp, llvm/test/Transforms/LoopVectorize vplan-based-stride-mv.ll

[VPlan] Handle trunc in replaceSymbolicStrides (#216367)

LoopAccessAnalysis skips IntegralCast expressions when speculating
strides, but the trunc case is missing in replaceSymbolicStrides. Add
the case, and make some non-functional improvements while at it.
DeltaFile
+13-14llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+1-2llvm/test/Transforms/LoopVectorize/vplan-based-stride-mv.ll
+14-162 files

LLVM/project 851ce84llvm/lib/CodeGen ModuloSchedule.cpp

ModuloSchedule: Use use_instructions instead of use_operands + getParent (#219297)

The use list only inspected the user, so directly loop over the users.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+6-7llvm/lib/CodeGen/ModuloSchedule.cpp
+6-71 files

LLVM/project b8cbca3llvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp

Update supportsWGP to use feature bits instead

Change-Id: Ie1ecc691fac766dc2f32ff4edcb41ccf2483a71c
DeltaFile
+1-3llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+1-31 files

LLVM/project 6a5367allvm/lib/CodeGen Rematerializer.cpp

Rematerializer: Use def_instructions instead of def_operands + getParent (#219298)

Directly iterate the user instructions instead of querying the same
parent for each use.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-4llvm/lib/CodeGen/Rematerializer.cpp
+2-41 files

LLVM/project c59f418llvm/include/llvm/ADT FoldingSet.h, llvm/include/llvm/Analysis ScalarEvolution.h

[ADT] Remove ComputeNodeHash and Trait::ComputeHash (NFC) (#219029)

With the switch to open addressing (commit b3411b89c3af),
FoldingSetNode stores its hash in the node itself.  Table growth
rehashes nodes by calling getFoldingSetHash(), leaving ComputeNodeHash
and Trait::ComputeHash unused.
DeltaFile
+0-36llvm/include/llvm/ADT/FoldingSet.h
+3-14llvm/include/llvm/CodeGen/SelectionDAG.h
+0-9llvm/include/llvm/Analysis/ScalarEvolution.h
+3-593 files

LLVM/project 9ebb067mlir/include/mlir/IR SymbolTable.h

[mlir][IR][NFC] Disambiguate `SymbolTable::Visibility` references (#219301)

As a follow-up to 979b722, address MSVC's confusion when it's trying to
resolve the underqualified enum name:
```
error C2955: 'mlir::OpTrait::SymbolTable': use of class template requires template argument list
```

Assisted-by: OpenAI Codex

Signed-off-by: Artem Gindinson <gindinson at roofline.ai>
DeltaFile
+11-10mlir/include/mlir/IR/SymbolTable.h
+11-101 files

LLVM/project 747588allvm/lib/Target/Hexagon HexagonBitSimplify.cpp

Hexagon: Use use_instructions in BitSimplify use scans

This only inspects the parent instruction, so use use_instructions
instead.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+8-10llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+8-101 files

LLVM/project 5964066compiler-rt/lib/scudo/standalone secondary.h, compiler-rt/lib/scudo/standalone/tests secondary_test.cpp

[scudo] Track maximum resident memory in cache (#219036)

Add tracking for the resident memory in MapAllocatorCache. Unreleased
cache entries where Time != 0 are assumed to be resident, while entries
that have passed through releaseOlderThan where Time == 0 have had their
physical pages discarded.

Tracking is performed by updating CurrentResidentBytes on store, remove,
and release operations, recoding the peak in maxResidentBytes and
reporting it in getStats.
DeltaFile
+44-0compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
+35-2compiler-rt/lib/scudo/standalone/secondary.h
+79-22 files

LLVM/project cd17483llvm/test/CodeGen/AArch64 vector-ldst-offset.ll vector-ldst-align.ll, llvm/test/CodeGen/AMDGPU/NextUseAnalysis test_ers_emit_restore_in_loop_preheader2.mir test_ers_nested_loops.mir

Rebase, address comments

Created using spr 1.3.7
DeltaFile
+9,921-0llvm/test/CodeGen/AArch64/vector-ldst-align-float.ll
+8,227-0llvm/test/CodeGen/AArch64/vector-ldst-align.ll
+0-6,246llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
+0-4,877llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
+3,448-2llvm/test/CodeGen/AArch64/vector-ldst-offset.ll
+2,421-285llvm/test/tools/llvm-mca/AArch64/Cortex/A57-forwarding.s
+24,017-11,4103,448 files not shown
+186,009-80,4233,454 files

LLVM/project 3aff3f8llvm/lib/Target/AMDGPU SIRegisterInfo.cpp AMDGPUInstructionSelector.cpp, llvm/lib/Target/RISCV RISCVRegisterInfo.h RISCVRegisterInfo.cpp

GlobalISel: Replace MachineOperand based register constraint API

Replace MachineOperand reference in getConstrainedRegClassForOperand with
a Register. It is only valid to call this on a generic vreg operand, which
must be a Register so there's no point in using an operand reference.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+31-33llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+6-6llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
+4-5llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+4-5llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+2-6llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
+3-2llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+50-575 files not shown
+59-6611 files

LLVM/project 367293aclang/include/clang/Basic OffloadArch.h, clang/lib/Basic Cuda.cpp OffloadArch.cpp

[Clang] Rename OffloadArch::TargetArch::SPIRV to AMDGCNSPIRV to avoid confusion (#218502)

Following up to
https://github.com/llvm/llvm-project/pull/213362/changes#r3745729994,
the `TargetArch::SPIRV` introduced by #213362 actually corresponds to
`amdgcnspirv`, which is not the same as standard SPIRV: This could prove
rather confusing in the future. Renaming to `TargetArch::AMDGCNSPIRV`
also decouples "`TargetArch::SPIRV`" from AMD-specific SPIRV support, as
SPIRV is used by other vendors as well.
DeltaFile
+12-10clang/include/clang/Basic/OffloadArch.h
+6-6clang/unittests/Basic/OffloadArchTest.cpp
+4-4clang/lib/Basic/OffloadArch.cpp
+3-3clang/lib/Driver/Driver.cpp
+2-2clang/lib/Basic/Cuda.cpp
+27-255 files

LLVM/project e192df0clang/lib/CIR/Dialect/Transforms CallConvLoweringPass.cpp, clang/test/CIR/CodeGen call-conv-lowering-x86_64-packed.c

[CIR] Classify a named bit-field access unit as a bit-field on x86_64

mapCIRType built the ABI FieldInfo for a bit-field access unit with IsBitField
set only for an unnamed one, so a named unit reached the classifier as an
ordinary field.  We now pass IsBitField with the unit's width to be able to
lower named bit-fields correctly.

Assisted-by: Cursor / claude-opus-5
DeltaFile
+33-0clang/test/CIR/CodeGen/call-conv-lowering-x86_64-packed.c
+6-1clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
+39-12 files

LLVM/project 41c2ec5llvm/include/llvm/Support KnownFPClass.h, llvm/lib/Analysis ValueTracking.cpp

[KnownFPClass] Add `KnownFPClass::frem` [NFC] (#218949)

Follow up to https://github.com/llvm/llvm-project/pull/218726

Moves `frem` deduction logic from `Analysis/ValueTracking.cpp` and
`CodeGen/GlobalISel/GISelValueTracking.cpp` to `KnownFPClass::frem`.
DeltaFile
+30-0llvm/lib/Support/KnownFPClass.cpp
+1-18llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+1-18llvm/lib/Analysis/ValueTracking.cpp
+5-0llvm/include/llvm/Support/KnownFPClass.h
+37-364 files

LLVM/project a58e481mlir/lib/Dialect/XeGPU/Transforms XeGPUArrayLengthOptimization.cpp, mlir/test/Dialect/XeGPU array-len-op-unit.mlir

[MLIR][XeGPU] Update array-length users atomically (#217478)

Preflight load and slice users before changing tensor descriptor types,
then update their dependent types and offsets in one pattern
application.

Assisted-by: Codex
DeltaFile
+88-147mlir/lib/Dialect/XeGPU/Transforms/XeGPUArrayLengthOptimization.cpp
+198-2mlir/test/Dialect/XeGPU/array-len-op-unit.mlir
+286-1492 files

LLVM/project d97960dllvm/lib/Target/AMDGPU/Utils AMDGPUBaseInfo.cpp, llvm/test/CodeGen/AMDGPU lds-limit-diagnostics.ll

[AMDGPU] Ignore CU mode on targets without WGP mode

isFullSIMDMode() treated +cumode as meaningful on every generation, so on
pre-gfx10 targets it halved both the physical and the addressable LDS size
and dropped getNumWorkGroupSIMDs() from 4 to 2. Before the LDS size rework
the CU/WGP adjustment was gated on isGFX10Plus(), and +cumode was simply
ignored elsewhere.

rocFFT passes -mcumode to hipRTC unconditionally, so its Bluestein kernels
started failing to compile on gfx942 with "local memory (65536) exceeds
limit (32768)".

Change-Id: I0b440751aedd8f8b5d334ee62b68ffdc449d53f8
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
DeltaFile
+5-0llvm/test/CodeGen/AMDGPU/lds-limit-diagnostics.ll
+3-1llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+8-12 files

LLVM/project 6560cd0llvm/lib/CodeGen Rematerializer.cpp

Rematerializer: Use def_instructions instead of def_operands + getParent

Directly iterate the user instructions instead of querying the same
parent for each use.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+2-4llvm/lib/CodeGen/Rematerializer.cpp
+2-41 files

LLVM/project 5e5edf0llvm/lib/Transforms/Vectorize VPlanPredicator.cpp, llvm/test/Transforms/LoopVectorize blend-in-header.ll predicatedinst-loop-invariant.ll

Don't preserve branch-on-constant
DeltaFile
+15-62llvm/test/Transforms/LoopVectorize/constantfolder.ll
+5-25llvm/test/Transforms/LoopVectorize/predicatedinst-loop-invariant.ll
+2-10llvm/test/Transforms/LoopVectorize/blend-in-header.ll
+11-1llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
+2-9llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll
+3-7llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
+38-1141 files not shown
+39-1217 files

LLVM/project 948eff3llvm/lib/CodeGen ModuloSchedule.cpp

ModuloSchedule: Use use_instructions instead of use_operands + getParent

The use list only inspected the user, so directly loop over the users.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
DeltaFile
+6-7llvm/lib/CodeGen/ModuloSchedule.cpp
+6-71 files

LLVM/project 0fd16c5llvm/lib/ProfileData InstrProf.cpp, llvm/test/tools/llvm-profdata merge-incompatible.test

[llvm-profdata] Clarify incompatible counter profile error (#219280)

Fix based on the comment on
https://github.com/llvm/llvm-project/pull/213177#pullrequestreview-5011647833
DeltaFile
+1-2llvm/lib/ProfileData/InstrProf.cpp
+1-1llvm/test/tools/llvm-profdata/merge-incompatible.test
+2-32 files

LLVM/project 6b1075cclang/test/CodeGen/AArch64/neon load.c, llvm/test/CodeGen/AMDGPU atomic_optimizations_global_pointer.ll

Merge branch 'users/adams381/cir-callconv-incomplete-record-decl' of https://github.com/llvm/llvm-project into cir-callconv-incomplete-record-decl
DeltaFile
+0-6,246llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
+0-4,877llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
+2,428-0llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-0.ll
+2,426-0llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-1.ll
+1,217-1,125llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+2,240-0clang/test/CodeGen/AArch64/neon/load.c
+8,311-12,2482,226 files not shown
+106,120-52,3252,232 files

LLVM/project a4d5d5fllvm/test/Transforms/SLPVectorizer/X86 splat-gather-operands.ll

[SLP][NFC]Add extra tests for gathered splats, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/219291
DeltaFile
+91-0llvm/test/Transforms/SLPVectorizer/X86/splat-gather-operands.ll
+91-01 files

LLVM/project 5d05e04offload/languages/include/kernel DefineLanguageNames.inc UndefineLanguageNames.inc, offload/languages/kernel/src LanguageRuntime.cpp

add StreamCreateWithFlags
DeltaFile
+26-1offload/languages/kernel/src/LanguageRuntime.cpp
+27-0offload/test/offloading/CUDA/stream_api.cu
+26-0offload/test/offloading/HIP/stream_api.hip
+10-1offload/languages/include/kernel/LanguageRuntime.h
+3-1offload/languages/include/kernel/UndefineLanguageNames.inc
+3-0offload/languages/include/kernel/DefineLanguageNames.inc
+95-36 files

LLVM/project 93bd9f4llvm/lib/Analysis ScalarEvolution.cpp

[SCEV] Remove unreachable visitMulExpr in SCEVCastSinkingRewriter (NFC) (#219279)

SCEVCastSinkingRewriter::visit() returns S unchanged unless S->getType()
is a pointer type. So visitMulExpr can never be entered.
DeltaFile
+0-10llvm/lib/Analysis/ScalarEvolution.cpp
+0-101 files

LLVM/project 18bd92aclang/lib/Driver/ToolChains CommonArgs.cpp, clang/test/Driver cuda-via-liboffload.cu

add PerThreadDefaultStream
DeltaFile
+28-0offload/languages/kernel/CMakeLists.txt
+14-0clang/test/Driver/cuda-via-liboffload.cu
+12-0offload/languages/kernel/src/PerThreadDefaultStream.cpp
+6-3offload/languages/kernel/src/State.cpp
+5-0clang/lib/Driver/ToolChains/CommonArgs.cpp
+1-0offload/languages/kernel/exports
+66-36 files

LLVM/project bd63550offload/languages/kernel/include OffloadErrors.h State.h, offload/languages/kernel/src LanguageRuntime.cpp State.cpp

add interal StreamTy
DeltaFile
+246-89offload/languages/kernel/src/State.cpp
+78-37offload/languages/kernel/include/State.h
+32-26offload/languages/kernel/src/LanguageRuntime.cpp
+31-9offload/test/offloading/CUDA/stream_api.cu
+30-8offload/test/offloading/HIP/stream_api.hip
+38-0offload/languages/kernel/include/OffloadErrors.h
+455-1695 files not shown
+539-20111 files