[LiveDebugVariables] Repair stale SlotIndexes
The analysis keeps its indexes from before the first register allocator
until DBG_VALUEs are emitted, by which point passes in between have
erased some of the instructions they point at. Resolve them at the
start of each allocator run and before emitting.
SlotIndexes can then reclaim the entries of erased instructions without
sparing the ones held here, which would have made generated code depend
on -g. Emitted locations are unchanged, except that intervals resolving
to one position now emit a single DBG_VALUE rather than identical
consecutive ones.
[SlotIndexes] Add queries for stale indexes
An erased instruction leaves its index list entry in place, making the
index indistinguishable from a block boundary entry. Add
isBlockBoundaryIndex() and isStaleIndex() to tell the two apart, and
canonicalizeIndex() to resolve a stale index to the closest preceding
instruction's register slot, or the block start if none survives.
NFC. No caller yet. LiveDebugVariables is next.
[ORC] Share one Mangler across a lookupAndApply group (#224285)
LookupPrepareFn now receives a Mangler that lookupAndApply builds once
from the search order's target triple, rather than each recordAddr /
recordProxy constructing its own per entry.
[OpenACC] Honor precomputed active par dims on a predicate region (#224390)
Example:
```mlir
acc.predicate_region {
memref.store %updated, %shared[] : memref<f64>
} {acc.active_par_dims = #acc<active_par_dims[]>}
```
Code outside a gang-level loop runs on every thread block, so the block
dims are treated as active and never predicated away. That is right for a
redundant computation, but not for an in-place update of memory the whole
launch shares: every block applies it. The attribute above was ignored
here, because only a privatization could state which dims run it
unpredicated.
Fix: honor a precomputed active set on a predicate region too. An empty
set leaves one block and one thread performing the update; listing the
thread dims of the enclosing loops keeps a work-shared update distributing
its iterations. Behavior is unchanged for a region without the attribute.
[LiveDebugVariables] Repair stale SlotIndexes
The analysis keeps its indexes from before the first register allocator
until DBG_VALUEs are emitted, by which point passes in between have
erased some of the instructions they point at. Resolve them at the
start of each allocator run and before emitting.
SlotIndexes can then reclaim the entries of erased instructions without
sparing the ones held here, which would have made generated code depend
on -g. Emitted locations are unchanged, except that intervals resolving
to one position now emit a single DBG_VALUE rather than identical
consecutive ones.
[SlotIndexes] Add queries for stale indexes
An erased instruction leaves its index list entry in place, making the
index indistinguishable from a block boundary entry. Add
isBlockBoundaryIndex() and isStaleIndex() to tell the two apart, and
canonicalizeIndex() to resolve a stale index to the closest preceding
instruction's register slot, or the block start if none survives.
NFC. No caller yet. LiveDebugVariables is next.
[OpenACC] Add a map flag for the attach/detach clause (#224433)
Example:
```fortran
!$acc enter data create(arr)
p => arr(:,1)
!$acc enter data attach(p)
```
In this code, computeDataClauseMapFlags returns no flag for
acc_attach/detach, so the resulting acc.map_info is indistinguishable
from one formed for a create/delete of the target, and the clause itself
is gone by that point.
Fix: give the attach/detach clause its own map flag.
[LiveDebugVariables] Repair stale SlotIndexes
The analysis keeps its indexes from before the first register allocator
until DBG_VALUEs are emitted, by which point passes in between have
erased some of the instructions they point at. Resolve them at the
start of each allocator run and before emitting.
SlotIndexes can then reclaim the entries of erased instructions without
sparing the ones held here, which would have made generated code depend
on -g. Emitted locations are unchanged, except that intervals resolving
to one position now emit a single DBG_VALUE rather than identical
consecutive ones.
[SlotIndexes] Add queries for stale indexes
An erased instruction leaves its index list entry in place, making the
index indistinguishable from a block boundary entry. Add
isBlockBoundaryIndex() and isStaleIndex() to tell the two apart, and
canonicalizeIndex() to resolve a stale index to the closest preceding
instruction's register slot, or the block start if none survives.
NFC. No caller yet. LiveDebugVariables is next.
[libc] Embeddeding API for seek and close (#221880)
This change introduces two new symbols to the embedding API hooks:
__llvm_libc_stdio_seek and __llvm_libc_stdio_close. These are used to
implement fclose, fseek, fseeko, ftell and ftello for baremetal.
The implementation was extracted from #221211.
Authored-by: voltur01
[LLVMABI][AARCH64] Support homogeneous aggregate arguments (#224138)
This adds support for handling homogeneous aggregate arguments in the
AArch64 implementation of the LLVM ABI library.
This required adding a new field to the llvm::abi::Type class to track
the unadjusted alignment of the field. This meant I needed to make
updates to the CIR calling convention lowering pass, but AArch64 isn't
supported in the CIR pass yet, so that part of the change is strictly
NFC at this point.
I'm removing the aarch64-pc-windows-msvc run lines from the
abi-classify-arg-types.cpp test because the new test cases added would
land in NYI diagnostic in isPermittedToBeHomogeneousAggregate(), and
they weren't adding any unique coverage.
Assisted-by: Cursor / various models
[lldb] Read the bool that a scripted thread plan's should_step returns (#215521)
Fixes part (1) of #215189.
`ScriptedThreadPlanPythonInterface::GetRunState()` used
`GetUnsignedIntegerValue()` to read the script's `should_step` return
value. A
Python `bool` arrives as a `StructuredData::Boolean`, so the return
value was
discarded and every scripted thread plan reported `eStateStepping`: a
plan
returning `False` single-stepped exactly like one returning `True`.
The documented contract for `should_step` is a bool
(`lldb/docs/use/tutorials/automating-stepping-logic.md` and
`lldb/examples/python/templates/scripted_thread_plan.py`). Read it as
one; any
other return value is logged and causes the plan to step.
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[ACCCGToGPU] Generate a per row barrier for a predicate region inside threadY loop. (#224461)
When a predicate region is inside a threadY (worker) loop, the generated
barrier should be to synchronize all threadsX (vector lanes) for that
threadY.
Previously, this code would generate a barrier for all inactive
dimensions and that can be problematic if we have no outer gang loop
(hence an inactive blockX dim) and trip count for worker loop isn't
divisible by number of workers. This would lead to a barrier for all
threads within the block leading to a deadlock.
Assisted-by: Codex
[CodeGen] Use SmallSetVectorImpl for getRegAllocationHints
Change TargetRegisterInfo::getRegAllocationHints and all target overrides
to accept SmallSetVectorImpl<MCPhysReg> &Hints instead of SmallVectorImpl,
structurally preventing duplicate register allocation hints while preserving
insertion order and avoiding hardcoding the inline capacity in virtual
method signatures.
Increase AllocationOrder's inline hint storage capacity from 16 to 32
registers to accommodate 32-register classes without heap allocations.
[mlir][xegpu] Remove chunk_size attribute; infer from types (#205122)
The chunk_size attribute on xegpu.load (LoadGatherOp) and xegpu.store
(StoreScatterOp) was redundant with the operand/result types: the XeVM
lowering never read it, VectorToXeGPU already built these ops with an
empty chunk_size, and the op docs noted it could be inferred from the
type.
Remove the attribute and infer the chunk size from the value/result and
mask types via a computed getChunkSize() op method. The mask carries one
element per lane, so the chunk size is the trailing value dimension when
the value has more elements than the mask, and 1 otherwise. This keeps
the existing op.getChunkSize() call sites working while respecting
library layering (no XeGPUUtils dependency from the IR library).
Update the gather/scatter builders, transforms (propagate-layout,
sg-to-lane, wg-to-sg, unroll), VectorToXeGPU lowerings, and lit tests.
Two invalid.mlir cases that were only invalid because a stated
chunk_size contradicted the type are removed; two others are
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Partially revert "RegisterPressure: Remove dead defs correctly" (#224371)
This partially reverts the lane-mask collector change from #222627
(bde5e74309f6). That flipped the dead-def reconciliation in both
RegisterOperandsCollector::collectInstr (register units) and
collectInstrLanes (lane masks). Instead of removing units covered by a
live def from the dead def set, it removed units covered by a dead def
from the live def set.
The flip regressed targets that track subregister liveness, which use
the
lane-mask collector path. When a live sub-register def overlaps a dead
super-register def, the shared register unit is flagged live on one
operand and dead on another. Removing the live def then drops the
genuinely-live unit, so the cached PressureDiff under-counts it and
trips
the EXPENSIVE_CHECKS pressure cross-check in GCNSchedStrategy.
Restore the original lane-mask path while keeping the new behavior on
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[mlir][LowerToLLVM] Pass DataLayoutAnalysis to LowerToLLVMOptions in `ArithToLLVM`, `ControlFlowToLLVM`, and `VectorToLLVM` passes (#206380)
These three conversion passes constructed `LowerToLLVMOptions` without a
`DataLayout`, causing the index bitwidth to be hard-wired to 64 even
when the module declares a narrower index via `dlti.dl_spec`.
```cpp
// Before (all three passes):
LowerToLLVMOptions options(&getContext());
LLVMTypeConverter converter(&getContext(), options);
// After:
const auto &dataLayoutAnalysis = getAnalysis<DataLayoutAnalysis>();
LowerToLLVMOptions options(&getContext(),
dataLayoutAnalysis.getAtOrAbove(getOperation()));
LLVMTypeConverter converter(&getContext(), options, &dataLayoutAnalysis);
```
I used AI to investigate this problem and to write the tests.
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docs: Compute the DataLayout from the triple in the tutorials
Update the exmaple code to avoid using TargetMachine::createDataLayout.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
[bazel][test][libc] Add tags to tests marking full-build compatibility
This allows Bazel to execute tests based on whether they support full-build mode or not, by running:
```
bazel test @llvm-project//libc/... --test_tag_filters=-llvm-libc-overlay-only --@llvm-project//libc:build_mode=full
```
Bazel is already able to tell which tests need to be skipped by using `target_compatible_with`, but using tags allows consumers to configure their CI so no tests get implicitly skipped.
mlir: Avoid using TargetMachine::createDataLayout
This should pass in an ABI name, but there doesn't appear to
be one around in context.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
lldb: Require x86_64 for x86_64-specific NativePDB tests (#224140)
These tests contained x86_64 datalayout and triples, but only
required system-windows. On an aarch64 windows host, %build will
be an incompatible datalayout, so require exactly x86_64 windows
hosts. Alternatively the test could be changed to not have the
datalayout, but I'm not sure if that's correct here.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
