[clang][NFC] Unify `MacroState` `isAmbiguous` and `getModuleInfo` (#197867)
Every call to `MacroState::getModuleInfo`, and `MacroState::isAmbiguous`
are paired in the same function. Rather than doing the same work twice,
just unify them into a single function, `getModuleInfo`, that returns
both pieces of information in a new type `ModuleMacroInfo`.
Unfortunately, `getModuleInfo` and`ModuleMacroInfo` already exist, so
rename them to `getFullModuleInfo` and `FullModuleMacroInfo`,
respectively, since the new type is a subset of the old type. The new
type contains just the pieces consumers care about.
While we're there, use the range constructor of `llvm::DenseSet` instead
of default constructing and calling `insert` in a loop.
[RegAllocFast] Eliminate dead copies (#196056)
github issue: https://github.com/llvm/llvm-project/issues/168201
This patch extends copy elimination in **RegAllocFast** to catch an
additional class of redundant copies. Previously, only identity copies
(where source and destination registers are the same) were marked for
removal.
Now, we check whether the current instruction is dead and remove it if
it is.
The change:
- Updates the copy-elimination condition to include dead destination
operands.
- Improves debug output to be more generic.
This reduces unnecessary instructions and can lead to slightly better
codegen by eliminating dead copies earlier in the fast register
allocation pass.
[DAG] SimplifyMultipleUseDemandedBits - use isIdentityElement to detect identity / fall through operands (#197952)
Now that isIdentityElement uses computeKnownBits we don't have to handle
this locally, and can handle all binops (inc smax/smin/umax/umin etc.)
at the same time
[IA][RISCV] Support gap mask for loads that are de-interleaved through intrinsics (#197062)
In the context of (de)interleaved loads and stores, a gap mask is a mask
that effectively skips the entire component / field. Starting from
#151612 , the InterleavedAccessPass gained support to recognize masks of
this kind and pass it to the TLI hook. RISC-V originally only supported
gap mask on fixed vectors, this patch adds support for recognizing gap
masks on loads that are de-interleaved through the
`llvm.vector.deinterleaveN` intrinsics, with both scalable vectors and
fixed vectors.
[AggressiveInstCombine] Loosen some conditions in the popcount pattern (#197536)
This PR refines and loosens some condition regarding the last AND mask
in the popcount pattern introduced by #180917 .
More specifically, this AND mask only needs to fulfill two conditions:
1. All ones for the lower NumLenBits-bits, where NumLenBits is the
number of bits needed to represent the size of the integer
2. Zeros from bit 8 and onward
Rest of the bits can have arbitrary values.
The compute known bits infrastructure is supposed to reason about this
but it was depth-limited in this particular case.
SystemZ: Remove always-true conditional (#197729)
About 20 lines above, the DSA64Bit is unconditionally set, so switching
on it later is not needed. Instead, we can print that bit
unconditionally.
Resolves #170125
[Hexagon] Add XRay custom and typed event support (#191749)
Add support for XRay custom events (llvm.xray.customevent) and typed
events (llvm.xray.typedevent) for Hexagon.
LLVM:
* Add Hexagon to the architecture gate in SelectionDAGBuilder for
xray_customevent and xray_typedevent intrinsic lowering
* Implement EmitInstrWithCustomInserter for PATCHABLE_EVENT_CALL and
PATCHABLE_TYPED_EVENT_CALL pseudo instructions
* Implement LowerPATCHABLE_EVENT_CALL in HexagonAsmPrinter that emits
inline sleds with jump-over, allocframe/deallocframe for LR:FP save,
argument register save/restore, and call to the event handler
* Add event pseudo dispatch in HexagonMCInstLower
* Prevent event pseudos from being packetized (solo instructions)
compiler-rt:
* Implement patchCustomEvent and patchTypedEvent in xray_hexagon.cpp to
patch the sled jump to nop (enable) or back (disable)
* Add __xray_CustomEvent and __xray_TypedEvent trampolines in the
Hexagon XRay trampoline assembly
[clang-sycl-linker] Remove dead and unnecessary check for no symbols image (#197596)
The `if (SI.Symbols.empty()) continue;` guard in `runSYCLLink` was
unreachable: `collectEntryPoints` always calls
`llvm::offloading::sycl::writeSymbolTable`, which emits at least a
4-byte `SymbolTableHeader` (`Count=0`) even when the input has no entry
points.
The check could never fire and was misleading suggesting that modules
without kernels would be dropped.
I checked other similar tools and did not find logic to filter out
images, if there are no entry points. This doesn't look like
responsibility of clang-sycl-linker.
If this scenario is required, we can consider adding it later with a
proper check.
---------
Co-authored-by: Alexey Bader <alexey.bader at intel.com>
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
This removes one of the uses of getTargetExtractSubreg, that creates a
Machine Node during DAG lowering. We instead use a scalar_to_vector to
convert to a vector and let the extract element legalize to a legal
type.
[VPlan] Make VPWidenLoad(EVL)Recipe VPSingleDefs (NFC). (#197496)
This updates VPWidenMemoryRecipe to no longer inherit directly from
VPRecipeBase. Instead VPWidenMemoryRecipe is turned into a mixin, like
VPIRMetadata and VPPhiAccessors. This in turn allows updating
VPWidenLoad(EVL)Recipe to inherit directly from VPSingleDefRecipe. This
brings them in line with all other recipes defining a single VPValue.
Depends on https://github.com/llvm/llvm-project/pull/197494
PR: https://github.com/llvm/llvm-project/pull/197496
[lldb] Skip new tests in TestLinuxCore on Windows and non-x86 targets (#197887)
This patch must fix broken tests after #197341 on buildbots
lldb-remote-linux-win, lldb-x86_64-win and lldb-aarch64-windows.
[lldb] Expose the process arguments in SBProcessInfo (#197719)
Add GetNumArguments() and GetArgumentAtIndex() to SBProcessInfo. Add a
convienence property `arguments` in the python api.
lldb-dap uses this to show more information to the user when picking a
process.
Fixes: #197509
[clang][deps] Move logic out of the PP callback (#197270)
This PR moves the main scanner logic from
`ModuleDepCollectorPP::EndOfMainFile()` to the new
`ModuleDepCollector::run()`. In a follow-up PR, this will allow invoking
the main logic with different `DependencyConsumer` objects and reusing
the `ModuleDepCollector` state, skipping some work on subsequent calls.
[AMDGPU] Implement -amdgpu-spill-cfi-saved-regs
These spills need special CFI anyway, so implementing them directly
where CFI is emitted avoids the need to invent a mechanism to track them
from ISel.
Change-Id: If4f34abb3a8e0e46b859a7c74ade21eff58c4047
Co-authored-by: Scott Linder scott.linder at amd.com
Co-authored-by: Venkata Ramanaiah Nalamothu VenkataRamanaiah.Nalamothu at amd.com
[AMDGPU] Implement CFI for CSR spills
Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.
Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.
Change-Id: I9b09646abd2ac4e56eddf5e9aeca1a5bebbd43dd
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Implement CFI for non-kernel functions
This does not implement CSR spills other than those AMDGPU handles
during PEI. The remaining spills are handled in a subsequent patch.
Change-Id: I5e3a9a62cf9189245011a82a129790d813d49373
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[AMDGPU] Emit entry function Dwarf CFI
Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.
Change-Id: I21580f6a24f4869ba32939c9c6332506032cc654
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
[Clang] Default to async unwind tables for amdgcn
To avoid codegen changes when enabling debug-info (see
https://bugs.llvm.org/show_bug.cgi?id=37240) we want to
enable unwind tables by default.
There is some pessimization in post-prologepilog scheduling, and a
general solution to the problem of CFI_INSTRUCTION-as-scheduling-barrier
should be explored.
Change-Id: I83625875966928c7c4411cd7b95174dc58bda25a
[MIR] Error on signed integer in getUnsigned
Previously we effectively took the absolute value of the APSInt, instead
diagnose the unexpected negative value.
Change-Id: I4efe961e7b29fdf1d5f97df12f8139aac12c9219
[MC][Dwarf] Add custom CFI pseudo-ops for use in AMDGPU
While these can be represented with .cfi_escape, using these pseudo-cfi
instructions makes .s/.mir files more readable, and it is necessary to
support updating registers in CFI instructions (something that the
AMDGPU backend requires).
Change-Id: I763d0cabe5990394670281d4afb5a170981e55d0
[DAG] isIdentityElement - use KnownBits instead of constant splat to match identity constants (#197455)
This works better with the DemandedElts mask to match hidden identity
constants (zero in particular.....).
I need this for the ongoing work to improve VECREDUCE simplification to
match identity elements (legalisation pads with identity elements) in an
expanded reduction shuffle chain.
[LoopInterchange] Handle PHI nodes in inner loop preheader (#196691)
Fixes #196242
LoopInterchange crashes when the inner loop preheader contains a
single-incoming PHI node.
This fix folds single-incoming PHI nodes by replacing them with their
incoming value and then erasing the PHI nodes.
Added a regression test under llvm/test/Transforms/LoopInterchange/
using the reproducer from issue #196242.
