LLVM/project e1ab1b1 — llvm/lib/Target/X86 X86ISelLowering.cpp, llvm/test/CodeGen/X86 avx512fp16-combine-fmsubadd.ll avx512fp16-combine-fmsubadd-fadd.ll

by Rohan Shenoy via GitHub on ⎇
[X86] Fold FMADDSUB into VFMULC for fp16 complex multiply (#227698)

We fold fmaddsub using isCFMulFromFMAddSub (formerly isCFMulFromFMSUBADD) into vfmulc.
DeltaFile
+54-0llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd-fadd.ll
+51-0llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
+15-11llvm/lib/Target/X86/X86ISelLowering.cpp
+120-113 files

LLVM/project 5b2879a — llvm/lib/Target/AMDGPU AMDGPUAtomicOptimizer.cpp, llvm/test/CodeGen/AMDGPU local-atomicrmw-fadd.ll atomic_optimizations_local_pointer.ll

by Dmitry Sidorov via GitHub on ⎇
[AMDGPU] Skip the iterative atomic scan on native LDS atomics (#227222)

The iterative scan runs a serial loop with one iteration per active lane. For an LDS atomic that the target executes natively, this costs more than the hardware serialization it replaces. Leave such atomics alone when the value is divergent.
DeltaFile
+733-5,435llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+68-479llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+7-0llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
+808-5,9143 files

LLVM/project 123ad4d — llvm/lib/IR Instructions.cpp, llvm/test/Transforms/InstCombine byte-cast-pairs.ll

by Pedro Lobo on ⎇
[IR] Don't fold bitcast pairs through bytes into invalid casts

A pair of bitcasts through a byte can change whether a value is a
pointer, or its address space. Merging such a pair produced an invalid
bitcast and crashed InstCombine, InstSimplify, constant folding and the
IR parser. Give bitcast pairs their own case, and only fold them if
neither end is a pointer, or both are pointers in the same address
space.

Also keep inttoptr and ptrtoint/ptrtoaddr separate from a pointer-byte
bitcast. These pairs used to hit an assertion.

Fixes #207532.
DeltaFile
+107-0llvm/test/Transforms/InstCombine/byte-cast-pairs.ll
+26-0llvm/test/Transforms/InstSimplify/byte-cast-pairs.ll
+20-1llvm/lib/IR/Instructions.cpp
+153-13 files

LLVM/project 795e750 — llvm/lib/Target/PowerPC/GISel PPCInstructionSelector.cpp

by Matt Arsenault via GitHub on ⎇
PowerPC/GlobalISel: Stop setting kill flags on selected instructions (#229016)

There is no point in maintaining these before register allocation
anymore.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+18-18llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+18-181 files

LLVM/project 73ad673 — llvm/lib/Target/VE VEISelLowering.cpp

by Matt Arsenault via GitHub on ⎇
VE: Stop setting kill flags on virtual registers before FinalizeISel (#229012)

There is no point in maintaining kill flags before register allocation
anymore.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+30-30llvm/lib/Target/VE/VEISelLowering.cpp
+30-301 files

LLVM/project 07cd029 — llvm/lib/Transforms/Vectorize VPlanTransforms.cpp

by Benjamin Maxwell via GitHub on ⎇
[LV] Make partial-reduction naming consistent (NFC) (#222377)

The partial-reduction code used "Chain" to refer to two different
concepts:

1. A `VPPartialReductionChain`, which is a collection of recipes that
   form a partial reduction.
2. A list of `VPPartialReductionChain` objects that forms a chained
   reduction.

This patch renames `VPPartialReductionChain` to
`PartialReductionDescriptor` and updates the terminology as follows: a
`Link` is a single `PartialReductionDescriptor`, a `Chain` is a list of
links, and `Chains` refers to a collection of chains.
DeltaFile
+60-60llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+60-601 files

LLVM/project f96e385 — llvm/lib/Target/VE VEInstrInfo.cpp, llvm/test/CodeGen/VE/Scalar builtin_sjlj.ll

by Matt Arsenault via GitHub on ⎇
VE: Compute live-ins after splitting for EXTEND_STACK expansion (#221553)

expandExtendStackPseudo splits its block but left the new blocks without
live-in lists, so their uses of registers live across the split are rejected by 
-verify-machineinstrs.

Co-authored-by: Claude (Claude-Opus-4.8)
DeltaFile
+5-0llvm/lib/Target/VE/VEInstrInfo.cpp
+2-2llvm/test/CodeGen/VE/Scalar/builtin_sjlj.ll
+7-22 files

LLVM/project 542f3e6 — libc/docs CMakeLists.txt, libc/docs/headers index.rst

by Prashanth via GitHub on ⎇
[libc][docs] Add sys/msg.h to the header status docs (#227619)

Add a header status page for `sys/msg.h`
https://github.com/llvm/llvm-project/issues/122006
DeltaFile
+13-0libc/utils/docgen/sys/msg.yaml
+1-0libc/docs/headers/index.rst
+1-0libc/docs/CMakeLists.txt
+15-03 files

LLVM/project fb89552 — llvm/docs/GlobalISel IRTranslator.md, llvm/lib/CodeGen/GlobalISel IRTranslator.cpp

by Pedro Lobo via GitHub on ⎇
[GlobalISel] Translate byte to ptr bitcasts to `G_INTTOPTR`/`G_PTRTOINT` (#226541)

Reverts #209557 and fixes the underlying crash it worked around.

A `bitcast` from a byte type to a pointer is valid IR and preserves
pointer provenance. #209557 replaced it with a `bitcast` to `i64`
followed by `inttoptr`, which drops provenance. That's unsound.

The crash came from the IRTranslator. It lowered scalar byte to pointer
bitcasts to `G_INTTOPTR` and `G_PTRTOINT`, but left vector forms as
`G_BITCAST`. The MachineVerifier rejects that when the pointer side is a
scalar pointer. We now go through an integer matching the pointer size,
and add a `G_BITCAST` first when the shapes differ:
```diff
 %r = bitcast <2 x b32> %v to ptr

-%r:_(p0) = G_BITCAST %v(<2 x i32>)   ; bitcast cannot convert between pointers and other types
+%i:_(i64) = G_BITCAST %v(<2 x i32>)
+%r:_(p0) = G_INTTOPTR %i(i64)
```
DeltaFile
+137-3llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
+16-10llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+0-18llvm/unittests/IR/IRBuilderTest.cpp
+5-10llvm/test/CodeGen/AMDGPU/promote-alloca-byte-ptr-cast.ll
+6-4llvm/docs/GlobalISel/IRTranslator.md
+2-6llvm/lib/IR/IRBuilder.cpp
+166-516 files

LLVM/project 98606f5 — llvm/test/Transforms/LoopVectorize/VPlan compress-idioms.ll

by Benjamin Maxwell on ⎇
Rebase fixups
DeltaFile
+3-3llvm/test/Transforms/LoopVectorize/VPlan/compress-idioms.ll
+3-31 files

LLVM/project cc802a8 — llvm/lib/Target/X86 X86FastISel.cpp X86ISelLowering.cpp

by Matt Arsenault on ⎇
X86: Stop setting kill flags on virtual registers before FinalizeISel

There is no point in maintaining kill flags before register allocation
anymore.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+6-6llvm/lib/Target/X86/X86ISelLowering.cpp
+3-3llvm/lib/Target/X86/X86FastISel.cpp
+9-92 files

LLVM/project 5451653 — llvm/lib/Transforms/Utils LoopUtils.cpp, llvm/lib/Transforms/Vectorize LoopVectorizationLegality.cpp LoopVectorize.cpp

by Benjamin Maxwell on ⎇
Fixups
DeltaFile
+67-0llvm/test/Transforms/LoopVectorize/compress-idioms-negative-tests.ll
+10-5llvm/lib/Transforms/Utils/LoopUtils.cpp
+6-8llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+9-5llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+1-10llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+7-4llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+100-321 files not shown
+101-337 files

LLVM/project c731ddd — llvm/include/llvm/Transforms/Utils LoopUtils.h

by Benjamin Maxwell on ⎇
Add LLVM_ABI marker
DeltaFile
+3-4llvm/include/llvm/Transforms/Utils/LoopUtils.h
+3-41 files

LLVM/project bab95c4 — llvm/lib/Transforms/Vectorize LoopVectorize.cpp

by Benjamin Maxwell on ⎇
Rebase fixups
DeltaFile
+1-1llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+1-11 files

LLVM/project b404eae — llvm/lib/Transforms/Utils LoopUtils.cpp

by Benjamin Maxwell on ⎇
Rebase fixups
DeltaFile
+1-1llvm/lib/Transforms/Utils/LoopUtils.cpp
+1-11 files

LLVM/project 845cffd — llvm/lib/Transforms/Vectorize LoopVectorizationPlanner.h LoopVectorizationPlanner.cpp

by Benjamin Maxwell on ⎇
Always pass a vector type to TTI.isLegalMaskedCompressStore/ExpandLoad
DeltaFile
+4-4llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+4-3llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+1-1llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+9-83 files

LLVM/project f42ac98 — llvm/test/Transforms/LoopVectorize/RISCV compress-idioms.ll, llvm/test/Transforms/LoopVectorize/X86 compress-idioms.ll

by Benjamin Maxwell on ⎇
Rebase tests
DeltaFile
+45-29llvm/test/Transforms/LoopVectorize/RISCV/compress-idioms.ll
+12-12llvm/test/Transforms/LoopVectorize/X86/compress-idioms.ll
+57-412 files

LLVM/project 0596847 — llvm/test/Transforms/LoopVectorize compress-store-vec-epilogue.ll compress-idioms.ll, llvm/test/Transforms/LoopVectorize/AArch64 compress-idioms.ll

by Benjamin Maxwell on ⎇
Update checks
DeltaFile
+333-418llvm/test/Transforms/LoopVectorize/compress-idioms.ll
+132-53llvm/test/Transforms/LoopVectorize/X86/compress-idioms.ll
+59-43llvm/test/Transforms/LoopVectorize/AArch64/compress-idioms.ll
+54-4llvm/test/Transforms/LoopVectorize/compress-store-vec-epilogue.ll
+578-5184 files

LLVM/project bb491b0 — llvm/include/llvm/Transforms/Vectorize LoopVectorizationLegality.h, llvm/lib/Transforms/Utils LoopUtils.cpp

by Sergey Kachkov via Benjamin Maxwell on ⎇
[LoopVectorize] Support vectorization of compressing patterns in VPlan

RFC link: https://discourse.llvm.org/t/rfc-loop-vectorization-of-compress-store-expand-load-patterns/86442

This adds loop vectorizer support for "compressing" patterns,
for example:

```
int dst_idx = 0;
for (int i = 0; i < n; i++) {
  if (cond[i])
    dst[dst_idx++] = src[i];
}
```

Can be vectorized with a `llvm.masked.compressstore` as:

```
int dst_idx = 0;

    [74 lines not shown]
DeltaFile
+153-0llvm/test/Transforms/LoopVectorize/VPlan/compress-idioms.ll
+94-12llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+91-0llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+75-0llvm/lib/Transforms/Utils/LoopUtils.cpp
+63-9llvm/lib/Transforms/Vectorize/VPlan.h
+55-1llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+531-2216 files not shown
+738-3522 files

LLVM/project 77fbd70 — llvm/lib/Target/AArch64 AArch64ISelLowering.cpp AArch64FastISel.cpp

by Matt Arsenault on ⎇
AArch64: Stop setting kill flags on virtual registers before FinalizeISel

There is no point in maintaining kill flags before register allocation
anymore.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+10-10llvm/lib/Target/AArch64/AArch64FastISel.cpp
+2-2llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+12-122 files

LLVM/project 8728f9e — llvm/lib/Target/ARM ARMFastISel.cpp ARMISelLowering.cpp

by Matt Arsenault on ⎇
ARM: Stop setting kill flags on virtual registers before FinalizeISel

There is no point in maintaining kill flags before register allocation
anymore.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+31-31llvm/lib/Target/ARM/ARMISelLowering.cpp
+4-5llvm/lib/Target/ARM/ARMFastISel.cpp
+35-362 files

LLVM/project 1670fa6 — libc/docs CMakeLists.txt, libc/docs/headers index.rst

by Prashanth via GitHub on ⎇
[libc][docs] Add syslog.h to the header status docs (#226982)

Add a header status page for `syslog.h` #122006
DeltaFile
+75-0libc/utils/docgen/syslog.yaml
+1-0libc/docs/headers/index.rst
+1-0libc/docs/CMakeLists.txt
+77-03 files

LLVM/project 6876386 — llvm/lib/Target/LoongArch LoongArchISelLowering.cpp

by Matt Arsenault on ⎇
LoongArch: Stop setting kill flags on virtual registers before FinalizeISel

These is no point to maintaining these before register allocation anymore.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+7-7llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+7-71 files

LLVM/project 4aa96eb — llvm/lib/Target/Mips MipsISelLowering.cpp MipsFastISel.cpp

by Matt Arsenault on ⎇
Mips: Stop setting kill flags on virtual registers before FinalizeISel

There is no point in maintaining these before register allocation anymore.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+3-3llvm/lib/Target/Mips/MipsISelLowering.cpp
+3-3llvm/lib/Target/Mips/MipsFastISel.cpp
+6-62 files

LLVM/project e1cdff9 — llvm/lib/Target/AMDGPU SIISelLowering.cpp, llvm/test/CodeGen/AMDGPU idot4s.ll idot4-test.ll

by Dmitry Sidorov via GitHub on ⎇
[AMDGPU] Extract byte lanes of a split vector from the 32-bit source

After a <4 x i8> is split into i16 halves, a byte lane is extended
from an i16 shift of a truncate. Rewrite it on the 32-bit source as an
and of srl or a sign_extend_inreg of srl, which select to a single bit
field extract.

Uniform zero and any extends are left alone, their i16 shift is already
promoted to i32.
DeltaFile
+154-227llvm/test/CodeGen/AMDGPU/v4i8-byte-lane-ext.ll
+108-134llvm/test/CodeGen/AMDGPU/idot4u.ll
+79-87llvm/test/CodeGen/AMDGPU/min.ll
+47-62llvm/test/CodeGen/AMDGPU/idot4-test.ll
+33-48llvm/test/CodeGen/AMDGPU/idot4s.ll
+64-0llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+485-5584 files not shown
+515-59210 files

LLVM/project 3105aff — llvm/test/CodeGen/AMDGPU v4i8-byte-lane-ext.ll

by Dmitry Sidorov via GitHub on ⎇
[AMDGPU] Precommit test for byte lane extension after vector split
DeltaFile
+747-0llvm/test/CodeGen/AMDGPU/v4i8-byte-lane-ext.ll
+747-01 files

LLVM/project 8ab3862 — llvm/lib/Target/PowerPC/GISel PPCInstructionSelector.cpp

by Matt Arsenault on ⎇
PowerPC/GlobalISel: Stop setting kill flags on selected instructions

There is no point in maintaining these before register allocation
anymore.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+18-18llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+18-181 files

LLVM/project 12888ae — llvm/lib/Target/RISCV RISCVISelLowering.cpp

by Matt Arsenault on ⎇
RISCV: Stop setting kill flags on virtual registers before FinalizeISel

Kill flags have no remaining use before register allocation and are
stripped by LiveIntervals.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
DeltaFile
+2-2llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+2-21 files

LLVM/project 0283f49 — llvm/lib/Analysis InstructionSimplify.cpp, llvm/lib/Transforms/InstCombine InstCombineCalls.cpp

by Simon Pilgrim via GitHub on ⎇
[InstCombine] Ensure i1 smulh(x,1) fold to zero (#229004)

Alive2: https://alive2.llvm.org/ce/z/ZEDAx8
DeltaFile
+16-0llvm/test/Transforms/InstCombine/umulh.ll
+16-0llvm/test/Transforms/InstCombine/smulh.ll
+4-4llvm/lib/Analysis/InstructionSimplify.cpp
+1-1llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+37-54 files

LLVM/project 0859c3c — mlir/lib/Conversion/TosaToLinalg TosaToLinalgNamed.cpp, mlir/test/Conversion/TosaToLinalg tosa-to-linalg-named.mlir

by Jack Frankland via GitHub on ⎇
[mlir][tosa] Preserve all-NaN max-pool windows (#225744)

Initialize IGNORE-mode floating-point max pooling with NaN and select
the first finite input. This keeps an all-NaN window NaN instead of
returning the lowest finite value.

Assited-by: Codex
DeltaFile
+82-0mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
+23-11mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
+105-112 files